1832 files changed, 328607 insertions, 1 deletions

diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_asd.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_asd.bin
index 186cb5b4..2c4cda74 100644
--- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_asd.bin
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_asd.bin
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_ce.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_ce.bin
index 015bb206..5e915181 100644
--- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_ce.bin
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_ce.bin
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_me.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_me.bin
index b2e0ec2d..3abf70a0 100644
--- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_me.bin
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_me.bin
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec.bin
index 5b68507f..738dc4c5 100644
--- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec.bin
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec.bin
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec2.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec2.bin
index 5b68507f..738dc4c5 100644
--- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec2.bin
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_mec2.bin
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_pfp.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_pfp.bin
index 17597231..77caf229 100644
--- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_pfp.bin
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_pfp.bin
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_sdma.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_sdma.bin
index 80e4fb65..139b9553 100644
--- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_sdma.bin
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-r1000/raven2_sdma.bin
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-v1000/raven_asd.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-v1000/raven_asd.bin
index 7c4e7c09..e9a3d848 100644
--- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-v1000/raven_asd.bin
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-v1000/raven_asd.bin
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-v1000/raven_dmcu.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-v1000/raven_dmcu.bin
new file mode 100644
index 00000000..0a5ee4d5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-v1000/raven_dmcu.bin
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-v1000/raven_kicker_rlc.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-v1000/raven_kicker_rlc.bin
new file mode 100644
index 00000000..51fc3699
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-v1000/raven_kicker_rlc.bin
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-v1000/raven_rlc.bin b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-v1000/raven_rlc.bin
index 9f0e8810..7df6be93 100644
--- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-v1000/raven_rlc.bin
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware-v1000/raven_rlc.bin
diff --git a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware.bb b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware.bb
index 161c4b14..66b0299c 100644
--- a/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware.bb
+++ b/meta-amd-bsp/recipes-kernel/linux-firmware/amdgpu-firmware.bb
@@ -20,7 +20,8 @@ SRC_URI_r1000 = "file://raven2_asd.bin \
 SRC_URI_v1000 = "file://raven_me.bin file://raven_pfp.bin file://raven_vcn.bin \
 		 file://raven_ce.bin file://raven_mec2.bin file://raven_rlc.bin \
 		 file://raven_gpu_info.bin file://raven_mec.bin file://raven_sdma.bin \
-		 file://raven_asd.bin file://LICENSE \
+		 file://raven_asd.bin file://raven_dmcu.bin file://raven_kicker_rlc.bin \
+		 file://LICENSE \
 "
 
 LIC_FILES_CHKSUM = "file://LICENSE;md5=07b0c31777bd686d8e1609c6940b5e74"
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/afalg.cfg b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/afalg.cfg
new file mode 100644
index 00000000..4f49b92b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/afalg.cfg
@@ -0,0 +1,44 @@
+#
+# General setup
+#
+CONFIG_AUDIT=y
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_AUDITSYSCALL=y
+CONFIG_AUDIT_WATCH=y
+CONFIG_AUDIT_TREE=y
+
+CONFIG_INTEGRITY_AUDIT=y
+
+#
+# Crypto core or helper
+#
+
+CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_MCRYPTD=m
+
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_ECHAINIV=m
+
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_DES3_EDE_X86_64=m
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_HASH=y
+CONFIG_CRYPTO_DRBG_CTR=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_USER_API=m
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_USER_API_RNG=m
+CONFIG_CRYPTO_USER_API_AEAD=m
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/amd-ccp.cfg b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/amd-ccp.cfg
new file mode 100644
index 00000000..cc9d9e10
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/amd-ccp.cfg
@@ -0,0 +1,27 @@
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+#
+# DMA Devices
+#
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DMA_ACPI=y
+# CONFIG_INTEL_IDMA64 is not set
+# CONFIG_INTEL_IOATDMA is not set
+# CONFIG_QCOM_HIDMA_MGMT is not set
+# CONFIG_QCOM_HIDMA is not set
+CONFIG_DW_DMAC_CORE=y
+# CONFIG_DW_DMAC is not set
+# CONFIG_DW_DMAC_PCI is not set
+CONFIG_HSU_DMA=y
+#
+# DMA Clients
+#
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+CONFIG_CRYPTO_DEV_CCP=y
+CONFIG_CRYPTO_DEV_CCP_DD=y
+CONFIG_CRYPTO_DEV_CCP_CRYPTO=y
+CONFIG_CRYPTO_DEV_SP_CCP=y
+CONFIG_CRYPTO_DEV_SP_PSP=y
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/amd-emmc-patches.scc b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/amd-emmc-patches.scc
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/amd-emmc-patches.scc
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/amd-xgbe-patches.scc b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/amd-xgbe-patches.scc
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/amd-xgbe-patches.scc
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/amd-xgbe.cfg b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/amd-xgbe.cfg
new file mode 100644
index 00000000..463ed1e8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/amd-xgbe.cfg
@@ -0,0 +1,51 @@
+CONFIG_MDIO=y
+CONFIG_AMD_XGBE=y
+CONFIG_AMD_XGBE_HAVE_ECC=y
+CONFIG_PHYLIB=y
+CONFIG_MDIO_GPIO=y
+
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_AX88179_178A=y
+CONFIG_USB_NET_CDCETHER=y
+# CONFIG_USB_NET_CDC_EEM is not set
+CONFIG_USB_NET_CDC_NCM=y
+# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set
+# CONFIG_USB_NET_CDC_MBIM is not set
+# CONFIG_USB_NET_DM9601 is not set
+# CONFIG_USB_NET_SR9700 is not set
+# CONFIG_USB_NET_SR9800 is not set
+# CONFIG_USB_NET_SMSC75XX is not set
+# CONFIG_USB_NET_SMSC95XX is not set
+# CONFIG_USB_NET_GL620A is not set
+CONFIG_USB_NET_NET1080=y
+# CONFIG_USB_NET_PLUSB is not set
+# CONFIG_USB_NET_MCS7830 is not set
+# CONFIG_USB_NET_RNDIS_HOST is not set
+CONFIG_USB_NET_CDC_SUBSET_ENABLE=y
+CONFIG_USB_NET_CDC_SUBSET=y
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=y
+CONFIG_USB_NET_CX82310_ETH=y
+# CONFIG_USB_NET_KALMIA is not set
+# CONFIG_USB_NET_QMI_WWAN is not set
+# CONFIG_USB_HSO is not set
+# CONFIG_USB_NET_INT51X1 is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_USB_SIERRA_NET is not set
+# CONFIG_USB_VL600 is not set
+# CONFIG_USB_NET_CH9200 is not set
+
+CONFIG_VFIO_PCI=y
+
+CONFIG_X86_X2APIC=y
+CONFIG_X86_NUMACHIP=y
+CONFIG_INET_TCP_DIAG=m
+CONFIG_INET_UDP_DIAG=m
+CONFIG_INET_DIAG=m
+CONFIG_NETLABEL=y
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/disable-graphics.cfg b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/disable-graphics.cfg
new file mode 100644
index 00000000..a33d4410
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/disable-graphics.cfg
@@ -0,0 +1,5 @@
+# CONFIG_FB is not set
+# CONFIG_DRM is not set
+# CONFIG_AGP is not set
+# CONFIG_VGA_SWITCHEROO is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/e3000-extra-config.cfg b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/e3000-extra-config.cfg
new file mode 100644
index 00000000..8e25b3f6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/e3000-extra-config.cfg
@@ -0,0 +1,325 @@
+CONFIG_PERF_EVENTS_INTEL_UNCORE=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_USELIB=y
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
+CONFIG_SRCU=y
+# CONFIG_TASKS_RCU is not set
+CONFIG_BUILD_BIN2C=y
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+CONFIG_PAGE_COUNTER=y
+CONFIG_BPF=y
+CONFIG_MULTIUSER=y
+CONFIG_SGETMASK_SYSCALL=y
+CONFIG_SYSFS_SYSCALL=y
+# CONFIG_BPF_SYSCALL is not set
+CONFIG_ADVISE_SYSCALLS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_ARCH_HUGE_VMAP=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+# CONFIG_MODULE_COMPRESS is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_X86_FEATURE_NAMES=y
+# CONFIG_X86_GOLDFISH is not set
+CONFIG_IOSF_MBI=m
+# CONFIG_IOSF_MBI_DEBUG is not set
+CONFIG_X86_VSYSCALL_EMULATION=y
+CONFIG_X86_DIRECT_GBPAGES=y
+CONFIG_MEMORY_BALLOON=y
+# CONFIG_ZSWAP is not set
+# CONFIG_ZPOOL is not set
+# CONFIG_ZBUD is not set
+CONFIG_GENERIC_EARLY_IOREMAP=y
+# CONFIG_X86_PMEM_LEGACY is not set
+# CONFIG_X86_INTEL_MPX is not set
+# CONFIG_EFI_MIXED is not set
+CONFIG_HAVE_LIVEPATCH=y
+# CONFIG_LIVEPATCH is not set
+CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
+CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
+CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
+CONFIG_ACPI_HOTPLUG_IOAPIC=y
+# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set
+CONFIG_HAVE_ACPI_APEI=y
+CONFIG_HAVE_ACPI_APEI_NMI=y
+# CONFIG_PMIC_OPREGION is not set
+CONFIG_PMC_ATOM=y
+CONFIG_NET_UDP_TUNNEL=m
+# CONFIG_NET_FOU is not set
+# CONFIG_NET_FOU_IP_TUNNELS is not set
+# CONFIG_GENEVE is not set
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_BRIDGE_NETFILTER=m
+CONFIG_NF_NAT_REDIRECT=m
+# CONFIG_NETFILTER_XT_NAT is not set
+# CONFIG_NF_LOG_ARP is not set
+# CONFIG_NF_LOG_IPV4 is not set
+CONFIG_NF_REJECT_IPV4=m
+CONFIG_NF_NAT_IPV4=m
+# CONFIG_NF_NAT_MASQUERADE_IPV4 is not set
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+# CONFIG_IP_NF_NAT is not set
+# CONFIG_NF_REJECT_IPV6 is not set
+# CONFIG_NF_LOG_IPV6 is not set
+CONFIG_TIPC_MEDIA_UDP=y
+# CONFIG_NET_ACT_VLAN is not set
+# CONFIG_NET_ACT_BPF is not set
+# CONFIG_NET_ACT_CONNMARK is not set
+# CONFIG_MPLS is not set
+# CONFIG_NET_SWITCHDEV is not set
+CONFIG_BT_BREDR=y
+CONFIG_BT_LE=y
+# CONFIG_BT_SELFTEST is not set
+CONFIG_BT_DEBUGFS=y
+CONFIG_BT_INTEL=m
+CONFIG_BT_BCM=m
+CONFIG_BT_HCIBTUSB_BCM=y
+# CONFIG_BT_HCIUART_INTEL is not set
+# CONFIG_BT_HCIUART_BCM is not set
+# CONFIG_MAC80211_RC_MINSTREL_VHT is not set
+CONFIG_UEVENT_HELPER=y
+# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
+CONFIG_ALLOW_DEV_COREDUMP=y
+# CONFIG_BLK_DEV_PMEM is not set
+# CONFIG_INTEL_MEI_TXE is not set
+# CONFIG_INTEL_MIC_BUS is not set
+# CONFIG_ECHO is not set
+# CONFIG_CXL_BASE is not set
+# CONFIG_SCSI_MQ_DEFAULT is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_WD719X is not set
+# CONFIG_DM_MQ_DEFAULT is not set
+# CONFIG_DM_ERA is not set
+# CONFIG_DM_LOG_WRITES is not set
+# CONFIG_IPVLAN is not set
+# CONFIG_NET_VENDOR_AGERE is not set
+# CONFIG_ET131X is not set
+# CONFIG_ALTERA_TSE is not set
+# CONFIG_BCMGENET is not set
+# CONFIG_CX_ECAT is not set
+# CONFIG_FM10K is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_SXGBE_ETH is not set
+# CONFIG_TI_CPSW_ALE is not set
+# CONFIG_BCM7XXX_PHY is not set
+# CONFIG_MDIO_BCM_UNIMAC is not set
+CONFIG_USB_NET_DRIVERS=y
+# CONFIG_ATH9K_DYNACK is not set
+# CONFIG_ATH9K_CHANNEL_CONTEXT is not set
+CONFIG_ATH9K_PCOEM=y
+CONFIG_BRCMFMAC_PROTO_BCDC=y
+# CONFIG_BRCMFMAC_PCIE is not set
+CONFIG_IWLWIFI_LEDS=y
+# CONFIG_RTL8723BE is not set
+# CONFIG_RTL8192EE is not set
+# CONFIG_RTL8821AE is not set
+# CONFIG_RSI_91X is not set
+# CONFIG_MOUSE_PS2_FOCALTECH is not set
+# CONFIG_MOUSE_ELAN_I2C is not set
+# CONFIG_TABLET_SERIAL_WACOM4 is not set
+# CONFIG_TOUCHSCREEN_GOODIX is not set
+# CONFIG_TOUCHSCREEN_ELAN is not set
+# CONFIG_TOUCHSCREEN_SX8654 is not set
+CONFIG_DEVMEM=y
+CONFIG_SERIAL_EARLYCON=y
+# CONFIG_SERIAL_8250_FINTEK is not set
+# CONFIG_SERIAL_SC16IS7XX is not set
+# CONFIG_IPMI_SSIF is not set
+# CONFIG_TCG_CRB is not set
+# CONFIG_TCG_TIS_ST33ZP24 is not set
+# CONFIG_XILLYBUS is not set
+CONFIG_ACPI_I2C_OPREGION=y
+# CONFIG_I2C_SLAVE is not set
+# CONFIG_SPI_CADENCE is not set
+# CONFIG_SPMI is not set
+# CONFIG_PINCTRL_BAYTRAIL is not set
+# CONFIG_PINCTRL_CHERRYVIEW is not set
+# CONFIG_PINCTRL_SUNRISEPOINT is not set
+CONFIG_GPIOLIB_IRQCHIP=y
+# CONFIG_GPIO_DWAPB is not set
+# CONFIG_GPIO_F7188X is not set
+# CONFIG_GPIO_ICH is not set
+# CONFIG_GPIO_LYNXPOINT is not set
+# CONFIG_GPIO_SCH311X is not set
+# CONFIG_GPIO_ADP5588 is not set
+# CONFIG_GPIO_BT8XX is not set
+# CONFIG_BATTERY_GAUGE_LTC2941 is not set
+# CONFIG_SENSORS_APPLESMC is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_G762 is not set
+# CONFIG_SENSORS_I5500 is not set
+# CONFIG_SENSORS_CORETEMP is not set
+# CONFIG_SENSORS_POWR1220 is not set
+# CONFIG_SENSORS_LTC2945 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4222 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4260 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX197 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_MAX6697 is not set
+# CONFIG_SENSORS_MCP3021 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_NCT6683 is not set
+# CONFIG_SENSORS_NCT6775 is not set
+# CONFIG_SENSORS_NCT7802 is not set
+# CONFIG_SENSORS_NCT7904 is not set
+# CONFIG_SENSORS_SHTC1 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_ADC128D818 is not set
+# CONFIG_SENSORS_TMP103 is not set
+# CONFIG_THERMAL_GOV_BANG_BANG is not set
+# CONFIG_INTEL_SOC_DTS_THERMAL is not set
+# CONFIG_INT340X_THERMAL is not set
+# CONFIG_XILINX_WATCHDOG is not set
+# CONFIG_CADENCE_WATCHDOG is not set
+CONFIG_BCMA_DRIVER_PCI=y
+# CONFIG_MFD_BCM590XX is not set
+# CONFIG_MFD_AXP20X is not set
+# CONFIG_MFD_DA9150 is not set
+# CONFIG_MFD_DLN2 is not set
+# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set
+# CONFIG_INTEL_SOC_PMIC is not set
+# CONFIG_MFD_MAX77843 is not set
+# CONFIG_MFD_MT6397 is not set
+# CONFIG_MFD_MENF21BMC is not set
+# CONFIG_MFD_RT5033 is not set
+# CONFIG_MFD_RN5T618 is not set
+# CONFIG_MFD_SKY81452 is not set
+# CONFIG_MFD_TPS65218 is not set
+# CONFIG_MEDIA_SDR_SUPPORT is not set
+# CONFIG_USB_GSPCA_DTCS033 is not set
+# CONFIG_USB_GSPCA_TOUPTEK is not set
+# CONFIG_DRM_I2C_ADV7511 is not set
+# CONFIG_DRM_VGEM is not set
+# CONFIG_HSA_AMD is not set
+CONFIG_FB_CMDLINE=y
+CONFIG_HDMI=y
+CONFIG_DUMMY_CONSOLE_COLUMNS=80
+CONFIG_DUMMY_CONSOLE_ROWS=25
+# CONFIG_HID_BETOP_FF is not set
+# CONFIG_HID_CP2112 is not set
+# CONFIG_HID_GT683R is not set
+# CONFIG_HID_LENOVO is not set
+# CONFIG_HID_LOGITECH_HIDPP is not set
+# CONFIG_HID_PENMOUNT is not set
+# CONFIG_HID_PLANTRONICS is not set
+# CONFIG_HID_RMI is not set
+# CONFIG_USB_OTG_FSM is not set
+CONFIG_USB_XHCI_PCI=y
+# CONFIG_USB_MAX3421_HCD is not set
+# CONFIG_USB_UAS is not set
+# CONFIG_USBIP_CORE is not set
+# CONFIG_USB_ISP1760 is not set
+# CONFIG_USB_LINK_LAYER_TEST is not set
+# CONFIG_USB_CHAOSKEY is not set
+# CONFIG_USB_LED_TRIG is not set
+# CONFIG_MMC_USDHI6ROL0 is not set
+# CONFIG_MMC_TOSHIBA_PCI is not set
+# CONFIG_LEDS_CLASS_FLASH is not set
+# CONFIG_LEDS_LP8860 is not set
+# CONFIG_EDAC_IE31200 is not set
+# CONFIG_RTC_DRV_ABB5ZES3 is not set
+# CONFIG_RTC_DRV_ABX80X is not set
+# CONFIG_RTC_DRV_PCF85063 is not set
+# CONFIG_RTC_DRV_DS1343 is not set
+# CONFIG_RTC_DRV_DS1347 is not set
+# CONFIG_RTC_DRV_MCP795 is not set
+# CONFIG_RTC_DRV_DS1685_FAMILY is not set
+# CONFIG_RTC_DRV_DS2404 is not set
+# CONFIG_RTC_DRV_XGENE is not set
+# CONFIG_FB_SM750 is not set
+# CONFIG_GS_FPGABOOT is not set
+# CONFIG_UNISYSSPAR is not set
+# CONFIG_FB_TFT is not set
+# CONFIG_DELL_SMO8800 is not set
+# CONFIG_TOSHIBA_HAPS is not set
+# CONFIG_COMMON_CLK_PXA is not set
+# CONFIG_COMMON_CLK_CDCE706 is not set
+# CONFIG_ATMEL_PIT is not set
+# CONFIG_SH_TIMER_CMT is not set
+# CONFIG_SH_TIMER_MTU2 is not set
+# CONFIG_SH_TIMER_TMU is not set
+# CONFIG_EM_TIMER_STI is not set
+# CONFIG_SOC_TI is not set
+# CONFIG_PM_DEVFREQ_EVENT is not set
+# CONFIG_BCM_KONA_USB2_PHY is not set
+# CONFIG_MCB is not set
+CONFIG_RAS=y
+# CONFIG_THUNDERBOLT is not set
+# CONFIG_ANDROID is not set
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+# CONFIG_EXT4_ENCRYPTION is not set
+# CONFIG_F2FS_FS is not set
+# CONFIG_FS_DAX is not set
+# CONFIG_OVERLAY_FS is not set
+CONFIG_KERNFS=y
+CONFIG_EFIVAR_FS=m
+# CONFIG_SQUASHFS_LZ4 is not set
+# CONFIG_PSTORE_PMSG is not set
+# CONFIG_NFSD_PNFS is not set
+CONFIG_GRACE_PERIOD=y
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
+# CONFIG_DEBUG_INFO_SPLIT is not set
+# CONFIG_DEBUG_INFO_DWARF4 is not set
+# CONFIG_GDB_SCRIPTS is not set
+# CONFIG_PAGE_OWNER is not set
+# CONFIG_PAGE_EXTENSION is not set
+CONFIG_HAVE_ARCH_KASAN=y
+# CONFIG_KASAN is not set
+CONFIG_KASAN_SHADOW_OFFSET=0xdffffc0000000000
+# CONFIG_SCHED_STACK_END_CHECK is not set
+# CONFIG_DEBUG_TIMEKEEPING is not set
+# CONFIG_LOCK_TORTURE_TEST is not set
+# CONFIG_DEBUG_PI_LIST is not set
+# CONFIG_PROVE_RCU is not set
+# CONFIG_TORTURE_TEST is not set
+# CONFIG_TRACEPOINT_BENCHMARK is not set
+# CONFIG_TEST_HEXDUMP is not set
+# CONFIG_TEST_RHASHTABLE is not set
+# CONFIG_TEST_LKM is not set
+# CONFIG_TEST_BPF is not set
+# CONFIG_TEST_FIRMWARE is not set
+# CONFIG_TEST_UDELAY is not set
+# CONFIG_MEMTEST is not set
+CONFIG_INTEGRITY=y
+# CONFIG_INTEGRITY_SIGNATURE is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_MCRYPTD is not set
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_GHASH=m
+# CONFIG_CRYPTO_SHA1_MB is not set
+# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set
+# CONFIG_CRYPTO_DRBG_MENU is not set
+# CONFIG_CRYPTO_USER_API_RNG is not set
+# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set
+CONFIG_KVM_COMPAT=y
+# CONFIG_HAVE_ARCH_BITREVERSE is not set
+CONFIG_RATIONAL=y
+CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
+# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_GLOB=y
+# CONFIG_GLOB_SELFTEST is not set
+CONFIG_ARCH_HAS_SG_CHAIN=y
+# CONFIG_PINMUX is not set
+CONFIG_UIO=y
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/e3000-standard-only.cfg b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/e3000-standard-only.cfg
new file mode 100644
index 00000000..bfc1701d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/e3000-standard-only.cfg
@@ -0,0 +1,3 @@
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
+CONFIG_X86_POWERNOW_K8=y
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/e3000-user-config.cfg b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/e3000-user-config.cfg
new file mode 100644
index 00000000..b5ec507a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/e3000-user-config.cfg
@@ -0,0 +1,405 @@
+CONFIG_X86_BIGSMP=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_IRQ_DOMAIN=y
+
+CONFIG_CGROUP_PERF=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_THROTTLING=y
+CONFIG_BLK_CMDLINE_PARSER=y
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+
+#
+# IO Schedulers
+#
+CONFIG_CFQ_GROUP_IOSCHED=y
+CONFIG_DEFAULT_DEADLINE=y
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_X86_AMD_PLATFORM_DEVICE=y
+CONFIG_PROCESSOR_SELECT=y
+CONFIG_CPU_SUP_AMD=y
+CONFIG_HPET_TIMER=y
+CONFIG_HPET_EMULATE_RTC=y
+CONFIG_GART_IOMMU=y
+CONFIG_CALGARY_IOMMU=y
+CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y
+CONFIG_SWIOTLB=y
+CONFIG_NR_CPUS=64
+CONFIG_X86_MCE=y
+CONFIG_X86_MCE_AMD=y
+CONFIG_X86_MCE_INJECT=m
+
+#
+# Performance monitoring
+#
+CONFIG_MICROCODE=y
+CONFIG_MICROCODE_AMD=y
+CONFIG_X86_MSR=m
+CONFIG_X86_CPUID=m
+CONFIG_NUMA=y
+CONFIG_AMD_NUMA=y
+CONFIG_X86_64_ACPI_NUMA=y
+CONFIG_NODES_SPAN_OTHER_NODES=y
+CONFIG_NODES_SHIFT=6
+CONFIG_ARCH_MEMORY_PROBE=y
+CONFIG_NEED_MULTIPLE_NODES=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_HAVE_BOOTMEM_INFO_NODE=y
+CONFIG_MEMORY_HOTPLUG=y
+CONFIG_MEMORY_HOTPLUG_SPARSE=y
+CONFIG_MEMORY_HOTREMOVE=y
+CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
+CONFIG_BOUNCE=y
+CONFIG_MMU_NOTIFIER=y
+CONFIG_KSM=y
+CONFIG_MEMORY_FAILURE=y
+CONFIG_CLEANCACHE=y
+CONFIG_FRONTSWAP=y
+CONFIG_CMA=y
+CONFIG_KEXEC=y
+CONFIG_CRASH_DUMP=y
+CONFIG_PHYSICAL_ALIGN=0x1000000
+CONFIG_RANDOMIZE_MEMORY=y
+CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa
+CONFIG_COMPAT_VDSO=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+
+#
+# Power management and ACPI options
+#
+CONFIG_ARCH_HIBERNATION_HEADER=y
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HIBERNATION=y
+CONFIG_PM_STD_PARTITION=""
+CONFIG_PM_TRACE=y
+CONFIG_PM_TRACE_RTC=y
+CONFIG_ACPI_VIDEO=m
+CONFIG_ACPI_NUMA=y
+CONFIG_ACPI_SBS=m
+CONFIG_ACPI_HED=y
+CONFIG_ACPI_BGRT=y
+CONFIG_ACPI_APEI=y
+CONFIG_ACPI_APEI_PCIEAER=y
+CONFIG_ACPI_APEI_MEMORY_FAILURE=y
+CONFIG_ACPI_APEI_EINJ=m
+CONFIG_ACPI_APEI_ERST_DEBUG=m
+CONFIG_SFI=y
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+
+#
+# CPU frequency scaling drivers
+#
+CONFIG_X86_PCC_CPUFREQ=y
+CONFIG_X86_ACPI_CPUFREQ=y
+CONFIG_X86_ACPI_CPUFREQ_CPB=y
+CONFIG_X86_POWERNOW_K8=y
+CONFIG_X86_AMD_FREQ_SENSITIVITY=m
+CONFIG_X86_SPEEDSTEP_CENTRINO=y
+CONFIG_X86_P4_CLOCKMOD=m
+
+#
+# shared options
+#
+CONFIG_X86_SPEEDSTEP_LIB=m
+
+
+#
+# Bus options (PCI etc.)
+#
+CONFIG_PCI_MMCONFIG=y
+CONFIG_PCI_REALLOC_ENABLE_AUTO=y
+CONFIG_PCI_STUB=m
+CONFIG_PCI_ATS=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_PRI=y
+CONFIG_PCI_PASID=y
+CONFIG_HOTPLUG_PCI_CPCI=y
+CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m
+CONFIG_HOTPLUG_PCI_SHPC=m
+
+#
+# PCI host controller drivers
+#
+CONFIG_AMD_NB=y
+
+#
+# RapidIO Switch drivers
+#
+CONFIG_X86_SYSFB=y
+
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_FQ=m
+#
+# Misc devices
+#
+CONFIG_ENCLOSURE_SERVICES=m
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_LEGACY=m
+
+
+#
+# Controllers with non-SFF native interface
+#
+CONFIG_SATA_AHCI_PLATFORM=m
+
+
+#
+# Distributed Switch Architecture drivers
+#
+CONFIG_E1000=y
+CONFIG_E1000E=y
+CONFIG_E1000E_HWTS=y
+CONFIG_IGB=y
+CONFIG_IGB_HWMON=y
+CONFIG_IGBVF=y
+CONFIG_IXGB=y
+CONFIG_IXGBE=y
+CONFIG_IXGBE_HWMON=y
+CONFIG_IXGBEVF=y
+
+#
+# MDIO bus device drivers
+#
+CONFIG_MDIO_GPIO=m
+
+#
+# MII PHY device drivers
+#
+CONFIG_AMD_PHY=m
+
+CONFIG_SERIAL_8250_NR_UARTS=48
+CONFIG_SERIAL_8250_RUNTIME_UARTS=32
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_8250_DW=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_IPMI_HANDLER=m
+CONFIG_HW_RANDOM_TPM=m
+CONFIG_NVRAM=m
+
+#
+# PCMCIA character devices
+#
+CONFIG_HANGCHECK_TIMER=m
+CONFIG_TCG_TPM=y
+
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_PIIX4=m
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_CBUS_GPIO=m
+CONFIG_I2C_DESIGNWARE_CORE=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_DESIGNWARE_PCI=m
+CONFIG_I2C_DESIGNWARE_BAYTRAIL=y
+CONFIG_I2C_GPIO=m
+CONFIG_I2C_KEMPLD=m
+CONFIG_I2C_OCORES=m
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=m
+#
+# Pin controllers
+#
+CONFIG_PINCTRL_AMD=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_ACPI=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_GENERIC=y
+#
+# Memory mapped GPIO drivers
+#
+CONFIG_GPIO_GENERIC_PLATFORM=y
+
+#
+# PCI GPIO expanders
+#
+CONFIG_GPIO_ML_IOH=m
+
+#
+# Native drivers
+#
+CONFIG_SENSORS_K10TEMP=m
+CONFIG_SENSORS_FAM15H_POWER=m
+
+#
+# ACPI drivers
+#
+CONFIG_SENSORS_ACPI_POWER=m
+
+
+#
+# Graphics support
+#
+CONFIG_AGP_AMD64=y
+CONFIG_VGA_SWITCHEROO=y
+
+
+#
+# Frame buffer Devices
+#
+
+#
+# Frame buffer hardware drivers
+#
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+#
+# Console display driver support
+#
+
+
+#
+# CODEC drivers
+#
+
+
+#
+# USB HID support
+#
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+CONFIG_USB_OHCI_HCD_PCI=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SPI=m
+
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EDAC=y
+CONFIG_EDAC_LEGACY_SYSFS=y
+CONFIG_EDAC_DECODE_MCE=y
+CONFIG_EDAC_AMD64=y
+CONFIG_EDAC_AMD64_ERROR_INJECTION=y
+
+#
+# DMABUF options
+#
+CONFIG_AUXDISPLAY=y
+
+
+#
+# Clock Source drivers
+#
+CONFIG_IOMMU_API=y
+CONFIG_IOMMU_SUPPORT=y
+
+#
+# Generic IOMMU Pagetable Support
+#
+CONFIG_IOMMU_IOVA=y
+CONFIG_AMD_IOMMU=y
+CONFIG_AMD_IOMMU_V2=y
+CONFIG_DMAR_TABLE=y
+CONFIG_IRQ_REMAP=y
+
+#
+# Broadcom SoC drivers
+#
+CONFIG_PM_DEVFREQ=y
+
+#
+# DEVFREQ Governors
+#
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+
+
+CONFIG_MEMORY=y
+
+#
+# Firmware Drivers
+#
+CONFIG_EDD=y
+CONFIG_EDD_OFF=y
+CONFIG_DMI_SYSFS=m
+
+#
+# EFI (Extensible Firmware Interface) Support
+#
+CONFIG_EFI_VARS=y
+CONFIG_EFI_VARS_PSTORE=m
+CONFIG_EFI_RUNTIME_MAP=y
+CONFIG_UEFI_CPER=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_UDF_FS=m
+
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_VMCORE=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_PSTORE=y
+
+#
+# Compile-time checks and compiler options
+#
+CONFIG_DEBUG_KERNEL=y
+
+CONFIG_SECURITYFS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_INTERVAL_TREE=y
+
+#
+# Graphics support
+#
+
+#
+# Console display driver support
+#
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/e3000-user-features.scc b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/e3000-user-features.scc
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/e3000-user-features.scc
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/e3000-user-patches.scc b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/e3000-user-patches.scc
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/e3000-user-patches.scc
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/e3000.cfg b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/e3000.cfg
new file mode 100644
index 00000000..b321cee6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/e3000.cfg
@@ -0,0 +1,59 @@
+CONFIG_PRINTK=y
+
+# Basic hardware support for the box - network, USB, PCI, sound
+CONFIG_NETDEVICES=y
+CONFIG_ATA=y
+CONFIG_ATA_GENERIC=y
+CONFIG_ATA_SFF=y
+CONFIG_PCI=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PCI=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB=y
+CONFIG_PATA_SCH=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_NET=y
+CONFIG_USB_UHCI_HCD=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+
+# Make sure these are on, otherwise the bootup won't be fun
+CONFIG_EXT3_FS=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_MODULES=y
+CONFIG_SHMEM=y
+CONFIG_TMPFS=y
+CONFIG_PACKET=y
+
+CONFIG_I2C=y
+CONFIG_AGP=y
+CONFIG_PM=y
+CONFIG_ACPI=y
+CONFIG_INPUT=y
+
+# Needed for booting (and using) USB memory sticks
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+
+CONFIG_RD_GZIP=y
+
+# Filesystems
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V4=y
+CONFIG_QFMT_V2
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+CONFIG_QUOTA_TREE=m
+CONFIG_QUOTACTL=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/kvm.cfg b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/kvm.cfg
new file mode 100644
index 00000000..f4ca1c77
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-e3000/kvm.cfg
@@ -0,0 +1,39 @@
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+# CONFIG_TASK_XACCT is not set
+
+CONFIG_USER_RETURN_NOTIFIER=y
+CONFIG_PREEMPT_NOTIFIERS=y
+CONFIG_VFIO_IOMMU_TYPE1=y
+CONFIG_VFIO_VIRQFD=y
+CONFIG_VFIO=y
+# CONFIG_VFIO_NOIOMMU is not set
+CONFIG_VFIO_PCI=y
+# CONFIG_VFIO_PCI_VGA is not set
+CONFIG_VFIO_PCI_MMAP=y
+CONFIG_VFIO_PCI_INTX=y
+CONFIG_VFIO_PCI_IGD=y
+CONFIG_IRQ_BYPASS_MANAGER=y
+CONFIG_VIRT_DRIVERS=y
+CONFIG_SCHED_INFO=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTIO_INPUT=y
+
+CONFIG_HAVE_KVM_IRQCHIP=y
+CONFIG_HAVE_KVM_IRQFD=y
+CONFIG_HAVE_KVM_IRQ_ROUTING=y
+CONFIG_HAVE_KVM_EVENTFD=y
+CONFIG_KVM_MMIO=y
+CONFIG_KVM_ASYNC_PF=y
+CONFIG_HAVE_KVM_MSI=y
+CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
+CONFIG_KVM_VFIO=y
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_KVM_COMPAT=y
+CONFIG_HAVE_KVM_IRQ_BYPASS=y
+CONFIG_KVM=y
+# CONFIG_KVM_INTEL is not set
+CONFIG_KVM_AMD=y
+# CONFIG_KVM_MMU_AUDIT is not set
+
+CONFIG_KVM_AMD_SEV=y
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000-extra-config.cfg b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000-extra-config.cfg
new file mode 100644
index 00000000..82ce9e4f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000-extra-config.cfg
@@ -0,0 +1,388 @@
+CONFIG_PERF_EVENTS_INTEL_UNCORE=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_USELIB=y
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
+CONFIG_SRCU=y
+# CONFIG_TASKS_RCU is not set
+CONFIG_BUILD_BIN2C=y
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+CONFIG_PAGE_COUNTER=y
+CONFIG_BPF=y
+CONFIG_MULTIUSER=y
+CONFIG_SGETMASK_SYSCALL=y
+CONFIG_SYSFS_SYSCALL=y
+# CONFIG_BPF_SYSCALL is not set
+CONFIG_ADVISE_SYSCALLS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_ARCH_HUGE_VMAP=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+# CONFIG_MODULE_COMPRESS is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_X86_FEATURE_NAMES=y
+# CONFIG_X86_GOLDFISH is not set
+CONFIG_IOSF_MBI=m
+# CONFIG_IOSF_MBI_DEBUG is not set
+CONFIG_X86_VSYSCALL_EMULATION=y
+CONFIG_X86_DIRECT_GBPAGES=y
+CONFIG_MEMORY_BALLOON=y
+# CONFIG_ZSWAP is not set
+# CONFIG_ZPOOL is not set
+# CONFIG_ZBUD is not set
+CONFIG_GENERIC_EARLY_IOREMAP=y
+# CONFIG_X86_PMEM_LEGACY is not set
+# CONFIG_X86_INTEL_MPX is not set
+# CONFIG_EFI_MIXED is not set
+CONFIG_HAVE_LIVEPATCH=y
+# CONFIG_LIVEPATCH is not set
+CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
+CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
+CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
+CONFIG_ACPI_HOTPLUG_IOAPIC=y
+# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set
+CONFIG_HAVE_ACPI_APEI=y
+CONFIG_HAVE_ACPI_APEI_NMI=y
+# CONFIG_PMIC_OPREGION is not set
+CONFIG_PMC_ATOM=y
+CONFIG_NET_UDP_TUNNEL=m
+# CONFIG_NET_FOU is not set
+# CONFIG_NET_FOU_IP_TUNNELS is not set
+# CONFIG_GENEVE is not set
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_BRIDGE_NETFILTER=m
+CONFIG_NF_NAT_REDIRECT=m
+# CONFIG_NETFILTER_XT_NAT is not set
+# CONFIG_NF_LOG_ARP is not set
+# CONFIG_NF_LOG_IPV4 is not set
+CONFIG_NF_REJECT_IPV4=m
+CONFIG_NF_NAT_IPV4=m
+# CONFIG_NF_NAT_MASQUERADE_IPV4 is not set
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+# CONFIG_IP_NF_NAT is not set
+# CONFIG_NF_REJECT_IPV6 is not set
+# CONFIG_NF_LOG_IPV6 is not set
+CONFIG_TIPC_MEDIA_UDP=y
+# CONFIG_NET_ACT_VLAN is not set
+# CONFIG_NET_ACT_BPF is not set
+# CONFIG_NET_ACT_CONNMARK is not set
+# CONFIG_MPLS is not set
+# CONFIG_NET_SWITCHDEV is not set
+# CONFIG_MAC80211_RC_MINSTREL_VHT is not set
+CONFIG_UEVENT_HELPER=y
+# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
+CONFIG_ALLOW_DEV_COREDUMP=y
+# CONFIG_BLK_DEV_PMEM is not set
+# CONFIG_INTEL_MEI_TXE is not set
+# CONFIG_INTEL_MIC_BUS is not set
+# CONFIG_ECHO is not set
+# CONFIG_CXL_BASE is not set
+# CONFIG_SCSI_MQ_DEFAULT is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_WD719X is not set
+# CONFIG_DM_MQ_DEFAULT is not set
+# CONFIG_DM_ERA is not set
+# CONFIG_DM_LOG_WRITES is not set
+# CONFIG_IPVLAN is not set
+# CONFIG_NET_VENDOR_AGERE is not set
+# CONFIG_ET131X is not set
+# CONFIG_ALTERA_TSE is not set
+# CONFIG_BCMGENET is not set
+# CONFIG_CX_ECAT is not set
+# CONFIG_FM10K is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_SXGBE_ETH is not set
+# CONFIG_TI_CPSW_ALE is not set
+# CONFIG_BCM7XXX_PHY is not set
+CONFIG_MARVELL_PHY=y
+# CONFIG_MDIO_BCM_UNIMAC is not set
+CONFIG_USB_NET_DRIVERS=y
+# CONFIG_ATH9K_DYNACK is not set
+# CONFIG_ATH9K_CHANNEL_CONTEXT is not set
+CONFIG_ATH9K_PCOEM=y
+CONFIG_BRCMFMAC_PROTO_BCDC=y
+# CONFIG_BRCMFMAC_PCIE is not set
+# CONFIG_RTL8723BE is not set
+# CONFIG_RTL8192EE is not set
+# CONFIG_RTL8821AE is not set
+# CONFIG_RSI_91X is not set
+# CONFIG_MOUSE_PS2_FOCALTECH is not set
+# CONFIG_MOUSE_ELAN_I2C is not set
+# CONFIG_TABLET_SERIAL_WACOM4 is not set
+# CONFIG_TOUCHSCREEN_GOODIX is not set
+# CONFIG_TOUCHSCREEN_ELAN is not set
+# CONFIG_TOUCHSCREEN_SX8654 is not set
+CONFIG_DEVMEM=y
+CONFIG_SERIAL_EARLYCON=y
+# CONFIG_SERIAL_8250_FINTEK is not set
+# CONFIG_SERIAL_SC16IS7XX is not set
+# CONFIG_IPMI_SSIF is not set
+# CONFIG_TCG_CRB is not set
+# CONFIG_TCG_TIS_ST33ZP24 is not set
+# CONFIG_XILLYBUS is not set
+CONFIG_ACPI_I2C_OPREGION=y
+# CONFIG_I2C_SLAVE is not set
+# CONFIG_SPI_CADENCE is not set
+# CONFIG_SPMI is not set
+# CONFIG_PINCTRL_BAYTRAIL is not set
+# CONFIG_PINCTRL_CHERRYVIEW is not set
+# CONFIG_PINCTRL_SUNRISEPOINT is not set
+CONFIG_GPIOLIB_IRQCHIP=y
+# CONFIG_GPIO_DWAPB is not set
+# CONFIG_GPIO_F7188X is not set
+# CONFIG_GPIO_ICH is not set
+# CONFIG_GPIO_LYNXPOINT is not set
+# CONFIG_GPIO_SCH311X is not set
+# CONFIG_GPIO_ADP5588 is not set
+# CONFIG_GPIO_BT8XX is not set
+# CONFIG_BATTERY_GAUGE_LTC2941 is not set
+# CONFIG_SENSORS_APPLESMC is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_G762 is not set
+# CONFIG_SENSORS_I5500 is not set
+# CONFIG_SENSORS_CORETEMP is not set
+# CONFIG_SENSORS_POWR1220 is not set
+# CONFIG_SENSORS_LTC2945 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4222 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4260 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX197 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_MAX6697 is not set
+# CONFIG_SENSORS_MCP3021 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_NCT6683 is not set
+# CONFIG_SENSORS_NCT6775 is not set
+# CONFIG_SENSORS_NCT7802 is not set
+# CONFIG_SENSORS_NCT7904 is not set
+# CONFIG_SENSORS_SHTC1 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_ADC128D818 is not set
+# CONFIG_SENSORS_TMP103 is not set
+# CONFIG_THERMAL_GOV_BANG_BANG is not set
+# CONFIG_INTEL_SOC_DTS_THERMAL is not set
+# CONFIG_INT340X_THERMAL is not set
+# CONFIG_XILINX_WATCHDOG is not set
+# CONFIG_CADENCE_WATCHDOG is not set
+CONFIG_BCMA_DRIVER_PCI=y
+# CONFIG_MFD_BCM590XX is not set
+# CONFIG_MFD_AXP20X is not set
+# CONFIG_MFD_DA9150 is not set
+# CONFIG_MFD_DLN2 is not set
+# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set
+# CONFIG_INTEL_SOC_PMIC is not set
+# CONFIG_MFD_MAX77843 is not set
+# CONFIG_MFD_MT6397 is not set
+# CONFIG_MFD_MENF21BMC is not set
+# CONFIG_MFD_RT5033 is not set
+# CONFIG_MFD_RN5T618 is not set
+# CONFIG_MFD_SKY81452 is not set
+# CONFIG_MFD_TPS65218 is not set
+# CONFIG_MEDIA_SDR_SUPPORT is not set
+# CONFIG_USB_GSPCA_DTCS033 is not set
+# CONFIG_USB_GSPCA_TOUPTEK is not set
+# CONFIG_DRM_I2C_ADV7511 is not set
+# CONFIG_DRM_VGEM is not set
+CONFIG_FB_CMDLINE=y
+CONFIG_HDMI=y
+CONFIG_DUMMY_CONSOLE_COLUMNS=80
+CONFIG_DUMMY_CONSOLE_ROWS=25
+CONFIG_SND_DMAENGINE_PCM=m
+# CONFIG_SND_SE6X is not set
+CONFIG_SND_HDA=y
+CONFIG_SND_HDA_PREALLOC_SIZE=64
+# CONFIG_SND_HDA_CODEC_CA0132_DSP is not set
+CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
+CONFIG_SND_HDA_CORE=y
+# CONFIG_SND_BCD2000 is not set
+# CONFIG_SND_USB_POD is not set
+# CONFIG_SND_USB_PODHD is not set
+# CONFIG_SND_USB_TONEPORT is not set
+# CONFIG_SND_USB_VARIAX is not set
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+# CONFIG_SND_SOC_FSL_ASRC is not set
+# CONFIG_SND_SOC_FSL_SAI is not set
+# CONFIG_SND_SOC_FSL_SSI is not set
+# CONFIG_SND_SOC_FSL_SPDIF is not set
+# CONFIG_SND_SOC_FSL_ESAI is not set
+# CONFIG_SND_SOC_IMX_AUDMUX is not set
+# CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH is not set
+# CONFIG_SND_SOC_QCOM is not set
+# CONFIG_SND_SOC_XTFPGA_I2S is not set
+# CONFIG_SND_SOC_ADAU1701 is not set
+# CONFIG_SND_SOC_AK4104 is not set
+# CONFIG_SND_SOC_AK4554 is not set
+# CONFIG_SND_SOC_AK4642 is not set
+# CONFIG_SND_SOC_AK5386 is not set
+# CONFIG_SND_SOC_ALC5623 is not set
+# CONFIG_SND_SOC_CS35L32 is not set
+# CONFIG_SND_SOC_CS42L51_I2C is not set
+# CONFIG_SND_SOC_CS42L52 is not set
+# CONFIG_SND_SOC_CS42L56 is not set
+# CONFIG_SND_SOC_CS42L73 is not set
+# CONFIG_SND_SOC_CS4265 is not set
+# CONFIG_SND_SOC_CS4270 is not set
+# CONFIG_SND_SOC_CS4271_I2C is not set
+# CONFIG_SND_SOC_CS4271_SPI is not set
+# CONFIG_SND_SOC_CS42XX8_I2C is not set
+# CONFIG_SND_SOC_HDMI_CODEC is not set
+# CONFIG_SND_SOC_ES8328 is not set
+# CONFIG_SND_SOC_PCM1681 is not set
+# CONFIG_SND_SOC_PCM512x_I2C is not set
+# CONFIG_SND_SOC_PCM512x_SPI is not set
+# CONFIG_SND_SOC_RT5631 is not set
+# CONFIG_SND_SOC_RT5677_SPI is not set
+# CONFIG_SND_SOC_SGTL5000 is not set
+# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set
+# CONFIG_SND_SOC_SPDIF is not set
+# CONFIG_SND_SOC_SSM2602_SPI is not set
+# CONFIG_SND_SOC_SSM2602_I2C is not set
+# CONFIG_SND_SOC_SSM4567 is not set
+# CONFIG_SND_SOC_STA32X is not set
+# CONFIG_SND_SOC_STA350 is not set
+# CONFIG_SND_SOC_TAS2552 is not set
+# CONFIG_SND_SOC_TAS5086 is not set
+# CONFIG_SND_SOC_TFA9879 is not set
+# CONFIG_SND_SOC_TLV320AIC23_I2C is not set
+# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
+# CONFIG_SND_SOC_TLV320AIC31XX is not set
+# CONFIG_SND_SOC_TLV320AIC3X is not set
+# CONFIG_SND_SOC_TS3A227E is not set
+# CONFIG_SND_SOC_WM8510 is not set
+# CONFIG_SND_SOC_WM8523 is not set
+# CONFIG_SND_SOC_WM8580 is not set
+# CONFIG_SND_SOC_WM8711 is not set
+# CONFIG_SND_SOC_WM8728 is not set
+# CONFIG_SND_SOC_WM8731 is not set
+# CONFIG_SND_SOC_WM8737 is not set
+# CONFIG_SND_SOC_WM8741 is not set
+# CONFIG_SND_SOC_WM8750 is not set
+# CONFIG_SND_SOC_WM8753 is not set
+# CONFIG_SND_SOC_WM8770 is not set
+# CONFIG_SND_SOC_WM8776 is not set
+# CONFIG_SND_SOC_WM8804_I2C is not set
+# CONFIG_SND_SOC_WM8804_SPI is not set
+# CONFIG_SND_SOC_WM8903 is not set
+# CONFIG_SND_SOC_WM8962 is not set
+# CONFIG_SND_SOC_WM8978 is not set
+# CONFIG_SND_SOC_TPA6130A2 is not set
+# CONFIG_USB_OTG_FSM is not set
+CONFIG_USB_XHCI_PCI=y
+# CONFIG_USB_MAX3421_HCD is not set
+# CONFIG_USB_UAS is not set
+# CONFIG_USBIP_CORE is not set
+# CONFIG_USB_ISP1760 is not set
+# CONFIG_USB_LINK_LAYER_TEST is not set
+# CONFIG_USB_CHAOSKEY is not set
+# CONFIG_USB_LED_TRIG is not set
+# CONFIG_MMC_USDHI6ROL0 is not set
+# CONFIG_MMC_TOSHIBA_PCI is not set
+# CONFIG_LEDS_CLASS_FLASH is not set
+# CONFIG_LEDS_LP8860 is not set
+# CONFIG_EDAC_IE31200 is not set
+# CONFIG_RTC_DRV_ABB5ZES3 is not set
+# CONFIG_RTC_DRV_ABX80X is not set
+# CONFIG_RTC_DRV_PCF85063 is not set
+# CONFIG_RTC_DRV_DS1343 is not set
+# CONFIG_RTC_DRV_DS1347 is not set
+# CONFIG_RTC_DRV_MCP795 is not set
+# CONFIG_RTC_DRV_DS1685_FAMILY is not set
+# CONFIG_RTC_DRV_DS2404 is not set
+# CONFIG_RTC_DRV_XGENE is not set
+CONFIG_VIRTIO_PCI_LEGACY=y
+# CONFIG_VIRTIO_INPUT is not set
+# CONFIG_FB_SM750 is not set
+# CONFIG_GS_FPGABOOT is not set
+# CONFIG_UNISYSSPAR is not set
+# CONFIG_FB_TFT is not set
+# CONFIG_DELL_SMO8800 is not set
+# CONFIG_TOSHIBA_HAPS is not set
+# CONFIG_COMMON_CLK_PXA is not set
+# CONFIG_COMMON_CLK_CDCE706 is not set
+# CONFIG_ATMEL_PIT is not set
+# CONFIG_SH_TIMER_CMT is not set
+# CONFIG_SH_TIMER_MTU2 is not set
+# CONFIG_SH_TIMER_TMU is not set
+# CONFIG_EM_TIMER_STI is not set
+# CONFIG_SOC_TI is not set
+# CONFIG_PM_DEVFREQ_EVENT is not set
+# CONFIG_BCM_KONA_USB2_PHY is not set
+# CONFIG_MCB is not set
+CONFIG_RAS=y
+# CONFIG_THUNDERBOLT is not set
+# CONFIG_ANDROID is not set
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+# CONFIG_EXT4_ENCRYPTION is not set
+# CONFIG_F2FS_FS is not set
+# CONFIG_FS_DAX is not set
+# CONFIG_OVERLAY_FS is not set
+CONFIG_KERNFS=y
+CONFIG_EFIVAR_FS=m
+# CONFIG_SQUASHFS_LZ4 is not set
+# CONFIG_PSTORE_PMSG is not set
+# CONFIG_NFSD_PNFS is not set
+CONFIG_GRACE_PERIOD=y
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
+# CONFIG_DEBUG_INFO_SPLIT is not set
+# CONFIG_DEBUG_INFO_DWARF4 is not set
+# CONFIG_GDB_SCRIPTS is not set
+# CONFIG_PAGE_OWNER is not set
+# CONFIG_PAGE_EXTENSION is not set
+CONFIG_HAVE_ARCH_KASAN=y
+# CONFIG_KASAN is not set
+CONFIG_KASAN_SHADOW_OFFSET=0xdffffc0000000000
+# CONFIG_SCHED_STACK_END_CHECK is not set
+# CONFIG_DEBUG_TIMEKEEPING is not set
+# CONFIG_LOCK_TORTURE_TEST is not set
+# CONFIG_DEBUG_PI_LIST is not set
+# CONFIG_PROVE_RCU is not set
+# CONFIG_TORTURE_TEST is not set
+# CONFIG_TRACEPOINT_BENCHMARK is not set
+# CONFIG_TEST_HEXDUMP is not set
+# CONFIG_TEST_RHASHTABLE is not set
+# CONFIG_TEST_LKM is not set
+# CONFIG_TEST_BPF is not set
+# CONFIG_TEST_FIRMWARE is not set
+# CONFIG_TEST_UDELAY is not set
+# CONFIG_MEMTEST is not set
+CONFIG_INTEGRITY=y
+# CONFIG_INTEGRITY_SIGNATURE is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_MCRYPTD is not set
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_GHASH=m
+# CONFIG_CRYPTO_SHA1_MB is not set
+# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set
+# CONFIG_CRYPTO_DRBG_MENU is not set
+# CONFIG_CRYPTO_USER_API_RNG is not set
+# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set
+CONFIG_KVM_COMPAT=y
+# CONFIG_HAVE_ARCH_BITREVERSE is not set
+CONFIG_RATIONAL=y
+CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
+# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_GLOB=y
+# CONFIG_GLOB_SELFTEST is not set
+CONFIG_ARCH_HAS_SG_CHAIN=y
+# CONFIG_PINMUX is not set
+# CONFIG_PAGE_TABLE_ISOLATION is not set
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000-gpu-config.cfg b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000-gpu-config.cfg
new file mode 100644
index 00000000..5b1cb049
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000-gpu-config.cfg
@@ -0,0 +1,7 @@
+CONFIG_DRM_AMDGPU=m
+CONFIG_DRM_AMDGPU_CIK=y
+CONFIG_DRM_AMDGPU_USERPTR=y
+CONFIG_HSA_AMD=y
+CONFIG_DRM_AMD_DC=y
+CONFIG_DRM_AMD_DC_DCN1_0=y
+CONFIG_SND_SOC_AMD_ACP=m
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000-standard-only.cfg b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000-standard-only.cfg
new file mode 100644
index 00000000..bfc1701d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000-standard-only.cfg
@@ -0,0 +1,3 @@
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
+CONFIG_X86_POWERNOW_K8=y
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000-user-config.cfg b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000-user-config.cfg
new file mode 100644
index 00000000..e31858d6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000-user-config.cfg
@@ -0,0 +1,196 @@
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_ACPI=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_GENERIC=m
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_SPIDEV=m
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_PIIX4=m
+CONFIG_IGB=m
+CONFIG_SENSORS_K10TEMP=m
+CONFIG_X86_MCE=y
+CONFIG_X86_MCE_AMD=y
+CONFIG_SND_USB=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_JACK=y
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
+CONFIG_SND_HDA_RECONFIG=y
+CONFIG_SND_HDA_INPUT_BEEP_MODE=1
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_NR_UARTS=16
+CONFIG_SERIAL_8250_RUNTIME_UARTS=8
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_X86_AMD_PLATFORM_DEVICE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_RCU_FAST_NO_HZ=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_THROTTLING=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_CFQ_GROUP_IOSCHED=y
+CONFIG_DEFAULT_DEADLINE=y
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_PROCESSOR_SELECT=y
+CONFIG_GART_IOMMU=y
+CONFIG_CALGARY_IOMMU=y
+CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y
+CONFIG_NR_CPUS=24
+CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
+CONFIG_X86_MCE_INJECT=m
+CONFIG_MICROCODE=y
+CONFIG_X86_MSR=m
+CONFIG_X86_CPUID=m
+CONFIG_NUMA=y
+CONFIG_AMD_NUMA=y
+CONFIG_X86_64_ACPI_NUMA=y
+CONFIG_NODES_SPAN_OTHER_NODES=y
+CONFIG_NODES_SHIFT=6
+CONFIG_ARCH_MEMORY_PROBE=y
+CONFIG_NEED_MULTIPLE_NODES=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_HAVE_BOOTMEM_INFO_NODE=y
+CONFIG_MEMORY_HOTPLUG=y
+CONFIG_MEMORY_HOTPLUG_SPARSE=y
+CONFIG_MEMORY_HOTREMOVE=y
+CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
+CONFIG_MMU_NOTIFIER=y
+CONFIG_KSM=y
+CONFIG_MEMORY_FAILURE=y
+CONFIG_CLEANCACHE=y
+CONFIG_FRONTSWAP=y
+CONFIG_KEXEC=y
+CONFIG_CRASH_DUMP=y
+CONFIG_PHYSICAL_ALIGN=0x1000000
+CONFIG_COMPAT_VDSO=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+CONFIG_ARCH_HIBERNATION_HEADER=y
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HIBERNATION=y
+CONFIG_PM_STD_PARTITION=""
+CONFIG_PM_TRACE=y
+CONFIG_PM_TRACE_RTC=y
+CONFIG_ACPI_VIDEO=m
+CONFIG_ACPI_NUMA=y
+CONFIG_ACPI_SBS=m
+CONFIG_ACPI_HED=y
+CONFIG_ACPI_BGRT=y
+CONFIG_ACPI_APEI=y
+CONFIG_ACPI_APEI_GHES=y
+CONFIG_ACPI_APEI_PCIEAER=y
+CONFIG_ACPI_APEI_MEMORY_FAILURE=y
+CONFIG_ACPI_APEI_EINJ=m
+CONFIG_ACPI_APEI_ERST_DEBUG=m
+CONFIG_SFI=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_X86_PCC_CPUFREQ=m
+CONFIG_X86_SPEEDSTEP_CENTRINO=y
+CONFIG_X86_P4_CLOCKMOD=m
+CONFIG_X86_SPEEDSTEP_LIB=m
+CONFIG_PCI_MMCONFIG=y
+CONFIG_PCI_REALLOC_ENABLE_AUTO=y
+CONFIG_PCI_STUB=m
+CONFIG_PCI_ATS=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_PRI=y
+CONFIG_PCI_PASID=y
+CONFIG_HOTPLUG_PCI_CPCI=y
+CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m
+CONFIG_HOTPLUG_PCI_SHPC=m
+CONFIG_X86_SYSFB=y
+CONFIG_NET_SCH_FQ=m
+CONFIG_ENCLOSURE_SERVICES=m
+CONFIG_EEPROM_LEGACY=m
+CONFIG_SATA_AHCI_PLATFORM=m
+CONFIG_E1000=m
+CONFIG_E1000E=m
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_IPMI_HANDLER=m
+CONFIG_HW_RANDOM_TPM=m
+CONFIG_NVRAM=m
+CONFIG_HANGCHECK_TIMER=m
+CONFIG_TCG_TPM=y
+CONFIG_GPIO_GENERIC_PLATFORM=m
+CONFIG_SENSORS_K8TEMP=m
+CONFIG_SENSORS_FAM15H_POWER=m
+CONFIG_SENSORS_ACPI_POWER=m
+CONFIG_AGP_AMD64=y
+CONFIG_VGA_SWITCHEROO=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_OHCI_HCD_PCI=m
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_MMC_SPI=m
+CONFIG_EDAC=y
+CONFIG_EDAC_LEGACY_SYSFS=y
+CONFIG_EDAC_DECODE_MCE=y
+CONFIG_EDAC_AMD64=m
+CONFIG_SYNC_FILE=y
+CONFIG_SW_SYNC=y
+CONFIG_AUXDISPLAY=y
+CONFIG_IOMMU_API=y
+CONFIG_AMD_IOMMU=y
+CONFIG_AMD_IOMMU_V2=m
+CONFIG_DMAR_TABLE=y
+CONFIG_IRQ_REMAP=y
+CONFIG_PM_DEVFREQ=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+CONFIG_MEMORY=y
+CONFIG_EDD=y
+CONFIG_EDD_OFF=y
+CONFIG_DMI_SYSFS=m
+CONFIG_EFI_VARS=y
+CONFIG_EFI_VARS_PSTORE=y
+CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
+CONFIG_EFI_RUNTIME_MAP=y
+CONFIG_UEFI_CPER=y
+CONFIG_UDF_FS=m
+CONFIG_PROC_VMCORE=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_PSTORE=y
+CONFIG_SECURITYFS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_INTERVAL_TREE=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_PINCTRL_AMD=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_SND_DESIGNWARE_I2S=m
+CONFIG_SND_SIMPLE_CARD=m
+CONFIG_GPIO_ML_IOH=m
+CONFIG_I2C_DESIGNWARE_CORE=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_DESIGNWARE_PCI=m
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_DRM_AMD_ACP=y
+CONFIG_SND_SOC=m
+CONFIG_SND_SOC_AMD_ACP3x=m
+CONFIG_FB_SIMPLE=y
+CONFIG_LOGO=y
+CONFIG_AMD_XGBE=y
+CONFIG_AMD_XGBE_DCB=y
+CONFIG_AMD_XGBE_HAVE_ECC=y
+CONFIG_DRM_I915_ALPHA_SUPPORT=y
+CONFIG_X86_BIGSMP=y
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000-user-features.scc b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000-user-features.scc
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000-user-features.scc
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000-user-patches.scc b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000-user-patches.scc
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000-user-patches.scc
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000.cfg b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000.cfg
new file mode 100644
index 00000000..9db8683e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8-v1000/v1000.cfg
@@ -0,0 +1,60 @@
+CONFIG_PRINTK=y
+
+# Basic hardware support for the box - network, USB, PCI, sound
+CONFIG_NETDEVICES=y
+CONFIG_ATA=y
+CONFIG_ATA_GENERIC=y
+CONFIG_ATA_SFF=y
+CONFIG_PCI=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PCI=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB=y
+CONFIG_R8169=y
+CONFIG_PATA_SCH=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_NET=y
+CONFIG_USB_UHCI_HCD=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+
+# Make sure these are on, otherwise the bootup won't be fun
+CONFIG_EXT3_FS=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_MODULES=y
+CONFIG_SHMEM=y
+CONFIG_TMPFS=y
+CONFIG_PACKET=y
+
+CONFIG_I2C=y
+CONFIG_AGP=y
+CONFIG_PM=y
+CONFIG_ACPI=y
+CONFIG_INPUT=y
+
+# Needed for booting (and using) USB memory sticks
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+
+CONFIG_RD_GZIP=y
+
+# Filesystems
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V4=y
+CONFIG_QFMT_V2
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+CONFIG_QUOTA_TREE=m
+CONFIG_QUOTACTL=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2941-drm-amdgpu-sort-probed-modes-before-adding-common-mo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2941-drm-amdgpu-sort-probed-modes-before-adding-common-mo.patch
new file mode 100644
index 00000000..4d055379
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2941-drm-amdgpu-sort-probed-modes-before-adding-common-mo.patch
@@ -0,0 +1,56 @@
+From 05d2fc19fb418579547802a11dd50116f690d8fc Mon Sep 17 00:00:00 2001
+From: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
+Date: Fri, 17 May 2019 15:46:58 +0530
+Subject: [PATCH 2941/4256] drm/amdgpu: sort probed modes before adding common
+ modes
+
+[Why]
+There are monitors which can have more than one preferred mode
+set. There are chances in these monitors that if common modes are
+added in function amdgpu_dm_connector_add_common_modes(), these
+common modes can be calculated with different preferred mode than
+the one used in function decide_crtc_timing_for_drm_display_mode().
+The preferred mode can be different because after common modes
+are added, the mode list is sorted and this changes the order of
+preferred modes in the list. The first mode in the list with
+preferred flag set is selected as preferred mode. Due to this the
+preferred mode selected varies.
+If same preferred mode is not selected in common mode calculation
+and crtc timing, then during mode set instead of setting preferred
+timing, common mode timing will be applied which can cause "out of
+range" message in the monitor with monitor blanking out.
+
+[How]
+Sort the modes before adding common modes. The same sorting function
+is called during common mode addition and deciding crtc timing.
+
+Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index d335b17689e4..32bad607712b 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -4910,6 +4910,15 @@ static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
+ 		amdgpu_dm_connector->num_modes =
+ 				drm_add_edid_modes(connector, edid);
+ 
++		/* sorting the probed modes before calling function
++		 * amdgpu_dm_get_native_mode() since EDID can have
++		 * more than one preferred mode. The modes that are
++		 * later in the probed mode list could be of higher
++		 * and preferred resolution. For example, 3840x2160
++		 * resolution in base EDID preferred timing and 4096x2160
++		 * preferred resolution in DID extension block later.
++		 */
++		drm_mode_sort(&connector->probed_modes);
+ 		amdgpu_dm_get_native_mode(connector);
+ 	} else {
+ 		amdgpu_dm_connector->num_modes = 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2942-drm-amdgpu-add-VCN2.5-basic-supports-1-7-patch.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2942-drm-amdgpu-add-VCN2.5-basic-supports-1-7-patch.patch
new file mode 100644
index 00000000..7fb14747
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2942-drm-amdgpu-add-VCN2.5-basic-supports-1-7-patch.patch
@@ -0,0 +1,453 @@
+From e8c05ecd25c039af735de84d52089e1bba6962e2 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Mon, 15 Apr 2019 12:21:42 -0400
+Subject: [PATCH 2942/4256] drm/amdgpu: add VCN2.5 basic supports 1/7 patch
+
+i.e. basic VCN IP SW structures
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile   |   3 +-
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 414 ++++++++++++++++++++++++++
+ 2 files changed, 416 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index 34de2df3ad9b..35998d3b60eb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -145,7 +145,8 @@ amdgpu-y += \
+ amdgpu-y += \
+ 	amdgpu_vcn.o \
+ 	vcn_v1_0.o \
+-	vcn_v2_0.o
++	vcn_v2_0.o \
++	vcn_v2_5.o
+ 
+ # add ATHUB block
+ amdgpu-y += \
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+new file mode 100644
+index 000000000000..0f553563ceb9
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -0,0 +1,414 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include <linux/firmware.h>
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "amdgpu_vcn.h"
++#include "soc15.h"
++#include "soc15d.h"
++#include "vcn_v2_0.h"
++
++#include "vcn/vcn_2_5_offset.h"
++#include "vcn/vcn_2_5_sh_mask.h"
++#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
++
++#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET			0x27
++#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET			0x0f
++#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET			0x10
++#define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET			0x11
++#define mmUVD_NO_OP_INTERNAL_OFFSET				0x29
++#define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET			0x66
++#define mmUVD_SCRATCH9_INTERNAL_OFFSET				0xc01d
++
++#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET			0x431
++#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET		0x3b4
++#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 	0x3b5
++#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET			0x25c
++
++#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET			0x401f
++
++static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
++static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
++static void vcn_v2_5_set_jpeg_ring_funcs(struct amdgpu_device *adev);
++static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
++static int vcn_v2_5_set_powergating_state(void *handle,
++				enum amd_powergating_state state);
++
++/**
++ * vcn_v2_5_early_init - set function pointers
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Set ring and irq function pointers
++ */
++static int vcn_v2_5_early_init(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++	adev->vcn.num_enc_rings = 2;
++
++	vcn_v2_5_set_dec_ring_funcs(adev);
++	vcn_v2_5_set_enc_ring_funcs(adev);
++	vcn_v2_5_set_jpeg_ring_funcs(adev);
++	vcn_v2_5_set_irq_funcs(adev);
++
++	return 0;
++}
++
++/**
++ * vcn_v2_5_sw_init - sw init for VCN block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Load firmware and sw initialization
++ */
++static int vcn_v2_5_sw_init(void *handle)
++{
++	struct amdgpu_ring *ring;
++	int i, r;
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++	/* VCN DEC TRAP */
++	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
++			VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.irq);
++	if (r)
++		return r;
++
++	/* VCN ENC TRAP */
++	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
++		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
++			i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.irq);
++		if (r)
++			return r;
++	}
++
++	/* VCN JPEG TRAP */
++	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
++			VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.irq);
++	if (r)
++		return r;
++
++	r = amdgpu_vcn_sw_init(adev);
++	if (r)
++		return r;
++
++	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
++		const struct common_firmware_header *hdr;
++		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
++		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
++		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
++		adev->firmware.fw_size +=
++			ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
++		DRM_INFO("PSP loading VCN firmware\n");
++	}
++
++	r = amdgpu_vcn_resume(adev);
++	if (r)
++		return r;
++
++	ring = &adev->vcn.ring_dec;
++	sprintf(ring->name, "vcn_dec");
++	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
++	if (r)
++		return r;
++
++	adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
++	adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
++	adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
++	adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
++	adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
++	adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
++
++	adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
++	adev->vcn.external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
++	adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
++	adev->vcn.external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
++	adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
++	adev->vcn.external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
++	adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
++	adev->vcn.external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
++	adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
++	adev->vcn.external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
++
++	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
++		ring = &adev->vcn.ring_enc[i];
++		sprintf(ring->name, "vcn_enc%d", i);
++		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
++		if (r)
++			return r;
++	}
++
++	ring = &adev->vcn.ring_jpeg;
++	sprintf(ring->name, "vcn_jpeg");
++	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
++	if (r)
++		return r;
++
++	adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
++	adev->vcn.external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
++
++	return 0;
++}
++
++/**
++ * vcn_v2_5_sw_fini - sw fini for VCN block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * VCN suspend and free up sw allocation
++ */
++static int vcn_v2_5_sw_fini(void *handle)
++{
++	int r;
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++	r = amdgpu_vcn_suspend(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_vcn_sw_fini(adev);
++
++	return r;
++}
++
++/**
++ * vcn_v2_5_hw_init - start and test VCN block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Initialize the hardware, boot up the VCPU and do some testing
++ */
++static int vcn_v2_5_hw_init(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
++	int i, r;
++
++	r = amdgpu_ring_test_ring(ring);
++	if (r) {
++		ring->sched.ready = false;
++		goto done;
++	}
++
++	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
++		ring = &adev->vcn.ring_enc[i];
++		ring->sched.ready = false;
++		continue;
++		r = amdgpu_ring_test_ring(ring);
++		if (r) {
++			ring->sched.ready = false;
++			goto done;
++		}
++	}
++
++	ring = &adev->vcn.ring_jpeg;
++	r = amdgpu_ring_test_ring(ring);
++	if (r) {
++		ring->sched.ready = false;
++		goto done;
++	}
++
++done:
++	if (!r)
++		DRM_INFO("VCN decode and encode initialized successfully.\n");
++
++	return r;
++}
++
++/**
++ * vcn_v2_5_hw_fini - stop the hardware block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Stop the VCN block, mark ring as not ready any more
++ */
++static int vcn_v2_5_hw_fini(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
++	int i;
++
++	if (RREG32_SOC15(VCN, 0, mmUVD_STATUS))
++		vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
++
++	ring->sched.ready = false;
++
++	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
++		ring = &adev->vcn.ring_enc[i];
++		ring->sched.ready = false;
++	}
++
++	ring = &adev->vcn.ring_jpeg;
++	ring->sched.ready = false;
++
++	return 0;
++}
++
++/**
++ * vcn_v2_5_suspend - suspend VCN block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * HW fini and suspend VCN block
++ */
++static int vcn_v2_5_suspend(void *handle)
++{
++	int r;
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++	r = vcn_v2_5_hw_fini(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_vcn_suspend(adev);
++
++	return r;
++}
++
++/**
++ * vcn_v2_5_resume - resume VCN block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Resume firmware and hw init VCN block
++ */
++static int vcn_v2_5_resume(void *handle)
++{
++	int r;
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++	r = amdgpu_vcn_resume(adev);
++	if (r)
++		return r;
++
++	r = vcn_v2_5_hw_init(adev);
++
++	return r;
++}
++
++static bool vcn_v2_5_is_idle(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++	return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
++}
++
++static int vcn_v2_5_wait_for_idle(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	int ret = 0;
++
++	SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
++		UVD_STATUS__IDLE, ret);
++
++	return ret;
++}
++
++static int vcn_v2_5_set_clockgating_state(void *handle,
++					  enum amd_clockgating_state state)
++{
++	return 0;
++}
++
++static int vcn_v2_5_set_powergating_state(void *handle,
++					  enum amd_powergating_state state)
++{
++	return 0;
++}
++
++static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev,
++					struct amdgpu_irq_src *source,
++					unsigned type,
++					enum amdgpu_interrupt_state state)
++{
++	return 0;
++}
++
++static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev,
++				      struct amdgpu_irq_src *source,
++				      struct amdgpu_iv_entry *entry)
++{
++	DRM_DEBUG("IH: VCN TRAP\n");
++
++	switch (entry->src_id) {
++	case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
++		amdgpu_fence_process(&adev->vcn.ring_dec);
++		break;
++	case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
++		amdgpu_fence_process(&adev->vcn.ring_enc[0]);
++		break;
++	case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
++		amdgpu_fence_process(&adev->vcn.ring_enc[1]);
++		break;
++	case VCN_2_0__SRCID__JPEG_DECODE:
++		amdgpu_fence_process(&adev->vcn.ring_jpeg);
++		break;
++	default:
++		DRM_ERROR("Unhandled interrupt: %d %d\n",
++			  entry->src_id, entry->src_data[0]);
++		break;
++	}
++
++	return 0;
++}
++
++static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = {
++	.set = vcn_v2_5_set_interrupt_state,
++	.process = vcn_v2_5_process_interrupt,
++};
++
++static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2;
++	adev->vcn.irq.funcs = &vcn_v2_5_irq_funcs;
++}
++
++static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
++	.name = "vcn_v2_5",
++	.early_init = vcn_v2_5_early_init,
++	.late_init = NULL,
++	.sw_init = vcn_v2_5_sw_init,
++	.sw_fini = vcn_v2_5_sw_fini,
++	.hw_init = vcn_v2_5_hw_init,
++	.hw_fini = vcn_v2_5_hw_fini,
++	.suspend = vcn_v2_5_suspend,
++	.resume = vcn_v2_5_resume,
++	.is_idle = vcn_v2_5_is_idle,
++	.wait_for_idle = vcn_v2_5_wait_for_idle,
++	.check_soft_reset = NULL,
++	.pre_soft_reset = NULL,
++	.soft_reset = NULL,
++	.post_soft_reset = NULL,
++	.set_clockgating_state = vcn_v2_5_set_clockgating_state,
++	.set_powergating_state = vcn_v2_5_set_powergating_state,
++};
++
++const struct amdgpu_ip_block_version vcn_v2_5_ip_block =
++{
++		.type = AMD_IP_BLOCK_TYPE_VCN,
++		.major = 2,
++		.minor = 5,
++		.rev = 0,
++		.funcs = &vcn_v2_5_ip_funcs,
++};
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2943-drm-amdgpu-add-VCN2.5-VCPU-start-and-stop-2-7-patch.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2943-drm-amdgpu-add-VCN2.5-VCPU-start-and-stop-2-7-patch.patch
new file mode 100644
index 00000000..cb792cfa
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2943-drm-amdgpu-add-VCN2.5-VCPU-start-and-stop-2-7-patch.patch
@@ -0,0 +1,509 @@
+From bf87a480b2c9a253abbd2ccd0e09b1654653a902 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Mon, 15 Apr 2019 12:41:09 -0400
+Subject: [PATCH 2943/4256] drm/amdgpu: add VCN2.5 VCPU start and stop 2/7
+ patch
+
+HW engine initialization and suspend sequences.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 467 +++++++++++++++++++++++++-
+ 1 file changed, 466 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index 0f553563ceb9..b6e72fff94f5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -307,6 +307,446 @@ static int vcn_v2_5_resume(void *handle)
+ 	return r;
+ }
+ 
++/**
++ * vcn_v2_5_mc_resume - memory controller programming
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Let the VCN memory controller know it's offsets
++ */
++static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
++{
++	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
++	uint32_t offset;
++
++	/* cache window 0: fw */
++	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
++		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
++			(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
++		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
++			(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
++		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
++		offset = 0;
++	} else {
++		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
++			lower_32_bits(adev->vcn.gpu_addr));
++		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
++			upper_32_bits(adev->vcn.gpu_addr));
++		offset = size;
++		/* No signed header for now from firmware
++		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
++			AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
++		*/
++		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
++	}
++	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
++
++	/* cache window 1: stack */
++	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
++		lower_32_bits(adev->vcn.gpu_addr + offset));
++	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
++		upper_32_bits(adev->vcn.gpu_addr + offset));
++	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
++	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
++
++	/* cache window 2: context */
++	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
++		lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
++	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
++		upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
++	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
++	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
++}
++
++/**
++ * vcn_v2_5_disable_clock_gating - disable VCN clock gating
++ *
++ * @adev: amdgpu_device pointer
++ * @sw: enable SW clock gating
++ *
++ * Disable clock gating for VCN block
++ */
++static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
++{
++	uint32_t data;
++	int ret = 0;
++
++	/* UVD disable CGC */
++	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
++	if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
++		data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++	else
++		data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
++	data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
++	data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
++	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
++
++	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
++	data &= ~(UVD_CGC_GATE__SYS_MASK
++		| UVD_CGC_GATE__UDEC_MASK
++		| UVD_CGC_GATE__MPEG2_MASK
++		| UVD_CGC_GATE__REGS_MASK
++		| UVD_CGC_GATE__RBC_MASK
++		| UVD_CGC_GATE__LMI_MC_MASK
++		| UVD_CGC_GATE__LMI_UMC_MASK
++		| UVD_CGC_GATE__IDCT_MASK
++		| UVD_CGC_GATE__MPRD_MASK
++		| UVD_CGC_GATE__MPC_MASK
++		| UVD_CGC_GATE__LBSI_MASK
++		| UVD_CGC_GATE__LRBBM_MASK
++		| UVD_CGC_GATE__UDEC_RE_MASK
++		| UVD_CGC_GATE__UDEC_CM_MASK
++		| UVD_CGC_GATE__UDEC_IT_MASK
++		| UVD_CGC_GATE__UDEC_DB_MASK
++		| UVD_CGC_GATE__UDEC_MP_MASK
++		| UVD_CGC_GATE__WCB_MASK
++		| UVD_CGC_GATE__VCPU_MASK
++		| UVD_CGC_GATE__MMSCH_MASK);
++
++	WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
++
++	SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_CGC_GATE, 0,  0xFFFFFFFF, ret);
++
++	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
++	data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
++		| UVD_CGC_CTRL__UDEC_CM_MODE_MASK
++		| UVD_CGC_CTRL__UDEC_IT_MODE_MASK
++		| UVD_CGC_CTRL__UDEC_DB_MODE_MASK
++		| UVD_CGC_CTRL__UDEC_MP_MODE_MASK
++		| UVD_CGC_CTRL__SYS_MODE_MASK
++		| UVD_CGC_CTRL__UDEC_MODE_MASK
++		| UVD_CGC_CTRL__MPEG2_MODE_MASK
++		| UVD_CGC_CTRL__REGS_MODE_MASK
++		| UVD_CGC_CTRL__RBC_MODE_MASK
++		| UVD_CGC_CTRL__LMI_MC_MODE_MASK
++		| UVD_CGC_CTRL__LMI_UMC_MODE_MASK
++		| UVD_CGC_CTRL__IDCT_MODE_MASK
++		| UVD_CGC_CTRL__MPRD_MODE_MASK
++		| UVD_CGC_CTRL__MPC_MODE_MASK
++		| UVD_CGC_CTRL__LBSI_MODE_MASK
++		| UVD_CGC_CTRL__LRBBM_MODE_MASK
++		| UVD_CGC_CTRL__WCB_MODE_MASK
++		| UVD_CGC_CTRL__VCPU_MODE_MASK
++		| UVD_CGC_CTRL__MMSCH_MODE_MASK);
++	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
++
++	/* turn on */
++	data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
++	data |= (UVD_SUVD_CGC_GATE__SRE_MASK
++		| UVD_SUVD_CGC_GATE__SIT_MASK
++		| UVD_SUVD_CGC_GATE__SMP_MASK
++		| UVD_SUVD_CGC_GATE__SCM_MASK
++		| UVD_SUVD_CGC_GATE__SDB_MASK
++		| UVD_SUVD_CGC_GATE__SRE_H264_MASK
++		| UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
++		| UVD_SUVD_CGC_GATE__SIT_H264_MASK
++		| UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
++		| UVD_SUVD_CGC_GATE__SCM_H264_MASK
++		| UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
++		| UVD_SUVD_CGC_GATE__SDB_H264_MASK
++		| UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
++		| UVD_SUVD_CGC_GATE__SCLR_MASK
++		| UVD_SUVD_CGC_GATE__UVD_SC_MASK
++		| UVD_SUVD_CGC_GATE__ENT_MASK
++		| UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
++		| UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
++		| UVD_SUVD_CGC_GATE__SITE_MASK
++		| UVD_SUVD_CGC_GATE__SRE_VP9_MASK
++		| UVD_SUVD_CGC_GATE__SCM_VP9_MASK
++		| UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
++		| UVD_SUVD_CGC_GATE__SDB_VP9_MASK
++		| UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
++	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
++
++	data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
++	data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
++		| UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
++		| UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
++		| UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
++		| UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
++		| UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
++		| UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
++		| UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
++		| UVD_SUVD_CGC_CTRL__IME_MODE_MASK
++		| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
++	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
++}
++
++/**
++ * vcn_v2_5_enable_clock_gating - enable VCN clock gating
++ *
++ * @adev: amdgpu_device pointer
++ * @sw: enable SW clock gating
++ *
++ * Enable clock gating for VCN block
++ */
++static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
++{
++	uint32_t data = 0;
++
++	/* enable UVD CGC */
++	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
++	if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
++		data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++	else
++		data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++	data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
++	data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
++	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
++
++	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
++	data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
++		| UVD_CGC_CTRL__UDEC_CM_MODE_MASK
++		| UVD_CGC_CTRL__UDEC_IT_MODE_MASK
++		| UVD_CGC_CTRL__UDEC_DB_MODE_MASK
++		| UVD_CGC_CTRL__UDEC_MP_MODE_MASK
++		| UVD_CGC_CTRL__SYS_MODE_MASK
++		| UVD_CGC_CTRL__UDEC_MODE_MASK
++		| UVD_CGC_CTRL__MPEG2_MODE_MASK
++		| UVD_CGC_CTRL__REGS_MODE_MASK
++		| UVD_CGC_CTRL__RBC_MODE_MASK
++		| UVD_CGC_CTRL__LMI_MC_MODE_MASK
++		| UVD_CGC_CTRL__LMI_UMC_MODE_MASK
++		| UVD_CGC_CTRL__IDCT_MODE_MASK
++		| UVD_CGC_CTRL__MPRD_MODE_MASK
++		| UVD_CGC_CTRL__MPC_MODE_MASK
++		| UVD_CGC_CTRL__LBSI_MODE_MASK
++		| UVD_CGC_CTRL__LRBBM_MODE_MASK
++		| UVD_CGC_CTRL__WCB_MODE_MASK
++		| UVD_CGC_CTRL__VCPU_MODE_MASK);
++	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
++
++	data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
++	data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
++		| UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
++		| UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
++		| UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
++		| UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
++		| UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
++		| UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
++		| UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
++		| UVD_SUVD_CGC_CTRL__IME_MODE_MASK
++		| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
++	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
++}
++
++static int vcn_v2_5_start(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
++	uint32_t rb_bufsz, tmp;
++	int i, j, r;
++
++	/* disable register anti-hang mechanism */
++	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
++		~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
++
++	/* set uvd status busy */
++	tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
++	WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
++
++	/*SW clock gating */
++	vcn_v2_5_disable_clock_gating(adev);
++
++	/* enable VCPU clock */
++	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
++		UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
++
++	/* disable master interrupt */
++	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
++		~UVD_MASTINT_EN__VCPU_EN_MASK);
++
++	/* setup mmUVD_LMI_CTRL */
++	tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
++	tmp &= ~0xff;
++	WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 0x8|
++		UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK	|
++		UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
++		UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
++		UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
++
++	/* setup mmUVD_MPC_CNTL */
++	tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
++	tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
++	tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
++	WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp);
++
++	/* setup UVD_MPC_SET_MUXA0 */
++	WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
++		((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
++		(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
++		(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
++		(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
++
++	/* setup UVD_MPC_SET_MUXB0 */
++	WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
++		((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
++		(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
++		(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
++		(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
++
++	/* setup mmUVD_MPC_SET_MUX */
++	WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
++		((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
++		(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
++		(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
++
++	vcn_v2_5_mc_resume(adev);
++
++	/* VCN global tiling registers */
++	WREG32_SOC15(UVD, 0, mmUVD_GFX8_ADDR_CONFIG,
++		adev->gfx.config.gb_addr_config);
++	WREG32_SOC15(UVD, 0, mmUVD_GFX8_ADDR_CONFIG,
++		adev->gfx.config.gb_addr_config);
++
++	/* enable LMI MC and UMC channels */
++	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
++		~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
++
++	/* unblock VCPU register access */
++	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_ARB_CTRL), 0,
++		~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
++
++	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
++		~UVD_VCPU_CNTL__BLK_RST_MASK);
++
++	for (i = 0; i < 10; ++i) {
++		uint32_t status;
++
++		for (j = 0; j < 100; ++j) {
++			status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
++			if (status & 2)
++				break;
++			if (amdgpu_emu_mode == 1)
++				msleep(500);
++			else
++				mdelay(10);
++		}
++		r = 0;
++		if (status & 2)
++			break;
++
++		DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
++		WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
++			UVD_VCPU_CNTL__BLK_RST_MASK,
++			~UVD_VCPU_CNTL__BLK_RST_MASK);
++		mdelay(10);
++		WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
++			~UVD_VCPU_CNTL__BLK_RST_MASK);
++
++		mdelay(10);
++		r = -1;
++	}
++
++	if (r) {
++		DRM_ERROR("VCN decode not responding, giving up!!!\n");
++		return r;
++	}
++
++	/* enable master interrupt */
++	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
++		UVD_MASTINT_EN__VCPU_EN_MASK,
++		~UVD_MASTINT_EN__VCPU_EN_MASK);
++
++	/* clear the busy bit of VCN_STATUS */
++	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
++		~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
++
++	WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0);
++
++	/* force RBC into idle state */
++	rb_bufsz = order_base_2(ring->ring_size);
++	tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
++	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
++	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
++	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
++	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
++	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
++
++	/* programm the RB_BASE for ring buffer */
++	WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
++		lower_32_bits(ring->gpu_addr));
++	WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
++		upper_32_bits(ring->gpu_addr));
++
++	/* Initialize the ring buffer's read and write pointers */
++	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
++
++	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
++	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
++			lower_32_bits(ring->wptr));
++	ring = &adev->vcn.ring_enc[0];
++	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
++	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
++	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
++	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
++	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
++
++	ring = &adev->vcn.ring_enc[1];
++	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
++	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
++	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
++	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
++	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
++
++	return r;
++}
++
++static int vcn_v2_5_stop(struct amdgpu_device *adev)
++{
++	uint32_t tmp;
++	int r;
++
++	/* wait for vcn idle */
++	SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
++	if (r)
++		return r;
++
++	tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
++		UVD_LMI_STATUS__READ_CLEAN_MASK |
++		UVD_LMI_STATUS__WRITE_CLEAN_MASK |
++		UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
++	SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
++	if (r)
++		return r;
++
++	/* block LMI UMC channel */
++	tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);
++	tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
++	WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp);
++
++	tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
++		UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
++	SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
++	if (r)
++		return r;
++
++	/* block VCPU register access */
++	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_ARB_CTRL),
++		UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
++		~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
++
++	/* reset VCPU */
++	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
++		UVD_VCPU_CNTL__BLK_RST_MASK,
++		~UVD_VCPU_CNTL__BLK_RST_MASK);
++
++	/* disable VCPU clock */
++	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
++		~(UVD_VCPU_CNTL__CLK_EN_MASK));
++
++	/* clear status */
++	WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
++
++	vcn_v2_5_enable_clock_gating(adev);
++
++	/* enable register anti-hang mechanism */
++	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
++		UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,
++		~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
++
++	return 0;
++}
++
+ static bool vcn_v2_5_is_idle(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+@@ -328,13 +768,38 @@ static int vcn_v2_5_wait_for_idle(void *handle)
+ static int vcn_v2_5_set_clockgating_state(void *handle,
+ 					  enum amd_clockgating_state state)
+ {
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
++
++	if (enable) {
++		if (vcn_v2_5_is_idle(handle))
++			return -EBUSY;
++		vcn_v2_5_enable_clock_gating(adev);
++	} else {
++		vcn_v2_5_disable_clock_gating(adev);
++	}
++
+ 	return 0;
+ }
+ 
+ static int vcn_v2_5_set_powergating_state(void *handle,
+ 					  enum amd_powergating_state state)
+ {
+-	return 0;
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	int ret;
++
++	if(state == adev->vcn.cur_state)
++		return 0;
++
++	if (state == AMD_PG_STATE_GATE)
++		ret = vcn_v2_5_stop(adev);
++	else
++		ret = vcn_v2_5_start(adev);
++
++	if(!ret)
++		adev->vcn.cur_state = state;
++
++	return ret;
+ }
+ 
+ static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2944-drm-amdgpu-add-Arcturus-to-the-VCN-family-3-7-patch.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2944-drm-amdgpu-add-Arcturus-to-the-VCN-family-3-7-patch.patch
new file mode 100644
index 00000000..a9306ce5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2944-drm-amdgpu-add-Arcturus-to-the-VCN-family-3-7-patch.patch
@@ -0,0 +1,47 @@
+From a01697b7ccb7ed4ab4ac2400a57a0316fcdfb4ca Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Tue, 9 Jul 2019 10:09:06 -0500
+Subject: [PATCH 2944/4256] drm/amdgpu: add Arcturus to the VCN family 3/7
+ patch
+
+including firmware support etc.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+index 8a162bdad79e..bb0d1ef50c9c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+@@ -45,12 +45,14 @@
+ #define FIRMWARE_RAVEN		"amdgpu/raven_vcn.bin"
+ #define FIRMWARE_PICASSO	"amdgpu/picasso_vcn.bin"
+ #define FIRMWARE_RAVEN2		"amdgpu/raven2_vcn.bin"
++#define FIRMWARE_ARCTURUS 	"amdgpu/arcturus_vcn.bin"
+ #define FIRMWARE_NAVI10 	"amdgpu/navi10_vcn.bin"
+ #define FIRMWARE_NAVI14 	"amdgpu/navi14_vcn.bin"
+ 
+ MODULE_FIRMWARE(FIRMWARE_RAVEN);
+ MODULE_FIRMWARE(FIRMWARE_PICASSO);
+ MODULE_FIRMWARE(FIRMWARE_RAVEN2);
++MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
+ MODULE_FIRMWARE(FIRMWARE_NAVI10);
+ MODULE_FIRMWARE(FIRMWARE_NAVI14);
+ 
+@@ -75,6 +77,9 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
+ 		else
+ 			fw_name = FIRMWARE_RAVEN;
+ 		break;
++	case CHIP_ARCTURUS:
++		fw_name = FIRMWARE_ARCTURUS;
++		break;
+ 	case CHIP_NAVI10:
+ 		fw_name = FIRMWARE_NAVI10;
+ 		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2945-drm-amdgpu-VCN2.5-set-decode-ring-functions-4-7-patc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2945-drm-amdgpu-VCN2.5-set-decode-ring-functions-4-7-patc.patch
new file mode 100644
index 00000000..0e2dc989
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2945-drm-amdgpu-VCN2.5-set-decode-ring-functions-4-7-patc.patch
@@ -0,0 +1,107 @@
+From 8f2e04b1df88018eab09dd49e85c5d73fa412ef1 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Tue, 16 Apr 2019 11:17:46 -0400
+Subject: [PATCH 2945/4256] drm/amdgpu/VCN2.5: set decode ring functions 4/7
+ patch
+
+Also reuse most of the VCN2.0 decode ring functions
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 78 +++++++++++++++++++++++++++
+ 1 file changed, 78 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index b6e72fff94f5..f16a4f682e26 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -747,6 +747,84 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
++/**
++ * vcn_v2_5_dec_ring_get_rptr - get read pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware read pointer
++ */
++static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
++}
++
++/**
++ * vcn_v2_5_dec_ring_get_wptr - get write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware write pointer
++ */
++static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
++}
++
++/**
++ * vcn_v2_5_dec_ring_set_wptr - set write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Commits the write pointer to the hardware
++ */
++static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
++}
++
++static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
++	.type = AMDGPU_RING_TYPE_VCN_DEC,
++	.align_mask = 0xf,
++	.vmhub = AMDGPU_MMHUB_1,
++	.get_rptr = vcn_v2_5_dec_ring_get_rptr,
++	.get_wptr = vcn_v2_5_dec_ring_get_wptr,
++	.set_wptr = vcn_v2_5_dec_ring_set_wptr,
++	.emit_frame_size =
++		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
++		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
++		8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
++		14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
++		6,
++	.emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
++	.emit_ib = vcn_v2_0_dec_ring_emit_ib,
++	.emit_fence = vcn_v2_0_dec_ring_emit_fence,
++	.emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
++	.test_ring = amdgpu_vcn_dec_ring_test_ring,
++	.test_ib = amdgpu_vcn_dec_ring_test_ib,
++	.insert_nop = vcn_v2_0_dec_ring_insert_nop,
++	.insert_start = vcn_v2_0_dec_ring_insert_start,
++	.insert_end = vcn_v2_0_dec_ring_insert_end,
++	.pad_ib = amdgpu_ring_generic_pad_ib,
++	.begin_use = amdgpu_vcn_ring_begin_use,
++	.end_use = amdgpu_vcn_ring_end_use,
++	.emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
++	.emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
++	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
++};
++
++static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
++{
++	adev->vcn.ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
++	DRM_INFO("VCN decode is enabled in VM mode\n");
++}
++
+ static bool vcn_v2_5_is_idle(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2946-drm-amdgpu-VCN2.5-set-encode-ring-functions-5-7-patc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2946-drm-amdgpu-VCN2.5-set-encode-ring-functions-5-7-patc.patch
new file mode 100644
index 00000000..bb55d5c9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2946-drm-amdgpu-VCN2.5-set-encode-ring-functions-5-7-patc.patch
@@ -0,0 +1,126 @@
+From 392421e850c2c095d1d6aabbcf2b408c376d3100 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Mon, 22 Apr 2019 12:17:38 -0400
+Subject: [PATCH 2946/4256] drm/amdgpu/VCN2.5: set encode ring functions 5/7
+ patch
+
+Also reuse most of the VCN2.0 encode ring functions
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 91 +++++++++++++++++++++++++++
+ 1 file changed, 91 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index f16a4f682e26..b42f6769ae06 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -819,12 +819,103 @@ static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
+ 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ };
+ 
++/**
++ * vcn_v2_5_enc_ring_get_rptr - get enc read pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware enc read pointer
++ */
++static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	if (ring == &adev->vcn.ring_enc[0])
++		return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
++	else
++		return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
++}
++
++/**
++ * vcn_v2_5_enc_ring_get_wptr - get enc write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware enc write pointer
++ */
++static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	if (ring == &adev->vcn.ring_enc[0])
++		return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
++	else
++		return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
++}
++
++/**
++ * vcn_v2_5_enc_ring_set_wptr - set enc write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Commits the enc write pointer to the hardware
++ */
++static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	if (ring == &adev->vcn.ring_enc[0])
++		WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
++	else
++		WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
++}
++
++static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = {
++	.type = AMDGPU_RING_TYPE_VCN_ENC,
++	.align_mask = 0x3f,
++	.nop = VCN_ENC_CMD_NO_OP,
++	.vmhub = AMDGPU_MMHUB_1,
++	.get_rptr = vcn_v2_5_enc_ring_get_rptr,
++	.get_wptr = vcn_v2_5_enc_ring_get_wptr,
++	.set_wptr = vcn_v2_5_enc_ring_set_wptr,
++	.emit_frame_size =
++		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
++		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
++		4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
++		5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
++		1, /* vcn_v2_0_enc_ring_insert_end */
++	.emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
++	.emit_ib = vcn_v2_0_enc_ring_emit_ib,
++	.emit_fence = vcn_v2_0_enc_ring_emit_fence,
++	.emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
++	.test_ring = amdgpu_vcn_enc_ring_test_ring,
++	.test_ib = amdgpu_vcn_enc_ring_test_ib,
++	.insert_nop = amdgpu_ring_insert_nop,
++	.insert_end = vcn_v2_0_enc_ring_insert_end,
++	.pad_ib = amdgpu_ring_generic_pad_ib,
++	.begin_use = amdgpu_vcn_ring_begin_use,
++	.end_use = amdgpu_vcn_ring_end_use,
++	.emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
++	.emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
++	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
++};
++
+ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
+ {
+ 	adev->vcn.ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
+ 	DRM_INFO("VCN decode is enabled in VM mode\n");
+ }
+ 
++static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < adev->vcn.num_enc_rings; ++i)
++		adev->vcn.ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
++
++	DRM_INFO("VCN encode is enabled in VM mode\n");
++}
++
+ static bool vcn_v2_5_is_idle(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2947-drm-amdgpu-add-JPEG2.5-HW-start-and-stop-6-7-patch.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2947-drm-amdgpu-add-JPEG2.5-HW-start-and-stop-6-7-patch.patch
new file mode 100644
index 00000000..19425b89
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2947-drm-amdgpu-add-JPEG2.5-HW-start-and-stop-6-7-patch.patch
@@ -0,0 +1,146 @@
+From 3446f4b29d2e6dbc4886bb6e09f382282679e5da Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Tue, 16 Apr 2019 11:32:22 -0400
+Subject: [PATCH 2947/4256] drm/amdgpu: add JPEG2.5 HW start and stop 6/7 patch
+
+JPEG engine initialization and suspend sequences
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 104 ++++++++++++++++++++++++++
+ 1 file changed, 104 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index b42f6769ae06..82c9c40e9ae4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -530,6 +530,104 @@ static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
+ 	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
+ }
+ 
++/**
++ * jpeg_v2_5_start - start JPEG block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Setup and start the JPEG block
++ */
++static int jpeg_v2_5_start(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring = &adev->vcn.ring_jpeg;
++	uint32_t tmp;
++
++	/* disable anti hang mechanism */
++	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), 0,
++		~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
++
++	/* JPEG disable CGC */
++	tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
++	tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++	tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
++	tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
++	WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp);
++
++	tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
++	tmp &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
++		| JPEG_CGC_GATE__JPEG2_DEC_MASK
++		| JPEG_CGC_GATE__JMCIF_MASK
++		| JPEG_CGC_GATE__JRBBM_MASK);
++	WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp);
++
++	tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
++	tmp &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
++		| JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
++		| JPEG_CGC_CTRL__JMCIF_MODE_MASK
++		| JPEG_CGC_CTRL__JRBBM_MODE_MASK);
++	WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp);
++
++	/* MJPEG global tiling registers */
++	WREG32_SOC15(UVD, 0, mmJPEG_DEC_GFX8_ADDR_CONFIG,
++		adev->gfx.config.gb_addr_config);
++	WREG32_SOC15(UVD, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG,
++		adev->gfx.config.gb_addr_config);
++
++	/* enable JMI channel */
++	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL), 0,
++		~UVD_JMI_CNTL__SOFT_RESET_MASK);
++
++	/* enable System Interrupt for JRBC */
++	WREG32_P(SOC15_REG_OFFSET(VCN, 0, mmJPEG_SYS_INT_EN),
++		JPEG_SYS_INT_EN__DJRBC_MASK,
++		~JPEG_SYS_INT_EN__DJRBC_MASK);
++
++	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
++	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
++	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
++		lower_32_bits(ring->gpu_addr));
++	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
++		upper_32_bits(ring->gpu_addr));
++	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
++	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
++	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
++	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
++	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
++
++	return 0;
++}
++
++/**
++ * jpeg_v2_5_stop - stop JPEG block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * stop the JPEG block
++ */
++static int jpeg_v2_5_stop(struct amdgpu_device *adev)
++{
++	uint32_t tmp;
++
++	/* reset JMI */
++	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL),
++		UVD_JMI_CNTL__SOFT_RESET_MASK,
++		~UVD_JMI_CNTL__SOFT_RESET_MASK);
++
++	tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
++	tmp |= (JPEG_CGC_GATE__JPEG_DEC_MASK
++		|JPEG_CGC_GATE__JPEG2_DEC_MASK
++		|JPEG_CGC_GATE__JMCIF_MASK
++		|JPEG_CGC_GATE__JRBBM_MASK);
++	WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp);
++
++	/* enable anti hang mechanism */
++	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS),
++		UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
++		~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
++
++	return 0;
++}
++
+ static int vcn_v2_5_start(struct amdgpu_device *adev)
+ {
+ 	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
+@@ -688,6 +786,8 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
+ 
++	r = jpeg_v2_5_start(adev);
++
+ 	return r;
+ }
+ 
+@@ -696,6 +796,10 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev)
+ 	uint32_t tmp;
+ 	int r;
+ 
++	r = jpeg_v2_5_stop(adev);
++	if (r)
++		return r;
++
+ 	/* wait for vcn idle */
+ 	SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
+ 	if (r)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2948-drm-amdgpu-VCN2.5-set-JPEG-decode-ring-functions-7-7.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2948-drm-amdgpu-VCN2.5-set-JPEG-decode-ring-functions-7-7.patch
new file mode 100644
index 00000000..ad47f22f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2948-drm-amdgpu-VCN2.5-set-JPEG-decode-ring-functions-7-7.patch
@@ -0,0 +1,114 @@
+From 3b7f4ae48179f4185c4cc0d083f3c2217406203b Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Mon, 22 Apr 2019 12:21:16 -0400
+Subject: [PATCH 2948/4256] drm/amdgpu/VCN2.5: set JPEG decode ring functions
+ 7/7 patch
+
+Also reuse most of the JPEG2.0 decode ring functions
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 78 +++++++++++++++++++++++++++
+ 1 file changed, 78 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index 82c9c40e9ae4..0ffc0d60fad8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -1004,6 +1004,78 @@ static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = {
+ 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ };
+ 
++/**
++ * vcn_v2_5_jpeg_ring_get_rptr - get read pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware read pointer
++ */
++static uint64_t vcn_v2_5_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
++}
++
++/**
++ * vcn_v2_5_jpeg_ring_get_wptr - get write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware write pointer
++ */
++static uint64_t vcn_v2_5_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
++}
++
++/**
++ * vcn_v2_5_jpeg_ring_set_wptr - set write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Commits the write pointer to the hardware
++ */
++static void vcn_v2_5_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
++}
++
++static const struct amdgpu_ring_funcs vcn_v2_5_jpeg_ring_vm_funcs = {
++	.type = AMDGPU_RING_TYPE_VCN_JPEG,
++	.align_mask = 0xf,
++	.vmhub = AMDGPU_MMHUB_1,
++	.get_rptr = vcn_v2_5_jpeg_ring_get_rptr,
++	.get_wptr = vcn_v2_5_jpeg_ring_get_wptr,
++	.set_wptr = vcn_v2_5_jpeg_ring_set_wptr,
++	.emit_frame_size =
++		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
++		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
++		8 + /* vcn_v2_0_jpeg_ring_emit_vm_flush */
++		18 + 18 + /* vcn_v2_0_jpeg_ring_emit_fence x2 vm fence */
++		8 + 16,
++	.emit_ib_size = 22, /* vcn_v2_0_jpeg_ring_emit_ib */
++	.emit_ib = vcn_v2_0_jpeg_ring_emit_ib,
++	.emit_fence = vcn_v2_0_jpeg_ring_emit_fence,
++	.emit_vm_flush = vcn_v2_0_jpeg_ring_emit_vm_flush,
++	.test_ring = amdgpu_vcn_jpeg_ring_test_ring,
++	.test_ib = amdgpu_vcn_jpeg_ring_test_ib,
++	.insert_nop = vcn_v2_0_jpeg_ring_nop,
++	.insert_start = vcn_v2_0_jpeg_ring_insert_start,
++	.insert_end = vcn_v2_0_jpeg_ring_insert_end,
++	.pad_ib = amdgpu_ring_generic_pad_ib,
++	.begin_use = amdgpu_vcn_ring_begin_use,
++	.end_use = amdgpu_vcn_ring_end_use,
++	.emit_wreg = vcn_v2_0_jpeg_ring_emit_wreg,
++	.emit_reg_wait = vcn_v2_0_jpeg_ring_emit_reg_wait,
++	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
++};
++
+ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
+ {
+ 	adev->vcn.ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
+@@ -1020,6 +1092,12 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
+ 	DRM_INFO("VCN encode is enabled in VM mode\n");
+ }
+ 
++static void vcn_v2_5_set_jpeg_ring_funcs(struct amdgpu_device *adev)
++{
++	adev->vcn.ring_jpeg.funcs = &vcn_v2_5_jpeg_ring_vm_funcs;
++	DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
++}
++
+ static bool vcn_v2_5_is_idle(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2949-drm-amdgpu-enable-VCN2.5-on-Arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2949-drm-amdgpu-enable-VCN2.5-on-Arcturus.patch
new file mode 100644
index 00000000..ceb61a55
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2949-drm-amdgpu-enable-VCN2.5-on-Arcturus.patch
@@ -0,0 +1,74 @@
+From 80950ab594b8726c76742bb5d352debc967eb440 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Tue, 16 Apr 2019 11:42:56 -0400
+Subject: [PATCH 2949/4256] drm/amdgpu: enable VCN2.5 on Arcturus
+
+VCN is the video decode and encode engine on Arcturus
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c    |  2 ++
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h | 29 +++++++++++++++++++++++++++
+ 2 files changed, 31 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index fb4c7aac8d9e..217afe23a2f6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -62,6 +62,7 @@
+ #include "uvd_v7_0.h"
+ #include "vce_v4_0.h"
+ #include "vcn_v1_0.h"
++#include "vcn_v2_5.h"
+ #include "dce_virtual.h"
+ #include "mxgpu_ai.h"
+ #include "amdgpu_smu.h"
+@@ -683,6 +684,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
++		amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
+ 		break;
+ 	default:
+ 		return -EINVAL;
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h
+new file mode 100644
+index 000000000000..8d9c0800b8e0
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __VCN_V2_5_H__
++#define __VCN_V2_5_H__
++
++extern const struct amdgpu_ip_block_version vcn_v2_5_ip_block;
++
++#endif /* __VCN_V2_5_H__ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2950-drm-amdgpu-add-vcn-doorbell-range-function-to-nbio7..patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2950-drm-amdgpu-add-vcn-doorbell-range-function-to-nbio7..patch
new file mode 100644
index 00000000..6790bc97
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2950-drm-amdgpu-add-vcn-doorbell-range-function-to-nbio7..patch
@@ -0,0 +1,74 @@
+From d8dcc77e99fbab3536ad747b3a8d77996c9ad488 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Tue, 9 Jul 2019 10:18:36 -0500
+Subject: [PATCH 2950/4256] drm/amdgpu: add vcn doorbell range function to
+ nbio7.4 (v2)
+
+To setup the aperture for VCN2.5
+
+v2: setup vcn doorbells in vcn2.5 hw_init (Alex)
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 21 +++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c  |  3 +++
+ 2 files changed, 24 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index fc45eaeaba6e..d8c9972a315b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -114,6 +114,26 @@ static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instan
+ 	WREG32(reg, doorbell_range);
+ }
+ 
++static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
++					 int doorbell_index)
++{
++	u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
++
++	u32 doorbell_range = RREG32(reg);
++
++	if (use_doorbell) {
++		doorbell_range = REG_SET_FIELD(doorbell_range,
++					       BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
++					       doorbell_index);
++		doorbell_range = REG_SET_FIELD(doorbell_range,
++					       BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
++	} else
++		doorbell_range = REG_SET_FIELD(doorbell_range,
++					       BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
++
++	WREG32(reg, doorbell_range);
++}
++
+ static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev,
+ 					       bool enable)
+ {
+@@ -292,6 +312,7 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ 	.hdp_flush = nbio_v7_4_hdp_flush,
+ 	.get_memsize = nbio_v7_4_get_memsize,
+ 	.sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range,
++	.vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range,
+ 	.enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
+ 	.enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture,
+ 	.ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index 0ffc0d60fad8..f9d6819f0260 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -205,6 +205,9 @@ static int vcn_v2_5_hw_init(void *handle)
+ 	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
+ 	int i, r;
+ 
++	adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell,
++		ring->doorbell_index);
++
+ 	r = amdgpu_ring_test_ring(ring);
+ 	if (r) {
+ 		ring->sched.ready = false;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2951-drm-amdgpu-enable-the-Doorbell-support-for-VCN2.5.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2951-drm-amdgpu-enable-the-Doorbell-support-for-VCN2.5.patch
new file mode 100644
index 00000000..003b5610
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2951-drm-amdgpu-enable-the-Doorbell-support-for-VCN2.5.patch
@@ -0,0 +1,164 @@
+From 2a26c64ad24a8c8511e0a4e9f85f32e3477cc2aa Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 26 Apr 2019 13:46:21 -0400
+Subject: [PATCH 2951/4256] drm/amdgpu: enable the Doorbell support for VCN2.5
+
+Including decode, encode, and JPEG decode rings
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c        | 64 ++++++++++++++++----
+ drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c |  4 ++
+ 2 files changed, 56 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index f9d6819f0260..840737df19c0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -128,6 +128,8 @@ static int vcn_v2_5_sw_init(void *handle)
+ 		return r;
+ 
+ 	ring = &adev->vcn.ring_dec;
++	ring->use_doorbell = true;
++	ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
+ 	sprintf(ring->name, "vcn_dec");
+ 	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
+ 	if (r)
+@@ -153,6 +155,8 @@ static int vcn_v2_5_sw_init(void *handle)
+ 
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ 		ring = &adev->vcn.ring_enc[i];
++		ring->use_doorbell = true;
++		ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
+ 		sprintf(ring->name, "vcn_enc%d", i);
+ 		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
+ 		if (r)
+@@ -160,6 +164,8 @@ static int vcn_v2_5_sw_init(void *handle)
+ 	}
+ 
+ 	ring = &adev->vcn.ring_jpeg;
++	ring->use_doorbell = true;
++	ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
+ 	sprintf(ring->name, "vcn_jpeg");
+ 	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
+ 	if (r)
+@@ -879,7 +885,10 @@ static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
++	if (ring->use_doorbell)
++		return adev->wb.wb[ring->wptr_offs];
++	else
++		return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
+ }
+ 
+ /**
+@@ -893,7 +902,12 @@ static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
++	if (ring->use_doorbell) {
++		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
++		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
++	} else {
++		WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
++	}
+ }
+ 
+ static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
+@@ -954,10 +968,17 @@ static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	if (ring == &adev->vcn.ring_enc[0])
+-		return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
+-	else
+-		return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
++	if (ring == &adev->vcn.ring_enc[0]) {
++		if (ring->use_doorbell)
++			return adev->wb.wb[ring->wptr_offs];
++		else
++			return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
++	} else {
++		if (ring->use_doorbell)
++			return adev->wb.wb[ring->wptr_offs];
++		else
++			return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
++	}
+ }
+ 
+ /**
+@@ -971,10 +992,21 @@ static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	if (ring == &adev->vcn.ring_enc[0])
+-		WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+-	else
+-		WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
++	if (ring == &adev->vcn.ring_enc[0]) {
++		if (ring->use_doorbell) {
++			adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
++			WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
++		} else {
++			WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
++		}
++	} else {
++		if (ring->use_doorbell) {
++			adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
++			WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
++		} else {
++			WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
++		}
++	}
+ }
+ 
+ static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = {
+@@ -1032,7 +1064,10 @@ static uint64_t vcn_v2_5_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
++	if (ring->use_doorbell)
++		return adev->wb.wb[ring->wptr_offs];
++	else
++		return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+ }
+ 
+ /**
+@@ -1046,7 +1081,12 @@ static void vcn_v2_5_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
++	if (ring->use_doorbell) {
++		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
++		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
++	} else {
++		WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
++	}
+ }
+ 
+ static const struct amdgpu_ring_funcs vcn_v2_5_jpeg_ring_vm_funcs = {
+diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+index 0db84386252a..79223188bd47 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
++++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+@@ -85,6 +85,10 @@ void vega20_doorbell_index_init(struct amdgpu_device *adev)
+ 	adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3;
+ 	adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5;
+ 	adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7;
++	adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_VEGA20_DOORBELL64_VCN0_1;
++	adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_VEGA20_DOORBELL64_VCN2_3;
++	adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_VEGA20_DOORBELL64_VCN4_5;
++	adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_VEGA20_DOORBELL64_VCN6_7;
+ 
+ 	adev->doorbell_index.first_non_cp = AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP;
+ 	adev->doorbell_index.last_non_cp = AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2952-drm-amdgpu-powerplay-add-arcturus-ppt-functions-1-2-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2952-drm-amdgpu-powerplay-add-arcturus-ppt-functions-1-2-.patch
new file mode 100644
index 00000000..c57a012b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2952-drm-amdgpu-powerplay-add-arcturus-ppt-functions-1-2-.patch
@@ -0,0 +1,374 @@
+From d979a8c92e195a99f491ad2208f023c03a92ce1c Mon Sep 17 00:00:00 2001
+From: Chengming Gui <Jack.Gui@amd.com>
+Date: Tue, 9 Jul 2019 10:52:20 -0500
+Subject: [PATCH 2952/4256] drm/amdgpu/powerplay: add arcturus ppt functions
+ 1/2 patch
+
+add arcturus_ppsmc.h rcturus_ppt.c and arcturus_ppt.h files.
+
+This is the initial power management support for Arcturus.
+
+Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/Makefile        |   2 +-
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  | 124 ++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.h  |  28 ++++
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  10 ++
+ .../drm/amd/powerplay/inc/arcturus_ppsmc.h    | 120 +++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     |   4 +
+ 6 files changed, 287 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+ create mode 100644 drivers/gpu/drm/amd/powerplay/arcturus_ppt.h
+ create mode 100644 drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h
+
+diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile
+index 727c5cff231c..e05a7e3d6d8d 100644
+--- a/drivers/gpu/drm/amd/powerplay/Makefile
++++ b/drivers/gpu/drm/amd/powerplay/Makefile
+@@ -35,7 +35,7 @@ AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/powerplay/,$(
+ 
+ include $(AMD_POWERPLAY)
+ 
+-POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o vega20_ppt.o navi10_ppt.o
++POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o vega20_ppt.o arcturus_ppt.o navi10_ppt.o
+ 
+ AMD_PP_POWER = $(addprefix $(AMD_PP_PATH)/,$(POWER_MGR))
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+new file mode 100644
+index 000000000000..534e450df4bb
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -0,0 +1,124 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include "pp_debug.h"
++#include <linux/firmware.h>
++#include "amdgpu.h"
++#include "amdgpu_smu.h"
++#include "atomfirmware.h"
++#include "amdgpu_atomfirmware.h"
++#include "smu_v11_0.h"
++#include "smu11_driver_if_arcturus.h"
++#include "soc15_common.h"
++#include "atom.h"
++#include "power_state.h"
++#include "arcturus_ppt.h"
++#include "arcturus_ppsmc.h"
++#include "nbio/nbio_7_4_sh_mask.h"
++
++#define MSG_MAP(msg, index) \
++	[SMU_MSG_##msg] = index
++
++static int arcturus_message_map[SMU_MSG_MAX_COUNT] = {
++	MSG_MAP(TestMessage,			     PPSMC_MSG_TestMessage),
++	MSG_MAP(GetSmuVersion,			     PPSMC_MSG_GetSmuVersion),
++	MSG_MAP(GetDriverIfVersion,		     PPSMC_MSG_GetDriverIfVersion),
++	MSG_MAP(SetAllowedFeaturesMaskLow,	     PPSMC_MSG_SetAllowedFeaturesMaskLow),
++	MSG_MAP(SetAllowedFeaturesMaskHigh,	     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
++	MSG_MAP(EnableAllSmuFeatures,		     PPSMC_MSG_EnableAllSmuFeatures),
++	MSG_MAP(DisableAllSmuFeatures,		     PPSMC_MSG_DisableAllSmuFeatures),
++	MSG_MAP(EnableSmuFeaturesLow,		     PPSMC_MSG_EnableSmuFeaturesLow),
++	MSG_MAP(EnableSmuFeaturesHigh,		     PPSMC_MSG_EnableSmuFeaturesHigh),
++	MSG_MAP(DisableSmuFeaturesLow,		     PPSMC_MSG_DisableSmuFeaturesLow),
++	MSG_MAP(DisableSmuFeaturesHigh,		     PPSMC_MSG_DisableSmuFeaturesHigh),
++	MSG_MAP(GetEnabledSmuFeaturesLow,	     PPSMC_MSG_GetEnabledSmuFeaturesLow),
++	MSG_MAP(GetEnabledSmuFeaturesHigh,	     PPSMC_MSG_GetEnabledSmuFeaturesHigh),
++	MSG_MAP(SetDriverDramAddrHigh,		     PPSMC_MSG_SetDriverDramAddrHigh),
++	MSG_MAP(SetDriverDramAddrLow,		     PPSMC_MSG_SetDriverDramAddrLow),
++	MSG_MAP(SetToolsDramAddrHigh,		     PPSMC_MSG_SetToolsDramAddrHigh),
++	MSG_MAP(SetToolsDramAddrLow,		     PPSMC_MSG_SetToolsDramAddrLow),
++	MSG_MAP(TransferTableSmu2Dram,		     PPSMC_MSG_TransferTableSmu2Dram),
++	MSG_MAP(TransferTableDram2Smu,		     PPSMC_MSG_TransferTableDram2Smu),
++	MSG_MAP(UseDefaultPPTable,		     PPSMC_MSG_UseDefaultPPTable),
++	MSG_MAP(UseBackupPPTable,		     PPSMC_MSG_UseBackupPPTable),
++	MSG_MAP(SetSystemVirtualDramAddrHigh,	     PPSMC_MSG_SetSystemVirtualDramAddrHigh),
++	MSG_MAP(SetSystemVirtualDramAddrLow,	     PPSMC_MSG_SetSystemVirtualDramAddrLow),
++	MSG_MAP(EnterBaco,			     PPSMC_MSG_EnterBaco),
++	MSG_MAP(ExitBaco,			     PPSMC_MSG_ExitBaco),
++	MSG_MAP(ArmD3,				     PPSMC_MSG_ArmD3),
++	MSG_MAP(SetSoftMinByFreq,		     PPSMC_MSG_SetSoftMinByFreq),
++	MSG_MAP(SetSoftMaxByFreq,		     PPSMC_MSG_SetSoftMaxByFreq),
++	MSG_MAP(SetHardMinByFreq,		     PPSMC_MSG_SetHardMinByFreq),
++	MSG_MAP(SetHardMaxByFreq,		     PPSMC_MSG_SetHardMaxByFreq),
++	MSG_MAP(GetMinDpmFreq,			     PPSMC_MSG_GetMinDpmFreq),
++	MSG_MAP(GetMaxDpmFreq,			     PPSMC_MSG_GetMaxDpmFreq),
++	MSG_MAP(GetDpmFreqByIndex,		     PPSMC_MSG_GetDpmFreqByIndex),
++	MSG_MAP(SetWorkloadMask,		     PPSMC_MSG_SetWorkloadMask),
++	MSG_MAP(SetDfSwitchType,		     PPSMC_MSG_SetDfSwitchType),
++	MSG_MAP(GetVoltageByDpm,		     PPSMC_MSG_GetVoltageByDpm),
++	MSG_MAP(GetVoltageByDpmOverdrive,	     PPSMC_MSG_GetVoltageByDpmOverdrive),
++	MSG_MAP(SetPptLimit,			     PPSMC_MSG_SetPptLimit),
++	MSG_MAP(GetPptLimit,			     PPSMC_MSG_GetPptLimit),
++	MSG_MAP(PowerUpVcn0,			     PPSMC_MSG_PowerUpVcn0),
++	MSG_MAP(PowerDownVcn01,			     PPSMC_MSG_PowerDownVcn01),
++	MSG_MAP(PowerUpVcn1,			     PPSMC_MSG_PowerUpVcn1),
++	MSG_MAP(PowerDownVcn1,			     PPSMC_MSG_PowerDownVcn1),
++	MSG_MAP(PrepareMp1ForUnload,		     PPSMC_MSG_PrepareMp1ForUnload),
++	MSG_MAP(PrepareMp1ForReset,		     PPSMC_MSG_PrepareMp1ForReset),
++	MSG_MAP(PrepareMp1ForShutdown,		     PPSMC_MSG_PrepareMp1ForShutdown),
++	MSG_MAP(SoftReset,			     PPSMC_MSG_SoftReset),
++	MSG_MAP(RunAfllBtc,			     PPSMC_MSG_RunAfllBtc),
++	MSG_MAP(RunGfxDcBtc,			     PPSMC_MSG_RunGfxDcBtc),
++	MSG_MAP(RunSocDcBtc,			     PPSMC_MSG_RunSocDcBtc),
++	MSG_MAP(DramLogSetDramAddrHigh,		     PPSMC_MSG_DramLogSetDramAddrHigh),
++	MSG_MAP(DramLogSetDramAddrLow,		     PPSMC_MSG_DramLogSetDramAddrLow),
++	MSG_MAP(DramLogSetDramSize,		     PPSMC_MSG_DramLogSetDramSize),
++	MSG_MAP(GetDebugData,			     PPSMC_MSG_GetDebugData),
++	MSG_MAP(WaflTest,			     PPSMC_MSG_WaflTest),
++	MSG_MAP(SetXgmiMode,			     PPSMC_MSG_SetXgmiMode),
++	MSG_MAP(SetMemoryChannelEnable,		     PPSMC_MSG_SetMemoryChannelEnable),
++};
++
++static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
++{
++	int val;
++
++	if (index >= SMU_MSG_MAX_COUNT)
++		return -EINVAL;
++
++	val = arcturus_message_map[index];
++	if (val > PPSMC_Message_Count)
++		return -EINVAL;
++
++	return val;
++}
++
++static const struct pptable_funcs arcturus_ppt_funcs = {
++	.get_smu_msg_index = arcturus_get_smu_msg_index,
++};
++
++void arcturus_set_ppt_funcs(struct smu_context *smu)
++{
++	smu->ppt_funcs = &arcturus_ppt_funcs;
++	smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
++}
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.h b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.h
+new file mode 100644
+index 000000000000..7b808d091b31
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.h
+@@ -0,0 +1,28 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __ARCTURUS_PPT_H__
++#define __ARCTURUS_PPT_H__
++
++extern void arcturus_set_ppt_funcs(struct smu_context *smu);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 135a3236f7ed..79e34097eb0f 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -242,6 +242,16 @@ enum smu_message_type
+ 	SMU_MSG_PowerDownJpeg,
+ 	SMU_MSG_BacoAudioD3PME,
+ 	SMU_MSG_ArmD3,
++	SMU_MSG_RunGfxDcBtc,
++	SMU_MSG_RunSocDcBtc,
++	SMU_MSG_SetMemoryChannelEnable,
++	SMU_MSG_SetDfSwitchType,
++	SMU_MSG_GetVoltageByDpm,
++	SMU_MSG_GetVoltageByDpmOverdrive,
++	SMU_MSG_PowerUpVcn0,
++	SMU_MSG_PowerDownVcn01,
++	SMU_MSG_PowerUpVcn1,
++	SMU_MSG_PowerDownVcn1,
+ 	SMU_MSG_MAX_COUNT,
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h
+new file mode 100644
+index 000000000000..b86bb2bc8a31
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h
+@@ -0,0 +1,120 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef ARCTURUS_PP_SMC_H
++#define ARCTURUS_PP_SMC_H
++
++#pragma pack(push, 1)
++
++// SMU Response Codes:
++#define PPSMC_Result_OK                    0x1
++#define PPSMC_Result_Failed                0xFF
++#define PPSMC_Result_UnknownCmd            0xFE
++#define PPSMC_Result_CmdRejectedPrereq     0xFD
++#define PPSMC_Result_CmdRejectedBusy       0xFC
++
++// Message Definitions:
++// BASIC
++#define PPSMC_MSG_TestMessage                    0x1
++#define PPSMC_MSG_GetSmuVersion                  0x2
++#define PPSMC_MSG_GetDriverIfVersion             0x3
++#define PPSMC_MSG_SetAllowedFeaturesMaskLow      0x4
++#define PPSMC_MSG_SetAllowedFeaturesMaskHigh     0x5
++#define PPSMC_MSG_EnableAllSmuFeatures           0x6
++#define PPSMC_MSG_DisableAllSmuFeatures          0x7
++#define PPSMC_MSG_EnableSmuFeaturesLow           0x8
++#define PPSMC_MSG_EnableSmuFeaturesHigh          0x9
++#define PPSMC_MSG_DisableSmuFeaturesLow          0xA
++#define PPSMC_MSG_DisableSmuFeaturesHigh         0xB
++#define PPSMC_MSG_GetEnabledSmuFeaturesLow       0xC
++#define PPSMC_MSG_GetEnabledSmuFeaturesHigh      0xD
++#define PPSMC_MSG_SetDriverDramAddrHigh          0xE
++#define PPSMC_MSG_SetDriverDramAddrLow           0xF
++#define PPSMC_MSG_SetToolsDramAddrHigh           0x10
++#define PPSMC_MSG_SetToolsDramAddrLow            0x11
++#define PPSMC_MSG_TransferTableSmu2Dram          0x12
++#define PPSMC_MSG_TransferTableDram2Smu          0x13
++#define PPSMC_MSG_UseDefaultPPTable              0x14
++#define PPSMC_MSG_UseBackupPPTable               0x15
++#define PPSMC_MSG_SetSystemVirtualDramAddrHigh   0x16
++#define PPSMC_MSG_SetSystemVirtualDramAddrLow    0x17
++
++//BACO/BAMACO/BOMACO
++#define PPSMC_MSG_EnterBaco                      0x18
++#define PPSMC_MSG_ExitBaco                       0x19
++#define PPSMC_MSG_ArmD3                          0x1A
++
++//DPM
++#define PPSMC_MSG_SetSoftMinByFreq               0x1B
++#define PPSMC_MSG_SetSoftMaxByFreq               0x1C
++#define PPSMC_MSG_SetHardMinByFreq               0x1D
++#define PPSMC_MSG_SetHardMaxByFreq               0x1E
++#define PPSMC_MSG_GetMinDpmFreq                  0x1F
++#define PPSMC_MSG_GetMaxDpmFreq                  0x20
++#define PPSMC_MSG_GetDpmFreqByIndex              0x21
++
++#define PPSMC_MSG_SetWorkloadMask                0x22
++#define PPSMC_MSG_SetDfSwitchType                0x23
++#define PPSMC_MSG_GetVoltageByDpm                0x24
++#define PPSMC_MSG_GetVoltageByDpmOverdrive       0x25
++
++#define PPSMC_MSG_SetPptLimit                    0x26
++#define PPSMC_MSG_GetPptLimit                    0x27
++
++//Power Gating
++#define PPSMC_MSG_PowerUpVcn0                    0x28
++#define PPSMC_MSG_PowerDownVcn01                 0x29
++#define PPSMC_MSG_PowerUpVcn1                    0x2A
++#define PPSMC_MSG_PowerDownVcn1                  0x2B
++
++//Resets and reload
++#define PPSMC_MSG_PrepareMp1ForUnload            0x2C
++#define PPSMC_MSG_PrepareMp1ForReset             0x2D
++#define PPSMC_MSG_PrepareMp1ForShutdown          0x2E
++#define PPSMC_MSG_SoftReset                      0x2F
++
++//BTC
++#define PPSMC_MSG_RunAfllBtc                     0x30
++#define PPSMC_MSG_RunGfxDcBtc                    0x31
++#define PPSMC_MSG_RunSocDcBtc                    0x32
++
++//Debug
++#define PPSMC_MSG_DramLogSetDramAddrHigh         0x33
++#define PPSMC_MSG_DramLogSetDramAddrLow          0x34
++#define PPSMC_MSG_DramLogSetDramSize             0x35
++#define PPSMC_MSG_GetDebugData                   0x36
++
++//WAFL and XGMI
++#define PPSMC_MSG_WaflTest                       0x37
++#define PPSMC_MSG_SetXgmiMode                    0x38
++
++//Others
++#define PPSMC_MSG_SetMemoryChannelEnable         0x39
++
++#define PPSMC_Message_Count                      0x3A
++
++typedef uint32_t PPSMC_Result;
++typedef uint32_t PPSMC_Msg;
++#pragma pack(pop)
++
++#endif
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index c60899de88bb..d0764ba2705c 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -30,6 +30,7 @@
+ #include "soc15_common.h"
+ #include "atom.h"
+ #include "vega20_ppt.h"
++#include "arcturus_ppt.h"
+ #include "navi10_ppt.h"
+ 
+ #include "asic_reg/thm/thm_11_0_2_offset.h"
+@@ -1793,6 +1794,9 @@ void smu_v11_0_set_smu_funcs(struct smu_context *smu)
+ 	case CHIP_VEGA20:
+ 		vega20_set_ppt_funcs(smu);
+ 		break;
++	case CHIP_ARCTURUS:
++		arcturus_set_ppt_funcs(smu);
++		break;
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+ 		navi10_set_ppt_funcs(smu);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2953-drm-amdgpu-powerplay-add-smu11-driver-interface-for-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2953-drm-amdgpu-powerplay-add-smu11-driver-interface-for-.patch
new file mode 100644
index 00000000..84a0fdc6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2953-drm-amdgpu-powerplay-add-smu11-driver-interface-for-.patch
@@ -0,0 +1,905 @@
+From fcdf8e5f832b0c3ab27aabe7abf96496ab6ab902 Mon Sep 17 00:00:00 2001
+From: Chengming Gui <Jack.Gui@amd.com>
+Date: Mon, 27 May 2019 19:01:39 +0800
+Subject: [PATCH 2953/4256] drm/amdgpu/powerplay: add smu11 driver interface
+ for arcturus. (v2) 2/2 patch
+
+add smu11_driver_if_arcturus.h file.
+
+v2: add license, fix header guard (Alex)
+
+Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../powerplay/inc/smu11_driver_if_arcturus.h  | 878 ++++++++++++++++++
+ 1 file changed, 878 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+new file mode 100644
+index 000000000000..7a9969e075d4
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+@@ -0,0 +1,878 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++
++#ifndef SMU11_DRIVER_IF_ARCTURUS_H
++#define SMU11_DRIVER_IF_ARCTURUS_H
++
++// *** IMPORTANT ***
++// SMU TEAM: Always increment the interface version if
++// any structure is changed in this file
++#define SMU11_DRIVER_IF_VERSION 0x06
++
++#define PPTABLE_ARCTURUS_SMU_VERSION 3
++
++#define NUM_GFXCLK_DPM_LEVELS  16
++#define NUM_VCLK_DPM_LEVELS    8
++#define NUM_DCLK_DPM_LEVELS    8
++#define NUM_MP0CLK_DPM_LEVELS  2
++#define NUM_SOCCLK_DPM_LEVELS  8
++#define NUM_UCLK_DPM_LEVELS    4
++#define NUM_FCLK_DPM_LEVELS    8
++#define NUM_XGMI_LEVELS        2
++
++#define MAX_GFXCLK_DPM_LEVEL  (NUM_GFXCLK_DPM_LEVELS  - 1)
++#define MAX_VCLK_DPM_LEVEL    (NUM_VCLK_DPM_LEVELS    - 1)
++#define MAX_DCLK_DPM_LEVEL    (NUM_DCLK_DPM_LEVELS    - 1)
++#define MAX_MP0CLK_DPM_LEVEL  (NUM_MP0CLK_DPM_LEVELS  - 1)
++#define MAX_SOCCLK_DPM_LEVEL  (NUM_SOCCLK_DPM_LEVELS  - 1)
++#define MAX_UCLK_DPM_LEVEL    (NUM_UCLK_DPM_LEVELS    - 1)
++#define MAX_FCLK_DPM_LEVEL    (NUM_FCLK_DPM_LEVELS    - 1)
++#define MAX_XGMI_LEVEL        (NUM_XGMI_LEVELS        - 1)
++
++// Feature Control Defines
++// DPM
++#define FEATURE_DPM_PREFETCHER_BIT      0
++#define FEATURE_DPM_GFXCLK_BIT          1
++#define FEATURE_DPM_UCLK_BIT            2
++#define FEATURE_DPM_SOCCLK_BIT          3
++#define FEATURE_DPM_FCLK_BIT            4
++#define FEATURE_DPM_MP0CLK_BIT          5
++#define FEATURE_DPM_XGMI_BIT            6
++// Idle
++#define FEATURE_DS_GFXCLK_BIT           7
++#define FEATURE_DS_SOCCLK_BIT           8
++#define FEATURE_DS_LCLK_BIT             9
++#define FEATURE_DS_FCLK_BIT             10
++#define FEATURE_DS_UCLK_BIT             11
++#define FEATURE_GFX_ULV_BIT             12
++#define FEATURE_DPM_VCN_BIT             13
++#define FEATURE_RSMU_SMN_CG_BIT         14
++#define FEATURE_WAFL_CG_BIT             15
++// Throttler/Response
++#define FEATURE_PPT_BIT                 16
++#define FEATURE_TDC_BIT                 17
++#define FEATURE_APCC_PLUS_BIT           18
++#define FEATURE_VR0HOT_BIT              19
++#define FEATURE_VR1HOT_BIT              20
++#define FEATURE_FW_CTF_BIT              21
++#define FEATURE_FAN_CONTROL_BIT         22
++#define FEATURE_THERMAL_BIT             23
++// Other
++#define FEATURE_OUT_OF_BAND_MONITOR_BIT 24
++#define FEATURE_TEMP_DEPENDENT_VMIN_BIT 25
++
++#define FEATURE_SPARE_26_BIT            26
++#define FEATURE_SPARE_27_BIT            27
++#define FEATURE_SPARE_28_BIT            28
++#define FEATURE_SPARE_29_BIT            29
++#define FEATURE_SPARE_30_BIT            30
++#define FEATURE_SPARE_31_BIT            31
++#define FEATURE_SPARE_32_BIT            32
++#define FEATURE_SPARE_33_BIT            33
++#define FEATURE_SPARE_34_BIT            34
++#define FEATURE_SPARE_35_BIT            35
++#define FEATURE_SPARE_36_BIT            36
++#define FEATURE_SPARE_37_BIT            37
++#define FEATURE_SPARE_38_BIT            38
++#define FEATURE_SPARE_39_BIT            39
++#define FEATURE_SPARE_40_BIT            40
++#define FEATURE_SPARE_41_BIT            41
++#define FEATURE_SPARE_42_BIT            42
++#define FEATURE_SPARE_43_BIT            43
++#define FEATURE_SPARE_44_BIT            44
++#define FEATURE_SPARE_45_BIT            45
++#define FEATURE_SPARE_46_BIT            46
++#define FEATURE_SPARE_47_BIT            47
++#define FEATURE_SPARE_48_BIT            48
++#define FEATURE_SPARE_49_BIT            49
++#define FEATURE_SPARE_50_BIT            50
++#define FEATURE_SPARE_51_BIT            51
++#define FEATURE_SPARE_52_BIT            52
++#define FEATURE_SPARE_53_BIT            53
++#define FEATURE_SPARE_54_BIT            54
++#define FEATURE_SPARE_55_BIT            55
++#define FEATURE_SPARE_56_BIT            56
++#define FEATURE_SPARE_57_BIT            57
++#define FEATURE_SPARE_58_BIT            58
++#define FEATURE_SPARE_59_BIT            59
++#define FEATURE_SPARE_60_BIT            60
++#define FEATURE_SPARE_61_BIT            61
++#define FEATURE_SPARE_62_BIT            62
++#define FEATURE_SPARE_63_BIT            63
++
++#define NUM_FEATURES                    64
++
++
++#define FEATURE_DPM_PREFETCHER_MASK       (1 << FEATURE_DPM_PREFETCHER_BIT       )
++#define FEATURE_DPM_GFXCLK_MASK           (1 << FEATURE_DPM_GFXCLK_BIT           )
++#define FEATURE_DPM_UCLK_MASK             (1 << FEATURE_DPM_UCLK_BIT             )
++#define FEATURE_DPM_SOCCLK_MASK           (1 << FEATURE_DPM_SOCCLK_BIT           )
++#define FEATURE_DPM_FCLK_MASK             (1 << FEATURE_DPM_FCLK_BIT             )
++#define FEATURE_DPM_MP0CLK_MASK           (1 << FEATURE_DPM_MP0CLK_BIT           )
++#define FEATURE_DPM_XGMI_MASK             (1 << FEATURE_DPM_XGMI_BIT             )
++
++#define FEATURE_DS_GFXCLK_MASK            (1 << FEATURE_DS_GFXCLK_BIT            )
++#define FEATURE_DS_SOCCLK_MASK            (1 << FEATURE_DS_SOCCLK_BIT            )
++#define FEATURE_DS_LCLK_MASK              (1 << FEATURE_DS_LCLK_BIT              )
++#define FEATURE_DS_FCLK_MASK              (1 << FEATURE_DS_FCLK_BIT              )
++#define FEATURE_DS_LCLK_MASK              (1 << FEATURE_DS_LCLK_BIT              )
++#define FEATURE_GFX_ULV_MASK              (1 << FEATURE_GFX_ULV_BIT              )
++#define FEATURE_VCN_PG_MASK               (1 << FEATURE_VCN_PG_BIT               )
++#define FEATURE_RSMU_SMN_CG_MASK          (1 << FEATURE_RSMU_SMN_CG_BIT          )
++#define FEATURE_WAFL_CG_MASK              (1 << FEATURE_WAFL_CG_BIT              )
++
++#define FEATURE_PPT_MASK                  (1 << FEATURE_PPT_BIT                  )
++#define FEATURE_TDC_MASK                  (1 << FEATURE_TDC_BIT                  )
++#define FEATURE_APCC_MASK                 (1 << FEATURE_APCC_BIT                 )
++#define FEATURE_VR0HOT_MASK               (1 << FEATURE_VR0HOT_BIT               )
++#define FEATURE_VR1HOT_MASK               (1 << FEATURE_VR1HOT_BIT               )
++#define FEATURE_FW_CTF_MASK               (1 << FEATURE_FW_CTF_BIT               )
++#define FEATURE_FAN_CONTROL_MASK          (1 << FEATURE_FAN_CONTROL_BIT          )
++#define FEATURE_THERMAL_MASK              (1 << FEATURE_THERMAL_BIT              )
++
++#define FEATURE_OUT_OF_BAND_MONITOR_MASK  (1 << EATURE_OUT_OF_BAND_MONITOR_BIT   )
++#define FEATURE_TEMP_DEPENDENT_VMIN_MASK  (1 << FEATURE_TEMP_DEPENDENT_VMIN_MASK )
++
++
++//FIXME need updating
++// Debug Overrides Bitmask
++#define DPM_OVERRIDE_DISABLE_UCLK_PID               0x00000001
++#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCN_FCLK      0x00000002
++
++// I2C Config Bit Defines
++#define I2C_CONTROLLER_ENABLED           1
++#define I2C_CONTROLLER_DISABLED          0
++
++// VR Mapping Bit Defines
++#define VR_MAPPING_VR_SELECT_MASK  0x01
++#define VR_MAPPING_VR_SELECT_SHIFT 0x00
++
++#define VR_MAPPING_PLANE_SELECT_MASK  0x02
++#define VR_MAPPING_PLANE_SELECT_SHIFT 0x01
++
++// PSI Bit Defines
++#define PSI_SEL_VR0_PLANE0_PSI0  0x01
++#define PSI_SEL_VR0_PLANE0_PSI1  0x02
++#define PSI_SEL_VR0_PLANE1_PSI0  0x04
++#define PSI_SEL_VR0_PLANE1_PSI1  0x08
++#define PSI_SEL_VR1_PLANE0_PSI0  0x10
++#define PSI_SEL_VR1_PLANE0_PSI1  0x20
++#define PSI_SEL_VR1_PLANE1_PSI0  0x40
++#define PSI_SEL_VR1_PLANE1_PSI1  0x80
++
++// Throttler Control/Status Bits
++#define THROTTLER_PADDING_BIT      0
++#define THROTTLER_TEMP_EDGE_BIT    1
++#define THROTTLER_TEMP_HOTSPOT_BIT 2
++#define THROTTLER_TEMP_MEM_BIT     3
++#define THROTTLER_TEMP_VR_GFX_BIT  4
++#define THROTTLER_TEMP_VR_MEM_BIT  5
++#define THROTTLER_TEMP_VR_SOC_BIT  6
++#define THROTTLER_TDC_GFX_BIT      7
++#define THROTTLER_TDC_SOC_BIT      8
++#define THROTTLER_PPT0_BIT         9
++#define THROTTLER_PPT1_BIT         10
++#define THROTTLER_PPT2_BIT         11
++#define THROTTLER_PPT3_BIT         12
++#define THROTTLER_PPM_BIT          13
++#define THROTTLER_FIT_BIT          14
++#define THROTTLER_APCC_BIT         15
++
++// Table transfer status
++#define TABLE_TRANSFER_OK         0x0
++#define TABLE_TRANSFER_FAILED     0xFF
++#define TABLE_TRANSFER_PENDING    0xAB
++
++// Workload bits
++#define WORKLOAD_PPLIB_DEFAULT_BIT        0
++#define WORKLOAD_PPLIB_POWER_SAVING_BIT   1
++#define WORKLOAD_PPLIB_VIDEO_BIT          2
++#define WORKLOAD_PPLIB_COMPUTE_BIT        3
++#define WORKLOAD_PPLIB_CUSTOM_BIT         4
++#define WORKLOAD_PPLIB_COUNT              5
++
++//XGMI performance states
++#define XGMI_STATE_D0                      1
++#define XGMI_STATE_D3                      0
++
++#define NUM_I2C_CONTROLLERS                8
++
++#define I2C_CONTROLLER_ENABLED             1
++#define I2C_CONTROLLER_DISABLED            0
++
++#define MAX_SW_I2C_COMMANDS                8
++
++typedef enum {
++  I2C_CONTROLLER_PORT_0 = 0,  //CKSVII2C0
++  I2C_CONTROLLER_PORT_1 = 1,  //CKSVII2C1
++  I2C_CONTROLLER_PORT_COUNT,
++} I2cControllerPort_e;
++
++typedef enum {
++  I2C_CONTROLLER_NAME_VR_GFX = 0,
++  I2C_CONTROLLER_NAME_VR_SOC,
++  I2C_CONTROLLER_NAME_VR_MEM,
++  I2C_CONTROLLER_NAME_SPARE,
++  I2C_CONTROLLER_NAME_COUNT,
++} I2cControllerName_e;
++
++typedef enum {
++  I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
++  I2C_CONTROLLER_THROTTLER_VR_GFX,
++  I2C_CONTROLLER_THROTTLER_VR_SOC,
++  I2C_CONTROLLER_THROTTLER_VR_MEM,
++  I2C_CONTROLLER_THROTTLER_COUNT,
++} I2cControllerThrottler_e;
++
++typedef enum {
++  I2C_CONTROLLER_PROTOCOL_VR_0,
++  I2C_CONTROLLER_PROTOCOL_VR_1,
++  I2C_CONTROLLER_PROTOCOL_TMP_0,
++  I2C_CONTROLLER_PROTOCOL_TMP_1,
++  I2C_CONTROLLER_PROTOCOL_SPARE_0,
++  I2C_CONTROLLER_PROTOCOL_SPARE_1,
++  I2C_CONTROLLER_PROTOCOL_COUNT,
++} I2cControllerProtocol_e;
++
++typedef struct {
++  uint8_t   Enabled;
++  uint8_t   Speed;
++  uint8_t   Padding[2];
++  uint32_t  SlaveAddress;
++  uint8_t   ControllerPort;
++  uint8_t   ControllerName;
++  uint8_t   ThermalThrotter;
++  uint8_t   I2cProtocol;
++} I2cControllerConfig_t;
++
++typedef enum {
++  I2C_PORT_SVD_SCL = 0,
++  I2C_PORT_GPIO,
++} I2cPort_e;
++
++typedef enum {
++  I2C_SPEED_FAST_50K = 0,      //50  Kbits/s
++  I2C_SPEED_FAST_100K,         //100 Kbits/s
++  I2C_SPEED_FAST_400K,         //400 Kbits/s
++  I2C_SPEED_FAST_PLUS_1M,      //1   Mbits/s (in fast mode)
++  I2C_SPEED_HIGH_1M,           //1   Mbits/s (in high speed mode)
++  I2C_SPEED_HIGH_2M,           //2.3 Mbits/s
++  I2C_SPEED_COUNT,
++} I2cSpeed_e;
++
++typedef enum {
++  I2C_CMD_READ = 0,
++  I2C_CMD_WRITE,
++  I2C_CMD_COUNT,
++} I2cCmdType_e;
++
++#define CMDCONFIG_STOP_BIT      0
++#define CMDCONFIG_RESTART_BIT   1
++
++#define CMDCONFIG_STOP_MASK     (1 << CMDCONFIG_STOP_BIT)
++#define CMDCONFIG_RESTART_MASK  (1 << CMDCONFIG_RESTART_BIT)
++
++typedef struct {
++  uint8_t RegisterAddr; ////only valid for write, ignored for read
++  uint8_t Cmd;  //Read(0) or Write(1)
++  uint8_t Data;  //Return data for read. Data to send for write
++  uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command
++} SwI2cCmd_t; //SW I2C Command Table
++
++typedef struct {
++  uint8_t     I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)
++  uint8_t     I2CSpeed;          //Slow(0) or Fast(1)
++  uint16_t    SlaveAddress;
++  uint8_t     NumCmds;           //Number of commands
++  uint8_t     Padding[3];
++
++  SwI2cCmd_t  SwI2cCmds[MAX_SW_I2C_COMMANDS];
++
++  uint32_t     MmHubPadding[8]; // SMU internal use
++
++} SwI2cRequest_t; // SW I2C Request Table
++
++//D3HOT sequences
++//sequence codes from spec: atlvp4p01.amd.com:1677@//gpu/doc/soc_arch/spec/feature/BACO/Navi/Navi2x/
++typedef enum {
++  BACO_SEQUENCE,
++  MSR_SEQUENCE,
++  BAMACO_SEQUENCE,
++  ULPS_SEQUENCE,
++  D3HOT_SEQUENCE_COUNT,
++}D3HOTSequence_e;
++
++//THis is aligned with RSMU PGFSM Register Mapping
++typedef enum {
++  PG_DYNAMIC_MODE = 0,
++  PG_STATIC_MODE,
++} PowerGatingMode_e;
++
++//This is aligned with RSMU PGFSM Register Mapping
++typedef enum {
++  PG_POWER_DOWN = 0,
++  PG_POWER_UP,
++} PowerGatingSettings_e;
++
++typedef struct {
++  uint32_t a;  // store in IEEE float format in this variable
++  uint32_t b;  // store in IEEE float format in this variable
++  uint32_t c;  // store in IEEE float format in this variable
++} QuadraticInt_t;
++
++typedef struct {
++  uint32_t m;  // store in IEEE float format in this variable
++  uint32_t b;  // store in IEEE float format in this variable
++} LinearInt_t;
++
++typedef struct {
++  uint32_t a;  // store in IEEE float format in this variable
++  uint32_t b;  // store in IEEE float format in this variable
++  uint32_t c;  // store in IEEE float format in this variable
++} DroopInt_t;
++
++typedef enum {
++  GFXCLK_SOURCE_PLL = 0,
++  GFXCLK_SOURCE_AFLL,
++  GFXCLK_SOURCE_COUNT,
++} GfxclkSrc_e;
++
++typedef enum {
++  PPCLK_GFXCLK,
++  PPCLK_VCLK,
++  PPCLK_DCLK,
++  PPCLK_SOCCLK,
++  PPCLK_UCLK,
++  PPCLK_FCLK,
++  PPCLK_COUNT,
++} PPCLK_e;
++
++typedef enum {
++  TEMP_EDGE,
++  TEMP_HOTSPOT,
++  TEMP_MEM,
++  TEMP_VR_GFX,
++  TEMP_VR_SOC,
++  TEMP_VR_MEM,
++  TEMP_COUNT
++} TEMP_TYPE_e;
++
++typedef enum  {
++  PPT_THROTTLER_PPT0,
++  PPT_THROTTLER_PPT1,
++  PPT_THROTTLER_PPT2,
++  PPT_THROTTLER_PPT3,
++  PPT_THROTTLER_COUNT
++} PPT_THROTTLER_e;
++
++typedef enum {
++  VOLTAGE_MODE_AVFS = 0,
++  VOLTAGE_MODE_AVFS_SS,
++  VOLTAGE_MODE_SS,
++  VOLTAGE_MODE_COUNT,
++} VOLTAGE_MODE_e;
++
++typedef enum {
++  AVFS_VOLTAGE_GFX = 0,
++  AVFS_VOLTAGE_SOC,
++  AVFS_VOLTAGE_COUNT,
++} AVFS_VOLTAGE_TYPE_e;
++
++typedef enum {
++  GPIO_INT_POLARITY_ACTIVE_LOW = 0,
++  GPIO_INT_POLARITY_ACTIVE_HIGH,
++} GpioIntPolarity_e;
++
++typedef enum {
++  MEMORY_TYPE_GDDR6 = 0,
++  MEMORY_TYPE_HBM,
++} MemoryType_e;
++
++typedef enum {
++  PWR_CONFIG_TDP = 0,
++  PWR_CONFIG_TGP,
++  PWR_CONFIG_TCP_ESTIMATED,
++  PWR_CONFIG_TCP_MEASURED,
++} PwrConfig_e;
++
++typedef enum {
++  XGMI_LINK_RATE_12 = 0,  // 12Gbps
++  XGMI_LINK_RATE_16,      // 16Gbps
++  XGMI_LINK_RATE_22,      // 22Gbps
++  XGMI_LINK_RATE_25,      // 25Gbps
++  XGMI_LINK_RATE_COUNT
++} XGMI_LINK_RATE_e;
++
++typedef enum {
++  XGMI_LINK_WIDTH_2 = 0, // x2
++  XGMI_LINK_WIDTH_4,     // x4
++  XGMI_LINK_WIDTH_8,     // x8
++  XGMI_LINK_WIDTH_16,    // x16
++  XGMI_LINK_WIDTH_COUNT
++} XGMI_LINK_WIDTH_e;
++
++typedef struct {
++  uint8_t        VoltageMode;         // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only
++  uint8_t        SnapToDiscrete;      // 0 - Fine grained DPM, 1 - Discrete DPM
++  uint8_t        NumDiscreteLevels;   // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used
++  uint8_t        padding;
++  LinearInt_t    ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
++  QuadraticInt_t SsCurve;             // Slow-slow curve (GHz->V)
++  uint16_t       SsFmin;              // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin
++  uint16_t       Padding16;
++} DpmDescriptor_t;
++
++typedef struct {
++  uint32_t Version;
++
++  // SECTION: Feature Enablement
++  uint32_t FeaturesToRun[2];
++
++  // SECTION: Infrastructure Limits
++  uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT];
++  uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT];
++  uint16_t TdcLimitSoc;             // Amps
++  uint16_t TdcLimitSocTau;          // Time constant of LPF in ms
++  uint16_t TdcLimitGfx;             // Amps
++  uint16_t TdcLimitGfxTau;          // Time constant of LPF in ms
++
++  uint16_t TedgeLimit;              // Celcius
++  uint16_t ThotspotLimit;           // Celcius
++  uint16_t TmemLimit;               // Celcius
++  uint16_t Tvr_gfxLimit;            // Celcius
++  uint16_t Tvr_memLimit;            // Celcius
++  uint16_t Tvr_socLimit;            // Celcius
++  uint32_t FitLimit;                // Failures in time (failures per million parts over the defined lifetime)
++
++  uint16_t PpmPowerLimit;           // Switch this this power limit when temperature is above PpmTempThreshold
++  uint16_t PpmTemperatureThreshold;
++
++  // SECTION: Throttler settings
++  uint32_t ThrottlerControlMask;   // See Throtter masks defines
++
++  // SECTION: ULV Settings
++  uint16_t  UlvVoltageOffsetGfx; // In mV(Q2)
++  uint16_t  UlvPadding;          // Padding
++
++  uint8_t  UlvGfxclkBypass;  // 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV
++  uint8_t  Padding234[3];
++
++  // SECTION: Voltage Control Parameters
++  uint16_t     MinVoltageGfx;     // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
++  uint16_t     MinVoltageSoc;     // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
++  uint16_t     MaxVoltageGfx;     // In mV(Q2) Maximum Voltage allowable of VDD_GFX
++  uint16_t     MaxVoltageSoc;     // In mV(Q2) Maximum Voltage allowable of VDD_SOC
++
++  uint16_t     LoadLineResistanceGfx;   // In mOhms with 8 fractional bits
++  uint16_t     LoadLineResistanceSoc;   // In mOhms with 8 fractional bits
++
++  //SECTION: DPM Config 1
++  DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
++
++  uint16_t       FreqTableGfx      [NUM_GFXCLK_DPM_LEVELS  ];     // In MHz
++  uint16_t       FreqTableVclk     [NUM_VCLK_DPM_LEVELS    ];     // In MHz
++  uint16_t       FreqTableDclk     [NUM_DCLK_DPM_LEVELS    ];     // In MHz
++  uint16_t       FreqTableSocclk   [NUM_SOCCLK_DPM_LEVELS  ];     // In MHz
++  uint16_t       FreqTableUclk     [NUM_UCLK_DPM_LEVELS    ];     // In MHz
++  uint16_t       FreqTableFclk     [NUM_FCLK_DPM_LEVELS    ];     // In MHz
++
++  uint32_t       Paddingclks[16];
++
++  // SECTION: DPM Config 2
++  uint16_t       Mp0clkFreq        [NUM_MP0CLK_DPM_LEVELS];       // in MHz
++  uint16_t       Mp0DpmVoltage     [NUM_MP0CLK_DPM_LEVELS];       // mV(Q2)
++
++  // GFXCLK DPM
++  uint16_t        GfxclkFidle;          // In MHz
++  uint16_t        GfxclkSlewRate;       // for PLL babystepping???
++  uint8_t         Padding567[4];
++  uint16_t        GfxclkDsMaxFreq;      // In MHz
++  uint8_t         GfxclkSource;         // 0 = PLL, 1 = AFLL
++  uint8_t         Padding456;
++
++  // GFXCLK Thermal DPM (formerly 'Boost' Settings)
++  uint16_t     EnableTdpm;
++  uint16_t     TdpmHighHystTemperature;
++  uint16_t     TdpmLowHystTemperature;
++  uint16_t     GfxclkFreqHighTempLimit; // High limit on GFXCLK when temperature is high, for reliability.
++
++  // SECTION: Fan Control
++  uint16_t     FanStopTemp;          //Celcius
++  uint16_t     FanStartTemp;         //Celcius
++
++  uint16_t     FanGainEdge;
++  uint16_t     FanGainHotspot;
++  uint16_t     FanGainVrGfx;
++  uint16_t     FanGainVrSoc;
++  uint16_t     FanGainVrMem;
++  uint16_t     FanGainHbm;
++  uint16_t     FanPwmMin;
++  uint16_t     FanAcousticLimitRpm;
++  uint16_t     FanThrottlingRpm;
++  uint16_t     FanMaximumRpm;
++  uint16_t     FanTargetTemperature;
++  uint16_t     FanTargetGfxclk;
++  uint8_t      FanZeroRpmEnable;
++  uint8_t      FanTachEdgePerRev;
++  uint8_t      FanTempInputSelect;
++  uint8_t      padding8_Fan;
++
++  // The following are AFC override parameters. Leave at 0 to use FW defaults.
++  int16_t      FuzzyFan_ErrorSetDelta;
++  int16_t      FuzzyFan_ErrorRateSetDelta;
++  int16_t      FuzzyFan_PwmSetDelta;
++  uint16_t     FuzzyFan_Reserved;
++
++
++  // SECTION: AVFS
++  // Overrides
++  uint8_t           OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
++  uint8_t           Padding8_Avfs[2];
++
++  QuadraticInt_t    qAvfsGb[AVFS_VOLTAGE_COUNT];              // GHz->V Override of fused curve
++  DroopInt_t        dBtcGbGfxPll;       // GHz->V BtcGb
++  DroopInt_t        dBtcGbGfxAfll;        // GHz->V BtcGb
++  DroopInt_t        dBtcGbSoc;            // GHz->V BtcGb
++  LinearInt_t       qAgingGb[AVFS_VOLTAGE_COUNT];          // GHz->V
++
++  QuadraticInt_t    qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V
++
++  uint16_t          DcTol[AVFS_VOLTAGE_COUNT];            // mV Q2
++
++  uint8_t           DcBtcEnabled[AVFS_VOLTAGE_COUNT];
++  uint8_t           Padding8_GfxBtc[2];
++
++  uint16_t          DcBtcMin[AVFS_VOLTAGE_COUNT];       // mV Q2
++  uint16_t          DcBtcMax[AVFS_VOLTAGE_COUNT];       // mV Q2
++
++  uint16_t          DcBtcGb[AVFS_VOLTAGE_COUNT];        // mV Q2
++
++  uint16_t          SsFmin[10]; // PPtable value to function similar to VFTFmin for SS Curve; Size is PPCLK_COUNT rounded to nearest multiple of 2
++
++  // SECTION: XGMI
++  uint8_t           XgmiLinkSpeed   [NUM_XGMI_LEVELS];
++  uint8_t           XgmiLinkWidth   [NUM_XGMI_LEVELS];
++
++  uint16_t          XgmiFclkFreq    [NUM_XGMI_LEVELS];
++  uint16_t          XgmiSocVoltage  [NUM_XGMI_LEVELS];
++
++  // Temperature Dependent Vmin
++  uint16_t     VDDGFX_TVmin;       //Celcius
++  uint16_t     VDDSOC_TVmin;       //Celcius
++  uint16_t     VDDGFX_Vmin_HiTemp; // mV Q2
++  uint16_t     VDDGFX_Vmin_LoTemp; // mV Q2
++  uint16_t     VDDSOC_Vmin_HiTemp; // mV Q2
++  uint16_t     VDDSOC_Vmin_LoTemp; // mV Q2
++
++  uint16_t     VDDGFX_TVminHystersis; // Celcius
++  uint16_t     VDDSOC_TVminHystersis; // Celcius
++
++
++  // SECTION: Advanced Options
++  uint32_t          DebugOverrides;
++  QuadraticInt_t    ReservedEquation0;
++  QuadraticInt_t    ReservedEquation1;
++  QuadraticInt_t    ReservedEquation2;
++  QuadraticInt_t    ReservedEquation3;
++
++  uint16_t     MinVoltageUlvGfx; // In mV(Q2)  Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
++  uint16_t     PaddingUlv;       // Padding
++
++  // Total Power configuration, use defines from PwrConfig_e
++  uint8_t      TotalPowerConfig;    //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured
++  uint8_t      TotalPowerSpare1;
++  uint16_t     TotalPowerSpare2;
++
++  // APCC Settings
++  uint16_t     PccThresholdLow;
++  uint16_t     PccThresholdHigh;
++  uint32_t     PaddingAPCC[6];  //FIXME pending SPEC
++
++  // SECTION: Reserved
++  uint32_t     Reserved[11];
++
++  // SECTION: BOARD PARAMETERS
++
++  // SVI2 Board Parameters
++  uint16_t     MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
++  uint16_t     MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
++
++  uint8_t      VddGfxVrMapping;     // Use VR_MAPPING* bitfields
++  uint8_t      VddSocVrMapping;     // Use VR_MAPPING* bitfields
++  uint8_t      VddMemVrMapping;     // Use VR_MAPPING* bitfields
++  uint8_t      BoardVrMapping;      // Use VR_MAPPING* bitfields
++
++  uint8_t      GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
++  uint8_t      ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
++  uint8_t      Padding8_V[2];
++
++  // Telemetry Settings
++  uint16_t     GfxMaxCurrent;   // in Amps
++  int8_t       GfxOffset;       // in Amps
++  uint8_t      Padding_TelemetryGfx;
++
++  uint16_t     SocMaxCurrent;   // in Amps
++  int8_t       SocOffset;       // in Amps
++  uint8_t      Padding_TelemetrySoc;
++
++  uint16_t     MemMaxCurrent;   // in Amps
++  int8_t       MemOffset;       // in Amps
++  uint8_t      Padding_TelemetryMem;
++
++  uint16_t     BoardMaxCurrent;   // in Amps
++  int8_t       BoardOffset;       // in Amps
++  uint8_t      Padding_TelemetryBoardInput;
++
++  // GPIO Settings
++  uint8_t      VR0HotGpio;      // GPIO pin configured for VR0 HOT event
++  uint8_t      VR0HotPolarity;  // GPIO polarity for VR0 HOT event
++  uint8_t      VR1HotGpio;      // GPIO pin configured for VR1 HOT event
++  uint8_t      VR1HotPolarity;  // GPIO polarity for VR1 HOT event
++
++  // GFXCLK PLL Spread Spectrum
++  uint8_t      PllGfxclkSpreadEnabled;   // on or off
++  uint8_t      PllGfxclkSpreadPercent;   // Q4.4
++  uint16_t     PllGfxclkSpreadFreq;      // kHz
++
++  // UCLK Spread Spectrum
++  uint8_t      UclkSpreadEnabled;   // on or off
++  uint8_t      UclkSpreadPercent;   // Q4.4
++  uint16_t     UclkSpreadFreq;      // kHz
++
++  // FCLK Spread Spectrum
++  uint8_t      FclkSpreadEnabled;   // on or off
++  uint8_t      FclkSpreadPercent;   // Q4.4
++  uint16_t     FclkSpreadFreq;      // kHz
++
++  // GFXCLK Fll Spread Spectrum
++  uint8_t      FllGfxclkSpreadEnabled;   // on or off
++  uint8_t      FllGfxclkSpreadPercent;   // Q4.4
++  uint16_t     FllGfxclkSpreadFreq;      // kHz
++
++  // I2C Controller Structure
++  I2cControllerConfig_t  I2cControllers[NUM_I2C_CONTROLLERS];
++
++  // Memory section
++  uint32_t     MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
++
++  uint8_t      DramBitWidth; // For DRAM use only.  See Dram Bit width type defines
++  uint8_t      PaddingMem[3];
++
++  // Total board power
++  uint16_t     TotalBoardPower;     //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
++  uint16_t     BoardPadding;
++
++  uint32_t     BoardReserved[10];
++
++  // Padding for MMHUB - do not modify this
++  uint32_t     MmHubPadding[8]; // SMU internal use
++
++} PPTable_t;
++
++typedef struct {
++  // Time constant parameters for clock averages in ms
++  uint16_t     GfxclkAverageLpfTau;
++  uint16_t     SocclkAverageLpfTau;
++  uint16_t     UclkAverageLpfTau;
++  uint16_t     GfxActivityLpfTau;
++  uint16_t     UclkActivityLpfTau;
++
++  uint16_t     Padding;
++
++  // Padding - ignore
++  uint32_t     MmHubPadding[8]; // SMU internal use
++} DriverSmuConfig_t;
++
++typedef struct {
++  uint16_t CurrClock[PPCLK_COUNT];
++  uint16_t AverageGfxclkFrequency;
++  uint16_t AverageSocclkFrequency;
++  uint16_t AverageUclkFrequency  ;
++  uint16_t AverageGfxActivity    ;
++  uint16_t AverageUclkActivity   ;
++  uint8_t  CurrSocVoltageOffset  ;
++  uint8_t  CurrGfxVoltageOffset  ;
++  uint8_t  CurrMemVidOffset      ;
++  uint8_t  Padding8              ;
++  uint16_t CurrSocketPower       ;
++  uint16_t TemperatureEdge       ;
++  uint16_t TemperatureHotspot    ;
++  uint16_t TemperatureHBM        ;
++  uint16_t TemperatureVrGfx      ;
++  uint16_t TemperatureVrSoc      ;
++  uint16_t TemperatureVrMem      ;
++  uint32_t ThrottlerStatus       ;
++
++  // Padding - ignore
++  uint32_t     MmHubPadding[7]; // SMU internal use
++} SmuMetrics_t;
++
++
++typedef struct {
++  uint16_t avgPsmCount[45];
++  uint16_t minPsmCount[45];
++  float    avgPsmVoltage[45];
++  float    minPsmVoltage[45];
++
++  uint16_t avgScsPsmCount;
++  uint16_t minScsPsmCount;
++  float    avgScsPsmVoltage;
++  float    minScsPsmVoltage;
++
++  uint32_t MmHubPadding[6]; // SMU internal use
++} AvfsDebugTable_t;
++
++typedef struct {
++  uint8_t  AvfsVersion;
++  uint8_t  Padding;
++  uint8_t  AvfsEn[AVFS_VOLTAGE_COUNT];
++
++  uint8_t  OverrideVFT[AVFS_VOLTAGE_COUNT];
++  uint8_t  OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
++
++  uint8_t  OverrideTemperatures[AVFS_VOLTAGE_COUNT];
++  uint8_t  OverrideVInversion[AVFS_VOLTAGE_COUNT];
++  uint8_t  OverrideP2V[AVFS_VOLTAGE_COUNT];
++  uint8_t  OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT];
++
++  int32_t VFT0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
++  int32_t VFT0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
++  int32_t VFT0_b[AVFS_VOLTAGE_COUNT];  // Q32
++
++  int32_t VFT1_m1[AVFS_VOLTAGE_COUNT]; // Q8.16
++  int32_t VFT1_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
++  int32_t VFT1_b[AVFS_VOLTAGE_COUNT];  // Q32
++
++  int32_t VFT2_m1[AVFS_VOLTAGE_COUNT]; // Q8.16
++  int32_t VFT2_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
++  int32_t VFT2_b[AVFS_VOLTAGE_COUNT];  // Q32
++
++  int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
++  int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
++  int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT];  // Q32
++
++  int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
++  int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
++  int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT];  // Q32
++
++  uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT];
++  uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT];
++  uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT];
++
++  uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits
++
++
++  int32_t P2V_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
++  int32_t P2V_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
++  int32_t P2V_b[AVFS_VOLTAGE_COUNT];  // Q32
++
++  uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units
++
++  uint32_t EnabledAvfsModules;
++
++  uint32_t MmHubPadding[7]; // SMU internal use
++} AvfsFuseOverride_t;
++
++/* NOT CURRENTLY USED
++typedef struct {
++  uint8_t   Gfx_ActiveHystLimit;
++  uint8_t   Gfx_IdleHystLimit;
++  uint8_t   Gfx_FPS;
++  uint8_t   Gfx_MinActiveFreqType;
++  uint8_t   Gfx_BoosterFreqType;
++  uint8_t   Gfx_MinFreqStep;                // Minimum delta between current and target frequeny in order for FW to change clock.
++  uint8_t   Gfx_UseRlcBusy;
++  uint8_t   PaddingGfx[3];
++  uint16_t  Gfx_MinActiveFreq;              // MHz
++  uint16_t  Gfx_BoosterFreq;                // MHz
++  uint16_t  Gfx_PD_Data_time_constant;      // Time constant of PD controller in ms
++  uint32_t  Gfx_PD_Data_limit_a;            // Q16
++  uint32_t  Gfx_PD_Data_limit_b;            // Q16
++  uint32_t  Gfx_PD_Data_limit_c;            // Q16
++  uint32_t  Gfx_PD_Data_error_coeff;        // Q16
++  uint32_t  Gfx_PD_Data_error_rate_coeff;   // Q16
++
++  uint8_t   Mem_ActiveHystLimit;
++  uint8_t   Mem_IdleHystLimit;
++  uint8_t   Mem_FPS;
++  uint8_t   Mem_MinActiveFreqType;
++  uint8_t   Mem_BoosterFreqType;
++  uint8_t   Mem_MinFreqStep;                // Minimum delta between current and target frequeny in order for FW to change clock.
++  uint8_t   Mem_UseRlcBusy;
++  uint8_t   PaddingMem[3];
++  uint16_t  Mem_MinActiveFreq;              // MHz
++  uint16_t  Mem_BoosterFreq;                // MHz
++  uint16_t  Mem_PD_Data_time_constant;      // Time constant of PD controller in ms
++  uint32_t  Mem_PD_Data_limit_a;            // Q16
++  uint32_t  Mem_PD_Data_limit_b;            // Q16
++  uint32_t  Mem_PD_Data_limit_c;            // Q16
++  uint32_t  Mem_PD_Data_error_coeff;        // Q16
++  uint32_t  Mem_PD_Data_error_rate_coeff;   // Q16
++
++  uint32_t  Mem_UpThreshold_Limit;          // Q16
++  uint8_t   Mem_UpHystLimit;
++  uint8_t   Mem_DownHystLimit;
++  uint16_t  Mem_Fps;
++
++  uint32_t  MmHubPadding[8]; // SMU internal use
++} DpmActivityMonitorCoeffInt_t;
++*/
++
++// These defines are used with the following messages:
++// SMC_MSG_TransferTableDram2Smu
++// SMC_MSG_TransferTableSmu2Dram
++#define TABLE_PPTABLE                 0
++#define TABLE_AVFS                    1
++#define TABLE_AVFS_PSM_DEBUG          2
++#define TABLE_AVFS_FUSE_OVERRIDE      3
++#define TABLE_PMSTATUSLOG             4
++#define TABLE_SMU_METRICS             5
++#define TABLE_DRIVER_SMU_CONFIG       6
++//#define TABLE_ACTIVITY_MONITOR_COEFF  7
++#define TABLE_OVERDRIVE               7
++#define TABLE_WAFL_XGMI_TOPOLOGY      8
++#define TABLE_COUNT                   9
++
++// These defines are used with the SMC_MSG_SetUclkFastSwitch message.
++typedef enum {
++  DF_SWITCH_TYPE_FAST = 0,
++  DF_SWITCH_TYPE_SLOW,
++  DF_SWITCH_TYPE_COUNT,
++} DF_SWITCH_TYPE_e;
++
++typedef enum {
++  DRAM_BIT_WIDTH_DISABLED = 0,
++  DRAM_BIT_WIDTH_X_8,
++  DRAM_BIT_WIDTH_X_16,
++  DRAM_BIT_WIDTH_X_32,
++  DRAM_BIT_WIDTH_X_64, // NOT USED.
++  DRAM_BIT_WIDTH_X_128,
++  DRAM_BIT_WIDTH_COUNT,
++} DRAM_BIT_WIDTH_TYPE_e;
++
++#define REMOVE_FMAX_MARGIN_BIT     0x0
++#define REMOVE_DCTOL_MARGIN_BIT    0x1
++#define REMOVE_PLATFORM_MARGIN_BIT 0x2
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2954-drm-amd-powerplay-get-smc-firmware-and-pptable.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2954-drm-amd-powerplay-get-smc-firmware-and-pptable.patch
new file mode 100644
index 00000000..9868da98
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2954-drm-amd-powerplay-get-smc-firmware-and-pptable.patch
@@ -0,0 +1,67 @@
+From 4f366a0aecd72fe950d4231fc2755ace32ac4d19 Mon Sep 17 00:00:00 2001
+From: Chengming Gui <Jack.Gui@amd.com>
+Date: Tue, 9 Jul 2019 11:04:17 -0500
+Subject: [PATCH 2954/4256] drm/amd/powerplay: get smc firmware and pptable
+
+get smc firmware and pptable for arcturus
+
+Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 11 ++++++++---
+ 1 file changed, 8 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index d0764ba2705c..7d723a5e4135 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -43,6 +43,7 @@
+ #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
+ 
+ MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
++MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
+ MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
+ MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
+ 
+@@ -153,6 +154,9 @@ static int smu_v11_0_init_microcode(struct smu_context *smu)
+ 	case CHIP_VEGA20:
+ 		chip_name = "vega20";
+ 		break;
++	case CHIP_ARCTURUS:
++		chip_name = "arcturus";
++		break;
+ 	case CHIP_NAVI10:
+ 		chip_name = "navi10";
+ 		break;
+@@ -204,7 +208,7 @@ static int smu_v11_0_load_microcode(struct smu_context *smu)
+ 	uint32_t i;
+ 	uint32_t mp1_fw_flags;
+ 
+-	hdr = (const struct smc_firmware_header_v1_0 *)	adev->pm.fw->data;
++	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
+ 	src = (const uint32_t *)(adev->pm.fw->data +
+ 		le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+ 
+@@ -291,7 +295,8 @@ static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uin
+ 	return 0;
+ }
+ 
+-static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, uint32_t *size, uint32_t pptable_id)
++static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
++				      uint32_t *size, uint32_t pptable_id)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+ 	const struct smc_firmware_header_v2_1 *v2_1;
+@@ -1739,7 +1744,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
+ 	.send_smc_msg = smu_v11_0_send_msg,
+ 	.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
+ 	.read_smc_arg = smu_v11_0_read_arg,
+-	.setup_pptable= smu_v11_0_setup_pptable,
++	.setup_pptable = smu_v11_0_setup_pptable,
+ 	.init_smc_tables = smu_v11_0_init_smc_tables,
+ 	.fini_smc_tables = smu_v11_0_fini_smc_tables,
+ 	.init_power = smu_v11_0_init_power,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2955-drm-amdgpu-skip-get-update-xgmi-topology-info-when-n.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2955-drm-amdgpu-skip-get-update-xgmi-topology-info-when-n.patch
new file mode 100644
index 00000000..216c3552
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2955-drm-amdgpu-skip-get-update-xgmi-topology-info-when-n.patch
@@ -0,0 +1,83 @@
+From 488e98e88d53c8861a5e33b5824a93a8f97d2c19 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Tue, 4 Jun 2019 14:58:49 +0800
+Subject: [PATCH 2955/4256] drm/amdgpu: skip get/update xgmi topology info when
+ no psp exists
+
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 48 +++++++++++++-----------
+ 1 file changed, 26 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+index 1725c1ec1536..64940759d8c0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+@@ -296,7 +296,7 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
+ 	struct amdgpu_xgmi	*entry;
+ 	struct amdgpu_device *tmp_adev = NULL;
+ 
+-	int count = 0, ret = -EINVAL;
++	int count = 0, ret = 0;
+ 
+ 	if (!adev->gmc.xgmi.supported)
+ 		return 0;
+@@ -337,28 +337,32 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
+ 	top_info->num_nodes = count;
+ 	hive->number_devices = count;
+ 
+-	list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
+-                /* update node list for other device in the hive */
+-                if (tmp_adev != adev) {
+-                        top_info = &tmp_adev->psp.xgmi_context.top_info;
+-                        top_info->nodes[count - 1].node_id = adev->gmc.xgmi.node_id;
+-                        top_info->num_nodes = count;
++        if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
++                list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
++                        /* update node list for other device in the hive */
++                        if (tmp_adev != adev) {
++                                top_info = &tmp_adev->psp.xgmi_context.top_info;
++                                top_info->nodes[count - 1].node_id =
++                                       adev->gmc.xgmi.node_id;
++                                top_info->num_nodes = count;
++                        }
++                        ret = amdgpu_xgmi_update_topology(hive, tmp_adev);
++                        if (ret)
++                                goto exit;
+                 }
+-                ret = amdgpu_xgmi_update_topology(hive, tmp_adev);
+-                if (ret)
+-                        goto exit;
+-        }
+-
+-        /* get latest topology info for each device from psp */
+-        list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
+-		ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, top_info);
+-		if (ret) {
+-			dev_err(tmp_adev->dev,
+-				"XGMI: Get topology failure on device %llx, hive %llx, ret %d",
+-				tmp_adev->gmc.xgmi.node_id,
+-				tmp_adev->gmc.xgmi.hive_id, ret);
+-			/* To do : continue with some node failed or disable the whole hive */
+-			goto exit;
++                /* get latest topology info for each device from psp */
++                list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
++                        ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
++                                        &tmp_adev->psp.xgmi_context.top_info);
++                        if (ret) {
++                                dev_err(tmp_adev->dev,
++                                        "XGMI: Get topology failure on device %llx, hive %llx, ret %d",
++                                        tmp_adev->gmc.xgmi.node_id,
++                                        tmp_adev->gmc.xgmi.hive_id, ret);
++                                /* To do : continue with some node failed or disable the whole hive */
++                                goto exit;
++                        }
++
+ 		}
+ 	}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2956-drm-amdgpu-set-system-aperture-to-cover-whole-FB-reg.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2956-drm-amdgpu-set-system-aperture-to-cover-whole-FB-reg.patch
new file mode 100644
index 00000000..38221732
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2956-drm-amdgpu-set-system-aperture-to-cover-whole-FB-reg.patch
@@ -0,0 +1,38 @@
+From 712fba8812ded9bd169b1897abf9060f58e819db Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 26 Apr 2019 16:36:44 +0800
+Subject: [PATCH 2956/4256] drm/amdgpu: set system aperture to cover whole FB
+ region in mmhub v9.4
+
+In XGMI configuration, the FB region covers vram region from peer
+device, adjust system aperture to cover all of them
+
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+index 6b7cdaadbd70..c0eb8f0a2182 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+@@ -114,12 +114,11 @@ static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev,
+ 	WREG32_SOC15_OFFSET(MMHUB, 0,
+ 			    mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
+ 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
+-			    min(adev->gmc.vram_start, adev->gmc.agp_start)
+-			    >> 18);
++			    min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
+ 	WREG32_SOC15_OFFSET(MMHUB, 0,
+ 			    mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+ 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
+-			    max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);
++			    max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
+ 
+ 	/* Set default page address. */
+ 	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2957-drm-amdgpu-correct-ip-for-mmHDP_READ_CACHE_INVALIDAT.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2957-drm-amdgpu-correct-ip-for-mmHDP_READ_CACHE_INVALIDAT.patch
new file mode 100644
index 00000000..6aadeadc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2957-drm-amdgpu-correct-ip-for-mmHDP_READ_CACHE_INVALIDAT.patch
@@ -0,0 +1,29 @@
+From 8eb30f011c3f56cc96536aad8ec88e82caa9e9ef Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Mon, 20 May 2019 17:04:05 +0800
+Subject: [PATCH 2957/4256] drm/amdgpu: correct ip for
+ mmHDP_READ_CACHE_INVALIDATE register access
+
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 217afe23a2f6..dc09469f77c5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -702,7 +702,7 @@ static void soc15_invalidate_hdp(struct amdgpu_device *adev,
+ 				 struct amdgpu_ring *ring)
+ {
+ 	if (!ring || !ring->funcs->emit_wreg)
+-		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
++		WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
+ 	else
+ 		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
+ 			HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2958-drm-amdkfd-Set-number-of-xgmi-optimized-SDMA-engines.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2958-drm-amdkfd-Set-number-of-xgmi-optimized-SDMA-engines.patch
new file mode 100644
index 00000000..fae86153
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2958-drm-amdkfd-Set-number-of-xgmi-optimized-SDMA-engines.patch
@@ -0,0 +1,30 @@
+From f715297320e3eb1072e62342be7cec03c6945d2f Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Wed, 5 Jun 2019 15:45:26 -0500
+Subject: [PATCH 2958/4256] drm/amdkfd: Set number of xgmi optimized SDMA
+ engines for arcturus
+
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index d4169d50b9ca..2e6a5dc662f7 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -329,7 +329,8 @@ static const struct kfd_device_info arcturus_device_info = {
+ 	.supports_cwsr = true,
+ 	.needs_iommu_device = false,
+ 	.needs_pci_atomics = false,
+-	.num_sdma_engines = 8,
++	.num_sdma_engines = 2,
++	.num_xgmi_sdma_engines = 6,
+ 	.num_sdma_queues_per_engine = 8,
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2959-drm-amdgpu-add-clientID-for-2nd-vcn-instance.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2959-drm-amdgpu-add-clientID-for-2nd-vcn-instance.patch
new file mode 100644
index 00000000..b783b34c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2959-drm-amdgpu-add-clientID-for-2nd-vcn-instance.patch
@@ -0,0 +1,37 @@
+From c7343b01804dd6fbaef691be4180b2da80b1893a Mon Sep 17 00:00:00 2001
+From: James Zhu <James.Zhu@amd.com>
+Date: Tue, 4 Jun 2019 14:41:48 -0400
+Subject: [PATCH 2959/4256] drm/amdgpu/: add clientID for 2nd vcn instance
+
+add clientID for 2nd vcn instance, remove unused SOC15_IH_CLIENTID_SYSHUB.
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Reviewed-by: Leo Liu <leo.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/soc15_ih_clientid.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/include/soc15_ih_clientid.h b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h
+index 0f386b2e1f4f..1794ad1fc4fc 100644
+--- a/drivers/gpu/drm/amd/include/soc15_ih_clientid.h
++++ b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h
+@@ -42,7 +42,6 @@ enum soc15_ih_clientid {
+ 	SOC15_IH_CLIENTID_SE1SH		= 0x0b,
+ 	SOC15_IH_CLIENTID_SE2SH		= 0x0c,
+ 	SOC15_IH_CLIENTID_SE3SH		= 0x0d,
+-	SOC15_IH_CLIENTID_SYSHUB	= 0x0e,
+ 	SOC15_IH_CLIENTID_UVD1		= 0x0e,
+ 	SOC15_IH_CLIENTID_THM		= 0x0f,
+ 	SOC15_IH_CLIENTID_UVD		= 0x10,
+@@ -64,6 +63,7 @@ enum soc15_ih_clientid {
+ 	SOC15_IH_CLIENTID_MAX,
+ 
+ 	SOC15_IH_CLIENTID_VCN		= SOC15_IH_CLIENTID_UVD,
++	SOC15_IH_CLIENTID_VCN1		= SOC15_IH_CLIENTID_UVD1,
+ 	SOC15_IH_CLIENTID_SDMA2		= SOC15_IH_CLIENTID_ACP,
+ 	SOC15_IH_CLIENTID_SDMA3		= SOC15_IH_CLIENTID_DCE,
+ 	SOC15_IH_CLIENTID_SDMA4		= SOC15_IH_CLIENTID_ISP,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2960-drm-amdgpu-add-ucodeID-for-2nd-vcn-instance.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2960-drm-amdgpu-add-ucodeID-for-2nd-vcn-instance.patch
new file mode 100644
index 00000000..32d16e51
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2960-drm-amdgpu-add-ucodeID-for-2nd-vcn-instance.patch
@@ -0,0 +1,29 @@
+From 56f10a12dbef80ec74d39802c726dc98acd0f554 Mon Sep 17 00:00:00 2001
+From: James Zhu <James.Zhu@amd.com>
+Date: Tue, 4 Jun 2019 14:44:33 -0400
+Subject: [PATCH 2960/4256] drm/amdgpu/: add ucodeID for 2nd vcn instance
+
+add ucodeID for 2nd vcn instance
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Reviewed-by: Leo Liu <leo.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+index c1fb6dc86440..2be106e81eda 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+@@ -281,6 +281,7 @@ enum AMDGPU_UCODE_ID {
+ 	AMDGPU_UCODE_ID_UVD1,
+ 	AMDGPU_UCODE_ID_VCE,
+ 	AMDGPU_UCODE_ID_VCN,
++	AMDGPU_UCODE_ID_VCN1,
+ 	AMDGPU_UCODE_ID_DMCU_ERAM,
+ 	AMDGPU_UCODE_ID_DMCU_INTV,
+ 	AMDGPU_UCODE_ID_VCN0_RAM,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2961-drm-amdgpu-add-doorbell-assignment-for-2nd-vcn-insta.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2961-drm-amdgpu-add-doorbell-assignment-for-2nd-vcn-insta.patch
new file mode 100644
index 00000000..f2a8cdf4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2961-drm-amdgpu-add-doorbell-assignment-for-2nd-vcn-insta.patch
@@ -0,0 +1,43 @@
+From 5e0d8466387d41c282b51f363fb66d6aa2a0aff1 Mon Sep 17 00:00:00 2001
+From: James Zhu <James.Zhu@amd.com>
+Date: Tue, 4 Jun 2019 14:47:10 -0400
+Subject: [PATCH 2961/4256] drm/amdgpu/: add doorbell assignment for 2nd vcn
+ instance
+
+add doorbell assignment for 2nd vcn instance
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Reviewed-by: Leo Liu <leo.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
+index 790263dcc064..3fa18003d4d6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
+@@ -130,13 +130,18 @@ typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
+ 	AMDGPU_VEGA20_DOORBELL_IH                      = 0x178,
+ 	/* MMSCH: 392~407
+ 	 * overlap the doorbell assignment with VCN as they are  mutually exclusive
+-	 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
++	 * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD
+ 	 */
+-	AMDGPU_VEGA20_DOORBELL64_VCN0_1                  = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
++	AMDGPU_VEGA20_DOORBELL64_VCN0_1                  = 0x188, /* VNC0 */
+ 	AMDGPU_VEGA20_DOORBELL64_VCN2_3                  = 0x189,
+ 	AMDGPU_VEGA20_DOORBELL64_VCN4_5                  = 0x18A,
+ 	AMDGPU_VEGA20_DOORBELL64_VCN6_7                  = 0x18B,
+ 
++	AMDGPU_VEGA20_DOORBELL64_VCN8_9                  = 0x18C, /* VNC1 */
++	AMDGPU_VEGA20_DOORBELL64_VCNa_b                  = 0x18D,
++	AMDGPU_VEGA20_DOORBELL64_VCNc_d                  = 0x18E,
++	AMDGPU_VEGA20_DOORBELL64_VCNe_f                  = 0x18F,
++
+ 	AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1             = 0x188,
+ 	AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3             = 0x189,
+ 	AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5             = 0x18A,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2962-drm-amdgpu-increase-AMDGPU_MAX_RINGS-to-add-2nd-vcn-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2962-drm-amdgpu-increase-AMDGPU_MAX_RINGS-to-add-2nd-vcn-.patch
new file mode 100644
index 00000000..38a5cd99
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2962-drm-amdgpu-increase-AMDGPU_MAX_RINGS-to-add-2nd-vcn-.patch
@@ -0,0 +1,31 @@
+From b0fda5f415cf7b7dec78dd9589974901561b8a43 Mon Sep 17 00:00:00 2001
+From: James Zhu <James.Zhu@amd.com>
+Date: Tue, 9 Jul 2019 11:07:51 -0500
+Subject: [PATCH 2962/4256] drm/amdgpu/: increase AMDGPU_MAX_RINGS to add 2nd
+ vcn instance
+
+increase AMDGPU_MAX_RINGS to add 2nd vcn instance
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Reviewed-by: Leo Liu <leo.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+index 4410c97ac9b7..930316e60155 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+@@ -29,7 +29,7 @@
+ #include <drm/drm_print.h>
+ 
+ /* max number of rings */
+-#define AMDGPU_MAX_RINGS		24
++#define AMDGPU_MAX_RINGS		28
+ #define AMDGPU_MAX_GFX_RINGS		2
+ #define AMDGPU_MAX_COMPUTE_RINGS	8
+ #define AMDGPU_MAX_VCE_RINGS		3
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2963-drm-amdgpu-add-vcn-nbio-doorbell-range-setting-for-2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2963-drm-amdgpu-add-vcn-nbio-doorbell-range-setting-for-2.patch
new file mode 100644
index 00000000..fb839c52
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2963-drm-amdgpu-add-vcn-nbio-doorbell-range-setting-for-2.patch
@@ -0,0 +1,114 @@
+From 026c0ad6f39bf35f3439c8a70172686d75ee84fa Mon Sep 17 00:00:00 2001
+From: James Zhu <James.Zhu@amd.com>
+Date: Wed, 10 Jul 2019 10:50:24 -0500
+Subject: [PATCH 2963/4256] drm/amdgpu: add vcn nbio doorbell range setting for
+ 2nd vcn instance
+
+add vcn nbio doorbell range setting for 2nd vcn instance
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Reviewed-by: Leo Liu <leo.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  2 +-
+ drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c |  2 +-
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 20 +++++++++++++++++---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c  |  2 +-
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c  |  2 +-
+ 5 files changed, 21 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index de204914ddb5..c3885b95727a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -690,7 +690,7 @@ struct amdgpu_nbio_funcs {
+ 	void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
+ 			bool use_doorbell, int doorbell_index, int doorbell_size);
+ 	void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
+-			int doorbell_index);
++				   int doorbell_index, int instance);
+ 	void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
+ 					 bool enable);
+ 	void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+index 72efe32f2406..f5611c479e28 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+@@ -92,7 +92,7 @@ static void nbio_v2_3_sdma_doorbell_range(struct amdgpu_device *adev, int instan
+ }
+ 
+ static void nbio_v2_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
+-					 int doorbell_index)
++					 int doorbell_index, int instance)
+ {
+ 	u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index d8c9972a315b..910fffced43b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -42,6 +42,14 @@
+ #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK	0x00010000L
+ #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK	0x00020000L
+ 
++#define mmBIF_MMSCH1_DOORBELL_RANGE                     0x01dc
++#define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX            2
++//BIF_MMSCH1_DOORBELL_RANGE
++#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT        0x2
++#define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT          0x10
++#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK          0x00000FFCL
++#define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK            0x001F0000L
++
+ static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
+ {
+ 	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
+@@ -115,11 +123,17 @@ static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instan
+ }
+ 
+ static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
+-					 int doorbell_index)
++					 int doorbell_index, int instance)
+ {
+-	u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
++	u32 reg;
++	u32 doorbell_range;
++
++	if (instance)
++		reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE);
++	else
++		reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
+ 
+-	u32 doorbell_range = RREG32(reg);
++	doorbell_range = RREG32(reg);
+ 
+ 	if (use_doorbell) {
+ 		doorbell_range = REG_SET_FIELD(doorbell_range,
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+index 52a5e3ac9f55..2b7bb6364e5a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+@@ -245,7 +245,7 @@ static int vcn_v2_0_hw_init(void *handle)
+ 	int i, r;
+ 
+ 	adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+-		ring->doorbell_index);
++					     ring->doorbell_index, 0);
+ 
+ 	ring->sched.ready = true;
+ 	r = amdgpu_ring_test_ring(ring);
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index 840737df19c0..75fdb6881ac0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -212,7 +212,7 @@ static int vcn_v2_5_hw_init(void *handle)
+ 	int i, r;
+ 
+ 	adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+-		ring->doorbell_index);
++					     ring->doorbell_index, 0);
+ 
+ 	r = amdgpu_ring_test_ring(ring);
+ 	if (r) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2964-drm-amdgpu-modify-amdgpu_vcn-to-support-multiple-ins.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2964-drm-amdgpu-modify-amdgpu_vcn-to-support-multiple-ins.patch
new file mode 100644
index 00000000..1fb12616
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2964-drm-amdgpu-modify-amdgpu_vcn-to-support-multiple-ins.patch
@@ -0,0 +1,1382 @@
+From 6830e0603ae6d8c0eba876b4c942eb1dc8890726 Mon Sep 17 00:00:00 2001
+From: James Zhu <James.Zhu@amd.com>
+Date: Wed, 10 Jul 2019 10:53:34 -0500
+Subject: [PATCH 2964/4256] drm/amdgpu: modify amdgpu_vcn to support multiple
+ instances
+
+Arcturus has dual-VCN. Need Restruct amdgpu_device::vcn to support
+multiple vcns. There are no any logical changes here
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Reviewed-by: Leo Liu <leo.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c |   6 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |   6 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c |  68 +++++++--------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  24 ++++--
+ drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 110 ++++++++++++------------
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c   | 106 +++++++++++------------
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c   |  87 ++++++++++---------
+ 7 files changed, 210 insertions(+), 197 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+index 871b591cf64a..4f7f8ca1986d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+@@ -157,15 +157,15 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
+ 			num_rings = 1;
+ 			break;
+ 		case AMDGPU_HW_IP_VCN_DEC:
+-			rings[0] = &adev->vcn.ring_dec;
++			rings[0] = &adev->vcn.inst[0].ring_dec;
+ 			num_rings = 1;
+ 			break;
+ 		case AMDGPU_HW_IP_VCN_ENC:
+-			rings[0] = &adev->vcn.ring_enc[0];
++			rings[0] = &adev->vcn.inst[0].ring_enc[0];
+ 			num_rings = 1;
+ 			break;
+ 		case AMDGPU_HW_IP_VCN_JPEG:
+-			rings[0] = &adev->vcn.ring_jpeg;
++			rings[0] = &adev->vcn.inst[0].ring_jpeg;
+ 			num_rings = 1;
+ 			break;
+ 		}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index c21b7d5d9c28..8782a58570e2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -402,7 +402,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
+ 		break;
+ 	case AMDGPU_HW_IP_VCN_DEC:
+ 		type = AMD_IP_BLOCK_TYPE_VCN;
+-		if (adev->vcn.ring_dec.sched.ready)
++		if (adev->vcn.inst[0].ring_dec.sched.ready)
+ 			++num_rings;
+ 		ib_start_alignment = 16;
+ 		ib_size_alignment = 16;
+@@ -410,14 +410,14 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
+ 	case AMDGPU_HW_IP_VCN_ENC:
+ 		type = AMD_IP_BLOCK_TYPE_VCN;
+ 		for (i = 0; i < adev->vcn.num_enc_rings; i++)
+-			if (adev->vcn.ring_enc[i].sched.ready)
++			if (adev->vcn.inst[0].ring_enc[i].sched.ready)
+ 				++num_rings;
+ 		ib_start_alignment = 64;
+ 		ib_size_alignment = 1;
+ 		break;
+ 	case AMDGPU_HW_IP_VCN_JPEG:
+ 		type = AMD_IP_BLOCK_TYPE_VCN;
+-		if (adev->vcn.ring_jpeg.sched.ready)
++		if (adev->vcn.inst[0].ring_jpeg.sched.ready)
+ 			++num_rings;
+ 		ib_start_alignment = 16;
+ 		ib_size_alignment = 16;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+index bb0d1ef50c9c..330f355b93a9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+@@ -146,8 +146,8 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
+ 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
+ 		bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
+ 	r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
+-				    AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
+-				    &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
++				    AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[0].vcpu_bo,
++				    &adev->vcn.inst[0].gpu_addr, &adev->vcn.inst[0].cpu_addr);
+ 	if (r) {
+ 		dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
+ 		return r;
+@@ -170,7 +170,7 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
+ {
+ 	int i;
+ 
+-	kvfree(adev->vcn.saved_bo);
++	kvfree(adev->vcn.inst[0].saved_bo);
+ 
+ 	if (adev->vcn.indirect_sram) {
+ 		amdgpu_bo_free_kernel(&adev->vcn.dpg_sram_bo,
+@@ -178,16 +178,16 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
+ 			      (void **)&adev->vcn.dpg_sram_cpu_addr);
+ 	}
+ 
+-	amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo,
+-			      &adev->vcn.gpu_addr,
+-			      (void **)&adev->vcn.cpu_addr);
++	amdgpu_bo_free_kernel(&adev->vcn.inst[0].vcpu_bo,
++			      &adev->vcn.inst[0].gpu_addr,
++			      (void **)&adev->vcn.inst[0].cpu_addr);
+ 
+-	amdgpu_ring_fini(&adev->vcn.ring_dec);
++	amdgpu_ring_fini(&adev->vcn.inst[0].ring_dec);
+ 
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i)
+-		amdgpu_ring_fini(&adev->vcn.ring_enc[i]);
++		amdgpu_ring_fini(&adev->vcn.inst[0].ring_enc[i]);
+ 
+-	amdgpu_ring_fini(&adev->vcn.ring_jpeg);
++	amdgpu_ring_fini(&adev->vcn.inst[0].ring_jpeg);
+ 
+ 	release_firmware(adev->vcn.fw);
+ 
+@@ -201,17 +201,17 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev)
+ 
+ 	cancel_delayed_work_sync(&adev->vcn.idle_work);
+ 
+-	if (adev->vcn.vcpu_bo == NULL)
++	if (adev->vcn.inst[0].vcpu_bo == NULL)
+ 		return 0;
+ 
+-	size = amdgpu_bo_size(adev->vcn.vcpu_bo);
+-	ptr = adev->vcn.cpu_addr;
++	size = amdgpu_bo_size(adev->vcn.inst[0].vcpu_bo);
++	ptr = adev->vcn.inst[0].cpu_addr;
+ 
+-	adev->vcn.saved_bo = kvmalloc(size, GFP_KERNEL);
+-	if (!adev->vcn.saved_bo)
++	adev->vcn.inst[0].saved_bo = kvmalloc(size, GFP_KERNEL);
++	if (!adev->vcn.inst[0].saved_bo)
+ 		return -ENOMEM;
+ 
+-	memcpy_fromio(adev->vcn.saved_bo, ptr, size);
++	memcpy_fromio(adev->vcn.inst[0].saved_bo, ptr, size);
+ 
+ 	return 0;
+ }
+@@ -221,16 +221,16 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
+ 	unsigned size;
+ 	void *ptr;
+ 
+-	if (adev->vcn.vcpu_bo == NULL)
++	if (adev->vcn.inst[0].vcpu_bo == NULL)
+ 		return -EINVAL;
+ 
+-	size = amdgpu_bo_size(adev->vcn.vcpu_bo);
+-	ptr = adev->vcn.cpu_addr;
++	size = amdgpu_bo_size(adev->vcn.inst[0].vcpu_bo);
++	ptr = adev->vcn.inst[0].cpu_addr;
+ 
+-	if (adev->vcn.saved_bo != NULL) {
+-		memcpy_toio(ptr, adev->vcn.saved_bo, size);
+-		kvfree(adev->vcn.saved_bo);
+-		adev->vcn.saved_bo = NULL;
++	if (adev->vcn.inst[0].saved_bo != NULL) {
++		memcpy_toio(ptr, adev->vcn.inst[0].saved_bo, size);
++		kvfree(adev->vcn.inst[0].saved_bo);
++		adev->vcn.inst[0].saved_bo = NULL;
+ 	} else {
+ 		const struct common_firmware_header *hdr;
+ 		unsigned offset;
+@@ -238,7 +238,7 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
+ 		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
+ 		if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+ 			offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
+-			memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
++			memcpy_toio(adev->vcn.inst[0].cpu_addr, adev->vcn.fw->data + offset,
+ 				    le32_to_cpu(hdr->ucode_size_bytes));
+ 			size -= le32_to_cpu(hdr->ucode_size_bytes);
+ 			ptr += le32_to_cpu(hdr->ucode_size_bytes);
+@@ -257,7 +257,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
+ 	unsigned int i;
+ 
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+-		fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]);
++		fences += amdgpu_fence_count_emitted(&adev->vcn.inst[0].ring_enc[i]);
+ 	}
+ 
+ 	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)	{
+@@ -268,7 +268,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
+ 		else
+ 			new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
+ 
+-		if (amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg))
++		if (amdgpu_fence_count_emitted(&adev->vcn.inst[0].ring_jpeg))
+ 			new_state.jpeg = VCN_DPG_STATE__PAUSE;
+ 		else
+ 			new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+@@ -276,8 +276,8 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
+ 		adev->vcn.pause_dpg_mode(adev, &new_state);
+ 	}
+ 
+-	fences += amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg);
+-	fences += amdgpu_fence_count_emitted(&adev->vcn.ring_dec);
++	fences += amdgpu_fence_count_emitted(&adev->vcn.inst[0].ring_jpeg);
++	fences += amdgpu_fence_count_emitted(&adev->vcn.inst[0].ring_dec);
+ 
+ 	if (fences == 0) {
+ 		amdgpu_gfx_off_ctrl(adev, true);
+@@ -311,14 +311,14 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
+ 		unsigned int i;
+ 
+ 		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+-			fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]);
++			fences += amdgpu_fence_count_emitted(&adev->vcn.inst[0].ring_enc[i]);
+ 		}
+ 		if (fences)
+ 			new_state.fw_based = VCN_DPG_STATE__PAUSE;
+ 		else
+ 			new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
+ 
+-		if (amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg))
++		if (amdgpu_fence_count_emitted(&adev->vcn.inst[0].ring_jpeg))
+ 			new_state.jpeg = VCN_DPG_STATE__PAUSE;
+ 		else
+ 			new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+@@ -344,7 +344,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
+ 	unsigned i;
+ 	int r;
+ 
+-	WREG32(adev->vcn.external.scratch9, 0xCAFEDEAD);
++	WREG32(adev->vcn.inst[0].external.scratch9, 0xCAFEDEAD);
+ 	r = amdgpu_ring_alloc(ring, 3);
+ 	if (r)
+ 		return r;
+@@ -352,7 +352,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
+ 	amdgpu_ring_write(ring, 0xDEADBEEF);
+ 	amdgpu_ring_commit(ring);
+ 	for (i = 0; i < adev->usec_timeout; i++) {
+-		tmp = RREG32(adev->vcn.external.scratch9);
++		tmp = RREG32(adev->vcn.inst[0].external.scratch9);
+ 		if (tmp == 0xDEADBEEF)
+ 			break;
+ 		DRM_UDELAY(1);
+@@ -663,7 +663,7 @@ int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
+ 	unsigned i;
+ 	int r;
+ 
+-	WREG32(adev->vcn.external.jpeg_pitch, 0xCAFEDEAD);
++	WREG32(adev->vcn.inst[0].external.jpeg_pitch, 0xCAFEDEAD);
+ 	r = amdgpu_ring_alloc(ring, 3);
+ 	if (r)
+ 		return r;
+@@ -673,7 +673,7 @@ int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
+ 	amdgpu_ring_commit(ring);
+ 
+ 	for (i = 0; i < adev->usec_timeout; i++) {
+-		tmp = RREG32(adev->vcn.external.jpeg_pitch);
++		tmp = RREG32(adev->vcn.inst[0].external.jpeg_pitch);
+ 		if (tmp == 0xDEADBEEF)
+ 			break;
+ 		DRM_UDELAY(1);
+@@ -747,7 +747,7 @@ int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+ 	}
+ 
+ 	for (i = 0; i < adev->usec_timeout; i++) {
+-		tmp = RREG32(adev->vcn.external.jpeg_pitch);
++		tmp = RREG32(adev->vcn.inst[0].external.jpeg_pitch);
+ 		if (tmp == 0xDEADBEEF)
+ 			break;
+ 		DRM_UDELAY(1);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+index bfd8c3cea13a..d2fc47a954ab 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+@@ -30,6 +30,8 @@
+ #define AMDGPU_VCN_FIRMWARE_OFFSET	256
+ #define AMDGPU_VCN_MAX_ENC_RINGS	3
+ 
++#define AMDGPU_MAX_VCN_INSTANCES	2
++
+ #define VCN_DEC_CMD_FENCE		0x00000000
+ #define VCN_DEC_CMD_TRAP		0x00000001
+ #define VCN_DEC_CMD_WRITE_REG		0x00000004
+@@ -155,30 +157,38 @@ struct amdgpu_vcn_reg{
+ 	unsigned	jpeg_pitch;
+ };
+ 
+-struct amdgpu_vcn {
++struct amdgpu_vcn_inst {
+ 	struct amdgpu_bo	*vcpu_bo;
+ 	void			*cpu_addr;
+ 	uint64_t		gpu_addr;
+-	unsigned		fw_version;
+ 	void			*saved_bo;
+-	struct delayed_work	idle_work;
+-	const struct firmware	*fw;	/* VCN firmware */
+ 	struct amdgpu_ring	ring_dec;
+ 	struct amdgpu_ring	ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
+ 	struct amdgpu_ring	ring_jpeg;
+ 	struct amdgpu_irq_src	irq;
++	struct amdgpu_vcn_reg	external;
++};
++
++struct amdgpu_vcn {
++	unsigned		fw_version;
++	struct delayed_work	idle_work;
++	const struct firmware	*fw;	/* VCN firmware */
+ 	unsigned		num_enc_rings;
+ 	enum amd_powergating_state cur_state;
+ 	struct dpg_pause_state pause_state;
+-	struct amdgpu_vcn_reg	internal, external;
+-	int (*pause_dpg_mode)(struct amdgpu_device *adev,
+-		struct dpg_pause_state *new_state);
+ 
+ 	bool			indirect_sram;
+ 	struct amdgpu_bo	*dpg_sram_bo;
+ 	void			*dpg_sram_cpu_addr;
+ 	uint64_t		dpg_sram_gpu_addr;
+ 	uint32_t		*dpg_sram_curr_addr;
++
++	uint8_t	num_vcn_inst;
++	struct amdgpu_vcn_inst	inst[AMDGPU_MAX_VCN_INSTANCES];
++	struct amdgpu_vcn_reg	internal;
++
++	int (*pause_dpg_mode)(struct amdgpu_device *adev,
++		struct dpg_pause_state *new_state);
+ };
+ 
+ int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+index 09dc9c87ebd1..07a2f36ea7ce 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+@@ -63,6 +63,7 @@ static int vcn_v1_0_early_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
++	adev->vcn.num_vcn_inst = 1;
+ 	adev->vcn.num_enc_rings = 2;
+ 
+ 	vcn_v1_0_set_dec_ring_funcs(adev);
+@@ -87,20 +88,21 @@ static int vcn_v1_0_sw_init(void *handle)
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
+ 	/* VCN DEC TRAP */
+-	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.irq);
++	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
++			VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq);
+ 	if (r)
+ 		return r;
+ 
+ 	/* VCN ENC TRAP */
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
+-					&adev->vcn.irq);
++					&adev->vcn.inst->irq);
+ 		if (r)
+ 			return r;
+ 	}
+ 
+ 	/* VCN JPEG TRAP */
+-	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.irq);
++	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.inst->irq);
+ 	if (r)
+ 		return r;
+ 
+@@ -122,39 +124,39 @@ static int vcn_v1_0_sw_init(void *handle)
+ 	if (r)
+ 		return r;
+ 
+-	ring = &adev->vcn.ring_dec;
++	ring = &adev->vcn.inst->ring_dec;
+ 	sprintf(ring->name, "vcn_dec");
+-	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
++	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
+ 	if (r)
+ 		return r;
+ 
+-	adev->vcn.internal.scratch9 = adev->vcn.external.scratch9 =
++	adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 =
+ 		SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
+-	adev->vcn.internal.data0 = adev->vcn.external.data0 =
++	adev->vcn.internal.data0 = adev->vcn.inst->external.data0 =
+ 		SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
+-	adev->vcn.internal.data1 = adev->vcn.external.data1 =
++	adev->vcn.internal.data1 = adev->vcn.inst->external.data1 =
+ 		SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
+-	adev->vcn.internal.cmd = adev->vcn.external.cmd =
++	adev->vcn.internal.cmd = adev->vcn.inst->external.cmd =
+ 		SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
+-	adev->vcn.internal.nop = adev->vcn.external.nop =
++	adev->vcn.internal.nop = adev->vcn.inst->external.nop =
+ 		SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
+ 
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+-		ring = &adev->vcn.ring_enc[i];
++		ring = &adev->vcn.inst->ring_enc[i];
+ 		sprintf(ring->name, "vcn_enc%d", i);
+-		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
++		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
+ 		if (r)
+ 			return r;
+ 	}
+ 
+-	ring = &adev->vcn.ring_jpeg;
++	ring = &adev->vcn.inst->ring_jpeg;
+ 	sprintf(ring->name, "vcn_jpeg");
+-	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
++	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
+ 	if (r)
+ 		return r;
+ 
+ 	adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode;
+-	adev->vcn.internal.jpeg_pitch = adev->vcn.external.jpeg_pitch =
++	adev->vcn.internal.jpeg_pitch = adev->vcn.inst->external.jpeg_pitch =
+ 		SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
+ 
+ 	return 0;
+@@ -191,7 +193,7 @@ static int vcn_v1_0_sw_fini(void *handle)
+ static int vcn_v1_0_hw_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
++	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
+ 	int i, r;
+ 
+ 	r = amdgpu_ring_test_helper(ring);
+@@ -199,14 +201,14 @@ static int vcn_v1_0_hw_init(void *handle)
+ 		goto done;
+ 
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+-		ring = &adev->vcn.ring_enc[i];
++		ring = &adev->vcn.inst->ring_enc[i];
+ 		ring->sched.ready = true;
+ 		r = amdgpu_ring_test_helper(ring);
+ 		if (r)
+ 			goto done;
+ 	}
+ 
+-	ring = &adev->vcn.ring_jpeg;
++	ring = &adev->vcn.inst->ring_jpeg;
+ 	r = amdgpu_ring_test_helper(ring);
+ 	if (r)
+ 		goto done;
+@@ -229,7 +231,7 @@ static int vcn_v1_0_hw_init(void *handle)
+ static int vcn_v1_0_hw_fini(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
++	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
+ 
+ 	if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
+ 		RREG32_SOC15(VCN, 0, mmUVD_STATUS))
+@@ -304,9 +306,9 @@ static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
+ 		offset = 0;
+ 	} else {
+ 		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+-			lower_32_bits(adev->vcn.gpu_addr));
++			lower_32_bits(adev->vcn.inst->gpu_addr));
+ 		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+-			upper_32_bits(adev->vcn.gpu_addr));
++			upper_32_bits(adev->vcn.inst->gpu_addr));
+ 		offset = size;
+ 		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
+ 			     AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
+@@ -316,17 +318,17 @@ static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
+ 
+ 	/* cache window 1: stack */
+ 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
+-		     lower_32_bits(adev->vcn.gpu_addr + offset));
++		     lower_32_bits(adev->vcn.inst->gpu_addr + offset));
+ 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
+-		     upper_32_bits(adev->vcn.gpu_addr + offset));
++		     upper_32_bits(adev->vcn.inst->gpu_addr + offset));
+ 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
+ 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
+ 
+ 	/* cache window 2: context */
+ 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
+-		     lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
++		     lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
+ 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
+-		     upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
++		     upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
+ 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
+ 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
+ 
+@@ -374,9 +376,9 @@ static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
+ 		offset = 0;
+ 	} else {
+ 		WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+-			lower_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0);
++			lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
+ 		WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+-			upper_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0);
++			upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
+ 		offset = size;
+ 		WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
+ 			     AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0);
+@@ -386,9 +388,9 @@ static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
+ 
+ 	/* cache window 1: stack */
+ 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
+-		     lower_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0);
++		     lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
+ 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
+-		     upper_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0);
++		     upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
+ 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
+ 			     0xFFFFFFFF, 0);
+ 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,
+@@ -396,10 +398,10 @@ static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
+ 
+ 	/* cache window 2: context */
+ 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
+-		     lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
++		     lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
+ 			     0xFFFFFFFF, 0);
+ 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
+-		     upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
++		     upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
+ 			     0xFFFFFFFF, 0);
+ 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
+ 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
+@@ -779,7 +781,7 @@ static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
+  */
+ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
+ {
+-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
++	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
+ 	uint32_t rb_bufsz, tmp;
+ 	uint32_t lmi_swap_cntl;
+ 	int i, j, r;
+@@ -932,21 +934,21 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
+ 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
+ 			~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
+ 
+-	ring = &adev->vcn.ring_enc[0];
++	ring = &adev->vcn.inst->ring_enc[0];
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
+ 
+-	ring = &adev->vcn.ring_enc[1];
++	ring = &adev->vcn.inst->ring_enc[1];
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
+ 
+-	ring = &adev->vcn.ring_jpeg;
++	ring = &adev->vcn.inst->ring_jpeg;
+ 	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
+ 	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
+ 			UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
+@@ -968,7 +970,7 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
+ 
+ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
+ {
+-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
++	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
+ 	uint32_t rb_bufsz, tmp;
+ 	uint32_t lmi_swap_cntl;
+ 
+@@ -1106,7 +1108,7 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
+ 			~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
+ 
+ 	/* initialize JPEG wptr */
+-	ring = &adev->vcn.ring_jpeg;
++	ring = &adev->vcn.inst->ring_jpeg;
+ 	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+ 
+ 	/* copy patch commands to the jpeg ring */
+@@ -1255,21 +1257,21 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
+ 						   UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
+ 
+ 				/* Restore */
+-				ring = &adev->vcn.ring_enc[0];
++				ring = &adev->vcn.inst->ring_enc[0];
+ 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
+ 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+ 				WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
+ 				WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
+ 				WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+ 
+-				ring = &adev->vcn.ring_enc[1];
++				ring = &adev->vcn.inst->ring_enc[1];
+ 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
+ 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+ 				WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
+ 				WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
+ 				WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+ 
+-				ring = &adev->vcn.ring_dec;
++				ring = &adev->vcn.inst->ring_dec;
+ 				WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
+ 						   RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
+ 				SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
+@@ -1315,7 +1317,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
+ 							UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code);
+ 
+ 				/* Restore */
+-				ring = &adev->vcn.ring_jpeg;
++				ring = &adev->vcn.inst->ring_jpeg;
+ 				WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
+ 				WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
+ 							UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
+@@ -1329,7 +1331,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
+ 				WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
+ 							UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
+ 
+-				ring = &adev->vcn.ring_dec;
++				ring = &adev->vcn.inst->ring_dec;
+ 				WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
+ 						   RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
+ 				SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
+@@ -1596,7 +1598,7 @@ static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	if (ring == &adev->vcn.ring_enc[0])
++	if (ring == &adev->vcn.inst->ring_enc[0])
+ 		return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
+ 	else
+ 		return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
+@@ -1613,7 +1615,7 @@ static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	if (ring == &adev->vcn.ring_enc[0])
++	if (ring == &adev->vcn.inst->ring_enc[0])
+ 		return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
+ 	else
+ 		return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
+@@ -1630,7 +1632,7 @@ static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	if (ring == &adev->vcn.ring_enc[0])
++	if (ring == &adev->vcn.inst->ring_enc[0])
+ 		WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
+ 			lower_32_bits(ring->wptr));
+ 	else
+@@ -2114,16 +2116,16 @@ static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
+ 
+ 	switch (entry->src_id) {
+ 	case 124:
+-		amdgpu_fence_process(&adev->vcn.ring_dec);
++		amdgpu_fence_process(&adev->vcn.inst->ring_dec);
+ 		break;
+ 	case 119:
+-		amdgpu_fence_process(&adev->vcn.ring_enc[0]);
++		amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
+ 		break;
+ 	case 120:
+-		amdgpu_fence_process(&adev->vcn.ring_enc[1]);
++		amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
+ 		break;
+ 	case 126:
+-		amdgpu_fence_process(&adev->vcn.ring_jpeg);
++		amdgpu_fence_process(&adev->vcn.inst->ring_jpeg);
+ 		break;
+ 	default:
+ 		DRM_ERROR("Unhandled interrupt: %d %d\n",
+@@ -2295,7 +2297,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_jpeg_ring_vm_funcs = {
+ 
+ static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
+ {
+-	adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
++	adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
+ 	DRM_INFO("VCN decode is enabled in VM mode\n");
+ }
+ 
+@@ -2304,14 +2306,14 @@ static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
+ 	int i;
+ 
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i)
+-		adev->vcn.ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
++		adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
+ 
+ 	DRM_INFO("VCN encode is enabled in VM mode\n");
+ }
+ 
+ static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
+ {
+-	adev->vcn.ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs;
++	adev->vcn.inst->ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs;
+ 	DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
+ }
+ 
+@@ -2322,8 +2324,8 @@ static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
+ 
+ static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
+ {
+-	adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2;
+-	adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs;
++	adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2;
++	adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs;
+ }
+ 
+ const struct amdgpu_ip_block_version vcn_v1_0_ip_block =
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+index 2b7bb6364e5a..3cb62e448a37 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+@@ -92,6 +92,7 @@ static int vcn_v2_0_early_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
++	adev->vcn.num_vcn_inst = 1;
+ 	adev->vcn.num_enc_rings = 2;
+ 
+ 	vcn_v2_0_set_dec_ring_funcs(adev);
+@@ -118,7 +119,7 @@ static int vcn_v2_0_sw_init(void *handle)
+ 	/* VCN DEC TRAP */
+ 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
+ 			      VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,
+-			      &adev->vcn.irq);
++			      &adev->vcn.inst->irq);
+ 	if (r)
+ 		return r;
+ 
+@@ -126,15 +127,14 @@ static int vcn_v2_0_sw_init(void *handle)
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
+ 				      i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
+-				      &adev->vcn.irq);
++				      &adev->vcn.inst->irq);
+ 		if (r)
+ 			return r;
+ 	}
+ 
+ 	/* VCN JPEG TRAP */
+ 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
+-			      VCN_2_0__SRCID__JPEG_DECODE,
+-			      &adev->vcn.irq);
++			      VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst->irq);
+ 	if (r)
+ 		return r;
+ 
+@@ -156,13 +156,13 @@ static int vcn_v2_0_sw_init(void *handle)
+ 	if (r)
+ 		return r;
+ 
+-	ring = &adev->vcn.ring_dec;
++	ring = &adev->vcn.inst->ring_dec;
+ 
+ 	ring->use_doorbell = true;
+ 	ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
+ 
+ 	sprintf(ring->name, "vcn_dec");
+-	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
++	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
+ 	if (r)
+ 		return r;
+ 
+@@ -174,38 +174,38 @@ static int vcn_v2_0_sw_init(void *handle)
+ 	adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
+ 
+ 	adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
+-	adev->vcn.external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
++	adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
+ 	adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
+-	adev->vcn.external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
++	adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
+ 	adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
+-	adev->vcn.external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
++	adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
+ 	adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
+-	adev->vcn.external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
++	adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
+ 	adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
+-	adev->vcn.external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
++	adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
+ 
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+-		ring = &adev->vcn.ring_enc[i];
++		ring = &adev->vcn.inst->ring_enc[i];
+ 		ring->use_doorbell = true;
+ 		ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
+ 		sprintf(ring->name, "vcn_enc%d", i);
+-		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
++		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
+ 		if (r)
+ 			return r;
+ 	}
+ 
+-	ring = &adev->vcn.ring_jpeg;
++	ring = &adev->vcn.inst->ring_jpeg;
+ 	ring->use_doorbell = true;
+ 	ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
+ 	sprintf(ring->name, "vcn_jpeg");
+-	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
++	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
+ 	if (r)
+ 		return r;
+ 
+ 	adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
+ 
+ 	adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
+-	adev->vcn.external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
++	adev->vcn.inst->external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
+ 
+ 	return 0;
+ }
+@@ -241,7 +241,7 @@ static int vcn_v2_0_sw_fini(void *handle)
+ static int vcn_v2_0_hw_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
++	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
+ 	int i, r;
+ 
+ 	adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+@@ -255,7 +255,7 @@ static int vcn_v2_0_hw_init(void *handle)
+ 	}
+ 
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+-		ring = &adev->vcn.ring_enc[i];
++		ring = &adev->vcn.inst->ring_enc[i];
+ 		ring->sched.ready = true;
+ 		r = amdgpu_ring_test_ring(ring);
+ 		if (r) {
+@@ -264,7 +264,7 @@ static int vcn_v2_0_hw_init(void *handle)
+ 		}
+ 	}
+ 
+-	ring = &adev->vcn.ring_jpeg;
++	ring = &adev->vcn.inst->ring_jpeg;
+ 	ring->sched.ready = true;
+ 	r = amdgpu_ring_test_ring(ring);
+ 	if (r) {
+@@ -290,7 +290,7 @@ static int vcn_v2_0_hw_init(void *handle)
+ static int vcn_v2_0_hw_fini(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
++	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
+ 	int i;
+ 
+ 	if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
+@@ -301,11 +301,11 @@ static int vcn_v2_0_hw_fini(void *handle)
+ 	ring->sched.ready = false;
+ 
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+-		ring = &adev->vcn.ring_enc[i];
++		ring = &adev->vcn.inst->ring_enc[i];
+ 		ring->sched.ready = false;
+ 	}
+ 
+-	ring = &adev->vcn.ring_jpeg;
++	ring = &adev->vcn.inst->ring_jpeg;
+ 	ring->sched.ready = false;
+ 
+ 	return 0;
+@@ -375,9 +375,9 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
+ 		offset = 0;
+ 	} else {
+ 		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+-			lower_32_bits(adev->vcn.gpu_addr));
++			lower_32_bits(adev->vcn.inst->gpu_addr));
+ 		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+-			upper_32_bits(adev->vcn.gpu_addr));
++			upper_32_bits(adev->vcn.inst->gpu_addr));
+ 		offset = size;
+ 		/* No signed header for now from firmware
+ 		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
+@@ -390,17 +390,17 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
+ 
+ 	/* cache window 1: stack */
+ 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
+-		lower_32_bits(adev->vcn.gpu_addr + offset));
++		lower_32_bits(adev->vcn.inst->gpu_addr + offset));
+ 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
+-		upper_32_bits(adev->vcn.gpu_addr + offset));
++		upper_32_bits(adev->vcn.inst->gpu_addr + offset));
+ 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
+ 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
+ 
+ 	/* cache window 2: context */
+ 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
+-		lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
++		lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
+ 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
+-		upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
++		upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
+ 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
+ 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
+ 
+@@ -436,10 +436,10 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec
+ 	} else {
+ 		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ 			UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+-			lower_32_bits(adev->vcn.gpu_addr), 0, indirect);
++			lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
+ 		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ 			UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+-			upper_32_bits(adev->vcn.gpu_addr), 0, indirect);
++			upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
+ 		offset = size;
+ 		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ 			UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
+@@ -457,10 +457,10 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec
+ 	if (!indirect) {
+ 		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ 			UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
+-			lower_32_bits(adev->vcn.gpu_addr + offset), 0, indirect);
++			lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
+ 		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ 			UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
+-			upper_32_bits(adev->vcn.gpu_addr + offset), 0, indirect);
++			upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
+ 		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ 			UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
+ 	} else {
+@@ -477,10 +477,10 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec
+ 	/* cache window 2: context */
+ 	WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ 		UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+-		lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
++		lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
+ 	WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ 		UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
+-		upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
++		upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
+ 	WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ 		UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
+ 	WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+@@ -668,7 +668,7 @@ static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
+  */
+ static int jpeg_v2_0_start(struct amdgpu_device *adev)
+ {
+-	struct amdgpu_ring *ring = &adev->vcn.ring_jpeg;
++	struct amdgpu_ring *ring = &adev->vcn.inst->ring_jpeg;
+ 	uint32_t tmp;
+ 	int r = 0;
+ 
+@@ -930,7 +930,7 @@ static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
+ 
+ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
+ {
+-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
++	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
+ 	uint32_t rb_bufsz, tmp;
+ 
+ 	vcn_v2_0_enable_static_power_gating(adev);
+@@ -1056,7 +1056,7 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
+ 
+ static int vcn_v2_0_start(struct amdgpu_device *adev)
+ {
+-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
++	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
+ 	uint32_t rb_bufsz, tmp;
+ 	uint32_t lmi_swap_cntl;
+ 	int i, j, r;
+@@ -1207,14 +1207,14 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)
+ 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
+ 			lower_32_bits(ring->wptr));
+ 
+-	ring = &adev->vcn.ring_enc[0];
++	ring = &adev->vcn.inst->ring_enc[0];
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
+ 
+-	ring = &adev->vcn.ring_enc[1];
++	ring = &adev->vcn.inst->ring_enc[1];
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
+@@ -1361,14 +1361,14 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
+ 					   UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
+ 
+ 				/* Restore */
+-				ring = &adev->vcn.ring_enc[0];
++				ring = &adev->vcn.inst->ring_enc[0];
+ 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
+ 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+ 				WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
+ 				WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
+ 				WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+ 
+-				ring = &adev->vcn.ring_enc[1];
++				ring = &adev->vcn.inst->ring_enc[1];
+ 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
+ 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+ 				WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
+@@ -1660,7 +1660,7 @@ static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	if (ring == &adev->vcn.ring_enc[0])
++	if (ring == &adev->vcn.inst->ring_enc[0])
+ 		return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
+ 	else
+ 		return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
+@@ -1677,7 +1677,7 @@ static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	if (ring == &adev->vcn.ring_enc[0]) {
++	if (ring == &adev->vcn.inst->ring_enc[0]) {
+ 		if (ring->use_doorbell)
+ 			return adev->wb.wb[ring->wptr_offs];
+ 		else
+@@ -1701,7 +1701,7 @@ static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	if (ring == &adev->vcn.ring_enc[0]) {
++	if (ring == &adev->vcn.inst->ring_enc[0]) {
+ 		if (ring->use_doorbell) {
+ 			adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+ 			WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
+@@ -2075,16 +2075,16 @@ static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
+ 
+ 	switch (entry->src_id) {
+ 	case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
+-		amdgpu_fence_process(&adev->vcn.ring_dec);
++		amdgpu_fence_process(&adev->vcn.inst->ring_dec);
+ 		break;
+ 	case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
+-		amdgpu_fence_process(&adev->vcn.ring_enc[0]);
++		amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
+ 		break;
+ 	case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
+-		amdgpu_fence_process(&adev->vcn.ring_enc[1]);
++		amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
+ 		break;
+ 	case VCN_2_0__SRCID__JPEG_DECODE:
+-		amdgpu_fence_process(&adev->vcn.ring_jpeg);
++		amdgpu_fence_process(&adev->vcn.inst->ring_jpeg);
+ 		break;
+ 	default:
+ 		DRM_ERROR("Unhandled interrupt: %d %d\n",
+@@ -2233,7 +2233,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_jpeg_ring_vm_funcs = {
+ 
+ static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
+ {
+-	adev->vcn.ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
++	adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
+ 	DRM_INFO("VCN decode is enabled in VM mode\n");
+ }
+ 
+@@ -2242,14 +2242,14 @@ static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)
+ 	int i;
+ 
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i)
+-		adev->vcn.ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;
++		adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;
+ 
+ 	DRM_INFO("VCN encode is enabled in VM mode\n");
+ }
+ 
+ static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
+ {
+-	adev->vcn.ring_jpeg.funcs = &vcn_v2_0_jpeg_ring_vm_funcs;
++	adev->vcn.inst->ring_jpeg.funcs = &vcn_v2_0_jpeg_ring_vm_funcs;
+ 	DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
+ }
+ 
+@@ -2260,8 +2260,8 @@ static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {
+ 
+ static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev)
+ {
+-	adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2;
+-	adev->vcn.irq.funcs = &vcn_v2_0_irq_funcs;
++	adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2;
++	adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;
+ }
+ 
+ const struct amdgpu_ip_block_version vcn_v2_0_ip_block =
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index 75fdb6881ac0..e27351267c9e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -66,6 +66,7 @@ static int vcn_v2_5_early_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
++	adev->vcn.num_vcn_inst = 1;
+ 	adev->vcn.num_enc_rings = 2;
+ 
+ 	vcn_v2_5_set_dec_ring_funcs(adev);
+@@ -91,21 +92,21 @@ static int vcn_v2_5_sw_init(void *handle)
+ 
+ 	/* VCN DEC TRAP */
+ 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
+-			VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.irq);
++			VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[0].irq);
+ 	if (r)
+ 		return r;
+ 
+ 	/* VCN ENC TRAP */
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
+-			i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.irq);
++			i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[0].irq);
+ 		if (r)
+ 			return r;
+ 	}
+ 
+ 	/* VCN JPEG TRAP */
+ 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
+-			VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.irq);
++			VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst[0].irq);
+ 	if (r)
+ 		return r;
+ 
+@@ -127,11 +128,11 @@ static int vcn_v2_5_sw_init(void *handle)
+ 	if (r)
+ 		return r;
+ 
+-	ring = &adev->vcn.ring_dec;
++	ring = &adev->vcn.inst[0].ring_dec;
+ 	ring->use_doorbell = true;
+ 	ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
+ 	sprintf(ring->name, "vcn_dec");
+-	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
++	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[0].irq, 0);
+ 	if (r)
+ 		return r;
+ 
+@@ -143,36 +144,36 @@ static int vcn_v2_5_sw_init(void *handle)
+ 	adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
+ 
+ 	adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
+-	adev->vcn.external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
++	adev->vcn.inst[0].external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
+ 	adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
+-	adev->vcn.external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
++	adev->vcn.inst[0].external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
+ 	adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
+-	adev->vcn.external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
++	adev->vcn.inst[0].external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
+ 	adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
+-	adev->vcn.external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
++	adev->vcn.inst[0].external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
+ 	adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
+-	adev->vcn.external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
++	adev->vcn.inst[0].external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
+ 
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+-		ring = &adev->vcn.ring_enc[i];
++		ring = &adev->vcn.inst[0].ring_enc[i];
+ 		ring->use_doorbell = true;
+ 		ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
+ 		sprintf(ring->name, "vcn_enc%d", i);
+-		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
++		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[0].irq, 0);
+ 		if (r)
+ 			return r;
+ 	}
+ 
+-	ring = &adev->vcn.ring_jpeg;
++	ring = &adev->vcn.inst[0].ring_jpeg;
+ 	ring->use_doorbell = true;
+ 	ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
+ 	sprintf(ring->name, "vcn_jpeg");
+-	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
++	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[0].irq, 0);
+ 	if (r)
+ 		return r;
+ 
+ 	adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
+-	adev->vcn.external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
++	adev->vcn.inst[0].external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
+ 
+ 	return 0;
+ }
+@@ -208,7 +209,7 @@ static int vcn_v2_5_sw_fini(void *handle)
+ static int vcn_v2_5_hw_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
++	struct amdgpu_ring *ring = &adev->vcn.inst[0].ring_dec;
+ 	int i, r;
+ 
+ 	adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+@@ -221,7 +222,7 @@ static int vcn_v2_5_hw_init(void *handle)
+ 	}
+ 
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+-		ring = &adev->vcn.ring_enc[i];
++		ring = &adev->vcn.inst[0].ring_enc[i];
+ 		ring->sched.ready = false;
+ 		continue;
+ 		r = amdgpu_ring_test_ring(ring);
+@@ -231,7 +232,7 @@ static int vcn_v2_5_hw_init(void *handle)
+ 		}
+ 	}
+ 
+-	ring = &adev->vcn.ring_jpeg;
++	ring = &adev->vcn.inst[0].ring_jpeg;
+ 	r = amdgpu_ring_test_ring(ring);
+ 	if (r) {
+ 		ring->sched.ready = false;
+@@ -255,7 +256,7 @@ static int vcn_v2_5_hw_init(void *handle)
+ static int vcn_v2_5_hw_fini(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
++	struct amdgpu_ring *ring = &adev->vcn.inst[0].ring_dec;
+ 	int i;
+ 
+ 	if (RREG32_SOC15(VCN, 0, mmUVD_STATUS))
+@@ -264,11 +265,11 @@ static int vcn_v2_5_hw_fini(void *handle)
+ 	ring->sched.ready = false;
+ 
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+-		ring = &adev->vcn.ring_enc[i];
++		ring = &adev->vcn.inst[0].ring_enc[i];
+ 		ring->sched.ready = false;
+ 	}
+ 
+-	ring = &adev->vcn.ring_jpeg;
++	ring = &adev->vcn.inst[0].ring_jpeg;
+ 	ring->sched.ready = false;
+ 
+ 	return 0;
+@@ -338,9 +339,9 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
+ 		offset = 0;
+ 	} else {
+ 		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+-			lower_32_bits(adev->vcn.gpu_addr));
++			lower_32_bits(adev->vcn.inst[0].gpu_addr));
+ 		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+-			upper_32_bits(adev->vcn.gpu_addr));
++			upper_32_bits(adev->vcn.inst[0].gpu_addr));
+ 		offset = size;
+ 		/* No signed header for now from firmware
+ 		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
+@@ -352,17 +353,17 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
+ 
+ 	/* cache window 1: stack */
+ 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
+-		lower_32_bits(adev->vcn.gpu_addr + offset));
++		lower_32_bits(adev->vcn.inst[0].gpu_addr + offset));
+ 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
+-		upper_32_bits(adev->vcn.gpu_addr + offset));
++		upper_32_bits(adev->vcn.inst[0].gpu_addr + offset));
+ 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
+ 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
+ 
+ 	/* cache window 2: context */
+ 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
+-		lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
++		lower_32_bits(adev->vcn.inst[0].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
+ 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
+-		upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
++		upper_32_bits(adev->vcn.inst[0].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
+ 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
+ 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
+ }
+@@ -548,7 +549,7 @@ static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
+  */
+ static int jpeg_v2_5_start(struct amdgpu_device *adev)
+ {
+-	struct amdgpu_ring *ring = &adev->vcn.ring_jpeg;
++	struct amdgpu_ring *ring = &adev->vcn.inst[0].ring_jpeg;
+ 	uint32_t tmp;
+ 
+ 	/* disable anti hang mechanism */
+@@ -639,7 +640,7 @@ static int jpeg_v2_5_stop(struct amdgpu_device *adev)
+ 
+ static int vcn_v2_5_start(struct amdgpu_device *adev)
+ {
+-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
++	struct amdgpu_ring *ring = &adev->vcn.inst[0].ring_dec;
+ 	uint32_t rb_bufsz, tmp;
+ 	int i, j, r;
+ 
+@@ -781,14 +782,14 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
+ 	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
+ 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
+ 			lower_32_bits(ring->wptr));
+-	ring = &adev->vcn.ring_enc[0];
++	ring = &adev->vcn.inst[0].ring_enc[0];
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
+ 
+-	ring = &adev->vcn.ring_enc[1];
++	ring = &adev->vcn.inst[0].ring_enc[1];
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
+@@ -951,7 +952,7 @@ static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	if (ring == &adev->vcn.ring_enc[0])
++	if (ring == &adev->vcn.inst[0].ring_enc[0])
+ 		return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
+ 	else
+ 		return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
+@@ -968,7 +969,7 @@ static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	if (ring == &adev->vcn.ring_enc[0]) {
++	if (ring == &adev->vcn.inst[0].ring_enc[0]) {
+ 		if (ring->use_doorbell)
+ 			return adev->wb.wb[ring->wptr_offs];
+ 		else
+@@ -992,7 +993,7 @@ static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	if (ring == &adev->vcn.ring_enc[0]) {
++	if (ring == &adev->vcn.inst[0].ring_enc[0]) {
+ 		if (ring->use_doorbell) {
+ 			adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+ 			WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
+@@ -1121,7 +1122,7 @@ static const struct amdgpu_ring_funcs vcn_v2_5_jpeg_ring_vm_funcs = {
+ 
+ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
+ {
+-	adev->vcn.ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
++	adev->vcn.inst[0].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
+ 	DRM_INFO("VCN decode is enabled in VM mode\n");
+ }
+ 
+@@ -1130,14 +1131,14 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
+ 	int i;
+ 
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i)
+-		adev->vcn.ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
++		adev->vcn.inst[0].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
+ 
+ 	DRM_INFO("VCN encode is enabled in VM mode\n");
+ }
+ 
+ static void vcn_v2_5_set_jpeg_ring_funcs(struct amdgpu_device *adev)
+ {
+-	adev->vcn.ring_jpeg.funcs = &vcn_v2_5_jpeg_ring_vm_funcs;
++	adev->vcn.inst[0].ring_jpeg.funcs = &vcn_v2_5_jpeg_ring_vm_funcs;
+ 	DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
+ }
+ 
+@@ -1212,16 +1213,16 @@ static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev,
+ 
+ 	switch (entry->src_id) {
+ 	case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
+-		amdgpu_fence_process(&adev->vcn.ring_dec);
++		amdgpu_fence_process(&adev->vcn.inst[0].ring_dec);
+ 		break;
+ 	case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
+-		amdgpu_fence_process(&adev->vcn.ring_enc[0]);
++		amdgpu_fence_process(&adev->vcn.inst[0].ring_enc[0]);
+ 		break;
+ 	case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
+-		amdgpu_fence_process(&adev->vcn.ring_enc[1]);
++		amdgpu_fence_process(&adev->vcn.inst[0].ring_enc[1]);
+ 		break;
+ 	case VCN_2_0__SRCID__JPEG_DECODE:
+-		amdgpu_fence_process(&adev->vcn.ring_jpeg);
++		amdgpu_fence_process(&adev->vcn.inst[0].ring_jpeg);
+ 		break;
+ 	default:
+ 		DRM_ERROR("Unhandled interrupt: %d %d\n",
+@@ -1239,8 +1240,8 @@ static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = {
+ 
+ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
+ {
+-	adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2;
+-	adev->vcn.irq.funcs = &vcn_v2_5_irq_funcs;
++	adev->vcn.inst[0].irq.num_types = adev->vcn.num_enc_rings + 2;
++	adev->vcn.inst[0].irq.funcs = &vcn_v2_5_irq_funcs;
+ }
+ 
+ static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2965-drm-amdgpu-add-multiple-instances-support-for-Arctur.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2965-drm-amdgpu-add-multiple-instances-support-for-Arctur.patch
new file mode 100644
index 00000000..2f3ee5fa
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2965-drm-amdgpu-add-multiple-instances-support-for-Arctur.patch
@@ -0,0 +1,1833 @@
+From 009b039b27a5e490402c6e20a7e069cb47993dc4 Mon Sep 17 00:00:00 2001
+From: James Zhu <James.Zhu@amd.com>
+Date: Wed, 10 Jul 2019 11:06:37 -0500
+Subject: [PATCH 2965/4256] drm/amdgpu: add multiple instances support for
+ Arcturus
+
+Arcturus has dual-VCN. Need add multiple instances support for Arcturus.
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Reviewed-by: Leo Liu <leo.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |   20 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c |  166 ++--
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c   | 1178 ++++++++++++-----------
+ 3 files changed, 737 insertions(+), 627 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 8782a58570e2..4169f6936367 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -402,23 +402,29 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
+ 		break;
+ 	case AMDGPU_HW_IP_VCN_DEC:
+ 		type = AMD_IP_BLOCK_TYPE_VCN;
+-		if (adev->vcn.inst[0].ring_dec.sched.ready)
+-			++num_rings;
++		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
++			if (adev->vcn.inst[i].ring_dec.sched.ready)
++				++num_rings;
++		}
+ 		ib_start_alignment = 16;
+ 		ib_size_alignment = 16;
+ 		break;
+ 	case AMDGPU_HW_IP_VCN_ENC:
+ 		type = AMD_IP_BLOCK_TYPE_VCN;
+-		for (i = 0; i < adev->vcn.num_enc_rings; i++)
+-			if (adev->vcn.inst[0].ring_enc[i].sched.ready)
+-				++num_rings;
++		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
++			for (j = 0; j < adev->vcn.num_enc_rings; j++)
++				if (adev->vcn.inst[i].ring_enc[j].sched.ready)
++					++num_rings;
++		}
+ 		ib_start_alignment = 64;
+ 		ib_size_alignment = 1;
+ 		break;
+ 	case AMDGPU_HW_IP_VCN_JPEG:
+ 		type = AMD_IP_BLOCK_TYPE_VCN;
+-		if (adev->vcn.inst[0].ring_jpeg.sched.ready)
+-			++num_rings;
++		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
++			if (adev->vcn.inst[i].ring_jpeg.sched.ready)
++				++num_rings;
++		}
+ 		ib_start_alignment = 16;
+ 		ib_size_alignment = 16;
+ 		break;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+index 330f355b93a9..5016fc570211 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+@@ -64,7 +64,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
+ 	const char *fw_name;
+ 	const struct common_firmware_header *hdr;
+ 	unsigned char fw_check;
+-	int r;
++	int i, r;
+ 
+ 	INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
+ 
+@@ -145,12 +145,15 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
+ 	bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
+ 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
+ 		bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
+-	r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
+-				    AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[0].vcpu_bo,
+-				    &adev->vcn.inst[0].gpu_addr, &adev->vcn.inst[0].cpu_addr);
+-	if (r) {
+-		dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
+-		return r;
++
++	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
++		r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
++						AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo,
++						&adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr);
++		if (r) {
++			dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
++			return r;
++		}
+ 	}
+ 
+ 	if (adev->vcn.indirect_sram) {
+@@ -168,26 +171,28 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
+ 
+ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
+ {
+-	int i;
+-
+-	kvfree(adev->vcn.inst[0].saved_bo);
++	int i, j;
+ 
+ 	if (adev->vcn.indirect_sram) {
+ 		amdgpu_bo_free_kernel(&adev->vcn.dpg_sram_bo,
+-			      &adev->vcn.dpg_sram_gpu_addr,
+-			      (void **)&adev->vcn.dpg_sram_cpu_addr);
++				      &adev->vcn.dpg_sram_gpu_addr,
++				      (void **)&adev->vcn.dpg_sram_cpu_addr);
+ 	}
+ 
+-	amdgpu_bo_free_kernel(&adev->vcn.inst[0].vcpu_bo,
+-			      &adev->vcn.inst[0].gpu_addr,
+-			      (void **)&adev->vcn.inst[0].cpu_addr);
++	for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
++		kvfree(adev->vcn.inst[j].saved_bo);
+ 
+-	amdgpu_ring_fini(&adev->vcn.inst[0].ring_dec);
++		amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
++					  &adev->vcn.inst[j].gpu_addr,
++					  (void **)&adev->vcn.inst[j].cpu_addr);
+ 
+-	for (i = 0; i < adev->vcn.num_enc_rings; ++i)
+-		amdgpu_ring_fini(&adev->vcn.inst[0].ring_enc[i]);
++		amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
+ 
+-	amdgpu_ring_fini(&adev->vcn.inst[0].ring_jpeg);
++		for (i = 0; i < adev->vcn.num_enc_rings; ++i)
++			amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
++
++		amdgpu_ring_fini(&adev->vcn.inst[j].ring_jpeg);
++	}
+ 
+ 	release_firmware(adev->vcn.fw);
+ 
+@@ -198,21 +203,23 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev)
+ {
+ 	unsigned size;
+ 	void *ptr;
++	int i;
+ 
+ 	cancel_delayed_work_sync(&adev->vcn.idle_work);
+ 
+-	if (adev->vcn.inst[0].vcpu_bo == NULL)
+-		return 0;
++	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.inst[i].vcpu_bo == NULL)
++			return 0;
+ 
+-	size = amdgpu_bo_size(adev->vcn.inst[0].vcpu_bo);
+-	ptr = adev->vcn.inst[0].cpu_addr;
++		size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
++		ptr = adev->vcn.inst[i].cpu_addr;
+ 
+-	adev->vcn.inst[0].saved_bo = kvmalloc(size, GFP_KERNEL);
+-	if (!adev->vcn.inst[0].saved_bo)
+-		return -ENOMEM;
+-
+-	memcpy_fromio(adev->vcn.inst[0].saved_bo, ptr, size);
++		adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
++		if (!adev->vcn.inst[i].saved_bo)
++			return -ENOMEM;
+ 
++		memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
++	}
+ 	return 0;
+ }
+ 
+@@ -220,32 +227,34 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
+ {
+ 	unsigned size;
+ 	void *ptr;
++	int i;
+ 
+-	if (adev->vcn.inst[0].vcpu_bo == NULL)
+-		return -EINVAL;
+-
+-	size = amdgpu_bo_size(adev->vcn.inst[0].vcpu_bo);
+-	ptr = adev->vcn.inst[0].cpu_addr;
+-
+-	if (adev->vcn.inst[0].saved_bo != NULL) {
+-		memcpy_toio(ptr, adev->vcn.inst[0].saved_bo, size);
+-		kvfree(adev->vcn.inst[0].saved_bo);
+-		adev->vcn.inst[0].saved_bo = NULL;
+-	} else {
+-		const struct common_firmware_header *hdr;
+-		unsigned offset;
+-
+-		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
+-		if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+-			offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
+-			memcpy_toio(adev->vcn.inst[0].cpu_addr, adev->vcn.fw->data + offset,
+-				    le32_to_cpu(hdr->ucode_size_bytes));
+-			size -= le32_to_cpu(hdr->ucode_size_bytes);
+-			ptr += le32_to_cpu(hdr->ucode_size_bytes);
++	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.inst[i].vcpu_bo == NULL)
++			return -EINVAL;
++
++		size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
++		ptr = adev->vcn.inst[i].cpu_addr;
++
++		if (adev->vcn.inst[i].saved_bo != NULL) {
++			memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
++			kvfree(adev->vcn.inst[i].saved_bo);
++			adev->vcn.inst[i].saved_bo = NULL;
++		} else {
++			const struct common_firmware_header *hdr;
++			unsigned offset;
++
++			hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
++			if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
++				offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
++				memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
++					    le32_to_cpu(hdr->ucode_size_bytes));
++				size -= le32_to_cpu(hdr->ucode_size_bytes);
++				ptr += le32_to_cpu(hdr->ucode_size_bytes);
++			}
++			memset_io(ptr, 0, size);
+ 		}
+-		memset_io(ptr, 0, size);
+ 	}
+-
+ 	return 0;
+ }
+ 
+@@ -253,31 +262,34 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
+ {
+ 	struct amdgpu_device *adev =
+ 		container_of(work, struct amdgpu_device, vcn.idle_work.work);
+-	unsigned int fences = 0;
+-	unsigned int i;
++	unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
++	unsigned int i, j;
+ 
+-	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+-		fences += amdgpu_fence_count_emitted(&adev->vcn.inst[0].ring_enc[i]);
+-	}
++	for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
++		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
++			fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
++		}
+ 
+-	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)	{
+-		struct dpg_pause_state new_state;
++		if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)	{
++			struct dpg_pause_state new_state;
+ 
+-		if (fences)
+-			new_state.fw_based = VCN_DPG_STATE__PAUSE;
+-		else
+-			new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
++			if (fence[j])
++				new_state.fw_based = VCN_DPG_STATE__PAUSE;
++			else
++				new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
+ 
+-		if (amdgpu_fence_count_emitted(&adev->vcn.inst[0].ring_jpeg))
+-			new_state.jpeg = VCN_DPG_STATE__PAUSE;
+-		else
+-			new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
++			if (amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg))
++				new_state.jpeg = VCN_DPG_STATE__PAUSE;
++			else
++				new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+ 
+-		adev->vcn.pause_dpg_mode(adev, &new_state);
+-	}
++			adev->vcn.pause_dpg_mode(adev, &new_state);
++		}
+ 
+-	fences += amdgpu_fence_count_emitted(&adev->vcn.inst[0].ring_jpeg);
+-	fences += amdgpu_fence_count_emitted(&adev->vcn.inst[0].ring_dec);
++		fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg);
++		fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
++		fences += fence[j];
++	}
+ 
+ 	if (fences == 0) {
+ 		amdgpu_gfx_off_ctrl(adev, true);
+@@ -311,14 +323,14 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
+ 		unsigned int i;
+ 
+ 		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+-			fences += amdgpu_fence_count_emitted(&adev->vcn.inst[0].ring_enc[i]);
++			fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
+ 		}
+ 		if (fences)
+ 			new_state.fw_based = VCN_DPG_STATE__PAUSE;
+ 		else
+ 			new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
+ 
+-		if (amdgpu_fence_count_emitted(&adev->vcn.inst[0].ring_jpeg))
++		if (amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_jpeg))
+ 			new_state.jpeg = VCN_DPG_STATE__PAUSE;
+ 		else
+ 			new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+@@ -344,7 +356,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
+ 	unsigned i;
+ 	int r;
+ 
+-	WREG32(adev->vcn.inst[0].external.scratch9, 0xCAFEDEAD);
++	WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
+ 	r = amdgpu_ring_alloc(ring, 3);
+ 	if (r)
+ 		return r;
+@@ -352,7 +364,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
+ 	amdgpu_ring_write(ring, 0xDEADBEEF);
+ 	amdgpu_ring_commit(ring);
+ 	for (i = 0; i < adev->usec_timeout; i++) {
+-		tmp = RREG32(adev->vcn.inst[0].external.scratch9);
++		tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
+ 		if (tmp == 0xDEADBEEF)
+ 			break;
+ 		DRM_UDELAY(1);
+@@ -663,7 +675,7 @@ int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
+ 	unsigned i;
+ 	int r;
+ 
+-	WREG32(adev->vcn.inst[0].external.jpeg_pitch, 0xCAFEDEAD);
++	WREG32(adev->vcn.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD);
+ 	r = amdgpu_ring_alloc(ring, 3);
+ 	if (r)
+ 		return r;
+@@ -673,7 +685,7 @@ int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
+ 	amdgpu_ring_commit(ring);
+ 
+ 	for (i = 0; i < adev->usec_timeout; i++) {
+-		tmp = RREG32(adev->vcn.inst[0].external.jpeg_pitch);
++		tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch);
+ 		if (tmp == 0xDEADBEEF)
+ 			break;
+ 		DRM_UDELAY(1);
+@@ -747,7 +759,7 @@ int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+ 	}
+ 
+ 	for (i = 0; i < adev->usec_timeout; i++) {
+-		tmp = RREG32(adev->vcn.inst[0].external.jpeg_pitch);
++		tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch);
+ 		if (tmp == 0xDEADBEEF)
+ 			break;
+ 		DRM_UDELAY(1);
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index e27351267c9e..b7dc069b637c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -48,6 +48,8 @@
+ 
+ #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET			0x401f
+ 
++#define VCN25_MAX_HW_INSTANCES_ARCTURUS				2
++
+ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
+ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
+ static void vcn_v2_5_set_jpeg_ring_funcs(struct amdgpu_device *adev);
+@@ -55,6 +57,11 @@ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
+ static int vcn_v2_5_set_powergating_state(void *handle,
+ 				enum amd_powergating_state state);
+ 
++static int amdgpu_ih_clientid_vcns[] = {
++	SOC15_IH_CLIENTID_VCN,
++	SOC15_IH_CLIENTID_VCN1
++};
++
+ /**
+  * vcn_v2_5_early_init - set function pointers
+  *
+@@ -65,8 +72,11 @@ static int vcn_v2_5_set_powergating_state(void *handle,
+ static int vcn_v2_5_early_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	if (adev->asic_type == CHIP_ARCTURUS)
+ 
+-	adev->vcn.num_vcn_inst = 1;
++		adev->vcn.num_vcn_inst = VCN25_MAX_HW_INSTANCES_ARCTURUS;
++	else
++		adev->vcn.num_vcn_inst = 1;
+ 	adev->vcn.num_enc_rings = 2;
+ 
+ 	vcn_v2_5_set_dec_ring_funcs(adev);
+@@ -87,29 +97,31 @@ static int vcn_v2_5_early_init(void *handle)
+ static int vcn_v2_5_sw_init(void *handle)
+ {
+ 	struct amdgpu_ring *ring;
+-	int i, r;
++	int i, j, r;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
+-	/* VCN DEC TRAP */
+-	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
+-			VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[0].irq);
+-	if (r)
+-		return r;
++	for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
++		/* VCN DEC TRAP */
++		r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
++				VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq);
++		if (r)
++			return r;
++
++		/* VCN ENC TRAP */
++		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
++			r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
++				i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq);
++			if (r)
++				return r;
++		}
+ 
+-	/* VCN ENC TRAP */
+-	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+-		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
+-			i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[0].irq);
++		/* VCN JPEG TRAP */
++		r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
++				VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst[j].irq);
+ 		if (r)
+ 			return r;
+ 	}
+ 
+-	/* VCN JPEG TRAP */
+-	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
+-			VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst[0].irq);
+-	if (r)
+-		return r;
+-
+ 	r = amdgpu_vcn_sw_init(adev);
+ 	if (r)
+ 		return r;
+@@ -121,6 +133,13 @@ static int vcn_v2_5_sw_init(void *handle)
+ 		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
+ 		adev->firmware.fw_size +=
+ 			ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
++
++		if (adev->vcn.num_vcn_inst == VCN25_MAX_HW_INSTANCES_ARCTURUS) {
++			adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1;
++			adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw;
++			adev->firmware.fw_size +=
++				ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
++		}
+ 		DRM_INFO("PSP loading VCN firmware\n");
+ 	}
+ 
+@@ -128,52 +147,54 @@ static int vcn_v2_5_sw_init(void *handle)
+ 	if (r)
+ 		return r;
+ 
+-	ring = &adev->vcn.inst[0].ring_dec;
+-	ring->use_doorbell = true;
+-	ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
+-	sprintf(ring->name, "vcn_dec");
+-	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[0].irq, 0);
+-	if (r)
+-		return r;
+-
+-	adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
+-	adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
+-	adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
+-	adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
+-	adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
+-	adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
+-
+-	adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
+-	adev->vcn.inst[0].external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
+-	adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
+-	adev->vcn.inst[0].external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
+-	adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
+-	adev->vcn.inst[0].external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
+-	adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
+-	adev->vcn.inst[0].external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
+-	adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
+-	adev->vcn.inst[0].external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
+-
+-	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+-		ring = &adev->vcn.inst[0].ring_enc[i];
++	for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
++		adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
++		adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
++		adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
++		adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
++		adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
++		adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
++
++		adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
++		adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(UVD, j, mmUVD_SCRATCH9);
++		adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
++		adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA0);
++		adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
++		adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA1);
++		adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
++		adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_CMD);
++		adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
++		adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(UVD, j, mmUVD_NO_OP);
++
++		adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
++		adev->vcn.inst[j].external.jpeg_pitch = SOC15_REG_OFFSET(UVD, j, mmUVD_JPEG_PITCH);
++
++		ring = &adev->vcn.inst[j].ring_dec;
+ 		ring->use_doorbell = true;
+-		ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
+-		sprintf(ring->name, "vcn_enc%d", i);
+-		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[0].irq, 0);
++		ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8*j;
++		sprintf(ring->name, "vcn_dec_%d", j);
++		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0);
+ 		if (r)
+ 			return r;
+-	}
+ 
+-	ring = &adev->vcn.inst[0].ring_jpeg;
+-	ring->use_doorbell = true;
+-	ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
+-	sprintf(ring->name, "vcn_jpeg");
+-	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[0].irq, 0);
+-	if (r)
+-		return r;
++		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
++			ring = &adev->vcn.inst[j].ring_enc[i];
++			ring->use_doorbell = true;
++			ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i + 8*j;
++			sprintf(ring->name, "vcn_enc_%d.%d", j, i);
++			r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0);
++			if (r)
++				return r;
++		}
+ 
+-	adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
+-	adev->vcn.inst[0].external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
++		ring = &adev->vcn.inst[j].ring_jpeg;
++		ring->use_doorbell = true;
++		ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8*j;
++		sprintf(ring->name, "vcn_jpeg_%d", j);
++		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0);
++		if (r)
++			return r;
++	}
+ 
+ 	return 0;
+ }
+@@ -209,36 +230,39 @@ static int vcn_v2_5_sw_fini(void *handle)
+ static int vcn_v2_5_hw_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	struct amdgpu_ring *ring = &adev->vcn.inst[0].ring_dec;
+-	int i, r;
++	struct amdgpu_ring *ring;
++	int i, j, r;
+ 
+-	adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+-					     ring->doorbell_index, 0);
++	for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
++		ring = &adev->vcn.inst[j].ring_dec;
+ 
+-	r = amdgpu_ring_test_ring(ring);
+-	if (r) {
+-		ring->sched.ready = false;
+-		goto done;
+-	}
++		adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell,
++						     ring->doorbell_index, j);
+ 
+-	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+-		ring = &adev->vcn.inst[0].ring_enc[i];
+-		ring->sched.ready = false;
+-		continue;
+ 		r = amdgpu_ring_test_ring(ring);
+ 		if (r) {
+ 			ring->sched.ready = false;
+ 			goto done;
+ 		}
+-	}
+ 
+-	ring = &adev->vcn.inst[0].ring_jpeg;
+-	r = amdgpu_ring_test_ring(ring);
+-	if (r) {
+-		ring->sched.ready = false;
+-		goto done;
+-	}
++		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
++			ring = &adev->vcn.inst[j].ring_enc[i];
++			ring->sched.ready = false;
++			continue;
++			r = amdgpu_ring_test_ring(ring);
++			if (r) {
++				ring->sched.ready = false;
++				goto done;
++			}
++		}
+ 
++		ring = &adev->vcn.inst[j].ring_jpeg;
++		r = amdgpu_ring_test_ring(ring);
++		if (r) {
++			ring->sched.ready = false;
++			goto done;
++		}
++	}
+ done:
+ 	if (!r)
+ 		DRM_INFO("VCN decode and encode initialized successfully.\n");
+@@ -256,21 +280,25 @@ static int vcn_v2_5_hw_init(void *handle)
+ static int vcn_v2_5_hw_fini(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	struct amdgpu_ring *ring = &adev->vcn.inst[0].ring_dec;
++	struct amdgpu_ring *ring;
+ 	int i;
+ 
+-	if (RREG32_SOC15(VCN, 0, mmUVD_STATUS))
+-		vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
++	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		ring = &adev->vcn.inst[i].ring_dec;
+ 
+-	ring->sched.ready = false;
++		if (RREG32_SOC15(VCN, i, mmUVD_STATUS))
++			vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ 
+-	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+-		ring = &adev->vcn.inst[0].ring_enc[i];
+ 		ring->sched.ready = false;
+-	}
+ 
+-	ring = &adev->vcn.inst[0].ring_jpeg;
+-	ring->sched.ready = false;
++		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
++			ring = &adev->vcn.inst[i].ring_enc[i];
++			ring->sched.ready = false;
++		}
++
++		ring = &adev->vcn.inst[i].ring_jpeg;
++		ring->sched.ready = false;
++	}
+ 
+ 	return 0;
+ }
+@@ -328,44 +356,47 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
+ {
+ 	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
+ 	uint32_t offset;
++	int i;
+ 
+-	/* cache window 0: fw */
+-	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+-		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+-			(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
+-		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+-			(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
+-		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
+-		offset = 0;
+-	} else {
+-		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+-			lower_32_bits(adev->vcn.inst[0].gpu_addr));
+-		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+-			upper_32_bits(adev->vcn.inst[0].gpu_addr));
+-		offset = size;
+-		/* No signed header for now from firmware
+-		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
+-			AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
+-		*/
+-		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
++	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		/* cache window 0: fw */
++		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
++			WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
++				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
++			WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
++				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
++			WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
++			offset = 0;
++		} else {
++			WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
++				lower_32_bits(adev->vcn.inst[i].gpu_addr));
++			WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
++				upper_32_bits(adev->vcn.inst[i].gpu_addr));
++			offset = size;
++			/* No signed header for now from firmware
++			WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
++				AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
++			*/
++			WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
++		}
++		WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
++
++		/* cache window 1: stack */
++		WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
++			lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
++		WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
++			upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));
++		WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, 0);
++		WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
++
++		/* cache window 2: context */
++		WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
++			lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
++		WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
++			upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
++		WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, 0);
++		WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
+ 	}
+-	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
+-
+-	/* cache window 1: stack */
+-	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
+-		lower_32_bits(adev->vcn.inst[0].gpu_addr + offset));
+-	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
+-		upper_32_bits(adev->vcn.inst[0].gpu_addr + offset));
+-	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
+-	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
+-
+-	/* cache window 2: context */
+-	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
+-		lower_32_bits(adev->vcn.inst[0].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
+-	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
+-		upper_32_bits(adev->vcn.inst[0].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
+-	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
+-	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
+ }
+ 
+ /**
+@@ -380,106 +411,109 @@ static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
+ {
+ 	uint32_t data;
+ 	int ret = 0;
++	int i;
+ 
+-	/* UVD disable CGC */
+-	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
+-	if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
+-		data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+-	else
+-		data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
+-	data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+-	data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+-	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
+-
+-	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
+-	data &= ~(UVD_CGC_GATE__SYS_MASK
+-		| UVD_CGC_GATE__UDEC_MASK
+-		| UVD_CGC_GATE__MPEG2_MASK
+-		| UVD_CGC_GATE__REGS_MASK
+-		| UVD_CGC_GATE__RBC_MASK
+-		| UVD_CGC_GATE__LMI_MC_MASK
+-		| UVD_CGC_GATE__LMI_UMC_MASK
+-		| UVD_CGC_GATE__IDCT_MASK
+-		| UVD_CGC_GATE__MPRD_MASK
+-		| UVD_CGC_GATE__MPC_MASK
+-		| UVD_CGC_GATE__LBSI_MASK
+-		| UVD_CGC_GATE__LRBBM_MASK
+-		| UVD_CGC_GATE__UDEC_RE_MASK
+-		| UVD_CGC_GATE__UDEC_CM_MASK
+-		| UVD_CGC_GATE__UDEC_IT_MASK
+-		| UVD_CGC_GATE__UDEC_DB_MASK
+-		| UVD_CGC_GATE__UDEC_MP_MASK
+-		| UVD_CGC_GATE__WCB_MASK
+-		| UVD_CGC_GATE__VCPU_MASK
+-		| UVD_CGC_GATE__MMSCH_MASK);
+-
+-	WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
+-
+-	SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_CGC_GATE, 0,  0xFFFFFFFF, ret);
+-
+-	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
+-	data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
+-		| UVD_CGC_CTRL__UDEC_CM_MODE_MASK
+-		| UVD_CGC_CTRL__UDEC_IT_MODE_MASK
+-		| UVD_CGC_CTRL__UDEC_DB_MODE_MASK
+-		| UVD_CGC_CTRL__UDEC_MP_MODE_MASK
+-		| UVD_CGC_CTRL__SYS_MODE_MASK
+-		| UVD_CGC_CTRL__UDEC_MODE_MASK
+-		| UVD_CGC_CTRL__MPEG2_MODE_MASK
+-		| UVD_CGC_CTRL__REGS_MODE_MASK
+-		| UVD_CGC_CTRL__RBC_MODE_MASK
+-		| UVD_CGC_CTRL__LMI_MC_MODE_MASK
+-		| UVD_CGC_CTRL__LMI_UMC_MODE_MASK
+-		| UVD_CGC_CTRL__IDCT_MODE_MASK
+-		| UVD_CGC_CTRL__MPRD_MODE_MASK
+-		| UVD_CGC_CTRL__MPC_MODE_MASK
+-		| UVD_CGC_CTRL__LBSI_MODE_MASK
+-		| UVD_CGC_CTRL__LRBBM_MODE_MASK
+-		| UVD_CGC_CTRL__WCB_MODE_MASK
+-		| UVD_CGC_CTRL__VCPU_MODE_MASK
+-		| UVD_CGC_CTRL__MMSCH_MODE_MASK);
+-	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
+-
+-	/* turn on */
+-	data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
+-	data |= (UVD_SUVD_CGC_GATE__SRE_MASK
+-		| UVD_SUVD_CGC_GATE__SIT_MASK
+-		| UVD_SUVD_CGC_GATE__SMP_MASK
+-		| UVD_SUVD_CGC_GATE__SCM_MASK
+-		| UVD_SUVD_CGC_GATE__SDB_MASK
+-		| UVD_SUVD_CGC_GATE__SRE_H264_MASK
+-		| UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
+-		| UVD_SUVD_CGC_GATE__SIT_H264_MASK
+-		| UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
+-		| UVD_SUVD_CGC_GATE__SCM_H264_MASK
+-		| UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
+-		| UVD_SUVD_CGC_GATE__SDB_H264_MASK
+-		| UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
+-		| UVD_SUVD_CGC_GATE__SCLR_MASK
+-		| UVD_SUVD_CGC_GATE__UVD_SC_MASK
+-		| UVD_SUVD_CGC_GATE__ENT_MASK
+-		| UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
+-		| UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
+-		| UVD_SUVD_CGC_GATE__SITE_MASK
+-		| UVD_SUVD_CGC_GATE__SRE_VP9_MASK
+-		| UVD_SUVD_CGC_GATE__SCM_VP9_MASK
+-		| UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
+-		| UVD_SUVD_CGC_GATE__SDB_VP9_MASK
+-		| UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
+-	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
+-
+-	data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
+-	data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
+-		| UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
+-		| UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
+-		| UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
+-		| UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
+-		| UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
+-		| UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
+-		| UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
+-		| UVD_SUVD_CGC_CTRL__IME_MODE_MASK
+-		| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
+-	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
++	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		/* UVD disable CGC */
++		data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
++		if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
++			data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++		else
++			data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
++		data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
++		data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
++		WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
++
++		data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE);
++		data &= ~(UVD_CGC_GATE__SYS_MASK
++			| UVD_CGC_GATE__UDEC_MASK
++			| UVD_CGC_GATE__MPEG2_MASK
++			| UVD_CGC_GATE__REGS_MASK
++			| UVD_CGC_GATE__RBC_MASK
++			| UVD_CGC_GATE__LMI_MC_MASK
++			| UVD_CGC_GATE__LMI_UMC_MASK
++			| UVD_CGC_GATE__IDCT_MASK
++			| UVD_CGC_GATE__MPRD_MASK
++			| UVD_CGC_GATE__MPC_MASK
++			| UVD_CGC_GATE__LBSI_MASK
++			| UVD_CGC_GATE__LRBBM_MASK
++			| UVD_CGC_GATE__UDEC_RE_MASK
++			| UVD_CGC_GATE__UDEC_CM_MASK
++			| UVD_CGC_GATE__UDEC_IT_MASK
++			| UVD_CGC_GATE__UDEC_DB_MASK
++			| UVD_CGC_GATE__UDEC_MP_MASK
++			| UVD_CGC_GATE__WCB_MASK
++			| UVD_CGC_GATE__VCPU_MASK
++			| UVD_CGC_GATE__MMSCH_MASK);
++
++		WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data);
++
++		SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0,  0xFFFFFFFF, ret);
++
++		data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
++		data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
++			| UVD_CGC_CTRL__UDEC_CM_MODE_MASK
++			| UVD_CGC_CTRL__UDEC_IT_MODE_MASK
++			| UVD_CGC_CTRL__UDEC_DB_MODE_MASK
++			| UVD_CGC_CTRL__UDEC_MP_MODE_MASK
++			| UVD_CGC_CTRL__SYS_MODE_MASK
++			| UVD_CGC_CTRL__UDEC_MODE_MASK
++			| UVD_CGC_CTRL__MPEG2_MODE_MASK
++			| UVD_CGC_CTRL__REGS_MODE_MASK
++			| UVD_CGC_CTRL__RBC_MODE_MASK
++			| UVD_CGC_CTRL__LMI_MC_MODE_MASK
++			| UVD_CGC_CTRL__LMI_UMC_MODE_MASK
++			| UVD_CGC_CTRL__IDCT_MODE_MASK
++			| UVD_CGC_CTRL__MPRD_MODE_MASK
++			| UVD_CGC_CTRL__MPC_MODE_MASK
++			| UVD_CGC_CTRL__LBSI_MODE_MASK
++			| UVD_CGC_CTRL__LRBBM_MODE_MASK
++			| UVD_CGC_CTRL__WCB_MODE_MASK
++			| UVD_CGC_CTRL__VCPU_MODE_MASK
++			| UVD_CGC_CTRL__MMSCH_MODE_MASK);
++		WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
++
++		/* turn on */
++		data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE);
++		data |= (UVD_SUVD_CGC_GATE__SRE_MASK
++			| UVD_SUVD_CGC_GATE__SIT_MASK
++			| UVD_SUVD_CGC_GATE__SMP_MASK
++			| UVD_SUVD_CGC_GATE__SCM_MASK
++			| UVD_SUVD_CGC_GATE__SDB_MASK
++			| UVD_SUVD_CGC_GATE__SRE_H264_MASK
++			| UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
++			| UVD_SUVD_CGC_GATE__SIT_H264_MASK
++			| UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
++			| UVD_SUVD_CGC_GATE__SCM_H264_MASK
++			| UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
++			| UVD_SUVD_CGC_GATE__SDB_H264_MASK
++			| UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
++			| UVD_SUVD_CGC_GATE__SCLR_MASK
++			| UVD_SUVD_CGC_GATE__UVD_SC_MASK
++			| UVD_SUVD_CGC_GATE__ENT_MASK
++			| UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
++			| UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
++			| UVD_SUVD_CGC_GATE__SITE_MASK
++			| UVD_SUVD_CGC_GATE__SRE_VP9_MASK
++			| UVD_SUVD_CGC_GATE__SCM_VP9_MASK
++			| UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
++			| UVD_SUVD_CGC_GATE__SDB_VP9_MASK
++			| UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
++		WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data);
++
++		data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
++		data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
++			| UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
++			| UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
++			| UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
++			| UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
++			| UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
++			| UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
++			| UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
++			| UVD_SUVD_CGC_CTRL__IME_MODE_MASK
++			| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
++		WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
++	}
+ }
+ 
+ /**
+@@ -493,51 +527,54 @@ static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
+ static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
+ {
+ 	uint32_t data = 0;
++	int i;
+ 
+-	/* enable UVD CGC */
+-	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
+-	if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
+-		data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+-	else
+-		data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+-	data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+-	data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+-	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
+-
+-	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
+-	data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
+-		| UVD_CGC_CTRL__UDEC_CM_MODE_MASK
+-		| UVD_CGC_CTRL__UDEC_IT_MODE_MASK
+-		| UVD_CGC_CTRL__UDEC_DB_MODE_MASK
+-		| UVD_CGC_CTRL__UDEC_MP_MODE_MASK
+-		| UVD_CGC_CTRL__SYS_MODE_MASK
+-		| UVD_CGC_CTRL__UDEC_MODE_MASK
+-		| UVD_CGC_CTRL__MPEG2_MODE_MASK
+-		| UVD_CGC_CTRL__REGS_MODE_MASK
+-		| UVD_CGC_CTRL__RBC_MODE_MASK
+-		| UVD_CGC_CTRL__LMI_MC_MODE_MASK
+-		| UVD_CGC_CTRL__LMI_UMC_MODE_MASK
+-		| UVD_CGC_CTRL__IDCT_MODE_MASK
+-		| UVD_CGC_CTRL__MPRD_MODE_MASK
+-		| UVD_CGC_CTRL__MPC_MODE_MASK
+-		| UVD_CGC_CTRL__LBSI_MODE_MASK
+-		| UVD_CGC_CTRL__LRBBM_MODE_MASK
+-		| UVD_CGC_CTRL__WCB_MODE_MASK
+-		| UVD_CGC_CTRL__VCPU_MODE_MASK);
+-	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
+-
+-	data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
+-	data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
+-		| UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
+-		| UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
+-		| UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
+-		| UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
+-		| UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
+-		| UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
+-		| UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
+-		| UVD_SUVD_CGC_CTRL__IME_MODE_MASK
+-		| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
+-	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
++	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		/* enable UVD CGC */
++		data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
++		if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
++			data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++		else
++			data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++		data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
++		data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
++		WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
++
++		data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
++		data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
++			| UVD_CGC_CTRL__UDEC_CM_MODE_MASK
++			| UVD_CGC_CTRL__UDEC_IT_MODE_MASK
++			| UVD_CGC_CTRL__UDEC_DB_MODE_MASK
++			| UVD_CGC_CTRL__UDEC_MP_MODE_MASK
++			| UVD_CGC_CTRL__SYS_MODE_MASK
++			| UVD_CGC_CTRL__UDEC_MODE_MASK
++			| UVD_CGC_CTRL__MPEG2_MODE_MASK
++			| UVD_CGC_CTRL__REGS_MODE_MASK
++			| UVD_CGC_CTRL__RBC_MODE_MASK
++			| UVD_CGC_CTRL__LMI_MC_MODE_MASK
++			| UVD_CGC_CTRL__LMI_UMC_MODE_MASK
++			| UVD_CGC_CTRL__IDCT_MODE_MASK
++			| UVD_CGC_CTRL__MPRD_MODE_MASK
++			| UVD_CGC_CTRL__MPC_MODE_MASK
++			| UVD_CGC_CTRL__LBSI_MODE_MASK
++			| UVD_CGC_CTRL__LRBBM_MODE_MASK
++			| UVD_CGC_CTRL__WCB_MODE_MASK
++			| UVD_CGC_CTRL__VCPU_MODE_MASK);
++		WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
++
++		data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
++		data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
++			| UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
++			| UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
++			| UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
++			| UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
++			| UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
++			| UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
++			| UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
++			| UVD_SUVD_CGC_CTRL__IME_MODE_MASK
++			| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
++		WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
++	}
+ }
+ 
+ /**
+@@ -549,60 +586,64 @@ static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
+  */
+ static int jpeg_v2_5_start(struct amdgpu_device *adev)
+ {
+-	struct amdgpu_ring *ring = &adev->vcn.inst[0].ring_jpeg;
++	struct amdgpu_ring *ring;
+ 	uint32_t tmp;
++	int i;
+ 
+-	/* disable anti hang mechanism */
+-	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), 0,
+-		~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
+-
+-	/* JPEG disable CGC */
+-	tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
+-	tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+-	tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+-	tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+-	WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp);
+-
+-	tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
+-	tmp &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
+-		| JPEG_CGC_GATE__JPEG2_DEC_MASK
+-		| JPEG_CGC_GATE__JMCIF_MASK
+-		| JPEG_CGC_GATE__JRBBM_MASK);
+-	WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp);
+-
+-	tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
+-	tmp &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
+-		| JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
+-		| JPEG_CGC_CTRL__JMCIF_MODE_MASK
+-		| JPEG_CGC_CTRL__JRBBM_MODE_MASK);
+-	WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp);
+-
+-	/* MJPEG global tiling registers */
+-	WREG32_SOC15(UVD, 0, mmJPEG_DEC_GFX8_ADDR_CONFIG,
+-		adev->gfx.config.gb_addr_config);
+-	WREG32_SOC15(UVD, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG,
+-		adev->gfx.config.gb_addr_config);
+-
+-	/* enable JMI channel */
+-	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL), 0,
+-		~UVD_JMI_CNTL__SOFT_RESET_MASK);
+-
+-	/* enable System Interrupt for JRBC */
+-	WREG32_P(SOC15_REG_OFFSET(VCN, 0, mmJPEG_SYS_INT_EN),
+-		JPEG_SYS_INT_EN__DJRBC_MASK,
+-		~JPEG_SYS_INT_EN__DJRBC_MASK);
+-
+-	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
+-	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
+-	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
+-		lower_32_bits(ring->gpu_addr));
+-	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
+-		upper_32_bits(ring->gpu_addr));
+-	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
+-	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
+-	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
+-	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
+-	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
++	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		ring = &adev->vcn.inst[i].ring_jpeg;
++		/* disable anti hang mechanism */
++		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS), 0,
++			~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
++
++		/* JPEG disable CGC */
++		tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL);
++		tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++		tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
++		tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
++		WREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL, tmp);
++
++		tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_GATE);
++		tmp &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
++			| JPEG_CGC_GATE__JPEG2_DEC_MASK
++			| JPEG_CGC_GATE__JMCIF_MASK
++			| JPEG_CGC_GATE__JRBBM_MASK);
++		WREG32_SOC15(VCN, i, mmJPEG_CGC_GATE, tmp);
++
++		tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL);
++		tmp &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
++			| JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
++			| JPEG_CGC_CTRL__JMCIF_MODE_MASK
++			| JPEG_CGC_CTRL__JRBBM_MODE_MASK);
++		WREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL, tmp);
++
++		/* MJPEG global tiling registers */
++		WREG32_SOC15(UVD, i, mmJPEG_DEC_GFX8_ADDR_CONFIG,
++			adev->gfx.config.gb_addr_config);
++		WREG32_SOC15(UVD, i, mmJPEG_DEC_GFX10_ADDR_CONFIG,
++			adev->gfx.config.gb_addr_config);
++
++		/* enable JMI channel */
++		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL), 0,
++			~UVD_JMI_CNTL__SOFT_RESET_MASK);
++
++		/* enable System Interrupt for JRBC */
++		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmJPEG_SYS_INT_EN),
++			JPEG_SYS_INT_EN__DJRBC_MASK,
++			~JPEG_SYS_INT_EN__DJRBC_MASK);
++
++		WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_VMID, 0);
++		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
++		WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
++			lower_32_bits(ring->gpu_addr));
++		WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
++			upper_32_bits(ring->gpu_addr));
++		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_RPTR, 0);
++		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR, 0);
++		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_CNTL, 0x00000002L);
++		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
++		ring->wptr = RREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR);
++	}
+ 
+ 	return 0;
+ }
+@@ -617,185 +658,194 @@ static int jpeg_v2_5_start(struct amdgpu_device *adev)
+ static int jpeg_v2_5_stop(struct amdgpu_device *adev)
+ {
+ 	uint32_t tmp;
++	int i;
+ 
+-	/* reset JMI */
+-	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL),
+-		UVD_JMI_CNTL__SOFT_RESET_MASK,
+-		~UVD_JMI_CNTL__SOFT_RESET_MASK);
+-
+-	tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
+-	tmp |= (JPEG_CGC_GATE__JPEG_DEC_MASK
+-		|JPEG_CGC_GATE__JPEG2_DEC_MASK
+-		|JPEG_CGC_GATE__JMCIF_MASK
+-		|JPEG_CGC_GATE__JRBBM_MASK);
+-	WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp);
+-
+-	/* enable anti hang mechanism */
+-	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS),
+-		UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
+-		~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
++	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		/* reset JMI */
++		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL),
++			UVD_JMI_CNTL__SOFT_RESET_MASK,
++			~UVD_JMI_CNTL__SOFT_RESET_MASK);
++
++		tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_GATE);
++		tmp |= (JPEG_CGC_GATE__JPEG_DEC_MASK
++			|JPEG_CGC_GATE__JPEG2_DEC_MASK
++			|JPEG_CGC_GATE__JMCIF_MASK
++			|JPEG_CGC_GATE__JRBBM_MASK);
++		WREG32_SOC15(VCN, i, mmJPEG_CGC_GATE, tmp);
++
++		/* enable anti hang mechanism */
++		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS),
++			UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
++			~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
++	}
+ 
+ 	return 0;
+ }
+ 
+ static int vcn_v2_5_start(struct amdgpu_device *adev)
+ {
+-	struct amdgpu_ring *ring = &adev->vcn.inst[0].ring_dec;
++	struct amdgpu_ring *ring;
+ 	uint32_t rb_bufsz, tmp;
+-	int i, j, r;
++	int i, j, k, r;
+ 
+-	/* disable register anti-hang mechanism */
+-	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
+-		~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
++	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		/* disable register anti-hang mechanism */
++		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0,
++			~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
+ 
+-	/* set uvd status busy */
+-	tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
+-	WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
++		/* set uvd status busy */
++		tmp = RREG32_SOC15(UVD, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
++		WREG32_SOC15(UVD, i, mmUVD_STATUS, tmp);
++	}
+ 
+ 	/*SW clock gating */
+ 	vcn_v2_5_disable_clock_gating(adev);
+ 
+-	/* enable VCPU clock */
+-	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
+-		UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
+-
+-	/* disable master interrupt */
+-	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
+-		~UVD_MASTINT_EN__VCPU_EN_MASK);
+-
+-	/* setup mmUVD_LMI_CTRL */
+-	tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
+-	tmp &= ~0xff;
+-	WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 0x8|
+-		UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK	|
+-		UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
+-		UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+-		UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
+-
+-	/* setup mmUVD_MPC_CNTL */
+-	tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
+-	tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
+-	tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
+-	WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp);
+-
+-	/* setup UVD_MPC_SET_MUXA0 */
+-	WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
+-		((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
+-		(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
+-		(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
+-		(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
+-
+-	/* setup UVD_MPC_SET_MUXB0 */
+-	WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
+-		((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
+-		(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
+-		(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
+-		(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
+-
+-	/* setup mmUVD_MPC_SET_MUX */
+-	WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
+-		((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
+-		(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
+-		(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
++	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		/* enable VCPU clock */
++		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
++			UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
++
++		/* disable master interrupt */
++		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 0,
++			~UVD_MASTINT_EN__VCPU_EN_MASK);
++
++		/* setup mmUVD_LMI_CTRL */
++		tmp = RREG32_SOC15(UVD, i, mmUVD_LMI_CTRL);
++		tmp &= ~0xff;
++		WREG32_SOC15(UVD, i, mmUVD_LMI_CTRL, tmp | 0x8|
++			UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK	|
++			UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
++			UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
++			UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
++
++		/* setup mmUVD_MPC_CNTL */
++		tmp = RREG32_SOC15(UVD, i, mmUVD_MPC_CNTL);
++		tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
++		tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
++		WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
++
++		/* setup UVD_MPC_SET_MUXA0 */
++		WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUXA0,
++			((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
++			(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
++			(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
++			(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
++
++		/* setup UVD_MPC_SET_MUXB0 */
++		WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUXB0,
++			((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
++			(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
++			(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
++			(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
++
++		/* setup mmUVD_MPC_SET_MUX */
++		WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUX,
++			((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
++			(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
++			(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
++	}
+ 
+ 	vcn_v2_5_mc_resume(adev);
+ 
+-	/* VCN global tiling registers */
+-	WREG32_SOC15(UVD, 0, mmUVD_GFX8_ADDR_CONFIG,
+-		adev->gfx.config.gb_addr_config);
+-	WREG32_SOC15(UVD, 0, mmUVD_GFX8_ADDR_CONFIG,
+-		adev->gfx.config.gb_addr_config);
++	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		/* VCN global tiling registers */
++		WREG32_SOC15(UVD, i, mmUVD_GFX8_ADDR_CONFIG,
++			adev->gfx.config.gb_addr_config);
++		WREG32_SOC15(UVD, i, mmUVD_GFX8_ADDR_CONFIG,
++			adev->gfx.config.gb_addr_config);
+ 
+-	/* enable LMI MC and UMC channels */
+-	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
+-		~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
++		/* enable LMI MC and UMC channels */
++		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
++			~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+ 
+-	/* unblock VCPU register access */
+-	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_ARB_CTRL), 0,
+-		~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
++		/* unblock VCPU register access */
++		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_ARB_CTRL), 0,
++			~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+ 
+-	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
+-		~UVD_VCPU_CNTL__BLK_RST_MASK);
+-
+-	for (i = 0; i < 10; ++i) {
+-		uint32_t status;
++		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
++			~UVD_VCPU_CNTL__BLK_RST_MASK);
+ 
+-		for (j = 0; j < 100; ++j) {
+-			status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
++		for (k = 0; k < 10; ++k) {
++			uint32_t status;
++
++			for (j = 0; j < 100; ++j) {
++				status = RREG32_SOC15(UVD, i, mmUVD_STATUS);
++				if (status & 2)
++					break;
++				if (amdgpu_emu_mode == 1)
++					msleep(500);
++				else
++					mdelay(10);
++			}
++			r = 0;
+ 			if (status & 2)
+ 				break;
+-			if (amdgpu_emu_mode == 1)
+-				msleep(500);
+-			else
+-				mdelay(10);
+-		}
+-		r = 0;
+-		if (status & 2)
+-			break;
+-
+-		DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
+-		WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
+-			UVD_VCPU_CNTL__BLK_RST_MASK,
+-			~UVD_VCPU_CNTL__BLK_RST_MASK);
+-		mdelay(10);
+-		WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
+-			~UVD_VCPU_CNTL__BLK_RST_MASK);
+ 
+-		mdelay(10);
+-		r = -1;
+-	}
++			DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
++			WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
++				UVD_VCPU_CNTL__BLK_RST_MASK,
++				~UVD_VCPU_CNTL__BLK_RST_MASK);
++			mdelay(10);
++			WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
++				~UVD_VCPU_CNTL__BLK_RST_MASK);
+ 
+-	if (r) {
+-		DRM_ERROR("VCN decode not responding, giving up!!!\n");
+-		return r;
+-	}
++			mdelay(10);
++			r = -1;
++		}
+ 
+-	/* enable master interrupt */
+-	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
+-		UVD_MASTINT_EN__VCPU_EN_MASK,
+-		~UVD_MASTINT_EN__VCPU_EN_MASK);
+-
+-	/* clear the busy bit of VCN_STATUS */
+-	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
+-		~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+-
+-	WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0);
+-
+-	/* force RBC into idle state */
+-	rb_bufsz = order_base_2(ring->ring_size);
+-	tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
+-	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
+-	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
+-	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
+-	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
+-	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
+-
+-	/* programm the RB_BASE for ring buffer */
+-	WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
+-		lower_32_bits(ring->gpu_addr));
+-	WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
+-		upper_32_bits(ring->gpu_addr));
+-
+-	/* Initialize the ring buffer's read and write pointers */
+-	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
+-
+-	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
+-	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
+-			lower_32_bits(ring->wptr));
+-	ring = &adev->vcn.inst[0].ring_enc[0];
+-	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
+-	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+-	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
+-	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+-	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
+-
+-	ring = &adev->vcn.inst[0].ring_enc[1];
+-	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
+-	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+-	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
+-	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+-	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
++		if (r) {
++			DRM_ERROR("VCN decode not responding, giving up!!!\n");
++			return r;
++		}
+ 
++		/* enable master interrupt */
++		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
++			UVD_MASTINT_EN__VCPU_EN_MASK,
++			~UVD_MASTINT_EN__VCPU_EN_MASK);
++
++		/* clear the busy bit of VCN_STATUS */
++		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0,
++			~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
++
++		WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_VMID, 0);
++
++		ring = &adev->vcn.inst[i].ring_dec;
++		/* force RBC into idle state */
++		rb_bufsz = order_base_2(ring->ring_size);
++		tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
++		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
++		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
++		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
++		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
++		WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, tmp);
++
++		/* programm the RB_BASE for ring buffer */
++		WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
++			lower_32_bits(ring->gpu_addr));
++		WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
++			upper_32_bits(ring->gpu_addr));
++
++		/* Initialize the ring buffer's read and write pointers */
++		WREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR, 0);
++
++		ring->wptr = RREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR);
++		WREG32_SOC15(UVD, i, mmUVD_RBC_RB_WPTR,
++				lower_32_bits(ring->wptr));
++		ring = &adev->vcn.inst[i].ring_enc[0];
++		WREG32_SOC15(UVD, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
++		WREG32_SOC15(UVD, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
++		WREG32_SOC15(UVD, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
++		WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
++		WREG32_SOC15(UVD, i, mmUVD_RB_SIZE, ring->ring_size / 4);
++
++		ring = &adev->vcn.inst[i].ring_enc[1];
++		WREG32_SOC15(UVD, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
++		WREG32_SOC15(UVD, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
++		WREG32_SOC15(UVD, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
++		WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
++		WREG32_SOC15(UVD, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
++	}
+ 	r = jpeg_v2_5_start(adev);
+ 
+ 	return r;
+@@ -804,59 +854,61 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
+ static int vcn_v2_5_stop(struct amdgpu_device *adev)
+ {
+ 	uint32_t tmp;
+-	int r;
++	int i, r;
+ 
+ 	r = jpeg_v2_5_stop(adev);
+ 	if (r)
+ 		return r;
+ 
+-	/* wait for vcn idle */
+-	SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
+-	if (r)
+-		return r;
++	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		/* wait for vcn idle */
++		SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
++		if (r)
++			return r;
+ 
+-	tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
+-		UVD_LMI_STATUS__READ_CLEAN_MASK |
+-		UVD_LMI_STATUS__WRITE_CLEAN_MASK |
+-		UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
+-	SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
+-	if (r)
+-		return r;
++		tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
++			UVD_LMI_STATUS__READ_CLEAN_MASK |
++			UVD_LMI_STATUS__WRITE_CLEAN_MASK |
++			UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
++		SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r);
++		if (r)
++			return r;
+ 
+-	/* block LMI UMC channel */
+-	tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);
+-	tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
+-	WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp);
++		/* block LMI UMC channel */
++		tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
++		tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
++		WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
+ 
+-	tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
+-		UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
+-	SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
+-	if (r)
+-		return r;
++		tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
++			UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
++		SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r);
++		if (r)
++			return r;
+ 
+-	/* block VCPU register access */
+-	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_ARB_CTRL),
+-		UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
+-		~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
++		/* block VCPU register access */
++		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_ARB_CTRL),
++			UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
++			~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+ 
+-	/* reset VCPU */
+-	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
+-		UVD_VCPU_CNTL__BLK_RST_MASK,
+-		~UVD_VCPU_CNTL__BLK_RST_MASK);
++		/* reset VCPU */
++		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
++			UVD_VCPU_CNTL__BLK_RST_MASK,
++			~UVD_VCPU_CNTL__BLK_RST_MASK);
+ 
+-	/* disable VCPU clock */
+-	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
+-		~(UVD_VCPU_CNTL__CLK_EN_MASK));
++		/* disable VCPU clock */
++		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
++			~(UVD_VCPU_CNTL__CLK_EN_MASK));
+ 
+-	/* clear status */
+-	WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
++		/* clear status */
++		WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
+ 
+-	vcn_v2_5_enable_clock_gating(adev);
++		vcn_v2_5_enable_clock_gating(adev);
+ 
+-	/* enable register anti-hang mechanism */
+-	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
+-		UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,
+-		~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
++		/* enable register anti-hang mechanism */
++		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS),
++			UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,
++			~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
++	}
+ 
+ 	return 0;
+ }
+@@ -872,7 +924,7 @@ static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
++	return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
+ }
+ 
+ /**
+@@ -889,7 +941,7 @@ static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
+ 	if (ring->use_doorbell)
+ 		return adev->wb.wb[ring->wptr_offs];
+ 	else
+-		return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
++		return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
+ }
+ 
+ /**
+@@ -907,7 +959,7 @@ static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
+ 		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+ 		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
+ 	} else {
+-		WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
++		WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
+ 	}
+ }
+ 
+@@ -952,10 +1004,10 @@ static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	if (ring == &adev->vcn.inst[0].ring_enc[0])
+-		return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
++	if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
++		return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);
+ 	else
+-		return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
++		return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);
+ }
+ 
+ /**
+@@ -969,16 +1021,16 @@ static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	if (ring == &adev->vcn.inst[0].ring_enc[0]) {
++	if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
+ 		if (ring->use_doorbell)
+ 			return adev->wb.wb[ring->wptr_offs];
+ 		else
+-			return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
++			return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);
+ 	} else {
+ 		if (ring->use_doorbell)
+ 			return adev->wb.wb[ring->wptr_offs];
+ 		else
+-			return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
++			return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);
+ 	}
+ }
+ 
+@@ -993,19 +1045,19 @@ static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	if (ring == &adev->vcn.inst[0].ring_enc[0]) {
++	if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
+ 		if (ring->use_doorbell) {
+ 			adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+ 			WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
+ 		} else {
+-			WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
++			WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+ 		}
+ 	} else {
+ 		if (ring->use_doorbell) {
+ 			adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+ 			WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
+ 		} else {
+-			WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
++			WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+ 		}
+ 	}
+ }
+@@ -1051,7 +1103,7 @@ static uint64_t vcn_v2_5_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+-	return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
++	return RREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_RPTR);
+ }
+ 
+ /**
+@@ -1068,7 +1120,7 @@ static uint64_t vcn_v2_5_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
+ 	if (ring->use_doorbell)
+ 		return adev->wb.wb[ring->wptr_offs];
+ 	else
+-		return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
++		return RREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_WPTR);
+ }
+ 
+ /**
+@@ -1086,7 +1138,7 @@ static void vcn_v2_5_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
+ 		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+ 		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
+ 	} else {
+-		WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
++		WREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
+ 	}
+ }
+ 
+@@ -1122,40 +1174,62 @@ static const struct amdgpu_ring_funcs vcn_v2_5_jpeg_ring_vm_funcs = {
+ 
+ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
+ {
+-	adev->vcn.inst[0].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
+-	DRM_INFO("VCN decode is enabled in VM mode\n");
++	int i;
++
++	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
++		adev->vcn.inst[i].ring_dec.me = i;
++		DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i);
++	}
+ }
+ 
+ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
+ {
+-	int i;
+-
+-	for (i = 0; i < adev->vcn.num_enc_rings; ++i)
+-		adev->vcn.inst[0].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
++	int i, j;
+ 
+-	DRM_INFO("VCN encode is enabled in VM mode\n");
++	for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
++		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
++			adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
++			adev->vcn.inst[j].ring_enc[i].me = j;
++		}
++		DRM_INFO("VCN(%d) encode is enabled in VM mode\n", j);
++	}
+ }
+ 
+ static void vcn_v2_5_set_jpeg_ring_funcs(struct amdgpu_device *adev)
+ {
+-	adev->vcn.inst[0].ring_jpeg.funcs = &vcn_v2_5_jpeg_ring_vm_funcs;
+-	DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
++	int i;
++
++	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		adev->vcn.inst[i].ring_jpeg.funcs = &vcn_v2_5_jpeg_ring_vm_funcs;
++		adev->vcn.inst[i].ring_jpeg.me = i;
++		DRM_INFO("VCN(%d) jpeg decode is enabled in VM mode\n", i);
++	}
+ }
+ 
+ static bool vcn_v2_5_is_idle(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	int i, ret = 1;
++
++	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
++	}
+ 
+-	return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
++	return ret;
+ }
+ 
+ static int vcn_v2_5_wait_for_idle(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	int ret = 0;
++	int i, ret = 0;
+ 
+-	SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
+-		UVD_STATUS__IDLE, ret);
++	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
++			UVD_STATUS__IDLE, ret);
++		if (ret)
++			return ret;
++	}
+ 
+ 	return ret;
+ }
+@@ -1209,20 +1283,34 @@ static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev,
+ 				      struct amdgpu_irq_src *source,
+ 				      struct amdgpu_iv_entry *entry)
+ {
++	uint32_t ip_instance;
++
++	switch (entry->client_id) {
++	case SOC15_IH_CLIENTID_VCN:
++		ip_instance = 0;
++		break;
++	case SOC15_IH_CLIENTID_VCN1:
++		ip_instance = 1;
++		break;
++	default:
++		DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
++		return 0;
++	}
++
+ 	DRM_DEBUG("IH: VCN TRAP\n");
+ 
+ 	switch (entry->src_id) {
+ 	case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
+-		amdgpu_fence_process(&adev->vcn.inst[0].ring_dec);
++		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
+ 		break;
+ 	case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
+-		amdgpu_fence_process(&adev->vcn.inst[0].ring_enc[0]);
++		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
+ 		break;
+ 	case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
+-		amdgpu_fence_process(&adev->vcn.inst[0].ring_enc[1]);
++		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
+ 		break;
+ 	case VCN_2_0__SRCID__JPEG_DECODE:
+-		amdgpu_fence_process(&adev->vcn.inst[0].ring_jpeg);
++		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_jpeg);
+ 		break;
+ 	default:
+ 		DRM_ERROR("Unhandled interrupt: %d %d\n",
+@@ -1240,8 +1328,12 @@ static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = {
+ 
+ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
+ {
+-	adev->vcn.inst[0].irq.num_types = adev->vcn.num_enc_rings + 2;
+-	adev->vcn.inst[0].irq.funcs = &vcn_v2_5_irq_funcs;
++	int i;
++
++	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 2;
++		adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs;
++	}
+ }
+ 
+ static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2966-drm-amdgpu-add-harvest-support-for-Arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2966-drm-amdgpu-add-harvest-support-for-Arcturus.patch
new file mode 100644
index 00000000..36011030
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2966-drm-amdgpu-add-harvest-support-for-Arcturus.patch
@@ -0,0 +1,328 @@
+From 5060751f184942b73d5e2ef1c0dcdfcc4f2d78b4 Mon Sep 17 00:00:00 2001
+From: James Zhu <James.Zhu@amd.com>
+Date: Wed, 10 Jul 2019 12:07:29 -0500
+Subject: [PATCH 2966/4256] drm/amdgpu: add harvest support for Arcturus
+
+Add harvest support for Arcturus
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Reviewed-by: Leo Liu <leo.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  9 ++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 11 +++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  4 ++
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c   | 55 ++++++++++++++++++++++++-
+ 4 files changed, 77 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 4169f6936367..141b86c1d3db 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -403,6 +403,9 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
+ 	case AMDGPU_HW_IP_VCN_DEC:
+ 		type = AMD_IP_BLOCK_TYPE_VCN;
+ 		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
++			if (adev->uvd.harvest_config & (1 << i))
++				continue;
++
+ 			if (adev->vcn.inst[i].ring_dec.sched.ready)
+ 				++num_rings;
+ 		}
+@@ -412,6 +415,9 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
+ 	case AMDGPU_HW_IP_VCN_ENC:
+ 		type = AMD_IP_BLOCK_TYPE_VCN;
+ 		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
++			if (adev->uvd.harvest_config & (1 << i))
++				continue;
++
+ 			for (j = 0; j < adev->vcn.num_enc_rings; j++)
+ 				if (adev->vcn.inst[i].ring_enc[j].sched.ready)
+ 					++num_rings;
+@@ -422,6 +428,9 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
+ 	case AMDGPU_HW_IP_VCN_JPEG:
+ 		type = AMD_IP_BLOCK_TYPE_VCN;
+ 		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
++			if (adev->uvd.harvest_config & (1 << i))
++				continue;
++
+ 			if (adev->vcn.inst[i].ring_jpeg.sched.ready)
+ 				++num_rings;
+ 		}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+index 5016fc570211..be34bdc47174 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+@@ -147,6 +147,9 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
+ 		bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
++		if (adev->vcn.harvest_config & (1 << i))
++			continue;
++
+ 		r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
+ 						AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo,
+ 						&adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr);
+@@ -180,6 +183,8 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
+ 	}
+ 
+ 	for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
++		if (adev->vcn.harvest_config & (1 << j))
++			continue;
+ 		kvfree(adev->vcn.inst[j].saved_bo);
+ 
+ 		amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
+@@ -208,6 +213,8 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev)
+ 	cancel_delayed_work_sync(&adev->vcn.idle_work);
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.harvest_config & (1 << i))
++			continue;
+ 		if (adev->vcn.inst[i].vcpu_bo == NULL)
+ 			return 0;
+ 
+@@ -230,6 +237,8 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
+ 	int i;
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.harvest_config & (1 << i))
++			continue;
+ 		if (adev->vcn.inst[i].vcpu_bo == NULL)
+ 			return -EINVAL;
+ 
+@@ -266,6 +275,8 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
+ 	unsigned int i, j;
+ 
+ 	for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
++		if (adev->vcn.harvest_config & (1 << j))
++			continue;
+ 		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ 			fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
+ 		}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+index d2fc47a954ab..38f0d53a6381 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+@@ -32,6 +32,9 @@
+ 
+ #define AMDGPU_MAX_VCN_INSTANCES	2
+ 
++#define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
++#define AMDGPU_VCN_HARVEST_VCN1 (1 << 1)
++
+ #define VCN_DEC_CMD_FENCE		0x00000000
+ #define VCN_DEC_CMD_TRAP		0x00000001
+ #define VCN_DEC_CMD_WRITE_REG		0x00000004
+@@ -187,6 +190,7 @@ struct amdgpu_vcn {
+ 	struct amdgpu_vcn_inst	inst[AMDGPU_MAX_VCN_INSTANCES];
+ 	struct amdgpu_vcn_reg	internal;
+ 
++	unsigned	harvest_config;
+ 	int (*pause_dpg_mode)(struct amdgpu_device *adev,
+ 		struct dpg_pause_state *new_state);
+ };
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index b7dc069b637c..ef8bb67844be 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -72,11 +72,24 @@ static int amdgpu_ih_clientid_vcns[] = {
+ static int vcn_v2_5_early_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	if (adev->asic_type == CHIP_ARCTURUS)
++	if (adev->asic_type == CHIP_ARCTURUS) {
++		u32 harvest;
++		int i;
+ 
+ 		adev->vcn.num_vcn_inst = VCN25_MAX_HW_INSTANCES_ARCTURUS;
+-	else
++		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
++			harvest = RREG32_SOC15(UVD, i, mmCC_UVD_HARVESTING);
++			if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
++				adev->vcn.harvest_config |= 1 << i;
++		}
++
++		if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
++						 AMDGPU_VCN_HARVEST_VCN1))
++			/* both instances are harvested, disable the block */
++			return -ENOENT;
++	} else
+ 		adev->vcn.num_vcn_inst = 1;
++
+ 	adev->vcn.num_enc_rings = 2;
+ 
+ 	vcn_v2_5_set_dec_ring_funcs(adev);
+@@ -101,6 +114,8 @@ static int vcn_v2_5_sw_init(void *handle)
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
+ 	for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
++		if (adev->vcn.harvest_config & (1 << j))
++			continue;
+ 		/* VCN DEC TRAP */
+ 		r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
+ 				VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq);
+@@ -148,6 +163,8 @@ static int vcn_v2_5_sw_init(void *handle)
+ 		return r;
+ 
+ 	for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
++		if (adev->vcn.harvest_config & (1 << j))
++			continue;
+ 		adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
+ 		adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
+ 		adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
+@@ -234,6 +251,8 @@ static int vcn_v2_5_hw_init(void *handle)
+ 	int i, j, r;
+ 
+ 	for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
++		if (adev->vcn.harvest_config & (1 << j))
++			continue;
+ 		ring = &adev->vcn.inst[j].ring_dec;
+ 
+ 		adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+@@ -284,6 +303,8 @@ static int vcn_v2_5_hw_fini(void *handle)
+ 	int i;
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.harvest_config & (1 << i))
++			continue;
+ 		ring = &adev->vcn.inst[i].ring_dec;
+ 
+ 		if (RREG32_SOC15(VCN, i, mmUVD_STATUS))
+@@ -359,6 +380,8 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
+ 	int i;
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.harvest_config & (1 << i))
++			continue;
+ 		/* cache window 0: fw */
+ 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ 			WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+@@ -414,6 +437,8 @@ static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
+ 	int i;
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.harvest_config & (1 << i))
++			continue;
+ 		/* UVD disable CGC */
+ 		data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
+ 		if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
+@@ -530,6 +555,8 @@ static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
+ 	int i;
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.harvest_config & (1 << i))
++			continue;
+ 		/* enable UVD CGC */
+ 		data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
+ 		if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
+@@ -591,6 +618,8 @@ static int jpeg_v2_5_start(struct amdgpu_device *adev)
+ 	int i;
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.harvest_config & (1 << i))
++			continue;
+ 		ring = &adev->vcn.inst[i].ring_jpeg;
+ 		/* disable anti hang mechanism */
+ 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS), 0,
+@@ -661,6 +690,8 @@ static int jpeg_v2_5_stop(struct amdgpu_device *adev)
+ 	int i;
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.harvest_config & (1 << i))
++			continue;
+ 		/* reset JMI */
+ 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL),
+ 			UVD_JMI_CNTL__SOFT_RESET_MASK,
+@@ -689,6 +720,8 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
+ 	int i, j, k, r;
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.harvest_config & (1 << i))
++			continue;
+ 		/* disable register anti-hang mechanism */
+ 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0,
+ 			~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
+@@ -702,6 +735,8 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
+ 	vcn_v2_5_disable_clock_gating(adev);
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.harvest_config & (1 << i))
++			continue;
+ 		/* enable VCPU clock */
+ 		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
+ 			UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
+@@ -749,6 +784,8 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
+ 	vcn_v2_5_mc_resume(adev);
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.harvest_config & (1 << i))
++			continue;
+ 		/* VCN global tiling registers */
+ 		WREG32_SOC15(UVD, i, mmUVD_GFX8_ADDR_CONFIG,
+ 			adev->gfx.config.gb_addr_config);
+@@ -861,6 +898,8 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev)
+ 		return r;
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.harvest_config & (1 << i))
++			continue;
+ 		/* wait for vcn idle */
+ 		SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
+ 		if (r)
+@@ -1177,6 +1216,8 @@ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
+ 	int i;
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.harvest_config & (1 << i))
++			continue;
+ 		adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
+ 		adev->vcn.inst[i].ring_dec.me = i;
+ 		DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i);
+@@ -1188,6 +1229,8 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
+ 	int i, j;
+ 
+ 	for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
++		if (adev->vcn.harvest_config & (1 << j))
++			continue;
+ 		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ 			adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
+ 			adev->vcn.inst[j].ring_enc[i].me = j;
+@@ -1201,6 +1244,8 @@ static void vcn_v2_5_set_jpeg_ring_funcs(struct amdgpu_device *adev)
+ 	int i;
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.harvest_config & (1 << i))
++			continue;
+ 		adev->vcn.inst[i].ring_jpeg.funcs = &vcn_v2_5_jpeg_ring_vm_funcs;
+ 		adev->vcn.inst[i].ring_jpeg.me = i;
+ 		DRM_INFO("VCN(%d) jpeg decode is enabled in VM mode\n", i);
+@@ -1213,6 +1258,8 @@ static bool vcn_v2_5_is_idle(void *handle)
+ 	int i, ret = 1;
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.harvest_config & (1 << i))
++			continue;
+ 		ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
+ 	}
+ 
+@@ -1225,6 +1272,8 @@ static int vcn_v2_5_wait_for_idle(void *handle)
+ 	int i, ret = 0;
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.harvest_config & (1 << i))
++			continue;
+ 		SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
+ 			UVD_STATUS__IDLE, ret);
+ 		if (ret)
+@@ -1331,6 +1380,8 @@ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
+ 	int i;
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
++		if (adev->vcn.harvest_config & (1 << i))
++			continue;
+ 		adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 2;
+ 		adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2967-drm-amdgpu-assign-fb_start-end-in-mmhub-v9.4-interfa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2967-drm-amdgpu-assign-fb_start-end-in-mmhub-v9.4-interfa.patch
new file mode 100644
index 00000000..4076fb50
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2967-drm-amdgpu-assign-fb_start-end-in-mmhub-v9.4-interfa.patch
@@ -0,0 +1,40 @@
+From 09c4feb7c39494538f42e8c7aea75546df4c3907 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Mon, 22 Apr 2019 17:14:59 +0800
+Subject: [PATCH 2967/4256] drm/amdgpu: assign fb_start/end in mmhub v9.4
+ interface
+
+Align with mmhub v1.0.
+
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+index c0eb8f0a2182..33b0de54a5da 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+@@ -39,10 +39,17 @@ u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev)
+ {
+ 	/* The base should be same b/t 2 mmhubs on Acrturus. Read one here. */
+ 	u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE);
++	u64 top = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP);
+ 
+ 	base &= VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
+ 	base <<= 24;
+ 
++	top &= VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
++	top <<= 24;
++
++	adev->gmc.fb_start = base;
++	adev->gmc.fb_end = top;
++
+ 	return base;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2968-drm-amdgpu-add-pci-DID-for-Arcturus-GL-XL.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2968-drm-amdgpu-add-pci-DID-for-Arcturus-GL-XL.patch
new file mode 100644
index 00000000..8c52e58c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2968-drm-amdgpu-add-pci-DID-for-Arcturus-GL-XL.patch
@@ -0,0 +1,30 @@
+From d6962909831f33d61080e05f545534be26b84c09 Mon Sep 17 00:00:00 2001
+From: Feifei Xu <Feifei.Xu@amd.com>
+Date: Tue, 9 Jul 2019 13:10:53 -0500
+Subject: [PATCH 2968/4256] drm/amdgpu: add pci DID for Arcturus GL-XL.
+
+Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 6c30b7f4dfe8..0f1a6824803e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1032,6 +1032,10 @@ static const struct pci_device_id pciidlist[] = {
+ 	/* Raven */
+ 	{0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
+ 	{0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
++	/* Arcturus */
++	{0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
++	{0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
++	{0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
+ 	/* Navi10 */
+ 	{0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
+ 	{0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2969-drm-amdgpu-add-arct-sdma-golden-settings.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2969-drm-amdgpu-add-arct-sdma-golden-settings.patch
new file mode 100644
index 00000000..1103376f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2969-drm-amdgpu-add-arct-sdma-golden-settings.patch
@@ -0,0 +1,85 @@
+From 4d6721ca1d47d0a098f383698088d1c716cb256b Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 27 Jun 2019 14:47:42 +0800
+Subject: [PATCH 2969/4256] drm/amdgpu: add arct sdma golden settings
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 45 ++++++++++++++++++++++++++
+ 1 file changed, 45 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 2660baa5ca32..48d4597ef9f6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -31,6 +31,18 @@
+ #include "sdma0/sdma0_4_2_sh_mask.h"
+ #include "sdma1/sdma1_4_2_offset.h"
+ #include "sdma1/sdma1_4_2_sh_mask.h"
++#include "sdma2/sdma2_4_2_2_offset.h"
++#include "sdma2/sdma2_4_2_2_sh_mask.h"
++#include "sdma3/sdma3_4_2_2_offset.h"
++#include "sdma3/sdma3_4_2_2_sh_mask.h"
++#include "sdma4/sdma4_4_2_2_offset.h"
++#include "sdma4/sdma4_4_2_2_sh_mask.h"
++#include "sdma5/sdma5_4_2_2_offset.h"
++#include "sdma5/sdma5_4_2_2_sh_mask.h"
++#include "sdma6/sdma6_4_2_2_offset.h"
++#include "sdma6/sdma6_4_2_2_sh_mask.h"
++#include "sdma7/sdma7_4_2_2_offset.h"
++#include "sdma7/sdma7_4_2_2_sh_mask.h"
+ #include "hdp/hdp_4_0_offset.h"
+ #include "sdma0/sdma0_4_1_default.h"
+ 
+@@ -207,6 +219,34 @@ static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
+ 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
+ };
+ 
++static const struct soc15_reg_golden golden_settings_sdma_arct[] =
++{
++	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
++	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
++	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
++	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
++	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
++	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
++	SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
++	SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
++	SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
++	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
++	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
++	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
++	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
++	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
++	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
++	SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
++	SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
++	SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
++	SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
++	SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
++	SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
++	SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
++	SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
++	SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002)
++};
++
+ static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
+ 		u32 instance, u32 offset)
+ {
+@@ -315,6 +355,11 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
+ 						golden_settings_sdma1_4_2,
+ 						ARRAY_SIZE(golden_settings_sdma1_4_2));
+ 		break;
++	case CHIP_ARCTURUS:
++		soc15_program_register_sequence(adev,
++						golden_settings_sdma_arct,
++						ARRAY_SIZE(golden_settings_sdma_arct));
++		break;
+ 	case CHIP_RAVEN:
+ 		soc15_program_register_sequence(adev,
+ 						golden_settings_sdma_4_1,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2970-drm-amdgpu-add-arct-gc-golden-settings.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2970-drm-amdgpu-add-arct-gc-golden-settings.patch
new file mode 100644
index 00000000..43fb5aae
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2970-drm-amdgpu-add-arct-gc-golden-settings.patch
@@ -0,0 +1,70 @@
+From c1e1981b537e0f907c144f484f19c83b3f23f150 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 27 Jun 2019 15:08:48 +0800
+Subject: [PATCH 2970/4256] drm/amdgpu: add arct gc golden settings
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 30 +++++++++++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index a202ad5c329d..e85f3f8d4b45 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -107,6 +107,19 @@ MODULE_FIRMWARE("amdgpu/arcturus_mec.bin");
+ MODULE_FIRMWARE("amdgpu/arcturus_mec2.bin");
+ MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin");
+ 
++#define mmTCP_CHAN_STEER_0_ARCT								0x0b03
++#define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX							0
++#define mmTCP_CHAN_STEER_1_ARCT								0x0b04
++#define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX							0
++#define mmTCP_CHAN_STEER_2_ARCT								0x0b09
++#define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX							0
++#define mmTCP_CHAN_STEER_3_ARCT								0x0b0a
++#define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX							0
++#define mmTCP_CHAN_STEER_4_ARCT								0x0b0b
++#define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX							0
++#define mmTCP_CHAN_STEER_5_ARCT								0x0b0c
++#define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX							0
++
+ static const struct soc15_reg_golden golden_settings_gc_9_0[] =
+ {
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
+@@ -274,6 +287,18 @@ static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] =
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
+ };
+ 
++static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] =
++{
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),
++};
++
+ static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
+ {
+ 	mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
+@@ -343,6 +368,11 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
+ 						golden_settings_gc_9_0_vg20,
+ 						ARRAY_SIZE(golden_settings_gc_9_0_vg20));
+ 		break;
++	case CHIP_ARCTURUS:
++		soc15_program_register_sequence(adev,
++						golden_settings_gc_9_4_1_arct,
++						ARRAY_SIZE(golden_settings_gc_9_4_1_arct));
++		break;
+ 	case CHIP_RAVEN:
+ 		soc15_program_register_sequence(adev, golden_settings_gc_9_1,
+ 						ARRAY_SIZE(golden_settings_gc_9_1));
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2971-drm-amdgpu-init-arct-external-rev-id.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2971-drm-amdgpu-init-arct-external-rev-id.patch
new file mode 100644
index 00000000..171169d1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2971-drm-amdgpu-init-arct-external-rev-id.patch
@@ -0,0 +1,27 @@
+From ded271bbb274130bd626b860b654cfab1d45f4d7 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 27 Jun 2019 18:05:30 +0800
+Subject: [PATCH 2971/4256] drm/amdgpu: init arct external rev id
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index dc09469f77c5..f67ecf814c8c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1016,6 +1016,7 @@ static int soc15_common_early_init(void *handle)
+ 		adev->asic_funcs = &vega20_asic_funcs;
+ 		adev->cg_flags = 0;
+ 		adev->pg_flags = 0;
++		adev->external_rev_id = adev->rev_id + 0x32;
+ 		break;
+ 	default:
+ 		/* FIXME: not supported yet */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2972-drm-amdgpu-keep-stolen-memory-for-arct.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2972-drm-amdgpu-keep-stolen-memory-for-arct.patch
new file mode 100644
index 00000000..597267e1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2972-drm-amdgpu-keep-stolen-memory-for-arct.patch
@@ -0,0 +1,47 @@
+From 3c78ba553985f91ce4f3bb221d2e2d243222191e Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Fri, 28 Jun 2019 11:07:53 +0800
+Subject: [PATCH 2972/4256] drm/amdgpu: keep stolen memory for arct
+
+Any dce register read back from arct is invalid. use hard code
+stolen memory for arct until we validate the s3.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 6ff53046fddd..0a7e16fe602d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -638,6 +638,7 @@ static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
+ 	switch (adev->asic_type) {
+ 	case CHIP_VEGA10:
+ 	case CHIP_RAVEN:
++	case CHIP_ARCTURUS:
+ 		return true;
+ 	case CHIP_VEGA12:
+ 	case CHIP_VEGA20:
+@@ -938,7 +939,7 @@ static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
+ 
+ static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
+ {
+-	u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
++	u32 d1vga_control;
+ 	unsigned size;
+ 
+ 	/*
+@@ -948,6 +949,7 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
+ 	if (gmc_v9_0_keep_stolen_memory(adev))
+ 		return 9 * 1024 * 1024;
+ 
++	d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
+ 	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
+ 		size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
+ 	} else {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2973-drm-amdgpu-init-gds-config-for-arct.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2973-drm-amdgpu-init-gds-config-for-arct.patch
new file mode 100644
index 00000000..791b13e5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2973-drm-amdgpu-init-gds-config-for-arct.patch
@@ -0,0 +1,40 @@
+From d5221f3627c48b7906ffd0b21537d6fd1da99d82 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Fri, 28 Jun 2019 13:22:32 +0800
+Subject: [PATCH 2973/4256] drm/amdgpu: init gds config for arct
+
+arct has 4KB gds (4 banks inside). there are 32 * 128 (CUs)
+so the max_wave_id should be 0xfff
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index e85f3f8d4b45..d4cff7b289f6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -5482,6 +5482,7 @@ static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
+ 		adev->gds.gds_size = 0x10000;
+ 		break;
+ 	case CHIP_RAVEN:
++	case CHIP_ARCTURUS:
+ 		adev->gds.gds_size = 0x1000;
+ 		break;
+ 	default:
+@@ -5503,6 +5504,9 @@ static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
+ 		else
+ 			adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */
+ 		break;
++	case CHIP_ARCTURUS:
++		adev->gds.gds_compute_max_wave_id = 0xfff;
++		break;
+ 	default:
+ 		/* this really depends on the chip */
+ 		adev->gds.gds_compute_max_wave_id = 0x7ff;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2974-drm-amdgpu-clean-up-nonexistent-firmware-declaration.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2974-drm-amdgpu-clean-up-nonexistent-firmware-declaration.patch
new file mode 100644
index 00000000..a919a42e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2974-drm-amdgpu-clean-up-nonexistent-firmware-declaration.patch
@@ -0,0 +1,31 @@
+From 25c26c6f15918f894fcbcf713af9669df2b424b8 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 28 Jun 2019 15:08:04 +0800
+Subject: [PATCH 2974/4256] drm/amdgpu: clean up nonexistent firmware
+ declaration for Arcturus
+
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index d4cff7b289f6..f85b92bbc5ec 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -100,9 +100,6 @@ MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
+ MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
+ MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin");
+ 
+-MODULE_FIRMWARE("amdgpu/arcturus_ce.bin");
+-MODULE_FIRMWARE("amdgpu/arcturus_pfp.bin");
+-MODULE_FIRMWARE("amdgpu/arcturus_me.bin");
+ MODULE_FIRMWARE("amdgpu/arcturus_mec.bin");
+ MODULE_FIRMWARE("amdgpu/arcturus_mec2.bin");
+ MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin");
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2975-amd-powerplay-No-SW-XGMI-dpm-for-Arcturus-rev-2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2975-amd-powerplay-No-SW-XGMI-dpm-for-Arcturus-rev-2.patch
new file mode 100644
index 00000000..871693f6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2975-amd-powerplay-No-SW-XGMI-dpm-for-Arcturus-rev-2.patch
@@ -0,0 +1,63 @@
+From 51c60bc85aa90d41b238cc5d36621ef667cb125e Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 28 Jun 2019 05:45:39 -0400
+Subject: [PATCH 2975/4256] amd/powerplay: No SW XGMI dpm for Arcturus rev 2
+
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c       |  2 +-
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     | 11 +++++++++++
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  1 +
+ 3 files changed, 13 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+index 64940759d8c0..28273d961a1b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+@@ -248,7 +248,7 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
+ 
+ 	dev_dbg(adev->dev, "Set xgmi pstate %d.\n", pstate);
+ 
+-	if (is_support_sw_smu(adev))
++	if (is_support_sw_smu_xgmi(adev))
+ 		ret = smu_set_xgmi_pstate(&adev->smu, pstate);
+ 	if (ret)
+ 		dev_err(adev->dev,
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 7d1bd0997b59..342d57f2fc5f 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -370,6 +370,17 @@ bool is_support_sw_smu(struct amdgpu_device *adev)
+ 		return false;
+ }
+ 
++bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
++{
++	if (amdgpu_dpm != 1)
++		return false;
++
++	if (adev->asic_type == CHIP_VEGA20)
++		return true;
++
++	return false;
++}
++
+ int smu_sys_get_pp_table(struct smu_context *smu, void **table)
+ {
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 79e34097eb0f..c80077db6cf5 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -951,6 +951,7 @@ int smu_update_table(struct smu_context *smu, uint32_t table_index,
+ 		     void *table_data, bool drv2smu);
+ 
+ bool is_support_sw_smu(struct amdgpu_device *adev);
++bool is_support_sw_smu_xgmi(struct amdgpu_device *adev);
+ int smu_reset(struct smu_context *smu);
+ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
+ 			   void *data, uint32_t *size);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2976-drm-amdkfd-Add-arcturus-CWSR-trap-handler.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2976-drm-amdkfd-Add-arcturus-CWSR-trap-handler.patch
new file mode 100644
index 00000000..3ff211ea
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2976-drm-amdkfd-Add-arcturus-CWSR-trap-handler.patch
@@ -0,0 +1,993 @@
+From 2acb53baf844aa97e113f4b0d5905cf6c6657a35 Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Tue, 9 Jul 2019 13:13:33 -0500
+Subject: [PATCH 2976/4256] drm/amdkfd: Add arcturus CWSR trap handler
+
+CWSR (compute wave save/restore) is used for
+preempting compute queues.
+
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h    | 198 +++++
+ .../amd/amdkfd/cwsr_trap_handler_arcturus.asm | 746 ++++++++++++++++++
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c       |   4 +
+ 3 files changed, 948 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_arcturus.asm
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+index dfa300975a45..fc9a3f7dfeb8 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+@@ -973,3 +973,201 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
+ 	0xbf9f0000, 0xbf9f0000,
+ 	0xbf9f0000, 0x00000000,
+ };
++static const uint32_t cwsr_trap_arcturus_hex[] = {
++	0xbf820001, 0xbf8200ca,
++	0xb8f0f802, 0x89708670,
++	0xb8f1f803, 0x8671ff71,
++	0x00000400, 0xbf850008,
++	0xb8f1f803, 0x8671ff71,
++	0x000001ff, 0xbf850001,
++	0x806c846c, 0x866dff6d,
++	0x0000ffff, 0xbe801f6c,
++	0xb8f1f803, 0x8671ff71,
++	0x00000100, 0xbf840006,
++	0xbef60080, 0xb9760203,
++	0x866dff6d, 0x0000ffff,
++	0x80ec886c, 0x82ed806d,
++	0xbef60080, 0xb9760283,
++	0xbef20068, 0xbef30069,
++	0xb8f62407, 0x8e769b76,
++	0x876d766d, 0xb8f603c7,
++	0x8e769a76, 0x876d766d,
++	0xb8f6f807, 0x8676ff76,
++	0x00007fff, 0xb976f807,
++	0xbeee007e, 0xbeef007f,
++	0xbefe0180, 0xbf900004,
++	0xbf8e0002, 0xbf88fffe,
++	0xbef4007e, 0x8675ff7f,
++	0x0000ffff, 0x8775ff75,
++	0x00040000, 0xbef60080,
++	0xbef700ff, 0x00807fac,
++	0x8676ff7f, 0x08000000,
++	0x8f768376, 0x87777677,
++	0x8676ff7f, 0x70000000,
++	0x8f768176, 0x87777677,
++	0xbefb007c, 0xbefa0080,
++	0xbf8a0000, 0x8676ff7f,
++	0x04000000, 0xbf840012,
++	0xbefe00c1, 0xbeff00c1,
++	0xb8f14306, 0x8671c171,
++	0xbf84000d, 0x8e718671,
++	0x8e718271, 0xbef60071,
++	0xbef600ff, 0x01000000,
++	0xbefc0080, 0xbf800000,
++	0x807cff7c, 0x00000100,
++	0x807aff7a, 0x00000100,
++	0xbf0a717c, 0xbf85fffa,
++	0xbefe00c1, 0xbeff00c1,
++	0xb8f12a05, 0x80718171,
++	0x8e718271, 0x8e768871,
++	0xbef600ff, 0x01000000,
++	0xbefc0080, 0xbf11017c,
++	0x8071ff71, 0x00001000,
++	0x7e000300, 0xe0724000,
++	0x7a1d0000, 0x807c817c,
++	0x807aff7a, 0x00000100,
++	0xbf0a717c, 0xbf85fff8,
++	0xbf9c0000, 0xbefe00c1,
++	0xbeff00c1, 0xb8f12a05,
++	0x80718171, 0x8e718271,
++	0x8e768871, 0xbef600ff,
++	0x01000000, 0xbefc0080,
++	0xbf11017c, 0x8071ff71,
++	0x00001000, 0xd3d84000,
++	0x18000100, 0x7e000000,
++	0x7e000000, 0xe0724000,
++	0x7a1d0000, 0x807c817c,
++	0x807aff7a, 0x00000100,
++	0xbf0a717c, 0xbf85fff5,
++	0xbf9c0000, 0xb8f11605,
++	0x80718171, 0x8e718471,
++	0x8e768871, 0xbef600ff,
++	0x01000000, 0xbefc0080,
++	0xbf800000, 0xbe802a00,
++	0x7e000200, 0xe0724000,
++	0x7a1d0000, 0x807aff7a,
++	0x00000100, 0x807c817c,
++	0xbf0a717c, 0xbf85fff7,
++	0xbef60084, 0xbef600ff,
++	0x01000000, 0x7e00027b,
++	0xe0724000, 0x7a1d0000,
++	0x807aff7a, 0x00000100,
++	0x7e00026c, 0xe0724000,
++	0x7a1d0000, 0x807aff7a,
++	0x00000100, 0x7e00026d,
++	0xe0724000, 0x7a1d0000,
++	0x807aff7a, 0x00000100,
++	0x7e00026e, 0xe0724000,
++	0x7a1d0000, 0x807aff7a,
++	0x00000100, 0x7e00026f,
++	0xe0724000, 0x7a1d0000,
++	0x807aff7a, 0x00000100,
++	0x7e000270, 0xe0724000,
++	0x7a1d0000, 0x807aff7a,
++	0x00000100, 0xb8f1f803,
++	0x7e000271, 0xe0724000,
++	0x7a1d0000, 0x807aff7a,
++	0x00000100, 0x7e000272,
++	0xe0724000, 0x7a1d0000,
++	0x807aff7a, 0x00000100,
++	0x7e000273, 0xe0724000,
++	0x7a1d0000, 0x807aff7a,
++	0x00000100, 0xb8fbf801,
++	0x7e00027b, 0xe0724000,
++	0x7a1d0000, 0x807aff7a,
++	0x00000100, 0xbf8200bb,
++	0xbef4007e, 0x8675ff7f,
++	0x0000ffff, 0x8775ff75,
++	0x00040000, 0xbef60080,
++	0xbef700ff, 0x00807fac,
++	0x8672ff7f, 0x08000000,
++	0x8f728372, 0x87777277,
++	0x8672ff7f, 0x70000000,
++	0x8f728172, 0x87777277,
++	0xbef80080, 0x8672ff7f,
++	0x04000000, 0xbf840011,
++	0xbefe00c1, 0xbeff00c1,
++	0xb8ef4306, 0x866fc16f,
++	0xbf84000c, 0x8e6f866f,
++	0x8e6f826f, 0xbef6006f,
++	0xbef600ff, 0x01000000,
++	0xbefc0080, 0x807cff7c,
++	0x00000100, 0x8078ff78,
++	0x00000100, 0xbf0a6f7c,
++	0xbf85fffa, 0xbefe00c1,
++	0xbeff00c1, 0xb8ef2a05,
++	0x806f816f, 0x8e6f826f,
++	0x8e76886f, 0xbef600ff,
++	0x01000000, 0xbef20078,
++	0x8078ff78, 0x00000100,
++	0xbefc0081, 0xbf11087c,
++	0x806fff6f, 0x00008000,
++	0xe0524000, 0x781d0000,
++	0xbf8c0f70, 0x7e000300,
++	0x807c817c, 0x8078ff78,
++	0x00000100, 0xbf0a6f7c,
++	0xbf85fff7, 0xbf9c0000,
++	0xbefe00c1, 0xbeff00c1,
++	0xb8ef2a05, 0x806f816f,
++	0x8e6f826f, 0x8e76886f,
++	0xbef600ff, 0x01000000,
++	0xbefc0080, 0xbf11087c,
++	0x806fff6f, 0x00008000,
++	0xe0524000, 0x781d0000,
++	0xbf8c0f70, 0xd3d94000,
++	0x18000100, 0x807c817c,
++	0x8078ff78, 0x00000100,
++	0xbf0a6f7c, 0xbf85fff6,
++	0xbf9c0000, 0xe0524000,
++	0x721d0000, 0xb8ef1605,
++	0x806f816f, 0x8e6f846f,
++	0x8e76886f, 0xbef600ff,
++	0x01000000, 0xc0211cba,
++	0x00000078, 0x8078ff78,
++	0x00000100, 0xbefc0081,
++	0xc021003a, 0x00000078,
++	0x8078ff78, 0x00000100,
++	0xbf8cc07f, 0xbe802c00,
++	0xbf800000, 0x807c817c,
++	0xbf0a6f7c, 0xbf85fff6,
++	0xbe800072, 0xbef60084,
++	0xbef600ff, 0x01000000,
++	0xc0211bfa, 0x00000078,
++	0x8078ff78, 0x00000100,
++	0xc0211b3a, 0x00000078,
++	0x8078ff78, 0x00000100,
++	0xc0211b7a, 0x00000078,
++	0x8078ff78, 0x00000100,
++	0xc0211eba, 0x00000078,
++	0x8078ff78, 0x00000100,
++	0xc0211efa, 0x00000078,
++	0x8078ff78, 0x00000100,
++	0xc0211c3a, 0x00000078,
++	0x8078ff78, 0x00000100,
++	0xc0211c7a, 0x00000078,
++	0x8078ff78, 0x00000100,
++	0xc0211a3a, 0x00000078,
++	0x8078ff78, 0x00000100,
++	0xc0211a7a, 0x00000078,
++	0x8078ff78, 0x00000100,
++	0xc0211cfa, 0x00000078,
++	0x8078ff78, 0x00000100,
++	0xbf8cc07f, 0xbef2006d,
++	0x866dff72, 0x0000ffff,
++	0xbefc006f, 0xbefe007a,
++	0xbeff007b, 0x866f71ff,
++	0x000003ff, 0xb96f4803,
++	0x866f71ff, 0xfffff800,
++	0x8f6f8b6f, 0xb96fa2c3,
++	0xb973f801, 0x866fff72,
++	0xf8000000, 0x8f6f9b6f,
++	0x8e6f906f, 0xbef30080,
++	0x87736f73, 0x866fff72,
++	0x04000000, 0x8f6f9a6f,
++	0x8e6f8f6f, 0x87736f73,
++	0x866fff70, 0x00800000,
++	0x8f6f976f, 0xb973f807,
++	0x86fe7e7e, 0x86ea6a6a,
++	0xb970f802, 0xbf8a0000,
++	0x95806f6c, 0xbf810000,
++};
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_arcturus.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_arcturus.asm
+new file mode 100644
+index 000000000000..b83e2a643ddb
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_arcturus.asm
+@@ -0,0 +1,746 @@
++shader main
++
++asic(DEFAULT)
++
++type(CS)
++
++/*************************************************************************/
++/*					control on how to run the shader					 */
++/*************************************************************************/
++//any hack that needs to be made to run this code in EMU (either becasue various EMU code are not ready or no compute save & restore in EMU run)
++var EMU_RUN_HACK					=	0
++var EMU_RUN_HACK_RESTORE_NORMAL		=	0
++var EMU_RUN_HACK_SAVE_NORMAL_EXIT	=	0
++var	EMU_RUN_HACK_SAVE_SINGLE_WAVE	=	0
++var EMU_RUN_HACK_SAVE_FIRST_TIME	= 	0					//for interrupted restore in which the first save is through EMU_RUN_HACK
++var SAVE_LDS						= 	0
++var WG_BASE_ADDR_LO					=   0x9000a000
++var WG_BASE_ADDR_HI					=	0x0
++var WAVE_SPACE						=	0x6000				//memory size that each wave occupies in workgroup state mem
++var CTX_SAVE_CONTROL				=	0x0
++var CTX_RESTORE_CONTROL				=	CTX_SAVE_CONTROL
++var SIM_RUN_HACK					=	0					//any hack that needs to be made to run this code in SIM (either becasue various RTL code are not ready or no compute save & restore in RTL run)
++var	SGPR_SAVE_USE_SQC				=	0					//use SQC D$ to do the write
++var USE_MTBUF_INSTEAD_OF_MUBUF		=	0					//need to change BUF_DATA_FORMAT in S_SAVE_BUF_RSRC_WORD3_MISC from 0 to BUF_DATA_FORMAT_32 if set to 1 (i.e. 0x00827FAC)
++var SWIZZLE_EN						=	0					//whether we use swizzled buffer addressing
++
++/**************************************************************************/
++/*                     	variables							              */
++/**************************************************************************/
++var SQ_WAVE_STATUS_INST_ATC_SHIFT  = 23
++var SQ_WAVE_STATUS_INST_ATC_MASK   = 0x00800000
++var SQ_WAVE_STATUS_SPI_PRIO_MASK   = 0x00000006
++
++var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT	= 12
++var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE		= 9
++var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT	= 8
++var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE	= 6
++var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT	= 24
++var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE	= 3						//FIXME	 sq.blk still has 4 bits at this time while SQ programming guide has 3 bits
++
++var	SQ_WAVE_TRAPSTS_SAVECTX_MASK	=	0x400
++var SQ_WAVE_TRAPSTS_EXCE_MASK       =   0x1FF          			// Exception mask
++var	SQ_WAVE_TRAPSTS_SAVECTX_SHIFT	=	10
++var	SQ_WAVE_TRAPSTS_MEM_VIOL_MASK	=	0x100
++var	SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT	=	8
++var	SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK 	=	0x3FF
++var	SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT 	=	0x0
++var	SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE 	=	10
++var	SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK 	=	0xFFFFF800
++var	SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT 	=	11
++var	SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE 	=	21
++
++var SQ_WAVE_IB_STS_RCNT_SHIFT			=	16					//FIXME
++var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT	=	15					//FIXME
++var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG	= 0x00007FFF	//FIXME
++
++var	SQ_BUF_RSRC_WORD1_ATC_SHIFT		=	24
++var	SQ_BUF_RSRC_WORD3_MTYPE_SHIFT	=	27
++
++
++/*      Save        */
++var	S_SAVE_BUF_RSRC_WORD1_STRIDE		=	0x00040000  		//stride is 4 bytes
++var	S_SAVE_BUF_RSRC_WORD3_MISC			= 	0x00807FAC			//SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE
++
++var	S_SAVE_SPI_INIT_ATC_MASK			=	0x08000000			//bit[27]: ATC bit
++var	S_SAVE_SPI_INIT_ATC_SHIFT			=	27
++var	S_SAVE_SPI_INIT_MTYPE_MASK			=	0x70000000			//bit[30:28]: Mtype
++var	S_SAVE_SPI_INIT_MTYPE_SHIFT			=	28
++var	S_SAVE_SPI_INIT_FIRST_WAVE_MASK		=	0x04000000			//bit[26]: FirstWaveInTG
++var	S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT	=	26
++
++var S_SAVE_PC_HI_RCNT_SHIFT				=	27					//FIXME	 check with Brian to ensure all fields other than PC[47:0] can be used
++var S_SAVE_PC_HI_RCNT_MASK				=   0xF8000000			//FIXME
++var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT		=	26					//FIXME
++var S_SAVE_PC_HI_FIRST_REPLAY_MASK		=	0x04000000			//FIXME
++
++var	s_save_spi_init_lo				=	exec_lo
++var s_save_spi_init_hi				=	exec_hi
++
++var	s_save_pc_lo			=	ttmp0			//{TTMP1, TTMP0} = {3¡¯h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]}
++var	s_save_pc_hi			=	ttmp1
++var s_save_exec_lo			=	ttmp2
++var s_save_exec_hi			= 	ttmp3
++var	s_save_status			=	ttmp4
++var	s_save_trapsts			=	ttmp5			//not really used until the end of the SAVE routine
++var s_save_xnack_mask_lo	=	ttmp6
++var s_save_xnack_mask_hi	=	ttmp7
++var	s_save_buf_rsrc0		=	ttmp8
++var	s_save_buf_rsrc1		=	ttmp9
++var	s_save_buf_rsrc2		=	ttmp10
++var	s_save_buf_rsrc3		=	ttmp11
++
++var s_save_mem_offset		= 	ttmp14
++var s_save_alloc_size		=	s_save_trapsts			//conflict
++var s_save_tmp              =   s_save_buf_rsrc2       	//shared with s_save_buf_rsrc2  (conflict: should not use mem access with s_save_tmp at the same time)
++var s_save_m0				=	ttmp15
++
++/*      Restore     */
++var	S_RESTORE_BUF_RSRC_WORD1_STRIDE			=	S_SAVE_BUF_RSRC_WORD1_STRIDE
++var	S_RESTORE_BUF_RSRC_WORD3_MISC			= 	S_SAVE_BUF_RSRC_WORD3_MISC
++
++var	S_RESTORE_SPI_INIT_ATC_MASK			    =	0x08000000			//bit[27]: ATC bit
++var	S_RESTORE_SPI_INIT_ATC_SHIFT			=	27
++var	S_RESTORE_SPI_INIT_MTYPE_MASK			=	0x70000000			//bit[30:28]: Mtype
++var	S_RESTORE_SPI_INIT_MTYPE_SHIFT			=	28
++var	S_RESTORE_SPI_INIT_FIRST_WAVE_MASK		=	0x04000000			//bit[26]: FirstWaveInTG
++var	S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT	    =	26
++
++var S_RESTORE_PC_HI_RCNT_SHIFT				=	S_SAVE_PC_HI_RCNT_SHIFT
++var S_RESTORE_PC_HI_RCNT_MASK				=   S_SAVE_PC_HI_RCNT_MASK
++var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT		=	S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
++var S_RESTORE_PC_HI_FIRST_REPLAY_MASK		=	S_SAVE_PC_HI_FIRST_REPLAY_MASK
++
++var s_restore_spi_init_lo                   =   exec_lo
++var s_restore_spi_init_hi                   =   exec_hi
++
++var s_restore_mem_offset		= 	ttmp12
++var s_restore_alloc_size		=	ttmp3
++var s_restore_tmp           	=   ttmp6
++var s_restore_mem_offset_save	= 	s_restore_tmp 		//no conflict
++
++var s_restore_m0			=	s_restore_alloc_size	//no conflict
++
++var s_restore_mode			=  	ttmp7
++
++var	s_restore_pc_lo		    =	ttmp0
++var	s_restore_pc_hi		    =	ttmp1
++var s_restore_exec_lo		=	ttmp14
++var s_restore_exec_hi		= 	ttmp15
++var	s_restore_status	    =	ttmp4
++var	s_restore_trapsts	    =	ttmp5
++var s_restore_xnack_mask_lo	=	xnack_mask_lo
++var s_restore_xnack_mask_hi	=	xnack_mask_hi
++var	s_restore_buf_rsrc0		=	ttmp8
++var	s_restore_buf_rsrc1		=	ttmp9
++var	s_restore_buf_rsrc2		=	ttmp10
++var	s_restore_buf_rsrc3		=	ttmp11
++
++/**************************************************************************/
++/*                     	trap handler entry points			              */
++/**************************************************************************/
++    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) 					//hack to use trap_id for determining save/restore
++		//FIXME VCCZ un-init assertion s_getreg_b32  	s_save_status, hwreg(HW_REG_STATUS)			//save STATUS since we will change SCC
++		s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000 				//change SCC
++    	s_cmp_eq_u32 s_save_tmp, 0x007e0000  						//Save: trap_id = 0x7e. Restore: trap_id = 0x7f.
++    	s_cbranch_scc0 L_JUMP_TO_RESTORE							//do not need to recover STATUS here  since we are going to RESTORE
++		//FIXME  s_setreg_b32 	hwreg(HW_REG_STATUS), 	s_save_status		//need to recover STATUS since we are going to SAVE
++		s_branch L_SKIP_RESTORE 									//NOT restore, SAVE actually
++	else
++		s_branch L_SKIP_RESTORE 									//NOT restore. might be a regular trap or save
++    end
++
++L_JUMP_TO_RESTORE:
++    s_branch L_RESTORE												//restore
++
++L_SKIP_RESTORE:
++
++	s_getreg_b32  	s_save_status, hwreg(HW_REG_STATUS)								//save STATUS since we will change SCC
++	s_andn2_b32		s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK      //check whether this is for save
++	s_getreg_b32  	s_save_trapsts, hwreg(HW_REG_TRAPSTS)
++	s_and_b32		s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK	//check whether this is for save
++	s_cbranch_scc1	L_SAVE															//this is the operation for save
++
++	// *********    Handle non-CWSR traps       *******************
++    if (!EMU_RUN_HACK)
++		s_getreg_b32     s_save_trapsts, hwreg(HW_REG_TRAPSTS)
++		s_and_b32        s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK // Check whether it is an exception
++		s_cbranch_scc1  L_EXCP_CASE   // Exception, jump back to the shader program directly.
++		s_add_u32    ttmp0, ttmp0, 4   // S_TRAP case, add 4 to ttmp0
++
++		L_EXCP_CASE:
++		s_and_b32    ttmp1, ttmp1, 0xFFFF
++		s_rfe_b64    [ttmp0, ttmp1]
++	end
++    // *********        End handling of non-CWSR traps   *******************
++
++/**************************************************************************/
++/*                     	save routine						              */
++/**************************************************************************/
++
++L_SAVE:
++
++	//check whether there is mem_viol
++	s_getreg_b32  	s_save_trapsts, hwreg(HW_REG_TRAPSTS)
++	s_and_b32		s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK
++	s_cbranch_scc0	L_NO_PC_REWIND
++
++	//if so, need rewind PC assuming GDS operation gets NACKed
++	s_mov_b32       s_save_tmp, 0															//clear mem_viol bit
++	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT, 1), s_save_tmp	//clear mem_viol bit
++	s_and_b32 		s_save_pc_hi, s_save_pc_hi, 0x0000ffff    //pc[47:32]
++	s_sub_u32 		s_save_pc_lo, s_save_pc_lo, 8             //pc[31:0]-8
++	s_subb_u32 		s_save_pc_hi, s_save_pc_hi, 0x0			  // -scc
++
++L_NO_PC_REWIND:
++    s_mov_b32       s_save_tmp, 0															//clear saveCtx bit
++	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp		//clear saveCtx bit
++
++	s_mov_b32		s_save_xnack_mask_lo,	xnack_mask_lo									//save XNACK_MASK
++	s_mov_b32		s_save_xnack_mask_hi,	xnack_mask_hi
++	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE)					//save RCNT
++	s_lshl_b32		s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT
++	s_or_b32		s_save_pc_hi, s_save_pc_hi, s_save_tmp
++	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE)	//save FIRST_REPLAY
++	s_lshl_b32		s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
++	s_or_b32		s_save_pc_hi, s_save_pc_hi, s_save_tmp
++	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS)										//clear RCNT and FIRST_REPLAY in IB_STS
++	s_and_b32		s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG
++
++	s_setreg_b32	hwreg(HW_REG_IB_STS), s_save_tmp
++
++	/*		inform SPI the readiness and wait for SPI's go signal */
++	s_mov_b32		s_save_exec_lo,	exec_lo													//save EXEC and use EXEC for the go signal from SPI
++	s_mov_b32		s_save_exec_hi,	exec_hi
++	s_mov_b64		exec, 	0x0																//clear EXEC to get ready to receive
++	if (EMU_RUN_HACK)
++
++	else
++		s_sendmsg	sendmsg(MSG_SAVEWAVE)													//send SPI a message and wait for SPI's write to EXEC
++	end
++
++  L_SLEEP:
++	s_sleep 0x2
++
++	if (EMU_RUN_HACK)
++
++	else
++		s_cbranch_execz	L_SLEEP
++	end
++
++
++	/*      setup Resource Contants    */
++	if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE))
++		//calculate wd_addr using absolute thread id
++		v_readlane_b32 s_save_tmp, v9, 0
++		s_lshr_b32 s_save_tmp, s_save_tmp, 6
++		s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE
++		s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO
++		s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI
++		s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL
++	else
++	end
++	if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE))
++		s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO
++		s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI
++		s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL
++	else
++	end
++
++
++	s_mov_b32		s_save_buf_rsrc0, 	s_save_spi_init_lo														//base_addr_lo
++	s_and_b32		s_save_buf_rsrc1, 	s_save_spi_init_hi, 0x0000FFFF											//base_addr_hi
++	s_or_b32		s_save_buf_rsrc1, 	s_save_buf_rsrc1,  S_SAVE_BUF_RSRC_WORD1_STRIDE
++    s_mov_b32       s_save_buf_rsrc2,   0                                               						//NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited
++	s_mov_b32		s_save_buf_rsrc3, 	S_SAVE_BUF_RSRC_WORD3_MISC
++	s_and_b32		s_save_tmp,         s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK
++	s_lshr_b32		s_save_tmp,  		s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT)			//get ATC bit into position
++	s_or_b32		s_save_buf_rsrc3, 	s_save_buf_rsrc3,  s_save_tmp											//or ATC TODO: ATC deprecated, no need anymore.
++	s_and_b32		s_save_tmp,         s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK
++	s_lshr_b32		s_save_tmp,  		s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT)		//get MTYPE bits into position
++	s_or_b32		s_save_buf_rsrc3, 	s_save_buf_rsrc3,  s_save_tmp											//or MTYPE
++
++	s_mov_b32		s_save_m0,			m0																	//save M0
++
++	/* 		global mem offset			*/
++	s_mov_b32		s_save_mem_offset, 	0x0																		//mem offset initial value = 0
++
++
++	/*      the first wave in the threadgroup    */
++	s_barrier																		//FIXME  not performance-optimal "LDS is used? wait for other waves in the same TG"
++	s_and_b32		s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK								//exec is still used here
++	s_cbranch_scc0	L_SAVE_VGPR
++
++	/*      	save LDS	    */
++	//////////////////////////////
++  L_SAVE_LDS:
++
++	s_mov_b32		exec_lo, 0xFFFFFFFF 											//need every thread from now on
++	s_mov_b32		exec_hi, 0xFFFFFFFF
++
++	s_getreg_b32 	s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) 			//lds_size
++	s_and_b32		s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF				//lds_size is zero?
++	s_cbranch_scc0	L_SAVE_VGPR														//no lds used? jump to L_SAVE_VGPR
++	s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 6 						//LDS size in dwords = lds_size * 64dw
++	s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 2 						//LDS size in bytes
++	s_mov_b32		s_save_buf_rsrc2,  s_save_alloc_size  							//NUM_RECORDS in bytes
++	if (SWIZZLE_EN)
++		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
++	else
++		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
++	end
++	s_mov_b32 		m0, 0x0 														//lds_offset initial value = 0
++	s_nop           0x0                                                             //Manually inserted wait states
++
++  L_SAVE_LDS_LOOP:
++	if (SAVE_LDS)
++	buffer_store_lds_dword	s_save_buf_rsrc0, s_save_mem_offset lds:1
++	end
++	s_add_u32		m0, m0, 256															//every buffer_store_lds does 256 bytes
++	s_add_u32		s_save_mem_offset, s_save_mem_offset, 256							//mem offset increased by 256 bytes
++	s_cmp_lt_u32	m0, s_save_alloc_size												//scc=(m0 < s_save_alloc_size) ? 1 : 0
++	s_cbranch_scc1  L_SAVE_LDS_LOOP														//LDS save is complete?
++
++
++	/*      	save VGPRs	    */
++	//////////////////////////////
++  L_SAVE_VGPR:
++
++ 	s_mov_b32		exec_lo, 0xFFFFFFFF 											//need every thread from now on
++	s_mov_b32		exec_hi, 0xFFFFFFFF
++
++	s_getreg_b32 	s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 					//vpgr_size
++	s_add_u32 		s_save_alloc_size, s_save_alloc_size, 1
++	s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 2 						//Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)   //FIXME for GFX, zero is possible
++	s_lshl_b32		s_save_buf_rsrc2,  s_save_alloc_size, 8							//NUM_RECORDS in bytes (64 threads*4)
++	if (SWIZZLE_EN)
++		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
++	else
++		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
++	end
++
++    s_mov_b32 		m0, 0x0 														//VGPR initial index value =0
++	s_set_gpr_idx_on  m0, 0x1														//M0[7:0] = M0[7:0] and M0[15:12] = 0x1
++    s_add_u32		s_save_alloc_size, s_save_alloc_size, 0x1000					//add 0x1000 since we compare m0 against it later
++
++  L_SAVE_VGPR_LOOP:
++	v_mov_b32 		v0, v0															//v0 = v[0+m0]
++
++    if(USE_MTBUF_INSTEAD_OF_MUBUF)
++		tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
++    else
++		buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
++	end
++
++    s_add_u32		m0, m0, 1														//next vgpr index
++	s_add_u32		s_save_mem_offset, s_save_mem_offset, 256						//every buffer_store_dword does 256 bytes
++	s_cmp_lt_u32 	m0,	s_save_alloc_size 											//scc = (m0 < s_save_alloc_size) ? 1 : 0
++	s_cbranch_scc1 	L_SAVE_VGPR_LOOP												//VGPR save is complete?
++	s_set_gpr_idx_off
++
++
++    /*      	save ACC_VGPRs	    */
++	//////////////////////////////
++  L_SAVE_ACC_VGPR:
++
++ 	s_mov_b32		exec_lo, 0xFFFFFFFF 											//need every thread from now on
++	s_mov_b32		exec_hi, 0xFFFFFFFF
++
++	s_getreg_b32 	s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 					//vpgr_size
++	s_add_u32 		s_save_alloc_size, s_save_alloc_size, 1
++	s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 2 						//Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)   //FIXME for GFX, zero is possible
++	s_lshl_b32		s_save_buf_rsrc2,  s_save_alloc_size, 8							//NUM_RECORDS in bytes (64 threads*4)
++	if (SWIZZLE_EN)
++		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
++	else
++		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
++	end
++
++    s_mov_b32 		m0, 0x0 														//VGPR initial index value =0
++	s_set_gpr_idx_on  m0, 0x1														//M0[7:0] = M0[7:0] and M0[15:12] = 0x1
++    s_add_u32		s_save_alloc_size, s_save_alloc_size, 0x1000					//add 0x1000 since we compare m0 against it later
++
++  L_SAVE_ACC_VGPR_LOOP:
++    v_accvgpr_read  v0, v0
++	v_nop
++    v_nop
++    if(USE_MTBUF_INSTEAD_OF_MUBUF)
++		tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
++    else
++		buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
++	end
++
++    s_add_u32		m0, m0, 1														//next vgpr index
++	s_add_u32		s_save_mem_offset, s_save_mem_offset, 256						//every buffer_store_dword does 256 bytes
++	s_cmp_lt_u32 	m0,	s_save_alloc_size 											//scc = (m0 < s_save_alloc_size) ? 1 : 0
++	s_cbranch_scc1 	L_SAVE_ACC_VGPR_LOOP												//VGPR save is complete?
++	s_set_gpr_idx_off
++
++
++	/*      	save SGPRs	    */
++	//////////////////////////////
++	s_getreg_b32 	s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) 				//spgr_size
++	s_add_u32 		s_save_alloc_size, s_save_alloc_size, 1
++	s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 4 						//Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value)
++
++	if (SGPR_SAVE_USE_SQC)
++		s_lshl_b32		s_save_buf_rsrc2,	s_save_alloc_size, 2					//NUM_RECORDS in bytes
++	else
++		s_lshl_b32		s_save_buf_rsrc2,	s_save_alloc_size, 8					//NUM_RECORDS in bytes (64 threads)
++	end
++
++	if (SWIZZLE_EN)
++		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
++	else
++		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
++	end
++
++	s_mov_b32 		m0, 0x0 														//SGPR initial index value =0
++    s_nop           0x0                                                             //Manually inserted wait states
++
++  L_SAVE_SGPR_LOOP:
++	s_movrels_b32 	s0, s0 															//s0 = s[0+m0]
++	write_sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)							//PV: the best performance should be using s_buffer_store_dwordx4
++	s_add_u32		m0, m0, 1														//next sgpr index
++	s_cmp_lt_u32 	m0, s_save_alloc_size 											//scc = (m0 < s_save_alloc_size) ? 1 : 0
++	s_cbranch_scc1 	L_SAVE_SGPR_LOOP												//SGPR save is complete?
++
++	/* 		save HW registers	*/
++	//////////////////////////////
++  L_SAVE_HWREG:
++    s_mov_b32		s_save_buf_rsrc2, 0x4								//NUM_RECORDS	in bytes
++	if (SWIZZLE_EN)
++		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
++	else
++		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
++	end
++
++
++	write_sgpr_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)					//M0
++
++	if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME))
++		s_add_u32 s_save_pc_lo, s_save_pc_lo, 4             //pc[31:0]+4
++		s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0			//carry bit over
++	end
++
++	write_sgpr_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)					//PC
++	write_sgpr_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
++	write_sgpr_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)				//EXEC
++	write_sgpr_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
++	write_sgpr_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)				//STATUS
++
++	//s_save_trapsts conflicts with s_save_alloc_size
++	s_getreg_b32    s_save_trapsts, hwreg(HW_REG_TRAPSTS)
++	write_sgpr_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)				//TRAPSTS
++
++	write_sgpr_to_mem(s_save_xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)			//XNACK_MASK_LO
++	write_sgpr_to_mem(s_save_xnack_mask_hi, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)			//XNACK_MASK_HI
++
++	//use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2
++	s_getreg_b32 	s_save_m0, hwreg(HW_REG_MODE)																						//MODE
++	write_sgpr_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
++
++	/*     S_PGM_END_SAVED  */    							//FIXME  graphics ONLY
++	if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT))
++		s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff    //pc[47:32]
++		s_add_u32 s_save_pc_lo, s_save_pc_lo, 4             //pc[31:0]+4
++		s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0			//carry bit over
++		s_rfe_b64 s_save_pc_lo                              //Return to the main shader program
++	else
++	end
++
++
++    s_branch	L_END_PGM
++
++
++
++/**************************************************************************/
++/*                     	restore routine						              */
++/**************************************************************************/
++
++L_RESTORE:
++    /*      Setup Resource Contants    */
++    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))
++		//calculate wd_addr using absolute thread id
++		v_readlane_b32 s_restore_tmp, v9, 0
++		s_lshr_b32 s_restore_tmp, s_restore_tmp, 6
++		s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE
++		s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO
++		s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI
++		s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL
++	else
++	end
++
++    s_mov_b32		s_restore_buf_rsrc0, 	s_restore_spi_init_lo															//base_addr_lo
++	s_and_b32		s_restore_buf_rsrc1, 	s_restore_spi_init_hi, 0x0000FFFF												//base_addr_hi
++	s_or_b32		s_restore_buf_rsrc1, 	s_restore_buf_rsrc1,  S_RESTORE_BUF_RSRC_WORD1_STRIDE
++    s_mov_b32       s_restore_buf_rsrc2,   	0                                               								//NUM_RECORDS initial value = 0 (in bytes)
++	s_mov_b32		s_restore_buf_rsrc3, 	S_RESTORE_BUF_RSRC_WORD3_MISC
++	s_and_b32		s_restore_tmp,         	s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK
++	s_lshr_b32		s_restore_tmp,  		s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT)		//get ATC bit into position
++	s_or_b32		s_restore_buf_rsrc3, 	s_restore_buf_rsrc3,  s_restore_tmp												//or ATC TODO: ATC deprecated, no need anymore.
++	s_and_b32		s_restore_tmp,         	s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK
++	s_lshr_b32		s_restore_tmp,  		s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT)	//get MTYPE bits into position
++	s_or_b32		s_restore_buf_rsrc3, 	s_restore_buf_rsrc3,  s_restore_tmp												//or MTYPE
++
++	/* 		global mem offset			*/
++	s_mov_b32		s_restore_mem_offset, 0x0								//mem offset initial value = 0
++
++	/*      the first wave in the threadgroup    */
++	s_and_b32		s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK
++	s_cbranch_scc0	L_RESTORE_VGPR
++
++    /*      	restore LDS	    */
++	//////////////////////////////
++  L_RESTORE_LDS:
++
++	s_mov_b32		exec_lo, 0xFFFFFFFF 													//need every thread from now on   //be consistent with SAVE although can be moved ahead
++	s_mov_b32		exec_hi, 0xFFFFFFFF
++
++	s_getreg_b32 	s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) 				//lds_size
++	s_and_b32		s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF					//lds_size is zero?
++	s_cbranch_scc0	L_RESTORE_VGPR															//no lds used? jump to L_RESTORE_VGPR
++	s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 6 							//LDS size in dwords = lds_size * 64dw
++	s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 2 							//LDS size in bytes
++	s_mov_b32		s_restore_buf_rsrc2,	s_restore_alloc_size							//NUM_RECORDS in bytes
++	if (SWIZZLE_EN)
++		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
++	else
++		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
++	end
++	s_mov_b32 		m0, 0x0 																//lds_offset initial value = 0
++
++  L_RESTORE_LDS_LOOP:
++	if (SAVE_LDS)
++	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1
++	end
++    s_add_u32		m0, m0, 256																//every buffer_load_dword does 256 bytes
++	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 256							//mem offset increased by 256 bytes
++	s_cmp_lt_u32	m0, s_restore_alloc_size												//scc=(m0 < s_restore_alloc_size) ? 1 : 0
++	s_cbranch_scc1  L_RESTORE_LDS_LOOP														//LDS restore is complete?
++
++
++    /*      	restore VGPRs	    */
++	//////////////////////////////
++  L_RESTORE_VGPR:
++
++ 	s_mov_b32		exec_lo, 0xFFFFFFFF 													//need every thread from now on   //be consistent with SAVE although can be moved ahead
++	s_mov_b32		exec_hi, 0xFFFFFFFF
++
++	s_getreg_b32 	s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 	//vpgr_size
++	s_add_u32 		s_restore_alloc_size, s_restore_alloc_size, 1
++	s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 2 							//Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)
++    s_lshl_b32		s_restore_buf_rsrc2,  s_restore_alloc_size, 8						    //NUM_RECORDS in bytes (64 threads*4)
++	if (SWIZZLE_EN)
++		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
++	else
++		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
++	end
++	s_mov_b32		s_restore_mem_offset_save, s_restore_mem_offset							// restore start with v1, v0 will be the last
++	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 256
++    s_mov_b32 		m0, 1 																	//VGPR initial index value = 1
++	s_set_gpr_idx_on  m0, 0x8																//M0[7:0] = M0[7:0] and M0[15:12] = 0x8
++    s_add_u32		s_restore_alloc_size, s_restore_alloc_size, 0x8000						//add 0x8000 since we compare m0 against it later
++
++  L_RESTORE_VGPR_LOOP:
++    if(USE_MTBUF_INSTEAD_OF_MUBUF)
++		tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
++    else
++		buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset	slc:1 glc:1
++	end
++	s_waitcnt		vmcnt(0)																//ensure data ready
++	v_mov_b32		v0, v0																	//v[0+m0] = v0
++    s_add_u32		m0, m0, 1																//next vgpr index
++	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 256							//every buffer_load_dword does 256 bytes
++	s_cmp_lt_u32 	m0,	s_restore_alloc_size 												//scc = (m0 < s_restore_alloc_size) ? 1 : 0
++	s_cbranch_scc1 	L_RESTORE_VGPR_LOOP														//VGPR restore (except v0) is complete?
++	s_set_gpr_idx_off
++
++
++    /*      	restore ACC_VGPRs	    */
++	//////////////////////////////
++  L_RESTORE_ACC_VGPR:
++
++ 	s_mov_b32		exec_lo, 0xFFFFFFFF 													//need every thread from now on   //be consistent with SAVE although can be moved ahead
++	s_mov_b32		exec_hi, 0xFFFFFFFF
++
++	s_getreg_b32 	s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 	//vpgr_size
++	s_add_u32 		s_restore_alloc_size, s_restore_alloc_size, 1
++	s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 2 							//Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)
++    s_lshl_b32		s_restore_buf_rsrc2,  s_restore_alloc_size, 8						    //NUM_RECORDS in bytes (64 threads*4)
++	if (SWIZZLE_EN)
++		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
++	else
++		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
++	end
++    s_mov_b32 		m0, 0 																	//VGPR initial index value = 0
++	s_set_gpr_idx_on  m0, 0x8																//M0[7:0] = M0[7:0] and M0[15:12] = 0x8
++    s_add_u32		s_restore_alloc_size, s_restore_alloc_size, 0x8000						//add 0x8000 since we compare m0 against it later
++
++  L_RESTORE_ACC_VGPR_LOOP:
++    if(USE_MTBUF_INSTEAD_OF_MUBUF)
++		tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
++    else
++		buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset	slc:1 glc:1
++	end
++	s_waitcnt		vmcnt(0)																//ensure data ready
++	v_accvgpr_write		v0, v0															//v[0+m0] = v0
++    s_add_u32		m0, m0, 1																//next vgpr index
++	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 256							//every buffer_load_dword does 256 bytes
++	s_cmp_lt_u32 	m0,	s_restore_alloc_size 												//scc = (m0 < s_restore_alloc_size) ? 1 : 0
++	s_cbranch_scc1 	L_RESTORE_ACC_VGPR_LOOP														//VGPR restore (except v0) is complete?
++	s_set_gpr_idx_off
++																							/* VGPR restore on v0 */
++    if(USE_MTBUF_INSTEAD_OF_MUBUF)
++		tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
++    else
++		buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save	slc:1 glc:1
++	end
++
++    /*      	restore SGPRs	    */
++	//////////////////////////////
++	s_getreg_b32 	s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) 				//spgr_size
++	s_add_u32 		s_restore_alloc_size, s_restore_alloc_size, 1
++	s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 4 							//Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value)
++
++	if (SGPR_SAVE_USE_SQC)
++		s_lshl_b32		s_restore_buf_rsrc2,	s_restore_alloc_size, 2						//NUM_RECORDS in bytes
++	else
++		s_lshl_b32		s_restore_buf_rsrc2,	s_restore_alloc_size, 8						//NUM_RECORDS in bytes (64 threads)
++	end
++	if (SWIZZLE_EN)
++		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
++	else
++		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
++	end
++	read_sgpr_from_mem(s_restore_tmp, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)		//save s0 to s_restore_tmp
++	s_mov_b32 		m0, 0x1																				//SGPR initial index value =1	//go on with with s1
++
++  L_RESTORE_SGPR_LOOP:
++	read_sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)															//PV: further performance improvement can be made
++	s_waitcnt		lgkmcnt(0)																//ensure data ready
++	s_movreld_b32 	s0, s0 																	//s[0+m0] = s0
++	s_nop 0 // hazard SALU M0=> S_MOVREL
++    s_add_u32		m0, m0, 1																//next sgpr index
++	s_cmp_lt_u32 	m0, s_restore_alloc_size 												//scc = (m0 < s_restore_alloc_size) ? 1 : 0
++	s_cbranch_scc1 	L_RESTORE_SGPR_LOOP														//SGPR restore (except s0) is complete?
++	s_mov_b32		s0, s_restore_tmp															/* SGPR restore on s0 */
++
++    /* 		restore HW registers	*/
++	//////////////////////////////
++  L_RESTORE_HWREG:
++    s_mov_b32		s_restore_buf_rsrc2, 0x4												//NUM_RECORDS	in bytes
++	if (SWIZZLE_EN)
++		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
++	else
++		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
++	end
++
++	read_sgpr_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//M0
++	read_sgpr_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//PC
++	read_sgpr_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)
++	read_sgpr_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//EXEC
++	read_sgpr_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)
++	read_sgpr_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//STATUS
++	read_sgpr_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//TRAPSTS
++    read_sgpr_from_mem(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//XNACK_MASK_LO
++	read_sgpr_from_mem(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//XNACK_MASK_HI
++	read_sgpr_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//MODE
++
++	s_waitcnt		lgkmcnt(0)																						//from now on, it is safe to restore STATUS and IB_STS
++
++	s_mov_b32 s_restore_tmp, s_restore_pc_hi
++	s_and_b32 s_restore_pc_hi, s_restore_tmp, 0x0000ffff    	//pc[47:32]        //Do it here in order not to affect STATUS
++
++	//for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise:
++	if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))
++		s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8            //pc[31:0]+8	  //two back-to-back s_trap are used (first for save and second for restore)
++		s_addc_u32	s_restore_pc_hi, s_restore_pc_hi, 0x0		 //carry bit over
++	end
++	if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL))
++		s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4            //pc[31:0]+4     // save is hack through s_trap but restore is normal
++		s_addc_u32	s_restore_pc_hi, s_restore_pc_hi, 0x0		 //carry bit over
++	end
++
++	s_mov_b32 		m0, 		s_restore_m0
++	s_mov_b32 		exec_lo, 	s_restore_exec_lo
++	s_mov_b32 		exec_hi, 	s_restore_exec_hi
++
++	s_and_b32		s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts
++	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0
++	s_and_b32		s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts
++	s_lshr_b32		s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT
++	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0
++	//s_setreg_b32 	hwreg(HW_REG_TRAPSTS), 	s_restore_trapsts      //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore
++	s_setreg_b32 	hwreg(HW_REG_MODE), 	s_restore_mode
++	//reuse s_restore_m0 as a temp register
++	s_and_b32		s_restore_m0, s_restore_tmp, S_SAVE_PC_HI_RCNT_MASK
++	s_lshr_b32		s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT
++	s_lshl_b32		s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT
++	s_mov_b32		s_restore_mode, 0x0																				//IB_STS is zero
++	s_or_b32		s_restore_mode, s_restore_mode, s_restore_m0
++	s_and_b32		s_restore_m0, s_restore_tmp, S_SAVE_PC_HI_FIRST_REPLAY_MASK
++	s_lshr_b32		s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
++	s_lshl_b32		s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT
++	s_or_b32		s_restore_mode, s_restore_mode, s_restore_m0
++    s_and_b32       s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK
++    s_lshr_b32		s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT
++	s_setreg_b32 	hwreg(HW_REG_IB_STS), 	s_restore_mode
++
++	s_and_b64    exec, exec, exec  // Restore STATUS.EXECZ, not writable by s_setreg_b32
++	s_and_b64    vcc, vcc, vcc  // Restore STATUS.VCCZ, not writable by s_setreg_b32
++	s_setreg_b32 	hwreg(HW_REG_STATUS), 	s_restore_status
++
++	s_barrier													//barrier to ensure the readiness of LDS before access attemps from any other wave in the same TG //FIXME not performance-optimal at this time
++
++
++//	s_rfe_b64 s_restore_pc_lo                              		//Return to the main shader program and resume execution
++    s_rfe_restore_b64  s_restore_pc_lo, s_restore_m0            // s_restore_m0[0] is used to set STATUS.inst_atc
++
++
++/**************************************************************************/
++/*                     	the END								              */
++/**************************************************************************/
++L_END_PGM:
++	s_endpgm
++
++end
++
++
++/**************************************************************************/
++/*                     	the helper functions							  */
++/**************************************************************************/
++
++function write_sgpr_to_mem(s, s_rsrc, s_mem_offset, use_sqc, use_mtbuf)
++	if (use_sqc)
++		s_mov_b32 exec_lo, m0					//assuming exec_lo is not needed anymore from this point on
++		s_mov_b32 m0, s_mem_offset
++		s_buffer_store_dword s, s_rsrc, m0		glc:1
++		s_add_u32		s_mem_offset, s_mem_offset, 4
++		s_mov_b32	m0, exec_lo
++	elsif (use_mtbuf)
++		v_mov_b32	v0,	s
++        tbuffer_store_format_x v0, v0, s_rsrc, s_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
++		s_add_u32		s_mem_offset, s_mem_offset, 256
++	else
++		v_mov_b32	v0,	s
++		buffer_store_dword	v0, v0, s_rsrc, s_mem_offset	slc:1 glc:1
++		s_add_u32		s_mem_offset, s_mem_offset, 256
++	end
++end
++
++
++
++function read_sgpr_from_mem(s, s_rsrc, s_mem_offset, use_sqc)
++	s_buffer_load_dword s, s_rsrc, s_mem_offset		glc:1
++	if (use_sqc)
++		s_add_u32		s_mem_offset, s_mem_offset, 4
++	else
++		s_add_u32		s_mem_offset, s_mem_offset, 256
++	end
++end
++
++
++
++
++
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index 2e6a5dc662f7..6bfbbadcfa06 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -555,6 +555,10 @@ static void kfd_cwsr_init(struct kfd_dev *kfd)
+ 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
+ 			kfd->cwsr_isa = cwsr_trap_gfx8_hex;
+ 			kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
++		} else if (kfd->device_info->asic_family == CHIP_ARCTURUS) {
++			BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE);
++			kfd->cwsr_isa = cwsr_trap_arcturus_hex;
++			kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
+ 		} else if (kfd->device_info->asic_family < CHIP_NAVI10) {
+ 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
+ 			kfd->cwsr_isa = cwsr_trap_gfx9_hex;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2977-drm-amdgpu-skip-gfx-9-common-golden-settings-for-arc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2977-drm-amdgpu-skip-gfx-9-common-golden-settings-for-arc.patch
new file mode 100644
index 00000000..5e56fe01
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2977-drm-amdgpu-skip-gfx-9-common-golden-settings-for-arc.patch
@@ -0,0 +1,34 @@
+From 18e8facaae3db508b7155d9a68dde44672b0ceba Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Sat, 29 Jun 2019 22:22:13 +0800
+Subject: [PATCH 2977/4256] drm/amdgpu: skip gfx 9 common golden settings for
+ arct
+
+They are not needed by arct
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index f85b92bbc5ec..3bcf02bf4c9b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -386,8 +386,9 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
+ 		break;
+ 	}
+ 
+-	soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
+-					(const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
++	if (adev->asic_type != CHIP_ARCTURUS)
++		soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
++						(const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
+ }
+ 
+ static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2978-drm-amdgpu-limit-sdma-instances-to-2-for-Arcturus-in.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2978-drm-amdgpu-limit-sdma-instances-to-2-for-Arcturus-in.patch
new file mode 100644
index 00000000..d0ea49e9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2978-drm-amdgpu-limit-sdma-instances-to-2-for-Arcturus-in.patch
@@ -0,0 +1,31 @@
+From d52cbb52f27d046aaef4c35cd52d0c95544ecb97 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Sun, 30 Jun 2019 11:35:32 +0800
+Subject: [PATCH 2978/4256] drm/amdgpu: limit sdma instances to 2 for Arcturus
+ in BU phase
+
+Another 6 sdma instances do not work at present. Disable them to unblock KFD
+for silicon bringup as a workaround
+
+Signed-off-by: Le Ma <le.ma@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 48d4597ef9f6..9c7a3eb9a9a0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1601,7 +1601,7 @@ static int sdma_v4_0_early_init(void *handle)
+ 	if (adev->asic_type == CHIP_RAVEN)
+ 		adev->sdma.num_instances = 1;
+ 	else if (adev->asic_type == CHIP_ARCTURUS)
+-		adev->sdma.num_instances = 8;
++		adev->sdma.num_instances = 2;
+ 	else
+ 		adev->sdma.num_instances = 2;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2979-drm-amdkfd-Add-device-id-for-real-asics.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2979-drm-amdkfd-Add-device-id-for-real-asics.patch
new file mode 100644
index 00000000..4423038c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2979-drm-amdkfd-Add-device-id-for-real-asics.patch
@@ -0,0 +1,30 @@
+From aa23a17644b7b141d6fc89f36000857fd54011d8 Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Tue, 9 Jul 2019 13:16:37 -0500
+Subject: [PATCH 2979/4256] drm/amdkfd: Add device id for real asics
+
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index 6bfbbadcfa06..52851e658bda 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -469,7 +469,9 @@ static const struct kfd_deviceid supported_devices[] = {
+ 	{ 0x66a4, &vega20_device_info },	/* Vega20 */
+ 	{ 0x66a7, &vega20_device_info },	/* Vega20 */
+ 	{ 0x66af, &vega20_device_info },	/* Vega20 */
+-	/* Navi10 */
++	{ 0x738C, &arcturus_device_info },	/* Arcturus */
++	{ 0x7388, &arcturus_device_info },	/* Arcturus */
++	{ 0x738E, &arcturus_device_info },	/* Arcturus */
+ 	{ 0x7310, &navi10_device_info },	/* Navi10 */
+ 	{ 0x7312, &navi10_device_info },	/* Navi10 */
+ 	{ 0x7318, &navi10_device_info },	/* Navi10 */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2980-drm-amdgpu-Add-more-detail-to-the-VM-fault-printing.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2980-drm-amdgpu-Add-more-detail-to-the-VM-fault-printing.patch
new file mode 100644
index 00000000..daf65f4b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2980-drm-amdgpu-Add-more-detail-to-the-VM-fault-printing.patch
@@ -0,0 +1,50 @@
+From 3e4558618d5d3a6cfb43564530a4f09853214dd8 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Mon, 1 Jul 2019 00:48:40 -0400
+Subject: [PATCH 2980/4256] drm/amdgpu: Add more detail to the VM fault
+ printing
+
+With the printing, we don't need to parse the value on our own any more.
+
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 18 ++++++++++++++++--
+ 1 file changed, 16 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 0a7e16fe602d..f99e02649f81 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -355,12 +355,26 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
+ 			entry->src_id, entry->ring_id, entry->vmid,
+ 			entry->pasid, task_info.process_name, task_info.tgid,
+ 			task_info.task_name, task_info.pid);
+-		dev_err(adev->dev, "  in page starting at address 0x%016llx from %d\n",
++		dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
+ 			addr, entry->client_id);
+-		if (!amdgpu_sriov_vf(adev))
++		if (!amdgpu_sriov_vf(adev)) {
+ 			dev_err(adev->dev,
+ 				"VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
+ 				status);
++			dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
++				REG_GET_FIELD(status,
++				VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
++			dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
++				REG_GET_FIELD(status,
++				VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
++			dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
++				REG_GET_FIELD(status,
++				VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
++			dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
++				REG_GET_FIELD(status,
++				VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
++
++		}
+ 	}
+ 
+ 	return 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2981-drm-amdkfd-Merge-gfx9-arcturus-trap-handlers-add-ACC.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2981-drm-amdkfd-Merge-gfx9-arcturus-trap-handlers-add-ACC.patch
new file mode 100644
index 00000000..e494459e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2981-drm-amdkfd-Merge-gfx9-arcturus-trap-handlers-add-ACC.patch
@@ -0,0 +1,1588 @@
+From 76d52d9b95294e02a49dfb085352bc540f44e7ce Mon Sep 17 00:00:00 2001
+From: Jay Cornwall <Jay.Cornwall@amd.com>
+Date: Mon, 1 Jul 2019 15:46:56 -0500
+Subject: [PATCH 2981/4256] drm/amdkfd: Merge gfx9/arcturus trap handlers, add
+ ACC VGPR save
+
+ACC VGPRs are a secondary VGPR set of same size as the primary VGPRs.
+Save them as a block immediately following VGPRs.
+
+Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h    | 627 +++++++++++----
+ .../amd/amdkfd/cwsr_trap_handler_arcturus.asm | 746 ------------------
+ .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm |  83 +-
+ 3 files changed, 538 insertions(+), 918 deletions(-)
+ delete mode 100644 drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_arcturus.asm
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+index fc9a3f7dfeb8..7274baff5c16 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+@@ -974,200 +974,487 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
+ 	0xbf9f0000, 0x00000000,
+ };
+ static const uint32_t cwsr_trap_arcturus_hex[] = {
+-	0xbf820001, 0xbf8200ca,
+-	0xb8f0f802, 0x89708670,
+-	0xb8f1f803, 0x8671ff71,
+-	0x00000400, 0xbf850008,
+-	0xb8f1f803, 0x8671ff71,
+-	0x000001ff, 0xbf850001,
+-	0x806c846c, 0x866dff6d,
+-	0x0000ffff, 0xbe801f6c,
+-	0xb8f1f803, 0x8671ff71,
+-	0x00000100, 0xbf840006,
+-	0xbef60080, 0xb9760203,
+-	0x866dff6d, 0x0000ffff,
++	0xbf820001, 0xbf8202bd,
++	0xb8f8f802, 0x89788678,
++	0xb8fbf803, 0x866eff7b,
++	0x00000400, 0xbf85003b,
++	0x866eff7b, 0x00000800,
++	0xbf850003, 0x866eff7b,
++	0x00000100, 0xbf84000c,
++	0x866eff78, 0x00002000,
++	0xbf840005, 0xbf8e0010,
++	0xb8eef803, 0x866eff6e,
++	0x00000400, 0xbf84fffb,
++	0x8778ff78, 0x00002000,
+ 	0x80ec886c, 0x82ed806d,
+-	0xbef60080, 0xb9760283,
+-	0xbef20068, 0xbef30069,
+-	0xb8f62407, 0x8e769b76,
+-	0x876d766d, 0xb8f603c7,
+-	0x8e769a76, 0x876d766d,
+-	0xb8f6f807, 0x8676ff76,
+-	0x00007fff, 0xb976f807,
+-	0xbeee007e, 0xbeef007f,
+-	0xbefe0180, 0xbf900004,
+-	0xbf8e0002, 0xbf88fffe,
++	0xb8eef807, 0x866fff6e,
++	0x001f8000, 0x8e6f8b6f,
++	0x8977ff77, 0xfc000000,
++	0x87776f77, 0x896eff6e,
++	0x001f8000, 0xb96ef807,
++	0xb8faf812, 0xb8fbf813,
++	0x8efa887a, 0xc0071bbd,
++	0x00000000, 0xbf8cc07f,
++	0xc0071ebd, 0x00000008,
++	0xbf8cc07f, 0x86ee6e6e,
++	0xbf840001, 0xbe801d6e,
++	0xb8fbf803, 0x867bff7b,
++	0x000001ff, 0xbf850002,
++	0x806c846c, 0x826d806d,
++	0x866dff6d, 0x0000ffff,
++	0x8f6e8b77, 0x866eff6e,
++	0x001f8000, 0xb96ef807,
++	0x86fe7e7e, 0x86ea6a6a,
++	0x8f6e8378, 0xb96ee0c2,
++	0xbf800002, 0xb9780002,
++	0xbe801f6c, 0x866dff6d,
++	0x0000ffff, 0xbefa0080,
++	0xb97a0283, 0xb8fa2407,
++	0x8e7a9b7a, 0x876d7a6d,
++	0xb8fa03c7, 0x8e7a9a7a,
++	0x876d7a6d, 0xb8faf807,
++	0x867aff7a, 0x00007fff,
++	0xb97af807, 0xbeee007e,
++	0xbeef007f, 0xbefe0180,
++	0xbf900004, 0x877a8478,
++	0xb97af802, 0xbf8e0002,
++	0xbf88fffe, 0xb8fa2a05,
++	0x807a817a, 0x8e7a8a7a,
++	0x8e7a817a, 0xb8fb1605,
++	0x807b817b, 0x8e7b867b,
++	0x807a7b7a, 0x807a7e7a,
++	0x827b807f, 0x867bff7b,
++	0x0000ffff, 0xc04b1c3d,
++	0x00000050, 0xbf8cc07f,
++	0xc04b1d3d, 0x00000060,
++	0xbf8cc07f, 0xc0431e7d,
++	0x00000074, 0xbf8cc07f,
+ 	0xbef4007e, 0x8675ff7f,
+ 	0x0000ffff, 0x8775ff75,
+ 	0x00040000, 0xbef60080,
+ 	0xbef700ff, 0x00807fac,
+-	0x8676ff7f, 0x08000000,
+-	0x8f768376, 0x87777677,
+-	0x8676ff7f, 0x70000000,
+-	0x8f768176, 0x87777677,
+-	0xbefb007c, 0xbefa0080,
+-	0xbf8a0000, 0x8676ff7f,
+-	0x04000000, 0xbf840012,
+-	0xbefe00c1, 0xbeff00c1,
+-	0xb8f14306, 0x8671c171,
+-	0xbf84000d, 0x8e718671,
+-	0x8e718271, 0xbef60071,
+-	0xbef600ff, 0x01000000,
++	0x867aff7f, 0x08000000,
++	0x8f7a837a, 0x87777a77,
++	0x867aff7f, 0x70000000,
++	0x8f7a817a, 0x87777a77,
++	0xbef1007c, 0xbef00080,
++	0xb8f02a05, 0x80708170,
++	0x8e708a70, 0x8e708170,
++	0xb8fa1605, 0x807a817a,
++	0x8e7a867a, 0x80707a70,
++	0xbef60084, 0xbef600ff,
++	0x01000000, 0xbefe007c,
++	0xbefc0070, 0xc0611c7a,
++	0x0000007c, 0xbf8cc07f,
++	0x80708470, 0xbefc007e,
++	0xbefe007c, 0xbefc0070,
++	0xc0611b3a, 0x0000007c,
++	0xbf8cc07f, 0x80708470,
++	0xbefc007e, 0xbefe007c,
++	0xbefc0070, 0xc0611b7a,
++	0x0000007c, 0xbf8cc07f,
++	0x80708470, 0xbefc007e,
++	0xbefe007c, 0xbefc0070,
++	0xc0611bba, 0x0000007c,
++	0xbf8cc07f, 0x80708470,
++	0xbefc007e, 0xbefe007c,
++	0xbefc0070, 0xc0611bfa,
++	0x0000007c, 0xbf8cc07f,
++	0x80708470, 0xbefc007e,
++	0xbefe007c, 0xbefc0070,
++	0xc0611e3a, 0x0000007c,
++	0xbf8cc07f, 0x80708470,
++	0xbefc007e, 0xb8fbf803,
++	0xbefe007c, 0xbefc0070,
++	0xc0611efa, 0x0000007c,
++	0xbf8cc07f, 0x80708470,
++	0xbefc007e, 0xbefe007c,
++	0xbefc0070, 0xc0611a3a,
++	0x0000007c, 0xbf8cc07f,
++	0x80708470, 0xbefc007e,
++	0xbefe007c, 0xbefc0070,
++	0xc0611a7a, 0x0000007c,
++	0xbf8cc07f, 0x80708470,
++	0xbefc007e, 0xb8f1f801,
++	0xbefe007c, 0xbefc0070,
++	0xc0611c7a, 0x0000007c,
++	0xbf8cc07f, 0x80708470,
++	0xbefc007e, 0x867aff7f,
++	0x04000000, 0xbeef0080,
++	0x876f6f7a, 0xb8f02a05,
++	0x80708170, 0x8e708a70,
++	0x8e708170, 0xb8fb1605,
++	0x807b817b, 0x8e7b847b,
++	0x8e76827b, 0xbef600ff,
++	0x01000000, 0xbef20174,
++	0x80747074, 0x82758075,
+ 	0xbefc0080, 0xbf800000,
+-	0x807cff7c, 0x00000100,
+-	0x807aff7a, 0x00000100,
+-	0xbf0a717c, 0xbf85fffa,
++	0xbe802b00, 0xbe822b02,
++	0xbe842b04, 0xbe862b06,
++	0xbe882b08, 0xbe8a2b0a,
++	0xbe8c2b0c, 0xbe8e2b0e,
++	0xc06b003a, 0x00000000,
++	0xbf8cc07f, 0xc06b013a,
++	0x00000010, 0xbf8cc07f,
++	0xc06b023a, 0x00000020,
++	0xbf8cc07f, 0xc06b033a,
++	0x00000030, 0xbf8cc07f,
++	0x8074c074, 0x82758075,
++	0x807c907c, 0xbf0a7b7c,
++	0xbf85ffe7, 0xbef40172,
++	0xbef00080, 0xbefe00c1,
++	0xbeff00c1, 0xbee80080,
++	0xbee90080, 0xbef600ff,
++	0x01000000, 0x867aff78,
++	0x00400000, 0xbf850003,
++	0xb8faf803, 0x897a7aff,
++	0x10000000, 0xbf85004d,
++	0xbe840080, 0xd2890000,
++	0x00000900, 0x80048104,
++	0xd2890001, 0x00000900,
++	0x80048104, 0xd2890002,
++	0x00000900, 0x80048104,
++	0xd2890003, 0x00000900,
++	0x80048104, 0xc069003a,
++	0x00000070, 0xbf8cc07f,
++	0x80709070, 0xbf06c004,
++	0xbf84ffee, 0xbe840080,
++	0xd2890000, 0x00000901,
++	0x80048104, 0xd2890001,
++	0x00000901, 0x80048104,
++	0xd2890002, 0x00000901,
++	0x80048104, 0xd2890003,
++	0x00000901, 0x80048104,
++	0xc069003a, 0x00000070,
++	0xbf8cc07f, 0x80709070,
++	0xbf06c004, 0xbf84ffee,
++	0xbe840080, 0xd2890000,
++	0x00000902, 0x80048104,
++	0xd2890001, 0x00000902,
++	0x80048104, 0xd2890002,
++	0x00000902, 0x80048104,
++	0xd2890003, 0x00000902,
++	0x80048104, 0xc069003a,
++	0x00000070, 0xbf8cc07f,
++	0x80709070, 0xbf06c004,
++	0xbf84ffee, 0xbe840080,
++	0xd2890000, 0x00000903,
++	0x80048104, 0xd2890001,
++	0x00000903, 0x80048104,
++	0xd2890002, 0x00000903,
++	0x80048104, 0xd2890003,
++	0x00000903, 0x80048104,
++	0xc069003a, 0x00000070,
++	0xbf8cc07f, 0x80709070,
++	0xbf06c004, 0xbf84ffee,
++	0xbf820008, 0xe0724000,
++	0x701d0000, 0xe0724100,
++	0x701d0100, 0xe0724200,
++	0x701d0200, 0xe0724300,
++	0x701d0300, 0xbefe00c1,
++	0xbeff00c1, 0xb8fb4306,
++	0x867bc17b, 0xbf840064,
++	0xbf8a0000, 0x867aff6f,
++	0x04000000, 0xbf840060,
++	0x8e7b867b, 0x8e7b827b,
++	0xbef6007b, 0xb8f02a05,
++	0x80708170, 0x8e708a70,
++	0x8e708170, 0xb8fa1605,
++	0x807a817a, 0x8e7a867a,
++	0x80707a70, 0x8070ff70,
++	0x00000080, 0xbef600ff,
++	0x01000000, 0xbefc0080,
++	0xd28c0002, 0x000100c1,
++	0xd28d0003, 0x000204c1,
++	0x867aff78, 0x00400000,
++	0xbf850003, 0xb8faf803,
++	0x897a7aff, 0x10000000,
++	0xbf850030, 0x24040682,
++	0xd86e4000, 0x00000002,
++	0xbf8cc07f, 0xbe840080,
++	0xd2890000, 0x00000900,
++	0x80048104, 0xd2890001,
++	0x00000900, 0x80048104,
++	0xd2890002, 0x00000900,
++	0x80048104, 0xd2890003,
++	0x00000900, 0x80048104,
++	0xc069003a, 0x00000070,
++	0xbf8cc07f, 0x80709070,
++	0xbf06c004, 0xbf84ffee,
++	0xbe840080, 0xd2890000,
++	0x00000901, 0x80048104,
++	0xd2890001, 0x00000901,
++	0x80048104, 0xd2890002,
++	0x00000901, 0x80048104,
++	0xd2890003, 0x00000901,
++	0x80048104, 0xc069003a,
++	0x00000070, 0xbf8cc07f,
++	0x80709070, 0xbf06c004,
++	0xbf84ffee, 0x680404ff,
++	0x00000200, 0xd0c9006a,
++	0x0000f702, 0xbf87ffd2,
++	0xbf820015, 0xd1060002,
++	0x00011103, 0x7e0602ff,
++	0x00000200, 0xbefc00ff,
++	0x00010000, 0xbe800077,
++	0x8677ff77, 0xff7fffff,
++	0x8777ff77, 0x00058000,
++	0xd8ec0000, 0x00000002,
++	0xbf8cc07f, 0xe0765000,
++	0x701d0002, 0x68040702,
++	0xd0c9006a, 0x0000f702,
++	0xbf87fff7, 0xbef70000,
++	0xbef000ff, 0x00000400,
+ 	0xbefe00c1, 0xbeff00c1,
+-	0xb8f12a05, 0x80718171,
+-	0x8e718271, 0x8e768871,
++	0xb8fb2a05, 0x807b817b,
++	0x8e7b827b, 0x8e76887b,
+ 	0xbef600ff, 0x01000000,
++	0xbefc0084, 0xbf0a7b7c,
++	0xbf84006d, 0xbf11017c,
++	0x807bff7b, 0x00001000,
++	0x867aff78, 0x00400000,
++	0xbf850003, 0xb8faf803,
++	0x897a7aff, 0x10000000,
++	0xbf850051, 0xbe840080,
++	0xd2890000, 0x00000900,
++	0x80048104, 0xd2890001,
++	0x00000900, 0x80048104,
++	0xd2890002, 0x00000900,
++	0x80048104, 0xd2890003,
++	0x00000900, 0x80048104,
++	0xc069003a, 0x00000070,
++	0xbf8cc07f, 0x80709070,
++	0xbf06c004, 0xbf84ffee,
++	0xbe840080, 0xd2890000,
++	0x00000901, 0x80048104,
++	0xd2890001, 0x00000901,
++	0x80048104, 0xd2890002,
++	0x00000901, 0x80048104,
++	0xd2890003, 0x00000901,
++	0x80048104, 0xc069003a,
++	0x00000070, 0xbf8cc07f,
++	0x80709070, 0xbf06c004,
++	0xbf84ffee, 0xbe840080,
++	0xd2890000, 0x00000902,
++	0x80048104, 0xd2890001,
++	0x00000902, 0x80048104,
++	0xd2890002, 0x00000902,
++	0x80048104, 0xd2890003,
++	0x00000902, 0x80048104,
++	0xc069003a, 0x00000070,
++	0xbf8cc07f, 0x80709070,
++	0xbf06c004, 0xbf84ffee,
++	0xbe840080, 0xd2890000,
++	0x00000903, 0x80048104,
++	0xd2890001, 0x00000903,
++	0x80048104, 0xd2890002,
++	0x00000903, 0x80048104,
++	0xd2890003, 0x00000903,
++	0x80048104, 0xc069003a,
++	0x00000070, 0xbf8cc07f,
++	0x80709070, 0xbf06c004,
++	0xbf84ffee, 0x807c847c,
++	0xbf0a7b7c, 0xbf85ffb1,
++	0xbf9c0000, 0xbf820012,
++	0x7e000300, 0x7e020301,
++	0x7e040302, 0x7e060303,
++	0xe0724000, 0x701d0000,
++	0xe0724100, 0x701d0100,
++	0xe0724200, 0x701d0200,
++	0xe0724300, 0x701d0300,
++	0x807c847c, 0x8070ff70,
++	0x00000400, 0xbf0a7b7c,
++	0xbf85ffef, 0xbf9c0000,
+ 	0xbefc0080, 0xbf11017c,
+-	0x8071ff71, 0x00001000,
+-	0x7e000300, 0xe0724000,
+-	0x7a1d0000, 0x807c817c,
+-	0x807aff7a, 0x00000100,
+-	0xbf0a717c, 0xbf85fff8,
+-	0xbf9c0000, 0xbefe00c1,
+-	0xbeff00c1, 0xb8f12a05,
+-	0x80718171, 0x8e718271,
+-	0x8e768871, 0xbef600ff,
+-	0x01000000, 0xbefc0080,
+-	0xbf11017c, 0x8071ff71,
+-	0x00001000, 0xd3d84000,
+-	0x18000100, 0x7e000000,
+-	0x7e000000, 0xe0724000,
+-	0x7a1d0000, 0x807c817c,
+-	0x807aff7a, 0x00000100,
+-	0xbf0a717c, 0xbf85fff5,
+-	0xbf9c0000, 0xb8f11605,
+-	0x80718171, 0x8e718471,
+-	0x8e768871, 0xbef600ff,
+-	0x01000000, 0xbefc0080,
+-	0xbf800000, 0xbe802a00,
+-	0x7e000200, 0xe0724000,
+-	0x7a1d0000, 0x807aff7a,
+-	0x00000100, 0x807c817c,
+-	0xbf0a717c, 0xbf85fff7,
+-	0xbef60084, 0xbef600ff,
+-	0x01000000, 0x7e00027b,
+-	0xe0724000, 0x7a1d0000,
+-	0x807aff7a, 0x00000100,
+-	0x7e00026c, 0xe0724000,
+-	0x7a1d0000, 0x807aff7a,
+-	0x00000100, 0x7e00026d,
+-	0xe0724000, 0x7a1d0000,
+-	0x807aff7a, 0x00000100,
+-	0x7e00026e, 0xe0724000,
+-	0x7a1d0000, 0x807aff7a,
+-	0x00000100, 0x7e00026f,
+-	0xe0724000, 0x7a1d0000,
+-	0x807aff7a, 0x00000100,
+-	0x7e000270, 0xe0724000,
+-	0x7a1d0000, 0x807aff7a,
+-	0x00000100, 0xb8f1f803,
+-	0x7e000271, 0xe0724000,
+-	0x7a1d0000, 0x807aff7a,
+-	0x00000100, 0x7e000272,
+-	0xe0724000, 0x7a1d0000,
+-	0x807aff7a, 0x00000100,
+-	0x7e000273, 0xe0724000,
+-	0x7a1d0000, 0x807aff7a,
+-	0x00000100, 0xb8fbf801,
+-	0x7e00027b, 0xe0724000,
+-	0x7a1d0000, 0x807aff7a,
+-	0x00000100, 0xbf8200bb,
+-	0xbef4007e, 0x8675ff7f,
+-	0x0000ffff, 0x8775ff75,
+-	0x00040000, 0xbef60080,
+-	0xbef700ff, 0x00807fac,
+-	0x8672ff7f, 0x08000000,
+-	0x8f728372, 0x87777277,
+-	0x8672ff7f, 0x70000000,
+-	0x8f728172, 0x87777277,
+-	0xbef80080, 0x8672ff7f,
+-	0x04000000, 0xbf840011,
++	0x867aff78, 0x00400000,
++	0xbf850003, 0xb8faf803,
++	0x897a7aff, 0x10000000,
++	0xbf850059, 0xd3d84000,
++	0x18000100, 0xd3d84001,
++	0x18000101, 0xd3d84002,
++	0x18000102, 0xd3d84003,
++	0x18000103, 0xbe840080,
++	0xd2890000, 0x00000900,
++	0x80048104, 0xd2890001,
++	0x00000900, 0x80048104,
++	0xd2890002, 0x00000900,
++	0x80048104, 0xd2890003,
++	0x00000900, 0x80048104,
++	0xc069003a, 0x00000070,
++	0xbf8cc07f, 0x80709070,
++	0xbf06c004, 0xbf84ffee,
++	0xbe840080, 0xd2890000,
++	0x00000901, 0x80048104,
++	0xd2890001, 0x00000901,
++	0x80048104, 0xd2890002,
++	0x00000901, 0x80048104,
++	0xd2890003, 0x00000901,
++	0x80048104, 0xc069003a,
++	0x00000070, 0xbf8cc07f,
++	0x80709070, 0xbf06c004,
++	0xbf84ffee, 0xbe840080,
++	0xd2890000, 0x00000902,
++	0x80048104, 0xd2890001,
++	0x00000902, 0x80048104,
++	0xd2890002, 0x00000902,
++	0x80048104, 0xd2890003,
++	0x00000902, 0x80048104,
++	0xc069003a, 0x00000070,
++	0xbf8cc07f, 0x80709070,
++	0xbf06c004, 0xbf84ffee,
++	0xbe840080, 0xd2890000,
++	0x00000903, 0x80048104,
++	0xd2890001, 0x00000903,
++	0x80048104, 0xd2890002,
++	0x00000903, 0x80048104,
++	0xd2890003, 0x00000903,
++	0x80048104, 0xc069003a,
++	0x00000070, 0xbf8cc07f,
++	0x80709070, 0xbf06c004,
++	0xbf84ffee, 0x807c847c,
++	0xbf0a7b7c, 0xbf85ffa9,
++	0xbf9c0000, 0xbf820016,
++	0xd3d84000, 0x18000100,
++	0xd3d84001, 0x18000101,
++	0xd3d84002, 0x18000102,
++	0xd3d84003, 0x18000103,
++	0xe0724000, 0x701d0000,
++	0xe0724100, 0x701d0100,
++	0xe0724200, 0x701d0200,
++	0xe0724300, 0x701d0300,
++	0x807c847c, 0x8070ff70,
++	0x00000400, 0xbf0a7b7c,
++	0xbf85ffeb, 0xbf9c0000,
++	0xbf820106, 0xbef4007e,
++	0x8675ff7f, 0x0000ffff,
++	0x8775ff75, 0x00040000,
++	0xbef60080, 0xbef700ff,
++	0x00807fac, 0x866eff7f,
++	0x08000000, 0x8f6e836e,
++	0x87776e77, 0x866eff7f,
++	0x70000000, 0x8f6e816e,
++	0x87776e77, 0x866eff7f,
++	0x04000000, 0xbf84001f,
+ 	0xbefe00c1, 0xbeff00c1,
+ 	0xb8ef4306, 0x866fc16f,
+-	0xbf84000c, 0x8e6f866f,
++	0xbf84001a, 0x8e6f866f,
+ 	0x8e6f826f, 0xbef6006f,
++	0xb8f82a05, 0x80788178,
++	0x8e788a78, 0x8e788178,
++	0xb8ee1605, 0x806e816e,
++	0x8e6e866e, 0x80786e78,
++	0x8078ff78, 0x00000080,
+ 	0xbef600ff, 0x01000000,
+-	0xbefc0080, 0x807cff7c,
+-	0x00000100, 0x8078ff78,
+-	0x00000100, 0xbf0a6f7c,
+-	0xbf85fffa, 0xbefe00c1,
+-	0xbeff00c1, 0xb8ef2a05,
+-	0x806f816f, 0x8e6f826f,
+-	0x8e76886f, 0xbef600ff,
+-	0x01000000, 0xbef20078,
+-	0x8078ff78, 0x00000100,
+-	0xbefc0081, 0xbf11087c,
+-	0x806fff6f, 0x00008000,
+-	0xe0524000, 0x781d0000,
+-	0xbf8c0f70, 0x7e000300,
+-	0x807c817c, 0x8078ff78,
+-	0x00000100, 0xbf0a6f7c,
+-	0xbf85fff7, 0xbf9c0000,
++	0xbefc0080, 0xe0510000,
++	0x781d0000, 0xe0510100,
++	0x781d0000, 0x807cff7c,
++	0x00000200, 0x8078ff78,
++	0x00000200, 0xbf0a6f7c,
++	0xbf85fff6, 0xbef80080,
+ 	0xbefe00c1, 0xbeff00c1,
+ 	0xb8ef2a05, 0x806f816f,
+ 	0x8e6f826f, 0x8e76886f,
+-	0xbef600ff, 0x01000000,
+-	0xbefc0080, 0xbf11087c,
+-	0x806fff6f, 0x00008000,
++	0xbef90076, 0xbef600ff,
++	0x01000000, 0xbeee0078,
++	0x8078ff78, 0x00000400,
++	0xbef30079, 0x8079ff79,
++	0x00000400, 0xbefc0084,
++	0xbf11087c, 0x806fff6f,
++	0x00008000, 0xe0524000,
++	0x791d0000, 0xe0524100,
++	0x791d0100, 0xe0524200,
++	0x791d0200, 0xe0524300,
++	0x791d0300, 0x8079ff79,
++	0x00000400, 0xbf8c0f70,
++	0xd3d94000, 0x18000100,
++	0xd3d94001, 0x18000101,
++	0xd3d94002, 0x18000102,
++	0xd3d94003, 0x18000103,
+ 	0xe0524000, 0x781d0000,
+-	0xbf8c0f70, 0xd3d94000,
+-	0x18000100, 0x807c817c,
+-	0x8078ff78, 0x00000100,
+-	0xbf0a6f7c, 0xbf85fff6,
++	0xe0524100, 0x781d0100,
++	0xe0524200, 0x781d0200,
++	0xe0524300, 0x781d0300,
++	0xbf8c0f70, 0x7e000300,
++	0x7e020301, 0x7e040302,
++	0x7e060303, 0x807c847c,
++	0x8078ff78, 0x00000400,
++	0xbf0a6f7c, 0xbf85ffdb,
+ 	0xbf9c0000, 0xe0524000,
+-	0x721d0000, 0xb8ef1605,
++	0x731d0000, 0xe0524100,
++	0x731d0100, 0xe0524200,
++	0x731d0200, 0xe0524300,
++	0x731d0300, 0xbf8c0f70,
++	0xd3d94000, 0x18000100,
++	0xd3d94001, 0x18000101,
++	0xd3d94002, 0x18000102,
++	0xd3d94003, 0x18000103,
++	0xe0524000, 0x6e1d0000,
++	0xe0524100, 0x6e1d0100,
++	0xe0524200, 0x6e1d0200,
++	0xe0524300, 0x6e1d0300,
++	0xb8f82a05, 0x80788178,
++	0x8e788a78, 0x8e788178,
++	0xb8ee1605, 0x806e816e,
++	0x8e6e866e, 0x80786e78,
++	0x80f8c078, 0xb8ef1605,
+ 	0x806f816f, 0x8e6f846f,
+-	0x8e76886f, 0xbef600ff,
+-	0x01000000, 0xc0211cba,
+-	0x00000078, 0x8078ff78,
+-	0x00000100, 0xbefc0081,
+-	0xc021003a, 0x00000078,
+-	0x8078ff78, 0x00000100,
+-	0xbf8cc07f, 0xbe802c00,
+-	0xbf800000, 0x807c817c,
+-	0xbf0a6f7c, 0xbf85fff6,
+-	0xbe800072, 0xbef60084,
+-	0xbef600ff, 0x01000000,
+-	0xc0211bfa, 0x00000078,
+-	0x8078ff78, 0x00000100,
++	0x8e76826f, 0xbef600ff,
++	0x01000000, 0xbefc006f,
++	0xc031003a, 0x00000078,
++	0x80f8c078, 0xbf8cc07f,
++	0x80fc907c, 0xbf800000,
++	0xbe802d00, 0xbe822d02,
++	0xbe842d04, 0xbe862d06,
++	0xbe882d08, 0xbe8a2d0a,
++	0xbe8c2d0c, 0xbe8e2d0e,
++	0xbf06807c, 0xbf84fff0,
++	0xb8f82a05, 0x80788178,
++	0x8e788a78, 0x8e788178,
++	0xb8ee1605, 0x806e816e,
++	0x8e6e866e, 0x80786e78,
++	0xbef60084, 0xbef600ff,
++	0x01000000, 0xc0211bfa,
++	0x00000078, 0x80788478,
+ 	0xc0211b3a, 0x00000078,
+-	0x8078ff78, 0x00000100,
+-	0xc0211b7a, 0x00000078,
+-	0x8078ff78, 0x00000100,
+-	0xc0211eba, 0x00000078,
+-	0x8078ff78, 0x00000100,
+-	0xc0211efa, 0x00000078,
+-	0x8078ff78, 0x00000100,
++	0x80788478, 0xc0211b7a,
++	0x00000078, 0x80788478,
+ 	0xc0211c3a, 0x00000078,
+-	0x8078ff78, 0x00000100,
+-	0xc0211c7a, 0x00000078,
+-	0x8078ff78, 0x00000100,
++	0x80788478, 0xc0211c7a,
++	0x00000078, 0x80788478,
++	0xc0211eba, 0x00000078,
++	0x80788478, 0xc0211efa,
++	0x00000078, 0x80788478,
+ 	0xc0211a3a, 0x00000078,
+-	0x8078ff78, 0x00000100,
+-	0xc0211a7a, 0x00000078,
+-	0x8078ff78, 0x00000100,
++	0x80788478, 0xc0211a7a,
++	0x00000078, 0x80788478,
+ 	0xc0211cfa, 0x00000078,
+-	0x8078ff78, 0x00000100,
+-	0xbf8cc07f, 0xbef2006d,
+-	0x866dff72, 0x0000ffff,
+-	0xbefc006f, 0xbefe007a,
+-	0xbeff007b, 0x866f71ff,
++	0x80788478, 0xbf8cc07f,
++	0xbefc006f, 0xbefe0070,
++	0xbeff0071, 0x866f7bff,
+ 	0x000003ff, 0xb96f4803,
+-	0x866f71ff, 0xfffff800,
++	0x866f7bff, 0xfffff800,
+ 	0x8f6f8b6f, 0xb96fa2c3,
+-	0xb973f801, 0x866fff72,
+-	0xf8000000, 0x8f6f9b6f,
+-	0x8e6f906f, 0xbef30080,
+-	0x87736f73, 0x866fff72,
+-	0x04000000, 0x8f6f9a6f,
+-	0x8e6f8f6f, 0x87736f73,
+-	0x866fff70, 0x00800000,
+-	0x8f6f976f, 0xb973f807,
+-	0x86fe7e7e, 0x86ea6a6a,
+-	0xb970f802, 0xbf8a0000,
++	0xb973f801, 0xb8ee2a05,
++	0x806e816e, 0x8e6e8a6e,
++	0x8e6e816e, 0xb8ef1605,
++	0x806f816f, 0x8e6f866f,
++	0x806e6f6e, 0x806e746e,
++	0x826f8075, 0x866fff6f,
++	0x0000ffff, 0xc00b1c37,
++	0x00000050, 0xc00b1d37,
++	0x00000060, 0xc0031e77,
++	0x00000074, 0xbf8cc07f,
++	0x866fff6d, 0xf8000000,
++	0x8f6f9b6f, 0x8e6f906f,
++	0xbeee0080, 0x876e6f6e,
++	0x866fff6d, 0x04000000,
++	0x8f6f9a6f, 0x8e6f8f6f,
++	0x876e6f6e, 0x866fff7a,
++	0x00800000, 0x8f6f976f,
++	0xb96ef807, 0x866dff6d,
++	0x0000ffff, 0x86fe7e7e,
++	0x86ea6a6a, 0x8f6e837a,
++	0xb96ee0c2, 0xbf800002,
++	0xb97a0002, 0xbf8a0000,
+ 	0x95806f6c, 0xbf810000,
+ };
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_arcturus.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_arcturus.asm
+deleted file mode 100644
+index b83e2a643ddb..000000000000
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_arcturus.asm
++++ /dev/null
+@@ -1,746 +0,0 @@
+-shader main
+-
+-asic(DEFAULT)
+-
+-type(CS)
+-
+-/*************************************************************************/
+-/*					control on how to run the shader					 */
+-/*************************************************************************/
+-//any hack that needs to be made to run this code in EMU (either becasue various EMU code are not ready or no compute save & restore in EMU run)
+-var EMU_RUN_HACK					=	0
+-var EMU_RUN_HACK_RESTORE_NORMAL		=	0
+-var EMU_RUN_HACK_SAVE_NORMAL_EXIT	=	0
+-var	EMU_RUN_HACK_SAVE_SINGLE_WAVE	=	0
+-var EMU_RUN_HACK_SAVE_FIRST_TIME	= 	0					//for interrupted restore in which the first save is through EMU_RUN_HACK
+-var SAVE_LDS						= 	0
+-var WG_BASE_ADDR_LO					=   0x9000a000
+-var WG_BASE_ADDR_HI					=	0x0
+-var WAVE_SPACE						=	0x6000				//memory size that each wave occupies in workgroup state mem
+-var CTX_SAVE_CONTROL				=	0x0
+-var CTX_RESTORE_CONTROL				=	CTX_SAVE_CONTROL
+-var SIM_RUN_HACK					=	0					//any hack that needs to be made to run this code in SIM (either becasue various RTL code are not ready or no compute save & restore in RTL run)
+-var	SGPR_SAVE_USE_SQC				=	0					//use SQC D$ to do the write
+-var USE_MTBUF_INSTEAD_OF_MUBUF		=	0					//need to change BUF_DATA_FORMAT in S_SAVE_BUF_RSRC_WORD3_MISC from 0 to BUF_DATA_FORMAT_32 if set to 1 (i.e. 0x00827FAC)
+-var SWIZZLE_EN						=	0					//whether we use swizzled buffer addressing
+-
+-/**************************************************************************/
+-/*                     	variables							              */
+-/**************************************************************************/
+-var SQ_WAVE_STATUS_INST_ATC_SHIFT  = 23
+-var SQ_WAVE_STATUS_INST_ATC_MASK   = 0x00800000
+-var SQ_WAVE_STATUS_SPI_PRIO_MASK   = 0x00000006
+-
+-var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT	= 12
+-var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE		= 9
+-var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT	= 8
+-var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE	= 6
+-var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT	= 24
+-var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE	= 3						//FIXME	 sq.blk still has 4 bits at this time while SQ programming guide has 3 bits
+-
+-var	SQ_WAVE_TRAPSTS_SAVECTX_MASK	=	0x400
+-var SQ_WAVE_TRAPSTS_EXCE_MASK       =   0x1FF          			// Exception mask
+-var	SQ_WAVE_TRAPSTS_SAVECTX_SHIFT	=	10
+-var	SQ_WAVE_TRAPSTS_MEM_VIOL_MASK	=	0x100
+-var	SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT	=	8
+-var	SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK 	=	0x3FF
+-var	SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT 	=	0x0
+-var	SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE 	=	10
+-var	SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK 	=	0xFFFFF800
+-var	SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT 	=	11
+-var	SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE 	=	21
+-
+-var SQ_WAVE_IB_STS_RCNT_SHIFT			=	16					//FIXME
+-var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT	=	15					//FIXME
+-var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG	= 0x00007FFF	//FIXME
+-
+-var	SQ_BUF_RSRC_WORD1_ATC_SHIFT		=	24
+-var	SQ_BUF_RSRC_WORD3_MTYPE_SHIFT	=	27
+-
+-
+-/*      Save        */
+-var	S_SAVE_BUF_RSRC_WORD1_STRIDE		=	0x00040000  		//stride is 4 bytes
+-var	S_SAVE_BUF_RSRC_WORD3_MISC			= 	0x00807FAC			//SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE
+-
+-var	S_SAVE_SPI_INIT_ATC_MASK			=	0x08000000			//bit[27]: ATC bit
+-var	S_SAVE_SPI_INIT_ATC_SHIFT			=	27
+-var	S_SAVE_SPI_INIT_MTYPE_MASK			=	0x70000000			//bit[30:28]: Mtype
+-var	S_SAVE_SPI_INIT_MTYPE_SHIFT			=	28
+-var	S_SAVE_SPI_INIT_FIRST_WAVE_MASK		=	0x04000000			//bit[26]: FirstWaveInTG
+-var	S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT	=	26
+-
+-var S_SAVE_PC_HI_RCNT_SHIFT				=	27					//FIXME	 check with Brian to ensure all fields other than PC[47:0] can be used
+-var S_SAVE_PC_HI_RCNT_MASK				=   0xF8000000			//FIXME
+-var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT		=	26					//FIXME
+-var S_SAVE_PC_HI_FIRST_REPLAY_MASK		=	0x04000000			//FIXME
+-
+-var	s_save_spi_init_lo				=	exec_lo
+-var s_save_spi_init_hi				=	exec_hi
+-
+-var	s_save_pc_lo			=	ttmp0			//{TTMP1, TTMP0} = {3¡¯h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]}
+-var	s_save_pc_hi			=	ttmp1
+-var s_save_exec_lo			=	ttmp2
+-var s_save_exec_hi			= 	ttmp3
+-var	s_save_status			=	ttmp4
+-var	s_save_trapsts			=	ttmp5			//not really used until the end of the SAVE routine
+-var s_save_xnack_mask_lo	=	ttmp6
+-var s_save_xnack_mask_hi	=	ttmp7
+-var	s_save_buf_rsrc0		=	ttmp8
+-var	s_save_buf_rsrc1		=	ttmp9
+-var	s_save_buf_rsrc2		=	ttmp10
+-var	s_save_buf_rsrc3		=	ttmp11
+-
+-var s_save_mem_offset		= 	ttmp14
+-var s_save_alloc_size		=	s_save_trapsts			//conflict
+-var s_save_tmp              =   s_save_buf_rsrc2       	//shared with s_save_buf_rsrc2  (conflict: should not use mem access with s_save_tmp at the same time)
+-var s_save_m0				=	ttmp15
+-
+-/*      Restore     */
+-var	S_RESTORE_BUF_RSRC_WORD1_STRIDE			=	S_SAVE_BUF_RSRC_WORD1_STRIDE
+-var	S_RESTORE_BUF_RSRC_WORD3_MISC			= 	S_SAVE_BUF_RSRC_WORD3_MISC
+-
+-var	S_RESTORE_SPI_INIT_ATC_MASK			    =	0x08000000			//bit[27]: ATC bit
+-var	S_RESTORE_SPI_INIT_ATC_SHIFT			=	27
+-var	S_RESTORE_SPI_INIT_MTYPE_MASK			=	0x70000000			//bit[30:28]: Mtype
+-var	S_RESTORE_SPI_INIT_MTYPE_SHIFT			=	28
+-var	S_RESTORE_SPI_INIT_FIRST_WAVE_MASK		=	0x04000000			//bit[26]: FirstWaveInTG
+-var	S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT	    =	26
+-
+-var S_RESTORE_PC_HI_RCNT_SHIFT				=	S_SAVE_PC_HI_RCNT_SHIFT
+-var S_RESTORE_PC_HI_RCNT_MASK				=   S_SAVE_PC_HI_RCNT_MASK
+-var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT		=	S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
+-var S_RESTORE_PC_HI_FIRST_REPLAY_MASK		=	S_SAVE_PC_HI_FIRST_REPLAY_MASK
+-
+-var s_restore_spi_init_lo                   =   exec_lo
+-var s_restore_spi_init_hi                   =   exec_hi
+-
+-var s_restore_mem_offset		= 	ttmp12
+-var s_restore_alloc_size		=	ttmp3
+-var s_restore_tmp           	=   ttmp6
+-var s_restore_mem_offset_save	= 	s_restore_tmp 		//no conflict
+-
+-var s_restore_m0			=	s_restore_alloc_size	//no conflict
+-
+-var s_restore_mode			=  	ttmp7
+-
+-var	s_restore_pc_lo		    =	ttmp0
+-var	s_restore_pc_hi		    =	ttmp1
+-var s_restore_exec_lo		=	ttmp14
+-var s_restore_exec_hi		= 	ttmp15
+-var	s_restore_status	    =	ttmp4
+-var	s_restore_trapsts	    =	ttmp5
+-var s_restore_xnack_mask_lo	=	xnack_mask_lo
+-var s_restore_xnack_mask_hi	=	xnack_mask_hi
+-var	s_restore_buf_rsrc0		=	ttmp8
+-var	s_restore_buf_rsrc1		=	ttmp9
+-var	s_restore_buf_rsrc2		=	ttmp10
+-var	s_restore_buf_rsrc3		=	ttmp11
+-
+-/**************************************************************************/
+-/*                     	trap handler entry points			              */
+-/**************************************************************************/
+-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) 					//hack to use trap_id for determining save/restore
+-		//FIXME VCCZ un-init assertion s_getreg_b32  	s_save_status, hwreg(HW_REG_STATUS)			//save STATUS since we will change SCC
+-		s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000 				//change SCC
+-    	s_cmp_eq_u32 s_save_tmp, 0x007e0000  						//Save: trap_id = 0x7e. Restore: trap_id = 0x7f.
+-    	s_cbranch_scc0 L_JUMP_TO_RESTORE							//do not need to recover STATUS here  since we are going to RESTORE
+-		//FIXME  s_setreg_b32 	hwreg(HW_REG_STATUS), 	s_save_status		//need to recover STATUS since we are going to SAVE
+-		s_branch L_SKIP_RESTORE 									//NOT restore, SAVE actually
+-	else
+-		s_branch L_SKIP_RESTORE 									//NOT restore. might be a regular trap or save
+-    end
+-
+-L_JUMP_TO_RESTORE:
+-    s_branch L_RESTORE												//restore
+-
+-L_SKIP_RESTORE:
+-
+-	s_getreg_b32  	s_save_status, hwreg(HW_REG_STATUS)								//save STATUS since we will change SCC
+-	s_andn2_b32		s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK      //check whether this is for save
+-	s_getreg_b32  	s_save_trapsts, hwreg(HW_REG_TRAPSTS)
+-	s_and_b32		s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK	//check whether this is for save
+-	s_cbranch_scc1	L_SAVE															//this is the operation for save
+-
+-	// *********    Handle non-CWSR traps       *******************
+-    if (!EMU_RUN_HACK)
+-		s_getreg_b32     s_save_trapsts, hwreg(HW_REG_TRAPSTS)
+-		s_and_b32        s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK // Check whether it is an exception
+-		s_cbranch_scc1  L_EXCP_CASE   // Exception, jump back to the shader program directly.
+-		s_add_u32    ttmp0, ttmp0, 4   // S_TRAP case, add 4 to ttmp0
+-
+-		L_EXCP_CASE:
+-		s_and_b32    ttmp1, ttmp1, 0xFFFF
+-		s_rfe_b64    [ttmp0, ttmp1]
+-	end
+-    // *********        End handling of non-CWSR traps   *******************
+-
+-/**************************************************************************/
+-/*                     	save routine						              */
+-/**************************************************************************/
+-
+-L_SAVE:
+-
+-	//check whether there is mem_viol
+-	s_getreg_b32  	s_save_trapsts, hwreg(HW_REG_TRAPSTS)
+-	s_and_b32		s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK
+-	s_cbranch_scc0	L_NO_PC_REWIND
+-
+-	//if so, need rewind PC assuming GDS operation gets NACKed
+-	s_mov_b32       s_save_tmp, 0															//clear mem_viol bit
+-	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT, 1), s_save_tmp	//clear mem_viol bit
+-	s_and_b32 		s_save_pc_hi, s_save_pc_hi, 0x0000ffff    //pc[47:32]
+-	s_sub_u32 		s_save_pc_lo, s_save_pc_lo, 8             //pc[31:0]-8
+-	s_subb_u32 		s_save_pc_hi, s_save_pc_hi, 0x0			  // -scc
+-
+-L_NO_PC_REWIND:
+-    s_mov_b32       s_save_tmp, 0															//clear saveCtx bit
+-	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp		//clear saveCtx bit
+-
+-	s_mov_b32		s_save_xnack_mask_lo,	xnack_mask_lo									//save XNACK_MASK
+-	s_mov_b32		s_save_xnack_mask_hi,	xnack_mask_hi
+-	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE)					//save RCNT
+-	s_lshl_b32		s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT
+-	s_or_b32		s_save_pc_hi, s_save_pc_hi, s_save_tmp
+-	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE)	//save FIRST_REPLAY
+-	s_lshl_b32		s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
+-	s_or_b32		s_save_pc_hi, s_save_pc_hi, s_save_tmp
+-	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS)										//clear RCNT and FIRST_REPLAY in IB_STS
+-	s_and_b32		s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG
+-
+-	s_setreg_b32	hwreg(HW_REG_IB_STS), s_save_tmp
+-
+-	/*		inform SPI the readiness and wait for SPI's go signal */
+-	s_mov_b32		s_save_exec_lo,	exec_lo													//save EXEC and use EXEC for the go signal from SPI
+-	s_mov_b32		s_save_exec_hi,	exec_hi
+-	s_mov_b64		exec, 	0x0																//clear EXEC to get ready to receive
+-	if (EMU_RUN_HACK)
+-
+-	else
+-		s_sendmsg	sendmsg(MSG_SAVEWAVE)													//send SPI a message and wait for SPI's write to EXEC
+-	end
+-
+-  L_SLEEP:
+-	s_sleep 0x2
+-
+-	if (EMU_RUN_HACK)
+-
+-	else
+-		s_cbranch_execz	L_SLEEP
+-	end
+-
+-
+-	/*      setup Resource Contants    */
+-	if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE))
+-		//calculate wd_addr using absolute thread id
+-		v_readlane_b32 s_save_tmp, v9, 0
+-		s_lshr_b32 s_save_tmp, s_save_tmp, 6
+-		s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE
+-		s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO
+-		s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI
+-		s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL
+-	else
+-	end
+-	if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE))
+-		s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO
+-		s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI
+-		s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL
+-	else
+-	end
+-
+-
+-	s_mov_b32		s_save_buf_rsrc0, 	s_save_spi_init_lo														//base_addr_lo
+-	s_and_b32		s_save_buf_rsrc1, 	s_save_spi_init_hi, 0x0000FFFF											//base_addr_hi
+-	s_or_b32		s_save_buf_rsrc1, 	s_save_buf_rsrc1,  S_SAVE_BUF_RSRC_WORD1_STRIDE
+-    s_mov_b32       s_save_buf_rsrc2,   0                                               						//NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited
+-	s_mov_b32		s_save_buf_rsrc3, 	S_SAVE_BUF_RSRC_WORD3_MISC
+-	s_and_b32		s_save_tmp,         s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK
+-	s_lshr_b32		s_save_tmp,  		s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT)			//get ATC bit into position
+-	s_or_b32		s_save_buf_rsrc3, 	s_save_buf_rsrc3,  s_save_tmp											//or ATC TODO: ATC deprecated, no need anymore.
+-	s_and_b32		s_save_tmp,         s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK
+-	s_lshr_b32		s_save_tmp,  		s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT)		//get MTYPE bits into position
+-	s_or_b32		s_save_buf_rsrc3, 	s_save_buf_rsrc3,  s_save_tmp											//or MTYPE
+-
+-	s_mov_b32		s_save_m0,			m0																	//save M0
+-
+-	/* 		global mem offset			*/
+-	s_mov_b32		s_save_mem_offset, 	0x0																		//mem offset initial value = 0
+-
+-
+-	/*      the first wave in the threadgroup    */
+-	s_barrier																		//FIXME  not performance-optimal "LDS is used? wait for other waves in the same TG"
+-	s_and_b32		s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK								//exec is still used here
+-	s_cbranch_scc0	L_SAVE_VGPR
+-
+-	/*      	save LDS	    */
+-	//////////////////////////////
+-  L_SAVE_LDS:
+-
+-	s_mov_b32		exec_lo, 0xFFFFFFFF 											//need every thread from now on
+-	s_mov_b32		exec_hi, 0xFFFFFFFF
+-
+-	s_getreg_b32 	s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) 			//lds_size
+-	s_and_b32		s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF				//lds_size is zero?
+-	s_cbranch_scc0	L_SAVE_VGPR														//no lds used? jump to L_SAVE_VGPR
+-	s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 6 						//LDS size in dwords = lds_size * 64dw
+-	s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 2 						//LDS size in bytes
+-	s_mov_b32		s_save_buf_rsrc2,  s_save_alloc_size  							//NUM_RECORDS in bytes
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
+-	end
+-	s_mov_b32 		m0, 0x0 														//lds_offset initial value = 0
+-	s_nop           0x0                                                             //Manually inserted wait states
+-
+-  L_SAVE_LDS_LOOP:
+-	if (SAVE_LDS)
+-	buffer_store_lds_dword	s_save_buf_rsrc0, s_save_mem_offset lds:1
+-	end
+-	s_add_u32		m0, m0, 256															//every buffer_store_lds does 256 bytes
+-	s_add_u32		s_save_mem_offset, s_save_mem_offset, 256							//mem offset increased by 256 bytes
+-	s_cmp_lt_u32	m0, s_save_alloc_size												//scc=(m0 < s_save_alloc_size) ? 1 : 0
+-	s_cbranch_scc1  L_SAVE_LDS_LOOP														//LDS save is complete?
+-
+-
+-	/*      	save VGPRs	    */
+-	//////////////////////////////
+-  L_SAVE_VGPR:
+-
+- 	s_mov_b32		exec_lo, 0xFFFFFFFF 											//need every thread from now on
+-	s_mov_b32		exec_hi, 0xFFFFFFFF
+-
+-	s_getreg_b32 	s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 					//vpgr_size
+-	s_add_u32 		s_save_alloc_size, s_save_alloc_size, 1
+-	s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 2 						//Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)   //FIXME for GFX, zero is possible
+-	s_lshl_b32		s_save_buf_rsrc2,  s_save_alloc_size, 8							//NUM_RECORDS in bytes (64 threads*4)
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
+-	end
+-
+-    s_mov_b32 		m0, 0x0 														//VGPR initial index value =0
+-	s_set_gpr_idx_on  m0, 0x1														//M0[7:0] = M0[7:0] and M0[15:12] = 0x1
+-    s_add_u32		s_save_alloc_size, s_save_alloc_size, 0x1000					//add 0x1000 since we compare m0 against it later
+-
+-  L_SAVE_VGPR_LOOP:
+-	v_mov_b32 		v0, v0															//v0 = v[0+m0]
+-
+-    if(USE_MTBUF_INSTEAD_OF_MUBUF)
+-		tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-    else
+-		buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
+-	end
+-
+-    s_add_u32		m0, m0, 1														//next vgpr index
+-	s_add_u32		s_save_mem_offset, s_save_mem_offset, 256						//every buffer_store_dword does 256 bytes
+-	s_cmp_lt_u32 	m0,	s_save_alloc_size 											//scc = (m0 < s_save_alloc_size) ? 1 : 0
+-	s_cbranch_scc1 	L_SAVE_VGPR_LOOP												//VGPR save is complete?
+-	s_set_gpr_idx_off
+-
+-
+-    /*      	save ACC_VGPRs	    */
+-	//////////////////////////////
+-  L_SAVE_ACC_VGPR:
+-
+- 	s_mov_b32		exec_lo, 0xFFFFFFFF 											//need every thread from now on
+-	s_mov_b32		exec_hi, 0xFFFFFFFF
+-
+-	s_getreg_b32 	s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 					//vpgr_size
+-	s_add_u32 		s_save_alloc_size, s_save_alloc_size, 1
+-	s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 2 						//Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)   //FIXME for GFX, zero is possible
+-	s_lshl_b32		s_save_buf_rsrc2,  s_save_alloc_size, 8							//NUM_RECORDS in bytes (64 threads*4)
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
+-	end
+-
+-    s_mov_b32 		m0, 0x0 														//VGPR initial index value =0
+-	s_set_gpr_idx_on  m0, 0x1														//M0[7:0] = M0[7:0] and M0[15:12] = 0x1
+-    s_add_u32		s_save_alloc_size, s_save_alloc_size, 0x1000					//add 0x1000 since we compare m0 against it later
+-
+-  L_SAVE_ACC_VGPR_LOOP:
+-    v_accvgpr_read  v0, v0
+-	v_nop
+-    v_nop
+-    if(USE_MTBUF_INSTEAD_OF_MUBUF)
+-		tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-    else
+-		buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
+-	end
+-
+-    s_add_u32		m0, m0, 1														//next vgpr index
+-	s_add_u32		s_save_mem_offset, s_save_mem_offset, 256						//every buffer_store_dword does 256 bytes
+-	s_cmp_lt_u32 	m0,	s_save_alloc_size 											//scc = (m0 < s_save_alloc_size) ? 1 : 0
+-	s_cbranch_scc1 	L_SAVE_ACC_VGPR_LOOP												//VGPR save is complete?
+-	s_set_gpr_idx_off
+-
+-
+-	/*      	save SGPRs	    */
+-	//////////////////////////////
+-	s_getreg_b32 	s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) 				//spgr_size
+-	s_add_u32 		s_save_alloc_size, s_save_alloc_size, 1
+-	s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 4 						//Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value)
+-
+-	if (SGPR_SAVE_USE_SQC)
+-		s_lshl_b32		s_save_buf_rsrc2,	s_save_alloc_size, 2					//NUM_RECORDS in bytes
+-	else
+-		s_lshl_b32		s_save_buf_rsrc2,	s_save_alloc_size, 8					//NUM_RECORDS in bytes (64 threads)
+-	end
+-
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
+-	end
+-
+-	s_mov_b32 		m0, 0x0 														//SGPR initial index value =0
+-    s_nop           0x0                                                             //Manually inserted wait states
+-
+-  L_SAVE_SGPR_LOOP:
+-	s_movrels_b32 	s0, s0 															//s0 = s[0+m0]
+-	write_sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)							//PV: the best performance should be using s_buffer_store_dwordx4
+-	s_add_u32		m0, m0, 1														//next sgpr index
+-	s_cmp_lt_u32 	m0, s_save_alloc_size 											//scc = (m0 < s_save_alloc_size) ? 1 : 0
+-	s_cbranch_scc1 	L_SAVE_SGPR_LOOP												//SGPR save is complete?
+-
+-	/* 		save HW registers	*/
+-	//////////////////////////////
+-  L_SAVE_HWREG:
+-    s_mov_b32		s_save_buf_rsrc2, 0x4								//NUM_RECORDS	in bytes
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
+-	end
+-
+-
+-	write_sgpr_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)					//M0
+-
+-	if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME))
+-		s_add_u32 s_save_pc_lo, s_save_pc_lo, 4             //pc[31:0]+4
+-		s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0			//carry bit over
+-	end
+-
+-	write_sgpr_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)					//PC
+-	write_sgpr_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
+-	write_sgpr_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)				//EXEC
+-	write_sgpr_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
+-	write_sgpr_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)				//STATUS
+-
+-	//s_save_trapsts conflicts with s_save_alloc_size
+-	s_getreg_b32    s_save_trapsts, hwreg(HW_REG_TRAPSTS)
+-	write_sgpr_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)				//TRAPSTS
+-
+-	write_sgpr_to_mem(s_save_xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)			//XNACK_MASK_LO
+-	write_sgpr_to_mem(s_save_xnack_mask_hi, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)			//XNACK_MASK_HI
+-
+-	//use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2
+-	s_getreg_b32 	s_save_m0, hwreg(HW_REG_MODE)																						//MODE
+-	write_sgpr_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
+-
+-	/*     S_PGM_END_SAVED  */    							//FIXME  graphics ONLY
+-	if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT))
+-		s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff    //pc[47:32]
+-		s_add_u32 s_save_pc_lo, s_save_pc_lo, 4             //pc[31:0]+4
+-		s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0			//carry bit over
+-		s_rfe_b64 s_save_pc_lo                              //Return to the main shader program
+-	else
+-	end
+-
+-
+-    s_branch	L_END_PGM
+-
+-
+-
+-/**************************************************************************/
+-/*                     	restore routine						              */
+-/**************************************************************************/
+-
+-L_RESTORE:
+-    /*      Setup Resource Contants    */
+-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))
+-		//calculate wd_addr using absolute thread id
+-		v_readlane_b32 s_restore_tmp, v9, 0
+-		s_lshr_b32 s_restore_tmp, s_restore_tmp, 6
+-		s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE
+-		s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO
+-		s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI
+-		s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL
+-	else
+-	end
+-
+-    s_mov_b32		s_restore_buf_rsrc0, 	s_restore_spi_init_lo															//base_addr_lo
+-	s_and_b32		s_restore_buf_rsrc1, 	s_restore_spi_init_hi, 0x0000FFFF												//base_addr_hi
+-	s_or_b32		s_restore_buf_rsrc1, 	s_restore_buf_rsrc1,  S_RESTORE_BUF_RSRC_WORD1_STRIDE
+-    s_mov_b32       s_restore_buf_rsrc2,   	0                                               								//NUM_RECORDS initial value = 0 (in bytes)
+-	s_mov_b32		s_restore_buf_rsrc3, 	S_RESTORE_BUF_RSRC_WORD3_MISC
+-	s_and_b32		s_restore_tmp,         	s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK
+-	s_lshr_b32		s_restore_tmp,  		s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT)		//get ATC bit into position
+-	s_or_b32		s_restore_buf_rsrc3, 	s_restore_buf_rsrc3,  s_restore_tmp												//or ATC TODO: ATC deprecated, no need anymore.
+-	s_and_b32		s_restore_tmp,         	s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK
+-	s_lshr_b32		s_restore_tmp,  		s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT)	//get MTYPE bits into position
+-	s_or_b32		s_restore_buf_rsrc3, 	s_restore_buf_rsrc3,  s_restore_tmp												//or MTYPE
+-
+-	/* 		global mem offset			*/
+-	s_mov_b32		s_restore_mem_offset, 0x0								//mem offset initial value = 0
+-
+-	/*      the first wave in the threadgroup    */
+-	s_and_b32		s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK
+-	s_cbranch_scc0	L_RESTORE_VGPR
+-
+-    /*      	restore LDS	    */
+-	//////////////////////////////
+-  L_RESTORE_LDS:
+-
+-	s_mov_b32		exec_lo, 0xFFFFFFFF 													//need every thread from now on   //be consistent with SAVE although can be moved ahead
+-	s_mov_b32		exec_hi, 0xFFFFFFFF
+-
+-	s_getreg_b32 	s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) 				//lds_size
+-	s_and_b32		s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF					//lds_size is zero?
+-	s_cbranch_scc0	L_RESTORE_VGPR															//no lds used? jump to L_RESTORE_VGPR
+-	s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 6 							//LDS size in dwords = lds_size * 64dw
+-	s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 2 							//LDS size in bytes
+-	s_mov_b32		s_restore_buf_rsrc2,	s_restore_alloc_size							//NUM_RECORDS in bytes
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
+-	end
+-	s_mov_b32 		m0, 0x0 																//lds_offset initial value = 0
+-
+-  L_RESTORE_LDS_LOOP:
+-	if (SAVE_LDS)
+-	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1
+-	end
+-    s_add_u32		m0, m0, 256																//every buffer_load_dword does 256 bytes
+-	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 256							//mem offset increased by 256 bytes
+-	s_cmp_lt_u32	m0, s_restore_alloc_size												//scc=(m0 < s_restore_alloc_size) ? 1 : 0
+-	s_cbranch_scc1  L_RESTORE_LDS_LOOP														//LDS restore is complete?
+-
+-
+-    /*      	restore VGPRs	    */
+-	//////////////////////////////
+-  L_RESTORE_VGPR:
+-
+- 	s_mov_b32		exec_lo, 0xFFFFFFFF 													//need every thread from now on   //be consistent with SAVE although can be moved ahead
+-	s_mov_b32		exec_hi, 0xFFFFFFFF
+-
+-	s_getreg_b32 	s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 	//vpgr_size
+-	s_add_u32 		s_restore_alloc_size, s_restore_alloc_size, 1
+-	s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 2 							//Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)
+-    s_lshl_b32		s_restore_buf_rsrc2,  s_restore_alloc_size, 8						    //NUM_RECORDS in bytes (64 threads*4)
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
+-	end
+-	s_mov_b32		s_restore_mem_offset_save, s_restore_mem_offset							// restore start with v1, v0 will be the last
+-	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 256
+-    s_mov_b32 		m0, 1 																	//VGPR initial index value = 1
+-	s_set_gpr_idx_on  m0, 0x8																//M0[7:0] = M0[7:0] and M0[15:12] = 0x8
+-    s_add_u32		s_restore_alloc_size, s_restore_alloc_size, 0x8000						//add 0x8000 since we compare m0 against it later
+-
+-  L_RESTORE_VGPR_LOOP:
+-    if(USE_MTBUF_INSTEAD_OF_MUBUF)
+-		tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-    else
+-		buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset	slc:1 glc:1
+-	end
+-	s_waitcnt		vmcnt(0)																//ensure data ready
+-	v_mov_b32		v0, v0																	//v[0+m0] = v0
+-    s_add_u32		m0, m0, 1																//next vgpr index
+-	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 256							//every buffer_load_dword does 256 bytes
+-	s_cmp_lt_u32 	m0,	s_restore_alloc_size 												//scc = (m0 < s_restore_alloc_size) ? 1 : 0
+-	s_cbranch_scc1 	L_RESTORE_VGPR_LOOP														//VGPR restore (except v0) is complete?
+-	s_set_gpr_idx_off
+-
+-
+-    /*      	restore ACC_VGPRs	    */
+-	//////////////////////////////
+-  L_RESTORE_ACC_VGPR:
+-
+- 	s_mov_b32		exec_lo, 0xFFFFFFFF 													//need every thread from now on   //be consistent with SAVE although can be moved ahead
+-	s_mov_b32		exec_hi, 0xFFFFFFFF
+-
+-	s_getreg_b32 	s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 	//vpgr_size
+-	s_add_u32 		s_restore_alloc_size, s_restore_alloc_size, 1
+-	s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 2 							//Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)
+-    s_lshl_b32		s_restore_buf_rsrc2,  s_restore_alloc_size, 8						    //NUM_RECORDS in bytes (64 threads*4)
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
+-	end
+-    s_mov_b32 		m0, 0 																	//VGPR initial index value = 0
+-	s_set_gpr_idx_on  m0, 0x8																//M0[7:0] = M0[7:0] and M0[15:12] = 0x8
+-    s_add_u32		s_restore_alloc_size, s_restore_alloc_size, 0x8000						//add 0x8000 since we compare m0 against it later
+-
+-  L_RESTORE_ACC_VGPR_LOOP:
+-    if(USE_MTBUF_INSTEAD_OF_MUBUF)
+-		tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-    else
+-		buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset	slc:1 glc:1
+-	end
+-	s_waitcnt		vmcnt(0)																//ensure data ready
+-	v_accvgpr_write		v0, v0															//v[0+m0] = v0
+-    s_add_u32		m0, m0, 1																//next vgpr index
+-	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 256							//every buffer_load_dword does 256 bytes
+-	s_cmp_lt_u32 	m0,	s_restore_alloc_size 												//scc = (m0 < s_restore_alloc_size) ? 1 : 0
+-	s_cbranch_scc1 	L_RESTORE_ACC_VGPR_LOOP														//VGPR restore (except v0) is complete?
+-	s_set_gpr_idx_off
+-																							/* VGPR restore on v0 */
+-    if(USE_MTBUF_INSTEAD_OF_MUBUF)
+-		tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-    else
+-		buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save	slc:1 glc:1
+-	end
+-
+-    /*      	restore SGPRs	    */
+-	//////////////////////////////
+-	s_getreg_b32 	s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) 				//spgr_size
+-	s_add_u32 		s_restore_alloc_size, s_restore_alloc_size, 1
+-	s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 4 							//Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value)
+-
+-	if (SGPR_SAVE_USE_SQC)
+-		s_lshl_b32		s_restore_buf_rsrc2,	s_restore_alloc_size, 2						//NUM_RECORDS in bytes
+-	else
+-		s_lshl_b32		s_restore_buf_rsrc2,	s_restore_alloc_size, 8						//NUM_RECORDS in bytes (64 threads)
+-	end
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
+-	end
+-	read_sgpr_from_mem(s_restore_tmp, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)		//save s0 to s_restore_tmp
+-	s_mov_b32 		m0, 0x1																				//SGPR initial index value =1	//go on with with s1
+-
+-  L_RESTORE_SGPR_LOOP:
+-	read_sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)															//PV: further performance improvement can be made
+-	s_waitcnt		lgkmcnt(0)																//ensure data ready
+-	s_movreld_b32 	s0, s0 																	//s[0+m0] = s0
+-	s_nop 0 // hazard SALU M0=> S_MOVREL
+-    s_add_u32		m0, m0, 1																//next sgpr index
+-	s_cmp_lt_u32 	m0, s_restore_alloc_size 												//scc = (m0 < s_restore_alloc_size) ? 1 : 0
+-	s_cbranch_scc1 	L_RESTORE_SGPR_LOOP														//SGPR restore (except s0) is complete?
+-	s_mov_b32		s0, s_restore_tmp															/* SGPR restore on s0 */
+-
+-    /* 		restore HW registers	*/
+-	//////////////////////////////
+-  L_RESTORE_HWREG:
+-    s_mov_b32		s_restore_buf_rsrc2, 0x4												//NUM_RECORDS	in bytes
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
+-	end
+-
+-	read_sgpr_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//M0
+-	read_sgpr_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//PC
+-	read_sgpr_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)
+-	read_sgpr_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//EXEC
+-	read_sgpr_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)
+-	read_sgpr_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//STATUS
+-	read_sgpr_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//TRAPSTS
+-    read_sgpr_from_mem(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//XNACK_MASK_LO
+-	read_sgpr_from_mem(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//XNACK_MASK_HI
+-	read_sgpr_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//MODE
+-
+-	s_waitcnt		lgkmcnt(0)																						//from now on, it is safe to restore STATUS and IB_STS
+-
+-	s_mov_b32 s_restore_tmp, s_restore_pc_hi
+-	s_and_b32 s_restore_pc_hi, s_restore_tmp, 0x0000ffff    	//pc[47:32]        //Do it here in order not to affect STATUS
+-
+-	//for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise:
+-	if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))
+-		s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8            //pc[31:0]+8	  //two back-to-back s_trap are used (first for save and second for restore)
+-		s_addc_u32	s_restore_pc_hi, s_restore_pc_hi, 0x0		 //carry bit over
+-	end
+-	if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL))
+-		s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4            //pc[31:0]+4     // save is hack through s_trap but restore is normal
+-		s_addc_u32	s_restore_pc_hi, s_restore_pc_hi, 0x0		 //carry bit over
+-	end
+-
+-	s_mov_b32 		m0, 		s_restore_m0
+-	s_mov_b32 		exec_lo, 	s_restore_exec_lo
+-	s_mov_b32 		exec_hi, 	s_restore_exec_hi
+-
+-	s_and_b32		s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts
+-	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0
+-	s_and_b32		s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts
+-	s_lshr_b32		s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT
+-	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0
+-	//s_setreg_b32 	hwreg(HW_REG_TRAPSTS), 	s_restore_trapsts      //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore
+-	s_setreg_b32 	hwreg(HW_REG_MODE), 	s_restore_mode
+-	//reuse s_restore_m0 as a temp register
+-	s_and_b32		s_restore_m0, s_restore_tmp, S_SAVE_PC_HI_RCNT_MASK
+-	s_lshr_b32		s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT
+-	s_lshl_b32		s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT
+-	s_mov_b32		s_restore_mode, 0x0																				//IB_STS is zero
+-	s_or_b32		s_restore_mode, s_restore_mode, s_restore_m0
+-	s_and_b32		s_restore_m0, s_restore_tmp, S_SAVE_PC_HI_FIRST_REPLAY_MASK
+-	s_lshr_b32		s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
+-	s_lshl_b32		s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT
+-	s_or_b32		s_restore_mode, s_restore_mode, s_restore_m0
+-    s_and_b32       s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK
+-    s_lshr_b32		s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT
+-	s_setreg_b32 	hwreg(HW_REG_IB_STS), 	s_restore_mode
+-
+-	s_and_b64    exec, exec, exec  // Restore STATUS.EXECZ, not writable by s_setreg_b32
+-	s_and_b64    vcc, vcc, vcc  // Restore STATUS.VCCZ, not writable by s_setreg_b32
+-	s_setreg_b32 	hwreg(HW_REG_STATUS), 	s_restore_status
+-
+-	s_barrier													//barrier to ensure the readiness of LDS before access attemps from any other wave in the same TG //FIXME not performance-optimal at this time
+-
+-
+-//	s_rfe_b64 s_restore_pc_lo                              		//Return to the main shader program and resume execution
+-    s_rfe_restore_b64  s_restore_pc_lo, s_restore_m0            // s_restore_m0[0] is used to set STATUS.inst_atc
+-
+-
+-/**************************************************************************/
+-/*                     	the END								              */
+-/**************************************************************************/
+-L_END_PGM:
+-	s_endpgm
+-
+-end
+-
+-
+-/**************************************************************************/
+-/*                     	the helper functions							  */
+-/**************************************************************************/
+-
+-function write_sgpr_to_mem(s, s_rsrc, s_mem_offset, use_sqc, use_mtbuf)
+-	if (use_sqc)
+-		s_mov_b32 exec_lo, m0					//assuming exec_lo is not needed anymore from this point on
+-		s_mov_b32 m0, s_mem_offset
+-		s_buffer_store_dword s, s_rsrc, m0		glc:1
+-		s_add_u32		s_mem_offset, s_mem_offset, 4
+-		s_mov_b32	m0, exec_lo
+-	elsif (use_mtbuf)
+-		v_mov_b32	v0,	s
+-        tbuffer_store_format_x v0, v0, s_rsrc, s_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-		s_add_u32		s_mem_offset, s_mem_offset, 256
+-	else
+-		v_mov_b32	v0,	s
+-		buffer_store_dword	v0, v0, s_rsrc, s_mem_offset	slc:1 glc:1
+-		s_add_u32		s_mem_offset, s_mem_offset, 256
+-	end
+-end
+-
+-
+-
+-function read_sgpr_from_mem(s, s_rsrc, s_mem_offset, use_sqc)
+-	s_buffer_load_dword s, s_rsrc, s_mem_offset		glc:1
+-	if (use_sqc)
+-		s_add_u32		s_mem_offset, s_mem_offset, 4
+-	else
+-		s_add_u32		s_mem_offset, s_mem_offset, 256
+-	end
+-end
+-
+-
+-
+-
+-
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
+index 2800e9bba1f9..4d146bca0b05 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
+@@ -200,13 +200,15 @@ var s_restore_spi_init_lo		    =	exec_lo
+ var s_restore_spi_init_hi		    =	exec_hi
+ 
+ var s_restore_mem_offset	=   ttmp12
++var s_restore_accvgpr_offset	=   ttmp13
+ var s_restore_alloc_size	=   ttmp3
+ var s_restore_tmp		=   ttmp2
+ var s_restore_mem_offset_save	=   s_restore_tmp	//no conflict
++var s_restore_accvgpr_offset_save = ttmp7
+ 
+ var s_restore_m0	    =	s_restore_alloc_size	//no conflict
+ 
+-var s_restore_mode	    =	ttmp7
++var s_restore_mode	    =	s_restore_accvgpr_offset_save
+ 
+ var s_restore_pc_lo	    =	ttmp0
+ var s_restore_pc_hi	    =	ttmp1
+@@ -229,7 +231,7 @@ var s_restore_ttmps_hi	    =	s_restore_alloc_size	//no conflict
+ /* Shader Main*/
+ 
+ shader main
+-  asic(GFX9)
++  asic(DEFAULT)
+   type(CS)
+ 
+ 
+@@ -840,10 +842,48 @@ end
+ 
+ L_SAVE_VGPR_END:
+ 
++if ASIC_TARGET_ARCTURUS
++    // Save ACC VGPRs
++    s_mov_b32 m0, 0x0 //VGPR initial index value =0
++    s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1
+ 
++if SAVE_AFTER_XNACK_ERROR
++    check_if_tcp_store_ok()
++    s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP
++
++L_SAVE_ACCVGPR_LOOP_SQC:
++    for var vgpr = 0; vgpr < 4; ++ vgpr
++        v_accvgpr_read v[vgpr], acc[vgpr]  // v[N] = acc[N+m0]
++    end
+ 
++    write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset)
+ 
++    s_add_u32 m0, m0, 4
++    s_cmp_lt_u32 m0, s_save_alloc_size
++    s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP_SQC
+ 
++    s_set_gpr_idx_off
++    s_branch L_SAVE_ACCVGPR_END
++end
++
++L_SAVE_ACCVGPR_LOOP:
++    for var vgpr = 0; vgpr < 4; ++ vgpr
++        v_accvgpr_read v[vgpr], acc[vgpr]  // v[N] = acc[N+m0]
++    end
++
++    buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
++    buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256
++    buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2
++    buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
++
++    s_add_u32 m0, m0, 4
++    s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4
++    s_cmp_lt_u32 m0, s_save_alloc_size
++    s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP
++    s_set_gpr_idx_off
++
++L_SAVE_ACCVGPR_END:
++end
+ 
+     /*	   S_PGM_END_SAVED  */				    //FIXME  graphics ONLY
+     if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT))
+@@ -970,6 +1010,11 @@ end
+     s_add_u32	    s_restore_alloc_size, s_restore_alloc_size, 1
+     s_lshl_b32	    s_restore_alloc_size, s_restore_alloc_size, 2			    //Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)
+     s_lshl_b32	    s_restore_buf_rsrc2,  s_restore_alloc_size, 8			    //NUM_RECORDS in bytes (64 threads*4)
++
++if ASIC_TARGET_ARCTURUS
++    s_mov_b32	    s_restore_accvgpr_offset, s_restore_buf_rsrc2                           //ACC VGPRs at end of VGPRs
++end
++
+     if (SWIZZLE_EN)
+ 	s_add_u32	s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0			    //FIXME need to use swizzle to enable bounds checking?
+     else
+@@ -1007,6 +1052,10 @@ else
+     // VGPR load using dw burst
+     s_mov_b32	    s_restore_mem_offset_save, s_restore_mem_offset	// restore start with v1, v0 will be the last
+     s_add_u32	    s_restore_mem_offset, s_restore_mem_offset, 256*4
++if ASIC_TARGET_ARCTURUS
++    s_mov_b32	    s_restore_accvgpr_offset_save, s_restore_accvgpr_offset
++    s_add_u32	    s_restore_accvgpr_offset, s_restore_accvgpr_offset, 256*4
++end
+     s_mov_b32	    m0, 4				//VGPR initial index value = 1
+     s_set_gpr_idx_on  m0, 0x8			    //M0[7:0] = M0[7:0] and M0[15:12] = 0x8
+     s_add_u32	    s_restore_alloc_size, s_restore_alloc_size, 0x8000			    //add 0x8000 since we compare m0 against it later
+@@ -1015,6 +1064,20 @@ else
+     if(USE_MTBUF_INSTEAD_OF_MUBUF)
+ 	tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+     else
++
++if ASIC_TARGET_ARCTURUS
++	buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1
++	buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1 offset:256
++	buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1 offset:256*2
++	buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1 offset:256*3
++	s_add_u32 s_restore_accvgpr_offset, s_restore_accvgpr_offset, 256*4
++	s_waitcnt vmcnt(0)
++
++	for var vgpr = 0; vgpr < 4; ++ vgpr
++		v_accvgpr_write acc[vgpr], v[vgpr]
++	end
++end
++
+ 	buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
+ 	buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256
+ 	buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2
+@@ -1031,6 +1094,18 @@ else
+     s_cbranch_scc1  L_RESTORE_VGPR_LOOP							    //VGPR restore (except v0) is complete?
+     s_set_gpr_idx_off
+ 											    /* VGPR restore on v0 */
++if ASIC_TARGET_ARCTURUS
++	buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1
++	buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1 offset:256
++	buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1 offset:256*2
++	buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1 offset:256*3
++	s_waitcnt vmcnt(0)
++
++	for var vgpr = 0; vgpr < 4; ++ vgpr
++		v_accvgpr_write acc[vgpr], v[vgpr]
++	end
++end
++
+     if(USE_MTBUF_INSTEAD_OF_MUBUF)
+ 	tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+     else
+@@ -1283,6 +1358,10 @@ function get_vgpr_size_bytes(s_vgpr_size_byte)
+     s_getreg_b32   s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE)	 //vpgr_size
+     s_add_u32	   s_vgpr_size_byte, s_vgpr_size_byte, 1
+     s_lshl_b32	   s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4	(non-zero value)   //FIXME for GFX, zero is possible
++
++if ASIC_TARGET_ARCTURUS
++    s_lshl_b32     s_vgpr_size_byte, s_vgpr_size_byte, 1  // Double size for ACC VGPRs
++end
+ end
+ 
+ function get_sgpr_size_bytes(s_sgpr_size_byte)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2982-drm-amdgpu-enable-all-8-sdma-instances-for-Arcturus-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2982-drm-amdgpu-enable-all-8-sdma-instances-for-Arcturus-.patch
new file mode 100644
index 00000000..2dbdb1b2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2982-drm-amdgpu-enable-all-8-sdma-instances-for-Arcturus-.patch
@@ -0,0 +1,33 @@
+From 969eb5140d4f2432e6e5ffe741f9793c98faa0cb Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Tue, 2 Jul 2019 11:15:37 +0800
+Subject: [PATCH 2982/4256] drm/amdgpu: enable all 8 sdma instances for
+ Arcturus silicon
+
+The more 6 sdma instances work fine now with DF fix in vbios:
+  * mmDF_PIE_AON_MiscClientsEnable(0x1c728)=0x3fe(DF_ALL_INSTANCE)
+       [9:4]MmhubsEnable=3f (change from 0)
+
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 9c7a3eb9a9a0..48d4597ef9f6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1601,7 +1601,7 @@ static int sdma_v4_0_early_init(void *handle)
+ 	if (adev->asic_type == CHIP_RAVEN)
+ 		adev->sdma.num_instances = 1;
+ 	else if (adev->asic_type == CHIP_ARCTURUS)
+-		adev->sdma.num_instances = 2;
++		adev->sdma.num_instances = 8;
+ 	else
+ 		adev->sdma.num_instances = 2;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2983-drm-amdkfd-Increase-vcrat-size-for-GPU.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2983-drm-amdkfd-Increase-vcrat-size-for-GPU.patch
new file mode 100644
index 00000000..b1389ad2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2983-drm-amdkfd-Increase-vcrat-size-for-GPU.patch
@@ -0,0 +1,32 @@
+From bc8f30d470d27c13c6b5c22b5756836d403bb4c4 Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Tue, 2 Jul 2019 22:01:59 -0500
+Subject: [PATCH 2983/4256] drm/amdkfd: Increase vcrat size for GPU
+
+GPU cache info (part of virtual CRAT) size depends on CU number.
+For arcturus, CU number has been increased from 64 to 128. So
+the required memory for vcrat also increases.
+
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+index e882f6d25043..a59253a31caf 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+@@ -790,7 +790,7 @@ int kfd_create_crat_image_acpi(void **crat_image, size_t *size)
+  * is put in the code to ensure we don't overwrite.
+  */
+ #define VCRAT_SIZE_FOR_CPU	(2 * PAGE_SIZE)
+-#define VCRAT_SIZE_FOR_GPU	(3 * PAGE_SIZE)
++#define VCRAT_SIZE_FOR_GPU	(4 * PAGE_SIZE)
+ 
+ /* kfd_fill_cu_for_cpu - Fill in Compute info for the given CPU NUMA node
+  *
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2984-drm-amdgpu-add-all-VCN-rings-into-schedule-request-q.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2984-drm-amdgpu-add-all-VCN-rings-into-schedule-request-q.patch
new file mode 100644
index 00000000..3ca33aae
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2984-drm-amdgpu-add-all-VCN-rings-into-schedule-request-q.patch
@@ -0,0 +1,75 @@
+From 5a41081028038e1bd226e650652e47144c392df4 Mon Sep 17 00:00:00 2001
+From: James Zhu <James.Zhu@amd.com>
+Date: Mon, 1 Jul 2019 19:12:14 -0400
+Subject: [PATCH 2984/4256] drm/amdgpu:add all VCN rings into schedule request
+ queue
+
+Add all VCN instances' decode/encode/jpeg decode rings into
+drm_sched_rq list.
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Reviewed-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 26 +++++++++++++++++--------
+ 1 file changed, 18 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+index 4f7f8ca1986d..54b9b955f12f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+@@ -75,7 +75,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
+ 			   struct amdgpu_ctx *ctx)
+ {
+ 	unsigned num_entities = amdgput_ctx_total_num_entities();
+-	unsigned i, j;
++	unsigned i, j, k;
+ 	int r;
+ 
+ 	if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
+@@ -126,7 +126,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
+ 	for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
+ 		struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
+ 		struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
+-		unsigned num_rings;
++		unsigned num_rings = 0;
+ 		unsigned num_rqs = 0;
+ 
+ 		switch (i) {
+@@ -157,16 +157,26 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
+ 			num_rings = 1;
+ 			break;
+ 		case AMDGPU_HW_IP_VCN_DEC:
+-			rings[0] = &adev->vcn.inst[0].ring_dec;
+-			num_rings = 1;
++			for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
++				if (adev->vcn.harvest_config & (1 << j))
++					continue;
++				rings[num_rings++] = &adev->vcn.inst[j].ring_dec;
++			}
+ 			break;
+ 		case AMDGPU_HW_IP_VCN_ENC:
+-			rings[0] = &adev->vcn.inst[0].ring_enc[0];
+-			num_rings = 1;
++			for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
++				if (adev->vcn.harvest_config & (1 << j))
++					continue;
++				for (k = 0; k < adev->vcn.num_enc_rings; ++k)
++					rings[num_rings++] = &adev->vcn.inst[j].ring_enc[k];
++			}
+ 			break;
+ 		case AMDGPU_HW_IP_VCN_JPEG:
+-			rings[0] = &adev->vcn.inst[0].ring_jpeg;
+-			num_rings = 1;
++			for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
++				if (adev->vcn.harvest_config & (1 << j))
++					continue;
++				rings[num_rings++] = &adev->vcn.inst[j].ring_jpeg;
++			}
+ 			break;
+ 		}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2985-drm-amdgpu-drop-unused-function-definitions.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2985-drm-amdgpu-drop-unused-function-definitions.patch
new file mode 100644
index 00000000..71b57249
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2985-drm-amdgpu-drop-unused-function-definitions.patch
@@ -0,0 +1,40 @@
+From 7d302eb044cf1aa286cbbf4a0bf0afd1319cdba1 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 11 Jul 2019 22:10:31 -0500
+Subject: [PATCH 2985/4256] drm/amdgpu: drop unused function definitions
+
+These were dropped and the headers never got cleaned up.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h | 14 --------------
+ 1 file changed, 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
+index b79d2a629768..26d8879bff9d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
+@@ -55,20 +55,6 @@ uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd,
+ 					unsigned int watch_point_id,
+ 					unsigned int reg_offset);
+ 
+-uint32_t kgd_gfx_v9_enable_debug_trap(struct kgd_dev *kgd,
+-				uint32_t trap_debug_wave_launch_mode,
+-				uint32_t vmid);
+-uint32_t kgd_gfx_v9_disable_debug_trap(struct kgd_dev *kgd);
+-uint32_t kgd_gfx_v9_set_debug_trap_data(struct kgd_dev *kgd,
+-					int trap_data0,
+-					int trap_data1);
+-uint32_t kgd_gfx_v9_set_wave_launch_trap_override(struct kgd_dev *kgd,
+-						uint32_t trap_override,
+-						uint32_t trap_mask);
+-uint32_t kgd_gfx_v9_set_wave_launch_mode(struct kgd_dev *kgd,
+-					uint8_t wave_launch_mode,
+-					uint32_t vmid);
+-
+ bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
+ 		uint8_t vmid);
+ uint16_t kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2986-drm-amdgpu-Fix-silent-amdgpu_bo_move-failures.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2986-drm-amdgpu-Fix-silent-amdgpu_bo_move-failures.patch
new file mode 100644
index 00000000..0b721785
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2986-drm-amdgpu-Fix-silent-amdgpu_bo_move-failures.patch
@@ -0,0 +1,110 @@
+From 43d07f6ba6b19edcb8fed98769bd057e3ba0a17b Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Sat, 13 Jul 2019 02:27:34 -0400
+Subject: [PATCH 2986/4256] drm/amdgpu: Fix silent amdgpu_bo_move failures
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Under memory pressure, buffer moves between RAM to VRAM  can
+fail when there is no GTT space available. In those cases
+amdgpu_bo_move falls back to ttm_bo_move_memcpy, which seems to
+succeed, although it doesn't really support non-contiguous or
+invisible VRAM. This manifests as VM faults with corrupted page
+table entries in KFD eviction stress tests.
+
+Print some helpful messages when lack of GTT space is causing buffer
+moves to fail. Check that source and destination memory regions are
+supported by ttm_bo_move_memcpy before taking that fallback.
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 40 +++++++++++++++++++++++--
+ 1 file changed, 37 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 12487f99e367..ff0ab1521cde 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -600,6 +600,7 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
+ 	placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
+ 	r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
+ 	if (unlikely(r)) {
++		pr_err("Failed to find GTT space for blit from VRAM\n");
+ 		return r;
+ 	}
+ 
+@@ -658,6 +659,7 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
+ 	placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
+ 	r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
+ 	if (unlikely(r)) {
++		pr_err("Failed to find GTT space for blit to VRAM\n");
+ 		return r;
+ 	}
+ 
+@@ -677,6 +679,30 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
+ 	return r;
+ }
+ 
++/**
++ * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
++ *
++ * Called by amdgpu_bo_move()
++ */
++static bool amdgpu_mem_visible(struct amdgpu_device *adev,
++			       struct ttm_mem_reg *mem)
++{
++	struct drm_mm_node *nodes = mem->mm_node;
++
++	if (mem->mem_type == TTM_PL_SYSTEM ||
++	    mem->mem_type == TTM_PL_TT)
++		return true;
++	if (mem->mem_type != TTM_PL_VRAM)
++		return false;
++
++	/* ttm_mem_reg_ioremap only supports contiguous memory */
++	if (nodes->size != mem->num_pages)
++		return false;
++
++	return ((nodes->start + nodes->size) << PAGE_SHIFT)
++		<= adev->gmc.visible_vram_size;
++}
++
+ /**
+  * amdgpu_bo_move - Move a buffer object to a new memory location
+  *
+@@ -725,8 +751,10 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
+ 		return 0;
+ 	}
+ 
+-	if (!adev->mman.buffer_funcs_enabled)
++	if (!adev->mman.buffer_funcs_enabled) {
++		r = -ENODEV;
+ 		goto memcpy;
++	}
+ 
+ 	if (old_mem->mem_type == TTM_PL_VRAM &&
+ 	    new_mem->mem_type == TTM_PL_SYSTEM) {
+@@ -741,10 +769,16 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
+ 
+ 	if (r) {
+ memcpy:
+-		r = ttm_bo_move_memcpy(bo, ctx, new_mem);
+-		if (r) {
++		/* Check that all memory is CPU accessible */
++		if (!amdgpu_mem_visible(adev, old_mem) ||
++		    !amdgpu_mem_visible(adev, new_mem)) {
++			pr_err("Move buffer fallback to memcpy unavailable\n");
+ 			return r;
+ 		}
++
++		r = ttm_bo_move_memcpy(bo, ctx, new_mem);
++		if (r)
++			return r;
+ 	}
+ 
+ 	if (bo->type == ttm_bo_type_device &&
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2987-drm-amd-powerplay-fix-memory-allocation-failure-chec.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2987-drm-amd-powerplay-fix-memory-allocation-failure-chec.patch
new file mode 100644
index 00000000..c4ee4572
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2987-drm-amd-powerplay-fix-memory-allocation-failure-chec.patch
@@ -0,0 +1,42 @@
+From 44b3ce5e8b9a3b2e64892f70cbe8cb3a623f0b21 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 12 Jul 2019 10:07:31 +0800
+Subject: [PATCH 2987/4256] drm/amd/powerplay: fix memory allocation failure
+ check V2
+
+Fix memory allocation failure check.
+
+- V2: fix one more similar error
+
+Change-Id: I012b082a7a2b92973a76db8029897fb4a3441694
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 2a299f708cd7..fd4f2d585bd6 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -319,7 +319,7 @@ static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
+ 	               AMDGPU_GEM_DOMAIN_VRAM);
+ 
+ 	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
+-	if (smu_table->metrics_table)
++	if (!smu_table->metrics_table)
+ 		return -ENOMEM;
+ 	smu_table->metrics_time = 0;
+ 
+@@ -1502,7 +1502,7 @@ static int vega20_set_default_od8_setttings(struct smu_context *smu)
+ 
+ 	od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL);
+ 
+-	if (od8_settings)
++	if (!od8_settings)
+ 		return -ENOMEM;
+ 
+ 	smu->od_settings = (void *)od8_settings;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2988-drm-amd-powerplay-avoid-access-before-allocation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2988-drm-amd-powerplay-avoid-access-before-allocation.patch
new file mode 100644
index 00000000..d780c043
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2988-drm-amd-powerplay-avoid-access-before-allocation.patch
@@ -0,0 +1,53 @@
+From 7d979ebd0b42fb1368b6327bd13e673ed7590ed6 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 12 Jul 2019 10:32:02 +0800
+Subject: [PATCH 2988/4256] drm/amd/powerplay: avoid access before allocation
+
+No access before allocation.
+
+Change-Id: Ia1d78786f2400cd1cd227d1ab6ea4c6a71619e4c
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index fd4f2d585bd6..7e8083b24012 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -441,7 +441,6 @@ static int vega20_store_powerplay_table(struct smu_context *smu)
+ {
+ 	ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
+ 	struct smu_table_context *table_context = &smu->smu_table;
+-	int ret;
+ 
+ 	if (!table_context->power_play_table)
+ 		return -EINVAL;
+@@ -455,9 +454,7 @@ static int vega20_store_powerplay_table(struct smu_context *smu)
+ 	table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
+ 	table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
+ 
+-	ret = vega20_setup_od8_information(smu);
+-
+-	return ret;
++	return 0;
+ }
+ 
+ static int vega20_append_powerplay_table(struct smu_context *smu)
+@@ -1507,6 +1504,12 @@ static int vega20_set_default_od8_setttings(struct smu_context *smu)
+ 
+ 	smu->od_settings = (void *)od8_settings;
+ 
++	ret = vega20_setup_od8_information(smu);
++	if (ret) {
++		pr_err("Retrieve board OD limits failed!\n");
++		return ret;
++	}
++
+ 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+ 		if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
+ 		    od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2989-drm-amd-powerplay-fix-deadlock-around-smu_handle_tas.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2989-drm-amd-powerplay-fix-deadlock-around-smu_handle_tas.patch
new file mode 100644
index 00000000..78836d6d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2989-drm-amd-powerplay-fix-deadlock-around-smu_handle_tas.patch
@@ -0,0 +1,38 @@
+From c21b51a8e22364794dffcc81c4269f041504f93b Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 12 Jul 2019 13:18:16 +0800
+Subject: [PATCH 2989/4256] drm/amd/powerplay: fix deadlock around
+ smu_handle_task V2
+
+As the lock was already held on the entrance to smu_handle_task.
+
+- V2: lock in small granularity
+
+Change-Id: I5388aa917ef0e330974e26c59db42d1354b6a865
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index ba3198399cc9..09b4b0dc94ab 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -2994,13 +2994,10 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
+ 	}
+ 
+ 	if (is_support_sw_smu(adev)) {
+-		struct smu_context *smu = &adev->smu;
+ 		struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
+-		mutex_lock(&(smu->mutex));
+ 		smu_handle_task(&adev->smu,
+ 				smu_dpm->dpm_level,
+ 				AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
+-		mutex_unlock(&(smu->mutex));
+ 	} else {
+ 		if (adev->powerplay.pp_funcs->dispatch_tasks) {
+ 			if (!amdgpu_device_has_dc_support(adev)) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2990-drm-amd-powerplay-correct-SW-SMU-valid-mapping-check.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2990-drm-amd-powerplay-correct-SW-SMU-valid-mapping-check.patch
new file mode 100644
index 00000000..625e0ca0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2990-drm-amd-powerplay-correct-SW-SMU-valid-mapping-check.patch
@@ -0,0 +1,451 @@
+From ea64e73f1cf835bb8a1b95d2fc89d0de6b5ad37b Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 11 Jul 2019 10:23:17 +0800
+Subject: [PATCH 2990/4256] drm/amd/powerplay: correct SW SMU valid mapping
+ check
+
+Current implementation is not actually able to detect
+invalid message/table/workload mapping.
+
+Change-Id: I66588f20dc2c39dfeb8aefb66757812589eab812
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ .../gpu/drm/amd/include/kgd_pp_interface.h    |  1 +
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  | 14 ++--
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 15 ++--
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 68 +++++++++++--------
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 67 ++++++++++--------
+ 5 files changed, 94 insertions(+), 71 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+index 9f661bf96ed0..9733bbf9bc72 100644
+--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
++++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+@@ -141,6 +141,7 @@ enum PP_SMC_POWER_PROFILE {
+ 	PP_SMC_POWER_PROFILE_VR           = 0x4,
+ 	PP_SMC_POWER_PROFILE_COMPUTE      = 0x5,
+ 	PP_SMC_POWER_PROFILE_CUSTOM       = 0x6,
++	PP_SMC_POWER_PROFILE_COUNT,
+ };
+ 
+ enum {
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 534e450df4bb..7d680f33ce3c 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -37,9 +37,9 @@
+ #include "nbio/nbio_7_4_sh_mask.h"
+ 
+ #define MSG_MAP(msg, index) \
+-	[SMU_MSG_##msg] = index
++	[SMU_MSG_##msg] = {1, (index)}
+ 
+-static int arcturus_message_map[SMU_MSG_MAX_COUNT] = {
++static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
+ 	MSG_MAP(TestMessage,			     PPSMC_MSG_TestMessage),
+ 	MSG_MAP(GetSmuVersion,			     PPSMC_MSG_GetSmuVersion),
+ 	MSG_MAP(GetDriverIfVersion,		     PPSMC_MSG_GetDriverIfVersion),
+@@ -101,16 +101,18 @@ static int arcturus_message_map[SMU_MSG_MAX_COUNT] = {
+ 
+ static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+ {
+-	int val;
++	struct smu_11_0_cmn2aisc_mapping mapping;
+ 
+ 	if (index >= SMU_MSG_MAX_COUNT)
+ 		return -EINVAL;
+ 
+-	val = arcturus_message_map[index];
+-	if (val > PPSMC_Message_Count)
++	mapping = arcturus_message_map[index];
++	if (!(mapping.valid_mapping)) {
++		pr_warn("Unsupported SMU message: %d\n", index);
+ 		return -EINVAL;
++	}
+ 
+-	return val;
++	return mapping.map_to;
+ }
+ 
+ static const struct pptable_funcs arcturus_ppt_funcs = {
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 2fff4b16cb4e..fcb58012170f 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -43,19 +43,24 @@
+ #define SMU11_TOOL_SIZE			0x19000
+ 
+ #define CLK_MAP(clk, index) \
+-	[SMU_##clk] = index
++	[SMU_##clk] = {1, (index)}
+ 
+ #define FEA_MAP(fea) \
+-	[SMU_FEATURE_##fea##_BIT] = FEATURE_##fea##_BIT
++	[SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}
+ 
+ #define TAB_MAP(tab) \
+-	[SMU_TABLE_##tab] = TABLE_##tab
++	[SMU_TABLE_##tab] = {1, TABLE_##tab}
+ 
+ #define PWR_MAP(tab) \
+-	[SMU_POWER_SOURCE_##tab] = POWER_SOURCE_##tab
++	[SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}
+ 
+ #define WORKLOAD_MAP(profile, workload) \
+-	[profile] = workload
++	[profile] = {1, (workload)}
++
++struct smu_11_0_cmn2aisc_mapping {
++	int	valid_mapping;
++	int	map_to;
++};
+ 
+ struct smu_11_0_max_sustainable_clocks {
+ 	uint32_t display_clock;
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index fa636d2b9eae..102310461119 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -49,9 +49,9 @@
+ 	FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
+ 
+ #define MSG_MAP(msg, index) \
+-	[SMU_MSG_##msg] = index
++	[SMU_MSG_##msg] = {1, (index)}
+ 
+-static int navi10_message_map[SMU_MSG_MAX_COUNT] = {
++static struct smu_11_0_cmn2aisc_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
+ 	MSG_MAP(TestMessage,			PPSMC_MSG_TestMessage),
+ 	MSG_MAP(GetSmuVersion,			PPSMC_MSG_GetSmuVersion),
+ 	MSG_MAP(GetDriverIfVersion,		PPSMC_MSG_GetDriverIfVersion),
+@@ -118,7 +118,7 @@ static int navi10_message_map[SMU_MSG_MAX_COUNT] = {
+ 	MSG_MAP(ArmD3,			PPSMC_MSG_ArmD3),
+ };
+ 
+-static int navi10_clk_map[SMU_CLK_COUNT] = {
++static struct smu_11_0_cmn2aisc_mapping navi10_clk_map[SMU_CLK_COUNT] = {
+ 	CLK_MAP(GFXCLK, PPCLK_GFXCLK),
+ 	CLK_MAP(SCLK,	PPCLK_GFXCLK),
+ 	CLK_MAP(SOCCLK, PPCLK_SOCCLK),
+@@ -133,7 +133,7 @@ static int navi10_clk_map[SMU_CLK_COUNT] = {
+ 	CLK_MAP(PHYCLK, PPCLK_PHYCLK),
+ };
+ 
+-static int navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
++static struct smu_11_0_cmn2aisc_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
+ 	FEA_MAP(DPM_PREFETCHER),
+ 	FEA_MAP(DPM_GFXCLK),
+ 	FEA_MAP(DPM_GFX_PACE),
+@@ -178,7 +178,7 @@ static int navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
+ 	FEA_MAP(ATHUB_PG),
+ };
+ 
+-static int navi10_table_map[SMU_TABLE_COUNT] = {
++static struct smu_11_0_cmn2aisc_mapping navi10_table_map[SMU_TABLE_COUNT] = {
+ 	TAB_MAP(PPTABLE),
+ 	TAB_MAP(WATERMARKS),
+ 	TAB_MAP(AVFS),
+@@ -193,12 +193,12 @@ static int navi10_table_map[SMU_TABLE_COUNT] = {
+ 	TAB_MAP(PACE),
+ };
+ 
+-static int navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
++static struct smu_11_0_cmn2aisc_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
+ 	PWR_MAP(AC),
+ 	PWR_MAP(DC),
+ };
+ 
+-static int navi10_workload_map[] = {
++static struct smu_11_0_cmn2aisc_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
+ 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,	WORKLOAD_PPLIB_DEFAULT_BIT),
+ 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,		WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
+ 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,		WORKLOAD_PPLIB_POWER_SAVING_BIT),
+@@ -210,79 +210,87 @@ static int navi10_workload_map[] = {
+ 
+ static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+ {
+-	int val;
++	struct smu_11_0_cmn2aisc_mapping mapping;
++
+ 	if (index > SMU_MSG_MAX_COUNT)
+ 		return -EINVAL;
+ 
+-	val = navi10_message_map[index];
+-	if (val > PPSMC_Message_Count)
++	mapping = navi10_message_map[index];
++	if (!(mapping.valid_mapping))
+ 		return -EINVAL;
+ 
+-	return val;
++	return mapping.map_to;
+ }
+ 
+ static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
+ {
+-	int val;
++	struct smu_11_0_cmn2aisc_mapping mapping;
++
+ 	if (index >= SMU_CLK_COUNT)
+ 		return -EINVAL;
+ 
+-	val = navi10_clk_map[index];
+-	if (val >= PPCLK_COUNT)
++	mapping = navi10_clk_map[index];
++	if (!(mapping.valid_mapping))
+ 		return -EINVAL;
+ 
+-	return val;
++	return mapping.map_to;
+ }
+ 
+ static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
+ {
+-	int val;
++	struct smu_11_0_cmn2aisc_mapping mapping;
++
+ 	if (index >= SMU_FEATURE_COUNT)
+ 		return -EINVAL;
+ 
+-	val = navi10_feature_mask_map[index];
+-	if (val > 64)
++	mapping = navi10_feature_mask_map[index];
++	if (!(mapping.valid_mapping))
+ 		return -EINVAL;
+ 
+-	return val;
++	return mapping.map_to;
+ }
+ 
+ static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
+ {
+-	int val;
++	struct smu_11_0_cmn2aisc_mapping mapping;
++
+ 	if (index >= SMU_TABLE_COUNT)
+ 		return -EINVAL;
+ 
+-	val = navi10_table_map[index];
+-	if (val >= TABLE_COUNT)
++	mapping = navi10_table_map[index];
++	if (!(mapping.valid_mapping))
+ 		return -EINVAL;
+ 
+-	return val;
++	return mapping.map_to;
+ }
+ 
+ static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
+ {
+-	int val;
++	struct smu_11_0_cmn2aisc_mapping mapping;
++
+ 	if (index >= SMU_POWER_SOURCE_COUNT)
+ 		return -EINVAL;
+ 
+-	val = navi10_pwr_src_map[index];
+-	if (val >= POWER_SOURCE_COUNT)
++	mapping = navi10_pwr_src_map[index];
++	if (!(mapping.valid_mapping))
+ 		return -EINVAL;
+ 
+-	return val;
++	return mapping.map_to;
+ }
+ 
+ 
+ static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
+ {
+-	int val;
++	struct smu_11_0_cmn2aisc_mapping mapping;
++
+ 	if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
+ 		return -EINVAL;
+ 
+-	val = navi10_workload_map[profile];
++	mapping = navi10_workload_map[profile];
++	if (!(mapping.valid_mapping))
++		return -EINVAL;
+ 
+-	return val;
++	return mapping.map_to;
+ }
+ 
+ static bool is_asic_secure(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 7e8083b24012..52ea26e328c3 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -47,7 +47,7 @@
+ #define CTF_OFFSET_HBM			5
+ 
+ #define MSG_MAP(msg) \
+-	[SMU_MSG_##msg] = PPSMC_MSG_##msg
++	[SMU_MSG_##msg] = {1, PPSMC_MSG_##msg}
+ 
+ #define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
+ 			 FEATURE_DPM_GFXCLK_MASK | \
+@@ -59,7 +59,7 @@
+ 			 FEATURE_DPM_LINK_MASK | \
+ 			 FEATURE_DPM_DCEFCLK_MASK)
+ 
+-static int vega20_message_map[SMU_MSG_MAX_COUNT] = {
++static struct smu_11_0_cmn2aisc_mapping vega20_message_map[SMU_MSG_MAX_COUNT] = {
+ 	MSG_MAP(TestMessage),
+ 	MSG_MAP(GetSmuVersion),
+ 	MSG_MAP(GetDriverIfVersion),
+@@ -145,7 +145,7 @@ static int vega20_message_map[SMU_MSG_MAX_COUNT] = {
+ 	MSG_MAP(GetAVFSVoltageByDpm),
+ };
+ 
+-static int vega20_clk_map[SMU_CLK_COUNT] = {
++static struct smu_11_0_cmn2aisc_mapping vega20_clk_map[SMU_CLK_COUNT] = {
+ 	CLK_MAP(GFXCLK, PPCLK_GFXCLK),
+ 	CLK_MAP(VCLK, PPCLK_VCLK),
+ 	CLK_MAP(DCLK, PPCLK_DCLK),
+@@ -159,7 +159,7 @@ static int vega20_clk_map[SMU_CLK_COUNT] = {
+ 	CLK_MAP(FCLK, PPCLK_FCLK),
+ };
+ 
+-static int vega20_feature_mask_map[SMU_FEATURE_COUNT] = {
++static struct smu_11_0_cmn2aisc_mapping vega20_feature_mask_map[SMU_FEATURE_COUNT] = {
+ 	FEA_MAP(DPM_PREFETCHER),
+ 	FEA_MAP(DPM_GFXCLK),
+ 	FEA_MAP(DPM_UCLK),
+@@ -195,7 +195,7 @@ static int vega20_feature_mask_map[SMU_FEATURE_COUNT] = {
+ 	FEA_MAP(XGMI),
+ };
+ 
+-static int vega20_table_map[SMU_TABLE_COUNT] = {
++static struct smu_11_0_cmn2aisc_mapping vega20_table_map[SMU_TABLE_COUNT] = {
+ 	TAB_MAP(PPTABLE),
+ 	TAB_MAP(WATERMARKS),
+ 	TAB_MAP(AVFS),
+@@ -208,12 +208,12 @@ static int vega20_table_map[SMU_TABLE_COUNT] = {
+ 	TAB_MAP(OVERDRIVE),
+ };
+ 
+-static int vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
++static struct smu_11_0_cmn2aisc_mapping vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
+ 	PWR_MAP(AC),
+ 	PWR_MAP(DC),
+ };
+ 
+-static int vega20_workload_map[] = {
++static struct smu_11_0_cmn2aisc_mapping vega20_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
+ 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,	WORKLOAD_DEFAULT_BIT),
+ 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,		WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
+ 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,		WORKLOAD_PPLIB_POWER_SAVING_BIT),
+@@ -225,79 +225,86 @@ static int vega20_workload_map[] = {
+ 
+ static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index)
+ {
+-	int val;
++	struct smu_11_0_cmn2aisc_mapping mapping;
++
+ 	if (index >= SMU_TABLE_COUNT)
+ 		return -EINVAL;
+ 
+-	val = vega20_table_map[index];
+-	if (val >= TABLE_COUNT)
++	mapping = vega20_table_map[index];
++	if (!(mapping.valid_mapping))
+ 		return -EINVAL;
+ 
+-	return val;
++	return mapping.map_to;
+ }
+ 
+ static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index)
+ {
+-	int val;
++	struct smu_11_0_cmn2aisc_mapping mapping;
++
+ 	if (index >= SMU_POWER_SOURCE_COUNT)
+ 		return -EINVAL;
+ 
+-	val = vega20_pwr_src_map[index];
+-	if (val >= POWER_SOURCE_COUNT)
++	mapping = vega20_pwr_src_map[index];
++	if (!(mapping.valid_mapping))
+ 		return -EINVAL;
+ 
+-	return val;
++	return mapping.map_to;
+ }
+ 
+ static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index)
+ {
+-	int val;
++	struct smu_11_0_cmn2aisc_mapping mapping;
++
+ 	if (index >= SMU_FEATURE_COUNT)
+ 		return -EINVAL;
+ 
+-	val = vega20_feature_mask_map[index];
+-	if (val > 64)
++	mapping = vega20_feature_mask_map[index];
++	if (!(mapping.valid_mapping))
+ 		return -EINVAL;
+ 
+-	return val;
++	return mapping.map_to;
+ }
+ 
+ static int vega20_get_smu_clk_index(struct smu_context *smc, uint32_t index)
+ {
+-	int val;
++	struct smu_11_0_cmn2aisc_mapping mapping;
++
+ 	if (index >= SMU_CLK_COUNT)
+ 		return -EINVAL;
+ 
+-	val = vega20_clk_map[index];
+-	if (val >= PPCLK_COUNT)
++	mapping = vega20_clk_map[index];
++	if (!(mapping.valid_mapping))
+ 		return -EINVAL;
+ 
+-	return val;
++	return mapping.map_to;
+ }
+ 
+ static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+ {
+-	int val;
++	struct smu_11_0_cmn2aisc_mapping mapping;
+ 
+ 	if (index >= SMU_MSG_MAX_COUNT)
+ 		return -EINVAL;
+ 
+-	val = vega20_message_map[index];
+-	if (val > PPSMC_Message_Count)
++	mapping = vega20_message_map[index];
++	if (!(mapping.valid_mapping))
+ 		return -EINVAL;
+ 
+-	return val;
++	return mapping.map_to;
+ }
+ 
+ static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
+ {
+-	int val;
++	struct smu_11_0_cmn2aisc_mapping mapping;
++
+ 	if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
+ 		return -EINVAL;
+ 
+-	val = vega20_workload_map[profile];
++	mapping = vega20_workload_map[profile];
++	if (!(mapping.valid_mapping))
++		return -EINVAL;
+ 
+-	return val;
++	return mapping.map_to;
+ }
+ 
+ static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2991-drm-amd-powerplay-input-check-for-unsupported-messag.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2991-drm-amd-powerplay-input-check-for-unsupported-messag.patch
new file mode 100644
index 00000000..fdad03f9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2991-drm-amd-powerplay-input-check-for-unsupported-messag.patch
@@ -0,0 +1,401 @@
+From 88f16f4dae5ced672fd9a3c2938b3233a6d24837 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 11 Jul 2019 14:36:44 +0800
+Subject: [PATCH 2991/4256] drm/amd/powerplay: input check for unsupported
+ message/clock index
+
+This can avoid them to be handled in a wrong way without notice.
+Since not all SMU messages/clocks are supported on every SMU11 ASIC.
+
+Change-Id: I440b80833c81066cd36613beae555f2fa068199f
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 18 +++++++----
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 31 ++++++++++++++-----
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c  | 35 ++++++++++++++++++----
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 31 ++++++++++++++-----
+ 4 files changed, 90 insertions(+), 25 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 342d57f2fc5f..40604fe1c684 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -331,7 +331,7 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index,
+ 	int ret = 0;
+ 	int table_id = smu_table_get_index(smu, table_index);
+ 
+-	if (!table_data || table_id >= smu_table->table_count)
++	if (!table_data || table_id >= smu_table->table_count || table_id < 0)
+ 		return -EINVAL;
+ 
+ 	table = &smu_table->tables[table_index];
+@@ -462,10 +462,12 @@ int smu_feature_init_dpm(struct smu_context *smu)
+ int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
+ {
+ 	struct smu_feature *feature = &smu->smu_feature;
+-	uint32_t feature_id;
++	int feature_id;
+ 	int ret = 0;
+ 
+ 	feature_id = smu_feature_get_index(smu, mask);
++	if (feature_id < 0)
++		return 0;
+ 
+ 	WARN_ON(feature_id > feature->feature_num);
+ 
+@@ -480,10 +482,12 @@ int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
+ 			    bool enable)
+ {
+ 	struct smu_feature *feature = &smu->smu_feature;
+-	uint32_t feature_id;
++	int feature_id;
+ 	int ret = 0;
+ 
+ 	feature_id = smu_feature_get_index(smu, mask);
++	if (feature_id < 0)
++		return -EINVAL;
+ 
+ 	WARN_ON(feature_id > feature->feature_num);
+ 
+@@ -506,10 +510,12 @@ int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
+ int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
+ {
+ 	struct smu_feature *feature = &smu->smu_feature;
+-	uint32_t feature_id;
++	int feature_id;
+ 	int ret = 0;
+ 
+ 	feature_id = smu_feature_get_index(smu, mask);
++	if (feature_id < 0)
++		return 0;
+ 
+ 	WARN_ON(feature_id > feature->feature_num);
+ 
+@@ -525,10 +531,12 @@ int smu_feature_set_supported(struct smu_context *smu,
+ 			      bool enable)
+ {
+ 	struct smu_feature *feature = &smu->smu_feature;
+-	uint32_t feature_id;
++	int feature_id;
+ 	int ret = 0;
+ 
+ 	feature_id = smu_feature_get_index(smu, mask);
++	if (feature_id < 0)
++		return -EINVAL;
+ 
+ 	WARN_ON(feature_id > feature->feature_num);
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 102310461119..0c40d390d04b 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -216,8 +216,10 @@ static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+ 		return -EINVAL;
+ 
+ 	mapping = navi10_message_map[index];
+-	if (!(mapping.valid_mapping))
++	if (!(mapping.valid_mapping)) {
++		pr_warn("Unsupported SMU message: %d\n", index);
+ 		return -EINVAL;
++	}
+ 
+ 	return mapping.map_to;
+ }
+@@ -230,8 +232,10 @@ static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
+ 		return -EINVAL;
+ 
+ 	mapping = navi10_clk_map[index];
+-	if (!(mapping.valid_mapping))
++	if (!(mapping.valid_mapping)) {
++		pr_warn("Unsupported SMU clock: %d\n", index);
+ 		return -EINVAL;
++	}
+ 
+ 	return mapping.map_to;
+ }
+@@ -244,8 +248,10 @@ static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
+ 		return -EINVAL;
+ 
+ 	mapping = navi10_feature_mask_map[index];
+-	if (!(mapping.valid_mapping))
++	if (!(mapping.valid_mapping)) {
++		pr_warn("Unsupported SMU feature: %d\n", index);
+ 		return -EINVAL;
++	}
+ 
+ 	return mapping.map_to;
+ }
+@@ -258,8 +264,10 @@ static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
+ 		return -EINVAL;
+ 
+ 	mapping = navi10_table_map[index];
+-	if (!(mapping.valid_mapping))
++	if (!(mapping.valid_mapping)) {
++		pr_warn("Unsupported SMU table: %d\n", index);
+ 		return -EINVAL;
++	}
+ 
+ 	return mapping.map_to;
+ }
+@@ -272,8 +280,10 @@ static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
+ 		return -EINVAL;
+ 
+ 	mapping = navi10_pwr_src_map[index];
+-	if (!(mapping.valid_mapping))
++	if (!(mapping.valid_mapping)) {
++		pr_warn("Unsupported power source: %d\n", index);
+ 		return -EINVAL;
++	}
+ 
+ 	return mapping.map_to;
+ }
+@@ -287,8 +297,10 @@ static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_P
+ 		return -EINVAL;
+ 
+ 	mapping = navi10_workload_map[profile];
+-	if (!(mapping.valid_mapping))
++	if (!(mapping.valid_mapping)) {
++		pr_warn("Unsupported workload: %d\n", (int)profile);
+ 		return -EINVAL;
++	}
+ 
+ 	return mapping.map_to;
+ }
+@@ -969,7 +981,7 @@ static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
+ {
+ 	DpmActivityMonitorCoeffInt_t activity_monitor;
+ 	uint32_t i, size = 0;
+-	uint16_t workload_type = 0;
++	int16_t workload_type = 0;
+ 	static const char *profile_name[] = {
+ 					"BOOTUP_DEFAULT",
+ 					"3D_FULL_SCREEN",
+@@ -1002,6 +1014,9 @@ static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
+ 	for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
+ 		/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
+ 		workload_type = smu_workload_get_type(smu, i);
++		if (workload_type < 0)
++			return -EINVAL;
++
+ 		result = smu_update_table(smu,
+ 					  SMU_TABLE_ACTIVITY_MONITOR_COEFF | workload_type << 16,
+ 					  (void *)(&activity_monitor), false);
+@@ -1130,6 +1145,8 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u
+ 
+ 	/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
+ 	workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
++	if (workload_type < 0)
++		return -EINVAL;
+ 	smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
+ 				    1 << workload_type);
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 7d723a5e4135..e60a5ceb5bff 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -928,11 +928,17 @@ smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
+ 				    enum smu_clk_type clock_select)
+ {
+ 	int ret = 0;
++	int clk_id;
+ 
+ 	if (!smu->pm_enabled)
+ 		return ret;
++
++	clk_id = smu_clk_get_index(smu, clock_select);
++	if (clk_id < 0)
++		return -EINVAL;
++
+ 	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
+-					  smu_clk_get_index(smu, clock_select) << 16);
++					  clk_id << 16);
+ 	if (ret) {
+ 		pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
+ 		return ret;
+@@ -947,7 +953,7 @@ smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
+ 
+ 	/* if DC limit is zero, return AC limit */
+ 	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
+-					  smu_clk_get_index(smu, clock_select) << 16);
++					  clk_id << 16);
+ 	if (ret) {
+ 		pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
+ 		return ret;
+@@ -1043,6 +1049,11 @@ static int smu_v11_0_get_power_limit(struct smu_context *smu,
+ 				     bool get_default)
+ {
+ 	int ret = 0;
++	int power_src;
++
++	power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
++	if (power_src < 0)
++		return -EINVAL;
+ 
+ 	if (get_default) {
+ 		mutex_lock(&smu->mutex);
+@@ -1054,7 +1065,7 @@ static int smu_v11_0_get_power_limit(struct smu_context *smu,
+ 		mutex_unlock(&smu->mutex);
+ 	} else {
+ 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
+-			smu_power_get_index(smu, SMU_POWER_SOURCE_AC) << 16);
++			power_src << 16);
+ 		if (ret) {
+ 			pr_err("[%s] get PPT limit failed!", __func__);
+ 			return ret;
+@@ -1097,16 +1108,21 @@ static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
+ {
+ 	int ret = 0;
+ 	uint32_t freq = 0;
++	int asic_clk_id;
+ 
+ 	if (clk_id >= SMU_CLK_COUNT || !value)
+ 		return -EINVAL;
+ 
++	asic_clk_id = smu_clk_get_index(smu, clk_id);
++	if (asic_clk_id < 0)
++		return -EINVAL;
++
+ 	/* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
+-	if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) == 0)
++	if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) < 0)
+ 		ret =  smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
+ 	else {
+ 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
+-						  (smu_clk_get_index(smu, clk_id) << 16));
++						  (asic_clk_id << 16));
+ 		if (ret)
+ 			return ret;
+ 
+@@ -1286,6 +1302,7 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
+ 	int ret = 0;
+ 	enum smu_clk_type clk_select = 0;
+ 	uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
++	int clk_id;
+ 
+ 	if (!smu->pm_enabled)
+ 		return -EINVAL;
+@@ -1317,9 +1334,15 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
+ 		if (ret)
+ 			goto failed;
+ 
++		clk_id = smu_clk_get_index(smu, clk_select);
++		if (clk_id < 0) {
++			ret = -EINVAL;
++			goto failed;
++		}
++
+ 		mutex_lock(&smu->mutex);
+ 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
+-			(smu_clk_get_index(smu, clk_select) << 16) | clk_freq);
++			(clk_id << 16) | clk_freq);
+ 		mutex_unlock(&smu->mutex);
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 52ea26e328c3..6b0180d1552b 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -231,8 +231,10 @@ static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index)
+ 		return -EINVAL;
+ 
+ 	mapping = vega20_table_map[index];
+-	if (!(mapping.valid_mapping))
++	if (!(mapping.valid_mapping)) {
++		pr_warn("Unsupported SMU table: %d\n", index);
+ 		return -EINVAL;
++	}
+ 
+ 	return mapping.map_to;
+ }
+@@ -245,8 +247,10 @@ static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index)
+ 		return -EINVAL;
+ 
+ 	mapping = vega20_pwr_src_map[index];
+-	if (!(mapping.valid_mapping))
++	if (!(mapping.valid_mapping)) {
++		pr_warn("Unsupported power source: %d\n", index);
+ 		return -EINVAL;
++	}
+ 
+ 	return mapping.map_to;
+ }
+@@ -259,8 +263,10 @@ static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index)
+ 		return -EINVAL;
+ 
+ 	mapping = vega20_feature_mask_map[index];
+-	if (!(mapping.valid_mapping))
++	if (!(mapping.valid_mapping)) {
++		pr_warn("Unsupported SMU feature: %d\n", index);
+ 		return -EINVAL;
++	}
+ 
+ 	return mapping.map_to;
+ }
+@@ -273,8 +279,10 @@ static int vega20_get_smu_clk_index(struct smu_context *smc, uint32_t index)
+ 		return -EINVAL;
+ 
+ 	mapping = vega20_clk_map[index];
+-	if (!(mapping.valid_mapping))
++	if (!(mapping.valid_mapping)) {
++		pr_warn("Unsupported SMU clock: %d\n", index);
+ 		return -EINVAL;
++	}
+ 
+ 	return mapping.map_to;
+ }
+@@ -287,8 +295,10 @@ static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+ 		return -EINVAL;
+ 
+ 	mapping = vega20_message_map[index];
+-	if (!(mapping.valid_mapping))
++	if (!(mapping.valid_mapping)) {
++		pr_warn("Unsupported SMU message: %d\n", index);
+ 		return -EINVAL;
++	}
+ 
+ 	return mapping.map_to;
+ }
+@@ -301,8 +311,10 @@ static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_P
+ 		return -EINVAL;
+ 
+ 	mapping = vega20_workload_map[profile];
+-	if (!(mapping.valid_mapping))
++	if (!(mapping.valid_mapping)) {
++		pr_warn("Unsupported SMU workload: %d\n", (int)profile);
+ 		return -EINVAL;
++	}
+ 
+ 	return mapping.map_to;
+ }
+@@ -1778,7 +1790,7 @@ static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf)
+ {
+ 	DpmActivityMonitorCoeffInt_t activity_monitor;
+ 	uint32_t i, size = 0;
+-	uint16_t workload_type = 0;
++	int16_t workload_type = 0;
+ 	static const char *profile_name[] = {
+ 					"BOOTUP_DEFAULT",
+ 					"3D_FULL_SCREEN",
+@@ -1811,6 +1823,9 @@ static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf)
+ 	for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
+ 		/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
+ 		workload_type = smu_workload_get_type(smu, i);
++		if (workload_type < 0)
++			return -EINVAL;
++
+ 		result = smu_update_table(smu,
+ 					  SMU_TABLE_ACTIVITY_MONITOR_COEFF | workload_type << 16,
+ 					  (void *)(&activity_monitor), false);
+@@ -1963,6 +1978,8 @@ static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, u
+ 
+ 	/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
+ 	workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
++	if (workload_type < 0)
++		return -EINVAL;
+ 	smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
+ 				    1 << workload_type);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2992-drm-amd-powerplay-correct-smu_update_table-usage.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2992-drm-amd-powerplay-correct-smu_update_table-usage.patch
new file mode 100644
index 00000000..a69e286f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2992-drm-amd-powerplay-correct-smu_update_table-usage.patch
@@ -0,0 +1,250 @@
+From ac9c38946a2e033899db8b46f89a6d8e295e273d Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 11 Jul 2019 15:13:17 +0800
+Subject: [PATCH 2992/4256] drm/amd/powerplay: correct smu_update_table usage
+
+The interface was used in a confusing way. In profile mode scenario,
+the 2nd parameter of the interface was used in a different way from
+other scenarios.
+
+Change-Id: Iabcebb47db8fdf242580c1059393132ee10b93e4
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  4 ++--
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  2 +-
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 16 +++++++--------
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     |  4 ++--
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 20 +++++++++----------
+ 5 files changed, 23 insertions(+), 23 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 40604fe1c684..5d5664fb1a84 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -323,7 +323,7 @@ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
+ 	return ret;
+ }
+ 
+-int smu_update_table(struct smu_context *smu, enum smu_table_id table_index,
++int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
+ 		     void *table_data, bool drv2smu)
+ {
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+@@ -350,7 +350,7 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index,
+ 	ret = smu_send_smc_msg_with_param(smu, drv2smu ?
+ 					  SMU_MSG_TransferTableDram2Smu :
+ 					  SMU_MSG_TransferTableSmu2Dram,
+-					  table_id);
++					  table_id | ((argument & 0xFFFF) << 16));
+ 	if (ret)
+ 		return ret;
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index c80077db6cf5..514d31518853 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -947,7 +947,7 @@ extern int smu_feature_is_supported(struct smu_context *smu,
+ extern int smu_feature_set_supported(struct smu_context *smu,
+ 				     enum smu_feature_mask mask, bool enable);
+ 
+-int smu_update_table(struct smu_context *smu, uint32_t table_index,
++int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
+ 		     void *table_data, bool drv2smu);
+ 
+ bool is_support_sw_smu(struct amdgpu_device *adev);
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 0c40d390d04b..0ab02efcbc83 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -633,7 +633,7 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
+ 
+ 	memset(&metrics, 0, sizeof(metrics));
+ 
+-	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics, false);
++	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -886,7 +886,7 @@ static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
+ 	if (!value)
+ 		return -EINVAL;
+ 
+-	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics,
++	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics,
+ 			       false);
+ 	if (ret)
+ 		return ret;
+@@ -908,7 +908,7 @@ static int navi10_get_current_activity_percent(struct smu_context *smu,
+ 
+ 	msleep(1);
+ 
+-	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
++	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
+ 			       (void *)&metrics, false);
+ 	if (ret)
+ 		return ret;
+@@ -949,7 +949,7 @@ static int navi10_get_fan_speed(struct smu_context *smu, uint16_t *value)
+ 
+ 	memset(&metrics, 0, sizeof(metrics));
+ 
+-	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
++	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
+ 			       (void *)&metrics, false);
+ 	if (ret)
+ 		return ret;
+@@ -1018,7 +1018,7 @@ static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
+ 			return -EINVAL;
+ 
+ 		result = smu_update_table(smu,
+-					  SMU_TABLE_ACTIVITY_MONITOR_COEFF | workload_type << 16,
++					  SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
+ 					  (void *)(&activity_monitor), false);
+ 		if (result) {
+ 			pr_err("[%s] Failed to get activity monitor!", __func__);
+@@ -1091,7 +1091,7 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u
+ 			return -EINVAL;
+ 
+ 		ret = smu_update_table(smu,
+-				       SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16,
++				       SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
+ 				       (void *)(&activity_monitor), false);
+ 		if (ret) {
+ 			pr_err("[%s] Failed to get activity monitor!", __func__);
+@@ -1135,7 +1135,7 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u
+ 		}
+ 
+ 		ret = smu_update_table(smu,
+-				       SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16,
++				       SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
+ 				       (void *)(&activity_monitor), true);
+ 		if (ret) {
+ 			pr_err("[%s] Failed to set activity monitor!", __func__);
+@@ -1303,7 +1303,7 @@ static int navi10_thermal_get_temperature(struct smu_context *smu,
+ 	if (!value)
+ 		return -EINVAL;
+ 
+-	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics, false);
++	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
+ 	if (ret)
+ 		return ret;
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index e60a5ceb5bff..9f60e5c78ba0 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -710,7 +710,7 @@ static int smu_v11_0_write_pptable(struct smu_context *smu)
+ 	struct smu_table_context *table_context = &smu->smu_table;
+ 	int ret = 0;
+ 
+-	ret = smu_update_table(smu, SMU_TABLE_PPTABLE,
++	ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
+ 			       table_context->driver_pptable, true);
+ 
+ 	return ret;
+@@ -729,7 +729,7 @@ static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
+ 	if (!table->cpu_addr)
+ 		return -EINVAL;
+ 
+-	ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, table->cpu_addr,
++	ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
+ 				true);
+ 
+ 	return ret;
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 6b0180d1552b..ff74ac76805d 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -1699,7 +1699,7 @@ static int vega20_get_metrics_table(struct smu_context *smu,
+ 	int ret = 0;
+ 
+ 	if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
+-		ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
++		ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
+ 				(void *)smu_table->metrics_table, false);
+ 		if (ret) {
+ 			pr_info("Failed to export SMU metrics table!\n");
+@@ -1728,7 +1728,7 @@ static int vega20_set_default_od_settings(struct smu_context *smu,
+ 		if (!table_context->overdrive_table)
+ 			return -ENOMEM;
+ 
+-		ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
++		ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
+ 				       table_context->overdrive_table, false);
+ 		if (ret) {
+ 			pr_err("Failed to export over drive table!\n");
+@@ -1740,7 +1740,7 @@ static int vega20_set_default_od_settings(struct smu_context *smu,
+ 			return ret;
+ 	}
+ 
+-	ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
++	ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
+ 			       table_context->overdrive_table, true);
+ 	if (ret) {
+ 		pr_err("Failed to import over drive table!\n");
+@@ -1827,7 +1827,7 @@ static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf)
+ 			return -EINVAL;
+ 
+ 		result = smu_update_table(smu,
+-					  SMU_TABLE_ACTIVITY_MONITOR_COEFF | workload_type << 16,
++					  SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
+ 					  (void *)(&activity_monitor), false);
+ 		if (result) {
+ 			pr_err("[%s] Failed to get activity monitor!", __func__);
+@@ -1913,7 +1913,7 @@ static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, u
+ 
+ 	if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
+ 		ret = smu_update_table(smu,
+-				       SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16,
++				       SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
+ 				       (void *)(&activity_monitor), false);
+ 		if (ret) {
+ 			pr_err("[%s] Failed to get activity monitor!", __func__);
+@@ -1968,7 +1968,7 @@ static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, u
+ 		}
+ 
+ 		ret = smu_update_table(smu,
+-				       SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16,
++				       SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
+ 				       (void *)(&activity_monitor), true);
+ 		if (ret) {
+ 			pr_err("[%s] Failed to set activity monitor!", __func__);
+@@ -2519,7 +2519,7 @@ static int vega20_update_od8_settings(struct smu_context *smu,
+ 	struct smu_table_context *table_context = &smu->smu_table;
+ 	int ret;
+ 
+-	ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
++	ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
+ 			       table_context->overdrive_table, false);
+ 	if (ret) {
+ 		pr_err("Failed to export over drive table!\n");
+@@ -2530,7 +2530,7 @@ static int vega20_update_od8_settings(struct smu_context *smu,
+ 	if (ret)
+ 		return ret;
+ 
+-	ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
++	ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
+ 			       table_context->overdrive_table, true);
+ 	if (ret) {
+ 		pr_err("Failed to import over drive table!\n");
+@@ -2794,7 +2794,7 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu,
+ 		break;
+ 
+ 	case PP_OD_RESTORE_DEFAULT_TABLE:
+-		ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, table_context->overdrive_table, false);
++		ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
+ 		if (ret) {
+ 			pr_err("Failed to export over drive table!\n");
+ 			return ret;
+@@ -2803,7 +2803,7 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu,
+ 		break;
+ 
+ 	case PP_OD_COMMIT_DPM_TABLE:
+-		ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, table_context->overdrive_table, true);
++		ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
+ 		if (ret) {
+ 			pr_err("Failed to import over drive table!\n");
+ 			return ret;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2993-drm-amd-powerplay-maintain-SMU-FW-backward-compatibi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2993-drm-amd-powerplay-maintain-SMU-FW-backward-compatibi.patch
new file mode 100644
index 00000000..b73fd571
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2993-drm-amd-powerplay-maintain-SMU-FW-backward-compatibi.patch
@@ -0,0 +1,47 @@
+From 49546878f068753b202b7778c6c4480117a17be5 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 16 Jul 2019 14:20:22 +0800
+Subject: [PATCH 2993/4256] drm/amd/powerplay: maintain SMU FW backward
+ compatibility
+
+Do not halt driver loading on if_version mismatch. As our
+driver and FWs are backward compatible.
+
+Change-Id: I01271202d08a62e775efabfb66310f6cc742b9dd
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 12 +++++++++---
+ 1 file changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 9f60e5c78ba0..76bc157525d0 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -267,14 +267,20 @@ static int smu_v11_0_check_fw_version(struct smu_context *smu)
+ 	smu_minor = (smu_version >> 8) & 0xff;
+ 	smu_debug = (smu_version >> 0) & 0xff;
+ 
+-
++	/*
++	 * 1. if_version mismatch is not critical as our fw is designed
++	 * to be backward compatible.
++	 * 2. New fw usually brings some optimizations. But that's visible
++	 * only on the paired driver.
++	 * Considering above, we just leave user a warning message instead
++	 * of halt driver loading.
++	 */
+ 	if (if_version != smu->smc_if_version) {
+ 		pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
+ 			"smu fw version = 0x%08x (%d.%d.%d)\n",
+ 			smu->smc_if_version, if_version,
+ 			smu_version, smu_major, smu_minor, smu_debug);
+-		pr_err("SMU driver if version not matched\n");
+-		ret = -EINVAL;
++		pr_warn("SMU driver if version not matched\n");
+ 	}
+ 
+ 	return ret;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2994-drm-amd-powerplay-update-vega20-driver-if-to-fit-lat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2994-drm-amd-powerplay-update-vega20-driver-if-to-fit-lat.patch
new file mode 100644
index 00000000..55abc7ea
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2994-drm-amd-powerplay-update-vega20-driver-if-to-fit-lat.patch
@@ -0,0 +1,49 @@
+From 77e8ffc5dfdadcb7b59ef9677ea40808fe8105d5 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 12 Jul 2019 10:53:11 +0800
+Subject: [PATCH 2994/4256] drm/amd/powerplay: update vega20 driver if to fit
+ latest SMU firmware
+
+Optimization for the socket power calculation is introduced.
+
+Change-Id: Icc8a687357ba46ae1d199d89cb2000c61b4de703
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
+index 195c4ae67058..755d51f9c6a9 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
+@@ -27,7 +27,7 @@
+ // *** IMPORTANT ***
+ // SMU TEAM: Always increment the interface version if
+ // any structure is changed in this file
+-#define SMU11_DRIVER_IF_VERSION 0x12
++#define SMU11_DRIVER_IF_VERSION 0x13
+ 
+ #define PPTABLE_V20_SMU_VERSION 3
+ 
+@@ -615,6 +615,7 @@ typedef struct {
+   uint16_t     UclkAverageLpfTau;
+   uint16_t     GfxActivityLpfTau;
+   uint16_t     UclkActivityLpfTau;
++  uint16_t     SocketPowerLpfTau;
+ 
+ 
+   uint32_t     MmHubPadding[8];
+@@ -665,7 +666,8 @@ typedef struct {
+   uint32_t ThrottlerStatus       ;
+ 
+   uint8_t  LinkDpmLevel;
+-  uint8_t  Padding[3];
++  uint16_t AverageSocketPower;
++  uint8_t  Padding;
+ 
+ 
+   uint32_t     MmHubPadding[7];
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2995-drm-amd-amdgpu-Fix-offset-for-vmid-selection-in-debu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2995-drm-amd-amdgpu-Fix-offset-for-vmid-selection-in-debu.patch
new file mode 100644
index 00000000..257bb7a9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2995-drm-amd-amdgpu-Fix-offset-for-vmid-selection-in-debu.patch
@@ -0,0 +1,35 @@
+From b2e76aebcb968ab62bd13e45548f4046c5f96bff Mon Sep 17 00:00:00 2001
+From: Tom St Denis <tom.stdenis@amd.com>
+Date: Tue, 16 Jul 2019 07:23:22 -0400
+Subject: [PATCH 2995/4256] drm/amd/amdgpu: Fix offset for vmid selection in
+ debugfs interface
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The register debugfs interface was using the wrong bitmask for vmid
+selection for GFX_CNTL.
+
+Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+index 87b32873046f..59849ed9797d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+@@ -132,7 +132,7 @@ static int  amdgpu_debugfs_process_reg_op(bool read, struct file *f,
+ 		me = (*pos & GENMASK_ULL(33, 24)) >> 24;
+ 		pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
+ 		queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
+-		vmid = (*pos & GENMASK_ULL(48, 45)) >> 54;
++		vmid = (*pos & GENMASK_ULL(58, 54)) >> 54;
+ 
+ 		use_ring = 1;
+ 	} else {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2996-drm-amdkfd-Remove-GWS-from-process-during-uninit.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2996-drm-amdkfd-Remove-GWS-from-process-during-uninit.patch
new file mode 100644
index 00000000..a87554f9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2996-drm-amdkfd-Remove-GWS-from-process-during-uninit.patch
@@ -0,0 +1,36 @@
+From 539de4f96970091637ca6df1da1e314f89f5657d Mon Sep 17 00:00:00 2001
+From: Joseph Greathouse <Joseph.Greathouse@amd.com>
+Date: Wed, 17 Jul 2019 09:47:58 -0500
+Subject: [PATCH 2996/4256] drm/amdkfd: Remove GWS from process during uninit
+
+If we shut down a process without having destroyed its GWS-using
+queues, it is possible that GWS BO will still be in the process
+BO list during the gpuvm destruction. This list should be empty
+at that time, so we should remove the GWS allocation at the
+process uninit point if it is still around.
+
+Change-Id: I098e7b315070dd5b0165bb7905aef643450f27f2
+Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+index da0958625861..7e6c3ee82f5b 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+@@ -150,6 +150,9 @@ void pqm_uninit(struct process_queue_manager *pqm)
+ 	struct process_queue_node *pqn, *next;
+ 
+ 	list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) {
++		if (pqn->q && pqn->q->gws)
++			amdgpu_amdkfd_remove_gws_from_process(pqm->process->kgd_process_info,
++				pqn->q->gws);
+ 		uninit_queue(pqn->q);
+ 		list_del(&pqn->process_queue_list);
+ 		kfree(pqn);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2997-drm-amdgpu-exposing-fica-registers-to-df-offsets.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2997-drm-amdgpu-exposing-fica-registers-to-df-offsets.patch
new file mode 100644
index 00000000..3ff2b3e0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2997-drm-amdgpu-exposing-fica-registers-to-df-offsets.patch
@@ -0,0 +1,31 @@
+From b94a5dbdea44dc80f67c683f3ac7a6dc8303c127 Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Thu, 11 Jul 2019 12:19:44 -0400
+Subject: [PATCH 2997/4256] drm/amdgpu: exposing fica registers to df offsets
+
+exposing fica registers to poll df pie data for xgmi error counters for
+vega20.
+
+Change-Id: Idc0d24f3bc795503491733d9ee4dff48c2fe0bef
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
+index 6efcaa93e17b..c2bd25589e84 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
+@@ -48,4 +48,8 @@
+ #define smnPerfMonCtrLo3					0x01d478UL
+ #define smnPerfMonCtrHi3					0x01d47cUL
+ 
++#define smnDF_PIE_AON_FabricIndirectConfigAccessAddress3	0x1d05cUL
++#define smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3		0x1d098UL
++#define smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3		0x1d09cUL
++
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2998-drm-amdgpu-Default-disable-GDS-for-compute-VMIDs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2998-drm-amdgpu-Default-disable-GDS-for-compute-VMIDs.patch
new file mode 100644
index 00000000..fdcbf353
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2998-drm-amdgpu-Default-disable-GDS-for-compute-VMIDs.patch
@@ -0,0 +1,121 @@
+From d4f38503c8c78bc6faa6c07f7c864f7aeec2241b Mon Sep 17 00:00:00 2001
+From: Joseph Greathouse <Joseph.Greathouse@amd.com>
+Date: Wed, 17 Jul 2019 11:55:22 -0500
+Subject: [PATCH 2998/4256] drm/amdgpu: Default disable GDS for compute VMIDs
+
+The GDS and GWS blocks default to allowing all VMIDs to
+access all entries. Graphics VMIDs can handle setting
+these limits when the driver launches work. However,
+compute workloads under HWS control don't go through the
+kernel driver. Instead, HWS firmware should set these
+limits when a process is put into a VMID slot.
+
+Disable access to these devices by default by turning off
+all mask bits (for OA) and setting BASE=SIZE=0 (for GDS
+and GWS) for all compute VMIDs. If a process wants to use
+these resources, they can request this from the HWS
+firmware (when such capabilities are enabled). HWS will
+then handle setting the base and limit for the process when
+it is assigned to a VMID.
+
+This will also prevent user kernels from getting 'stuck' in
+GWS by accident if they write GWS-using code but HWS
+firmware is not set up to handle GWS reset. Until HWS is
+enabled to handle GWS properly, all GWS accesses will
+MEM_VIOL fault the kernel.
+
+v2: Move initialization outside of SRBM mutex
+
+Change-Id: I3129a1295998b4234df8c3e824b0002058cf9c64
+Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 9 +++++++++
+ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  | 9 +++++++++
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 9 +++++++++
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 9 +++++++++
+ 4 files changed, 36 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 85d33d6af5a3..ed48dc5fe36a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1516,6 +1516,15 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
+ 	}
+ 	nv_grbm_select(adev, 0, 0, 0, 0);
+ 	mutex_unlock(&adev->srbm_mutex);
++
++	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
++	   acccess. These should be enabled by FW for target VMIDs. */
++	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
++		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
++		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
++		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
++		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
++	}
+ }
+ 
+ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+index e1e2a44ee13c..3f98624772a4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+@@ -1877,6 +1877,15 @@ static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
+ 	}
+ 	cik_srbm_select(adev, 0, 0, 0, 0);
+ 	mutex_unlock(&adev->srbm_mutex);
++
++	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
++	   acccess. These should be enabled by FW for target VMIDs. */
++	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
++		WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
++		WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
++		WREG32(amdgpu_gds_reg_offset[i].gws, 0);
++		WREG32(amdgpu_gds_reg_offset[i].oa, 0);
++	}
+ }
+ 
+ static void gfx_v7_0_config_init(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index e16800839172..a18d8ab1e4b2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -3702,6 +3702,15 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
+ 	}
+ 	vi_srbm_select(adev, 0, 0, 0, 0);
+ 	mutex_unlock(&adev->srbm_mutex);
++
++	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
++	   acccess. These should be enabled by FW for target VMIDs. */
++	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
++		WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
++		WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
++		WREG32(amdgpu_gds_reg_offset[i].gws, 0);
++		WREG32(amdgpu_gds_reg_offset[i].oa, 0);
++	}
+ }
+ 
+ static void gfx_v8_0_config_init(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 3bcf02bf4c9b..6fa433ff6043 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -2025,6 +2025,15 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
+ 	}
+ 	soc15_grbm_select(adev, 0, 0, 0, 0);
+ 	mutex_unlock(&adev->srbm_mutex);
++
++	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
++	   acccess. These should be enabled by FW for target VMIDs. */
++	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
++		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
++		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
++		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
++		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
++	}
+ }
+ 
+ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2999-drm-amdgpu-Add-navi10-kfd-support-for-amdgpu-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2999-drm-amdgpu-Add-navi10-kfd-support-for-amdgpu-v3.patch
new file mode 100644
index 00000000..9fd5c79a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2999-drm-amdgpu-Add-navi10-kfd-support-for-amdgpu-v3.patch
@@ -0,0 +1,1076 @@
+From b6cb691101faba6dcc77c6f395a0bfd5c55f23fc Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Tue, 5 Mar 2019 19:59:30 +0800
+Subject: [PATCH 2999/4256] drm/amdgpu: Add navi10 kfd support for amdgpu (v3)
+
+KFD (Kernel Fusion Driver) is the compute backend driver
+for AMD GPUs.
+
+v2: squash in updates (Alex)
+v3: fix warnings (Alex)
+
+Change-Id: I173523953bc281a7a4df9ebf87d865f3bbbc32c4
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Signed-off-by: Philip Cox <Philip.Cox@amd.com>
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile           |   3 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c    |  16 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h    |   1 +
+ .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c    | 975 ++++++++++++++++++
+ 4 files changed, 991 insertions(+), 4 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index 35998d3b60eb..bb2e00bbdee1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -169,7 +169,8 @@ amdgpu-y += \
+ 	 amdgpu_amdkfd_gpuvm.o \
+ 	 amdgpu_amdkfd_gfx_v8.o \
+ 	 amdgpu_amdkfd_gfx_v9.o \
+-	 amdgpu_amdkfd_arcturus.o
++	 amdgpu_amdkfd_arcturus.o \
++	 amdgpu_amdkfd_gfx_v10.o
+ 
+ ifneq ($(CONFIG_DRM_AMDGPU_CIK),)
+ amdgpu-y += amdgpu_amdkfd_gfx_v7.o
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+index 78b78f898de1..859763c7f419 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+@@ -96,6 +96,8 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
+ 		break;
+ 	case CHIP_ARCTURUS:
+ 		kfd2kgd = amdgpu_amdkfd_arcturus_get_functions();
++	case CHIP_NAVI10:
++		kfd2kgd = amdgpu_amdkfd_gfx_10_0_get_functions();
+ 		break;
+ 	default:
+ 		dev_info(adev->dev, "kfd not supported on this ASIC\n");
+@@ -457,9 +459,12 @@ void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
+ 
+ 	if (amdgpu_sriov_vf(adev))
+ 		mem_info->mem_clk_max = adev->clock.default_mclk / 100;
+-	else if (adev->powerplay.pp_funcs)
+-		mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
+-	else
++	else if (adev->powerplay.pp_funcs) {
++		if (amdgpu_emu_mode == 1)
++			mem_info->mem_clk_max = 0;
++		else
++			mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
++	} else
+ 		mem_info->mem_clk_max = 100;
+ }
+ 
+@@ -739,6 +744,11 @@ struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void)
+ 	return NULL;
+ }
+ 
++struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions(void)
++{
++	return NULL;
++}
++
+ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
+ 			      const struct kfd2kgd_calls *f2g)
+ {
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+index cec816566833..a344f37e48c0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+@@ -142,6 +142,7 @@ struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void);
+ struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void);
+ struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void);
+ struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void);
++struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions(void);
+ int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem,
+ 		uint64_t src_offset, struct kgd_mem *dst_mem,
+ 		uint64_t dest_offset, uint64_t size, struct dma_fence **f,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+new file mode 100644
+index 000000000000..39ffb078beb4
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+@@ -0,0 +1,975 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++#undef pr_fmt
++#define pr_fmt(fmt) "kfd2kgd: " fmt
++
++#include <linux/module.h>
++#include <linux/fdtable.h>
++#include <linux/uaccess.h>
++#include <linux/firmware.h>
++#include <linux/mmu_context.h>
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "amdgpu_amdkfd.h"
++#include "amdgpu_ucode.h"
++#include "soc15_hw_ip.h"
++#include "gc/gc_10_1_0_offset.h"
++#include "gc/gc_10_1_0_sh_mask.h"
++#include "navi10_enum.h"
++#include "athub/athub_2_0_0_offset.h"
++#include "athub/athub_2_0_0_sh_mask.h"
++#include "oss/osssys_5_0_0_offset.h"
++#include "oss/osssys_5_0_0_sh_mask.h"
++#include "soc15_common.h"
++#include "v10_structs.h"
++#include "nv.h"
++#include "nvd.h"
++
++enum hqd_dequeue_request_type {
++	NO_ACTION = 0,
++	DRAIN_PIPE,
++	RESET_WAVES,
++	SAVE_WAVES
++};
++
++/*
++ * Register access functions
++ */
++
++static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
++		uint32_t sh_mem_config,
++		uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
++		uint32_t sh_mem_bases);
++static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
++		unsigned int vmid);
++static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
++static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
++			uint32_t queue_id, uint32_t __user *wptr,
++			uint32_t wptr_shift, uint32_t wptr_mask,
++			struct mm_struct *mm);
++static int kgd_hqd_dump(struct kgd_dev *kgd,
++			uint32_t pipe_id, uint32_t queue_id,
++			uint32_t (**dump)[2], uint32_t *n_regs);
++static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
++			     uint32_t __user *wptr, struct mm_struct *mm);
++static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
++			     uint32_t engine_id, uint32_t queue_id,
++			     uint32_t (**dump)[2], uint32_t *n_regs);
++static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
++		uint32_t pipe_id, uint32_t queue_id);
++static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
++static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
++				enum kfd_preempt_type reset_type,
++				unsigned int utimeout, uint32_t pipe_id,
++				uint32_t queue_id);
++static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
++				unsigned int utimeout);
++#if 0
++static uint32_t get_watch_base_addr(struct amdgpu_device *adev);
++#endif
++static int kgd_address_watch_disable(struct kgd_dev *kgd);
++static int kgd_address_watch_execute(struct kgd_dev *kgd,
++					unsigned int watch_point_id,
++					uint32_t cntl_val,
++					uint32_t addr_hi,
++					uint32_t addr_lo);
++static int kgd_wave_control_execute(struct kgd_dev *kgd,
++					uint32_t gfx_index_val,
++					uint32_t sq_cmd);
++static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
++					unsigned int watch_point_id,
++					unsigned int reg_offset);
++
++static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
++		uint8_t vmid);
++static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
++		uint8_t vmid);
++static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
++		uint64_t page_table_base);
++static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
++static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
++
++/* Because of REG_GET_FIELD() being used, we put this function in the
++ * asic specific file.
++ */
++static int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
++		struct tile_config *config)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
++
++	config->gb_addr_config = adev->gfx.config.gb_addr_config;
++#if 0
++/* TODO - confirm REG_GET_FIELD x2, should be OK as is... but
++ * MC_ARB_RAMCFG register doesn't exist on Vega10 - initial amdgpu
++ * changes commented out related code, doing the same here for now but
++ * need to sync with Ken et al
++ */
++	config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
++				MC_ARB_RAMCFG, NOOFBANK);
++	config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
++				MC_ARB_RAMCFG, NOOFRANKS);
++#endif
++
++	config->tile_config_ptr = adev->gfx.config.tile_mode_array;
++	config->num_tile_configs =
++			ARRAY_SIZE(adev->gfx.config.tile_mode_array);
++	config->macro_tile_config_ptr =
++			adev->gfx.config.macrotile_mode_array;
++	config->num_macro_tile_configs =
++			ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
++
++	return 0;
++}
++
++static const struct kfd2kgd_calls kfd2kgd = {
++	.program_sh_mem_settings = kgd_program_sh_mem_settings,
++	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
++	.init_interrupts = kgd_init_interrupts,
++	.hqd_load = kgd_hqd_load,
++	.hqd_sdma_load = kgd_hqd_sdma_load,
++	.hqd_dump = kgd_hqd_dump,
++	.hqd_sdma_dump = kgd_hqd_sdma_dump,
++	.hqd_is_occupied = kgd_hqd_is_occupied,
++	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
++	.hqd_destroy = kgd_hqd_destroy,
++	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
++	.address_watch_disable = kgd_address_watch_disable,
++	.address_watch_execute = kgd_address_watch_execute,
++	.wave_control_execute = kgd_wave_control_execute,
++	.address_watch_get_offset = kgd_address_watch_get_offset,
++	.get_atc_vmid_pasid_mapping_pasid =
++			get_atc_vmid_pasid_mapping_pasid,
++	.get_atc_vmid_pasid_mapping_valid =
++			get_atc_vmid_pasid_mapping_valid,
++	.invalidate_tlbs = invalidate_tlbs,
++	.invalidate_tlbs_vmid = invalidate_tlbs_vmid,
++	.set_vm_context_page_table_base = set_vm_context_page_table_base,
++	.get_tile_config = amdgpu_amdkfd_get_tile_config,
++};
++
++struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions()
++{
++	return (struct kfd2kgd_calls *)&kfd2kgd;
++}
++
++static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
++{
++	return (struct amdgpu_device *)kgd;
++}
++
++static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
++			uint32_t queue, uint32_t vmid)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++
++	mutex_lock(&adev->srbm_mutex);
++	nv_grbm_select(adev, mec, pipe, queue, vmid);
++}
++
++static void unlock_srbm(struct kgd_dev *kgd)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++
++	nv_grbm_select(adev, 0, 0, 0, 0);
++	mutex_unlock(&adev->srbm_mutex);
++}
++
++static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
++				uint32_t queue_id)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++
++	uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
++	uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
++
++	lock_srbm(kgd, mec, pipe, queue_id, 0);
++}
++
++static uint32_t get_queue_mask(struct amdgpu_device *adev,
++			       uint32_t pipe_id, uint32_t queue_id)
++{
++	unsigned int bit = (pipe_id * adev->gfx.mec.num_queue_per_pipe +
++			    queue_id) & 31;
++
++	return ((uint32_t)1) << bit;
++}
++
++static void release_queue(struct kgd_dev *kgd)
++{
++	unlock_srbm(kgd);
++}
++
++static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
++					uint32_t sh_mem_config,
++					uint32_t sh_mem_ape1_base,
++					uint32_t sh_mem_ape1_limit,
++					uint32_t sh_mem_bases)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++
++	lock_srbm(kgd, 0, 0, 0, vmid);
++
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
++	/* APE1 no longer exists on GFX9 */
++
++	unlock_srbm(kgd);
++}
++
++static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
++					unsigned int vmid)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++
++	/*
++	 * We have to assume that there is no outstanding mapping.
++	 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
++	 * a mapping is in progress or because a mapping finished
++	 * and the SW cleared it.
++	 * So the protocol is to always wait & clear.
++	 */
++	uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
++			ATC_VMID0_PASID_MAPPING__VALID_MASK;
++
++	pr_debug("pasid 0x%x vmid %d, reg value %x\n", pasid, vmid, pasid_mapping);
++	/*
++	 * need to do this twice, once for gfx and once for mmhub
++	 * for ATC add 16 to VMID for mmhub, for IH different registers.
++	 * ATC_VMID0..15 registers are separate from ATC_VMID16..31.
++	 */
++
++	pr_debug("ATHUB, reg %x\n",SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid);
++	WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
++	       pasid_mapping);
++
++#if 0
++	/* TODO: uncomment this code when the hardware support is ready. */
++	while (!(RREG32(SOC15_REG_OFFSET(
++				ATHUB, 0,
++				mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) &
++		 (1U << vmid)))
++		cpu_relax();
++
++	pr_debug("ATHUB mapping update finished\n");
++	WREG32(SOC15_REG_OFFSET(ATHUB, 0,
++				mmATC_VMID_PASID_MAPPING_UPDATE_STATUS),
++	       1U << vmid);
++#endif
++
++	/* Mapping vmid to pasid also for IH block */
++	pr_debug("update mapping for IH block and mmhub");
++	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
++	       pasid_mapping);
++
++	return 0;
++}
++
++/* TODO - RING0 form of field is obsolete, seems to date back to SI
++ * but still works
++ */
++
++static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++	uint32_t mec;
++	uint32_t pipe;
++
++	mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
++	pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
++
++	lock_srbm(kgd, mec, pipe, 0, 0);
++
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
++		CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
++		CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
++
++	unlock_srbm(kgd);
++
++	return 0;
++}
++
++static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
++				unsigned int engine_id,
++				unsigned int queue_id)
++{
++	uint32_t base[2] = {
++		SOC15_REG_OFFSET(SDMA0, 0,
++				 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
++		/* On gfx10, mmSDMA1_xxx registers are defined NOT based
++		 * on SDMA1 base address (dw 0x1860) but based on SDMA0
++		 * base address (dw 0x1260). Therefore use mmSDMA0_RLC0_RB_CNTL
++		 * instead of mmSDMA1_RLC0_RB_CNTL for the base address calc
++		 * below
++		 */
++		SOC15_REG_OFFSET(SDMA1, 0,
++				 mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL
++	};
++	uint32_t retval;
++
++	retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL -
++					       mmSDMA0_RLC0_RB_CNTL);
++
++	pr_debug("sdma base address: 0x%x\n", retval);
++
++	return retval;
++}
++
++#if 0
++static uint32_t get_watch_base_addr(struct amdgpu_device *adev)
++{
++	uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) -
++			mmTCP_WATCH0_ADDR_H;
++
++	pr_debug("kfd: reg watch base address: 0x%x\n", retval);
++
++	return retval;
++}
++#endif
++
++static inline struct v10_compute_mqd *get_mqd(void *mqd)
++{
++	return (struct v10_compute_mqd *)mqd;
++}
++
++static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd)
++{
++	return (struct v10_sdma_mqd *)mqd;
++}
++
++static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
++			uint32_t queue_id, uint32_t __user *wptr,
++			uint32_t wptr_shift, uint32_t wptr_mask,
++			struct mm_struct *mm)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++	struct v10_compute_mqd *m;
++	uint32_t *mqd_hqd;
++	uint32_t reg, hqd_base, data;
++
++	m = get_mqd(mqd);
++
++	pr_debug("Load hqd of pipe %d queue %d\n", pipe_id, queue_id);
++	acquire_queue(kgd, pipe_id, queue_id);
++
++	/* HIQ is set during driver init period with vmid set to 0*/
++	if (m->cp_hqd_vmid == 0) {
++		uint32_t value, mec, pipe;
++
++		mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
++		pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
++
++		pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
++			mec, pipe, queue_id);
++		value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS));
++		value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
++			((mec << 5) | (pipe << 3) | queue_id | 0x80));
++		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value);
++	}
++
++	/* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
++	mqd_hqd = &m->cp_mqd_base_addr_lo;
++	hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
++
++	for (reg = hqd_base;
++	     reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
++		WREG32(reg, mqd_hqd[reg - hqd_base]);
++
++
++	/* Activate doorbell logic before triggering WPTR poll. */
++	data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
++			     CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
++
++	if (wptr) {
++		/* Don't read wptr with get_user because the user
++		 * context may not be accessible (if this function
++		 * runs in a work queue). Instead trigger a one-shot
++		 * polling read from memory in the CP. This assumes
++		 * that wptr is GPU-accessible in the queue's VMID via
++		 * ATC or SVM. WPTR==RPTR before starting the poll so
++		 * the CP starts fetching new commands from the right
++		 * place.
++		 *
++		 * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit
++		 * tricky. Assume that the queue didn't overflow. The
++		 * number of valid bits in the 32-bit RPTR depends on
++		 * the queue size. The remaining bits are taken from
++		 * the saved 64-bit WPTR. If the WPTR wrapped, add the
++		 * queue size.
++		 */
++		uint32_t queue_size =
++			2 << REG_GET_FIELD(m->cp_hqd_pq_control,
++					   CP_HQD_PQ_CONTROL, QUEUE_SIZE);
++		uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1);
++
++		if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr)
++			guessed_wptr += queue_size;
++		guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
++		guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
++
++		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
++		       lower_32_bits(guessed_wptr));
++		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
++		       upper_32_bits(guessed_wptr));
++		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
++		       lower_32_bits((uint64_t)wptr));
++		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
++		       upper_32_bits((uint64_t)wptr));
++		pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__, get_queue_mask(adev, pipe_id, queue_id));
++		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
++		       get_queue_mask(adev, pipe_id, queue_id));
++	}
++
++	/* Start the EOP fetcher */
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
++	       REG_SET_FIELD(m->cp_hqd_eop_rptr,
++			     CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
++
++	data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
++
++	release_queue(kgd);
++
++	return 0;
++}
++
++static int kgd_hqd_dump(struct kgd_dev *kgd,
++			uint32_t pipe_id, uint32_t queue_id,
++			uint32_t (**dump)[2], uint32_t *n_regs)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++	uint32_t i = 0, reg;
++#define HQD_N_REGS 56
++#define DUMP_REG(addr) do {				\
++		if (WARN_ON_ONCE(i >= HQD_N_REGS))	\
++			break;				\
++		(*dump)[i][0] = (addr) << 2;		\
++		(*dump)[i++][1] = RREG32(addr);		\
++	} while (0)
++
++	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
++	if (*dump == NULL)
++		return -ENOMEM;
++
++	acquire_queue(kgd, pipe_id, queue_id);
++
++	for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
++	     reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
++		DUMP_REG(reg);
++
++	release_queue(kgd);
++
++	WARN_ON_ONCE(i != HQD_N_REGS);
++	*n_regs = i;
++
++	return 0;
++}
++
++static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
++			     uint32_t __user *wptr, struct mm_struct *mm)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++	struct v10_sdma_mqd *m;
++	uint32_t sdma_base_addr, sdmax_gfx_context_cntl;
++	unsigned long end_jiffies;
++	uint32_t data;
++	uint64_t data64;
++	uint64_t __user *wptr64 = (uint64_t __user *)wptr;
++
++	m = get_sdma_mqd(mqd);
++	sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
++					    m->sdma_queue_id);
++	pr_debug("sdma load base addr %x for engine %d, queue %d\n", sdma_base_addr, m->sdma_engine_id, m->sdma_queue_id);
++	sdmax_gfx_context_cntl = m->sdma_engine_id ?
++		SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_CONTEXT_CNTL) :
++		SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_CONTEXT_CNTL);
++
++	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
++		m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
++
++	end_jiffies = msecs_to_jiffies(2000) + jiffies;
++	while (true) {
++		data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
++		if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
++			break;
++		if (time_after(jiffies, end_jiffies))
++			return -ETIME;
++		usleep_range(500, 1000);
++	}
++	data = RREG32(sdmax_gfx_context_cntl);
++	data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
++			     RESUME_CTX, 0);
++	WREG32(sdmax_gfx_context_cntl, data);
++
++	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
++	       m->sdmax_rlcx_doorbell_offset);
++
++	data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
++			     ENABLE, 1);
++	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
++	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
++	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI,
++				m->sdmax_rlcx_rb_rptr_hi);
++
++	WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
++	if (read_user_wptr(mm, wptr64, data64)) {
++		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
++		       lower_32_bits(data64));
++		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
++		       upper_32_bits(data64));
++	} else {
++		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
++		       m->sdmax_rlcx_rb_rptr);
++		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
++		       m->sdmax_rlcx_rb_rptr_hi);
++	}
++	WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
++
++	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
++	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
++			m->sdmax_rlcx_rb_base_hi);
++	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
++			m->sdmax_rlcx_rb_rptr_addr_lo);
++	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
++			m->sdmax_rlcx_rb_rptr_addr_hi);
++
++	data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
++			     RB_ENABLE, 1);
++	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
++
++	return 0;
++}
++
++static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
++			     uint32_t engine_id, uint32_t queue_id,
++			     uint32_t (**dump)[2], uint32_t *n_regs)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++	uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id);
++	uint32_t i = 0, reg;
++#undef HQD_N_REGS
++#define HQD_N_REGS (19+6+7+10)
++
++	pr_debug("sdma dump engine id %d queue_id %d\n", engine_id, queue_id);
++	pr_debug("sdma base addr %x\n", sdma_base_addr);
++
++	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
++	if (*dump == NULL)
++		return -ENOMEM;
++
++	for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
++		DUMP_REG(sdma_base_addr + reg);
++	for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
++		DUMP_REG(sdma_base_addr + reg);
++	for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
++	     reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
++		DUMP_REG(sdma_base_addr + reg);
++	for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
++	     reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
++		DUMP_REG(sdma_base_addr + reg);
++
++	WARN_ON_ONCE(i != HQD_N_REGS);
++	*n_regs = i;
++
++	return 0;
++}
++
++static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
++				uint32_t pipe_id, uint32_t queue_id)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++	uint32_t act;
++	bool retval = false;
++	uint32_t low, high;
++
++	acquire_queue(kgd, pipe_id, queue_id);
++	act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
++	if (act) {
++		low = lower_32_bits(queue_address >> 8);
++		high = upper_32_bits(queue_address >> 8);
++
++		if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
++		   high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
++			retval = true;
++	}
++	release_queue(kgd);
++	return retval;
++}
++
++static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++	struct v10_sdma_mqd *m;
++	uint32_t sdma_base_addr;
++	uint32_t sdma_rlc_rb_cntl;
++
++	m = get_sdma_mqd(mqd);
++	sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
++					    m->sdma_queue_id);
++
++	sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
++
++	if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
++		return true;
++
++	return false;
++}
++
++static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
++				enum kfd_preempt_type reset_type,
++				unsigned int utimeout, uint32_t pipe_id,
++				uint32_t queue_id)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++	enum hqd_dequeue_request_type type;
++	unsigned long end_jiffies;
++	uint32_t temp;
++	struct v10_compute_mqd *m = get_mqd(mqd);
++
++#if 0
++	unsigned long flags;
++	int retry;
++#endif
++
++	acquire_queue(kgd, pipe_id, queue_id);
++
++	if (m->cp_hqd_vmid == 0)
++		WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0);
++
++	switch (reset_type) {
++	case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
++		type = DRAIN_PIPE;
++		break;
++	case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
++		type = RESET_WAVES;
++		break;
++	default:
++		type = DRAIN_PIPE;
++		break;
++	}
++
++#if 0 /* Is this still needed? */
++	/* Workaround: If IQ timer is active and the wait time is close to or
++	 * equal to 0, dequeueing is not safe. Wait until either the wait time
++	 * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is
++	 * cleared before continuing. Also, ensure wait times are set to at
++	 * least 0x3.
++	 */
++	local_irq_save(flags);
++	preempt_disable();
++	retry = 5000; /* wait for 500 usecs at maximum */
++	while (true) {
++		temp = RREG32(mmCP_HQD_IQ_TIMER);
++		if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
++			pr_debug("HW is processing IQ\n");
++			goto loop;
++		}
++		if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
++			if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
++					== 3) /* SEM-rearm is safe */
++				break;
++			/* Wait time 3 is safe for CP, but our MMIO read/write
++			 * time is close to 1 microsecond, so check for 10 to
++			 * leave more buffer room
++			 */
++			if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
++					>= 10)
++				break;
++			pr_debug("IQ timer is active\n");
++		} else
++			break;
++loop:
++		if (!retry) {
++			pr_err("CP HQD IQ timer status time out\n");
++			break;
++		}
++		ndelay(100);
++		--retry;
++	}
++	retry = 1000;
++	while (true) {
++		temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
++		if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK))
++			break;
++		pr_debug("Dequeue request is pending\n");
++
++		if (!retry) {
++			pr_err("CP HQD dequeue request time out\n");
++			break;
++		}
++		ndelay(100);
++		--retry;
++	}
++	local_irq_restore(flags);
++	preempt_enable();
++#endif
++
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);
++
++	end_jiffies = (utimeout * HZ / 1000) + jiffies;
++	while (true) {
++		temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
++		if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
++			break;
++		if (time_after(jiffies, end_jiffies)) {
++			pr_err("cp queue preemption time out.\n");
++			release_queue(kgd);
++			return -ETIME;
++		}
++		usleep_range(500, 1000);
++	}
++
++	release_queue(kgd);
++	return 0;
++}
++
++static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
++				unsigned int utimeout)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++	struct v10_sdma_mqd *m;
++	uint32_t sdma_base_addr;
++	uint32_t temp;
++	unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
++
++	m = get_sdma_mqd(mqd);
++	sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
++					    m->sdma_queue_id);
++
++	temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
++	temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
++	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
++
++	while (true) {
++		temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
++		if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
++			break;
++		if (time_after(jiffies, end_jiffies))
++			return -ETIME;
++		usleep_range(500, 1000);
++	}
++
++	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
++	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
++		RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
++		SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
++
++	m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
++	m->sdmax_rlcx_rb_rptr_hi =
++		RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI);
++
++	return 0;
++}
++
++static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
++							uint8_t vmid)
++{
++	uint32_t reg;
++	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
++
++	reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
++		     + vmid);
++	return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
++}
++
++static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
++								uint8_t vmid)
++{
++	uint32_t reg;
++	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
++
++	reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
++		     + vmid);
++	return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
++}
++
++static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
++	uint32_t req = (1 << vmid) |
++		(0 << GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT) |/* legacy */
++		GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK |
++		GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK |
++		GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK |
++		GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK |
++		GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK;
++
++	mutex_lock(&adev->srbm_mutex);
++
++	/* Use light weight invalidation.
++	 *
++	 * TODO 1: agree on the right set of invalidation registers for
++	 * KFD use. Use the last one for now. Invalidate only GCHUB as
++	 * SDMA is now moved to GCHUB
++	 *
++	 * TODO 2: support range-based invalidation, requires kfg2kgd
++	 * interface change
++	 */
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32),
++				0xffffffff);
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32),
++				0x0000001f);
++
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ), req);
++
++	while (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK)) &
++					(1 << vmid)))
++		cpu_relax();
++
++	mutex_unlock(&adev->srbm_mutex);
++}
++
++static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid)
++{
++	signed long r;
++	uint32_t seq;
++	struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
++
++	spin_lock(&adev->gfx.kiq.ring_lock);
++	amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/
++	amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
++	amdgpu_ring_write(ring,
++			PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
++			PACKET3_INVALIDATE_TLBS_PASID(pasid));
++	amdgpu_fence_emit_polling(ring, &seq);
++	amdgpu_ring_commit(ring);
++	spin_unlock(&adev->gfx.kiq.ring_lock);
++
++	r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
++	if (r < 1) {
++		DRM_ERROR("wait for kiq fence error: %ld.\n", r);
++		return -ETIME;
++	}
++
++	return 0;
++}
++
++static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
++	int vmid;
++	struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
++
++	if (amdgpu_emu_mode == 0 && ring->sched.ready)
++		return invalidate_tlbs_with_kiq(adev, pasid);
++
++	for (vmid = 0; vmid < 16; vmid++) {
++		if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
++			continue;
++		if (get_atc_vmid_pasid_mapping_valid(kgd, vmid)) {
++			if (get_atc_vmid_pasid_mapping_pasid(kgd, vmid)
++				== pasid) {
++				write_vmid_invalidate_request(kgd, vmid);
++				break;
++			}
++		}
++	}
++
++	return 0;
++}
++
++static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
++
++	if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
++		pr_err("non kfd vmid %d\n", vmid);
++		return 0;
++	}
++
++	write_vmid_invalidate_request(kgd, vmid);
++	return 0;
++}
++
++static int kgd_address_watch_disable(struct kgd_dev *kgd)
++{
++	return 0;
++}
++
++static int kgd_address_watch_execute(struct kgd_dev *kgd,
++					unsigned int watch_point_id,
++					uint32_t cntl_val,
++					uint32_t addr_hi,
++					uint32_t addr_lo)
++{
++	return 0;
++}
++
++static int kgd_wave_control_execute(struct kgd_dev *kgd,
++					uint32_t gfx_index_val,
++					uint32_t sq_cmd)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++	uint32_t data = 0;
++
++	mutex_lock(&adev->grbm_idx_mutex);
++
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val);
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
++
++	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
++		INSTANCE_BROADCAST_WRITES, 1);
++	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
++		SA_BROADCAST_WRITES, 1);
++	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
++		SE_BROADCAST_WRITES, 1);
++
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);
++	mutex_unlock(&adev->grbm_idx_mutex);
++
++	return 0;
++}
++
++static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
++					unsigned int watch_point_id,
++					unsigned int reg_offset)
++{
++	return 0;
++}
++
++static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
++		uint64_t page_table_base)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++	uint64_t base = page_table_base | AMDGPU_PTE_VALID;
++
++	if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
++		pr_err("trying to set page table base for wrong VMID %u\n",
++		       vmid);
++		return;
++	}
++
++	/* TODO: take advantage of per-process address space size. For
++	 * now, all processes share the same address space size, like
++	 * on GFX8 and older.
++	 */
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0);
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0);
++
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2),
++			lower_32_bits(adev->vm_manager.max_pfn - 1));
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2),
++			upper_32_bits(adev->vm_manager.max_pfn - 1));
++
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base));
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base));
++}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3000-drm-amd-powerplay-change-sysfs-pp_dpm_xxx-format-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3000-drm-amd-powerplay-change-sysfs-pp_dpm_xxx-format-for.patch
new file mode 100644
index 00000000..ba4f0c8a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3000-drm-amd-powerplay-change-sysfs-pp_dpm_xxx-format-for.patch
@@ -0,0 +1,103 @@
+From 040f55650a185d0dfa7915093f24c4d0b55d00b4 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Thu, 18 Jul 2019 15:46:55 +0800
+Subject: [PATCH 3000/4256] drm/amd/powerplay: change sysfs pp_dpm_xxx format
+ for navi10
+
+v2:
+set average clock value on level 1 when current clock equal
+min or max clock (fine grained dpm support).
+
+the navi10 gfxclk (sclk) support fine grained DPM,
+so use level 1 to show current dpm freq in sysfs pp_dpm_xxx
+
+Change-Id: I730bfdedbbcf118f781057be6b2620f047c5d57b
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 47 +++++++++++++++++++---
+ 1 file changed, 41 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 0ab02efcbc83..e44041a25e64 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -646,11 +646,26 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
+ 	return ret;
+ }
+ 
++static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
++{
++	PPTable_t *pptable = smu->smu_table.driver_pptable;
++	DpmDescriptor_t *dpm_desc = NULL;
++	uint32_t clk_index = 0;
++
++	clk_index = smu_clk_get_index(smu, clk_type);
++	dpm_desc = &pptable->DpmDescriptor[clk_index];
++
++	/* 0 - Fine grained DPM, 1 - Discrete DPM */
++	return dpm_desc->SnapToDiscrete == 0 ? true : false;
++}
++
+ static int navi10_print_clk_levels(struct smu_context *smu,
+ 			enum smu_clk_type clk_type, char *buf)
+ {
+ 	int i, size = 0, ret = 0;
+ 	uint32_t cur_value = 0, value = 0, count = 0;
++	uint32_t freq_values[3] = {0};
++	uint32_t mark_index = 0;
+ 
+ 	switch (clk_type) {
+ 	case SMU_GFXCLK:
+@@ -663,22 +678,42 @@ static int navi10_print_clk_levels(struct smu_context *smu,
+ 		ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
+ 		if (ret)
+ 			return size;
++
+ 		/* 10KHz -> MHz */
+ 		cur_value = cur_value / 100;
+ 
+-		size += sprintf(buf, "current clk: %uMhz\n", cur_value);
+-
+ 		ret = smu_get_dpm_level_count(smu, clk_type, &count);
+ 		if (ret)
+ 			return size;
+ 
+-		for (i = 0; i < count; i++) {
+-			ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
++		if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
++			for (i = 0; i < count; i++) {
++				ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
++				if (ret)
++					return size;
++
++				size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
++						cur_value == value ? "*" : "");
++			}
++		} else {
++			ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
++			if (ret)
++				return size;
++			ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
+ 			if (ret)
+ 				return size;
+ 
+-			size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
+-					cur_value == value ? "*" : "");
++			freq_values[1] = cur_value;
++			mark_index = cur_value == freq_values[0] ? 0 :
++				     cur_value == freq_values[2] ? 2 : 1;
++			if (mark_index != 1)
++				freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
++
++			for (i = 0; i < 3; i++) {
++				size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
++						i == mark_index ? "*" : "");
++			}
++
+ 		}
+ 		break;
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3001-drm-amdgpu-do-not-create-ras-debugfs-sysfs-node-for-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3001-drm-amdgpu-do-not-create-ras-debugfs-sysfs-node-for-.patch
new file mode 100644
index 00000000..164c46f7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3001-drm-amdgpu-do-not-create-ras-debugfs-sysfs-node-for-.patch
@@ -0,0 +1,36 @@
+From 92c190bcf2f6ddb2cf67528c1e617932b085c2eb Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 18 Jul 2019 12:49:15 +0800
+Subject: [PATCH 3001/4256] drm/amdgpu: do not create ras debugfs/sysfs node
+ for ASICs that don't have ras ability
+
+driver shouldn't init any ras debugfs/sysfs node for ASICs that don't have ras
+hardware ability
+
+Change-Id: I7a84814b4fc79375e4daab2ba4fec6b35e53b9a6
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 614116c7036a..cba2c0f90c77 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1555,6 +1555,12 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
+ 
+ 	amdgpu_ras_check_supported(adev, &con->hw_supported,
+ 			&con->supported);
++	if (!con->hw_supported) {
++		amdgpu_ras_set_context(adev, NULL);
++		kfree(con);
++		return 0;
++	}
++
+ 	con->features = 0;
+ 	INIT_LIST_HEAD(&con->head);
+ 	/* Might need get this flag from vbios. */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3002-drm-amdgpu-disable-GFX-RAS-by-default.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3002-drm-amdgpu-disable-GFX-RAS-by-default.patch
new file mode 100644
index 00000000..fcd7e70b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3002-drm-amdgpu-disable-GFX-RAS-by-default.patch
@@ -0,0 +1,33 @@
+From 30dd8c47d1d970a348c9a953a58d3ec8e8c2e3d3 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 18 Jul 2019 12:52:56 +0800
+Subject: [PATCH 3002/4256] drm/amdgpu: disable GFX RAS by default
+
+GFX RAS has not been stablized yet. disable GFX ras until
+it is fully funcitonal.
+
+Change-Id: I6e97f28153c0a558816bcb00e37378bd2c7e482f
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 0f1a6824803e..e7c6f9b6e4ba 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -150,8 +150,8 @@ int amdgpu_noretry;
+ struct amdgpu_mgpu_info mgpu_info = {
+ 	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
+ };
+-int amdgpu_ras_enable;
+-uint amdgpu_ras_mask = 0xffffffff;
++int amdgpu_ras_enable = -1;
++uint amdgpu_ras_mask = 0xfffffffb;
+ 
+ /**
+  * DOC: vramlimit (int)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3003-drm-amdgpu-only-allow-error-injection-to-UMC-IP-bloc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3003-drm-amdgpu-only-allow-error-injection-to-UMC-IP-bloc.patch
new file mode 100644
index 00000000..d38caa75
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3003-drm-amdgpu-only-allow-error-injection-to-UMC-IP-bloc.patch
@@ -0,0 +1,36 @@
+From 6b125996bcfeecb1c72fe0eecdd6ca2d699a9631 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 18 Jul 2019 13:59:38 +0800
+Subject: [PATCH 3003/4256] drm/amdgpu: only allow error injection to UMC IP
+ block
+
+error injection to other IP blocks (except UMC) will be enabled
+until RAS feature stablize on those IP blocks
+
+Change-Id: I871333d717ec2920a6f4e656feb90cc87eb7e834
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index cba2c0f90c77..403ef3b7b198 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -687,6 +687,12 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev,
+ 	if (!obj)
+ 		return -EINVAL;
+ 
++	if (block_info.block_id != TA_RAS_BLOCK__UMC) {
++		DRM_INFO("%s error injection is not supported yet\n",
++			 ras_block_str(info->head.block));
++		return -EINVAL;
++	}
++
+ 	ret = psp_ras_trigger_error(&adev->psp, &block_info);
+ 	if (ret)
+ 		DRM_ERROR("RAS ERROR: inject %s error failed ret %d\n",
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3004-drm-amdgpu-drop-ras-self-test.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3004-drm-amdgpu-drop-ras-self-test.patch
new file mode 100644
index 00000000..eaf6d2d6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3004-drm-amdgpu-drop-ras-self-test.patch
@@ -0,0 +1,44 @@
+From 6cf48a51b13fffa12d0c14e3115e6e35489298b5 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 18 Jul 2019 16:03:46 +0800
+Subject: [PATCH 3004/4256] drm/amdgpu: drop ras self test
+
+this function is not needed any more. error injection is
+the only way to validate ras but it can't be executed in
+amdgpu_ras_init, where gpu is even not initialized
+
+Change-Id: Ieb583a5b217f6fc8c766e49f82384a37258c72e3
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 -------
+ 1 file changed, 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 403ef3b7b198..b45aaf04a574 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -134,11 +134,6 @@ static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev,
+ static int amdgpu_ras_release_vram(struct amdgpu_device *adev,
+ 		struct amdgpu_bo **bo_ptr);
+ 
+-static void amdgpu_ras_self_test(struct amdgpu_device *adev)
+-{
+-	/* TODO */
+-}
+-
+ static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
+ 					size_t size, loff_t *pos)
+ {
+@@ -1580,8 +1575,6 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
+ 	if (amdgpu_ras_fs_init(adev))
+ 		goto fs_out;
+ 
+-	amdgpu_ras_self_test(adev);
+-
+ 	DRM_INFO("RAS INFO: ras initialized successfully, "
+ 			"hardware ability[%x] ras_mask[%x]\n",
+ 			con->hw_supported, con->supported);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3005-drm-amd-powerplay-custom-peak-clock-freq-for-navi10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3005-drm-amd-powerplay-custom-peak-clock-freq-for-navi10.patch
new file mode 100644
index 00000000..956b1644
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3005-drm-amd-powerplay-custom-peak-clock-freq-for-navi10.patch
@@ -0,0 +1,239 @@
+From 0dc8137e3fb92d3597459d77c8d83d5cf3281d83 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Fri, 19 Jul 2019 11:39:21 +0800
+Subject: [PATCH 3005/4256] drm/amd/powerplay: custom peak clock freq for
+ navi10
+
+v2:
+add function smu_default_set_performance_level as default dpm level handler.
+change function name smu_set_performance_level to smu_asic_set_performance_level
+
+v1:
+1.NAVI10_PEAK_SCLK_XTX    1830 Mhz
+2.NAVI10_PEAK_SCLK_XT     1755 Mhz
+3.NAVI10_PEAK_SCLK_XL     1625 Mhz
+
+Change-Id: Ic63bc85da1b932f862d8ec8b9dc02001b8a42255
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Jack Gui <Jack.Gui@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 73 ++++++++++---------
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  4 +
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 55 ++++++++++++++
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.h    |  4 +
+ 4 files changed, 103 insertions(+), 33 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 5d5664fb1a84..8dc755d3aaa3 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1369,13 +1369,49 @@ static int smu_enable_umd_pstate(void *handle,
+ 	return 0;
+ }
+ 
++static int smu_default_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
++{
++	int ret = 0;
++	uint32_t sclk_mask, mclk_mask, soc_mask;
++
++	switch (level) {
++	case AMD_DPM_FORCED_LEVEL_HIGH:
++		ret = smu_force_dpm_limit_value(smu, true);
++		break;
++	case AMD_DPM_FORCED_LEVEL_LOW:
++		ret = smu_force_dpm_limit_value(smu, false);
++		break;
++	case AMD_DPM_FORCED_LEVEL_AUTO:
++	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
++		ret = smu_unforce_dpm_levels(smu);
++		break;
++	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
++	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
++	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
++		ret = smu_get_profiling_clk_mask(smu, level,
++						 &sclk_mask,
++						 &mclk_mask,
++						 &soc_mask);
++		if (ret)
++			return ret;
++		smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
++		smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
++		smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
++		break;
++	case AMD_DPM_FORCED_LEVEL_MANUAL:
++	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
++	default:
++		break;
++	}
++	return ret;
++}
++
+ int smu_adjust_power_state_dynamic(struct smu_context *smu,
+ 				   enum amd_dpm_forced_level level,
+ 				   bool skip_display_settings)
+ {
+ 	int ret = 0;
+ 	int index = 0;
+-	uint32_t sclk_mask, mclk_mask, soc_mask;
+ 	long workload;
+ 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+ 
+@@ -1406,39 +1442,10 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
+ 	}
+ 
+ 	if (smu_dpm_ctx->dpm_level != level) {
+-		switch (level) {
+-		case AMD_DPM_FORCED_LEVEL_HIGH:
+-			ret = smu_force_dpm_limit_value(smu, true);
+-			break;
+-		case AMD_DPM_FORCED_LEVEL_LOW:
+-			ret = smu_force_dpm_limit_value(smu, false);
+-			break;
+-
+-		case AMD_DPM_FORCED_LEVEL_AUTO:
+-		case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
+-			ret = smu_unforce_dpm_levels(smu);
+-			break;
+-
+-		case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+-		case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
+-		case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
+-			ret = smu_get_profiling_clk_mask(smu, level,
+-							 &sclk_mask,
+-							 &mclk_mask,
+-							 &soc_mask);
+-			if (ret)
+-				return ret;
+-			smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
+-			smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
+-			smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
+-			break;
+-
+-		case AMD_DPM_FORCED_LEVEL_MANUAL:
+-		case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
+-		default:
+-			break;
++		ret = smu_asic_set_performance_level(smu, level);
++		if (ret) {
++			ret = smu_default_set_performance_level(smu, level);
+ 		}
+-
+ 		if (!ret)
+ 			smu_dpm_ctx->dpm_level = level;
+ 	}
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 514d31518853..34093ddca105 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -631,6 +631,7 @@ struct pptable_funcs {
+ 	int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
+ 	int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
+ 	int (*set_default_od_settings)(struct smu_context *smu, bool initialize);
++	int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
+ };
+ 
+ struct smu_funcs
+@@ -928,6 +929,9 @@ struct smu_funcs
+ 	((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0)
+ #define smu_baco_reset(smu) \
+ 	((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
++#define smu_asic_set_performance_level(smu, level) \
++	((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
++
+ 
+ extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
+ 				   uint16_t *size, uint8_t *frev, uint8_t *crev,
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index e44041a25e64..a3c82867e431 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1590,6 +1590,60 @@ static int navi10_set_ppfeature_status(struct smu_context *smu,
+ 	return 0;
+ }
+ 
++static int navi10_set_peak_clock_by_device(struct smu_context *smu)
++{
++	struct amdgpu_device *adev = smu->adev;
++	int ret = 0;
++	uint32_t sclk_freq = 0, uclk_freq = 0;
++	uint32_t uclk_level = 0;
++
++	switch (adev->rev_id) {
++	case 0xf0: /* XTX */
++	case 0xc0:
++		sclk_freq = NAVI10_PEAK_SCLK_XTX;
++		break;
++	case 0xf1: /* XT */
++	case 0xc1:
++		sclk_freq = NAVI10_PEAK_SCLK_XT;
++		break;
++	default: /* XL */
++		sclk_freq = NAVI10_PEAK_SCLK_XL;
++		break;
++	}
++
++	ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level);
++	if (ret)
++		return ret;
++	ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, uclk_level - 1, &uclk_freq);
++	if (ret)
++		return ret;
++
++	ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
++	if (ret)
++		return ret;
++	ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
++	if (ret)
++		return ret;
++
++	return ret;
++}
++
++static int navi10_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
++{
++	int ret = 0;
++
++	switch (level) {
++	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
++		ret = navi10_set_peak_clock_by_device(smu);
++		break;
++	default:
++		ret = -EINVAL;
++		break;
++	}
++
++	return ret;
++}
++
+ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.tables_init = navi10_tables_init,
+ 	.alloc_dpm_context = navi10_allocate_dpm_context,
+@@ -1625,6 +1679,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.get_uclk_dpm_states = navi10_get_uclk_dpm_states,
+ 	.get_ppfeature_status = navi10_get_ppfeature_status,
+ 	.set_ppfeature_status = navi10_set_ppfeature_status,
++	.set_performance_level = navi10_set_performance_level,
+ };
+ 
+ void navi10_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+index 957288e22f47..620ff17c2fef 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+@@ -23,6 +23,10 @@
+ #ifndef __NAVI10_PPT_H__
+ #define __NAVI10_PPT_H__
+ 
++#define NAVI10_PEAK_SCLK_XTX		(1830)
++#define NAVI10_PEAK_SCLK_XT  		(1755)
++#define NAVI10_PEAK_SCLK_XL  		(1625)
++
+ extern void navi10_set_ppt_funcs(struct smu_context *smu);
+ 
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3006-drm-amd-powerplay-remove-redundancy-debug-log-in-smu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3006-drm-amd-powerplay-remove-redundancy-debug-log-in-smu.patch
new file mode 100644
index 00000000..7273154e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3006-drm-amd-powerplay-remove-redundancy-debug-log-in-smu.patch
@@ -0,0 +1,148 @@
+From 952aa9bc2634d153c97c06bd9d7e86d02cb4e393 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Fri, 19 Jul 2019 16:06:29 +0800
+Subject: [PATCH 3006/4256] drm/amd/powerplay: remove redundancy debug log in
+ smu
+
+remove redundacy debug log in smu.
+eg:
+[ 6897.969447] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
+[ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
+[ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
+[ 6899.024114] amdgpu: [powerplay] Unsupported SMU message: 38
+[ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
+[ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
+[ 6899.024152] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
+[ 6900.078296] amdgpu: [powerplay] Unsupported SMU message: 38
+[ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
+[ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
+[ 6900.078333] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
+[ 6901.133230] amdgpu: [powerplay] Unsupported SMU message: 38
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 1 -
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 6 ------
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 6 ------
+ 3 files changed, 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 8dc755d3aaa3..f67206c607ca 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -237,7 +237,6 @@ bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
+ 	}
+ 
+ 	if(!smu_feature_is_enabled(smu, feature_id)) {
+-		pr_warn("smu %d clk dpm feature %d is not enabled\n", clk_type, feature_id);
+ 		return false;
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index a3c82867e431..46e2913e4af4 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -217,7 +217,6 @@ static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+ 
+ 	mapping = navi10_message_map[index];
+ 	if (!(mapping.valid_mapping)) {
+-		pr_warn("Unsupported SMU message: %d\n", index);
+ 		return -EINVAL;
+ 	}
+ 
+@@ -233,7 +232,6 @@ static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
+ 
+ 	mapping = navi10_clk_map[index];
+ 	if (!(mapping.valid_mapping)) {
+-		pr_warn("Unsupported SMU clock: %d\n", index);
+ 		return -EINVAL;
+ 	}
+ 
+@@ -249,7 +247,6 @@ static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
+ 
+ 	mapping = navi10_feature_mask_map[index];
+ 	if (!(mapping.valid_mapping)) {
+-		pr_warn("Unsupported SMU feature: %d\n", index);
+ 		return -EINVAL;
+ 	}
+ 
+@@ -265,7 +262,6 @@ static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
+ 
+ 	mapping = navi10_table_map[index];
+ 	if (!(mapping.valid_mapping)) {
+-		pr_warn("Unsupported SMU table: %d\n", index);
+ 		return -EINVAL;
+ 	}
+ 
+@@ -281,7 +277,6 @@ static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
+ 
+ 	mapping = navi10_pwr_src_map[index];
+ 	if (!(mapping.valid_mapping)) {
+-		pr_warn("Unsupported power source: %d\n", index);
+ 		return -EINVAL;
+ 	}
+ 
+@@ -298,7 +293,6 @@ static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_P
+ 
+ 	mapping = navi10_workload_map[profile];
+ 	if (!(mapping.valid_mapping)) {
+-		pr_warn("Unsupported workload: %d\n", (int)profile);
+ 		return -EINVAL;
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index ff74ac76805d..bcd0efaf7bbd 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -232,7 +232,6 @@ static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index)
+ 
+ 	mapping = vega20_table_map[index];
+ 	if (!(mapping.valid_mapping)) {
+-		pr_warn("Unsupported SMU table: %d\n", index);
+ 		return -EINVAL;
+ 	}
+ 
+@@ -248,7 +247,6 @@ static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index)
+ 
+ 	mapping = vega20_pwr_src_map[index];
+ 	if (!(mapping.valid_mapping)) {
+-		pr_warn("Unsupported power source: %d\n", index);
+ 		return -EINVAL;
+ 	}
+ 
+@@ -264,7 +262,6 @@ static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index)
+ 
+ 	mapping = vega20_feature_mask_map[index];
+ 	if (!(mapping.valid_mapping)) {
+-		pr_warn("Unsupported SMU feature: %d\n", index);
+ 		return -EINVAL;
+ 	}
+ 
+@@ -280,7 +277,6 @@ static int vega20_get_smu_clk_index(struct smu_context *smc, uint32_t index)
+ 
+ 	mapping = vega20_clk_map[index];
+ 	if (!(mapping.valid_mapping)) {
+-		pr_warn("Unsupported SMU clock: %d\n", index);
+ 		return -EINVAL;
+ 	}
+ 
+@@ -296,7 +292,6 @@ static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+ 
+ 	mapping = vega20_message_map[index];
+ 	if (!(mapping.valid_mapping)) {
+-		pr_warn("Unsupported SMU message: %d\n", index);
+ 		return -EINVAL;
+ 	}
+ 
+@@ -312,7 +307,6 @@ static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_P
+ 
+ 	mapping = vega20_workload_map[profile];
+ 	if (!(mapping.valid_mapping)) {
+-		pr_warn("Unsupported SMU workload: %d\n", (int)profile);
+ 		return -EINVAL;
+ 	}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3007-drm-amdgpu-set-sdma-irq-src-num-according-to-sdma-in.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3007-drm-amdgpu-set-sdma-irq-src-num-according-to-sdma-in.patch
new file mode 100644
index 00000000..229684fc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3007-drm-amdgpu-set-sdma-irq-src-num-according-to-sdma-in.patch
@@ -0,0 +1,49 @@
+From 6b5a0a993fde6c15a756a9e85618f22d9a928c54 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Fri, 19 Jul 2019 19:09:38 +0800
+Subject: [PATCH 3007/4256] drm/amdgpu: set sdma irq src num according to sdma
+ instances
+
+Otherwise, it will cause driver access non-existing sdma registers
+in gpu reset code path
+
+Change-Id: I1c218985d8c0c883f9c36a21d2c58c3654c7acc1
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 17 +++++++++++++++--
+ 1 file changed, 15 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 48d4597ef9f6..2ddeff86aaea 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -2415,10 +2415,23 @@ static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = {
+ 
+ static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
+ {
+-	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
++	switch (adev->sdma.num_instances) {
++	case 1:
++		adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
++		adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
++		break;
++	case 8:
++		adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
++		adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
++		break;
++	case 2:
++	default:
++		adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
++		adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
++		break;
++	}
+ 	adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
+ 	adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
+-	adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
+ 	adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3008-drm-amd-powerplay-report-bootup-clock-as-max-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3008-drm-amd-powerplay-report-bootup-clock-as-max-support.patch
new file mode 100644
index 00000000..49b79822
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3008-drm-amd-powerplay-report-bootup-clock-as-max-support.patch
@@ -0,0 +1,62 @@
+From da07e7120d9105561fcfac24b5518d9cb8800cad Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Wed, 17 Jul 2019 16:32:27 +0800
+Subject: [PATCH 3008/4256] drm/amd/powerplay: report bootup clock as max
+ supported on dpm disabled
+
+With gfxclk or uclk dpm disabled, it's reasonable to report bootup clock
+as the max supported.
+
+Change-Id: If8aa7a912e8a34414b0e9c2b46de9b6e316fd9d7
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 27 +++++++++++++++++++++-
+ 1 file changed, 26 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index f67206c607ca..416f9a837fa8 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -137,12 +137,37 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ {
+ 	int ret = 0, clk_id = 0;
+ 	uint32_t param = 0;
++	uint32_t clock_limit;
+ 
+ 	if (!min && !max)
+ 		return -EINVAL;
+ 
+-	if (!smu_clk_dpm_is_enabled(smu, clk_type))
++	if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
++		switch (clk_type) {
++		case SMU_MCLK:
++		case SMU_UCLK:
++			clock_limit = smu->smu_table.boot_values.uclk;
++			break;
++		case SMU_GFXCLK:
++		case SMU_SCLK:
++			clock_limit = smu->smu_table.boot_values.gfxclk;
++			break;
++		case SMU_SOCCLK:
++			clock_limit = smu->smu_table.boot_values.socclk;
++			break;
++		default:
++			clock_limit = 0;
++			break;
++		}
++
++		/* clock in Mhz unit */
++		if (min)
++			*min = clock_limit / 100;
++		if (max)
++			*max = clock_limit / 100;
++
+ 		return 0;
++	}
+ 
+ 	mutex_lock(&smu->mutex);
+ 	clk_id = smu_clk_get_index(smu, clk_type);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3009-drm-amd-display-initialize-p_state-to-proper-value.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3009-drm-amd-display-initialize-p_state-to-proper-value.patch
new file mode 100644
index 00000000..5875599b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3009-drm-amd-display-initialize-p_state-to-proper-value.patch
@@ -0,0 +1,38 @@
+From b4d0759597dff75d37e96d8cc8548cfaf2eef474 Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Fri, 31 May 2019 15:14:13 -0400
+Subject: [PATCH 3009/4256] drm/amd/display: initialize p_state to proper value
+
+[why]
+On some modes SMU will be in infinite loop state at boot, this is
+because driver assumes p_state_support is false, but this is the
+opposite of the assumed boot state by SMU.  we optimize away
+notifying SMU about no pstate, and so they will get stuck
+
+[how]
+when we init clk manager, init pstate to true, so it matches driver load
+assumption
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index 08a774fc7b67..740f5db22bb5 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -301,6 +301,8 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
+ void dcn2_init_clocks(struct clk_mgr *clk_mgr)
+ {
+ 	memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
++	// Assumption is that boot state always supports pstate
++	clk_mgr->clks.p_state_change_support = true;
+ }
+ 
+ void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3010-drm-amd-display-Add-ability-to-set-preferred-link-tr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3010-drm-amd-display-Add-ability-to-set-preferred-link-tr.patch
new file mode 100644
index 00000000..8793efd1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3010-drm-amd-display-Add-ability-to-set-preferred-link-tr.patch
@@ -0,0 +1,895 @@
+From df04ab320b7ac0e0cd458b824c84553e88d7bff7 Mon Sep 17 00:00:00 2001
+From: David Galiffi <David.Galiffi@amd.com>
+Date: Thu, 30 May 2019 11:56:39 -0400
+Subject: [PATCH 3010/4256] drm/amd/display: Add ability to set preferred link
+ training parameters.
+
+[WHY]
+To add support for OS requirement to set preferred link training
+parameters.
+
+[HOW]
+Create new structure of dp link training overrides. During link training
+processes, these values should be used instead of the default training
+parameters.
+
+Signed-off-by: David Galiffi <David.Galiffi@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c |  46 ++-
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 337 +++++++++++++-----
+ .../drm/amd/display/dc/core/dc_link_hwss.c    |  28 +-
+ drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |  21 ++
+ drivers/gpu/drm/amd/display/dc/dc_link.h      |  11 +
+ .../gpu/drm/amd/display/dc/inc/link_hwss.h    |   2 +-
+ .../amd/display/include/link_service_types.h  |  17 +-
+ 7 files changed, 338 insertions(+), 124 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index dbc925273512..accd0f72e03f 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -1187,6 +1187,9 @@ static bool construct(
+ 	link->ctx = dc_ctx;
+ 	link->link_index = init_params->link_index;
+ 
++	memset(&link->preferred_training_settings, 0, sizeof(struct dc_link_training_overrides));
++	memset(&link->preferred_link_setting, 0, sizeof(struct dc_link_settings));
++
+ 	link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
+ 
+ 	if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
+@@ -1465,6 +1468,9 @@ static enum dc_status enable_link_dp(
+ 	struct dc_link *link = stream->link;
+ 	struct dc_link_settings link_settings = {0};
+ 	enum dp_panel_mode panel_mode;
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	bool fec_enable;
++#endif
+ 
+ 	/* get link settings for video mode timing */
+ 	decide_link_settings(stream, &link_settings);
+@@ -1509,10 +1515,20 @@ static enum dc_status enable_link_dp(
+ 			skip_video_pattern = false;
+ 
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-	dp_set_fec_ready(link, true);
++	if (link->preferred_training_settings.fec_enable != NULL)
++		fec_enable = *link->preferred_training_settings.fec_enable;
++	else
++		fec_enable = true;
++
++	dp_set_fec_ready(link, fec_enable);
+ #endif
+ 
+-	if (perform_link_training_with_retries(
++	if (link->aux_access_disabled) {
++		dc_link_dp_perform_link_training_skip_aux(link, &link_settings);
++
++		link->cur_link_settings = link_settings;
++		status = DC_OK;
++	} else if (perform_link_training_with_retries(
+ 			link,
+ 			&link_settings,
+ 			skip_video_pattern,
+@@ -1524,7 +1540,7 @@ static enum dc_status enable_link_dp(
+ 		status = DC_FAIL_DP_LINK_TRAINING;
+ 
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-	dp_set_fec_enable(link, true);
++	dp_set_fec_enable(link, fec_enable);
+ #endif
+ 	return status;
+ }
+@@ -3012,6 +3028,29 @@ void dc_link_set_preferred_link_settings(struct dc *dc,
+ 		dp_retrain_link_dp_test(link, &store_settings, false);
+ }
+ 
++void dc_link_set_preferred_training_settings(struct dc *dc,
++						 struct dc_link_settings *link_setting,
++						 struct dc_link_training_overrides *lt_overrides,
++						 struct dc_link *link,
++						 bool skip_immediate_retrain)
++{
++	if (lt_overrides != NULL)
++		link->preferred_training_settings = *lt_overrides;
++	else
++		memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
++
++	if (link_setting != NULL) {
++		link->preferred_link_setting = *link_setting;
++	} else {
++		link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
++		link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
++	}
++
++	/* Retrain now, or wait until next stream update to apply */
++	if (skip_immediate_retrain == false)
++		dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
++}
++
+ void dc_link_enable_hpd(const struct dc_link *link)
+ {
+ 	dc_link_dp_enable_hpd(link);
+@@ -3022,7 +3061,6 @@ void dc_link_disable_hpd(const struct dc_link *link)
+ 	dc_link_dp_disable_hpd(link);
+ }
+ 
+-
+ void dc_link_set_test_pattern(struct dc_link *link,
+ 			      enum dp_test_pattern test_pattern,
+ 			      const struct link_training_settings *p_link_settings,
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 056be4c34a98..3f8a8f61cd76 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -49,7 +49,7 @@ static struct dc_link_settings get_common_supported_link_settings(
+ 		struct dc_link_settings link_setting_a,
+ 		struct dc_link_settings link_setting_b);
+ 
+-static void wait_for_training_aux_rd_interval(
++static uint32_t get_training_aux_rd_interval(
+ 	struct dc_link *link,
+ 	uint32_t default_wait_in_micro_secs)
+ {
+@@ -68,15 +68,21 @@ static void wait_for_training_aux_rd_interval(
+ 			sizeof(training_rd_interval));
+ 
+ 		if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
+-			default_wait_in_micro_secs =
+-				training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
++			default_wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
+ 	}
+ 
+-	udelay(default_wait_in_micro_secs);
++	return default_wait_in_micro_secs;
++}
++
++static void wait_for_training_aux_rd_interval(
++	struct dc_link *link,
++	uint32_t wait_in_micro_secs)
++{
++	udelay(wait_in_micro_secs);
+ 
+ 	DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
+ 		__func__,
+-		default_wait_in_micro_secs);
++		wait_in_micro_secs);
+ }
+ 
+ static void dpcd_set_training_pattern(
+@@ -95,27 +101,27 @@ static void dpcd_set_training_pattern(
+ 		dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
+ }
+ 
+-static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link)
++static enum dc_dp_training_pattern get_supported_tp(struct dc_link *link)
+ {
+-	enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2;
++	enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
+ 	struct encoder_feature_support *features = &link->link_enc->features;
+ 	struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
+ 
+ 	if (features->flags.bits.IS_TPS3_CAPABLE)
+-		highest_tp = HW_DP_TRAINING_PATTERN_3;
++		highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
+ 
+ 	if (features->flags.bits.IS_TPS4_CAPABLE)
+-		highest_tp = HW_DP_TRAINING_PATTERN_4;
++		highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
+ 
+ 	if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
+-		highest_tp >= HW_DP_TRAINING_PATTERN_4)
+-		return HW_DP_TRAINING_PATTERN_4;
++		highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
++		return DP_TRAINING_PATTERN_SEQUENCE_4;
+ 
+ 	if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
+-		highest_tp >= HW_DP_TRAINING_PATTERN_3)
+-		return HW_DP_TRAINING_PATTERN_3;
++		highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
++		return DP_TRAINING_PATTERN_SEQUENCE_3;
+ 
+-	return HW_DP_TRAINING_PATTERN_2;
++	return DP_TRAINING_PATTERN_SEQUENCE_2;
+ }
+ 
+ static void dpcd_set_link_settings(
+@@ -126,7 +132,7 @@ static void dpcd_set_link_settings(
+ 
+ 	union down_spread_ctrl downspread = { {0} };
+ 	union lane_count_set lane_count_set = { {0} };
+-	enum hw_dp_training_pattern hw_tr_pattern;
++	enum dc_dp_training_pattern dp_tr_pattern;
+ 
+ 	downspread.raw = (uint8_t)
+ 	(lt_settings->link_settings.link_spread);
+@@ -134,21 +140,21 @@ static void dpcd_set_link_settings(
+ 	lane_count_set.bits.LANE_COUNT_SET =
+ 	lt_settings->link_settings.lane_count;
+ 
+-	lane_count_set.bits.ENHANCED_FRAMING = 1;
+-
++	lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
+ 	lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
+ 
+-	hw_tr_pattern = get_supported_tp(link);
+-	if (hw_tr_pattern != HW_DP_TRAINING_PATTERN_4) {
++	dp_tr_pattern = get_supported_tp(link);
++
++	if (dp_tr_pattern != DP_TRAINING_PATTERN_SEQUENCE_4) {
+ 		lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
+ 				link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
+ 	}
+ 
+ 	core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
+-	&downspread.raw, sizeof(downspread));
++		&downspread.raw, sizeof(downspread));
+ 
+ 	core_link_write_dpcd(link, DP_LANE_COUNT_SET,
+-	&lane_count_set.raw, 1);
++		&lane_count_set.raw, 1);
+ 
+ 	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
+ 			lt_settings->link_settings.use_link_rate_set == true) {
+@@ -162,46 +168,47 @@ static void dpcd_set_link_settings(
+ 	}
+ 
+ 	if (rate) {
+-		DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n",
++		DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
+ 			__func__,
+ 			DP_LINK_BW_SET,
+ 			lt_settings->link_settings.link_rate,
+ 			DP_LANE_COUNT_SET,
+ 			lt_settings->link_settings.lane_count,
++			lt_settings->enhanced_framing,
+ 			DP_DOWNSPREAD_CTRL,
+ 			lt_settings->link_settings.link_spread);
+ 	} else {
+-		DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x\n %x spread = %x\n",
++		DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
+ 			__func__,
+ 			DP_LINK_RATE_SET,
+ 			lt_settings->link_settings.link_rate_set,
+ 			DP_LANE_COUNT_SET,
+ 			lt_settings->link_settings.lane_count,
++			lt_settings->enhanced_framing,
+ 			DP_DOWNSPREAD_CTRL,
+ 			lt_settings->link_settings.link_spread);
+ 	}
+-
+ }
+ 
+ static enum dpcd_training_patterns
+-	hw_training_pattern_to_dpcd_training_pattern(
++	dc_dp_training_pattern_to_dpcd_training_pattern(
+ 	struct dc_link *link,
+-	enum hw_dp_training_pattern pattern)
++	enum dc_dp_training_pattern pattern)
+ {
+ 	enum dpcd_training_patterns dpcd_tr_pattern =
+ 	DPCD_TRAINING_PATTERN_VIDEOIDLE;
+ 
+ 	switch (pattern) {
+-	case HW_DP_TRAINING_PATTERN_1:
++	case DP_TRAINING_PATTERN_SEQUENCE_1:
+ 		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
+ 		break;
+-	case HW_DP_TRAINING_PATTERN_2:
++	case DP_TRAINING_PATTERN_SEQUENCE_2:
+ 		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
+ 		break;
+-	case HW_DP_TRAINING_PATTERN_3:
++	case DP_TRAINING_PATTERN_SEQUENCE_3:
+ 		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
+ 		break;
+-	case HW_DP_TRAINING_PATTERN_4:
++	case DP_TRAINING_PATTERN_SEQUENCE_4:
+ 		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
+ 		break;
+ 	default:
+@@ -212,13 +219,12 @@ static enum dpcd_training_patterns
+ 	}
+ 
+ 	return dpcd_tr_pattern;
+-
+ }
+ 
+ static void dpcd_set_lt_pattern_and_lane_settings(
+ 	struct dc_link *link,
+ 	const struct link_training_settings *lt_settings,
+-	enum hw_dp_training_pattern pattern)
++	enum dc_dp_training_pattern pattern)
+ {
+ 	union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
+ 	const uint32_t dpcd_base_lt_offset =
+@@ -233,7 +239,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
+ 	* DpcdAddress_TrainingPatternSet
+ 	*****************************************************************/
+ 	dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
+-		hw_training_pattern_to_dpcd_training_pattern(link, pattern);
++		dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
+ 
+ 	dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
+ 		= dpcd_pattern.raw;
+@@ -346,12 +352,20 @@ static void update_drive_settings(
+ {
+ 	uint32_t lane;
+ 	for (lane = 0; lane < src.link_settings.lane_count; lane++) {
+-		dest->lane_settings[lane].VOLTAGE_SWING =
+-			src.lane_settings[lane].VOLTAGE_SWING;
+-		dest->lane_settings[lane].PRE_EMPHASIS =
+-			src.lane_settings[lane].PRE_EMPHASIS;
+-		dest->lane_settings[lane].POST_CURSOR2 =
+-			src.lane_settings[lane].POST_CURSOR2;
++		if (dest->voltage_swing == NULL)
++			dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
++		else
++			dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
++
++		if (dest->pre_emphasis == NULL)
++			dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
++		else
++			dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
++
++		if (dest->post_cursor2 == NULL)
++			dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
++		else
++			dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
+ 	}
+ }
+ 
+@@ -754,15 +768,15 @@ static enum link_training_result perform_channel_equalization_sequence(
+ 	struct link_training_settings *lt_settings)
+ {
+ 	struct link_training_settings req_settings;
+-	enum hw_dp_training_pattern hw_tr_pattern;
++	enum dc_dp_training_pattern tr_pattern;
+ 	uint32_t retries_ch_eq;
+ 	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
+ 	union lane_align_status_updated dpcd_lane_status_updated = { {0} };
+ 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
+ 
+-	hw_tr_pattern = get_supported_tp(link);
++	tr_pattern = lt_settings->pattern_for_eq;
+ 
+-	dp_set_hw_training_pattern(link, hw_tr_pattern);
++	dp_set_hw_training_pattern(link, tr_pattern);
+ 
+ 	for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
+ 		retries_ch_eq++) {
+@@ -776,12 +790,12 @@ static enum link_training_result perform_channel_equalization_sequence(
+ 			dpcd_set_lt_pattern_and_lane_settings(
+ 				link,
+ 				lt_settings,
+-				hw_tr_pattern);
++				tr_pattern);
+ 		else
+ 			dpcd_set_lane_settings(link, lt_settings);
+ 
+ 		/* 3. wait for receiver to lock-on*/
+-		wait_for_training_aux_rd_interval(link, 400);
++		wait_for_training_aux_rd_interval(link, lt_settings->eq_pattern_time);
+ 
+ 		/* 4. Read lane status and requested
+ 		 * drive settings as set by the sink*/
+@@ -817,27 +831,16 @@ static enum link_training_result perform_clock_recovery_sequence(
+ {
+ 	uint32_t retries_cr;
+ 	uint32_t retry_count;
+-	uint32_t lane;
+ 	struct link_training_settings req_settings;
+-	enum dc_lane_count lane_count =
+-	lt_settings->link_settings.lane_count;
+-	enum hw_dp_training_pattern hw_tr_pattern = HW_DP_TRAINING_PATTERN_1;
++	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
++	enum dc_dp_training_pattern tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_1;
+ 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
+ 	union lane_align_status_updated dpcd_lane_status_updated;
+ 
+ 	retries_cr = 0;
+ 	retry_count = 0;
+-	/* initial drive setting (VS/PE/PC2)*/
+-	for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
+-		lt_settings->lane_settings[lane].VOLTAGE_SWING =
+-		VOLTAGE_SWING_LEVEL0;
+-		lt_settings->lane_settings[lane].PRE_EMPHASIS =
+-		PRE_EMPHASIS_DISABLED;
+-		lt_settings->lane_settings[lane].POST_CURSOR2 =
+-		POST_CURSOR2_DISABLED;
+-	}
+ 
+-	dp_set_hw_training_pattern(link, hw_tr_pattern);
++	dp_set_hw_training_pattern(link, tr_pattern);
+ 
+ 	/* najeeb - The synaptics MST hub can put the LT in
+ 	* infinite loop by switching the VS
+@@ -845,7 +848,7 @@ static enum link_training_result perform_clock_recovery_sequence(
+ 	/* between level 0 and level 1 continuously, here
+ 	* we try for CR lock for LinkTrainingMaxCRRetry count*/
+ 	while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
+-	(retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
++		(retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
+ 
+ 		memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
+ 		memset(&dpcd_lane_status_updated, '\0',
+@@ -863,7 +866,7 @@ static enum link_training_result perform_clock_recovery_sequence(
+ 			dpcd_set_lt_pattern_and_lane_settings(
+ 					link,
+ 					lt_settings,
+-					hw_tr_pattern);
++					tr_pattern);
+ 		else
+ 			dpcd_set_lane_settings(
+ 					link,
+@@ -872,7 +875,7 @@ static enum link_training_result perform_clock_recovery_sequence(
+ 		/* 3. wait receiver to lock-on*/
+ 		wait_for_training_aux_rd_interval(
+ 				link,
+-				100);
++				lt_settings->cr_pattern_time);
+ 
+ 		/* 4. Read lane status and requested drive
+ 		* settings as set by the sink
+@@ -939,7 +942,7 @@ static inline enum link_training_result perform_link_training_int(
+ 	 * TPS4 must be used instead of POST_LT_ADJ_REQ.
+ 	 */
+ 	if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
+-			get_supported_tp(link) == HW_DP_TRAINING_PATTERN_4)
++			get_supported_tp(link) == DP_TRAINING_PATTERN_SEQUENCE_4)
+ 		return status;
+ 
+ 	if (status == LINK_TRAINING_SUCCESS &&
+@@ -947,7 +950,7 @@ static inline enum link_training_result perform_link_training_int(
+ 		status = LINK_TRAINING_LQA_FAIL;
+ 
+ 	lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
+-	lane_count_set.bits.ENHANCED_FRAMING = 1;
++	lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
+ 	lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
+ 
+ 	core_link_write_dpcd(
+@@ -959,24 +962,28 @@ static inline enum link_training_result perform_link_training_int(
+ 	return status;
+ }
+ 
+-enum link_training_result dc_link_dp_perform_link_training(
+-	struct dc_link *link,
++static void initialize_training_settings(
++	 struct dc_link *link,
+ 	const struct dc_link_settings *link_setting,
+-	bool skip_video_pattern)
++	struct link_training_settings *lt_settings)
+ {
+-	enum link_training_result status = LINK_TRAINING_SUCCESS;
++	uint32_t lane;
+ 
+-	char *link_rate = "Unknown";
+-	char *lt_result = "Unknown";
++	memset(lt_settings, '\0', sizeof(struct link_training_settings));
+ 
+-	struct link_training_settings lt_settings;
++	/* Initialize link settings */
++	lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
++	lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
+ 
+-	memset(&lt_settings, '\0', sizeof(lt_settings));
++	if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
++		lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
++	else
++		lt_settings->link_settings.link_rate = link_setting->link_rate;
+ 
+-	lt_settings.link_settings.link_rate = link_setting->link_rate;
+-	lt_settings.link_settings.lane_count = link_setting->lane_count;
+-	lt_settings.link_settings.use_link_rate_set = link_setting->use_link_rate_set;
+-	lt_settings.link_settings.link_rate_set = link_setting->link_rate_set;
++	if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
++		lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
++	else
++		lt_settings->link_settings.lane_count = link_setting->lane_count;
+ 
+ 	/*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
+ 
+@@ -987,31 +994,75 @@ enum link_training_result dc_link_dp_perform_link_training(
+ 	 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
+ 	 * LINK_SPREAD_DISABLED;
+ 	 */
++	/* Initialize link spread */
+ 	if (link->dp_ss_off)
+-		lt_settings.link_settings.link_spread = LINK_SPREAD_DISABLED;
++		lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
++	else if (link->preferred_training_settings.downspread != NULL)
++		lt_settings->link_settings.link_spread
++			= *link->preferred_training_settings.downspread
++			? LINK_SPREAD_05_DOWNSPREAD_30KHZ
++			: LINK_SPREAD_DISABLED;
+ 	else
+-		lt_settings.link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
++		lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
+ 
+-	/* 1. set link rate, lane count and spread*/
+-	dpcd_set_link_settings(link, &lt_settings);
++	/* Initialize lane settings overrides */
++	if (link->preferred_training_settings.voltage_swing != NULL)
++		lt_settings->voltage_swing = link->preferred_training_settings.voltage_swing;
+ 
+-	/* 2. perform link training (set link training done
+-	 *  to false is done as well)*/
+-	status = perform_clock_recovery_sequence(link, &lt_settings);
+-	if (status == LINK_TRAINING_SUCCESS) {
+-		status = perform_channel_equalization_sequence(link,
+-				&lt_settings);
+-	}
++	if (link->preferred_training_settings.pre_emphasis != NULL)
++		lt_settings->pre_emphasis = link->preferred_training_settings.pre_emphasis;
+ 
+-	if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
+-		status = perform_link_training_int(link,
+-				&lt_settings,
+-				status);
++	if (link->preferred_training_settings.post_cursor2 != NULL)
++		lt_settings->post_cursor2 = link->preferred_training_settings.post_cursor2;
++
++	/* Initialize lane settings (VS/PE/PC2) */
++	for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
++		lt_settings->lane_settings[lane].VOLTAGE_SWING =
++			lt_settings->voltage_swing != NULL ?
++			*lt_settings->voltage_swing :
++			VOLTAGE_SWING_LEVEL0;
++		lt_settings->lane_settings[lane].PRE_EMPHASIS =
++			lt_settings->pre_emphasis != NULL ?
++			*lt_settings->pre_emphasis
++			: PRE_EMPHASIS_DISABLED;
++		lt_settings->lane_settings[lane].POST_CURSOR2 =
++			lt_settings->post_cursor2 != NULL ?
++			*lt_settings->post_cursor2
++			: POST_CURSOR2_DISABLED;
+ 	}
+ 
+-	/* 6. print status message*/
+-	switch (lt_settings.link_settings.link_rate) {
++	/* Initialize training timings */
++	if (link->preferred_training_settings.cr_pattern_time != NULL)
++		lt_settings->cr_pattern_time = *link->preferred_training_settings.cr_pattern_time;
++	else
++		lt_settings->cr_pattern_time = get_training_aux_rd_interval(link, 100);
++
++	if (link->preferred_training_settings.eq_pattern_time != NULL)
++		lt_settings->eq_pattern_time = *link->preferred_training_settings.eq_pattern_time;
++	else
++		lt_settings->eq_pattern_time = get_training_aux_rd_interval(link, 400);
++
++	if (link->preferred_training_settings.pattern_for_eq != NULL)
++		lt_settings->pattern_for_eq = *link->preferred_training_settings.pattern_for_eq;
++	else
++		lt_settings->pattern_for_eq = get_supported_tp(link);
++
++	if (link->preferred_training_settings.enhanced_framing != NULL)
++		lt_settings->enhanced_framing = *link->preferred_training_settings.enhanced_framing;
++	else
++		lt_settings->enhanced_framing = 1;
++}
++
++static void print_status_message(
++	struct dc_link *link,
++	const struct link_training_settings *lt_settings,
++	enum link_training_result status)
++{
++	char *link_rate = "Unknown";
++	char *lt_result = "Unknown";
++	char *lt_spread = "Disabled";
+ 
++	switch (lt_settings->link_settings.link_rate) {
+ 	case LINK_RATE_LOW:
+ 		link_rate = "RBR";
+ 		break;
+@@ -1057,13 +1108,102 @@ enum link_training_result dc_link_dp_perform_link_training(
+ 		break;
+ 	}
+ 
++	switch (lt_settings->link_settings.link_spread) {
++	case LINK_SPREAD_DISABLED:
++		lt_spread = "Disabled";
++		break;
++	case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
++		lt_spread = "0.5% 30KHz";
++		break;
++	case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
++		lt_spread = "0.5% 33KHz";
++		break;
++	default:
++		break;
++	}
++
+ 	/* Connectivity log: link training */
+-	CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d",
+-			link_rate,
+-			lt_settings.link_settings.lane_count,
+-			lt_result,
+-			lt_settings.lane_settings[0].VOLTAGE_SWING,
+-			lt_settings.lane_settings[0].PRE_EMPHASIS);
++	CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
++				link_rate,
++				lt_settings->link_settings.lane_count,
++				lt_result,
++				lt_settings->lane_settings[0].VOLTAGE_SWING,
++				lt_settings->lane_settings[0].PRE_EMPHASIS,
++				lt_spread);
++}
++
++bool dc_link_dp_perform_link_training_skip_aux(
++	struct dc_link *link,
++	const struct dc_link_settings *link_setting)
++{
++	struct link_training_settings lt_settings;
++	enum dc_dp_training_pattern pattern_for_cr = DP_TRAINING_PATTERN_SEQUENCE_1;
++
++	initialize_training_settings(link, link_setting, &lt_settings);
++
++	/* 1. Perform_clock_recovery_sequence. */
++
++	/* transmit training pattern for clock recovery */
++	dp_set_hw_training_pattern(link, pattern_for_cr);
++
++	/* call HWSS to set lane settings*/
++	dp_set_hw_lane_settings(link, &lt_settings);
++
++	/* wait receiver to lock-on*/
++	wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
++
++	/* 2. Perform_channel_equalization_sequence. */
++
++	/* transmit training pattern for channel equalization. */
++	dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq);
++
++	/* call HWSS to set lane settings*/
++	dp_set_hw_lane_settings(link, &lt_settings);
++
++	/* wait receiver to lock-on. */
++	wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
++
++	/* 3. Perform_link_training_int. */
++
++	/* Mainlink output idle pattern. */
++	dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
++
++	print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
++
++	return true;
++}
++
++enum link_training_result dc_link_dp_perform_link_training(
++	struct dc_link *link,
++	const struct dc_link_settings *link_setting,
++	bool skip_video_pattern)
++{
++	enum link_training_result status = LINK_TRAINING_SUCCESS;
++
++	struct link_training_settings lt_settings;
++
++	initialize_training_settings(link, link_setting, &lt_settings);
++
++	/* 1. set link rate, lane count and spread. */
++	dpcd_set_link_settings(link, &lt_settings);
++
++	/* 2. perform link training (set link training done
++	 *  to false is done as well)
++	 */
++	status = perform_clock_recovery_sequence(link, &lt_settings);
++	if (status == LINK_TRAINING_SUCCESS) {
++		status = perform_channel_equalization_sequence(link,
++				&lt_settings);
++	}
++
++	if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
++		status = perform_link_training_int(link,
++				&lt_settings,
++				status);
++	}
++
++	/* 6. print status message*/
++	print_status_message(link, &lt_settings, status);
+ 
+ 	if (status != LINK_TRAINING_SUCCESS)
+ 		link->ctx->dc->debug_data.ltFailCount++;
+@@ -1071,7 +1211,6 @@ enum link_training_result dc_link_dp_perform_link_training(
+ 	return status;
+ }
+ 
+-
+ bool perform_link_training_with_retries(
+ 	struct dc_link *link,
+ 	const struct dc_link_settings *link_setting,
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index 2d019e1f6135..211fadefe2f5 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -25,10 +25,11 @@ enum dc_status core_link_read_dpcd(
+ 	uint8_t *data,
+ 	uint32_t size)
+ {
+-	if (!dm_helpers_dp_read_dpcd(link->ctx,
+-			link,
+-			address, data, size))
+-			return DC_ERROR_UNEXPECTED;
++	if (!link->aux_access_disabled &&
++			!dm_helpers_dp_read_dpcd(link->ctx,
++			link, address, data, size)) {
++		return DC_ERROR_UNEXPECTED;
++	}
+ 
+ 	return DC_OK;
+ }
+@@ -39,10 +40,11 @@ enum dc_status core_link_write_dpcd(
+ 	const uint8_t *data,
+ 	uint32_t size)
+ {
+-	if (!dm_helpers_dp_write_dpcd(link->ctx,
+-			link,
+-			address, data, size))
+-				return DC_ERROR_UNEXPECTED;
++	if (!link->aux_access_disabled &&
++			!dm_helpers_dp_write_dpcd(link->ctx,
++			link, address, data, size)) {
++		return DC_ERROR_UNEXPECTED;
++	}
+ 
+ 	return DC_OK;
+ }
+@@ -203,21 +205,21 @@ void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal)
+ 
+ bool dp_set_hw_training_pattern(
+ 	struct dc_link *link,
+-	enum hw_dp_training_pattern pattern)
++	enum dc_dp_training_pattern pattern)
+ {
+ 	enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
+ 
+ 	switch (pattern) {
+-	case HW_DP_TRAINING_PATTERN_1:
++	case DP_TRAINING_PATTERN_SEQUENCE_1:
+ 		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN1;
+ 		break;
+-	case HW_DP_TRAINING_PATTERN_2:
++	case DP_TRAINING_PATTERN_SEQUENCE_2:
+ 		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN2;
+ 		break;
+-	case HW_DP_TRAINING_PATTERN_3:
++	case DP_TRAINING_PATTERN_SEQUENCE_3:
+ 		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN3;
+ 		break;
+-	case HW_DP_TRAINING_PATTERN_4:
++	case DP_TRAINING_PATTERN_SEQUENCE_4:
+ 		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
+ 		break;
+ 	default:
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+index dfcec4d3e9c0..efa7a47f6b7e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+@@ -90,6 +90,13 @@ enum dc_post_cursor2 {
+ 	POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
+ };
+ 
++enum dc_dp_training_pattern {
++	DP_TRAINING_PATTERN_SEQUENCE_1 = 0,
++	DP_TRAINING_PATTERN_SEQUENCE_2,
++	DP_TRAINING_PATTERN_SEQUENCE_3,
++	DP_TRAINING_PATTERN_SEQUENCE_4,
++};
++
+ struct dc_link_settings {
+ 	enum dc_lane_count lane_count;
+ 	enum dc_link_rate link_rate;
+@@ -109,6 +116,20 @@ struct dc_link_training_settings {
+ 	struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
+ };
+ 
++struct dc_link_training_overrides {
++	enum dc_voltage_swing *voltage_swing;
++	enum dc_pre_emphasis *pre_emphasis;
++	enum dc_post_cursor2 *post_cursor2;
++
++	uint16_t *cr_pattern_time;
++	uint16_t *eq_pattern_time;
++	enum dc_dp_training_pattern *pattern_for_eq;
++
++	enum dc_link_spread *downspread;
++	bool *alternate_scrambler_reset;
++	bool *enhanced_framing;
++	bool *fec_enable;
++};
+ 
+ union dpcd_rev {
+ 	struct {
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
+index 6f0b80111e58..d6ff5af70c71 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
+@@ -83,6 +83,7 @@ struct dc_link {
+ 	bool is_hpd_filter_disabled;
+ 	bool dp_ss_off;
+ 	bool link_state_valid;
++	bool aux_access_disabled;
+ 
+ 	/* caps is the same as reported_link_cap. link_traing use
+ 	 * reported_link_cap. Will clean up.  TODO
+@@ -92,6 +93,7 @@ struct dc_link {
+ 	struct dc_link_settings cur_link_settings;
+ 	struct dc_lane_settings cur_lane_setting;
+ 	struct dc_link_settings preferred_link_setting;
++	struct dc_link_training_overrides preferred_training_settings;
+ 
+ 	uint8_t ddc_hw_inst;
+ 
+@@ -217,6 +219,10 @@ void dc_link_dp_set_drive_settings(
+ 	struct dc_link *link,
+ 	struct link_training_settings *lt_settings);
+ 
++bool dc_link_dp_perform_link_training_skip_aux(
++	struct dc_link *link,
++	const struct dc_link_settings *link_setting);
++
+ enum link_training_result dc_link_dp_perform_link_training(
+ 	struct dc_link *link,
+ 	const struct dc_link_settings *link_setting,
+@@ -251,6 +257,11 @@ void dc_link_perform_link_training(struct dc *dc,
+ void dc_link_set_preferred_link_settings(struct dc *dc,
+ 					 struct dc_link_settings *link_setting,
+ 					 struct dc_link *link);
++void dc_link_set_preferred_training_settings(struct dc *dc,
++					struct dc_link_settings *link_setting,
++					struct dc_link_training_overrides *lt_overrides,
++					struct dc_link *link,
++					bool skip_immediate_retrain);
+ void dc_link_enable_hpd(const struct dc_link *link);
+ void dc_link_disable_hpd(const struct dc_link *link);
+ void dc_link_set_test_pattern(struct dc_link *link,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+index 30be7bb4a01a..3680846674e8 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+@@ -60,7 +60,7 @@ void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal);
+ 
+ bool dp_set_hw_training_pattern(
+ 	struct dc_link *link,
+-	enum hw_dp_training_pattern pattern);
++	enum dc_dp_training_pattern pattern);
+ 
+ void dp_set_hw_lane_settings(
+ 	struct dc_link *link,
+diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
+index 80f0d93cfd94..876b0b3e1a9c 100644
+--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
++++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
+@@ -71,14 +71,17 @@ enum link_training_result {
+ struct link_training_settings {
+ 	struct dc_link_settings link_settings;
+ 	struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
+-	bool allow_invalid_msa_timing_param;
+-};
+ 
+-enum hw_dp_training_pattern {
+-	HW_DP_TRAINING_PATTERN_1 = 0,
+-	HW_DP_TRAINING_PATTERN_2,
+-	HW_DP_TRAINING_PATTERN_3,
+-	HW_DP_TRAINING_PATTERN_4
++	enum dc_voltage_swing *voltage_swing;
++	enum dc_pre_emphasis *pre_emphasis;
++	enum dc_post_cursor2 *post_cursor2;
++
++	uint16_t cr_pattern_time;
++	uint16_t eq_pattern_time;
++	enum dc_dp_training_pattern pattern_for_eq;
++
++	bool enhanced_framing;
++	bool allow_invalid_msa_timing_param;
+ };
+ 
+ /*TODO: Move this enum test harness*/
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3011-drm-amd-display-3.2.36.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3011-drm-amd-display-3.2.36.patch
new file mode 100644
index 00000000..a3ecd021
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3011-drm-amd-display-3.2.36.patch
@@ -0,0 +1,27 @@
+From 94378295ab03c9b153c6586ae8634976127dc2ad Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Mon, 3 Jun 2019 09:12:55 -0400
+Subject: [PATCH 3011/4256] drm/amd/display: 3.2.36
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 3ff0890ace0c..6b8de1c94701 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -42,7 +42,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.35"
++#define DC_VER "3.2.36"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3012-drm-amd-display-fix-up-HUBBUB-hw-programming-for-VM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3012-drm-amd-display-fix-up-HUBBUB-hw-programming-for-VM.patch
new file mode 100644
index 00000000..38e939b5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3012-drm-amd-display-fix-up-HUBBUB-hw-programming-for-VM.patch
@@ -0,0 +1,77 @@
+From 1409151b4833b16601d3df7639557236dae9edd0 Mon Sep 17 00:00:00 2001
+From: Jun Lei <jun.lei@amd.com>
+Date: Mon, 3 Jun 2019 08:13:12 -0400
+Subject: [PATCH 3012/4256] drm/amd/display: fix up HUBBUB hw programming for
+ VM
+
+[why]
+Some values were not being converted or bit-shifted properly for
+HW registers, causing black screen
+
+[how]
+Fix up the values before programming HW
+
+Signed-off-by: Jun Lei <jun.lei@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 17 ++++++++---------
+ .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h    |  4 ++--
+ 2 files changed, 10 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+index ece6e136437b..c72a9ff57f15 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+@@ -366,25 +366,24 @@ int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub,
+ 	struct dcn_vmid_page_table_config phys_config;
+ 
+ 	REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
+-			FB_BASE, pa_config->system_aperture.fb_base);
++			FB_BASE, pa_config->system_aperture.fb_base >> 24);
+ 	REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
+-			FB_TOP, pa_config->system_aperture.fb_top);
++			FB_TOP, pa_config->system_aperture.fb_top >> 24);
+ 	REG_SET(DCN_VM_FB_OFFSET, 0,
+-			FB_OFFSET, pa_config->system_aperture.fb_offset);
++			FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
+ 	REG_SET(DCN_VM_AGP_BOT, 0,
+-			AGP_BOT, pa_config->system_aperture.agp_bot);
++			AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
+ 	REG_SET(DCN_VM_AGP_TOP, 0,
+-			AGP_TOP, pa_config->system_aperture.agp_top);
++			AGP_TOP, pa_config->system_aperture.agp_top >> 24);
+ 	REG_SET(DCN_VM_AGP_BASE, 0,
+-			AGP_BASE, pa_config->system_aperture.agp_base);
++			AGP_BASE, pa_config->system_aperture.agp_base >> 24);
+ 
+ 	if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
+-		phys_config.depth = 1;
+-		phys_config.block_size = 4096;
+ 		phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
+ 		phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12;
+ 		phys_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
+-
++		phys_config.depth = 0;
++		phys_config.block_size = 0;
+ 		// Init VMID 0 based on PA config
+ 		dcn20_vmid_setup(&hubbub1->vmid[0], &phys_config);
+ 	}
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+index 959f5b654611..1ea505f7a05a 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+@@ -61,8 +61,8 @@ enum dcn_hubbub_page_table_depth {
+ };
+ 
+ enum dcn_hubbub_page_table_block_size {
+-	DCN_PAGE_TABLE_BLOCK_SIZE_4KB,
+-	DCN_PAGE_TABLE_BLOCK_SIZE_64KB
++	DCN_PAGE_TABLE_BLOCK_SIZE_4KB = 0,
++	DCN_PAGE_TABLE_BLOCK_SIZE_64KB = 4
+ };
+ 
+ struct dcn_hubbub_phys_addr_config {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3013-drm-amd-display-fix-dsc-disable.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3013-drm-amd-display-fix-dsc-disable.patch
new file mode 100644
index 00000000..bca627ad
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3013-drm-amd-display-fix-dsc-disable.patch
@@ -0,0 +1,34 @@
+From 0d402e03c13734d266ec1fff9ea900a404f4aee9 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Thu, 30 May 2019 15:47:51 -0400
+Subject: [PATCH 3013/4256] drm/amd/display: fix dsc disable
+
+A regression caused dsc to never get disabled in certain situations.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 6925d25d2457..45f9dad95644 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1715,8 +1715,11 @@ static void dcn20_reset_back_end_for_pipe(
+ 		else if (pipe_ctx->stream_res.audio) {
+ 			dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
+ 		}
+-
+ 	}
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	else if (pipe_ctx->stream_res.dsc)
++		dp_set_dsc_enable(pipe_ctx, false);
++#endif
+ 
+ 	/* by upper caller loop, parent pipe: pipe0, will be reset last.
+ 	 * back end share by all pipes and will be disable only when disable
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3014-drm-amd-display-3.2.37.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3014-drm-amd-display-3.2.37.patch
new file mode 100644
index 00000000..75f7734a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3014-drm-amd-display-3.2.37.patch
@@ -0,0 +1,27 @@
+From c12827f347f1ffa944f05a4124729c7df08c90a7 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Mon, 3 Jun 2019 11:30:43 -0400
+Subject: [PATCH 3014/4256] drm/amd/display: 3.2.37
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 6b8de1c94701..6462db311e97 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -42,7 +42,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.36"
++#define DC_VER "3.2.37"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3015-drm-amd-display-move-bw-calc-code-into-helpers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3015-drm-amd-display-move-bw-calc-code-into-helpers.patch
new file mode 100644
index 00000000..21bf0756
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3015-drm-amd-display-move-bw-calc-code-into-helpers.patch
@@ -0,0 +1,396 @@
+From 4662aa48edacb59942d375fc920b296a26878bff Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Wed, 22 May 2019 14:24:40 -0400
+Subject: [PATCH 3015/4256] drm/amd/display: move bw calc code into helpers
+
+[Why]
+For better readability and reusability
+
+[How]
+Move snippets of BW calculation code into helpers.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Fatemeh Darbehani <Fatemeh.Darbehani@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |   1 +
+ .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  |   2 -
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 250 +++++++++++-------
+ .../drm/amd/display/dc/dcn20/dcn20_resource.h |  11 +
+ .../amd/display/dc/inc/hw/clk_mgr_internal.h  |   2 +
+ 5 files changed, 167 insertions(+), 99 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 429794becdcd..aa007e9958a0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -128,6 +128,7 @@ static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
+ 		amdgpu_device_get_pcie_replay_count, NULL);
+ 
+ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
++static void amdgpu_device_parse_faked_did(struct amdgpu_device *adev);
+ 
+ /**
+  * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index 740f5db22bb5..614a941eb9f2 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -26,8 +26,6 @@
+ #include "dccg.h"
+ #include "clk_mgr_internal.h"
+ 
+-
+-#include "dcn20/dcn20_clk_mgr.h"
+ #include "dce100/dce_clk_mgr.h"
+ #include "reg_helper.h"
+ #include "core_types.h"
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 20cf98f090b0..842f48403226 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2016,15 +2016,16 @@ static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
+ }
+ #endif
+ 
+-bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
+-		bool fast_validate)
++bool dcn20_fast_validate_bw(
++		struct dc *dc,
++		struct dc_state *context,
++		display_e2e_pipe_params_st *pipes,
++		int *pipe_split_from,
++		int *vlevel_out)
+ {
+ 	bool out = false;
+ 
+-	BW_VAL_TRACE_SETUP();
+-
+ 	int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
+-	int pipe_split_from[MAX_PIPES];
+ 	bool odm_capable = context->bw_ctx.dml.ip.odm_capable;
+ 	bool force_split = false;
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+@@ -2032,10 +2033,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
+ #endif
+ 	int split_threshold = dc->res_pool->pipe_count / 2;
+ 	bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
+-	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
+-	DC_LOGGER_INIT(dc->ctx->logger);
+ 
+-	BW_VAL_TRACE_COUNT();
+ 
+ 	ASSERT(pipes);
+ 	if (!pipes)
+@@ -2075,7 +2073,6 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
+ 			&context->res_ctx, pipes);
+ 
+ 	if (!pipe_cnt) {
+-		BW_VAL_TRACE_SKIP(pass);
+ 		out = true;
+ 		goto validate_out;
+ 	}
+@@ -2240,101 +2237,128 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
+ 	}
+ #endif
+ 
+-	BW_VAL_TRACE_END_VOLTAGE_LEVEL();
++	*vlevel_out = vlevel;
+ 
+-	if (fast_validate) {
+-		BW_VAL_TRACE_SKIP(fast);
+-		out = true;
+-		goto validate_out;
+-	}
++	out = true;
++	goto validate_out;
++
++validate_fail:
++	out = false;
++
++validate_out:
++	return out;
++}
++
++void dcn20_calculate_wm(
++		struct dc *dc, struct dc_state *context,
++		display_e2e_pipe_params_st *pipes,
++		int *out_pipe_cnt,
++		int *pipe_split_from,
++		int vlevel)
++{
++	int pipe_cnt, i, pipe_idx;
+ 
+ 	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
+-		if (!context->res_ctx.pipe_ctx[i].stream)
+-			continue;
++			if (!context->res_ctx.pipe_ctx[i].stream)
++				continue;
+ 
+-		pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
+-		pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
++			pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
++			pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
+ 
+-		if (pipe_split_from[i] < 0) {
+-			pipes[pipe_cnt].clks_cfg.dppclk_mhz =
+-					context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
+-			if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
+-				pipes[pipe_cnt].pipe.dest.odm_combine =
+-						context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
+-			else
+-				pipes[pipe_cnt].pipe.dest.odm_combine = 0;
+-			pipe_idx++;
+-		} else {
+-			pipes[pipe_cnt].clks_cfg.dppclk_mhz =
+-					context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
+-			if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
+-				pipes[pipe_cnt].pipe.dest.odm_combine =
+-						context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]];
++			if (pipe_split_from[i] < 0) {
++				pipes[pipe_cnt].clks_cfg.dppclk_mhz =
++						context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
++				if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
++					pipes[pipe_cnt].pipe.dest.odm_combine =
++							context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
++				else
++					pipes[pipe_cnt].pipe.dest.odm_combine = 0;
++				pipe_idx++;
++			} else {
++				pipes[pipe_cnt].clks_cfg.dppclk_mhz =
++						context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
++				if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
++					pipes[pipe_cnt].pipe.dest.odm_combine =
++							context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]];
++				else
++					pipes[pipe_cnt].pipe.dest.odm_combine = 0;
++			}
++
++			if (dc->config.forced_clocks) {
++				pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
++				pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
++			}
++
++			pipe_cnt++;
++		}
++
++		if (pipe_cnt != pipe_idx) {
++			if (dc->res_pool->funcs->populate_dml_pipes)
++				pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
++					&context->res_ctx, pipes);
+ 			else
+-				pipes[pipe_cnt].pipe.dest.odm_combine = 0;
++				pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
++					&context->res_ctx, pipes);
+ 		}
+-		if (dc->config.forced_clocks) {
+-			pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
+-			pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
++
++		*out_pipe_cnt = pipe_cnt;
++
++		pipes[0].clks_cfg.voltage = vlevel;
++		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
++		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
++
++		/* only pipe 0 is read for voltage and dcf/soc clocks */
++		if (vlevel < 1) {
++			pipes[0].clks_cfg.voltage = 1;
++			pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
++			pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
+ 		}
+-		pipe_cnt++;
+-	}
++		context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++		context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++		context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++		context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++		context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++
++		if (vlevel < 2) {
++			pipes[0].clks_cfg.voltage = 2;
++			pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
++			pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
++		}
++		context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++		context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++		context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++		context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++		context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++
++		if (vlevel < 3) {
++			pipes[0].clks_cfg.voltage = 3;
++			pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
++			pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
++		}
++		context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++		context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++		context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++		context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++		context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++
++		pipes[0].clks_cfg.voltage = vlevel;
++		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
++		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
++		context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++		context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++}
++
++void dcn20_calculate_dlg_params(
++		struct dc *dc, struct dc_state *context,
++		display_e2e_pipe_params_st *pipes,
++		int pipe_cnt,
++		int vlevel)
++{
++	int i, pipe_idx;
+ 
+-	if (pipe_cnt != pipe_idx) {
+-		if (dc->res_pool->funcs->populate_dml_pipes)
+-			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
+-				&context->res_ctx, pipes);
+-		else
+-			pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
+-				&context->res_ctx, pipes);
+-	}
+-
+-	pipes[0].clks_cfg.voltage = vlevel;
+-	pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
+-	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
+-
+-	/* only pipe 0 is read for voltage and dcf/soc clocks */
+-	if (vlevel < 1) {
+-		pipes[0].clks_cfg.voltage = 1;
+-		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
+-		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
+-	}
+-	context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-	context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-
+-	if (vlevel < 2) {
+-		pipes[0].clks_cfg.voltage = 2;
+-		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
+-		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
+-	}
+-	context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-	context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-
+-	if (vlevel < 3) {
+-		pipes[0].clks_cfg.voltage = 3;
+-		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
+-		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
+-	}
+-	context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-	context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-
+-	pipes[0].clks_cfg.voltage = vlevel;
+-	pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
+-	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
+-	context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-	context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ 	/* Writeback MCIF_WB arbitration parameters */
+ 	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
+ 
+@@ -2349,7 +2373,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
+ 							!= dm_dram_clock_change_unsupported;
+ 	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
+ 
+-	BW_VAL_TRACE_END_WATERMARKS();
++
+ 
+ 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+ 		if (!context->res_ctx.pipe_ctx[i].stream)
+@@ -2391,8 +2415,40 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
+ 				pipes[pipe_idx].pipe);
+ 		pipe_idx++;
+ 	}
++}
++
++bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
++		bool fast_validate)
++{
++	bool out = false;
++
++	BW_VAL_TRACE_SETUP();
++
++	int vlevel = 0;
++	int pipe_split_from[MAX_PIPES];
++	int pipe_cnt = 0;
++	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
++	DC_LOGGER_INIT(dc->ctx->logger);
++
++	BW_VAL_TRACE_COUNT();
++
++	out = dcn20_fast_validate_bw(dc, context, pipes, pipe_split_from, &vlevel);
++
++	if (!out)
++		goto validate_fail;
++
++	BW_VAL_TRACE_END_VOLTAGE_LEVEL();
++
++	if (fast_validate) {
++		BW_VAL_TRACE_SKIP(fast);
++		goto validate_out;
++	}
++
++	dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
++	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
++
++	BW_VAL_TRACE_END_WATERMARKS();
+ 
+-	out = true;
+ 	goto validate_out;
+ 
+ validate_fail:
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+index b5a75289f444..2b3692e0c48d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+@@ -116,6 +116,17 @@ void dcn20_set_mcif_arb_params(
+ 		display_e2e_pipe_params_st *pipes,
+ 		int pipe_cnt);
+ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate);
++bool dcn20_fast_validate_bw(
++		struct dc *dc,
++		struct dc_state *context,
++		display_e2e_pipe_params_st *pipes,
++		int *pipe_split_from,
++		int *vlevel_out);
++void dcn20_calculate_dlg_params(
++		struct dc *dc, struct dc_state *context,
++		display_e2e_pipe_params_st *pipes,
++		int pipe_cnt,
++		int vlevel);
+ 
+ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);
+ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+index 0835ac041acf..3c105124dcdd 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+@@ -64,6 +64,8 @@ enum dentist_divider_range {
+  ***************************************************************************************
+  */
+ 
++/* Macros */
++
+ #define TO_CLK_MGR_INTERNAL(clk_mgr)\
+ 	container_of(clk_mgr, struct clk_mgr_internal, base)
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3016-drm-amd-display-cap-DCFCLK-hardmin-to-507-for-NV10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3016-drm-amd-display-cap-DCFCLK-hardmin-to-507-for-NV10.patch
new file mode 100644
index 00000000..be76afdc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3016-drm-amd-display-cap-DCFCLK-hardmin-to-507-for-NV10.patch
@@ -0,0 +1,39 @@
+From 46af0f46f380d9006ccb3f2fa3c0b7da8958bfa5 Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Mon, 3 Jun 2019 11:37:44 -0400
+Subject: [PATCH 3016/4256] drm/amd/display: cap DCFCLK hardmin to 507 for NV10
+
+[why]
+Due to limitation in SMU/PPLIB, it is not possible to know Fmax @ Vmin for DCFCLK.
+This causes issues at high display configurations where extra headroom of DCFCLK
+can enable P-state switching
+
+[how]
+Use existing override logic.  If override not defined, then force
+min = 507
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 842f48403226..d07d35a9dd0a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2704,6 +2704,10 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_
+ 
+ 	if (dc->bb_overrides.min_dcfclk_mhz > 0)
+ 		min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
++	else
++		// Accounting for SOC/DCF relationship, we can go as high as
++		// 506Mhz in Vmin.  We need to code 507 since SMU will round down to 506.
++		min_dcfclk = 507;
+ 
+ 	for (i = 0; i < num_states; i++) {
+ 		int min_fclk_required_by_uclk;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3017-drm-amd-display-No-audio-endpoint-for-Dell-MST-displ.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3017-drm-amd-display-No-audio-endpoint-for-Dell-MST-displ.patch
new file mode 100644
index 00000000..643d3197
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3017-drm-amd-display-No-audio-endpoint-for-Dell-MST-displ.patch
@@ -0,0 +1,55 @@
+From 60171cb83f2722df1279f0775031f0082a375051 Mon Sep 17 00:00:00 2001
+From: Harmanprit Tatla <harmanprit.tatla@amd.com>
+Date: Tue, 4 Jun 2019 14:12:21 -0400
+Subject: [PATCH 3017/4256] drm/amd/display: No audio endpoint for Dell MST
+ display
+
+[Why]
+There are certain MST displays (i.e. Dell P2715Q)
+that although have the MST feature set to off may still
+report it is a branch device and a non-zero
+value for downstream port present.
+This can lead to us incorrectly classifying a
+dp dongle connection as being active and
+disabling the audio endpoint for the display.
+
+[How]
+Modified the placement and
+condition used to assign
+the is_branch_dev bit.
+
+Signed-off-by: Harmanprit Tatla <harmanprit.tatla@amd.com>
+Reviewed-by: Aric Cyr <aric.cyr@amd.com>
+Acked-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 3f8a8f61cd76..fca1bfc901b6 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2369,11 +2369,18 @@ static void get_active_converter_info(
+ 		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
+ 		ddc_service_set_dongle_type(link->ddc,
+ 				link->dpcd_caps.dongle_type);
++		link->dpcd_caps.is_branch_dev = false;
+ 		return;
+ 	}
+ 
+ 	/* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
+-	link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
++	if (ds_port.fields.PORT_TYPE == DOWNSTREAM_DP) {
++		link->dpcd_caps.is_branch_dev = false;
++	}
++
++	else {
++		link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
++	}
+ 
+ 	switch (ds_port.fields.PORT_TYPE) {
+ 	case DOWNSTREAM_VGA:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3018-drm-amd-display-Add-aux-tracing-log-in-dce.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3018-drm-amd-display-Add-aux-tracing-log-in-dce.patch
new file mode 100644
index 00000000..3a118663
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3018-drm-amd-display-Add-aux-tracing-log-in-dce.patch
@@ -0,0 +1,57 @@
+From 687b0b628e362665779368eafd671cb585099848 Mon Sep 17 00:00:00 2001
+From: Chiawen Huang <chiawen.huang@amd.com>
+Date: Tue, 14 May 2019 16:16:11 +0800
+Subject: [PATCH 3018/4256] drm/amd/display: Add aux tracing log in dce
+
+[Why]
+dce was re-arch'd, therefore adding aux tracing log into new dce
+
+[How]
+The porting from submit_channel_request/process_channel_reply of aux_engine_dce110.c
+
+Signed-off-by: Chiawen Huang <chiawen.huang@amd.com>
+Reviewed-by: Tony Cheng <tong.cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+index bd33c47183fc..79a16942ce98 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+@@ -27,6 +27,7 @@
+ #include "core_types.h"
+ #include "dce_aux.h"
+ #include "dce/dce_11_0_sh_mask.h"
++#include "dm_event_log.h"
+ 
+ #define CTX \
+ 	aux110->base.ctx
+@@ -249,6 +250,8 @@ static void submit_channel_request(
+ 	}
+ 
+ 	REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);
++	EVENT_LOG_AUX_REQ(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_NATIVE,
++					request->action, request->address, request->length, request->data);
+ }
+ 
+ static int read_channel_reply(struct dce_aux *engine, uint32_t size,
+@@ -477,9 +480,13 @@ int dce_aux_transfer_raw(struct ddc_service *ddc,
+ 	*operation_result = get_channel_status(aux_engine, &returned_bytes);
+ 
+ 	if (*operation_result == AUX_CHANNEL_OPERATION_SUCCEEDED) {
+-		read_channel_reply(aux_engine, payload->length,
++		int bytes_replied = 0;
++		bytes_replied = read_channel_reply(aux_engine, payload->length,
+ 					 payload->data, payload->reply,
+ 					 &status);
++		EVENT_LOG_AUX_REP(aux_engine->ddc->pin_data->en,
++					EVENT_LOG_AUX_ORIGIN_NATIVE, *payload->reply,
++					bytes_replied, payload->data);
+ 		res = returned_bytes;
+ 	} else {
+ 		res = -1;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3019-drm-amd-display-Update-drm_dsc-to-reflect-native-4.2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3019-drm-amd-display-Update-drm_dsc-to-reflect-native-4.2.patch
new file mode 100644
index 00000000..c039b79d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3019-drm-amd-display-Update-drm_dsc-to-reflect-native-4.2.patch
@@ -0,0 +1,142 @@
+From a7cf3feb831962e5808d200c19e2618be14f99de Mon Sep 17 00:00:00 2001
+From: David Francis <David.Francis@amd.com>
+Date: Tue, 4 Jun 2019 16:05:14 -0400
+Subject: [PATCH 3019/4256] drm/amd/display: Update drm_dsc to reflect native
+ 4.2.0 DSC spec
+
+[Why]
+Some parts of the DSC spec relating to 4.2.0 were not reflected in
+drm_dsc_compute_rc_parameters, causing unexpected config failures
+
+[How]
+Add nsl_bpg_offset and rbs_min computation
+
+Signed-off-by: David Francis <David.Francis@amd.com>
+Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c   | 73 ++++++++++++++++++-
+ 1 file changed, 69 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c b/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c
+index 67089765780b..04c6295f296e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c
++++ b/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c
+@@ -15,6 +15,7 @@
+ #define ERANGE			-1
+ #define DRM_DEBUG_KMS(msg)	/* nothing */
+ #define cpu_to_be16(__x) little_to_big(__x)
++#define MAX(x, y)		((x) > (y) ? (x) : (y))
+ 
+ static unsigned short little_to_big(int data)
+ {
+@@ -232,6 +233,38 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
+ }
+ EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
+ 
++static int compute_offset(struct drm_dsc_config *vdsc_cfg, int pixels_per_group,
++				int groups_per_line, int grpcnt)
++{
++	int offset = 0;
++	int grpcnt_id = DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay, pixels_per_group);
++
++	if (grpcnt <= grpcnt_id)
++		offset = DIV_ROUND_UP(grpcnt * pixels_per_group * vdsc_cfg->bits_per_pixel, 16);
++	else
++		offset = DIV_ROUND_UP(grpcnt_id * pixels_per_group * vdsc_cfg->bits_per_pixel, 16)
++			- (((grpcnt - grpcnt_id) * vdsc_cfg->slice_bpg_offset) >> 11);
++
++	if (grpcnt <= groups_per_line)
++		offset += grpcnt * vdsc_cfg->first_line_bpg_offset;
++	else
++		offset += groups_per_line * vdsc_cfg->first_line_bpg_offset
++			- (((grpcnt - groups_per_line) * vdsc_cfg->nfl_bpg_offset) >> 11);
++
++	if (vdsc_cfg->native_420) {
++		if (grpcnt <= groups_per_line)
++			offset -= (grpcnt * vdsc_cfg->nsl_bpg_offset) >> 11;
++		else if (grpcnt <= 2 * groups_per_line)
++			offset += (grpcnt - groups_per_line) * vdsc_cfg->second_line_bpg_offset
++				- ((groups_per_line * vdsc_cfg->nsl_bpg_offset) >> 11);
++		else
++			offset += (grpcnt - groups_per_line) * vdsc_cfg->second_line_bpg_offset
++				- (((grpcnt - groups_per_line) * vdsc_cfg->nsl_bpg_offset) >> 11);
++	}
++
++	return offset;
++}
++
+ /**
+  * drm_dsc_compute_rc_parameters() - Write rate control
+  * parameters to the dsc configuration defined in
+@@ -251,6 +284,7 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
+ 	unsigned long hrd_delay = 0;
+ 	unsigned long final_scale = 0;
+ 	unsigned long rbs_min = 0;
++	unsigned long max_offset = 0;
+ 
+ 	if (vdsc_cfg->native_420 || vdsc_cfg->native_422) {
+ 		/* Number of groups used to code each line of a slice */
+@@ -329,6 +363,17 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
+ 		return -ERANGE;
+ 	}
+ 
++	if (vdsc_cfg->slice_height > 2)
++		vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->second_line_bpg_offset << 11),
++							(vdsc_cfg->slice_height - 1));
++	else
++		vdsc_cfg->nsl_bpg_offset = 0;
++
++	if (vdsc_cfg->nsl_bpg_offset > 65535) {
++		DRM_DEBUG_KMS("NslBpgOffset is too large for this slice height\n");
++		return -ERANGE;
++	}
++
+ 	/* Number of groups used to code the entire slice */
+ 	groups_total = groups_per_line * vdsc_cfg->slice_height;
+ 
+@@ -348,6 +393,7 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
+ 		vdsc_cfg->scale_increment_interval =
+ 				(vdsc_cfg->final_offset * (1 << 11)) /
+ 				((vdsc_cfg->nfl_bpg_offset +
++				vdsc_cfg->nsl_bpg_offset +
+ 				vdsc_cfg->slice_bpg_offset) *
+ 				(final_scale - 9));
+ 	} else {
+@@ -368,10 +414,29 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
+ 	 * bits/pixel (bpp) rate that is used by the encoder,
+ 	 * in steps of 1/16 of a bit per pixel
+ 	 */
+-	rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
+-		DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
+-			     vdsc_cfg->bits_per_pixel, 16) +
+-		groups_per_line * vdsc_cfg->first_line_bpg_offset;
++	if (vdsc_cfg->dsc_version_minor == 2 && (vdsc_cfg->native_420 || vdsc_cfg->native_422)) {
++
++		max_offset = compute_offset(vdsc_cfg, DSC_RC_PIXELS_PER_GROUP, groups_per_line,
++					DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay,
++						DSC_RC_PIXELS_PER_GROUP));
++
++		max_offset = MAX(max_offset,
++				compute_offset(vdsc_cfg, DSC_RC_PIXELS_PER_GROUP, groups_per_line,
++					DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay,
++						groups_per_line)));
++
++		max_offset = MAX(max_offset,
++				compute_offset(vdsc_cfg, DSC_RC_PIXELS_PER_GROUP, groups_per_line,
++					DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay,
++						groups_per_line * 2)));
++
++		rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + max_offset;
++	} else {
++		rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
++			DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
++				     vdsc_cfg->bits_per_pixel, 16) +
++			groups_per_line * vdsc_cfg->first_line_bpg_offset;
++	}
+ 
+ 	hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
+ 	vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3020-drm-amd-display-early-return-when-pipe_cnt-is-0-in-b.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3020-drm-amd-display-early-return-when-pipe_cnt-is-0-in-b.patch
new file mode 100644
index 00000000..e7e2f4d6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3020-drm-amd-display-early-return-when-pipe_cnt-is-0-in-b.patch
@@ -0,0 +1,71 @@
+From f216519d24cefc2f52f5a238da064fc5b6f14767 Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Tue, 4 Jun 2019 18:14:43 -0400
+Subject: [PATCH 3020/4256] drm/amd/display: early return when pipe_cnt is 0 in
+ bw validation
+
+[Why]
+Unintentionally introduced behaviour change from previous refactor,
+which causes clks to be 0 in no stream cases, which will cause
+divide by 0.
+
+[How]
+Skip calculation of clocks when no stream. Which is the same as old
+behaviour.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Tony Cheng <tong.cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 8 +++++++-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h | 1 +
+ 2 files changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index d07d35a9dd0a..022d0f38723b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2020,6 +2020,7 @@ bool dcn20_fast_validate_bw(
+ 		struct dc *dc,
+ 		struct dc_state *context,
+ 		display_e2e_pipe_params_st *pipes,
++		int *pipe_cnt_out,
+ 		int *pipe_split_from,
+ 		int *vlevel_out)
+ {
+@@ -2072,6 +2073,8 @@ bool dcn20_fast_validate_bw(
+ 		pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
+ 			&context->res_ctx, pipes);
+ 
++	*pipe_cnt_out = pipe_cnt;
++
+ 	if (!pipe_cnt) {
+ 		out = true;
+ 		goto validate_out;
+@@ -2432,7 +2435,10 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
+ 
+ 	BW_VAL_TRACE_COUNT();
+ 
+-	out = dcn20_fast_validate_bw(dc, context, pipes, pipe_split_from, &vlevel);
++	out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
++
++	if (pipe_cnt == 0)
++		goto validate_out;
+ 
+ 	if (!out)
+ 		goto validate_fail;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+index 2b3692e0c48d..44f95aa0d61e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+@@ -120,6 +120,7 @@ bool dcn20_fast_validate_bw(
+ 		struct dc *dc,
+ 		struct dc_state *context,
+ 		display_e2e_pipe_params_st *pipes,
++		int *pipe_cnt_out,
+ 		int *pipe_split_from,
+ 		int *vlevel_out);
+ void dcn20_calculate_dlg_params(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3021-drm-amd-display-Set-default-block_size-even-in-unexp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3021-drm-amd-display-Set-default-block_size-even-in-unexp.patch
new file mode 100644
index 00000000..a54e57ca
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3021-drm-amd-display-Set-default-block_size-even-in-unexp.patch
@@ -0,0 +1,45 @@
+From a184885fe5c3b08ddd60f516c38e1637c657bbdb Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Tue, 4 Jun 2019 14:48:33 -0400
+Subject: [PATCH 3021/4256] drm/amd/display: Set default block_size, even in
+ unexpected cases
+
+We're not expected to enter the default case, but not returning a
+default value here is incorrect.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 1 +
+ drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h    | 2 +-
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+index c72a9ff57f15..6e2dbd03f9bf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+@@ -337,6 +337,7 @@ static enum dcn_hubbub_page_table_block_size page_table_block_size_to_hw(unsigne
+ 		break;
+ 	default:
+ 		ASSERT(false);
++		block_size = page_table_block_size;
+ 		break;
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+index 1ea505f7a05a..9502478c4a1b 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+@@ -62,7 +62,7 @@ enum dcn_hubbub_page_table_depth {
+ 
+ enum dcn_hubbub_page_table_block_size {
+ 	DCN_PAGE_TABLE_BLOCK_SIZE_4KB = 0,
+-	DCN_PAGE_TABLE_BLOCK_SIZE_64KB = 4
++	DCN_PAGE_TABLE_BLOCK_SIZE_64KB = 4,
+ };
+ 
+ struct dcn_hubbub_phys_addr_config {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3022-drm-amd-display-Set-one-4-2-0-related-PPS-field-as-r.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3022-drm-amd-display-Set-one-4-2-0-related-PPS-field-as-r.patch
new file mode 100644
index 00000000..221062a2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3022-drm-amd-display-Set-one-4-2-0-related-PPS-field-as-r.patch
@@ -0,0 +1,40 @@
+From 6162463ce6b40387effec15b11d4e6792d1e6e51 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Wed, 5 Jun 2019 14:29:47 -0400
+Subject: [PATCH 3022/4256] drm/amd/display: Set one 4:2:0-related PPS field as
+ recommended by DSC spec
+
+[why]
+'second_line_offset_adj' was mistakenly left at zero, even though DSC spec
+v1.2a recommends setting this field to 512 for 4:2:0.
+
+[how]
+Set 'second_line_offset_adj' to 512 for 4:2:0 and leave at zero otherwise
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c b/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c
+index 04c6295f296e..fd1fb1653479 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c
++++ b/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c
+@@ -442,6 +442,12 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
+ 	vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
+ 	vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
+ 
++	/* As per DSC spec v1.2a recommendation: */
++	if (vdsc_cfg->native_420)
++		vdsc_cfg->second_line_offset_adj = 512;
++	else
++		vdsc_cfg->second_line_offset_adj = 0;
++
+ 	return 0;
+ }
+ EXPORT_SYMBOL(drm_dsc_compute_rc_parameters);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3023-drm-amd-display-swap-system-aperture-high-low.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3023-drm-amd-display-swap-system-aperture-high-low.patch
new file mode 100644
index 00000000..9cc2d3a0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3023-drm-amd-display-swap-system-aperture-high-low.patch
@@ -0,0 +1,37 @@
+From 9b07d278f4fe8327730c3915582b73ce79819acd Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Wed, 5 Jun 2019 10:53:40 -0400
+Subject: [PATCH 3023/4256] drm/amd/display: swap system aperture high/low
+
+[why]
+Currently logical values are swapped in HW, causing
+system aperture to be undefined, so VA and PA cannot co-exist
+
+[how]
+program values correctly
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 45f9dad95644..8d3bc156de6f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1128,8 +1128,8 @@ void dcn20_enable_plane(
+ 
+ 		apt.sys_default.quad_part = 0;
+ 
+-		apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.start_addr;
+-		apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.end_addr;
++		apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
++		apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
+ 
+ 		// Program system aperture settings
+ 		pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3024-drm-amd-display-skip-retrain-in-dc_link_set_preferre.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3024-drm-amd-display-skip-retrain-in-dc_link_set_preferre.patch
new file mode 100644
index 00000000..36b24de9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3024-drm-amd-display-skip-retrain-in-dc_link_set_preferre.patch
@@ -0,0 +1,49 @@
+From bab52b2a79a219932a497777198c86614a467849 Mon Sep 17 00:00:00 2001
+From: Samson Tam <Samson.Tam@amd.com>
+Date: Tue, 4 Jun 2019 15:52:59 -0400
+Subject: [PATCH 3024/4256] drm/amd/display: skip retrain in
+ dc_link_set_preferred_link_settings() if using passive dongle
+
+[Why]
+Fixes issue when we have a display connected using a passive
+dongle and then emulate over it using a DP connection at 1 x 1.62 Ghz.
+System hangs because register bus returns back 0xFFFFFFFF for all
+register reads after setting register DIG_BE_CNTL in
+dcn10_link_encoder_connect_dig_be_to_fe().  Hang occurs later
+when trying to do a register read.
+
+[How]
+At the start of the emulation, dc_link_set_preferred_link_settings()
+and dp_retrain_link_dp_test() is called, even though it is connected
+using a passive dongle.
+
+Add an extra condition in dp_retrain_link_dp_test() to check for
+link->dongle_max_pix_clk > 0.  This is the only way we know if the
+connection is using passive dongle so we don't retrain DP.
+
+Signed-off-by: Samson Tam <Samson.Tam@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index accd0f72e03f..551fff68a5dc 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2998,8 +2998,10 @@ void dc_link_set_preferred_link_settings(struct dc *dc,
+ 
+ 	/* Retrain with preferred link settings only relevant for
+ 	 * DP signal type
++	 * Check for non-DP signal or if passive dongle present
+ 	 */
+-	if (!dc_is_dp_signal(link->connector_signal))
++	if (!dc_is_dp_signal(link->connector_signal) ||
++		link->dongle_max_pix_clk > 0)
+ 		return;
+ 
+ 	for (i = 0; i < MAX_PIPES; i++) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3025-drm-amd-display-Split-out-common-HUBP-registers-and-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3025-drm-amd-display-Split-out-common-HUBP-registers-and-.patch
new file mode 100644
index 00000000..4d4ca082
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3025-drm-amd-display-Split-out-common-HUBP-registers-and-.patch
@@ -0,0 +1,342 @@
+From 9a458db365cb2222f2c6e0417630ce8eb7829622 Mon Sep 17 00:00:00 2001
+From: Charlene Liu <charlene.liu@amd.com>
+Date: Wed, 5 Jun 2019 15:21:03 -0400
+Subject: [PATCH 3025/4256] drm/amd/display: Split out common HUBP registers
+ and code
+
+There are shared regs and code across DCN generations. Pull them out
+into a shared common location.
+
+Also, expose some dcn20 init functions.
+
+Signed-off-by: Charlene Liu <charlene.liu@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dce/dce_hwseq.h    |  3 +-
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 50 ++++++++++++-------
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 23 ++++++---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 23 +++++----
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 43 +++++++++++++++-
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.h    | 14 ++----
+ 6 files changed, 109 insertions(+), 47 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+index cb0a037b1c4a..3a49f1ffb5dd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+@@ -696,7 +696,8 @@ struct dce_hwseq_registers {
+ 	type D2VGA_MODE_ENABLE; \
+ 	type D3VGA_MODE_ENABLE; \
+ 	type D4VGA_MODE_ENABLE; \
+-	type AZALIA_AUDIO_DTO_MODULE;
++	type AZALIA_AUDIO_DTO_MODULE;\
++	type HPO_HDMISTREAMCLK_GATE_DIS;
+ 
+ struct dce_hwseq_shift {
+ 	HWSEQ_REG_FIELD_LIST(uint8_t)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+index 934bacc0c6ad..a16128814d62 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+@@ -843,7 +843,7 @@ void min_set_viewport(
+ 		  PRI_VIEWPORT_Y_START_C, viewport_c->y);
+ }
+ 
+-void hubp1_read_state(struct hubp *hubp)
++void hubp1_read_state_common(struct hubp *hubp)
+ {
+ 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
+ 	struct dcn_hubp_state *s = &hubp1->state;
+@@ -859,24 +859,6 @@ void hubp1_read_state(struct hubp *hubp)
+ 			PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
+ 			MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
+ 			CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
+-	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
+-		CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
+-		MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
+-		META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
+-		MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
+-		DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
+-		MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
+-		SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
+-		PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
+-	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
+-		CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
+-		MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
+-		META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
+-		MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
+-		DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
+-		MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
+-		SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
+-		PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
+ 
+ 	/* DLG - Per hubp */
+ 	REG_GET_2(BLANK_OFFSET_0,
+@@ -1030,8 +1012,38 @@ void hubp1_read_state(struct hubp *hubp)
+ 	REG_GET_2(DCN_TTU_QOS_WM,
+ 			QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
+ 			QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
++
+ }
+ 
++void hubp1_read_state(struct hubp *hubp)
++{
++	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
++	struct dcn_hubp_state *s = &hubp1->state;
++	struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
++
++	hubp1_read_state_common(hubp);
++
++	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
++		CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
++		MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
++		META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
++		MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
++		DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
++		MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
++		SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
++		PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
++
++	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
++		CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
++		MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
++		META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
++		MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
++		DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
++		MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
++		SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
++		PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
++
++}
+ enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch)
+ {
+ 	enum cursor_pitch hw_pitch;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+index 31c8fdd3206c..8f4bcdc74116 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+@@ -249,7 +249,8 @@
+ 	.field_name = reg_name ## __ ## field_name ## post_fix
+ 
+ /* Mask/shift struct generation macro for all ASICs (including those with reduced functionality) */
+-#define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)\
++/*1.x, 2.x, and 3.x*/
++#define HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh)\
+ 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
+ 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
+ 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
+@@ -265,7 +266,6 @@
+ 	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
+ 	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
+ 	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
+-	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
+ 	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
+@@ -372,12 +372,17 @@
+ 	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
+ 	HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh)
+-
+-#define HUBP_MASK_SH_LIST_DCN(mask_sh)\
+-	HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh),\
++/*2.x and 1.x only*/
++#define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)\
++	HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\
++	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
+ 	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
+ 	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh)
+ 
++/*2.x and 1.x only*/
++#define HUBP_MASK_SH_LIST_DCN(mask_sh)\
++	HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)
++
+ /* Mask/shift struct generation macro for ASICs with VM */
+ #define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\
+ 	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
+@@ -434,7 +439,7 @@
+ 	HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
+ 	HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
+ 
+-#define DCN_HUBP_REG_FIELD_LIST(type) \
++#define DCN_HUBP_REG_FIELD_BASE_LIST(type) \
+ 	type HUBP_BLANK_EN;\
+ 	type HUBP_DISABLE;\
+ 	type HUBP_TTU_DISABLE;\
+@@ -459,7 +464,6 @@
+ 	type ROTATION_ANGLE;\
+ 	type H_MIRROR_EN;\
+ 	type SURFACE_PIXEL_FORMAT;\
+-	type ALPHA_PLANE_EN;\
+ 	type SURFACE_FLIP_TYPE;\
+ 	type SURFACE_FLIP_MODE_FOR_STEREOSYNC;\
+ 	type SURFACE_FLIP_IN_STEREOSYNC;\
+@@ -632,6 +636,10 @@
+ 	type CURSOR_DST_X_OFFSET; \
+ 	type OUTPUT_FP
+ 
++#define DCN_HUBP_REG_FIELD_LIST(type) \
++	DCN_HUBP_REG_FIELD_BASE_LIST(type);\
++	type ALPHA_PLANE_EN
++
+ struct dcn_mi_registers {
+ 	HUBP_COMMON_REG_VARIABLE_LIST;
+ };
+@@ -760,5 +768,6 @@ void hubp1_vready_workaround(struct hubp *hubp,
+ 		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
+ 
+ void hubp1_init(struct hubp *hubp);
++void hubp1_read_state_common(struct hubp *hubp);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+index d5acc348be22..2c6405a62fc1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+@@ -72,8 +72,8 @@
+ 	SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
+ 	SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB)
+ 
+-#define HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh)\
+-	HUBP_MASK_SH_LIST_DCN(mask_sh),\
++#define HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh)\
++	HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\
+ 	HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
+ 	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
+ 	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
+@@ -127,13 +127,21 @@
+ 	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh)
+ 
++/*DCN2.x and DCN1.x*/
++#define HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh)\
++	HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh),\
++	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
++	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
++	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh)
++
++/*DCN2.0 specific*/
+ #define HUBP_MASK_SH_LIST_DCN20(mask_sh)\
+ 	HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh),\
+ 	HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
+ 	HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
+ 	HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh)
+ 
+-
++/*DCN2.x */
+ #define DCN2_HUBP_REG_COMMON_VARIABLE_LIST \
+ 	HUBP_COMMON_REG_VARIABLE_LIST; \
+ 	uint32_t DMDATA_ADDRESS_HIGH; \
+@@ -149,14 +157,11 @@
+ 	uint32_t FLIP_PARAMETERS_2;\
+ 	uint32_t DCN_CUR1_TTU_CNTL0;\
+ 	uint32_t DCN_CUR1_TTU_CNTL1;\
+-	uint32_t VMID_SETTINGS_0;\
+-	uint32_t FLIP_PARAMETERS_3;\
+-	uint32_t FLIP_PARAMETERS_4;\
+-	uint32_t VBLANK_PARAMETERS_5;\
+-	uint32_t VBLANK_PARAMETERS_6
++	uint32_t VMID_SETTINGS_0
++
+ 
+ #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
+-	DCN_HUBP_REG_FIELD_LIST(type); \
++	DCN_HUBP_REG_FIELD_BASE_LIST(type); \
+ 	type DMDATA_ADDRESS_HIGH;\
+ 	type DMDATA_MODE;\
+ 	type DMDATA_UPDATED;\
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 8d3bc156de6f..f820e9667e3c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -115,7 +115,7 @@ static void enable_power_gating_plane(
+ 	REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
+ }
+ 
+-static void dcn20_dccg_init(struct dce_hwseq *hws)
++void dcn20_dccg_init(struct dce_hwseq *hws)
+ {
+ 	/*
+ 	 * set MICROSECOND_TIME_BASE_DIV
+@@ -138,6 +138,45 @@ static void dcn20_dccg_init(struct dce_hwseq *hws)
+ 	/* This value is dependent on the hardware pipeline delay so set once per SOC */
+ 	REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
+ }
++void dcn20_display_init(struct dc *dc)
++{
++	struct dce_hwseq *hws = dc->hwseq;
++
++	/* RBBMIF
++	 * disable RBBMIF timeout detection for all clients
++	 * Ensure RBBMIF does not drop register accesses due to the per-client timeout
++	 */
++	REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
++	REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
++
++	/* DCCG */
++	dcn20_dccg_init(hws);
++
++	/* Disable all memory low power mode. All memories are enabled. */
++	REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 1);
++
++	/* DCHUB/MMHUBBUB
++	 * set global timer refclk divider
++	 * 100Mhz refclk -> 2
++	 * 27Mhz refclk ->  1
++	 * 48Mhz refclk ->  1
++	 */
++	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
++	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
++	REG_WRITE(REFCLK_CNTL, 0);
++
++	/* OPTC
++	 * OTG_CONTROL.OTG_DISABLE_POINT_CNTL = 0x3; will be set during optc2_enable_crtc
++	 */
++
++	/* AZ
++	 * default value is 0x64 for 100Mhz ref clock, if the ref clock is 100Mhz, no need to program this regiser,
++	 * if not, it should be programmed according to the ref clock
++	 */
++	REG_UPDATE(AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, 0x64);
++	/* Enable controller clock gating */
++	REG_WRITE(AZALIA_CONTROLLER_CLOCK_GATING, 0x1);
++}
+ 
+ static void disable_vga(
+ 	struct dce_hwseq *hws)
+@@ -163,7 +202,7 @@ void dcn20_program_tripleBuffer(
+ }
+ 
+ /* Blank pixel data during initialization */
+-static void dcn20_init_blank(
++void dcn20_init_blank(
+ 		struct dc *dc,
+ 		struct timing_generator *tg)
+ {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+index 2b0409454073..689c2765b071 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+@@ -91,13 +91,9 @@ void dcn20_pipe_control_lock_global(
+ void dcn20_setup_gsl_group_as_lock(const struct dc *dc,
+ 				struct pipe_ctx *pipe_ctx,
+ 				bool enable);
+-void dcn20_pipe_control_lock(
+-	struct dc *dc,
+-	struct pipe_ctx *pipe,
+-	bool lock);
+-void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
+-void dcn20_enable_plane(
+-	struct dc *dc,
+-	struct pipe_ctx *pipe_ctx,
+-	struct dc_state *context);
++void dcn20_dccg_init(struct dce_hwseq *hws);
++void dcn20_init_blank(
++	   struct dc *dc,
++	   struct timing_generator *tg);
++void dcn20_display_init(struct dc *dc);
+ #endif /* __DC_HWSS_DCN20_H__ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3026-drm-amd-display-3.2.38.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3026-drm-amd-display-3.2.38.patch
new file mode 100644
index 00000000..1145ed59
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3026-drm-amd-display-3.2.38.patch
@@ -0,0 +1,27 @@
+From 47f96e8fd679afdaacfdb62415cb202752ab3514 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Mon, 10 Jun 2019 08:49:36 -0400
+Subject: [PATCH 3026/4256] drm/amd/display: 3.2.38
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 6462db311e97..a8ecd93a1063 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -42,7 +42,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.37"
++#define DC_VER "3.2.38"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3027-drm-amd-display-Incorrect-Read-Interval-Time-For-CR-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3027-drm-amd-display-Incorrect-Read-Interval-Time-For-CR-.patch
new file mode 100644
index 00000000..f376f1b9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3027-drm-amd-display-Incorrect-Read-Interval-Time-For-CR-.patch
@@ -0,0 +1,37 @@
+From 4030f2ec229dc865a012c894f7695094018510de Mon Sep 17 00:00:00 2001
+From: David Galiffi <david.galiffi@amd.com>
+Date: Fri, 7 Jun 2019 21:32:34 -0400
+Subject: [PATCH 3027/4256] drm/amd/display: Incorrect Read Interval Time For
+ CR Sequence
+
+[WHY]
+TRAINING_AUX_RD_INTERVAL (DPCD 000Eh) modifies the read interval
+for the EQ training sequence. CR read interval should remain 100 us.
+Currently, the CR interval is also being modified.
+
+[HOW]
+lt_settings->cr_pattern_time should always be 100 us.
+
+Signed-off-by: David Galiffi <david.galiffi@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index fca1bfc901b6..4442e7b1e5b5 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -1035,7 +1035,7 @@ static void initialize_training_settings(
+ 	if (link->preferred_training_settings.cr_pattern_time != NULL)
+ 		lt_settings->cr_pattern_time = *link->preferred_training_settings.cr_pattern_time;
+ 	else
+-		lt_settings->cr_pattern_time = get_training_aux_rd_interval(link, 100);
++		lt_settings->cr_pattern_time = 100;
+ 
+ 	if (link->preferred_training_settings.eq_pattern_time != NULL)
+ 		lt_settings->eq_pattern_time = *link->preferred_training_settings.eq_pattern_time;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3028-drm-amd-display-Clock-does-not-lower-in-Updateplanes.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3028-drm-amd-display-Clock-does-not-lower-in-Updateplanes.patch
new file mode 100644
index 00000000..109102f6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3028-drm-amd-display-Clock-does-not-lower-in-Updateplanes.patch
@@ -0,0 +1,41 @@
+From 287ff50c3bd0ff28fb7d305e294f3077bd35e653 Mon Sep 17 00:00:00 2001
+From: Murton Liu <murton.liu@amd.com>
+Date: Mon, 10 Jun 2019 17:55:28 -0400
+Subject: [PATCH 3028/4256] drm/amd/display: Clock does not lower in
+ Updateplanes
+
+[why]
+We reset the optimized_required in atomic_plane_disable
+flag immediately after it is set in atomic_plane_disconnect, causing us to
+never have flag set during next flip in UpdatePlanes.
+
+[how]
+Optimize directly after each time plane is removed.
+
+Signed-off-by: Murton Liu <murton.liu@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index af5f6a3dd61f..15ac6de3fd30 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2514,6 +2514,12 @@ static void dcn10_apply_ctx_for_surface(
+ 		if (removed_pipe[i])
+ 			dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
+ 
++	for (i = 0; i < dc->res_pool->pipe_count; i++)
++		if (removed_pipe[i]) {
++			dc->hwss.optimize_bandwidth(dc, context);
++			break;
++		}
++
+ 	if (dc->hwseq->wa.DEGVIDCN10_254)
+ 		hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3029-drm-amd-display-Copy-max_clks_by_state-after-dce_clk.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3029-drm-amd-display-Copy-max_clks_by_state-after-dce_clk.patch
new file mode 100644
index 00000000..c143415f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3029-drm-amd-display-Copy-max_clks_by_state-after-dce_clk.patch
@@ -0,0 +1,85 @@
+From a6fb89dc8bda4a9b9f39f513036ef37d5d67d24f Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Wed, 5 Jun 2019 15:02:04 -0400
+Subject: [PATCH 3029/4256] drm/amd/display: Copy max_clks_by_state after
+ dce_clk_mgr_construct
+
+[Why]
+For DCE110, DCE112 and DCE120 the max_clks_by_state for the clk_mgr are
+copied from their respective table before the call to
+dce_clk_mgr_construct, but then dce_clk_mgr_construct overwrites
+these with the dce80_max_clks_by_state.
+
+[How]
+Copy these after we call dce_clk_mgr_construct so we're using the
+right tables.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: David Francis <David.Francis@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c    | 4 ++--
+ .../gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c    | 4 ++--
+ .../gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c    | 4 ++--
+ 3 files changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+index c1a92c16535c..5cc3acccda2a 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+@@ -262,12 +262,12 @@ void dce110_clk_mgr_construct(
+ 		struct dc_context *ctx,
+ 		struct clk_mgr_internal *clk_mgr)
+ {
++	dce_clk_mgr_construct(ctx, clk_mgr);
++
+ 	memcpy(clk_mgr->max_clks_by_state,
+ 		dce110_max_clks_by_state,
+ 		sizeof(dce110_max_clks_by_state));
+ 
+-	dce_clk_mgr_construct(ctx, clk_mgr);
+-
+ 	clk_mgr->regs = &disp_clk_regs;
+ 	clk_mgr->clk_mgr_shift = &disp_clk_shift;
+ 	clk_mgr->clk_mgr_mask = &disp_clk_mask;
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+index 778392c73187..7c746ef1e32e 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+@@ -226,12 +226,12 @@ void dce112_clk_mgr_construct(
+ 		struct dc_context *ctx,
+ 		struct clk_mgr_internal *clk_mgr)
+ {
++	dce_clk_mgr_construct(ctx, clk_mgr);
++
+ 	memcpy(clk_mgr->max_clks_by_state,
+ 		dce112_max_clks_by_state,
+ 		sizeof(dce112_max_clks_by_state));
+ 
+-	dce_clk_mgr_construct(ctx, clk_mgr);
+-
+ 	clk_mgr->regs = &disp_clk_regs;
+ 	clk_mgr->clk_mgr_shift = &disp_clk_shift;
+ 	clk_mgr->clk_mgr_mask = &disp_clk_mask;
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
+index 906310c3e2eb..5399b8cf6b75 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c
+@@ -127,12 +127,12 @@ static struct clk_mgr_funcs dce120_funcs = {
+ 
+ void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr)
+ {
++	dce_clk_mgr_construct(ctx, clk_mgr);
++
+ 	memcpy(clk_mgr->max_clks_by_state,
+ 		dce120_max_clks_by_state,
+ 		sizeof(dce120_max_clks_by_state));
+ 
+-	dce_clk_mgr_construct(ctx, clk_mgr);
+-
+ 	clk_mgr->base.dprefclk_khz = 600000;
+ 	clk_mgr->base.funcs = &dce120_funcs;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3030-drm-amd-display-Use-Pixel-clock-in-100Hz-units-for-H.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3030-drm-amd-display-Use-Pixel-clock-in-100Hz-units-for-H.patch
new file mode 100644
index 00000000..3f3dec2c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3030-drm-amd-display-Use-Pixel-clock-in-100Hz-units-for-H.patch
@@ -0,0 +1,316 @@
+From 0052bb274197e3f3e6832242f9440692f64d057c Mon Sep 17 00:00:00 2001
+From: Nevenko Stupar <Nevenko.Stupar@amd.com>
+Date: Tue, 11 Jun 2019 17:35:16 -0400
+Subject: [PATCH 3030/4256] drm/amd/display:Use Pixel clock in 100Hz units for
+ HDMI Audio wall clock DTO
+
+[Why]
+-Pass and use pixel clock in 100 Hz to Audio for HDMI
+audio DTO for Audio wall clock programming so audio DTO gets
+increased precision for timings with /1001 factor.
+-For HDMI TMDS for N and CTS ACR tables are based on 10 KHz
+units, these does not need to be modified as N and CTS values
+are still valid using current tables.
+
+Signed-off-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dce/dce_audio.c    | 28 ++++++++---------
+ .../amd/display/dc/dce/dce_stream_encoder.c   | 30 +++++++++----------
+ .../display/dc/dce110/dce110_hw_sequencer.c   | 22 +++++++-------
+ .../display/dc/dcn10/dcn10_stream_encoder.c   | 30 +++++++++----------
+ .../display/dc/dcn10/dcn10_stream_encoder.h   |  4 +--
+ .../gpu/drm/amd/display/include/audio_types.h |  4 +--
+ 6 files changed, 59 insertions(+), 59 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+index d43d5d924c19..ad7bc7d44268 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+@@ -143,20 +143,20 @@ static void check_audio_bandwidth_hdmi(
+ 	if (channel_count > 2) {
+ 
+ 		/* Based on HDMI spec 1.3 Table 7.5 */
+-		if ((crtc_info->requested_pixel_clock <= 27000) &&
++		if ((crtc_info->requested_pixel_clock_100Hz <= 270000) &&
+ 		(crtc_info->v_active <= 576) &&
+ 		!(crtc_info->interlaced) &&
+ 		!(crtc_info->pixel_repetition == 2 ||
+ 		crtc_info->pixel_repetition == 4)) {
+ 			limit_freq_to_48_khz = true;
+ 
+-		} else if ((crtc_info->requested_pixel_clock <= 27000) &&
++		} else if ((crtc_info->requested_pixel_clock_100Hz <= 270000) &&
+ 				(crtc_info->v_active <= 576) &&
+ 				(crtc_info->interlaced) &&
+ 				(crtc_info->pixel_repetition == 2)) {
+ 			limit_freq_to_88_2_khz = true;
+ 
+-		} else if ((crtc_info->requested_pixel_clock <= 54000) &&
++		} else if ((crtc_info->requested_pixel_clock_100Hz <= 540000) &&
+ 				(crtc_info->v_active <= 576) &&
+ 				!(crtc_info->interlaced)) {
+ 			limit_freq_to_174_4_khz = true;
+@@ -735,8 +735,8 @@ void dce_aud_az_configure(
+ 
+ /* search pixel clock value for Azalia HDMI Audio */
+ static void get_azalia_clock_info_hdmi(
+-	uint32_t crtc_pixel_clock_in_khz,
+-	uint32_t actual_pixel_clock_in_khz,
++	uint32_t crtc_pixel_clock_100hz,
++	uint32_t actual_pixel_clock_100Hz,
+ 	struct azalia_clock_info *azalia_clock_info)
+ {
+ 	/* audio_dto_phase= 24 * 10,000;
+@@ -747,11 +747,11 @@ static void get_azalia_clock_info_hdmi(
+ 	/* audio_dto_module = PCLKFrequency * 10,000;
+ 	 *  [khz] -> [100Hz] */
+ 	azalia_clock_info->audio_dto_module =
+-			actual_pixel_clock_in_khz * 10;
++			actual_pixel_clock_100Hz;
+ }
+ 
+ static void get_azalia_clock_info_dp(
+-	uint32_t requested_pixel_clock_in_khz,
++	uint32_t requested_pixel_clock_100Hz,
+ 	const struct audio_pll_info *pll_info,
+ 	struct azalia_clock_info *azalia_clock_info)
+ {
+@@ -790,15 +790,15 @@ void dce_aud_wall_dto_setup(
+ 
+ 		/* calculate DTO settings */
+ 		get_azalia_clock_info_hdmi(
+-			crtc_info->requested_pixel_clock,
+-			crtc_info->calculated_pixel_clock,
++			crtc_info->requested_pixel_clock_100Hz,
++			crtc_info->calculated_pixel_clock_100Hz,
+ 			&clock_info);
+ 
+-		DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock = %d"\
+-				"calculated_pixel_clock =%d\n"\
++		DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\
++				"calculated_pixel_clock_100Hz =%d\n"\
+ 				"audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
+-				crtc_info->requested_pixel_clock,\
+-				crtc_info->calculated_pixel_clock,\
++				crtc_info->requested_pixel_clock_100Hz,\
++				crtc_info->calculated_pixel_clock_100Hz,\
+ 				clock_info.audio_dto_module,\
+ 				clock_info.audio_dto_phase);
+ 
+@@ -831,7 +831,7 @@ void dce_aud_wall_dto_setup(
+ 
+ 		calculate DTO settings */
+ 		get_azalia_clock_info_dp(
+-			crtc_info->requested_pixel_clock,
++			crtc_info->requested_pixel_clock_100Hz,
+ 			pll_info,
+ 			&clock_info);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+index d13e05a1937d..bd353796b767 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+@@ -1249,13 +1249,13 @@ static uint32_t calc_max_audio_packets_per_line(
+ 
+ static void get_audio_clock_info(
+ 	enum dc_color_depth color_depth,
+-	uint32_t crtc_pixel_clock_in_khz,
+-	uint32_t actual_pixel_clock_in_khz,
++	uint32_t crtc_pixel_clock_100Hz,
++	uint32_t actual_pixel_clock_100Hz,
+ 	struct audio_clock_info *audio_clock_info)
+ {
+ 	const struct audio_clock_info *clock_info;
+ 	uint32_t index;
+-	uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
++	uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
+ 	uint32_t audio_array_size;
+ 
+ 	switch (color_depth) {
+@@ -1292,16 +1292,16 @@ static void get_audio_clock_info(
+ 	}
+ 
+ 	/* not found */
+-	if (actual_pixel_clock_in_khz == 0)
+-		actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
++	if (actual_pixel_clock_100Hz == 0)
++		actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
+ 
+ 	/* See HDMI spec  the table entry under
+ 	 *  pixel clock of "Other". */
+ 	audio_clock_info->pixel_clock_in_10khz =
+-			actual_pixel_clock_in_khz / 10;
+-	audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
+-	audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
+-	audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
++			actual_pixel_clock_100Hz / 100;
++	audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
++	audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
++	audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
+ 
+ 	audio_clock_info->n_32khz = 4096;
+ 	audio_clock_info->n_44khz = 6272;
+@@ -1367,14 +1367,14 @@ static void dce110_se_setup_hdmi_audio(
+ 
+ 	/* Program audio clock sample/regeneration parameters */
+ 	get_audio_clock_info(crtc_info->color_depth,
+-			     crtc_info->requested_pixel_clock,
+-			     crtc_info->calculated_pixel_clock,
++			     crtc_info->requested_pixel_clock_100Hz,
++			     crtc_info->calculated_pixel_clock_100Hz,
+ 			     &audio_clock_info);
+ 	DC_LOG_HW_AUDIO(
+-			"\n%s:Input::requested_pixel_clock = %d"	\
+-			"calculated_pixel_clock = %d \n", __func__,	\
+-			crtc_info->requested_pixel_clock,		\
+-			crtc_info->calculated_pixel_clock);
++			"\n%s:Input::requested_pixel_clock_100Hz = %d"	\
++			"calculated_pixel_clock_100Hz = %d \n", __func__,	\
++			crtc_info->requested_pixel_clock_100Hz,		\
++			crtc_info->calculated_pixel_clock_100Hz);
+ 
+ 	/* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
+ 	REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 84d90b475e2a..6fa1f6b5375b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -1159,27 +1159,27 @@ static void build_audio_output(
+ 			stream->timing.flags.INTERLACE;
+ 
+ 	audio_output->crtc_info.refresh_rate =
+-		(stream->timing.pix_clk_100hz*10000)/
++		(stream->timing.pix_clk_100hz*100)/
+ 		(stream->timing.h_total*stream->timing.v_total);
+ 
+ 	audio_output->crtc_info.color_depth =
+ 		stream->timing.display_color_depth;
+ 
+-	audio_output->crtc_info.requested_pixel_clock =
+-			pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
++	audio_output->crtc_info.requested_pixel_clock_100Hz =
++			pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
+ 
+-	audio_output->crtc_info.calculated_pixel_clock =
+-			pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
++	audio_output->crtc_info.calculated_pixel_clock_100Hz =
++			pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
+ 
+ /*for HDMI, audio ACR is with deep color ratio factor*/
+ 	if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
+-		audio_output->crtc_info.requested_pixel_clock ==
+-				(stream->timing.pix_clk_100hz / 10)) {
++		audio_output->crtc_info.requested_pixel_clock_100Hz ==
++				(stream->timing.pix_clk_100hz)) {
+ 		if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
+-			audio_output->crtc_info.requested_pixel_clock =
+-					audio_output->crtc_info.requested_pixel_clock/2;
+-			audio_output->crtc_info.calculated_pixel_clock =
+-					pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/20;
++			audio_output->crtc_info.requested_pixel_clock_100Hz =
++					audio_output->crtc_info.requested_pixel_clock_100Hz/2;
++			audio_output->crtc_info.calculated_pixel_clock_100Hz =
++					pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;
+ 
+ 		}
+ 	}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+index 2d15ae664226..64adb9fb300c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+@@ -1195,13 +1195,13 @@ static union audio_cea_channels speakers_to_channels(
+ 
+ void get_audio_clock_info(
+ 	enum dc_color_depth color_depth,
+-	uint32_t crtc_pixel_clock_in_khz,
+-	uint32_t actual_pixel_clock_in_khz,
++	uint32_t crtc_pixel_clock_100Hz,
++	uint32_t actual_pixel_clock_100Hz,
+ 	struct audio_clock_info *audio_clock_info)
+ {
+ 	const struct audio_clock_info *clock_info;
+ 	uint32_t index;
+-	uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
++	uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
+ 	uint32_t audio_array_size;
+ 
+ 	switch (color_depth) {
+@@ -1238,16 +1238,16 @@ void get_audio_clock_info(
+ 	}
+ 
+ 	/* not found */
+-	if (actual_pixel_clock_in_khz == 0)
+-		actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
++	if (actual_pixel_clock_100Hz == 0)
++		actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
+ 
+ 	/* See HDMI spec  the table entry under
+ 	 *  pixel clock of "Other". */
+ 	audio_clock_info->pixel_clock_in_10khz =
+-			actual_pixel_clock_in_khz / 10;
+-	audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
+-	audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
+-	audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
++			actual_pixel_clock_100Hz / 100;
++	audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
++	audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
++	audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
+ 
+ 	audio_clock_info->n_32khz = 4096;
+ 	audio_clock_info->n_44khz = 6272;
+@@ -1307,14 +1307,14 @@ static void enc1_se_setup_hdmi_audio(
+ 
+ 	/* Program audio clock sample/regeneration parameters */
+ 	get_audio_clock_info(crtc_info->color_depth,
+-			     crtc_info->requested_pixel_clock,
+-			     crtc_info->calculated_pixel_clock,
++			     crtc_info->requested_pixel_clock_100Hz,
++			     crtc_info->calculated_pixel_clock_100Hz,
+ 			     &audio_clock_info);
+ 	DC_LOG_HW_AUDIO(
+-			"\n%s:Input::requested_pixel_clock = %d"	\
+-			"calculated_pixel_clock = %d \n", __func__,	\
+-			crtc_info->requested_pixel_clock,		\
+-			crtc_info->calculated_pixel_clock);
++			"\n%s:Input::requested_pixel_clock_100Hz = %d"	\
++			"calculated_pixel_clock_100Hz = %d \n", __func__,	\
++			crtc_info->requested_pixel_clock_100Hz,		\
++			crtc_info->calculated_pixel_clock_100Hz);
+ 
+ 	/* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
+ 	REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+index bc2b4af9543b..075e49c1283a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+@@ -605,8 +605,8 @@ void enc1_se_enable_dp_audio(
+ 
+ void get_audio_clock_info(
+ 	enum dc_color_depth color_depth,
+-	uint32_t crtc_pixel_clock_in_khz,
+-	uint32_t actual_pixel_clock_in_khz,
++	uint32_t crtc_pixel_clock_100Hz,
++	uint32_t actual_pixel_clock_100Hz,
+ 	struct audio_clock_info *audio_clock_info);
+ 
+ #endif /* __DC_STREAM_ENCODER_DCN10_H__ */
+diff --git a/drivers/gpu/drm/amd/display/include/audio_types.h b/drivers/gpu/drm/amd/display/include/audio_types.h
+index 6364fbc24cfe..66a54da0641c 100644
+--- a/drivers/gpu/drm/amd/display/include/audio_types.h
++++ b/drivers/gpu/drm/amd/display/include/audio_types.h
+@@ -38,8 +38,8 @@ struct audio_crtc_info {
+ 	uint32_t h_active;
+ 	uint32_t v_active;
+ 	uint32_t pixel_repetition;
+-	uint32_t requested_pixel_clock; /* in KHz */
+-	uint32_t calculated_pixel_clock; /* in KHz */
++	uint32_t requested_pixel_clock_100Hz; /* in 100Hz */
++	uint32_t calculated_pixel_clock_100Hz; /* in 100Hz */
+ 	uint32_t refresh_rate;
+ 	enum dc_color_depth color_depth;
+ 	bool interlaced;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3031-drm-amd-display-wait-for-the-whole-frame-after-globa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3031-drm-amd-display-wait-for-the-whole-frame-after-globa.patch
new file mode 100644
index 00000000..92c43283
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3031-drm-amd-display-wait-for-the-whole-frame-after-globa.patch
@@ -0,0 +1,39 @@
+From 897f1712316ef76df460d56c8d4aad22362bdcf9 Mon Sep 17 00:00:00 2001
+From: Wenjing Liu <Wenjing.Liu@amd.com>
+Date: Tue, 11 Jun 2019 18:18:36 -0400
+Subject: [PATCH 3031/4256] drm/amd/display: wait for the whole frame after
+ global unlock
+
+[why]
+The current code will not wait for the entire frame
+ after global unlock.
+This causes dsc dynamic target bpp update corruption when
+there is a surface update immediately happens after this.
+
+[how]
+Wait for the entire whole frame after unlock before continuing
+the rest of stream and surface update.
+
+Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index f820e9667e3c..7c08f81000c5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1256,6 +1256,8 @@ void dcn20_pipe_control_lock_global(
+ 				CRTC_STATE_VACTIVE);
+ 		pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
+ 				CRTC_STATE_VBLANK);
++		pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
++				CRTC_STATE_VACTIVE);
+ 		pipe->stream_res.tg->funcs->lock_doublebuffer_disable(
+ 				pipe->stream_res.tg);
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3032-drm-amd-display-refactor-dump_clk_registers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3032-drm-amd-display-refactor-dump_clk_registers.patch
new file mode 100644
index 00000000..e00a0922
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3032-drm-amd-display-refactor-dump_clk_registers.patch
@@ -0,0 +1,50 @@
+From 6a8047e707d1b36829d33843fc91259da7d093d7 Mon Sep 17 00:00:00 2001
+From: Su Sung Chung <Su.Chung@amd.com>
+Date: Wed, 22 May 2019 14:28:52 -0400
+Subject: [PATCH 3032/4256] drm/amd/display: refactor dump_clk_registers
+
+[why]
+for 2 purposes:
+
+1. get raw register value dumped on the log, which will make it easier
+to talk to other team who only knows about the register
+
+2. enable other HW to be able to use the same interface as raven to log
+clock register data
+
+Signed-off-by: Su Sung Chung <Su.Chung@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dm_services.h                    | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
+index 6e47444109d7..7f4766e45dff 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
+@@ -45,7 +45,7 @@
+ #include "dcn10_cm_common.h"
+ #include "clk_mgr.h"
+ 
+-static unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...)
++unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...)
+ {
+ 	unsigned int ret_vsnprintf;
+ 	unsigned int chars_printed;
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
+index b426ba02b793..1a0429744630 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
+@@ -151,6 +151,7 @@ void generic_reg_wait(const struct dc_context *ctx,
+ 	unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
+ 	const char *func_name, int line);
+ 
++unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...);
+ 
+ /* These macros need to be used with soc15 registers in order to retrieve
+  * the actual offset.
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3033-drm-amd-display-add-hdmi2.1-dsc-pps-packet-programmi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3033-drm-amd-display-add-hdmi2.1-dsc-pps-packet-programmi.patch
new file mode 100644
index 00000000..1d66c947
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3033-drm-amd-display-add-hdmi2.1-dsc-pps-packet-programmi.patch
@@ -0,0 +1,141 @@
+From 94a92a427e633a38290cef3bcb504204e67a6eea Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 5 Jun 2019 16:35:08 -0400
+Subject: [PATCH 3033/4256] drm/amd/display: add hdmi2.1 dsc pps packet
+ programming
+
+This change adds EMP packet programming for enabling dsc with
+hdmi. The packets are structured according to VESA HDMI 2.1x
+r2 spec, section 10.10.2.2.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c      | 14 +++++++-------
+ drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 13 ++++++-------
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c |  3 ++-
+ drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h    |  1 +
+ 4 files changed, 16 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 551fff68a5dc..168b853434d7 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2769,10 +2769,10 @@ void core_link_enable_stream(
+ 			allocate_mst_payload(pipe_ctx);
+ 
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-		if (pipe_ctx->stream->timing.flags.DSC &&
+-				(dc_is_dp_signal(pipe_ctx->stream->signal) ||
+-				dc_is_virtual_signal(pipe_ctx->stream->signal))) {
+-			dp_set_dsc_enable(pipe_ctx, true);
++		if (pipe_ctx->stream->timing.flags.DSC) {
++			if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
++					dc_is_virtual_signal(pipe_ctx->stream->signal))
++				dp_set_dsc_enable(pipe_ctx, true);
+ 			pipe_ctx->stream_res.tg->funcs->wait_for_state(
+ 					pipe_ctx->stream_res.tg,
+ 					CRTC_STATE_VBLANK);
+@@ -2833,9 +2833,9 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
+ 
+ 	disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-	if (pipe_ctx->stream->timing.flags.DSC &&
+-			dc_is_dp_signal(pipe_ctx->stream->signal)) {
+-		dp_set_dsc_enable(pipe_ctx, false);
++	if (pipe_ctx->stream->timing.flags.DSC) {
++		if (dc_is_dp_signal(pipe_ctx->stream->signal))
++			dp_set_dsc_enable(pipe_ctx, false);
+ 	}
+ #endif
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index 211fadefe2f5..46257f0fcbe7 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -396,7 +396,7 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
+ 
+ /* This has to be done after DSC was enabled on RX first, i.e. after dp_enable_dsc_on_rx() had been called
+  */
+-static void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
++void set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ {
+ 	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
+ 	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
+@@ -435,7 +435,7 @@ static void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ 
+ 		dsc_optc_config_log(dsc, &dsc_optc_cfg);
+ 		/* Enable DSC in encoder */
+-		if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) && pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config)
++		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
+ 			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,
+ 									optc_dsc_mode,
+ 									dsc_optc_cfg.bytes_per_pixel,
+@@ -454,11 +454,10 @@ static void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ 				OPTC_DSC_DISABLED, 0, 0);
+ 
+ 		/* disable DSC in stream encoder */
+-		if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
+ 			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(
+ 					pipe_ctx->stream_res.stream_enc,
+ 					OPTC_DSC_DISABLED, 0, 0, NULL);
+-		}
+ 
+ 		/* disable DSC block */
+ 		pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
+@@ -479,12 +478,12 @@ bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)
+ 
+ 	if (enable) {
+ 		if (dp_set_dsc_on_rx(pipe_ctx, true)) {
+-			dp_set_dsc_on_stream(pipe_ctx, true);
++			set_dsc_on_stream(pipe_ctx, true);
+ 			result = true;
+ 		}
+ 	} else {
+ 		dp_set_dsc_on_rx(pipe_ctx, false);
+-		dp_set_dsc_on_stream(pipe_ctx, false);
++		set_dsc_on_stream(pipe_ctx, false);
+ 		result = true;
+ 	}
+ out:
+@@ -500,7 +499,7 @@ bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx)
+ 	if (!dsc)
+ 		return false;
+ 
+-	dp_set_dsc_on_stream(pipe_ctx, true);
++	set_dsc_on_stream(pipe_ctx, true);
+ 	return true;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 7c08f81000c5..db57c2a99a15 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1758,8 +1758,9 @@ static void dcn20_reset_back_end_for_pipe(
+ 		}
+ 	}
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-	else if (pipe_ctx->stream_res.dsc)
++	else if (pipe_ctx->stream_res.dsc) {
+ 		dp_set_dsc_enable(pipe_ctx, false);
++	}
+ #endif
+ 
+ 	/* by upper caller loop, parent pipe: pipe0, will be reset last.
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+index 2d95eff94239..c5293f9508fa 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+@@ -66,6 +66,7 @@ void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
+ void dp_set_fec_ready(struct dc_link *link, bool ready);
+ void dp_set_fec_enable(struct dc_link *link, bool enable);
+ bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
++void set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
+ bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
+ #endif
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3034-drm-amd-display-add-monitor-patch-to-add-T7-delay.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3034-drm-amd-display-add-monitor-patch-to-add-T7-delay.patch
new file mode 100644
index 00000000..eaa7e6a9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3034-drm-amd-display-add-monitor-patch-to-add-T7-delay.patch
@@ -0,0 +1,58 @@
+From a0048d5fbb6f5e6a1fc395b60ced875242518e5f Mon Sep 17 00:00:00 2001
+From: Anthony Koo <anthony.koo@amd.com>
+Date: Wed, 12 Jun 2019 16:30:15 -0400
+Subject: [PATCH 3034/4256] drm/amd/display: add monitor patch to add T7 delay
+
+[Why]
+Specifically to one panel,
+TCON is able to accept active video signal quickly, but
+the Source Driver requires 2-3 frames of extra time.
+
+It is a Panel issue since TCON needs to take care of
+all Sink requirements including Source Driver. But in
+this case it does not.
+
+Customer is asking to add fixed T7 delay as panel
+workaround.
+
+[How]
+Add monitor specific patch to add T7 delay
+
+Signed-off-by: Anthony Koo <anthony.koo@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 4 ++++
+ drivers/gpu/drm/amd/display/dc/dc_types.h          | 1 +
+ 2 files changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index 46257f0fcbe7..878f47b59d5a 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -162,6 +162,10 @@ bool edp_receiver_ready_T7(struct dc_link *link)
+ 			break;
+ 		udelay(25); //MAx T7 is 50ms
+ 	} while (++tries < 300);
++
++	if (link->local_sink->edid_caps.panel_patch.extra_t7_ms > 0)
++		udelay(link->local_sink->edid_caps.panel_patch.extra_t7_ms * 1000);
++
+ 	return result;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
+index 2e1d1a8652d8..4279b355c1f4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
+@@ -211,6 +211,7 @@ struct dc_panel_patch {
+ 	unsigned int dppowerup_delay;
+ 	unsigned int extra_t12_ms;
+ 	unsigned int extra_delay_backlight_off;
++	unsigned int extra_t7_ms;
+ };
+ 
+ struct dc_edid_caps {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3035-drm-amd-display-Poll-for-GPUVM-context-ready.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3035-drm-amd-display-Poll-for-GPUVM-context-ready.patch
new file mode 100644
index 00000000..e10e7cd0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3035-drm-amd-display-Poll-for-GPUVM-context-ready.patch
@@ -0,0 +1,76 @@
+From a64abd033c46e7d8f75bf617563703d50005dd55 Mon Sep 17 00:00:00 2001
+From: Julian Parkin <julian.parkin@amd.com>
+Date: Thu, 13 Jun 2019 12:49:37 -0400
+Subject: [PATCH 3035/4256] drm/amd/display: Poll for GPUVM context ready
+
+[Why]
+Hardware docs state that we must wait until the GPUVM context is ready
+after programming it.
+
+[How]
+Poll until the valid bit of PAGE_TABLE_BASE_ADDR_LO32 is set to 1 after
+programming it.
+
+Signed-off-by: Julian Parkin <julian.parkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c | 35 +++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c
+index 27679ef6ebe8..84512e646f87 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c
+@@ -36,6 +36,38 @@
+ #define FN(reg_name, field_name) \
+ 	vmid->shifts->field_name, vmid->masks->field_name
+ 
++static void dcn20_wait_for_vmid_ready(struct dcn20_vmid *vmid)
++{
++	/* According the hardware spec, we need to poll for the lowest
++	 * bit of PAGE_TABLE_BASE_ADDR_LO32 = 1 any time a GPUVM
++	 * context is updated. We can't use REG_WAIT here since we
++	 * don't have a seperate field to wait on.
++	 *
++	 * TODO: Confirm timeout / poll interval with hardware team
++	 */
++
++	int max_times = 10000;
++	int delay_us  = 5;
++	int i;
++
++	for (i = 0; i < max_times; ++i) {
++		uint32_t entry_lo32;
++
++		REG_GET(PAGE_TABLE_BASE_ADDR_LO32,
++			VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32,
++			&entry_lo32);
++
++		if (entry_lo32 & 0x1)
++			return;
++
++		udelay(delay_us);
++	}
++
++	/* VM setup timed out */
++	DC_LOG_WARNING("Timeout while waiting for GPUVM context update\n");
++	ASSERT(0);
++}
++
+ void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct dcn_vmid_page_table_config *config)
+ {
+ 	REG_SET(PAGE_TABLE_START_ADDR_HI32, 0,
+@@ -54,6 +86,9 @@ void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct dcn_vmid_page_table_
+ 
+ 	REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0,
+ 			VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, (config->page_table_base_addr >> 32) & 0xFFFFFFFF);
++	/* Note: per hardware spec PAGE_TABLE_BASE_ADDR_LO32 must be programmed last in sequence */
+ 	REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0,
+ 			VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, config->page_table_base_addr & 0xFFFFFFFF);
++
++	dcn20_wait_for_vmid_ready(vmid);
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3036-drm-amd-display-dc-fix-TRANSMITTER_UNIPHY_G-offset.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3036-drm-amd-display-dc-fix-TRANSMITTER_UNIPHY_G-offset.patch
new file mode 100644
index 00000000..3cd43abf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3036-drm-amd-display-dc-fix-TRANSMITTER_UNIPHY_G-offset.patch
@@ -0,0 +1,45 @@
+From 0846da24b527a02c016678f8199ea56f3a4c78fb Mon Sep 17 00:00:00 2001
+From: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
+Date: Mon, 19 Aug 2019 16:29:45 +0530
+Subject: [PATCH 3036/4256] drm/amd/display/dc: fix TRANSMITTER_UNIPHY_G offset
+
+[why?]
+The enum value for TRANSMITTER_UNIPHY_G is 9 but in dce80_resoruce.c
+UNIPHY_G registers are initialized at index 6. This is because in
+dce11 there are other TRANSMITTER initialized at 6, 7 and 8.
+
+[how?]
+Initialize dummy elemets for 6, 7 and 8 so that at index 9 UNIPHY_G
+registers are available.
+
+Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+index 1dccd59c59c5..69e9325e0f74 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -226,7 +226,7 @@ static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
+ };
+ 
+ #define link_regs(id)\
+-[id] = {\
++{\
+ 	LE_DCE80_REG_LIST(id)\
+ }
+ 
+@@ -237,6 +237,9 @@ static const struct dce110_link_enc_registers link_enc_regs[] = {
+ 	link_regs(3),
+ 	link_regs(4),
+ 	link_regs(5),
++	link_regs(0),
++	link_regs(0),
++	link_regs(0),
+ 	link_regs(6),
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3037-drm-amd-display-add-functionality-to-grab-DPRX-CRC-e.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3037-drm-amd-display-add-functionality-to-grab-DPRX-CRC-e.patch
new file mode 100644
index 00000000..8e082ec6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3037-drm-amd-display-add-functionality-to-grab-DPRX-CRC-e.patch
@@ -0,0 +1,340 @@
+From aac416b2b4e47acea0ce5526a876e09436d95273 Mon Sep 17 00:00:00 2001
+From: Dingchen Zhang <dingchen.zhang@amd.com>
+Date: Wed, 15 May 2019 17:15:05 -0400
+Subject: [PATCH 3037/4256] drm/amd/display: add functionality to grab DPRX CRC
+ entries.
+
+[Why]
+We need to compare DPRX CRCs with framebuffer CRCs for digital bypass mode.
+
+[How]
+Hook into DRM to grab DP receiver CRCs through drm_dp_start_crc.
+
+Change-Id: Ib3ab9508baba6a7f752d2a2ac63b35bbb39ac701
+Signed-off-by: Dingchen Zhang <dingchen.zhang@amd.com>
+Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 ++--
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 16 +---
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 92 ++++++++++++++-----
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 56 +++++++++++
+ 4 files changed, 139 insertions(+), 44 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 32bad607712b..2dbf11563476 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -3747,7 +3747,7 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
+ 	state->abm_level = cur->abm_level;
+         state->vrr_supported = cur->vrr_supported;
+         state->freesync_config = cur->freesync_config;
+-	state->crc_enabled = cur->crc_enabled;
++	state->crc_src= cur->crc_src;
+ 	state->cm_has_degamma = cur->cm_has_degamma;
+ 	state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
+ 
+@@ -5953,6 +5953,7 @@ static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev,
+ 	struct drm_crtc *crtc;
+ 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
+ 	int i;
++	enum amdgpu_dm_pipe_crc_source source;
+ 
+ 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
+ 				      new_crtc_state, i) {
+@@ -5978,9 +5979,13 @@ static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev,
+ 
+ #ifdef CONFIG_DEBUG_FS
+ 		/* The stream has changed so CRC capture needs to re-enabled. */
+-		if (dm_new_crtc_state->crc_enabled) {
+-			dm_new_crtc_state->crc_enabled = false;
+-			amdgpu_dm_crtc_set_crc_source(crtc, "auto");
++                source = dm_new_crtc_state->crc_src;
++                if (amdgpu_dm_is_valid_crc_source(source)) {
++                        dm_new_crtc_state->crc_src = AMDGPU_DM_PIPE_CRC_SOURCE_NONE;
++                        if (source == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC)
++                                amdgpu_dm_crtc_set_crc_source(crtc, "crtc");
++                        else if (source == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX)
++                                amdgpu_dm_crtc_set_crc_source(crtc, "dprx");
+ 		}
+ #endif
+ 	}
+@@ -6036,7 +6041,7 @@ static int amdgpu_dm_atomic_commit(struct drm_device *dev,
+                          * Drop the extra vblank reference added by CRC
+                          * capture if applicable.
+                          */
+-                        if (dm_new_crtc_state->crc_enabled)
++			if (amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src))
+                                 drm_crtc_vblank_put(crtc);
+ 
+                         /*
+@@ -6044,8 +6049,7 @@ static int amdgpu_dm_atomic_commit(struct drm_device *dev,
+                          * still a stream for the CRTC.
+                          */
+                         if (!dm_new_crtc_state->stream)
+-                                dm_new_crtc_state->crc_enabled = false;
+-
++				dm_new_crtc_state->crc_src = AMDGPU_DM_PIPE_CRC_SOURCE_NONE;
+ 
+ 			manage_dm_interrupts(adev, acrtc, false);
+ 		}
+@@ -6741,6 +6745,7 @@ static bool should_reset_plane(struct drm_atomic_state *state,
+ 	struct drm_plane_state *old_other_state, *new_other_state;
+ 	struct drm_crtc_state *new_crtc_state;
+ 	int i;
++	enum amdgpu_dm_pipe_crc_source source;
+ 
+ 	/*
+ 	 * TODO: Remove this hack once the checks below are sufficient
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+index 407c0fe0c20b..d323746f1bdd 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+@@ -47,6 +47,7 @@
+ 
+ #include "irq_types.h"
+ #include "signal_types.h"
++#include "amdgpu_dm_crc.h"
+ 
+ /* Forward declarations */
+ struct amdgpu_device;
+@@ -307,7 +308,7 @@ struct dm_crtc_state {
+ 	bool interrupts_enabled;
+ 
+ 	int crc_skip_count;
+-	bool crc_enabled;
++	enum amdgpu_dm_pipe_crc_source crc_src;
+ 
+ 	bool freesync_timing_changed;
+ 	bool freesync_vrr_info_changed;
+@@ -376,19 +377,6 @@ void dm_restore_drm_connector_state(struct drm_device *dev,
+ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
+ 					struct edid *edid);
+ 
+-/* amdgpu_dm_crc.c */
+-#ifdef CONFIG_DEBUG_FS
+-int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
+-int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
+-				     const char *src_name,
+-				     size_t *values_cnt);
+-void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
+-#else
+-#define amdgpu_dm_crtc_set_crc_source NULL
+-#define amdgpu_dm_crtc_verify_crc_source NULL
+-#define amdgpu_dm_crtc_handle_crc_irq(x)
+-#endif
+-
+ #define MAX_COLOR_LUT_ENTRIES 4096
+ /* Legacy gamm LUT users such as X doesn't like large LUT sizes */
+ #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+index 993a83ecde64..54dc86e4d6bf 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+@@ -29,19 +29,14 @@
+ #include "amdgpu_dm.h"
+ #include "dc.h"
+ 
+-enum amdgpu_dm_pipe_crc_source {
+-	AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
+-	AMDGPU_DM_PIPE_CRC_SOURCE_AUTO,
+-	AMDGPU_DM_PIPE_CRC_SOURCE_MAX,
+-	AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1,
+-};
+-
+ static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source)
+ {
+ 	if (!source || !strcmp(source, "none"))
+ 		return AMDGPU_DM_PIPE_CRC_SOURCE_NONE;
+-	if (!strcmp(source, "auto"))
+-		return AMDGPU_DM_PIPE_CRC_SOURCE_AUTO;
++	if (!strcmp(source, "auto") || !strcmp(source, "crtc"))
++		return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC;
++	if (!strcmp(source, "dprx"))
++		return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX;
+ 
+ 	return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID;
+ }
+@@ -67,7 +62,10 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+ 	struct amdgpu_device *adev = crtc->dev->dev_private;
+ 	struct dm_crtc_state *crtc_state = to_dm_crtc_state(crtc->state);
+ 	struct dc_stream_state *stream_state = crtc_state->stream;
+-	bool enable;
++	struct amdgpu_dm_connector *aconn;
++	struct drm_dp_aux *aux = NULL;
++	bool enable = false;
++	bool enabled = false;
+ 
+ 	enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
+ 
+@@ -82,11 +80,44 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+ 		return -EINVAL;
+ 	}
+ 
+-	enable = (source == AMDGPU_DM_PIPE_CRC_SOURCE_AUTO);
+-
+-	if (!dc_stream_configure_crc(stream_state->ctx->dc, stream_state,
+-				     enable, enable))
+-		return -EINVAL;
++	enable = amdgpu_dm_is_valid_crc_source(source);
++
++	mutex_lock(&adev->dm.dc_lock);
++
++        /*
++         * USER REQ SRC | CURRENT SRC | BEHAVIOR
++         * -----------------------------
++         * None         | None        | Do nothing
++         * None         | CRTC        | Disable CRTC CRC
++         * None         | DPRX        | Disable DPRX CRC, need 'aux'
++         * CRTC         | XXXX        | Enable CRTC CRC, configure DC strm
++         * DPRX         | XXXX        | Enable DPRX CRC, need 'aux'
++         */
++        if (source == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX ||
++                (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE &&
++                 crtc_state->crc_src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX)) {
++                aconn = stream_state->link->priv;
++
++                if (!aconn) {
++                        DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index);
++                        mutex_unlock(&adev->dm.dc_lock);
++                        return -EINVAL;
++                }
++
++                aux = &aconn->dm_dp_aux.aux;
++
++                if (!aux) {
++                        DRM_DEBUG_DRIVER("No dp aux for amd connector\n");
++                        mutex_unlock(&adev->dm.dc_lock);
++                        return -EINVAL;
++                }
++        } else if (source == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) {
++                if (!dc_stream_configure_crc(stream_state->ctx->dc, stream_state,
++                                             enable, enable)) {
++                        mutex_unlock(&adev->dm.dc_lock);
++                        return -EINVAL;
++                }
++        }
+ 
+ 	/* When enabling CRC, we should also disable dithering. */
+ 	dc_stream_set_dither_option(stream_state,
+@@ -97,12 +128,26 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+ 	 * Reading the CRC requires the vblank interrupt handler to be
+ 	 * enabled. Keep a reference until CRC capture stops.
+ 	 */
+-	if (!crtc_state->crc_enabled && enable)
++	enabled = amdgpu_dm_is_valid_crc_source(crtc_state->crc_src);
++	if (!enabled && enable) {
+ 		drm_crtc_vblank_get(crtc);
+-	else if (crtc_state->crc_enabled && !enable)
++		if (source == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) {
++			if (drm_dp_start_crc(aux, crtc)) {
++				DRM_DEBUG_DRIVER("dp start crc failed\n");
++				return -EINVAL;
++			}
++		}
++	} else if (enabled && !enable) {
+ 		drm_crtc_vblank_put(crtc);
++		if (crtc_state->crc_src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) {
++			if (drm_dp_stop_crc(aux)) {
++				DRM_DEBUG_DRIVER("dp stop crc failed\n");
++				return -EINVAL;
++			}
++		}
++	}
+ 
+-	crtc_state->crc_enabled = enable;
++	crtc_state->crc_src = source;
+ 
+ 	/* Reset crc_skipped on dm state */
+ 	crtc_state->crc_skip_count = 0;
+@@ -129,7 +174,7 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc)
+ 	stream_state = crtc_state->stream;
+ 
+ 	/* Early return if CRC capture is not enabled. */
+-	if (!crtc_state->crc_enabled)
++	if (!amdgpu_dm_is_valid_crc_source(crtc_state->crc_src))
+ 		return;
+ 
+ 	/*
+@@ -143,10 +188,11 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc)
+ 		return;
+ 	}
+ 
+-	if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state,
+-			       &crcs[0], &crcs[1], &crcs[2]))
+-		return;
+-
++        if (crtc_state->crc_src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) {
++                if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state,
++                                       &crcs[0], &crcs[1], &crcs[2]))
++                        return;
+ 	drm_crtc_add_crc_entry(crtc, true,
+ 			       drm_crtc_accurate_vblank_count(crtc), crcs);
++	}
+ }
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
+new file mode 100644
+index 000000000000..3793dc872436
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
+@@ -0,0 +1,56 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
++#define AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
++
++enum amdgpu_dm_pipe_crc_source {
++	AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
++	AMDGPU_DM_PIPE_CRC_SOURCE_CRTC,
++	AMDGPU_DM_PIPE_CRC_SOURCE_DPRX,
++	AMDGPU_DM_PIPE_CRC_SOURCE_MAX,
++	AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1,
++};
++
++static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source)
++{
++	return (source == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) ||
++		   (source == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX);
++}
++
++/* amdgpu_dm_crc.c */
++#ifdef CONFIG_DEBUG_FS
++int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
++int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
++				     const char *src_name,
++				     size_t *values_cnt);
++void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
++#else
++#define amdgpu_dm_crtc_set_crc_source NULL
++#define amdgpu_dm_crtc_verify_crc_source NULL
++#define amdgpu_dm_crtc_handle_crc_irq(x)
++#endif
++
++#endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3038-drm-amd-display-add-functionality-to-get-pipe-CRC-so.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3038-drm-amd-display-add-functionality-to-get-pipe-CRC-so.patch
new file mode 100644
index 00000000..3453e724
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3038-drm-amd-display-add-functionality-to-get-pipe-CRC-so.patch
@@ -0,0 +1,123 @@
+From 6d3236dab95ff312959904f7876c10df3b2cf218 Mon Sep 17 00:00:00 2001
+From: Dingchen Zhang <dingchen.zhang@amd.com>
+Date: Wed, 29 May 2019 18:52:52 -0400
+Subject: [PATCH 3038/4256] drm/amd/display: add functionality to get pipe CRC
+ source.
+
+[Why]
+We need to check the pipe crc source through debugfs for bypass mode test.
+
+[How]
+add implementation of amdgpu_dm_crtc_get_crc_sources and hook into drm_crtc
+callback get_crc_sources.
+
+Change-Id: Ib2b74295fda878eca3a304d4691d2228e43a6afe
+Signed-off-by: Dingchen Zhang <dingchen.zhang@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  1 +
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 14 +++++++++++
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h |  3 +++
+ include/drm/drm_crtc.h                        | 23 +++++++++++++++++++
+ 4 files changed, 41 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 2dbf11563476..844e9442449f 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -3817,6 +3817,7 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
+ 	.atomic_destroy_state = dm_crtc_destroy_state,
+ 	.set_crc_source = amdgpu_dm_crtc_set_crc_source,
+ 	.verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
++	.get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
+ 	.enable_vblank = dm_enable_vblank,
+ 	.disable_vblank = dm_disable_vblank,
+ };
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+index 54dc86e4d6bf..609f1fdc10b3 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+@@ -29,6 +29,13 @@
+ #include "amdgpu_dm.h"
+ #include "dc.h"
+ 
++static const char *const pipe_crc_sources[] = {
++	"none",
++	"crtc",
++	"dprx",
++	"auto",
++};
++
+ static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source)
+ {
+ 	if (!source || !strcmp(source, "none"))
+@@ -41,6 +48,13 @@ static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source)
+ 	return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID;
+ }
+ 
++const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
++                                                  size_t *count)
++{
++        *count = ARRAY_SIZE(pipe_crc_sources);
++        return pipe_crc_sources;
++}
++
+ int
+ amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
+ 				 size_t *values_cnt)
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
+index 3793dc872436..b63a9011f511 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
+@@ -46,10 +46,13 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
+ int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
+ 				     const char *src_name,
+ 				     size_t *values_cnt);
++const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
++						  size_t *count);
+ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
+ #else
+ #define amdgpu_dm_crtc_set_crc_source NULL
+ #define amdgpu_dm_crtc_verify_crc_source NULL
++#define amdgpu_dm_crtc_get_crc_sources NULL
+ #define amdgpu_dm_crtc_handle_crc_irq(x)
+ #endif
+ 
+diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
+index a92f548502c8..2cf8ca1ae594 100644
+--- a/include/drm/drm_crtc.h
++++ b/include/drm/drm_crtc.h
+@@ -772,6 +772,29 @@ struct drm_crtc_funcs {
+         int (*verify_crc_source)(struct drm_crtc *crtc, const char *source,
+                                  size_t *values_cnt);
+ 
++	/**
++         * @get_crc_sources:
++         *
++         * Driver callback for getting a list of all the available sources for
++         * CRC generation. This callback depends upon verify_crc_source, So
++         * verify_crc_source callback should be implemented before implementing
++         * this. Driver can pass full list of available crc sources, this
++         * callback does the verification on each crc-source before passing it
++         * to userspace.
++         *
++         * This callback is optional if the driver does not support exporting of
++         * possible CRC sources list.
++         *
++         * RETURNS:
++         *
++         * a constant character pointer to the list of all the available CRC
++         * sources. On failure driver should return NULL. count should be
++         * updated with number of sources in list. if zero we don't process any
++         * source from the list.
++         */
++        const char *const *(*get_crc_sources)(struct drm_crtc *crtc,
++                                              size_t *count);
++
+ 	/**
+ 	 * @atomic_print_state:
+ 	 *
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3039-drm-amd-display-Wait-for-backlight-programming-compl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3039-drm-amd-display-Wait-for-backlight-programming-compl.patch
new file mode 100644
index 00000000..af5e9ef7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3039-drm-amd-display-Wait-for-backlight-programming-compl.patch
@@ -0,0 +1,39 @@
+From 6ec47858f376996e075c44a3f8295366840bfb78 Mon Sep 17 00:00:00 2001
+From: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
+Date: Fri, 14 Jun 2019 15:04:00 -0400
+Subject: [PATCH 3039/4256] drm/amd/display: Wait for backlight programming
+ completion in set backlight level
+
+[WHY]
+Currently we don't wait for blacklight programming completion in DMCU
+when setting backlight level. Some sequences such as PSR static screen
+event trigger reprogramming requires it to be complete.
+
+[How]
+Add generic wait for dmcu command completion in set backlight level.
+
+Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+index 3d87a8800300..adde7a5760bc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+@@ -237,6 +237,10 @@ static void dmcu_set_backlight_level(
+ 	s2 |= (backlight_8_bit << ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
+ 
+ 	REG_WRITE(BIOS_SCRATCH_2, s2);
++
++	/* waitDMCUReadyForCmd */
++	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
++			0, 1, 80000);
+ }
+ 
+ static void dce_abm_init(struct abm *abm)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3040-drm-amd-display-3.2.39.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3040-drm-amd-display-3.2.39.patch
new file mode 100644
index 00000000..8016d116
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3040-drm-amd-display-3.2.39.patch
@@ -0,0 +1,27 @@
+From 4dbf4e39c6e0df4ff3f51586a7ac4d2e3f945a1a Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Mon, 17 Jun 2019 10:58:57 -0400
+Subject: [PATCH 3040/4256] drm/amd/display: 3.2.39
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index a8ecd93a1063..84f602457a9e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -42,7 +42,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.38"
++#define DC_VER "3.2.39"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3041-drm-amd-display-Expose-enc2_set_dynamic_metadata.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3041-drm-amd-display-Expose-enc2_set_dynamic_metadata.patch
new file mode 100644
index 00000000..15115c51
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3041-drm-amd-display-Expose-enc2_set_dynamic_metadata.patch
@@ -0,0 +1,47 @@
+From f208999fd72d634b9929fd35df219c87aaae2d51 Mon Sep 17 00:00:00 2001
+From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Date: Wed, 29 May 2019 18:52:17 -0400
+Subject: [PATCH 3041/4256] drm/amd/display: Expose enc2_set_dynamic_metadata
+
+[Why]
+Need to implement register programming for HDR dynamic
+metadata transmission and tests.
+
+Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h | 5 +++++
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+index 791aa745efd2..403f1f865a06 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+@@ -371,7 +371,7 @@ static void enc2_read_state(struct stream_encoder *enc, struct enc_state *s)
+  *
+  *   Ensure the OTG master update lock is set when changing DME configuration.
+  */
+-static void enc2_set_dynamic_metadata(struct stream_encoder *enc,
++void enc2_set_dynamic_metadata(struct stream_encoder *enc,
+ 		bool enable_dme,
+ 		uint32_t hubp_requestor_id,
+ 		enum dynamic_metadata_mode dmdata_mode)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
+index 6d40e8c9b78f..3f94a9f13c4a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
+@@ -104,4 +104,9 @@ void enc2_stream_encoder_dp_unblank(
+ 	struct stream_encoder *enc,
+ 	const struct encoder_unblank_param *param);
+ 
++void enc2_set_dynamic_metadata(struct stream_encoder *enc,
++		bool enable_dme,
++		uint32_t hubp_requestor_id,
++		enum dynamic_metadata_mode dmdata_mode);
++
+ #endif /* __DC_STREAM_ENCODER_DCN20_H__ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3042-drm-amd-display-Check-for-valid-stream_encode.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3042-drm-amd-display-Check-for-valid-stream_encode.patch
new file mode 100644
index 00000000..4f3a736b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3042-drm-amd-display-Check-for-valid-stream_encode.patch
@@ -0,0 +1,31 @@
+From 564d26a797aa20d2c1eba8502adcdb9de7ca9c0e Mon Sep 17 00:00:00 2001
+From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Date: Wed, 29 May 2019 18:52:17 -0400
+Subject: [PATCH 3042/4256] drm/amd/display: Check for valid stream_encode
+
+Before accessing it's vtable, check that stream_encoder is non-null.
+
+Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+index 1bc19d42fc9f..35d697dd5808 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+@@ -609,7 +609,8 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc,
+ 
+ 	pipe_ctx->stream->dmdata_address = attr->address;
+ 
+-	if (pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata != NULL) {
++	if (pipe_ctx->stream_res.stream_enc &&
++			pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata != NULL) {
+ 		if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
+ 			/* if using dynamic meta, don't set up generic infopackets */
+ 			pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3043-drm-amd-display-Fix-some-HUBP-programming-issues.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3043-drm-amd-display-Fix-some-HUBP-programming-issues.patch
new file mode 100644
index 00000000..10ad6b4a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3043-drm-amd-display-Fix-some-HUBP-programming-issues.patch
@@ -0,0 +1,823 @@
+From f3bf57204740b59d66274fcf5a8c41aa7650d86a Mon Sep 17 00:00:00 2001
+From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Date: Wed, 12 Jun 2019 12:40:42 -0400
+Subject: [PATCH 3043/4256] drm/amd/display: Fix some HUBP programming issues
+
+[Why]
+A hubp pointer was being passed to DCN1 functions, which
+expect the enclosing structure (for the purpose of container_of macros)
+to be dcn10_hubp, but the actual type was dcn20_hubp.
+
+[How]
+Copy existing DCN1 functions and alter them slightly for use with
+dcn20_hubp.
+
+Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 682 +++++++++++++++++-
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h |  37 +
+ 2 files changed, 705 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+index d3f7dd374d50..02e8c0c6a233 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+@@ -156,7 +156,85 @@ void hubp2_program_deadline(
+ {
+ 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+ 
+-	hubp1_program_deadline(hubp, dlg_attr, ttu_attr);
++	/* DLG - Per hubp */
++	REG_SET_2(BLANK_OFFSET_0, 0,
++		REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,
++		DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);
++
++	REG_SET(BLANK_OFFSET_1, 0,
++		MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
++
++	REG_SET(DST_DIMENSIONS, 0,
++		REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);
++
++	REG_SET_2(DST_AFTER_SCALER, 0,
++		REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
++		DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
++
++	REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
++		REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
++
++	/* DLG - Per luma/chroma */
++	REG_SET(VBLANK_PARAMETERS_1, 0,
++		REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
++
++	if (REG(NOM_PARAMETERS_0))
++		REG_SET(NOM_PARAMETERS_0, 0,
++			DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
++
++	if (REG(NOM_PARAMETERS_1))
++		REG_SET(NOM_PARAMETERS_1, 0,
++			REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
++
++	REG_SET(NOM_PARAMETERS_4, 0,
++		DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
++
++	REG_SET(NOM_PARAMETERS_5, 0,
++		REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
++
++	REG_SET_2(PER_LINE_DELIVERY, 0,
++		REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
++		REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
++
++	REG_SET(VBLANK_PARAMETERS_2, 0,
++		REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
++
++	if (REG(NOM_PARAMETERS_2))
++		REG_SET(NOM_PARAMETERS_2, 0,
++			DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
++
++	if (REG(NOM_PARAMETERS_3))
++		REG_SET(NOM_PARAMETERS_3, 0,
++			REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
++
++	REG_SET(NOM_PARAMETERS_6, 0,
++		DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
++
++	REG_SET(NOM_PARAMETERS_7, 0,
++		REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);
++
++	/* TTU - per hubp */
++	REG_SET_2(DCN_TTU_QOS_WM, 0,
++		QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
++		QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
++
++	/* TTU - per luma/chroma */
++	/* Assumed surf0 is luma and 1 is chroma */
++
++	REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
++		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
++		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
++		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
++
++	REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
++		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
++		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
++		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
++
++	REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
++		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
++		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
++		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
+ 
+ 	REG_SET(FLIP_PARAMETERS_1, 0,
+ 		REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l);
+@@ -184,6 +262,39 @@ void hubp2_vready_at_or_After_vsync(struct hubp *hubp,
+ 	REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value);
+ }
+ 
++void hubp2_program_requestor(
++		struct hubp *hubp,
++		struct _vcs_dpi_display_rq_regs_st *rq_regs)
++{
++	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
++
++	REG_UPDATE(HUBPRET_CONTROL,
++			DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
++	REG_SET_4(DCN_EXPANSION_MODE, 0,
++			DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
++			PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
++			MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
++			CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
++	REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
++		CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
++		MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
++		META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
++		MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
++		DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
++		MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
++		SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
++		PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
++	REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0,
++		CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
++		MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
++		META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
++		MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
++		DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
++		MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
++		SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
++		PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
++}
++
+ static void hubp2_setup(
+ 		struct hubp *hubp,
+ 		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
+@@ -196,7 +307,7 @@ static void hubp2_setup(
+ 	 */
+ 
+ 	hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
+-	hubp1_program_requestor(hubp, rq_regs);
++	hubp2_program_requestor(hubp, rq_regs);
+ 	hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
+ 
+ }
+@@ -283,6 +394,196 @@ static void hubp2_program_tiling(
+ 			PIPE_ALIGNED, 0);
+ }
+ 
++void hubp2_program_size(
++	struct hubp *hubp,
++	enum surface_pixel_format format,
++	const union plane_size *plane_size,
++	struct dc_plane_dcc_param *dcc)
++{
++	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
++	uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c;
++
++	/* Program data and meta surface pitch (calculation from addrlib)
++	 * 444 or 420 luma
++	 */
++	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) {
++		ASSERT(plane_size->video.chroma_pitch != 0);
++		/* Chroma pitch zero can cause system hang! */
++
++		pitch = plane_size->video.luma_pitch - 1;
++		meta_pitch = dcc->video.meta_pitch_l - 1;
++		pitch_c = plane_size->video.chroma_pitch - 1;
++		meta_pitch_c = dcc->video.meta_pitch_c - 1;
++	} else {
++		pitch = plane_size->grph.surface_pitch - 1;
++		meta_pitch = dcc->grph.meta_pitch - 1;
++		pitch_c = 0;
++		meta_pitch_c = 0;
++	}
++
++	if (!dcc->enable) {
++		meta_pitch = 0;
++		meta_pitch_c = 0;
++	}
++
++	REG_UPDATE_2(DCSURF_SURFACE_PITCH,
++			PITCH, pitch, META_PITCH, meta_pitch);
++
++	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
++		REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
++			PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
++}
++
++void hubp2_program_rotation(
++	struct hubp *hubp,
++	enum dc_rotation_angle rotation,
++	bool horizontal_mirror)
++{
++	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
++	uint32_t mirror;
++
++
++	if (horizontal_mirror)
++		mirror = 1;
++	else
++		mirror = 0;
++
++	/* Program rotation angle and horz mirror - no mirror */
++	if (rotation == ROTATION_ANGLE_0)
++		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
++				ROTATION_ANGLE, 0,
++				H_MIRROR_EN, mirror);
++	else if (rotation == ROTATION_ANGLE_90)
++		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
++				ROTATION_ANGLE, 1,
++				H_MIRROR_EN, mirror);
++	else if (rotation == ROTATION_ANGLE_180)
++		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
++				ROTATION_ANGLE, 2,
++				H_MIRROR_EN, mirror);
++	else if (rotation == ROTATION_ANGLE_270)
++		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
++				ROTATION_ANGLE, 3,
++				H_MIRROR_EN, mirror);
++}
++
++void hubp2_dcc_control(struct hubp *hubp, bool enable,
++		bool independent_64b_blks)
++{
++	uint32_t dcc_en = enable ? 1 : 0;
++	uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
++	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
++
++	REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
++			PRIMARY_SURFACE_DCC_EN, dcc_en,
++			PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk,
++			SECONDARY_SURFACE_DCC_EN, dcc_en,
++			SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
++}
++
++void hubp2_program_pixel_format(
++	struct hubp *hubp,
++	enum surface_pixel_format format)
++{
++	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
++	uint32_t red_bar = 3;
++	uint32_t blue_bar = 2;
++
++	/* swap for ABGR format */
++	if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
++			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
++			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
++			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
++		red_bar = 2;
++		blue_bar = 3;
++	}
++
++	REG_UPDATE_2(HUBPRET_CONTROL,
++			CROSSBAR_SRC_CB_B, blue_bar,
++			CROSSBAR_SRC_CR_R, red_bar);
++
++	/* Mapping is same as ipp programming (cnvc) */
++
++	switch (format)	{
++	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
++		REG_UPDATE(DCSURF_SURFACE_CONFIG,
++				SURFACE_PIXEL_FORMAT, 1);
++		break;
++	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
++		REG_UPDATE(DCSURF_SURFACE_CONFIG,
++				SURFACE_PIXEL_FORMAT, 3);
++		break;
++	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
++	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
++		REG_UPDATE(DCSURF_SURFACE_CONFIG,
++				SURFACE_PIXEL_FORMAT, 8);
++		break;
++	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
++	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
++	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
++		REG_UPDATE(DCSURF_SURFACE_CONFIG,
++				SURFACE_PIXEL_FORMAT, 10);
++		break;
++	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
++		REG_UPDATE(DCSURF_SURFACE_CONFIG,
++				SURFACE_PIXEL_FORMAT, 22);
++		break;
++	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
++	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
++		REG_UPDATE(DCSURF_SURFACE_CONFIG,
++				SURFACE_PIXEL_FORMAT, 24);
++		break;
++
++	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
++		REG_UPDATE(DCSURF_SURFACE_CONFIG,
++				SURFACE_PIXEL_FORMAT, 65);
++		break;
++	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
++		REG_UPDATE(DCSURF_SURFACE_CONFIG,
++				SURFACE_PIXEL_FORMAT, 64);
++		break;
++	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
++		REG_UPDATE(DCSURF_SURFACE_CONFIG,
++				SURFACE_PIXEL_FORMAT, 67);
++		break;
++	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
++		REG_UPDATE(DCSURF_SURFACE_CONFIG,
++				SURFACE_PIXEL_FORMAT, 66);
++		break;
++	case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
++		REG_UPDATE(DCSURF_SURFACE_CONFIG,
++				SURFACE_PIXEL_FORMAT, 12);
++		break;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
++		REG_UPDATE(DCSURF_SURFACE_CONFIG,
++				SURFACE_PIXEL_FORMAT, 112);
++		break;
++	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
++		REG_UPDATE(DCSURF_SURFACE_CONFIG,
++				SURFACE_PIXEL_FORMAT, 113);
++		break;
++	case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
++		REG_UPDATE(DCSURF_SURFACE_CONFIG,
++				SURFACE_PIXEL_FORMAT, 114);
++		break;
++	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
++		REG_UPDATE(DCSURF_SURFACE_CONFIG,
++				SURFACE_PIXEL_FORMAT, 118);
++		break;
++	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
++		REG_UPDATE(DCSURF_SURFACE_CONFIG,
++				SURFACE_PIXEL_FORMAT, 119);
++		break;
++#endif
++	default:
++		BREAK_TO_DEBUGGER();
++		break;
++	}
++
++	/* don't see the need of program the xbar in DCN 1.0 */
++}
++
+ void hubp2_program_surface_config(
+ 	struct hubp *hubp,
+ 	enum surface_pixel_format format,
+@@ -295,11 +596,11 @@ void hubp2_program_surface_config(
+ {
+ 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+ 
+-	hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);
++	hubp2_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);
+ 	hubp2_program_tiling(hubp2, tiling_info, format);
+-	hubp1_program_size(hubp, format, plane_size, dcc);
+-	hubp1_program_rotation(hubp, rotation, horizontal_mirror);
+-	hubp1_program_pixel_format(hubp, format);
++	hubp2_program_size(hubp, format, plane_size, dcc);
++	hubp2_program_rotation(hubp, rotation, horizontal_mirror);
++	hubp2_program_pixel_format(hubp, format);
+ }
+ 
+ enum cursor_lines_per_chunk hubp2_get_lines_per_chunk(
+@@ -652,28 +953,381 @@ void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable)
+ 	REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0);
+ }
+ 
++bool hubp2_is_flip_pending(struct hubp *hubp)
++{
++	uint32_t flip_pending = 0;
++	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
++	struct dc_plane_address earliest_inuse_address;
++
++	REG_GET(DCSURF_FLIP_CONTROL,
++			SURFACE_FLIP_PENDING, &flip_pending);
++
++	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
++			SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
++
++	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
++			SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
++
++	if (flip_pending)
++		return true;
++
++	if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
++		return true;
++
++	return false;
++}
++
++void hubp2_set_blank(struct hubp *hubp, bool blank)
++{
++	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
++	uint32_t blank_en = blank ? 1 : 0;
++
++	REG_UPDATE_2(DCHUBP_CNTL,
++			HUBP_BLANK_EN, blank_en,
++			HUBP_TTU_DISABLE, blank_en);
++
++	if (blank) {
++		uint32_t reg_val = REG_READ(DCHUBP_CNTL);
++
++		if (reg_val) {
++			/* init sequence workaround: in case HUBP is
++			 * power gated, this wait would timeout.
++			 *
++			 * we just wrote reg_val to non-0, if it stay 0
++			 * it means HUBP is gated
++			 */
++			REG_WAIT(DCHUBP_CNTL,
++					HUBP_NO_OUTSTANDING_REQ, 1,
++					1, 200);
++		}
++
++		hubp->mpcc_id = 0xf;
++		hubp->opp_id = OPP_ID_INVALID;
++	}
++}
++
++void hubp2_cursor_set_position(
++		struct hubp *hubp,
++		const struct dc_cursor_position *pos,
++		const struct dc_cursor_mi_param *param)
++{
++	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
++	int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
++	int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
++	int x_hotspot = pos->x_hotspot;
++	int y_hotspot = pos->y_hotspot;
++	uint32_t dst_x_offset;
++	uint32_t cur_en = pos->enable ? 1 : 0;
++
++	/*
++	 * Guard aganst cursor_set_position() from being called with invalid
++	 * attributes
++	 *
++	 * TODO: Look at combining cursor_set_position() and
++	 * cursor_set_attributes() into cursor_update()
++	 */
++	if (hubp->curs_attr.address.quad_part == 0)
++		return;
++
++	if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
++		src_x_offset = pos->y - pos->y_hotspot - param->viewport.x;
++		y_hotspot = pos->x_hotspot;
++		x_hotspot = pos->y_hotspot;
++	}
++
++	if (param->mirror) {
++		x_hotspot = param->viewport.width - x_hotspot;
++		src_x_offset = param->viewport.x + param->viewport.width - src_x_offset;
++	}
++
++	dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
++	dst_x_offset *= param->ref_clk_khz;
++	dst_x_offset /= param->pixel_clk_khz;
++
++	ASSERT(param->h_scale_ratio.value);
++
++	if (param->h_scale_ratio.value)
++		dst_x_offset = dc_fixpt_floor(dc_fixpt_div(
++				dc_fixpt_from_int(dst_x_offset),
++				param->h_scale_ratio));
++
++	if (src_x_offset >= (int)param->viewport.width)
++		cur_en = 0;  /* not visible beyond right edge*/
++
++	if (src_x_offset + (int)hubp->curs_attr.width <= 0)
++		cur_en = 0;  /* not visible beyond left edge*/
++
++	if (src_y_offset >= (int)param->viewport.height)
++		cur_en = 0;  /* not visible beyond bottom edge*/
++
++	if (src_y_offset + (int)hubp->curs_attr.height <= 0)
++		cur_en = 0;  /* not visible beyond top edge*/
++
++	if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
++		hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
++
++	REG_UPDATE(CURSOR_CONTROL,
++			CURSOR_ENABLE, cur_en);
++
++	REG_SET_2(CURSOR_POSITION, 0,
++			CURSOR_X_POSITION, pos->x,
++			CURSOR_Y_POSITION, pos->y);
++
++	REG_SET_2(CURSOR_HOT_SPOT, 0,
++			CURSOR_HOT_SPOT_X, x_hotspot,
++			CURSOR_HOT_SPOT_Y, y_hotspot);
++
++	REG_SET(CURSOR_DST_OFFSET, 0,
++			CURSOR_DST_X_OFFSET, dst_x_offset);
++	/* TODO Handle surface pixel formats other than 4:4:4 */
++}
++
++void hubp2_clk_cntl(struct hubp *hubp, bool enable)
++{
++	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
++	uint32_t clk_enable = enable ? 1 : 0;
++
++	REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);
++}
++
++void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst)
++{
++	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
++
++	REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
++}
++
++void hubp2_clear_underflow(struct hubp *hubp)
++{
++	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
++
++	REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);
++}
++
++void hubp2_read_state_common(struct hubp *hubp)
++{
++	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
++	struct dcn_hubp_state *s = &hubp2->state;
++	struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
++	struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
++	struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
++
++	/* Requester */
++	REG_GET(HUBPRET_CONTROL,
++			DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
++	REG_GET_4(DCN_EXPANSION_MODE,
++			DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
++			PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
++			MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
++			CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
++
++	/* DLG - Per hubp */
++	REG_GET_2(BLANK_OFFSET_0,
++		REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
++		DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
++
++	REG_GET(BLANK_OFFSET_1,
++		MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
++
++	REG_GET(DST_DIMENSIONS,
++		REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
++
++	REG_GET_2(DST_AFTER_SCALER,
++		REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
++		DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
++
++	if (REG(PREFETCH_SETTINS))
++		REG_GET_2(PREFETCH_SETTINS,
++			DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
++			VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
++	else
++		REG_GET_2(PREFETCH_SETTINGS,
++			DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
++			VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
++
++	REG_GET_2(VBLANK_PARAMETERS_0,
++		DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
++		DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
++
++	REG_GET(REF_FREQ_TO_PIX_FREQ,
++		REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
++
++	/* DLG - Per luma/chroma */
++	REG_GET(VBLANK_PARAMETERS_1,
++		REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
++
++	REG_GET(VBLANK_PARAMETERS_3,
++		REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
++
++	if (REG(NOM_PARAMETERS_0))
++		REG_GET(NOM_PARAMETERS_0,
++			DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
++
++	if (REG(NOM_PARAMETERS_1))
++		REG_GET(NOM_PARAMETERS_1,
++			REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
++
++	REG_GET(NOM_PARAMETERS_4,
++		DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
++
++	REG_GET(NOM_PARAMETERS_5,
++		REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
++
++	REG_GET_2(PER_LINE_DELIVERY_PRE,
++		REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
++		REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
++
++	REG_GET_2(PER_LINE_DELIVERY,
++		REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
++		REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
++
++	if (REG(PREFETCH_SETTINS_C))
++		REG_GET(PREFETCH_SETTINS_C,
++			VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
++	else
++		REG_GET(PREFETCH_SETTINGS_C,
++			VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
++
++	REG_GET(VBLANK_PARAMETERS_2,
++		REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
++
++	REG_GET(VBLANK_PARAMETERS_4,
++		REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
++
++	if (REG(NOM_PARAMETERS_2))
++		REG_GET(NOM_PARAMETERS_2,
++			DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
++
++	if (REG(NOM_PARAMETERS_3))
++		REG_GET(NOM_PARAMETERS_3,
++			REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
++
++	REG_GET(NOM_PARAMETERS_6,
++		DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
++
++	REG_GET(NOM_PARAMETERS_7,
++		REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
++
++	/* TTU - per hubp */
++	REG_GET_2(DCN_TTU_QOS_WM,
++		QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
++		QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
++
++	REG_GET_2(DCN_GLOBAL_TTU_CNTL,
++		MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
++		QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
++
++	/* TTU - per luma/chroma */
++	/* Assumed surf0 is luma and 1 is chroma */
++
++	REG_GET_3(DCN_SURF0_TTU_CNTL0,
++		REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
++		QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
++		QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
++
++	REG_GET(DCN_SURF0_TTU_CNTL1,
++		REFCYC_PER_REQ_DELIVERY_PRE,
++		&ttu_attr->refcyc_per_req_delivery_pre_l);
++
++	REG_GET_3(DCN_SURF1_TTU_CNTL0,
++		REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
++		QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
++		QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
++
++	REG_GET(DCN_SURF1_TTU_CNTL1,
++		REFCYC_PER_REQ_DELIVERY_PRE,
++		&ttu_attr->refcyc_per_req_delivery_pre_c);
++
++	/* Rest of hubp */
++	REG_GET(DCSURF_SURFACE_CONFIG,
++			SURFACE_PIXEL_FORMAT, &s->pixel_format);
++
++	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
++			SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
++
++	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
++			SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo);
++
++	REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
++			PRI_VIEWPORT_WIDTH, &s->viewport_width,
++			PRI_VIEWPORT_HEIGHT, &s->viewport_height);
++
++	REG_GET_2(DCSURF_SURFACE_CONFIG,
++			ROTATION_ANGLE, &s->rotation_angle,
++			H_MIRROR_EN, &s->h_mirror_en);
++
++	REG_GET(DCSURF_TILING_CONFIG,
++			SW_MODE, &s->sw_mode);
++
++	REG_GET(DCSURF_SURFACE_CONTROL,
++			PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
++
++	REG_GET_3(DCHUBP_CNTL,
++			HUBP_BLANK_EN, &s->blank_en,
++			HUBP_TTU_DISABLE, &s->ttu_disable,
++			HUBP_UNDERFLOW_STATUS, &s->underflow_status);
++
++	REG_GET(DCN_GLOBAL_TTU_CNTL,
++			MIN_TTU_VBLANK, &s->min_ttu_vblank);
++
++	REG_GET_2(DCN_TTU_QOS_WM,
++			QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
++			QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
++
++}
++
++void hubp2_read_state(struct hubp *hubp)
++{
++	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
++	struct dcn_hubp_state *s = &hubp2->state;
++	struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
++
++	hubp2_read_state_common(hubp);
++
++	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
++		CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
++		MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
++		META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
++		MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
++		DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
++		MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
++		SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
++		PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
++
++	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
++		CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
++		MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
++		META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
++		MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
++		DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
++		MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
++		SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
++		PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
++
++}
++
+ static struct hubp_funcs dcn20_hubp_funcs = {
+ 	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
+ 	.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
+ 	.hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr,
+ 	.hubp_program_surface_config = hubp2_program_surface_config,
+-	.hubp_is_flip_pending = hubp1_is_flip_pending,
++	.hubp_is_flip_pending = hubp2_is_flip_pending,
+ 	.hubp_setup = hubp2_setup,
+ 	.hubp_setup_interdependent = hubp2_setup_interdependent,
+ 	.hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings,
+-	.set_blank = hubp1_set_blank,
+-	.dcc_control = hubp1_dcc_control,
++	.set_blank = hubp2_set_blank,
++	.dcc_control = hubp2_dcc_control,
+ 	.hubp_update_dchub = hubp2_update_dchub,
+ 	.mem_program_viewport = min_set_viewport,
+ 	.set_cursor_attributes	= hubp2_cursor_set_attributes,
+-	.set_cursor_position	= hubp1_cursor_set_position,
+-	.hubp_clk_cntl = hubp1_clk_cntl,
+-	.hubp_vtg_sel = hubp1_vtg_sel,
++	.set_cursor_position	= hubp2_cursor_set_position,
++	.hubp_clk_cntl = hubp2_clk_cntl,
++	.hubp_vtg_sel = hubp2_vtg_sel,
+ 	.dmdata_set_attributes = hubp2_dmdata_set_attributes,
+ 	.dmdata_load = hubp2_dmdata_load,
+ 	.dmdata_status_done = hubp2_dmdata_status_done,
+-	.hubp_read_state = hubp1_read_state,
+-	.hubp_clear_underflow = hubp1_clear_underflow,
++	.hubp_read_state = hubp2_read_state,
++	.hubp_clear_underflow = hubp2_clear_underflow,
+ 	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
+ 	.hubp_init = hubp1_init,
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+index 2c6405a62fc1..c8418235e154 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+@@ -267,6 +267,24 @@ bool hubp2_program_surface_flip_and_addr(
+ 	const struct dc_plane_address *address,
+ 	bool flip_immediate);
+ 
++void hubp2_dcc_control(struct hubp *hubp, bool enable,
++		bool independent_64b_blks);
++
++void hubp2_program_size(
++	struct hubp *hubp,
++	enum surface_pixel_format format,
++	const union plane_size *plane_size,
++	struct dc_plane_dcc_param *dcc);
++
++void hubp2_program_rotation(
++	struct hubp *hubp,
++	enum dc_rotation_angle rotation,
++	bool horizontal_mirror);
++
++void hubp2_program_pixel_format(
++	struct hubp *hubp,
++	enum surface_pixel_format format);
++
+ void hubp2_program_surface_config(
+ 	struct hubp *hubp,
+ 	enum surface_pixel_format format,
+@@ -277,6 +295,25 @@ void hubp2_program_surface_config(
+ 	bool horizontal_mirror,
+ 	unsigned int compat_level);
+ 
++bool hubp2_is_flip_pending(struct hubp *hubp);
++
++void hubp2_set_blank(struct hubp *hubp, bool blank);
++
++void hubp2_cursor_set_position(
++		struct hubp *hubp,
++		const struct dc_cursor_position *pos,
++		const struct dc_cursor_mi_param *param);
++
++void hubp2_clk_cntl(struct hubp *hubp, bool enable);
++
++void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst);
++
++void hubp2_clear_underflow(struct hubp *hubp);
++
++void hubp2_read_state_common(struct hubp *hubp);
++
++void hubp2_read_state(struct hubp *hubp);
++
+ #endif /* __DC_MEM_INPUT_DCN20_H__ */
+ 
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3044-drm-amd-display-Read-max-down-spread.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3044-drm-amd-display-Read-max-down-spread.patch
new file mode 100644
index 00000000..3f14f76f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3044-drm-amd-display-Read-max-down-spread.patch
@@ -0,0 +1,47 @@
+From 341e27e01cf40e83b168b22c11a56acb537ec292 Mon Sep 17 00:00:00 2001
+From: Derek Lai <Derek.Lai@amd.com>
+Date: Tue, 18 Jun 2019 14:55:57 +0800
+Subject: [PATCH 3044/4256] drm/amd/display: Read max down spread
+
+[Why]
+When launch D10.2, driver will write DPCD 0x107 with 0x00
+
+[How]
+Read MAX_DOWNSPREAD (0x0003h) then keep in current
+link settings
+
+Signed-off-by: Derek Lai <Derek.Lai@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 168b853434d7..fdce64c288c5 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -530,6 +530,7 @@ static void read_edp_current_link_settings_on_detect(struct dc_link *link)
+ 	uint32_t read_dpcd_retry_cnt = 10;
+ 	enum dc_status status = DC_ERROR_UNEXPECTED;
+ 	int i;
++	union max_down_spread max_down_spread = { {0} };
+ 
+ 	// Read DPCD 00101h to find out the number of lanes currently set
+ 	for (i = 0; i < read_dpcd_retry_cnt; i++) {
+@@ -574,6 +575,12 @@ static void read_edp_current_link_settings_on_detect(struct dc_link *link)
+ 		link->cur_link_settings.link_rate = link_bw_set;
+ 		link->cur_link_settings.use_link_rate_set = false;
+ 	}
++	// Read DPCD 00003h to find the max down spread.
++	core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
++			&max_down_spread.raw, sizeof(max_down_spread));
++	link->cur_link_settings.link_spread =
++		max_down_spread.bits.MAX_DOWN_SPREAD ?
++		LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
+ }
+ 
+ static bool detect_dp(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3045-drm-amd-display-Remove-dsc-disable_ich-flag-programm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3045-drm-amd-display-Remove-dsc-disable_ich-flag-programm.patch
new file mode 100644
index 00000000..f3951e00
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3045-drm-amd-display-Remove-dsc-disable_ich-flag-programm.patch
@@ -0,0 +1,68 @@
+From 0cb4e22d1ee24a6a9522bd36252ce7ed39ba5624 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Tue, 18 Jun 2019 15:57:03 -0400
+Subject: [PATCH 3045/4256] drm/amd/display: Remove dsc disable_ich flag
+ programming.
+
+Current default is sufficient for a flag that does not change.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 8 +++++---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h | 4 ++--
+ 2 files changed, 7 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+index ffd0014ec3b5..e870caa8d4fa 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+@@ -436,7 +436,7 @@ static void dsc_init_reg_values(struct dsc_reg_values *reg_vals)
+ 	reg_vals->ich_reset_at_eol            = 0;
+ 	reg_vals->alternate_ich_encoding_en   = 0;
+ 	reg_vals->rc_buffer_model_size        = 0;
+-	reg_vals->disable_ich                 = 0;
++	/*reg_vals->disable_ich                 = 0;*/
+ 	reg_vals->dsc_dbg_en                  = 0;
+ 
+ 	for (i = 0; i < 4; i++)
+@@ -518,9 +518,11 @@ static void dsc_write_to_registers(struct display_stream_compressor *dsc, const
+ 		ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en,
+ 		NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1);
+ 
+-	REG_SET_2(DSCC_CONFIG1, 0,
++	REG_SET(DSCC_CONFIG1, 0,
++			DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size);
++	/*REG_SET_2(DSCC_CONFIG1, 0,
+ 		DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size,
+-		DSCC_DISABLE_ICH, reg_vals->disable_ich);
++		DSCC_DISABLE_ICH, reg_vals->disable_ich);*/
+ 
+ 	REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0,
+ 		DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0],
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
+index 168865a16288..4e2fb38390a4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
+@@ -103,7 +103,7 @@
+ 	DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \
+ 	DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, mask_sh), \
+ 	DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, mask_sh), \
+-	DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_DISABLE_ICH, mask_sh), \
++	/*DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_DISABLE_ICH, mask_sh),*/ \
+ 	DSC_SF(DSCC0_DSCC_STATUS, DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \
+ 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED, mask_sh), \
+ 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED, mask_sh), \
+@@ -278,7 +278,7 @@
+ 	type ALTERNATE_ICH_ENCODING_EN; \
+ 	type NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION; \
+ 	type DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE; \
+-	type DSCC_DISABLE_ICH; \
++	/*type DSCC_DISABLE_ICH;*/ \
+ 	type DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING; \
+ 	type DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED; \
+ 	type DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED; \
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3046-drm-amd-display-Power-gate-all-DSCs-at-driver-init-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3046-drm-amd-display-Power-gate-all-DSCs-at-driver-init-t.patch
new file mode 100644
index 00000000..47745cda
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3046-drm-amd-display-Power-gate-all-DSCs-at-driver-init-t.patch
@@ -0,0 +1,40 @@
+From aa07dc450ffff6826e4877f410143ebcd01f6e0e Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Wed, 19 Jun 2019 14:30:52 -0400
+Subject: [PATCH 3046/4256] drm/amd/display: Power-gate all DSCs at driver init
+ time
+
+[why]
+DSC should be powered-on only on as-needed basis, i.e. if the mode
+requires it
+
+[how]
+Loop over all the DSCs at driver init time and power-gate each
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index db57c2a99a15..b753e40c4196 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -599,6 +599,12 @@ static void dcn20_init_hw(struct dc *dc)
+ 		}
+ 	}
+ 
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	/* Power gate DSCs */
++	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
++		dcn20_dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
++#endif
++
+ 	/* Blank pixel data with OPP DPG */
+ 	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
+ 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3047-drm-amd-display-Disable-Audio-on-reinitialize-hardwa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3047-drm-amd-display-Disable-Audio-on-reinitialize-hardwa.patch
new file mode 100644
index 00000000..f2a3258d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3047-drm-amd-display-Disable-Audio-on-reinitialize-hardwa.patch
@@ -0,0 +1,77 @@
+From 61873a1b8b322fc2a6e26da460a518ccd0d7ea36 Mon Sep 17 00:00:00 2001
+From: Alvin Lee <alvin.lee2@amd.com>
+Date: Thu, 20 Jun 2019 13:03:25 -0400
+Subject: [PATCH 3047/4256] drm/amd/display: Disable Audio on reinitialize
+ hardware
+
+[Why]
+When we recover from hang, we do not want to skip the audio enable call.
+
+[How]
+Disable audio in dc_reinitialize_hardware
+
+Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  |  1 +
+ .../display/dc/dce110/dce110_hw_sequencer.c   | 20 +++++++++++++++----
+ 2 files changed, 17 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index 614a941eb9f2..e9a7a7af11df 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -331,6 +331,7 @@ void dcn20_clk_mgr_construct(
+ 		struct dccg *dccg)
+ {
+ 	clk_mgr->base.ctx = ctx;
++	clk_mgr->pp_smu = pp_smu;
+ 	clk_mgr->base.funcs = &dcn2_funcs;
+ 	clk_mgr->regs = &clk_mgr_regs;
+ 	clk_mgr->clk_mgr_shift = &clk_mgr_shift;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 6fa1f6b5375b..fedbc6d0c40d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -962,11 +962,17 @@ void hwss_edp_backlight_control(
+ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
+ {
+ 	/* notify audio driver for audio modes of monitor */
+-	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
++	struct dc *core_dc;
+ 	struct pp_smu_funcs *pp_smu = NULL;
+-	struct clk_mgr *clk_mgr = core_dc->clk_mgr;
++	struct clk_mgr *clk_mgr;
+ 	unsigned int i, num_audio = 1;
+ 
++	if (!pipe_ctx->stream)
++		return;
++
++	core_dc = pipe_ctx->stream->ctx->dc;
++	clk_mgr = core_dc->clk_mgr;
++
+ 	if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
+ 		return;
+ 
+@@ -996,9 +1002,15 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
+ 
+ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
+ {
+-	struct dc *dc = pipe_ctx->stream->ctx->dc;
++	struct dc *dc;
+ 	struct pp_smu_funcs *pp_smu = NULL;
+-	struct clk_mgr *clk_mgr = dc->clk_mgr;
++	struct clk_mgr *clk_mgr;
++
++	if (!pipe_ctx || !pipe_ctx->stream)
++		return;
++
++	dc = pipe_ctx->stream->ctx->dc;
++	clk_mgr = dc->clk_mgr;
+ 
+ 	if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
+ 		return;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3048-drm-amd-display-fix-DMCU-hang-when-going-into-Modern.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3048-drm-amd-display-fix-DMCU-hang-when-going-into-Modern.patch
new file mode 100644
index 00000000..f7104f1b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3048-drm-amd-display-fix-DMCU-hang-when-going-into-Modern.patch
@@ -0,0 +1,55 @@
+From ec8ce00544e202a41f305ccf6a23414992870195 Mon Sep 17 00:00:00 2001
+From: Zi Yu Liao <ziyu.liao@amd.com>
+Date: Thu, 20 Jun 2019 10:55:26 -0400
+Subject: [PATCH 3048/4256] drm/amd/display: fix DMCU hang when going into
+ Modern Standby
+
+[why]
+When the system is going into suspend, set_backlight gets called
+after the eDP got blanked. Since smooth brightness is enabled,
+the driver will make a call into the DMCU to ramp the brightness.
+The DMCU would try to enable ABM to do so. But since the display is
+blanked, this ends up causing ABM1_ACE_DBUF_REG_UPDATE_PENDING to
+get stuck at 1, which results in a dead lock in the DMCU firmware.
+
+[how]
+Disable brightness ramping when the eDP display is blanked.
+
+Signed-off-by: Zi Yu Liao <ziyu.liao@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index fdce64c288c5..b7c2ac3033f2 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2350,7 +2350,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link,
+ 			if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) {
+ 				if (core_dc->current_state->res_ctx.
+ 						pipe_ctx[i].stream->link
+-						== link)
++						== link) {
+ 					/* DMCU -1 for all controller id values,
+ 					 * therefore +1 here
+ 					 */
+@@ -2358,6 +2358,13 @@ bool dc_link_set_backlight_level(const struct dc_link *link,
+ 						core_dc->current_state->
+ 						res_ctx.pipe_ctx[i].stream_res.tg->inst +
+ 						1;
++
++					/* Disable brightness ramping when the display is blanked
++					 * as it can hang the DMCU
++					 */
++					if (core_dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL)
++						frame_ramp = 0;
++				}
+ 			}
+ 		}
+ 		abm->funcs->set_backlight_level_pwm(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3049-drm-amd-display-Do-not-fill-Null-packet-in-the-blank.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3049-drm-amd-display-Do-not-fill-Null-packet-in-the-blank.patch
new file mode 100644
index 00000000..a54837d8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3049-drm-amd-display-Do-not-fill-Null-packet-in-the-blank.patch
@@ -0,0 +1,59 @@
+From fcbf8cb16721bc5abf5f310ce6254aeed981e0f9 Mon Sep 17 00:00:00 2001
+From: Charlene Liu <charlene.liu@amd.com>
+Date: Wed, 19 Jun 2019 21:35:35 -0400
+Subject: [PATCH 3049/4256] drm/amd/display: Do not fill Null packet in the
+ blank period
+
+[Description]
+Do not fill Null packet in the blank period for new packet gen
+This is based on HW IP team recommended default setting change.
+
+Signed-off-by: Charlene Liu <charlene.liu@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 3 ++-
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h | 2 ++
+ 2 files changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+index 64adb9fb300c..a098287d71ae 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+@@ -511,11 +511,12 @@ void enc1_stream_encoder_hdmi_set_stream_attribute(
+ 	enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
+ 
+ 	/* setup HDMI engine */
+-	REG_UPDATE_5(HDMI_CONTROL,
++	REG_UPDATE_6(HDMI_CONTROL,
+ 		HDMI_PACKET_GEN_VERSION, 1,
+ 		HDMI_KEEPOUT_MODE, 1,
+ 		HDMI_DEEP_COLOR_ENABLE, 0,
+ 		HDMI_DATA_SCRAMBLE_EN, 0,
++		HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
+ 		HDMI_CLOCK_CHANNEL_RATE, 0);
+ 
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+index 075e49c1283a..ab0ead3c3f46 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+@@ -189,6 +189,7 @@ struct dcn10_stream_enc_registers {
+ 	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
+ 	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
+ 	SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
++	SE_SF(DIG0_HDMI_CONTROL, HDMI_NO_EXTRA_NULL_PACKET_FILLED, mask_sh),\
+ 	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
+ 	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
+ 	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
+@@ -374,6 +375,7 @@ struct dcn10_stream_enc_registers {
+ 	type HDMI_GC_SEND;\
+ 	type HDMI_NULL_SEND;\
+ 	type HDMI_DATA_SCRAMBLE_EN;\
++	type HDMI_NO_EXTRA_NULL_PACKET_FILLED;\
+ 	type HDMI_AUDIO_INFO_SEND;\
+ 	type AFMT_AUDIO_INFO_UPDATE;\
+ 	type HDMI_AUDIO_INFO_LINE;\
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3050-drm-amd-display-Remove-unnecessary-NULL-check-in-set.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3050-drm-amd-display-Remove-unnecessary-NULL-check-in-set.patch
new file mode 100644
index 00000000..f3ffa336
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3050-drm-amd-display-Remove-unnecessary-NULL-check-in-set.patch
@@ -0,0 +1,56 @@
+From 5af27eaf2f6385cce2874b4a0c5749ad193c40be Mon Sep 17 00:00:00 2001
+From: Harry Wentland <harry.wentland@amd.com>
+Date: Fri, 31 May 2019 14:17:43 -0400
+Subject: [PATCH 3050/4256] drm/amd/display: Remove unnecessary NULL check in
+ set_preferred_link_settings
+
+[Why]
+link_stream is never NULL here as we've dereferenced it a couple lines before
+and have done so for a couple months now.
+
+[How]
+- Drop the NULL check.
+- Initialize where we know link_stream is non-NULL
+
+Signed-off-by: Harry Wentland <harry.wentland@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 9 ++++-----
+ 1 file changed, 4 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index b7c2ac3033f2..815b687de494 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -3021,8 +3021,10 @@ void dc_link_set_preferred_link_settings(struct dc *dc,
+ 	for (i = 0; i < MAX_PIPES; i++) {
+ 		pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+ 		if (pipe->stream && pipe->stream->link) {
+-			if (pipe->stream->link == link)
++			if (pipe->stream->link == link) {
++				link_stream = pipe->stream;
+ 				break;
++			}
+ 		}
+ 	}
+ 
+@@ -3030,14 +3032,11 @@ void dc_link_set_preferred_link_settings(struct dc *dc,
+ 	if (i == MAX_PIPES)
+ 		return;
+ 
+-	link_stream = link->dc->current_state->res_ctx.pipe_ctx[i].stream;
+-
+ 	/* Cannot retrain link if backend is off */
+ 	if (link_stream->dpms_off)
+ 		return;
+ 
+-	if (link_stream)
+-		decide_link_settings(link_stream, &store_settings);
++	decide_link_settings(link_stream, &store_settings);
+ 
+ 	if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
+ 		(store_settings.link_rate != LINK_RATE_UNKNOWN))
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3051-drm-amd-display-use-encoder-s-engine-id-to-find-matc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3051-drm-amd-display-use-encoder-s-engine-id-to-find-matc.patch
new file mode 100644
index 00000000..a991332f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3051-drm-amd-display-use-encoder-s-engine-id-to-find-matc.patch
@@ -0,0 +1,53 @@
+From 3393bebc0dc28f5ac9faa381b4a756ad96ac412e Mon Sep 17 00:00:00 2001
+From: Tai Man <taiman.wong@amd.com>
+Date: Fri, 7 Jun 2019 17:32:27 -0400
+Subject: [PATCH 3051/4256] drm/amd/display: use encoder's engine id to find
+ matched free audio device
+
+[Why]
+On some platforms, the encoder id 3 is not populated. So the encoders
+are not stored in right order as index (id: 0, 1, 2, 4, 5) at pool. This
+would cause encoders id 4 & id 5 to fail when finding corresponding
+audio device, defaulting to the first available audio device. As result,
+we cannot stream audio into two DP ports with encoders id 4 & id 5.
+
+[How]
+It need to create enough audio device objects (0 - 5) to perform matching.
+Then use encoder engine id to find matched audio device.
+
+Signed-off-by: Tai Man <taiman.wong@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 5b85139fb3ce..5e7b8b2dd178 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -265,7 +265,7 @@ bool resource_construct(
+ 		 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
+ 		 */
+ 		update_num_audio(&straps, &num_audio, &pool->audio_support);
+-		for (i = 0; i < pool->pipe_count && i < num_audio; i++) {
++		for (i = 0; i < caps->num_audio; i++) {
+ 			struct audio *aud = create_funcs->create_audio(ctx, i);
+ 
+ 			if (aud == NULL) {
+@@ -1676,6 +1676,12 @@ static struct audio *find_first_free_audio(
+ 			return pool->audios[i];
+ 		}
+ 	}
++
++    /* use engine id to find free audio */
++	if ((id < pool->audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
++		return pool->audios[id];
++	}
++
+ 	/*not found the matching one, first come first serve*/
+ 	for (i = 0; i < pool->audio_count; i++) {
+ 		if (res_ctx->is_audio_acquired[i] == false) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3052-drm-amd-display-fix-not-calling-ppsmu-to-trigger-PME.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3052-drm-amd-display-fix-not-calling-ppsmu-to-trigger-PME.patch
new file mode 100644
index 00000000..a1d9fd77
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3052-drm-amd-display-fix-not-calling-ppsmu-to-trigger-PME.patch
@@ -0,0 +1,36 @@
+From 111395239f9f23713ffab278444e9a81eb3754ee Mon Sep 17 00:00:00 2001
+From: Su Sung Chung <Su.Chung@amd.com>
+Date: Fri, 21 Jun 2019 16:14:36 -0400
+Subject: [PATCH 3052/4256] drm/amd/display: fix not calling ppsmu to trigger
+ PME
+
+[why]
+dcn20_clk_mgr_construct was not initializing pp_smu, and PME call gets
+filtered out by the null check
+
+[how]
+initialize pp_smu dcn20_clk_mgr_construct
+
+Signed-off-by: Su Sung Chung <Su.Chung@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index e9a7a7af11df..4842c91771d8 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -346,6 +346,8 @@ void dcn20_clk_mgr_construct(
+ 
+ 	clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
+ 
++	clk_mgr->pp_smu = pp_smu;
++
+ 	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
+ 		dcn2_funcs.update_clocks = dcn2_update_clocks_fpga;
+ 		clk_mgr->dentist_vco_freq_khz = 3850000;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3053-drm-amd-display-Change-min_h_sync_width-from-8-to-4.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3053-drm-amd-display-Change-min_h_sync_width-from-8-to-4.patch
new file mode 100644
index 00000000..a4173401
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3053-drm-amd-display-Change-min_h_sync_width-from-8-to-4.patch
@@ -0,0 +1,41 @@
+From e64143d2703ef981b8119c6f3db77fc939639300 Mon Sep 17 00:00:00 2001
+From: Fatemeh Darbehani <fatemeh.darbehani@amd.com>
+Date: Fri, 21 Jun 2019 17:44:50 -0400
+Subject: [PATCH 3053/4256] drm/amd/display: Change min_h_sync_width from 8 to
+ 4
+
+[Why]
+Some display's hsync width is lower than the minimum dcn20 is set
+to support right now. This will cause optc1_validate_timing to fail which
+eventually will result in wrong set mode. This was set to 8 as per
+HW team's request for no valid reason.
+
+[How]
+Changing min_h_sync_width to 4 will let us validate timing for
+preffered mode and light up the headset. This change was made
+to Vega 10 before for a similar issue.
+
+Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com>
+Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
+Acked-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+index 26a66ccf6e72..1ae973962d53 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+@@ -535,7 +535,7 @@ void dcn20_timing_generator_init(struct optc *optc1)
+ 	optc1->min_h_blank = 32;
+ 	optc1->min_v_blank = 3;
+ 	optc1->min_v_blank_interlace = 5;
+-	optc1->min_h_sync_width = 8;
++	optc1->min_h_sync_width = 4;//	Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue.
+ 	optc1->min_v_sync_width = 1;
+ 	optc1->comb_opp_id = 0xf;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3054-drm-amd-display-Remove-second-initialization-of-pp_s.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3054-drm-amd-display-Remove-second-initialization-of-pp_s.patch
new file mode 100644
index 00000000..2a410db0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3054-drm-amd-display-Remove-second-initialization-of-pp_s.patch
@@ -0,0 +1,35 @@
+From 47ec76f175b71d3b9ded126e4ae9b0ad6ac7ed1d Mon Sep 17 00:00:00 2001
+From: Alvin Lee <alvin.lee2@amd.com>
+Date: Fri, 21 Jun 2019 17:58:41 -0400
+Subject: [PATCH 3054/4256] drm/amd/display: Remove second initialization of
+ pp_smu
+
+[why]
+We initialize pp_smu twice
+
+[how]
+Remove second initialization of pp_smu
+
+Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
+Reviewed-by: Jaehyun Chung <Jaehyun.Chung@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index 4842c91771d8..e9a7a7af11df 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -346,8 +346,6 @@ void dcn20_clk_mgr_construct(
+ 
+ 	clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
+ 
+-	clk_mgr->pp_smu = pp_smu;
+-
+ 	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
+ 		dcn2_funcs.update_clocks = dcn2_update_clocks_fpga;
+ 		clk_mgr->dentist_vco_freq_khz = 3850000;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3055-drm-amd-display-3.2.40.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3055-drm-amd-display-3.2.40.patch
new file mode 100644
index 00000000..9918292b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3055-drm-amd-display-3.2.40.patch
@@ -0,0 +1,27 @@
+From 3b830f1dafa24edce199361e956657c9269c8729 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Sun, 23 Jun 2019 17:27:43 -0400
+Subject: [PATCH 3055/4256] drm/amd/display: 3.2.40
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 84f602457a9e..441d0c376a9f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -42,7 +42,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.39"
++#define DC_VER "3.2.40"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3056-drm-amd-display-Wait-for-flip-to-complete.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3056-drm-amd-display-Wait-for-flip-to-complete.patch
new file mode 100644
index 00000000..a9b13be5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3056-drm-amd-display-Wait-for-flip-to-complete.patch
@@ -0,0 +1,43 @@
+From b713b48f76896f3c7bc345888bb1be0a869b1389 Mon Sep 17 00:00:00 2001
+From: Alvin Lee <alvin.lee2@amd.com>
+Date: Mon, 24 Jun 2019 09:49:44 -0400
+Subject: [PATCH 3056/4256] drm/amd/display: Wait for flip to complete
+
+[why]
+In pipe split issue occurs when we program immediate flip while vsync flip is pending
+
+[how]
+Don't program immediate flip until flip is no longer pending
+
+Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
+Reviewed-by: Jaehyun Chung <Jaehyun.Chung@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index b753e40c4196..b089ba1c7614 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1285,6 +1285,17 @@ void dcn20_pipe_control_lock(
+ 	if (pipe->plane_state != NULL)
+ 		flip_immediate = pipe->plane_state->flip_immediate;
+ 
++	if (flip_immediate && lock) {
++		while (pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp))	{
++			udelay(1);
++		}
++
++		if (pipe->bottom_pipe != NULL)
++			while (pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp))	{
++				udelay(1);
++			}
++	}
++
+ 	/* In flip immediate and pipe splitting case, we need to use GSL
+ 	 * for synchronization. Only do setup on locking and on flip type change.
+ 	 */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3057-drm-amd-display-Implement-generic-MUX-registers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3057-drm-amd-display-Implement-generic-MUX-registers.patch
new file mode 100644
index 00000000..c71e05d2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3057-drm-amd-display-Implement-generic-MUX-registers.patch
@@ -0,0 +1,408 @@
+From 7de1bb6103448dfcc8adddfc4f4d3a9762b668e9 Mon Sep 17 00:00:00 2001
+From: Murton Liu <murton.liu@amd.com>
+Date: Mon, 24 Jun 2019 11:28:06 -0400
+Subject: [PATCH 3057/4256] drm/amd/display: Implement generic MUX registers
+
+[Why]
+Logic & structures for generic regs does not exist in DC currently.
+
+[How]
+Implement register masks/shifts and relevant functions for generic mux,
+similar to existing HPD and DDC objects.
+
+Signed-off-by: Murton Liu <murton.liu@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Joshua Aberback <Joshua.Aberback@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/gpio/Makefile  |   2 +-
+ .../display/dc/gpio/dcn20/hw_factory_dcn20.c  |  41 +++++-
+ .../dc/gpio/diagnostics/hw_factory_diag.c     |   1 +
+ .../drm/amd/display/dc/gpio/generic_regs.h    |  66 +++++++++
+ .../gpu/drm/amd/display/dc/gpio/hw_factory.h  |   3 +
+ .../gpu/drm/amd/display/dc/gpio/hw_generic.c  | 132 ++++++++++++++++++
+ .../gpu/drm/amd/display/dc/gpio/hw_generic.h  |  46 ++++++
+ 7 files changed, 288 insertions(+), 3 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+index c3d92878875d..113affea49bf 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+@@ -24,7 +24,7 @@
+ # It provides the control and status of HW GPIO pins.
+ 
+ GPIO = gpio_base.o gpio_service.o hw_factory.o \
+-       hw_gpio.o hw_hpd.o hw_ddc.o hw_translate.o
++       hw_gpio.o hw_hpd.o hw_ddc.o hw_generic.o hw_translate.o
+ 
+ AMD_DAL_GPIO = $(addprefix $(AMDDALPATH)/dc/gpio/,$(GPIO))
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
+index abd76d855375..afb7c0f111bf 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
+@@ -31,6 +31,7 @@
+ #include "../hw_gpio.h"
+ #include "../hw_ddc.h"
+ #include "../hw_hpd.h"
++#include "../hw_generic.h"
+ 
+ #include "hw_factory_dcn20.h"
+ 
+@@ -138,6 +139,32 @@ static const struct ddc_sh_mask ddc_mask[] = {
+ 	DDC_MASK_SH_LIST_DCN2(_MASK, 6)
+ };
+ 
++#include "../generic_regs.h"
++
++/* set field name */
++#define SF_GENERIC(reg_name, field_name, post_fix)\
++	.field_name = reg_name ## __ ## field_name ## post_fix
++
++#define generic_regs(id) \
++{\
++	GENERIC_REG_LIST(id)\
++}
++
++static const struct generic_registers generic_regs[] = {
++	generic_regs(A),
++	generic_regs(B),
++};
++
++static const struct generic_sh_mask generic_shift[] = {
++	GENERIC_MASK_SH_LIST(__SHIFT, A),
++	GENERIC_MASK_SH_LIST(__SHIFT, B),
++};
++
++static const struct generic_sh_mask generic_mask[] = {
++	GENERIC_MASK_SH_LIST(_MASK, A),
++	GENERIC_MASK_SH_LIST(_MASK, B),
++};
++
+ static void define_ddc_registers(
+ 		struct hw_gpio_pin *pin,
+ 		uint32_t en)
+@@ -173,17 +200,27 @@ static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
+ 	hpd->base.regs = &hpd_regs[en].gpio;
+ }
+ 
++static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
++{
++	struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
++
++	generic->regs = &generic_regs[en];
++	generic->shifts = &generic_shift[en];
++	generic->masks = &generic_mask[en];
++	generic->base.regs = &generic_regs[en].gpio;
++}
+ 
+ /* fucntion table */
+ static const struct hw_factory_funcs funcs = {
+ 	.create_ddc_data = dal_hw_ddc_create,
+ 	.create_ddc_clock = dal_hw_ddc_create,
+-	.create_generic = NULL,
++	.create_generic = dal_hw_generic_create,
+ 	.create_hpd = dal_hw_hpd_create,
+ 	.create_sync = NULL,
+ 	.create_gsl = NULL,
+ 	.define_hpd_registers = define_hpd_registers,
+-	.define_ddc_registers = define_ddc_registers
++	.define_ddc_registers = define_ddc_registers,
++	.define_generic_registers = define_generic_registers,
+ };
+ /*
+  * dal_hw_factory_dcn10_init
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c b/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c
+index 26695b963c58..f15288c3986e 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c
+@@ -38,6 +38,7 @@
+ #include "../hw_gpio.h"
+ #include "../hw_ddc.h"
+ #include "../hw_hpd.h"
++#include "../hw_generic.h"
+ 
+ /* function table */
+ static const struct hw_factory_funcs funcs = {
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h b/drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h
+new file mode 100644
+index 000000000000..8c05295c05c2
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h
+@@ -0,0 +1,66 @@
++/*
++ * Copyright 2012-16 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_GENERIC_REGS_H_
++#define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_GENERIC_REGS_H_
++
++#include "gpio_regs.h"
++
++#define GENERIC_GPIO_REG_LIST_ENTRY(type, cd, id) \
++	.type ## _reg =  REG(DC_GPIO_GENERIC_## type),\
++	.type ## _mask =  DC_GPIO_GENERIC_ ## type ## __DC_GPIO_GENERIC ## id ## _ ## type ## _MASK,\
++	.type ## _shift = DC_GPIO_GENERIC_ ## type ## __DC_GPIO_GENERIC ## id ## _ ## type ## __SHIFT
++
++#define GENERIC_GPIO_REG_LIST(id) \
++	{\
++	GENERIC_GPIO_REG_LIST_ENTRY(MASK, cd, id),\
++	GENERIC_GPIO_REG_LIST_ENTRY(A, cd, id),\
++	GENERIC_GPIO_REG_LIST_ENTRY(EN, cd, id),\
++	GENERIC_GPIO_REG_LIST_ENTRY(Y, cd, id)\
++	}
++
++#define GENERIC_REG_LIST(id) \
++	GENERIC_GPIO_REG_LIST(id), \
++	.mux = REG(DC_GENERIC ## id),\
++
++#define GENERIC_MASK_SH_LIST(mask_sh, cd) \
++	{(DC_GENERIC ## cd ##__GENERIC ## cd ##_EN## mask_sh),\
++	(DC_GENERIC ## cd ##__GENERIC ## cd ##_SEL## mask_sh)}
++
++struct generic_registers {
++	struct gpio_registers gpio;
++	uint32_t mux;
++};
++
++struct generic_sh_mask {
++	/* enable */
++	uint32_t GENERIC_EN;
++	/* select */
++	uint32_t GENERIC_SEL;
++
++};
++
++
++#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_GENERIC_REGS_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h
+index 6e4dd3521935..7017c9337348 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h
+@@ -63,6 +63,9 @@ struct hw_factory {
+ 		void (*define_ddc_registers)(
+ 				struct hw_gpio_pin *pin,
+ 				uint32_t en);
++		void (*define_generic_registers)(
++				struct hw_gpio_pin *pin,
++				uint32_t en);
+ 	} *funcs;
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
+new file mode 100644
+index 000000000000..ea0a1fc8cf23
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
+@@ -0,0 +1,132 @@
++/*
++ * Copyright 2012-15 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "dm_services.h"
++
++#include "include/gpio_types.h"
++#include "hw_gpio.h"
++#include "hw_generic.h"
++
++#include "reg_helper.h"
++#include "generic_regs.h"
++
++#undef FN
++#define FN(reg_name, field_name) \
++	generic->shifts->field_name, generic->masks->field_name
++
++#define CTX \
++	generic->base.base.ctx
++#define REG(reg)\
++	(generic->regs->reg)
++
++static void dal_hw_generic_construct(
++	struct hw_generic *pin,
++	enum gpio_id id,
++	uint32_t en,
++	struct dc_context *ctx)
++{
++	dal_hw_gpio_construct(&pin->base, id, en, ctx);
++}
++
++static void dal_hw_generic_destruct(
++	struct hw_generic *pin)
++{
++	dal_hw_gpio_destruct(&pin->base);
++}
++
++static void destroy(
++	struct hw_gpio_pin **ptr)
++{
++	struct hw_generic *generic = HW_GENERIC_FROM_BASE(*ptr);
++
++	dal_hw_generic_destruct(generic);
++
++	kfree(generic);
++
++	*ptr = NULL;
++}
++
++static enum gpio_result set_config(
++	struct hw_gpio_pin *ptr,
++	const struct gpio_config_data *config_data)
++{
++	struct hw_generic *generic = HW_GENERIC_FROM_BASE(ptr);
++
++	if (!config_data)
++		return GPIO_RESULT_INVALID_DATA;
++
++	REG_UPDATE_2(mux,
++		GENERIC_EN, config_data->config.generic_mux.enable_output_from_mux,
++		GENERIC_SEL, config_data->config.generic_mux.mux_select);
++
++	return GPIO_RESULT_OK;
++}
++
++static const struct hw_gpio_pin_funcs funcs = {
++	.destroy = destroy,
++	.open = dal_hw_gpio_open,
++	.get_value = dal_hw_gpio_get_value,
++	.set_value = dal_hw_gpio_set_value,
++	.set_config = set_config,
++	.change_mode = dal_hw_gpio_change_mode,
++	.close = dal_hw_gpio_close,
++};
++
++static void construct(
++	struct hw_generic *generic,
++	enum gpio_id id,
++	uint32_t en,
++	struct dc_context *ctx)
++{
++	dal_hw_generic_construct(generic, id, en, ctx);
++	generic->base.base.funcs = &funcs;
++}
++
++struct hw_gpio_pin *dal_hw_generic_create(
++	struct dc_context *ctx,
++	enum gpio_id id,
++	uint32_t en)
++{
++	struct hw_generic *generic;
++
++	if (id != GPIO_ID_GENERIC) {
++		ASSERT_CRITICAL(false);
++		return NULL;
++	}
++
++	if ((en < GPIO_GENERIC_MIN) || (en > GPIO_GENERIC_MAX)) {
++		ASSERT_CRITICAL(false);
++		return NULL;
++	}
++
++	generic = kzalloc(sizeof(struct hw_generic), GFP_KERNEL);
++	if (!generic) {
++		ASSERT_CRITICAL(false);
++		return NULL;
++	}
++
++	construct(generic, id, en, ctx);
++	return &generic->base.base;
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h
+new file mode 100644
+index 000000000000..3ea1c13e3ea6
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h
+@@ -0,0 +1,46 @@
++/*
++ * Copyright 2012-15 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DAL_HW_generic_H__
++#define __DAL_HW_generic_H__
++
++#include "generic_regs.h"
++
++struct hw_generic {
++	struct hw_gpio base;
++	const struct generic_registers *regs;
++	const struct generic_sh_mask *shifts;
++	const struct generic_sh_mask *masks;
++};
++
++#define HW_GENERIC_FROM_BASE(hw_gpio) \
++	container_of((HW_GPIO_FROM_BASE(hw_gpio)), struct hw_generic, base)
++
++struct hw_gpio_pin *dal_hw_generic_create(
++	struct dc_context *ctx,
++	enum gpio_id id,
++	uint32_t en);
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3058-drm-amd-display-Use-helper-for-determining-HDMI-sign.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3058-drm-amd-display-Use-helper-for-determining-HDMI-sign.patch
new file mode 100644
index 00000000..9ee3bb79
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3058-drm-amd-display-Use-helper-for-determining-HDMI-sign.patch
@@ -0,0 +1,31 @@
+From d5dff7f0d8ed67e94a04fb3defb2f9c9dea2ccb9 Mon Sep 17 00:00:00 2001
+From: Eric Bernstein <eric.bernstein@amd.com>
+Date: Mon, 24 Jun 2019 14:11:55 -0400
+Subject: [PATCH 3058/4256] drm/amd/display: Use helper for determining HDMI
+ signal
+
+Use helper to determine if HDMI signal when processing avmute.
+
+Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 815b687de494..64a8586a8476 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2858,7 +2858,7 @@ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
+ {
+ 	struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
+ 
+-	if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
++	if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
+ 		return;
+ 
+ 	core_dc->hwss.set_avmute(pipe_ctx, enable);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3059-drm-amd-display-Set-FEC_READY-always-before-link-tra.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3059-drm-amd-display-Set-FEC_READY-always-before-link-tra.patch
new file mode 100644
index 00000000..948a172e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3059-drm-amd-display-Set-FEC_READY-always-before-link-tra.patch
@@ -0,0 +1,109 @@
+From 874da5622bc0da927a23a2a80cbecd9ccd7ff771 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Mon, 24 Jun 2019 15:44:42 -0400
+Subject: [PATCH 3059/4256] drm/amd/display: Set FEC_READY always before link
+ training
+
+[why]
+Right now we FEC_READY is set only before the final link training,
+i.e. at mode set time. This means FEC_READY won't be set when doing
+link training as a response to HPD. It also fails UCD400 FEC test in
+DP compliance.
+
+[how]
+Move FEC_READY setup to link training.
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c  | 14 +++++---------
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c   | 18 +++++++++++++++---
+ 2 files changed, 20 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 64a8586a8476..e2f86fd07790 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -1521,15 +1521,6 @@ static enum dc_status enable_link_dp(
+ 	if (link_settings.link_rate == LINK_RATE_LOW)
+ 			skip_video_pattern = false;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-	if (link->preferred_training_settings.fec_enable != NULL)
+-		fec_enable = *link->preferred_training_settings.fec_enable;
+-	else
+-		fec_enable = true;
+-
+-	dp_set_fec_ready(link, fec_enable);
+-#endif
+-
+ 	if (link->aux_access_disabled) {
+ 		dc_link_dp_perform_link_training_skip_aux(link, &link_settings);
+ 
+@@ -1547,6 +1538,11 @@ static enum dc_status enable_link_dp(
+ 		status = DC_FAIL_DP_LINK_TRAINING;
+ 
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	if (link->preferred_training_settings.fec_enable != NULL)
++		fec_enable = *link->preferred_training_settings.fec_enable;
++	else
++		fec_enable = true;
++
+ 	dp_set_fec_enable(link, fec_enable);
+ #endif
+ 	return status;
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 4442e7b1e5b5..5c8e3318239c 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -1179,14 +1179,26 @@ enum link_training_result dc_link_dp_perform_link_training(
+ 	bool skip_video_pattern)
+ {
+ 	enum link_training_result status = LINK_TRAINING_SUCCESS;
+-
+ 	struct link_training_settings lt_settings;
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	bool fec_enable;
++#endif
+ 
+ 	initialize_training_settings(link, link_setting, &lt_settings);
+ 
+ 	/* 1. set link rate, lane count and spread. */
+ 	dpcd_set_link_settings(link, &lt_settings);
+ 
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	if (link->preferred_training_settings.fec_enable != NULL)
++		fec_enable = *link->preferred_training_settings.fec_enable;
++	else
++		fec_enable = true;
++
++	dp_set_fec_ready(link, fec_enable);
++#endif
++
++
+ 	/* 2. perform link training (set link training done
+ 	 *  to false is done as well)
+ 	 */
+@@ -3153,7 +3165,7 @@ void dp_set_fec_ready(struct dc_link *link, bool ready)
+ 
+ 	if (link_enc->funcs->fec_set_ready &&
+ 			link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
+-		if (link->fec_state == dc_link_fec_not_ready && ready) {
++		if (ready) {
+ 			fec_config = 1;
+ 			if (core_link_write_dpcd(link,
+ 					DP_FEC_CONFIGURATION,
+@@ -3164,7 +3176,7 @@ void dp_set_fec_ready(struct dc_link *link, bool ready)
+ 			} else {
+ 				dm_error("dpcd write failed to set fec_ready");
+ 			}
+-		} else if (link->fec_state == dc_link_fec_ready && !ready) {
++		} else if (link->fec_state == dc_link_fec_ready) {
+ 			fec_config = 0;
+ 			core_link_write_dpcd(link,
+ 					DP_FEC_CONFIGURATION,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3060-drm-amd-display-put-back-front-end-initialization-se.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3060-drm-amd-display-put-back-front-end-initialization-se.patch
new file mode 100644
index 00000000..d4a4d734
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3060-drm-amd-display-put-back-front-end-initialization-se.patch
@@ -0,0 +1,59 @@
+From d3ad897d071068a1378270eac70e7c849ab90914 Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Mon, 24 Jun 2019 18:18:58 -0400
+Subject: [PATCH 3060/4256] drm/amd/display: put back front end initialization
+ sequence
+
+[Why]
+Seamless boot optimization removed proper front end power off sequence.
+In driver disable enable case, this causes driver to power gate hubp
+and dpp while there is still memory fetching going on, this can cause
+invalid memory requests to be generated which will hang data fabric.
+
+[How]
+Put back proper front end power off sequence
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Acked-by: Tony Cheng <Tony.Cheng@amd.com>
+---
+ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 15 +--------------
+ 1 file changed, 1 insertion(+), 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 15ac6de3fd30..2b5614bea6c3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1194,16 +1194,7 @@ static void dcn10_init_hw(struct dc *dc)
+ 	 * everything down.
+ 	 */
+ 	if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
+-		for (i = 0; i < dc->res_pool->pipe_count; i++) {
+-			struct hubp *hubp = dc->res_pool->hubps[i];
+-			struct dpp *dpp = dc->res_pool->dpps[i];
+-
+-			hubp->funcs->hubp_init(hubp);
+-			dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
+-			plane_atomic_power_down(dc, dpp, hubp);
+-		}
+-
+-		apply_DEGVIDCN10_253_wa(dc);
++		dc->hwss.init_pipes(dc, dc->current_state);
+ 	}
+ 
+ 	for (i = 0; i < dc->res_pool->audio_count; i++) {
+@@ -1373,10 +1364,6 @@ static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
+ 	return result;
+ }
+ 
+-
+-
+-
+-
+ static bool
+ dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
+ 			       const struct dc_stream_state *stream)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3061-drm-amd-display-Optimize-gamma-calculations.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3061-drm-amd-display-Optimize-gamma-calculations.patch
new file mode 100644
index 00000000..61b986dd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3061-drm-amd-display-Optimize-gamma-calculations.patch
@@ -0,0 +1,333 @@
+From 9d796880fd196a54088a4ab097b441d5fadfba05 Mon Sep 17 00:00:00 2001
+From: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Date: Tue, 18 Jun 2019 17:38:43 -0400
+Subject: [PATCH 3061/4256] drm/amd/display: Optimize gamma calculations
+
+[Why&How]
+
+1. Stack usage is pretty high as fixed31_32 struct is 8 bytes and we
+have functions with >30 vars on the stack.
+
+2. Optimize gamma calculation by reducing number of calls to
+dc_fixpt_pow Our X points are divided into 32 regions wth 16 pts each.
+Each region is 2x the previous, meaning x[i] = 2*x[i-16] for i>=16.
+Using (2x)^gamma = 2^gamma * x^gamma, we can recursively compute powers
+of gamma, we just need first 16 pts to start it up. dc_fixpt_pow() is
+expensive, it computes x^y by doing exp(y*logx) Exp is done by Taylor
+series approximation, and log by Newton-like approximation that also
+uses exp internally. In short, it's significantly heavier than
+run-of-the-mill addition/subtraction/multiply.
+
+Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc_hw_types.h  |   1 -
+ .../amd/display/modules/color/color_gamma.c   | 163 +++++++++++-------
+ .../amd/display/modules/color/color_gamma.h   |   9 +
+ 3 files changed, 111 insertions(+), 62 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+index 22db5682aa6c..e9a6225f4720 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+@@ -482,7 +482,6 @@ struct dc_gamma {
+ 	 * is_logical_identity indicates the given gamma ramp regardless of type is identity.
+ 	 */
+ 	bool is_identity;
+-	bool is_logical_identity;
+ };
+ 
+ /* Used by both ipp amd opp functions*/
+diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+index 3f413fb9f2ce..294fe4f0cb67 100644
+--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
++++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+@@ -37,6 +37,33 @@ static struct hw_x_point coordinates_x[MAX_HW_POINTS + 2];
+ static struct fixed31_32 pq_table[MAX_HW_POINTS + 2];
+ static struct fixed31_32 de_pq_table[MAX_HW_POINTS + 2];
+ 
++// these are helpers for calculations to reduce stack usage
++// do not depend on these being preserved across calls
++static struct fixed31_32 scratch_1;
++static struct fixed31_32 scratch_2;
++static struct translate_from_linear_space_args scratch_gamma_args;
++
++/* Helper to optimize gamma calculation, only use in translate_from_linear, in
++ * particular the dc_fixpt_pow function which is very expensive
++ * The idea is that our regions for X points are exponential and currently they all use
++ * the same number of points (NUM_PTS_IN_REGION) and in each region every point
++ * is exactly 2x the one at the same index in the previous region. In other words
++ * X[i] = 2 * X[i-NUM_PTS_IN_REGION] for i>=16
++ * The other fact is that (2x)^gamma = 2^gamma * x^gamma
++ * So we compute and save x^gamma for the first 16 regions, and for every next region
++ * just multiply with 2^gamma which can be computed once, and save the result so we
++ * recursively compute all the values.
++ */
++static struct fixed31_32 pow_buffer[NUM_PTS_IN_REGION];
++static struct fixed31_32 gamma_of_2; // 2^gamma
++int pow_buffer_ptr = -1;
++
++static const int32_t gamma_numerator01[] = { 31308,	180000,	0};
++static const int32_t gamma_numerator02[] = { 12920,	4500,	0};
++static const int32_t gamma_numerator03[] = { 55,	99,	0};
++static const int32_t gamma_numerator04[] = { 55,	99,	0};
++static const int32_t gamma_numerator05[] = { 2400,	2200, 2200};
++
+ static bool pq_initialized; /* = false; */
+ static bool de_pq_initialized; /* = false; */
+ 
+@@ -248,11 +275,7 @@ enum gamma_type_index {
+ 
+ static void build_coefficients(struct gamma_coefficients *coefficients, enum gamma_type_index type)
+ {
+-	static const int32_t numerator01[] = { 31308,	180000,	0};
+-	static const int32_t numerator02[] = { 12920,	4500,	0};
+-	static const int32_t numerator03[] = { 55,		99,		0};
+-	static const int32_t numerator04[] = { 55,		99,		0};
+-	static const int32_t numerator05[] = { 2400,	2200, 2200};
++
+ 
+ 	uint32_t i = 0;
+ 	uint32_t index = 0;
+@@ -264,69 +287,74 @@ static void build_coefficients(struct gamma_coefficients *coefficients, enum gam
+ 
+ 	do {
+ 		coefficients->a0[i] = dc_fixpt_from_fraction(
+-			numerator01[index], 10000000);
++			gamma_numerator01[index], 10000000);
+ 		coefficients->a1[i] = dc_fixpt_from_fraction(
+-			numerator02[index], 1000);
++			gamma_numerator02[index], 1000);
+ 		coefficients->a2[i] = dc_fixpt_from_fraction(
+-			numerator03[index], 1000);
++			gamma_numerator03[index], 1000);
+ 		coefficients->a3[i] = dc_fixpt_from_fraction(
+-			numerator04[index], 1000);
++			gamma_numerator04[index], 1000);
+ 		coefficients->user_gamma[i] = dc_fixpt_from_fraction(
+-			numerator05[index], 1000);
++			gamma_numerator05[index], 1000);
+ 
+ 		++i;
+ 	} while (i != ARRAY_SIZE(coefficients->a0));
+ }
+ 
+ static struct fixed31_32 translate_from_linear_space(
+-	struct fixed31_32 arg,
+-	struct fixed31_32 a0,
+-	struct fixed31_32 a1,
+-	struct fixed31_32 a2,
+-	struct fixed31_32 a3,
+-	struct fixed31_32 gamma)
++		struct translate_from_linear_space_args *args)
+ {
+ 	const struct fixed31_32 one = dc_fixpt_from_int(1);
+ 
+-	if (dc_fixpt_lt(one, arg))
++	if (dc_fixpt_le(one, args->arg))
+ 		return one;
+ 
+-	if (dc_fixpt_le(arg, dc_fixpt_neg(a0)))
+-		return dc_fixpt_sub(
+-			a2,
+-			dc_fixpt_mul(
+-				dc_fixpt_add(
+-					one,
+-					a3),
+-				dc_fixpt_pow(
+-					dc_fixpt_neg(arg),
+-					dc_fixpt_recip(gamma))));
+-	else if (dc_fixpt_le(a0, arg))
+-		return dc_fixpt_sub(
+-			dc_fixpt_mul(
+-				dc_fixpt_add(
+-					one,
+-					a3),
+-				dc_fixpt_pow(
+-					arg,
+-					dc_fixpt_recip(gamma))),
+-			a2);
++	if (dc_fixpt_le(args->arg, dc_fixpt_neg(args->a0))) {
++		scratch_1 = dc_fixpt_add(one, args->a3);
++		scratch_2 = dc_fixpt_pow(
++				dc_fixpt_neg(args->arg),
++				dc_fixpt_recip(args->gamma));
++		scratch_1 = dc_fixpt_mul(scratch_1, scratch_2);
++		scratch_1 = dc_fixpt_sub(args->a2, scratch_1);
++
++		return scratch_1;
++	} else if (dc_fixpt_le(args->a0, args->arg)) {
++		if (pow_buffer_ptr == 0) {
++			gamma_of_2 = dc_fixpt_pow(dc_fixpt_from_int(2),
++					dc_fixpt_recip(args->gamma));
++		}
++		scratch_1 = dc_fixpt_add(one, args->a3);
++		if (pow_buffer_ptr < 16)
++			scratch_2 = dc_fixpt_pow(args->arg,
++					dc_fixpt_recip(args->gamma));
++		else
++			scratch_2 = dc_fixpt_mul(gamma_of_2,
++					pow_buffer[pow_buffer_ptr%16]);
++
++		pow_buffer[pow_buffer_ptr%16] = scratch_2;
++		pow_buffer_ptr++;
++
++		scratch_1 = dc_fixpt_mul(scratch_1, scratch_2);
++		scratch_1 = dc_fixpt_sub(scratch_1, args->a2);
++
++		return scratch_1;
++	}
+ 	else
+-		return dc_fixpt_mul(
+-			arg,
+-			a1);
++		return dc_fixpt_mul(args->arg, args->a1);
+ }
+ 
+ static struct fixed31_32 calculate_gamma22(struct fixed31_32 arg)
+ {
+ 	struct fixed31_32 gamma = dc_fixpt_from_fraction(22, 10);
+ 
+-	return translate_from_linear_space(arg,
+-			dc_fixpt_zero,
+-			dc_fixpt_zero,
+-			dc_fixpt_zero,
+-			dc_fixpt_zero,
+-			gamma);
++	scratch_gamma_args.arg = arg;
++	scratch_gamma_args.a0 = dc_fixpt_zero;
++	scratch_gamma_args.a1 = dc_fixpt_zero;
++	scratch_gamma_args.a2 = dc_fixpt_zero;
++	scratch_gamma_args.a3 = dc_fixpt_zero;
++	scratch_gamma_args.gamma = gamma;
++
++	return translate_from_linear_space(&scratch_gamma_args);
+ }
+ 
+ static struct fixed31_32 translate_to_linear_space(
+@@ -362,18 +390,19 @@ static struct fixed31_32 translate_to_linear_space(
+ 	return linear;
+ }
+ 
+-static inline struct fixed31_32 translate_from_linear_space_ex(
++static struct fixed31_32 translate_from_linear_space_ex(
+ 	struct fixed31_32 arg,
+ 	struct gamma_coefficients *coeff,
+ 	uint32_t color_index)
+ {
+-	return translate_from_linear_space(
+-		arg,
+-		coeff->a0[color_index],
+-		coeff->a1[color_index],
+-		coeff->a2[color_index],
+-		coeff->a3[color_index],
+-		coeff->user_gamma[color_index]);
++	scratch_gamma_args.arg = arg;
++	scratch_gamma_args.a0 = coeff->a0[color_index];
++	scratch_gamma_args.a1 = coeff->a1[color_index];
++	scratch_gamma_args.a2 = coeff->a2[color_index];
++	scratch_gamma_args.a3 = coeff->a3[color_index];
++	scratch_gamma_args.gamma = coeff->user_gamma[color_index];
++
++	return translate_from_linear_space(&scratch_gamma_args);
+ }
+ 
+ 
+@@ -712,24 +741,32 @@ static void build_regamma(struct pwl_float_data_ex *rgb_regamma,
+ {
+ 	uint32_t i;
+ 
+-	struct gamma_coefficients coeff;
++	struct gamma_coefficients *coeff;
+ 	struct pwl_float_data_ex *rgb = rgb_regamma;
+ 	const struct hw_x_point *coord_x = coordinate_x;
+ 
+-	build_coefficients(&coeff, type);
++	coeff = kvzalloc(sizeof(*coeff), GFP_KERNEL);
++	if (!coeff)
++		return;
+ 
+-	i = 0;
++	build_coefficients(coeff, type);
+ 
+-	while (i != hw_points_num + 1) {
++	memset(pow_buffer, 0, NUM_PTS_IN_REGION * sizeof(struct fixed31_32));
++	pow_buffer_ptr = 0; // see variable definition for more info
++	i = 0;
++	while (i <= hw_points_num) {
+ 		/*TODO use y vs r,g,b*/
+ 		rgb->r = translate_from_linear_space_ex(
+-			coord_x->x, &coeff, 0);
++			coord_x->x, coeff, 0);
+ 		rgb->g = rgb->r;
+ 		rgb->b = rgb->r;
+ 		++coord_x;
+ 		++rgb;
+ 		++i;
+ 	}
++	pow_buffer_ptr = -1; // reset back to no optimize
++
++	kfree(coeff);
+ }
+ 
+ static void hermite_spline_eetf(struct fixed31_32 input_x,
+@@ -859,6 +896,8 @@ static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
+ 	else
+ 		max_content = max_display;
+ 
++	if (!use_eetf)
++		pow_buffer_ptr = 0; // see var definition for more info
+ 	rgb += 32; // first 32 points have problems with fixed point, too small
+ 	coord_x += 32;
+ 	for (i = 32; i <= hw_points_num; i++) {
+@@ -897,6 +936,7 @@ static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
+ 		++coord_x;
+ 		++rgb;
+ 	}
++	pow_buffer_ptr = -1;
+ 
+ 	return true;
+ }
+@@ -1569,14 +1609,15 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
+ 			output_tf->tf == TRANSFER_FUNCTION_SRGB) {
+ 		if (ramp == NULL)
+ 			return true;
+-		if ((ramp->is_logical_identity) ||
++		if ((ramp->is_identity && ramp->type != GAMMA_CS_TFM_1D) ||
+ 				(!mapUserRamp && ramp->type == GAMMA_RGB_256))
+ 			return true;
+ 	}
+ 
+ 	output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
+ 
+-	if (ramp && (mapUserRamp || ramp->type != GAMMA_RGB_256)) {
++	if (ramp && ramp->type != GAMMA_CS_TFM_1D &&
++			(mapUserRamp || ramp->type != GAMMA_RGB_256)) {
+ 		rgb_user = kvcalloc(ramp->num_entries + _EXTRA_POINTS,
+ 			    sizeof(*rgb_user),
+ 			    GFP_KERNEL);
+diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
+index 369953fafadf..69cecd2ec251 100644
+--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
++++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
+@@ -82,6 +82,15 @@ struct freesync_hdr_tf_params {
+ 	unsigned int skip_tm; // skip tm
+ };
+ 
++struct translate_from_linear_space_args {
++	struct fixed31_32 arg;
++	struct fixed31_32 a0;
++	struct fixed31_32 a1;
++	struct fixed31_32 a2;
++	struct fixed31_32 a3;
++	struct fixed31_32 gamma;
++};
++
+ void setup_x_points_distribution(void);
+ void precompute_pq(void);
+ void precompute_de_pq(void);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3062-drm-amd-display-Clear-FEC_READY-shadow-register-if-D.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3062-drm-amd-display-Clear-FEC_READY-shadow-register-if-D.patch
new file mode 100644
index 00000000..42de4087
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3062-drm-amd-display-Clear-FEC_READY-shadow-register-if-D.patch
@@ -0,0 +1,36 @@
+From 533cd145e9b688d42573bf0ea16e51e1c20274b6 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Tue, 25 Jun 2019 17:19:25 -0400
+Subject: [PATCH 3062/4256] drm/amd/display: Clear FEC_READY shadow register if
+ DPCD write fails
+
+[why]
+As a fail-safe, in case 'set FEC_READY' DPCD write fails, a HW shadow
+register should be cleared and the internal FEC stat should be set to
+'not ready'. This is to make sure HW settings will be consistent with
+FEC_READY state on the RX.
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
+Acked-by: Chris Park <Chris.Park@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 5c8e3318239c..b512fecae061 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -3174,6 +3174,8 @@ void dp_set_fec_ready(struct dc_link *link, bool ready)
+ 				link_enc->funcs->fec_set_ready(link_enc, true);
+ 				link->fec_state = dc_link_fec_ready;
+ 			} else {
++				link->link_enc->funcs->fec_set_ready(link->link_enc, false);
++				link->fec_state = dc_link_fec_not_ready;
+ 				dm_error("dpcd write failed to set fec_ready");
+ 			}
+ 		} else if (link->fec_state == dc_link_fec_ready) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3063-drm-amd-display-Add-debug-option-to-disable-timing-s.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3063-drm-amd-display-Add-debug-option-to-disable-timing-s.patch
new file mode 100644
index 00000000..7b7fc4fd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3063-drm-amd-display-Add-debug-option-to-disable-timing-s.patch
@@ -0,0 +1,48 @@
+From d8e2154aba6dc991ae2852562bca2202dcc56c7b Mon Sep 17 00:00:00 2001
+From: Joshua Aberback <joshua.aberback@amd.com>
+Date: Fri, 17 May 2019 14:43:10 -0400
+Subject: [PATCH 3063/4256] drm/amd/display: Add debug option to disable timing
+ sync
+
+[Why]
+We want a debug option to disable timing sync for testing.
+
+[How]
+New dc debug option that must be false to call program_timing_sync
+
+Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dc.h      | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index c1bda186fd40..2503e3308b42 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1072,7 +1072,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ 	if (result != DC_OK)
+ 		return result;
+ 
+-	if (context->stream_count > 1) {
++	if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
+ 		enable_timing_multisync(dc, context);
+ 		program_timing_sync(dc, context);
+ 	}
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 441d0c376a9f..6d69fd12e422 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -381,6 +381,7 @@ struct dc_debug_options {
+ 	 * watermarks are not affected.
+ 	 */
+ 	unsigned int force_min_dcfclk_mhz;
++	bool disable_timing_sync;
+ };
+ 
+ struct dc_debug_data {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3064-drm-amd-display-Add-MPC-3DLUT-resource-management.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3064-drm-amd-display-Add-MPC-3DLUT-resource-management.patch
new file mode 100644
index 00000000..f67b6741
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3064-drm-amd-display-Add-MPC-3DLUT-resource-management.patch
@@ -0,0 +1,98 @@
+From abbab24a6e8856277dc8d53c2de73a3aa6e279b9 Mon Sep 17 00:00:00 2001
+From: Vitaly Prosyak <vitaly.prosyak@amd.com>
+Date: Fri, 21 Jun 2019 10:13:16 -0500
+Subject: [PATCH 3064/4256] drm/amd/display: Add MPC 3DLUT resource management
+
+[Why & How]
+Number of 3DLUT's in MPC are not equal to number of pipes.
+Resource management is required.
+Activate on FPGA entire tm solution  which includes
+the following :hdr multiplier, shaper, 3dlut.
+
+Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Gary Kattan <Gary.Kattan@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_surface.c |  3 +--
+ drivers/gpu/drm/amd/display/dc/dc.h              | 16 +++++++++++++++-
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c   |  4 ++--
+ 3 files changed, 18 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+index 394a87981614..9184f877f537 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+@@ -58,7 +58,6 @@ static void construct(struct dc_context *ctx, struct dc_plane_state *plane_state
+ 	plane_state->lut3d_func = dc_create_3dlut_func();
+ 	if (plane_state->lut3d_func != NULL) {
+ 		plane_state->lut3d_func->ctx = ctx;
+-		plane_state->lut3d_func->initialized = false;
+ 	}
+ 	plane_state->blend_tf = dc_create_transfer_func();
+ 	if (plane_state->blend_tf != NULL) {
+@@ -277,7 +276,7 @@ struct dc_3dlut *dc_create_3dlut_func(void)
+ 		goto alloc_fail;
+ 
+ 	kref_init(&lut->refcount);
+-	lut->initialized = false;
++	lut->state.raw = 0;
+ 
+ 	return lut;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 6d69fd12e422..d0ff9c5bf332 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -630,12 +630,26 @@ struct dc_transfer_func {
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 
++union dc_3dlut_state {
++	struct {
++		uint32_t initialized:1;		/*if 3dlut is went through color module for initialization */
++		uint32_t rmu_idx_valid:1;	/*if mux settings are valid*/
++		uint32_t rmu_mux_num:3;		/*index of mux to use*/
++		uint32_t mpc_rmu0_mux:4;	/*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
++		uint32_t mpc_rmu1_mux:4;
++		uint32_t mpc_rmu2_mux:4;
++		uint32_t reserved:15;
++	} bits;
++	uint32_t raw;
++};
++
+ 
+ struct dc_3dlut {
+ 	struct kref refcount;
+ 	struct tetrahedral_params lut_3d;
+ 	uint32_t hdr_multiplier;
+-	bool initialized;
++	bool initialized; /*remove after diag fix*/
++	union dc_3dlut_state state;
+ 	struct dc_context *ctx;
+ };
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index b089ba1c7614..23cbc72f71c8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -929,14 +929,14 @@ static bool dcn20_set_shaper_3dlut(
+ 
+ 	result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
+ 	if (plane_state->lut3d_func &&
+-		plane_state->lut3d_func->initialized == true)
++		plane_state->lut3d_func->state.bits.initialized == 1)
+ 		result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
+ 								&plane_state->lut3d_func->lut_3d);
+ 	else
+ 		result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
+ 
+ 	if (plane_state->lut3d_func &&
+-		plane_state->lut3d_func->initialized == true &&
++		plane_state->lut3d_func->state.bits.initialized == 1 &&
+ 		plane_state->lut3d_func->hdr_multiplier != 0)
+ 		dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base,
+ 				plane_state->lut3d_func->hdr_multiplier);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3065-drm-amd-display-Add-CM_BYPASS-via-debug-option.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3065-drm-amd-display-Add-CM_BYPASS-via-debug-option.patch
new file mode 100644
index 00000000..3e81a0e3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3065-drm-amd-display-Add-CM_BYPASS-via-debug-option.patch
@@ -0,0 +1,115 @@
+From 604835a3a5651ab05a65444588872dc2f1c57aa2 Mon Sep 17 00:00:00 2001
+From: Qingqing Zhuo <qingqing.zhuo@amd.com>
+Date: Thu, 27 Jun 2019 19:17:23 -0400
+Subject: [PATCH 3065/4256] drm/amd/display: Add CM_BYPASS via debug option
+
+[Why]
+bypass CM block and MPC ogam for debug or triage use.
+
+[How]
+create a new flag cm_bypass_mode, which will set both CM_CONTROL
+and MPCC_OGAM_MODE to bypass when set to 1.
+
+Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h                 |  3 +++
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c |  7 ++++++-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c    | 11 +++++++++++
+ drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h         |  1 +
+ drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h         |  1 +
+ 5 files changed, 22 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index d0ff9c5bf332..6e6dc24e443b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -382,6 +382,9 @@ struct dc_debug_options {
+ 	 */
+ 	unsigned int force_min_dcfclk_mhz;
+ 	bool disable_timing_sync;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++	bool cm_in_bypass;
++#endif
+ };
+ 
+ struct dc_debug_data {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
+index e28b8e7bedf5..2d112c316424 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
+@@ -52,7 +52,12 @@ static void dpp2_enable_cm_block(
+ {
+ 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
+ 
+-	REG_UPDATE(CM_CONTROL, CM_BYPASS, 0);
++	unsigned int cm_bypass_mode = 0;
++	//Temp, put CM in bypass mode
++	if (dpp_base->ctx->dc->debug.cm_in_bypass)
++		cm_bypass_mode = 1;
++
++	REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode);
+ }
+ 
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+index 240749e4cf83..f4d3008e5efa 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+@@ -368,6 +368,11 @@ void apply_DEDCN20_305_wa(
+ {
+ 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
+ 
++	if (mpc->ctx->dc->debug.cm_in_bypass) {
++		REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
++		return;
++	}
++
+ 	if (mpc->ctx->dc->work_arounds.dedcn20_305_wa == false) {
+ 		/*hw fixed in new review*/
+ 		return;
+@@ -390,10 +395,16 @@ void mpc2_set_output_gamma(
+ 	enum dc_lut_mode next_mode;
+ 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
+ 
++	if (mpc->ctx->dc->debug.cm_in_bypass) {
++		REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
++		return;
++	}
++
+ 	if (params == NULL) {
+ 		REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
+ 		return;
+ 	}
++
+ 	current_mode = mpc20_get_ogam_current(mpc, mpcc_id);
+ 	if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
+ 		next_mode = LUT_RAM_B;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+index 60c671fcf186..9b69a06ab46f 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+@@ -42,6 +42,7 @@ struct dpp {
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	struct pwl_params shaper_params;
++	bool cm_bypass_mode;
+ #endif
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+index 45b94e319cd4..9f00289bda78 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+@@ -128,6 +128,7 @@ struct mpc {
+ 	struct mpcc mpcc_array[MAX_MPCC];
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	struct pwl_params blender_params;
++	bool cm_bypass_mode;
+ #endif
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3066-drm-amd-display-Add-DIG_CLOCK_PATTERN-register.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3066-drm-amd-display-Add-DIG_CLOCK_PATTERN-register.patch
new file mode 100644
index 00000000..16d3e8b9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3066-drm-amd-display-Add-DIG_CLOCK_PATTERN-register.patch
@@ -0,0 +1,59 @@
+From 164d9d908d610e980513d9bcd2dac1b760575aae Mon Sep 17 00:00:00 2001
+From: Nevenko Stupar <Nevenko.Stupar@amd.com>
+Date: Fri, 28 Jun 2019 12:12:13 -0400
+Subject: [PATCH 3066/4256] drm/amd/display: Add DIG_CLOCK_PATTERN register
+
+Add this register for future use
+
+Signed-off-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
+Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/dcn10/dcn10_stream_encoder.h    | 10 +++++++---
+ 1 file changed, 7 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+index ab0ead3c3f46..f585e7b620cc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+@@ -89,7 +89,8 @@
+ 	SRI(DP_VID_STREAM_CNTL, DP, id), \
+ 	SRI(DP_VID_TIMING, DP, id), \
+ 	SRI(DP_SEC_AUD_N, DP, id), \
+-	SRI(DP_SEC_TIMESTAMP, DP, id)
++	SRI(DP_SEC_TIMESTAMP, DP, id), \
++	SRI(DIG_CLOCK_PATTERN, DIG, id)
+ 
+ #define SE_DCN_REG_LIST(id)\
+ 	SE_COMMON_DCN_REG_LIST(id)
+@@ -170,6 +171,7 @@ struct dcn10_stream_enc_registers {
+ 	uint32_t HDMI_METADATA_PACKET_CONTROL;
+ 	uint32_t DP_SEC_FRAMING4;
+ #endif
++	uint32_t DIG_CLOCK_PATTERN;
+ };
+ 
+ 
+@@ -298,7 +300,8 @@ struct dcn10_stream_enc_registers {
+ 	SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
+ 	SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
+ 	SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
+-	SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh)
++	SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh),\
++	SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh)
+ 
+ #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
+ 	SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
+@@ -460,7 +463,8 @@ struct dcn10_stream_enc_registers {
+ 	type HDMI_DB_DISABLE;\
+ 	type DP_VID_N_MUL;\
+ 	type DP_VID_M_DOUBLE_VALUE_EN;\
+-	type DIG_SOURCE_SELECT
++	type DIG_SOURCE_SELECT;\
++	type DIG_CLOCK_PATTERN
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define SE_REG_FIELD_LIST_DCN2_0(type) \
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3067-drm-amd-display-Cache-the-use_pitch_c-conditional.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3067-drm-amd-display-Cache-the-use_pitch_c-conditional.patch
new file mode 100644
index 00000000..2fad8881
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3067-drm-amd-display-Cache-the-use_pitch_c-conditional.patch
@@ -0,0 +1,47 @@
+From 283a2a8ff3094db6016321baabc3e49ff8bac8c5 Mon Sep 17 00:00:00 2001
+From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Date: Wed, 19 Jun 2019 17:33:02 -0400
+Subject: [PATCH 3067/4256] drm/amd/display: Cache the use_pitch_c conditional
+
+For clarity, save the use_pitch_c logic to a bool
+
+Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Reviewed-by: Eric Bernstein <eric.bernstein@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+index 02e8c0c6a233..a167f867cb72 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+@@ -402,11 +402,14 @@ void hubp2_program_size(
+ {
+ 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+ 	uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c;
++	bool use_pitch_c = false;
+ 
+ 	/* Program data and meta surface pitch (calculation from addrlib)
+ 	 * 444 or 420 luma
+ 	 */
+-	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) {
++	use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
++		&& format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END;
++	if (use_pitch_c) {
+ 		ASSERT(plane_size->video.chroma_pitch != 0);
+ 		/* Chroma pitch zero can cause system hang! */
+ 
+@@ -429,7 +432,8 @@ void hubp2_program_size(
+ 	REG_UPDATE_2(DCSURF_SURFACE_PITCH,
+ 			PITCH, pitch, META_PITCH, meta_pitch);
+ 
+-	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
++	use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN;
++	if (use_pitch_c)
+ 		REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
+ 			PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3068-drm-amd-display-Fixes-for-some-MPO-cases.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3068-drm-amd-display-Fixes-for-some-MPO-cases.patch
new file mode 100644
index 00000000..cbb2fed6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3068-drm-amd-display-Fixes-for-some-MPO-cases.patch
@@ -0,0 +1,50 @@
+From 508f257fdd740ab6c89188d94de3f0fd4435f2b9 Mon Sep 17 00:00:00 2001
+From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Date: Wed, 26 Jun 2019 14:52:46 -0400
+Subject: [PATCH 3068/4256] drm/amd/display: Fixes for some MPO cases
+
+[Why]
+Alpha could be improperly applied (only affecting half the
+frame) for some source pixel formats.
+
+[How]
+Change how alpha is enabled in MPC/DPP LB and change the
+bottom plane blend mode in MPC.
+
+Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   | 2 +-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+index 0bca011ed7c9..4f7a10390c57 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+@@ -211,7 +211,7 @@ struct mpcc *mpc1_insert_plane(
+ 	} else {
+ 		new_mpcc->mpcc_bot = NULL;
+ 		REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
+-		REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH);
++		REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_ONLY);
+ 	}
+ 	REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id);
+ 	REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 23cbc72f71c8..432156b52602 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1840,7 +1840,7 @@ static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ 	struct mpcc_blnd_cfg blnd_cfg = { {0} };
+-	bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
++	bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
+ 	int mpcc_id;
+ 	struct mpcc *new_mpcc;
+ 	struct mpc *mpc = dc->res_pool->mpc;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3069-drm-amd-display-3.2.41.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3069-drm-amd-display-3.2.41.patch
new file mode 100644
index 00000000..ff30f8c0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3069-drm-amd-display-3.2.41.patch
@@ -0,0 +1,27 @@
+From 324386398eba9bd1eff399b50f881f275876c277 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Mon, 1 Jul 2019 23:15:42 -0400
+Subject: [PATCH 3069/4256] drm/amd/display: 3.2.41
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 6e6dc24e443b..bd4c32afd603 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -42,7 +42,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.40"
++#define DC_VER "3.2.41"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3070-drm-amd-display-Hook-up-calls-to-do-stereo-mux-and-d.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3070-drm-amd-display-Hook-up-calls-to-do-stereo-mux-and-d.patch
new file mode 100644
index 00000000..a6432523
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3070-drm-amd-display-Hook-up-calls-to-do-stereo-mux-and-d.patch
@@ -0,0 +1,322 @@
+From f9eb6fef4679f546c2ad208ba22d00d782d6a3fe Mon Sep 17 00:00:00 2001
+From: Murton Liu <murton.liu@amd.com>
+Date: Tue, 25 Jun 2019 11:15:09 -0400
+Subject: [PATCH 3070/4256] drm/amd/display: Hook up calls to do stereo mux and
+ dig programming to stereo control interface
+
+[Why]
+Implementation of stereo mux register is complete, but unused. Need to
+call functions to write relevant configs.
+
+[How]
+Add function to write stereo config for enable/disable case and call in
+stereo control interface.
+
+Signed-off-by: Murton Liu <murton.liu@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c      | 47 ++++++++++++
+ drivers/gpu/drm/amd/display/dc/dc.h           |  3 +
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  7 ++
+ .../display/dc/gpio/dcn10/hw_factory_dcn10.c  | 42 ++++++++++-
+ .../drm/amd/display/dc/gpio/gpio_service.c    | 72 +++++++++++++++++++
+ .../display/include/gpio_service_interface.h  | 18 ++++-
+ 6 files changed, 186 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 2503e3308b42..7142651ab640 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1246,6 +1246,53 @@ void dc_release_state(struct dc_state *context)
+ 	kref_put(&context->refcount, dc_state_free);
+ }
+ 
++bool dc_set_generic_gpio_for_stereo(bool enable,
++		struct gpio_service *gpio_service)
++{
++	enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
++	struct gpio_pin_info pin_info;
++	struct gpio *generic;
++	struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
++			   GFP_KERNEL);
++
++	pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
++
++	if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
++		kfree(config);
++		return false;
++	} else {
++		generic = dal_gpio_service_create_generic_mux(
++			gpio_service,
++			pin_info.offset,
++			pin_info.mask);
++	}
++
++	if (!generic) {
++		kfree(config);
++		return false;
++	}
++
++	gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
++
++	config->enable_output_from_mux = enable;
++	config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
++
++	if (gpio_result == GPIO_RESULT_OK)
++		gpio_result = dal_mux_setup_config(generic, config);
++
++	if (gpio_result == GPIO_RESULT_OK) {
++		dal_gpio_close(generic);
++		dal_gpio_destroy_generic_mux(&generic);
++		kfree(config);
++		return true;
++	} else {
++		dal_gpio_close(generic);
++		dal_gpio_destroy_generic_mux(&generic);
++		kfree(config);
++		return false;
++	}
++}
++
+ static bool is_surface_in_context(
+ 		const struct dc_state *context,
+ 		const struct dc_plane_state *plane_state)
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index bd4c32afd603..783c37977e73 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -866,6 +866,9 @@ enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *pla
+ 
+ void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
+ 
++bool dc_set_generic_gpio_for_stereo(bool enable,
++		struct gpio_service *gpio_service);
++
+ /*
+  * fast_validate: we return after determining if we can support the new state,
+  * but before we populate the programming info
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 2b5614bea6c3..4ac9056f79d1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2690,6 +2690,13 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
+ 
+ 	dcn10_config_stereo_parameters(stream, &flags);
+ 
++	if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
++		if (!dc_set_generic_gpio_for_stereo(true, dc->ctx->gpio_service))
++			dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);
++	} else {
++		dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);
++	}
++
+ 	pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
+ 		pipe_ctx->stream_res.opp,
+ 		flags.PROGRAM_STEREO == 1 ? true:false,
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
+index 32aa47a04a0d..5711f30cf848 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
+@@ -31,6 +31,7 @@
+ #include "../hw_gpio.h"
+ #include "../hw_ddc.h"
+ #include "../hw_hpd.h"
++#include "../hw_generic.h"
+ 
+ #include "hw_factory_dcn10.h"
+ 
+@@ -121,6 +122,42 @@ static const struct ddc_sh_mask ddc_mask = {
+ 		DDC_MASK_SH_LIST(_MASK)
+ };
+ 
++#include "../generic_regs.h"
++
++/* set field name */
++#define SF_GENERIC(reg_name, field_name, post_fix)\
++	.field_name = reg_name ## __ ## field_name ## post_fix
++
++#define generic_regs(id) \
++{\
++	GENERIC_REG_LIST(id)\
++}
++
++static const struct generic_registers generic_regs[] = {
++	generic_regs(A),
++	generic_regs(B),
++};
++
++static const struct generic_sh_mask generic_shift[] = {
++	GENERIC_MASK_SH_LIST(__SHIFT, A),
++	GENERIC_MASK_SH_LIST(__SHIFT, B),
++};
++
++static const struct generic_sh_mask generic_mask[] = {
++	GENERIC_MASK_SH_LIST(_MASK, A),
++	GENERIC_MASK_SH_LIST(_MASK, B),
++};
++
++static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
++{
++	struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
++
++	generic->regs = &generic_regs[en];
++	generic->shifts = &generic_shift[en];
++	generic->masks = &generic_mask[en];
++	generic->base.regs = &generic_regs[en].gpio;
++}
++
+ static void define_ddc_registers(
+ 		struct hw_gpio_pin *pin,
+ 		uint32_t en)
+@@ -161,12 +198,13 @@ static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
+ static const struct hw_factory_funcs funcs = {
+ 	.create_ddc_data = dal_hw_ddc_create,
+ 	.create_ddc_clock = dal_hw_ddc_create,
+-	.create_generic = NULL,
++	.create_generic = dal_hw_generic_create,
+ 	.create_hpd = dal_hw_hpd_create,
+ 	.create_sync = NULL,
+ 	.create_gsl = NULL,
+ 	.define_hpd_registers = define_hpd_registers,
+-	.define_ddc_registers = define_ddc_registers
++	.define_ddc_registers = define_ddc_registers,
++	.define_generic_registers = define_generic_registers
+ };
+ /*
+  * dal_hw_factory_dcn10_init
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
+index 3c63a3c04dbb..937478bac796 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
+@@ -139,6 +139,62 @@ struct gpio *dal_gpio_service_create_irq(
+ 	return dal_gpio_create_irq(service, id, en);
+ }
+ 
++struct gpio *dal_gpio_service_create_generic_mux(
++	struct gpio_service *service,
++	uint32_t offset,
++	uint32_t mask)
++{
++	enum gpio_id id;
++	uint32_t en;
++	struct gpio *generic;
++
++	if (mask == 1)
++		en = GPIO_GENERIC_A;
++	else if (mask == 0x00000100L)
++		en = GPIO_GENERIC_B;
++	else
++		return NULL;
++
++	id = GPIO_ID_GENERIC;
++
++	generic = dal_gpio_create(
++		service, id, en, GPIO_PIN_OUTPUT_STATE_DEFAULT);
++
++	return generic;
++}
++
++void dal_gpio_destroy_generic_mux(
++	struct gpio **mux)
++{
++	if (!mux || !*mux) {
++		ASSERT_CRITICAL(false);
++		return;
++	}
++
++	dal_gpio_close(*mux);
++	dal_gpio_destroy(mux);
++	kfree(*mux);
++
++	*mux = NULL;
++}
++
++struct gpio_pin_info dal_gpio_get_generic_pin_info(
++	struct gpio_service *service,
++	enum gpio_id id,
++	uint32_t en)
++{
++	struct gpio_pin_info pin;
++
++	if (service->translate.funcs->id_to_offset) {
++		service->translate.funcs->id_to_offset(id, en, &pin);
++	} else {
++		pin.mask = 0xFFFFFFFF;
++		pin.offset = 0xFFFFFFFF;
++	}
++
++	return pin;
++}
++
+ void dal_gpio_service_destroy(
+ 	struct gpio_service **ptr)
+ {
+@@ -163,6 +219,21 @@ void dal_gpio_service_destroy(
+ 	*ptr = NULL;
+ }
+ 
++enum gpio_result dal_mux_setup_config(
++	struct gpio *mux,
++	struct gpio_generic_mux_config *config)
++{
++	struct gpio_config_data config_data;
++
++	if (!config)
++		return GPIO_RESULT_INVALID_DATA;
++
++	config_data.config.generic_mux = *config;
++	config_data.type = GPIO_CONFIG_TYPE_GENERIC_MUX;
++
++	return dal_gpio_set_config(mux, &config_data);
++}
++
+ /*
+  * @brief
+  * Private API.
+@@ -253,6 +324,7 @@ enum gpio_result dal_gpio_service_open(
+ 	case GPIO_ID_GENERIC:
+ 		pin = service->factory.funcs->create_generic(
+ 			service->ctx, id, en);
++		service->factory.funcs->define_generic_registers(pin, en);
+ 	break;
+ 	case GPIO_ID_HPD:
+ 		pin = service->factory.funcs->create_hpd(
+diff --git a/drivers/gpu/drm/amd/display/include/gpio_service_interface.h b/drivers/gpu/drm/amd/display/include/gpio_service_interface.h
+index f40259bade40..9c55d247227e 100644
+--- a/drivers/gpu/drm/amd/display/include/gpio_service_interface.h
++++ b/drivers/gpu/drm/amd/display/include/gpio_service_interface.h
+@@ -51,13 +51,29 @@ struct gpio *dal_gpio_service_create_irq(
+ 	uint32_t offset,
+ 	uint32_t mask);
+ 
++struct gpio *dal_gpio_service_create_generic_mux(
++	struct gpio_service *service,
++	uint32_t offset,
++	uint32_t mask);
++
++void dal_gpio_destroy_generic_mux(
++	struct gpio **mux);
++
++enum gpio_result dal_mux_setup_config(
++	struct gpio *mux,
++	struct gpio_generic_mux_config *config);
++
++struct gpio_pin_info dal_gpio_get_generic_pin_info(
++	struct gpio_service *service,
++	enum gpio_id id,
++	uint32_t en);
++
+ struct ddc *dal_gpio_create_ddc(
+ 	struct gpio_service *service,
+ 	uint32_t offset,
+ 	uint32_t mask,
+ 	struct gpio_ddc_hw_info *info);
+ 
+-
+ void dal_gpio_destroy_ddc(
+ 	struct ddc **ddc);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3071-drm-amd-display-allocate-4-ddc-engines-for-RV2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3071-drm-amd-display-allocate-4-ddc-engines-for-RV2.patch
new file mode 100644
index 00000000..4eb68339
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3071-drm-amd-display-allocate-4-ddc-engines-for-RV2.patch
@@ -0,0 +1,35 @@
+From cb8971ff7026f06f18ea4ca19ad1f9ee040ea0cd Mon Sep 17 00:00:00 2001
+From: Derek Lai <Derek.Lai@amd.com>
+Date: Tue, 2 Jul 2019 17:50:41 +0800
+Subject: [PATCH 3071/4256] drm/amd/display: allocate 4 ddc engines for RV2
+
+[Why]
+Driver will create 0, 1, and 2 ddc engines for RV2,
+but some platforms used 0, 1, and 3.
+
+[How]
+Still allocate 4 ddc engines for RV2.
+
+Signed-off-by: Derek Lai <Derek.Lai@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index 29fd3cb9422b..2a01645c4bfd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -506,7 +506,7 @@ static const struct resource_caps rv2_res_cap = {
+ 		.num_audio = 3,
+ 		.num_stream_encoder = 3,
+ 		.num_pll = 3,
+-		.num_ddc = 3,
++		.num_ddc = 4,
+ };
+ 
+ static const struct dc_plane_cap plane_cap = {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3072-drm-amd-display-add-set-and-get-clock-for-testing-pu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3072-drm-amd-display-add-set-and-get-clock-for-testing-pu.patch
new file mode 100644
index 00000000..23d8b586
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3072-drm-amd-display-add-set-and-get-clock-for-testing-pu.patch
@@ -0,0 +1,295 @@
+From 62559da1aa340518a418b6797943df3dfcfdf697 Mon Sep 17 00:00:00 2001
+From: Charlene Liu <charlene.liu@amd.com>
+Date: Thu, 27 Jun 2019 18:16:21 -0400
+Subject: [PATCH 3072/4256] drm/amd/display: add set and get clock for testing
+ purposes
+
+add dc_set_clock
+add dc_get_clock
+
+this is for testing and diagnostics to get/set DPPCLK and DISPCLK.
+
+Signed-off-by: Charlene Liu <charlene.liu@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  | 23 +++++++-
+ .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h  |  5 ++
+ drivers/gpu/drm/amd/display/dc/core/dc.c      | 11 ++++
+ drivers/gpu/drm/amd/display/dc/dc.h           |  5 ++
+ drivers/gpu/drm/amd/display/dc/dc_types.h     | 13 +++++
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 53 ++++++++++++++++++-
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c |  5 ++
+ .../gpu/drm/amd/display/dc/inc/core_status.h  |  3 ++
+ .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   |  7 +++
+ .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  9 ++++
+ 10 files changed, 132 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index e9a7a7af11df..9a873e2b3736 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -316,11 +316,32 @@ void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
+ 	}
+ }
+ 
++void dcn2_get_clock(struct clk_mgr *clk_mgr,
++		struct dc_state *context,
++			enum dc_clock_type clock_type,
++			struct dc_clock_config *clock_cfg)
++{
++
++	if (clock_type == DC_CLOCK_TYPE_DISPCLK) {
++		clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
++		clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz;
++		clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz;
++		clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;
++	}
++	if (clock_type == DC_CLOCK_TYPE_DPPCLK) {
++		clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
++		clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz;
++		clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz;
++		clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;
++	}
++}
++
+ static struct clk_mgr_funcs dcn2_funcs = {
+ 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
+ 	.update_clocks = dcn2_update_clocks,
+ 	.init_clocks = dcn2_init_clocks,
+-	.enable_pme_wa = dcn2_enable_pme_wa
++	.enable_pme_wa = dcn2_enable_pme_wa,
++	.get_clock = dcn2_get_clock,
+ };
+ 
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
+index 5661a5a89847..ac31a9787305 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
+@@ -45,4 +45,9 @@ void dcn20_clk_mgr_construct(struct dc_context *ctx,
+ 
+ uint32_t dentist_get_did_from_divider(int divider);
+ 
++void dcn2_get_clock(struct clk_mgr *clk_mgr,
++		struct dc_state *context,
++			enum dc_clock_type clock_type,
++			struct dc_clock_config *clock_cfg);
++
+ #endif //__DCN20_CLK_MGR_H__
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 7142651ab640..a05b47c667a8 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -2440,3 +2440,14 @@ void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx
+ 	info->fClock					= (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
+ 	info->phyClock					= (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
+ }
++enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
++{
++	if (dc->hwss.set_clock)
++		return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
++	return DC_ERROR_UNEXPECTED;
++}
++void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
++{
++	if (dc->hwss.get_clock)
++		dc->hwss.get_clock(dc, clock_type, clock_cfg);
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 783c37977e73..79827884cd80 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -255,7 +255,10 @@ enum wm_report_mode {
+ struct dc_clocks {
+ 	int dispclk_khz;
+ 	int max_supported_dppclk_khz;
++	int max_supported_dispclk_khz;
+ 	int dppclk_khz;
++	int bw_dppclk_khz; /*a copy of dppclk_khz*/
++	int bw_dispclk_khz;
+ 	int dcfclk_khz;
+ 	int socclk_khz;
+ 	int dcfclk_deep_sleep_khz;
+@@ -1055,6 +1058,8 @@ unsigned int dc_get_target_backlight_pwm(struct dc *dc);
+ 
+ bool dc_is_dmcu_initialized(struct dc *dc);
+ 
++enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
++void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
+ #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
+ /*******************************************************************************
+  * DSC Interfaces
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
+index 4279b355c1f4..d93758e919a1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
+@@ -735,6 +735,19 @@ struct AsicStateEx {
+ 	unsigned int phyClock;
+ };
+ 
++
++enum dc_clock_type {
++	DC_CLOCK_TYPE_DISPCLK = 0,
++	DC_CLOCK_TYPE_DPPCLK        = 1,
++};
++
++struct dc_clock_config {
++	uint32_t max_clock_khz;
++	uint32_t min_clock_khz;
++	uint32_t bw_requirequired_clock_khz;
++	uint32_t current_clock_khz;/*current clock in use*/
++};
++
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* DSC DPCD capabilities */
+ union dsc_slice_caps1 {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 4ac9056f79d1..5ded8b0ed93a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -3067,6 +3067,56 @@ static void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
+ 				sdp_message_size);
+ 	}
+ }
++static enum dc_status dcn10_set_clock(struct dc *dc,
++			enum dc_clock_type clock_type,
++			uint32_t clk_khz,
++			uint32_t stepping)
++{
++	struct dc_state *context = dc->current_state;
++	struct dc_clock_config clock_cfg = {0};
++	struct dc_clocks *current_clocks = &context->bw_ctx.bw.dcn.clk;
++
++	if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
++				dc->clk_mgr->funcs->get_clock(dc->clk_mgr,
++						context, clock_type, &clock_cfg);
++
++	if (!dc->clk_mgr->funcs->get_clock)
++		return DC_FAIL_UNSUPPORTED_1;
++
++	if (clk_khz > clock_cfg.max_clock_khz)
++		return DC_FAIL_CLK_EXCEED_MAX;
++
++	if (clk_khz < clock_cfg.min_clock_khz)
++		return DC_FAIL_CLK_BELOW_MIN;
++
++	if (clk_khz < clock_cfg.bw_requirequired_clock_khz)
++		return DC_FAIL_CLK_BELOW_CFG_REQUIRED;
++
++	/*update internal request clock for update clock use*/
++	if (clock_type == DC_CLOCK_TYPE_DISPCLK)
++		current_clocks->dispclk_khz = clk_khz;
++	else if (clock_type == DC_CLOCK_TYPE_DPPCLK)
++		current_clocks->dppclk_khz = clk_khz;
++	else
++		return DC_ERROR_UNEXPECTED;
++
++	if (dc->clk_mgr && dc->clk_mgr->funcs->update_clocks)
++				dc->clk_mgr->funcs->update_clocks(dc->clk_mgr,
++				context, true);
++	return DC_OK;
++
++}
++
++static void dcn10_get_clock(struct dc *dc,
++			enum dc_clock_type clock_type,
++			struct dc_clock_config *clock_cfg)
++{
++	struct dc_state *context = dc->current_state;
++
++	if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
++				dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);
++
++}
+ 
+ static const struct hw_sequencer_funcs dcn10_funcs = {
+ 	.program_gamut_remap = program_gamut_remap,
+@@ -3121,7 +3171,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
+ 	.enable_stream_gating = NULL,
+ 	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
+ 	.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
+-	.did_underflow_occur = dcn10_did_underflow_occur
++	.set_clock = dcn10_set_clock,
++	.get_clock = dcn10_get_clock,
+ };
+ 
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 022d0f38723b..158743b165e8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2396,6 +2396,11 @@ void dcn20_calculate_dlg_params(
+ 		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
+ 		pipe_idx++;
+ 	}
++	/*save a original dppclock copy*/
++	context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
++	context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
++	context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz*1000;
++	context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz*1000;
+ 
+ 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+ 		bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+index 0a094d7c9380..fd39e2abe2ed 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+@@ -48,6 +48,9 @@ enum dc_status {
+ 	DC_NO_DSC_RESOURCE = 17,
+ #endif
+ 	DC_FAIL_UNSUPPORTED_1 = 18,
++	DC_FAIL_CLK_EXCEED_MAX = 21,
++	DC_FAIL_CLK_BELOW_MIN = 22, /*THIS IS MIN PER IP*/
++	DC_FAIL_CLK_BELOW_CFG_REQUIRED = 23, /*THIS IS hard_min in PPLIB*/
+ 
+ 	DC_ERROR_UNEXPECTED = -1
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+index 36ebd5bc7863..938bdc5c21a1 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+@@ -28,6 +28,9 @@
+ 
+ #include "dc.h"
+ 
++#define DCN_MINIMUM_DISPCLK_Khz 100000
++#define DCN_MINIMUM_DPPCLK_Khz 100000
++
+ /* Public interfaces */
+ 
+ struct clk_states {
+@@ -51,6 +54,10 @@ struct clk_mgr_funcs {
+ 	void (*init_clocks)(struct clk_mgr *clk_mgr);
+ 
+ 	void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
++	void (*get_clock)(struct clk_mgr *clk_mgr,
++			struct dc_state *context,
++			enum dc_clock_type clock_type,
++			struct dc_clock_config *clock_cfg);
+ };
+ 
+ struct clk_mgr {
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index 4d56d48a3179..36be08adae05 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -294,6 +294,15 @@ struct hw_sequencer_funcs {
+ 	void (*disable_writeback)(struct dc *dc,
+ 			unsigned int dwb_pipe_inst);
+ #endif
++	enum dc_status (*set_clock)(struct dc *dc,
++			enum dc_clock_type clock_type,
++			uint32_t clk_khz,
++			uint32_t stepping);
++
++	void (*get_clock)(struct dc *dc,
++			enum dc_clock_type clock_type,
++			struct dc_clock_config *clock_cfg);
++
+ };
+ 
+ void color_space_to_black_color(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3073-drm-amd-display-Change-offset_to_id-to-reflect-what-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3073-drm-amd-display-Change-offset_to_id-to-reflect-what-.patch
new file mode 100644
index 00000000..ee289099
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3073-drm-amd-display-Change-offset_to_id-to-reflect-what-.patch
@@ -0,0 +1,55 @@
+From 8f645d48793e10259b3241b106579288bb143a56 Mon Sep 17 00:00:00 2001
+From: Murton Liu <murton.liu@amd.com>
+Date: Tue, 2 Jul 2019 11:32:19 -0400
+Subject: [PATCH 3073/4256] drm/amd/display: Change offset_to_id to reflect
+ what id_to_offset returns
+
+id_to_offset does not point to the same reg offset that offset_to_id checks for,
+causing unintended asserts
+
+Signed-off-by: Murton Liu <murton.liu@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c |  2 +-
+ drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c     | 10 +++-------
+ 2 files changed, 4 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
+index b393cc13298a..915e896e0e91 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
+@@ -71,7 +71,7 @@ static bool offset_to_id(
+ {
+ 	switch (offset) {
+ 	/* GENERIC */
+-	case REG(DC_GENERICA):
++	case REG(DC_GPIO_GENERIC_A):
+ 		*id = GPIO_ID_GENERIC;
+ 		switch (mask) {
+ 		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
+index 937478bac796..80f938e68285 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
+@@ -148,14 +148,10 @@ struct gpio *dal_gpio_service_create_generic_mux(
+ 	uint32_t en;
+ 	struct gpio *generic;
+ 
+-	if (mask == 1)
+-		en = GPIO_GENERIC_A;
+-	else if (mask == 0x00000100L)
+-		en = GPIO_GENERIC_B;
+-	else
++	if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) {
++		ASSERT_CRITICAL(false);
+ 		return NULL;
+-
+-	id = GPIO_ID_GENERIC;
++	}
+ 
+ 	generic = dal_gpio_create(
+ 		service, id, en, GPIO_PIN_OUTPUT_STATE_DEFAULT);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3074-drm-amd-display-init-res_pool-dccg_ref-dchub_ref-wit.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3074-drm-amd-display-init-res_pool-dccg_ref-dchub_ref-wit.patch
new file mode 100644
index 00000000..a337b330
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3074-drm-amd-display-init-res_pool-dccg_ref-dchub_ref-wit.patch
@@ -0,0 +1,129 @@
+From 7ac71c9eae141cc72c5642ab4863eafa13f40e97 Mon Sep 17 00:00:00 2001
+From: hersen wu <hersenxs.wu@amd.com>
+Date: Wed, 26 Jun 2019 13:06:07 -0400
+Subject: [PATCH 3074/4256] drm/amd/display: init res_pool dccg_ref, dchub_ref
+ with xtalin_freq
+
+[WHY] dc sw clock implementation of navi10 and raven are not exact the
+same. dcccg, dchub reference clock initialization is done after dc calls
+vbios dispcontroller_init table. for raven family, before
+dispcontroller_init is called by dc, the ref clk values are referred
+by sw clock implementation and program asic register using wrong
+values. this causes dchub pstate error. This need provide valid ref
+clk values. for navi10, since dispcontroller_init is not called,
+dchubbub_global_timer_enable = 0, hubbub2_get_dchub_ref_freq will
+hit aeert. this need remove hubbub2_get_dchub_ref_freq from this
+location and move to dcn20_init_hw.
+
+[HOW] for all asic, initialize dccg, dchub ref clk with data from
+vbios firmware table by default. for raven asic family, use these data
+from vbios, for asic which support sw dccg component, like navi10,
+read ref clk by sw dccg functions and update the ref clk.
+
+Signed-off-by: hersen wu <hersenxs.wu@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_resource.c | 42 +++++++------------
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 25 +++++++++++
+ 2 files changed, 41 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 5e7b8b2dd178..b567b2159f1a 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -172,32 +172,22 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
+ 	if (res_pool != NULL) {
+ 		struct dc_firmware_info fw_info = { { 0 } };
+ 
+-		if (dc->ctx->dc_bios->funcs->get_firmware_info(
+-				dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
+-				res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency;
+-
+-				if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+-					// On FPGA these dividers are currently not configured by GDB
+-					res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
+-					res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
+-				} else if (res_pool->dccg && res_pool->hubbub) {
+-					// If DCCG reference frequency cannot be determined (usually means not set to xtalin) then this is a critical error
+-					// as this value must be known for DCHUB programming
+-					(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+-							fw_info.pll_info.crystal_frequency,
+-							&res_pool->ref_clocks.dccg_ref_clock_inKhz);
+-
+-					// Similarly, if DCHUB reference frequency cannot be determined, then it is also a critical error
+-					(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+-							res_pool->ref_clocks.dccg_ref_clock_inKhz,
+-							&res_pool->ref_clocks.dchub_ref_clock_inKhz);
+-				} else {
+-					// Not all ASICs have DCCG sw component
+-					res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
+-					res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
+-				}
+-			} else
+-				ASSERT_CRITICAL(false);
++		if (dc->ctx->dc_bios->funcs->get_firmware_info(dc->ctx->dc_bios,
++				&fw_info) == BP_RESULT_OK) {
++			res_pool->ref_clocks.xtalin_clock_inKhz =
++				fw_info.pll_info.crystal_frequency;
++			/* initialize with firmware data first, no all
++			 * ASIC have DCCG SW component. FPGA or
++			 * simulation need initialization of
++			 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
++			 * with xtalin_clock_inKhz
++			 */
++			res_pool->ref_clocks.dccg_ref_clock_inKhz =
++				res_pool->ref_clocks.xtalin_clock_inKhz;
++			res_pool->ref_clocks.dchub_ref_clock_inKhz =
++				res_pool->ref_clocks.xtalin_clock_inKhz;
++		} else
++			ASSERT_CRITICAL(false);
+ 	}
+ 
+ 	return res_pool;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 432156b52602..c7c47f2a6e38 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -562,6 +562,7 @@ static void dcn20_init_hw(struct dc *dc)
+ 	struct dc_bios *dcb = dc->ctx->dc_bios;
+ 	struct resource_pool *res_pool = dc->res_pool;
+ 	struct dc_state  *context = dc->current_state;
++	struct dc_firmware_info fw_info = { { 0 } };
+ 
+ 	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
+ 		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
+@@ -585,6 +586,30 @@ static void dcn20_init_hw(struct dc *dc)
+ 	} else {
+ 		if (!dcb->funcs->is_accelerated_mode(dcb)) {
+ 			bios_golden_init(dc);
++			if (dc->ctx->dc_bios->funcs->get_firmware_info(
++					dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
++				res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency;
++
++				if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
++					if (res_pool->dccg && res_pool->hubbub) {
++
++						(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
++								fw_info.pll_info.crystal_frequency,
++								&res_pool->ref_clocks.dccg_ref_clock_inKhz);
++
++						(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
++								res_pool->ref_clocks.dccg_ref_clock_inKhz,
++								&res_pool->ref_clocks.dchub_ref_clock_inKhz);
++					} else {
++						// Not all ASICs have DCCG sw component
++						res_pool->ref_clocks.dccg_ref_clock_inKhz =
++								res_pool->ref_clocks.xtalin_clock_inKhz;
++						res_pool->ref_clocks.dchub_ref_clock_inKhz =
++								res_pool->ref_clocks.xtalin_clock_inKhz;
++					}
++				}
++			} else
++				ASSERT_CRITICAL(false);
+ 			disable_vga(dc->hwseq);
+ 		}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3075-drm-amd-display-add-a-option-to-force-the-clock-at-e.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3075-drm-amd-display-add-a-option-to-force-the-clock-at-e.patch
new file mode 100644
index 00000000..a59bcc5a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3075-drm-amd-display-add-a-option-to-force-the-clock-at-e.patch
@@ -0,0 +1,61 @@
+From 8ab65fac8b5810dedc0c1f4a0cf599b43cd67179 Mon Sep 17 00:00:00 2001
+From: Charlene Liu <charlene.liu@amd.com>
+Date: Tue, 2 Jul 2019 14:04:35 -0400
+Subject: [PATCH 3075/4256] drm/amd/display: add a option to force the clock at
+ every mode change.
+
+[Description]
+This is for HW negative stress testing use.
+force reset the dispclk and dppclk even the same clock already set in HW.
+
+Signed-off-by: Charlene Liu <charlene.liu@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 9 ++++++++-
+ drivers/gpu/drm/amd/display/dc/dc.h                      | 1 +
+ 2 files changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index 9a873e2b3736..3cff4f0518d3 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -151,7 +151,14 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+ 	bool enter_display_off = false;
+ 	bool dpp_clock_lowered = false;
+ 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
++	bool force_reset = false;
+ 
++	if (clk_mgr_base->clks.dispclk_khz == 0 ||
++		dc->debug.force_clock_mode & 0x1) {
++		//this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3.
++		force_reset = true;
++		//force_clock_mode 0x1:  force reset the clock even it is the same clock as long as it is in Passive level.
++	}
+ 	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
+ 	if (dc->res_pool->pp_smu)
+ 		pp_smu = &dc->res_pool->pp_smu->nv_funcs;
+@@ -223,7 +230,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+ 
+ 		update_dispclk = true;
+ 	}
+-	if (dc->config.forced_clocks == false) {
++	if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
+ 		if (dpp_clock_lowered) {
+ 			// if clock is being lowered, increase DTO before lowering refclk
+ 			dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 79827884cd80..fded67795e73 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -388,6 +388,7 @@ struct dc_debug_options {
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	bool cm_in_bypass;
+ #endif
++	int force_clock_mode;/*every mode change.*/
+ };
+ 
+ struct dc_debug_data {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3076-drm-amd-display-use-min-disp-and-dpp-clk-debug-optio.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3076-drm-amd-display-use-min-disp-and-dpp-clk-debug-optio.patch
new file mode 100644
index 00000000..049798a1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3076-drm-amd-display-use-min-disp-and-dpp-clk-debug-optio.patch
@@ -0,0 +1,58 @@
+From 377dd6145f4f34175ad5dc359a147391a7b0d4d8 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Tue, 2 Jul 2019 14:51:01 -0400
+Subject: [PATCH 3076/4256] drm/amd/display: use min disp and dpp clk debug
+ option for dcn2
+
+This allows to set a minimum display and dpp clock on dcn2+ HW
+by adjusting clocks used for dml calculations.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h                   | 1 +
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 8 ++++----
+ 2 files changed, 5 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index fded67795e73..df06b41dcd5e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -347,6 +347,7 @@ struct dc_debug_options {
+ 	bool disable_pplib_wm_range;
+ 	enum wm_report_mode pplib_wm_report_mode;
+ 	unsigned int min_disp_clk_khz;
++	unsigned int min_dpp_clk_khz;
+ 	int sr_exit_time_dpm0_ns;
+ 	int sr_enter_plus_exit_time_dpm0_ns;
+ 	int sr_exit_time_ns;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 158743b165e8..5571b8bfc942 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2168,10 +2168,6 @@ bool dcn20_fast_validate_bw(
+ 		}
+ 		if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
+ 			context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
+-		if (dc->config.forced_clocks == true) {
+-			context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] =
+-					context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
+-		}
+ 		if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
+ 			hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe);
+ 			ASSERT(hsplit_pipe);
+@@ -2291,6 +2287,10 @@ void dcn20_calculate_wm(
+ 				pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
+ 				pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
+ 			}
++			if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
++				pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
++			if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
++				pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
+ 
+ 			pipe_cnt++;
+ 		}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3077-drm-amd-display-add-pipe-CRC-sources-without-disabli.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3077-drm-amd-display-add-pipe-CRC-sources-without-disabli.patch
new file mode 100644
index 00000000..4ee4eec6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3077-drm-amd-display-add-pipe-CRC-sources-without-disabli.patch
@@ -0,0 +1,183 @@
+From 353c7398469f749a6607d4a7bef52158fa909e55 Mon Sep 17 00:00:00 2001
+From: Dingchen Zhang <dingchen.zhang@amd.com>
+Date: Fri, 28 Jun 2019 17:23:24 -0400
+Subject: [PATCH 3077/4256] drm/amd/display: add pipe CRC sources without
+ disabling dithering.
+
+[Why]
+need to verify the impact of spatial dithering on 8bpc bypass mode.
+
+[How]
+added CRC sources and configure dihter option from dc stream.
+
+Change-Id: I8b6a55065146856ee210c98804e10316ab3e7e4b
+Signed-off-by: Dingchen Zhang <dingchen.zhang@amd.com>
+Reviewed-by: Hanghong Ma <Hanghong.Ma@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 61 ++++++++++++++-----
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h |  6 +-
+ 2 files changed, 51 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+index 609f1fdc10b3..e9a2c432e4d0 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+@@ -32,7 +32,9 @@
+ static const char *const pipe_crc_sources[] = {
+ 	"none",
+ 	"crtc",
++	"crtc dither",
+ 	"dprx",
++	"dprx dither",
+ 	"auto",
+ };
+ 
+@@ -44,10 +46,33 @@ static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source)
+ 		return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC;
+ 	if (!strcmp(source, "dprx"))
+ 		return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX;
++        if (!strcmp(source, "crtc dither"))
++                return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER;
++        if (!strcmp(source, "dprx dither"))
++                return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER;
+ 
+ 	return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID;
+ }
+ 
++static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src)
++{
++        return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) ||
++               (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER);
++}
++
++static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src)
++{
++        return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) ||
++               (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER);
++}
++
++static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src)
++{
++        return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) ||
++               (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) ||
++               (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE);
++}
++
+ const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
+                                                   size_t *count)
+ {
+@@ -55,6 +80,7 @@ const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
+         return pipe_crc_sources;
+ }
+ 
++
+ int
+ amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
+ 				 size_t *values_cnt)
+@@ -102,14 +128,18 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+          * USER REQ SRC | CURRENT SRC | BEHAVIOR
+          * -----------------------------
+          * None         | None        | Do nothing
+-         * None         | CRTC        | Disable CRTC CRC
+-         * None         | DPRX        | Disable DPRX CRC, need 'aux'
+-         * CRTC         | XXXX        | Enable CRTC CRC, configure DC strm
+-         * DPRX         | XXXX        | Enable DPRX CRC, need 'aux'
++         * None         | CRTC        | Disable CRTC CRC, set default to dither
++         * None         | DPRX        | Disable DPRX CRC, need 'aux', set default to dither
++         * None         | CRTC DITHER | Disable CRTC CRC
++         * None         | DPRX DITHER | Disable DPRX CRC, need 'aux'
++         * CRTC         | XXXX        | Enable CRTC CRC, no dither
++         * DPRX         | XXXX        | Enable DPRX CRC, need 'aux', no dither
++         * CRTC DITHER  | XXXX        | Enable CRTC CRC, set dither
++         * DPRX DITHER  | XXXX        | Enable DPRX CRC, need 'aux', set dither
+          */
+-        if (source == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX ||
++	if (dm_is_crc_source_dprx(source) ||
+                 (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE &&
+-                 crtc_state->crc_src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX)) {
++		 dm_is_crc_source_dprx(crtc_state->crc_src))) {
+                 aconn = stream_state->link->priv;
+ 
+                 if (!aconn) {
+@@ -125,7 +155,7 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+                         mutex_unlock(&adev->dm.dc_lock);
+                         return -EINVAL;
+                 }
+-        } else if (source == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) {
++	} else if (dm_is_crc_source_crtc(source)) {
+                 if (!dc_stream_configure_crc(stream_state->ctx->dc, stream_state,
+                                              enable, enable)) {
+                         mutex_unlock(&adev->dm.dc_lock);
+@@ -133,10 +163,13 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+                 }
+         }
+ 
+-	/* When enabling CRC, we should also disable dithering. */
+-	dc_stream_set_dither_option(stream_state,
+-				    enable ? DITHER_OPTION_TRUN8
+-					   : DITHER_OPTION_DEFAULT);
++        /* configure dithering */
++        if (!dm_need_crc_dither(source))
++                dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8);
++        else if (!dm_need_crc_dither(crtc_state->crc_src))
++                dc_stream_set_dither_option(stream_state, DITHER_OPTION_DEFAULT);
++
++	mutex_unlock(&adev->dm.dc_lock);
+ 
+ 	/*
+ 	 * Reading the CRC requires the vblank interrupt handler to be
+@@ -145,7 +178,7 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+ 	enabled = amdgpu_dm_is_valid_crc_source(crtc_state->crc_src);
+ 	if (!enabled && enable) {
+ 		drm_crtc_vblank_get(crtc);
+-		if (source == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) {
++		if (dm_is_crc_source_dprx(source)) {
+ 			if (drm_dp_start_crc(aux, crtc)) {
+ 				DRM_DEBUG_DRIVER("dp start crc failed\n");
+ 				return -EINVAL;
+@@ -153,7 +186,7 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+ 		}
+ 	} else if (enabled && !enable) {
+ 		drm_crtc_vblank_put(crtc);
+-		if (crtc_state->crc_src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) {
++		if (dm_is_crc_source_dprx(source)) {
+ 			if (drm_dp_stop_crc(aux)) {
+ 				DRM_DEBUG_DRIVER("dp stop crc failed\n");
+ 				return -EINVAL;
+@@ -202,7 +235,7 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc)
+ 		return;
+ 	}
+ 
+-        if (crtc_state->crc_src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) {
++	if (dm_is_crc_source_crtc(crtc_state->crc_src)) {
+                 if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state,
+                                        &crcs[0], &crcs[1], &crcs[2]))
+                         return;
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
+index b63a9011f511..14de7301c28d 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
+@@ -29,15 +29,17 @@
+ enum amdgpu_dm_pipe_crc_source {
+ 	AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
+ 	AMDGPU_DM_PIPE_CRC_SOURCE_CRTC,
++	AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER,
+ 	AMDGPU_DM_PIPE_CRC_SOURCE_DPRX,
++	AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER,
+ 	AMDGPU_DM_PIPE_CRC_SOURCE_MAX,
+ 	AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1,
+ };
+ 
+ static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source)
+ {
+-	return (source == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) ||
+-		   (source == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX);
++	return (source > AMDGPU_DM_PIPE_CRC_SOURCE_NONE) &&
++	       (source < AMDGPU_DM_PIPE_CRC_SOURCE_MAX);
+ }
+ 
+ /* amdgpu_dm_crc.c */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3078-drm-amd-display-Implement-DAL3-GPU-Integer-Scaling.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3078-drm-amd-display-Implement-DAL3-GPU-Integer-Scaling.patch
new file mode 100644
index 00000000..37093bae
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3078-drm-amd-display-Implement-DAL3-GPU-Integer-Scaling.patch
@@ -0,0 +1,72 @@
+From 061134fb8b67e34cc7719560555e7f626e780896 Mon Sep 17 00:00:00 2001
+From: Reza Amini <Reza.Amini@amd.com>
+Date: Mon, 10 Jun 2019 16:45:50 -0400
+Subject: [PATCH 3078/4256] drm/amd/display: Implement DAL3 GPU Integer Scaling
+
+[WHY]
+Users want to not have filtering when scaling by integer
+multiples to native timing.
+
+[HOW]
+If timing is a multiple integer of view, we set number of taps
+to 1 (effectivly closest neighbour).
+
+Signed-off-by: Reza Amini <Reza.Amini@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Acked-by: Tony Cheng <Tony.Cheng@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_resource.c    | 16 ++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/dc_hw_types.h     |  1 +
+ 2 files changed, 17 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index b567b2159f1a..31a49c59c278 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -937,7 +937,14 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
+ 	data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
+ 
+ }
++static bool are_rect_integer_multiples(struct rect src, struct rect dest)
++{
++	if (dest.width  >= src.width  && dest.width  % src.width  == 0 &&
++		dest.height >= src.height && dest.height % src.height == 0)
++		return true;
+ 
++	return false;
++}
+ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
+ {
+ 	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+@@ -980,6 +987,15 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
+ 	if (pipe_ctx->plane_res.dpp != NULL)
+ 		res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
+ 				pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
++
++	if (res &&
++	    plane_state->scaling_quality.integer_scaling &&
++	    are_rect_integer_multiples(pipe_ctx->plane_res.scl_data.viewport,
++				       pipe_ctx->plane_res.scl_data.recout)) {
++		pipe_ctx->plane_res.scl_data.taps.v_taps = 1;
++		pipe_ctx->plane_res.scl_data.taps.h_taps = 1;
++	}
++
+ 	if (!res) {
+ 		/* Try 24 bpp linebuffer */
+ 		pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+index e9a6225f4720..28a2cd2d2a49 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+@@ -614,6 +614,7 @@ struct scaling_taps {
+ 	uint32_t h_taps;
+ 	uint32_t v_taps_c;
+ 	uint32_t h_taps_c;
++	bool integer_scaling;
+ };
+ 
+ enum dc_timing_standard {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3079-drm-amd-display-add-dcc-programming-for-dual-plane.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3079-drm-amd-display-add-dcc-programming-for-dual-plane.patch
new file mode 100644
index 00000000..90d40b7b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3079-drm-amd-display-add-dcc-programming-for-dual-plane.patch
@@ -0,0 +1,712 @@
+From 859be483bd5528fc2069d69f8477c45b4b6630df Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 3 Jul 2019 16:20:42 -0400
+Subject: [PATCH 3079/4256] drm/amd/display: add dcc programming for dual plane
+
+Add dual plane dcc programming support for
+surfaces.
+
+Removes unions from plane size and dcc params as they
+serve no practical purpose only making our code
+more convoluted. This results in easy dual plane
+dcc and surface size programming.
+
+Temporary diags_dm code is used to handle the interface
+change without breaking functionality as a diags change
+needs to be applied after this one.
+
+Change-Id: Ibad8dbc1f3e2dfdb457ac47bd43488bd0b8c2021
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 42 +++++++--------
+ .../gpu/drm/amd/display/dc/calcs/dce_calcs.c  |  2 +-
+ .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c  |  2 +-
+ drivers/gpu/drm/amd/display/dc/core/dc.c      | 10 ++--
+ .../gpu/drm/amd/display/dc/core/dc_debug.c    | 40 +++++++-------
+ drivers/gpu/drm/amd/display/dc/dc.h           |  4 +-
+ drivers/gpu/drm/amd/display/dc/dc_hw_types.h  | 54 +++++++++----------
+ .../drm/amd/display/dc/dce/dce_mem_input.c    | 10 ++--
+ .../display/dc/dce110/dce110_mem_input_v.c    | 42 +++++++--------
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 20 +++----
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h |  4 +-
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  4 +-
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 20 +++----
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h |  4 +-
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 12 ++---
+ drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |  2 +-
+ .../gpu/drm/amd/display/dc/inc/hw/mem_input.h |  2 +-
+ 17 files changed, 136 insertions(+), 138 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 844e9442449f..33150eb3c135 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -2756,7 +2756,7 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev,
+ 			  const struct amdgpu_framebuffer *afb,
+ 			  const enum surface_pixel_format format,
+ 			  const enum dc_rotation_angle rotation,
+-			  const union plane_size *plane_size,
++			  const struct plane_size *plane_size,
+ 			  const union dc_tiling_info *tiling_info,
+ 			  const uint64_t info,
+ 			  struct dc_plane_dcc_param *dcc,
+@@ -2782,8 +2782,8 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev,
+ 		return -EINVAL;
+ 
+ 	input.format = format;
+-	input.surface_size.width = plane_size->grph.surface_size.width;
+-	input.surface_size.height = plane_size->grph.surface_size.height;
++	input.surface_size.width = plane_size->surface_size.width;
++	input.surface_size.height = plane_size->surface_size.height;
+ 	input.swizzle_mode = tiling_info->gfx9.swizzle;
+ 
+ 	if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
+@@ -2801,9 +2801,9 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev,
+ 		return -EINVAL;
+ 
+ 	dcc->enable = 1;
+-	dcc->grph.meta_pitch =
++	dcc->meta_pitch =
+ 		AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
+-	dcc->grph.independent_64b_blks = i64b;
++	dcc->independent_64b_blks = i64b;
+ 
+ 	dcc_address = get_dcc_address(afb->address, info);
+ 	address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
+@@ -2819,7 +2819,7 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
+ 			     const enum dc_rotation_angle rotation,
+ 			     const uint64_t tiling_flags,
+ 			     union dc_tiling_info *tiling_info,
+-			     union plane_size *plane_size,
++			     struct plane_size *plane_size,
+ 			     struct dc_plane_dcc_param *dcc,
+ 			     struct dc_plane_address *address)
+ {
+@@ -2832,11 +2832,11 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
+ 	memset(address, 0, sizeof(*address));
+ 
+ 	if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
+-		plane_size->grph.surface_size.x = 0;
+-		plane_size->grph.surface_size.y = 0;
+-		plane_size->grph.surface_size.width = fb->width;
+-		plane_size->grph.surface_size.height = fb->height;
+-		plane_size->grph.surface_pitch =
++		plane_size->surface_size.x = 0;
++                plane_size->surface_size.y = 0;
++                plane_size->surface_size.width = fb->width;
++                plane_size->surface_size.height = fb->height;
++                plane_size->surface_pitch =
+ 			fb->pitches[0] / fb->format->cpp[0];
+ 
+ 		address->type = PLN_ADDR_TYPE_GRAPHICS;
+@@ -2845,20 +2845,20 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
+ 	} else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
+ 		uint64_t chroma_addr = afb->address + fb->offsets[1];
+ 
+-		plane_size->video.luma_size.x = 0;
+-		plane_size->video.luma_size.y = 0;
+-		plane_size->video.luma_size.width = fb->width;
+-		plane_size->video.luma_size.height = fb->height;
+-		plane_size->video.luma_pitch =
++		plane_size->surface_size.x = 0;
++                plane_size->surface_size.y = 0;
++                plane_size->surface_size.width = fb->width;
++                plane_size->surface_size.height = fb->height;
++                plane_size->surface_pitch =
+ 			fb->pitches[0] / fb->format->cpp[0];
+ 
+-		plane_size->video.chroma_size.x = 0;
+-		plane_size->video.chroma_size.y = 0;
++		plane_size->chroma_size.x = 0;
++		plane_size->chroma_size.y = 0;
+ 		/* TODO: set these based on surface format */
+-		plane_size->video.chroma_size.width = fb->width / 2;
+-		plane_size->video.chroma_size.height = fb->height / 2;
++		plane_size->chroma_size.width = fb->width / 2;
++		plane_size->chroma_size.height = fb->height / 2;
+ 
+-		plane_size->video.chroma_pitch =
++		plane_size->chroma_pitch =
+ 			fb->pitches[1] / fb->format->cpp[1];
+ 
+ 		address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+index f3aa7b53d2aa..fdab16ea0a2e 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
++++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+@@ -2850,7 +2850,7 @@ static void populate_initial_data(
+ 			data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.height);
+ 			data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.width);
+ 			data->pitch_in_pixels[num_displays * 2 + j] = bw_int_to_fixed(
+-					pipe[i].bottom_pipe->plane_state->plane_size.grph.surface_pitch);
++					pipe[i].bottom_pipe->plane_state->plane_size.surface_pitch);
+ 			data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps);
+ 			data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps);
+ 			data->h_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed(
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+index 38365dd911a3..061c6e3a3088 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+@@ -329,7 +329,7 @@ static void pipe_ctx_to_e2e_pipe_params (
+ 			dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0;
+ 	}
+ 	input->src.dcc_rate            = 1;
+-	input->src.meta_pitch          = pipe->plane_state->dcc.grph.meta_pitch;
++	input->src.meta_pitch          = pipe->plane_state->dcc.meta_pitch;
+ 	input->src.source_scan         = dm_horz;
+ 	input->src.sw_mode             = pipe->plane_state->tiling_info.gfx9.swizzle;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index a05b47c667a8..0b7fbd59cb3b 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1359,8 +1359,8 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
+ 	}
+ 
+ 	if (u->plane_info->dcc.enable != u->surface->dcc.enable
+-			|| u->plane_info->dcc.grph.independent_64b_blks != u->surface->dcc.grph.independent_64b_blks
+-			|| u->plane_info->dcc.grph.meta_pitch != u->surface->dcc.grph.meta_pitch) {
++			|| u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
++			|| u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
+ 		update_flags->bits.dcc_change = 1;
+ 		elevate_update_type(&update_type, UPDATE_TYPE_MED);
+ 	}
+@@ -1374,9 +1374,9 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
+ 		elevate_update_type(&update_type, UPDATE_TYPE_FULL);
+ 	}
+ 
+-	if (u->plane_info->plane_size.grph.surface_pitch != u->surface->plane_size.grph.surface_pitch
+-			|| u->plane_info->plane_size.video.luma_pitch != u->surface->plane_size.video.luma_pitch
+-			|| u->plane_info->plane_size.video.chroma_pitch != u->surface->plane_size.video.chroma_pitch) {
++	if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
++			|| u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
++			|| u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
+ 		update_flags->bits.plane_size_change = 1;
+ 		elevate_update_type(&update_type, UPDATE_TYPE_MED);
+ 	}
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+index 5903e7822f98..b9227d5de3a3 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+@@ -115,16 +115,16 @@ void pre_surface_trace(
+ 				plane_state->clip_rect.height);
+ 
+ 		SURFACE_TRACE(
+-				"plane_state->plane_size.grph.surface_size.x = %d;\n"
+-				"plane_state->plane_size.grph.surface_size.y = %d;\n"
+-				"plane_state->plane_size.grph.surface_size.width = %d;\n"
+-				"plane_state->plane_size.grph.surface_size.height = %d;\n"
+-				"plane_state->plane_size.grph.surface_pitch = %d;\n",
+-				plane_state->plane_size.grph.surface_size.x,
+-				plane_state->plane_size.grph.surface_size.y,
+-				plane_state->plane_size.grph.surface_size.width,
+-				plane_state->plane_size.grph.surface_size.height,
+-				plane_state->plane_size.grph.surface_pitch);
++				"plane_state->plane_size.surface_size.x = %d;\n"
++				"plane_state->plane_size.surface_size.y = %d;\n"
++				"plane_state->plane_size.surface_size.width = %d;\n"
++				"plane_state->plane_size.surface_size.height = %d;\n"
++				"plane_state->plane_size.surface_pitch = %d;\n",
++				plane_state->plane_size.surface_size.x,
++				plane_state->plane_size.surface_size.y,
++				plane_state->plane_size.surface_size.width,
++				plane_state->plane_size.surface_size.height,
++				plane_state->plane_size.surface_pitch);
+ 
+ 
+ 		SURFACE_TRACE(
+@@ -202,20 +202,20 @@ void update_surface_trace(
+ 			SURFACE_TRACE(
+ 					"plane_info->color_space = %d;\n"
+ 					"plane_info->format = %d;\n"
+-					"plane_info->plane_size.grph.surface_pitch = %d;\n"
+-					"plane_info->plane_size.grph.surface_size.height = %d;\n"
+-					"plane_info->plane_size.grph.surface_size.width = %d;\n"
+-					"plane_info->plane_size.grph.surface_size.x = %d;\n"
+-					"plane_info->plane_size.grph.surface_size.y = %d;\n"
++					"plane_info->plane_size.surface_pitch = %d;\n"
++					"plane_info->plane_size.surface_size.height = %d;\n"
++					"plane_info->plane_size.surface_size.width = %d;\n"
++					"plane_info->plane_size.surface_size.x = %d;\n"
++					"plane_info->plane_size.surface_size.y = %d;\n"
+ 					"plane_info->rotation = %d;\n"
+ 					"plane_info->stereo_format = %d;\n",
+ 					update->plane_info->color_space,
+ 					update->plane_info->format,
+-					update->plane_info->plane_size.grph.surface_pitch,
+-					update->plane_info->plane_size.grph.surface_size.height,
+-					update->plane_info->plane_size.grph.surface_size.width,
+-					update->plane_info->plane_size.grph.surface_size.x,
+-					update->plane_info->plane_size.grph.surface_size.y,
++					update->plane_info->plane_size.surface_pitch,
++					update->plane_info->plane_size.surface_size.height,
++					update->plane_info->plane_size.surface_size.width,
++					update->plane_info->plane_size.surface_size.x,
++					update->plane_info->plane_size.surface_size.y,
+ 					update->plane_info->rotation,
+ 					update->plane_info->stereo_format);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index df06b41dcd5e..d5ac34f0a511 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -719,7 +719,7 @@ struct dc_plane_state {
+ 	struct rect dst_rect;
+ 	struct rect clip_rect;
+ 
+-	union plane_size plane_size;
++	struct plane_size plane_size;
+ 	union dc_tiling_info tiling_info;
+ 
+ 	struct dc_plane_dcc_param dcc;
+@@ -768,7 +768,7 @@ struct dc_plane_state {
+ };
+ 
+ struct dc_plane_info {
+-	union plane_size plane_size;
++	struct plane_size plane_size;
+ 	union dc_tiling_info tiling_info;
+ 	struct dc_plane_dcc_param dcc;
+ 	enum surface_pixel_format format;
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+index 28a2cd2d2a49..929c4eadc1dc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+@@ -115,42 +115,40 @@ struct rect {
+ 	int height;
+ };
+ 
+-union plane_size {
+-	/* Grph or Video will be selected
+-	 * based on format above:
+-	 * Use Video structure if
+-	 * format >= DalPixelFormat_VideoBegin
+-	 * else use Grph structure
++struct plane_size {
++	/* Graphic surface pitch in pixels.
++	 * In LINEAR_GENERAL mode, pitch
++	 * is 32 pixel aligned.
+ 	 */
+-	struct {
+-		struct rect surface_size;
+-		/* Graphic surface pitch in pixels.
+-		 * In LINEAR_GENERAL mode, pitch
+-		 * is 32 pixel aligned.
+-		 */
+-		int surface_pitch;
+-	} grph;
++	int surface_pitch;
++	int chroma_pitch;
++	struct rect surface_size;
++	struct rect chroma_size;
+ 
+-	struct {
+-		struct rect luma_size;
+-		/* Graphic surface pitch in pixels.
+-		 * In LINEAR_GENERAL mode, pitch is
+-		 * 32 pixel aligned.
+-		 */
+-		int luma_pitch;
++	union {
++		struct {
++			struct rect surface_size;
++			int surface_pitch;
++		} grph;
+ 
+-		struct rect chroma_size;
+-		/* Graphic surface pitch in pixels.
+-		 * In LINEAR_GENERAL mode, pitch is
+-		 * 32 pixel aligned.
+-		 */
+-		int chroma_pitch;
+-	} video;
++		struct {
++			struct rect luma_size;
++			int luma_pitch;
++			struct rect chroma_size;
++			int chroma_pitch;
++		} video;
++	};
+ };
+ 
+ struct dc_plane_dcc_param {
+ 	bool enable;
+ 
++	int meta_pitch;
++	bool independent_64b_blks;
++
++	int meta_pitch_c;
++	bool independent_64b_blks_c;
++
+ 	union {
+ 		struct {
+ 			int meta_pitch;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+index a24a2bda8656..1488ffddf4e3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+@@ -391,10 +391,10 @@ static void program_tiling(
+ static void program_size_and_rotation(
+ 	struct dce_mem_input *dce_mi,
+ 	enum dc_rotation_angle rotation,
+-	const union plane_size *plane_size)
++	const struct plane_size *plane_size)
+ {
+-	const struct rect *in_rect = &plane_size->grph.surface_size;
+-	struct rect hw_rect = plane_size->grph.surface_size;
++	const struct rect *in_rect = &plane_size->surface_size;
++	struct rect hw_rect = plane_size->surface_size;
+ 	const uint32_t rotation_angles[ROTATION_ANGLE_COUNT] = {
+ 			[ROTATION_ANGLE_0] = 0,
+ 			[ROTATION_ANGLE_90] = 1,
+@@ -423,7 +423,7 @@ static void program_size_and_rotation(
+ 			GRPH_Y_END, hw_rect.height);
+ 
+ 	REG_SET(GRPH_PITCH, 0,
+-			GRPH_PITCH, plane_size->grph.surface_pitch);
++			GRPH_PITCH, plane_size->surface_pitch);
+ 
+ 	REG_SET(HW_ROTATION, 0,
+ 			GRPH_ROTATION_ANGLE, rotation_angles[rotation]);
+@@ -505,7 +505,7 @@ static void dce_mi_program_surface_config(
+ 	struct mem_input *mi,
+ 	enum surface_pixel_format format,
+ 	union dc_tiling_info *tiling_info,
+-	union plane_size *plane_size,
++	struct plane_size *plane_size,
+ 	enum dc_rotation_angle rotation,
+ 	struct dc_plane_dcc_param *dcc,
+ 	bool horizontal_mirror)
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+index 9b9fc3d96c07..d54172d88f5f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+@@ -229,26 +229,26 @@ static void program_tiling(
+ static void program_size_and_rotation(
+ 	struct dce_mem_input *mem_input110,
+ 	enum dc_rotation_angle rotation,
+-	const union plane_size *plane_size)
++	const struct plane_size *plane_size)
+ {
+ 	uint32_t value = 0;
+-	union plane_size local_size = *plane_size;
++	struct plane_size local_size = *plane_size;
+ 
+ 	if (rotation == ROTATION_ANGLE_90 ||
+ 		rotation == ROTATION_ANGLE_270) {
+ 
+-		swap(local_size.video.luma_size.x,
+-		     local_size.video.luma_size.y);
+-		swap(local_size.video.luma_size.width,
+-		     local_size.video.luma_size.height);
+-		swap(local_size.video.chroma_size.x,
+-		     local_size.video.chroma_size.y);
+-		swap(local_size.video.chroma_size.width,
+-		     local_size.video.chroma_size.height);
++		swap(local_size.surface_size.x,
++		     local_size.surface_size.y);
++		swap(local_size.surface_size.width,
++		     local_size.surface_size.height);
++		swap(local_size.chroma_size.x,
++		     local_size.chroma_size.y);
++		swap(local_size.chroma_size.width,
++		     local_size.chroma_size.height);
+ 	}
+ 
+ 	value = 0;
+-	set_reg_field_value(value, local_size.video.luma_pitch,
++	set_reg_field_value(value, local_size.surface_pitch,
+ 			UNP_GRPH_PITCH_L, GRPH_PITCH_L);
+ 
+ 	dm_write_reg(
+@@ -257,7 +257,7 @@ static void program_size_and_rotation(
+ 		value);
+ 
+ 	value = 0;
+-	set_reg_field_value(value, local_size.video.chroma_pitch,
++	set_reg_field_value(value, local_size.chroma_pitch,
+ 			UNP_GRPH_PITCH_C, GRPH_PITCH_C);
+ 	dm_write_reg(
+ 		mem_input110->base.ctx,
+@@ -297,8 +297,8 @@ static void program_size_and_rotation(
+ 		value);
+ 
+ 	value = 0;
+-	set_reg_field_value(value, local_size.video.luma_size.x +
+-			local_size.video.luma_size.width,
++	set_reg_field_value(value, local_size.surface_size.x +
++			local_size.surface_size.width,
+ 			UNP_GRPH_X_END_L, GRPH_X_END_L);
+ 	dm_write_reg(
+ 		mem_input110->base.ctx,
+@@ -306,8 +306,8 @@ static void program_size_and_rotation(
+ 		value);
+ 
+ 	value = 0;
+-	set_reg_field_value(value, local_size.video.chroma_size.x +
+-			local_size.video.chroma_size.width,
++	set_reg_field_value(value, local_size.chroma_size.x +
++			local_size.chroma_size.width,
+ 			UNP_GRPH_X_END_C, GRPH_X_END_C);
+ 	dm_write_reg(
+ 		mem_input110->base.ctx,
+@@ -315,8 +315,8 @@ static void program_size_and_rotation(
+ 		value);
+ 
+ 	value = 0;
+-	set_reg_field_value(value, local_size.video.luma_size.y +
+-			local_size.video.luma_size.height,
++	set_reg_field_value(value, local_size.surface_size.y +
++			local_size.surface_size.height,
+ 			UNP_GRPH_Y_END_L, GRPH_Y_END_L);
+ 	dm_write_reg(
+ 		mem_input110->base.ctx,
+@@ -324,8 +324,8 @@ static void program_size_and_rotation(
+ 		value);
+ 
+ 	value = 0;
+-	set_reg_field_value(value, local_size.video.chroma_size.y +
+-			local_size.video.chroma_size.height,
++	set_reg_field_value(value, local_size.chroma_size.y +
++			local_size.chroma_size.height,
+ 			UNP_GRPH_Y_END_C, GRPH_Y_END_C);
+ 	dm_write_reg(
+ 		mem_input110->base.ctx,
+@@ -637,7 +637,7 @@ void dce_mem_input_v_program_surface_config(
+ 	struct mem_input *mem_input,
+ 	enum surface_pixel_format format,
+ 	union dc_tiling_info *tiling_info,
+-	union plane_size *plane_size,
++	struct plane_size *plane_size,
+ 	enum dc_rotation_angle rotation,
+ 	struct dc_plane_dcc_param *dcc,
+ 	bool horizotal_mirror)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+index a16128814d62..03f5aa10c4c4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+@@ -163,7 +163,7 @@ void hubp1_program_tiling(
+ void hubp1_program_size(
+ 	struct hubp *hubp,
+ 	enum surface_pixel_format format,
+-	const union plane_size *plane_size,
++	const struct plane_size *plane_size,
+ 	struct dc_plane_dcc_param *dcc)
+ {
+ 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
+@@ -173,16 +173,16 @@ void hubp1_program_size(
+ 	 * 444 or 420 luma
+ 	 */
+ 	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) {
+-		ASSERT(plane_size->video.chroma_pitch != 0);
++		ASSERT(plane_size->chroma_pitch != 0);
+ 		/* Chroma pitch zero can cause system hang! */
+ 
+-		pitch = plane_size->video.luma_pitch - 1;
+-		meta_pitch = dcc->video.meta_pitch_l - 1;
+-		pitch_c = plane_size->video.chroma_pitch - 1;
+-		meta_pitch_c = dcc->video.meta_pitch_c - 1;
++		pitch = plane_size->surface_pitch - 1;
++		meta_pitch = dcc->meta_pitch - 1;
++		pitch_c = plane_size->chroma_pitch - 1;
++		meta_pitch_c = dcc->meta_pitch_c - 1;
+ 	} else {
+-		pitch = plane_size->grph.surface_pitch - 1;
+-		meta_pitch = dcc->grph.meta_pitch - 1;
++		pitch = plane_size->surface_pitch - 1;
++		meta_pitch = dcc->meta_pitch - 1;
+ 		pitch_c = 0;
+ 		meta_pitch_c = 0;
+ 	}
+@@ -526,13 +526,13 @@ void hubp1_program_surface_config(
+ 	struct hubp *hubp,
+ 	enum surface_pixel_format format,
+ 	union dc_tiling_info *tiling_info,
+-	union plane_size *plane_size,
++	struct plane_size *plane_size,
+ 	enum dc_rotation_angle rotation,
+ 	struct dc_plane_dcc_param *dcc,
+ 	bool horizontal_mirror,
+ 	unsigned int compat_level)
+ {
+-	hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);
++	hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
+ 	hubp1_program_tiling(hubp, tiling_info, format);
+ 	hubp1_program_size(hubp, format, plane_size, dcc);
+ 	hubp1_program_rotation(hubp, rotation, horizontal_mirror);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+index 8f4bcdc74116..344e446e337d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+@@ -685,7 +685,7 @@ void hubp1_program_surface_config(
+ 	struct hubp *hubp,
+ 	enum surface_pixel_format format,
+ 	union dc_tiling_info *tiling_info,
+-	union plane_size *plane_size,
++	struct plane_size *plane_size,
+ 	enum dc_rotation_angle rotation,
+ 	struct dc_plane_dcc_param *dcc,
+ 	bool horizontal_mirror,
+@@ -707,7 +707,7 @@ void hubp1_program_pixel_format(
+ void hubp1_program_size(
+ 	struct hubp *hubp,
+ 	enum surface_pixel_format format,
+-	const union plane_size *plane_size,
++	const struct plane_size *plane_size,
+ 	struct dc_plane_dcc_param *dcc);
+ 
+ void hubp1_program_rotation(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 5ded8b0ed93a..29e548ab73c4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2130,7 +2130,7 @@ void update_dchubp_dpp(
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
+ 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+-	union plane_size size = plane_state->plane_size;
++	struct plane_size size = plane_state->plane_size;
+ 	unsigned int compat_level = 0;
+ 
+ 	/* depends on DML calculation, DPP clock value may change dynamically */
+@@ -2176,7 +2176,7 @@ void update_dchubp_dpp(
+ 			&pipe_ctx->ttu_regs);
+ 	}
+ 
+-	size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
++	size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
+ 
+ 	if (plane_state->update_flags.bits.full_update ||
+ 		plane_state->update_flags.bits.bpp_change)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+index a167f867cb72..487de87b03eb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+@@ -397,7 +397,7 @@ static void hubp2_program_tiling(
+ void hubp2_program_size(
+ 	struct hubp *hubp,
+ 	enum surface_pixel_format format,
+-	const union plane_size *plane_size,
++	const struct plane_size *plane_size,
+ 	struct dc_plane_dcc_param *dcc)
+ {
+ 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+@@ -410,16 +410,16 @@ void hubp2_program_size(
+ 	use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
+ 		&& format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END;
+ 	if (use_pitch_c) {
+-		ASSERT(plane_size->video.chroma_pitch != 0);
++		ASSERT(plane_size->chroma_pitch != 0);
+ 		/* Chroma pitch zero can cause system hang! */
+ 
+-		pitch = plane_size->video.luma_pitch - 1;
+-		meta_pitch = dcc->video.meta_pitch_l - 1;
+-		pitch_c = plane_size->video.chroma_pitch - 1;
+-		meta_pitch_c = dcc->video.meta_pitch_c - 1;
++		pitch = plane_size->surface_pitch - 1;
++		meta_pitch = dcc->meta_pitch - 1;
++		pitch_c = plane_size->chroma_pitch - 1;
++		meta_pitch_c = dcc->meta_pitch_c - 1;
+ 	} else {
+-		pitch = plane_size->grph.surface_pitch - 1;
+-		meta_pitch = dcc->grph.meta_pitch - 1;
++		pitch = plane_size->surface_pitch - 1;
++		meta_pitch = dcc->meta_pitch - 1;
+ 		pitch_c = 0;
+ 		meta_pitch_c = 0;
+ 	}
+@@ -592,7 +592,7 @@ void hubp2_program_surface_config(
+ 	struct hubp *hubp,
+ 	enum surface_pixel_format format,
+ 	union dc_tiling_info *tiling_info,
+-	union plane_size *plane_size,
++	struct plane_size *plane_size,
+ 	enum dc_rotation_angle rotation,
+ 	struct dc_plane_dcc_param *dcc,
+ 	bool horizontal_mirror,
+@@ -600,7 +600,7 @@ void hubp2_program_surface_config(
+ {
+ 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+ 
+-	hubp2_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);
++	hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
+ 	hubp2_program_tiling(hubp2, tiling_info, format);
+ 	hubp2_program_size(hubp, format, plane_size, dcc);
+ 	hubp2_program_rotation(hubp, rotation, horizontal_mirror);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+index c8418235e154..1c53af4811e8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+@@ -273,7 +273,7 @@ void hubp2_dcc_control(struct hubp *hubp, bool enable,
+ void hubp2_program_size(
+ 	struct hubp *hubp,
+ 	enum surface_pixel_format format,
+-	const union plane_size *plane_size,
++	const struct plane_size *plane_size,
+ 	struct dc_plane_dcc_param *dcc);
+ 
+ void hubp2_program_rotation(
+@@ -289,7 +289,7 @@ void hubp2_program_surface_config(
+ 	struct hubp *hubp,
+ 	enum surface_pixel_format format,
+ 	union dc_tiling_info *tiling_info,
+-	union plane_size *plane_size,
++	struct plane_size *plane_size,
+ 	enum dc_rotation_angle rotation,
+ 	struct dc_plane_dcc_param *dcc,
+ 	bool horizontal_mirror,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 5571b8bfc942..296bc7e4c4a2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1820,13 +1820,13 @@ int dcn20_populate_dml_pipes_from_context(
+ 			pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
+ 			pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
+ 			if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
+-				pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.video.luma_pitch;
+-				pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.video.chroma_pitch;
+-				pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.video.meta_pitch_l;
+-				pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.video.meta_pitch_c;
++				pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
++				pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
++				pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
++				pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
+ 			} else {
+-				pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.grph.surface_pitch;
+-				pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.grph.meta_pitch;
++				pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
++				pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
+ 			}
+ 			pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
+ 			pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+index 51bff8717cc9..61cd4f8752c3 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+@@ -103,7 +103,7 @@ struct hubp_funcs {
+ 		struct hubp *hubp,
+ 		enum surface_pixel_format format,
+ 		union dc_tiling_info *tiling_info,
+-		union plane_size *plane_size,
++		struct plane_size *plane_size,
+ 		enum dc_rotation_angle rotation,
+ 		struct dc_plane_dcc_param *dcc,
+ 		bool horizontal_mirror,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+index da89c2edb07c..7193acfcd779 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+@@ -149,7 +149,7 @@ struct mem_input_funcs {
+ 		struct mem_input *mem_input,
+ 		enum surface_pixel_format format,
+ 		union dc_tiling_info *tiling_info,
+-		union plane_size *plane_size,
++		struct plane_size *plane_size,
+ 		enum dc_rotation_angle rotation,
+ 		struct dc_plane_dcc_param *dcc,
+ 		bool horizontal_mirror);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3080-drm-amd-display-populate-last-calculated-bb-state-wi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3080-drm-amd-display-populate-last-calculated-bb-state-wi.patch
new file mode 100644
index 00000000..efec6b66
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3080-drm-amd-display-populate-last-calculated-bb-state-wi.patch
@@ -0,0 +1,39 @@
+From 2d0db3d83f6b28f613bf5546145f5b57a5b83aca Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Wed, 3 Jul 2019 16:52:38 -0400
+Subject: [PATCH 3080/4256] drm/amd/display: populate last calculated bb state
+ with max clocks
+
+[why]
+update_bounding_box calculates intermediate bb states based on clock relationship
+however, the last state doesn't need to maintain a minimum relationship, but should
+actually contain maximum of every clock.  otherwise maximum clocks are not usable
+
+[how]
+once the calculated bb is built, override the last state with max values
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 296bc7e4c4a2..193270ba60e6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2746,6 +2746,10 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_
+ 		num_calculated_states++;
+ 	}
+ 
++	calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
++	calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
++	calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
++
+ 	memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
+ 	bb->num_states = num_calculated_states;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3081-drm-amd-display-Fix-dc_create-failure-handling-and-6.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3081-drm-amd-display-Fix-dc_create-failure-handling-and-6.patch
new file mode 100644
index 00000000..c7cc95e3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3081-drm-amd-display-Fix-dc_create-failure-handling-and-6.patch
@@ -0,0 +1,60 @@
+From c42bfe5dd7a03dd01309f4fba554f0e21afd1e7e Mon Sep 17 00:00:00 2001
+From: Julian Parkin <julian.parkin@amd.com>
+Date: Tue, 25 Jun 2019 14:55:53 -0400
+Subject: [PATCH 3081/4256] drm/amd/display: Fix dc_create failure handling and
+ 666 color depths
+
+[Why]
+It is possible (but very unlikely) that constructing dc fails
+before current_state is created.
+
+We support 666 color depth in some scenarios, but this
+isn't handled in get_norm_pix_clk. It uses exactly the
+same pixel clock as the 888 case.
+
+[How]
+Check for non null current_state before destructing.
+
+Add case for 666 color depth to get_norm_pix_clk to
+avoid assertion.
+
+Signed-off-by: Julian Parkin <julian.parkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c          | 6 ++++--
+ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 1 +
+ 2 files changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 0b7fbd59cb3b..886fcc1e701f 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -506,8 +506,10 @@ void dc_stream_set_static_screen_events(struct dc *dc,
+ 
+ static void destruct(struct dc *dc)
+ {
+-	dc_release_state(dc->current_state);
+-	dc->current_state = NULL;
++	if (dc->current_state) {
++		dc_release_state(dc->current_state);
++		dc->current_state = NULL;
++	}
+ 
+ 	destroy_links(dc);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 31a49c59c278..c5a740821c0e 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -1852,6 +1852,7 @@ static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
+ 		pix_clk /= 2;
+ 	if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
+ 		switch (timing->display_color_depth) {
++		case COLOR_DEPTH_666:
+ 		case COLOR_DEPTH_888:
+ 			normalized_pix_clk = pix_clk;
+ 			break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3082-drm-amd-display-Only-enable-audio-if-speaker-allocat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3082-drm-amd-display-Only-enable-audio-if-speaker-allocat.patch
new file mode 100644
index 00000000..5f0c42cb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3082-drm-amd-display-Only-enable-audio-if-speaker-allocat.patch
@@ -0,0 +1,41 @@
+From 91970e424c03a6ae1b551929a4de40781452b3e2 Mon Sep 17 00:00:00 2001
+From: Alvin Lee <alvin.lee2@amd.com>
+Date: Thu, 4 Jul 2019 15:17:42 -0400
+Subject: [PATCH 3082/4256] drm/amd/display: Only enable audio if speaker
+ allocation exists
+
+[Why]
+
+In dm_helpers_parse_edid_caps, there is a corner case where no speakers
+can be allocated even though the audio mode count is greater than 0.
+Enabling audio when no speaker allocations exists can cause issues in
+the video stream.
+
+[How]
+
+Add a check to not enable audio unless one or more speaker allocations
+exist (since doing this can cause issues in the video stream).
+
+Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index c5a740821c0e..43bb4c933da7 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -1999,7 +1999,7 @@ enum dc_status resource_map_pool_resources(
+ 	/* TODO: Add check if ASIC support and EDID audio */
+ 	if (!stream->converter_disable_audio &&
+ 	    dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
+-	    stream->audio_info.mode_count) {
++	    stream->audio_info.mode_count && stream->audio_info.flags.all) {
+ 		pipe_ctx->stream_res.audio = find_first_free_audio(
+ 		&context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3083-drm-amd-display-Clean-up-dynamic-metadata-logic.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3083-drm-amd-display-Clean-up-dynamic-metadata-logic.patch
new file mode 100644
index 00000000..3f4ac77d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3083-drm-amd-display-Clean-up-dynamic-metadata-logic.patch
@@ -0,0 +1,218 @@
+From f14a81f2232855ca1cd2f6725846cabdbb977dbe Mon Sep 17 00:00:00 2001
+From: Julian Parkin <julian.parkin@amd.com>
+Date: Wed, 3 Jul 2019 13:59:26 -0400
+Subject: [PATCH 3083/4256] drm/amd/display: Clean up dynamic metadata logic
+
+ [Why]
+Code to enable DCN20 dynamic metadata feature is duplicated in two places
+and was added to DCE110 enable stream.
+
+[How]
+Create DCN20 specific enable stream function for clarity, and add a hardware
+sequencer function to program dynamic metadata to avoid the duplicate
+code.
+
+Signed-off-by: Julian Parkin <julian.parkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_stream.c   | 27 +++----
+ .../display/dc/dce110/dce110_hw_sequencer.c   | 24 +-----
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 74 +++++++++++++++++++
+ .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  1 +
+ 4 files changed, 86 insertions(+), 40 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+index 35d697dd5808..41032c4c5bdf 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+@@ -563,6 +563,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
+ 
+ 	return ret;
+ }
++
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
+ {
+@@ -594,6 +595,14 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc,
+ 	struct hubp *hubp;
+ 	int i;
+ 
++	/* Dynamic metadata is only supported on HDMI or DP */
++	if (!dc_is_hdmi_signal(stream->signal) && !dc_is_dp_signal(stream->signal))
++		return false;
++
++	/* Check hardware support */
++	if (!dc->hwss.program_dmdata_engine)
++		return false;
++
+ 	for (i = 0; i < MAX_PIPES; i++) {
+ 		pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
+ 		if (pipe_ctx->stream == stream)
+@@ -609,23 +618,7 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc,
+ 
+ 	pipe_ctx->stream->dmdata_address = attr->address;
+ 
+-	if (pipe_ctx->stream_res.stream_enc &&
+-			pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata != NULL) {
+-		if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
+-			/* if using dynamic meta, don't set up generic infopackets */
+-			pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
+-			pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata(
+-					pipe_ctx->stream_res.stream_enc,
+-					true, pipe_ctx->plane_res.hubp->inst,
+-					dc_is_dp_signal(pipe_ctx->stream->signal) ?
+-							dmdata_dp : dmdata_hdmi);
+-		} else
+-			pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata(
+-					pipe_ctx->stream_res.stream_enc,
+-					false, pipe_ctx->plane_res.hubp->inst,
+-					dc_is_dp_signal(pipe_ctx->stream->signal) ?
+-							dmdata_dp : dmdata_hdmi);
+-	}
++	dc->hwss.program_dmdata_engine(pipe_ctx);
+ 
+ 	if (hubp->funcs->dmdata_set_attributes != NULL &&
+ 			pipe_ctx->stream->dmdata_address.quad_part != 0) {
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index fedbc6d0c40d..b8ef57a24228 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -664,29 +664,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
+ 	link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
+ 						    pipe_ctx->stream_res.stream_enc->id, true);
+ 
+-	/* update AVI info frame (HDMI, DP)*/
+-	/* TODO: FPGA may change to hwss.update_info_frame */
+-
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+-	if (pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata != NULL &&
+-			pipe_ctx->plane_res.hubp != NULL) {
+-		if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
+-			/* if using dynamic meta, don't set up generic infopackets */
+-			pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
+-			pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata(
+-					pipe_ctx->stream_res.stream_enc,
+-					true, pipe_ctx->plane_res.hubp->inst,
+-					dc_is_dp_signal(pipe_ctx->stream->signal) ?
+-							dmdata_dp : dmdata_hdmi);
+-		} else
+-			pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata(
+-					pipe_ctx->stream_res.stream_enc,
+-					false, pipe_ctx->plane_res.hubp->inst,
+-					dc_is_dp_signal(pipe_ctx->stream->signal) ?
+-							dmdata_dp : dmdata_hdmi);
+-	}
+-#endif
+-	dce110_update_info_frame(pipe_ctx);
++	link->dc->hwss.update_info_frame(pipe_ctx);
+ 
+ 	/* enable early control to avoid corruption on DP monitor*/
+ 	active_total_with_borders =
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index c7c47f2a6e38..e60be115691b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -2058,6 +2058,78 @@ static void dcn20_set_flip_control_gsl(
+ 
+ }
+ 
++static void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
++{
++	enum dc_lane_count lane_count =
++		pipe_ctx->stream->link->cur_link_settings.lane_count;
++
++	struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
++	struct dc_link *link = pipe_ctx->stream->link;
++
++	uint32_t active_total_with_borders;
++	uint32_t early_control = 0;
++	struct timing_generator *tg = pipe_ctx->stream_res.tg;
++
++	/* For MST, there are multiply stream go to only one link.
++	 * connect DIG back_end to front_end while enable_stream and
++	 * disconnect them during disable_stream
++	 * BY this, it is logic clean to separate stream and link
++	 */
++	link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
++						    pipe_ctx->stream_res.stream_enc->id, true);
++
++	if (link->dc->hwss.program_dmdata_engine)
++		link->dc->hwss.program_dmdata_engine(pipe_ctx);
++
++	link->dc->hwss.update_info_frame(pipe_ctx);
++
++	/* enable early control to avoid corruption on DP monitor*/
++	active_total_with_borders =
++			timing->h_addressable
++				+ timing->h_border_left
++				+ timing->h_border_right;
++
++	if (lane_count != 0)
++		early_control = active_total_with_borders % lane_count;
++
++	if (early_control == 0)
++		early_control = lane_count;
++
++	tg->funcs->set_early_control(tg, early_control);
++
++	/* enable audio only within mode set */
++	if (pipe_ctx->stream_res.audio != NULL) {
++		if (dc_is_dp_signal(pipe_ctx->stream->signal))
++			pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
++	}
++}
++
++static void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
++{
++	struct dc_stream_state    *stream     = pipe_ctx->stream;
++	struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
++	bool                       enable     = false;
++	struct stream_encoder     *stream_enc = pipe_ctx->stream_res.stream_enc;
++	enum dynamic_metadata_mode mode       = dc_is_dp_signal(stream->signal)
++							? dmdata_dp
++							: dmdata_hdmi;
++
++	/* if using dynamic meta, don't set up generic infopackets */
++	if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
++		pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
++		enable = true;
++	}
++
++	if (!hubp)
++		return;
++
++	if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
++		return;
++
++	stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
++						hubp->inst, mode);
++}
++
+ void dcn20_hw_sequencer_construct(struct dc *dc)
+ {
+ 	dcn10_hw_sequencer_construct(dc);
+@@ -2082,6 +2154,8 @@ void dcn20_hw_sequencer_construct(struct dc *dc)
+ 	dc->hwss.update_odm = dcn20_update_odm;
+ 	dc->hwss.blank_pixel_data = dcn20_blank_pixel_data;
+ 	dc->hwss.dmdata_status_done = dcn20_dmdata_status_done;
++	dc->hwss.program_dmdata_engine = dcn20_program_dmdata_engine;
++	dc->hwss.enable_stream = dcn20_enable_stream;
+ 	dc->hwss.disable_stream = dcn20_disable_stream;
+ 	dc->hwss.init_sys_ctx = dcn20_init_sys_ctx;
+ 	dc->hwss.init_vm_ctx = dcn20_init_vm_ctx;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index 36be08adae05..28645e10f854 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -231,6 +231,7 @@ struct hw_sequencer_funcs {
+ 	bool (*update_bandwidth)(
+ 			struct dc *dc,
+ 			struct dc_state *context);
++	void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx);
+ 	bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx);
+ #endif
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3084-drm-amd-display-Set-enabled-to-false-at-start-of-aud.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3084-drm-amd-display-Set-enabled-to-false-at-start-of-aud.patch
new file mode 100644
index 00000000..9d144ac6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3084-drm-amd-display-Set-enabled-to-false-at-start-of-aud.patch
@@ -0,0 +1,58 @@
+From e520e3ddd6783feb67e51d81d74f6546906af887 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Wed, 3 Jul 2019 10:02:39 -0400
+Subject: [PATCH 3084/4256] drm/amd/display: Set enabled to false at start of
+ audio disable
+
+[Why]
+In an effort to stop redundant calls to dce110_disable_audio_stream
+the audio->enabled flag was added to the audio resource struct. While
+this state probably shouldn't have been tracked on the audio struct
+itself it still works fine for some sequences.
+
+However, it does not work for cases where we're freeing the audio
+resource (such as hotplugs) or when dynamic audio is enabled.
+
+In these cases the pipe_ctx->stream_res.audio = NULL before we can
+set audio->enabled = false. The next time we acquire the audio resource
+such as on hotplug the audio will not be enabled for the stream since
+DC thinks it's still enabled.
+
+Audio state tracking should cover this sequence.
+
+[How]
+Set audio->enabled = false at the start as long as we have
+pipe_ctx->stream_res.audio.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Zhan Liu <Zhan.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index b8ef57a24228..46dfab749679 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -996,6 +996,8 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
+ 	pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
+ 			pipe_ctx->stream_res.stream_enc, true);
+ 	if (pipe_ctx->stream_res.audio) {
++		pipe_ctx->stream_res.audio->enabled = false;
++
+ 		if (dc->res_pool->pp_smu)
+ 			pp_smu = dc->res_pool->pp_smu;
+ 
+@@ -1026,8 +1028,6 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
+ 		/* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
+ 		 * stream->stream_engine_id);
+ 		 */
+-		if (pipe_ctx->stream_res.audio)
+-			pipe_ctx->stream_res.audio->enabled = false;
+ 	}
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3085-drm-amd-display-drop-ASSERT-if-eDP-panel-is-not-conn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3085-drm-amd-display-drop-ASSERT-if-eDP-panel-is-not-conn.patch
new file mode 100644
index 00000000..44934c0c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3085-drm-amd-display-drop-ASSERT-if-eDP-panel-is-not-conn.patch
@@ -0,0 +1,37 @@
+From 35ee268b577f32dbeeb2af75def50667fd329a9b Mon Sep 17 00:00:00 2001
+From: Zhan Liu <zhan.liu@amd.com>
+Date: Tue, 2 Jul 2019 15:17:07 -0400
+Subject: [PATCH 3085/4256] drm/amd/display: drop ASSERT() if eDP panel is not
+ connected
+
+[Why]
+For boards that support eDP but do not have a physical eDP
+display connected an ASSERT will be thrown. This is not a
+critical failure and shouldn't be treated as such.
+
+[How]
+Drop the assertion.
+
+Signed-off-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index e2f86fd07790..7999c7d3ebc5 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -552,8 +552,6 @@ static void read_edp_current_link_settings_on_detect(struct dc_link *link)
+ 		msleep(8);
+ 	}
+ 
+-	ASSERT(status == DC_OK);
+-
+ 	// Read DPCD 00100h to find if standard link rates are set
+ 	core_link_read_dpcd(link, DP_LINK_BW_SET,
+ 			&link_bw_set, sizeof(link_bw_set));
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3086-drm-amd-display-3.2.42.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3086-drm-amd-display-3.2.42.patch
new file mode 100644
index 00000000..6f661535
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3086-drm-amd-display-3.2.42.patch
@@ -0,0 +1,27 @@
+From da72f676801b99938e45b1bf67714203fad86e36 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Sun, 7 Jul 2019 21:25:35 -0400
+Subject: [PATCH 3086/4256] drm/amd/display: 3.2.42
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index d5ac34f0a511..24320d04f5d1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -42,7 +42,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.41"
++#define DC_VER "3.2.42"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3087-drm-amd-display-Increase-size-of-audios-array.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3087-drm-amd-display-Increase-size-of-audios-array.patch
new file mode 100644
index 00000000..2d8cc014
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3087-drm-amd-display-Increase-size-of-audios-array.patch
@@ -0,0 +1,49 @@
+From 4cdf3ff09a4c1a622c38205f3fca6192b35907da Mon Sep 17 00:00:00 2001
+From: Tai Man <taiman.wong@amd.com>
+Date: Fri, 28 Jun 2019 11:40:38 -0400
+Subject: [PATCH 3087/4256] drm/amd/display: Increase size of audios array
+
+[Why]
+The audios array defined in "struct resource_pool" is only 6 (MAX_PIPES)
+but the max number of audio devices (num_audio) is 7. In some projects,
+it will run out of audios array.
+
+[How]
+Incraese the audios array size to 7.
+
+Signed-off-by: Tai Man <taiman.wong@amd.com>
+Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/inc/core_types.h   | 2 +-
+ drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index c89393c19232..a148ffde8b12 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -212,7 +212,7 @@ struct resource_pool {
+ 	struct clock_source *clock_sources[MAX_CLOCK_SOURCES];
+ 	unsigned int clk_src_count;
+ 
+-	struct audio *audios[MAX_PIPES];
++	struct audio *audios[MAX_AUDIOS];
+ 	unsigned int audio_count;
+ 	struct audio_support audio_support;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+index 8759ec03aede..f82365e2d03c 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+@@ -34,6 +34,7 @@
+  * Data types shared between different Virtual HW blocks
+  ******************************************************************************/
+ 
++#define MAX_AUDIOS 7
+ #define MAX_PIPES 6
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define MAX_DWB_PIPES	1
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3088-drm-amd-display-do-not-read-link-setting-if-edp-not-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3088-drm-amd-display-do-not-read-link-setting-if-edp-not-.patch
new file mode 100644
index 00000000..ccce5137
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3088-drm-amd-display-do-not-read-link-setting-if-edp-not-.patch
@@ -0,0 +1,50 @@
+From 95daef3ffa5067d4eaa0ec63e18e6326c49eef44 Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Sat, 29 Jun 2019 14:38:04 -0400
+Subject: [PATCH 3088/4256] drm/amd/display: do not read link setting if edp
+ not connected
+
+[Why]
+Previously assume eDP sink present if connector present. Do not
+need to enforce this restriction. Fix issue where driver attempt
+to read link setting even though no edp connected.
+
+{How]
+Only read link setting after reading connection status.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 +-------
+ 1 file changed, 1 insertion(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 7999c7d3ebc5..333ce7a5d89c 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -720,13 +720,6 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
+ 		return false;
+ 	}
+ 
+-	if (link->connector_signal == SIGNAL_TYPE_EDP) {
+-		/* On detect, we want to make sure current link settings are
+-		 * up to date, especially if link was powered on by GOP.
+-		 */
+-		read_edp_current_link_settings_on_detect(link);
+-	}
+-
+ 	prev_sink = link->local_sink;
+ 	if (prev_sink != NULL) {
+ 		dc_sink_retain(prev_sink);
+@@ -768,6 +761,7 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
+ 		}
+ 
+ 		case SIGNAL_TYPE_EDP: {
++			read_edp_current_link_settings_on_detect(link);
+ 			detect_edp_sink_caps(link);
+ 			sink_caps.transaction_type =
+ 				DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3089-drm-amd-display-fix-mpcc-assert-condition.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3089-drm-amd-display-fix-mpcc-assert-condition.patch
new file mode 100644
index 00000000..a77ad874
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3089-drm-amd-display-fix-mpcc-assert-condition.patch
@@ -0,0 +1,63 @@
+From 5d910719753531aef80d869d66a81e580ca51df3 Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Sat, 29 Jun 2019 16:02:37 -0400
+Subject: [PATCH 3089/4256] drm/amd/display: fix mpcc assert condition
+
+[Why]
+In DCN2x asic, the MPCC status register definition changed, and
+our logic for assert is incorrect. disabled is valid state,
+where we should see idle and not busy, where as in not
+disabled state, we should see not idle.
+
+[How]
+Change assert condition to be more sensible.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c  | 23 +++++++++----------
+ 1 file changed, 11 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+index f4d3008e5efa..67f0128f0b38 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+@@ -446,23 +446,22 @@ void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)
+ {
+ 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
+ 	unsigned int top_sel, mpc_busy, mpc_idle, mpc_disabled;
+-	REG_GET(MPCC_STATUS[mpcc_id], MPCC_DISABLED, &mpc_disabled);
+-
+-	if (mpc_disabled) {
+-		ASSERT(0);
+-		return;
+-	}
+ 
+ 	REG_GET(MPCC_TOP_SEL[mpcc_id],
+ 			MPCC_TOP_SEL, &top_sel);
+ 
+-	if (top_sel == 0xf) {
+-		REG_GET_2(MPCC_STATUS[mpcc_id],
+-				MPCC_BUSY, &mpc_busy,
+-				MPCC_IDLE, &mpc_idle);
++	REG_GET_3(MPCC_STATUS[mpcc_id],
++			MPCC_BUSY, &mpc_busy,
++			MPCC_IDLE, &mpc_idle,
++			MPCC_DISABLED, &mpc_disabled);
+ 
+-		ASSERT(mpc_busy == 0);
+-		ASSERT(mpc_idle == 1);
++	if (top_sel == 0xf) {
++		ASSERT(!mpc_busy);
++		ASSERT(mpc_idle);
++		ASSERT(mpc_disabled);
++	} else {
++		ASSERT(!mpc_disabled);
++		ASSERT(!mpc_idle);
+ 	}
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3090-drm-amd-display-support-dummy-pstate.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3090-drm-amd-display-support-dummy-pstate.patch
new file mode 100644
index 00000000..992d3920
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3090-drm-amd-display-support-dummy-pstate.patch
@@ -0,0 +1,7283 @@
+From e1e58ece64ca912cda59f58f4b0a4037d5cdbe08 Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Mon, 8 Jul 2019 15:15:42 -0400
+Subject: [PATCH 3090/4256] drm/amd/display: support "dummy pstate"
+
+[why]
+Existing support in DC for pstate only accounts for a single latency.  This is sufficient when the
+variance of latency is small, or that pstate support isn't necessary for correct ASIC functionality.
+
+Newer ASICs violate both existing assumptions.  PState support is mandatory of correct ASIC
+functionality, but not all latencies have to be supported.  Existing code supports a "full p state" which
+allows memory clock to change, but is hard for DCN to support (as it requires very large buffers).
+New code will now fall back to a "dummy p state" support when "full p state" cannot be support.
+This easy p state support should always be allowed.
+
+[how]
+Define a new latency in socBB.  Add fallback logic to support it.  Note DML is also updated to ensure
+that fallback will always work.
+
+Change-Id: I068e34cae8fa2f7cd31b530a68822c479525048c
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  |    2 +
+ drivers/gpu/drm/amd/display/dc/dc.h           |    7 +
+ .../drm/amd/display/dc/dcn20/dcn20_hubbub.c   |   11 +
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |   10 +-
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c |   59 +-
+ drivers/gpu/drm/amd/display/dc/dml/Makefile   |    3 +
+ .../dc/dml/dcn20/display_mode_vba_20v2.c      | 5109 +++++++++++++++++
+ .../dc/dml/dcn20/display_mode_vba_20v2.h      |   32 +
+ .../dc/dml/dcn20/display_rq_dlg_calc_20v2.c   | 1701 ++++++
+ .../dc/dml/dcn20/display_rq_dlg_calc_20v2.h   |   74 +
+ .../drm/amd/display/dc/dml/display_mode_lib.c |   12 +
+ .../drm/amd/display/dc/dml/display_mode_lib.h |    1 +
+ .../amd/display/dc/dml/display_mode_structs.h |    1 +
+ .../drm/amd/display/dc/dml/display_mode_vba.c |    8 +-
+ 14 files changed, 7022 insertions(+), 8 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index 3cff4f0518d3..7ff0396956b3 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -201,6 +201,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+ 	}
+ 
+ 	if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
++		clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
+ 		clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support;
+ 		if (pp_smu && pp_smu->set_pstate_handshake_support)
+ 			pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);
+@@ -308,6 +309,7 @@ void dcn2_init_clocks(struct clk_mgr *clk_mgr)
+ 	memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
+ 	// Assumption is that boot state always supports pstate
+ 	clk_mgr->clks.p_state_change_support = true;
++	clk_mgr->clks.prev_p_state_change_support = true;
+ }
+ 
+ void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 24320d04f5d1..8d890468908f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -124,6 +124,7 @@ struct dc_caps {
+ struct dc_bug_wa {
+ 	bool no_connect_phy_config;
+ 	bool dedcn20_305_wa;
++	struct display_mode_lib alternate_dml;
+ };
+ #endif
+ 
+@@ -266,6 +267,12 @@ struct dc_clocks {
+ 	int phyclk_khz;
+ 	int dramclk_khz;
+ 	bool p_state_change_support;
++
++	/*
++	 * Elements below are not compared for the purposes of
++	 * optimization required
++	 */
++	bool prev_p_state_change_support;
+ };
+ 
+ struct dc_bw_validation_profile {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+index 6e2dbd03f9bf..31d6e79ba2b8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+@@ -26,6 +26,7 @@
+ 
+ #include "dcn20_hubbub.h"
+ #include "reg_helper.h"
++#include "clk_mgr.h"
+ 
+ #define REG(reg)\
+ 	hubbub1->regs->reg
+@@ -553,6 +554,16 @@ static void hubbub2_program_watermarks(
+ 	 */
+ 	hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
+ 	hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
++
++	/*
++	 * There's a special case when going from p-state support to p-state unsupported
++	 * here we are going to LOWER watermarks to go to dummy p-state only, but this has
++	 * to be done prepare_bandwidth, not optimize
++	 */
++	if (hubbub1->base.ctx->dc->clk_mgr->clks.prev_p_state_change_support == true &&
++		hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false)
++		safe_to_lower = true;
++
+ 	hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
+ 
+ 	REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index e60be115691b..08a96faef775 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1445,16 +1445,16 @@ void dcn20_prepare_bandwidth(
+ {
+ 	struct hubbub *hubbub = dc->res_pool->hubbub;
+ 
++	dc->clk_mgr->funcs->update_clocks(
++			dc->clk_mgr,
++			context,
++			false);
++
+ 	/* program dchubbub watermarks */
+ 	hubbub->funcs->program_watermarks(hubbub,
+ 					&context->bw_ctx.bw.dcn.watermarks,
+ 					dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
+ 					false);
+-
+-	dc->clk_mgr->funcs->update_clocks(
+-			dc->clk_mgr,
+-			context,
+-			false);
+ }
+ 
+ void dcn20_optimize_bandwidth(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 193270ba60e6..2cf788a3704e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2425,7 +2425,7 @@ void dcn20_calculate_dlg_params(
+ 	}
+ }
+ 
+-bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
++static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
+ 		bool fast_validate)
+ {
+ 	bool out = false;
+@@ -2477,6 +2477,62 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
+ 	return out;
+ }
+ 
++
++bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
++		bool fast_validate)
++{
++	bool voltage_supported = false;
++	bool full_pstate_supported = false;
++	bool dummy_pstate_supported = false;
++	double p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
++
++	if (fast_validate)
++		return dcn20_validate_bandwidth_internal(dc, context, true);
++
++
++	// Best case, we support full UCLK switch latency
++	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
++	full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
++
++	if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
++		(voltage_supported && full_pstate_supported)) {
++		context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
++		goto restore_dml_state;
++	}
++
++	// Fallback #1: Try to only support G6 temperature read latency
++	context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
++
++	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
++	dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
++
++	if (voltage_supported && dummy_pstate_supported) {
++		context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
++		goto restore_dml_state;
++	}
++
++	// Fallback #2: Retry with "new" DCN20 to support G6 temperature read latency
++	memcpy (&context->bw_ctx.dml, &dc->work_arounds.alternate_dml, sizeof (struct display_mode_lib));
++	context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
++
++	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
++	dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
++
++	if (voltage_supported && dummy_pstate_supported) {
++		context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
++		goto restore_dml_state;
++	}
++
++	// ERROR: fallback #2 is supposed to always work.
++	ASSERT(false);
++
++restore_dml_state:
++	memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
++	context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
++
++	return voltage_supported;
++}
++
+ struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
+ 		struct dc_state *state,
+ 		const struct resource_pool *pool,
+@@ -3073,6 +3129,7 @@ static bool construct(
+ 	}
+ 
+ 	dml_init_instance(&dc->dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10);
++	dml_init_instance(&dc->work_arounds.alternate_dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10v2);
+ 
+ 	if (!dc->debug.disable_pplib_wm_range) {
+ 		struct pp_smu_wm_range_sets ranges = {0};
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+index 0bb7a20675c4..1735fc1e2eb1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+@@ -38,6 +38,8 @@ ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ CFLAGS_display_mode_vba.o := $(dml_ccflags)
+ CFLAGS_display_mode_vba_20.o := $(dml_ccflags)
+ CFLAGS_display_rq_dlg_calc_20.o := $(dml_ccflags)
++CFLAGS_display_mode_vba_20v2.o := $(dml_ccflags)
++CFLAGS_display_rq_dlg_calc_20v2.o := $(dml_ccflags)
+ endif
+ ifdef CONFIG_DRM_AMD_DCN3AG
+ CFLAGS_display_mode_vba_3ag.o := $(dml_ccflags)
+@@ -51,6 +53,7 @@ DML = display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
+ 
+ ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_20.o
++DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o
+ endif
+ 
+ AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+new file mode 100644
+index 000000000000..22455db54980
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+@@ -0,0 +1,5109 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "../display_mode_lib.h"
++#include "display_mode_vba_20v2.h"
++#include "../dml_inline_defs.h"
++
++/*
++ * NOTE:
++ *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
++ *
++ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
++ * ways. Unless there is something clearly wrong with it the code should
++ * remain as-is as it provides us with a guarantee from HW that it is correct.
++ */
++
++#define BPP_INVALID 0
++#define BPP_BLENDED_PIPE 0xffffffff
++
++static double adjust_ReturnBW(
++		struct display_mode_lib *mode_lib,
++		double ReturnBW,
++		bool DCCEnabledAnyPlane,
++		double ReturnBandwidthToDCN);
++static unsigned int dscceComputeDelay(
++		unsigned int bpc,
++		double bpp,
++		unsigned int sliceWidth,
++		unsigned int numSlices,
++		enum output_format_class pixelFormat);
++static unsigned int dscComputeDelay(enum output_format_class pixelFormat);
++static bool CalculateDelayAfterScaler(
++		struct display_mode_lib *mode_lib,
++		double ReturnBW,
++		double ReadBandwidthPlaneLuma,
++		double ReadBandwidthPlaneChroma,
++		double TotalDataReadBandwidth,
++		double DisplayPipeLineDeliveryTimeLuma,
++		double DisplayPipeLineDeliveryTimeChroma,
++		double DPPCLK,
++		double DISPCLK,
++		double PixelClock,
++		unsigned int DSCDelay,
++		unsigned int DPPPerPlane,
++		bool ScalerEnabled,
++		unsigned int NumberOfCursors,
++		double DPPCLKDelaySubtotal,
++		double DPPCLKDelaySCL,
++		double DPPCLKDelaySCLLBOnly,
++		double DPPCLKDelayCNVCFormater,
++		double DPPCLKDelayCNVCCursor,
++		double DISPCLKDelaySubtotal,
++		unsigned int ScalerRecoutWidth,
++		enum output_format_class OutputFormat,
++		unsigned int HTotal,
++		unsigned int SwathWidthSingleDPPY,
++		double BytePerPixelDETY,
++		double BytePerPixelDETC,
++		unsigned int SwathHeightY,
++		unsigned int SwathHeightC,
++		bool Interlace,
++		bool ProgressiveToInterlaceUnitInOPP,
++		double *DSTXAfterScaler,
++		double *DSTYAfterScaler
++		);
++// Super monster function with some 45 argument
++static bool CalculatePrefetchSchedule(
++		struct display_mode_lib *mode_lib,
++		double DPPCLK,
++		double DISPCLK,
++		double PixelClock,
++		double DCFCLKDeepSleep,
++		unsigned int DPPPerPlane,
++		unsigned int NumberOfCursors,
++		unsigned int VBlank,
++		unsigned int HTotal,
++		unsigned int MaxInterDCNTileRepeaters,
++		unsigned int VStartup,
++		unsigned int PageTableLevels,
++		bool GPUVMEnable,
++		bool DynamicMetadataEnable,
++		unsigned int DynamicMetadataLinesBeforeActiveRequired,
++		unsigned int DynamicMetadataTransmittedBytes,
++		bool DCCEnable,
++		double UrgentLatencyPixelDataOnly,
++		double UrgentExtraLatency,
++		double TCalc,
++		unsigned int PDEAndMetaPTEBytesFrame,
++		unsigned int MetaRowByte,
++		unsigned int PixelPTEBytesPerRow,
++		double PrefetchSourceLinesY,
++		unsigned int SwathWidthY,
++		double BytePerPixelDETY,
++		double VInitPreFillY,
++		unsigned int MaxNumSwathY,
++		double PrefetchSourceLinesC,
++		double BytePerPixelDETC,
++		double VInitPreFillC,
++		unsigned int MaxNumSwathC,
++		unsigned int SwathHeightY,
++		unsigned int SwathHeightC,
++		double TWait,
++		bool XFCEnabled,
++		double XFCRemoteSurfaceFlipDelay,
++		bool InterlaceEnable,
++		bool ProgressiveToInterlaceUnitInOPP,
++		double DSTXAfterScaler,
++		double DSTYAfterScaler,
++		double *DestinationLinesForPrefetch,
++		double *PrefetchBandwidth,
++		double *DestinationLinesToRequestVMInVBlank,
++		double *DestinationLinesToRequestRowInVBlank,
++		double *VRatioPrefetchY,
++		double *VRatioPrefetchC,
++		double *RequiredPrefetchPixDataBW,
++		double *Tno_bw,
++		unsigned int *VUpdateOffsetPix,
++		double *VUpdateWidthPix,
++		double *VReadyOffsetPix);
++static double RoundToDFSGranularityUp(double Clock, double VCOSpeed);
++static double RoundToDFSGranularityDown(double Clock, double VCOSpeed);
++static double CalculatePrefetchSourceLines(
++		struct display_mode_lib *mode_lib,
++		double VRatio,
++		double vtaps,
++		bool Interlace,
++		bool ProgressiveToInterlaceUnitInOPP,
++		unsigned int SwathHeight,
++		unsigned int ViewportYStart,
++		double *VInitPreFill,
++		unsigned int *MaxNumSwath);
++static unsigned int CalculateVMAndRowBytes(
++		struct display_mode_lib *mode_lib,
++		bool DCCEnable,
++		unsigned int BlockHeight256Bytes,
++		unsigned int BlockWidth256Bytes,
++		enum source_format_class SourcePixelFormat,
++		unsigned int SurfaceTiling,
++		unsigned int BytePerPixel,
++		enum scan_direction_class ScanDirection,
++		unsigned int ViewportWidth,
++		unsigned int ViewportHeight,
++		unsigned int SwathWidthY,
++		bool GPUVMEnable,
++		unsigned int VMMPageSize,
++		unsigned int PTEBufferSizeInRequestsLuma,
++		unsigned int PDEProcessingBufIn64KBReqs,
++		unsigned int Pitch,
++		unsigned int DCCMetaPitch,
++		unsigned int *MacroTileWidth,
++		unsigned int *MetaRowByte,
++		unsigned int *PixelPTEBytesPerRow,
++		bool *PTEBufferSizeNotExceeded,
++		unsigned int *dpte_row_height,
++		unsigned int *meta_row_height);
++static double CalculateTWait(
++		unsigned int PrefetchMode,
++		double DRAMClockChangeLatency,
++		double UrgentLatencyPixelDataOnly,
++		double SREnterPlusExitTime);
++static double CalculateRemoteSurfaceFlipDelay(
++		struct display_mode_lib *mode_lib,
++		double VRatio,
++		double SwathWidth,
++		double Bpp,
++		double LineTime,
++		double XFCTSlvVupdateOffset,
++		double XFCTSlvVupdateWidth,
++		double XFCTSlvVreadyOffset,
++		double XFCXBUFLatencyTolerance,
++		double XFCFillBWOverhead,
++		double XFCSlvChunkSize,
++		double XFCBusTransportTime,
++		double TCalc,
++		double TWait,
++		double *SrcActiveDrainRate,
++		double *TInitXFill,
++		double *TslvChk);
++static void CalculateActiveRowBandwidth(
++		bool GPUVMEnable,
++		enum source_format_class SourcePixelFormat,
++		double VRatio,
++		bool DCCEnable,
++		double LineTime,
++		unsigned int MetaRowByteLuma,
++		unsigned int MetaRowByteChroma,
++		unsigned int meta_row_height_luma,
++		unsigned int meta_row_height_chroma,
++		unsigned int PixelPTEBytesPerRowLuma,
++		unsigned int PixelPTEBytesPerRowChroma,
++		unsigned int dpte_row_height_luma,
++		unsigned int dpte_row_height_chroma,
++		double *meta_row_bw,
++		double *dpte_row_bw,
++		double *qual_row_bw);
++static void CalculateFlipSchedule(
++		struct display_mode_lib *mode_lib,
++		double UrgentExtraLatency,
++		double UrgentLatencyPixelDataOnly,
++		unsigned int GPUVMMaxPageTableLevels,
++		bool GPUVMEnable,
++		double BandwidthAvailableForImmediateFlip,
++		unsigned int TotImmediateFlipBytes,
++		enum source_format_class SourcePixelFormat,
++		unsigned int ImmediateFlipBytes,
++		double LineTime,
++		double VRatio,
++		double Tno_bw,
++		double PDEAndMetaPTEBytesFrame,
++		unsigned int MetaRowByte,
++		unsigned int PixelPTEBytesPerRow,
++		bool DCCEnable,
++		unsigned int dpte_row_height,
++		unsigned int meta_row_height,
++		double qual_row_bw,
++		double *DestinationLinesToRequestVMInImmediateFlip,
++		double *DestinationLinesToRequestRowInImmediateFlip,
++		double *final_flip_bw,
++		bool *ImmediateFlipSupportedForPipe);
++static double CalculateWriteBackDelay(
++		enum source_format_class WritebackPixelFormat,
++		double WritebackHRatio,
++		double WritebackVRatio,
++		unsigned int WritebackLumaHTaps,
++		unsigned int WritebackLumaVTaps,
++		unsigned int WritebackChromaHTaps,
++		unsigned int WritebackChromaVTaps,
++		unsigned int WritebackDestinationWidth);
++
++static void dml20v2_DisplayPipeConfiguration(struct display_mode_lib *mode_lib);
++static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
++		struct display_mode_lib *mode_lib);
++
++void dml20v2_recalculate(struct display_mode_lib *mode_lib)
++{
++	ModeSupportAndSystemConfiguration(mode_lib);
++	mode_lib->vba.FabricAndDRAMBandwidth = dml_min(
++		mode_lib->vba.DRAMSpeed * mode_lib->vba.NumberOfChannels * mode_lib->vba.DRAMChannelWidth,
++		mode_lib->vba.FabricClock * mode_lib->vba.FabricDatapathToDCNDataReturn) / 1000.0;
++	PixelClockAdjustmentForProgressiveToInterlaceUnit(mode_lib);
++	dml20v2_DisplayPipeConfiguration(mode_lib);
++	dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(mode_lib);
++}
++
++static double adjust_ReturnBW(
++		struct display_mode_lib *mode_lib,
++		double ReturnBW,
++		bool DCCEnabledAnyPlane,
++		double ReturnBandwidthToDCN)
++{
++	double CriticalCompression;
++
++	if (DCCEnabledAnyPlane
++			&& ReturnBandwidthToDCN
++					> mode_lib->vba.DCFCLK * mode_lib->vba.ReturnBusWidth / 4.0)
++		ReturnBW =
++				dml_min(
++						ReturnBW,
++						ReturnBandwidthToDCN * 4
++								* (1.0
++										- mode_lib->vba.UrgentLatencyPixelDataOnly
++												/ ((mode_lib->vba.ROBBufferSizeInKByte
++														- mode_lib->vba.PixelChunkSizeInKByte)
++														* 1024
++														/ ReturnBandwidthToDCN
++														- mode_lib->vba.DCFCLK
++																* mode_lib->vba.ReturnBusWidth
++																/ 4)
++										+ mode_lib->vba.UrgentLatencyPixelDataOnly));
++
++	CriticalCompression = 2.0 * mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLK
++			* mode_lib->vba.UrgentLatencyPixelDataOnly
++			/ (ReturnBandwidthToDCN * mode_lib->vba.UrgentLatencyPixelDataOnly
++					+ (mode_lib->vba.ROBBufferSizeInKByte
++							- mode_lib->vba.PixelChunkSizeInKByte)
++							* 1024);
++
++	if (DCCEnabledAnyPlane && CriticalCompression > 1.0 && CriticalCompression < 4.0)
++		ReturnBW =
++				dml_min(
++						ReturnBW,
++						4.0 * ReturnBandwidthToDCN
++								* (mode_lib->vba.ROBBufferSizeInKByte
++										- mode_lib->vba.PixelChunkSizeInKByte)
++								* 1024
++								* mode_lib->vba.ReturnBusWidth
++								* mode_lib->vba.DCFCLK
++								* mode_lib->vba.UrgentLatencyPixelDataOnly
++								/ dml_pow(
++										(ReturnBandwidthToDCN
++												* mode_lib->vba.UrgentLatencyPixelDataOnly
++												+ (mode_lib->vba.ROBBufferSizeInKByte
++														- mode_lib->vba.PixelChunkSizeInKByte)
++														* 1024),
++										2));
++
++	return ReturnBW;
++}
++
++static unsigned int dscceComputeDelay(
++		unsigned int bpc,
++		double bpp,
++		unsigned int sliceWidth,
++		unsigned int numSlices,
++		enum output_format_class pixelFormat)
++{
++	// valid bpc         = source bits per component in the set of {8, 10, 12}
++	// valid bpp         = increments of 1/16 of a bit
++	//                    min = 6/7/8 in N420/N422/444, respectively
++	//                    max = such that compression is 1:1
++	//valid sliceWidth  = number of pixels per slice line, must be less than or equal to 5184/numSlices (or 4096/numSlices in 420 mode)
++	//valid numSlices   = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4}
++	//valid pixelFormat = pixel/color format in the set of {:N444_RGB, :S422, :N422, :N420}
++
++	// fixed value
++	unsigned int rcModelSize = 8192;
++
++	// N422/N420 operate at 2 pixels per clock
++	unsigned int pixelsPerClock, lstall, D, initalXmitDelay, w, s, ix, wx, p, l0, a, ax, l,
++			Delay, pixels;
++
++	if (pixelFormat == dm_n422 || pixelFormat == dm_420)
++		pixelsPerClock = 2;
++	// #all other modes operate at 1 pixel per clock
++	else
++		pixelsPerClock = 1;
++
++	//initial transmit delay as per PPS
++	initalXmitDelay = dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock);
++
++	//compute ssm delay
++	if (bpc == 8)
++		D = 81;
++	else if (bpc == 10)
++		D = 89;
++	else
++		D = 113;
++
++	//divide by pixel per cycle to compute slice width as seen by DSC
++	w = sliceWidth / pixelsPerClock;
++
++	//422 mode has an additional cycle of delay
++	if (pixelFormat == dm_s422)
++		s = 1;
++	else
++		s = 0;
++
++	//main calculation for the dscce
++	ix = initalXmitDelay + 45;
++	wx = (w + 2) / 3;
++	p = 3 * wx - w;
++	l0 = ix / w;
++	a = ix + p * l0;
++	ax = (a + 2) / 3 + D + 6 + 1;
++	l = (ax + wx - 1) / wx;
++	if ((ix % w) == 0 && p != 0)
++		lstall = 1;
++	else
++		lstall = 0;
++	Delay = l * wx * (numSlices - 1) + ax + s + lstall + 22;
++
++	//dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels
++	pixels = Delay * 3 * pixelsPerClock;
++	return pixels;
++}
++
++static unsigned int dscComputeDelay(enum output_format_class pixelFormat)
++{
++	unsigned int Delay = 0;
++
++	if (pixelFormat == dm_420) {
++		//   sfr
++		Delay = Delay + 2;
++		//   dsccif
++		Delay = Delay + 0;
++		//   dscc - input deserializer
++		Delay = Delay + 3;
++		//   dscc gets pixels every other cycle
++		Delay = Delay + 2;
++		//   dscc - input cdc fifo
++		Delay = Delay + 12;
++		//   dscc gets pixels every other cycle
++		Delay = Delay + 13;
++		//   dscc - cdc uncertainty
++		Delay = Delay + 2;
++		//   dscc - output cdc fifo
++		Delay = Delay + 7;
++		//   dscc gets pixels every other cycle
++		Delay = Delay + 3;
++		//   dscc - cdc uncertainty
++		Delay = Delay + 2;
++		//   dscc - output serializer
++		Delay = Delay + 1;
++		//   sft
++		Delay = Delay + 1;
++	} else if (pixelFormat == dm_n422) {
++		//   sfr
++		Delay = Delay + 2;
++		//   dsccif
++		Delay = Delay + 1;
++		//   dscc - input deserializer
++		Delay = Delay + 5;
++		//  dscc - input cdc fifo
++		Delay = Delay + 25;
++		//   dscc - cdc uncertainty
++		Delay = Delay + 2;
++		//   dscc - output cdc fifo
++		Delay = Delay + 10;
++		//   dscc - cdc uncertainty
++		Delay = Delay + 2;
++		//   dscc - output serializer
++		Delay = Delay + 1;
++		//   sft
++		Delay = Delay + 1;
++	} else {
++		//   sfr
++		Delay = Delay + 2;
++		//   dsccif
++		Delay = Delay + 0;
++		//   dscc - input deserializer
++		Delay = Delay + 3;
++		//   dscc - input cdc fifo
++		Delay = Delay + 12;
++		//   dscc - cdc uncertainty
++		Delay = Delay + 2;
++		//   dscc - output cdc fifo
++		Delay = Delay + 7;
++		//   dscc - output serializer
++		Delay = Delay + 1;
++		//   dscc - cdc uncertainty
++		Delay = Delay + 2;
++		//   sft
++		Delay = Delay + 1;
++	}
++
++	return Delay;
++}
++
++static bool CalculateDelayAfterScaler(
++		struct display_mode_lib *mode_lib,
++		double ReturnBW,
++		double ReadBandwidthPlaneLuma,
++		double ReadBandwidthPlaneChroma,
++		double TotalDataReadBandwidth,
++		double DisplayPipeLineDeliveryTimeLuma,
++		double DisplayPipeLineDeliveryTimeChroma,
++		double DPPCLK,
++		double DISPCLK,
++		double PixelClock,
++		unsigned int DSCDelay,
++		unsigned int DPPPerPlane,
++		bool ScalerEnabled,
++		unsigned int NumberOfCursors,
++		double DPPCLKDelaySubtotal,
++		double DPPCLKDelaySCL,
++		double DPPCLKDelaySCLLBOnly,
++		double DPPCLKDelayCNVCFormater,
++		double DPPCLKDelayCNVCCursor,
++		double DISPCLKDelaySubtotal,
++		unsigned int ScalerRecoutWidth,
++		enum output_format_class OutputFormat,
++		unsigned int HTotal,
++		unsigned int SwathWidthSingleDPPY,
++		double BytePerPixelDETY,
++		double BytePerPixelDETC,
++		unsigned int SwathHeightY,
++		unsigned int SwathHeightC,
++		bool Interlace,
++		bool ProgressiveToInterlaceUnitInOPP,
++		double *DSTXAfterScaler,
++		double *DSTYAfterScaler
++		)
++{
++	unsigned int DPPCycles, DISPCLKCycles;
++	double DataFabricLineDeliveryTimeLuma;
++	double DataFabricLineDeliveryTimeChroma;
++	double DSTTotalPixelsAfterScaler;
++
++	DataFabricLineDeliveryTimeLuma = SwathWidthSingleDPPY * SwathHeightY * dml_ceil(BytePerPixelDETY, 1) / (mode_lib->vba.ReturnBW * ReadBandwidthPlaneLuma / TotalDataReadBandwidth);
++	mode_lib->vba.LastPixelOfLineExtraWatermark = dml_max(mode_lib->vba.LastPixelOfLineExtraWatermark, DataFabricLineDeliveryTimeLuma - DisplayPipeLineDeliveryTimeLuma);
++
++	if (BytePerPixelDETC != 0) {
++		DataFabricLineDeliveryTimeChroma = SwathWidthSingleDPPY / 2 * SwathHeightC * dml_ceil(BytePerPixelDETC, 2) / (mode_lib->vba.ReturnBW * ReadBandwidthPlaneChroma / TotalDataReadBandwidth);
++		mode_lib->vba.LastPixelOfLineExtraWatermark = dml_max(mode_lib->vba.LastPixelOfLineExtraWatermark, DataFabricLineDeliveryTimeChroma - DisplayPipeLineDeliveryTimeChroma);
++	}
++
++	if (ScalerEnabled)
++		DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCL;
++	else
++		DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly;
++
++	DPPCycles = DPPCycles + DPPCLKDelayCNVCFormater + NumberOfCursors * DPPCLKDelayCNVCCursor;
++
++	DISPCLKCycles = DISPCLKDelaySubtotal;
++
++	if (DPPCLK == 0.0 || DISPCLK == 0.0)
++		return true;
++
++	*DSTXAfterScaler = DPPCycles * PixelClock / DPPCLK + DISPCLKCycles * PixelClock / DISPCLK
++			+ DSCDelay;
++
++	if (DPPPerPlane > 1)
++		*DSTXAfterScaler = *DSTXAfterScaler + ScalerRecoutWidth;
++
++	if (OutputFormat == dm_420 || (Interlace && ProgressiveToInterlaceUnitInOPP))
++		*DSTYAfterScaler = 1;
++	else
++		*DSTYAfterScaler = 0;
++
++	DSTTotalPixelsAfterScaler = ((double) (*DSTYAfterScaler * HTotal)) + *DSTXAfterScaler;
++	*DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / HTotal, 1);
++	*DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * HTotal));
++
++	return true;
++}
++
++static bool CalculatePrefetchSchedule(
++		struct display_mode_lib *mode_lib,
++		double DPPCLK,
++		double DISPCLK,
++		double PixelClock,
++		double DCFCLKDeepSleep,
++		unsigned int DPPPerPlane,
++		unsigned int NumberOfCursors,
++		unsigned int VBlank,
++		unsigned int HTotal,
++		unsigned int MaxInterDCNTileRepeaters,
++		unsigned int VStartup,
++		unsigned int PageTableLevels,
++		bool GPUVMEnable,
++		bool DynamicMetadataEnable,
++		unsigned int DynamicMetadataLinesBeforeActiveRequired,
++		unsigned int DynamicMetadataTransmittedBytes,
++		bool DCCEnable,
++		double UrgentLatencyPixelDataOnly,
++		double UrgentExtraLatency,
++		double TCalc,
++		unsigned int PDEAndMetaPTEBytesFrame,
++		unsigned int MetaRowByte,
++		unsigned int PixelPTEBytesPerRow,
++		double PrefetchSourceLinesY,
++		unsigned int SwathWidthY,
++		double BytePerPixelDETY,
++		double VInitPreFillY,
++		unsigned int MaxNumSwathY,
++		double PrefetchSourceLinesC,
++		double BytePerPixelDETC,
++		double VInitPreFillC,
++		unsigned int MaxNumSwathC,
++		unsigned int SwathHeightY,
++		unsigned int SwathHeightC,
++		double TWait,
++		bool XFCEnabled,
++		double XFCRemoteSurfaceFlipDelay,
++		bool InterlaceEnable,
++		bool ProgressiveToInterlaceUnitInOPP,
++		double DSTXAfterScaler,
++		double DSTYAfterScaler,
++		double *DestinationLinesForPrefetch,
++		double *PrefetchBandwidth,
++		double *DestinationLinesToRequestVMInVBlank,
++		double *DestinationLinesToRequestRowInVBlank,
++		double *VRatioPrefetchY,
++		double *VRatioPrefetchC,
++		double *RequiredPrefetchPixDataBW,
++		double *Tno_bw,
++		unsigned int *VUpdateOffsetPix,
++		double *VUpdateWidthPix,
++		double *VReadyOffsetPix)
++{
++	bool MyError = false;
++	double TotalRepeaterDelayTime;
++	double Tdm, LineTime, Tsetup;
++	double dst_y_prefetch_equ;
++	double Tsw_oto;
++	double prefetch_bw_oto;
++	double Tvm_oto;
++	double Tr0_oto;
++	double Tpre_oto;
++	double dst_y_prefetch_oto;
++	double TimeForFetchingMetaPTE = 0;
++	double TimeForFetchingRowInVBlank = 0;
++	double LinesToRequestPrefetchPixelData = 0;
++
++	*VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1);
++	TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / DPPCLK + 3.0 / DISPCLK);
++	*VUpdateWidthPix = (14.0 / DCFCLKDeepSleep + 12.0 / DPPCLK + TotalRepeaterDelayTime)
++			* PixelClock;
++
++	*VReadyOffsetPix = dml_max(
++			150.0 / DPPCLK,
++			TotalRepeaterDelayTime + 20.0 / DCFCLKDeepSleep + 10.0 / DPPCLK)
++			* PixelClock;
++
++	Tsetup = (double) (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / PixelClock;
++
++	LineTime = (double) HTotal / PixelClock;
++
++	if (DynamicMetadataEnable) {
++		double Tdmbf, Tdmec, Tdmsks;
++
++		Tdm = dml_max(0.0, UrgentExtraLatency - TCalc);
++		Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK;
++		Tdmec = LineTime;
++		if (DynamicMetadataLinesBeforeActiveRequired == 0)
++			Tdmsks = VBlank * LineTime / 2.0;
++		else
++			Tdmsks = DynamicMetadataLinesBeforeActiveRequired * LineTime;
++		if (InterlaceEnable && !ProgressiveToInterlaceUnitInOPP)
++			Tdmsks = Tdmsks / 2;
++		if (VStartup * LineTime
++				< Tsetup + TWait + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) {
++			MyError = true;
++		}
++	} else
++		Tdm = 0;
++
++	if (GPUVMEnable) {
++		if (PageTableLevels == 4)
++			*Tno_bw = UrgentExtraLatency + UrgentLatencyPixelDataOnly;
++		else if (PageTableLevels == 3)
++			*Tno_bw = UrgentExtraLatency;
++		else
++			*Tno_bw = 0;
++	} else if (DCCEnable)
++		*Tno_bw = LineTime;
++	else
++		*Tno_bw = LineTime / 4;
++
++	dst_y_prefetch_equ = VStartup - dml_max(TCalc + TWait, XFCRemoteSurfaceFlipDelay) / LineTime
++			- (Tsetup + Tdm) / LineTime
++			- (DSTYAfterScaler + DSTXAfterScaler / HTotal);
++
++	Tsw_oto = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime;
++
++	prefetch_bw_oto = (MetaRowByte + PixelPTEBytesPerRow
++			+ PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1)
++			+ PrefetchSourceLinesC * SwathWidthY / 2 * dml_ceil(BytePerPixelDETC, 2))
++			/ Tsw_oto;
++
++	if (GPUVMEnable == true) {
++		Tvm_oto =
++				dml_max(
++						*Tno_bw + PDEAndMetaPTEBytesFrame / prefetch_bw_oto,
++						dml_max(
++								UrgentExtraLatency
++										+ UrgentLatencyPixelDataOnly
++												* (PageTableLevels
++														- 1),
++								LineTime / 4.0));
++	} else
++		Tvm_oto = LineTime / 4.0;
++
++	if ((GPUVMEnable == true || DCCEnable == true)) {
++		Tr0_oto = dml_max(
++				(MetaRowByte + PixelPTEBytesPerRow) / prefetch_bw_oto,
++				dml_max(UrgentLatencyPixelDataOnly, dml_max(LineTime - Tvm_oto, LineTime / 4)));
++	} else
++		Tr0_oto = LineTime - Tvm_oto;
++
++	Tpre_oto = Tvm_oto + Tr0_oto + Tsw_oto;
++
++	dst_y_prefetch_oto = Tpre_oto / LineTime;
++
++	if (dst_y_prefetch_oto < dst_y_prefetch_equ)
++		*DestinationLinesForPrefetch = dst_y_prefetch_oto;
++	else
++		*DestinationLinesForPrefetch = dst_y_prefetch_equ;
++
++	*DestinationLinesForPrefetch = dml_floor(4.0 * (*DestinationLinesForPrefetch + 0.125), 1)
++			/ 4;
++
++	dml_print("DML: VStartup: %d\n", VStartup);
++	dml_print("DML: TCalc: %f\n", TCalc);
++	dml_print("DML: TWait: %f\n", TWait);
++	dml_print("DML: XFCRemoteSurfaceFlipDelay: %f\n", XFCRemoteSurfaceFlipDelay);
++	dml_print("DML: LineTime: %f\n", LineTime);
++	dml_print("DML: Tsetup: %f\n", Tsetup);
++	dml_print("DML: Tdm: %f\n", Tdm);
++	dml_print("DML: DSTYAfterScaler: %f\n", DSTYAfterScaler);
++	dml_print("DML: DSTXAfterScaler: %f\n", DSTXAfterScaler);
++	dml_print("DML: HTotal: %d\n", HTotal);
++
++	*PrefetchBandwidth = 0;
++	*DestinationLinesToRequestVMInVBlank = 0;
++	*DestinationLinesToRequestRowInVBlank = 0;
++	*VRatioPrefetchY = 0;
++	*VRatioPrefetchC = 0;
++	*RequiredPrefetchPixDataBW = 0;
++	if (*DestinationLinesForPrefetch > 1) {
++		*PrefetchBandwidth = (PDEAndMetaPTEBytesFrame + 2 * MetaRowByte
++				+ 2 * PixelPTEBytesPerRow
++				+ PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1)
++				+ PrefetchSourceLinesC * SwathWidthY / 2
++						* dml_ceil(BytePerPixelDETC, 2))
++				/ (*DestinationLinesForPrefetch * LineTime - *Tno_bw);
++		if (GPUVMEnable) {
++			TimeForFetchingMetaPTE =
++					dml_max(
++							*Tno_bw
++									+ (double) PDEAndMetaPTEBytesFrame
++											/ *PrefetchBandwidth,
++							dml_max(
++									UrgentExtraLatency
++											+ UrgentLatencyPixelDataOnly
++													* (PageTableLevels
++															- 1),
++									LineTime / 4));
++		} else {
++			if (NumberOfCursors > 0 || XFCEnabled)
++				TimeForFetchingMetaPTE = LineTime / 4;
++			else
++				TimeForFetchingMetaPTE = 0.0;
++		}
++
++		if ((GPUVMEnable == true || DCCEnable == true)) {
++			TimeForFetchingRowInVBlank =
++					dml_max(
++							(MetaRowByte + PixelPTEBytesPerRow)
++									/ *PrefetchBandwidth,
++							dml_max(
++									UrgentLatencyPixelDataOnly,
++									dml_max(
++											LineTime
++													- TimeForFetchingMetaPTE,
++											LineTime
++													/ 4.0)));
++		} else {
++			if (NumberOfCursors > 0 || XFCEnabled)
++				TimeForFetchingRowInVBlank = LineTime - TimeForFetchingMetaPTE;
++			else
++				TimeForFetchingRowInVBlank = 0.0;
++		}
++
++		*DestinationLinesToRequestVMInVBlank = dml_floor(
++				4.0 * (TimeForFetchingMetaPTE / LineTime + 0.125),
++				1) / 4.0;
++
++		*DestinationLinesToRequestRowInVBlank = dml_floor(
++				4.0 * (TimeForFetchingRowInVBlank / LineTime + 0.125),
++				1) / 4.0;
++
++		LinesToRequestPrefetchPixelData =
++				*DestinationLinesForPrefetch
++						- ((NumberOfCursors > 0 || GPUVMEnable
++								|| DCCEnable) ?
++								(*DestinationLinesToRequestVMInVBlank
++										+ *DestinationLinesToRequestRowInVBlank) :
++								0.0);
++
++		if (LinesToRequestPrefetchPixelData > 0) {
++
++			*VRatioPrefetchY = (double) PrefetchSourceLinesY
++					/ LinesToRequestPrefetchPixelData;
++			*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
++			if ((SwathHeightY > 4) && (VInitPreFillY > 3)) {
++				if (LinesToRequestPrefetchPixelData > (VInitPreFillY - 3.0) / 2.0) {
++					*VRatioPrefetchY =
++							dml_max(
++									(double) PrefetchSourceLinesY
++											/ LinesToRequestPrefetchPixelData,
++									(double) MaxNumSwathY
++											* SwathHeightY
++											/ (LinesToRequestPrefetchPixelData
++													- (VInitPreFillY
++															- 3.0)
++															/ 2.0));
++					*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
++				} else {
++					MyError = true;
++					*VRatioPrefetchY = 0;
++				}
++			}
++
++			*VRatioPrefetchC = (double) PrefetchSourceLinesC
++					/ LinesToRequestPrefetchPixelData;
++			*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
++
++			if ((SwathHeightC > 4)) {
++				if (LinesToRequestPrefetchPixelData > (VInitPreFillC - 3.0) / 2.0) {
++					*VRatioPrefetchC =
++							dml_max(
++									*VRatioPrefetchC,
++									(double) MaxNumSwathC
++											* SwathHeightC
++											/ (LinesToRequestPrefetchPixelData
++													- (VInitPreFillC
++															- 3.0)
++															/ 2.0));
++					*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
++				} else {
++					MyError = true;
++					*VRatioPrefetchC = 0;
++				}
++			}
++
++			*RequiredPrefetchPixDataBW =
++					DPPPerPlane
++							* ((double) PrefetchSourceLinesY
++									/ LinesToRequestPrefetchPixelData
++									* dml_ceil(
++											BytePerPixelDETY,
++											1)
++									+ (double) PrefetchSourceLinesC
++											/ LinesToRequestPrefetchPixelData
++											* dml_ceil(
++													BytePerPixelDETC,
++													2)
++											/ 2)
++							* SwathWidthY / LineTime;
++		} else {
++			MyError = true;
++			*VRatioPrefetchY = 0;
++			*VRatioPrefetchC = 0;
++			*RequiredPrefetchPixDataBW = 0;
++		}
++
++	} else {
++		MyError = true;
++	}
++
++	if (MyError) {
++		*PrefetchBandwidth = 0;
++		TimeForFetchingMetaPTE = 0;
++		TimeForFetchingRowInVBlank = 0;
++		*DestinationLinesToRequestVMInVBlank = 0;
++		*DestinationLinesToRequestRowInVBlank = 0;
++		*DestinationLinesForPrefetch = 0;
++		LinesToRequestPrefetchPixelData = 0;
++		*VRatioPrefetchY = 0;
++		*VRatioPrefetchC = 0;
++		*RequiredPrefetchPixDataBW = 0;
++	}
++
++	return MyError;
++}
++
++static double RoundToDFSGranularityUp(double Clock, double VCOSpeed)
++{
++	return VCOSpeed * 4 / dml_floor(VCOSpeed * 4 / Clock, 1);
++}
++
++static double RoundToDFSGranularityDown(double Clock, double VCOSpeed)
++{
++	return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4 / Clock, 1);
++}
++
++static double CalculatePrefetchSourceLines(
++		struct display_mode_lib *mode_lib,
++		double VRatio,
++		double vtaps,
++		bool Interlace,
++		bool ProgressiveToInterlaceUnitInOPP,
++		unsigned int SwathHeight,
++		unsigned int ViewportYStart,
++		double *VInitPreFill,
++		unsigned int *MaxNumSwath)
++{
++	unsigned int MaxPartialSwath;
++
++	if (ProgressiveToInterlaceUnitInOPP)
++		*VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1);
++	else
++		*VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1);
++
++	if (!mode_lib->vba.IgnoreViewportPositioning) {
++
++		*MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0;
++
++		if (*VInitPreFill > 1.0)
++			MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight;
++		else
++			MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2)
++					% SwathHeight;
++		MaxPartialSwath = dml_max(1U, MaxPartialSwath);
++
++	} else {
++
++		if (ViewportYStart != 0)
++			dml_print(
++					"WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n");
++
++		*MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1);
++
++		if (*VInitPreFill > 1.0)
++			MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight;
++		else
++			MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 1)
++					% SwathHeight;
++	}
++
++	return *MaxNumSwath * SwathHeight + MaxPartialSwath;
++}
++
++static unsigned int CalculateVMAndRowBytes(
++		struct display_mode_lib *mode_lib,
++		bool DCCEnable,
++		unsigned int BlockHeight256Bytes,
++		unsigned int BlockWidth256Bytes,
++		enum source_format_class SourcePixelFormat,
++		unsigned int SurfaceTiling,
++		unsigned int BytePerPixel,
++		enum scan_direction_class ScanDirection,
++		unsigned int ViewportWidth,
++		unsigned int ViewportHeight,
++		unsigned int SwathWidth,
++		bool GPUVMEnable,
++		unsigned int VMMPageSize,
++		unsigned int PTEBufferSizeInRequestsLuma,
++		unsigned int PDEProcessingBufIn64KBReqs,
++		unsigned int Pitch,
++		unsigned int DCCMetaPitch,
++		unsigned int *MacroTileWidth,
++		unsigned int *MetaRowByte,
++		unsigned int *PixelPTEBytesPerRow,
++		bool *PTEBufferSizeNotExceeded,
++		unsigned int *dpte_row_height,
++		unsigned int *meta_row_height)
++{
++	unsigned int MetaRequestHeight;
++	unsigned int MetaRequestWidth;
++	unsigned int MetaSurfWidth;
++	unsigned int MetaSurfHeight;
++	unsigned int MPDEBytesFrame;
++	unsigned int MetaPTEBytesFrame;
++	unsigned int DCCMetaSurfaceBytes;
++
++	unsigned int MacroTileSizeBytes;
++	unsigned int MacroTileHeight;
++	unsigned int DPDE0BytesFrame;
++	unsigned int ExtraDPDEBytesFrame;
++	unsigned int PDEAndMetaPTEBytesFrame;
++
++	if (DCCEnable == true) {
++		MetaRequestHeight = 8 * BlockHeight256Bytes;
++		MetaRequestWidth = 8 * BlockWidth256Bytes;
++		if (ScanDirection == dm_horz) {
++			*meta_row_height = MetaRequestHeight;
++			MetaSurfWidth = dml_ceil((double) SwathWidth - 1, MetaRequestWidth)
++					+ MetaRequestWidth;
++			*MetaRowByte = MetaSurfWidth * MetaRequestHeight * BytePerPixel / 256.0;
++		} else {
++			*meta_row_height = MetaRequestWidth;
++			MetaSurfHeight = dml_ceil((double) SwathWidth - 1, MetaRequestHeight)
++					+ MetaRequestHeight;
++			*MetaRowByte = MetaSurfHeight * MetaRequestWidth * BytePerPixel / 256.0;
++		}
++		if (ScanDirection == dm_horz) {
++			DCCMetaSurfaceBytes = DCCMetaPitch
++					* (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes)
++							+ 64 * BlockHeight256Bytes) * BytePerPixel
++					/ 256;
++		} else {
++			DCCMetaSurfaceBytes = DCCMetaPitch
++					* (dml_ceil(
++							(double) ViewportHeight - 1,
++							64 * BlockHeight256Bytes)
++							+ 64 * BlockHeight256Bytes) * BytePerPixel
++					/ 256;
++		}
++		if (GPUVMEnable == true) {
++			MetaPTEBytesFrame = (dml_ceil(
++					(double) (DCCMetaSurfaceBytes - VMMPageSize)
++							/ (8 * VMMPageSize),
++					1) + 1) * 64;
++			MPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 1);
++		} else {
++			MetaPTEBytesFrame = 0;
++			MPDEBytesFrame = 0;
++		}
++	} else {
++		MetaPTEBytesFrame = 0;
++		MPDEBytesFrame = 0;
++		*MetaRowByte = 0;
++	}
++
++	if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_lvp) {
++		MacroTileSizeBytes = 256;
++		MacroTileHeight = BlockHeight256Bytes;
++	} else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x
++			|| SurfaceTiling == dm_sw_4kb_d || SurfaceTiling == dm_sw_4kb_d_x) {
++		MacroTileSizeBytes = 4096;
++		MacroTileHeight = 4 * BlockHeight256Bytes;
++	} else if (SurfaceTiling == dm_sw_64kb_s || SurfaceTiling == dm_sw_64kb_s_t
++			|| SurfaceTiling == dm_sw_64kb_s_x || SurfaceTiling == dm_sw_64kb_d
++			|| SurfaceTiling == dm_sw_64kb_d_t || SurfaceTiling == dm_sw_64kb_d_x
++			|| SurfaceTiling == dm_sw_64kb_r_x) {
++		MacroTileSizeBytes = 65536;
++		MacroTileHeight = 16 * BlockHeight256Bytes;
++	} else {
++		MacroTileSizeBytes = 262144;
++		MacroTileHeight = 32 * BlockHeight256Bytes;
++	}
++	*MacroTileWidth = MacroTileSizeBytes / BytePerPixel / MacroTileHeight;
++
++	if (GPUVMEnable == true && mode_lib->vba.GPUVMMaxPageTableLevels > 1) {
++		if (ScanDirection == dm_horz) {
++			DPDE0BytesFrame =
++					64
++							* (dml_ceil(
++									((Pitch
++											* (dml_ceil(
++													ViewportHeight
++															- 1,
++													MacroTileHeight)
++													+ MacroTileHeight)
++											* BytePerPixel)
++											- MacroTileSizeBytes)
++											/ (8
++													* 2097152),
++									1) + 1);
++		} else {
++			DPDE0BytesFrame =
++					64
++							* (dml_ceil(
++									((Pitch
++											* (dml_ceil(
++													(double) SwathWidth
++															- 1,
++													MacroTileHeight)
++													+ MacroTileHeight)
++											* BytePerPixel)
++											- MacroTileSizeBytes)
++											/ (8
++													* 2097152),
++									1) + 1);
++		}
++		ExtraDPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 2);
++	} else {
++		DPDE0BytesFrame = 0;
++		ExtraDPDEBytesFrame = 0;
++	}
++
++	PDEAndMetaPTEBytesFrame = MetaPTEBytesFrame + MPDEBytesFrame + DPDE0BytesFrame
++			+ ExtraDPDEBytesFrame;
++
++	if (GPUVMEnable == true) {
++		unsigned int PTERequestSize;
++		unsigned int PixelPTEReqHeight;
++		unsigned int PixelPTEReqWidth;
++		double FractionOfPTEReturnDrop;
++		unsigned int EffectivePDEProcessingBufIn64KBReqs;
++
++		if (SurfaceTiling == dm_sw_linear) {
++			PixelPTEReqHeight = 1;
++			PixelPTEReqWidth = 8.0 * VMMPageSize / BytePerPixel;
++			PTERequestSize = 64;
++			FractionOfPTEReturnDrop = 0;
++		} else if (MacroTileSizeBytes == 4096) {
++			PixelPTEReqHeight = MacroTileHeight;
++			PixelPTEReqWidth = 8 * *MacroTileWidth;
++			PTERequestSize = 64;
++			if (ScanDirection == dm_horz)
++				FractionOfPTEReturnDrop = 0;
++			else
++				FractionOfPTEReturnDrop = 7 / 8;
++		} else if (VMMPageSize == 4096 && MacroTileSizeBytes > 4096) {
++			PixelPTEReqHeight = 16 * BlockHeight256Bytes;
++			PixelPTEReqWidth = 16 * BlockWidth256Bytes;
++			PTERequestSize = 128;
++			FractionOfPTEReturnDrop = 0;
++		} else {
++			PixelPTEReqHeight = MacroTileHeight;
++			PixelPTEReqWidth = 8 * *MacroTileWidth;
++			PTERequestSize = 64;
++			FractionOfPTEReturnDrop = 0;
++		}
++
++		if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10)
++			EffectivePDEProcessingBufIn64KBReqs = PDEProcessingBufIn64KBReqs / 2;
++		else
++			EffectivePDEProcessingBufIn64KBReqs = PDEProcessingBufIn64KBReqs;
++
++		if (SurfaceTiling == dm_sw_linear) {
++			*dpte_row_height =
++					dml_min(
++							128,
++							1
++									<< (unsigned int) dml_floor(
++											dml_log2(
++													dml_min(
++															(double) PTEBufferSizeInRequestsLuma
++																	* PixelPTEReqWidth,
++															EffectivePDEProcessingBufIn64KBReqs
++																	* 65536.0
++																	/ BytePerPixel)
++															/ Pitch),
++											1));
++			*PixelPTEBytesPerRow = PTERequestSize
++					* (dml_ceil(
++							(double) (Pitch * *dpte_row_height - 1)
++									/ PixelPTEReqWidth,
++							1) + 1);
++		} else if (ScanDirection == dm_horz) {
++			*dpte_row_height = PixelPTEReqHeight;
++			*PixelPTEBytesPerRow = PTERequestSize
++					* (dml_ceil(((double) SwathWidth - 1) / PixelPTEReqWidth, 1)
++							+ 1);
++		} else {
++			*dpte_row_height = dml_min(PixelPTEReqWidth, *MacroTileWidth);
++			*PixelPTEBytesPerRow = PTERequestSize
++					* (dml_ceil(
++							((double) SwathWidth - 1)
++									/ PixelPTEReqHeight,
++							1) + 1);
++		}
++		if (*PixelPTEBytesPerRow * (1 - FractionOfPTEReturnDrop)
++				<= 64 * PTEBufferSizeInRequestsLuma) {
++			*PTEBufferSizeNotExceeded = true;
++		} else {
++			*PTEBufferSizeNotExceeded = false;
++		}
++	} else {
++		*PixelPTEBytesPerRow = 0;
++		*PTEBufferSizeNotExceeded = true;
++	}
++
++	return PDEAndMetaPTEBytesFrame;
++}
++
++static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
++		struct display_mode_lib *mode_lib)
++{
++	unsigned int j, k;
++
++	mode_lib->vba.WritebackDISPCLK = 0.0;
++	mode_lib->vba.DISPCLKWithRamping = 0;
++	mode_lib->vba.DISPCLKWithoutRamping = 0;
++	mode_lib->vba.GlobalDPPCLK = 0.0;
++
++	// dml_ml->vba.DISPCLK and dml_ml->vba.DPPCLK Calculation
++	//
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.WritebackEnable[k]) {
++			mode_lib->vba.WritebackDISPCLK =
++					dml_max(
++							mode_lib->vba.WritebackDISPCLK,
++							CalculateWriteBackDISPCLK(
++									mode_lib->vba.WritebackPixelFormat[k],
++									mode_lib->vba.PixelClock[k],
++									mode_lib->vba.WritebackHRatio[k],
++									mode_lib->vba.WritebackVRatio[k],
++									mode_lib->vba.WritebackLumaHTaps[k],
++									mode_lib->vba.WritebackLumaVTaps[k],
++									mode_lib->vba.WritebackChromaHTaps[k],
++									mode_lib->vba.WritebackChromaVTaps[k],
++									mode_lib->vba.WritebackDestinationWidth[k],
++									mode_lib->vba.HTotal[k],
++									mode_lib->vba.WritebackChromaLineBufferWidth));
++		}
++	}
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.HRatio[k] > 1) {
++			mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min(
++					mode_lib->vba.MaxDCHUBToPSCLThroughput,
++					mode_lib->vba.MaxPSCLToLBThroughput
++							* mode_lib->vba.HRatio[k]
++							/ dml_ceil(
++									mode_lib->vba.htaps[k]
++											/ 6.0,
++									1));
++		} else {
++			mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min(
++					mode_lib->vba.MaxDCHUBToPSCLThroughput,
++					mode_lib->vba.MaxPSCLToLBThroughput);
++		}
++
++		mode_lib->vba.DPPCLKUsingSingleDPPLuma =
++				mode_lib->vba.PixelClock[k]
++						* dml_max(
++								mode_lib->vba.vtaps[k] / 6.0
++										* dml_min(
++												1.0,
++												mode_lib->vba.HRatio[k]),
++								dml_max(
++										mode_lib->vba.HRatio[k]
++												* mode_lib->vba.VRatio[k]
++												/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k],
++										1.0));
++
++		if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6)
++				&& mode_lib->vba.DPPCLKUsingSingleDPPLuma
++						< 2 * mode_lib->vba.PixelClock[k]) {
++			mode_lib->vba.DPPCLKUsingSingleDPPLuma = 2 * mode_lib->vba.PixelClock[k];
++		}
++
++		if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
++				&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
++			mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = 0.0;
++			mode_lib->vba.DPPCLKUsingSingleDPP[k] =
++					mode_lib->vba.DPPCLKUsingSingleDPPLuma;
++		} else {
++			if (mode_lib->vba.HRatio[k] > 1) {
++				mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] =
++						dml_min(
++								mode_lib->vba.MaxDCHUBToPSCLThroughput,
++								mode_lib->vba.MaxPSCLToLBThroughput
++										* mode_lib->vba.HRatio[k]
++										/ 2
++										/ dml_ceil(
++												mode_lib->vba.HTAPsChroma[k]
++														/ 6.0,
++												1.0));
++			} else {
++				mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = dml_min(
++						mode_lib->vba.MaxDCHUBToPSCLThroughput,
++						mode_lib->vba.MaxPSCLToLBThroughput);
++			}
++			mode_lib->vba.DPPCLKUsingSingleDPPChroma =
++					mode_lib->vba.PixelClock[k]
++							* dml_max(
++									mode_lib->vba.VTAPsChroma[k]
++											/ 6.0
++											* dml_min(
++													1.0,
++													mode_lib->vba.HRatio[k]
++															/ 2),
++									dml_max(
++											mode_lib->vba.HRatio[k]
++													* mode_lib->vba.VRatio[k]
++													/ 4
++													/ mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k],
++											1.0));
++
++			if ((mode_lib->vba.HTAPsChroma[k] > 6 || mode_lib->vba.VTAPsChroma[k] > 6)
++					&& mode_lib->vba.DPPCLKUsingSingleDPPChroma
++							< 2 * mode_lib->vba.PixelClock[k]) {
++				mode_lib->vba.DPPCLKUsingSingleDPPChroma = 2
++						* mode_lib->vba.PixelClock[k];
++			}
++
++			mode_lib->vba.DPPCLKUsingSingleDPP[k] = dml_max(
++					mode_lib->vba.DPPCLKUsingSingleDPPLuma,
++					mode_lib->vba.DPPCLKUsingSingleDPPChroma);
++		}
++	}
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.BlendingAndTiming[k] != k)
++			continue;
++		if (mode_lib->vba.ODMCombineEnabled[k]) {
++			mode_lib->vba.DISPCLKWithRamping =
++					dml_max(
++							mode_lib->vba.DISPCLKWithRamping,
++							mode_lib->vba.PixelClock[k] / 2
++									* (1
++											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
++													/ 100)
++									* (1
++											+ mode_lib->vba.DISPCLKRampingMargin
++													/ 100));
++			mode_lib->vba.DISPCLKWithoutRamping =
++					dml_max(
++							mode_lib->vba.DISPCLKWithoutRamping,
++							mode_lib->vba.PixelClock[k] / 2
++									* (1
++											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
++													/ 100));
++		} else if (!mode_lib->vba.ODMCombineEnabled[k]) {
++			mode_lib->vba.DISPCLKWithRamping =
++					dml_max(
++							mode_lib->vba.DISPCLKWithRamping,
++							mode_lib->vba.PixelClock[k]
++									* (1
++											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
++													/ 100)
++									* (1
++											+ mode_lib->vba.DISPCLKRampingMargin
++													/ 100));
++			mode_lib->vba.DISPCLKWithoutRamping =
++					dml_max(
++							mode_lib->vba.DISPCLKWithoutRamping,
++							mode_lib->vba.PixelClock[k]
++									* (1
++											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
++													/ 100));
++		}
++	}
++
++	mode_lib->vba.DISPCLKWithRamping = dml_max(
++			mode_lib->vba.DISPCLKWithRamping,
++			mode_lib->vba.WritebackDISPCLK);
++	mode_lib->vba.DISPCLKWithoutRamping = dml_max(
++			mode_lib->vba.DISPCLKWithoutRamping,
++			mode_lib->vba.WritebackDISPCLK);
++
++	ASSERT(mode_lib->vba.DISPCLKDPPCLKVCOSpeed != 0);
++	mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(
++			mode_lib->vba.DISPCLKWithRamping,
++			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
++	mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(
++			mode_lib->vba.DISPCLKWithoutRamping,
++			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
++	mode_lib->vba.MaxDispclkRoundedToDFSGranularity = RoundToDFSGranularityDown(
++			mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz,
++			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
++	if (mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity
++			> mode_lib->vba.MaxDispclkRoundedToDFSGranularity) {
++		mode_lib->vba.DISPCLK_calculated =
++				mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity;
++	} else if (mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity
++			> mode_lib->vba.MaxDispclkRoundedToDFSGranularity) {
++		mode_lib->vba.DISPCLK_calculated = mode_lib->vba.MaxDispclkRoundedToDFSGranularity;
++	} else {
++		mode_lib->vba.DISPCLK_calculated =
++				mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity;
++	}
++	DTRACE("   dispclk_mhz (calculated) = %f", mode_lib->vba.DISPCLK_calculated);
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.DPPPerPlane[k] == 0) {
++			mode_lib->vba.DPPCLK_calculated[k] = 0;
++		} else {
++			mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.DPPCLKUsingSingleDPP[k]
++					/ mode_lib->vba.DPPPerPlane[k]
++					* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100);
++		}
++		mode_lib->vba.GlobalDPPCLK = dml_max(
++				mode_lib->vba.GlobalDPPCLK,
++				mode_lib->vba.DPPCLK_calculated[k]);
++	}
++	mode_lib->vba.GlobalDPPCLK = RoundToDFSGranularityUp(
++			mode_lib->vba.GlobalDPPCLK,
++			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.GlobalDPPCLK / 255
++				* dml_ceil(
++						mode_lib->vba.DPPCLK_calculated[k] * 255
++								/ mode_lib->vba.GlobalDPPCLK,
++						1);
++		DTRACE("   dppclk_mhz[%i] (calculated) = %f", k, mode_lib->vba.DPPCLK_calculated[k]);
++	}
++
++	// Urgent Watermark
++	mode_lib->vba.DCCEnabledAnyPlane = false;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
++		if (mode_lib->vba.DCCEnable[k])
++			mode_lib->vba.DCCEnabledAnyPlane = true;
++
++	mode_lib->vba.ReturnBandwidthToDCN = dml_min(
++			mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLK,
++			mode_lib->vba.FabricAndDRAMBandwidth * 1000)
++			* mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly / 100;
++
++	mode_lib->vba.ReturnBW = mode_lib->vba.ReturnBandwidthToDCN;
++	mode_lib->vba.ReturnBW = adjust_ReturnBW(
++			mode_lib,
++			mode_lib->vba.ReturnBW,
++			mode_lib->vba.DCCEnabledAnyPlane,
++			mode_lib->vba.ReturnBandwidthToDCN);
++
++	// Let's do this calculation again??
++	mode_lib->vba.ReturnBandwidthToDCN = dml_min(
++			mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLK,
++			mode_lib->vba.FabricAndDRAMBandwidth * 1000);
++	mode_lib->vba.ReturnBW = adjust_ReturnBW(
++			mode_lib,
++			mode_lib->vba.ReturnBW,
++			mode_lib->vba.DCCEnabledAnyPlane,
++			mode_lib->vba.ReturnBandwidthToDCN);
++
++	DTRACE("   dcfclk_mhz         = %f", mode_lib->vba.DCFCLK);
++	DTRACE("   return_bw_to_dcn   = %f", mode_lib->vba.ReturnBandwidthToDCN);
++	DTRACE("   return_bus_bw      = %f", mode_lib->vba.ReturnBW);
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		bool MainPlaneDoesODMCombine = false;
++
++		if (mode_lib->vba.SourceScan[k] == dm_horz)
++			mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportWidth[k];
++		else
++			mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportHeight[k];
++
++		if (mode_lib->vba.ODMCombineEnabled[k] == true)
++			MainPlaneDoesODMCombine = true;
++		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j)
++			if (mode_lib->vba.BlendingAndTiming[k] == j
++					&& mode_lib->vba.ODMCombineEnabled[j] == true)
++				MainPlaneDoesODMCombine = true;
++
++		if (MainPlaneDoesODMCombine == true)
++			mode_lib->vba.SwathWidthY[k] = dml_min(
++					(double) mode_lib->vba.SwathWidthSingleDPPY[k],
++					dml_round(
++							mode_lib->vba.HActive[k] / 2.0
++									* mode_lib->vba.HRatio[k]));
++		else {
++			if (mode_lib->vba.DPPPerPlane[k] == 0) {
++				mode_lib->vba.SwathWidthY[k] = 0;
++			} else {
++				mode_lib->vba.SwathWidthY[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
++						/ mode_lib->vba.DPPPerPlane[k];
++			}
++		}
++	}
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
++			mode_lib->vba.BytePerPixelDETY[k] = 8;
++			mode_lib->vba.BytePerPixelDETC[k] = 0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
++			mode_lib->vba.BytePerPixelDETY[k] = 4;
++			mode_lib->vba.BytePerPixelDETC[k] = 0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
++			mode_lib->vba.BytePerPixelDETY[k] = 2;
++			mode_lib->vba.BytePerPixelDETC[k] = 0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) {
++			mode_lib->vba.BytePerPixelDETY[k] = 1;
++			mode_lib->vba.BytePerPixelDETC[k] = 0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
++			mode_lib->vba.BytePerPixelDETY[k] = 1;
++			mode_lib->vba.BytePerPixelDETC[k] = 2;
++		} else { // dm_420_10
++			mode_lib->vba.BytePerPixelDETY[k] = 4.0 / 3.0;
++			mode_lib->vba.BytePerPixelDETC[k] = 8.0 / 3.0;
++		}
++	}
++
++	mode_lib->vba.TotalDataReadBandwidth = 0.0;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		mode_lib->vba.ReadBandwidthPlaneLuma[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
++				* dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1)
++				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
++				* mode_lib->vba.VRatio[k];
++		mode_lib->vba.ReadBandwidthPlaneChroma[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
++				/ 2 * dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2)
++				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
++				* mode_lib->vba.VRatio[k] / 2;
++		DTRACE(
++				"   read_bw[%i] = %fBps",
++				k,
++				mode_lib->vba.ReadBandwidthPlaneLuma[k]
++						+ mode_lib->vba.ReadBandwidthPlaneChroma[k]);
++		mode_lib->vba.TotalDataReadBandwidth += mode_lib->vba.ReadBandwidthPlaneLuma[k]
++				+ mode_lib->vba.ReadBandwidthPlaneChroma[k];
++	}
++
++	mode_lib->vba.TotalDCCActiveDPP = 0;
++	mode_lib->vba.TotalActiveDPP = 0;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP
++				+ mode_lib->vba.DPPPerPlane[k];
++		if (mode_lib->vba.DCCEnable[k])
++			mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP
++					+ mode_lib->vba.DPPPerPlane[k];
++	}
++
++	mode_lib->vba.UrgentRoundTripAndOutOfOrderLatency =
++			(mode_lib->vba.RoundTripPingLatencyCycles + 32) / mode_lib->vba.DCFCLK
++					+ mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly
++							* mode_lib->vba.NumberOfChannels
++							/ mode_lib->vba.ReturnBW;
++
++	mode_lib->vba.LastPixelOfLineExtraWatermark = 0;
++
++	mode_lib->vba.UrgentExtraLatency = mode_lib->vba.UrgentRoundTripAndOutOfOrderLatency
++			+ (mode_lib->vba.TotalActiveDPP * mode_lib->vba.PixelChunkSizeInKByte
++					+ mode_lib->vba.TotalDCCActiveDPP
++							* mode_lib->vba.MetaChunkSize) * 1024.0
++					/ mode_lib->vba.ReturnBW;
++
++	if (mode_lib->vba.GPUVMEnable)
++		mode_lib->vba.UrgentExtraLatency += mode_lib->vba.TotalActiveDPP
++				* mode_lib->vba.PTEGroupSize / mode_lib->vba.ReturnBW;
++
++	mode_lib->vba.UrgentWatermark = mode_lib->vba.UrgentLatencyPixelDataOnly
++			+ mode_lib->vba.LastPixelOfLineExtraWatermark
++			+ mode_lib->vba.UrgentExtraLatency;
++
++	DTRACE("   urgent_extra_latency = %fus", mode_lib->vba.UrgentExtraLatency);
++	DTRACE("   wm_urgent = %fus", mode_lib->vba.UrgentWatermark);
++
++	mode_lib->vba.UrgentLatency = mode_lib->vba.UrgentLatencyPixelDataOnly;
++
++	mode_lib->vba.TotalActiveWriteback = 0;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.WritebackEnable[k])
++			mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + mode_lib->vba.ActiveWritebacksPerPlane[k];
++	}
++
++	if (mode_lib->vba.TotalActiveWriteback <= 1)
++		mode_lib->vba.WritebackUrgentWatermark = mode_lib->vba.WritebackLatency;
++	else
++		mode_lib->vba.WritebackUrgentWatermark = mode_lib->vba.WritebackLatency
++				+ mode_lib->vba.WritebackChunkSize * 1024.0 / 32
++						/ mode_lib->vba.SOCCLK;
++
++	DTRACE("   wm_wb_urgent = %fus", mode_lib->vba.WritebackUrgentWatermark);
++
++	// NB P-State/DRAM Clock Change Watermark
++	mode_lib->vba.DRAMClockChangeWatermark = mode_lib->vba.DRAMClockChangeLatency
++			+ mode_lib->vba.UrgentWatermark;
++
++	DTRACE("   wm_pstate_change = %fus", mode_lib->vba.DRAMClockChangeWatermark);
++
++	DTRACE("   calculating wb pstate watermark");
++	DTRACE("      total wb outputs %d", mode_lib->vba.TotalActiveWriteback);
++	DTRACE("      socclk frequency %f Mhz", mode_lib->vba.SOCCLK);
++
++	if (mode_lib->vba.TotalActiveWriteback <= 1)
++		mode_lib->vba.WritebackDRAMClockChangeWatermark =
++				mode_lib->vba.DRAMClockChangeLatency
++						+ mode_lib->vba.WritebackLatency;
++	else
++		mode_lib->vba.WritebackDRAMClockChangeWatermark =
++				mode_lib->vba.DRAMClockChangeLatency
++						+ mode_lib->vba.WritebackLatency
++						+ mode_lib->vba.WritebackChunkSize * 1024.0 / 32
++								/ mode_lib->vba.SOCCLK;
++
++	DTRACE("   wm_wb_pstate %fus", mode_lib->vba.WritebackDRAMClockChangeWatermark);
++
++	// Stutter Efficiency
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		mode_lib->vba.LinesInDETY[k] = mode_lib->vba.DETBufferSizeY[k]
++				/ mode_lib->vba.BytePerPixelDETY[k] / mode_lib->vba.SwathWidthY[k];
++		mode_lib->vba.LinesInDETYRoundedDownToSwath[k] = dml_floor(
++				mode_lib->vba.LinesInDETY[k],
++				mode_lib->vba.SwathHeightY[k]);
++		mode_lib->vba.FullDETBufferingTimeY[k] =
++				mode_lib->vba.LinesInDETYRoundedDownToSwath[k]
++						* (mode_lib->vba.HTotal[k]
++								/ mode_lib->vba.PixelClock[k])
++						/ mode_lib->vba.VRatio[k];
++		if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
++			mode_lib->vba.LinesInDETC[k] = mode_lib->vba.DETBufferSizeC[k]
++					/ mode_lib->vba.BytePerPixelDETC[k]
++					/ (mode_lib->vba.SwathWidthY[k] / 2);
++			mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = dml_floor(
++					mode_lib->vba.LinesInDETC[k],
++					mode_lib->vba.SwathHeightC[k]);
++			mode_lib->vba.FullDETBufferingTimeC[k] =
++					mode_lib->vba.LinesInDETCRoundedDownToSwath[k]
++							* (mode_lib->vba.HTotal[k]
++									/ mode_lib->vba.PixelClock[k])
++							/ (mode_lib->vba.VRatio[k] / 2);
++		} else {
++			mode_lib->vba.LinesInDETC[k] = 0;
++			mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = 0;
++			mode_lib->vba.FullDETBufferingTimeC[k] = 999999;
++		}
++	}
++
++	mode_lib->vba.MinFullDETBufferingTime = 999999.0;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.FullDETBufferingTimeY[k]
++				< mode_lib->vba.MinFullDETBufferingTime) {
++			mode_lib->vba.MinFullDETBufferingTime =
++					mode_lib->vba.FullDETBufferingTimeY[k];
++			mode_lib->vba.FrameTimeForMinFullDETBufferingTime =
++					(double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k]
++							/ mode_lib->vba.PixelClock[k];
++		}
++		if (mode_lib->vba.FullDETBufferingTimeC[k]
++				< mode_lib->vba.MinFullDETBufferingTime) {
++			mode_lib->vba.MinFullDETBufferingTime =
++					mode_lib->vba.FullDETBufferingTimeC[k];
++			mode_lib->vba.FrameTimeForMinFullDETBufferingTime =
++					(double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k]
++							/ mode_lib->vba.PixelClock[k];
++		}
++	}
++
++	mode_lib->vba.AverageReadBandwidthGBytePerSecond = 0.0;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.DCCEnable[k]) {
++			mode_lib->vba.AverageReadBandwidthGBytePerSecond =
++					mode_lib->vba.AverageReadBandwidthGBytePerSecond
++							+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
++									/ mode_lib->vba.DCCRate[k]
++									/ 1000
++							+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
++									/ mode_lib->vba.DCCRate[k]
++									/ 1000;
++		} else {
++			mode_lib->vba.AverageReadBandwidthGBytePerSecond =
++					mode_lib->vba.AverageReadBandwidthGBytePerSecond
++							+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
++									/ 1000
++							+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
++									/ 1000;
++		}
++		if (mode_lib->vba.DCCEnable[k]) {
++			mode_lib->vba.AverageReadBandwidthGBytePerSecond =
++					mode_lib->vba.AverageReadBandwidthGBytePerSecond
++							+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
++									/ 1000 / 256
++							+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
++									/ 1000 / 256;
++		}
++		if (mode_lib->vba.GPUVMEnable) {
++			mode_lib->vba.AverageReadBandwidthGBytePerSecond =
++					mode_lib->vba.AverageReadBandwidthGBytePerSecond
++							+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
++									/ 1000 / 512
++							+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
++									/ 1000 / 512;
++		}
++	}
++
++	mode_lib->vba.PartOfBurstThatFitsInROB =
++			dml_min(
++					mode_lib->vba.MinFullDETBufferingTime
++							* mode_lib->vba.TotalDataReadBandwidth,
++					mode_lib->vba.ROBBufferSizeInKByte * 1024
++							* mode_lib->vba.TotalDataReadBandwidth
++							/ (mode_lib->vba.AverageReadBandwidthGBytePerSecond
++									* 1000));
++	mode_lib->vba.StutterBurstTime = mode_lib->vba.PartOfBurstThatFitsInROB
++			* (mode_lib->vba.AverageReadBandwidthGBytePerSecond * 1000)
++			/ mode_lib->vba.TotalDataReadBandwidth / mode_lib->vba.ReturnBW
++			+ (mode_lib->vba.MinFullDETBufferingTime
++					* mode_lib->vba.TotalDataReadBandwidth
++					- mode_lib->vba.PartOfBurstThatFitsInROB)
++					/ (mode_lib->vba.DCFCLK * 64);
++	if (mode_lib->vba.TotalActiveWriteback == 0) {
++		mode_lib->vba.StutterEfficiencyNotIncludingVBlank = (1
++				- (mode_lib->vba.SRExitTime + mode_lib->vba.StutterBurstTime)
++						/ mode_lib->vba.MinFullDETBufferingTime) * 100;
++	} else {
++		mode_lib->vba.StutterEfficiencyNotIncludingVBlank = 0;
++	}
++
++	mode_lib->vba.SmallestVBlank = 999999;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {
++			mode_lib->vba.VBlankTime = (double) (mode_lib->vba.VTotal[k]
++					- mode_lib->vba.VActive[k]) * mode_lib->vba.HTotal[k]
++					/ mode_lib->vba.PixelClock[k];
++		} else {
++			mode_lib->vba.VBlankTime = 0;
++		}
++		mode_lib->vba.SmallestVBlank = dml_min(
++				mode_lib->vba.SmallestVBlank,
++				mode_lib->vba.VBlankTime);
++	}
++
++	mode_lib->vba.StutterEfficiency = (mode_lib->vba.StutterEfficiencyNotIncludingVBlank / 100
++			* (mode_lib->vba.FrameTimeForMinFullDETBufferingTime
++					- mode_lib->vba.SmallestVBlank)
++			+ mode_lib->vba.SmallestVBlank)
++			/ mode_lib->vba.FrameTimeForMinFullDETBufferingTime * 100;
++
++	// dml_ml->vba.DCFCLK Deep Sleep
++	mode_lib->vba.DCFCLKDeepSleep = 8.0;
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++) {
++		if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
++			mode_lib->vba.DCFCLKDeepSleepPerPlane[k] =
++					dml_max(
++							1.1 * mode_lib->vba.SwathWidthY[k]
++									* dml_ceil(
++											mode_lib->vba.BytePerPixelDETY[k],
++											1) / 32
++									/ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k],
++							1.1 * mode_lib->vba.SwathWidthY[k] / 2.0
++									* dml_ceil(
++											mode_lib->vba.BytePerPixelDETC[k],
++											2) / 32
++									/ mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k]);
++		} else
++			mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = 1.1 * mode_lib->vba.SwathWidthY[k]
++					* dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1) / 64.0
++					/ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k];
++		mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(
++				mode_lib->vba.DCFCLKDeepSleepPerPlane[k],
++				mode_lib->vba.PixelClock[k] / 16.0);
++		mode_lib->vba.DCFCLKDeepSleep = dml_max(
++				mode_lib->vba.DCFCLKDeepSleep,
++				mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
++
++		DTRACE(
++				"   dcfclk_deepsleep_per_plane[%i] = %fMHz",
++				k,
++				mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
++	}
++
++	DTRACE("   dcfclk_deepsleep_mhz = %fMHz", mode_lib->vba.DCFCLKDeepSleep);
++
++	// Stutter Watermark
++	mode_lib->vba.StutterExitWatermark = mode_lib->vba.SRExitTime
++			+ mode_lib->vba.LastPixelOfLineExtraWatermark
++			+ mode_lib->vba.UrgentExtraLatency + 10 / mode_lib->vba.DCFCLKDeepSleep;
++	mode_lib->vba.StutterEnterPlusExitWatermark = mode_lib->vba.SREnterPlusExitTime
++			+ mode_lib->vba.LastPixelOfLineExtraWatermark
++			+ mode_lib->vba.UrgentExtraLatency;
++
++	DTRACE("   wm_cstate_exit       = %fus", mode_lib->vba.StutterExitWatermark);
++	DTRACE("   wm_cstate_enter_exit = %fus", mode_lib->vba.StutterEnterPlusExitWatermark);
++
++	// Urgent Latency Supported
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		mode_lib->vba.EffectiveDETPlusLBLinesLuma =
++				dml_floor(
++						mode_lib->vba.LinesInDETY[k]
++								+ dml_min(
++										mode_lib->vba.LinesInDETY[k]
++												* mode_lib->vba.DPPCLK[k]
++												* mode_lib->vba.BytePerPixelDETY[k]
++												* mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
++												/ (mode_lib->vba.ReturnBW
++														/ mode_lib->vba.DPPPerPlane[k]),
++										(double) mode_lib->vba.EffectiveLBLatencyHidingSourceLinesLuma),
++						mode_lib->vba.SwathHeightY[k]);
++
++		mode_lib->vba.UrgentLatencySupportUsLuma = mode_lib->vba.EffectiveDETPlusLBLinesLuma
++				* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
++				/ mode_lib->vba.VRatio[k]
++				- mode_lib->vba.EffectiveDETPlusLBLinesLuma
++						* mode_lib->vba.SwathWidthY[k]
++						* mode_lib->vba.BytePerPixelDETY[k]
++						/ (mode_lib->vba.ReturnBW
++								/ mode_lib->vba.DPPPerPlane[k]);
++
++		if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
++			mode_lib->vba.EffectiveDETPlusLBLinesChroma =
++					dml_floor(
++							mode_lib->vba.LinesInDETC[k]
++									+ dml_min(
++											mode_lib->vba.LinesInDETC[k]
++													* mode_lib->vba.DPPCLK[k]
++													* mode_lib->vba.BytePerPixelDETC[k]
++													* mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k]
++													/ (mode_lib->vba.ReturnBW
++															/ mode_lib->vba.DPPPerPlane[k]),
++											(double) mode_lib->vba.EffectiveLBLatencyHidingSourceLinesChroma),
++							mode_lib->vba.SwathHeightC[k]);
++			mode_lib->vba.UrgentLatencySupportUsChroma =
++					mode_lib->vba.EffectiveDETPlusLBLinesChroma
++							* (mode_lib->vba.HTotal[k]
++									/ mode_lib->vba.PixelClock[k])
++							/ (mode_lib->vba.VRatio[k] / 2)
++							- mode_lib->vba.EffectiveDETPlusLBLinesChroma
++									* (mode_lib->vba.SwathWidthY[k]
++											/ 2)
++									* mode_lib->vba.BytePerPixelDETC[k]
++									/ (mode_lib->vba.ReturnBW
++											/ mode_lib->vba.DPPPerPlane[k]);
++			mode_lib->vba.UrgentLatencySupportUs[k] = dml_min(
++					mode_lib->vba.UrgentLatencySupportUsLuma,
++					mode_lib->vba.UrgentLatencySupportUsChroma);
++		} else {
++			mode_lib->vba.UrgentLatencySupportUs[k] =
++					mode_lib->vba.UrgentLatencySupportUsLuma;
++		}
++	}
++
++	mode_lib->vba.MinUrgentLatencySupportUs = 999999;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		mode_lib->vba.MinUrgentLatencySupportUs = dml_min(
++				mode_lib->vba.MinUrgentLatencySupportUs,
++				mode_lib->vba.UrgentLatencySupportUs[k]);
++	}
++
++	// Non-Urgent Latency Tolerance
++	mode_lib->vba.NonUrgentLatencyTolerance = mode_lib->vba.MinUrgentLatencySupportUs
++			- mode_lib->vba.UrgentWatermark;
++
++	// DSCCLK
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
++			mode_lib->vba.DSCCLK_calculated[k] = 0.0;
++		} else {
++			if (mode_lib->vba.OutputFormat[k] == dm_420
++					|| mode_lib->vba.OutputFormat[k] == dm_n422)
++				mode_lib->vba.DSCFormatFactor = 2;
++			else
++				mode_lib->vba.DSCFormatFactor = 1;
++			if (mode_lib->vba.ODMCombineEnabled[k])
++				mode_lib->vba.DSCCLK_calculated[k] =
++						mode_lib->vba.PixelClockBackEnd[k] / 6
++								/ mode_lib->vba.DSCFormatFactor
++								/ (1
++										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
++												/ 100);
++			else
++				mode_lib->vba.DSCCLK_calculated[k] =
++						mode_lib->vba.PixelClockBackEnd[k] / 3
++								/ mode_lib->vba.DSCFormatFactor
++								/ (1
++										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
++												/ 100);
++		}
++	}
++
++	// DSC Delay
++	// TODO
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		double bpp = mode_lib->vba.OutputBpp[k];
++		unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k];
++
++		if (mode_lib->vba.DSCEnabled[k] && bpp != 0) {
++			if (!mode_lib->vba.ODMCombineEnabled[k]) {
++				mode_lib->vba.DSCDelay[k] =
++						dscceComputeDelay(
++								mode_lib->vba.DSCInputBitPerComponent[k],
++								bpp,
++								dml_ceil(
++										(double) mode_lib->vba.HActive[k]
++												/ mode_lib->vba.NumberOfDSCSlices[k],
++										1),
++								slices,
++								mode_lib->vba.OutputFormat[k])
++								+ dscComputeDelay(
++										mode_lib->vba.OutputFormat[k]);
++			} else {
++				mode_lib->vba.DSCDelay[k] =
++						2
++								* (dscceComputeDelay(
++										mode_lib->vba.DSCInputBitPerComponent[k],
++										bpp,
++										dml_ceil(
++												(double) mode_lib->vba.HActive[k]
++														/ mode_lib->vba.NumberOfDSCSlices[k],
++												1),
++										slices / 2.0,
++										mode_lib->vba.OutputFormat[k])
++										+ dscComputeDelay(
++												mode_lib->vba.OutputFormat[k]));
++			}
++			mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[k]
++					* mode_lib->vba.PixelClock[k]
++					/ mode_lib->vba.PixelClockBackEnd[k];
++		} else {
++			mode_lib->vba.DSCDelay[k] = 0;
++		}
++	}
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
++		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) // NumberOfPlanes
++			if (j != k && mode_lib->vba.BlendingAndTiming[k] == j
++					&& mode_lib->vba.DSCEnabled[j])
++				mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[j];
++
++	// Prefetch
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		unsigned int PDEAndMetaPTEBytesFrameY;
++		unsigned int PixelPTEBytesPerRowY;
++		unsigned int MetaRowByteY;
++		unsigned int MetaRowByteC;
++		unsigned int PDEAndMetaPTEBytesFrameC;
++		unsigned int PixelPTEBytesPerRowC;
++
++		Calculate256BBlockSizes(
++				mode_lib->vba.SourcePixelFormat[k],
++				mode_lib->vba.SurfaceTiling[k],
++				dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
++				dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2),
++				&mode_lib->vba.BlockHeight256BytesY[k],
++				&mode_lib->vba.BlockHeight256BytesC[k],
++				&mode_lib->vba.BlockWidth256BytesY[k],
++				&mode_lib->vba.BlockWidth256BytesC[k]);
++		PDEAndMetaPTEBytesFrameY = CalculateVMAndRowBytes(
++				mode_lib,
++				mode_lib->vba.DCCEnable[k],
++				mode_lib->vba.BlockHeight256BytesY[k],
++				mode_lib->vba.BlockWidth256BytesY[k],
++				mode_lib->vba.SourcePixelFormat[k],
++				mode_lib->vba.SurfaceTiling[k],
++				dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
++				mode_lib->vba.SourceScan[k],
++				mode_lib->vba.ViewportWidth[k],
++				mode_lib->vba.ViewportHeight[k],
++				mode_lib->vba.SwathWidthY[k],
++				mode_lib->vba.GPUVMEnable,
++				mode_lib->vba.VMMPageSize,
++				mode_lib->vba.PTEBufferSizeInRequestsLuma,
++				mode_lib->vba.PDEProcessingBufIn64KBReqs,
++				mode_lib->vba.PitchY[k],
++				mode_lib->vba.DCCMetaPitchY[k],
++				&mode_lib->vba.MacroTileWidthY[k],
++				&MetaRowByteY,
++				&PixelPTEBytesPerRowY,
++				&mode_lib->vba.PTEBufferSizeNotExceeded[mode_lib->vba.VoltageLevel][0],
++				&mode_lib->vba.dpte_row_height[k],
++				&mode_lib->vba.meta_row_height[k]);
++		mode_lib->vba.PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
++				mode_lib,
++				mode_lib->vba.VRatio[k],
++				mode_lib->vba.vtaps[k],
++				mode_lib->vba.Interlace[k],
++				mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
++				mode_lib->vba.SwathHeightY[k],
++				mode_lib->vba.ViewportYStartY[k],
++				&mode_lib->vba.VInitPreFillY[k],
++				&mode_lib->vba.MaxNumSwathY[k]);
++
++		if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
++				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
++				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
++				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_8)) {
++			PDEAndMetaPTEBytesFrameC =
++					CalculateVMAndRowBytes(
++							mode_lib,
++							mode_lib->vba.DCCEnable[k],
++							mode_lib->vba.BlockHeight256BytesC[k],
++							mode_lib->vba.BlockWidth256BytesC[k],
++							mode_lib->vba.SourcePixelFormat[k],
++							mode_lib->vba.SurfaceTiling[k],
++							dml_ceil(
++									mode_lib->vba.BytePerPixelDETC[k],
++									2),
++							mode_lib->vba.SourceScan[k],
++							mode_lib->vba.ViewportWidth[k] / 2,
++							mode_lib->vba.ViewportHeight[k] / 2,
++							mode_lib->vba.SwathWidthY[k] / 2,
++							mode_lib->vba.GPUVMEnable,
++							mode_lib->vba.VMMPageSize,
++							mode_lib->vba.PTEBufferSizeInRequestsLuma,
++							mode_lib->vba.PDEProcessingBufIn64KBReqs,
++							mode_lib->vba.PitchC[k],
++							0,
++							&mode_lib->vba.MacroTileWidthC[k],
++							&MetaRowByteC,
++							&PixelPTEBytesPerRowC,
++							&mode_lib->vba.PTEBufferSizeNotExceeded[mode_lib->vba.VoltageLevel][0],
++							&mode_lib->vba.dpte_row_height_chroma[k],
++							&mode_lib->vba.meta_row_height_chroma[k]);
++			mode_lib->vba.PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
++					mode_lib,
++					mode_lib->vba.VRatio[k] / 2,
++					mode_lib->vba.VTAPsChroma[k],
++					mode_lib->vba.Interlace[k],
++					mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
++					mode_lib->vba.SwathHeightC[k],
++					mode_lib->vba.ViewportYStartC[k],
++					&mode_lib->vba.VInitPreFillC[k],
++					&mode_lib->vba.MaxNumSwathC[k]);
++		} else {
++			PixelPTEBytesPerRowC = 0;
++			PDEAndMetaPTEBytesFrameC = 0;
++			MetaRowByteC = 0;
++			mode_lib->vba.MaxNumSwathC[k] = 0;
++			mode_lib->vba.PrefetchSourceLinesC[k] = 0;
++		}
++
++		mode_lib->vba.PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
++		mode_lib->vba.PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY
++				+ PDEAndMetaPTEBytesFrameC;
++		mode_lib->vba.MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
++
++		CalculateActiveRowBandwidth(
++				mode_lib->vba.GPUVMEnable,
++				mode_lib->vba.SourcePixelFormat[k],
++				mode_lib->vba.VRatio[k],
++				mode_lib->vba.DCCEnable[k],
++				mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
++				MetaRowByteY,
++				MetaRowByteC,
++				mode_lib->vba.meta_row_height[k],
++				mode_lib->vba.meta_row_height_chroma[k],
++				PixelPTEBytesPerRowY,
++				PixelPTEBytesPerRowC,
++				mode_lib->vba.dpte_row_height[k],
++				mode_lib->vba.dpte_row_height_chroma[k],
++				&mode_lib->vba.meta_row_bw[k],
++				&mode_lib->vba.dpte_row_bw[k],
++				&mode_lib->vba.qual_row_bw[k]);
++	}
++
++	mode_lib->vba.TCalc = 24.0 / mode_lib->vba.DCFCLKDeepSleep;
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.BlendingAndTiming[k] == k) {
++			if (mode_lib->vba.WritebackEnable[k] == true) {
++				mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
++						mode_lib->vba.WritebackLatency
++								+ CalculateWriteBackDelay(
++										mode_lib->vba.WritebackPixelFormat[k],
++										mode_lib->vba.WritebackHRatio[k],
++										mode_lib->vba.WritebackVRatio[k],
++										mode_lib->vba.WritebackLumaHTaps[k],
++										mode_lib->vba.WritebackLumaVTaps[k],
++										mode_lib->vba.WritebackChromaHTaps[k],
++										mode_lib->vba.WritebackChromaVTaps[k],
++										mode_lib->vba.WritebackDestinationWidth[k])
++										/ mode_lib->vba.DISPCLK;
++			} else
++				mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0;
++			for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) {
++				if (mode_lib->vba.BlendingAndTiming[j] == k
++						&& mode_lib->vba.WritebackEnable[j] == true) {
++					mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
++							dml_max(
++									mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k],
++									mode_lib->vba.WritebackLatency
++											+ CalculateWriteBackDelay(
++													mode_lib->vba.WritebackPixelFormat[j],
++													mode_lib->vba.WritebackHRatio[j],
++													mode_lib->vba.WritebackVRatio[j],
++													mode_lib->vba.WritebackLumaHTaps[j],
++													mode_lib->vba.WritebackLumaVTaps[j],
++													mode_lib->vba.WritebackChromaHTaps[j],
++													mode_lib->vba.WritebackChromaVTaps[j],
++													mode_lib->vba.WritebackDestinationWidth[j])
++													/ mode_lib->vba.DISPCLK);
++				}
++			}
++		}
++	}
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
++		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j)
++			if (mode_lib->vba.BlendingAndTiming[k] == j)
++				mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
++						mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][j];
++
++	mode_lib->vba.VStartupLines = 13;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		mode_lib->vba.MaxVStartupLines[k] =
++				mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
++						- dml_max(
++								1.0,
++								dml_ceil(
++										mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k]
++												/ (mode_lib->vba.HTotal[k]
++														/ mode_lib->vba.PixelClock[k]),
++										1));
++	}
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
++		mode_lib->vba.MaximumMaxVStartupLines = dml_max(
++				mode_lib->vba.MaximumMaxVStartupLines,
++				mode_lib->vba.MaxVStartupLines[k]);
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		mode_lib->vba.cursor_bw[k] = 0.0;
++		for (j = 0; j < mode_lib->vba.NumberOfCursors[k]; ++j)
++			mode_lib->vba.cursor_bw[k] += mode_lib->vba.CursorWidth[k][j]
++					* mode_lib->vba.CursorBPP[k][j] / 8.0
++					/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
++					* mode_lib->vba.VRatio[k];
++	}
++
++	do {
++		double MaxTotalRDBandwidth = 0;
++		bool DestinationLineTimesForPrefetchLessThan2 = false;
++		bool VRatioPrefetchMoreThan4 = false;
++		bool prefetch_vm_bw_valid = true;
++		bool prefetch_row_bw_valid = true;
++		double TWait = CalculateTWait(
++				mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
++				mode_lib->vba.DRAMClockChangeLatency,
++				mode_lib->vba.UrgentLatencyPixelDataOnly,
++				mode_lib->vba.SREnterPlusExitTime);
++
++		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++			if (mode_lib->vba.XFCEnabled[k] == true) {
++				mode_lib->vba.XFCRemoteSurfaceFlipDelay =
++						CalculateRemoteSurfaceFlipDelay(
++								mode_lib,
++								mode_lib->vba.VRatio[k],
++								mode_lib->vba.SwathWidthY[k],
++								dml_ceil(
++										mode_lib->vba.BytePerPixelDETY[k],
++										1),
++								mode_lib->vba.HTotal[k]
++										/ mode_lib->vba.PixelClock[k],
++								mode_lib->vba.XFCTSlvVupdateOffset,
++								mode_lib->vba.XFCTSlvVupdateWidth,
++								mode_lib->vba.XFCTSlvVreadyOffset,
++								mode_lib->vba.XFCXBUFLatencyTolerance,
++								mode_lib->vba.XFCFillBWOverhead,
++								mode_lib->vba.XFCSlvChunkSize,
++								mode_lib->vba.XFCBusTransportTime,
++								mode_lib->vba.TCalc,
++								TWait,
++								&mode_lib->vba.SrcActiveDrainRate,
++								&mode_lib->vba.TInitXFill,
++								&mode_lib->vba.TslvChk);
++			} else {
++				mode_lib->vba.XFCRemoteSurfaceFlipDelay = 0;
++			}
++
++			CalculateDelayAfterScaler(mode_lib, mode_lib->vba.ReturnBW, mode_lib->vba.ReadBandwidthPlaneLuma[k], mode_lib->vba.ReadBandwidthPlaneChroma[k], mode_lib->vba.TotalDataReadBandwidth,
++					mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k],
++					mode_lib->vba.DPPCLK[k], mode_lib->vba.DISPCLK, mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDelay[k], mode_lib->vba.DPPPerPlane[k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k],
++					mode_lib->vba.DPPCLKDelaySubtotal, mode_lib->vba.DPPCLKDelaySCL, mode_lib->vba.DPPCLKDelaySCLLBOnly, mode_lib->vba.DPPCLKDelayCNVCFormater, mode_lib->vba.DPPCLKDelayCNVCCursor, mode_lib->vba.DISPCLKDelaySubtotal,
++					mode_lib->vba.SwathWidthY[k] / mode_lib->vba.HRatio[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k],
++					mode_lib->vba.SwathWidthSingleDPPY[k], mode_lib->vba.BytePerPixelDETY[k], mode_lib->vba.BytePerPixelDETC[k], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SwathHeightC[k], mode_lib->vba.Interlace[k],
++					mode_lib->vba.ProgressiveToInterlaceUnitInOPP, &mode_lib->vba.DSTXAfterScaler[k], &mode_lib->vba.DSTYAfterScaler[k]);
++
++			mode_lib->vba.ErrorResult[k] =
++					CalculatePrefetchSchedule(
++							mode_lib,
++							mode_lib->vba.DPPCLK[k],
++							mode_lib->vba.DISPCLK,
++							mode_lib->vba.PixelClock[k],
++							mode_lib->vba.DCFCLKDeepSleep,
++							mode_lib->vba.DPPPerPlane[k],
++							mode_lib->vba.NumberOfCursors[k],
++							mode_lib->vba.VTotal[k]
++									- mode_lib->vba.VActive[k],
++							mode_lib->vba.HTotal[k],
++							mode_lib->vba.MaxInterDCNTileRepeaters,
++							dml_min(
++									mode_lib->vba.VStartupLines,
++									mode_lib->vba.MaxVStartupLines[k]),
++							mode_lib->vba.GPUVMMaxPageTableLevels,
++							mode_lib->vba.GPUVMEnable,
++							mode_lib->vba.DynamicMetadataEnable[k],
++							mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
++							mode_lib->vba.DynamicMetadataTransmittedBytes[k],
++							mode_lib->vba.DCCEnable[k],
++							mode_lib->vba.UrgentLatencyPixelDataOnly,
++							mode_lib->vba.UrgentExtraLatency,
++							mode_lib->vba.TCalc,
++							mode_lib->vba.PDEAndMetaPTEBytesFrame[k],
++							mode_lib->vba.MetaRowByte[k],
++							mode_lib->vba.PixelPTEBytesPerRow[k],
++							mode_lib->vba.PrefetchSourceLinesY[k],
++							mode_lib->vba.SwathWidthY[k],
++							mode_lib->vba.BytePerPixelDETY[k],
++							mode_lib->vba.VInitPreFillY[k],
++							mode_lib->vba.MaxNumSwathY[k],
++							mode_lib->vba.PrefetchSourceLinesC[k],
++							mode_lib->vba.BytePerPixelDETC[k],
++							mode_lib->vba.VInitPreFillC[k],
++							mode_lib->vba.MaxNumSwathC[k],
++							mode_lib->vba.SwathHeightY[k],
++							mode_lib->vba.SwathHeightC[k],
++							TWait,
++							mode_lib->vba.XFCEnabled[k],
++							mode_lib->vba.XFCRemoteSurfaceFlipDelay,
++							mode_lib->vba.Interlace[k],
++							mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
++							mode_lib->vba.DSTXAfterScaler[k],
++							mode_lib->vba.DSTYAfterScaler[k],
++							&mode_lib->vba.DestinationLinesForPrefetch[k],
++							&mode_lib->vba.PrefetchBandwidth[k],
++							&mode_lib->vba.DestinationLinesToRequestVMInVBlank[k],
++							&mode_lib->vba.DestinationLinesToRequestRowInVBlank[k],
++							&mode_lib->vba.VRatioPrefetchY[k],
++							&mode_lib->vba.VRatioPrefetchC[k],
++							&mode_lib->vba.RequiredPrefetchPixDataBWLuma[k],
++							&mode_lib->vba.Tno_bw[k],
++							&mode_lib->vba.VUpdateOffsetPix[k],
++							&mode_lib->vba.VUpdateWidthPix[k],
++							&mode_lib->vba.VReadyOffsetPix[k]);
++
++			if (mode_lib->vba.BlendingAndTiming[k] == k) {
++				mode_lib->vba.VStartup[k] = dml_min(
++						mode_lib->vba.VStartupLines,
++						mode_lib->vba.MaxVStartupLines[k]);
++				if (mode_lib->vba.VStartupRequiredWhenNotEnoughTimeForDynamicMetadata
++						!= 0) {
++					mode_lib->vba.VStartup[k] =
++							mode_lib->vba.VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
++				}
++			} else {
++				mode_lib->vba.VStartup[k] =
++						dml_min(
++								mode_lib->vba.VStartupLines,
++								mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]);
++			}
++		}
++
++		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++
++			if (mode_lib->vba.PDEAndMetaPTEBytesFrame[k] == 0)
++				mode_lib->vba.prefetch_vm_bw[k] = 0;
++			else if (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] > 0) {
++				mode_lib->vba.prefetch_vm_bw[k] =
++						(double) mode_lib->vba.PDEAndMetaPTEBytesFrame[k]
++								/ (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
++										* mode_lib->vba.HTotal[k]
++										/ mode_lib->vba.PixelClock[k]);
++			} else {
++				mode_lib->vba.prefetch_vm_bw[k] = 0;
++				prefetch_vm_bw_valid = false;
++			}
++			if (mode_lib->vba.MetaRowByte[k] + mode_lib->vba.PixelPTEBytesPerRow[k]
++					== 0)
++				mode_lib->vba.prefetch_row_bw[k] = 0;
++			else if (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k] > 0) {
++				mode_lib->vba.prefetch_row_bw[k] =
++						(double) (mode_lib->vba.MetaRowByte[k]
++								+ mode_lib->vba.PixelPTEBytesPerRow[k])
++								/ (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k]
++										* mode_lib->vba.HTotal[k]
++										/ mode_lib->vba.PixelClock[k]);
++			} else {
++				mode_lib->vba.prefetch_row_bw[k] = 0;
++				prefetch_row_bw_valid = false;
++			}
++
++			MaxTotalRDBandwidth =
++					MaxTotalRDBandwidth + mode_lib->vba.cursor_bw[k]
++							+ dml_max(
++									mode_lib->vba.prefetch_vm_bw[k],
++									dml_max(
++											mode_lib->vba.prefetch_row_bw[k],
++											dml_max(
++													mode_lib->vba.ReadBandwidthPlaneLuma[k]
++															+ mode_lib->vba.ReadBandwidthPlaneChroma[k],
++													mode_lib->vba.RequiredPrefetchPixDataBWLuma[k])
++													+ mode_lib->vba.meta_row_bw[k]
++													+ mode_lib->vba.dpte_row_bw[k]));
++
++			if (mode_lib->vba.DestinationLinesForPrefetch[k] < 2)
++				DestinationLineTimesForPrefetchLessThan2 = true;
++			if (mode_lib->vba.VRatioPrefetchY[k] > 4
++					|| mode_lib->vba.VRatioPrefetchC[k] > 4)
++				VRatioPrefetchMoreThan4 = true;
++		}
++
++		if (MaxTotalRDBandwidth <= mode_lib->vba.ReturnBW && prefetch_vm_bw_valid
++				&& prefetch_row_bw_valid && !VRatioPrefetchMoreThan4
++				&& !DestinationLineTimesForPrefetchLessThan2)
++			mode_lib->vba.PrefetchModeSupported = true;
++		else {
++			mode_lib->vba.PrefetchModeSupported = false;
++			dml_print(
++					"DML: CalculatePrefetchSchedule ***failed***. Bandwidth violation. Results are NOT valid\n");
++		}
++
++		if (mode_lib->vba.PrefetchModeSupported == true) {
++			double final_flip_bw[DC__NUM_DPP__MAX];
++			unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX];
++			double total_dcn_read_bw_with_flip = 0;
++
++			mode_lib->vba.BandwidthAvailableForImmediateFlip = mode_lib->vba.ReturnBW;
++			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++				mode_lib->vba.BandwidthAvailableForImmediateFlip =
++						mode_lib->vba.BandwidthAvailableForImmediateFlip
++								- mode_lib->vba.cursor_bw[k]
++								- dml_max(
++										mode_lib->vba.ReadBandwidthPlaneLuma[k]
++												+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
++												+ mode_lib->vba.qual_row_bw[k],
++										mode_lib->vba.PrefetchBandwidth[k]);
++			}
++
++			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++				ImmediateFlipBytes[k] = 0;
++				if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
++					ImmediateFlipBytes[k] =
++							mode_lib->vba.PDEAndMetaPTEBytesFrame[k]
++									+ mode_lib->vba.MetaRowByte[k]
++									+ mode_lib->vba.PixelPTEBytesPerRow[k];
++				}
++			}
++			mode_lib->vba.TotImmediateFlipBytes = 0;
++			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++				if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
++					mode_lib->vba.TotImmediateFlipBytes =
++							mode_lib->vba.TotImmediateFlipBytes
++									+ ImmediateFlipBytes[k];
++				}
++			}
++			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++				CalculateFlipSchedule(
++						mode_lib,
++						mode_lib->vba.UrgentExtraLatency,
++						mode_lib->vba.UrgentLatencyPixelDataOnly,
++						mode_lib->vba.GPUVMMaxPageTableLevels,
++						mode_lib->vba.GPUVMEnable,
++						mode_lib->vba.BandwidthAvailableForImmediateFlip,
++						mode_lib->vba.TotImmediateFlipBytes,
++						mode_lib->vba.SourcePixelFormat[k],
++						ImmediateFlipBytes[k],
++						mode_lib->vba.HTotal[k]
++								/ mode_lib->vba.PixelClock[k],
++						mode_lib->vba.VRatio[k],
++						mode_lib->vba.Tno_bw[k],
++						mode_lib->vba.PDEAndMetaPTEBytesFrame[k],
++						mode_lib->vba.MetaRowByte[k],
++						mode_lib->vba.PixelPTEBytesPerRow[k],
++						mode_lib->vba.DCCEnable[k],
++						mode_lib->vba.dpte_row_height[k],
++						mode_lib->vba.meta_row_height[k],
++						mode_lib->vba.qual_row_bw[k],
++						&mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k],
++						&mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k],
++						&final_flip_bw[k],
++						&mode_lib->vba.ImmediateFlipSupportedForPipe[k]);
++			}
++			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++				total_dcn_read_bw_with_flip =
++						total_dcn_read_bw_with_flip
++								+ mode_lib->vba.cursor_bw[k]
++								+ dml_max(
++										mode_lib->vba.prefetch_vm_bw[k],
++										dml_max(
++												mode_lib->vba.prefetch_row_bw[k],
++												final_flip_bw[k]
++														+ dml_max(
++																mode_lib->vba.ReadBandwidthPlaneLuma[k]
++																		+ mode_lib->vba.ReadBandwidthPlaneChroma[k],
++																mode_lib->vba.RequiredPrefetchPixDataBWLuma[k])));
++			}
++			mode_lib->vba.ImmediateFlipSupported = true;
++			if (total_dcn_read_bw_with_flip > mode_lib->vba.ReturnBW) {
++				mode_lib->vba.ImmediateFlipSupported = false;
++			}
++			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++				if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) {
++					mode_lib->vba.ImmediateFlipSupported = false;
++				}
++			}
++		} else {
++			mode_lib->vba.ImmediateFlipSupported = false;
++		}
++
++		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++			if (mode_lib->vba.ErrorResult[k]) {
++				mode_lib->vba.PrefetchModeSupported = false;
++				dml_print(
++						"DML: CalculatePrefetchSchedule ***failed***. Prefetch schedule violation. Results are NOT valid\n");
++			}
++		}
++
++		mode_lib->vba.VStartupLines = mode_lib->vba.VStartupLines + 1;
++	} while (!((mode_lib->vba.PrefetchModeSupported
++			&& (!mode_lib->vba.ImmediateFlipSupport
++					|| mode_lib->vba.ImmediateFlipSupported))
++			|| mode_lib->vba.MaximumMaxVStartupLines < mode_lib->vba.VStartupLines));
++
++	//Display Pipeline Delivery Time in Prefetch
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.VRatioPrefetchY[k] <= 1) {
++			mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
++					mode_lib->vba.SwathWidthY[k] * mode_lib->vba.DPPPerPlane[k]
++							/ mode_lib->vba.HRatio[k]
++							/ mode_lib->vba.PixelClock[k];
++		} else {
++			mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
++					mode_lib->vba.SwathWidthY[k]
++							/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
++							/ mode_lib->vba.DPPCLK[k];
++		}
++		if (mode_lib->vba.BytePerPixelDETC[k] == 0) {
++			mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
++		} else {
++			if (mode_lib->vba.VRatioPrefetchC[k] <= 1) {
++				mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
++						mode_lib->vba.SwathWidthY[k]
++								* mode_lib->vba.DPPPerPlane[k]
++								/ mode_lib->vba.HRatio[k]
++								/ mode_lib->vba.PixelClock[k];
++			} else {
++				mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
++						mode_lib->vba.SwathWidthY[k]
++								/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
++								/ mode_lib->vba.DPPCLK[k];
++			}
++		}
++	}
++
++	// Min TTUVBlank
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) {
++			mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = true;
++			mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;
++			mode_lib->vba.MinTTUVBlank[k] = dml_max(
++					mode_lib->vba.DRAMClockChangeWatermark,
++					dml_max(
++							mode_lib->vba.StutterEnterPlusExitWatermark,
++							mode_lib->vba.UrgentWatermark));
++		} else if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 1) {
++			mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
++			mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;
++			mode_lib->vba.MinTTUVBlank[k] = dml_max(
++					mode_lib->vba.StutterEnterPlusExitWatermark,
++					mode_lib->vba.UrgentWatermark);
++		} else {
++			mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
++			mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = false;
++			mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark;
++		}
++		if (!mode_lib->vba.DynamicMetadataEnable[k])
++			mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.TCalc
++					+ mode_lib->vba.MinTTUVBlank[k];
++	}
++
++	// DCC Configuration
++	mode_lib->vba.ActiveDPPs = 0;
++	// NB P-State/DRAM Clock Change Support
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		mode_lib->vba.ActiveDPPs = mode_lib->vba.ActiveDPPs + mode_lib->vba.DPPPerPlane[k];
++	}
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		double EffectiveLBLatencyHidingY;
++		double EffectiveLBLatencyHidingC;
++		double DPPOutputBufferLinesY;
++		double DPPOutputBufferLinesC;
++		double DPPOPPBufferingY;
++		double MaxDETBufferingTimeY;
++		double ActiveDRAMClockChangeLatencyMarginY;
++
++		mode_lib->vba.LBLatencyHidingSourceLinesY =
++				dml_min(
++						mode_lib->vba.MaxLineBufferLines,
++						(unsigned int) dml_floor(
++								(double) mode_lib->vba.LineBufferSize
++										/ mode_lib->vba.LBBitPerPixel[k]
++										/ (mode_lib->vba.SwathWidthY[k]
++												/ dml_max(
++														mode_lib->vba.HRatio[k],
++														1.0)),
++								1)) - (mode_lib->vba.vtaps[k] - 1);
++
++		mode_lib->vba.LBLatencyHidingSourceLinesC =
++				dml_min(
++						mode_lib->vba.MaxLineBufferLines,
++						(unsigned int) dml_floor(
++								(double) mode_lib->vba.LineBufferSize
++										/ mode_lib->vba.LBBitPerPixel[k]
++										/ (mode_lib->vba.SwathWidthY[k]
++												/ 2.0
++												/ dml_max(
++														mode_lib->vba.HRatio[k]
++																/ 2,
++														1.0)),
++								1))
++						- (mode_lib->vba.VTAPsChroma[k] - 1);
++
++		EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY
++				/ mode_lib->vba.VRatio[k]
++				* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]);
++
++		EffectiveLBLatencyHidingC = mode_lib->vba.LBLatencyHidingSourceLinesC
++				/ (mode_lib->vba.VRatio[k] / 2)
++				* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]);
++
++		if (mode_lib->vba.SwathWidthY[k] > 2 * mode_lib->vba.DPPOutputBufferPixels) {
++			DPPOutputBufferLinesY = mode_lib->vba.DPPOutputBufferPixels
++					/ mode_lib->vba.SwathWidthY[k];
++		} else if (mode_lib->vba.SwathWidthY[k] > mode_lib->vba.DPPOutputBufferPixels) {
++			DPPOutputBufferLinesY = 0.5;
++		} else {
++			DPPOutputBufferLinesY = 1;
++		}
++
++		if (mode_lib->vba.SwathWidthY[k] / 2 > 2 * mode_lib->vba.DPPOutputBufferPixels) {
++			DPPOutputBufferLinesC = mode_lib->vba.DPPOutputBufferPixels
++					/ (mode_lib->vba.SwathWidthY[k] / 2);
++		} else if (mode_lib->vba.SwathWidthY[k] / 2 > mode_lib->vba.DPPOutputBufferPixels) {
++			DPPOutputBufferLinesC = 0.5;
++		} else {
++			DPPOutputBufferLinesC = 1;
++		}
++
++		DPPOPPBufferingY = (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
++				* (DPPOutputBufferLinesY + mode_lib->vba.OPPOutputBufferLines);
++		MaxDETBufferingTimeY = mode_lib->vba.FullDETBufferingTimeY[k]
++				+ (mode_lib->vba.LinesInDETY[k]
++						- mode_lib->vba.LinesInDETYRoundedDownToSwath[k])
++						/ mode_lib->vba.SwathHeightY[k]
++						* (mode_lib->vba.HTotal[k]
++								/ mode_lib->vba.PixelClock[k]);
++
++		ActiveDRAMClockChangeLatencyMarginY = DPPOPPBufferingY + EffectiveLBLatencyHidingY
++				+ MaxDETBufferingTimeY - mode_lib->vba.DRAMClockChangeWatermark;
++
++		if (mode_lib->vba.ActiveDPPs > 1) {
++			ActiveDRAMClockChangeLatencyMarginY =
++					ActiveDRAMClockChangeLatencyMarginY
++							- (1 - 1 / (mode_lib->vba.ActiveDPPs - 1))
++									* mode_lib->vba.SwathHeightY[k]
++									* (mode_lib->vba.HTotal[k]
++											/ mode_lib->vba.PixelClock[k]);
++		}
++
++		if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
++			double DPPOPPBufferingC = (mode_lib->vba.HTotal[k]
++					/ mode_lib->vba.PixelClock[k])
++					* (DPPOutputBufferLinesC
++							+ mode_lib->vba.OPPOutputBufferLines);
++			double MaxDETBufferingTimeC =
++					mode_lib->vba.FullDETBufferingTimeC[k]
++							+ (mode_lib->vba.LinesInDETC[k]
++									- mode_lib->vba.LinesInDETCRoundedDownToSwath[k])
++									/ mode_lib->vba.SwathHeightC[k]
++									* (mode_lib->vba.HTotal[k]
++											/ mode_lib->vba.PixelClock[k]);
++			double ActiveDRAMClockChangeLatencyMarginC = DPPOPPBufferingC
++					+ EffectiveLBLatencyHidingC + MaxDETBufferingTimeC
++					- mode_lib->vba.DRAMClockChangeWatermark;
++
++			if (mode_lib->vba.ActiveDPPs > 1) {
++				ActiveDRAMClockChangeLatencyMarginC =
++						ActiveDRAMClockChangeLatencyMarginC
++								- (1
++										- 1
++												/ (mode_lib->vba.ActiveDPPs
++														- 1))
++										* mode_lib->vba.SwathHeightC[k]
++										* (mode_lib->vba.HTotal[k]
++												/ mode_lib->vba.PixelClock[k]);
++			}
++			mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
++					ActiveDRAMClockChangeLatencyMarginY,
++					ActiveDRAMClockChangeLatencyMarginC);
++		} else {
++			mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] =
++					ActiveDRAMClockChangeLatencyMarginY;
++		}
++
++		if (mode_lib->vba.WritebackEnable[k]) {
++			double WritebackDRAMClockChangeLatencyMargin;
++
++			if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
++				WritebackDRAMClockChangeLatencyMargin =
++						(double) (mode_lib->vba.WritebackInterfaceLumaBufferSize
++								+ mode_lib->vba.WritebackInterfaceChromaBufferSize)
++								/ (mode_lib->vba.WritebackDestinationWidth[k]
++										* mode_lib->vba.WritebackDestinationHeight[k]
++										/ (mode_lib->vba.WritebackSourceHeight[k]
++												* mode_lib->vba.HTotal[k]
++												/ mode_lib->vba.PixelClock[k])
++										* 4)
++								- mode_lib->vba.WritebackDRAMClockChangeWatermark;
++			} else if (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
++				WritebackDRAMClockChangeLatencyMargin =
++						dml_min(
++								(double) mode_lib->vba.WritebackInterfaceLumaBufferSize
++										* 8.0 / 10,
++								2.0
++										* mode_lib->vba.WritebackInterfaceChromaBufferSize
++										* 8 / 10)
++								/ (mode_lib->vba.WritebackDestinationWidth[k]
++										* mode_lib->vba.WritebackDestinationHeight[k]
++										/ (mode_lib->vba.WritebackSourceHeight[k]
++												* mode_lib->vba.HTotal[k]
++												/ mode_lib->vba.PixelClock[k]))
++								- mode_lib->vba.WritebackDRAMClockChangeWatermark;
++			} else {
++				WritebackDRAMClockChangeLatencyMargin =
++						dml_min(
++								(double) mode_lib->vba.WritebackInterfaceLumaBufferSize,
++								2.0
++										* mode_lib->vba.WritebackInterfaceChromaBufferSize)
++								/ (mode_lib->vba.WritebackDestinationWidth[k]
++										* mode_lib->vba.WritebackDestinationHeight[k]
++										/ (mode_lib->vba.WritebackSourceHeight[k]
++												* mode_lib->vba.HTotal[k]
++												/ mode_lib->vba.PixelClock[k]))
++								- mode_lib->vba.WritebackDRAMClockChangeWatermark;
++			}
++			mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
++					mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k],
++					WritebackDRAMClockChangeLatencyMargin);
++		}
++	}
++
++	mode_lib->vba.MinActiveDRAMClockChangeMargin = 999999;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]
++				< mode_lib->vba.MinActiveDRAMClockChangeMargin) {
++			mode_lib->vba.MinActiveDRAMClockChangeMargin =
++					mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
++		}
++	}
++
++	mode_lib->vba.MinActiveDRAMClockChangeLatencySupported =
++			mode_lib->vba.MinActiveDRAMClockChangeMargin
++					+ mode_lib->vba.DRAMClockChangeLatency;
++
++	if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
++		mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
++	} else {
++		if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {
++			mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vblank;
++			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++				if (!mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k]) {
++					mode_lib->vba.DRAMClockChangeSupport[0][0] =
++							dm_dram_clock_change_unsupported;
++				}
++			}
++		} else {
++			mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_unsupported;
++		}
++	}
++	for (k = 0; k <= mode_lib->vba.soc.num_states; k++)
++		for (j = 0; j < 2; j++)
++			mode_lib->vba.DRAMClockChangeSupport[k][j] = mode_lib->vba.DRAMClockChangeSupport[0][0];
++
++	//XFC Parameters:
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.XFCEnabled[k] == true) {
++			double TWait;
++
++			mode_lib->vba.XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset;
++			mode_lib->vba.XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth;
++			mode_lib->vba.XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset;
++			TWait = CalculateTWait(
++					mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
++					mode_lib->vba.DRAMClockChangeLatency,
++					mode_lib->vba.UrgentLatencyPixelDataOnly,
++					mode_lib->vba.SREnterPlusExitTime);
++			mode_lib->vba.XFCRemoteSurfaceFlipDelay = CalculateRemoteSurfaceFlipDelay(
++					mode_lib,
++					mode_lib->vba.VRatio[k],
++					mode_lib->vba.SwathWidthY[k],
++					dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
++					mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
++					mode_lib->vba.XFCTSlvVupdateOffset,
++					mode_lib->vba.XFCTSlvVupdateWidth,
++					mode_lib->vba.XFCTSlvVreadyOffset,
++					mode_lib->vba.XFCXBUFLatencyTolerance,
++					mode_lib->vba.XFCFillBWOverhead,
++					mode_lib->vba.XFCSlvChunkSize,
++					mode_lib->vba.XFCBusTransportTime,
++					mode_lib->vba.TCalc,
++					TWait,
++					&mode_lib->vba.SrcActiveDrainRate,
++					&mode_lib->vba.TInitXFill,
++					&mode_lib->vba.TslvChk);
++			mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] =
++					dml_floor(
++							mode_lib->vba.XFCRemoteSurfaceFlipDelay
++									/ (mode_lib->vba.HTotal[k]
++											/ mode_lib->vba.PixelClock[k]),
++							1);
++			mode_lib->vba.XFCTransferDelay[k] =
++					dml_ceil(
++							mode_lib->vba.XFCBusTransportTime
++									/ (mode_lib->vba.HTotal[k]
++											/ mode_lib->vba.PixelClock[k]),
++							1);
++			mode_lib->vba.XFCPrechargeDelay[k] =
++					dml_ceil(
++							(mode_lib->vba.XFCBusTransportTime
++									+ mode_lib->vba.TInitXFill
++									+ mode_lib->vba.TslvChk)
++									/ (mode_lib->vba.HTotal[k]
++											/ mode_lib->vba.PixelClock[k]),
++							1);
++			mode_lib->vba.InitFillLevel = mode_lib->vba.XFCXBUFLatencyTolerance
++					* mode_lib->vba.SrcActiveDrainRate;
++			mode_lib->vba.FinalFillMargin =
++					(mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
++							+ mode_lib->vba.DestinationLinesToRequestRowInVBlank[k])
++							* mode_lib->vba.HTotal[k]
++							/ mode_lib->vba.PixelClock[k]
++							* mode_lib->vba.SrcActiveDrainRate
++							+ mode_lib->vba.XFCFillConstant;
++			mode_lib->vba.FinalFillLevel = mode_lib->vba.XFCRemoteSurfaceFlipDelay
++					* mode_lib->vba.SrcActiveDrainRate
++					+ mode_lib->vba.FinalFillMargin;
++			mode_lib->vba.RemainingFillLevel = dml_max(
++					0.0,
++					mode_lib->vba.FinalFillLevel - mode_lib->vba.InitFillLevel);
++			mode_lib->vba.TFinalxFill = mode_lib->vba.RemainingFillLevel
++					/ (mode_lib->vba.SrcActiveDrainRate
++							* mode_lib->vba.XFCFillBWOverhead / 100);
++			mode_lib->vba.XFCPrefetchMargin[k] =
++					mode_lib->vba.XFCRemoteSurfaceFlipDelay
++							+ mode_lib->vba.TFinalxFill
++							+ (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
++									+ mode_lib->vba.DestinationLinesToRequestRowInVBlank[k])
++									* mode_lib->vba.HTotal[k]
++									/ mode_lib->vba.PixelClock[k];
++		} else {
++			mode_lib->vba.XFCSlaveVUpdateOffset[k] = 0;
++			mode_lib->vba.XFCSlaveVupdateWidth[k] = 0;
++			mode_lib->vba.XFCSlaveVReadyOffset[k] = 0;
++			mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] = 0;
++			mode_lib->vba.XFCPrechargeDelay[k] = 0;
++			mode_lib->vba.XFCTransferDelay[k] = 0;
++			mode_lib->vba.XFCPrefetchMargin[k] = 0;
++		}
++	}
++	{
++		unsigned int VStartupMargin = 0;
++		bool FirstMainPlane = true;
++
++		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++			if (mode_lib->vba.BlendingAndTiming[k] == k) {
++				unsigned int Margin = (mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k])
++						* mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k];
++
++				if (FirstMainPlane) {
++					VStartupMargin = Margin;
++					FirstMainPlane = false;
++				} else
++					VStartupMargin = dml_min(VStartupMargin, Margin);
++		}
++
++		if (mode_lib->vba.UseMaximumVStartup) {
++			if (mode_lib->vba.VTotal_Max[k] == mode_lib->vba.VTotal[k]) {
++				//only use max vstart if it is not drr or lateflip.
++				mode_lib->vba.VStartup[k] = mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]];
++			}
++		}
++	}
++}
++}
++
++static void dml20v2_DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
++{
++	double BytePerPixDETY;
++	double BytePerPixDETC;
++	double Read256BytesBlockHeightY;
++	double Read256BytesBlockHeightC;
++	double Read256BytesBlockWidthY;
++	double Read256BytesBlockWidthC;
++	double MaximumSwathHeightY;
++	double MaximumSwathHeightC;
++	double MinimumSwathHeightY;
++	double MinimumSwathHeightC;
++	double SwathWidth;
++	double SwathWidthGranularityY;
++	double SwathWidthGranularityC;
++	double RoundedUpMaxSwathSizeBytesY;
++	double RoundedUpMaxSwathSizeBytesC;
++	unsigned int j, k;
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		bool MainPlaneDoesODMCombine = false;
++
++		if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
++			BytePerPixDETY = 8;
++			BytePerPixDETC = 0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
++			BytePerPixDETY = 4;
++			BytePerPixDETC = 0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
++			BytePerPixDETY = 2;
++			BytePerPixDETC = 0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) {
++			BytePerPixDETY = 1;
++			BytePerPixDETC = 0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
++			BytePerPixDETY = 1;
++			BytePerPixDETC = 2;
++		} else {
++			BytePerPixDETY = 4.0 / 3.0;
++			BytePerPixDETC = 8.0 / 3.0;
++		}
++
++		if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
++			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
++				Read256BytesBlockHeightY = 1;
++			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
++				Read256BytesBlockHeightY = 4;
++			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32
++					|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
++				Read256BytesBlockHeightY = 8;
++			} else {
++				Read256BytesBlockHeightY = 16;
++			}
++			Read256BytesBlockWidthY = 256 / dml_ceil(BytePerPixDETY, 1)
++					/ Read256BytesBlockHeightY;
++			Read256BytesBlockHeightC = 0;
++			Read256BytesBlockWidthC = 0;
++		} else {
++			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
++				Read256BytesBlockHeightY = 1;
++				Read256BytesBlockHeightC = 1;
++			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
++				Read256BytesBlockHeightY = 16;
++				Read256BytesBlockHeightC = 8;
++			} else {
++				Read256BytesBlockHeightY = 8;
++				Read256BytesBlockHeightC = 8;
++			}
++			Read256BytesBlockWidthY = 256 / dml_ceil(BytePerPixDETY, 1)
++					/ Read256BytesBlockHeightY;
++			Read256BytesBlockWidthC = 256 / dml_ceil(BytePerPixDETC, 2)
++					/ Read256BytesBlockHeightC;
++		}
++
++		if (mode_lib->vba.SourceScan[k] == dm_horz) {
++			MaximumSwathHeightY = Read256BytesBlockHeightY;
++			MaximumSwathHeightC = Read256BytesBlockHeightC;
++		} else {
++			MaximumSwathHeightY = Read256BytesBlockWidthY;
++			MaximumSwathHeightC = Read256BytesBlockWidthC;
++		}
++
++		if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
++			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
++					|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
++							&& (mode_lib->vba.SurfaceTiling[k]
++									== dm_sw_4kb_s
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_4kb_s_x
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_64kb_s
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_64kb_s_t
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_64kb_s_x
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_var_s
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_var_s_x)
++							&& mode_lib->vba.SourceScan[k] == dm_horz)) {
++				MinimumSwathHeightY = MaximumSwathHeightY;
++			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8
++					&& mode_lib->vba.SourceScan[k] != dm_horz) {
++				MinimumSwathHeightY = MaximumSwathHeightY;
++			} else {
++				MinimumSwathHeightY = MaximumSwathHeightY / 2.0;
++			}
++			MinimumSwathHeightC = MaximumSwathHeightC;
++		} else {
++			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
++				MinimumSwathHeightY = MaximumSwathHeightY;
++				MinimumSwathHeightC = MaximumSwathHeightC;
++			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
++					&& mode_lib->vba.SourceScan[k] == dm_horz) {
++				MinimumSwathHeightY = MaximumSwathHeightY / 2.0;
++				MinimumSwathHeightC = MaximumSwathHeightC;
++			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
++					&& mode_lib->vba.SourceScan[k] == dm_horz) {
++				MinimumSwathHeightC = MaximumSwathHeightC / 2.0;
++				MinimumSwathHeightY = MaximumSwathHeightY;
++			} else {
++				MinimumSwathHeightY = MaximumSwathHeightY;
++				MinimumSwathHeightC = MaximumSwathHeightC;
++			}
++		}
++
++		if (mode_lib->vba.SourceScan[k] == dm_horz) {
++			SwathWidth = mode_lib->vba.ViewportWidth[k];
++		} else {
++			SwathWidth = mode_lib->vba.ViewportHeight[k];
++		}
++
++		if (mode_lib->vba.ODMCombineEnabled[k] == true) {
++			MainPlaneDoesODMCombine = true;
++		}
++		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) {
++			if (mode_lib->vba.BlendingAndTiming[k] == j
++					&& mode_lib->vba.ODMCombineEnabled[j] == true) {
++				MainPlaneDoesODMCombine = true;
++			}
++		}
++
++		if (MainPlaneDoesODMCombine == true) {
++			SwathWidth = dml_min(
++					SwathWidth,
++					mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]);
++		} else {
++			if (mode_lib->vba.DPPPerPlane[k] == 0)
++				SwathWidth = 0;
++			else
++				SwathWidth = SwathWidth / mode_lib->vba.DPPPerPlane[k];
++		}
++
++		SwathWidthGranularityY = 256 / dml_ceil(BytePerPixDETY, 1) / MaximumSwathHeightY;
++		RoundedUpMaxSwathSizeBytesY = (dml_ceil(
++				(double) (SwathWidth - 1),
++				SwathWidthGranularityY) + SwathWidthGranularityY) * BytePerPixDETY
++				* MaximumSwathHeightY;
++		if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
++			RoundedUpMaxSwathSizeBytesY = dml_ceil(RoundedUpMaxSwathSizeBytesY, 256)
++					+ 256;
++		}
++		if (MaximumSwathHeightC > 0) {
++			SwathWidthGranularityC = 256.0 / dml_ceil(BytePerPixDETC, 2)
++					/ MaximumSwathHeightC;
++			RoundedUpMaxSwathSizeBytesC = (dml_ceil(
++					(double) (SwathWidth / 2.0 - 1),
++					SwathWidthGranularityC) + SwathWidthGranularityC)
++					* BytePerPixDETC * MaximumSwathHeightC;
++			if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
++				RoundedUpMaxSwathSizeBytesC = dml_ceil(
++						RoundedUpMaxSwathSizeBytesC,
++						256) + 256;
++			}
++		} else
++			RoundedUpMaxSwathSizeBytesC = 0.0;
++
++		if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC
++				<= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) {
++			mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY;
++			mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC;
++		} else {
++			mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY;
++			mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC;
++		}
++
++		if (mode_lib->vba.SwathHeightC[k] == 0) {
++			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte * 1024;
++			mode_lib->vba.DETBufferSizeC[k] = 0;
++		} else if (mode_lib->vba.SwathHeightY[k] <= mode_lib->vba.SwathHeightC[k]) {
++			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte
++					* 1024.0 / 2;
++			mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte
++					* 1024.0 / 2;
++		} else {
++			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte
++					* 1024.0 * 2 / 3;
++			mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte
++					* 1024.0 / 3;
++		}
++	}
++}
++
++static double CalculateTWait(
++		unsigned int PrefetchMode,
++		double DRAMClockChangeLatency,
++		double UrgentLatencyPixelDataOnly,
++		double SREnterPlusExitTime)
++{
++	if (PrefetchMode == 0) {
++		return dml_max(
++				DRAMClockChangeLatency + UrgentLatencyPixelDataOnly,
++				dml_max(SREnterPlusExitTime, UrgentLatencyPixelDataOnly));
++	} else if (PrefetchMode == 1) {
++		return dml_max(SREnterPlusExitTime, UrgentLatencyPixelDataOnly);
++	} else {
++		return UrgentLatencyPixelDataOnly;
++	}
++}
++
++static double CalculateRemoteSurfaceFlipDelay(
++		struct display_mode_lib *mode_lib,
++		double VRatio,
++		double SwathWidth,
++		double Bpp,
++		double LineTime,
++		double XFCTSlvVupdateOffset,
++		double XFCTSlvVupdateWidth,
++		double XFCTSlvVreadyOffset,
++		double XFCXBUFLatencyTolerance,
++		double XFCFillBWOverhead,
++		double XFCSlvChunkSize,
++		double XFCBusTransportTime,
++		double TCalc,
++		double TWait,
++		double *SrcActiveDrainRate,
++		double *TInitXFill,
++		double *TslvChk)
++{
++	double TSlvSetup, AvgfillRate, result;
++
++	*SrcActiveDrainRate = VRatio * SwathWidth * Bpp / LineTime;
++	TSlvSetup = XFCTSlvVupdateOffset + XFCTSlvVupdateWidth + XFCTSlvVreadyOffset;
++	*TInitXFill = XFCXBUFLatencyTolerance / (1 + XFCFillBWOverhead / 100);
++	AvgfillRate = *SrcActiveDrainRate * (1 + XFCFillBWOverhead / 100);
++	*TslvChk = XFCSlvChunkSize / AvgfillRate;
++	dml_print(
++			"DML::CalculateRemoteSurfaceFlipDelay: SrcActiveDrainRate: %f\n",
++			*SrcActiveDrainRate);
++	dml_print("DML::CalculateRemoteSurfaceFlipDelay: TSlvSetup: %f\n", TSlvSetup);
++	dml_print("DML::CalculateRemoteSurfaceFlipDelay: TInitXFill: %f\n", *TInitXFill);
++	dml_print("DML::CalculateRemoteSurfaceFlipDelay: AvgfillRate: %f\n", AvgfillRate);
++	dml_print("DML::CalculateRemoteSurfaceFlipDelay: TslvChk: %f\n", *TslvChk);
++	result = 2 * XFCBusTransportTime + TSlvSetup + TCalc + TWait + *TslvChk + *TInitXFill; // TODO: This doesn't seem to match programming guide
++	dml_print("DML::CalculateRemoteSurfaceFlipDelay: RemoteSurfaceFlipDelay: %f\n", result);
++	return result;
++}
++
++static double CalculateWriteBackDelay(
++		enum source_format_class WritebackPixelFormat,
++		double WritebackHRatio,
++		double WritebackVRatio,
++		unsigned int WritebackLumaHTaps,
++		unsigned int WritebackLumaVTaps,
++		unsigned int WritebackChromaHTaps,
++		unsigned int WritebackChromaVTaps,
++		unsigned int WritebackDestinationWidth)
++{
++	double CalculateWriteBackDelay =
++			dml_max(
++					dml_ceil(WritebackLumaHTaps / 4.0, 1) / WritebackHRatio,
++					WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 1)
++							* dml_ceil(
++									WritebackDestinationWidth
++											/ 4.0,
++									1)
++							+ dml_ceil(1.0 / WritebackVRatio, 1)
++									* (dml_ceil(
++											WritebackLumaVTaps
++													/ 4.0,
++											1) + 4));
++
++	if (WritebackPixelFormat != dm_444_32) {
++		CalculateWriteBackDelay =
++				dml_max(
++						CalculateWriteBackDelay,
++						dml_max(
++								dml_ceil(
++										WritebackChromaHTaps
++												/ 2.0,
++										1)
++										/ (2
++												* WritebackHRatio),
++								WritebackChromaVTaps
++										* dml_ceil(
++												1
++														/ (2
++																* WritebackVRatio),
++												1)
++										* dml_ceil(
++												WritebackDestinationWidth
++														/ 2.0
++														/ 2.0,
++												1)
++										+ dml_ceil(
++												1
++														/ (2
++																* WritebackVRatio),
++												1)
++												* (dml_ceil(
++														WritebackChromaVTaps
++																/ 4.0,
++														1)
++														+ 4)));
++	}
++	return CalculateWriteBackDelay;
++}
++
++static void CalculateActiveRowBandwidth(
++		bool GPUVMEnable,
++		enum source_format_class SourcePixelFormat,
++		double VRatio,
++		bool DCCEnable,
++		double LineTime,
++		unsigned int MetaRowByteLuma,
++		unsigned int MetaRowByteChroma,
++		unsigned int meta_row_height_luma,
++		unsigned int meta_row_height_chroma,
++		unsigned int PixelPTEBytesPerRowLuma,
++		unsigned int PixelPTEBytesPerRowChroma,
++		unsigned int dpte_row_height_luma,
++		unsigned int dpte_row_height_chroma,
++		double *meta_row_bw,
++		double *dpte_row_bw,
++		double *qual_row_bw)
++{
++	if (DCCEnable != true) {
++		*meta_row_bw = 0;
++	} else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) {
++		*meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime)
++				+ VRatio / 2 * MetaRowByteChroma
++						/ (meta_row_height_chroma * LineTime);
++	} else {
++		*meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime);
++	}
++
++	if (GPUVMEnable != true) {
++		*dpte_row_bw = 0;
++	} else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) {
++		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime)
++				+ VRatio / 2 * PixelPTEBytesPerRowChroma
++						/ (dpte_row_height_chroma * LineTime);
++	} else {
++		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime);
++	}
++
++	if ((SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10)) {
++		*qual_row_bw = *meta_row_bw + *dpte_row_bw;
++	} else {
++		*qual_row_bw = 0;
++	}
++}
++
++static void CalculateFlipSchedule(
++		struct display_mode_lib *mode_lib,
++		double UrgentExtraLatency,
++		double UrgentLatencyPixelDataOnly,
++		unsigned int GPUVMMaxPageTableLevels,
++		bool GPUVMEnable,
++		double BandwidthAvailableForImmediateFlip,
++		unsigned int TotImmediateFlipBytes,
++		enum source_format_class SourcePixelFormat,
++		unsigned int ImmediateFlipBytes,
++		double LineTime,
++		double VRatio,
++		double Tno_bw,
++		double PDEAndMetaPTEBytesFrame,
++		unsigned int MetaRowByte,
++		unsigned int PixelPTEBytesPerRow,
++		bool DCCEnable,
++		unsigned int dpte_row_height,
++		unsigned int meta_row_height,
++		double qual_row_bw,
++		double *DestinationLinesToRequestVMInImmediateFlip,
++		double *DestinationLinesToRequestRowInImmediateFlip,
++		double *final_flip_bw,
++		bool *ImmediateFlipSupportedForPipe)
++{
++	double min_row_time = 0.0;
++
++	if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) {
++		*DestinationLinesToRequestVMInImmediateFlip = 0.0;
++		*DestinationLinesToRequestRowInImmediateFlip = 0.0;
++		*final_flip_bw = qual_row_bw;
++		*ImmediateFlipSupportedForPipe = true;
++	} else {
++		double TimeForFetchingMetaPTEImmediateFlip;
++		double TimeForFetchingRowInVBlankImmediateFlip;
++
++		if (GPUVMEnable == true) {
++			mode_lib->vba.ImmediateFlipBW[0] = BandwidthAvailableForImmediateFlip
++					* ImmediateFlipBytes / TotImmediateFlipBytes;
++			TimeForFetchingMetaPTEImmediateFlip =
++					dml_max(
++							Tno_bw
++									+ PDEAndMetaPTEBytesFrame
++											/ mode_lib->vba.ImmediateFlipBW[0],
++							dml_max(
++									UrgentExtraLatency
++											+ UrgentLatencyPixelDataOnly
++													* (GPUVMMaxPageTableLevels
++															- 1),
++									LineTime / 4.0));
++		} else {
++			TimeForFetchingMetaPTEImmediateFlip = 0;
++		}
++
++		*DestinationLinesToRequestVMInImmediateFlip = dml_floor(
++				4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime + 0.125),
++				1) / 4.0;
++
++		if ((GPUVMEnable == true || DCCEnable == true)) {
++			mode_lib->vba.ImmediateFlipBW[0] = BandwidthAvailableForImmediateFlip
++					* ImmediateFlipBytes / TotImmediateFlipBytes;
++			TimeForFetchingRowInVBlankImmediateFlip = dml_max(
++					(MetaRowByte + PixelPTEBytesPerRow)
++							/ mode_lib->vba.ImmediateFlipBW[0],
++					dml_max(UrgentLatencyPixelDataOnly, LineTime / 4.0));
++		} else {
++			TimeForFetchingRowInVBlankImmediateFlip = 0;
++		}
++
++		*DestinationLinesToRequestRowInImmediateFlip = dml_floor(
++				4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime + 0.125),
++				1) / 4.0;
++
++		if (GPUVMEnable == true) {
++			*final_flip_bw =
++					dml_max(
++							PDEAndMetaPTEBytesFrame
++									/ (*DestinationLinesToRequestVMInImmediateFlip
++											* LineTime),
++							(MetaRowByte + PixelPTEBytesPerRow)
++									/ (TimeForFetchingRowInVBlankImmediateFlip
++											* LineTime));
++		} else if (MetaRowByte + PixelPTEBytesPerRow > 0) {
++			*final_flip_bw = (MetaRowByte + PixelPTEBytesPerRow)
++					/ (TimeForFetchingRowInVBlankImmediateFlip * LineTime);
++		} else {
++			*final_flip_bw = 0;
++		}
++
++		if (GPUVMEnable && !DCCEnable)
++			min_row_time = dpte_row_height * LineTime / VRatio;
++		else if (!GPUVMEnable && DCCEnable)
++			min_row_time = meta_row_height * LineTime / VRatio;
++		else
++			min_row_time = dml_min(dpte_row_height, meta_row_height) * LineTime
++					/ VRatio;
++
++		if (*DestinationLinesToRequestVMInImmediateFlip >= 8
++				|| *DestinationLinesToRequestRowInImmediateFlip >= 16
++				|| TimeForFetchingMetaPTEImmediateFlip
++						+ 2 * TimeForFetchingRowInVBlankImmediateFlip
++						> min_row_time)
++			*ImmediateFlipSupportedForPipe = false;
++		else
++			*ImmediateFlipSupportedForPipe = true;
++	}
++}
++
++static unsigned int TruncToValidBPP(
++		double DecimalBPP,
++		bool DSCEnabled,
++		enum output_encoder_class Output,
++		enum output_format_class Format,
++		unsigned int DSCInputBitPerComponent)
++{
++	if (Output == dm_hdmi) {
++		if (Format == dm_420) {
++			if (DecimalBPP >= 18)
++				return 18;
++			else if (DecimalBPP >= 15)
++				return 15;
++			else if (DecimalBPP >= 12)
++				return 12;
++			else
++				return BPP_INVALID;
++		} else if (Format == dm_444) {
++			if (DecimalBPP >= 36)
++				return 36;
++			else if (DecimalBPP >= 30)
++				return 30;
++			else if (DecimalBPP >= 24)
++				return 24;
++			else if (DecimalBPP >= 18)
++				return 18;
++			else
++				return BPP_INVALID;
++		} else {
++			if (DecimalBPP / 1.5 >= 24)
++				return 24;
++			else if (DecimalBPP / 1.5 >= 20)
++				return 20;
++			else if (DecimalBPP / 1.5 >= 16)
++				return 16;
++			else
++				return BPP_INVALID;
++		}
++	} else {
++		if (DSCEnabled) {
++			if (Format == dm_420) {
++				if (DecimalBPP < 6)
++					return BPP_INVALID;
++				else if (DecimalBPP >= 1.5 * DSCInputBitPerComponent - 1 / 16)
++					return 1.5 * DSCInputBitPerComponent - 1 / 16;
++				else
++					return dml_floor(16 * DecimalBPP, 1) / 16;
++			} else if (Format == dm_n422) {
++				if (DecimalBPP < 7)
++					return BPP_INVALID;
++				else if (DecimalBPP >= 2 * DSCInputBitPerComponent - 1 / 16)
++					return 2 * DSCInputBitPerComponent - 1 / 16;
++				else
++					return dml_floor(16 * DecimalBPP, 1) / 16;
++			} else {
++				if (DecimalBPP < 8)
++					return BPP_INVALID;
++				else if (DecimalBPP >= 3 * DSCInputBitPerComponent - 1 / 16)
++					return 3 * DSCInputBitPerComponent - 1 / 16;
++				else
++					return dml_floor(16 * DecimalBPP, 1) / 16;
++			}
++		} else if (Format == dm_420) {
++			if (DecimalBPP >= 18)
++				return 18;
++			else if (DecimalBPP >= 15)
++				return 15;
++			else if (DecimalBPP >= 12)
++				return 12;
++			else
++				return BPP_INVALID;
++		} else if (Format == dm_s422 || Format == dm_n422) {
++			if (DecimalBPP >= 24)
++				return 24;
++			else if (DecimalBPP >= 20)
++				return 20;
++			else if (DecimalBPP >= 16)
++				return 16;
++			else
++				return BPP_INVALID;
++		} else {
++			if (DecimalBPP >= 36)
++				return 36;
++			else if (DecimalBPP >= 30)
++				return 30;
++			else if (DecimalBPP >= 24)
++				return 24;
++			else if (DecimalBPP >= 18)
++				return 18;
++			else
++				return BPP_INVALID;
++		}
++	}
++}
++
++void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
++{
++	struct vba_vars_st *locals = &mode_lib->vba;
++
++	int i;
++	unsigned int j, k, m;
++
++	/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/
++
++	/*Scale Ratio, taps Support Check*/
++
++	mode_lib->vba.ScaleRatioAndTapsSupport = true;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.ScalerEnabled[k] == false
++				&& ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)
++						|| mode_lib->vba.HRatio[k] != 1.0
++						|| mode_lib->vba.htaps[k] != 1.0
++						|| mode_lib->vba.VRatio[k] != 1.0
++						|| mode_lib->vba.vtaps[k] != 1.0)) {
++			mode_lib->vba.ScaleRatioAndTapsSupport = false;
++		} else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0
++				|| mode_lib->vba.htaps[k] < 1.0 || mode_lib->vba.htaps[k] > 8.0
++				|| (mode_lib->vba.htaps[k] > 1.0
++						&& (mode_lib->vba.htaps[k] % 2) == 1)
++				|| mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio
++				|| mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio
++				|| mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k]
++				|| mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k]
++				|| (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
++						&& (mode_lib->vba.HRatio[k] / 2.0
++								> mode_lib->vba.HTAPsChroma[k]
++								|| mode_lib->vba.VRatio[k] / 2.0
++										> mode_lib->vba.VTAPsChroma[k]))) {
++			mode_lib->vba.ScaleRatioAndTapsSupport = false;
++		}
++	}
++	/*Source Format, Pixel Format and Scan Support Check*/
++
++	mode_lib->vba.SourceFormatPixelAndScanSupport = true;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
++				&& mode_lib->vba.SourceScan[k] != dm_horz)
++				|| ((mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d
++						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d_x
++						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d
++						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_t
++						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_x
++						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d
++						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d_x)
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_64)
++				|| (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x
++						&& (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8
++								|| mode_lib->vba.SourcePixelFormat[k]
++										== dm_420_8
++								|| mode_lib->vba.SourcePixelFormat[k]
++										== dm_420_10))
++				|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
++						|| mode_lib->vba.SurfaceTiling[k]
++								== dm_sw_gfx7_2d_thin_lvp)
++						&& !((mode_lib->vba.SourcePixelFormat[k]
++								== dm_444_64
++								|| mode_lib->vba.SourcePixelFormat[k]
++										== dm_444_32)
++								&& mode_lib->vba.SourceScan[k]
++										== dm_horz
++								&& mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
++										== true
++								&& mode_lib->vba.DCCEnable[k]
++										== false))
++						|| (mode_lib->vba.DCCEnable[k] == true
++								&& (mode_lib->vba.SurfaceTiling[k]
++										== dm_sw_linear
++										|| mode_lib->vba.SourcePixelFormat[k]
++												== dm_420_8
++										|| mode_lib->vba.SourcePixelFormat[k]
++												== dm_420_10)))) {
++			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
++		}
++	}
++	/*Bandwidth Support Check*/
++
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
++			locals->BytePerPixelInDETY[k] = 8.0;
++			locals->BytePerPixelInDETC[k] = 0.0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
++			locals->BytePerPixelInDETY[k] = 4.0;
++			locals->BytePerPixelInDETC[k] = 0.0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) {
++			locals->BytePerPixelInDETY[k] = 2.0;
++			locals->BytePerPixelInDETC[k] = 0.0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) {
++			locals->BytePerPixelInDETY[k] = 1.0;
++			locals->BytePerPixelInDETC[k] = 0.0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
++			locals->BytePerPixelInDETY[k] = 1.0;
++			locals->BytePerPixelInDETC[k] = 2.0;
++		} else {
++			locals->BytePerPixelInDETY[k] = 4.0 / 3;
++			locals->BytePerPixelInDETC[k] = 8.0 / 3;
++		}
++		if (mode_lib->vba.SourceScan[k] == dm_horz) {
++			locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k];
++		} else {
++			locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k];
++		}
++	}
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		locals->ReadBandwidthLuma[k] = locals->SwathWidthYSingleDPP[k] * dml_ceil(locals->BytePerPixelInDETY[k], 1.0)
++				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
++		locals->ReadBandwidthChroma[k] = locals->SwathWidthYSingleDPP[k] / 2 * dml_ceil(locals->BytePerPixelInDETC[k], 2.0)
++				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] / 2.0;
++		locals->ReadBandwidth[k] = locals->ReadBandwidthLuma[k] + locals->ReadBandwidthChroma[k];
++	}
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.WritebackEnable[k] == true
++				&& mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
++			locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
++					* mode_lib->vba.WritebackDestinationHeight[k]
++					/ (mode_lib->vba.WritebackSourceHeight[k]
++							* mode_lib->vba.HTotal[k]
++							/ mode_lib->vba.PixelClock[k]) * 4.0;
++		} else if (mode_lib->vba.WritebackEnable[k] == true
++				&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
++			locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
++					* mode_lib->vba.WritebackDestinationHeight[k]
++					/ (mode_lib->vba.WritebackSourceHeight[k]
++							* mode_lib->vba.HTotal[k]
++							/ mode_lib->vba.PixelClock[k]) * 3.0;
++		} else if (mode_lib->vba.WritebackEnable[k] == true) {
++			locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
++					* mode_lib->vba.WritebackDestinationHeight[k]
++					/ (mode_lib->vba.WritebackSourceHeight[k]
++							* mode_lib->vba.HTotal[k]
++							/ mode_lib->vba.PixelClock[k]) * 1.5;
++		} else {
++			locals->WriteBandwidth[k] = 0.0;
++		}
++	}
++	mode_lib->vba.DCCEnabledInAnyPlane = false;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.DCCEnable[k] == true) {
++			mode_lib->vba.DCCEnabledInAnyPlane = true;
++		}
++	}
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		locals->FabricAndDRAMBandwidthPerState[i] = dml_min(
++				mode_lib->vba.DRAMSpeedPerState[i] * mode_lib->vba.NumberOfChannels
++						* mode_lib->vba.DRAMChannelWidth,
++				mode_lib->vba.FabricClockPerState[i]
++						* mode_lib->vba.FabricDatapathToDCNDataReturn) / 1000;
++		locals->ReturnBWToDCNPerState = dml_min(locals->ReturnBusWidth * locals->DCFCLKPerState[i],
++				locals->FabricAndDRAMBandwidthPerState[i] * 1000)
++				* locals->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly / 100;
++
++		locals->ReturnBWPerState[i] = locals->ReturnBWToDCNPerState;
++
++		if (locals->DCCEnabledInAnyPlane == true && locals->ReturnBWToDCNPerState > locals->DCFCLKPerState[i] * locals->ReturnBusWidth / 4) {
++			locals->ReturnBWPerState[i] = dml_min(locals->ReturnBWPerState[i],
++					locals->ReturnBWToDCNPerState * 4 * (1 - locals->UrgentLatency /
++					((locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024
++					/ (locals->ReturnBWToDCNPerState - locals->DCFCLKPerState[i]
++					* locals->ReturnBusWidth / 4) + locals->UrgentLatency)));
++		}
++		locals->CriticalPoint = 2 * locals->ReturnBusWidth * locals->DCFCLKPerState[i] *
++				locals->UrgentLatency / (locals->ReturnBWToDCNPerState * locals->UrgentLatency
++				+ (locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024);
++
++		if (locals->DCCEnabledInAnyPlane && locals->CriticalPoint > 1 && locals->CriticalPoint < 4) {
++			locals->ReturnBWPerState[i] = dml_min(locals->ReturnBWPerState[i],
++				4 * locals->ReturnBWToDCNPerState *
++				(locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024
++				* locals->ReturnBusWidth * locals->DCFCLKPerState[i] * locals->UrgentLatency /
++				dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency
++				+ (locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024), 2));
++		}
++
++		locals->ReturnBWToDCNPerState = dml_min(locals->ReturnBusWidth *
++				locals->DCFCLKPerState[i], locals->FabricAndDRAMBandwidthPerState[i] * 1000);
++
++		if (locals->DCCEnabledInAnyPlane == true && locals->ReturnBWToDCNPerState > locals->DCFCLKPerState[i] * locals->ReturnBusWidth / 4) {
++			locals->ReturnBWPerState[i] = dml_min(locals->ReturnBWPerState[i],
++					locals->ReturnBWToDCNPerState * 4 * (1 - locals->UrgentLatency /
++					((locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024
++					/ (locals->ReturnBWToDCNPerState - locals->DCFCLKPerState[i]
++					* locals->ReturnBusWidth / 4) + locals->UrgentLatency)));
++		}
++		locals->CriticalPoint = 2 * locals->ReturnBusWidth * locals->DCFCLKPerState[i] *
++				locals->UrgentLatency / (locals->ReturnBWToDCNPerState * locals->UrgentLatency
++				+ (locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024);
++
++		if (locals->DCCEnabledInAnyPlane && locals->CriticalPoint > 1 && locals->CriticalPoint < 4) {
++			locals->ReturnBWPerState[i] = dml_min(locals->ReturnBWPerState[i],
++				4 * locals->ReturnBWToDCNPerState *
++				(locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024
++				* locals->ReturnBusWidth * locals->DCFCLKPerState[i] * locals->UrgentLatency /
++				dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency
++				+ (locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024), 2));
++		}
++	}
++	/*Writeback Latency support check*/
++
++	mode_lib->vba.WritebackLatencySupport = true;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.WritebackEnable[k] == true) {
++			if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
++				if (locals->WriteBandwidth[k]
++						> (mode_lib->vba.WritebackInterfaceLumaBufferSize
++								+ mode_lib->vba.WritebackInterfaceChromaBufferSize)
++								/ mode_lib->vba.WritebackLatency) {
++					mode_lib->vba.WritebackLatencySupport = false;
++				}
++			} else {
++				if (locals->WriteBandwidth[k]
++						> 1.5
++								* dml_min(
++										mode_lib->vba.WritebackInterfaceLumaBufferSize,
++										2.0
++												* mode_lib->vba.WritebackInterfaceChromaBufferSize)
++								/ mode_lib->vba.WritebackLatency) {
++					mode_lib->vba.WritebackLatencySupport = false;
++				}
++			}
++		}
++	}
++	/*Re-ordering Buffer Support Check*/
++
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		locals->UrgentRoundTripAndOutOfOrderLatencyPerState[i] =
++				(mode_lib->vba.RoundTripPingLatencyCycles + 32.0) / mode_lib->vba.DCFCLKPerState[i]
++				+ locals->UrgentOutOfOrderReturnPerChannel * mode_lib->vba.NumberOfChannels / locals->ReturnBWPerState[i];
++		if ((mode_lib->vba.ROBBufferSizeInKByte - mode_lib->vba.PixelChunkSizeInKByte) * 1024.0 / locals->ReturnBWPerState[i]
++				> locals->UrgentRoundTripAndOutOfOrderLatencyPerState[i]) {
++			locals->ROBSupport[i] = true;
++		} else {
++			locals->ROBSupport[i] = false;
++		}
++	}
++	/*Writeback Mode Support Check*/
++
++	mode_lib->vba.TotalNumberOfActiveWriteback = 0;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.WritebackEnable[k] == true) {
++			if (mode_lib->vba.ActiveWritebacksPerPlane[k] == 0)
++				mode_lib->vba.ActiveWritebacksPerPlane[k] = 1;
++			mode_lib->vba.TotalNumberOfActiveWriteback =
++					mode_lib->vba.TotalNumberOfActiveWriteback
++							+ mode_lib->vba.ActiveWritebacksPerPlane[k];
++		}
++	}
++	mode_lib->vba.WritebackModeSupport = true;
++	if (mode_lib->vba.TotalNumberOfActiveWriteback > mode_lib->vba.MaxNumWriteback) {
++		mode_lib->vba.WritebackModeSupport = false;
++	}
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.WritebackEnable[k] == true
++				&& mode_lib->vba.Writeback10bpc420Supported != true
++				&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
++			mode_lib->vba.WritebackModeSupport = false;
++		}
++	}
++	/*Writeback Scale Ratio and Taps Support Check*/
++
++	mode_lib->vba.WritebackScaleRatioAndTapsSupport = true;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.WritebackEnable[k] == true) {
++			if (mode_lib->vba.WritebackLumaAndChromaScalingSupported == false
++					&& (mode_lib->vba.WritebackHRatio[k] != 1.0
++							|| mode_lib->vba.WritebackVRatio[k] != 1.0)) {
++				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
++			}
++			if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio
++					|| mode_lib->vba.WritebackVRatio[k]
++							> mode_lib->vba.WritebackMaxVSCLRatio
++					|| mode_lib->vba.WritebackHRatio[k]
++							< mode_lib->vba.WritebackMinHSCLRatio
++					|| mode_lib->vba.WritebackVRatio[k]
++							< mode_lib->vba.WritebackMinVSCLRatio
++					|| mode_lib->vba.WritebackLumaHTaps[k]
++							> mode_lib->vba.WritebackMaxHSCLTaps
++					|| mode_lib->vba.WritebackLumaVTaps[k]
++							> mode_lib->vba.WritebackMaxVSCLTaps
++					|| mode_lib->vba.WritebackHRatio[k]
++							> mode_lib->vba.WritebackLumaHTaps[k]
++					|| mode_lib->vba.WritebackVRatio[k]
++							> mode_lib->vba.WritebackLumaVTaps[k]
++					|| (mode_lib->vba.WritebackLumaHTaps[k] > 2.0
++							&& ((mode_lib->vba.WritebackLumaHTaps[k] % 2)
++									== 1))
++					|| (mode_lib->vba.WritebackPixelFormat[k] != dm_444_32
++							&& (mode_lib->vba.WritebackChromaHTaps[k]
++									> mode_lib->vba.WritebackMaxHSCLTaps
++									|| mode_lib->vba.WritebackChromaVTaps[k]
++											> mode_lib->vba.WritebackMaxVSCLTaps
++									|| 2.0
++											* mode_lib->vba.WritebackHRatio[k]
++											> mode_lib->vba.WritebackChromaHTaps[k]
++									|| 2.0
++											* mode_lib->vba.WritebackVRatio[k]
++											> mode_lib->vba.WritebackChromaVTaps[k]
++									|| (mode_lib->vba.WritebackChromaHTaps[k] > 2.0
++										&& ((mode_lib->vba.WritebackChromaHTaps[k] % 2) == 1))))) {
++				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
++			}
++			if (mode_lib->vba.WritebackVRatio[k] < 1.0) {
++				mode_lib->vba.WritebackLumaVExtra =
++						dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0);
++			} else {
++				mode_lib->vba.WritebackLumaVExtra = -1;
++			}
++			if ((mode_lib->vba.WritebackPixelFormat[k] == dm_444_32
++					&& mode_lib->vba.WritebackLumaVTaps[k]
++							> (mode_lib->vba.WritebackLineBufferLumaBufferSize
++									+ mode_lib->vba.WritebackLineBufferChromaBufferSize)
++									/ 3.0
++									/ mode_lib->vba.WritebackDestinationWidth[k]
++									- mode_lib->vba.WritebackLumaVExtra)
++					|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
++							&& mode_lib->vba.WritebackLumaVTaps[k]
++									> mode_lib->vba.WritebackLineBufferLumaBufferSize
++											* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
++											- mode_lib->vba.WritebackLumaVExtra)
++					|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
++							&& mode_lib->vba.WritebackLumaVTaps[k]
++									> mode_lib->vba.WritebackLineBufferLumaBufferSize
++											* 8.0 / 10.0
++											/ mode_lib->vba.WritebackDestinationWidth[k]
++											- mode_lib->vba.WritebackLumaVExtra)) {
++				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
++			}
++			if (2.0 * mode_lib->vba.WritebackVRatio[k] < 1) {
++				mode_lib->vba.WritebackChromaVExtra = 0.0;
++			} else {
++				mode_lib->vba.WritebackChromaVExtra = -1;
++			}
++			if ((mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
++					&& mode_lib->vba.WritebackChromaVTaps[k]
++							> mode_lib->vba.WritebackLineBufferChromaBufferSize
++									* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
++									- mode_lib->vba.WritebackChromaVExtra)
++					|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
++							&& mode_lib->vba.WritebackChromaVTaps[k]
++									> mode_lib->vba.WritebackLineBufferChromaBufferSize
++											* 8.0 / 10.0
++											/ mode_lib->vba.WritebackDestinationWidth[k]
++											- mode_lib->vba.WritebackChromaVExtra)) {
++				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
++			}
++		}
++	}
++	/*Maximum DISPCLK/DPPCLK Support check*/
++
++	mode_lib->vba.WritebackRequiredDISPCLK = 0.0;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.WritebackEnable[k] == true) {
++			mode_lib->vba.WritebackRequiredDISPCLK =
++					dml_max(
++							mode_lib->vba.WritebackRequiredDISPCLK,
++							CalculateWriteBackDISPCLK(
++									mode_lib->vba.WritebackPixelFormat[k],
++									mode_lib->vba.PixelClock[k],
++									mode_lib->vba.WritebackHRatio[k],
++									mode_lib->vba.WritebackVRatio[k],
++									mode_lib->vba.WritebackLumaHTaps[k],
++									mode_lib->vba.WritebackLumaVTaps[k],
++									mode_lib->vba.WritebackChromaHTaps[k],
++									mode_lib->vba.WritebackChromaVTaps[k],
++									mode_lib->vba.WritebackDestinationWidth[k],
++									mode_lib->vba.HTotal[k],
++									mode_lib->vba.WritebackChromaLineBufferWidth));
++		}
++	}
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.HRatio[k] > 1.0) {
++			locals->PSCL_FACTOR[k] = dml_min(
++					mode_lib->vba.MaxDCHUBToPSCLThroughput,
++					mode_lib->vba.MaxPSCLToLBThroughput
++							* mode_lib->vba.HRatio[k]
++							/ dml_ceil(
++									mode_lib->vba.htaps[k]
++											/ 6.0,
++									1.0));
++		} else {
++			locals->PSCL_FACTOR[k] = dml_min(
++					mode_lib->vba.MaxDCHUBToPSCLThroughput,
++					mode_lib->vba.MaxPSCLToLBThroughput);
++		}
++		if (locals->BytePerPixelInDETC[k] == 0.0) {
++			locals->PSCL_FACTOR_CHROMA[k] = 0.0;
++			locals->MinDPPCLKUsingSingleDPP[k] =
++					mode_lib->vba.PixelClock[k]
++							* dml_max3(
++									mode_lib->vba.vtaps[k] / 6.0
++											* dml_min(
++													1.0,
++													mode_lib->vba.HRatio[k]),
++									mode_lib->vba.HRatio[k]
++											* mode_lib->vba.VRatio[k]
++											/ locals->PSCL_FACTOR[k],
++									1.0);
++			if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0)
++					&& locals->MinDPPCLKUsingSingleDPP[k]
++							< 2.0 * mode_lib->vba.PixelClock[k]) {
++				locals->MinDPPCLKUsingSingleDPP[k] = 2.0
++						* mode_lib->vba.PixelClock[k];
++			}
++		} else {
++			if (mode_lib->vba.HRatio[k] / 2.0 > 1.0) {
++				locals->PSCL_FACTOR_CHROMA[k] =
++						dml_min(
++								mode_lib->vba.MaxDCHUBToPSCLThroughput,
++								mode_lib->vba.MaxPSCLToLBThroughput
++										* mode_lib->vba.HRatio[k]
++										/ 2.0
++										/ dml_ceil(
++												mode_lib->vba.HTAPsChroma[k]
++														/ 6.0,
++												1.0));
++			} else {
++				locals->PSCL_FACTOR_CHROMA[k] = dml_min(
++						mode_lib->vba.MaxDCHUBToPSCLThroughput,
++						mode_lib->vba.MaxPSCLToLBThroughput);
++			}
++			locals->MinDPPCLKUsingSingleDPP[k] =
++					mode_lib->vba.PixelClock[k]
++							* dml_max5(
++									mode_lib->vba.vtaps[k] / 6.0
++											* dml_min(
++													1.0,
++													mode_lib->vba.HRatio[k]),
++									mode_lib->vba.HRatio[k]
++											* mode_lib->vba.VRatio[k]
++											/ locals->PSCL_FACTOR[k],
++									mode_lib->vba.VTAPsChroma[k]
++											/ 6.0
++											* dml_min(
++													1.0,
++													mode_lib->vba.HRatio[k]
++															/ 2.0),
++									mode_lib->vba.HRatio[k]
++											* mode_lib->vba.VRatio[k]
++											/ 4.0
++											/ locals->PSCL_FACTOR_CHROMA[k],
++									1.0);
++			if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0
++					|| mode_lib->vba.HTAPsChroma[k] > 6.0
++					|| mode_lib->vba.VTAPsChroma[k] > 6.0)
++					&& locals->MinDPPCLKUsingSingleDPP[k]
++							< 2.0 * mode_lib->vba.PixelClock[k]) {
++				locals->MinDPPCLKUsingSingleDPP[k] = 2.0
++						* mode_lib->vba.PixelClock[k];
++			}
++		}
++	}
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		Calculate256BBlockSizes(
++				mode_lib->vba.SourcePixelFormat[k],
++				mode_lib->vba.SurfaceTiling[k],
++				dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
++				dml_ceil(locals->BytePerPixelInDETC[k], 2.0),
++				&locals->Read256BlockHeightY[k],
++				&locals->Read256BlockHeightC[k],
++				&locals->Read256BlockWidthY[k],
++				&locals->Read256BlockWidthC[k]);
++		if (mode_lib->vba.SourceScan[k] == dm_horz) {
++			locals->MaxSwathHeightY[k] = locals->Read256BlockHeightY[k];
++			locals->MaxSwathHeightC[k] = locals->Read256BlockHeightC[k];
++		} else {
++			locals->MaxSwathHeightY[k] = locals->Read256BlockWidthY[k];
++			locals->MaxSwathHeightC[k] = locals->Read256BlockWidthC[k];
++		}
++		if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_8)) {
++			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
++					|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
++							&& (mode_lib->vba.SurfaceTiling[k]
++									== dm_sw_4kb_s
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_4kb_s_x
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_64kb_s
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_64kb_s_t
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_64kb_s_x
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_var_s
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_var_s_x)
++							&& mode_lib->vba.SourceScan[k] == dm_horz)) {
++				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
++			} else {
++				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
++						/ 2.0;
++			}
++			locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
++		} else {
++			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
++				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
++				locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
++			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
++					&& mode_lib->vba.SourceScan[k] == dm_horz) {
++				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
++						/ 2.0;
++				locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
++			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
++					&& mode_lib->vba.SourceScan[k] == dm_horz) {
++				locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]
++						/ 2.0;
++				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
++			} else {
++				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
++				locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
++			}
++		}
++		if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
++			mode_lib->vba.MaximumSwathWidthSupport = 8192.0;
++		} else {
++			mode_lib->vba.MaximumSwathWidthSupport = 5120.0;
++		}
++		mode_lib->vba.MaximumSwathWidthInDETBuffer =
++				dml_min(
++						mode_lib->vba.MaximumSwathWidthSupport,
++						mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0
++								/ (locals->BytePerPixelInDETY[k]
++										* locals->MinSwathHeightY[k]
++										+ locals->BytePerPixelInDETC[k]
++												/ 2.0
++												* locals->MinSwathHeightC[k]));
++		if (locals->BytePerPixelInDETC[k] == 0.0) {
++			mode_lib->vba.MaximumSwathWidthInLineBuffer =
++					mode_lib->vba.LineBufferSize
++							* dml_max(mode_lib->vba.HRatio[k], 1.0)
++							/ mode_lib->vba.LBBitPerPixel[k]
++							/ (mode_lib->vba.vtaps[k]
++									+ dml_max(
++											dml_ceil(
++													mode_lib->vba.VRatio[k],
++													1.0)
++													- 2,
++											0.0));
++		} else {
++			mode_lib->vba.MaximumSwathWidthInLineBuffer =
++					dml_min(
++							mode_lib->vba.LineBufferSize
++									* dml_max(
++											mode_lib->vba.HRatio[k],
++											1.0)
++									/ mode_lib->vba.LBBitPerPixel[k]
++									/ (mode_lib->vba.vtaps[k]
++											+ dml_max(
++													dml_ceil(
++															mode_lib->vba.VRatio[k],
++															1.0)
++															- 2,
++													0.0)),
++							2.0 * mode_lib->vba.LineBufferSize
++									* dml_max(
++											mode_lib->vba.HRatio[k]
++													/ 2.0,
++											1.0)
++									/ mode_lib->vba.LBBitPerPixel[k]
++									/ (mode_lib->vba.VTAPsChroma[k]
++											+ dml_max(
++													dml_ceil(
++															mode_lib->vba.VRatio[k]
++																	/ 2.0,
++															1.0)
++															- 2,
++													0.0)));
++		}
++		locals->MaximumSwathWidth[k] = dml_min(
++				mode_lib->vba.MaximumSwathWidthInDETBuffer,
++				mode_lib->vba.MaximumSwathWidthInLineBuffer);
++	}
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		for (j = 0; j < 2; j++) {
++			mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(
++				mode_lib->vba.MaxDispclk[i],
++				mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
++			mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(
++				mode_lib->vba.MaxDppclk[i],
++				mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
++			locals->RequiredDISPCLK[i][j] = 0.0;
++			locals->DISPCLK_DPPCLK_Support[i][j] = true;
++			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++				mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine =
++						mode_lib->vba.PixelClock[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
++								* (1.0 + mode_lib->vba.DISPCLKRampingMargin / 100.0);
++				if (mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine >= mode_lib->vba.MaxDispclk[i]
++						&& i == mode_lib->vba.soc.num_states)
++					mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine = mode_lib->vba.PixelClock[k]
++							* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
++
++				mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
++					* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * (1 + mode_lib->vba.DISPCLKRampingMargin / 100.0);
++				if (mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine >= mode_lib->vba.MaxDispclk[i]
++						&& i == mode_lib->vba.soc.num_states)
++					mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
++							* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
++				if (mode_lib->vba.ODMCapability == false || mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine <= mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
++					locals->ODMCombineEnablePerState[i][k] = false;
++					mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
++				} else {
++					locals->ODMCombineEnablePerState[i][k] = true;
++					mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
++				}
++				if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
++						&& locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]
++						&& locals->ODMCombineEnablePerState[i][k] == false) {
++					locals->NoOfDPP[i][j][k] = 1;
++					locals->RequiredDPPCLK[i][j][k] =
++						locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
++				} else {
++					locals->NoOfDPP[i][j][k] = 2;
++					locals->RequiredDPPCLK[i][j][k] =
++						locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
++				}
++				locals->RequiredDISPCLK[i][j] = dml_max(
++						locals->RequiredDISPCLK[i][j],
++						mode_lib->vba.PlaneRequiredDISPCLK);
++				if ((locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
++						> mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity)
++						|| (mode_lib->vba.PlaneRequiredDISPCLK > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity)) {
++					locals->DISPCLK_DPPCLK_Support[i][j] = false;
++				}
++			}
++			locals->TotalNumberOfActiveDPP[i][j] = 0.0;
++			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
++				locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
++			if (j == 1) {
++				while (locals->TotalNumberOfActiveDPP[i][j] < mode_lib->vba.MaxNumDPP
++						&& locals->TotalNumberOfActiveDPP[i][j] < 2 * mode_lib->vba.NumberOfActivePlanes) {
++					double BWOfNonSplitPlaneOfMaximumBandwidth;
++					unsigned int NumberOfNonSplitPlaneOfMaximumBandwidth;
++
++					BWOfNonSplitPlaneOfMaximumBandwidth = 0;
++					NumberOfNonSplitPlaneOfMaximumBandwidth = 0;
++					for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++						if (locals->ReadBandwidth[k] > BWOfNonSplitPlaneOfMaximumBandwidth && locals->NoOfDPP[i][j][k] == 1) {
++							BWOfNonSplitPlaneOfMaximumBandwidth = locals->ReadBandwidth[k];
++							NumberOfNonSplitPlaneOfMaximumBandwidth = k;
++						}
++					}
++					locals->NoOfDPP[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = 2;
++					locals->RequiredDPPCLK[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] =
++						locals->MinDPPCLKUsingSingleDPP[NumberOfNonSplitPlaneOfMaximumBandwidth]
++							* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100) / 2;
++					locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + 1;
++				}
++			}
++			if (locals->TotalNumberOfActiveDPP[i][j] > mode_lib->vba.MaxNumDPP) {
++				locals->RequiredDISPCLK[i][j] = 0.0;
++				locals->DISPCLK_DPPCLK_Support[i][j] = true;
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					locals->ODMCombineEnablePerState[i][k] = false;
++					if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
++						locals->NoOfDPP[i][j][k] = 1;
++						locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
++							* (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
++					} else {
++						locals->NoOfDPP[i][j][k] = 2;
++						locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
++										* (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
++					}
++					if (i != mode_lib->vba.soc.num_states) {
++						mode_lib->vba.PlaneRequiredDISPCLK =
++								mode_lib->vba.PixelClock[k]
++										* (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
++										* (1.0 + mode_lib->vba.DISPCLKRampingMargin / 100.0);
++					} else {
++						mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PixelClock[k]
++							* (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
++					}
++					locals->RequiredDISPCLK[i][j] = dml_max(
++							locals->RequiredDISPCLK[i][j],
++							mode_lib->vba.PlaneRequiredDISPCLK);
++					if (locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
++							> mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
++							|| mode_lib->vba.PlaneRequiredDISPCLK > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity)
++						locals->DISPCLK_DPPCLK_Support[i][j] = false;
++				}
++				locals->TotalNumberOfActiveDPP[i][j] = 0.0;
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
++					locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
++			}
++			locals->RequiredDISPCLK[i][j] = dml_max(
++					locals->RequiredDISPCLK[i][j],
++					mode_lib->vba.WritebackRequiredDISPCLK);
++			if (mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity
++					< mode_lib->vba.WritebackRequiredDISPCLK) {
++				locals->DISPCLK_DPPCLK_Support[i][j] = false;
++			}
++		}
++	}
++	/*Viewport Size Check*/
++
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		locals->ViewportSizeSupport[i] = true;
++		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++			if (locals->ODMCombineEnablePerState[i][k] == true) {
++				if (dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]))
++						> locals->MaximumSwathWidth[k]) {
++					locals->ViewportSizeSupport[i] = false;
++				}
++			} else {
++				if (locals->SwathWidthYSingleDPP[k] / 2.0 > locals->MaximumSwathWidth[k]) {
++					locals->ViewportSizeSupport[i] = false;
++				}
++			}
++		}
++	}
++	/*Total Available Pipes Support Check*/
++
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		for (j = 0; j < 2; j++) {
++			if (locals->TotalNumberOfActiveDPP[i][j] <= mode_lib->vba.MaxNumDPP)
++				locals->TotalAvailablePipesSupport[i][j] = true;
++			else
++				locals->TotalAvailablePipesSupport[i][j] = false;
++		}
++	}
++	/*Total Available OTG Support Check*/
++
++	mode_lib->vba.TotalNumberOfActiveOTG = 0.0;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.BlendingAndTiming[k] == k) {
++			mode_lib->vba.TotalNumberOfActiveOTG = mode_lib->vba.TotalNumberOfActiveOTG
++					+ 1.0;
++		}
++	}
++	if (mode_lib->vba.TotalNumberOfActiveOTG <= mode_lib->vba.MaxNumOTG) {
++		mode_lib->vba.NumberOfOTGSupport = true;
++	} else {
++		mode_lib->vba.NumberOfOTGSupport = false;
++	}
++	/*Display IO and DSC Support Check*/
++
++	mode_lib->vba.NonsupportedDSCInputBPC = false;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0
++				|| mode_lib->vba.DSCInputBitPerComponent[k] == 10.0
++				|| mode_lib->vba.DSCInputBitPerComponent[k] == 8.0)) {
++			mode_lib->vba.NonsupportedDSCInputBPC = true;
++		}
++	}
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++			locals->RequiresDSC[i][k] = 0;
++			locals->RequiresFEC[i][k] = 0;
++			if (mode_lib->vba.BlendingAndTiming[k] == k) {
++				if (mode_lib->vba.Output[k] == dm_hdmi) {
++					locals->RequiresDSC[i][k] = 0;
++					locals->RequiresFEC[i][k] = 0;
++					locals->OutputBppPerState[i][k] = TruncToValidBPP(
++							dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24,
++							false,
++							mode_lib->vba.Output[k],
++							mode_lib->vba.OutputFormat[k],
++							mode_lib->vba.DSCInputBitPerComponent[k]);
++				} else if (mode_lib->vba.Output[k] == dm_dp
++						|| mode_lib->vba.Output[k] == dm_edp) {
++					if (mode_lib->vba.Output[k] == dm_edp) {
++						mode_lib->vba.EffectiveFECOverhead = 0.0;
++					} else {
++						mode_lib->vba.EffectiveFECOverhead =
++								mode_lib->vba.FECOverhead;
++					}
++					if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) {
++						mode_lib->vba.Outbpp = TruncToValidBPP(
++								(1.0 - mode_lib->vba.Downspreading / 100.0) * 270.0
++								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
++								false,
++								mode_lib->vba.Output[k],
++								mode_lib->vba.OutputFormat[k],
++								mode_lib->vba.DSCInputBitPerComponent[k]);
++						mode_lib->vba.OutbppDSC = TruncToValidBPP(
++								(1.0 - mode_lib->vba.Downspreading / 100.0) * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 270.0
++								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
++								true,
++								mode_lib->vba.Output[k],
++								mode_lib->vba.OutputFormat[k],
++								mode_lib->vba.DSCInputBitPerComponent[k]);
++						if (mode_lib->vba.DSCEnabled[k] == true) {
++							locals->RequiresDSC[i][k] = true;
++							if (mode_lib->vba.Output[k] == dm_dp) {
++								locals->RequiresFEC[i][k] = true;
++							} else {
++								locals->RequiresFEC[i][k] = false;
++							}
++							mode_lib->vba.Outbpp = mode_lib->vba.OutbppDSC;
++						} else {
++							locals->RequiresDSC[i][k] = false;
++							locals->RequiresFEC[i][k] = false;
++						}
++						locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
++					}
++					if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) {
++						mode_lib->vba.Outbpp = TruncToValidBPP(
++								(1.0 - mode_lib->vba.Downspreading / 100.0) * 540.0
++								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
++									false,
++									mode_lib->vba.Output[k],
++									mode_lib->vba.OutputFormat[k],
++									mode_lib->vba.DSCInputBitPerComponent[k]);
++						mode_lib->vba.OutbppDSC = TruncToValidBPP(
++								(1.0 - mode_lib->vba.Downspreading / 100.0) * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 540.0
++								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
++								true,
++								mode_lib->vba.Output[k],
++								mode_lib->vba.OutputFormat[k],
++								mode_lib->vba.DSCInputBitPerComponent[k]);
++						if (mode_lib->vba.DSCEnabled[k] == true) {
++							locals->RequiresDSC[i][k] = true;
++							if (mode_lib->vba.Output[k] == dm_dp) {
++								locals->RequiresFEC[i][k] = true;
++							} else {
++								locals->RequiresFEC[i][k] = false;
++							}
++							mode_lib->vba.Outbpp = mode_lib->vba.OutbppDSC;
++						} else {
++							locals->RequiresDSC[i][k] = false;
++							locals->RequiresFEC[i][k] = false;
++						}
++						locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
++					}
++					if (mode_lib->vba.Outbpp == BPP_INVALID
++							&& mode_lib->vba.PHYCLKPerState[i]
++									>= 810.0) {
++						mode_lib->vba.Outbpp = TruncToValidBPP(
++								(1.0 - mode_lib->vba.Downspreading / 100.0) * 810.0
++								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
++								false,
++								mode_lib->vba.Output[k],
++								mode_lib->vba.OutputFormat[k],
++								mode_lib->vba.DSCInputBitPerComponent[k]);
++						mode_lib->vba.OutbppDSC = TruncToValidBPP(
++								(1.0 - mode_lib->vba.Downspreading / 100.0) * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 810.0
++								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
++								true,
++								mode_lib->vba.Output[k],
++								mode_lib->vba.OutputFormat[k],
++								mode_lib->vba.DSCInputBitPerComponent[k]);
++						if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) {
++							locals->RequiresDSC[i][k] = true;
++							if (mode_lib->vba.Output[k] == dm_dp) {
++								locals->RequiresFEC[i][k] = true;
++							} else {
++								locals->RequiresFEC[i][k] = false;
++							}
++							mode_lib->vba.Outbpp = mode_lib->vba.OutbppDSC;
++						} else {
++							locals->RequiresDSC[i][k] = false;
++							locals->RequiresFEC[i][k] = false;
++						}
++						locals->OutputBppPerState[i][k] =
++								mode_lib->vba.Outbpp;
++					}
++				}
++			} else {
++				locals->OutputBppPerState[i][k] = BPP_BLENDED_PIPE;
++			}
++		}
++	}
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		locals->DIOSupport[i] = true;
++		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++			if (locals->OutputBppPerState[i][k] == BPP_INVALID
++					|| (mode_lib->vba.OutputFormat[k] == dm_420
++							&& mode_lib->vba.Interlace[k] == true
++							&& mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true)) {
++				locals->DIOSupport[i] = false;
++			}
++		}
++	}
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++			locals->DSCCLKRequiredMoreThanSupported[i] = false;
++			if (mode_lib->vba.BlendingAndTiming[k] == k) {
++				if ((mode_lib->vba.Output[k] == dm_dp
++						|| mode_lib->vba.Output[k] == dm_edp)) {
++					if (mode_lib->vba.OutputFormat[k] == dm_420
++							|| mode_lib->vba.OutputFormat[k]
++									== dm_n422) {
++						mode_lib->vba.DSCFormatFactor = 2;
++					} else {
++						mode_lib->vba.DSCFormatFactor = 1;
++					}
++					if (locals->RequiresDSC[i][k] == true) {
++						if (locals->ODMCombineEnablePerState[i][k]
++								== true) {
++							if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor
++									> (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i]) {
++								locals->DSCCLKRequiredMoreThanSupported[i] =
++										true;
++							}
++						} else {
++							if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor
++									> (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i]) {
++								locals->DSCCLKRequiredMoreThanSupported[i] =
++										true;
++							}
++						}
++					}
++				}
++			}
++		}
++	}
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		locals->NotEnoughDSCUnits[i] = false;
++		mode_lib->vba.TotalDSCUnitsRequired = 0.0;
++		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++			if (locals->RequiresDSC[i][k] == true) {
++				if (locals->ODMCombineEnablePerState[i][k] == true) {
++					mode_lib->vba.TotalDSCUnitsRequired =
++							mode_lib->vba.TotalDSCUnitsRequired + 2.0;
++				} else {
++					mode_lib->vba.TotalDSCUnitsRequired =
++							mode_lib->vba.TotalDSCUnitsRequired + 1.0;
++				}
++			}
++		}
++		if (mode_lib->vba.TotalDSCUnitsRequired > mode_lib->vba.NumberOfDSC) {
++			locals->NotEnoughDSCUnits[i] = true;
++		}
++	}
++	/*DSC Delay per state*/
++
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++			if (mode_lib->vba.BlendingAndTiming[k] != k) {
++				mode_lib->vba.slices = 0;
++			} else if (locals->RequiresDSC[i][k] == 0
++					|| locals->RequiresDSC[i][k] == false) {
++				mode_lib->vba.slices = 0;
++			} else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) {
++				mode_lib->vba.slices = dml_ceil(
++						mode_lib->vba.PixelClockBackEnd[k] / 400.0,
++						4.0);
++			} else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) {
++				mode_lib->vba.slices = 8.0;
++			} else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) {
++				mode_lib->vba.slices = 4.0;
++			} else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) {
++				mode_lib->vba.slices = 2.0;
++			} else {
++				mode_lib->vba.slices = 1.0;
++			}
++			if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE
++					|| locals->OutputBppPerState[i][k] == BPP_INVALID) {
++				mode_lib->vba.bpp = 0.0;
++			} else {
++				mode_lib->vba.bpp = locals->OutputBppPerState[i][k];
++			}
++			if (locals->RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) {
++				if (locals->ODMCombineEnablePerState[i][k] == false) {
++					locals->DSCDelayPerState[i][k] =
++							dscceComputeDelay(
++									mode_lib->vba.DSCInputBitPerComponent[k],
++									mode_lib->vba.bpp,
++									dml_ceil(
++											mode_lib->vba.HActive[k]
++													/ mode_lib->vba.slices,
++											1.0),
++									mode_lib->vba.slices,
++									mode_lib->vba.OutputFormat[k])
++									+ dscComputeDelay(
++											mode_lib->vba.OutputFormat[k]);
++				} else {
++					locals->DSCDelayPerState[i][k] =
++							2.0 * (dscceComputeDelay(
++											mode_lib->vba.DSCInputBitPerComponent[k],
++											mode_lib->vba.bpp,
++											dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0),
++											mode_lib->vba.slices / 2,
++											mode_lib->vba.OutputFormat[k])
++									+ dscComputeDelay(mode_lib->vba.OutputFormat[k]));
++				}
++				locals->DSCDelayPerState[i][k] =
++						locals->DSCDelayPerState[i][k] * mode_lib->vba.PixelClock[k] / mode_lib->vba.PixelClockBackEnd[k];
++			} else {
++				locals->DSCDelayPerState[i][k] = 0.0;
++			}
++		}
++		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++			for (m = 0; m <= mode_lib->vba.NumberOfActivePlanes - 1; m++) {
++				for (j = 0; j <= mode_lib->vba.NumberOfActivePlanes - 1; j++) {
++					if (mode_lib->vba.BlendingAndTiming[k] == m && locals->RequiresDSC[i][m] == true)
++						locals->DSCDelayPerState[i][k] = locals->DSCDelayPerState[i][m];
++				}
++			}
++		}
++	}
++
++	//Prefetch Check
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		for (j = 0; j < 2; j++) {
++			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++				if (locals->ODMCombineEnablePerState[i][k] == true)
++					locals->SwathWidthYPerState[i][j][k] = dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k]));
++				else
++					locals->SwathWidthYPerState[i][j][k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k];
++				locals->SwathWidthGranularityY = 256  / dml_ceil(locals->BytePerPixelInDETY[k], 1) / locals->MaxSwathHeightY[k];
++				locals->RoundedUpMaxSwathSizeBytesY = (dml_ceil(locals->SwathWidthYPerState[i][j][k] - 1, locals->SwathWidthGranularityY)
++						+ locals->SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k];
++				if (locals->SourcePixelFormat[k] == dm_420_10) {
++					locals->RoundedUpMaxSwathSizeBytesY = dml_ceil(locals->RoundedUpMaxSwathSizeBytesY, 256) + 256;
++				}
++				if (locals->MaxSwathHeightC[k] > 0) {
++					locals->SwathWidthGranularityC = 256 / dml_ceil(locals->BytePerPixelInDETC[k], 2) / locals->MaxSwathHeightC[k];
++
++					locals->RoundedUpMaxSwathSizeBytesC = (dml_ceil(locals->SwathWidthYPerState[i][j][k] / 2 - 1, locals->SwathWidthGranularityC)
++					+ locals->SwathWidthGranularityC) * locals->BytePerPixelInDETC[k] * locals->MaxSwathHeightC[k];
++				}
++				if (locals->SourcePixelFormat[k] == dm_420_10) {
++					locals->RoundedUpMaxSwathSizeBytesC = dml_ceil(locals->RoundedUpMaxSwathSizeBytesC, 256)  + 256;
++				} else {
++					locals->RoundedUpMaxSwathSizeBytesC = 0;
++				}
++
++				if (locals->RoundedUpMaxSwathSizeBytesY + locals->RoundedUpMaxSwathSizeBytesC <= locals->DETBufferSizeInKByte * 1024 / 2) {
++					locals->SwathHeightYPerState[i][j][k] = locals->MaxSwathHeightY[k];
++					locals->SwathHeightCPerState[i][j][k] = locals->MaxSwathHeightC[k];
++				} else {
++					locals->SwathHeightYPerState[i][j][k] = locals->MinSwathHeightY[k];
++					locals->SwathHeightCPerState[i][j][k] = locals->MinSwathHeightC[k];
++				}
++
++				if (locals->BytePerPixelInDETC[k] == 0) {
++					locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
++					locals->LinesInDETChroma = 0;
++				} else if (locals->SwathHeightYPerState[i][j][k] <= locals->SwathHeightCPerState[i][j][k]) {
++					locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 / 2 / locals->BytePerPixelInDETY[k] /
++							locals->SwathWidthYPerState[i][j][k];
++					locals->LinesInDETChroma = locals->DETBufferSizeInKByte * 1024 / 2 / locals->BytePerPixelInDETC[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
++				} else {
++					locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 * 2 / 3 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
++					locals->LinesInDETChroma = locals->DETBufferSizeInKByte * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
++				}
++
++				locals->EffectiveLBLatencyHidingSourceLinesLuma = dml_min(locals->MaxLineBufferLines,
++					dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] / (locals->SwathWidthYPerState[i][j][k]
++					/ dml_max(locals->HRatio[k], 1)), 1)) - (locals->vtaps[k] - 1);
++
++				locals->EffectiveLBLatencyHidingSourceLinesChroma =  dml_min(locals->MaxLineBufferLines,
++						dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k]
++						/ (locals->SwathWidthYPerState[i][j][k] / 2
++						/ dml_max(locals->HRatio[k] / 2, 1)), 1)) - (locals->VTAPsChroma[k] - 1);
++
++				locals->EffectiveDETLBLinesLuma = dml_floor(locals->LinesInDETLuma +  dml_min(
++						locals->LinesInDETLuma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETY[k] *
++						locals->PSCL_FACTOR[k] / locals->ReturnBWPerState[i],
++						locals->EffectiveLBLatencyHidingSourceLinesLuma),
++						locals->SwathHeightYPerState[i][j][k]);
++
++				locals->EffectiveDETLBLinesChroma = dml_floor(locals->LinesInDETChroma + dml_min(
++						locals->LinesInDETChroma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETC[k] *
++						locals->PSCL_FACTOR_CHROMA[k] / locals->ReturnBWPerState[i],
++						locals->EffectiveLBLatencyHidingSourceLinesChroma),
++						locals->SwathHeightCPerState[i][j][k]);
++
++				if (locals->BytePerPixelInDETC[k] == 0) {
++					locals->UrgentLatencySupportUsPerState[i][j][k] = locals->EffectiveDETLBLinesLuma * (locals->HTotal[k] / locals->PixelClock[k])
++							/ locals->VRatio[k] - locals->EffectiveDETLBLinesLuma * locals->SwathWidthYPerState[i][j][k] *
++								dml_ceil(locals->BytePerPixelInDETY[k], 1) / (locals->ReturnBWPerState[i] / locals->NoOfDPP[i][j][k]);
++				} else {
++					locals->UrgentLatencySupportUsPerState[i][j][k] = dml_min(
++						locals->EffectiveDETLBLinesLuma * (locals->HTotal[k] / locals->PixelClock[k])
++						/ locals->VRatio[k] - locals->EffectiveDETLBLinesLuma * locals->SwathWidthYPerState[i][j][k] *
++						dml_ceil(locals->BytePerPixelInDETY[k], 1) / (locals->ReturnBWPerState[i] / locals->NoOfDPP[i][j][k]),
++							locals->EffectiveDETLBLinesChroma * (locals->HTotal[k] / locals->PixelClock[k]) / (locals->VRatio[k] / 2) -
++							locals->EffectiveDETLBLinesChroma * locals->SwathWidthYPerState[i][j][k] / 2 *
++							dml_ceil(locals->BytePerPixelInDETC[k], 2) / (locals->ReturnBWPerState[i] / locals->NoOfDPP[i][j][k]));
++				}
++			}
++		}
++	}
++
++	for (i = 0; i <= locals->soc.num_states; i++) {
++		for (j = 0; j < 2; j++) {
++			locals->UrgentLatencySupport[i][j] = true;
++			for (k = 0; k < locals->NumberOfActivePlanes; k++) {
++				if (locals->UrgentLatencySupportUsPerState[i][j][k] < locals->UrgentLatency)
++					locals->UrgentLatencySupport[i][j] = false;
++			}
++		}
++	}
++
++
++	/*Prefetch Check*/
++	for (i = 0; i <= locals->soc.num_states; i++) {
++		for (j = 0; j < 2; j++) {
++			locals->TotalNumberOfDCCActiveDPP[i][j] = 0;
++			for (k = 0; k < locals->NumberOfActivePlanes; k++) {
++				if (locals->DCCEnable[k] == true) {
++					locals->TotalNumberOfDCCActiveDPP[i][j] =
++						locals->TotalNumberOfDCCActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
++				}
++			}
++		}
++	}
++
++	CalculateMinAndMaxPrefetchMode(locals->AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, &locals->MinPrefetchMode, &locals->MaxPrefetchMode);
++
++	locals->MaxTotalVActiveRDBandwidth = 0;
++	for (k = 0; k < locals->NumberOfActivePlanes; k++) {
++		locals->MaxTotalVActiveRDBandwidth = locals->MaxTotalVActiveRDBandwidth + locals->ReadBandwidth[k];
++	}
++
++	for (i = 0; i <= locals->soc.num_states; i++) {
++		for (j = 0; j < 2; j++) {
++			for (k = 0; k < locals->NumberOfActivePlanes; k++) {
++				locals->NoOfDPPThisState[k] = locals->NoOfDPP[i][j][k];
++				locals->RequiredDPPCLKThisState[k] = locals->RequiredDPPCLK[i][j][k];
++				locals->SwathHeightYThisState[k] = locals->SwathHeightYPerState[i][j][k];
++				locals->SwathHeightCThisState[k] = locals->SwathHeightCPerState[i][j][k];
++				locals->SwathWidthYThisState[k] = locals->SwathWidthYPerState[i][j][k];
++				mode_lib->vba.ProjectedDCFCLKDeepSleep = dml_max(
++						mode_lib->vba.ProjectedDCFCLKDeepSleep,
++						mode_lib->vba.PixelClock[k] / 16.0);
++				if (mode_lib->vba.BytePerPixelInDETC[k] == 0.0) {
++					if (mode_lib->vba.VRatio[k] <= 1.0) {
++						mode_lib->vba.ProjectedDCFCLKDeepSleep =
++								dml_max(
++										mode_lib->vba.ProjectedDCFCLKDeepSleep,
++										1.1
++												* dml_ceil(
++														mode_lib->vba.BytePerPixelInDETY[k],
++														1.0)
++												/ 64.0
++												* mode_lib->vba.HRatio[k]
++												* mode_lib->vba.PixelClock[k]
++												/ mode_lib->vba.NoOfDPP[i][j][k]);
++					} else {
++						mode_lib->vba.ProjectedDCFCLKDeepSleep =
++								dml_max(
++										mode_lib->vba.ProjectedDCFCLKDeepSleep,
++										1.1
++												* dml_ceil(
++														mode_lib->vba.BytePerPixelInDETY[k],
++														1.0)
++												/ 64.0
++												* mode_lib->vba.PSCL_FACTOR[k]
++												* mode_lib->vba.RequiredDPPCLK[i][j][k]);
++					}
++				} else {
++					if (mode_lib->vba.VRatio[k] <= 1.0) {
++						mode_lib->vba.ProjectedDCFCLKDeepSleep =
++								dml_max(
++										mode_lib->vba.ProjectedDCFCLKDeepSleep,
++										1.1
++												* dml_ceil(
++														mode_lib->vba.BytePerPixelInDETY[k],
++														1.0)
++												/ 32.0
++												* mode_lib->vba.HRatio[k]
++												* mode_lib->vba.PixelClock[k]
++												/ mode_lib->vba.NoOfDPP[i][j][k]);
++					} else {
++						mode_lib->vba.ProjectedDCFCLKDeepSleep =
++								dml_max(
++										mode_lib->vba.ProjectedDCFCLKDeepSleep,
++										1.1
++												* dml_ceil(
++														mode_lib->vba.BytePerPixelInDETY[k],
++														1.0)
++												/ 32.0
++												* mode_lib->vba.PSCL_FACTOR[k]
++												* mode_lib->vba.RequiredDPPCLK[i][j][k]);
++					}
++					if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0) {
++						mode_lib->vba.ProjectedDCFCLKDeepSleep =
++								dml_max(
++										mode_lib->vba.ProjectedDCFCLKDeepSleep,
++										1.1
++												* dml_ceil(
++														mode_lib->vba.BytePerPixelInDETC[k],
++														2.0)
++												/ 32.0
++												* mode_lib->vba.HRatio[k]
++												/ 2.0
++												* mode_lib->vba.PixelClock[k]
++												/ mode_lib->vba.NoOfDPP[i][j][k]);
++					} else {
++						mode_lib->vba.ProjectedDCFCLKDeepSleep =
++								dml_max(
++										mode_lib->vba.ProjectedDCFCLKDeepSleep,
++										1.1
++												* dml_ceil(
++														mode_lib->vba.BytePerPixelInDETC[k],
++														2.0)
++												/ 32.0
++												* mode_lib->vba.PSCL_FACTOR_CHROMA[k]
++												* mode_lib->vba.RequiredDPPCLK[i][j][k]);
++					}
++				}
++			}
++			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++				mode_lib->vba.PDEAndMetaPTEBytesPerFrameY = CalculateVMAndRowBytes(
++						mode_lib,
++						mode_lib->vba.DCCEnable[k],
++						mode_lib->vba.Read256BlockHeightY[k],
++						mode_lib->vba.Read256BlockWidthY[k],
++						mode_lib->vba.SourcePixelFormat[k],
++						mode_lib->vba.SurfaceTiling[k],
++						dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0),
++						mode_lib->vba.SourceScan[k],
++						mode_lib->vba.ViewportWidth[k],
++						mode_lib->vba.ViewportHeight[k],
++						mode_lib->vba.SwathWidthYPerState[i][j][k],
++						mode_lib->vba.GPUVMEnable,
++						mode_lib->vba.VMMPageSize,
++						mode_lib->vba.PTEBufferSizeInRequestsLuma,
++						mode_lib->vba.PDEProcessingBufIn64KBReqs,
++						mode_lib->vba.PitchY[k],
++						mode_lib->vba.DCCMetaPitchY[k],
++						&mode_lib->vba.MacroTileWidthY[k],
++						&mode_lib->vba.MetaRowBytesY,
++						&mode_lib->vba.DPTEBytesPerRowY,
++						&mode_lib->vba.PTEBufferSizeNotExceededY[i][j][k],
++						&mode_lib->vba.dpte_row_height[k],
++						&mode_lib->vba.meta_row_height[k]);
++				mode_lib->vba.PrefetchLinesY[k] = CalculatePrefetchSourceLines(
++						mode_lib,
++						mode_lib->vba.VRatio[k],
++						mode_lib->vba.vtaps[k],
++						mode_lib->vba.Interlace[k],
++						mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
++						mode_lib->vba.SwathHeightYPerState[i][j][k],
++						mode_lib->vba.ViewportYStartY[k],
++						&mode_lib->vba.PrefillY[k],
++						&mode_lib->vba.MaxNumSwY[k]);
++				if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)) {
++					mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = CalculateVMAndRowBytes(
++							mode_lib,
++							mode_lib->vba.DCCEnable[k],
++							mode_lib->vba.Read256BlockHeightY[k],
++							mode_lib->vba.Read256BlockWidthY[k],
++							mode_lib->vba.SourcePixelFormat[k],
++							mode_lib->vba.SurfaceTiling[k],
++							dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0),
++							mode_lib->vba.SourceScan[k],
++							mode_lib->vba.ViewportWidth[k] / 2.0,
++							mode_lib->vba.ViewportHeight[k] / 2.0,
++							mode_lib->vba.SwathWidthYPerState[i][j][k] / 2.0,
++							mode_lib->vba.GPUVMEnable,
++							mode_lib->vba.VMMPageSize,
++							mode_lib->vba.PTEBufferSizeInRequestsLuma,
++							mode_lib->vba.PDEProcessingBufIn64KBReqs,
++							mode_lib->vba.PitchC[k],
++							0.0,
++							&mode_lib->vba.MacroTileWidthC[k],
++							&mode_lib->vba.MetaRowBytesC,
++							&mode_lib->vba.DPTEBytesPerRowC,
++							&mode_lib->vba.PTEBufferSizeNotExceededC[i][j][k],
++							&mode_lib->vba.dpte_row_height_chroma[k],
++							&mode_lib->vba.meta_row_height_chroma[k]);
++					mode_lib->vba.PrefetchLinesC[k] = CalculatePrefetchSourceLines(
++							mode_lib,
++							mode_lib->vba.VRatio[k] / 2.0,
++							mode_lib->vba.VTAPsChroma[k],
++							mode_lib->vba.Interlace[k],
++							mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
++							mode_lib->vba.SwathHeightCPerState[i][j][k],
++							mode_lib->vba.ViewportYStartC[k],
++							&mode_lib->vba.PrefillC[k],
++							&mode_lib->vba.MaxNumSwC[k]);
++				} else {
++					mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = 0.0;
++					mode_lib->vba.MetaRowBytesC = 0.0;
++					mode_lib->vba.DPTEBytesPerRowC = 0.0;
++					locals->PrefetchLinesC[k] = 0.0;
++					locals->PTEBufferSizeNotExceededC[i][j][k] = true;
++					locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma + mode_lib->vba.PTEBufferSizeInRequestsChroma;
++				}
++				locals->PDEAndMetaPTEBytesPerFrame[k] =
++						mode_lib->vba.PDEAndMetaPTEBytesPerFrameY + mode_lib->vba.PDEAndMetaPTEBytesPerFrameC;
++				locals->MetaRowBytes[k] = mode_lib->vba.MetaRowBytesY + mode_lib->vba.MetaRowBytesC;
++				locals->DPTEBytesPerRow[k] = mode_lib->vba.DPTEBytesPerRowY + mode_lib->vba.DPTEBytesPerRowC;
++
++				CalculateActiveRowBandwidth(
++						mode_lib->vba.GPUVMEnable,
++						mode_lib->vba.SourcePixelFormat[k],
++						mode_lib->vba.VRatio[k],
++						mode_lib->vba.DCCEnable[k],
++						mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
++						mode_lib->vba.MetaRowBytesY,
++						mode_lib->vba.MetaRowBytesC,
++						mode_lib->vba.meta_row_height[k],
++						mode_lib->vba.meta_row_height_chroma[k],
++						mode_lib->vba.DPTEBytesPerRowY,
++						mode_lib->vba.DPTEBytesPerRowC,
++						mode_lib->vba.dpte_row_height[k],
++						mode_lib->vba.dpte_row_height_chroma[k],
++						&mode_lib->vba.meta_row_bw[k],
++						&mode_lib->vba.dpte_row_bw[k],
++						&mode_lib->vba.qual_row_bw[k]);
++			}
++			mode_lib->vba.ExtraLatency =
++					mode_lib->vba.UrgentRoundTripAndOutOfOrderLatencyPerState[i]
++							+ (mode_lib->vba.TotalNumberOfActiveDPP[i][j]
++									* mode_lib->vba.PixelChunkSizeInKByte
++									+ mode_lib->vba.TotalNumberOfDCCActiveDPP[i][j]
++											* mode_lib->vba.MetaChunkSize)
++									* 1024.0
++									/ mode_lib->vba.ReturnBWPerState[i];
++			if (mode_lib->vba.GPUVMEnable == true) {
++				mode_lib->vba.ExtraLatency = mode_lib->vba.ExtraLatency
++						+ mode_lib->vba.TotalNumberOfActiveDPP[i][j]
++								* mode_lib->vba.PTEGroupSize
++								/ mode_lib->vba.ReturnBWPerState[i];
++			}
++			mode_lib->vba.TimeCalc = 24.0 / mode_lib->vba.ProjectedDCFCLKDeepSleep;
++
++			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++				if (mode_lib->vba.BlendingAndTiming[k] == k) {
++					if (mode_lib->vba.WritebackEnable[k] == true) {
++						locals->WritebackDelay[i][k] = mode_lib->vba.WritebackLatency
++								+ CalculateWriteBackDelay(
++										mode_lib->vba.WritebackPixelFormat[k],
++										mode_lib->vba.WritebackHRatio[k],
++										mode_lib->vba.WritebackVRatio[k],
++										mode_lib->vba.WritebackLumaHTaps[k],
++										mode_lib->vba.WritebackLumaVTaps[k],
++										mode_lib->vba.WritebackChromaHTaps[k],
++										mode_lib->vba.WritebackChromaVTaps[k],
++										mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j];
++					} else {
++						locals->WritebackDelay[i][k] = 0.0;
++					}
++					for (m = 0; m <= mode_lib->vba.NumberOfActivePlanes - 1; m++) {
++						if (mode_lib->vba.BlendingAndTiming[m] == k
++								&& mode_lib->vba.WritebackEnable[m]
++										== true) {
++							locals->WritebackDelay[i][k] = dml_max(locals->WritebackDelay[i][k],
++											mode_lib->vba.WritebackLatency + CalculateWriteBackDelay(
++													mode_lib->vba.WritebackPixelFormat[m],
++													mode_lib->vba.WritebackHRatio[m],
++													mode_lib->vba.WritebackVRatio[m],
++													mode_lib->vba.WritebackLumaHTaps[m],
++													mode_lib->vba.WritebackLumaVTaps[m],
++													mode_lib->vba.WritebackChromaHTaps[m],
++													mode_lib->vba.WritebackChromaVTaps[m],
++													mode_lib->vba.WritebackDestinationWidth[m]) / locals->RequiredDISPCLK[i][j]);
++						}
++					}
++				}
++			}
++			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++				for (m = 0; m <= mode_lib->vba.NumberOfActivePlanes - 1; m++) {
++					if (mode_lib->vba.BlendingAndTiming[k] == m) {
++						locals->WritebackDelay[i][k] = locals->WritebackDelay[i][m];
++					}
++				}
++			}
++			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++				for (m = 0; m < locals->NumberOfCursors[k]; m++)
++					locals->cursor_bw[k] = locals->NumberOfCursors[k] * locals->CursorWidth[k][m] * locals->CursorBPP[k][m]
++						/ 8 / (locals->HTotal[k] / locals->PixelClock[k]) * locals->VRatio[k];
++			}
++
++			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++				locals->MaximumVStartup[k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
++					- dml_max(1.0, dml_ceil(locals->WritebackDelay[i][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0));
++			}
++
++			mode_lib->vba.NextPrefetchMode = mode_lib->vba.MinPrefetchMode;
++			do {
++				mode_lib->vba.PrefetchMode[i][j] = mode_lib->vba.NextPrefetchMode;
++				mode_lib->vba.NextPrefetchMode = mode_lib->vba.NextPrefetchMode + 1;
++
++				mode_lib->vba.TWait = CalculateTWait(
++						mode_lib->vba.PrefetchMode[i][j],
++						mode_lib->vba.DRAMClockChangeLatency,
++						mode_lib->vba.UrgentLatency,
++						mode_lib->vba.SREnterPlusExitTime);
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++
++					if (mode_lib->vba.XFCEnabled[k] == true) {
++						mode_lib->vba.XFCRemoteSurfaceFlipDelay =
++								CalculateRemoteSurfaceFlipDelay(
++										mode_lib,
++										mode_lib->vba.VRatio[k],
++										locals->SwathWidthYPerState[i][j][k],
++										dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
++										mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
++										mode_lib->vba.XFCTSlvVupdateOffset,
++										mode_lib->vba.XFCTSlvVupdateWidth,
++										mode_lib->vba.XFCTSlvVreadyOffset,
++										mode_lib->vba.XFCXBUFLatencyTolerance,
++										mode_lib->vba.XFCFillBWOverhead,
++										mode_lib->vba.XFCSlvChunkSize,
++										mode_lib->vba.XFCBusTransportTime,
++										mode_lib->vba.TimeCalc,
++										mode_lib->vba.TWait,
++										&mode_lib->vba.SrcActiveDrainRate,
++										&mode_lib->vba.TInitXFill,
++										&mode_lib->vba.TslvChk);
++					} else {
++						mode_lib->vba.XFCRemoteSurfaceFlipDelay = 0.0;
++					}
++
++					CalculateDelayAfterScaler(mode_lib, mode_lib->vba.ReturnBWPerState[i], mode_lib->vba.ReadBandwidthLuma[k], mode_lib->vba.ReadBandwidthChroma[k], mode_lib->vba.MaxTotalVActiveRDBandwidth,
++						mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k],
++						mode_lib->vba.RequiredDPPCLK[i][j][k], mode_lib->vba.RequiredDISPCLK[i][j], mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDelayPerState[i][k], mode_lib->vba.NoOfDPP[i][j][k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k],
++						mode_lib->vba.DPPCLKDelaySubtotal, mode_lib->vba.DPPCLKDelaySCL, mode_lib->vba.DPPCLKDelaySCLLBOnly, mode_lib->vba.DPPCLKDelayCNVCFormater, mode_lib->vba.DPPCLKDelayCNVCCursor, mode_lib->vba.DISPCLKDelaySubtotal,
++						mode_lib->vba.SwathWidthYPerState[i][j][k] / mode_lib->vba.HRatio[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k],
++						mode_lib->vba.SwathWidthYSingleDPP[k], mode_lib->vba.BytePerPixelInDETY[k], mode_lib->vba.BytePerPixelInDETC[k], mode_lib->vba.SwathHeightYThisState[k], mode_lib->vba.SwathHeightCThisState[k], mode_lib->vba.Interlace[k], mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
++						&mode_lib->vba.DSTXAfterScaler[k], &mode_lib->vba.DSTYAfterScaler[k]);
++
++					mode_lib->vba.IsErrorResult[i][j][k] =
++							CalculatePrefetchSchedule(
++									mode_lib,
++									mode_lib->vba.RequiredDPPCLK[i][j][k],
++									mode_lib->vba.RequiredDISPCLK[i][j],
++									mode_lib->vba.PixelClock[k],
++									mode_lib->vba.ProjectedDCFCLKDeepSleep,
++									mode_lib->vba.NoOfDPP[i][j][k],
++									mode_lib->vba.NumberOfCursors[k],
++									mode_lib->vba.VTotal[k]
++											- mode_lib->vba.VActive[k],
++									mode_lib->vba.HTotal[k],
++									mode_lib->vba.MaxInterDCNTileRepeaters,
++									mode_lib->vba.MaximumVStartup[k],
++									mode_lib->vba.GPUVMMaxPageTableLevels,
++									mode_lib->vba.GPUVMEnable,
++									mode_lib->vba.DynamicMetadataEnable[k],
++									mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
++									mode_lib->vba.DynamicMetadataTransmittedBytes[k],
++									mode_lib->vba.DCCEnable[k],
++									mode_lib->vba.UrgentLatencyPixelDataOnly,
++									mode_lib->vba.ExtraLatency,
++									mode_lib->vba.TimeCalc,
++									mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k],
++									mode_lib->vba.MetaRowBytes[k],
++									mode_lib->vba.DPTEBytesPerRow[k],
++									mode_lib->vba.PrefetchLinesY[k],
++									mode_lib->vba.SwathWidthYPerState[i][j][k],
++									mode_lib->vba.BytePerPixelInDETY[k],
++									mode_lib->vba.PrefillY[k],
++									mode_lib->vba.MaxNumSwY[k],
++									mode_lib->vba.PrefetchLinesC[k],
++									mode_lib->vba.BytePerPixelInDETC[k],
++									mode_lib->vba.PrefillC[k],
++									mode_lib->vba.MaxNumSwC[k],
++									mode_lib->vba.SwathHeightYPerState[i][j][k],
++									mode_lib->vba.SwathHeightCPerState[i][j][k],
++									mode_lib->vba.TWait,
++									mode_lib->vba.XFCEnabled[k],
++									mode_lib->vba.XFCRemoteSurfaceFlipDelay,
++									mode_lib->vba.Interlace[k],
++									mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
++									mode_lib->vba.DSTXAfterScaler[k],
++									mode_lib->vba.DSTYAfterScaler[k],
++									&mode_lib->vba.LineTimesForPrefetch[k],
++									&mode_lib->vba.PrefetchBW[k],
++									&mode_lib->vba.LinesForMetaPTE[k],
++									&mode_lib->vba.LinesForMetaAndDPTERow[k],
++									&mode_lib->vba.VRatioPreY[i][j][k],
++									&mode_lib->vba.VRatioPreC[i][j][k],
++									&mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k],
++									&mode_lib->vba.Tno_bw[k],
++									&mode_lib->vba.VUpdateOffsetPix[k],
++									&mode_lib->vba.VUpdateWidthPix[k],
++									&mode_lib->vba.VReadyOffsetPix[k]);
++				}
++				mode_lib->vba.MaximumReadBandwidthWithoutPrefetch = 0.0;
++				mode_lib->vba.MaximumReadBandwidthWithPrefetch = 0.0;
++				locals->prefetch_vm_bw_valid = true;
++				locals->prefetch_row_bw_valid = true;
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					if (locals->PDEAndMetaPTEBytesPerFrame[k] == 0)
++						locals->prefetch_vm_bw[k] = 0;
++					else if (locals->LinesForMetaPTE[k] > 0)
++						locals->prefetch_vm_bw[k] = locals->PDEAndMetaPTEBytesPerFrame[k]
++							/ (locals->LinesForMetaPTE[k] * locals->HTotal[k] / locals->PixelClock[k]);
++					else {
++						locals->prefetch_vm_bw[k] = 0;
++						locals->prefetch_vm_bw_valid = false;
++					}
++					if (locals->MetaRowBytes[k] + locals->DPTEBytesPerRow[k] == 0)
++						locals->prefetch_row_bw[k] = 0;
++					else if (locals->LinesForMetaAndDPTERow[k] > 0)
++						locals->prefetch_row_bw[k] = (locals->MetaRowBytes[k] + locals->DPTEBytesPerRow[k])
++							/ (locals->LinesForMetaAndDPTERow[k] * locals->HTotal[k] / locals->PixelClock[k]);
++					else {
++						locals->prefetch_row_bw[k] = 0;
++						locals->prefetch_row_bw_valid = false;
++					}
++
++					mode_lib->vba.MaximumReadBandwidthWithoutPrefetch = mode_lib->vba.MaximumReadBandwidthWithPrefetch
++							+ mode_lib->vba.cursor_bw[k] + mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.meta_row_bw[k] + mode_lib->vba.dpte_row_bw[k];
++					mode_lib->vba.MaximumReadBandwidthWithPrefetch =
++							mode_lib->vba.MaximumReadBandwidthWithPrefetch
++									+ mode_lib->vba.cursor_bw[k]
++									+ dml_max3(
++											mode_lib->vba.prefetch_vm_bw[k],
++											mode_lib->vba.prefetch_row_bw[k],
++											dml_max(mode_lib->vba.ReadBandwidth[k],
++											mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k])
++											+ mode_lib->vba.meta_row_bw[k] + mode_lib->vba.dpte_row_bw[k]);
++				}
++				locals->BandwidthWithoutPrefetchSupported[i] = true;
++				if (mode_lib->vba.MaximumReadBandwidthWithoutPrefetch > locals->ReturnBWPerState[i]) {
++					locals->BandwidthWithoutPrefetchSupported[i] = false;
++				}
++
++				locals->PrefetchSupported[i][j] = true;
++				if (mode_lib->vba.MaximumReadBandwidthWithPrefetch > locals->ReturnBWPerState[i]) {
++					locals->PrefetchSupported[i][j] = false;
++				}
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					if (locals->LineTimesForPrefetch[k] < 2.0
++							|| locals->LinesForMetaPTE[k] >= 8.0
++							|| locals->LinesForMetaAndDPTERow[k] >= 16.0
++							|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
++						locals->PrefetchSupported[i][j] = false;
++					}
++				}
++				locals->VRatioInPrefetchSupported[i][j] = true;
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					if (locals->VRatioPreY[i][j][k] > 4.0
++							|| locals->VRatioPreC[i][j][k] > 4.0
++							|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
++						locals->VRatioInPrefetchSupported[i][j] = false;
++					}
++				}
++			} while ((locals->PrefetchSupported[i][j] != true || locals->VRatioInPrefetchSupported[i][j] != true)
++					&& mode_lib->vba.NextPrefetchMode < mode_lib->vba.MaxPrefetchMode);
++
++			if (mode_lib->vba.PrefetchSupported[i][j] == true
++					&& mode_lib->vba.VRatioInPrefetchSupported[i][j] == true) {
++				mode_lib->vba.BandwidthAvailableForImmediateFlip =
++						mode_lib->vba.ReturnBWPerState[i];
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					mode_lib->vba.BandwidthAvailableForImmediateFlip =
++							mode_lib->vba.BandwidthAvailableForImmediateFlip
++									- mode_lib->vba.cursor_bw[k]
++									- dml_max(
++											mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.qual_row_bw[k],
++											mode_lib->vba.PrefetchBW[k]);
++				}
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					mode_lib->vba.ImmediateFlipBytes[k] = 0.0;
++					if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
++							&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
++						mode_lib->vba.ImmediateFlipBytes[k] =
++								mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k]
++										+ mode_lib->vba.MetaRowBytes[k]
++										+ mode_lib->vba.DPTEBytesPerRow[k];
++					}
++				}
++				mode_lib->vba.TotImmediateFlipBytes = 0.0;
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
++							&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
++						mode_lib->vba.TotImmediateFlipBytes =
++								mode_lib->vba.TotImmediateFlipBytes
++										+ mode_lib->vba.ImmediateFlipBytes[k];
++					}
++				}
++
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					CalculateFlipSchedule(
++							mode_lib,
++							mode_lib->vba.ExtraLatency,
++							mode_lib->vba.UrgentLatencyPixelDataOnly,
++							mode_lib->vba.GPUVMMaxPageTableLevels,
++							mode_lib->vba.GPUVMEnable,
++							mode_lib->vba.BandwidthAvailableForImmediateFlip,
++							mode_lib->vba.TotImmediateFlipBytes,
++							mode_lib->vba.SourcePixelFormat[k],
++							mode_lib->vba.ImmediateFlipBytes[k],
++							mode_lib->vba.HTotal[k]
++									/ mode_lib->vba.PixelClock[k],
++							mode_lib->vba.VRatio[k],
++							mode_lib->vba.Tno_bw[k],
++							mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k],
++							mode_lib->vba.MetaRowBytes[k],
++							mode_lib->vba.DPTEBytesPerRow[k],
++							mode_lib->vba.DCCEnable[k],
++							mode_lib->vba.dpte_row_height[k],
++							mode_lib->vba.meta_row_height[k],
++							mode_lib->vba.qual_row_bw[k],
++							&mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k],
++							&mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k],
++							&mode_lib->vba.final_flip_bw[k],
++							&mode_lib->vba.ImmediateFlipSupportedForPipe[k]);
++				}
++				mode_lib->vba.total_dcn_read_bw_with_flip = 0.0;
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					mode_lib->vba.total_dcn_read_bw_with_flip =
++							mode_lib->vba.total_dcn_read_bw_with_flip
++									+ mode_lib->vba.cursor_bw[k]
++									+ dml_max3(
++											mode_lib->vba.prefetch_vm_bw[k],
++											mode_lib->vba.prefetch_row_bw[k],
++											mode_lib->vba.final_flip_bw[k]
++													+ dml_max(
++															mode_lib->vba.ReadBandwidth[k],
++															mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k]));
++				}
++				mode_lib->vba.ImmediateFlipSupportedForState[i][j] = true;
++				if (mode_lib->vba.total_dcn_read_bw_with_flip
++						> mode_lib->vba.ReturnBWPerState[i]) {
++					mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false;
++				}
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) {
++						mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false;
++					}
++				}
++			} else {
++				mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false;
++			}
++		}
++	}
++
++	/*Vertical Active BW support*/
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i] = dml_min(mode_lib->vba.ReturnBusWidth *
++				mode_lib->vba.DCFCLKPerState[i], mode_lib->vba.FabricAndDRAMBandwidthPerState[i] * 1000) *
++				mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation / 100;
++		if (mode_lib->vba.MaxTotalVActiveRDBandwidth <= mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i])
++			mode_lib->vba.TotalVerticalActiveBandwidthSupport[i] = true;
++		else
++			mode_lib->vba.TotalVerticalActiveBandwidthSupport[i] = false;
++	}
++
++	/*PTE Buffer Size Check*/
++
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		for (j = 0; j < 2; j++) {
++			locals->PTEBufferSizeNotExceeded[i][j] = true;
++			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++				if (locals->PTEBufferSizeNotExceededY[i][j][k] == false
++						|| locals->PTEBufferSizeNotExceededC[i][j][k] == false) {
++					locals->PTEBufferSizeNotExceeded[i][j] = false;
++				}
++			}
++		}
++	}
++	/*Cursor Support Check*/
++	mode_lib->vba.CursorSupport = true;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		for (j = 0; j < 2; j++) {
++			if (mode_lib->vba.CursorWidth[k][j] > 0.0) {
++				if (dml_floor(
++						dml_floor(
++								mode_lib->vba.CursorBufferSize
++										- mode_lib->vba.CursorChunkSize,
++								mode_lib->vba.CursorChunkSize) * 1024.0
++								/ (mode_lib->vba.CursorWidth[k][j]
++										* mode_lib->vba.CursorBPP[k][j]
++										/ 8.0),
++						1.0)
++						* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
++						/ mode_lib->vba.VRatio[k] < mode_lib->vba.UrgentLatencyPixelDataOnly
++						|| (mode_lib->vba.CursorBPP[k][j] == 64.0
++								&& mode_lib->vba.Cursor64BppSupport == false)) {
++					mode_lib->vba.CursorSupport = false;
++				}
++			}
++		}
++	}
++	/*Valid Pitch Check*/
++
++	mode_lib->vba.PitchSupport = true;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		locals->AlignedYPitch[k] = dml_ceil(
++				dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]),
++				locals->MacroTileWidthY[k]);
++		if (locals->AlignedYPitch[k] > mode_lib->vba.PitchY[k]) {
++			mode_lib->vba.PitchSupport = false;
++		}
++		if (mode_lib->vba.DCCEnable[k] == true) {
++			locals->AlignedDCCMetaPitch[k] = dml_ceil(
++					dml_max(
++							mode_lib->vba.DCCMetaPitchY[k],
++							mode_lib->vba.ViewportWidth[k]),
++					64.0 * locals->Read256BlockWidthY[k]);
++		} else {
++			locals->AlignedDCCMetaPitch[k] = mode_lib->vba.DCCMetaPitchY[k];
++		}
++		if (locals->AlignedDCCMetaPitch[k] > mode_lib->vba.DCCMetaPitchY[k]) {
++			mode_lib->vba.PitchSupport = false;
++		}
++		if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
++				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
++				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
++				&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
++				&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) {
++			locals->AlignedCPitch[k] = dml_ceil(
++					dml_max(
++							mode_lib->vba.PitchC[k],
++							mode_lib->vba.ViewportWidth[k] / 2.0),
++					locals->MacroTileWidthC[k]);
++		} else {
++			locals->AlignedCPitch[k] = mode_lib->vba.PitchC[k];
++		}
++		if (locals->AlignedCPitch[k] > mode_lib->vba.PitchC[k]) {
++			mode_lib->vba.PitchSupport = false;
++		}
++	}
++	/*Mode Support, Voltage State and SOC Configuration*/
++
++	for (i = mode_lib->vba.soc.num_states; i >= 0; i--) {
++		for (j = 0; j < 2; j++) {
++			enum dm_validation_status status = DML_VALIDATION_OK;
++
++			if (mode_lib->vba.ScaleRatioAndTapsSupport != true) {
++				status = DML_FAIL_SCALE_RATIO_TAP;
++			} else if (mode_lib->vba.SourceFormatPixelAndScanSupport != true) {
++				status = DML_FAIL_SOURCE_PIXEL_FORMAT;
++			} else if (locals->ViewportSizeSupport[i] != true) {
++				status = DML_FAIL_VIEWPORT_SIZE;
++			} else if (locals->DIOSupport[i] != true) {
++				status = DML_FAIL_DIO_SUPPORT;
++			} else if (locals->NotEnoughDSCUnits[i] != false) {
++				status = DML_FAIL_NOT_ENOUGH_DSC;
++			} else if (locals->DSCCLKRequiredMoreThanSupported[i] != false) {
++				status = DML_FAIL_DSC_CLK_REQUIRED;
++			} else if (locals->UrgentLatencySupport[i][j] != true) {
++				status = DML_FAIL_URGENT_LATENCY;
++			} else if (locals->ROBSupport[i] != true) {
++				status = DML_FAIL_REORDERING_BUFFER;
++			} else if (locals->DISPCLK_DPPCLK_Support[i][j] != true) {
++				status = DML_FAIL_DISPCLK_DPPCLK;
++			} else if (locals->TotalAvailablePipesSupport[i][j] != true) {
++				status = DML_FAIL_TOTAL_AVAILABLE_PIPES;
++			} else if (mode_lib->vba.NumberOfOTGSupport != true) {
++				status = DML_FAIL_NUM_OTG;
++			} else if (mode_lib->vba.WritebackModeSupport != true) {
++				status = DML_FAIL_WRITEBACK_MODE;
++			} else if (mode_lib->vba.WritebackLatencySupport != true) {
++				status = DML_FAIL_WRITEBACK_LATENCY;
++			} else if (mode_lib->vba.WritebackScaleRatioAndTapsSupport != true) {
++				status = DML_FAIL_WRITEBACK_SCALE_RATIO_TAP;
++			} else if (mode_lib->vba.CursorSupport != true) {
++				status = DML_FAIL_CURSOR_SUPPORT;
++			} else if (mode_lib->vba.PitchSupport != true) {
++				status = DML_FAIL_PITCH_SUPPORT;
++			} else if (locals->PrefetchSupported[i][j] != true) {
++				status = DML_FAIL_PREFETCH_SUPPORT;
++			} else if (locals->TotalVerticalActiveBandwidthSupport[i] != true) {
++				status = DML_FAIL_TOTAL_V_ACTIVE_BW;
++			} else if (locals->VRatioInPrefetchSupported[i][j] != true) {
++				status = DML_FAIL_V_RATIO_PREFETCH;
++			} else if (locals->PTEBufferSizeNotExceeded[i][j] != true) {
++				status = DML_FAIL_PTE_BUFFER_SIZE;
++			} else if (mode_lib->vba.NonsupportedDSCInputBPC != false) {
++				status = DML_FAIL_DSC_INPUT_BPC;
++			}
++
++			if (status == DML_VALIDATION_OK) {
++				locals->ModeSupport[i][j] = true;
++			} else {
++				locals->ModeSupport[i][j] = false;
++			}
++			locals->ValidationStatus[i] = status;
++		}
++	}
++	{
++		unsigned int MaximumMPCCombine = 0;
++		mode_lib->vba.VoltageLevel = mode_lib->vba.soc.num_states + 1;
++		for (i = mode_lib->vba.VoltageOverrideLevel; i <= mode_lib->vba.soc.num_states; i++) {
++			if (locals->ModeSupport[i][0] == true || locals->ModeSupport[i][1] == true) {
++				mode_lib->vba.VoltageLevel = i;
++				if (locals->ModeSupport[i][1] == true && (locals->ModeSupport[i][0] == false
++						|| mode_lib->vba.WhenToDoMPCCombine == dm_mpc_always_when_possible)) {
++					MaximumMPCCombine = 1;
++				} else {
++					MaximumMPCCombine = 0;
++				}
++				break;
++			}
++		}
++		mode_lib->vba.ImmediateFlipSupport =
++			locals->ImmediateFlipSupportedForState[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
++		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++			mode_lib->vba.DPPPerPlane[k] = locals->NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
++			locals->DPPCLK[k] = locals->RequiredDPPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
++		}
++		mode_lib->vba.DISPCLK = locals->RequiredDISPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
++		mode_lib->vba.maxMpcComb = MaximumMPCCombine;
++	}
++	mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKPerState[mode_lib->vba.VoltageLevel];
++	mode_lib->vba.DRAMSpeed = mode_lib->vba.DRAMSpeedPerState[mode_lib->vba.VoltageLevel];
++	mode_lib->vba.FabricClock = mode_lib->vba.FabricClockPerState[mode_lib->vba.VoltageLevel];
++	mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel];
++	mode_lib->vba.ReturnBW = locals->ReturnBWPerState[mode_lib->vba.VoltageLevel];
++	mode_lib->vba.FabricAndDRAMBandwidth = locals->FabricAndDRAMBandwidthPerState[mode_lib->vba.VoltageLevel];
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.BlendingAndTiming[k] == k) {
++			mode_lib->vba.ODMCombineEnabled[k] =
++					locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
++		} else {
++			mode_lib->vba.ODMCombineEnabled[k] = 0;
++		}
++		mode_lib->vba.DSCEnabled[k] =
++				locals->RequiresDSC[mode_lib->vba.VoltageLevel][k];
++		mode_lib->vba.OutputBpp[k] =
++				locals->OutputBppPerState[mode_lib->vba.VoltageLevel][k];
++	}
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.h b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.h
+new file mode 100644
+index 000000000000..a989d3ca1e99
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.h
+@@ -0,0 +1,32 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DCN20V2_DISPLAY_MODE_VBA_H_
++#define _DCN20V2_DISPLAY_MODE_VBA_H_
++
++void dml20v2_recalculate(struct display_mode_lib *mode_lib);
++void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
+new file mode 100644
+index 000000000000..ed8bf5f723c9
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
+@@ -0,0 +1,1701 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "../display_mode_lib.h"
++#include "../display_mode_vba.h"
++#include "display_rq_dlg_calc_20v2.h"
++
++// Function: dml20v2_rq_dlg_get_rq_params
++//  Calculate requestor related parameters that register definition agnostic
++//  (i.e. this layer does try to separate real values from register definition)
++// Input:
++//  pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
++// Output:
++//  rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
++//
++static void dml20v2_rq_dlg_get_rq_params(
++		struct display_mode_lib *mode_lib,
++		display_rq_params_st * rq_param,
++		const display_pipe_source_params_st pipe_src_param);
++
++// Function: dml20v2_rq_dlg_get_dlg_params
++//  Calculate deadline related parameters
++//
++static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
++		const display_e2e_pipe_params_st *e2e_pipe_param,
++		const unsigned int num_pipes,
++		const unsigned int pipe_idx,
++		display_dlg_regs_st *disp_dlg_regs,
++		display_ttu_regs_st *disp_ttu_regs,
++		const display_rq_dlg_params_st rq_dlg_param,
++		const display_dlg_sys_params_st dlg_sys_param,
++		const bool cstate_en,
++		const bool pstate_en);
++/*
++ * NOTE:
++ *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
++ *
++ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
++ * ways. Unless there is something clearly wrong with it the code should
++ * remain as-is as it provides us with a guarantee from HW that it is correct.
++ */
++
++static void calculate_ttu_cursor(struct display_mode_lib *mode_lib,
++		double *refcyc_per_req_delivery_pre_cur,
++		double *refcyc_per_req_delivery_cur,
++		double refclk_freq_in_mhz,
++		double ref_freq_to_pix_freq,
++		double hscale_pixel_rate_l,
++		double hscl_ratio,
++		double vratio_pre_l,
++		double vratio_l,
++		unsigned int cur_width,
++		enum cursor_bpp cur_bpp);
++
++#include "../dml_inline_defs.h"
++
++static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)
++{
++	unsigned int ret_val = 0;
++
++	if (source_format == dm_444_16) {
++		if (!is_chroma)
++			ret_val = 2;
++	} else if (source_format == dm_444_32) {
++		if (!is_chroma)
++			ret_val = 4;
++	} else if (source_format == dm_444_64) {
++		if (!is_chroma)
++			ret_val = 8;
++	} else if (source_format == dm_420_8) {
++		if (is_chroma)
++			ret_val = 2;
++		else
++			ret_val = 1;
++	} else if (source_format == dm_420_10) {
++		if (is_chroma)
++			ret_val = 4;
++		else
++			ret_val = 2;
++	} else if (source_format == dm_444_8) {
++		ret_val = 1;
++	}
++	return ret_val;
++}
++
++static bool is_dual_plane(enum source_format_class source_format)
++{
++	bool ret_val = 0;
++
++	if ((source_format == dm_420_8) || (source_format == dm_420_10))
++		ret_val = 1;
++
++	return ret_val;
++}
++
++static double get_refcyc_per_delivery(struct display_mode_lib *mode_lib,
++		double refclk_freq_in_mhz,
++		double pclk_freq_in_mhz,
++		bool odm_combine,
++		unsigned int recout_width,
++		unsigned int hactive,
++		double vratio,
++		double hscale_pixel_rate,
++		unsigned int delivery_width,
++		unsigned int req_per_swath_ub)
++{
++	double refcyc_per_delivery = 0.0;
++
++	if (vratio <= 1.0) {
++		if (odm_combine)
++			refcyc_per_delivery = (double) refclk_freq_in_mhz
++					* dml_min((double) recout_width, (double) hactive / 2.0)
++					/ pclk_freq_in_mhz / (double) req_per_swath_ub;
++		else
++			refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width
++					/ pclk_freq_in_mhz / (double) req_per_swath_ub;
++	} else {
++		refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width
++				/ (double) hscale_pixel_rate / (double) req_per_swath_ub;
++	}
++
++	dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz);
++	dml_print("DML_DLG: %s: pclk_freq_in_mhz   = %3.2f\n", __func__, pclk_freq_in_mhz);
++	dml_print("DML_DLG: %s: recout_width       = %d\n", __func__, recout_width);
++	dml_print("DML_DLG: %s: vratio             = %3.2f\n", __func__, vratio);
++	dml_print("DML_DLG: %s: req_per_swath_ub   = %d\n", __func__, req_per_swath_ub);
++	dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery);
++
++	return refcyc_per_delivery;
++
++}
++
++static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size)
++{
++	if (tile_size == dm_256k_tile)
++		return (256 * 1024);
++	else if (tile_size == dm_64k_tile)
++		return (64 * 1024);
++	else
++		return (4 * 1024);
++}
++
++static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib,
++		display_data_rq_regs_st *rq_regs,
++		const display_data_rq_sizing_params_st rq_sizing)
++{
++	dml_print("DML_DLG: %s: rq_sizing param\n", __func__);
++	print__data_rq_sizing_params_st(mode_lib, rq_sizing);
++
++	rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;
++
++	if (rq_sizing.min_chunk_bytes == 0)
++		rq_regs->min_chunk_size = 0;
++	else
++		rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
++
++	rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
++	if (rq_sizing.min_meta_chunk_bytes == 0)
++		rq_regs->min_meta_chunk_size = 0;
++	else
++		rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;
++
++	rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;
++	rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;
++}
++
++static void extract_rq_regs(struct display_mode_lib *mode_lib,
++		display_rq_regs_st *rq_regs,
++		const display_rq_params_st rq_param)
++{
++	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
++	unsigned int detile_buf_plane1_addr = 0;
++
++	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
++
++	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),
++			1) - 3;
++
++	if (rq_param.yuv420) {
++		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);
++		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),
++				1) - 3;
++	}
++
++	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
++	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
++
++	// FIXME: take the max between luma, chroma chunk size?
++	// okay for now, as we are setting chunk_bytes to 8kb anyways
++	if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb
++		rq_regs->drq_expansion_mode = 0;
++	} else {
++		rq_regs->drq_expansion_mode = 2;
++	}
++	rq_regs->prq_expansion_mode = 1;
++	rq_regs->mrq_expansion_mode = 1;
++	rq_regs->crq_expansion_mode = 1;
++
++	if (rq_param.yuv420) {
++		if ((double) rq_param.misc.rq_l.stored_swath_bytes
++				/ (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) {
++			detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma
++		} else {
++			detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0),
++					256,
++					0) / 64.0; // 2/3 to chroma
++		}
++	}
++	rq_regs->plane1_base_address = detile_buf_plane1_addr;
++}
++
++static void handle_det_buf_split(struct display_mode_lib *mode_lib,
++		display_rq_params_st *rq_param,
++		const display_pipe_source_params_st pipe_src_param)
++{
++	unsigned int total_swath_bytes = 0;
++	unsigned int swath_bytes_l = 0;
++	unsigned int swath_bytes_c = 0;
++	unsigned int full_swath_bytes_packed_l = 0;
++	unsigned int full_swath_bytes_packed_c = 0;
++	bool req128_l = 0;
++	bool req128_c = 0;
++	bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
++	bool surf_vert = (pipe_src_param.source_scan == dm_vert);
++	unsigned int log2_swath_height_l = 0;
++	unsigned int log2_swath_height_c = 0;
++	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
++
++	full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes;
++	full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes;
++
++	if (rq_param->yuv420_10bpc) {
++		full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2 / 3,
++				256,
++				1) + 256;
++		full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2 / 3,
++				256,
++				1) + 256;
++	}
++
++	if (rq_param->yuv420) {
++		total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c;
++
++		if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request
++			req128_l = 0;
++			req128_c = 0;
++			swath_bytes_l = full_swath_bytes_packed_l;
++			swath_bytes_c = full_swath_bytes_packed_c;
++		} else { //128b request (for luma only for yuv420 8bpc)
++			req128_l = 1;
++			req128_c = 0;
++			swath_bytes_l = full_swath_bytes_packed_l / 2;
++			swath_bytes_c = full_swath_bytes_packed_c;
++		}
++		// Note: assumption, the config that pass in will fit into
++		//       the detiled buffer.
++	} else {
++		total_swath_bytes = 2 * full_swath_bytes_packed_l;
++
++		if (total_swath_bytes <= detile_buf_size_in_bytes)
++			req128_l = 0;
++		else
++			req128_l = 1;
++
++		swath_bytes_l = total_swath_bytes;
++		swath_bytes_c = 0;
++	}
++	rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l;
++	rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c;
++
++	if (surf_linear) {
++		log2_swath_height_l = 0;
++		log2_swath_height_c = 0;
++	} else if (!surf_vert) {
++		log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l;
++		log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c;
++	} else {
++		log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l;
++		log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c;
++	}
++	rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
++	rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
++
++	dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l);
++	dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c);
++	dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n",
++			__func__,
++			full_swath_bytes_packed_l);
++	dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n",
++			__func__,
++			full_swath_bytes_packed_c);
++}
++
++static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib,
++		display_data_rq_dlg_params_st *rq_dlg_param,
++		display_data_rq_misc_params_st *rq_misc_param,
++		display_data_rq_sizing_params_st *rq_sizing_param,
++		unsigned int vp_width,
++		unsigned int vp_height,
++		unsigned int data_pitch,
++		unsigned int meta_pitch,
++		unsigned int source_format,
++		unsigned int tiling,
++		unsigned int macro_tile_size,
++		unsigned int source_scan,
++		unsigned int is_chroma)
++{
++	bool surf_linear = (tiling == dm_sw_linear);
++	bool surf_vert = (source_scan == dm_vert);
++
++	unsigned int bytes_per_element;
++	unsigned int bytes_per_element_y = get_bytes_per_element((enum source_format_class)(source_format),
++			false);
++	unsigned int bytes_per_element_c = get_bytes_per_element((enum source_format_class)(source_format),
++			true);
++
++	unsigned int blk256_width = 0;
++	unsigned int blk256_height = 0;
++
++	unsigned int blk256_width_y = 0;
++	unsigned int blk256_height_y = 0;
++	unsigned int blk256_width_c = 0;
++	unsigned int blk256_height_c = 0;
++	unsigned int log2_bytes_per_element;
++	unsigned int log2_blk256_width;
++	unsigned int log2_blk256_height;
++	unsigned int blk_bytes;
++	unsigned int log2_blk_bytes;
++	unsigned int log2_blk_height;
++	unsigned int log2_blk_width;
++	unsigned int log2_meta_req_bytes;
++	unsigned int log2_meta_req_height;
++	unsigned int log2_meta_req_width;
++	unsigned int meta_req_width;
++	unsigned int meta_req_height;
++	unsigned int log2_meta_row_height;
++	unsigned int meta_row_width_ub;
++	unsigned int log2_meta_chunk_bytes;
++	unsigned int log2_meta_chunk_height;
++
++	//full sized meta chunk width in unit of data elements
++	unsigned int log2_meta_chunk_width;
++	unsigned int log2_min_meta_chunk_bytes;
++	unsigned int min_meta_chunk_width;
++	unsigned int meta_chunk_width;
++	unsigned int meta_chunk_per_row_int;
++	unsigned int meta_row_remainder;
++	unsigned int meta_chunk_threshold;
++	unsigned int meta_blk_bytes;
++	unsigned int meta_blk_height;
++	unsigned int meta_blk_width;
++	unsigned int meta_surface_bytes;
++	unsigned int vmpg_bytes;
++	unsigned int meta_pte_req_per_frame_ub;
++	unsigned int meta_pte_bytes_per_frame_ub;
++	const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
++	const unsigned int dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma;
++	const unsigned int pde_proc_buffer_size_64k_reqs =
++			mode_lib->ip.pde_proc_buffer_size_64k_reqs;
++
++	unsigned int log2_vmpg_height = 0;
++	unsigned int log2_vmpg_width = 0;
++	unsigned int log2_dpte_req_height_ptes = 0;
++	unsigned int log2_dpte_req_height = 0;
++	unsigned int log2_dpte_req_width = 0;
++	unsigned int log2_dpte_row_height_linear = 0;
++	unsigned int log2_dpte_row_height = 0;
++	unsigned int log2_dpte_group_width = 0;
++	unsigned int dpte_row_width_ub = 0;
++	unsigned int dpte_req_height = 0;
++	unsigned int dpte_req_width = 0;
++	unsigned int dpte_group_width = 0;
++	unsigned int log2_dpte_group_bytes = 0;
++	unsigned int log2_dpte_group_length = 0;
++	unsigned int pde_buf_entries;
++	bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10);
++
++	Calculate256BBlockSizes((enum source_format_class)(source_format),
++			(enum dm_swizzle_mode)(tiling),
++			bytes_per_element_y,
++			bytes_per_element_c,
++			&blk256_height_y,
++			&blk256_height_c,
++			&blk256_width_y,
++			&blk256_width_c);
++
++	if (!is_chroma) {
++		blk256_width = blk256_width_y;
++		blk256_height = blk256_height_y;
++		bytes_per_element = bytes_per_element_y;
++	} else {
++		blk256_width = blk256_width_c;
++		blk256_height = blk256_height_c;
++		bytes_per_element = bytes_per_element_c;
++	}
++
++	log2_bytes_per_element = dml_log2(bytes_per_element);
++
++	dml_print("DML_DLG: %s: surf_linear        = %d\n", __func__, surf_linear);
++	dml_print("DML_DLG: %s: surf_vert          = %d\n", __func__, surf_vert);
++	dml_print("DML_DLG: %s: blk256_width       = %d\n", __func__, blk256_width);
++	dml_print("DML_DLG: %s: blk256_height      = %d\n", __func__, blk256_height);
++
++	log2_blk256_width = dml_log2((double) blk256_width);
++	log2_blk256_height = dml_log2((double) blk256_height);
++	blk_bytes = surf_linear ?
++			256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);
++	log2_blk_bytes = dml_log2((double) blk_bytes);
++	log2_blk_height = 0;
++	log2_blk_width = 0;
++
++	// remember log rule
++	// "+" in log is multiply
++	// "-" in log is divide
++	// "/2" is like square root
++	// blk is vertical biased
++	if (tiling != dm_sw_linear)
++		log2_blk_height = log2_blk256_height
++				+ dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
++	else
++		log2_blk_height = 0;  // blk height of 1
++
++	log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
++
++	if (!surf_vert) {
++		rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1)
++				+ blk256_width;
++		rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width;
++	} else {
++		rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_height - 1, blk256_height, 1)
++				+ blk256_height;
++		rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height;
++	}
++
++	if (!surf_vert)
++		rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height
++				* bytes_per_element;
++	else
++		rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width
++				* bytes_per_element;
++
++	rq_misc_param->blk256_height = blk256_height;
++	rq_misc_param->blk256_width = blk256_width;
++
++	// -------
++	// meta
++	// -------
++	log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element
++
++	// each 64b meta request for dcn is 8x8 meta elements and
++	// a meta element covers one 256b block of the the data surface.
++	log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256
++	log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element
++			- log2_meta_req_height;
++	meta_req_width = 1 << log2_meta_req_width;
++	meta_req_height = 1 << log2_meta_req_height;
++	log2_meta_row_height = 0;
++	meta_row_width_ub = 0;
++
++	// the dimensions of a meta row are meta_row_width x meta_row_height in elements.
++	// calculate upper bound of the meta_row_width
++	if (!surf_vert) {
++		log2_meta_row_height = log2_meta_req_height;
++		meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
++				+ meta_req_width;
++		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
++	} else {
++		log2_meta_row_height = log2_meta_req_width;
++		meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1)
++				+ meta_req_height;
++		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height;
++	}
++	rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64;
++
++	rq_dlg_param->meta_row_height = 1 << log2_meta_row_height;
++
++	log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes);
++	log2_meta_chunk_height = log2_meta_row_height;
++
++	//full sized meta chunk width in unit of data elements
++	log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element
++			- log2_meta_chunk_height;
++	log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes);
++	min_meta_chunk_width = 1
++			<< (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element
++					- log2_meta_chunk_height);
++	meta_chunk_width = 1 << log2_meta_chunk_width;
++	meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width);
++	meta_row_remainder = meta_row_width_ub % meta_chunk_width;
++	meta_chunk_threshold = 0;
++	meta_blk_bytes = 4096;
++	meta_blk_height = blk256_height * 64;
++	meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height;
++	meta_surface_bytes = meta_pitch
++			* (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height)
++			* bytes_per_element / 256;
++	vmpg_bytes = mode_lib->soc.vmm_page_size_bytes;
++	meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes,
++			8 * vmpg_bytes,
++			1) + 8 * vmpg_bytes) / (8 * vmpg_bytes);
++	meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request
++	rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub;
++
++	dml_print("DML_DLG: %s: meta_blk_height             = %d\n", __func__, meta_blk_height);
++	dml_print("DML_DLG: %s: meta_blk_width              = %d\n", __func__, meta_blk_width);
++	dml_print("DML_DLG: %s: meta_surface_bytes          = %d\n", __func__, meta_surface_bytes);
++	dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub   = %d\n",
++			__func__,
++			meta_pte_req_per_frame_ub);
++	dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n",
++			__func__,
++			meta_pte_bytes_per_frame_ub);
++
++	if (!surf_vert)
++		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
++	else
++		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
++
++	if (meta_row_remainder <= meta_chunk_threshold)
++		rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
++	else
++		rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
++
++	// ------
++	// dpte
++	// ------
++	if (surf_linear) {
++		log2_vmpg_height = 0;   // one line high
++	} else {
++		log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
++	}
++	log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
++
++	// only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4.
++	if (surf_linear) { //one 64B PTE request returns 8 PTEs
++		log2_dpte_req_height_ptes = 0;
++		log2_dpte_req_width = log2_vmpg_width + 3;
++		log2_dpte_req_height = 0;
++	} else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size
++		//one 64B req gives 8x1 PTEs for 4KB tile
++		log2_dpte_req_height_ptes = 0;
++		log2_dpte_req_width = log2_blk_width + 3;
++		log2_dpte_req_height = log2_blk_height + 0;
++	} else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB
++		//two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB
++		log2_dpte_req_height_ptes = 4;
++		log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width
++		log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height
++	} else { //64KB page size and must 64KB tile block
++		 //one 64B req gives 8x1 PTEs for 64KB tile
++		log2_dpte_req_height_ptes = 0;
++		log2_dpte_req_width = log2_blk_width + 3;
++		log2_dpte_req_height = log2_blk_height + 0;
++	}
++
++	// The dpte request dimensions in data elements is dpte_req_width x dpte_req_height
++	// log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent
++	// That depends on the pte shape (i.e. 8x1, 4x2, 2x4)
++	//log2_dpte_req_height    = log2_vmpg_height + log2_dpte_req_height_ptes;
++	//log2_dpte_req_width     = log2_vmpg_width + log2_dpte_req_width_ptes;
++	dpte_req_height = 1 << log2_dpte_req_height;
++	dpte_req_width = 1 << log2_dpte_req_width;
++
++	// calculate pitch dpte row buffer can hold
++	// round the result down to a power of two.
++	pde_buf_entries = yuv420 ? (pde_proc_buffer_size_64k_reqs >> 1) : pde_proc_buffer_size_64k_reqs;
++	if (surf_linear) {
++		unsigned int dpte_row_height;
++
++		log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries
++										/ bytes_per_element,
++								dpte_buf_in_pte_reqs
++										* dpte_req_width)
++								/ data_pitch),
++				1);
++
++		ASSERT(log2_dpte_row_height_linear >= 3);
++
++		if (log2_dpte_row_height_linear > 7)
++			log2_dpte_row_height_linear = 7;
++
++		log2_dpte_row_height = log2_dpte_row_height_linear;
++		// For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary.
++		// the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
++		dpte_row_height = 1 << log2_dpte_row_height;
++		dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1,
++				dpte_req_width,
++				1) + dpte_req_width;
++		rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
++	} else {
++		// the upper bound of the dpte_row_width without dependency on viewport position follows.
++		// for tiled mode, row height is the same as req height and row store up to vp size upper bound
++		if (!surf_vert) {
++			log2_dpte_row_height = log2_dpte_req_height;
++			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
++					+ dpte_req_width;
++			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
++		} else {
++			log2_dpte_row_height =
++					(log2_blk_width < log2_dpte_req_width) ?
++							log2_blk_width : log2_dpte_req_width;
++			dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
++					+ dpte_req_height;
++			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
++		}
++	}
++	if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB
++		rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request
++	else
++		rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request
++
++	rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
++
++	// the dpte_group_bytes is reduced for the specific case of vertical
++	// access of a tile surface that has dpte request of 8x1 ptes.
++	if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group
++		rq_sizing_param->dpte_group_bytes = 512;
++	else
++		//full size
++		rq_sizing_param->dpte_group_bytes = 2048;
++
++	//since pte request size is 64byte, the number of data pte requests per full sized group is as follows.
++	log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes);
++	log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests
++
++	// full sized data pte group width in elements
++	if (!surf_vert)
++		log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width;
++	else
++		log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height;
++
++	//But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B
++	if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB
++		log2_dpte_group_width = log2_dpte_group_width - 1;
++
++	dpte_group_width = 1 << log2_dpte_group_width;
++
++	// since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
++	// the upper bound for the dpte groups per row is as follows.
++	rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width,
++			1);
++}
++
++static void get_surf_rq_param(struct display_mode_lib *mode_lib,
++		display_data_rq_sizing_params_st *rq_sizing_param,
++		display_data_rq_dlg_params_st *rq_dlg_param,
++		display_data_rq_misc_params_st *rq_misc_param,
++		const display_pipe_source_params_st pipe_src_param,
++		bool is_chroma)
++{
++	bool mode_422 = 0;
++	unsigned int vp_width = 0;
++	unsigned int vp_height = 0;
++	unsigned int data_pitch = 0;
++	unsigned int meta_pitch = 0;
++	unsigned int ppe = mode_422 ? 2 : 1;
++
++	// FIXME check if ppe apply for both luma and chroma in 422 case
++	if (is_chroma) {
++		vp_width = pipe_src_param.viewport_width_c / ppe;
++		vp_height = pipe_src_param.viewport_height_c;
++		data_pitch = pipe_src_param.data_pitch_c;
++		meta_pitch = pipe_src_param.meta_pitch_c;
++	} else {
++		vp_width = pipe_src_param.viewport_width / ppe;
++		vp_height = pipe_src_param.viewport_height;
++		data_pitch = pipe_src_param.data_pitch;
++		meta_pitch = pipe_src_param.meta_pitch;
++	}
++
++	rq_sizing_param->chunk_bytes = 8192;
++
++	if (rq_sizing_param->chunk_bytes == 64 * 1024)
++		rq_sizing_param->min_chunk_bytes = 0;
++	else
++		rq_sizing_param->min_chunk_bytes = 1024;
++
++	rq_sizing_param->meta_chunk_bytes = 2048;
++	rq_sizing_param->min_meta_chunk_bytes = 256;
++
++	rq_sizing_param->mpte_group_bytes = 2048;
++
++	get_meta_and_pte_attr(mode_lib,
++			rq_dlg_param,
++			rq_misc_param,
++			rq_sizing_param,
++			vp_width,
++			vp_height,
++			data_pitch,
++			meta_pitch,
++			pipe_src_param.source_format,
++			pipe_src_param.sw_mode,
++			pipe_src_param.macro_tile_size,
++			pipe_src_param.source_scan,
++			is_chroma);
++}
++
++static void dml20v2_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib,
++		display_rq_params_st *rq_param,
++		const display_pipe_source_params_st pipe_src_param)
++{
++	// get param for luma surface
++	rq_param->yuv420 = pipe_src_param.source_format == dm_420_8
++			|| pipe_src_param.source_format == dm_420_10;
++	rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10;
++
++	get_surf_rq_param(mode_lib,
++			&(rq_param->sizing.rq_l),
++			&(rq_param->dlg.rq_l),
++			&(rq_param->misc.rq_l),
++			pipe_src_param,
++			0);
++
++	if (is_dual_plane((enum source_format_class)(pipe_src_param.source_format))) {
++		// get param for chroma surface
++		get_surf_rq_param(mode_lib,
++				&(rq_param->sizing.rq_c),
++				&(rq_param->dlg.rq_c),
++				&(rq_param->misc.rq_c),
++				pipe_src_param,
++				1);
++	}
++
++	// calculate how to split the det buffer space between luma and chroma
++	handle_det_buf_split(mode_lib, rq_param, pipe_src_param);
++	print__rq_params_st(mode_lib, *rq_param);
++}
++
++void dml20v2_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
++		display_rq_regs_st *rq_regs,
++		const display_pipe_params_st pipe_param)
++{
++	display_rq_params_st rq_param = {0};
++
++	memset(rq_regs, 0, sizeof(*rq_regs));
++	dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param.src);
++	extract_rq_regs(mode_lib, rq_regs, rq_param);
++
++	print__rq_regs_st(mode_lib, *rq_regs);
++}
++
++// Note: currently taken in as is.
++// Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma.
++static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
++		const display_e2e_pipe_params_st *e2e_pipe_param,
++		const unsigned int num_pipes,
++		const unsigned int pipe_idx,
++		display_dlg_regs_st *disp_dlg_regs,
++		display_ttu_regs_st *disp_ttu_regs,
++		const display_rq_dlg_params_st rq_dlg_param,
++		const display_dlg_sys_params_st dlg_sys_param,
++		const bool cstate_en,
++		const bool pstate_en)
++{
++	const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
++	const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
++	const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout;
++	const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
++	const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
++	const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;
++
++	// -------------------------
++	// Section 1.15.2.1: OTG dependent Params
++	// -------------------------
++	// Timing
++	unsigned int htotal = dst->htotal;
++//    unsigned int hblank_start = dst.hblank_start; // TODO: Remove
++	unsigned int hblank_end = dst->hblank_end;
++	unsigned int vblank_start = dst->vblank_start;
++	unsigned int vblank_end = dst->vblank_end;
++	unsigned int min_vblank = mode_lib->ip.min_vblank_lines;
++
++	double dppclk_freq_in_mhz = clks->dppclk_mhz;
++	double dispclk_freq_in_mhz = clks->dispclk_mhz;
++	double refclk_freq_in_mhz = clks->refclk_mhz;
++	double pclk_freq_in_mhz = dst->pixel_rate_mhz;
++	bool interlaced = dst->interlaced;
++
++	double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
++
++	double min_dcfclk_mhz;
++	double t_calc_us;
++	double min_ttu_vblank;
++
++	double min_dst_y_ttu_vblank;
++	unsigned int dlg_vblank_start;
++	bool dual_plane;
++	bool mode_422;
++	unsigned int access_dir;
++	unsigned int vp_height_l;
++	unsigned int vp_width_l;
++	unsigned int vp_height_c;
++	unsigned int vp_width_c;
++
++	// Scaling
++	unsigned int htaps_l;
++	unsigned int htaps_c;
++	double hratio_l;
++	double hratio_c;
++	double vratio_l;
++	double vratio_c;
++	bool scl_enable;
++
++	double line_time_in_us;
++	//    double vinit_l;
++	//    double vinit_c;
++	//    double vinit_bot_l;
++	//    double vinit_bot_c;
++
++	//    unsigned int swath_height_l;
++	unsigned int swath_width_ub_l;
++	//    unsigned int dpte_bytes_per_row_ub_l;
++	unsigned int dpte_groups_per_row_ub_l;
++	//    unsigned int meta_pte_bytes_per_frame_ub_l;
++	//    unsigned int meta_bytes_per_row_ub_l;
++
++	//    unsigned int swath_height_c;
++	unsigned int swath_width_ub_c;
++	//   unsigned int dpte_bytes_per_row_ub_c;
++	unsigned int dpte_groups_per_row_ub_c;
++
++	unsigned int meta_chunks_per_row_ub_l;
++	unsigned int meta_chunks_per_row_ub_c;
++	unsigned int vupdate_offset;
++	unsigned int vupdate_width;
++	unsigned int vready_offset;
++
++	unsigned int dppclk_delay_subtotal;
++	unsigned int dispclk_delay_subtotal;
++	unsigned int pixel_rate_delay_subtotal;
++
++	unsigned int vstartup_start;
++	unsigned int dst_x_after_scaler;
++	unsigned int dst_y_after_scaler;
++	double line_wait;
++	double dst_y_prefetch;
++	double dst_y_per_vm_vblank;
++	double dst_y_per_row_vblank;
++	double dst_y_per_vm_flip;
++	double dst_y_per_row_flip;
++	double min_dst_y_per_vm_vblank;
++	double min_dst_y_per_row_vblank;
++	double lsw;
++	double vratio_pre_l;
++	double vratio_pre_c;
++	unsigned int req_per_swath_ub_l;
++	unsigned int req_per_swath_ub_c;
++	unsigned int meta_row_height_l;
++	unsigned int meta_row_height_c;
++	unsigned int swath_width_pixels_ub_l;
++	unsigned int swath_width_pixels_ub_c;
++	unsigned int scaler_rec_in_width_l;
++	unsigned int scaler_rec_in_width_c;
++	unsigned int dpte_row_height_l;
++	unsigned int dpte_row_height_c;
++	double hscale_pixel_rate_l;
++	double hscale_pixel_rate_c;
++	double min_hratio_fact_l;
++	double min_hratio_fact_c;
++	double refcyc_per_line_delivery_pre_l;
++	double refcyc_per_line_delivery_pre_c;
++	double refcyc_per_line_delivery_l;
++	double refcyc_per_line_delivery_c;
++
++	double refcyc_per_req_delivery_pre_l;
++	double refcyc_per_req_delivery_pre_c;
++	double refcyc_per_req_delivery_l;
++	double refcyc_per_req_delivery_c;
++
++	unsigned int full_recout_width;
++	double xfc_transfer_delay;
++	double xfc_precharge_delay;
++	double xfc_remote_surface_flip_latency;
++	double xfc_dst_y_delta_drq_limit;
++	double xfc_prefetch_margin;
++	double refcyc_per_req_delivery_pre_cur0;
++	double refcyc_per_req_delivery_cur0;
++	double refcyc_per_req_delivery_pre_cur1;
++	double refcyc_per_req_delivery_cur1;
++
++	memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
++	memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
++
++	dml_print("DML_DLG: %s:  cstate_en = %d\n", __func__, cstate_en);
++	dml_print("DML_DLG: %s:  pstate_en = %d\n", __func__, pstate_en);
++
++	dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n", __func__, dppclk_freq_in_mhz);
++	dml_print("DML_DLG: %s: dispclk_freq_in_mhz    = %3.2f\n", __func__, dispclk_freq_in_mhz);
++	dml_print("DML_DLG: %s: refclk_freq_in_mhz     = %3.2f\n", __func__, refclk_freq_in_mhz);
++	dml_print("DML_DLG: %s: pclk_freq_in_mhz       = %3.2f\n", __func__, pclk_freq_in_mhz);
++	dml_print("DML_DLG: %s: interlaced             = %d\n", __func__, interlaced);
++	ASSERT(ref_freq_to_pix_freq < 4.0);
++
++	disp_dlg_regs->ref_freq_to_pix_freq =
++			(unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
++	disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal
++			* dml_pow(2, 8));
++	disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
++	disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end
++			* (double) ref_freq_to_pix_freq);
++	ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));
++
++	min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;
++	t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes);
++	min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++
++	min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
++	dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
++
++	disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start
++			+ min_dst_y_ttu_vblank) * dml_pow(2, 2));
++	ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
++
++	dml_print("DML_DLG: %s: min_dcfclk_mhz                         = %3.2f\n",
++			__func__,
++			min_dcfclk_mhz);
++	dml_print("DML_DLG: %s: min_ttu_vblank                         = %3.2f\n",
++			__func__,
++			min_ttu_vblank);
++	dml_print("DML_DLG: %s: min_dst_y_ttu_vblank                   = %3.2f\n",
++			__func__,
++			min_dst_y_ttu_vblank);
++	dml_print("DML_DLG: %s: t_calc_us                              = %3.2f\n",
++			__func__,
++			t_calc_us);
++	dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start    = 0x%0x\n",
++			__func__,
++			disp_dlg_regs->min_dst_y_next_start);
++	dml_print("DML_DLG: %s: ref_freq_to_pix_freq                   = %3.2f\n",
++			__func__,
++			ref_freq_to_pix_freq);
++
++	// -------------------------
++	// Section 1.15.2.2: Prefetch, Active and TTU
++	// -------------------------
++	// Prefetch Calc
++	// Source
++//             dcc_en              = src.dcc;
++	dual_plane = is_dual_plane((enum source_format_class)(src->source_format));
++	mode_422 = 0; // FIXME
++	access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
++//      bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0);
++//      bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1);
++	vp_height_l = src->viewport_height;
++	vp_width_l = src->viewport_width;
++	vp_height_c = src->viewport_height_c;
++	vp_width_c = src->viewport_width_c;
++
++	// Scaling
++	htaps_l = taps->htaps;
++	htaps_c = taps->htaps_c;
++	hratio_l = scl->hscl_ratio;
++	hratio_c = scl->hscl_ratio_c;
++	vratio_l = scl->vscl_ratio;
++	vratio_c = scl->vscl_ratio_c;
++	scl_enable = scl->scl_enable;
++
++	line_time_in_us = (htotal / pclk_freq_in_mhz);
++//     vinit_l         = scl.vinit;
++//     vinit_c         = scl.vinit_c;
++//     vinit_bot_l     = scl.vinit_bot;
++//     vinit_bot_c     = scl.vinit_bot_c;
++
++//    unsigned int swath_height_l                 = rq_dlg_param.rq_l.swath_height;
++	swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub;
++//    unsigned int dpte_bytes_per_row_ub_l        = rq_dlg_param.rq_l.dpte_bytes_per_row_ub;
++	dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub;
++//    unsigned int meta_pte_bytes_per_frame_ub_l  = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub;
++//    unsigned int meta_bytes_per_row_ub_l        = rq_dlg_param.rq_l.meta_bytes_per_row_ub;
++
++//    unsigned int swath_height_c                 = rq_dlg_param.rq_c.swath_height;
++	swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub;
++	//   dpte_bytes_per_row_ub_c        = rq_dlg_param.rq_c.dpte_bytes_per_row_ub;
++	dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub;
++
++	meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub;
++	meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub;
++	vupdate_offset = dst->vupdate_offset;
++	vupdate_width = dst->vupdate_width;
++	vready_offset = dst->vready_offset;
++
++	dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal;
++	dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal;
++
++	if (scl_enable)
++		dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl;
++	else
++		dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only;
++
++	dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter
++			+ src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor;
++
++	if (dout->dsc_enable) {
++		double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++
++		dispclk_delay_subtotal += dsc_delay;
++	}
++
++	pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz
++			+ dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz;
++
++	vstartup_start = dst->vstartup_start;
++	if (interlaced) {
++		if (vstartup_start / 2.0
++				- (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
++				<= vblank_end / 2.0)
++			disp_dlg_regs->vready_after_vcount0 = 1;
++		else
++			disp_dlg_regs->vready_after_vcount0 = 0;
++	} else {
++		if (vstartup_start
++				- (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
++				<= vblank_end)
++			disp_dlg_regs->vready_after_vcount0 = 1;
++		else
++			disp_dlg_regs->vready_after_vcount0 = 0;
++	}
++
++	// TODO: Where is this coming from?
++	if (interlaced)
++		vstartup_start = vstartup_start / 2;
++
++	// TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp?
++	if (vstartup_start >= min_vblank) {
++		dml_print("WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n",
++				__func__,
++				vblank_start,
++				vblank_end);
++		dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",
++				__func__,
++				vstartup_start,
++				min_vblank);
++		min_vblank = vstartup_start + 1;
++		dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",
++				__func__,
++				vstartup_start,
++				min_vblank);
++	}
++
++	dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++	dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++
++	dml_print("DML_DLG: %s: htotal                                 = %d\n", __func__, htotal);
++	dml_print("DML_DLG: %s: pixel_rate_delay_subtotal              = %d\n",
++			__func__,
++			pixel_rate_delay_subtotal);
++	dml_print("DML_DLG: %s: dst_x_after_scaler                     = %d\n",
++			__func__,
++			dst_x_after_scaler);
++	dml_print("DML_DLG: %s: dst_y_after_scaler                     = %d\n",
++			__func__,
++			dst_y_after_scaler);
++
++	// Lwait
++	line_wait = mode_lib->soc.urgent_latency_us;
++	if (cstate_en)
++		line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait);
++	if (pstate_en)
++		line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us
++						+ mode_lib->soc.urgent_latency_us,
++				line_wait);
++	line_wait = line_wait / line_time_in_us;
++
++	dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++	dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch);
++
++	dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib,
++			e2e_pipe_param,
++			num_pipes,
++			pipe_idx);
++	dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib,
++			e2e_pipe_param,
++			num_pipes,
++			pipe_idx);
++	dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++	dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++
++	min_dst_y_per_vm_vblank = 8.0;
++	min_dst_y_per_row_vblank = 16.0;
++
++	// magic!
++	if (htotal <= 75) {
++		min_vblank = 300;
++		min_dst_y_per_vm_vblank = 100.0;
++		min_dst_y_per_row_vblank = 100.0;
++	}
++
++	dml_print("DML_DLG: %s: dst_y_per_vm_vblank    = %3.2f\n", __func__, dst_y_per_vm_vblank);
++	dml_print("DML_DLG: %s: dst_y_per_row_vblank   = %3.2f\n", __func__, dst_y_per_row_vblank);
++
++	ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank);
++	ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank);
++
++	ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
++	lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank);
++
++	dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw);
++
++	vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++	vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++
++	dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l);
++	dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c);
++
++	// Active
++	req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub;
++	req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub;
++	meta_row_height_l = rq_dlg_param.rq_l.meta_row_height;
++	meta_row_height_c = rq_dlg_param.rq_c.meta_row_height;
++	swath_width_pixels_ub_l = 0;
++	swath_width_pixels_ub_c = 0;
++	scaler_rec_in_width_l = 0;
++	scaler_rec_in_width_c = 0;
++	dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
++	dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
++
++	if (mode_422) {
++		swath_width_pixels_ub_l = swath_width_ub_l * 2;  // *2 for 2 pixel per element
++		swath_width_pixels_ub_c = swath_width_ub_c * 2;
++	} else {
++		swath_width_pixels_ub_l = swath_width_ub_l * 1;
++		swath_width_pixels_ub_c = swath_width_ub_c * 1;
++	}
++
++	hscale_pixel_rate_l = 0.;
++	hscale_pixel_rate_c = 0.;
++	min_hratio_fact_l = 1.0;
++	min_hratio_fact_c = 1.0;
++
++	if (htaps_l <= 1)
++		min_hratio_fact_l = 2.0;
++	else if (htaps_l <= 6) {
++		if ((hratio_l * 2.0) > 4.0)
++			min_hratio_fact_l = 4.0;
++		else
++			min_hratio_fact_l = hratio_l * 2.0;
++	} else {
++		if (hratio_l > 4.0)
++			min_hratio_fact_l = 4.0;
++		else
++			min_hratio_fact_l = hratio_l;
++	}
++
++	hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;
++
++	if (htaps_c <= 1)
++		min_hratio_fact_c = 2.0;
++	else if (htaps_c <= 6) {
++		if ((hratio_c * 2.0) > 4.0)
++			min_hratio_fact_c = 4.0;
++		else
++			min_hratio_fact_c = hratio_c * 2.0;
++	} else {
++		if (hratio_c > 4.0)
++			min_hratio_fact_c = 4.0;
++		else
++			min_hratio_fact_c = hratio_c;
++	}
++
++	hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz;
++
++	refcyc_per_line_delivery_pre_l = 0.;
++	refcyc_per_line_delivery_pre_c = 0.;
++	refcyc_per_line_delivery_l = 0.;
++	refcyc_per_line_delivery_c = 0.;
++
++	refcyc_per_req_delivery_pre_l = 0.;
++	refcyc_per_req_delivery_pre_c = 0.;
++	refcyc_per_req_delivery_l = 0.;
++	refcyc_per_req_delivery_c = 0.;
++
++	full_recout_width = 0;
++	// In ODM
++	if (src->is_hsplit) {
++		// This "hack"  is only allowed (and valid) for MPC combine. In ODM
++		// combine, you MUST specify the full_recout_width...according to Oswin
++		if (dst->full_recout_width == 0 && !dst->odm_combine) {
++			dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n",
++					__func__);
++			full_recout_width = dst->recout_width * 2; // assume half split for dcn1
++		} else
++			full_recout_width = dst->full_recout_width;
++	} else
++		full_recout_width = dst->recout_width;
++
++	// As of DCN2, mpc_combine and odm_combine are mutually exclusive
++	refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib,
++			refclk_freq_in_mhz,
++			pclk_freq_in_mhz,
++			dst->odm_combine,
++			full_recout_width,
++			dst->hactive,
++			vratio_pre_l,
++			hscale_pixel_rate_l,
++			swath_width_pixels_ub_l,
++			1); // per line
++
++	refcyc_per_line_delivery_l = get_refcyc_per_delivery(mode_lib,
++			refclk_freq_in_mhz,
++			pclk_freq_in_mhz,
++			dst->odm_combine,
++			full_recout_width,
++			dst->hactive,
++			vratio_l,
++			hscale_pixel_rate_l,
++			swath_width_pixels_ub_l,
++			1); // per line
++
++	dml_print("DML_DLG: %s: full_recout_width              = %d\n",
++			__func__,
++			full_recout_width);
++	dml_print("DML_DLG: %s: hscale_pixel_rate_l            = %3.2f\n",
++			__func__,
++			hscale_pixel_rate_l);
++	dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n",
++			__func__,
++			refcyc_per_line_delivery_pre_l);
++	dml_print("DML_DLG: %s: refcyc_per_line_delivery_l     = %3.2f\n",
++			__func__,
++			refcyc_per_line_delivery_l);
++
++	if (dual_plane) {
++		refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(mode_lib,
++				refclk_freq_in_mhz,
++				pclk_freq_in_mhz,
++				dst->odm_combine,
++				full_recout_width,
++				dst->hactive,
++				vratio_pre_c,
++				hscale_pixel_rate_c,
++				swath_width_pixels_ub_c,
++				1); // per line
++
++		refcyc_per_line_delivery_c = get_refcyc_per_delivery(mode_lib,
++				refclk_freq_in_mhz,
++				pclk_freq_in_mhz,
++				dst->odm_combine,
++				full_recout_width,
++				dst->hactive,
++				vratio_c,
++				hscale_pixel_rate_c,
++				swath_width_pixels_ub_c,
++				1);  // per line
++
++		dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n",
++				__func__,
++				refcyc_per_line_delivery_pre_c);
++		dml_print("DML_DLG: %s: refcyc_per_line_delivery_c     = %3.2f\n",
++				__func__,
++				refcyc_per_line_delivery_c);
++	}
++
++	// TTU - Luma / Chroma
++	if (access_dir) {  // vertical access
++		scaler_rec_in_width_l = vp_height_l;
++		scaler_rec_in_width_c = vp_height_c;
++	} else {
++		scaler_rec_in_width_l = vp_width_l;
++		scaler_rec_in_width_c = vp_width_c;
++	}
++
++	refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(mode_lib,
++			refclk_freq_in_mhz,
++			pclk_freq_in_mhz,
++			dst->odm_combine,
++			full_recout_width,
++			dst->hactive,
++			vratio_pre_l,
++			hscale_pixel_rate_l,
++			scaler_rec_in_width_l,
++			req_per_swath_ub_l);  // per req
++	refcyc_per_req_delivery_l = get_refcyc_per_delivery(mode_lib,
++			refclk_freq_in_mhz,
++			pclk_freq_in_mhz,
++			dst->odm_combine,
++			full_recout_width,
++			dst->hactive,
++			vratio_l,
++			hscale_pixel_rate_l,
++			scaler_rec_in_width_l,
++			req_per_swath_ub_l);  // per req
++
++	dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n",
++			__func__,
++			refcyc_per_req_delivery_pre_l);
++	dml_print("DML_DLG: %s: refcyc_per_req_delivery_l     = %3.2f\n",
++			__func__,
++			refcyc_per_req_delivery_l);
++
++	ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
++	ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
++
++	if (dual_plane) {
++		refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(mode_lib,
++				refclk_freq_in_mhz,
++				pclk_freq_in_mhz,
++				dst->odm_combine,
++				full_recout_width,
++				dst->hactive,
++				vratio_pre_c,
++				hscale_pixel_rate_c,
++				scaler_rec_in_width_c,
++				req_per_swath_ub_c);  // per req
++		refcyc_per_req_delivery_c = get_refcyc_per_delivery(mode_lib,
++				refclk_freq_in_mhz,
++				pclk_freq_in_mhz,
++				dst->odm_combine,
++				full_recout_width,
++				dst->hactive,
++				vratio_c,
++				hscale_pixel_rate_c,
++				scaler_rec_in_width_c,
++				req_per_swath_ub_c);  // per req
++
++		dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n",
++				__func__,
++				refcyc_per_req_delivery_pre_c);
++		dml_print("DML_DLG: %s: refcyc_per_req_delivery_c     = %3.2f\n",
++				__func__,
++				refcyc_per_req_delivery_c);
++
++		ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
++		ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
++	}
++
++	// XFC
++	xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++	xfc_precharge_delay = get_xfc_precharge_delay(mode_lib,
++			e2e_pipe_param,
++			num_pipes,
++			pipe_idx);
++	xfc_remote_surface_flip_latency = get_xfc_remote_surface_flip_latency(mode_lib,
++			e2e_pipe_param,
++			num_pipes,
++			pipe_idx);
++	xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency;
++	xfc_prefetch_margin = get_xfc_prefetch_margin(mode_lib,
++			e2e_pipe_param,
++			num_pipes,
++			pipe_idx);
++
++	// TTU - Cursor
++	refcyc_per_req_delivery_pre_cur0 = 0.0;
++	refcyc_per_req_delivery_cur0 = 0.0;
++	if (src->num_cursors > 0) {
++		calculate_ttu_cursor(mode_lib,
++				&refcyc_per_req_delivery_pre_cur0,
++				&refcyc_per_req_delivery_cur0,
++				refclk_freq_in_mhz,
++				ref_freq_to_pix_freq,
++				hscale_pixel_rate_l,
++				scl->hscl_ratio,
++				vratio_pre_l,
++				vratio_l,
++				src->cur0_src_width,
++				(enum cursor_bpp)(src->cur0_bpp));
++	}
++
++	refcyc_per_req_delivery_pre_cur1 = 0.0;
++	refcyc_per_req_delivery_cur1 = 0.0;
++	if (src->num_cursors > 1) {
++		calculate_ttu_cursor(mode_lib,
++				&refcyc_per_req_delivery_pre_cur1,
++				&refcyc_per_req_delivery_cur1,
++				refclk_freq_in_mhz,
++				ref_freq_to_pix_freq,
++				hscale_pixel_rate_l,
++				scl->hscl_ratio,
++				vratio_pre_l,
++				vratio_l,
++				src->cur1_src_width,
++				(enum cursor_bpp)(src->cur1_bpp));
++	}
++
++	// TTU - Misc
++	// all hard-coded
++
++	// Assignment to register structures
++	disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line
++	disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk
++	ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));
++	disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
++	disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
++	disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
++	disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));
++	disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
++
++	disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
++	disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
++
++	disp_dlg_regs->refcyc_per_pte_group_vblank_l =
++			(unsigned int) (dst_y_per_row_vblank * (double) htotal
++					* ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
++	ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));
++
++	if (dual_plane) {
++		disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank
++				* (double) htotal * ref_freq_to_pix_freq
++				/ (double) dpte_groups_per_row_ub_c);
++		ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c
++						< (unsigned int) dml_pow(2, 13));
++	}
++
++	disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
++			(unsigned int) (dst_y_per_row_vblank * (double) htotal
++					* ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l);
++	ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));
++
++	disp_dlg_regs->refcyc_per_meta_chunk_vblank_c =
++			disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
++
++	disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
++			* ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l;
++	disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
++			* ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l;
++
++	if (dual_plane) {
++		disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip
++				* htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c;
++		disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip
++				* htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c;
++	}
++
++	disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l
++			/ (double) vratio_l * dml_pow(2, 2));
++	ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));
++
++	if (dual_plane) {
++		disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c
++				/ (double) vratio_c * dml_pow(2, 2));
++		if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {
++			dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n",
++					__func__,
++					disp_dlg_regs->dst_y_per_pte_row_nom_c,
++					(unsigned int) dml_pow(2, 17) - 1);
++		}
++	}
++
++	disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l
++			/ (double) vratio_l * dml_pow(2, 2));
++	ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));
++
++	disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
++
++	disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l
++			/ (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
++			/ (double) dpte_groups_per_row_ub_l);
++	if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
++		disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
++	disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l
++			/ (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
++			/ (double) meta_chunks_per_row_ub_l);
++	if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
++		disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
++
++	if (dual_plane) {
++		disp_dlg_regs->refcyc_per_pte_group_nom_c =
++				(unsigned int) ((double) dpte_row_height_c / (double) vratio_c
++						* (double) htotal * ref_freq_to_pix_freq
++						/ (double) dpte_groups_per_row_ub_c);
++		if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
++			disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
++
++		// TODO: Is this the right calculation? Does htotal need to be halved?
++		disp_dlg_regs->refcyc_per_meta_chunk_nom_c =
++				(unsigned int) ((double) meta_row_height_c / (double) vratio_c
++						* (double) htotal * ref_freq_to_pix_freq
++						/ (double) meta_chunks_per_row_ub_c);
++		if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))
++			disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;
++	}
++
++	disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l,
++			1);
++	disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l,
++			1);
++	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));
++	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));
++
++	disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c,
++			1);
++	disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c,
++			1);
++	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13));
++	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));
++
++	disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
++	disp_dlg_regs->dst_y_offset_cur0 = 0;
++	disp_dlg_regs->chunk_hdl_adjust_cur1 = 3;
++	disp_dlg_regs->dst_y_offset_cur1 = 0;
++
++	disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay;
++	disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay;
++	disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency;
++	disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(xfc_prefetch_margin * refclk_freq_in_mhz,
++			1);
++
++	// slave has to have this value also set to off
++	if (src->xfc_enable && !src->xfc_slave)
++		disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
++	else
++		disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
++
++	disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l
++			* dml_pow(2, 10));
++	disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l
++			* dml_pow(2, 10));
++	disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c
++			* dml_pow(2, 10));
++	disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c
++			* dml_pow(2, 10));
++	disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 =
++			(unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
++	disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0
++			* dml_pow(2, 10));
++	disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 =
++			(unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));
++	disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1
++			* dml_pow(2, 10));
++	disp_ttu_regs->qos_level_low_wm = 0;
++	ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
++	disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
++			* ref_freq_to_pix_freq);
++	/*ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));*/
++
++	disp_ttu_regs->qos_level_flip = 14;
++	disp_ttu_regs->qos_level_fixed_l = 8;
++	disp_ttu_regs->qos_level_fixed_c = 8;
++	disp_ttu_regs->qos_level_fixed_cur0 = 8;
++	disp_ttu_regs->qos_ramp_disable_l = 0;
++	disp_ttu_regs->qos_ramp_disable_c = 0;
++	disp_ttu_regs->qos_ramp_disable_cur0 = 0;
++
++	disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
++	ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
++
++	print__ttu_regs_st(mode_lib, *disp_ttu_regs);
++	print__dlg_regs_st(mode_lib, *disp_dlg_regs);
++}
++
++void dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
++		display_dlg_regs_st *dlg_regs,
++		display_ttu_regs_st *ttu_regs,
++		display_e2e_pipe_params_st *e2e_pipe_param,
++		const unsigned int num_pipes,
++		const unsigned int pipe_idx,
++		const bool cstate_en,
++		const bool pstate_en,
++		const bool vm_en,
++		const bool ignore_viewport_pos,
++		const bool immediate_flip_support)
++{
++	display_rq_params_st rq_param = {0};
++	display_dlg_sys_params_st dlg_sys_param = {0};
++
++	// Get watermark and Tex.
++	dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes);
++	dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib,
++			e2e_pipe_param,
++			num_pipes);
++	dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes);
++	dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes);
++	dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes);
++	dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes);
++	dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib,
++			e2e_pipe_param,
++			num_pipes);
++	dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib,
++			e2e_pipe_param,
++			num_pipes);
++	dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency
++			/ dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated
++
++	print__dlg_sys_params_st(mode_lib, dlg_sys_param);
++
++	// system parameter calculation done
++
++	dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx);
++	dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe.src);
++	dml20v2_rq_dlg_get_dlg_params(mode_lib,
++			e2e_pipe_param,
++			num_pipes,
++			pipe_idx,
++			dlg_regs,
++			ttu_regs,
++			rq_param.dlg,
++			dlg_sys_param,
++			cstate_en,
++			pstate_en);
++	dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
++}
++
++static void calculate_ttu_cursor(struct display_mode_lib *mode_lib,
++		double *refcyc_per_req_delivery_pre_cur,
++		double *refcyc_per_req_delivery_cur,
++		double refclk_freq_in_mhz,
++		double ref_freq_to_pix_freq,
++		double hscale_pixel_rate_l,
++		double hscl_ratio,
++		double vratio_pre_l,
++		double vratio_l,
++		unsigned int cur_width,
++		enum cursor_bpp cur_bpp)
++{
++	unsigned int cur_src_width = cur_width;
++	unsigned int cur_req_size = 0;
++	unsigned int cur_req_width = 0;
++	double cur_width_ub = 0.0;
++	double cur_req_per_width = 0.0;
++	double hactive_cur = 0.0;
++
++	ASSERT(cur_src_width <= 256);
++
++	*refcyc_per_req_delivery_pre_cur = 0.0;
++	*refcyc_per_req_delivery_cur = 0.0;
++	if (cur_src_width > 0) {
++		unsigned int cur_bit_per_pixel = 0;
++
++		if (cur_bpp == dm_cur_2bit) {
++			cur_req_size = 64; // byte
++			cur_bit_per_pixel = 2;
++		} else { // 32bit
++			cur_bit_per_pixel = 32;
++			if (cur_src_width >= 1 && cur_src_width <= 16)
++				cur_req_size = 64;
++			else if (cur_src_width >= 17 && cur_src_width <= 31)
++				cur_req_size = 128;
++			else
++				cur_req_size = 256;
++		}
++
++		cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0);
++		cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1)
++				* (double) cur_req_width;
++		cur_req_per_width = cur_width_ub / (double) cur_req_width;
++		hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor
++
++		if (vratio_pre_l <= 1.0) {
++			*refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq
++					/ (double) cur_req_per_width;
++		} else {
++			*refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz
++					* (double) cur_src_width / hscale_pixel_rate_l
++					/ (double) cur_req_per_width;
++		}
++
++		ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
++
++		if (vratio_l <= 1.0) {
++			*refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq
++					/ (double) cur_req_per_width;
++		} else {
++			*refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz
++					* (double) cur_src_width / hscale_pixel_rate_l
++					/ (double) cur_req_per_width;
++		}
++
++		dml_print("DML_DLG: %s: cur_req_width                     = %d\n",
++				__func__,
++				cur_req_width);
++		dml_print("DML_DLG: %s: cur_width_ub                      = %3.2f\n",
++				__func__,
++				cur_width_ub);
++		dml_print("DML_DLG: %s: cur_req_per_width                 = %3.2f\n",
++				__func__,
++				cur_req_per_width);
++		dml_print("DML_DLG: %s: hactive_cur                       = %3.2f\n",
++				__func__,
++				hactive_cur);
++		dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur   = %3.2f\n",
++				__func__,
++				*refcyc_per_req_delivery_pre_cur);
++		dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur       = %3.2f\n",
++				__func__,
++				*refcyc_per_req_delivery_cur);
++
++		ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
++	}
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
+new file mode 100644
+index 000000000000..0378406bf7e7
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
+@@ -0,0 +1,74 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DML20V2_DISPLAY_RQ_DLG_CALC_H__
++#define __DML20V2_DISPLAY_RQ_DLG_CALC_H__
++
++#include "../dml_common_defs.h"
++#include "../display_rq_dlg_helpers.h"
++
++struct display_mode_lib;
++
++
++// Function: dml_rq_dlg_get_rq_reg
++//  Main entry point for test to get the register values out of this DML class.
++//  This function calls <get_rq_param> and <extract_rq_regs> fucntions to calculate
++//  and then populate the rq_regs struct
++// Input:
++//  pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
++// Output:
++//  rq_regs - struct that holds all the RQ registers field value.
++//            See also: <display_rq_regs_st>
++void dml20v2_rq_dlg_get_rq_reg(
++		struct display_mode_lib *mode_lib,
++		display_rq_regs_st *rq_regs,
++		const display_pipe_params_st pipe_param);
++
++
++// Function: dml_rq_dlg_get_dlg_reg
++//   Calculate and return DLG and TTU register struct given the system setting
++// Output:
++//  dlg_regs - output DLG register struct
++//  ttu_regs - output DLG TTU register struct
++// Input:
++//  e2e_pipe_param - "compacted" array of e2e pipe param struct
++//  num_pipes - num of active "pipe" or "route"
++//  pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
++//  cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
++//           Added for legacy or unrealistic timing tests.
++void dml20v2_rq_dlg_get_dlg_reg(
++		struct display_mode_lib *mode_lib,
++		display_dlg_regs_st *dlg_regs,
++		display_ttu_regs_st *ttu_regs,
++		display_e2e_pipe_params_st *e2e_pipe_param,
++		const unsigned int num_pipes,
++		const unsigned int pipe_idx,
++		const bool cstate_en,
++		const bool pstate_en,
++		const bool vm_en,
++		const bool ignore_viewport_pos,
++		const bool immediate_flip_support);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+index 91810c7d5cf5..96dfcd8c36bc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+@@ -28,6 +28,8 @@
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "dcn20/display_mode_vba_20.h"
+ #include "dcn20/display_rq_dlg_calc_20.h"
++#include "dcn20/display_mode_vba_20v2.h"
++#include "dcn20/display_rq_dlg_calc_20v2.h"
+ #endif
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+@@ -37,6 +39,13 @@ const struct dml_funcs dml20_funcs = {
+ 	.rq_dlg_get_dlg_reg = dml20_rq_dlg_get_dlg_reg,
+ 	.rq_dlg_get_rq_reg = dml20_rq_dlg_get_rq_reg
+ };
++
++const struct dml_funcs dml20v2_funcs = {
++	.validate = dml20v2_ModeSupportAndSystemConfigurationFull,
++	.recalculate = dml20v2_recalculate,
++	.rq_dlg_get_dlg_reg = dml20v2_rq_dlg_get_dlg_reg,
++	.rq_dlg_get_rq_reg = dml20v2_rq_dlg_get_rq_reg
++};
+ #endif
+ 
+ void dml_init_instance(struct display_mode_lib *lib,
+@@ -52,6 +61,9 @@ void dml_init_instance(struct display_mode_lib *lib,
+ 	case DML_PROJECT_NAVI10:
+ 		lib->funcs = dml20_funcs;
+ 		break;
++	case DML_PROJECT_NAVI10v2:
++		lib->funcs = dml20v2_funcs;
++		break;
+ #endif
+ 	default:
+ 		break;
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+index 5bf13d67f289..870716e3c132 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+@@ -36,6 +36,7 @@ enum dml_project {
+ 	DML_PROJECT_RAVEN1,
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	DML_PROJECT_NAVI10,
++	DML_PROJECT_NAVI10v2,
+ #endif
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+index 5678472546ab..ab34fd26702f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+@@ -100,6 +100,7 @@ struct _vcs_dpi_soc_bounding_box_st {
+ 	unsigned int vmm_page_size_bytes;
+ 	unsigned int hostvm_min_page_size_bytes;
+ 	double dram_clock_change_latency_us;
++	double dummy_pstate_latency_us;
+ 	double writeback_dram_clock_change_latency_us;
+ 	unsigned int return_bus_width_bytes;
+ 	unsigned int voltage_override;
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+index 4d2a1262d9db..88e63f16f7fc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+@@ -568,6 +568,7 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
+ 		if (src->is_hsplit) {
+ 			for (k = j + 1; k < mode_lib->vba.cache_num_pipes; ++k) {
+ 				display_pipe_source_params_st *src_k = &pipes[k].pipe.src;
++				display_pipe_dest_params_st *dst_k = &pipes[k].pipe.dest;
+ 
+ 				if (src_k->is_hsplit && !visited[k]
+ 						&& src->hsplit_grp == src_k->hsplit_grp) {
+@@ -575,12 +576,15 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
+ 							mode_lib->vba.NumberOfActivePlanes;
+ 					mode_lib->vba.DPPPerPlane[mode_lib->vba.NumberOfActivePlanes]++;
+ 					if (mode_lib->vba.SourceScan[mode_lib->vba.NumberOfActivePlanes]
+-							== dm_horz)
++							== dm_horz) {
+ 						mode_lib->vba.ViewportWidth[mode_lib->vba.NumberOfActivePlanes] +=
+ 								src_k->viewport_width;
+-					else
++						mode_lib->vba.ScalerRecoutWidth[mode_lib->vba.NumberOfActivePlanes] +=
++								dst_k->recout_width;
++					} else {
+ 						mode_lib->vba.ViewportHeight[mode_lib->vba.NumberOfActivePlanes] +=
+ 								src_k->viewport_height;
++					}
+ 
+ 					visited[k] = true;
+ 				}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3091-drm-amd-display-Add-SMU-version-field-to-clk_mgr_int.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3091-drm-amd-display-Add-SMU-version-field-to-clk_mgr_int.patch
new file mode 100644
index 00000000..5b204ef6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3091-drm-amd-display-Add-SMU-version-field-to-clk_mgr_int.patch
@@ -0,0 +1,32 @@
+From a2f23ec0c8a1d38f4a64cdbaa8a2128f5599aadb Mon Sep 17 00:00:00 2001
+From: Fatemeh Darbehani <fatemeh.darbehani@amd.com>
+Date: Wed, 10 Jul 2019 10:34:31 -0400
+Subject: [PATCH 3091/4256] drm/amd/display: Add SMU version field to
+ clk_mgr_internal
+
+For some platforms, we need to know SMU version for driver/SMU
+compatibility. This change adds that field.
+
+Change-Id: I2586161fb645bf0d16d30c91954a871f83e87edf
+Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+index 3c105124dcdd..4b5505fa980c 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+@@ -191,6 +191,7 @@ struct state_dependent_clocks {
+ 
+ struct clk_mgr_internal {
+ 	struct clk_mgr base;
++	int smu_ver;
+ 	struct pp_smu_funcs *pp_smu;
+ 	struct clk_mgr_internal_funcs *funcs;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3092-drm-amd-display-avoid-power-gate-domains-that-doesn-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3092-drm-amd-display-avoid-power-gate-domains-that-doesn-.patch
new file mode 100644
index 00000000..40c472f6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3092-drm-amd-display-avoid-power-gate-domains-that-doesn-.patch
@@ -0,0 +1,78 @@
+From d88601b2e31af39ade3f7059907a5cb44425e481 Mon Sep 17 00:00:00 2001
+From: Tony Cheng <tony.cheng@amd.com>
+Date: Sun, 23 Jun 2019 12:07:02 -0500
+Subject: [PATCH 3092/4256] drm/amd/display: avoid power gate domains that
+ doesn't exist
+
+Change-Id: I7800685ccebbf8faa2b7185c501ac0ad78e13e48
+Signed-off-by: Tony Cheng <tony.cheng@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dce/dce_hwseq.h    |  4 ++--
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 24 ++++++++++++-------
+ 2 files changed, 17 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+index 3a49f1ffb5dd..245b80b92681 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+@@ -227,8 +227,8 @@
+ 	SR(DOMAIN7_PG_CONFIG), \
+ 	SR(DOMAIN8_PG_CONFIG), \
+ 	SR(DOMAIN9_PG_CONFIG), \
+-	SR(DOMAIN10_PG_CONFIG), \
+-	SR(DOMAIN11_PG_CONFIG), \
++/*	SR(DOMAIN10_PG_CONFIG), Navi1x HUBP5 not powergate-able*/\
++/*	SR(DOMAIN11_PG_CONFIG), Navi1x DPP5 is not powergate-able */\
+ 	SR(DOMAIN16_PG_CONFIG), \
+ 	SR(DOMAIN17_PG_CONFIG), \
+ 	SR(DOMAIN18_PG_CONFIG), \
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 08a96faef775..6f990f772a8b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -94,25 +94,31 @@ static void enable_power_gating_plane(
+ 	REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
+ 	REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
+ 	REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
+-	REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
+-	/*Do not power gate DCHUB5, should be left at HW default, power on permanently*/
+-	/*REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, force_on);*/
++	if (REG(DOMAIN8_PG_CONFIG))
++		REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
++	if (REG(DOMAIN10_PG_CONFIG))
++		REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
+ 
+ 	/* DPP0/1/2/3/4/5 */
+ 	REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
+ 	REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
+ 	REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
+ 	REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
+-	REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
+-	/*Do not power gate DPP5, should be left at HW default, power on permanently*/
+-	/*REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, force_on);*/
++	if (REG(DOMAIN9_PG_CONFIG))
++		REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
++	if (REG(DOMAIN11_PG_CONFIG))
++		REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
+ 
++	/* DCS0/1/2/3/4/5 */
+ 	REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
+ 	REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
+ 	REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
+-	REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
+-	REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
+-	REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
++	if (REG(DOMAIN19_PG_CONFIG))
++		REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
++	if (REG(DOMAIN20_PG_CONFIG))
++		REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
++	if (REG(DOMAIN21_PG_CONFIG))
++		REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
+ }
+ 
+ void dcn20_dccg_init(struct dce_hwseq *hws)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3093-drm-amd-display-Add-debug-entry-to-destroy-disconnec.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3093-drm-amd-display-Add-debug-entry-to-destroy-disconnec.patch
new file mode 100644
index 00000000..67266058
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3093-drm-amd-display-Add-debug-entry-to-destroy-disconnec.patch
@@ -0,0 +1,67 @@
+From 0d4087e3311bc196972bfa8820912e2ad464411c Mon Sep 17 00:00:00 2001
+From: Lewis Huang <Lewis.Huang@amd.com>
+Date: Tue, 2 Jul 2019 22:33:34 -0500
+Subject: [PATCH 3093/4256] drm/amd/display: Add debug entry to destroy
+ disconnected edp link
+
+Add a flag to dc_debug_options to determine if a disconnected edp link
+should be destroyed.
+
+Change-Id: I49ccabe2cedc02d49fe3cd085710ea7459bca205
+Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 20 ++++++++++++++++----
+ drivers/gpu/drm/amd/display/dc/dc.h      |  1 +
+ 2 files changed, 17 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 886fcc1e701f..ecf562e386cb 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -184,13 +184,25 @@ static bool create_links(
+ 		link = link_create(&link_init_params);
+ 
+ 		if (link) {
+-			if (dc->config.edp_not_connected &&
+-					link->connector_signal == SIGNAL_TYPE_EDP) {
+-				link_destroy(&link);
+-			} else {
++			bool should_destory_link = false;
++
++			if (link->connector_signal == SIGNAL_TYPE_EDP) {
++				if (dc->config.edp_not_connected)
++					should_destory_link = true;
++				else if (dc->debug.remove_disconnect_edp) {
++					enum dc_connection_type type;
++					dc_link_detect_sink(link, &type);
++					if (type == dc_connection_none)
++						should_destory_link = true;
++				}
++			}
++
++			if (!should_destory_link) {
+ 				dc->links[dc->link_count] = link;
+ 				link->dc = dc;
+ 				++dc->link_count;
++			} else {
++				link_destroy(&link);
+ 			}
+ 		}
+ 	}
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 8d890468908f..85e1ce5d5225 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -381,6 +381,7 @@ struct dc_debug_options {
+ 	bool scl_reset_length10;
+ 	bool hdmi20_disable;
+ 	bool skip_detection_link_training;
++	bool remove_disconnect_edp;
+ 	unsigned int force_odm_combine; //bit vector based on otg inst
+ 	unsigned int force_fclk_khz;
+ 	bool disable_tri_buf;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3094-drm-amd-display-Copy-GSL-groups-when-committing-a-ne.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3094-drm-amd-display-Copy-GSL-groups-when-committing-a-ne.patch
new file mode 100644
index 00000000..f94dae6c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3094-drm-amd-display-Copy-GSL-groups-when-committing-a-ne.patch
@@ -0,0 +1,72 @@
+From 51f35bffb53f14e148cde05c10091fa45eaad8eb Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Thu, 11 Jul 2019 12:32:43 -0400
+Subject: [PATCH 3094/4256] drm/amd/display: Copy GSL groups when committing a
+ new context
+
+[Why]
+DC configures the GSL group for the pipe when pipe_split is enabled
+and we're switching flip types (buffered <-> immediate flip) on DCN2.
+
+In order to record what GSL group the pipe is using DC stores it in
+the pipe's stream_res. DM is not aware of this internal grouping, nor
+is DC resource.
+
+So when DM creates a dc_state context and passes it to DC the current
+GSL group is lost - DM never knew about it in the first place.
+
+After 3 immediate flips we run out of GSL groups and we're no longer
+able to correctly perform *any* flip for multi-pipe scenarios.
+
+[How]
+The gsl_group needs to be copied to the new context.
+
+DM has no insight into GSL grouping and could even potentially create
+a brand new context without referencing current hardware state. So this
+makes the most sense to have happen in DC.
+
+There are two places where DC can apply a new context:
+- dc_commit_state
+- dc_commit_updates_for_stream
+
+But what's shared between both of these is apply_ctx_for_surface.
+
+This logic only matters for DCN2, so it can be placed in
+dcn20_apply_ctx_for_surface. Before doing any locking (where the GSL
+group is setup) we can copy over the GSL groups before committing the
+new context.
+
+Change-Id: Id73647f50058dbe130e15fee23fa91ec37c67682
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersen.wu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 6f990f772a8b..38b3c89b2a59 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1366,6 +1366,18 @@ static void dcn20_apply_ctx_for_surface(
+ 	if (!top_pipe_to_program)
+ 		return;
+ 
++	/* Carry over GSL groups in case the context is changing. */
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
++		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
++		struct pipe_ctx *old_pipe_ctx =
++			&dc->current_state->res_ctx.pipe_ctx[i];
++
++		if (pipe_ctx->stream == stream &&
++		    pipe_ctx->stream == old_pipe_ctx->stream)
++			pipe_ctx->stream_res.gsl_group =
++				old_pipe_ctx->stream_res.gsl_group;
++	}
++
+ 	tg = top_pipe_to_program->stream_res.tg;
+ 
+ 	interdependent_update = top_pipe_to_program->plane_state &&
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3095-drm-amd-display-handle-active-dongle-port-type-is-DP.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3095-drm-amd-display-handle-active-dongle-port-type-is-DP.patch
new file mode 100644
index 00000000..ac80e147
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3095-drm-amd-display-handle-active-dongle-port-type-is-DP.patch
@@ -0,0 +1,103 @@
+From 3edc48db116e53270a1547acab1c70e29a02b08b Mon Sep 17 00:00:00 2001
+From: Dale Zhao <dale.zhao@amd.com>
+Date: Wed, 10 Jul 2019 17:36:53 +0800
+Subject: [PATCH 3095/4256] drm/amd/display: handle active dongle port type is
+ DP++ or DP case
+
+[Why]:
+Some active dongles have DP++ port and DP port at the same time. Current
+code doesn't cover DP++ case and processes as default DVI case, in which
+audio is disabled. Because of dual mode, DP case is also treat as DVI case
+for the other port.
+
+[How]:
+According DP 1.4 spec, add DP++ procedure similar with HDMI case. Also
+add None dongle type for DP case.
+
+Change-Id: I15c02256326d319ba66c1bba44d8e669353aface
+Signed-off-by: Dale Zhao <dale.zhao@amd.com>
+Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 30 ++++++++++++-------
+ .../gpu/drm/amd/display/include/dpcd_defs.h   |  2 +-
+ 2 files changed, 21 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index b512fecae061..08bd9c96b9b0 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2398,8 +2398,8 @@ static void get_active_converter_info(
+ 	case DOWNSTREAM_VGA:
+ 		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
+ 		break;
+-	case DOWNSTREAM_DVI_HDMI:
+-		/* At this point we don't know is it DVI or HDMI,
++	case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
++		/* At this point we don't know is it DVI or HDMI or DP++,
+ 		 * assume DVI.*/
+ 		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
+ 		break;
+@@ -2416,6 +2416,10 @@ static void get_active_converter_info(
+ 				det_caps, sizeof(det_caps));
+ 
+ 		switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
++		/*Handle DP case as DONGLE_NONE*/
++		case DOWN_STREAM_DETAILED_DP:
++			link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
++			break;
+ 		case DOWN_STREAM_DETAILED_VGA:
+ 			link->dpcd_caps.dongle_type =
+ 				DISPLAY_DONGLE_DP_VGA_CONVERTER;
+@@ -2425,6 +2429,8 @@ static void get_active_converter_info(
+ 				DISPLAY_DONGLE_DP_DVI_CONVERTER;
+ 			break;
+ 		case DOWN_STREAM_DETAILED_HDMI:
++		case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
++			/*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
+ 			link->dpcd_caps.dongle_type =
+ 				DISPLAY_DONGLE_DP_HDMI_CONVERTER;
+ 
+@@ -2440,14 +2446,18 @@ static void get_active_converter_info(
+ 
+ 				link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
+ 					hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
+-				link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
+-					hdmi_caps.bits.YCrCr422_PASS_THROUGH;
+-				link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
+-					hdmi_caps.bits.YCrCr420_PASS_THROUGH;
+-				link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
+-					hdmi_caps.bits.YCrCr422_CONVERSION;
+-				link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
+-					hdmi_caps.bits.YCrCr420_CONVERSION;
++				/*YCBCR capability only for HDMI case*/
++				if (port_caps->bits.DWN_STRM_PORTX_TYPE
++						== DOWN_STREAM_DETAILED_HDMI) {
++					link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
++							hdmi_caps.bits.YCrCr422_PASS_THROUGH;
++					link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
++							hdmi_caps.bits.YCrCr420_PASS_THROUGH;
++					link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
++							hdmi_caps.bits.YCrCr422_CONVERSION;
++					link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
++							hdmi_caps.bits.YCrCr420_CONVERSION;
++				}
+ 
+ 				link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
+ 					translate_dpcd_max_bpc(
+diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h b/drivers/gpu/drm/amd/display/include/dpcd_defs.h
+index 1c66166d0a94..2c90d1b46c8b 100644
+--- a/drivers/gpu/drm/amd/display/include/dpcd_defs.h
++++ b/drivers/gpu/drm/amd/display/include/dpcd_defs.h
+@@ -43,7 +43,7 @@ enum dpcd_revision {
+ enum dpcd_downstream_port_type {
+ 	DOWNSTREAM_DP = 0,
+ 	DOWNSTREAM_VGA,
+-	DOWNSTREAM_DVI_HDMI,
++	DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS,/* DVI, HDMI, DP++ */
+ 	DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3096-drm-ttm-use-the-same-attributes-when-freeing-d_page-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3096-drm-ttm-use-the-same-attributes-when-freeing-d_page-.patch
new file mode 100644
index 00000000..f2437881
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3096-drm-ttm-use-the-same-attributes-when-freeing-d_page-.patch
@@ -0,0 +1,42 @@
+From de39f009ae0d7c04cdb5978b0b417f29441a142a Mon Sep 17 00:00:00 2001
+From: Fuqian Huang <huangfq.daxian@gmail.com>
+Date: Thu, 11 Jul 2019 11:10:21 +0800
+Subject: [PATCH 3096/4256] drm/ttm: use the same attributes when freeing
+ d_page->vaddr
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+In function __ttm_dma_alloc_page(), d_page->addr is allocated
+by dma_alloc_attrs() but freed with use dma_free_coherent() in
+__ttm_dma_free_page().
+Use the correct dma_free_attrs() to free d_page->vaddr.
+
+Signed-off-by: Fuqian Huang <huangfq.daxian@gmail.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
+index 507be7ac1165..c326ac4e6b1f 100644
+--- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
++++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
+@@ -285,9 +285,13 @@ static int ttm_set_pages_caching(struct dma_pool *pool,
+ 
+ static void __ttm_dma_free_page(struct dma_pool *pool, struct dma_page *d_page)
+ {
++	unsigned long attrs = 0;
+ 	dma_addr_t dma = d_page->dma;
+ 	d_page->vaddr &= ~VADDR_FLAG_HUGE_POOL;
+-	dma_free_coherent(pool->dev, pool->size, (void *)d_page->vaddr, dma);
++	if (pool->type & IS_HUGE)
++		attrs = DMA_ATTR_NO_WARN;
++
++	dma_free_attrs(pool->dev, pool->size, (void *)d_page->vaddr, dma, attrs);
+ 
+ 	kfree(d_page);
+ 	d_page = NULL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3097-drm-amdgpu-use-VCN-firmware-offset-for-cache-window.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3097-drm-amdgpu-use-VCN-firmware-offset-for-cache-window.patch
new file mode 100644
index 00000000..98213237
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3097-drm-amdgpu-use-VCN-firmware-offset-for-cache-window.patch
@@ -0,0 +1,35 @@
+From 9e826714589cab98de8d435fec585ef5026afc94 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Thu, 18 Jul 2019 11:38:46 -0400
+Subject: [PATCH 3097/4256] drm/amdgpu: use VCN firmware offset for cache
+ window
+
+Since we are using the signed FW now, and also using PSP firmware loading,
+but it's still potential to break driver when loading FW directly
+instead of PSP, so we should add offset.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+index 3cb62e448a37..88e3dedcf926 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+@@ -379,11 +379,8 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
+ 		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+ 			upper_32_bits(adev->vcn.inst->gpu_addr));
+ 		offset = size;
+-		/* No signed header for now from firmware
+ 		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
+ 			AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
+-		*/
+-		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
+ 	}
+ 
+ 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3098-drm-amdgpu-pm-remove-check-for-pp-funcs-in-freq-sysf.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3098-drm-amdgpu-pm-remove-check-for-pp-funcs-in-freq-sysf.patch
new file mode 100644
index 00000000..5a5e26af
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3098-drm-amdgpu-pm-remove-check-for-pp-funcs-in-freq-sysf.patch
@@ -0,0 +1,46 @@
+From a1cd7d5813e190882ad829984d298dad2821706d Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 17 Jul 2019 13:10:39 -0500
+Subject: [PATCH 3098/4256] drm/amdgpu/pm: remove check for pp funcs in freq
+ sysfs handlers
+
+The dpm sensor function already does this for us.  This fixes
+the freq*_input files with the new SMU implementation.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 10 ----------
+ 1 file changed, 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index 09b4b0dc94ab..481658a92ee7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -2074,11 +2074,6 @@ static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
+ 	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+ 		return -EINVAL;
+ 
+-	/* sanity check PP is enabled */
+-	if (!(adev->powerplay.pp_funcs &&
+-	      adev->powerplay.pp_funcs->read_sensor))
+-	      return -EINVAL;
+-
+ 	/* get the sclk */
+ 	r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
+ 				   (void *)&sclk, &size);
+@@ -2109,11 +2104,6 @@ static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
+ 	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+ 		return -EINVAL;
+ 
+-	/* sanity check PP is enabled */
+-	if (!(adev->powerplay.pp_funcs &&
+-	      adev->powerplay.pp_funcs->read_sensor))
+-	      return -EINVAL;
+-
+ 	/* get the sclk */
+ 	r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
+ 				   (void *)&mclk, &size);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3099-drm-amd-display-Force-uclk-to-max-for-every-state.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3099-drm-amd-display-Force-uclk-to-max-for-every-state.patch
new file mode 100644
index 00000000..3447f3ab
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3099-drm-amd-display-Force-uclk-to-max-for-every-state.patch
@@ -0,0 +1,83 @@
+From 766ec49917d91473e96859b4b36ec64c1a1212c2 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Fri, 5 Jul 2019 16:54:28 -0400
+Subject: [PATCH 3099/4256] drm/amd/display: Force uclk to max for every state
+
+Workaround for now to avoid underflow.
+
+The uclk switch time should really be bumped up to 404, but doing so
+would expose p-state hang issues for higher bandwidth display
+configurations.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+Reviewed-by: Zhan Liu <Zhan.Liu@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c   |  6 +++---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c  | 10 ++++++++++
+ 2 files changed, 13 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+index e0f1bd32567d..7bc7abcf3db1 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+@@ -912,11 +912,11 @@ void dm_pp_get_funcs(
+ 		/* todo set_pme_wa_enable cause 4k@6ohz display not light up */
+ 		funcs->nv_funcs.set_pme_wa_enable = NULL;
+ 		/* todo debug waring message */
+-		funcs->nv_funcs.set_hard_min_uclk_by_freq = NULL;
++		funcs->nv_funcs.set_hard_min_uclk_by_freq = pp_nv_set_hard_min_uclk_by_freq;
+ 		/* todo  compare data with window driver*/
+-		funcs->nv_funcs.get_maximum_sustainable_clocks = NULL;
++		funcs->nv_funcs.get_maximum_sustainable_clocks = pp_nv_get_maximum_sustainable_clocks;
+ 		/*todo  compare data with window driver */
+-		funcs->nv_funcs.get_uclk_dpm_states = NULL;
++		funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
+ 		break;
+ #endif
+ 	default:
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 2cf788a3704e..44537651f0a1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2707,6 +2707,9 @@ static void cap_soc_clocks(
+ 						&& max_clocks.uClockInKhz != 0)
+ 			bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
+ 
++		// HACK: Force every uclk to max for now to "disable" uclk switching.
++		bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
++
+ 		if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
+ 						&& max_clocks.fabricClockInKhz != 0)
+ 			bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
+@@ -2922,6 +2925,8 @@ static bool init_soc_bounding_box(struct dc *dc,
+ 				le32_to_cpu(bb->vmm_page_size_bytes);
+ 		dcn2_0_soc.dram_clock_change_latency_us =
+ 				fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
++		// HACK!! Lower uclock latency switch time so we don't switch
++		dcn2_0_soc.dram_clock_change_latency_us = 10;
+ 		dcn2_0_soc.writeback_dram_clock_change_latency_us =
+ 				fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
+ 		dcn2_0_soc.return_bus_width_bytes =
+@@ -2963,6 +2968,7 @@ static bool init_soc_bounding_box(struct dc *dc,
+ 		struct pp_smu_nv_clock_table max_clocks = {0};
+ 		unsigned int uclk_states[8] = {0};
+ 		unsigned int num_states = 0;
++		int i;
+ 		enum pp_smu_status status;
+ 		bool clock_limits_available = false;
+ 		bool uclk_states_available = false;
+@@ -2984,6 +2990,10 @@ static bool init_soc_bounding_box(struct dc *dc,
+ 			clock_limits_available = (status == PP_SMU_RESULT_OK);
+ 		}
+ 
++		// HACK: Use the max uclk_states value for all elements.
++		for (i = 0; i < num_states; i++)
++			uclk_states[i] = uclk_states[num_states - 1];
++
+ 		if (clock_limits_available && uclk_states_available && num_states)
+ 			update_bounding_box(dc, &dcn2_0_soc, &max_clocks, uclk_states, num_states);
+ 		else if (clock_limits_available)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3100-drm-amdgpu-Remove-undefined-amdgpu_device_parse_fake.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3100-drm-amdgpu-Remove-undefined-amdgpu_device_parse_fake.patch
new file mode 100644
index 00000000..2d0d6ba3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3100-drm-amdgpu-Remove-undefined-amdgpu_device_parse_fake.patch
@@ -0,0 +1,36 @@
+From 21d45e6dc1a375d4f7f017577a1b8fa481f8c93a Mon Sep 17 00:00:00 2001
+From: Leo Li <sunpeng.li@amd.com>
+Date: Thu, 18 Jul 2019 12:05:48 -0400
+Subject: [PATCH 3100/4256] drm/amdgpu: Remove undefined
+ amdgpu_device_parse_faked_did
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This forward declare was added for no apparent reason. Remove it to
+resolve this warning:
+
+drivers/gpu/drm//amd/amdgpu/amdgpu_device.c:131:13: warning: ‘amdgpu_device_parse_faked_did’ declared ‘static’ but never defined [-Wunused-function]
+ static void amdgpu_device_parse_faked_did(struct amdgpu_device *adev);
+
+Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index aa007e9958a0..429794becdcd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -128,7 +128,6 @@ static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
+ 		amdgpu_device_get_pcie_replay_count, NULL);
+ 
+ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
+-static void amdgpu_device_parse_faked_did(struct amdgpu_device *adev);
+ 
+ /**
+  * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3101-drm-amdgpu-smu-move-fan-rpm-query-into-the-asic-spec.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3101-drm-amdgpu-smu-move-fan-rpm-query-into-the-asic-spec.patch
new file mode 100644
index 00000000..489f6e13
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3101-drm-amdgpu-smu-move-fan-rpm-query-into-the-asic-spec.patch
@@ -0,0 +1,213 @@
+From 3b90c86beb76a4670f18c7a0a3e04eb318fcfad4 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 18 Jul 2019 15:25:04 -0500
+Subject: [PATCH 3101/4256] drm/amdgpu/smu: move fan rpm query into the asic
+ specific code
+
+On vega20, there is an SMU message to query it.  On navi, it's fetched
+from the metrics table.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c        |  4 ++--
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  6 +++---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 12 ++++++-----
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 18 -----------------
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 20 ++++++++++++++++++-
+ 5 files changed, 31 insertions(+), 29 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index 481658a92ee7..8f702cf5e080 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -1731,7 +1731,7 @@ static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
+ 		return -EINVAL;
+ 
+ 	if (is_support_sw_smu(adev)) {
+-		err = smu_get_current_rpm(&adev->smu, &speed);
++		err = smu_get_fan_speed_rpm(&adev->smu, &speed);
+ 		if (err)
+ 			return err;
+ 	} else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
+@@ -1791,7 +1791,7 @@ static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
+ 		return -EINVAL;
+ 
+ 	if (is_support_sw_smu(adev)) {
+-		err = smu_get_current_rpm(&adev->smu, &rpm);
++		err = smu_get_fan_speed_rpm(&adev->smu, &rpm);
+ 		if (err)
+ 			return err;
+ 	} else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 34093ddca105..b702c9ee975f 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -623,6 +623,7 @@ struct pptable_funcs {
+ 	int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
+ 	int (*set_thermal_fan_table)(struct smu_context *smu);
+ 	int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
++	int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
+ 	int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,
+ 				    struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
+ 	int (*get_current_clk_freq_by_table)(struct smu_context *smu,
+@@ -696,7 +697,6 @@ struct smu_funcs
+ 	int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
+ 					       struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
+ 	int (*conv_power_profile_to_pplib_workload)(int power_profile);
+-	int (*get_current_rpm)(struct smu_context *smu, uint32_t *speed);
+ 	uint32_t (*get_fan_control_mode)(struct smu_context *smu);
+ 	int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
+ 	int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
+@@ -762,8 +762,6 @@ struct smu_funcs
+ 	((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
+ #define smu_set_default_od_settings(smu, initialize) \
+ 	((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
+-#define smu_get_current_rpm(smu, speed) \
+-	((smu)->funcs->get_current_rpm ? (smu)->funcs->get_current_rpm((smu), (speed)) : 0)
+ #define smu_set_fan_speed_rpm(smu, speed) \
+ 	((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs->set_fan_speed_rpm((smu), (speed)) : 0)
+ #define smu_send_smc_msg(smu, msg) \
+@@ -852,6 +850,8 @@ struct smu_funcs
+ 	((smu)->ppt_funcs->get_fan_speed_percent ? (smu)->ppt_funcs->get_fan_speed_percent((smu), (speed)) : 0)
+ #define smu_set_fan_speed_percent(smu, speed) \
+ 	((smu)->funcs->set_fan_speed_percent ? (smu)->funcs->set_fan_speed_percent((smu), (speed)) : 0)
++#define smu_get_fan_speed_rpm(smu, speed) \
++	((smu)->ppt_funcs->get_fan_speed_rpm ? (smu)->ppt_funcs->get_fan_speed_rpm((smu), (speed)) : 0)
+ 
+ #define smu_msg_get_index(smu, msg) \
+ 	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 46e2913e4af4..c8ce9bbae276 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -968,12 +968,13 @@ static bool navi10_is_dpm_running(struct smu_context *smu)
+ 	return !!(feature_enabled & SMC_DPM_FEATURE);
+ }
+ 
+-static int navi10_get_fan_speed(struct smu_context *smu, uint16_t *value)
++static int navi10_get_fan_speed_rpm(struct smu_context *smu,
++				    uint32_t *speed)
+ {
+ 	SmuMetrics_t metrics;
+ 	int ret = 0;
+ 
+-	if (!value)
++	if (!speed)
+ 		return -EINVAL;
+ 
+ 	memset(&metrics, 0, sizeof(metrics));
+@@ -983,7 +984,7 @@ static int navi10_get_fan_speed(struct smu_context *smu, uint16_t *value)
+ 	if (ret)
+ 		return ret;
+ 
+-	*value = metrics.CurrFanSpeed;
++	*speed = metrics.CurrFanSpeed;
+ 
+ 	return ret;
+ }
+@@ -993,10 +994,10 @@ static int navi10_get_fan_speed_percent(struct smu_context *smu,
+ {
+ 	int ret = 0;
+ 	uint32_t percent = 0;
+-	uint16_t current_rpm;
++	uint32_t current_rpm;
+ 	PPTable_t *pptable = smu->smu_table.driver_pptable;
+ 
+-	ret = navi10_get_fan_speed(smu, &current_rpm);
++	ret = navi10_get_fan_speed_rpm(smu, &current_rpm);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -1665,6 +1666,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.unforce_dpm_levels = navi10_unforce_dpm_levels,
+ 	.is_dpm_running = navi10_is_dpm_running,
+ 	.get_fan_speed_percent = navi10_get_fan_speed_percent,
++	.get_fan_speed_rpm = navi10_get_fan_speed_rpm,
+ 	.get_power_profile_mode = navi10_get_power_profile_mode,
+ 	.set_power_profile_mode = navi10_set_power_profile_mode,
+ 	.get_profiling_clk_mask = navi10_get_profiling_clk_mask,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 76bc157525d0..e3a178403546 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1402,23 +1402,6 @@ static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_get_current_rpm(struct smu_context *smu,
+-				     uint32_t *current_rpm)
+-{
+-	int ret;
+-
+-	ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
+-
+-	if (ret) {
+-		pr_err("Attempt to get current RPM from SMC Failed!\n");
+-		return ret;
+-	}
+-
+-	smu_read_smc_arg(smu, current_rpm);
+-
+-	return 0;
+-}
+-
+ static uint32_t
+ smu_v11_0_get_fan_control_mode(struct smu_context *smu)
+ {
+@@ -1803,7 +1786,6 @@ static const struct smu_funcs smu_v11_0_funcs = {
+ 	.set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
+ 	.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
+ 	.set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
+-	.get_current_rpm = smu_v11_0_get_current_rpm,
+ 	.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
+ 	.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
+ 	.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index bcd0efaf7bbd..9ead36192787 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -3033,6 +3033,23 @@ static int vega20_set_thermal_fan_table(struct smu_context *smu)
+ 	return ret;
+ }
+ 
++static int vega20_get_fan_speed_rpm(struct smu_context *smu,
++				    uint32_t *speed)
++{
++	int ret;
++
++	ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
++
++	if (ret) {
++		pr_err("Attempt to get current RPM from SMC Failed!\n");
++		return ret;
++	}
++
++	smu_read_smc_arg(smu, speed);
++
++	return 0;
++}
++
+ static int vega20_get_fan_speed_percent(struct smu_context *smu,
+ 					uint32_t *speed)
+ {
+@@ -3040,7 +3057,7 @@ static int vega20_get_fan_speed_percent(struct smu_context *smu,
+ 	uint32_t current_rpm = 0, percent = 0;
+ 	PPTable_t *pptable = smu->smu_table.driver_pptable;
+ 
+-	ret = smu_get_current_rpm(smu, &current_rpm);
++	ret = vega20_get_fan_speed_rpm(smu, &current_rpm);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -3311,6 +3328,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
+ 	.is_dpm_running = vega20_is_dpm_running,
+ 	.set_thermal_fan_table = vega20_set_thermal_fan_table,
+ 	.get_fan_speed_percent = vega20_get_fan_speed_percent,
++	.get_fan_speed_rpm = vega20_get_fan_speed_rpm,
+ 	.set_watermarks_table = vega20_set_watermarks_table,
+ 	.get_thermal_temperature_range = vega20_get_thermal_temperature_range
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3102-drm-amdkfd-Fix-sdma_bitmap-overflow-issue.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3102-drm-amdkfd-Fix-sdma_bitmap-overflow-issue.patch
new file mode 100644
index 00000000..cef3590a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3102-drm-amdkfd-Fix-sdma_bitmap-overflow-issue.patch
@@ -0,0 +1,45 @@
+From 84dd0558b395698b7a005725892d5ec88d69f299 Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Tue, 9 Jul 2019 09:40:15 -0500
+Subject: [PATCH 3102/4256] drm/amdkfd: Fix sdma_bitmap overflow issue
+
+In the original formula, when sdma queue number is 64,
+the left shift overflows. Use an equivalence that won't
+overflow.
+
+Change-Id: Ibf55a1bcaee32a098147ac76a7a11ac5808d2c75
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 471519f5f3f2..d8418e6bec86 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -962,8 +962,8 @@ static int initialize_nocpsch(struct device_queue_manager *dqm)
+   }
+ 
+   dqm->vmid_bitmap = (1 << dqm->dev->vm_info.vmid_num_kfd) - 1;
+-  dqm->sdma_bitmap = (1ULL << get_num_sdma_queues(dqm)) - 1;
+-  dqm->xgmi_sdma_bitmap = (1ULL << get_num_xgmi_sdma_queues(dqm)) - 1;
++  dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
++  dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
+ 
+   return 0;
+ }
+@@ -1101,8 +1101,8 @@ static int initialize_cpsch(struct device_queue_manager *dqm)
+   dqm->sdma_queue_count = 0;
+   dqm->xgmi_sdma_queue_count = 0;
+   dqm->active_runlist = false;
+-  dqm->sdma_bitmap = (1ULL << get_num_sdma_queues(dqm)) - 1;
+-  dqm->xgmi_sdma_bitmap = (1ULL << get_num_xgmi_sdma_queues(dqm)) - 1;
++  dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
++  dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
+   dqm->trap_debug_vmid = 0;
+ 
+   INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3103-drm-amdkfd-Fix-missing-break-in-switch-statement.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3103-drm-amdkfd-Fix-missing-break-in-switch-statement.patch
new file mode 100644
index 00000000..24890f20
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3103-drm-amdkfd-Fix-missing-break-in-switch-statement.patch
@@ -0,0 +1,34 @@
+From f0d86e35f87513e2c370abc1134b6f9f2e074154 Mon Sep 17 00:00:00 2001
+From: "Gustavo A. R. Silva" <gustavo@embeddedor.com>
+Date: Sun, 21 Jul 2019 16:49:35 -0500
+Subject: [PATCH 3103/4256] drm/amdkfd: Fix missing break in switch statement
+
+Add missing break statement in order to prevent the code from falling
+through to case CHIP_NAVI10.
+
+This bug was found thanks to the ongoing efforts to enable
+-Wimplicit-fallthrough.
+
+Fixes: 14328aa58ce5 ("drm/amdkfd: Add navi10 support to amdkfd. (v3)")
+Cc: stable@vger.kernel.org
+Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+index a59253a31caf..4d6427440758 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+@@ -669,6 +669,7 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
+ 	case CHIP_RAVEN:
+ 		pcache_info = raven_cache_info;
+ 		num_of_cache_types = ARRAY_SIZE(raven_cache_info);
++		break;
+ 	case CHIP_NAVI10:
+ 		pcache_info = navi10_cache_info;
+ 		num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3104-drm-amdgpu-gfx10-Fix-missing-break-in-switch-stateme.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3104-drm-amdgpu-gfx10-Fix-missing-break-in-switch-stateme.patch
new file mode 100644
index 00000000..fe965d5b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3104-drm-amdgpu-gfx10-Fix-missing-break-in-switch-stateme.patch
@@ -0,0 +1,35 @@
+From 603aa5c4366ed8616c938c040f8a41de868bb85b Mon Sep 17 00:00:00 2001
+From: "Gustavo A. R. Silva" <gustavo@embeddedor.com>
+Date: Sun, 21 Jul 2019 17:39:49 -0500
+Subject: [PATCH 3104/4256] drm/amdgpu/gfx10: Fix missing break in switch
+ statement
+
+Add missing break statement in order to prevent the code from falling
+through to case AMDGPU_IRQ_STATE_ENABLE.
+
+This bug was found thanks to the ongoing efforts to enable
+-Wimplicit-fallthrough.
+
+Fixes: a644d85a5cd4 ("drm/amdgpu: add gfx v10 implementation (v10)")
+Cc: stable@vger.kernel.org
+Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index ed48dc5fe36a..23ed5b2dae19 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -4678,6 +4678,7 @@ gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
+ 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
+ 					    TIME_STAMP_INT_ENABLE, 0);
+ 		WREG32(cp_int_cntl_reg, cp_int_cntl);
++		break;
+ 	case AMDGPU_IRQ_STATE_ENABLE:
+ 		cp_int_cntl = RREG32(cp_int_cntl_reg);
+ 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3105-drm-amdkfd-kfd_mqd_manager_v10-Avoid-fall-through-wa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3105-drm-amdkfd-kfd_mqd_manager_v10-Avoid-fall-through-wa.patch
new file mode 100644
index 00000000..f4953dec
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3105-drm-amdkfd-kfd_mqd_manager_v10-Avoid-fall-through-wa.patch
@@ -0,0 +1,63 @@
+From d5098f7379f888812a7260397504fcaf13929e25 Mon Sep 17 00:00:00 2001
+From: "Gustavo A. R. Silva" <gustavo@embeddedor.com>
+Date: Mon, 22 Jul 2019 12:47:16 -0500
+Subject: [PATCH 3105/4256] drm/amdkfd/kfd_mqd_manager_v10: Avoid fall-through
+ warning
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+In preparation to enabling -Wimplicit-fallthrough, this patch silences
+the following warning:
+
+drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v10.c: In function ‘mqd_manager_init_v10’:
+./include/linux/dynamic_debug.h:122:52: warning: this statement may fall through [-Wimplicit-fallthrough=]
+ #define __dynamic_func_call(id, fmt, func, ...) do { \
+                                                    ^
+./include/linux/dynamic_debug.h:143:2: note: in expansion of macro ‘__dynamic_func_call’
+  __dynamic_func_call(__UNIQUE_ID(ddebug), fmt, func, ##__VA_ARGS__)
+  ^~~~~~~~~~~~~~~~~~~
+./include/linux/dynamic_debug.h:153:2: note: in expansion of macro ‘_dynamic_func_call’
+  _dynamic_func_call(fmt, __dynamic_pr_debug,  \
+  ^~~~~~~~~~~~~~~~~~
+./include/linux/printk.h:336:2: note: in expansion of macro ‘dynamic_pr_debug’
+  dynamic_pr_debug(fmt, ##__VA_ARGS__)
+  ^~~~~~~~~~~~~~~~
+drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v10.c:432:3: note: in expansion of macro ‘pr_debug’
+   pr_debug("%s@%i\n", __func__, __LINE__);
+   ^~~~~~~~
+drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v10.c:433:2: note: here
+  case KFD_MQD_TYPE_COMPUTE:
+  ^~~~
+
+by removing the call to pr_debug() in KFD_MQD_TYPE_CP:
+
+"The mqd init for CP and COMPUTE will have the same  routine." [1]
+
+This bug was found thanks to the ongoing efforts to enable
+-Wimplicit-fallthrough.
+
+[1] https://lore.kernel.org/lkml/c735a1cc-a545-50fb-44e7-c0ad93ee8ee7@amd.com/
+
+Reviewed-by:  shaoyunl <shaoyun.liu@amd.com>
+Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index 0b68a17eb902..29d50d6af9d7 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -429,7 +429,6 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+ 
+ 	switch (type) {
+ 	case KFD_MQD_TYPE_CP:
+-		pr_debug("%s@%i\n", __func__, __LINE__);
+ 	case KFD_MQD_TYPE_COMPUTE:
+ 		pr_debug("%s@%i\n", __func__, __LINE__);
+ 		mqd->allocate_mqd = allocate_mqd;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3106-drm-amd-powerplay-add-callback-function-of-get_therm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3106-drm-amd-powerplay-add-callback-function-of-get_therm.patch
new file mode 100644
index 00000000..3fa6acc2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3106-drm-amd-powerplay-add-callback-function-of-get_therm.patch
@@ -0,0 +1,189 @@
+From 3dac7803ad99655bee5c4b321cbc97cc9e8727ee Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Mon, 3 Jun 2019 15:58:31 +0800
+Subject: [PATCH 3106/4256] drm/amd/powerplay: add callback function of
+ get_thermal_temperature_range
+
+1. the thermal temperature is asic related data, move the code logic to
+xxx_ppt.c.
+2. replace data structure PP_TemperatureRange with
+smu_temperature_range.
+3. change temperature uint from temp*1000 to temp (temperature uint).
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
+Acked-by: Huang Rui <ray.huang@amd.com>
+---
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  1 -
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 17 ++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 18 ++++++----
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 34 ++++++-------------
+ 4 files changed, 40 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index b702c9ee975f..33d2d75ba903 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -439,7 +439,6 @@ struct smu_table_context
+ 	struct smu_table		*tables;
+ 	uint32_t			table_count;
+ 	struct smu_table		memory_pool;
+-	uint16_t                        software_shutdown_temp;
+ 	uint8_t                         thermal_controller_type;
+ 	uint16_t			TDPODLimit;
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index c8ce9bbae276..c873228bf05f 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1639,6 +1639,22 @@ static int navi10_set_performance_level(struct smu_context *smu, enum amd_dpm_fo
+ 	return ret;
+ }
+ 
++static int navi10_get_thermal_temperature_range(struct smu_context *smu,
++						struct smu_temperature_range *range)
++{
++	struct smu_table_context *table_context = &smu->smu_table;
++	struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
++
++	if (!range || !powerplay_table)
++		return -EINVAL;
++
++	/* The unit is temperature */
++	range->min = 0;
++	range->max = powerplay_table->software_shutdown_temp;
++
++	return 0;
++}
++
+ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.tables_init = navi10_tables_init,
+ 	.alloc_dpm_context = navi10_allocate_dpm_context,
+@@ -1676,6 +1692,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.get_ppfeature_status = navi10_get_ppfeature_status,
+ 	.set_ppfeature_status = navi10_set_ppfeature_status,
+ 	.set_performance_level = navi10_set_performance_level,
++	.get_thermal_temperature_range = navi10_get_thermal_temperature_range,
+ };
+ 
+ void navi10_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index e3a178403546..745b35a1600d 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1147,10 +1147,8 @@ static int smu_v11_0_set_thermal_range(struct smu_context *smu,
+ 				       struct smu_temperature_range *range)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+-	int low = SMU_THERMAL_MINIMUM_ALERT_TEMP *
+-		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+-	int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP *
+-		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
++	int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
+ 	uint32_t val;
+ 
+ 	if (!range)
+@@ -1161,6 +1159,9 @@ static int smu_v11_0_set_thermal_range(struct smu_context *smu,
+ 	if (high > range->max)
+ 		high = range->max;
+ 
++	low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, range->min);
++	high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, range->max);
++
+ 	if (low > high)
+ 		return -EINVAL;
+ 
+@@ -1169,8 +1170,8 @@ static int smu_v11_0_set_thermal_range(struct smu_context *smu,
+ 	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
+ 	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
+ 	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
+-	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES));
+-	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES));
++	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
++	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
+ 	val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
+ 
+ 	WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
+@@ -1209,7 +1210,10 @@ static int smu_v11_0_start_thermal_control(struct smu_context *smu)
+ 
+ 	if (!smu->pm_enabled)
+ 		return ret;
++
+ 	ret = smu_get_thermal_temperature_range(smu, &range);
++	if (ret)
++		return ret;
+ 
+ 	if (smu->smu_table.thermal_controller_type) {
+ 		ret = smu_v11_0_set_thermal_range(smu, &range);
+@@ -1234,6 +1238,8 @@ static int smu_v11_0_start_thermal_control(struct smu_context *smu)
+ 	adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
+ 	adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
+ 	adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
++	adev->pm.dpm.thermal.min_temp = range.min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	adev->pm.dpm.thermal.max_temp = range.max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ 
+ 	return ret;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 9ead36192787..c06a9472c3b2 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -463,7 +463,6 @@ static int vega20_store_powerplay_table(struct smu_context *smu)
+ 	memcpy(table_context->driver_pptable, &powerplay_table->smcPPTable,
+ 	       sizeof(PPTable_t));
+ 
+-	table_context->software_shutdown_temp = powerplay_table->usSoftwareShutdownTemp;
+ 	table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
+ 	table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
+ 
+@@ -3252,35 +3251,24 @@ static int vega20_set_watermarks_table(struct smu_context *smu,
+ 	return 0;
+ }
+ 
+-static const struct smu_temperature_range vega20_thermal_policy[] =
+-{
+-	{-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
+-	{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
+-};
+-
+ static int vega20_get_thermal_temperature_range(struct smu_context *smu,
+ 						struct smu_temperature_range*range)
+ {
+-
++	struct smu_table_context *table_context = &smu->smu_table;
++	ATOM_Vega20_POWERPLAYTABLE *powerplay_table = table_context->power_play_table;
+ 	PPTable_t *pptable = smu->smu_table.driver_pptable;
+ 
+-	if (!range)
++	if (!range || !powerplay_table)
+ 		return -EINVAL;
+ 
+-	memcpy(range, &vega20_thermal_policy[0], sizeof(struct smu_temperature_range));
+-
+-	range->max = pptable->TedgeLimit *
+-		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+-	range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
+-		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+-	range->hotspot_crit_max = pptable->ThotspotLimit *
+-		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+-	range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
+-		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+-	range->mem_crit_max = pptable->ThbmLimit *
+-		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+-	range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM)*
+-		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	/* The unit is temperature */
++	range->min = 0;
++	range->max = powerplay_table->usSoftwareShutdownTemp;
++	range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE);
++	range->hotspot_crit_max = pptable->ThotspotLimit;
++	range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT);
++	range->mem_crit_max = pptable->ThbmLimit;
++	range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM);
+ 
+ 
+ 	return 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3107-drm-amdkfd-Fix-byte-align-on-VegaM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3107-drm-amdkfd-Fix-byte-align-on-VegaM.patch
new file mode 100644
index 00000000..0fb86b93
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3107-drm-amdkfd-Fix-byte-align-on-VegaM.patch
@@ -0,0 +1,30 @@
+From e3dbace764edff9200901cbb11dab3afbc53c14f Mon Sep 17 00:00:00 2001
+From: Kent Russell <kent.russell@amd.com>
+Date: Tue, 23 Jul 2019 10:18:01 -0400
+Subject: [PATCH 3107/4256] drm/amdkfd: Fix byte align on VegaM
+
+This was missed during the addition of VegaM support
+
+Change-Id: I61c8fbbea77338126e3ebdfa74c286b665bdd670
+Signed-off-by: Kent Russell <kent.russell@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index 2cae9d1d26ac..d144d04d7b0e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -1206,7 +1206,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
+ 			adev->asic_type != CHIP_FIJI &&
+ 			adev->asic_type != CHIP_POLARIS10 &&
+ 			adev->asic_type != CHIP_POLARIS11 &&
+-			adev->asic_type != CHIP_POLARIS12) ?
++			adev->asic_type != CHIP_POLARIS12 &&
++			adev->asic_type != CHIP_VEGAM) ?
+ 			VI_BO_SIZE_ALIGN : 1;
+ 
+ 	mapping_flags = AMDGPU_VM_PAGE_READABLE;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3108-drm-amd-display-readd-msse2-to-prevent-Clang-from-em.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3108-drm-amd-display-readd-msse2-to-prevent-Clang-from-em.patch
new file mode 100644
index 00000000..bb3b2922
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3108-drm-amd-display-readd-msse2-to-prevent-Clang-from-em.patch
@@ -0,0 +1,95 @@
+From 564dc5dcb5b92e0ee99009e84cdf26855296f694 Mon Sep 17 00:00:00 2001
+From: Nick Desaulniers <ndesaulniers@google.com>
+Date: Mon, 22 Jul 2019 15:31:05 -0700
+Subject: [PATCH 3108/4256] drm/amd/display: readd -msse2 to prevent Clang from
+ emitting libcalls to undefined SW FP routines
+
+arch/x86/Makefile disables SSE and SSE2 for the whole kernel.  The
+AMDGPU drivers modified in this patch re-enable SSE but not SSE2.  Turn
+on SSE2 to support emitting double precision floating point instructions
+rather than calls to non-existent (usually available from gcc_s or
+compiler_rt) floating point helper routines for Clang.
+
+This was originally landed in:
+commit 10117450735c ("drm/amd/display: add -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines")
+but reverted in:
+commit 193392ed9f69 ("Revert "drm/amd/display: add -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines"")
+due to bugreports from GCC builds. Add guards to only do so for Clang.
+
+Link: https://bugs.freedesktop.org/show_bug.cgi?id=109487
+Link: https://github.com/ClangBuiltLinux/linux/issues/327
+
+Suggested-by: Sedat Dilek <sedat.dilek@gmail.com>
+Suggested-by: Sami Tolvanen <samitolvanen@google.com>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/calcs/Makefile | 4 ++++
+ drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 4 ++++
+ drivers/gpu/drm/amd/display/dc/dml/Makefile   | 4 ++++
+ drivers/gpu/drm/amd/display/dc/dsc/Makefile   | 4 ++++
+ 4 files changed, 16 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+index 95f332ee3e7e..16614d73a5fc 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+@@ -32,6 +32,10 @@ endif
+ 
+ calcs_ccflags := -mhard-float -msse $(cc_stack_align)
+ 
++ifdef CONFIG_CC_IS_CLANG
++calcs_ccflags += -msse2
++endif
++
+ CFLAGS_dcn_calcs.o := $(calcs_ccflags)
+ CFLAGS_dcn_calc_auto.o := $(calcs_ccflags)
+ CFLAGS_dcn_calc_math.o := $(calcs_ccflags) -Wno-tautological-compare
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+index e9721a906592..f57a3b281408 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+@@ -18,6 +18,10 @@ endif
+ 
+ CFLAGS_dcn20_resource.o := -mhard-float -msse $(cc_stack_align)
+ 
++ifdef CONFIG_CC_IS_CLANG
++CFLAGS_dcn20_resource.o += -msse2
++endif
++
+ AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20))
+ 
+ AMD_DISPLAY_FILES += $(AMD_DAL_DCN20)
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+index 1735fc1e2eb1..95fd2beca80c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+@@ -32,6 +32,10 @@ endif
+ 
+ dml_ccflags := -mhard-float -msse $(cc_stack_align)
+ 
++ifdef CONFIG_CC_IS_CLANG
++dml_ccflags += -msse2
++endif
++
+ CFLAGS_display_mode_lib.o := $(dml_ccflags)
+ 
+ ifdef CONFIG_DRM_AMD_DC_DCN2_0
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+index e019cd9447e8..17db603f2d1f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+@@ -9,6 +9,10 @@ endif
+ 
+ dsc_ccflags := -mhard-float -msse $(cc_stack_align)
+ 
++ifdef CONFIG_CC_IS_CLANG
++dsc_ccflags += -msse2
++endif
++
+ CFLAGS_rc_calc.o := $(dsc_ccflags)
+ CFLAGS_rc_calc_dpi.o := $(dsc_ccflags)
+ CFLAGS_codec_main_amd.o := $(dsc_ccflags)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3109-drm-amdgpu-Use-dev_get_drvdata-where-possible.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3109-drm-amdgpu-Use-dev_get_drvdata-where-possible.patch
new file mode 100644
index 00000000..7ccb8c65
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3109-drm-amdgpu-Use-dev_get_drvdata-where-possible.patch
@@ -0,0 +1,88 @@
+From 6b00ff9d6424c84f567814e7fffa6b29c91a084a Mon Sep 17 00:00:00 2001
+From: Chuhong Yuan <hslester96@gmail.com>
+Date: Tue, 23 Jul 2019 17:04:50 +0800
+Subject: [PATCH 3109/4256] drm/amdgpu: Use dev_get_drvdata where possible
+
+Instead of using to_pci_dev + pci_get_drvdata,
+use dev_get_drvdata to make code simpler.
+
+Signed-off-by: Chuhong Yuan <hslester96@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 21 +++++++--------------
+ 1 file changed, 7 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index e7c6f9b6e4ba..1d72e2e784d0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1136,16 +1136,14 @@ amdgpu_pci_shutdown(struct pci_dev *pdev)
+ 
+ static int amdgpu_pmops_suspend(struct device *dev)
+ {
+-	struct pci_dev *pdev = to_pci_dev(dev);
++	struct drm_device *drm_dev = dev_get_drvdata(dev);
+ 
+-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
+ 	return amdgpu_device_suspend(drm_dev, true, true);
+ }
+ 
+ static int amdgpu_pmops_resume(struct device *dev)
+ {
+-	struct pci_dev *pdev = to_pci_dev(dev);
+-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
++	struct drm_device *drm_dev = dev_get_drvdata(dev);
+ 
+ 	/* GPU comes up enabled by the bios on resume */
+ 	if (amdgpu_device_is_px(drm_dev)) {
+@@ -1159,33 +1157,29 @@ static int amdgpu_pmops_resume(struct device *dev)
+ 
+ static int amdgpu_pmops_freeze(struct device *dev)
+ {
+-	struct pci_dev *pdev = to_pci_dev(dev);
++	struct drm_device *drm_dev = dev_get_drvdata(dev);
+ 
+-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
+ 	return amdgpu_device_suspend(drm_dev, false, true);
+ }
+ 
+ static int amdgpu_pmops_thaw(struct device *dev)
+ {
+-	struct pci_dev *pdev = to_pci_dev(dev);
++	struct drm_device *drm_dev = dev_get_drvdata(dev);
+ 
+-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
+ 	return amdgpu_device_resume(drm_dev, false, true);
+ }
+ 
+ static int amdgpu_pmops_poweroff(struct device *dev)
+ {
+-	struct pci_dev *pdev = to_pci_dev(dev);
++	struct drm_device *drm_dev = dev_get_drvdata(dev);
+ 
+-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
+ 	return amdgpu_device_suspend(drm_dev, true, true);
+ }
+ 
+ static int amdgpu_pmops_restore(struct device *dev)
+ {
+-	struct pci_dev *pdev = to_pci_dev(dev);
++	struct drm_device *drm_dev = dev_get_drvdata(dev);
+ 
+-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
+ 	return amdgpu_device_resume(drm_dev, false, true);
+ }
+ 
+@@ -1244,8 +1238,7 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
+ 
+ static int amdgpu_pmops_runtime_idle(struct device *dev)
+ {
+-	struct pci_dev *pdev = to_pci_dev(dev);
+-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
++	struct drm_device *drm_dev = dev_get_drvdata(dev);
+ 	struct drm_crtc *crtc;
+ 
+ 	if (!amdgpu_device_is_px(drm_dev)) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3110-drm-amd-display-Use-dev_get_drvdata.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3110-drm-amd-display-Use-dev_get_drvdata.patch
new file mode 100644
index 00000000..b20ff0bd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3110-drm-amd-display-Use-dev_get_drvdata.patch
@@ -0,0 +1,31 @@
+From 205d55e83236d5caea150c875add840a5bd56b66 Mon Sep 17 00:00:00 2001
+From: Chuhong Yuan <hslester96@gmail.com>
+Date: Tue, 23 Jul 2019 17:04:22 +0800
+Subject: [PATCH 3110/4256] drm/amd/display: Use dev_get_drvdata
+
+Instead of using to_pci_dev + pci_get_drvdata,
+use dev_get_drvdata to make code simpler.
+
+Signed-off-by: Chuhong Yuan <hslester96@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 33150eb3c135..8d55650cb622 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -2513,8 +2513,7 @@ static ssize_t s3_debug_store(struct device *device,
+ {
+ 	int ret;
+ 	int s3_state;
+-	struct pci_dev *pdev = to_pci_dev(device);
+-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
++	struct drm_device *drm_dev = dev_get_drvdata(device);
+ 	struct amdgpu_device *adev = drm_dev->dev_private;
+ 
+ 	ret = kstrtoint(buf, 0, &s3_state);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3111-drm-amd-display-fix-a-missing-null-check-on-a-failed.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3111-drm-amd-display-fix-a-missing-null-check-on-a-failed.patch
new file mode 100644
index 00000000..e6da9b89
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3111-drm-amd-display-fix-a-missing-null-check-on-a-failed.patch
@@ -0,0 +1,34 @@
+From d059da84f0dee9afb90dd6b5f6c41611ac480c23 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Tue, 23 Jul 2019 15:23:12 +0100
+Subject: [PATCH 3111/4256] drm/amd/display: fix a missing null check on a
+ failed kzalloc
+
+Currently the allocation of config may fail and a null pointer
+dereference on config can occur.  Fix this by added a null
+check on a failed allocation of config.
+
+Addresses-Coverity: ("Dereference null return")
+Fixes: c2cd9d04ecf0 ("drm/amd/display: Hook up calls to do stereo mux and dig programming to stereo control interface")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index ecf562e386cb..bc48e8e6ce4d 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1269,6 +1269,8 @@ bool dc_set_generic_gpio_for_stereo(bool enable,
+ 	struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
+ 			   GFP_KERNEL);
+ 
++	if (!config)
++		return false;
+ 	pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
+ 
+ 	if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3112-amd-amdgpu-Enable-debug-vmid-trap-mask.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3112-amd-amdgpu-Enable-debug-vmid-trap-mask.patch
new file mode 100644
index 00000000..cfda20e6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3112-amd-amdgpu-Enable-debug-vmid-trap-mask.patch
@@ -0,0 +1,81 @@
+From f87a9b09dff509976836971a0372a715864f3cc8 Mon Sep 17 00:00:00 2001
+From: Philip Cox <Philip.Cox@amd.com>
+Date: Tue, 16 Jul 2019 09:39:44 -0400
+Subject: [PATCH 3112/4256] amd/amdgpu: Enable debug vmid trap mask
+
+To always have wave state info available for the debugger, we enable
+the debug trap mask always for vg10 asics.
+
+Change-Id: Ic8d50c39ecbc70b031f8c199c1bcae78674a4edf
+Signed-off-by: Philip Cox <Philip.Cox@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c |  9 ---------
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c             | 11 +++++++++++
+ 2 files changed, 11 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+index 35f845a6b1c3..c98b57a5e9b2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+@@ -869,13 +869,6 @@ static uint32_t kgd_enable_debug_trap(struct kgd_dev *kgd,
+ 	data = 0;
+ 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data);
+ 
+-	data = 0;
+-	data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
+-		VMID_SEL, 1<<vmid);
+-	data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
+-		TRAP_EN, 1);
+-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
+-
+ 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), orig_stall_vmid);
+ 
+ 	mutex_unlock(&adev->grbm_idx_mutex);
+@@ -889,8 +882,6 @@ static uint32_t kgd_disable_debug_trap(struct kgd_dev *kgd)
+ 
+ 	mutex_lock(&adev->grbm_idx_mutex);
+ 
+-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), 0);
+-
+ 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
+ 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 6fa433ff6043..45d5919b0cd5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -2003,6 +2003,8 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
+ 	int i;
+ 	uint32_t sh_mem_config;
+ 	uint32_t sh_mem_bases;
++	uint32_t trap_config_vmid_mask = 0;
++	uint32_t data;
+ 
+ 	/*
+ 	 * Configure apertures:
+@@ -2022,6 +2024,9 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
+ 		/* CP and shaders */
+ 		WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
+ 		WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
++
++		/* Calculate trap config vmid mask */
++		trap_config_vmid_mask |= (1 << i);
+ 	}
+ 	soc15_grbm_select(adev, 0, 0, 0, 0);
+ 	mutex_unlock(&adev->srbm_mutex);
+@@ -2034,6 +2039,12 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
+ 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
+ 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
+ 	}
++	data = 0;
++	data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
++			VMID_SEL, trap_config_vmid_mask);
++	data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
++			TRAP_EN, 1);
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
+ }
+ 
+ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3113-drm-amdgpu-use-VCN-firmware-offset-for-cache-window.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3113-drm-amdgpu-use-VCN-firmware-offset-for-cache-window.patch
new file mode 100644
index 00000000..22f33bfd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3113-drm-amdgpu-use-VCN-firmware-offset-for-cache-window.patch
@@ -0,0 +1,35 @@
+From f4da538be90988a0aa63fb4746a6de7b881f6159 Mon Sep 17 00:00:00 2001
+From: James Zhu <James.Zhu@amd.com>
+Date: Tue, 23 Jul 2019 16:45:19 -0400
+Subject: [PATCH 3113/4256] drm/amdgpu: use VCN firmware offset for cache
+ window
+
+Since we are using the signed FW now, and also using PSP firmware loading,
+but it's still potential to break driver when loading FW directly
+instead of PSP, so we should add offset.
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Reviewed-by: Leo Liu <leo.liu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index ef8bb67844be..0c84dbc6a62d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -396,11 +396,8 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
+ 			WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+ 				upper_32_bits(adev->vcn.inst[i].gpu_addr));
+ 			offset = size;
+-			/* No signed header for now from firmware
+ 			WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
+ 				AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
+-			*/
+-			WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
+ 		}
+ 		WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3114-drm-amd-powerplay-no-pptable-transfer-and-dpms-enabl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3114-drm-amd-powerplay-no-pptable-transfer-and-dpms-enabl.patch
new file mode 100644
index 00000000..2609d8c3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3114-drm-amd-powerplay-no-pptable-transfer-and-dpms-enabl.patch
@@ -0,0 +1,34 @@
+From 840b2107a5557d8bbf7e2e53a3cba82f7b9e9162 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 23 Jul 2019 14:27:20 +0800
+Subject: [PATCH 3114/4256] drm/amd/powerplay: no pptable transfer and dpms
+ enabled with "dpm=0"
+
+Honor the 'dpm' module parameter setting on SW SMU routine as what
+we did on previous ASICs. SMU FW loading is still proceeded even
+with "dpm=0".
+
+Change-Id: I4e2bd434035c315391d0c0cbabb6ac8c6f23f239
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 416f9a837fa8..1d2d17aad861 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1083,6 +1083,9 @@ static int smu_hw_init(void *handle)
+ 		}
+ 	}
+ 
++	if (!smu->pm_enabled)
++		return 0;
++
+ 	ret = smu_feature_init_dpm(smu);
+ 	if (ret)
+ 		goto failed;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3115-drm-amd-powerplay-some-cosmetic-fixes.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3115-drm-amd-powerplay-some-cosmetic-fixes.patch
new file mode 100644
index 00000000..0c0bb0c7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3115-drm-amd-powerplay-some-cosmetic-fixes.patch
@@ -0,0 +1,142 @@
+From e77ef0f17df1e619e2238d5d9a9301ca7efd9a85 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 23 Jul 2019 16:23:28 +0800
+Subject: [PATCH 3115/4256] drm/amd/powerplay: some cosmetic fixes
+
+Drop redundant check, duplicate check, duplicate setting
+and fix the return value.
+
+Change-Id: I04171bcac82f17152371d05e6958d4fc072c0f6b
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c     | 33 +++++++++++-----------
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 30 ++++++++------------
+ 2 files changed, 28 insertions(+), 35 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index 8f702cf5e080..a68c25203518 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -314,13 +314,6 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
+ 	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+ 		return -EINVAL;
+ 
+-	if (!amdgpu_sriov_vf(adev)) {
+-		if (is_support_sw_smu(adev))
+-			current_level = smu_get_performance_level(&adev->smu);
+-		else if (adev->powerplay.pp_funcs->get_performance_level)
+-			current_level = amdgpu_dpm_get_performance_level(adev);
+-	}
+-
+ 	if (strncmp("low", buf, strlen("low")) == 0) {
+ 		level = AMD_DPM_FORCED_LEVEL_LOW;
+ 	} else if (strncmp("high", buf, strlen("high")) == 0) {
+@@ -344,17 +337,23 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
+ 		goto fail;
+ 	}
+ 
+-        if (amdgpu_sriov_vf(adev)) {
+-                if (amdgim_is_hwperf(adev) &&
+-                    adev->virt.ops->force_dpm_level) {
+-                        mutex_lock(&adev->pm.mutex);
+-                        adev->virt.ops->force_dpm_level(adev, level);
+-                        mutex_unlock(&adev->pm.mutex);
+-                        return count;
+-                } else {
+-                        return -EINVAL;
++	/* handle sriov case here */
++	if (amdgpu_sriov_vf(adev)) {
++		if (amdgim_is_hwperf(adev) &&
++		    adev->virt.ops->force_dpm_level) {
++			mutex_lock(&adev->pm.mutex);
++			adev->virt.ops->force_dpm_level(adev, level);
++			mutex_unlock(&adev->pm.mutex);
++			return count;
++		} else {
++			return -EINVAL;
+ 		}
+-        }
++	}
++
++	if (is_support_sw_smu(adev))
++		current_level = smu_get_performance_level(&adev->smu);
++	else if (adev->powerplay.pp_funcs->get_performance_level)
++		current_level = amdgpu_dpm_get_performance_level(adev);
+ 
+ 	if (current_level == level)
+ 		return count;
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 1d2d17aad861..abfb19ebf929 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1444,6 +1444,7 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
+ 
+ 	if (!smu->pm_enabled)
+ 		return -EINVAL;
++
+ 	if (!skip_display_settings) {
+ 		ret = smu_display_config_changed(smu);
+ 		if (ret) {
+@@ -1452,8 +1453,6 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
+ 		}
+ 	}
+ 
+-	if (!smu->pm_enabled)
+-		return -EINVAL;
+ 	ret = smu_apply_clocks_adjust_rules(smu);
+ 	if (ret) {
+ 		pr_err("Failed to apply clocks adjust rules!");
+@@ -1472,9 +1471,14 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
+ 		ret = smu_asic_set_performance_level(smu, level);
+ 		if (ret) {
+ 			ret = smu_default_set_performance_level(smu, level);
++			if (ret) {
++				pr_err("Failed to set performance level!");
++				return ret;
++			}
+ 		}
+-		if (!ret)
+-			smu_dpm_ctx->dpm_level = level;
++
++		/* update the saved copy */
++		smu_dpm_ctx->dpm_level = level;
+ 	}
+ 
+ 	if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
+@@ -1533,28 +1537,18 @@ enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
+ 
+ int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
+ {
+-	int ret = 0;
+-	int i;
+ 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
++	int ret = 0;
+ 
+ 	if (!smu_dpm_ctx->dpm_context)
+ 		return -EINVAL;
+ 
+-	for (i = 0; i < smu->adev->num_ip_blocks; i++) {
+-		if (smu->adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)
+-			break;
+-	}
+-
+-
+-	smu->adev->ip_blocks[i].version->funcs->enable_umd_pstate(smu, &level);
+-	ret = smu_handle_task(smu, level,
+-			      AMD_PP_TASK_READJUST_POWER_STATE);
++	ret = smu_enable_umd_pstate(smu, &level);
+ 	if (ret)
+ 		return ret;
+ 
+-	mutex_lock(&smu->mutex);
+-	smu_dpm_ctx->dpm_level = level;
+-	mutex_unlock(&smu->mutex);
++	ret = smu_handle_task(smu, level,
++			      AMD_PP_TASK_READJUST_POWER_STATE);
+ 
+ 	return ret;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3116-drm-amd-powerplay-fix-temperature-granularity-error-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3116-drm-amd-powerplay-fix-temperature-granularity-error-.patch
new file mode 100644
index 00000000..d1f75057
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3116-drm-amd-powerplay-fix-temperature-granularity-error-.patch
@@ -0,0 +1,49 @@
+From 9449e5dfd67b9b4a2373d1acc2603cac23681415 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Tue, 23 Jul 2019 19:56:52 +0800
+Subject: [PATCH 3116/4256] drm/amd/powerplay: fix temperature granularity
+ error in smu11
+
+in this patch,
+drm/amd/powerplay: add callback function of get_thermal_temperature_range
+the driver missed temperature granularity change on other temperature.
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 745b35a1600d..735802bb07b9 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1229,15 +1229,15 @@ static int smu_v11_0_start_thermal_control(struct smu_context *smu)
+ 			return ret;
+ 	}
+ 
+-	adev->pm.dpm.thermal.min_temp = range.min;
+-	adev->pm.dpm.thermal.max_temp = range.max;
+-	adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
+-	adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
+-	adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
+-	adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
+-	adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
+-	adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
+-	adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
++	adev->pm.dpm.thermal.min_temp = range.min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	adev->pm.dpm.thermal.max_temp = range.max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	adev->pm.dpm.thermal.min_mem_temp = range.mem_min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ 	adev->pm.dpm.thermal.min_temp = range.min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ 	adev->pm.dpm.thermal.max_temp = range.max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3117-drm-amdgpu-gmc10-fix-pte-mytpe-field-error-for-navi1.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3117-drm-amdgpu-gmc10-fix-pte-mytpe-field-error-for-navi1.patch
new file mode 100644
index 00000000..c63df659
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3117-drm-amdgpu-gmc10-fix-pte-mytpe-field-error-for-navi1.patch
@@ -0,0 +1,45 @@
+From 082911282ddf72d9c08426f3d869aa896a32e1a5 Mon Sep 17 00:00:00 2001
+From: tiancyin <tianci.yin@amd.com>
+Date: Tue, 16 Jul 2019 18:25:01 +0800
+Subject: [PATCH 3117/4256] drm/amdgpu/gmc10: fix pte mytpe field error for
+ navi14
+
+navi14 share same PTE format with navi10.
+
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: tiancyin <tianci.yin@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 5777d11443d4..3ed870f294f5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -1539,7 +1539,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
+ 	flags &= ~AMDGPU_PTE_EXECUTABLE;
+ 	flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
+ 
+-	if (adev->asic_type == CHIP_NAVI10) {
++	if (adev->asic_type >= CHIP_NAVI10) {
+ 		flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
+ 		flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
+ 	} else {
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+index d857b508ebe9..6733189db978 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+@@ -90,7 +90,7 @@ struct amdgpu_bo_list_entry;
+                                 | AMDGPU_PTE_WRITEABLE  \
+                                 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))
+ 
+-/* NAVI10 only */
++/* gfx10 */
+ #define AMDGPU_PTE_MTYPE_NV10(a)       ((uint64_t)(a) << 48)
+ #define AMDGPU_PTE_MTYPE_NV10_MASK     AMDGPU_PTE_MTYPE_NV10(7ULL)
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3118-drm-amdkfd-Fix-lost-single-step-exceptions-in-gfx9-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3118-drm-amdkfd-Fix-lost-single-step-exceptions-in-gfx9-t.patch
new file mode 100644
index 00000000..12336abb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3118-drm-amdkfd-Fix-lost-single-step-exceptions-in-gfx9-t.patch
@@ -0,0 +1,1656 @@
+From c7ab06839c35613a93801f718b7f4929622689c3 Mon Sep 17 00:00:00 2001
+From: Jay Cornwall <jay.cornwall@amd.com>
+Date: Mon, 22 Jul 2019 19:21:13 -0500
+Subject: [PATCH 3118/4256] drm/amdkfd: Fix lost single step exceptions in gfx9
+ trap handler
+
+If the trap is entered due to MODE.DEBUG_EN=1 and SAVECTX is raised
+concurrently the handler cannot identify the source of the exception.
+This causes the debugger to lose single step exception notification
+when a context save request arrives at the same time.
+
+When MODE.DEBUG_EN=1 and STATUS.HALT=0 (exception not already handled)
+jump to the second-level trap handler upon entering the trap. The
+second-level trap will set STATUS.HALT=1 and return to the shader.
+If SAVECTX was raised then control flow will return to the trap, which
+will then handle the context save request.
+
+Cc: Tony Tye <tony.tye@amd.com>
+Cc: Laurent Morichetti <laurent.morichetti@amd.com>
+Cc: Qingchuan Shi <qingchuan.shi@amd.com>
+Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
+Reviewed-by: Laurent Morichetti <laurent.morichetti@amd.com>
+---
+ .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h    | 1418 +++++++++--------
+ .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm |   20 +
+ 2 files changed, 733 insertions(+), 705 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+index 7274baff5c16..427594035597 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+@@ -274,405 +274,409 @@ static const uint32_t cwsr_trap_gfx8_hex[] = {
+ 
+ 
+ static const uint32_t cwsr_trap_gfx9_hex[] = {
+-	0xbf820001, 0xbf820241,
++	0xbf820001, 0xbf820248,
+ 	0xb8f8f802, 0x89788678,
+-	0xb8fbf803, 0x866eff7b,
+-	0x00000400, 0xbf85003b,
+-	0x866eff7b, 0x00000800,
+-	0xbf850003, 0x866eff7b,
+-	0x00000100, 0xbf84000c,
++	0xb8eef801, 0x866eff6e,
++	0x00000800, 0xbf840003,
+ 	0x866eff78, 0x00002000,
+-	0xbf840005, 0xbf8e0010,
+-	0xb8eef803, 0x866eff6e,
+-	0x00000400, 0xbf84fffb,
+-	0x8778ff78, 0x00002000,
+-	0x80ec886c, 0x82ed806d,
+-	0xb8eef807, 0x866fff6e,
+-	0x001f8000, 0x8e6f8b6f,
+-	0x8977ff77, 0xfc000000,
+-	0x87776f77, 0x896eff6e,
+-	0x001f8000, 0xb96ef807,
+-	0xb8faf812, 0xb8fbf813,
+-	0x8efa887a, 0xc0071bbd,
+-	0x00000000, 0xbf8cc07f,
+-	0xc0071ebd, 0x00000008,
+-	0xbf8cc07f, 0x86ee6e6e,
+-	0xbf840001, 0xbe801d6e,
+-	0xb8fbf803, 0x867bff7b,
+-	0x000001ff, 0xbf850002,
+-	0x806c846c, 0x826d806d,
++	0xbf840016, 0xb8fbf803,
++	0x866eff7b, 0x00000400,
++	0xbf85003b, 0x866eff7b,
++	0x00000800, 0xbf850003,
++	0x866eff7b, 0x00000100,
++	0xbf84000c, 0x866eff78,
++	0x00002000, 0xbf840005,
++	0xbf8e0010, 0xb8eef803,
++	0x866eff6e, 0x00000400,
++	0xbf84fffb, 0x8778ff78,
++	0x00002000, 0x80ec886c,
++	0x82ed806d, 0xb8eef807,
++	0x866fff6e, 0x001f8000,
++	0x8e6f8b6f, 0x8977ff77,
++	0xfc000000, 0x87776f77,
++	0x896eff6e, 0x001f8000,
++	0xb96ef807, 0xb8faf812,
++	0xb8fbf813, 0x8efa887a,
++	0xc0071bbd, 0x00000000,
++	0xbf8cc07f, 0xc0071ebd,
++	0x00000008, 0xbf8cc07f,
++	0x86ee6e6e, 0xbf840001,
++	0xbe801d6e, 0xb8fbf803,
++	0x867bff7b, 0x000001ff,
++	0xbf850002, 0x806c846c,
++	0x826d806d, 0x866dff6d,
++	0x0000ffff, 0x8f6e8b77,
++	0x866eff6e, 0x001f8000,
++	0xb96ef807, 0x86fe7e7e,
++	0x86ea6a6a, 0x8f6e8378,
++	0xb96ee0c2, 0xbf800002,
++	0xb9780002, 0xbe801f6c,
+ 	0x866dff6d, 0x0000ffff,
+-	0x8f6e8b77, 0x866eff6e,
+-	0x001f8000, 0xb96ef807,
+-	0x86fe7e7e, 0x86ea6a6a,
+-	0x8f6e8378, 0xb96ee0c2,
+-	0xbf800002, 0xb9780002,
+-	0xbe801f6c, 0x866dff6d,
+-	0x0000ffff, 0xbefa0080,
+-	0xb97a0283, 0xb8fa2407,
+-	0x8e7a9b7a, 0x876d7a6d,
+-	0xb8fa03c7, 0x8e7a9a7a,
+-	0x876d7a6d, 0xb8faf807,
+-	0x867aff7a, 0x00007fff,
+-	0xb97af807, 0xbeee007e,
+-	0xbeef007f, 0xbefe0180,
+-	0xbf900004, 0x877a8478,
+-	0xb97af802, 0xbf8e0002,
+-	0xbf88fffe, 0xb8fa2a05,
+-	0x807a817a, 0x8e7a8a7a,
+-	0xb8fb1605, 0x807b817b,
+-	0x8e7b867b, 0x807a7b7a,
+-	0x807a7e7a, 0x827b807f,
+-	0x867bff7b, 0x0000ffff,
+-	0xc04b1c3d, 0x00000050,
+-	0xbf8cc07f, 0xc04b1d3d,
+-	0x00000060, 0xbf8cc07f,
+-	0xc0431e7d, 0x00000074,
+-	0xbf8cc07f, 0xbef4007e,
+-	0x8675ff7f, 0x0000ffff,
+-	0x8775ff75, 0x00040000,
+-	0xbef60080, 0xbef700ff,
+-	0x00807fac, 0x867aff7f,
+-	0x08000000, 0x8f7a837a,
+-	0x87777a77, 0x867aff7f,
+-	0x70000000, 0x8f7a817a,
+-	0x87777a77, 0xbef1007c,
+-	0xbef00080, 0xb8f02a05,
+-	0x80708170, 0x8e708a70,
+-	0xb8fa1605, 0x807a817a,
+-	0x8e7a867a, 0x80707a70,
+-	0xbef60084, 0xbef600ff,
+-	0x01000000, 0xbefe007c,
+-	0xbefc0070, 0xc0611c7a,
+-	0x0000007c, 0xbf8cc07f,
+-	0x80708470, 0xbefc007e,
++	0xbefa0080, 0xb97a0283,
++	0xb8fa2407, 0x8e7a9b7a,
++	0x876d7a6d, 0xb8fa03c7,
++	0x8e7a9a7a, 0x876d7a6d,
++	0xb8faf807, 0x867aff7a,
++	0x00007fff, 0xb97af807,
++	0xbeee007e, 0xbeef007f,
++	0xbefe0180, 0xbf900004,
++	0x877a8478, 0xb97af802,
++	0xbf8e0002, 0xbf88fffe,
++	0xb8fa2a05, 0x807a817a,
++	0x8e7a8a7a, 0xb8fb1605,
++	0x807b817b, 0x8e7b867b,
++	0x807a7b7a, 0x807a7e7a,
++	0x827b807f, 0x867bff7b,
++	0x0000ffff, 0xc04b1c3d,
++	0x00000050, 0xbf8cc07f,
++	0xc04b1d3d, 0x00000060,
++	0xbf8cc07f, 0xc0431e7d,
++	0x00000074, 0xbf8cc07f,
++	0xbef4007e, 0x8675ff7f,
++	0x0000ffff, 0x8775ff75,
++	0x00040000, 0xbef60080,
++	0xbef700ff, 0x00807fac,
++	0x867aff7f, 0x08000000,
++	0x8f7a837a, 0x87777a77,
++	0x867aff7f, 0x70000000,
++	0x8f7a817a, 0x87777a77,
++	0xbef1007c, 0xbef00080,
++	0xb8f02a05, 0x80708170,
++	0x8e708a70, 0xb8fa1605,
++	0x807a817a, 0x8e7a867a,
++	0x80707a70, 0xbef60084,
++	0xbef600ff, 0x01000000,
+ 	0xbefe007c, 0xbefc0070,
+-	0xc0611b3a, 0x0000007c,
++	0xc0611c7a, 0x0000007c,
+ 	0xbf8cc07f, 0x80708470,
+ 	0xbefc007e, 0xbefe007c,
+-	0xbefc0070, 0xc0611b7a,
++	0xbefc0070, 0xc0611b3a,
+ 	0x0000007c, 0xbf8cc07f,
+ 	0x80708470, 0xbefc007e,
+ 	0xbefe007c, 0xbefc0070,
+-	0xc0611bba, 0x0000007c,
++	0xc0611b7a, 0x0000007c,
+ 	0xbf8cc07f, 0x80708470,
+ 	0xbefc007e, 0xbefe007c,
+-	0xbefc0070, 0xc0611bfa,
++	0xbefc0070, 0xc0611bba,
+ 	0x0000007c, 0xbf8cc07f,
+ 	0x80708470, 0xbefc007e,
+ 	0xbefe007c, 0xbefc0070,
+-	0xc0611e3a, 0x0000007c,
+-	0xbf8cc07f, 0x80708470,
+-	0xbefc007e, 0xb8fbf803,
+-	0xbefe007c, 0xbefc0070,
+-	0xc0611efa, 0x0000007c,
++	0xc0611bfa, 0x0000007c,
+ 	0xbf8cc07f, 0x80708470,
+ 	0xbefc007e, 0xbefe007c,
+-	0xbefc0070, 0xc0611a3a,
++	0xbefc0070, 0xc0611e3a,
++	0x0000007c, 0xbf8cc07f,
++	0x80708470, 0xbefc007e,
++	0xb8fbf803, 0xbefe007c,
++	0xbefc0070, 0xc0611efa,
+ 	0x0000007c, 0xbf8cc07f,
+ 	0x80708470, 0xbefc007e,
+ 	0xbefe007c, 0xbefc0070,
+-	0xc0611a7a, 0x0000007c,
+-	0xbf8cc07f, 0x80708470,
+-	0xbefc007e, 0xb8f1f801,
+-	0xbefe007c, 0xbefc0070,
+-	0xc0611c7a, 0x0000007c,
++	0xc0611a3a, 0x0000007c,
+ 	0xbf8cc07f, 0x80708470,
+-	0xbefc007e, 0x867aff7f,
+-	0x04000000, 0xbeef0080,
+-	0x876f6f7a, 0xb8f02a05,
+-	0x80708170, 0x8e708a70,
+-	0xb8fb1605, 0x807b817b,
+-	0x8e7b847b, 0x8e76827b,
+-	0xbef600ff, 0x01000000,
+-	0xbef20174, 0x80747074,
+-	0x82758075, 0xbefc0080,
+-	0xbf800000, 0xbe802b00,
+-	0xbe822b02, 0xbe842b04,
+-	0xbe862b06, 0xbe882b08,
+-	0xbe8a2b0a, 0xbe8c2b0c,
+-	0xbe8e2b0e, 0xc06b003a,
+-	0x00000000, 0xbf8cc07f,
+-	0xc06b013a, 0x00000010,
+-	0xbf8cc07f, 0xc06b023a,
+-	0x00000020, 0xbf8cc07f,
+-	0xc06b033a, 0x00000030,
+-	0xbf8cc07f, 0x8074c074,
+-	0x82758075, 0x807c907c,
+-	0xbf0a7b7c, 0xbf85ffe7,
+-	0xbef40172, 0xbef00080,
+-	0xbefe00c1, 0xbeff00c1,
+-	0xbee80080, 0xbee90080,
+-	0xbef600ff, 0x01000000,
+-	0x867aff78, 0x00400000,
+-	0xbf850003, 0xb8faf803,
+-	0x897a7aff, 0x10000000,
+-	0xbf85004d, 0xbe840080,
+-	0xd2890000, 0x00000900,
+-	0x80048104, 0xd2890001,
+-	0x00000900, 0x80048104,
+-	0xd2890002, 0x00000900,
+-	0x80048104, 0xd2890003,
+-	0x00000900, 0x80048104,
+-	0xc069003a, 0x00000070,
+-	0xbf8cc07f, 0x80709070,
+-	0xbf06c004, 0xbf84ffee,
++	0xbefc007e, 0xbefe007c,
++	0xbefc0070, 0xc0611a7a,
++	0x0000007c, 0xbf8cc07f,
++	0x80708470, 0xbefc007e,
++	0xb8f1f801, 0xbefe007c,
++	0xbefc0070, 0xc0611c7a,
++	0x0000007c, 0xbf8cc07f,
++	0x80708470, 0xbefc007e,
++	0x867aff7f, 0x04000000,
++	0xbeef0080, 0x876f6f7a,
++	0xb8f02a05, 0x80708170,
++	0x8e708a70, 0xb8fb1605,
++	0x807b817b, 0x8e7b847b,
++	0x8e76827b, 0xbef600ff,
++	0x01000000, 0xbef20174,
++	0x80747074, 0x82758075,
++	0xbefc0080, 0xbf800000,
++	0xbe802b00, 0xbe822b02,
++	0xbe842b04, 0xbe862b06,
++	0xbe882b08, 0xbe8a2b0a,
++	0xbe8c2b0c, 0xbe8e2b0e,
++	0xc06b003a, 0x00000000,
++	0xbf8cc07f, 0xc06b013a,
++	0x00000010, 0xbf8cc07f,
++	0xc06b023a, 0x00000020,
++	0xbf8cc07f, 0xc06b033a,
++	0x00000030, 0xbf8cc07f,
++	0x8074c074, 0x82758075,
++	0x807c907c, 0xbf0a7b7c,
++	0xbf85ffe7, 0xbef40172,
++	0xbef00080, 0xbefe00c1,
++	0xbeff00c1, 0xbee80080,
++	0xbee90080, 0xbef600ff,
++	0x01000000, 0x867aff78,
++	0x00400000, 0xbf850003,
++	0xb8faf803, 0x897a7aff,
++	0x10000000, 0xbf85004d,
+ 	0xbe840080, 0xd2890000,
+-	0x00000901, 0x80048104,
+-	0xd2890001, 0x00000901,
++	0x00000900, 0x80048104,
++	0xd2890001, 0x00000900,
+ 	0x80048104, 0xd2890002,
+-	0x00000901, 0x80048104,
+-	0xd2890003, 0x00000901,
++	0x00000900, 0x80048104,
++	0xd2890003, 0x00000900,
+ 	0x80048104, 0xc069003a,
+ 	0x00000070, 0xbf8cc07f,
+ 	0x80709070, 0xbf06c004,
+ 	0xbf84ffee, 0xbe840080,
+-	0xd2890000, 0x00000902,
++	0xd2890000, 0x00000901,
+ 	0x80048104, 0xd2890001,
+-	0x00000902, 0x80048104,
+-	0xd2890002, 0x00000902,
++	0x00000901, 0x80048104,
++	0xd2890002, 0x00000901,
+ 	0x80048104, 0xd2890003,
+-	0x00000902, 0x80048104,
++	0x00000901, 0x80048104,
+ 	0xc069003a, 0x00000070,
+ 	0xbf8cc07f, 0x80709070,
+ 	0xbf06c004, 0xbf84ffee,
+ 	0xbe840080, 0xd2890000,
+-	0x00000903, 0x80048104,
+-	0xd2890001, 0x00000903,
++	0x00000902, 0x80048104,
++	0xd2890001, 0x00000902,
+ 	0x80048104, 0xd2890002,
+-	0x00000903, 0x80048104,
+-	0xd2890003, 0x00000903,
++	0x00000902, 0x80048104,
++	0xd2890003, 0x00000902,
+ 	0x80048104, 0xc069003a,
+ 	0x00000070, 0xbf8cc07f,
+ 	0x80709070, 0xbf06c004,
+-	0xbf84ffee, 0xbf820008,
+-	0xe0724000, 0x701d0000,
+-	0xe0724100, 0x701d0100,
+-	0xe0724200, 0x701d0200,
+-	0xe0724300, 0x701d0300,
+-	0xbefe00c1, 0xbeff00c1,
+-	0xb8fb4306, 0x867bc17b,
+-	0xbf840063, 0xbf8a0000,
+-	0x867aff6f, 0x04000000,
+-	0xbf84005f, 0x8e7b867b,
+-	0x8e7b827b, 0xbef6007b,
+-	0xb8f02a05, 0x80708170,
+-	0x8e708a70, 0xb8fa1605,
+-	0x807a817a, 0x8e7a867a,
+-	0x80707a70, 0x8070ff70,
+-	0x00000080, 0xbef600ff,
+-	0x01000000, 0xbefc0080,
+-	0xd28c0002, 0x000100c1,
+-	0xd28d0003, 0x000204c1,
+-	0x867aff78, 0x00400000,
+-	0xbf850003, 0xb8faf803,
+-	0x897a7aff, 0x10000000,
+-	0xbf850030, 0x24040682,
+-	0xd86e4000, 0x00000002,
+-	0xbf8cc07f, 0xbe840080,
+-	0xd2890000, 0x00000900,
++	0xbf84ffee, 0xbe840080,
++	0xd2890000, 0x00000903,
+ 	0x80048104, 0xd2890001,
+-	0x00000900, 0x80048104,
+-	0xd2890002, 0x00000900,
++	0x00000903, 0x80048104,
++	0xd2890002, 0x00000903,
+ 	0x80048104, 0xd2890003,
+-	0x00000900, 0x80048104,
++	0x00000903, 0x80048104,
+ 	0xc069003a, 0x00000070,
+ 	0xbf8cc07f, 0x80709070,
+ 	0xbf06c004, 0xbf84ffee,
++	0xbf820008, 0xe0724000,
++	0x701d0000, 0xe0724100,
++	0x701d0100, 0xe0724200,
++	0x701d0200, 0xe0724300,
++	0x701d0300, 0xbefe00c1,
++	0xbeff00c1, 0xb8fb4306,
++	0x867bc17b, 0xbf840063,
++	0xbf8a0000, 0x867aff6f,
++	0x04000000, 0xbf84005f,
++	0x8e7b867b, 0x8e7b827b,
++	0xbef6007b, 0xb8f02a05,
++	0x80708170, 0x8e708a70,
++	0xb8fa1605, 0x807a817a,
++	0x8e7a867a, 0x80707a70,
++	0x8070ff70, 0x00000080,
++	0xbef600ff, 0x01000000,
++	0xbefc0080, 0xd28c0002,
++	0x000100c1, 0xd28d0003,
++	0x000204c1, 0x867aff78,
++	0x00400000, 0xbf850003,
++	0xb8faf803, 0x897a7aff,
++	0x10000000, 0xbf850030,
++	0x24040682, 0xd86e4000,
++	0x00000002, 0xbf8cc07f,
+ 	0xbe840080, 0xd2890000,
+-	0x00000901, 0x80048104,
+-	0xd2890001, 0x00000901,
++	0x00000900, 0x80048104,
++	0xd2890001, 0x00000900,
+ 	0x80048104, 0xd2890002,
+-	0x00000901, 0x80048104,
+-	0xd2890003, 0x00000901,
++	0x00000900, 0x80048104,
++	0xd2890003, 0x00000900,
+ 	0x80048104, 0xc069003a,
+ 	0x00000070, 0xbf8cc07f,
+ 	0x80709070, 0xbf06c004,
+-	0xbf84ffee, 0x680404ff,
+-	0x00000200, 0xd0c9006a,
+-	0x0000f702, 0xbf87ffd2,
+-	0xbf820015, 0xd1060002,
+-	0x00011103, 0x7e0602ff,
+-	0x00000200, 0xbefc00ff,
+-	0x00010000, 0xbe800077,
+-	0x8677ff77, 0xff7fffff,
+-	0x8777ff77, 0x00058000,
+-	0xd8ec0000, 0x00000002,
+-	0xbf8cc07f, 0xe0765000,
+-	0x701d0002, 0x68040702,
+-	0xd0c9006a, 0x0000f702,
+-	0xbf87fff7, 0xbef70000,
+-	0xbef000ff, 0x00000400,
+-	0xbefe00c1, 0xbeff00c1,
+-	0xb8fb2a05, 0x807b817b,
+-	0x8e7b827b, 0x8e76887b,
+-	0xbef600ff, 0x01000000,
+-	0xbefc0084, 0xbf0a7b7c,
+-	0xbf84006d, 0xbf11017c,
+-	0x807bff7b, 0x00001000,
+-	0x867aff78, 0x00400000,
+-	0xbf850003, 0xb8faf803,
+-	0x897a7aff, 0x10000000,
+-	0xbf850051, 0xbe840080,
+-	0xd2890000, 0x00000900,
++	0xbf84ffee, 0xbe840080,
++	0xd2890000, 0x00000901,
+ 	0x80048104, 0xd2890001,
+-	0x00000900, 0x80048104,
+-	0xd2890002, 0x00000900,
++	0x00000901, 0x80048104,
++	0xd2890002, 0x00000901,
+ 	0x80048104, 0xd2890003,
+-	0x00000900, 0x80048104,
++	0x00000901, 0x80048104,
+ 	0xc069003a, 0x00000070,
+ 	0xbf8cc07f, 0x80709070,
+ 	0xbf06c004, 0xbf84ffee,
++	0x680404ff, 0x00000200,
++	0xd0c9006a, 0x0000f702,
++	0xbf87ffd2, 0xbf820015,
++	0xd1060002, 0x00011103,
++	0x7e0602ff, 0x00000200,
++	0xbefc00ff, 0x00010000,
++	0xbe800077, 0x8677ff77,
++	0xff7fffff, 0x8777ff77,
++	0x00058000, 0xd8ec0000,
++	0x00000002, 0xbf8cc07f,
++	0xe0765000, 0x701d0002,
++	0x68040702, 0xd0c9006a,
++	0x0000f702, 0xbf87fff7,
++	0xbef70000, 0xbef000ff,
++	0x00000400, 0xbefe00c1,
++	0xbeff00c1, 0xb8fb2a05,
++	0x807b817b, 0x8e7b827b,
++	0x8e76887b, 0xbef600ff,
++	0x01000000, 0xbefc0084,
++	0xbf0a7b7c, 0xbf84006d,
++	0xbf11017c, 0x807bff7b,
++	0x00001000, 0x867aff78,
++	0x00400000, 0xbf850003,
++	0xb8faf803, 0x897a7aff,
++	0x10000000, 0xbf850051,
+ 	0xbe840080, 0xd2890000,
+-	0x00000901, 0x80048104,
+-	0xd2890001, 0x00000901,
++	0x00000900, 0x80048104,
++	0xd2890001, 0x00000900,
+ 	0x80048104, 0xd2890002,
+-	0x00000901, 0x80048104,
+-	0xd2890003, 0x00000901,
++	0x00000900, 0x80048104,
++	0xd2890003, 0x00000900,
+ 	0x80048104, 0xc069003a,
+ 	0x00000070, 0xbf8cc07f,
+ 	0x80709070, 0xbf06c004,
+ 	0xbf84ffee, 0xbe840080,
+-	0xd2890000, 0x00000902,
++	0xd2890000, 0x00000901,
+ 	0x80048104, 0xd2890001,
+-	0x00000902, 0x80048104,
+-	0xd2890002, 0x00000902,
++	0x00000901, 0x80048104,
++	0xd2890002, 0x00000901,
+ 	0x80048104, 0xd2890003,
+-	0x00000902, 0x80048104,
++	0x00000901, 0x80048104,
+ 	0xc069003a, 0x00000070,
+ 	0xbf8cc07f, 0x80709070,
+ 	0xbf06c004, 0xbf84ffee,
+ 	0xbe840080, 0xd2890000,
+-	0x00000903, 0x80048104,
+-	0xd2890001, 0x00000903,
++	0x00000902, 0x80048104,
++	0xd2890001, 0x00000902,
+ 	0x80048104, 0xd2890002,
+-	0x00000903, 0x80048104,
+-	0xd2890003, 0x00000903,
++	0x00000902, 0x80048104,
++	0xd2890003, 0x00000902,
+ 	0x80048104, 0xc069003a,
+ 	0x00000070, 0xbf8cc07f,
+ 	0x80709070, 0xbf06c004,
+-	0xbf84ffee, 0x807c847c,
+-	0xbf0a7b7c, 0xbf85ffb1,
+-	0xbf9c0000, 0xbf820012,
+-	0x7e000300, 0x7e020301,
+-	0x7e040302, 0x7e060303,
+-	0xe0724000, 0x701d0000,
+-	0xe0724100, 0x701d0100,
+-	0xe0724200, 0x701d0200,
+-	0xe0724300, 0x701d0300,
+-	0x807c847c, 0x8070ff70,
+-	0x00000400, 0xbf0a7b7c,
+-	0xbf85ffef, 0xbf9c0000,
+-	0xbf8200da, 0xbef4007e,
+-	0x8675ff7f, 0x0000ffff,
+-	0x8775ff75, 0x00040000,
+-	0xbef60080, 0xbef700ff,
+-	0x00807fac, 0x866eff7f,
+-	0x08000000, 0x8f6e836e,
+-	0x87776e77, 0x866eff7f,
+-	0x70000000, 0x8f6e816e,
+-	0x87776e77, 0x866eff7f,
+-	0x04000000, 0xbf84001e,
+-	0xbefe00c1, 0xbeff00c1,
+-	0xb8ef4306, 0x866fc16f,
+-	0xbf840019, 0x8e6f866f,
+-	0x8e6f826f, 0xbef6006f,
+-	0xb8f82a05, 0x80788178,
+-	0x8e788a78, 0xb8ee1605,
+-	0x806e816e, 0x8e6e866e,
+-	0x80786e78, 0x8078ff78,
+-	0x00000080, 0xbef600ff,
+-	0x01000000, 0xbefc0080,
+-	0xe0510000, 0x781d0000,
+-	0xe0510100, 0x781d0000,
+-	0x807cff7c, 0x00000200,
+-	0x8078ff78, 0x00000200,
+-	0xbf0a6f7c, 0xbf85fff6,
+-	0xbef80080, 0xbefe00c1,
+-	0xbeff00c1, 0xb8ef2a05,
+-	0x806f816f, 0x8e6f826f,
+-	0x8e76886f, 0xbef600ff,
+-	0x01000000, 0xbeee0078,
+-	0x8078ff78, 0x00000400,
+-	0xbefc0084, 0xbf11087c,
+-	0x806fff6f, 0x00008000,
+-	0xe0524000, 0x781d0000,
+-	0xe0524100, 0x781d0100,
+-	0xe0524200, 0x781d0200,
+-	0xe0524300, 0x781d0300,
+-	0xbf8c0f70, 0x7e000300,
++	0xbf84ffee, 0xbe840080,
++	0xd2890000, 0x00000903,
++	0x80048104, 0xd2890001,
++	0x00000903, 0x80048104,
++	0xd2890002, 0x00000903,
++	0x80048104, 0xd2890003,
++	0x00000903, 0x80048104,
++	0xc069003a, 0x00000070,
++	0xbf8cc07f, 0x80709070,
++	0xbf06c004, 0xbf84ffee,
++	0x807c847c, 0xbf0a7b7c,
++	0xbf85ffb1, 0xbf9c0000,
++	0xbf820012, 0x7e000300,
+ 	0x7e020301, 0x7e040302,
+-	0x7e060303, 0x807c847c,
+-	0x8078ff78, 0x00000400,
+-	0xbf0a6f7c, 0xbf85ffee,
+-	0xbf9c0000, 0xe0524000,
+-	0x6e1d0000, 0xe0524100,
+-	0x6e1d0100, 0xe0524200,
+-	0x6e1d0200, 0xe0524300,
+-	0x6e1d0300, 0xb8f82a05,
++	0x7e060303, 0xe0724000,
++	0x701d0000, 0xe0724100,
++	0x701d0100, 0xe0724200,
++	0x701d0200, 0xe0724300,
++	0x701d0300, 0x807c847c,
++	0x8070ff70, 0x00000400,
++	0xbf0a7b7c, 0xbf85ffef,
++	0xbf9c0000, 0xbf8200da,
++	0xbef4007e, 0x8675ff7f,
++	0x0000ffff, 0x8775ff75,
++	0x00040000, 0xbef60080,
++	0xbef700ff, 0x00807fac,
++	0x866eff7f, 0x08000000,
++	0x8f6e836e, 0x87776e77,
++	0x866eff7f, 0x70000000,
++	0x8f6e816e, 0x87776e77,
++	0x866eff7f, 0x04000000,
++	0xbf84001e, 0xbefe00c1,
++	0xbeff00c1, 0xb8ef4306,
++	0x866fc16f, 0xbf840019,
++	0x8e6f866f, 0x8e6f826f,
++	0xbef6006f, 0xb8f82a05,
+ 	0x80788178, 0x8e788a78,
+ 	0xb8ee1605, 0x806e816e,
+ 	0x8e6e866e, 0x80786e78,
+-	0x80f8c078, 0xb8ef1605,
+-	0x806f816f, 0x8e6f846f,
+-	0x8e76826f, 0xbef600ff,
+-	0x01000000, 0xbefc006f,
+-	0xc031003a, 0x00000078,
+-	0x80f8c078, 0xbf8cc07f,
+-	0x80fc907c, 0xbf800000,
+-	0xbe802d00, 0xbe822d02,
+-	0xbe842d04, 0xbe862d06,
+-	0xbe882d08, 0xbe8a2d0a,
+-	0xbe8c2d0c, 0xbe8e2d0e,
+-	0xbf06807c, 0xbf84fff0,
++	0x8078ff78, 0x00000080,
++	0xbef600ff, 0x01000000,
++	0xbefc0080, 0xe0510000,
++	0x781d0000, 0xe0510100,
++	0x781d0000, 0x807cff7c,
++	0x00000200, 0x8078ff78,
++	0x00000200, 0xbf0a6f7c,
++	0xbf85fff6, 0xbef80080,
++	0xbefe00c1, 0xbeff00c1,
++	0xb8ef2a05, 0x806f816f,
++	0x8e6f826f, 0x8e76886f,
++	0xbef600ff, 0x01000000,
++	0xbeee0078, 0x8078ff78,
++	0x00000400, 0xbefc0084,
++	0xbf11087c, 0x806fff6f,
++	0x00008000, 0xe0524000,
++	0x781d0000, 0xe0524100,
++	0x781d0100, 0xe0524200,
++	0x781d0200, 0xe0524300,
++	0x781d0300, 0xbf8c0f70,
++	0x7e000300, 0x7e020301,
++	0x7e040302, 0x7e060303,
++	0x807c847c, 0x8078ff78,
++	0x00000400, 0xbf0a6f7c,
++	0xbf85ffee, 0xbf9c0000,
++	0xe0524000, 0x6e1d0000,
++	0xe0524100, 0x6e1d0100,
++	0xe0524200, 0x6e1d0200,
++	0xe0524300, 0x6e1d0300,
+ 	0xb8f82a05, 0x80788178,
+ 	0x8e788a78, 0xb8ee1605,
+ 	0x806e816e, 0x8e6e866e,
+-	0x80786e78, 0xbef60084,
++	0x80786e78, 0x80f8c078,
++	0xb8ef1605, 0x806f816f,
++	0x8e6f846f, 0x8e76826f,
+ 	0xbef600ff, 0x01000000,
+-	0xc0211bfa, 0x00000078,
+-	0x80788478, 0xc0211b3a,
++	0xbefc006f, 0xc031003a,
++	0x00000078, 0x80f8c078,
++	0xbf8cc07f, 0x80fc907c,
++	0xbf800000, 0xbe802d00,
++	0xbe822d02, 0xbe842d04,
++	0xbe862d06, 0xbe882d08,
++	0xbe8a2d0a, 0xbe8c2d0c,
++	0xbe8e2d0e, 0xbf06807c,
++	0xbf84fff0, 0xb8f82a05,
++	0x80788178, 0x8e788a78,
++	0xb8ee1605, 0x806e816e,
++	0x8e6e866e, 0x80786e78,
++	0xbef60084, 0xbef600ff,
++	0x01000000, 0xc0211bfa,
+ 	0x00000078, 0x80788478,
+-	0xc0211b7a, 0x00000078,
+-	0x80788478, 0xc0211c3a,
++	0xc0211b3a, 0x00000078,
++	0x80788478, 0xc0211b7a,
+ 	0x00000078, 0x80788478,
+-	0xc0211c7a, 0x00000078,
+-	0x80788478, 0xc0211eba,
++	0xc0211c3a, 0x00000078,
++	0x80788478, 0xc0211c7a,
+ 	0x00000078, 0x80788478,
+-	0xc0211efa, 0x00000078,
+-	0x80788478, 0xc0211a3a,
++	0xc0211eba, 0x00000078,
++	0x80788478, 0xc0211efa,
+ 	0x00000078, 0x80788478,
+-	0xc0211a7a, 0x00000078,
+-	0x80788478, 0xc0211cfa,
++	0xc0211a3a, 0x00000078,
++	0x80788478, 0xc0211a7a,
+ 	0x00000078, 0x80788478,
+-	0xbf8cc07f, 0xbefc006f,
+-	0xbefe0070, 0xbeff0071,
+-	0x866f7bff, 0x000003ff,
+-	0xb96f4803, 0x866f7bff,
+-	0xfffff800, 0x8f6f8b6f,
+-	0xb96fa2c3, 0xb973f801,
+-	0xb8ee2a05, 0x806e816e,
+-	0x8e6e8a6e, 0xb8ef1605,
+-	0x806f816f, 0x8e6f866f,
+-	0x806e6f6e, 0x806e746e,
+-	0x826f8075, 0x866fff6f,
+-	0x0000ffff, 0xc00b1c37,
+-	0x00000050, 0xc00b1d37,
+-	0x00000060, 0xc0031e77,
+-	0x00000074, 0xbf8cc07f,
+-	0x866fff6d, 0xf8000000,
+-	0x8f6f9b6f, 0x8e6f906f,
+-	0xbeee0080, 0x876e6f6e,
+-	0x866fff6d, 0x04000000,
+-	0x8f6f9a6f, 0x8e6f8f6f,
+-	0x876e6f6e, 0x866fff7a,
+-	0x00800000, 0x8f6f976f,
+-	0xb96ef807, 0x866dff6d,
+-	0x0000ffff, 0x86fe7e7e,
+-	0x86ea6a6a, 0x8f6e837a,
+-	0xb96ee0c2, 0xbf800002,
+-	0xb97a0002, 0xbf8a0000,
+-	0x95806f6c, 0xbf810000,
++	0xc0211cfa, 0x00000078,
++	0x80788478, 0xbf8cc07f,
++	0xbefc006f, 0xbefe0070,
++	0xbeff0071, 0x866f7bff,
++	0x000003ff, 0xb96f4803,
++	0x866f7bff, 0xfffff800,
++	0x8f6f8b6f, 0xb96fa2c3,
++	0xb973f801, 0xb8ee2a05,
++	0x806e816e, 0x8e6e8a6e,
++	0xb8ef1605, 0x806f816f,
++	0x8e6f866f, 0x806e6f6e,
++	0x806e746e, 0x826f8075,
++	0x866fff6f, 0x0000ffff,
++	0xc00b1c37, 0x00000050,
++	0xc00b1d37, 0x00000060,
++	0xc0031e77, 0x00000074,
++	0xbf8cc07f, 0x866fff6d,
++	0xf8000000, 0x8f6f9b6f,
++	0x8e6f906f, 0xbeee0080,
++	0x876e6f6e, 0x866fff6d,
++	0x04000000, 0x8f6f9a6f,
++	0x8e6f8f6f, 0x876e6f6e,
++	0x866fff7a, 0x00800000,
++	0x8f6f976f, 0xb96ef807,
++	0x866dff6d, 0x0000ffff,
++	0x86fe7e7e, 0x86ea6a6a,
++	0x8f6e837a, 0xb96ee0c2,
++	0xbf800002, 0xb97a0002,
++	0xbf8a0000, 0x95806f6c,
++	0xbf810000, 0x00000000,
+ };
+ 
+ static const uint32_t cwsr_trap_gfx10_hex[] = {
+@@ -974,248 +978,145 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
+ 	0xbf9f0000, 0x00000000,
+ };
+ static const uint32_t cwsr_trap_arcturus_hex[] = {
+-	0xbf820001, 0xbf8202bd,
++	0xbf820001, 0xbf8202c4,
+ 	0xb8f8f802, 0x89788678,
+-	0xb8fbf803, 0x866eff7b,
+-	0x00000400, 0xbf85003b,
+-	0x866eff7b, 0x00000800,
+-	0xbf850003, 0x866eff7b,
+-	0x00000100, 0xbf84000c,
++	0xb8eef801, 0x866eff6e,
++	0x00000800, 0xbf840003,
+ 	0x866eff78, 0x00002000,
+-	0xbf840005, 0xbf8e0010,
+-	0xb8eef803, 0x866eff6e,
+-	0x00000400, 0xbf84fffb,
+-	0x8778ff78, 0x00002000,
+-	0x80ec886c, 0x82ed806d,
+-	0xb8eef807, 0x866fff6e,
+-	0x001f8000, 0x8e6f8b6f,
+-	0x8977ff77, 0xfc000000,
+-	0x87776f77, 0x896eff6e,
+-	0x001f8000, 0xb96ef807,
+-	0xb8faf812, 0xb8fbf813,
+-	0x8efa887a, 0xc0071bbd,
+-	0x00000000, 0xbf8cc07f,
+-	0xc0071ebd, 0x00000008,
+-	0xbf8cc07f, 0x86ee6e6e,
+-	0xbf840001, 0xbe801d6e,
+-	0xb8fbf803, 0x867bff7b,
+-	0x000001ff, 0xbf850002,
+-	0x806c846c, 0x826d806d,
++	0xbf840016, 0xb8fbf803,
++	0x866eff7b, 0x00000400,
++	0xbf85003b, 0x866eff7b,
++	0x00000800, 0xbf850003,
++	0x866eff7b, 0x00000100,
++	0xbf84000c, 0x866eff78,
++	0x00002000, 0xbf840005,
++	0xbf8e0010, 0xb8eef803,
++	0x866eff6e, 0x00000400,
++	0xbf84fffb, 0x8778ff78,
++	0x00002000, 0x80ec886c,
++	0x82ed806d, 0xb8eef807,
++	0x866fff6e, 0x001f8000,
++	0x8e6f8b6f, 0x8977ff77,
++	0xfc000000, 0x87776f77,
++	0x896eff6e, 0x001f8000,
++	0xb96ef807, 0xb8faf812,
++	0xb8fbf813, 0x8efa887a,
++	0xc0071bbd, 0x00000000,
++	0xbf8cc07f, 0xc0071ebd,
++	0x00000008, 0xbf8cc07f,
++	0x86ee6e6e, 0xbf840001,
++	0xbe801d6e, 0xb8fbf803,
++	0x867bff7b, 0x000001ff,
++	0xbf850002, 0x806c846c,
++	0x826d806d, 0x866dff6d,
++	0x0000ffff, 0x8f6e8b77,
++	0x866eff6e, 0x001f8000,
++	0xb96ef807, 0x86fe7e7e,
++	0x86ea6a6a, 0x8f6e8378,
++	0xb96ee0c2, 0xbf800002,
++	0xb9780002, 0xbe801f6c,
+ 	0x866dff6d, 0x0000ffff,
+-	0x8f6e8b77, 0x866eff6e,
+-	0x001f8000, 0xb96ef807,
+-	0x86fe7e7e, 0x86ea6a6a,
+-	0x8f6e8378, 0xb96ee0c2,
+-	0xbf800002, 0xb9780002,
+-	0xbe801f6c, 0x866dff6d,
+-	0x0000ffff, 0xbefa0080,
+-	0xb97a0283, 0xb8fa2407,
+-	0x8e7a9b7a, 0x876d7a6d,
+-	0xb8fa03c7, 0x8e7a9a7a,
+-	0x876d7a6d, 0xb8faf807,
+-	0x867aff7a, 0x00007fff,
+-	0xb97af807, 0xbeee007e,
+-	0xbeef007f, 0xbefe0180,
+-	0xbf900004, 0x877a8478,
+-	0xb97af802, 0xbf8e0002,
+-	0xbf88fffe, 0xb8fa2a05,
+-	0x807a817a, 0x8e7a8a7a,
+-	0x8e7a817a, 0xb8fb1605,
+-	0x807b817b, 0x8e7b867b,
+-	0x807a7b7a, 0x807a7e7a,
+-	0x827b807f, 0x867bff7b,
+-	0x0000ffff, 0xc04b1c3d,
+-	0x00000050, 0xbf8cc07f,
+-	0xc04b1d3d, 0x00000060,
+-	0xbf8cc07f, 0xc0431e7d,
+-	0x00000074, 0xbf8cc07f,
+-	0xbef4007e, 0x8675ff7f,
+-	0x0000ffff, 0x8775ff75,
+-	0x00040000, 0xbef60080,
+-	0xbef700ff, 0x00807fac,
+-	0x867aff7f, 0x08000000,
+-	0x8f7a837a, 0x87777a77,
+-	0x867aff7f, 0x70000000,
+-	0x8f7a817a, 0x87777a77,
+-	0xbef1007c, 0xbef00080,
+-	0xb8f02a05, 0x80708170,
+-	0x8e708a70, 0x8e708170,
+-	0xb8fa1605, 0x807a817a,
+-	0x8e7a867a, 0x80707a70,
+-	0xbef60084, 0xbef600ff,
+-	0x01000000, 0xbefe007c,
+-	0xbefc0070, 0xc0611c7a,
+-	0x0000007c, 0xbf8cc07f,
+-	0x80708470, 0xbefc007e,
++	0xbefa0080, 0xb97a0283,
++	0xb8fa2407, 0x8e7a9b7a,
++	0x876d7a6d, 0xb8fa03c7,
++	0x8e7a9a7a, 0x876d7a6d,
++	0xb8faf807, 0x867aff7a,
++	0x00007fff, 0xb97af807,
++	0xbeee007e, 0xbeef007f,
++	0xbefe0180, 0xbf900004,
++	0x877a8478, 0xb97af802,
++	0xbf8e0002, 0xbf88fffe,
++	0xb8fa2a05, 0x807a817a,
++	0x8e7a8a7a, 0x8e7a817a,
++	0xb8fb1605, 0x807b817b,
++	0x8e7b867b, 0x807a7b7a,
++	0x807a7e7a, 0x827b807f,
++	0x867bff7b, 0x0000ffff,
++	0xc04b1c3d, 0x00000050,
++	0xbf8cc07f, 0xc04b1d3d,
++	0x00000060, 0xbf8cc07f,
++	0xc0431e7d, 0x00000074,
++	0xbf8cc07f, 0xbef4007e,
++	0x8675ff7f, 0x0000ffff,
++	0x8775ff75, 0x00040000,
++	0xbef60080, 0xbef700ff,
++	0x00807fac, 0x867aff7f,
++	0x08000000, 0x8f7a837a,
++	0x87777a77, 0x867aff7f,
++	0x70000000, 0x8f7a817a,
++	0x87777a77, 0xbef1007c,
++	0xbef00080, 0xb8f02a05,
++	0x80708170, 0x8e708a70,
++	0x8e708170, 0xb8fa1605,
++	0x807a817a, 0x8e7a867a,
++	0x80707a70, 0xbef60084,
++	0xbef600ff, 0x01000000,
+ 	0xbefe007c, 0xbefc0070,
+-	0xc0611b3a, 0x0000007c,
++	0xc0611c7a, 0x0000007c,
+ 	0xbf8cc07f, 0x80708470,
+ 	0xbefc007e, 0xbefe007c,
+-	0xbefc0070, 0xc0611b7a,
++	0xbefc0070, 0xc0611b3a,
+ 	0x0000007c, 0xbf8cc07f,
+ 	0x80708470, 0xbefc007e,
+ 	0xbefe007c, 0xbefc0070,
+-	0xc0611bba, 0x0000007c,
++	0xc0611b7a, 0x0000007c,
+ 	0xbf8cc07f, 0x80708470,
+ 	0xbefc007e, 0xbefe007c,
+-	0xbefc0070, 0xc0611bfa,
++	0xbefc0070, 0xc0611bba,
+ 	0x0000007c, 0xbf8cc07f,
+ 	0x80708470, 0xbefc007e,
+ 	0xbefe007c, 0xbefc0070,
+-	0xc0611e3a, 0x0000007c,
+-	0xbf8cc07f, 0x80708470,
+-	0xbefc007e, 0xb8fbf803,
+-	0xbefe007c, 0xbefc0070,
+-	0xc0611efa, 0x0000007c,
++	0xc0611bfa, 0x0000007c,
+ 	0xbf8cc07f, 0x80708470,
+ 	0xbefc007e, 0xbefe007c,
+-	0xbefc0070, 0xc0611a3a,
++	0xbefc0070, 0xc0611e3a,
++	0x0000007c, 0xbf8cc07f,
++	0x80708470, 0xbefc007e,
++	0xb8fbf803, 0xbefe007c,
++	0xbefc0070, 0xc0611efa,
+ 	0x0000007c, 0xbf8cc07f,
+ 	0x80708470, 0xbefc007e,
+ 	0xbefe007c, 0xbefc0070,
+-	0xc0611a7a, 0x0000007c,
+-	0xbf8cc07f, 0x80708470,
+-	0xbefc007e, 0xb8f1f801,
+-	0xbefe007c, 0xbefc0070,
+-	0xc0611c7a, 0x0000007c,
++	0xc0611a3a, 0x0000007c,
+ 	0xbf8cc07f, 0x80708470,
+-	0xbefc007e, 0x867aff7f,
+-	0x04000000, 0xbeef0080,
+-	0x876f6f7a, 0xb8f02a05,
+-	0x80708170, 0x8e708a70,
+-	0x8e708170, 0xb8fb1605,
+-	0x807b817b, 0x8e7b847b,
+-	0x8e76827b, 0xbef600ff,
+-	0x01000000, 0xbef20174,
+-	0x80747074, 0x82758075,
+-	0xbefc0080, 0xbf800000,
+-	0xbe802b00, 0xbe822b02,
+-	0xbe842b04, 0xbe862b06,
+-	0xbe882b08, 0xbe8a2b0a,
+-	0xbe8c2b0c, 0xbe8e2b0e,
+-	0xc06b003a, 0x00000000,
+-	0xbf8cc07f, 0xc06b013a,
+-	0x00000010, 0xbf8cc07f,
+-	0xc06b023a, 0x00000020,
+-	0xbf8cc07f, 0xc06b033a,
+-	0x00000030, 0xbf8cc07f,
+-	0x8074c074, 0x82758075,
+-	0x807c907c, 0xbf0a7b7c,
+-	0xbf85ffe7, 0xbef40172,
+-	0xbef00080, 0xbefe00c1,
+-	0xbeff00c1, 0xbee80080,
+-	0xbee90080, 0xbef600ff,
+-	0x01000000, 0x867aff78,
+-	0x00400000, 0xbf850003,
+-	0xb8faf803, 0x897a7aff,
+-	0x10000000, 0xbf85004d,
+-	0xbe840080, 0xd2890000,
+-	0x00000900, 0x80048104,
+-	0xd2890001, 0x00000900,
+-	0x80048104, 0xd2890002,
+-	0x00000900, 0x80048104,
+-	0xd2890003, 0x00000900,
+-	0x80048104, 0xc069003a,
+-	0x00000070, 0xbf8cc07f,
+-	0x80709070, 0xbf06c004,
+-	0xbf84ffee, 0xbe840080,
+-	0xd2890000, 0x00000901,
+-	0x80048104, 0xd2890001,
+-	0x00000901, 0x80048104,
+-	0xd2890002, 0x00000901,
+-	0x80048104, 0xd2890003,
+-	0x00000901, 0x80048104,
+-	0xc069003a, 0x00000070,
+-	0xbf8cc07f, 0x80709070,
+-	0xbf06c004, 0xbf84ffee,
+-	0xbe840080, 0xd2890000,
+-	0x00000902, 0x80048104,
+-	0xd2890001, 0x00000902,
+-	0x80048104, 0xd2890002,
+-	0x00000902, 0x80048104,
+-	0xd2890003, 0x00000902,
+-	0x80048104, 0xc069003a,
+-	0x00000070, 0xbf8cc07f,
+-	0x80709070, 0xbf06c004,
+-	0xbf84ffee, 0xbe840080,
+-	0xd2890000, 0x00000903,
+-	0x80048104, 0xd2890001,
+-	0x00000903, 0x80048104,
+-	0xd2890002, 0x00000903,
+-	0x80048104, 0xd2890003,
+-	0x00000903, 0x80048104,
+-	0xc069003a, 0x00000070,
+-	0xbf8cc07f, 0x80709070,
+-	0xbf06c004, 0xbf84ffee,
+-	0xbf820008, 0xe0724000,
+-	0x701d0000, 0xe0724100,
+-	0x701d0100, 0xe0724200,
+-	0x701d0200, 0xe0724300,
+-	0x701d0300, 0xbefe00c1,
+-	0xbeff00c1, 0xb8fb4306,
+-	0x867bc17b, 0xbf840064,
+-	0xbf8a0000, 0x867aff6f,
+-	0x04000000, 0xbf840060,
+-	0x8e7b867b, 0x8e7b827b,
+-	0xbef6007b, 0xb8f02a05,
+-	0x80708170, 0x8e708a70,
+-	0x8e708170, 0xb8fa1605,
+-	0x807a817a, 0x8e7a867a,
+-	0x80707a70, 0x8070ff70,
+-	0x00000080, 0xbef600ff,
+-	0x01000000, 0xbefc0080,
+-	0xd28c0002, 0x000100c1,
+-	0xd28d0003, 0x000204c1,
+-	0x867aff78, 0x00400000,
+-	0xbf850003, 0xb8faf803,
+-	0x897a7aff, 0x10000000,
+-	0xbf850030, 0x24040682,
+-	0xd86e4000, 0x00000002,
+-	0xbf8cc07f, 0xbe840080,
+-	0xd2890000, 0x00000900,
+-	0x80048104, 0xd2890001,
+-	0x00000900, 0x80048104,
+-	0xd2890002, 0x00000900,
+-	0x80048104, 0xd2890003,
+-	0x00000900, 0x80048104,
+-	0xc069003a, 0x00000070,
+-	0xbf8cc07f, 0x80709070,
+-	0xbf06c004, 0xbf84ffee,
+-	0xbe840080, 0xd2890000,
+-	0x00000901, 0x80048104,
+-	0xd2890001, 0x00000901,
+-	0x80048104, 0xd2890002,
+-	0x00000901, 0x80048104,
+-	0xd2890003, 0x00000901,
+-	0x80048104, 0xc069003a,
+-	0x00000070, 0xbf8cc07f,
+-	0x80709070, 0xbf06c004,
+-	0xbf84ffee, 0x680404ff,
+-	0x00000200, 0xd0c9006a,
+-	0x0000f702, 0xbf87ffd2,
+-	0xbf820015, 0xd1060002,
+-	0x00011103, 0x7e0602ff,
+-	0x00000200, 0xbefc00ff,
+-	0x00010000, 0xbe800077,
+-	0x8677ff77, 0xff7fffff,
+-	0x8777ff77, 0x00058000,
+-	0xd8ec0000, 0x00000002,
+-	0xbf8cc07f, 0xe0765000,
+-	0x701d0002, 0x68040702,
+-	0xd0c9006a, 0x0000f702,
+-	0xbf87fff7, 0xbef70000,
+-	0xbef000ff, 0x00000400,
++	0xbefc007e, 0xbefe007c,
++	0xbefc0070, 0xc0611a7a,
++	0x0000007c, 0xbf8cc07f,
++	0x80708470, 0xbefc007e,
++	0xb8f1f801, 0xbefe007c,
++	0xbefc0070, 0xc0611c7a,
++	0x0000007c, 0xbf8cc07f,
++	0x80708470, 0xbefc007e,
++	0x867aff7f, 0x04000000,
++	0xbeef0080, 0x876f6f7a,
++	0xb8f02a05, 0x80708170,
++	0x8e708a70, 0x8e708170,
++	0xb8fb1605, 0x807b817b,
++	0x8e7b847b, 0x8e76827b,
++	0xbef600ff, 0x01000000,
++	0xbef20174, 0x80747074,
++	0x82758075, 0xbefc0080,
++	0xbf800000, 0xbe802b00,
++	0xbe822b02, 0xbe842b04,
++	0xbe862b06, 0xbe882b08,
++	0xbe8a2b0a, 0xbe8c2b0c,
++	0xbe8e2b0e, 0xc06b003a,
++	0x00000000, 0xbf8cc07f,
++	0xc06b013a, 0x00000010,
++	0xbf8cc07f, 0xc06b023a,
++	0x00000020, 0xbf8cc07f,
++	0xc06b033a, 0x00000030,
++	0xbf8cc07f, 0x8074c074,
++	0x82758075, 0x807c907c,
++	0xbf0a7b7c, 0xbf85ffe7,
++	0xbef40172, 0xbef00080,
+ 	0xbefe00c1, 0xbeff00c1,
+-	0xb8fb2a05, 0x807b817b,
+-	0x8e7b827b, 0x8e76887b,
++	0xbee80080, 0xbee90080,
+ 	0xbef600ff, 0x01000000,
+-	0xbefc0084, 0xbf0a7b7c,
+-	0xbf84006d, 0xbf11017c,
+-	0x807bff7b, 0x00001000,
+ 	0x867aff78, 0x00400000,
+ 	0xbf850003, 0xb8faf803,
+ 	0x897a7aff, 0x10000000,
+-	0xbf850051, 0xbe840080,
++	0xbf85004d, 0xbe840080,
+ 	0xd2890000, 0x00000900,
+ 	0x80048104, 0xd2890001,
+ 	0x00000900, 0x80048104,
+@@ -1253,208 +1154,315 @@ static const uint32_t cwsr_trap_arcturus_hex[] = {
+ 	0x80048104, 0xc069003a,
+ 	0x00000070, 0xbf8cc07f,
+ 	0x80709070, 0xbf06c004,
+-	0xbf84ffee, 0x807c847c,
+-	0xbf0a7b7c, 0xbf85ffb1,
+-	0xbf9c0000, 0xbf820012,
+-	0x7e000300, 0x7e020301,
+-	0x7e040302, 0x7e060303,
++	0xbf84ffee, 0xbf820008,
+ 	0xe0724000, 0x701d0000,
+ 	0xe0724100, 0x701d0100,
+ 	0xe0724200, 0x701d0200,
+ 	0xe0724300, 0x701d0300,
+-	0x807c847c, 0x8070ff70,
+-	0x00000400, 0xbf0a7b7c,
+-	0xbf85ffef, 0xbf9c0000,
+-	0xbefc0080, 0xbf11017c,
+-	0x867aff78, 0x00400000,
+-	0xbf850003, 0xb8faf803,
+-	0x897a7aff, 0x10000000,
+-	0xbf850059, 0xd3d84000,
+-	0x18000100, 0xd3d84001,
+-	0x18000101, 0xd3d84002,
+-	0x18000102, 0xd3d84003,
+-	0x18000103, 0xbe840080,
+-	0xd2890000, 0x00000900,
+-	0x80048104, 0xd2890001,
++	0xbefe00c1, 0xbeff00c1,
++	0xb8fb4306, 0x867bc17b,
++	0xbf840064, 0xbf8a0000,
++	0x867aff6f, 0x04000000,
++	0xbf840060, 0x8e7b867b,
++	0x8e7b827b, 0xbef6007b,
++	0xb8f02a05, 0x80708170,
++	0x8e708a70, 0x8e708170,
++	0xb8fa1605, 0x807a817a,
++	0x8e7a867a, 0x80707a70,
++	0x8070ff70, 0x00000080,
++	0xbef600ff, 0x01000000,
++	0xbefc0080, 0xd28c0002,
++	0x000100c1, 0xd28d0003,
++	0x000204c1, 0x867aff78,
++	0x00400000, 0xbf850003,
++	0xb8faf803, 0x897a7aff,
++	0x10000000, 0xbf850030,
++	0x24040682, 0xd86e4000,
++	0x00000002, 0xbf8cc07f,
++	0xbe840080, 0xd2890000,
+ 	0x00000900, 0x80048104,
+-	0xd2890002, 0x00000900,
+-	0x80048104, 0xd2890003,
++	0xd2890001, 0x00000900,
++	0x80048104, 0xd2890002,
+ 	0x00000900, 0x80048104,
++	0xd2890003, 0x00000900,
++	0x80048104, 0xc069003a,
++	0x00000070, 0xbf8cc07f,
++	0x80709070, 0xbf06c004,
++	0xbf84ffee, 0xbe840080,
++	0xd2890000, 0x00000901,
++	0x80048104, 0xd2890001,
++	0x00000901, 0x80048104,
++	0xd2890002, 0x00000901,
++	0x80048104, 0xd2890003,
++	0x00000901, 0x80048104,
+ 	0xc069003a, 0x00000070,
+ 	0xbf8cc07f, 0x80709070,
+ 	0xbf06c004, 0xbf84ffee,
++	0x680404ff, 0x00000200,
++	0xd0c9006a, 0x0000f702,
++	0xbf87ffd2, 0xbf820015,
++	0xd1060002, 0x00011103,
++	0x7e0602ff, 0x00000200,
++	0xbefc00ff, 0x00010000,
++	0xbe800077, 0x8677ff77,
++	0xff7fffff, 0x8777ff77,
++	0x00058000, 0xd8ec0000,
++	0x00000002, 0xbf8cc07f,
++	0xe0765000, 0x701d0002,
++	0x68040702, 0xd0c9006a,
++	0x0000f702, 0xbf87fff7,
++	0xbef70000, 0xbef000ff,
++	0x00000400, 0xbefe00c1,
++	0xbeff00c1, 0xb8fb2a05,
++	0x807b817b, 0x8e7b827b,
++	0x8e76887b, 0xbef600ff,
++	0x01000000, 0xbefc0084,
++	0xbf0a7b7c, 0xbf84006d,
++	0xbf11017c, 0x807bff7b,
++	0x00001000, 0x867aff78,
++	0x00400000, 0xbf850003,
++	0xb8faf803, 0x897a7aff,
++	0x10000000, 0xbf850051,
+ 	0xbe840080, 0xd2890000,
+-	0x00000901, 0x80048104,
+-	0xd2890001, 0x00000901,
++	0x00000900, 0x80048104,
++	0xd2890001, 0x00000900,
+ 	0x80048104, 0xd2890002,
+-	0x00000901, 0x80048104,
+-	0xd2890003, 0x00000901,
++	0x00000900, 0x80048104,
++	0xd2890003, 0x00000900,
+ 	0x80048104, 0xc069003a,
+ 	0x00000070, 0xbf8cc07f,
+ 	0x80709070, 0xbf06c004,
+ 	0xbf84ffee, 0xbe840080,
+-	0xd2890000, 0x00000902,
++	0xd2890000, 0x00000901,
+ 	0x80048104, 0xd2890001,
+-	0x00000902, 0x80048104,
+-	0xd2890002, 0x00000902,
++	0x00000901, 0x80048104,
++	0xd2890002, 0x00000901,
+ 	0x80048104, 0xd2890003,
+-	0x00000902, 0x80048104,
++	0x00000901, 0x80048104,
+ 	0xc069003a, 0x00000070,
+ 	0xbf8cc07f, 0x80709070,
+ 	0xbf06c004, 0xbf84ffee,
+ 	0xbe840080, 0xd2890000,
+-	0x00000903, 0x80048104,
+-	0xd2890001, 0x00000903,
++	0x00000902, 0x80048104,
++	0xd2890001, 0x00000902,
+ 	0x80048104, 0xd2890002,
+-	0x00000903, 0x80048104,
+-	0xd2890003, 0x00000903,
++	0x00000902, 0x80048104,
++	0xd2890003, 0x00000902,
+ 	0x80048104, 0xc069003a,
+ 	0x00000070, 0xbf8cc07f,
+ 	0x80709070, 0xbf06c004,
+-	0xbf84ffee, 0x807c847c,
+-	0xbf0a7b7c, 0xbf85ffa9,
+-	0xbf9c0000, 0xbf820016,
++	0xbf84ffee, 0xbe840080,
++	0xd2890000, 0x00000903,
++	0x80048104, 0xd2890001,
++	0x00000903, 0x80048104,
++	0xd2890002, 0x00000903,
++	0x80048104, 0xd2890003,
++	0x00000903, 0x80048104,
++	0xc069003a, 0x00000070,
++	0xbf8cc07f, 0x80709070,
++	0xbf06c004, 0xbf84ffee,
++	0x807c847c, 0xbf0a7b7c,
++	0xbf85ffb1, 0xbf9c0000,
++	0xbf820012, 0x7e000300,
++	0x7e020301, 0x7e040302,
++	0x7e060303, 0xe0724000,
++	0x701d0000, 0xe0724100,
++	0x701d0100, 0xe0724200,
++	0x701d0200, 0xe0724300,
++	0x701d0300, 0x807c847c,
++	0x8070ff70, 0x00000400,
++	0xbf0a7b7c, 0xbf85ffef,
++	0xbf9c0000, 0xbefc0080,
++	0xbf11017c, 0x867aff78,
++	0x00400000, 0xbf850003,
++	0xb8faf803, 0x897a7aff,
++	0x10000000, 0xbf850059,
+ 	0xd3d84000, 0x18000100,
+ 	0xd3d84001, 0x18000101,
+ 	0xd3d84002, 0x18000102,
+ 	0xd3d84003, 0x18000103,
+-	0xe0724000, 0x701d0000,
+-	0xe0724100, 0x701d0100,
+-	0xe0724200, 0x701d0200,
+-	0xe0724300, 0x701d0300,
+-	0x807c847c, 0x8070ff70,
+-	0x00000400, 0xbf0a7b7c,
+-	0xbf85ffeb, 0xbf9c0000,
+-	0xbf820106, 0xbef4007e,
+-	0x8675ff7f, 0x0000ffff,
+-	0x8775ff75, 0x00040000,
+-	0xbef60080, 0xbef700ff,
+-	0x00807fac, 0x866eff7f,
+-	0x08000000, 0x8f6e836e,
+-	0x87776e77, 0x866eff7f,
+-	0x70000000, 0x8f6e816e,
+-	0x87776e77, 0x866eff7f,
+-	0x04000000, 0xbf84001f,
+-	0xbefe00c1, 0xbeff00c1,
+-	0xb8ef4306, 0x866fc16f,
+-	0xbf84001a, 0x8e6f866f,
+-	0x8e6f826f, 0xbef6006f,
+-	0xb8f82a05, 0x80788178,
+-	0x8e788a78, 0x8e788178,
+-	0xb8ee1605, 0x806e816e,
+-	0x8e6e866e, 0x80786e78,
+-	0x8078ff78, 0x00000080,
++	0xbe840080, 0xd2890000,
++	0x00000900, 0x80048104,
++	0xd2890001, 0x00000900,
++	0x80048104, 0xd2890002,
++	0x00000900, 0x80048104,
++	0xd2890003, 0x00000900,
++	0x80048104, 0xc069003a,
++	0x00000070, 0xbf8cc07f,
++	0x80709070, 0xbf06c004,
++	0xbf84ffee, 0xbe840080,
++	0xd2890000, 0x00000901,
++	0x80048104, 0xd2890001,
++	0x00000901, 0x80048104,
++	0xd2890002, 0x00000901,
++	0x80048104, 0xd2890003,
++	0x00000901, 0x80048104,
++	0xc069003a, 0x00000070,
++	0xbf8cc07f, 0x80709070,
++	0xbf06c004, 0xbf84ffee,
++	0xbe840080, 0xd2890000,
++	0x00000902, 0x80048104,
++	0xd2890001, 0x00000902,
++	0x80048104, 0xd2890002,
++	0x00000902, 0x80048104,
++	0xd2890003, 0x00000902,
++	0x80048104, 0xc069003a,
++	0x00000070, 0xbf8cc07f,
++	0x80709070, 0xbf06c004,
++	0xbf84ffee, 0xbe840080,
++	0xd2890000, 0x00000903,
++	0x80048104, 0xd2890001,
++	0x00000903, 0x80048104,
++	0xd2890002, 0x00000903,
++	0x80048104, 0xd2890003,
++	0x00000903, 0x80048104,
++	0xc069003a, 0x00000070,
++	0xbf8cc07f, 0x80709070,
++	0xbf06c004, 0xbf84ffee,
++	0x807c847c, 0xbf0a7b7c,
++	0xbf85ffa9, 0xbf9c0000,
++	0xbf820016, 0xd3d84000,
++	0x18000100, 0xd3d84001,
++	0x18000101, 0xd3d84002,
++	0x18000102, 0xd3d84003,
++	0x18000103, 0xe0724000,
++	0x701d0000, 0xe0724100,
++	0x701d0100, 0xe0724200,
++	0x701d0200, 0xe0724300,
++	0x701d0300, 0x807c847c,
++	0x8070ff70, 0x00000400,
++	0xbf0a7b7c, 0xbf85ffeb,
++	0xbf9c0000, 0xbf820106,
++	0xbef4007e, 0x8675ff7f,
++	0x0000ffff, 0x8775ff75,
++	0x00040000, 0xbef60080,
++	0xbef700ff, 0x00807fac,
++	0x866eff7f, 0x08000000,
++	0x8f6e836e, 0x87776e77,
++	0x866eff7f, 0x70000000,
++	0x8f6e816e, 0x87776e77,
++	0x866eff7f, 0x04000000,
++	0xbf84001f, 0xbefe00c1,
++	0xbeff00c1, 0xb8ef4306,
++	0x866fc16f, 0xbf84001a,
++	0x8e6f866f, 0x8e6f826f,
++	0xbef6006f, 0xb8f82a05,
++	0x80788178, 0x8e788a78,
++	0x8e788178, 0xb8ee1605,
++	0x806e816e, 0x8e6e866e,
++	0x80786e78, 0x8078ff78,
++	0x00000080, 0xbef600ff,
++	0x01000000, 0xbefc0080,
++	0xe0510000, 0x781d0000,
++	0xe0510100, 0x781d0000,
++	0x807cff7c, 0x00000200,
++	0x8078ff78, 0x00000200,
++	0xbf0a6f7c, 0xbf85fff6,
++	0xbef80080, 0xbefe00c1,
++	0xbeff00c1, 0xb8ef2a05,
++	0x806f816f, 0x8e6f826f,
++	0x8e76886f, 0xbef90076,
+ 	0xbef600ff, 0x01000000,
+-	0xbefc0080, 0xe0510000,
+-	0x781d0000, 0xe0510100,
+-	0x781d0000, 0x807cff7c,
+-	0x00000200, 0x8078ff78,
+-	0x00000200, 0xbf0a6f7c,
+-	0xbf85fff6, 0xbef80080,
+-	0xbefe00c1, 0xbeff00c1,
+-	0xb8ef2a05, 0x806f816f,
+-	0x8e6f826f, 0x8e76886f,
+-	0xbef90076, 0xbef600ff,
+-	0x01000000, 0xbeee0078,
+-	0x8078ff78, 0x00000400,
+-	0xbef30079, 0x8079ff79,
+-	0x00000400, 0xbefc0084,
+-	0xbf11087c, 0x806fff6f,
+-	0x00008000, 0xe0524000,
+-	0x791d0000, 0xe0524100,
+-	0x791d0100, 0xe0524200,
+-	0x791d0200, 0xe0524300,
+-	0x791d0300, 0x8079ff79,
+-	0x00000400, 0xbf8c0f70,
+-	0xd3d94000, 0x18000100,
+-	0xd3d94001, 0x18000101,
+-	0xd3d94002, 0x18000102,
+-	0xd3d94003, 0x18000103,
+-	0xe0524000, 0x781d0000,
+-	0xe0524100, 0x781d0100,
+-	0xe0524200, 0x781d0200,
+-	0xe0524300, 0x781d0300,
+-	0xbf8c0f70, 0x7e000300,
+-	0x7e020301, 0x7e040302,
+-	0x7e060303, 0x807c847c,
+-	0x8078ff78, 0x00000400,
+-	0xbf0a6f7c, 0xbf85ffdb,
+-	0xbf9c0000, 0xe0524000,
+-	0x731d0000, 0xe0524100,
+-	0x731d0100, 0xe0524200,
+-	0x731d0200, 0xe0524300,
+-	0x731d0300, 0xbf8c0f70,
+-	0xd3d94000, 0x18000100,
+-	0xd3d94001, 0x18000101,
+-	0xd3d94002, 0x18000102,
+-	0xd3d94003, 0x18000103,
+-	0xe0524000, 0x6e1d0000,
+-	0xe0524100, 0x6e1d0100,
+-	0xe0524200, 0x6e1d0200,
+-	0xe0524300, 0x6e1d0300,
+-	0xb8f82a05, 0x80788178,
+-	0x8e788a78, 0x8e788178,
+-	0xb8ee1605, 0x806e816e,
+-	0x8e6e866e, 0x80786e78,
+-	0x80f8c078, 0xb8ef1605,
+-	0x806f816f, 0x8e6f846f,
+-	0x8e76826f, 0xbef600ff,
+-	0x01000000, 0xbefc006f,
+-	0xc031003a, 0x00000078,
+-	0x80f8c078, 0xbf8cc07f,
+-	0x80fc907c, 0xbf800000,
+-	0xbe802d00, 0xbe822d02,
+-	0xbe842d04, 0xbe862d06,
+-	0xbe882d08, 0xbe8a2d0a,
+-	0xbe8c2d0c, 0xbe8e2d0e,
+-	0xbf06807c, 0xbf84fff0,
+-	0xb8f82a05, 0x80788178,
+-	0x8e788a78, 0x8e788178,
+-	0xb8ee1605, 0x806e816e,
+-	0x8e6e866e, 0x80786e78,
+-	0xbef60084, 0xbef600ff,
+-	0x01000000, 0xc0211bfa,
++	0xbeee0078, 0x8078ff78,
++	0x00000400, 0xbef30079,
++	0x8079ff79, 0x00000400,
++	0xbefc0084, 0xbf11087c,
++	0x806fff6f, 0x00008000,
++	0xe0524000, 0x791d0000,
++	0xe0524100, 0x791d0100,
++	0xe0524200, 0x791d0200,
++	0xe0524300, 0x791d0300,
++	0x8079ff79, 0x00000400,
++	0xbf8c0f70, 0xd3d94000,
++	0x18000100, 0xd3d94001,
++	0x18000101, 0xd3d94002,
++	0x18000102, 0xd3d94003,
++	0x18000103, 0xe0524000,
++	0x781d0000, 0xe0524100,
++	0x781d0100, 0xe0524200,
++	0x781d0200, 0xe0524300,
++	0x781d0300, 0xbf8c0f70,
++	0x7e000300, 0x7e020301,
++	0x7e040302, 0x7e060303,
++	0x807c847c, 0x8078ff78,
++	0x00000400, 0xbf0a6f7c,
++	0xbf85ffdb, 0xbf9c0000,
++	0xe0524000, 0x731d0000,
++	0xe0524100, 0x731d0100,
++	0xe0524200, 0x731d0200,
++	0xe0524300, 0x731d0300,
++	0xbf8c0f70, 0xd3d94000,
++	0x18000100, 0xd3d94001,
++	0x18000101, 0xd3d94002,
++	0x18000102, 0xd3d94003,
++	0x18000103, 0xe0524000,
++	0x6e1d0000, 0xe0524100,
++	0x6e1d0100, 0xe0524200,
++	0x6e1d0200, 0xe0524300,
++	0x6e1d0300, 0xb8f82a05,
++	0x80788178, 0x8e788a78,
++	0x8e788178, 0xb8ee1605,
++	0x806e816e, 0x8e6e866e,
++	0x80786e78, 0x80f8c078,
++	0xb8ef1605, 0x806f816f,
++	0x8e6f846f, 0x8e76826f,
++	0xbef600ff, 0x01000000,
++	0xbefc006f, 0xc031003a,
++	0x00000078, 0x80f8c078,
++	0xbf8cc07f, 0x80fc907c,
++	0xbf800000, 0xbe802d00,
++	0xbe822d02, 0xbe842d04,
++	0xbe862d06, 0xbe882d08,
++	0xbe8a2d0a, 0xbe8c2d0c,
++	0xbe8e2d0e, 0xbf06807c,
++	0xbf84fff0, 0xb8f82a05,
++	0x80788178, 0x8e788a78,
++	0x8e788178, 0xb8ee1605,
++	0x806e816e, 0x8e6e866e,
++	0x80786e78, 0xbef60084,
++	0xbef600ff, 0x01000000,
++	0xc0211bfa, 0x00000078,
++	0x80788478, 0xc0211b3a,
+ 	0x00000078, 0x80788478,
+-	0xc0211b3a, 0x00000078,
+-	0x80788478, 0xc0211b7a,
++	0xc0211b7a, 0x00000078,
++	0x80788478, 0xc0211c3a,
+ 	0x00000078, 0x80788478,
+-	0xc0211c3a, 0x00000078,
+-	0x80788478, 0xc0211c7a,
++	0xc0211c7a, 0x00000078,
++	0x80788478, 0xc0211eba,
+ 	0x00000078, 0x80788478,
+-	0xc0211eba, 0x00000078,
+-	0x80788478, 0xc0211efa,
++	0xc0211efa, 0x00000078,
++	0x80788478, 0xc0211a3a,
+ 	0x00000078, 0x80788478,
+-	0xc0211a3a, 0x00000078,
+-	0x80788478, 0xc0211a7a,
++	0xc0211a7a, 0x00000078,
++	0x80788478, 0xc0211cfa,
+ 	0x00000078, 0x80788478,
+-	0xc0211cfa, 0x00000078,
+-	0x80788478, 0xbf8cc07f,
+-	0xbefc006f, 0xbefe0070,
+-	0xbeff0071, 0x866f7bff,
+-	0x000003ff, 0xb96f4803,
+-	0x866f7bff, 0xfffff800,
+-	0x8f6f8b6f, 0xb96fa2c3,
+-	0xb973f801, 0xb8ee2a05,
+-	0x806e816e, 0x8e6e8a6e,
+-	0x8e6e816e, 0xb8ef1605,
+-	0x806f816f, 0x8e6f866f,
+-	0x806e6f6e, 0x806e746e,
+-	0x826f8075, 0x866fff6f,
+-	0x0000ffff, 0xc00b1c37,
+-	0x00000050, 0xc00b1d37,
+-	0x00000060, 0xc0031e77,
+-	0x00000074, 0xbf8cc07f,
+-	0x866fff6d, 0xf8000000,
+-	0x8f6f9b6f, 0x8e6f906f,
+-	0xbeee0080, 0x876e6f6e,
+-	0x866fff6d, 0x04000000,
+-	0x8f6f9a6f, 0x8e6f8f6f,
+-	0x876e6f6e, 0x866fff7a,
+-	0x00800000, 0x8f6f976f,
+-	0xb96ef807, 0x866dff6d,
+-	0x0000ffff, 0x86fe7e7e,
+-	0x86ea6a6a, 0x8f6e837a,
+-	0xb96ee0c2, 0xbf800002,
+-	0xb97a0002, 0xbf8a0000,
+-	0x95806f6c, 0xbf810000,
++	0xbf8cc07f, 0xbefc006f,
++	0xbefe0070, 0xbeff0071,
++	0x866f7bff, 0x000003ff,
++	0xb96f4803, 0x866f7bff,
++	0xfffff800, 0x8f6f8b6f,
++	0xb96fa2c3, 0xb973f801,
++	0xb8ee2a05, 0x806e816e,
++	0x8e6e8a6e, 0x8e6e816e,
++	0xb8ef1605, 0x806f816f,
++	0x8e6f866f, 0x806e6f6e,
++	0x806e746e, 0x826f8075,
++	0x866fff6f, 0x0000ffff,
++	0xc00b1c37, 0x00000050,
++	0xc00b1d37, 0x00000060,
++	0xc0031e77, 0x00000074,
++	0xbf8cc07f, 0x866fff6d,
++	0xf8000000, 0x8f6f9b6f,
++	0x8e6f906f, 0xbeee0080,
++	0x876e6f6e, 0x866fff6d,
++	0x04000000, 0x8f6f9a6f,
++	0x8e6f8f6f, 0x876e6f6e,
++	0x866fff7a, 0x00800000,
++	0x8f6f976f, 0xb96ef807,
++	0x866dff6d, 0x0000ffff,
++	0x86fe7e7e, 0x86ea6a6a,
++	0x8f6e837a, 0xb96ee0c2,
++	0xbf800002, 0xb97a0002,
++	0xbf8a0000, 0x95806f6c,
++	0xbf810000, 0x00000000,
+ };
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
+index 4d146bca0b05..cee4cfd5182d 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
+@@ -95,6 +95,7 @@ var USE_MTBUF_INSTEAD_OF_MUBUF	    =	0		    //because TC EMU currently asserts o
+ var SWIZZLE_EN			    =	0		    //whether we use swizzled buffer addressing
+ var ACK_SQC_STORE		    =	1		    //workaround for suspected SQC store bug causing incorrect stores under concurrency
+ var SAVE_AFTER_XNACK_ERROR	    =	1		    //workaround for TCP store failure after XNACK error when ALLOW_REPLAY=0, for debugger
++var SINGLE_STEP_MISSED_WORKAROUND   =	1		    //workaround for lost MODE.DEBUG_EN exception when SAVECTX raised
+ 
+ /**************************************************************************/
+ /*			variables					  */
+@@ -136,6 +137,8 @@ var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT	=   15			//FIXME
+ var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK	= 0x1F8000
+ var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG	= 0x00007FFF	//FIXME
+ 
++var SQ_WAVE_MODE_DEBUG_EN_MASK		=   0x800
++
+ var SQ_BUF_RSRC_WORD1_ATC_SHIFT	    =	24
+ var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT   =	27
+ 
+@@ -253,6 +256,23 @@ L_SKIP_RESTORE:
+ 
+     s_getreg_b32    s_save_status, hwreg(HW_REG_STATUS)				    //save STATUS since we will change SCC
+     s_andn2_b32	    s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK	    //check whether this is for save
++
++if SINGLE_STEP_MISSED_WORKAROUND
++    // No single step exceptions if MODE.DEBUG_EN=0.
++    s_getreg_b32    ttmp2, hwreg(HW_REG_MODE)
++    s_and_b32       ttmp2, ttmp2, SQ_WAVE_MODE_DEBUG_EN_MASK
++    s_cbranch_scc0  L_NO_SINGLE_STEP_WORKAROUND
++
++    // Second-level trap already handled exception if STATUS.HALT=1.
++    s_and_b32       ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK
++
++    // Prioritize single step exception over context save.
++    // Second-level trap will halt wave and RFE, re-entering for SAVECTX.
++    s_cbranch_scc0  L_FETCH_2ND_TRAP
++
++L_NO_SINGLE_STEP_WORKAROUND:
++end
++
+     s_getreg_b32    s_save_trapsts, hwreg(HW_REG_TRAPSTS)
+     s_and_b32       ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK    //check whether this is for save
+     s_cbranch_scc1  L_SAVE					//this is the operation for save
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3119-drm-amdkfd-Replace-gfx10-trap-handler-with-correct-b.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3119-drm-amdkfd-Replace-gfx10-trap-handler-with-correct-b.patch
new file mode 100644
index 00000000..4821ab4b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3119-drm-amdkfd-Replace-gfx10-trap-handler-with-correct-b.patch
@@ -0,0 +1,2655 @@
+From 2a3d8424c1f5d22418083a272bff16dc3c79ed05 Mon Sep 17 00:00:00 2001
+From: Jay Cornwall <jay.cornwall@amd.com>
+Date: Wed, 24 Jul 2019 12:23:42 -0500
+Subject: [PATCH 3119/4256] drm/amdkfd: Replace gfx10 trap handler with correct
+ branch
+
+Previously submitted code was taken from an incorrect branch and
+was non-functional.
+
+Cc: Oak Zeng <oak.zeng@amd.com>
+Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-By: Oak Zeng <oak.zeng@amd.com>
+---
+ .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h    |  553 +++--
+ .../amd/amdkfd/cwsr_trap_handler_gfx10.asm    | 1978 ++++++++---------
+ 2 files changed, 1220 insertions(+), 1311 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+index 427594035597..2b3d7017f142 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+@@ -680,24 +680,47 @@ static const uint32_t cwsr_trap_gfx9_hex[] = {
+ };
+ 
+ static const uint32_t cwsr_trap_gfx10_hex[] = {
+-	0xbf820001, 0xbf82012e,
+-	0xb0804004, 0xb970f802,
+-	0x8a708670, 0xb971f803,
+-	0x8771ff71, 0x00000400,
+-	0xbf850008, 0xb971f803,
+-	0x8771ff71, 0x000001ff,
+-	0xbf850001, 0x806c846c,
++	0xbf820001, 0xbf8201b2,
++	0xb0804004, 0xb978f802,
++	0x8a788678, 0xb971f803,
++	0x876eff71, 0x00000400,
++	0xbf850033, 0x876eff71,
++	0x00000100, 0xbf840002,
++	0x8878ff78, 0x00002000,
++	0x8a77ff77, 0xff000000,
++	0xb96ef807, 0x876fff6e,
++	0x02000000, 0x8f6f866f,
++	0x88776f77, 0x876fff6e,
++	0x003f8000, 0x8f6f896f,
++	0x88776f77, 0x8a6eff6e,
++	0x023f8000, 0xb9eef807,
++	0xb970f812, 0xb971f813,
++	0x8ff08870, 0xf4051bb8,
++	0xfa000000, 0xbf8cc07f,
++	0xf4051c38, 0xfa000008,
++	0xbf8cc07f, 0x87ee6e6e,
++	0xbf840001, 0xbe80206e,
++	0xb971f803, 0x8771ff71,
++	0x000001ff, 0xbf850002,
++	0x806c846c, 0x826d806d,
++	0x876dff6d, 0x0000ffff,
++	0x906e8977, 0x876fff6e,
++	0x003f8000, 0x906e8677,
++	0x876eff6e, 0x02000000,
++	0x886e6f6e, 0xb9eef807,
++	0x87fe7e7e, 0x87ea6a6a,
++	0xb9f8f802, 0xbe80226c,
++	0xb971f803, 0x8771ff71,
++	0x00000100, 0xbf840006,
++	0xbef60380, 0xb9f60203,
+ 	0x876dff6d, 0x0000ffff,
+-	0xbe80226c, 0xb971f803,
+-	0x8771ff71, 0x00000100,
+-	0xbf840006, 0xbef60380,
+-	0xb9f60203, 0x876dff6d,
+-	0x0000ffff, 0x80ec886c,
+-	0x82ed806d, 0xbef60380,
+-	0xb9f60283, 0xb973f816,
+-	0xb9762c07, 0x8f769c76,
+-	0x886d766d, 0xb97603c7,
+-	0x8f769b76, 0x886d766d,
++	0x80ec886c, 0x82ed806d,
++	0xbef60380, 0xb9f60283,
++	0xb972f816, 0xb9762c07,
++	0x8f769a76, 0x886d766d,
++	0xb97603c7, 0x8f769976,
++	0x886d766d, 0xb9760647,
++	0x8f769876, 0x886d766d,
+ 	0xb976f807, 0x8776ff76,
+ 	0x00007fff, 0xb9f6f807,
+ 	0xbeee037e, 0xbeef037f,
+@@ -706,32 +729,167 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
+ 	0xbef4037e, 0x8775ff7f,
+ 	0x0000ffff, 0x8875ff75,
+ 	0x00040000, 0xbef60380,
+-	0xbef703ff, 0x00807fac,
++	0xbef703ff, 0x10807fac,
+ 	0x8776ff7f, 0x08000000,
+ 	0x90768376, 0x88777677,
+ 	0x8776ff7f, 0x70000000,
+ 	0x90768176, 0x88777677,
+ 	0xbefb037c, 0xbefa0380,
+-	0xb97202dc, 0x8872727f,
+-	0xbefe03c1, 0x877c8172,
++	0xb97302dc, 0x8f739973,
++	0x8873737f, 0xb97a2a05,
++	0x807a817a, 0x907c9973,
++	0x877c817c, 0xbf06817c,
++	0xbf850002, 0x8f7a897a,
++	0xbf820001, 0x8f7a8a7a,
++	0xb9761e06, 0x8f768a76,
++	0x807a767a, 0x807aff7a,
++	0x00000200, 0xbef603ff,
++	0x01000000, 0xbefe037c,
++	0xbefc037a, 0xf4611efa,
++	0xf8000000, 0x807a847a,
++	0xbefc037e, 0xbefe037c,
++	0xbefc037a, 0xf4611b3a,
++	0xf8000000, 0x807a847a,
++	0xbefc037e, 0xbefe037c,
++	0xbefc037a, 0xf4611b7a,
++	0xf8000000, 0x807a847a,
++	0xbefc037e, 0xbefe037c,
++	0xbefc037a, 0xf4611bba,
++	0xf8000000, 0x807a847a,
++	0xbefc037e, 0xbefe037c,
++	0xbefc037a, 0xf4611bfa,
++	0xf8000000, 0x807a847a,
++	0xbefc037e, 0xbefe037c,
++	0xbefc037a, 0xf4611e3a,
++	0xf8000000, 0x807a847a,
++	0xbefc037e, 0xb971f803,
++	0xbefe037c, 0xbefc037a,
++	0xf4611c7a, 0xf8000000,
++	0x807a847a, 0xbefc037e,
++	0xbefe037c, 0xbefc037a,
++	0xf4611cba, 0xf8000000,
++	0x807a847a, 0xbefc037e,
++	0xb97bf801, 0xbefe037c,
++	0xbefc037a, 0xf4611efa,
++	0xf8000000, 0x807a847a,
++	0xbefc037e, 0x8776ff7f,
++	0x04000000, 0xbeef0380,
++	0x886f6f76, 0xb97a2a05,
++	0x807a817a, 0x907c9973,
++	0x877c817c, 0xbf06817c,
++	0xbf850002, 0x8f7a897a,
++	0xbf820001, 0x8f7a8a7a,
++	0xb9761e06, 0x8f768a76,
++	0x807a767a, 0xbef603ff,
++	0x01000000, 0xbef20374,
++	0x80747a74, 0x82758075,
++	0xbefc0380, 0xbf800000,
++	0xbe802f00, 0xbe822f02,
++	0xbe842f04, 0xbe862f06,
++	0xbe882f08, 0xbe8a2f0a,
++	0xbe8c2f0c, 0xbe8e2f0e,
++	0xf469003a, 0xfa000000,
++	0xf469013a, 0xfa000010,
++	0xf469023a, 0xfa000020,
++	0xf469033a, 0xfa000030,
++	0x8074c074, 0x82758075,
++	0x807c907c, 0xbf0aff7c,
++	0x00000060, 0xbf85ffea,
++	0xbe802f00, 0xbe822f02,
++	0xbe842f04, 0xbe862f06,
++	0xbe882f08, 0xf469003a,
++	0xfa000000, 0xf469013a,
++	0xfa000010, 0xf465023a,
++	0xfa000020, 0x8074c074,
++	0x82758075, 0xbef40372,
++	0xbefa0380, 0xbefe03c1,
++	0x907c9973, 0x877c817c,
+ 	0xbf06817c, 0xbf850002,
+-	0xbeff0380, 0xbf820001,
+-	0xbeff03c1, 0xb9712a05,
+-	0x80718171, 0x8f718271,
+-	0x877c8172, 0xbf06817c,
+-	0xbf85000d, 0x8f768771,
++	0xbeff0380, 0xbf820002,
++	0xbeff03c1, 0xbf82000b,
+ 	0xbef603ff, 0x01000000,
+-	0xbefc0380, 0x7e008700,
+ 	0xe0704000, 0x7a5d0000,
+-	0x807c817c, 0x807aff7a,
+-	0x00000080, 0xbf0a717c,
+-	0xbf85fff8, 0xbf82001b,
+-	0x8f768871, 0xbef603ff,
+-	0x01000000, 0xbefc0380,
+-	0x7e008700, 0xe0704000,
+-	0x7a5d0000, 0x807c817c,
+-	0x807aff7a, 0x00000100,
+-	0xbf0a717c, 0xbf85fff8,
++	0xe0704080, 0x7a5d0100,
++	0xe0704100, 0x7a5d0200,
++	0xe0704180, 0x7a5d0300,
++	0xbf82000a, 0xbef603ff,
++	0x01000000, 0xe0704000,
++	0x7a5d0000, 0xe0704100,
++	0x7a5d0100, 0xe0704200,
++	0x7a5d0200, 0xe0704300,
++	0x7a5d0300, 0xbefe03c1,
++	0x907c9973, 0x877c817c,
++	0xbf06817c, 0xbf850002,
++	0xbeff0380, 0xbf820001,
++	0xbeff03c1, 0xb9714306,
++	0x8771c171, 0xbf840046,
++	0xbf8a0000, 0x8776ff6f,
++	0x04000000, 0xbf840042,
++	0x8f718671, 0x8f718271,
++	0xbef60371, 0xb97a2a05,
++	0x807a817a, 0x907c9973,
++	0x877c817c, 0xbf06817c,
++	0xbf850002, 0x8f7a897a,
++	0xbf820001, 0x8f7a8a7a,
++	0xb9761e06, 0x8f768a76,
++	0x807a767a, 0x807aff7a,
++	0x00000200, 0x807aff7a,
++	0x00000080, 0xbef603ff,
++	0x01000000, 0xd7650000,
++	0x000100c1, 0xd7660000,
++	0x000200c1, 0x16000084,
++	0x907c9973, 0x877c817c,
++	0xbf06817c, 0xbefc0380,
++	0xbf850012, 0xbe8303ff,
++	0x00000080, 0xbf800000,
++	0xbf800000, 0xbf800000,
++	0xd8d80000, 0x01000000,
++	0xbf8c0000, 0xe0704000,
++	0x7a5d0100, 0x807c037c,
++	0x807a037a, 0xd5250000,
++	0x0001ff00, 0x00000080,
++	0xbf0a717c, 0xbf85fff4,
++	0xbf820011, 0xbe8303ff,
++	0x00000100, 0xbf800000,
++	0xbf800000, 0xbf800000,
++	0xd8d80000, 0x01000000,
++	0xbf8c0000, 0xe0704000,
++	0x7a5d0100, 0x807c037c,
++	0x807a037a, 0xd5250000,
++	0x0001ff00, 0x00000100,
++	0xbf0a717c, 0xbf85fff4,
++	0xbefe03c1, 0x907c9973,
++	0x877c817c, 0xbf06817c,
++	0xbf850004, 0xbefa03ff,
++	0x00000200, 0xbeff0380,
++	0xbf820003, 0xbefa03ff,
++	0x00000400, 0xbeff03c1,
++	0xb9712a05, 0x80718171,
++	0x8f718271, 0x907c9973,
++	0x877c817c, 0xbf06817c,
++	0xbf850017, 0xbef603ff,
++	0x01000000, 0xbefc0384,
++	0xbf0a717c, 0xbf840037,
++	0x7e008700, 0x7e028701,
++	0x7e048702, 0x7e068703,
++	0xe0704000, 0x7a5d0000,
++	0xe0704080, 0x7a5d0100,
++	0xe0704100, 0x7a5d0200,
++	0xe0704180, 0x7a5d0300,
++	0x807c847c, 0x807aff7a,
++	0x00000200, 0xbf0a717c,
++	0xbf85ffef, 0xbf820025,
++	0xbef603ff, 0x01000000,
++	0xbefc0384, 0xbf0a717c,
++	0xbf840020, 0x7e008700,
++	0x7e028701, 0x7e048702,
++	0x7e068703, 0xe0704000,
++	0x7a5d0000, 0xe0704100,
++	0x7a5d0100, 0xe0704200,
++	0x7a5d0200, 0xe0704300,
++	0x7a5d0300, 0x807c847c,
++	0x807aff7a, 0x00000400,
++	0xbf0a717c, 0xbf85ffef,
+ 	0xb9711e06, 0x8771c171,
+ 	0xbf84000c, 0x8f718371,
+ 	0x80717c71, 0xbefe03c1,
+@@ -739,133 +897,82 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
+ 	0xe0704000, 0x7a5d0000,
+ 	0x807c817c, 0x807aff7a,
+ 	0x00000080, 0xbf0a717c,
+-	0xbf85fff8, 0xbf8a0000,
+-	0x8776ff72, 0x04000000,
+-	0xbf84002b, 0xbefe03c1,
+-	0x877c8172, 0xbf06817c,
+-	0xbf850002, 0xbeff0380,
+-	0xbf820001, 0xbeff03c1,
+-	0xb9714306, 0x8771c171,
+-	0xbf840021, 0x8f718671,
+-	0x8f718271, 0xbef60371,
+-	0xbef603ff, 0x01000000,
+-	0xd7650000, 0x000100c1,
+-	0xd7660000, 0x000200c1,
+-	0x16000084, 0x877c8172,
+-	0xbf06817c, 0xbefc0380,
+-	0xbf85000a, 0x807cff7c,
+-	0x00000080, 0x807aff7a,
+-	0x00000080, 0xd5250000,
+-	0x0001ff00, 0x00000080,
+-	0xbf0a717c, 0xbf85fff7,
+-	0xbf820009, 0x807cff7c,
+-	0x00000100, 0x807aff7a,
+-	0x00000100, 0xd5250000,
+-	0x0001ff00, 0x00000100,
+-	0xbf0a717c, 0xbf85fff7,
+-	0x877c8172, 0xbf06817c,
+-	0xbf850003, 0x8f7687ff,
+-	0x0000006a, 0xbf820002,
+-	0x8f7688ff, 0x0000006a,
+-	0xbef603ff, 0x01000000,
+-	0x877c8172, 0xbf06817c,
+-	0xbefc0380, 0xbf800000,
+-	0xbf85000b, 0xbe802e00,
+-	0x7e000200, 0xe0704000,
+-	0x7a5d0000, 0x807aff7a,
+-	0x00000080, 0x807c817c,
+-	0xbf0aff7c, 0x0000006a,
+-	0xbf85fff6, 0xbf82000a,
+-	0xbe802e00, 0x7e000200,
+-	0xe0704000, 0x7a5d0000,
+-	0x807aff7a, 0x00000100,
+-	0x807c817c, 0xbf0aff7c,
+-	0x0000006a, 0xbf85fff6,
+-	0xbef60384, 0xbef603ff,
+-	0x01000000, 0x877c8172,
+-	0xbf06817c, 0xbf850030,
+-	0x7e00027b, 0xe0704000,
+-	0x7a5d0000, 0x807aff7a,
+-	0x00000080, 0x7e00026c,
+-	0xe0704000, 0x7a5d0000,
+-	0x807aff7a, 0x00000080,
+-	0x7e00026d, 0xe0704000,
+-	0x7a5d0000, 0x807aff7a,
+-	0x00000080, 0x7e00026e,
+-	0xe0704000, 0x7a5d0000,
+-	0x807aff7a, 0x00000080,
+-	0x7e00026f, 0xe0704000,
+-	0x7a5d0000, 0x807aff7a,
+-	0x00000080, 0x7e000270,
+-	0xe0704000, 0x7a5d0000,
+-	0x807aff7a, 0x00000080,
+-	0xb971f803, 0x7e000271,
+-	0xe0704000, 0x7a5d0000,
+-	0x807aff7a, 0x00000080,
+-	0x7e000273, 0xe0704000,
+-	0x7a5d0000, 0x807aff7a,
+-	0x00000080, 0xb97bf801,
+-	0x7e00027b, 0xe0704000,
+-	0x7a5d0000, 0x807aff7a,
+-	0x00000080, 0xbf82002f,
+-	0x7e00027b, 0xe0704000,
+-	0x7a5d0000, 0x807aff7a,
+-	0x00000100, 0x7e00026c,
+-	0xe0704000, 0x7a5d0000,
+-	0x807aff7a, 0x00000100,
+-	0x7e00026d, 0xe0704000,
+-	0x7a5d0000, 0x807aff7a,
+-	0x00000100, 0x7e00026e,
+-	0xe0704000, 0x7a5d0000,
+-	0x807aff7a, 0x00000100,
+-	0x7e00026f, 0xe0704000,
+-	0x7a5d0000, 0x807aff7a,
+-	0x00000100, 0x7e000270,
+-	0xe0704000, 0x7a5d0000,
+-	0x807aff7a, 0x00000100,
+-	0xb971f803, 0x7e000271,
+-	0xe0704000, 0x7a5d0000,
+-	0x807aff7a, 0x00000100,
+-	0x7e000273, 0xe0704000,
+-	0x7a5d0000, 0x807aff7a,
+-	0x00000100, 0xb97bf801,
+-	0x7e00027b, 0xe0704000,
+-	0x7a5d0000, 0x807aff7a,
+-	0x00000100, 0xbf820119,
++	0xbf85fff8, 0xbf820138,
+ 	0xbef4037e, 0x8775ff7f,
+ 	0x0000ffff, 0x8875ff75,
+ 	0x00040000, 0xbef60380,
+-	0xbef703ff, 0x00807fac,
++	0xbef703ff, 0x10807fac,
+ 	0x8772ff7f, 0x08000000,
+ 	0x90728372, 0x88777277,
+ 	0x8772ff7f, 0x70000000,
+ 	0x90728172, 0x88777277,
+-	0xb97902dc, 0x8879797f,
+-	0xbef80380, 0xbefe03c1,
+-	0x877c8179, 0xbf06817c,
++	0xb97302dc, 0x8f739973,
++	0x8873737f, 0x8772ff7f,
++	0x04000000, 0xbf840036,
++	0xbefe03c1, 0x907c9973,
++	0x877c817c, 0xbf06817c,
+ 	0xbf850002, 0xbeff0380,
+ 	0xbf820001, 0xbeff03c1,
+-	0xb96f2a05, 0x806f816f,
+-	0x8f6f826f, 0x877c8179,
+-	0xbf06817c, 0xbf850013,
+-	0x8f76876f, 0xbef603ff,
+-	0x01000000, 0xbef20378,
+-	0x8078ff78, 0x00000080,
+-	0xbefc0381, 0xe0304000,
+-	0x785d0000, 0xbf8c3f70,
+-	0x7e008500, 0x807c817c,
++	0xb96f4306, 0x876fc16f,
++	0xbf84002b, 0x8f6f866f,
++	0x8f6f826f, 0xbef6036f,
++	0xb9782a05, 0x80788178,
++	0x907c9973, 0x877c817c,
++	0xbf06817c, 0xbf850002,
++	0x8f788978, 0xbf820001,
++	0x8f788a78, 0xb9721e06,
++	0x8f728a72, 0x80787278,
++	0x8078ff78, 0x00000200,
+ 	0x8078ff78, 0x00000080,
+-	0xbf0a6f7c, 0xbf85fff7,
+-	0xe0304000, 0x725d0000,
+-	0xbf820023, 0x8f76886f,
++	0xbef603ff, 0x01000000,
++	0x907c9973, 0x877c817c,
++	0xbf06817c, 0xbefc0380,
++	0xbf850009, 0xe0310000,
++	0x781d0000, 0x807cff7c,
++	0x00000080, 0x8078ff78,
++	0x00000080, 0xbf0a6f7c,
++	0xbf85fff8, 0xbf820008,
++	0xe0310000, 0x781d0000,
++	0x807cff7c, 0x00000100,
++	0x8078ff78, 0x00000100,
++	0xbf0a6f7c, 0xbf85fff8,
++	0xbef80380, 0xbefe03c1,
++	0x907c9973, 0x877c817c,
++	0xbf06817c, 0xbf850002,
++	0xbeff0380, 0xbf820001,
++	0xbeff03c1, 0xb96f2a05,
++	0x806f816f, 0x8f6f826f,
++	0x907c9973, 0x877c817c,
++	0xbf06817c, 0xbf850021,
+ 	0xbef603ff, 0x01000000,
+ 	0xbef20378, 0x8078ff78,
+-	0x00000100, 0xbefc0381,
++	0x00000200, 0xbefc0384,
+ 	0xe0304000, 0x785d0000,
++	0xe0304080, 0x785d0100,
++	0xe0304100, 0x785d0200,
++	0xe0304180, 0x785d0300,
+ 	0xbf8c3f70, 0x7e008500,
+-	0x807c817c, 0x8078ff78,
+-	0x00000100, 0xbf0a6f7c,
+-	0xbf85fff7, 0xb96f1e06,
++	0x7e028501, 0x7e048502,
++	0x7e068503, 0x807c847c,
++	0x8078ff78, 0x00000200,
++	0xbf0a6f7c, 0xbf85ffee,
++	0xe0304000, 0x725d0000,
++	0xe0304080, 0x725d0100,
++	0xe0304100, 0x725d0200,
++	0xe0304180, 0x725d0300,
++	0xbf820031, 0xbef603ff,
++	0x01000000, 0xbef20378,
++	0x8078ff78, 0x00000400,
++	0xbefc0384, 0xe0304000,
++	0x785d0000, 0xe0304100,
++	0x785d0100, 0xe0304200,
++	0x785d0200, 0xe0304300,
++	0x785d0300, 0xbf8c3f70,
++	0x7e008500, 0x7e028501,
++	0x7e048502, 0x7e068503,
++	0x807c847c, 0x8078ff78,
++	0x00000400, 0xbf0a6f7c,
++	0xbf85ffee, 0xb96f1e06,
+ 	0x876fc16f, 0xbf84000e,
+ 	0x8f6f836f, 0x806f7c6f,
+ 	0xbefe03c1, 0xbeff0380,
+@@ -875,107 +982,81 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
+ 	0x00000080, 0xbf0a6f7c,
+ 	0xbf85fff7, 0xbeff03c1,
+ 	0xe0304000, 0x725d0000,
+-	0x8772ff79, 0x04000000,
+-	0xbf840020, 0xbefe03c1,
+-	0x877c8179, 0xbf06817c,
+-	0xbf850002, 0xbeff0380,
+-	0xbf820001, 0xbeff03c1,
+-	0xb96f4306, 0x876fc16f,
+-	0xbf840016, 0x8f6f866f,
+-	0x8f6f826f, 0xbef6036f,
+-	0xbef603ff, 0x01000000,
+-	0x877c8172, 0xbf06817c,
+-	0xbefc0380, 0xbf850007,
+-	0x807cff7c, 0x00000080,
+-	0x8078ff78, 0x00000080,
+-	0xbf0a6f7c, 0xbf85fffa,
+-	0xbf820006, 0x807cff7c,
+-	0x00000100, 0x8078ff78,
+-	0x00000100, 0xbf0a6f7c,
+-	0xbf85fffa, 0x877c8179,
+-	0xbf06817c, 0xbf850003,
+-	0x8f7687ff, 0x0000006a,
+-	0xbf820002, 0x8f7688ff,
+-	0x0000006a, 0xbef603ff,
+-	0x01000000, 0x877c8179,
+-	0xbf06817c, 0xbf850012,
+-	0xf4211cba, 0xf0000000,
+-	0x8078ff78, 0x00000080,
+-	0xbefc0381, 0xf421003a,
+-	0xf0000000, 0x8078ff78,
+-	0x00000080, 0xbf8cc07f,
+-	0xbe803000, 0xbf800000,
+-	0x807c817c, 0xbf0aff7c,
+-	0x0000006a, 0xbf85fff5,
+-	0xbe800372, 0xbf820011,
+-	0xf4211cba, 0xf0000000,
+-	0x8078ff78, 0x00000100,
+-	0xbefc0381, 0xf421003a,
+-	0xf0000000, 0x8078ff78,
+-	0x00000100, 0xbf8cc07f,
+-	0xbe803000, 0xbf800000,
+-	0x807c817c, 0xbf0aff7c,
+-	0x0000006a, 0xbf85fff5,
+-	0xbe800372, 0xbef60384,
++	0xe0304080, 0x725d0100,
++	0xe0304100, 0x725d0200,
++	0xe0304180, 0x725d0300,
++	0xb9782a05, 0x80788178,
++	0x907c9973, 0x877c817c,
++	0xbf06817c, 0xbf850002,
++	0x8f788978, 0xbf820001,
++	0x8f788a78, 0xb9721e06,
++	0x8f728a72, 0x80787278,
++	0x8078ff78, 0x00000200,
++	0x80f8ff78, 0x00000058,
++	0x80f88878, 0xbef603ff,
++	0x01000000, 0xbefc03ff,
++	0x0000006a, 0xf425003a,
++	0xf0000000, 0x80f8a078,
++	0xbf8cc07f, 0x80fc827c,
++	0xbf800000, 0xbe803100,
++	0xf42d003a, 0xf0000000,
++	0x80f8c078, 0xbf8cc07f,
++	0x80fc887c, 0xbf800000,
++	0xbe803100, 0xbe823102,
++	0xbe843104, 0xbe863106,
++	0xf431003a, 0xf0000000,
++	0x80f8c078, 0xbf8cc07f,
++	0x80fc907c, 0xbf800000,
++	0xbe803100, 0xbe823102,
++	0xbe843104, 0xbe863106,
++	0xbe883108, 0xbe8a310a,
++	0xbe8c310c, 0xbe8e310e,
++	0xbf06807c, 0xbf84fff0,
++	0xb9782a05, 0x80788178,
++	0x907c9973, 0x877c817c,
++	0xbf06817c, 0xbf850002,
++	0x8f788978, 0xbf820001,
++	0x8f788a78, 0xb9721e06,
++	0x8f728a72, 0x80787278,
++	0x8078ff78, 0x00000200,
+ 	0xbef603ff, 0x01000000,
+-	0x877c8179, 0xbf06817c,
+-	0xbf850025, 0xf4211bfa,
+-	0xf0000000, 0x8078ff78,
+-	0x00000080, 0xf4211b3a,
+-	0xf0000000, 0x8078ff78,
+-	0x00000080, 0xf4211b7a,
+-	0xf0000000, 0x8078ff78,
+-	0x00000080, 0xf4211eba,
+-	0xf0000000, 0x8078ff78,
+-	0x00000080, 0xf4211efa,
+-	0xf0000000, 0x8078ff78,
+-	0x00000080, 0xf4211c3a,
+-	0xf0000000, 0x8078ff78,
+-	0x00000080, 0xf4211c7a,
+-	0xf0000000, 0x8078ff78,
+-	0x00000080, 0xf4211cfa,
+-	0xf0000000, 0x8078ff78,
+-	0x00000080, 0xf4211e7a,
+-	0xf0000000, 0x8078ff78,
+-	0x00000080, 0xbf820024,
+ 	0xf4211bfa, 0xf0000000,
+-	0x8078ff78, 0x00000100,
+-	0xf4211b3a, 0xf0000000,
+-	0x8078ff78, 0x00000100,
++	0x80788478, 0xf4211b3a,
++	0xf0000000, 0x80788478,
+ 	0xf4211b7a, 0xf0000000,
+-	0x8078ff78, 0x00000100,
+-	0xf4211eba, 0xf0000000,
+-	0x8078ff78, 0x00000100,
++	0x80788478, 0xf4211eba,
++	0xf0000000, 0x80788478,
+ 	0xf4211efa, 0xf0000000,
+-	0x8078ff78, 0x00000100,
+-	0xf4211c3a, 0xf0000000,
+-	0x8078ff78, 0x00000100,
++	0x80788478, 0xf4211c3a,
++	0xf0000000, 0x80788478,
+ 	0xf4211c7a, 0xf0000000,
+-	0x8078ff78, 0x00000100,
++	0x80788478, 0xf4211e7a,
++	0xf0000000, 0x80788478,
+ 	0xf4211cfa, 0xf0000000,
+-	0x8078ff78, 0x00000100,
+-	0xf4211e7a, 0xf0000000,
+-	0x8078ff78, 0x00000100,
+-	0xbf8cc07f, 0x876dff6d,
++	0x80788478, 0xbf8cc07f,
++	0xbef2036d, 0x876dff72,
+ 	0x0000ffff, 0xbefc036f,
+ 	0xbefe037a, 0xbeff037b,
+ 	0x876f71ff, 0x000003ff,
+-	0xb9ef4803, 0xb9f3f816,
++	0xb9ef4803, 0xb9f9f816,
+ 	0x876f71ff, 0xfffff800,
+ 	0x906f8b6f, 0xb9efa2c3,
+-	0xb9f9f801, 0x876fff6d,
+-	0xf0000000, 0x906f9c6f,
+-	0x8f6f906f, 0xbef20380,
+-	0x88726f72, 0x876fff6d,
+-	0x08000000, 0x906f9b6f,
+-	0x8f6f8f6f, 0x88726f72,
+-	0x876fff70, 0x00800000,
+-	0x906f976f, 0xb9f2f807,
+-	0xb9f0f802, 0xbf8a0000,
+-	0xbe80226c, 0xbf810000,
++	0xb9f3f801, 0x876fff72,
++	0xfc000000, 0x906f9a6f,
++	0x8f6f906f, 0xbef30380,
++	0x88736f73, 0x876fff72,
++	0x02000000, 0x906f996f,
++	0x8f6f8f6f, 0x88736f73,
++	0x876fff72, 0x01000000,
++	0x906f986f, 0x8f6f996f,
++	0x88736f73, 0x876fff70,
++	0x00800000, 0x906f976f,
++	0xb9f3f807, 0x87fe7e7e,
++	0x87ea6a6a, 0xb9f0f802,
++	0xbf8a0000, 0xbe80226c,
++	0xbf810000, 0xbf9f0000,
+ 	0xbf9f0000, 0xbf9f0000,
+ 	0xbf9f0000, 0xbf9f0000,
+-	0xbf9f0000, 0x00000000,
+ };
+ static const uint32_t cwsr_trap_arcturus_hex[] = {
+ 	0xbf820001, 0xbf8202c4,
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
+index f20e463e748b..261e05430852 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
+@@ -20,1105 +20,933 @@
+  * OTHER DEALINGS IN THE SOFTWARE.
+  */
+ 
++var SQ_WAVE_STATUS_INST_ATC_SHIFT		= 23
++var SQ_WAVE_STATUS_INST_ATC_MASK		= 0x00800000
++var SQ_WAVE_STATUS_SPI_PRIO_MASK		= 0x00000006
++var SQ_WAVE_STATUS_HALT_MASK			= 0x2000
++
++var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT		= 12
++var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE		= 9
++var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT		= 8
++var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE		= 6
++var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT		= 24
++var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE		= 4
++var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT	= 24
++var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE	= 4
++var SQ_WAVE_IB_STS2_WAVE64_SHIFT		= 11
++var SQ_WAVE_IB_STS2_WAVE64_SIZE			= 1
++
++var SQ_WAVE_TRAPSTS_SAVECTX_MASK		= 0x400
++var SQ_WAVE_TRAPSTS_EXCE_MASK			= 0x1FF
++var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT		= 10
++var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK		= 0x100
++var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT		= 8
++var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK		= 0x3FF
++var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT		= 0x0
++var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE		= 10
++var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK		= 0xFFFFF800
++var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT		= 11
++var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE		= 21
++var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK		= 0x800
++
++var SQ_WAVE_IB_STS_RCNT_SHIFT			= 16
++var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT		= 15
++var SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT		= 25
++var SQ_WAVE_IB_STS_REPLAY_W64H_SIZE		= 1
++var SQ_WAVE_IB_STS_REPLAY_W64H_MASK		= 0x02000000
++var SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE		= 1
++var SQ_WAVE_IB_STS_RCNT_SIZE			= 6
++var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK	= 0x003F8000
++var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG	= 0x00007FFF
++
++var SQ_BUF_RSRC_WORD1_ATC_SHIFT			= 24
++var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT		= 27
++
++// bits [31:24] unused by SPI debug data
++var TTMP11_SAVE_REPLAY_W64H_SHIFT		= 31
++var TTMP11_SAVE_REPLAY_W64H_MASK		= 0x80000000
++var TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT		= 24
++var TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK		= 0x7F000000
++
++// SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14]
++// when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE
++var S_SAVE_BUF_RSRC_WORD1_STRIDE		= 0x00040000
++var S_SAVE_BUF_RSRC_WORD3_MISC			= 0x10807FAC
++
++var S_SAVE_SPI_INIT_ATC_MASK			= 0x08000000
++var S_SAVE_SPI_INIT_ATC_SHIFT			= 27
++var S_SAVE_SPI_INIT_MTYPE_MASK			= 0x70000000
++var S_SAVE_SPI_INIT_MTYPE_SHIFT			= 28
++var S_SAVE_SPI_INIT_FIRST_WAVE_MASK		= 0x04000000
++var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT		= 26
++
++var S_SAVE_PC_HI_RCNT_SHIFT			= 26
++var S_SAVE_PC_HI_RCNT_MASK			= 0xFC000000
++var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT		= 25
++var S_SAVE_PC_HI_FIRST_REPLAY_MASK		= 0x02000000
++var S_SAVE_PC_HI_REPLAY_W64H_SHIFT		= 24
++var S_SAVE_PC_HI_REPLAY_W64H_MASK		= 0x01000000
++
++var s_sgpr_save_num				= 106
++
++var s_save_spi_init_lo				= exec_lo
++var s_save_spi_init_hi				= exec_hi
++var s_save_pc_lo				= ttmp0
++var s_save_pc_hi				= ttmp1
++var s_save_exec_lo				= ttmp2
++var s_save_exec_hi				= ttmp3
++var s_save_status				= ttmp12
++var s_save_trapsts				= ttmp5
++var s_save_xnack_mask				= ttmp6
++var s_wave_size					= ttmp7
++var s_save_buf_rsrc0				= ttmp8
++var s_save_buf_rsrc1				= ttmp9
++var s_save_buf_rsrc2				= ttmp10
++var s_save_buf_rsrc3				= ttmp11
++var s_save_mem_offset				= ttmp14
++var s_save_alloc_size				= s_save_trapsts
++var s_save_tmp					= s_save_buf_rsrc2
++var s_save_m0					= ttmp15
++
++var S_RESTORE_BUF_RSRC_WORD1_STRIDE		= S_SAVE_BUF_RSRC_WORD1_STRIDE
++var S_RESTORE_BUF_RSRC_WORD3_MISC		= S_SAVE_BUF_RSRC_WORD3_MISC
++
++var S_RESTORE_SPI_INIT_ATC_MASK			= 0x08000000
++var S_RESTORE_SPI_INIT_ATC_SHIFT		= 27
++var S_RESTORE_SPI_INIT_MTYPE_MASK		= 0x70000000
++var S_RESTORE_SPI_INIT_MTYPE_SHIFT		= 28
++var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK		= 0x04000000
++var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT		= 26
++var S_WAVE_SIZE					= 25
++
++var S_RESTORE_PC_HI_RCNT_SHIFT			= S_SAVE_PC_HI_RCNT_SHIFT
++var S_RESTORE_PC_HI_RCNT_MASK			= S_SAVE_PC_HI_RCNT_MASK
++var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT		= S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
++var S_RESTORE_PC_HI_FIRST_REPLAY_MASK		= S_SAVE_PC_HI_FIRST_REPLAY_MASK
++
++var s_restore_spi_init_lo			= exec_lo
++var s_restore_spi_init_hi			= exec_hi
++var s_restore_mem_offset			= ttmp12
++var s_restore_alloc_size			= ttmp3
++var s_restore_tmp				= ttmp6
++var s_restore_mem_offset_save			= s_restore_tmp
++var s_restore_m0				= s_restore_alloc_size
++var s_restore_mode				= ttmp7
++var s_restore_pc_lo				= ttmp0
++var s_restore_pc_hi				= ttmp1
++var s_restore_exec_lo				= ttmp14
++var s_restore_exec_hi				= ttmp15
++var s_restore_status				= ttmp4
++var s_restore_trapsts				= ttmp5
++var s_restore_xnack_mask			= ttmp13
++var s_restore_buf_rsrc0				= ttmp8
++var s_restore_buf_rsrc1				= ttmp9
++var s_restore_buf_rsrc2				= ttmp10
++var s_restore_buf_rsrc3				= ttmp11
++var s_restore_size				= ttmp7
+ 
+ shader main
++	asic(DEFAULT)
++	type(CS)
++	wave_size(32)
+ 
+-asic(DEFAULT)
+-
+-type(CS)
+-
+-wave_size(32)
+-/*************************************************************************/
+-/*					control on how to run the shader					 */
+-/*************************************************************************/
+-//any hack that needs to be made to run this code in EMU (either becasue various EMU code are not ready or no compute save & restore in EMU run)
+-var EMU_RUN_HACK					=	0
+-var EMU_RUN_HACK_RESTORE_NORMAL		=	0
+-var EMU_RUN_HACK_SAVE_NORMAL_EXIT	=	0
+-var	EMU_RUN_HACK_SAVE_SINGLE_WAVE	=	0
+-var EMU_RUN_HACK_SAVE_FIRST_TIME	= 	0					//for interrupted restore in which the first save is through EMU_RUN_HACK
+-var SAVE_LDS						= 	0
+-var WG_BASE_ADDR_LO					=   0x9000a000
+-var WG_BASE_ADDR_HI					=	0x0
+-var WAVE_SPACE						=	0x9000				//memory size that each wave occupies in workgroup state mem, increase from 5000 to 9000 for more SGPR need to be saved
+-var CTX_SAVE_CONTROL				=	0x0
+-var CTX_RESTORE_CONTROL				=	CTX_SAVE_CONTROL
+-var SIM_RUN_HACK					=	0					//any hack that needs to be made to run this code in SIM (either becasue various RTL code are not ready or no compute save & restore in RTL run)
+-var	SGPR_SAVE_USE_SQC				=	0					//use SQC D$ to do the write
+-var USE_MTBUF_INSTEAD_OF_MUBUF		=	0					//need to change BUF_DATA_FORMAT in S_SAVE_BUF_RSRC_WORD3_MISC from 0 to BUF_DATA_FORMAT_32 if set to 1 (i.e. 0x00827FAC)
+-var SWIZZLE_EN						=	0					//whether we use swizzled buffer addressing
+-var SAVE_RESTORE_HWID_DDID          =   0
+-var RESTORE_DDID_IN_SGPR18          =   0
+-/**************************************************************************/
+-/*                     	variables							              */
+-/**************************************************************************/
+-var SQ_WAVE_STATUS_INST_ATC_SHIFT  = 23
+-var SQ_WAVE_STATUS_INST_ATC_MASK   = 0x00800000
+-var SQ_WAVE_STATUS_SPI_PRIO_MASK   = 0x00000006
+-
+-var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT	= 12
+-var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE		= 9
+-var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT	= 8
+-var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE	= 6
+-var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT	= 24
+-var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE	= 4						//FIXME	 sq.blk still has 4 bits at this time while SQ programming guide has 3 bits
+-var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT    = 24
+-var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE     = 4
+-var SQ_WAVE_IB_STS2_WAVE64_SHIFT        = 11
+-var SQ_WAVE_IB_STS2_WAVE64_SIZE         = 1
+-
+-var	SQ_WAVE_TRAPSTS_SAVECTX_MASK	=	0x400
+-var SQ_WAVE_TRAPSTS_EXCE_MASK       =   0x1FF          			// Exception mask
+-var	SQ_WAVE_TRAPSTS_SAVECTX_SHIFT	=	10					
+-var	SQ_WAVE_TRAPSTS_MEM_VIOL_MASK	=	0x100					
+-var	SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT	=	8		
+-var	SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK 	=	0x3FF
+-var	SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT 	=	0x0
+-var	SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE 	=	10
+-var	SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK 	=	0xFFFFF800	
+-var	SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT 	=	11
+-var	SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE 	=	21	
+-
+-var SQ_WAVE_IB_STS_RCNT_SHIFT			=	16					//FIXME
+-var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT	=	15					//FIXME
+-var SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE    =   1                   //FIXME
+-var SQ_WAVE_IB_STS_RCNT_SIZE            =   6                   //FIXME
+-var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG	= 0x00007FFF	//FIXME
+- 
+-var	SQ_BUF_RSRC_WORD1_ATC_SHIFT		=	24
+-var	SQ_BUF_RSRC_WORD3_MTYPE_SHIFT	=	27
+-
+-
+-/*      Save        */
+-var	S_SAVE_BUF_RSRC_WORD1_STRIDE		=	0x00040000  		//stride is 4 bytes 
+-var	S_SAVE_BUF_RSRC_WORD3_MISC			= 	0x00807FAC			//SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE			
+-
+-var	S_SAVE_SPI_INIT_ATC_MASK			=	0x08000000			//bit[27]: ATC bit
+-var	S_SAVE_SPI_INIT_ATC_SHIFT			=	27
+-var	S_SAVE_SPI_INIT_MTYPE_MASK			=	0x70000000			//bit[30:28]: Mtype
+-var	S_SAVE_SPI_INIT_MTYPE_SHIFT			=	28
+-var	S_SAVE_SPI_INIT_FIRST_WAVE_MASK		=	0x04000000			//bit[26]: FirstWaveInTG
+-var	S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT	=	26
+-
+-var S_SAVE_PC_HI_RCNT_SHIFT				=	28					//FIXME	 check with Brian to ensure all fields other than PC[47:0] can be used
+-var S_SAVE_PC_HI_RCNT_MASK				=   0xF0000000			//FIXME
+-var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT		=	27					//FIXME
+-var S_SAVE_PC_HI_FIRST_REPLAY_MASK		=	0x08000000			//FIXME
+-
+-var	s_save_spi_init_lo				=	exec_lo
+-var s_save_spi_init_hi				=	exec_hi
+-
+-var	s_save_pc_lo			=	ttmp0			//{TTMP1, TTMP0} = {3¡¯h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]}
+-var	s_save_pc_hi			=	ttmp1			
+-var s_save_exec_lo			=	ttmp2
+-var s_save_exec_hi			= 	ttmp3			
+-var	s_save_status			=	ttmp4			
+-var	s_save_trapsts			=	ttmp5			//not really used until the end of the SAVE routine
+-var s_wave_size         	=	ttmp6           //ttmp6 is not needed now, since it's only 32bit xnack mask, now use it to determine wave32 or wave64 in EMU_HACK
+-var s_save_xnack_mask	    =	ttmp7
+-var	s_save_buf_rsrc0		=	ttmp8
+-var	s_save_buf_rsrc1		=	ttmp9
+-var	s_save_buf_rsrc2		=	ttmp10
+-var	s_save_buf_rsrc3		=	ttmp11
+-
+-var s_save_mem_offset		= 	ttmp14
+-var s_sgpr_save_num         =   106                     //in gfx10, all sgpr must be saved
+-var s_save_alloc_size		=	s_save_trapsts			//conflict
+-var s_save_tmp              =   s_save_buf_rsrc2       	//shared with s_save_buf_rsrc2  (conflict: should not use mem access with s_save_tmp at the same time)
+-var s_save_m0				=	ttmp15					
+-
+-/*      Restore     */
+-var	S_RESTORE_BUF_RSRC_WORD1_STRIDE			=	S_SAVE_BUF_RSRC_WORD1_STRIDE 
+-var	S_RESTORE_BUF_RSRC_WORD3_MISC			= 	S_SAVE_BUF_RSRC_WORD3_MISC		 
+-
+-var	S_RESTORE_SPI_INIT_ATC_MASK			    =	0x08000000			//bit[27]: ATC bit
+-var	S_RESTORE_SPI_INIT_ATC_SHIFT			=	27
+-var	S_RESTORE_SPI_INIT_MTYPE_MASK			=	0x70000000			//bit[30:28]: Mtype
+-var	S_RESTORE_SPI_INIT_MTYPE_SHIFT			=	28
+-var	S_RESTORE_SPI_INIT_FIRST_WAVE_MASK		=	0x04000000			//bit[26]: FirstWaveInTG
+-var	S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT	    =	26
+-
+-var S_RESTORE_PC_HI_RCNT_SHIFT				=	S_SAVE_PC_HI_RCNT_SHIFT
+-var S_RESTORE_PC_HI_RCNT_MASK				=   S_SAVE_PC_HI_RCNT_MASK
+-var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT		=	S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
+-var S_RESTORE_PC_HI_FIRST_REPLAY_MASK		=	S_SAVE_PC_HI_FIRST_REPLAY_MASK
+-
+-var s_restore_spi_init_lo                   =   exec_lo
+-var s_restore_spi_init_hi                   =   exec_hi
+-
+-var s_restore_mem_offset		= 	ttmp12
+-var s_restore_alloc_size		=	ttmp3
+-var s_restore_tmp           	=   ttmp6
+-var s_restore_mem_offset_save	= 	s_restore_tmp 		//no conflict
+-
+-var s_restore_m0			=	s_restore_alloc_size	//no conflict			
+-
+-var s_restore_mode			=  	ttmp13
+-var s_restore_hwid1         =  ttmp2
+-var s_restore_ddid          =  s_restore_hwid1
+-var	s_restore_pc_lo		    =	ttmp0			
+-var	s_restore_pc_hi		    =	ttmp1
+-var s_restore_exec_lo		=	ttmp14
+-var s_restore_exec_hi		= 	ttmp15
+-var	s_restore_status	    =	ttmp4			
+-var	s_restore_trapsts	    =	ttmp5
+-//var s_restore_xnack_mask_lo	=	xnack_mask_lo
+-//var s_restore_xnack_mask_hi	=	xnack_mask_hi
+-var s_restore_xnack_mask    =   ttmp7
+-var	s_restore_buf_rsrc0		=	ttmp8
+-var	s_restore_buf_rsrc1		=	ttmp9
+-var	s_restore_buf_rsrc2		=	ttmp10
+-var	s_restore_buf_rsrc3		=	ttmp11
+-var s_restore_size         	=	ttmp13                  //ttmp13 has no conflict
+-
+-/**************************************************************************/
+-/*                     	trap handler entry points			              */
+-/**************************************************************************/
+-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) 					//hack to use trap_id for determining save/restore
+-		//FIXME VCCZ un-init assertion s_getreg_b32  	s_save_status, hwreg(HW_REG_STATUS)			//save STATUS since we will change SCC
+-		s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000 				//change SCC
+-    	s_cmp_eq_u32 s_save_tmp, 0x007e0000  						//Save: trap_id = 0x7e. Restore: trap_id = 0x7f.  
+-    	s_cbranch_scc0 L_JUMP_TO_RESTORE							//do not need to recover STATUS here  since we are going to RESTORE
+-		//FIXME  s_setreg_b32 	hwreg(HW_REG_STATUS), 	s_save_status		//need to recover STATUS since we are going to SAVE	
+-		s_branch L_SKIP_RESTORE 									//NOT restore, SAVE actually
+-	else	
+-		s_branch L_SKIP_RESTORE 									//NOT restore. might be a regular trap or save
+-    end
++	s_branch	L_SKIP_RESTORE						//NOT restore. might be a regular trap or save
+ 
+ L_JUMP_TO_RESTORE:
+-    s_branch L_RESTORE												//restore
++	s_branch	L_RESTORE
+ 
+ L_SKIP_RESTORE:
+-	
+-	s_getreg_b32  	s_save_status, hwreg(HW_REG_STATUS)								//save STATUS since we will change SCC
+-    s_andn2_b32		s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK      //check whether this is for save
+-	s_getreg_b32  	s_save_trapsts, hwreg(HW_REG_TRAPSTS)    		 				
+-	s_and_b32		s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK	//check whether this is for save  
+-	s_cbranch_scc1	L_SAVE															//this is the operation for save
+-
+-    // *********    Handle non-CWSR traps       *******************
+-    if (!EMU_RUN_HACK)
+-		s_getreg_b32     s_save_trapsts, hwreg(HW_REG_TRAPSTS)
+-		s_and_b32        s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK // Check whether it is an exception
+-		s_cbranch_scc1  L_EXCP_CASE   // Exception, jump back to the shader program directly.
+-		s_add_u32    ttmp0, ttmp0, 4   // S_TRAP case, add 4 to ttmp0 
+-		
+-		L_EXCP_CASE:
+-		s_and_b32    ttmp1, ttmp1, 0xFFFF
+-		s_rfe_b64    [ttmp0, ttmp1]
+-	end
+-    // *********        End handling of non-CWSR traps   *******************
+-
+-/**************************************************************************/
+-/*                     	save routine						              */
+-/**************************************************************************/
+-
+-L_SAVE:	
+-	
++	s_getreg_b32	s_save_status, hwreg(HW_REG_STATUS)			//save STATUS since we will change SCC
++	s_andn2_b32	s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK
++	s_getreg_b32	s_save_trapsts, hwreg(HW_REG_TRAPSTS)
++	s_and_b32	ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK	//check whether this is for save
++	s_cbranch_scc1	L_SAVE
++
++	// If STATUS.MEM_VIOL is asserted then halt the wave to prevent
++	// the exception raising again and blocking context save.
++	s_and_b32	ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK
++	s_cbranch_scc0	L_FETCH_2ND_TRAP
++	s_or_b32	s_save_status, s_save_status, SQ_WAVE_STATUS_HALT_MASK
++
++L_FETCH_2ND_TRAP:
++	// Preserve and clear scalar XNACK state before issuing scalar loads.
++	// Save IB_STS.REPLAY_W64H[25], RCNT[21:16], FIRST_REPLAY[15] into
++	// unused space ttmp11[31:24].
++	s_andn2_b32	ttmp11, ttmp11, (TTMP11_SAVE_REPLAY_W64H_MASK | TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK)
++	s_getreg_b32	ttmp2, hwreg(HW_REG_IB_STS)
++	s_and_b32	ttmp3, ttmp2, SQ_WAVE_IB_STS_REPLAY_W64H_MASK
++	s_lshl_b32	ttmp3, ttmp3, (TTMP11_SAVE_REPLAY_W64H_SHIFT - SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT)
++	s_or_b32	ttmp11, ttmp11, ttmp3
++	s_and_b32	ttmp3, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK
++	s_lshl_b32	ttmp3, ttmp3, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT)
++	s_or_b32	ttmp11, ttmp11, ttmp3
++	s_andn2_b32	ttmp2, ttmp2, (SQ_WAVE_IB_STS_REPLAY_W64H_MASK | SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK)
++	s_setreg_b32	hwreg(HW_REG_IB_STS), ttmp2
++
++	// Read second-level TBA/TMA from first-level TMA and jump if available.
++	// ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data)
++	// ttmp12 holds SQ_WAVE_STATUS
++	s_getreg_b32	ttmp4, hwreg(HW_REG_SHADER_TMA_LO)
++	s_getreg_b32	ttmp5, hwreg(HW_REG_SHADER_TMA_HI)
++	s_lshl_b64	[ttmp4, ttmp5], [ttmp4, ttmp5], 0x8
++	s_load_dwordx2	[ttmp2, ttmp3], [ttmp4, ttmp5], 0x0 glc:1		// second-level TBA
++	s_waitcnt	lgkmcnt(0)
++	s_load_dwordx2	[ttmp4, ttmp5], [ttmp4, ttmp5], 0x8 glc:1		// second-level TMA
++	s_waitcnt	lgkmcnt(0)
++	s_and_b64	[ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3]
++	s_cbranch_scc0	L_NO_NEXT_TRAP						// second-level trap handler not been set
++	s_setpc_b64	[ttmp2, ttmp3]						// jump to second-level trap handler
++
++L_NO_NEXT_TRAP:
++	s_getreg_b32	s_save_trapsts, hwreg(HW_REG_TRAPSTS)
++	s_and_b32	s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK
++	s_cbranch_scc1	L_EXCP_CASE						// Exception, jump back to the shader program directly.
++	s_add_u32	ttmp0, ttmp0, 4						// S_TRAP case, add 4 to ttmp0
++	s_addc_u32	ttmp1, ttmp1, 0
++L_EXCP_CASE:
++	s_and_b32	ttmp1, ttmp1, 0xFFFF
++
++	// Restore SQ_WAVE_IB_STS.
++	s_lshr_b32	ttmp2, ttmp11, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT)
++	s_and_b32	ttmp3, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK
++	s_lshr_b32	ttmp2, ttmp11, (TTMP11_SAVE_REPLAY_W64H_SHIFT - SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT)
++	s_and_b32	ttmp2, ttmp2, SQ_WAVE_IB_STS_REPLAY_W64H_MASK
++	s_or_b32	ttmp2, ttmp2, ttmp3
++	s_setreg_b32	hwreg(HW_REG_IB_STS), ttmp2
++
++	// Restore SQ_WAVE_STATUS.
++	s_and_b64	exec, exec, exec					// Restore STATUS.EXECZ, not writable by s_setreg_b32
++	s_and_b64	vcc, vcc, vcc						// Restore STATUS.VCCZ, not writable by s_setreg_b32
++	s_setreg_b32	hwreg(HW_REG_STATUS), s_save_status
++
++	s_rfe_b64	[ttmp0, ttmp1]
++
++L_SAVE:
+ 	//check whether there is mem_viol
+-	s_getreg_b32  	s_save_trapsts, hwreg(HW_REG_TRAPSTS)    		 				
+-	s_and_b32		s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK			
++	s_getreg_b32	s_save_trapsts, hwreg(HW_REG_TRAPSTS)
++	s_and_b32	s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK
+ 	s_cbranch_scc0	L_NO_PC_REWIND
+-    
++
+ 	//if so, need rewind PC assuming GDS operation gets NACKed
+-	s_mov_b32       s_save_tmp, 0															//clear mem_viol bit
+-	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT, 1), s_save_tmp	//clear mem_viol bit 
+-	s_and_b32 		s_save_pc_hi, s_save_pc_hi, 0x0000ffff    //pc[47:32]
+-	s_sub_u32 		s_save_pc_lo, s_save_pc_lo, 8             //pc[31:0]-8
+-	s_subb_u32 		s_save_pc_hi, s_save_pc_hi, 0x0			  // -scc
++	s_mov_b32	s_save_tmp, 0
++	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT, 1), s_save_tmp	//clear mem_viol bit
++	s_and_b32	s_save_pc_hi, s_save_pc_hi, 0x0000ffff			//pc[47:32]
++	s_sub_u32	s_save_pc_lo, s_save_pc_lo, 8				//pc[31:0]-8
++	s_subb_u32	s_save_pc_hi, s_save_pc_hi, 0x0
+ 
+ L_NO_PC_REWIND:
+-    s_mov_b32       s_save_tmp, 0															//clear saveCtx bit
+-	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp		//clear saveCtx bit   
+-
+-	//s_mov_b32		s_save_xnack_mask_lo,	xnack_mask_lo									//save XNACK_MASK  
+-	//s_mov_b32		s_save_xnack_mask_hi,	xnack_mask_hi
+-    s_getreg_b32	s_save_xnack_mask,  hwreg(HW_REG_SHADER_XNACK_MASK)  
+-	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE)					//save RCNT
+-	s_lshl_b32		s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT
+-	s_or_b32		s_save_pc_hi, s_save_pc_hi, s_save_tmp
+-	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE)	//save FIRST_REPLAY
+-	s_lshl_b32		s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
+-	s_or_b32		s_save_pc_hi, s_save_pc_hi, s_save_tmp
+-	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS)										//clear RCNT and FIRST_REPLAY in IB_STS
+-	s_and_b32		s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG
++	s_mov_b32	s_save_tmp, 0
++	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp	//clear saveCtx bit
++
++	s_getreg_b32	s_save_xnack_mask, hwreg(HW_REG_SHADER_XNACK_MASK)
++	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE)
++	s_lshl_b32	s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT
++	s_or_b32	s_save_pc_hi, s_save_pc_hi, s_save_tmp
++	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE)
++	s_lshl_b32	s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
++	s_or_b32	s_save_pc_hi, s_save_pc_hi, s_save_tmp
++	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT, SQ_WAVE_IB_STS_REPLAY_W64H_SIZE)
++	s_lshl_b32	s_save_tmp, s_save_tmp, S_SAVE_PC_HI_REPLAY_W64H_SHIFT
++	s_or_b32	s_save_pc_hi, s_save_pc_hi, s_save_tmp
++	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS)			//clear RCNT and FIRST_REPLAY and REPLAY_W64H in IB_STS
++	s_and_b32	s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG
+ 
+ 	s_setreg_b32	hwreg(HW_REG_IB_STS), s_save_tmp
+-    
+-	/*		inform SPI the readiness and wait for SPI's go signal */
+-	s_mov_b32		s_save_exec_lo,	exec_lo													//save EXEC and use EXEC for the go signal from SPI
+-	s_mov_b32		s_save_exec_hi,	exec_hi
+-	s_mov_b64		exec, 	0x0																//clear EXEC to get ready to receive
+-	if (EMU_RUN_HACK)
+-	
+-	else
+-		s_sendmsg	sendmsg(MSG_SAVEWAVE)													//send SPI a message and wait for SPI's write to EXEC  
+-	end
+-
+-  L_SLEEP:		
+-	s_sleep 0x2
+-	
+-	if (EMU_RUN_HACK)
+-																							
+-	else
+-		s_cbranch_execz	L_SLEEP                                                         
+-	end
+-
+-
+-	/*      setup Resource Contants    */
+-	if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE))	
+-		//calculate wd_addr using absolute thread id 
+-		v_readlane_b32 s_save_tmp, v9, 0
+-        //determine it is wave32 or wave64
+-        s_getreg_b32 	s_wave_size, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE)
+-        s_cmp_eq_u32    s_wave_size, 0
+-        s_cbranch_scc1  L_SAVE_WAVE32
+-        s_lshr_b32 s_save_tmp, s_save_tmp, 6 //SAVE WAVE64
+-        s_branch    L_SAVE_CON
+-    L_SAVE_WAVE32:
+-        s_lshr_b32 s_save_tmp, s_save_tmp, 5 //SAVE WAVE32
+-    L_SAVE_CON:
+-		s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE
+-		s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO
+-		s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI
+-		s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL		
+-	else
+-	end
+-	if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE))
+-		s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO
+-		s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI
+-		s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL		
+-	else
+-	end
+-	
+-	
+-	s_mov_b32		s_save_buf_rsrc0, 	s_save_spi_init_lo														//base_addr_lo
+-	s_and_b32		s_save_buf_rsrc1, 	s_save_spi_init_hi, 0x0000FFFF											//base_addr_hi
+-	s_or_b32		s_save_buf_rsrc1, 	s_save_buf_rsrc1,  S_SAVE_BUF_RSRC_WORD1_STRIDE
+-    s_mov_b32       s_save_buf_rsrc2,   0                                               						//NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited
+-	s_mov_b32		s_save_buf_rsrc3, 	S_SAVE_BUF_RSRC_WORD3_MISC
+-	s_and_b32		s_save_tmp,         s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK		
+-	s_lshr_b32		s_save_tmp,  		s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT)			//get ATC bit into position
+-	s_or_b32		s_save_buf_rsrc3, 	s_save_buf_rsrc3,  s_save_tmp											//or ATC
+-	s_and_b32		s_save_tmp,         s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK		
+-	s_lshr_b32		s_save_tmp,  		s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT)		//get MTYPE bits into position
+-	s_or_b32		s_save_buf_rsrc3, 	s_save_buf_rsrc3,  s_save_tmp											//or MTYPE	
+-	
+-	s_mov_b32		s_save_m0,			m0																	//save M0
+-	
+-	/* 		global mem offset			*/
+-	s_mov_b32		s_save_mem_offset, 	0x0																		//mem offset initial value = 0
+-    s_getreg_b32 	s_wave_size, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE) //get wave_save_size
+-    s_or_b32        s_wave_size, s_save_spi_init_hi,    s_wave_size                                             //share s_wave_size with exec_hi
+-
+-    /*      	save VGPRs	    */
+-	//////////////////////////////
+-  L_SAVE_VGPR:
+-  
+- 	s_mov_b32		exec_lo, 0xFFFFFFFF 											//need every thread from now on
+-    s_and_b32       m0, s_wave_size, 1
+-    s_cmp_eq_u32    m0, 1  
+-    s_cbranch_scc1  L_ENABLE_SAVE_VGPR_EXEC_HI   
+-    s_mov_b32		exec_hi, 0x00000000
+-    s_branch        L_SAVE_VGPR_NORMAL
+-  L_ENABLE_SAVE_VGPR_EXEC_HI:
+-	s_mov_b32		exec_hi, 0xFFFFFFFF
+-  L_SAVE_VGPR_NORMAL:	
+-	s_getreg_b32 	s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 					//vpgr_size
+-	//for wave32 and wave64, the num of vgpr function is the same?
+-    s_add_u32 		s_save_alloc_size, s_save_alloc_size, 1
+-	s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 2 						//Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)   //FIXME for GFX, zero is possible
+-    //determine it is wave32 or wave64
+-    s_and_b32       m0, s_wave_size, 1
+-    s_cmp_eq_u32    m0, 1
+-    s_cbranch_scc1  L_SAVE_VGPR_WAVE64
+-
+-    //zhenxu added it for save vgpr for wave32
+-	s_lshl_b32		s_save_buf_rsrc2,  s_save_alloc_size, 7							//NUM_RECORDS in bytes (32 threads*4)
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
+-	end
+-	
+-    s_mov_b32 		m0, 0x0 														//VGPR initial index value =0
+-	//s_set_gpr_idx_on  m0, 0x1														//M0[7:0] = M0[7:0] and M0[15:12] = 0x1
+-    //s_add_u32		s_save_alloc_size, s_save_alloc_size, 0x1000					//add 0x1000 since we compare m0 against it later, doesn't need this in gfx10
+-
+-  L_SAVE_VGPR_WAVE32_LOOP: 										
+-	v_movrels_b32 		v0, v0															//v0 = v[0+m0]	
+-	    
+-    if(USE_MTBUF_INSTEAD_OF_MUBUF)       
+-		tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-    else
+-		buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
+-	end
+-
+-    s_add_u32		m0, m0, 1														//next vgpr index
+-	s_add_u32		s_save_mem_offset, s_save_mem_offset, 128						//every buffer_store_dword does 128 bytes
+-	s_cmp_lt_u32 	m0,	s_save_alloc_size 											//scc = (m0 < s_save_alloc_size) ? 1 : 0
+-	s_cbranch_scc1 	L_SAVE_VGPR_WAVE32_LOOP												//VGPR save is complete?
+-    s_branch    L_SAVE_LDS
+-    //save vgpr for wave32 ends
+-
+-  L_SAVE_VGPR_WAVE64:
+-	s_lshl_b32		s_save_buf_rsrc2,  s_save_alloc_size, 8							//NUM_RECORDS in bytes (64 threads*4)
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
+-	end
+-	
+-    s_mov_b32 		m0, 0x0 														//VGPR initial index value =0
+-	//s_set_gpr_idx_on  m0, 0x1														//M0[7:0] = M0[7:0] and M0[15:12] = 0x1
+-    //s_add_u32		s_save_alloc_size, s_save_alloc_size, 0x1000					//add 0x1000 since we compare m0 against it later, doesn't need this in gfx10
+-
+-  L_SAVE_VGPR_WAVE64_LOOP: 										
+-	v_movrels_b32 		v0, v0															//v0 = v[0+m0]	
+-	    
+-    if(USE_MTBUF_INSTEAD_OF_MUBUF)       
+-		tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-    else
+-		buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
+-	end
+-
+-    s_add_u32		m0, m0, 1														//next vgpr index
+-	s_add_u32		s_save_mem_offset, s_save_mem_offset, 256						//every buffer_store_dword does 256 bytes
+-	s_cmp_lt_u32 	m0,	s_save_alloc_size 											//scc = (m0 < s_save_alloc_size) ? 1 : 0
+-	s_cbranch_scc1 	L_SAVE_VGPR_WAVE64_LOOP												//VGPR save is complete?
+-	//s_set_gpr_idx_off
+-    //
+-    //Below part will be the save shared vgpr part (new for gfx10)
+-    s_getreg_b32 	s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) 			//shared_vgpr_size
+-    s_and_b32		s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF				//shared_vgpr_size is zero?
+-    s_cbranch_scc0	L_SAVE_LDS													    //no shared_vgpr used? jump to L_SAVE_LDS
+-    s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 3 						//Number of SHARED_VGPRs = shared_vgpr_size * 8    (non-zero value)
+-    //m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count.
+-    //save shared_vgpr will start from the index of m0
+-    s_add_u32       s_save_alloc_size, s_save_alloc_size, m0
+-    s_mov_b32		exec_lo, 0xFFFFFFFF
+-    s_mov_b32		exec_hi, 0x00000000
+-    L_SAVE_SHARED_VGPR_WAVE64_LOOP: 										
+-	v_movrels_b32 		v0, v0															//v0 = v[0+m0]	
+-	buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
+-    s_add_u32		m0, m0, 1														//next vgpr index
+-	s_add_u32		s_save_mem_offset, s_save_mem_offset, 128						//every buffer_store_dword does 256 bytes
+-	s_cmp_lt_u32 	m0,	s_save_alloc_size 											//scc = (m0 < s_save_alloc_size) ? 1 : 0
+-	s_cbranch_scc1 	L_SAVE_SHARED_VGPR_WAVE64_LOOP									//SHARED_VGPR save is complete?
+-    
+-	/*      	save LDS	    */
+-	//////////////////////////////
+-  L_SAVE_LDS:
+-
+-    //Only check the first wave need LDS
+-	/*      the first wave in the threadgroup    */
+-	s_barrier																		//FIXME  not performance-optimal "LDS is used? wait for other waves in the same TG" 
+-	s_and_b32		s_save_tmp, s_wave_size, S_SAVE_SPI_INIT_FIRST_WAVE_MASK								//exec is still used here
+-	s_cbranch_scc0	L_SAVE_SGPR
+-	
+-	s_mov_b32		exec_lo, 0xFFFFFFFF 											//need every thread from now on
+-    s_and_b32       m0, s_wave_size, 1
+-    s_cmp_eq_u32    m0, 1
+-    s_cbranch_scc1  L_ENABLE_SAVE_LDS_EXEC_HI   
+-    s_mov_b32		exec_hi, 0x00000000
+-    s_branch        L_SAVE_LDS_NORMAL
+-  L_ENABLE_SAVE_LDS_EXEC_HI:
+-	s_mov_b32		exec_hi, 0xFFFFFFFF
+-  L_SAVE_LDS_NORMAL:	
+-	s_getreg_b32 	s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) 			//lds_size
+-	s_and_b32		s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF				//lds_size is zero?
+-	s_cbranch_scc0	L_SAVE_SGPR														//no lds used? jump to L_SAVE_VGPR
+-	s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 6 						//LDS size in dwords = lds_size * 64dw
+-	s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 2 						//LDS size in bytes
+-	s_mov_b32		s_save_buf_rsrc2,  s_save_alloc_size  							//NUM_RECORDS in bytes
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
+-	end
+-
+-    //load 0~63*4(byte address) to vgpr v15
+-    v_mbcnt_lo_u32_b32 v0, -1, 0
+-    v_mbcnt_hi_u32_b32 v0, -1, v0
+-    v_mul_u32_u24 v0, 4, v0
+-
+-    s_and_b32       m0, s_wave_size, 1
+-    s_cmp_eq_u32    m0, 1
+-    s_mov_b32 		m0, 0x0
+-    s_cbranch_scc1  L_SAVE_LDS_LOOP_W64
+-
+-  L_SAVE_LDS_LOOP_W32:									
+-	if (SAVE_LDS)
+-    ds_read_b32 v1, v0
+-    s_waitcnt 0														    //ensure data ready
+-    buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
+-	//buffer_store_lds_dword	s_save_buf_rsrc0, s_save_mem_offset lds:1               //save lds to memory doesn't exist in 10
+-	end
+-	s_add_u32		m0, m0, 128															//every buffer_store_lds does 128 bytes
+-	s_add_u32		s_save_mem_offset, s_save_mem_offset, 128							//mem offset increased by 128 bytes
+-    v_add_nc_u32    v0, v0, 128
+-	s_cmp_lt_u32	m0, s_save_alloc_size												//scc=(m0 < s_save_alloc_size) ? 1 : 0
+-	s_cbranch_scc1  L_SAVE_LDS_LOOP_W32													//LDS save is complete?
+-    s_branch        L_SAVE_SGPR
+-
+-  L_SAVE_LDS_LOOP_W64:									
+-	if (SAVE_LDS)
+-    ds_read_b32 v1, v0
+-    s_waitcnt 0														    //ensure data ready
+-    buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
+-	//buffer_store_lds_dword	s_save_buf_rsrc0, s_save_mem_offset lds:1               //save lds to memory doesn't exist in 10
+-	end
+-	s_add_u32		m0, m0, 256															//every buffer_store_lds does 256 bytes
+-	s_add_u32		s_save_mem_offset, s_save_mem_offset, 256							//mem offset increased by 256 bytes
+-    v_add_nc_u32    v0, v0, 256
+-	s_cmp_lt_u32	m0, s_save_alloc_size												//scc=(m0 < s_save_alloc_size) ? 1 : 0
+-	s_cbranch_scc1  L_SAVE_LDS_LOOP_W64													//LDS save is complete?
+-   
+-	
+-	/*      	save SGPRs	    */
+-	//////////////////////////////
+-	//s_getreg_b32 	s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) 				//spgr_size
+-	//s_add_u32 		s_save_alloc_size, s_save_alloc_size, 1
+-	//s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 4 						//Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value) 
+-	//s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 3 						//In gfx10, Number of SGPRs = (sgpr_size + 1) * 8   (non-zero value) 
+-  L_SAVE_SGPR:
+-    //need to look at it is wave32 or wave64
+-    s_and_b32       m0, s_wave_size, 1
+-    s_cmp_eq_u32    m0, 1
+-    s_cbranch_scc1  L_SAVE_SGPR_VMEM_WAVE64
+-    if (SGPR_SAVE_USE_SQC)
+-		s_lshl_b32		s_save_buf_rsrc2,	s_sgpr_save_num, 2					//NUM_RECORDS in bytes
+-    else
+-        s_lshl_b32		s_save_buf_rsrc2,	s_sgpr_save_num, 7					//NUM_RECORDS in bytes (32 threads)
+-    end
+-    s_branch    L_SAVE_SGPR_CONT    
+-  L_SAVE_SGPR_VMEM_WAVE64:
+-	if (SGPR_SAVE_USE_SQC)
+-		s_lshl_b32		s_save_buf_rsrc2,	s_sgpr_save_num, 2					//NUM_RECORDS in bytes 
+-	else
+-		s_lshl_b32		s_save_buf_rsrc2,	s_sgpr_save_num, 8					//NUM_RECORDS in bytes (64 threads)
+-	end
+-  L_SAVE_SGPR_CONT:
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
+-	end
+-	
+-	//s_mov_b32 		m0, 0x0 														//SGPR initial index value =0		
+-    //s_nop           0x0                                                             //Manually inserted wait states
+-	
+-    s_and_b32       m0, s_wave_size, 1
+-    s_cmp_eq_u32    m0, 1
+-    
+-    s_mov_b32 		m0, 0x0 														//SGPR initial index value =0		
+-    s_nop           0x0                                                             //Manually inserted wait states
+-
+-    s_cbranch_scc1  L_SAVE_SGPR_LOOP_WAVE64
+-
+-  L_SAVE_SGPR_LOOP_WAVE32: 										
+-	s_movrels_b32 	s0, s0 															//s0 = s[0+m0]
+-    //zhenxu, adding one more argument to save sgpr function, this is only for vmem, using sqc is not change    
+-	write_sgpr_to_mem_wave32(s0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)							//PV: the best performance should be using s_buffer_store_dwordx4
+-	s_add_u32		m0, m0, 1														//next sgpr index
+-	s_cmp_lt_u32 	m0, s_sgpr_save_num 											//scc = (m0 < s_sgpr_save_num) ? 1 : 0
+-	s_cbranch_scc1 	L_SAVE_SGPR_LOOP_WAVE32												//SGPR save is complete?
+-    s_branch    L_SAVE_HWREG
+-
+-  L_SAVE_SGPR_LOOP_WAVE64: 										
+-	s_movrels_b32 	s0, s0 															//s0 = s[0+m0]
+-    //zhenxu, adding one more argument to save sgpr function, this is only for vmem, using sqc is not change    
+-	write_sgpr_to_mem_wave64(s0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)							//PV: the best performance should be using s_buffer_store_dwordx4
+-	s_add_u32		m0, m0, 1														//next sgpr index
+-	s_cmp_lt_u32 	m0, s_sgpr_save_num 											//scc = (m0 < s_sgpr_save_num) ? 1 : 0
+-	s_cbranch_scc1 	L_SAVE_SGPR_LOOP_WAVE64												//SGPR save is complete?
+-
+-	
+-	/* 		save HW registers	*/
+-	//////////////////////////////
+-  L_SAVE_HWREG:
+-    s_mov_b32		s_save_buf_rsrc2, 0x4								//NUM_RECORDS	in bytes
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
+-	end
+-
+-    s_and_b32       m0, s_wave_size, 1
+-    s_cmp_eq_u32    m0, 1
+-    s_cbranch_scc1  L_SAVE_HWREG_WAVE64
+-	
+-	write_sgpr_to_mem_wave32(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)					//M0
+-
+-	if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME))      
+-		s_add_u32 s_save_pc_lo, s_save_pc_lo, 4             //pc[31:0]+4
+-		s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0			//carry bit over
+-	end
+-
+-	write_sgpr_to_mem_wave32(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)					//PC
+-	write_sgpr_to_mem_wave32(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
+-	write_sgpr_to_mem_wave32(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)				//EXEC
+-	write_sgpr_to_mem_wave32(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
+-	write_sgpr_to_mem_wave32(s_save_status, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)				//STATUS 
+-	
+-	//s_save_trapsts conflicts with s_save_alloc_size
+-	s_getreg_b32    s_save_trapsts, hwreg(HW_REG_TRAPSTS)
+-	write_sgpr_to_mem_wave32(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)				//TRAPSTS
+-	
+-	//write_sgpr_to_mem_wave32(s_save_xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)			//XNACK_MASK_LO
+-	write_sgpr_to_mem_wave32(s_save_xnack_mask, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)			//XNACK_MASK_HI
+-	
+-	//use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2
+-	s_getreg_b32 	s_save_m0, hwreg(HW_REG_MODE)																						//MODE
+-	write_sgpr_to_mem_wave32(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
+-    if(SAVE_RESTORE_HWID_DDID)
+-    s_getreg_b32 	s_save_m0, hwreg(HW_REG_HW_ID1)																						//HW_ID1, handler records the SE/SA/WGP/SIMD/wave of the original wave
+-    write_sgpr_to_mem_wave32(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
+-    end
+-    s_branch   L_S_PGM_END_SAVED
+-
+-  L_SAVE_HWREG_WAVE64:
+-    write_sgpr_to_mem_wave64(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)					//M0
+-
+-	if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME))      
+-		s_add_u32 s_save_pc_lo, s_save_pc_lo, 4             //pc[31:0]+4
+-		s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0			//carry bit over
+-	end
+-
+-	write_sgpr_to_mem_wave64(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)					//PC
+-	write_sgpr_to_mem_wave64(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
+-	write_sgpr_to_mem_wave64(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)				//EXEC
+-	write_sgpr_to_mem_wave64(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
+-	write_sgpr_to_mem_wave64(s_save_status, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)				//STATUS 
+-	
+-	//s_save_trapsts conflicts with s_save_alloc_size
+-	s_getreg_b32    s_save_trapsts, hwreg(HW_REG_TRAPSTS)
+-	write_sgpr_to_mem_wave64(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)				//TRAPSTS
+-	
+-	//write_sgpr_to_mem_wave64(s_save_xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)			//XNACK_MASK_LO
+-	write_sgpr_to_mem_wave64(s_save_xnack_mask, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)			//XNACK_MASK_HI
+-	
+-	//use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2
+-	s_getreg_b32 	s_save_m0, hwreg(HW_REG_MODE)																						//MODE
+-	write_sgpr_to_mem_wave64(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
+-
+-
+-    if(SAVE_RESTORE_HWID_DDID)
+-    s_getreg_b32 	s_save_m0, hwreg(HW_REG_HW_ID1)																						//HW_ID1, handler records the SE/SA/WGP/SIMD/wave of the original wave
+-    write_sgpr_to_mem_wave64(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
+-
+-	/* 		save DDID	*/
+-	//////////////////////////////
+-  L_SAVE_DDID:
+-    //EXEC has been saved, no vector inst following
+-    s_mov_b32	exec_lo, 0x80000000    //Set MSB to 1. Cleared when draw index is returned
+-    s_sendmsg sendmsg(MSG_GET_DDID)
+-
+-  L_WAIT_DDID_LOOP:    
+-    s_nop		7			// sleep a bit
+-    s_bitcmp0_b32 exec_lo, 31	// test to see if MSB is cleared, meaning done
+-    s_cbranch_scc0	L_WAIT_DDID_LOOP
+-
+-    s_mov_b32	s_save_m0, exec_lo
+-
+-
+-    s_mov_b32		s_save_buf_rsrc2, 0x4								//NUM_RECORDS	in bytes
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
+-	end
+-    s_and_b32       m0, s_wave_size, 1
+-    s_cmp_eq_u32    m0, 1
+-    s_cbranch_scc1  L_SAVE_DDID_WAVE64
+-
+-    write_sgpr_to_mem_wave32(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) 
+-
+-  L_SAVE_DDID_WAVE64:
+-    write_sgpr_to_mem_wave64(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) 
+-
+-    end
+-   
+-  L_S_PGM_END_SAVED:
+-	/*     S_PGM_END_SAVED  */    							//FIXME  graphics ONLY
+-	if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT))	
+-		s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff    //pc[47:32]
+-		s_add_u32 s_save_pc_lo, s_save_pc_lo, 4             //pc[31:0]+4
+-		s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0			//carry bit over
+-		s_rfe_b64 s_save_pc_lo                              //Return to the main shader program
+-	else
+-	end
+-
+-	
+-    s_branch	L_END_PGM
+-	
+-
+-				
+-/**************************************************************************/
+-/*                     	restore routine						              */
+-/**************************************************************************/
++
++	/* inform SPI the readiness and wait for SPI's go signal */
++	s_mov_b32	s_save_exec_lo, exec_lo					//save EXEC and use EXEC for the go signal from SPI
++	s_mov_b32	s_save_exec_hi, exec_hi
++	s_mov_b64	exec, 0x0						//clear EXEC to get ready to receive
++
++	s_sendmsg	sendmsg(MSG_SAVEWAVE)					//send SPI a message and wait for SPI's write to EXEC
++
++L_SLEEP:
++	// sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause
++	// SQ hang, since the 7,8th wave could not get arbit to exec inst, while
++	// other waves are stuck into the sleep-loop and waiting for wrexec!=0
++	s_sleep		0x2
++	s_cbranch_execz	L_SLEEP
++
++	/* setup Resource Contants */
++	s_mov_b32	s_save_buf_rsrc0, s_save_spi_init_lo			//base_addr_lo
++	s_and_b32	s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF	//base_addr_hi
++	s_or_b32	s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE
++	s_mov_b32	s_save_buf_rsrc2, 0					//NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited
++	s_mov_b32	s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC
++	s_and_b32	s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK
++	s_lshr_b32	s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT)
++	s_or_b32	s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp		//or ATC
++	s_and_b32	s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK
++	s_lshr_b32	s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT)
++	s_or_b32	s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp		//or MTYPE
++
++	s_mov_b32	s_save_m0, m0
++
++	/* global mem offset */
++	s_mov_b32	s_save_mem_offset, 0x0
++	s_getreg_b32	s_wave_size, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE)
++	s_lshl_b32	s_wave_size, s_wave_size, S_WAVE_SIZE
++	s_or_b32	s_wave_size, s_save_spi_init_hi, s_wave_size		//share s_wave_size with exec_hi, it's at bit25
++
++	/* save HW registers */
++
++L_SAVE_HWREG:
++	// HWREG SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)
++	get_vgpr_size_bytes(s_save_mem_offset, s_wave_size)
++	get_svgpr_size_bytes(s_save_tmp)
++	s_add_u32	s_save_mem_offset, s_save_mem_offset, s_save_tmp
++	s_add_u32	s_save_mem_offset, s_save_mem_offset, get_sgpr_size_bytes()
++
++	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
++
++	write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)
++	write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset)
++	write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset)
++	write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset)
++	write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset)
++	write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset)
++
++	s_getreg_b32	s_save_trapsts, hwreg(HW_REG_TRAPSTS)
++	write_hwreg_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset)
++	write_hwreg_to_mem(s_save_xnack_mask, s_save_buf_rsrc0, s_save_mem_offset)
++
++	s_getreg_b32	s_save_m0, hwreg(HW_REG_MODE)
++	write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)
++
++	/* the first wave in the threadgroup */
++	s_and_b32	s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK
++	s_mov_b32	s_save_exec_hi, 0x0
++	s_or_b32	s_save_exec_hi, s_save_tmp, s_save_exec_hi		// save first wave bit to s_save_exec_hi.bits[26]
++
++	/* save SGPRs */
++	// Save SGPR before LDS save, then the s0 to s4 can be used during LDS save...
++
++	// SGPR SR memory offset : size(VGPR)+size(SVGPR)
++	get_vgpr_size_bytes(s_save_mem_offset, s_wave_size)
++	get_svgpr_size_bytes(s_save_tmp)
++	s_add_u32	s_save_mem_offset, s_save_mem_offset, s_save_tmp
++	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
++
++	// backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0
++	s_mov_b32	s_save_xnack_mask, s_save_buf_rsrc0
++	s_add_u32	s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset
++	s_addc_u32	s_save_buf_rsrc1, s_save_buf_rsrc1, 0
++
++	s_mov_b32	m0, 0x0							//SGPR initial index value =0
++	s_nop		0x0							//Manually inserted wait states
++L_SAVE_SGPR_LOOP:
++	// SGPR is allocated in 16 SGPR granularity
++	s_movrels_b64	s0, s0							//s0 = s[0+m0], s1 = s[1+m0]
++	s_movrels_b64	s2, s2							//s2 = s[2+m0], s3 = s[3+m0]
++	s_movrels_b64	s4, s4							//s4 = s[4+m0], s5 = s[5+m0]
++	s_movrels_b64	s6, s6							//s6 = s[6+m0], s7 = s[7+m0]
++	s_movrels_b64	s8, s8							//s8 = s[8+m0], s9 = s[9+m0]
++	s_movrels_b64	s10, s10						//s10 = s[10+m0], s11 = s[11+m0]
++	s_movrels_b64	s12, s12						//s12 = s[12+m0], s13 = s[13+m0]
++	s_movrels_b64	s14, s14						//s14 = s[14+m0], s15 = s[15+m0]
++
++	write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset)
++	s_add_u32	m0, m0, 16						//next sgpr index
++	s_cmp_lt_u32	m0, 96							//scc = (m0 < first 96 SGPR) ? 1 : 0
++	s_cbranch_scc1	L_SAVE_SGPR_LOOP					//first 96 SGPR save is complete?
++
++	//save the rest 10 SGPR
++	s_movrels_b64	s0, s0							//s0 = s[0+m0], s1 = s[1+m0]
++	s_movrels_b64	s2, s2							//s2 = s[2+m0], s3 = s[3+m0]
++	s_movrels_b64	s4, s4							//s4 = s[4+m0], s5 = s[5+m0]
++	s_movrels_b64	s6, s6							//s6 = s[6+m0], s7 = s[7+m0]
++	s_movrels_b64	s8, s8							//s8 = s[8+m0], s9 = s[9+m0]
++	write_10sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset)
++
++	// restore s_save_buf_rsrc0,1
++	s_mov_b32	s_save_buf_rsrc0, s_save_xnack_mask
++
++	/* save first 4 VGPR, then LDS save could use   */
++	// each wave will alloc 4 vgprs at least...
++
++	s_mov_b32	s_save_mem_offset, 0
++ 	s_mov_b32	exec_lo, 0xFFFFFFFF					//need every thread from now on
++	s_lshr_b32	m0, s_wave_size, S_WAVE_SIZE
++	s_and_b32	m0, m0, 1
++	s_cmp_eq_u32	m0, 1
++	s_cbranch_scc1	L_ENABLE_SAVE_4VGPR_EXEC_HI
++	s_mov_b32	exec_hi, 0x00000000
++	s_branch	L_SAVE_4VGPR_WAVE32
++L_ENABLE_SAVE_4VGPR_EXEC_HI:
++	s_mov_b32	exec_hi, 0xFFFFFFFF
++	s_branch	L_SAVE_4VGPR_WAVE64
++L_SAVE_4VGPR_WAVE32:
++	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
++
++	// VGPR Allocated in 4-GPR granularity
++
++	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
++	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128
++	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*2
++	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*3
++	s_branch	L_SAVE_LDS
++
++L_SAVE_4VGPR_WAVE64:
++	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
++
++	// VGPR Allocated in 4-GPR granularity
++
++	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
++	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256
++	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2
++	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
++
++	/* save LDS */
++
++L_SAVE_LDS:
++	// Change EXEC to all threads...
++	s_mov_b32	exec_lo, 0xFFFFFFFF					//need every thread from now on
++	s_lshr_b32	m0, s_wave_size, S_WAVE_SIZE
++	s_and_b32	m0, m0, 1
++	s_cmp_eq_u32	m0, 1
++	s_cbranch_scc1	L_ENABLE_SAVE_LDS_EXEC_HI
++	s_mov_b32	exec_hi, 0x00000000
++	s_branch	L_SAVE_LDS_NORMAL
++L_ENABLE_SAVE_LDS_EXEC_HI:
++	s_mov_b32	exec_hi, 0xFFFFFFFF
++L_SAVE_LDS_NORMAL:
++	s_getreg_b32	s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE)
++	s_and_b32	s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF	//lds_size is zero?
++	s_cbranch_scc0	L_SAVE_LDS_DONE						//no lds used? jump to L_SAVE_DONE
++
++	s_barrier								//LDS is used? wait for other waves in the same TG
++	s_and_b32	s_save_tmp, s_save_exec_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK
++	s_cbranch_scc0	L_SAVE_LDS_DONE
++
++	// first wave do LDS save;
++
++	s_lshl_b32	s_save_alloc_size, s_save_alloc_size, 6			//LDS size in dwords = lds_size * 64dw
++	s_lshl_b32	s_save_alloc_size, s_save_alloc_size, 2			//LDS size in bytes
++	s_mov_b32	s_save_buf_rsrc2, s_save_alloc_size			//NUM_RECORDS in bytes
++
++	// LDS at offset: size(VGPR)+size(SVGPR)+SIZE(SGPR)+SIZE(HWREG)
++	//
++	get_vgpr_size_bytes(s_save_mem_offset, s_wave_size)
++	get_svgpr_size_bytes(s_save_tmp)
++	s_add_u32	s_save_mem_offset, s_save_mem_offset, s_save_tmp
++	s_add_u32	s_save_mem_offset, s_save_mem_offset, get_sgpr_size_bytes()
++	s_add_u32	s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes()
++
++	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
++
++	//load 0~63*4(byte address) to vgpr v0
++	v_mbcnt_lo_u32_b32	v0, -1, 0
++	v_mbcnt_hi_u32_b32	v0, -1, v0
++	v_mul_u32_u24	v0, 4, v0
++
++	s_lshr_b32	m0, s_wave_size, S_WAVE_SIZE
++	s_and_b32	m0, m0, 1
++	s_cmp_eq_u32	m0, 1
++	s_mov_b32	m0, 0x0
++	s_cbranch_scc1	L_SAVE_LDS_W64
++
++L_SAVE_LDS_W32:
++	s_mov_b32	s3, 128
++	s_nop		0
++	s_nop		0
++	s_nop		0
++L_SAVE_LDS_LOOP_W32:
++	ds_read_b32	v1, v0
++	s_waitcnt	0
++	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
++
++	s_add_u32	m0, m0, s3						//every buffer_store_lds does 256 bytes
++	s_add_u32	s_save_mem_offset, s_save_mem_offset, s3
++	v_add_nc_u32	v0, v0, 128						//mem offset increased by 128 bytes
++	s_cmp_lt_u32	m0, s_save_alloc_size					//scc=(m0 < s_save_alloc_size) ? 1 : 0
++	s_cbranch_scc1	L_SAVE_LDS_LOOP_W32					//LDS save is complete?
++
++	s_branch	L_SAVE_LDS_DONE
++
++L_SAVE_LDS_W64:
++	s_mov_b32	s3, 256
++	s_nop		0
++	s_nop		0
++	s_nop		0
++L_SAVE_LDS_LOOP_W64:
++	ds_read_b32	v1, v0
++	s_waitcnt	0
++	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
++
++	s_add_u32	m0, m0, s3						//every buffer_store_lds does 256 bytes
++	s_add_u32	s_save_mem_offset, s_save_mem_offset, s3
++	v_add_nc_u32	v0, v0, 256						//mem offset increased by 256 bytes
++	s_cmp_lt_u32	m0, s_save_alloc_size					//scc=(m0 < s_save_alloc_size) ? 1 : 0
++	s_cbranch_scc1	L_SAVE_LDS_LOOP_W64					//LDS save is complete?
++
++L_SAVE_LDS_DONE:
++	/* save VGPRs  - set the Rest VGPRs */
++L_SAVE_VGPR:
++	// VGPR SR memory offset: 0
++	s_mov_b32	exec_lo, 0xFFFFFFFF					//need every thread from now on
++	s_lshr_b32	m0, s_wave_size, S_WAVE_SIZE
++	s_and_b32	m0, m0, 1
++	s_cmp_eq_u32	m0, 1
++	s_cbranch_scc1	L_ENABLE_SAVE_VGPR_EXEC_HI
++	s_mov_b32	s_save_mem_offset, (0+128*4)				// for the rest VGPRs
++	s_mov_b32	exec_hi, 0x00000000
++	s_branch	L_SAVE_VGPR_NORMAL
++L_ENABLE_SAVE_VGPR_EXEC_HI:
++	s_mov_b32	s_save_mem_offset, (0+256*4)				// for the rest VGPRs
++	s_mov_b32	exec_hi, 0xFFFFFFFF
++L_SAVE_VGPR_NORMAL:
++	s_getreg_b32	s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE)
++	s_add_u32	s_save_alloc_size, s_save_alloc_size, 1
++	s_lshl_b32	s_save_alloc_size, s_save_alloc_size, 2			//Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)
++	//determine it is wave32 or wave64
++	s_lshr_b32	m0, s_wave_size, S_WAVE_SIZE
++	s_and_b32	m0, m0, 1
++	s_cmp_eq_u32	m0, 1
++	s_cbranch_scc1	L_SAVE_VGPR_WAVE64
++
++	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
++
++	// VGPR Allocated in 4-GPR granularity
++
++	// VGPR store using dw burst
++	s_mov_b32	m0, 0x4							//VGPR initial index value =4
++	s_cmp_lt_u32	m0, s_save_alloc_size
++	s_cbranch_scc0	L_SAVE_VGPR_END
++
++L_SAVE_VGPR_W32_LOOP:
++	v_movrels_b32	v0, v0							//v0 = v[0+m0]
++	v_movrels_b32	v1, v1							//v1 = v[1+m0]
++	v_movrels_b32	v2, v2							//v2 = v[2+m0]
++	v_movrels_b32	v3, v3							//v3 = v[3+m0]
++
++	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
++	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128
++	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*2
++	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*3
++
++	s_add_u32	m0, m0, 4						//next vgpr index
++	s_add_u32	s_save_mem_offset, s_save_mem_offset, 128*4		//every buffer_store_dword does 128 bytes
++	s_cmp_lt_u32	m0, s_save_alloc_size					//scc = (m0 < s_save_alloc_size) ? 1 : 0
++	s_cbranch_scc1	L_SAVE_VGPR_W32_LOOP					//VGPR save is complete?
++
++	s_branch	L_SAVE_VGPR_END
++
++L_SAVE_VGPR_WAVE64:
++	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
++
++	// VGPR store using dw burst
++	s_mov_b32	m0, 0x4							//VGPR initial index value =4
++	s_cmp_lt_u32	m0, s_save_alloc_size
++	s_cbranch_scc0	L_SAVE_VGPR_END
++
++L_SAVE_VGPR_W64_LOOP:
++	v_movrels_b32	v0, v0							//v0 = v[0+m0]
++	v_movrels_b32	v1, v1							//v1 = v[1+m0]
++	v_movrels_b32	v2, v2							//v2 = v[2+m0]
++	v_movrels_b32	v3, v3							//v3 = v[3+m0]
++
++	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
++	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256
++	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2
++	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
++
++	s_add_u32	m0, m0, 4						//next vgpr index
++	s_add_u32	s_save_mem_offset, s_save_mem_offset, 256*4		//every buffer_store_dword does 256 bytes
++	s_cmp_lt_u32	m0, s_save_alloc_size					//scc = (m0 < s_save_alloc_size) ? 1 : 0
++	s_cbranch_scc1	L_SAVE_VGPR_W64_LOOP					//VGPR save is complete?
++
++	//Below part will be the save shared vgpr part (new for gfx10)
++	s_getreg_b32	s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE)
++	s_and_b32	s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF	//shared_vgpr_size is zero?
++	s_cbranch_scc0	L_SAVE_VGPR_END						//no shared_vgpr used? jump to L_SAVE_LDS
++	s_lshl_b32	s_save_alloc_size, s_save_alloc_size, 3			//Number of SHARED_VGPRs = shared_vgpr_size * 8    (non-zero value)
++	//m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count.
++	//save shared_vgpr will start from the index of m0
++	s_add_u32	s_save_alloc_size, s_save_alloc_size, m0
++	s_mov_b32	exec_lo, 0xFFFFFFFF
++	s_mov_b32	exec_hi, 0x00000000
++L_SAVE_SHARED_VGPR_WAVE64_LOOP:
++	v_movrels_b32	v0, v0							//v0 = v[0+m0]
++	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
++	s_add_u32	m0, m0, 1						//next vgpr index
++	s_add_u32	s_save_mem_offset, s_save_mem_offset, 128
++	s_cmp_lt_u32	m0, s_save_alloc_size					//scc = (m0 < s_save_alloc_size) ? 1 : 0
++	s_cbranch_scc1	L_SAVE_SHARED_VGPR_WAVE64_LOOP				//SHARED_VGPR save is complete?
++
++L_SAVE_VGPR_END:
++	s_branch	L_END_PGM
+ 
+ L_RESTORE:
+-    /*      Setup Resource Contants    */
+-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))
+-		//calculate wd_addr using absolute thread id
+-		v_readlane_b32 s_restore_tmp, v9, 0
+-        //determine it is wave32 or wave64
+-        s_getreg_b32 	s_restore_size, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE) //change to ttmp13
+-        s_cmp_eq_u32    s_restore_size, 0
+-        s_cbranch_scc1  L_RESTORE_WAVE32
+-        s_lshr_b32 s_restore_tmp, s_restore_tmp, 6 //SAVE WAVE64
+-        s_branch    L_RESTORE_CON
+-    L_RESTORE_WAVE32:
+-        s_lshr_b32 s_restore_tmp, s_restore_tmp, 5 //SAVE WAVE32
+-    L_RESTORE_CON:
+-		s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE
+-		s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO
+-		s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI
+-		s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL	
+-	else
+-	end
+-	
+-    s_mov_b32		s_restore_buf_rsrc0, 	s_restore_spi_init_lo															//base_addr_lo
+-	s_and_b32		s_restore_buf_rsrc1, 	s_restore_spi_init_hi, 0x0000FFFF												//base_addr_hi
+-	s_or_b32		s_restore_buf_rsrc1, 	s_restore_buf_rsrc1,  S_RESTORE_BUF_RSRC_WORD1_STRIDE
+-    s_mov_b32       s_restore_buf_rsrc2,   	0                                               								//NUM_RECORDS initial value = 0 (in bytes)
+-	s_mov_b32		s_restore_buf_rsrc3, 	S_RESTORE_BUF_RSRC_WORD3_MISC
+-	s_and_b32		s_restore_tmp,         	s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK		
+-	s_lshr_b32		s_restore_tmp,  		s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT)		//get ATC bit into position
+-	s_or_b32		s_restore_buf_rsrc3, 	s_restore_buf_rsrc3,  s_restore_tmp												//or ATC
+-	s_and_b32		s_restore_tmp,         	s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK		
+-	s_lshr_b32		s_restore_tmp,  		s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT)	//get MTYPE bits into position
+-	s_or_b32		s_restore_buf_rsrc3, 	s_restore_buf_rsrc3,  s_restore_tmp												//or MTYPE
+-    //determine it is wave32 or wave64
+-    s_getreg_b32 	s_restore_size, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE)
+-    s_or_b32        s_restore_size, s_restore_spi_init_hi,    s_restore_size                                             //share s_wave_size with exec_hi
+-	
+-	/* 		global mem offset			*/
+-	s_mov_b32		s_restore_mem_offset, 0x0								//mem offset initial value = 0
+-
+-        /*      	restore VGPRs	    */
+-	//////////////////////////////
+-  L_RESTORE_VGPR:
+-  
+- 	s_mov_b32		exec_lo, 0xFFFFFFFF 													//need every thread from now on   //be consistent with SAVE although can be moved ahead
+-    s_and_b32       m0, s_restore_size, 1
+-    s_cmp_eq_u32    m0, 1
+-    s_cbranch_scc1  L_ENABLE_RESTORE_VGPR_EXEC_HI   
+-    s_mov_b32		exec_hi, 0x00000000
+-    s_branch        L_RESTORE_VGPR_NORMAL
+-  L_ENABLE_RESTORE_VGPR_EXEC_HI:
+-	s_mov_b32		exec_hi, 0xFFFFFFFF
+-  L_RESTORE_VGPR_NORMAL:	
+-	s_getreg_b32 	s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 	//vpgr_size
+-	s_add_u32 		s_restore_alloc_size, s_restore_alloc_size, 1
+-	s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 2 							//Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)
+-    //determine it is wave32 or wave64
+-    s_and_b32       m0, s_restore_size, 1
+-    s_cmp_eq_u32    m0, 1
+-    s_cbranch_scc1  L_RESTORE_VGPR_WAVE64
+-
+-    s_lshl_b32		s_restore_buf_rsrc2,  s_restore_alloc_size, 7						    //NUM_RECORDS in bytes (32 threads*4)
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
+-	end	
+-
+-	s_mov_b32		s_restore_mem_offset_save, s_restore_mem_offset							// restore start with v1, v0 will be the last
+-	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 128
+-    s_mov_b32 		m0, 1 																	//VGPR initial index value = 1
+-	//s_set_gpr_idx_on  m0, 0x8																//M0[7:0] = M0[7:0] and M0[15:12] = 0x8
+-    //s_add_u32		s_restore_alloc_size, s_restore_alloc_size, 0x8000						//add 0x8000 since we compare m0 against it later, might not need this in gfx10	
+-
+-  L_RESTORE_VGPR_WAVE32_LOOP: 										
+-    if(USE_MTBUF_INSTEAD_OF_MUBUF)       
+-		tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-    else
+-		buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset	slc:1 glc:1	
+-	end
+-	s_waitcnt		vmcnt(0)																//ensure data ready
+-	v_movreld_b32		v0, v0																	//v[0+m0] = v0
+-    s_add_u32		m0, m0, 1																//next vgpr index
+-	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 128							//every buffer_load_dword does 128 bytes
+-	s_cmp_lt_u32 	m0,	s_restore_alloc_size 												//scc = (m0 < s_restore_alloc_size) ? 1 : 0
+-	s_cbranch_scc1 	L_RESTORE_VGPR_WAVE32_LOOP														//VGPR restore (except v0) is complete?
+-	//s_set_gpr_idx_off
+-																							/* VGPR restore on v0 */
+-    if(USE_MTBUF_INSTEAD_OF_MUBUF)       
+-		tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-    else
+-		buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save	slc:1 glc:1	
+-	end
+-
+-    s_branch    L_RESTORE_LDS
+-
+-  L_RESTORE_VGPR_WAVE64:
+-    s_lshl_b32		s_restore_buf_rsrc2,  s_restore_alloc_size, 8						    //NUM_RECORDS in bytes (64 threads*4)
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
+-	end	
+-
+-	s_mov_b32		s_restore_mem_offset_save, s_restore_mem_offset							// restore start with v1, v0 will be the last
+-	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 256
+-    s_mov_b32 		m0, 1 																	//VGPR initial index value = 1
+-  L_RESTORE_VGPR_WAVE64_LOOP: 										
+-    if(USE_MTBUF_INSTEAD_OF_MUBUF)       
+-		tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-    else
+-		buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset	slc:1 glc:1	
+-	end
+-	s_waitcnt		vmcnt(0)																//ensure data ready
+-	v_movreld_b32		v0, v0																	//v[0+m0] = v0
+-    s_add_u32		m0, m0, 1																//next vgpr index
+-	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 256							//every buffer_load_dword does 256 bytes
+-	s_cmp_lt_u32 	m0,	s_restore_alloc_size 												//scc = (m0 < s_restore_alloc_size) ? 1 : 0
+-	s_cbranch_scc1 	L_RESTORE_VGPR_WAVE64_LOOP														//VGPR restore (except v0) is complete?
+-	//s_set_gpr_idx_off
+-    //
+-    //Below part will be the restore shared vgpr part (new for gfx10)
+-    s_getreg_b32 	s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) 			//shared_vgpr_size
+-    s_and_b32		s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF				//shared_vgpr_size is zero?
+-    s_cbranch_scc0	L_RESTORE_V0													    //no shared_vgpr used? jump to L_SAVE_LDS
+-    s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 3 						//Number of SHARED_VGPRs = shared_vgpr_size * 8    (non-zero value)
+-    //m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count.
+-    //restore shared_vgpr will start from the index of m0
+-    s_add_u32       s_restore_alloc_size, s_restore_alloc_size, m0
+-    s_mov_b32		exec_lo, 0xFFFFFFFF
+-    s_mov_b32		exec_hi, 0x00000000
+-    L_RESTORE_SHARED_VGPR_WAVE64_LOOP: 
+-    buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset	slc:1 glc:1
+-    s_waitcnt		vmcnt(0)																//ensure data ready
+-	v_movreld_b32		v0, v0																	//v[0+m0] = v0
+-    s_add_u32		m0, m0, 1																//next vgpr index
+-	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 128							//every buffer_load_dword does 256 bytes
+-	s_cmp_lt_u32 	m0,	s_restore_alloc_size 												//scc = (m0 < s_restore_alloc_size) ? 1 : 0
+-	s_cbranch_scc1 	L_RESTORE_SHARED_VGPR_WAVE64_LOOP														//VGPR restore (except v0) is complete?
+-
+-    s_mov_b32 exec_hi, 0xFFFFFFFF                                                           //restore back exec_hi before restoring V0!!
+-	
+-    /* VGPR restore on v0 */
+-  L_RESTORE_V0:
+-    if(USE_MTBUF_INSTEAD_OF_MUBUF)       
+-		tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-    else
+-		buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save	slc:1 glc:1	
+-	end
+-
+-
+-    /*      	restore LDS	    */
+-	//////////////////////////////
+-  L_RESTORE_LDS:
+-
+-    //Only need to check the first wave    
+-	/*      the first wave in the threadgroup    */
+-	s_and_b32		s_restore_tmp, s_restore_size, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK			
+-	s_cbranch_scc0	L_RESTORE_SGPR
+-	
+-    s_mov_b32		exec_lo, 0xFFFFFFFF 													//need every thread from now on   //be consistent with SAVE although can be moved ahead
+-    s_and_b32       m0, s_restore_size, 1
+-    s_cmp_eq_u32    m0, 1
+-    s_cbranch_scc1  L_ENABLE_RESTORE_LDS_EXEC_HI   
+-    s_mov_b32		exec_hi, 0x00000000
+-    s_branch        L_RESTORE_LDS_NORMAL
+-  L_ENABLE_RESTORE_LDS_EXEC_HI:
+-	s_mov_b32		exec_hi, 0xFFFFFFFF
+-  L_RESTORE_LDS_NORMAL:	
+-	s_getreg_b32 	s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) 				//lds_size
+-	s_and_b32		s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF					//lds_size is zero?
+-	s_cbranch_scc0	L_RESTORE_SGPR															//no lds used? jump to L_RESTORE_VGPR
+-	s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 6 							//LDS size in dwords = lds_size * 64dw
+-	s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 2 							//LDS size in bytes
+-	s_mov_b32		s_restore_buf_rsrc2,	s_restore_alloc_size							//NUM_RECORDS in bytes
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
+-	end
+-
+-    s_and_b32       m0, s_wave_size, 1
+-    s_cmp_eq_u32    m0, 1
+-    s_mov_b32 		m0, 0x0
+-    s_cbranch_scc1  L_RESTORE_LDS_LOOP_W64
+-
+-  L_RESTORE_LDS_LOOP_W32:									
+-	if (SAVE_LDS)
+-	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1
+-    s_waitcnt 0
+-	end
+-    s_add_u32		m0, m0, 128																//every buffer_load_dword does 256 bytes
+-	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 128						//mem offset increased by 256 bytes
+-	s_cmp_lt_u32	m0, s_restore_alloc_size												//scc=(m0 < s_restore_alloc_size) ? 1 : 0
+-	s_cbranch_scc1  L_RESTORE_LDS_LOOP_W32														//LDS restore is complete?
+-    s_branch        L_RESTORE_SGPR
+-
+-  L_RESTORE_LDS_LOOP_W64:									
+-	if (SAVE_LDS)
+-	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1
+-    s_waitcnt 0
+-	end
+-    s_add_u32		m0, m0, 256																//every buffer_load_dword does 256 bytes
+-	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 256							//mem offset increased by 256 bytes
+-	s_cmp_lt_u32	m0, s_restore_alloc_size												//scc=(m0 < s_restore_alloc_size) ? 1 : 0
+-	s_cbranch_scc1  L_RESTORE_LDS_LOOP_W64														//LDS restore is complete?
+-
+-	
+-    /*      	restore SGPRs	    */
+-	//////////////////////////////
+-	//s_getreg_b32 	s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) 				//spgr_size
+-	//s_add_u32 		s_restore_alloc_size, s_restore_alloc_size, 1
+-	//s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 4 							//Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value)
+-	//s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 3 							//Number of SGPRs = (sgpr_size + 1) * 8   (non-zero value)
+-  L_RESTORE_SGPR:
+-    //need to look at it is wave32 or wave64
+-    s_and_b32       m0, s_restore_size, 1
+-    s_cmp_eq_u32    m0, 1
+-    s_cbranch_scc1  L_RESTORE_SGPR_VMEM_WAVE64
+-	if (SGPR_SAVE_USE_SQC)
+-		s_lshl_b32		s_restore_buf_rsrc2,	s_sgpr_save_num, 2						//NUM_RECORDS in bytes 
+-	else
+-        s_lshl_b32		s_restore_buf_rsrc2,	s_sgpr_save_num, 7						//NUM_RECORDS in bytes (32 threads)
+-    end
+-    s_branch        L_RESTORE_SGPR_CONT
+-  L_RESTORE_SGPR_VMEM_WAVE64:
+-    if (SGPR_SAVE_USE_SQC)
+-		s_lshl_b32		s_restore_buf_rsrc2,	s_sgpr_save_num, 2						//NUM_RECORDS in bytes 
+-	else
+-		s_lshl_b32		s_restore_buf_rsrc2,	s_sgpr_save_num, 8						//NUM_RECORDS in bytes (64 threads)
+-	end
+-
+-  L_RESTORE_SGPR_CONT:
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
+-	end
+-
+-    s_and_b32       m0, s_restore_size, 1
+-    s_cmp_eq_u32    m0, 1
+-    s_cbranch_scc1  L_RESTORE_SGPR_WAVE64
+-
+-    read_sgpr_from_mem_wave32(s_restore_tmp, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)		//save s0 to s_restore_tmp
+-	s_mov_b32 		m0, 0x1
+-
+-  L_RESTORE_SGPR_LOOP_WAVE32:
+-    read_sgpr_from_mem_wave32(s0, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)															//PV: further performance improvement can be made
+-	s_waitcnt		lgkmcnt(0)																//ensure data ready
+-	s_movreld_b32 	s0, s0                                                                  //s[0+m0] = s0
+-    s_nop 0                                                                                 // hazard SALU M0=> S_MOVREL
+-	s_add_u32		m0, m0, 1																//next sgpr index
+-	s_cmp_lt_u32 	m0, s_sgpr_save_num												//scc = (m0 < s_restore_alloc_size) ? 1 : 0
+-	s_cbranch_scc1 	L_RESTORE_SGPR_LOOP_WAVE32														//SGPR restore (except s0) is complete?
+-	s_mov_b32		s0, s_restore_tmp															/* SGPR restore on s0 */
+-    s_branch        L_RESTORE_HWREG
+-  
+-  L_RESTORE_SGPR_WAVE64:
+-	read_sgpr_from_mem_wave64(s_restore_tmp, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)		//save s0 to s_restore_tmp
+-	s_mov_b32 		m0, 0x1																				//SGPR initial index value =1	//go on with with s1
+-	
+-  L_RESTORE_SGPR_LOOP_WAVE64: 																					
+-	read_sgpr_from_mem_wave64(s0, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)															//PV: further performance improvement can be made
+-	s_waitcnt		lgkmcnt(0)																//ensure data ready
+-	s_movreld_b32 	s0, s0                                                                  //s[0+m0] = s0
+-    s_nop 0                                                                                 // hazard SALU M0=> S_MOVREL
+-	s_add_u32		m0, m0, 1																//next sgpr index
+-	s_cmp_lt_u32 	m0, s_sgpr_save_num												//scc = (m0 < s_restore_alloc_size) ? 1 : 0
+-	s_cbranch_scc1 	L_RESTORE_SGPR_LOOP_WAVE64														//SGPR restore (except s0) is complete?
+-	s_mov_b32		s0, s_restore_tmp															/* SGPR restore on s0 */
+-
+-	
+-    /* 		restore HW registers	*/
+-	//////////////////////////////
+-  L_RESTORE_HWREG:
+-    s_mov_b32		s_restore_buf_rsrc2, 0x4												//NUM_RECORDS	in bytes
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
+-	end
+-
+-    s_and_b32       m0, s_restore_size, 1
+-    s_cmp_eq_u32    m0, 1
+-    s_cbranch_scc1  L_RESTORE_HWREG_WAVE64
+-
+-    read_sgpr_from_mem_wave32(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//M0
+-	read_sgpr_from_mem_wave32(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//PC
+-	read_sgpr_from_mem_wave32(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)
+-	read_sgpr_from_mem_wave32(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//EXEC
+-	read_sgpr_from_mem_wave32(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)
+-	read_sgpr_from_mem_wave32(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//STATUS
+-	read_sgpr_from_mem_wave32(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//TRAPSTS
+-    //read_sgpr_from_mem_wave32(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//XNACK_MASK_LO
+-	//read_sgpr_from_mem_wave32(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//XNACK_MASK_HI
+-    read_sgpr_from_mem_wave32(s_restore_xnack_mask, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//XNACK_MASK
+-	read_sgpr_from_mem_wave32(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//MODE
+-    if(SAVE_RESTORE_HWID_DDID)
+-    read_sgpr_from_mem_wave32(s_restore_hwid1, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//HW_ID1
+-    end
+-    s_branch        L_RESTORE_HWREG_FINISH
+-
+-  L_RESTORE_HWREG_WAVE64:
+-	read_sgpr_from_mem_wave64(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//M0
+-	read_sgpr_from_mem_wave64(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//PC
+-	read_sgpr_from_mem_wave64(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)
+-	read_sgpr_from_mem_wave64(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//EXEC
+-	read_sgpr_from_mem_wave64(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)
+-	read_sgpr_from_mem_wave64(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//STATUS
+-	read_sgpr_from_mem_wave64(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//TRAPSTS
+-    //read_sgpr_from_mem_wave64(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//XNACK_MASK_LO
+-	//read_sgpr_from_mem_wave64(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//XNACK_MASK_HI
+-    read_sgpr_from_mem_wave64(s_restore_xnack_mask, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//XNACK_MASK
+-	read_sgpr_from_mem_wave64(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//MODE
+-    if(SAVE_RESTORE_HWID_DDID)
+-    read_sgpr_from_mem_wave64(s_restore_hwid1, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//HW_ID1
+-    end
+-  L_RESTORE_HWREG_FINISH:
+-	s_waitcnt		lgkmcnt(0)																						//from now on, it is safe to restore STATUS and IB_STS
+-  
+-
+-
+-    if(SAVE_RESTORE_HWID_DDID)
+-  L_RESTORE_DDID:
+-    s_mov_b32      m0, s_restore_hwid1                                                      //virture ttrace support: The save-context handler records the SE/SA/WGP/SIMD/wave of the original wave
+-    s_ttracedata                                                                            //and then can output it as SHADER_DATA to ttrace on restore to provide a correlation across the save-restore
+-                                    
+-    s_mov_b32		s_restore_buf_rsrc2, 0x4												//NUM_RECORDS	in bytes
+-	if (SWIZZLE_EN)
+-		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
+-	else
+-		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
+-	end
+-
+-    s_and_b32       m0, s_restore_size, 1
+-    s_cmp_eq_u32    m0, 1
+-    s_cbranch_scc1  L_RESTORE_DDID_WAVE64
+-
+-    read_sgpr_from_mem_wave32(s_restore_ddid, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)	
+-    s_branch        L_RESTORE_DDID_FINISH
+-  L_RESTORE_DDID_WAVE64:
+-    read_sgpr_from_mem_wave64(s_restore_ddid, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)	
+-
+-  L_RESTORE_DDID_FINISH:
+-    s_waitcnt		lgkmcnt(0)
+-    //s_mov_b32      m0, s_restore_ddid
+-    //s_ttracedata   
+-    if (RESTORE_DDID_IN_SGPR18)
+-        s_mov_b32   s18, s_restore_ddid
+-	end	
+-    
+-    end   
+-
+-	s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff    	//pc[47:32]        //Do it here in order not to affect STATUS
+-
+-	//for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise:
+-	if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))
+-		s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8            //pc[31:0]+8	  //two back-to-back s_trap are used (first for save and second for restore)
+-		s_addc_u32	s_restore_pc_hi, s_restore_pc_hi, 0x0		 //carry bit over
+-	end	
+-	if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL))	      
+-		s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4            //pc[31:0]+4     // save is hack through s_trap but restore is normal
+-		s_addc_u32	s_restore_pc_hi, s_restore_pc_hi, 0x0		 //carry bit over
+-	end
+-	
+-	s_mov_b32 		m0, 		s_restore_m0
+-	s_mov_b32 		exec_lo, 	s_restore_exec_lo
+-	s_mov_b32 		exec_hi, 	s_restore_exec_hi
+-	
+-	s_and_b32		s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts
++	/* Setup Resource Contants */
++	s_mov_b32	s_restore_buf_rsrc0, s_restore_spi_init_lo		//base_addr_lo
++	s_and_b32	s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF	//base_addr_hi
++	s_or_b32	s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE
++	s_mov_b32	s_restore_buf_rsrc2, 0					//NUM_RECORDS initial value = 0 (in bytes)
++	s_mov_b32	s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC
++	s_and_b32	s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK
++	s_lshr_b32	s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT)
++	s_or_b32	s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp	//or ATC
++	s_and_b32	s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK
++	s_lshr_b32	s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT)
++	s_or_b32	s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp	//or MTYPE
++	//determine it is wave32 or wave64
++	s_getreg_b32	s_restore_size, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE)
++	s_lshl_b32	s_restore_size, s_restore_size, S_WAVE_SIZE
++	s_or_b32	s_restore_size, s_restore_spi_init_hi, s_restore_size
++
++	s_and_b32	s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK
++	s_cbranch_scc0	L_RESTORE_VGPR
++
++	/* restore LDS */
++L_RESTORE_LDS:
++	s_mov_b32	exec_lo, 0xFFFFFFFF					//need every thread from now on
++	s_lshr_b32	m0, s_restore_size, S_WAVE_SIZE
++	s_and_b32	m0, m0, 1
++	s_cmp_eq_u32	m0, 1
++	s_cbranch_scc1	L_ENABLE_RESTORE_LDS_EXEC_HI
++	s_mov_b32	exec_hi, 0x00000000
++	s_branch	L_RESTORE_LDS_NORMAL
++L_ENABLE_RESTORE_LDS_EXEC_HI:
++	s_mov_b32	exec_hi, 0xFFFFFFFF
++L_RESTORE_LDS_NORMAL:
++	s_getreg_b32	s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE)
++	s_and_b32	s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF	//lds_size is zero?
++	s_cbranch_scc0	L_RESTORE_VGPR						//no lds used? jump to L_RESTORE_VGPR
++	s_lshl_b32	s_restore_alloc_size, s_restore_alloc_size, 6		//LDS size in dwords = lds_size * 64dw
++	s_lshl_b32	s_restore_alloc_size, s_restore_alloc_size, 2		//LDS size in bytes
++	s_mov_b32	s_restore_buf_rsrc2, s_restore_alloc_size		//NUM_RECORDS in bytes
++
++	// LDS at offset: size(VGPR)+size(SVGPR)+SIZE(SGPR)+SIZE(HWREG)
++	//
++	get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size)
++	get_svgpr_size_bytes(s_restore_tmp)
++	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp
++	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes()
++	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes()
++
++	s_mov_b32	s_restore_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
++
++	s_lshr_b32	m0, s_wave_size, S_WAVE_SIZE
++	s_and_b32	m0, m0, 1
++	s_cmp_eq_u32	m0, 1
++	s_mov_b32	m0, 0x0
++	s_cbranch_scc1	L_RESTORE_LDS_LOOP_W64
++
++L_RESTORE_LDS_LOOP_W32:
++	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1	// first 64DW
++	s_add_u32	m0, m0, 128						// 128 DW
++	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 128		//mem offset increased by 128DW
++	s_cmp_lt_u32	m0, s_restore_alloc_size				//scc=(m0 < s_restore_alloc_size) ? 1 : 0
++	s_cbranch_scc1	L_RESTORE_LDS_LOOP_W32					//LDS restore is complete?
++	s_branch	L_RESTORE_VGPR
++
++L_RESTORE_LDS_LOOP_W64:
++	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1	// first 64DW
++	s_add_u32	m0, m0, 256						// 256 DW
++	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 256		//mem offset increased by 256DW
++	s_cmp_lt_u32	m0, s_restore_alloc_size				//scc=(m0 < s_restore_alloc_size) ? 1 : 0
++	s_cbranch_scc1	L_RESTORE_LDS_LOOP_W64					//LDS restore is complete?
++
++	/* restore VGPRs */
++L_RESTORE_VGPR:
++	// VGPR SR memory offset : 0
++	s_mov_b32	s_restore_mem_offset, 0x0
++ 	s_mov_b32	exec_lo, 0xFFFFFFFF					//need every thread from now on
++	s_lshr_b32	m0, s_restore_size, S_WAVE_SIZE
++	s_and_b32	m0, m0, 1
++	s_cmp_eq_u32	m0, 1
++	s_cbranch_scc1	L_ENABLE_RESTORE_VGPR_EXEC_HI
++	s_mov_b32	exec_hi, 0x00000000
++	s_branch	L_RESTORE_VGPR_NORMAL
++L_ENABLE_RESTORE_VGPR_EXEC_HI:
++	s_mov_b32	exec_hi, 0xFFFFFFFF
++L_RESTORE_VGPR_NORMAL:
++	s_getreg_b32	s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE)
++	s_add_u32	s_restore_alloc_size, s_restore_alloc_size, 1
++	s_lshl_b32	s_restore_alloc_size, s_restore_alloc_size, 2		//Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)
++	//determine it is wave32 or wave64
++	s_lshr_b32	m0, s_restore_size, S_WAVE_SIZE
++	s_and_b32	m0, m0, 1
++	s_cmp_eq_u32	m0, 1
++	s_cbranch_scc1	L_RESTORE_VGPR_WAVE64
++
++	s_mov_b32	s_restore_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
++
++	// VGPR load using dw burst
++	s_mov_b32	s_restore_mem_offset_save, s_restore_mem_offset		// restore start with v1, v0 will be the last
++	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 128*4
++	s_mov_b32	m0, 4							//VGPR initial index value = 4
++
++L_RESTORE_VGPR_WAVE32_LOOP:
++	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
++	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128
++	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128*2
++	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128*3
++	s_waitcnt	vmcnt(0)
++	v_movreld_b32	v0, v0							//v[0+m0] = v0
++	v_movreld_b32	v1, v1
++	v_movreld_b32	v2, v2
++	v_movreld_b32	v3, v3
++	s_add_u32	m0, m0, 4						//next vgpr index
++	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 128*4	//every buffer_load_dword does 128 bytes
++	s_cmp_lt_u32	m0, s_restore_alloc_size				//scc = (m0 < s_restore_alloc_size) ? 1 : 0
++	s_cbranch_scc1	L_RESTORE_VGPR_WAVE32_LOOP				//VGPR restore (except v0) is complete?
++
++	/* VGPR restore on v0 */
++	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1
++	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128
++	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*2
++	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*3
++
++	s_branch	L_RESTORE_SGPR
++
++L_RESTORE_VGPR_WAVE64:
++	s_mov_b32	s_restore_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
++
++	// VGPR load using dw burst
++	s_mov_b32	s_restore_mem_offset_save, s_restore_mem_offset		// restore start with v4, v0 will be the last
++	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 256*4
++	s_mov_b32	m0, 4							//VGPR initial index value = 4
++
++L_RESTORE_VGPR_WAVE64_LOOP:
++	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
++	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256
++	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2
++	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3
++	s_waitcnt	vmcnt(0)
++	v_movreld_b32	v0, v0							//v[0+m0] = v0
++	v_movreld_b32	v1, v1
++	v_movreld_b32	v2, v2
++	v_movreld_b32	v3, v3
++	s_add_u32	m0, m0, 4						//next vgpr index
++	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 256*4	//every buffer_load_dword does 256 bytes
++	s_cmp_lt_u32	m0, s_restore_alloc_size				//scc = (m0 < s_restore_alloc_size) ? 1 : 0
++	s_cbranch_scc1	L_RESTORE_VGPR_WAVE64_LOOP				//VGPR restore (except v0) is complete?
++
++	//Below part will be the restore shared vgpr part (new for gfx10)
++	s_getreg_b32	s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE)	//shared_vgpr_size
++	s_and_b32	s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF	//shared_vgpr_size is zero?
++	s_cbranch_scc0	L_RESTORE_V0						//no shared_vgpr used?
++	s_lshl_b32	s_restore_alloc_size, s_restore_alloc_size, 3		//Number of SHARED_VGPRs = shared_vgpr_size * 8    (non-zero value)
++	//m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count.
++	//restore shared_vgpr will start from the index of m0
++	s_add_u32	s_restore_alloc_size, s_restore_alloc_size, m0
++	s_mov_b32	exec_lo, 0xFFFFFFFF
++	s_mov_b32	exec_hi, 0x00000000
++L_RESTORE_SHARED_VGPR_WAVE64_LOOP:
++	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
++	s_waitcnt	vmcnt(0)
++	v_movreld_b32	v0, v0							//v[0+m0] = v0
++	s_add_u32	m0, m0, 1						//next vgpr index
++	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 128
++	s_cmp_lt_u32	m0, s_restore_alloc_size				//scc = (m0 < s_restore_alloc_size) ? 1 : 0
++	s_cbranch_scc1	L_RESTORE_SHARED_VGPR_WAVE64_LOOP			//VGPR restore (except v0) is complete?
++
++	s_mov_b32	exec_hi, 0xFFFFFFFF					//restore back exec_hi before restoring V0!!
++
++	/* VGPR restore on v0 */
++L_RESTORE_V0:
++	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1
++	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128
++	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*2
++	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*3
++
++	/* restore SGPRs */
++	//will be 2+8+16*6
++	// SGPR SR memory offset : size(VGPR)+size(SVGPR)
++L_RESTORE_SGPR:
++	get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size)
++	get_svgpr_size_bytes(s_restore_tmp)
++	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp
++	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes()
++	s_sub_u32	s_restore_mem_offset, s_restore_mem_offset, 22*4	//s106~s127 is not saved
++	s_sub_u32	s_restore_mem_offset, s_restore_mem_offset, 2*4		// restore SGPR from S[n] to S[0], by 2 sgprs group
++
++	s_mov_b32	s_restore_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
++
++	s_mov_b32	m0, s_sgpr_save_num
++
++	read_2sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset)
++
++	s_waitcnt	lgkmcnt(0)
++
++	s_sub_u32	m0, m0, 2						// Restore from S[n] to S[0]
++	s_nop		0							// hazard SALU M0=> S_MOVREL
++
++	s_movreld_b64	s0, s0							//s[0+m0] = s0
++
++	read_8sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset)
++	s_waitcnt	lgkmcnt(0)
++
++	s_sub_u32	m0, m0, 8						// Restore from S[n] to S[0]
++	s_nop		0							// hazard SALU M0=> S_MOVREL
++
++	s_movreld_b64	s0, s0							//s[0+m0] = s0
++	s_movreld_b64	s2, s2
++	s_movreld_b64	s4, s4
++	s_movreld_b64	s6, s6
++
++ L_RESTORE_SGPR_LOOP:
++	read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset)
++	s_waitcnt	lgkmcnt(0)
++
++	s_sub_u32	m0, m0, 16						// Restore from S[n] to S[0]
++	s_nop		0							// hazard SALU M0=> S_MOVREL
++
++	s_movreld_b64	s0, s0							//s[0+m0] = s0
++	s_movreld_b64	s2, s2
++	s_movreld_b64	s4, s4
++	s_movreld_b64	s6, s6
++	s_movreld_b64	s8, s8
++	s_movreld_b64	s10, s10
++	s_movreld_b64	s12, s12
++	s_movreld_b64	s14, s14
++
++	s_cmp_eq_u32	m0, 0							//scc = (m0 < s_sgpr_save_num) ? 1 : 0
++	s_cbranch_scc0	L_RESTORE_SGPR_LOOP
++
++	/* restore HW registers */
++L_RESTORE_HWREG:
++	// HWREG SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)
++	get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size)
++	get_svgpr_size_bytes(s_restore_tmp)
++	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp
++	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes()
++
++	s_mov_b32	s_restore_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
++
++	read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset)
++	read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset)
++	read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset)
++	read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset)
++	read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset)
++	read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset)
++	read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset)
++	read_hwreg_from_mem(s_restore_xnack_mask, s_restore_buf_rsrc0, s_restore_mem_offset)
++	read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset)
++
++	s_waitcnt	lgkmcnt(0)						//from now on, it is safe to restore STATUS and IB_STS
++
++	s_mov_b32	s_restore_tmp, s_restore_pc_hi
++	s_and_b32	s_restore_pc_hi, s_restore_tmp, 0x0000ffff		//pc[47:32] //Do it here in order not to affect STATUS
++
++	s_mov_b32	m0, s_restore_m0
++	s_mov_b32	exec_lo, s_restore_exec_lo
++	s_mov_b32	exec_hi, s_restore_exec_hi
++
++	s_and_b32	s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts
+ 	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0
+-    s_setreg_b32    hwreg(HW_REG_SHADER_XNACK_MASK), s_restore_xnack_mask         //restore xnack_mask
+-	s_and_b32		s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts
+-	s_lshr_b32		s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT
++	s_setreg_b32	hwreg(HW_REG_SHADER_XNACK_MASK), s_restore_xnack_mask
++	s_and_b32	s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts
++	s_lshr_b32	s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT
+ 	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0
+-	//s_setreg_b32 	hwreg(HW_REG_TRAPSTS), 	s_restore_trapsts      //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore
+-	s_setreg_b32 	hwreg(HW_REG_MODE), 	s_restore_mode
+-	//reuse s_restore_m0 as a temp register
+-	s_and_b32		s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_RCNT_MASK
+-	s_lshr_b32		s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT
+-	s_lshl_b32		s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT
+-	s_mov_b32		s_restore_tmp, 0x0																				//IB_STS is zero
+-	s_or_b32		s_restore_tmp, s_restore_tmp, s_restore_m0
+-	s_and_b32		s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_FIRST_REPLAY_MASK
+-	s_lshr_b32		s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
+-	s_lshl_b32		s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT
+-	s_or_b32		s_restore_tmp, s_restore_tmp, s_restore_m0
+-    s_and_b32       s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK 
+-    s_lshr_b32		s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT
+-	s_setreg_b32 	hwreg(HW_REG_IB_STS), 	s_restore_tmp
+-	s_setreg_b32 	hwreg(HW_REG_STATUS), 	s_restore_status
+-
+-	s_barrier													//barrier to ensure the readiness of LDS before access attemps from any other wave in the same TG //FIXME not performance-optimal at this time
+-	
+-	
+-//	s_rfe_b64 s_restore_pc_lo                              		//Return to the main shader program and resume execution
+-    s_rfe_b64  s_restore_pc_lo            // s_restore_m0[0] is used to set STATUS.inst_atc 
+-
+-
+-/**************************************************************************/
+-/*                     	the END								              */
+-/**************************************************************************/	
+-L_END_PGM:	
++	s_setreg_b32	hwreg(HW_REG_MODE), s_restore_mode
++	s_and_b32	s_restore_m0, s_restore_tmp, S_SAVE_PC_HI_RCNT_MASK
++	s_lshr_b32	s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT
++	s_lshl_b32	s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT
++	s_mov_b32	s_restore_mode, 0x0
++	s_or_b32	s_restore_mode, s_restore_mode, s_restore_m0
++	s_and_b32	s_restore_m0, s_restore_tmp, S_SAVE_PC_HI_FIRST_REPLAY_MASK
++	s_lshr_b32	s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
++	s_lshl_b32	s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT
++	s_or_b32	s_restore_mode, s_restore_mode, s_restore_m0
++	s_and_b32	s_restore_m0, s_restore_tmp, S_SAVE_PC_HI_REPLAY_W64H_MASK
++	s_lshr_b32	s_restore_m0, s_restore_m0, S_SAVE_PC_HI_REPLAY_W64H_SHIFT
++	s_lshl_b32	s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT
++	s_or_b32	s_restore_mode, s_restore_mode, s_restore_m0
++
++	s_and_b32	s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK
++	s_lshr_b32	s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT
++	s_setreg_b32 	hwreg(HW_REG_IB_STS), s_restore_mode
++
++	s_and_b64	exec, exec, exec					// Restore STATUS.EXECZ, not writable by s_setreg_b32
++	s_and_b64	vcc, vcc, vcc						// Restore STATUS.VCCZ, not writable by s_setreg_b32
++	s_setreg_b32	hwreg(HW_REG_STATUS), s_restore_status			// SCC is included, which is changed by previous salu
++
++	s_barrier								//barrier to ensure the readiness of LDS before access attemps from any other wave in the same TG
++
++	s_rfe_b64	s_restore_pc_lo						//Return to the main shader program and resume execution
++
++L_END_PGM:
+ 	s_endpgm
+-	
+-end	
+-
+-
+-/**************************************************************************/
+-/*                     	the helper functions							  */
+-/**************************************************************************/
+-function write_sgpr_to_mem_wave32(s, s_rsrc, s_mem_offset, use_sqc, use_mtbuf)
+-	if (use_sqc)
+-		s_mov_b32 exec_lo, m0					//assuming exec_lo is not needed anymore from this point on
+-		s_mov_b32 m0, s_mem_offset
+-		s_buffer_store_dword s, s_rsrc, m0		glc:1	
+-		s_add_u32		s_mem_offset, s_mem_offset, 4
+-		s_mov_b32	m0, exec_lo
+-    elsif (use_mtbuf)
+-        v_mov_b32	v0,	s
+-        tbuffer_store_format_x v0, v0, s_rsrc, s_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-		s_add_u32		s_mem_offset, s_mem_offset, 128
+-    else 
+-        v_mov_b32	v0,	s
+-		buffer_store_dword	v0, v0, s_rsrc, s_mem_offset	slc:1 glc:1
+-        s_add_u32		s_mem_offset, s_mem_offset, 128
+-	end
+ end
+ 
+-function write_sgpr_to_mem_wave64(s, s_rsrc, s_mem_offset, use_sqc, use_mtbuf)
+-	if (use_sqc)
+-		s_mov_b32 exec_lo, m0					//assuming exec_lo is not needed anymore from this point on
+-		s_mov_b32 m0, s_mem_offset
+-		s_buffer_store_dword s, s_rsrc, m0		glc:1	
+-		s_add_u32		s_mem_offset, s_mem_offset, 4
+-		s_mov_b32	m0, exec_lo
+-    elsif (use_mtbuf)
+-        v_mov_b32	v0,	s
+-        tbuffer_store_format_x v0, v0, s_rsrc, s_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-		s_add_u32		s_mem_offset, s_mem_offset, 256
+-    else 
+-        v_mov_b32	v0,	s
+-		buffer_store_dword	v0, v0, s_rsrc, s_mem_offset	slc:1 glc:1
+-        s_add_u32		s_mem_offset, s_mem_offset, 256
+-	end
++function write_hwreg_to_mem(s, s_rsrc, s_mem_offset)
++	s_mov_b32	exec_lo, m0
++	s_mov_b32	m0, s_mem_offset
++	s_buffer_store_dword	s, s_rsrc, m0 glc:1
++	s_add_u32	s_mem_offset, s_mem_offset, 4
++	s_mov_b32	m0, exec_lo
++end
++
++
++function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset)
++	s_buffer_store_dwordx4	s[0], s_rsrc, 0 glc:1
++	s_buffer_store_dwordx4	s[4], s_rsrc, 16 glc:1
++	s_buffer_store_dwordx4	s[8], s_rsrc, 32 glc:1
++	s_buffer_store_dwordx4	s[12], s_rsrc, 48 glc:1
++	s_add_u32	s_rsrc[0], s_rsrc[0], 4*16
++	s_addc_u32	s_rsrc[1], s_rsrc[1], 0x0
++end
++
++function write_10sgpr_to_mem(s, s_rsrc, s_mem_offset)
++	s_buffer_store_dwordx4	s[0], s_rsrc, 0 glc:1
++	s_buffer_store_dwordx4	s[4], s_rsrc, 16 glc:1
++	s_buffer_store_dwordx2	s[8], s_rsrc, 32 glc:1
++	s_add_u32	s_rsrc[0], s_rsrc[0], 4*16
++	s_addc_u32	s_rsrc[1], s_rsrc[1], 0x0
++end
++
++
++function read_hwreg_from_mem(s, s_rsrc, s_mem_offset)
++	s_buffer_load_dword	s, s_rsrc, s_mem_offset glc:1
++	s_add_u32	s_mem_offset, s_mem_offset, 4
+ end
+ 
+-function read_sgpr_from_mem_wave32(s, s_rsrc, s_mem_offset, use_sqc)
+-	s_buffer_load_dword s, s_rsrc, s_mem_offset		glc:1
+-	if (use_sqc)
+-		s_add_u32		s_mem_offset, s_mem_offset, 4
+-	else
+-        s_add_u32		s_mem_offset, s_mem_offset, 128
+-	end
++function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset)
++	s_buffer_load_dwordx16	s, s_rsrc, s_mem_offset glc:1
++	s_sub_u32	s_mem_offset, s_mem_offset, 4*16
+ end
+ 
+-function read_sgpr_from_mem_wave64(s, s_rsrc, s_mem_offset, use_sqc)
+-	s_buffer_load_dword s, s_rsrc, s_mem_offset		glc:1
+-	if (use_sqc)
+-		s_add_u32		s_mem_offset, s_mem_offset, 4
+-	else
+-        s_add_u32		s_mem_offset, s_mem_offset, 256
+-	end
++function read_8sgpr_from_mem(s, s_rsrc, s_mem_offset)
++	s_buffer_load_dwordx8	s, s_rsrc, s_mem_offset glc:1
++	s_sub_u32	s_mem_offset, s_mem_offset, 4*16
+ end
+ 
++function read_2sgpr_from_mem(s, s_rsrc, s_mem_offset)
++	s_buffer_load_dwordx2 s, s_rsrc, s_mem_offset glc:1
++	s_sub_u32	s_mem_offset, s_mem_offset, 4*8
++end
++
++
++function get_lds_size_bytes(s_lds_size_byte)
++	s_getreg_b32	s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE)
++	s_lshl_b32	s_lds_size_byte, s_lds_size_byte, 8			//LDS size in dwords = lds_size * 64 *4Bytes // granularity 64DW
++end
++
++function get_vgpr_size_bytes(s_vgpr_size_byte, s_size)
++	s_getreg_b32	s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE)
++	s_add_u32	s_vgpr_size_byte, s_vgpr_size_byte, 1
++	s_lshr_b32	m0, s_size, S_WAVE_SIZE
++	s_and_b32	m0, m0, 1
++	s_cmp_eq_u32	m0, 1
++	s_cbranch_scc1	L_ENABLE_SHIFT_W64
++	s_lshl_b32	s_vgpr_size_byte, s_vgpr_size_byte, (2+7)		//Number of VGPRs = (vgpr_size + 1) * 4 * 32 * 4   (non-zero value)
++	s_branch	L_SHIFT_DONE
++L_ENABLE_SHIFT_W64:
++	s_lshl_b32	s_vgpr_size_byte, s_vgpr_size_byte, (2+8)		//Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4   (non-zero value)
++L_SHIFT_DONE:
++end
++
++function get_svgpr_size_bytes(s_svgpr_size_byte)
++	s_getreg_b32	s_svgpr_size_byte, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE)
++	s_lshl_b32	s_svgpr_size_byte, s_svgpr_size_byte, (3+7)
++end
++
++function get_sgpr_size_bytes
++	return 512
++end
++
++function get_hwreg_size_bytes
++	return 128
++end
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3120-drm-amdkfd-Remove-dead-code-from-gfx8-gfx9-trap-hand.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3120-drm-amdkfd-Remove-dead-code-from-gfx8-gfx9-trap-hand.patch
new file mode 100644
index 00000000..1d95615b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3120-drm-amdkfd-Remove-dead-code-from-gfx8-gfx9-trap-hand.patch
@@ -0,0 +1,1254 @@
+From 230da4ce3763dee028f54f5a280cb2fc025e8bbe Mon Sep 17 00:00:00 2001
+From: Jay Cornwall <jay.cornwall@amd.com>
+Date: Wed, 24 Jul 2019 12:26:08 -0500
+Subject: [PATCH 3120/4256] drm/amdkfd: Remove dead code from gfx8/gfx9 trap
+ handlers
+
+Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm | 395 +-----------------
+ .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 375 +----------------
+ 2 files changed, 5 insertions(+), 765 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm
+index a47f5b933120..b195b7cd8a17 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm
+@@ -24,78 +24,6 @@
+  * PROJECT=vi ./sp3 cwsr_trap_handler_gfx8.asm -hex tmp.hex
+  */
+ 
+-/* HW (VI) source code for CWSR trap handler */
+-/* Version 18 + multiple trap handler */
+-
+-// this performance-optimal version was originally from Seven Xu at SRDC
+-
+-// Revison #18   --...
+-/* Rev History
+-** #1. Branch from gc dv.   //gfxip/gfx8/main/src/test/suites/block/cs/sr/cs_trap_handler.sp3#1,#50, #51, #52-53(Skip, Already Fixed by PV), #54-56(merged),#57-58(mergerd, skiped-already fixed by PV)
+-** #4. SR Memory Layout:
+-**             1. VGPR-SGPR-HWREG-{LDS}
+-**             2. tba_hi.bits.26 - reconfigured as the first wave in tg bits, for defer Save LDS for a threadgroup.. performance concern..
+-** #5. Update: 1. Accurate g8sr_ts_save_d timestamp
+-** #6. Update: 1. Fix s_barrier usage; 2. VGPR s/r using swizzle buffer?(NoNeed, already matched the swizzle pattern, more investigation)
+-** #7. Update: 1. don't barrier if noLDS
+-** #8. Branch: 1. Branch to ver#0, which is very similar to gc dv version
+-**             2. Fix SQ issue by s_sleep 2
+-** #9. Update: 1. Fix scc restore failed issue, restore wave_status at last
+-**             2. optimize s_buffer save by burst 16sgprs...
+-** #10. Update 1. Optimize restore sgpr by busrt 16 sgprs.
+-** #11. Update 1. Add 2 more timestamp for debug version
+-** #12. Update 1. Add VGPR SR using DWx4, some case improve and some case drop performance
+-** #13. Integ  1. Always use MUBUF for PV trap shader...
+-** #14. Update 1. s_buffer_store soft clause...
+-** #15. Update 1. PERF - sclar write with glc:0/mtype0 to allow L2 combine. perf improvement a lot.
+-** #16. Update 1. PRRF - UNROLL LDS_DMA got 2500cycle save in IP tree
+-** #17. Update 1. FUNC - LDS_DMA has issues while ATC, replace with ds_read/buffer_store for save part[TODO restore part]
+-**             2. PERF - Save LDS before save VGPR to cover LDS save long latency...
+-** #18. Update 1. FUNC - Implicitly estore STATUS.VCCZ, which is not writable by s_setreg_b32
+-**             2. FUNC - Handle non-CWSR traps
+-*/
+-
+-var G8SR_WDMEM_HWREG_OFFSET = 0
+-var G8SR_WDMEM_SGPR_OFFSET  = 128  // in bytes
+-
+-// Keep definition same as the app shader, These 2 time stamps are part of the app shader... Should before any Save and after restore.
+-
+-var G8SR_DEBUG_TIMESTAMP = 0
+-var G8SR_DEBUG_TS_SAVE_D_OFFSET = 40*4  // ts_save_d timestamp offset relative to SGPR_SR_memory_offset
+-var s_g8sr_ts_save_s    = s[34:35]   // save start
+-var s_g8sr_ts_sq_save_msg  = s[36:37]   // The save shader send SAVEWAVE msg to spi
+-var s_g8sr_ts_spi_wrexec   = s[38:39]   // the SPI write the sr address to SQ
+-var s_g8sr_ts_save_d    = s[40:41]   // save end
+-var s_g8sr_ts_restore_s = s[42:43]   // restore start
+-var s_g8sr_ts_restore_d = s[44:45]   // restore end
+-
+-var G8SR_VGPR_SR_IN_DWX4 = 0
+-var G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 = 0x00100000    // DWx4 stride is 4*4Bytes
+-var G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4  = G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4
+-
+-
+-/*************************************************************************/
+-/*                  control on how to run the shader                     */
+-/*************************************************************************/
+-//any hack that needs to be made to run this code in EMU (either because various EMU code are not ready or no compute save & restore in EMU run)
+-var EMU_RUN_HACK                    =   0
+-var EMU_RUN_HACK_RESTORE_NORMAL     =   0
+-var EMU_RUN_HACK_SAVE_NORMAL_EXIT   =   0
+-var EMU_RUN_HACK_SAVE_SINGLE_WAVE   =   0
+-var EMU_RUN_HACK_SAVE_FIRST_TIME    =   0                   //for interrupted restore in which the first save is through EMU_RUN_HACK
+-var EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_LO =   0                   //for interrupted restore in which the first save is through EMU_RUN_HACK
+-var EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_HI =   0                   //for interrupted restore in which the first save is through EMU_RUN_HACK
+-var SAVE_LDS                        =   1
+-var WG_BASE_ADDR_LO                 =   0x9000a000
+-var WG_BASE_ADDR_HI                 =   0x0
+-var WAVE_SPACE                      =   0x5000              //memory size that each wave occupies in workgroup state mem
+-var CTX_SAVE_CONTROL                =   0x0
+-var CTX_RESTORE_CONTROL             =   CTX_SAVE_CONTROL
+-var SIM_RUN_HACK                    =   0                   //any hack that needs to be made to run this code in SIM (either because various RTL code are not ready or no compute save & restore in RTL run)
+-var SGPR_SAVE_USE_SQC               =   1                   //use SQC D$ to do the write
+-var USE_MTBUF_INSTEAD_OF_MUBUF      =   0                   //because TC EMU currently asserts on 0 of // overload DFMT field to carry 4 more bits of stride for MUBUF opcodes
+-var SWIZZLE_EN                      =   0                   //whether we use swizzled buffer addressing
+-
+ /**************************************************************************/
+ /*                      variables                                         */
+ /**************************************************************************/
+@@ -226,16 +154,7 @@ shader main
+   type(CS)
+ 
+ 
+-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))                   //hack to use trap_id for determining save/restore
+-        //FIXME VCCZ un-init assertion s_getreg_b32     s_save_status, hwreg(HW_REG_STATUS)         //save STATUS since we will change SCC
+-        s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000              //change SCC
+-        s_cmp_eq_u32 s_save_tmp, 0x007e0000                         //Save: trap_id = 0x7e. Restore: trap_id = 0x7f.
+-        s_cbranch_scc0 L_JUMP_TO_RESTORE                            //do not need to recover STATUS here  since we are going to RESTORE
+-        //FIXME  s_setreg_b32   hwreg(HW_REG_STATUS),   s_save_status       //need to recover STATUS since we are going to SAVE
+-        s_branch L_SKIP_RESTORE                                     //NOT restore, SAVE actually
+-    else
+         s_branch L_SKIP_RESTORE                                     //NOT restore. might be a regular trap or save
+-    end
+ 
+ L_JUMP_TO_RESTORE:
+     s_branch L_RESTORE                                              //restore
+@@ -249,7 +168,7 @@ L_SKIP_RESTORE:
+     s_cbranch_scc1  L_SAVE                                      //this is the operation for save
+ 
+     // *********    Handle non-CWSR traps       *******************
+-if (!EMU_RUN_HACK)
++
+     /* read tba and tma for next level trap handler, ttmp4 is used as s_save_status */
+     s_load_dwordx4  [ttmp8,ttmp9,ttmp10, ttmp11], [tma_lo,tma_hi], 0
+     s_waitcnt lgkmcnt(0)
+@@ -268,7 +187,7 @@ L_EXCP_CASE:
+     s_and_b32   ttmp1, ttmp1, 0xFFFF
+     set_status_without_spi_prio(s_save_status, ttmp2) //restore HW status(SCC)
+     s_rfe_b64       [ttmp0, ttmp1]
+-end
++
+     // *********        End handling of non-CWSR traps   *******************
+ 
+ /**************************************************************************/
+@@ -276,12 +195,6 @@ end
+ /**************************************************************************/
+ 
+ L_SAVE:
+-
+-if G8SR_DEBUG_TIMESTAMP
+-        s_memrealtime   s_g8sr_ts_save_s
+-        s_waitcnt lgkmcnt(0)         //FIXME, will cause xnack??
+-end
+-
+     s_mov_b32       s_save_tmp, 0                                                           //clear saveCtx bit
+     s_setreg_b32    hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp     //clear saveCtx bit
+ 
+@@ -303,16 +216,7 @@ end
+     s_mov_b32       s_save_exec_hi, exec_hi
+     s_mov_b64       exec,   0x0                                                             //clear EXEC to get ready to receive
+ 
+-if G8SR_DEBUG_TIMESTAMP
+-        s_memrealtime  s_g8sr_ts_sq_save_msg
+-        s_waitcnt lgkmcnt(0)
+-end
+-
+-    if (EMU_RUN_HACK)
+-
+-    else
+         s_sendmsg   sendmsg(MSG_SAVEWAVE)  //send SPI a message and wait for SPI's write to EXEC
+-    end
+ 
+     // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for.
+     s_or_b32 s_save_tmp, s_save_status, (2 << SQ_WAVE_STATUS_SPI_PRIO_SHIFT)
+@@ -321,36 +225,9 @@ end
+   L_SLEEP:
+     s_sleep 0x2                // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0
+ 
+-    if (EMU_RUN_HACK)
+-
+-    else
+         s_cbranch_execz L_SLEEP
+-    end
+-
+-if G8SR_DEBUG_TIMESTAMP
+-        s_memrealtime  s_g8sr_ts_spi_wrexec
+-        s_waitcnt lgkmcnt(0)
+-end
+ 
+     /*      setup Resource Contants    */
+-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE))
+-        //calculate wd_addr using absolute thread id
+-        v_readlane_b32 s_save_tmp, v9, 0
+-        s_lshr_b32 s_save_tmp, s_save_tmp, 6
+-        s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE
+-        s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO
+-        s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI
+-        s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL
+-    else
+-    end
+-    if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE))
+-        s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO
+-        s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI
+-        s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL
+-    else
+-    end
+-
+-
+     s_mov_b32       s_save_buf_rsrc0,   s_save_spi_init_lo                                                      //base_addr_lo
+     s_and_b32       s_save_buf_rsrc1,   s_save_spi_init_hi, 0x0000FFFF                                          //base_addr_hi
+     s_or_b32        s_save_buf_rsrc1,   s_save_buf_rsrc1,  S_SAVE_BUF_RSRC_WORD1_STRIDE
+@@ -383,22 +260,10 @@ end
+ 
+ 
+     s_mov_b32       s_save_buf_rsrc2, 0x4                               //NUM_RECORDS   in bytes
+-    if (SWIZZLE_EN)
+-        s_add_u32       s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0                     //FIXME need to use swizzle to enable bounds checking?
+-    else
+         s_mov_b32       s_save_buf_rsrc2,  0x1000000                                //NUM_RECORDS in bytes
+-    end
+ 
+ 
+     write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)                  //M0
+-
+-    if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME))
+-        s_add_u32 s_save_pc_lo, s_save_pc_lo, 4             //pc[31:0]+4
+-        s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0          //carry bit over
+-        s_mov_b32   tba_lo, EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_LO
+-        s_mov_b32   tba_hi, EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_HI
+-    end
+-
+     write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset)                   //PC
+     write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset)
+     write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset)             //EXEC
+@@ -440,18 +305,8 @@ end
+     s_add_u32       s_save_alloc_size, s_save_alloc_size, 1
+     s_lshl_b32      s_save_alloc_size, s_save_alloc_size, 4                         //Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value)
+ 
+-    if (SGPR_SAVE_USE_SQC)
+         s_lshl_b32      s_save_buf_rsrc2,   s_save_alloc_size, 2                    //NUM_RECORDS in bytes
+-    else
+-        s_lshl_b32      s_save_buf_rsrc2,   s_save_alloc_size, 8                    //NUM_RECORDS in bytes (64 threads)
+-    end
+-
+-    if (SWIZZLE_EN)
+-        s_add_u32       s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0                     //FIXME need to use swizzle to enable bounds checking?
+-    else
+         s_mov_b32       s_save_buf_rsrc2,  0x1000000                                //NUM_RECORDS in bytes
+-    end
+-
+ 
+     // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0
+     //s_mov_b64 s_save_pc_lo, s_save_buf_rsrc0
+@@ -490,30 +345,14 @@ end
+     s_mov_b32       exec_lo, 0xFFFFFFFF                                             //need every thread from now on
+     s_mov_b32       exec_hi, 0xFFFFFFFF
+ 
+-    if (SWIZZLE_EN)
+-        s_add_u32       s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0                     //FIXME need to use swizzle to enable bounds checking?
+-    else
+         s_mov_b32       s_save_buf_rsrc2,  0x1000000                                //NUM_RECORDS in bytes
+-    end
+-
+ 
+     // VGPR Allocated in 4-GPR granularity
+ 
+-if G8SR_VGPR_SR_IN_DWX4
+-        // the const stride for DWx4 is 4*4 bytes
+-        s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
+-        s_or_b32  s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4  // const stride to 4*4 bytes
+-
+-        buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
+-
+-        s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
+-        s_or_b32  s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE  // reset const stride to 4 bytes
+-else
+         buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
+         buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256
+         buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*2
+         buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*3
+-end
+ 
+ 
+ 
+@@ -549,64 +388,10 @@ end
+     s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes()
+ 
+ 
+-    if (SWIZZLE_EN)
+-        s_add_u32       s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0       //FIXME need to use swizzle to enable bounds checking?
+-    else
+         s_mov_b32       s_save_buf_rsrc2,  0x1000000                  //NUM_RECORDS in bytes
+-    end
+-
+     s_mov_b32       m0, 0x0                                               //lds_offset initial value = 0
+ 
+ 
+-var LDS_DMA_ENABLE = 0
+-var UNROLL = 0
+-if UNROLL==0 && LDS_DMA_ENABLE==1
+-        s_mov_b32  s3, 256*2
+-        s_nop 0
+-        s_nop 0
+-        s_nop 0
+-  L_SAVE_LDS_LOOP:
+-        //TODO: looks the 2 buffer_store/load clause for s/r will hurt performance.???
+-    if (SAVE_LDS)     //SPI always alloc LDS space in 128DW granularity
+-            buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1            // first 64DW
+-            buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW
+-    end
+-
+-    s_add_u32       m0, m0, s3                                          //every buffer_store_lds does 256 bytes
+-    s_add_u32       s_save_mem_offset, s_save_mem_offset, s3                            //mem offset increased by 256 bytes
+-    s_cmp_lt_u32    m0, s_save_alloc_size                                               //scc=(m0 < s_save_alloc_size) ? 1 : 0
+-    s_cbranch_scc1  L_SAVE_LDS_LOOP                                                     //LDS save is complete?
+-
+-elsif LDS_DMA_ENABLE==1 && UNROLL==1 // UNROOL  , has ichace miss
+-      // store from higest LDS address to lowest
+-      s_mov_b32  s3, 256*2
+-      s_sub_u32  m0, s_save_alloc_size, s3
+-      s_add_u32 s_save_mem_offset, s_save_mem_offset, m0
+-      s_lshr_b32 s_save_alloc_size, s_save_alloc_size, 9   // how many 128 trunks...
+-      s_sub_u32 s_save_alloc_size, 128, s_save_alloc_size   // store from higheset addr to lowest
+-      s_mul_i32 s_save_alloc_size, s_save_alloc_size, 6*4   // PC offset increment,  each LDS save block cost 6*4 Bytes instruction
+-      s_add_u32 s_save_alloc_size, s_save_alloc_size, 3*4   //2is the below 2 inst...//s_addc and s_setpc
+-      s_nop 0
+-      s_nop 0
+-      s_nop 0   //pad 3 dw to let LDS_DMA align with 64Bytes
+-      s_getpc_b64 s[0:1]                              // reuse s[0:1], since s[0:1] already saved
+-      s_add_u32   s0, s0,s_save_alloc_size
+-      s_addc_u32  s1, s1, 0
+-      s_setpc_b64 s[0:1]
+-
+-
+-       for var i =0; i< 128; i++
+-            // be careful to make here a 64Byte aligned address, which could improve performance...
+-            buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:0           // first 64DW
+-            buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256           // second 64DW
+-
+-        if i!=127
+-        s_sub_u32  m0, m0, s3      // use a sgpr to shrink 2DW-inst to 1DW inst to improve performance , i.e.  pack more LDS_DMA inst to one Cacheline
+-            s_sub_u32  s_save_mem_offset, s_save_mem_offset,  s3
+-            end
+-       end
+-
+-else   // BUFFER_STORE
+       v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0
+       v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2     // tid
+       v_mul_i32_i24 v2, v3, 8   // tid*8
+@@ -628,8 +413,6 @@ L_SAVE_LDS_LOOP_VECTOR:
+       // restore rsrc3
+       s_mov_b32 s_save_buf_rsrc3, s0
+ 
+-end
+-
+ L_SAVE_LDS_DONE:
+ 
+ 
+@@ -647,44 +430,8 @@ L_SAVE_LDS_DONE:
+     s_add_u32       s_save_alloc_size, s_save_alloc_size, 1
+     s_lshl_b32      s_save_alloc_size, s_save_alloc_size, 2                         //Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)   //FIXME for GFX, zero is possible
+     s_lshl_b32      s_save_buf_rsrc2,  s_save_alloc_size, 8                         //NUM_RECORDS in bytes (64 threads*4)
+-    if (SWIZZLE_EN)
+-        s_add_u32       s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0                     //FIXME need to use swizzle to enable bounds checking?
+-    else
+         s_mov_b32       s_save_buf_rsrc2,  0x1000000                                //NUM_RECORDS in bytes
+-    end
+-
+-
+-    // VGPR Allocated in 4-GPR granularity
+-
+-if G8SR_VGPR_SR_IN_DWX4
+-        // the const stride for DWx4 is 4*4 bytes
+-        s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
+-        s_or_b32  s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4  // const stride to 4*4 bytes
+-
+-        s_mov_b32         m0, 4     // skip first 4 VGPRs
+-        s_cmp_lt_u32      m0, s_save_alloc_size
+-        s_cbranch_scc0    L_SAVE_VGPR_LOOP_END      // no more vgprs
+ 
+-        s_set_gpr_idx_on  m0, 0x1   // This will change M0
+-        s_add_u32         s_save_alloc_size, s_save_alloc_size, 0x1000  // because above inst change m0
+-L_SAVE_VGPR_LOOP:
+-        v_mov_b32         v0, v0   // v0 = v[0+m0]
+-        v_mov_b32         v1, v1
+-        v_mov_b32         v2, v2
+-        v_mov_b32         v3, v3
+-
+-
+-        buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
+-        s_add_u32         m0, m0, 4
+-        s_add_u32         s_save_mem_offset, s_save_mem_offset, 256*4
+-        s_cmp_lt_u32      m0, s_save_alloc_size
+-    s_cbranch_scc1  L_SAVE_VGPR_LOOP                                                //VGPR save is complete?
+-    s_set_gpr_idx_off
+-L_SAVE_VGPR_LOOP_END:
+-
+-        s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
+-        s_or_b32  s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE  // reset const stride to 4 bytes
+-else
+     // VGPR store using dw burst
+     s_mov_b32         m0, 0x4   //VGPR initial index value =0
+     s_cmp_lt_u32      m0, s_save_alloc_size
+@@ -700,52 +447,18 @@ else
+     v_mov_b32       v2, v2              //v0 = v[0+m0]
+     v_mov_b32       v3, v3              //v0 = v[0+m0]
+ 
+-    if(USE_MTBUF_INSTEAD_OF_MUBUF)
+-        tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-    else
+         buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
+         buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256
+         buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*2
+         buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*3
+-    end
+ 
+     s_add_u32       m0, m0, 4                                                       //next vgpr index
+     s_add_u32       s_save_mem_offset, s_save_mem_offset, 256*4                     //every buffer_store_dword does 256 bytes
+     s_cmp_lt_u32    m0, s_save_alloc_size                                           //scc = (m0 < s_save_alloc_size) ? 1 : 0
+     s_cbranch_scc1  L_SAVE_VGPR_LOOP                                                //VGPR save is complete?
+     s_set_gpr_idx_off
+-end
+ 
+ L_SAVE_VGPR_END:
+-
+-
+-
+-
+-
+-
+-    /*     S_PGM_END_SAVED  */                              //FIXME  graphics ONLY
+-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT))
+-        s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff    //pc[47:32]
+-        s_add_u32 s_save_pc_lo, s_save_pc_lo, 4             //pc[31:0]+4
+-        s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0          //carry bit over
+-        s_rfe_b64 s_save_pc_lo                              //Return to the main shader program
+-    else
+-    end
+-
+-// Save Done timestamp
+-if G8SR_DEBUG_TIMESTAMP
+-        s_memrealtime   s_g8sr_ts_save_d
+-        // SGPR SR memory offset : size(VGPR)
+-        get_vgpr_size_bytes(s_save_mem_offset)
+-        s_add_u32 s_save_mem_offset, s_save_mem_offset, G8SR_DEBUG_TS_SAVE_D_OFFSET
+-        s_waitcnt lgkmcnt(0)         //FIXME, will cause xnack??
+-        // Need reset rsrc2??
+-        s_mov_b32 m0, s_save_mem_offset
+-        s_mov_b32 s_save_buf_rsrc2,  0x1000000                                  //NUM_RECORDS in bytes
+-        s_buffer_store_dwordx2 s_g8sr_ts_save_d, s_save_buf_rsrc0, m0       glc:1
+-end
+-
+-
+     s_branch    L_END_PGM
+ 
+ 
+@@ -756,27 +469,6 @@ end
+ 
+ L_RESTORE:
+     /*      Setup Resource Contants    */
+-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))
+-        //calculate wd_addr using absolute thread id
+-        v_readlane_b32 s_restore_tmp, v9, 0
+-        s_lshr_b32 s_restore_tmp, s_restore_tmp, 6
+-        s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE
+-        s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO
+-        s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI
+-        s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL
+-    else
+-    end
+-
+-if G8SR_DEBUG_TIMESTAMP
+-        s_memrealtime   s_g8sr_ts_restore_s
+-        s_waitcnt lgkmcnt(0)         //FIXME, will cause xnack??
+-        // tma_lo/hi are sgpr 110, 111, which will not used for 112 SGPR allocated case...
+-        s_mov_b32 s_restore_pc_lo, s_g8sr_ts_restore_s[0]
+-        s_mov_b32 s_restore_pc_hi, s_g8sr_ts_restore_s[1]   //backup ts to ttmp0/1, sicne exec will be finally restored..
+-end
+-
+-
+-
+     s_mov_b32       s_restore_buf_rsrc0,    s_restore_spi_init_lo                                                           //base_addr_lo
+     s_and_b32       s_restore_buf_rsrc1,    s_restore_spi_init_hi, 0x0000FFFF                                               //base_addr_hi
+     s_or_b32        s_restore_buf_rsrc1,    s_restore_buf_rsrc1,  S_RESTORE_BUF_RSRC_WORD1_STRIDE
+@@ -818,18 +510,12 @@ end
+     s_add_u32  s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes()            //FIXME, Check if offset overflow???
+ 
+ 
+-    if (SWIZZLE_EN)
+-        s_add_u32       s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0                       //FIXME need to use swizzle to enable bounds checking?
+-    else
+         s_mov_b32       s_restore_buf_rsrc2,  0x1000000                                     //NUM_RECORDS in bytes
+-    end
+     s_mov_b32       m0, 0x0                                                                 //lds_offset initial value = 0
+ 
+   L_RESTORE_LDS_LOOP:
+-    if (SAVE_LDS)
+         buffer_load_dword   v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1                    // first 64DW
+         buffer_load_dword   v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256         // second 64DW
+-    end
+     s_add_u32       m0, m0, 256*2                                               // 128 DW
+     s_add_u32       s_restore_mem_offset, s_restore_mem_offset, 256*2           //mem offset increased by 128DW
+     s_cmp_lt_u32    m0, s_restore_alloc_size                                    //scc=(m0 < s_restore_alloc_size) ? 1 : 0
+@@ -848,40 +534,8 @@ end
+     s_add_u32       s_restore_alloc_size, s_restore_alloc_size, 1
+     s_lshl_b32      s_restore_alloc_size, s_restore_alloc_size, 2                           //Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)
+     s_lshl_b32      s_restore_buf_rsrc2,  s_restore_alloc_size, 8                           //NUM_RECORDS in bytes (64 threads*4)
+-    if (SWIZZLE_EN)
+-        s_add_u32       s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0                       //FIXME need to use swizzle to enable bounds checking?
+-    else
+         s_mov_b32       s_restore_buf_rsrc2,  0x1000000                                     //NUM_RECORDS in bytes
+-    end
+-
+-if G8SR_VGPR_SR_IN_DWX4
+-     get_vgpr_size_bytes(s_restore_mem_offset)
+-     s_sub_u32         s_restore_mem_offset, s_restore_mem_offset, 256*4
+-
+-     // the const stride for DWx4 is 4*4 bytes
+-     s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
+-     s_or_b32  s_restore_buf_rsrc1, s_restore_buf_rsrc1, G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4  // const stride to 4*4 bytes
+-
+-     s_mov_b32         m0, s_restore_alloc_size
+-     s_set_gpr_idx_on  m0, 0x8    // Note.. This will change m0
+-
+-L_RESTORE_VGPR_LOOP:
+-     buffer_load_dwordx4 v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
+-     s_waitcnt vmcnt(0)
+-     s_sub_u32         m0, m0, 4
+-     v_mov_b32         v0, v0   // v[0+m0] = v0
+-     v_mov_b32         v1, v1
+-     v_mov_b32         v2, v2
+-     v_mov_b32         v3, v3
+-     s_sub_u32         s_restore_mem_offset, s_restore_mem_offset, 256*4
+-     s_cmp_eq_u32      m0, 0x8000
+-     s_cbranch_scc0    L_RESTORE_VGPR_LOOP
+-     s_set_gpr_idx_off
+-
+-     s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
+-     s_or_b32  s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE  // const stride to 4*4 bytes
+-
+-else
++
+     // VGPR load using dw burst
+     s_mov_b32       s_restore_mem_offset_save, s_restore_mem_offset     // restore start with v1, v0 will be the last
+     s_add_u32       s_restore_mem_offset, s_restore_mem_offset, 256*4
+@@ -890,14 +544,10 @@ else
+     s_add_u32       s_restore_alloc_size, s_restore_alloc_size, 0x8000                      //add 0x8000 since we compare m0 against it later
+ 
+   L_RESTORE_VGPR_LOOP:
+-    if(USE_MTBUF_INSTEAD_OF_MUBUF)
+-        tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-    else
+         buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
+         buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256
+         buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2
+         buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3
+-    end
+     s_waitcnt       vmcnt(0)                                                                //ensure data ready
+     v_mov_b32       v0, v0                                                                  //v[0+m0] = v0
+     v_mov_b32       v1, v1
+@@ -909,16 +559,10 @@ else
+     s_cbranch_scc1  L_RESTORE_VGPR_LOOP                                                     //VGPR restore (except v0) is complete?
+     s_set_gpr_idx_off
+                                                                                             /* VGPR restore on v0 */
+-    if(USE_MTBUF_INSTEAD_OF_MUBUF)
+-        tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-    else
+         buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1
+         buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1 offset:256
+         buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1 offset:256*2
+         buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1 offset:256*3
+-    end
+-
+-end
+ 
+     /*          restore SGPRs       */
+     //////////////////////////////
+@@ -934,16 +578,8 @@ end
+     s_add_u32       s_restore_alloc_size, s_restore_alloc_size, 1
+     s_lshl_b32      s_restore_alloc_size, s_restore_alloc_size, 4                           //Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value)
+ 
+-    if (SGPR_SAVE_USE_SQC)
+         s_lshl_b32      s_restore_buf_rsrc2,    s_restore_alloc_size, 2                     //NUM_RECORDS in bytes
+-    else
+-        s_lshl_b32      s_restore_buf_rsrc2,    s_restore_alloc_size, 8                     //NUM_RECORDS in bytes (64 threads)
+-    end
+-    if (SWIZZLE_EN)
+-        s_add_u32       s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0                       //FIXME need to use swizzle to enable bounds checking?
+-    else
+         s_mov_b32       s_restore_buf_rsrc2,  0x1000000                                     //NUM_RECORDS in bytes
+-    end
+ 
+     /* If 112 SGPRs ar allocated, 4 sgprs are not used TBA(108,109),TMA(110,111),
+        However, we are safe to restore these 4 SGPRs anyway, since TBA,TMA will later be restored by HWREG
+@@ -972,12 +608,6 @@ end
+     //////////////////////////////
+   L_RESTORE_HWREG:
+ 
+-
+-if G8SR_DEBUG_TIMESTAMP
+-      s_mov_b32 s_g8sr_ts_restore_s[0], s_restore_pc_lo
+-      s_mov_b32 s_g8sr_ts_restore_s[1], s_restore_pc_hi
+-end
+-
+     // HWREG SR memory offset : size(VGPR)+size(SGPR)
+     get_vgpr_size_bytes(s_restore_mem_offset)
+     get_sgpr_size_bytes(s_restore_tmp)
+@@ -985,11 +615,7 @@ end
+ 
+ 
+     s_mov_b32       s_restore_buf_rsrc2, 0x4                                                //NUM_RECORDS   in bytes
+-    if (SWIZZLE_EN)
+-        s_add_u32       s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0                       //FIXME need to use swizzle to enable bounds checking?
+-    else
+         s_mov_b32       s_restore_buf_rsrc2,  0x1000000                                     //NUM_RECORDS in bytes
+-    end
+ 
+     read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset)                    //M0
+     read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset)             //PC
+@@ -1006,16 +632,6 @@ end
+ 
+     s_waitcnt       lgkmcnt(0)                                                                                      //from now on, it is safe to restore STATUS and IB_STS
+ 
+-    //for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise:
+-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))
+-        s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8            //pc[31:0]+8     //two back-to-back s_trap are used (first for save and second for restore)
+-        s_addc_u32  s_restore_pc_hi, s_restore_pc_hi, 0x0        //carry bit over
+-    end
+-    if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL))
+-        s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4            //pc[31:0]+4     // save is hack through s_trap but restore is normal
+-        s_addc_u32  s_restore_pc_hi, s_restore_pc_hi, 0x0        //carry bit over
+-    end
+-
+     s_mov_b32       m0,         s_restore_m0
+     s_mov_b32       exec_lo,    s_restore_exec_lo
+     s_mov_b32       exec_hi,    s_restore_exec_hi
+@@ -1048,11 +664,6 @@ end
+ 
+     s_barrier                                                   //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time
+ 
+-if G8SR_DEBUG_TIMESTAMP
+-    s_memrealtime s_g8sr_ts_restore_d
+-    s_waitcnt lgkmcnt(0)
+-end
+-
+ //  s_rfe_b64 s_restore_pc_lo                                   //Return to the main shader program and resume execution
+     s_rfe_restore_b64  s_restore_pc_lo, s_restore_m0            // s_restore_m0[0] is used to set STATUS.inst_atc
+ 
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
+index cee4cfd5182d..75f29d13c90f 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
+@@ -24,75 +24,6 @@
+  * PROJECT=greenland ./sp3 cwsr_trap_handler_gfx9.asm -hex tmp.hex
+  */
+ 
+-/* HW (GFX9) source code for CWSR trap handler */
+-/* Version 18 + multiple trap handler */
+-
+-// this performance-optimal version was originally from Seven Xu at SRDC
+-
+-// Revison #18	 --...
+-/* Rev History
+-** #1. Branch from gc dv.   //gfxip/gfx9/main/src/test/suites/block/cs/sr/cs_trap_handler.sp3#1,#50, #51, #52-53(Skip, Already Fixed by PV), #54-56(merged),#57-58(mergerd, skiped-already fixed by PV)
+-** #4. SR Memory Layout:
+-**			 1. VGPR-SGPR-HWREG-{LDS}
+-**			 2. tba_hi.bits.26 - reconfigured as the first wave in tg bits, for defer Save LDS for a threadgroup.. performance concern..
+-** #5. Update: 1. Accurate g8sr_ts_save_d timestamp
+-** #6. Update: 1. Fix s_barrier usage; 2. VGPR s/r using swizzle buffer?(NoNeed, already matched the swizzle pattern, more investigation)
+-** #7. Update: 1. don't barrier if noLDS
+-** #8. Branch: 1. Branch to ver#0, which is very similar to gc dv version
+-**	       2. Fix SQ issue by s_sleep 2
+-** #9. Update: 1. Fix scc restore failed issue, restore wave_status at last
+-**	       2. optimize s_buffer save by burst 16sgprs...
+-** #10. Update 1. Optimize restore sgpr by busrt 16 sgprs.
+-** #11. Update 1. Add 2 more timestamp for debug version
+-** #12. Update 1. Add VGPR SR using DWx4, some case improve and some case drop performance
+-** #13. Integ  1. Always use MUBUF for PV trap shader...
+-** #14. Update 1. s_buffer_store soft clause...
+-** #15. Update 1. PERF - sclar write with glc:0/mtype0 to allow L2 combine. perf improvement a lot.
+-** #16. Update 1. PRRF - UNROLL LDS_DMA got 2500cycle save in IP tree
+-** #17. Update 1. FUNC - LDS_DMA has issues while ATC, replace with ds_read/buffer_store for save part[TODO restore part]
+-**	       2. PERF - Save LDS before save VGPR to cover LDS save long latency...
+-** #18. Update 1. FUNC - Implicitly estore STATUS.VCCZ, which is not writable by s_setreg_b32
+-**	       2. FUNC - Handle non-CWSR traps
+-*/
+-
+-var G8SR_WDMEM_HWREG_OFFSET = 0
+-var G8SR_WDMEM_SGPR_OFFSET  = 128  // in bytes
+-
+-// Keep definition same as the app shader, These 2 time stamps are part of the app shader... Should before any Save and after restore.
+-
+-var G8SR_DEBUG_TIMESTAMP = 0
+-var G8SR_DEBUG_TS_SAVE_D_OFFSET = 40*4	// ts_save_d timestamp offset relative to SGPR_SR_memory_offset
+-var s_g8sr_ts_save_s	= s[34:35]   // save start
+-var s_g8sr_ts_sq_save_msg  = s[36:37]	// The save shader send SAVEWAVE msg to spi
+-var s_g8sr_ts_spi_wrexec   = s[38:39]	// the SPI write the sr address to SQ
+-var s_g8sr_ts_save_d	= s[40:41]   // save end
+-var s_g8sr_ts_restore_s = s[42:43]   // restore start
+-var s_g8sr_ts_restore_d = s[44:45]   // restore end
+-
+-var G8SR_VGPR_SR_IN_DWX4 = 0
+-var G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 = 0x00100000	 // DWx4 stride is 4*4Bytes
+-var G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4  = G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4
+-
+-
+-/*************************************************************************/
+-/*		    control on how to run the shader			 */
+-/*************************************************************************/
+-//any hack that needs to be made to run this code in EMU (either because various EMU code are not ready or no compute save & restore in EMU run)
+-var EMU_RUN_HACK		    =	0
+-var EMU_RUN_HACK_RESTORE_NORMAL	    =	0
+-var EMU_RUN_HACK_SAVE_NORMAL_EXIT   =	0
+-var EMU_RUN_HACK_SAVE_SINGLE_WAVE   =	0
+-var EMU_RUN_HACK_SAVE_FIRST_TIME    =	0		    //for interrupted restore in which the first save is through EMU_RUN_HACK
+-var SAVE_LDS			    =	1
+-var WG_BASE_ADDR_LO		    =	0x9000a000
+-var WG_BASE_ADDR_HI		    =	0x0
+-var WAVE_SPACE			    =	0x5000		    //memory size that each wave occupies in workgroup state mem
+-var CTX_SAVE_CONTROL		    =	0x0
+-var CTX_RESTORE_CONTROL		    =	CTX_SAVE_CONTROL
+-var SIM_RUN_HACK		    =	0		    //any hack that needs to be made to run this code in SIM (either because various RTL code are not ready or no compute save & restore in RTL run)
+-var SGPR_SAVE_USE_SQC		    =	1		    //use SQC D$ to do the write
+-var USE_MTBUF_INSTEAD_OF_MUBUF	    =	0		    //because TC EMU currently asserts on 0 of // overload DFMT field to carry 4 more bits of stride for MUBUF opcodes
+-var SWIZZLE_EN			    =	0		    //whether we use swizzled buffer addressing
+ var ACK_SQC_STORE		    =	1		    //workaround for suspected SQC store bug causing incorrect stores under concurrency
+ var SAVE_AFTER_XNACK_ERROR	    =	1		    //workaround for TCP store failure after XNACK error when ALLOW_REPLAY=0, for debugger
+ var SINGLE_STEP_MISSED_WORKAROUND   =	1		    //workaround for lost MODE.DEBUG_EN exception when SAVECTX raised
+@@ -238,16 +169,7 @@ shader main
+   type(CS)
+ 
+ 
+-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))		    //hack to use trap_id for determining save/restore
+-	//FIXME VCCZ un-init assertion s_getreg_b32	s_save_status, hwreg(HW_REG_STATUS)	    //save STATUS since we will change SCC
+-	s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000		    //change SCC
+-	s_cmp_eq_u32 s_save_tmp, 0x007e0000			    //Save: trap_id = 0x7e. Restore: trap_id = 0x7f.
+-	s_cbranch_scc0 L_JUMP_TO_RESTORE			    //do not need to recover STATUS here  since we are going to RESTORE
+-	//FIXME	 s_setreg_b32	hwreg(HW_REG_STATUS),	s_save_status	    //need to recover STATUS since we are going to SAVE
+-	s_branch L_SKIP_RESTORE					    //NOT restore, SAVE actually
+-    else
+ 	s_branch L_SKIP_RESTORE					    //NOT restore. might be a regular trap or save
+-    end
+ 
+ L_JUMP_TO_RESTORE:
+     s_branch L_RESTORE						    //restore
+@@ -278,7 +200,7 @@ end
+     s_cbranch_scc1  L_SAVE					//this is the operation for save
+ 
+     // *********    Handle non-CWSR traps	*******************
+-if (!EMU_RUN_HACK)
++
+     // Illegal instruction is a non-maskable exception which blocks context save.
+     // Halt the wavefront and return from the trap.
+     s_and_b32       ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK
+@@ -355,7 +277,7 @@ L_EXCP_CASE:
+     set_status_without_spi_prio(s_save_status, ttmp2)
+ 
+     s_rfe_b64       [ttmp0, ttmp1]
+-end
++
+     // *********	End handling of non-CWSR traps	 *******************
+ 
+ /**************************************************************************/
+@@ -363,12 +285,6 @@ end
+ /**************************************************************************/
+ 
+ L_SAVE:
+-
+-if G8SR_DEBUG_TIMESTAMP
+-	s_memrealtime	s_g8sr_ts_save_s
+-	s_waitcnt lgkmcnt(0)	     //FIXME, will cause xnack??
+-end
+-
+     s_and_b32	    s_save_pc_hi, s_save_pc_hi, 0x0000ffff    //pc[47:32]
+ 
+     s_mov_b32	    s_save_tmp, 0							    //clear saveCtx bit
+@@ -390,16 +306,7 @@ end
+     s_mov_b32	    s_save_exec_hi, exec_hi
+     s_mov_b64	    exec,   0x0								    //clear EXEC to get ready to receive
+ 
+-if G8SR_DEBUG_TIMESTAMP
+-	s_memrealtime  s_g8sr_ts_sq_save_msg
+-	s_waitcnt lgkmcnt(0)
+-end
+-
+-    if (EMU_RUN_HACK)
+-
+-    else
+ 	s_sendmsg   sendmsg(MSG_SAVEWAVE)  //send SPI a message and wait for SPI's write to EXEC
+-    end
+ 
+     // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for.
+     s_or_b32 s_save_tmp, s_save_status, (2 << SQ_WAVE_STATUS_SPI_PRIO_SHIFT)
+@@ -408,33 +315,7 @@ end
+   L_SLEEP:
+     s_sleep 0x2		       // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0
+ 
+-    if (EMU_RUN_HACK)
+-
+-    else
+ 	s_cbranch_execz L_SLEEP
+-    end
+-
+-if G8SR_DEBUG_TIMESTAMP
+-	s_memrealtime  s_g8sr_ts_spi_wrexec
+-	s_waitcnt lgkmcnt(0)
+-end
+-
+-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE))
+-	//calculate wd_addr using absolute thread id
+-	v_readlane_b32 s_save_tmp, v9, 0
+-	s_lshr_b32 s_save_tmp, s_save_tmp, 6
+-	s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE
+-	s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO
+-	s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI
+-	s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL
+-    else
+-    end
+-    if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE))
+-	s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO
+-	s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI
+-	s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL
+-    else
+-    end
+ 
+     // Save trap temporaries 4-11, 13 initialized by SPI debug dispatch logic
+     // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40
+@@ -484,20 +365,10 @@ end
+ 
+ 
+     s_mov_b32	    s_save_buf_rsrc2, 0x4				//NUM_RECORDS	in bytes
+-    if (SWIZZLE_EN)
+-	s_add_u32	s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0			    //FIXME need to use swizzle to enable bounds checking?
+-    else
+ 	s_mov_b32	s_save_buf_rsrc2,  0x1000000				    //NUM_RECORDS in bytes
+-    end
+ 
+ 
+     write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)			//M0
+-
+-    if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME))
+-	s_add_u32 s_save_pc_lo, s_save_pc_lo, 4		    //pc[31:0]+4
+-	s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0	    //carry bit over
+-    end
+-
+     write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset)		    //PC
+     write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset)
+     write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset)		//EXEC
+@@ -535,17 +406,9 @@ end
+     s_add_u32	    s_save_alloc_size, s_save_alloc_size, 1
+     s_lshl_b32	    s_save_alloc_size, s_save_alloc_size, 4			    //Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value)
+ 
+-    if (SGPR_SAVE_USE_SQC)
+ 	s_lshl_b32	s_save_buf_rsrc2,   s_save_alloc_size, 2		    //NUM_RECORDS in bytes
+-    else
+-	s_lshl_b32	s_save_buf_rsrc2,   s_save_alloc_size, 8		    //NUM_RECORDS in bytes (64 threads)
+-    end
+ 
+-    if (SWIZZLE_EN)
+-	s_add_u32	s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0			    //FIXME need to use swizzle to enable bounds checking?
+-    else
+ 	s_mov_b32	s_save_buf_rsrc2,  0x1000000				    //NUM_RECORDS in bytes
+-    end
+ 
+ 
+     // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0
+@@ -588,25 +451,11 @@ end
+     s_mov_b32	    xnack_mask_lo, 0x0
+     s_mov_b32	    xnack_mask_hi, 0x0
+ 
+-    if (SWIZZLE_EN)
+-	s_add_u32	s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0			    //FIXME need to use swizzle to enable bounds checking?
+-    else
+ 	s_mov_b32	s_save_buf_rsrc2,  0x1000000				    //NUM_RECORDS in bytes
+-    end
+ 
+ 
+     // VGPR Allocated in 4-GPR granularity
+ 
+-if G8SR_VGPR_SR_IN_DWX4
+-	// the const stride for DWx4 is 4*4 bytes
+-	s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
+-	s_or_b32  s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4  // const stride to 4*4 bytes
+-
+-	buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
+-
+-	s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
+-	s_or_b32  s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE  // reset const stride to 4 bytes
+-else
+ if SAVE_AFTER_XNACK_ERROR
+ 	check_if_tcp_store_ok()
+ 	s_cbranch_scc1 L_SAVE_FIRST_VGPRS_WITH_TCP
+@@ -621,7 +470,6 @@ end
+ 	buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256
+ 	buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*2
+ 	buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*3
+-end
+ 
+ 
+ 
+@@ -656,64 +504,11 @@ end
+     s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes()
+ 
+ 
+-    if (SWIZZLE_EN)
+-	s_add_u32	s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0	      //FIXME need to use swizzle to enable bounds checking?
+-    else
+ 	s_mov_b32	s_save_buf_rsrc2,  0x1000000		      //NUM_RECORDS in bytes
+-    end
+ 
+     s_mov_b32	    m0, 0x0						  //lds_offset initial value = 0
+ 
+ 
+-var LDS_DMA_ENABLE = 0
+-var UNROLL = 0
+-if UNROLL==0 && LDS_DMA_ENABLE==1
+-	s_mov_b32  s3, 256*2
+-	s_nop 0
+-	s_nop 0
+-	s_nop 0
+-  L_SAVE_LDS_LOOP:
+-	//TODO: looks the 2 buffer_store/load clause for s/r will hurt performance.???
+-    if (SAVE_LDS)     //SPI always alloc LDS space in 128DW granularity
+-	    buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1		// first 64DW
+-	    buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW
+-    end
+-
+-    s_add_u32	    m0, m0, s3						//every buffer_store_lds does 256 bytes
+-    s_add_u32	    s_save_mem_offset, s_save_mem_offset, s3				//mem offset increased by 256 bytes
+-    s_cmp_lt_u32    m0, s_save_alloc_size						//scc=(m0 < s_save_alloc_size) ? 1 : 0
+-    s_cbranch_scc1  L_SAVE_LDS_LOOP							//LDS save is complete?
+-
+-elsif LDS_DMA_ENABLE==1 && UNROLL==1 // UNROOL	, has ichace miss
+-      // store from higest LDS address to lowest
+-      s_mov_b32	 s3, 256*2
+-      s_sub_u32	 m0, s_save_alloc_size, s3
+-      s_add_u32 s_save_mem_offset, s_save_mem_offset, m0
+-      s_lshr_b32 s_save_alloc_size, s_save_alloc_size, 9   // how many 128 trunks...
+-      s_sub_u32 s_save_alloc_size, 128, s_save_alloc_size   // store from higheset addr to lowest
+-      s_mul_i32 s_save_alloc_size, s_save_alloc_size, 6*4   // PC offset increment,  each LDS save block cost 6*4 Bytes instruction
+-      s_add_u32 s_save_alloc_size, s_save_alloc_size, 3*4   //2is the below 2 inst...//s_addc and s_setpc
+-      s_nop 0
+-      s_nop 0
+-      s_nop 0	//pad 3 dw to let LDS_DMA align with 64Bytes
+-      s_getpc_b64 s[0:1]			      // reuse s[0:1], since s[0:1] already saved
+-      s_add_u32	  s0, s0,s_save_alloc_size
+-      s_addc_u32  s1, s1, 0
+-      s_setpc_b64 s[0:1]
+-
+-
+-       for var i =0; i< 128; i++
+-	    // be careful to make here a 64Byte aligned address, which could improve performance...
+-	    buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:0		// first 64DW
+-	    buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256		  // second 64DW
+-
+-	if i!=127
+-	s_sub_u32  m0, m0, s3	   // use a sgpr to shrink 2DW-inst to 1DW inst to improve performance , i.e.  pack more LDS_DMA inst to one Cacheline
+-	    s_sub_u32  s_save_mem_offset, s_save_mem_offset,  s3
+-	    end
+-       end
+-
+-else   // BUFFER_STORE
+       v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0
+       v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2	// tid
+ 
+@@ -757,8 +552,6 @@ L_SAVE_LDS_LOOP_VECTOR:
+       // restore rsrc3
+       s_mov_b32 s_save_buf_rsrc3, s0
+ 
+-end
+-
+ L_SAVE_LDS_DONE:
+ 
+ 
+@@ -776,44 +569,9 @@ L_SAVE_LDS_DONE:
+     s_add_u32	    s_save_alloc_size, s_save_alloc_size, 1
+     s_lshl_b32	    s_save_alloc_size, s_save_alloc_size, 2			    //Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)	  //FIXME for GFX, zero is possible
+     s_lshl_b32	    s_save_buf_rsrc2,  s_save_alloc_size, 8			    //NUM_RECORDS in bytes (64 threads*4)
+-    if (SWIZZLE_EN)
+-	s_add_u32	s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0			    //FIXME need to use swizzle to enable bounds checking?
+-    else
+ 	s_mov_b32	s_save_buf_rsrc2,  0x1000000				    //NUM_RECORDS in bytes
+-    end
+ 
+ 
+-    // VGPR Allocated in 4-GPR granularity
+-
+-if G8SR_VGPR_SR_IN_DWX4
+-	// the const stride for DWx4 is 4*4 bytes
+-	s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
+-	s_or_b32  s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4  // const stride to 4*4 bytes
+-
+-	s_mov_b32	  m0, 4	    // skip first 4 VGPRs
+-	s_cmp_lt_u32	  m0, s_save_alloc_size
+-	s_cbranch_scc0	  L_SAVE_VGPR_LOOP_END	    // no more vgprs
+-
+-	s_set_gpr_idx_on  m0, 0x1   // This will change M0
+-	s_add_u32	  s_save_alloc_size, s_save_alloc_size, 0x1000	// because above inst change m0
+-L_SAVE_VGPR_LOOP:
+-	v_mov_b32	  v0, v0   // v0 = v[0+m0]
+-	v_mov_b32	  v1, v1
+-	v_mov_b32	  v2, v2
+-	v_mov_b32	  v3, v3
+-
+-
+-	buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
+-	s_add_u32	  m0, m0, 4
+-	s_add_u32	  s_save_mem_offset, s_save_mem_offset, 256*4
+-	s_cmp_lt_u32	  m0, s_save_alloc_size
+-    s_cbranch_scc1  L_SAVE_VGPR_LOOP						    //VGPR save is complete?
+-    s_set_gpr_idx_off
+-L_SAVE_VGPR_LOOP_END:
+-
+-	s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
+-	s_or_b32  s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE  // reset const stride to 4 bytes
+-else
+     // VGPR store using dw burst
+     s_mov_b32	      m0, 0x4	//VGPR initial index value =0
+     s_cmp_lt_u32      m0, s_save_alloc_size
+@@ -844,21 +602,16 @@ end
+     v_mov_b32	    v2, v2		//v0 = v[0+m0]
+     v_mov_b32	    v3, v3		//v0 = v[0+m0]
+ 
+-    if(USE_MTBUF_INSTEAD_OF_MUBUF)
+-	tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-    else
+ 	buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
+ 	buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256
+ 	buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*2
+ 	buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*3
+-    end
+ 
+     s_add_u32	    m0, m0, 4							    //next vgpr index
+     s_add_u32	    s_save_mem_offset, s_save_mem_offset, 256*4			    //every buffer_store_dword does 256 bytes
+     s_cmp_lt_u32    m0, s_save_alloc_size					    //scc = (m0 < s_save_alloc_size) ? 1 : 0
+     s_cbranch_scc1  L_SAVE_VGPR_LOOP						    //VGPR save is complete?
+     s_set_gpr_idx_off
+-end
+ 
+ L_SAVE_VGPR_END:
+ 
+@@ -905,29 +658,6 @@ L_SAVE_ACCVGPR_LOOP:
+ L_SAVE_ACCVGPR_END:
+ end
+ 
+-    /*	   S_PGM_END_SAVED  */				    //FIXME  graphics ONLY
+-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT))
+-	s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff    //pc[47:32]
+-	s_add_u32 s_save_pc_lo, s_save_pc_lo, 4		    //pc[31:0]+4
+-	s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0	    //carry bit over
+-	s_rfe_b64 s_save_pc_lo				    //Return to the main shader program
+-    else
+-    end
+-
+-// Save Done timestamp
+-if G8SR_DEBUG_TIMESTAMP
+-	s_memrealtime	s_g8sr_ts_save_d
+-	// SGPR SR memory offset : size(VGPR)
+-	get_vgpr_size_bytes(s_save_mem_offset)
+-	s_add_u32 s_save_mem_offset, s_save_mem_offset, G8SR_DEBUG_TS_SAVE_D_OFFSET
+-	s_waitcnt lgkmcnt(0)	     //FIXME, will cause xnack??
+-	// Need reset rsrc2??
+-	s_mov_b32 m0, s_save_mem_offset
+-	s_mov_b32 s_save_buf_rsrc2,  0x1000000					//NUM_RECORDS in bytes
+-	s_buffer_store_dwordx2 s_g8sr_ts_save_d, s_save_buf_rsrc0, m0	    glc:1
+-end
+-
+-
+     s_branch	L_END_PGM
+ 
+ 
+@@ -938,27 +668,6 @@ end
+ 
+ L_RESTORE:
+     /*	    Setup Resource Contants    */
+-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))
+-	//calculate wd_addr using absolute thread id
+-	v_readlane_b32 s_restore_tmp, v9, 0
+-	s_lshr_b32 s_restore_tmp, s_restore_tmp, 6
+-	s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE
+-	s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO
+-	s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI
+-	s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL
+-    else
+-    end
+-
+-if G8SR_DEBUG_TIMESTAMP
+-	s_memrealtime	s_g8sr_ts_restore_s
+-	s_waitcnt lgkmcnt(0)	     //FIXME, will cause xnack??
+-	// tma_lo/hi are sgpr 110, 111, which will not used for 112 SGPR allocated case...
+-	s_mov_b32 s_restore_pc_lo, s_g8sr_ts_restore_s[0]
+-	s_mov_b32 s_restore_pc_hi, s_g8sr_ts_restore_s[1]   //backup ts to ttmp0/1, sicne exec will be finally restored..
+-end
+-
+-
+-
+     s_mov_b32	    s_restore_buf_rsrc0,    s_restore_spi_init_lo							    //base_addr_lo
+     s_and_b32	    s_restore_buf_rsrc1,    s_restore_spi_init_hi, 0x0000FFFF						    //base_addr_hi
+     s_or_b32	    s_restore_buf_rsrc1,    s_restore_buf_rsrc1,  S_RESTORE_BUF_RSRC_WORD1_STRIDE
+@@ -1000,18 +709,12 @@ end
+     s_add_u32  s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes()	     //FIXME, Check if offset overflow???
+ 
+ 
+-    if (SWIZZLE_EN)
+-	s_add_u32	s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0			    //FIXME need to use swizzle to enable bounds checking?
+-    else
+ 	s_mov_b32	s_restore_buf_rsrc2,  0x1000000					    //NUM_RECORDS in bytes
+-    end
+     s_mov_b32	    m0, 0x0								    //lds_offset initial value = 0
+ 
+   L_RESTORE_LDS_LOOP:
+-    if (SAVE_LDS)
+ 	buffer_load_dword   v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1		       // first 64DW
+ 	buffer_load_dword   v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256	       // second 64DW
+-    end
+     s_add_u32	    m0, m0, 256*2						// 128 DW
+     s_add_u32	    s_restore_mem_offset, s_restore_mem_offset, 256*2		//mem offset increased by 128DW
+     s_cmp_lt_u32    m0, s_restore_alloc_size					//scc=(m0 < s_restore_alloc_size) ? 1 : 0
+@@ -1035,40 +738,8 @@ if ASIC_TARGET_ARCTURUS
+     s_mov_b32	    s_restore_accvgpr_offset, s_restore_buf_rsrc2                           //ACC VGPRs at end of VGPRs
+ end
+ 
+-    if (SWIZZLE_EN)
+-	s_add_u32	s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0			    //FIXME need to use swizzle to enable bounds checking?
+-    else
+ 	s_mov_b32	s_restore_buf_rsrc2,  0x1000000					    //NUM_RECORDS in bytes
+-    end
+ 
+-if G8SR_VGPR_SR_IN_DWX4
+-     get_vgpr_size_bytes(s_restore_mem_offset)
+-     s_sub_u32	       s_restore_mem_offset, s_restore_mem_offset, 256*4
+-
+-     // the const stride for DWx4 is 4*4 bytes
+-     s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
+-     s_or_b32  s_restore_buf_rsrc1, s_restore_buf_rsrc1, G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4  // const stride to 4*4 bytes
+-
+-     s_mov_b32	       m0, s_restore_alloc_size
+-     s_set_gpr_idx_on  m0, 0x8	  // Note.. This will change m0
+-
+-L_RESTORE_VGPR_LOOP:
+-     buffer_load_dwordx4 v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
+-     s_waitcnt vmcnt(0)
+-     s_sub_u32	       m0, m0, 4
+-     v_mov_b32	       v0, v0	// v[0+m0] = v0
+-     v_mov_b32	       v1, v1
+-     v_mov_b32	       v2, v2
+-     v_mov_b32	       v3, v3
+-     s_sub_u32	       s_restore_mem_offset, s_restore_mem_offset, 256*4
+-     s_cmp_eq_u32      m0, 0x8000
+-     s_cbranch_scc0    L_RESTORE_VGPR_LOOP
+-     s_set_gpr_idx_off
+-
+-     s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
+-     s_or_b32  s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE  // const stride to 4*4 bytes
+-
+-else
+     // VGPR load using dw burst
+     s_mov_b32	    s_restore_mem_offset_save, s_restore_mem_offset	// restore start with v1, v0 will be the last
+     s_add_u32	    s_restore_mem_offset, s_restore_mem_offset, 256*4
+@@ -1081,9 +752,6 @@ end
+     s_add_u32	    s_restore_alloc_size, s_restore_alloc_size, 0x8000			    //add 0x8000 since we compare m0 against it later
+ 
+   L_RESTORE_VGPR_LOOP:
+-    if(USE_MTBUF_INSTEAD_OF_MUBUF)
+-	tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-    else
+ 
+ if ASIC_TARGET_ARCTURUS
+ 	buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1
+@@ -1102,7 +770,6 @@ end
+ 	buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256
+ 	buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2
+ 	buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3
+-    end
+     s_waitcnt	    vmcnt(0)								    //ensure data ready
+     v_mov_b32	    v0, v0								    //v[0+m0] = v0
+     v_mov_b32	    v1, v1
+@@ -1126,16 +793,10 @@ if ASIC_TARGET_ARCTURUS
+ 	end
+ end
+ 
+-    if(USE_MTBUF_INSTEAD_OF_MUBUF)
+-	tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
+-    else
+ 	buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1
+ 	buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1 offset:256
+ 	buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1 offset:256*2
+ 	buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1 offset:256*3
+-    end
+-
+-end
+ 
+     /*		restore SGPRs	    */
+     //////////////////////////////
+@@ -1151,16 +812,8 @@ end
+     s_add_u32	    s_restore_alloc_size, s_restore_alloc_size, 1
+     s_lshl_b32	    s_restore_alloc_size, s_restore_alloc_size, 4			    //Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value)
+ 
+-    if (SGPR_SAVE_USE_SQC)
+ 	s_lshl_b32	s_restore_buf_rsrc2,	s_restore_alloc_size, 2			    //NUM_RECORDS in bytes
+-    else
+-	s_lshl_b32	s_restore_buf_rsrc2,	s_restore_alloc_size, 8			    //NUM_RECORDS in bytes (64 threads)
+-    end
+-    if (SWIZZLE_EN)
+-	s_add_u32	s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0			    //FIXME need to use swizzle to enable bounds checking?
+-    else
+ 	s_mov_b32	s_restore_buf_rsrc2,  0x1000000					    //NUM_RECORDS in bytes
+-    end
+ 
+     s_mov_b32 m0, s_restore_alloc_size
+ 
+@@ -1188,11 +841,6 @@ end
+   L_RESTORE_HWREG:
+ 
+ 
+-if G8SR_DEBUG_TIMESTAMP
+-      s_mov_b32 s_g8sr_ts_restore_s[0], s_restore_pc_lo
+-      s_mov_b32 s_g8sr_ts_restore_s[1], s_restore_pc_hi
+-end
+-
+     // HWREG SR memory offset : size(VGPR)+size(SGPR)
+     get_vgpr_size_bytes(s_restore_mem_offset)
+     get_sgpr_size_bytes(s_restore_tmp)
+@@ -1200,11 +848,7 @@ end
+ 
+ 
+     s_mov_b32	    s_restore_buf_rsrc2, 0x4						    //NUM_RECORDS   in bytes
+-    if (SWIZZLE_EN)
+-	s_add_u32	s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0			    //FIXME need to use swizzle to enable bounds checking?
+-    else
+ 	s_mov_b32	s_restore_buf_rsrc2,  0x1000000					    //NUM_RECORDS in bytes
+-    end
+ 
+     read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset)		    //M0
+     read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset)		//PC
+@@ -1219,16 +863,6 @@ end
+ 
+     s_waitcnt	    lgkmcnt(0)											    //from now on, it is safe to restore STATUS and IB_STS
+ 
+-    //for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise:
+-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))
+-	s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8		 //pc[31:0]+8	  //two back-to-back s_trap are used (first for save and second for restore)
+-	s_addc_u32  s_restore_pc_hi, s_restore_pc_hi, 0x0	 //carry bit over
+-    end
+-    if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL))
+-	s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4		 //pc[31:0]+4	  // save is hack through s_trap but restore is normal
+-	s_addc_u32  s_restore_pc_hi, s_restore_pc_hi, 0x0	 //carry bit over
+-    end
+-
+     s_mov_b32	    m0,		s_restore_m0
+     s_mov_b32	    exec_lo,	s_restore_exec_lo
+     s_mov_b32	    exec_hi,	s_restore_exec_hi
+@@ -1275,11 +909,6 @@ end
+ 
+     s_barrier							//barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time
+ 
+-if G8SR_DEBUG_TIMESTAMP
+-    s_memrealtime s_g8sr_ts_restore_d
+-    s_waitcnt lgkmcnt(0)
+-end
+-
+ //  s_rfe_b64 s_restore_pc_lo					//Return to the main shader program and resume execution
+     s_rfe_restore_b64  s_restore_pc_lo, s_restore_m0		// s_restore_m0[0] is used to set STATUS.inst_atc
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3121-drm-amdgpu-add-perfmon-and-fica-atomics-for-df.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3121-drm-amdgpu-add-perfmon-and-fica-atomics-for-df.patch
new file mode 100644
index 00000000..880c1321
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3121-drm-amdgpu-add-perfmon-and-fica-atomics-for-df.patch
@@ -0,0 +1,338 @@
+From b5c4e0f89339081b9b6e8008b2652f90e6bef53d Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Tue, 9 Jul 2019 15:47:57 -0400
+Subject: [PATCH 3121/4256] drm/amdgpu: add perfmon and fica atomics for df
+
+adding perfmon and fica atomic operations to adhere to data fabrics finite
+state machine requirements for indirect register access.
+
+Change-Id: I36c8fbe8b2df2ee848ac5b3bb931557c5488cd13
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+Reviewed-by: Kent Russell <Kent.Russell@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h  |   3 +
+ drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 202 +++++++++++++++++----------
+ 2 files changed, 128 insertions(+), 77 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index c3885b95727a..fcb92ec6b73d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -727,6 +727,9 @@ struct amdgpu_df_funcs {
+                                          int is_disable);
+         void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
+                                          uint64_t *count);
++	uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
++        void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
++                        uint32_t ficadl_val, uint32_t ficadh_val);
+ };
+ /* Define the HW IP blocks will be used in driver , add more if necessary */
+ enum amd_hw_ip_block_type {
+diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+index 7e0e8cda31b7..47ba0b31a8a4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
++++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+@@ -93,6 +93,96 @@ const struct attribute_group *df_v3_6_attr_groups[] = {
+ 		NULL
+ };
+ 
++static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
++				 uint32_t ficaa_val)
++{
++	unsigned long flags, address, data;
++	uint32_t ficadl_val, ficadh_val;
++
++	address = adev->nbio_funcs->get_pcie_index_offset(adev);
++	data = adev->nbio_funcs->get_pcie_data_offset(adev);
++
++	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
++	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
++	WREG32(data, ficaa_val);
++
++	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3);
++	ficadl_val = RREG32(data);
++
++	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
++	ficadh_val = RREG32(data);
++
++	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
++
++	return (((ficadh_val & 0xFFFFFFFFFFFFFFFF) << 32) | ficadl_val);
++}
++
++static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
++			     uint32_t ficadl_val, uint32_t ficadh_val)
++{
++	unsigned long flags, address, data;
++
++	address = adev->nbio_funcs->get_pcie_index_offset(adev);
++	data = adev->nbio_funcs->get_pcie_data_offset(adev);
++
++	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
++	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
++	WREG32(data, ficaa_val);
++
++	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3);
++	WREG32(data, ficadl_val);
++
++	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
++	WREG32(data, ficadh_val);
++
++	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
++}
++
++/*
++ * df_v3_6_perfmon_rreg - read perfmon lo and hi
++ *
++ * required to be atomic.  no mmio method provided so subsequent reads for lo
++ * and hi require to preserve df finite state machine
++ */
++static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev,
++			    uint32_t lo_addr, uint32_t *lo_val,
++			    uint32_t hi_addr, uint32_t *hi_val)
++{
++	unsigned long flags, address, data;
++
++	address = adev->nbio_funcs->get_pcie_index_offset(adev);
++	data = adev->nbio_funcs->get_pcie_data_offset(adev);
++
++	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
++	WREG32(address, lo_addr);
++	*lo_val = RREG32(data);
++	WREG32(address, hi_addr);
++	*hi_val = RREG32(data);
++	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
++}
++
++/*
++ * df_v3_6_perfmon_wreg - write to perfmon lo and hi
++ *
++ * required to be atomic.  no mmio method provided so subsequent reads after
++ * data writes cannot occur to preserve data fabrics finite state machine.
++ */
++static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr,
++			    uint32_t lo_val, uint32_t hi_addr, uint32_t hi_val)
++{
++	unsigned long flags, address, data;
++
++	address = adev->nbio_funcs->get_pcie_index_offset(adev);
++	data = adev->nbio_funcs->get_pcie_data_offset(adev);
++
++	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
++	WREG32(address, lo_addr);
++	WREG32(data, lo_val);
++	WREG32(address, hi_addr);
++	WREG32(data, hi_val);
++	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
++}
++
+ /* get the number of df counters available */
+ static ssize_t df_v3_6_get_df_cntr_avail(struct device *dev,
+ 		struct device_attribute *attr,
+@@ -268,6 +358,10 @@ static int df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev,
+ 					  uint32_t *lo_val,
+ 					  uint32_t *hi_val)
+ {
++
++	uint32_t eventsel, instance, unitmask;
++	uint32_t instance_10, instance_5432, instance_76;
++
+ 	df_v3_6_pmc_get_addr(adev, config, 1, lo_base_addr, hi_base_addr);
+ 
+ 	if ((*lo_base_addr == 0) || (*hi_base_addr == 0)) {
+@@ -276,40 +370,33 @@ static int df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev,
+ 		return -ENXIO;
+ 	}
+ 
+-	if (lo_val && hi_val) {
+-		uint32_t eventsel, instance, unitmask;
+-		uint32_t instance_10, instance_5432, instance_76;
++	eventsel = DF_V3_6_GET_EVENT(config) & 0x3f;
++	unitmask = DF_V3_6_GET_UNITMASK(config) & 0xf;
++	instance = DF_V3_6_GET_INSTANCE(config);
+ 
+-		eventsel = DF_V3_6_GET_EVENT(config) & 0x3f;
+-		unitmask = DF_V3_6_GET_UNITMASK(config) & 0xf;
+-		instance = DF_V3_6_GET_INSTANCE(config);
++	instance_10 = instance & 0x3;
++	instance_5432 = (instance >> 2) & 0xf;
++	instance_76 = (instance >> 6) & 0x3;
+ 
+-		instance_10 = instance & 0x3;
+-		instance_5432 = (instance >> 2) & 0xf;
+-		instance_76 = (instance >> 6) & 0x3;
++	*lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel | (1 << 22);
++	*hi_val = (instance_76 << 29) | instance_5432;
+ 
+-		*lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel;
+-		*hi_val = (instance_76 << 29) | instance_5432;
+-	}
++	DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
++		config, *lo_base_addr, *hi_base_addr, *lo_val, *hi_val);
+ 
+ 	return 0;
+ }
+ 
+-/* assign df performance counters for read */
+-static int df_v3_6_pmc_assign_cntr(struct amdgpu_device *adev,
+-				   uint64_t config,
+-				   int *is_assigned)
++/* add df performance counters for read */
++static int df_v3_6_pmc_add_cntr(struct amdgpu_device *adev,
++				   uint64_t config)
+ {
+ 	int i, target_cntr;
+ 
+-	*is_assigned = 0;
+-
+ 	target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
+ 
+-	if (target_cntr >= 0) {
+-		*is_assigned = 1;
++	if (target_cntr >= 0)
+ 		return 0;
+-	}
+ 
+ 	for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
+ 		if (adev->df_perfmon_config_assign_mask[i] == 0U) {
+@@ -344,45 +431,13 @@ static void df_v3_6_reset_perfmon_cntr(struct amdgpu_device *adev,
+ 	if ((lo_base_addr == 0) || (hi_base_addr == 0))
+ 		return;
+ 
+-	WREG32_PCIE(lo_base_addr, 0UL);
+-	WREG32_PCIE(hi_base_addr, 0UL);
+-}
+-
+-
+-static int df_v3_6_add_perfmon_cntr(struct amdgpu_device *adev,
+-				      uint64_t config)
+-{
+-	uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
+-	int ret, is_assigned;
+-
+-	ret = df_v3_6_pmc_assign_cntr(adev, config, &is_assigned);
+-
+-	if (ret || is_assigned)
+-		return ret;
+-
+-	ret = df_v3_6_pmc_get_ctrl_settings(adev,
+-			config,
+-			&lo_base_addr,
+-			&hi_base_addr,
+-			&lo_val,
+-			&hi_val);
+-
+-	if (ret)
+-		return ret;
+-
+-	DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
+-			config, lo_base_addr, hi_base_addr, lo_val, hi_val);
+-
+-	WREG32_PCIE(lo_base_addr, lo_val);
+-	WREG32_PCIE(hi_base_addr, hi_val);
+-
+-	return ret;
++	df_v3_6_perfmon_wreg(adev, lo_base_addr, 0, hi_base_addr, 0);
+ }
+ 
+ static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
+ 			     int is_enable)
+ {
+-	uint32_t lo_base_addr, hi_base_addr, lo_val;
++	uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
+ 	int ret = 0;
+ 
+ 	switch (adev->asic_type) {
+@@ -391,24 +446,20 @@ static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
+ 		df_v3_6_reset_perfmon_cntr(adev, config);
+ 
+ 		if (is_enable) {
+-			ret = df_v3_6_add_perfmon_cntr(adev, config);
++			ret = df_v3_6_pmc_add_cntr(adev, config);
+ 		} else {
+ 			ret = df_v3_6_pmc_get_ctrl_settings(adev,
+ 					config,
+ 					&lo_base_addr,
+ 					&hi_base_addr,
+-					NULL,
+-					NULL);
++					&lo_val,
++					&hi_val);
+ 
+ 			if (ret)
+ 				return ret;
+ 
+-			lo_val = RREG32_PCIE(lo_base_addr);
+-
+-			DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x",
+-				config, lo_base_addr, hi_base_addr, lo_val);
+-
+-			WREG32_PCIE(lo_base_addr, lo_val | (1ULL << 22));
++			df_v3_6_perfmon_wreg(adev, lo_base_addr, lo_val,
++					hi_base_addr, hi_val);
+ 		}
+ 
+ 		break;
+@@ -422,7 +473,7 @@ static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
+ static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,
+ 			    int is_disable)
+ {
+-	uint32_t lo_base_addr, hi_base_addr, lo_val;
++	uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
+ 	int ret = 0;
+ 
+ 	switch (adev->asic_type) {
+@@ -432,18 +483,13 @@ static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,
+ 			config,
+ 			&lo_base_addr,
+ 			&hi_base_addr,
+-			NULL,
+-			NULL);
++			&lo_val,
++			&hi_val);
+ 
+ 		if (ret)
+ 			return ret;
+ 
+-		lo_val = RREG32_PCIE(lo_base_addr);
+-
+-		DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x",
+-				config, lo_base_addr, hi_base_addr, lo_val);
+-
+-		WREG32_PCIE(lo_base_addr, lo_val & ~(1ULL << 22));
++		df_v3_6_perfmon_wreg(adev, lo_base_addr, 0, hi_base_addr, 0);
+ 
+ 		if (is_disable)
+ 			df_v3_6_pmc_release_cntr(adev, config);
+@@ -472,8 +518,8 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
+ 		if ((lo_base_addr == 0) || (hi_base_addr == 0))
+ 			return;
+ 
+-		lo_val = RREG32_PCIE(lo_base_addr);
+-		hi_val = RREG32_PCIE(hi_base_addr);
++		df_v3_6_perfmon_rreg(adev, lo_base_addr, &lo_val,
++				hi_base_addr, &hi_val);
+ 
+ 		*count  = ((hi_val | 0ULL) << 32) | (lo_val | 0ULL);
+ 
+@@ -481,7 +527,7 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
+ 			*count = 0;
+ 
+ 		DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
+-			config, lo_base_addr, hi_base_addr, lo_val, hi_val);
++			 config, lo_base_addr, hi_base_addr, lo_val, hi_val);
+ 
+ 		break;
+ 
+@@ -500,5 +546,7 @@ const struct amdgpu_df_funcs df_v3_6_funcs = {
+ 	.get_clockgating_state = df_v3_6_get_clockgating_state,
+ 	.pmc_start = df_v3_6_pmc_start,
+ 	.pmc_stop = df_v3_6_pmc_stop,
+-	.pmc_get_count = df_v3_6_pmc_get_count
++	.pmc_get_count = df_v3_6_pmc_get_count,
++	.get_fica = df_v3_6_get_fica,
++	.set_fica = df_v3_6_set_fica
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3122-drm-amdgpu-Fix-hard-hang-for-S-G-display-BOs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3122-drm-amdgpu-Fix-hard-hang-for-S-G-display-BOs.patch
new file mode 100644
index 00000000..ea5f57d4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3122-drm-amdgpu-Fix-hard-hang-for-S-G-display-BOs.patch
@@ -0,0 +1,69 @@
+From 0896382d968bf924ae82d06e1077384094abb61d Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Mon, 15 Jul 2019 18:04:08 -0400
+Subject: [PATCH 3122/4256] drm/amdgpu: Fix hard hang for S/G display BOs.
+
+HW requires for caching to be unset for scanout BO
+mappings when the BO placement is in GTT memory.
+Usually the flag to unset is passed from user mode
+but for FB mode this was missing.
+
+v2:
+Keep all BO placement logic in amdgpu_display_supported_domains
+
+Suggested-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Tested-by: Shirish S <shirish.s@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  | 7 +++----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 ++-
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+index 5cbde74b97dd..ce594ef5af4d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+@@ -139,14 +139,14 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
+ 	mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
+ 						  fb_tiled);
+ 	domain = amdgpu_display_supported_domains(adev);
+-
+ 	height = ALIGN(mode_cmd->height, 8);
+ 	size = mode_cmd->pitches[0] * height;
+ 	aligned_size = ALIGN(size, PAGE_SIZE);
+ 	ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain,
+ 				       AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+-				       AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+-				       AMDGPU_GEM_CREATE_VRAM_CLEARED,
++				       AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS     |
++				       AMDGPU_GEM_CREATE_VRAM_CLEARED 	     |
++				       AMDGPU_GEM_CREATE_CPU_GTT_USWC,
+ 				       ttm_bo_type_kernel, NULL, &gobj);
+ 	if (ret) {
+ 		pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
+@@ -168,7 +168,6 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
+ 			dev_err(adev->dev, "FB failed to set tiling flags\n");
+ 	}
+ 
+-
+ 	ret = amdgpu_bo_pin(abo, domain);
+ 	if (ret) {
+ 		amdgpu_bo_unreserve(abo);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+index 1ae59641d23f..1b51194036b5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+@@ -829,7 +829,8 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
+ 	struct amdgpu_device *adev = dev->dev_private;
+ 	struct drm_gem_object *gobj;
+ 	uint32_t handle;
+-	u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
++	u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
++		    AMDGPU_GEM_CREATE_CPU_GTT_USWC;
+ 	u32 domain;
+ 	int r;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3123-drm-amdgpu-Create-helper-to-clear-AMDGPU_GEM_CREATE_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3123-drm-amdgpu-Create-helper-to-clear-AMDGPU_GEM_CREATE_.patch
new file mode 100644
index 00000000..b573e832
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3123-drm-amdgpu-Create-helper-to-clear-AMDGPU_GEM_CREATE_.patch
@@ -0,0 +1,121 @@
+From 434afe927a6eb690c36541da6f90d10fd5179605 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Wed, 24 Jul 2019 10:04:27 -0400
+Subject: [PATCH 3123/4256] drm/amdgpu: Create helper to clear
+ AMDGPU_GEM_CREATE_CPU_GTT_USWC
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Move the logic to clear AMDGPU_GEM_CREATE_CPU_GTT_USWC in
+amdgpu_bo_do_create into standalone helper so it can be reused
+in other functions.
+
+v4:
+Switch to return bool.
+
+v5: Fix typos.
+
+Change-Id: Iff8a1a527813d35bcd4b3ef77350d9397904db95
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Acked-by: Michel Dänzer <michel.daenzer@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 61 +++++++++++++---------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  2 +
+ 2 files changed, 37 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+index 2401d61cb741..495c5d33fc62 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+@@ -434,6 +434,40 @@ static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
+ 	return false;
+ }
+ 
++bool amdgpu_bo_support_uswc(u64 bo_flags)
++{
++
++#ifdef CONFIG_X86_32
++	/* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
++	 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
++	 */
++	return false;
++#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
++	/* Don't try to enable write-combining when it can't work, or things
++	 * may be slow
++	 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
++	 */
++
++#ifndef CONFIG_COMPILE_TEST
++#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
++	 thanks to write-combining
++#endif
++
++	if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
++		DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
++			      "better performance thanks to write-combining\n");
++	return false;
++#else
++	/* For architectures that don't support WC memory,
++	 * mask out the WC flag from the BO
++	 */
++	if (!drm_arch_can_wc_memory())
++		return false;
++
++	return true;
++#endif
++}
++
+ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
+ 			       struct amdgpu_bo_param *bp,
+ 			       struct amdgpu_bo **bo_ptr)
+@@ -487,33 +521,8 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
+ 
+ 	bo->flags = bp->flags;
+ 
+-#ifdef CONFIG_X86_32
+-	/* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
+-	 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
+-	 */
+-	bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
+-#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
+-	/* Don't try to enable write-combining when it can't work, or things
+-	 * may be slow
+-	 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
+-	 */
+-
+-#ifndef CONFIG_COMPILE_TEST
+-#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
+-	 thanks to write-combining
+-#endif
+-
+-	if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
+-		DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
+-			      "better performance thanks to write-combining\n");
+-	bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
+-#else
+-	/* For architectures that don't support WC memory,
+-	 * mask out the WC flag from the BO
+-	 */
+-	if (!drm_arch_can_wc_memory())
++	if (!amdgpu_bo_support_uswc(bo->flags))
+ 		bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
+-#endif
+ 
+ 	bo->tbo.bdev = &adev->mman.bdev;
+ 	if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+index b27271290c33..6658c2399223 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+@@ -312,5 +312,7 @@ void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
+ 					 struct seq_file *m);
+ #endif
+ 
++bool amdgpu_bo_support_uswc(u64 bo_flags);
++
+ 
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3124-drm-amdgpu-Add-check-for-USWC-support-for-amdgpu_dis.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3124-drm-amdgpu-Add-check-for-USWC-support-for-amdgpu_dis.patch
new file mode 100644
index 00000000..2058ca82
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3124-drm-amdgpu-Add-check-for-USWC-support-for-amdgpu_dis.patch
@@ -0,0 +1,42 @@
+From cc71845f9c18fb982846fe21719ebebd6adff312 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Wed, 24 Jul 2019 11:09:03 -0400
+Subject: [PATCH 3124/4256] drm/amdgpu: Add check for USWC support for
+ amdgpu_display_supported_domains
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This verifies we don't add GTT as allowed domnain for APUs when USWC
+is disabled.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Acked-by: Michel Dänzer <michel.daenzer@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+index 36da6372607b..86bb15f83dcc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+@@ -498,8 +498,15 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev)
+ 	uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
+ 
+ #if defined(CONFIG_DRM_AMD_DC)
++	/*
++	 * if amdgpu_bo_validate_uswc returns false it means that USWC mappings
++	 * is not supported for this board. But this mapping is required
++	 * to avoid hang caused by placement of scanout BO in GTT on certain
++	 * APUs. So force the BO placement to VRAM in case this architecture
++	 * will not allow USWC mappings.
++	 */
+ 	if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN &&
+-	    adev->flags & AMD_IS_APU &&
++	    adev->flags & AMD_IS_APU && amdgpu_bo_support_uswc(0) &&
+ 	    amdgpu_device_asic_has_dc_support(adev->asic_type))
+ 		domain |= AMDGPU_GEM_DOMAIN_GTT;
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3125-drm-amd-display-enable-S-G-for-RAVEN-chip.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3125-drm-amd-display-enable-S-G-for-RAVEN-chip.patch
new file mode 100644
index 00000000..209e91e3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3125-drm-amd-display-enable-S-G-for-RAVEN-chip.patch
@@ -0,0 +1,55 @@
+From 8fbff19b7115fed1ffd9a4d2e012b229a9082a55 Mon Sep 17 00:00:00 2001
+From: Shirish S <shirish.s@amd.com>
+Date: Tue, 16 Jul 2019 14:49:48 +0530
+Subject: [PATCH 3125/4256] drm/amd/display: enable S/G for RAVEN chip
+
+enables gpu_vm_support in dm and adds
+AMDGPU_GEM_DOMAIN_GTT as supported domain
+
+v2:
+Move BO placement logic into amdgpu_display_supported_domains
+
+v3:
+Use amdgpu_bo_validate_uswc in amdgpu_display_supported_domains.
+
+v4:
+amdgpu_bo_validate_uswc moved to sepperate patch.
+
+Change-Id: If34300beaa60be2d36170b7b5b096ec644502b20
+Signed-off-by: Shirish S <shirish.s@amd.com>
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c       | 2 +-
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+index 86bb15f83dcc..f1df323f1da5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+@@ -505,7 +505,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev)
+ 	 * APUs. So force the BO placement to VRAM in case this architecture
+ 	 * will not allow USWC mappings.
+ 	 */
+-	if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN &&
++	if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <= CHIP_RAVEN &&
+ 	    adev->flags & AMD_IS_APU && amdgpu_bo_support_uswc(0) &&
+ 	    amdgpu_device_asic_has_dc_support(adev->asic_type))
+ 		domain |= AMDGPU_GEM_DOMAIN_GTT;
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 8d55650cb622..a21d46ecc886 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -686,7 +686,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ 	 */
+ 	if (adev->flags & AMD_IS_APU &&
+ 	    adev->asic_type >= CHIP_CARRIZO &&
+-	    adev->asic_type < CHIP_RAVEN)
++	    adev->asic_type <= CHIP_RAVEN)
+ 		init_data.flags.gpu_vm_support = true;
+ 
+ 	if (amdgpu_dc_feature_mask & DC_FBC_MASK)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3126-drm-amd-powerplay-minor-fixes-around-SW-SMU-power-an.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3126-drm-amd-powerplay-minor-fixes-around-SW-SMU-power-an.patch
new file mode 100644
index 00000000..c284ba4e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3126-drm-amd-powerplay-minor-fixes-around-SW-SMU-power-an.patch
@@ -0,0 +1,162 @@
+From 9bd0a9e97f397623427fc5e449a73e935c76b926 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Wed, 24 Jul 2019 14:06:09 +0800
+Subject: [PATCH 3126/4256] drm/amd/powerplay: minor fixes around SW SMU power
+ and fan setting
+
+Add checking for possible invalid input and null pointer. And
+drop redundant code.
+
+Change-Id: I6ebd6acd944e821fb19af77ed1eaa8c4b1d407ce
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c    | 22 ++++++++++-----------
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 24 +++++++++++------------
+ 2 files changed, 21 insertions(+), 25 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index a68c25203518..d24eb6980ec1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -1613,20 +1613,16 @@ static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
+ 	     (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+ 		return -EINVAL;
+ 
+-	if (is_support_sw_smu(adev)) {
+-		err = kstrtoint(buf, 10, &value);
+-		if (err)
+-			return err;
++	err = kstrtoint(buf, 10, &value);
++	if (err)
++		return err;
+ 
++	if (is_support_sw_smu(adev)) {
+ 		smu_set_fan_control_mode(&adev->smu, value);
+ 	} else {
+ 		if (!adev->powerplay.pp_funcs->set_fan_control_mode)
+ 			return -EINVAL;
+ 
+-		err = kstrtoint(buf, 10, &value);
+-		if (err)
+-			return err;
+-
+ 		amdgpu_dpm_set_fan_control_mode(adev, value);
+ 	}
+ 
+@@ -2046,16 +2042,18 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
+ 		return err;
+ 
+ 	value = value / 1000000; /* convert to Watt */
++
+ 	if (is_support_sw_smu(adev)) {
+-		adev->smu.funcs->set_power_limit(&adev->smu, value);
++		err = smu_set_power_limit(&adev->smu, value);
+ 	} else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
+ 		err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
+-		if (err)
+-			return err;
+ 	} else {
+-		return -EINVAL;
++		err = -EINVAL;
+ 	}
+ 
++	if (err)
++		return err;
++
+ 	return count;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 735802bb07b9..cee480b39ffc 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1097,6 +1097,8 @@ static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
+ 		max_power_limit *= (100 + smu->smu_table.TDPODLimit);
+ 		max_power_limit /= 100;
+ 	}
++	if (n > max_power_limit)
++		return -EINVAL;
+ 
+ 	if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
+ 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
+@@ -1418,17 +1420,17 @@ smu_v11_0_get_fan_control_mode(struct smu_context *smu)
+ }
+ 
+ static int
+-smu_v11_0_smc_fan_control(struct smu_context *smu, bool start)
++smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
+ {
+ 	int ret = 0;
+ 
+ 	if (smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
+ 		return 0;
+ 
+-	ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start);
++	ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
+ 	if (ret)
+ 		pr_err("[%s]%s smc FAN CONTROL feature failed!",
+-		       __func__, (start ? "Start" : "Stop"));
++		       __func__, (auto_fan_control ? "Start" : "Stop"));
+ 
+ 	return ret;
+ }
+@@ -1452,16 +1454,15 @@ static int
+ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+-	uint32_t duty100;
+-	uint32_t duty;
++	uint32_t duty100, duty;
+ 	uint64_t tmp64;
+-	bool stop = 0;
+ 
+ 	if (speed > 100)
+ 		speed = 100;
+ 
+-	if (smu_v11_0_smc_fan_control(smu, stop))
++	if (smu_v11_0_auto_fan_control(smu, 0))
+ 		return -EINVAL;
++
+ 	duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
+ 				CG_FDO_CTRL1, FMAX_DUTY100);
+ 	if (!duty100)
+@@ -1483,18 +1484,16 @@ smu_v11_0_set_fan_control_mode(struct smu_context *smu,
+ 			       uint32_t mode)
+ {
+ 	int ret = 0;
+-	bool start = 1;
+-	bool stop  = 0;
+ 
+ 	switch (mode) {
+ 	case AMD_FAN_CTRL_NONE:
+ 		ret = smu_v11_0_set_fan_speed_percent(smu, 100);
+ 		break;
+ 	case AMD_FAN_CTRL_MANUAL:
+-		ret = smu_v11_0_smc_fan_control(smu, stop);
++		ret = smu_v11_0_auto_fan_control(smu, 0);
+ 		break;
+ 	case AMD_FAN_CTRL_AUTO:
+-		ret = smu_v11_0_smc_fan_control(smu, start);
++		ret = smu_v11_0_auto_fan_control(smu, 1);
+ 		break;
+ 	default:
+ 		break;
+@@ -1514,13 +1513,12 @@ static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
+ 	struct amdgpu_device *adev = smu->adev;
+ 	int ret;
+ 	uint32_t tach_period, crystal_clock_freq;
+-	bool stop = 0;
+ 
+ 	if (!speed)
+ 		return -EINVAL;
+ 
+ 	mutex_lock(&(smu->mutex));
+-	ret = smu_v11_0_smc_fan_control(smu, stop);
++	ret = smu_v11_0_auto_fan_control(smu, 0);
+ 	if (ret)
+ 		goto set_fan_speed_rpm_failed;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3127-drm-amd-powerplay-fix-null-pointer-dereference-aroun.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3127-drm-amd-powerplay-fix-null-pointer-dereference-aroun.patch
new file mode 100644
index 00000000..96ee9417
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3127-drm-amd-powerplay-fix-null-pointer-dereference-aroun.patch
@@ -0,0 +1,72 @@
+From 296307cdf9ba0f228c07cf08156cd7958ae9d4dd Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 25 Jul 2019 12:10:34 +0800
+Subject: [PATCH 3127/4256] drm/amd/powerplay: fix null pointer dereference
+ around dpm state relates
+
+DPM state relates are not supported on the new SW SMU ASICs. But still
+it's not OK to trigger null pointer dereference on accessing them.
+
+Change-Id: I368d108fbea438ed5d9e3b849d006ddd5308052b
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c     | 18 +++++++++++++-----
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c |  3 ++-
+ 2 files changed, 15 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index d24eb6980ec1..d9d1a7dd6514 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -156,12 +156,16 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev,
+ 	struct amdgpu_device *adev = ddev->dev_private;
+ 	enum amd_pm_state_type pm;
+ 
+-	if (is_support_sw_smu(adev) && adev->smu.ppt_funcs->get_current_power_state)
+-		pm = amdgpu_smu_get_current_power_state(adev);
+-	else if (adev->powerplay.pp_funcs->get_current_power_state)
++	if (is_support_sw_smu(adev)) {
++		if (adev->smu.ppt_funcs->get_current_power_state)
++			pm = amdgpu_smu_get_current_power_state(adev);
++		else
++			pm = adev->pm.dpm.user_state;
++	} else if (adev->powerplay.pp_funcs->get_current_power_state) {
+ 		pm = amdgpu_dpm_get_current_power_state(adev);
+-	else
++	} else {
+ 		pm = adev->pm.dpm.user_state;
++	}
+ 
+ 	return snprintf(buf, PAGE_SIZE, "%s\n",
+ 			(pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
+@@ -188,7 +192,11 @@ static ssize_t amdgpu_set_dpm_state(struct device *dev,
+ 		goto fail;
+ 	}
+ 
+-	if (adev->powerplay.pp_funcs->dispatch_tasks) {
++	if (is_support_sw_smu(adev)) {
++		mutex_lock(&adev->pm.mutex);
++		adev->pm.dpm.user_state = state;
++		mutex_unlock(&adev->pm.mutex);
++	} else if (adev->powerplay.pp_funcs->dispatch_tasks) {
+ 		amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
+ 	} else {
+ 		mutex_lock(&adev->pm.mutex);
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index abfb19ebf929..c22b4d5673fa 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -305,7 +305,8 @@ int smu_get_power_num_states(struct smu_context *smu,
+ 
+ 	/* not support power state */
+ 	memset(state_info, 0, sizeof(struct pp_states_info));
+-	state_info->nums = 0;
++	state_info->nums = 1;
++	state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
+ 
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3128-drm-amd-powerplay-enable-SW-SMU-reset-functionality.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3128-drm-amd-powerplay-enable-SW-SMU-reset-functionality.patch
new file mode 100644
index 00000000..6399c71f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3128-drm-amd-powerplay-enable-SW-SMU-reset-functionality.patch
@@ -0,0 +1,67 @@
+From 632af13b7f5ddb00c69ed0cd0daa3af5b7c719c4 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 25 Jul 2019 10:12:42 +0800
+Subject: [PATCH 3128/4256] drm/amd/powerplay: enable SW SMU reset
+ functionality
+
+Move SMU irq handler register to sw_init as that's totally
+software related. Otherwise, it will prevent SMU reset working.
+
+Change-Id: Ibd3e48ae9a90ab57f42b3f2ddbb736deeebc8715
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 16 +++++++++-------
+ 1 file changed, 9 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index c22b4d5673fa..b78eeeab87da 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -743,6 +743,12 @@ static int smu_sw_init(void *handle)
+ 		return ret;
+ 	}
+ 
++	ret = smu_register_irq_handler(smu);
++	if (ret) {
++		pr_err("Failed to register smc irq handler!\n");
++		return ret;
++	}
++
+ 	return 0;
+ }
+ 
+@@ -752,6 +758,9 @@ static int smu_sw_fini(void *handle)
+ 	struct smu_context *smu = &adev->smu;
+ 	int ret;
+ 
++	kfree(smu->irq_source);
++	smu->irq_source = NULL;
++
+ 	ret = smu_smc_table_sw_fini(smu);
+ 	if (ret) {
+ 		pr_err("Failed to sw fini smc table!\n");
+@@ -1111,10 +1120,6 @@ static int smu_hw_init(void *handle)
+ 	if (ret)
+ 		goto failed;
+ 
+-	ret = smu_register_irq_handler(smu);
+-	if (ret)
+-		goto failed;
+-
+ 	if (!smu->pm_enabled)
+ 		adev->pm.dpm_enabled = false;
+ 	else
+@@ -1144,9 +1149,6 @@ static int smu_hw_fini(void *handle)
+ 	kfree(table_context->overdrive_table);
+ 	table_context->overdrive_table = NULL;
+ 
+-	kfree(smu->irq_source);
+-	smu->irq_source = NULL;
+-
+ 	ret = smu_fini_fb_allocations(smu);
+ 	if (ret)
+ 		return ret;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3129-drm-amdgpu-add-an-asic-callback-to-determine-the-res.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3129-drm-amdgpu-add-an-asic-callback-to-determine-the-res.patch
new file mode 100644
index 00000000..ccaffd54
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3129-drm-amdgpu-add-an-asic-callback-to-determine-the-res.patch
@@ -0,0 +1,53 @@
+From c160c3bbea6beae78244a8b75e57b9350a04970b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 23 Jul 2019 23:27:21 -0500
+Subject: [PATCH 3129/4256] drm/amdgpu: add an asic callback to determine the
+ reset method
+
+Sometimes the driver may have to behave differently depending
+on the method we are using to reset the GPU.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index fcb92ec6b73d..ba666a4afdfe 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -538,6 +538,14 @@ struct amdgpu_allowed_register_entry {
+ 	bool grbm_indexed;
+ };
+ 
++enum amd_reset_method {
++	AMD_RESET_METHOD_LEGACY = 0,
++	AMD_RESET_METHOD_MODE0,
++	AMD_RESET_METHOD_MODE1,
++	AMD_RESET_METHOD_MODE2,
++	AMD_RESET_METHOD_BACO
++};
++
+ /*
+  * ASIC specific functions.
+  */
+@@ -549,6 +557,7 @@ struct amdgpu_asic_funcs {
+ 			     u32 sh_num, u32 reg_offset, u32 *value);
+ 	void (*set_vga_state)(struct amdgpu_device *adev, bool state);
+ 	int (*reset)(struct amdgpu_device *adev);
++	enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
+ 	/* get the reference clock */
+ 	u32 (*get_xclk)(struct amdgpu_device *adev);
+ 	/* MM block clocks */
+@@ -1149,6 +1158,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
+  */
+ #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
+ #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
++#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
+ #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
+ #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
+ #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3130-drm-amdgpu-add-reset_method-asic-callback-for-si.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3130-drm-amdgpu-add-reset_method-asic-callback-for-si.patch
new file mode 100644
index 00000000..d8ee9b92
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3130-drm-amdgpu-add-reset_method-asic-callback-for-si.patch
@@ -0,0 +1,41 @@
+From 085ce4756361bef938d04f50265a3dc15a043fe5 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 23 Jul 2019 23:44:54 -0500
+Subject: [PATCH 3130/4256] drm/amdgpu: add reset_method asic callback for si
+
+SI always uses the legacy pci based reset.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/si.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
+index 4b1e0c16ac41..904361451650 100644
+--- a/drivers/gpu/drm/amd/amdgpu/si.c
++++ b/drivers/gpu/drm/amd/amdgpu/si.c
+@@ -1185,6 +1185,12 @@ static int si_asic_reset(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
++static enum amd_reset_method
++si_asic_reset_method(struct amdgpu_device *adev)
++{
++	return AMD_RESET_METHOD_LEGACY;
++}
++
+ static u32 si_get_config_memsize(struct amdgpu_device *adev)
+ {
+ 	return RREG32(mmCONFIG_MEMSIZE);
+@@ -1393,6 +1399,7 @@ static const struct amdgpu_asic_funcs si_asic_funcs =
+ 	.read_bios_from_rom = &si_read_bios_from_rom,
+ 	.read_register = &si_read_register,
+ 	.reset = &si_asic_reset,
++	.reset_method = &si_asic_reset_method,
+ 	.set_vga_state = &si_vga_set_state,
+ 	.get_xclk = &si_get_xclk,
+ 	.set_uvd_clocks = &si_set_uvd_clocks,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3131-drm-amdgpu-add-reset_method-asic-callback-for-cik.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3131-drm-amdgpu-add-reset_method-asic-callback-for-cik.patch
new file mode 100644
index 00000000..e24e4a48
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3131-drm-amdgpu-add-reset_method-asic-callback-for-cik.patch
@@ -0,0 +1,41 @@
+From 36a792fb993dcf08eb4cf2774284a43eb4df5e16 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 23 Jul 2019 23:45:39 -0500
+Subject: [PATCH 3131/4256] drm/amdgpu: add reset_method asic callback for cik
+
+CIK always uses the legacy pci based reset.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/cik.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
+index 3a4f20766a39..7b63d7a8298a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik.c
+@@ -1290,6 +1290,12 @@ static int cik_asic_reset(struct amdgpu_device *adev)
+ 	return r;
+ }
+ 
++static enum amd_reset_method
++cik_asic_reset_method(struct amdgpu_device *adev)
++{
++	return AMD_RESET_METHOD_LEGACY;
++}
++
+ static u32 cik_get_config_memsize(struct amdgpu_device *adev)
+ {
+ 	return RREG32(mmCONFIG_MEMSIZE);
+@@ -1822,6 +1828,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs =
+ 	.read_bios_from_rom = &cik_read_bios_from_rom,
+ 	.read_register = &cik_read_register,
+ 	.reset = &cik_asic_reset,
++	.reset_method = &cik_asic_reset_method,
+ 	.set_vga_state = &cik_vga_set_state,
+ 	.get_xclk = &cik_get_xclk,
+ 	.set_uvd_clocks = &cik_set_uvd_clocks,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3132-drm-amdgpu-add-reset_method-asic-callback-for-vi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3132-drm-amdgpu-add-reset_method-asic-callback-for-vi.patch
new file mode 100644
index 00000000..65768fb8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3132-drm-amdgpu-add-reset_method-asic-callback-for-vi.patch
@@ -0,0 +1,41 @@
+From 54ceb3e2c29a2646a28d50d9b2b6838255447bec Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 23 Jul 2019 23:46:12 -0500
+Subject: [PATCH 3132/4256] drm/amdgpu: add reset_method asic callback for vi
+
+VI always uses the legacy pci based reset.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vi.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
+index fffae4c2973b..56c882b3ea3c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vi.c
++++ b/drivers/gpu/drm/amd/amdgpu/vi.c
+@@ -709,6 +709,12 @@ static int vi_asic_reset(struct amdgpu_device *adev)
+ 	return r;
+ }
+ 
++static enum amd_reset_method
++vi_asic_reset_method(struct amdgpu_device *adev)
++{
++	return AMD_RESET_METHOD_LEGACY;
++}
++
+ static u32 vi_get_config_memsize(struct amdgpu_device *adev)
+ {
+ 	return RREG32(mmCONFIG_MEMSIZE);
+@@ -1021,6 +1027,7 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =
+ 	.read_bios_from_rom = &vi_read_bios_from_rom,
+ 	.read_register = &vi_read_register,
+ 	.reset = &vi_asic_reset,
++	.reset_method = &vi_asic_reset_method,
+ 	.set_vga_state = &vi_vga_set_state,
+ 	.get_xclk = &vi_get_xclk,
+ 	.set_uvd_clocks = &vi_set_uvd_clocks,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3133-drm-amdgpu-add-reset_method-asic-callback-for-soc15.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3133-drm-amdgpu-add-reset_method-asic-callback-for-soc15.patch
new file mode 100644
index 00000000..732a2d16
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3133-drm-amdgpu-add-reset_method-asic-callback-for-soc15.patch
@@ -0,0 +1,64 @@
+From 17ee4a1e296d912c82b43ede367c7b7091699e9e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 23 Jul 2019 23:47:06 -0500
+Subject: [PATCH 3133/4256] drm/amdgpu: add reset_method asic callback for
+ soc15
+
+APUs only support mode2 reset.  dGPUs use either mode1 or
+baco depending on various conditions.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 17 +++++++++++++++--
+ 1 file changed, 15 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index f67ecf814c8c..4405b983dd09 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -464,12 +464,14 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
+-static int soc15_asic_reset(struct amdgpu_device *adev)
++static enum amd_reset_method
++soc15_asic_reset_method(struct amdgpu_device *adev)
+ {
+-	int ret;
+ 	bool baco_reset;
+ 
+ 	switch (adev->asic_type) {
++	case CHIP_RAVEN:
++		return AMD_RESET_METHOD_MODE2;
+ 	case CHIP_VEGA10:
+ 	case CHIP_VEGA12:
+ 		soc15_asic_get_baco_capability(adev, &baco_reset);
+@@ -493,6 +495,16 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
+ 	}
+ 
+ 	if (baco_reset)
++		return AMD_RESET_METHOD_BACO;
++	else
++		return AMD_RESET_METHOD_MODE1;
++}
++
++static int soc15_asic_reset(struct amdgpu_device *adev)
++{
++	int ret;
++
++	if (soc15_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
+ 		ret = soc15_asic_baco_reset(adev);
+ 	else
+ 		ret = soc15_asic_mode1_reset(adev);
+@@ -806,6 +818,7 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs =
+ 	.read_bios_from_rom = &soc15_read_bios_from_rom,
+ 	.read_register = &soc15_read_register,
+ 	.reset = &soc15_asic_reset,
++	.reset_method = &soc15_asic_reset_method,
+ 	.set_vga_state = &soc15_vga_set_state,
+ 	.get_xclk = &soc15_get_xclk,
+ 	.set_uvd_clocks = &soc15_set_uvd_clocks,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3134-drm-amdgpu-add-reset_method-asic-callback-for-navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3134-drm-amdgpu-add-reset_method-asic-callback-for-navi.patch
new file mode 100644
index 00000000..168e4e7b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3134-drm-amdgpu-add-reset_method-asic-callback-for-navi.patch
@@ -0,0 +1,57 @@
+From 548f69228fd63749d71e15301f697fca3c969a3e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 23 Jul 2019 23:48:21 -0500
+Subject: [PATCH 3134/4256] drm/amdgpu: add reset_method asic callback for navi
+
+Navi uses either mode1 or baco depending on various
+conditions.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 15 ++++++++++++++-
+ 1 file changed, 14 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 6c59b64b9bb1..bf4cbcdeef78 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -289,6 +289,18 @@ static int nv_asic_mode1_reset(struct amdgpu_device *adev)
+ 
+ 	return ret;
+ }
++
++static enum amd_reset_method
++nv_asic_reset_method(struct amdgpu_device *adev)
++{
++	struct smu_context *smu = &adev->smu;
++
++	if (smu_baco_is_support(smu))
++		return AMD_RESET_METHOD_BACO;
++	else
++		return AMD_RESET_METHOD_MODE1;
++}
++
+ static int nv_asic_reset(struct amdgpu_device *adev)
+ {
+ 
+@@ -303,7 +315,7 @@ static int nv_asic_reset(struct amdgpu_device *adev)
+ 	int ret = 0;
+ 	struct smu_context *smu = &adev->smu;
+ 
+-	if (smu_baco_is_support(smu))
++	if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
+ 		ret = smu_baco_reset(smu);
+ 	else
+ 		ret = nv_asic_mode1_reset(adev);
+@@ -500,6 +512,7 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
+ 	.read_bios_from_rom = &nv_read_bios_from_rom,
+ 	.read_register = &nv_read_register,
+ 	.reset = &nv_asic_reset,
++	.reset_method = &nv_asic_reset_method,
+ 	.set_vga_state = &nv_vga_set_state,
+ 	.get_xclk = &nv_get_xclk,
+ 	.set_uvd_clocks = &nv_set_uvd_clocks,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3135-drm-amdgpu-powerplay-add-a-new-interface-to-set-the-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3135-drm-amdgpu-powerplay-add-a-new-interface-to-set-the-.patch
new file mode 100644
index 00000000..89392eb7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3135-drm-amdgpu-powerplay-add-a-new-interface-to-set-the-.patch
@@ -0,0 +1,93 @@
+From c056e7c76f4949acc006db8929de369ae487b249 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 25 Jul 2019 09:41:53 -0500
+Subject: [PATCH 3135/4256] drm/amdgpu/powerplay: add a new interface to set
+ the mp1 state
+
+This is required for certain cases such as various GPU resets
+(mode1, mode2), BACO, shutdown, unload, etc. to put the SMU into
+the appropriate state for when the hw is re-initialized.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/kgd_pp_interface.h |  8 ++++++++
+ drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 16 ++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/inc/hwmgr.h      |  1 +
+ 3 files changed, 25 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+index 9733bbf9bc72..95edc3d3a9c4 100644
+--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
++++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+@@ -171,6 +171,13 @@ enum PP_HWMON_TEMP {
+ 	PP_TEMP_MAX
+ };
+ 
++enum pp_mp1_state {
++	PP_MP1_STATE_NONE,
++	PP_MP1_STATE_SHUTDOWN,
++	PP_MP1_STATE_UNLOAD,
++	PP_MP1_STATE_RESET,
++};
++
+ #define PP_GROUP_MASK        0xF0000000
+ #define PP_GROUP_SHIFT       28
+ 
+@@ -266,6 +273,7 @@ struct amd_pm_funcs {
+ 	int (*get_power_profile_mode)(void *handle, char *buf);
+ 	int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
+ 	int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
++	int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
+ /* export to DC */
+ 	u32 (*get_sclk)(void *handle, bool low);
+ 	u32 (*get_mclk)(void *handle, bool low);
+diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+index bea1587d352d..88a2ef75b7e1 100644
+--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+@@ -924,6 +924,21 @@ static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint3
+ 	return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size);
+ }
+ 
++static int pp_dpm_set_mp1_state(void *handle, enum pp_mp1_state mp1_state)
++{
++	struct pp_hwmgr *hwmgr = handle;
++
++	if (!hwmgr || !hwmgr->pm_en)
++		return -EINVAL;
++
++	if (hwmgr->hwmgr_func->set_mp1_state == NULL) {
++		pr_info_ratelimited("%s was not implemented.\n", __func__);
++		return -EINVAL;
++	}
++
++	return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state);
++}
++
+ static int pp_dpm_switch_power_profile(void *handle,
+ 		enum PP_SMC_POWER_PROFILE type, bool en)
+ {
+@@ -1525,6 +1540,7 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
+ 	.get_power_profile_mode = pp_get_power_profile_mode,
+ 	.set_power_profile_mode = pp_set_power_profile_mode,
+ 	.odn_edit_dpm_table = pp_odn_edit_dpm_table,
++	.set_mp1_state = pp_dpm_set_mp1_state,
+ 	.set_power_limit = pp_set_power_limit,
+ 	.get_power_limit = pp_get_power_limit,
+ /* export to DC */
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+index c5989cb38b1b..07fd64aad2ae 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+@@ -344,6 +344,7 @@ struct pp_hwmgr_func {
+ 	int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
+ 	int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
+ 	int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
++	int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
+ };
+ 
+ struct pp_table_func {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3136-drm-amdgpu-powerplay-add-set_mp1_state-for-vega20.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3136-drm-amdgpu-powerplay-add-set_mp1_state-for-vega20.patch
new file mode 100644
index 00000000..18168780
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3136-drm-amdgpu-powerplay-add-set_mp1_state-for-vega20.patch
@@ -0,0 +1,64 @@
+From b0689f90d76a4277628b7bf5c57b9ffe775897b8 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 25 Jul 2019 10:43:28 -0500
+Subject: [PATCH 3136/4256] drm/amdgpu/powerplay: add set_mp1_state for vega20
+
+This sets the SMU into the proper state for various
+operations (shutdown, unload, GPU reset, etc.).
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c    | 29 +++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+index f27c6fbb192e..0516c294b377 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+@@ -3063,6 +3063,34 @@ static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
+ 	return 0;
+ }
+ 
++static int vega20_set_mp1_state(struct pp_hwmgr *hwmgr,
++				enum pp_mp1_state mp1_state)
++{
++	uint16_t msg;
++	int ret;
++
++	switch (mp1_state) {
++	case PP_MP1_STATE_SHUTDOWN:
++		msg = PPSMC_MSG_PrepareMp1ForShutdown;
++		break;
++	case PP_MP1_STATE_UNLOAD:
++		msg = PPSMC_MSG_PrepareMp1ForUnload;
++		break;
++	case PP_MP1_STATE_RESET:
++		msg = PPSMC_MSG_PrepareMp1ForReset;
++		break;
++	case PP_MP1_STATE_NONE:
++	default:
++		return 0;
++	}
++
++	PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg)) == 0,
++			    "[PrepareMp1] Failed!",
++			    return ret);
++
++	return 0;
++}
++
+ static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
+ {
+ 	static const char *ppfeature_name[] = {
+@@ -4123,6 +4151,7 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
+ 	.get_asic_baco_capability = vega20_baco_get_capability,
+ 	.get_asic_baco_state = vega20_baco_get_state,
+ 	.set_asic_baco_state = vega20_baco_set_state,
++	.set_mp1_state = vega20_set_mp1_state,
+ };
+ 
+ int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3137-drm-amdgpu-powerplay-add-set_mp1_state-for-vega10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3137-drm-amdgpu-powerplay-add-set_mp1_state-for-vega10.patch
new file mode 100644
index 00000000..364f5a58
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3137-drm-amdgpu-powerplay-add-set_mp1_state-for-vega10.patch
@@ -0,0 +1,61 @@
+From 271573b4bf0403ee536de31223cbc7932c5fdc72 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 25 Jul 2019 10:55:25 -0500
+Subject: [PATCH 3137/4256] drm/amdgpu/powerplay: add set_mp1_state for vega10
+
+This sets the SMU into the proper state for various
+operations (shutdown, unload, GPU reset, etc.).
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c    | 26 ++++++++++++++++++-
+ 1 file changed, 25 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+index 4f9dd879db41..3ac4745708cf 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+@@ -5218,6 +5218,30 @@ static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
+ 	return 0;
+ }
+ 
++static int vega10_set_mp1_state(struct pp_hwmgr *hwmgr,
++				enum pp_mp1_state mp1_state)
++{
++	uint16_t msg;
++	int ret;
++
++	switch (mp1_state) {
++	case PP_MP1_STATE_UNLOAD:
++		msg = PPSMC_MSG_PrepareMp1ForUnload;
++		break;
++	case PP_MP1_STATE_SHUTDOWN:
++	case PP_MP1_STATE_RESET:
++	case PP_MP1_STATE_NONE:
++	default:
++		return 0;
++	}
++
++	PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg)) == 0,
++			    "[PrepareMp1] Failed!",
++			    return ret);
++
++	return 0;
++}
++
+ static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
+ 				PHM_PerformanceLevelDesignation designation, uint32_t index,
+ 				PHM_PerformanceLevel *level)
+@@ -5306,7 +5330,7 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
+ 	.set_asic_baco_state = vega10_baco_set_state,
+         .get_ppfeature_status = vega10_get_ppfeature_status,
+         .set_ppfeature_status = vega10_set_ppfeature_status,
+-
++	.set_mp1_state = vega10_set_mp1_state,
+ };
+ 
+ int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3138-drm-amdgpu-powerplay-add-set_mp1_state-for-vega12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3138-drm-amdgpu-powerplay-add-set_mp1_state-for-vega12.patch
new file mode 100644
index 00000000..cca76f39
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3138-drm-amdgpu-powerplay-add-set_mp1_state-for-vega12.patch
@@ -0,0 +1,61 @@
+From b1eaba3c58092d48a275eb2d93aaa36cc2fb8c5e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 25 Jul 2019 10:55:57 -0500
+Subject: [PATCH 3138/4256] drm/amdgpu/powerplay: add set_mp1_state for vega12
+
+This sets the SMU into the proper state for various
+operations (shutdown, unload, GPU reset, etc.).
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c    | 26 ++++++++++++++++++-
+ 1 file changed, 25 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+index efb6d3762feb..7af9ad450ac4 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+@@ -2639,6 +2639,30 @@ static int vega12_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_
+ 	return 0;
+ }
+ 
++static int vega12_set_mp1_state(struct pp_hwmgr *hwmgr,
++				enum pp_mp1_state mp1_state)
++{
++	uint16_t msg;
++	int ret;
++
++	switch (mp1_state) {
++	case PP_MP1_STATE_UNLOAD:
++		msg = PPSMC_MSG_PrepareMp1ForUnload;
++		break;
++	case PP_MP1_STATE_SHUTDOWN:
++	case PP_MP1_STATE_RESET:
++	case PP_MP1_STATE_NONE:
++	default:
++		return 0;
++	}
++
++	PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg)) == 0,
++			    "[PrepareMp1] Failed!",
++			    return ret);
++
++	return 0;
++}
++
+ static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
+ 	.backend_init = vega12_hwmgr_backend_init,
+ 	.backend_fini = vega12_hwmgr_backend_fini,
+@@ -2695,7 +2719,7 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
+ 	.set_asic_baco_state = vega12_baco_set_state,
+ 	.get_ppfeature_status = vega12_get_ppfeature_status,
+ 	.set_ppfeature_status = vega12_set_ppfeature_status,
+-
++	.set_mp1_state = vega12_set_mp1_state,
+ };
+ 
+ int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3139-drm-amdgpu-put-the-SMC-into-the-proper-state-on-rese.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3139-drm-amdgpu-put-the-SMC-into-the-proper-state-on-rese.patch
new file mode 100644
index 00000000..e05b8eb5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3139-drm-amdgpu-put-the-SMC-into-the-proper-state-on-rese.patch
@@ -0,0 +1,106 @@
+From 20db592b684f4023488f5329a9d1015af2f8cef1 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 25 Jul 2019 11:44:59 -0500
+Subject: [PATCH 3139/4256] drm/amdgpu: put the SMC into the proper state on
+ reset/unload
+
+When doing a GPU reset or unloading the driver, we need to
+put the SMU into the apprpriate state for the re-init after
+the reset or unload to reliably work.
+
+I don't think this is necessary for BACO because the SMU actually
+controls the BACO state to it needs to be active.
+
+For suspend (S3), the asic is put into D3 so the SMU would be
+powered down so I don't think we need to put the SMU into
+any special state.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 27 ++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c    |  2 ++
+ 3 files changed, 30 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index ba666a4afdfe..015ebcf3de17 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1030,6 +1030,7 @@ struct amdgpu_device {
+ 	/* record last mm index being written through WREG32*/
+ 	unsigned long last_mm_index;
+ 	bool                            in_gpu_reset;
++	enum pp_mp1_state               mp1_state;
+ 	struct mutex  lock_reset;
+ 	struct amdgpu_doorbell_index doorbell_index;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 429794becdcd..23d0301aad4d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2167,6 +2167,21 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
+ 			DRM_ERROR("suspend of IP block <%s> failed %d\n",
+ 				  adev->ip_blocks[i].version->funcs->name, r);
+ 		}
++		/* handle putting the SMC in the appropriate state */
++		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
++			if (is_support_sw_smu(adev)) {
++				/* todo */
++			} else if (adev->powerplay.pp_funcs &&
++				   adev->powerplay.pp_funcs->set_mp1_state) {
++				r = adev->powerplay.pp_funcs->set_mp1_state(
++					adev->powerplay.pp_handle,
++					adev->mp1_state);
++				if (r) {
++					DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
++						  adev->mp1_state, r);
++				}
++			}
++		}
+ 	}
+ 
+ 	return 0;
+@@ -3641,6 +3656,17 @@ static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, bool trylock)
+ 
+ 	atomic_inc(&adev->gpu_reset_counter);
+ 	adev->in_gpu_reset = 1;
++	switch (amdgpu_asic_reset_method(adev)) {
++	case AMD_RESET_METHOD_MODE1:
++		adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
++		break;
++	case AMD_RESET_METHOD_MODE2:
++		adev->mp1_state = PP_MP1_STATE_RESET;
++		break;
++	default:
++		adev->mp1_state = PP_MP1_STATE_NONE;
++		break;
++	}
+ 	/* Block kfd: SRIOV would do it separately */
+ 	if (!amdgpu_sriov_vf(adev))
+                 amdgpu_amdkfd_pre_reset(adev);
+@@ -3654,6 +3680,7 @@ static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
+ 	if (!amdgpu_sriov_vf(adev))
+                 amdgpu_amdkfd_post_reset(adev);
+ 	amdgpu_vf_error_trans_all(adev);
++	adev->mp1_state = PP_MP1_STATE_NONE;
+ 	adev->in_gpu_reset = 0;
+ 	mutex_unlock(&adev->lock_reset);
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 1d72e2e784d0..2c0e077d209f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1131,7 +1131,9 @@ amdgpu_pci_shutdown(struct pci_dev *pdev)
+ 	 * unfortunately we can't detect certain
+ 	 * hypervisors so just do this all the time.
+ 	 */
++	adev->mp1_state = PP_MP1_STATE_UNLOAD;
+ 	amdgpu_device_ip_suspend(adev);
++	adev->mp1_state = PP_MP1_STATE_NONE;
+ }
+ 
+ static int amdgpu_pmops_suspend(struct device *dev)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3140-drm-amdgpu-powerplay-use-proper-revision-id-for-navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3140-drm-amdgpu-powerplay-use-proper-revision-id-for-navi.patch
new file mode 100644
index 00000000..92792a83
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3140-drm-amdgpu-powerplay-use-proper-revision-id-for-navi.patch
@@ -0,0 +1,32 @@
+From feaacc6c67264e005e2ed8673c7941e9fd3e684b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 25 Jul 2019 22:28:58 -0500
+Subject: [PATCH 3140/4256] drm/amdgpu/powerplay: use proper revision id for
+ navi
+
+The PCI revision id determines the sku.
+
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index c873228bf05f..dbac24e44174 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1592,7 +1592,7 @@ static int navi10_set_peak_clock_by_device(struct smu_context *smu)
+ 	uint32_t sclk_freq = 0, uclk_freq = 0;
+ 	uint32_t uclk_level = 0;
+ 
+-	switch (adev->rev_id) {
++	switch (adev->pdev->revision) {
+ 	case 0xf0: /* XTX */
+ 	case 0xc0:
+ 		sclk_freq = NAVI10_PEAK_SCLK_XTX;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3141-drm-amdgpu-Fix-amdgpu_display_supported_domains-logi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3141-drm-amdgpu-Fix-amdgpu_display_supported_domains-logi.patch
new file mode 100644
index 00000000..45a9650c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3141-drm-amdgpu-Fix-amdgpu_display_supported_domains-logi.patch
@@ -0,0 +1,156 @@
+From fbeb9e7c8c1c0019193e95fa37eb1655a8fbdff4 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Fri, 26 Jul 2019 09:24:35 -0400
+Subject: [PATCH 3141/4256] drm/amdgpu: Fix amdgpu_display_supported_domains
+ logic.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add restriction to dissallow GTT domain if the relevant BO
+doesn't have USWC flag set to avoid the APU hang scenario.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c      | 16 +++++++++++-----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_display.h      |  3 ++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c      |  2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c           | 12 ++++++------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c          |  2 +-
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c    |  2 +-
+ 6 files changed, 22 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+index f1df323f1da5..543f7a8f6c76 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+@@ -189,7 +189,8 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
+ 	}
+ 
+ 	if (!adev->enable_virtual_display) {
+-		r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev));
++		r = amdgpu_bo_pin(new_abo,
++				  amdgpu_display_supported_domains(adev, new_abo->flags));
+ 		if (unlikely(r != 0)) {
+ 			DRM_ERROR("failed to pin new abo buffer before flip\n");
+ 			goto unreserve;
+@@ -493,20 +494,25 @@ static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
+ 	.create_handle = drm_gem_fb_create_handle,
+ };
+ 
+-uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev)
++uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
++					  uint64_t bo_flags)
+ {
+ 	uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
+ 
+ #if defined(CONFIG_DRM_AMD_DC)
+ 	/*
+-	 * if amdgpu_bo_validate_uswc returns false it means that USWC mappings
++	 * if amdgpu_bo_support_uswc returns false it means that USWC mappings
+ 	 * is not supported for this board. But this mapping is required
+ 	 * to avoid hang caused by placement of scanout BO in GTT on certain
+ 	 * APUs. So force the BO placement to VRAM in case this architecture
+ 	 * will not allow USWC mappings.
++	 * Also, don't allow GTT domain if the BO doens't have USWC falg set.
+ 	 */
+-	if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <= CHIP_RAVEN &&
+-	    adev->flags & AMD_IS_APU && amdgpu_bo_support_uswc(0) &&
++	if (adev->asic_type >= CHIP_CARRIZO &&
++	    adev->asic_type <= CHIP_RAVEN &&
++	    (adev->flags & AMD_IS_APU) &&
++	    (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
++	    amdgpu_bo_support_uswc(bo_flags) &&
+ 	    amdgpu_device_asic_has_dc_support(adev->asic_type))
+ 		domain |= AMDGPU_GEM_DOMAIN_GTT;
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
+index ba7b9fb53864..4bed3ce31ae8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
+@@ -38,7 +38,8 @@
+ int amdgpu_display_freesync_ioctl(struct drm_device *dev, void *data,
+ 				  struct drm_file *filp);
+ void amdgpu_display_update_priority(struct amdgpu_device *adev);
+-uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev);
++uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
++					  uint64_t bo_flags);
+ struct drm_framebuffer *
+ amdgpu_display_user_framebuffer_create(struct drm_device *dev,
+ 				       struct drm_file *file_priv,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+index b9d9b4e6c8bf..91f023c928dc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+@@ -301,7 +301,7 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
+ 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
+ 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+ 	struct ttm_operation_ctx ctx = { true, false };
+-	u32 domain = amdgpu_display_supported_domains(adev);
++	u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
+ 	int ret;
+ 	bool reads = (direction == DMA_BIDIRECTIONAL ||
+ 		      direction == DMA_FROM_DEVICE);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+index ce594ef5af4d..72ffe2aa0e6e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+@@ -132,21 +132,21 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
+ 	int aligned_size, size;
+ 	int height = mode_cmd->height;
+ 	u32 cpp;
++	u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
++			       AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS     |
++			       AMDGPU_GEM_CREATE_VRAM_CLEARED 	     |
++			       AMDGPU_GEM_CREATE_CPU_GTT_USWC;
+ 
+ 	cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);
+ 
+ 	/* need to align pitch with crtc limits */
+ 	mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
+ 						  fb_tiled);
+-	domain = amdgpu_display_supported_domains(adev);
++	domain = amdgpu_display_supported_domains(adev, flags);
+ 	height = ALIGN(mode_cmd->height, 8);
+ 	size = mode_cmd->pitches[0] * height;
+ 	aligned_size = ALIGN(size, PAGE_SIZE);
+-	ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain,
+-				       AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+-				       AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS     |
+-				       AMDGPU_GEM_CREATE_VRAM_CLEARED 	     |
+-				       AMDGPU_GEM_CREATE_CPU_GTT_USWC,
++	ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, flags,
+ 				       ttm_bo_type_kernel, NULL, &gobj);
+ 	if (ret) {
+ 		pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+index 1b51194036b5..3642abd765b6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+@@ -847,7 +847,7 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
+ 	args->size = (u64)args->pitch * args->height;
+ 	args->size = ALIGN(args->size, PAGE_SIZE);
+ 	domain = amdgpu_bo_get_preferred_pin_domain(adev,
+-				amdgpu_display_supported_domains(adev));
++				amdgpu_display_supported_domains(adev, flags));
+ 	r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
+ 				     ttm_bo_type_device, NULL, &gobj);
+ 	if (r)
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index a21d46ecc886..d981cbcd2ce2 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -4437,7 +4437,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
+ 		return r;
+ 
+ 	if (plane->type != DRM_PLANE_TYPE_CURSOR)
+-		domain = amdgpu_display_supported_domains(adev);
++		domain = amdgpu_display_supported_domains(adev, rbo->flags);
+ 	else
+ 		domain = AMDGPU_GEM_DOMAIN_VRAM;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3142-drm-amd-amdgpu-vcn_v2_0-Mark-RB-commands-as-KMD-comm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3142-drm-amd-amdgpu-vcn_v2_0-Mark-RB-commands-as-KMD-comm.patch
new file mode 100644
index 00000000..790caf57
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3142-drm-amd-amdgpu-vcn_v2_0-Mark-RB-commands-as-KMD-comm.patch
@@ -0,0 +1,94 @@
+From 2649ecb6a221c7a60c9b3aa1ae71ce58a780f0d0 Mon Sep 17 00:00:00 2001
+From: Thong Thai <thong.thai@amd.com>
+Date: Thu, 25 Jul 2019 11:21:58 -0400
+Subject: [PATCH 3142/4256] drm/amd/amdgpu/vcn_v2_0: Mark RB commands as KMD
+ commands
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This
+bit was previously set by the RBC HW on older firmware. Newer firmware
+uses a SW RBC and this bit has to be set by the driver.
+
+Signed-off-by: Thong Thai <thong.thai@amd.com>
+Reviewed-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  1 +
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c   | 12 ++++++------
+ 2 files changed, 7 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+index 38f0d53a6381..dface275c81a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+@@ -35,6 +35,7 @@
+ #define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
+ #define AMDGPU_VCN_HARVEST_VCN1 (1 << 1)
+ 
++#define VCN_DEC_KMD_CMD 		0x80000000
+ #define VCN_DEC_CMD_FENCE		0x00000000
+ #define VCN_DEC_CMD_TRAP		0x00000001
+ #define VCN_DEC_CMD_WRITE_REG		0x00000004
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+index 88e3dedcf926..800db1f297f6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+@@ -1494,7 +1494,7 @@ void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
+ 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
+ 	amdgpu_ring_write(ring, 0);
+ 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
+-	amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
++	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
+ }
+ 
+ /**
+@@ -1509,7 +1509,7 @@ void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
+ 	struct amdgpu_device *adev = ring->adev;
+ 
+ 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
+-	amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
++	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
+ }
+ 
+ /**
+@@ -1556,7 +1556,7 @@ void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
+ 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
+ 
+ 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
+-	amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
++	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));
+ 
+ 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
+ 	amdgpu_ring_write(ring, 0);
+@@ -1566,7 +1566,7 @@ void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
+ 
+ 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
+ 
+-	amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
++	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));
+ }
+ 
+ /**
+@@ -1612,7 +1612,7 @@ void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+ 
+ 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
+ 
+-	amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
++	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
+ }
+ 
+ void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
+@@ -1643,7 +1643,7 @@ void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
+ 
+ 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
+ 
+-	amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
++	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));
+ }
+ 
+ /**
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3143-drm-amdkfd-Fill-the-name-field-in-node-topology-with.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3143-drm-amdkfd-Fill-the-name-field-in-node-topology-with.patch
new file mode 100644
index 00000000..e8b6a389
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3143-drm-amdkfd-Fill-the-name-field-in-node-topology-with.patch
@@ -0,0 +1,245 @@
+From e1df710802aba86f3e84051f4e5b7bbf3784d31b Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 17 Jul 2019 17:49:19 -0400
+Subject: [PATCH 3143/4256] drm/amdkfd: Fill the name field in node topology
+ with asic name
+
+The name field in node topology has not been used. We re-purpose it to
+hold the asic name, which can be queried by user space applications
+through sysfs.
+
+Change-Id: I6eac5c01cdba41022d6c5b2f4629679a57b32a73
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c   | 18 ++++++++++++++++++
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h     |  1 +
+ drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 16 ++++++----------
+ drivers/gpu/drm/amd/amdkfd/kfd_topology.h |  4 ++--
+ 4 files changed, 27 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index 52851e658bda..b333e81061f5 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -42,6 +42,7 @@ static atomic_t kfd_locked = ATOMIC_INIT(0);
+ #ifdef KFD_SUPPORT_IOMMU_V2
+ static const struct kfd_device_info kaveri_device_info = {
+ 	.asic_family = CHIP_KAVERI,
++	.asic_name = "Kaveri",
+ 	.max_pasid_bits = 16,
+ 	/* max num of queues for KV.TODO should be a dynamic value */
+ 	.max_no_of_hqd	= 24,
+@@ -60,6 +61,7 @@ static const struct kfd_device_info kaveri_device_info = {
+ 
+ static const struct kfd_device_info carrizo_device_info = {
+ 	.asic_family = CHIP_CARRIZO,
++	.asic_name = "Carrizo",
+ 	.max_pasid_bits = 16,
+ 	/* max num of queues for CZ.TODO should be a dynamic value */
+ 	.max_no_of_hqd	= 24,
+@@ -78,6 +80,7 @@ static const struct kfd_device_info carrizo_device_info = {
+ 
+ static const struct kfd_device_info raven_device_info = {
+ 	.asic_family = CHIP_RAVEN,
++	.asic_name = "Raven",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 8,
+@@ -96,6 +99,7 @@ static const struct kfd_device_info raven_device_info = {
+ 
+ static const struct kfd_device_info hawaii_device_info = {
+ 	.asic_family = CHIP_HAWAII,
++	.asic_name = "Hawaii",
+ 	.max_pasid_bits = 16,
+ 	/* max num of queues for KV.TODO should be a dynamic value */
+ 	.max_no_of_hqd	= 24,
+@@ -114,6 +118,7 @@ static const struct kfd_device_info hawaii_device_info = {
+ 
+ static const struct kfd_device_info tonga_device_info = {
+ 	.asic_family = CHIP_TONGA,
++	.asic_name = "Tonga",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 4,
+@@ -131,6 +136,7 @@ static const struct kfd_device_info tonga_device_info = {
+ 
+ static const struct kfd_device_info fiji_device_info = {
+ 	.asic_family = CHIP_FIJI,
++	.asic_name = "Fiji",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 4,
+@@ -148,6 +154,7 @@ static const struct kfd_device_info fiji_device_info = {
+ 
+ static const struct kfd_device_info fiji_vf_device_info = {
+ 	.asic_family = CHIP_FIJI,
++	.asic_name = "Fiji",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 4,
+@@ -166,6 +173,7 @@ static const struct kfd_device_info fiji_vf_device_info = {
+ 
+ static const struct kfd_device_info polaris10_device_info = {
+ 	.asic_family = CHIP_POLARIS10,
++	.asic_name = "Polaris10",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 4,
+@@ -183,6 +191,7 @@ static const struct kfd_device_info polaris10_device_info = {
+ 
+ static const struct kfd_device_info polaris10_vf_device_info = {
+ 	.asic_family = CHIP_POLARIS10,
++	.asic_name = "Polaris10",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 4,
+@@ -200,6 +209,7 @@ static const struct kfd_device_info polaris10_vf_device_info = {
+ 
+ static const struct kfd_device_info polaris11_device_info = {
+ 	.asic_family = CHIP_POLARIS11,
++	.asic_name = "Polaris11",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 4,
+@@ -217,6 +227,7 @@ static const struct kfd_device_info polaris11_device_info = {
+ 
+ static const struct kfd_device_info polaris12_device_info = {
+ 	.asic_family = CHIP_POLARIS12,
++	.asic_name = "Polaris12",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 4,
+@@ -234,6 +245,7 @@ static const struct kfd_device_info polaris12_device_info = {
+ 
+ static const struct kfd_device_info vegam_device_info = {
+ 	.asic_family = CHIP_VEGAM,
++	.asic_name = "VegaM",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 4,
+@@ -251,6 +263,7 @@ static const struct kfd_device_info vegam_device_info = {
+ 
+ static const struct kfd_device_info vega10_device_info = {
+ 	.asic_family = CHIP_VEGA10,
++	.asic_name = "Vega10",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 8,
+@@ -268,6 +281,7 @@ static const struct kfd_device_info vega10_device_info = {
+ 
+ static const struct kfd_device_info vega10_vf_device_info = {
+ 	.asic_family = CHIP_VEGA10,
++	.asic_name = "Vega10",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 8,
+@@ -285,6 +299,7 @@ static const struct kfd_device_info vega10_vf_device_info = {
+ 
+ static const struct kfd_device_info vega12_device_info = {
+ 	.asic_family = CHIP_VEGA12,
++	.asic_name = "Vega12",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 8,
+@@ -302,6 +317,7 @@ static const struct kfd_device_info vega12_device_info = {
+ 
+ static const struct kfd_device_info vega20_device_info = {
+ 	.asic_family = CHIP_VEGA20,
++	.asic_name = "Vega20",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd	= 24,
+ 	.doorbell_size	= 8,
+@@ -319,6 +335,7 @@ static const struct kfd_device_info vega20_device_info = {
+ 
+ static const struct kfd_device_info arcturus_device_info = {
+ 	.asic_family = CHIP_ARCTURUS,
++	.asic_name = "Arcturus",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd	= 24,
+ 	.doorbell_size	= 8,
+@@ -336,6 +353,7 @@ static const struct kfd_device_info arcturus_device_info = {
+ 
+ static const struct kfd_device_info navi10_device_info = {
+ 	.asic_family = CHIP_NAVI10,
++	.asic_name = "Navi10",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 8,
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index a8fe46c22c7d..267c2e4d69a0 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -211,6 +211,7 @@ struct kfd_event_interrupt_class {
+ 
+ struct kfd_device_info {
+ 	enum amd_asic_type asic_family;
++	const char *asic_name;
+ 	const struct kfd_event_interrupt_class *event_interrupt_class;
+ 	unsigned int max_pasid_bits;
+ 	unsigned int max_no_of_hqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+index 65f831f5955c..39ea6a104d63 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+@@ -428,8 +428,6 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr,
+ 		char *buffer)
+ {
+ 	struct kfd_topology_device *dev;
+-	char public_name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
+-	uint32_t i;
+ 	uint32_t log_max_watch_addr;
+ 	struct kfd_local_mem_info local_mem_info;
+ 
+@@ -449,14 +447,8 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr,
+ 				attr_name);
+ 		if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu))
+ 			return -EPERM;
+-		for (i = 0; i < KFD_TOPOLOGY_PUBLIC_NAME_SIZE; i++) {
+-			public_name[i] =
+-					(char)dev->node_props.marketing_name[i];
+-			if (dev->node_props.marketing_name[i] == 0)
+-				break;
+-		}
+-		public_name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE-1] = 0x0;
+-		return sysfs_show_str_val(buffer, public_name);
++
++		return sysfs_show_str_val(buffer, dev->node_props.name);
+ 	}
+ 
+ 	dev = container_of(attr, struct kfd_topology_device,
+@@ -1346,6 +1338,10 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
+ 	 */
+ 
+ 	amdgpu_amdkfd_get_cu_info(dev->gpu->kgd, &cu_info);
++
++	strncpy(dev->node_props.name, gpu->device_info->asic_name,
++			KFD_TOPOLOGY_PUBLIC_NAME_SIZE);
++
+ 	dev->node_props.simd_arrays_per_engine =
+ 		cu_info.num_shader_arrays_per_engine;
+ 
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
+index 0b80ee02e9e7..ba0c62084cc6 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
+@@ -27,7 +27,7 @@
+ #include <linux/list.h>
+ #include "kfd_crat.h"
+ 
+-#define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 128
++#define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 32
+ 
+ #define HSA_CAP_HOT_PLUGGABLE			0x00000001
+ #define HSA_CAP_ATS_PRESENT			0x00000002
+@@ -87,7 +87,7 @@ struct kfd_node_properties {
+ 	int32_t  drm_render_minor;
+ 	uint32_t num_sdma_engines;
+ 	uint32_t num_sdma_xgmi_engines;
+-	uint16_t marketing_name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
++	char name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
+ };
+ 
+ #define HSA_MEM_HEAP_TYPE_SYSTEM	0
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3144-drm-amdgpu-Default-disable-GDS-for-compute-gfx.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3144-drm-amdgpu-Default-disable-GDS-for-compute-gfx.patch
new file mode 100644
index 00000000..60233c15
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3144-drm-amdgpu-Default-disable-GDS-for-compute-gfx.patch
@@ -0,0 +1,219 @@
+From 8d4a229f773bc4e574b7877ce26544272db4b0f7 Mon Sep 17 00:00:00 2001
+From: Joseph Greathouse <Joseph.Greathouse@amd.com>
+Date: Fri, 26 Jul 2019 15:52:05 -0500
+Subject: [PATCH 3144/4256] drm/amdgpu: Default disable GDS for compute+gfx
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Units in the GDS block default to allowing all VMIDs access to all
+entries. Disable shader access to the GDS, GWS, and OA blocks from all
+compute and gfx VMIDs by default. For compute, HWS firmware will set
+up the access bits for the appropriate VMID when a compute queue
+requires access to these blocks.
+The driver will handle enabling access on-demand for graphics VMIDs.
+
+Leaving VMID0 with full access because otherwise HWS cannot save or
+restore values during task switch.
+
+v2: Fixed code and comment styling.
+
+Change-Id: I5b8cf2023b79480555dc909019f062c3c7e37241
+Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 25 ++++++++++++++++-------
+ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  | 24 +++++++++++++++-------
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 24 +++++++++++++++-------
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 28 +++++++++++++++++---------
+ 4 files changed, 71 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 23ed5b2dae19..3df1e6212123 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1516,17 +1516,27 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
+ 	}
+ 	nv_grbm_select(adev, 0, 0, 0, 0);
+ 	mutex_unlock(&adev->srbm_mutex);
++}
+ 
+-	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
+-	   acccess. These should be enabled by FW for target VMIDs. */
+-	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+-		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
+-		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
+-		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
+-		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
++static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
++{
++	int vmid;
++
++	/*
++	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
++	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
++	 * the driver can enable them for graphics. VMID0 should maintain
++	 * access so that HWS firmware can save/restore entries.
++	 */
++	for (vmid = 1; vmid < 16; vmid++) {
++		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
++		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
++		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
++		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
+ 	}
+ }
+ 
++
+ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
+ {
+ 	int i, j, k;
+@@ -1629,6 +1639,7 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
+ 	mutex_unlock(&adev->srbm_mutex);
+ 
+ 	gfx_v10_0_init_compute_vmid(adev);
++	gfx_v10_0_init_gds_vmid(adev);
+ 
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+index 3f98624772a4..48796b6824cf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+@@ -1877,14 +1877,23 @@ static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
+ 	}
+ 	cik_srbm_select(adev, 0, 0, 0, 0);
+ 	mutex_unlock(&adev->srbm_mutex);
++}
+ 
+-	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
+-	   acccess. These should be enabled by FW for target VMIDs. */
+-	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+-		WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
+-		WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
+-		WREG32(amdgpu_gds_reg_offset[i].gws, 0);
+-		WREG32(amdgpu_gds_reg_offset[i].oa, 0);
++static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev)
++{
++	int vmid;
++
++	/*
++	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
++	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
++	 * the driver can enable them for graphics. VMID0 should maintain
++	 * access so that HWS firmware can save/restore entries.
++	 */
++	for (vmid = 1; vmid < 16; vmid++) {
++		WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
++		WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
++		WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
++		WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
+ 	}
+ }
+ 
+@@ -1966,6 +1975,7 @@ static void gfx_v7_0_constants_init(struct amdgpu_device *adev)
+ 	mutex_unlock(&adev->srbm_mutex);
+ 
+ 	gfx_v7_0_init_compute_vmid(adev);
++	gfx_v7_0_init_gds_vmid(adev);
+ 
+ 	WREG32(mmSX_DEBUG_1, 0x20);
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index a18d8ab1e4b2..79ccc4bfb676 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -3702,14 +3702,23 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
+ 	}
+ 	vi_srbm_select(adev, 0, 0, 0, 0);
+ 	mutex_unlock(&adev->srbm_mutex);
++}
+ 
+-	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
+-	   acccess. These should be enabled by FW for target VMIDs. */
+-	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+-		WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
+-		WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
+-		WREG32(amdgpu_gds_reg_offset[i].gws, 0);
+-		WREG32(amdgpu_gds_reg_offset[i].oa, 0);
++static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
++{
++	int vmid;
++
++	/*
++	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
++	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
++	 * the driver can enable them for graphics. VMID0 should maintain
++	 * access so that HWS firmware can save/restore entries.
++	 */
++	for (vmid = 1; vmid < 16; vmid++) {
++		WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
++		WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
++		WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
++		WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
+ 	}
+ }
+ 
+@@ -3779,6 +3788,7 @@ static void gfx_v8_0_constants_init(struct amdgpu_device *adev)
+ 	mutex_unlock(&adev->srbm_mutex);
+ 
+ 	gfx_v8_0_init_compute_vmid(adev);
++	gfx_v8_0_init_gds_vmid(adev);
+ 
+ 	mutex_lock(&adev->grbm_idx_mutex);
+ 	/*
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 45d5919b0cd5..1b24a338cbdf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -2030,15 +2030,6 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
+ 	}
+ 	soc15_grbm_select(adev, 0, 0, 0, 0);
+ 	mutex_unlock(&adev->srbm_mutex);
+-
+-	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
+-	   acccess. These should be enabled by FW for target VMIDs. */
+-	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+-		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
+-		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
+-		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
+-		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
+-	}
+ 	data = 0;
+ 	data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
+ 			VMID_SEL, trap_config_vmid_mask);
+@@ -2047,6 +2038,24 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
+ 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
+ }
+ 
++static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev)
++{
++	int vmid;
++
++	/*
++	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
++	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
++	 * the driver can enable them for graphics. VMID0 should maintain
++	 * access so that HWS firmware can save/restore entries.
++	 */
++	for (vmid = 1; vmid < 16; vmid++) {
++		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
++		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
++		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
++		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
++	}
++}
++
+ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
+ {
+ 	u32 tmp;
+@@ -2091,6 +2100,7 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
+ 	mutex_unlock(&adev->srbm_mutex);
+ 
+ 	gfx_v9_0_init_compute_vmid(adev);
++	gfx_v9_0_init_gds_vmid(adev);
+ }
+ 
+ static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3145-drm-amd-powerplay-move-smu-types-to-smu_types.h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3145-drm-amd-powerplay-move-smu-types-to-smu_types.h.patch
new file mode 100644
index 00000000..935e6e4b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3145-drm-amd-powerplay-move-smu-types-to-smu_types.h.patch
@@ -0,0 +1,447 @@
+From ff727cb715b8197cfb2ac7710c20fef12d47dccb Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Thu, 25 Jul 2019 09:59:46 +0800
+Subject: [PATCH 3145/4256] drm/amd/powerplay: move smu types to smu_types.h
+
+move some enum type (message, feature, clock) to smu_types.h.
+these types is too long in amdgpu_smu.h, and not clearly.
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    | 186 +---------------
+ drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 210 ++++++++++++++++++
+ 2 files changed, 211 insertions(+), 185 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 33d2d75ba903..397040a4d1b4 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -26,6 +26,7 @@
+ #include "kgd_pp_interface.h"
+ #include "dm_pp_interface.h"
+ #include "dm_pp_smu.h"
++#include "smu_types.h"
+ 
+ #define SMU_THERMAL_MINIMUM_ALERT_TEMP		0
+ #define SMU_THERMAL_MAXIMUM_ALERT_TEMP		255
+@@ -150,134 +151,6 @@ struct smu_power_state {
+ 	struct smu_hw_power_state                     hardware;
+ };
+ 
+-enum smu_message_type
+-{
+-	SMU_MSG_TestMessage = 0,
+-	SMU_MSG_GetSmuVersion,
+-	SMU_MSG_GetDriverIfVersion,
+-	SMU_MSG_SetAllowedFeaturesMaskLow,
+-	SMU_MSG_SetAllowedFeaturesMaskHigh,
+-	SMU_MSG_EnableAllSmuFeatures,
+-	SMU_MSG_DisableAllSmuFeatures,
+-	SMU_MSG_EnableSmuFeaturesLow,
+-	SMU_MSG_EnableSmuFeaturesHigh,
+-	SMU_MSG_DisableSmuFeaturesLow,
+-	SMU_MSG_DisableSmuFeaturesHigh,
+-	SMU_MSG_GetEnabledSmuFeaturesLow,
+-	SMU_MSG_GetEnabledSmuFeaturesHigh,
+-	SMU_MSG_SetWorkloadMask,
+-	SMU_MSG_SetPptLimit,
+-	SMU_MSG_SetDriverDramAddrHigh,
+-	SMU_MSG_SetDriverDramAddrLow,
+-	SMU_MSG_SetToolsDramAddrHigh,
+-	SMU_MSG_SetToolsDramAddrLow,
+-	SMU_MSG_TransferTableSmu2Dram,
+-	SMU_MSG_TransferTableDram2Smu,
+-	SMU_MSG_UseDefaultPPTable,
+-	SMU_MSG_UseBackupPPTable,
+-	SMU_MSG_RunBtc,
+-	SMU_MSG_RequestI2CBus,
+-	SMU_MSG_ReleaseI2CBus,
+-	SMU_MSG_SetFloorSocVoltage,
+-	SMU_MSG_SoftReset,
+-	SMU_MSG_StartBacoMonitor,
+-	SMU_MSG_CancelBacoMonitor,
+-	SMU_MSG_EnterBaco,
+-	SMU_MSG_SetSoftMinByFreq,
+-	SMU_MSG_SetSoftMaxByFreq,
+-	SMU_MSG_SetHardMinByFreq,
+-	SMU_MSG_SetHardMaxByFreq,
+-	SMU_MSG_GetMinDpmFreq,
+-	SMU_MSG_GetMaxDpmFreq,
+-	SMU_MSG_GetDpmFreqByIndex,
+-	SMU_MSG_GetDpmClockFreq,
+-	SMU_MSG_GetSsVoltageByDpm,
+-	SMU_MSG_SetMemoryChannelConfig,
+-	SMU_MSG_SetGeminiMode,
+-	SMU_MSG_SetGeminiApertureHigh,
+-	SMU_MSG_SetGeminiApertureLow,
+-	SMU_MSG_SetMinLinkDpmByIndex,
+-	SMU_MSG_OverridePcieParameters,
+-	SMU_MSG_OverDriveSetPercentage,
+-	SMU_MSG_SetMinDeepSleepDcefclk,
+-	SMU_MSG_ReenableAcDcInterrupt,
+-	SMU_MSG_NotifyPowerSource,
+-	SMU_MSG_SetUclkFastSwitch,
+-	SMU_MSG_SetUclkDownHyst,
+-	SMU_MSG_GfxDeviceDriverReset,
+-	SMU_MSG_GetCurrentRpm,
+-	SMU_MSG_SetVideoFps,
+-	SMU_MSG_SetTjMax,
+-	SMU_MSG_SetFanTemperatureTarget,
+-	SMU_MSG_PrepareMp1ForUnload,
+-	SMU_MSG_DramLogSetDramAddrHigh,
+-	SMU_MSG_DramLogSetDramAddrLow,
+-	SMU_MSG_DramLogSetDramSize,
+-	SMU_MSG_SetFanMaxRpm,
+-	SMU_MSG_SetFanMinPwm,
+-	SMU_MSG_ConfigureGfxDidt,
+-	SMU_MSG_NumOfDisplays,
+-	SMU_MSG_RemoveMargins,
+-	SMU_MSG_ReadSerialNumTop32,
+-	SMU_MSG_ReadSerialNumBottom32,
+-	SMU_MSG_SetSystemVirtualDramAddrHigh,
+-	SMU_MSG_SetSystemVirtualDramAddrLow,
+-	SMU_MSG_WaflTest,
+-	SMU_MSG_SetFclkGfxClkRatio,
+-	SMU_MSG_AllowGfxOff,
+-	SMU_MSG_DisallowGfxOff,
+-	SMU_MSG_GetPptLimit,
+-	SMU_MSG_GetDcModeMaxDpmFreq,
+-	SMU_MSG_GetDebugData,
+-	SMU_MSG_SetXgmiMode,
+-	SMU_MSG_RunAfllBtc,
+-	SMU_MSG_ExitBaco,
+-	SMU_MSG_PrepareMp1ForReset,
+-	SMU_MSG_PrepareMp1ForShutdown,
+-	SMU_MSG_SetMGpuFanBoostLimitRpm,
+-	SMU_MSG_GetAVFSVoltageByDpm,
+-	SMU_MSG_PowerUpVcn,
+-	SMU_MSG_PowerDownVcn,
+-	SMU_MSG_PowerUpJpeg,
+-	SMU_MSG_PowerDownJpeg,
+-	SMU_MSG_BacoAudioD3PME,
+-	SMU_MSG_ArmD3,
+-	SMU_MSG_RunGfxDcBtc,
+-	SMU_MSG_RunSocDcBtc,
+-	SMU_MSG_SetMemoryChannelEnable,
+-	SMU_MSG_SetDfSwitchType,
+-	SMU_MSG_GetVoltageByDpm,
+-	SMU_MSG_GetVoltageByDpmOverdrive,
+-	SMU_MSG_PowerUpVcn0,
+-	SMU_MSG_PowerDownVcn01,
+-	SMU_MSG_PowerUpVcn1,
+-	SMU_MSG_PowerDownVcn1,
+-	SMU_MSG_MAX_COUNT,
+-};
+-
+-enum smu_clk_type
+-{
+-	SMU_GFXCLK,
+-	SMU_VCLK,
+-	SMU_DCLK,
+-	SMU_ECLK,
+-	SMU_SOCCLK,
+-	SMU_UCLK,
+-	SMU_DCEFCLK,
+-	SMU_DISPCLK,
+-	SMU_PIXCLK,
+-	SMU_PHYCLK,
+-	SMU_FCLK,
+-	SMU_SCLK,
+-	SMU_MCLK,
+-	SMU_PCIE,
+-	SMU_OD_SCLK,
+-	SMU_OD_MCLK,
+-	SMU_OD_VDDC_CURVE,
+-	SMU_OD_RANGE,
+-	SMU_CLK_COUNT,
+-};
+-
+ enum smu_power_src_type
+ {
+ 	SMU_POWER_SOURCE_AC,
+@@ -285,63 +158,6 @@ enum smu_power_src_type
+ 	SMU_POWER_SOURCE_COUNT,
+ };
+ 
+-enum smu_feature_mask
+-{
+-	SMU_FEATURE_DPM_PREFETCHER_BIT,
+-	SMU_FEATURE_DPM_GFXCLK_BIT,
+-	SMU_FEATURE_DPM_UCLK_BIT,
+-	SMU_FEATURE_DPM_SOCCLK_BIT,
+-	SMU_FEATURE_DPM_UVD_BIT,
+-	SMU_FEATURE_DPM_VCE_BIT,
+-	SMU_FEATURE_ULV_BIT,
+-	SMU_FEATURE_DPM_MP0CLK_BIT,
+-	SMU_FEATURE_DPM_LINK_BIT,
+-	SMU_FEATURE_DPM_DCEFCLK_BIT,
+-	SMU_FEATURE_DS_GFXCLK_BIT,
+-	SMU_FEATURE_DS_SOCCLK_BIT,
+-	SMU_FEATURE_DS_LCLK_BIT,
+-	SMU_FEATURE_PPT_BIT,
+-	SMU_FEATURE_TDC_BIT,
+-	SMU_FEATURE_THERMAL_BIT,
+-	SMU_FEATURE_GFX_PER_CU_CG_BIT,
+-	SMU_FEATURE_RM_BIT,
+-	SMU_FEATURE_DS_DCEFCLK_BIT,
+-	SMU_FEATURE_ACDC_BIT,
+-	SMU_FEATURE_VR0HOT_BIT,
+-	SMU_FEATURE_VR1HOT_BIT,
+-	SMU_FEATURE_FW_CTF_BIT,
+-	SMU_FEATURE_LED_DISPLAY_BIT,
+-	SMU_FEATURE_FAN_CONTROL_BIT,
+-	SMU_FEATURE_GFX_EDC_BIT,
+-	SMU_FEATURE_GFXOFF_BIT,
+-	SMU_FEATURE_CG_BIT,
+-	SMU_FEATURE_DPM_FCLK_BIT,
+-	SMU_FEATURE_DS_FCLK_BIT,
+-	SMU_FEATURE_DS_MP1CLK_BIT,
+-	SMU_FEATURE_DS_MP0CLK_BIT,
+-	SMU_FEATURE_XGMI_BIT,
+-	SMU_FEATURE_DPM_GFX_PACE_BIT,
+-	SMU_FEATURE_MEM_VDDCI_SCALING_BIT,
+-	SMU_FEATURE_MEM_MVDD_SCALING_BIT,
+-	SMU_FEATURE_DS_UCLK_BIT,
+-	SMU_FEATURE_GFX_ULV_BIT,
+-	SMU_FEATURE_FW_DSTATE_BIT,
+-	SMU_FEATURE_BACO_BIT,
+-	SMU_FEATURE_VCN_PG_BIT,
+-	SMU_FEATURE_JPEG_PG_BIT,
+-	SMU_FEATURE_USB_PG_BIT,
+-	SMU_FEATURE_RSMU_SMN_CG_BIT,
+-	SMU_FEATURE_APCC_PLUS_BIT,
+-	SMU_FEATURE_GTHR_BIT,
+-	SMU_FEATURE_GFX_DCS_BIT,
+-	SMU_FEATURE_GFX_SS_BIT,
+-	SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,
+-	SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT,
+-	SMU_FEATURE_MMHUB_PG_BIT,
+-	SMU_FEATURE_ATHUB_PG_BIT,
+-	SMU_FEATURE_COUNT,
+-};
+-
+ enum smu_memory_pool_size
+ {
+     SMU_MEMORY_POOL_SIZE_ZERO   = 0,
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+new file mode 100644
+index 000000000000..29d14c162417
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+@@ -0,0 +1,210 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef __SMU_TYPES_H__
++#define __SMU_TYPES_H__
++
++
++enum smu_message_type {
++	SMU_MSG_TestMessage = 0,
++	SMU_MSG_GetSmuVersion,
++	SMU_MSG_GetDriverIfVersion,
++	SMU_MSG_SetAllowedFeaturesMaskLow,
++	SMU_MSG_SetAllowedFeaturesMaskHigh,
++	SMU_MSG_EnableAllSmuFeatures,
++	SMU_MSG_DisableAllSmuFeatures,
++	SMU_MSG_EnableSmuFeaturesLow,
++	SMU_MSG_EnableSmuFeaturesHigh,
++	SMU_MSG_DisableSmuFeaturesLow,
++	SMU_MSG_DisableSmuFeaturesHigh,
++	SMU_MSG_GetEnabledSmuFeaturesLow,
++	SMU_MSG_GetEnabledSmuFeaturesHigh,
++	SMU_MSG_SetWorkloadMask,
++	SMU_MSG_SetPptLimit,
++	SMU_MSG_SetDriverDramAddrHigh,
++	SMU_MSG_SetDriverDramAddrLow,
++	SMU_MSG_SetToolsDramAddrHigh,
++	SMU_MSG_SetToolsDramAddrLow,
++	SMU_MSG_TransferTableSmu2Dram,
++	SMU_MSG_TransferTableDram2Smu,
++	SMU_MSG_UseDefaultPPTable,
++	SMU_MSG_UseBackupPPTable,
++	SMU_MSG_RunBtc,
++	SMU_MSG_RequestI2CBus,
++	SMU_MSG_ReleaseI2CBus,
++	SMU_MSG_SetFloorSocVoltage,
++	SMU_MSG_SoftReset,
++	SMU_MSG_StartBacoMonitor,
++	SMU_MSG_CancelBacoMonitor,
++	SMU_MSG_EnterBaco,
++	SMU_MSG_SetSoftMinByFreq,
++	SMU_MSG_SetSoftMaxByFreq,
++	SMU_MSG_SetHardMinByFreq,
++	SMU_MSG_SetHardMaxByFreq,
++	SMU_MSG_GetMinDpmFreq,
++	SMU_MSG_GetMaxDpmFreq,
++	SMU_MSG_GetDpmFreqByIndex,
++	SMU_MSG_GetDpmClockFreq,
++	SMU_MSG_GetSsVoltageByDpm,
++	SMU_MSG_SetMemoryChannelConfig,
++	SMU_MSG_SetGeminiMode,
++	SMU_MSG_SetGeminiApertureHigh,
++	SMU_MSG_SetGeminiApertureLow,
++	SMU_MSG_SetMinLinkDpmByIndex,
++	SMU_MSG_OverridePcieParameters,
++	SMU_MSG_OverDriveSetPercentage,
++	SMU_MSG_SetMinDeepSleepDcefclk,
++	SMU_MSG_ReenableAcDcInterrupt,
++	SMU_MSG_NotifyPowerSource,
++	SMU_MSG_SetUclkFastSwitch,
++	SMU_MSG_SetUclkDownHyst,
++	SMU_MSG_GfxDeviceDriverReset,
++	SMU_MSG_GetCurrentRpm,
++	SMU_MSG_SetVideoFps,
++	SMU_MSG_SetTjMax,
++	SMU_MSG_SetFanTemperatureTarget,
++	SMU_MSG_PrepareMp1ForUnload,
++	SMU_MSG_DramLogSetDramAddrHigh,
++	SMU_MSG_DramLogSetDramAddrLow,
++	SMU_MSG_DramLogSetDramSize,
++	SMU_MSG_SetFanMaxRpm,
++	SMU_MSG_SetFanMinPwm,
++	SMU_MSG_ConfigureGfxDidt,
++	SMU_MSG_NumOfDisplays,
++	SMU_MSG_RemoveMargins,
++	SMU_MSG_ReadSerialNumTop32,
++	SMU_MSG_ReadSerialNumBottom32,
++	SMU_MSG_SetSystemVirtualDramAddrHigh,
++	SMU_MSG_SetSystemVirtualDramAddrLow,
++	SMU_MSG_WaflTest,
++	SMU_MSG_SetFclkGfxClkRatio,
++	SMU_MSG_AllowGfxOff,
++	SMU_MSG_DisallowGfxOff,
++	SMU_MSG_GetPptLimit,
++	SMU_MSG_GetDcModeMaxDpmFreq,
++	SMU_MSG_GetDebugData,
++	SMU_MSG_SetXgmiMode,
++	SMU_MSG_RunAfllBtc,
++	SMU_MSG_ExitBaco,
++	SMU_MSG_PrepareMp1ForReset,
++	SMU_MSG_PrepareMp1ForShutdown,
++	SMU_MSG_SetMGpuFanBoostLimitRpm,
++	SMU_MSG_GetAVFSVoltageByDpm,
++	SMU_MSG_PowerUpVcn,
++	SMU_MSG_PowerDownVcn,
++	SMU_MSG_PowerUpJpeg,
++	SMU_MSG_PowerDownJpeg,
++	SMU_MSG_BacoAudioD3PME,
++	SMU_MSG_ArmD3,
++	SMU_MSG_RunGfxDcBtc,
++	SMU_MSG_RunSocDcBtc,
++	SMU_MSG_SetMemoryChannelEnable,
++	SMU_MSG_SetDfSwitchType,
++	SMU_MSG_GetVoltageByDpm,
++	SMU_MSG_GetVoltageByDpmOverdrive,
++	SMU_MSG_PowerUpVcn0,
++	SMU_MSG_PowerDownVcn01,
++	SMU_MSG_PowerUpVcn1,
++	SMU_MSG_PowerDownVcn1,
++	SMU_MSG_MAX_COUNT,
++};
++
++enum smu_clk_type {
++	SMU_GFXCLK,
++	SMU_VCLK,
++	SMU_DCLK,
++	SMU_ECLK,
++	SMU_SOCCLK,
++	SMU_UCLK,
++	SMU_DCEFCLK,
++	SMU_DISPCLK,
++	SMU_PIXCLK,
++	SMU_PHYCLK,
++	SMU_FCLK,
++	SMU_SCLK,
++	SMU_MCLK,
++	SMU_PCIE,
++	SMU_OD_SCLK,
++	SMU_OD_MCLK,
++	SMU_OD_VDDC_CURVE,
++	SMU_OD_RANGE,
++	SMU_CLK_COUNT,
++};
++
++enum smu_feature_mask {
++	SMU_FEATURE_DPM_PREFETCHER_BIT,
++	SMU_FEATURE_DPM_GFXCLK_BIT,
++	SMU_FEATURE_DPM_UCLK_BIT,
++	SMU_FEATURE_DPM_SOCCLK_BIT,
++	SMU_FEATURE_DPM_UVD_BIT,
++	SMU_FEATURE_DPM_VCE_BIT,
++	SMU_FEATURE_ULV_BIT,
++	SMU_FEATURE_DPM_MP0CLK_BIT,
++	SMU_FEATURE_DPM_LINK_BIT,
++	SMU_FEATURE_DPM_DCEFCLK_BIT,
++	SMU_FEATURE_DS_GFXCLK_BIT,
++	SMU_FEATURE_DS_SOCCLK_BIT,
++	SMU_FEATURE_DS_LCLK_BIT,
++	SMU_FEATURE_PPT_BIT,
++	SMU_FEATURE_TDC_BIT,
++	SMU_FEATURE_THERMAL_BIT,
++	SMU_FEATURE_GFX_PER_CU_CG_BIT,
++	SMU_FEATURE_RM_BIT,
++	SMU_FEATURE_DS_DCEFCLK_BIT,
++	SMU_FEATURE_ACDC_BIT,
++	SMU_FEATURE_VR0HOT_BIT,
++	SMU_FEATURE_VR1HOT_BIT,
++	SMU_FEATURE_FW_CTF_BIT,
++	SMU_FEATURE_LED_DISPLAY_BIT,
++	SMU_FEATURE_FAN_CONTROL_BIT,
++	SMU_FEATURE_GFX_EDC_BIT,
++	SMU_FEATURE_GFXOFF_BIT,
++	SMU_FEATURE_CG_BIT,
++	SMU_FEATURE_DPM_FCLK_BIT,
++	SMU_FEATURE_DS_FCLK_BIT,
++	SMU_FEATURE_DS_MP1CLK_BIT,
++	SMU_FEATURE_DS_MP0CLK_BIT,
++	SMU_FEATURE_XGMI_BIT,
++	SMU_FEATURE_DPM_GFX_PACE_BIT,
++	SMU_FEATURE_MEM_VDDCI_SCALING_BIT,
++	SMU_FEATURE_MEM_MVDD_SCALING_BIT,
++	SMU_FEATURE_DS_UCLK_BIT,
++	SMU_FEATURE_GFX_ULV_BIT,
++	SMU_FEATURE_FW_DSTATE_BIT,
++	SMU_FEATURE_BACO_BIT,
++	SMU_FEATURE_VCN_PG_BIT,
++	SMU_FEATURE_JPEG_PG_BIT,
++	SMU_FEATURE_USB_PG_BIT,
++	SMU_FEATURE_RSMU_SMN_CG_BIT,
++	SMU_FEATURE_APCC_PLUS_BIT,
++	SMU_FEATURE_GTHR_BIT,
++	SMU_FEATURE_GFX_DCS_BIT,
++	SMU_FEATURE_GFX_SS_BIT,
++	SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,
++	SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT,
++	SMU_FEATURE_MMHUB_PG_BIT,
++	SMU_FEATURE_ATHUB_PG_BIT,
++	SMU_FEATURE_COUNT,
++};
++
++#endif
++
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3146-drm-amd-powerplay-add-smu-message-name-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3146-drm-amd-powerplay-add-smu-message-name-support.patch
new file mode 100644
index 00000000..4efa6ae3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3146-drm-amd-powerplay-add-smu-message-name-support.patch
@@ -0,0 +1,313 @@
+From 349fb584033fb9b4321e45287749342229233713 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Thu, 25 Jul 2019 10:32:48 +0800
+Subject: [PATCH 3146/4256] drm/amd/powerplay: add smu message name support
+
+add smu_get_message_name support in smu.
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  13 ++
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |   1 +
+ drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 205 +++++++++---------
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     |  12 +-
+ 4 files changed, 124 insertions(+), 107 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index b78eeeab87da..ba403b5028eb 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -30,6 +30,19 @@
+ #include "atom.h"
+ #include "amd_pcie.h"
+ 
++#undef __SMU_DUMMY_MAP
++#define __SMU_DUMMY_MAP(type)	#type
++static const char* __smu_message_names[] = {
++	SMU_MESSAGE_TYPES
++};
++
++const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
++{
++	if (type < 0 || type > SMU_MSG_MAX_COUNT)
++		return "unknow smu message";
++	return __smu_message_names[type];
++}
++
+ int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
+ {
+ 	int ret = 0;
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 397040a4d1b4..035f857922ec 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -804,5 +804,6 @@ enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
+ int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
+ int smu_set_display_count(struct smu_context *smu, uint32_t count);
+ bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
++const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+index 29d14c162417..d42e3424e704 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+@@ -23,108 +23,112 @@
+ #ifndef __SMU_TYPES_H__
+ #define __SMU_TYPES_H__
+ 
++#define SMU_MESSAGE_TYPES			      \
++       __SMU_DUMMY_MAP(TestMessage),		      \
++       __SMU_DUMMY_MAP(GetSmuVersion),                \
++       __SMU_DUMMY_MAP(GetDriverIfVersion),           \
++       __SMU_DUMMY_MAP(SetAllowedFeaturesMaskLow),    \
++       __SMU_DUMMY_MAP(SetAllowedFeaturesMaskHigh),   \
++       __SMU_DUMMY_MAP(EnableAllSmuFeatures),         \
++       __SMU_DUMMY_MAP(DisableAllSmuFeatures),        \
++       __SMU_DUMMY_MAP(EnableSmuFeaturesLow),         \
++       __SMU_DUMMY_MAP(EnableSmuFeaturesHigh),        \
++       __SMU_DUMMY_MAP(DisableSmuFeaturesLow),        \
++       __SMU_DUMMY_MAP(DisableSmuFeaturesHigh),       \
++       __SMU_DUMMY_MAP(GetEnabledSmuFeaturesLow),     \
++       __SMU_DUMMY_MAP(GetEnabledSmuFeaturesHigh),    \
++       __SMU_DUMMY_MAP(SetWorkloadMask),              \
++       __SMU_DUMMY_MAP(SetPptLimit),                  \
++       __SMU_DUMMY_MAP(SetDriverDramAddrHigh),        \
++       __SMU_DUMMY_MAP(SetDriverDramAddrLow),         \
++       __SMU_DUMMY_MAP(SetToolsDramAddrHigh),         \
++       __SMU_DUMMY_MAP(SetToolsDramAddrLow),          \
++       __SMU_DUMMY_MAP(TransferTableSmu2Dram),        \
++       __SMU_DUMMY_MAP(TransferTableDram2Smu),        \
++       __SMU_DUMMY_MAP(UseDefaultPPTable),            \
++       __SMU_DUMMY_MAP(UseBackupPPTable),             \
++       __SMU_DUMMY_MAP(RunBtc),                       \
++       __SMU_DUMMY_MAP(RequestI2CBus),                \
++       __SMU_DUMMY_MAP(ReleaseI2CBus),                \
++       __SMU_DUMMY_MAP(SetFloorSocVoltage),           \
++       __SMU_DUMMY_MAP(SoftReset),                    \
++       __SMU_DUMMY_MAP(StartBacoMonitor),             \
++       __SMU_DUMMY_MAP(CancelBacoMonitor),            \
++       __SMU_DUMMY_MAP(EnterBaco),                    \
++       __SMU_DUMMY_MAP(SetSoftMinByFreq),             \
++       __SMU_DUMMY_MAP(SetSoftMaxByFreq),             \
++       __SMU_DUMMY_MAP(SetHardMinByFreq),             \
++       __SMU_DUMMY_MAP(SetHardMaxByFreq),             \
++       __SMU_DUMMY_MAP(GetMinDpmFreq),                \
++       __SMU_DUMMY_MAP(GetMaxDpmFreq),                \
++       __SMU_DUMMY_MAP(GetDpmFreqByIndex),            \
++       __SMU_DUMMY_MAP(GetDpmClockFreq),              \
++       __SMU_DUMMY_MAP(GetSsVoltageByDpm),            \
++       __SMU_DUMMY_MAP(SetMemoryChannelConfig),       \
++       __SMU_DUMMY_MAP(SetGeminiMode),                \
++       __SMU_DUMMY_MAP(SetGeminiApertureHigh),        \
++       __SMU_DUMMY_MAP(SetGeminiApertureLow),         \
++       __SMU_DUMMY_MAP(SetMinLinkDpmByIndex),         \
++       __SMU_DUMMY_MAP(OverridePcieParameters),       \
++       __SMU_DUMMY_MAP(OverDriveSetPercentage),       \
++       __SMU_DUMMY_MAP(SetMinDeepSleepDcefclk),       \
++       __SMU_DUMMY_MAP(ReenableAcDcInterrupt),        \
++       __SMU_DUMMY_MAP(NotifyPowerSource),            \
++       __SMU_DUMMY_MAP(SetUclkFastSwitch),            \
++       __SMU_DUMMY_MAP(SetUclkDownHyst),              \
++       __SMU_DUMMY_MAP(GfxDeviceDriverReset),         \
++       __SMU_DUMMY_MAP(GetCurrentRpm),                \
++       __SMU_DUMMY_MAP(SetVideoFps),                  \
++       __SMU_DUMMY_MAP(SetTjMax),                     \
++       __SMU_DUMMY_MAP(SetFanTemperatureTarget),      \
++       __SMU_DUMMY_MAP(PrepareMp1ForUnload),          \
++       __SMU_DUMMY_MAP(DramLogSetDramAddrHigh),       \
++       __SMU_DUMMY_MAP(DramLogSetDramAddrLow),        \
++       __SMU_DUMMY_MAP(DramLogSetDramSize),           \
++       __SMU_DUMMY_MAP(SetFanMaxRpm),                 \
++       __SMU_DUMMY_MAP(SetFanMinPwm),                 \
++       __SMU_DUMMY_MAP(ConfigureGfxDidt),             \
++       __SMU_DUMMY_MAP(NumOfDisplays),                \
++       __SMU_DUMMY_MAP(RemoveMargins),                \
++       __SMU_DUMMY_MAP(ReadSerialNumTop32),           \
++       __SMU_DUMMY_MAP(ReadSerialNumBottom32),        \
++       __SMU_DUMMY_MAP(SetSystemVirtualDramAddrHigh), \
++       __SMU_DUMMY_MAP(SetSystemVirtualDramAddrLow),  \
++       __SMU_DUMMY_MAP(WaflTest),                     \
++       __SMU_DUMMY_MAP(SetFclkGfxClkRatio),           \
++       __SMU_DUMMY_MAP(AllowGfxOff),                  \
++       __SMU_DUMMY_MAP(DisallowGfxOff),               \
++       __SMU_DUMMY_MAP(GetPptLimit),                  \
++       __SMU_DUMMY_MAP(GetDcModeMaxDpmFreq),          \
++       __SMU_DUMMY_MAP(GetDebugData),                 \
++       __SMU_DUMMY_MAP(SetXgmiMode),                  \
++       __SMU_DUMMY_MAP(RunAfllBtc),                   \
++       __SMU_DUMMY_MAP(ExitBaco),                     \
++       __SMU_DUMMY_MAP(PrepareMp1ForReset),           \
++       __SMU_DUMMY_MAP(PrepareMp1ForShutdown),        \
++       __SMU_DUMMY_MAP(SetMGpuFanBoostLimitRpm),      \
++       __SMU_DUMMY_MAP(GetAVFSVoltageByDpm),          \
++       __SMU_DUMMY_MAP(PowerUpVcn),                   \
++       __SMU_DUMMY_MAP(PowerDownVcn),                 \
++       __SMU_DUMMY_MAP(PowerUpJpeg),                  \
++       __SMU_DUMMY_MAP(PowerDownJpeg),                \
++       __SMU_DUMMY_MAP(BacoAudioD3PME),               \
++       __SMU_DUMMY_MAP(ArmD3),                        \
++       __SMU_DUMMY_MAP(RunGfxDcBtc),                  \
++       __SMU_DUMMY_MAP(RunSocDcBtc),                  \
++       __SMU_DUMMY_MAP(SetMemoryChannelEnable),       \
++       __SMU_DUMMY_MAP(SetDfSwitchType),              \
++       __SMU_DUMMY_MAP(GetVoltageByDpm),              \
++       __SMU_DUMMY_MAP(GetVoltageByDpmOverdrive),     \
++       __SMU_DUMMY_MAP(PowerUpVcn0),                  \
++       __SMU_DUMMY_MAP(PowerDownVcn01),               \
++       __SMU_DUMMY_MAP(PowerUpVcn1),                  \
++       __SMU_DUMMY_MAP(PowerDownVcn1),                \
+ 
++#undef __SMU_DUMMY_MAP
++#define __SMU_DUMMY_MAP(type)	SMU_MSG_##type
+ enum smu_message_type {
+-	SMU_MSG_TestMessage = 0,
+-	SMU_MSG_GetSmuVersion,
+-	SMU_MSG_GetDriverIfVersion,
+-	SMU_MSG_SetAllowedFeaturesMaskLow,
+-	SMU_MSG_SetAllowedFeaturesMaskHigh,
+-	SMU_MSG_EnableAllSmuFeatures,
+-	SMU_MSG_DisableAllSmuFeatures,
+-	SMU_MSG_EnableSmuFeaturesLow,
+-	SMU_MSG_EnableSmuFeaturesHigh,
+-	SMU_MSG_DisableSmuFeaturesLow,
+-	SMU_MSG_DisableSmuFeaturesHigh,
+-	SMU_MSG_GetEnabledSmuFeaturesLow,
+-	SMU_MSG_GetEnabledSmuFeaturesHigh,
+-	SMU_MSG_SetWorkloadMask,
+-	SMU_MSG_SetPptLimit,
+-	SMU_MSG_SetDriverDramAddrHigh,
+-	SMU_MSG_SetDriverDramAddrLow,
+-	SMU_MSG_SetToolsDramAddrHigh,
+-	SMU_MSG_SetToolsDramAddrLow,
+-	SMU_MSG_TransferTableSmu2Dram,
+-	SMU_MSG_TransferTableDram2Smu,
+-	SMU_MSG_UseDefaultPPTable,
+-	SMU_MSG_UseBackupPPTable,
+-	SMU_MSG_RunBtc,
+-	SMU_MSG_RequestI2CBus,
+-	SMU_MSG_ReleaseI2CBus,
+-	SMU_MSG_SetFloorSocVoltage,
+-	SMU_MSG_SoftReset,
+-	SMU_MSG_StartBacoMonitor,
+-	SMU_MSG_CancelBacoMonitor,
+-	SMU_MSG_EnterBaco,
+-	SMU_MSG_SetSoftMinByFreq,
+-	SMU_MSG_SetSoftMaxByFreq,
+-	SMU_MSG_SetHardMinByFreq,
+-	SMU_MSG_SetHardMaxByFreq,
+-	SMU_MSG_GetMinDpmFreq,
+-	SMU_MSG_GetMaxDpmFreq,
+-	SMU_MSG_GetDpmFreqByIndex,
+-	SMU_MSG_GetDpmClockFreq,
+-	SMU_MSG_GetSsVoltageByDpm,
+-	SMU_MSG_SetMemoryChannelConfig,
+-	SMU_MSG_SetGeminiMode,
+-	SMU_MSG_SetGeminiApertureHigh,
+-	SMU_MSG_SetGeminiApertureLow,
+-	SMU_MSG_SetMinLinkDpmByIndex,
+-	SMU_MSG_OverridePcieParameters,
+-	SMU_MSG_OverDriveSetPercentage,
+-	SMU_MSG_SetMinDeepSleepDcefclk,
+-	SMU_MSG_ReenableAcDcInterrupt,
+-	SMU_MSG_NotifyPowerSource,
+-	SMU_MSG_SetUclkFastSwitch,
+-	SMU_MSG_SetUclkDownHyst,
+-	SMU_MSG_GfxDeviceDriverReset,
+-	SMU_MSG_GetCurrentRpm,
+-	SMU_MSG_SetVideoFps,
+-	SMU_MSG_SetTjMax,
+-	SMU_MSG_SetFanTemperatureTarget,
+-	SMU_MSG_PrepareMp1ForUnload,
+-	SMU_MSG_DramLogSetDramAddrHigh,
+-	SMU_MSG_DramLogSetDramAddrLow,
+-	SMU_MSG_DramLogSetDramSize,
+-	SMU_MSG_SetFanMaxRpm,
+-	SMU_MSG_SetFanMinPwm,
+-	SMU_MSG_ConfigureGfxDidt,
+-	SMU_MSG_NumOfDisplays,
+-	SMU_MSG_RemoveMargins,
+-	SMU_MSG_ReadSerialNumTop32,
+-	SMU_MSG_ReadSerialNumBottom32,
+-	SMU_MSG_SetSystemVirtualDramAddrHigh,
+-	SMU_MSG_SetSystemVirtualDramAddrLow,
+-	SMU_MSG_WaflTest,
+-	SMU_MSG_SetFclkGfxClkRatio,
+-	SMU_MSG_AllowGfxOff,
+-	SMU_MSG_DisallowGfxOff,
+-	SMU_MSG_GetPptLimit,
+-	SMU_MSG_GetDcModeMaxDpmFreq,
+-	SMU_MSG_GetDebugData,
+-	SMU_MSG_SetXgmiMode,
+-	SMU_MSG_RunAfllBtc,
+-	SMU_MSG_ExitBaco,
+-	SMU_MSG_PrepareMp1ForReset,
+-	SMU_MSG_PrepareMp1ForShutdown,
+-	SMU_MSG_SetMGpuFanBoostLimitRpm,
+-	SMU_MSG_GetAVFSVoltageByDpm,
+-	SMU_MSG_PowerUpVcn,
+-	SMU_MSG_PowerDownVcn,
+-	SMU_MSG_PowerUpJpeg,
+-	SMU_MSG_PowerDownJpeg,
+-	SMU_MSG_BacoAudioD3PME,
+-	SMU_MSG_ArmD3,
+-	SMU_MSG_RunGfxDcBtc,
+-	SMU_MSG_RunSocDcBtc,
+-	SMU_MSG_SetMemoryChannelEnable,
+-	SMU_MSG_SetDfSwitchType,
+-	SMU_MSG_GetVoltageByDpm,
+-	SMU_MSG_GetVoltageByDpmOverdrive,
+-	SMU_MSG_PowerUpVcn0,
+-	SMU_MSG_PowerDownVcn01,
+-	SMU_MSG_PowerUpVcn1,
+-	SMU_MSG_PowerDownVcn1,
++	SMU_MESSAGE_TYPES
+ 	SMU_MSG_MAX_COUNT,
+ };
+ 
+@@ -207,4 +211,3 @@ enum smu_feature_mask {
+ };
+ 
+ #endif
+-
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index cee480b39ffc..95a182b20098 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -102,8 +102,8 @@ static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
+ 	ret = smu_v11_0_wait_for_response(smu);
+ 
+ 	if (ret)
+-		pr_err("Failed to send message 0x%x, response 0x%x\n", index,
+-		       ret);
++		pr_err("failed send message: %10s (%d) response %#x\n",
++		       smu_get_message_name(smu, msg), index, ret);
+ 
+ 	return ret;
+ 
+@@ -123,8 +123,8 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
+ 
+ 	ret = smu_v11_0_wait_for_response(smu);
+ 	if (ret)
+-		pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
+-		       index, ret, param);
++		pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
++		       smu_get_message_name(smu, msg), index, param, ret);
+ 
+ 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
+ 
+@@ -134,8 +134,8 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
+ 
+ 	ret = smu_v11_0_wait_for_response(smu);
+ 	if (ret)
+-		pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
+-		       index, ret, param);
++		pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
++		       smu_get_message_name(smu, msg), index, param, ret);
+ 
+ 	return ret;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3147-drm-amd-powerplay-add-smu-feature-name-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3147-drm-amd-powerplay-add-smu-feature-name-support.patch
new file mode 100644
index 00000000..28d4d915
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3147-drm-amd-powerplay-add-smu-feature-name-support.patch
@@ -0,0 +1,174 @@
+From e523eee2ebe26bc73cc015ed79a2b91f959e310c Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Thu, 25 Jul 2019 11:08:42 +0800
+Subject: [PATCH 3147/4256] drm/amd/powerplay: add smu feature name support
+
+add smu_get_feature_name support in smu.
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  13 +++
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |   1 +
+ drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 109 +++++++++---------
+ 3 files changed, 71 insertions(+), 52 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index ba403b5028eb..18623c66f694 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -43,6 +43,19 @@ const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type
+ 	return __smu_message_names[type];
+ }
+ 
++#undef __SMU_DUMMY_MAP
++#define __SMU_DUMMY_MAP(fea)	#fea
++static const char* __smu_feature_names[] = {
++	SMU_FEATURE_MASKS
++};
++
++const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
++{
++	if (feature < 0 || feature > SMU_FEATURE_COUNT)
++		return "unknow smu feature";
++	return __smu_feature_names[feature];
++}
++
+ int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
+ {
+ 	int ret = 0;
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 035f857922ec..ba2385026b89 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -805,5 +805,6 @@ int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_lev
+ int smu_set_display_count(struct smu_context *smu, uint32_t count);
+ bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
+ const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
++const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+index d42e3424e704..8793c8d0dc52 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+@@ -154,59 +154,64 @@ enum smu_clk_type {
+ 	SMU_CLK_COUNT,
+ };
+ 
++#define SMU_FEATURE_MASKS				\
++       __SMU_DUMMY_MAP(DPM_PREFETCHER),			\
++       __SMU_DUMMY_MAP(DPM_GFXCLK),                    	\
++       __SMU_DUMMY_MAP(DPM_UCLK),                      	\
++       __SMU_DUMMY_MAP(DPM_SOCCLK),                    	\
++       __SMU_DUMMY_MAP(DPM_UVD),                       	\
++       __SMU_DUMMY_MAP(DPM_VCE),                       	\
++       __SMU_DUMMY_MAP(ULV),                           	\
++       __SMU_DUMMY_MAP(DPM_MP0CLK),                    	\
++       __SMU_DUMMY_MAP(DPM_LINK),                      	\
++       __SMU_DUMMY_MAP(DPM_DCEFCLK),                   	\
++       __SMU_DUMMY_MAP(DS_GFXCLK),                     	\
++       __SMU_DUMMY_MAP(DS_SOCCLK),                     	\
++       __SMU_DUMMY_MAP(DS_LCLK),                       	\
++       __SMU_DUMMY_MAP(PPT),                           	\
++       __SMU_DUMMY_MAP(TDC),                           	\
++       __SMU_DUMMY_MAP(THERMAL),                       	\
++       __SMU_DUMMY_MAP(GFX_PER_CU_CG),                 	\
++       __SMU_DUMMY_MAP(RM),                            	\
++       __SMU_DUMMY_MAP(DS_DCEFCLK),                    	\
++       __SMU_DUMMY_MAP(ACDC),                          	\
++       __SMU_DUMMY_MAP(VR0HOT),                        	\
++       __SMU_DUMMY_MAP(VR1HOT),                        	\
++       __SMU_DUMMY_MAP(FW_CTF),                        	\
++       __SMU_DUMMY_MAP(LED_DISPLAY),                   	\
++       __SMU_DUMMY_MAP(FAN_CONTROL),                   	\
++       __SMU_DUMMY_MAP(GFX_EDC),                       	\
++       __SMU_DUMMY_MAP(GFXOFF),                        	\
++       __SMU_DUMMY_MAP(CG),                            	\
++       __SMU_DUMMY_MAP(DPM_FCLK),                      	\
++       __SMU_DUMMY_MAP(DS_FCLK),                       	\
++       __SMU_DUMMY_MAP(DS_MP1CLK),                     	\
++       __SMU_DUMMY_MAP(DS_MP0CLK),                     	\
++       __SMU_DUMMY_MAP(XGMI),                          	\
++       __SMU_DUMMY_MAP(DPM_GFX_PACE),                  	\
++       __SMU_DUMMY_MAP(MEM_VDDCI_SCALING),             	\
++       __SMU_DUMMY_MAP(MEM_MVDD_SCALING),              	\
++       __SMU_DUMMY_MAP(DS_UCLK),                       	\
++       __SMU_DUMMY_MAP(GFX_ULV),                       	\
++       __SMU_DUMMY_MAP(FW_DSTATE),                     	\
++       __SMU_DUMMY_MAP(BACO),                          	\
++       __SMU_DUMMY_MAP(VCN_PG),                        	\
++       __SMU_DUMMY_MAP(JPEG_PG),                       	\
++       __SMU_DUMMY_MAP(USB_PG),                        	\
++       __SMU_DUMMY_MAP(RSMU_SMN_CG),                   	\
++       __SMU_DUMMY_MAP(APCC_PLUS),                     	\
++       __SMU_DUMMY_MAP(GTHR),                          	\
++       __SMU_DUMMY_MAP(GFX_DCS),                       	\
++       __SMU_DUMMY_MAP(GFX_SS),                        	\
++       __SMU_DUMMY_MAP(OUT_OF_BAND_MONITOR),           	\
++       __SMU_DUMMY_MAP(TEMP_DEPENDENT_VMIN),           	\
++       __SMU_DUMMY_MAP(MMHUB_PG),                      	\
++       __SMU_DUMMY_MAP(ATHUB_PG),                      	\
++
++#undef __SMU_DUMMY_MAP
++#define __SMU_DUMMY_MAP(feature)	SMU_FEATURE_##feature##_BIT
+ enum smu_feature_mask {
+-	SMU_FEATURE_DPM_PREFETCHER_BIT,
+-	SMU_FEATURE_DPM_GFXCLK_BIT,
+-	SMU_FEATURE_DPM_UCLK_BIT,
+-	SMU_FEATURE_DPM_SOCCLK_BIT,
+-	SMU_FEATURE_DPM_UVD_BIT,
+-	SMU_FEATURE_DPM_VCE_BIT,
+-	SMU_FEATURE_ULV_BIT,
+-	SMU_FEATURE_DPM_MP0CLK_BIT,
+-	SMU_FEATURE_DPM_LINK_BIT,
+-	SMU_FEATURE_DPM_DCEFCLK_BIT,
+-	SMU_FEATURE_DS_GFXCLK_BIT,
+-	SMU_FEATURE_DS_SOCCLK_BIT,
+-	SMU_FEATURE_DS_LCLK_BIT,
+-	SMU_FEATURE_PPT_BIT,
+-	SMU_FEATURE_TDC_BIT,
+-	SMU_FEATURE_THERMAL_BIT,
+-	SMU_FEATURE_GFX_PER_CU_CG_BIT,
+-	SMU_FEATURE_RM_BIT,
+-	SMU_FEATURE_DS_DCEFCLK_BIT,
+-	SMU_FEATURE_ACDC_BIT,
+-	SMU_FEATURE_VR0HOT_BIT,
+-	SMU_FEATURE_VR1HOT_BIT,
+-	SMU_FEATURE_FW_CTF_BIT,
+-	SMU_FEATURE_LED_DISPLAY_BIT,
+-	SMU_FEATURE_FAN_CONTROL_BIT,
+-	SMU_FEATURE_GFX_EDC_BIT,
+-	SMU_FEATURE_GFXOFF_BIT,
+-	SMU_FEATURE_CG_BIT,
+-	SMU_FEATURE_DPM_FCLK_BIT,
+-	SMU_FEATURE_DS_FCLK_BIT,
+-	SMU_FEATURE_DS_MP1CLK_BIT,
+-	SMU_FEATURE_DS_MP0CLK_BIT,
+-	SMU_FEATURE_XGMI_BIT,
+-	SMU_FEATURE_DPM_GFX_PACE_BIT,
+-	SMU_FEATURE_MEM_VDDCI_SCALING_BIT,
+-	SMU_FEATURE_MEM_MVDD_SCALING_BIT,
+-	SMU_FEATURE_DS_UCLK_BIT,
+-	SMU_FEATURE_GFX_ULV_BIT,
+-	SMU_FEATURE_FW_DSTATE_BIT,
+-	SMU_FEATURE_BACO_BIT,
+-	SMU_FEATURE_VCN_PG_BIT,
+-	SMU_FEATURE_JPEG_PG_BIT,
+-	SMU_FEATURE_USB_PG_BIT,
+-	SMU_FEATURE_RSMU_SMN_CG_BIT,
+-	SMU_FEATURE_APCC_PLUS_BIT,
+-	SMU_FEATURE_GTHR_BIT,
+-	SMU_FEATURE_GFX_DCS_BIT,
+-	SMU_FEATURE_GFX_SS_BIT,
+-	SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,
+-	SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT,
+-	SMU_FEATURE_MMHUB_PG_BIT,
+-	SMU_FEATURE_ATHUB_PG_BIT,
++	SMU_FEATURE_MASKS
+ 	SMU_FEATURE_COUNT,
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3148-drm-amd-powerplay-move-smu_feature_update_enable_sta.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3148-drm-amd-powerplay-move-smu_feature_update_enable_sta.patch
new file mode 100644
index 00000000..5e1c29f8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3148-drm-amd-powerplay-move-smu_feature_update_enable_sta.patch
@@ -0,0 +1,173 @@
+From 64b93cee2413c817ebe68ac4d9ce8a1b429ebc2c Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Thu, 25 Jul 2019 11:57:25 +0800
+Subject: [PATCH 3148/4256] drm/amd/powerplay: move
+ smu_feature_update_enable_state to up level
+
+this function is not ip or asic related function,
+so move it to top level as public api in smu.
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 40 ++++++++++++++++++-
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  4 +-
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 39 ------------------
+ 3 files changed, 40 insertions(+), 43 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 18623c66f694..1863a71d3d8d 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -509,6 +509,41 @@ int smu_feature_init_dpm(struct smu_context *smu)
+ 
+ 	return ret;
+ }
++int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled)
++{
++	uint32_t feature_low = 0, feature_high = 0;
++	int ret = 0;
++
++	if (!smu->pm_enabled)
++		return ret;
++
++	feature_low = (feature_mask >> 0 ) & 0xffffffff;
++	feature_high = (feature_mask >> 32) & 0xffffffff;
++
++	if (enabled) {
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
++						  feature_low);
++		if (ret)
++			return ret;
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
++						  feature_high);
++		if (ret)
++			return ret;
++
++	} else {
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
++						  feature_low);
++		if (ret)
++			return ret;
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
++						  feature_high);
++		if (ret)
++			return ret;
++
++	}
++
++	return ret;
++}
+ 
+ int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
+ {
+@@ -534,6 +569,7 @@ int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
+ {
+ 	struct smu_feature *feature = &smu->smu_feature;
+ 	int feature_id;
++	uint64_t feature_mask = 0;
+ 	int ret = 0;
+ 
+ 	feature_id = smu_feature_get_index(smu, mask);
+@@ -542,8 +578,10 @@ int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
+ 
+ 	WARN_ON(feature_id > feature->feature_num);
+ 
++	feature_mask = 1ULL << feature_id;
++
+ 	mutex_lock(&feature->mutex);
+-	ret = smu_feature_update_enable_state(smu, feature_id, enable);
++	ret = smu_feature_update_enable_state(smu, feature_mask, enable);
+ 	if (ret)
+ 		goto failed;
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index ba2385026b89..abc2644b4c07 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -479,7 +479,6 @@ struct smu_funcs
+ 	int (*init_display_count)(struct smu_context *smu, uint32_t count);
+ 	int (*set_allowed_mask)(struct smu_context *smu);
+ 	int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
+-	int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
+ 	int (*notify_display_change)(struct smu_context *smu);
+ 	int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool def);
+ 	int (*set_power_limit)(struct smu_context *smu, uint32_t n);
+@@ -595,8 +594,6 @@ struct smu_funcs
+ 	((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
+ #define smu_is_dpm_running(smu) \
+ 	((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
+-#define smu_feature_update_enable_state(smu, feature_id, enabled) \
+-	((smu)->funcs->update_feature_enable_state? (smu)->funcs->update_feature_enable_state((smu), (feature_id), (enabled)) : 0)
+ #define smu_notify_display_change(smu) \
+ 	((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
+ #define smu_store_powerplay_table(smu) \
+@@ -804,6 +801,7 @@ enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
+ int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
+ int smu_set_display_count(struct smu_context *smu, uint32_t count);
+ bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
++int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);
+ const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
+ const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 95a182b20098..caf02ea4a481 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -795,44 +795,6 @@ static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32_t feature_id, bool enabled)
+-{
+-	uint32_t feature_low = 0, feature_high = 0;
+-	int ret = 0;
+-
+-	if (!smu->pm_enabled)
+-		return ret;
+-	if (feature_id >= 0 && feature_id < 31)
+-		feature_low = (1 << feature_id);
+-	else if (feature_id > 31 && feature_id < 63)
+-		feature_high = (1 << feature_id);
+-	else
+-		return -EINVAL;
+-
+-	if (enabled) {
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
+-						  feature_low);
+-		if (ret)
+-			return ret;
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
+-						  feature_high);
+-		if (ret)
+-			return ret;
+-
+-	} else {
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
+-						  feature_low);
+-		if (ret)
+-			return ret;
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
+-						  feature_high);
+-		if (ret)
+-			return ret;
+-
+-	}
+-
+-	return ret;
+-}
+ 
+ static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
+ {
+@@ -1779,7 +1741,6 @@ static const struct smu_funcs smu_v11_0_funcs = {
+ 	.set_allowed_mask = smu_v11_0_set_allowed_mask,
+ 	.get_enabled_mask = smu_v11_0_get_enabled_mask,
+ 	.system_features_control = smu_v11_0_system_features_control,
+-	.update_feature_enable_state = smu_v11_0_update_feature_enable_state,
+ 	.notify_display_change = smu_v11_0_notify_display_change,
+ 	.get_power_limit = smu_v11_0_get_power_limit,
+ 	.set_power_limit = smu_v11_0_set_power_limit,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3149-drm-amd-powerplay-implment-sysfs-feature-status-func.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3149-drm-amd-powerplay-implment-sysfs-feature-status-func.patch
new file mode 100644
index 00000000..d3f08916
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3149-drm-amd-powerplay-implment-sysfs-feature-status-func.patch
@@ -0,0 +1,570 @@
+From 6d6780efd48311e04a1a13544c5d1fa315b7d056 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Thu, 25 Jul 2019 11:47:44 +0800
+Subject: [PATCH 3149/4256] drm/amd/powerplay: implment sysfs feature status
+ function in smu
+
+1. Unified feature enable status format in sysfs
+2. Rename ppfeature to pp_features to adapt other pp sysfs node name
+3. this function support all asic, not asic related function.
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Acked-by: Rui Huang <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c        |  24 +--
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  61 +++++++
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |   8 +-
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 165 ------------------
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 153 ----------------
+ 5 files changed, 75 insertions(+), 336 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index d9d1a7dd6514..783cd0192d33 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -742,10 +742,10 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
+ }
+ 
+ /**
+- * DOC: ppfeatures
++ * DOC: pp_features
+  *
+  * The amdgpu driver provides a sysfs API for adjusting what powerplay
+- * features to be enabled. The file ppfeatures is used for this. And
++ * features to be enabled. The file pp_features is used for this. And
+  * this is only available for Vega10 and later dGPUs.
+  *
+  * Reading back the file will show you the followings:
+@@ -757,7 +757,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
+  * the corresponding bit from original ppfeature masks and input the
+  * new ppfeature masks.
+  */
+-static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
++static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
+ 		struct device_attribute *attr,
+ 		const char *buf,
+ 		size_t count)
+@@ -774,7 +774,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
+ 	pr_debug("featuremask = 0x%llx\n", featuremask);
+ 
+ 	if (is_support_sw_smu(adev)) {
+-		ret = smu_set_ppfeature_status(&adev->smu, featuremask);
++		ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
+ 		if (ret)
+ 			return -EINVAL;
+ 	} else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
+@@ -786,7 +786,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
+ 	return count;
+ }
+ 
+-static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
++static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
+ 		struct device_attribute *attr,
+ 		char *buf)
+ {
+@@ -794,7 +794,7 @@ static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
+ 	struct amdgpu_device *adev = ddev->dev_private;
+ 
+ 	if (is_support_sw_smu(adev)) {
+-		return smu_get_ppfeature_status(&adev->smu, buf);
++		return smu_sys_get_pp_feature_mask(&adev->smu, buf);
+ 	} else if (adev->powerplay.pp_funcs->get_ppfeature_status)
+ 		return amdgpu_dpm_get_ppfeature_status(adev, buf);
+ 
+@@ -1454,9 +1454,9 @@ static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
+ static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
+ 		amdgpu_get_memory_busy_percent, NULL);
+ static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
+-static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
+-		amdgpu_get_ppfeature_status,
+-		amdgpu_set_ppfeature_status);
++static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR,
++		amdgpu_get_pp_feature_status,
++		amdgpu_set_pp_feature_status);
+ static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);
+ 
+ static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
+@@ -2912,10 +2912,10 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
+ 	if ((adev->asic_type >= CHIP_VEGA10) &&
+ 	    !(adev->flags & AMD_IS_APU)) {
+ 		ret = device_create_file(adev->dev,
+-				&dev_attr_ppfeatures);
++				&dev_attr_pp_features);
+ 		if (ret) {
+ 			DRM_ERROR("failed to create device file	"
+-					"ppfeatures\n");
++					"pp_features\n");
+ 			return ret;
+ 		}
+ 	}
+@@ -2969,7 +2969,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
+ 		device_remove_file(adev->dev, &dev_attr_unique_id);
+ 	if ((adev->asic_type >= CHIP_VEGA10) &&
+ 	    !(adev->flags & AMD_IS_APU))
+-		device_remove_file(adev->dev, &dev_attr_ppfeatures);
++		device_remove_file(adev->dev, &dev_attr_pp_features);
+ }
+ 
+ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 1863a71d3d8d..974472015487 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -56,6 +56,67 @@ const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask
+ 	return __smu_feature_names[feature];
+ }
+ 
++size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
++{
++	size_t size = 0;
++	int ret = 0, i = 0;
++	uint32_t feature_mask[2] = { 0 };
++	int32_t feature_index = 0;
++	uint32_t count = 0;
++
++	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
++	if (ret)
++		goto failed;
++
++	size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
++			feature_mask[1], feature_mask[0]);
++
++	for (i = 0; i < SMU_FEATURE_COUNT; i++) {
++		feature_index = smu_feature_get_index(smu, i);
++		if (feature_index < 0)
++			continue;
++		size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
++			       count++,
++			       smu_get_feature_name(smu, i),
++			       feature_index,
++			       !!smu_feature_is_enabled(smu, i) ? "enabeld" : "disabled");
++	}
++
++failed:
++	return size;
++}
++
++int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
++{
++	int ret = 0;
++	uint32_t feature_mask[2] = { 0 };
++	uint64_t feature_2_enabled = 0;
++	uint64_t feature_2_disabled = 0;
++	uint64_t feature_enables = 0;
++
++	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
++	if (ret)
++		return ret;
++
++	feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
++
++	feature_2_enabled  = ~feature_enables & new_mask;
++	feature_2_disabled = feature_enables & ~new_mask;
++
++	if (feature_2_enabled) {
++		ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
++		if (ret)
++			return ret;
++	}
++	if (feature_2_disabled) {
++		ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
++		if (ret)
++			return ret;
++	}
++
++	return ret;
++}
++
+ int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
+ {
+ 	int ret = 0;
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index abc2644b4c07..ac9e9d5d8a5c 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -432,8 +432,6 @@ struct pptable_funcs {
+ 				      uint32_t *mclk_mask,
+ 				      uint32_t *soc_mask);
+ 	int (*set_cpu_power_state)(struct smu_context *smu);
+-	int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures);
+-	int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
+ 	bool (*is_dpm_running)(struct smu_context *smu);
+ 	int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
+ 	int (*set_thermal_fan_table)(struct smu_context *smu);
+@@ -713,10 +711,6 @@ struct smu_funcs
+ 	((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
+ #define smu_set_xgmi_pstate(smu, pstate) \
+ 		((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
+-#define smu_set_ppfeature_status(smu, ppfeatures) \
+-	((smu)->ppt_funcs->set_ppfeature_status ? (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)
+-#define smu_get_ppfeature_status(smu, buf) \
+-	((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)
+ #define smu_set_watermarks_table(smu, tab, clock_ranges) \
+ 	((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
+ #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
+@@ -804,5 +798,7 @@ bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
+ int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);
+ const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
+ const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
++size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
++int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index dbac24e44174..9dd96d8b8dd5 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1422,169 +1422,6 @@ static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_
+ 	return 0;
+ }
+ 
+-static int navi10_get_ppfeature_status(struct smu_context *smu,
+-				       char *buf)
+-{
+-	static const char *ppfeature_name[] = {
+-				"DPM_PREFETCHER",
+-				"DPM_GFXCLK",
+-				"DPM_GFX_PACE",
+-				"DPM_UCLK",
+-				"DPM_SOCCLK",
+-				"DPM_MP0CLK",
+-				"DPM_LINK",
+-				"DPM_DCEFCLK",
+-				"MEM_VDDCI_SCALING",
+-				"MEM_MVDD_SCALING",
+-				"DS_GFXCLK",
+-				"DS_SOCCLK",
+-				"DS_LCLK",
+-				"DS_DCEFCLK",
+-				"DS_UCLK",
+-				"GFX_ULV",
+-				"FW_DSTATE",
+-				"GFXOFF",
+-				"BACO",
+-				"VCN_PG",
+-				"JPEG_PG",
+-				"USB_PG",
+-				"RSMU_SMN_CG",
+-				"PPT",
+-				"TDC",
+-				"GFX_EDC",
+-				"APCC_PLUS",
+-				"GTHR",
+-				"ACDC",
+-				"VR0HOT",
+-				"VR1HOT",
+-				"FW_CTF",
+-				"FAN_CONTROL",
+-				"THERMAL",
+-				"GFX_DCS",
+-				"RM",
+-				"LED_DISPLAY",
+-				"GFX_SS",
+-				"OUT_OF_BAND_MONITOR",
+-				"TEMP_DEPENDENT_VMIN",
+-				"MMHUB_PG",
+-				"ATHUB_PG"};
+-	static const char *output_title[] = {
+-				"FEATURES",
+-				"BITMASK",
+-				"ENABLEMENT"};
+-	uint64_t features_enabled;
+-	uint32_t feature_mask[2];
+-	int i;
+-	int ret = 0;
+-	int size = 0;
+-
+-	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+-	PP_ASSERT_WITH_CODE(!ret,
+-			"[GetPPfeatureStatus] Failed to get enabled smc features!",
+-			return ret);
+-	features_enabled = (uint64_t)feature_mask[0] |
+-			   (uint64_t)feature_mask[1] << 32;
+-
+-	size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
+-	size += sprintf(buf + size, "%-19s %-22s %s\n",
+-				output_title[0],
+-				output_title[1],
+-				output_title[2]);
+-	for (i = 0; i < (sizeof(ppfeature_name) / sizeof(ppfeature_name[0])); i++) {
+-		size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
+-					ppfeature_name[i],
+-					1ULL << i,
+-					(features_enabled & (1ULL << i)) ? "Y" : "N");
+-	}
+-
+-	return size;
+-}
+-
+-static int navi10_enable_smc_features(struct smu_context *smu,
+-				      bool enabled,
+-				      uint64_t feature_masks)
+-{
+-	struct smu_feature *feature = &smu->smu_feature;
+-	uint32_t feature_low, feature_high;
+-	uint32_t feature_mask[2];
+-	int ret = 0;
+-
+-	feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);
+-	feature_high = (uint32_t)((feature_masks & 0xFFFFFFFF00000000ULL) >> 32);
+-
+-	if (enabled) {
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
+-						  feature_low);
+-		if (ret)
+-			return ret;
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
+-						  feature_high);
+-		if (ret)
+-			return ret;
+-	} else {
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
+-						  feature_low);
+-		if (ret)
+-			return ret;
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
+-						  feature_high);
+-		if (ret)
+-			return ret;
+-	}
+-
+-	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+-	if (ret)
+-		return ret;
+-
+-	mutex_lock(&feature->mutex);
+-	bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
+-		    feature->feature_num);
+-	mutex_unlock(&feature->mutex);
+-
+-	return 0;
+-}
+-
+-static int navi10_set_ppfeature_status(struct smu_context *smu,
+-				       uint64_t new_ppfeature_masks)
+-{
+-	uint64_t features_enabled;
+-	uint32_t feature_mask[2];
+-	uint64_t features_to_enable;
+-	uint64_t features_to_disable;
+-	int ret = 0;
+-
+-	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+-	PP_ASSERT_WITH_CODE(!ret,
+-			"[SetPPfeatureStatus] Failed to get enabled smc features!",
+-			return ret);
+-	features_enabled = (uint64_t)feature_mask[0] |
+-			   (uint64_t)feature_mask[1] << 32;
+-
+-	features_to_disable =
+-		features_enabled & ~new_ppfeature_masks;
+-	features_to_enable =
+-		~features_enabled & new_ppfeature_masks;
+-
+-	pr_debug("features_to_disable 0x%llx\n", features_to_disable);
+-	pr_debug("features_to_enable 0x%llx\n", features_to_enable);
+-
+-	if (features_to_disable) {
+-		ret = navi10_enable_smc_features(smu, false, features_to_disable);
+-		PP_ASSERT_WITH_CODE(!ret,
+-				"[SetPPfeatureStatus] Failed to disable smc features!",
+-				return ret);
+-	}
+-
+-	if (features_to_enable) {
+-		ret = navi10_enable_smc_features(smu, true, features_to_enable);
+-		PP_ASSERT_WITH_CODE(!ret,
+-				"[SetPPfeatureStatus] Failed to enable smc features!",
+-				return ret);
+-	}
+-
+-	return 0;
+-}
+-
+ static int navi10_set_peak_clock_by_device(struct smu_context *smu)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+@@ -1689,8 +1526,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.set_watermarks_table = navi10_set_watermarks_table,
+ 	.read_sensor = navi10_read_sensor,
+ 	.get_uclk_dpm_states = navi10_get_uclk_dpm_states,
+-	.get_ppfeature_status = navi10_get_ppfeature_status,
+-	.set_ppfeature_status = navi10_set_ppfeature_status,
+ 	.set_performance_level = navi10_set_performance_level,
+ 	.get_thermal_temperature_range = navi10_get_thermal_temperature_range,
+ };
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index c06a9472c3b2..52c8fc9f1ff4 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -2858,157 +2858,6 @@ static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
+ 	return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
+ }
+ 
+-static int vega20_get_enabled_smc_features(struct smu_context *smu,
+-		uint64_t *features_enabled)
+-{
+-	uint32_t feature_mask[2] = {0, 0};
+-	int ret = 0;
+-
+-	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+-	if (ret)
+-		return ret;
+-
+-	*features_enabled = ((((uint64_t)feature_mask[0] << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
+-			(((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
+-
+-	return ret;
+-}
+-
+-static int vega20_enable_smc_features(struct smu_context *smu,
+-		bool enable, uint64_t feature_mask)
+-{
+-	uint32_t smu_features_low, smu_features_high;
+-	int ret = 0;
+-
+-	smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
+-	smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
+-
+-	if (enable) {
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
+-						  smu_features_low);
+-		if (ret)
+-			return ret;
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
+-						  smu_features_high);
+-		if (ret)
+-			return ret;
+-	} else {
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
+-						  smu_features_low);
+-		if (ret)
+-			return ret;
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
+-						  smu_features_high);
+-		if (ret)
+-			return ret;
+-	}
+-
+-	return 0;
+-
+-}
+-
+-static int vega20_get_ppfeature_status(struct smu_context *smu, char *buf)
+-{
+-	static const char *ppfeature_name[] = {
+-				"DPM_PREFETCHER",
+-				"GFXCLK_DPM",
+-				"UCLK_DPM",
+-				"SOCCLK_DPM",
+-				"UVD_DPM",
+-				"VCE_DPM",
+-				"ULV",
+-				"MP0CLK_DPM",
+-				"LINK_DPM",
+-				"DCEFCLK_DPM",
+-				"GFXCLK_DS",
+-				"SOCCLK_DS",
+-				"LCLK_DS",
+-				"PPT",
+-				"TDC",
+-				"THERMAL",
+-				"GFX_PER_CU_CG",
+-				"RM",
+-				"DCEFCLK_DS",
+-				"ACDC",
+-				"VR0HOT",
+-				"VR1HOT",
+-				"FW_CTF",
+-				"LED_DISPLAY",
+-				"FAN_CONTROL",
+-				"GFX_EDC",
+-				"GFXOFF",
+-				"CG",
+-				"FCLK_DPM",
+-				"FCLK_DS",
+-				"MP1CLK_DS",
+-				"MP0CLK_DS",
+-				"XGMI",
+-				"ECC"};
+-	static const char *output_title[] = {
+-				"FEATURES",
+-				"BITMASK",
+-				"ENABLEMENT"};
+-	uint64_t features_enabled;
+-	int i;
+-	int ret = 0;
+-	int size = 0;
+-
+-	ret = vega20_get_enabled_smc_features(smu, &features_enabled);
+-	if (ret)
+-		return ret;
+-
+-	size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
+-	size += sprintf(buf + size, "%-19s %-22s %s\n",
+-				output_title[0],
+-				output_title[1],
+-				output_title[2]);
+-	for (i = 0; i < GNLD_FEATURES_MAX; i++) {
+-		size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
+-					ppfeature_name[i],
+-					1ULL << i,
+-					(features_enabled & (1ULL << i)) ? "Y" : "N");
+-	}
+-
+-	return size;
+-}
+-
+-static int vega20_set_ppfeature_status(struct smu_context *smu, uint64_t new_ppfeature_masks)
+-{
+-	uint64_t features_enabled;
+-	uint64_t features_to_enable;
+-	uint64_t features_to_disable;
+-	int ret = 0;
+-
+-	if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
+-		return -EINVAL;
+-
+-	ret = vega20_get_enabled_smc_features(smu, &features_enabled);
+-	if (ret)
+-		return ret;
+-
+-	features_to_disable =
+-		features_enabled & ~new_ppfeature_masks;
+-	features_to_enable =
+-		~features_enabled & new_ppfeature_masks;
+-
+-	pr_debug("features_to_disable 0x%llx\n", features_to_disable);
+-	pr_debug("features_to_enable 0x%llx\n", features_to_enable);
+-
+-	if (features_to_disable) {
+-		ret = vega20_enable_smc_features(smu, false, features_to_disable);
+-		if (ret)
+-			return ret;
+-	}
+-
+-	if (features_to_enable) {
+-		ret = vega20_enable_smc_features(smu, true, features_to_enable);
+-		if (ret)
+-			return ret;
+-	}
+-
+-	return 0;
+-}
+-
+ static bool vega20_is_dpm_running(struct smu_context *smu)
+ {
+ 	int ret = 0;
+@@ -3311,8 +3160,6 @@ static const struct pptable_funcs vega20_ppt_funcs = {
+ 	.force_dpm_limit_value = vega20_force_dpm_limit_value,
+ 	.unforce_dpm_levels = vega20_unforce_dpm_levels,
+ 	.get_profiling_clk_mask = vega20_get_profiling_clk_mask,
+-	.set_ppfeature_status = vega20_set_ppfeature_status,
+-	.get_ppfeature_status = vega20_get_ppfeature_status,
+ 	.is_dpm_running = vega20_is_dpm_running,
+ 	.set_thermal_fan_table = vega20_set_thermal_fan_table,
+ 	.get_fan_speed_percent = vega20_get_fan_speed_percent,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3150-drm-amdgpu-gfx10-update-golden-settings-for-navi14.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3150-drm-amdgpu-gfx10-update-golden-settings-for-navi14.patch
new file mode 100644
index 00000000..ebcb1567
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3150-drm-amdgpu-gfx10-update-golden-settings-for-navi14.patch
@@ -0,0 +1,28 @@
+From 690da05c6c50d1895fa1992ac9514d189de5274c Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 26 Jul 2019 14:14:15 -0500
+Subject: [PATCH 3150/4256] drm/amdgpu/gfx10: update golden settings for navi14
+
+Updated settings for hw team.
+
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 3df1e6212123..8f4af2c49cf6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -138,7 +138,6 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
+-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000043),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3151-drm-amd-amdgpu-vcn_v2_0-Move-VCN-2.0-specific-dec-ri.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3151-drm-amd-amdgpu-vcn_v2_0-Move-VCN-2.0-specific-dec-ri.patch
new file mode 100644
index 00000000..0d2eb534
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3151-drm-amd-amdgpu-vcn_v2_0-Move-VCN-2.0-specific-dec-ri.patch
@@ -0,0 +1,68 @@
+From aa2985a982cbdb1c8b8ecfe91f401d4a5afab3a0 Mon Sep 17 00:00:00 2001
+From: Thong Thai <thong.thai@amd.com>
+Date: Thu, 25 Jul 2019 11:26:56 -0400
+Subject: [PATCH 3151/4256] drm/amd/amdgpu/vcn_v2_0: Move VCN 2.0 specific dec
+ ring test to vcn_v2_0
+
+VCN 2.0 firmware now requires a packet start command to be sent before
+any other decode ring buffer command.
+
+Signed-off-by: Thong Thai <thong.thai@amd.com>
+Reviewed-by: Leo Liu <leo.liu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 32 ++++++++++++++++++++++++++-
+ 1 file changed, 31 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+index 800db1f297f6..7528b1b562e1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+@@ -2092,6 +2092,36 @@ static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
+ 	return 0;
+ }
+ 
++static int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	uint32_t tmp = 0;
++	unsigned i;
++	int r;
++
++	WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
++	r = amdgpu_ring_alloc(ring, 4);
++	if (r)
++		return r;
++	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
++	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
++	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
++	amdgpu_ring_write(ring, 0xDEADBEEF);
++	amdgpu_ring_commit(ring);
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
++		if (tmp == 0xDEADBEEF)
++			break;
++		DRM_UDELAY(1);
++	}
++
++	if (i >= adev->usec_timeout)
++		r = -ETIMEDOUT;
++
++	return r;
++}
++
++
+ static int vcn_v2_0_set_powergating_state(void *handle,
+ 					  enum amd_powergating_state state)
+ {
+@@ -2155,7 +2185,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
+ 	.emit_ib = vcn_v2_0_dec_ring_emit_ib,
+ 	.emit_fence = vcn_v2_0_dec_ring_emit_fence,
+ 	.emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
+-	.test_ring = amdgpu_vcn_dec_ring_test_ring,
++	.test_ring = vcn_v2_0_dec_ring_test_ring,
+ 	.test_ib = amdgpu_vcn_dec_ring_test_ib,
+ 	.insert_nop = vcn_v2_0_dec_ring_insert_nop,
+ 	.insert_start = vcn_v2_0_dec_ring_insert_start,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3152-drm-amdgpu-powerplay-provide-the-interface-to-disabl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3152-drm-amdgpu-powerplay-provide-the-interface-to-disabl.patch
new file mode 100644
index 00000000..5261fffe
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3152-drm-amdgpu-powerplay-provide-the-interface-to-disabl.patch
@@ -0,0 +1,156 @@
+From be181b4de5913347626303efc0e6ad704e5fccfc Mon Sep 17 00:00:00 2001
+From: Kenneth Feng <kenneth.feng@amd.com>
+Date: Mon, 29 Jul 2019 17:51:55 +0800
+Subject: [PATCH 3152/4256] drm/amdgpu/powerplay: provide the interface to
+ disable uclk switch for DAL
+
+provide the interface for DAL to disable uclk switch on navi10.
+in this case, the uclk will be fixed to maximum.
+this is a workaround when display configuration causes underflow issue.
+
+Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c  | 14 +++++++++++
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  5 ++++
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 25 +++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     |  7 ++++++
+ 4 files changed, 51 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+index 7bc7abcf3db1..583f8fbb9027 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+@@ -802,6 +802,19 @@ enum pp_smu_status pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz)
+ 	return PP_SMU_RESULT_OK;
+ }
+ 
++enum pp_smu_status pp_nv_set_pstate_handshake_support(
++	struct pp_smu *pp, BOOLEAN pstate_handshake_supported)
++{
++	const struct dc_context *ctx = pp->dm;
++	struct amdgpu_device *adev = ctx->driver_context;
++	struct smu_context *smu = &adev->smu;
++
++	if (smu_display_disable_memory_clock_switch(smu, !pstate_handshake_supported))
++		return PP_SMU_RESULT_FAIL;
++
++	return PP_SMU_RESULT_OK;
++}
++
+ enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
+ 		enum pp_smu_nv_clock_id clock_id, int mhz)
+ {
+@@ -917,6 +930,7 @@ void dm_pp_get_funcs(
+ 		funcs->nv_funcs.get_maximum_sustainable_clocks = pp_nv_get_maximum_sustainable_clocks;
+ 		/*todo  compare data with window driver */
+ 		funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
++		funcs->nv_funcs.set_pstate_handshake_support = pp_nv_set_pstate_handshake_support;
+ 		break;
+ #endif
+ 	default:
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index ac9e9d5d8a5c..fcd0db362977 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -365,6 +365,8 @@ struct smu_context
+ #define WATERMARKS_EXIST	(1 << 0)
+ #define WATERMARKS_LOADED	(1 << 1)
+ 	uint32_t watermarks_bitmap;
++	uint32_t hard_min_uclk_req_from_dal;
++	bool disable_uclk_switch;
+ 
+ 	uint32_t workload_mask;
+ 	uint32_t workload_prority[WORKLOAD_POLICY_MAX];
+@@ -446,6 +448,7 @@ struct pptable_funcs {
+ 	int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
+ 	int (*set_default_od_settings)(struct smu_context *smu, bool initialize);
+ 	int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
++	int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
+ };
+ 
+ struct smu_funcs
+@@ -695,6 +698,8 @@ struct smu_funcs
+ 	((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
+ #define smu_display_clock_voltage_request(smu, clock_req) \
+ 	((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
++#define smu_display_disable_memory_clock_switch(smu, disable_memory_clock_switch) \
++	((smu)->ppt_funcs->display_disable_memory_clock_switch ? (smu)->ppt_funcs->display_disable_memory_clock_switch((smu), (disable_memory_clock_switch)) : -EINVAL)
+ #define smu_get_dal_power_level(smu, clocks) \
+ 	((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
+ #define smu_get_perf_level(smu, designation, level) \
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 9dd96d8b8dd5..7706c8e0cfbe 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1492,6 +1492,30 @@ static int navi10_get_thermal_temperature_range(struct smu_context *smu,
+ 	return 0;
+ }
+ 
++static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
++						bool disable_memory_clock_switch)
++{
++	int ret = 0;
++	struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
++		(struct smu_11_0_max_sustainable_clocks *)
++			smu->smu_table.max_sustainable_clocks;
++	uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
++	uint32_t max_memory_clock = max_sustainable_clocks->uclock;
++
++	if(smu->disable_uclk_switch == disable_memory_clock_switch)
++		return 0;
++
++	if(disable_memory_clock_switch)
++		ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
++	else
++		ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
++
++	if(!ret)
++		smu->disable_uclk_switch = disable_memory_clock_switch;
++
++	return ret;
++}
++
+ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.tables_init = navi10_tables_init,
+ 	.alloc_dpm_context = navi10_allocate_dpm_context,
+@@ -1528,6 +1552,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.get_uclk_dpm_states = navi10_get_uclk_dpm_states,
+ 	.set_performance_level = navi10_set_performance_level,
+ 	.get_thermal_temperature_range = navi10_get_thermal_temperature_range,
++	.display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
+ };
+ 
+ void navi10_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index caf02ea4a481..3457e06a5f70 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1310,16 +1310,23 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
+ 		if (ret)
+ 			goto failed;
+ 
++		if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
++			return 0;
++
+ 		clk_id = smu_clk_get_index(smu, clk_select);
+ 		if (clk_id < 0) {
+ 			ret = -EINVAL;
+ 			goto failed;
+ 		}
+ 
++
+ 		mutex_lock(&smu->mutex);
+ 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
+ 			(clk_id << 16) | clk_freq);
+ 		mutex_unlock(&smu->mutex);
++
++		if(clk_select == SMU_UCLK)
++			smu->hard_min_uclk_req_from_dal = clk_freq;
+ 	}
+ 
+ failed:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3153-drm-syncobj-fix-leaking-dma_fence-in-drm_syncobj_que.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3153-drm-syncobj-fix-leaking-dma_fence-in-drm_syncobj_que.patch
new file mode 100644
index 00000000..232f5008
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3153-drm-syncobj-fix-leaking-dma_fence-in-drm_syncobj_que.patch
@@ -0,0 +1,113 @@
+From 4352bbe79144d6293cab9514012b625a820207f9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Mon, 22 Jul 2019 14:56:25 +0200
+Subject: [PATCH 3153/4256] drm/syncobj: fix leaking dma_fence in
+ drm_syncobj_query_ioctl
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We need to check the context number instead if the previous sequence to detect
+an error and if an error is detected we need to drop the reference to the
+current fence or otherwise would leak it.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+Fixes: 27b575a9aa2f ("drm/syncobj: add timeline payload query ioctl v6")
+Link: https://patchwork.freedesktop.org/patch/319123/
+---
+ drivers/gpu/drm/drm_syncobj.c | 62 +++++++++++++++++++++++++++++++++++
+ include/uapi/drm/drm.h        |  7 ++++
+ 2 files changed, 69 insertions(+)
+
+diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
+index 74482832c759..abda0a01d8dc 100644
+--- a/drivers/gpu/drm/drm_syncobj.c
++++ b/drivers/gpu/drm/drm_syncobj.c
+@@ -1069,3 +1069,65 @@ drm_syncobj_signal_ioctl(struct drm_device *dev, void *data,
+ 
+ 	return ret;
+ }
++
++int drm_syncobj_query_ioctl(struct drm_device *dev, void *data,
++                            struct drm_file *file_private)
++{
++        struct drm_syncobj_timeline_array *args = data;
++        struct drm_syncobj **syncobjs;
++        uint64_t __user *points = u64_to_user_ptr(args->points);
++        uint32_t i;
++        int ret;
++
++        if (!drm_core_check_feature(dev, DRIVER_SYNCOBJ))
++                return -ENODEV;
++
++        if (args->pad != 0)
++                return -EINVAL;
++
++        if (args->count_handles == 0)
++                return -EINVAL;
++
++        ret = drm_syncobj_array_find(file_private,
++                                     u64_to_user_ptr(args->handles),
++                                     args->count_handles,
++                                     &syncobjs);
++        if (ret < 0)
++                return ret;
++
++        for (i = 0; i < args->count_handles; i++) {
++                struct dma_fence_chain *chain;
++                struct dma_fence *fence;
++                uint64_t point;
++
++                fence = drm_syncobj_fence_get(syncobjs[i]);
++                chain = to_dma_fence_chain(fence);
++                if (chain) {
++                        struct dma_fence *iter, *last_signaled = NULL;
++
++                        dma_fence_chain_for_each(iter, fence) {
++                                if (iter->context != fence->context) {
++                                        dma_fence_put(iter);
++                                        /* It is most likely that timeline has
++                                         * unorder points. */
++                                        break;
++                                }
++                                dma_fence_put(last_signaled);
++                                last_signaled = dma_fence_get(iter);
++                        }
++                        point = dma_fence_is_signaled(last_signaled) ?
++                                last_signaled->seqno :
++                                to_dma_fence_chain(last_signaled)->prev_seqno;
++                        dma_fence_put(last_signaled);
++                } else {
++                        point = 0;
++                }
++                ret = copy_to_user(&points[i], &point, sizeof(uint64_t));
++                ret = ret ? -EFAULT : 0;
++                if (ret)
++                        break;
++        }
++        drm_syncobj_array_free(syncobjs, args->count_handles);
++
++        return ret;
++}
+diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
+index 300f336633f2..c18616d7fcd5 100644
+--- a/include/uapi/drm/drm.h
++++ b/include/uapi/drm/drm.h
+@@ -753,6 +753,13 @@ struct drm_syncobj_array {
+ 	__u32 pad;
+ };
+ 
++struct drm_syncobj_timeline_array {
++        __u64 handles;
++        __u64 points;
++        __u32 count_handles;
++        __u32 pad;
++};
++
+ /* Query current scanout sequence number */
+ struct drm_crtc_get_sequence {
+ 	__u32 crtc_id;		/* requested crtc_id */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3154-drm-amdgpu-fix-error-handling-in-amdgpu_cs_process_f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3154-drm-amdgpu-fix-error-handling-in-amdgpu_cs_process_f.patch
new file mode 100644
index 00000000..aec8e875
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3154-drm-amdgpu-fix-error-handling-in-amdgpu_cs_process_f.patch
@@ -0,0 +1,67 @@
+From 9f1b02fbe6751f968b493cae1e8b31ef36490d05 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Tue, 30 Jul 2019 11:17:03 +0200
+Subject: [PATCH 3154/4256] drm/amdgpu: fix error handling in
+ amdgpu_cs_process_fence_dep
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We always need to drop the ctx reference and should check
+for errors first and then dereference the fence pointer.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 26 ++++++++++++--------------
+ 1 file changed, 12 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+index fe2901d470d5..e745432315be 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+@@ -1035,29 +1035,27 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
+ 			return r;
+ 		}
+ 
+-		fence = amdgpu_ctx_get_fence(ctx, entity,
+-					     deps[i].handle);
++		fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
++		amdgpu_ctx_put(ctx);
++
++		if (IS_ERR(fence))
++			return PTR_ERR(fence);
++		else if (!fence)
++			continue;
+ 
+ 		if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
+-			struct drm_sched_fence *s_fence = to_drm_sched_fence(fence);
++			struct drm_sched_fence *s_fence;
+ 			struct dma_fence *old = fence;
+ 
++			s_fence = to_drm_sched_fence(fence);
+ 			fence = dma_fence_get(&s_fence->scheduled);
+ 			dma_fence_put(old);
+ 		}
+ 
+-		if (IS_ERR(fence)) {
+-			r = PTR_ERR(fence);
+-			amdgpu_ctx_put(ctx);
++		r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
++		dma_fence_put(fence);
++		if (r)
+ 			return r;
+-		} else if (fence) {
+-			r = amdgpu_sync_fence(p->adev, &p->job->sync, fence,
+-					true);
+-			dma_fence_put(fence);
+-			amdgpu_ctx_put(ctx);
+-			if (r)
+-				return r;
+-		}
+ 	}
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3155-dma-buf-add-dma_fence_chain_for_each_unwrap-helper.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3155-dma-buf-add-dma_fence_chain_for_each_unwrap-helper.patch
new file mode 100644
index 00000000..7a313a76
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3155-dma-buf-add-dma_fence_chain_for_each_unwrap-helper.patch
@@ -0,0 +1,104 @@
+From 64652321fc6b7ce743e7184a66bbe7a053862024 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Mon, 22 Jul 2019 14:20:47 +0200
+Subject: [PATCH 3155/4256] dma-buf: add dma_fence_chain_for_each_unwrap helper
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add another for_each helper to iterate over all the fences in a chain
+with unwrapping each chain node.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/dma-buf/dma-fence-chain.c | 11 ++++------
+ include/linux/dma-fence-chain.h   | 34 +++++++++++++++++++++++++++++++
+ 2 files changed, 38 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-fence-chain.c
+index c729f98a7bd3..c13ddc62107b 100644
+--- a/drivers/dma-buf/dma-fence-chain.c
++++ b/drivers/dma-buf/dma-fence-chain.c
+@@ -151,12 +151,10 @@ static void dma_fence_chain_cb(struct dma_fence *f, struct dma_fence_cb *cb)
+ static bool dma_fence_chain_enable_signaling(struct dma_fence *fence)
+ {
+ 	struct dma_fence_chain *head = to_dma_fence_chain(fence);
++	struct dma_fence *f;
+ 
+ 	dma_fence_get(&head->base);
+-	dma_fence_chain_for_each(fence, &head->base) {
+-		struct dma_fence_chain *chain = to_dma_fence_chain(fence);
+-		struct dma_fence *f = chain ? chain->fence : fence;
+-
++	dma_fence_chain_for_each_unwrap(f, fence, &head->base) {
+ 		dma_fence_get(f);
+ 		if (!dma_fence_add_callback(f, &head->cb, dma_fence_chain_cb)) {
+ 			dma_fence_put(fence);
+@@ -170,10 +168,9 @@ static bool dma_fence_chain_enable_signaling(struct dma_fence *fence)
+ 
+ static bool dma_fence_chain_signaled(struct dma_fence *fence)
+ {
+-	dma_fence_chain_for_each(fence, fence) {
+-		struct dma_fence_chain *chain = to_dma_fence_chain(fence);
+-		struct dma_fence *f = chain ? chain->fence : fence;
++	struct dma_fence *f;
+ 
++	dma_fence_chain_for_each_unwrap(f, fence, fence) {
+ 		if (!dma_fence_is_signaled(f)) {
+ 			dma_fence_put(fence);
+ 			return false;
+diff --git a/include/linux/dma-fence-chain.h b/include/linux/dma-fence-chain.h
+index 934a442db8ac..7466d7b8837e 100644
+--- a/include/linux/dma-fence-chain.h
++++ b/include/linux/dma-fence-chain.h
+@@ -59,6 +59,24 @@ to_dma_fence_chain(struct dma_fence *fence)
+ 	return container_of(fence, struct dma_fence_chain, base);
+ }
+ 
++/**
++ * dma_fence_chain_unwrap - unwrap chain node
++ * @fence: fence which could be a chain node
++ *
++ * If the paramter is a chain node return the cotained fence, otherwise return
++ * the parameter itself.
++ */
++static inline struct dma_fence *
++dma_fence_chain_unwrap(struct dma_fence *fence)
++{
++	struct dma_fence_chain *chain = to_dma_fence_chain(fence);
++
++	if (!chain)
++		return fence;
++
++	return chain->fence;
++}
++
+ /**
+  * dma_fence_chain_for_each - iterate over all fences in chain
+  * @iter: current fence
+@@ -71,6 +89,22 @@ to_dma_fence_chain(struct dma_fence *fence)
+ 	for (iter = dma_fence_get(head); iter; \
+ 	     iter = dma_fence_chain_walk(iter))
+ 
++/**
++ * dma_fence_chain_for_each_unwrap - iterate over all unwrapped fences in chain
++ * @fence: the unwrapped fence
++ * @iter: current fence
++ * @head: starting point
++ *
++ * Iterate over all fences in the chain with unwrapping. We keep a reference to
++ * the current fence while inside the loop which must be dropped when breaking
++ * out.
++ */
++#define dma_fence_chain_for_each_unwrap(fence, iter, head)	\
++	for (iter = dma_fence_get(head),			\
++	     fence = dma_fence_chain_unwrap(iter);		\
++	     iter; iter = dma_fence_chain_walk(iter),		\
++	     fence = dma_fence_chain_unwrap(iter))
++
+ struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence);
+ int dma_fence_chain_find_seqno(struct dma_fence **pfence, uint64_t seqno);
+ void dma_fence_chain_init(struct dma_fence_chain *chain,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3156-dma-buf-add-dma_fence_chain_remove_fence.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3156-dma-buf-add-dma_fence_chain_remove_fence.patch
new file mode 100644
index 00000000..02cc3b87
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3156-dma-buf-add-dma_fence_chain_remove_fence.patch
@@ -0,0 +1,208 @@
+From 0e942c4a21d90c92b458829ca0ffd708fbf5dd26 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Fri, 28 Jun 2019 09:43:38 +0200
+Subject: [PATCH 3156/4256] dma-buf: add dma_fence_chain_remove_fence
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add helpers to remove a fence from a dma_fence_chain.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/dma-buf/dma-fence-chain.c | 133 ++++++++++++++++++++++++------
+ include/linux/dma-fence-chain.h   |   1 +
+ 2 files changed, 107 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-fence-chain.c
+index c13ddc62107b..58fc68ed5df9 100644
+--- a/drivers/dma-buf/dma-fence-chain.c
++++ b/drivers/dma-buf/dma-fence-chain.c
+@@ -20,22 +20,67 @@
+ static bool dma_fence_chain_enable_signaling(struct dma_fence *fence);
+ 
+ /**
+- * dma_fence_chain_get_prev - use RCU to get a reference to the previous fence
+- * @chain: chain node to get the previous node from
++ * dma_fence_chain_get - use RCU to get a reference to a fence
++ * @pfence: rcu protected fence pointer
+  *
+- * Use dma_fence_get_rcu_safe to get a reference to the previous fence of the
+- * chain node.
++ * Use dma_fence_get_rcu_safe to get a reference to a fence in a chain.
+  */
+-static struct dma_fence *dma_fence_chain_get_prev(struct dma_fence_chain *chain)
++static struct dma_fence *dma_fence_chain_get(struct dma_fence __rcu **pfence)
+ {
+ 	struct dma_fence *prev;
+ 
+ 	rcu_read_lock();
+-	prev = dma_fence_get_rcu_safe(&chain->prev);
++	prev = dma_fence_get_rcu_safe(pfence);
+ 	rcu_read_unlock();
+ 	return prev;
+ }
+ 
++/**
++ * dma_fence_chain_is_dead - check if dma_fence_chain should be unlinked
++ * @fence: fence to check
++ *
++ * If @fence is a dma_fence_chain node we check if the contained fence is
++ * signaled, otherwise we check if just this fence is signaled.
++ */
++static bool dma_fence_chain_is_dead(struct dma_fence *fence)
++{
++	struct dma_fence_chain *chain = to_dma_fence_chain(fence);
++
++	if (chain)
++		return dma_fence_is_signaled(chain->fence);
++
++	return dma_fence_is_signaled(fence);
++}
++
++/**
++ * dma_fence_chain_unlink - make an RCU safe removal of a chain node
++ * @pfence: the pointer to replace
++ * @old: the current value of that pointer
++ *
++ * Tries to replace the RCU protected value of pointer @pfence with the previous
++ * fence in the chain. The reference to the old fence is dropped no matter if
++ * the exchange was succesfully or not.
++ */
++static void dma_fence_chain_unlink(struct dma_fence __rcu **pfence,
++				   struct dma_fence *old)
++{
++	struct dma_fence *replacement, *tmp;
++	struct dma_fence_chain *chain;
++
++	chain = to_dma_fence_chain(old);
++	if (chain)
++		replacement = dma_fence_chain_get(&chain->prev);
++	else
++		replacement = NULL;
++
++	tmp = cmpxchg((void **)pfence, (void *)current, (void *)replacement);
++	if (tmp == old)
++		dma_fence_put(tmp);
++	else
++		dma_fence_put(replacement);
++	dma_fence_put(old);
++}
++
+ /**
+  * dma_fence_chain_walk - chain walking function
+  * @fence: current chain node
+@@ -46,8 +91,8 @@ static struct dma_fence *dma_fence_chain_get_prev(struct dma_fence_chain *chain)
+  */
+ struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence)
+ {
+-	struct dma_fence_chain *chain, *prev_chain;
+-	struct dma_fence *prev, *replacement, *tmp;
++	struct dma_fence_chain *chain;
++	struct dma_fence *prev;
+ 
+ 	chain = to_dma_fence_chain(fence);
+ 	if (!chain) {
+@@ -55,27 +100,12 @@ struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence)
+ 		return NULL;
+ 	}
+ 
+-	while ((prev = dma_fence_chain_get_prev(chain))) {
+-
+-		prev_chain = to_dma_fence_chain(prev);
+-		if (prev_chain) {
+-			if (!dma_fence_is_signaled(prev_chain->fence))
+-				break;
+-
+-			replacement = dma_fence_chain_get_prev(prev_chain);
+-		} else {
+-			if (!dma_fence_is_signaled(prev))
+-				break;
++	while ((prev = dma_fence_chain_get(&chain->prev))) {
+ 
+-			replacement = NULL;
+-		}
++		if (!dma_fence_chain_is_dead(prev))
++			break;
+ 
+-		tmp = cmpxchg((void **)&chain->prev, (void *)prev, (void *)replacement);
+-		if (tmp == prev)
+-			dma_fence_put(tmp);
+-		else
+-			dma_fence_put(replacement);
+-		dma_fence_put(prev);
++		dma_fence_chain_unlink(&chain->prev, prev);
+ 	}
+ 
+ 	dma_fence_put(fence);
+@@ -116,6 +146,55 @@ int dma_fence_chain_find_seqno(struct dma_fence **pfence, uint64_t seqno)
+ }
+ EXPORT_SYMBOL(dma_fence_chain_find_seqno);
+ 
++/**
++ * dma_fence_chain_remove_fences - remove fences from a chain
++ * @pfence: pointer to the chain node where to start
++ * @cb: callback to decide if fence should be removed
++ * @data: data for the callback
++ *
++ * Iterate over the chain nodes until we can be sure that there are no more
++ * fences which should be removed.
++ *
++ * To remove a node we need to iterate at least twice to make sure we doesn't
++ * collide with concurrent operations.
++ */
++void dma_fence_chain_remove_fence(struct dma_fence __rcu **pfence,
++				  bool (*cb)(struct dma_fence *f, void *data),
++				  void *data)
++{
++	struct dma_fence_chain *chain = NULL;
++	struct dma_fence **prev, *fence;
++
++retry:
++	prev = pfence;
++	while ((fence = dma_fence_chain_get(prev))) {
++		dma_fence_put(&chain->base);
++		chain = to_dma_fence_chain(fence);
++
++		if (dma_fence_chain_is_dead(fence)) {
++			dma_fence_chain_unlink(prev, fence);
++			continue;
++		}
++
++		if (cb(chain ? chain->fence : fence, data)) {
++			dma_fence_chain_unlink(prev, fence);
++			/* Restart the search cause it can be that the previous
++			 * chain is unlinked just as we try to unlink this one.
++			 */
++			goto retry;
++		}
++
++		if (!chain) {
++			dma_fence_put(fence);
++			break;
++		}
++
++		prev = &chain->prev;
++	}
++	dma_fence_put(&chain->base);
++}
++EXPORT_SYMBOL(dma_fence_chain_remove_fence);
++
+ static const char *dma_fence_chain_get_driver_name(struct dma_fence *fence)
+ {
+         return "dma_fence_chain";
+diff --git a/include/linux/dma-fence-chain.h b/include/linux/dma-fence-chain.h
+index 7466d7b8837e..694f35fb2b5e 100644
+--- a/include/linux/dma-fence-chain.h
++++ b/include/linux/dma-fence-chain.h
+@@ -107,6 +107,7 @@ dma_fence_chain_unwrap(struct dma_fence *fence)
+ 
+ struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence);
+ int dma_fence_chain_find_seqno(struct dma_fence **pfence, uint64_t seqno);
++void dma_fence_chain_purge_ctx(struct dma_fence **pfence, uint64_t ctx);
+ void dma_fence_chain_init(struct dma_fence_chain *chain,
+ 			  struct dma_fence *prev,
+ 			  struct dma_fence *fence,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3157-drm-amdgpu-fix-a-potential-information-leaking-bug.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3157-drm-amdgpu-fix-a-potential-information-leaking-bug.patch
new file mode 100644
index 00000000..0f072a39
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3157-drm-amdgpu-fix-a-potential-information-leaking-bug.patch
@@ -0,0 +1,44 @@
+From 9bf6dab4e3d5582d96da3ab6399b32a74c50ec6f Mon Sep 17 00:00:00 2001
+From: Wang Xiayang <xywang.sjtu@sjtu.edu.cn>
+Date: Sat, 27 Jul 2019 17:30:30 +0800
+Subject: [PATCH 3157/4256] drm/amdgpu: fix a potential information leaking bug
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Coccinelle reports a path that the array "data" is never initialized.
+The path skips the checks in the conditional branches when either
+of callback functions, read_wave_vgprs and read_wave_sgprs, is not
+registered. Later, the uninitialized "data" array is read
+in the while-loop below and passed to put_user().
+
+Fix the path by allocating the array with kcalloc().
+
+The patch is simplier than adding a fall-back branch that explicitly
+calls memset(data, 0, ...). Also it does not need the multiplication
+1024*sizeof(*data) as the size parameter for memset() though there is
+no risk of integer overflow.
+
+Signed-off-by: Wang Xiayang <xywang.sjtu@sjtu.edu.cn>
+Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+index 59849ed9797d..79c8cf61c577 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+@@ -704,7 +704,7 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
+ 	thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
+ 	bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
+ 
+-	data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
++	data = kcalloc(1024, sizeof(*data), GFP_KERNEL);
+ 	if (!data)
+ 		return -ENOMEM;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3158-Revert-accidential-push.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3158-Revert-accidential-push.patch
new file mode 100644
index 00000000..915e55ec
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3158-Revert-accidential-push.patch
@@ -0,0 +1,283 @@
+From 2d58eecf8ce15aaeb210dc2d4e42e136c4fa5330 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Tue, 30 Jul 2019 14:01:11 +0200
+Subject: [PATCH 3158/4256] Revert accidential push
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This reverts commit 51b7e1515aa2d9ea34cd8f629667cc99b3114e99.
+This reverts commit 77012ddc093927f3cd0a0826b4b6eb13df3489dd.
+This reverts commit b71ea8f524f88de51be73fd74a111e2f3aa4d119.
+
+Accidentially pushed.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/dma-buf/dma-fence-chain.c | 144 +++++++-----------------------
+ include/linux/dma-fence-chain.h   |  35 --------
+ 2 files changed, 34 insertions(+), 145 deletions(-)
+
+diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-fence-chain.c
+index 58fc68ed5df9..c729f98a7bd3 100644
+--- a/drivers/dma-buf/dma-fence-chain.c
++++ b/drivers/dma-buf/dma-fence-chain.c
+@@ -20,67 +20,22 @@
+ static bool dma_fence_chain_enable_signaling(struct dma_fence *fence);
+ 
+ /**
+- * dma_fence_chain_get - use RCU to get a reference to a fence
+- * @pfence: rcu protected fence pointer
++ * dma_fence_chain_get_prev - use RCU to get a reference to the previous fence
++ * @chain: chain node to get the previous node from
+  *
+- * Use dma_fence_get_rcu_safe to get a reference to a fence in a chain.
++ * Use dma_fence_get_rcu_safe to get a reference to the previous fence of the
++ * chain node.
+  */
+-static struct dma_fence *dma_fence_chain_get(struct dma_fence __rcu **pfence)
++static struct dma_fence *dma_fence_chain_get_prev(struct dma_fence_chain *chain)
+ {
+ 	struct dma_fence *prev;
+ 
+ 	rcu_read_lock();
+-	prev = dma_fence_get_rcu_safe(pfence);
++	prev = dma_fence_get_rcu_safe(&chain->prev);
+ 	rcu_read_unlock();
+ 	return prev;
+ }
+ 
+-/**
+- * dma_fence_chain_is_dead - check if dma_fence_chain should be unlinked
+- * @fence: fence to check
+- *
+- * If @fence is a dma_fence_chain node we check if the contained fence is
+- * signaled, otherwise we check if just this fence is signaled.
+- */
+-static bool dma_fence_chain_is_dead(struct dma_fence *fence)
+-{
+-	struct dma_fence_chain *chain = to_dma_fence_chain(fence);
+-
+-	if (chain)
+-		return dma_fence_is_signaled(chain->fence);
+-
+-	return dma_fence_is_signaled(fence);
+-}
+-
+-/**
+- * dma_fence_chain_unlink - make an RCU safe removal of a chain node
+- * @pfence: the pointer to replace
+- * @old: the current value of that pointer
+- *
+- * Tries to replace the RCU protected value of pointer @pfence with the previous
+- * fence in the chain. The reference to the old fence is dropped no matter if
+- * the exchange was succesfully or not.
+- */
+-static void dma_fence_chain_unlink(struct dma_fence __rcu **pfence,
+-				   struct dma_fence *old)
+-{
+-	struct dma_fence *replacement, *tmp;
+-	struct dma_fence_chain *chain;
+-
+-	chain = to_dma_fence_chain(old);
+-	if (chain)
+-		replacement = dma_fence_chain_get(&chain->prev);
+-	else
+-		replacement = NULL;
+-
+-	tmp = cmpxchg((void **)pfence, (void *)current, (void *)replacement);
+-	if (tmp == old)
+-		dma_fence_put(tmp);
+-	else
+-		dma_fence_put(replacement);
+-	dma_fence_put(old);
+-}
+-
+ /**
+  * dma_fence_chain_walk - chain walking function
+  * @fence: current chain node
+@@ -91,8 +46,8 @@ static void dma_fence_chain_unlink(struct dma_fence __rcu **pfence,
+  */
+ struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence)
+ {
+-	struct dma_fence_chain *chain;
+-	struct dma_fence *prev;
++	struct dma_fence_chain *chain, *prev_chain;
++	struct dma_fence *prev, *replacement, *tmp;
+ 
+ 	chain = to_dma_fence_chain(fence);
+ 	if (!chain) {
+@@ -100,12 +55,27 @@ struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence)
+ 		return NULL;
+ 	}
+ 
+-	while ((prev = dma_fence_chain_get(&chain->prev))) {
++	while ((prev = dma_fence_chain_get_prev(chain))) {
+ 
+-		if (!dma_fence_chain_is_dead(prev))
+-			break;
++		prev_chain = to_dma_fence_chain(prev);
++		if (prev_chain) {
++			if (!dma_fence_is_signaled(prev_chain->fence))
++				break;
++
++			replacement = dma_fence_chain_get_prev(prev_chain);
++		} else {
++			if (!dma_fence_is_signaled(prev))
++				break;
+ 
+-		dma_fence_chain_unlink(&chain->prev, prev);
++			replacement = NULL;
++		}
++
++		tmp = cmpxchg((void **)&chain->prev, (void *)prev, (void *)replacement);
++		if (tmp == prev)
++			dma_fence_put(tmp);
++		else
++			dma_fence_put(replacement);
++		dma_fence_put(prev);
+ 	}
+ 
+ 	dma_fence_put(fence);
+@@ -146,55 +116,6 @@ int dma_fence_chain_find_seqno(struct dma_fence **pfence, uint64_t seqno)
+ }
+ EXPORT_SYMBOL(dma_fence_chain_find_seqno);
+ 
+-/**
+- * dma_fence_chain_remove_fences - remove fences from a chain
+- * @pfence: pointer to the chain node where to start
+- * @cb: callback to decide if fence should be removed
+- * @data: data for the callback
+- *
+- * Iterate over the chain nodes until we can be sure that there are no more
+- * fences which should be removed.
+- *
+- * To remove a node we need to iterate at least twice to make sure we doesn't
+- * collide with concurrent operations.
+- */
+-void dma_fence_chain_remove_fence(struct dma_fence __rcu **pfence,
+-				  bool (*cb)(struct dma_fence *f, void *data),
+-				  void *data)
+-{
+-	struct dma_fence_chain *chain = NULL;
+-	struct dma_fence **prev, *fence;
+-
+-retry:
+-	prev = pfence;
+-	while ((fence = dma_fence_chain_get(prev))) {
+-		dma_fence_put(&chain->base);
+-		chain = to_dma_fence_chain(fence);
+-
+-		if (dma_fence_chain_is_dead(fence)) {
+-			dma_fence_chain_unlink(prev, fence);
+-			continue;
+-		}
+-
+-		if (cb(chain ? chain->fence : fence, data)) {
+-			dma_fence_chain_unlink(prev, fence);
+-			/* Restart the search cause it can be that the previous
+-			 * chain is unlinked just as we try to unlink this one.
+-			 */
+-			goto retry;
+-		}
+-
+-		if (!chain) {
+-			dma_fence_put(fence);
+-			break;
+-		}
+-
+-		prev = &chain->prev;
+-	}
+-	dma_fence_put(&chain->base);
+-}
+-EXPORT_SYMBOL(dma_fence_chain_remove_fence);
+-
+ static const char *dma_fence_chain_get_driver_name(struct dma_fence *fence)
+ {
+         return "dma_fence_chain";
+@@ -230,10 +151,12 @@ static void dma_fence_chain_cb(struct dma_fence *f, struct dma_fence_cb *cb)
+ static bool dma_fence_chain_enable_signaling(struct dma_fence *fence)
+ {
+ 	struct dma_fence_chain *head = to_dma_fence_chain(fence);
+-	struct dma_fence *f;
+ 
+ 	dma_fence_get(&head->base);
+-	dma_fence_chain_for_each_unwrap(f, fence, &head->base) {
++	dma_fence_chain_for_each(fence, &head->base) {
++		struct dma_fence_chain *chain = to_dma_fence_chain(fence);
++		struct dma_fence *f = chain ? chain->fence : fence;
++
+ 		dma_fence_get(f);
+ 		if (!dma_fence_add_callback(f, &head->cb, dma_fence_chain_cb)) {
+ 			dma_fence_put(fence);
+@@ -247,9 +170,10 @@ static bool dma_fence_chain_enable_signaling(struct dma_fence *fence)
+ 
+ static bool dma_fence_chain_signaled(struct dma_fence *fence)
+ {
+-	struct dma_fence *f;
++	dma_fence_chain_for_each(fence, fence) {
++		struct dma_fence_chain *chain = to_dma_fence_chain(fence);
++		struct dma_fence *f = chain ? chain->fence : fence;
+ 
+-	dma_fence_chain_for_each_unwrap(f, fence, fence) {
+ 		if (!dma_fence_is_signaled(f)) {
+ 			dma_fence_put(fence);
+ 			return false;
+diff --git a/include/linux/dma-fence-chain.h b/include/linux/dma-fence-chain.h
+index 694f35fb2b5e..934a442db8ac 100644
+--- a/include/linux/dma-fence-chain.h
++++ b/include/linux/dma-fence-chain.h
+@@ -59,24 +59,6 @@ to_dma_fence_chain(struct dma_fence *fence)
+ 	return container_of(fence, struct dma_fence_chain, base);
+ }
+ 
+-/**
+- * dma_fence_chain_unwrap - unwrap chain node
+- * @fence: fence which could be a chain node
+- *
+- * If the paramter is a chain node return the cotained fence, otherwise return
+- * the parameter itself.
+- */
+-static inline struct dma_fence *
+-dma_fence_chain_unwrap(struct dma_fence *fence)
+-{
+-	struct dma_fence_chain *chain = to_dma_fence_chain(fence);
+-
+-	if (!chain)
+-		return fence;
+-
+-	return chain->fence;
+-}
+-
+ /**
+  * dma_fence_chain_for_each - iterate over all fences in chain
+  * @iter: current fence
+@@ -89,25 +71,8 @@ dma_fence_chain_unwrap(struct dma_fence *fence)
+ 	for (iter = dma_fence_get(head); iter; \
+ 	     iter = dma_fence_chain_walk(iter))
+ 
+-/**
+- * dma_fence_chain_for_each_unwrap - iterate over all unwrapped fences in chain
+- * @fence: the unwrapped fence
+- * @iter: current fence
+- * @head: starting point
+- *
+- * Iterate over all fences in the chain with unwrapping. We keep a reference to
+- * the current fence while inside the loop which must be dropped when breaking
+- * out.
+- */
+-#define dma_fence_chain_for_each_unwrap(fence, iter, head)	\
+-	for (iter = dma_fence_get(head),			\
+-	     fence = dma_fence_chain_unwrap(iter);		\
+-	     iter; iter = dma_fence_chain_walk(iter),		\
+-	     fence = dma_fence_chain_unwrap(iter))
+-
+ struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence);
+ int dma_fence_chain_find_seqno(struct dma_fence **pfence, uint64_t seqno);
+-void dma_fence_chain_purge_ctx(struct dma_fence **pfence, uint64_t ctx);
+ void dma_fence_chain_init(struct dma_fence_chain *chain,
+ 			  struct dma_fence *prev,
+ 			  struct dma_fence *fence,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3159-drm-amd-display-Embed-DCN2-SOC-bounding-box.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3159-drm-amd-display-Embed-DCN2-SOC-bounding-box.patch
new file mode 100644
index 00000000..a76cef42
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3159-drm-amd-display-Embed-DCN2-SOC-bounding-box.patch
@@ -0,0 +1,162 @@
+From 017e8e8e16a1527ce02507e8395482689b01783b Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 30 Jul 2019 09:08:34 -0400
+Subject: [PATCH 3159/4256] drm/amd/display: Embed DCN2 SOC bounding box
+
+[Why]
+In order to support uclk switching on NV10 the SOC bounding box
+needs to be updated.
+
+[How]
+We currently read the constants from the gpu info FW, but supporting
+workarounds in DC for different versions of the FW adds additional
+complexity to the codebase.
+
+NV10 has been released so it's cleanest to keep the bounding box and
+source code in sync by embedding the bounding box like we do for
+other ASICs.
+
+Fixes: 02316e963a5a ("drm/amd/display: Force uclk to max for every state")
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 114 +++++++++++++++++-
+ 1 file changed, 112 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 44537651f0a1..ff30f5cc4981 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -80,7 +80,7 @@
+ 
+ #include "amdgpu_socbb.h"
+ 
+-#define SOC_BOUNDING_BOX_VALID false
++#define SOC_BOUNDING_BOX_VALID true
+ #define DC_LOGGER_INIT(logger)
+ 
+ struct _vcs_dpi_ip_params_st dcn2_0_ip = {
+@@ -154,7 +154,117 @@ struct _vcs_dpi_ip_params_st dcn2_0_ip = {
+ 	.xfc_fill_constant_bytes = 0,
+ };
+ 
+-struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { 0 };
++struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
++	/* Defaults that get patched on driver load from firmware. */
++	.clock_limits = {
++			{
++				.state = 0,
++				.dcfclk_mhz = 560.0,
++				.fabricclk_mhz = 560.0,
++				.dispclk_mhz = 513.0,
++				.dppclk_mhz = 513.0,
++				.phyclk_mhz = 540.0,
++				.socclk_mhz = 560.0,
++				.dscclk_mhz = 171.0,
++				.dram_speed_mts = 8960.0,
++			},
++			{
++				.state = 1,
++				.dcfclk_mhz = 694.0,
++				.fabricclk_mhz = 694.0,
++				.dispclk_mhz = 642.0,
++				.dppclk_mhz = 642.0,
++				.phyclk_mhz = 600.0,
++				.socclk_mhz = 694.0,
++				.dscclk_mhz = 214.0,
++				.dram_speed_mts = 11104.0,
++			},
++			{
++				.state = 2,
++				.dcfclk_mhz = 875.0,
++				.fabricclk_mhz = 875.0,
++				.dispclk_mhz = 734.0,
++				.dppclk_mhz = 734.0,
++				.phyclk_mhz = 810.0,
++				.socclk_mhz = 875.0,
++				.dscclk_mhz = 245.0,
++				.dram_speed_mts = 14000.0,
++			},
++			{
++				.state = 3,
++				.dcfclk_mhz = 1000.0,
++				.fabricclk_mhz = 1000.0,
++				.dispclk_mhz = 1100.0,
++				.dppclk_mhz = 1100.0,
++				.phyclk_mhz = 810.0,
++				.socclk_mhz = 1000.0,
++				.dscclk_mhz = 367.0,
++				.dram_speed_mts = 16000.0,
++			},
++			{
++				.state = 4,
++				.dcfclk_mhz = 1200.0,
++				.fabricclk_mhz = 1200.0,
++				.dispclk_mhz = 1284.0,
++				.dppclk_mhz = 1284.0,
++				.phyclk_mhz = 810.0,
++				.socclk_mhz = 1200.0,
++				.dscclk_mhz = 428.0,
++				.dram_speed_mts = 16000.0,
++			},
++			/*Extra state, no dispclk ramping*/
++			{
++				.state = 5,
++				.dcfclk_mhz = 1200.0,
++				.fabricclk_mhz = 1200.0,
++				.dispclk_mhz = 1284.0,
++				.dppclk_mhz = 1284.0,
++				.phyclk_mhz = 810.0,
++				.socclk_mhz = 1200.0,
++				.dscclk_mhz = 428.0,
++				.dram_speed_mts = 16000.0,
++			},
++		},
++	.num_states = 5,
++	.sr_exit_time_us = 8.6,
++	.sr_enter_plus_exit_time_us = 10.9,
++	.urgent_latency_us = 4.0,
++	.urgent_latency_pixel_data_only_us = 4.0,
++	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
++	.urgent_latency_vm_data_only_us = 4.0,
++	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
++	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
++	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
++	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
++	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
++	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
++	.max_avg_sdp_bw_use_normal_percent = 40.0,
++	.max_avg_dram_bw_use_normal_percent = 40.0,
++	.writeback_latency_us = 12.0,
++	.ideal_dram_bw_after_urgent_percent = 40.0,
++	.max_request_size_bytes = 256,
++	.dram_channel_width_bytes = 2,
++	.fabric_datapath_to_dcn_data_return_bytes = 64,
++	.dcn_downspread_percent = 0.5,
++	.downspread_percent = 0.38,
++	.dram_page_open_time_ns = 50.0,
++	.dram_rw_turnaround_time_ns = 17.5,
++	.dram_return_buffer_per_channel_bytes = 8192,
++	.round_trip_ping_latency_dcfclk_cycles = 131,
++	.urgent_out_of_order_return_per_channel_bytes = 256,
++	.channel_interleave_bytes = 256,
++	.num_banks = 8,
++	.num_chans = 16,
++	.vmm_page_size_bytes = 4096,
++	.dram_clock_change_latency_us = 404.0,
++	.dummy_pstate_latency_us = 5.0,
++	.writeback_dram_clock_change_latency_us = 23.0,
++	.return_bus_width_bytes = 64,
++	.dispclk_dppclk_vco_speed_mhz = 3850,
++	.xfc_bus_transport_time_us = 20,
++	.xfc_xbuf_latency_tolerance_us = 4,
++	.use_urgent_burst_bw = 0
++};
+ 
+ 
+ #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3160-drm-amd-display-Support-uclk-switching-for-DCN2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3160-drm-amd-display-Support-uclk-switching-for-DCN2.patch
new file mode 100644
index 00000000..3d89b372
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3160-drm-amd-display-Support-uclk-switching-for-DCN2.patch
@@ -0,0 +1,78 @@
+From 4090dc5ab539ecba25b5ae156f34a32adb87b115 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 30 Jul 2019 09:45:33 -0400
+Subject: [PATCH 3160/4256] drm/amd/display: Support uclk switching for DCN2
+
+[Why]
+We were previously forcing the uclk for every state to max and reducing
+the switch time to prevent uclk switching from occuring. This workaround
+was previously needed in order to avoid hangs + underflow under certain
+display configurations.
+
+Now that DC has the proper fix complete we can drop the hacks and
+improve power for most display configurations.
+
+[How]
+We still need the function pointers hooked up to grab the real uclk
+states from pplib. The rest of the prior hack can be reverted.
+
+The key requirements here are really just DC support, updated firmware,
+and support for disabling p-state support when needed in pplib/smu.
+
+When these requirements are met uclk switching works without underflow
+or hangs.
+
+Fixes: 02316e963a5a ("drm/amd/display: Force uclk to max for every state")
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 10 ----------
+ 1 file changed, 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index ff30f5cc4981..42d3666f2037 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2817,9 +2817,6 @@ static void cap_soc_clocks(
+ 						&& max_clocks.uClockInKhz != 0)
+ 			bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
+ 
+-		// HACK: Force every uclk to max for now to "disable" uclk switching.
+-		bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
+-
+ 		if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
+ 						&& max_clocks.fabricClockInKhz != 0)
+ 			bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
+@@ -3035,8 +3032,6 @@ static bool init_soc_bounding_box(struct dc *dc,
+ 				le32_to_cpu(bb->vmm_page_size_bytes);
+ 		dcn2_0_soc.dram_clock_change_latency_us =
+ 				fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
+-		// HACK!! Lower uclock latency switch time so we don't switch
+-		dcn2_0_soc.dram_clock_change_latency_us = 10;
+ 		dcn2_0_soc.writeback_dram_clock_change_latency_us =
+ 				fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
+ 		dcn2_0_soc.return_bus_width_bytes =
+@@ -3078,7 +3073,6 @@ static bool init_soc_bounding_box(struct dc *dc,
+ 		struct pp_smu_nv_clock_table max_clocks = {0};
+ 		unsigned int uclk_states[8] = {0};
+ 		unsigned int num_states = 0;
+-		int i;
+ 		enum pp_smu_status status;
+ 		bool clock_limits_available = false;
+ 		bool uclk_states_available = false;
+@@ -3100,10 +3094,6 @@ static bool init_soc_bounding_box(struct dc *dc,
+ 			clock_limits_available = (status == PP_SMU_RESULT_OK);
+ 		}
+ 
+-		// HACK: Use the max uclk_states value for all elements.
+-		for (i = 0; i < num_states; i++)
+-			uclk_states[i] = uclk_states[num_states - 1];
+-
+ 		if (clock_limits_available && uclk_states_available && num_states)
+ 			update_bounding_box(dc, &dcn2_0_soc, &max_clocks, uclk_states, num_states);
+ 		else if (clock_limits_available)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3161-drm-amdkfd-Fix-gfx10-wave64-VGPR-context-restore.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3161-drm-amdkfd-Fix-gfx10-wave64-VGPR-context-restore.patch
new file mode 100644
index 00000000..4c019e1e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3161-drm-amdkfd-Fix-gfx10-wave64-VGPR-context-restore.patch
@@ -0,0 +1,53 @@
+From 0979dea9621b3035b6a5f919920f75ea463b0b90 Mon Sep 17 00:00:00 2001
+From: Jay Cornwall <jay.cornwall@amd.com>
+Date: Sun, 28 Jul 2019 15:24:40 -0500
+Subject: [PATCH 3161/4256] drm/amdkfd: Fix gfx10 wave64 VGPR context restore
+
+Copy/paste error, first 4 VGPRs are separated by 64 dwords (256 bytes).
+
+Cc: Shaoyun Liu <shaoyun.liu@amd.com>
+Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: shaoyunl <shaoyun.liu@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h         | 6 +++---
+ drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm | 6 +++---
+ 2 files changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+index 2b3d7017f142..c10e424dd1f5 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+@@ -982,9 +982,9 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
+ 	0x00000080, 0xbf0a6f7c,
+ 	0xbf85fff7, 0xbeff03c1,
+ 	0xe0304000, 0x725d0000,
+-	0xe0304080, 0x725d0100,
+-	0xe0304100, 0x725d0200,
+-	0xe0304180, 0x725d0300,
++	0xe0304100, 0x725d0100,
++	0xe0304200, 0x725d0200,
++	0xe0304300, 0x725d0300,
+ 	0xb9782a05, 0x80788178,
+ 	0x907c9973, 0x877c817c,
+ 	0xbf06817c, 0xbf850002,
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
+index 261e05430852..be6f7d1847fa 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
+@@ -747,9 +747,9 @@ L_RESTORE_SHARED_VGPR_WAVE64_LOOP:
+ 	/* VGPR restore on v0 */
+ L_RESTORE_V0:
+ 	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1
+-	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128
+-	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*2
+-	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*3
++	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256
++	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2
++	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3
+ 
+ 	/* restore SGPRs */
+ 	//will be 2+8+16*6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3162-drm-amdkfd-Save-restore-flat_scratch_lo-hi-on-gfx10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3162-drm-amdkfd-Save-restore-flat_scratch_lo-hi-on-gfx10.patch
new file mode 100644
index 00000000..e274e73c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3162-drm-amdkfd-Save-restore-flat_scratch_lo-hi-on-gfx10.patch
@@ -0,0 +1,154 @@
+From 12596bce220b105b2ad0708ce1fe0b240fa55f5e Mon Sep 17 00:00:00 2001
+From: Jay Cornwall <jay.cornwall@amd.com>
+Date: Sun, 28 Jul 2019 15:25:05 -0500
+Subject: [PATCH 3162/4256] drm/amdkfd: Save/restore flat_scratch_lo/hi on
+ gfx10
+
+These moved from SGPRs in gfx9 to HWREG in gfx10.
+
+Cc: Shaoyun Liu <shaoyun.liu@amd.com>
+Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: shaoyunl <shaoyun.liu@amd.com>
+---
+ .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h    | 56 +++++++++++--------
+ .../amd/amdkfd/cwsr_trap_handler_gfx10.asm    | 14 +++++
+ 2 files changed, 48 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+index c10e424dd1f5..8089bb37f393 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+@@ -680,7 +680,7 @@ static const uint32_t cwsr_trap_gfx9_hex[] = {
+ };
+ 
+ static const uint32_t cwsr_trap_gfx10_hex[] = {
+-	0xbf820001, 0xbf8201b2,
++	0xbf820001, 0xbf8201c0,
+ 	0xb0804004, 0xb978f802,
+ 	0x8a788678, 0xb971f803,
+ 	0x876eff71, 0x00000400,
+@@ -772,6 +772,13 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
+ 	0xb97bf801, 0xbefe037c,
+ 	0xbefc037a, 0xf4611efa,
+ 	0xf8000000, 0x807a847a,
++	0xbefc037e, 0xb97bf814,
++	0xbefe037c, 0xbefc037a,
++	0xf4611efa, 0xf8000000,
++	0x807a847a, 0xbefc037e,
++	0xb97bf815, 0xbefe037c,
++	0xbefc037a, 0xf4611efa,
++	0xf8000000, 0x807a847a,
+ 	0xbefc037e, 0x8776ff7f,
+ 	0x04000000, 0xbeef0380,
+ 	0x886f6f76, 0xb97a2a05,
+@@ -897,7 +904,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
+ 	0xe0704000, 0x7a5d0000,
+ 	0x807c817c, 0x807aff7a,
+ 	0x00000080, 0xbf0a717c,
+-	0xbf85fff8, 0xbf820138,
++	0xbf85fff8, 0xbf820141,
+ 	0xbef4037e, 0x8775ff7f,
+ 	0x0000ffff, 0x8875ff75,
+ 	0x00040000, 0xbef60380,
+@@ -1033,30 +1040,35 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
+ 	0x80788478, 0xf4211e7a,
+ 	0xf0000000, 0x80788478,
+ 	0xf4211cfa, 0xf0000000,
++	0x80788478, 0xf4211bba,
++	0xf0000000, 0x80788478,
++	0xbf8cc07f, 0xb9eef814,
++	0xf4211bba, 0xf0000000,
+ 	0x80788478, 0xbf8cc07f,
+-	0xbef2036d, 0x876dff72,
+-	0x0000ffff, 0xbefc036f,
+-	0xbefe037a, 0xbeff037b,
+-	0x876f71ff, 0x000003ff,
+-	0xb9ef4803, 0xb9f9f816,
+-	0x876f71ff, 0xfffff800,
+-	0x906f8b6f, 0xb9efa2c3,
+-	0xb9f3f801, 0x876fff72,
+-	0xfc000000, 0x906f9a6f,
+-	0x8f6f906f, 0xbef30380,
++	0xb9eef815, 0xbef2036d,
++	0x876dff72, 0x0000ffff,
++	0xbefc036f, 0xbefe037a,
++	0xbeff037b, 0x876f71ff,
++	0x000003ff, 0xb9ef4803,
++	0xb9f9f816, 0x876f71ff,
++	0xfffff800, 0x906f8b6f,
++	0xb9efa2c3, 0xb9f3f801,
++	0x876fff72, 0xfc000000,
++	0x906f9a6f, 0x8f6f906f,
++	0xbef30380, 0x88736f73,
++	0x876fff72, 0x02000000,
++	0x906f996f, 0x8f6f8f6f,
+ 	0x88736f73, 0x876fff72,
+-	0x02000000, 0x906f996f,
+-	0x8f6f8f6f, 0x88736f73,
+-	0x876fff72, 0x01000000,
+-	0x906f986f, 0x8f6f996f,
+-	0x88736f73, 0x876fff70,
+-	0x00800000, 0x906f976f,
+-	0xb9f3f807, 0x87fe7e7e,
+-	0x87ea6a6a, 0xb9f0f802,
+-	0xbf8a0000, 0xbe80226c,
+-	0xbf810000, 0xbf9f0000,
++	0x01000000, 0x906f986f,
++	0x8f6f996f, 0x88736f73,
++	0x876fff70, 0x00800000,
++	0x906f976f, 0xb9f3f807,
++	0x87fe7e7e, 0x87ea6a6a,
++	0xb9f0f802, 0xbf8a0000,
++	0xbe80226c, 0xbf810000,
+ 	0xbf9f0000, 0xbf9f0000,
+ 	0xbf9f0000, 0xbf9f0000,
++	0xbf9f0000, 0x00000000,
+ };
+ static const uint32_t cwsr_trap_arcturus_hex[] = {
+ 	0xbf820001, 0xbf8202c4,
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
+index be6f7d1847fa..fafdfd2ac610 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
+@@ -132,6 +132,7 @@ var s_restore_tmp				= ttmp6
+ var s_restore_mem_offset_save			= s_restore_tmp
+ var s_restore_m0				= s_restore_alloc_size
+ var s_restore_mode				= ttmp7
++var s_restore_flat_scratch			= ttmp2
+ var s_restore_pc_lo				= ttmp0
+ var s_restore_pc_hi				= ttmp1
+ var s_restore_exec_lo				= ttmp14
+@@ -313,6 +314,12 @@ L_SAVE_HWREG:
+ 	s_getreg_b32	s_save_m0, hwreg(HW_REG_MODE)
+ 	write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)
+ 
++	s_getreg_b32	s_save_m0, hwreg(HW_REG_SHADER_FLAT_SCRATCH_LO)
++	write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)
++
++	s_getreg_b32	s_save_m0, hwreg(HW_REG_SHADER_FLAT_SCRATCH_HI)
++	write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)
++
+ 	/* the first wave in the threadgroup */
+ 	s_and_b32	s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK
+ 	s_mov_b32	s_save_exec_hi, 0x0
+@@ -824,9 +831,16 @@ L_RESTORE_HWREG:
+ 	read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset)
+ 	read_hwreg_from_mem(s_restore_xnack_mask, s_restore_buf_rsrc0, s_restore_mem_offset)
+ 	read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset)
++	read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset)
++	s_waitcnt	lgkmcnt(0)
++
++	s_setreg_b32	hwreg(HW_REG_SHADER_FLAT_SCRATCH_LO), s_restore_flat_scratch
+ 
++	read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset)
+ 	s_waitcnt	lgkmcnt(0)						//from now on, it is safe to restore STATUS and IB_STS
+ 
++	s_setreg_b32	hwreg(HW_REG_SHADER_FLAT_SCRATCH_HI), s_restore_flat_scratch
++
+ 	s_mov_b32	s_restore_tmp, s_restore_pc_hi
+ 	s_and_b32	s_restore_pc_hi, s_restore_tmp, 0x0000ffff		//pc[47:32] //Do it here in order not to affect STATUS
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3163-drm-amdkfd-Save-restore-vcc-on-gfx10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3163-drm-amdkfd-Save-restore-vcc-on-gfx10.patch
new file mode 100644
index 00000000..f8361cab
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3163-drm-amdkfd-Save-restore-vcc-on-gfx10.patch
@@ -0,0 +1,633 @@
+From dde83f1e7d3fbec842a6cae87f593c7adc1be001 Mon Sep 17 00:00:00 2001
+From: Jay Cornwall <jay.cornwall@amd.com>
+Date: Sun, 28 Jul 2019 16:00:59 -0500
+Subject: [PATCH 3163/4256] drm/amdkfd: Save/restore vcc on gfx10
+
+VCC moved out of user SGPR allocation in gfx10. It's now stored
+in SGPRs 106-107.
+
+Also fixes incorrect SGPR read offsets.
+
+Cc: Shaoyun Liu <shaoyun.liu@amd.com>
+Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: shaoyunl <shaoyun.liu@amd.com>
+---
+ .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h    | 452 +++++++++---------
+ .../amd/amdkfd/cwsr_trap_handler_gfx10.asm    |  34 +-
+ 2 files changed, 243 insertions(+), 243 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+index 8089bb37f393..a8cf82d46109 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+@@ -680,7 +680,7 @@ static const uint32_t cwsr_trap_gfx9_hex[] = {
+ };
+ 
+ static const uint32_t cwsr_trap_gfx10_hex[] = {
+-	0xbf820001, 0xbf8201c0,
++	0xbf820001, 0xbf8201c1,
+ 	0xb0804004, 0xb978f802,
+ 	0x8a788678, 0xb971f803,
+ 	0x876eff71, 0x00000400,
+@@ -804,271 +804,271 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
+ 	0x00000060, 0xbf85ffea,
+ 	0xbe802f00, 0xbe822f02,
+ 	0xbe842f04, 0xbe862f06,
+-	0xbe882f08, 0xf469003a,
+-	0xfa000000, 0xf469013a,
+-	0xfa000010, 0xf465023a,
+-	0xfa000020, 0x8074c074,
+-	0x82758075, 0xbef40372,
+-	0xbefa0380, 0xbefe03c1,
+-	0x907c9973, 0x877c817c,
+-	0xbf06817c, 0xbf850002,
+-	0xbeff0380, 0xbf820002,
+-	0xbeff03c1, 0xbf82000b,
++	0xbe882f08, 0xbe8a2f0a,
++	0xf469003a, 0xfa000000,
++	0xf469013a, 0xfa000010,
++	0xf469023a, 0xfa000020,
++	0x8074b074, 0x82758075,
++	0xbef40372, 0xbefa0380,
++	0xbefe03c1, 0x907c9973,
++	0x877c817c, 0xbf06817c,
++	0xbf850002, 0xbeff0380,
++	0xbf820002, 0xbeff03c1,
++	0xbf82000b, 0xbef603ff,
++	0x01000000, 0xe0704000,
++	0x7a5d0000, 0xe0704080,
++	0x7a5d0100, 0xe0704100,
++	0x7a5d0200, 0xe0704180,
++	0x7a5d0300, 0xbf82000a,
+ 	0xbef603ff, 0x01000000,
+ 	0xe0704000, 0x7a5d0000,
+-	0xe0704080, 0x7a5d0100,
+-	0xe0704100, 0x7a5d0200,
+-	0xe0704180, 0x7a5d0300,
+-	0xbf82000a, 0xbef603ff,
+-	0x01000000, 0xe0704000,
+-	0x7a5d0000, 0xe0704100,
+-	0x7a5d0100, 0xe0704200,
+-	0x7a5d0200, 0xe0704300,
+-	0x7a5d0300, 0xbefe03c1,
++	0xe0704100, 0x7a5d0100,
++	0xe0704200, 0x7a5d0200,
++	0xe0704300, 0x7a5d0300,
++	0xbefe03c1, 0x907c9973,
++	0x877c817c, 0xbf06817c,
++	0xbf850002, 0xbeff0380,
++	0xbf820001, 0xbeff03c1,
++	0xb9714306, 0x8771c171,
++	0xbf840046, 0xbf8a0000,
++	0x8776ff6f, 0x04000000,
++	0xbf840042, 0x8f718671,
++	0x8f718271, 0xbef60371,
++	0xb97a2a05, 0x807a817a,
+ 	0x907c9973, 0x877c817c,
+ 	0xbf06817c, 0xbf850002,
+-	0xbeff0380, 0xbf820001,
+-	0xbeff03c1, 0xb9714306,
+-	0x8771c171, 0xbf840046,
+-	0xbf8a0000, 0x8776ff6f,
+-	0x04000000, 0xbf840042,
+-	0x8f718671, 0x8f718271,
+-	0xbef60371, 0xb97a2a05,
+-	0x807a817a, 0x907c9973,
++	0x8f7a897a, 0xbf820001,
++	0x8f7a8a7a, 0xb9761e06,
++	0x8f768a76, 0x807a767a,
++	0x807aff7a, 0x00000200,
++	0x807aff7a, 0x00000080,
++	0xbef603ff, 0x01000000,
++	0xd7650000, 0x000100c1,
++	0xd7660000, 0x000200c1,
++	0x16000084, 0x907c9973,
+ 	0x877c817c, 0xbf06817c,
+-	0xbf850002, 0x8f7a897a,
+-	0xbf820001, 0x8f7a8a7a,
+-	0xb9761e06, 0x8f768a76,
+-	0x807a767a, 0x807aff7a,
+-	0x00000200, 0x807aff7a,
+-	0x00000080, 0xbef603ff,
+-	0x01000000, 0xd7650000,
+-	0x000100c1, 0xd7660000,
+-	0x000200c1, 0x16000084,
+-	0x907c9973, 0x877c817c,
+-	0xbf06817c, 0xbefc0380,
+-	0xbf850012, 0xbe8303ff,
+-	0x00000080, 0xbf800000,
++	0xbefc0380, 0xbf850012,
++	0xbe8303ff, 0x00000080,
+ 	0xbf800000, 0xbf800000,
+-	0xd8d80000, 0x01000000,
+-	0xbf8c0000, 0xe0704000,
+-	0x7a5d0100, 0x807c037c,
+-	0x807a037a, 0xd5250000,
+-	0x0001ff00, 0x00000080,
+-	0xbf0a717c, 0xbf85fff4,
+-	0xbf820011, 0xbe8303ff,
+-	0x00000100, 0xbf800000,
++	0xbf800000, 0xd8d80000,
++	0x01000000, 0xbf8c0000,
++	0xe0704000, 0x7a5d0100,
++	0x807c037c, 0x807a037a,
++	0xd5250000, 0x0001ff00,
++	0x00000080, 0xbf0a717c,
++	0xbf85fff4, 0xbf820011,
++	0xbe8303ff, 0x00000100,
+ 	0xbf800000, 0xbf800000,
+-	0xd8d80000, 0x01000000,
+-	0xbf8c0000, 0xe0704000,
+-	0x7a5d0100, 0x807c037c,
+-	0x807a037a, 0xd5250000,
+-	0x0001ff00, 0x00000100,
+-	0xbf0a717c, 0xbf85fff4,
+-	0xbefe03c1, 0x907c9973,
+-	0x877c817c, 0xbf06817c,
+-	0xbf850004, 0xbefa03ff,
+-	0x00000200, 0xbeff0380,
+-	0xbf820003, 0xbefa03ff,
+-	0x00000400, 0xbeff03c1,
+-	0xb9712a05, 0x80718171,
+-	0x8f718271, 0x907c9973,
+-	0x877c817c, 0xbf06817c,
+-	0xbf850017, 0xbef603ff,
+-	0x01000000, 0xbefc0384,
+-	0xbf0a717c, 0xbf840037,
+-	0x7e008700, 0x7e028701,
+-	0x7e048702, 0x7e068703,
+-	0xe0704000, 0x7a5d0000,
+-	0xe0704080, 0x7a5d0100,
+-	0xe0704100, 0x7a5d0200,
+-	0xe0704180, 0x7a5d0300,
+-	0x807c847c, 0x807aff7a,
+-	0x00000200, 0xbf0a717c,
+-	0xbf85ffef, 0xbf820025,
++	0xbf800000, 0xd8d80000,
++	0x01000000, 0xbf8c0000,
++	0xe0704000, 0x7a5d0100,
++	0x807c037c, 0x807a037a,
++	0xd5250000, 0x0001ff00,
++	0x00000100, 0xbf0a717c,
++	0xbf85fff4, 0xbefe03c1,
++	0x907c9973, 0x877c817c,
++	0xbf06817c, 0xbf850004,
++	0xbefa03ff, 0x00000200,
++	0xbeff0380, 0xbf820003,
++	0xbefa03ff, 0x00000400,
++	0xbeff03c1, 0xb9712a05,
++	0x80718171, 0x8f718271,
++	0x907c9973, 0x877c817c,
++	0xbf06817c, 0xbf850017,
+ 	0xbef603ff, 0x01000000,
+ 	0xbefc0384, 0xbf0a717c,
+-	0xbf840020, 0x7e008700,
++	0xbf840037, 0x7e008700,
+ 	0x7e028701, 0x7e048702,
+ 	0x7e068703, 0xe0704000,
+-	0x7a5d0000, 0xe0704100,
+-	0x7a5d0100, 0xe0704200,
+-	0x7a5d0200, 0xe0704300,
++	0x7a5d0000, 0xe0704080,
++	0x7a5d0100, 0xe0704100,
++	0x7a5d0200, 0xe0704180,
+ 	0x7a5d0300, 0x807c847c,
+-	0x807aff7a, 0x00000400,
++	0x807aff7a, 0x00000200,
+ 	0xbf0a717c, 0xbf85ffef,
+-	0xb9711e06, 0x8771c171,
+-	0xbf84000c, 0x8f718371,
+-	0x80717c71, 0xbefe03c1,
+-	0xbeff0380, 0x7e008700,
++	0xbf820025, 0xbef603ff,
++	0x01000000, 0xbefc0384,
++	0xbf0a717c, 0xbf840020,
++	0x7e008700, 0x7e028701,
++	0x7e048702, 0x7e068703,
+ 	0xe0704000, 0x7a5d0000,
+-	0x807c817c, 0x807aff7a,
+-	0x00000080, 0xbf0a717c,
+-	0xbf85fff8, 0xbf820141,
+-	0xbef4037e, 0x8775ff7f,
+-	0x0000ffff, 0x8875ff75,
+-	0x00040000, 0xbef60380,
+-	0xbef703ff, 0x10807fac,
+-	0x8772ff7f, 0x08000000,
+-	0x90728372, 0x88777277,
+-	0x8772ff7f, 0x70000000,
+-	0x90728172, 0x88777277,
+-	0xb97302dc, 0x8f739973,
+-	0x8873737f, 0x8772ff7f,
+-	0x04000000, 0xbf840036,
+-	0xbefe03c1, 0x907c9973,
+-	0x877c817c, 0xbf06817c,
+-	0xbf850002, 0xbeff0380,
+-	0xbf820001, 0xbeff03c1,
+-	0xb96f4306, 0x876fc16f,
+-	0xbf84002b, 0x8f6f866f,
+-	0x8f6f826f, 0xbef6036f,
+-	0xb9782a05, 0x80788178,
++	0xe0704100, 0x7a5d0100,
++	0xe0704200, 0x7a5d0200,
++	0xe0704300, 0x7a5d0300,
++	0x807c847c, 0x807aff7a,
++	0x00000400, 0xbf0a717c,
++	0xbf85ffef, 0xb9711e06,
++	0x8771c171, 0xbf84000c,
++	0x8f718371, 0x80717c71,
++	0xbefe03c1, 0xbeff0380,
++	0x7e008700, 0xe0704000,
++	0x7a5d0000, 0x807c817c,
++	0x807aff7a, 0x00000080,
++	0xbf0a717c, 0xbf85fff8,
++	0xbf820141, 0xbef4037e,
++	0x8775ff7f, 0x0000ffff,
++	0x8875ff75, 0x00040000,
++	0xbef60380, 0xbef703ff,
++	0x10807fac, 0x8772ff7f,
++	0x08000000, 0x90728372,
++	0x88777277, 0x8772ff7f,
++	0x70000000, 0x90728172,
++	0x88777277, 0xb97302dc,
++	0x8f739973, 0x8873737f,
++	0x8772ff7f, 0x04000000,
++	0xbf840036, 0xbefe03c1,
+ 	0x907c9973, 0x877c817c,
+ 	0xbf06817c, 0xbf850002,
+-	0x8f788978, 0xbf820001,
+-	0x8f788a78, 0xb9721e06,
+-	0x8f728a72, 0x80787278,
+-	0x8078ff78, 0x00000200,
+-	0x8078ff78, 0x00000080,
+-	0xbef603ff, 0x01000000,
+-	0x907c9973, 0x877c817c,
+-	0xbf06817c, 0xbefc0380,
+-	0xbf850009, 0xe0310000,
+-	0x781d0000, 0x807cff7c,
+-	0x00000080, 0x8078ff78,
+-	0x00000080, 0xbf0a6f7c,
+-	0xbf85fff8, 0xbf820008,
++	0xbeff0380, 0xbf820001,
++	0xbeff03c1, 0xb96f4306,
++	0x876fc16f, 0xbf84002b,
++	0x8f6f866f, 0x8f6f826f,
++	0xbef6036f, 0xb9782a05,
++	0x80788178, 0x907c9973,
++	0x877c817c, 0xbf06817c,
++	0xbf850002, 0x8f788978,
++	0xbf820001, 0x8f788a78,
++	0xb9721e06, 0x8f728a72,
++	0x80787278, 0x8078ff78,
++	0x00000200, 0x8078ff78,
++	0x00000080, 0xbef603ff,
++	0x01000000, 0x907c9973,
++	0x877c817c, 0xbf06817c,
++	0xbefc0380, 0xbf850009,
+ 	0xe0310000, 0x781d0000,
+-	0x807cff7c, 0x00000100,
+-	0x8078ff78, 0x00000100,
++	0x807cff7c, 0x00000080,
++	0x8078ff78, 0x00000080,
+ 	0xbf0a6f7c, 0xbf85fff8,
+-	0xbef80380, 0xbefe03c1,
+-	0x907c9973, 0x877c817c,
+-	0xbf06817c, 0xbf850002,
+-	0xbeff0380, 0xbf820001,
+-	0xbeff03c1, 0xb96f2a05,
+-	0x806f816f, 0x8f6f826f,
+-	0x907c9973, 0x877c817c,
+-	0xbf06817c, 0xbf850021,
+-	0xbef603ff, 0x01000000,
+-	0xbef20378, 0x8078ff78,
+-	0x00000200, 0xbefc0384,
+-	0xe0304000, 0x785d0000,
+-	0xe0304080, 0x785d0100,
+-	0xe0304100, 0x785d0200,
+-	0xe0304180, 0x785d0300,
+-	0xbf8c3f70, 0x7e008500,
+-	0x7e028501, 0x7e048502,
+-	0x7e068503, 0x807c847c,
+-	0x8078ff78, 0x00000200,
+-	0xbf0a6f7c, 0xbf85ffee,
+-	0xe0304000, 0x725d0000,
+-	0xe0304080, 0x725d0100,
+-	0xe0304100, 0x725d0200,
+-	0xe0304180, 0x725d0300,
+-	0xbf820031, 0xbef603ff,
++	0xbf820008, 0xe0310000,
++	0x781d0000, 0x807cff7c,
++	0x00000100, 0x8078ff78,
++	0x00000100, 0xbf0a6f7c,
++	0xbf85fff8, 0xbef80380,
++	0xbefe03c1, 0x907c9973,
++	0x877c817c, 0xbf06817c,
++	0xbf850002, 0xbeff0380,
++	0xbf820001, 0xbeff03c1,
++	0xb96f2a05, 0x806f816f,
++	0x8f6f826f, 0x907c9973,
++	0x877c817c, 0xbf06817c,
++	0xbf850021, 0xbef603ff,
+ 	0x01000000, 0xbef20378,
+-	0x8078ff78, 0x00000400,
++	0x8078ff78, 0x00000200,
+ 	0xbefc0384, 0xe0304000,
+-	0x785d0000, 0xe0304100,
+-	0x785d0100, 0xe0304200,
+-	0x785d0200, 0xe0304300,
++	0x785d0000, 0xe0304080,
++	0x785d0100, 0xe0304100,
++	0x785d0200, 0xe0304180,
+ 	0x785d0300, 0xbf8c3f70,
+ 	0x7e008500, 0x7e028501,
+ 	0x7e048502, 0x7e068503,
+ 	0x807c847c, 0x8078ff78,
+-	0x00000400, 0xbf0a6f7c,
+-	0xbf85ffee, 0xb96f1e06,
+-	0x876fc16f, 0xbf84000e,
+-	0x8f6f836f, 0x806f7c6f,
+-	0xbefe03c1, 0xbeff0380,
++	0x00000200, 0xbf0a6f7c,
++	0xbf85ffee, 0xe0304000,
++	0x725d0000, 0xe0304080,
++	0x725d0100, 0xe0304100,
++	0x725d0200, 0xe0304180,
++	0x725d0300, 0xbf820031,
++	0xbef603ff, 0x01000000,
++	0xbef20378, 0x8078ff78,
++	0x00000400, 0xbefc0384,
+ 	0xe0304000, 0x785d0000,
++	0xe0304100, 0x785d0100,
++	0xe0304200, 0x785d0200,
++	0xe0304300, 0x785d0300,
+ 	0xbf8c3f70, 0x7e008500,
+-	0x807c817c, 0x8078ff78,
+-	0x00000080, 0xbf0a6f7c,
+-	0xbf85fff7, 0xbeff03c1,
+-	0xe0304000, 0x725d0000,
+-	0xe0304100, 0x725d0100,
+-	0xe0304200, 0x725d0200,
+-	0xe0304300, 0x725d0300,
+-	0xb9782a05, 0x80788178,
+-	0x907c9973, 0x877c817c,
+-	0xbf06817c, 0xbf850002,
+-	0x8f788978, 0xbf820001,
+-	0x8f788a78, 0xb9721e06,
+-	0x8f728a72, 0x80787278,
+-	0x8078ff78, 0x00000200,
+-	0x80f8ff78, 0x00000058,
+-	0x80f88878, 0xbef603ff,
++	0x7e028501, 0x7e048502,
++	0x7e068503, 0x807c847c,
++	0x8078ff78, 0x00000400,
++	0xbf0a6f7c, 0xbf85ffee,
++	0xb96f1e06, 0x876fc16f,
++	0xbf84000e, 0x8f6f836f,
++	0x806f7c6f, 0xbefe03c1,
++	0xbeff0380, 0xe0304000,
++	0x785d0000, 0xbf8c3f70,
++	0x7e008500, 0x807c817c,
++	0x8078ff78, 0x00000080,
++	0xbf0a6f7c, 0xbf85fff7,
++	0xbeff03c1, 0xe0304000,
++	0x725d0000, 0xe0304100,
++	0x725d0100, 0xe0304200,
++	0x725d0200, 0xe0304300,
++	0x725d0300, 0xb9782a05,
++	0x80788178, 0x907c9973,
++	0x877c817c, 0xbf06817c,
++	0xbf850002, 0x8f788978,
++	0xbf820001, 0x8f788a78,
++	0xb9721e06, 0x8f728a72,
++	0x80787278, 0x8078ff78,
++	0x00000200, 0x80f8ff78,
++	0x00000050, 0xbef603ff,
+ 	0x01000000, 0xbefc03ff,
+-	0x0000006a, 0xf425003a,
+-	0xf0000000, 0x80f8a078,
+-	0xbf8cc07f, 0x80fc827c,
++	0x0000006c, 0x80f89078,
++	0xf429003a, 0xf0000000,
++	0xbf8cc07f, 0x80fc847c,
+ 	0xbf800000, 0xbe803100,
++	0xbe823102, 0x80f8a078,
+ 	0xf42d003a, 0xf0000000,
+-	0x80f8c078, 0xbf8cc07f,
+-	0x80fc887c, 0xbf800000,
+-	0xbe803100, 0xbe823102,
+-	0xbe843104, 0xbe863106,
++	0xbf8cc07f, 0x80fc887c,
++	0xbf800000, 0xbe803100,
++	0xbe823102, 0xbe843104,
++	0xbe863106, 0x80f8c078,
+ 	0xf431003a, 0xf0000000,
+-	0x80f8c078, 0xbf8cc07f,
+-	0x80fc907c, 0xbf800000,
+-	0xbe803100, 0xbe823102,
+-	0xbe843104, 0xbe863106,
+-	0xbe883108, 0xbe8a310a,
+-	0xbe8c310c, 0xbe8e310e,
+-	0xbf06807c, 0xbf84fff0,
+-	0xb9782a05, 0x80788178,
+-	0x907c9973, 0x877c817c,
+-	0xbf06817c, 0xbf850002,
+-	0x8f788978, 0xbf820001,
+-	0x8f788a78, 0xb9721e06,
+-	0x8f728a72, 0x80787278,
+-	0x8078ff78, 0x00000200,
+-	0xbef603ff, 0x01000000,
+-	0xf4211bfa, 0xf0000000,
+-	0x80788478, 0xf4211b3a,
++	0xbf8cc07f, 0x80fc907c,
++	0xbf800000, 0xbe803100,
++	0xbe823102, 0xbe843104,
++	0xbe863106, 0xbe883108,
++	0xbe8a310a, 0xbe8c310c,
++	0xbe8e310e, 0xbf06807c,
++	0xbf84fff0, 0xb9782a05,
++	0x80788178, 0x907c9973,
++	0x877c817c, 0xbf06817c,
++	0xbf850002, 0x8f788978,
++	0xbf820001, 0x8f788a78,
++	0xb9721e06, 0x8f728a72,
++	0x80787278, 0x8078ff78,
++	0x00000200, 0xbef603ff,
++	0x01000000, 0xf4211bfa,
+ 	0xf0000000, 0x80788478,
+-	0xf4211b7a, 0xf0000000,
+-	0x80788478, 0xf4211eba,
++	0xf4211b3a, 0xf0000000,
++	0x80788478, 0xf4211b7a,
+ 	0xf0000000, 0x80788478,
+-	0xf4211efa, 0xf0000000,
+-	0x80788478, 0xf4211c3a,
++	0xf4211eba, 0xf0000000,
++	0x80788478, 0xf4211efa,
+ 	0xf0000000, 0x80788478,
+-	0xf4211c7a, 0xf0000000,
+-	0x80788478, 0xf4211e7a,
++	0xf4211c3a, 0xf0000000,
++	0x80788478, 0xf4211c7a,
+ 	0xf0000000, 0x80788478,
+-	0xf4211cfa, 0xf0000000,
+-	0x80788478, 0xf4211bba,
++	0xf4211e7a, 0xf0000000,
++	0x80788478, 0xf4211cfa,
+ 	0xf0000000, 0x80788478,
+-	0xbf8cc07f, 0xb9eef814,
+ 	0xf4211bba, 0xf0000000,
+ 	0x80788478, 0xbf8cc07f,
+-	0xb9eef815, 0xbef2036d,
+-	0x876dff72, 0x0000ffff,
+-	0xbefc036f, 0xbefe037a,
+-	0xbeff037b, 0x876f71ff,
+-	0x000003ff, 0xb9ef4803,
+-	0xb9f9f816, 0x876f71ff,
+-	0xfffff800, 0x906f8b6f,
+-	0xb9efa2c3, 0xb9f3f801,
+-	0x876fff72, 0xfc000000,
+-	0x906f9a6f, 0x8f6f906f,
+-	0xbef30380, 0x88736f73,
+-	0x876fff72, 0x02000000,
+-	0x906f996f, 0x8f6f8f6f,
++	0xb9eef814, 0xf4211bba,
++	0xf0000000, 0x80788478,
++	0xbf8cc07f, 0xb9eef815,
++	0xbef2036d, 0x876dff72,
++	0x0000ffff, 0xbefc036f,
++	0xbefe037a, 0xbeff037b,
++	0x876f71ff, 0x000003ff,
++	0xb9ef4803, 0xb9f9f816,
++	0x876f71ff, 0xfffff800,
++	0x906f8b6f, 0xb9efa2c3,
++	0xb9f3f801, 0x876fff72,
++	0xfc000000, 0x906f9a6f,
++	0x8f6f906f, 0xbef30380,
+ 	0x88736f73, 0x876fff72,
+-	0x01000000, 0x906f986f,
+-	0x8f6f996f, 0x88736f73,
+-	0x876fff70, 0x00800000,
+-	0x906f976f, 0xb9f3f807,
+-	0x87fe7e7e, 0x87ea6a6a,
+-	0xb9f0f802, 0xbf8a0000,
+-	0xbe80226c, 0xbf810000,
++	0x02000000, 0x906f996f,
++	0x8f6f8f6f, 0x88736f73,
++	0x876fff72, 0x01000000,
++	0x906f986f, 0x8f6f996f,
++	0x88736f73, 0x876fff70,
++	0x00800000, 0x906f976f,
++	0xb9f3f807, 0x87fe7e7e,
++	0x87ea6a6a, 0xb9f0f802,
++	0xbf8a0000, 0xbe80226c,
++	0xbf810000, 0xbf9f0000,
+ 	0xbf9f0000, 0xbf9f0000,
+ 	0xbf9f0000, 0xbf9f0000,
+-	0xbf9f0000, 0x00000000,
+ };
+ static const uint32_t cwsr_trap_arcturus_hex[] = {
+ 	0xbf820001, 0xbf8202c4,
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
+index fafdfd2ac610..35986219ce5f 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
+@@ -87,7 +87,7 @@ var S_SAVE_PC_HI_FIRST_REPLAY_MASK		= 0x02000000
+ var S_SAVE_PC_HI_REPLAY_W64H_SHIFT		= 24
+ var S_SAVE_PC_HI_REPLAY_W64H_MASK		= 0x01000000
+ 
+-var s_sgpr_save_num				= 106
++var s_sgpr_save_num				= 108
+ 
+ var s_save_spi_init_lo				= exec_lo
+ var s_save_spi_init_hi				= exec_hi
+@@ -357,13 +357,14 @@ L_SAVE_SGPR_LOOP:
+ 	s_cmp_lt_u32	m0, 96							//scc = (m0 < first 96 SGPR) ? 1 : 0
+ 	s_cbranch_scc1	L_SAVE_SGPR_LOOP					//first 96 SGPR save is complete?
+ 
+-	//save the rest 10 SGPR
++	//save the rest 12 SGPR
+ 	s_movrels_b64	s0, s0							//s0 = s[0+m0], s1 = s[1+m0]
+ 	s_movrels_b64	s2, s2							//s2 = s[2+m0], s3 = s[3+m0]
+ 	s_movrels_b64	s4, s4							//s4 = s[4+m0], s5 = s[5+m0]
+ 	s_movrels_b64	s6, s6							//s6 = s[6+m0], s7 = s[7+m0]
+ 	s_movrels_b64	s8, s8							//s8 = s[8+m0], s9 = s[9+m0]
+-	write_10sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset)
++	s_movrels_b64	s10, s10						//s10 = s[10+m0], s11 = s[11+m0]
++	write_12sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset)
+ 
+ 	// restore s_save_buf_rsrc0,1
+ 	s_mov_b32	s_save_buf_rsrc0, s_save_xnack_mask
+@@ -766,26 +767,25 @@ L_RESTORE_SGPR:
+ 	get_svgpr_size_bytes(s_restore_tmp)
+ 	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp
+ 	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes()
+-	s_sub_u32	s_restore_mem_offset, s_restore_mem_offset, 22*4	//s106~s127 is not saved
+-	s_sub_u32	s_restore_mem_offset, s_restore_mem_offset, 2*4		// restore SGPR from S[n] to S[0], by 2 sgprs group
++	s_sub_u32	s_restore_mem_offset, s_restore_mem_offset, 20*4	//s108~s127 is not saved
+ 
+ 	s_mov_b32	s_restore_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
+ 
+ 	s_mov_b32	m0, s_sgpr_save_num
+ 
+-	read_2sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset)
+-
++	read_4sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset)
+ 	s_waitcnt	lgkmcnt(0)
+ 
+-	s_sub_u32	m0, m0, 2						// Restore from S[n] to S[0]
++	s_sub_u32	m0, m0, 4						// Restore from S[0] to S[104]
+ 	s_nop		0							// hazard SALU M0=> S_MOVREL
+ 
+ 	s_movreld_b64	s0, s0							//s[0+m0] = s0
++	s_movreld_b64	s2, s2
+ 
+ 	read_8sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset)
+ 	s_waitcnt	lgkmcnt(0)
+ 
+-	s_sub_u32	m0, m0, 8						// Restore from S[n] to S[0]
++	s_sub_u32	m0, m0, 8						// Restore from S[0] to S[96]
+ 	s_nop		0							// hazard SALU M0=> S_MOVREL
+ 
+ 	s_movreld_b64	s0, s0							//s[0+m0] = s0
+@@ -903,11 +903,11 @@ function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset)
+ 	s_addc_u32	s_rsrc[1], s_rsrc[1], 0x0
+ end
+ 
+-function write_10sgpr_to_mem(s, s_rsrc, s_mem_offset)
++function write_12sgpr_to_mem(s, s_rsrc, s_mem_offset)
+ 	s_buffer_store_dwordx4	s[0], s_rsrc, 0 glc:1
+ 	s_buffer_store_dwordx4	s[4], s_rsrc, 16 glc:1
+-	s_buffer_store_dwordx2	s[8], s_rsrc, 32 glc:1
+-	s_add_u32	s_rsrc[0], s_rsrc[0], 4*16
++	s_buffer_store_dwordx4	s[8], s_rsrc, 32 glc:1
++	s_add_u32	s_rsrc[0], s_rsrc[0], 4*12
+ 	s_addc_u32	s_rsrc[1], s_rsrc[1], 0x0
+ end
+ 
+@@ -918,18 +918,18 @@ function read_hwreg_from_mem(s, s_rsrc, s_mem_offset)
+ end
+ 
+ function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset)
+-	s_buffer_load_dwordx16	s, s_rsrc, s_mem_offset glc:1
+ 	s_sub_u32	s_mem_offset, s_mem_offset, 4*16
++	s_buffer_load_dwordx16	s, s_rsrc, s_mem_offset glc:1
+ end
+ 
+ function read_8sgpr_from_mem(s, s_rsrc, s_mem_offset)
++	s_sub_u32	s_mem_offset, s_mem_offset, 4*8
+ 	s_buffer_load_dwordx8	s, s_rsrc, s_mem_offset glc:1
+-	s_sub_u32	s_mem_offset, s_mem_offset, 4*16
+ end
+ 
+-function read_2sgpr_from_mem(s, s_rsrc, s_mem_offset)
+-	s_buffer_load_dwordx2 s, s_rsrc, s_mem_offset glc:1
+-	s_sub_u32	s_mem_offset, s_mem_offset, 4*8
++function read_4sgpr_from_mem(s, s_rsrc, s_mem_offset)
++	s_sub_u32	s_mem_offset, s_mem_offset, 4*4
++	s_buffer_load_dwordx4	s, s_rsrc, s_mem_offset glc:1
+ end
+ 
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3164-drm-amdkfd-kfd_events-SIGUSR2-interrupt-changes.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3164-drm-amdkfd-kfd_events-SIGUSR2-interrupt-changes.patch
new file mode 100644
index 00000000..01b6f908
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3164-drm-amdkfd-kfd_events-SIGUSR2-interrupt-changes.patch
@@ -0,0 +1,65 @@
+From c3b95d2327d3bf730c28170341eb1de1aba7f9a5 Mon Sep 17 00:00:00 2001
+From: Saleel Kudchadker <Saleel.Kudchadker@amd.com>
+Date: Tue, 23 Jul 2019 14:30:31 -0700
+Subject: [PATCH 3164/4256] drm/amdkfd/kfd_events: SIGUSR2 interrupt changes
+
+Signal SIGUSR2 to parent process only forevent type
+KFD_EVENT_TYPE_DEBUG
+
+Change-Id: I17e3af4d0947027b3fe4e4fb71f0743b37959314
+Signed-off-by: Saleel Kudchadker <Saleel.Kudchadker@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Keuhling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_events.c | 12 +++++++-----
+ 1 file changed, 7 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+index ab76749bf44e..88c05303a30d 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+@@ -495,7 +495,7 @@ static void set_event_from_interrupt(struct kfd_process *p,
+ void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id,
+ 				uint32_t valid_id_bits)
+ {
+-	bool events_signaled = false;
++	bool debug_events_signaled = false;
+ 	struct kfd_event *ev = NULL;
+ 
+ 	/*
+@@ -515,7 +515,7 @@ void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id,
+ 							 valid_id_bits);
+ 	if (ev) {
+ 		set_event_from_interrupt(p, ev);
+-		events_signaled = true;
++		debug_events_signaled |= (ev->type == KFD_EVENT_TYPE_DEBUG);
+ 	} else if (p->signal_page) {
+ 		/*
+ 		 * Partial ID lookup failed. Assume that the event ID
+@@ -539,7 +539,8 @@ void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id,
+ 
+ 				if (slots[id] != UNSIGNALED_EVENT_SLOT) {
+ 					set_event_from_interrupt(p, ev);
+-					events_signaled = true;
++					debug_events_signaled |=
++					(ev->type == KFD_EVENT_TYPE_DEBUG);
+ 				}
+ 			}
+ 		} else {
+@@ -551,11 +552,12 @@ void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id,
+ 				if (slots[id] != UNSIGNALED_EVENT_SLOT) {
+ 					ev = lookup_event_by_id(p, id);
+ 					set_event_from_interrupt(p, ev);
+-					events_signaled = true;
++					debug_events_signaled |=
++					(ev->type == KFD_EVENT_TYPE_DEBUG);
+ 				}
+ 		}
+ 	}
+-	if (events_signaled)
++	if (debug_events_signaled)
+ 		signal_event_to_debugger(p);
+ 
+ 	mutex_unlock(&p->event_mutex);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3165-drm-amd-powerplay-add-smcdpminfo-table-v4_6-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3165-drm-amd-powerplay-add-smcdpminfo-table-v4_6-support.patch
new file mode 100644
index 00000000..eebd16b4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3165-drm-amd-powerplay-add-smcdpminfo-table-v4_6-support.patch
@@ -0,0 +1,115 @@
+From 96be0cef1b429617106a8a7955f3e20066365dd7 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Wed, 10 Jul 2019 09:29:57 +0800
+Subject: [PATCH 3165/4256] drm/amd/powerplay: add smcdpminfo table v4_6
+ support
+
+New smcdpminfo table used in arcturus.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/atomfirmware.h | 86 ++++++++++++++++++++++
+ 1 file changed, 86 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
+index 3ec0aadee03f..73e31c377402 100644
+--- a/drivers/gpu/drm/amd/include/atomfirmware.h
++++ b/drivers/gpu/drm/amd/include/atomfirmware.h
+@@ -1789,6 +1789,92 @@ struct atom_smc_dpm_info_v4_5
+ 
+ };
+ 
++struct atom_smc_dpm_info_v4_6
++{
++  struct   atom_common_table_header  table_header;
++  // section: board parameters
++  uint32_t     i2c_padding[3];   // old i2c control are moved to new area
++
++  uint16_t     maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
++  uint16_t     maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
++
++  uint8_t      vddgfxvrmapping;     // use vr_mapping* bitfields
++  uint8_t      vddsocvrmapping;     // use vr_mapping* bitfields
++  uint8_t      vddmemvrmapping;     // use vr_mapping* bitfields
++  uint8_t      boardvrmapping;      // use vr_mapping* bitfields
++
++  uint8_t      gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode
++  uint8_t      externalsensorpresent; // external rdi connected to tmon (aka temp in)
++  uint8_t      padding8_v[2];
++
++  // telemetry settings
++  uint16_t     gfxmaxcurrent;   // in amps
++  uint8_t      gfxoffset;       // in amps
++  uint8_t      padding_telemetrygfx;
++
++  uint16_t     socmaxcurrent;   // in amps
++  uint8_t      socoffset;       // in amps
++  uint8_t      padding_telemetrysoc;
++
++  uint16_t     memmaxcurrent;   // in amps
++  uint8_t      memoffset;       // in amps
++  uint8_t      padding_telemetrymem;
++
++  uint16_t     boardmaxcurrent;   // in amps
++  uint8_t      boardoffset;       // in amps
++  uint8_t      padding_telemetryboardinput;
++
++  // gpio settings
++  uint8_t      vr0hotgpio;      // gpio pin configured for vr0 hot event
++  uint8_t      vr0hotpolarity;  // gpio polarity for vr0 hot event
++  uint8_t      vr1hotgpio;      // gpio pin configured for vr1 hot event
++  uint8_t      vr1hotpolarity;  // gpio polarity for vr1 hot event
++
++ // gfxclk pll spread spectrum
++  uint8_t	   pllgfxclkspreadenabled;	// on or off
++  uint8_t	   pllgfxclkspreadpercent;	// q4.4
++  uint16_t	   pllgfxclkspreadfreq;		// khz
++
++ // uclk spread spectrum
++  uint8_t	   uclkspreadenabled;   // on or off
++  uint8_t	   uclkspreadpercent;   // q4.4
++  uint16_t	   uclkspreadfreq;	   // khz
++
++ // fclk spread spectrum
++  uint8_t	   fclkspreadenabled;   // on or off
++  uint8_t	   fclkspreadpercent;   // q4.4
++  uint16_t	   fclkspreadfreq;	   // khz
++
++
++  // gfxclk fll spread spectrum
++  uint8_t      fllgfxclkspreadenabled;   // on or off
++  uint8_t      fllgfxclkspreadpercent;   // q4.4
++  uint16_t     fllgfxclkspreadfreq;      // khz
++
++  // i2c controller structure
++  struct smudpm_i2c_controller_config_v2 i2ccontrollers[8];
++
++  // memory section
++  uint32_t	 memorychannelenabled; // for dram use only, max 32 channels enabled bit mask.
++
++  uint8_t 	 drambitwidth; // for dram use only.  see dram bit width type defines
++  uint8_t 	 paddingmem[3];
++
++	// total board power
++  uint16_t	 totalboardpower;	  //only needed for tcp estimated case, where tcp = tgp+total board power
++  uint16_t	 boardpadding;
++
++	// section: xgmi training
++  uint8_t 	 xgmilinkspeed[4];
++  uint8_t 	 xgmilinkwidth[4];
++
++  uint16_t	 xgmifclkfreq[4];
++  uint16_t	 xgmisocvoltage[4];
++
++  // reserved
++  uint32_t   boardreserved[10];
++};
++
+ /* 
+   ***************************************************************************
+     Data Table asic_profiling_info  structure
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3166-drm-amd-powerplay-add-SW-SMU-interface-for-dumping-p.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3166-drm-amd-powerplay-add-SW-SMU-interface-for-dumping-p.patch
new file mode 100644
index 00000000..b2b97360
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3166-drm-amd-powerplay-add-SW-SMU-interface-for-dumping-p.patch
@@ -0,0 +1,56 @@
+From 9b477d148ad39db6e470e1c7806a539636690610 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 30 Jul 2019 22:50:14 -0500
+Subject: [PATCH 3166/4256] drm/amd/powerplay: add SW SMU interface for dumping
+ pptable out (v2)
+
+This is especially useful in early bring up phase.
+
+v2: disabled by default (Alex)
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     | 2 ++
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 +++-
+ 2 files changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 974472015487..c45fa2fb4da9 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1064,6 +1064,8 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ 			return ret;
+ 	}
+ 
++	/* smu_dump_pptable(smu); */
++
+ 	/*
+ 	 * Copy pptable bo in the vram to smc with SMU MSGs such as
+ 	 * SetDriverDramAddr and TransferTableDram2Smu.
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index fcd0db362977..76edb2ccf160 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -449,6 +449,7 @@ struct pptable_funcs {
+ 	int (*set_default_od_settings)(struct smu_context *smu, bool initialize);
+ 	int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
+ 	int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
++	void (*dump_pptable)(struct smu_context *smu);
+ };
+ 
+ struct smu_funcs
+@@ -742,7 +743,8 @@ struct smu_funcs
+ 	((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
+ #define smu_asic_set_performance_level(smu, level) \
+ 	((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
+-
++#define smu_dump_pptable(smu) \
++	((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0)
+ 
+ extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
+ 				   uint16_t *size, uint8_t *frev, uint8_t *crev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3167-drm-amd-powerplay-update-smu11_driver_if_arcturus.h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3167-drm-amd-powerplay-update-smu11_driver_if_arcturus.h.patch
new file mode 100644
index 00000000..a8440607
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3167-drm-amd-powerplay-update-smu11_driver_if_arcturus.h.patch
@@ -0,0 +1,172 @@
+From ca1b0eb5099e7d4078ec933789380eb97d202128 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 12 Jul 2019 16:24:34 +0800
+Subject: [PATCH 3167/4256] drm/amd/powerplay: update
+ smu11_driver_if_arcturus.h
+
+It guides how driver should interface with SMU in arcturus.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../powerplay/inc/smu11_driver_if_arcturus.h  | 58 +++++++++++--------
+ 1 file changed, 33 insertions(+), 25 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+index 7a9969e075d4..c7a7953b52b7 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+@@ -21,16 +21,15 @@
+  *
+  */
+ 
+-
+ #ifndef SMU11_DRIVER_IF_ARCTURUS_H
+ #define SMU11_DRIVER_IF_ARCTURUS_H
+ 
+ // *** IMPORTANT ***
+ // SMU TEAM: Always increment the interface version if
+ // any structure is changed in this file
+-#define SMU11_DRIVER_IF_VERSION 0x06
++#define SMU11_DRIVER_IF_VERSION 0x08
+ 
+-#define PPTABLE_ARCTURUS_SMU_VERSION 3
++#define PPTABLE_ARCTURUS_SMU_VERSION 4
+ 
+ #define NUM_GFXCLK_DPM_LEVELS  16
+ #define NUM_VCLK_DPM_LEVELS    8
+@@ -40,6 +39,7 @@
+ #define NUM_UCLK_DPM_LEVELS    4
+ #define NUM_FCLK_DPM_LEVELS    8
+ #define NUM_XGMI_LEVELS        2
++#define NUM_XGMI_PSTATE_LEVELS 4
+ 
+ #define MAX_GFXCLK_DPM_LEVEL  (NUM_GFXCLK_DPM_LEVELS  - 1)
+ #define MAX_VCLK_DPM_LEVEL    (NUM_VCLK_DPM_LEVELS    - 1)
+@@ -49,6 +49,7 @@
+ #define MAX_UCLK_DPM_LEVEL    (NUM_UCLK_DPM_LEVELS    - 1)
+ #define MAX_FCLK_DPM_LEVEL    (NUM_FCLK_DPM_LEVELS    - 1)
+ #define MAX_XGMI_LEVEL        (NUM_XGMI_LEVELS        - 1)
++#define MAX_XGMI_PSTATE_LEVEL (NUM_XGMI_PSTATE_LEVELS - 1)
+ 
+ // Feature Control Defines
+ // DPM
+@@ -213,8 +214,8 @@
+ #define WORKLOAD_PPLIB_COUNT              5
+ 
+ //XGMI performance states
+-#define XGMI_STATE_D0                      1
+-#define XGMI_STATE_D3                      0
++#define XGMI_STATE_D0 1
++#define XGMI_STATE_D3 0
+ 
+ #define NUM_I2C_CONTROLLERS                8
+ 
+@@ -314,7 +315,6 @@ typedef struct {
+ } SwI2cRequest_t; // SW I2C Request Table
+ 
+ //D3HOT sequences
+-//sequence codes from spec: atlvp4p01.amd.com:1677@//gpu/doc/soc_arch/spec/feature/BACO/Navi/Navi2x/
+ typedef enum {
+   BACO_SEQUENCE,
+   MSR_SEQUENCE,
+@@ -368,6 +368,12 @@ typedef enum {
+   PPCLK_COUNT,
+ } PPCLK_e;
+ 
++typedef enum {
++  POWER_SOURCE_AC,
++  POWER_SOURCE_DC,
++  POWER_SOURCE_COUNT,
++} POWER_SOURCE_e;
++
+ typedef enum {
+   TEMP_EDGE,
+   TEMP_HOTSPOT,
+@@ -568,14 +574,9 @@ typedef struct {
+ 
+   uint16_t          DcBtcGb[AVFS_VOLTAGE_COUNT];        // mV Q2
+ 
+-  uint16_t          SsFmin[10]; // PPtable value to function similar to VFTFmin for SS Curve; Size is PPCLK_COUNT rounded to nearest multiple of 2
+-
+   // SECTION: XGMI
+-  uint8_t           XgmiLinkSpeed   [NUM_XGMI_LEVELS];
+-  uint8_t           XgmiLinkWidth   [NUM_XGMI_LEVELS];
+-
+-  uint16_t          XgmiFclkFreq    [NUM_XGMI_LEVELS];
+-  uint16_t          XgmiSocVoltage  [NUM_XGMI_LEVELS];
++  uint8_t           XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low.  0-P0, 1-P1, 2-P2, 3-P3.
++  uint8_t           XgmiDpmSpare[2];
+ 
+   // Temperature Dependent Vmin
+   uint16_t     VDDGFX_TVmin;       //Celcius
+@@ -683,6 +684,13 @@ typedef struct {
+   uint16_t     TotalBoardPower;     //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
+   uint16_t     BoardPadding;
+ 
++  // SECTION: XGMI Training
++  uint8_t           XgmiLinkSpeed   [NUM_XGMI_PSTATE_LEVELS];
++  uint8_t           XgmiLinkWidth   [NUM_XGMI_PSTATE_LEVELS];
++
++  uint16_t          XgmiFclkFreq    [NUM_XGMI_PSTATE_LEVELS];
++  uint16_t          XgmiSocVoltage  [NUM_XGMI_PSTATE_LEVELS];
++
+   uint32_t     BoardReserved[10];
+ 
+   // Padding for MMHUB - do not modify this
+@@ -698,7 +706,7 @@ typedef struct {
+   uint16_t     GfxActivityLpfTau;
+   uint16_t     UclkActivityLpfTau;
+ 
+-  uint16_t     Padding;
++  uint16_t     SocketPowerLpfTau;
+ 
+   // Padding - ignore
+   uint32_t     MmHubPadding[8]; // SMU internal use
+@@ -715,7 +723,7 @@ typedef struct {
+   uint8_t  CurrGfxVoltageOffset  ;
+   uint8_t  CurrMemVidOffset      ;
+   uint8_t  Padding8              ;
+-  uint16_t CurrSocketPower       ;
++  uint16_t AverageSocketPower    ;
+   uint16_t TemperatureEdge       ;
+   uint16_t TemperatureHotspot    ;
+   uint16_t TemperatureHBM        ;
+@@ -724,23 +732,23 @@ typedef struct {
+   uint16_t TemperatureVrMem      ;
+   uint32_t ThrottlerStatus       ;
+ 
++  uint16_t CurrFanSpeed          ;
++  uint16_t Padding16;
++
++  uint32_t Padding[4];
++
+   // Padding - ignore
+   uint32_t     MmHubPadding[7]; // SMU internal use
+ } SmuMetrics_t;
+ 
+ 
+ typedef struct {
+-  uint16_t avgPsmCount[45];
+-  uint16_t minPsmCount[45];
+-  float    avgPsmVoltage[45];
+-  float    minPsmVoltage[45];
+-
+-  uint16_t avgScsPsmCount;
+-  uint16_t minScsPsmCount;
+-  float    avgScsPsmVoltage;
+-  float    minScsPsmVoltage;
++  uint16_t avgPsmCount[75];
++  uint16_t minPsmCount[75];
++  float    avgPsmVoltage[75];
++  float    minPsmVoltage[75];
+ 
+-  uint32_t MmHubPadding[6]; // SMU internal use
++  uint32_t MmHubPadding[3]; // SMU internal use
+ } AvfsDebugTable_t;
+ 
+ typedef struct {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3168-drm-amd-powerplay-update-arcturus_ppsmc.h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3168-drm-amd-powerplay-update-arcturus_ppsmc.h.patch
new file mode 100644
index 00000000..d9580863
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3168-drm-amd-powerplay-update-arcturus_ppsmc.h.patch
@@ -0,0 +1,51 @@
+From c630821a54b38fe43f35f300e7df2880243dc61b Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 12 Jul 2019 16:28:02 +0800
+Subject: [PATCH 3168/4256] drm/amd/powerplay: update arcturus_ppsmc.h
+
+Correct header and fix typo.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c       | 1 -
+ drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h | 4 ++--
+ 2 files changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 7d680f33ce3c..e995c49afacf 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -80,7 +80,6 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT]
+ 	MSG_MAP(SetPptLimit,			     PPSMC_MSG_SetPptLimit),
+ 	MSG_MAP(GetPptLimit,			     PPSMC_MSG_GetPptLimit),
+ 	MSG_MAP(PowerUpVcn0,			     PPSMC_MSG_PowerUpVcn0),
+-	MSG_MAP(PowerDownVcn01,			     PPSMC_MSG_PowerDownVcn01),
+ 	MSG_MAP(PowerUpVcn1,			     PPSMC_MSG_PowerUpVcn1),
+ 	MSG_MAP(PowerDownVcn1,			     PPSMC_MSG_PowerDownVcn1),
+ 	MSG_MAP(PrepareMp1ForUnload,		     PPSMC_MSG_PrepareMp1ForUnload),
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h
+index b86bb2bc8a31..78e5927b7711 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2018 Advanced Micro Devices, Inc.
++ * Copyright 2019 Advanced Micro Devices, Inc.
+  *
+  * Permission is hereby granted, free of charge, to any person obtaining a
+  * copy of this software and associated documentation files (the "Software"),
+@@ -83,7 +83,7 @@
+ 
+ //Power Gating
+ #define PPSMC_MSG_PowerUpVcn0                    0x28
+-#define PPSMC_MSG_PowerDownVcn01                 0x29
++#define PPSMC_MSG_PowerDownVcn0                  0x29
+ #define PPSMC_MSG_PowerUpVcn1                    0x2A
+ #define PPSMC_MSG_PowerDownVcn1                  0x2B
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3169-drm-amd-powerplay-update-arcturus_ppt.c-h-V3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3169-drm-amd-powerplay-update-arcturus_ppt.c-h-V3.patch
new file mode 100644
index 00000000..c0356c95
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3169-drm-amd-powerplay-update-arcturus_ppt.c-h-V3.patch
@@ -0,0 +1,1329 @@
+From 838f50e42eca9eb6245a3955919397edbecd139e Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 29 Jul 2019 12:43:28 -0500
+Subject: [PATCH 3169/4256] drm/amd/powerplay: update arcturus_ppt.c/h V3
+
+Arcturus ASIC specific powerplay interfaces.
+
+V2: correct SMU msg naming
+    drop unnecessary debugs
+
+V3: rebase (Alex)
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  | 1192 +++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.h  |   44 +
+ drivers/gpu/drm/amd/powerplay/inc/smu_types.h |    2 +-
+ 3 files changed, 1237 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index e995c49afacf..b1c350721ebb 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -33,12 +33,22 @@
+ #include "atom.h"
+ #include "power_state.h"
+ #include "arcturus_ppt.h"
++#include "smu_v11_0_pptable.h"
+ #include "arcturus_ppsmc.h"
+ #include "nbio/nbio_7_4_sh_mask.h"
+ 
++#define CTF_OFFSET_EDGE			5
++#define CTF_OFFSET_HOTSPOT		5
++#define CTF_OFFSET_HBM			5
++
+ #define MSG_MAP(msg, index) \
+ 	[SMU_MSG_##msg] = {1, (index)}
+ 
++#define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
++#define SMU_FEATURES_LOW_SHIFT       0
++#define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
++#define SMU_FEATURES_HIGH_SHIFT      32
++
+ static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
+ 	MSG_MAP(TestMessage,			     PPSMC_MSG_TestMessage),
+ 	MSG_MAP(GetSmuVersion,			     PPSMC_MSG_GetSmuVersion),
+@@ -80,6 +90,7 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT]
+ 	MSG_MAP(SetPptLimit,			     PPSMC_MSG_SetPptLimit),
+ 	MSG_MAP(GetPptLimit,			     PPSMC_MSG_GetPptLimit),
+ 	MSG_MAP(PowerUpVcn0,			     PPSMC_MSG_PowerUpVcn0),
++	MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0),
+ 	MSG_MAP(PowerUpVcn1,			     PPSMC_MSG_PowerUpVcn1),
+ 	MSG_MAP(PowerDownVcn1,			     PPSMC_MSG_PowerDownVcn1),
+ 	MSG_MAP(PrepareMp1ForUnload,		     PPSMC_MSG_PrepareMp1ForUnload),
+@@ -98,6 +109,65 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT]
+ 	MSG_MAP(SetMemoryChannelEnable,		     PPSMC_MSG_SetMemoryChannelEnable),
+ };
+ 
++static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
++	CLK_MAP(GFXCLK, PPCLK_GFXCLK),
++	CLK_MAP(SCLK,	PPCLK_GFXCLK),
++	CLK_MAP(SOCCLK, PPCLK_SOCCLK),
++	CLK_MAP(FCLK, PPCLK_FCLK),
++	CLK_MAP(UCLK, PPCLK_UCLK),
++	CLK_MAP(MCLK, PPCLK_UCLK),
++	CLK_MAP(DCLK, PPCLK_DCLK),
++	CLK_MAP(VCLK, PPCLK_VCLK),
++};
++
++static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
++	FEA_MAP(DPM_PREFETCHER),
++	FEA_MAP(DPM_GFXCLK),
++	FEA_MAP(DPM_UCLK),
++	FEA_MAP(DPM_SOCCLK),
++	FEA_MAP(DPM_MP0CLK),
++	FEA_MAP(DS_GFXCLK),
++	FEA_MAP(DS_SOCCLK),
++	FEA_MAP(DS_LCLK),
++	FEA_MAP(DS_UCLK),
++	FEA_MAP(GFX_ULV),
++	FEA_MAP(RSMU_SMN_CG),
++	FEA_MAP(PPT),
++	FEA_MAP(TDC),
++	FEA_MAP(APCC_PLUS),
++	FEA_MAP(VR0HOT),
++	FEA_MAP(VR1HOT),
++	FEA_MAP(FW_CTF),
++	FEA_MAP(FAN_CONTROL),
++	FEA_MAP(THERMAL),
++	FEA_MAP(OUT_OF_BAND_MONITOR),
++	FEA_MAP(TEMP_DEPENDENT_VMIN),
++};
++
++static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
++	TAB_MAP(PPTABLE),
++	TAB_MAP(AVFS),
++	TAB_MAP(AVFS_PSM_DEBUG),
++	TAB_MAP(AVFS_FUSE_OVERRIDE),
++	TAB_MAP(PMSTATUSLOG),
++	TAB_MAP(SMU_METRICS),
++	TAB_MAP(DRIVER_SMU_CONFIG),
++	TAB_MAP(OVERDRIVE),
++};
++
++static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
++	PWR_MAP(AC),
++	PWR_MAP(DC),
++};
++
++static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
++	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,	WORKLOAD_PPLIB_DEFAULT_BIT),
++	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,		WORKLOAD_PPLIB_POWER_SAVING_BIT),
++	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,		WORKLOAD_PPLIB_VIDEO_BIT),
++	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,		WORKLOAD_PPLIB_CUSTOM_BIT),
++	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
++};
++
+ static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+ {
+ 	struct smu_11_0_cmn2aisc_mapping mapping;
+@@ -114,12 +184,1134 @@ static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+ 	return mapping.map_to;
+ }
+ 
++static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
++{
++	struct smu_11_0_cmn2aisc_mapping mapping;
++
++	if (index >= SMU_CLK_COUNT)
++		return -EINVAL;
++
++	mapping = arcturus_clk_map[index];
++	if (!(mapping.valid_mapping)) {
++		pr_warn("Unsupported SMU clk: %d\n", index);
++		return -EINVAL;
++	}
++
++	return mapping.map_to;
++}
++
++static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)
++{
++	struct smu_11_0_cmn2aisc_mapping mapping;
++
++	if (index >= SMU_FEATURE_COUNT)
++		return -EINVAL;
++
++	mapping = arcturus_feature_mask_map[index];
++	if (!(mapping.valid_mapping)) {
++		pr_warn("Unsupported SMU feature: %d\n", index);
++		return -EINVAL;
++	}
++
++	return mapping.map_to;
++}
++
++static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
++{
++	struct smu_11_0_cmn2aisc_mapping mapping;
++
++	if (index >= SMU_TABLE_COUNT)
++		return -EINVAL;
++
++	mapping = arcturus_table_map[index];
++	if (!(mapping.valid_mapping)) {
++		pr_warn("Unsupported SMU table: %d\n", index);
++		return -EINVAL;
++	}
++
++	return mapping.map_to;
++}
++
++static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
++{
++	struct smu_11_0_cmn2aisc_mapping mapping;
++
++	if (index >= SMU_POWER_SOURCE_COUNT)
++		return -EINVAL;
++
++	mapping = arcturus_pwr_src_map[index];
++	if (!(mapping.valid_mapping)) {
++		pr_warn("Unsupported SMU power source: %d\n", index);
++		return -EINVAL;
++	}
++
++	return mapping.map_to;
++}
++
++
++static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
++{
++	struct smu_11_0_cmn2aisc_mapping mapping;
++
++	if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
++		return -EINVAL;
++
++	mapping = arcturus_workload_map[profile];
++	if (!(mapping.valid_mapping)) {
++		pr_warn("Unsupported SMU power source: %d\n", profile);
++		return -EINVAL;
++	}
++
++	return mapping.map_to;
++}
++
++static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
++{
++	SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
++		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
++
++	SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
++		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
++
++	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
++		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
++
++	return 0;
++}
++
++static int arcturus_allocate_dpm_context(struct smu_context *smu)
++{
++	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
++
++	if (smu_dpm->dpm_context)
++		return -EINVAL;
++
++	smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
++				       GFP_KERNEL);
++	if (!smu_dpm->dpm_context)
++		return -ENOMEM;
++
++	if (smu_dpm->golden_dpm_context)
++		return -EINVAL;
++
++	smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
++					      GFP_KERNEL);
++	if (!smu_dpm->golden_dpm_context)
++		return -ENOMEM;
++
++	smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
++
++	smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
++				       GFP_KERNEL);
++	if (!smu_dpm->dpm_current_power_state)
++		return -ENOMEM;
++
++	smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
++				       GFP_KERNEL);
++	if (!smu_dpm->dpm_request_power_state)
++		return -ENOMEM;
++
++	return 0;
++}
++
++#define FEATURE_MASK(feature) (1ULL << feature)
++static int
++arcturus_get_allowed_feature_mask(struct smu_context *smu,
++				  uint32_t *feature_mask, uint32_t num)
++{
++	if (num > 2)
++		return -EINVAL;
++
++	memset(feature_mask, 0, sizeof(uint32_t) * num);
++
++	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
++				| FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
++
++	return 0;
++}
++
++static int
++arcturus_set_single_dpm_table(struct smu_context *smu,
++			    struct arcturus_single_dpm_table *single_dpm_table,
++			    PPCLK_e clk_id)
++{
++	int ret = 0;
++	uint32_t i, num_of_levels = 0, clk;
++
++	ret = smu_send_smc_msg_with_param(smu,
++			SMU_MSG_GetDpmFreqByIndex,
++			(clk_id << 16 | 0xFF));
++	if (ret) {
++		pr_err("[%s] failed to get dpm levels!\n", __func__);
++		return ret;
++	}
++
++	smu_read_smc_arg(smu, &num_of_levels);
++	if (!num_of_levels) {
++		pr_err("[%s] number of clk levels is invalid!\n", __func__);
++		return -EINVAL;
++	}
++
++	single_dpm_table->count = num_of_levels;
++	for (i = 0; i < num_of_levels; i++) {
++		ret = smu_send_smc_msg_with_param(smu,
++				SMU_MSG_GetDpmFreqByIndex,
++				(clk_id << 16 | i));
++		if (ret) {
++			pr_err("[%s] failed to get dpm freq by index!\n", __func__);
++			return ret;
++		}
++		smu_read_smc_arg(smu, &clk);
++		if (!clk) {
++			pr_err("[%s] clk value is invalid!\n", __func__);
++			return -EINVAL;
++		}
++		single_dpm_table->dpm_levels[i].value = clk;
++		single_dpm_table->dpm_levels[i].enabled = true;
++	}
++	return 0;
++}
++
++static void arcturus_init_single_dpm_state(struct arcturus_dpm_state *dpm_state)
++{
++	dpm_state->soft_min_level = 0x0;
++	dpm_state->soft_max_level = 0xffff;
++        dpm_state->hard_min_level = 0x0;
++        dpm_state->hard_max_level = 0xffff;
++}
++
++static int arcturus_set_default_dpm_table(struct smu_context *smu)
++{
++	int ret;
++
++	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
++	struct arcturus_dpm_table *dpm_table = NULL;
++	struct arcturus_single_dpm_table *single_dpm_table;
++
++	dpm_table = smu_dpm->dpm_context;
++
++	/* socclk */
++	single_dpm_table = &(dpm_table->soc_table);
++	if (smu_feature_is_enabled(smu, FEATURE_DPM_SOCCLK_BIT)) {
++		ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
++						  PPCLK_SOCCLK);
++		if (ret) {
++			pr_err("[%s] failed to get socclk dpm levels!\n", __func__);
++			return ret;
++		}
++	} else {
++		single_dpm_table->count = 1;
++		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
++	}
++	arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
++
++	/* gfxclk */
++	single_dpm_table = &(dpm_table->gfx_table);
++	if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT)) {
++		ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
++						  PPCLK_GFXCLK);
++		if (ret) {
++			pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
++			return ret;
++		}
++	} else {
++		single_dpm_table->count = 1;
++		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
++	}
++	arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
++
++	/* memclk */
++	single_dpm_table = &(dpm_table->mem_table);
++	if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
++		ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
++						  PPCLK_UCLK);
++		if (ret) {
++			pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
++			return ret;
++		}
++	} else {
++		single_dpm_table->count = 1;
++		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
++	}
++	arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
++
++	/* fclk */
++	single_dpm_table = &(dpm_table->fclk_table);
++	if (smu_feature_is_enabled(smu,FEATURE_DPM_FCLK_BIT)) {
++		ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
++						  PPCLK_FCLK);
++		if (ret) {
++			pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
++			return ret;
++		}
++	} else {
++		single_dpm_table->count = 0;
++	}
++	arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
++
++	memcpy(smu_dpm->golden_dpm_context, dpm_table,
++	       sizeof(struct arcturus_dpm_table));
++
++	return 0;
++}
++
++static int arcturus_check_powerplay_table(struct smu_context *smu)
++{
++	return 0;
++}
++
++static int arcturus_store_powerplay_table(struct smu_context *smu)
++{
++	struct smu_11_0_powerplay_table *powerplay_table = NULL;
++	struct smu_table_context *table_context = &smu->smu_table;
++	int ret = 0;
++
++	if (!table_context->power_play_table)
++		return -EINVAL;
++
++	powerplay_table = table_context->power_play_table;
++
++	memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
++	       sizeof(PPTable_t));
++
++	table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
++
++	return ret;
++}
++
++static int arcturus_append_powerplay_table(struct smu_context *smu)
++{
++	struct smu_table_context *table_context = &smu->smu_table;
++	PPTable_t *smc_pptable = table_context->driver_pptable;
++	struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
++	int index, ret;
++
++	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
++					   smc_dpm_info);
++
++	ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
++				      (uint8_t **)&smc_dpm_table);
++	if (ret)
++		return ret;
++
++	pr_info("smc_dpm_info table revision(format.content): %d.%d\n",
++			smc_dpm_table->table_header.format_revision,
++			smc_dpm_table->table_header.content_revision);
++
++	if ((smc_dpm_table->table_header.format_revision == 4) &&
++	    (smc_dpm_table->table_header.content_revision == 6))
++		memcpy(&smc_pptable->MaxVoltageStepGfx,
++		       &smc_dpm_table->maxvoltagestepgfx,
++		       sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
++
++	return 0;
++}
++
++static int arcturus_run_btc_afll(struct smu_context *smu)
++{
++	return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
++}
++
++static int arcturus_populate_umd_state_clk(struct smu_context *smu)
++{
++	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
++	struct arcturus_dpm_table *dpm_table = NULL;
++	struct arcturus_single_dpm_table *gfx_table = NULL;
++	struct arcturus_single_dpm_table *mem_table = NULL;
++
++	dpm_table = smu_dpm->dpm_context;
++	gfx_table = &(dpm_table->gfx_table);
++	mem_table = &(dpm_table->mem_table);
++
++	smu->pstate_sclk = gfx_table->dpm_levels[0].value;
++	smu->pstate_mclk = mem_table->dpm_levels[0].value;
++
++	if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
++	    mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
++		smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
++		smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
++	}
++
++	smu->pstate_sclk = smu->pstate_sclk * 100;
++	smu->pstate_mclk = smu->pstate_mclk * 100;
++
++	return 0;
++}
++
++static int arcturus_get_clk_table(struct smu_context *smu,
++			struct pp_clock_levels_with_latency *clocks,
++			struct arcturus_single_dpm_table *dpm_table)
++{
++	int i, count;
++
++	count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
++	clocks->num_levels = count;
++
++	for (i = 0; i < count; i++) {
++		clocks->data[i].clocks_in_khz =
++			dpm_table->dpm_levels[i].value * 1000;
++		clocks->data[i].latency_in_us = 0;
++	}
++
++	return 0;
++}
++
++static int arcturus_print_clk_levels(struct smu_context *smu,
++			enum smu_clk_type type, char *buf)
++{
++	int i, now, size = 0;
++	int ret = 0;
++	struct pp_clock_levels_with_latency clocks;
++	struct arcturus_single_dpm_table *single_dpm_table;
++	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
++	struct arcturus_dpm_table *dpm_table = NULL;
++
++	dpm_table = smu_dpm->dpm_context;
++
++	switch (type) {
++	case SMU_SCLK:
++		ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
++		if (ret) {
++			pr_err("Attempt to get current gfx clk Failed!");
++			return ret;
++		}
++
++		single_dpm_table = &(dpm_table->gfx_table);
++		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
++		if (ret) {
++			pr_err("Attempt to get gfx clk levels Failed!");
++			return ret;
++		}
++
++		for (i = 0; i < clocks.num_levels; i++)
++			size += sprintf(buf + size, "%d: %uMhz %s\n", i,
++					clocks.data[i].clocks_in_khz / 1000,
++					(clocks.data[i].clocks_in_khz == now * 10)
++					? "*" : "");
++		break;
++
++	case SMU_MCLK:
++		ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
++		if (ret) {
++			pr_err("Attempt to get current mclk Failed!");
++			return ret;
++		}
++
++		single_dpm_table = &(dpm_table->mem_table);
++		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
++		if (ret) {
++			pr_err("Attempt to get memory clk levels Failed!");
++			return ret;
++		}
++
++		for (i = 0; i < clocks.num_levels; i++)
++			size += sprintf(buf + size, "%d: %uMhz %s\n",
++				i, clocks.data[i].clocks_in_khz / 1000,
++				(clocks.data[i].clocks_in_khz == now * 10)
++				? "*" : "");
++		break;
++
++	case SMU_SOCCLK:
++		ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
++		if (ret) {
++			pr_err("Attempt to get current socclk Failed!");
++			return ret;
++		}
++
++		single_dpm_table = &(dpm_table->soc_table);
++		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
++		if (ret) {
++			pr_err("Attempt to get socclk levels Failed!");
++			return ret;
++		}
++
++		for (i = 0; i < clocks.num_levels; i++)
++			size += sprintf(buf + size, "%d: %uMhz %s\n",
++				i, clocks.data[i].clocks_in_khz / 1000,
++				(clocks.data[i].clocks_in_khz == now * 10)
++				? "*" : "");
++		break;
++
++	case SMU_FCLK:
++		ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
++		if (ret) {
++			pr_err("Attempt to get current fclk Failed!");
++			return ret;
++		}
++
++		single_dpm_table = &(dpm_table->fclk_table);
++		for (i = 0; i < single_dpm_table->count; i++)
++			size += sprintf(buf + size, "%d: %uMhz %s\n",
++				i, single_dpm_table->dpm_levels[i].value,
++				(single_dpm_table->dpm_levels[i].value == now / 100)
++				? "*" : "");
++		break;
++
++	default:
++		break;
++	}
++
++	return size;
++}
++
++static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
++				   uint32_t feature_mask)
++{
++	struct arcturus_dpm_table *dpm_table;
++	struct arcturus_single_dpm_table *single_dpm_table;
++	uint32_t freq;
++	int ret = 0;
++
++	dpm_table = smu->smu_dpm.dpm_context;
++	if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT) &&
++	    (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
++		single_dpm_table = &(dpm_table->gfx_table);
++		freq = max ? single_dpm_table->dpm_state.soft_max_level :
++			single_dpm_table->dpm_state.soft_min_level;
++		ret = smu_send_smc_msg_with_param(smu,
++			(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
++			(PPCLK_GFXCLK << 16) | (freq & 0xffff));
++		if (ret) {
++			pr_err("Failed to set soft %s gfxclk !\n",
++						max ? "max" : "min");
++			return ret;
++		}
++	}
++
++	return ret;
++}
++
++static int arcturus_force_clk_levels(struct smu_context *smu,
++			enum smu_clk_type type, uint32_t mask)
++{
++	struct arcturus_dpm_table *dpm_table;
++	struct arcturus_single_dpm_table *single_dpm_table;
++	uint32_t soft_min_level, soft_max_level;
++	int ret = 0;
++
++	mutex_lock(&(smu->mutex));
++
++	soft_min_level = mask ? (ffs(mask) - 1) : 0;
++	soft_max_level = mask ? (fls(mask) - 1) : 0;
++
++	dpm_table = smu->smu_dpm.dpm_context;
++
++	switch (type) {
++	case SMU_SCLK:
++		single_dpm_table = &(dpm_table->gfx_table);
++
++		if (soft_max_level >= single_dpm_table->count) {
++			pr_err("Clock level specified %d is over max allowed %d\n",
++					soft_max_level, single_dpm_table->count - 1);
++			ret = -EINVAL;
++			break;
++		}
++
++		single_dpm_table->dpm_state.soft_min_level =
++			single_dpm_table->dpm_levels[soft_min_level].value;
++		single_dpm_table->dpm_state.soft_max_level =
++			single_dpm_table->dpm_levels[soft_max_level].value;
++
++		ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
++		if (ret) {
++			pr_err("Failed to upload boot level to lowest!\n");
++			break;
++		}
++
++		ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
++		if (ret)
++			pr_err("Failed to upload dpm max level to highest!\n");
++
++		break;
++
++	case SMU_MCLK:
++		single_dpm_table = &(dpm_table->mem_table);
++
++		if (soft_max_level >= single_dpm_table->count) {
++			pr_err("Clock level specified %d is over max allowed %d\n",
++					soft_max_level, single_dpm_table->count - 1);
++			ret = -EINVAL;
++			break;
++		}
++
++		single_dpm_table->dpm_state.soft_min_level =
++			single_dpm_table->dpm_levels[soft_min_level].value;
++		single_dpm_table->dpm_state.soft_max_level =
++			single_dpm_table->dpm_levels[soft_max_level].value;
++
++		ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
++		if (ret) {
++			pr_err("Failed to upload boot level to lowest!\n");
++			break;
++		}
++
++		ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
++		if (ret)
++			pr_err("Failed to upload dpm max level to highest!\n");
++
++		break;
++
++	case SMU_SOCCLK:
++		single_dpm_table = &(dpm_table->soc_table);
++
++		if (soft_max_level >= single_dpm_table->count) {
++			pr_err("Clock level specified %d is over max allowed %d\n",
++					soft_max_level, single_dpm_table->count - 1);
++			ret = -EINVAL;
++			break;
++		}
++
++		single_dpm_table->dpm_state.soft_min_level =
++			single_dpm_table->dpm_levels[soft_min_level].value;
++		single_dpm_table->dpm_state.soft_max_level =
++			single_dpm_table->dpm_levels[soft_max_level].value;
++
++		ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
++		if (ret) {
++			pr_err("Failed to upload boot level to lowest!\n");
++			break;
++		}
++
++		ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
++		if (ret)
++			pr_err("Failed to upload dpm max level to highest!\n");
++
++		break;
++
++	case SMU_FCLK:
++		single_dpm_table = &(dpm_table->fclk_table);
++
++		if (soft_max_level >= single_dpm_table->count) {
++			pr_err("Clock level specified %d is over max allowed %d\n",
++					soft_max_level, single_dpm_table->count - 1);
++			ret = -EINVAL;
++			break;
++		}
++
++		single_dpm_table->dpm_state.soft_min_level =
++			single_dpm_table->dpm_levels[soft_min_level].value;
++		single_dpm_table->dpm_state.soft_max_level =
++			single_dpm_table->dpm_levels[soft_max_level].value;
++
++		ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
++		if (ret) {
++			pr_err("Failed to upload boot level to lowest!\n");
++			break;
++		}
++
++		ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
++		if (ret)
++			pr_err("Failed to upload dpm max level to highest!\n");
++
++		break;
++
++	default:
++		break;
++	}
++
++	mutex_unlock(&(smu->mutex));
++	return ret;
++}
++
++static const struct smu_temperature_range arcturus_thermal_policy[] =
++{
++	{-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
++	{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
++};
++
++static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
++						struct smu_temperature_range *range)
++{
++
++	PPTable_t *pptable = smu->smu_table.driver_pptable;
++
++	if (!range)
++		return -EINVAL;
++
++	memcpy(range, &arcturus_thermal_policy[0], sizeof(struct smu_temperature_range));
++
++	range->max = pptable->TedgeLimit *
++		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
++		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	range->hotspot_crit_max = pptable->ThotspotLimit *
++		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
++		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	range->mem_crit_max = pptable->TmemLimit *
++		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
++		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++
++
++	return 0;
++}
++
++static void arcturus_dump_pptable(struct smu_context *smu)
++{
++	struct smu_table_context *table_context = &smu->smu_table;
++	PPTable_t *pptable = table_context->driver_pptable;
++	int i;
++
++	pr_info("Dumped PPTable:\n");
++
++	pr_info("Version = 0x%08x\n", pptable->Version);
++
++	pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
++	pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
++
++	for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
++		pr_info("SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
++		pr_info("SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
++	}
++
++	pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
++	pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
++	pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
++	pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
++
++	pr_info("TedgeLimit = %d\n", pptable->TedgeLimit);
++	pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit);
++	pr_info("TmemLimit = %d\n", pptable->TmemLimit);
++	pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
++	pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
++	pr_info("Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
++	pr_info("FitLimit = %d\n", pptable->FitLimit);
++
++	pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
++	pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
++
++	pr_info("ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
++
++	pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
++	pr_info("UlvPadding = 0x%08x\n", pptable->UlvPadding);
++
++	pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
++	pr_info("Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
++	pr_info("Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
++	pr_info("Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
++
++	pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
++	pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
++	pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
++	pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
++
++	pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
++	pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
++
++	pr_info("[PPCLK_GFXCLK]\n"
++			"  .VoltageMode          = 0x%02x\n"
++			"  .SnapToDiscrete       = 0x%02x\n"
++			"  .NumDiscreteLevels    = 0x%02x\n"
++			"  .padding              = 0x%02x\n"
++			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
++			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
++			"  .SsFmin               = 0x%04x\n"
++			"  .Padding_16           = 0x%04x\n",
++			pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
++			pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
++			pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
++			pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
++			pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
++			pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
++			pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
++			pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
++			pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
++			pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
++			pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
++
++	pr_info("[PPCLK_VCLK]\n"
++			"  .VoltageMode          = 0x%02x\n"
++			"  .SnapToDiscrete       = 0x%02x\n"
++			"  .NumDiscreteLevels    = 0x%02x\n"
++			"  .padding              = 0x%02x\n"
++			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
++			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
++			"  .SsFmin               = 0x%04x\n"
++			"  .Padding_16           = 0x%04x\n",
++			pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
++			pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
++			pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
++			pptable->DpmDescriptor[PPCLK_VCLK].padding,
++			pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
++			pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
++			pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
++			pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
++			pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
++			pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
++			pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
++
++	pr_info("[PPCLK_DCLK]\n"
++			"  .VoltageMode          = 0x%02x\n"
++			"  .SnapToDiscrete       = 0x%02x\n"
++			"  .NumDiscreteLevels    = 0x%02x\n"
++			"  .padding              = 0x%02x\n"
++			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
++			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
++			"  .SsFmin               = 0x%04x\n"
++			"  .Padding_16           = 0x%04x\n",
++			pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
++			pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
++			pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
++			pptable->DpmDescriptor[PPCLK_DCLK].padding,
++			pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
++			pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
++			pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
++			pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
++			pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
++			pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
++			pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
++
++	pr_info("[PPCLK_SOCCLK]\n"
++			"  .VoltageMode          = 0x%02x\n"
++			"  .SnapToDiscrete       = 0x%02x\n"
++			"  .NumDiscreteLevels    = 0x%02x\n"
++			"  .padding              = 0x%02x\n"
++			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
++			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
++			"  .SsFmin               = 0x%04x\n"
++			"  .Padding_16           = 0x%04x\n",
++			pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
++			pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
++			pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
++			pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
++			pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
++			pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
++			pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
++			pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
++			pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
++			pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
++			pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
++
++	pr_info("[PPCLK_UCLK]\n"
++			"  .VoltageMode          = 0x%02x\n"
++			"  .SnapToDiscrete       = 0x%02x\n"
++			"  .NumDiscreteLevels    = 0x%02x\n"
++			"  .padding              = 0x%02x\n"
++			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
++			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
++			"  .SsFmin               = 0x%04x\n"
++			"  .Padding_16           = 0x%04x\n",
++			pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
++			pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
++			pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
++			pptable->DpmDescriptor[PPCLK_UCLK].padding,
++			pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
++			pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
++			pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
++			pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
++			pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
++			pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
++			pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
++
++	pr_info("[PPCLK_FCLK]\n"
++			"  .VoltageMode          = 0x%02x\n"
++			"  .SnapToDiscrete       = 0x%02x\n"
++			"  .NumDiscreteLevels    = 0x%02x\n"
++			"  .padding              = 0x%02x\n"
++			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
++			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
++			"  .SsFmin               = 0x%04x\n"
++			"  .Padding_16           = 0x%04x\n",
++			pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
++			pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
++			pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
++			pptable->DpmDescriptor[PPCLK_FCLK].padding,
++			pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
++			pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
++			pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
++			pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
++			pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
++			pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
++			pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
++
++
++	pr_info("FreqTableGfx\n");
++	for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
++		pr_info("  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
++
++	pr_info("FreqTableVclk\n");
++	for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
++		pr_info("  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
++
++	pr_info("FreqTableDclk\n");
++	for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
++		pr_info("  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
++
++	pr_info("FreqTableSocclk\n");
++	for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
++		pr_info("  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
++
++	pr_info("FreqTableUclk\n");
++	for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
++		pr_info("  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
++
++	pr_info("FreqTableFclk\n");
++	for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
++		pr_info("  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
++
++	pr_info("Mp0clkFreq\n");
++	for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
++		pr_info("  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
++
++	pr_info("Mp0DpmVoltage\n");
++	for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
++		pr_info("  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
++
++	pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
++	pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
++	pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]);
++	pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]);
++	pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]);
++	pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]);
++	pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
++	pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
++	pr_info("Padding456 = 0x%x\n", pptable->Padding456);
++
++	pr_info("EnableTdpm = %d\n", pptable->EnableTdpm);
++	pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
++	pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
++	pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
++
++	pr_info("FanStopTemp = %d\n", pptable->FanStopTemp);
++	pr_info("FanStartTemp = %d\n", pptable->FanStartTemp);
++
++	pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
++	pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
++	pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
++	pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
++	pr_info("FanGainVrMem = %d\n", pptable->FanGainVrMem);
++	pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
++
++	pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
++	pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
++	pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
++	pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
++	pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
++	pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
++	pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
++	pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
++	pr_info("FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
++
++	pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
++	pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
++	pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
++	pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
++
++	pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
++	pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
++	pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
++	pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
++
++	pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
++			pptable->dBtcGbGfxPll.a,
++			pptable->dBtcGbGfxPll.b,
++			pptable->dBtcGbGfxPll.c);
++	pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
++			pptable->dBtcGbGfxAfll.a,
++			pptable->dBtcGbGfxAfll.b,
++			pptable->dBtcGbGfxAfll.c);
++	pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
++			pptable->dBtcGbSoc.a,
++			pptable->dBtcGbSoc.b,
++			pptable->dBtcGbSoc.c);
++
++	pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
++			pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
++			pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
++	pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
++			pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
++			pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
++
++	pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
++			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
++			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
++			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
++	pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
++			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
++			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
++			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
++
++	pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
++	pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
++
++	pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
++	pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
++	pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
++	pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
++
++	pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
++	pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
++	pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
++	pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
++
++	pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
++	pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
++
++	pr_info("XgmiDpmPstates\n");
++	for (i = 0; i < NUM_XGMI_LEVELS; i++)
++		pr_info("  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
++	pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
++	pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
++
++	pr_info("VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
++	pr_info("VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
++	pr_info("VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
++	pr_info("VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
++	pr_info("VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
++	pr_info("VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
++	pr_info("VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
++	pr_info("VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
++
++	pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
++	pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
++			pptable->ReservedEquation0.a,
++			pptable->ReservedEquation0.b,
++			pptable->ReservedEquation0.c);
++	pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
++			pptable->ReservedEquation1.a,
++			pptable->ReservedEquation1.b,
++			pptable->ReservedEquation1.c);
++	pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
++			pptable->ReservedEquation2.a,
++			pptable->ReservedEquation2.b,
++			pptable->ReservedEquation2.c);
++	pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
++			pptable->ReservedEquation3.a,
++			pptable->ReservedEquation3.b,
++			pptable->ReservedEquation3.c);
++
++	pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
++	pr_info("PaddingUlv = %d\n", pptable->PaddingUlv);
++
++	pr_info("TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
++	pr_info("TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
++	pr_info("TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
++
++	pr_info("PccThresholdLow = %d\n", pptable->PccThresholdLow);
++	pr_info("PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
++
++	pr_info("Board Parameters:\n");
++	pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
++	pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
++
++	pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
++	pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
++	pr_info("VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
++	pr_info("BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
++
++	pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
++	pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
++
++	pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
++	pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
++	pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
++
++	pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
++	pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
++	pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
++
++	pr_info("MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
++	pr_info("MemOffset = 0x%x\n", pptable->MemOffset);
++	pr_info("Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
++
++	pr_info("BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
++	pr_info("BoardOffset = 0x%x\n", pptable->BoardOffset);
++	pr_info("Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
++
++	pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio);
++	pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
++	pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio);
++	pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
++
++	pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
++	pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
++	pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
++
++	pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
++	pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
++	pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
++
++	pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
++	pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
++	pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
++
++	pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
++	pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
++	pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
++
++	for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
++		pr_info("I2cControllers[%d]:\n", i);
++		pr_info("                   .Enabled = %d\n",
++				pptable->I2cControllers[i].Enabled);
++		pr_info("                   .SlaveAddress = 0x%x\n",
++				pptable->I2cControllers[i].SlaveAddress);
++		pr_info("                   .ControllerPort = %d\n",
++				pptable->I2cControllers[i].ControllerPort);
++		pr_info("                   .ControllerName = %d\n",
++				pptable->I2cControllers[i].ControllerName);
++		pr_info("                   .ThermalThrottler = %d\n",
++				pptable->I2cControllers[i].ThermalThrotter);
++		pr_info("                   .I2cProtocol = %d\n",
++				pptable->I2cControllers[i].I2cProtocol);
++		pr_info("                   .Speed = %d\n",
++				pptable->I2cControllers[i].Speed);
++	}
++
++	pr_info("MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
++	pr_info("DramBitWidth = %d\n", pptable->DramBitWidth);
++
++	pr_info("TotalBoardPower = %d\n", pptable->TotalBoardPower);
++
++	pr_info("XgmiLinkSpeed\n");
++	for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
++		pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
++	pr_info("XgmiLinkWidth\n");
++	for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
++		pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
++	pr_info("XgmiFclkFreq\n");
++	for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
++		pr_info("  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
++	pr_info("XgmiSocVoltage\n");
++	for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
++		pr_info("  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
++
++}
++
+ static const struct pptable_funcs arcturus_ppt_funcs = {
++	/* translate smu index into arcturus specific index */
+ 	.get_smu_msg_index = arcturus_get_smu_msg_index,
++	.get_smu_clk_index = arcturus_get_smu_clk_index,
++	.get_smu_feature_index = arcturus_get_smu_feature_index,
++	.get_smu_table_index = arcturus_get_smu_table_index,
++	.get_smu_power_index= arcturus_get_pwr_src_index,
++	.get_workload_type = arcturus_get_workload_type,
++	/* internal structurs allocations */
++	.tables_init = arcturus_tables_init,
++	.alloc_dpm_context = arcturus_allocate_dpm_context,
++	/* pptable related */
++	.check_powerplay_table = arcturus_check_powerplay_table,
++	.store_powerplay_table = arcturus_store_powerplay_table,
++	.append_powerplay_table = arcturus_append_powerplay_table,
++	/* init dpm */
++	.get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
++	/* btc */
++	.run_afll_btc = arcturus_run_btc_afll,
++	/* dpm/clk tables */
++	.set_default_dpm_table = arcturus_set_default_dpm_table,
++	.populate_umd_state_clk = arcturus_populate_umd_state_clk,
++	.get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
++	.print_clk_levels = arcturus_print_clk_levels,
++	.force_clk_levels = arcturus_force_clk_levels,
++	/* debug (internal used) */
++	.dump_pptable = arcturus_dump_pptable,
+ };
+ 
+ void arcturus_set_ppt_funcs(struct smu_context *smu)
+ {
++	struct smu_table_context *smu_table = &smu->smu_table;
++
+ 	smu->ppt_funcs = &arcturus_ppt_funcs;
+ 	smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
++	smu_table->table_count = TABLE_COUNT;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.h b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.h
+index 7b808d091b31..d756b16924b8 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.h
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.h
+@@ -23,6 +23,50 @@
+ #ifndef __ARCTURUS_PPT_H__
+ #define __ARCTURUS_PPT_H__
+ 
++#define ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL         0x3
++#define ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL         0x3
++#define ARCTURUS_UMD_PSTATE_MCLK_LEVEL           0x2
++
++#define MAX_DPM_NUMBER 16
++#define MAX_PCIE_CONF 2
++
++struct arcturus_dpm_level {
++        bool            enabled;
++        uint32_t        value;
++        uint32_t        param1;
++};
++
++struct arcturus_dpm_state {
++        uint32_t  soft_min_level;
++        uint32_t  soft_max_level;
++        uint32_t  hard_min_level;
++        uint32_t  hard_max_level;
++};
++
++struct arcturus_single_dpm_table {
++        uint32_t                count;
++        struct arcturus_dpm_state dpm_state;
++        struct arcturus_dpm_level dpm_levels[MAX_DPM_NUMBER];
++};
++
++struct arcturus_pcie_table {
++        uint16_t count;
++        uint8_t  pcie_gen[MAX_PCIE_CONF];
++        uint8_t  pcie_lane[MAX_PCIE_CONF];
++        uint32_t lclk[MAX_PCIE_CONF];
++};
++
++struct arcturus_dpm_table {
++        struct arcturus_single_dpm_table  soc_table;
++        struct arcturus_single_dpm_table  gfx_table;
++        struct arcturus_single_dpm_table  mem_table;
++        struct arcturus_single_dpm_table  eclk_table;
++        struct arcturus_single_dpm_table  vclk_table;
++        struct arcturus_single_dpm_table  dclk_table;
++        struct arcturus_single_dpm_table  fclk_table;
++        struct arcturus_pcie_table        pcie_table;
++};
++
+ extern void arcturus_set_ppt_funcs(struct smu_context *smu);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+index 8793c8d0dc52..72962e842d69 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+@@ -121,7 +121,7 @@
+        __SMU_DUMMY_MAP(GetVoltageByDpm),              \
+        __SMU_DUMMY_MAP(GetVoltageByDpmOverdrive),     \
+        __SMU_DUMMY_MAP(PowerUpVcn0),                  \
+-       __SMU_DUMMY_MAP(PowerDownVcn01),               \
++       __SMU_DUMMY_MAP(PowerDownVcn0),               \
+        __SMU_DUMMY_MAP(PowerUpVcn1),                  \
+        __SMU_DUMMY_MAP(PowerDownVcn1),                \
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3170-drm-amd-powerplay-enable-SW-SMU-routine-support-for-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3170-drm-amd-powerplay-enable-SW-SMU-routine-support-for-.patch
new file mode 100644
index 00000000..fc3da04d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3170-drm-amd-powerplay-enable-SW-SMU-routine-support-for-.patch
@@ -0,0 +1,111 @@
+From 6f977f9facf0e317e68ae3f99788330b010e7eaa Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 29 Jul 2019 12:50:42 -0500
+Subject: [PATCH 3170/4256] drm/amd/powerplay: enable SW SMU routine support
+ for arcturus
+
+Enable arcturus SW SMU routines.
+
+Change-Id: I2ddba23f12090ac68f440713bc007c671238c54a
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 49 +++++++++++++---------
+ 1 file changed, 30 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index c45fa2fb4da9..8ebfe41a4dc9 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -476,7 +476,7 @@ bool is_support_sw_smu(struct amdgpu_device *adev)
+ {
+ 	if (adev->asic_type == CHIP_VEGA20)
+ 		return (amdgpu_dpm == 2) ? true: false;
+-	else if (adev->asic_type >= CHIP_NAVI10)
++	else if (adev->asic_type >= CHIP_ARCTURUS)
+ 		return true;
+ 	else
+ 		return false;
+@@ -708,6 +708,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
+ 	case CHIP_VEGA20:
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_ARCTURUS:
+ 		if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
+ 			smu->od_enabled = true;
+ 		smu_v11_0_set_smu_funcs(smu);
+@@ -1013,9 +1014,11 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ 		return 0;
+ 	}
+ 
+-	ret = smu_init_display_count(smu, 0);
+-	if (ret)
+-		return ret;
++	if (adev->asic_type != CHIP_ARCTURUS) {
++		ret = smu_init_display_count(smu, 0);
++		if (ret)
++			return ret;
++	}
+ 
+ 	if (initialize) {
+ 		/* get boot_values from vbios to set revision, gfxclk, and etc. */
+@@ -1091,17 +1094,19 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ 	if (ret)
+ 		return ret;
+ 
+-	ret = smu_notify_display_change(smu);
+-	if (ret)
+-		return ret;
++	if (adev->asic_type != CHIP_ARCTURUS) {
++		ret = smu_notify_display_change(smu);
++		if (ret)
++			return ret;
+ 
+-	/*
+-	 * Set min deep sleep dce fclk with bootup value from vbios via
+-	 * SetMinDeepSleepDcefclk MSG.
+-	 */
+-	ret = smu_set_min_dcef_deep_sleep(smu);
+-	if (ret)
+-		return ret;
++		/*
++		 * Set min deep sleep dce fclk with bootup value from vbios via
++		 * SetMinDeepSleepDcefclk MSG.
++		 */
++		ret = smu_set_min_dcef_deep_sleep(smu);
++		if (ret)
++			return ret;
++	}
+ 
+ 	/*
+ 	 * Set initialized values (get from vbios) to dpm tables context such as
+@@ -1212,14 +1217,20 @@ static int smu_hw_init(void *handle)
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 	struct smu_context *smu = &adev->smu;
+ 
+-	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+-		ret = smu_check_fw_status(smu);
+-		if (ret) {
+-			pr_err("SMC firmware status is not correct\n");
+-			return ret;
++	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
++		if (adev->asic_type < CHIP_NAVI10) {
++			ret = smu_load_microcode(smu);
++			if (ret)
++				return ret;
+ 		}
+ 	}
+ 
++	ret = smu_check_fw_status(smu);
++	if (ret) {
++		pr_err("SMC firmware status is not correct\n");
++		return ret;
++	}
++
+ 	if (!smu->pm_enabled)
+ 		return 0;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3171-drm-amd-powerplay-initialize-arcturus-MP1-and-THM-ba.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3171-drm-amd-powerplay-initialize-arcturus-MP1-and-THM-ba.patch
new file mode 100644
index 00000000..a868854f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3171-drm-amd-powerplay-initialize-arcturus-MP1-and-THM-ba.patch
@@ -0,0 +1,38 @@
+From 8a84125bc53d28ede782c5d21ae771ee3ea5f6df Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 12 Jul 2019 16:50:52 +0800
+Subject: [PATCH 3171/4256] drm/amd/powerplay: initialize arcturus MP1 and THM
+ base address
+
+Initialize base address for those IPs which are used in powerplay.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/arct_reg_init.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c b/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c
+index 51b8cdffb196..4853899b1824 100644
+--- a/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c
++++ b/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c
+@@ -38,6 +38,7 @@ int arct_reg_base_init(struct amdgpu_device *adev)
+ 		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
+ 		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
+ 		adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
++		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
+ 		adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
+ 		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
+ 		adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
+@@ -50,6 +51,7 @@ int arct_reg_base_init(struct amdgpu_device *adev)
+ 		adev->reg_offset[SDMA6_HWIP][i] = (uint32_t *)(&(SDMA6_BASE.instance[i]));
+ 		adev->reg_offset[SDMA7_HWIP][i] = (uint32_t *)(&(SDMA7_BASE.instance[i]));
+ 		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
++		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
+ 	}
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3172-drm-amd-powerplay-enable-arcturus-powerplay.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3172-drm-amd-powerplay-enable-arcturus-powerplay.patch
new file mode 100644
index 00000000..654176a2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3172-drm-amd-powerplay-enable-arcturus-powerplay.patch
@@ -0,0 +1,29 @@
+From 4a06d609f12dc58e3328c080c9b6d7f1a85192da Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 12 Jul 2019 16:53:28 +0800
+Subject: [PATCH 3172/4256] drm/amd/powerplay: enable arcturus powerplay
+
+Arcturus powerplay is ready to use.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 4405b983dd09..347a44f2757a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -696,6 +696,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
++		amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
+ 		break;
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3173-drm-amdgpu-correct-VCN-powergate-routine-for-acturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3173-drm-amdgpu-correct-VCN-powergate-routine-for-acturus.patch
new file mode 100644
index 00000000..d6248ba2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3173-drm-amdgpu-correct-VCN-powergate-routine-for-acturus.patch
@@ -0,0 +1,41 @@
+From e85f552c6e29f8e826fbd065bd37b57814c18ffb Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 16 Jul 2019 11:03:10 +0800
+Subject: [PATCH 3173/4256] drm/amdgpu: correct VCN powergate routine for
+ acturus
+
+Arcturus VCN should powergate in the way as Navi.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+index be34bdc47174..21ca8e0ab8b6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+@@ -304,7 +304,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
+ 
+ 	if (fences == 0) {
+ 		amdgpu_gfx_off_ctrl(adev, true);
+-		if (adev->asic_type < CHIP_NAVI10 && adev->pm.dpm_enabled)
++		if (adev->asic_type < CHIP_ARCTURUS && adev->pm.dpm_enabled)
+ 			amdgpu_dpm_enable_uvd(adev, false);
+ 		else
+ 			amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
+@@ -321,7 +321,7 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
+ 
+ 	if (set_clocks) {
+ 		amdgpu_gfx_off_ctrl(adev, false);
+-		if (adev->asic_type < CHIP_NAVI10 && adev->pm.dpm_enabled)
++		if (adev->asic_type < CHIP_ARCTURUS && adev->pm.dpm_enabled)
+ 			amdgpu_dpm_enable_uvd(adev, true);
+ 		else
+ 			amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3174-drm-amd-powerplay-hold-on-the-arcturus-gfx-dpm-suppo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3174-drm-amd-powerplay-hold-on-the-arcturus-gfx-dpm-suppo.patch
new file mode 100644
index 00000000..9253ccf8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3174-drm-amd-powerplay-hold-on-the-arcturus-gfx-dpm-suppo.patch
@@ -0,0 +1,33 @@
+From d4f757b240eee85b497af0cbc80d78bf60ce0cec Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Wed, 17 Jul 2019 09:34:13 +0800
+Subject: [PATCH 3174/4256] drm/amd/powerplay: hold on the arcturus gfx dpm
+ support in driver
+
+As for now, only "Prefetcher" is guarded to be working from
+SMU firmware.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index b1c350721ebb..66f89dabc914 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -324,8 +324,7 @@ arcturus_get_allowed_feature_mask(struct smu_context *smu,
+ 
+ 	memset(feature_mask, 0, sizeof(uint32_t) * num);
+ 
+-	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
+-				| FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
++	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT);
+ 
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3175-drm-amd-include-adjust-base-offset-of-SMUIO-and-THM-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3175-drm-amd-include-adjust-base-offset-of-SMUIO-and-THM-.patch
new file mode 100644
index 00000000..be437490
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3175-drm-amd-include-adjust-base-offset-of-SMUIO-and-THM-.patch
@@ -0,0 +1,44 @@
+From 1cc257ac713d4855e1e02b8147f5859580746a09 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Mon, 15 Jul 2019 18:00:50 +0800
+Subject: [PATCH 3175/4256] drm/amd/include: adjust base offset of SMUIO and
+ THM for Arcturus
+
+Arcturus has different _BASE_IDX value in some HWIP_offset.h. To make source
+files like smu_v11_0.c and soc15.c that include HWIP_offset.h of Vega20
+reusable for Arcturus, align this base offset with Vega20.
+
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/arct_ip_offset.h | 8 ++------
+ 1 file changed, 2 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/include/arct_ip_offset.h b/drivers/gpu/drm/amd/include/arct_ip_offset.h
+index 3211b3a96d68..a7791a9e1f90 100644
+--- a/drivers/gpu/drm/amd/include/arct_ip_offset.h
++++ b/drivers/gpu/drm/amd/include/arct_ip_offset.h
+@@ -196,17 +196,13 @@ static const struct IP_BASE SDMA7_BASE            ={ { { { 0x00013800, 0x0001F40
+                                         { { 0, 0, 0, 0, 0, 0 } },
+                                         { { 0, 0, 0, 0, 0, 0 } },
+                                         { { 0, 0, 0, 0, 0, 0 } } } };
+-static const struct IP_BASE SMUIO_BASE            ={ { { { 0x00012080, 0x00016800, 0x00016A00, 0x00401000, 0x00440000, 0 } },
+-                                        { { 0, 0, 0, 0, 0, 0 } },
+-                                        { { 0, 0, 0, 0, 0, 0 } },
++static const struct IP_BASE SMUIO_BASE            ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } },
+                                         { { 0, 0, 0, 0, 0, 0 } },
+                                         { { 0, 0, 0, 0, 0, 0 } },
+                                         { { 0, 0, 0, 0, 0, 0 } },
+                                         { { 0, 0, 0, 0, 0, 0 } },
+                                         { { 0, 0, 0, 0, 0, 0 } } } };
+-static const struct IP_BASE THM_BASE            ={ { { { 0x00012060, 0x00016600, 0x00400C00, 0, 0, 0 } },
+-                                        { { 0, 0, 0, 0, 0, 0 } },
+-                                        { { 0, 0, 0, 0, 0, 0 } },
++static const struct IP_BASE THM_BASE            ={ { { { 0x00016600, 0, 0, 0, 0, 0 } },
+                                         { { 0, 0, 0, 0, 0, 0 } },
+                                         { { 0, 0, 0, 0, 0, 0 } },
+                                         { { 0, 0, 0, 0, 0, 0 } },
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3176-drm-amdgpu-update-more-sdma-instances-irq-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3176-drm-amdgpu-update-more-sdma-instances-irq-support.patch
new file mode 100644
index 00000000..91566d6e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3176-drm-amdgpu-update-more-sdma-instances-irq-support.patch
@@ -0,0 +1,176 @@
+From cd33457f0a0bd14fca5c2d6f1ec69795c8f2b4e1 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Tue, 16 Jul 2019 15:21:54 +0800
+Subject: [PATCH 3176/4256] drm/amdgpu: update more sdma instances irq support
+
+Update for sdma ras ecc_irq and other minors.
+
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 77 +++++++++-----------------
+ 1 file changed, 27 insertions(+), 50 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 2ddeff86aaea..2876cdabef41 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -295,7 +295,7 @@ static unsigned sdma_v4_0_seq_to_irq_id(int seq_num)
+ 	default:
+ 		break;
+ 	}
+-	return 0;
++	return -EINVAL;
+ }
+ 
+ static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
+@@ -320,7 +320,7 @@ static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
+ 	default:
+ 		break;
+ 	}
+-	return 0;
++	return -EINVAL;
+ }
+ 
+ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
+@@ -1645,7 +1645,7 @@ static int sdma_v4_0_late_init(void *handle)
+ 		.sub_block_index = 0,
+ 		.name = "sdma",
+ 	};
+-	int r;
++	int r, i;
+ 
+ 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
+ 		amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0);
+@@ -1702,14 +1702,11 @@ static int sdma_v4_0_late_init(void *handle)
+ 	if (r)
+ 		goto sysfs;
+ resume:
+-	r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE0);
+-	if (r)
+-		goto irq;
+-
+-	r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE1);
+-	if (r) {
+-		amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE0);
+-		goto irq;
++	for (i = 0; i < adev->sdma.num_instances; i++) {
++		r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq,
++			sdma_v4_0_seq_to_irq_id(i));
++		if (r)
++			goto irq;
+ 	}
+ 
+ 	return 0;
+@@ -1742,16 +1739,13 @@ static int sdma_v4_0_sw_init(void *handle)
+ 	}
+ 
+ 	/* SDMA SRAM ECC event */
+-	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
+-			&adev->sdma.ecc_irq);
+-	if (r)
+-		return r;
+-
+-	/* SDMA SRAM ECC event */
+-	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_SRAM_ECC,
+-			&adev->sdma.ecc_irq);
+-	if (r)
+-		return r;
++	for (i = 0; i < adev->sdma.num_instances; i++) {
++		r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
++				      SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
++				      &adev->sdma.ecc_irq);
++		if (r)
++			return r;
++	}
+ 
+ 	for (i = 0; i < adev->sdma.num_instances; i++) {
+ 		ring = &adev->sdma.instance[i].ring;
+@@ -1784,9 +1778,7 @@ static int sdma_v4_0_sw_init(void *handle)
+ 			sprintf(ring->name, "page%d", i);
+ 			r = amdgpu_ring_init(adev, ring, 1024,
+ 					     &adev->sdma.trap_irq,
+-					     (i == 0) ?
+-					     AMDGPU_SDMA_IRQ_INSTANCE0 :
+-					     AMDGPU_SDMA_IRQ_INSTANCE1);
++					     AMDGPU_SDMA_IRQ_INSTANCE0 + i);
+ 			if (r)
+ 				return r;
+ 		}
+@@ -1849,12 +1841,15 @@ static int sdma_v4_0_hw_init(void *handle)
+ static int sdma_v4_0_hw_fini(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	int i;
+ 
+ 	if (amdgpu_sriov_vf(adev))
+ 		return 0;
+ 
+-	amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE0);
+-	amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE1);
++	for (i = 0; i < adev->sdma.num_instances; i++) {
++		amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
++			sdma_v4_0_seq_to_irq_id(i));
++	}
+ 
+ 	sdma_v4_0_ctx_switch_enable(adev, false);
+ 	sdma_v4_0_enable(adev, false);
+@@ -1968,16 +1963,9 @@ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
+ {
+ 	uint32_t instance, err_source;
+ 
+-	switch (entry->client_id) {
+-	case SOC15_IH_CLIENTID_SDMA0:
+-		instance = 0;
+-		break;
+-	case SOC15_IH_CLIENTID_SDMA1:
+-		instance = 1;
+-		break;
+-	default:
++	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
++	if (instance < 0)
+ 		return 0;
+-	}
+ 
+ 	switch (entry->src_id) {
+ 	case SDMA0_4_0__SRCID__SDMA_SRAM_ECC:
+@@ -2023,16 +2011,9 @@ static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
+ 
+ 	DRM_ERROR("Illegal instruction in SDMA command stream\n");
+ 
+-	switch (entry->client_id) {
+-	case SOC15_IH_CLIENTID_SDMA0:
+-		instance = 0;
+-		break;
+-	case SOC15_IH_CLIENTID_SDMA1:
+-		instance = 1;
+-		break;
+-	default:
++	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
++	if (instance < 0)
+ 		return 0;
+-	}
+ 
+ 	switch (entry->ring_id) {
+ 	case 0:
+@@ -2049,14 +2030,10 @@ static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev,
+ {
+ 	u32 sdma_edc_config;
+ 
+-	u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
+-		sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_EDC_CONFIG) :
+-		sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_EDC_CONFIG);
+-
+-	sdma_edc_config = RREG32(reg_offset);
++	sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG);
+ 	sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,
+ 		       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+-	WREG32(reg_offset, sdma_edc_config);
++	WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config);
+ 
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3177-drm-amd-powerplay-add-new-sensor-type-for-VCN-powerg.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3177-drm-amd-powerplay-add-new-sensor-type-for-VCN-powerg.patch
new file mode 100644
index 00000000..58b46a2e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3177-drm-amd-powerplay-add-new-sensor-type-for-VCN-powerg.patch
@@ -0,0 +1,31 @@
+From cf86d2c50588f5f67131804f6267474919645a72 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 22 Jul 2019 09:51:59 +0800
+Subject: [PATCH 3177/4256] drm/amd/powerplay: add new sensor type for VCN
+ powergate status
+
+VCN is widely used in new ASICs and different from tranditional
+UVD and VCE.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+index 95edc3d3a9c4..bba1291ae405 100644
+--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
++++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+@@ -123,6 +123,7 @@ enum amd_pp_sensors {
+ 	AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
+ 	AMDGPU_PP_SENSOR_MIN_FAN_RPM,
+ 	AMDGPU_PP_SENSOR_MAX_FAN_RPM,
++	AMDGPU_PP_SENSOR_VCN_POWER_STATE,
+ };
+ 
+ enum amd_pp_task {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3178-drm-amd-powerplay-support-VCN-powergate-status-retri.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3178-drm-amd-powerplay-support-VCN-powergate-status-retri.patch
new file mode 100644
index 00000000..bf9db5cd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3178-drm-amd-powerplay-support-VCN-powergate-status-retri.patch
@@ -0,0 +1,64 @@
+From 5bbdcd5d075f49d136893b2c7b5ce7a2bea379fa Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 22 Jul 2019 09:55:36 +0800
+Subject: [PATCH 3178/4256] drm/amd/powerplay: support VCN powergate status
+ retrieval on Raven
+
+Enable VCN powergate status report on Raven.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+index e32ae9d3373c..18e780f566fa 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+@@ -1111,6 +1111,7 @@ static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
+ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
+ 			  void *value, int *size)
+ {
++	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
+ 	uint32_t sclk, mclk;
+ 	int ret = 0;
+ 
+@@ -1132,6 +1133,10 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
+ 	case AMDGPU_PP_SENSOR_GPU_TEMP:
+ 		*((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);
+ 		break;
++	case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
++		*(uint32_t *)value =  smu10_data->vcn_power_gated ? 0 : 1;
++		*size = 4;
++		break;
+ 	default:
+ 		ret = -EINVAL;
+ 		break;
+@@ -1175,18 +1180,22 @@ static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)
+ 
+ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
+ {
++	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
++
+ 	if (bgate) {
+ 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,
+ 						AMD_IP_BLOCK_TYPE_VCN,
+ 						AMD_PG_STATE_GATE);
+ 		smum_send_msg_to_smc_with_parameter(hwmgr,
+ 					PPSMC_MSG_PowerDownVcn, 0);
++		smu10_data->vcn_power_gated = true;
+ 	} else {
+ 		smum_send_msg_to_smc_with_parameter(hwmgr,
+ 						PPSMC_MSG_PowerUpVcn, 0);
+ 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,
+ 						AMD_IP_BLOCK_TYPE_VCN,
+ 						AMD_PG_STATE_UNGATE);
++		smu10_data->vcn_power_gated = false;
+ 	}
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3179-drm-amd-powerplay-support-VCN-powergate-status-retri.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3179-drm-amd-powerplay-support-VCN-powergate-status-retri.patch
new file mode 100644
index 00000000..1aaa4d80
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3179-drm-amd-powerplay-support-VCN-powergate-status-retri.patch
@@ -0,0 +1,33 @@
+From 3888f3b78967de759444b11d3aa332ea2c949c3b Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 22 Jul 2019 09:57:27 +0800
+Subject: [PATCH 3179/4256] drm/amd/powerplay: support VCN powergate status
+ retrieval for SW SMU
+
+Commonly used for VCN powergate status retrieval for SW SMU.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 8ebfe41a4dc9..3f615d4624c7 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -424,6 +424,10 @@ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
+ 		*(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
+ 		*size = 4;
+ 		break;
++	case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
++		*(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT) ? 1 : 0;
++		*size = 4;
++		break;
+ 	default:
+ 		ret = -EINVAL;
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3180-drm-amd-powerplay-correct-Navi10-VCN-powergate-contr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3180-drm-amd-powerplay-correct-Navi10-VCN-powergate-contr.patch
new file mode 100644
index 00000000..62f4c0d6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3180-drm-amd-powerplay-correct-Navi10-VCN-powergate-contr.patch
@@ -0,0 +1,65 @@
+From 1f4ef5c2e1441732f0921c62948da10ffd5673e5 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 22 Jul 2019 10:27:21 +0800
+Subject: [PATCH 3180/4256] drm/amd/powerplay: correct Navi10 VCN powergate
+ control (v2)
+
+No VCN DPM bit check as that's different from VCN PG. Also
+no extra check for possible double enablement/disablement
+as that's already done by VCN.
+
+v2: check return value of smu_feature_set_enabled
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 28 ++++++++--------------
+ 1 file changed, 10 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 7706c8e0cfbe..f04a54e8e164 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -591,28 +591,20 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
+ static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
+ {
+ 	int ret = 0;
+-	struct smu_power_context *smu_power = &smu->smu_power;
+-	struct smu_power_gate *power_gate = &smu_power->power_gate;
+ 
+-	if (enable && power_gate->uvd_gated) {
+-		if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
+-			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
+-			if (ret)
+-				return ret;
+-		}
+-		power_gate->uvd_gated = false;
++	if (enable) {
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
++		if (ret)
++			return ret;
+ 	} else {
+-		if (!enable && !power_gate->uvd_gated) {
+-			if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
+-				ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
+-				if (ret)
+-					return ret;
+-			}
+-			power_gate->uvd_gated = true;
+-		}
++		ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
++		if (ret)
++			return ret;
+ 	}
+ 
+-	return 0;
++	ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, enable);
++
++	return ret;
+ }
+ 
+ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3181-drm-amd-powerplay-correct-UVD-VCE-VCN-power-status-r.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3181-drm-amd-powerplay-correct-UVD-VCE-VCN-power-status-r.patch
new file mode 100644
index 00000000..8fb1fc15
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3181-drm-amd-powerplay-correct-UVD-VCE-VCN-power-status-r.patch
@@ -0,0 +1,88 @@
+From 0288a2898fcdb948a8be9bd37a34828fbbb7798c Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 22 Jul 2019 10:42:29 +0800
+Subject: [PATCH 3181/4256] drm/amd/powerplay: correct UVD/VCE/VCN power status
+ retrieval
+
+VCN should be used for Vega20 later ASICs while UVD and VCE
+are for previous ASICs.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 56 +++++++++++++++++---------
+ 1 file changed, 36 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index 783cd0192d33..6cff61802400 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -3070,28 +3070,44 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a
+ 	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
+ 		seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
+ 
+-	/* UVD clocks */
+-	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
+-		if (!value) {
+-			seq_printf(m, "UVD: Disabled\n");
+-		} else {
+-			seq_printf(m, "UVD: Enabled\n");
+-			if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
+-				seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
+-			if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
+-				seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
++	if (adev->asic_type > CHIP_VEGA20) {
++		/* VCN clocks */
++		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
++			if (!value) {
++				seq_printf(m, "VCN: Disabled\n");
++			} else {
++				seq_printf(m, "VCN: Enabled\n");
++				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
++					seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
++				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
++					seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
++			}
+ 		}
+-	}
+-	seq_printf(m, "\n");
++		seq_printf(m, "\n");
++	} else {
++		/* UVD clocks */
++		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
++			if (!value) {
++				seq_printf(m, "UVD: Disabled\n");
++			} else {
++				seq_printf(m, "UVD: Enabled\n");
++				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
++					seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
++				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
++					seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
++			}
++		}
++		seq_printf(m, "\n");
+ 
+-	/* VCE clocks */
+-	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
+-		if (!value) {
+-			seq_printf(m, "VCE: Disabled\n");
+-		} else {
+-			seq_printf(m, "VCE: Enabled\n");
+-			if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
+-				seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
++		/* VCE clocks */
++		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
++			if (!value) {
++				seq_printf(m, "VCE: Disabled\n");
++			} else {
++				seq_printf(m, "VCE: Enabled\n");
++				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
++					seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
++			}
+ 		}
+ 	}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3182-drm-amd-powerplay-init-arcturus-SMU-metrics-table-on.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3182-drm-amd-powerplay-init-arcturus-SMU-metrics-table-on.patch
new file mode 100644
index 00000000..f99b9a29
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3182-drm-amd-powerplay-init-arcturus-SMU-metrics-table-on.patch
@@ -0,0 +1,44 @@
+From dad4aebbbec8096c63b53b7a5aee73793f17ea16 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 22 Jul 2019 15:55:52 +0800
+Subject: [PATCH 3182/4256] drm/amd/powerplay: init arcturus SMU metrics table
+ on bootup
+
+Initialize arcturus SMU metrics table.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 66f89dabc914..53199f4046e0 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -267,6 +267,8 @@ static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER
+ 
+ static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
+ {
++	struct smu_table_context *smu_table = &smu->smu_table;
++
+ 	SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
+ 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ 
+@@ -276,6 +278,11 @@ static int arcturus_tables_init(struct smu_context *smu, struct smu_table *table
+ 	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
+ 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ 
++	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
++	if (!smu_table->metrics_table)
++		return -ENOMEM;
++	smu_table->metrics_time = 0;
++
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3183-drm-amd-powerplay-support-sensor-reading-on-arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3183-drm-amd-powerplay-support-sensor-reading-on-arcturus.patch
new file mode 100644
index 00000000..2384fdff
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3183-drm-amd-powerplay-support-sensor-reading-on-arcturus.patch
@@ -0,0 +1,180 @@
+From 2c1deffb5455cc892cc3bd6b9f11801f6e5d6aa2 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 29 Jul 2019 13:18:37 -0500
+Subject: [PATCH 3183/4256] drm/amd/powerplay: support sensor reading on
+ arcturus
+
+Support sensor reading for gpu loading, power and
+temperatures.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 142 +++++++++++++++++++
+ 1 file changed, 142 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 53199f4046e0..6aa7f1f62a81 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -853,6 +853,147 @@ static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
+ 	return 0;
+ }
+ 
++static int arcturus_get_metrics_table(struct smu_context *smu,
++				      SmuMetrics_t *metrics_table)
++{
++	struct smu_table_context *smu_table= &smu->smu_table;
++	int ret = 0;
++
++	if (!smu_table->metrics_time ||
++	     time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
++		ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
++				(void *)smu_table->metrics_table, false);
++		if (ret) {
++			pr_info("Failed to export SMU metrics table!\n");
++			return ret;
++		}
++		smu_table->metrics_time = jiffies;
++	}
++
++	memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
++
++	return ret;
++}
++
++static int arcturus_get_current_activity_percent(struct smu_context *smu,
++						 enum amd_pp_sensors sensor,
++						 uint32_t *value)
++{
++	SmuMetrics_t metrics;
++	int ret = 0;
++
++	if (!value)
++		return -EINVAL;
++
++	ret = arcturus_get_metrics_table(smu, &metrics);
++	if (ret)
++		return ret;
++
++	switch (sensor) {
++	case AMDGPU_PP_SENSOR_GPU_LOAD:
++		*value = metrics.AverageGfxActivity;
++		break;
++	case AMDGPU_PP_SENSOR_MEM_LOAD:
++		*value = metrics.AverageUclkActivity;
++		break;
++	default:
++		pr_err("Invalid sensor for retrieving clock activity\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
++{
++	SmuMetrics_t metrics;
++	int ret = 0;
++
++	if (!value)
++		return -EINVAL;
++
++	ret = arcturus_get_metrics_table(smu, &metrics);
++	if (ret)
++		return ret;
++
++	*value = metrics.AverageSocketPower << 8;
++
++	return 0;
++}
++
++static int arcturus_thermal_get_temperature(struct smu_context *smu,
++					    enum amd_pp_sensors sensor,
++					    uint32_t *value)
++{
++	SmuMetrics_t metrics;
++	int ret = 0;
++
++	if (!value)
++		return -EINVAL;
++
++	ret = arcturus_get_metrics_table(smu, &metrics);
++	if (ret)
++		return ret;
++
++	switch (sensor) {
++	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
++		*value = metrics.TemperatureHotspot *
++			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++		break;
++	case AMDGPU_PP_SENSOR_EDGE_TEMP:
++		*value = metrics.TemperatureEdge *
++			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++		break;
++	case AMDGPU_PP_SENSOR_MEM_TEMP:
++		*value = metrics.TemperatureHBM *
++			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++		break;
++	default:
++		pr_err("Invalid sensor for retrieving temp\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int arcturus_read_sensor(struct smu_context *smu,
++				enum amd_pp_sensors sensor,
++				void *data, uint32_t *size)
++{
++	struct smu_table_context *table_context = &smu->smu_table;
++	PPTable_t *pptable = table_context->driver_pptable;
++	int ret = 0;
++
++	switch (sensor) {
++	case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
++		*(uint32_t *)data = pptable->FanMaximumRpm;
++		*size = 4;
++		break;
++	case AMDGPU_PP_SENSOR_MEM_LOAD:
++	case AMDGPU_PP_SENSOR_GPU_LOAD:
++		ret = arcturus_get_current_activity_percent(smu,
++							    sensor,
++						(uint32_t *)data);
++		*size = 4;
++		break;
++	case AMDGPU_PP_SENSOR_GPU_POWER:
++		ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
++		*size = 4;
++		break;
++	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
++	case AMDGPU_PP_SENSOR_EDGE_TEMP:
++	case AMDGPU_PP_SENSOR_MEM_TEMP:
++		ret = arcturus_thermal_get_temperature(smu, sensor,
++						(uint32_t *)data);
++		*size = 4;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return ret;
++}
++
+ static void arcturus_dump_pptable(struct smu_context *smu)
+ {
+ 	struct smu_table_context *table_context = &smu->smu_table;
+@@ -1309,6 +1450,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 	.get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
+ 	.print_clk_levels = arcturus_print_clk_levels,
+ 	.force_clk_levels = arcturus_force_clk_levels,
++	.read_sensor = arcturus_read_sensor,
+ 	/* debug (internal used) */
+ 	.dump_pptable = arcturus_dump_pptable,
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3184-drm-amd-powerplay-support-real-time-clock-retrieval-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3184-drm-amd-powerplay-support-real-time-clock-retrieval-.patch
new file mode 100644
index 00000000..720a7b44
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3184-drm-amd-powerplay-support-real-time-clock-retrieval-.patch
@@ -0,0 +1,61 @@
+From 9404288acc547c838bb96804be30acd62c2b9e09 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 19 Jul 2019 17:18:34 +0800
+Subject: [PATCH 3184/4256] drm/amd/powerplay: support real-time clock
+ retrieval on arcturus
+
+Enable arcturus real-time clock retrieval.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 24 ++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 6aa7f1f62a81..6d1691d9ac7c 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -994,6 +994,29 @@ static int arcturus_read_sensor(struct smu_context *smu,
+ 	return ret;
+ }
+ 
++static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
++				       enum smu_clk_type clk_type,
++				       uint32_t *value)
++{
++	static SmuMetrics_t metrics;
++	int ret = 0, clk_id = 0;
++
++	if (!value)
++		return -EINVAL;
++
++	clk_id = smu_clk_get_index(smu, clk_type);
++	if (clk_id < 0)
++		return -EINVAL;
++
++	ret = arcturus_get_metrics_table(smu, &metrics);
++	if (ret)
++		return ret;
++
++	*value = metrics.CurrClock[clk_id];
++
++	return ret;
++}
++
+ static void arcturus_dump_pptable(struct smu_context *smu)
+ {
+ 	struct smu_table_context *table_context = &smu->smu_table;
+@@ -1448,6 +1471,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 	.set_default_dpm_table = arcturus_set_default_dpm_table,
+ 	.populate_umd_state_clk = arcturus_populate_umd_state_clk,
+ 	.get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
++	.get_current_clk_freq_by_table = arcturus_get_current_clk_freq_by_table,
+ 	.print_clk_levels = arcturus_print_clk_levels,
+ 	.force_clk_levels = arcturus_force_clk_levels,
+ 	.read_sensor = arcturus_read_sensor,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3185-drm-amd-powerplay-support-fan-speed-retrieval-on-arc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3185-drm-amd-powerplay-support-fan-speed-retrieval-on-arc.patch
new file mode 100644
index 00000000..3b56fc75
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3185-drm-amd-powerplay-support-fan-speed-retrieval-on-arc.patch
@@ -0,0 +1,77 @@
+From 294dede95546ec7066f5446bf7082f83283d17e1 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 22 Jul 2019 12:09:38 +0800
+Subject: [PATCH 3185/4256] drm/amd/powerplay: support fan speed retrieval on
+ arcturus
+
+Support arcturus fan speed retrieval.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 40 ++++++++++++++++++++
+ 1 file changed, 40 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 6d1691d9ac7c..1bdebb77c55b 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -994,6 +994,44 @@ static int arcturus_read_sensor(struct smu_context *smu,
+ 	return ret;
+ }
+ 
++static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
++				      uint32_t *speed)
++{
++	SmuMetrics_t metrics;
++	int ret = 0;
++
++	if (!speed)
++		return -EINVAL;
++
++	ret = arcturus_get_metrics_table(smu, &metrics);
++	if (ret)
++		return ret;
++
++	*speed = metrics.CurrFanSpeed;
++
++	return ret;
++}
++
++static int arcturus_get_fan_speed_percent(struct smu_context *smu,
++					  uint32_t *speed)
++{
++	PPTable_t *pptable = smu->smu_table.driver_pptable;
++	uint32_t percent, current_rpm;
++	int ret = 0;
++
++	if (!speed)
++		return -EINVAL;
++
++	ret = arcturus_get_fan_speed_rpm(smu, &current_rpm);
++	if (ret)
++		return ret;
++
++	percent = current_rpm * 100 / pptable->FanMaximumRpm;
++	*speed = percent > 100 ? 100 : percent;
++
++	return ret;
++}
++
+ static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
+ 				       enum smu_clk_type clk_type,
+ 				       uint32_t *value)
+@@ -1475,6 +1513,8 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 	.print_clk_levels = arcturus_print_clk_levels,
+ 	.force_clk_levels = arcturus_force_clk_levels,
+ 	.read_sensor = arcturus_read_sensor,
++	.get_fan_speed_percent = arcturus_get_fan_speed_percent,
++	.get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
+ 	/* debug (internal used) */
+ 	.dump_pptable = arcturus_dump_pptable,
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3186-drm-amd-powerplay-add-missing-arcturus-feature-maps.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3186-drm-amd-powerplay-add-missing-arcturus-feature-maps.patch
new file mode 100644
index 00000000..0957a24a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3186-drm-amd-powerplay-add-missing-arcturus-feature-maps.patch
@@ -0,0 +1,48 @@
+From e0a2c93c50bd1bb82cd5e0c2dbb3cf1f7be8bd5b Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 22 Jul 2019 16:26:04 +0800
+Subject: [PATCH 3186/4256] drm/amd/powerplay: add missing arcturus feature
+ maps
+
+Add missing feature maps for arcturus.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 1bdebb77c55b..f3930367e7ef 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -43,6 +43,8 @@
+ 
+ #define MSG_MAP(msg, index) \
+ 	[SMU_MSG_##msg] = {1, (index)}
++#define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
++	[smu_feature] = {1, (arcturus_feature)}
+ 
+ #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
+ #define SMU_FEATURES_LOW_SHIFT       0
+@@ -125,12 +127,15 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_CO
+ 	FEA_MAP(DPM_GFXCLK),
+ 	FEA_MAP(DPM_UCLK),
+ 	FEA_MAP(DPM_SOCCLK),
++	FEA_MAP(DPM_FCLK),
+ 	FEA_MAP(DPM_MP0CLK),
+ 	FEA_MAP(DS_GFXCLK),
+ 	FEA_MAP(DS_SOCCLK),
+ 	FEA_MAP(DS_LCLK),
++	FEA_MAP(DS_FCLK),
+ 	FEA_MAP(DS_UCLK),
+ 	FEA_MAP(GFX_ULV),
++	ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
+ 	FEA_MAP(RSMU_SMN_CG),
+ 	FEA_MAP(PPT),
+ 	FEA_MAP(TDC),
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3187-drm-amd-powerplay-correct-the-bitmask-used-in-arctur.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3187-drm-amd-powerplay-correct-the-bitmask-used-in-arctur.patch
new file mode 100644
index 00000000..2f6bc653
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3187-drm-amd-powerplay-correct-the-bitmask-used-in-arctur.patch
@@ -0,0 +1,59 @@
+From bc954784a689e0cdf62357d73f7578cba4363dd3 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 22 Jul 2019 17:03:02 +0800
+Subject: [PATCH 3187/4256] drm/amd/powerplay: correct the bitmask used in
+ arcturus
+
+Those bitmask prefixed by "SMU_" should be used.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index f3930367e7ef..932a3cc7c1bc 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -403,7 +403,7 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu)
+ 
+ 	/* socclk */
+ 	single_dpm_table = &(dpm_table->soc_table);
+-	if (smu_feature_is_enabled(smu, FEATURE_DPM_SOCCLK_BIT)) {
++	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+ 		ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
+ 						  PPCLK_SOCCLK);
+ 		if (ret) {
+@@ -418,7 +418,7 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu)
+ 
+ 	/* gfxclk */
+ 	single_dpm_table = &(dpm_table->gfx_table);
+-	if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT)) {
++	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
+ 		ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
+ 						  PPCLK_GFXCLK);
+ 		if (ret) {
+@@ -433,7 +433,7 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu)
+ 
+ 	/* memclk */
+ 	single_dpm_table = &(dpm_table->mem_table);
+-	if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
++	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
+ 		ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
+ 						  PPCLK_UCLK);
+ 		if (ret) {
+@@ -448,7 +448,7 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu)
+ 
+ 	/* fclk */
+ 	single_dpm_table = &(dpm_table->fclk_table);
+-	if (smu_feature_is_enabled(smu,FEATURE_DPM_FCLK_BIT)) {
++	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
+ 		ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
+ 						  PPCLK_FCLK);
+ 		if (ret) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3188-drm-amd-powerplay-fix-arcturus-real-time-clock-frequ.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3188-drm-amd-powerplay-fix-arcturus-real-time-clock-frequ.patch
new file mode 100644
index 00000000..23b3c1ce
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3188-drm-amd-powerplay-fix-arcturus-real-time-clock-frequ.patch
@@ -0,0 +1,60 @@
+From 359b0648b0975416ff29526fc5df4c398120e555 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 23 Jul 2019 11:42:24 +0800
+Subject: [PATCH 3188/4256] drm/amd/powerplay: fix arcturus real-time clock
+ frequency retrieval
+
+Make sure we can still get the accurate gfxclk/uclk/socclk frequency
+even on dpm disabled.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 30 +++++++++++++++++++-
+ 1 file changed, 29 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 932a3cc7c1bc..ecbc1aad2697 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -1055,7 +1055,35 @@ static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
+ 	if (ret)
+ 		return ret;
+ 
+-	*value = metrics.CurrClock[clk_id];
++	switch (clk_id) {
++	case PPCLK_GFXCLK:
++		/*
++		 * CurrClock[clk_id] can provide accurate
++		 *   output only when the dpm feature is enabled.
++		 * We can use Average_* for dpm disabled case.
++		 *   But this is available for gfxclk/uclk/socclk.
++		 */
++		if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
++			*value = metrics.CurrClock[PPCLK_GFXCLK];
++		else
++			*value = metrics.AverageGfxclkFrequency;
++		break;
++	case PPCLK_UCLK:
++		if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
++			*value = metrics.CurrClock[PPCLK_UCLK];
++		else
++			*value = metrics.AverageUclkFrequency;
++		break;
++	case PPCLK_SOCCLK:
++		if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
++			*value = metrics.CurrClock[PPCLK_SOCCLK];
++		else
++			*value = metrics.AverageSocclkFrequency;
++		break;
++	default:
++		*value = metrics.CurrClock[clk_id];
++		break;
++	}
+ 
+ 	return ret;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3189-drm-amd-powerplay-support-UMD-PSTATE-settings-on-arc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3189-drm-amd-powerplay-support-UMD-PSTATE-settings-on-arc.patch
new file mode 100644
index 00000000..f1c225a2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3189-drm-amd-powerplay-support-UMD-PSTATE-settings-on-arc.patch
@@ -0,0 +1,284 @@
+From 3ae4e8b06db26685081f99595560c8fec81cbef9 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 23 Jul 2019 17:30:35 +0800
+Subject: [PATCH 3189/4256] drm/amd/powerplay: support UMD PSTATE settings on
+ arcturus
+
+Enable arcturus UMD PSTATE support.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 229 ++++++++++++++++++-
+ 1 file changed, 225 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index ecbc1aad2697..79fee8ba32ce 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -666,15 +666,15 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
+ }
+ 
+ static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
+-				   uint32_t feature_mask)
++				     uint32_t feature_mask)
+ {
+-	struct arcturus_dpm_table *dpm_table;
+ 	struct arcturus_single_dpm_table *single_dpm_table;
++	struct arcturus_dpm_table *dpm_table =
++			smu->smu_dpm.dpm_context;
+ 	uint32_t freq;
+ 	int ret = 0;
+ 
+-	dpm_table = smu->smu_dpm.dpm_context;
+-	if (smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT) &&
++	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
+ 	    (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
+ 		single_dpm_table = &(dpm_table->gfx_table);
+ 		freq = max ? single_dpm_table->dpm_state.soft_max_level :
+@@ -689,6 +689,36 @@ static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
+ 		}
+ 	}
+ 
++	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
++	    (feature_mask & FEATURE_DPM_UCLK_MASK)) {
++		single_dpm_table = &(dpm_table->mem_table);
++		freq = max ? single_dpm_table->dpm_state.soft_max_level :
++			single_dpm_table->dpm_state.soft_min_level;
++		ret = smu_send_smc_msg_with_param(smu,
++			(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
++			(PPCLK_UCLK << 16) | (freq & 0xffff));
++		if (ret) {
++			pr_err("Failed to set soft %s memclk !\n",
++						max ? "max" : "min");
++			return ret;
++		}
++	}
++
++	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
++	    (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
++		single_dpm_table = &(dpm_table->soc_table);
++		freq = max ? single_dpm_table->dpm_state.soft_max_level :
++			single_dpm_table->dpm_state.soft_min_level;
++		ret = smu_send_smc_msg_with_param(smu,
++			(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
++			(PPCLK_SOCCLK << 16) | (freq & 0xffff));
++		if (ret) {
++			pr_err("Failed to set soft %s socclk !\n",
++						max ? "max" : "min");
++			return ret;
++		}
++	}
++
+ 	return ret;
+ }
+ 
+@@ -1088,6 +1118,194 @@ static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
+ 	return ret;
+ }
+ 
++static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table *table)
++{
++	uint32_t i;
++
++	for (i = 0; i < table->count; i++) {
++		if (table->dpm_levels[i].enabled)
++			break;
++	}
++	if (i >= table->count) {
++		i = 0;
++		table->dpm_levels[i].enabled = true;
++	}
++
++	return i;
++}
++
++static uint32_t arcturus_find_highest_dpm_level(struct arcturus_single_dpm_table *table)
++{
++	int i = 0;
++
++	if (table->count <= 0) {
++		pr_err("[%s] DPM Table has no entry!", __func__);
++		return 0;
++	}
++	if (table->count > MAX_DPM_NUMBER) {
++		pr_err("[%s] DPM Table has too many entries!", __func__);
++		return MAX_DPM_NUMBER - 1;
++	}
++
++	for (i = table->count - 1; i >= 0; i--) {
++		if (table->dpm_levels[i].enabled)
++			break;
++	}
++	if (i < 0) {
++		i = 0;
++		table->dpm_levels[i].enabled = true;
++	}
++
++	return i;
++}
++
++
++
++static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
++{
++	struct arcturus_dpm_table *dpm_table =
++		(struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
++	uint32_t soft_level;
++	int ret = 0;
++
++	/* gfxclk */
++	if (highest)
++		soft_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
++	else
++		soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
++
++	dpm_table->gfx_table.dpm_state.soft_min_level =
++		dpm_table->gfx_table.dpm_state.soft_max_level =
++		dpm_table->gfx_table.dpm_levels[soft_level].value;
++
++	/* uclk */
++	if (highest)
++		soft_level = arcturus_find_highest_dpm_level(&(dpm_table->mem_table));
++	else
++		soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->mem_table));
++
++	dpm_table->mem_table.dpm_state.soft_min_level =
++		dpm_table->mem_table.dpm_state.soft_max_level =
++		dpm_table->mem_table.dpm_levels[soft_level].value;
++
++	/* socclk */
++	if (highest)
++		soft_level = arcturus_find_highest_dpm_level(&(dpm_table->soc_table));
++	else
++		soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->soc_table));
++
++	dpm_table->soc_table.dpm_state.soft_min_level =
++		dpm_table->soc_table.dpm_state.soft_max_level =
++		dpm_table->soc_table.dpm_levels[soft_level].value;
++
++	ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
++	if (ret) {
++		pr_err("Failed to upload boot level to %s!\n",
++				highest ? "highest" : "lowest");
++		return ret;
++	}
++
++	ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
++	if (ret) {
++		pr_err("Failed to upload dpm max level to %s!\n!",
++				highest ? "highest" : "lowest");
++		return ret;
++	}
++
++	return ret;
++}
++
++static int arcturus_unforce_dpm_levels(struct smu_context *smu)
++{
++	struct arcturus_dpm_table *dpm_table =
++		(struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
++	uint32_t soft_min_level, soft_max_level;
++	int ret = 0;
++
++	/* gfxclk */
++	soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
++	soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
++	dpm_table->gfx_table.dpm_state.soft_min_level =
++		dpm_table->gfx_table.dpm_levels[soft_min_level].value;
++	dpm_table->gfx_table.dpm_state.soft_max_level =
++		dpm_table->gfx_table.dpm_levels[soft_max_level].value;
++
++	/* uclk */
++	soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->mem_table));
++	soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->mem_table));
++	dpm_table->mem_table.dpm_state.soft_min_level =
++		dpm_table->gfx_table.dpm_levels[soft_min_level].value;
++	dpm_table->mem_table.dpm_state.soft_max_level =
++		dpm_table->gfx_table.dpm_levels[soft_max_level].value;
++
++	/* socclk */
++	soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->soc_table));
++	soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->soc_table));
++	dpm_table->soc_table.dpm_state.soft_min_level =
++		dpm_table->soc_table.dpm_levels[soft_min_level].value;
++	dpm_table->soc_table.dpm_state.soft_max_level =
++		dpm_table->soc_table.dpm_levels[soft_max_level].value;
++
++	ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
++	if (ret) {
++		pr_err("Failed to upload DPM Bootup Levels!");
++		return ret;
++	}
++
++	ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
++	if (ret) {
++		pr_err("Failed to upload DPM Max Levels!");
++		return ret;
++	}
++
++	return ret;
++}
++
++static int
++arcturus_get_profiling_clk_mask(struct smu_context *smu,
++				enum amd_dpm_forced_level level,
++				uint32_t *sclk_mask,
++				uint32_t *mclk_mask,
++				uint32_t *soc_mask)
++{
++	struct arcturus_dpm_table *dpm_table =
++		(struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
++	struct arcturus_single_dpm_table *gfx_dpm_table;
++	struct arcturus_single_dpm_table *mem_dpm_table;
++	struct arcturus_single_dpm_table *soc_dpm_table;
++
++	if (!smu->smu_dpm.dpm_context)
++		return -EINVAL;
++
++	gfx_dpm_table = &dpm_table->gfx_table;
++	mem_dpm_table = &dpm_table->mem_table;
++	soc_dpm_table = &dpm_table->soc_table;
++
++	*sclk_mask = 0;
++	*mclk_mask = 0;
++	*soc_mask  = 0;
++
++	if (gfx_dpm_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
++	    mem_dpm_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
++	    soc_dpm_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
++		*sclk_mask = ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL;
++		*mclk_mask = ARCTURUS_UMD_PSTATE_MCLK_LEVEL;
++		*soc_mask  = ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL;
++	}
++
++	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
++		*sclk_mask = 0;
++	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
++		*mclk_mask = 0;
++	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
++		*sclk_mask = gfx_dpm_table->count - 1;
++		*mclk_mask = mem_dpm_table->count - 1;
++		*soc_mask  = soc_dpm_table->count - 1;
++	}
++
++	return 0;
++}
++
+ static void arcturus_dump_pptable(struct smu_context *smu)
+ {
+ 	struct smu_table_context *table_context = &smu->smu_table;
+@@ -1548,6 +1766,9 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 	.read_sensor = arcturus_read_sensor,
+ 	.get_fan_speed_percent = arcturus_get_fan_speed_percent,
+ 	.get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
++	.force_dpm_limit_value = arcturus_force_dpm_limit_value,
++	.unforce_dpm_levels = arcturus_unforce_dpm_levels,
++	.get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
+ 	/* debug (internal used) */
+ 	.dump_pptable = arcturus_dump_pptable,
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3190-drm-amd-powerplay-correct-arcturus-current-clock-lev.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3190-drm-amd-powerplay-correct-arcturus-current-clock-lev.patch
new file mode 100644
index 00000000..c7344845
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3190-drm-amd-powerplay-correct-arcturus-current-clock-lev.patch
@@ -0,0 +1,103 @@
+From 403aba8e48f665aadd567e31b05a902f9a78b0ec Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 23 Jul 2019 20:28:14 +0800
+Subject: [PATCH 3190/4256] drm/amd/powerplay: correct arcturus current clock
+ level calculation
+
+There may be 1Mhz delta between target and actual frequency. That
+should be taken into consideration for current level check.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 35 +++++++++++++++-----
+ 1 file changed, 27 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 79fee8ba32ce..ceb9a85bb1c8 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -51,6 +51,9 @@
+ #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
+ #define SMU_FEATURES_HIGH_SHIFT      32
+ 
++/* possible frequency drift (1Mhz) */
++#define EPSILON				1
++
+ static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
+ 	MSG_MAP(TestMessage,			     PPSMC_MSG_TestMessage),
+ 	MSG_MAP(GetSmuVersion,			     PPSMC_MSG_GetSmuVersion),
+@@ -567,6 +570,12 @@ static int arcturus_get_clk_table(struct smu_context *smu,
+ 	return 0;
+ }
+ 
++static int arcturus_freqs_in_same_level(int32_t frequency1,
++					int32_t frequency2)
++{
++	return (abs(frequency1 - frequency2) <= EPSILON);
++}
++
+ static int arcturus_print_clk_levels(struct smu_context *smu,
+ 			enum smu_clk_type type, char *buf)
+ {
+@@ -597,8 +606,9 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
+ 		for (i = 0; i < clocks.num_levels; i++)
+ 			size += sprintf(buf + size, "%d: %uMhz %s\n", i,
+ 					clocks.data[i].clocks_in_khz / 1000,
+-					(clocks.data[i].clocks_in_khz == now * 10)
+-					? "*" : "");
++					arcturus_freqs_in_same_level(
++					clocks.data[i].clocks_in_khz / 1000,
++					now / 100) ? "*" : "");
+ 		break;
+ 
+ 	case SMU_MCLK:
+@@ -618,8 +628,9 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
+ 		for (i = 0; i < clocks.num_levels; i++)
+ 			size += sprintf(buf + size, "%d: %uMhz %s\n",
+ 				i, clocks.data[i].clocks_in_khz / 1000,
+-				(clocks.data[i].clocks_in_khz == now * 10)
+-				? "*" : "");
++				arcturus_freqs_in_same_level(
++				clocks.data[i].clocks_in_khz / 1000,
++				now / 100) ? "*" : "");
+ 		break;
+ 
+ 	case SMU_SOCCLK:
+@@ -639,8 +650,9 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
+ 		for (i = 0; i < clocks.num_levels; i++)
+ 			size += sprintf(buf + size, "%d: %uMhz %s\n",
+ 				i, clocks.data[i].clocks_in_khz / 1000,
+-				(clocks.data[i].clocks_in_khz == now * 10)
+-				? "*" : "");
++				arcturus_freqs_in_same_level(
++				clocks.data[i].clocks_in_khz / 1000,
++				now / 100) ? "*" : "");
+ 		break;
+ 
+ 	case SMU_FCLK:
+@@ -651,11 +663,18 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
+ 		}
+ 
+ 		single_dpm_table = &(dpm_table->fclk_table);
++		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
++		if (ret) {
++			pr_err("Attempt to get fclk levels Failed!");
++			return ret;
++		}
++
+ 		for (i = 0; i < single_dpm_table->count; i++)
+ 			size += sprintf(buf + size, "%d: %uMhz %s\n",
+ 				i, single_dpm_table->dpm_levels[i].value,
+-				(single_dpm_table->dpm_levels[i].value == now / 100)
+-				? "*" : "");
++				arcturus_freqs_in_same_level(
++				clocks.data[i].clocks_in_khz / 1000,
++				now / 100) ? "*" : "");
+ 		break;
+ 
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3191-drm-amd-powerplay-make-power-limit-retrieval-as-asic.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3191-drm-amd-powerplay-make-power-limit-retrieval-as-asic.patch
new file mode 100644
index 00000000..2d0be82e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3191-drm-amd-powerplay-make-power-limit-retrieval-as-asic.patch
@@ -0,0 +1,291 @@
+From 91d5d2e644a961f4a6cf8cf1040bb6ba5d7d7559 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 30 Jul 2019 22:52:37 -0500
+Subject: [PATCH 3191/4256] drm/amd/powerplay: make power limit retrieval as
+ asic specific
+
+The power limit retrieval should be done per asic. Since we may
+need to lookup in the pptable and that's really asic specific.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  2 +-
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  | 51 +++++++++++++++++
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  4 +-
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 51 +++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 55 ++++---------------
+ 5 files changed, 116 insertions(+), 47 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 3f615d4624c7..330cc3258e61 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1136,7 +1136,7 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ 		if (ret)
+ 			return ret;
+ 
+-		ret = smu_get_power_limit(smu, &smu->default_power_limit, false);
++		ret = smu_get_power_limit(smu, &smu->default_power_limit, true);
+ 		if (ret)
+ 			return ret;
+ 	}
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index ceb9a85bb1c8..97a247a234a8 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -1325,6 +1325,56 @@ arcturus_get_profiling_clk_mask(struct smu_context *smu,
+ 	return 0;
+ }
+ 
++static int arcturus_get_power_limit(struct smu_context *smu,
++				     uint32_t *limit,
++				     bool asic_default)
++{
++	PPTable_t *pptable = smu->smu_table.driver_pptable;
++	uint32_t asic_default_power_limit;
++	int ret = 0;
++	int power_src;
++
++	if (!smu->default_power_limit ||
++	    !smu->power_limit) {
++		if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
++			power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
++			if (power_src < 0)
++				return -EINVAL;
++
++			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
++				power_src << 16);
++			if (ret) {
++				pr_err("[%s] get PPT limit failed!", __func__);
++				return ret;
++			}
++			smu_read_smc_arg(smu, &asic_default_power_limit);
++		} else {
++			/* the last hope to figure out the ppt limit */
++			if (!pptable) {
++				pr_err("Cannot get PPT limit due to pptable missing!");
++				return -EINVAL;
++			}
++			asic_default_power_limit =
++				pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
++		}
++
++		if (smu->od_enabled) {
++			asic_default_power_limit *= (100 + smu->smu_table.TDPODLimit);
++			asic_default_power_limit /= 100;
++		}
++
++		smu->default_power_limit = asic_default_power_limit;
++		smu->power_limit = asic_default_power_limit;
++	}
++
++	if (asic_default)
++		*limit = smu->default_power_limit;
++	else
++		*limit = smu->power_limit;
++
++	return 0;
++}
++
+ static void arcturus_dump_pptable(struct smu_context *smu)
+ {
+ 	struct smu_table_context *table_context = &smu->smu_table;
+@@ -1790,6 +1840,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 	.get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
+ 	/* debug (internal used) */
+ 	.dump_pptable = arcturus_dump_pptable,
++	.get_power_limit = arcturus_get_power_limit,
+ };
+ 
+ void arcturus_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 76edb2ccf160..1ecd73cd768c 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -450,6 +450,7 @@ struct pptable_funcs {
+ 	int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
+ 	int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
+ 	void (*dump_pptable)(struct smu_context *smu);
++	int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool asic_default);
+ };
+ 
+ struct smu_funcs
+@@ -482,7 +483,6 @@ struct smu_funcs
+ 	int (*set_allowed_mask)(struct smu_context *smu);
+ 	int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
+ 	int (*notify_display_change)(struct smu_context *smu);
+-	int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool def);
+ 	int (*set_power_limit)(struct smu_context *smu, uint32_t n);
+ 	int (*get_current_clk_freq)(struct smu_context *smu, enum smu_clk_type clk_id, uint32_t *value);
+ 	int (*init_max_sustainable_clocks)(struct smu_context *smu);
+@@ -611,7 +611,7 @@ struct smu_funcs
+ #define smu_set_default_od8_settings(smu) \
+ 	((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
+ #define smu_get_power_limit(smu, limit, def) \
+-	((smu)->funcs->get_power_limit ? (smu)->funcs->get_power_limit((smu), (limit), (def)) : 0)
++	((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit((smu), (limit), (def)) : 0)
+ #define smu_set_power_limit(smu, limit) \
+ 	((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0)
+ #define smu_get_current_clk_freq(smu, clk_id, value) \
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index f04a54e8e164..f3adb713784a 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1508,6 +1508,56 @@ static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
+ 	return ret;
+ }
+ 
++static int navi10_get_power_limit(struct smu_context *smu,
++				     uint32_t *limit,
++				     bool asic_default)
++{
++	PPTable_t *pptable = smu->smu_table.driver_pptable;
++	uint32_t asic_default_power_limit;
++	int ret = 0;
++	int power_src;
++
++	if (!smu->default_power_limit ||
++	    !smu->power_limit) {
++		if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
++			power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
++			if (power_src < 0)
++				return -EINVAL;
++
++			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
++				power_src << 16);
++			if (ret) {
++				pr_err("[%s] get PPT limit failed!", __func__);
++				return ret;
++			}
++			smu_read_smc_arg(smu, &asic_default_power_limit);
++		} else {
++			/* the last hope to figure out the ppt limit */
++			if (!pptable) {
++				pr_err("Cannot get PPT limit due to pptable missing!");
++				return -EINVAL;
++			}
++			asic_default_power_limit =
++				pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
++		}
++
++		if (smu->od_enabled) {
++			asic_default_power_limit *= (100 + smu->smu_table.TDPODLimit);
++			asic_default_power_limit /= 100;
++		}
++
++		smu->default_power_limit = asic_default_power_limit;
++		smu->power_limit = asic_default_power_limit;
++	}
++
++	if (asic_default)
++		*limit = smu->default_power_limit;
++	else
++		*limit = smu->power_limit;
++
++	return 0;
++}
++
+ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.tables_init = navi10_tables_init,
+ 	.alloc_dpm_context = navi10_allocate_dpm_context,
+@@ -1545,6 +1595,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.set_performance_level = navi10_set_performance_level,
+ 	.get_thermal_temperature_range = navi10_get_thermal_temperature_range,
+ 	.display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
++	.get_power_limit = navi10_get_power_limit,
+ };
+ 
+ void navi10_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 3457e06a5f70..0588dd8cd1ba 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1012,64 +1012,32 @@ static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
+ 	return 0;
+ }
+ 
+-static int smu_v11_0_get_power_limit(struct smu_context *smu,
+-				     uint32_t *limit,
+-				     bool get_default)
++static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
+ {
+ 	int ret = 0;
+-	int power_src;
+ 
+-	power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
+-	if (power_src < 0)
++	if (n > smu->default_power_limit) {
++		pr_err("New power limit is over the max allowed %d\n",
++				smu->default_power_limit);
+ 		return -EINVAL;
+-
+-	if (get_default) {
+-		mutex_lock(&smu->mutex);
+-		*limit = smu->default_power_limit;
+-		if (smu->od_enabled) {
+-			*limit *= (100 + smu->smu_table.TDPODLimit);
+-			*limit /= 100;
+-		}
+-		mutex_unlock(&smu->mutex);
+-	} else {
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
+-			power_src << 16);
+-		if (ret) {
+-			pr_err("[%s] get PPT limit failed!", __func__);
+-			return ret;
+-		}
+-		smu_read_smc_arg(smu, limit);
+-		smu->power_limit = *limit;
+ 	}
+ 
+-	return ret;
+-}
+-
+-static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
+-{
+-	uint32_t max_power_limit;
+-	int ret = 0;
+-
+ 	if (n == 0)
+ 		n = smu->default_power_limit;
+ 
+-	max_power_limit = smu->default_power_limit;
+-
+-	if (smu->od_enabled) {
+-		max_power_limit *= (100 + smu->smu_table.TDPODLimit);
+-		max_power_limit /= 100;
++	if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
++		pr_err("Setting new power limit is not supported!\n");
++		return -EOPNOTSUPP;
+ 	}
+-	if (n > max_power_limit)
+-		return -EINVAL;
+ 
+-	if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
++	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
+ 	if (ret) {
+-		pr_err("[%s] Set power limit Failed!", __func__);
++		pr_err("[%s] Set power limit Failed!\n", __func__);
+ 		return ret;
+ 	}
++	smu->power_limit = n;
+ 
+-	return ret;
++	return 0;
+ }
+ 
+ static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
+@@ -1749,7 +1717,6 @@ static const struct smu_funcs smu_v11_0_funcs = {
+ 	.get_enabled_mask = smu_v11_0_get_enabled_mask,
+ 	.system_features_control = smu_v11_0_system_features_control,
+ 	.notify_display_change = smu_v11_0_notify_display_change,
+-	.get_power_limit = smu_v11_0_get_power_limit,
+ 	.set_power_limit = smu_v11_0_set_power_limit,
+ 	.get_current_clk_freq = smu_v11_0_get_current_clk_freq,
+ 	.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3192-drm-amdgpu-correct-irq-type-used-for-sdma-ecc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3192-drm-amdgpu-correct-irq-type-used-for-sdma-ecc.patch
new file mode 100644
index 00000000..753160d7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3192-drm-amdgpu-correct-irq-type-used-for-sdma-ecc.patch
@@ -0,0 +1,40 @@
+From 2cd794a2612abb253f572cb41dce3020e02c4aa6 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 25 Jul 2019 17:22:01 +0800
+Subject: [PATCH 3192/4256] drm/amdgpu: correct irq type used for sdma ecc
+
+we should pass irq type, instead of irq client id,
+to irq_get/put interface
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 2876cdabef41..1e2f3d949d2e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1704,7 +1704,7 @@ static int sdma_v4_0_late_init(void *handle)
+ resume:
+ 	for (i = 0; i < adev->sdma.num_instances; i++) {
+ 		r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq,
+-			sdma_v4_0_seq_to_irq_id(i));
++				   AMDGPU_SDMA_IRQ_INSTANCE0 + i);
+ 		if (r)
+ 			goto irq;
+ 	}
+@@ -1848,7 +1848,7 @@ static int sdma_v4_0_hw_fini(void *handle)
+ 
+ 	for (i = 0; i < adev->sdma.num_instances; i++) {
+ 		amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
+-			sdma_v4_0_seq_to_irq_id(i));
++			       AMDGPU_SDMA_IRQ_INSTANCE0 + i);
+ 	}
+ 
+ 	sdma_v4_0_ctx_switch_enable(adev, false);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3193-drm-amd-powerplay-determine-the-features-to-enable-b.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3193-drm-amd-powerplay-determine-the-features-to-enable-b.patch
new file mode 100644
index 00000000..48f7546e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3193-drm-amd-powerplay-determine-the-features-to-enable-b.patch
@@ -0,0 +1,44 @@
+From 8ad7f85043fbd3b8594d1273bbe03fcb4d2c22c6 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 25 Jul 2019 16:40:51 +0800
+Subject: [PATCH 3193/4256] drm/amd/powerplay: determine the features to enable
+ by pptable only
+
+Per current logics, the features to enable are determined together
+by driver and pptable. This is not efficient in co-debug with
+firmware team.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 97a247a234a8..c9145c190d9f 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -329,7 +329,6 @@ static int arcturus_allocate_dpm_context(struct smu_context *smu)
+ 	return 0;
+ }
+ 
+-#define FEATURE_MASK(feature) (1ULL << feature)
+ static int
+ arcturus_get_allowed_feature_mask(struct smu_context *smu,
+ 				  uint32_t *feature_mask, uint32_t num)
+@@ -337,9 +336,8 @@ arcturus_get_allowed_feature_mask(struct smu_context *smu,
+ 	if (num > 2)
+ 		return -EINVAL;
+ 
+-	memset(feature_mask, 0, sizeof(uint32_t) * num);
+-
+-	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT);
++	/* pptable will handle the features to enable */
++	memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
+ 
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3194-drm-amdgpu-powerplay-return-success-if-set_mp1_state.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3194-drm-amdgpu-powerplay-return-success-if-set_mp1_state.patch
new file mode 100644
index 00000000..80e13f9e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3194-drm-amdgpu-powerplay-return-success-if-set_mp1_state.patch
@@ -0,0 +1,38 @@
+From 57c5fe43666c76302bc70d258e45f260ef731ce0 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 30 Jul 2019 21:27:03 -0500
+Subject: [PATCH 3194/4256] drm/amdgpu/powerplay: return success if
+ set_mp1_state is not set
+
+Some asics (APUs) don't have this callback so we want to return
+success.  Avoids spurious error messages on APUs.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+index 88a2ef75b7e1..2e3d9ef625bf 100644
+--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+@@ -931,12 +931,10 @@ static int pp_dpm_set_mp1_state(void *handle, enum pp_mp1_state mp1_state)
+ 	if (!hwmgr || !hwmgr->pm_en)
+ 		return -EINVAL;
+ 
+-	if (hwmgr->hwmgr_func->set_mp1_state == NULL) {
+-		pr_info_ratelimited("%s was not implemented.\n", __func__);
+-		return -EINVAL;
+-	}
++	if (hwmgr->hwmgr_func->set_mp1_state)
++		return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state);
+ 
+-	return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state);
++	return 0;
+ }
+ 
+ static int pp_dpm_switch_power_profile(void *handle,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3195-drm-amdgpu-move-some-ras-data-structure-to-amdgpu_ra.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3195-drm-amdgpu-move-some-ras-data-structure-to-amdgpu_ra.patch
new file mode 100644
index 00000000..8545efcc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3195-drm-amdgpu-move-some-ras-data-structure-to-amdgpu_ra.patch
@@ -0,0 +1,179 @@
+From d4fb3e00b06342beb8228a8c8142efcf32e37d3d Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 17 Jul 2019 17:34:46 +0800
+Subject: [PATCH 3195/4256] drm/amdgpu: move some ras data structure to
+ amdgpu_ras.h
+
+These are common structures that can be included by IP specific
+source files
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 68 ------------------------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 69 ++++++++++++++++++++++++-
+ 2 files changed, 68 insertions(+), 69 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index b45aaf04a574..3be306bf1603 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -28,74 +28,6 @@
+ #include "amdgpu_ras.h"
+ #include "amdgpu_atomfirmware.h"
+ 
+-struct ras_ih_data {
+-	/* interrupt bottom half */
+-	struct work_struct ih_work;
+-	int inuse;
+-	/* IP callback */
+-	ras_ih_cb cb;
+-	/* full of entries */
+-	unsigned char *ring;
+-	unsigned int ring_size;
+-	unsigned int element_size;
+-	unsigned int aligned_element_size;
+-	unsigned int rptr;
+-	unsigned int wptr;
+-};
+-
+-struct ras_fs_data {
+-	char sysfs_name[32];
+-	char debugfs_name[32];
+-};
+-
+-struct ras_err_data {
+-	unsigned long ue_count;
+-	unsigned long ce_count;
+-};
+-
+-struct ras_err_handler_data {
+-	/* point to bad pages array */
+-	struct {
+-		unsigned long bp;
+-		struct amdgpu_bo *bo;
+-	} *bps;
+-	/* the count of entries */
+-	int count;
+-	/* the space can place new entries */
+-	int space_left;
+-	/* last reserved entry's index + 1 */
+-	int last_reserved;
+-};
+-
+-struct ras_manager {
+-	struct ras_common_if head;
+-	/* reference count */
+-	int use;
+-	/* ras block link */
+-	struct list_head node;
+-	/* the device */
+-	struct amdgpu_device *adev;
+-	/* debugfs */
+-	struct dentry *ent;
+-	/* sysfs */
+-	struct device_attribute sysfs_attr;
+-	int attr_inuse;
+-
+-	/* fs node name */
+-	struct ras_fs_data fs_data;
+-
+-	/* IH data */
+-	struct ras_ih_data ih_data;
+-
+-	struct ras_err_data err_data;
+-};
+-
+-struct ras_badpage {
+-	unsigned int bp;
+-	unsigned int size;
+-	unsigned int flags;
+-};
+-
+ const char *ras_error_string[] = {
+ 	"none",
+ 	"parity",
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index b2841195bd3b..80e94d604a2e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -108,8 +108,75 @@ struct amdgpu_ras {
+ 	uint32_t flags;
+ };
+ 
+-/* interfaces for IP */
++struct ras_ih_data {
++	/* interrupt bottom half */
++	struct work_struct ih_work;
++	int inuse;
++	/* IP callback */
++	ras_ih_cb cb;
++	/* full of entries */
++	unsigned char *ring;
++	unsigned int ring_size;
++	unsigned int element_size;
++	unsigned int aligned_element_size;
++	unsigned int rptr;
++	unsigned int wptr;
++};
++
++struct ras_fs_data {
++	char sysfs_name[32];
++	char debugfs_name[32];
++};
++
++struct ras_err_data {
++	unsigned long ue_count;
++	unsigned long ce_count;
++};
++
++struct ras_err_handler_data {
++	/* point to bad pages array */
++	struct {
++		unsigned long bp;
++		struct amdgpu_bo *bo;
++	} *bps;
++	/* the count of entries */
++	int count;
++	/* the space can place new entries */
++	int space_left;
++	/* last reserved entry's index + 1 */
++	int last_reserved;
++};
+ 
++struct ras_manager {
++	struct ras_common_if head;
++	/* reference count */
++	int use;
++	/* ras block link */
++	struct list_head node;
++	/* the device */
++	struct amdgpu_device *adev;
++	/* debugfs */
++	struct dentry *ent;
++	/* sysfs */
++	struct device_attribute sysfs_attr;
++	int attr_inuse;
++
++	/* fs node name */
++	struct ras_fs_data fs_data;
++
++	/* IH data */
++	struct ras_ih_data ih_data;
++
++	struct ras_err_data err_data;
++};
++
++struct ras_badpage {
++	unsigned int bp;
++	unsigned int size;
++	unsigned int flags;
++};
++
++/* interfaces for IP */
+ struct ras_fs_if {
+ 	struct ras_common_if head;
+ 	char sysfs_name[32];
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3196-drm-amdgpu-init-RSMU-and-UMC-ip-base-address-for-veg.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3196-drm-amdgpu-init-RSMU-and-UMC-ip-base-address-for-veg.patch
new file mode 100644
index 00000000..d17e038e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3196-drm-amdgpu-init-RSMU-and-UMC-ip-base-address-for-veg.patch
@@ -0,0 +1,45 @@
+From 5c36ab60839fe88bb92e5324583558b9a61bf83d Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 17 Jul 2019 17:52:28 +0800
+Subject: [PATCH 3196/4256] drm/amdgpu: init RSMU and UMC ip base address for
+ vega20
+
+the driver needs to program RSMU and UMC registers to
+support vega20 RAS feature
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h          | 2 ++
+ drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 2 ++
+ 2 files changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 015ebcf3de17..c16bce6181fa 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -768,6 +768,8 @@ enum amd_hw_ip_block_type {
+ 	NBIF_HWIP,
+ 	THM_HWIP,
+ 	CLK_HWIP,
++	UMC_HWIP,
++	RSMU_HWIP,
+ 	MAX_HWIP
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+index 79223188bd47..587e33f5dcce 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
++++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+@@ -50,6 +50,8 @@ int vega20_reg_base_init(struct amdgpu_device *adev)
+ 		adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
+ 		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
+ 		adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
++		adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));
++		adev->reg_offset[RSMU_HWIP][i] = (uint32_t *)(&(RSMU_BASE.instance[i]));
+ 	}
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3197-drm-amdgpu-add-amdgpu_umc_functions-structure.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3197-drm-amdgpu-add-amdgpu_umc_functions-structure.patch
new file mode 100644
index 00000000..bbb3e13b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3197-drm-amdgpu-add-amdgpu_umc_functions-structure.patch
@@ -0,0 +1,73 @@
+From 3076939bb56d91a08173d5f5992b17765a8e6cec Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Tue, 23 Jul 2019 19:42:03 +0800
+Subject: [PATCH 3197/4256] drm/amdgpu: add amdgpu_umc_functions structure
+
+This is common structure as UMC callback function
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  2 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 29 +++++++++++++++++++++++++
+ 2 files changed, 31 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index c16bce6181fa..a948e65d6093 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -87,6 +87,7 @@
+ #include "amdgpu_smu.h"
+ #include "amdgpu_discovery.h"
+ #include "amdgpu_mes.h"
++#include "amdgpu_umc.h"
+ 
+ #define MAX_GPU_INSTANCE		16
+ 
+@@ -1007,6 +1008,7 @@ struct amdgpu_device {
+ 
+ 	const struct amdgpu_nbio_funcs	*nbio_funcs;
+ 	const struct amdgpu_df_funcs	*df_funcs;
++	const struct amdgpu_umc_funcs	*umc_funcs;
+ 
+ 	/* delayed work_func for deferring clockgating during resume */
+ 	struct delayed_work     delayed_init_work;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+new file mode 100644
+index 000000000000..1ee1a00e5ac8
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright (C) 2019  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef __AMDGPU_UMC_H__
++#define __AMDGPU_UMC_H__
++
++struct amdgpu_umc_funcs {
++	void (*query_ras_error_count)(struct amdgpu_device *adev,
++					void *ras_error_status);
++};
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3198-drm-amdgpu-add-rsmu-v_0_0_2-ip-headers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3198-drm-amdgpu-add-rsmu-v_0_0_2-ip-headers.patch
new file mode 100644
index 00000000..49428c66
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3198-drm-amdgpu-add-rsmu-v_0_0_2-ip-headers.patch
@@ -0,0 +1,91 @@
+From 966893a7dfc6d788183ace86d459bff6cbc37fca Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 24 Jul 2019 14:13:53 +0800
+Subject: [PATCH 3198/4256] drm/amdgpu: add rsmu v_0_0_2 ip headers
+
+remote smu (rsmu) is a sub-block used as ip register interface,
+error handling, reset generation.etc
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+---
+ .../include/asic_reg/rsmu/rsmu_0_0_2_offset.h | 27 ++++++++++++++++
+ .../asic_reg/rsmu/rsmu_0_0_2_sh_mask.h        | 32 +++++++++++++++++++
+ 2 files changed, 59 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_offset.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_sh_mask.h
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_offset.h
+new file mode 100644
+index 000000000000..46466ae77f19
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_offset.h
+@@ -0,0 +1,27 @@
++/*
++ * Copyright (C) 2019  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _rsmu_0_0_2_OFFSET_HEADER
++#define _rsmu_0_0_2_OFFSET_HEADER
++
++#define	mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU								0x0d91
++#define	mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU_BASE_IDX						0
++
++#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_sh_mask.h
+new file mode 100644
+index 000000000000..ea0acb598254
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_sh_mask.h
+@@ -0,0 +1,32 @@
++/*
++ * Copyright (C) 2019  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _rsmu_0_0_2_SH_MASK_HEADER
++#define _rsmu_0_0_2_SH_MASK_HEADER
++
++//RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU
++#define	RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_WREN__SHIFT				0x0
++#define	RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_INSTANCE__SHIFT				0x10
++#define	RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_MODE_EN__SHIFT				0x1f
++#define	RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_WREN_MASK					0x0000FFFFL
++#define	RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_INSTANCE_MASK				0x000F0000L
++#define	RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_MODE_EN_MASK				0x80000000L
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3199-drm-amdgpu-add-umc-v6_1_1-IP-headers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3199-drm-amdgpu-add-umc-v6_1_1-IP-headers.patch
new file mode 100644
index 00000000..0e9ee008
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3199-drm-amdgpu-add-umc-v6_1_1-IP-headers.patch
@@ -0,0 +1,153 @@
+From 4edf43d2b644fc1671d982ad485df4f1b836793d Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 24 Jul 2019 14:36:49 +0800
+Subject: [PATCH 3199/4256] drm/amdgpu: add umc v6_1_1 IP headers
+
+the change introduces IP headers for unified memory controller (umc)
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+---
+ .../include/asic_reg/umc/umc_6_1_1_offset.h   | 31 +++++++
+ .../include/asic_reg/umc/umc_6_1_1_sh_mask.h  | 91 +++++++++++++++++++
+ 2 files changed, 122 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h
+new file mode 100644
+index 000000000000..043aa695d63f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h
+@@ -0,0 +1,31 @@
++/*
++ * Copyright (C) 2019  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _umc_6_1_1_OFFSET_HEADER
++#define _umc_6_1_1_OFFSET_HEADER
++
++#define mmUMCCH0_0_EccErrCntSel                                                                        0x0360
++#define mmUMCCH0_0_EccErrCntSel_BASE_IDX                                                               0
++#define mmUMCCH0_0_EccErrCnt                                                                           0x0361
++#define mmUMCCH0_0_EccErrCnt_BASE_IDX                                                                  0
++#define mmMCA_UMC_UMC0_MCUMC_STATUST0                                                                  0x03c2
++#define mmMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX                                                         0
++
++#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h
+new file mode 100644
+index 000000000000..45c888280af9
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h
+@@ -0,0 +1,91 @@
++/*
++ * Copyright (C) 2019  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _umc_6_1_1_SH_MASK_HEADER
++#define _umc_6_1_1_SH_MASK_HEADER
++
++//UMCCH0_0_EccErrCntSel
++#define UMCCH0_0_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
++#define UMCCH0_0_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
++#define UMCCH0_0_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
++#define UMCCH0_0_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
++#define UMCCH0_0_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
++#define UMCCH0_0_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
++//UMCCH0_0_EccErrCnt
++#define UMCCH0_0_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
++#define UMCCH0_0_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
++//MCA_UMC_UMC0_MCUMC_STATUST0
++#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT                                                         0x0
++#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT                                                      0x10
++#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV0__SHIFT                                                           0x16
++#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT                                                         0x20
++#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV1__SHIFT                                                           0x26
++#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub__SHIFT                                                             0x28
++#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV2__SHIFT                                                           0x29
++#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison__SHIFT                                                            0x2b
++#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred__SHIFT                                                          0x2c
++#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC__SHIFT                                                              0x2d
++#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC__SHIFT                                                              0x2e
++#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV3__SHIFT                                                           0x2f
++#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent__SHIFT                                                       0x34
++#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV__SHIFT                                                             0x35
++#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV4__SHIFT                                                           0x36
++#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC__SHIFT                                                               0x37
++#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal__SHIFT                                                      0x38
++#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC__SHIFT                                                               0x39
++#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV__SHIFT                                                             0x3a
++#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV__SHIFT                                                             0x3b
++#define MCA_UMC_UMC0_MCUMC_STATUST0__En__SHIFT                                                                0x3c
++#define MCA_UMC_UMC0_MCUMC_STATUST0__UC__SHIFT                                                                0x3d
++#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow__SHIFT                                                          0x3e
++#define MCA_UMC_UMC0_MCUMC_STATUST0__Val__SHIFT                                                               0x3f
++#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode_MASK                                                           0x000000000000FFFFL
++#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt_MASK                                                        0x00000000003F0000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV0_MASK                                                             0x00000000FFC00000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId_MASK                                                           0x0000003F00000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV1_MASK                                                             0x000000C000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub_MASK                                                               0x0000010000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV2_MASK                                                             0x0000060000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison_MASK                                                              0x0000080000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred_MASK                                                            0x0000100000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC_MASK                                                                0x0000200000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC_MASK                                                                0x0000400000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV3_MASK                                                             0x000F800000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent_MASK                                                         0x0010000000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV_MASK                                                               0x0020000000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV4_MASK                                                             0x0040000000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC_MASK                                                                 0x0080000000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal_MASK                                                        0x0100000000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC_MASK                                                                 0x0200000000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV_MASK                                                               0x0400000000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV_MASK                                                               0x0800000000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__En_MASK                                                                  0x1000000000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__UC_MASK                                                                  0x2000000000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow_MASK                                                            0x4000000000000000L
++#define MCA_UMC_UMC0_MCUMC_STATUST0__Val_MASK                                                                 0x8000000000000000L
++//MCA_UMC_UMC0_MCUMC_ADDRT0
++#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT                                                           0x0
++#define MCA_UMC_UMC0_MCUMC_ADDRT0__LSB__SHIFT                                                                 0x38
++#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT                                                            0x3e
++#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK                                                             0x00FFFFFFFFFFFFFFL
++#define MCA_UMC_UMC0_MCUMC_ADDRT0__LSB_MASK                                                                   0x3F00000000000000L
++#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved_MASK                                                              0xC000000000000000L
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3200-drm-amdgpu-add-umc-v6_1-query-error-count-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3200-drm-amdgpu-add-umc-v6_1-query-error-count-support.patch
new file mode 100644
index 00000000..04652b12
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3200-drm-amdgpu-add-umc-v6_1-query-error-count-support.patch
@@ -0,0 +1,250 @@
+From a01add62c600eb697dc1cb18d2dc07fd5969d98f Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 31 Jul 2019 20:23:01 +0800
+Subject: [PATCH 3200/4256] drm/amdgpu: add umc v6_1 query error count support
+
+Implement umc query_ras_error_count function to support querry
+both correctable and uncorrectable error
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile   |   4 +
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 162 ++++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.h |  39 +++++++
+ 3 files changed, 205 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index bb2e00bbdee1..797f8a7e4f72 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -81,6 +81,10 @@ amdgpu-y += \
+ 	gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \
+ 	gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o
+ 
++# add UMC block
++amdgpu-y += \
++	umc_v6_1.o
++
+ # add IH block
+ amdgpu-y += \
+ 	amdgpu_irq.o \
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+new file mode 100644
+index 000000000000..1ca5ae642946
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+@@ -0,0 +1,162 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "umc_v6_1.h"
++#include "amdgpu_ras.h"
++#include "amdgpu.h"
++
++#include "rsmu/rsmu_0_0_2_offset.h"
++#include "rsmu/rsmu_0_0_2_sh_mask.h"
++#include "umc/umc_6_1_1_offset.h"
++#include "umc/umc_6_1_1_sh_mask.h"
++
++static void umc_v6_1_enable_umc_index_mode(struct amdgpu_device *adev,
++					   uint32_t umc_instance)
++{
++	uint32_t rsmu_umc_index;
++
++	rsmu_umc_index = RREG32_SOC15(RSMU, 0,
++			mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU);
++	rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
++			RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
++			RSMU_UMC_INDEX_MODE_EN, 1);
++	rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
++			RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
++			RSMU_UMC_INDEX_INSTANCE, umc_instance);
++	rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
++			RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
++			RSMU_UMC_INDEX_WREN, 1 << umc_instance);
++	WREG32_SOC15(RSMU, 0, mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
++				rsmu_umc_index);
++}
++
++static void umc_v6_1_disable_umc_index_mode(struct amdgpu_device *adev)
++{
++	WREG32_FIELD15(RSMU, 0, RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
++			RSMU_UMC_INDEX_MODE_EN, 0);
++}
++
++static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
++						   uint32_t umc_reg_offset,
++						   unsigned long *error_count)
++{
++	uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
++	uint32_t ecc_err_cnt, ecc_err_cnt_addr;
++	uint64_t mc_umc_status;
++	uint32_t mc_umc_status_addr;
++
++	ecc_err_cnt_sel_addr =
++		SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
++	ecc_err_cnt_addr =
++		SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
++	mc_umc_status_addr =
++		SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
++
++	/* select the lower chip and check the error count */
++	ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset);
++	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
++					EccErrCntCsSel, 0);
++	WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
++	ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset);
++	*error_count +=
++		REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt);
++	/* clear the lower chip err count */
++	WREG32(ecc_err_cnt_addr + umc_reg_offset, 0);
++
++	/* select the higher chip and check the err counter */
++	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
++					EccErrCntCsSel, 1);
++	WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
++	ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset);
++	*error_count +=
++		REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt);
++	/* clear the higher chip err count */
++	WREG32(ecc_err_cnt_addr + umc_reg_offset, 0);
++
++	/* check for SRAM correctable error
++	  MCUMC_STATUS is a 64 bit register */
++	mc_umc_status =
++		RREG32(mc_umc_status_addr + umc_reg_offset);
++	mc_umc_status |=
++		(uint64_t)RREG32(mc_umc_status_addr + umc_reg_offset + 1) << 32;
++	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
++	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
++	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
++		*error_count += 1;
++
++	/* clear the MCUMC_STATUS */
++	WREG32(mc_umc_status_addr + umc_reg_offset, 0);
++	WREG32(mc_umc_status_addr + umc_reg_offset + 1, 0);
++}
++
++static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev,
++						      uint32_t umc_reg_offset,
++						      unsigned long *error_count)
++{
++	uint64_t mc_umc_status;
++	uint32_t mc_umc_status_addr;
++
++	mc_umc_status_addr =
++                SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
++
++	/* check the MCUMC_STATUS */
++	mc_umc_status = RREG32(mc_umc_status_addr + umc_reg_offset);
++	mc_umc_status |=
++		(uint64_t)RREG32(mc_umc_status_addr + umc_reg_offset + 1) << 32;
++
++	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
++		REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
++		(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
++		REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
++		REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
++		REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
++		*error_count += 1;
++
++	/* clear the MCUMC_STATUS */
++	WREG32(mc_umc_status_addr + umc_reg_offset, 0);
++	WREG32(mc_umc_status_addr + umc_reg_offset + 1, 0);
++}
++
++static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev,
++					   void *ras_error_status)
++{
++	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
++	uint32_t umc_inst, channel_inst, umc_reg_offset;
++
++	for (umc_inst = 0; umc_inst < UMC_V6_1_UMC_INSTANCE_NUM; umc_inst++) {
++		/* enable the index mode to query eror count per channel */
++		umc_v6_1_enable_umc_index_mode(adev, umc_inst);
++		for (channel_inst = 0; channel_inst < UMC_V6_1_CHANNEL_INSTANCE_NUM; channel_inst++) {
++			/* calc the register offset according to channel instance */
++			umc_reg_offset = UMC_V6_1_PER_CHANNEL_OFFSET * channel_inst;
++			umc_v6_1_query_correctable_error_count(adev, umc_reg_offset,
++							       &(err_data->ce_count));
++			umc_v6_1_querry_uncorrectable_error_count(adev, umc_reg_offset,
++								  &(err_data->ue_count));
++		}
++	}
++	umc_v6_1_disable_umc_index_mode(adev);
++}
++
++const struct amdgpu_umc_funcs umc_v6_1_funcs = {
++	.query_ras_error_count = umc_v6_1_query_ras_error_count,
++};
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
+new file mode 100644
+index 000000000000..d25ae414f4d8
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
+@@ -0,0 +1,39 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __UMC_V6_1_H__
++#define __UMC_V6_1_H__
++
++#include "soc15_common.h"
++
++/* HBM  Memory Channel Width */
++#define UMC_V6_1_HBM_MEMORY_CHANNEL_WIDTH	128
++/* number of umc channel instance with memory map register access */
++#define UMC_V6_1_CHANNEL_INSTANCE_NUM		4
++/* number of umc instance with memory map register access */
++#define UMC_V6_1_UMC_INSTANCE_NUM		8
++/* UMC regiser per channel offset */
++#define UMC_V6_1_PER_CHANNEL_OFFSET		0x800
++
++extern const struct amdgpu_umc_funcs umc_v6_1_funcs;
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3201-drm-amdgpu-init-umc-v6_1-functions-for-vega20.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3201-drm-amdgpu-init-umc-v6_1-functions-for-vega20.patch
new file mode 100644
index 00000000..ee23add0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3201-drm-amdgpu-init-umc-v6_1-functions-for-vega20.patch
@@ -0,0 +1,61 @@
+From 8c828c0f40f806a1cd9a0a98c450349085c49c50 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 17 Jul 2019 21:47:44 +0800
+Subject: [PATCH 3201/4256] drm/amdgpu: init umc v6_1 functions for vega20
+
+init umc callback function for vega20 in sw early init phase
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index f99e02649f81..ac5a6bf477cb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -45,6 +45,7 @@
+ #include "mmhub_v1_0.h"
+ #include "gfxhub_v1_1.h"
+ #include "mmhub_v9_4.h"
++#include "umc_v6_1.h"
+ 
+ #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
+ 
+@@ -620,12 +621,24 @@ static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
+ 	adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
+ }
+ 
++static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
++{
++	switch (adev->asic_type) {
++	case CHIP_VEGA20:
++		adev->umc_funcs = &umc_v6_1_funcs;
++		break;
++	default:
++		break;
++	}
++}
++
+ static int gmc_v9_0_early_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
+ 	gmc_v9_0_set_gmc_funcs(adev);
+ 	gmc_v9_0_set_irq_funcs(adev);
++	gmc_v9_0_set_umc_funcs(adev);
+ 
+ 	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
+ 	adev->gmc.shared_aperture_end =
+@@ -714,6 +727,7 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ 		amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0);
+ 		return 0;
+ 	}
++
+ 	/* handle resume path. */
+ 	if (*ras_if) {
+ 		/* resend ras TA enable cmd during resume.
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3202-drm-amdgpu-querry-umc-error-count.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3202-drm-amdgpu-querry-umc-error-count.patch
new file mode 100644
index 00000000..85278b11
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3202-drm-amdgpu-querry-umc-error-count.patch
@@ -0,0 +1,66 @@
+From c7ba5637701bc3b4cc193988913c5528a80dc392 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 17 Jul 2019 21:49:53 +0800
+Subject: [PATCH 3202/4256] drm/amdgpu: querry umc error count
+
+check umc error count in both ras querry function and
+ras interrupt handler
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 11 ++++++++++-
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |  3 +++
+ 2 files changed, 13 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 3be306bf1603..845e75f35b19 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -586,11 +586,19 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev,
+ 		struct ras_query_if *info)
+ {
+ 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
++	struct ras_err_data err_data = {0, 0};
+ 
+ 	if (!obj)
+ 		return -EINVAL;
+-	/* TODO might read the register to read the count */
+ 
++	switch (info->head.block) {
++	case AMDGPU_RAS_BLOCK__UMC:
++		if (adev->umc_funcs->query_ras_error_count)
++			adev->umc_funcs->query_ras_error_count(adev, &err_data);
++		break;
++	default:
++		break;
++	}
+ 	info->ue_count = obj->err_data.ue_count;
+ 	info->ce_count = obj->err_data.ce_count;
+ 
+@@ -984,6 +992,7 @@ static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
+ 	struct ras_ih_data *data = &obj->ih_data;
+ 	struct amdgpu_iv_entry entry;
+ 	int ret;
++	struct ras_err_data err_data = {0, 0};
+ 
+ 	while (data->rptr != data->wptr) {
+ 		rmb();
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index ac5a6bf477cb..fe22eb40d384 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -241,7 +241,10 @@ static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
+ static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+ 		struct amdgpu_iv_entry *entry)
+ {
++	struct ras_err_data err_data = {0, 0};
+ 	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
++	if (adev->umc_funcs->query_ras_error_count)
++		adev->umc_funcs->query_ras_error_count(adev, &err_data);
+ 	amdgpu_ras_reset_gpu(adev, 0);
+ 	return AMDGPU_RAS_UE;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3203-drm-amdgpu-add-ras-error-count-after-each-query-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3203-drm-amdgpu-add-ras-error-count-after-each-query-v2.patch
new file mode 100644
index 00000000..e0df8655
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3203-drm-amdgpu-add-ras-error-count-after-each-query-v2.patch
@@ -0,0 +1,44 @@
+From 5506fd967aab388d764d3212482b19267f23fc93 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Wed, 31 Jul 2019 20:28:13 +0800
+Subject: [PATCH 3203/4256] drm/amdgpu: add ras error count after each query
+ (v2)
+
+v1: increase ras ce/ue error count
+v2: log the number of correctable and uncorrectable errors
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 845e75f35b19..4f81b1f6d09f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -599,9 +599,20 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev,
+ 	default:
+ 		break;
+ 	}
++
++	obj->err_data.ue_count += err_data.ue_count;
++	obj->err_data.ce_count += err_data.ce_count;
++
+ 	info->ue_count = obj->err_data.ue_count;
+ 	info->ce_count = obj->err_data.ce_count;
+ 
++	if (err_data.ce_count)
++		dev_info(adev->dev, "%ld correctable errors detected in %s block\n",
++			 obj->err_data.ce_count, ras_block_str(info->head.block));
++	if (err_data.ue_count)
++		dev_info(adev->dev, "%ld uncorrectable errors detected in %s block\n",
++			 obj->err_data.ue_count, ras_block_str(info->head.block));
++
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3204-drm-amdgpu-add-RREG64-WREG64-_PCIE-operations.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3204-drm-amdgpu-add-RREG64-WREG64-_PCIE-operations.patch
new file mode 100644
index 00000000..42b3af22
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3204-drm-amdgpu-add-RREG64-WREG64-_PCIE-operations.patch
@@ -0,0 +1,230 @@
+From 68e4f084546e86dc88ede3c01514f8f29f4403dd Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Wed, 24 Jul 2019 15:13:27 +0800
+Subject: [PATCH 3204/4256] drm/amdgpu: add RREG64/WREG64(_PCIE) operations
+
+add 64 bits register access functions
+
+v2: implement 64 bit functions in low level
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 11 ++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 73 ++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/soc15.c         | 45 +++++++++++++
+ 3 files changed, 129 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index a948e65d6093..8aa67b43e974 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -653,6 +653,9 @@ void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
+ typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
+ typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
+ 
++typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
++typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
++
+ typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
+ typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
+ 
+@@ -870,6 +873,8 @@ struct amdgpu_device {
+ 	amdgpu_wreg_t			pcie_wreg;
+ 	amdgpu_rreg_t			pciep_rreg;
+ 	amdgpu_wreg_t			pciep_wreg;
++	amdgpu_rreg64_t			pcie_rreg64;
++	amdgpu_wreg64_t			pcie_wreg64;
+ 	/* protects concurrent UVD register access */
+ 	spinlock_t uvd_ctx_idx_lock;
+ 	amdgpu_rreg_t			uvd_ctx_rreg;
+@@ -1070,6 +1075,8 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
+ 		    uint32_t acc_flags);
+ void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
+ uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
++uint64_t amdgpu_mm_rreg64(struct amdgpu_device *adev, uint32_t reg);
++void amdgpu_mm_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v);
+ 
+ u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
+ void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
+@@ -1097,12 +1104,16 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
+ #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
+ #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
+ #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
++#define RREG64(reg) amdgpu_mm_rreg64(adev, (reg))
++#define WREG64(reg, v) amdgpu_mm_wreg64(adev, (reg), (v))
+ #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
+ #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
+ #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
+ #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
+ #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
+ #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
++#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
++#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
+ #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
+ #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
+ #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 23d0301aad4d..5e44ddeb21db 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -260,6 +260,43 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
+ 	}
+ }
+ 
++/**
++ * amdgpu_mm_rreg64 - read a 64 bit memory mapped IO register
++ *
++ * @adev: amdgpu_device pointer
++ * @reg: dword aligned register offset
++ *
++ * Returns the 64 bit value from the offset specified.
++ */
++uint64_t amdgpu_mm_rreg64(struct amdgpu_device *adev, uint32_t reg)
++{
++	uint64_t ret;
++
++	if ((reg * 4) < adev->rmmio_size)
++		ret = readq(((void __iomem *)adev->rmmio) + (reg * 4));
++	else
++		BUG();
++
++	return ret;
++}
++
++/**
++ * amdgpu_mm_wreg64 - write to a 64 bit memory mapped IO register
++ *
++ * @adev: amdgpu_device pointer
++ * @reg: dword aligned register offset
++ * @v: 64 bit value to write to the register
++ *
++ * Writes the value specified to the offset specified.
++ */
++void amdgpu_mm_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
++{
++	if ((reg * 4) < adev->rmmio_size)
++		writeq(v, ((void __iomem *)adev->rmmio) + (reg * 4));
++	else
++		BUG();
++}
++
+ /**
+  * amdgpu_io_rreg - read an IO register
+  *
+@@ -415,6 +452,40 @@ static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32
+ 	BUG();
+ }
+ 
++/**
++ * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
++ *
++ * @adev: amdgpu device pointer
++ * @reg: offset of register
++ *
++ * Dummy register read function.  Used for register blocks
++ * that certain asics don't have (all asics).
++ * Returns the value in the register.
++ */
++static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
++{
++	DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
++	BUG();
++	return 0;
++}
++
++/**
++ * amdgpu_invalid_wreg64 - dummy reg write function
++ *
++ * @adev: amdgpu device pointer
++ * @reg: offset of register
++ * @v: value to write to the register
++ *
++ * Dummy register read function.  Used for register blocks
++ * that certain asics don't have (all asics).
++ */
++static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
++{
++	DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
++		  reg, v);
++	BUG();
++}
++
+ /**
+  * amdgpu_block_invalid_rreg - dummy reg read function
+  *
+@@ -2530,6 +2601,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ 	adev->pcie_wreg = &amdgpu_invalid_wreg;
+ 	adev->pciep_rreg = &amdgpu_invalid_rreg;
+ 	adev->pciep_wreg = &amdgpu_invalid_wreg;
++	adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
++	adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
+ 	adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
+ 	adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
+ 	adev->didt_rreg = &amdgpu_invalid_rreg;
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 347a44f2757a..214fc9d880e5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -115,6 +115,49 @@ static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+ 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+ }
+ 
++static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
++{
++	unsigned long flags, address, data;
++	u64 r;
++	address = adev->nbio_funcs->get_pcie_index_offset(adev);
++	data = adev->nbio_funcs->get_pcie_data_offset(adev);
++
++	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
++	/* read low 32 bit */
++	WREG32(address, reg);
++	(void)RREG32(address);
++	r = RREG32(data);
++
++	/* read high 32 bit*/
++	WREG32(address, reg + 4);
++	(void)RREG32(address);
++	r |= ((u64)RREG32(data) << 32);
++	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
++	return r;
++}
++
++static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
++{
++	unsigned long flags, address, data;
++
++	address = adev->nbio_funcs->get_pcie_index_offset(adev);
++	data = adev->nbio_funcs->get_pcie_data_offset(adev);
++
++	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
++	/* write low 32 bit */
++	WREG32(address, reg);
++	(void)RREG32(address);
++	WREG32(data, (u32)(v & 0xffffffffULL));
++	(void)RREG32(data);
++
++	/* write high 32 bit */
++	WREG32(address, reg + 4);
++	(void)RREG32(address);
++	WREG32(data, (u32)(v >> 32));
++	(void)RREG32(data);
++	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
++}
++
+ static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
+ {
+ 	unsigned long flags, address, data;
+@@ -865,6 +908,8 @@ static int soc15_common_early_init(void *handle)
+ 	adev->smc_wreg = NULL;
+ 	adev->pcie_rreg = &soc15_pcie_rreg;
+ 	adev->pcie_wreg = &soc15_pcie_wreg;
++	adev->pcie_rreg64 = &soc15_pcie_rreg64;
++	adev->pcie_wreg64 = &soc15_pcie_wreg64;
+ 	adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
+ 	adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
+ 	adev->didt_rreg = &soc15_didt_rreg;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3205-drm-amdgpu-use-64bit-operation-macros-for-umc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3205-drm-amdgpu-use-64bit-operation-macros-for-umc.patch
new file mode 100644
index 00000000..70053eab
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3205-drm-amdgpu-use-64bit-operation-macros-for-umc.patch
@@ -0,0 +1,83 @@
+From 230d97dc6ed9ab524ae67799e52b6f77b0d45fb8 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Tue, 23 Jul 2019 11:57:15 +0800
+Subject: [PATCH 3205/4256] drm/amdgpu: use 64bit operation macros for umc
+
+replace some 32bit macros with 64bit operations to simplify code
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 25 ++++++++-----------------
+ 1 file changed, 8 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+index 1ca5ae642946..8fbd81d3ce70 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+@@ -94,18 +94,11 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
+ 
+ 	/* check for SRAM correctable error
+ 	  MCUMC_STATUS is a 64 bit register */
+-	mc_umc_status =
+-		RREG32(mc_umc_status_addr + umc_reg_offset);
+-	mc_umc_status |=
+-		(uint64_t)RREG32(mc_umc_status_addr + umc_reg_offset + 1) << 32;
++	mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
+ 	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
+ 	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
+ 	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
+ 		*error_count += 1;
+-
+-	/* clear the MCUMC_STATUS */
+-	WREG32(mc_umc_status_addr + umc_reg_offset, 0);
+-	WREG32(mc_umc_status_addr + umc_reg_offset + 1, 0);
+ }
+ 
+ static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev,
+@@ -119,10 +112,7 @@ static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev
+                 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
+ 
+ 	/* check the MCUMC_STATUS */
+-	mc_umc_status = RREG32(mc_umc_status_addr + umc_reg_offset);
+-	mc_umc_status |=
+-		(uint64_t)RREG32(mc_umc_status_addr + umc_reg_offset + 1) << 32;
+-
++	mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
+ 	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
+ 		REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
+ 		(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
+@@ -130,17 +120,16 @@ static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev
+ 		REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
+ 		REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
+ 		*error_count += 1;
+-
+-	/* clear the MCUMC_STATUS */
+-	WREG32(mc_umc_status_addr + umc_reg_offset, 0);
+-	WREG32(mc_umc_status_addr + umc_reg_offset + 1, 0);
+ }
+ 
+ static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev,
+ 					   void *ras_error_status)
+ {
+ 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+-	uint32_t umc_inst, channel_inst, umc_reg_offset;
++	uint32_t umc_inst, channel_inst, umc_reg_offset, mc_umc_status_addr;
++
++	mc_umc_status_addr =
++		SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
+ 
+ 	for (umc_inst = 0; umc_inst < UMC_V6_1_UMC_INSTANCE_NUM; umc_inst++) {
+ 		/* enable the index mode to query eror count per channel */
+@@ -152,6 +141,8 @@ static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev,
+ 							       &(err_data->ce_count));
+ 			umc_v6_1_querry_uncorrectable_error_count(adev, umc_reg_offset,
+ 								  &(err_data->ue_count));
++			/* clear umc status */
++			WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
+ 		}
+ 	}
+ 	umc_v6_1_disable_umc_index_mode(adev);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3206-drm-amdgpu-switch-to-amdgpu_umc-structure.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3206-drm-amdgpu-switch-to-amdgpu_umc-structure.patch
new file mode 100644
index 00000000..05a33567
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3206-drm-amdgpu-switch-to-amdgpu_umc-structure.patch
@@ -0,0 +1,99 @@
+From 0d9146882b97dfa5a65350f6269e58f8c9524091 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Tue, 23 Jul 2019 12:18:39 +0800
+Subject: [PATCH 3206/4256] drm/amdgpu: switch to amdgpu_umc structure
+
+create new amdgpu_umc structure to for more umc
+settings in future and switch to the new structure
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 4 +++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 6 ++++++
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 8 +++++---
+ 4 files changed, 16 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 8aa67b43e974..9ef363f02f8a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -988,6 +988,9 @@ struct amdgpu_device {
+ 	/* KFD */
+ 	struct amdgpu_kfd_dev		kfd;
+ 
++	/* UMC */
++	struct amdgpu_umc		umc;
++
+ 	/* display related functionality */
+ 	struct amdgpu_display_manager dm;
+ 
+@@ -1013,7 +1016,6 @@ struct amdgpu_device {
+ 
+ 	const struct amdgpu_nbio_funcs	*nbio_funcs;
+ 	const struct amdgpu_df_funcs	*df_funcs;
+-	const struct amdgpu_umc_funcs	*umc_funcs;
+ 
+ 	/* delayed work_func for deferring clockgating during resume */
+ 	struct delayed_work     delayed_init_work;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 4f81b1f6d09f..e087da46fc24 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -593,8 +593,8 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev,
+ 
+ 	switch (info->head.block) {
+ 	case AMDGPU_RAS_BLOCK__UMC:
+-		if (adev->umc_funcs->query_ras_error_count)
+-			adev->umc_funcs->query_ras_error_count(adev, &err_data);
++		if (adev->umc.funcs->query_ras_error_count)
++			adev->umc.funcs->query_ras_error_count(adev, &err_data);
+ 		break;
+ 	default:
+ 		break;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+index 1ee1a00e5ac8..f5d6def96414 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+@@ -26,4 +26,10 @@ struct amdgpu_umc_funcs {
+ 					void *ras_error_status);
+ };
+ 
++struct amdgpu_umc {
++	/* max error count in one ras query call */
++	uint32_t max_ras_err_cnt_per_query;
++	const struct amdgpu_umc_funcs *funcs;
++};
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index fe22eb40d384..111ca34fdafe 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -243,8 +243,8 @@ static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+ {
+ 	struct ras_err_data err_data = {0, 0};
+ 	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
+-	if (adev->umc_funcs->query_ras_error_count)
+-		adev->umc_funcs->query_ras_error_count(adev, &err_data);
++	if (adev->umc.funcs->query_ras_error_count)
++		adev->umc.funcs->query_ras_error_count(adev, &err_data);
+ 	amdgpu_ras_reset_gpu(adev, 0);
+ 	return AMDGPU_RAS_UE;
+ }
+@@ -628,7 +628,9 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
+ {
+ 	switch (adev->asic_type) {
+ 	case CHIP_VEGA20:
+-		adev->umc_funcs = &umc_v6_1_funcs;
++		adev->umc.max_ras_err_cnt_per_query =
++			UMC_V6_1_UMC_INSTANCE_NUM * UMC_V6_1_CHANNEL_INSTANCE_NUM;
++		adev->umc.funcs = &umc_v6_1_funcs;
+ 		break;
+ 	default:
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3207-drm-amdgpu-update-algorithm-of-umc-uncorrectable-err.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3207-drm-amdgpu-update-algorithm-of-umc-uncorrectable-err.patch
new file mode 100644
index 00000000..f0f00fa7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3207-drm-amdgpu-update-algorithm-of-umc-uncorrectable-err.patch
@@ -0,0 +1,43 @@
+From bac0e5e29e22c9ff444aa61c4af1363e412da79b Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Tue, 23 Jul 2019 12:25:16 +0800
+Subject: [PATCH 3207/4256] drm/amdgpu: update algorithm of umc uncorrectable
+ error counting
+
+remove the check of ErrorCodeExt
+
+v2: refine the if condition for ue counting
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+index 8fbd81d3ce70..5b1ccb81b3a2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+@@ -113,12 +113,12 @@ static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev
+ 
+ 	/* check the MCUMC_STATUS */
+ 	mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
+-	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
+-		REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
+-		(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
+-		REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
+-		REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
+-		REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
++	if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
++	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
++	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
++	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
++	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
++	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
+ 		*error_count += 1;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3208-drm-amdgpu-add-support-for-recording-ras-error-addre.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3208-drm-amdgpu-add-support-for-recording-ras-error-addre.patch
new file mode 100644
index 00000000..576e2a31
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3208-drm-amdgpu-add-support-for-recording-ras-error-addre.patch
@@ -0,0 +1,45 @@
+From c1306d170905197794efe95841dbc0d81b6d7134 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Mon, 22 Jul 2019 19:20:29 +0800
+Subject: [PATCH 3208/4256] drm/amdgpu: add support for recording ras error
+ address
+
+more than one error address may be recorded in one query
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 2 ++
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index e087da46fc24..1914f37bee59 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -586,7 +586,7 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev,
+ 		struct ras_query_if *info)
+ {
+ 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
+-	struct ras_err_data err_data = {0, 0};
++	struct ras_err_data err_data = {0, 0, 0, NULL};
+ 
+ 	if (!obj)
+ 		return -EINVAL;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index 80e94d604a2e..0920db7aff34 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -131,6 +131,8 @@ struct ras_fs_data {
+ struct ras_err_data {
+ 	unsigned long ue_count;
+ 	unsigned long ce_count;
++	unsigned long err_addr_cnt;
++	uint64_t *err_addr;
+ };
+ 
+ struct ras_err_handler_data {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3209-drm-amdgpu-add-structures-for-umc-error-address-tran.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3209-drm-amdgpu-add-structures-for-umc-error-address-tran.patch
new file mode 100644
index 00000000..db77869d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3209-drm-amdgpu-add-structures-for-umc-error-address-tran.patch
@@ -0,0 +1,52 @@
+From 9f38114f77a6ff68c3c59fb64e6f73439148c206 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Mon, 22 Jul 2019 18:30:59 +0800
+Subject: [PATCH 3209/4256] drm/amdgpu: add structures for umc error address
+ translation
+
+add related registers, callback function and channel index table
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h |  2 ++
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.c   | 10 ++++++++++
+ 2 files changed, 12 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+index f5d6def96414..dfa1a39e57af 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+@@ -24,6 +24,8 @@
+ struct amdgpu_umc_funcs {
+ 	void (*query_ras_error_count)(struct amdgpu_device *adev,
+ 					void *ras_error_status);
++	void (*query_ras_error_address)(struct amdgpu_device *adev,
++					void *ras_error_status);
+ };
+ 
+ struct amdgpu_umc {
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+index 5b1ccb81b3a2..e05f3e68edb0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+@@ -29,6 +29,16 @@
+ #include "umc/umc_6_1_1_offset.h"
+ #include "umc/umc_6_1_1_sh_mask.h"
+ 
++#define smnMCA_UMC0_MCUMC_ADDRT0	0x50f10
++
++static uint32_t
++	umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM] = {
++		{2, 18, 11, 27},	{4, 20, 13, 29},
++		{1, 17, 8, 24},		{7, 23, 14, 30},
++		{10, 26, 3, 19},	{12, 28, 5, 21},
++		{9, 25, 0, 16},		{15, 31, 6, 22}
++};
++
+ static void umc_v6_1_enable_umc_index_mode(struct amdgpu_device *adev,
+ 					   uint32_t umc_instance)
+ {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3210-drm-amdgpu-query-umc-ras-error-address.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3210-drm-amdgpu-query-umc-ras-error-address.patch
new file mode 100644
index 00000000..494c8abb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3210-drm-amdgpu-query-umc-ras-error-address.patch
@@ -0,0 +1,116 @@
+From 65ded04e13634290a69e07b16f081f03e684a8b8 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Wed, 24 Jul 2019 21:43:45 +0800
+Subject: [PATCH 3210/4256] drm/amdgpu: query umc ras error address
+
+query umc ras error address, translate it to gpu 4k page view
+and save it.
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 80 +++++++++++++++++++++++++++
+ 1 file changed, 80 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+index e05f3e68edb0..bff1a12f2cc9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+@@ -31,6 +31,16 @@
+ 
+ #define smnMCA_UMC0_MCUMC_ADDRT0	0x50f10
+ 
++/*
++ * (addr / 256) * 8192, the higher 26 bits in ErrorAddr
++ * is the index of 8KB block
++ */
++#define ADDR_OF_8KB_BLOCK(addr)		(((addr) & ~0xffULL) << 5)
++/* channel index is the index of 256B block */
++#define ADDR_OF_256B_BLOCK(channel_index)	((channel_index) << 8)
++/* offset in 256B block */
++#define OFFSET_IN_256B_BLOCK(addr)		((addr) & 0xffULL)
++
+ static uint32_t
+ 	umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM] = {
+ 		{2, 18, 11, 27},	{4, 20, 13, 29},
+@@ -158,6 +168,76 @@ static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev,
+ 	umc_v6_1_disable_umc_index_mode(adev);
+ }
+ 
++static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
++					 uint32_t umc_reg_offset, uint32_t channel_index,
++					 struct ras_err_data *err_data)
++{
++	uint32_t lsb;
++	uint64_t mc_umc_status, err_addr;
++	uint32_t mc_umc_status_addr;
++
++	/* skip error address process if -ENOMEM */
++	if (!err_data->err_addr)
++		return;
++
++	mc_umc_status_addr =
++		SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
++	mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
++
++	/* calculate error address if ue/ce error is detected */
++	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
++	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
++	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
++		err_addr = RREG64_PCIE(smnMCA_UMC0_MCUMC_ADDRT0 + umc_reg_offset * 4);
++
++		/* the lowest lsb bits should be ignored */
++		lsb = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, LSB);
++		err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
++		err_addr &= ~((0x1ULL << lsb) - 1);
++
++		/* translate umc channel address to soc pa, 3 parts are included */
++		err_data->err_addr[err_data->err_addr_cnt] =
++						ADDR_OF_8KB_BLOCK(err_addr)
++						| ADDR_OF_256B_BLOCK(channel_index)
++						| OFFSET_IN_256B_BLOCK(err_addr);
++
++		err_data->err_addr_cnt++;
++	}
++}
++
++static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
++					     void *ras_error_status)
++{
++	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
++	uint32_t umc_inst, channel_inst, umc_reg_offset;
++	uint32_t channel_index, mc_umc_status_addr;
++
++	mc_umc_status_addr =
++		SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
++
++	for (umc_inst = 0; umc_inst < UMC_V6_1_UMC_INSTANCE_NUM; umc_inst++) {
++		/* enable the index mode to query eror count per channel */
++		umc_v6_1_enable_umc_index_mode(adev, umc_inst);
++		for (channel_inst = 0; channel_inst < UMC_V6_1_CHANNEL_INSTANCE_NUM; channel_inst++) {
++			/* calc the register offset according to channel instance */
++			umc_reg_offset = UMC_V6_1_PER_CHANNEL_OFFSET * channel_inst;
++			/* get channel index of interleaved memory */
++			channel_index = umc_v6_1_channel_idx_tbl[umc_inst][channel_inst];
++
++			umc_v6_1_query_error_address(adev, umc_reg_offset,
++						     channel_index, err_data);
++
++			/* clear umc status */
++			WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
++			/* clear error address register */
++			WREG64_PCIE(smnMCA_UMC0_MCUMC_ADDRT0 + umc_reg_offset * 4, 0x0ULL);
++		}
++	}
++
++	umc_v6_1_disable_umc_index_mode(adev);
++}
++
+ const struct amdgpu_umc_funcs umc_v6_1_funcs = {
+ 	.query_ras_error_count = umc_v6_1_query_ras_error_count,
++	.query_ras_error_address = umc_v6_1_query_ras_error_address,
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3211-drm-amdgpu-allow-ras-interrupt-callback-to-return-er.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3211-drm-amdgpu-allow-ras-interrupt-callback-to-return-er.patch
new file mode 100644
index 00000000..1903dd72
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3211-drm-amdgpu-allow-ras-interrupt-callback-to-return-er.patch
@@ -0,0 +1,111 @@
+From cf82d487dc70caa465fdacf1608424646200f333 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Mon, 22 Jul 2019 20:27:25 +0800
+Subject: [PATCH 3211/4256] drm/amdgpu: allow ras interrupt callback to return
+ error data patch 1/2
+
+add error data as parameter for ras interrupt cb and process it
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c |  6 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 37 +++++++++++++------------
+ 2 files changed, 22 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 1914f37bee59..0eeb85d8399d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1003,7 +1003,7 @@ static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
+ 	struct ras_ih_data *data = &obj->ih_data;
+ 	struct amdgpu_iv_entry entry;
+ 	int ret;
+-	struct ras_err_data err_data = {0, 0};
++	struct ras_err_data err_data = {0, 0, 0, NULL};
+ 
+ 	while (data->rptr != data->wptr) {
+ 		rmb();
+@@ -1018,14 +1018,14 @@ static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
+ 		 * from the callback to udpate the error type/count, etc
+ 		 */
+ 		if (data->cb) {
+-			ret = data->cb(obj->adev, &entry);
++			ret = data->cb(obj->adev, &err_data, &entry);
+ 			/* ue will trigger an interrupt, and in that case
+ 			 * we need do a reset to recovery the whole system.
+ 			 * But leave IP do that recovery, here we just dispatch
+ 			 * the error.
+ 			 */
+ 			if (ret == AMDGPU_RAS_UE) {
+-				obj->err_data.ue_count++;
++				obj->err_data.ue_count += err_data.ue_count;
+ 			}
+ 			/* Might need get ce count by register, but not all IP
+ 			 * saves ce count, some IP just use one bit or two bits
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index 0920db7aff34..2c86a5135ec9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -76,9 +76,6 @@ struct ras_common_if {
+ 	char name[32];
+ };
+ 
+-typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
+-		struct amdgpu_iv_entry *entry);
+-
+ struct amdgpu_ras {
+ 	/* ras infrastructure */
+ 	/* for ras itself. */
+@@ -108,21 +105,6 @@ struct amdgpu_ras {
+ 	uint32_t flags;
+ };
+ 
+-struct ras_ih_data {
+-	/* interrupt bottom half */
+-	struct work_struct ih_work;
+-	int inuse;
+-	/* IP callback */
+-	ras_ih_cb cb;
+-	/* full of entries */
+-	unsigned char *ring;
+-	unsigned int ring_size;
+-	unsigned int element_size;
+-	unsigned int aligned_element_size;
+-	unsigned int rptr;
+-	unsigned int wptr;
+-};
+-
+ struct ras_fs_data {
+ 	char sysfs_name[32];
+ 	char debugfs_name[32];
+@@ -149,6 +131,25 @@ struct ras_err_handler_data {
+ 	int last_reserved;
+ };
+ 
++typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
++		struct ras_err_data *err_data,
++		struct amdgpu_iv_entry *entry);
++
++struct ras_ih_data {
++	/* interrupt bottom half */
++	struct work_struct ih_work;
++	int inuse;
++	/* IP callback */
++	ras_ih_cb cb;
++	/* full of entries */
++	unsigned char *ring;
++	unsigned int ring_size;
++	unsigned int element_size;
++	unsigned int aligned_element_size;
++	unsigned int rptr;
++	unsigned int wptr;
++};
++
+ struct ras_manager {
+ 	struct ras_common_if head;
+ 	/* reference count */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3212-drm-amdgpu-update-interrupt-callback-for-all-ras-cli.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3212-drm-amdgpu-update-interrupt-callback-for-all-ras-cli.patch
new file mode 100644
index 00000000..c11e4289
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3212-drm-amdgpu-update-interrupt-callback-for-all-ras-cli.patch
@@ -0,0 +1,79 @@
+From d47e3fd7dc46f7fa43ad4cba7c4d0310ef26fa44 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Mon, 22 Jul 2019 20:33:39 +0800
+Subject: [PATCH 3212/4256] drm/amdgpu: update interrupt callback for all ras
+ clients patch 2/2
+
+add err_data parameter in interrupt cb for ras clients
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 2 ++
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 ++
+ 3 files changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 1b24a338cbdf..b6569f221b51 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -3962,6 +3962,7 @@ static int gfx_v9_0_early_init(void *handle)
+ }
+ 
+ static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
++		struct ras_err_data *err_data,
+ 		struct amdgpu_iv_entry *entry);
+ 
+ static int gfx_v9_0_ecc_late_init(void *handle)
+@@ -5276,6 +5277,7 @@ static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
+ }
+ 
+ static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
++		struct ras_err_data *err_data,
+ 		struct amdgpu_iv_entry *entry)
+ {
+ 	/* TODO ue will trigger an interrupt. */
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 111ca34fdafe..76769e35a774 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -239,12 +239,12 @@ static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
+ }
+ 
+ static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
++		struct ras_err_data *err_data,
+ 		struct amdgpu_iv_entry *entry)
+ {
+-	struct ras_err_data err_data = {0, 0};
+ 	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
+ 	if (adev->umc.funcs->query_ras_error_count)
+-		adev->umc.funcs->query_ras_error_count(adev, &err_data);
++		adev->umc.funcs->query_ras_error_count(adev, err_data);
+ 	amdgpu_ras_reset_gpu(adev, 0);
+ 	return AMDGPU_RAS_UE;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 1e2f3d949d2e..bf9365c6e9b7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1626,6 +1626,7 @@ static int sdma_v4_0_early_init(void *handle)
+ }
+ 
+ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
++		struct ras_err_data *err_data,
+ 		struct amdgpu_iv_entry *entry);
+ 
+ static int sdma_v4_0_late_init(void *handle)
+@@ -1959,6 +1960,7 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
+ }
+ 
+ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
++		struct ras_err_data *err_data,
+ 		struct amdgpu_iv_entry *entry)
+ {
+ 	uint32_t instance, err_source;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3213-drm-amdgpu-add-check-for-ras-error-type.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3213-drm-amdgpu-add-check-for-ras-error-type.patch
new file mode 100644
index 00000000..61c39d80
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3213-drm-amdgpu-add-check-for-ras-error-type.patch
@@ -0,0 +1,39 @@
+From 2cbf422191513218b6b0108ef5441ff1272b6618 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Tue, 23 Jul 2019 13:07:24 +0800
+Subject: [PATCH 3213/4256] drm/amdgpu: add check for ras error type
+
+only ue and ce errors are supported
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 11 ++++++++---
+ 1 file changed, 8 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 0eeb85d8399d..a87deb7be414 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -153,9 +153,14 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
+ 			return -EINVAL;
+ 
+ 		data->head.block = block_id;
+-		data->head.type = memcmp("ue", err, 2) == 0 ?
+-			AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE :
+-			AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
++		/* only ue and ce errors are supported */
++		if (!memcmp("ue", err, 2))
++			data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++		else if (!memcmp("ce", err, 2))
++			data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
++		else
++			return -EINVAL;
++
+ 		data->op = op;
+ 
+ 		if (op == 2) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3214-drm-amdgpu-remove-ras_reserve_vram-in-ras-injection.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3214-drm-amdgpu-remove-ras_reserve_vram-in-ras-injection.patch
new file mode 100644
index 00000000..ac12913c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3214-drm-amdgpu-remove-ras_reserve_vram-in-ras-injection.patch
@@ -0,0 +1,65 @@
+From cefbcc894b7ae40b12dd6a0b6ad943ac8238344d Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Wed, 24 Jul 2019 11:19:56 +0800
+Subject: [PATCH 3214/4256] drm/amdgpu: remove ras_reserve_vram in ras
+ injection
+
+error injection address is not in gpu address space
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Dennis Li <dennis.li@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 21 ++++++++++-----------
+ 1 file changed, 10 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index a87deb7be414..ccd5863bca88 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -60,6 +60,9 @@ const char *ras_block_string[] = {
+ #define AMDGPU_RAS_FLAG_INIT_NEED_RESET		2
+ #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
+ 
++/* inject address is 52 bits */
++#define	RAS_UMC_INJECT_ADDR_LIMIT	(0x1ULL << 52)
++
+ static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev,
+ 		uint64_t offset, uint64_t size,
+ 		struct amdgpu_bo **bo_ptr);
+@@ -245,7 +248,6 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
+ 	struct ras_debug_if data;
+-	struct amdgpu_bo *bo;
+ 	int ret = 0;
+ 
+ 	ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
+@@ -263,17 +265,14 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *
+ 		ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
+ 		break;
+ 	case 2:
+-		ret = amdgpu_ras_reserve_vram(adev,
+-				data.inject.address, PAGE_SIZE, &bo);
+-		if (ret) {
+-			/* address was offset, now it is absolute.*/
+-			data.inject.address += adev->gmc.vram_start;
+-			if (data.inject.address > adev->gmc.vram_end)
+-				break;
+-		} else
+-			data.inject.address = amdgpu_bo_gpu_offset(bo);
++		if ((data.inject.address >= adev->gmc.mc_vram_size) ||
++		    (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
++			ret = -EINVAL;
++			break;
++		}
++
++		/* data.inject.address is offset instead of absolute gpu address */
+ 		ret = amdgpu_ras_error_inject(adev, &data.inject);
+-		amdgpu_ras_release_vram(adev, &bo);
+ 		break;
+ 	default:
+ 		ret = -EINVAL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3215-drm-amd-include-add-bitfield-define-for-EDC-register.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3215-drm-amd-include-add-bitfield-define-for-EDC-register.patch
new file mode 100644
index 00000000..0aeebb59
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3215-drm-amd-include-add-bitfield-define-for-EDC-register.patch
@@ -0,0 +1,206 @@
+From 28216d886f429203204f4cc011821d7223e117f8 Mon Sep 17 00:00:00 2001
+From: Dennis Li <Dennis.Li@amd.com>
+Date: Fri, 19 Jul 2019 14:42:49 +0800
+Subject: [PATCH 3215/4256] drm/amd/include: add bitfield define for EDC
+ registers
+
+Add EDC registers to support VEGA20 RAS
+
+Change-Id: Iafa8029135aa407edc0c77f1779a1cb9982c1492
+Signed-off-by: Dennis Li <Dennis.Li@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ .../amd/include/asic_reg/gc/gc_9_0_sh_mask.h  | 157 ++++++++++++++++++
+ 1 file changed, 157 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
+index 2e1214be67a2..064c4bb1dc62 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
+@@ -21,6 +21,105 @@
+ #ifndef _gc_9_0_SH_MASK_HEADER
+ #define _gc_9_0_SH_MASK_HEADER
+ 
++//GCEA_EDC_CNT
++#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                          0x0
++#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                          0x2
++#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                          0x4
++#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
++#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                         0x8
++#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                         0xa
++#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                            0xc
++#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                            0xe
++#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                            0x10
++#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                            0x12
++#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                         0x14
++#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                         0x16
++#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                            0x18
++#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                            0x1a
++#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                           0x1c
++#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                            0x00000003L
++#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                            0x0000000CL
++#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                            0x00000030L
++#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
++#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                           0x00000300L
++#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                           0x00000C00L
++#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                              0x00003000L
++#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                              0x0000C000L
++#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                              0x00030000L
++#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                              0x000C0000L
++#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                           0x00300000L
++#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                           0x00C00000L
++#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                              0x03000000L
++#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                              0x0C000000L
++#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                             0x30000000L
++
++#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                          0x0
++#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                          0x2
++#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                          0x4
++#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
++#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                         0x8
++#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                         0xa
++#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                         0xc
++#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                         0xe
++#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT                                                             0x10
++#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT                                                             0x12
++#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT                                                             0x14
++#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT                                                             0x16
++#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                            0x00000003L
++#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                            0x0000000CL
++#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                            0x00000030L
++#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
++#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                           0x00000300L
++#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                           0x00000C00L
++#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                           0x00003000L
++#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                           0x0000C000L
++#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK                                                               0x00030000L
++#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK                                                               0x000C0000L
++#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK                                                               0x00300000L
++#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK                                                               0x00C00000L
++
++// addressBlock: gc_cppdec2
++//CPF_EDC_TAG_CNT
++#define CPF_EDC_TAG_CNT__DED_COUNT__SHIFT                                                                     0x0
++#define CPF_EDC_TAG_CNT__SEC_COUNT__SHIFT                                                                     0x2
++#define CPF_EDC_TAG_CNT__DED_COUNT_MASK                                                                       0x00000003L
++#define CPF_EDC_TAG_CNT__SEC_COUNT_MASK                                                                       0x0000000CL
++//CPF_EDC_ROQ_CNT
++#define CPF_EDC_ROQ_CNT__COUNT_ME1__SHIFT                                                                     0x0
++#define CPF_EDC_ROQ_CNT__COUNT_ME2__SHIFT                                                                     0x2
++#define CPF_EDC_ROQ_CNT__COUNT_ME1_MASK                                                                       0x00000003L
++#define CPF_EDC_ROQ_CNT__COUNT_ME2_MASK                                                                       0x0000000CL
++//CPG_EDC_TAG_CNT
++#define CPG_EDC_TAG_CNT__DED_COUNT__SHIFT                                                                     0x0
++#define CPG_EDC_TAG_CNT__SEC_COUNT__SHIFT                                                                     0x2
++#define CPG_EDC_TAG_CNT__DED_COUNT_MASK                                                                       0x00000003L
++#define CPG_EDC_TAG_CNT__SEC_COUNT_MASK                                                                       0x0000000CL
++//CPG_EDC_DMA_CNT
++#define CPG_EDC_DMA_CNT__ROQ_COUNT__SHIFT                                                                     0x0
++#define CPG_EDC_DMA_CNT__TAG_DED_COUNT__SHIFT                                                                 0x2
++#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT__SHIFT                                                                 0x4
++#define CPG_EDC_DMA_CNT__ROQ_COUNT_MASK                                                                       0x00000003L
++#define CPG_EDC_DMA_CNT__TAG_DED_COUNT_MASK                                                                   0x0000000CL
++#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT_MASK                                                                   0x00000030L
++//CPC_EDC_SCRATCH_CNT
++#define CPC_EDC_SCRATCH_CNT__DED_COUNT__SHIFT                                                                 0x0
++#define CPC_EDC_SCRATCH_CNT__SEC_COUNT__SHIFT                                                                 0x2
++#define CPC_EDC_SCRATCH_CNT__DED_COUNT_MASK                                                                   0x00000003L
++#define CPC_EDC_SCRATCH_CNT__SEC_COUNT_MASK                                                                   0x0000000CL
++//CPC_EDC_UCODE_CNT
++#define CPC_EDC_UCODE_CNT__DED_COUNT__SHIFT                                                                   0x0
++#define CPC_EDC_UCODE_CNT__SEC_COUNT__SHIFT                                                                   0x2
++#define CPC_EDC_UCODE_CNT__DED_COUNT_MASK                                                                     0x00000003L
++#define CPC_EDC_UCODE_CNT__SEC_COUNT_MASK                                                                     0x0000000CL
++//DC_EDC_STATE_CNT
++#define DC_EDC_STATE_CNT__COUNT_ME1__SHIFT                                                                    0x0
++#define DC_EDC_STATE_CNT__COUNT_ME1_MASK                                                                      0x00000003L
++//DC_EDC_CSINVOC_CNT
++#define DC_EDC_CSINVOC_CNT__COUNT_ME1__SHIFT                                                                  0x0
++#define DC_EDC_CSINVOC_CNT__COUNT_ME1_MASK                                                                    0x00000003L
++//DC_EDC_RESTORE_CNT
++#define DC_EDC_RESTORE_CNT__COUNT_ME1__SHIFT                                                                  0x0
++#define DC_EDC_RESTORE_CNT__COUNT_ME1_MASK                                                                    0x00000003L
+ 
+ // addressBlock: gc_grbmdec
+ //GRBM_CNTL
+@@ -9033,11 +9132,15 @@
+ #define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT__SHIFT                                                      0x4
+ #define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT__SHIFT                                                  0x6
+ #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT__SHIFT                                                   0x8
++#define TCC_EDC_CNT2__WRRET_TAG_WRITE_RETURN_SED_COUNT__SHIFT                                                 0xa
++#define TCC_EDC_CNT2__ATOMIC_RETURN_BUFFER_SED_COUNT__SHIFT                                                   0xc
+ #define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT_MASK                                                             0x00000003L
+ #define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT_MASK                                                         0x0000000CL
+ #define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT_MASK                                                        0x00000030L
+ #define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT_MASK                                                    0x000000C0L
+ #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT_MASK                                                     0x00000300L
++#define TCC_EDC_CNT2__WRRET_TAG_WRITE_RETURN_SED_COUNT_MASK                                                   0x00000C00L
++#define TCC_EDC_CNT2__ATOMIC_RETURN_BUFFER_SED_COUNT_MASK                                                     0x00003000L
+ //TCC_REDUNDANCY
+ #define TCC_REDUNDANCY__MC_SEL0__SHIFT                                                                        0x0
+ #define TCC_REDUNDANCY__MC_SEL1__SHIFT                                                                        0x1
+@@ -29818,6 +29921,60 @@
+ #define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                         0x0
+ #define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                           0xFFFFFFFFL
+ 
++//TA_EDC_CNT
++#define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT__SHIFT                                                              0x0
++#define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT__SHIFT                                                              0x2
++#define TA_EDC_CNT__TA_FS_AFIFO_SED_COUNT__SHIFT                                                              0x4
++#define TA_EDC_CNT__TA_FL_LFIFO_SED_COUNT__SHIFT                                                              0x6
++#define TA_EDC_CNT__TA_FX_LFIFO_SED_COUNT__SHIFT                                                              0x8
++#define TA_EDC_CNT__TA_FS_CFIFO_SED_COUNT__SHIFT                                                              0xa
++#define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT_MASK                                                                0x00000003L
++#define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT_MASK                                                                0x0000000CL
++#define TA_EDC_CNT__TA_FS_AFIFO_SED_COUNT_MASK                                                                0x00000030L
++#define TA_EDC_CNT__TA_FL_LFIFO_SED_COUNT_MASK                                                                0x000000C0L
++#define TA_EDC_CNT__TA_FX_LFIFO_SED_COUNT_MASK                                                                0x00000300L
++#define TA_EDC_CNT__TA_FS_CFIFO_SED_COUNT_MASK                                                                0x00000C00L
++
++//TCI_EDC_CNT
++#define TCI_EDC_CNT__WRITE_RAM_SED_COUNT__SHIFT                                                               0x0
++#define TCI_EDC_CNT__WRITE_RAM_SED_COUNT_MASK                                                                 0x00000003L
++
++//TCP_EDC_CNT_NEW
++#define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT__SHIFT                                                           0x0
++#define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT__SHIFT                                                           0x2
++#define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT__SHIFT                                                           0x4
++#define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT__SHIFT                                                           0x6
++#define TCP_EDC_CNT_NEW__CMD_FIFO_SED_COUNT__SHIFT                                                            0x8
++#define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT__SHIFT                                                             0xa
++#define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT__SHIFT                                                             0xc
++#define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT__SHIFT                                                              0xe
++#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT__SHIFT                                                        0x10
++#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT__SHIFT                                                        0x12
++#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT__SHIFT                                                        0x14
++#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT__SHIFT                                                        0x16
++#define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT_MASK                                                             0x00000003L
++#define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT_MASK                                                             0x0000000CL
++#define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT_MASK                                                             0x00000030L
++#define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT_MASK                                                             0x000000C0L
++#define TCP_EDC_CNT_NEW__CMD_FIFO_SED_COUNT_MASK                                                              0x00000300L
++#define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT_MASK                                                               0x00000C00L
++#define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT_MASK                                                               0x00003000L
++#define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT_MASK                                                                0x0000C000L
++#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT_MASK                                                          0x00030000L
++#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT_MASK                                                          0x000C0000L
++#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT_MASK                                                          0x00300000L
++#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT_MASK                                                          0x00C00000L
+ 
++//TD_EDC_CNT
++#define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT__SHIFT                                                               0x0
++#define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT__SHIFT                                                               0x2
++#define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT__SHIFT                                                               0x4
++#define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT__SHIFT                                                               0x6
++#define TD_EDC_CNT__CS_FIFO_SED_COUNT__SHIFT                                                                  0x8
++#define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT_MASK                                                                 0x00000003L
++#define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT_MASK                                                                 0x0000000CL
++#define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT_MASK                                                                 0x00000030L
++#define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT_MASK                                                                 0x000000C0L
++#define TD_EDC_CNT__CS_FIFO_SED_COUNT_MASK                                                                    0x00000300L
+ 
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3216-drm-amd-include-add-define-of-TCP_EDC_CNT_NEW.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3216-drm-amd-include-add-define-of-TCP_EDC_CNT_NEW.patch
new file mode 100644
index 00000000..f72facf9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3216-drm-amd-include-add-define-of-TCP_EDC_CNT_NEW.patch
@@ -0,0 +1,29 @@
+From 8d2dd63167d0ef3303f3d95a1eaf230e823b1387 Mon Sep 17 00:00:00 2001
+From: Dennis Li <Dennis.Li@amd.com>
+Date: Fri, 19 Jul 2019 14:50:25 +0800
+Subject: [PATCH 3216/4256] drm/amd/include: add define of TCP_EDC_CNT_NEW
+
+Change-Id: Iedd4bac2187e3b800662485d4623ace246af3f36
+Signed-off-by: Dennis Li <Dennis.Li@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
+index f1d048e0ed2c..ca16d9125fbc 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
+@@ -1700,6 +1700,8 @@
+ #define mmTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX                                                           0
+ #define mmTCP_EDC_CNT                                                                                  0x0b17
+ #define mmTCP_EDC_CNT_BASE_IDX                                                                         0
++#define mmTCP_EDC_CNT_NEW                                                                              0x0b18
++#define mmTCP_EDC_CNT_NEW_BASE_IDX                                                                     0
+ #define mmTC_CFG_L1_LOAD_POLICY0                                                                       0x0b1a
+ #define mmTC_CFG_L1_LOAD_POLICY0_BASE_IDX                                                              0
+ #define mmTC_CFG_L1_LOAD_POLICY1                                                                       0x0b1b
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3217-drm-amdgpu-add-define-for-gfx-ras-subblock.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3217-drm-amdgpu-add-define-for-gfx-ras-subblock.patch
new file mode 100644
index 00000000..ab57e943
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3217-drm-amdgpu-add-define-for-gfx-ras-subblock.patch
@@ -0,0 +1,470 @@
+From 915c10e08f420ab049cc46351589a34e886864dc Mon Sep 17 00:00:00 2001
+From: Dennis Li <Dennis.Li@amd.com>
+Date: Fri, 19 Jul 2019 15:22:29 +0800
+Subject: [PATCH 3217/4256] drm/amdgpu: add define for gfx ras subblock
+
+Change-Id: Ib4b019b2bcbe6ef0b85ef170e7cf032bfa400553
+Signed-off-by: Dennis Li <Dennis.Li@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 230 ++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 201 +++++++++++++++++++++
+ 2 files changed, 431 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index 2c86a5135ec9..2765f2dbb1e6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -52,6 +52,236 @@ enum amdgpu_ras_block {
+ #define AMDGPU_RAS_BLOCK_COUNT	AMDGPU_RAS_BLOCK__LAST
+ #define AMDGPU_RAS_BLOCK_MASK	((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
+ 
++enum amdgpu_ras_gfx_subblock {
++	/* CPC */
++	AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
++	AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
++		AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
++	AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
++	AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
++	AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
++	AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
++	AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
++	AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
++	AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
++		AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
++	/* CPF */
++	AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
++		AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
++	AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
++	AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
++	/* CPG */
++	AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
++		AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
++	AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
++	AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
++	/* GDS */
++	AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
++	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
++	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
++	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
++	AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
++		AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
++	/* SPI */
++	AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
++	/* SQ */
++	AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
++	AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
++	AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
++	AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
++	/* SQC (3 ranges) */
++	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
++	/* SQC range 0 */
++	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
++		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
++		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
++	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
++	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
++	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
++	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
++	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
++	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
++	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
++		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
++	/* SQC range 1 */
++	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
++	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
++		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
++	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
++	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
++	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
++	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
++	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
++	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
++	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
++	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
++	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
++		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
++	/* SQC range 2 */
++	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
++	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
++		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
++	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
++	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
++	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
++	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
++	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
++	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
++	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
++	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
++	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
++		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
++	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
++		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
++	/* TA */
++	AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
++		AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
++	AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
++	AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
++	AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
++	AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
++	/* TCA */
++	AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
++		AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
++	AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
++		AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
++	/* TCC (5 sub-ranges) */
++	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
++	/* TCC range 0 */
++	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
++		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
++		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
++	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
++	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
++	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
++	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
++	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
++	AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
++	AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
++	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
++		AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
++	/* TCC range 1 */
++	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
++	AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
++		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
++	AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
++	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
++		AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
++	/* TCC range 2 */
++	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
++	AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
++		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
++	AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
++	AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
++	AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
++	AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
++	AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
++	AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
++	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
++	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
++		AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
++	/* TCC range 3 */
++	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
++	AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
++		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
++	AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
++	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
++		AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
++	/* TCC range 4 */
++	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
++	AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
++		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
++	AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
++	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
++		AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
++	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
++		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
++	/* TCI */
++	AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
++	/* TCP */
++	AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
++		AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
++	AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
++	AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
++	AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
++	AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
++	AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
++	AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
++		AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
++	/* TD */
++	AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
++		AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
++	AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
++	AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
++	/* EA (3 sub-ranges) */
++	AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
++	/* EA range 0 */
++	AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
++		AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
++	AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
++		AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
++	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
++	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
++	AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
++	AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
++	AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
++	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
++	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
++	AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
++		AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
++	/* EA range 1 */
++	AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
++	AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
++		AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
++	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
++	AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
++	AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
++	AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
++	AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
++	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
++	AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
++		AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
++	/* EA range 2 */
++	AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
++	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
++		AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
++	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
++	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
++	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
++	AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
++		AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
++	AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
++		AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
++	/* UTC VM L2 bank */
++	AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
++	/* UTC VM walker */
++	AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
++	/* UTC ATC L2 2MB cache */
++	AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
++	/* UTC ATC L2 4KB cache */
++	AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
++	AMDGPU_RAS_BLOCK__GFX_MAX
++};
++
+ enum amdgpu_ras_error_type {
+ 	AMDGPU_RAS_ERROR__NONE							= 0,
+ 	AMDGPU_RAS_ERROR__PARITY						= 1,
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index b6569f221b51..e10bc8749333 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -117,6 +117,207 @@ MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin");
+ #define mmTCP_CHAN_STEER_5_ARCT								0x0b0c
+ #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX							0
+ 
++enum ta_ras_gfx_subblock {
++	/*CPC*/
++	TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
++	TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START,
++	TA_RAS_BLOCK__GFX_CPC_UCODE,
++	TA_RAS_BLOCK__GFX_DC_STATE_ME1,
++	TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
++	TA_RAS_BLOCK__GFX_DC_RESTORE_ME1,
++	TA_RAS_BLOCK__GFX_DC_STATE_ME2,
++	TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
++	TA_RAS_BLOCK__GFX_DC_RESTORE_ME2,
++	TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2,
++	/* CPF*/
++	TA_RAS_BLOCK__GFX_CPF_INDEX_START,
++	TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START,
++	TA_RAS_BLOCK__GFX_CPF_ROQ_ME1,
++	TA_RAS_BLOCK__GFX_CPF_TAG,
++	TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG,
++	/* CPG*/
++	TA_RAS_BLOCK__GFX_CPG_INDEX_START,
++	TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START,
++	TA_RAS_BLOCK__GFX_CPG_DMA_TAG,
++	TA_RAS_BLOCK__GFX_CPG_TAG,
++	TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG,
++	/* GDS*/
++	TA_RAS_BLOCK__GFX_GDS_INDEX_START,
++	TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START,
++	TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
++	TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
++	TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
++	TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
++	TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
++	/* SPI*/
++	TA_RAS_BLOCK__GFX_SPI_SR_MEM,
++	/* SQ*/
++	TA_RAS_BLOCK__GFX_SQ_INDEX_START,
++	TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START,
++	TA_RAS_BLOCK__GFX_SQ_LDS_D,
++	TA_RAS_BLOCK__GFX_SQ_LDS_I,
++	TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/
++	TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR,
++	/* SQC (3 ranges)*/
++	TA_RAS_BLOCK__GFX_SQC_INDEX_START,
++	/* SQC range 0*/
++	TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START,
++	TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
++		TA_RAS_BLOCK__GFX_SQC_INDEX0_START,
++	TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
++	TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
++	TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
++	TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
++	TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
++	TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
++	TA_RAS_BLOCK__GFX_SQC_INDEX0_END =
++		TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
++	/* SQC range 1*/
++	TA_RAS_BLOCK__GFX_SQC_INDEX1_START,
++	TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
++		TA_RAS_BLOCK__GFX_SQC_INDEX1_START,
++	TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
++	TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
++	TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
++	TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
++	TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
++	TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
++	TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
++	TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
++	TA_RAS_BLOCK__GFX_SQC_INDEX1_END =
++		TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
++	/* SQC range 2*/
++	TA_RAS_BLOCK__GFX_SQC_INDEX2_START,
++	TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
++		TA_RAS_BLOCK__GFX_SQC_INDEX2_START,
++	TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
++	TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
++	TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
++	TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
++	TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
++	TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
++	TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
++	TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
++	TA_RAS_BLOCK__GFX_SQC_INDEX2_END =
++		TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
++	TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END,
++	/* TA*/
++	TA_RAS_BLOCK__GFX_TA_INDEX_START,
++	TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START,
++	TA_RAS_BLOCK__GFX_TA_FS_AFIFO,
++	TA_RAS_BLOCK__GFX_TA_FL_LFIFO,
++	TA_RAS_BLOCK__GFX_TA_FX_LFIFO,
++	TA_RAS_BLOCK__GFX_TA_FS_CFIFO,
++	TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO,
++	/* TCA*/
++	TA_RAS_BLOCK__GFX_TCA_INDEX_START,
++	TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START,
++	TA_RAS_BLOCK__GFX_TCA_REQ_FIFO,
++	TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO,
++	/* TCC (5 sub-ranges)*/
++	TA_RAS_BLOCK__GFX_TCC_INDEX_START,
++	/* TCC range 0*/
++	TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START,
++	TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START,
++	TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
++	TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
++	TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
++	TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
++	TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
++	TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
++	TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
++	TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
++	/* TCC range 1*/
++	TA_RAS_BLOCK__GFX_TCC_INDEX1_START,
++	TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START,
++	TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
++	TA_RAS_BLOCK__GFX_TCC_INDEX1_END =
++		TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
++	/* TCC range 2*/
++	TA_RAS_BLOCK__GFX_TCC_INDEX2_START,
++	TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START,
++	TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
++	TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
++	TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
++	TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
++	TA_RAS_BLOCK__GFX_TCC_SRC_FIFO,
++	TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
++	TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
++	TA_RAS_BLOCK__GFX_TCC_INDEX2_END =
++		TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
++	/* TCC range 3*/
++	TA_RAS_BLOCK__GFX_TCC_INDEX3_START,
++	TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START,
++	TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
++	TA_RAS_BLOCK__GFX_TCC_INDEX3_END =
++		TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
++	/* TCC range 4*/
++	TA_RAS_BLOCK__GFX_TCC_INDEX4_START,
++	TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
++		TA_RAS_BLOCK__GFX_TCC_INDEX4_START,
++	TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
++	TA_RAS_BLOCK__GFX_TCC_INDEX4_END =
++		TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
++	TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END,
++	/* TCI*/
++	TA_RAS_BLOCK__GFX_TCI_WRITE_RAM,
++	/* TCP*/
++	TA_RAS_BLOCK__GFX_TCP_INDEX_START,
++	TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START,
++	TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
++	TA_RAS_BLOCK__GFX_TCP_CMD_FIFO,
++	TA_RAS_BLOCK__GFX_TCP_VM_FIFO,
++	TA_RAS_BLOCK__GFX_TCP_DB_RAM,
++	TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
++	TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
++	TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
++	/* TD*/
++	TA_RAS_BLOCK__GFX_TD_INDEX_START,
++	TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START,
++	TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
++	TA_RAS_BLOCK__GFX_TD_CS_FIFO,
++	TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO,
++	/* EA (3 sub-ranges)*/
++	TA_RAS_BLOCK__GFX_EA_INDEX_START,
++	/* EA range 0*/
++	TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START,
++	TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START,
++	TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
++	TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
++	TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
++	TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
++	TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
++	TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
++	TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
++	TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
++	/* EA range 1*/
++	TA_RAS_BLOCK__GFX_EA_INDEX1_START,
++	TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START,
++	TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
++	TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
++	TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
++	TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
++	TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
++	TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
++	TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
++	/* EA range 2*/
++	TA_RAS_BLOCK__GFX_EA_INDEX2_START,
++	TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START,
++	TA_RAS_BLOCK__GFX_EA_MAM_D1MEM,
++	TA_RAS_BLOCK__GFX_EA_MAM_D2MEM,
++	TA_RAS_BLOCK__GFX_EA_MAM_D3MEM,
++	TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM,
++	TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END,
++	/* UTC VM L2 bank*/
++	TA_RAS_BLOCK__UTC_VML2_BANK_CACHE,
++	/* UTC VM walker*/
++	TA_RAS_BLOCK__UTC_VML2_WALKER,
++	/* UTC ATC L2 2MB cache*/
++	TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
++	/* UTC ATC L2 4KB cache*/
++	TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
++	TA_RAS_BLOCK__GFX_MAX
++};
+ static const struct soc15_reg_golden golden_settings_gc_9_0[] =
+ {
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3218-drm-amdgpu-add-RAS-callback-for-gfx.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3218-drm-amdgpu-add-RAS-callback-for-gfx.patch
new file mode 100644
index 00000000..ad6c6e9f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3218-drm-amdgpu-add-RAS-callback-for-gfx.patch
@@ -0,0 +1,593 @@
+From c4a4357417ddafd414890af7506d8514f1bcae30 Mon Sep 17 00:00:00 2001
+From: Dennis Li <Dennis.Li@amd.com>
+Date: Wed, 31 Jul 2019 20:42:15 +0800
+Subject: [PATCH 3218/4256] drm/amdgpu: add RAS callback for gfx
+
+Add functions for RAS error inject and query error counter
+
+Signed-off-by: Dennis Li <Dennis.Li@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |   2 +
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 530 +++++++++++++++++++++++-
+ 2 files changed, 531 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+index 1199b5828b90..554a59b3c4a6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+@@ -196,6 +196,8 @@ struct amdgpu_gfx_funcs {
+ 				uint32_t *dst);
+ 	void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
+ 				 u32 queue, u32 vmid);
++	int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
++	int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status);
+ };
+ 
+ struct amdgpu_ngg_buf {
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index e10bc8749333..371abcdccb32 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -318,6 +318,135 @@ enum ta_ras_gfx_subblock {
+ 	TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
+ 	TA_RAS_BLOCK__GFX_MAX
+ };
++
++struct ras_gfx_subblock {
++	unsigned char *name;
++	int ta_subblock;
++	int supported_error_type;
++};
++
++#define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d)                             \
++	[AMDGPU_RAS_BLOCK__##subblock] = {                                     \
++		#subblock,                                                     \
++		TA_RAS_BLOCK__##subblock,                                      \
++		((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)),                  \
++	}
++
++static const struct ras_gfx_subblock ras_gfx_subblocks[] = {
++	AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1),
++};
++
+ static const struct soc15_reg_golden golden_settings_gc_9_0[] =
+ {
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
+@@ -536,6 +665,10 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
+ static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
+ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
+ static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
++static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
++					  void *ras_error_status);
++static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
++				     void *inject_if);
+ 
+ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
+ {
+@@ -1621,7 +1754,9 @@ static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
+ 	.read_wave_data = &gfx_v9_0_read_wave_data,
+ 	.read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
+ 	.read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
+-	.select_me_pipe_q = &gfx_v9_0_select_me_pipe_q
++	.select_me_pipe_q = &gfx_v9_0_select_me_pipe_q,
++	.ras_error_inject = &gfx_v9_0_ras_error_inject,
++	.query_ras_error_count = &gfx_v9_0_query_ras_error_count
+ };
+ 
+ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
+@@ -5487,6 +5622,399 @@ static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+ 	return AMDGPU_RAS_UE;
+ }
+ 
++static const struct {
++	const char *name;
++	uint32_t ip;
++	uint32_t inst;
++	uint32_t seg;
++	uint32_t reg_offset;
++	uint32_t per_se_instance;
++	int32_t num_instance;
++	uint32_t sec_count_mask;
++	uint32_t ded_count_mask;
++} gfx_ras_edc_regs[] = {
++	{ "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1,
++	  REG_FIELD_MASK(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
++	  REG_FIELD_MASK(CPC_EDC_SCRATCH_CNT, DED_COUNT) },
++	{ "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1,
++	  REG_FIELD_MASK(CPC_EDC_UCODE_CNT, SEC_COUNT),
++	  REG_FIELD_MASK(CPC_EDC_UCODE_CNT, DED_COUNT) },
++	{ "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1,
++	  REG_FIELD_MASK(CPF_EDC_ROQ_CNT, COUNT_ME1), 0 },
++	{ "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1,
++	  REG_FIELD_MASK(CPF_EDC_ROQ_CNT, COUNT_ME2), 0 },
++	{ "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1,
++	  REG_FIELD_MASK(CPF_EDC_TAG_CNT, SEC_COUNT),
++	  REG_FIELD_MASK(CPF_EDC_TAG_CNT, DED_COUNT) },
++	{ "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1,
++	  REG_FIELD_MASK(CPG_EDC_DMA_CNT, ROQ_COUNT), 0 },
++	{ "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1,
++	  REG_FIELD_MASK(CPG_EDC_DMA_CNT, TAG_SEC_COUNT),
++	  REG_FIELD_MASK(CPG_EDC_DMA_CNT, TAG_DED_COUNT) },
++	{ "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1,
++	  REG_FIELD_MASK(CPG_EDC_TAG_CNT, SEC_COUNT),
++	  REG_FIELD_MASK(CPG_EDC_TAG_CNT, DED_COUNT) },
++	{ "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1,
++	  REG_FIELD_MASK(DC_EDC_CSINVOC_CNT, COUNT_ME1), 0 },
++	{ "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1,
++	  REG_FIELD_MASK(DC_EDC_RESTORE_CNT, COUNT_ME1), 0 },
++	{ "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1,
++	  REG_FIELD_MASK(DC_EDC_STATE_CNT, COUNT_ME1), 0 },
++	{ "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1,
++	  REG_FIELD_MASK(GDS_EDC_CNT, GDS_MEM_SEC),
++	  REG_FIELD_MASK(GDS_EDC_CNT, GDS_MEM_DED) },
++	{ "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1,
++	  REG_FIELD_MASK(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), 0 },
++	{ "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
++	  0, 1, REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC),
++	  REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) },
++	{ "GDS_OA_PHY_PHY_CMD_RAM_MEM",
++	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1,
++	  REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC),
++	  REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) },
++	{ "GDS_OA_PHY_PHY_DATA_RAM_MEM",
++	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1,
++	  REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), 0 },
++	{ "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM",
++	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
++	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC),
++	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) },
++	{ "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM",
++	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
++	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC),
++	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) },
++	{ "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM",
++	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
++	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC),
++	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) },
++	{ "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM",
++	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
++	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC),
++	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) },
++	{ "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 1, 1,
++	  REG_FIELD_MASK(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), 0 },
++	{ "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
++	  REG_FIELD_MASK(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT),
++	  REG_FIELD_MASK(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) },
++	{ "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
++	  REG_FIELD_MASK(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), 0 },
++	{ "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
++	  REG_FIELD_MASK(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), 0 },
++	{ "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
++	  REG_FIELD_MASK(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), 0 },
++	{ "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
++	  REG_FIELD_MASK(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), 0 },
++	{ "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 2,
++	  REG_FIELD_MASK(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), 0 },
++	{ "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 2,
++	  REG_FIELD_MASK(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), 0 },
++	{ "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
++	  REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT),
++	  REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) },
++	{ "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
++	  REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT),
++	  REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) },
++	{ "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
++	  REG_FIELD_MASK(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT),
++	  REG_FIELD_MASK(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) },
++	{ "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
++	  REG_FIELD_MASK(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT),
++	  REG_FIELD_MASK(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) },
++	{ "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
++	  REG_FIELD_MASK(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT),
++	  REG_FIELD_MASK(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) },
++	{ "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
++	  REG_FIELD_MASK(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), 0 },
++	{ "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
++	  REG_FIELD_MASK(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), 0 },
++	{ "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
++	  REG_FIELD_MASK(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), 0 },
++	{ "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
++	  REG_FIELD_MASK(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), 0 },
++	{ "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
++	  REG_FIELD_MASK(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), 0 },
++	{ "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
++	  REG_FIELD_MASK(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), 0 },
++	{ "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 16,
++	  REG_FIELD_MASK(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), 0 },
++	{ "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 16,
++	  REG_FIELD_MASK(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), 0 },
++	{ "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0,
++	  16, REG_FIELD_MASK(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), 0 },
++	{ "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
++	  0, 16, REG_FIELD_MASK(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT),
++	  0 },
++	{ "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0,
++	  16, REG_FIELD_MASK(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), 0 },
++	{ "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
++	  0, 16, REG_FIELD_MASK(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT),
++	  0 },
++	{ "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0,
++	  16, REG_FIELD_MASK(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), 0 },
++	{ "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 72,
++	  REG_FIELD_MASK(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), 0 },
++	{ "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
++	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT),
++	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) },
++	{ "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
++	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT),
++	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) },
++	{ "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
++	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), 0 },
++	{ "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
++	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), 0 },
++	{ "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
++	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 0 },
++	{ "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
++	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT),
++	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) },
++	{ "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
++	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT),
++	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) },
++	{ "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16,
++	  REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT),
++	  REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) },
++	{ "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16,
++	  REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT),
++	  REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) },
++	{ "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16,
++	  REG_FIELD_MASK(TD_EDC_CNT, CS_FIFO_SED_COUNT), 0 },
++	{ "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
++	  REG_FIELD_MASK(SQ_EDC_CNT, LDS_D_SEC_COUNT),
++	  REG_FIELD_MASK(SQ_EDC_CNT, LDS_D_DED_COUNT) },
++	{ "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
++	  REG_FIELD_MASK(SQ_EDC_CNT, LDS_I_SEC_COUNT),
++	  REG_FIELD_MASK(SQ_EDC_CNT, LDS_I_DED_COUNT) },
++	{ "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
++	  REG_FIELD_MASK(SQ_EDC_CNT, SGPR_SEC_COUNT),
++	  REG_FIELD_MASK(SQ_EDC_CNT, SGPR_DED_COUNT) },
++	{ "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
++	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR0_SEC_COUNT),
++	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR0_DED_COUNT) },
++	{ "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
++	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR1_SEC_COUNT),
++	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR1_DED_COUNT) },
++	{ "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
++	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR2_SEC_COUNT),
++	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR2_DED_COUNT) },
++	{ "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
++	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR3_SEC_COUNT),
++	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR3_DED_COUNT) },
++	{ "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
++	  1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT),
++	  REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) },
++	{ "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1,
++	  6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT),
++	  REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) },
++	{ "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
++	  1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT),
++	  REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) },
++	{ "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1,
++	  6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT),
++	  REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) },
++	{ "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
++	  1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT),
++	  REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) },
++	{ "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1,
++	  6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT),
++	  REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) },
++	{ "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
++	  6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT),
++	  REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) },
++	{ "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
++	  6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT),
++	  REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) },
++	{ "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
++	  6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT),
++	  REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) },
++	{ "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
++	  6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT),
++	  REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) },
++	{ "SQC_INST_BANKA_UTCL1_MISS_FIFO",
++	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6,
++	  REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT),
++	  0 },
++	{ "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
++	  6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), 0 },
++	{ "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
++	  6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), 0 },
++	{ "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
++	  6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), 0 },
++	{ "SQC_DATA_BANKA_DIRTY_BIT_RAM",
++	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6,
++	  REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), 0 },
++	{ "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6,
++	  REG_FIELD_MASK(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT),
++	  REG_FIELD_MASK(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) },
++	{ "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
++	  6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT),
++	  REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) },
++	{ "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
++	  6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT),
++	  REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) },
++	{ "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
++	  6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT),
++	  REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) },
++	{ "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
++	  6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT),
++	  REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) },
++	{ "SQC_INST_BANKB_UTCL1_MISS_FIFO",
++	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, 6,
++	  REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT),
++	  0 },
++	{ "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
++	  6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), 0 },
++	{ "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
++	  6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), 0 },
++	{ "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
++	  6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), 0 },
++	{ "SQC_DATA_BANKB_DIRTY_BIT_RAM",
++	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, 6,
++	  REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), 0 },
++	{ "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
++	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) },
++	{ "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
++	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) },
++	{ "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
++	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) },
++	{ "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
++	  REG_FIELD_MASK(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) },
++	{ "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
++	  REG_FIELD_MASK(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) },
++	{ "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 0 },
++	{ "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 0 },
++	{ "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 0 },
++	{ "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 0 },
++	{ "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 0 },
++	{ "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
++	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) },
++	{ "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
++	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) },
++	{ "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
++	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) },
++	{ "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 0 },
++	{ "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 0 },
++	{ "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), 0 },
++	{ "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), 0 },
++	{ "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), 0 },
++	{ "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
++	  REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), 0 },
++};
++
++static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
++				     void *inject_if)
++{
++	struct ras_inject_if *info = (struct ras_inject_if *)inject_if;
++	int ret;
++	struct ta_ras_trigger_error_input block_info = { 0 };
++
++	if (adev->asic_type != CHIP_VEGA20)
++		return -EINVAL;
++
++	if (!ras_gfx_subblocks[info->head.sub_block_index].name)
++		return -EPERM;
++
++	if (!(ras_gfx_subblocks[info->head.sub_block_index].supported_error_type &
++	      info->head.type))
++		return -EPERM;
++
++	block_info.block_id = amdgpu_ras_block_to_ta(info->head.block);
++	block_info.sub_block_index =
++		ras_gfx_subblocks[info->head.sub_block_index].ta_subblock;
++	block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type);
++	block_info.address = info->address;
++	block_info.value = info->value;
++
++	mutex_lock(&adev->grbm_idx_mutex);
++	ret = psp_ras_trigger_error(&adev->psp, &block_info);
++	mutex_unlock(&adev->grbm_idx_mutex);
++
++	return ret;
++}
++
++static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
++					  void *ras_error_status)
++{
++	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
++	uint32_t sec_count, ded_count;
++	uint32_t i;
++	uint32_t reg_value;
++	uint32_t se_id, instance_id;
++
++	if (adev->asic_type != CHIP_VEGA20)
++		return -EINVAL;
++
++	err_data->ue_count = 0;
++	err_data->ce_count = 0;
++
++	mutex_lock(&adev->grbm_idx_mutex);
++	for (se_id = 0; se_id < adev->gfx.config.max_shader_engines; se_id++) {
++		for (instance_id = 0; instance_id < 256; instance_id++) {
++			for (i = 0;
++			     i < sizeof(gfx_ras_edc_regs) / sizeof(gfx_ras_edc_regs[0]);
++			     i++) {
++				if (se_id != 0 &&
++				    !gfx_ras_edc_regs[i].per_se_instance)
++					continue;
++				if (instance_id >= gfx_ras_edc_regs[i].num_instance)
++					continue;
++
++				gfx_v9_0_select_se_sh(adev, se_id, 0,
++						      instance_id);
++
++				reg_value = RREG32(
++					adev->reg_offset[gfx_ras_edc_regs[i].ip]
++							[gfx_ras_edc_regs[i].inst]
++							[gfx_ras_edc_regs[i].seg] +
++					gfx_ras_edc_regs[i].reg_offset);
++				sec_count = reg_value &
++					    gfx_ras_edc_regs[i].sec_count_mask;
++				ded_count = reg_value &
++					    gfx_ras_edc_regs[i].ded_count_mask;
++				if (sec_count) {
++					DRM_INFO(
++						"Instance[%d][%d]: SubBlock %s, SEC %d\n",
++						se_id, instance_id,
++						gfx_ras_edc_regs[i].name,
++						sec_count);
++					err_data->ce_count++;
++				}
++
++				if (ded_count) {
++					DRM_INFO(
++						"Instance[%d][%d]: SubBlock %s, DED %d\n",
++						se_id, instance_id,
++						gfx_ras_edc_regs[i].name,
++						ded_count);
++					err_data->ue_count++;
++				}
++			}
++		}
++	}
++	gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
++	mutex_unlock(&adev->grbm_idx_mutex);
++
++	return 0;
++}
++
+ static int gfx_v9_0_cp_ecc_error_irq(struct amdgpu_device *adev,
+ 				  struct amdgpu_irq_src *source,
+ 				  struct amdgpu_iv_entry *entry)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3219-drm-amdgpu-support-gfx-ras-error-injection-and-err_c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3219-drm-amdgpu-support-gfx-ras-error-injection-and-err_c.patch
new file mode 100644
index 00000000..0a7587a8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3219-drm-amdgpu-support-gfx-ras-error-injection-and-err_c.patch
@@ -0,0 +1,77 @@
+From 8481e79de033e64e283b0346ea346db86ceb6c19 Mon Sep 17 00:00:00 2001
+From: Dennis Li <Dennis.Li@amd.com>
+Date: Wed, 31 Jul 2019 20:45:50 +0800
+Subject: [PATCH 3219/4256] drm/amdgpu: support gfx ras error injection and
+ err_cnt query
+
+check gfx error count in both ras querry function and
+ras interrupt handler.
+
+gfx ras is still disabled by default due to known stability
+issue found in gpu reset.
+
+Signed-off-by: Dennis Li <Dennis.Li@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 19 ++++++++++++++++---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   |  2 ++
+ 2 files changed, 18 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index ccd5863bca88..a96b0f17c619 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -600,6 +600,10 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev,
+ 		if (adev->umc.funcs->query_ras_error_count)
+ 			adev->umc.funcs->query_ras_error_count(adev, &err_data);
+ 		break;
++	case AMDGPU_RAS_BLOCK__GFX:
++		if (adev->gfx.funcs->query_ras_error_count)
++			adev->gfx.funcs->query_ras_error_count(adev, &err_data);
++		break;
+ 	default:
+ 		break;
+ 	}
+@@ -637,13 +641,22 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev,
+ 	if (!obj)
+ 		return -EINVAL;
+ 
+-	if (block_info.block_id != TA_RAS_BLOCK__UMC) {
++	switch (info->head.block) {
++	case AMDGPU_RAS_BLOCK__GFX:
++		if (adev->gfx.funcs->ras_error_inject)
++			ret = adev->gfx.funcs->ras_error_inject(adev, info);
++		else
++			ret = -EINVAL;
++		break;
++	case AMDGPU_RAS_BLOCK__UMC:
++		ret = psp_ras_trigger_error(&adev->psp, &block_info);
++		break;
++	default:
+ 		DRM_INFO("%s error injection is not supported yet\n",
+ 			 ras_block_str(info->head.block));
+-		return -EINVAL;
++		ret = -EINVAL;
+ 	}
+ 
+-	ret = psp_ras_trigger_error(&adev->psp, &block_info);
+ 	if (ret)
+ 		DRM_ERROR("RAS ERROR: inject %s error failed ret %d\n",
+ 				ras_block_str(info->head.block),
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 371abcdccb32..738eb477f775 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -5618,6 +5618,8 @@ static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+ {
+ 	/* TODO ue will trigger an interrupt. */
+ 	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
++	if (adev->gfx.funcs->query_ras_error_count)
++		adev->gfx.funcs->query_ras_error_count(adev, err_data);
+ 	amdgpu_ras_reset_gpu(adev, 0);
+ 	return AMDGPU_RAS_UE;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3220-drm-amdgpu-disable-inject-for-failed-subblocks-of-gf.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3220-drm-amdgpu-disable-inject-for-failed-subblocks-of-gf.patch
new file mode 100644
index 00000000..f71f2519
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3220-drm-amdgpu-disable-inject-for-failed-subblocks-of-gf.patch
@@ -0,0 +1,328 @@
+From 407c0bcc7d93e81182e2ef1ba96abc11e6fd3bf3 Mon Sep 17 00:00:00 2001
+From: Dennis Li <Dennis.Li@amd.com>
+Date: Tue, 23 Jul 2019 18:23:44 +0800
+Subject: [PATCH 3220/4256] drm/amdgpu: disable inject for failed subblocks of
+ gfx
+
+some subblocks of gfx fail in inject test, disable them
+
+Change-Id: I54176e291cf5d58a94838ec688a96289c6cebb46
+Signed-off-by: Dennis Li <Dennis.Li@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 281 +++++++++++++++-----------
+ 1 file changed, 165 insertions(+), 116 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 738eb477f775..baccfc8f624c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -322,129 +322,166 @@ enum ta_ras_gfx_subblock {
+ struct ras_gfx_subblock {
+ 	unsigned char *name;
+ 	int ta_subblock;
+-	int supported_error_type;
++	int hw_supported_error_type;
++	int sw_supported_error_type;
+ };
+ 
+-#define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d)                             \
++#define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h)                             \
+ 	[AMDGPU_RAS_BLOCK__##subblock] = {                                     \
+ 		#subblock,                                                     \
+ 		TA_RAS_BLOCK__##subblock,                                      \
+ 		((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)),                  \
++		(((e) << 1) | ((f) << 3) | (g) | ((h) << 2)),                  \
+ 	}
+ 
+ static const struct ras_gfx_subblock ras_gfx_subblocks[] = {
+-	AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1),
+-	AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1),
+-	AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
++			     0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
++			     0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
++			     0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,
++			     1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,
++			     0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,
++			     0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,
++			     0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,
++			     0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0,
++			     1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0,
++			     1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0,
++			     1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0,
++			     0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0,
++			     0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0),
++	AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0),
+ };
+ 
+ static const struct soc15_reg_golden golden_settings_gc_9_0[] =
+@@ -5934,9 +5971,21 @@ static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
+ 	if (!ras_gfx_subblocks[info->head.sub_block_index].name)
+ 		return -EPERM;
+ 
+-	if (!(ras_gfx_subblocks[info->head.sub_block_index].supported_error_type &
+-	      info->head.type))
++	if (!(ras_gfx_subblocks[info->head.sub_block_index].hw_supported_error_type &
++	      info->head.type)) {
++		DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n",
++			ras_gfx_subblocks[info->head.sub_block_index].name,
++			info->head.type);
+ 		return -EPERM;
++	}
++
++	if (!(ras_gfx_subblocks[info->head.sub_block_index].sw_supported_error_type &
++	      info->head.type)) {
++		DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n",
++			ras_gfx_subblocks[info->head.sub_block_index].name,
++			info->head.type);
++		return -EPERM;
++	}
+ 
+ 	block_info.block_id = amdgpu_ras_block_to_ta(info->head.block);
+ 	block_info.sub_block_index =
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3221-drm-amdkfd-enable-KFD-support-for-navi14.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3221-drm-amdkfd-enable-KFD-support-for-navi14.patch
new file mode 100644
index 00000000..1b26da1b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3221-drm-amdkfd-enable-KFD-support-for-navi14.patch
@@ -0,0 +1,28 @@
+From d0182fa5fcc200949cce1627e0bdf71217d9e7cc Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 26 Jul 2019 14:15:12 -0500
+Subject: [PATCH 3221/4256] drm/amdkfd: enable KFD support for navi14
+
+Same as navi10.
+
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+index 859763c7f419..bb2374842b82 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+@@ -97,6 +97,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
+ 	case CHIP_ARCTURUS:
+ 		kfd2kgd = amdgpu_amdkfd_arcturus_get_functions();
+ 	case CHIP_NAVI10:
++	case CHIP_NAVI14:
+ 		kfd2kgd = amdgpu_amdkfd_gfx_10_0_get_functions();
+ 		break;
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3222-drm-amd-powerplay-sort-feature-status-index-by-asic-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3222-drm-amd-powerplay-sort-feature-status-index-by-asic-.patch
new file mode 100644
index 00000000..d705e9da
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3222-drm-amd-powerplay-sort-feature-status-index-by-asic-.patch
@@ -0,0 +1,90 @@
+From a33b06f3307dcacddf6d594160055314c3e061a7 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Wed, 31 Jul 2019 15:37:07 +0800
+Subject: [PATCH 3222/4256] drm/amd/powerplay: sort feature status index by
+ asic feature id for smu
+
+before this change, the pp_feature sysfs show feature enable state by
+logic feature id, it is not easy to read.
+this change will sort pp_features show index by asic feature id.
+
+before:
+features high: 0x00000623 low: 0xb3cdaffb
+00. DPM_PREFETCHER       ( 0) : enabeld
+01. DPM_GFXCLK           ( 1) : enabeld
+02. DPM_UCLK             ( 3) : enabeld
+03. DPM_SOCCLK           ( 4) : enabeld
+04. DPM_MP0CLK           ( 5) : enabeld
+05. DPM_LINK             ( 6) : enabeld
+06. DPM_DCEFCLK          ( 7) : enabeld
+07. DS_GFXCLK            (10) : enabeld
+08. DS_SOCCLK            (11) : enabeld
+09. DS_LCLK              (12) : disabled
+10. PPT                  (23) : enabeld
+11. TDC                  (24) : enabeld
+12. THERMAL              (33) : enabeld
+13. RM                   (35) : disabled
+......
+
+after:
+features high: 0x00000623 low: 0xb3cdaffb
+00. DPM_PREFETCHER       ( 0) : enabeld
+01. DPM_GFXCLK           ( 1) : enabeld
+02. DPM_GFX_PACE         ( 2) : disabled
+03. DPM_UCLK             ( 3) : enabeld
+04. DPM_SOCCLK           ( 4) : enabeld
+05. DPM_MP0CLK           ( 5) : enabeld
+06. DPM_LINK             ( 6) : enabeld
+07. DPM_DCEFCLK          ( 7) : enabeld
+08. MEM_VDDCI_SCALING    ( 8) : enabeld
+09. MEM_MVDD_SCALING     ( 9) : enabeld
+10. DS_GFXCLK            (10) : enabeld
+11. DS_SOCCLK            (11) : enabeld
+12. DS_LCLK              (12) : disabled
+13. DS_DCEFCLK           (13) : enabeld
+......
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 14 +++++++++++---
+ 1 file changed, 11 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 330cc3258e61..8641b3a8f81e 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -63,6 +63,8 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
+ 	uint32_t feature_mask[2] = { 0 };
+ 	int32_t feature_index = 0;
+ 	uint32_t count = 0;
++	uint32_t sort_feature[SMU_FEATURE_COUNT];
++	uint64_t hw_feature_count = 0;
+ 
+ 	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+ 	if (ret)
+@@ -75,11 +77,17 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
+ 		feature_index = smu_feature_get_index(smu, i);
+ 		if (feature_index < 0)
+ 			continue;
++		sort_feature[feature_index] = i;
++		hw_feature_count++;
++	}
++
++	for (i = 0; i < hw_feature_count; i++) {
+ 		size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
+ 			       count++,
+-			       smu_get_feature_name(smu, i),
+-			       feature_index,
+-			       !!smu_feature_is_enabled(smu, i) ? "enabeld" : "disabled");
++			       smu_get_feature_name(smu, sort_feature[i]),
++			       i,
++			       !!smu_feature_is_enabled(smu, sort_feature[i]) ?
++			       "enabeld" : "disabled");
+ 	}
+ 
+ failed:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3223-drm-amdgpu-cleanup-vega10-SRIOV-code-path.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3223-drm-amdgpu-cleanup-vega10-SRIOV-code-path.patch
new file mode 100644
index 00000000..04395d5c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3223-drm-amdgpu-cleanup-vega10-SRIOV-code-path.patch
@@ -0,0 +1,442 @@
+From a9c3a46b977e371701962f0117242daeb01c8e3a Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Tue, 30 Jul 2019 17:21:19 +0800
+Subject: [PATCH 3223/4256] drm/amdgpu: cleanup vega10 SRIOV code path
+
+we can simplify all those unnecessary function under
+SRIOV for vega10 since:
+1) PSP L1 policy is by force enabled in SRIOV
+2) original logic always set all flags which make itself
+   a dummy step
+
+besides,
+1) the ih_doorbell_range set should also be skipped
+for VEGA10 SRIOV.
+2) the gfx_common registers should also be skipped
+for VEGA10 SRIOV.
+
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+Reviewed-by: Emily Deng <Emily.Deng@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  3 --
+ drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c   | 45 ----------------------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h   | 13 -------
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c      | 17 ++++----
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c      |  2 +-
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c    | 10 ++---
+ drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c      | 15 --------
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c     | 17 ++++----
+ drivers/gpu/drm/amd/amdgpu/soc15.c         | 11 ++----
+ drivers/gpu/drm/amd/amdgpu/soc15_common.h  |  5 ++-
+ drivers/gpu/drm/amd/amdgpu/vega10_ih.c     | 18 ++++-----
+ 11 files changed, 38 insertions(+), 118 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 5e44ddeb21db..111d3fc175d8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1643,9 +1643,6 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
+ 		r = amdgpu_virt_request_full_gpu(adev, true);
+ 		if (r)
+ 			return -EAGAIN;
+-
+-		/* query the reg access mode at the very beginning */
+-		amdgpu_virt_init_reg_access_mode(adev);
+ 	}
+ 
+ 	adev->pm.pp_feature = amdgpu_pp_feature_mask;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+index 1d68729a9a6b..f04eb1a64271 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+@@ -426,48 +426,3 @@ uint32_t amdgpu_virt_get_mclk(struct amdgpu_device *adev, bool lowest)
+ 
+ 	return clk;
+ }
+-
+-void amdgpu_virt_init_reg_access_mode(struct amdgpu_device *adev)
+-{
+-	struct amdgpu_virt *virt = &adev->virt;
+-
+-	if (virt->ops && virt->ops->init_reg_access_mode)
+-		virt->ops->init_reg_access_mode(adev);
+-}
+-
+-bool amdgpu_virt_support_psp_prg_ih_reg(struct amdgpu_device *adev)
+-{
+-	bool ret = false;
+-	struct amdgpu_virt *virt = &adev->virt;
+-
+-	if (amdgpu_sriov_vf(adev)
+-		&& (virt->reg_access_mode & AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH))
+-		ret = true;
+-
+-	return ret;
+-}
+-
+-bool amdgpu_virt_support_rlc_prg_reg(struct amdgpu_device *adev)
+-{
+-	bool ret = false;
+-	struct amdgpu_virt *virt = &adev->virt;
+-
+-	if (amdgpu_sriov_vf(adev)
+-		&& (virt->reg_access_mode & AMDGPU_VIRT_REG_ACCESS_RLC)
+-		&& !(amdgpu_sriov_runtime(adev)))
+-		ret = true;
+-
+-	return ret;
+-}
+-
+-bool amdgpu_virt_support_skip_setting(struct amdgpu_device *adev)
+-{
+-	bool ret = false;
+-	struct amdgpu_virt *virt = &adev->virt;
+-
+-	if (amdgpu_sriov_vf(adev)
+-		&& (virt->reg_access_mode & AMDGPU_VIRT_REG_SKIP_SEETING))
+-		ret = true;
+-
+-	return ret;
+-}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+index f5107731e9c4..b0b2bdc750df 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+@@ -48,12 +48,6 @@ struct amdgpu_vf_error_buffer {
+ 	uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
+ };
+ 
+-/* According to the fw feature, some new reg access modes are supported */
+-#define AMDGPU_VIRT_REG_ACCESS_LEGACY          (1 << 0) /* directly mmio */
+-#define AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH      (1 << 1) /* by PSP */
+-#define AMDGPU_VIRT_REG_ACCESS_RLC             (1 << 2) /* by RLC */
+-#define AMDGPU_VIRT_REG_SKIP_SEETING           (1 << 3) /* Skip setting reg */
+-
+ /**
+  * struct amdgpu_virt_ops - amdgpu device virt operations
+  */
+@@ -65,7 +59,6 @@ struct amdgpu_virt_ops {
+ 	void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3);
+ 	int (*get_pp_clk)(struct amdgpu_device *adev, u32 type, char *buf);
+ 	int (*force_dpm_level)(struct amdgpu_device *adev, u32 level);
+-	void (*init_reg_access_mode)(struct amdgpu_device *adev);
+ };
+ 
+ /*
+@@ -315,10 +308,4 @@ int amdgpu_virt_fw_reserve_get_checksum(void *obj, unsigned long obj_size,
+ void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
+ uint32_t amdgpu_virt_get_sclk(struct amdgpu_device *adev, bool lowest);
+ uint32_t amdgpu_virt_get_mclk(struct amdgpu_device *adev, bool lowest);
+-
+-void amdgpu_virt_init_reg_access_mode(struct amdgpu_device *adev);
+-bool amdgpu_virt_support_psp_prg_ih_reg(struct amdgpu_device *adev);
+-bool amdgpu_virt_support_rlc_prg_reg(struct amdgpu_device *adev);
+-bool amdgpu_virt_support_skip_setting(struct amdgpu_device *adev);
+-
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index baccfc8f624c..1ba428d5c2e1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -711,14 +711,12 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
+ {
+ 	switch (adev->asic_type) {
+ 	case CHIP_VEGA10:
+-		if (!amdgpu_virt_support_skip_setting(adev)) {
+-			soc15_program_register_sequence(adev,
+-							 golden_settings_gc_9_0,
+-							 ARRAY_SIZE(golden_settings_gc_9_0));
+-			soc15_program_register_sequence(adev,
+-							 golden_settings_gc_9_0_vg10,
+-							 ARRAY_SIZE(golden_settings_gc_9_0_vg10));
+-		}
++		soc15_program_register_sequence(adev,
++						golden_settings_gc_9_0,
++						ARRAY_SIZE(golden_settings_gc_9_0));
++		soc15_program_register_sequence(adev,
++						golden_settings_gc_9_0_vg10,
++						ARRAY_SIZE(golden_settings_gc_9_0_vg10));
+ 		break;
+ 	case CHIP_VEGA12:
+ 		soc15_program_register_sequence(adev,
+@@ -3808,7 +3806,8 @@ static int gfx_v9_0_hw_init(void *handle)
+ 	int r;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
+-	gfx_v9_0_init_golden_registers(adev);
++	if (!amdgpu_sriov_vf(adev))
++		gfx_v9_0_init_golden_registers(adev);
+ 
+ 	gfx_v9_0_constants_init(adev);
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 76769e35a774..7f4da9254dfb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -1194,7 +1194,7 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_VEGA10:
+-		if (amdgpu_virt_support_skip_setting(adev))
++		if (amdgpu_sriov_vf(adev))
+ 			break;
+ 		/* fall through */
+ 	case CHIP_VEGA20:
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index e3fc03b6a618..df0117df45a9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -111,7 +111,7 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
+                 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+ 				max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
+ 
+-	if (amdgpu_virt_support_skip_setting(adev))
++	if (amdgpu_sriov_vf(adev))
+ 		return;
+ 
+ 	/* Set default page address. */
+@@ -159,7 +159,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
+ {
+ 	uint32_t tmp;
+ 
+-	if (amdgpu_virt_support_skip_setting(adev))
++	if (amdgpu_sriov_vf(adev))
+ 		return;
+ 
+ 	/* Setup L2 cache */
+@@ -208,7 +208,7 @@ static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
+ 
+ static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
+ {
+-	if (amdgpu_virt_support_skip_setting(adev))
++	if (amdgpu_sriov_vf(adev))
+ 		return;
+ 
+ 	WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
+@@ -348,7 +348,7 @@ void mmhub_v1_0_gart_disable(struct amdgpu_device *adev)
+ 				0);
+ 	WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
+ 
+-	if (!amdgpu_virt_support_skip_setting(adev)) {
++	if (!amdgpu_sriov_vf(adev)) {
+ 		/* Setup L2 cache */
+ 		tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
+ 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
+@@ -367,7 +367,7 @@ void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
+ {
+ 	u32 tmp;
+ 
+-	if (amdgpu_virt_support_skip_setting(adev))
++	if (amdgpu_sriov_vf(adev))
+ 		return;
+ 
+ 	tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
+diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+index 235548c0b41f..cc5bf595f9b1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
++++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+@@ -449,20 +449,6 @@ void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev)
+ 	amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
+ }
+ 
+-static void xgpu_ai_init_reg_access_mode(struct amdgpu_device *adev)
+-{
+-	adev->virt.reg_access_mode = AMDGPU_VIRT_REG_ACCESS_LEGACY;
+-
+-	/* Enable L1 security reg access mode by defaul,  as non-security VF
+-	 * will no longer be supported.
+-	 */
+-	adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_RLC;
+-
+-	adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH;
+-
+-	adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_SKIP_SEETING;
+-}
+-
+ const struct amdgpu_virt_ops xgpu_ai_virt_ops = {
+ 	.req_full_gpu	= xgpu_ai_request_full_gpu_access,
+ 	.rel_full_gpu	= xgpu_ai_release_full_gpu_access,
+@@ -471,5 +457,4 @@ const struct amdgpu_virt_ops xgpu_ai_virt_ops = {
+ 	.trans_msg = xgpu_ai_mailbox_trans_msg,
+ 	.get_pp_clk = xgpu_ai_get_pp_clk,
+ 	.force_dpm_level = xgpu_ai_force_dpm_level,
+-	.init_reg_access_mode = xgpu_ai_init_reg_access_mode,
+ };
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index bf9365c6e9b7..93cd0a64eca0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -327,14 +327,12 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
+ {
+ 	switch (adev->asic_type) {
+ 	case CHIP_VEGA10:
+-		if (!amdgpu_virt_support_skip_setting(adev)) {
+-			soc15_program_register_sequence(adev,
+-							 golden_settings_sdma_4,
+-							 ARRAY_SIZE(golden_settings_sdma_4));
+-			soc15_program_register_sequence(adev,
+-							 golden_settings_sdma_vg10,
+-							 ARRAY_SIZE(golden_settings_sdma_vg10));
+-		}
++		soc15_program_register_sequence(adev,
++						golden_settings_sdma_4,
++						ARRAY_SIZE(golden_settings_sdma_4));
++		soc15_program_register_sequence(adev,
++						golden_settings_sdma_vg10,
++						ARRAY_SIZE(golden_settings_sdma_vg10));
+ 		break;
+ 	case CHIP_VEGA12:
+ 		soc15_program_register_sequence(adev,
+@@ -1832,7 +1830,8 @@ static int sdma_v4_0_hw_init(void *handle)
+ 			adev->powerplay.pp_funcs->set_powergating_by_smu)
+ 		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
+ 
+-	sdma_v4_0_init_golden_registers(adev);
++	if (!amdgpu_sriov_vf(adev))
++		sdma_v4_0_init_golden_registers(adev);
+ 
+ 	r = sdma_v4_0_start(adev);
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 214fc9d880e5..dc553978d23a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1122,21 +1122,18 @@ static void soc15_doorbell_range_init(struct amdgpu_device *adev)
+ 	int i;
+ 	struct amdgpu_ring *ring;
+ 
+-	/*  Two reasons to skip
+-	*		1, Host driver already programmed them
+-	*		2, To avoid registers program violations in SR-IOV
+-	*/
+-	if (!amdgpu_virt_support_skip_setting(adev)) {
++	/* sdma/ih doorbell range are programed by hypervisor */
++	if (!amdgpu_sriov_vf(adev)) {
+ 		for (i = 0; i < adev->sdma.num_instances; i++) {
+ 			ring = &adev->sdma.instance[i].ring;
+ 			adev->nbio_funcs->sdma_doorbell_range(adev, i,
+ 				ring->use_doorbell, ring->doorbell_index,
+ 				adev->doorbell_index.sdma_doorbell_range);
+ 		}
+-	}
+ 
+-	adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
++		adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
+ 						adev->irq.ih.doorbell_index);
++	}
+ }
+ 
+ static int soc15_common_hw_init(void *handle)
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+index 47f74dab365d..839f186e1182 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
++++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+@@ -69,9 +69,10 @@
+ 		}						\
+ 	} while (0)
+ 
++#define AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(a) (amdgpu_sriov_vf((a)) && !amdgpu_sriov_runtime((a)))
+ #define WREG32_RLC(reg, value) \
+ 	do {							\
+-		if (amdgpu_virt_support_rlc_prg_reg(adev)) {    \
++		if (AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(adev)) {    \
+ 			uint32_t i = 0;	\
+ 			uint32_t retries = 50000;	\
+ 			uint32_t r0 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0;	\
+@@ -96,7 +97,7 @@
+ #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \
+ 	do {							\
+ 		uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
+-		if (amdgpu_virt_support_rlc_prg_reg(adev)) {    \
++		if (AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(adev)) {    \
+ 			uint32_t r2 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2;	\
+ 			uint32_t r3 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3;	\
+ 			uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;   \
+diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+index ee9cd8579038..a55525abb73c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
++++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+@@ -48,7 +48,7 @@ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
+ 
+ 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
+ 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
+-	if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
++	if (amdgpu_sriov_vf(adev)) {
+ 		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
+ 			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+ 			return;
+@@ -62,7 +62,7 @@ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
+ 		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+ 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
+ 					   RB_ENABLE, 1);
+-		if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
++		if (amdgpu_sriov_vf(adev)) {
+ 			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
+ 						ih_rb_cntl)) {
+ 				DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
+@@ -78,7 +78,7 @@ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
+ 		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
+ 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
+ 					   RB_ENABLE, 1);
+-		if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
++		if (amdgpu_sriov_vf(adev)) {
+ 			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
+ 						ih_rb_cntl)) {
+ 				DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
+@@ -104,7 +104,7 @@ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
+ 
+ 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
+ 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
+-	if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
++	if (amdgpu_sriov_vf(adev)) {
+ 		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
+ 			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+ 			return;
+@@ -123,7 +123,7 @@ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
+ 		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+ 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
+ 					   RB_ENABLE, 0);
+-		if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
++		if (amdgpu_sriov_vf(adev)) {
+ 			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
+ 						ih_rb_cntl)) {
+ 				DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
+@@ -143,7 +143,7 @@ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
+ 		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
+ 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
+ 					   RB_ENABLE, 0);
+-		if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
++		if (amdgpu_sriov_vf(adev)) {
+ 			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
+ 						ih_rb_cntl)) {
+ 				DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
+@@ -236,7 +236,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
+ 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM,
+ 				   !!adev->irq.msi_enabled);
+ 
+-	if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
++	if (amdgpu_sriov_vf(adev)) {
+ 		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
+ 			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+ 			return -ETIMEDOUT;
+@@ -279,7 +279,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
+ 					   WPTR_OVERFLOW_ENABLE, 0);
+ 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+ 					   RB_FULL_DRAIN_ENABLE, 1);
+-		if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
++		if (amdgpu_sriov_vf(adev)) {
+ 			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
+ 						ih_rb_cntl)) {
+ 				DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
+@@ -306,7 +306,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
+ 		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
+ 		ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
+ 
+-		if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
++		if (amdgpu_sriov_vf(adev)) {
+ 			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
+ 						ih_rb_cntl)) {
+ 				DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3224-drm-amdgpu-fix-incorrect-judge-on-sos-fw-version.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3224-drm-amdgpu-fix-incorrect-judge-on-sos-fw-version.patch
new file mode 100644
index 00000000..04d0f5e4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3224-drm-amdgpu-fix-incorrect-judge-on-sos-fw-version.patch
@@ -0,0 +1,31 @@
+From 7d0c21aa7553c1e6901d2b401ab6f79db3ac15d3 Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Tue, 30 Jul 2019 17:32:27 +0800
+Subject: [PATCH 3224/4256] drm/amdgpu: fix incorrect judge on sos fw version
+
+for SRIOV the SOS fw of PSP is loaded in hypervisor thus
+guest won't tell the version of it, and judging feature by
+reading the sos fw version in guest side is completely wrong
+
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+Reviewed-by: Emily Deng <Emily.Deng@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+index ec3a05602f11..ba327581f301 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+@@ -634,7 +634,7 @@ static int psp_v3_1_mode1_reset(struct psp_context *psp)
+ 
+ static bool psp_v3_1_support_vmr_ring(struct psp_context *psp)
+ {
+-	if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version >= 0x80455)
++	if (amdgpu_sriov_vf(psp->adev))
+ 		return true;
+ 
+ 	return false;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3225-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3225-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch
new file mode 100644
index 00000000..34ba31f3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3225-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch
@@ -0,0 +1,183 @@
+From dfeb69f03e80ff120ec8d59b4a05e4593538a1c4 Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Wed, 31 Jul 2019 16:47:56 +0800
+Subject: [PATCH 3225/4256] drm/amdgpu: fix double ucode load by PSP(v3)
+
+previously the ucode loading of PSP was repreated, one executed in
+phase_1 init/re-init/resume and the other in fw_loading routine
+
+Avoid this double loading by clearing ip_blocks.status.hw in suspend or reset
+prior to the FW loading and any block's hw_init/resume
+
+v2:
+still do the smu fw loading since it is needed by bare-metal
+
+v3:
+drop the change in reinit_early_sriov, just clear all block's status.hw
+in the head place and set the status.hw after hw_init done is enough
+
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+Reviewed-by: Emily Deng <Emily.Deng@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 59 ++++++++++++++--------
+ 1 file changed, 38 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 111d3fc175d8..87179dd882d0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1745,28 +1745,34 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
+ 
+ 	if (adev->asic_type >= CHIP_VEGA10) {
+ 		for (i = 0; i < adev->num_ip_blocks; i++) {
+-			if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
+-				if (adev->in_gpu_reset || adev->in_suspend) {
+-					if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset)
+-						break; /* sriov gpu reset, psp need to do hw_init before IH because of hw limit */
+-					r = adev->ip_blocks[i].version->funcs->resume(adev);
+-					if (r) {
+-						DRM_ERROR("resume of IP block <%s> failed %d\n",
++			if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
++				continue;
++
++			/* no need to do the fw loading again if already done*/
++			if (adev->ip_blocks[i].status.hw == true)
++				break;
++
++			if (adev->in_gpu_reset || adev->in_suspend) {
++				r = adev->ip_blocks[i].version->funcs->resume(adev);
++				if (r) {
++					DRM_ERROR("resume of IP block <%s> failed %d\n",
+ 							  adev->ip_blocks[i].version->funcs->name, r);
+-						return r;
+-					}
+-				} else {
+-					r = adev->ip_blocks[i].version->funcs->hw_init(adev);
+-					if (r) {
+-						DRM_ERROR("hw_init of IP block <%s> failed %d\n",
+-						  adev->ip_blocks[i].version->funcs->name, r);
+-						return r;
+-					}
++					return r;
++				}
++			} else {
++				r = adev->ip_blocks[i].version->funcs->hw_init(adev);
++				if (r) {
++					DRM_ERROR("hw_init of IP block <%s> failed %d\n",
++							  adev->ip_blocks[i].version->funcs->name, r);
++					return r;
+ 				}
+-				adev->ip_blocks[i].status.hw = true;
+ 			}
++
++			adev->ip_blocks[i].status.hw = true;
++			break;
+ 		}
+ 	}
++
+ 	r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
+ 
+ 	return r;
+@@ -2200,7 +2206,9 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
+ 			if (r) {
+ 				DRM_ERROR("suspend of IP block <%s> failed %d\n",
+ 					  adev->ip_blocks[i].version->funcs->name, r);
++				return r;
+ 			}
++			adev->ip_blocks[i].status.hw = false;
+ 		}
+ 	}
+ 
+@@ -2240,14 +2248,16 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
+ 			if (is_support_sw_smu(adev)) {
+ 				/* todo */
+ 			} else if (adev->powerplay.pp_funcs &&
+-				   adev->powerplay.pp_funcs->set_mp1_state) {
++					   adev->powerplay.pp_funcs->set_mp1_state) {
+ 				r = adev->powerplay.pp_funcs->set_mp1_state(
+ 					adev->powerplay.pp_handle,
+ 					adev->mp1_state);
+ 				if (r) {
+ 					DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
+ 						  adev->mp1_state, r);
++					return r;
+ 				}
++				adev->ip_blocks[i].status.hw = false;
+ 			}
+ 		}
+ 	}
+@@ -2302,6 +2312,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
+ 		for (j = 0; j < adev->num_ip_blocks; j++) {
+ 			block = &adev->ip_blocks[j];
+ 
++			block->status.hw = false;
+ 			if (block->version->type != ip_order[i] ||
+ 				!block->status.valid)
+ 				continue;
+@@ -2310,6 +2321,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
+ 			DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
+ 			if (r)
+ 				return r;
++			block->status.hw = true;
+ 		}
+ 	}
+ 
+@@ -2337,13 +2349,15 @@ static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
+ 			block = &adev->ip_blocks[j];
+ 
+ 			if (block->version->type != ip_order[i] ||
+-				!block->status.valid)
++				!block->status.valid ||
++				block->status.hw)
+ 				continue;
+ 
+ 			r = block->version->funcs->hw_init(adev);
+ 			DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
+ 			if (r)
+ 				return r;
++			block->status.hw = true;
+ 		}
+ 	}
+ 
+@@ -2367,17 +2381,19 @@ static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
+ 	int i, r;
+ 
+ 	for (i = 0; i < adev->num_ip_blocks; i++) {
+-		if (!adev->ip_blocks[i].status.valid)
++		if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
+ 			continue;
+ 		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
+ 		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
+ 		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
++
+ 			r = adev->ip_blocks[i].version->funcs->resume(adev);
+ 			if (r) {
+ 				DRM_ERROR("resume of IP block <%s> failed %d\n",
+ 					  adev->ip_blocks[i].version->funcs->name, r);
+ 				return r;
+ 			}
++			adev->ip_blocks[i].status.hw = true;
+ 		}
+ 	}
+ 
+@@ -2402,7 +2418,7 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
+ 	int i, r;
+ 
+ 	for (i = 0; i < adev->num_ip_blocks; i++) {
+-		if (!adev->ip_blocks[i].status.valid)
++		if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
+ 			continue;
+ 		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
+ 		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
+@@ -2415,6 +2431,7 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
+ 				  adev->ip_blocks[i].version->funcs->name, r);
+ 			return r;
+ 		}
++		adev->ip_blocks[i].status.hw = true;
+ 	}
+ 
+ 	return 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3226-drm-amd-display-Use-proper-enum-conversion-functions.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3226-drm-amd-display-Use-proper-enum-conversion-functions.patch
new file mode 100644
index 00000000..eaa55b3a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3226-drm-amd-display-Use-proper-enum-conversion-functions.patch
@@ -0,0 +1,58 @@
+From 061f19554ca0a9d320fa4826f8f10954d29c85e0 Mon Sep 17 00:00:00 2001
+From: Nathan Chancellor <natechancellor@gmail.com>
+Date: Wed, 3 Jul 2019 22:52:16 -0700
+Subject: [PATCH 3226/4256] drm/amd/display: Use proper enum conversion
+ functions
+
+clang warns:
+
+drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.c:336:8:
+warning: implicit conversion from enumeration type 'enum smu_clk_type'
+to different enumeration type 'enum amd_pp_clock_type'
+[-Wenum-conversion]
+                                        dc_to_smu_clock_type(clk_type),
+                                        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.c:421:14:
+warning: implicit conversion from enumeration type 'enum
+amd_pp_clock_type' to different enumeration type 'enum smu_clk_type'
+[-Wenum-conversion]
+                                        dc_to_pp_clock_type(clk_type),
+                                        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+There are functions to properly convert between all of these types, use
+them so there are no longer any warnings.
+
+Fixes: a43913ea50a5 ("drm/amd/powerplay: add function get_clock_by_type_with_latency for navi10")
+Fixes: e5e4e22391c2 ("drm/amd/powerplay: add interface to get clock by type with latency for display (v2)")
+Link: https://github.com/ClangBuiltLinux/linux/issues/586
+Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
+Reviewed-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+index 583f8fbb9027..c25246fad42f 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+@@ -335,7 +335,7 @@ bool dm_pp_get_clock_levels_by_type(
+ 		}
+ 	} else if (adev->smu.funcs && adev->smu.funcs->get_clock_by_type) {
+ 		if (smu_get_clock_by_type(&adev->smu,
+-					  dc_to_smu_clock_type(clk_type),
++					  dc_to_pp_clock_type(clk_type),
+ 					  &pp_clks)) {
+ 			get_default_clock_levels(clk_type, dc_clks);
+ 			return true;
+@@ -420,7 +420,7 @@ bool dm_pp_get_clock_levels_by_type_with_latency(
+ 			return false;
+ 	} else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type_with_latency) {
+ 		if (smu_get_clock_by_type_with_latency(&adev->smu,
+-						       dc_to_pp_clock_type(clk_type),
++						       dc_to_smu_clock_type(clk_type),
+ 						       &pp_clks))
+ 			return false;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3227-drm-amd-display-Use-switch-table-for-dc_to_smu_clock.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3227-drm-amd-display-Use-switch-table-for-dc_to_smu_clock.patch
new file mode 100644
index 00000000..7669c0c8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3227-drm-amd-display-Use-switch-table-for-dc_to_smu_clock.patch
@@ -0,0 +1,70 @@
+From 0ddef51f75858ad44b45e59c78f02c85eb9bf410 Mon Sep 17 00:00:00 2001
+From: Leo Li <sunpeng.li@amd.com>
+Date: Thu, 25 Jul 2019 13:12:24 -0400
+Subject: [PATCH 3227/4256] drm/amd/display: Use switch table for
+ dc_to_smu_clock_type
+
+Using a static int array will cause errors if the given dm_pp_clk_type
+is out-of-bounds. For robustness, use a switch table, with a default
+case to handle all invalid values.
+
+v2: 0 is a valid clock type for smu_clk_type. Return SMU_CLK_COUNT
+    instead on invalid mapping.
+
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c  | 37 +++++++++++++------
+ 1 file changed, 25 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+index c25246fad42f..9b2ce0264df6 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+@@ -152,18 +152,31 @@ static void get_default_clock_levels(
+ static enum smu_clk_type dc_to_smu_clock_type(
+ 		enum dm_pp_clock_type dm_pp_clk_type)
+ {
+-#define DCCLK_MAP_SMUCLK(dcclk, smuclk) \
+-	[dcclk] = smuclk
+-
+-	static int dc_clk_type_map[] = {
+-		DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_DISPLAY_CLK,	SMU_DISPCLK),
+-		DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_ENGINE_CLK,	SMU_GFXCLK),
+-		DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_MEMORY_CLK,	SMU_MCLK),
+-		DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_DCEFCLK,	SMU_DCEFCLK),
+-		DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_SOCCLK,	SMU_SOCCLK),
+-	};
+-
+-	return dc_clk_type_map[dm_pp_clk_type];
++	enum smu_clk_type smu_clk_type = SMU_CLK_COUNT;
++
++	switch (dm_pp_clk_type) {
++	case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
++		smu_clk_type = SMU_DISPCLK;
++		break;
++	case DM_PP_CLOCK_TYPE_ENGINE_CLK:
++		smu_clk_type = SMU_GFXCLK;
++		break;
++	case DM_PP_CLOCK_TYPE_MEMORY_CLK:
++		smu_clk_type = SMU_MCLK;
++		break;
++	case DM_PP_CLOCK_TYPE_DCEFCLK:
++		smu_clk_type = SMU_DCEFCLK;
++		break;
++	case DM_PP_CLOCK_TYPE_SOCCLK:
++		smu_clk_type = SMU_SOCCLK;
++		break;
++	default:
++		DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
++			  dm_pp_clk_type);
++		break;
++	}
++
++	return smu_clk_type;
+ }
+ 
+ static enum amd_pp_clock_type dc_to_pp_clock_type(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3228-drm-ttm-Add-release_notify-callback-to-ttm_bo_driver.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3228-drm-ttm-Add-release_notify-callback-to-ttm_bo_driver.patch
new file mode 100644
index 00000000..5d5c14f1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3228-drm-ttm-Add-release_notify-callback-to-ttm_bo_driver.patch
@@ -0,0 +1,68 @@
+From 4c54c6afe906f0f39ea8a677623f621a81d0eae6 Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Tue, 9 Jul 2019 19:09:42 -0400
+Subject: [PATCH 3228/4256] drm/ttm: Add release_notify callback to
+ ttm_bo_driver
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This notifies the driver that a BO is about to be released.
+
+Releasing a BO also invokes the move_notify callback from
+ttm_bo_cleanup_memtype_use, but that happens too late for anything
+that would add fences to the BO and require a delayed delete.
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/ttm/ttm_bo.c    |  3 +++
+ include/drm/ttm/ttm_bo_driver.h | 18 ++++++++++++++++++
+ 2 files changed, 21 insertions(+)
+
+diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
+index 5692eb0ce888..19fe14514e4c 100644
+--- a/drivers/gpu/drm/ttm/ttm_bo.c
++++ b/drivers/gpu/drm/ttm/ttm_bo.c
+@@ -668,6 +668,9 @@ static void ttm_bo_release(struct kref *kref)
+ 	struct ttm_bo_device *bdev = bo->bdev;
+ 	struct ttm_mem_type_manager *man = &bdev->man[bo->mem.mem_type];
+ 
++	if (bo->bdev->driver->release_notify)
++		bo->bdev->driver->release_notify(bo);
++
+ 	drm_vma_offset_remove(&bdev->vma_manager, &bo->vma_node);
+ 	ttm_mem_io_lock(man, false);
+ 	ttm_mem_io_free_vm(bo);
+diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
+index 6652c155902d..27782b3c44a6 100644
+--- a/include/drm/ttm/ttm_bo_driver.h
++++ b/include/drm/ttm/ttm_bo_driver.h
+@@ -384,6 +384,24 @@ struct ttm_bo_driver {
+ 	 */
+ 	int (*access_memory)(struct ttm_buffer_object *bo, unsigned long offset,
+ 			     void *buf, int len, int write);
++	/**
++         * struct ttm_bo_driver member del_from_lru_notify
++         *
++         * @bo: the buffer object deleted from lru
++         *
++         * notify driver that a BO was deleted from LRU.
++         */
++        void (*del_from_lru_notify)(struct ttm_buffer_object *bo);
++
++        /**
++         * Notify the driver that we're about to release a BO
++         *
++         * @bo: BO that is about to be released
++         *
++         * Gives the driver a chance to do any cleanup, including
++         * adding fences that may force a delayed delete
++         */
++        void (*release_notify)(struct ttm_buffer_object *bo);
+ };
+ 
+ /**
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3229-drm-amdgpu-Add-flag-to-wipe-VRAM-on-release.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3229-drm-amdgpu-Add-flag-to-wipe-VRAM-on-release.patch
new file mode 100644
index 00000000..f63b153d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3229-drm-amdgpu-Add-flag-to-wipe-VRAM-on-release.patch
@@ -0,0 +1,35 @@
+From 0dc3d43ed7e0ec05f2fcda64d9b7ffeb53aa6024 Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Mon, 8 Jul 2019 20:09:21 -0400
+Subject: [PATCH 3229/4256] drm/amdgpu: Add flag to wipe VRAM on release
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This memory allocation flag will be used to indicate BOs containing
+sensitive data that should not be leaked to other processes.
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ include/uapi/drm/amdgpu_drm.h | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
+index 66b00e41fbcd..6944be414ee0 100644
+--- a/include/uapi/drm/amdgpu_drm.h
++++ b/include/uapi/drm/amdgpu_drm.h
+@@ -142,6 +142,10 @@ extern "C" {
+  * for the second page onward should be set to NC.
+  */
+ #define AMDGPU_GEM_CREATE_MQD_GFX9		(1 << 8)
++/* Flag that BO may contain sensitive data that must be wiped before
++ * releasing the memory
++ */
++#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE	(1 << 9)
+ 
+ /* hybrid specific */
+ /* Flag that the memory allocation should be from top of domain */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3230-drm-amdgpu-Implement-VRAM-wipe-on-release.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3230-drm-amdgpu-Implement-VRAM-wipe-on-release.patch
new file mode 100644
index 00000000..f8c93779
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3230-drm-amdgpu-Implement-VRAM-wipe-on-release.patch
@@ -0,0 +1,152 @@
+From ab078e115c18e916aed4da927c4dec714e05a6af Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Tue, 9 Jul 2019 19:12:44 -0400
+Subject: [PATCH 3230/4256] drm/amdgpu: Implement VRAM wipe on release
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Wipe VRAM memory containing sensitive data when moving or releasing
+BOs. Clearing the memory is pipelined to minimize any impact on
+subsequent memory allocation latency. Use of a poison value should
+help debug future use-after-free bugs.
+
+When moving BOs, the existing ttm_bo_pipelined_move ensures that the
+memory won't be reused before being wiped.
+
+When releasing BOs, the BO is fenced with the memory fill operation,
+which results in queuing the BO for a delayed delete.
+
+v2: Move amdgpu_amdkfd_unreserve_memory_limit into
+amdgpu_bo_release_notify so that KFD can use memory that's still
+being cleared in the background
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 39 ++++++++++++++++++++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    | 17 ++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h    |  2 ++
+ 4 files changed, 56 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+index 495c5d33fc62..c983b386889c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+@@ -82,9 +82,6 @@ static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
+ 	if (bo->pin_count > 0)
+ 		amdgpu_bo_subtract_pin_size(bo);
+ 
+-	if (bo->kfd_bo)
+-		amdgpu_amdkfd_unreserve_memory_limit(bo);
+-
+ 	amdgpu_bo_kunmap(bo);
+ 
+ 	if (bo->gem_base.import_attach)
+@@ -1253,6 +1250,42 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
+ 	trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
+ }
+ 
++/**
++ * amdgpu_bo_move_notify - notification about a BO being released
++ * @bo: pointer to a buffer object
++ *
++ * Wipes VRAM buffers whose contents should not be leaked before the
++ * memory is released.
++ */
++void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
++{
++	struct dma_fence *fence = NULL;
++	struct amdgpu_bo *abo;
++	int r;
++
++	if (!amdgpu_bo_is_amdgpu_bo(bo))
++		return;
++
++	abo = ttm_to_amdgpu_bo(bo);
++
++	if (abo->kfd_bo)
++		amdgpu_amdkfd_unreserve_memory_limit(abo);
++
++	if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node ||
++	    !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE))
++		return;
++
++	reservation_object_lock(bo->resv, NULL);
++
++	r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->resv, &fence);
++	if (!WARN_ON(r)) {
++		amdgpu_bo_fence(abo, fence, false);
++		dma_fence_put(fence);
++	}
++
++	reservation_object_unlock(bo->resv);
++}
++
+ /**
+  * amdgpu_bo_fault_reserve_notify - notification about a memory fault
+  * @bo: pointer to a buffer object
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+index 6658c2399223..aed30cc3f4ca 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+@@ -269,6 +269,7 @@ int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
+ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
+ 			   bool evict,
+ 			   struct ttm_mem_reg *new_mem);
++void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
+ int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
+ void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
+ 		     bool shared);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index ff0ab1521cde..5b21dae64755 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -555,6 +555,22 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
+ 	if (r)
+ 		goto error;
+ 
++	/* clear the space being freed */
++	if (old_mem->mem_type == TTM_PL_VRAM &&
++	    (ttm_to_amdgpu_bo(bo)->flags &
++	     AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
++		struct dma_fence *wipe_fence = NULL;
++
++		r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
++				       NULL, &wipe_fence);
++		if (r) {
++			goto error;
++		} else if (wipe_fence) {
++			dma_fence_put(fence);
++			fence = wipe_fence;
++		}
++	}
++
+ 	/* Always block for VM page tables before committing the new location */
+ 	if (bo->type == ttm_bo_type_kernel)
+ 		r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
+@@ -1741,6 +1757,7 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
+ 	.move = &amdgpu_bo_move,
+ 	.verify_access = &amdgpu_verify_access,
+ 	.move_notify = &amdgpu_bo_move_notify,
++	.release_notify = &amdgpu_bo_release_notify,
+ 	.fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
+ 	.io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
+ 	.io_mem_free = &amdgpu_ttm_io_mem_free,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+index 6b93fcb0b12e..b92297987138 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+@@ -42,6 +42,8 @@
+ #define AMDGPU_GTT_MAX_TRANSFER_SIZE	512
+ #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS	2
+ 
++#define AMDGPU_POISON	0xd0bed0be
++
+ struct amdgpu_mman {
+ 	struct ttm_bo_global_ref        bo_global_ref;
+ 	struct drm_global_reference	mem_global_ref;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3231-drm-amdgpu-Add-amdgpu_asic_funcs.reset_method-for-Ve.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3231-drm-amdgpu-Add-amdgpu_asic_funcs.reset_method-for-Ve.patch
new file mode 100644
index 00000000..e316f80f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3231-drm-amdgpu-Add-amdgpu_asic_funcs.reset_method-for-Ve.patch
@@ -0,0 +1,29 @@
+From 1b239d9f2ea7fe0baf2e97a7f127bae3a52bd5b1 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Thu, 1 Aug 2019 11:44:17 -0400
+Subject: [PATCH 3231/4256] drm/amdgpu: Add amdgpu_asic_funcs.reset_method for
+ Vega20
+
+Fixes GPU reset crash.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index dc553978d23a..543f19b6655d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -895,6 +895,7 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
+ 	.get_pcie_usage = &soc15_get_pcie_usage,
+ 	.need_reset_on_init = &soc15_need_reset_on_init,
+ 	.get_pcie_replay_count = &soc15_get_pcie_replay_count,
++	.reset_method = &soc15_asic_reset_method
+ };
+ 
+ static int soc15_common_early_init(void *handle)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3232-drm-amdgpu-Update-NBIO-headers-to-add-TXCLK3-4.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3232-drm-amdgpu-Update-NBIO-headers-to-add-TXCLK3-4.patch
new file mode 100644
index 00000000..bf2cd004
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3232-drm-amdgpu-Update-NBIO-headers-to-add-TXCLK3-4.patch
@@ -0,0 +1,76 @@
+From 54427ac8bb6fbe9a4d311960311669f9f94e6974 Mon Sep 17 00:00:00 2001
+From: Kent Russell <kent.russell@amd.com>
+Date: Wed, 31 Jul 2019 09:23:45 -0400
+Subject: [PATCH 3232/4256] drm/amdgpu: Update NBIO headers to add TXCLK3/4
+
+These are added for VG20, and are needed for PCIe bandwidth.
+
+Change-Id: I54474bb53ed563d083521d24944f5f97d372f001
+Signed-off-by: Kent Russell <kent.russell@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../include/asic_reg/nbio/nbio_7_0_sh_mask.h  | 30 +++++++++++++++++++
+ .../amd/include/asic_reg/nbio/nbio_7_0_smn.h  |  6 ++++
+ 2 files changed, 36 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h
+index 88602479a1aa..ee8c15e4543d 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h
+@@ -74709,6 +74709,36 @@
+ //PCIE_PERF_COUNT1_TXCLK2
+ #define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT                                                              0x0
+ #define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK                                                                0xFFFFFFFFL
++//PCIE_PERF_CNTL_TXCLK3
++#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL__SHIFT                                                              0x0
++#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL__SHIFT                                                              0x8
++#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER__SHIFT                                                          0x10
++#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER__SHIFT                                                          0x18
++#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL_MASK                                                                0x000000FFL
++#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL_MASK                                                                0x0000FF00L
++#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER_MASK                                                            0x00FF0000L
++#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER_MASK                                                            0xFF000000L
++//PCIE_PERF_COUNT0_TXCLK3
++#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0__SHIFT                                                              0x0
++#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0_MASK                                                                0xFFFFFFFFL
++//PCIE_PERF_COUNT1_TXCLK3
++#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1__SHIFT                                                              0x0
++#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1_MASK                                                                0xFFFFFFFFL
++//PCIE_PERF_CNTL_TXCLK4
++#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL__SHIFT                                                              0x0
++#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL__SHIFT                                                              0x8
++#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER__SHIFT                                                          0x10
++#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER__SHIFT                                                          0x18
++#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL_MASK                                                                0x000000FFL
++#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL_MASK                                                                0x0000FF00L
++#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER_MASK                                                            0x00FF0000L
++#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER_MASK                                                            0xFF000000L
++//PCIE_PERF_COUNT0_TXCLK4
++#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0__SHIFT                                                              0x0
++#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0_MASK                                                                0xFFFFFFFFL
++//PCIE_PERF_COUNT1_TXCLK4
++#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1__SHIFT                                                              0x0
++#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1_MASK                                                                0xFFFFFFFFL
+ //PCIE_PRBS_CLR
+ #define PCIE_PRBS_CLR__PRBS_CLR__SHIFT                                                                        0x0
+ #define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT                                                                0x18
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
+index caf5ffdc130a..6702575bc6e3 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
+@@ -50,6 +50,12 @@
+ #define smnPCIE_PERF_CNTL_TXCLK2			0x11180254
+ #define smnPCIE_PERF_COUNT0_TXCLK2			0x11180258
+ #define smnPCIE_PERF_COUNT1_TXCLK2			0x1118025c
++#define smnPCIE_PERF_CNTL_TXCLK3                        0x1118021c
++#define smnPCIE_PERF_COUNT0_TXCLK3                      0x11180220
++#define smnPCIE_PERF_COUNT1_TXCLK3                      0x11180224
++#define smnPCIE_PERF_CNTL_TXCLK4                        0x11180228
++#define smnPCIE_PERF_COUNT0_TXCLK4                      0x1118022c
++#define smnPCIE_PERF_COUNT1_TXCLK4                      0x11180230
+ 
+ #define smnPCIE_RX_NUM_NAK				0x11180038
+ #define smnPCIE_RX_NUM_NAK_GENERATED			0x1118003c
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3233-drm-amdgpu-Fix-pcie_bw-on-Vega20.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3233-drm-amdgpu-Fix-pcie_bw-on-Vega20.patch
new file mode 100644
index 00000000..1197864e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3233-drm-amdgpu-Fix-pcie_bw-on-Vega20.patch
@@ -0,0 +1,105 @@
+From dd7ccac5720f796a9a63dbe4833031ab8f4c3f70 Mon Sep 17 00:00:00 2001
+From: Kent Russell <kent.russell@amd.com>
+Date: Wed, 31 Jul 2019 09:24:32 -0400
+Subject: [PATCH 3233/4256] drm/amdgpu: Fix pcie_bw on Vega20
+
+The registers used for VG20 are different in that certain performance
+counters were split off to TXCLK3/4. Vega10/12 doesn't have this, so add
+a new vg20_get_pcie_usage to reflect this change.
+
+Change-Id: Iec4bf608411b46f0827e7ffeb74ce93e1fd3d1b8
+Signed-off-by: Kent Russell <kent.russell@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 60 ++++++++++++++++++++++++++----
+ 1 file changed, 52 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 543f19b6655d..125ba1b15b6a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -784,14 +784,9 @@ static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
+ 
+ 	/* Set the 2 events that we wish to watch, defined above */
+ 	/* Reg 40 is # received msgs */
++	/* Reg 104 is # of posted requests sent */
+ 	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
+-	/* Pre-VG20, Reg 104 is # of posted requests sent. On VG20 it's 108 */
+-	if (adev->asic_type == CHIP_VEGA20)
+-		perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
+-					EVENT1_SEL, 108);
+-	else
+-		perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
+-					EVENT1_SEL, 104);
++	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
+ 
+ 	/* Write to enable desired perf counters */
+ 	WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
+@@ -821,6 +816,55 @@ static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
+ 	*count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
+ }
+ 
++static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
++				 uint64_t *count1)
++{
++	uint32_t perfctr = 0;
++	uint64_t cnt0_of, cnt1_of;
++	int tmp;
++
++	/* This reports 0 on APUs, so return to avoid writing/reading registers
++	 * that may or may not be different from their GPU counterparts
++	 */
++	if (adev->flags & AMD_IS_APU)
++		return;
++
++	/* Set the 2 events that we wish to watch, defined above */
++	/* Reg 40 is # received msgs */
++	/* Reg 108 is # of posted requests sent on VG20 */
++	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
++				EVENT0_SEL, 40);
++	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
++				EVENT1_SEL, 108);
++
++	/* Write to enable desired perf counters */
++	WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
++	/* Zero out and enable the perf counters
++	 * Write 0x5:
++	 * Bit 0 = Start all counters(1)
++	 * Bit 2 = Global counter reset enable(1)
++	 */
++	WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
++
++	msleep(1000);
++
++	/* Load the shadow and disable the perf counters
++	 * Write 0x2:
++	 * Bit 0 = Stop counters(0)
++	 * Bit 1 = Load the shadow counters(1)
++	 */
++	WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
++
++	/* Read register values to get any >32bit overflow */
++	tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
++	cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
++	cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
++
++	/* Get the values and add the overflow */
++	*count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
++	*count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
++}
++
+ static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
+ {
+ 	u32 sol_reg;
+@@ -892,7 +936,7 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
+ 	.invalidate_hdp = &soc15_invalidate_hdp,
+ 	.need_full_reset = &soc15_need_full_reset,
+ 	.init_doorbell_index = &vega20_doorbell_index_init,
+-	.get_pcie_usage = &soc15_get_pcie_usage,
++	.get_pcie_usage = &vega20_get_pcie_usage,
+ 	.need_reset_on_init = &soc15_need_reset_on_init,
+ 	.get_pcie_replay_count = &soc15_get_pcie_replay_count,
+ 	.reset_method = &soc15_asic_reset_method
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3234-drm-amdgpu-support-get_cu_info-for-Arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3234-drm-amdgpu-support-get_cu_info-for-Arcturus.patch
new file mode 100644
index 00000000..cebd9fd9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3234-drm-amdgpu-support-get_cu_info-for-Arcturus.patch
@@ -0,0 +1,96 @@
+From dc532463d4d4334dcbb16c104e5efa9329eba89b Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Mon, 8 Jul 2019 20:17:48 +0800
+Subject: [PATCH 3234/4256] drm/amdgpu: support get_cu_info for Arcturus
+
+This change is because SE/SH layout on Arcturus is 8*1, different from
+4*2(or 4*1) on Vega ASICs.
+
+Currently the cu bitmap array is 4x4 size, and besides the bitmap is used widely
+across SW stack. To mostly reduce the scale of impact, we make the cu bitmap
+array compatible with SE/SH layout on Arcturus. Then the store of cu bits of
+each shader array for Arcturus will be like below:
+    SE0,SH0 --> bitmap[0][0]
+    SE1,SH0 --> bitmap[1][0]
+    SE2,SH0 --> bitmap[2][0]
+    SE3,SH0 --> bitmap[3][0]
+    SE4,SH0 --> bitmap[0][1]
+    SE5,SH0 --> bitmap[1][1]
+    SE6,SH0 --> bitmap[2][1]
+    SE7,SH0 --> bitmap[3][1]
+
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 35 +++++++++++++++++++++------
+ 1 file changed, 28 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 1ba428d5c2e1..3a8fc96032ef 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -6360,12 +6360,21 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
+ {
+ 	int i, j, k, counter, active_cu_number = 0;
+ 	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
+-	unsigned disable_masks[4 * 2];
++	unsigned disable_masks[4 * 4];
+ 
+ 	if (!adev || !cu_info)
+ 		return -EINVAL;
+ 
+-	amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
++	/*
++	 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs
++	 */
++	if (adev->gfx.config.max_shader_engines *
++		adev->gfx.config.max_sh_per_se > 16)
++		return -EINVAL;
++
++	amdgpu_gfx_parse_disable_cu(disable_masks,
++				    adev->gfx.config.max_shader_engines,
++				    adev->gfx.config.max_sh_per_se);
+ 
+ 	mutex_lock(&adev->grbm_idx_mutex);
+ 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
+@@ -6374,11 +6383,23 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
+ 			ao_bitmap = 0;
+ 			counter = 0;
+ 			gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
+-			if (i < 4 && j < 2)
+-				gfx_v9_0_set_user_cu_inactive_bitmap(
+-					adev, disable_masks[i * 2 + j]);
++			gfx_v9_0_set_user_cu_inactive_bitmap(
++				adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]);
+ 			bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
+-			cu_info->bitmap[i][j] = bitmap;
++
++			/*
++			 * The bitmap(and ao_cu_bitmap) in cu_info structure is
++			 * 4x4 size array, and it's usually suitable for Vega
++			 * ASICs which has 4*2 SE/SH layout.
++			 * But for Arcturus, SE/SH layout is changed to 8*1.
++			 * To mostly reduce the impact, we make it compatible
++			 * with current bitmap array as below:
++			 *    SE4,SH0 --> bitmap[0][1]
++			 *    SE5,SH0 --> bitmap[1][1]
++			 *    SE6,SH0 --> bitmap[2][1]
++			 *    SE7,SH0 --> bitmap[3][1]
++			 */
++			cu_info->bitmap[i % 4][j + i / 4] = bitmap;
+ 
+ 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
+ 				if (bitmap & mask) {
+@@ -6391,7 +6412,7 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
+ 			active_cu_number += counter;
+ 			if (i < 2 && j < 2)
+ 				ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
+-			cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
++			cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap;
+ 		}
+ 	}
+ 	gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3235-drm-amdkfd-Extend-CU-mask-to-8-SEs-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3235-drm-amdkfd-Extend-CU-mask-to-8-SEs-v3.patch
new file mode 100644
index 00000000..5f65ba13
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3235-drm-amdkfd-Extend-CU-mask-to-8-SEs-v3.patch
@@ -0,0 +1,152 @@
+From eb1280f13d782ff87cb9f04fcfb6c351b8d125e6 Mon Sep 17 00:00:00 2001
+From: Jay Cornwall <Jay.Cornwall@amd.com>
+Date: Thu, 18 Jul 2019 16:57:22 -0500
+Subject: [PATCH 3235/4256] drm/amdkfd: Extend CU mask to 8 SEs (v3)
+
+Following bitmap layout logic introduced by:
+"drm/amdgpu: support get_cu_info for Arcturus".
+
+v2: squash in fixup for gfx_v9_0.c (Alex)
+v3: squash in debug print output fix
+
+Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c          |  4 ++++
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c   | 10 +++++-----
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h   |  2 ++
+ .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c    | 18 +++++++++++++++---
+ drivers/gpu/drm/amd/include/v9_structs.h       |  8 ++++----
+ 5 files changed, 30 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 3a8fc96032ef..51de6268c177 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -3348,6 +3348,10 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
+ 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
+ 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
+ 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
++	mqd->compute_static_thread_mgmt_se4 = 0xffffffff;
++	mqd->compute_static_thread_mgmt_se5 = 0xffffffff;
++	mqd->compute_static_thread_mgmt_se6 = 0xffffffff;
++	mqd->compute_static_thread_mgmt_se7 = 0xffffffff;
+ 	mqd->compute_misc_reserved = 0x00000003;
+ 
+ 	mqd->dynamic_cu_mask_addr_lo =
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
+index d6cf391da591..88813dad731f 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
+@@ -98,8 +98,8 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
+ 		uint32_t *se_mask)
+ {
+ 	struct kfd_cu_info cu_info;
+-	uint32_t cu_per_sh[4] = {0};
+-	int i, se, cu = 0;
++	uint32_t cu_per_se[KFD_MAX_NUM_SE] = {0};
++	int i, se, sh, cu = 0;
+ 
+ 	amdgpu_amdkfd_get_cu_info(mm->dev->kgd, &cu_info);
+ 
+@@ -107,8 +107,8 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
+ 		cu_mask_count = cu_info.cu_active_number;
+ 
+ 	for (se = 0; se < cu_info.num_shader_engines; se++)
+-		for (i = 0; i < 4; i++)
+-			cu_per_sh[se] += hweight32(cu_info.cu_bitmap[se][i]);
++		for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++)
++			cu_per_se[se] += hweight32(cu_info.cu_bitmap[se % 4][sh + (se / 4)]);
+ 
+ 	/* Symmetrically map cu_mask to all SEs:
+ 	 * cu_mask[0] bit0 -> se_mask[0] bit0;
+@@ -128,6 +128,6 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
+ 				se = 0;
+ 				cu++;
+ 			}
+-		} while (cu >= cu_per_sh[se] && cu < 32);
++		} while (cu >= cu_per_se[se] && cu < 32);
+ 	}
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
+index 10c2ff1ad683..e1455a921a3b 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
+@@ -26,6 +26,8 @@
+ 
+ #include "kfd_priv.h"
+ 
++#define KFD_MAX_NUM_SE 8
++
+ /**
+  * struct mqd_manager
+  *
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index 31c045178065..785ceda52c94 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -89,7 +89,7 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd,
+ 			struct queue_properties *q)
+ {
+ 	struct v9_mqd *m;
+-	uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */
++	uint32_t se_mask[KFD_MAX_NUM_SE] = {0};
+ 
+ 	if (q->cu_mask_count == 0)
+ 		return;
+@@ -102,12 +102,20 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd,
+ 	m->compute_static_thread_mgmt_se1 = se_mask[1];
+ 	m->compute_static_thread_mgmt_se2 = se_mask[2];
+ 	m->compute_static_thread_mgmt_se3 = se_mask[3];
++	m->compute_static_thread_mgmt_se4 = se_mask[4];
++	m->compute_static_thread_mgmt_se5 = se_mask[5];
++	m->compute_static_thread_mgmt_se6 = se_mask[6];
++	m->compute_static_thread_mgmt_se7 = se_mask[7];
+ 
+-	pr_debug("update cu mask to %#x %#x %#x %#x\n",
++	pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n",
+ 		m->compute_static_thread_mgmt_se0,
+ 		m->compute_static_thread_mgmt_se1,
+ 		m->compute_static_thread_mgmt_se2,
+-		m->compute_static_thread_mgmt_se3);
++		m->compute_static_thread_mgmt_se3,
++		m->compute_static_thread_mgmt_se4,
++		m->compute_static_thread_mgmt_se5,
++		m->compute_static_thread_mgmt_se6,
++		m->compute_static_thread_mgmt_se7);
+ }
+ 
+ static void set_priority(struct v9_mqd *m, struct queue_properties *q)
+@@ -168,6 +176,10 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,
+ 	m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
+ 	m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
+ 	m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
++	m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF;
++	m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF;
++	m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF;
++	m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF;
+ 
+ 	m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
+ 			0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
+diff --git a/drivers/gpu/drm/amd/include/v9_structs.h b/drivers/gpu/drm/amd/include/v9_structs.h
+index 8b383dbe1cda..a0c672889fe4 100644
+--- a/drivers/gpu/drm/amd/include/v9_structs.h
++++ b/drivers/gpu/drm/amd/include/v9_structs.h
+@@ -196,10 +196,10 @@ struct v9_mqd {
+ 	uint32_t compute_wave_restore_addr_lo;
+ 	uint32_t compute_wave_restore_addr_hi;
+ 	uint32_t compute_wave_restore_control;
+-	uint32_t reserved_39;
+-	uint32_t reserved_40;
+-	uint32_t reserved_41;
+-	uint32_t reserved_42;
++	uint32_t compute_static_thread_mgmt_se4;
++	uint32_t compute_static_thread_mgmt_se5;
++	uint32_t compute_static_thread_mgmt_se6;
++	uint32_t compute_static_thread_mgmt_se7;
+ 	uint32_t reserved_43;
+ 	uint32_t reserved_44;
+ 	uint32_t reserved_45;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3236-drm-amd-powerplay-fix-off-by-one-upper-bounds-limit-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3236-drm-amd-powerplay-fix-off-by-one-upper-bounds-limit-.patch
new file mode 100644
index 00000000..0c16f2ba
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3236-drm-amd-powerplay-fix-off-by-one-upper-bounds-limit-.patch
@@ -0,0 +1,43 @@
+From 53619aa32a5b2a5f3909b8f87bc10de7c6770bb9 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Thu, 1 Aug 2019 12:15:41 +0100
+Subject: [PATCH 3236/4256] drm/amd/powerplay: fix off-by-one upper bounds
+ limit checks
+
+There are two occurrances of off-by-one upper bound checking of indexes
+causing potential out-of-bounds array reads. Fix these.
+
+Addresses-Coverity: ("Out-of-bounds read")
+Fixes: cb33363d0e85 ("drm/amd/powerplay: add smu feature name support")
+Fixes: 6b294793e384 ("drm/amd/powerplay: add smu message name support")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 8641b3a8f81e..70522aa6a7b2 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -38,7 +38,7 @@ static const char* __smu_message_names[] = {
+ 
+ const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
+ {
+-	if (type < 0 || type > SMU_MSG_MAX_COUNT)
++	if (type < 0 || type >= SMU_MSG_MAX_COUNT)
+ 		return "unknow smu message";
+ 	return __smu_message_names[type];
+ }
+@@ -51,7 +51,7 @@ static const char* __smu_feature_names[] = {
+ 
+ const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
+ {
+-	if (feature < 0 || feature > SMU_FEATURE_COUNT)
++	if (feature < 0 || feature >= SMU_FEATURE_COUNT)
+ 		return "unknow smu feature";
+ 	return __smu_feature_names[feature];
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3237-drm-amd-powerplay-fix-a-few-spelling-mistakes.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3237-drm-amd-powerplay-fix-a-few-spelling-mistakes.patch
new file mode 100644
index 00000000..0f90b102
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3237-drm-amd-powerplay-fix-a-few-spelling-mistakes.patch
@@ -0,0 +1,48 @@
+From 0f9fec68713d59ce11117770ef2297d52b76e77e Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Thu, 1 Aug 2019 09:39:41 +0100
+Subject: [PATCH 3237/4256] drm/amd/powerplay: fix a few spelling mistakes
+
+There are a few spelling mistakes "unknow" -> "unknown" and
+"enabeld" -> "enabled". Fix these.
+
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 70522aa6a7b2..46976c90843b 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -39,7 +39,7 @@ static const char* __smu_message_names[] = {
+ const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
+ {
+ 	if (type < 0 || type >= SMU_MSG_MAX_COUNT)
+-		return "unknow smu message";
++		return "unknown smu message";
+ 	return __smu_message_names[type];
+ }
+ 
+@@ -52,7 +52,7 @@ static const char* __smu_feature_names[] = {
+ const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
+ {
+ 	if (feature < 0 || feature >= SMU_FEATURE_COUNT)
+-		return "unknow smu feature";
++		return "unknown smu feature";
+ 	return __smu_feature_names[feature];
+ }
+ 
+@@ -87,7 +87,7 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
+ 			       smu_get_feature_name(smu, sort_feature[i]),
+ 			       i,
+ 			       !!smu_feature_is_enabled(smu, sort_feature[i]) ?
+-			       "enabeld" : "disabled");
++			       "enabled" : "disabled");
+ 	}
+ 
+ failed:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3238-drm-amd-powerplay-Allow-changing-of-fan_control-in-s.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3238-drm-amd-powerplay-Allow-changing-of-fan_control-in-s.patch
new file mode 100644
index 00000000..26e6e56a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3238-drm-amd-powerplay-Allow-changing-of-fan_control-in-s.patch
@@ -0,0 +1,39 @@
+From e4599062f7af7528f596bda1ae84adc8d1f04d2e Mon Sep 17 00:00:00 2001
+From: Matt Coffin <mcoffin13@gmail.com>
+Date: Wed, 31 Jul 2019 14:14:35 -0600
+Subject: [PATCH 3238/4256] drm/amd/powerplay: Allow changing of fan_control in
+ smu_v11_0
+
+[Why]
+Before this change, the fan control state on smu_v11 was not able to be
+changed because the capability check for checking if the fan control
+capability existed was inverted.
+
+[How]
+The capability check for fan control in smu_v11_0_auto_fan_control was
+inverted, to correctly check for the absence, instead of presence of fan
+control capabilities.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Matt Coffin <mcoffin13@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 0588dd8cd1ba..43fcbdbba630 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1361,7 +1361,7 @@ smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
+ {
+ 	int ret = 0;
+ 
+-	if (smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
++	if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
+ 		return 0;
+ 
+ 	ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3239-drm-amdgpu-fix-unsigned-variable-instance-compared-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3239-drm-amdgpu-fix-unsigned-variable-instance-compared-t.patch
new file mode 100644
index 00000000..c07004cf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3239-drm-amdgpu-fix-unsigned-variable-instance-compared-t.patch
@@ -0,0 +1,35 @@
+From f04a0ccc189e163316d72afb419c3637a1280ec7 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Thu, 1 Aug 2019 12:01:45 +0100
+Subject: [PATCH 3239/4256] drm/amdgpu: fix unsigned variable instance compared
+ to less than zero
+
+Currenly the error check on variable instance is always false because
+it is a uint32_t type and this is never less than zero. Fix this by
+making it an int type.
+
+Addresses-Coverity: ("Unsigned compared against 0")
+Fixes: 7d0e6329dfdc ("drm/amdgpu: update more sdma instances irq support")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 93cd0a64eca0..efbb6f22fefc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1962,7 +1962,8 @@ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
+ 		struct ras_err_data *err_data,
+ 		struct amdgpu_iv_entry *entry)
+ {
+-	uint32_t instance, err_source;
++	uint32_t err_source;
++	int instance;
+ 
+ 	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
+ 	if (instance < 0)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3240-drm-amd-display-Allow-cursor-async-updates-for-frame.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3240-drm-amd-display-Allow-cursor-async-updates-for-frame.patch
new file mode 100644
index 00000000..e2941138
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3240-drm-amd-display-Allow-cursor-async-updates-for-frame.patch
@@ -0,0 +1,60 @@
+From 8b1385c1108b9d6f1a52a62a7caea496ec2442e2 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Mon, 10 Jun 2019 08:47:57 -0400
+Subject: [PATCH 3240/4256] drm/amd/display: Allow cursor async updates for
+ framebuffer swaps
+
+[Why]
+We previously allowed framebuffer swaps as async updates for cursor
+planes but had to disable them due to a bug in DRM with async update
+handling and incorrect ref counting. The check to block framebuffer
+swaps has been added to DRM for a while now, so this check is redundant.
+
+The real fix that allows this to properly in DRM has also finally been
+merged and is getting backported into stable branches, so dropping
+this now seems to be the right time to do so.
+
+[How]
+Drop the redundant check for old_fb != new_fb.
+
+With the proper fix in DRM, this should also fix some cursor stuttering
+issues with xf86-video-amdgpu since it double buffers the cursor.
+
+IGT tests that swap framebuffers (-varying-size for example) should
+also pass again.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: David Francis <david.francis@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ----------
+ 1 file changed, 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index d981cbcd2ce2..ea57affae0cc 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -4527,20 +4527,10 @@ static int dm_plane_atomic_check(struct drm_plane *plane,
+ static int dm_plane_atomic_async_check(struct drm_plane *plane,
+ 				       struct drm_plane_state *new_plane_state)
+ {
+-	struct drm_plane_state *old_plane_state =
+-		drm_atomic_get_old_plane_state(new_plane_state->state, plane);
+-
+ 	/* Only support async updates on cursor planes. */
+ 	if (plane->type != DRM_PLANE_TYPE_CURSOR)
+ 		return -EINVAL;
+ 
+-	/*
+-	 * DRM calls prepare_fb and cleanup_fb on new_plane_state for
+-	 * async commits so don't allow fb changes.
+-	 */
+-	if (old_plane_state->fb != new_plane_state->fb)
+-		return -EINVAL;
+-
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3241-drm-amd-display-Skip-determining-update-type-for-asy.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3241-drm-amd-display-Skip-determining-update-type-for-asy.patch
new file mode 100644
index 00000000..24e35382
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3241-drm-amd-display-Skip-determining-update-type-for-asy.patch
@@ -0,0 +1,76 @@
+From b8a6ddcdb8c99bed67cd3a0bc5ca8a9b6b2487e8 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Wed, 31 Jul 2019 09:45:16 -0400
+Subject: [PATCH 3241/4256] drm/amd/display: Skip determining update type for
+ async updates
+
+[Why]
+By passing through the dm_determine_update_type_for_commit for atomic
+commits that can be done asynchronously we are incurring a
+performance penalty by locking access to the global private object
+and holding that access until the end of the programming sequence.
+
+This is also allocating a new large dc_state on every access in addition
+to retaining all the references on each stream and plane until the end
+of the programming sequence.
+
+[How]
+Shift the determination for async update before validation. Return early
+if it's going to be an async update.
+
+Change-Id: I811fff81376d83820b20b8ac622d33a87fdec896
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: David Francis <david.francis@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 27 ++++++++++++++-----
+ 1 file changed, 20 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index ea57affae0cc..2d408b614ee0 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -7225,6 +7225,26 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
+ 	if (ret)
+ 		goto fail;
+ 
++	if (state->legacy_cursor_update) {
++		/*
++		 * This is a fast cursor update coming from the plane update
++		 * helper, check if it can be done asynchronously for better
++		 * performance.
++		 */
++		state->async_update =
++			!drm_atomic_helper_async_check(dev, state);
++
++		/*
++		 * Skip the remaining global validation if this is an async
++		 * update. Cursor updates can be done without affecting
++		 * state or bandwidth calcs and this avoids the performance
++		 * penalty of locking the private state object and
++		 * allocating a new dc_state.
++		 */
++		if (state->async_update)
++			return 0;
++	}
++
+ 	/* Check scaling and underscan changes*/
+ 	/*TODO Removed scaling changes validation due to inability to commit
+ 	 * new stream into context w\o causing full reset. Need to
+@@ -7277,13 +7297,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
+ 			ret = -EINVAL;
+ 			goto fail;
+ 		}
+-	} else if (state->legacy_cursor_update) {
+-		/*
+-		 * This is a fast cursor update coming from the plane update
+-		 * helper, check if it can be done asynchronously for better
+-		 * performance.
+-		 */
+-		state->async_update = !drm_atomic_helper_async_check(dev, state);
+ 	}
+ 
+ 	/* Must be success */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3242-drm-amd-display-Don-t-replace-the-dc_state-for-fast-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3242-drm-amd-display-Don-t-replace-the-dc_state-for-fast-.patch
new file mode 100644
index 00000000..397f8968
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3242-drm-amd-display-Don-t-replace-the-dc_state-for-fast-.patch
@@ -0,0 +1,102 @@
+From f7ff7c11108290d5c87009a1d43c532a20260d46 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Wed, 31 Jul 2019 10:33:54 -0400
+Subject: [PATCH 3242/4256] drm/amd/display: Don't replace the dc_state for
+ fast updates
+
+[Why]
+DRM private objects have no hw_done/flip_done fencing mechanism on their
+own and cannot be used to sequence commits accordingly.
+
+When issuing commits that don't touch the same set of hardware resources
+like page-flips on different CRTCs we can run into the issue below
+because of this:
+
+1. Client requests non-blocking Commit #1, has a new dc_state #1,
+state is swapped, commit tail is deferred to work queue
+
+2. Client requests non-blocking Commit #2, has a new dc_state #2,
+state is swapped, commit tail is deferred to work queue
+
+3. Commit #2 work starts, commit tail finishes,
+atomic state is cleared, dc_state #1 is freed
+
+4. Commit #1 work starts,
+commit tail encounters null pointer deref on dc_state #1
+
+In order to change the DC state as in the private object we need to
+ensure that we wait for all outstanding commits to finish and that
+any other pending commits must wait for the current one to finish as
+well.
+
+We do this for MEDIUM and FULL updates. But not for FAST updates, nor
+would we want to since it would cause stuttering from the delays.
+
+FAST updates that go through dm_determine_update_type_for_commit always
+create a new dc_state and lock the DRM private object if there are
+any changed planes.
+
+We need the old state to validate, but we don't actually need the new
+state here.
+
+[How]
+If the commit isn't a full update then the use after free can be
+resolved by simply discarding the new state entirely and retaining
+the existing one instead.
+
+With this change the sequence above can be reexamined. Commit #2 will
+still free Commit #1's reference, but before this happens we actually
+added an additional reference as part of Commit #2.
+
+If an update comes in during this that needs to change the dc_state
+it will need to wait on Commit #1 and Commit #2 to finish. Then it'll
+swap the state, finish the work in commit tail and drop the last
+reference on Commit #2's dc_state.
+
+Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204181
+Fixes: 004b3938e637 ("drm/amd/display: Check scaling info when determing update type")
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: David Francis <david.francis@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 +++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 2d408b614ee0..3ec42eb79ec9 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -7297,6 +7297,29 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
+ 			ret = -EINVAL;
+ 			goto fail;
+ 		}
++	} else {
++		/*
++		 * The commit is a fast update. Fast updates shouldn't change
++		 * the DC context, affect global validation, and can have their
++		 * commit work done in parallel with other commits not touching
++		 * the same resource. If we have a new DC context as part of
++		 * the DM atomic state from validation we need to free it and
++		 * retain the existing one instead.
++		 */
++		struct dm_atomic_state *new_dm_state, *old_dm_state;
++
++		new_dm_state = dm_atomic_get_new_state(state);
++		old_dm_state = dm_atomic_get_old_state(state);
++
++		if (new_dm_state && old_dm_state) {
++			if (new_dm_state->context)
++				dc_release_state(new_dm_state->context);
++
++			new_dm_state->context = old_dm_state->context;
++
++			if (old_dm_state->context)
++				dc_retain_state(old_dm_state->context);
++		}
+ 	}
+ 
+ 	/* Must be success */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3243-drm-amd-powerplay-correct-navi10-vcn-powergate.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3243-drm-amd-powerplay-correct-navi10-vcn-powergate.patch
new file mode 100644
index 00000000..41ac0007
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3243-drm-amd-powerplay-correct-navi10-vcn-powergate.patch
@@ -0,0 +1,93 @@
+From dd1805a1c232a7c4934d0b37d329d6ffe6f66595 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 2 Aug 2019 16:38:32 +0800
+Subject: [PATCH 3243/4256] drm/amd/powerplay: correct navi10 vcn powergate
+
+vcn dpm on is a prerequisite for vcn power gate control.
+
+Change-Id: If89a81bc0709f1c26569e378507a873cfaf6e0ef
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  4 +++-
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  1 +
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 23 ++++++++++++-------
+ 3 files changed, 19 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 46976c90843b..02077604a43a 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -409,6 +409,8 @@ int smu_get_power_num_states(struct smu_context *smu,
+ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
+ 			   void *data, uint32_t *size)
+ {
++	struct smu_power_context *smu_power = &smu->smu_power;
++	struct smu_power_gate *power_gate = &smu_power->power_gate;
+ 	int ret = 0;
+ 
+ 	switch (sensor) {
+@@ -433,7 +435,7 @@ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
+ 		*size = 4;
+ 		break;
+ 	case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
+-		*(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT) ? 1 : 0;
++		*(uint32_t *)data = power_gate->vcn_gated ? 0 : 1;
+ 		*size = 4;
+ 		break;
+ 	default:
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 1ecd73cd768c..2579b002616c 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -277,6 +277,7 @@ struct smu_dpm_context {
+ struct smu_power_gate {
+ 	bool uvd_gated;
+ 	bool vce_gated;
++	bool vcn_gated;
+ };
+ 
+ struct smu_power_context {
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index f3adb713784a..b7bb0f78f489 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -590,20 +590,27 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
+ 
+ static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
+ {
++	struct smu_power_context *smu_power = &smu->smu_power;
++	struct smu_power_gate *power_gate = &smu_power->power_gate;
+ 	int ret = 0;
+ 
+ 	if (enable) {
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
+-		if (ret)
+-			return ret;
++		/* vcn dpm on is a prerequisite for vcn power gate messages */
++		if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
++			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
++			if (ret)
++				return ret;
++		}
++		power_gate->vcn_gated = false;
+ 	} else {
+-		ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
+-		if (ret)
+-			return ret;
++		if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
++			ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
++			if (ret)
++				return ret;
++		}
++		power_gate->vcn_gated = true;
+ 	}
+ 
+-	ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, enable);
+-
+ 	return ret;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3244-drm-amd-powerplay-honor-hw-limit-on-fetching-metrics.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3244-drm-amd-powerplay-honor-hw-limit-on-fetching-metrics.patch
new file mode 100644
index 00000000..6df773f8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3244-drm-amd-powerplay-honor-hw-limit-on-fetching-metrics.patch
@@ -0,0 +1,131 @@
+From 5f67ba93c9f5047feeff8e6db1dcc64fa79ddc54 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Fri, 2 Aug 2019 12:01:00 +0800
+Subject: [PATCH 3244/4256] drm/amd/powerplay: honor hw limit on fetching
+ metrics data for navi10
+
+too frequently to update mertrics table will cause smu internal error.
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 56 +++++++++++++++-------
+ 1 file changed, 38 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index b7bb0f78f489..c9a7d26e6c92 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -515,6 +515,8 @@ static int navi10_store_powerplay_table(struct smu_context *smu)
+ 
+ static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
+ {
++	struct smu_table_context *smu_table = &smu->smu_table;
++
+ 	SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
+ 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ 	SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
+@@ -529,9 +531,35 @@ static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
+ 		       sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
+ 	               AMDGPU_GEM_DOMAIN_VRAM);
+ 
++	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
++	if (!smu_table->metrics_table)
++		return -ENOMEM;
++	smu_table->metrics_time = 0;
++
+ 	return 0;
+ }
+ 
++static int navi10_get_metrics_table(struct smu_context *smu,
++				    SmuMetrics_t *metrics_table)
++{
++	struct smu_table_context *smu_table= &smu->smu_table;
++	int ret = 0;
++
++	if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
++		ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
++				(void *)smu_table->metrics_table, false);
++		if (ret) {
++			pr_info("Failed to export SMU metrics table!\n");
++			return ret;
++		}
++		smu_table->metrics_time = jiffies;
++	}
++
++	memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
++
++	return ret;
++}
++
+ static int navi10_allocate_dpm_context(struct smu_context *smu)
+ {
+ 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+@@ -618,15 +646,10 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
+ 				       enum smu_clk_type clk_type,
+ 				       uint32_t *value)
+ {
+-	static SmuMetrics_t metrics;
+ 	int ret = 0, clk_id = 0;
++	SmuMetrics_t metrics;
+ 
+-	if (!value)
+-		return -EINVAL;
+-
+-	memset(&metrics, 0, sizeof(metrics));
+-
+-	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
++	ret = navi10_get_metrics_table(smu, &metrics);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -914,8 +937,9 @@ static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
+ 	if (!value)
+ 		return -EINVAL;
+ 
+-	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics,
+-			       false);
++	ret = navi10_get_metrics_table(smu, &metrics);
++	if (ret)
++		return ret;
+ 	if (ret)
+ 		return ret;
+ 
+@@ -934,10 +958,7 @@ static int navi10_get_current_activity_percent(struct smu_context *smu,
+ 	if (!value)
+ 		return -EINVAL;
+ 
+-	msleep(1);
+-
+-	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
+-			       (void *)&metrics, false);
++	ret = navi10_get_metrics_table(smu, &metrics);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -976,10 +997,9 @@ static int navi10_get_fan_speed_rpm(struct smu_context *smu,
+ 	if (!speed)
+ 		return -EINVAL;
+ 
+-	memset(&metrics, 0, sizeof(metrics));
+-
+-	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
+-			       (void *)&metrics, false);
++	ret = navi10_get_metrics_table(smu, &metrics);
++	if (ret)
++		return ret;
+ 	if (ret)
+ 		return ret;
+ 
+@@ -1332,7 +1352,7 @@ static int navi10_thermal_get_temperature(struct smu_context *smu,
+ 	if (!value)
+ 		return -EINVAL;
+ 
+-	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
++	ret = navi10_get_metrics_table(smu, &metrics);
+ 	if (ret)
+ 		return ret;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3245-drm-amdgpu-remove-the-clear-of-MCA_ADDR.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3245-drm-amdgpu-remove-the-clear-of-MCA_ADDR.patch
new file mode 100644
index 00000000..9a2706ab
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3245-drm-amdgpu-remove-the-clear-of-MCA_ADDR.patch
@@ -0,0 +1,31 @@
+From 2af391bb445728061428dceaabccc6a6e6ab9b48 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Mon, 29 Jul 2019 10:28:57 +0800
+Subject: [PATCH 3245/4256] drm/amdgpu: remove the clear of MCA_ADDR
+
+clearing MCA_STATUS is enough to reset the whole MCA, writing zero to
+MCA_ADDR is unnecessary
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+index bff1a12f2cc9..035e4fea472c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+@@ -229,8 +229,6 @@ static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
+ 
+ 			/* clear umc status */
+ 			WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
+-			/* clear error address register */
+-			WREG64_PCIE(smnMCA_UMC0_MCUMC_ADDRT0 + umc_reg_offset * 4, 0x0ULL);
+ 		}
+ 	}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3246-drm-amdgpu-add-more-parameters-and-functions-to-amdg.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3246-drm-amdgpu-add-more-parameters-and-functions-to-amdg.patch
new file mode 100644
index 00000000..15647b0c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3246-drm-amdgpu-add-more-parameters-and-functions-to-amdg.patch
@@ -0,0 +1,65 @@
+From 0827eb7f189a8419a457b0bfe73c7927a8bcca10 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Mon, 29 Jul 2019 14:10:54 +0800
+Subject: [PATCH 3246/4256] drm/amdgpu: add more parameters and functions to
+ amdgpu_umc structure
+
+expose more parameters and functions of specific umc version to common
+umc layer, so amdgpu_umc layer and other blocks could access them
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 13 +++++++++++++
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.h   |  2 ++
+ 2 files changed, 15 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+index dfa1a39e57af..2604f5076867 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+@@ -22,15 +22,28 @@
+ #define __AMDGPU_UMC_H__
+ 
+ struct amdgpu_umc_funcs {
++	void (*ras_init)(struct amdgpu_device *adev);
+ 	void (*query_ras_error_count)(struct amdgpu_device *adev,
+ 					void *ras_error_status);
+ 	void (*query_ras_error_address)(struct amdgpu_device *adev,
+ 					void *ras_error_status);
++	void (*enable_umc_index_mode)(struct amdgpu_device *adev,
++					uint32_t umc_instance);
++	void (*disable_umc_index_mode)(struct amdgpu_device *adev);
+ };
+ 
+ struct amdgpu_umc {
+ 	/* max error count in one ras query call */
+ 	uint32_t max_ras_err_cnt_per_query;
++	/* number of umc channel instance with memory map register access */
++	uint32_t channel_inst_num;
++	/* number of umc instance with memory map register access */
++	uint32_t umc_inst_num;
++	/* UMC regiser per channel offset */
++	uint32_t channel_offs;
++	/* channel index table of interleaved memory */
++	const uint32_t *channel_idx_tbl;
++
+ 	const struct amdgpu_umc_funcs *funcs;
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
+index d25ae414f4d8..bddaf14a77f9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
+@@ -31,6 +31,8 @@
+ #define UMC_V6_1_CHANNEL_INSTANCE_NUM		4
+ /* number of umc instance with memory map register access */
+ #define UMC_V6_1_UMC_INSTANCE_NUM		8
++/* total channel instances in one umc block */
++#define UMC_V6_1_TOTAL_CHANNEL_NUM	(UMC_V6_1_CHANNEL_INSTANCE_NUM * UMC_V6_1_UMC_INSTANCE_NUM)
+ /* UMC regiser per channel offset */
+ #define UMC_V6_1_PER_CHANNEL_OFFSET		0x800
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3247-drm-amdgpu-initialize-new-parameters-and-functions-f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3247-drm-amdgpu-initialize-new-parameters-and-functions-f.patch
new file mode 100644
index 00000000..8e54744a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3247-drm-amdgpu-initialize-new-parameters-and-functions-f.patch
@@ -0,0 +1,86 @@
+From b31dcf8604c639c2d7c2db273b8fb0c37ae0922f Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Mon, 29 Jul 2019 14:28:35 +0800
+Subject: [PATCH 3247/4256] drm/amdgpu: initialize new parameters and functions
+ for amdgpu_umc structure
+
+add initialization for new members of amdgpu_umc structure
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  7 +++++--
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 10 +++++++++-
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.h |  3 +++
+ 3 files changed, 17 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 7f4da9254dfb..2f72968ec566 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -628,8 +628,11 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
+ {
+ 	switch (adev->asic_type) {
+ 	case CHIP_VEGA20:
+-		adev->umc.max_ras_err_cnt_per_query =
+-			UMC_V6_1_UMC_INSTANCE_NUM * UMC_V6_1_CHANNEL_INSTANCE_NUM;
++		adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
++		adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
++		adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
++		adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET;
++		adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
+ 		adev->umc.funcs = &umc_v6_1_funcs;
+ 		break;
+ 	default:
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+index 035e4fea472c..9ba015d7eb57 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+@@ -41,7 +41,7 @@
+ /* offset in 256B block */
+ #define OFFSET_IN_256B_BLOCK(addr)		((addr) & 0xffULL)
+ 
+-static uint32_t
++const uint32_t
+ 	umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM] = {
+ 		{2, 18, 11, 27},	{4, 20, 13, 29},
+ 		{1, 17, 8, 24},		{7, 23, 14, 30},
+@@ -235,7 +235,15 @@ static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
+ 	umc_v6_1_disable_umc_index_mode(adev);
+ }
+ 
++static void umc_v6_1_ras_init(struct amdgpu_device *adev)
++{
++
++}
++
+ const struct amdgpu_umc_funcs umc_v6_1_funcs = {
++	.ras_init = umc_v6_1_ras_init,
+ 	.query_ras_error_count = umc_v6_1_query_ras_error_count,
+ 	.query_ras_error_address = umc_v6_1_query_ras_error_address,
++	.enable_umc_index_mode = umc_v6_1_enable_umc_index_mode,
++	.disable_umc_index_mode = umc_v6_1_disable_umc_index_mode,
+ };
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
+index bddaf14a77f9..ad4598c0e495 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
+@@ -24,6 +24,7 @@
+ #define __UMC_V6_1_H__
+ 
+ #include "soc15_common.h"
++#include "amdgpu.h"
+ 
+ /* HBM  Memory Channel Width */
+ #define UMC_V6_1_HBM_MEMORY_CHANNEL_WIDTH	128
+@@ -37,5 +38,7 @@
+ #define UMC_V6_1_PER_CHANNEL_OFFSET		0x800
+ 
+ extern const struct amdgpu_umc_funcs umc_v6_1_funcs;
++extern const uint32_t
++	umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM];
+ 
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3248-drm-amdgpu-add-macro-of-umc-for-each-channel.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3248-drm-amdgpu-add-macro-of-umc-for-each-channel.patch
new file mode 100644
index 00000000..4f90532a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3248-drm-amdgpu-add-macro-of-umc-for-each-channel.patch
@@ -0,0 +1,52 @@
+From 910bb3b65f4b3f4dd2f870ea86fcab335a84eda5 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Mon, 29 Jul 2019 14:50:35 +0800
+Subject: [PATCH 3248/4256] drm/amdgpu: add macro of umc for each channel
+
+common function for all umc versions, loop for each umc channel is
+a frequent used operation in umc block, define it as a macro to
+simplify code
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+index 2604f5076867..9efdd66279e5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+@@ -21,6 +21,29 @@
+ #ifndef __AMDGPU_UMC_H__
+ #define __AMDGPU_UMC_H__
+ 
++/*
++ * void (*func)(struct amdgpu_device *adev, struct ras_err_data *err_data,
++ *				uint32_t umc_reg_offset, uint32_t channel_index)
++ */
++#define amdgpu_umc_for_each_channel(func)	\
++	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;	\
++	uint32_t umc_inst, channel_inst, umc_reg_offset, channel_index;	\
++	for (umc_inst = 0; umc_inst < adev->umc.umc_inst_num; umc_inst++) {	\
++		/* enable the index mode to query eror count per channel */	\
++		adev->umc.funcs->enable_umc_index_mode(adev, umc_inst);	\
++		for (channel_inst = 0;	\
++			channel_inst < adev->umc.channel_inst_num;	\
++			channel_inst++) {	\
++			/* calc the register offset according to channel instance */	\
++			umc_reg_offset = adev->umc.channel_offs * channel_inst;	\
++			/* get channel index of interleaved memory */	\
++			channel_index = adev->umc.channel_idx_tbl[	\
++				umc_inst * adev->umc.channel_inst_num + channel_inst];	\
++			(func)(adev, err_data, umc_reg_offset, channel_index);	\
++		}	\
++	}	\
++	adev->umc.funcs->disable_umc_index_mode(adev);
++
+ struct amdgpu_umc_funcs {
+ 	void (*ras_init)(struct amdgpu_device *adev);
+ 	void (*query_ras_error_count)(struct amdgpu_device *adev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3249-drm-amdgpu-apply-umc_for_each_channel-macro-to-umc_6.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3249-drm-amdgpu-apply-umc_for_each_channel-macro-to-umc_6.patch
new file mode 100644
index 00000000..5923718d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3249-drm-amdgpu-apply-umc_for_each_channel-macro-to-umc_6.patch
@@ -0,0 +1,139 @@
+From 27eb00df7e5058be92235a96d3ec189310060e7f Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 1 Aug 2019 11:37:25 +0800
+Subject: [PATCH 3249/4256] drm/amdgpu: apply umc_for_each_channel macro to
+ umc_6_1
+
+use umc_for_each_channel to make code simpler
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 84 +++++++++------------------
+ 1 file changed, 28 insertions(+), 56 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+index 9ba015d7eb57..5747a0252624 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+@@ -142,46 +142,39 @@ static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev
+ 		*error_count += 1;
+ }
+ 
++static void umc_v6_1_query_error_count(struct amdgpu_device *adev,
++					   struct ras_err_data *err_data, uint32_t umc_reg_offset,
++					   uint32_t channel_index)
++{
++	umc_v6_1_query_correctable_error_count(adev, umc_reg_offset,
++						   &(err_data->ce_count));
++	umc_v6_1_querry_uncorrectable_error_count(adev, umc_reg_offset,
++						  &(err_data->ue_count));
++}
++
+ static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev,
+ 					   void *ras_error_status)
+ {
+-	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+-	uint32_t umc_inst, channel_inst, umc_reg_offset, mc_umc_status_addr;
+-
+-	mc_umc_status_addr =
+-		SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
+-
+-	for (umc_inst = 0; umc_inst < UMC_V6_1_UMC_INSTANCE_NUM; umc_inst++) {
+-		/* enable the index mode to query eror count per channel */
+-		umc_v6_1_enable_umc_index_mode(adev, umc_inst);
+-		for (channel_inst = 0; channel_inst < UMC_V6_1_CHANNEL_INSTANCE_NUM; channel_inst++) {
+-			/* calc the register offset according to channel instance */
+-			umc_reg_offset = UMC_V6_1_PER_CHANNEL_OFFSET * channel_inst;
+-			umc_v6_1_query_correctable_error_count(adev, umc_reg_offset,
+-							       &(err_data->ce_count));
+-			umc_v6_1_querry_uncorrectable_error_count(adev, umc_reg_offset,
+-								  &(err_data->ue_count));
+-			/* clear umc status */
+-			WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
+-		}
+-	}
+-	umc_v6_1_disable_umc_index_mode(adev);
++	amdgpu_umc_for_each_channel(umc_v6_1_query_error_count);
+ }
+ 
+ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
+-					 uint32_t umc_reg_offset, uint32_t channel_index,
+-					 struct ras_err_data *err_data)
++					 struct ras_err_data *err_data,
++					 uint32_t umc_reg_offset, uint32_t channel_index)
+ {
+-	uint32_t lsb;
++	uint32_t lsb, mc_umc_status_addr;
+ 	uint64_t mc_umc_status, err_addr;
+-	uint32_t mc_umc_status_addr;
++
++	mc_umc_status_addr =
++		SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
+ 
+ 	/* skip error address process if -ENOMEM */
+-	if (!err_data->err_addr)
++	if (!err_data->err_addr) {
++		/* clear umc status */
++		WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
+ 		return;
++	}
+ 
+-	mc_umc_status_addr =
+-		SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
+ 	mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
+ 
+ 	/* calculate error address if ue/ce error is detected */
+@@ -197,42 +190,21 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
+ 
+ 		/* translate umc channel address to soc pa, 3 parts are included */
+ 		err_data->err_addr[err_data->err_addr_cnt] =
+-						ADDR_OF_8KB_BLOCK(err_addr)
+-						| ADDR_OF_256B_BLOCK(channel_index)
+-						| OFFSET_IN_256B_BLOCK(err_addr);
++						ADDR_OF_8KB_BLOCK(err_addr) |
++						ADDR_OF_256B_BLOCK(channel_index) |
++						OFFSET_IN_256B_BLOCK(err_addr);
+ 
+ 		err_data->err_addr_cnt++;
+ 	}
++
++	/* clear umc status */
++	WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
+ }
+ 
+ static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
+ 					     void *ras_error_status)
+ {
+-	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+-	uint32_t umc_inst, channel_inst, umc_reg_offset;
+-	uint32_t channel_index, mc_umc_status_addr;
+-
+-	mc_umc_status_addr =
+-		SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
+-
+-	for (umc_inst = 0; umc_inst < UMC_V6_1_UMC_INSTANCE_NUM; umc_inst++) {
+-		/* enable the index mode to query eror count per channel */
+-		umc_v6_1_enable_umc_index_mode(adev, umc_inst);
+-		for (channel_inst = 0; channel_inst < UMC_V6_1_CHANNEL_INSTANCE_NUM; channel_inst++) {
+-			/* calc the register offset according to channel instance */
+-			umc_reg_offset = UMC_V6_1_PER_CHANNEL_OFFSET * channel_inst;
+-			/* get channel index of interleaved memory */
+-			channel_index = umc_v6_1_channel_idx_tbl[umc_inst][channel_inst];
+-
+-			umc_v6_1_query_error_address(adev, umc_reg_offset,
+-						     channel_index, err_data);
+-
+-			/* clear umc status */
+-			WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
+-		}
+-	}
+-
+-	umc_v6_1_disable_umc_index_mode(adev);
++	amdgpu_umc_for_each_channel(umc_v6_1_query_error_address);
+ }
+ 
+ static void umc_v6_1_ras_init(struct amdgpu_device *adev)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3250-drm-amdgpu-add-error-address-query-for-umc-ras.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3250-drm-amdgpu-add-error-address-query-for-umc-ras.patch
new file mode 100644
index 00000000..5d04f9e9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3250-drm-amdgpu-add-error-address-query-for-umc-ras.patch
@@ -0,0 +1,50 @@
+From 9d0ee84afd1ea064452ebfd85300739b39a9bcf6 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 1 Aug 2019 11:41:39 +0800
+Subject: [PATCH 3250/4256] drm/amdgpu: add error address query for umc ras
+
+umc error address query can get ce/ue error address and clear error
+status
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 +++++
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 5 +++++
+ 2 files changed, 10 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index a96b0f17c619..094c27000b83 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -599,6 +599,11 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev,
+ 	case AMDGPU_RAS_BLOCK__UMC:
+ 		if (adev->umc.funcs->query_ras_error_count)
+ 			adev->umc.funcs->query_ras_error_count(adev, &err_data);
++		/* umc query_ras_error_address is also responsible for clearing
++		 * error status
++		 */
++		if (adev->umc.funcs->query_ras_error_address)
++			adev->umc.funcs->query_ras_error_address(adev, &err_data);
+ 		break;
+ 	case AMDGPU_RAS_BLOCK__GFX:
+ 		if (adev->gfx.funcs->query_ras_error_count)
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 2f72968ec566..656cd11ccadf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -245,6 +245,11 @@ static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+ 	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
+ 	if (adev->umc.funcs->query_ras_error_count)
+ 		adev->umc.funcs->query_ras_error_count(adev, err_data);
++	/* umc query_ras_error_address is also responsible for clearing
++	 * error status
++	 */
++	if (adev->umc.funcs->query_ras_error_address)
++		adev->umc.funcs->query_ras_error_address(adev, err_data);
+ 	amdgpu_ras_reset_gpu(adev, 0);
+ 	return AMDGPU_RAS_UE;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3251-drm-amdgpu-support-ce-interrupt-in-ras-module.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3251-drm-amdgpu-support-ce-interrupt-in-ras-module.patch
new file mode 100644
index 00000000..8a4c233b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3251-drm-amdgpu-support-ce-interrupt-in-ras-module.patch
@@ -0,0 +1,49 @@
+From ab56d79eeae10a3013d0d83b36d819ab45e81576 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Mon, 29 Jul 2019 16:04:33 +0800
+Subject: [PATCH 3251/4256] drm/amdgpu: support ce interrupt in ras module
+
+correctable error can also trigger interrupt in some ras blocks
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 094c27000b83..4a0dc5269ddf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1047,12 +1047,12 @@ static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
+ 			 * the error.
+ 			 */
+ 			if (ret == AMDGPU_RAS_UE) {
++				/* these counts could be left as 0 if
++				 * some blocks do not count error number
++				 */
+ 				obj->err_data.ue_count += err_data.ue_count;
++				obj->err_data.ce_count += err_data.ce_count;
+ 			}
+-			/* Might need get ce count by register, but not all IP
+-			 * saves ce count, some IP just use one bit or two bits
+-			 * to indicate ce happened.
+-			 */
+ 		}
+ 	}
+ }
+@@ -1549,6 +1549,10 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
+ 	if (amdgpu_ras_fs_init(adev))
+ 		goto fs_out;
+ 
++	/* ras init for each ras block */
++	if (adev->umc.funcs->ras_init)
++		adev->umc.funcs->ras_init(adev);
++
+ 	DRM_INFO("RAS INFO: ras initialized successfully, "
+ 			"hardware ability[%x] ras_mask[%x]\n",
+ 			con->hw_supported, con->supported);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3252-drm-amdgpu-implement-umc-ras-init-function.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3252-drm-amdgpu-implement-umc-ras-init-function.patch
new file mode 100644
index 00000000..1fe98eb9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3252-drm-amdgpu-implement-umc-ras-init-function.patch
@@ -0,0 +1,82 @@
+From 9d7f42f7e58ded80129bd6b351d3a022d54d34e4 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Mon, 29 Jul 2019 17:01:39 +0800
+Subject: [PATCH 3252/4256] drm/amdgpu: implement umc ras init function
+
+enable umc ce interrupt and initialize ecc error count
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 32 +++++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.h |  7 ++++++
+ 2 files changed, 39 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+index 5747a0252624..0ab2e96b4f77 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+@@ -207,9 +207,41 @@ static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
+ 	amdgpu_umc_for_each_channel(umc_v6_1_query_error_address);
+ }
+ 
++static void umc_v6_1_ras_init_per_channel(struct amdgpu_device *adev,
++					 struct ras_err_data *err_data,
++					 uint32_t umc_reg_offset, uint32_t channel_index)
++{
++	uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
++	uint32_t ecc_err_cnt_addr;
++
++	ecc_err_cnt_sel_addr =
++		SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
++	ecc_err_cnt_addr =
++		SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
++
++	/* select the lower chip and check the error count */
++	ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset);
++	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
++					EccErrCntCsSel, 0);
++	/* set ce error interrupt type to APIC based interrupt */
++	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
++					EccErrInt, 0x1);
++	WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
++	/* set error count to initial value */
++	WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
++
++	/* select the higher chip and check the err counter */
++	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
++					EccErrCntCsSel, 1);
++	WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
++	WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
++}
++
+ static void umc_v6_1_ras_init(struct amdgpu_device *adev)
+ {
++	void *ras_error_status = NULL;
+ 
++	amdgpu_umc_for_each_channel(umc_v6_1_ras_init_per_channel);
+ }
+ 
+ const struct amdgpu_umc_funcs umc_v6_1_funcs = {
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
+index ad4598c0e495..dab9cbd292c5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
+@@ -37,6 +37,13 @@
+ /* UMC regiser per channel offset */
+ #define UMC_V6_1_PER_CHANNEL_OFFSET		0x800
+ 
++/* EccErrCnt max value */
++#define UMC_V6_1_CE_CNT_MAX		0xffff
++/* umc ce interrupt threshold */
++#define UMC_V6_1_CE_INT_THRESHOLD	0xffff
++/* umc ce count initial value */
++#define UMC_V6_1_CE_CNT_INIT	(UMC_V6_1_CE_CNT_MAX - UMC_V6_1_CE_INT_THRESHOLD)
++
+ extern const struct amdgpu_umc_funcs umc_v6_1_funcs;
+ extern const uint32_t
+ 	umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM];
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3253-drm-amdgpu-update-the-calc-algorithm-of-umc-ecc-erro.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3253-drm-amdgpu-update-the-calc-algorithm-of-umc-ecc-erro.patch
new file mode 100644
index 00000000..ecd50f0c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3253-drm-amdgpu-update-the-calc-algorithm-of-umc-ecc-erro.patch
@@ -0,0 +1,48 @@
+From d824d5a05162198195d9bbcaa8ae1fd8cde628e2 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Mon, 29 Jul 2019 17:19:57 +0800
+Subject: [PATCH 3253/4256] drm/amdgpu: update the calc algorithm of umc ecc
+ error count
+
+the initial value of ecc error count can be adjusted
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 10 ++++++----
+ 1 file changed, 6 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+index 0ab2e96b4f77..64df37b860dd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+@@ -98,9 +98,10 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
+ 	WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
+ 	ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset);
+ 	*error_count +=
+-		REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt);
++		(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
++		 UMC_V6_1_CE_CNT_INIT);
+ 	/* clear the lower chip err count */
+-	WREG32(ecc_err_cnt_addr + umc_reg_offset, 0);
++	WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
+ 
+ 	/* select the higher chip and check the err counter */
+ 	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
+@@ -108,9 +109,10 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
+ 	WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
+ 	ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset);
+ 	*error_count +=
+-		REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt);
++		(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
++		 UMC_V6_1_CE_CNT_INIT);
+ 	/* clear the higher chip err count */
+-	WREG32(ecc_err_cnt_addr + umc_reg_offset, 0);
++	WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
+ 
+ 	/* check for SRAM correctable error
+ 	  MCUMC_STATUS is a 64 bit register */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3254-drm-amdgpu-only-uncorrectable-error-needs-gpu-reset.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3254-drm-amdgpu-only-uncorrectable-error-needs-gpu-reset.patch
new file mode 100644
index 00000000..b414e0a9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3254-drm-amdgpu-only-uncorrectable-error-needs-gpu-reset.patch
@@ -0,0 +1,37 @@
+From a4c63985afc13da200995bd6994088b58675f6c7 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 1 Aug 2019 12:52:54 +0800
+Subject: [PATCH 3254/4256] drm/amdgpu: only uncorrectable error needs gpu
+ reset
+
+we only read error information for correctable error in interrupt
+handler, gpu reset is unnecessary since there is no data lost
+in correctable error
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 656cd11ccadf..fd23d9081286 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -250,7 +250,11 @@ static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+ 	 */
+ 	if (adev->umc.funcs->query_ras_error_address)
+ 		adev->umc.funcs->query_ras_error_address(adev, err_data);
+-	amdgpu_ras_reset_gpu(adev, 0);
++
++	/* only uncorrectable error needs gpu reset */
++	if (err_data->ue_count)
++		amdgpu_ras_reset_gpu(adev, 0);
++
+ 	return AMDGPU_RAS_UE;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3255-drm-amdgpu-replace-AMDGPU_RAS_UE-with-AMDGPU_RAS_SUC.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3255-drm-amdgpu-replace-AMDGPU_RAS_UE-with-AMDGPU_RAS_SUC.patch
new file mode 100644
index 00000000..1c7d4482
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3255-drm-amdgpu-replace-AMDGPU_RAS_UE-with-AMDGPU_RAS_SUC.patch
@@ -0,0 +1,75 @@
+From 8162f784baf1b1f5aaae1d25b75726ff6bc5df37 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 1 Aug 2019 17:30:35 +0800
+Subject: [PATCH 3255/4256] drm/amdgpu: replace AMDGPU_RAS_UE with
+ AMDGPU_RAS_SUCCESS
+
+ce can also trigger interrupt, and even both ce and ue error can be
+found in one ras query, distinguishing between ce and ue in interrupt
+handler is uncessary.
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Suggested-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 2 +-
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 2 +-
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c  | 2 +-
+ 4 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 4a0dc5269ddf..d2e8a85f6e38 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1046,7 +1046,7 @@ static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
+ 			 * But leave IP do that recovery, here we just dispatch
+ 			 * the error.
+ 			 */
+-			if (ret == AMDGPU_RAS_UE) {
++			if (ret == AMDGPU_RAS_SUCCESS) {
+ 				/* these counts could be left as 0 if
+ 				 * some blocks do not count error number
+ 				 */
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 51de6268c177..6168d1df31d7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -5661,7 +5661,7 @@ static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+ 	if (adev->gfx.funcs->query_ras_error_count)
+ 		adev->gfx.funcs->query_ras_error_count(adev, err_data);
+ 	amdgpu_ras_reset_gpu(adev, 0);
+-	return AMDGPU_RAS_UE;
++	return AMDGPU_RAS_SUCCESS;
+ }
+ 
+ static const struct {
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index fd23d9081286..41c4f6fea273 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -255,7 +255,7 @@ static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+ 	if (err_data->ue_count)
+ 		amdgpu_ras_reset_gpu(adev, 0);
+ 
+-	return AMDGPU_RAS_UE;
++	return AMDGPU_RAS_SUCCESS;
+ }
+ 
+ static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev,
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index efbb6f22fefc..3cfef19aadd2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1984,7 +1984,7 @@ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
+ 
+ 	amdgpu_ras_reset_gpu(adev, 0);
+ 
+-	return AMDGPU_RAS_UE;
++	return AMDGPU_RAS_SUCCESS;
+ }
+ 
+ static int sdma_v4_0_process_ecc_irq(struct amdgpu_device *adev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3256-drm-amd-powerplay-guard-consistency-between-CPU-copy.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3256-drm-amd-powerplay-guard-consistency-between-CPU-copy.patch
new file mode 100644
index 00000000..cd74b892
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3256-drm-amd-powerplay-guard-consistency-between-CPU-copy.patch
@@ -0,0 +1,150 @@
+From 62155a3e75c77ce77a20758d53508fdecbf76ec1 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 30 Jul 2019 16:39:45 +0800
+Subject: [PATCH 3256/4256] drm/amd/powerplay: guard consistency between CPU
+ copy and local VRAM
+
+This can prevent CPU to use the out-dated copy.
+
+Change-Id: Ia18e89a923e3522e01717aa4d5ba35f8f4f20763
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c           | 4 ++++
+ drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c  | 4 ++++
+ drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 4 ++++
+ drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c | 4 ++++
+ drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c | 8 ++++++++
+ 5 files changed, 24 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 02077604a43a..9ba24ac54502 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -453,6 +453,7 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int
+ 		     void *table_data, bool drv2smu)
+ {
+ 	struct smu_table_context *smu_table = &smu->smu_table;
++	struct amdgpu_device *adev = smu->adev;
+ 	struct smu_table *table = NULL;
+ 	int ret = 0;
+ 	int table_id = smu_table_get_index(smu, table_index);
+@@ -480,6 +481,9 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int
+ 	if (ret)
+ 		return ret;
+ 
++	/* flush hdp cache */
++	adev->nbio_funcs->hdp_flush(adev, NULL);
++
+ 	if (!drv2smu)
+ 		memcpy(table_data, table->cpu_addr, table->size);
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
+index ca660351a363..59b11ac5b53b 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
+@@ -116,6 +116,7 @@ static int smu10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
+ {
+ 	struct smu10_smumgr *priv =
+ 			(struct smu10_smumgr *)(hwmgr->smu_backend);
++	struct amdgpu_device *adev = hwmgr->adev;
+ 
+ 	PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
+ 			"Invalid SMU Table ID!", return -EINVAL;);
+@@ -133,6 +134,9 @@ static int smu10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
+ 			PPSMC_MSG_TransferTableSmu2Dram,
+ 			priv->smu_tables.entry[table_id].table_id);
+ 
++	/* flush hdp cache */
++	adev->nbio_funcs->hdp_flush(adev, NULL);
++
+ 	memcpy(table, (uint8_t *)priv->smu_tables.entry[table_id].table,
+ 			priv->smu_tables.entry[table_id].size);
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+index 7bfef8d85cda..8e07fc1fb9ce 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+@@ -37,6 +37,7 @@ static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
+ 		uint8_t *table, int16_t table_id)
+ {
+ 	struct vega10_smumgr *priv = hwmgr->smu_backend;
++	struct amdgpu_device *adev = hwmgr->adev;
+ 
+ 	PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
+ 			"Invalid SMU Table ID!", return -EINVAL);
+@@ -54,6 +55,9 @@ static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
+ 			PPSMC_MSG_TransferTableSmu2Dram,
+ 			priv->smu_tables.entry[table_id].table_id);
+ 
++	/* flush hdp cache */
++	adev->nbio_funcs->hdp_flush(adev, NULL);
++
+ 	memcpy(table, priv->smu_tables.entry[table_id].table,
+ 			priv->smu_tables.entry[table_id].size);
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
+index 9ad07a91c38b..c11dae720a35 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
+@@ -42,6 +42,7 @@ static int vega12_copy_table_from_smc(struct pp_hwmgr *hwmgr,
+ {
+ 	struct vega12_smumgr *priv =
+ 			(struct vega12_smumgr *)(hwmgr->smu_backend);
++	struct amdgpu_device *adev = hwmgr->adev;
+ 
+ 	PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
+ 			"Invalid SMU Table ID!", return -EINVAL);
+@@ -64,6 +65,9 @@ static int vega12_copy_table_from_smc(struct pp_hwmgr *hwmgr,
+ 			"[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
+ 			return -EINVAL);
+ 
++	/* flush hdp cache */
++	adev->nbio_funcs->hdp_flush(adev, NULL);
++
+ 	memcpy(table, priv->smu_tables.entry[table_id].table,
+ 			priv->smu_tables.entry[table_id].size);
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
+index 957446cf467e..3e97b83950dc 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
+@@ -163,6 +163,7 @@ static int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr,
+ {
+ 	struct vega20_smumgr *priv =
+ 			(struct vega20_smumgr *)(hwmgr->smu_backend);
++	struct amdgpu_device *adev = hwmgr->adev;
+ 	int ret = 0;
+ 
+ 	PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
+@@ -187,6 +188,9 @@ static int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr,
+ 			"[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
+ 			return ret);
+ 
++	/* flush hdp cache */
++	adev->nbio_funcs->hdp_flush(adev, NULL);
++
+ 	memcpy(table, priv->smu_tables.entry[table_id].table,
+ 			priv->smu_tables.entry[table_id].size);
+ 
+@@ -266,6 +270,7 @@ int vega20_get_activity_monitor_coeff(struct pp_hwmgr *hwmgr,
+ {
+ 	struct vega20_smumgr *priv =
+ 			(struct vega20_smumgr *)(hwmgr->smu_backend);
++	struct amdgpu_device *adev = hwmgr->adev;
+ 	int ret = 0;
+ 
+ 	PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
+@@ -284,6 +289,9 @@ int vega20_get_activity_monitor_coeff(struct pp_hwmgr *hwmgr,
+ 			"[GetActivityMonitor] Attempt to Transfer Table From SMU Failed!",
+ 			return ret);
+ 
++	/* flush hdp cache */
++	adev->nbio_funcs->hdp_flush(adev, NULL);
++
+ 	memcpy(table, priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table,
+ 			priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].size);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3257-drm-amd-powerplay-support-power-profile-retrieval-an.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3257-drm-amd-powerplay-support-power-profile-retrieval-an.patch
new file mode 100644
index 00000000..a7a16404
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3257-drm-amd-powerplay-support-power-profile-retrieval-an.patch
@@ -0,0 +1,110 @@
+From 4993641cd36b5e471eca37904359b2bbf52867bf Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 29 Jul 2019 15:17:27 +0800
+Subject: [PATCH 3257/4256] drm/amd/powerplay: support power profile retrieval
+ and setting on arcturus
+
+Enable arcturus power profile retrieval and setting.
+
+Change-Id: I85447ba9ca7de8e197840f76ce3745363c4133a6
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 74 ++++++++++++++++++++
+ 1 file changed, 74 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index c9145c190d9f..bf373d5b0e38 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -1373,6 +1373,78 @@ static int arcturus_get_power_limit(struct smu_context *smu,
+ 	return 0;
+ }
+ 
++static int arcturus_get_power_profile_mode(struct smu_context *smu,
++					   char *buf)
++{
++	static const char *profile_name[] = {
++					"BOOTUP_DEFAULT",
++					"3D_FULL_SCREEN",
++					"POWER_SAVING",
++					"VIDEO",
++					"VR",
++					"COMPUTE",
++					"CUSTOM"};
++	uint32_t i, size = 0;
++	int16_t workload_type = 0;
++
++	if (!smu->pm_enabled || !buf)
++		return -EINVAL;
++
++	for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
++		/*
++		 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
++		 * Not all profile modes are supported on arcturus.
++		 */
++		workload_type = smu_workload_get_type(smu, i);
++		if (workload_type < 0)
++			continue;
++
++		size += sprintf(buf + size, "%2d %14s%s\n",
++			i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
++	}
++
++	return size;
++}
++
++static int arcturus_set_power_profile_mode(struct smu_context *smu,
++					   long *input,
++					   uint32_t size)
++{
++	int workload_type = 0;
++	uint32_t profile_mode = input[size];
++	int ret = 0;
++
++	if (!smu->pm_enabled)
++		return -EINVAL;
++
++	if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
++		pr_err("Invalid power profile mode %d\n", profile_mode);
++		return -EINVAL;
++	}
++
++	/*
++	 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
++	 * Not all profile modes are supported on arcturus.
++	 */
++	workload_type = smu_workload_get_type(smu, profile_mode);
++	if (workload_type < 0) {
++		pr_err("Unsupported power profile mode %d on arcturus\n", profile_mode);
++		return -EINVAL;
++	}
++
++	ret = smu_send_smc_msg_with_param(smu,
++					  SMU_MSG_SetWorkloadMask,
++					  1 << workload_type);
++	if (ret) {
++		pr_err("Fail to set workload type %d\n", workload_type);
++		return ret;
++	}
++
++	smu->power_profile_mode = profile_mode;
++
++	return 0;
++}
++
+ static void arcturus_dump_pptable(struct smu_context *smu)
+ {
+ 	struct smu_table_context *table_context = &smu->smu_table;
+@@ -1836,6 +1908,8 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 	.force_dpm_limit_value = arcturus_force_dpm_limit_value,
+ 	.unforce_dpm_levels = arcturus_unforce_dpm_levels,
+ 	.get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
++	.get_power_profile_mode = arcturus_get_power_profile_mode,
++	.set_power_profile_mode = arcturus_set_power_profile_mode,
+ 	/* debug (internal used) */
+ 	.dump_pptable = arcturus_dump_pptable,
+ 	.get_power_limit = arcturus_get_power_limit,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3258-drm-amd-powerplay-enable-SW-SMU-power-profile-switch.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3258-drm-amd-powerplay-enable-SW-SMU-power-profile-switch.patch
new file mode 100644
index 00000000..87a93d8d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3258-drm-amd-powerplay-enable-SW-SMU-power-profile-switch.patch
@@ -0,0 +1,100 @@
+From 5bb0060dffd82183d4e8c537abfd2fda95a5a158 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Wed, 31 Jul 2019 10:34:36 +0800
+Subject: [PATCH 3258/4256] drm/amd/powerplay: enable SW SMU power profile
+ switch support in KFD
+
+Hook up the SW SMU power profile switch in KFD routine.
+
+Change-Id: I41e53762cdc7504285de89f30e3e6e2bb396b953
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c    |  8 +++--
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 36 +++++++++++++++++++
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  3 ++
+ 3 files changed, 45 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+index bb2374842b82..34529ee28d4d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+@@ -671,8 +671,12 @@ void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+ 
+-	if (adev->powerplay.pp_funcs &&
+-	    adev->powerplay.pp_funcs->switch_power_profile)
++	if (is_support_sw_smu(adev))
++		smu_switch_power_profile(&adev->smu,
++					 PP_SMC_POWER_PROFILE_COMPUTE,
++					 !idle);
++	else if (adev->powerplay.pp_funcs &&
++		 adev->powerplay.pp_funcs->switch_power_profile)
+ 		amdgpu_dpm_switch_power_profile(adev,
+ 						PP_SMC_POWER_PROFILE_COMPUTE,
+ 						!idle);
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 9ba24ac54502..f928c5f97d07 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1679,6 +1679,42 @@ int smu_handle_task(struct smu_context *smu,
+ 	return ret;
+ }
+ 
++int smu_switch_power_profile(struct smu_context *smu,
++			     enum PP_SMC_POWER_PROFILE type,
++			     bool en)
++{
++	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
++	long workload;
++	uint32_t index;
++
++	if (!smu->pm_enabled)
++		return -EINVAL;
++
++	if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
++		return -EINVAL;
++
++	mutex_lock(&smu->mutex);
++
++	if (!en) {
++		smu->workload_mask &= ~(1 << smu->workload_prority[type]);
++		index = fls(smu->workload_mask);
++		index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
++		workload = smu->workload_setting[index];
++	} else {
++		smu->workload_mask |= (1 << smu->workload_prority[type]);
++		index = fls(smu->workload_mask);
++		index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
++		workload = smu->workload_setting[index];
++	}
++
++	if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
++		smu_set_power_profile_mode(smu, &workload, 0);
++
++	mutex_unlock(&smu->mutex);
++
++	return 0;
++}
++
+ enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
+ {
+ 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 2579b002616c..f813072ab9e4 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -788,6 +788,9 @@ extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, b
+ extern int smu_handle_task(struct smu_context *smu,
+ 			   enum amd_dpm_forced_level level,
+ 			   enum amd_pp_task task_id);
++int smu_switch_power_profile(struct smu_context *smu,
++			     enum PP_SMC_POWER_PROFILE type,
++			     bool en);
+ int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version);
+ int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
+ 			      uint16_t level, uint32_t *value);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3259-drm-amdgpu-removed-duplicate-line.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3259-drm-amdgpu-removed-duplicate-line.patch
new file mode 100644
index 00000000..1bb2659b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3259-drm-amdgpu-removed-duplicate-line.patch
@@ -0,0 +1,30 @@
+From 72c9843c9b4acb53608e6453979e496fbe9e17ee Mon Sep 17 00:00:00 2001
+From: John Clements <John.Clements@amd.com>
+Date: Wed, 31 Jul 2019 16:11:38 +0800
+Subject: [PATCH 3259/4256] drm/amdgpu: removed duplicate line
+
+Remove duplicate break.
+
+Change-Id: I8da4b70bb2c84723075136597c2e5bcdee0ec560
+Signed-off-by: John Clements <John.Clements@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 6168d1df31d7..bc8f35853196 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -1330,7 +1330,6 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
+ 		else
+ 			chip_name = "raven";
+ 		break;
+-		break;
+ 	case CHIP_ARCTURUS:
+ 		chip_name = "arcturus";
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3260-drm-amdgpu-add-PSP-SW-init-support-for-Arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3260-drm-amdgpu-add-PSP-SW-init-support-for-Arcturus.patch
new file mode 100644
index 00000000..0fd42b3e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3260-drm-amdgpu-add-PSP-SW-init-support-for-Arcturus.patch
@@ -0,0 +1,52 @@
+From a48357e5f60d47d83f293812f3e3a2d5ca43d6ac Mon Sep 17 00:00:00 2001
+From: John Clements <John.Clements@amd.com>
+Date: Thu, 1 Aug 2019 18:05:50 +0800
+Subject: [PATCH 3260/4256] drm/amdgpu: add PSP SW init support for Arcturus
+
+Add arcturus cases to psp init sewquence.
+
+Change-Id: I99406d62a180b3e0ca89a8aac2d0736a18c4f408
+Signed-off-by: John Clements <John.Clements@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c  | 3 +++
+ 2 files changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index f54fa7b6c3bf..1c0a1e2dba78 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -54,6 +54,7 @@ static int psp_early_init(void *handle)
+ 		psp->autoload_supported = false;
+ 		break;
+ 	case CHIP_VEGA20:
++	case CHIP_ARCTURUS:
+ 		psp_v11_0_set_psp_funcs(psp);
+ 		psp->autoload_supported = false;
+ 		break;
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index 3b8d8a89b1b4..6e50c7bcf06d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -44,6 +44,8 @@ MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
+ MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
+ MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
+ MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
++MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
++MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
+ 
+ /* address block */
+ #define smnMP1_FIRMWARE_FLAGS		0x3010024
+@@ -172,6 +174,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
+ 		break;
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_ARCTURUS:
+ 		break;
+ 	default:
+ 		BUG();
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3261-drm-amdgpu-add-PSP-KDB-loading-support-for-Arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3261-drm-amdgpu-add-PSP-KDB-loading-support-for-Arcturus.patch
new file mode 100644
index 00000000..227c8816
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3261-drm-amdgpu-add-PSP-KDB-loading-support-for-Arcturus.patch
@@ -0,0 +1,98 @@
+From 07530f9e865478bef78a04343d62b18d9732608a Mon Sep 17 00:00:00 2001
+From: John Clements <John.Clements@amd.com>
+Date: Mon, 22 Jul 2019 18:06:58 +0800
+Subject: [PATCH 3261/4256] drm/amdgpu: add PSP KDB loading support for
+ Arcturus
+
+Add support for the arcturus specific psp metadata to the
+amdgpu firmware and properly parse it when loading it.
+
+Change-Id: I3dc6cfc869db9e6f4e25c8918332edb8d80d4f83
+Signed-off-by: John Clements <John.Clements@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 10 ++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h |  9 +++++++++
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c    | 10 ++++++++++
+ 3 files changed, 29 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+index 1ec696858d78..21fe00eef30e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+@@ -269,6 +269,16 @@ void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
+ 			DRM_DEBUG("kdb_size_bytes: %u\n",
+ 				  le32_to_cpu(psp_hdr_v1_1->kdb_size_bytes));
+ 		}
++		if (version_minor == 2) {
++			const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
++				container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
++			DRM_DEBUG("kdb_header_version: %u\n",
++				  le32_to_cpu(psp_hdr_v1_2->kdb_header_version));
++			DRM_DEBUG("kdb_offset_bytes: %u\n",
++				  le32_to_cpu(psp_hdr_v1_2->kdb_offset_bytes));
++			DRM_DEBUG("kdb_size_bytes: %u\n",
++				  le32_to_cpu(psp_hdr_v1_2->kdb_size_bytes));
++		}
+ 	} else {
+ 		DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
+ 			  version_major, version_minor);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+index 2be106e81eda..4f1b167a9394 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+@@ -90,6 +90,15 @@ struct psp_firmware_header_v1_1 {
+ 	uint32_t kdb_size_bytes;
+ };
+ 
++/* version_major=1, version_minor=2 */
++struct psp_firmware_header_v1_2 {
++	struct psp_firmware_header_v1_0 v1_0;
++	uint32_t reserve[3];
++	uint32_t kdb_header_version;
++	uint32_t kdb_offset_bytes;
++	uint32_t kdb_size_bytes;
++};
++
+ /* version_major=1, version_minor=0 */
+ struct ta_firmware_header_v1_0 {
+ 	struct common_firmware_header header;
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index 6e50c7bcf06d..246cb9b75c05 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -65,6 +65,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
+ 	int err = 0;
+         const struct psp_firmware_header_v1_0 *sos_hdr;
+ 	const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
++	const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
+ 	const struct psp_firmware_header_v1_0 *asd_hdr;
+         const struct ta_firmware_header_v1_0 *ta_hdr;
+ 	uint32_t bl_version;
+@@ -81,6 +82,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
+ 	case CHIP_NAVI14:
+ 		chip_name = "navi14";
+ 		break;
++	case CHIP_ARCTURUS:
++		chip_name = "arcturus";
++		break;
+ 	default:
+ 		BUG();
+ 	}
+@@ -122,6 +126,12 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
+ 			adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
+ 					le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
+ 		}
++		if (sos_hdr->header.header_version_minor == 2) {
++			sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
++			adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);
++			adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
++						    le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);
++		}
+ 		break;
+ 	default:
+ 		dev_err(adev->dev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3262-drm-amdgpu-update-PSP-CMD-fail-response-status-print.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3262-drm-amdgpu-update-PSP-CMD-fail-response-status-print.patch
new file mode 100644
index 00000000..ce3ea0a1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3262-drm-amdgpu-update-PSP-CMD-fail-response-status-print.patch
@@ -0,0 +1,34 @@
+From 010a99cb725c033772d595838d2cfb282eb7c94b Mon Sep 17 00:00:00 2001
+From: John Clements <John.Clements@amd.com>
+Date: Thu, 25 Jul 2019 15:29:11 +0800
+Subject: [PATCH 3262/4256] drm/amdgpu: update PSP CMD fail response status
+ print
+
+Print the response in hex with the apprpriate mask.
+
+Change-Id: I83f1a9147778fdcc6e2d246b4b6daf2a857c75a0
+Signed-off-by: John Clements <John.Clements@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 1c0a1e2dba78..0c0f3cb2b627 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -167,8 +167,8 @@ psp_cmd_submit_buf(struct psp_context *psp,
+                 if (ucode)
+                         DRM_WARN("failed to load ucode id (%d) ",
+                                   ucode->ucode_id);
+-                DRM_WARN("psp command failed and response status is (%d)\n",
+-                          psp->cmd_buf_mem->resp.status);
++		DRM_WARN("psp command failed and response status is (0x%X)\n",
++				psp->cmd_buf_mem->resp.status & GFX_CMD_STATUS_MASK);
+ 		if (!timeout) {
+ 			mutex_unlock(&psp->mutex);
+                 	return -EINVAL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3263-drm-amdgpu-disable-MEC2-JT-context-init-for-Arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3263-drm-amdgpu-disable-MEC2-JT-context-init-for-Arcturus.patch
new file mode 100644
index 00000000..6ef45fb9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3263-drm-amdgpu-disable-MEC2-JT-context-init-for-Arcturus.patch
@@ -0,0 +1,46 @@
+From 91c47c1e2c9d4c0f929f1ca5d5f26c24725543fc Mon Sep 17 00:00:00 2001
+From: John Clements <John.Clements@amd.com>
+Date: Wed, 31 Jul 2019 16:11:08 +0800
+Subject: [PATCH 3263/4256] drm/amdgpu: disable MEC2 JT context init for
+ Arcturus
+
+We don't need to handle it like other asics.
+
+Change-Id: I01fc3538b4888b58b90826306c6acb32bd0d26f4
+Signed-off-by: John Clements <John.Clements@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 16 +++++++++++-----
+ 1 file changed, 11 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index bc8f35853196..c04cf92214e1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -1282,11 +1282,17 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev,
+ 			cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
+ 			adev->firmware.fw_size +=
+ 				ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
+-			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
+-			info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
+-			info->fw = adev->gfx.mec2_fw;
+-			adev->firmware.fw_size +=
+-				ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
++
++			/* TODO: Determine if MEC2 JT FW loading can be removed
++				 for all GFX V9 asic and above */
++			if (adev->asic_type != CHIP_ARCTURUS) {
++				info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
++				info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
++				info->fw = adev->gfx.mec2_fw;
++				adev->firmware.fw_size +=
++					ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
++					PAGE_SIZE);
++			}
+ 		}
+ 	}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3264-drm-amdgpu-extend-PSP-FW-loading-support-to-8-SDMA-i.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3264-drm-amdgpu-extend-PSP-FW-loading-support-to-8-SDMA-i.patch
new file mode 100644
index 00000000..9c15393a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3264-drm-amdgpu-extend-PSP-FW-loading-support-to-8-SDMA-i.patch
@@ -0,0 +1,119 @@
+From df778354e7666f3066931e087862b6239aeee5f0 Mon Sep 17 00:00:00 2001
+From: John Clements <John.Clements@amd.com>
+Date: Thu, 1 Aug 2019 17:59:55 +0800
+Subject: [PATCH 3264/4256] drm/amdgpu: extend PSP FW loading support to 8 SDMA
+ instances
+
+Arcturus has 8 instances of SDMA.  Update host to PSP interface
+to handle it.
+
+Change-Id: Id59b66eb98a4f4bef8f345499bbdaa0344cf6c49
+Signed-off-by: John Clements <John.Clements@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c   | 27 ++++++++++++++++++++++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h |  6 +++++
+ drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h   | 11 +++++++--
+ 3 files changed, 41 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 0c0f3cb2b627..fb5d7b8cbd03 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -836,7 +836,6 @@ static int psp_hw_start(struct psp_context *psp)
+ 				"XGMI: Failed to initialize XGMI session\n");
+ 	}
+ 
+-
+ 	if (psp->adev->psp.ta_fw) {
+ 		ret = psp_ras_initialize(psp);
+ 		if (ret)
+@@ -857,6 +856,24 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
+ 	case AMDGPU_UCODE_ID_SDMA1:
+ 		*type = GFX_FW_TYPE_SDMA1;
+ 		break;
++	case AMDGPU_UCODE_ID_SDMA2:
++		*type = GFX_FW_TYPE_SDMA2;
++		break;
++	case AMDGPU_UCODE_ID_SDMA3:
++		*type = GFX_FW_TYPE_SDMA3;
++		break;
++	case AMDGPU_UCODE_ID_SDMA4:
++		*type = GFX_FW_TYPE_SDMA4;
++		break;
++	case AMDGPU_UCODE_ID_SDMA5:
++		*type = GFX_FW_TYPE_SDMA5;
++		break;
++	case AMDGPU_UCODE_ID_SDMA6:
++		*type = GFX_FW_TYPE_SDMA6;
++		break;
++	case AMDGPU_UCODE_ID_SDMA7:
++		*type = GFX_FW_TYPE_SDMA7;
++		break;
+ 	case AMDGPU_UCODE_ID_CP_CE:
+ 		*type = GFX_FW_TYPE_CP_CE;
+ 		break;
+@@ -985,12 +1002,20 @@ static int psp_np_fw_load(struct psp_context *psp)
+ 		if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
+ 		    (psp_smu_reload_quirk(psp) || psp->autoload_supported))
+ 			continue;
++
+ 		if (amdgpu_sriov_vf(adev) &&
+ 		   (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
+ 		    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
++		    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
++		    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
++		    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
++		    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
++		    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
++		    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
+ 		    || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
+ 			/*skip ucode loading in SRIOV VF */
+ 			continue;
++
+ 		if (psp->autoload_supported &&
+ 		    (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
+ 		     ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+index 4f1b167a9394..b34f00d42049 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+@@ -271,6 +271,12 @@ union amdgpu_firmware_header {
+ enum AMDGPU_UCODE_ID {
+ 	AMDGPU_UCODE_ID_SDMA0 = 0,
+ 	AMDGPU_UCODE_ID_SDMA1,
++	AMDGPU_UCODE_ID_SDMA2,
++	AMDGPU_UCODE_ID_SDMA3,
++	AMDGPU_UCODE_ID_SDMA4,
++	AMDGPU_UCODE_ID_SDMA5,
++	AMDGPU_UCODE_ID_SDMA6,
++	AMDGPU_UCODE_ID_SDMA7,
+ 	AMDGPU_UCODE_ID_CP_CE,
+ 	AMDGPU_UCODE_ID_CP_PFP,
+ 	AMDGPU_UCODE_ID_CP_ME,
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
+index 5080a73a95a5..74a9fe8e0cfb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
++++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
+@@ -233,8 +233,15 @@ enum psp_gfx_fw_type {
+ 	GFX_FW_TYPE_RLCP_CAM                        = 46,   /* RLCP CAM                 NV      */
+ 	GFX_FW_TYPE_RLC_SPP_CAM_EXT                 = 47,   /* RLC SPP CAM EXT          NV      */
+ 	GFX_FW_TYPE_RLX6_DRAM_BOOT                  = 48,   /* RLX6 DRAM BOOT           NV      */
+-	GFX_FW_TYPE_VCN0_RAM                        = 49,   /* VCN_RAM  NV */
+-	GFX_FW_TYPE_VCN1_RAM                        = 50,   /* VCN_RAM  NV */
++	GFX_FW_TYPE_VCN0_RAM                        = 49,   /* VCN_RAM                  NV + RN */
++	GFX_FW_TYPE_VCN1_RAM                        = 50,   /* VCN_RAM                  NV + RN */
++	GFX_FW_TYPE_DMUB                            = 51,   /* DMUB                          RN */
++	GFX_FW_TYPE_SDMA2                           = 52,   /* SDMA2                    MI      */
++	GFX_FW_TYPE_SDMA3                           = 53,   /* SDMA3                    MI      */
++	GFX_FW_TYPE_SDMA4                           = 54,   /* SDMA4                    MI      */
++	GFX_FW_TYPE_SDMA5                           = 55,   /* SDMA5                    MI      */
++	GFX_FW_TYPE_SDMA6                           = 56,   /* SDMA6                    MI      */
++	GFX_FW_TYPE_SDMA7                           = 57,   /* SDMA7                    MI      */
+ 	GFX_FW_TYPE_MAX
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3265-drm-amdgpu-update-SDMA-V4-microcode-init.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3265-drm-amdgpu-update-SDMA-V4-microcode-init.patch
new file mode 100644
index 00000000..86f1e776
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3265-drm-amdgpu-update-SDMA-V4-microcode-init.patch
@@ -0,0 +1,179 @@
+From 6a9b87db7e01fffe9a113ac6fce60fc273c030a8 Mon Sep 17 00:00:00 2001
+From: John Clements <John.Clements@amd.com>
+Date: Thu, 1 Aug 2019 15:16:12 +0800
+Subject: [PATCH 3265/4256] drm/amdgpu: update SDMA V4 microcode init
+
+Removed loading duplicate instances of SDMA FW for Arcturus.
+We use a single image for all instances.
+
+Change-Id: I5dd897dec926d4ba65bf9608ca4773b1de9b532b
+Signed-off-by: John Clements <John.Clements@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 110 +++++++++++++++++--------
+ 1 file changed, 75 insertions(+), 35 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 3cfef19aadd2..af80f3782811 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -65,13 +65,6 @@ MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
+ MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
+ MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
+ MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin");
+-MODULE_FIRMWARE("amdgpu/arcturus_sdma1.bin");
+-MODULE_FIRMWARE("amdgpu/arcturus_sdma2.bin");
+-MODULE_FIRMWARE("amdgpu/arcturus_sdma3.bin");
+-MODULE_FIRMWARE("amdgpu/arcturus_sdma4.bin");
+-MODULE_FIRMWARE("amdgpu/arcturus_sdma5.bin");
+-MODULE_FIRMWARE("amdgpu/arcturus_sdma6.bin");
+-MODULE_FIRMWARE("amdgpu/arcturus_sdma7.bin");
+ 
+ #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
+ #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
+@@ -376,6 +369,43 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
+ 	}
+ }
+ 
++static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
++{
++	int err = 0;
++	const struct sdma_firmware_header_v1_0 *hdr;
++
++	err = amdgpu_ucode_validate(sdma_inst->fw);
++	if (err)
++		return err;
++
++	hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
++	sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
++	sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
++
++	if (sdma_inst->feature_version >= 20)
++		sdma_inst->burst_nop = true;
++
++	return 0;
++}
++
++static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < adev->sdma.num_instances; i++) {
++		if (adev->sdma.instance[i].fw != NULL)
++			release_firmware(adev->sdma.instance[i].fw);
++
++		/* arcturus shares the same FW memory across
++		   all SDMA isntances */
++		if (adev->asic_type == CHIP_ARCTURUS)
++			break;
++	}
++
++	memset((void*)adev->sdma.instance, 0,
++		sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
++}
++
+ /**
+  * sdma_v4_0_init_microcode - load ucode images from disk
+  *
+@@ -395,7 +425,6 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
+ 	int err = 0, i;
+ 	struct amdgpu_firmware_info *info = NULL;
+ 	const struct common_firmware_header *header = NULL;
+-	const struct sdma_firmware_header_v1_0 *hdr;
+ 
+ 	DRM_DEBUG("\n");
+ 
+@@ -424,26 +453,42 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
+ 		BUG();
+ 	}
+ 
+-	for (i = 0; i < adev->sdma.num_instances; i++) {
+-		if (i == 0)
+-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
+-		else
++	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
++
++	err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
++	if (err)
++		goto out;
++
++	err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]);
++	if (err)
++		goto out;
++
++	for (i = 1; i < adev->sdma.num_instances; i++) {
++		if (adev->asic_type == CHIP_ARCTURUS) {
++			/* Acturus will leverage the same FW memory
++			   for every SDMA instance */
++			memcpy((void*)&adev->sdma.instance[i],
++			       (void*)&adev->sdma.instance[0],
++			       sizeof(struct amdgpu_sdma_instance));
++		}
++		else {
+ 			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
+-		err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
+-		if (err)
+-			goto out;
+-		err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
+-		if (err)
+-			goto out;
+-		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
+-		adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
+-		adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
+-		if (adev->sdma.instance[i].feature_version >= 20)
+-			adev->sdma.instance[i].burst_nop = true;
+-		DRM_DEBUG("psp_load == '%s'\n",
+-				adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
+-
+-		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
++
++			err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
++			if (err)
++				goto out;
++
++			err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]);
++			if (err)
++				goto out;
++		}
++	}
++
++	DRM_DEBUG("psp_load == '%s'\n",
++		adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
++
++	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
++		for (i = 0; i < adev->sdma.num_instances; i++) {
+ 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
+ 			info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
+ 			info->fw = adev->sdma.instance[i].fw;
+@@ -452,13 +497,11 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
+ 				ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+ 		}
+ 	}
++
+ out:
+ 	if (err) {
+ 		DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
+-		for (i = 0; i < adev->sdma.num_instances; i++) {
+-			release_firmware(adev->sdma.instance[i].fw);
+-			adev->sdma.instance[i].fw = NULL;
+-		}
++		sdma_v4_0_destroy_inst_ctx(adev);
+ 	}
+ 	return err;
+ }
+@@ -1813,10 +1856,7 @@ static int sdma_v4_0_sw_fini(void *handle)
+ 			amdgpu_ring_fini(&adev->sdma.instance[i].page);
+ 	}
+ 
+-	for (i = 0; i < adev->sdma.num_instances; i++) {
+-		release_firmware(adev->sdma.instance[i].fw);
+-		adev->sdma.instance[i].fw = NULL;
+-	}
++	sdma_v4_0_destroy_inst_ctx(adev);
+ 
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3266-drm-amdgpu-add-ip-offset-header-for-navi12-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3266-drm-amdgpu-add-ip-offset-header-for-navi12-v2.patch
new file mode 100644
index 00000000..e51e4a0b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3266-drm-amdgpu-add-ip-offset-header-for-navi12-v2.patch
@@ -0,0 +1,1146 @@
+From f33f0ae6ce95ae30a4b66eb7fd19b400bebdc5cb Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Tue, 14 May 2019 15:18:19 +0800
+Subject: [PATCH 3266/4256] drm/amdgpu: add ip offset header for navi12 (v2)
+
+This adds the absolute offsets of each IP regiser block.
+
+v2: Squash in MP1 update
+
+Change-Id: Id596577a846a09a675840581770461f1192f6617
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/include/navi12_ip_offset.h    | 1119 +++++++++++++++++
+ 1 file changed, 1119 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/include/navi12_ip_offset.h
+
+diff --git a/drivers/gpu/drm/amd/include/navi12_ip_offset.h b/drivers/gpu/drm/amd/include/navi12_ip_offset.h
+new file mode 100644
+index 000000000000..229e8fddfcc1
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/navi12_ip_offset.h
+@@ -0,0 +1,1119 @@
++/*
++ * Copyright (C) 2019  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _navi10_ip_offset_HEADER
++#define _navi10_ip_offset_HEADER
++
++#define MAX_INSTANCE                                       7
++#define MAX_SEGMENT                                        5
++
++
++struct IP_BASE_INSTANCE
++{
++    unsigned int segment[MAX_SEGMENT];
++};
++
++struct IP_BASE
++{
++    struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
++};
++
++
++static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
++                                        { { 0x00016E00, 0x02401C00, 0, 0, 0 } },
++                                        { { 0x00017000, 0x02402000, 0, 0, 0 } },
++                                        { { 0x00017200, 0x02402400, 0, 0, 0 } },
++                                        { { 0x0001B000, 0x0242D800, 0, 0, 0 } },
++                                        { { 0x00017E00, 0x0240BC00, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE HDA_BASE ={ { { { 0x004C0000, 0x02404800, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00E80000, 0x00EC0000, 0x00F00000, 0x02400400 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE SDMA_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
++                                        { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },
++                                        { { 0x00054000, 0x02425C00, 0, 0, 0 } },
++                                        { { 0x00094000, 0x02426000, 0, 0, 0 } },
++                                        { { 0x000D4000, 0x02426400, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++
++
++#define ATHUB_BASE__INST0_SEG0                     0x00000C00
++#define ATHUB_BASE__INST0_SEG1                     0x02408C00
++#define ATHUB_BASE__INST0_SEG2                     0
++#define ATHUB_BASE__INST0_SEG3                     0
++#define ATHUB_BASE__INST0_SEG4                     0
++
++#define ATHUB_BASE__INST1_SEG0                     0
++#define ATHUB_BASE__INST1_SEG1                     0
++#define ATHUB_BASE__INST1_SEG2                     0
++#define ATHUB_BASE__INST1_SEG3                     0
++#define ATHUB_BASE__INST1_SEG4                     0
++
++#define ATHUB_BASE__INST2_SEG0                     0
++#define ATHUB_BASE__INST2_SEG1                     0
++#define ATHUB_BASE__INST2_SEG2                     0
++#define ATHUB_BASE__INST2_SEG3                     0
++#define ATHUB_BASE__INST2_SEG4                     0
++
++#define ATHUB_BASE__INST3_SEG0                     0
++#define ATHUB_BASE__INST3_SEG1                     0
++#define ATHUB_BASE__INST3_SEG2                     0
++#define ATHUB_BASE__INST3_SEG3                     0
++#define ATHUB_BASE__INST3_SEG4                     0
++
++#define ATHUB_BASE__INST4_SEG0                     0
++#define ATHUB_BASE__INST4_SEG1                     0
++#define ATHUB_BASE__INST4_SEG2                     0
++#define ATHUB_BASE__INST4_SEG3                     0
++#define ATHUB_BASE__INST4_SEG4                     0
++
++#define ATHUB_BASE__INST5_SEG0                     0
++#define ATHUB_BASE__INST5_SEG1                     0
++#define ATHUB_BASE__INST5_SEG2                     0
++#define ATHUB_BASE__INST5_SEG3                     0
++#define ATHUB_BASE__INST5_SEG4                     0
++
++#define ATHUB_BASE__INST6_SEG0                     0
++#define ATHUB_BASE__INST6_SEG1                     0
++#define ATHUB_BASE__INST6_SEG2                     0
++#define ATHUB_BASE__INST6_SEG3                     0
++#define ATHUB_BASE__INST6_SEG4                     0
++
++#define CLK_BASE__INST0_SEG0                       0x00016C00
++#define CLK_BASE__INST0_SEG1                       0x02401800
++#define CLK_BASE__INST0_SEG2                       0
++#define CLK_BASE__INST0_SEG3                       0
++#define CLK_BASE__INST0_SEG4                       0
++
++#define CLK_BASE__INST1_SEG0                       0x00016E00
++#define CLK_BASE__INST1_SEG1                       0x02401C00
++#define CLK_BASE__INST1_SEG2                       0
++#define CLK_BASE__INST1_SEG3                       0
++#define CLK_BASE__INST1_SEG4                       0
++
++#define CLK_BASE__INST2_SEG0                       0x00017000
++#define CLK_BASE__INST2_SEG1                       0x02402000
++#define CLK_BASE__INST2_SEG2                       0
++#define CLK_BASE__INST2_SEG3                       0
++#define CLK_BASE__INST2_SEG4                       0
++
++#define CLK_BASE__INST3_SEG0                       0x00017200
++#define CLK_BASE__INST3_SEG1                       0x02402400
++#define CLK_BASE__INST3_SEG2                       0
++#define CLK_BASE__INST3_SEG3                       0
++#define CLK_BASE__INST3_SEG4                       0
++
++#define CLK_BASE__INST4_SEG0                       0x0001B000
++#define CLK_BASE__INST4_SEG1                       0x0242D800
++#define CLK_BASE__INST4_SEG2                       0
++#define CLK_BASE__INST4_SEG3                       0
++#define CLK_BASE__INST4_SEG4                       0
++
++#define CLK_BASE__INST5_SEG0                       0x00017E00
++#define CLK_BASE__INST5_SEG1                       0x0240BC00
++#define CLK_BASE__INST5_SEG2                       0
++#define CLK_BASE__INST5_SEG3                       0
++#define CLK_BASE__INST5_SEG4                       0
++
++#define CLK_BASE__INST6_SEG0                       0
++#define CLK_BASE__INST6_SEG1                       0
++#define CLK_BASE__INST6_SEG2                       0
++#define CLK_BASE__INST6_SEG3                       0
++#define CLK_BASE__INST6_SEG4                       0
++
++#define DF_BASE__INST0_SEG0                        0x00007000
++#define DF_BASE__INST0_SEG1                        0x0240B800
++#define DF_BASE__INST0_SEG2                        0
++#define DF_BASE__INST0_SEG3                        0
++#define DF_BASE__INST0_SEG4                        0
++
++#define DF_BASE__INST1_SEG0                        0
++#define DF_BASE__INST1_SEG1                        0
++#define DF_BASE__INST1_SEG2                        0
++#define DF_BASE__INST1_SEG3                        0
++#define DF_BASE__INST1_SEG4                        0
++
++#define DF_BASE__INST2_SEG0                        0
++#define DF_BASE__INST2_SEG1                        0
++#define DF_BASE__INST2_SEG2                        0
++#define DF_BASE__INST2_SEG3                        0
++#define DF_BASE__INST2_SEG4                        0
++
++#define DF_BASE__INST3_SEG0                        0
++#define DF_BASE__INST3_SEG1                        0
++#define DF_BASE__INST3_SEG2                        0
++#define DF_BASE__INST3_SEG3                        0
++#define DF_BASE__INST3_SEG4                        0
++
++#define DF_BASE__INST4_SEG0                        0
++#define DF_BASE__INST4_SEG1                        0
++#define DF_BASE__INST4_SEG2                        0
++#define DF_BASE__INST4_SEG3                        0
++#define DF_BASE__INST4_SEG4                        0
++
++#define DF_BASE__INST5_SEG0                        0
++#define DF_BASE__INST5_SEG1                        0
++#define DF_BASE__INST5_SEG2                        0
++#define DF_BASE__INST5_SEG3                        0
++#define DF_BASE__INST5_SEG4                        0
++
++#define DF_BASE__INST6_SEG0                        0
++#define DF_BASE__INST6_SEG1                        0
++#define DF_BASE__INST6_SEG2                        0
++#define DF_BASE__INST6_SEG3                        0
++#define DF_BASE__INST6_SEG4                        0
++
++#define DIO_BASE__INST0_SEG0                       0x02404000
++#define DIO_BASE__INST0_SEG1                       0
++#define DIO_BASE__INST0_SEG2                       0
++#define DIO_BASE__INST0_SEG3                       0
++#define DIO_BASE__INST0_SEG4                       0
++
++#define DIO_BASE__INST1_SEG0                       0
++#define DIO_BASE__INST1_SEG1                       0
++#define DIO_BASE__INST1_SEG2                       0
++#define DIO_BASE__INST1_SEG3                       0
++#define DIO_BASE__INST1_SEG4                       0
++
++#define DIO_BASE__INST2_SEG0                       0
++#define DIO_BASE__INST2_SEG1                       0
++#define DIO_BASE__INST2_SEG2                       0
++#define DIO_BASE__INST2_SEG3                       0
++#define DIO_BASE__INST2_SEG4                       0
++
++#define DIO_BASE__INST3_SEG0                       0
++#define DIO_BASE__INST3_SEG1                       0
++#define DIO_BASE__INST3_SEG2                       0
++#define DIO_BASE__INST3_SEG3                       0
++#define DIO_BASE__INST3_SEG4                       0
++
++#define DIO_BASE__INST4_SEG0                       0
++#define DIO_BASE__INST4_SEG1                       0
++#define DIO_BASE__INST4_SEG2                       0
++#define DIO_BASE__INST4_SEG3                       0
++#define DIO_BASE__INST4_SEG4                       0
++
++#define DIO_BASE__INST5_SEG0                       0
++#define DIO_BASE__INST5_SEG1                       0
++#define DIO_BASE__INST5_SEG2                       0
++#define DIO_BASE__INST5_SEG3                       0
++#define DIO_BASE__INST5_SEG4                       0
++
++#define DIO_BASE__INST6_SEG0                       0
++#define DIO_BASE__INST6_SEG1                       0
++#define DIO_BASE__INST6_SEG2                       0
++#define DIO_BASE__INST6_SEG3                       0
++#define DIO_BASE__INST6_SEG4                       0
++
++#define DMU_BASE__INST0_SEG0                       0x00000012
++#define DMU_BASE__INST0_SEG1                       0x000000C0
++#define DMU_BASE__INST0_SEG2                       0x000034C0
++#define DMU_BASE__INST0_SEG3                       0x00009000
++#define DMU_BASE__INST0_SEG4                       0x02403C00
++
++#define DMU_BASE__INST1_SEG0                       0
++#define DMU_BASE__INST1_SEG1                       0
++#define DMU_BASE__INST1_SEG2                       0
++#define DMU_BASE__INST1_SEG3                       0
++#define DMU_BASE__INST1_SEG4                       0
++
++#define DMU_BASE__INST2_SEG0                       0
++#define DMU_BASE__INST2_SEG1                       0
++#define DMU_BASE__INST2_SEG2                       0
++#define DMU_BASE__INST2_SEG3                       0
++#define DMU_BASE__INST2_SEG4                       0
++
++#define DMU_BASE__INST3_SEG0                       0
++#define DMU_BASE__INST3_SEG1                       0
++#define DMU_BASE__INST3_SEG2                       0
++#define DMU_BASE__INST3_SEG3                       0
++#define DMU_BASE__INST3_SEG4                       0
++
++#define DMU_BASE__INST4_SEG0                       0
++#define DMU_BASE__INST4_SEG1                       0
++#define DMU_BASE__INST4_SEG2                       0
++#define DMU_BASE__INST4_SEG3                       0
++#define DMU_BASE__INST4_SEG4                       0
++
++#define DMU_BASE__INST5_SEG0                       0
++#define DMU_BASE__INST5_SEG1                       0
++#define DMU_BASE__INST5_SEG2                       0
++#define DMU_BASE__INST5_SEG3                       0
++#define DMU_BASE__INST5_SEG4                       0
++
++#define DMU_BASE__INST6_SEG0                       0
++#define DMU_BASE__INST6_SEG1                       0
++#define DMU_BASE__INST6_SEG2                       0
++#define DMU_BASE__INST6_SEG3                       0
++#define DMU_BASE__INST6_SEG4                       0
++
++#define DPCS_BASE__INST0_SEG0                      0x00000012
++#define DPCS_BASE__INST0_SEG1                      0x000000C0
++#define DPCS_BASE__INST0_SEG2                      0x000034C0
++#define DPCS_BASE__INST0_SEG3                      0x00009000
++#define DPCS_BASE__INST0_SEG4                      0x02403C00
++
++#define DPCS_BASE__INST1_SEG0                      0
++#define DPCS_BASE__INST1_SEG1                      0
++#define DPCS_BASE__INST1_SEG2                      0
++#define DPCS_BASE__INST1_SEG3                      0
++#define DPCS_BASE__INST1_SEG4                      0
++
++#define DPCS_BASE__INST2_SEG0                      0
++#define DPCS_BASE__INST2_SEG1                      0
++#define DPCS_BASE__INST2_SEG2                      0
++#define DPCS_BASE__INST2_SEG3                      0
++#define DPCS_BASE__INST2_SEG4                      0
++
++#define DPCS_BASE__INST3_SEG0                      0
++#define DPCS_BASE__INST3_SEG1                      0
++#define DPCS_BASE__INST3_SEG2                      0
++#define DPCS_BASE__INST3_SEG3                      0
++#define DPCS_BASE__INST3_SEG4                      0
++
++#define DPCS_BASE__INST4_SEG0                      0
++#define DPCS_BASE__INST4_SEG1                      0
++#define DPCS_BASE__INST4_SEG2                      0
++#define DPCS_BASE__INST4_SEG3                      0
++#define DPCS_BASE__INST4_SEG4                      0
++
++#define DPCS_BASE__INST5_SEG0                      0
++#define DPCS_BASE__INST5_SEG1                      0
++#define DPCS_BASE__INST5_SEG2                      0
++#define DPCS_BASE__INST5_SEG3                      0
++#define DPCS_BASE__INST5_SEG4                      0
++
++#define DPCS_BASE__INST6_SEG0                      0
++#define DPCS_BASE__INST6_SEG1                      0
++#define DPCS_BASE__INST6_SEG2                      0
++#define DPCS_BASE__INST6_SEG3                      0
++#define DPCS_BASE__INST6_SEG4                      0
++
++#define FUSE_BASE__INST0_SEG0                      0x00017400
++#define FUSE_BASE__INST0_SEG1                      0x02401400
++#define FUSE_BASE__INST0_SEG2                      0
++#define FUSE_BASE__INST0_SEG3                      0
++#define FUSE_BASE__INST0_SEG4                      0
++
++#define FUSE_BASE__INST1_SEG0                      0
++#define FUSE_BASE__INST1_SEG1                      0
++#define FUSE_BASE__INST1_SEG2                      0
++#define FUSE_BASE__INST1_SEG3                      0
++#define FUSE_BASE__INST1_SEG4                      0
++
++#define FUSE_BASE__INST2_SEG0                      0
++#define FUSE_BASE__INST2_SEG1                      0
++#define FUSE_BASE__INST2_SEG2                      0
++#define FUSE_BASE__INST2_SEG3                      0
++#define FUSE_BASE__INST2_SEG4                      0
++
++#define FUSE_BASE__INST3_SEG0                      0
++#define FUSE_BASE__INST3_SEG1                      0
++#define FUSE_BASE__INST3_SEG2                      0
++#define FUSE_BASE__INST3_SEG3                      0
++#define FUSE_BASE__INST3_SEG4                      0
++
++#define FUSE_BASE__INST4_SEG0                      0
++#define FUSE_BASE__INST4_SEG1                      0
++#define FUSE_BASE__INST4_SEG2                      0
++#define FUSE_BASE__INST4_SEG3                      0
++#define FUSE_BASE__INST4_SEG4                      0
++
++#define FUSE_BASE__INST5_SEG0                      0
++#define FUSE_BASE__INST5_SEG1                      0
++#define FUSE_BASE__INST5_SEG2                      0
++#define FUSE_BASE__INST5_SEG3                      0
++#define FUSE_BASE__INST5_SEG4                      0
++
++#define FUSE_BASE__INST6_SEG0                      0
++#define FUSE_BASE__INST6_SEG1                      0
++#define FUSE_BASE__INST6_SEG2                      0
++#define FUSE_BASE__INST6_SEG3                      0
++#define FUSE_BASE__INST6_SEG4                      0
++
++#define GC_BASE__INST0_SEG0                        0x00001260
++#define GC_BASE__INST0_SEG1                        0x0000A000
++#define GC_BASE__INST0_SEG2                        0x02402C00
++#define GC_BASE__INST0_SEG3                        0
++#define GC_BASE__INST0_SEG4                        0
++
++#define GC_BASE__INST1_SEG0                        0
++#define GC_BASE__INST1_SEG1                        0
++#define GC_BASE__INST1_SEG2                        0
++#define GC_BASE__INST1_SEG3                        0
++#define GC_BASE__INST1_SEG4                        0
++
++#define GC_BASE__INST2_SEG0                        0
++#define GC_BASE__INST2_SEG1                        0
++#define GC_BASE__INST2_SEG2                        0
++#define GC_BASE__INST2_SEG3                        0
++#define GC_BASE__INST2_SEG4                        0
++
++#define GC_BASE__INST3_SEG0                        0
++#define GC_BASE__INST3_SEG1                        0
++#define GC_BASE__INST3_SEG2                        0
++#define GC_BASE__INST3_SEG3                        0
++#define GC_BASE__INST3_SEG4                        0
++
++#define GC_BASE__INST4_SEG0                        0
++#define GC_BASE__INST4_SEG1                        0
++#define GC_BASE__INST4_SEG2                        0
++#define GC_BASE__INST4_SEG3                        0
++#define GC_BASE__INST4_SEG4                        0
++
++#define GC_BASE__INST5_SEG0                        0
++#define GC_BASE__INST5_SEG1                        0
++#define GC_BASE__INST5_SEG2                        0
++#define GC_BASE__INST5_SEG3                        0
++#define GC_BASE__INST5_SEG4                        0
++
++#define GC_BASE__INST6_SEG0                        0
++#define GC_BASE__INST6_SEG1                        0
++#define GC_BASE__INST6_SEG2                        0
++#define GC_BASE__INST6_SEG3                        0
++#define GC_BASE__INST6_SEG4                        0
++
++#define HDA_BASE__INST0_SEG0                       0x004C0000
++#define HDA_BASE__INST0_SEG1                       0x02404800
++#define HDA_BASE__INST0_SEG2                       0
++#define HDA_BASE__INST0_SEG3                       0
++#define HDA_BASE__INST0_SEG4                       0
++
++#define HDA_BASE__INST1_SEG0                       0
++#define HDA_BASE__INST1_SEG1                       0
++#define HDA_BASE__INST1_SEG2                       0
++#define HDA_BASE__INST1_SEG3                       0
++#define HDA_BASE__INST1_SEG4                       0
++
++#define HDA_BASE__INST2_SEG0                       0
++#define HDA_BASE__INST2_SEG1                       0
++#define HDA_BASE__INST2_SEG2                       0
++#define HDA_BASE__INST2_SEG3                       0
++#define HDA_BASE__INST2_SEG4                       0
++
++#define HDA_BASE__INST3_SEG0                       0
++#define HDA_BASE__INST3_SEG1                       0
++#define HDA_BASE__INST3_SEG2                       0
++#define HDA_BASE__INST3_SEG3                       0
++#define HDA_BASE__INST3_SEG4                       0
++
++#define HDA_BASE__INST4_SEG0                       0
++#define HDA_BASE__INST4_SEG1                       0
++#define HDA_BASE__INST4_SEG2                       0
++#define HDA_BASE__INST4_SEG3                       0
++#define HDA_BASE__INST4_SEG4                       0
++
++#define HDA_BASE__INST5_SEG0                       0
++#define HDA_BASE__INST5_SEG1                       0
++#define HDA_BASE__INST5_SEG2                       0
++#define HDA_BASE__INST5_SEG3                       0
++#define HDA_BASE__INST5_SEG4                       0
++
++#define HDA_BASE__INST6_SEG0                       0
++#define HDA_BASE__INST6_SEG1                       0
++#define HDA_BASE__INST6_SEG2                       0
++#define HDA_BASE__INST6_SEG3                       0
++#define HDA_BASE__INST6_SEG4                       0
++
++#define HDP_BASE__INST0_SEG0                       0x00000F20
++#define HDP_BASE__INST0_SEG1                       0x0240A400
++#define HDP_BASE__INST0_SEG2                       0
++#define HDP_BASE__INST0_SEG3                       0
++#define HDP_BASE__INST0_SEG4                       0
++
++#define HDP_BASE__INST1_SEG0                       0
++#define HDP_BASE__INST1_SEG1                       0
++#define HDP_BASE__INST1_SEG2                       0
++#define HDP_BASE__INST1_SEG3                       0
++#define HDP_BASE__INST1_SEG4                       0
++
++#define HDP_BASE__INST2_SEG0                       0
++#define HDP_BASE__INST2_SEG1                       0
++#define HDP_BASE__INST2_SEG2                       0
++#define HDP_BASE__INST2_SEG3                       0
++#define HDP_BASE__INST2_SEG4                       0
++
++#define HDP_BASE__INST3_SEG0                       0
++#define HDP_BASE__INST3_SEG1                       0
++#define HDP_BASE__INST3_SEG2                       0
++#define HDP_BASE__INST3_SEG3                       0
++#define HDP_BASE__INST3_SEG4                       0
++
++#define HDP_BASE__INST4_SEG0                       0
++#define HDP_BASE__INST4_SEG1                       0
++#define HDP_BASE__INST4_SEG2                       0
++#define HDP_BASE__INST4_SEG3                       0
++#define HDP_BASE__INST4_SEG4                       0
++
++#define HDP_BASE__INST5_SEG0                       0
++#define HDP_BASE__INST5_SEG1                       0
++#define HDP_BASE__INST5_SEG2                       0
++#define HDP_BASE__INST5_SEG3                       0
++#define HDP_BASE__INST5_SEG4                       0
++
++#define HDP_BASE__INST6_SEG0                       0
++#define HDP_BASE__INST6_SEG1                       0
++#define HDP_BASE__INST6_SEG2                       0
++#define HDP_BASE__INST6_SEG3                       0
++#define HDP_BASE__INST6_SEG4                       0
++
++#define MMHUB_BASE__INST0_SEG0                     0x0001A000
++#define MMHUB_BASE__INST0_SEG1                     0x02408800
++#define MMHUB_BASE__INST0_SEG2                     0
++#define MMHUB_BASE__INST0_SEG3                     0
++#define MMHUB_BASE__INST0_SEG4                     0
++
++#define MMHUB_BASE__INST1_SEG0                     0
++#define MMHUB_BASE__INST1_SEG1                     0
++#define MMHUB_BASE__INST1_SEG2                     0
++#define MMHUB_BASE__INST1_SEG3                     0
++#define MMHUB_BASE__INST1_SEG4                     0
++
++#define MMHUB_BASE__INST2_SEG0                     0
++#define MMHUB_BASE__INST2_SEG1                     0
++#define MMHUB_BASE__INST2_SEG2                     0
++#define MMHUB_BASE__INST2_SEG3                     0
++#define MMHUB_BASE__INST2_SEG4                     0
++
++#define MMHUB_BASE__INST3_SEG0                     0
++#define MMHUB_BASE__INST3_SEG1                     0
++#define MMHUB_BASE__INST3_SEG2                     0
++#define MMHUB_BASE__INST3_SEG3                     0
++#define MMHUB_BASE__INST3_SEG4                     0
++
++#define MMHUB_BASE__INST4_SEG0                     0
++#define MMHUB_BASE__INST4_SEG1                     0
++#define MMHUB_BASE__INST4_SEG2                     0
++#define MMHUB_BASE__INST4_SEG3                     0
++#define MMHUB_BASE__INST4_SEG4                     0
++
++#define MMHUB_BASE__INST5_SEG0                     0
++#define MMHUB_BASE__INST5_SEG1                     0
++#define MMHUB_BASE__INST5_SEG2                     0
++#define MMHUB_BASE__INST5_SEG3                     0
++#define MMHUB_BASE__INST5_SEG4                     0
++
++#define MMHUB_BASE__INST6_SEG0                     0
++#define MMHUB_BASE__INST6_SEG1                     0
++#define MMHUB_BASE__INST6_SEG2                     0
++#define MMHUB_BASE__INST6_SEG3                     0
++#define MMHUB_BASE__INST6_SEG4                     0
++
++#define MP0_BASE__INST0_SEG0                       0x00016000
++#define MP0_BASE__INST0_SEG1                       0x00DC0000
++#define MP0_BASE__INST0_SEG2                       0x00E00000
++#define MP0_BASE__INST0_SEG3                       0x00E40000
++#define MP0_BASE__INST0_SEG4                       0x0243FC00
++
++#define MP0_BASE__INST1_SEG0                       0
++#define MP0_BASE__INST1_SEG1                       0
++#define MP0_BASE__INST1_SEG2                       0
++#define MP0_BASE__INST1_SEG3                       0
++#define MP0_BASE__INST1_SEG4                       0
++
++#define MP0_BASE__INST2_SEG0                       0
++#define MP0_BASE__INST2_SEG1                       0
++#define MP0_BASE__INST2_SEG2                       0
++#define MP0_BASE__INST2_SEG3                       0
++#define MP0_BASE__INST2_SEG4                       0
++
++#define MP0_BASE__INST3_SEG0                       0
++#define MP0_BASE__INST3_SEG1                       0
++#define MP0_BASE__INST3_SEG2                       0
++#define MP0_BASE__INST3_SEG3                       0
++#define MP0_BASE__INST3_SEG4                       0
++
++#define MP0_BASE__INST4_SEG0                       0
++#define MP0_BASE__INST4_SEG1                       0
++#define MP0_BASE__INST4_SEG2                       0
++#define MP0_BASE__INST4_SEG3                       0
++#define MP0_BASE__INST4_SEG4                       0
++
++#define MP0_BASE__INST5_SEG0                       0
++#define MP0_BASE__INST5_SEG1                       0
++#define MP0_BASE__INST5_SEG2                       0
++#define MP0_BASE__INST5_SEG3                       0
++#define MP0_BASE__INST5_SEG4                       0
++
++#define MP0_BASE__INST6_SEG0                       0
++#define MP0_BASE__INST6_SEG1                       0
++#define MP0_BASE__INST6_SEG2                       0
++#define MP0_BASE__INST6_SEG3                       0
++#define MP0_BASE__INST6_SEG4                       0
++
++#define MP1_BASE__INST0_SEG0                       0x00016200
++#define MP1_BASE__INST0_SEG1                       0x00E80000
++#define MP1_BASE__INST0_SEG2                       0x00EC0000
++#define MP1_BASE__INST0_SEG3                       0x00F00000
++#define MP1_BASE__INST0_SEG4                       0x02400400
++
++#define MP1_BASE__INST1_SEG0                       0
++#define MP1_BASE__INST1_SEG1                       0
++#define MP1_BASE__INST1_SEG2                       0
++#define MP1_BASE__INST1_SEG3                       0
++#define MP1_BASE__INST1_SEG4                       0
++
++#define MP1_BASE__INST2_SEG0                       0
++#define MP1_BASE__INST2_SEG1                       0
++#define MP1_BASE__INST2_SEG2                       0
++#define MP1_BASE__INST2_SEG3                       0
++#define MP1_BASE__INST2_SEG4                       0
++
++#define MP1_BASE__INST3_SEG0                       0
++#define MP1_BASE__INST3_SEG1                       0
++#define MP1_BASE__INST3_SEG2                       0
++#define MP1_BASE__INST3_SEG3                       0
++#define MP1_BASE__INST3_SEG4                       0
++
++#define MP1_BASE__INST4_SEG0                       0
++#define MP1_BASE__INST4_SEG1                       0
++#define MP1_BASE__INST4_SEG2                       0
++#define MP1_BASE__INST4_SEG3                       0
++#define MP1_BASE__INST4_SEG4                       0
++
++#define MP1_BASE__INST5_SEG0                       0
++#define MP1_BASE__INST5_SEG1                       0
++#define MP1_BASE__INST5_SEG2                       0
++#define MP1_BASE__INST5_SEG3                       0
++#define MP1_BASE__INST5_SEG4                       0
++
++#define MP1_BASE__INST6_SEG0                       0
++#define MP1_BASE__INST6_SEG1                       0
++#define MP1_BASE__INST6_SEG2                       0
++#define MP1_BASE__INST6_SEG3                       0
++#define MP1_BASE__INST6_SEG4                       0
++
++#define NBIF0_BASE__INST0_SEG0                     0x00000000
++#define NBIF0_BASE__INST0_SEG1                     0x00000014
++#define NBIF0_BASE__INST0_SEG2                     0x00000D20
++#define NBIF0_BASE__INST0_SEG3                     0x00010400
++#define NBIF0_BASE__INST0_SEG4                     0x0241B000
++
++#define NBIF0_BASE__INST1_SEG0                     0
++#define NBIF0_BASE__INST1_SEG1                     0
++#define NBIF0_BASE__INST1_SEG2                     0
++#define NBIF0_BASE__INST1_SEG3                     0
++#define NBIF0_BASE__INST1_SEG4                     0
++
++#define NBIF0_BASE__INST2_SEG0                     0
++#define NBIF0_BASE__INST2_SEG1                     0
++#define NBIF0_BASE__INST2_SEG2                     0
++#define NBIF0_BASE__INST2_SEG3                     0
++#define NBIF0_BASE__INST2_SEG4                     0
++
++#define NBIF0_BASE__INST3_SEG0                     0
++#define NBIF0_BASE__INST3_SEG1                     0
++#define NBIF0_BASE__INST3_SEG2                     0
++#define NBIF0_BASE__INST3_SEG3                     0
++#define NBIF0_BASE__INST3_SEG4                     0
++
++#define NBIF0_BASE__INST4_SEG0                     0
++#define NBIF0_BASE__INST4_SEG1                     0
++#define NBIF0_BASE__INST4_SEG2                     0
++#define NBIF0_BASE__INST4_SEG3                     0
++#define NBIF0_BASE__INST4_SEG4                     0
++
++#define NBIF0_BASE__INST5_SEG0                     0
++#define NBIF0_BASE__INST5_SEG1                     0
++#define NBIF0_BASE__INST5_SEG2                     0
++#define NBIF0_BASE__INST5_SEG3                     0
++#define NBIF0_BASE__INST5_SEG4                     0
++
++#define NBIF0_BASE__INST6_SEG0                     0
++#define NBIF0_BASE__INST6_SEG1                     0
++#define NBIF0_BASE__INST6_SEG2                     0
++#define NBIF0_BASE__INST6_SEG3                     0
++#define NBIF0_BASE__INST6_SEG4                     0
++
++#define OSSSYS_BASE__INST0_SEG0                    0x000010A0
++#define OSSSYS_BASE__INST0_SEG1                    0x0240A000
++#define OSSSYS_BASE__INST0_SEG2                    0
++#define OSSSYS_BASE__INST0_SEG3                    0
++#define OSSSYS_BASE__INST0_SEG4                    0
++
++#define OSSSYS_BASE__INST1_SEG0                    0
++#define OSSSYS_BASE__INST1_SEG1                    0
++#define OSSSYS_BASE__INST1_SEG2                    0
++#define OSSSYS_BASE__INST1_SEG3                    0
++#define OSSSYS_BASE__INST1_SEG4                    0
++
++#define OSSSYS_BASE__INST2_SEG0                    0
++#define OSSSYS_BASE__INST2_SEG1                    0
++#define OSSSYS_BASE__INST2_SEG2                    0
++#define OSSSYS_BASE__INST2_SEG3                    0
++#define OSSSYS_BASE__INST2_SEG4                    0
++
++#define OSSSYS_BASE__INST3_SEG0                    0
++#define OSSSYS_BASE__INST3_SEG1                    0
++#define OSSSYS_BASE__INST3_SEG2                    0
++#define OSSSYS_BASE__INST3_SEG3                    0
++#define OSSSYS_BASE__INST3_SEG4                    0
++
++#define OSSSYS_BASE__INST4_SEG0                    0
++#define OSSSYS_BASE__INST4_SEG1                    0
++#define OSSSYS_BASE__INST4_SEG2                    0
++#define OSSSYS_BASE__INST4_SEG3                    0
++#define OSSSYS_BASE__INST4_SEG4                    0
++
++#define OSSSYS_BASE__INST5_SEG0                    0
++#define OSSSYS_BASE__INST5_SEG1                    0
++#define OSSSYS_BASE__INST5_SEG2                    0
++#define OSSSYS_BASE__INST5_SEG3                    0
++#define OSSSYS_BASE__INST5_SEG4                    0
++
++#define OSSSYS_BASE__INST6_SEG0                    0
++#define OSSSYS_BASE__INST6_SEG1                    0
++#define OSSSYS_BASE__INST6_SEG2                    0
++#define OSSSYS_BASE__INST6_SEG3                    0
++#define OSSSYS_BASE__INST6_SEG4                    0
++
++#define PCIE0_BASE__INST0_SEG0                     0x02411800
++#define PCIE0_BASE__INST0_SEG1                     0x04440000
++#define PCIE0_BASE__INST0_SEG2                     0
++#define PCIE0_BASE__INST0_SEG3                     0
++#define PCIE0_BASE__INST0_SEG4                     0
++
++#define PCIE0_BASE__INST1_SEG0                     0
++#define PCIE0_BASE__INST1_SEG1                     0
++#define PCIE0_BASE__INST1_SEG2                     0
++#define PCIE0_BASE__INST1_SEG3                     0
++#define PCIE0_BASE__INST1_SEG4                     0
++
++#define PCIE0_BASE__INST2_SEG0                     0
++#define PCIE0_BASE__INST2_SEG1                     0
++#define PCIE0_BASE__INST2_SEG2                     0
++#define PCIE0_BASE__INST2_SEG3                     0
++#define PCIE0_BASE__INST2_SEG4                     0
++
++#define PCIE0_BASE__INST3_SEG0                     0
++#define PCIE0_BASE__INST3_SEG1                     0
++#define PCIE0_BASE__INST3_SEG2                     0
++#define PCIE0_BASE__INST3_SEG3                     0
++#define PCIE0_BASE__INST3_SEG4                     0
++
++#define PCIE0_BASE__INST4_SEG0                     0
++#define PCIE0_BASE__INST4_SEG1                     0
++#define PCIE0_BASE__INST4_SEG2                     0
++#define PCIE0_BASE__INST4_SEG3                     0
++#define PCIE0_BASE__INST4_SEG4                     0
++
++#define PCIE0_BASE__INST5_SEG0                     0
++#define PCIE0_BASE__INST5_SEG1                     0
++#define PCIE0_BASE__INST5_SEG2                     0
++#define PCIE0_BASE__INST5_SEG3                     0
++#define PCIE0_BASE__INST5_SEG4                     0
++
++#define PCIE0_BASE__INST6_SEG0                     0
++#define PCIE0_BASE__INST6_SEG1                     0
++#define PCIE0_BASE__INST6_SEG2                     0
++#define PCIE0_BASE__INST6_SEG3                     0
++#define PCIE0_BASE__INST6_SEG4                     0
++
++#define SDMA_BASE__INST0_SEG0                      0x00001260
++#define SDMA_BASE__INST0_SEG1                      0x0000A000
++#define SDMA_BASE__INST0_SEG2                      0x02402C00
++#define SDMA_BASE__INST0_SEG3                      0
++#define SDMA_BASE__INST0_SEG4                      0
++
++#define SDMA_BASE__INST1_SEG0                      0x00001260
++#define SDMA_BASE__INST1_SEG1                      0x0000A000
++#define SDMA_BASE__INST1_SEG2                      0x02402C00
++#define SDMA_BASE__INST1_SEG3                      0
++#define SDMA_BASE__INST1_SEG4                      0
++
++#define SDMA_BASE__INST2_SEG0                      0
++#define SDMA_BASE__INST2_SEG1                      0
++#define SDMA_BASE__INST2_SEG2                      0
++#define SDMA_BASE__INST2_SEG3                      0
++#define SDMA_BASE__INST2_SEG4                      0
++
++#define SDMA_BASE__INST3_SEG0                      0
++#define SDMA_BASE__INST3_SEG1                      0
++#define SDMA_BASE__INST3_SEG2                      0
++#define SDMA_BASE__INST3_SEG3                      0
++#define SDMA_BASE__INST3_SEG4                      0
++
++#define SDMA_BASE__INST4_SEG0                      0
++#define SDMA_BASE__INST4_SEG1                      0
++#define SDMA_BASE__INST4_SEG2                      0
++#define SDMA_BASE__INST4_SEG3                      0
++#define SDMA_BASE__INST4_SEG4                      0
++
++#define SDMA_BASE__INST5_SEG0                      0
++#define SDMA_BASE__INST5_SEG1                      0
++#define SDMA_BASE__INST5_SEG2                      0
++#define SDMA_BASE__INST5_SEG3                      0
++#define SDMA_BASE__INST5_SEG4                      0
++
++#define SDMA_BASE__INST6_SEG0                      0
++#define SDMA_BASE__INST6_SEG1                      0
++#define SDMA_BASE__INST6_SEG2                      0
++#define SDMA_BASE__INST6_SEG3                      0
++#define SDMA_BASE__INST6_SEG4                      0
++
++#define SMUIO_BASE__INST0_SEG0                     0x00016800
++#define SMUIO_BASE__INST0_SEG1                     0x00016A00
++#define SMUIO_BASE__INST0_SEG2                     0x00440000
++#define SMUIO_BASE__INST0_SEG3                     0x02401000
++#define SMUIO_BASE__INST0_SEG4                     0
++
++#define SMUIO_BASE__INST1_SEG0                     0
++#define SMUIO_BASE__INST1_SEG1                     0
++#define SMUIO_BASE__INST1_SEG2                     0
++#define SMUIO_BASE__INST1_SEG3                     0
++#define SMUIO_BASE__INST1_SEG4                     0
++
++#define SMUIO_BASE__INST2_SEG0                     0
++#define SMUIO_BASE__INST2_SEG1                     0
++#define SMUIO_BASE__INST2_SEG2                     0
++#define SMUIO_BASE__INST2_SEG3                     0
++#define SMUIO_BASE__INST2_SEG4                     0
++
++#define SMUIO_BASE__INST3_SEG0                     0
++#define SMUIO_BASE__INST3_SEG1                     0
++#define SMUIO_BASE__INST3_SEG2                     0
++#define SMUIO_BASE__INST3_SEG3                     0
++#define SMUIO_BASE__INST3_SEG4                     0
++
++#define SMUIO_BASE__INST4_SEG0                     0
++#define SMUIO_BASE__INST4_SEG1                     0
++#define SMUIO_BASE__INST4_SEG2                     0
++#define SMUIO_BASE__INST4_SEG3                     0
++#define SMUIO_BASE__INST4_SEG4                     0
++
++#define SMUIO_BASE__INST5_SEG0                     0
++#define SMUIO_BASE__INST5_SEG1                     0
++#define SMUIO_BASE__INST5_SEG2                     0
++#define SMUIO_BASE__INST5_SEG3                     0
++#define SMUIO_BASE__INST5_SEG4                     0
++
++#define SMUIO_BASE__INST6_SEG0                     0
++#define SMUIO_BASE__INST6_SEG1                     0
++#define SMUIO_BASE__INST6_SEG2                     0
++#define SMUIO_BASE__INST6_SEG3                     0
++#define SMUIO_BASE__INST6_SEG4                     0
++
++#define THM_BASE__INST0_SEG0                       0x00016600
++#define THM_BASE__INST0_SEG1                       0x02400C00
++#define THM_BASE__INST0_SEG2                       0
++#define THM_BASE__INST0_SEG3                       0
++#define THM_BASE__INST0_SEG4                       0
++
++#define THM_BASE__INST1_SEG0                       0
++#define THM_BASE__INST1_SEG1                       0
++#define THM_BASE__INST1_SEG2                       0
++#define THM_BASE__INST1_SEG3                       0
++#define THM_BASE__INST1_SEG4                       0
++
++#define THM_BASE__INST2_SEG0                       0
++#define THM_BASE__INST2_SEG1                       0
++#define THM_BASE__INST2_SEG2                       0
++#define THM_BASE__INST2_SEG3                       0
++#define THM_BASE__INST2_SEG4                       0
++
++#define THM_BASE__INST3_SEG0                       0
++#define THM_BASE__INST3_SEG1                       0
++#define THM_BASE__INST3_SEG2                       0
++#define THM_BASE__INST3_SEG3                       0
++#define THM_BASE__INST3_SEG4                       0
++
++#define THM_BASE__INST4_SEG0                       0
++#define THM_BASE__INST4_SEG1                       0
++#define THM_BASE__INST4_SEG2                       0
++#define THM_BASE__INST4_SEG3                       0
++#define THM_BASE__INST4_SEG4                       0
++
++#define THM_BASE__INST5_SEG0                       0
++#define THM_BASE__INST5_SEG1                       0
++#define THM_BASE__INST5_SEG2                       0
++#define THM_BASE__INST5_SEG3                       0
++#define THM_BASE__INST5_SEG4                       0
++
++#define THM_BASE__INST6_SEG0                       0
++#define THM_BASE__INST6_SEG1                       0
++#define THM_BASE__INST6_SEG2                       0
++#define THM_BASE__INST6_SEG3                       0
++#define THM_BASE__INST6_SEG4                       0
++
++#define UMC_BASE__INST0_SEG0                       0x00014000
++#define UMC_BASE__INST0_SEG1                       0x02425800
++#define UMC_BASE__INST0_SEG2                       0
++#define UMC_BASE__INST0_SEG3                       0
++#define UMC_BASE__INST0_SEG4                       0
++
++#define UMC_BASE__INST1_SEG0                       0x00054000
++#define UMC_BASE__INST1_SEG1                       0x02425C00
++#define UMC_BASE__INST1_SEG2                       0
++#define UMC_BASE__INST1_SEG3                       0
++#define UMC_BASE__INST1_SEG4                       0
++
++#define UMC_BASE__INST2_SEG0                       0x00094000
++#define UMC_BASE__INST2_SEG1                       0x02426000
++#define UMC_BASE__INST2_SEG2                       0
++#define UMC_BASE__INST2_SEG3                       0
++#define UMC_BASE__INST2_SEG4                       0
++
++#define UMC_BASE__INST3_SEG0                       0x000D4000
++#define UMC_BASE__INST3_SEG1                       0x02426400
++#define UMC_BASE__INST3_SEG2                       0
++#define UMC_BASE__INST3_SEG3                       0
++#define UMC_BASE__INST3_SEG4                       0
++
++#define UMC_BASE__INST4_SEG0                       0
++#define UMC_BASE__INST4_SEG1                       0
++#define UMC_BASE__INST4_SEG2                       0
++#define UMC_BASE__INST4_SEG3                       0
++#define UMC_BASE__INST4_SEG4                       0
++
++#define UMC_BASE__INST5_SEG0                       0
++#define UMC_BASE__INST5_SEG1                       0
++#define UMC_BASE__INST5_SEG2                       0
++#define UMC_BASE__INST5_SEG3                       0
++#define UMC_BASE__INST5_SEG4                       0
++
++#define UMC_BASE__INST6_SEG0                       0
++#define UMC_BASE__INST6_SEG1                       0
++#define UMC_BASE__INST6_SEG2                       0
++#define UMC_BASE__INST6_SEG3                       0
++#define UMC_BASE__INST6_SEG4                       0
++
++#define USB0_BASE__INST0_SEG0                      0x0242A800
++#define USB0_BASE__INST0_SEG1                      0x05B00000
++#define USB0_BASE__INST0_SEG2                      0
++#define USB0_BASE__INST0_SEG3                      0
++#define USB0_BASE__INST0_SEG4                      0
++
++#define USB0_BASE__INST1_SEG0                      0
++#define USB0_BASE__INST1_SEG1                      0
++#define USB0_BASE__INST1_SEG2                      0
++#define USB0_BASE__INST1_SEG3                      0
++#define USB0_BASE__INST1_SEG4                      0
++
++#define USB0_BASE__INST2_SEG0                      0
++#define USB0_BASE__INST2_SEG1                      0
++#define USB0_BASE__INST2_SEG2                      0
++#define USB0_BASE__INST2_SEG3                      0
++#define USB0_BASE__INST2_SEG4                      0
++
++#define USB0_BASE__INST3_SEG0                      0
++#define USB0_BASE__INST3_SEG1                      0
++#define USB0_BASE__INST3_SEG2                      0
++#define USB0_BASE__INST3_SEG3                      0
++#define USB0_BASE__INST3_SEG4                      0
++
++#define USB0_BASE__INST4_SEG0                      0
++#define USB0_BASE__INST4_SEG1                      0
++#define USB0_BASE__INST4_SEG2                      0
++#define USB0_BASE__INST4_SEG3                      0
++#define USB0_BASE__INST4_SEG4                      0
++
++#define USB0_BASE__INST5_SEG0                      0
++#define USB0_BASE__INST5_SEG1                      0
++#define USB0_BASE__INST5_SEG2                      0
++#define USB0_BASE__INST5_SEG3                      0
++#define USB0_BASE__INST5_SEG4                      0
++
++#define USB0_BASE__INST6_SEG0                      0
++#define USB0_BASE__INST6_SEG1                      0
++#define USB0_BASE__INST6_SEG2                      0
++#define USB0_BASE__INST6_SEG3                      0
++#define USB0_BASE__INST6_SEG4                      0
++
++#define UVD0_BASE__INST0_SEG0                      0x00007800
++#define UVD0_BASE__INST0_SEG1                      0x00007E00
++#define UVD0_BASE__INST0_SEG2                      0x02403000
++#define UVD0_BASE__INST0_SEG3                      0
++#define UVD0_BASE__INST0_SEG4                      0
++
++#define UVD0_BASE__INST1_SEG0                      0
++#define UVD0_BASE__INST1_SEG1                      0
++#define UVD0_BASE__INST1_SEG2                      0
++#define UVD0_BASE__INST1_SEG3                      0
++#define UVD0_BASE__INST1_SEG4                      0
++
++#define UVD0_BASE__INST2_SEG0                      0
++#define UVD0_BASE__INST2_SEG1                      0
++#define UVD0_BASE__INST2_SEG2                      0
++#define UVD0_BASE__INST2_SEG3                      0
++#define UVD0_BASE__INST2_SEG4                      0
++
++#define UVD0_BASE__INST3_SEG0                      0
++#define UVD0_BASE__INST3_SEG1                      0
++#define UVD0_BASE__INST3_SEG2                      0
++#define UVD0_BASE__INST3_SEG3                      0
++#define UVD0_BASE__INST3_SEG4                      0
++
++#define UVD0_BASE__INST4_SEG0                      0
++#define UVD0_BASE__INST4_SEG1                      0
++#define UVD0_BASE__INST4_SEG2                      0
++#define UVD0_BASE__INST4_SEG3                      0
++#define UVD0_BASE__INST4_SEG4                      0
++
++#define UVD0_BASE__INST5_SEG0                      0
++#define UVD0_BASE__INST5_SEG1                      0
++#define UVD0_BASE__INST5_SEG2                      0
++#define UVD0_BASE__INST5_SEG3                      0
++#define UVD0_BASE__INST5_SEG4                      0
++
++#define UVD0_BASE__INST6_SEG0                      0
++#define UVD0_BASE__INST6_SEG1                      0
++#define UVD0_BASE__INST6_SEG2                      0
++#define UVD0_BASE__INST6_SEG3                      0
++#define UVD0_BASE__INST6_SEG4                      0
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3267-drm-amdgpu-initialize-reg-base-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3267-drm-amdgpu-initialize-reg-base-for-navi12.patch
new file mode 100644
index 00000000..456afd25
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3267-drm-amdgpu-initialize-reg-base-for-navi12.patch
@@ -0,0 +1,131 @@
+From da527aa4ee827be7c1497ff4b45103dcdb040930 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Tue, 14 May 2019 15:22:53 +0800
+Subject: [PATCH 3267/4256] drm/amdgpu: initialize reg base for navi12
+
+Set up the register offset map for navi12.
+
+Change-Id: I4b48592e8474db17634b10183c98cd399f0203aa
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile          |  2 +-
+ drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c | 53 ++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/nv.c              |  3 ++
+ drivers/gpu/drm/amd/amdgpu/nv.h              |  1 +
+ include/drm/amd_asic_type.h                  |  1 +
+ 5 files changed, 59 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index 797f8a7e4f72..651d77c59ba3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -67,7 +67,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce
+ amdgpu-y += \
+ 	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
+ 	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
+-	arct_reg_init.o
++	arct_reg_init.o navi12_reg_init.o
+ 
+ # add DF block
+ amdgpu-y += \
+diff --git a/drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c b/drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c
+new file mode 100644
+index 000000000000..cadc7603ca41
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c
+@@ -0,0 +1,53 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "amdgpu.h"
++#include "nv.h"
++
++#include "soc15_common.h"
++#include "soc15_hw_ip.h"
++#include "navi12_ip_offset.h"
++
++int navi12_reg_base_init(struct amdgpu_device *adev)
++{
++	/* HW has more IP blocks,  only initialized the blocks needed by driver */
++	uint32_t i;
++	for (i = 0 ; i < MAX_INSTANCE ; ++i) {
++		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
++		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
++		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
++		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
++		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
++		adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
++		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
++		adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i]));
++		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
++		adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i]));
++		adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
++		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
++		adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
++		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
++		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
++		adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
++	}
++	return 0;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index bf4cbcdeef78..1e0852c28c93 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -385,6 +385,9 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ 	case CHIP_NAVI14:
+ 		navi14_reg_base_init(adev);
+ 		break;
++	case CHIP_NAVI12:
++		navi12_reg_base_init(adev);
++		break;
+ 	default:
+ 		return -EINVAL;
+ 	}
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h
+index 332d5cdc308e..82e6cb432f3d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.h
++++ b/drivers/gpu/drm/amd/amdgpu/nv.h
+@@ -31,4 +31,5 @@ void nv_grbm_select(struct amdgpu_device *adev,
+ int nv_set_ip_blocks(struct amdgpu_device *adev);
+ int navi10_reg_base_init(struct amdgpu_device *adev);
+ int navi14_reg_base_init(struct amdgpu_device *adev);
++int navi12_reg_base_init(struct amdgpu_device *adev);
+ #endif
+diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
+index 5595483933aa..4fce10a2bbee 100644
+--- a/include/drm/amd_asic_type.h
++++ b/include/drm/amd_asic_type.h
+@@ -53,6 +53,7 @@ enum amd_asic_type {
+ 	CHIP_PICASSO,
+ 	CHIP_NAVI10,
+ 	CHIP_NAVI14,
++	CHIP_NAVI12,
+ 	CHIP_LAST,
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3268-drm-amdgpu-add-navi12-asic-type.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3268-drm-amdgpu-add-navi12-asic-type.patch
new file mode 100644
index 00000000..b2e0e65d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3268-drm-amdgpu-add-navi12-asic-type.patch
@@ -0,0 +1,28 @@
+From 3bc09316391e610cb8c59d5394fe8a754a9b2765 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Mon, 17 Dec 2018 18:00:26 +0800
+Subject: [PATCH 3268/4256] drm/amdgpu: add navi12 asic type
+
+Change-Id: Iaa760f994ee683a029046dd9bdae9cca58791f0d
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 87179dd882d0..c8c87711f6f1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -102,6 +102,7 @@ static const char *amdgpu_asic_name[] = {
+ 	"ARCTURUS",
+ 	"NAVI10",
+ 	"NAVI14",
++	"NAVI12",
+ 	"LAST",
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3269-drm-amdgpu-add-gpu_info-firmware-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3269-drm-amdgpu-add-gpu_info-firmware-for-navi12.patch
new file mode 100644
index 00000000..37636d81
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3269-drm-amdgpu-add-gpu_info-firmware-for-navi12.patch
@@ -0,0 +1,40 @@
+From 26bcf60294c7c7f0acef1ddcd418822b80573a68 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Mon, 17 Dec 2018 18:01:38 +0800
+Subject: [PATCH 3269/4256] drm/amdgpu: add gpu_info firmware for navi12
+
+gpu_info firmare store asic configuration details.
+
+Change-Id: I790cf04572bf1f43ff3c83a504308e5e3efb6ce3
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index c8c87711f6f1..993f4e5b7fdd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -72,6 +72,7 @@ MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
+ MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
+ MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
+ MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
++MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
+ 
+ #define AMDGPU_RESUME_MS		2000
+ 
+@@ -1469,6 +1470,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
+ 	case CHIP_NAVI14:
+ 		chip_name = "navi14";
+ 		break;
++	case CHIP_NAVI12:
++		chip_name = "navi12";
++		break;
+ 	}
+ 
+ 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3270-drm-amdgpu-set-asic-family-and-ip-blocks-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3270-drm-amdgpu-set-asic-family-and-ip-blocks-for-navi12.patch
new file mode 100644
index 00000000..a422295e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3270-drm-amdgpu-set-asic-family-and-ip-blocks-for-navi12.patch
@@ -0,0 +1,31 @@
+From b8dc7da02e6511c2826ba412c89141503852bc58 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 16 May 2019 17:36:41 +0800
+Subject: [PATCH 3270/4256] drm/amdgpu: set asic family and ip blocks for
+ navi12
+
+same with navi10
+
+Change-Id: I7c782e718f6ab26ce2a713972294e3dd12c33e97
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 993f4e5b7fdd..4cc58ec46c9d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1627,6 +1627,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
+ 		break;
+ 	case  CHIP_NAVI10:
+ 	case  CHIP_NAVI14:
++	case  CHIP_NAVI12:
+ 		adev->family = AMDGPU_FAMILY_NV;
+ 
+ 		r = nv_set_ip_blocks(adev);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3271-drm-amdgpu-use-front-door-firmware-loading-for-navi1.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3271-drm-amdgpu-use-front-door-firmware-loading-for-navi1.patch
new file mode 100644
index 00000000..1290f0c9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3271-drm-amdgpu-use-front-door-firmware-loading-for-navi1.patch
@@ -0,0 +1,31 @@
+From e8848768484373fc1ebdabc10081cebdbc882ba0 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Mon, 17 Dec 2018 18:04:19 +0800
+Subject: [PATCH 3271/4256] drm/amdgpu: use front door firmware loading for
+ navi12
+
+Same as other navi asics.
+
+Change-Id: I76cfe863e6d1da7c8b5e89d118ec9ca20675c73e
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+index 21fe00eef30e..6185ba0730a8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+@@ -362,6 +362,7 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
+ 	case CHIP_VEGA20:
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 		if (!load_type)
+ 			return AMDGPU_FW_LOAD_DIRECT;
+ 		else
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3272-drm-amdgpu-initialize-cg-pg-flags-and-external-rev-i.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3272-drm-amdgpu-initialize-cg-pg-flags-and-external-rev-i.patch
new file mode 100644
index 00000000..7e2a1362
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3272-drm-amdgpu-initialize-cg-pg-flags-and-external-rev-i.patch
@@ -0,0 +1,38 @@
+From 4f90f4895dfa59537ac76bc96d184f95c8d18249 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 16 May 2019 19:47:33 +0800
+Subject: [PATCH 3272/4256] drm/amdgpu: initialize cg/pg flags and external rev
+ id for navi12
+
+don't enable any cg/pg features yet.
+
+v2: calculate external revision id from revision id so that we can
+    differentiate navi12 A0 from A1 directly.
+
+Change-Id: I0d67d25ca73cb580dcbd8bfa9c7f35a064ac937d
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 1e0852c28c93..bdb6fa4674b7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -595,6 +595,11 @@ static int nv_common_early_init(void *handle)
+ 			AMD_PG_SUPPORT_VCN_DPG;
+ 		adev->external_rev_id = adev->rev_id + 0x1; /* ??? */
+ 		break;
++	case CHIP_NAVI12:
++		adev->cg_flags = 0;
++		adev->pg_flags = 0;
++		adev->external_rev_id = adev->rev_id + 0xa;
++		break;
+ 	default:
+ 		/* FIXME: not supported yet */
+ 		return -EINVAL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3273-drm-amdgpu-set-nbio-hdp-cg-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3273-drm-amdgpu-set-nbio-hdp-cg-for-navi12.patch
new file mode 100644
index 00000000..6a5a429a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3273-drm-amdgpu-set-nbio-hdp-cg-for-navi12.patch
@@ -0,0 +1,29 @@
+From f8ff8d70d7644f3a47eb25eb6398f78689191a53 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 16 May 2019 19:51:12 +0800
+Subject: [PATCH 3273/4256] drm/amdgpu: set nbio/hdp cg for navi12
+
+Same as navi10.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index bdb6fa4674b7..352847acfeae 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -793,6 +793,7 @@ static int nv_common_set_clockgating_state(void *handle,
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 		adev->nbio_funcs->update_medium_grain_clock_gating(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+ 		adev->nbio_funcs->update_medium_grain_light_sleep(adev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3274-drm-amdgpu-gfx10-set-gfx-cg-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3274-drm-amdgpu-gfx10-set-gfx-cg-for-navi12.patch
new file mode 100644
index 00000000..3efcf1b3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3274-drm-amdgpu-gfx10-set-gfx-cg-for-navi12.patch
@@ -0,0 +1,29 @@
+From 9a4133c95cf46d258b5848970170e5169909c126 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 16 May 2019 19:03:01 +0800
+Subject: [PATCH 3274/4256] drm/amdgpu/gfx10: set gfx cg for navi12
+
+Same as other navi asics.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 8f4af2c49cf6..313009f11207 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -4145,6 +4145,7 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 		gfx_v10_0_update_gfx_clock_gating(adev,
+ 						 state == AMD_CG_STATE_GATE ? true : false);
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3275-drm-amdgpu-gfx10-add-gfx-config-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3275-drm-amdgpu-gfx10-add-gfx-config-for-navi12.patch
new file mode 100644
index 00000000..afa39568
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3275-drm-amdgpu-gfx10-add-gfx-config-for-navi12.patch
@@ -0,0 +1,45 @@
+From f515f542e67ca39fb62b223eb3215eb466b15cfd Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 16 May 2019 19:01:19 +0800
+Subject: [PATCH 3275/4256] drm/amdgpu/gfx10: add gfx config for navi12
+
+got from mmCP_MAX_CONTEXT and mmPA_SC_FIFO_SIZE
+
+v2: squash all navi asics together because the
+settings are the same.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 10 ++--------
+ 1 file changed, 2 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 313009f11207..0c7395a37c68 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1091,18 +1091,12 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+-		adev->gfx.config.max_hw_contexts = 8;
+-		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
+-		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
+-		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
+-		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
+-		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
+-		break;
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 		adev->gfx.config.max_hw_contexts = 8;
+ 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
+ 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
+-		adev->gfx.config.sc_hiz_tile_fifo_size = 0x0;
++		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
+ 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
+ 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3276-drm-amdgpu-gfx10-declare-cp-rlc-firmwares-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3276-drm-amdgpu-gfx10-declare-cp-rlc-firmwares-for-navi12.patch
new file mode 100644
index 00000000..e1e695a4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3276-drm-amdgpu-gfx10-declare-cp-rlc-firmwares-for-navi12.patch
@@ -0,0 +1,46 @@
+From f6defb80fa0b926198c9c492719d5e9e3e085a29 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Tue, 11 Jun 2019 11:16:38 +0800
+Subject: [PATCH 3276/4256] drm/amdgpu/gfx10: declare cp/rlc firmwares for
+ navi12
+
+Set the name properly to load the right ucode.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 0c7395a37c68..cf7afdad267d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -73,6 +73,13 @@ MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
+ MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
+ MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
+ 
++MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
++MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
++MODULE_FIRMWARE("amdgpu/navi12_me.bin");
++MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
++MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
++MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
++
+ static const struct soc15_reg_golden golden_settings_gc_10_1[] =
+ {
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
+@@ -546,6 +553,9 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
+ 	case CHIP_NAVI14:
+ 		chip_name = "navi14";
+ 		break;
++	case CHIP_NAVI12:
++		chip_name = "navi12";
++		break;
+ 	default:
+ 		BUG();
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3277-drm-amdgpu-gfx10-add-placeholder-for-navi12-golden-s.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3277-drm-amdgpu-gfx10-add-placeholder-for-navi12-golden-s.patch
new file mode 100644
index 00000000..24e3a495
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3277-drm-amdgpu-gfx10-add-placeholder-for-navi12-golden-s.patch
@@ -0,0 +1,49 @@
+From 54b0293967a4f41d2f84d6d75d281c79bb5f507c Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Tue, 11 Jun 2019 11:16:54 +0800
+Subject: [PATCH 3277/4256] drm/amdgpu/gfx10: add placeholder for navi12 golden
+ settings
+
+Not used yet.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index cf7afdad267d..ecbe3349bcfd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -170,6 +170,11 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
+ 	/* Pending on emulation bring up */
+ };
+ 
++static const struct soc15_reg_golden golden_settings_gc_10_1_nv12[] =
++{
++	/* Pending on emulation bring up */
++};
++
+ #define DEFAULT_SH_MEM_CONFIG \
+ 	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
+ 	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
+@@ -319,6 +324,14 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
+ 						golden_settings_gc_10_1_nv14,
+ 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
+ 		break;
++	case CHIP_NAVI12:
++		soc15_program_register_sequence(adev,
++						golden_settings_gc_10_1,
++						(const u32)ARRAY_SIZE(golden_settings_gc_10_1));
++		soc15_program_register_sequence(adev,
++						golden_settings_gc_10_1_nv12,
++						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv12));
++		break;
+ 	default:
+ 		break;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3278-drm-amdgpu-gfx10-set-number-of-me-c-pipe-queue-for-n.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3278-drm-amdgpu-gfx10-set-number-of-me-c-pipe-queue-for-n.patch
new file mode 100644
index 00000000..815fa6d8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3278-drm-amdgpu-gfx10-set-number-of-me-c-pipe-queue-for-n.patch
@@ -0,0 +1,30 @@
+From 00a13a4391247efa1bea2e5d0748981eeeeebe62 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 16 May 2019 20:01:03 +0800
+Subject: [PATCH 3278/4256] drm/amdgpu/gfx10: set number of me(c)/pipe/queue
+ for navi12
+
+Same as other navi asics.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index ecbe3349bcfd..99e462f456ab 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1224,6 +1224,7 @@ static int gfx_v10_0_sw_init(void *handle)
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 		adev->gfx.me.num_me = 1;
+ 		adev->gfx.me.num_pipe_per_me = 2;
+ 		adev->gfx.me.num_queue_per_pipe = 1;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3279-drm-amdgpu-gfx10-set-rlc-funcs-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3279-drm-amdgpu-gfx10-set-rlc-funcs-for-navi12.patch
new file mode 100644
index 00000000..6080e77f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3279-drm-amdgpu-gfx10-set-rlc-funcs-for-navi12.patch
@@ -0,0 +1,29 @@
+From 9d25a0f8931fdf5d9700fe44219c53c7b69520cc Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 16 May 2019 20:02:14 +0800
+Subject: [PATCH 3279/4256] drm/amdgpu/gfx10: set rlc funcs for navi12
+
+Same as other navi asics.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 99e462f456ab..716b812c9d31 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -5185,6 +5185,7 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
+ 		break;
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3280-drm-amdgpu-sdma5-declare-sdma-firmwares-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3280-drm-amdgpu-sdma5-declare-sdma-firmwares-for-navi12.patch
new file mode 100644
index 00000000..93fa0c80
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3280-drm-amdgpu-sdma5-declare-sdma-firmwares-for-navi12.patch
@@ -0,0 +1,41 @@
+From f0562af3b550881ff54113d95a967248c60e6637 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Mon, 17 Dec 2018 18:05:32 +0800
+Subject: [PATCH 3280/4256] drm/amdgpu/sdma5: declare sdma firmwares for navi12
+
+Declare the firmwares and load the proper ones for navi12.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+index 3e536140bfd6..506b62270e7c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+@@ -45,6 +45,9 @@ MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
+ MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
+ MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
+ 
++MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
++MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
++
+ #define SDMA1_REG_OFFSET 0x600
+ #define SDMA0_HYP_DEC_REG_START 0x5880
+ #define SDMA0_HYP_DEC_REG_END 0x5893
+@@ -164,6 +167,9 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
+ 	case CHIP_NAVI14:
+ 		chip_name = "navi14";
+ 		break;
++	case CHIP_NAVI12:
++		chip_name = "navi12";
++		break;
+ 	default:
+ 		BUG();
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3281-drm-amdgpu-sdma5-add-placeholder-for-navi12-golden-s.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3281-drm-amdgpu-sdma5-add-placeholder-for-navi12-golden-s.patch
new file mode 100644
index 00000000..16bbf001
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3281-drm-amdgpu-sdma5-add-placeholder-for-navi12-golden-s.patch
@@ -0,0 +1,47 @@
+From d3d80c31d8c77adde76c001b572dc8f50cba0ebb Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Mon, 17 Dec 2018 18:07:22 +0800
+Subject: [PATCH 3281/4256] drm/amdgpu/sdma5: add placeholder for navi12 golden
+ settings
+
+None yet.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+index 506b62270e7c..eb6ab506e309 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+@@ -95,6 +95,9 @@ static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+ };
+ 
++static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
++};
++
+ static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
+ {
+ 	u32 base;
+@@ -132,6 +135,14 @@ static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
+ 						golden_settings_sdma_nv14,
+ 						(const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
+ 		break;
++	case CHIP_NAVI12:
++		soc15_program_register_sequence(adev,
++						golden_settings_sdma_5,
++						(const u32)ARRAY_SIZE(golden_settings_sdma_5));
++		soc15_program_register_sequence(adev,
++						golden_settings_sdma_nv12,
++						(const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
++		break;
+ 	default:
+ 		break;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3282-drm-amdgpu-gmc10-set-gart-size-and-vm-size-for-navi1.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3282-drm-amdgpu-gmc10-set-gart-size-and-vm-size-for-navi1.patch
new file mode 100644
index 00000000..e2840e10
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3282-drm-amdgpu-gmc10-set-gart-size-and-vm-size-for-navi1.patch
@@ -0,0 +1,51 @@
+From a456a8b243d0248f16035fa8d603076ae0a08b4a Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 16 May 2019 18:05:37 +0800
+Subject: [PATCH 3282/4256] drm/amdgpu/gmc10: set gart size and vm size for
+ navi12
+
+Same as other navi asics.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index a0bd14e9b8fe..4e3ac1084a94 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -525,6 +525,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
+ 		switch (adev->asic_type) {
+ 		case CHIP_NAVI10:
+ 		case CHIP_NAVI14:
++		case CHIP_NAVI12:
+ 		default:
+ 			adev->gmc.gart_size = 512ULL << 20;
+ 			break;
+@@ -603,10 +604,11 @@ static int gmc_v10_0_sw_init(void *handle)
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 		adev->num_vmhubs = 2;
+ 		/*
+ 		 * To fulfill 4-level page support,
+-		 * vm size is 256TB (48bit), maximum size of Navi10/Navi14,
++		 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
+ 		 * block size 512 (9bit)
+ 		 */
+ 		amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
+@@ -721,6 +723,7 @@ static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 		break;
+ 	default:
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3283-drm-amdgpu-add-ip-blocks-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3283-drm-amdgpu-add-ip-blocks-for-navi12.patch
new file mode 100644
index 00000000..f58f61cb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3283-drm-amdgpu-add-ip-blocks-for-navi12.patch
@@ -0,0 +1,33 @@
+From e22e152175f39856dfaef943cf196bb71991ea16 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 16 May 2019 19:58:19 +0800
+Subject: [PATCH 3283/4256] drm/amdgpu: add ip blocks for navi12
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 352847acfeae..7c74541c4e82 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -421,6 +421,13 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ 		if (adev->enable_mes)
+ 			amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
+ 		break;
++	case CHIP_NAVI12:
++		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
++		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
++		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
++		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
++		amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
++		break;
+ 	default:
+ 		return -EINVAL;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3284-drm-amdgpu-gfx10-set-tcp-harvest-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3284-drm-amdgpu-gfx10-set-tcp-harvest-for-navi12.patch
new file mode 100644
index 00000000..bdc4f0e8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3284-drm-amdgpu-gfx10-set-tcp-harvest-for-navi12.patch
@@ -0,0 +1,50 @@
+From 7533ce2befc6ca4bab1a0ab7abbeb56b759d9b2c Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Tue, 29 Jan 2019 22:36:15 +0800
+Subject: [PATCH 3284/4256] drm/amdgpu/gfx10: set tcp harvest for navi12
+
+Same as navi10.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 716b812c9d31..eeb381029b07 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1563,7 +1563,7 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
+ 	u32 utcl_invreq_disable = 0;
+ 	/*
+ 	 * GCRD_TARGETS_DISABLE field contains
+-	 * for Navi10: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
++	 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
+ 	 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
+ 	 */
+ 	u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
+@@ -1572,7 +1572,7 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
+ 			4); /* GL1C */
+ 	/*
+ 	 * UTCL1_UTCL0_INVREQ_DISABLE field contains
+-	 * for Navi10: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
++	 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
+ 	 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
+ 	 */
+ 	u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
+@@ -1581,7 +1581,9 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
+ 			4 + /* RMI */
+ 			1); /* SQG */
+ 
+-	if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_NAVI14) {
++	if (adev->asic_type == CHIP_NAVI10 ||
++	    adev->asic_type == CHIP_NAVI14 ||
++	    adev->asic_type == CHIP_NAVI12) {
+ 		mutex_lock(&adev->grbm_idx_mutex);
+ 		for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
+ 			for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3285-drm-amdgpu-enable-virtual-display-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3285-drm-amdgpu-enable-virtual-display-for-navi12.patch
new file mode 100644
index 00000000..fd338cb7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3285-drm-amdgpu-enable-virtual-display-for-navi12.patch
@@ -0,0 +1,45 @@
+From c7b1ca2f0a38813280eaabd14b75c4d9d1f17bbd Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 26 Jun 2019 19:19:57 +0800
+Subject: [PATCH 3285/4256] drm/amdgpu: enable virtual display for navi12
+
+Virtual display is a sw display interface for
+bring up and virtualization or for cards without
+display hardware.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 1 +
+ drivers/gpu/drm/amd/amdgpu/nv.c          | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+index 9b45f6e12c7c..c81d7a2067ad 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+@@ -458,6 +458,7 @@ static int dce_virtual_hw_init(void *handle)
+ 	case CHIP_ARCTURUS:
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 		break;
+ 	default:
+ 		DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", adev->asic_type);
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 7c74541c4e82..b29352924bd4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -425,6 +425,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ 		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
++		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
++			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3286-drm-amdgpu-gfx10-add-golden-settings-for-navi12-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3286-drm-amdgpu-gfx10-add-golden-settings-for-navi12-v2.patch
new file mode 100644
index 00000000..97fa5358
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3286-drm-amdgpu-gfx10-add-golden-settings-for-navi12-v2.patch
@@ -0,0 +1,98 @@
+From 3cbb189eed430d7e679ea5360934574d5026421c Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Tue, 9 Jul 2019 14:16:22 +0800
+Subject: [PATCH 3286/4256] drm/amdgpu/gfx10: add golden settings for navi12
+ (v2)
+
+Add initial golden settings for navi12 gfx.
+
+v2: update settings
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 54 +++++++++++++++++++++++---
+ 1 file changed, 49 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index eeb381029b07..4a0c55f3d848 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -165,12 +165,56 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000),
+ };
+ 
++static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
++{
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0xc0000100),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
++};
++
+ static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
+ {
+ 	/* Pending on emulation bring up */
+ };
+ 
+-static const struct soc15_reg_golden golden_settings_gc_10_1_nv12[] =
++static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
+ {
+ 	/* Pending on emulation bring up */
+ };
+@@ -326,11 +370,11 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
+ 		break;
+ 	case CHIP_NAVI12:
+ 		soc15_program_register_sequence(adev,
+-						golden_settings_gc_10_1,
+-						(const u32)ARRAY_SIZE(golden_settings_gc_10_1));
++						golden_settings_gc_10_1_2,
++						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
+ 		soc15_program_register_sequence(adev,
+-						golden_settings_gc_10_1_nv12,
+-						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv12));
++						golden_settings_gc_10_1_2_nv12,
++						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
+ 		break;
+ 	default:
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3287-drm-amdgpu-sdma5-add-golden-settings-for-navi12-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3287-drm-amdgpu-sdma5-add-golden-settings-for-navi12-v2.patch
new file mode 100644
index 00000000..c7e336d6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3287-drm-amdgpu-sdma5-add-golden-settings-for-navi12-v2.patch
@@ -0,0 +1,33 @@
+From 1fd0245b3d2b402f6fac7d97d12dcbdfed838c08 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Tue, 9 Jul 2019 14:17:08 +0800
+Subject: [PATCH 3287/4256] drm/amdgpu/sdma5: add golden settings for navi12
+ (v2)
+
+common golden settings are put in golden_settings_sdma_5 array
+
+v2: update settings (Alex)
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+index eb6ab506e309..4d30b3ff5c35 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+@@ -96,6 +96,8 @@ static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
+ };
+ 
+ static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+ };
+ 
+ static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3288-drm-amdgpu-add-CGTT_GS_NGG_CLK_CTRL-register-to-gc-h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3288-drm-amdgpu-add-CGTT_GS_NGG_CLK_CTRL-register-to-gc-h.patch
new file mode 100644
index 00000000..02e3cd3b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3288-drm-amdgpu-add-CGTT_GS_NGG_CLK_CTRL-register-to-gc-h.patch
@@ -0,0 +1,81 @@
+From 2ad74e74f64fbd31111582fc37d6adc1b7154dae Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 10 Jul 2019 18:50:20 +0800
+Subject: [PATCH 3288/4256] drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc
+ header
+
+gc 10.1.2 introduced this new register
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../include/asic_reg/gc/gc_10_1_0_offset.h    |  2 +
+ .../include/asic_reg/gc/gc_10_1_0_sh_mask.h   | 39 +++++++++++++++++++
+ 2 files changed, 41 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+index 1dbc7cefbc05..075867d4b1da 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+@@ -10107,6 +10107,8 @@
+ #define mmCGTT_IA_CLK_CTRL_BASE_IDX                                                                    1
+ #define mmCGTT_WD_CLK_CTRL                                                                             0x5086
+ #define mmCGTT_WD_CLK_CTRL_BASE_IDX                                                                    1
++#define mmCGTT_GS_NGG_CLK_CTRL                                                                         0x5087
++#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX                                                                1
+ #define mmCGTT_PA_CLK_CTRL                                                                             0x5088
+ #define mmCGTT_PA_CLK_CTRL_BASE_IDX                                                                    1
+ #define mmCGTT_SC_CLK_CTRL0                                                                            0x5089
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
+index 6c2a421fe8b7..e7db6f9f9c86 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
+@@ -37872,6 +37872,45 @@
+ #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK                                                                  0x20000000L
+ #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK                                                            0x40000000L
+ #define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK                                                                   0x80000000L
++//CGTT_GS_NGG_CLK_CTRL
++#define CGTT_GS_NGG_CLK_CTRL__ON_DELAY__SHIFT                                                                 0x0
++#define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                           0x4
++#define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE__SHIFT                                                              0xf
++#define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE__SHIFT                                                               0x10
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                     0x11
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                     0x12
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                     0x13
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                     0x14
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                     0x15
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                     0x16
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                     0x17
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                           0x18
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                           0x19
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                           0x1a
++#define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT                                                         0x1b
++#define CGTT_GS_NGG_CLK_CTRL__GS1_OVERRIDE__SHIFT                                                             0x1c
++#define CGTT_GS_NGG_CLK_CTRL__GS0_OVERRIDE__SHIFT                                                             0x1d
++#define CGTT_GS_NGG_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT                                                      0x1e
++#define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE__SHIFT                                                             0x1f
++#define CGTT_GS_NGG_CLK_CTRL__ON_DELAY_MASK                                                                   0x0000000FL
++#define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS_MASK                                                             0x00000FF0L
++#define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE_MASK                                                                0x00008000L
++#define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE_MASK                                                                 0x00010000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                       0x00020000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                       0x00040000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                       0x00080000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                       0x00100000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                       0x00200000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                       0x00400000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                       0x00800000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                             0x01000000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                             0x02000000L
++#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                             0x04000000L
++#define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE_MASK                                                           0x08000000L
++#define CGTT_GS_NGG_CLK_CTRL__GS1_OVERRIDE_MASK                                                               0x10000000L
++#define CGTT_GS_NGG_CLK_CTRL__GS0_OVERRIDE_MASK                                                               0x20000000L
++#define CGTT_GS_NGG_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK                                                        0x40000000L
++#define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE_MASK                                                               0x80000000L
+ //CGTT_PA_CLK_CTRL
+ #define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
+ #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3289-drm-amdgpu-correct-smu-rlc-handshake-enablement-bit.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3289-drm-amdgpu-correct-smu-rlc-handshake-enablement-bit.patch
new file mode 100644
index 00000000..e859678f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3289-drm-amdgpu-correct-smu-rlc-handshake-enablement-bit.patch
@@ -0,0 +1,34 @@
+From a561c0210a9bfc449d0b63f9bd828dc396a03958 Mon Sep 17 00:00:00 2001
+From: Jack Xiao <Jack.Xiao@amd.com>
+Date: Mon, 15 Jul 2019 05:12:21 +0800
+Subject: [PATCH 3289/4256] drm/amdgpu: correct smu rlc handshake enablement
+ bit
+
+Correct the enablement bit of SMU RLC handshake.
+
+Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 4a0c55f3d848..beee75df22a0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1775,9 +1775,9 @@ static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
+ 		 * hence no handshake between SMU & RLC
+ 		 * GFXOFF will be disabled
+ 		 */
+-		rlc_pg_cntl |= 0x80000;
++		rlc_pg_cntl |= 0x800000;
+ 	} else
+-		rlc_pg_cntl &= ~0x80000;
++		rlc_pg_cntl &= ~0x800000;
+ 	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3290-drm-amdgpu-smu11-add-smu-support-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3290-drm-amdgpu-smu11-add-smu-support-for-navi12.patch
new file mode 100644
index 00000000..eff19817
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3290-drm-amdgpu-smu11-add-smu-support-for-navi12.patch
@@ -0,0 +1,69 @@
+From bf7a811340ebafff2be31977943fe986fd07679e Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 1 Aug 2019 14:54:59 -0500
+Subject: [PATCH 3290/4256] drm/amdgpu/smu11: add smu support for navi12
+
+Same as other Navi asics.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 1 +
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c  | 6 ++++++
+ 2 files changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index f928c5f97d07..5ba038260091 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -726,6 +726,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
+ 	case CHIP_VEGA20:
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 	case CHIP_ARCTURUS:
+ 		if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
+ 			smu->od_enabled = true;
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 43fcbdbba630..84eb14a6650f 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -46,6 +46,7 @@ MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
+ MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
+ MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
+ MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
++MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
+ 
+ #define SMU11_VOLTAGE_SCALE 4
+ 
+@@ -163,6 +164,9 @@ static int smu_v11_0_init_microcode(struct smu_context *smu)
+ 	case CHIP_NAVI14:
+ 		chip_name = "navi14";
+ 		break;
++	case CHIP_NAVI12:
++		chip_name = "navi12";
++		break;
+ 	default:
+ 		BUG();
+ 	}
+@@ -1331,6 +1335,7 @@ static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
+ 		break;
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 		if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
+ 			return 0;
+ 		mutex_lock(&smu->mutex);
+@@ -1754,6 +1759,7 @@ void smu_v11_0_set_smu_funcs(struct smu_context *smu)
+ 		break;
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 		navi10_set_ppt_funcs(smu);
+ 		break;
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3291-drm-amdgpu-psp11-add-psp-support-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3291-drm-amdgpu-psp11-add-psp-support-for-navi12.patch
new file mode 100644
index 00000000..0e3e2be2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3291-drm-amdgpu-psp11-add-psp-support-for-navi12.patch
@@ -0,0 +1,61 @@
+From 021204b245504e66e7c86f8c4f4c2ba5b64b3fa1 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Fri, 2 Aug 2019 08:59:36 -0500
+Subject: [PATCH 3291/4256] drm/amdgpu/psp11: add psp support for navi12
+
+Same as other navi asics.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c  | 6 ++++++
+ 2 files changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index fb5d7b8cbd03..ec3d0ba9462d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -60,6 +60,7 @@ static int psp_early_init(void *handle)
+ 		break;
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 		psp_v11_0_set_psp_funcs(psp);
+ 		psp->autoload_supported = true;
+ 		break;
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index 246cb9b75c05..4954b1d7d3d0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -44,6 +44,8 @@ MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
+ MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
+ MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
+ MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
++MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
++MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
+ MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
+ MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
+ 
+@@ -82,6 +84,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
+ 	case CHIP_NAVI14:
+ 		chip_name = "navi14";
+ 		break;
++	case CHIP_NAVI12:
++		chip_name = "navi12";
++		break;
+ 	case CHIP_ARCTURUS:
+ 		chip_name = "arcturus";
+ 		break;
+@@ -184,6 +189,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
+ 		break;
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 	case CHIP_ARCTURUS:
+ 		break;
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3292-drm-amdgpu-start-autoload-till-RLCG-fw-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3292-drm-amdgpu-start-autoload-till-RLCG-fw-for-navi12.patch
new file mode 100644
index 00000000..0b459043
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3292-drm-amdgpu-start-autoload-till-RLCG-fw-for-navi12.patch
@@ -0,0 +1,31 @@
+From 44001852519e72041b1302f1534b20e54180c8f8 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 18 Jul 2019 05:00:00 +0800
+Subject: [PATCH 3292/4256] drm/amdgpu: start autoload till RLCG fw for navi12
+
+rlc save restore list is not ready yet for navi12
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index ec3d0ba9462d..c83642e9ed34 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1028,7 +1028,8 @@ static int psp_np_fw_load(struct psp_context *psp)
+ 			return ret;
+ 
+ 		/* Start rlc autoload after psp recieved all the gfx firmware */
+-		if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
++		if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM ||
++		    (adev->asic_type == CHIP_NAVI12 && ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G)) {
+ 			ret = psp_rlc_autoload(psp);
+ 			if (ret) {
+ 				DRM_ERROR("Failed to start rlc autoload\n");
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3293-drm-amdgpu-add-smu-ip-block-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3293-drm-amdgpu-add-smu-ip-block-for-navi12.patch
new file mode 100644
index 00000000..eceb0248
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3293-drm-amdgpu-add-smu-ip-block-for-navi12.patch
@@ -0,0 +1,36 @@
+From 6c6125d9bf2ce721da6f817cb22a67ff300c7735 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Tue, 16 Jul 2019 03:26:49 +0800
+Subject: [PATCH 3293/4256] drm/amdgpu: add smu ip block for navi12
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index b29352924bd4..87dc59546771 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -425,10 +425,16 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ 		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
++		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
++		    is_support_sw_smu(adev))
++			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+ 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
++		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
++		    is_support_sw_smu(adev))
++			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ 		break;
+ 	default:
+ 		return -EINVAL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3294-drm-amdgpu-add-psp-ip-block-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3294-drm-amdgpu-add-psp-ip-block-for-navi12.patch
new file mode 100644
index 00000000..30bc9c0b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3294-drm-amdgpu-add-psp-ip-block-for-navi12.patch
@@ -0,0 +1,27 @@
+From 33a1d8f2f345c8e93cfa24b11fc5b27526c62b6f Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 18 Jul 2019 02:54:29 +0800
+Subject: [PATCH 3294/4256] drm/amdgpu: add psp ip block for navi12
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 87dc59546771..e503b226ccdb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -425,6 +425,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ 		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
++		amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+ 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
+ 		    is_support_sw_smu(adev))
+ 			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3295-drm-amdgpu-add-Navi12-VCN-firmware-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3295-drm-amdgpu-add-Navi12-VCN-firmware-support.patch
new file mode 100644
index 00000000..726ee05b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3295-drm-amdgpu-add-Navi12-VCN-firmware-support.patch
@@ -0,0 +1,57 @@
+From 47030f6eeb8d696cd8d9a8b4d2dbf5c1f73bf098 Mon Sep 17 00:00:00 2001
+From: Boyuan Zhang <boyuan.zhang@amd.com>
+Date: Thu, 18 Jul 2019 09:17:24 -0400
+Subject: [PATCH 3295/4256] drm/amdgpu: add Navi12 VCN firmware support
+
+Add Navi12 to VCN family
+
+Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
+Reviewed-by: Leo Liu <leo.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+index 21ca8e0ab8b6..b74f0f679aca 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+@@ -48,6 +48,7 @@
+ #define FIRMWARE_ARCTURUS 	"amdgpu/arcturus_vcn.bin"
+ #define FIRMWARE_NAVI10 	"amdgpu/navi10_vcn.bin"
+ #define FIRMWARE_NAVI14 	"amdgpu/navi14_vcn.bin"
++#define FIRMWARE_NAVI12 	"amdgpu/navi12_vcn.bin"
+ 
+ MODULE_FIRMWARE(FIRMWARE_RAVEN);
+ MODULE_FIRMWARE(FIRMWARE_PICASSO);
+@@ -55,6 +56,7 @@ MODULE_FIRMWARE(FIRMWARE_RAVEN2);
+ MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
+ MODULE_FIRMWARE(FIRMWARE_NAVI10);
+ MODULE_FIRMWARE(FIRMWARE_NAVI14);
++MODULE_FIRMWARE(FIRMWARE_NAVI12);
+ 
+ static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
+ 
+@@ -86,12 +88,18 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
+ 		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
+ 			adev->vcn.indirect_sram = true;
+ 		break;
+-    case CHIP_NAVI14:
++	case CHIP_NAVI14:
+ 		fw_name = FIRMWARE_NAVI14;
+ 		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
+ 		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
+ 			adev->vcn.indirect_sram = true;
+ 		break;
++	case CHIP_NAVI12:
++		fw_name = FIRMWARE_NAVI12;
++		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
++		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
++			adev->vcn.indirect_sram = true;
++		break;
+ 	default:
+ 		return -EINVAL;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3296-drm-amdgpu-add-VCN-ip-block-for-Navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3296-drm-amdgpu-add-VCN-ip-block-for-Navi12.patch
new file mode 100644
index 00000000..a0d5e68b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3296-drm-amdgpu-add-VCN-ip-block-for-Navi12.patch
@@ -0,0 +1,29 @@
+From 8e18bf5939631b294ea8db60e2cb1b7ab04e1c14 Mon Sep 17 00:00:00 2001
+From: Boyuan Zhang <boyuan.zhang@amd.com>
+Date: Thu, 18 Jul 2019 10:13:23 -0400
+Subject: [PATCH 3296/4256] drm/amdgpu: add VCN ip block for Navi12
+
+Add VCN2 ip block for Navi12
+
+Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
+Reviewed-by: Leo Liu <leo.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index e503b226ccdb..7c00aaeefda9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -436,6 +436,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
+ 		    is_support_sw_smu(adev))
+ 			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
++		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
+ 		break;
+ 	default:
+ 		return -EINVAL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3297-drm-amdgpu-enable-DPG-mode-for-Navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3297-drm-amdgpu-enable-DPG-mode-for-Navi12.patch
new file mode 100644
index 00000000..50565b95
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3297-drm-amdgpu-enable-DPG-mode-for-Navi12.patch
@@ -0,0 +1,30 @@
+From dec322ce876ffbe898ca3c214fc048957d69c944 Mon Sep 17 00:00:00 2001
+From: Boyuan Zhang <boyuan.zhang@amd.com>
+Date: Thu, 18 Jul 2019 17:39:07 -0400
+Subject: [PATCH 3297/4256] drm/amdgpu: enable DPG mode for Navi12
+
+Enable Dynamic Power Gating VCN for Navi12.
+
+Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 7c00aaeefda9..85e7688dbaa0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -614,7 +614,7 @@ static int nv_common_early_init(void *handle)
+ 		break;
+ 	case CHIP_NAVI12:
+ 		adev->cg_flags = 0;
+-		adev->pg_flags = 0;
++		adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
+ 		adev->external_rev_id = adev->rev_id + 0xa;
+ 		break;
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3298-drm-amd-display-Add-ASICREV_IS_NAVI-macros.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3298-drm-amd-display-Add-ASICREV_IS_NAVI-macros.patch
new file mode 100644
index 00000000..0d7d4da0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3298-drm-amd-display-Add-ASICREV_IS_NAVI-macros.patch
@@ -0,0 +1,36 @@
+From c0102384042b1e313721af0ebe1dbf7bf3dd6bde Mon Sep 17 00:00:00 2001
+From: Leo Li <sunpeng.li@amd.com>
+Date: Tue, 16 Jul 2019 11:50:06 -0400
+Subject: [PATCH 3298/4256] drm/amd/display: Add ASICREV_IS_NAVI macros
+
+They are used by DC to determine ASIC revs.
+
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/include/dal_asic_id.h | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+index 54e9246f3f82..cb9b1873f947 100644
+--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
++++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+@@ -151,11 +151,13 @@
+ 
+ enum {
+ 	NV_NAVI10_P_A0      = 1,
++	NV_NAVI12_P_A0      = 10,
+ 	NV_NAVI14_M_A0      = 20,
+ 	NV_UNKNOWN          = 0xFF
+ };
+ 
+-#define ASICREV_IS_NAVI10_P(eChipRev)        (eChipRev < NV_NAVI14_M_A0)
++#define ASICREV_IS_NAVI10_P(eChipRev)        (eChipRev < NV_NAVI12_P_A0)
++#define ASICREV_IS_NAVI12_P(eChipRev)        ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0))
+ #define ASICREV_IS_NAVI14_M(eChipRev)        ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN))
+ #endif
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3299-drm-amdgpu-Add-nv12-DC-ip-block.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3299-drm-amdgpu-Add-nv12-DC-ip-block.patch
new file mode 100644
index 00000000..8d033fad
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3299-drm-amdgpu-Add-nv12-DC-ip-block.patch
@@ -0,0 +1,44 @@
+From a49b9d8d1bbe9b97af3d1eecf04b92d59afce327 Mon Sep 17 00:00:00 2001
+From: Leo Li <sunpeng.li@amd.com>
+Date: Tue, 16 Jul 2019 18:12:13 -0400
+Subject: [PATCH 3299/4256] drm/amdgpu: Add nv12 DC ip block
+
+Load DC and amdgpu display manager
+
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
+ drivers/gpu/drm/amd/amdgpu/nv.c            | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 4cc58ec46c9d..a74c73dd292a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2538,6 +2538,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ #endif
+ 		return amdgpu_dc != 0;
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 85e7688dbaa0..9614c65fa292 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -431,6 +431,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ 			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+ 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
++		else if (amdgpu_device_has_dc_support(adev))
++			amdgpu_device_ip_block_add(adev, &dm_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
+ 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3300-drm-amd-display-Add-missing-NV12-asic-IDs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3300-drm-amd-display-Add-missing-NV12-asic-IDs.patch
new file mode 100644
index 00000000..724c34e3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3300-drm-amd-display-Add-missing-NV12-asic-IDs.patch
@@ -0,0 +1,45 @@
+From 383217f684918802742c65a54879854185bc0b04 Mon Sep 17 00:00:00 2001
+From: Roman Li <Roman.Li@amd.com>
+Date: Tue, 16 Jul 2019 17:26:14 -0400
+Subject: [PATCH 3300/4256] drm/amd/display: Add missing NV12 asic IDs
+
+Add missing navi12 asic ids.
+
+Signed-off-by: Roman Li <Roman.Li@amd.com>
+Reviewed-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 3ec42eb79ec9..5bb3dfa341df 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -807,6 +807,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
+ 	case CHIP_VEGA20:
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 		return 0;
+ 	case CHIP_RAVEN:
+ 		if (ASICREV_IS_PICASSO(adev->external_rev_id))
+@@ -2600,6 +2601,7 @@ static int dm_early_init(void *handle)
+ #endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	case CHIP_NAVI10:
++	case CHIP_NAVI12:
+ 		adev->mode_info.num_crtc = 6;
+ 		adev->mode_info.num_hpd = 6;
+ 		adev->mode_info.num_dig = 6;
+@@ -2905,6 +2907,7 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	    adev->asic_type == CHIP_NAVI10 ||
+ 	    adev->asic_type == CHIP_NAVI14 ||
++	    adev->asic_type == CHIP_NAVI12 ||
+ #endif
+ 	    adev->asic_type == CHIP_RAVEN) {
+ 		/* Fill GFX9 params */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3301-drm-amdgpu-enable-Navi12-kfd-support-for-amdgpu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3301-drm-amdgpu-enable-Navi12-kfd-support-for-amdgpu.patch
new file mode 100644
index 00000000..c3bca31a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3301-drm-amdgpu-enable-Navi12-kfd-support-for-amdgpu.patch
@@ -0,0 +1,29 @@
+From 96871c707d07608df29b99d65f80c7a2199707b5 Mon Sep 17 00:00:00 2001
+From: shaoyunl <shaoyun.liu@amd.com>
+Date: Fri, 26 Jul 2019 14:19:02 -0500
+Subject: [PATCH 3301/4256] drm/amdgpu: enable Navi12 kfd support for amdgpu
+
+Navi12 has the same interface as Navi10
+
+Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
+Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+index 34529ee28d4d..074206458323 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+@@ -98,6 +98,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
+ 		kfd2kgd = amdgpu_amdkfd_arcturus_get_functions();
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 		kfd2kgd = amdgpu_amdkfd_gfx_10_0_get_functions();
+ 		break;
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3302-drm-amd-display-Validate-dc_plane_info-and-dc_plane_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3302-drm-amd-display-Validate-dc_plane_info-and-dc_plane_.patch
new file mode 100644
index 00000000..a506d7aa
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3302-drm-amd-display-Validate-dc_plane_info-and-dc_plane_.patch
@@ -0,0 +1,72 @@
+From 90ae05e714d21532d89541867b16fcb45c59b1d6 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Fri, 2 Aug 2019 10:31:29 -0400
+Subject: [PATCH 3302/4256] drm/amd/display: Validate dc_plane_info and
+ dc_plane_size in atomic check
+
+[Why]
+Pitch, DCC, rotation and mirroring can result in updates that are not
+UPDATE_TYPE_FAST but UPDATE_TYPE_MED instead. DC needs dc_plane_info
+and dc_plane_size to make this determination and we aren't currently
+passing this into DC during atomic check.
+
+Underflow (visible or non-visible) can occur if we don't validate this
+correctly. This also will generally trigger p-state warnings, typically
+via the cursor handler when locking.
+
+[How]
+Get the framebuffer tiling flags and generate the required structures
+for DC in dm_determine_update_type_for_commit.
+
+Change-Id: Ib380299632e8a4ffe609e633adb6c2f623d0cec0
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: David Francis <david.francis@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 24 +++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 5bb3dfa341df..79172215cc9f 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -6988,6 +6988,12 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
+ 			continue;
+ 
+ 		for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
++                        const struct amdgpu_framebuffer *amdgpu_fb =
++                                to_amdgpu_framebuffer(new_plane_state->fb);
++                        struct dc_plane_info plane_info;
++                        struct dc_flip_addrs flip_addr;
++                        uint64_t tiling_flags;
++
+ 			new_plane_crtc = new_plane_state->crtc;
+ 			old_plane_crtc = old_plane_state->crtc;
+ 			new_dm_plane_state = to_dm_plane_state(new_plane_state);
+@@ -7031,6 +7037,24 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
+ 
+ 			updates[num_plane].scaling_info = &scaling_info;
+ 
++			if (amdgpu_fb) {
++				ret = get_fb_info(amdgpu_fb, &tiling_flags);
++				if (ret)
++					goto cleanup;
++
++				memset(&flip_addr, 0, sizeof(flip_addr));
++
++				ret = fill_dc_plane_info_and_addr(
++					dm->adev, new_plane_state, tiling_flags,
++					&plane_info,
++					&flip_addr.address);
++				if (ret)
++					goto cleanup;
++
++				updates[num_plane].plane_info = &plane_info;
++				updates[num_plane].flip_addr = &flip_addr;
++			}
++
+ 			num_plane++;
+ 		}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3303-drm-amd-display-Block-immediate-flips-for-non-fast-u.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3303-drm-amd-display-Block-immediate-flips-for-non-fast-u.patch
new file mode 100644
index 00000000..7d7c0796
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3303-drm-amd-display-Block-immediate-flips-for-non-fast-u.patch
@@ -0,0 +1,79 @@
+From 55f6f8a637cc700f30939140fb14e4a4c0821a33 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Fri, 2 Aug 2019 10:45:11 -0400
+Subject: [PATCH 3303/4256] drm/amd/display: Block immediate flips for non-fast
+ updates
+
+[Why]
+Underflow can occur in the case where we change buffer pitch, DCC state,
+rotation or mirroring for a plane while also performing an immediate
+flip. It can also generate a p-state warning stack trace on DCN1 which
+is typically observed during the cursor handler pipe locking because of
+how frequent cursor updates can occur.
+
+[How]
+Store the update type on each CRTC - every plane will have access to
+the CRTC state if it's flipping. If the update type is not
+UPDATE_TYPE_FAST then the immediate flip should be disallowed.
+
+No changes to the target vblank sequencing need to be done, we just
+need to ensure that the surface registers do a double buffered update.
+
+Change-Id: I08f1c1c6452811c97deb4190fe6d373bbfa58fa6
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: David Francis <david.francis@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 ++++++++++++++-
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  1 +
+ 2 files changed, 15 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 79172215cc9f..a1ee74584913 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -5699,9 +5699,14 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
+ 
+ 		bundle->surface_updates[planes_count].plane_info =
+ 			&bundle->plane_infos[planes_count];
++		/*
++                 * Only allow immediate flips for fast updates that don't
++                 * change FB pitch, DCC state, rotation or mirroing.
++                 */
+ 
+ 		bundle->flip_addrs[planes_count].flip_immediate =
+-				(crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
++				(crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0 &&
++				acrtc_state->update_type == UPDATE_TYPE_FAST;
+ 
+ 		timestamp_ns = ktime_get_ns();
+ 		bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
+@@ -7349,6 +7354,14 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
+ 		}
+ 	}
+ 
++	/* Store the overall update type for use later in atomic check. */
++	for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
++		struct dm_crtc_state *dm_new_crtc_state =
++			to_dm_crtc_state(new_crtc_state);
++
++		dm_new_crtc_state->update_type = (int)overall_update_type;
++	}
++
+ 	/* Must be success */
+ 	WARN_ON(ret);
+ 	return ret;
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+index d323746f1bdd..32893635c995 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+@@ -304,6 +304,7 @@ struct dm_crtc_state {
+ 	bool cm_has_degamma;
+ 	bool cm_is_degamma_srgb;
+ 
++	int update_type;
+ 	int active_planes;
+ 	bool interrupts_enabled;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3304-Revert-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3304-Revert-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch
new file mode 100644
index 00000000..99516796
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3304-Revert-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch
@@ -0,0 +1,170 @@
+From b236dd767bfd1c0655921a7cd023cefa58a092bb Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Mon, 5 Aug 2019 15:35:04 +0800
+Subject: [PATCH 3304/4256] Revert "drm/amdgpu: fix double ucode load by
+ PSP(v3)"
+
+Change-Id: Id77fddafde4f0d241313dc5ccbe322f8e4b812bc
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 59 ++++++++--------------
+ 1 file changed, 21 insertions(+), 38 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index a74c73dd292a..59099f040800 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1751,34 +1751,28 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
+ 
+ 	if (adev->asic_type >= CHIP_VEGA10) {
+ 		for (i = 0; i < adev->num_ip_blocks; i++) {
+-			if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
+-				continue;
+-
+-			/* no need to do the fw loading again if already done*/
+-			if (adev->ip_blocks[i].status.hw == true)
+-				break;
+-
+-			if (adev->in_gpu_reset || adev->in_suspend) {
+-				r = adev->ip_blocks[i].version->funcs->resume(adev);
+-				if (r) {
+-					DRM_ERROR("resume of IP block <%s> failed %d\n",
++			if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
++				if (adev->in_gpu_reset || adev->in_suspend) {
++					if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset)
++						break; /* sriov gpu reset, psp need to do hw_init before IH because of hw limit */
++					r = adev->ip_blocks[i].version->funcs->resume(adev);
++					if (r) {
++						DRM_ERROR("resume of IP block <%s> failed %d\n",
+ 							  adev->ip_blocks[i].version->funcs->name, r);
+-					return r;
+-				}
+-			} else {
+-				r = adev->ip_blocks[i].version->funcs->hw_init(adev);
+-				if (r) {
+-					DRM_ERROR("hw_init of IP block <%s> failed %d\n",
+-							  adev->ip_blocks[i].version->funcs->name, r);
+-					return r;
++						return r;
++					}
++				} else {
++					r = adev->ip_blocks[i].version->funcs->hw_init(adev);
++					if (r) {
++						DRM_ERROR("hw_init of IP block <%s> failed %d\n",
++						  adev->ip_blocks[i].version->funcs->name, r);
++						return r;
++					}
+ 				}
++				adev->ip_blocks[i].status.hw = true;
+ 			}
+-
+-			adev->ip_blocks[i].status.hw = true;
+-			break;
+ 		}
+ 	}
+-
+ 	r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
+ 
+ 	return r;
+@@ -2212,9 +2206,7 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
+ 			if (r) {
+ 				DRM_ERROR("suspend of IP block <%s> failed %d\n",
+ 					  adev->ip_blocks[i].version->funcs->name, r);
+-				return r;
+ 			}
+-			adev->ip_blocks[i].status.hw = false;
+ 		}
+ 	}
+ 
+@@ -2254,16 +2246,14 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
+ 			if (is_support_sw_smu(adev)) {
+ 				/* todo */
+ 			} else if (adev->powerplay.pp_funcs &&
+-					   adev->powerplay.pp_funcs->set_mp1_state) {
++				   adev->powerplay.pp_funcs->set_mp1_state) {
+ 				r = adev->powerplay.pp_funcs->set_mp1_state(
+ 					adev->powerplay.pp_handle,
+ 					adev->mp1_state);
+ 				if (r) {
+ 					DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
+ 						  adev->mp1_state, r);
+-					return r;
+ 				}
+-				adev->ip_blocks[i].status.hw = false;
+ 			}
+ 		}
+ 	}
+@@ -2318,7 +2308,6 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
+ 		for (j = 0; j < adev->num_ip_blocks; j++) {
+ 			block = &adev->ip_blocks[j];
+ 
+-			block->status.hw = false;
+ 			if (block->version->type != ip_order[i] ||
+ 				!block->status.valid)
+ 				continue;
+@@ -2327,7 +2316,6 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
+ 			DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
+ 			if (r)
+ 				return r;
+-			block->status.hw = true;
+ 		}
+ 	}
+ 
+@@ -2355,15 +2343,13 @@ static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
+ 			block = &adev->ip_blocks[j];
+ 
+ 			if (block->version->type != ip_order[i] ||
+-				!block->status.valid ||
+-				block->status.hw)
++				!block->status.valid)
+ 				continue;
+ 
+ 			r = block->version->funcs->hw_init(adev);
+ 			DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
+ 			if (r)
+ 				return r;
+-			block->status.hw = true;
+ 		}
+ 	}
+ 
+@@ -2387,19 +2373,17 @@ static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
+ 	int i, r;
+ 
+ 	for (i = 0; i < adev->num_ip_blocks; i++) {
+-		if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
++		if (!adev->ip_blocks[i].status.valid)
+ 			continue;
+ 		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
+ 		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
+ 		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
+-
+ 			r = adev->ip_blocks[i].version->funcs->resume(adev);
+ 			if (r) {
+ 				DRM_ERROR("resume of IP block <%s> failed %d\n",
+ 					  adev->ip_blocks[i].version->funcs->name, r);
+ 				return r;
+ 			}
+-			adev->ip_blocks[i].status.hw = true;
+ 		}
+ 	}
+ 
+@@ -2424,7 +2408,7 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
+ 	int i, r;
+ 
+ 	for (i = 0; i < adev->num_ip_blocks; i++) {
+-		if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
++		if (!adev->ip_blocks[i].status.valid)
+ 			continue;
+ 		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
+ 		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
+@@ -2437,7 +2421,6 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
+ 				  adev->ip_blocks[i].version->funcs->name, r);
+ 			return r;
+ 		}
+-		adev->ip_blocks[i].status.hw = true;
+ 	}
+ 
+ 	return 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3305-Revert-drm-amd-powerplay-honor-hw-limit-on-fetching-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3305-Revert-drm-amd-powerplay-honor-hw-limit-on-fetching-.patch
new file mode 100644
index 00000000..4ff82a00
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3305-Revert-drm-amd-powerplay-honor-hw-limit-on-fetching-.patch
@@ -0,0 +1,128 @@
+From dae1e634442e27626a54c775d8c235ac5651fcfe Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Mon, 5 Aug 2019 15:43:07 +0800
+Subject: [PATCH 3305/4256] Revert "drm/amd/powerplay: honor hw limit on
+ fetching metrics data for navi10"
+
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 56 +++++++---------------
+ 1 file changed, 18 insertions(+), 38 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index c9a7d26e6c92..b7bb0f78f489 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -515,8 +515,6 @@ static int navi10_store_powerplay_table(struct smu_context *smu)
+ 
+ static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
+ {
+-	struct smu_table_context *smu_table = &smu->smu_table;
+-
+ 	SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
+ 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ 	SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
+@@ -531,35 +529,9 @@ static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
+ 		       sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
+ 	               AMDGPU_GEM_DOMAIN_VRAM);
+ 
+-	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
+-	if (!smu_table->metrics_table)
+-		return -ENOMEM;
+-	smu_table->metrics_time = 0;
+-
+ 	return 0;
+ }
+ 
+-static int navi10_get_metrics_table(struct smu_context *smu,
+-				    SmuMetrics_t *metrics_table)
+-{
+-	struct smu_table_context *smu_table= &smu->smu_table;
+-	int ret = 0;
+-
+-	if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
+-		ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
+-				(void *)smu_table->metrics_table, false);
+-		if (ret) {
+-			pr_info("Failed to export SMU metrics table!\n");
+-			return ret;
+-		}
+-		smu_table->metrics_time = jiffies;
+-	}
+-
+-	memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
+-
+-	return ret;
+-}
+-
+ static int navi10_allocate_dpm_context(struct smu_context *smu)
+ {
+ 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+@@ -646,10 +618,15 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
+ 				       enum smu_clk_type clk_type,
+ 				       uint32_t *value)
+ {
++	static SmuMetrics_t metrics;
+ 	int ret = 0, clk_id = 0;
+-	SmuMetrics_t metrics;
+ 
+-	ret = navi10_get_metrics_table(smu, &metrics);
++	if (!value)
++		return -EINVAL;
++
++	memset(&metrics, 0, sizeof(metrics));
++
++	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -937,9 +914,8 @@ static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
+ 	if (!value)
+ 		return -EINVAL;
+ 
+-	ret = navi10_get_metrics_table(smu, &metrics);
+-	if (ret)
+-		return ret;
++	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics,
++			       false);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -958,7 +934,10 @@ static int navi10_get_current_activity_percent(struct smu_context *smu,
+ 	if (!value)
+ 		return -EINVAL;
+ 
+-	ret = navi10_get_metrics_table(smu, &metrics);
++	msleep(1);
++
++	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
++			       (void *)&metrics, false);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -997,9 +976,10 @@ static int navi10_get_fan_speed_rpm(struct smu_context *smu,
+ 	if (!speed)
+ 		return -EINVAL;
+ 
+-	ret = navi10_get_metrics_table(smu, &metrics);
+-	if (ret)
+-		return ret;
++	memset(&metrics, 0, sizeof(metrics));
++
++	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
++			       (void *)&metrics, false);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -1352,7 +1332,7 @@ static int navi10_thermal_get_temperature(struct smu_context *smu,
+ 	if (!value)
+ 		return -EINVAL;
+ 
+-	ret = navi10_get_metrics_table(smu, &metrics);
++	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
+ 	if (ret)
+ 		return ret;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3306-drm-amd-powerplay-skip-pcie-params-override-on-Arctu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3306-drm-amd-powerplay-skip-pcie-params-override-on-Arctu.patch
new file mode 100644
index 00000000..27939e94
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3306-drm-amd-powerplay-skip-pcie-params-override-on-Arctu.patch
@@ -0,0 +1,42 @@
+From d346b4a0b37bb0a9947eaa55d4f52c29f3b9d9ae Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 5 Aug 2019 14:53:12 +0800
+Subject: [PATCH 3306/4256] drm/amd/powerplay: skip pcie params override on
+ Arcturus V2
+
+This is not supported on Arcturus.
+
+Affected ASIC: Arcturus
+
+V2: minor cosmetic fix
+
+Change-Id: I62a8bce17a070ce4eda5fa22f4b12a7ffa1201cd
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 5ba038260091..f21bafb1a0d2 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1109,11 +1109,11 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ 	if (ret)
+ 		return ret;
+ 
+-	ret = smu_override_pcie_parameters(smu);
+-	if (ret)
+-		return ret;
+-
+ 	if (adev->asic_type != CHIP_ARCTURUS) {
++		ret = smu_override_pcie_parameters(smu);
++		if (ret)
++			return ret;
++
+ 		ret = smu_notify_display_change(smu);
+ 		if (ret)
+ 			return ret;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3307-drm-amdkfd-fix-missing-break-in-kfd2kgd-pointer-init.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3307-drm-amdkfd-fix-missing-break-in-kfd2kgd-pointer-init.patch
new file mode 100644
index 00000000..a8d7d123
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3307-drm-amdkfd-fix-missing-break-in-kfd2kgd-pointer-init.patch
@@ -0,0 +1,34 @@
+From 9ad8d634e50a39f132797984a7a726582d7b937d Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 6 Aug 2019 10:14:17 +0800
+Subject: [PATCH 3307/4256] drm/amdkfd: fix missing break in kfd2kgd pointer
+ init
+
+This seems a cherry-pick error and will break Arcturus KFD.
+
+Needed for hybrid branch only.
+
+Affected ASIC: Arcturus
+
+Change-Id: I4b4d845172144296624cb4c3255d440bcaef4705
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+index 074206458323..8a1ba9c93e12 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+@@ -96,6 +96,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
+ 		break;
+ 	case CHIP_ARCTURUS:
+ 		kfd2kgd = amdgpu_amdkfd_arcturus_get_functions();
++		break;
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+ 	case CHIP_NAVI12:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3308-drm-amd-powerplay-remove-redundancy-debug-log-in-smu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3308-drm-amd-powerplay-remove-redundancy-debug-log-in-smu.patch
new file mode 100644
index 00000000..f167ae22
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3308-drm-amd-powerplay-remove-redundancy-debug-log-in-smu.patch
@@ -0,0 +1,47 @@
+From 183422d9854932f5978d905159127e1fce0f20b3 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Fri, 19 Jul 2019 16:06:29 +0800
+Subject: [PATCH 3308/4256] drm/amd/powerplay: remove redundancy debug log in
+ smu
+
+remove redundacy debug log in smu.
+eg:
+[ 6897.969447] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
+[ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
+[ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
+[ 6899.024114] amdgpu: [powerplay] Unsupported SMU message: 38
+[ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
+[ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
+[ 6899.024152] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
+[ 6900.078296] amdgpu: [powerplay] Unsupported SMU message: 38
+[ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
+[ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
+[ 6900.078333] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
+[ 6901.133230] amdgpu: [powerplay] Unsupported SMU message: 38
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index bf373d5b0e38..d63956ae3f42 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -184,10 +184,8 @@ static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+ 		return -EINVAL;
+ 
+ 	mapping = arcturus_message_map[index];
+-	if (!(mapping.valid_mapping)) {
+-		pr_warn("Unsupported SMU message: %d\n", index);
++	if (!(mapping.valid_mapping))
+ 		return -EINVAL;
+-	}
+ 
+ 	return mapping.map_to;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3309-drm-amdgpu-pin-the-csb-buffer-on-hw-init-for-gfx-v8.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3309-drm-amdgpu-pin-the-csb-buffer-on-hw-init-for-gfx-v8.patch
new file mode 100644
index 00000000..c16ccea9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3309-drm-amdgpu-pin-the-csb-buffer-on-hw-init-for-gfx-v8.patch
@@ -0,0 +1,86 @@
+From 961782c2df0850f9eff178d53e14d12281a9f4f6 Mon Sep 17 00:00:00 2001
+From: Likun Gao <Likun.Gao@amd.com>
+Date: Fri, 2 Aug 2019 15:18:57 +0800
+Subject: [PATCH 3309/4256] drm/amdgpu: pin the csb buffer on hw init for gfx
+ v8
+
+Without this pin, the csb buffer will be filled with inconsistent
+data after S3 resume. And that will causes gfx hang on gfxoff
+exit since this csb will be executed then.
+
+Signed-off-by: Likun Gao <Likun.Gao@amd.com>
+Tested-by: Paul Gover <pmw.gover@yahoo.co.uk>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 40 +++++++++++++++++++++++++++
+ 1 file changed, 40 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index 79ccc4bfb676..bd19af733fa8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -1317,6 +1317,39 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
++static int gfx_v8_0_csb_vram_pin(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
++	if (unlikely(r != 0))
++		return r;
++
++	r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
++			AMDGPU_GEM_DOMAIN_VRAM);
++	if (!r)
++		adev->gfx.rlc.clear_state_gpu_addr =
++			amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
++
++	amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
++
++	return r;
++}
++
++static void gfx_v8_0_csb_vram_unpin(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (!adev->gfx.rlc.clear_state_obj)
++		return;
++
++	r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
++	if (likely(r == 0)) {
++		amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
++		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
++	}
++}
++
+ static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
+ {
+ 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
+@@ -4790,6 +4823,10 @@ static int gfx_v8_0_hw_init(void *handle)
+ 	gfx_v8_0_init_golden_registers(adev);
+ 	gfx_v8_0_constants_init(adev);
+ 
++	r = gfx_v8_0_csb_vram_pin(adev);
++	if (r)
++		return r;
++
+ 	r = adev->gfx.rlc.funcs->resume(adev);
+ 	if (r)
+ 		return r;
+@@ -4906,6 +4943,9 @@ static int gfx_v8_0_hw_fini(void *handle)
+ 	else
+ 		pr_err("rlc is busy, skip halt rlc\n");
+ 	amdgpu_gfx_rlc_exit_safe_mode(adev);
++
++	gfx_v8_0_csb_vram_unpin(adev);
++
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3310-drm-amdgpu-Fix-panic-during-gpu-reset.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3310-drm-amdgpu-Fix-panic-during-gpu-reset.patch
new file mode 100644
index 00000000..8f03bbf5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3310-drm-amdgpu-Fix-panic-during-gpu-reset.patch
@@ -0,0 +1,29 @@
+From 2bee270b22da14a0159663ab5446a7f12d390bd1 Mon Sep 17 00:00:00 2001
+From: xinhui pan <xinhui.pan@amd.com>
+Date: Mon, 5 Aug 2019 14:53:49 +0800
+Subject: [PATCH 3310/4256] drm/amdgpu: Fix panic during gpu reset
+
+Clear the flag after hw suspend, otherwise it skips the corresponding hw
+resume.
+
+Signed-off-by: xinhui pan <xinhui.pan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 59099f040800..6a9b14e68e6e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2241,6 +2241,7 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
+ 			DRM_ERROR("suspend of IP block <%s> failed %d\n",
+ 				  adev->ip_blocks[i].version->funcs->name, r);
+ 		}
++		adev->ip_blocks[i].status.hw = false;
+ 		/* handle putting the SMC in the appropriate state */
+ 		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
+ 			if (is_support_sw_smu(adev)) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3311-drm-amdgpu-update-ras-sysfs-feature-info.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3311-drm-amdgpu-update-ras-sysfs-feature-info.patch
new file mode 100644
index 00000000..80a83a9d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3311-drm-amdgpu-update-ras-sysfs-feature-info.patch
@@ -0,0 +1,51 @@
+From 1efbb5c26892e5bbdf6aa718a7361605f39ee8d9 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Mon, 5 Aug 2019 15:48:30 +0800
+Subject: [PATCH 3311/4256] drm/amdgpu: update ras sysfs feature info
+
+remove confused ras error type info
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 17 +++++------------
+ 1 file changed, 5 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index d2e8a85f6e38..369651247b23 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -787,25 +787,18 @@ static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
+ 	struct amdgpu_device *adev = ddev->dev_private;
+ 	struct ras_common_if head;
+ 	int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
+-	int i;
++	int i, enabled;
+ 	ssize_t s;
+-	struct ras_manager *obj;
+ 
+ 	s = scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
+ 
+ 	for (i = 0; i < ras_block_count; i++) {
+ 		head.block = i;
++		enabled = amdgpu_ras_is_feature_enabled(adev, &head);
+ 
+-		if (amdgpu_ras_is_feature_enabled(adev, &head)) {
+-			obj = amdgpu_ras_find_obj(adev, &head);
+-			s += scnprintf(&buf[s], PAGE_SIZE - s,
+-					"%s: %s\n",
+-					ras_block_str(i),
+-					ras_err_str(obj->head.type));
+-		} else
+-			s += scnprintf(&buf[s], PAGE_SIZE - s,
+-					"%s: disabled\n",
+-					ras_block_str(i));
++		s += scnprintf(&buf[s], PAGE_SIZE - s,
++				"%s ras feature mask: %s\n",
++				ras_block_str(i), enabled?"on":"off");
+ 	}
+ 
+ 	return s;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3312-drm-amdgpu-soc15-fix-external_rev_id-for-navi14.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3312-drm-amdgpu-soc15-fix-external_rev_id-for-navi14.patch
new file mode 100644
index 00000000..14f3ca15
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3312-drm-amdgpu-soc15-fix-external_rev_id-for-navi14.patch
@@ -0,0 +1,30 @@
+From 441a35f5e5cb9298c93fc7d10a10cde22964f327 Mon Sep 17 00:00:00 2001
+From: tiancyin <tianci.yin@amd.com>
+Date: Mon, 5 Aug 2019 17:32:45 +0800
+Subject: [PATCH 3312/4256] drm/amdgpu/soc15: fix external_rev_id for navi14
+
+fix the hard code external_rev_id.
+
+Change-Id: I7b46f7b49b6d0586d1fa282d4961815fb124379b
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: tiancyin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 9614c65fa292..1e2edb561ab9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -612,7 +612,7 @@ static int nv_common_early_init(void *handle)
+ 			AMD_CG_SUPPORT_BIF_LS;
+ 		adev->pg_flags = AMD_PG_SUPPORT_VCN |
+ 			AMD_PG_SUPPORT_VCN_DPG;
+-		adev->external_rev_id = adev->rev_id + 0x1; /* ??? */
++		adev->external_rev_id = adev->rev_id + 20;
+ 		break;
+ 	case CHIP_NAVI12:
+ 		adev->cg_flags = 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3313-drm-amdgpu-discovery-move-common-discovery-code-out-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3313-drm-amdgpu-discovery-move-common-discovery-code-out-.patch
new file mode 100644
index 00000000..169c7899
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3313-drm-amdgpu-discovery-move-common-discovery-code-out-.patch
@@ -0,0 +1,120 @@
+From 62e450325b03d6997bdb6958994562385aec0036 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Mon, 5 Aug 2019 16:19:45 +0800
+Subject: [PATCH 3313/4256] drm/amdgpu/discovery: move common discovery code
+ out of navi1*_reg_base_init()
+
+move amdgpu_discovery_reg_base_init() from navi1*_reg_base_init() to a
+common function nv_reg_base_init().
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c | 14 +---------
+ drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c | 14 +---------
+ drivers/gpu/drm/amd/amdgpu/nv.c              | 29 ++++++++++++++++++--
+ 3 files changed, 29 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
+index 55014ce8670a..a56c93620e78 100644
+--- a/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
++++ b/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
+@@ -29,20 +29,8 @@
+ 
+ int navi10_reg_base_init(struct amdgpu_device *adev)
+ {
+-	int r, i;
++	int i;
+ 
+-	if (amdgpu_discovery) {
+-		r = amdgpu_discovery_reg_base_init(adev);
+-		if (r) {
+-			DRM_WARN("failed to init reg base from ip discovery table, "
+-					"fallback to legacy init method\n");
+-			goto legacy_init;
+-		}
+-
+-		return 0;
+-	}
+-
+-legacy_init:
+ 	for (i = 0 ; i < MAX_INSTANCE ; ++i) {
+ 		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ 		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
+diff --git a/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c b/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c
+index 864668a7f1d2..3b5f0f65e096 100644
+--- a/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c
++++ b/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c
+@@ -29,20 +29,8 @@
+ 
+ int navi14_reg_base_init(struct amdgpu_device *adev)
+ {
+-	int r, i;
++	int i;
+ 
+-	if (amdgpu_discovery) {
+-		r = amdgpu_discovery_reg_base_init(adev);
+-		if (r) {
+-			DRM_WARN("failed to init reg base from ip discovery table, "
+-					"fallback to legacy init method\n");
+-			goto legacy_init;
+-		}
+-
+-		return 0;
+-	}
+-
+-legacy_init:
+ 	for (i = 0 ; i < MAX_INSTANCE ; ++i) {
+ 		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+ 		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 1e2edb561ab9..280ae6ee6ada 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -375,9 +375,22 @@ static const struct amdgpu_ip_block_version nv_common_ip_block =
+ 	.funcs = &nv_common_ip_funcs,
+ };
+ 
+-int nv_set_ip_blocks(struct amdgpu_device *adev)
++static int nv_reg_base_init(struct amdgpu_device *adev)
+ {
+-	/* Set IP register base before any HW register access */
++	int r;
++
++	if (amdgpu_discovery) {
++		r = amdgpu_discovery_reg_base_init(adev);
++		if (r) {
++			DRM_WARN("failed to init reg base from ip discovery table, "
++					"fallback to legacy init method\n");
++			goto legacy_init;
++		}
++
++		return 0;
++	}
++
++legacy_init:
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+ 		navi10_reg_base_init(adev);
+@@ -392,6 +405,18 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ 		return -EINVAL;
+ 	}
+ 
++	return 0;
++}
++
++int nv_set_ip_blocks(struct amdgpu_device *adev)
++{
++	int r;
++
++	/* Set IP register base before any HW register access */
++	r = nv_reg_base_init(adev);
++	if (r)
++		return r;
++
+ 	adev->nbio_funcs = &nbio_v2_3_funcs;
+ 
+ 	adev->nbio_funcs->detect_hw_virt(adev);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3314-drm-amd-powerplay-check-before-issuing-messages-for-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3314-drm-amd-powerplay-check-before-issuing-messages-for-.patch
new file mode 100644
index 00000000..847ecd8c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3314-drm-amd-powerplay-check-before-issuing-messages-for-.patch
@@ -0,0 +1,36 @@
+From 0e0f7c9591c5808ddd116f7c95eda56435f21229 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 6 Aug 2019 16:14:22 +0800
+Subject: [PATCH 3314/4256] drm/amd/powerplay: check before issuing messages
+ for max sustainable clocks
+
+Those messages are not supported on Arcturus and should not be
+issued.
+
+Affected ASIC: Arcturus
+
+Change-Id: I391099fc28e00356234fd2ae7b68f5861fd4c147
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 84eb14a6650f..2ddb4ec75305 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -905,6 +905,10 @@ smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
+ 	if (!smu->pm_enabled)
+ 		return ret;
+ 
++	if ((smu_msg_get_index(smu, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
++	    (smu_msg_get_index(smu, SMU_MSG_GetMaxDpmFreq) < 0))
++		return 0;
++
+ 	clk_id = smu_clk_get_index(smu, clock_select);
+ 	if (clk_id < 0)
+ 		return -EINVAL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3315-drm-amdgpu-Fix-GPU-reset-crash-regression.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3315-drm-amdgpu-Fix-GPU-reset-crash-regression.patch
new file mode 100644
index 00000000..7eab67d3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3315-drm-amdgpu-Fix-GPU-reset-crash-regression.patch
@@ -0,0 +1,32 @@
+From 4bd5c54c2e48773c11225c12af4da663f53b2a47 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Fri, 2 Aug 2019 16:48:08 -0400
+Subject: [PATCH 3315/4256] drm/amdgpu: Fix GPU reset crash regression.
+
+amdgpu_ip_block.status.hw for GMC wasn't set to
+false on suspend during GPU reset and so on resume gmc_v9_0_resume
+wasn't called.
+Caused by 'drm/amdgpu: fix double ucode load by PSP(v3)'
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 6a9b14e68e6e..1f88222d007d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2257,6 +2257,8 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
+ 				}
+ 			}
+ 		}
++
++		adev->ip_blocks[i].status.hw = false;
+ 	}
+ 
+ 	return 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3316-MAINTAINERS-update-amdkfd-maintainer-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3316-MAINTAINERS-update-amdkfd-maintainer-v3.patch
new file mode 100644
index 00000000..e02ed19e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3316-MAINTAINERS-update-amdkfd-maintainer-v3.patch
@@ -0,0 +1,49 @@
+From 434cb993d2c612b5ba32330634c6422a4961ee82 Mon Sep 17 00:00:00 2001
+From: Oded Gabbay <oded.gabbay@gmail.com>
+Date: Thu, 4 Jul 2019 09:32:20 +0300
+Subject: [PATCH 3316/4256] MAINTAINERS: update amdkfd maintainer (v3)
+
+I'm leaving the role of amdkfd maintainer. Therefore, update the relevant
+entry in the MAINTAINERS file with the name of the new maintainer.
+
+Good Luck!
+
+v3: update mailing list, file list (Alex)
+
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> (v2)
+Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ MAINTAINERS | 16 +++++-----------
+ 1 file changed, 5 insertions(+), 11 deletions(-)
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 9e9b19ecf6f7..38f553e09240 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -773,17 +773,11 @@ F:	drivers/iommu/amd_iommu*.[ch]
+ F:	include/linux/amd-iommu.h
+ 
+ AMD KFD
+-M:	Oded Gabbay <oded.gabbay@gmail.com>
+-L:	dri-devel@lists.freedesktop.org
+-T:	git git://people.freedesktop.org/~gabbayo/linux.git
+-S:	Supported
+-F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+-F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+-F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+-F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+-F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+-F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
+-F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++M:	Felix Kuehling <Felix.Kuehling@amd.com>
++L:	amd-gfx@lists.freedesktop.org
++T:	git git://people.freedesktop.org/~agd5f/linux
++S:	Supported
++F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd*.[ch]
+ F:	drivers/gpu/drm/amd/amdkfd/
+ F:	drivers/gpu/drm/amd/include/cik_structs.h
+ F:	drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3317-drm-amd-powerplay-Zero-initialize-some-variables.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3317-drm-amd-powerplay-Zero-initialize-some-variables.patch
new file mode 100644
index 00000000..4adaf15c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3317-drm-amd-powerplay-Zero-initialize-some-variables.patch
@@ -0,0 +1,98 @@
+From 520bc48786cc605d50cfaf803137a2d039d6a391 Mon Sep 17 00:00:00 2001
+From: Nathan Chancellor <natechancellor@gmail.com>
+Date: Sun, 4 Aug 2019 13:37:13 -0700
+Subject: [PATCH 3317/4256] drm/amd/powerplay: Zero initialize some variables
+
+Clang warns (only Navi warning shown but Arcturus warns as well):
+
+drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:1534:4: warning:
+variable 'asic_default_power_limit' is used uninitialized whenever '?:'
+condition is false [-Wsometimes-uninitialized]
+                        smu_read_smc_arg(smu, &asic_default_power_limit);
+                        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amdgpu_smu.h:588:3: note:
+expanded from macro 'smu_read_smc_arg'
+        ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
+         ^~~~~~~~~~~~~~~~~~~~~~~~~~
+drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:1550:30: note:
+uninitialized use occurs here
+                smu->default_power_limit = asic_default_power_limit;
+                                           ^~~~~~~~~~~~~~~~~~~~~~~~
+drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:1534:4: note:
+remove the '?:' if its condition is always true
+                        smu_read_smc_arg(smu, &asic_default_power_limit);
+                        ^
+drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amdgpu_smu.h:588:3: note:
+expanded from macro 'smu_read_smc_arg'
+        ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
+         ^
+drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:1517:35: note:
+initialize the variable 'asic_default_power_limit' to silence this
+warning
+        uint32_t asic_default_power_limit;
+                                         ^
+                                          = 0
+1 warning generated.
+
+As the code is currently written, if read_smc_arg were ever NULL, arg
+would fail to be initialized but the code would continue executing as
+normal because the return value would just be zero.
+
+There are a few different possible solutions to resolve this class
+of warnings which have appeared in these drivers before:
+
+1. Assume the function pointer will never be NULL and eliminate the
+   wrapper macros.
+
+2. Have the wrapper macros initialize arg when the function pointer is
+   NULL.
+
+3. Have the wrapper macros return an error code instead of 0 when the
+   function pointer is NULL so that the callsites can properly bail out
+   before arg can be used.
+
+4. Initialize arg at the top of its function.
+
+Number four is the path of least resistance right now as every other
+change will be driver wide so do that here. I only make the comment
+now as food for thought.
+
+Fixes: b4af964e75c4 ("drm/amd/powerplay: make power limit retrieval as asic specific")
+Link: https://github.com/ClangBuiltLinux/linux/issues/627
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 +-
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c   | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index d63956ae3f42..52e6214c3f22 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -1326,7 +1326,7 @@ static int arcturus_get_power_limit(struct smu_context *smu,
+ 				     bool asic_default)
+ {
+ 	PPTable_t *pptable = smu->smu_table.driver_pptable;
+-	uint32_t asic_default_power_limit;
++	uint32_t asic_default_power_limit = 0;
+ 	int ret = 0;
+ 	int power_src;
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index b7bb0f78f489..96cc2f95d078 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1520,7 +1520,7 @@ static int navi10_get_power_limit(struct smu_context *smu,
+ 				     bool asic_default)
+ {
+ 	PPTable_t *pptable = smu->smu_table.driver_pptable;
+-	uint32_t asic_default_power_limit;
++	uint32_t asic_default_power_limit = 0;
+ 	int ret = 0;
+ 	int power_src;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3318-gpu-drm-amd-powerplay-Remove-logically-dead-code.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3318-gpu-drm-amd-powerplay-Remove-logically-dead-code.patch
new file mode 100644
index 00000000..3194d0ec
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3318-gpu-drm-amd-powerplay-Remove-logically-dead-code.patch
@@ -0,0 +1,32 @@
+From 73c809a562f9fea7f96a10486c0a366d2a922716 Mon Sep 17 00:00:00 2001
+From: Hariprasad Kelam <hariprasad.kelam@gmail.com>
+Date: Mon, 5 Aug 2019 22:51:38 +0530
+Subject: [PATCH 3318/4256] gpu: drm: amd: powerplay: Remove logically dead
+ code
+
+Result of pointer airthmentic is never null
+
+fix coverity defect:1451876
+
+Signed-off-by: Hariprasad Kelam <hariprasad.kelam@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 2ddb4ec75305..c078bf4d522e 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -733,8 +733,6 @@ static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
+ 	struct smu_table *table = NULL;
+ 
+ 	table = &smu_table->tables[SMU_TABLE_WATERMARKS];
+-	if (!table)
+-		return -EINVAL;
+ 
+ 	if (!table->cpu_addr)
+ 		return -EINVAL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3319-drm-amdkfd-Remove-GPU-ID-in-GWS-queue-creation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3319-drm-amdkfd-Remove-GPU-ID-in-GWS-queue-creation.patch
new file mode 100644
index 00000000..d083c98e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3319-drm-amdkfd-Remove-GPU-ID-in-GWS-queue-creation.patch
@@ -0,0 +1,144 @@
+From 35cb67e0d12a865676f588010923a6a305b41bfe Mon Sep 17 00:00:00 2001
+From: Joseph Greathouse <Joseph.Greathouse@amd.com>
+Date: Fri, 26 Jul 2019 19:28:31 -0500
+Subject: [PATCH 3319/4256] drm/amdkfd: Remove GPU ID in GWS queue creation
+
+The gpu_id argument is not needed when enabling GWS on a queue.
+The queue can only be associated with one device, so the only
+possible situations for the call as previously defined were:
+1) the gpu_id was for the device associated with the target queue
+and things worked as expected, or 2) the gpu_id was for a device
+not associated with the target queue and the request was undefined.
+
+In particular, the previous result of the undefined operation is
+that you would allocate the number of GWS entries available on the
+gpu_id device, even if the queue was on a device with a different
+number available. For example: a queue on a device without GWS
+capability, but the user passes in a gpu_id for a device with GWS.
+We would end up trying to allocate GWS on the device that does not
+support it.
+
+Rather than leaving this footgun around and making life more
+difficult for user space, we can instead grab the gpu_id from the
+target queue. The gpu_id argument being passed in is thus not
+needed.
+
+v2: Fixed styling, removed gpu_id since it never hit main release
+
+Change-Id: Ic11a781c98d1dad490f2eb237b5c703eb4be56b8
+Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c      | 25 +++++++++++++------
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h         |  2 ++
+ .../amd/amdkfd/kfd_process_queue_manager.c    |  9 +++++++
+ include/uapi/linux/kfd_ioctl.h                |  3 +--
+ 4 files changed, 30 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index 33381ae358fb..e96aa4eaaa66 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -1611,25 +1611,36 @@ static int kfd_ioctl_alloc_queue_gws(struct file *filep,
+ {
+ 	int retval;
+ 	struct kfd_ioctl_alloc_queue_gws_args *args = data;
++	struct queue *q;
+ 	struct kfd_dev *dev;
+ 
+ 	if (!hws_gws_support)
+ 		return -ENODEV;
+ 
+-	dev = kfd_device_by_id(args->gpu_id);
+-	if (!dev) {
+-		pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
+-		return -ENODEV;
++	mutex_lock(&p->mutex);
++	q = pqm_get_user_queue(&p->pqm, args->queue_id);
++
++	if (q) {
++		dev = q->device;
++	} else {
++		retval = -EINVAL;
++		goto out_unlock;
++	}
++
++	if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
++		retval = -ENODEV;
++		goto out_unlock;
+ 	}
+-	if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
+-		return -ENODEV;
+ 
+-	mutex_lock(&p->mutex);
+ 	retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL);
+ 	mutex_unlock(&p->mutex);
+ 
+ 	args->first_gws = 0;
+ 	return retval;
++
++out_unlock:
++	mutex_unlock(&p->mutex);
++	return retval;
+ }
+ 
+ static int kfd_ioctl_get_dmabuf_info(struct file *filep,
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index 267c2e4d69a0..40c2b0d5a954 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -1035,6 +1035,8 @@ int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid,
+ 			void *gws);
+ struct kernel_queue *pqm_get_kernel_queue(struct process_queue_manager *pqm,
+ 						unsigned int qid);
++struct queue *pqm_get_user_queue(struct process_queue_manager *pqm,
++						unsigned int qid);
+ int pqm_get_wave_state(struct process_queue_manager *pqm,
+ 		       unsigned int qid,
+ 		       void __user *ctl_stack,
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+index 7e6c3ee82f5b..7a61a5b09ed8 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+@@ -473,6 +473,15 @@ struct kernel_queue *pqm_get_kernel_queue(
+ 	return NULL;
+ }
+ 
++struct queue *pqm_get_user_queue(struct process_queue_manager *pqm,
++					unsigned int qid)
++{
++	struct process_queue_node *pqn;
++
++	pqn = get_queue_by_qid(pqm, qid);
++	return pqn ? pqn->q : NULL;
++}
++
+ int pqm_get_wave_state(struct process_queue_manager *pqm,
+ 		       unsigned int qid,
+ 		       void __user *ctl_stack,
+diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
+index 082f28493e14..8c2862565444 100644
+--- a/include/uapi/linux/kfd_ioctl.h
++++ b/include/uapi/linux/kfd_ioctl.h
+@@ -477,17 +477,16 @@ enum kfd_mmio_remap {
+ 
+ /* Allocate GWS for specific queue
+  *
+- * @gpu_id:      device identifier
+  * @queue_id:    queue's id that GWS is allocated for
+  * @num_gws:     how many GWS to allocate
+  * @first_gws:   index of the first GWS allocated.
+  *               only support contiguous GWS allocation
+  */
+ struct kfd_ioctl_alloc_queue_gws_args {
+-	__u32 gpu_id;		/* to KFD */
+ 	__u32 queue_id;		/* to KFD */
+ 	__u32 num_gws;		/* to KFD */
+ 	__u32 first_gws;	/* from KFD */
++	__u32 pad;
+ };
+ 
+ struct kfd_ioctl_get_dmabuf_info_args {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3320-drm-amdgpu-Mark-KFD-VRAM-allocations-for-wipe-on-rel.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3320-drm-amdgpu-Mark-KFD-VRAM-allocations-for-wipe-on-rel.patch
new file mode 100644
index 00000000..96961069
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3320-drm-amdgpu-Mark-KFD-VRAM-allocations-for-wipe-on-rel.patch
@@ -0,0 +1,41 @@
+From 0954dece4cd9593544905479c8ec25f68c4c485e Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Mon, 8 Jul 2019 20:01:22 -0400
+Subject: [PATCH 3320/4256] drm/amdgpu: Mark KFD VRAM allocations for wipe on
+ release
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Memory used by KFD applications can contain sensitive information that
+should not be leaked to other processes. The current approach to prevent
+leaks is to clear VRAM at allocation time. This is not effective because
+memory can be reused in other ways without being cleared. Synchronously
+clearing memory on the allocation path also carries a significant
+performance penalty.
+
+Stop clearing memory at allocation time. Instead mark the memory for
+wipe on release.
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index d144d04d7b0e..580f52eda694 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -1149,7 +1149,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
+ 	 */
+ 	if (flags & ALLOC_MEM_FLAGS_VRAM) {
+ 		domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
+-		alloc_flags = AMDGPU_GEM_CREATE_VRAM_CLEARED;
++		alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
+ 		alloc_flags |= (flags & ALLOC_MEM_FLAGS_PUBLIC) ?
+ 			AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED :
+ 			AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3321-drm-amdgpu-enable-gfx-clock-gating-for-Arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3321-drm-amdgpu-enable-gfx-clock-gating-for-Arcturus.patch
new file mode 100644
index 00000000..c25e84f1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3321-drm-amdgpu-enable-gfx-clock-gating-for-Arcturus.patch
@@ -0,0 +1,34 @@
+From 7166343a08b32ea88d0098568c8f52a865119da3 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Wed, 7 Aug 2019 14:52:38 +0800
+Subject: [PATCH 3321/4256] drm/amdgpu: enable gfx clock gating for Arcturus
+
+Init gfx MGCG/LS and CGCG/LS flag.
+
+Change-Id: I88db76d1b8f2b2cecce10846a4d22eec638eea8a
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 125ba1b15b6a..a2d95342719b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1118,7 +1118,10 @@ static int soc15_common_early_init(void *handle)
+ 		break;
+ 	case CHIP_ARCTURUS:
+ 		adev->asic_funcs = &vega20_asic_funcs;
+-		adev->cg_flags = 0;
++		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
++			AMD_CG_SUPPORT_GFX_MGLS |
++			AMD_CG_SUPPORT_GFX_CGCG |
++			AMD_CG_SUPPORT_GFX_CGLS;
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x32;
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3322-drm-amdgpu-add-hdp-clock-gating-for-Arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3322-drm-amdgpu-add-hdp-clock-gating-for-Arcturus.patch
new file mode 100644
index 00000000..ed4ad876
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3322-drm-amdgpu-add-hdp-clock-gating-for-Arcturus.patch
@@ -0,0 +1,43 @@
+From fe3d20fe72a0c2a3f6d14e16b896badd7dff35c3 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Wed, 7 Aug 2019 15:16:19 +0800
+Subject: [PATCH 3322/4256] drm/amdgpu: add hdp clock gating for Arcturus
+
+Add hdp CGLS for Arcturus in set common clockgating function
+
+Change-Id: I44e392fa5f7653908b36b0902e721d56eed3eb92
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index a2d95342719b..162f9c1d7c8f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1258,7 +1258,8 @@ static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable
+ {
+ 	uint32_t def, data;
+ 
+-	if (adev->asic_type == CHIP_VEGA20) {
++	if (adev->asic_type == CHIP_VEGA20 ||
++		adev->asic_type == CHIP_ARCTURUS) {
+ 		def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
+ 
+ 		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
+@@ -1390,6 +1391,10 @@ static int soc15_common_set_clockgating_state(void *handle,
+ 		soc15_update_rom_medium_grain_clock_gating(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+ 		break;
++	case CHIP_ARCTURUS:
++		soc15_update_hdp_light_sleep(adev,
++				state == AMD_CG_STATE_GATE ? true : false);
++		break;
+ 	default:
+ 		break;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3323-drm-amdgpu-enable-hdp-clock-gating-for-Arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3323-drm-amdgpu-enable-hdp-clock-gating-for-Arcturus.patch
new file mode 100644
index 00000000..04c0a92b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3323-drm-amdgpu-enable-hdp-clock-gating-for-Arcturus.patch
@@ -0,0 +1,33 @@
+From 8c6891009d48c0c8b3f9aa98a50e3fe695df58b9 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Wed, 7 Aug 2019 15:17:38 +0800
+Subject: [PATCH 3323/4256] drm/amdgpu: enable hdp clock gating for Arcturus
+
+Init hdp MGCG/LS flag as Vega20
+
+Change-Id: Ia33ca064f79ac409c53d3beb6f01b6e814a92041
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 162f9c1d7c8f..ccc040c14399 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1121,7 +1121,9 @@ static int soc15_common_early_init(void *handle)
+ 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+ 			AMD_CG_SUPPORT_GFX_MGLS |
+ 			AMD_CG_SUPPORT_GFX_CGCG |
+-			AMD_CG_SUPPORT_GFX_CGLS;
++			AMD_CG_SUPPORT_GFX_CGLS |
++			AMD_CG_SUPPORT_HDP_MGCG |
++			AMD_CG_SUPPORT_HDP_LS;
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x32;
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3324-drm-amdgpu-support-sdma-clock-gating-for-more-instan.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3324-drm-amdgpu-support-sdma-clock-gating-for-more-instan.patch
new file mode 100644
index 00000000..83001590
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3324-drm-amdgpu-support-sdma-clock-gating-for-more-instan.patch
@@ -0,0 +1,154 @@
+From 8dc0c3a6785b524ec831b1414674e8110cee966f Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Wed, 7 Aug 2019 15:45:25 +0800
+Subject: [PATCH 3324/4256] drm/amdgpu: support sdma clock gating for more
+ instances
+
+Shorten the code with RREG32_SDMA/WREG32_SDMA macro in CG part.
+
+Change-Id: Icbf94169bb703877b105a307f14c708609faaae4
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 105 ++++++++-----------------
+ 1 file changed, 34 insertions(+), 71 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index af80f3782811..84ad12c1e601 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -2085,61 +2085,35 @@ static void sdma_v4_0_update_medium_grain_clock_gating(
+ 		bool enable)
+ {
+ 	uint32_t data, def;
++	int i;
+ 
+ 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
+-		/* enable sdma0 clock gating */
+-		def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
+-		data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
+-			  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
+-			  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
+-			  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
+-			  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
+-			  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
+-			  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
+-			  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
+-		if (def != data)
+-			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
+-
+-		if (adev->sdma.num_instances > 1) {
+-			def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
+-			data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
+-				  SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
+-				  SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
+-				  SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
+-				  SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
+-				  SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
+-				  SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
+-				  SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
++		for (i = 0; i < adev->sdma.num_instances; i++) {
++			def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
++			data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
++				  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
++				  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
++				  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
++				  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
++				  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
++				  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
++				  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
+ 			if (def != data)
+-				WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
++				WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
+ 		}
+ 	} else {
+-		/* disable sdma0 clock gating */
+-		def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
+-		data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
+-			 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
+-			 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
+-			 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
+-			 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
+-			 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
+-			 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
+-			 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
+-
+-		if (def != data)
+-			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
+-
+-		if (adev->sdma.num_instances > 1) {
+-			def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
+-			data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
+-				 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
+-				 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
+-				 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
+-				 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
+-				 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
+-				 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
+-				 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
++		for (i = 0; i < adev->sdma.num_instances; i++) {
++			def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
++			data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
++				 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
++				 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
++				 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
++				 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
++				 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
++				 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
++				 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
+ 			if (def != data)
+-				WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
++				WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
+ 		}
+ 	}
+ }
+@@ -2150,34 +2124,23 @@ static void sdma_v4_0_update_medium_grain_light_sleep(
+ 		bool enable)
+ {
+ 	uint32_t data, def;
++	int i;
+ 
+ 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
+-		/* 1-not override: enable sdma0 mem light sleep */
+-		def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
+-		data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
+-		if (def != data)
+-			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
+-
+-		/* 1-not override: enable sdma1 mem light sleep */
+-		if (adev->sdma.num_instances > 1) {
+-			def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
+-			data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
++		for (i = 0; i < adev->sdma.num_instances; i++) {
++			/* 1-not override: enable sdma mem light sleep */
++			def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
++			data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
+ 			if (def != data)
+-				WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
++				WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
+ 		}
+ 	} else {
+-		/* 0-override:disable sdma0 mem light sleep */
+-		def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
+-		data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
+-		if (def != data)
+-			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
+-
+-		/* 0-override:disable sdma1 mem light sleep */
+-		if (adev->sdma.num_instances > 1) {
+-			def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
+-			data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
++		for (i = 0; i < adev->sdma.num_instances; i++) {
++		/* 0-override:disable sdma mem light sleep */
++			def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
++			data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
+ 			if (def != data)
+-				WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
++				WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
+ 		}
+ 	}
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3325-drm-amdgpu-add-sdma-clock-gating-for-Arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3325-drm-amdgpu-add-sdma-clock-gating-for-Arcturus.patch
new file mode 100644
index 00000000..07075bb0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3325-drm-amdgpu-add-sdma-clock-gating-for-Arcturus.patch
@@ -0,0 +1,30 @@
+From 053b93da1aee75de5e63f22cbc27d8ff2b9ac10e Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Wed, 7 Aug 2019 15:47:34 +0800
+Subject: [PATCH 3325/4256] drm/amdgpu: add sdma clock gating for Arcturus
+
+Add ARCTURUS case in sdma set clockgating function
+
+Change-Id: I65a3d99a140a8a76949b4d03c20bc6e0195c9854
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 84ad12c1e601..08774110bcbb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -2158,6 +2158,7 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
+ 	case CHIP_VEGA12:
+ 	case CHIP_VEGA20:
+ 	case CHIP_RAVEN:
++	case CHIP_ARCTURUS:
+ 		sdma_v4_0_update_medium_grain_clock_gating(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+ 		sdma_v4_0_update_medium_grain_light_sleep(adev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3326-drm-amdgpu-enable-sdma-clock-gating-for-Arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3326-drm-amdgpu-enable-sdma-clock-gating-for-Arcturus.patch
new file mode 100644
index 00000000..5bc01774
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3326-drm-amdgpu-enable-sdma-clock-gating-for-Arcturus.patch
@@ -0,0 +1,33 @@
+From 2b853dab6998d8a72fd8b588c7f0820a8b329200 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Wed, 7 Aug 2019 15:48:44 +0800
+Subject: [PATCH 3326/4256] drm/amdgpu: enable sdma clock gating for Arcturus
+
+Init sdma MGCG/LS flag
+
+Change-Id: I600b8c67b1dfa74240269f2f028960b2c93a0ec2
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index ccc040c14399..261493a6c49f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1123,7 +1123,9 @@ static int soc15_common_early_init(void *handle)
+ 			AMD_CG_SUPPORT_GFX_CGCG |
+ 			AMD_CG_SUPPORT_GFX_CGLS |
+ 			AMD_CG_SUPPORT_HDP_MGCG |
+-			AMD_CG_SUPPORT_HDP_LS;
++			AMD_CG_SUPPORT_HDP_LS |
++			AMD_CG_SUPPORT_SDMA_MGCG |
++			AMD_CG_SUPPORT_SDMA_LS;
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x32;
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3327-drm-amdgpu-split-athub-clock-gating-from-mmhub.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3327-drm-amdgpu-split-athub-clock-gating-from-mmhub.patch
new file mode 100644
index 00000000..121da08f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3327-drm-amdgpu-split-athub-clock-gating-from-mmhub.patch
@@ -0,0 +1,319 @@
+From 121ba769169c7575536154b26ea5d14788fe00ff Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Thu, 8 Aug 2019 14:54:12 +0800
+Subject: [PATCH 3327/4256] drm/amdgpu: split athub clock gating from mmhub
+
+Untie the bind of get/set athub CG state from mmhub, for cosmetic fix and Asic
+not using mmhub 1.0. Besides, also fix wrong athub CG state in amdgpu_pm_info.
+
+Change-Id: I4ba970cae558ad5163e93fa9bc77f589196a22b1
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile     |   1 +
+ drivers/gpu/drm/amd/amdgpu/athub_v1_0.c | 103 ++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/athub_v1_0.h |  30 +++++++
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |   9 ++-
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c |  55 +++----------
+ 5 files changed, 154 insertions(+), 44 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/athub_v1_0.c
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/athub_v1_0.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index 651d77c59ba3..c82efd378f1d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -154,6 +154,7 @@ amdgpu-y += \
+ 
+ # add ATHUB block
+ amdgpu-y += \
++	athub_v1_0.o \
+ 	athub_v2_0.o
+ 
+ # add amdkfd interfaces
+diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/athub_v1_0.c
+new file mode 100644
+index 000000000000..d9cc746af5e6
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/athub_v1_0.c
+@@ -0,0 +1,103 @@
++/*
++ * Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "amdgpu.h"
++#include "athub_v1_0.h"
++
++#include "athub/athub_1_0_offset.h"
++#include "athub/athub_1_0_sh_mask.h"
++#include "vega10_enum.h"
++
++#include "soc15_common.h"
++
++static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev,
++						   bool enable)
++{
++	uint32_t def, data;
++
++	def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
++
++	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
++		data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
++	else
++		data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
++
++	if (def != data)
++		WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
++}
++
++static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev,
++						  bool enable)
++{
++	uint32_t def, data;
++
++	def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
++
++	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
++	    (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
++		data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
++	else
++		data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
++
++	if(def != data)
++		WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
++}
++
++int athub_v1_0_set_clockgating(struct amdgpu_device *adev,
++			       enum amd_clockgating_state state)
++{
++	if (amdgpu_sriov_vf(adev))
++		return 0;
++
++	switch (adev->asic_type) {
++	case CHIP_VEGA10:
++	case CHIP_VEGA12:
++	case CHIP_VEGA20:
++	case CHIP_RAVEN:
++		athub_update_medium_grain_clock_gating(adev,
++				state == AMD_CG_STATE_GATE ? true : false);
++		athub_update_medium_grain_light_sleep(adev,
++				state == AMD_CG_STATE_GATE ? true : false);
++		break;
++	default:
++		break;
++	}
++
++	return 0;
++}
++
++void athub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
++{
++	int data;
++
++	if (amdgpu_sriov_vf(adev))
++		*flags = 0;
++
++	/* AMD_CG_SUPPORT_ATHUB_MGCG */
++	data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
++	if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
++		*flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
++
++	/* AMD_CG_SUPPORT_ATHUB_LS */
++	if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
++		*flags |= AMD_CG_SUPPORT_ATHUB_LS;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v1_0.h b/drivers/gpu/drm/amd/amdgpu/athub_v1_0.h
+new file mode 100644
+index 000000000000..b279af59e34f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/athub_v1_0.h
+@@ -0,0 +1,30 @@
++/*
++ * Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __ATHUB_V1_0_H__
++#define __ATHUB_V1_0_H__
++
++int athub_v1_0_set_clockgating(struct amdgpu_device *adev,
++			       enum amd_clockgating_state state);
++void athub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 41c4f6fea273..56c8de2fb15c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -43,6 +43,7 @@
+ 
+ #include "gfxhub_v1_0.h"
+ #include "mmhub_v1_0.h"
++#include "athub_v1_0.h"
+ #include "gfxhub_v1_1.h"
+ #include "mmhub_v9_4.h"
+ #include "umc_v6_1.h"
+@@ -1403,7 +1404,11 @@ static int gmc_v9_0_set_clockgating_state(void *handle,
+ 	if (adev->asic_type == CHIP_ARCTURUS)
+ 		return 0;
+ 
+-	return mmhub_v1_0_set_clockgating(adev, state);
++	mmhub_v1_0_set_clockgating(adev, state);
++
++	athub_v1_0_set_clockgating(adev, state);
++
++	return 0;
+ }
+ 
+ static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
+@@ -1414,6 +1419,8 @@ static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
+ 		return;
+ 
+ 	mmhub_v1_0_get_clockgating(adev, flags);
++
++	athub_v1_0_get_clockgating(adev, flags);
+ }
+ 
+ static int gmc_v9_0_set_powergating_state(void *handle,
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index df0117df45a9..da214ca06cee 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -26,8 +26,6 @@
+ #include "mmhub/mmhub_1_0_offset.h"
+ #include "mmhub/mmhub_1_0_sh_mask.h"
+ #include "mmhub/mmhub_1_0_default.h"
+-#include "athub/athub_1_0_offset.h"
+-#include "athub/athub_1_0_sh_mask.h"
+ #include "vega10_enum.h"
+ 
+ #include "soc15_common.h"
+@@ -491,22 +489,6 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
+ 		WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);
+ }
+ 
+-static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+-						   bool enable)
+-{
+-	uint32_t def, data;
+-
+-	def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
+-
+-	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
+-		data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
+-	else
+-		data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
+-
+-	if (def != data)
+-		WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
+-}
+-
+ static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+ 						       bool enable)
+ {
+@@ -523,23 +505,6 @@ static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
+ 		WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
+ }
+ 
+-static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+-						  bool enable)
+-{
+-	uint32_t def, data;
+-
+-	def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
+-
+-	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
+-	    (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
+-		data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
+-	else
+-		data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
+-
+-	if(def != data)
+-		WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
+-}
+-
+ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
+ 			       enum amd_clockgating_state state)
+ {
+@@ -553,12 +518,8 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
+ 	case CHIP_RAVEN:
+ 		mmhub_v1_0_update_medium_grain_clock_gating(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+-		athub_update_medium_grain_clock_gating(adev,
+-				state == AMD_CG_STATE_GATE ? true : false);
+ 		mmhub_v1_0_update_medium_grain_light_sleep(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+-		athub_update_medium_grain_light_sleep(adev,
+-				state == AMD_CG_STATE_GATE ? true : false);
+ 		break;
+ 	default:
+ 		break;
+@@ -569,18 +530,26 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
+ 
+ void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
+ {
+-	int data;
++	int data, data1;
+ 
+ 	if (amdgpu_sriov_vf(adev))
+ 		*flags = 0;
+ 
++	data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
++
++	data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
++
+ 	/* AMD_CG_SUPPORT_MC_MGCG */
+-	data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
+-	if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
++	if ((data & ATC_L2_MISC_CG__ENABLE_MASK) &&
++	    !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
++		       DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
++		       DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
++		       DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
++		       DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
++		       DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
+ 		*flags |= AMD_CG_SUPPORT_MC_MGCG;
+ 
+ 	/* AMD_CG_SUPPORT_MC_LS */
+-	data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
+ 	if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
+ 		*flags |= AMD_CG_SUPPORT_MC_LS;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3328-drm-amdgpu-add-GFX_CP_LS-flag-to-Arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3328-drm-amdgpu-add-GFX_CP_LS-flag-to-Arcturus.patch
new file mode 100644
index 00000000..ab9b8005
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3328-drm-amdgpu-add-GFX_CP_LS-flag-to-Arcturus.patch
@@ -0,0 +1,30 @@
+From 7e90ac15519fa8f8628ad091e81f73957f7f0269 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 9 Aug 2019 15:24:56 +0800
+Subject: [PATCH 3328/4256] drm/amdgpu: add GFX_CP_LS flag to Arcturus
+
+Missed AMD_CG_SUPPORT_GFX_CP_LS accidently when commit patch before
+    drm/amdgpu: enable gfx clock gating for Arcturus
+
+Change-Id: I9d70319dd07f7d642416cb260f9f5b3342b6f3f2
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 261493a6c49f..aecba1cff555 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1122,6 +1122,7 @@ static int soc15_common_early_init(void *handle)
+ 			AMD_CG_SUPPORT_GFX_MGLS |
+ 			AMD_CG_SUPPORT_GFX_CGCG |
+ 			AMD_CG_SUPPORT_GFX_CGLS |
++			AMD_CG_SUPPORT_GFX_CP_LS |
+ 			AMD_CG_SUPPORT_HDP_MGCG |
+ 			AMD_CG_SUPPORT_HDP_LS |
+ 			AMD_CG_SUPPORT_SDMA_MGCG |
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3329-drm-amdgpu-increase-CGCG-gfx-idle-threshold-for-Arct.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3329-drm-amdgpu-increase-CGCG-gfx-idle-threshold-for-Arct.patch
new file mode 100644
index 00000000..b695403b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3329-drm-amdgpu-increase-CGCG-gfx-idle-threshold-for-Arct.patch
@@ -0,0 +1,37 @@
+From 0879632dc82a1b84522bec8129a9c568abe6bd16 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 9 Aug 2019 15:13:38 +0800
+Subject: [PATCH 3329/4256] drm/amdgpu: increase CGCG gfx idle threshold for
+ Arcturus
+
+Follow the hw spec, and no need to consider gfxoff on Arcturus
+
+Change-Id: Ib9cad79b1b9c096014447fc0a7d29cdb594e15e3
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index c04cf92214e1..713f73ac1c61 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4685,8 +4685,12 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
+ 		/* enable cgcg FSM(0x0000363F) */
+ 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
+ 
+-		data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
+-			RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
++		if (adev->asic_type == CHIP_ARCTURUS)
++			data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
++				RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
++		else
++			data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
++				RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
+ 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
+ 			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
+ 				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3330-drm-amdgpu-add-mmhub-clock-gating-for-Arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3330-drm-amdgpu-add-mmhub-clock-gating-for-Arcturus.patch
new file mode 100644
index 00000000..8c7e5edc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3330-drm-amdgpu-add-mmhub-clock-gating-for-Arcturus.patch
@@ -0,0 +1,196 @@
+From 2c614d796ad5cfaf4d019918ad0cae5b08acf71a Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 9 Aug 2019 18:57:15 +0800
+Subject: [PATCH 3330/4256] drm/amdgpu: add mmhub clock gating for Arcturus
+
+Add 2 mmhub instances CG
+
+Change-Id: I76ab7a50cd9a40de3022f733787b42e4e5c4dbf5
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |  12 +--
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 126 ++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h |   3 +
+ 3 files changed, 135 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 56c8de2fb15c..004ae69c8def 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -1402,9 +1402,9 @@ static int gmc_v9_0_set_clockgating_state(void *handle,
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
+ 	if (adev->asic_type == CHIP_ARCTURUS)
+-		return 0;
+-
+-	mmhub_v1_0_set_clockgating(adev, state);
++		mmhub_v9_4_set_clockgating(adev, state);
++	else
++		mmhub_v1_0_set_clockgating(adev, state);
+ 
+ 	athub_v1_0_set_clockgating(adev, state);
+ 
+@@ -1416,9 +1416,9 @@ static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
+ 	if (adev->asic_type == CHIP_ARCTURUS)
+-		return;
+-
+-	mmhub_v1_0_get_clockgating(adev, flags);
++		mmhub_v9_4_get_clockgating(adev, flags);
++	else
++		mmhub_v1_0_get_clockgating(adev, flags);
+ 
+ 	athub_v1_0_get_clockgating(adev, flags);
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+index 33b0de54a5da..e52e4d1860f5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+@@ -515,3 +515,129 @@ void mmhub_v9_4_init(struct amdgpu_device *adev)
+ 				    i * MMHUB_INSTANCE_REGISTER_OFFSET;
+ 	}
+ }
++
++static void mmhub_v9_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
++							bool enable)
++{
++	uint32_t def, data, def1, data1;
++	int i, j;
++	int dist = mmDAGB1_CNTL_MISC2 - mmDAGB0_CNTL_MISC2;
++
++	for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
++		def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
++					mmATCL2_0_ATC_L2_MISC_CG,
++					i * MMHUB_INSTANCE_REGISTER_OFFSET);
++
++		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
++			data |= ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
++		else
++			data &= ~ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
++
++		if (def != data)
++			WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
++				i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
++
++		for (j = 0; j < 5; j++) {
++			def1 = data1 = RREG32_SOC15_OFFSET(MMHUB, 0,
++					mmDAGB0_CNTL_MISC2,
++					i * MMHUB_INSTANCE_REGISTER_OFFSET +
++					j * dist);
++			if (enable &&
++			    (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
++				data1 &=
++				    ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
++				    DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
++				    DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
++				    DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
++				    DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
++				    DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
++			} else {
++				data1 |=
++				    (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
++				    DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
++				    DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
++				    DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
++				    DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
++				    DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
++			}
++
++			if (def1 != data1)
++				WREG32_SOC15_OFFSET(MMHUB, 0,
++					mmDAGB0_CNTL_MISC2,
++					i * MMHUB_INSTANCE_REGISTER_OFFSET +
++					j * dist, data1);
++
++			if (i == 1 && j == 3)
++				break;
++		}
++	}
++}
++
++static void mmhub_v9_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
++						       bool enable)
++{
++	uint32_t def, data;
++	int i;
++
++	for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
++		def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
++					mmATCL2_0_ATC_L2_MISC_CG,
++					i * MMHUB_INSTANCE_REGISTER_OFFSET);
++
++		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
++			data |= ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
++		else
++			data &= ~ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
++
++		if (def != data)
++			WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
++				i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
++	}
++}
++
++int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
++			       enum amd_clockgating_state state)
++{
++	if (amdgpu_sriov_vf(adev))
++		return 0;
++
++	switch (adev->asic_type) {
++	case CHIP_ARCTURUS:
++		mmhub_v9_4_update_medium_grain_clock_gating(adev,
++				state == AMD_CG_STATE_GATE ? true : false);
++		mmhub_v9_4_update_medium_grain_light_sleep(adev,
++				state == AMD_CG_STATE_GATE ? true : false);
++		break;
++	default:
++		break;
++	}
++
++	return 0;
++}
++
++/* TODO: get 2 mmhub instances CG state */
++void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags)
++{
++	int data, data1;
++
++	if (amdgpu_sriov_vf(adev))
++		*flags = 0;
++
++	/* AMD_CG_SUPPORT_MC_MGCG */
++	data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
++
++	data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
++
++	if ((data & ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK) &&
++	    !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
++		       DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
++		       DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
++		       DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
++		       DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
++		       DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
++		*flags |= AMD_CG_SUPPORT_MC_MGCG;
++
++	/* AMD_CG_SUPPORT_MC_LS */
++	if (data & ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
++		*flags |= AMD_CG_SUPPORT_MC_LS;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
+index 9ba3dd808826..d435cfcec1a8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
+@@ -29,5 +29,8 @@ void mmhub_v9_4_gart_disable(struct amdgpu_device *adev);
+ void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev,
+ 					 bool value);
+ void mmhub_v9_4_init(struct amdgpu_device *adev);
++int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
++			       enum amd_clockgating_state state);
++void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags);
+ 
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3331-drm-amdgpu-enable-mmhub-clock-gating-for-Arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3331-drm-amdgpu-enable-mmhub-clock-gating-for-Arcturus.patch
new file mode 100644
index 00000000..d6886c00
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3331-drm-amdgpu-enable-mmhub-clock-gating-for-Arcturus.patch
@@ -0,0 +1,45 @@
+From ebeb541f2501c232fa3492daab032207a3f27f84 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 9 Aug 2019 18:58:42 +0800
+Subject: [PATCH 3331/4256] drm/amdgpu: enable mmhub clock gating for Arcturus
+
+Init MC_MGCG/LS flag. Also apply to athub CG.
+
+Change-Id: Ic00cb8e6d69eb75dd32f34f778352cee93063ee0
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 1 -
+ drivers/gpu/drm/amd/amdgpu/soc15.c      | 4 +++-
+ 2 files changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+index e52e4d1860f5..0cf7ef44b4b5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+@@ -615,7 +615,6 @@ int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
+ 	return 0;
+ }
+ 
+-/* TODO: get 2 mmhub instances CG state */
+ void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags)
+ {
+ 	int data, data1;
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index aecba1cff555..235cb5b156b9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1126,7 +1126,9 @@ static int soc15_common_early_init(void *handle)
+ 			AMD_CG_SUPPORT_HDP_MGCG |
+ 			AMD_CG_SUPPORT_HDP_LS |
+ 			AMD_CG_SUPPORT_SDMA_MGCG |
+-			AMD_CG_SUPPORT_SDMA_LS;
++			AMD_CG_SUPPORT_SDMA_LS |
++			AMD_CG_SUPPORT_MC_MGCG |
++			AMD_CG_SUPPORT_MC_LS;
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x32;
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3332-drm-amdgpu-add-gfx-clock-gating-for-Arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3332-drm-amdgpu-add-gfx-clock-gating-for-Arcturus.patch
new file mode 100644
index 00000000..9c303f29
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3332-drm-amdgpu-add-gfx-clock-gating-for-Arcturus.patch
@@ -0,0 +1,40 @@
+From 639ab65f508441a7937a0d73b3e5723f683283c2 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Wed, 7 Aug 2019 14:59:07 +0800
+Subject: [PATCH 3332/4256] drm/amdgpu: add gfx clock gating for Arcturus
+
+Add ARCTURUS case in gfx set clockgating function. No 3d clock on Arcturus.
+
+Change-Id: I9893a2afea7f0b5d433baa14f48ae55a36516fac
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 713f73ac1c61..56faabc8fb13 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4620,6 +4620,9 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
+ {
+ 	uint32_t data, def;
+ 
++	if (adev->asic_type == CHIP_ARCTURUS)
++		return;
++
+ 	amdgpu_gfx_rlc_enter_safe_mode(adev);
+ 
+ 	/* Enable 3D CGCG/CGLS */
+@@ -4816,6 +4819,7 @@ static int gfx_v9_0_set_clockgating_state(void *handle,
+ 	case CHIP_VEGA12:
+ 	case CHIP_VEGA20:
+ 	case CHIP_RAVEN:
++	case CHIP_ARCTURUS:
+ 		gfx_v9_0_update_gfx_clock_gating(adev,
+ 						 state == AMD_CG_STATE_GATE ? true : false);
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3333-drm-amdgpu-replace-readq-writeq-with-atomic64-operat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3333-drm-amdgpu-replace-readq-writeq-with-atomic64-operat.patch
new file mode 100644
index 00000000..8613a9ca
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3333-drm-amdgpu-replace-readq-writeq-with-atomic64-operat.patch
@@ -0,0 +1,47 @@
+From 0e0db070470423c2bf31c24f4664003d34881680 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Wed, 7 Aug 2019 10:28:54 +0800
+Subject: [PATCH 3333/4256] drm/amdgpu: replace readq/writeq with atomic64
+ operations
+
+what we really want is a read or write that is guaranteed to be 64 bits
+at a time, atomic64 operations are supported on all architectures
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++------
+ 1 file changed, 2 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 1f88222d007d..5bfc5391155b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -272,14 +272,10 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
+  */
+ uint64_t amdgpu_mm_rreg64(struct amdgpu_device *adev, uint32_t reg)
+ {
+-	uint64_t ret;
+-
+ 	if ((reg * 4) < adev->rmmio_size)
+-		ret = readq(((void __iomem *)adev->rmmio) + (reg * 4));
++		return atomic64_read((atomic64_t *)(adev->rmmio + (reg * 4)));
+ 	else
+ 		BUG();
+-
+-	return ret;
+ }
+ 
+ /**
+@@ -294,7 +290,7 @@ uint64_t amdgpu_mm_rreg64(struct amdgpu_device *adev, uint32_t reg)
+ void amdgpu_mm_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
+ {
+ 	if ((reg * 4) < adev->rmmio_size)
+-		writeq(v, ((void __iomem *)adev->rmmio) + (reg * 4));
++		atomic64_set((atomic64_t *)(adev->rmmio + (reg * 4)), v);
+ 	else
+ 		BUG();
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3334-drm-amdgpu-enable-gfx-clock-gatings-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3334-drm-amdgpu-enable-gfx-clock-gatings-for-navi12.patch
new file mode 100644
index 00000000..24ebcaaf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3334-drm-amdgpu-enable-gfx-clock-gatings-for-navi12.patch
@@ -0,0 +1,41 @@
+From 5ee32dfe61357c681bddda36ba128cc42a35c6e5 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Tue, 30 Jul 2019 11:28:20 +0800
+Subject: [PATCH 3334/4256] drm/amdgpu: enable gfx clock gatings for navi12
+
+enables following gfx clock gating features:
+
+- medium grained clock gating
+- medium grained light sleep
+- coarse grained clock gating
+- cp memory light sleep
+- rlc memory light sleep
+
+CGLS (Coarse Grained Light Sleep) will break s3, so don't enable it.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 280ae6ee6ada..056f0467419b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -640,7 +640,11 @@ static int nv_common_early_init(void *handle)
+ 		adev->external_rev_id = adev->rev_id + 20;
+ 		break;
+ 	case CHIP_NAVI12:
+-		adev->cg_flags = 0;
++		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
++			AMD_CG_SUPPORT_GFX_MGLS |
++			AMD_CG_SUPPORT_GFX_CGCG |
++			AMD_CG_SUPPORT_GFX_CP_LS |
++			AMD_CG_SUPPORT_GFX_RLC_LS;
+ 		adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
+ 		adev->external_rev_id = adev->rev_id + 0xa;
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3335-drm-amdgpu-enable-hdp-clock-gating-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3335-drm-amdgpu-enable-hdp-clock-gating-for-navi12.patch
new file mode 100644
index 00000000..0995b76d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3335-drm-amdgpu-enable-hdp-clock-gating-for-navi12.patch
@@ -0,0 +1,31 @@
+From c9c507655dde5f5374da43859858c24e2ea013f9 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 1 Aug 2019 15:00:28 +0800
+Subject: [PATCH 3335/4256] drm/amdgpu: enable hdp clock gating for navi12
+
+enables hdp medium grained clock gating and memory light sleep
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 056f0467419b..804388b44c86 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -644,7 +644,9 @@ static int nv_common_early_init(void *handle)
+ 			AMD_CG_SUPPORT_GFX_MGLS |
+ 			AMD_CG_SUPPORT_GFX_CGCG |
+ 			AMD_CG_SUPPORT_GFX_CP_LS |
+-			AMD_CG_SUPPORT_GFX_RLC_LS;
++			AMD_CG_SUPPORT_GFX_RLC_LS |
++			AMD_CG_SUPPORT_HDP_MGCG |
++			AMD_CG_SUPPORT_HDP_LS;
+ 		adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
+ 		adev->external_rev_id = adev->rev_id + 0xa;
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3336-drm-amdgpu-sdma5-set-sdma-clock-gating-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3336-drm-amdgpu-sdma5-set-sdma-clock-gating-for-navi12.patch
new file mode 100644
index 00000000..eb245a7e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3336-drm-amdgpu-sdma5-set-sdma-clock-gating-for-navi12.patch
@@ -0,0 +1,28 @@
+From 510c544d0fe52b067d17c2ba151dba030d68d2d8 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Tue, 30 Jul 2019 12:16:02 +0800
+Subject: [PATCH 3336/4256] drm/amdgpu/sdma5: set sdma clock gating for navi12
+
+add navi12 define
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+index 4d30b3ff5c35..41932d8b88c3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+@@ -1513,6 +1513,7 @@ static int sdma_v5_0_set_clockgating_state(void *handle,
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 		sdma_v5_0_update_medium_grain_clock_gating(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+ 		sdma_v5_0_update_medium_grain_light_sleep(adev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3337-drm-amdgpu-enable-sdma-clock-gating-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3337-drm-amdgpu-enable-sdma-clock-gating-for-navi12.patch
new file mode 100644
index 00000000..0134364f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3337-drm-amdgpu-enable-sdma-clock-gating-for-navi12.patch
@@ -0,0 +1,31 @@
+From bf2fddb5d39c6044d59c2e002dd998d1c92ad176 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Tue, 30 Jul 2019 12:18:55 +0800
+Subject: [PATCH 3337/4256] drm/amdgpu: enable sdma clock gating for navi12
+
+enables sdma medium grained clock gating and memory light sleep
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 804388b44c86..5a84b89eeaa4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -646,7 +646,9 @@ static int nv_common_early_init(void *handle)
+ 			AMD_CG_SUPPORT_GFX_CP_LS |
+ 			AMD_CG_SUPPORT_GFX_RLC_LS |
+ 			AMD_CG_SUPPORT_HDP_MGCG |
+-			AMD_CG_SUPPORT_HDP_LS;
++			AMD_CG_SUPPORT_HDP_LS |
++			AMD_CG_SUPPORT_SDMA_MGCG |
++			AMD_CG_SUPPORT_SDMA_LS;
+ 		adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
+ 		adev->external_rev_id = adev->rev_id + 0xa;
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3338-drm-amdgpu-mmhub2-set-clock-gating-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3338-drm-amdgpu-mmhub2-set-clock-gating-for-navi12.patch
new file mode 100644
index 00000000..03a0ee0c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3338-drm-amdgpu-mmhub2-set-clock-gating-for-navi12.patch
@@ -0,0 +1,28 @@
+From fd3752aa19f6988d0757924242b62f533afe3cd0 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 1 Aug 2019 15:47:15 +0800
+Subject: [PATCH 3338/4256] drm/amdgpu/mmhub2: set clock gating for navi12
+
+add navi12 define
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+index d2f4775299c7..8ee1225d1a18 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+@@ -407,6 +407,7 @@ int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 		mmhub_v2_0_update_medium_grain_clock_gating(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+ 		mmhub_v2_0_update_medium_grain_light_sleep(adev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3339-drm-amdgpu-enable-mmhub-clock-gating-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3339-drm-amdgpu-enable-mmhub-clock-gating-for-navi12.patch
new file mode 100644
index 00000000..86b4b3ab
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3339-drm-amdgpu-enable-mmhub-clock-gating-for-navi12.patch
@@ -0,0 +1,31 @@
+From e1f9cdc7ff4e8f1670ac45bf4de80ed7dc0c5d85 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 1 Aug 2019 15:39:59 +0800
+Subject: [PATCH 3339/4256] drm/amdgpu: enable mmhub clock gating for navi12
+
+enables mmhub medium grained clock gating and memory light sleep
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 5a84b89eeaa4..fea6742dd1ad 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -648,7 +648,9 @@ static int nv_common_early_init(void *handle)
+ 			AMD_CG_SUPPORT_HDP_MGCG |
+ 			AMD_CG_SUPPORT_HDP_LS |
+ 			AMD_CG_SUPPORT_SDMA_MGCG |
+-			AMD_CG_SUPPORT_SDMA_LS;
++			AMD_CG_SUPPORT_SDMA_LS |
++			AMD_CG_SUPPORT_MC_MGCG |
++			AMD_CG_SUPPORT_MC_LS;
+ 		adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
+ 		adev->external_rev_id = adev->rev_id + 0xa;
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3340-drm-amdgpu-enable-ih-clock-gating-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3340-drm-amdgpu-enable-ih-clock-gating-for-navi12.patch
new file mode 100644
index 00000000..5312c4cc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3340-drm-amdgpu-enable-ih-clock-gating-for-navi12.patch
@@ -0,0 +1,28 @@
+From f84afa3c8ed966900958e31f0445a49c3c166ee2 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 1 Aug 2019 15:01:23 +0800
+Subject: [PATCH 3340/4256] drm/amdgpu: enable ih clock gating for navi12
+
+enables ih clock gating
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index fea6742dd1ad..83ad65e42f60 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -645,6 +645,7 @@ static int nv_common_early_init(void *handle)
+ 			AMD_CG_SUPPORT_GFX_CGCG |
+ 			AMD_CG_SUPPORT_GFX_CP_LS |
+ 			AMD_CG_SUPPORT_GFX_RLC_LS |
++			AMD_CG_SUPPORT_IH_CG |
+ 			AMD_CG_SUPPORT_HDP_MGCG |
+ 			AMD_CG_SUPPORT_HDP_LS |
+ 			AMD_CG_SUPPORT_SDMA_MGCG |
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3341-drm-amdgpu-athub2-set-clock-gating-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3341-drm-amdgpu-athub2-set-clock-gating-for-navi12.patch
new file mode 100644
index 00000000..812cbd58
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3341-drm-amdgpu-athub2-set-clock-gating-for-navi12.patch
@@ -0,0 +1,28 @@
+From 209bd27568efef9edbad823bcc076170074da794 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Tue, 6 Aug 2019 13:42:03 +0800
+Subject: [PATCH 3341/4256] drm/amdgpu/athub2: set clock gating for navi12
+
+add navi12 define
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/athub_v2_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
+index 8b99d34f876f..a8ec54248ea4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
+@@ -75,6 +75,7 @@ int athub_v2_0_set_clockgating(struct amdgpu_device *adev,
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++	case CHIP_NAVI12:
+ 		athub_v2_0_update_medium_grain_clock_gating(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+ 		athub_v2_0_update_medium_grain_light_sleep(adev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3342-drm-amdgpu-enable-athub-clock-gating-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3342-drm-amdgpu-enable-athub-clock-gating-for-navi12.patch
new file mode 100644
index 00000000..611819f2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3342-drm-amdgpu-enable-athub-clock-gating-for-navi12.patch
@@ -0,0 +1,31 @@
+From 554d66639a4a29b9185ad69da42fe0215045cd98 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 1 Aug 2019 15:19:10 +0800
+Subject: [PATCH 3342/4256] drm/amdgpu: enable athub clock gating for navi12
+
+enables athub medium grained clock gating and memory light sleep
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 83ad65e42f60..8e845cc82c96 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -651,7 +651,9 @@ static int nv_common_early_init(void *handle)
+ 			AMD_CG_SUPPORT_SDMA_MGCG |
+ 			AMD_CG_SUPPORT_SDMA_LS |
+ 			AMD_CG_SUPPORT_MC_MGCG |
+-			AMD_CG_SUPPORT_MC_LS;
++			AMD_CG_SUPPORT_MC_LS |
++			AMD_CG_SUPPORT_ATHUB_MGCG |
++			AMD_CG_SUPPORT_ATHUB_LS;
+ 		adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
+ 		adev->external_rev_id = adev->rev_id + 0xa;
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3343-drm-amdgpu-enable-vcn-clock-gating-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3343-drm-amdgpu-enable-vcn-clock-gating-for-navi12.patch
new file mode 100644
index 00000000..770c333a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3343-drm-amdgpu-enable-vcn-clock-gating-for-navi12.patch
@@ -0,0 +1,30 @@
+From 314f81a88e46df4a0a5a910873e6b8d9bd44b0e9 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 1 Aug 2019 15:22:59 +0800
+Subject: [PATCH 3343/4256] drm/amdgpu: enable vcn clock gating for navi12
+
+enables vcn medium grained clock gating
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 8e845cc82c96..d4a2012b4832 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -653,7 +653,8 @@ static int nv_common_early_init(void *handle)
+ 			AMD_CG_SUPPORT_MC_MGCG |
+ 			AMD_CG_SUPPORT_MC_LS |
+ 			AMD_CG_SUPPORT_ATHUB_MGCG |
+-			AMD_CG_SUPPORT_ATHUB_LS;
++			AMD_CG_SUPPORT_ATHUB_LS |
++			AMD_CG_SUPPORT_VCN_MGCG;
+ 		adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
+ 		adev->external_rev_id = adev->rev_id + 0xa;
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3344-drm-amd-display-Remove-drm_dsc_dc.c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3344-drm-amd-display-Remove-drm_dsc_dc.c.patch
new file mode 100644
index 00000000..eed017e4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3344-drm-amd-display-Remove-drm_dsc_dc.c.patch
@@ -0,0 +1,482 @@
+From 99ac0c6e1f39d3a0e22c240f1214b726783c32e4 Mon Sep 17 00:00:00 2001
+From: David Francis <David.Francis@amd.com>
+Date: Wed, 7 Aug 2019 10:25:48 -0400
+Subject: [PATCH 3344/4256] drm/amd/display: Remove drm_dsc_dc.c
+
+This file was accidentally added to the driver during
+Navi promotion
+
+Nothing includes it. No makefile attempts to compile it, and
+it would fail compilation if they tried
+
+Remove it
+
+Signed-off-by: David Francis <David.Francis@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>w
+---
+ .../gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c   | 453 ------------------
+ 1 file changed, 453 deletions(-)
+ delete mode 100644 drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c b/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c
+deleted file mode 100644
+index fd1fb1653479..000000000000
+--- a/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c
++++ /dev/null
+@@ -1,453 +0,0 @@
+-// SPDX-License-Identifier: MIT
+-/*
+- * Copyright © 2018 Intel Corp
+- *
+- * Author:
+- * Manasi Navare <manasi.d.navare@intel.com>
+- */
+-
+-/* DC versions of linux includes */
+-#include <include/drm_dsc_dc.h>
+-
+-#define EXPORT_SYMBOL(symbol)	/* nothing */
+-#define BUILD_BUG_ON(cond)	/* nothing */
+-#define DIV_ROUND_UP(a, b)	(((b) + (a) - 1) / (b))
+-#define ERANGE			-1
+-#define DRM_DEBUG_KMS(msg)	/* nothing */
+-#define cpu_to_be16(__x) little_to_big(__x)
+-#define MAX(x, y)		((x) > (y) ? (x) : (y))
+-
+-static unsigned short little_to_big(int data)
+-{
+-	/* Swap lower and upper byte. DMCU uses big endian format. */
+-	return (0xff & (data >> 8)) + ((data & 0xff) << 8);
+-}
+-
+-/*
+- * Everything below this comment was copied directly from drm_dsc.c.
+- * Only the functions needed in DC are included.
+- * Please keep this file synced with upstream.
+- */
+-
+-/**
+- * DOC: dsc helpers
+- *
+- * These functions contain some common logic and helpers to deal with VESA
+- * Display Stream Compression standard required for DSC on Display Port/eDP or
+- * MIPI display interfaces.
+- */
+-
+-/**
+- * drm_dsc_pps_payload_pack() - Populates the DSC PPS
+- *
+- * @pps_payload:
+- * Bitwise struct for DSC Picture Parameter Set. This is defined
+- * by &struct drm_dsc_picture_parameter_set
+- * @dsc_cfg:
+- * DSC Configuration data filled by driver as defined by
+- * &struct drm_dsc_config
+- *
+- * DSC source device sends a picture parameter set (PPS) containing the
+- * information required by the sink to decode the compressed frame. Driver
+- * populates the DSC PPS struct using the DSC configuration parameters in
+- * the order expected by the DSC Display Sink device. For the DSC, the sink
+- * device expects the PPS payload in big endian format for fields
+- * that span more than 1 byte.
+- */
+-void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
+-				const struct drm_dsc_config *dsc_cfg)
+-{
+-	int i;
+-
+-	/* Protect against someone accidently changing struct size */
+-	BUILD_BUG_ON(sizeof(*pps_payload) !=
+-		     DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
+-
+-	memset(pps_payload, 0, sizeof(*pps_payload));
+-
+-	/* PPS 0 */
+-	pps_payload->dsc_version =
+-		dsc_cfg->dsc_version_minor |
+-		dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
+-
+-	/* PPS 1, 2 is 0 */
+-
+-	/* PPS 3 */
+-	pps_payload->pps_3 =
+-		dsc_cfg->line_buf_depth |
+-		dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
+-
+-	/* PPS 4 */
+-	pps_payload->pps_4 =
+-		((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
+-		 DSC_PPS_MSB_SHIFT) |
+-		dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
+-		dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT |
+-		dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
+-		dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
+-
+-	/* PPS 5 */
+-	pps_payload->bits_per_pixel_low =
+-		(dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
+-
+-	/*
+-	 * The DSC panel expects the PPS packet to have big endian format
+-	 * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert
+-	 * to big endian format. If format is little endian, it will swap
+-	 * bytes to convert to Big endian else keep it unchanged.
+-	 */
+-
+-	/* PPS 6, 7 */
+-	pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height);
+-
+-	/* PPS 8, 9 */
+-	pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width);
+-
+-	/* PPS 10, 11 */
+-	pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height);
+-
+-	/* PPS 12, 13 */
+-	pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width);
+-
+-	/* PPS 14, 15 */
+-	pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
+-
+-	/* PPS 16 */
+-	pps_payload->initial_xmit_delay_high =
+-		((dsc_cfg->initial_xmit_delay &
+-		  DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
+-		 DSC_PPS_MSB_SHIFT);
+-
+-	/* PPS 17 */
+-	pps_payload->initial_xmit_delay_low =
+-		(dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);
+-
+-	/* PPS 18, 19 */
+-	pps_payload->initial_dec_delay =
+-		cpu_to_be16(dsc_cfg->initial_dec_delay);
+-
+-	/* PPS 20 is 0 */
+-
+-	/* PPS 21 */
+-	pps_payload->initial_scale_value =
+-		dsc_cfg->initial_scale_value;
+-
+-	/* PPS 22, 23 */
+-	pps_payload->scale_increment_interval =
+-		cpu_to_be16(dsc_cfg->scale_increment_interval);
+-
+-	/* PPS 24 */
+-	pps_payload->scale_decrement_interval_high =
+-		((dsc_cfg->scale_decrement_interval &
+-		  DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
+-		 DSC_PPS_MSB_SHIFT);
+-
+-	/* PPS 25 */
+-	pps_payload->scale_decrement_interval_low =
+-		(dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);
+-
+-	/* PPS 26[7:0], PPS 27[7:5] RESERVED */
+-
+-	/* PPS 27 */
+-	pps_payload->first_line_bpg_offset =
+-		dsc_cfg->first_line_bpg_offset;
+-
+-	/* PPS 28, 29 */
+-	pps_payload->nfl_bpg_offset =
+-		cpu_to_be16(dsc_cfg->nfl_bpg_offset);
+-
+-	/* PPS 30, 31 */
+-	pps_payload->slice_bpg_offset =
+-		cpu_to_be16(dsc_cfg->slice_bpg_offset);
+-
+-	/* PPS 32, 33 */
+-	pps_payload->initial_offset =
+-		cpu_to_be16(dsc_cfg->initial_offset);
+-
+-	/* PPS 34, 35 */
+-	pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset);
+-
+-	/* PPS 36 */
+-	pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp;
+-
+-	/* PPS 37 */
+-	pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
+-
+-	/* PPS 38, 39 */
+-	pps_payload->rc_model_size =
+-		cpu_to_be16(DSC_RC_MODEL_SIZE_CONST);
+-
+-	/* PPS 40 */
+-	pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
+-
+-	/* PPS 41 */
+-	pps_payload->rc_quant_incr_limit0 =
+-		dsc_cfg->rc_quant_incr_limit0;
+-
+-	/* PPS 42 */
+-	pps_payload->rc_quant_incr_limit1 =
+-		dsc_cfg->rc_quant_incr_limit1;
+-
+-	/* PPS 43 */
+-	pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
+-		DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
+-
+-	/* PPS 44 - 57 */
+-	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
+-		pps_payload->rc_buf_thresh[i] =
+-			dsc_cfg->rc_buf_thresh[i];
+-
+-	/* PPS 58 - 87 */
+-	/*
+-	 * For DSC sink programming the RC Range parameter fields
+-	 * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
+-	 */
+-	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+-		pps_payload->rc_range_parameters[i] =
+-			((dsc_cfg->rc_range_params[i].range_min_qp <<
+-			  DSC_PPS_RC_RANGE_MINQP_SHIFT) |
+-			 (dsc_cfg->rc_range_params[i].range_max_qp <<
+-			  DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
+-			 (dsc_cfg->rc_range_params[i].range_bpg_offset));
+-		pps_payload->rc_range_parameters[i] =
+-			cpu_to_be16(pps_payload->rc_range_parameters[i]);
+-	}
+-
+-	/* PPS 88 */
+-	pps_payload->native_422_420 = dsc_cfg->native_422 |
+-		dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
+-
+-	/* PPS 89 */
+-	pps_payload->second_line_bpg_offset =
+-		dsc_cfg->second_line_bpg_offset;
+-
+-	/* PPS 90, 91 */
+-	pps_payload->nsl_bpg_offset =
+-		cpu_to_be16(dsc_cfg->nsl_bpg_offset);
+-
+-	/* PPS 92, 93 */
+-	pps_payload->second_line_offset_adj =
+-		cpu_to_be16(dsc_cfg->second_line_offset_adj);
+-
+-	/* PPS 94 - 127 are O */
+-}
+-EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
+-
+-static int compute_offset(struct drm_dsc_config *vdsc_cfg, int pixels_per_group,
+-				int groups_per_line, int grpcnt)
+-{
+-	int offset = 0;
+-	int grpcnt_id = DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay, pixels_per_group);
+-
+-	if (grpcnt <= grpcnt_id)
+-		offset = DIV_ROUND_UP(grpcnt * pixels_per_group * vdsc_cfg->bits_per_pixel, 16);
+-	else
+-		offset = DIV_ROUND_UP(grpcnt_id * pixels_per_group * vdsc_cfg->bits_per_pixel, 16)
+-			- (((grpcnt - grpcnt_id) * vdsc_cfg->slice_bpg_offset) >> 11);
+-
+-	if (grpcnt <= groups_per_line)
+-		offset += grpcnt * vdsc_cfg->first_line_bpg_offset;
+-	else
+-		offset += groups_per_line * vdsc_cfg->first_line_bpg_offset
+-			- (((grpcnt - groups_per_line) * vdsc_cfg->nfl_bpg_offset) >> 11);
+-
+-	if (vdsc_cfg->native_420) {
+-		if (grpcnt <= groups_per_line)
+-			offset -= (grpcnt * vdsc_cfg->nsl_bpg_offset) >> 11;
+-		else if (grpcnt <= 2 * groups_per_line)
+-			offset += (grpcnt - groups_per_line) * vdsc_cfg->second_line_bpg_offset
+-				- ((groups_per_line * vdsc_cfg->nsl_bpg_offset) >> 11);
+-		else
+-			offset += (grpcnt - groups_per_line) * vdsc_cfg->second_line_bpg_offset
+-				- (((grpcnt - groups_per_line) * vdsc_cfg->nsl_bpg_offset) >> 11);
+-	}
+-
+-	return offset;
+-}
+-
+-/**
+- * drm_dsc_compute_rc_parameters() - Write rate control
+- * parameters to the dsc configuration defined in
+- * &struct drm_dsc_config in accordance with the DSC 1.2
+- * specification. Some configuration fields must be present
+- * beforehand.
+- *
+- * @vdsc_cfg:
+- * DSC Configuration data partially filled by driver
+- */
+-int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
+-{
+-	unsigned long groups_per_line = 0;
+-	unsigned long groups_total = 0;
+-	unsigned long num_extra_mux_bits = 0;
+-	unsigned long slice_bits = 0;
+-	unsigned long hrd_delay = 0;
+-	unsigned long final_scale = 0;
+-	unsigned long rbs_min = 0;
+-	unsigned long max_offset = 0;
+-
+-	if (vdsc_cfg->native_420 || vdsc_cfg->native_422) {
+-		/* Number of groups used to code each line of a slice */
+-		groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2,
+-					       DSC_RC_PIXELS_PER_GROUP);
+-
+-		/* chunksize in Bytes */
+-		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
+-							  vdsc_cfg->bits_per_pixel,
+-							  (8 * 16));
+-	} else {
+-		/* Number of groups used to code each line of a slice */
+-		groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
+-					       DSC_RC_PIXELS_PER_GROUP);
+-
+-		/* chunksize in Bytes */
+-		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
+-							  vdsc_cfg->bits_per_pixel,
+-							  (8 * 16));
+-	}
+-
+-	if (vdsc_cfg->convert_rgb)
+-		num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
+-					  (4 * vdsc_cfg->bits_per_component + 4)
+-					  - 2);
+-	else if (vdsc_cfg->native_422)
+-		num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size +
+-			(4 * vdsc_cfg->bits_per_component + 4) +
+-			3 * (4 * vdsc_cfg->bits_per_component) - 2;
+-	else
+-		num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
+-			(4 * vdsc_cfg->bits_per_component + 4) +
+-			2 * (4 * vdsc_cfg->bits_per_component) - 2;
+-	/* Number of bits in one Slice */
+-	slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
+-
+-	while ((num_extra_mux_bits > 0) &&
+-	       ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
+-		num_extra_mux_bits--;
+-
+-	if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
+-		vdsc_cfg->initial_scale_value = groups_per_line + 8;
+-
+-	/* scale_decrement_interval calculation according to DSC spec 1.11 */
+-	if (vdsc_cfg->initial_scale_value > 8)
+-		vdsc_cfg->scale_decrement_interval = groups_per_line /
+-			(vdsc_cfg->initial_scale_value - 8);
+-	else
+-		vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
+-
+-	vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
+-		(vdsc_cfg->initial_xmit_delay *
+-		 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
+-
+-	if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
+-		DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
+-		return -ERANGE;
+-	}
+-
+-	final_scale = (vdsc_cfg->rc_model_size * 8) /
+-		(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
+-	if (vdsc_cfg->slice_height > 1)
+-		/*
+-		 * NflBpgOffset is 16 bit value with 11 fractional bits
+-		 * hence we multiply by 2^11 for preserving the
+-		 * fractional part
+-		 */
+-		vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
+-							(vdsc_cfg->slice_height - 1));
+-	else
+-		vdsc_cfg->nfl_bpg_offset = 0;
+-
+-	/* 2^16 - 1 */
+-	if (vdsc_cfg->nfl_bpg_offset > 65535) {
+-		DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n");
+-		return -ERANGE;
+-	}
+-
+-	if (vdsc_cfg->slice_height > 2)
+-		vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->second_line_bpg_offset << 11),
+-							(vdsc_cfg->slice_height - 1));
+-	else
+-		vdsc_cfg->nsl_bpg_offset = 0;
+-
+-	if (vdsc_cfg->nsl_bpg_offset > 65535) {
+-		DRM_DEBUG_KMS("NslBpgOffset is too large for this slice height\n");
+-		return -ERANGE;
+-	}
+-
+-	/* Number of groups used to code the entire slice */
+-	groups_total = groups_per_line * vdsc_cfg->slice_height;
+-
+-	/* slice_bpg_offset is 16 bit value with 11 fractional bits */
+-	vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
+-						    vdsc_cfg->initial_offset +
+-						    num_extra_mux_bits) << 11),
+-						  groups_total);
+-
+-	if (final_scale > 9) {
+-		/*
+-		 * ScaleIncrementInterval =
+-		 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
+-		 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
+-		 * we need divide by 2^11 from pstDscCfg values
+-		 */
+-		vdsc_cfg->scale_increment_interval =
+-				(vdsc_cfg->final_offset * (1 << 11)) /
+-				((vdsc_cfg->nfl_bpg_offset +
+-				vdsc_cfg->nsl_bpg_offset +
+-				vdsc_cfg->slice_bpg_offset) *
+-				(final_scale - 9));
+-	} else {
+-		/*
+-		 * If finalScaleValue is less than or equal to 9, a value of 0 should
+-		 * be used to disable the scale increment at the end of the slice
+-		 */
+-		vdsc_cfg->scale_increment_interval = 0;
+-	}
+-
+-	if (vdsc_cfg->scale_increment_interval > 65535) {
+-		DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n");
+-		return -ERANGE;
+-	}
+-
+-	/*
+-	 * DSC spec mentions that bits_per_pixel specifies the target
+-	 * bits/pixel (bpp) rate that is used by the encoder,
+-	 * in steps of 1/16 of a bit per pixel
+-	 */
+-	if (vdsc_cfg->dsc_version_minor == 2 && (vdsc_cfg->native_420 || vdsc_cfg->native_422)) {
+-
+-		max_offset = compute_offset(vdsc_cfg, DSC_RC_PIXELS_PER_GROUP, groups_per_line,
+-					DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay,
+-						DSC_RC_PIXELS_PER_GROUP));
+-
+-		max_offset = MAX(max_offset,
+-				compute_offset(vdsc_cfg, DSC_RC_PIXELS_PER_GROUP, groups_per_line,
+-					DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay,
+-						groups_per_line)));
+-
+-		max_offset = MAX(max_offset,
+-				compute_offset(vdsc_cfg, DSC_RC_PIXELS_PER_GROUP, groups_per_line,
+-					DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay,
+-						groups_per_line * 2)));
+-
+-		rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + max_offset;
+-	} else {
+-		rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
+-			DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
+-				     vdsc_cfg->bits_per_pixel, 16) +
+-			groups_per_line * vdsc_cfg->first_line_bpg_offset;
+-	}
+-
+-	hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
+-	vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
+-	vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
+-
+-	/* As per DSC spec v1.2a recommendation: */
+-	if (vdsc_cfg->native_420)
+-		vdsc_cfg->second_line_offset_adj = 512;
+-	else
+-		vdsc_cfg->second_line_offset_adj = 0;
+-
+-	return 0;
+-}
+-EXPORT_SYMBOL(drm_dsc_compute_rc_parameters);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3345-drm-amdgpu-Update-pitch-on-page-flips-without-DC-as-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3345-drm-amdgpu-Update-pitch-on-page-flips-without-DC-as-.patch
new file mode 100644
index 00000000..53e08208
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3345-drm-amdgpu-Update-pitch-on-page-flips-without-DC-as-.patch
@@ -0,0 +1,124 @@
+From b864d1ec92247f632c524dd7babe1cd3aeb4b159 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <michel.daenzer@amd.com>
+Date: Wed, 24 Jul 2019 17:56:28 +0200
+Subject: [PATCH 3345/4256] drm/amdgpu: Update pitch on page flips without DC
+ as well
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+DC already handles this correctly since amdgpu minor version 31. Bump
+the minor version again so that xf86-video-amdgpu can take advantage of
+this working without DC as well now.
+
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c  | 4 ++++
+ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c  | 4 ++++
+ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c   | 4 ++++
+ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c   | 4 ++++
+ 5 files changed, 18 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 2c0e077d209f..7d3a39cebd90 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -77,9 +77,10 @@
+  * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
+  * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
+  * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
++ * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
+  */
+ #define KMS_DRIVER_MAJOR	3
+-#define KMS_DRIVER_MINOR	33
++#define KMS_DRIVER_MINOR	34
+ #define KMS_DRIVER_PATCHLEVEL	0
+ 
+ #define AMDGPU_VERSION          "19.10.9.418"
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+index 4cfecdce29a3..6cc3498fce9e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+@@ -233,6 +233,7 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev,
+ 				int crtc_id, u64 crtc_base, bool async)
+ {
+ 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
++	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
+ 	u32 tmp;
+ 
+ 	/* flip at hsync for async, default is vsync */
+@@ -240,6 +241,9 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev,
+ 	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
+ 			    GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
+ 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++	/* update pitch */
++	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
++	       fb->pitches[0] / fb->format->cpp[0]);
+ 	/* update the primary scanout address */
+ 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
+ 	       upper_32_bits(crtc_base));
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+index 7c868916d90f..73b91e1f1cd9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+@@ -251,6 +251,7 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev,
+ 				int crtc_id, u64 crtc_base, bool async)
+ {
+ 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
++	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
+ 	u32 tmp;
+ 
+ 	/* flip immediate for async, default is vsync */
+@@ -258,6 +259,9 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev,
+ 	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
+ 			    GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
+ 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
++	/* update pitch */
++	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
++	       fb->pitches[0] / fb->format->cpp[0]);
+ 	/* update the scanout addresses */
+ 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
+ 	       upper_32_bits(crtc_base));
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+index 3a707b8618b7..04c81df035c3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+@@ -186,10 +186,14 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev,
+ 			       int crtc_id, u64 crtc_base, bool async)
+ {
+ 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
++	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
+ 
+ 	/* flip at hsync for async, default is vsync */
+ 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
+ 	       GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
++	/* update pitch */
++	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
++	       fb->pitches[0] / fb->format->cpp[0]);
+ 	/* update the scanout addresses */
+ 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
+ 	       upper_32_bits(crtc_base));
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+index 8c0576978d36..b239b04bd6c0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+@@ -181,10 +181,14 @@ static void dce_v8_0_page_flip(struct amdgpu_device *adev,
+ 			       int crtc_id, u64 crtc_base, bool async)
+ {
+ 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
++	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
+ 
+ 	/* flip at hsync for async, default is vsync */
+ 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
+ 	       GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
++	/* update pitch */
++	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
++	       fb->pitches[0] / fb->format->cpp[0]);
+ 	/* update the primary scanout addresses */
+ 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
+ 	       upper_32_bits(crtc_base));
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3346-drm-dp-Use-non-cyclic-idr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3346-drm-dp-Use-non-cyclic-idr.patch
new file mode 100644
index 00000000..a6f157fa
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3346-drm-dp-Use-non-cyclic-idr.patch
@@ -0,0 +1,36 @@
+From 7c14e97f165f19fd3a48876c9136df2405ee5bb8 Mon Sep 17 00:00:00 2001
+From: Leo Li <sunpeng.li@amd.com>
+Date: Thu, 11 Apr 2019 14:07:25 -0400
+Subject: [PATCH 3346/4256] drm/dp: Use non-cyclic idr
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+In preparation for adding aux devices for DP MST, make the IDR
+non-cyclic. That way, hotplug cycling MST devices won't needlessly
+increment the minor version index.
+
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+Reviewed-by: Lyude Paul <lyude@redhat.com>
+Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+---
+ drivers/gpu/drm/drm_dp_aux_dev.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/drm_dp_aux_dev.c b/drivers/gpu/drm/drm_dp_aux_dev.c
+index 0e4f25d63fd2..6d8461105ed4 100644
+--- a/drivers/gpu/drm/drm_dp_aux_dev.c
++++ b/drivers/gpu/drm/drm_dp_aux_dev.c
+@@ -80,8 +80,7 @@ static struct drm_dp_aux_dev *alloc_drm_dp_aux_dev(struct drm_dp_aux *aux)
+ 	kref_init(&aux_dev->refcount);
+ 
+ 	mutex_lock(&aux_idr_mutex);
+-	index = idr_alloc_cyclic(&aux_idr, aux_dev, 0, DRM_AUX_MINORS,
+-				 GFP_KERNEL);
++	index = idr_alloc(&aux_idr, aux_dev, 0, DRM_AUX_MINORS, GFP_KERNEL);
+ 	mutex_unlock(&aux_idr_mutex);
+ 	if (index < 0) {
+ 		kfree(aux_dev);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3347-drm-amd-display-Use-connector-kdev-as-aux-device-par.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3347-drm-amd-display-Use-connector-kdev-as-aux-device-par.patch
new file mode 100644
index 00000000..00166c68
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3347-drm-amd-display-Use-connector-kdev-as-aux-device-par.patch
@@ -0,0 +1,45 @@
+From 89752c6f44875bc102901df82ee10443a0b558ea Mon Sep 17 00:00:00 2001
+From: Leo Li <sunpeng.li@amd.com>
+Date: Fri, 26 Apr 2019 13:40:08 -0400
+Subject: [PATCH 3347/4256] drm/amd/display: Use connector kdev as aux device
+ parent
+
+Set the connector's kernel device as the parent for the aux kernel
+device. This allows udev rules to access connector attributes when
+creating symlinks to aux devices.
+
+For example, the following udev rule:
+
+SUBSYSTEM=="drm_dp_aux_dev", SUBSYSTEMS=="drm", ATTRS{edid}=="*",
+	SYMLINK+="drm_dp_aux/by-name/$id"
+
+Will create the following symlinks using the connector's name:
+
+$ ls /dev/drm_dp_aux/by-name/
+card0-DP-1  card0-DP-2  card0-DP-3
+
+Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Cc: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
+Cc: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+index a6f44a47adcb..083fb9729346 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+@@ -385,7 +385,7 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
+ 				       struct amdgpu_dm_connector *aconnector)
+ {
+ 	aconnector->dm_dp_aux.aux.name = "dmdc";
+-	aconnector->dm_dp_aux.aux.dev = dm->adev->dev;
++	aconnector->dm_dp_aux.aux.dev = aconnector->base.kdev;
+ 	aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
+ 	aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3348-drm-amd-display-Implement-MST-Aux-device-registratio.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3348-drm-amd-display-Implement-MST-Aux-device-registratio.patch
new file mode 100644
index 00000000..28aeb453
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3348-drm-amd-display-Implement-MST-Aux-device-registratio.patch
@@ -0,0 +1,142 @@
+From 89dc36ff36c1b8754861ff8bf1d3354f3688997c Mon Sep 17 00:00:00 2001
+From: Leo Li <sunpeng.li@amd.com>
+Date: Wed, 12 Jun 2019 17:53:13 -0400
+Subject: [PATCH 3348/4256] drm/amd/display: Implement MST Aux device
+ registration
+
+Implement late_register and early_unregister hooks for MST connectors.
+Call drm helpers for MST connector registration, which registers the
+AUX devices.
+
+Cc: Jerry Zuo <Jerry.Zuo@amd.com>
+Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Cc: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 24 ++++++++++-
+ drivers/gpu/drm/drm_dp_mst_topology.c         | 42 +++++++++++++++++++
+ include/drm/drm_dp_mst_helper.h               |  5 +++
+ 3 files changed, 70 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+index 083fb9729346..98916da6d25f 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+@@ -155,6 +155,26 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector)
+ 	kfree(amdgpu_dm_connector);
+ }
+ 
++static int
++amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
++{
++	struct amdgpu_dm_connector *amdgpu_dm_connector =
++		to_amdgpu_dm_connector(connector);
++	struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
++
++	return drm_dp_mst_connector_late_register(connector, port);
++}
++
++static void
++amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
++{
++	struct amdgpu_dm_connector *amdgpu_dm_connector =
++		to_amdgpu_dm_connector(connector);
++	struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
++
++	drm_dp_mst_connector_early_unregister(connector, port);
++}
++
+ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
+ 	.detect = dm_dp_mst_detect,
+ 	.fill_modes = drm_helper_probe_single_connector_modes,
+@@ -163,7 +183,9 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
+ 	.atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
+ 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+ 	.atomic_set_property = amdgpu_dm_connector_atomic_set_property,
+-	.atomic_get_property = amdgpu_dm_connector_atomic_get_property
++	.atomic_get_property = amdgpu_dm_connector_atomic_get_property,
++	.late_register = amdgpu_dm_mst_connector_late_register,
++	.early_unregister = amdgpu_dm_mst_connector_early_unregister,
+ };
+ 
+ static int dm_dp_mst_get_modes(struct drm_connector *connector)
+diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
+index c0c7d006568e..c36e5e704a32 100644
+--- a/drivers/gpu/drm/drm_dp_mst_topology.c
++++ b/drivers/gpu/drm/drm_dp_mst_topology.c
+@@ -35,6 +35,8 @@
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_crtc_helper.h>
+ 
++#include "drm_crtc_helper_internal.h"
++
+ /**
+  * DOC: dp mst helper
+  *
+@@ -1137,6 +1139,46 @@ static void build_mst_prop_path(const struct drm_dp_mst_branch *mstb,
+ 	strlcat(proppath, temp, proppath_size);
+ }
+ 
++/**
++ * drm_dp_mst_connector_late_register() - Late MST connector registration
++ * @drm_connector: The MST connector
++ * @port: The MST port for this connector
++ *
++ * Helper to register the remote aux device for this MST port. Drivers should
++ * call this from their mst connector's late_register hook to enable MST aux
++ * devices.
++ *
++ * Return: 0 on success, negative error code on failure.
++ */
++int drm_dp_mst_connector_late_register(struct drm_connector *connector,
++                                       struct drm_dp_mst_port *port)
++{
++        DRM_DEBUG_KMS("registering %s remote bus for %s\n",
++                      port->aux.name, connector->kdev->kobj.name);
++
++        port->aux.dev = connector->kdev;
++        return drm_dp_aux_register_devnode(&port->aux);
++}
++EXPORT_SYMBOL(drm_dp_mst_connector_late_register);
++
++/**
++ * drm_dp_mst_connector_early_unregister() - Early MST connector unregistration
++ * @drm_connector: The MST connector
++ * @port: The MST port for this connector
++ *
++ * Helper to unregister the remote aux device for this MST port, registered by
++ * drm_dp_mst_connector_late_register(). Drivers should call this from their mst
++ * connector's early_unregister hook.
++ */
++void drm_dp_mst_connector_early_unregister(struct drm_connector *connector,
++                                           struct drm_dp_mst_port *port)
++{
++        DRM_DEBUG_KMS("unregistering %s remote bus for %s\n",
++                      port->aux.name, connector->kdev->kobj.name);
++        drm_dp_aux_unregister_devnode(&port->aux);
++}
++EXPORT_SYMBOL(drm_dp_mst_connector_early_unregister);
++
+ static void drm_dp_add_port(struct drm_dp_mst_branch *mstb,
+ 			    struct drm_device *dev,
+ 			    struct drm_dp_link_addr_reply_port *port_msg)
+diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
+index 7f78d26a0766..c97dac8765d3 100644
+--- a/include/drm/drm_dp_mst_helper.h
++++ b/include/drm/drm_dp_mst_helper.h
+@@ -623,6 +623,11 @@ void drm_dp_mst_dump_topology(struct seq_file *m,
+ 
+ void drm_dp_mst_topology_mgr_suspend(struct drm_dp_mst_topology_mgr *mgr);
+ int drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr);
++int drm_dp_mst_connector_late_register(struct drm_connector *connector,
++                                       struct drm_dp_mst_port *port);
++void drm_dp_mst_connector_early_unregister(struct drm_connector *connector,
++                                           struct drm_dp_mst_port *port);
++
+ struct drm_dp_mst_topology_state *drm_atomic_get_mst_topology_state(struct drm_atomic_state *state,
+ 								    struct drm_dp_mst_topology_mgr *mgr);
+ int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3349-drm-amdgpu-add-navi14-PCI-ID.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3349-drm-amdgpu-add-navi14-PCI-ID.patch
new file mode 100644
index 00000000..7f1eec65
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3349-drm-amdgpu-add-navi14-PCI-ID.patch
@@ -0,0 +1,29 @@
+From 2744b284c884fea065c15162dff07c4ebd6e8444 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 7 Aug 2019 14:37:26 -0500
+Subject: [PATCH 3349/4256] drm/amdgpu: add navi14 PCI ID
+
+Add the navi14 PCI device id.
+
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 7d3a39cebd90..43b059d8f58d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1045,6 +1045,8 @@ static const struct pci_device_id pciidlist[] = {
+ 	{0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
+ 	{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
+ 	{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
++	/* Navi14 */
++	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
+ 
+ 	{0, 0, 0}
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3350-drm-amd-powerplay-re-define-smu-interface-version-fo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3350-drm-amd-powerplay-re-define-smu-interface-version-fo.patch
new file mode 100644
index 00000000..71dced06
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3350-drm-amd-powerplay-re-define-smu-interface-version-fo.patch
@@ -0,0 +1,124 @@
+From d21d6e2265879bd1db86620bbf3d9298c5ad7d9e Mon Sep 17 00:00:00 2001
+From: tiancyin <tianci.yin@amd.com>
+Date: Thu, 8 Aug 2019 11:57:28 +0800
+Subject: [PATCH 3350/4256] drm/amd/powerplay: re-define smu interface version
+ for smu v11
+
+[why]
+navi14 share same defination of smu interface version with navi10,
+anyone of them update the version may break the other one's
+version checking.
+
+[how]
+create different version defination, so that they can
+update their version separately.
+
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: tiancyin <tianci.yin@amd.com>
+---
+ .../gpu/drm/amd/powerplay/inc/smu11_driver_if.h  |  4 +++-
+ .../amd/powerplay/inc/smu11_driver_if_navi10.h   |  4 +++-
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h    |  5 +++++
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c       |  1 -
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c        | 16 ++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c       |  1 -
+ 6 files changed, 27 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
+index 755d51f9c6a9..fdc6b7a57bc9 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
+@@ -27,7 +27,9 @@
+ // *** IMPORTANT ***
+ // SMU TEAM: Always increment the interface version if
+ // any structure is changed in this file
+-#define SMU11_DRIVER_IF_VERSION 0x13
++// Be aware of that the version should be updated in
++// smu_v11_0.h, rename is also needed.
++// #define SMU11_DRIVER_IF_VERSION 0x13
+ 
+ #define PPTABLE_V20_SMU_VERSION 3
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
+index adbbfebbb1e5..6d9e79e5bf9d 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
+@@ -26,7 +26,9 @@
+ // *** IMPORTANT ***
+ // SMU TEAM: Always increment the interface version if 
+ // any structure is changed in this file
+-#define SMU11_DRIVER_IF_VERSION 0x33
++// Be aware of that the version should be updated in
++// smu_v11_0.h, maybe rename is also needed.
++// #define SMU11_DRIVER_IF_VERSION 0x33
+ 
+ #define PPTABLE_NV10_SMU_VERSION 8
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index fcb58012170f..97605e963c2b 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -25,6 +25,11 @@
+ 
+ #include "amdgpu_smu.h"
+ 
++#define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
++#define SMU11_DRIVER_IF_VERSION_VG20 0x13
++#define SMU11_DRIVER_IF_VERSION_NV10 0x33
++#define SMU11_DRIVER_IF_VERSION_NV14 0x33
++
+ /* MP Apertures */
+ #define MP0_Public			0x03800000
+ #define MP0_SRAM			0x03900000
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 96cc2f95d078..7398b281cbb0 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1610,6 +1610,5 @@ void navi10_set_ppt_funcs(struct smu_context *smu)
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 
+ 	smu->ppt_funcs = &navi10_ppt_funcs;
+-	smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
+ 	smu_table->table_count = TABLE_COUNT;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index c078bf4d522e..91dfae1a2b16 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -271,6 +271,22 @@ static int smu_v11_0_check_fw_version(struct smu_context *smu)
+ 	smu_minor = (smu_version >> 8) & 0xff;
+ 	smu_debug = (smu_version >> 0) & 0xff;
+ 
++	switch (smu->adev->asic_type) {
++	case CHIP_VEGA20:
++		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_VG20;
++		break;
++	case CHIP_NAVI10:
++		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV10;
++		break;
++	case CHIP_NAVI14:
++		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV14;
++		break;
++	default:
++		pr_err("smu unsuported asic type:%d.\n",smu->adev->asic_type);
++		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_INV;
++		break;
++	}
++
+ 	/*
+ 	 * 1. if_version mismatch is not critical as our fw is designed
+ 	 * to be backward compatible.
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 52c8fc9f1ff4..e28c004e0036 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -3173,6 +3173,5 @@ void vega20_set_ppt_funcs(struct smu_context *smu)
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 
+ 	smu->ppt_funcs = &vega20_ppt_funcs;
+-	smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
+ 	smu_table->table_count = TABLE_COUNT;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3351-drm-amdgpu-add-check-to-avoid-array-bound-issue.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3351-drm-amdgpu-add-check-to-avoid-array-bound-issue.patch
new file mode 100644
index 00000000..e862d490
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3351-drm-amdgpu-add-check-to-avoid-array-bound-issue.patch
@@ -0,0 +1,33 @@
+From b4b46de5417802601c423c7ba7e22ae60e432c88 Mon Sep 17 00:00:00 2001
+From: Guchun Chen <guchun.chen@amd.com>
+Date: Thu, 8 Aug 2019 14:54:41 +0800
+Subject: [PATCH 3351/4256] drm/amdgpu: add check to avoid array bound issue
+
+Sub_block_index can be passed from user level, so
+add one check before accessing the array first to
+prevent array index out of bound problem.
+
+Change-Id: I556fc560b44215848ba3a95f757febdf3d0af422
+Signed-off-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 56faabc8fb13..c25002329728 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -5984,6 +5984,9 @@ static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
+ 	if (adev->asic_type != CHIP_VEGA20)
+ 		return -EINVAL;
+ 
++	if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks))
++		return -EINVAL;
++
+ 	if (!ras_gfx_subblocks[info->head.sub_block_index].name)
+ 		return -EPERM;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3352-drm-amdgpu-add-sub-block-parameter-in-ras-inject-com.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3352-drm-amdgpu-add-sub-block-parameter-in-ras-inject-com.patch
new file mode 100644
index 00000000..0d232619
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3352-drm-amdgpu-add-sub-block-parameter-in-ras-inject-com.patch
@@ -0,0 +1,70 @@
+From f9df41172be164bffbf1f6fc4ee3061f1a10e9b9 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Wed, 7 Aug 2019 14:27:42 +0800
+Subject: [PATCH 3352/4256] drm/amdgpu: add sub block parameter in ras inject
+ command
+
+ras sub block index could be passed from shell command
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 17 ++++++++++-------
+ 1 file changed, 10 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 369651247b23..bc766cdbeaae 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -129,6 +129,7 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
+ 	char err[9] = "ue";
+ 	int op = -1;
+ 	int block_id;
++	uint32_t sub_block;
+ 	u64 address, value;
+ 
+ 	if (*pos)
+@@ -167,11 +168,12 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
+ 		data->op = op;
+ 
+ 		if (op == 2) {
+-			if (sscanf(str, "%*s %*s %*s %llu %llu",
+-						&address, &value) != 2)
+-				if (sscanf(str, "%*s %*s %*s 0x%llx 0x%llx",
+-							&address, &value) != 2)
++			if (sscanf(str, "%*s %*s %*s %u %llu %llu",
++						&sub_block, &address, &value) != 3)
++				if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
++							&sub_block, &address, &value) != 3)
+ 					return -EINVAL;
++			data->head.sub_block_index = sub_block;
+ 			data->inject.address = address;
+ 			data->inject.value = value;
+ 		}
+@@ -216,7 +218,7 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
+  * write the struct to the control node.
+  *
+  * bash:
+- * echo op block [error [address value]] > .../ras/ras_ctrl
++ * echo op block [error [sub_blcok address value]] > .../ras/ras_ctrl
+  *	op: disable, enable, inject
+  *		disable: only block is needed
+  *		enable: block and error are needed
+@@ -226,10 +228,11 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
+  *	error: ue, ce
+  *		ue: multi_uncorrectable
+  *		ce: single_correctable
++ *	sub_block: sub block index, pass 0 if there is no sub block
+  *
+  * here are some examples for bash commands,
+- *	echo inject umc ue 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
+- *	echo inject umc ce 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
++ *	echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
++ *	echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
+  *	echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
+  *
+  * How to check the result?
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3353-drm-amdgpu-fix-transform-feedback-GDS-hang-on-gfx10-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3353-drm-amdgpu-fix-transform-feedback-GDS-hang-on-gfx10-.patch
new file mode 100644
index 00000000..df7d27fc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3353-drm-amdgpu-fix-transform-feedback-GDS-hang-on-gfx10-.patch
@@ -0,0 +1,77 @@
+From 989b9e2b38a64202d237c30da82f31082110c885 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Wed, 19 Jun 2019 19:26:24 -0400
+Subject: [PATCH 3353/4256] drm/amdgpu: fix transform feedback GDS hang on
+ gfx10 (v2)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+v2: update emit_ib_size
+(though it's still wrong because it was wrong before)
+
+Signed-off-by: Marek Olšák <marek.olsak@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h |  3 ++-
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 14 +++++++++++---
+ 2 files changed, 13 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
+index dad2186f4ed5..df8a23554831 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
+@@ -31,7 +31,8 @@ struct amdgpu_gds {
+ 	uint32_t gds_size;
+ 	uint32_t gws_size;
+ 	uint32_t oa_size;
+-	uint32_t			gds_compute_max_wave_id;
++	uint32_t gds_compute_max_wave_id;
++	uint32_t vgt_gs_max_wave_id;
+ };
+ 
+ struct amdgpu_gds_reg_offset {
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index beee75df22a0..ba8f66f27d2f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -4360,6 +4360,15 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
+ 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
+ 	u32 header, control = 0;
+ 
++	/* Prevent a hw deadlock due to a wave ID mismatch between ME and GDS.
++	 * This resets the wave ID counters. (needed by transform feedback)
++	 * TODO: This might only be needed on a VMID switch when we change
++	 *       the GDS OA mapping, not sure.
++	 */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
++	amdgpu_ring_write(ring, mmVGT_GS_MAX_WAVE_ID);
++	amdgpu_ring_write(ring, ring->adev->gds.vgt_gs_max_wave_id);
++
+ 	if (ib->flags & AMDGPU_IB_FLAG_CE)
+ 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
+ 	else
+@@ -5094,7 +5103,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
+ 		5 + /* HDP_INVL */
+ 		8 + 8 + /* FENCE x2 */
+ 		2, /* SWITCH_BUFFER */
+-	.emit_ib_size =	4, /* gfx_v10_0_ring_emit_ib_gfx */
++	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_gfx */
+ 	.emit_ib = gfx_v10_0_ring_emit_ib_gfx,
+ 	.emit_fence = gfx_v10_0_ring_emit_fence,
+ 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
+@@ -5244,10 +5253,9 @@ static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
+ 	/* init asic gds info */
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+-		adev->gds.gds_size = 0x10000;
+-		break;
+ 	default:
+ 		adev->gds.gds_size = 0x10000;
++		adev->gds.vgt_gs_max_wave_id = 0x3ff;
+ 		break;
+ 	}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3354-drm-amdgpu-handle-AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3354-drm-amdgpu-handle-AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_.patch
new file mode 100644
index 00000000..cd43d868
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3354-drm-amdgpu-handle-AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_.patch
@@ -0,0 +1,71 @@
+From 5c2be5f5d4d600e258d4d6465ed621952ab67c1f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Wed, 19 Jun 2019 19:26:59 -0400
+Subject: [PATCH 3354/4256] drm/amdgpu: handle
+ AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID on gfx10
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Marek Olšák <marek.olsak@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 21 +++++++++++++++++++--
+ 1 file changed, 19 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index ba8f66f27d2f..7d3e6a3161dd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -4406,6 +4406,22 @@ static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
+ 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
+ 	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
+ 
++	/* Currently, there is a high possibility to get wave ID mismatch
++	 * between ME and GDS, leading to a hw deadlock, because ME generates
++	 * different wave IDs than the GDS expects. This situation happens
++	 * randomly when at least 5 compute pipes use GDS ordered append.
++	 * The wave IDs generated by ME are also wrong after suspend/resume.
++	 * Those are probably bugs somewhere else in the kernel driver.
++	 *
++	 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
++	 * GDS to 0 for this ring (me/pipe).
++	 */
++	if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
++		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
++		amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
++		amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
++	}
++
+ 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
+ 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
+ 	amdgpu_ring_write(ring,
+@@ -5142,7 +5158,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
+ 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
+ 		2 + /* gfx_v10_0_ring_emit_vm_flush */
+ 		8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
+-	.emit_ib_size =	4, /* gfx_v10_0_ring_emit_ib_compute */
++	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
+ 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
+ 	.emit_fence = gfx_v10_0_ring_emit_fence,
+ 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
+@@ -5175,7 +5191,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
+ 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
+ 		2 + /* gfx_v10_0_ring_emit_vm_flush */
+ 		8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
+-	.emit_ib_size =	4, /* gfx_v10_0_ring_emit_ib_compute */
++	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
+ 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
+ 	.emit_fence = gfx_v10_0_ring_emit_fence_kiq,
+ 	.test_ring = gfx_v10_0_ring_test_ring,
+@@ -5255,6 +5271,7 @@ static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
+ 	case CHIP_NAVI10:
+ 	default:
+ 		adev->gds.gds_size = 0x10000;
++		adev->gds.gds_compute_max_wave_id = 0x4ff;
+ 		adev->gds.vgt_gs_max_wave_id = 0x3ff;
+ 		break;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3355-Revert-drm-amdgpu-fix-transform-feedback-GDS-hang-on.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3355-Revert-drm-amdgpu-fix-transform-feedback-GDS-hang-on.patch
new file mode 100644
index 00000000..ebfbf381
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3355-Revert-drm-amdgpu-fix-transform-feedback-GDS-hang-on.patch
@@ -0,0 +1,76 @@
+From 6ac842561a16cad68c85bff512c4646659d3ecd5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Fri, 2 Aug 2019 17:44:06 -0400
+Subject: [PATCH 3355/4256] Revert "drm/amdgpu: fix transform feedback GDS hang
+ on gfx10 (v2)"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This reverts commit b41335c6c0303d100abe89c843e52645d1974cd9.
+
+SET_CONFIG_REG writes to memory if register shadowing is enabled,
+causing a VM fault.
+
+NGG streamout is unstable anyway, so all UMDs should use legacy
+streamout. I think Mesa is the only driver using NGG streamout.
+
+Signed-off-by: Marek Olšák <marek.olsak@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h |  1 -
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 12 +-----------
+ 2 files changed, 1 insertion(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
+index df8a23554831..f6ac1e9548f2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
+@@ -32,7 +32,6 @@ struct amdgpu_gds {
+ 	uint32_t gws_size;
+ 	uint32_t oa_size;
+ 	uint32_t gds_compute_max_wave_id;
+-	uint32_t vgt_gs_max_wave_id;
+ };
+ 
+ struct amdgpu_gds_reg_offset {
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 7d3e6a3161dd..066ba593af23 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -4360,15 +4360,6 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
+ 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
+ 	u32 header, control = 0;
+ 
+-	/* Prevent a hw deadlock due to a wave ID mismatch between ME and GDS.
+-	 * This resets the wave ID counters. (needed by transform feedback)
+-	 * TODO: This might only be needed on a VMID switch when we change
+-	 *       the GDS OA mapping, not sure.
+-	 */
+-	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+-	amdgpu_ring_write(ring, mmVGT_GS_MAX_WAVE_ID);
+-	amdgpu_ring_write(ring, ring->adev->gds.vgt_gs_max_wave_id);
+-
+ 	if (ib->flags & AMDGPU_IB_FLAG_CE)
+ 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
+ 	else
+@@ -5119,7 +5110,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
+ 		5 + /* HDP_INVL */
+ 		8 + 8 + /* FENCE x2 */
+ 		2, /* SWITCH_BUFFER */
+-	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_gfx */
++	.emit_ib_size =	4, /* gfx_v10_0_ring_emit_ib_gfx */
+ 	.emit_ib = gfx_v10_0_ring_emit_ib_gfx,
+ 	.emit_fence = gfx_v10_0_ring_emit_fence,
+ 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
+@@ -5272,7 +5263,6 @@ static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
+ 	default:
+ 		adev->gds.gds_size = 0x10000;
+ 		adev->gds.gds_compute_max_wave_id = 0x4ff;
+-		adev->gds.vgt_gs_max_wave_id = 0x3ff;
+ 		break;
+ 	}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3356-drm-amdgpu-add-amdgpu_mmhub_funcs-definition.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3356-drm-amdgpu-add-amdgpu_mmhub_funcs-definition.patch
new file mode 100644
index 00000000..aae06189
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3356-drm-amdgpu-add-amdgpu_mmhub_funcs-definition.patch
@@ -0,0 +1,139 @@
+From 196e13b86631efa51c7aa8cef2a586b1e136b758 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Tue, 6 Aug 2019 20:15:55 +0800
+Subject: [PATCH 3356/4256] drm/amdgpu: add amdgpu_mmhub_funcs definition
+
+add amdgpu_mmhub_funcs definition and initialize it,
+prepare for mmhub ras enablement
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h       |  2 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h | 31 +++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c     | 12 +++++++++
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c   |  9 +++++++
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h   |  2 ++
+ 5 files changed, 56 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 9ef363f02f8a..1bbe7589af7a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -88,6 +88,7 @@
+ #include "amdgpu_discovery.h"
+ #include "amdgpu_mes.h"
+ #include "amdgpu_umc.h"
++#include "amdgpu_mmhub.h"
+ 
+ #define MAX_GPU_INSTANCE		16
+ 
+@@ -1016,6 +1017,7 @@ struct amdgpu_device {
+ 
+ 	const struct amdgpu_nbio_funcs	*nbio_funcs;
+ 	const struct amdgpu_df_funcs	*df_funcs;
++	const struct amdgpu_mmhub_funcs	*mmhub_funcs;
+ 
+ 	/* delayed work_func for deferring clockgating during resume */
+ 	struct delayed_work     delayed_init_work;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
+new file mode 100644
+index 000000000000..2d75ecfa199b
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
+@@ -0,0 +1,31 @@
++/*
++ * Copyright (C) 2019  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef __AMDGPU_MMHUB_H__
++#define __AMDGPU_MMHUB_H__
++
++struct amdgpu_mmhub_funcs {
++	void (*ras_init)(struct amdgpu_device *adev);
++	void (*query_ras_error_count)(struct amdgpu_device *adev,
++					void *ras_error_status);
++};
++
++#endif
++
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 004ae69c8def..ca9c06b8e02c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -650,6 +650,17 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
+ 	}
+ }
+ 
++static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
++{
++	switch (adev->asic_type) {
++	case CHIP_VEGA20:
++		adev->mmhub_funcs = &mmhub_v1_0_funcs;
++		break;
++	default:
++		break;
++	}
++}
++
+ static int gmc_v9_0_early_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+@@ -657,6 +668,7 @@ static int gmc_v9_0_early_init(void *handle)
+ 	gmc_v9_0_set_gmc_funcs(adev);
+ 	gmc_v9_0_set_irq_funcs(adev);
+ 	gmc_v9_0_set_umc_funcs(adev);
++	gmc_v9_0_set_mmhub_funcs(adev);
+ 
+ 	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
+ 	adev->gmc.shared_aperture_end =
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index da214ca06cee..86b19a3e9b91 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -553,3 +553,12 @@ void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
+ 	if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
+ 		*flags |= AMD_CG_SUPPORT_MC_LS;
+ }
++
++static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev,
++					   void *ras_error_status)
++{
++}
++
++const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {
++	.query_ras_error_count = mmhub_v1_0_query_ras_error_count,
++};
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
+index 0de0fdf98c00..c43319e8f945 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
+@@ -23,6 +23,8 @@
+ #ifndef __MMHUB_V1_0_H__
+ #define __MMHUB_V1_0_H__
+ 
++extern const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs;
++
+ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev);
+ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev);
+ void mmhub_v1_0_gart_disable(struct amdgpu_device *adev);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3357-drm-amdgpu-support-mmhub-ras-in-amdgpu-ras.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3357-drm-amdgpu-support-mmhub-ras-in-amdgpu-ras.patch
new file mode 100644
index 00000000..60d01b25
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3357-drm-amdgpu-support-mmhub-ras-in-amdgpu-ras.patch
@@ -0,0 +1,39 @@
+From fa118b379b2ef860629331038407a53fbe821a6d Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Tue, 6 Aug 2019 20:22:49 +0800
+Subject: [PATCH 3357/4256] drm/amdgpu: support mmhub ras in amdgpu ras
+
+call mmhub ras query/inject in amdgpu ras
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index bc766cdbeaae..be59102526a1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -612,6 +612,10 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev,
+ 		if (adev->gfx.funcs->query_ras_error_count)
+ 			adev->gfx.funcs->query_ras_error_count(adev, &err_data);
+ 		break;
++	case AMDGPU_RAS_BLOCK__MMHUB:
++		if (adev->mmhub_funcs->query_ras_error_count)
++			adev->mmhub_funcs->query_ras_error_count(adev, &err_data);
++		break;
+ 	default:
+ 		break;
+ 	}
+@@ -657,6 +661,7 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev,
+ 			ret = -EINVAL;
+ 		break;
+ 	case AMDGPU_RAS_BLOCK__UMC:
++	case AMDGPU_RAS_BLOCK__MMHUB:
+ 		ret = psp_ras_trigger_error(&adev->psp, &block_info);
+ 		break;
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3358-drm-amdgpu-create-mmhub-ras-framework.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3358-drm-amdgpu-create-mmhub-ras-framework.patch
new file mode 100644
index 00000000..659018c6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3358-drm-amdgpu-create-mmhub-ras-framework.patch
@@ -0,0 +1,230 @@
+From 61356ce21d437598963b0261c740a0495b3e677e Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Wed, 7 Aug 2019 12:21:22 +0800
+Subject: [PATCH 3358/4256] drm/amdgpu: create mmhub ras framework
+
+enable mmhub ras feature and create sysfs/debugfs node for mmhub
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |   3 +-
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 112 +++++++++++++++++-------
+ 2 files changed, 82 insertions(+), 33 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+index e43036cefb64..f614ae0302cb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+@@ -177,7 +177,8 @@ struct amdgpu_gmc {
+ 
+ 	struct amdgpu_xgmi xgmi;
+ 	struct amdgpu_irq_src	ecc_irq;
+-	struct ras_common_if    *ras_if;
++	struct ras_common_if    *umc_ras_if;
++	struct ras_common_if    *mmhub_ras_if;
+ };
+ 
+ #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, type) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (type))
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index ca9c06b8e02c..37c0d085d5c9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -263,7 +263,7 @@ static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev,
+ 		struct amdgpu_irq_src *source,
+ 		struct amdgpu_iv_entry *entry)
+ {
+-	struct ras_common_if *ras_if = adev->gmc.ras_if;
++	struct ras_common_if *ras_if = adev->gmc.umc_ras_if;
+ 	struct ras_dispatch_if ih_data = {
+ 		.entry = entry,
+ 	};
+@@ -734,27 +734,25 @@ static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
+-static int gmc_v9_0_ecc_late_init(void *handle)
++static int gmc_v9_0_ecc_ras_block_late_init(void *handle,
++			struct ras_fs_if *fs_info, struct ras_common_if *ras_block)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	struct ras_common_if **ras_if = &adev->gmc.ras_if;
++	struct ras_common_if **ras_if = NULL;
+ 	struct ras_ih_if ih_info = {
+ 		.cb = gmc_v9_0_process_ras_data_cb,
+ 	};
+-	struct ras_fs_if fs_info = {
+-		.sysfs_name = "umc_err_count",
+-		.debugfs_name = "umc_err_inject",
+-	};
+-	struct ras_common_if ras_block = {
+-		.block = AMDGPU_RAS_BLOCK__UMC,
+-		.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
+-		.sub_block_index = 0,
+-		.name = "umc",
+-	};
+ 	int r;
+ 
+-	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) {
+-		amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0);
++	if (ras_block->block == AMDGPU_RAS_BLOCK__UMC)
++		ras_if = &adev->gmc.umc_ras_if;
++	else if (ras_block->block == AMDGPU_RAS_BLOCK__MMHUB)
++		ras_if = &adev->gmc.mmhub_ras_if;
++	else
++		BUG();
++
++	if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
++		amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
+ 		return 0;
+ 	}
+ 
+@@ -769,7 +767,7 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ 			if (r == -EAGAIN) {
+ 				/* request a gpu reset. will run again. */
+ 				amdgpu_ras_request_reset_on_boot(adev,
+-						AMDGPU_RAS_BLOCK__UMC);
++						ras_block->block);
+ 				return 0;
+ 			}
+ 			/* fail to enable ras, cleanup all. */
+@@ -783,41 +781,46 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ 	if (!*ras_if)
+ 		return -ENOMEM;
+ 
+-	**ras_if = ras_block;
++	**ras_if = *ras_block;
+ 
+ 	r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
+ 	if (r) {
+ 		if (r == -EAGAIN) {
+ 			amdgpu_ras_request_reset_on_boot(adev,
+-					AMDGPU_RAS_BLOCK__UMC);
++					ras_block->block);
+ 			r = 0;
+ 		}
+ 		goto feature;
+ 	}
+ 
+ 	ih_info.head = **ras_if;
+-	fs_info.head = **ras_if;
++	fs_info->head = **ras_if;
+ 
+-	r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
+-	if (r)
+-		goto interrupt;
++	if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) {
++		r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
++		if (r)
++			goto interrupt;
++	}
+ 
+-	amdgpu_ras_debugfs_create(adev, &fs_info);
++	amdgpu_ras_debugfs_create(adev, fs_info);
+ 
+-	r = amdgpu_ras_sysfs_create(adev, &fs_info);
++	r = amdgpu_ras_sysfs_create(adev, fs_info);
+ 	if (r)
+ 		goto sysfs;
+ resume:
+-	r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
+-	if (r)
+-		goto irq;
++	if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) {
++		r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
++		if (r)
++			goto irq;
++	}
+ 
+ 	return 0;
+ irq:
+ 	amdgpu_ras_sysfs_remove(adev, *ras_if);
+ sysfs:
+ 	amdgpu_ras_debugfs_remove(adev, *ras_if);
+-	amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
++	if (ras_block->block == AMDGPU_RAS_BLOCK__UMC)
++		amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
+ interrupt:
+ 	amdgpu_ras_feature_enable(adev, *ras_if, 0);
+ feature:
+@@ -826,6 +829,40 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ 	return r;
+ }
+ 
++static int gmc_v9_0_ecc_late_init(void *handle)
++{
++	int r;
++
++	struct ras_fs_if umc_fs_info = {
++		.sysfs_name = "umc_err_count",
++		.debugfs_name = "umc_err_inject",
++	};
++	struct ras_common_if umc_ras_block = {
++		.block = AMDGPU_RAS_BLOCK__UMC,
++		.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
++		.sub_block_index = 0,
++		.name = "umc",
++	};
++	struct ras_fs_if mmhub_fs_info = {
++		.sysfs_name = "mmhub_err_count",
++		.debugfs_name = "mmhub_err_inject",
++	};
++	struct ras_common_if mmhub_ras_block = {
++		.block = AMDGPU_RAS_BLOCK__MMHUB,
++		.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
++		.sub_block_index = 0,
++		.name = "mmhub",
++	};
++
++	r = gmc_v9_0_ecc_ras_block_late_init(handle,
++			&umc_fs_info, &umc_ras_block);
++	if (r)
++		return r;
++
++	r = gmc_v9_0_ecc_ras_block_late_init(handle,
++			&mmhub_fs_info, &mmhub_ras_block);
++	return r;
++}
+ 
+ static int gmc_v9_0_late_init(void *handle)
+ {
+@@ -1186,21 +1223,32 @@ static int gmc_v9_0_sw_fini(void *handle)
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
+ 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
+-			adev->gmc.ras_if) {
+-		struct ras_common_if *ras_if = adev->gmc.ras_if;
++			adev->gmc.umc_ras_if) {
++		struct ras_common_if *ras_if = adev->gmc.umc_ras_if;
+ 		struct ras_ih_if ih_info = {
+ 			.head = *ras_if,
+ 		};
+ 
+-		/*remove fs first*/
++		/* remove fs first */
+ 		amdgpu_ras_debugfs_remove(adev, ras_if);
+ 		amdgpu_ras_sysfs_remove(adev, ras_if);
+-		/*remove the IH*/
++		/* remove the IH */
+ 		amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
+ 		amdgpu_ras_feature_enable(adev, ras_if, 0);
+ 		kfree(ras_if);
+ 	}
+ 
++	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) &&
++			adev->gmc.mmhub_ras_if) {
++		struct ras_common_if *ras_if = adev->gmc.mmhub_ras_if;
++
++		/* remove fs and disable ras feature */
++		amdgpu_ras_debugfs_remove(adev, ras_if);
++		amdgpu_ras_sysfs_remove(adev, ras_if);
++		amdgpu_ras_feature_enable(adev, ras_if, 0);
++		kfree(ras_if);
++	}
++
+ 	amdgpu_gem_force_release(adev);
+ 	amdgpu_vm_manager_fini(adev);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3359-drm-amd-powerplay-change-smu_read_sensor-sequence-in.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3359-drm-amd-powerplay-change-smu_read_sensor-sequence-in.patch
new file mode 100644
index 00000000..d931c94f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3359-drm-amd-powerplay-change-smu_read_sensor-sequence-in.patch
@@ -0,0 +1,124 @@
+From 8b33cca7136c5aa019859361d9a15988d656fbbc Mon Sep 17 00:00:00 2001
+From: Kenneth Feng <kenneth.feng@amd.com>
+Date: Tue, 23 Jul 2019 12:16:25 +0800
+Subject: [PATCH 3359/4256] drm/amd/powerplay: change smu_read_sensor sequence
+ in smu
+
+change the smu_read_sensor sequence to:
+
+asic specific sensor read -> smu v11 specific sensor read -> smu v11 common sensor read
+
+Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     | 3 +++
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++--
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c     | 5 ++++-
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c      | 8 ++++----
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c     | 5 ++++-
+ 5 files changed, 17 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index f21bafb1a0d2..4df7fb6eaf3c 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -413,6 +413,9 @@ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
+ 	struct smu_power_gate *power_gate = &smu_power->power_gate;
+ 	int ret = 0;
+ 
++	if(!data || !size)
++		return -EINVAL;
++
+ 	switch (sensor) {
+ 	case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
+ 		*((uint32_t *)data) = smu->pstate_sclk;
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index f813072ab9e4..ca9b9ec39de8 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -634,9 +634,9 @@ struct smu_funcs
+ #define smu_start_thermal_control(smu) \
+ 	((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
+ #define smu_read_sensor(smu, sensor, data, size) \
+-	((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
+-#define smu_asic_read_sensor(smu, sensor, data, size) \
+ 	((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
++#define smu_smc_read_sensor(smu, sensor, data, size) \
++	((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
+ #define smu_get_power_profile_mode(smu, buf) \
+ 	((smu)->ppt_funcs->get_power_profile_mode ? (smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
+ #define smu_set_power_profile_mode(smu, param, param_size) \
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 7398b281cbb0..907035a6e995 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1365,6 +1365,9 @@ static int navi10_read_sensor(struct smu_context *smu,
+ 	struct smu_table_context *table_context = &smu->smu_table;
+ 	PPTable_t *pptable = table_context->driver_pptable;
+ 
++	if(!data || !size)
++		return -EINVAL;
++
+ 	switch (sensor) {
+ 	case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
+ 		*(uint32_t *)data = pptable->FanMaximumRpm;
+@@ -1386,7 +1389,7 @@ static int navi10_read_sensor(struct smu_context *smu,
+ 		*size = 4;
+ 		break;
+ 	default:
+-		return -EINVAL;
++		ret = smu_smc_read_sensor(smu, sensor, data, size);
+ 	}
+ 
+ 	return ret;
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 91dfae1a2b16..071a63dd4ba2 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1227,6 +1227,10 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
+ 				 void *data, uint32_t *size)
+ {
+ 	int ret = 0;
++
++	if(!data || !size)
++		return -EINVAL;
++
+ 	switch (sensor) {
+ 	case AMDGPU_PP_SENSOR_GFX_MCLK:
+ 		ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
+@@ -1249,10 +1253,6 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
+ 		break;
+ 	}
+ 
+-	/* try get sensor data by asic */
+-	if (ret)
+-		ret = smu_asic_read_sensor(smu, sensor, data, size);
+-
+ 	if (ret)
+ 		*size = 0;
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index e28c004e0036..acf075393c13 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -3011,6 +3011,9 @@ static int vega20_read_sensor(struct smu_context *smu,
+ 	struct smu_table_context *table_context = &smu->smu_table;
+ 	PPTable_t *pptable = table_context->driver_pptable;
+ 
++	if(!data || !size)
++		return -EINVAL;
++
+ 	switch (sensor) {
+ 	case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
+ 		*(uint32_t *)data = pptable->FanMaximumRpm;
+@@ -3034,7 +3037,7 @@ static int vega20_read_sensor(struct smu_context *smu,
+ 		*size = 4;
+ 		break;
+ 	default:
+-		return -EINVAL;
++		ret = smu_smc_read_sensor(smu, sensor, data, size);
+ 	}
+ 
+ 	return ret;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3360-drm-amdgpu-implement-UMC-64-bits-REG-operations.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3360-drm-amdgpu-implement-UMC-64-bits-REG-operations.patch
new file mode 100644
index 00000000..cab6fc21
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3360-drm-amdgpu-implement-UMC-64-bits-REG-operations.patch
@@ -0,0 +1,88 @@
+From 1ce9141a9692fdfb7796a771077e163f43f63f5b Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Fri, 9 Aug 2019 11:41:09 +0800
+Subject: [PATCH 3360/4256] drm/amdgpu: implement UMC 64 bits REG operations
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+implement 64 bits operations via 32 bits interface
+
+v2: make use of lower_32_bits() and upper_32_bits() macros
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h |  9 +++++++++
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.c   | 10 +++++-----
+ 2 files changed, 14 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+index 9efdd66279e5..975afa04df09 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+@@ -21,6 +21,15 @@
+ #ifndef __AMDGPU_UMC_H__
+ #define __AMDGPU_UMC_H__
+ 
++/* implement 64 bits REG operations via 32 bits interface */
++#define RREG64_UMC(reg)	(RREG32(reg) | \
++				((uint64_t)RREG32((reg) + 1) << 32))
++#define WREG64_UMC(reg, v)	\
++	do {	\
++		WREG32((reg), lower_32_bits(v));	\
++		WREG32((reg) + 1, upper_32_bits(v));	\
++	} while (0)
++
+ /*
+  * void (*func)(struct amdgpu_device *adev, struct ras_err_data *err_data,
+  *				uint32_t umc_reg_offset, uint32_t channel_index)
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+index 64df37b860dd..8502e736f721 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+@@ -116,7 +116,7 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
+ 
+ 	/* check for SRAM correctable error
+ 	  MCUMC_STATUS is a 64 bit register */
+-	mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
++	mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
+ 	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
+ 	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
+ 	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
+@@ -134,7 +134,7 @@ static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev
+                 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
+ 
+ 	/* check the MCUMC_STATUS */
+-	mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
++	mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
+ 	if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
+ 	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
+ 	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
+@@ -173,11 +173,11 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
+ 	/* skip error address process if -ENOMEM */
+ 	if (!err_data->err_addr) {
+ 		/* clear umc status */
+-		WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
++		WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
+ 		return;
+ 	}
+ 
+-	mc_umc_status = RREG64(mc_umc_status_addr + umc_reg_offset);
++	mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
+ 
+ 	/* calculate error address if ue/ce error is detected */
+ 	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
+@@ -200,7 +200,7 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
+ 	}
+ 
+ 	/* clear umc status */
+-	WREG64(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
++	WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
+ }
+ 
+ static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3361-drm-amdgpu-remove-RREG64-WREG64.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3361-drm-amdgpu-remove-RREG64-WREG64.patch
new file mode 100644
index 00000000..8815dd96
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3361-drm-amdgpu-remove-RREG64-WREG64.patch
@@ -0,0 +1,87 @@
+From 45d69e65a7f8fcc979cd0856026c5852ca99d8ca Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Fri, 9 Aug 2019 11:51:24 +0800
+Subject: [PATCH 3361/4256] drm/amdgpu: remove RREG64/WREG64
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+atomic 64 bits REG operations are useless currently
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  4 ---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 33 ----------------------
+ 2 files changed, 37 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 1bbe7589af7a..0d68005ceef7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1079,8 +1079,6 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
+ 		    uint32_t acc_flags);
+ void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
+ uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
+-uint64_t amdgpu_mm_rreg64(struct amdgpu_device *adev, uint32_t reg);
+-void amdgpu_mm_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v);
+ 
+ u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
+ void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
+@@ -1108,8 +1106,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
+ #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
+ #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
+ #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
+-#define RREG64(reg) amdgpu_mm_rreg64(adev, (reg))
+-#define WREG64(reg, v) amdgpu_mm_wreg64(adev, (reg), (v))
+ #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
+ #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
+ #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 5bfc5391155b..b4e950504a0e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -262,39 +262,6 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
+ 	}
+ }
+ 
+-/**
+- * amdgpu_mm_rreg64 - read a 64 bit memory mapped IO register
+- *
+- * @adev: amdgpu_device pointer
+- * @reg: dword aligned register offset
+- *
+- * Returns the 64 bit value from the offset specified.
+- */
+-uint64_t amdgpu_mm_rreg64(struct amdgpu_device *adev, uint32_t reg)
+-{
+-	if ((reg * 4) < adev->rmmio_size)
+-		return atomic64_read((atomic64_t *)(adev->rmmio + (reg * 4)));
+-	else
+-		BUG();
+-}
+-
+-/**
+- * amdgpu_mm_wreg64 - write to a 64 bit memory mapped IO register
+- *
+- * @adev: amdgpu_device pointer
+- * @reg: dword aligned register offset
+- * @v: 64 bit value to write to the register
+- *
+- * Writes the value specified to the offset specified.
+- */
+-void amdgpu_mm_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
+-{
+-	if ((reg * 4) < adev->rmmio_size)
+-		atomic64_set((atomic64_t *)(adev->rmmio + (reg * 4)), v);
+-	else
+-		BUG();
+-}
+-
+ /**
+  * amdgpu_io_rreg - read an IO register
+  *
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3362-drm-amdgpu-remove-ras-block-s-feature-status-info-in.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3362-drm-amdgpu-remove-ras-block-s-feature-status-info-in.patch
new file mode 100644
index 00000000..2bce788f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3362-drm-amdgpu-remove-ras-block-s-feature-status-info-in.patch
@@ -0,0 +1,52 @@
+From b40f887824200239ae4baf4a12cf958936db11e5 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Fri, 9 Aug 2019 17:39:06 +0800
+Subject: [PATCH 3362/4256] drm/amdgpu: remove ras block's feature status info
+ in sysfs
+
+feature mask info is enough for rocm tool,
+"cat /sys/class/drm/card0/device/ras/features" will get the
+info like this:
+
+feature mask: 0x3ffb
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 19 +------------------
+ 1 file changed, 1 insertion(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index be59102526a1..50c13b02d234 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -791,25 +791,8 @@ static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
+ {
+ 	struct amdgpu_ras *con =
+ 		container_of(attr, struct amdgpu_ras, features_attr);
+-	struct drm_device *ddev = dev_get_drvdata(dev);
+-	struct amdgpu_device *adev = ddev->dev_private;
+-	struct ras_common_if head;
+-	int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
+-	int i, enabled;
+-	ssize_t s;
+-
+-	s = scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
+-
+-	for (i = 0; i < ras_block_count; i++) {
+-		head.block = i;
+-		enabled = amdgpu_ras_is_feature_enabled(adev, &head);
+-
+-		s += scnprintf(&buf[s], PAGE_SIZE - s,
+-				"%s ras feature mask: %s\n",
+-				ras_block_str(i), enabled?"on":"off");
+-	}
+ 
+-	return s;
++	return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
+ }
+ 
+ static int amdgpu_ras_sysfs_create_feature_node(struct amdgpu_device *adev)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3363-drm-amdgpu-powerplay-update-Arcturus-smu-version-in-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3363-drm-amdgpu-powerplay-update-Arcturus-smu-version-in-.patch
new file mode 100644
index 00000000..6cbd97e4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3363-drm-amdgpu-powerplay-update-Arcturus-smu-version-in-.patch
@@ -0,0 +1,72 @@
+From 68bdf62105778266b6f576304531ecf4e7e07a31 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 9 Aug 2019 15:44:22 +0800
+Subject: [PATCH 3363/4256] drm/amdgpu/powerplay: update Arcturus smu version
+ in new place
+
+Follow patch below:
+    drm/amd/powerplay: re-define smu interface version for smu v11
+
+Change-Id: Id78651209adc7a094f4c19ba965dcded37dd3ba7
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c                 | 1 -
+ drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h | 2 +-
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h                | 1 +
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c                    | 3 +++
+ 4 files changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 52e6214c3f22..6aa135938e00 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -1918,6 +1918,5 @@ void arcturus_set_ppt_funcs(struct smu_context *smu)
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 
+ 	smu->ppt_funcs = &arcturus_ppt_funcs;
+-	smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
+ 	smu_table->table_count = TABLE_COUNT;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+index c7a7953b52b7..b99e98c40720 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+@@ -27,7 +27,7 @@
+ // *** IMPORTANT ***
+ // SMU TEAM: Always increment the interface version if
+ // any structure is changed in this file
+-#define SMU11_DRIVER_IF_VERSION 0x08
++//#define SMU11_DRIVER_IF_VERSION 0x08
+ 
+ #define PPTABLE_ARCTURUS_SMU_VERSION 4
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 97605e963c2b..3e571016df80 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -27,6 +27,7 @@
+ 
+ #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
+ #define SMU11_DRIVER_IF_VERSION_VG20 0x13
++#define SMU11_DRIVER_IF_VERSION_ARCT 0x08
+ #define SMU11_DRIVER_IF_VERSION_NV10 0x33
+ #define SMU11_DRIVER_IF_VERSION_NV14 0x33
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 071a63dd4ba2..3a081acdf1a8 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -275,6 +275,9 @@ static int smu_v11_0_check_fw_version(struct smu_context *smu)
+ 	case CHIP_VEGA20:
+ 		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_VG20;
+ 		break;
++	case CHIP_ARCTURUS:
++		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
++		break;
+ 	case CHIP_NAVI10:
+ 		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV10;
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3364-drm-amd-powerplay-honor-hw-limit-on-fetching-metrics.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3364-drm-amd-powerplay-honor-hw-limit-on-fetching-metrics.patch
new file mode 100644
index 00000000..633e6b7c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3364-drm-amd-powerplay-honor-hw-limit-on-fetching-metrics.patch
@@ -0,0 +1,131 @@
+From 3d70fac9bc2242f6f49db5f6b632d1949f6c6e7a Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Fri, 2 Aug 2019 12:01:00 +0800
+Subject: [PATCH 3364/4256] drm/amd/powerplay: honor hw limit on fetching
+ metrics data for navi10
+
+too frequently to update mertrics table will cause smu internal error.
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 56 +++++++++++++++-------
+ 1 file changed, 38 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 907035a6e995..99c1f94e44d1 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -515,6 +515,8 @@ static int navi10_store_powerplay_table(struct smu_context *smu)
+ 
+ static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
+ {
++	struct smu_table_context *smu_table = &smu->smu_table;
++
+ 	SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
+ 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ 	SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
+@@ -529,9 +531,35 @@ static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
+ 		       sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
+ 	               AMDGPU_GEM_DOMAIN_VRAM);
+ 
++	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
++	if (!smu_table->metrics_table)
++		return -ENOMEM;
++	smu_table->metrics_time = 0;
++
+ 	return 0;
+ }
+ 
++static int navi10_get_metrics_table(struct smu_context *smu,
++				    SmuMetrics_t *metrics_table)
++{
++	struct smu_table_context *smu_table= &smu->smu_table;
++	int ret = 0;
++
++	if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
++		ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
++				(void *)smu_table->metrics_table, false);
++		if (ret) {
++			pr_info("Failed to export SMU metrics table!\n");
++			return ret;
++		}
++		smu_table->metrics_time = jiffies;
++	}
++
++	memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
++
++	return ret;
++}
++
+ static int navi10_allocate_dpm_context(struct smu_context *smu)
+ {
+ 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+@@ -618,15 +646,10 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
+ 				       enum smu_clk_type clk_type,
+ 				       uint32_t *value)
+ {
+-	static SmuMetrics_t metrics;
+ 	int ret = 0, clk_id = 0;
++	SmuMetrics_t metrics;
+ 
+-	if (!value)
+-		return -EINVAL;
+-
+-	memset(&metrics, 0, sizeof(metrics));
+-
+-	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
++	ret = navi10_get_metrics_table(smu, &metrics);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -914,8 +937,9 @@ static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
+ 	if (!value)
+ 		return -EINVAL;
+ 
+-	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics,
+-			       false);
++	ret = navi10_get_metrics_table(smu, &metrics);
++	if (ret)
++		return ret;
+ 	if (ret)
+ 		return ret;
+ 
+@@ -934,10 +958,7 @@ static int navi10_get_current_activity_percent(struct smu_context *smu,
+ 	if (!value)
+ 		return -EINVAL;
+ 
+-	msleep(1);
+-
+-	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
+-			       (void *)&metrics, false);
++	ret = navi10_get_metrics_table(smu, &metrics);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -976,10 +997,9 @@ static int navi10_get_fan_speed_rpm(struct smu_context *smu,
+ 	if (!speed)
+ 		return -EINVAL;
+ 
+-	memset(&metrics, 0, sizeof(metrics));
+-
+-	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
+-			       (void *)&metrics, false);
++	ret = navi10_get_metrics_table(smu, &metrics);
++	if (ret)
++		return ret;
+ 	if (ret)
+ 		return ret;
+ 
+@@ -1332,7 +1352,7 @@ static int navi10_thermal_get_temperature(struct smu_context *smu,
+ 	if (!value)
+ 		return -EINVAL;
+ 
+-	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
++	ret = navi10_get_metrics_table(smu, &metrics);
+ 	if (ret)
+ 		return ret;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3365-drm-amdgpu-fix-gfx9-soft-recovery.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3365-drm-amdgpu-fix-gfx9-soft-recovery.patch
new file mode 100644
index 00000000..3b53c603
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3365-drm-amdgpu-fix-gfx9-soft-recovery.patch
@@ -0,0 +1,35 @@
+From 08b3d96b9e002eca6c564bfd79246e347f4d0efd Mon Sep 17 00:00:00 2001
+From: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
+Date: Tue, 6 Aug 2019 18:27:26 +0200
+Subject: [PATCH 3365/4256] drm/amdgpu: fix gfx9 soft recovery
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The SOC15_REG_OFFSET() macro wasn't used, making the soft recovery fail.
+
+v2: use WREG32_SOC15 instead of WREG32 + SOC15_REG_OFFSET
+
+Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index c25002329728..5188a5ea5ffc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -5402,7 +5402,7 @@ static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
+ 	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
+ 	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
+ 	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
+-	WREG32(mmSQ_CMD, value);
++	WREG32_SOC15(GC, 0, mmSQ_CMD, value);
+ }
+ 
+ static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3366-drm-amd-display-use-kvmalloc-for-dc_state-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3366-drm-amd-display-use-kvmalloc-for-dc_state-v2.patch
new file mode 100644
index 00000000..995c4c97
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3366-drm-amd-display-use-kvmalloc-for-dc_state-v2.patch
@@ -0,0 +1,57 @@
+From 883bc9f7e09949638a8292489a27be34bfe771f0 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 8 Aug 2019 00:29:23 -0500
+Subject: [PATCH 3366/4256] drm/amd/display: use kvmalloc for dc_state (v2)
+
+It's large and doesn't need contiguous memory.  Fixes
+allocation failures in some cases.
+
+v2: kvfree the memory.
+
+Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index bc48e8e6ce4d..51653834dab6 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1193,8 +1193,8 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
+ 
+ struct dc_state *dc_create_state(struct dc *dc)
+ {
+-	struct dc_state *context = kzalloc(sizeof(struct dc_state),
+-					   GFP_KERNEL);
++	struct dc_state *context = kvzalloc(sizeof(struct dc_state),
++					    GFP_KERNEL);
+ 
+ 	if (!context)
+ 		return NULL;
+@@ -1214,11 +1214,11 @@ struct dc_state *dc_create_state(struct dc *dc)
+ struct dc_state *dc_copy_state(struct dc_state *src_ctx)
+ {
+ 	int i, j;
+-	struct dc_state *new_ctx = kmemdup(src_ctx,
+-			sizeof(struct dc_state), GFP_KERNEL);
++	struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
+ 
+ 	if (!new_ctx)
+ 		return NULL;
++	memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
+ 
+ 	for (i = 0; i < MAX_PIPES; i++) {
+ 			struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
+@@ -1252,7 +1252,7 @@ static void dc_state_free(struct kref *kref)
+ {
+ 	struct dc_state *context = container_of(kref, struct dc_state, refcount);
+ 	dc_resource_state_destruct(context);
+-	kfree(context);
++	kvfree(context);
+ }
+ 
+ void dc_release_state(struct dc_state *context)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3367-drm-amd-display-Fix-a-typo-dce_aduio_mask-dce_audio_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3367-drm-amd-display-Fix-a-typo-dce_aduio_mask-dce_audio_.patch
new file mode 100644
index 00000000..fb6280ee
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3367-drm-amd-display-Fix-a-typo-dce_aduio_mask-dce_audio_.patch
@@ -0,0 +1,160 @@
+From 506545d6735e47440c4278813370ba79079e27ed Mon Sep 17 00:00:00 2001
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Date: Fri, 9 Aug 2019 22:12:19 +0200
+Subject: [PATCH 3367/4256] drm/amd/display: Fix a typo - dce_aduio_mask -->
+ dce_audio_mask
+
+This should be 'dce_audio_mask', not 'dce_aduio_mask'.
+
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_audio.c          | 2 +-
+ drivers/gpu/drm/amd/display/dc/dce/dce_audio.h          | 6 +++---
+ drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c   | 2 +-
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c   | 2 +-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c   | 2 +-
+ 9 files changed, 11 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+index ad7bc7d44268..b7d63ca126df 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+@@ -934,7 +934,7 @@ struct audio *dce_audio_create(
+ 		unsigned int inst,
+ 		const struct dce_audio_registers *reg,
+ 		const struct dce_audio_shift *shifts,
+-		const struct dce_aduio_mask *masks
++		const struct dce_audio_mask *masks
+ 		)
+ {
+ 	struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
+index a0d5724aab31..1392fab0860b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
+@@ -101,7 +101,7 @@ struct dce_audio_shift {
+ 	uint32_t DCCG_AUDIO_DTO1_USE_512FBR_DTO;
+ };
+ 
+-struct dce_aduio_mask {
++struct dce_audio_mask {
+ 	uint32_t AZALIA_ENDPOINT_REG_INDEX;
+ 	uint32_t AZALIA_ENDPOINT_REG_DATA;
+ 
+@@ -125,7 +125,7 @@ struct dce_audio {
+ 	struct audio base;
+ 	const struct dce_audio_registers *regs;
+ 	const struct dce_audio_shift *shifts;
+-	const struct dce_aduio_mask *masks;
++	const struct dce_audio_mask *masks;
+ };
+ 
+ struct audio *dce_audio_create(
+@@ -133,7 +133,7 @@ struct audio *dce_audio_create(
+ 		unsigned int inst,
+ 		const struct dce_audio_registers *reg,
+ 		const struct dce_audio_shift *shifts,
+-		const struct dce_aduio_mask *masks);
++		const struct dce_audio_mask *masks);
+ 
+ void dce_aud_destroy(struct audio **audio);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+index ae87c5017756..bb199534ea3b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+@@ -301,7 +301,7 @@ static const struct dce_audio_shift audio_shift = {
+ 		AUD_COMMON_MASK_SH_LIST(__SHIFT)
+ };
+ 
+-static const struct dce_aduio_mask audio_mask = {
++static const struct dce_audio_mask audio_mask = {
+ 		AUD_COMMON_MASK_SH_LIST(_MASK)
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index 113cfb3d972c..ae89721c3a99 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -329,7 +329,7 @@ static const struct dce_audio_shift audio_shift = {
+ 		AUD_COMMON_MASK_SH_LIST(__SHIFT)
+ };
+ 
+-static const struct dce_aduio_mask audio_mask = {
++static const struct dce_audio_mask audio_mask = {
+ 		AUD_COMMON_MASK_SH_LIST(_MASK)
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+index 1c3e8939696a..e327d98b54ca 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+@@ -335,7 +335,7 @@ static const struct dce_audio_shift audio_shift = {
+ 		AUD_COMMON_MASK_SH_LIST(__SHIFT)
+ };
+ 
+-static const struct dce_aduio_mask audio_mask = {
++static const struct dce_audio_mask audio_mask = {
+ 		AUD_COMMON_MASK_SH_LIST(_MASK)
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index 719c020cc1f7..c4588d6462a4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -350,7 +350,7 @@ static const struct dce_audio_shift audio_shift = {
+ 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
+ };
+ 
+-static const struct dce_aduio_mask audio_mask = {
++static const struct dce_audio_mask audio_mask = {
+ 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+index 69e9325e0f74..2f224e1ae5f2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -323,7 +323,7 @@ static const struct dce_audio_shift audio_shift = {
+ 		AUD_COMMON_MASK_SH_LIST(__SHIFT)
+ };
+ 
+-static const struct dce_aduio_mask audio_mask = {
++static const struct dce_audio_mask audio_mask = {
+ 		AUD_COMMON_MASK_SH_LIST(_MASK)
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index 2a01645c4bfd..cd223603a0a8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -268,7 +268,7 @@ static const struct dce_audio_shift audio_shift = {
+ 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
+ };
+ 
+-static const struct dce_aduio_mask audio_mask = {
++static const struct dce_audio_mask audio_mask = {
+ 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 42d3666f2037..291846cc4f21 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -422,7 +422,7 @@ static const struct dce_audio_shift audio_shift = {
+ 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
+ };
+ 
+-static const struct dce_aduio_mask audio_mask = {
++static const struct dce_audio_mask audio_mask = {
+ 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3368-drm-amd-powerplay-remove-redundant-duplicated-return.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3368-drm-amd-powerplay-remove-redundant-duplicated-return.patch
new file mode 100644
index 00000000..43af0e5b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3368-drm-amd-powerplay-remove-redundant-duplicated-return.patch
@@ -0,0 +1,43 @@
+From 24e0d3ddd845c28240b9c84d4c429c95b33e66a5 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Mon, 5 Aug 2019 11:29:40 +0100
+Subject: [PATCH 3368/4256] drm/amd/powerplay: remove redundant duplicated
+ return check
+
+The check on ret is duplicated in two places, it is redundant code.
+Remove it.
+
+Addresses-Coverity: ("Logically dead code")
+Fixes: b94afb61cdae ("drm/amd/powerplay: honor hw limit on fetching metrics data for navi10")
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 99c1f94e44d1..920156e9fb9d 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -940,8 +940,6 @@ static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
+ 	ret = navi10_get_metrics_table(smu, &metrics);
+ 	if (ret)
+ 		return ret;
+-	if (ret)
+-		return ret;
+ 
+ 	*value = metrics.AverageSocketPower << 8;
+ 
+@@ -1000,8 +998,6 @@ static int navi10_get_fan_speed_rpm(struct smu_context *smu,
+ 	ret = navi10_get_metrics_table(smu, &metrics);
+ 	if (ret)
+ 		return ret;
+-	if (ret)
+-		return ret;
+ 
+ 	*speed = metrics.CurrFanSpeed;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3369-drm-amdgpu-add-renoir-header-files-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3369-drm-amdgpu-add-renoir-header-files-v2.patch
new file mode 100644
index 00000000..055d335a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3369-drm-amdgpu-add-renoir-header-files-v2.patch
@@ -0,0 +1,1237 @@
+From 08901ff9c37abb93ba846ad40117eb8696f1dfe7 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Thu, 25 Oct 2018 19:49:10 +0800
+Subject: [PATCH 3369/4256] drm/amdgpu: add renoir header files (v2)
+
+This patch add all renoir header files.
+
+v2: clean up headers (Alex)
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../include/asic_reg/mp/mp_12_0_0_offset.h    | 336 +++++++
+ .../include/asic_reg/mp/mp_12_0_0_sh_mask.h   | 866 ++++++++++++++++++
+ 2 files changed, 1202 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_offset.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_offset.h
+new file mode 100644
+index 000000000000..1fe51fcb648e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_offset.h
+@@ -0,0 +1,336 @@
++/*
++ * Copyright (C) 2019  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _mp_12_0_0_OFFSET_HEADER
++#define _mp_12_0_0_OFFSET_HEADER
++
++
++
++// addressBlock: mp_SmuMp0_SmnDec
++// base address: 0x0
++#define mmMP0_SMN_C2PMSG_32                                                                            0x0060
++#define mmMP0_SMN_C2PMSG_32_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_33                                                                            0x0061
++#define mmMP0_SMN_C2PMSG_33_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_34                                                                            0x0062
++#define mmMP0_SMN_C2PMSG_34_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_35                                                                            0x0063
++#define mmMP0_SMN_C2PMSG_35_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_36                                                                            0x0064
++#define mmMP0_SMN_C2PMSG_36_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_37                                                                            0x0065
++#define mmMP0_SMN_C2PMSG_37_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_38                                                                            0x0066
++#define mmMP0_SMN_C2PMSG_38_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_39                                                                            0x0067
++#define mmMP0_SMN_C2PMSG_39_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_40                                                                            0x0068
++#define mmMP0_SMN_C2PMSG_40_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_41                                                                            0x0069
++#define mmMP0_SMN_C2PMSG_41_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_42                                                                            0x006a
++#define mmMP0_SMN_C2PMSG_42_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_43                                                                            0x006b
++#define mmMP0_SMN_C2PMSG_43_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_44                                                                            0x006c
++#define mmMP0_SMN_C2PMSG_44_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_45                                                                            0x006d
++#define mmMP0_SMN_C2PMSG_45_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_46                                                                            0x006e
++#define mmMP0_SMN_C2PMSG_46_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_47                                                                            0x006f
++#define mmMP0_SMN_C2PMSG_47_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_48                                                                            0x0070
++#define mmMP0_SMN_C2PMSG_48_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_49                                                                            0x0071
++#define mmMP0_SMN_C2PMSG_49_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_50                                                                            0x0072
++#define mmMP0_SMN_C2PMSG_50_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_51                                                                            0x0073
++#define mmMP0_SMN_C2PMSG_51_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_52                                                                            0x0074
++#define mmMP0_SMN_C2PMSG_52_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_53                                                                            0x0075
++#define mmMP0_SMN_C2PMSG_53_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_54                                                                            0x0076
++#define mmMP0_SMN_C2PMSG_54_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_55                                                                            0x0077
++#define mmMP0_SMN_C2PMSG_55_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_56                                                                            0x0078
++#define mmMP0_SMN_C2PMSG_56_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_57                                                                            0x0079
++#define mmMP0_SMN_C2PMSG_57_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_58                                                                            0x007a
++#define mmMP0_SMN_C2PMSG_58_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_59                                                                            0x007b
++#define mmMP0_SMN_C2PMSG_59_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_60                                                                            0x007c
++#define mmMP0_SMN_C2PMSG_60_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_61                                                                            0x007d
++#define mmMP0_SMN_C2PMSG_61_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_62                                                                            0x007e
++#define mmMP0_SMN_C2PMSG_62_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_63                                                                            0x007f
++#define mmMP0_SMN_C2PMSG_63_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_64                                                                            0x0080
++#define mmMP0_SMN_C2PMSG_64_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_65                                                                            0x0081
++#define mmMP0_SMN_C2PMSG_65_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_66                                                                            0x0082
++#define mmMP0_SMN_C2PMSG_66_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_67                                                                            0x0083
++#define mmMP0_SMN_C2PMSG_67_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_68                                                                            0x0084
++#define mmMP0_SMN_C2PMSG_68_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_69                                                                            0x0085
++#define mmMP0_SMN_C2PMSG_69_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_70                                                                            0x0086
++#define mmMP0_SMN_C2PMSG_70_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_71                                                                            0x0087
++#define mmMP0_SMN_C2PMSG_71_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_72                                                                            0x0088
++#define mmMP0_SMN_C2PMSG_72_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_73                                                                            0x0089
++#define mmMP0_SMN_C2PMSG_73_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_74                                                                            0x008a
++#define mmMP0_SMN_C2PMSG_74_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_75                                                                            0x008b
++#define mmMP0_SMN_C2PMSG_75_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_76                                                                            0x008c
++#define mmMP0_SMN_C2PMSG_76_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_77                                                                            0x008d
++#define mmMP0_SMN_C2PMSG_77_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_78                                                                            0x008e
++#define mmMP0_SMN_C2PMSG_78_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_79                                                                            0x008f
++#define mmMP0_SMN_C2PMSG_79_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_80                                                                            0x0090
++#define mmMP0_SMN_C2PMSG_80_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_81                                                                            0x0091
++#define mmMP0_SMN_C2PMSG_81_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_82                                                                            0x0092
++#define mmMP0_SMN_C2PMSG_82_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_83                                                                            0x0093
++#define mmMP0_SMN_C2PMSG_83_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_84                                                                            0x0094
++#define mmMP0_SMN_C2PMSG_84_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_85                                                                            0x0095
++#define mmMP0_SMN_C2PMSG_85_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_86                                                                            0x0096
++#define mmMP0_SMN_C2PMSG_86_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_87                                                                            0x0097
++#define mmMP0_SMN_C2PMSG_87_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_88                                                                            0x0098
++#define mmMP0_SMN_C2PMSG_88_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_89                                                                            0x0099
++#define mmMP0_SMN_C2PMSG_89_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_90                                                                            0x009a
++#define mmMP0_SMN_C2PMSG_90_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_91                                                                            0x009b
++#define mmMP0_SMN_C2PMSG_91_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_92                                                                            0x009c
++#define mmMP0_SMN_C2PMSG_92_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_93                                                                            0x009d
++#define mmMP0_SMN_C2PMSG_93_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_94                                                                            0x009e
++#define mmMP0_SMN_C2PMSG_94_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_95                                                                            0x009f
++#define mmMP0_SMN_C2PMSG_95_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_96                                                                            0x00a0
++#define mmMP0_SMN_C2PMSG_96_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_97                                                                            0x00a1
++#define mmMP0_SMN_C2PMSG_97_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_98                                                                            0x00a2
++#define mmMP0_SMN_C2PMSG_98_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_99                                                                            0x00a3
++#define mmMP0_SMN_C2PMSG_99_BASE_IDX                                                                   0
++#define mmMP0_SMN_C2PMSG_100                                                                           0x00a4
++#define mmMP0_SMN_C2PMSG_100_BASE_IDX                                                                  0
++#define mmMP0_SMN_C2PMSG_101                                                                           0x00a5
++#define mmMP0_SMN_C2PMSG_101_BASE_IDX                                                                  0
++#define mmMP0_SMN_C2PMSG_102                                                                           0x00a6
++#define mmMP0_SMN_C2PMSG_102_BASE_IDX                                                                  0
++#define mmMP0_SMN_C2PMSG_103                                                                           0x00a7
++#define mmMP0_SMN_C2PMSG_103_BASE_IDX                                                                  0
++#define mmMP0_SMN_IH_CREDIT                                                                            0x00c1
++#define mmMP0_SMN_IH_CREDIT_BASE_IDX                                                                   0
++#define mmMP0_SMN_IH_SW_INT                                                                            0x00c2
++#define mmMP0_SMN_IH_SW_INT_BASE_IDX                                                                   0
++#define mmMP0_SMN_IH_SW_INT_CTRL                                                                       0x00c3
++#define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              0
++
++
++// addressBlock: mp_SmuMp1_SmnDec
++// base address: 0x0
++#define mmMP1_SMN_C2PMSG_32                                                                            0x0260
++#define mmMP1_SMN_C2PMSG_32_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_33                                                                            0x0261
++#define mmMP1_SMN_C2PMSG_33_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_34                                                                            0x0262
++#define mmMP1_SMN_C2PMSG_34_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_35                                                                            0x0263
++#define mmMP1_SMN_C2PMSG_35_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_36                                                                            0x0264
++#define mmMP1_SMN_C2PMSG_36_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_37                                                                            0x0265
++#define mmMP1_SMN_C2PMSG_37_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_38                                                                            0x0266
++#define mmMP1_SMN_C2PMSG_38_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_39                                                                            0x0267
++#define mmMP1_SMN_C2PMSG_39_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_40                                                                            0x0268
++#define mmMP1_SMN_C2PMSG_40_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_41                                                                            0x0269
++#define mmMP1_SMN_C2PMSG_41_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_42                                                                            0x026a
++#define mmMP1_SMN_C2PMSG_42_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_43                                                                            0x026b
++#define mmMP1_SMN_C2PMSG_43_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_44                                                                            0x026c
++#define mmMP1_SMN_C2PMSG_44_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_45                                                                            0x026d
++#define mmMP1_SMN_C2PMSG_45_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_46                                                                            0x026e
++#define mmMP1_SMN_C2PMSG_46_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_47                                                                            0x026f
++#define mmMP1_SMN_C2PMSG_47_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_48                                                                            0x0270
++#define mmMP1_SMN_C2PMSG_48_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_49                                                                            0x0271
++#define mmMP1_SMN_C2PMSG_49_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_50                                                                            0x0272
++#define mmMP1_SMN_C2PMSG_50_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_51                                                                            0x0273
++#define mmMP1_SMN_C2PMSG_51_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_52                                                                            0x0274
++#define mmMP1_SMN_C2PMSG_52_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_53                                                                            0x0275
++#define mmMP1_SMN_C2PMSG_53_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_54                                                                            0x0276
++#define mmMP1_SMN_C2PMSG_54_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_55                                                                            0x0277
++#define mmMP1_SMN_C2PMSG_55_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_56                                                                            0x0278
++#define mmMP1_SMN_C2PMSG_56_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_57                                                                            0x0279
++#define mmMP1_SMN_C2PMSG_57_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_58                                                                            0x027a
++#define mmMP1_SMN_C2PMSG_58_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_59                                                                            0x027b
++#define mmMP1_SMN_C2PMSG_59_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_60                                                                            0x027c
++#define mmMP1_SMN_C2PMSG_60_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_61                                                                            0x027d
++#define mmMP1_SMN_C2PMSG_61_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_62                                                                            0x027e
++#define mmMP1_SMN_C2PMSG_62_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_63                                                                            0x027f
++#define mmMP1_SMN_C2PMSG_63_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_64                                                                            0x0280
++#define mmMP1_SMN_C2PMSG_64_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_65                                                                            0x0281
++#define mmMP1_SMN_C2PMSG_65_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_66                                                                            0x0282
++#define mmMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_67                                                                            0x0283
++#define mmMP1_SMN_C2PMSG_67_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_68                                                                            0x0284
++#define mmMP1_SMN_C2PMSG_68_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_69                                                                            0x0285
++#define mmMP1_SMN_C2PMSG_69_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_70                                                                            0x0286
++#define mmMP1_SMN_C2PMSG_70_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_71                                                                            0x0287
++#define mmMP1_SMN_C2PMSG_71_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_72                                                                            0x0288
++#define mmMP1_SMN_C2PMSG_72_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_73                                                                            0x0289
++#define mmMP1_SMN_C2PMSG_73_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_74                                                                            0x028a
++#define mmMP1_SMN_C2PMSG_74_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_75                                                                            0x028b
++#define mmMP1_SMN_C2PMSG_75_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_76                                                                            0x028c
++#define mmMP1_SMN_C2PMSG_76_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_77                                                                            0x028d
++#define mmMP1_SMN_C2PMSG_77_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_78                                                                            0x028e
++#define mmMP1_SMN_C2PMSG_78_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_79                                                                            0x028f
++#define mmMP1_SMN_C2PMSG_79_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_80                                                                            0x0290
++#define mmMP1_SMN_C2PMSG_80_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_81                                                                            0x0291
++#define mmMP1_SMN_C2PMSG_81_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_82                                                                            0x0292
++#define mmMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_83                                                                            0x0293
++#define mmMP1_SMN_C2PMSG_83_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_84                                                                            0x0294
++#define mmMP1_SMN_C2PMSG_84_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_85                                                                            0x0295
++#define mmMP1_SMN_C2PMSG_85_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_86                                                                            0x0296
++#define mmMP1_SMN_C2PMSG_86_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_87                                                                            0x0297
++#define mmMP1_SMN_C2PMSG_87_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_88                                                                            0x0298
++#define mmMP1_SMN_C2PMSG_88_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_89                                                                            0x0299
++#define mmMP1_SMN_C2PMSG_89_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_90                                                                            0x029a
++#define mmMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_91                                                                            0x029b
++#define mmMP1_SMN_C2PMSG_91_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_92                                                                            0x029c
++#define mmMP1_SMN_C2PMSG_92_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_93                                                                            0x029d
++#define mmMP1_SMN_C2PMSG_93_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_94                                                                            0x029e
++#define mmMP1_SMN_C2PMSG_94_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_95                                                                            0x029f
++#define mmMP1_SMN_C2PMSG_95_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_96                                                                            0x02a0
++#define mmMP1_SMN_C2PMSG_96_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_97                                                                            0x02a1
++#define mmMP1_SMN_C2PMSG_97_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_98                                                                            0x02a2
++#define mmMP1_SMN_C2PMSG_98_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_99                                                                            0x02a3
++#define mmMP1_SMN_C2PMSG_99_BASE_IDX                                                                   0
++#define mmMP1_SMN_C2PMSG_100                                                                           0x02a4
++#define mmMP1_SMN_C2PMSG_100_BASE_IDX                                                                  0
++#define mmMP1_SMN_C2PMSG_101                                                                           0x02a5
++#define mmMP1_SMN_C2PMSG_101_BASE_IDX                                                                  0
++#define mmMP1_SMN_C2PMSG_102                                                                           0x02a6
++#define mmMP1_SMN_C2PMSG_102_BASE_IDX                                                                  0
++#define mmMP1_SMN_C2PMSG_103                                                                           0x02a7
++#define mmMP1_SMN_C2PMSG_103_BASE_IDX                                                                  0
++#define mmMP1_SMN_IH_CREDIT                                                                            0x02c1
++#define mmMP1_SMN_IH_CREDIT_BASE_IDX                                                                   0
++#define mmMP1_SMN_IH_SW_INT                                                                            0x02c2
++#define mmMP1_SMN_IH_SW_INT_BASE_IDX                                                                   0
++#define mmMP1_SMN_IH_SW_INT_CTRL                                                                       0x02c3
++#define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              0
++#define mmMP1_SMN_FPS_CNT                                                                              0x02c4
++#define mmMP1_SMN_FPS_CNT_BASE_IDX                                                                     0
++
++
++#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h
+new file mode 100644
+index 000000000000..c78151e624b3
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h
+@@ -0,0 +1,866 @@
++/*
++ * Copyright (C) 2019  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _mp_12_0_0_SH_MASK_HEADER
++#define _mp_12_0_0_SH_MASK_HEADER
++
++
++// addressBlock: mp_SmuMp0_SmnDec
++//MP0_SMN_C2PMSG_32
++#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_32__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_33
++#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_33__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_34
++#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_34__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_35
++#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_35__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_36
++#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_36__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_37
++#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_37__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_38
++#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_38__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_39
++#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_39__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_40
++#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_40__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_41
++#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_41__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_42
++#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_42__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_43
++#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_43__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_44
++#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_44__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_45
++#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_45__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_46
++#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_46__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_47
++#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_47__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_48
++#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_48__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_49
++#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_49__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_50
++#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_50__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_51
++#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_51__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_52
++#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_52__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_53
++#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_53__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_54
++#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_54__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_55
++#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_55__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_56
++#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_56__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_57
++#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_57__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_58
++#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_58__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_59
++#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_59__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_60
++#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_60__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_61
++#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_61__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_62
++#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_62__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_63
++#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_63__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_64
++#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_64__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_65
++#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_65__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_66
++#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_66__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_67
++#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_67__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_68
++#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_68__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_69
++#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_69__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_70
++#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_70__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_71
++#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_71__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_72
++#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_72__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_73
++#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_73__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_74
++#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_74__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_75
++#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_75__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_76
++#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_76__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_77
++#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_77__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_78
++#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_78__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_79
++#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_79__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_80
++#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_80__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_81
++#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_81__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_82
++#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_82__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_83
++#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_83__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_84
++#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_84__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_85
++#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_85__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_86
++#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_86__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_87
++#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_87__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_88
++#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_88__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_89
++#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_89__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_90
++#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_90__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_91
++#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_91__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_92
++#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_92__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_93
++#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_93__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_94
++#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_94__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_95
++#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_95__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_96
++#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_96__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_97
++#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_97__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_98
++#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_98__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_99
++#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT                                                                     0x0
++#define MP0_SMN_C2PMSG_99__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP0_SMN_C2PMSG_100
++#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT                                                                    0x0
++#define MP0_SMN_C2PMSG_100__CONTENT_MASK                                                                      0xFFFFFFFFL
++//MP0_SMN_C2PMSG_101
++#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT                                                                    0x0
++#define MP0_SMN_C2PMSG_101__CONTENT_MASK                                                                      0xFFFFFFFFL
++//MP0_SMN_C2PMSG_102
++#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT                                                                    0x0
++#define MP0_SMN_C2PMSG_102__CONTENT_MASK                                                                      0xFFFFFFFFL
++//MP0_SMN_C2PMSG_103
++#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0
++#define MP0_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL
++//MP0_SMN_IH_CREDIT
++#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0
++#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10
++#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                  0x00000003L
++#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                     0x00FF0000L
++//MP0_SMN_IH_SW_INT
++#define MP0_SMN_IH_SW_INT__ID__SHIFT                                                                          0x0
++#define MP0_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
++#define MP0_SMN_IH_SW_INT__ID_MASK                                                                            0x000000FFL
++#define MP0_SMN_IH_SW_INT__VALID_MASK                                                                         0x00000100L
++
++
++// addressBlock: mp_SmuMp1_SmnDec
++//MP1_SMN_C2PMSG_32
++#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_32__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_33
++#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_33__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_34
++#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_34__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_35
++#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_35__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_36
++#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_36__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_37
++#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_37__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_38
++#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_38__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_39
++#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_39__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_40
++#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_40__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_41
++#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_41__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_42
++#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_42__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_43
++#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_43__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_44
++#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_44__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_45
++#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_45__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_46
++#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_46__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_47
++#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_47__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_48
++#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_48__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_49
++#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_49__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_50
++#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_50__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_51
++#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_51__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_52
++#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_52__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_53
++#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_53__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_54
++#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_54__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_55
++#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_55__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_56
++#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_56__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_57
++#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_57__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_58
++#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_58__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_59
++#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_59__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_60
++#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_60__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_61
++#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_61__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_62
++#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_62__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_63
++#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_63__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_64
++#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_64__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_65
++#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_65__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_66
++#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_66__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_67
++#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_67__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_68
++#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_68__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_69
++#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_69__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_70
++#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_70__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_71
++#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_71__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_72
++#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_72__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_73
++#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_73__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_74
++#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_74__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_75
++#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_75__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_76
++#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_76__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_77
++#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_77__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_78
++#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_78__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_79
++#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_79__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_80
++#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_80__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_81
++#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_81__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_82
++#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_82__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_83
++#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_83__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_84
++#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_84__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_85
++#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_85__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_86
++#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_86__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_87
++#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_87__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_88
++#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_88__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_89
++#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_89__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_90
++#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_90__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_91
++#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_91__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_92
++#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_92__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_93
++#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_93__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_94
++#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_94__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_95
++#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_95__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_96
++#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_96__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_97
++#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_97__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_98
++#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_98__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_99
++#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT                                                                     0x0
++#define MP1_SMN_C2PMSG_99__CONTENT_MASK                                                                       0xFFFFFFFFL
++//MP1_SMN_C2PMSG_100
++#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT                                                                    0x0
++#define MP1_SMN_C2PMSG_100__CONTENT_MASK                                                                      0xFFFFFFFFL
++//MP1_SMN_C2PMSG_101
++#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT                                                                    0x0
++#define MP1_SMN_C2PMSG_101__CONTENT_MASK                                                                      0xFFFFFFFFL
++//MP1_SMN_C2PMSG_102
++#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT                                                                    0x0
++#define MP1_SMN_C2PMSG_102__CONTENT_MASK                                                                      0xFFFFFFFFL
++//MP1_SMN_C2PMSG_103
++#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0
++#define MP1_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL
++//MP1_SMN_IH_CREDIT
++#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0
++#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10
++#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                  0x00000003L
++#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                     0x00FF0000L
++//MP1_SMN_IH_SW_INT
++#define MP1_SMN_IH_SW_INT__ID__SHIFT                                                                          0x0
++#define MP1_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
++#define MP1_SMN_IH_SW_INT__ID_MASK                                                                            0x000000FFL
++#define MP1_SMN_IH_SW_INT__VALID_MASK                                                                         0x00000100L
++//MP1_SMN_FPS_CNT
++#define MP1_SMN_FPS_CNT__COUNT__SHIFT                                                                         0x0
++#define MP1_SMN_FPS_CNT__COUNT_MASK                                                                           0xFFFFFFFFL
++
++
++// addressBlock: mp_SmuMp0Pub_CruDec
++//MP0_IH_CREDIT
++#define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                    0x0
++#define MP0_IH_CREDIT__CLIENT_ID__SHIFT                                                                       0x10
++#define MP0_IH_CREDIT__CREDIT_VALUE_MASK                                                                      0x00000003L
++#define MP0_IH_CREDIT__CLIENT_ID_MASK                                                                         0x00FF0000L
++//MP0_IH_SW_INT
++#define MP0_IH_SW_INT__ID__SHIFT                                                                              0x0
++#define MP0_IH_SW_INT__VALID__SHIFT                                                                           0x8
++#define MP0_IH_SW_INT__ID_MASK                                                                                0x000000FFL
++#define MP0_IH_SW_INT__VALID_MASK                                                                             0x00000100L
++//MP0_IH_SW_INT_CTRL
++#define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                                   0x0
++#define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                    0x8
++#define MP0_IH_SW_INT_CTRL__INT_MASK_MASK                                                                     0x00000001L
++#define MP0_IH_SW_INT_CTRL__INT_ACK_MASK                                                                      0x00000100L
++
++
++// addressBlock: mp_SmuMp1Pub_CruDec
++//MP1_FIRMWARE_FLAGS
++#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT                                                         0x0
++#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT                                                                   0x1
++#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK                                                           0x00000001L
++#define MP1_FIRMWARE_FLAGS__RESERVED_MASK                                                                     0xFFFFFFFEL
++//MP1_C2PMSG_0
++#define MP1_C2PMSG_0__CONTENT__SHIFT                                                                          0x0
++#define MP1_C2PMSG_0__CONTENT_MASK                                                                            0xFFFFFFFFL
++//MP1_C2PMSG_1
++#define MP1_C2PMSG_1__CONTENT__SHIFT                                                                          0x0
++#define MP1_C2PMSG_1__CONTENT_MASK                                                                            0xFFFFFFFFL
++//MP1_C2PMSG_2
++#define MP1_C2PMSG_2__CONTENT__SHIFT                                                                          0x0
++#define MP1_C2PMSG_2__CONTENT_MASK                                                                            0xFFFFFFFFL
++//MP1_C2PMSG_3
++#define MP1_C2PMSG_3__CONTENT__SHIFT                                                                          0x0
++#define MP1_C2PMSG_3__CONTENT_MASK                                                                            0xFFFFFFFFL
++//MP1_C2PMSG_4
++#define MP1_C2PMSG_4__CONTENT__SHIFT                                                                          0x0
++#define MP1_C2PMSG_4__CONTENT_MASK                                                                            0xFFFFFFFFL
++//MP1_C2PMSG_5
++#define MP1_C2PMSG_5__CONTENT__SHIFT                                                                          0x0
++#define MP1_C2PMSG_5__CONTENT_MASK                                                                            0xFFFFFFFFL
++//MP1_C2PMSG_6
++#define MP1_C2PMSG_6__CONTENT__SHIFT                                                                          0x0
++#define MP1_C2PMSG_6__CONTENT_MASK                                                                            0xFFFFFFFFL
++//MP1_C2PMSG_7
++#define MP1_C2PMSG_7__CONTENT__SHIFT                                                                          0x0
++#define MP1_C2PMSG_7__CONTENT_MASK                                                                            0xFFFFFFFFL
++//MP1_C2PMSG_8
++#define MP1_C2PMSG_8__CONTENT__SHIFT                                                                          0x0
++#define MP1_C2PMSG_8__CONTENT_MASK                                                                            0xFFFFFFFFL
++//MP1_C2PMSG_9
++#define MP1_C2PMSG_9__CONTENT__SHIFT                                                                          0x0
++#define MP1_C2PMSG_9__CONTENT_MASK                                                                            0xFFFFFFFFL
++//MP1_C2PMSG_10
++#define MP1_C2PMSG_10__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_10__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_11
++#define MP1_C2PMSG_11__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_11__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_12
++#define MP1_C2PMSG_12__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_12__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_13
++#define MP1_C2PMSG_13__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_13__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_14
++#define MP1_C2PMSG_14__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_14__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_15
++#define MP1_C2PMSG_15__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_15__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_16
++#define MP1_C2PMSG_16__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_16__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_17
++#define MP1_C2PMSG_17__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_17__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_18
++#define MP1_C2PMSG_18__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_18__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_19
++#define MP1_C2PMSG_19__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_19__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_20
++#define MP1_C2PMSG_20__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_20__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_21
++#define MP1_C2PMSG_21__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_21__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_22
++#define MP1_C2PMSG_22__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_22__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_23
++#define MP1_C2PMSG_23__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_23__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_24
++#define MP1_C2PMSG_24__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_24__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_25
++#define MP1_C2PMSG_25__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_25__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_26
++#define MP1_C2PMSG_26__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_26__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_27
++#define MP1_C2PMSG_27__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_27__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_28
++#define MP1_C2PMSG_28__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_28__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_29
++#define MP1_C2PMSG_29__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_29__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_30
++#define MP1_C2PMSG_30__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_30__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_31
++#define MP1_C2PMSG_31__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_31__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_P2CMSG_0
++#define MP1_P2CMSG_0__CONTENT__SHIFT                                                                          0x0
++#define MP1_P2CMSG_0__CONTENT_MASK                                                                            0xFFFFFFFFL
++//MP1_P2CMSG_1
++#define MP1_P2CMSG_1__CONTENT__SHIFT                                                                          0x0
++#define MP1_P2CMSG_1__CONTENT_MASK                                                                            0xFFFFFFFFL
++//MP1_P2CMSG_2
++#define MP1_P2CMSG_2__CONTENT__SHIFT                                                                          0x0
++#define MP1_P2CMSG_2__CONTENT_MASK                                                                            0xFFFFFFFFL
++//MP1_P2CMSG_3
++#define MP1_P2CMSG_3__CONTENT__SHIFT                                                                          0x0
++#define MP1_P2CMSG_3__CONTENT_MASK                                                                            0xFFFFFFFFL
++//MP1_P2CMSG_INTEN
++#define MP1_P2CMSG_INTEN__INTEN__SHIFT                                                                        0x0
++#define MP1_P2CMSG_INTEN__INTEN_MASK                                                                          0x0000000FL
++//MP1_P2CMSG_INTSTS
++#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT                                                                     0x0
++#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT                                                                     0x1
++#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT                                                                     0x2
++#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT                                                                     0x3
++#define MP1_P2CMSG_INTSTS__INTSTS0_MASK                                                                       0x00000001L
++#define MP1_P2CMSG_INTSTS__INTSTS1_MASK                                                                       0x00000002L
++#define MP1_P2CMSG_INTSTS__INTSTS2_MASK                                                                       0x00000004L
++#define MP1_P2CMSG_INTSTS__INTSTS3_MASK                                                                       0x00000008L
++//MP1_C2PMSG_32
++#define MP1_C2PMSG_32__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_32__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_33
++#define MP1_C2PMSG_33__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_33__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_34
++#define MP1_C2PMSG_34__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_34__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_35
++#define MP1_C2PMSG_35__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_35__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_36
++#define MP1_C2PMSG_36__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_36__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_37
++#define MP1_C2PMSG_37__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_37__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_38
++#define MP1_C2PMSG_38__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_38__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_39
++#define MP1_C2PMSG_39__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_39__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_40
++#define MP1_C2PMSG_40__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_40__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_41
++#define MP1_C2PMSG_41__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_41__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_42
++#define MP1_C2PMSG_42__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_42__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_43
++#define MP1_C2PMSG_43__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_43__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_44
++#define MP1_C2PMSG_44__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_44__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_45
++#define MP1_C2PMSG_45__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_45__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_46
++#define MP1_C2PMSG_46__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_46__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_47
++#define MP1_C2PMSG_47__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_47__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_48
++#define MP1_C2PMSG_48__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_48__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_49
++#define MP1_C2PMSG_49__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_49__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_50
++#define MP1_C2PMSG_50__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_50__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_51
++#define MP1_C2PMSG_51__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_51__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_52
++#define MP1_C2PMSG_52__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_52__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_53
++#define MP1_C2PMSG_53__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_53__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_54
++#define MP1_C2PMSG_54__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_54__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_55
++#define MP1_C2PMSG_55__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_55__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_56
++#define MP1_C2PMSG_56__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_56__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_57
++#define MP1_C2PMSG_57__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_57__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_58
++#define MP1_C2PMSG_58__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_58__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_59
++#define MP1_C2PMSG_59__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_59__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_60
++#define MP1_C2PMSG_60__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_60__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_61
++#define MP1_C2PMSG_61__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_61__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_62
++#define MP1_C2PMSG_62__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_62__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_63
++#define MP1_C2PMSG_63__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_63__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_64
++#define MP1_C2PMSG_64__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_64__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_65
++#define MP1_C2PMSG_65__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_65__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_66
++#define MP1_C2PMSG_66__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_66__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_67
++#define MP1_C2PMSG_67__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_67__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_68
++#define MP1_C2PMSG_68__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_68__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_69
++#define MP1_C2PMSG_69__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_69__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_70
++#define MP1_C2PMSG_70__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_70__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_71
++#define MP1_C2PMSG_71__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_71__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_72
++#define MP1_C2PMSG_72__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_72__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_73
++#define MP1_C2PMSG_73__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_73__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_74
++#define MP1_C2PMSG_74__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_74__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_75
++#define MP1_C2PMSG_75__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_75__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_76
++#define MP1_C2PMSG_76__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_76__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_77
++#define MP1_C2PMSG_77__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_77__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_78
++#define MP1_C2PMSG_78__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_78__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_79
++#define MP1_C2PMSG_79__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_79__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_80
++#define MP1_C2PMSG_80__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_80__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_81
++#define MP1_C2PMSG_81__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_81__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_82
++#define MP1_C2PMSG_82__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_82__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_83
++#define MP1_C2PMSG_83__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_83__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_84
++#define MP1_C2PMSG_84__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_84__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_85
++#define MP1_C2PMSG_85__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_85__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_86
++#define MP1_C2PMSG_86__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_86__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_87
++#define MP1_C2PMSG_87__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_87__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_88
++#define MP1_C2PMSG_88__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_88__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_89
++#define MP1_C2PMSG_89__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_89__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_90
++#define MP1_C2PMSG_90__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_90__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_91
++#define MP1_C2PMSG_91__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_91__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_92
++#define MP1_C2PMSG_92__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_92__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_93
++#define MP1_C2PMSG_93__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_93__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_94
++#define MP1_C2PMSG_94__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_94__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_95
++#define MP1_C2PMSG_95__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_95__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_96
++#define MP1_C2PMSG_96__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_96__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_97
++#define MP1_C2PMSG_97__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_97__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_98
++#define MP1_C2PMSG_98__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_98__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_99
++#define MP1_C2PMSG_99__CONTENT__SHIFT                                                                         0x0
++#define MP1_C2PMSG_99__CONTENT_MASK                                                                           0xFFFFFFFFL
++//MP1_C2PMSG_100
++#define MP1_C2PMSG_100__CONTENT__SHIFT                                                                        0x0
++#define MP1_C2PMSG_100__CONTENT_MASK                                                                          0xFFFFFFFFL
++//MP1_C2PMSG_101
++#define MP1_C2PMSG_101__CONTENT__SHIFT                                                                        0x0
++#define MP1_C2PMSG_101__CONTENT_MASK                                                                          0xFFFFFFFFL
++//MP1_C2PMSG_102
++#define MP1_C2PMSG_102__CONTENT__SHIFT                                                                        0x0
++#define MP1_C2PMSG_102__CONTENT_MASK                                                                          0xFFFFFFFFL
++//MP1_C2PMSG_103
++#define MP1_C2PMSG_103__CONTENT__SHIFT                                                                        0x0
++#define MP1_C2PMSG_103__CONTENT_MASK                                                                          0xFFFFFFFFL
++//MP1_IH_CREDIT
++#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                    0x0
++#define MP1_IH_CREDIT__CLIENT_ID__SHIFT                                                                       0x10
++#define MP1_IH_CREDIT__CREDIT_VALUE_MASK                                                                      0x00000003L
++#define MP1_IH_CREDIT__CLIENT_ID_MASK                                                                         0x00FF0000L
++//MP1_IH_SW_INT
++#define MP1_IH_SW_INT__ID__SHIFT                                                                              0x0
++#define MP1_IH_SW_INT__VALID__SHIFT                                                                           0x8
++#define MP1_IH_SW_INT__ID_MASK                                                                                0x000000FFL
++#define MP1_IH_SW_INT__VALID_MASK                                                                             0x00000100L
++//MP1_IH_SW_INT_CTRL
++#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                                   0x0
++#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                    0x8
++#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK                                                                     0x00000001L
++#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK                                                                      0x00000100L
++//MP1_FPS_CNT
++#define MP1_FPS_CNT__COUNT__SHIFT                                                                             0x0
++#define MP1_FPS_CNT__COUNT_MASK                                                                               0xFFFFFFFFL
++
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3370-drm-amdgpu-add-renoir-asic_type-enum.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3370-drm-amdgpu-add-renoir-asic_type-enum.patch
new file mode 100644
index 00000000..4bb24220
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3370-drm-amdgpu-add-renoir-asic_type-enum.patch
@@ -0,0 +1,43 @@
+From 060b8fd8752cfca2888c36b75869de60368d3a6b Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Wed, 24 Jul 2019 13:36:09 -0500
+Subject: [PATCH 3370/4256] drm/amdgpu: add renoir asic_type enum
+
+This patch adds renoir to amd_asic_type enum and amdgpu_asic_name[].
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
+ include/drm/amd_asic_type.h                | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index b4e950504a0e..b8906a00b9fc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -101,6 +101,7 @@ static const char *amdgpu_asic_name[] = {
+ 	"VEGA20",
+ 	"RAVEN",
+ 	"ARCTURUS",
++	"RENOIR",
+ 	"NAVI10",
+ 	"NAVI14",
+ 	"NAVI12",
+diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
+index 4fce10a2bbee..f4eda333c11c 100644
+--- a/include/drm/amd_asic_type.h
++++ b/include/drm/amd_asic_type.h
+@@ -50,6 +50,7 @@ enum amd_asic_type {
+ 	CHIP_VEGA20,
+ 	CHIP_RAVEN,
+ 	CHIP_ARCTURUS,
++	CHIP_RENOIR,
+ 	CHIP_PICASSO,
+ 	CHIP_NAVI10,
+ 	CHIP_NAVI14,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3371-drm-amdgpu-add-renoir-support-for-gpu_info-and-ip-bl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3371-drm-amdgpu-add-renoir-support-for-gpu_info-and-ip-bl.patch
new file mode 100644
index 00000000..20f47aee
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3371-drm-amdgpu-add-renoir-support-for-gpu_info-and-ip-bl.patch
@@ -0,0 +1,52 @@
+From 33465a70a40a9147c75898431723f36ee86ef8c9 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Wed, 24 Jul 2019 13:38:15 -0500
+Subject: [PATCH 3371/4256] drm/amdgpu: add renoir support for gpu_info and ip
+ block setting
+
+This patch adds renoir support for gpu_info firmware and ip block setting.
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index b8906a00b9fc..80904cb6bccc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -70,6 +70,7 @@ MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
+ MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
+ MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
+ MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
++MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
+ MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
+ MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
+ MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
+@@ -1428,6 +1429,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
+ 	case CHIP_ARCTURUS:
+ 		chip_name = "arcturus";
+ 		break;
++	case CHIP_RENOIR:
++		chip_name = "renoir";
++		break;
+ 	case CHIP_NAVI10:
+ 		chip_name = "navi10";
+ 		break;
+@@ -1580,7 +1584,9 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
+ 	case CHIP_VEGA20:
+ 	case CHIP_RAVEN:
+ 	case CHIP_ARCTURUS:
+-		if (adev->asic_type == CHIP_RAVEN)
++	case CHIP_RENOIR:
++		if (adev->asic_type == CHIP_RAVEN ||
++		    adev->asic_type == CHIP_RENOIR)
+ 			adev->family = AMDGPU_FAMILY_RV;
+ 		else
+ 			adev->family = AMDGPU_FAMILY_AI;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3372-drm-amdgpu-add-soc15-common-ip-block-support-for-ren.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3372-drm-amdgpu-add-soc15-common-ip-block-support-for-ren.patch
new file mode 100644
index 00000000..ca2cdf7e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3372-drm-amdgpu-add-soc15-common-ip-block-support-for-ren.patch
@@ -0,0 +1,43 @@
+From 19fff1e7ab62601e804a6271e5846be195b6269f Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Wed, 24 Jul 2019 13:39:36 -0500
+Subject: [PATCH 3372/4256] drm/amdgpu: add soc15 common ip block support for
+ renoir
+
+This patch adds common ip support for renoir.
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 235cb5b156b9..996adeb6a64a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -636,6 +636,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ 	case CHIP_VEGA10:
+ 	case CHIP_VEGA12:
+ 	case CHIP_RAVEN:
++	case CHIP_RENOIR:
+ 		vega10_reg_base_init(adev);
+ 		break;
+ 	case CHIP_VEGA20:
+@@ -1132,6 +1133,11 @@ static int soc15_common_early_init(void *handle)
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x32;
+ 		break;
++	case CHIP_RENOIR:
++		adev->cg_flags = 0;
++		adev->pg_flags = 0;
++		adev->external_rev_id = adev->rev_id + 0x91;
++		break;
+ 	default:
+ 		/* FIXME: not supported yet */
+ 		return -EINVAL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3373-drm-amdgpu-add-gmc-v9-supports-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3373-drm-amdgpu-add-gmc-v9-supports-for-renoir.patch
new file mode 100644
index 00000000..176d4ab6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3373-drm-amdgpu-add-gmc-v9-supports-for-renoir.patch
@@ -0,0 +1,73 @@
+From 35fedcbcf12b52ee3181b6f9d9eb1f258db9b1c0 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Wed, 24 Jul 2019 13:42:16 -0500
+Subject: [PATCH 3373/4256] drm/amdgpu: add gmc v9 supports for renoir
+
+Add gfx memory controller support for renoir.
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 37c0d085d5c9..e42c2a4dadac 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -696,6 +696,7 @@ static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
+ 	case CHIP_VEGA10:
+ 	case CHIP_RAVEN:
+ 	case CHIP_ARCTURUS:
++	case CHIP_RENOIR:
+ 		return true;
+ 	case CHIP_VEGA12:
+ 	case CHIP_VEGA20:
+@@ -1002,6 +1003,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
+ 			adev->gmc.gart_size = 512ULL << 20;
+ 			break;
+ 		case CHIP_RAVEN:   /* DCE SG support */
++		case CHIP_RENOIR:
+ 			adev->gmc.gart_size = 1024ULL << 20;
+ 			break;
+ 		}
+@@ -1052,6 +1054,7 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
+ 
+ 		switch (adev->asic_type) {
+ 		case CHIP_RAVEN:
++		case CHIP_RENOIR:
+ 			viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
+ 			size = (REG_GET_FIELD(viewport,
+ 					      HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
+@@ -1108,8 +1111,10 @@ static int gmc_v9_0_sw_init(void *handle)
+ 	case CHIP_VEGA10:
+ 	case CHIP_VEGA12:
+ 	case CHIP_VEGA20:
++	case CHIP_RENOIR:
+ 		adev->num_vmhubs = 2;
+ 
++
+ 		/*
+ 		 * To fulfill 4-level page support,
+ 		 * vm size is 256TB (48bit), maximum size of Vega10,
+@@ -1281,6 +1286,7 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
+ 	case CHIP_VEGA12:
+ 		break;
+ 	case CHIP_RAVEN:
++		/* TODO for renoir */
+ 		soc15_program_register_sequence(adev,
+ 						golden_settings_athub_1_0_0,
+ 						ARRAY_SIZE(golden_settings_athub_1_0_0));
+@@ -1315,6 +1321,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_RAVEN:
++		/* TODO for renoir */
+ 		mmhub_v1_0_update_power_gating(adev, true);
+ 		break;
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3374-drm-amdgpu-set-fw-load-type-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3374-drm-amdgpu-set-fw-load-type-for-renoir.patch
new file mode 100644
index 00000000..ad699d87
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3374-drm-amdgpu-set-fw-load-type-for-renoir.patch
@@ -0,0 +1,31 @@
+From 17f648a26fa401f86cca0311dc01076341c88e50 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Wed, 24 Jul 2019 13:43:16 -0500
+Subject: [PATCH 3374/4256] drm/amdgpu: set fw load type for renoir
+
+This patch sets fw load type as direct for renoir for the moment.
+Will switch to psp when psp is ready.
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+index 6185ba0730a8..f6bce50e2b09 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+@@ -368,6 +368,7 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
+ 		else
+ 			return AMDGPU_FW_LOAD_PSP;
+ 	case CHIP_ARCTURUS:
++	case CHIP_RENOIR:
+ 		return AMDGPU_FW_LOAD_DIRECT;
+ 	default:
+ 		DRM_ERROR("Unknown firmware load type\n");
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3375-drm-amdgpu-add-gfx-support-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3375-drm-amdgpu-add-gfx-support-for-renoir.patch
new file mode 100644
index 00000000..300c1608
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3375-drm-amdgpu-add-gfx-support-for-renoir.patch
@@ -0,0 +1,97 @@
+From f13a0b925eaf40f594932f1f5b3424bf178bf150 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Wed, 24 Jul 2019 13:47:52 -0500
+Subject: [PATCH 3375/4256] drm/amdgpu: add gfx support for renoir
+
+Add Renoir checks to gfx9 code.
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 26 ++++++++++++++++++++++++--
+ 1 file changed, 24 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 5188a5ea5ffc..180df6f44073 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -104,6 +104,13 @@ MODULE_FIRMWARE("amdgpu/arcturus_mec.bin");
+ MODULE_FIRMWARE("amdgpu/arcturus_mec2.bin");
+ MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin");
+ 
++MODULE_FIRMWARE("amdgpu/renoir_ce.bin");
++MODULE_FIRMWARE("amdgpu/renoir_pfp.bin");
++MODULE_FIRMWARE("amdgpu/renoir_me.bin");
++MODULE_FIRMWARE("amdgpu/renoir_mec.bin");
++MODULE_FIRMWARE("amdgpu/renoir_mec2.bin");
++MODULE_FIRMWARE("amdgpu/renoir_rlc.bin");
++
+ #define mmTCP_CHAN_STEER_0_ARCT								0x0b03
+ #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX							0
+ #define mmTCP_CHAN_STEER_1_ARCT								0x0b04
+@@ -1339,6 +1346,9 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
+ 	case CHIP_ARCTURUS:
+ 		chip_name = "arcturus";
+ 		break;
++	case CHIP_RENOIR:
++		chip_name = "renoir";
++		break;
+ 	default:
+ 		BUG();
+ 	}
+@@ -1598,7 +1608,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
+ 			return r;
+ 	}
+ 
+-	if (adev->asic_type == CHIP_RAVEN) {
++	if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) {
+ 		/* TODO: double check the cp_table_size for RV */
+ 		adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
+ 		r = amdgpu_gfx_rlc_init_cpt(adev);
+@@ -1859,6 +1869,16 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
+ 		gb_addr_config &= ~0xf3e777ff;
+ 		gb_addr_config |= 0x22014042;
+ 		break;
++	case CHIP_RENOIR:
++		adev->gfx.config.max_hw_contexts = 8;
++		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
++		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
++		adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;
++		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
++		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
++		gb_addr_config &= ~0xf3e777ff;
++		gb_addr_config |= 0x22010042;
++		break;
+ 	default:
+ 		BUG();
+ 		break;
+@@ -2136,6 +2156,7 @@ static int gfx_v9_0_sw_init(void *handle)
+ 	case CHIP_VEGA20:
+ 	case CHIP_RAVEN:
+ 	case CHIP_ARCTURUS:
++	case CHIP_RENOIR:
+ 		adev->gfx.mec.num_mec = 2;
+ 		break;
+ 	default:
+@@ -2293,7 +2314,7 @@ static int gfx_v9_0_sw_fini(void *handle)
+ 	gfx_v9_0_mec_fini(adev);
+ 	gfx_v9_0_ngg_fini(adev);
+ 	amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
+-	if (adev->asic_type == CHIP_RAVEN) {
++	if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) {
+ 		amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
+ 				&adev->gfx.rlc.cp_table_gpu_addr,
+ 				(void **)&adev->gfx.rlc.cp_table_ptr);
+@@ -2974,6 +2995,7 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_RAVEN:
++	case CHIP_RENOIR:
+ 		if (amdgpu_lbpw == 0)
+ 			gfx_v9_0_enable_lbpw(adev, false);
+ 		else
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3376-drm-amdgpu-add-sdma-support-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3376-drm-amdgpu-add-sdma-support-for-renoir.patch
new file mode 100644
index 00000000..40f95b1f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3376-drm-amdgpu-add-sdma-support-for-renoir.patch
@@ -0,0 +1,49 @@
+From a12b48c774b601a746b6fba6267adc226a243963 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Thu, 8 Aug 2019 14:58:51 -0500
+Subject: [PATCH 3376/4256] drm/amdgpu: add sdma support for renoir
+
+Add renoir checks to appropriate places.
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 08774110bcbb..0c137b476572 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -65,6 +65,7 @@ MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
+ MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
+ MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
+ MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin");
++MODULE_FIRMWARE("amdgpu/renoir_sdma.bin");
+ 
+ #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
+ #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
+@@ -449,6 +450,9 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
+ 	case CHIP_ARCTURUS:
+ 		chip_name = "arcturus";
+ 		break;
++	case CHIP_RENOIR:
++		chip_name = "renoir";
++		break;
+ 	default:
+ 		BUG();
+ 	}
+@@ -1639,7 +1643,7 @@ static int sdma_v4_0_early_init(void *handle)
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 	int r;
+ 
+-	if (adev->asic_type == CHIP_RAVEN)
++	if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR)
+ 		adev->sdma.num_instances = 1;
+ 	else if (adev->asic_type == CHIP_ARCTURUS)
+ 		adev->sdma.num_instances = 8;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3377-drm-amdgpu-set-ip-blocks-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3377-drm-amdgpu-set-ip-blocks-for-renoir.patch
new file mode 100644
index 00000000..e63e00c7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3377-drm-amdgpu-set-ip-blocks-for-renoir.patch
@@ -0,0 +1,36 @@
+From e89049ff929dd2930079adaa372445034b56ba5d Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Wed, 24 Jul 2019 13:50:22 -0500
+Subject: [PATCH 3377/4256] drm/amdgpu: set ip blocks for renoir
+
+Enable ip blocks for renoir.
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 996adeb6a64a..1b0149e83b8b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -743,6 +743,13 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ 		amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
+ 		break;
++	case CHIP_RENOIR:
++		amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
++		amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
++		amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
++		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
++		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
++		break;
+ 	default:
+ 		return -EINVAL;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3378-drm-amdgpu-add-renoir-pci-id.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3378-drm-amdgpu-add-renoir-pci-id.patch
new file mode 100644
index 00000000..fc274b82
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3378-drm-amdgpu-add-renoir-pci-id.patch
@@ -0,0 +1,32 @@
+From 2585e15ec9909346383dd134a9535dc70a84e86b Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Tue, 30 Oct 2018 11:43:02 +0800
+Subject: [PATCH 3378/4256] drm/amdgpu: add renoir pci id
+
+Add Renoir PCI id support.
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 43b059d8f58d..73d5ede4329d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1048,6 +1048,9 @@ static const struct pci_device_id pciidlist[] = {
+ 	/* Navi14 */
+ 	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
+ 
++	/* Renoir */
++	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
++
+ 	{0, 0, 0}
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3379-drm-amdgpu-fix-no-interrupt-issue-for-renoir-emu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3379-drm-amdgpu-fix-no-interrupt-issue-for-renoir-emu.patch
new file mode 100644
index 00000000..2be910c2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3379-drm-amdgpu-fix-no-interrupt-issue-for-renoir-emu.patch
@@ -0,0 +1,35 @@
+From 29c18072e8ae9c152743b7f8e4184fe1e7298a48 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Wed, 24 Jul 2019 13:53:17 -0500
+Subject: [PATCH 3379/4256] drm/amdgpu: fix no interrupt issue for renoir emu
+
+In renoir's ih model, there's a change in mmIH_CHICKEN
+register, that limits IH to use physical address directly.
+Those chicken bits need to be programmed first.
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+index a55525abb73c..f19268aea38d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
++++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+@@ -245,7 +245,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
+ 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
+ 	}
+ 
+-	if (adev->asic_type == CHIP_ARCTURUS &&
++	if ((adev->asic_type == CHIP_ARCTURUS || adev->asic_type == CHIP_RENOIR) &&
+ 		adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
+ 		if (adev->irq.ih.use_bus_addr) {
+ 			ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3380-drm-amdgpu-enable-dce-virtual-ip-module-for-Renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3380-drm-amdgpu-enable-dce-virtual-ip-module-for-Renoir.patch
new file mode 100644
index 00000000..61ba0957
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3380-drm-amdgpu-enable-dce-virtual-ip-module-for-Renoir.patch
@@ -0,0 +1,42 @@
+From d64e7ee0dd1c4f8dfd7692c5d197fbf28733f2c6 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Wed, 24 Jul 2019 13:55:38 -0500
+Subject: [PATCH 3380/4256] drm/amdgpu: enable dce virtual ip module for Renoir
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 1 +
+ drivers/gpu/drm/amd/amdgpu/soc15.c       | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+index c81d7a2067ad..6dadbed7ce43 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+@@ -456,6 +456,7 @@ static int dce_virtual_hw_init(void *handle)
+ 	case CHIP_VEGA12:
+ 	case CHIP_VEGA20:
+ 	case CHIP_ARCTURUS:
++	case CHIP_RENOIR:
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+ 	case CHIP_NAVI12:
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 1b0149e83b8b..bac728e21714 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -749,6 +749,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ 		amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
++		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
++			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+ 		break;
+ 	default:
+ 		return -EINVAL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3381-drm-amdgpu-add-asic-funcs-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3381-drm-amdgpu-add-asic-funcs-for-renoir.patch
new file mode 100644
index 00000000..d03c7c0f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3381-drm-amdgpu-add-asic-funcs-for-renoir.patch
@@ -0,0 +1,31 @@
+From baeddb7419f026d43ac7bfe2069ce3f6ab3d5873 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Mon, 8 Apr 2019 13:14:28 +0800
+Subject: [PATCH 3381/4256] drm/amdgpu: add asic funcs for renoir
+
+add asic funcs for renoir, init soc15_asic_funcs
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index bac728e21714..69c18c26f77c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1143,6 +1143,7 @@ static int soc15_common_early_init(void *handle)
+ 		adev->external_rev_id = adev->rev_id + 0x32;
+ 		break;
+ 	case CHIP_RENOIR:
++		adev->asic_funcs = &soc15_asic_funcs;
+ 		adev->cg_flags = 0;
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x91;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3382-drm-amdgpu-set-rlc-funcs-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3382-drm-amdgpu-set-rlc-funcs-for-renoir.patch
new file mode 100644
index 00000000..51edd4d9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3382-drm-amdgpu-set-rlc-funcs-for-renoir.patch
@@ -0,0 +1,31 @@
+From 7ee1ad4c3197fecb008c84c7f77043a8e77938ef Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Wed, 24 Jul 2019 13:56:27 -0500
+Subject: [PATCH 3382/4256] drm/amdgpu: set rlc funcs for renoir
+
+add gfx_v9_0_rlc_funcs for renoir
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 180df6f44073..1df9866d8f24 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -6316,6 +6316,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
+ 	case CHIP_VEGA20:
+ 	case CHIP_RAVEN:
+ 	case CHIP_ARCTURUS:
++	case CHIP_RENOIR:
+ 		adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
+ 		break;
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3383-drm-amdgpu-add-psp_v12_0-for-renoir-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3383-drm-amdgpu-add-psp_v12_0-for-renoir-v2.patch
new file mode 100644
index 00000000..be56a768
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3383-drm-amdgpu-add-psp_v12_0-for-renoir-v2.patch
@@ -0,0 +1,731 @@
+From 3f08259629ef01db90deec044f18c30217a0acfd Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Fri, 9 Aug 2019 10:32:15 -0500
+Subject: [PATCH 3383/4256] drm/amdgpu: add psp_v12_0 for renoir (v2)
+
+1. Add psp ip block
+2. Use direct loading type by default and it can also config psp
+   loading type.
+3. Bypass sos fw loading and xgmi&ras interface
+
+v2: drop TA loading
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile       |   3 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c   |  13 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h   |   1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c |   7 +-
+ drivers/gpu/drm/amd/amdgpu/psp_v12_0.c    | 565 ++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/psp_v12_0.h    |  30 ++
+ drivers/gpu/drm/amd/amdgpu/soc15.c        |   2 +
+ 7 files changed, 619 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v12_0.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index c82efd378f1d..1b74396c6187 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -100,7 +100,8 @@ amdgpu-y += \
+ 	amdgpu_psp.o \
+ 	psp_v3_1.o \
+ 	psp_v10_0.o \
+-	psp_v11_0.o
++	psp_v11_0.o \
++	psp_v12_0.o
+ 
+ # add SMC block
+ amdgpu-y += \
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index c83642e9ed34..fbb245908bcb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -32,6 +32,7 @@
+ #include "psp_v3_1.h"
+ #include "psp_v10_0.h"
+ #include "psp_v11_0.h"
++#include "psp_v12_0.h"
+ 
+ static void psp_set_funcs(struct amdgpu_device *adev);
+ 
+@@ -64,6 +65,9 @@ static int psp_early_init(void *handle)
+ 		psp_v11_0_set_psp_funcs(psp);
+ 		psp->autoload_supported = true;
+ 		break;
++	case CHIP_RENOIR:
++		psp_v12_0_set_psp_funcs(psp);
++		break;
+ 	default:
+ 		return -EINVAL;
+ 	}
+@@ -1361,3 +1365,12 @@ const struct amdgpu_ip_block_version psp_v11_0_ip_block =
+ 	.rev = 0,
+ 	.funcs = &psp_ip_funcs,
+ };
++
++const struct amdgpu_ip_block_version psp_v12_0_ip_block =
++{
++	.type = AMD_IP_BLOCK_TYPE_PSP,
++	.major = 12,
++	.minor = 0,
++	.rev = 0,
++	.funcs = &psp_ip_funcs,
++};
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+index e0fc2a790e53..0029fa2b2ff9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+@@ -270,6 +270,7 @@ extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
+ 			uint32_t field_val, uint32_t mask, bool check_changed);
+ 
+ extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
++extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
+ 
+ int psp_gpu_reset(struct amdgpu_device *adev);
+ int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+index f6bce50e2b09..ee6a9bee8f08 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+@@ -368,8 +368,13 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
+ 		else
+ 			return AMDGPU_FW_LOAD_PSP;
+ 	case CHIP_ARCTURUS:
+-	case CHIP_RENOIR:
+ 		return AMDGPU_FW_LOAD_DIRECT;
++	case CHIP_RENOIR:
++		if (load_type == AMDGPU_FW_LOAD_PSP)
++			return AMDGPU_FW_LOAD_PSP;
++		else
++			return AMDGPU_FW_LOAD_DIRECT;
++
+ 	default:
+ 		DRM_ERROR("Unknown firmware load type\n");
+ 	}
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+new file mode 100644
+index 000000000000..f37b8af4b986
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+@@ -0,0 +1,565 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include <linux/firmware.h>
++#include "amdgpu.h"
++#include "amdgpu_psp.h"
++#include "amdgpu_ucode.h"
++#include "soc15_common.h"
++#include "psp_v12_0.h"
++
++#include "mp/mp_12_0_0_offset.h"
++#include "mp/mp_12_0_0_sh_mask.h"
++#include "gc/gc_9_0_offset.h"
++#include "sdma0/sdma0_4_0_offset.h"
++#include "nbio/nbio_7_4_offset.h"
++
++#include "oss/osssys_4_0_offset.h"
++#include "oss/osssys_4_0_sh_mask.h"
++
++MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
++/* address block */
++#define smnMP1_FIRMWARE_FLAGS		0x3010024
++
++static int psp_v12_0_init_microcode(struct psp_context *psp)
++{
++	struct amdgpu_device *adev = psp->adev;
++	const char *chip_name;
++	char fw_name[30];
++	int err = 0;
++	const struct psp_firmware_header_v1_0 *asd_hdr;
++
++	DRM_DEBUG("\n");
++
++	switch (adev->asic_type) {
++	case CHIP_RENOIR:
++		chip_name = "renoir";
++		break;
++	default:
++		BUG();
++	}
++
++	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
++	err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
++	if (err)
++		goto out1;
++
++	err = amdgpu_ucode_validate(adev->psp.asd_fw);
++	if (err)
++		goto out1;
++
++	asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
++	adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
++	adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
++	adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
++	adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
++				le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
++
++	return 0;
++
++out1:
++	release_firmware(adev->psp.asd_fw);
++	adev->psp.asd_fw = NULL;
++
++	return err;
++}
++
++static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
++{
++	int ret;
++	uint32_t psp_gfxdrv_command_reg = 0;
++	struct amdgpu_device *adev = psp->adev;
++	uint32_t sol_reg;
++
++	/* Check sOS sign of life register to confirm sys driver and sOS
++	 * are already been loaded.
++	 */
++	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
++	if (sol_reg) {
++		psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
++		printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
++		return 0;
++	}
++
++	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
++	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
++			   0x80000000, 0x80000000, false);
++	if (ret)
++		return ret;
++
++	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
++
++	/* Copy PSP System Driver binary to memory */
++	memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
++
++	/* Provide the sys driver to bootloader */
++	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
++	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
++	psp_gfxdrv_command_reg = 1 << 16;
++	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
++	       psp_gfxdrv_command_reg);
++
++	/* there might be handshake issue with hardware which needs delay */
++	mdelay(20);
++
++	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
++			   0x80000000, 0x80000000, false);
++
++	return ret;
++}
++
++static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
++{
++	int ret;
++	unsigned int psp_gfxdrv_command_reg = 0;
++	struct amdgpu_device *adev = psp->adev;
++	uint32_t sol_reg;
++
++	/* Check sOS sign of life register to confirm sys driver and sOS
++	 * are already been loaded.
++	 */
++	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
++	if (sol_reg)
++		return 0;
++
++	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
++	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
++			   0x80000000, 0x80000000, false);
++	if (ret)
++		return ret;
++
++	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
++
++	/* Copy Secure OS binary to PSP memory */
++	memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
++
++	/* Provide the PSP secure OS to bootloader */
++	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
++	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
++	psp_gfxdrv_command_reg = 2 << 16;
++	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
++	       psp_gfxdrv_command_reg);
++
++	/* there might be handshake issue with hardware which needs delay */
++	mdelay(20);
++	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
++			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
++			   0, true);
++
++	return ret;
++}
++
++static void psp_v12_0_reroute_ih(struct psp_context *psp)
++{
++	struct amdgpu_device *adev = psp->adev;
++	uint32_t tmp;
++
++	/* Change IH ring for VMC */
++	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
++	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
++	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
++
++	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
++	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
++	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
++
++	mdelay(20);
++	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
++		     0x80000000, 0x8000FFFF, false);
++
++	/* Change IH ring for UMC */
++	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
++	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
++
++	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
++	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
++	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
++
++	mdelay(20);
++	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
++		     0x80000000, 0x8000FFFF, false);
++}
++
++static int psp_v12_0_ring_init(struct psp_context *psp,
++			      enum psp_ring_type ring_type)
++{
++	int ret = 0;
++	struct psp_ring *ring;
++	struct amdgpu_device *adev = psp->adev;
++
++	psp_v12_0_reroute_ih(psp);
++
++	ring = &psp->km_ring;
++
++	ring->ring_type = ring_type;
++
++	/* allocate 4k Page of Local Frame Buffer memory for ring */
++	ring->ring_size = 0x1000;
++	ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
++				      AMDGPU_GEM_DOMAIN_VRAM,
++				      &adev->firmware.rbuf,
++				      &ring->ring_mem_mc_addr,
++				      (void **)&ring->ring_mem);
++	if (ret) {
++		ring->ring_size = 0;
++		return ret;
++	}
++
++	return 0;
++}
++
++static bool psp_v12_0_support_vmr_ring(struct psp_context *psp)
++{
++	if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
++		return true;
++	return false;
++}
++
++static int psp_v12_0_ring_create(struct psp_context *psp,
++				enum psp_ring_type ring_type)
++{
++	int ret = 0;
++	unsigned int psp_ring_reg = 0;
++	struct psp_ring *ring = &psp->km_ring;
++	struct amdgpu_device *adev = psp->adev;
++
++	if (psp_v12_0_support_vmr_ring(psp)) {
++		/* Write low address of the ring to C2PMSG_102 */
++		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
++		/* Write high address of the ring to C2PMSG_103 */
++		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
++
++		/* Write the ring initialization command to C2PMSG_101 */
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
++					     GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
++
++		/* there might be handshake issue with hardware which needs delay */
++		mdelay(20);
++
++		/* Wait for response flag (bit 31) in C2PMSG_101 */
++		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
++				   0x80000000, 0x8000FFFF, false);
++
++	} else {
++		/* Write low address of the ring to C2PMSG_69 */
++		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
++		/* Write high address of the ring to C2PMSG_70 */
++		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
++		/* Write size of ring to C2PMSG_71 */
++		psp_ring_reg = ring->ring_size;
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
++		/* Write the ring initialization command to C2PMSG_64 */
++		psp_ring_reg = ring_type;
++		psp_ring_reg = psp_ring_reg << 16;
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
++
++		/* there might be handshake issue with hardware which needs delay */
++		mdelay(20);
++
++		/* Wait for response flag (bit 31) in C2PMSG_64 */
++		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
++				   0x80000000, 0x8000FFFF, false);
++	}
++
++	return ret;
++}
++
++static int psp_v12_0_ring_stop(struct psp_context *psp,
++			      enum psp_ring_type ring_type)
++{
++	int ret = 0;
++	struct amdgpu_device *adev = psp->adev;
++
++	/* Write the ring destroy command*/
++	if (psp_v12_0_support_vmr_ring(psp))
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
++				     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
++	else
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
++				     GFX_CTRL_CMD_ID_DESTROY_RINGS);
++
++	/* there might be handshake issue with hardware which needs delay */
++	mdelay(20);
++
++	/* Wait for response flag (bit 31) */
++	if (psp_v12_0_support_vmr_ring(psp))
++		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
++				   0x80000000, 0x80000000, false);
++	else
++		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
++				   0x80000000, 0x80000000, false);
++
++	return ret;
++}
++
++static int psp_v12_0_ring_destroy(struct psp_context *psp,
++				 enum psp_ring_type ring_type)
++{
++	int ret = 0;
++	struct psp_ring *ring = &psp->km_ring;
++	struct amdgpu_device *adev = psp->adev;
++
++	ret = psp_v12_0_ring_stop(psp, ring_type);
++	if (ret)
++		DRM_ERROR("Fail to stop psp ring\n");
++
++	amdgpu_bo_free_kernel(&adev->firmware.rbuf,
++			      &ring->ring_mem_mc_addr,
++			      (void **)&ring->ring_mem);
++
++	return ret;
++}
++
++static int psp_v12_0_cmd_submit(struct psp_context *psp,
++			       struct amdgpu_firmware_info *ucode,
++			       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
++			       int index)
++{
++	unsigned int psp_write_ptr_reg = 0;
++	struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
++	struct psp_ring *ring = &psp->km_ring;
++	struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
++	struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
++		ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
++	struct amdgpu_device *adev = psp->adev;
++	uint32_t ring_size_dw = ring->ring_size / 4;
++	uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
++
++	/* KM (GPCOM) prepare write pointer */
++	if (psp_v12_0_support_vmr_ring(psp))
++		psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
++	else
++		psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
++
++	/* Update KM RB frame pointer to new frame */
++	/* write_frame ptr increments by size of rb_frame in bytes */
++	/* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
++	if ((psp_write_ptr_reg % ring_size_dw) == 0)
++		write_frame = ring_buffer_start;
++	else
++		write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
++	/* Check invalid write_frame ptr address */
++	if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
++		DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
++			  ring_buffer_start, ring_buffer_end, write_frame);
++		DRM_ERROR("write_frame is pointing to address out of bounds\n");
++		return -EINVAL;
++	}
++
++	/* Initialize KM RB frame */
++	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
++
++	/* Update KM RB frame */
++	write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
++	write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
++	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
++	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
++	write_frame->fence_value = index;
++
++	/* Update the write Pointer in DWORDs */
++	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
++	if (psp_v12_0_support_vmr_ring(psp)) {
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
++	} else
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
++
++	return 0;
++}
++
++static int
++psp_v12_0_sram_map(struct amdgpu_device *adev,
++		  unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
++		  unsigned int *sram_data_reg_offset,
++		  enum AMDGPU_UCODE_ID ucode_id)
++{
++	int ret = 0;
++
++	switch (ucode_id) {
++/* TODO: needs to confirm */
++#if 0
++	case AMDGPU_UCODE_ID_SMC:
++		*sram_offset = 0;
++		*sram_addr_reg_offset = 0;
++		*sram_data_reg_offset = 0;
++		break;
++#endif
++
++	case AMDGPU_UCODE_ID_CP_CE:
++		*sram_offset = 0x0;
++		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
++		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
++		break;
++
++	case AMDGPU_UCODE_ID_CP_PFP:
++		*sram_offset = 0x0;
++		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
++		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
++		break;
++
++	case AMDGPU_UCODE_ID_CP_ME:
++		*sram_offset = 0x0;
++		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
++		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
++		break;
++
++	case AMDGPU_UCODE_ID_CP_MEC1:
++		*sram_offset = 0x10000;
++		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
++		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
++		break;
++
++	case AMDGPU_UCODE_ID_CP_MEC2:
++		*sram_offset = 0x10000;
++		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
++		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
++		break;
++
++	case AMDGPU_UCODE_ID_RLC_G:
++		*sram_offset = 0x2000;
++		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
++		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
++		break;
++
++	case AMDGPU_UCODE_ID_SDMA0:
++		*sram_offset = 0x0;
++		*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
++		*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
++		break;
++
++/* TODO: needs to confirm */
++#if 0
++	case AMDGPU_UCODE_ID_SDMA1:
++		*sram_offset = ;
++		*sram_addr_reg_offset = ;
++		break;
++
++	case AMDGPU_UCODE_ID_UVD:
++		*sram_offset = ;
++		*sram_addr_reg_offset = ;
++		break;
++
++	case AMDGPU_UCODE_ID_VCE:
++		*sram_offset = ;
++		*sram_addr_reg_offset = ;
++		break;
++#endif
++
++	case AMDGPU_UCODE_ID_MAXIMUM:
++	default:
++		ret = -EINVAL;
++		break;
++	}
++
++	return ret;
++}
++
++static bool psp_v12_0_compare_sram_data(struct psp_context *psp,
++				       struct amdgpu_firmware_info *ucode,
++				       enum AMDGPU_UCODE_ID ucode_type)
++{
++	int err = 0;
++	unsigned int fw_sram_reg_val = 0;
++	unsigned int fw_sram_addr_reg_offset = 0;
++	unsigned int fw_sram_data_reg_offset = 0;
++	unsigned int ucode_size;
++	uint32_t *ucode_mem = NULL;
++	struct amdgpu_device *adev = psp->adev;
++
++	err = psp_v12_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
++				&fw_sram_data_reg_offset, ucode_type);
++	if (err)
++		return false;
++
++	WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
++
++	ucode_size = ucode->ucode_size;
++	ucode_mem = (uint32_t *)ucode->kaddr;
++	while (ucode_size) {
++		fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
++
++		if (*ucode_mem != fw_sram_reg_val)
++			return false;
++
++		ucode_mem++;
++		/* 4 bytes */
++		ucode_size -= 4;
++	}
++
++	return true;
++}
++
++static int psp_v12_0_mode1_reset(struct psp_context *psp)
++{
++	int ret;
++	uint32_t offset;
++	struct amdgpu_device *adev = psp->adev;
++
++	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
++
++	ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
++
++	if (ret) {
++		DRM_INFO("psp is not working correctly before mode1 reset!\n");
++		return -EINVAL;
++	}
++
++	/*send the mode 1 reset command*/
++	WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
++
++	msleep(500);
++
++	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
++
++	ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
++
++	if (ret) {
++		DRM_INFO("psp mode 1 reset failed!\n");
++		return -EINVAL;
++	}
++
++	DRM_INFO("psp mode1 reset succeed \n");
++
++	return 0;
++}
++
++static const struct psp_funcs psp_v12_0_funcs = {
++	.init_microcode = psp_v12_0_init_microcode,
++	.bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
++	.bootloader_load_sos = psp_v12_0_bootloader_load_sos,
++	.ring_init = psp_v12_0_ring_init,
++	.ring_create = psp_v12_0_ring_create,
++	.ring_stop = psp_v12_0_ring_stop,
++	.ring_destroy = psp_v12_0_ring_destroy,
++	.cmd_submit = psp_v12_0_cmd_submit,
++	.compare_sram_data = psp_v12_0_compare_sram_data,
++	.mode1_reset = psp_v12_0_mode1_reset,
++};
++
++void psp_v12_0_set_psp_funcs(struct psp_context *psp)
++{
++	psp->funcs = &psp_v12_0_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.h b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.h
+new file mode 100644
+index 000000000000..241693ab1990
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.h
+@@ -0,0 +1,30 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __PSP_V12_0_H__
++#define __PSP_V12_0_H__
++
++#include "amdgpu_psp.h"
++
++void psp_v12_0_set_psp_funcs(struct psp_context *psp);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 69c18c26f77c..1aacf95998b9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -747,6 +747,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ 		amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
++		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
++			amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
+ 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3384-drm-amdgpu-add-gfx-golden-settings-for-renoir-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3384-drm-amdgpu-add-gfx-golden-settings-for-renoir-v2.patch
new file mode 100644
index 00000000..3f19e443
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3384-drm-amdgpu-add-gfx-golden-settings-for-renoir-v2.patch
@@ -0,0 +1,78 @@
+From dd6744508a516e47bf3b293f16698cecab66c064 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Sun, 23 Jun 2019 02:51:57 +0800
+Subject: [PATCH 3384/4256] drm/amdgpu: add gfx golden settings for renoir (v2)
+
+This patch adds gfx golden settings for renoir real asic.
+
+v2: update settings (Alex)
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 1df9866d8f24..75ea77cc457f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -32,6 +32,7 @@
+ 
+ #include "gc/gc_9_0_offset.h"
+ #include "gc/gc_9_0_sh_mask.h"
++
+ #include "vega10_enum.h"
+ #include "hdp/hdp_4_0_offset.h"
+ 
+@@ -56,6 +57,9 @@
+ #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK		0x00000001L
+ #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK		0x00000006L
+ 
++#define mmGCEA_PROBE_MAP                        0x070c
++#define mmGCEA_PROBE_MAP_BASE_IDX               0
++
+ MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
+ MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
+ MODULE_FIRMWARE("amdgpu/vega10_me.bin");
+@@ -614,6 +618,23 @@ static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] =
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
+ };
+ 
++static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] =
++{
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22010042),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22010042),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc),
++};
++
+ static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
+ {
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff),
+@@ -758,6 +779,11 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
+ 							golden_settings_gc_9_1_rv1,
+ 							ARRAY_SIZE(golden_settings_gc_9_1_rv1));
+ 		break;
++	 case CHIP_RENOIR:
++		soc15_program_register_sequence(adev,
++						golden_settings_gc_9_1_rn,
++						ARRAY_SIZE(golden_settings_gc_9_1_rn));
++		break;
+ 	default:
+ 		break;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3385-drm-amdgpu-add-sdma-golden-settings-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3385-drm-amdgpu-add-sdma-golden-settings-for-renoir.patch
new file mode 100644
index 00000000..b02c3dac
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3385-drm-amdgpu-add-sdma-golden-settings-for-renoir.patch
@@ -0,0 +1,52 @@
+From e2aba1159059e62730fb7141ae859fc9a2d31bba Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Wed, 24 Jul 2019 14:03:25 -0500
+Subject: [PATCH 3385/4256] drm/amdgpu: add sdma golden settings for renoir
+
+This patch adds sdma golden settings for renoir asic.
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 0c137b476572..e336dae8be33 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -241,6 +241,18 @@ static const struct soc15_reg_golden golden_settings_sdma_arct[] =
+ 	SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002)
+ };
+ 
++static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
++	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
++	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
++	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003002),
++	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003002),
++	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
++	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
++	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
++	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
++	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
++};
++
+ static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
+ 		u32 instance, u32 offset)
+ {
+@@ -365,6 +377,11 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
+ 							golden_settings_sdma_rv1,
+ 							ARRAY_SIZE(golden_settings_sdma_rv1));
+ 		break;
++	case CHIP_RENOIR:
++		soc15_program_register_sequence(adev,
++						golden_settings_sdma_4_3,
++						ARRAY_SIZE(golden_settings_sdma_4_3));
++		break;
+ 	default:
+ 		break;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3386-drm-amdgpu-enable-Renoir-VCN-firmware-loading.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3386-drm-amdgpu-enable-Renoir-VCN-firmware-loading.patch
new file mode 100644
index 00000000..7ec8d018
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3386-drm-amdgpu-enable-Renoir-VCN-firmware-loading.patch
@@ -0,0 +1,51 @@
+From 5696089579835c373ca6b0df11f5b1fe3fd0f2f9 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Mon, 15 Jul 2019 09:01:51 -0400
+Subject: [PATCH 3386/4256] drm/amdgpu: enable Renoir VCN firmware loading
+
+By adding new Renoir VCN firmware
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+index b74f0f679aca..8566a264961f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+@@ -46,6 +46,7 @@
+ #define FIRMWARE_PICASSO	"amdgpu/picasso_vcn.bin"
+ #define FIRMWARE_RAVEN2		"amdgpu/raven2_vcn.bin"
+ #define FIRMWARE_ARCTURUS 	"amdgpu/arcturus_vcn.bin"
++#define FIRMWARE_RENOIR 	"amdgpu/renoir_vcn.bin"
+ #define FIRMWARE_NAVI10 	"amdgpu/navi10_vcn.bin"
+ #define FIRMWARE_NAVI14 	"amdgpu/navi14_vcn.bin"
+ #define FIRMWARE_NAVI12 	"amdgpu/navi12_vcn.bin"
+@@ -54,6 +55,7 @@ MODULE_FIRMWARE(FIRMWARE_RAVEN);
+ MODULE_FIRMWARE(FIRMWARE_PICASSO);
+ MODULE_FIRMWARE(FIRMWARE_RAVEN2);
+ MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
++MODULE_FIRMWARE(FIRMWARE_RENOIR);
+ MODULE_FIRMWARE(FIRMWARE_NAVI10);
+ MODULE_FIRMWARE(FIRMWARE_NAVI14);
+ MODULE_FIRMWARE(FIRMWARE_NAVI12);
+@@ -82,6 +84,12 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
+ 	case CHIP_ARCTURUS:
+ 		fw_name = FIRMWARE_ARCTURUS;
+ 		break;
++	case CHIP_RENOIR:
++		fw_name = FIRMWARE_RENOIR;
++		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
++		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
++			adev->vcn.indirect_sram = true;
++		break;
+ 	case CHIP_NAVI10:
+ 		fw_name = FIRMWARE_NAVI10;
+ 		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3387-drm-amdgpu-enable-Doorbell-support-for-Renoir-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3387-drm-amdgpu-enable-Doorbell-support-for-Renoir-v2.patch
new file mode 100644
index 00000000..df12ed0c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3387-drm-amdgpu-enable-Doorbell-support-for-Renoir-v2.patch
@@ -0,0 +1,75 @@
+From 736bbbac9ebbfd08548410a913b00357ccbf21a0 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Mon, 15 Jul 2019 10:14:17 -0400
+Subject: [PATCH 3387/4256] drm/amdgpu: enable Doorbell support for Renoir (v2)
+
+Add VCN range aperture to NBIO 7.0
+
+v2: rebase (Alex)
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c       | 21 ++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c |  4 ++++
+ 2 files changed, 25 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+index f73fb25ba242..6f3b55d0aa3c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+@@ -104,6 +104,26 @@ static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instan
+ 	WREG32(reg, doorbell_range);
+ }
+ 
++static void nbio_v7_0_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
++					 int doorbell_index, int instance)
++{
++	u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
++
++	u32 doorbell_range = RREG32(reg);
++
++	if (use_doorbell) {
++		doorbell_range = REG_SET_FIELD(doorbell_range,
++					       BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
++					       doorbell_index);
++		doorbell_range = REG_SET_FIELD(doorbell_range,
++					       BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
++	} else
++		doorbell_range = REG_SET_FIELD(doorbell_range,
++					       BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
++
++	WREG32(reg, doorbell_range);
++}
++
+ static void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
+ 					       bool enable)
+ {
+@@ -298,6 +318,7 @@ const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
+ 	.hdp_flush = nbio_v7_0_hdp_flush,
+ 	.get_memsize = nbio_v7_0_get_memsize,
+ 	.sdma_doorbell_range = nbio_v7_0_sdma_doorbell_range,
++	.vcn_doorbell_range = nbio_v7_0_vcn_doorbell_range,
+ 	.enable_doorbell_aperture = nbio_v7_0_enable_doorbell_aperture,
+ 	.enable_doorbell_selfring_aperture = nbio_v7_0_enable_doorbell_selfring_aperture,
+ 	.ih_doorbell_range = nbio_v7_0_ih_doorbell_range,
+diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+index a8e92638a2e8..bd0580334f83 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
++++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+@@ -81,6 +81,10 @@ void vega10_doorbell_index_init(struct amdgpu_device *adev)
+ 	adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_DOORBELL64_VCE_RING2_3;
+ 	adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_DOORBELL64_VCE_RING4_5;
+ 	adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_DOORBELL64_VCE_RING6_7;
++	adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_DOORBELL64_VCN0_1;
++	adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_DOORBELL64_VCN2_3;
++	adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_DOORBELL64_VCN4_5;
++	adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_DOORBELL64_VCN6_7;
+ 
+ 	adev->doorbell_index.first_non_cp = AMDGPU_DOORBELL64_FIRST_NON_CP;
+ 	adev->doorbell_index.last_non_cp = AMDGPU_DOORBELL64_LAST_NON_CP;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3388-drm-amdgpu-add-VCN2.0-to-Renoir-IP-blocks.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3388-drm-amdgpu-add-VCN2.0-to-Renoir-IP-blocks.patch
new file mode 100644
index 00000000..957b9a3b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3388-drm-amdgpu-add-VCN2.0-to-Renoir-IP-blocks.patch
@@ -0,0 +1,38 @@
+From e9b067bb551d9feecb63917ab7bdbd2e9d089c2b Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Mon, 15 Jul 2019 09:21:57 -0400
+Subject: [PATCH 3388/4256] drm/amdgpu: add VCN2.0 to Renoir IP blocks
+
+Thus enable VCN2.0 for Renoir
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 1aacf95998b9..8d3e711d5123 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -62,6 +62,7 @@
+ #include "uvd_v7_0.h"
+ #include "vce_v4_0.h"
+ #include "vcn_v1_0.h"
++#include "vcn_v2_0.h"
+ #include "vcn_v2_5.h"
+ #include "dce_virtual.h"
+ #include "mxgpu_ai.h"
+@@ -753,6 +754,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ 		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
+ 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+ 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
++		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
+ 		break;
+ 	default:
+ 		return -EINVAL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3389-drm-amdgpu-enable-clock-gating-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3389-drm-amdgpu-enable-clock-gating-for-renoir.patch
new file mode 100644
index 00000000..eef867a2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3389-drm-amdgpu-enable-clock-gating-for-renoir.patch
@@ -0,0 +1,44 @@
+From 548d197d71bb57e27da4dc7ea34807e2d532ced1 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Mon, 12 Aug 2019 11:32:56 -0500
+Subject: [PATCH 3389/4256] drm/amdgpu: enable clock gating for renoir
+
+enable gfx&common clock gating for renoir
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
+ drivers/gpu/drm/amd/amdgpu/soc15.c    | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 75ea77cc457f..db9d7f986b92 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4868,6 +4868,7 @@ static int gfx_v9_0_set_clockgating_state(void *handle,
+ 	case CHIP_VEGA20:
+ 	case CHIP_RAVEN:
+ 	case CHIP_ARCTURUS:
++	case CHIP_RENOIR:
+ 		gfx_v9_0_update_gfx_clock_gating(adev,
+ 						 state == AMD_CG_STATE_GATE ? true : false);
+ 		break;
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 8d3e711d5123..c2d324d8da75 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1405,6 +1405,7 @@ static int soc15_common_set_clockgating_state(void *handle,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+ 		break;
+ 	case CHIP_RAVEN:
++	case CHIP_RENOIR:
+ 		adev->nbio_funcs->update_medium_grain_clock_gating(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+ 		adev->nbio_funcs->update_medium_grain_light_sleep(adev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3390-drm-amdgpu-enable-power-gating-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3390-drm-amdgpu-enable-power-gating-for-renoir.patch
new file mode 100644
index 00000000..cae57bbe
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3390-drm-amdgpu-enable-power-gating-for-renoir.patch
@@ -0,0 +1,31 @@
+From 628e9198d8ddbd74b42ee7e7e2e7ee9034ea89e7 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Tue, 16 Jul 2019 17:09:47 +0800
+Subject: [PATCH 3390/4256] drm/amdgpu: enable power gating for renoir
+
+enable gfx power gating for renoir
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index db9d7f986b92..73440967c589 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4813,6 +4813,7 @@ static int gfx_v9_0_set_powergating_state(void *handle,
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_RAVEN:
++	case CHIP_RENOIR:
+ 		if (!enable) {
+ 			amdgpu_gfx_off_ctrl(adev, false);
+ 			cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3391-drm-amdgpu-update-lbpw-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3391-drm-amdgpu-update-lbpw-for-renoir.patch
new file mode 100644
index 00000000..ad6d9be3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3391-drm-amdgpu-update-lbpw-for-renoir.patch
@@ -0,0 +1,31 @@
+From 5f1c0a571eaecf239684f35491a9c6d6c6d2eb03 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Tue, 16 Jul 2019 17:36:43 +0800
+Subject: [PATCH 3391/4256] drm/amdgpu: update lbpw for renoir
+
+enable gfx_v9_0_init_lbpw for renoir
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 73440967c589..5c8107dc8803 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -1644,6 +1644,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_RAVEN:
++	case CHIP_RENOIR:
+ 		gfx_v9_0_init_lbpw(adev);
+ 		break;
+ 	case CHIP_VEGA20:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3392-drm-amdgpu-set-fw-default-loading-by-psp-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3392-drm-amdgpu-set-fw-default-loading-by-psp-for-renoir.patch
new file mode 100644
index 00000000..85ff2301
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3392-drm-amdgpu-set-fw-default-loading-by-psp-for-renoir.patch
@@ -0,0 +1,43 @@
+From 5934b99de598865073529455e871cf87ed2abd93 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Fri, 9 Aug 2019 10:46:36 -0500
+Subject: [PATCH 3392/4256] drm/amdgpu: set fw default loading by psp for
+ renoir
+
+By default, set amdgpu ucode type to AMDGPU_FW_LOAD_PSP.
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 6 +-----
+ 1 file changed, 1 insertion(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+index ee6a9bee8f08..35fd46bdfc53 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+@@ -360,6 +360,7 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
+ 	case CHIP_RAVEN:
+ 	case CHIP_VEGA12:
+ 	case CHIP_VEGA20:
++	case CHIP_RENOIR:
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+ 	case CHIP_NAVI12:
+@@ -369,11 +370,6 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
+ 			return AMDGPU_FW_LOAD_PSP;
+ 	case CHIP_ARCTURUS:
+ 		return AMDGPU_FW_LOAD_DIRECT;
+-	case CHIP_RENOIR:
+-		if (load_type == AMDGPU_FW_LOAD_PSP)
+-			return AMDGPU_FW_LOAD_PSP;
+-		else
+-			return AMDGPU_FW_LOAD_DIRECT;
+ 
+ 	default:
+ 		DRM_ERROR("Unknown firmware load type\n");
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3393-drm-amdgpu-skip-mec2-jump-table-loading-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3393-drm-amdgpu-skip-mec2-jump-table-loading-for-renoir.patch
new file mode 100644
index 00000000..fd942fc8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3393-drm-amdgpu-skip-mec2-jump-table-loading-for-renoir.patch
@@ -0,0 +1,33 @@
+From 9ba041aa366f9fd85127b2b2e49b277dc92582b8 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Sun, 21 Jul 2019 22:27:50 +0800
+Subject: [PATCH 3393/4256] drm/amdgpu: skip mec2 jump table loading for renoir
+
+Renoir need not load mec2 jump table with psp.
+
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Aaron Liu <aaron.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index fbb245908bcb..60e421d5aae4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1026,6 +1026,10 @@ static int psp_np_fw_load(struct psp_context *psp)
+ 		     ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
+ 			/* skip mec JT when autoload is enabled */
+ 			continue;
++		/* Renoir only needs to load mec jump table one time */
++		if (adev->asic_type == CHIP_RENOIR &&
++		    ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)
++			continue;
+ 
+ 		ret = psp_execute_np_fw_load(psp, ucode);
+ 		if (ret)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3394-drm-amd-powerplay-remove-redundancy-debug-log-about-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3394-drm-amd-powerplay-remove-redundancy-debug-log-about-.patch
new file mode 100644
index 00000000..56fe4d94
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3394-drm-amd-powerplay-remove-redundancy-debug-log-about-.patch
@@ -0,0 +1,30 @@
+From 7314ada7e5809987fa6429feb11ff7bc01fcba34 Mon Sep 17 00:00:00 2001
+From: Chengming Gui <Jack.Gui@amd.com>
+Date: Mon, 12 Aug 2019 10:06:34 +0800
+Subject: [PATCH 3394/4256] drm/amd/powerplay: remove redundancy debug log
+ about smu unsupported features
+
+remove redundancy debug log about smu unsupported features
+
+Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 6aa135938e00..efce71f858af 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -215,7 +215,6 @@ static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t inde
+ 
+ 	mapping = arcturus_feature_mask_map[index];
+ 	if (!(mapping.valid_mapping)) {
+-		pr_warn("Unsupported SMU feature: %d\n", index);
+ 		return -EINVAL;
+ 	}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3395-drm-amd-powerplay-add-arcturus_is_dpm_running-functi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3395-drm-amd-powerplay-add-arcturus_is_dpm_running-functi.patch
new file mode 100644
index 00000000..b38863e7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3395-drm-amd-powerplay-add-arcturus_is_dpm_running-functi.patch
@@ -0,0 +1,63 @@
+From 9d5aa46bb0bcf862436f5ea47900f028c9102f13 Mon Sep 17 00:00:00 2001
+From: Chengming Gui <Jack.Gui@amd.com>
+Date: Mon, 12 Aug 2019 10:23:04 +0800
+Subject: [PATCH 3395/4256] drm/amd/powerplay: add arcturus_is_dpm_running
+ function for arcturus
+
+add arcturus_is_dpm_running function
+
+Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 21 ++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index efce71f858af..fdf5b2c47cd0 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -51,6 +51,15 @@
+ #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
+ #define SMU_FEATURES_HIGH_SHIFT      32
+ 
++#define SMC_DPM_FEATURE ( \
++	FEATURE_DPM_PREFETCHER_MASK | \
++	FEATURE_DPM_GFXCLK_MASK | \
++	FEATURE_DPM_UCLK_MASK | \
++	FEATURE_DPM_SOCCLK_MASK | \
++	FEATURE_DPM_MP0CLK_MASK | \
++	FEATURE_DPM_FCLK_MASK | \
++	FEATURE_DPM_XGMI_MASK)
++
+ /* possible frequency drift (1Mhz) */
+ #define EPSILON				1
+ 
+@@ -1873,6 +1882,17 @@ static void arcturus_dump_pptable(struct smu_context *smu)
+ 
+ }
+ 
++static bool arcturus_is_dpm_running(struct smu_context *smu)
++{
++	int ret = 0;
++	uint32_t feature_mask[2];
++	unsigned long feature_enabled;
++	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
++	feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
++			   ((uint64_t)feature_mask[1] << 32));
++	return !!(feature_enabled & SMC_DPM_FEATURE);
++}
++
+ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 	/* translate smu index into arcturus specific index */
+ 	.get_smu_msg_index = arcturus_get_smu_msg_index,
+@@ -1910,6 +1930,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 	/* debug (internal used) */
+ 	.dump_pptable = arcturus_dump_pptable,
+ 	.get_power_limit = arcturus_get_power_limit,
++	.is_dpm_running = arcturus_is_dpm_running,
+ };
+ 
+ void arcturus_set_ppt_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3396-drm-amdkfd-Fill-amdgpu_task_info-for-KFD-VMs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3396-drm-amdkfd-Fill-amdgpu_task_info-for-KFD-VMs.patch
new file mode 100644
index 00000000..3250592b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3396-drm-amdkfd-Fill-amdgpu_task_info-for-KFD-VMs.patch
@@ -0,0 +1,30 @@
+From e1e865d2ff94f3450c93afff64f87e6f17d415d4 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 7 Aug 2019 17:45:37 -0400
+Subject: [PATCH 3396/4256] drm/amdkfd: Fill amdgpu_task_info for KFD VMs
+
+The amdgpu_task_info will be used when printing VM page fault for KFD
+processes.
+
+Change-Id: Ifd983db5dceb1d477e7287e4893f80565a7a6b06
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+index bcdc1f915bc8..04a621a76822 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+@@ -874,6 +874,8 @@ int kfd_process_device_init_vm(struct kfd_process_device *pdd,
+ 		return ret;
+ 	}
+ 
++	amdgpu_vm_set_task_info(pdd->vm);
++
+ 	ret = kfd_process_device_reserve_ib_mem(pdd);
+ 	if (ret)
+ 		goto err_reserve_ib_mem;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3397-drm-amd-display-reset-drr-programming-on-pipe-reset.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3397-drm-amd-display-reset-drr-programming-on-pipe-reset.patch
new file mode 100644
index 00000000..08c471df
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3397-drm-amd-display-reset-drr-programming-on-pipe-reset.patch
@@ -0,0 +1,52 @@
+From 23f4b699fefc836643463331c83f1e7bcacd7b1e Mon Sep 17 00:00:00 2001
+From: Wenjing Liu <Wenjing.Liu@amd.com>
+Date: Wed, 10 Jul 2019 18:31:38 -0400
+Subject: [PATCH 3397/4256] drm/amd/display: reset drr programming on pipe
+ reset
+
+[why]
+drr is still enabled after driver is unloaded causing black screen
+
+[how]
+disable drr during pipe reset.
+
+Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 +++
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c        | 4 ++++
+ 2 files changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 29e548ab73c4..84980d4f324d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -822,6 +822,9 @@ static void dcn10_reset_back_end_for_pipe(
+ 		pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
+ 
+ 		pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
++		if (pipe_ctx->stream_res.tg->funcs->set_drr)
++			pipe_ctx->stream_res.tg->funcs->set_drr(
++					pipe_ctx->stream_res.tg, NULL);
+ 	}
+ 
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 38b3c89b2a59..27d143418cc7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1834,6 +1834,10 @@ static void dcn20_reset_back_end_for_pipe(
+ 		if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
+ 			pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
+ 					pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
++
++		if (pipe_ctx->stream_res.tg->funcs->set_drr)
++			pipe_ctx->stream_res.tg->funcs->set_drr(
++					pipe_ctx->stream_res.tg, NULL);
+ 	}
+ 
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3398-drm-amd-display-reset-hdmi-tmds-rate-and-data-scramb.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3398-drm-amd-display-reset-hdmi-tmds-rate-and-data-scramb.patch
new file mode 100644
index 00000000..9295676a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3398-drm-amd-display-reset-hdmi-tmds-rate-and-data-scramb.patch
@@ -0,0 +1,176 @@
+From b86f17b2dd5226ec88b5af5829a3f0fce25a0689 Mon Sep 17 00:00:00 2001
+From: Wenjing Liu <Wenjing.Liu@amd.com>
+Date: Wed, 10 Jul 2019 18:35:18 -0400
+Subject: [PATCH 3398/4256] drm/amd/display: reset hdmi tmds rate and data
+ scramble on pipe reset
+
+[why]
+hdmi data scramble and tmds rate is not reset during pipe reset.
+
+[how]
+reset hdmi tmds rate and data scramble on pipe reset
+
+Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Reviewed-by: Chris Park <Chris.Park@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/dce/dce_stream_encoder.c   | 19 +++++++++++++++++++
+ .../display/dc/dce110/dce110_hw_sequencer.c   |  5 ++++-
+ .../display/dc/dcn10/dcn10_stream_encoder.c   | 14 ++++++++++++++
+ .../display/dc/dcn10/dcn10_stream_encoder.h   |  3 +++
+ .../display/dc/dcn20/dcn20_stream_encoder.c   |  1 +
+ .../amd/display/dc/inc/hw/stream_encoder.h    |  3 +++
+ .../dc/virtual/virtual_stream_encoder.c       |  5 +++++
+ 7 files changed, 49 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+index bd353796b767..7e8b8ae036ee 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+@@ -1036,6 +1036,24 @@ static void dce110_stream_encoder_set_avmute(
+ }
+ 
+ 
++static void dce110_reset_hdmi_stream_attribute(
++	struct stream_encoder *enc)
++{
++	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
++	if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN)
++		REG_UPDATE_5(HDMI_CONTROL,
++			HDMI_PACKET_GEN_VERSION, 1,
++			HDMI_KEEPOUT_MODE, 1,
++			HDMI_DEEP_COLOR_ENABLE, 0,
++			HDMI_DATA_SCRAMBLE_EN, 0,
++			HDMI_CLOCK_CHANNEL_RATE, 0);
++	else
++		REG_UPDATE_3(HDMI_CONTROL,
++			HDMI_PACKET_GEN_VERSION, 1,
++			HDMI_KEEPOUT_MODE, 1,
++			HDMI_DEEP_COLOR_ENABLE, 0);
++}
++
+ #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
+ #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
+ 
+@@ -1616,6 +1634,7 @@ static const struct stream_encoder_funcs dce110_str_enc_funcs = {
+ 	.setup_stereo_sync  = setup_stereo_sync,
+ 	.set_avmute = dce110_stream_encoder_set_avmute,
+ 	.dig_connect_to_otg  = dig_connect_to_otg,
++	.hdmi_reset_stream_attribute = dce110_reset_hdmi_stream_attribute,
+ };
+ 
+ void dce110_stream_encoder_construct(
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 46dfab749679..919647166bce 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -1037,9 +1037,12 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
+ 	struct dc_link *link = stream->link;
+ 	struct dc *dc = pipe_ctx->stream->ctx->dc;
+ 
+-	if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
++	if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
+ 		pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
+ 			pipe_ctx->stream_res.stream_enc);
++		pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(
++			pipe_ctx->stream_res.stream_enc);
++	}
+ 
+ 	if (dc_is_dp_signal(pipe_ctx->stream->signal))
+ 		pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+index a098287d71ae..00aa9dde5538 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+@@ -1003,6 +1003,19 @@ void enc1_stream_encoder_set_avmute(
+ 	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
+ }
+ 
++void enc1_reset_hdmi_stream_attribute(
++	struct stream_encoder *enc)
++{
++	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
++
++	REG_UPDATE_5(HDMI_CONTROL,
++		HDMI_PACKET_GEN_VERSION, 1,
++		HDMI_KEEPOUT_MODE, 1,
++		HDMI_DEEP_COLOR_ENABLE, 0,
++		HDMI_DATA_SCRAMBLE_EN, 0,
++		HDMI_CLOCK_CHANNEL_RATE, 0);
++}
++
+ 
+ #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
+ #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
+@@ -1562,6 +1575,7 @@ static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
+ 	.setup_stereo_sync  = enc1_setup_stereo_sync,
+ 	.set_avmute = enc1_stream_encoder_set_avmute,
+ 	.dig_connect_to_otg  = enc1_dig_connect_to_otg,
++	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
+ };
+ 
+ void dcn10_stream_encoder_construct(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+index f585e7b620cc..8b8921e75984 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+@@ -615,4 +615,7 @@ void get_audio_clock_info(
+ 	uint32_t actual_pixel_clock_100Hz,
+ 	struct audio_clock_info *audio_clock_info);
+ 
++void enc1_reset_hdmi_stream_attribute(
++	struct stream_encoder *enc);
++
+ #endif /* __DC_STREAM_ENCODER_DCN10_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+index 403f1f865a06..b2c1cad3c94f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+@@ -586,6 +586,7 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = {
+ 	.dp_set_dsc_config = enc2_dp_set_dsc_config,
+ #endif
+ 	.set_dynamic_metadata = enc2_set_dynamic_metadata,
++	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
+ };
+ 
+ void dcn20_stream_encoder_construct(
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+index ed7d9588b309..38e2c3e7412e 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+@@ -211,6 +211,9 @@ struct stream_encoder_funcs {
+ 		struct stream_encoder *enc,
+ 		int tg_inst);
+ 
++	void (*hdmi_reset_stream_attribute)(
++		struct stream_encoder *enc);
++
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	void (*dp_set_dsc_config)(
+diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
+index 768bc8c75b6a..0c6d502da8a6 100644
+--- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
+@@ -75,6 +75,10 @@ static void virtual_audio_mute_control(
+ 	struct stream_encoder *enc,
+ 	bool mute) {}
+ 
++static void virtual_stream_encoder_reset_hdmi_stream_attribute(
++		struct stream_encoder *enc)
++{}
++
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ static void virtual_enc_dp_set_odm_combine(
+@@ -114,6 +118,7 @@ static const struct stream_encoder_funcs virtual_str_enc_funcs = {
+ 
+ 	.audio_mute_control = virtual_audio_mute_control,
+ 	.set_avmute = virtual_stream_encoder_set_avmute,
++	.hdmi_reset_stream_attribute = virtual_stream_encoder_reset_hdmi_stream_attribute,
+ };
+ 
+ bool virtual_stream_encoder_construct(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3399-drm-amd-display-fix-issue-where-252-255-values-are-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3399-drm-amd-display-fix-issue-where-252-255-values-are-c.patch
new file mode 100644
index 00000000..9d73c5ef
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3399-drm-amd-display-fix-issue-where-252-255-values-are-c.patch
@@ -0,0 +1,41 @@
+From 9ae5bc2f604a7415e688a2ca56e95809282f9644 Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Fri, 12 Jul 2019 10:52:54 -0400
+Subject: [PATCH 3399/4256] drm/amd/display: fix issue where 252-255 values are
+ clipped
+
+[Why]
+When endpoint is at the boundary of a region, such as at 2^0=1
+we find that the last segment has a sharp slope and some points
+are clipped at the top.
+
+[How]
+If end point is 1, which is exactly at the 2^0 region boundary, we
+need to program an additional region beyond this point.
+
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+index 7469333a2c8a..8166fdbacd73 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+@@ -357,9 +357,10 @@ bool cm_helper_translate_curve_to_hw_format(
+ 		seg_distr[7] = 4;
+ 		seg_distr[8] = 4;
+ 		seg_distr[9] = 4;
++		seg_distr[10] = 1;
+ 
+ 		region_start = -10;
+-		region_end = 0;
++		region_end = 1;
+ 	}
+ 
+ 	for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3400-drm-amd-display-Fix-frames_to_insert-math.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3400-drm-amd-display-Fix-frames_to_insert-math.patch
new file mode 100644
index 00000000..8b7c0cc8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3400-drm-amd-display-Fix-frames_to_insert-math.patch
@@ -0,0 +1,108 @@
+From b5ab6ab9b86b247af329cdc2a6da0a245f70cd03 Mon Sep 17 00:00:00 2001
+From: Bayan Zabihiyan <bayan.zabihiyan@amd.com>
+Date: Wed, 10 Jul 2019 16:00:53 -0400
+Subject: [PATCH 3400/4256] drm/amd/display: Fix frames_to_insert math
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+[Why]
+The math on deciding on how many
+"frames to insert" sometimes sent us over the max refresh rate.
+Also integer overflow can occur if we have high refresh rates.
+
+[How]
+Instead of clipping the  frame duration such that it doesn’t go below the min,
+just remove a frame from the number of frames to insert. +
+Use unsigned long long for intermediate calculations to prevent
+integer overflow.
+
+Signed-off-by: Bayan Zabihiyan <bayan.zabihiyan@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/modules/freesync/freesync.c   | 27 ++++++++++++-------
+ 1 file changed, 17 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+index 19b1eaebe484..000a9db9dad8 100644
+--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
++++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+@@ -433,6 +433,12 @@ static void apply_below_the_range(struct core_freesync *core_freesync,
+ 		/* Either we've calculated the number of frames to insert,
+ 		 * or we need to insert min duration frames
+ 		 */
++		if (last_render_time_in_us / frames_to_insert <
++				in_out_vrr->min_duration_in_us){
++			frames_to_insert -= (frames_to_insert > 1) ?
++					1 : 0;
++		}
++
+ 		if (frames_to_insert > 0)
+ 			inserted_frame_duration_in_us = last_render_time_in_us /
+ 							frames_to_insert;
+@@ -885,8 +891,8 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
+ 	struct core_freesync *core_freesync = NULL;
+ 	unsigned long long nominal_field_rate_in_uhz = 0;
+ 	unsigned int refresh_range = 0;
+-	unsigned int min_refresh_in_uhz = 0;
+-	unsigned int max_refresh_in_uhz = 0;
++	unsigned long long min_refresh_in_uhz = 0;
++	unsigned long long max_refresh_in_uhz = 0;
+ 
+ 	if (mod_freesync == NULL)
+ 		return;
+@@ -913,7 +919,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
+ 		min_refresh_in_uhz = nominal_field_rate_in_uhz;
+ 
+ 	if (!vrr_settings_require_update(core_freesync,
+-			in_config, min_refresh_in_uhz, max_refresh_in_uhz,
++			in_config, (unsigned int)min_refresh_in_uhz, (unsigned int)max_refresh_in_uhz,
+ 			in_out_vrr))
+ 		return;
+ 
+@@ -929,15 +935,15 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
+ 		return;
+ 
+ 	} else {
+-		in_out_vrr->min_refresh_in_uhz = min_refresh_in_uhz;
++		in_out_vrr->min_refresh_in_uhz = (unsigned int)min_refresh_in_uhz;
+ 		in_out_vrr->max_duration_in_us =
+ 				calc_duration_in_us_from_refresh_in_uhz(
+-						min_refresh_in_uhz);
++						(unsigned int)min_refresh_in_uhz);
+ 
+-		in_out_vrr->max_refresh_in_uhz = max_refresh_in_uhz;
++		in_out_vrr->max_refresh_in_uhz = (unsigned int)max_refresh_in_uhz;
+ 		in_out_vrr->min_duration_in_us =
+ 				calc_duration_in_us_from_refresh_in_uhz(
+-						max_refresh_in_uhz);
++						(unsigned int)max_refresh_in_uhz);
+ 
+ 		refresh_range = in_out_vrr->max_refresh_in_uhz -
+ 				in_out_vrr->min_refresh_in_uhz;
+@@ -948,17 +954,18 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
+ 	in_out_vrr->fixed.ramping_active = in_config->ramping;
+ 
+ 	in_out_vrr->btr.btr_enabled = in_config->btr;
++
+ 	if (in_out_vrr->max_refresh_in_uhz <
+ 			2 * in_out_vrr->min_refresh_in_uhz)
+ 		in_out_vrr->btr.btr_enabled = false;
++
+ 	in_out_vrr->btr.btr_active = false;
+ 	in_out_vrr->btr.inserted_duration_in_us = 0;
+ 	in_out_vrr->btr.frames_to_insert = 0;
+ 	in_out_vrr->btr.frame_counter = 0;
+ 	in_out_vrr->btr.mid_point_in_us =
+-			in_out_vrr->min_duration_in_us +
+-				(in_out_vrr->max_duration_in_us -
+-				in_out_vrr->min_duration_in_us) / 2;
++				(in_out_vrr->min_duration_in_us +
++				 in_out_vrr->max_duration_in_us) / 2;
+ 
+ 	if (in_out_vrr->state == VRR_STATE_UNSUPPORTED) {
+ 		in_out_vrr->adjust.v_total_min = stream->timing.v_total;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3401-drm-amd-display-Add-22-24-and-26-degamma.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3401-drm-amd-display-Add-22-24-and-26-degamma.patch
new file mode 100644
index 00000000..4c4db92e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3401-drm-amd-display-Add-22-24-and-26-degamma.patch
@@ -0,0 +1,315 @@
+From 0b57b3eaddc330776ccd037d0705c4d965adda9f Mon Sep 17 00:00:00 2001
+From: Vitaly Prosyak <vitaly.prosyak@amd.com>
+Date: Wed, 10 Jul 2019 14:20:08 -0500
+Subject: [PATCH 3401/4256] drm/amd/display: Add 22, 24, and 26 degamma
+
+[Why & How]
+Support degamma ROM and RAM based on hardware capabilities.
+Some refactoring into color module
+
+Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
+Reviewed-by: Gary Kattan <Gary.Kattan@amd.com>
+Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Acked-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h           |   5 +-
+ .../amd/display/modules/color/color_gamma.c   | 116 +++++++++++-------
+ 2 files changed, 75 insertions(+), 46 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 85e1ce5d5225..110055142ac5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -628,9 +628,12 @@ enum dc_transfer_func_predefined {
+ 	TRANSFER_FUNCTION_UNITY,
+ 	TRANSFER_FUNCTION_HLG,
+ 	TRANSFER_FUNCTION_HLG12,
+-	TRANSFER_FUNCTION_GAMMA22
++	TRANSFER_FUNCTION_GAMMA22,
++	TRANSFER_FUNCTION_GAMMA24,
++	TRANSFER_FUNCTION_GAMMA26
+ };
+ 
++
+ struct dc_transfer_func {
+ 	struct kref refcount;
+ 	enum dc_transfer_func_type type;
+diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+index 294fe4f0cb67..8b2ee606dbc2 100644
+--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
++++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+@@ -57,12 +57,12 @@ static struct translate_from_linear_space_args scratch_gamma_args;
+ static struct fixed31_32 pow_buffer[NUM_PTS_IN_REGION];
+ static struct fixed31_32 gamma_of_2; // 2^gamma
+ int pow_buffer_ptr = -1;
+-
+-static const int32_t gamma_numerator01[] = { 31308,	180000,	0};
+-static const int32_t gamma_numerator02[] = { 12920,	4500,	0};
+-static const int32_t gamma_numerator03[] = { 55,	99,	0};
+-static const int32_t gamma_numerator04[] = { 55,	99,	0};
+-static const int32_t gamma_numerator05[] = { 2400,	2200, 2200};
++										/*sRGB	 709 2.2 2.4 P3*/
++static const int32_t gamma_numerator01[] = { 31308,	180000,	0,	0,	0};
++static const int32_t gamma_numerator02[] = { 12920,	4500,	0,	0,	0};
++static const int32_t gamma_numerator03[] = { 55,	99,		0,	0,	0};
++static const int32_t gamma_numerator04[] = { 55,	99,		0,	0,	0};
++static const int32_t gamma_numerator05[] = { 2400,	2200,	2200, 2400, 2600};
+ 
+ static bool pq_initialized; /* = false; */
+ static bool de_pq_initialized; /* = false; */
+@@ -267,23 +267,28 @@ struct dividers {
+ 	struct fixed31_32 divider3;
+ };
+ 
+-enum gamma_type_index {
+-	gamma_type_index_2_4,
+-	gamma_type_index_2_2,
+-	gamma_type_index_2_2_flat
+-};
+ 
+-static void build_coefficients(struct gamma_coefficients *coefficients, enum gamma_type_index type)
++static bool build_coefficients(struct gamma_coefficients *coefficients, enum dc_transfer_func_predefined type)
+ {
+ 
+-
+ 	uint32_t i = 0;
+ 	uint32_t index = 0;
++	bool ret = true;
+ 
+-	if (type == gamma_type_index_2_2)
++	if (type == TRANSFER_FUNCTION_SRGB)
++		index = 0;
++	else if (type == TRANSFER_FUNCTION_BT709)
+ 		index = 1;
+-	else if (type == gamma_type_index_2_2_flat)
++	else if (type == TRANSFER_FUNCTION_GAMMA22)
+ 		index = 2;
++	else if (type == TRANSFER_FUNCTION_GAMMA24)
++		index = 3;
++	else if (type == TRANSFER_FUNCTION_GAMMA26)
++		index = 4;
++	else {
++		ret = false;
++		goto release;
++	}
+ 
+ 	do {
+ 		coefficients->a0[i] = dc_fixpt_from_fraction(
+@@ -299,6 +304,8 @@ static void build_coefficients(struct gamma_coefficients *coefficients, enum gam
+ 
+ 		++i;
+ 	} while (i != ARRAY_SIZE(coefficients->a0));
++release:
++	return ret;
+ }
+ 
+ static struct fixed31_32 translate_from_linear_space(
+@@ -735,11 +742,12 @@ static void build_de_pq(struct pwl_float_data_ex *de_pq,
+ 	}
+ }
+ 
+-static void build_regamma(struct pwl_float_data_ex *rgb_regamma,
++static bool build_regamma(struct pwl_float_data_ex *rgb_regamma,
+ 		uint32_t hw_points_num,
+-		const struct hw_x_point *coordinate_x, enum gamma_type_index type)
++		const struct hw_x_point *coordinate_x, enum dc_transfer_func_predefined type)
+ {
+ 	uint32_t i;
++	bool ret = false;
+ 
+ 	struct gamma_coefficients *coeff;
+ 	struct pwl_float_data_ex *rgb = rgb_regamma;
+@@ -747,9 +755,10 @@ static void build_regamma(struct pwl_float_data_ex *rgb_regamma,
+ 
+ 	coeff = kvzalloc(sizeof(*coeff), GFP_KERNEL);
+ 	if (!coeff)
+-		return;
++		goto release;
+ 
+-	build_coefficients(coeff, type);
++	if (!build_coefficients(coeff, type))
++		goto release;
+ 
+ 	memset(pow_buffer, 0, NUM_PTS_IN_REGION * sizeof(struct fixed31_32));
+ 	pow_buffer_ptr = 0; // see variable definition for more info
+@@ -765,8 +774,10 @@ static void build_regamma(struct pwl_float_data_ex *rgb_regamma,
+ 		++i;
+ 	}
+ 	pow_buffer_ptr = -1; // reset back to no optimize
+-
++	ret = true;
++release:
+ 	kfree(coeff);
++	return ret;
+ }
+ 
+ static void hermite_spline_eetf(struct fixed31_32 input_x,
+@@ -941,15 +952,18 @@ static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
+ 	return true;
+ }
+ 
+-static void build_degamma(struct pwl_float_data_ex *curve,
++static bool build_degamma(struct pwl_float_data_ex *curve,
+ 		uint32_t hw_points_num,
+-		const struct hw_x_point *coordinate_x, enum gamma_type_index type)
++		const struct hw_x_point *coordinate_x, enum dc_transfer_func_predefined type)
+ {
+ 	uint32_t i;
+ 	struct gamma_coefficients coeff;
+ 	uint32_t begin_index, end_index;
++	bool ret = false;
++
++	if (!build_coefficients(&coeff, type))
++		goto release;
+ 
+-	build_coefficients(&coeff, type);
+ 	i = 0;
+ 
+ 	/* X points is 2^-25 to 2^7
+@@ -978,6 +992,9 @@ static void build_degamma(struct pwl_float_data_ex *curve,
+ 		curve[i].b = dc_fixpt_one;
+ 		i++;
+ 	}
++	ret = true;
++release:
++	return ret;
+ }
+ 
+ static void build_hlg_degamma(struct pwl_float_data_ex *degamma,
+@@ -1672,6 +1689,12 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
+ 				MAX_HW_POINTS,
+ 				coordinates_x,
+ 				fs_params);
++	} else if (tf == TRANSFER_FUNCTION_HLG) {
++		build_freesync_hdr(rgb_regamma,
++				MAX_HW_POINTS,
++				coordinates_x,
++				fs_params);
++
+ 	} else {
+ 		tf_pts->end_exponent = 0;
+ 		tf_pts->x_point_at_y1_red = 1;
+@@ -1680,9 +1703,7 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
+ 
+ 		build_regamma(rgb_regamma,
+ 				MAX_HW_POINTS,
+-				coordinates_x, tf == TRANSFER_FUNCTION_SRGB ? gamma_type_index_2_4 :
+-					tf == TRANSFER_FUNCTION_GAMMA22 ?
+-					gamma_type_index_2_2_flat : gamma_type_index_2_2);
++				coordinates_x, tf);
+ 	}
+ 	map_regamma_hw_to_x_user(ramp, coeff, rgb_user,
+ 			coordinates_x, axis_x, rgb_regamma,
+@@ -1883,13 +1904,19 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf,
+ 				MAX_HW_POINTS,
+ 				coordinates_x);
+ 	else if (tf == TRANSFER_FUNCTION_SRGB ||
+-			tf == TRANSFER_FUNCTION_BT709)
++		tf == TRANSFER_FUNCTION_BT709 ||
++		tf == TRANSFER_FUNCTION_GAMMA22 ||
++		tf == TRANSFER_FUNCTION_GAMMA24 ||
++		tf == TRANSFER_FUNCTION_GAMMA26)
+ 		build_degamma(curve,
+ 				MAX_HW_POINTS,
+ 				coordinates_x,
+-				tf == TRANSFER_FUNCTION_SRGB ?
+-				gamma_type_index_2_4 : tf == TRANSFER_FUNCTION_GAMMA22 ?
+-				gamma_type_index_2_2_flat : gamma_type_index_2_2);
++				tf);
++	else if (tf == TRANSFER_FUNCTION_HLG)
++		build_hlg_degamma(curve,
++				MAX_HW_POINTS,
++				coordinates_x,
++				true);
+ 	else if (tf == TRANSFER_FUNCTION_LINEAR) {
+ 		// just copy coordinates_x into curve
+ 		i = 0;
+@@ -1976,7 +2003,10 @@ bool  mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
+ 
+ 		kvfree(rgb_regamma);
+ 	} else if (trans == TRANSFER_FUNCTION_SRGB ||
+-			  trans == TRANSFER_FUNCTION_BT709) {
++		trans == TRANSFER_FUNCTION_BT709 ||
++		trans == TRANSFER_FUNCTION_GAMMA22 ||
++		trans == TRANSFER_FUNCTION_GAMMA24 ||
++		trans == TRANSFER_FUNCTION_GAMMA26) {
+ 		rgb_regamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS,
+ 				       sizeof(*rgb_regamma),
+ 				       GFP_KERNEL);
+@@ -1990,9 +2020,7 @@ bool  mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
+ 		build_regamma(rgb_regamma,
+ 				MAX_HW_POINTS,
+ 				coordinates_x,
+-				trans == TRANSFER_FUNCTION_SRGB ?
+-				gamma_type_index_2_4 : trans == TRANSFER_FUNCTION_GAMMA22 ?
+-				gamma_type_index_2_2_flat : gamma_type_index_2_2);
++				trans);
+ 		for (i = 0; i <= MAX_HW_POINTS ; i++) {
+ 			points->red[i]    = rgb_regamma[i].r;
+ 			points->green[i]  = rgb_regamma[i].g;
+@@ -2001,8 +2029,7 @@ bool  mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
+ 		ret = true;
+ 
+ 		kvfree(rgb_regamma);
+-	} else if (trans == TRANSFER_FUNCTION_HLG ||
+-		trans == TRANSFER_FUNCTION_HLG12) {
++	} else if (trans == TRANSFER_FUNCTION_HLG) {
+ 		rgb_regamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS,
+ 				       sizeof(*rgb_regamma),
+ 				       GFP_KERNEL);
+@@ -2012,7 +2039,7 @@ bool  mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
+ 		build_hlg_regamma(rgb_regamma,
+ 				MAX_HW_POINTS,
+ 				coordinates_x,
+-				trans == TRANSFER_FUNCTION_HLG12 ? true:false);
++				true);
+ 		for (i = 0; i <= MAX_HW_POINTS ; i++) {
+ 			points->red[i]    = rgb_regamma[i].r;
+ 			points->green[i]  = rgb_regamma[i].g;
+@@ -2062,8 +2089,10 @@ bool  mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
+ 
+ 		kvfree(rgb_degamma);
+ 	} else if (trans == TRANSFER_FUNCTION_SRGB ||
+-			  trans == TRANSFER_FUNCTION_BT709 ||
+-			  trans == TRANSFER_FUNCTION_GAMMA22) {
++		trans == TRANSFER_FUNCTION_BT709 ||
++		trans == TRANSFER_FUNCTION_GAMMA22 ||
++		trans == TRANSFER_FUNCTION_GAMMA24 ||
++		trans == TRANSFER_FUNCTION_GAMMA26) {
+ 		rgb_degamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS,
+ 				       sizeof(*rgb_degamma),
+ 				       GFP_KERNEL);
+@@ -2073,9 +2102,7 @@ bool  mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
+ 		build_degamma(rgb_degamma,
+ 				MAX_HW_POINTS,
+ 				coordinates_x,
+-				trans == TRANSFER_FUNCTION_SRGB ?
+-				gamma_type_index_2_4 : trans == TRANSFER_FUNCTION_GAMMA22 ?
+-				gamma_type_index_2_2_flat : gamma_type_index_2_2);
++				trans);
+ 		for (i = 0; i <= MAX_HW_POINTS ; i++) {
+ 			points->red[i]    = rgb_degamma[i].r;
+ 			points->green[i]  = rgb_degamma[i].g;
+@@ -2084,8 +2111,7 @@ bool  mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
+ 		ret = true;
+ 
+ 		kvfree(rgb_degamma);
+-	} else if (trans == TRANSFER_FUNCTION_HLG ||
+-		trans == TRANSFER_FUNCTION_HLG12) {
++	} else if (trans == TRANSFER_FUNCTION_HLG) {
+ 		rgb_degamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS,
+ 				       sizeof(*rgb_degamma),
+ 				       GFP_KERNEL);
+@@ -2095,7 +2121,7 @@ bool  mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
+ 		build_hlg_degamma(rgb_degamma,
+ 				MAX_HW_POINTS,
+ 				coordinates_x,
+-				trans == TRANSFER_FUNCTION_HLG12 ? true:false);
++				true);
+ 		for (i = 0; i <= MAX_HW_POINTS ; i++) {
+ 			points->red[i]    = rgb_degamma[i].r;
+ 			points->green[i]  = rgb_degamma[i].g;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3402-drm-amd-display-Improve-sharing-of-HUBBUB-register-l.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3402-drm-amd-display-Improve-sharing-of-HUBBUB-register-l.patch
new file mode 100644
index 00000000..dd2f6034
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3402-drm-amd-display-Improve-sharing-of-HUBBUB-register-l.patch
@@ -0,0 +1,48 @@
+From 44d626dddb7c5632baf3e55ed9bc173a29a5aa7b Mon Sep 17 00:00:00 2001
+From: Julian Parkin <julian.parkin@amd.com>
+Date: Fri, 12 Jul 2019 17:30:06 -0400
+Subject: [PATCH 3402/4256] drm/amd/display: Improve sharing of HUBBUB register
+ lists
+
+Add DCN20 common register list that contains registers shared
+between DCN20 generations.
+
+Signed-off-by: Julian Parkin <julian.parkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
+index a7b6ca26a9ad..caf7273ca240 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
+@@ -32,10 +32,8 @@
+ #define TO_DCN20_HUBBUB(hubbub)\
+ 	container_of(hubbub, struct dcn20_hubbub, base)
+ 
+-#define HUBBUB_REG_LIST_DCN20(id)\
++#define HUBBUB_REG_LIST_DCN20_COMMON()\
+ 	HUBBUB_REG_LIST_DCN_COMMON(), \
+-	HUBBUB_VM_REG_LIST(), \
+-	HUBBUB_SR_WATERMARK_REG_LIST(), \
+ 	SR(DCHUBBUB_CRC_CTRL), \
+ 	SR(DCN_VM_FB_LOCATION_BASE),\
+ 	SR(DCN_VM_FB_LOCATION_TOP),\
+@@ -44,6 +42,11 @@
+ 	SR(DCN_VM_AGP_TOP),\
+ 	SR(DCN_VM_AGP_BASE)
+ 
++#define HUBBUB_REG_LIST_DCN20(id)\
++	HUBBUB_REG_LIST_DCN20_COMMON(), \
++	HUBBUB_SR_WATERMARK_REG_LIST(), \
++	HUBBUB_VM_REG_LIST()
++
+ #define HUBBUB_MASK_SH_LIST_DCN20(mask_sh)\
+ 	HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
+ 	HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3403-drm-amd-display-Synchronous-DisplayPort-Link-Trainin.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3403-drm-amd-display-Synchronous-DisplayPort-Link-Trainin.patch
new file mode 100644
index 00000000..0aadd3bd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3403-drm-amd-display-Synchronous-DisplayPort-Link-Trainin.patch
@@ -0,0 +1,622 @@
+From 3ad3e128c0b59e0b90a75a758470c275e3a64b70 Mon Sep 17 00:00:00 2001
+From: David Galiffi <david.galiffi@amd.com>
+Date: Mon, 24 Jun 2019 10:34:13 -0400
+Subject: [PATCH 3403/4256] drm/amd/display: Synchronous DisplayPort Link
+ Training
+
+[WHY]
+We require a method to perform synchronous link training.
+
+[HOW]
+Sync LT is broken into 3 basic steps.
+"Begin" starts the state machine, and resets "preferred" link settings.
+"Attempt" will attempt to train the link with a given set of training
+parameters.
+"End" stops the state machine, and will optionally disable the link phy.
+Between "Begin" and "End" DPCD:600h must not be set to "2"
+(D3:Powered Down).
+Between "Begin" and "End", there may be multiple "Attempts" with different
+training parameters.
+
+Signed-off-by: David Galiffi <david.galiffi@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c |  53 +---
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 293 ++++++++++++++++--
+ .../drm/amd/display/dc/core/dc_link_hwss.c    |  43 +--
+ drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |   3 +
+ drivers/gpu/drm/amd/display/dc/dc_link.h      |  10 +
+ .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |   3 +
+ .../gpu/drm/amd/display/dc/inc/link_hwss.h    |   2 -
+ 7 files changed, 282 insertions(+), 125 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 333ce7a5d89c..ed8bdcf44c8e 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -1385,57 +1385,6 @@ void link_destroy(struct dc_link **link)
+ 	*link = NULL;
+ }
+ 
+-static void dpcd_configure_panel_mode(
+-	struct dc_link *link,
+-	enum dp_panel_mode panel_mode)
+-{
+-	union dpcd_edp_config edp_config_set;
+-	bool panel_mode_edp = false;
+-	DC_LOGGER_INIT(link->ctx->logger);
+-
+-	memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
+-
+-	if (DP_PANEL_MODE_DEFAULT != panel_mode) {
+-
+-		switch (panel_mode) {
+-		case DP_PANEL_MODE_EDP:
+-		case DP_PANEL_MODE_SPECIAL:
+-			panel_mode_edp = true;
+-			break;
+-
+-		default:
+-			break;
+-		}
+-
+-		/*set edp panel mode in receiver*/
+-		core_link_read_dpcd(
+-			link,
+-			DP_EDP_CONFIGURATION_SET,
+-			&edp_config_set.raw,
+-			sizeof(edp_config_set.raw));
+-
+-		if (edp_config_set.bits.PANEL_MODE_EDP
+-			!= panel_mode_edp) {
+-			enum ddc_result result = DDC_RESULT_UNKNOWN;
+-
+-			edp_config_set.bits.PANEL_MODE_EDP =
+-			panel_mode_edp;
+-			result = core_link_write_dpcd(
+-				link,
+-				DP_EDP_CONFIGURATION_SET,
+-				&edp_config_set.raw,
+-				sizeof(edp_config_set.raw));
+-
+-			ASSERT(result == DDC_RESULT_SUCESSFULL);
+-		}
+-	}
+-	DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
+-			"eDP panel mode enabled: %d \n",
+-			link->link_index,
+-			link->dpcd_caps.panel_mode_edp,
+-			panel_mode_edp);
+-}
+-
+ static void enable_stream_features(struct pipe_ctx *pipe_ctx)
+ {
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+@@ -1506,7 +1455,7 @@ static enum dc_status enable_link_dp(
+ 	}
+ 
+ 	panel_mode = dp_get_panel_mode(link);
+-	dpcd_configure_panel_mode(link, panel_mode);
++	dp_set_panel_mode(link, panel_mode);
+ 
+ 	skip_video_pattern = true;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 08bd9c96b9b0..8e66b2e9d6af 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -965,6 +965,7 @@ static inline enum link_training_result perform_link_training_int(
+ static void initialize_training_settings(
+ 	 struct dc_link *link,
+ 	const struct dc_link_settings *link_setting,
++	const struct dc_link_training_overrides *overrides,
+ 	struct link_training_settings *lt_settings)
+ {
+ 	uint32_t lane;
+@@ -997,23 +998,23 @@ static void initialize_training_settings(
+ 	/* Initialize link spread */
+ 	if (link->dp_ss_off)
+ 		lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
+-	else if (link->preferred_training_settings.downspread != NULL)
++	else if (overrides->downspread != NULL)
+ 		lt_settings->link_settings.link_spread
+-			= *link->preferred_training_settings.downspread
++			= *overrides->downspread
+ 			? LINK_SPREAD_05_DOWNSPREAD_30KHZ
+ 			: LINK_SPREAD_DISABLED;
+ 	else
+ 		lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
+ 
+ 	/* Initialize lane settings overrides */
+-	if (link->preferred_training_settings.voltage_swing != NULL)
+-		lt_settings->voltage_swing = link->preferred_training_settings.voltage_swing;
++	if (overrides->voltage_swing != NULL)
++		lt_settings->voltage_swing = overrides->voltage_swing;
+ 
+-	if (link->preferred_training_settings.pre_emphasis != NULL)
+-		lt_settings->pre_emphasis = link->preferred_training_settings.pre_emphasis;
++	if (overrides->pre_emphasis != NULL)
++		lt_settings->pre_emphasis = overrides->pre_emphasis;
+ 
+-	if (link->preferred_training_settings.post_cursor2 != NULL)
+-		lt_settings->post_cursor2 = link->preferred_training_settings.post_cursor2;
++	if (overrides->post_cursor2 != NULL)
++		lt_settings->post_cursor2 = overrides->post_cursor2;
+ 
+ 	/* Initialize lane settings (VS/PE/PC2) */
+ 	for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
+@@ -1032,23 +1033,23 @@ static void initialize_training_settings(
+ 	}
+ 
+ 	/* Initialize training timings */
+-	if (link->preferred_training_settings.cr_pattern_time != NULL)
+-		lt_settings->cr_pattern_time = *link->preferred_training_settings.cr_pattern_time;
++	if (overrides->cr_pattern_time != NULL)
++		lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
+ 	else
+-		lt_settings->cr_pattern_time = 100;
++		lt_settings->cr_pattern_time = get_training_aux_rd_interval(link, 100);
+ 
+-	if (link->preferred_training_settings.eq_pattern_time != NULL)
+-		lt_settings->eq_pattern_time = *link->preferred_training_settings.eq_pattern_time;
++	if (overrides->eq_pattern_time != NULL)
++		lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
+ 	else
+ 		lt_settings->eq_pattern_time = get_training_aux_rd_interval(link, 400);
+ 
+-	if (link->preferred_training_settings.pattern_for_eq != NULL)
+-		lt_settings->pattern_for_eq = *link->preferred_training_settings.pattern_for_eq;
++	if (overrides->pattern_for_eq != NULL)
++		lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
+ 	else
+ 		lt_settings->pattern_for_eq = get_supported_tp(link);
+ 
+-	if (link->preferred_training_settings.enhanced_framing != NULL)
+-		lt_settings->enhanced_framing = *link->preferred_training_settings.enhanced_framing;
++	if (overrides->enhanced_framing != NULL)
++		lt_settings->enhanced_framing = *overrides->enhanced_framing;
+ 	else
+ 		lt_settings->enhanced_framing = 1;
+ }
+@@ -1139,7 +1140,11 @@ bool dc_link_dp_perform_link_training_skip_aux(
+ 	struct link_training_settings lt_settings;
+ 	enum dc_dp_training_pattern pattern_for_cr = DP_TRAINING_PATTERN_SEQUENCE_1;
+ 
+-	initialize_training_settings(link, link_setting, &lt_settings);
++	initialize_training_settings(
++			link,
++			link_setting,
++			&link->preferred_training_settings,
++			&lt_settings);
+ 
+ 	/* 1. Perform_clock_recovery_sequence. */
+ 
+@@ -1184,7 +1189,11 @@ enum link_training_result dc_link_dp_perform_link_training(
+ 	bool fec_enable;
+ #endif
+ 
+-	initialize_training_settings(link, link_setting, &lt_settings);
++	initialize_training_settings(
++			link,
++			link_setting,
++			&link->preferred_training_settings,
++			&lt_settings);
+ 
+ 	/* 1. set link rate, lane count and spread. */
+ 	dpcd_set_link_settings(link, &lt_settings);
+@@ -1247,6 +1256,146 @@ bool perform_link_training_with_retries(
+ 	return false;
+ }
+ 
++static enum clock_source_id get_clock_source_id(struct dc_link *link)
++{
++	enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
++	struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
++
++	if (dp_cs != NULL) {
++		dp_cs_id = dp_cs->id;
++	} else {
++		/*
++		 * dp clock source is not initialized for some reason.
++		 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
++		 */
++		ASSERT(dp_cs);
++	}
++
++	return dp_cs_id;
++}
++
++static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
++{
++	if (mst_enable == false &&
++		link->type == dc_connection_mst_branch) {
++		/* Disable MST on link. Use only local sink. */
++		dp_disable_link_phy_mst(link, link->connector_signal);
++
++		link->type = dc_connection_single;
++		link->local_sink = link->remote_sinks[0];
++		link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
++	} else if (mst_enable == true &&
++			link->type == dc_connection_single &&
++			link->remote_sinks[0] != NULL) {
++		/* Re-enable MST on link. */
++		dp_disable_link_phy(link, link->connector_signal);
++		dp_enable_mst_on_sink(link, true);
++
++		link->type = dc_connection_mst_branch;
++		link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
++	}
++}
++
++bool dc_link_dp_sync_lt_begin(struct dc_link *link)
++{
++	/* Begin Sync LT. During this time,
++	 * DPCD:600h must not be powered down.
++	 */
++	link->sync_lt_in_progress = true;
++
++	/*Clear any existing preferred settings.*/
++	memset(&link->preferred_training_settings, 0,
++		sizeof(struct dc_link_training_overrides));
++	memset(&link->preferred_link_setting, 0,
++		sizeof(struct dc_link_settings));
++
++	return true;
++}
++
++enum link_training_result dc_link_dp_sync_lt_attempt(
++    struct dc_link *link,
++    struct dc_link_settings *link_settings,
++    struct dc_link_training_overrides *lt_overrides)
++{
++	struct link_training_settings lt_settings;
++	enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
++	enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
++	enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	bool fec_enable = false;
++#endif
++
++	initialize_training_settings(
++		link,
++		link_settings,
++		lt_overrides,
++		&lt_settings);
++
++	/* Setup MST Mode */
++	if (lt_overrides->mst_enable)
++		set_dp_mst_mode(link, *lt_overrides->mst_enable);
++
++	/* Disable link */
++	dp_disable_link_phy(link, link->connector_signal);
++
++	/* Enable link */
++	dp_cs_id = get_clock_source_id(link);
++	dp_enable_link_phy(link, link->connector_signal,
++		dp_cs_id, link_settings);
++
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	/* Set FEC enable */
++	fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
++	dp_set_fec_ready(link, fec_enable);
++#endif
++
++	if (lt_overrides->alternate_scrambler_reset) {
++		if (*lt_overrides->alternate_scrambler_reset)
++			panel_mode = DP_PANEL_MODE_EDP;
++		else
++			panel_mode = DP_PANEL_MODE_DEFAULT;
++	} else
++		panel_mode = dp_get_panel_mode(link);
++
++	dp_set_panel_mode(link, panel_mode);
++
++	/* Attempt to train with given link training settings */
++
++	/* Set link rate, lane count and spread. */
++	dpcd_set_link_settings(link, &lt_settings);
++
++	/* 2. perform link training (set link training done
++	 *  to false is done as well)
++	 */
++	lt_status = perform_clock_recovery_sequence(link, &lt_settings);
++	if (lt_status == LINK_TRAINING_SUCCESS) {
++		lt_status = perform_channel_equalization_sequence(link,
++						&lt_settings);
++	}
++
++	/* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
++	/* 4. print status message*/
++	print_status_message(link, &lt_settings, lt_status);
++
++	return lt_status;
++}
++
++bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
++{
++	/* If input parameter is set, shut down phy.
++	 * Still shouldn't turn off dp_receiver (DPCD:600h)
++	 */
++	if (link_down == true) {
++		dp_disable_link_phy(link, link->connector_signal);
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++		dp_set_fec_ready(link, false);
++#endif
++	}
++
++	link->sync_lt_in_progress = false;
++	return true;
++}
++
+ static struct dc_link_settings get_max_link_cap(struct dc_link *link)
+ {
+ 	/* Set Default link settings */
+@@ -1401,7 +1550,6 @@ bool dp_verify_link_cap(
+ 	bool success;
+ 	bool skip_link_training;
+ 	bool skip_video_pattern;
+-	struct clock_source *dp_cs;
+ 	enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
+ 	enum link_training_result status;
+ 	union hpd_irq_data irq_data;
+@@ -1425,17 +1573,7 @@ bool dp_verify_link_cap(
+ 	/* disable PHY done possible by BIOS, will be done by driver itself */
+ 	dp_disable_link_phy(link, link->connector_signal);
+ 
+-	dp_cs = link->dc->res_pool->dp_clock_source;
+-
+-	if (dp_cs)
+-		dp_cs_id = dp_cs->id;
+-	else {
+-		/*
+-		 * dp clock source is not initialized for some reason.
+-		 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
+-		 */
+-		ASSERT(dp_cs);
+-	}
++	dp_cs_id = get_clock_source_id(link);
+ 
+ 	/* link training starts with the maximum common settings
+ 	 * supported by both sink and ASIC.
+@@ -2307,6 +2445,11 @@ bool is_mst_supported(struct dc_link *link)
+ 	union dpcd_rev rev;
+ 	union mstm_cap cap;
+ 
++	if (link->preferred_training_settings.mst_enable &&
++		*link->preferred_training_settings.mst_enable == false) {
++		return false;
++	}
++
+ 	rev.raw  = 0;
+ 	cap.raw  = 0;
+ 
+@@ -3158,6 +3301,94 @@ void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
+ 	core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
+ }
+ 
++void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
++{
++	union dpcd_edp_config edp_config_set;
++	bool panel_mode_edp = false;
++
++	memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
++
++	if (panel_mode != DP_PANEL_MODE_DEFAULT) {
++
++		switch (panel_mode) {
++		case DP_PANEL_MODE_EDP:
++		case DP_PANEL_MODE_SPECIAL:
++			panel_mode_edp = true;
++			break;
++
++		default:
++				break;
++		}
++
++		/*set edp panel mode in receiver*/
++		core_link_read_dpcd(
++			link,
++			DP_EDP_CONFIGURATION_SET,
++			&edp_config_set.raw,
++			sizeof(edp_config_set.raw));
++
++		if (edp_config_set.bits.PANEL_MODE_EDP
++			!= panel_mode_edp) {
++			enum ddc_result result = DDC_RESULT_UNKNOWN;
++
++			edp_config_set.bits.PANEL_MODE_EDP =
++			panel_mode_edp;
++			result = core_link_write_dpcd(
++				link,
++				DP_EDP_CONFIGURATION_SET,
++				&edp_config_set.raw,
++				sizeof(edp_config_set.raw));
++
++			ASSERT(result == DDC_RESULT_SUCESSFULL);
++		}
++	}
++	DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
++		 "eDP panel mode enabled: %d \n",
++		 link->link_index,
++		 link->dpcd_caps.panel_mode_edp,
++		 panel_mode_edp);
++}
++
++enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
++{
++	/* We need to explicitly check that connector
++	 * is not DP. Some Travis_VGA get reported
++	 * by video bios as DP.
++	 */
++	if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
++
++		switch (link->dpcd_caps.branch_dev_id) {
++		case DP_BRANCH_DEVICE_ID_2:
++			if (strncmp(
++				link->dpcd_caps.branch_dev_name,
++				DP_VGA_LVDS_CONVERTER_ID_2,
++				sizeof(
++				link->dpcd_caps.
++				branch_dev_name)) == 0) {
++					return DP_PANEL_MODE_SPECIAL;
++			}
++			break;
++		case DP_BRANCH_DEVICE_ID_3:
++			if (strncmp(link->dpcd_caps.branch_dev_name,
++				DP_VGA_LVDS_CONVERTER_ID_3,
++				sizeof(
++				link->dpcd_caps.
++				branch_dev_name)) == 0) {
++					return DP_PANEL_MODE_SPECIAL;
++			}
++			break;
++		default:
++			break;
++		}
++	}
++
++	if (link->dpcd_caps.panel_mode_edp) {
++		return DP_PANEL_MODE_EDP;
++	}
++
++	return DP_PANEL_MODE_DEFAULT;
++}
++
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ void dp_set_fec_ready(struct dc_link *link, bool ready)
+ {
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index 878f47b59d5a..daaff7319413 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -55,6 +55,9 @@ void dp_receiver_power_ctrl(struct dc_link *link, bool on)
+ 
+ 	state = on ? DP_POWER_STATE_D0 : DP_POWER_STATE_D3;
+ 
++	if (link->sync_lt_in_progress)
++		return;
++
+ 	core_link_write_dpcd(link, DP_SET_POWER, &state,
+ 			sizeof(state));
+ }
+@@ -245,46 +248,6 @@ void dp_set_hw_lane_settings(
+ 	encoder->funcs->dp_set_lane_settings(encoder, link_settings);
+ }
+ 
+-enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
+-{
+-	/* We need to explicitly check that connector
+-	 * is not DP. Some Travis_VGA get reported
+-	 * by video bios as DP.
+-	 */
+-	if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
+-
+-		switch (link->dpcd_caps.branch_dev_id) {
+-		case DP_BRANCH_DEVICE_ID_2:
+-			if (strncmp(
+-				link->dpcd_caps.branch_dev_name,
+-				DP_VGA_LVDS_CONVERTER_ID_2,
+-				sizeof(
+-				link->dpcd_caps.
+-				branch_dev_name)) == 0) {
+-				return DP_PANEL_MODE_SPECIAL;
+-			}
+-			break;
+-		case DP_BRANCH_DEVICE_ID_3:
+-			if (strncmp(link->dpcd_caps.branch_dev_name,
+-				DP_VGA_LVDS_CONVERTER_ID_3,
+-				sizeof(
+-				link->dpcd_caps.
+-				branch_dev_name)) == 0) {
+-				return DP_PANEL_MODE_SPECIAL;
+-			}
+-			break;
+-		default:
+-			break;
+-		}
+-	}
+-
+-	if (link->dpcd_caps.panel_mode_edp) {
+-		return DP_PANEL_MODE_EDP;
+-	}
+-
+-	return DP_PANEL_MODE_DEFAULT;
+-}
+-
+ void dp_set_hw_test_pattern(
+ 	struct dc_link *link,
+ 	enum dp_test_pattern test_pattern,
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+index efa7a47f6b7e..ef79a686e4c2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+@@ -128,7 +128,10 @@ struct dc_link_training_overrides {
+ 	enum dc_link_spread *downspread;
+ 	bool *alternate_scrambler_reset;
+ 	bool *enhanced_framing;
++	bool *mst_enable;
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	bool *fec_enable;
++#endif
+ };
+ 
+ union dpcd_rev {
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
+index d6ff5af70c71..9ea75db3484e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
+@@ -84,6 +84,7 @@ struct dc_link {
+ 	bool dp_ss_off;
+ 	bool link_state_valid;
+ 	bool aux_access_disabled;
++	bool sync_lt_in_progress;
+ 
+ 	/* caps is the same as reported_link_cap. link_traing use
+ 	 * reported_link_cap. Will clean up.  TODO
+@@ -228,6 +229,15 @@ enum link_training_result dc_link_dp_perform_link_training(
+ 	const struct dc_link_settings *link_setting,
+ 	bool skip_video_pattern);
+ 
++bool dc_link_dp_sync_lt_begin(struct dc_link *link);
++
++enum link_training_result dc_link_dp_sync_lt_attempt(
++	struct dc_link *link,
++	struct dc_link_settings *link_setting,
++	struct dc_link_training_overrides *lt_settings);
++
++bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down);
++
+ void dc_link_dp_enable_hpd(const struct dc_link *link);
+ 
+ void dc_link_dp_disable_hpd(const struct dc_link *link);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+index c5293f9508fa..2ef23963e1f7 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+@@ -62,6 +62,9 @@ bool is_dp_active_dongle(const struct dc_link *link);
+ 
+ void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
+ 
++enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
++void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);
++
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ void dp_set_fec_ready(struct dc_link *link, bool ready);
+ void dp_set_fec_enable(struct dc_link *link, bool enable);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+index 3680846674e8..4eff5d38a2f9 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+@@ -72,8 +72,6 @@ void dp_set_hw_test_pattern(
+ 	uint8_t *custom_pattern,
+ 	uint32_t custom_pattern_size);
+ 
+-enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
+-
+ void dp_retrain_link_dp_test(struct dc_link *link,
+ 		struct dc_link_settings *link_setting,
+ 		bool skip_video_pattern);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3404-drm-amd-display-make-firmware-info-only-load-once-du.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3404-drm-amd-display-make-firmware-info-only-load-once-du.patch
new file mode 100644
index 00000000..c806b8f4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3404-drm-amd-display-make-firmware-info-only-load-once-du.patch
@@ -0,0 +1,455 @@
+From c80b8af508e609586c2bb2085e220bc12873ce99 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Fri, 12 Jul 2019 15:06:06 -0400
+Subject: [PATCH 3404/4256] drm/amd/display: make firmware info only load once
+ during dc_bios create
+
+Currently every time DC wants to access firmware info we make a call
+into VBIOS. This makes no sense as there is nothing that can change
+runtime inside fw info and can cause issues when calling unstable
+bios during bringup.
+
+This change eliminate this behavior by only calling bios once for fw
+info and keeping it stored as part of dc_bios.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Chris Park <Chris.Park@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/bios/bios_parser.c |  3 +-
+ .../drm/amd/display/dc/bios/bios_parser2.c    |  3 +-
+ .../display/dc/clk_mgr/dce100/dce_clk_mgr.c   | 17 ++++------
+ .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c    |  6 ++--
+ .../gpu/drm/amd/display/dc/core/dc_resource.c |  7 ++--
+ .../gpu/drm/amd/display/dc/dc_bios_types.h    |  5 ++-
+ .../drm/amd/display/dc/dce/dce_clock_source.c | 32 +++++++------------
+ .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c   | 13 +-------
+ .../amd/display/dc/dce100/dce100_resource.c   |  4 +--
+ .../amd/display/dc/dce110/dce110_resource.c   |  4 +--
+ .../drm/amd/display/dc/dce80/dce80_resource.c | 12 ++-----
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  9 +++---
+ 12 files changed, 36 insertions(+), 79 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+index a4c97d32e751..207f6084525c 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+@@ -2794,8 +2794,6 @@ static const struct dc_vbios_funcs vbios_funcs = {
+ 
+ 	.get_device_tag = bios_parser_get_device_tag,
+ 
+-	.get_firmware_info = bios_parser_get_firmware_info,
+-
+ 	.get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
+ 
+ 	.get_ss_entry_number = bios_parser_get_ss_entry_number,
+@@ -2920,6 +2918,7 @@ static bool bios_parser_construct(
+ 	dal_bios_parser_init_cmd_tbl_helper(&bp->cmd_helper, dce_version);
+ 
+ 	bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
++	bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
+ 
+ 	return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index 99f40b8a231c..c9f65c4df530 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -1879,8 +1879,6 @@ static const struct dc_vbios_funcs vbios_funcs = {
+ 
+ 	.get_device_tag = bios_parser_get_device_tag,
+ 
+-	.get_firmware_info = bios_parser_get_firmware_info,
+-
+ 	.get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
+ 
+ 	.get_ss_entry_number = bios_parser_get_ss_entry_number,
+@@ -1996,6 +1994,7 @@ static bool bios_parser_construct(
+ 	dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
+ 
+ 	bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
++	bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
+ 
+ 	return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+index 6a0dd78ab65a..7634982a6bb0 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+@@ -270,18 +270,12 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)
+ {
+ 	struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;
+ 	struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
+-	struct integrated_info info = { { { 0 } } };
+-	struct dc_firmware_info fw_info = { { 0 } };
+ 	int i;
+ 
+ 	if (bp->integrated_info)
+-		info = *bp->integrated_info;
+-
+-	clk_mgr_dce->dentist_vco_freq_khz = info.dentist_vco_freq;
++		clk_mgr_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
+ 	if (clk_mgr_dce->dentist_vco_freq_khz == 0) {
+-		bp->funcs->get_firmware_info(bp, &fw_info);
+-		clk_mgr_dce->dentist_vco_freq_khz =
+-			fw_info.smu_gpu_pll_output_freq;
++		clk_mgr_dce->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
+ 		if (clk_mgr_dce->dentist_vco_freq_khz == 0)
+ 			clk_mgr_dce->dentist_vco_freq_khz = 3600000;
+ 	}
+@@ -314,9 +308,10 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)
+ 
+ 		/*Do not allow bad VBIOS/SBIOS to override with invalid values,
+ 		 * check for > 100MHz*/
+-		if (info.disp_clk_voltage[i].max_supported_clk >= 100000)
+-			clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =
+-				info.disp_clk_voltage[i].max_supported_clk;
++		if (bp->integrated_info)
++			if (bp->integrated_info->disp_clk_voltage[i].max_supported_clk >= 100000)
++				clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =
++					bp->integrated_info->disp_clk_voltage[i].max_supported_clk;
+ 	}
+ 
+ 	if (!debug->disable_dfs_bypass && bp->integrated_info)
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+index ed53b483f838..ad1478378f16 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+@@ -248,7 +248,6 @@ void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_
+ {
+ 	struct dc_debug_options *debug = &ctx->dc->debug;
+ 	struct dc_bios *bp = ctx->dc_bios;
+-	struct dc_firmware_info fw_info = { { 0 } };
+ 
+ 	clk_mgr->base.ctx = ctx;
+ 	clk_mgr->pp_smu = pp_smu;
+@@ -264,9 +263,8 @@ void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_
+ 
+ 	if (bp->integrated_info)
+ 		clk_mgr->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
+-	if (clk_mgr->dentist_vco_freq_khz == 0) {
+-		bp->funcs->get_firmware_info(bp, &fw_info);
+-		clk_mgr->dentist_vco_freq_khz = fw_info.smu_gpu_pll_output_freq;
++	if (bp->fw_info_valid && clk_mgr->dentist_vco_freq_khz == 0) {
++		clk_mgr->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
+ 		if (clk_mgr->dentist_vco_freq_khz == 0)
+ 			clk_mgr->dentist_vco_freq_khz = 3600000;
+ 	}
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 43bb4c933da7..5f2f2c7e7445 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -170,12 +170,9 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
+ 		break;
+ 	}
+ 	if (res_pool != NULL) {
+-		struct dc_firmware_info fw_info = { { 0 } };
+-
+-		if (dc->ctx->dc_bios->funcs->get_firmware_info(dc->ctx->dc_bios,
+-				&fw_info) == BP_RESULT_OK) {
++		if (dc->ctx->dc_bios->fw_info_valid) {
+ 			res_pool->ref_clocks.xtalin_clock_inKhz =
+-				fw_info.pll_info.crystal_frequency;
++				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
+ 			/* initialize with firmware data first, no all
+ 			 * ASIC have DCCG SW component. FPGA or
+ 			 * simulation need initialization of
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+index 78c3b300ec45..b1dd0d60d98e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+@@ -61,9 +61,6 @@ struct dc_vbios_funcs {
+ 		struct graphics_object_id connector_object_id,
+ 		uint32_t device_tag_index,
+ 		struct connector_device_tag_info *info);
+-	enum bp_result (*get_firmware_info)(
+-		struct dc_bios *bios,
+-		struct dc_firmware_info *info);
+ 	enum bp_result (*get_spread_spectrum_info)(
+ 		struct dc_bios *bios,
+ 		enum as_signal_type signal,
+@@ -152,6 +149,8 @@ struct dc_bios {
+ 	struct dc_context *ctx;
+ 	const struct bios_registers *regs;
+ 	struct integrated_info *integrated_info;
++	struct dc_firmware_info fw_info;
++	bool fw_info_valid;
+ };
+ 
+ #endif /* DC_BIOS_TYPES_H */
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+index c72aed35f4db..464d7c3830ef 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+@@ -1232,37 +1232,35 @@ static bool calc_pll_max_vco_construct(
+ 			struct calc_pll_clock_source_init_data *init_data)
+ {
+ 	uint32_t i;
+-	struct dc_firmware_info fw_info = { { 0 } };
++	struct dc_firmware_info *fw_info = &init_data->bp->fw_info;
+ 	if (calc_pll_cs == NULL ||
+ 			init_data == NULL ||
+ 			init_data->bp == NULL)
+ 		return false;
+ 
+-	if (init_data->bp->funcs->get_firmware_info(
+-				init_data->bp,
+-				&fw_info) != BP_RESULT_OK)
++	if (init_data->bp->fw_info_valid)
+ 		return false;
+ 
+ 	calc_pll_cs->ctx = init_data->ctx;
+-	calc_pll_cs->ref_freq_khz = fw_info.pll_info.crystal_frequency;
++	calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency;
+ 	calc_pll_cs->min_vco_khz =
+-			fw_info.pll_info.min_output_pxl_clk_pll_frequency;
++			fw_info->pll_info.min_output_pxl_clk_pll_frequency;
+ 	calc_pll_cs->max_vco_khz =
+-			fw_info.pll_info.max_output_pxl_clk_pll_frequency;
++			fw_info->pll_info.max_output_pxl_clk_pll_frequency;
+ 
+ 	if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0)
+ 		calc_pll_cs->max_pll_input_freq_khz =
+ 			init_data->max_override_input_pxl_clk_pll_freq_khz;
+ 	else
+ 		calc_pll_cs->max_pll_input_freq_khz =
+-			fw_info.pll_info.max_input_pxl_clk_pll_frequency;
++			fw_info->pll_info.max_input_pxl_clk_pll_frequency;
+ 
+ 	if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0)
+ 		calc_pll_cs->min_pll_input_freq_khz =
+ 			init_data->min_override_input_pxl_clk_pll_freq_khz;
+ 	else
+ 		calc_pll_cs->min_pll_input_freq_khz =
+-			fw_info.pll_info.min_input_pxl_clk_pll_frequency;
++			fw_info->pll_info.min_input_pxl_clk_pll_frequency;
+ 
+ 	calc_pll_cs->min_pix_clock_pll_post_divider =
+ 			init_data->min_pix_clk_pll_post_divider;
+@@ -1314,7 +1312,6 @@ bool dce110_clk_src_construct(
+ 	const struct dce110_clk_src_shift *cs_shift,
+ 	const struct dce110_clk_src_mask *cs_mask)
+ {
+-	struct dc_firmware_info fw_info = { { 0 } };
+ 	struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi;
+ 	struct calc_pll_clock_source_init_data calc_pll_cs_init_data;
+ 
+@@ -1327,14 +1324,12 @@ bool dce110_clk_src_construct(
+ 	clk_src->cs_shift = cs_shift;
+ 	clk_src->cs_mask = cs_mask;
+ 
+-	if (clk_src->bios->funcs->get_firmware_info(
+-			clk_src->bios, &fw_info) != BP_RESULT_OK) {
++	if (!clk_src->bios->fw_info_valid) {
+ 		ASSERT_CRITICAL(false);
+ 		goto unexpected_failure;
+ 	}
+ 
+-	clk_src->ext_clk_khz =
+-			fw_info.external_clock_source_frequency_for_dp;
++	clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
+ 
+ 	/* structure normally used with PLL ranges from ATOMBIOS; DS on by default */
+ 	calc_pll_cs_init_data.bp = bios;
+@@ -1374,7 +1369,7 @@ bool dce110_clk_src_construct(
+ 			FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
+ 	calc_pll_cs_init_data_hdmi.ctx = ctx;
+ 
+-	clk_src->ref_freq_khz = fw_info.pll_info.crystal_frequency;
++	clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency;
+ 
+ 	if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL)
+ 		return true;
+@@ -1417,8 +1412,6 @@ bool dce112_clk_src_construct(
+ 	const struct dce110_clk_src_shift *cs_shift,
+ 	const struct dce110_clk_src_mask *cs_mask)
+ {
+-	struct dc_firmware_info fw_info = { { 0 } };
+-
+ 	clk_src->base.ctx = ctx;
+ 	clk_src->bios = bios;
+ 	clk_src->base.id = id;
+@@ -1428,13 +1421,12 @@ bool dce112_clk_src_construct(
+ 	clk_src->cs_shift = cs_shift;
+ 	clk_src->cs_mask = cs_mask;
+ 
+-	if (clk_src->bios->funcs->get_firmware_info(
+-			clk_src->bios, &fw_info) != BP_RESULT_OK) {
++	if (!clk_src->bios->fw_info_valid) {
+ 		ASSERT_CRITICAL(false);
+ 		return false;
+ 	}
+ 
+-	clk_src->ext_clk_khz = fw_info.external_clock_source_frequency_for_dp;
++	clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
+ 
+ 	return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+index b2786a704708..caace5229826 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+@@ -96,17 +96,6 @@ static uint32_t get_hw_buffer_available_size(
+ 			dce_i2c_hw->buffer_used_bytes;
+ }
+ 
+-uint32_t get_reference_clock(
+-		struct dc_bios *bios)
+-{
+-	struct dc_firmware_info info = { { 0 } };
+-
+-	if (bios->funcs->get_firmware_info(bios, &info) != BP_RESULT_OK)
+-		return 0;
+-
+-	return info.pll_info.crystal_frequency;
+-}
+-
+ static uint32_t get_speed(
+ 	const struct dce_i2c_hw *dce_i2c_hw)
+ {
+@@ -629,7 +618,7 @@ void dce_i2c_hw_construct(
+ {
+ 	dce_i2c_hw->ctx = ctx;
+ 	dce_i2c_hw->engine_id = engine_id;
+-	dce_i2c_hw->reference_frequency = get_reference_clock(ctx->dc_bios) >> 1;
++	dce_i2c_hw->reference_frequency = (ctx->dc_bios->fw_info.pll_info.crystal_frequency) >> 1;
+ 	dce_i2c_hw->regs = regs;
+ 	dce_i2c_hw->shifts = shifts;
+ 	dce_i2c_hw->masks = masks;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+index bb199534ea3b..9de2a0bda38a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+@@ -907,7 +907,6 @@ static bool construct(
+ {
+ 	unsigned int i;
+ 	struct dc_context *ctx = dc->ctx;
+-	struct dc_firmware_info info;
+ 	struct dc_bios *bp;
+ 
+ 	ctx->dc_bios->regs = &bios_regs;
+@@ -918,8 +917,7 @@ static bool construct(
+ 
+ 	bp = ctx->dc_bios;
+ 
+-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
+-		info.external_clock_source_frequency_for_dp != 0) {
++	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
+ 		pool->base.dp_clock_source =
+ 				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index ae89721c3a99..dc1764f2f8c2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -1272,7 +1272,6 @@ static bool construct(
+ {
+ 	unsigned int i;
+ 	struct dc_context *ctx = dc->ctx;
+-	struct dc_firmware_info info;
+ 	struct dc_bios *bp;
+ 
+ 	ctx->dc_bios->regs = &bios_regs;
+@@ -1298,8 +1297,7 @@ static bool construct(
+ 
+ 	bp = ctx->dc_bios;
+ 
+-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
+-		info.external_clock_source_frequency_for_dp != 0) {
++	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
+ 		pool->base.dp_clock_source =
+ 				dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+index 2f224e1ae5f2..8e4effb1f439 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -877,7 +877,6 @@ static bool dce80_construct(
+ {
+ 	unsigned int i;
+ 	struct dc_context *ctx = dc->ctx;
+-	struct dc_firmware_info info;
+ 	struct dc_bios *bp;
+ 
+ 	ctx->dc_bios->regs = &bios_regs;
+@@ -903,8 +902,7 @@ static bool dce80_construct(
+ 
+ 	bp = ctx->dc_bios;
+ 
+-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
+-		info.external_clock_source_frequency_for_dp != 0) {
++	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
+ 		pool->base.dp_clock_source =
+ 				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+ 
+@@ -1076,7 +1074,6 @@ static bool dce81_construct(
+ {
+ 	unsigned int i;
+ 	struct dc_context *ctx = dc->ctx;
+-	struct dc_firmware_info info;
+ 	struct dc_bios *bp;
+ 
+ 	ctx->dc_bios->regs = &bios_regs;
+@@ -1102,8 +1099,7 @@ static bool dce81_construct(
+ 
+ 	bp = ctx->dc_bios;
+ 
+-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
+-		info.external_clock_source_frequency_for_dp != 0) {
++	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
+ 		pool->base.dp_clock_source =
+ 				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+ 
+@@ -1275,7 +1271,6 @@ static bool dce83_construct(
+ {
+ 	unsigned int i;
+ 	struct dc_context *ctx = dc->ctx;
+-	struct dc_firmware_info info;
+ 	struct dc_bios *bp;
+ 
+ 	ctx->dc_bios->regs = &bios_regs;
+@@ -1301,8 +1296,7 @@ static bool dce83_construct(
+ 
+ 	bp = ctx->dc_bios;
+ 
+-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
+-		info.external_clock_source_frequency_for_dp != 0) {
++	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
+ 		pool->base.dp_clock_source =
+ 				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 27d143418cc7..fb7cde33c88b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -568,7 +568,6 @@ static void dcn20_init_hw(struct dc *dc)
+ 	struct dc_bios *dcb = dc->ctx->dc_bios;
+ 	struct resource_pool *res_pool = dc->res_pool;
+ 	struct dc_state  *context = dc->current_state;
+-	struct dc_firmware_info fw_info = { { 0 } };
+ 
+ 	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
+ 		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
+@@ -592,15 +591,15 @@ static void dcn20_init_hw(struct dc *dc)
+ 	} else {
+ 		if (!dcb->funcs->is_accelerated_mode(dcb)) {
+ 			bios_golden_init(dc);
+-			if (dc->ctx->dc_bios->funcs->get_firmware_info(
+-					dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
+-				res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency;
++			if (dc->ctx->dc_bios->fw_info_valid) {
++				res_pool->ref_clocks.xtalin_clock_inKhz =
++						dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
+ 
+ 				if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 					if (res_pool->dccg && res_pool->hubbub) {
+ 
+ 						(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+-								fw_info.pll_info.crystal_frequency,
++								dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
+ 								&res_pool->ref_clocks.dccg_ref_clock_inKhz);
+ 
+ 						(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3405-drm-amd-display-fixup-DPP-programming-sequence.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3405-drm-amd-display-fixup-DPP-programming-sequence.patch
new file mode 100644
index 00000000..3b4f39a7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3405-drm-amd-display-fixup-DPP-programming-sequence.patch
@@ -0,0 +1,395 @@
+From 7e39c65edcacc447951589bb95d33391f9c459a9 Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Mon, 15 Jul 2019 10:41:47 -0400
+Subject: [PATCH 3405/4256] drm/amd/display: fixup DPP programming sequence
+
+[why]
+DC does not correct account for the fact that DPP DTO is double buffered while DPP ref is not.
+This means that when DPP ref clock is lowered when it's "safe to lower", the DPP blocks that need
+an increased divider will temporarily have actual DPP clock drop below minimum while DTO
+double buffering takes effect.  This results in temporary underflow.
+
+[how]
+To fix this, DPP clock cannot be programmed atomically, but rather be broken up into the DTO and the
+ref.  Each has a separate "safe to lower" logic.  When doing "prepare" the ref and dividers may only increase.
+When doing "optimize", both may decrease.  It is guaranteed that we won't exceed max DPP clock because
+we do not use dividers larger than 1.
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  | 133 +++++++++++++-----
+ drivers/gpu/drm/amd/display/dc/core/dc.c      |   3 +
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   3 +-
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c |  31 +++-
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h |   2 +-
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c |   2 +-
+ .../gpu/drm/amd/display/dc/inc/core_types.h   |   1 -
+ .../amd/display/dc/inc/hw/clk_mgr_internal.h  |  10 +-
+ drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |   3 +-
+ 9 files changed, 141 insertions(+), 47 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index 7ff0396956b3..24775ab81216 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -104,7 +104,6 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
+ {
+ 	int i;
+ 
+-	clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
+ 	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
+ 		int dpp_inst, dppclk_khz;
+ 
+@@ -114,28 +113,75 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
+ 		dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
+ 		dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
+ 		clk_mgr->dccg->funcs->update_dpp_dto(
+-				clk_mgr->dccg, dpp_inst, dppclk_khz);
++				clk_mgr->dccg, dpp_inst, dppclk_khz, false);
+ 	}
+ }
+ 
+-void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr)
++static void update_global_dpp_clk(struct clk_mgr_internal *clk_mgr, unsigned int khz)
+ {
+ 	int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+-			* clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
+-	int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+-			* clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
++			* clk_mgr->dentist_vco_freq_khz / khz;
+ 
+ 	uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
+-	uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
+ 
+-	REG_UPDATE(DENTIST_DISPCLK_CNTL,
+-			DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
+-//	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100);
+ 	REG_UPDATE(DENTIST_DISPCLK_CNTL,
+ 			DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);
+ 	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
+ }
+ 
++static void update_display_clk(struct clk_mgr_internal *clk_mgr, unsigned int khz)
++{
++	int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
++			* clk_mgr->dentist_vco_freq_khz / khz;
++
++	uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
++
++	REG_UPDATE(DENTIST_DISPCLK_CNTL,
++			DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
++}
++
++static void request_voltage_and_program_disp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz)
++{
++	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
++	struct dc *dc = clk_mgr_base->ctx->dc;
++	struct pp_smu_funcs_nv *pp_smu = NULL;
++	bool going_up = clk_mgr->base.clks.dispclk_khz < khz;
++
++	if (dc->res_pool->pp_smu)
++		pp_smu = &dc->res_pool->pp_smu->nv_funcs;
++
++	clk_mgr->base.clks.dispclk_khz = khz;
++
++	if (going_up && pp_smu && pp_smu->set_voltage_by_freq)
++		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
++
++	update_display_clk(clk_mgr, khz);
++
++	if (!going_up && pp_smu && pp_smu->set_voltage_by_freq)
++		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
++}
++
++static void request_voltage_and_program_global_dpp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz)
++{
++	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
++	struct dc *dc = clk_mgr_base->ctx->dc;
++	struct pp_smu_funcs_nv *pp_smu = NULL;
++	bool going_up = clk_mgr->base.clks.dppclk_khz < khz;
++
++	if (dc->res_pool->pp_smu)
++		pp_smu = &dc->res_pool->pp_smu->nv_funcs;
++
++	clk_mgr->base.clks.dppclk_khz = khz;
++	clk_mgr->dccg->ref_dppclk = khz;
++
++	if (going_up && pp_smu && pp_smu->set_voltage_by_freq)
++		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);
++
++	update_global_dpp_clk(clk_mgr, khz);
++
++	if (!going_up && pp_smu && pp_smu->set_voltage_by_freq)
++		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);
++}
+ 
+ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+ 			struct dc_state *context,
+@@ -146,12 +192,11 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+ 	struct dc *dc = clk_mgr_base->ctx->dc;
+ 	struct pp_smu_funcs_nv *pp_smu = NULL;
+ 	int display_count;
+-	bool update_dppclk = false;
+ 	bool update_dispclk = false;
+ 	bool enter_display_off = false;
+-	bool dpp_clock_lowered = false;
+ 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
+ 	bool force_reset = false;
++	int i;
+ 
+ 	if (clk_mgr_base->clks.dispclk_khz == 0 ||
+ 		dc->debug.force_clock_mode & 0x1) {
+@@ -177,6 +222,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+ 			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
+ 	}
+ 
++
+ 	if (dc->debug.force_min_dcfclk_mhz > 0)
+ 		new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
+ 				new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
+@@ -202,10 +248,12 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+ 
+ 	if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
+ 		clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
++
+ 		clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support;
+ 		if (pp_smu && pp_smu->set_pstate_handshake_support)
+ 			pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);
+ 	}
++	clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
+ 
+ 	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
+ 		clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
+@@ -213,35 +261,48 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+ 			pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000);
+ 	}
+ 
+-	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
+-		if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
+-			dpp_clock_lowered = true;
+-		clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
++	if (dc->config.forced_clocks == false) {
++		// First update display clock
++		if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz))
++			request_voltage_and_program_disp_clk(clk_mgr_base, new_clocks->dispclk_khz);
+ 
+-		if (pp_smu && pp_smu->set_voltage_by_freq)
+-			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);
++		// Updating DPP clock requires some more logic
++		if (!safe_to_lower) {
++			// For pre-programming, we need to make sure any DPP clock that will go up has to go up
+ 
+-		update_dppclk = true;
+-	}
++			// First raise the global reference if needed
++			if (new_clocks->dppclk_khz > clk_mgr_base->clks.dppclk_khz)
++				request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz);
+ 
+-	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
+-		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
+-		if (pp_smu && pp_smu->set_voltage_by_freq)
+-			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
++			// Then raise any dividers that need raising
++			for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
++				int dpp_inst, dppclk_khz;
+ 
+-		update_dispclk = true;
+-	}
+-	if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
+-		if (dpp_clock_lowered) {
+-			// if clock is being lowered, increase DTO before lowering refclk
+-			dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
+-			dcn20_update_clocks_update_dentist(clk_mgr);
++				if (!context->res_ctx.pipe_ctx[i].plane_state)
++					continue;
++
++				dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
++				dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
++
++				clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, true);
++			}
+ 		} else {
+-			// if clock is being raised, increase refclk before lowering DTO
+-			if (update_dppclk || update_dispclk)
+-				dcn20_update_clocks_update_dentist(clk_mgr);
+-			if (update_dppclk)
+-				dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
++			// For post-programming, we can lower ref clk if needed, and unconditionally set all the DTOs
++
++			if (new_clocks->dppclk_khz < clk_mgr_base->clks.dppclk_khz)
++				request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz);
++
++			for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
++				int dpp_inst, dppclk_khz;
++
++				if (!context->res_ctx.pipe_ctx[i].plane_state)
++					continue;
++
++				dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
++				dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
++
++				clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, false);
++			}
+ 		}
+ 	}
+ 	if (update_dispclk &&
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 51653834dab6..409d9a02f613 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1612,6 +1612,9 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
+ 		for (i = 0; i < surface_count; i++)
+ 			updates[i].surface->update_flags.raw = 0xFFFFFFFF;
+ 
++	if (type == UPDATE_TYPE_FAST && memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0)
++		dc->optimized_required = true;
++
+ 	return type;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 84980d4f324d..627684213461 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2153,7 +2153,8 @@ void update_dchubp_dpp(
+ 			dc->res_pool->dccg->funcs->update_dpp_dto(
+ 					dc->res_pool->dccg,
+ 					dpp->inst,
+-					pipe_ctx->plane_res.bw.dppclk_khz);
++					pipe_ctx->plane_res.bw.dppclk_khz,
++					false);
+ 		else
+ 			dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
+ 						dc->clk_mgr->clks.dispclk_khz / 2 :
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
+index 23362dd4b6d3..f9b99f8cfc31 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
+@@ -42,12 +42,16 @@
+ #define DC_LOGGER \
+ 	dccg->ctx->logger
+ 
+-void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
++void dccg2_update_dpp_dto(struct dccg *dccg,
++		int dpp_inst,
++		int req_dppclk,
++		bool reduce_divider_only)
+ {
+ 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+ 
+ 	if (dccg->ref_dppclk && req_dppclk) {
+ 		int ref_dppclk = dccg->ref_dppclk;
++		int current_phase, current_modulo;
+ 
+ 		ASSERT(req_dppclk <= ref_dppclk);
+ 		/* need to clamp to 8 bits */
+@@ -59,9 +63,28 @@ void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
+ 			if (req_dppclk > ref_dppclk)
+ 				req_dppclk = ref_dppclk;
+ 		}
+-		REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
+-				DPPCLK0_DTO_PHASE, req_dppclk,
+-				DPPCLK0_DTO_MODULO, ref_dppclk);
++
++		REG_GET_2(DPPCLK_DTO_PARAM[dpp_inst],
++				DPPCLK0_DTO_PHASE, &current_phase,
++				DPPCLK0_DTO_MODULO, &current_modulo);
++
++		if (reduce_divider_only) {
++			// requested phase/modulo greater than current
++			if (req_dppclk * current_modulo >= current_phase * ref_dppclk) {
++				REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
++						DPPCLK0_DTO_PHASE, req_dppclk,
++						DPPCLK0_DTO_MODULO, ref_dppclk);
++			} else {
++				REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
++						DPPCLK0_DTO_PHASE, current_phase,
++						DPPCLK0_DTO_MODULO, current_modulo);
++			}
++		} else {
++			REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
++					DPPCLK0_DTO_PHASE, req_dppclk,
++					DPPCLK0_DTO_MODULO, ref_dppclk);
++		}
++
+ 		REG_UPDATE(DPPCLK_DTO_CTRL,
+ 				DPPCLK_DTO_ENABLE[dpp_inst], 1);
+ 	} else {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+index 2205cb0204e7..74a074a873cd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+@@ -97,7 +97,7 @@ struct dcn_dccg {
+ 	const struct dccg_mask *dccg_mask;
+ };
+ 
+-void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
++void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk, bool raise_divider_only);
+ 
+ void dccg2_get_dccg_ref_freq(struct dccg *dccg,
+ 		unsigned int xtalin_freq_inKhz,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 291846cc4f21..a26541bafc75 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2480,7 +2480,7 @@ void dcn20_calculate_dlg_params(
+ 	context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
+ 	context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
+ 	context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
+-	context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
++	context->bw_ctx.bw.dcn.clk.fclk_khz = 0;
+ 	context->bw_ctx.bw.dcn.clk.p_state_change_support =
+ 		context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
+ 							!= dm_dram_clock_change_unsupported;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index a148ffde8b12..1d66c4b09612 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -228,7 +228,6 @@ struct resource_pool {
+ 
+ struct dcn_fe_bandwidth {
+ 	int dppclk_khz;
+-
+ };
+ 
+ struct stream_resource {
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+index 4b5505fa980c..9b6c885c0bba 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+@@ -279,8 +279,14 @@ static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_cl
+ 
+ static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support)
+ {
+-	// Whenever we are transitioning pstate support, we always want to notify prior to committing state
+-	return (calc_support != cur_support) ? !safe_to_lower : false;
++	if (cur_support != calc_support) {
++		if (calc_support == true && safe_to_lower)
++			return true;
++		else if (calc_support == false && !safe_to_lower)
++			return true;
++	}
++
++	return false;
+ }
+ 
+ int clk_mgr_helper_get_active_display_cnt(
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+index 05ee5295d2c1..d8e744f366e5 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+@@ -38,7 +38,8 @@ struct dccg {
+ struct dccg_funcs {
+ 	void (*update_dpp_dto)(struct dccg *dccg,
+ 			int dpp_inst,
+-			int req_dppclk);
++			int req_dppclk,
++			bool reduce_divider_only);
+ 	void (*get_dccg_ref_freq)(struct dccg *dccg,
+ 			unsigned int xtalin_freq_inKhz,
+ 			unsigned int *dccg_ref_freq_inKhz);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3406-drm-amd-display-Add-work-around-option-to-skip-DCN20.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3406-drm-amd-display-Add-work-around-option-to-skip-DCN20.patch
new file mode 100644
index 00000000..6ac92127
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3406-drm-amd-display-Add-work-around-option-to-skip-DCN20.patch
@@ -0,0 +1,48 @@
+From 02bea9d0e8cb12d2f3a463e99723a537b44481a2 Mon Sep 17 00:00:00 2001
+From: Jaehyun Chung <jaehyun.chung@amd.com>
+Date: Mon, 15 Jul 2019 17:35:56 -0400
+Subject: [PATCH 3406/4256] drm/amd/display: Add work-around option to skip
+ DCN20 clock updates
+
+[Why] Auto Overclock Memory fails for some systems that don't support
+p-state.
+
+[How] Implement the workaround, and it's corresponding enable flag.
+
+Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
+Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 3 +++
+ drivers/gpu/drm/amd/display/dc/dc.h                          | 1 +
+ 2 files changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index 24775ab81216..3e8ac303bd52 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -198,6 +198,9 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+ 	bool force_reset = false;
+ 	int i;
+ 
++	if (dc->work_arounds.skip_clock_update)
++		return;
++
+ 	if (clk_mgr_base->clks.dispclk_khz == 0 ||
+ 		dc->debug.force_clock_mode & 0x1) {
+ 		//this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3.
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 110055142ac5..f8cb2745dc09 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -125,6 +125,7 @@ struct dc_bug_wa {
+ 	bool no_connect_phy_config;
+ 	bool dedcn20_305_wa;
+ 	struct display_mode_lib alternate_dml;
++	bool skip_clock_update;
+ };
+ #endif
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3407-drm-amd-display-refactor-gpio-to-allocate-hw_contain.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3407-drm-amd-display-refactor-gpio-to-allocate-hw_contain.patch
new file mode 100644
index 00000000..dc20f736
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3407-drm-amd-display-refactor-gpio-to-allocate-hw_contain.patch
@@ -0,0 +1,812 @@
+From c88c69c8487f0424fa6a08b35d3a92fa4b01cf91 Mon Sep 17 00:00:00 2001
+From: Su Sung Chung <Su.Chung@amd.com>
+Date: Mon, 8 Jul 2019 11:31:39 -0400
+Subject: [PATCH 3407/4256] drm/amd/display: refactor gpio to allocate
+ hw_container in constructor
+
+[why]
+if dynamic allocation fails during gpio_open, it will cause crash due to
+page fault.
+
+[how]
+handle allocation when gpio object gets created and prevent from calling
+gpio_open if allocation failed
+
+Signed-off-by: Su Sung Chung <Su.Chung@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../dc/gpio/dce110/hw_factory_dce110.c        | 18 +++--
+ .../dc/gpio/dce120/hw_factory_dce120.c        | 14 ++--
+ .../display/dc/gpio/dce80/hw_factory_dce80.c  | 14 ++--
+ .../display/dc/gpio/dcn10/hw_factory_dcn10.c  | 12 +--
+ .../display/dc/gpio/dcn20/hw_factory_dcn20.c  | 12 +--
+ .../dc/gpio/diagnostics/hw_factory_diag.c     |  9 +--
+ .../gpu/drm/amd/display/dc/gpio/gpio_base.c   | 74 ++++++++++++++++++-
+ .../drm/amd/display/dc/gpio/gpio_service.c    | 51 ++++++-------
+ .../drm/amd/display/dc/gpio/gpio_service.h    |  6 +-
+ drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c  | 26 ++++---
+ drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h  |  5 +-
+ .../gpu/drm/amd/display/dc/gpio/hw_factory.h  | 48 ++++++------
+ .../gpu/drm/amd/display/dc/gpio/hw_generic.c  | 32 ++++----
+ .../gpu/drm/amd/display/dc/gpio/hw_generic.h  |  6 +-
+ drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c  | 31 ++++----
+ drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h  |  5 +-
+ drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h  | 10 +++
+ .../drm/amd/display/include/gpio_interface.h  |  9 +++
+ 18 files changed, 245 insertions(+), 137 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c b/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c
+index 20d81bca119c..66e4841f41e4 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c
+@@ -24,9 +24,15 @@
+  */
+ 
+ #include "dm_services.h"
++
+ #include "include/gpio_types.h"
+ #include "../hw_factory.h"
+ 
++#include "../hw_gpio.h"
++#include "../hw_ddc.h"
++#include "../hw_hpd.h"
++#include "../hw_generic.h"
++
+ #include "hw_factory_dce110.h"
+ 
+ #include "dce/dce_11_0_d.h"
+@@ -143,12 +149,12 @@ static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
+ }
+ 
+ static const struct hw_factory_funcs funcs = {
+-	.create_ddc_data = dal_hw_ddc_create,
+-	.create_ddc_clock = dal_hw_ddc_create,
+-	.create_generic = NULL,
+-	.create_hpd = dal_hw_hpd_create,
+-	.create_sync = NULL,
+-	.create_gsl = NULL,
++	.init_ddc_data = dal_hw_ddc_init,
++	.init_generic = NULL,
++	.init_hpd = dal_hw_hpd_init,
++	.get_ddc_pin = dal_hw_ddc_get_pin,
++	.get_hpd_pin = dal_hw_hpd_get_pin,
++	.get_generic_pin = NULL,
+ 	.define_hpd_registers = define_hpd_registers,
+ 	.define_ddc_registers = define_ddc_registers
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
+index ea3f888e5c65..cf98aa827a9a 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
+@@ -27,10 +27,10 @@
+ #include "include/gpio_types.h"
+ #include "../hw_factory.h"
+ 
+-
+ #include "../hw_gpio.h"
+ #include "../hw_ddc.h"
+ #include "../hw_hpd.h"
++#include "../hw_generic.h"
+ 
+ #include "hw_factory_dce120.h"
+ 
+@@ -164,12 +164,12 @@ static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
+ 
+ /* fucntion table */
+ static const struct hw_factory_funcs funcs = {
+-	.create_ddc_data = dal_hw_ddc_create,
+-	.create_ddc_clock = dal_hw_ddc_create,
+-	.create_generic = NULL,
+-	.create_hpd = dal_hw_hpd_create,
+-	.create_sync = NULL,
+-	.create_gsl = NULL,
++	.init_ddc_data = dal_hw_ddc_init,
++	.init_generic = NULL,
++	.init_hpd = dal_hw_hpd_init,
++	.get_ddc_pin = dal_hw_ddc_get_pin,
++	.get_hpd_pin = dal_hw_hpd_get_pin,
++	.get_generic_pin = NULL,
+ 	.define_hpd_registers = define_hpd_registers,
+ 	.define_ddc_registers = define_ddc_registers
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c b/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c
+index 48b67866377e..496d3ffb74bb 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c
+@@ -32,10 +32,12 @@
+ #include "../hw_gpio.h"
+ #include "../hw_ddc.h"
+ #include "../hw_hpd.h"
++#include "../hw_generic.h"
+ 
+ #include "dce/dce_8_0_d.h"
+ #include "dce/dce_8_0_sh_mask.h"
+ 
++
+ #define REG(reg_name)\
+ 		mm ## reg_name
+ 
+@@ -147,12 +149,12 @@ static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
+ }
+ 
+ static const struct hw_factory_funcs funcs = {
+-	.create_ddc_data = dal_hw_ddc_create,
+-	.create_ddc_clock = dal_hw_ddc_create,
+-	.create_generic = NULL,
+-	.create_hpd = dal_hw_hpd_create,
+-	.create_sync = NULL,
+-	.create_gsl = NULL,
++	.init_ddc_data = dal_hw_ddc_init,
++	.init_generic = NULL,
++	.init_hpd = dal_hw_hpd_init,
++	.get_ddc_pin = dal_hw_ddc_get_pin,
++	.get_hpd_pin = dal_hw_hpd_get_pin,
++	.get_generic_pin = NULL,
+ 	.define_hpd_registers = define_hpd_registers,
+ 	.define_ddc_registers = define_ddc_registers
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
+index 5711f30cf848..b38c96c9fed3 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
+@@ -196,12 +196,12 @@ static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
+ 
+ /* fucntion table */
+ static const struct hw_factory_funcs funcs = {
+-	.create_ddc_data = dal_hw_ddc_create,
+-	.create_ddc_clock = dal_hw_ddc_create,
+-	.create_generic = dal_hw_generic_create,
+-	.create_hpd = dal_hw_hpd_create,
+-	.create_sync = NULL,
+-	.create_gsl = NULL,
++	.init_ddc_data = dal_hw_ddc_init,
++	.init_generic = dal_hw_generic_init,
++	.init_hpd = dal_hw_hpd_init,
++	.get_ddc_pin = dal_hw_ddc_get_pin,
++	.get_hpd_pin = dal_hw_hpd_get_pin,
++	.get_generic_pin = dal_hw_generic_get_pin,
+ 	.define_hpd_registers = define_hpd_registers,
+ 	.define_ddc_registers = define_ddc_registers,
+ 	.define_generic_registers = define_generic_registers
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
+index afb7c0f111bf..43a440385b43 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
+@@ -212,12 +212,12 @@ static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
+ 
+ /* fucntion table */
+ static const struct hw_factory_funcs funcs = {
+-	.create_ddc_data = dal_hw_ddc_create,
+-	.create_ddc_clock = dal_hw_ddc_create,
+-	.create_generic = dal_hw_generic_create,
+-	.create_hpd = dal_hw_hpd_create,
+-	.create_sync = NULL,
+-	.create_gsl = NULL,
++	.init_ddc_data = dal_hw_ddc_init,
++	.init_generic = dal_hw_generic_init,
++	.init_hpd = dal_hw_hpd_init,
++	.get_ddc_pin = dal_hw_ddc_get_pin,
++	.get_hpd_pin = dal_hw_hpd_get_pin,
++	.get_generic_pin = dal_hw_generic_get_pin,
+ 	.define_hpd_registers = define_hpd_registers,
+ 	.define_ddc_registers = define_ddc_registers,
+ 	.define_generic_registers = define_generic_registers,
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c b/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c
+index f15288c3986e..df68430aeb0c 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c
+@@ -42,12 +42,9 @@
+ 
+ /* function table */
+ static const struct hw_factory_funcs funcs = {
+-	.create_ddc_data = NULL,
+-	.create_ddc_clock = NULL,
+-	.create_generic = NULL,
+-	.create_hpd = NULL,
+-	.create_sync = NULL,
+-	.create_gsl = NULL,
++	.init_ddc_data = NULL,
++	.init_generic = NULL,
++	.init_hpd = NULL,
+ };
+ 
+ void dal_hw_factory_diag_fpga_init(struct hw_factory *factory)
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c
+index cf76ea2d9f5a..c6f1a7c3affd 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c
+@@ -65,10 +65,14 @@ enum gpio_result dal_gpio_open_ex(
+ 		return GPIO_RESULT_ALREADY_OPENED;
+ 	}
+ 
++	// No action if allocation failed during gpio construct
++	if (!gpio->hw_container.ddc) {
++		ASSERT_CRITICAL(false);
++		return GPIO_RESULT_NON_SPECIFIC_ERROR;
++	}
+ 	gpio->mode = mode;
+ 
+-	return dal_gpio_service_open(
+-		gpio->service, gpio->id, gpio->en, mode, &gpio->pin);
++	return dal_gpio_service_open(gpio);
+ }
+ 
+ enum gpio_result dal_gpio_get_value(
+@@ -229,6 +233,21 @@ enum gpio_pin_output_state dal_gpio_get_output_state(
+ 	return gpio->output_state;
+ }
+ 
++struct hw_ddc *dal_gpio_get_ddc(struct gpio *gpio)
++{
++	return gpio->hw_container.ddc;
++}
++
++struct hw_hpd *dal_gpio_get_hpd(struct gpio *gpio)
++{
++	return gpio->hw_container.hpd;
++}
++
++struct hw_generic *dal_gpio_get_generic(struct gpio *gpio)
++{
++	return gpio->hw_container.generic;
++}
++
+ void dal_gpio_close(
+ 	struct gpio *gpio)
+ {
+@@ -265,6 +284,30 @@ struct gpio *dal_gpio_create(
+ 	gpio->mode = GPIO_MODE_UNKNOWN;
+ 	gpio->output_state = output_state;
+ 
++	//initialize hw_container union based on id
++	switch (gpio->id) {
++	case GPIO_ID_DDC_DATA:
++		gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en);
++		break;
++	case GPIO_ID_DDC_CLOCK:
++		gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en);
++		break;
++	case GPIO_ID_GENERIC:
++		gpio->service->factory.funcs->init_generic(&gpio->hw_container.generic, service->ctx, id, en);
++		break;
++	case GPIO_ID_HPD:
++		gpio->service->factory.funcs->init_hpd(&gpio->hw_container.hpd, service->ctx, id, en);
++		break;
++	// TODO: currently gpio for sync and gsl does not get created, might need it later
++	case GPIO_ID_SYNC:
++		break;
++	case GPIO_ID_GSL:
++		break;
++	default:
++		ASSERT_CRITICAL(false);
++		gpio->pin = NULL;
++	}
++
+ 	return gpio;
+ }
+ 
+@@ -278,6 +321,33 @@ void dal_gpio_destroy(
+ 
+ 	dal_gpio_close(*gpio);
+ 
++	switch ((*gpio)->id) {
++	case GPIO_ID_DDC_DATA:
++		kfree((*gpio)->hw_container.ddc);
++		(*gpio)->hw_container.ddc = NULL;
++		break;
++	case GPIO_ID_DDC_CLOCK:
++		//TODO: might want to change it to init_ddc_clock
++		kfree((*gpio)->hw_container.ddc);
++		(*gpio)->hw_container.ddc = NULL;
++		break;
++	case GPIO_ID_GENERIC:
++		kfree((*gpio)->hw_container.generic);
++		(*gpio)->hw_container.generic = NULL;
++		break;
++	case GPIO_ID_HPD:
++		kfree((*gpio)->hw_container.hpd);
++		(*gpio)->hw_container.hpd = NULL;
++		break;
++	// TODO: currently gpio for sync and gsl does not get created, might need it later
++	case GPIO_ID_SYNC:
++		break;
++	case GPIO_ID_GSL:
++		break;
++	default:
++		break;
++	}
++
+ 	kfree(*gpio);
+ 
+ 	*gpio = NULL;
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
+index 80f938e68285..30028223f8bc 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
+@@ -288,13 +288,15 @@ enum gpio_result dal_gpio_service_unlock(
+ }
+ 
+ enum gpio_result dal_gpio_service_open(
+-	struct gpio_service *service,
+-	enum gpio_id id,
+-	uint32_t en,
+-	enum gpio_mode mode,
+-	struct hw_gpio_pin **ptr)
++	struct gpio *gpio)
+ {
+-	struct hw_gpio_pin *pin;
++	struct gpio_service *service = gpio->service;
++	enum gpio_id id = gpio->id;
++	uint32_t en = gpio->en;
++	enum gpio_mode mode = gpio->mode;
++
++	struct hw_gpio_pin **pin = &gpio->pin;
++
+ 
+ 	if (!service->busyness[id]) {
+ 		ASSERT_CRITICAL(false);
+@@ -308,51 +310,43 @@ enum gpio_result dal_gpio_service_open(
+ 
+ 	switch (id) {
+ 	case GPIO_ID_DDC_DATA:
+-		pin = service->factory.funcs->create_ddc_data(
+-			service->ctx, id, en);
+-		service->factory.funcs->define_ddc_registers(pin, en);
++		*pin = service->factory.funcs->get_ddc_pin(gpio);
++		service->factory.funcs->define_ddc_registers(*pin, en);
+ 	break;
+ 	case GPIO_ID_DDC_CLOCK:
+-		pin = service->factory.funcs->create_ddc_clock(
+-			service->ctx, id, en);
+-		service->factory.funcs->define_ddc_registers(pin, en);
++		*pin = service->factory.funcs->get_ddc_pin(gpio);
++		service->factory.funcs->define_ddc_registers(*pin, en);
+ 	break;
+ 	case GPIO_ID_GENERIC:
+-		pin = service->factory.funcs->create_generic(
+-			service->ctx, id, en);
+-		service->factory.funcs->define_generic_registers(pin, en);
++		*pin = service->factory.funcs->get_generic_pin(gpio);
++		service->factory.funcs->define_generic_registers(*pin, en);
+ 	break;
+ 	case GPIO_ID_HPD:
+-		pin = service->factory.funcs->create_hpd(
+-			service->ctx, id, en);
+-		service->factory.funcs->define_hpd_registers(pin, en);
++		*pin = service->factory.funcs->get_hpd_pin(gpio);
++		service->factory.funcs->define_hpd_registers(*pin, en);
+ 	break;
++
++	//TODO: gsl and sync support? create_sync and create_gsl are NULL
+ 	case GPIO_ID_SYNC:
+-		pin = service->factory.funcs->create_sync(
+-			service->ctx, id, en);
+-	break;
+ 	case GPIO_ID_GSL:
+-		pin = service->factory.funcs->create_gsl(
+-			service->ctx, id, en);
+ 	break;
+ 	default:
+ 		ASSERT_CRITICAL(false);
+ 		return GPIO_RESULT_NON_SPECIFIC_ERROR;
+ 	}
+ 
+-	if (!pin) {
++	if (!*pin) {
+ 		ASSERT_CRITICAL(false);
+ 		return GPIO_RESULT_NON_SPECIFIC_ERROR;
+ 	}
+ 
+-	if (!pin->funcs->open(pin, mode)) {
++	if (!(*pin)->funcs->open(*pin, mode)) {
+ 		ASSERT_CRITICAL(false);
+-		dal_gpio_service_close(service, &pin);
++		dal_gpio_service_close(service, pin);
+ 		return GPIO_RESULT_OPEN_FAILED;
+ 	}
+ 
+ 	set_pin_busy(service, id, en);
+-	*ptr = pin;
+ 	return GPIO_RESULT_OK;
+ }
+ 
+@@ -374,11 +368,10 @@ void dal_gpio_service_close(
+ 
+ 		pin->funcs->close(pin);
+ 
+-		pin->funcs->destroy(ptr);
++		*ptr = NULL;
+ 	}
+ }
+ 
+-
+ enum dc_irq_source dal_irq_get_source(
+ 	const struct gpio *irq)
+ {
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.h b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.h
+index 0c678af75331..b9775a131ecd 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.h
++++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.h
+@@ -42,11 +42,7 @@ struct gpio_service {
+ };
+ 
+ enum gpio_result dal_gpio_service_open(
+-	struct gpio_service *service,
+-	enum gpio_id id,
+-	uint32_t en,
+-	enum gpio_mode mode,
+-	struct hw_gpio_pin **ptr);
++	struct gpio *gpio);
+ 
+ void dal_gpio_service_close(
+ 	struct gpio_service *service,
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
+index 49a99248e7f6..e1c84a2f7298 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
+@@ -25,6 +25,7 @@
+ 
+ #include "dm_services.h"
+ 
++#include "include/gpio_interface.h"
+ #include "include/gpio_types.h"
+ #include "hw_gpio.h"
+ #include "hw_ddc.h"
+@@ -42,6 +43,8 @@
+ #define REG(reg)\
+ 	(ddc->regs->reg)
+ 
++struct gpio;
++
+ static void destruct(
+ 	struct hw_ddc *pin)
+ {
+@@ -224,24 +227,29 @@ static void construct(
+ 	ddc->base.base.funcs = &funcs;
+ }
+ 
+-struct hw_gpio_pin *dal_hw_ddc_create(
++void dal_hw_ddc_init(
++	struct hw_ddc **hw_ddc,
+ 	struct dc_context *ctx,
+ 	enum gpio_id id,
+ 	uint32_t en)
+ {
+-	struct hw_ddc *pin;
+-
+ 	if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
+ 		ASSERT_CRITICAL(false);
+-		return NULL;
++		*hw_ddc = NULL;
+ 	}
+ 
+-	pin = kzalloc(sizeof(struct hw_ddc), GFP_KERNEL);
+-	if (!pin) {
++	*hw_ddc = kzalloc(sizeof(struct hw_ddc), GFP_KERNEL);
++	if (!*hw_ddc) {
+ 		ASSERT_CRITICAL(false);
+-		return NULL;
++		return;
+ 	}
+ 
+-	construct(pin, id, en, ctx);
+-	return &pin->base.base;
++	construct(*hw_ddc, id, en, ctx);
++}
++
++struct hw_gpio_pin *dal_hw_ddc_get_pin(struct gpio *gpio)
++{
++	struct hw_ddc *hw_ddc = dal_gpio_get_ddc(gpio);
++
++	return &hw_ddc->base.base;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h
+index 9690e2a885d7..cc30e65df431 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h
+@@ -38,9 +38,12 @@ struct hw_ddc {
+ #define HW_DDC_FROM_BASE(hw_gpio) \
+ 	container_of((HW_GPIO_FROM_BASE(hw_gpio)), struct hw_ddc, base)
+ 
+-struct hw_gpio_pin *dal_hw_ddc_create(
++void dal_hw_ddc_init(
++	struct hw_ddc **hw_ddc,
+ 	struct dc_context *ctx,
+ 	enum gpio_id id,
+ 	uint32_t en);
+ 
++struct hw_gpio_pin *dal_hw_ddc_get_pin(struct gpio *gpio);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h
+index 7017c9337348..e15b037f3bcd 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h
+@@ -28,35 +28,35 @@
+ 
+ struct hw_gpio_pin;
+ struct hw_hpd;
++struct hw_ddc;
++struct hw_generic;
++struct gpio;
+ 
+ struct hw_factory {
+ 	uint32_t number_of_pins[GPIO_ID_COUNT];
+ 
+ 	const struct hw_factory_funcs {
+-		struct hw_gpio_pin *(*create_ddc_data)(
+-			struct dc_context *ctx,
+-			enum gpio_id id,
+-			uint32_t en);
+-		struct hw_gpio_pin *(*create_ddc_clock)(
+-			struct dc_context *ctx,
+-			enum gpio_id id,
+-			uint32_t en);
+-		struct hw_gpio_pin *(*create_generic)(
+-			struct dc_context *ctx,
+-			enum gpio_id id,
+-			uint32_t en);
+-		struct hw_gpio_pin *(*create_hpd)(
+-			struct dc_context *ctx,
+-			enum gpio_id id,
+-			uint32_t en);
+-		struct hw_gpio_pin *(*create_sync)(
+-			struct dc_context *ctx,
+-			enum gpio_id id,
+-			uint32_t en);
+-		struct hw_gpio_pin *(*create_gsl)(
+-			struct dc_context *ctx,
+-			enum gpio_id id,
+-			uint32_t en);
++		void (*init_ddc_data)(
++				struct hw_ddc **hw_ddc,
++				struct dc_context *ctx,
++				enum gpio_id id,
++				uint32_t en);
++		void (*init_generic)(
++				struct hw_generic **hw_generic,
++				struct dc_context *ctx,
++				enum gpio_id id,
++				uint32_t en);
++		void (*init_hpd)(
++				struct hw_hpd **hw_hpd,
++				struct dc_context *ctx,
++				enum gpio_id id,
++				uint32_t en);
++		struct hw_gpio_pin *(*get_hpd_pin)(
++				struct gpio *gpio);
++		struct hw_gpio_pin *(*get_ddc_pin)(
++				struct gpio *gpio);
++		struct hw_gpio_pin *(*get_generic_pin)(
++				struct gpio *gpio);
+ 		void (*define_hpd_registers)(
+ 				struct hw_gpio_pin *pin,
+ 				uint32_t en);
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
+index ea0a1fc8cf23..f039c5982ac8 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
+@@ -25,6 +25,7 @@
+ 
+ #include "dm_services.h"
+ 
++#include "include/gpio_interface.h"
+ #include "include/gpio_types.h"
+ #include "hw_gpio.h"
+ #include "hw_generic.h"
+@@ -41,6 +42,8 @@
+ #define REG(reg)\
+ 	(generic->regs->reg)
+ 
++struct gpio;
++
+ static void dal_hw_generic_construct(
+ 	struct hw_generic *pin,
+ 	enum gpio_id id,
+@@ -104,29 +107,30 @@ static void construct(
+ 	generic->base.base.funcs = &funcs;
+ }
+ 
+-struct hw_gpio_pin *dal_hw_generic_create(
++void dal_hw_generic_init(
++	struct hw_generic **hw_generic,
+ 	struct dc_context *ctx,
+ 	enum gpio_id id,
+ 	uint32_t en)
+ {
+-	struct hw_generic *generic;
+-
+-	if (id != GPIO_ID_GENERIC) {
++	if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
+ 		ASSERT_CRITICAL(false);
+-		return NULL;
++		*hw_generic = NULL;
+ 	}
+ 
+-	if ((en < GPIO_GENERIC_MIN) || (en > GPIO_GENERIC_MAX)) {
++	*hw_generic = kzalloc(sizeof(struct hw_generic), GFP_KERNEL);
++	if (!*hw_generic) {
+ 		ASSERT_CRITICAL(false);
+-		return NULL;
++		return;
+ 	}
+ 
+-	generic = kzalloc(sizeof(struct hw_generic), GFP_KERNEL);
+-	if (!generic) {
+-		ASSERT_CRITICAL(false);
+-		return NULL;
+-	}
++	construct(*hw_generic, id, en, ctx);
++}
++
++
++struct hw_gpio_pin *dal_hw_generic_get_pin(struct gpio *gpio)
++{
++	struct hw_generic *hw_generic = dal_gpio_get_generic(gpio);
+ 
+-	construct(generic, id, en, ctx);
+-	return &generic->base.base;
++	return &hw_generic->base.base;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h
+index 3ea1c13e3ea6..bd6ffeb5e9df 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h
+@@ -27,6 +27,7 @@
+ #define __DAL_HW_generic_H__
+ 
+ #include "generic_regs.h"
++#include "hw_gpio.h"
+ 
+ struct hw_generic {
+ 	struct hw_gpio base;
+@@ -38,9 +39,12 @@ struct hw_generic {
+ #define HW_GENERIC_FROM_BASE(hw_gpio) \
+ 	container_of((HW_GPIO_FROM_BASE(hw_gpio)), struct hw_generic, base)
+ 
+-struct hw_gpio_pin *dal_hw_generic_create(
++void dal_hw_generic_init(
++	struct hw_generic **hw_generic,
+ 	struct dc_context *ctx,
+ 	enum gpio_id id,
+ 	uint32_t en);
+ 
++struct hw_gpio_pin *dal_hw_generic_get_pin(struct gpio *gpio);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
+index 784feccc5853..88798cf3965e 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
+@@ -25,6 +25,7 @@
+ 
+ #include "dm_services.h"
+ 
++#include "include/gpio_interface.h"
+ #include "include/gpio_types.h"
+ #include "hw_gpio.h"
+ #include "hw_hpd.h"
+@@ -41,6 +42,8 @@
+ #define REG(reg)\
+ 	(hpd->regs->reg)
+ 
++struct gpio;
++
+ static void dal_hw_hpd_construct(
+ 	struct hw_hpd *pin,
+ 	enum gpio_id id,
+@@ -134,29 +137,29 @@ static void construct(
+ 	hpd->base.base.funcs = &funcs;
+ }
+ 
+-struct hw_gpio_pin *dal_hw_hpd_create(
++void dal_hw_hpd_init(
++	struct hw_hpd **hw_hpd,
+ 	struct dc_context *ctx,
+ 	enum gpio_id id,
+ 	uint32_t en)
+ {
+-	struct hw_hpd *hpd;
+-
+-	if (id != GPIO_ID_HPD) {
++	if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
+ 		ASSERT_CRITICAL(false);
+-		return NULL;
++		*hw_hpd = NULL;
+ 	}
+ 
+-	if ((en < GPIO_HPD_MIN) || (en > GPIO_HPD_MAX)) {
++	*hw_hpd = kzalloc(sizeof(struct hw_hpd), GFP_KERNEL);
++	if (!*hw_hpd) {
+ 		ASSERT_CRITICAL(false);
+-		return NULL;
++		return;
+ 	}
+ 
+-	hpd = kzalloc(sizeof(struct hw_hpd), GFP_KERNEL);
+-	if (!hpd) {
+-		ASSERT_CRITICAL(false);
+-		return NULL;
+-	}
++	construct(*hw_hpd, id, en, ctx);
++}
++
++struct hw_gpio_pin *dal_hw_hpd_get_pin(struct gpio *gpio)
++{
++	struct hw_hpd *hw_hpd = dal_gpio_get_hpd(gpio);
+ 
+-	construct(hpd, id, en, ctx);
+-	return &hpd->base.base;
++	return &hw_hpd->base.base;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h
+index 4ab7a208f781..e7d8b3bb016c 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h
+@@ -38,9 +38,12 @@ struct hw_hpd {
+ #define HW_HPD_FROM_BASE(hw_gpio) \
+ 	container_of((HW_GPIO_FROM_BASE(hw_gpio)), struct hw_hpd, base)
+ 
+-struct hw_gpio_pin *dal_hw_hpd_create(
++void dal_hw_hpd_init(
++	struct hw_hpd **hw_hpd,
+ 	struct dc_context *ctx,
+ 	enum gpio_id id,
+ 	uint32_t en);
+ 
++struct hw_gpio_pin *dal_hw_hpd_get_pin(struct gpio *gpio);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h b/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h
+index 90d0148430fb..5253dc8b15f8 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h
+@@ -28,12 +28,22 @@
+ 
+ #include "gpio_types.h"
+ 
++
++union gpio_hw_container {
++	struct hw_ddc *ddc;
++	struct hw_generic *generic;
++	struct hw_hpd *hpd;
++};
++
+ struct gpio {
+ 	struct gpio_service *service;
+ 	struct hw_gpio_pin *pin;
+ 	enum gpio_id id;
+ 	uint32_t en;
++
++	union gpio_hw_container hw_container;
+ 	enum gpio_mode mode;
++
+ 	/* when GPIO comes from VBIOS, it has defined output state */
+ 	enum gpio_pin_output_state output_state;
+ };
+diff --git a/drivers/gpu/drm/amd/display/include/gpio_interface.h b/drivers/gpu/drm/amd/display/include/gpio_interface.h
+index 7de64195dc33..5e888a093c16 100644
+--- a/drivers/gpu/drm/amd/display/include/gpio_interface.h
++++ b/drivers/gpu/drm/amd/display/include/gpio_interface.h
+@@ -93,8 +93,17 @@ enum sync_source dal_gpio_get_sync_source(
+ enum gpio_pin_output_state dal_gpio_get_output_state(
+ 	const struct gpio *gpio);
+ 
++struct hw_ddc *dal_gpio_get_ddc(struct gpio *gpio);
++
++struct hw_hpd *dal_gpio_get_hpd(struct gpio *gpio);
++
++struct hw_generic *dal_gpio_get_generic(struct gpio *gpio);
++
+ /* Close the handle */
+ void dal_gpio_close(
+ 	struct gpio *gpio);
+ 
++
++
++
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3408-drm-amd-display-wait-for-pending-complete-when-enabl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3408-drm-amd-display-wait-for-pending-complete-when-enabl.patch
new file mode 100644
index 00000000..8c81ee69
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3408-drm-amd-display-wait-for-pending-complete-when-enabl.patch
@@ -0,0 +1,70 @@
+From 7dbe39921f97167c8f59e9c623b3dda654490939 Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Tue, 16 Jul 2019 13:02:41 -0400
+Subject: [PATCH 3408/4256] drm/amd/display: wait for pending complete when
+ enabling a plane
+
+[why]
+When planes are enabled, they must be enabled using VSYNC update (not immediate).
+However, before the VUPDATE occurs, DM may call with an "immediate" flip which is address
+only.  This operation would normally be okay, but if the locking for immediate flip happens
+to occur before the VUPDATE associated with the initial plane enablement, it will cause HW
+to hang.
+
+[how]
+HWSS should enforce plane enable in HW to be synchronous with the call that enables the plane.
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 20 ++++++++++++++++++-
+ 1 file changed, 19 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index fb7cde33c88b..c11de6f0fe5c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1353,13 +1353,15 @@ static void dcn20_apply_ctx_for_surface(
+ 		int num_planes,
+ 		struct dc_state *context)
+ {
+-
++	const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
+ 	int i;
+ 	struct timing_generator *tg;
+ 	bool removed_pipe[6] = { false };
+ 	bool interdependent_update = false;
+ 	struct pipe_ctx *top_pipe_to_program =
+ 			find_top_pipe_for_stream(dc, context, stream);
++	struct pipe_ctx *prev_top_pipe_to_program =
++			find_top_pipe_for_stream(dc, dc->current_state, stream);
+ 	DC_LOGGER_INIT(dc->ctx->logger);
+ 
+ 	if (!top_pipe_to_program)
+@@ -1453,6 +1455,22 @@ static void dcn20_apply_ctx_for_surface(
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++)
+ 		if (removed_pipe[i])
+ 			dcn20_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
++
++	/*
++	 * If we are enabling a pipe, we need to wait for pending clear as this is a critical
++	 * part of the enable operation otherwise, DM may request an immediate flip which
++	 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
++	 * is unsupported on DCN.
++	 */
++	i = 0;
++	if (num_planes > 0 && top_pipe_to_program &&
++			(prev_top_pipe_to_program == NULL || prev_top_pipe_to_program->plane_state == NULL)) {
++		while (i < TIMEOUT_FOR_PIPE_ENABLE_MS &&
++				top_pipe_to_program->plane_res.hubp->funcs->hubp_is_flip_pending(top_pipe_to_program->plane_res.hubp)) {
++			i += 1;
++			msleep(1);
++		}
++	}
+ }
+ 
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3409-drm-amd-display-3.2.43.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3409-drm-amd-display-3.2.43.patch
new file mode 100644
index 00000000..b6d154d0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3409-drm-amd-display-3.2.43.patch
@@ -0,0 +1,27 @@
+From daa452590011e113944a4c9d98dc5e08ed97d11d Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Mon, 15 Jul 2019 10:34:30 -0400
+Subject: [PATCH 3409/4256] drm/amd/display: 3.2.43
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index f8cb2745dc09..b9275993fcde 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -42,7 +42,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.42"
++#define DC_VER "3.2.43"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3410-drm-amd-display-Make-init_hw-and-init_pipes-generic-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3410-drm-amd-display-Make-init_hw-and-init_pipes-generic-.patch
new file mode 100644
index 00000000..1de82ea5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3410-drm-amd-display-Make-init_hw-and-init_pipes-generic-.patch
@@ -0,0 +1,1085 @@
+From ff8ce0bf7f897e15874a17c1d3bfd58925c747ac Mon Sep 17 00:00:00 2001
+From: Martin Leung <martin.leung@amd.com>
+Date: Tue, 9 Jul 2019 15:15:17 -0400
+Subject: [PATCH 3410/4256] drm/amd/display: Make init_hw and init_pipes
+ generic for seamless boot
+
+[Why]
+For seamless boot the init_hw sequence must be split into
+actual hardware vs pipes, in order to defer pipe initialization to set mode
+and skip of pipe-destructive sequences
+
+[How]
+made dcn10_init_hw and dcn10_init_pipes generic for future dcns to inherit
+deleted dcn20 specific versions. This is part 1 of a 2 partimplementation
+of seamless boot
+
+Signed-off-by: Martin Leung <martin.leung@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../display/dc/dce110/dce110_hw_sequencer.c   |  12 +-
+ .../display/dc/dce110/dce110_hw_sequencer.h   |   6 +-
+ .../drm/amd/display/dc/dcn10/dcn10_hubbub.c   |   4 +-
+ .../drm/amd/display/dc/dcn10/dcn10_hubbub.h   |   2 +-
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 182 ++++++---
+ .../drm/amd/display/dc/dcn20/dcn20_hubbub.c   |   2 +-
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 383 +++++++-----------
+ .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h  |   4 +
+ .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  32 ++
+ 9 files changed, 314 insertions(+), 313 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 919647166bce..5a046e5bc756 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -728,7 +728,7 @@ static enum bp_result link_transmitter_control(
+  * @brief
+  * eDP only.
+  */
+-void hwss_edp_wait_for_hpd_ready(
++void dce110_edp_wait_for_hpd_ready(
+ 		struct dc_link *link,
+ 		bool power_up)
+ {
+@@ -796,7 +796,7 @@ void hwss_edp_wait_for_hpd_ready(
+ 	}
+ }
+ 
+-void hwss_edp_power_control(
++void dce110_edp_power_control(
+ 		struct dc_link *link,
+ 		bool power_up)
+ {
+@@ -878,7 +878,7 @@ void hwss_edp_power_control(
+  * @brief
+  * eDP only. Control the backlight of the eDP panel
+  */
+-void hwss_edp_backlight_control(
++void dce110_edp_backlight_control(
+ 		struct dc_link *link,
+ 		bool enable)
+ {
+@@ -2755,9 +2755,9 @@ static const struct hw_sequencer_funcs dce110_funcs = {
+ 	.setup_stereo = NULL,
+ 	.set_avmute = dce110_set_avmute,
+ 	.wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
+-	.edp_backlight_control = hwss_edp_backlight_control,
+-	.edp_power_control = hwss_edp_power_control,
+-	.edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
++	.edp_backlight_control = dce110_edp_backlight_control,
++	.edp_power_control = dce110_edp_power_control,
++	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+ 	.set_cursor_position = dce110_set_cursor_position,
+ 	.set_cursor_attribute = dce110_set_cursor_attribute
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+index cd3e36d52a52..668feb0d169d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+@@ -73,15 +73,15 @@ void dce110_optimize_bandwidth(
+ 
+ void dp_receiver_power_ctrl(struct dc_link *link, bool on);
+ 
+-void hwss_edp_power_control(
++void dce110_edp_power_control(
+ 		struct dc_link *link,
+ 		bool power_up);
+ 
+-void hwss_edp_backlight_control(
++void dce110_edp_backlight_control(
+ 	struct dc_link *link,
+ 	bool enable);
+ 
+-void hwss_edp_wait_for_hpd_ready(
++void dce110_edp_wait_for_hpd_ready(
+ 		struct dc_link *link,
+ 		bool power_up);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+index 0ab391446d3d..90c30a21bd09 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+@@ -102,7 +102,7 @@ void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow)
+ 			DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, !allow);
+ }
+ 
+-bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
++bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
+ {
+ 	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
+ 	uint32_t enable = 0;
+@@ -943,6 +943,8 @@ static const struct hubbub_funcs hubbub1_funcs = {
+ 	.get_dcc_compression_cap = hubbub1_get_dcc_compression_cap,
+ 	.wm_read_state = hubbub1_wm_read_state,
+ 	.program_watermarks = hubbub1_program_watermarks,
++	.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
++	.allow_self_refresh_control = hubbub1_allow_self_refresh_control,
+ };
+ 
+ void hubbub1_construct(struct hubbub *hubbub,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+index 7c2559c9ae23..70e5d84fc69a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+@@ -247,7 +247,7 @@ void hubbub1_program_watermarks(
+ 
+ void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow);
+ 
+-bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubub);
++bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubub);
+ 
+ void hubbub1_toggle_watermark_change_req(
+ 		struct hubbub *hubbub);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 627684213461..cfe8331c4b46 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -437,7 +437,7 @@ bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	return false;
+ }
+ 
+-static void enable_power_gating_plane(
++static void dcn10_enable_power_gating_plane(
+ 	struct dce_hwseq *hws,
+ 	bool enable)
+ {
+@@ -459,7 +459,7 @@ static void enable_power_gating_plane(
+ 	REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
+ }
+ 
+-static void disable_vga(
++static void dcn10_disable_vga(
+ 	struct dce_hwseq *hws)
+ {
+ 	unsigned int in_vga1_mode = 0;
+@@ -492,7 +492,7 @@ static void disable_vga(
+ 	REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
+ }
+ 
+-static void dpp_pg_control(
++static void dcn10_dpp_pg_control(
+ 		struct dce_hwseq *hws,
+ 		unsigned int dpp_inst,
+ 		bool power_on)
+@@ -544,7 +544,7 @@ static void dpp_pg_control(
+ 	}
+ }
+ 
+-static void hubp_pg_control(
++static void dcn10_hubp_pg_control(
+ 		struct dce_hwseq *hws,
+ 		unsigned int hubp_inst,
+ 		bool power_on)
+@@ -604,8 +604,8 @@ static void power_on_plane(
+ 	if (REG(DC_IP_REQUEST_CNTL)) {
+ 		REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 				IP_REQUEST_EN, 1);
+-		dpp_pg_control(hws, plane_id, true);
+-		hubp_pg_control(hws, plane_id, true);
++		hws->ctx->dc->hwss.dpp_pg_control(hws, plane_id, true);
++		hws->ctx->dc->hwss.hubp_pg_control(hws, plane_id, true);
+ 		REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 				IP_REQUEST_EN, 0);
+ 		DC_LOG_DEBUG(
+@@ -626,7 +626,7 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc)
+ 	REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 			IP_REQUEST_EN, 1);
+ 
+-	hubp_pg_control(hws, 0, false);
++	dc->hwss.hubp_pg_control(hws, 0, false);
+ 	REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 			IP_REQUEST_EN, 0);
+ 
+@@ -655,7 +655,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc)
+ 	REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 			IP_REQUEST_EN, 1);
+ 
+-	hubp_pg_control(hws, 0, true);
++	dc->hwss.hubp_pg_control(hws, 0, true);
+ 	REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 			IP_REQUEST_EN, 0);
+ 
+@@ -663,10 +663,23 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc)
+ 	hws->wa_state.DEGVIDCN10_253_applied = true;
+ }
+ 
+-static void bios_golden_init(struct dc *dc)
++static void dcn10_bios_golden_init(struct dc *dc)
+ {
+ 	struct dc_bios *bp = dc->ctx->dc_bios;
+ 	int i;
++	bool allow_self_fresh_force_enable = true;
++
++	if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)
++		allow_self_fresh_force_enable =
++				dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);
++
++
++	/* WA for making DF sleep when idle after resume from S0i3.
++	 * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
++	 * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
++	 * before calling command table and it changed to 1 after,
++	 * it should be set back to 0.
++	 */
+ 
+ 	/* initialize dcn global */
+ 	bp->funcs->enable_disp_power_gating(bp,
+@@ -677,6 +690,12 @@ static void bios_golden_init(struct dc *dc)
+ 		bp->funcs->enable_disp_power_gating(bp,
+ 				CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
+ 	}
++
++	if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
++		if (allow_self_fresh_force_enable == false &&
++				dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub))
++			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, true);
++
+ }
+ 
+ static void false_optc_underflow_wa(
+@@ -970,7 +989,7 @@ void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 		dcn10_verify_allow_pstate_change_high(dc);
+ }
+ 
+-static void plane_atomic_power_down(struct dc *dc,
++static void dcn10_plane_atomic_power_down(struct dc *dc,
+ 		struct dpp *dpp,
+ 		struct hubp *hubp)
+ {
+@@ -980,8 +999,8 @@ static void plane_atomic_power_down(struct dc *dc,
+ 	if (REG(DC_IP_REQUEST_CNTL)) {
+ 		REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 				IP_REQUEST_EN, 1);
+-		dpp_pg_control(hws, dpp->inst, false);
+-		hubp_pg_control(hws, hubp->inst, false);
++		dc->hwss.dpp_pg_control(hws, dpp->inst, false);
++		dc->hwss.hubp_pg_control(hws, hubp->inst, false);
+ 		dpp->funcs->dpp_reset(dpp);
+ 		REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 				IP_REQUEST_EN, 0);
+@@ -993,7 +1012,7 @@ static void plane_atomic_power_down(struct dc *dc,
+ /* disable HW used by plane.
+  * note:  cannot disable until disconnect is complete
+  */
+-static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
++static void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
+@@ -1013,7 +1032,7 @@ static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	hubp->power_gated = true;
+ 	dc->optimized_required = false; /* We're powering off, no need to optimize */
+ 
+-	plane_atomic_power_down(dc,
++	dc->hwss.plane_atomic_power_down(dc,
+ 			pipe_ctx->plane_res.dpp,
+ 			pipe_ctx->plane_res.hubp);
+ 
+@@ -1032,7 +1051,7 @@ static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
+ 		return;
+ 
+-	plane_atomic_disable(dc, pipe_ctx);
++	dc->hwss.plane_atomic_disable(dc, pipe_ctx);
+ 
+ 	apply_DEGVIDCN10_253_wa(dc);
+ 
+@@ -1067,9 +1086,14 @@ static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
+ 		 * command table.
+ 		 */
+ 		if (tg->funcs->is_tg_enabled(tg)) {
+-			tg->funcs->lock(tg);
+-			tg->funcs->set_blank(tg, true);
+-			hwss_wait_for_blank_complete(tg);
++			if (dc->hwss.init_blank != NULL) {
++				dc->hwss.init_blank(dc, tg);
++				tg->funcs->lock(tg);
++			} else {
++				tg->funcs->lock(tg);
++				tg->funcs->set_blank(tg, true);
++				hwss_wait_for_blank_complete(tg);
++			}
+ 		}
+ 	}
+ 
+@@ -1113,12 +1137,12 @@ static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
+ 		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
+ 		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
+ 
+-		hwss1_plane_atomic_disconnect(dc, pipe_ctx);
++		dc->hwss.plane_atomic_disconnect(dc, pipe_ctx);
+ 
+ 		if (tg->funcs->is_tg_enabled(tg))
+ 			tg->funcs->unlock(tg);
+ 
+-		dcn10_disable_plane(dc, pipe_ctx);
++		dc->hwss.disable_plane(dc, pipe_ctx);
+ 
+ 		pipe_ctx->stream_res.tg = NULL;
+ 		pipe_ctx->plane_res.hubp = NULL;
+@@ -1134,8 +1158,17 @@ static void dcn10_init_hw(struct dc *dc)
+ 	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 	struct dce_hwseq *hws = dc->hwseq;
+ 	struct dc_bios *dcb = dc->ctx->dc_bios;
++	struct resource_pool *res_pool = dc->res_pool;
++
++	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
++		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
++
++	// Initialize the dccg
++	if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)
++		dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);
+ 
+ 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
++
+ 		REG_WRITE(REFCLK_CNTL, 0);
+ 		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
+ 		REG_WRITE(DIO_MEM_PWR_CTRL, 0);
+@@ -1149,30 +1182,39 @@ static void dcn10_init_hw(struct dc *dc)
+ 			REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
+ 		}
+ 
+-		enable_power_gating_plane(dc->hwseq, true);
++		//Enable ability to power gate / don't force power on permanently
++		dc->hwss.enable_power_gating_plane(hws, true);
+ 
+-		/* end of FPGA. Below if real ASIC */
+ 		return;
+ 	}
+ 
+ 	if (!dcb->funcs->is_accelerated_mode(dcb)) {
+-		bool allow_self_fresh_force_enable =
+-			hububu1_is_allow_self_refresh_enabled(
+-						dc->res_pool->hubbub);
+-
+-		bios_golden_init(dc);
+-
+-		/* WA for making DF sleep when idle after resume from S0i3.
+-		 * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
+-		 * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
+-		 * before calling command table and it changed to 1 after,
+-		 * it should be set back to 0.
+-		 */
+-		if (allow_self_fresh_force_enable == false &&
+-				hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub))
+-			hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, true);
+-
+-		disable_vga(dc->hwseq);
++		dc->hwss.bios_golden_init(dc);
++		if (dc->ctx->dc_bios->fw_info_valid) {
++			res_pool->ref_clocks.xtalin_clock_inKhz =
++					dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
++
++			if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
++				if (res_pool->dccg && res_pool->hubbub) {
++
++					(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
++							dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
++							&res_pool->ref_clocks.dccg_ref_clock_inKhz);
++
++					(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
++							res_pool->ref_clocks.dccg_ref_clock_inKhz,
++							&res_pool->ref_clocks.dchub_ref_clock_inKhz);
++				} else {
++					// Not all ASICs have DCCG sw component
++					res_pool->ref_clocks.dccg_ref_clock_inKhz =
++							res_pool->ref_clocks.xtalin_clock_inKhz;
++					res_pool->ref_clocks.dchub_ref_clock_inKhz =
++							res_pool->ref_clocks.xtalin_clock_inKhz;
++				}
++			}
++		} else
++			ASSERT_CRITICAL(false);
++		dc->hwss.disable_vga(dc->hwseq);
+ 	}
+ 
+ 	for (i = 0; i < dc->link_count; i++) {
+@@ -1190,6 +1232,13 @@ static void dcn10_init_hw(struct dc *dc)
+ 			link->link_status.link_active = true;
+ 	}
+ 
++	/* Power gate DSCs */
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
++		if (dc->hwss.dsc_pg_control != NULL)
++			dc->hwss.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
++#endif
++
+ 	/* If taking control over from VBIOS, we may want to optimize our first
+ 	 * mode set, so we need to skip powering down pipes until we know which
+ 	 * pipes we want to use.
+@@ -1198,10 +1247,21 @@ static void dcn10_init_hw(struct dc *dc)
+ 	 */
+ 	if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
+ 		dc->hwss.init_pipes(dc, dc->current_state);
++		for (i = 0; i < res_pool->pipe_count; i++) {
++			struct hubp *hubp = res_pool->hubps[i];
++			struct dpp *dpp = res_pool->dpps[i];
++
++			hubp->funcs->hubp_init(hubp);
++			res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
++			dc->hwss.plane_atomic_power_down(dc, dpp, hubp);
++		}
++
++		apply_DEGVIDCN10_253_wa(dc);
+ 	}
+ 
+-	for (i = 0; i < dc->res_pool->audio_count; i++) {
+-		struct audio *audio = dc->res_pool->audios[i];
++
++	for (i = 0; i < res_pool->audio_count; i++) {
++		struct audio *audio = res_pool->audios[i];
+ 
+ 		audio->funcs->hw_init(audio);
+ 	}
+@@ -1229,7 +1289,7 @@ static void dcn10_init_hw(struct dc *dc)
+ 		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
+ 	}
+ 
+-	enable_power_gating_plane(dc->hwseq, true);
++	dc->hwss.enable_power_gating_plane(dc->hwseq, true);
+ 
+ 	memset(&dc->clk_mgr->clks, 0, sizeof(dc->clk_mgr->clks));
+ }
+@@ -1787,7 +1847,7 @@ static void dcn10_enable_plane(
+ 	}
+ }
+ 
+-static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
++static void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)
+ {
+ 	int i = 0;
+ 	struct dpp_grph_csc_adjustment adjust;
+@@ -2218,7 +2278,7 @@ void update_dchubp_dpp(
+ 
+ 	if (plane_state->update_flags.bits.full_update) {
+ 		/*gamut remap*/
+-		program_gamut_remap(pipe_ctx);
++		dc->hwss.program_gamut_remap(pipe_ctx);
+ 
+ 		dc->hwss.program_output_csc(dc,
+ 				pipe_ctx,
+@@ -2455,7 +2515,7 @@ static void dcn10_apply_ctx_for_surface(
+ 			if (old_pipe_ctx->stream_res.tg == tg &&
+ 			    old_pipe_ctx->plane_res.hubp &&
+ 			    old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID)
+-				dcn10_disable_plane(dc, old_pipe_ctx);
++				dc->hwss.disable_plane(dc, old_pipe_ctx);
+ 		}
+ 
+ 		if ((!pipe_ctx->plane_state ||
+@@ -2503,7 +2563,7 @@ static void dcn10_apply_ctx_for_surface(
+ 
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++)
+ 		if (removed_pipe[i])
+-			dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
++			dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
+ 
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++)
+ 		if (removed_pipe[i]) {
+@@ -2595,7 +2655,7 @@ static void dcn10_optimize_bandwidth(
+ 		dcn10_verify_allow_pstate_change_high(dc);
+ }
+ 
+-static void set_drr(struct pipe_ctx **pipe_ctx,
++static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
+ 		int num_pipes, int vmin, int vmax)
+ {
+ 	int i = 0;
+@@ -2620,7 +2680,7 @@ static void set_drr(struct pipe_ctx **pipe_ctx,
+ 	}
+ }
+ 
+-static void get_position(struct pipe_ctx **pipe_ctx,
++static void dcn10_get_position(struct pipe_ctx **pipe_ctx,
+ 		int num_pipes,
+ 		struct crtc_position *position)
+ {
+@@ -2632,7 +2692,7 @@ static void get_position(struct pipe_ctx **pipe_ctx,
+ 		pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
+ }
+ 
+-static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
++static void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
+ 		int num_pipes, const struct dc_static_screen_events *events)
+ {
+ 	unsigned int i;
+@@ -3123,7 +3183,7 @@ static void dcn10_get_clock(struct dc *dc,
+ }
+ 
+ static const struct hw_sequencer_funcs dcn10_funcs = {
+-	.program_gamut_remap = program_gamut_remap,
++	.program_gamut_remap = dcn10_program_gamut_remap,
+ 	.init_hw = dcn10_init_hw,
+ 	.init_pipes = dcn10_init_pipes,
+ 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+@@ -3156,18 +3216,18 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
+ 	.optimize_bandwidth = dcn10_optimize_bandwidth,
+ 	.reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
+ 	.enable_stream_timing = dcn10_enable_stream_timing,
+-	.set_drr = set_drr,
+-	.get_position = get_position,
+-	.set_static_screen_control = set_static_screen_control,
++	.set_drr = dcn10_set_drr,
++	.get_position = dcn10_get_position,
++	.set_static_screen_control = dcn10_set_static_screen_control,
+ 	.setup_stereo = dcn10_setup_stereo,
+ 	.set_avmute = dce110_set_avmute,
+ 	.log_hw_state = dcn10_log_hw_state,
+ 	.get_hw_state = dcn10_get_hw_state,
+ 	.clear_status_bits = dcn10_clear_status_bits,
+ 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+-	.edp_backlight_control = hwss_edp_backlight_control,
+-	.edp_power_control = hwss_edp_power_control,
+-	.edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
++	.edp_backlight_control = dce110_edp_backlight_control,
++	.edp_power_control = dce110_edp_power_control,
++	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+ 	.set_cursor_position = dcn10_set_cursor_position,
+ 	.set_cursor_attribute = dcn10_set_cursor_attribute,
+ 	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
+@@ -3177,6 +3237,16 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
+ 	.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
+ 	.set_clock = dcn10_set_clock,
+ 	.get_clock = dcn10_get_clock,
++	.did_underflow_occur = dcn10_did_underflow_occur,
++	.init_blank = NULL,
++	.disable_vga = dcn10_disable_vga,
++	.bios_golden_init = dcn10_bios_golden_init,
++	.plane_atomic_disable = dcn10_plane_atomic_disable,
++	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
++	.enable_power_gating_plane = dcn10_enable_power_gating_plane,
++	.dpp_pg_control = dcn10_dpp_pg_control,
++	.hubp_pg_control = dcn10_hubp_pg_control,
++	.dsc_pg_control = NULL,
+ };
+ 
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+index 31d6e79ba2b8..cd101bbd8163 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+@@ -582,7 +582,7 @@ static const struct hubbub_funcs hubbub2_funcs = {
+ 	.get_dcc_compression_cap = hubbub2_get_dcc_compression_cap,
+ 	.wm_read_state = hubbub2_wm_read_state,
+ 	.get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
+-	.program_watermarks = hubbub2_program_watermarks,
++	.program_watermarks = hubbub2_program_watermarks
+ };
+ 
+ void hubbub2_construct(struct dcn20_hubbub *hubbub,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index c11de6f0fe5c..e337ff821e60 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -64,23 +64,7 @@
+ #define FN(reg_name, field_name) \
+ 	hws->shifts->field_name, hws->masks->field_name
+ 
+-static void bios_golden_init(struct dc *dc)
+-{
+-	struct dc_bios *bp = dc->ctx->dc_bios;
+-	int i;
+-
+-	/* initialize dcn global */
+-	bp->funcs->enable_disp_power_gating(bp,
+-			CONTROLLER_ID_D0, ASIC_PIPE_INIT);
+-
+-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+-		/* initialize dcn per pipe */
+-		bp->funcs->enable_disp_power_gating(bp,
+-				CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
+-	}
+-}
+-
+-static void enable_power_gating_plane(
++static void dcn20_enable_power_gating_plane(
+ 	struct dce_hwseq *hws,
+ 	bool enable)
+ {
+@@ -184,7 +168,7 @@ void dcn20_display_init(struct dc *dc)
+ 	REG_WRITE(AZALIA_CONTROLLER_CLOCK_GATING, 0x1);
+ }
+ 
+-static void disable_vga(
++void dcn20_disable_vga(
+ 	struct dce_hwseq *hws)
+ {
+ 	REG_WRITE(D1VGA_CONTROL, 0);
+@@ -487,29 +471,6 @@ static void dcn20_hubp_pg_control(
+ }
+ 
+ 
+-
+-static void dcn20_plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx)
+-{
+-	struct dce_hwseq *hws = dc->hwseq;
+-	struct dpp *dpp = pipe_ctx->plane_res.dpp;
+-
+-	DC_LOGGER_INIT(dc->ctx->logger);
+-
+-	if (REG(DC_IP_REQUEST_CNTL)) {
+-		REG_SET(DC_IP_REQUEST_CNTL, 0,
+-				IP_REQUEST_EN, 1);
+-		dcn20_dpp_pg_control(hws, dpp->inst, false);
+-		dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false);
+-		dpp->funcs->dpp_reset(dpp);
+-		REG_SET(DC_IP_REQUEST_CNTL, 0,
+-				IP_REQUEST_EN, 0);
+-		DC_LOG_DEBUG(
+-				"Power gated front end %d\n", pipe_ctx->pipe_idx);
+-	}
+-}
+-
+-
+-
+ /* disable HW used by plane.
+  * note:  cannot disable until disconnect is complete
+  */
+@@ -535,7 +496,9 @@ static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	hubp->power_gated = true;
+ 	dc->optimized_required = false; /* We're powering off, no need to optimize */
+ 
+-	dcn20_plane_atomic_power_down(dc, pipe_ctx);
++	dc->hwss.plane_atomic_power_down(dc,
++			pipe_ctx->plane_res.dpp,
++			pipe_ctx->plane_res.hubp);
+ 
+ 	pipe_ctx->stream = NULL;
+ 	memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
+@@ -559,204 +522,6 @@ void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 					pipe_ctx->pipe_idx);
+ }
+ 
+-static void dcn20_init_hw(struct dc *dc)
+-{
+-	int i, j;
+-	struct abm *abm = dc->res_pool->abm;
+-	struct dmcu *dmcu = dc->res_pool->dmcu;
+-	struct dce_hwseq *hws = dc->hwseq;
+-	struct dc_bios *dcb = dc->ctx->dc_bios;
+-	struct resource_pool *res_pool = dc->res_pool;
+-	struct dc_state  *context = dc->current_state;
+-
+-	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
+-		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
+-
+-	// Initialize the dccg
+-	if (res_pool->dccg->funcs->dccg_init)
+-		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
+-
+-	//Enable ability to power gate / don't force power on permanently
+-	enable_power_gating_plane(dc->hwseq, true);
+-
+-	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+-		REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
+-		REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
+-
+-		dcn20_dccg_init(hws);
+-
+-		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
+-		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
+-		REG_WRITE(REFCLK_CNTL, 0);
+-	} else {
+-		if (!dcb->funcs->is_accelerated_mode(dcb)) {
+-			bios_golden_init(dc);
+-			if (dc->ctx->dc_bios->fw_info_valid) {
+-				res_pool->ref_clocks.xtalin_clock_inKhz =
+-						dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
+-
+-				if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+-					if (res_pool->dccg && res_pool->hubbub) {
+-
+-						(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+-								dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
+-								&res_pool->ref_clocks.dccg_ref_clock_inKhz);
+-
+-						(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+-								res_pool->ref_clocks.dccg_ref_clock_inKhz,
+-								&res_pool->ref_clocks.dchub_ref_clock_inKhz);
+-					} else {
+-						// Not all ASICs have DCCG sw component
+-						res_pool->ref_clocks.dccg_ref_clock_inKhz =
+-								res_pool->ref_clocks.xtalin_clock_inKhz;
+-						res_pool->ref_clocks.dchub_ref_clock_inKhz =
+-								res_pool->ref_clocks.xtalin_clock_inKhz;
+-					}
+-				}
+-			} else
+-				ASSERT_CRITICAL(false);
+-			disable_vga(dc->hwseq);
+-		}
+-
+-		for (i = 0; i < dc->link_count; i++) {
+-			/* Power up AND update implementation according to the
+-			 * required signal (which may be different from the
+-			 * default signal on connector).
+-			 */
+-			struct dc_link *link = dc->links[i];
+-
+-			link->link_enc->funcs->hw_init(link->link_enc);
+-		}
+-	}
+-
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-	/* Power gate DSCs */
+-	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
+-		dcn20_dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
+-#endif
+-
+-	/* Blank pixel data with OPP DPG */
+-	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
+-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+-
+-		if (tg->funcs->is_tg_enabled(tg)) {
+-			dcn20_init_blank(dc, tg);
+-		}
+-	}
+-
+-	for (i = 0; i < res_pool->timing_generator_count; i++) {
+-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+-
+-		if (tg->funcs->is_tg_enabled(tg))
+-			tg->funcs->lock(tg);
+-	}
+-
+-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+-		struct dpp *dpp = res_pool->dpps[i];
+-
+-		dpp->funcs->dpp_reset(dpp);
+-	}
+-
+-	/* Reset all MPCC muxes */
+-	res_pool->mpc->funcs->mpc_init(res_pool->mpc);
+-
+-	/* initialize OPP mpc_tree parameter */
+-	for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
+-		res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
+-		res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
+-		for (j = 0; j < MAX_PIPES; j++)
+-			res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
+-	}
+-
+-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+-		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+-		struct hubp *hubp = dc->res_pool->hubps[i];
+-		struct dpp *dpp = dc->res_pool->dpps[i];
+-
+-		pipe_ctx->stream_res.tg = tg;
+-		pipe_ctx->pipe_idx = i;
+-
+-		pipe_ctx->plane_res.hubp = hubp;
+-		pipe_ctx->plane_res.dpp = dpp;
+-		pipe_ctx->plane_res.mpcc_inst = dpp->inst;
+-		hubp->mpcc_id = dpp->inst;
+-		hubp->opp_id = OPP_ID_INVALID;
+-		hubp->power_gated = false;
+-		pipe_ctx->stream_res.opp = NULL;
+-
+-		hubp->funcs->hubp_init(hubp);
+-
+-		//dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
+-		//dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
+-		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
+-		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
+-		/*to do*/
+-		hwss1_plane_atomic_disconnect(dc, pipe_ctx);
+-	}
+-
+-	/* initialize DWB pointer to MCIF_WB */
+-	for (i = 0; i < res_pool->res_cap->num_dwb; i++)
+-		res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
+-
+-	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
+-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+-
+-		if (tg->funcs->is_tg_enabled(tg))
+-			tg->funcs->unlock(tg);
+-	}
+-
+-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+-		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+-
+-		dc->hwss.disable_plane(dc, pipe_ctx);
+-
+-		pipe_ctx->stream_res.tg = NULL;
+-		pipe_ctx->plane_res.hubp = NULL;
+-	}
+-
+-	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
+-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+-
+-		tg->funcs->tg_init(tg);
+-	}
+-
+-	/* end of FPGA. Below if real ASIC */
+-	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+-		return;
+-
+-
+-	for (i = 0; i < res_pool->audio_count; i++) {
+-		struct audio *audio = res_pool->audios[i];
+-
+-		audio->funcs->hw_init(audio);
+-	}
+-
+-	if (abm != NULL) {
+-		abm->funcs->init_backlight(abm);
+-		abm->funcs->abm_init(abm);
+-	}
+-
+-	if (dmcu != NULL)
+-		dmcu->funcs->dmcu_init(dmcu);
+-
+-	if (abm != NULL && dmcu != NULL)
+-		abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
+-
+-	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
+-	REG_WRITE(DIO_MEM_PWR_CTRL, 0);
+-
+-	if (!dc->debug.disable_clock_gate) {
+-		/* enable all DCN clock gating */
+-		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
+-
+-		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
+-
+-		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
+-	}
+-
+-}
+-
+ enum dc_status dcn20_enable_stream_timing(
+ 		struct pipe_ctx *pipe_ctx,
+ 		struct dc_state *context,
+@@ -1409,7 +1174,7 @@ static void dcn20_apply_ctx_for_surface(
+ 			if (old_pipe_ctx->stream_res.tg == tg &&
+ 			    old_pipe_ctx->plane_res.hubp &&
+ 			    old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID)
+-				dcn20_disable_plane(dc, old_pipe_ctx);
++				dc->hwss.disable_plane(dc, old_pipe_ctx);
+ 		}
+ 
+ 		if ((!pipe_ctx->plane_state ||
+@@ -2169,14 +1934,126 @@ static void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
+ 						hubp->inst, mode);
+ }
+ 
++static void dcn20_fpga_init_hw(struct dc *dc)
++{
++	int i, j;
++	struct dce_hwseq *hws = dc->hwseq;
++	struct resource_pool *res_pool = dc->res_pool;
++	struct dc_state  *context = dc->current_state;
++
++	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
++		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
++
++	// Initialize the dccg
++	if (res_pool->dccg->funcs->dccg_init)
++		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
++
++	//Enable ability to power gate / don't force power on permanently
++	dc->hwss.enable_power_gating_plane(hws, true);
++
++	// Specific to FPGA dccg and registers
++	REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
++	REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
++
++	dcn20_dccg_init(hws);
++
++	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
++	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
++	REG_WRITE(REFCLK_CNTL, 0);
++	//
++
++
++	/* Blank pixel data with OPP DPG */
++	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
++		struct timing_generator *tg = dc->res_pool->timing_generators[i];
++
++		if (tg->funcs->is_tg_enabled(tg))
++			dcn20_init_blank(dc, tg);
++	}
++
++	for (i = 0; i < res_pool->timing_generator_count; i++) {
++		struct timing_generator *tg = dc->res_pool->timing_generators[i];
++
++		if (tg->funcs->is_tg_enabled(tg))
++			tg->funcs->lock(tg);
++	}
++
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
++		struct dpp *dpp = res_pool->dpps[i];
++
++		dpp->funcs->dpp_reset(dpp);
++	}
++
++	/* Reset all MPCC muxes */
++	res_pool->mpc->funcs->mpc_init(res_pool->mpc);
++
++	/* initialize OPP mpc_tree parameter */
++	for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
++		res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
++		res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
++		for (j = 0; j < MAX_PIPES; j++)
++			res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
++	}
++
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
++		struct timing_generator *tg = dc->res_pool->timing_generators[i];
++		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
++		struct hubp *hubp = dc->res_pool->hubps[i];
++		struct dpp *dpp = dc->res_pool->dpps[i];
++
++		pipe_ctx->stream_res.tg = tg;
++		pipe_ctx->pipe_idx = i;
++
++		pipe_ctx->plane_res.hubp = hubp;
++		pipe_ctx->plane_res.dpp = dpp;
++		pipe_ctx->plane_res.mpcc_inst = dpp->inst;
++		hubp->mpcc_id = dpp->inst;
++		hubp->opp_id = OPP_ID_INVALID;
++		hubp->power_gated = false;
++		pipe_ctx->stream_res.opp = NULL;
++
++		hubp->funcs->hubp_init(hubp);
++
++		//dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
++		//dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
++		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
++		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
++		/*to do*/
++		hwss1_plane_atomic_disconnect(dc, pipe_ctx);
++	}
++
++	/* initialize DWB pointer to MCIF_WB */
++	for (i = 0; i < res_pool->res_cap->num_dwb; i++)
++		res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
++
++	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
++		struct timing_generator *tg = dc->res_pool->timing_generators[i];
++
++		if (tg->funcs->is_tg_enabled(tg))
++			tg->funcs->unlock(tg);
++	}
++
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
++		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
++
++		dc->hwss.disable_plane(dc, pipe_ctx);
++
++		pipe_ctx->stream_res.tg = NULL;
++		pipe_ctx->plane_res.hubp = NULL;
++	}
++
++	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
++		struct timing_generator *tg = dc->res_pool->timing_generators[i];
++
++		tg->funcs->tg_init(tg);
++	}
++}
++
+ void dcn20_hw_sequencer_construct(struct dc *dc)
+ {
+ 	dcn10_hw_sequencer_construct(dc);
+-	dc->hwss.init_hw = dcn20_init_hw;
+-	dc->hwss.init_pipes = NULL;
+ 	dc->hwss.unblank_stream = dcn20_unblank_stream;
+ 	dc->hwss.update_plane_addr = dcn20_update_plane_addr;
+-	dc->hwss.disable_plane = dcn20_disable_plane,
+ 	dc->hwss.enable_stream_timing = dcn20_enable_stream_timing;
+ 	dc->hwss.program_triplebuffer = dcn20_program_tripleBuffer;
+ 	dc->hwss.set_input_transfer_func = dcn20_set_input_transfer_func;
+@@ -2204,5 +2081,21 @@ void dcn20_hw_sequencer_construct(struct dc *dc)
+ 	dc->hwss.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap;
+ 	dc->hwss.update_mpcc = dcn20_update_mpcc;
+ 	dc->hwss.set_flip_control_gsl = dcn20_set_flip_control_gsl;
+-	dc->hwss.did_underflow_occur = dcn10_did_underflow_occur;
++	dc->hwss.init_blank = dcn20_init_blank;
++	dc->hwss.disable_plane = dcn20_disable_plane;
++	dc->hwss.plane_atomic_disable = dcn20_plane_atomic_disable;
++	dc->hwss.enable_power_gating_plane = dcn20_enable_power_gating_plane;
++	dc->hwss.dpp_pg_control = dcn20_dpp_pg_control;
++	dc->hwss.hubp_pg_control = dcn20_hubp_pg_control;
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
++#endif
++	dc->hwss.disable_vga = dcn20_disable_vga;
++
++	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
++		dc->hwss.init_hw = dcn20_fpga_init_hw;
++		dc->hwss.init_pipes = NULL;
++	}
++
++
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+index 9502478c4a1b..c1f29b1654d9 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+@@ -141,6 +141,10 @@ struct hubbub_funcs {
+ 			struct dcn_watermark_set *watermarks,
+ 			unsigned int refclk_mhz,
+ 			bool safe_to_lower);
++
++	bool (*is_allow_self_refresh_enabled)(struct hubbub *hubbub);
++	void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow);
++
+ };
+ 
+ struct hubbub {
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index 28645e10f854..80de2febd7cb 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -78,6 +78,8 @@ struct stream_resource;
+ struct dc_phy_addr_space_config;
+ struct dc_virtual_addr_space_config;
+ #endif
++struct hubp;
++struct dpp;
+ 
+ struct hw_sequencer_funcs {
+ 
+@@ -280,6 +282,36 @@ struct hw_sequencer_funcs {
+ 	void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx);
+ 	bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+ 
++	void (*init_blank)(struct dc *dc, struct timing_generator *tg);
++	void (*disable_vga)(struct dce_hwseq *hws);
++	void (*bios_golden_init)(struct dc *dc);
++	void (*plane_atomic_power_down)(struct dc *dc,
++			struct dpp *dpp,
++			struct hubp *hubp);
++
++	void (*plane_atomic_disable)(
++			struct dc *dc, struct pipe_ctx *pipe_ctx);
++
++	void (*enable_power_gating_plane)(
++		struct dce_hwseq *hws,
++		bool enable);
++
++	void (*dpp_pg_control)(
++			struct dce_hwseq *hws,
++			unsigned int dpp_inst,
++			bool power_on);
++
++	void (*hubp_pg_control)(
++			struct dce_hwseq *hws,
++			unsigned int hubp_inst,
++			bool power_on);
++
++	void (*dsc_pg_control)(
++			struct dce_hwseq *hws,
++			unsigned int dsc_inst,
++			bool power_on);
++
++
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
+ 	void (*program_all_writeback_pipes_in_tree)(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3411-drm-amd-display-fix-dcn-specific-clk_mgr-init_clocks.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3411-drm-amd-display-fix-dcn-specific-clk_mgr-init_clocks.patch
new file mode 100644
index 00000000..85dfa045
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3411-drm-amd-display-fix-dcn-specific-clk_mgr-init_clocks.patch
@@ -0,0 +1,63 @@
+From 234148db1b2013476a71e751e99471d8da621871 Mon Sep 17 00:00:00 2001
+From: Martin Leung <martin.leung@amd.com>
+Date: Sun, 28 Jul 2019 11:09:11 -0400
+Subject: [PATCH 3411/4256] drm/amd/display: fix dcn-specific clk_mgr
+ init_clocks
+
+[Why]
+underflow seen on certain monitor setups caused by making dcnxx_init_hw
+generic
+
+[How]
+by moving dcn20_init_hw into dcn10, we added a dcn-specific clk_mgr
+init (dc->clk_mgr->funcs->init_clocks()). Thus, put old clk_mgr
+memset in an else statement so both memsets don't get set
+
+Signed-off-by: Martin Leung <martin.leung@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 6 ++++++
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 2 --
+ 2 files changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+index ad1478378f16..d00ee9fa04e4 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+@@ -31,6 +31,11 @@
+ #include "rv1_clk_mgr_vbios_smu.h"
+ #include "rv1_clk_mgr_clk.h"
+ 
++void rv1_init_clocks(struct clk_mgr *clk_mgr)
++{
++	memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
++}
++
+ static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)
+ {
+ 	bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
+@@ -234,6 +239,7 @@ static void rv1_enable_pme_wa(struct clk_mgr *clk_mgr_base)
+ }
+ 
+ static struct clk_mgr_funcs rv1_clk_funcs = {
++	.init_clocks = rv1_init_clocks,
+ 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
+ 	.update_clocks = rv1_update_clocks,
+ 	.enable_pme_wa = rv1_enable_pme_wa,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index cfe8331c4b46..167bd6e92afa 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1290,8 +1290,6 @@ static void dcn10_init_hw(struct dc *dc)
+ 	}
+ 
+ 	dc->hwss.enable_power_gating_plane(dc->hwseq, true);
+-
+-	memset(&dc->clk_mgr->clks, 0, sizeof(dc->clk_mgr->clks));
+ }
+ 
+ static void dcn10_reset_hw_ctx_wrap(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3412-drm-amd-display-enabling-seamless-boot-sequence-for-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3412-drm-amd-display-enabling-seamless-boot-sequence-for-.patch
new file mode 100644
index 00000000..c91df5fa
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3412-drm-amd-display-enabling-seamless-boot-sequence-for-.patch
@@ -0,0 +1,521 @@
+From 5f3077c37a139b6fda265aa32fe5cb9d43414c61 Mon Sep 17 00:00:00 2001
+From: Martin Leung <martin.leung@amd.com>
+Date: Wed, 17 Jul 2019 16:08:19 -0400
+Subject: [PATCH 3412/4256] drm/amd/display: enabling seamless boot sequence
+ for dcn2
+
+[Why]
+Seamless boot (building SW state inheriting BIOS-initialized timing) was
+enabled on DCN2, including fixes
+
+[How]
+Includes fixes for MPC, DPPCLK, and DIG FE mapping/OTG source select/
+Pixel clock.
+
+This is part 2 of 2 for seamless boot NV10
+
+Signed-off-by: Martin Leung <martin.leung@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c      | 26 +++++++---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 13 ++++-
+ .../gpu/drm/amd/display/dc/core/dc_resource.c | 39 +++++++++------
+ .../drm/amd/display/dc/dce/dce_clock_source.c |  3 +-
+ .../amd/display/dc/dce/dce_stream_encoder.c   | 12 +++++
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 13 +++--
+ .../amd/display/dc/dcn10/dcn10_link_encoder.c | 49 +++++++++++++++----
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c  | 19 +++++++
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h  |  4 ++
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |  4 ++
+ .../display/dc/dcn10/dcn10_stream_encoder.c   | 12 +++++
+ .../display/dc/dcn10/dcn10_stream_encoder.h   |  3 ++
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c  |  1 +
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c |  3 +-
+ .../display/dc/dcn20/dcn20_stream_encoder.c   |  1 +
+ drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h   |  3 ++
+ .../amd/display/dc/inc/hw/stream_encoder.h    |  3 ++
+ 17 files changed, 172 insertions(+), 36 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 409d9a02f613..3e79bdbc68e9 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -969,7 +969,7 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
+ {
+ 	struct timing_generator *tg;
+ 	struct dc_link *link = sink->link;
+-	unsigned int inst;
++	unsigned int enc_inst, tg_inst;
+ 
+ 	/* Check for enabled DIG to identify enabled display */
+ 	if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
+@@ -981,13 +981,22 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
+ 	 * current implementation always map 1-to-1, so this code makes
+ 	 * the same assumption and doesn't check OTG source.
+ 	 */
+-	inst = link->link_enc->funcs->get_dig_frontend(link->link_enc) - 1;
++	enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
+ 
+ 	/* Instance should be within the range of the pool */
+-	if (inst >= dc->res_pool->pipe_count)
++	if (enc_inst >= dc->res_pool->pipe_count)
+ 		return false;
+ 
+-	tg = dc->res_pool->timing_generators[inst];
++	if (enc_inst >= dc->res_pool->stream_enc_count)
++		return false;
++
++	tg_inst = dc->res_pool->stream_enc[enc_inst]->funcs->dig_source_otg(
++		dc->res_pool->stream_enc[enc_inst]);
++
++	if (tg_inst >= dc->res_pool->timing_generator_count)
++		return false;
++
++	tg = dc->res_pool->timing_generators[tg_inst];
+ 
+ 	if (!tg->funcs->is_matching_timing)
+ 		return false;
+@@ -1000,10 +1009,11 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
+ 
+ 		dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
+ 			dc->res_pool->dp_clock_source,
+-			inst, &pix_clk_100hz);
++			tg_inst, &pix_clk_100hz);
+ 
+ 		if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
+ 			return false;
++
+ 	}
+ 
+ 	return true;
+@@ -1913,13 +1923,17 @@ static void commit_planes_do_stream_update(struct dc *dc,
+ 
+ 			if (stream_update->dpms_off) {
+ 				dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
++
+ 				if (*stream_update->dpms_off) {
+ 					core_link_disable_stream(pipe_ctx, KEEP_ACQUIRED_RESOURCE);
+ 					dc->hwss.optimize_bandwidth(dc, dc->current_state);
+ 				} else {
+-					dc->hwss.prepare_bandwidth(dc, dc->current_state);
++					if (!dc->optimize_seamless_boot)
++						dc->hwss.prepare_bandwidth(dc, dc->current_state);
++
+ 					core_link_enable_stream(dc->current_state, pipe_ctx);
+ 				}
++
+ 				dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
+ 			}
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index ed8bdcf44c8e..9fe324dbbe91 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -1419,6 +1419,16 @@ static enum dc_status enable_link_dp(
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	bool fec_enable;
+ #endif
++	int i;
++	bool apply_seamless_boot_optimization = false;
++
++	// check for seamless boot
++	for (i = 0; i < state->stream_count; i++) {
++		if (state->streams[i]->apply_seamless_boot_optimization) {
++			apply_seamless_boot_optimization = true;
++			break;
++		}
++	}
+ 
+ 	/* get link settings for video mode timing */
+ 	decide_link_settings(stream, &link_settings);
+@@ -1440,7 +1450,8 @@ static enum dc_status enable_link_dp(
+ 
+ 	pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
+ 			link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
+-	state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false);
++	if (!apply_seamless_boot_optimization)
++		state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false);
+ 
+ 	dp_enable_link_phy(
+ 		link,
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 5f2f2c7e7445..fa94dfc04dce 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -1890,7 +1890,7 @@ static int acquire_resource_from_hw_enabled_state(
+ 		struct dc_stream_state *stream)
+ {
+ 	struct dc_link *link = stream->link;
+-	unsigned int inst;
++	unsigned int inst, tg_inst;
+ 
+ 	/* Check for enabled DIG to identify enabled display */
+ 	if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
+@@ -1902,28 +1902,37 @@ static int acquire_resource_from_hw_enabled_state(
+ 	 * current implementation always map 1-to-1, so this code makes
+ 	 * the same assumption and doesn't check OTG source.
+ 	 */
+-	inst = link->link_enc->funcs->get_dig_frontend(link->link_enc) - 1;
++	inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
+ 
+ 	/* Instance should be within the range of the pool */
+ 	if (inst >= pool->pipe_count)
+ 		return -1;
+ 
+-	if (!res_ctx->pipe_ctx[inst].stream) {
+-		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[inst];
++	if (inst >= pool->stream_enc_count)
++		return -1;
++
++	tg_inst = pool->stream_enc[inst]->funcs->dig_source_otg(pool->stream_enc[inst]);
++
++	if (tg_inst >= pool->timing_generator_count)
++		return false;
++
++	if (!res_ctx->pipe_ctx[tg_inst].stream) {
++		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
++
++		pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
++		pipe_ctx->plane_res.mi = pool->mis[tg_inst];
++		pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
++		pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
++		pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
++		pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
++		pipe_ctx->stream_res.opp = pool->opps[tg_inst];
+ 
+-		pipe_ctx->stream_res.tg = pool->timing_generators[inst];
+-		pipe_ctx->plane_res.mi = pool->mis[inst];
+-		pipe_ctx->plane_res.hubp = pool->hubps[inst];
+-		pipe_ctx->plane_res.ipp = pool->ipps[inst];
+-		pipe_ctx->plane_res.xfm = pool->transforms[inst];
+-		pipe_ctx->plane_res.dpp = pool->dpps[inst];
+-		pipe_ctx->stream_res.opp = pool->opps[inst];
+-		if (pool->dpps[inst])
+-			pipe_ctx->plane_res.mpcc_inst = pool->dpps[inst]->inst;
+-		pipe_ctx->pipe_idx = inst;
++		if (pool->dpps[tg_inst])
++			pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
++		pipe_ctx->pipe_idx = tg_inst;
+ 
+ 		pipe_ctx->stream = stream;
+-		return inst;
++		return tg_inst;
+ 	}
+ 
+ 	return -1;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+index 464d7c3830ef..990481b35682 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+@@ -1059,7 +1059,8 @@ static bool dcn20_program_pix_clk(
+ static const struct clock_source_funcs dcn20_clk_src_funcs = {
+ 	.cs_power_down = dce110_clock_source_power_down,
+ 	.program_pix_clk = dcn20_program_pix_clk,
+-	.get_pix_clk_dividers = dce112_get_pix_clk_dividers
++	.get_pix_clk_dividers = dce112_get_pix_clk_dividers,
++	.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
+ };
+ #endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+index 7e8b8ae036ee..9205fb2e08bd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+@@ -1600,6 +1600,17 @@ static void dig_connect_to_otg(
+ 	REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
+ }
+ 
++static unsigned int dig_source_otg(
++	struct stream_encoder *enc)
++{
++	uint32_t tg_inst = 0;
++	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
++
++	REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
++
++	return tg_inst;
++}
++
+ static const struct stream_encoder_funcs dce110_str_enc_funcs = {
+ 	.dp_set_stream_attribute =
+ 		dce110_stream_encoder_dp_set_stream_attribute,
+@@ -1635,6 +1646,7 @@ static const struct stream_encoder_funcs dce110_str_enc_funcs = {
+ 	.set_avmute = dce110_stream_encoder_set_avmute,
+ 	.dig_connect_to_otg  = dig_connect_to_otg,
+ 	.hdmi_reset_stream_attribute = dce110_reset_hdmi_stream_attribute,
++	.dig_source_otg = dig_source_otg,
+ };
+ 
+ void dce110_stream_encoder_construct(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 167bd6e92afa..86f874bddd84 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1097,9 +1097,16 @@ static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
+ 		}
+ 	}
+ 
+-	/* Cannot reset the MPC mux if seamless boot */
+-	if (!can_apply_seamless_boot)
+-		dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
++		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
++
++		/* Cannot reset the MPC mux if seamless boot */
++		if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
++			continue;
++
++		dc->res_pool->mpc->funcs->mpc_init_single_inst(
++				dc->res_pool->mpc, i);
++	}
+ 
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+index 9427a461bb26..e4c7ecd87de7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+@@ -443,6 +443,46 @@ static uint8_t get_frontend_source(
+ 	}
+ }
+ 
++unsigned int dcn10_get_dig_frontend(struct link_encoder *enc)
++{
++	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
++	int32_t value;
++	enum engine_id result;
++
++	REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
++
++	switch (value) {
++	case DCN10_DIG_FE_SOURCE_SELECT_DIGA:
++		result = ENGINE_ID_DIGA;
++		break;
++	case DCN10_DIG_FE_SOURCE_SELECT_DIGB:
++		result = ENGINE_ID_DIGB;
++		break;
++	case DCN10_DIG_FE_SOURCE_SELECT_DIGC:
++		result = ENGINE_ID_DIGC;
++		break;
++	case DCN10_DIG_FE_SOURCE_SELECT_DIGD:
++		result = ENGINE_ID_DIGD;
++		break;
++	case DCN10_DIG_FE_SOURCE_SELECT_DIGE:
++		result = ENGINE_ID_DIGE;
++		break;
++	case DCN10_DIG_FE_SOURCE_SELECT_DIGF:
++		result = ENGINE_ID_DIGF;
++		break;
++	case DCN10_DIG_FE_SOURCE_SELECT_DIGG:
++		result = ENGINE_ID_DIGG;
++		break;
++	default:
++		// invalid source select DIG
++		ASSERT(false);
++		result = ENGINE_ID_UNKNOWN;
++	}
++
++	return result;
++
++}
++
+ void enc1_configure_encoder(
+ 	struct dcn10_link_encoder *enc10,
+ 	const struct dc_link_settings *link_settings)
+@@ -498,15 +538,6 @@ bool dcn10_is_dig_enabled(struct link_encoder *enc)
+ 	return value;
+ }
+ 
+-unsigned int dcn10_get_dig_frontend(struct link_encoder *enc)
+-{
+-	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+-	uint32_t value;
+-
+-	REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
+-	return value;
+-}
+-
+ static void link_encoder_disable(struct dcn10_link_encoder *enc10)
+ {
+ 	/* reset training pattern */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+index 4f7a10390c57..8b2f29f6dabd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+@@ -364,6 +364,24 @@ void mpc1_mpc_init(struct mpc *mpc)
+ 	}
+ }
+ 
++void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id)
++{
++	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
++	int opp_id;
++
++	REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
++
++	REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
++	REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
++	REG_SET(MPCC_OPP_ID[mpcc_id],  0, MPCC_OPP_ID,  0xf);
++
++	mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
++
++	if (opp_id < MAX_OPP && REG(MUX[opp_id]))
++		REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);
++}
++
++
+ void mpc1_init_mpcc_list_from_hw(
+ 	struct mpc *mpc,
+ 	struct mpc_tree *tree)
+@@ -433,6 +451,7 @@ static const struct mpc_funcs dcn10_mpc_funcs = {
+ 	.insert_plane = mpc1_insert_plane,
+ 	.remove_mpcc = mpc1_remove_mpcc,
+ 	.mpc_init = mpc1_mpc_init,
++	.mpc_init_single_inst = mpc1_mpc_init_single_inst,
+ 	.get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
+ 	.wait_for_idle = mpc1_assert_idle_mpcc,
+ 	.assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
+index d3d16c4cbea3..962a68e322ee 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
+@@ -149,6 +149,10 @@ void mpc1_remove_mpcc(
+ void mpc1_mpc_init(
+ 	struct mpc *mpc);
+ 
++void mpc1_mpc_init_single_inst(
++	struct mpc *mpc,
++	unsigned int mpcc_id);
++
+ void mpc1_assert_idle_mpcc(
+ 	struct mpc *mpc,
+ 	int id);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+index 02599eb92ca6..66c08d05da0e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+@@ -539,6 +539,10 @@ struct dcn_otg_state {
+ void optc1_read_otg_state(struct optc *optc1,
+ 		struct dcn_otg_state *s);
+ 
++bool optc1_is_matching_timing(
++	struct timing_generator *tg,
++	const struct dc_crtc_timing *otg_timing);
++
+ bool optc1_validate_timing(
+ 	struct timing_generator *optc,
+ 	const struct dc_crtc_timing *timing);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+index 00aa9dde5538..6800b906a86e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+@@ -1541,6 +1541,17 @@ void enc1_dig_connect_to_otg(
+ 	REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
+ }
+ 
++unsigned int enc1_dig_source_otg(
++	struct stream_encoder *enc)
++{
++	uint32_t tg_inst = 0;
++	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
++
++	REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
++
++	return tg_inst;
++}
++
+ static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
+ 	.dp_set_stream_attribute =
+ 		enc1_stream_encoder_dp_set_stream_attribute,
+@@ -1576,6 +1587,7 @@ static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
+ 	.set_avmute = enc1_stream_encoder_set_avmute,
+ 	.dig_connect_to_otg  = enc1_dig_connect_to_otg,
+ 	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
++	.dig_source_otg = enc1_dig_source_otg,
+ };
+ 
+ void dcn10_stream_encoder_construct(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+index 8b8921e75984..a512cbea00d1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+@@ -598,6 +598,9 @@ void enc1_dig_connect_to_otg(
+ 	struct stream_encoder *enc,
+ 	int tg_inst);
+ 
++unsigned int enc1_dig_source_otg(
++	struct stream_encoder *enc);
++
+ void enc1_stream_encoder_set_stream_attribute_helper(
+ 	struct dcn10_stream_encoder *enc1,
+ 	struct dc_crtc_timing *crtc_timing);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+index 67f0128f0b38..17950d9e53cf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+@@ -498,6 +498,7 @@ const struct mpc_funcs dcn20_mpc_funcs = {
+ 	.insert_plane = mpc1_insert_plane,
+ 	.remove_mpcc = mpc1_remove_mpcc,
+ 	.mpc_init = mpc1_mpc_init,
++	.mpc_init_single_inst = mpc1_mpc_init_single_inst,
+ 	.update_blending = mpc2_update_blending,
+ 	.get_mpcc_for_dpp = mpc2_get_mpcc_for_dpp,
+ 	.wait_for_idle = mpc2_assert_idle_mpcc,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+index 1ae973962d53..6dede495d0fd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+@@ -522,7 +522,8 @@ static struct timing_generator_funcs dcn20_tg_funcs = {
+ 		.set_gsl_source_select = optc2_set_gsl_source_select,
+ 		.set_vtg_params = optc1_set_vtg_params,
+ 		.program_manual_trigger = optc2_program_manual_trigger,
+-		.setup_manual_trigger = optc2_setup_manual_trigger
++		.setup_manual_trigger = optc2_setup_manual_trigger,
++		.is_matching_timing = optc1_is_matching_timing
+ };
+ 
+ void dcn20_timing_generator_init(struct optc *optc1)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+index b2c1cad3c94f..a2f15387e946 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+@@ -578,6 +578,7 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = {
+ 	.setup_stereo_sync  = enc1_setup_stereo_sync,
+ 	.set_avmute = enc1_stream_encoder_set_avmute,
+ 	.dig_connect_to_otg  = enc1_dig_connect_to_otg,
++	.dig_source_otg = enc1_dig_source_otg,
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	.enc_read_state = enc2_read_state,
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+index 9f00289bda78..9dde88d4571c 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+@@ -199,6 +199,9 @@ struct mpc_funcs {
+ 	 * Return:  void
+ 	 */
+ 	void (*mpc_init)(struct mpc *mpc);
++	void (*mpc_init_single_inst)(
++			struct mpc *mpc,
++			unsigned int mpcc_id);
+ 
+ 	/*
+ 	 * Update the blending configuration for a specified MPCC.
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+index 38e2c3e7412e..067ba6fc04c1 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+@@ -214,6 +214,9 @@ struct stream_encoder_funcs {
+ 	void (*hdmi_reset_stream_attribute)(
+ 		struct stream_encoder *enc);
+ 
++	unsigned int (*dig_source_otg)(
++		struct stream_encoder *enc);
++
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	void (*dp_set_dsc_config)(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3413-drm-amd-display-clean-up-DML-for-DCN2x.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3413-drm-amd-display-clean-up-DML-for-DCN2x.patch
new file mode 100644
index 00000000..74a898de
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3413-drm-amd-display-clean-up-DML-for-DCN2x.patch
@@ -0,0 +1,80 @@
+From b0f836172fa28e0aa3b64bc6c473372d6232cab5 Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Thu, 18 Jul 2019 10:02:40 -0400
+Subject: [PATCH 3413/4256] drm/amd/display: clean up DML for DCN2x
+
+[why]
+Previous "less risky" implemenation of 3 tiered fallback is no longer necessary since
+DMLv2 has gone through proper validation.  v2 can now be used as the default and 1
+level of fallback can be removed
+
+[how]
+remove previous workaround implemenation
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h           |  1 -
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 19 +++----------------
+ 2 files changed, 3 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index b9275993fcde..32312827daae 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -124,7 +124,6 @@ struct dc_caps {
+ struct dc_bug_wa {
+ 	bool no_connect_phy_config;
+ 	bool dedcn20_305_wa;
+-	struct display_mode_lib alternate_dml;
+ 	bool skip_clock_update;
+ };
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index a26541bafc75..af8ab57a8af5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2610,7 +2610,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
+ 		goto restore_dml_state;
+ 	}
+ 
+-	// Fallback #1: Try to only support G6 temperature read latency
++	// Fallback: Try to only support G6 temperature read latency
+ 	context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
+ 
+ 	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
+@@ -2621,19 +2621,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
+ 		goto restore_dml_state;
+ 	}
+ 
+-	// Fallback #2: Retry with "new" DCN20 to support G6 temperature read latency
+-	memcpy (&context->bw_ctx.dml, &dc->work_arounds.alternate_dml, sizeof (struct display_mode_lib));
+-	context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
+-
+-	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
+-	dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
+-
+-	if (voltage_supported && dummy_pstate_supported) {
+-		context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
+-		goto restore_dml_state;
+-	}
+-
+-	// ERROR: fallback #2 is supposed to always work.
++	// ERROR: fallback is supposed to always work.
+ 	ASSERT(false);
+ 
+ restore_dml_state:
+@@ -3238,8 +3226,7 @@ static bool construct(
+ 		goto create_fail;
+ 	}
+ 
+-	dml_init_instance(&dc->dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10);
+-	dml_init_instance(&dc->work_arounds.alternate_dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10v2);
++	dml_init_instance(&dc->dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10v2);
+ 
+ 	if (!dc->debug.disable_pplib_wm_range) {
+ 		struct pp_smu_wm_range_sets ranges = {0};
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3414-drm-amd-display-Add-HLG-support-in-color-module.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3414-drm-amd-display-Add-HLG-support-in-color-module.patch
new file mode 100644
index 00000000..3f800c77
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3414-drm-amd-display-Add-HLG-support-in-color-module.patch
@@ -0,0 +1,220 @@
+From 9f40a74d44ce4097b30d7be991434e3e8f6f1aa5 Mon Sep 17 00:00:00 2001
+From: Vitaly Prosyak <vitaly.prosyak@amd.com>
+Date: Thu, 18 Jul 2019 13:07:03 -0500
+Subject: [PATCH 3414/4256] drm/amd/display: Add HLG support in color module
+
+[Why & How]
+Support hlg OETF and EOTF based on BT.2100-2
+Follow up is required.
+
+Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
+Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Acked-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com>
+---
+ .../amd/display/modules/color/color_gamma.c   | 102 +++++++++++-------
+ 1 file changed, 61 insertions(+), 41 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+index 8b2ee606dbc2..4808113b91be 100644
+--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
++++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+@@ -27,7 +27,6 @@
+ #include "opp.h"
+ #include "color_gamma.h"
+ 
+-
+ #define NUM_PTS_IN_REGION 16
+ #define NUM_REGIONS 32
+ #define MAX_HW_POINTS (NUM_PTS_IN_REGION*NUM_REGIONS)
+@@ -159,59 +158,68 @@ static void compute_de_pq(struct fixed31_32 in_x, struct fixed31_32 *out_y)
+ 
+ }
+ 
++
+ /*de gamma, none linear to linear*/
+-static void compute_hlg_oetf(struct fixed31_32 in_x, bool is_light0_12, struct fixed31_32 *out_y)
++static void compute_hlg_eotf(struct fixed31_32 in_x,
++		struct fixed31_32 *out_y,
++		uint32_t sdr_white_level, uint32_t max_luminance_nits)
+ {
+ 	struct fixed31_32 a;
+ 	struct fixed31_32 b;
+ 	struct fixed31_32 c;
+ 	struct fixed31_32 threshold;
+-	struct fixed31_32 reference_white_level;
++	struct fixed31_32 x;
+ 
++	struct fixed31_32 scaling_factor =
++			dc_fixpt_from_fraction(max_luminance_nits, sdr_white_level);
+ 	a = dc_fixpt_from_fraction(17883277, 100000000);
+-	if (is_light0_12) {
+-		/*light 0-12*/
+-		b = dc_fixpt_from_fraction(28466892, 100000000);
+-		c = dc_fixpt_from_fraction(55991073, 100000000);
+-		threshold = dc_fixpt_one;
+-		reference_white_level = dc_fixpt_half;
++	b = dc_fixpt_from_fraction(28466892, 100000000);
++	c = dc_fixpt_from_fraction(55991073, 100000000);
++	threshold = dc_fixpt_from_fraction(1, 2);
++
++	if (dc_fixpt_lt(in_x, threshold)) {
++		x = dc_fixpt_mul(in_x, in_x);
++		x = dc_fixpt_div_int(x, 3);
+ 	} else {
+-		/*light 0-1*/
+-		b = dc_fixpt_from_fraction(2372241, 100000000);
+-		c = dc_fixpt_add(dc_fixpt_one, dc_fixpt_from_fraction(429347, 100000000));
+-		threshold = dc_fixpt_from_fraction(1, 12);
+-		reference_white_level = dc_fixpt_pow(dc_fixpt_from_fraction(3, 1), dc_fixpt_half);
++		x = dc_fixpt_sub(in_x, c);
++		x = dc_fixpt_div(x, a);
++		x = dc_fixpt_exp(x);
++		x = dc_fixpt_add(x, b);
++		x = dc_fixpt_div_int(x, 12);
+ 	}
+-	if (dc_fixpt_lt(threshold, in_x))
+-		*out_y = dc_fixpt_add(c, dc_fixpt_mul(a, dc_fixpt_log(dc_fixpt_sub(in_x, b))));
+-	else
+-		*out_y = dc_fixpt_mul(dc_fixpt_pow(in_x, dc_fixpt_half), reference_white_level);
++	*out_y = dc_fixpt_mul(x, scaling_factor);
++
+ }
+ 
+ /*re gamma, linear to none linear*/
+-static void compute_hlg_eotf(struct fixed31_32 in_x, bool is_light0_12, struct fixed31_32 *out_y)
++static void compute_hlg_oetf(struct fixed31_32 in_x, struct fixed31_32 *out_y,
++		uint32_t sdr_white_level, uint32_t max_luminance_nits)
+ {
+ 	struct fixed31_32 a;
+ 	struct fixed31_32 b;
+ 	struct fixed31_32 c;
+-	struct fixed31_32 reference_white_level;
++	struct fixed31_32 threshold;
++	struct fixed31_32 x;
+ 
++	struct fixed31_32 scaling_factor =
++			dc_fixpt_from_fraction(sdr_white_level, max_luminance_nits);
+ 	a = dc_fixpt_from_fraction(17883277, 100000000);
+-	if (is_light0_12) {
+-		/*light 0-12*/
+-		b = dc_fixpt_from_fraction(28466892, 100000000);
+-		c = dc_fixpt_from_fraction(55991073, 100000000);
+-		reference_white_level = dc_fixpt_from_fraction(4, 1);
++	b = dc_fixpt_from_fraction(28466892, 100000000);
++	c = dc_fixpt_from_fraction(55991073, 100000000);
++	threshold = dc_fixpt_from_fraction(1, 12);
++	x = dc_fixpt_mul(in_x, scaling_factor);
++
++
++	if (dc_fixpt_lt(x, threshold)) {
++		x = dc_fixpt_mul(x, dc_fixpt_from_fraction(3, 1));
++		*out_y = dc_fixpt_pow(x, dc_fixpt_half);
+ 	} else {
+-		/*light 0-1*/
+-		b = dc_fixpt_from_fraction(2372241, 100000000);
+-		c = dc_fixpt_add(dc_fixpt_one, dc_fixpt_from_fraction(429347, 100000000));
+-		reference_white_level = dc_fixpt_from_fraction(1, 3);
++		x = dc_fixpt_mul(x, dc_fixpt_from_fraction(12, 1));
++		x = dc_fixpt_sub(x, b);
++		x = dc_fixpt_log(x);
++		x = dc_fixpt_mul(a, x);
++		*out_y = dc_fixpt_add(x, c);
+ 	}
+-	if (dc_fixpt_lt(dc_fixpt_half, in_x))
+-		*out_y = dc_fixpt_add(dc_fixpt_exp(dc_fixpt_div(dc_fixpt_sub(in_x, c), a)), b);
+-	else
+-		*out_y = dc_fixpt_mul(dc_fixpt_pow(in_x, dc_fixpt_from_fraction(2, 1)), reference_white_level);
+ }
+ 
+ 
+@@ -997,9 +1005,14 @@ static bool build_degamma(struct pwl_float_data_ex *curve,
+ 	return ret;
+ }
+ 
++
++
++
++
+ static void build_hlg_degamma(struct pwl_float_data_ex *degamma,
+ 		uint32_t hw_points_num,
+-		const struct hw_x_point *coordinate_x, bool is_light0_12)
++		const struct hw_x_point *coordinate_x,
++		uint32_t sdr_white_level, uint32_t max_luminance_nits)
+ {
+ 	uint32_t i;
+ 
+@@ -1007,9 +1020,9 @@ static void build_hlg_degamma(struct pwl_float_data_ex *degamma,
+ 	const struct hw_x_point *coord_x = coordinate_x;
+ 
+ 	i = 0;
+-
++	//check when i == 434
+ 	while (i != hw_points_num + 1) {
+-		compute_hlg_oetf(coord_x->x, is_light0_12, &rgb->r);
++		compute_hlg_eotf(coord_x->x, &rgb->r, sdr_white_level, max_luminance_nits);
+ 		rgb->g = rgb->r;
+ 		rgb->b = rgb->r;
+ 		++coord_x;
+@@ -1018,9 +1031,11 @@ static void build_hlg_degamma(struct pwl_float_data_ex *degamma,
+ 	}
+ }
+ 
++
+ static void build_hlg_regamma(struct pwl_float_data_ex *regamma,
+ 		uint32_t hw_points_num,
+-		const struct hw_x_point *coordinate_x, bool is_light0_12)
++		const struct hw_x_point *coordinate_x,
++		uint32_t sdr_white_level, uint32_t max_luminance_nits)
+ {
+ 	uint32_t i;
+ 
+@@ -1029,8 +1044,9 @@ static void build_hlg_regamma(struct pwl_float_data_ex *regamma,
+ 
+ 	i = 0;
+ 
++	//when i == 471
+ 	while (i != hw_points_num + 1) {
+-		compute_hlg_eotf(coord_x->x, is_light0_12, &rgb->r);
++		compute_hlg_oetf(coord_x->x, &rgb->r, sdr_white_level, max_luminance_nits);
+ 		rgb->g = rgb->r;
+ 		rgb->b = rgb->r;
+ 		++coord_x;
+@@ -1916,7 +1932,7 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf,
+ 		build_hlg_degamma(curve,
+ 				MAX_HW_POINTS,
+ 				coordinates_x,
+-				true);
++				80, 1000);
+ 	else if (tf == TRANSFER_FUNCTION_LINEAR) {
+ 		// just copy coordinates_x into curve
+ 		i = 0;
+@@ -2035,11 +2051,15 @@ bool  mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
+ 				       GFP_KERNEL);
+ 		if (!rgb_regamma)
+ 			goto rgb_regamma_alloc_fail;
++		points->end_exponent = 4;
++		points->x_point_at_y1_red = 12;
++		points->x_point_at_y1_green = 12;
++		points->x_point_at_y1_blue = 12;
+ 
+ 		build_hlg_regamma(rgb_regamma,
+ 				MAX_HW_POINTS,
+ 				coordinates_x,
+-				true);
++				80, 1000);
+ 		for (i = 0; i <= MAX_HW_POINTS ; i++) {
+ 			points->red[i]    = rgb_regamma[i].r;
+ 			points->green[i]  = rgb_regamma[i].g;
+@@ -2121,7 +2141,7 @@ bool  mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
+ 		build_hlg_degamma(rgb_degamma,
+ 				MAX_HW_POINTS,
+ 				coordinates_x,
+-				true);
++				80, 1000);
+ 		for (i = 0; i <= MAX_HW_POINTS ; i++) {
+ 			points->red[i]    = rgb_degamma[i].r;
+ 			points->green[i]  = rgb_degamma[i].g;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3415-drm-amd-display-Change-DSC-policy-from-slices-per-co.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3415-drm-amd-display-Change-DSC-policy-from-slices-per-co.patch
new file mode 100644
index 00000000..0ef18026
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3415-drm-amd-display-Change-DSC-policy-from-slices-per-co.patch
@@ -0,0 +1,143 @@
+From d7f3cd93b7ddc53ec4e1e1c1a7cfaa00025008c3 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Thu, 18 Jul 2019 19:13:26 -0400
+Subject: [PATCH 3415/4256] drm/amd/display: Change DSC policy from slices per
+ column to minimum slice height
+
+[why] Minimum slice height is recommended by VESA DSC Spreadsheet user guide
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 71 ++++++++++-----------
+ 1 file changed, 32 insertions(+), 39 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+index ef5f84a144c3..5995bcdfed54 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+@@ -28,6 +28,23 @@
+ #include "dsc.h"
+ #include <drm/drm_dp_helper.h>
+ 
++struct dc_dsc_policy {
++	bool use_min_slices_h;
++	int max_slices_h; // Maximum available if 0
++	int min_sice_height; // Must not be less than 8
++	int max_target_bpp;
++	int min_target_bpp; // Minimum target bits per pixel
++};
++
++const struct dc_dsc_policy dsc_policy = {
++	.use_min_slices_h = true, // DSC Policy: Use minimum number of slices that fits the pixel clock
++	.max_slices_h = 0, // DSC Policy: Use max available slices (in our case 4 for or 8, depending on the mode)
++	.min_sice_height = 108, // DSC Policy: Use slice height recommended by VESA DSC Spreadsheet user guide
++	.max_target_bpp = 16,
++	.min_target_bpp = 8,
++};
++
++
+ /* This module's internal functions */
+ 
+ static bool dsc_buff_block_size_from_dpcd(int dpcd_buff_block_size, int *buff_block_size)
+@@ -241,14 +258,6 @@ static bool intersect_dsc_caps(
+ 	return true;
+ }
+ 
+-struct dc_dsc_policy {
+-	bool use_min_slices_h;
+-	int max_slices_h; // Maximum available if 0
+-	int num_slices_v;
+-	int max_target_bpp;
+-	int min_target_bpp; // Minimum target bits per pixel
+-};
+-
+ static inline uint32_t dsc_div_by_10_round_up(uint32_t value)
+ {
+ 	return (value + 9) / 10;
+@@ -270,19 +279,6 @@ static inline uint32_t calc_dsc_bpp_x16(uint32_t stream_bandwidth_kbps, uint32_t
+ 	return dsc_target_bpp_x16;
+ }
+ 
+-const struct dc_dsc_policy dsc_policy = {
+-	.use_min_slices_h = true, // DSC Policy: Use minimum number of slices that fits the pixel clock
+-	.max_slices_h = 0, // DSC Policy: Use max available slices (in our case 4 for or 8, depending on the mode)
+-	/* DSC Policy: Number of vertical slices set to 2 for no particular reason.
+-	 * Seems small enough to not affect the quality too much, while still providing some error
+-	 * propagation control (which may also help debugging).
+-	 */
+-	.num_slices_v = 16,
+-	.max_target_bpp = 16,
+-	.min_target_bpp = 8,
+-};
+-
+-
+ /* Get DSC bandwidth range based on [min_bpp, max_bpp] target bitrate range, and timing's pixel clock
+  * and uncompressed bandwidth.
+  */
+@@ -528,8 +524,8 @@ static bool setup_dsc_config(
+ 	int sink_per_slice_throughput_mps;
+ 	int branch_max_throughput_mps = 0;
+ 	bool is_dsc_possible = false;
+-	int num_slices_v;
+ 	int pic_height;
++	int slice_height;
+ 
+ 	memset(dsc_cfg, 0, sizeof(struct dc_dsc_config));
+ 
+@@ -615,7 +611,7 @@ static bool setup_dsc_config(
+ 	if (!is_dsc_possible)
+ 		goto done;
+ 
+-	// DSC slicing
++	// Slice width (i.e. number of slices per line)
+ 	max_slices_h = get_max_dsc_slices(dsc_common_caps.slice_caps);
+ 
+ 	while (max_slices_h > 0) {
+@@ -678,29 +674,26 @@ static bool setup_dsc_config(
+ 	dsc_cfg->num_slices_h = num_slices_h;
+ 	slice_width = pic_width / num_slices_h;
+ 
+-	// Vertical number of slices: start from policy and pick the first one that height is divisible by.
++	is_dsc_possible = slice_width <= dsc_common_caps.max_slice_width;
++	if (!is_dsc_possible)
++		goto done;
++
++	// Slice height (i.e. number of slices per column): start with policy and pick the first one that height is divisible by.
+ 	// For 4:2:0 make sure the slice height is divisible by 2 as well.
+-	num_slices_v = dsc_policy.num_slices_v;
+-	if (num_slices_v < 1)
+-		num_slices_v = 1;
+-
+-	while (num_slices_v >= 1) {
+-		if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
+-			int slice_height = pic_height / num_slices_v;
+-			if (pic_height % num_slices_v == 0 && slice_height % 2 == 0)
+-				break;
+-		} else if (pic_height % num_slices_v == 0)
+-			break;
++	slice_height = min(dsc_policy.min_sice_height, pic_height);
+ 
+-		num_slices_v--;
+-	}
++	while (slice_height < pic_height && (pic_height % slice_height != 0 ||
++		(timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 && slice_height % 2 != 0)))
++		slice_height++;
+ 
+-	dsc_cfg->num_slices_v = num_slices_v;
++	if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) // For the case when pic_height < dsc_policy.min_sice_height
++		is_dsc_possible = (slice_height % 2 == 0);
+ 
+-	is_dsc_possible = slice_width <= dsc_common_caps.max_slice_width;
+ 	if (!is_dsc_possible)
+ 		goto done;
+ 
++	dsc_cfg->num_slices_v = pic_height/slice_height;
++
+ 	// Final decission: can we do DSC or not?
+ 	if (is_dsc_possible) {
+ 		// Fill out the rest of DSC settings
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3416-drm-amd-display-Set-DSC-before-DIG-front-end-is-conn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3416-drm-amd-display-Set-DSC-before-DIG-front-end-is-conn.patch
new file mode 100644
index 00000000..bb89323b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3416-drm-amd-display-Set-DSC-before-DIG-front-end-is-conn.patch
@@ -0,0 +1,566 @@
+From 17f4668db8e266746de89547d36a046457d090ae Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Wed, 17 Jul 2019 19:02:14 -0400
+Subject: [PATCH 3416/4256] drm/amd/display: Set DSC before DIG front-end is
+ connected to its back-end
+
+[why]
+At the time DIG FE is connected to its BE, the clocks in OTG are enabled and
+PHY will also be set up. When DSC has to be used to fit the stream into the
+available bandwidth, without DSC being set DIG could get exposed to the
+higer bandwidth it (or link) could handle. This causes the HW to "reject"
+video enable setup (the register shows that video enable was attempted, but
+the status bit shows it as disabled).
+
+[how]
+- Separate DSC setup into DSC register config and DSC PPS SDP setup
+
+- Move most of the DSC setup (register config) to before
+  dcn10_link_encoder_connect_dig_be_to_fe() is  called
+
+- Set up DSC PPS SDP after DIG FE is connected to its BE. This is because
+  setting DSC PPS SDP before that has no effect.
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c |  20 ++--
+ .../drm/amd/display/dc/core/dc_link_hwss.c    |  78 +++++++++++---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c  | 100 ++++++++++--------
+ .../display/dc/dcn20/dcn20_stream_encoder.c   |  25 +++--
+ .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |   3 +-
+ drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h   |   4 +-
+ .../amd/display/dc/inc/hw/stream_encoder.h    |  12 ++-
+ 7 files changed, 158 insertions(+), 84 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 9fe324dbbe91..10b24af73c51 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2725,21 +2725,27 @@ void core_link_enable_stream(
+ 					CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
+ 					COLOR_DEPTH_UNDEFINED);
+ 
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++		if (pipe_ctx->stream->timing.flags.DSC) {
++			if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
++					dc_is_virtual_signal(pipe_ctx->stream->signal))
++				dp_set_dsc_enable(pipe_ctx, true);
++		}
++#endif
+ 		core_dc->hwss.enable_stream(pipe_ctx);
+ 
+-		if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
+-			allocate_mst_payload(pipe_ctx);
+-
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++		/* Set DPS PPS SDP (AKA "info frames") */
+ 		if (pipe_ctx->stream->timing.flags.DSC) {
+ 			if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+ 					dc_is_virtual_signal(pipe_ctx->stream->signal))
+-				dp_set_dsc_enable(pipe_ctx, true);
+-			pipe_ctx->stream_res.tg->funcs->wait_for_state(
+-					pipe_ctx->stream_res.tg,
+-					CRTC_STATE_VBLANK);
++				dp_set_dsc_pps_sdp(pipe_ctx, true);
+ 		}
+ #endif
++
++		if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
++			allocate_mst_payload(pipe_ctx);
++
+ 		core_dc->hwss.unblank_stream(pipe_ctx,
+ 			&pipe_ctx->stream->link->cur_link_settings);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index daaff7319413..af65071b6cf5 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -361,9 +361,10 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
+ 	return result;
+ }
+ 
+-/* This has to be done after DSC was enabled on RX first, i.e. after dp_enable_dsc_on_rx() had been called
++/* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first,
++ * i.e. after dp_enable_dsc_on_rx() had been called
+  */
+-void set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
++void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ {
+ 	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
+ 	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
+@@ -371,11 +372,9 @@ void set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ 	struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
+ 
+ 	if (enable) {
+-		/* TODO proper function */
+ 		struct dsc_config dsc_cfg;
+ 		struct dsc_optc_config dsc_optc_cfg;
+ 		enum optc_dsc_mode optc_dsc_mode;
+-		uint8_t dsc_packed_pps[128];
+ 
+ 		/* Enable DSC hw block */
+ 		dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
+@@ -384,19 +383,20 @@ void set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ 		dsc_cfg.color_depth = stream->timing.display_color_depth;
+ 		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
+ 
+-		dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg, &dsc_packed_pps[0]);
+ 		if (odm_pipe) {
+ 			struct display_stream_compressor *bot_dsc = odm_pipe->stream_res.dsc;
+-			uint8_t dsc_packed_pps_odm[128];
+ 
+ 			dsc_cfg.pic_width /= 2;
+ 			ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % 2 == 0);
+ 			dsc_cfg.dc_dsc_cfg.num_slices_h /= 2;
+-			dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg, &dsc_packed_pps_odm[0]);
+-			bot_dsc->funcs->dsc_set_config(bot_dsc, &dsc_cfg, &dsc_optc_cfg, &dsc_packed_pps_odm[0]);
++			dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
++			bot_dsc->funcs->dsc_set_config(bot_dsc, &dsc_cfg, &dsc_optc_cfg);
++			dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
+ 			bot_dsc->funcs->dsc_enable(bot_dsc, odm_pipe->stream_res.opp->inst);
++		} else {
++			dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
++			dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
+ 		}
+-		dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
+ 
+ 		optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
+ 
+@@ -406,8 +406,9 @@ void set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ 			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,
+ 									optc_dsc_mode,
+ 									dsc_optc_cfg.bytes_per_pixel,
+-									dsc_optc_cfg.slice_width,
+-									&dsc_packed_pps[0]);
++									dsc_optc_cfg.slice_width);
++
++			/* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */
+ 
+ 		/* Enable DSC in OPTC */
+ 		pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
+@@ -421,10 +422,14 @@ void set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ 				OPTC_DSC_DISABLED, 0, 0);
+ 
+ 		/* disable DSC in stream encoder */
+-		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
++		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
+ 			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(
+ 					pipe_ctx->stream_res.stream_enc,
+-					OPTC_DSC_DISABLED, 0, 0, NULL);
++					OPTC_DSC_DISABLED, 0, 0);
++
++			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
++					pipe_ctx->stream_res.stream_enc, false, NULL);
++		}
+ 
+ 		/* disable DSC block */
+ 		pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
+@@ -445,18 +450,57 @@ bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)
+ 
+ 	if (enable) {
+ 		if (dp_set_dsc_on_rx(pipe_ctx, true)) {
+-			set_dsc_on_stream(pipe_ctx, true);
++			dp_set_dsc_on_stream(pipe_ctx, true);
+ 			result = true;
+ 		}
+ 	} else {
+ 		dp_set_dsc_on_rx(pipe_ctx, false);
+-		set_dsc_on_stream(pipe_ctx, false);
++		dp_set_dsc_on_stream(pipe_ctx, false);
+ 		result = true;
+ 	}
+ out:
+ 	return result;
+ }
+ 
++bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
++{
++	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
++	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
++	struct dc_stream_state *stream = pipe_ctx->stream;
++
++	if (!pipe_ctx->stream->timing.flags.DSC || !dsc)
++		return false;
++
++	if (enable) {
++		struct dsc_config dsc_cfg;
++		uint8_t dsc_packed_pps[128];
++
++		/* Enable DSC hw block */
++		dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
++		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
++		dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
++		dsc_cfg.color_depth = stream->timing.display_color_depth;
++		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
++
++		dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);
++		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
++			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
++									pipe_ctx->stream_res.stream_enc,
++									true,
++									&dsc_packed_pps[0]);
++
++	} else {
++		/* disable DSC PPS in stream encoder */
++		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
++						pipe_ctx->stream_res.stream_enc, false, NULL);
++		}
++	}
++
++	return true;
++}
++
++
+ bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx)
+ {
+ 	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
+@@ -466,9 +510,9 @@ bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx)
+ 	if (!dsc)
+ 		return false;
+ 
+-	set_dsc_on_stream(pipe_ctx, true);
++	dp_set_dsc_on_stream(pipe_ctx, true);
++	dp_set_dsc_pps_sdp(pipe_ctx, true);
+ 	return true;
+ }
+-
+ #endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+index e870caa8d4fa..e4d184cdea82 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+@@ -29,7 +29,7 @@
+ #include "dsc/dscc_types.h"
+ 
+ static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps);
+-static bool dsc_prepare_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
++static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,
+ 			struct dsc_optc_config *dsc_optc_cfg);
+ static void dsc_init_reg_values(struct dsc_reg_values *reg_vals);
+ static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params);
+@@ -42,7 +42,8 @@ static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock
+ static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
+ static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
+ static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
+-		struct dsc_optc_config *dsc_optc_cfg, uint8_t *dsc_packed_pps);
++		struct dsc_optc_config *dsc_optc_cfg);
++static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps);
+ static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe);
+ static void dsc2_disable(struct display_stream_compressor *dsc);
+ 
+@@ -51,6 +52,7 @@ const struct dsc_funcs dcn20_dsc_funcs = {
+ 	.dsc_read_state = dsc2_read_state,
+ 	.dsc_validate_stream = dsc2_validate_stream,
+ 	.dsc_set_config = dsc2_set_config,
++	.dsc_get_packed_pps = dsc2_get_packed_pps,
+ 	.dsc_enable = dsc2_enable,
+ 	.dsc_disable = dsc2_disable,
+ };
+@@ -162,18 +164,17 @@ static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_ds
+ static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)
+ {
+ 	struct dsc_optc_config dsc_optc_cfg;
++	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
+ 
+-	if (dsc_cfg->pic_width > TO_DCN20_DSC(dsc)->max_image_width)
++	if (dsc_cfg->pic_width > dsc20->max_image_width)
+ 		return false;
+ 
+-	return dsc_prepare_config(dsc, dsc_cfg, &dsc_optc_cfg);
++	return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg);
+ }
+ 
+ 
+-static void dsc_config_log(struct display_stream_compressor *dsc,
+-		const struct dsc_config *config)
++static void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config)
+ {
+-	DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
+ 	DC_LOG_DSC("\n\tnum_slices_h %d\n\tnum_slices_v %d\n\tbits_per_pixel %d\n\tcolor_depth %d",
+ 		config->dc_dsc_cfg.num_slices_h,
+ 		config->dc_dsc_cfg.num_slices_v,
+@@ -182,20 +183,37 @@ static void dsc_config_log(struct display_stream_compressor *dsc,
+ }
+ 
+ static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
+-		struct dsc_optc_config *dsc_optc_cfg, uint8_t *dsc_packed_pps)
++		struct dsc_optc_config *dsc_optc_cfg)
+ {
+ 	bool is_config_ok;
+ 	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
+ 
++	DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
+ 	dsc_config_log(dsc, dsc_cfg);
+-	is_config_ok = dsc_prepare_config(dsc, dsc_cfg, dsc_optc_cfg);
++	is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg);
+ 	ASSERT(is_config_ok);
+-	drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc20->reg_vals.pps);
+ 	dsc_log_pps(dsc, &dsc20->reg_vals.pps);
+ 	dsc_write_to_registers(dsc, &dsc20->reg_vals);
+ }
+ 
+ 
++static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps)
++{
++	bool is_config_ok;
++	struct dsc_reg_values dsc_reg_vals;
++	struct dsc_optc_config dsc_optc_cfg;
++
++	DC_LOG_DSC("Packed DSC PPS for DSC Config:");
++	dsc_config_log(dsc, dsc_cfg);
++	is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg);
++	ASSERT(is_config_ok);
++	drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps);
++	dsc_log_pps(dsc, &dsc_reg_vals.pps);
++
++	return is_config_ok;
++}
++
++
+ static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)
+ {
+ 	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
+@@ -282,13 +300,11 @@ static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_co
+ 	}
+ }
+ 
+-static bool dsc_prepare_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
++static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,
+ 			struct dsc_optc_config *dsc_optc_cfg)
+ {
+ 	struct dsc_parameters dsc_params;
+ 
+-	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
+-
+ 	/* Validate input parameters */
+ 	ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h);
+ 	ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v);
+@@ -315,54 +331,54 @@ static bool dsc_prepare_config(struct display_stream_compressor *dsc, const stru
+ 		return false;
+ 	}
+ 
+-	dsc_init_reg_values(&dsc20->reg_vals);
++	dsc_init_reg_values(dsc_reg_vals);
+ 
+ 	/* Copy input config */
+-	dsc20->reg_vals.pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple);
+-	dsc20->reg_vals.num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h;
+-	dsc20->reg_vals.num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v;
+-	dsc20->reg_vals.pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor;
+-	dsc20->reg_vals.pps.pic_width = dsc_cfg->pic_width;
+-	dsc20->reg_vals.pps.pic_height = dsc_cfg->pic_height;
+-	dsc20->reg_vals.pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth);
+-	dsc20->reg_vals.pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable;
+-	dsc20->reg_vals.pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth;
+-	dsc20->reg_vals.alternate_ich_encoding_en = dsc20->reg_vals.pps.dsc_version_minor == 1 ? 0 : 1;
++	dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple);
++	dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h;
++	dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v;
++	dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor;
++	dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width;
++	dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height;
++	dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth);
++	dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable;
++	dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth;
++	dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1;
+ 
+ 	// TODO: in addition to validating slice height (pic height must be divisible by slice height),
+ 	// see what happens when the same condition doesn't apply for slice_width/pic_width.
+-	dsc20->reg_vals.pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h;
+-	dsc20->reg_vals.pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;
++	dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h;
++	dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;
+ 
+-	ASSERT(dsc20->reg_vals.pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
+-	if (!(dsc20->reg_vals.pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {
++	ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
++	if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {
+ 		dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v);
+ 		return false;
+ 	}
+ 
+-	dsc20->reg_vals.bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1;
+-	if (dsc20->reg_vals.pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc20->reg_vals.pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
+-		dsc20->reg_vals.pps.bits_per_pixel = dsc20->reg_vals.bpp_x32;
++	dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1;
++	if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
++		dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32;
+ 	else
+-		dsc20->reg_vals.pps.bits_per_pixel = dsc20->reg_vals.bpp_x32 >> 1;
++		dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1;
+ 
+-	dsc20->reg_vals.pps.convert_rgb = dsc20->reg_vals.pixel_format == DSC_PIXFMT_RGB ? 1 : 0;
+-	dsc20->reg_vals.pps.native_422 = (dsc20->reg_vals.pixel_format == DSC_PIXFMT_NATIVE_YCBCR422);
+-	dsc20->reg_vals.pps.native_420 = (dsc20->reg_vals.pixel_format == DSC_PIXFMT_NATIVE_YCBCR420);
+-	dsc20->reg_vals.pps.simple_422 = (dsc20->reg_vals.pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422);
++	dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0;
++	dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422);
++	dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420);
++	dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422);
+ 
+-	if (dscc_compute_dsc_parameters(&dsc20->reg_vals.pps, &dsc_params)) {
++	if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &dsc_params)) {
+ 		dm_output_to_console("%s: DSC config failed\n", __func__);
+ 		return false;
+ 	}
+ 
+-	dsc_update_from_dsc_parameters(&dsc20->reg_vals, &dsc_params);
++	dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params);
+ 
+ 	dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel;
+-	dsc_optc_cfg->slice_width = dsc20->reg_vals.pps.slice_width;
+-	dsc_optc_cfg->is_pixel_format_444 = dsc20->reg_vals.pixel_format == DSC_PIXFMT_RGB ||
+-					dsc20->reg_vals.pixel_format == DSC_PIXFMT_YCBCR444 ||
+-					dsc20->reg_vals.pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422;
++	dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width;
++	dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ||
++					dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 ||
++					dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422;
+ 
+ 	return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+index a2f15387e946..6d54942ab98b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+@@ -205,9 +205,8 @@ static void enc2_stream_encoder_stop_hdmi_info_packets(
+ 
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 
+-
+ /* Update GSP7 SDP 128 byte long */
+-static void enc2_send_gsp7_128_info_packet(
++static void enc2_update_gsp7_128_info_packet(
+ 	struct dcn10_stream_encoder *enc1,
+ 	const struct dc_info_packet_128 *info_packet)
+ {
+@@ -275,8 +274,7 @@ static void enc2_send_gsp7_128_info_packet(
+ static void enc2_dp_set_dsc_config(struct stream_encoder *enc,
+ 					enum optc_dsc_mode dsc_mode,
+ 					uint32_t dsc_bytes_per_pixel,
+-					uint32_t dsc_slice_width,
+-					uint8_t *dsc_packed_pps)
++					uint32_t dsc_slice_width)
+ {
+ 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+ 	uint32_t dsc_value = 0;
+@@ -294,8 +292,16 @@ static void enc2_dp_set_dsc_config(struct stream_encoder *enc,
+ 
+ 	REG_SET(DP_DSC_BYTES_PER_PIXEL, 0,
+ 		DP_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
++}
++
++
++static void enc2_dp_set_dsc_pps_info_packet(struct stream_encoder *enc,
++					bool enable,
++					uint8_t *dsc_packed_pps)
++{
++	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+ 
+-	if (dsc_mode != OPTC_DSC_DISABLED) {
++	if (enable) {
+ 		struct dc_info_packet_128 pps_sdp;
+ 
+ 		ASSERT(dsc_packed_pps);
+@@ -307,7 +313,7 @@ static void enc2_dp_set_dsc_config(struct stream_encoder *enc,
+ 		pps_sdp.hb2 = 127;
+ 		pps_sdp.hb3 = 0;
+ 		memcpy(&pps_sdp.sb[0], dsc_packed_pps, sizeof(pps_sdp.sb));
+-		enc2_send_gsp7_128_info_packet(enc1, &pps_sdp);
++		enc2_update_gsp7_128_info_packet(enc1, &pps_sdp);
+ 
+ 		/* Enable Generic Stream Packet 7 (GSP) transmission */
+ 		//REG_UPDATE(DP_SEC_CNTL,
+@@ -338,9 +344,8 @@ static void enc2_dp_set_dsc_config(struct stream_encoder *enc,
+ 		REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 0);
+ 	}
+ }
+-#endif
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++
+ /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
+  * into a dcn_dsc_state struct.
+  */
+@@ -581,10 +586,8 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = {
+ 	.dig_source_otg = enc1_dig_source_otg,
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	.enc_read_state = enc2_read_state,
+-#endif
+-
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	.dp_set_dsc_config = enc2_dp_set_dsc_config,
++	.dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet,
+ #endif
+ 	.set_dynamic_metadata = enc2_set_dynamic_metadata,
+ 	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+index 2ef23963e1f7..b4e7b0c56f83 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+@@ -69,7 +69,8 @@ void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);
+ void dp_set_fec_ready(struct dc_link *link, bool ready);
+ void dp_set_fec_enable(struct dc_link *link, bool enable);
+ bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
+-void set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
++bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
++void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
+ bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
+ #endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
+index c905d020b59e..1ddb1c6fa149 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
+@@ -92,7 +92,9 @@ struct dsc_funcs {
+ 	void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
+ 	bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
+ 	void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
+-			struct dsc_optc_config *dsc_optc_cfg, uint8_t *dsc_packed_pps);
++			struct dsc_optc_config *dsc_optc_cfg);
++	bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
++			uint8_t *dsc_packed_pps);
+ 	void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe);
+ 	void (*dsc_disable)(struct display_stream_compressor *dsc);
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+index 067ba6fc04c1..8bb3e3d56ac9 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+@@ -122,9 +122,6 @@ struct enc_state {
+ #endif
+ 
+ struct stream_encoder_funcs {
+-	#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-		void (*enc_read_state)(struct stream_encoder *enc, struct enc_state *s);
+-	#endif
+ 	void (*dp_set_stream_attribute)(
+ 		struct stream_encoder *enc,
+ 		struct dc_crtc_timing *crtc_timing,
+@@ -219,12 +216,17 @@ struct stream_encoder_funcs {
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	void (*enc_read_state)(struct stream_encoder *enc, struct enc_state *s);
++
+ 	void (*dp_set_dsc_config)(
+ 			struct stream_encoder *enc,
+ 			enum optc_dsc_mode dsc_mode,
+ 			uint32_t dsc_bytes_per_pixel,
+-			uint32_t dsc_slice_width,
+-			uint8_t *dsc_packed_pps);
++			uint32_t dsc_slice_width);
++
++	void (*dp_set_dsc_pps_info_packet)(struct stream_encoder *enc,
++				bool enable,
++				uint8_t *dsc_packed_pps);
+ #endif
+ 
+ 	void (*set_dynamic_metadata)(struct stream_encoder *enc,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3417-drm-amd-display-3.2.44.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3417-drm-amd-display-3.2.44.patch
new file mode 100644
index 00000000..bab7b09c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3417-drm-amd-display-3.2.44.patch
@@ -0,0 +1,27 @@
+From 0868f46fb40e64f0886504574eb60837908db3ed Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Fri, 19 Jul 2019 17:41:56 -0400
+Subject: [PATCH 3417/4256] drm/amd/display: 3.2.44
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 32312827daae..a5cb2a246a0c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -42,7 +42,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.43"
++#define DC_VER "3.2.44"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3418-drm-amd-display-fix-pipe-selection-logic-in-validate.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3418-drm-amd-display-fix-pipe-selection-logic-in-validate.patch
new file mode 100644
index 00000000..683d8282
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3418-drm-amd-display-fix-pipe-selection-logic-in-validate.patch
@@ -0,0 +1,125 @@
+From fe94baa31d7dd52be4ab26f0688ee6ee05d48dd0 Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Mon, 22 Jul 2019 09:45:20 -0400
+Subject: [PATCH 3418/4256] drm/amd/display: fix pipe selection logic in
+ validate
+
+[why]
+Resource mapping done in dcn20_validate_bandwidth has a flaw:  When a full
+update is performed, the HWSS will only update the MPCC tree for the stream
+that is updated as opposed to all streams.  This means that when mapping pipes
+in validation, care must be taken to not change any existing mapping, otherwise it
+leads to partial hw programming
+
+[how]
+it's not strictly necessary to track which stream/mpcc tree is being updated, but
+rather it's sufficient to compare current and new state and just keep pipes that were
+previously already mapped unchanged.
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 72 ++++++++++++++++++-
+ 1 file changed, 70 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index af8ab57a8af5..bdd3478f80ee 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2126,6 +2126,74 @@ static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
+ }
+ #endif
+ 
++static struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
++		struct resource_context *res_ctx,
++		const struct resource_pool *pool,
++		const struct pipe_ctx *primary_pipe)
++{
++	struct pipe_ctx *secondary_pipe = NULL;
++
++	if (dc && primary_pipe) {
++		int j;
++		int preferred_pipe_idx = 0;
++
++		/* first check the prev dc state:
++		 * if this primary pipe has a bottom pipe in prev. state
++		 * and if the bottom pipe is still available (which it should be),
++		 * pick that pipe as secondary
++		 */
++		if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
++			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
++			if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
++				secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
++				secondary_pipe->pipe_idx = preferred_pipe_idx;
++			}
++		}
++
++		/*
++		 * if this primary pipe does not have a bottom pipe in prev. state
++		 * start backward and find a pipe that did not used to be a bottom pipe in
++		 * prev. dc state. This way we make sure we keep the same assignment as
++		 * last state and will not have to reprogram every pipe
++		 */
++		if (secondary_pipe == NULL) {
++			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
++				if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL) {
++					preferred_pipe_idx = j;
++
++					if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
++						secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
++						secondary_pipe->pipe_idx = preferred_pipe_idx;
++						break;
++					}
++				}
++			}
++		}
++		/*
++		 * We should never hit this assert unless assignments are shuffled around
++		 * if this happens we will prob. hit a vsync tdr
++		 */
++		ASSERT(secondary_pipe);
++		/*
++		 * search backwards for the second pipe to keep pipe
++		 * assignment more consistent
++		 */
++		if (secondary_pipe == NULL) {
++			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
++				preferred_pipe_idx = j;
++
++				if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
++					secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
++					secondary_pipe->pipe_idx = preferred_pipe_idx;
++					break;
++				}
++			}
++		}
++	}
++
++	return secondary_pipe;
++}
++
+ bool dcn20_fast_validate_bw(
+ 		struct dc *dc,
+ 		struct dc_state *context,
+@@ -2279,7 +2347,7 @@ bool dcn20_fast_validate_bw(
+ 		if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
+ 			context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
+ 		if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
+-			hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe);
++			hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
+ 			ASSERT(hsplit_pipe);
+ 			if (!dcn20_split_stream_for_combine(
+ 					&context->res_ctx, dc->res_pool,
+@@ -2320,7 +2388,7 @@ bool dcn20_fast_validate_bw(
+ 		if (need_split3d || need_split || force_split) {
+ 			if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
+ 				/* pipe not split previously needs split */
+-				hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe);
++				hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
+ 				ASSERT(hsplit_pipe || force_split);
+ 				if (!hsplit_pipe)
+ 					continue;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3419-drm-amd-display-Remove-duplicate-interface-for-progr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3419-drm-amd-display-Remove-duplicate-interface-for-progr.patch
new file mode 100644
index 00000000..40efbe58
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3419-drm-amd-display-Remove-duplicate-interface-for-progr.patch
@@ -0,0 +1,371 @@
+From c1b9fbe9b19ccfc47c880dac1ac65757584a8fa5 Mon Sep 17 00:00:00 2001
+From: Julian Parkin <julian.parkin@amd.com>
+Date: Mon, 15 Jul 2019 12:16:01 -0400
+Subject: [PATCH 3419/4256] drm/amd/display: Remove duplicate interface for
+ programming FB
+
+[Why]
+There are currently two interfaces for exactly the same thing:
+hupb_update_dchub in hupb and update_dchub in hubbub. The hubbub
+version is currently unused past dcn10, largely because the call
+from the dcn10 hardware sequencer does not call through the
+interface, so the hupb interface was used instead. This is
+confusing because of the duplicate code, the unused functions,
+and the fact that more that one block currently owns this set
+of registers.
+
+[How]
+Remove the hubp interface entirely, as well as the register
+declarations that are not longer needed because of this. Change
+the call site to always call the hubbub version through the
+interface. Fix the update_dchub function in dcn20_hubbub.c to
+program the correct registers for dcn20.
+
+Signed-off-by: Julian Parkin <julian.parkin@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 24 ------
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 +--
+ .../drm/amd/display/dc/dcn20/dcn20_hubbub.c   | 81 +++++++++++--------
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 76 -----------------
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 16 ----
+ drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |  3 -
+ 6 files changed, 50 insertions(+), 160 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+index 344e446e337d..91116b3d4b48 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+@@ -125,8 +125,6 @@
+ 	SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\
+ 	SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\
+ 	SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\
+-	SR(DCHUBBUB_SDPIF_FB_BASE),\
+-	SR(DCHUBBUB_SDPIF_FB_OFFSET),\
+ 	SRI(CURSOR_SETTINS, HUBPREQ, id), \
+ 	SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
+ 	SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
+@@ -226,14 +224,6 @@
+ 	uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; \
+ 	uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; \
+ 	uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; \
+-	uint32_t DCHUBBUB_SDPIF_FB_BASE; \
+-	uint32_t DCHUBBUB_SDPIF_FB_OFFSET; \
+-	uint32_t DCN_VM_FB_LOCATION_TOP; \
+-	uint32_t DCN_VM_FB_LOCATION_BASE; \
+-	uint32_t DCN_VM_FB_OFFSET; \
+-	uint32_t DCN_VM_AGP_BASE; \
+-	uint32_t DCN_VM_AGP_BOT; \
+-	uint32_t DCN_VM_AGP_TOP; \
+ 	uint32_t CURSOR_SETTINS; \
+ 	uint32_t CURSOR_SETTINGS; \
+ 	uint32_t CURSOR_SURFACE_ADDRESS_HIGH; \
+@@ -417,8 +407,6 @@
+ 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\
+-	HUBP_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\
+-	HUBP_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\
+@@ -593,18 +581,6 @@
+ 	type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\
+ 	type MC_VM_SYSTEM_APERTURE_LOW_ADDR;\
+ 	type MC_VM_SYSTEM_APERTURE_HIGH_ADDR;\
+-	type SDPIF_FB_TOP;\
+-	type SDPIF_FB_BASE;\
+-	type SDPIF_FB_OFFSET;\
+-	type SDPIF_AGP_BASE;\
+-	type SDPIF_AGP_BOT;\
+-	type SDPIF_AGP_TOP;\
+-	type FB_TOP;\
+-	type FB_BASE;\
+-	type FB_OFFSET;\
+-	type AGP_BASE;\
+-	type AGP_BOT;\
+-	type AGP_TOP;\
+ 	type DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
+ 	type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
+ 	type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 86f874bddd84..8fd2d51477ea 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2856,14 +2856,10 @@ static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
+ 
+ static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
+ {
+-	if (hws->ctx->dc->res_pool->hubbub != NULL) {
+-		struct hubp *hubp = hws->ctx->dc->res_pool->hubps[0];
++	struct hubbub *hubbub = hws->ctx->dc->res_pool->hubbub;
+ 
+-		if (hubp->funcs->hubp_update_dchub)
+-			hubp->funcs->hubp_update_dchub(hubp, dh_data);
+-		else
+-			hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
+-	}
++	/* In DCN, this programming sequence is owned by the hubbub */
++	hubbub->funcs->update_dchub(hubbub, dh_data);
+ }
+ 
+ static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+index cd101bbd8163..f13e039f8ef4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+@@ -398,54 +398,67 @@ void hubbub2_update_dchub(struct hubbub *hubbub,
+ {
+ 	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
+ 
+-	if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) {
+-		ASSERT(false);
+-		/*should not come here*/
++	if (REG(DCN_VM_FB_LOCATION_TOP) == 0)
+ 		return;
+-	}
+-	/* TODO: port code from dal2 */
++
+ 	switch (dh_data->fb_mode) {
+ 	case FRAME_BUFFER_MODE_ZFB_ONLY:
+ 		/*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
+-		REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP,
+-				SDPIF_FB_TOP, 0);
+-
+-		REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE,
+-				SDPIF_FB_BASE, 0x0FFFF);
+-
+-		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
+-				SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+-
+-		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
+-				SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+-
+-		REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
+-				SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
+-						dh_data->zfb_size_in_byte - 1) >> 22);
++		REG_UPDATE(DCN_VM_FB_LOCATION_TOP,
++				FB_TOP, 0);
++
++		REG_UPDATE(DCN_VM_FB_LOCATION_BASE,
++				FB_BASE, 0xFFFFFF);
++
++		/*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
++		REG_UPDATE(DCN_VM_AGP_BASE,
++				AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
++
++		/*This field defines the bottom range of the AGP aperture and represents the 24*/
++		/*MSBs, bits [47:24] of the 48 address bits*/
++		REG_UPDATE(DCN_VM_AGP_BOT,
++				AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
++
++		/*This field defines the top range of the AGP aperture and represents the 24*/
++		/*MSBs, bits [47:24] of the 48 address bits*/
++		REG_UPDATE(DCN_VM_AGP_TOP,
++				AGP_TOP, (dh_data->zfb_mc_base_addr +
++						dh_data->zfb_size_in_byte - 1) >> 24);
+ 		break;
+ 	case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
+ 		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
+ 
+-		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
+-				SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
++		/*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
++		REG_UPDATE(DCN_VM_AGP_BASE,
++				AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
+ 
+-		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
+-				SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
++		/*This field defines the bottom range of the AGP aperture and represents the 24*/
++		/*MSBs, bits [47:24] of the 48 address bits*/
++		REG_UPDATE(DCN_VM_AGP_BOT,
++				AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
+ 
+-		REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
+-				SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
+-						dh_data->zfb_size_in_byte - 1) >> 22);
++		/*This field defines the top range of the AGP aperture and represents the 24*/
++		/*MSBs, bits [47:24] of the 48 address bits*/
++		REG_UPDATE(DCN_VM_AGP_TOP,
++				AGP_TOP, (dh_data->zfb_mc_base_addr +
++						dh_data->zfb_size_in_byte - 1) >> 24);
+ 		break;
+ 	case FRAME_BUFFER_MODE_LOCAL_ONLY:
+-		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
+-		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
+-				SDPIF_AGP_BASE, 0);
++		/*Should not touch FB LOCATION (should be done by VBIOS)*/
++
++		/*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
++		REG_UPDATE(DCN_VM_AGP_BASE,
++				AGP_BASE, 0);
+ 
+-		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
+-				SDPIF_AGP_BOT, 0X03FFFF);
++		/*This field defines the bottom range of the AGP aperture and represents the 24*/
++		/*MSBs, bits [47:24] of the 48 address bits*/
++		REG_UPDATE(DCN_VM_AGP_BOT,
++				AGP_BOT, 0xFFFFFF);
+ 
+-		REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
+-				SDPIF_AGP_TOP, 0);
++		/*This field defines the top range of the AGP aperture and represents the 24*/
++		/*MSBs, bits [47:24] of the 48 address bits*/
++		REG_UPDATE(DCN_VM_AGP_TOP,
++				AGP_TOP, 0);
+ 		break;
+ 	default:
+ 		break;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+index 487de87b03eb..ac01e636ae27 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+@@ -40,81 +40,6 @@
+ #define FN(reg_name, field_name) \
+ 	hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
+ 
+-void hubp2_update_dchub(
+-	struct hubp *hubp,
+-	struct dchub_init_data *dh_data)
+-{
+-	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+-	if (REG(DCN_VM_FB_LOCATION_TOP) == 0)
+-		return;
+-
+-	switch (dh_data->fb_mode) {
+-	case FRAME_BUFFER_MODE_ZFB_ONLY:
+-		/*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
+-		REG_UPDATE(DCN_VM_FB_LOCATION_TOP,
+-				FB_TOP, 0);
+-
+-		REG_UPDATE(DCN_VM_FB_LOCATION_BASE,
+-				FB_BASE, 0xFFFFFF);
+-
+-		/*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
+-		REG_UPDATE(DCN_VM_AGP_BASE,
+-				AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
+-
+-		/*This field defines the bottom range of the AGP aperture and represents the 24*/
+-		/*MSBs, bits [47:24] of the 48 address bits*/
+-		REG_UPDATE(DCN_VM_AGP_BOT,
+-				AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
+-
+-		/*This field defines the top range of the AGP aperture and represents the 24*/
+-		/*MSBs, bits [47:24] of the 48 address bits*/
+-		REG_UPDATE(DCN_VM_AGP_TOP,
+-				AGP_TOP, (dh_data->zfb_mc_base_addr +
+-						dh_data->zfb_size_in_byte - 1) >> 24);
+-		break;
+-	case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
+-		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
+-
+-		/*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
+-		REG_UPDATE(DCN_VM_AGP_BASE,
+-				AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
+-
+-		/*This field defines the bottom range of the AGP aperture and represents the 24*/
+-		/*MSBs, bits [47:24] of the 48 address bits*/
+-		REG_UPDATE(DCN_VM_AGP_BOT,
+-				AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
+-
+-		/*This field defines the top range of the AGP aperture and represents the 24*/
+-		/*MSBs, bits [47:24] of the 48 address bits*/
+-		REG_UPDATE(DCN_VM_AGP_TOP,
+-				AGP_TOP, (dh_data->zfb_mc_base_addr +
+-						dh_data->zfb_size_in_byte - 1) >> 24);
+-		break;
+-	case FRAME_BUFFER_MODE_LOCAL_ONLY:
+-		/*Should not touch FB LOCATION (should be done by VBIOS)*/
+-
+-		/*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
+-		REG_UPDATE(DCN_VM_AGP_BASE,
+-				AGP_BASE, 0);
+-
+-		/*This field defines the bottom range of the AGP aperture and represents the 24*/
+-		/*MSBs, bits [47:24] of the 48 address bits*/
+-		REG_UPDATE(DCN_VM_AGP_BOT,
+-				AGP_BOT, 0xFFFFFF);
+-
+-		/*This field defines the top range of the AGP aperture and represents the 24*/
+-		/*MSBs, bits [47:24] of the 48 address bits*/
+-		REG_UPDATE(DCN_VM_AGP_TOP,
+-				AGP_TOP, 0);
+-		break;
+-	default:
+-		break;
+-	}
+-
+-	dh_data->dchub_initialzied = true;
+-	dh_data->dchub_info_valid = false;
+-}
+-
+ void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,
+ 		struct vm_system_aperture_param *apt)
+ {
+@@ -1321,7 +1246,6 @@ static struct hubp_funcs dcn20_hubp_funcs = {
+ 	.hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings,
+ 	.set_blank = hubp2_set_blank,
+ 	.dcc_control = hubp2_dcc_control,
+-	.hubp_update_dchub = hubp2_update_dchub,
+ 	.mem_program_viewport = min_set_viewport,
+ 	.set_cursor_attributes	= hubp2_cursor_set_attributes,
+ 	.set_cursor_position	= hubp2_cursor_set_position,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+index 1c53af4811e8..924699e5f443 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+@@ -38,12 +38,6 @@
+ 	SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\
+ 	SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id),\
+ 	SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id),\
+-	SR(DCN_VM_FB_LOCATION_TOP),\
+-	SR(DCN_VM_FB_LOCATION_BASE),\
+-	SR(DCN_VM_FB_OFFSET),\
+-	SR(DCN_VM_AGP_BASE),\
+-	SR(DCN_VM_AGP_BOT),\
+-	SR(DCN_VM_AGP_TOP),\
+ 	SRI(CURSOR_SETTINGS, HUBPREQ, id), \
+ 	SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \
+ 	SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \
+@@ -82,12 +76,6 @@
+ 	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\
+-	HUBP_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh),\
+-	HUBP_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh),\
+-	HUBP_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh),\
+-	HUBP_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh),\
+-	HUBP_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh),\
+-	HUBP_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
+ 	HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
+ 	HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
+@@ -222,10 +210,6 @@ void hubp2_setup_interdependent(
+ void hubp2_vready_at_or_After_vsync(struct hubp *hubp,
+ 		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
+ 
+-void hubp2_update_dchub(
+-		struct hubp *hubp,
+-		struct dchub_init_data *dh_data);
+-
+ void hubp2_cursor_set_attributes(
+ 		struct hubp *hubp,
+ 		const struct dc_cursor_attributes *attr);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+index 61cd4f8752c3..4993f134e747 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+@@ -111,9 +111,6 @@ struct hubp_funcs {
+ 
+ 	bool (*hubp_is_flip_pending)(struct hubp *hubp);
+ 
+-	void (*hubp_update_dchub)(struct hubp *hubp,
+-				struct dchub_init_data *dh_data);
+-
+ 	void (*set_blank)(struct hubp *hubp, bool blank);
+ 	void (*set_hubp_blank_en)(struct hubp *hubp, bool blank);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3420-drm-amd-display-Update-DML-parameters.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3420-drm-amd-display-Update-DML-parameters.patch
new file mode 100644
index 00000000..0f49d17f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3420-drm-amd-display-Update-DML-parameters.patch
@@ -0,0 +1,222 @@
+From 583c9f7ae716367cb1e623dfa492146a8ccf7bc2 Mon Sep 17 00:00:00 2001
+From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Date: Wed, 17 Jul 2019 18:33:48 -0400
+Subject: [PATCH 3420/4256] drm/amd/display: Update DML parameters
+
+[Why]
+Need to add DML struct members that were omitted in previous
+DML implemenations.
+
+[How]
+- Add missing enum values
+- Add missing struct members
+- Set new input values in the fetch functions
+
+Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/dml/display_mode_enums.h   | 22 ++++++++++++++-----
+ .../amd/display/dc/dml/display_mode_structs.h |  3 +++
+ .../drm/amd/display/dc/dml/display_mode_vba.c |  9 ++++++++
+ .../drm/amd/display/dc/dml/display_mode_vba.h | 18 +++++++++++++++
+ 4 files changed, 46 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+index 0c2fab1e93b6..1c97083b8d0b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+@@ -37,11 +37,14 @@ enum source_format_class {
+ 	dm_444_64 = 2,
+ 	dm_420_8 = 3,
+ 	dm_420_10 = 4,
+-	dm_422_8 = 5,
+-	dm_422_10 = 6,
+-	dm_444_8 = 7,
++	dm_420_12 = 5,
++	dm_422_8 = 6,
++	dm_422_10 = 7,
++	dm_444_8 = 8,
+ 	dm_mono_8 = dm_444_8,
+-	dm_mono_16 = dm_444_16
++	dm_mono_16 = dm_444_16,
++	dm_rgbe = 9,
++	dm_rgbe_alpha = 10,
+ };
+ enum output_bpc_class {
+ 	dm_out_6 = 0, dm_out_8 = 1, dm_out_10 = 2, dm_out_12 = 3, dm_out_16 = 4
+@@ -83,7 +86,7 @@ enum dm_swizzle_mode {
+ 	dm_sw_var_d_x = 30,
+ 	dm_sw_64kb_r_x,
+ 	dm_sw_gfx7_2d_thin_lvp,
+-	dm_sw_gfx7_2d_thin_gl
++	dm_sw_gfx7_2d_thin_gl,
+ };
+ enum lb_depth {
+ 	dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16 = 4,
+@@ -112,7 +115,8 @@ enum output_standard {
+ enum mpc_combine_affinity {
+ 	dm_mpc_always_when_possible,
+ 	dm_mpc_reduce_voltage,
+-	dm_mpc_reduce_voltage_and_clocks
++	dm_mpc_reduce_voltage_and_clocks,
++	dm_mpc_never
+ };
+ 
+ enum self_refresh_affinity {
+@@ -157,4 +161,10 @@ enum writeback_config {
+ 	dm_whole_buffer_for_single_stream_interleave,
+ };
+ 
++enum odm_combine_mode {
++	dm_odm_combine_mode_disabled,
++	dm_odm_combine_mode_2to1,
++	dm_odm_combine_mode_4to1,
++};
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+index ab34fd26702f..f4c1ef9046bf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+@@ -109,6 +109,9 @@ struct _vcs_dpi_soc_bounding_box_st {
+ 	int use_urgent_burst_bw;
+ 	unsigned int num_states;
+ 	struct _vcs_dpi_voltage_scaling_st clock_limits[MAX_CLOCK_LIMIT_STATES];
++	bool do_urgent_latency_adjustment;
++	double urgent_latency_adjustment_fabric_clock_component_us;
++	double urgent_latency_adjustment_fabric_clock_reference_mhz;
+ };
+ 
+ struct _vcs_dpi_ip_params_st {
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+index 88e63f16f7fc..bd634dce6f3a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+@@ -262,6 +262,13 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
+ 		//mode_lib->vba.DRAMSpeedPerState[i] = soc->clock_limits[i].dram_speed_mhz;
+ 		mode_lib->vba.MaxDispclk[i] = soc->clock_limits[i].dispclk_mhz;
+ 	}
++
++	mode_lib->vba.DoUrgentLatencyAdjustment =
++		soc->do_urgent_latency_adjustment;
++	mode_lib->vba.UrgentLatencyAdjustmentFabricClockComponent =
++		soc->urgent_latency_adjustment_fabric_clock_component_us;
++	mode_lib->vba.UrgentLatencyAdjustmentFabricClockReference =
++		soc->urgent_latency_adjustment_fabric_clock_reference_mhz;
+ }
+ 
+ static void fetch_ip_params(struct display_mode_lib *mode_lib)
+@@ -385,8 +392,10 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
+ 				src->viewport_y_c;
+ 		mode_lib->vba.PitchY[mode_lib->vba.NumberOfActivePlanes] = src->data_pitch;
+ 		mode_lib->vba.SurfaceHeightY[mode_lib->vba.NumberOfActivePlanes] = src->viewport_height;
++		mode_lib->vba.SurfaceWidthY[mode_lib->vba.NumberOfActivePlanes] = src->viewport_width;
+ 		mode_lib->vba.PitchC[mode_lib->vba.NumberOfActivePlanes] = src->data_pitch_c;
+ 		mode_lib->vba.SurfaceHeightC[mode_lib->vba.NumberOfActivePlanes] = src->viewport_height_c;
++		mode_lib->vba.SurfaceWidthC[mode_lib->vba.NumberOfActivePlanes] = src->viewport_width_c;
+ 		mode_lib->vba.DCCMetaPitchY[mode_lib->vba.NumberOfActivePlanes] = src->meta_pitch;
+ 		mode_lib->vba.DCCMetaPitchC[mode_lib->vba.NumberOfActivePlanes] = src->meta_pitch_c;
+ 		mode_lib->vba.HRatio[mode_lib->vba.NumberOfActivePlanes] = scl->hscl_ratio;
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+index 0347f74cda3a..52d2583b2f74 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+@@ -290,6 +290,7 @@ struct vba_vars_st {
+ 	double PixelClock[DC__NUM_DPP__MAX];
+ 	double PixelClockBackEnd[DC__NUM_DPP__MAX];
+ 	bool DCCEnable[DC__NUM_DPP__MAX];
++	bool FECEnable[DC__NUM_DPP__MAX];
+ 	unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
+ 	unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX];
+ 	enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
+@@ -317,6 +318,7 @@ struct vba_vars_st {
+ 	double DCCRate[DC__NUM_DPP__MAX];
+ 	double AverageDCCCompressionRate;
+ 	bool ODMCombineEnabled[DC__NUM_DPP__MAX];
++	enum odm_combine_mode ODMCombineTypeEnabled[DC__NUM_DPP__MAX];
+ 	double OutputBpp[DC__NUM_DPP__MAX];
+ 	bool DSCEnabled[DC__NUM_DPP__MAX];
+ 	unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX];
+@@ -395,6 +397,7 @@ struct vba_vars_st {
+ 	double FabricClockPerState[DC__VOLTAGE_STATES + 1];
+ 	double SOCCLKPerState[DC__VOLTAGE_STATES + 1];
+ 	double PHYCLKPerState[DC__VOLTAGE_STATES + 1];
++	double DTBCLKPerState[DC__VOLTAGE_STATES + 1];
+ 	double MaxDppclk[DC__VOLTAGE_STATES + 1];
+ 	double MaxDSCCLK[DC__VOLTAGE_STATES + 1];
+ 	double DRAMSpeedPerState[DC__VOLTAGE_STATES + 1];
+@@ -488,6 +491,7 @@ struct vba_vars_st {
+ 	unsigned int NoOfDPP[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
+ 	int NoOfDPPThisState[DC__NUM_DPP__MAX];
+ 	bool ODMCombineEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
++	bool ODMCombineTypeEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
+ 	unsigned int SwathWidthYThisState[DC__NUM_DPP__MAX];
+ 	unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
+ 	unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX];
+@@ -513,6 +517,7 @@ struct vba_vars_st {
+ 	bool DIOSupport[DC__VOLTAGE_STATES + 1];
+ 	bool NotEnoughDSCUnits[DC__VOLTAGE_STATES + 1];
+ 	bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1];
++	bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1];
+ 	double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES + 1];
+ 	bool ROBSupport[DC__VOLTAGE_STATES + 1];
+ 	bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES + 1][2];
+@@ -605,6 +610,7 @@ struct vba_vars_st {
+ 	double         MaximumSwathWidthLuma[DC__NUM_DPP__MAX];
+ 	double         MaximumSwathWidthChroma[DC__NUM_DPP__MAX];
+ 	bool odm_combine_dummy[DC__NUM_DPP__MAX];
++	enum odm_combine_mode odm_combine_mode_dummy[DC__NUM_DPP__MAX];
+ 	double         dummy1[DC__NUM_DPP__MAX];
+ 	double         dummy2[DC__NUM_DPP__MAX];
+ 	double         dummy3[DC__NUM_DPP__MAX];
+@@ -625,6 +631,11 @@ struct vba_vars_st {
+ 	unsigned int        dummyinteger10;
+ 	unsigned int        dummyinteger11;
+ 	unsigned int        dummyinteger12;
++	unsigned int        dummyintegerarr1[DC__NUM_DPP__MAX];
++	unsigned int        dummyintegerarr2[DC__NUM_DPP__MAX];
++	unsigned int        dummyintegerarr3[DC__NUM_DPP__MAX];
++	unsigned int        dummyintegerarr4[DC__NUM_DPP__MAX];
++	long                dummylongarr1[DC__NUM_DPP__MAX];
+ 	bool           dummysinglestring;
+ 	bool           SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
+ 	double         PlaneRequiredDISPCLKWithODMCombine2To1;
+@@ -633,6 +644,7 @@ struct vba_vars_st {
+ 	bool           LinkDSCEnable;
+ 	bool           ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES + 1];
+ 	bool ODMCombineEnableThisState[DC__NUM_DPP__MAX];
++	enum odm_combine_mode ODMCombineEnableTypeThisState[DC__NUM_DPP__MAX];
+ 	unsigned int   SwathWidthCThisState[DC__NUM_DPP__MAX];
+ 	bool           ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
+ 	double         AlignedDCCMetaPitchY[DC__NUM_DPP__MAX];
+@@ -641,6 +653,7 @@ struct vba_vars_st {
+ 	unsigned int NotEnoughUrgentLatencyHiding;
+ 	unsigned int NotEnoughUrgentLatencyHidingPre;
+ 	long PTEBufferSizeInRequestsForLuma;
++	long PTEBufferSizeInRequestsForChroma;
+ 
+ 	// Missing from VBA
+ 	long dpte_group_bytes_chroma;
+@@ -787,6 +800,9 @@ struct vba_vars_st {
+ 	unsigned int PDEProcessingBufIn64KBReqs;
+ 
+ 	double MaxTotalVActiveRDBandwidth;
++	bool DoUrgentLatencyAdjustment;
++	double UrgentLatencyAdjustmentFabricClockComponent;
++	double UrgentLatencyAdjustmentFabricClockReference;
+ 	double MinUrgentLatencySupportUs;
+ 	double MinFullDETBufferingTime;
+ 	double AverageReadBandwidthGBytePerSecond;
+@@ -801,6 +817,8 @@ struct vba_vars_st {
+ 	bool ModeIsSupported;
+ 	bool ODMCombine4To1Supported;
+ 
++	unsigned int SurfaceWidthY[DC__NUM_DPP__MAX];
++	unsigned int SurfaceWidthC[DC__NUM_DPP__MAX];
+ 	unsigned int SurfaceHeightY[DC__NUM_DPP__MAX];
+ 	unsigned int SurfaceHeightC[DC__NUM_DPP__MAX];
+ 	unsigned int WritebackHTaps[DC__NUM_DPP__MAX];
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3421-drm-amd-display-update-optc-odm-interface-for-more-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3421-drm-amd-display-update-optc-odm-interface-for-more-t.patch
new file mode 100644
index 00000000..8c789b33
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3421-drm-amd-display-update-optc-odm-interface-for-more-t.patch
@@ -0,0 +1,202 @@
+From e4cc502e5dd0fe6d64f3ac727508ed4f2c185826 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Fri, 19 Jul 2019 11:43:39 -0400
+Subject: [PATCH 3421/4256] drm/amd/display: update optc odm interface for more
+ than 2 opps
+
+Current optc odm interface only accepts 2 opps, we need to
+expand this to allow 4 to 1 odm combine.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c |  3 +--
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |  2 +-
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 22 +++++++++++--------
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 20 +++++++++--------
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |  4 ++--
+ .../amd/display/dc/inc/hw/timing_generator.h  |  6 ++---
+ 6 files changed, 31 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+index b99b77dd2e8e..a96e73baefbd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+@@ -287,7 +287,7 @@ void optc1_program_timing(
+ 
+ 	h_div_2 = optc1_is_two_pixels_per_containter(&patched_crtc_timing);
+ 	REG_UPDATE(OTG_H_TIMING_CNTL,
+-			OTG_H_TIMING_DIV_BY2, h_div_2 || optc1->comb_opp_id != 0xf);
++			OTG_H_TIMING_DIV_BY2, h_div_2 || optc1->opp_count == 2);
+ 
+ }
+ 
+@@ -1524,7 +1524,6 @@ void dcn10_timing_generator_init(struct optc *optc1)
+ 	optc1->min_v_blank_interlace = 5;
+ 	optc1->min_h_sync_width = 8;
+ 	optc1->min_v_sync_width = 1;
+-	optc1->comb_opp_id = 0xf;
+ }
+ 
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+index 66c08d05da0e..82d91ab54ba5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+@@ -494,7 +494,7 @@ struct optc {
+ 	const struct dcn_optc_shift *tg_shift;
+ 	const struct dcn_optc_mask *tg_mask;
+ 
+-	int comb_opp_id;
++	int opp_count;
+ 
+ 	uint32_t max_h_total;
+ 	uint32_t max_v_total;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index e337ff821e60..3356795882ed 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -545,12 +545,14 @@ enum dc_status dcn20_enable_stream_timing(
+ 
+ 	/* TODO check if timing_changed, disable stream if timing changed */
+ 
+-	if (odm_pipe)
++	if (odm_pipe) {
++		int opp_inst[2] = { pipe_ctx->stream_res.opp->inst, odm_pipe->stream_res.opp->inst };
++
+ 		pipe_ctx->stream_res.tg->funcs->set_odm_combine(
+ 				pipe_ctx->stream_res.tg,
+-				odm_pipe->stream_res.opp->inst,
+-				pipe_ctx->stream->timing.h_addressable/2,
+-				pipe_ctx->stream->timing.pixel_encoding);
++				opp_inst, 2,
++				&pipe_ctx->stream->timing);
++	}
+ 	/* HW program guide assume display already disable
+ 	 * by unplug sequence. OTG assume stop.
+ 	 */
+@@ -822,13 +824,15 @@ static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pip
+ {
+ 	struct pipe_ctx *combine_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
+ 
+-	if (combine_pipe)
++	if (combine_pipe) {
++		int opp_inst[2] = { pipe_ctx->stream_res.opp->inst,
++				combine_pipe->stream_res.opp->inst };
++
+ 		pipe_ctx->stream_res.tg->funcs->set_odm_combine(
+ 				pipe_ctx->stream_res.tg,
+-				combine_pipe->stream_res.opp->inst,
+-				pipe_ctx->plane_res.scl_data.h_active,
+-				pipe_ctx->stream->timing.pixel_encoding);
+-	else
++				opp_inst, 2,
++				&pipe_ctx->stream->timing);
++	} else
+ 		pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
+ 				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+index 6dede495d0fd..aedf9de1c947 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+@@ -224,7 +224,6 @@ void optc2_set_odm_bypass(struct timing_generator *optc,
+ 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+ 	uint32_t h_div_2 = 0;
+ 
+-	optc1->comb_opp_id = 0xf;
+ 	REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
+ 			OPTC_NUM_OF_INPUT_SEGMENT, 0,
+ 			OPTC_SEG0_SRC_SEL, optc->inst,
+@@ -236,13 +235,16 @@ void optc2_set_odm_bypass(struct timing_generator *optc,
+ 			OTG_H_TIMING_DIV_BY2, h_div_2);
+ 	REG_SET(OPTC_MEMORY_CONFIG, 0,
+ 			OPTC_MEM_SEL, 0);
++	optc1->opp_count = 1;
+ }
+ 
+-void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id,
+-		int mpcc_hactive, enum dc_pixel_encoding pixel_encoding)
++void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
++		struct dc_crtc_timing *timing)
+ {
+ 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+ 	/* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192 */
++	int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
++			/ opp_cnt;
+ 	int memory_mask = mpcc_hactive <= 2560 ? 0x3 : 0xf;
+ 	uint32_t data_fmt = 0;
+ 
+@@ -257,23 +259,24 @@ void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id,
+ 		REG_SET(OPTC_MEMORY_CONFIG, 0,
+ 			OPTC_MEM_SEL, memory_mask << (optc->inst * 4));
+ 
+-	if (pixel_encoding == PIXEL_ENCODING_YCBCR422)
++	if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
+ 		data_fmt = 1;
+-	else if (pixel_encoding == PIXEL_ENCODING_YCBCR420)
++	else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
+ 		data_fmt = 2;
+ 
+ 	REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
+ 
++	ASSERT(opp_cnt == 2);
+ 	REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
+ 			OPTC_NUM_OF_INPUT_SEGMENT, 1,
+-			OPTC_SEG0_SRC_SEL, optc->inst,
+-			OPTC_SEG1_SRC_SEL, combine_opp_id);
++			OPTC_SEG0_SRC_SEL, opp_id[0],
++			OPTC_SEG1_SRC_SEL, opp_id[1]);
+ 
+ 	REG_UPDATE(OPTC_WIDTH_CONTROL,
+ 			OPTC_SEGMENT_WIDTH, mpcc_hactive);
+ 
+ 	REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);
+-	optc1->comb_opp_id = combine_opp_id;
++	optc1->opp_count = opp_cnt;
+ }
+ 
+ void optc2_get_optc_source(struct timing_generator *optc,
+@@ -538,6 +541,5 @@ void dcn20_timing_generator_init(struct optc *optc1)
+ 	optc1->min_v_blank_interlace = 5;
+ 	optc1->min_h_sync_width = 4;//	Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue.
+ 	optc1->min_v_sync_width = 1;
+-	optc1->comb_opp_id = 0xf;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+index ebf07c582da2..47cb4de1564c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+@@ -96,8 +96,8 @@ void optc2_set_dsc_config(struct timing_generator *optc,
+ void optc2_set_odm_bypass(struct timing_generator *optc,
+ 		const struct dc_crtc_timing *dc_crtc_timing);
+ 
+-void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id,
+-		int mpcc_hactive, enum dc_pixel_encoding pixel_encoding);
++void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
++		struct dc_crtc_timing *timing);
+ 
+ void optc2_get_optc_source(struct timing_generator *optc,
+ 		uint32_t *num_of_src_opp,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+index 5e93bc0e8ff9..1f83cb7c7dd4 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+@@ -267,9 +267,9 @@ struct timing_generator_funcs {
+ 			       uint32_t dsc_bytes_per_pixel,
+ 			       uint32_t dsc_slice_width);
+ #endif
+-	void (*set_odm_bypass)(struct timing_generator *tg, const struct dc_crtc_timing *dc_crtc_timing);
+-	void (*set_odm_combine)(struct timing_generator *tg, int combine_opp_id,
+-		int mpcc_hactive, enum dc_pixel_encoding pixel_encoding);
++	void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing);
++	void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
++			struct dc_crtc_timing *timing);
+ 	void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
+ 	void (*set_gsl_source_select)(struct timing_generator *optc,
+ 			int group_idx,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3422-drm-amd-display-HUBP-HUBBUB-register-programming-fix.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3422-drm-amd-display-HUBP-HUBBUB-register-programming-fix.patch
new file mode 100644
index 00000000..67f74d65
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3422-drm-amd-display-HUBP-HUBBUB-register-programming-fix.patch
@@ -0,0 +1,106 @@
+From d40390ff9acce835b28859519b7fd87bb965e8fd Mon Sep 17 00:00:00 2001
+From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Date: Mon, 22 Jul 2019 14:12:25 -0400
+Subject: [PATCH 3422/4256] drm/amd/display: HUBP/HUBBUB register programming
+ fixes
+
+[Why]
+- Need to change interface function signature / add an enum
+  to reflect the available register field values
+
+[How]
+- Add a new enum and modify existing functions to use it instead
+  of bool
+
+Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 2 +-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 2 +-
+ drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h      | 8 +++++++-
+ 5 files changed, 11 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+index 03f5aa10c4c4..001db49e4bb2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+@@ -509,7 +509,7 @@ bool hubp1_program_surface_flip_and_addr(
+ }
+ 
+ void hubp1_dcc_control(struct hubp *hubp, bool enable,
+-		bool independent_64b_blks)
++		enum hubp_ind_block_size independent_64b_blks)
+ {
+ 	uint32_t dcc_en = enable ? 1 : 0;
+ 	uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+index 91116b3d4b48..cb20d10288c0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+@@ -698,7 +698,7 @@ void hubp1_program_tiling(
+ 
+ void hubp1_dcc_control(struct hubp *hubp,
+ 		bool enable,
+-		bool independent_64b_blks);
++		enum hubp_ind_block_size independent_64b_blks);
+ 
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ bool hubp1_program_surface_flip_and_addr(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+index ac01e636ae27..b4b384c7fa9b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+@@ -397,7 +397,7 @@ void hubp2_program_rotation(
+ }
+ 
+ void hubp2_dcc_control(struct hubp *hubp, bool enable,
+-		bool independent_64b_blks)
++		enum hubp_ind_block_size independent_64b_blks)
+ {
+ 	uint32_t dcc_en = enable ? 1 : 0;
+ 	uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+index 924699e5f443..c4ed8f1b9424 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+@@ -252,7 +252,7 @@ bool hubp2_program_surface_flip_and_addr(
+ 	bool flip_immediate);
+ 
+ void hubp2_dcc_control(struct hubp *hubp, bool enable,
+-		bool independent_64b_blks);
++		enum hubp_ind_block_size independent_64b_blks);
+ 
+ void hubp2_program_size(
+ 	struct hubp *hubp,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+index 4993f134e747..809b62b51a43 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+@@ -47,6 +47,11 @@ enum cursor_lines_per_chunk {
+ 	CURSOR_LINE_PER_CHUNK_16
+ };
+ 
++enum hubp_ind_block_size {
++	hubp_ind_block_unconstrained = 0,
++	hubp_ind_block_64b,
++};
++
+ struct hubp {
+ 	const struct hubp_funcs *funcs;
+ 	struct dc_context *ctx;
+@@ -74,7 +79,8 @@ struct hubp_funcs {
+ 			struct _vcs_dpi_display_ttu_regs_st *ttu_regs);
+ 
+ 	void (*dcc_control)(struct hubp *hubp, bool enable,
+-			bool independent_64b_blks);
++			enum hubp_ind_block_size blk_size);
++
+ 	void (*mem_program_viewport)(
+ 			struct hubp *hubp,
+ 			const struct rect *viewport,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3423-drm-amd-display-Enable-type-C-hotplug.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3423-drm-amd-display-Enable-type-C-hotplug.patch
new file mode 100644
index 00000000..e24d7c73
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3423-drm-amd-display-Enable-type-C-hotplug.patch
@@ -0,0 +1,123 @@
+From 2959d2e5b4477b563e879a75edd81e656603bf9c Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Wed, 10 Jul 2019 22:41:51 -0400
+Subject: [PATCH 3423/4256] drm/amd/display: Enable type C hotplug
+
+[Why and How]
+We want to change where timing is done for alt mode.
+Some of the commented out #ifs are needed for DCN20
+so we enable them for that case.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 59 +++++++++++++++++++
+ .../amd/display/dc/dcn10/dcn10_link_encoder.h |  1 +
+ .../drm/amd/display/dc/inc/hw/link_encoder.h  |  1 +
+ 3 files changed, 61 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 10b24af73c51..429c1ad59089 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -682,6 +682,56 @@ static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
+ 	return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
+ }
+ 
++bool wait_for_alt_mode(struct dc_link *link)
++{
++
++	/**
++	 * something is terribly wrong if time out is > 200ms. (5Hz)
++	 * 500 microseconds * 400 tries us 200 ms
++	 **/
++	unsigned int sleep_time_in_microseconds = 500;
++	unsigned int tries_allowed = 400;
++	bool is_in_alt_mode;
++	unsigned long long enter_timestamp;
++	unsigned long long finish_timestamp;
++	unsigned long long time_taken_in_ns;
++	int tries_taken;
++
++	DC_LOGGER_INIT(link->ctx->logger);
++
++	if (link->link_enc->funcs->is_in_alt_mode == NULL)
++		return true;
++
++	is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
++	DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
++
++	if (is_in_alt_mode)
++		return true;
++
++	enter_timestamp = dm_get_timestamp(link->ctx);
++
++	for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
++		udelay(sleep_time_in_microseconds);
++		/* ask the link if alt mode is enabled, if so return ok */
++		if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
++
++			finish_timestamp = dm_get_timestamp(link->ctx);
++			time_taken_in_ns = dm_get_elapse_time_in_ns(
++				link->ctx, finish_timestamp, enter_timestamp);
++			DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
++				       time_taken_in_ns / 1000000);
++			return true;
++		}
++
++	}
++	finish_timestamp = dm_get_timestamp(link->ctx);
++	time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
++						    enter_timestamp);
++	DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
++			time_taken_in_ns / 1000000);
++	return false;
++}
++
+ /**
+  * dc_link_detect() - Detect if a sink is attached to a given link
+  *
+@@ -770,6 +820,15 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
+ 		}
+ 
+ 		case SIGNAL_TYPE_DISPLAY_PORT: {
++			/* wa HPD high coming too early*/
++			if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
++
++				/* if alt mode times out, return false */
++				if (wait_for_alt_mode(link) == false) {
++					return false;
++				}
++			}
++
+ 			if (!detect_dp(
+ 				link,
+ 				&sink_caps,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+index 33b2af1a181c..f3e57343417c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+@@ -337,6 +337,7 @@ struct dcn10_link_enc_registers {
+ 		type RDPCS_TX_FIFO_ERROR_MASK;\
+ 		type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\
+ 		type RDPCS_DPALT_4LANE_TOGGLE_MASK;\
++		type RDPCS_PHY_DPALT_DISABLE;\
+ 		type RDPCS_PHY_DPALT_DISABLE_ACK;\
+ 		type RDPCS_PHY_DP_MPLLB_V2I;\
+ 		type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+index e5e8640a9ef3..7001bfbd6681 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+@@ -183,6 +183,7 @@ struct link_encoder_funcs {
+ 
+ 	bool (*fec_is_active)(struct link_encoder *enc);
+ #endif
++	bool (*is_in_alt_mode) (struct link_encoder *enc);
+ };
+ 
+ #endif /* LINK_ENCODER_H_ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3424-drm-amd-display-reprogram-VM-config-when-system-resu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3424-drm-amd-display-reprogram-VM-config-when-system-resu.patch
new file mode 100644
index 00000000..0ebdaaff
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3424-drm-amd-display-reprogram-VM-config-when-system-resu.patch
@@ -0,0 +1,45 @@
+From 43316ae2274d58cda5a87bb7daa68e887d6156be Mon Sep 17 00:00:00 2001
+From: Lewis Huang <Lewis.Huang@amd.com>
+Date: Mon, 22 Jul 2019 15:23:32 -0400
+Subject: [PATCH 3424/4256] drm/amd/display: reprogram VM config when system
+ resume
+
+[Why]
+The vm config will be clear to 0 when system enter S4. It will
+cause hubbub didn't know how to fetch data when system resume.
+The flip always pending because earliest_inuse_address and
+request_address are different.
+
+[How]
+Reprogram VM config when system resume
+
+Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 3e79bdbc68e9..90c860d8e449 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -2273,6 +2273,14 @@ void dc_set_power_state(
+ 		dc_resource_state_construct(dc, dc->current_state);
+ 
+ 		dc->hwss.init_hw(dc);
++
++#ifdef CONFIG_DRM_AMD_DC_DCN2_0
++		if (dc->hwss.init_sys_ctx != NULL &&
++			dc->vm_pa_config.valid) {
++			dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
++		}
++#endif
++
+ 		break;
+ 	default:
+ 		ASSERT(dc->current_state->stream_count == 0);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3425-drm-amd-display-Remove-4-2-2-DSC-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3425-drm-amd-display-Remove-4-2-2-DSC-support.patch
new file mode 100644
index 00000000..bbec6a79
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3425-drm-amd-display-Remove-4-2-2-DSC-support.patch
@@ -0,0 +1,36 @@
+From 4b90aaeb56103bf80223315964d1ce1b79422a9c Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Tue, 23 Jul 2019 16:38:02 -0400
+Subject: [PATCH 3425/4256] drm/amd/display: Remove 4:2:2 DSC support
+
+[why]
+If DSC is available, a higher picture quality is achieved by using
+DSC with 4:4:4 format. Using 4:2:2 instead does not offer any benefit
+and would only introduce loss of quality. Removing it reduces
+maintenance and testing effort.
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+index e4d184cdea82..14270a98c96d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+@@ -118,8 +118,8 @@ static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock
+ 
+ 	dsc_enc_caps->color_formats.bits.RGB = 1;
+ 	dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;
+-	dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;
+-	dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1;
++	dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 0;
++	dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;
+ 	dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;
+ 
+ 	dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3426-drm-amd-display-Add-Logging-for-Gamma-Related-inform.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3426-drm-amd-display-Add-Logging-for-Gamma-Related-inform.patch
new file mode 100644
index 00000000..7f582054
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3426-drm-amd-display-Add-Logging-for-Gamma-Related-inform.patch
@@ -0,0 +1,84 @@
+From 30f60efca2009f794f042e4156d38cc627402b14 Mon Sep 17 00:00:00 2001
+From: Wyatt Wood <wyatt.wood@amd.com>
+Date: Wed, 24 Jul 2019 13:29:38 -0400
+Subject: [PATCH 3426/4256] drm/amd/display: Add Logging for Gamma Related
+ information (1/2)
+
+[Why]
+A recent bug showed that logging would be useful in
+debugging various gamma issues.
+
+[How]
+Add new log types and logging code to the color module.
+
+Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/include/logger_interface.h   |  2 ++
+ drivers/gpu/drm/amd/display/include/logger_types.h   |  1 +
+ .../gpu/drm/amd/display/modules/color/color_gamma.c  | 12 ++++++++++++
+ .../gpu/drm/amd/display/modules/color/color_gamma.h  |  1 +
+ 4 files changed, 16 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h
+index a0b68c266dab..6e008de25629 100644
+--- a/drivers/gpu/drm/amd/display/include/logger_interface.h
++++ b/drivers/gpu/drm/amd/display/include/logger_interface.h
+@@ -155,4 +155,6 @@ void context_clock_trace(
+ 
+ #define DISPLAY_STATS_END(entry) (void)(entry)
+ 
++#define LOG_GAMMA_WRITE(msg, ...)
++
+ #endif /* __DAL_LOGGER_INTERFACE_H__ */
+diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h
+index ea8d445816b8..81650ee40f0b 100644
+--- a/drivers/gpu/drm/amd/display/include/logger_types.h
++++ b/drivers/gpu/drm/amd/display/include/logger_types.h
+@@ -117,6 +117,7 @@ enum dc_log_type {
+ 	LOG_DSC,
+ #endif
+ 	LOG_DWB,
++	LOG_GAMMA_DEBUG,
+ 	LOG_SECTION_TOTAL_COUNT
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+index 4808113b91be..8f78ea226dae 100644
+--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
++++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+@@ -94,6 +94,18 @@ void setup_x_points_distribution(void)
+ 	}
+ }
+ 
++void log_x_points_distribution(struct dal_logger *logger)
++{
++	int i = 0;
++
++	if (logger != NULL) {
++		LOG_GAMMA_WRITE("]Log X Distribution\n");
++
++		for (i = 0; i < MAX_HW_POINTS; i++)
++			LOG_GAMMA_WRITE("]%llu\n", coordinates_x[i].x.value);
++	}
++}
++
+ static void compute_pq(struct fixed31_32 in_x, struct fixed31_32 *out_y)
+ {
+ 	/* consts for PQ gamma formula. */
+diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
+index 69cecd2ec251..44ddea58523a 100644
+--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
++++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
+@@ -92,6 +92,7 @@ struct translate_from_linear_space_args {
+ };
+ 
+ void setup_x_points_distribution(void);
++void log_x_points_distribution(struct dal_logger *logger);
+ void precompute_pq(void);
+ void precompute_de_pq(void);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3427-drm-amd-display-Fix-type-of-ODMCombineType-field.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3427-drm-amd-display-Fix-type-of-ODMCombineType-field.patch
new file mode 100644
index 00000000..b81b5f42
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3427-drm-amd-display-Fix-type-of-ODMCombineType-field.patch
@@ -0,0 +1,31 @@
+From 1b18e1560bea569aab5116463b9c4e9ba2a897f9 Mon Sep 17 00:00:00 2001
+From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Date: Wed, 24 Jul 2019 12:36:55 -0400
+Subject: [PATCH 3427/4256] drm/amd/display: Fix type of ODMCombineType field
+
+The type was changed previously to better reflect possible register
+values.
+
+Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+index 52d2583b2f74..91decac50557 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+@@ -491,7 +491,7 @@ struct vba_vars_st {
+ 	unsigned int NoOfDPP[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
+ 	int NoOfDPPThisState[DC__NUM_DPP__MAX];
+ 	bool ODMCombineEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
+-	bool ODMCombineTypeEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
++	enum odm_combine_mode ODMCombineTypeEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
+ 	unsigned int SwathWidthYThisState[DC__NUM_DPP__MAX];
+ 	unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
+ 	unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX];
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3428-drm-amd-display-Check-if-set_blank_data_double_buffe.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3428-drm-amd-display-Check-if-set_blank_data_double_buffe.patch
new file mode 100644
index 00000000..17350b78
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3428-drm-amd-display-Check-if-set_blank_data_double_buffe.patch
@@ -0,0 +1,33 @@
+From f9cea8683451f972957ed9bfb2ebecb8771397ee Mon Sep 17 00:00:00 2001
+From: Vitaly Prosyak <vitaly.prosyak@amd.com>
+Date: Fri, 19 Jul 2019 16:07:33 -0500
+Subject: [PATCH 3428/4256] drm/amd/display: Check if
+ set_blank_data_double_buffer exists before call
+
+Not all ASIC types have this function implemented - check before
+calling.
+
+Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
+Reviewed-by: Julian Parkin <jparkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 8fd2d51477ea..ee553262039f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -720,7 +720,8 @@ static void false_optc_underflow_wa(
+ 		dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
+ 	}
+ 
+-	tg->funcs->set_blank_data_double_buffer(tg, true);
++	if (tg->funcs->set_blank_data_double_buffer)
++		tg->funcs->set_blank_data_double_buffer(tg, true);
+ 
+ 	if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
+ 		tg->funcs->clear_optc_underflow(tg);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3429-drm-amd-display-Correct-DSC-PPS-log.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3429-drm-amd-display-Correct-DSC-PPS-log.patch
new file mode 100644
index 00000000..dcb34a8b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3429-drm-amd-display-Correct-DSC-PPS-log.patch
@@ -0,0 +1,42 @@
+From eff06b5a22b1d9588ceec1438792ede891e612ae Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Thu, 25 Jul 2019 17:27:03 -0400
+Subject: [PATCH 3429/4256] drm/amd/display: Correct DSC PPS log
+
+[why]
+A misleading message "Programming PPS" appears before both programming
+and "query PPS" functions
+
+[how]
+Move the message from "log PPS" function to "program PPS" function
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+index 14270a98c96d..808f4d154e61 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+@@ -192,6 +192,7 @@ static void dsc2_set_config(struct display_stream_compressor *dsc, const struct
+ 	dsc_config_log(dsc, dsc_cfg);
+ 	is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg);
+ 	ASSERT(is_config_ok);
++	DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");
+ 	dsc_log_pps(dsc, &dsc20->reg_vals.pps);
+ 	dsc_write_to_registers(dsc, &dsc20->reg_vals);
+ }
+@@ -250,7 +251,6 @@ static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_co
+ 	int i;
+ 	int bits_per_pixel = pps->bits_per_pixel;
+ 
+-	DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");
+ 	DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major);
+ 	DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor);
+ 	DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3430-drm-amd-display-wake-up-ogam-mem-pwr-before-programm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3430-drm-amd-display-wake-up-ogam-mem-pwr-before-programm.patch
new file mode 100644
index 00000000..f577f190
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3430-drm-amd-display-wake-up-ogam-mem-pwr-before-programm.patch
@@ -0,0 +1,220 @@
+From be743ffc3f2b983c9e44c9a332856855841367db Mon Sep 17 00:00:00 2001
+From: Charlene Liu <charlene.liu@amd.com>
+Date: Wed, 24 Jul 2019 18:14:46 -0400
+Subject: [PATCH 3430/4256] drm/amd/display: wake up ogam mem pwr before
+ programming ocsc
+
+[Description]
+OGAM_MEM_PWR could stay in light up when driver woke up to update gamma.
+either disable MEM_LOW power feature or set to OGAM_bypass could make artificial color distortion goes away.
+Easy reproduce after LOW_MEM Power feature enables and resume from S3.
+
+Signed-off-by: Charlene Liu <charlene.liu@amd.com>
+Reviewed-by: Julian Parkin <jparkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c  | 16 ++++++++++++++++
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h  | 19 +++++++++++++++----
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  6 ++++++
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c  |  5 +++--
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h  |  6 +++++-
+ drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h   |  4 ++++
+ 6 files changed, 49 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+index 9bc5dd23d297..db311574f42f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+@@ -72,6 +72,21 @@ void dpp20_read_state(struct dpp *dpp_base,
+ 	}
+ }
+ 
++void dpp2_power_on_obuf(
++		struct dpp *dpp_base,
++	bool power_on)
++{
++	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
++
++	REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0);
++
++	REG_UPDATE(OBUF_MEM_PWR_CTRL,
++			OBUF_MEM_PWR_FORCE, power_on == true ? 0:1);
++
++	REG_UPDATE(DSCL_MEM_PWR_CTRL,
++			LUT_MEM_PWR_FORCE, power_on == true ? 0:1);
++}
++
+ void dpp2_dummy_program_input_lut(
+ 		struct dpp *dpp_base,
+ 		const struct dc_gamma *gamma)
+@@ -227,6 +242,7 @@ static void dpp2_cnv_setup (
+ 				CUR0_ENABLE, 0);
+ 
+ 	}
++	dpp2_power_on_obuf(dpp_base, true);
+ 
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
+index 59b67ed57c19..1f5d99a6d240 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
+@@ -162,7 +162,9 @@
+ 	SRI(COLOR_KEYER_GREEN, CNVC_CFG, id), \
+ 	SRI(COLOR_KEYER_BLUE, CNVC_CFG, id), \
+ 	SRI(CM_SHAPER_LUT_DATA, CM, id), \
+-	SRI(CURSOR_CONTROL, CURSOR0_, id)
++	SRI(CURSOR_CONTROL, CURSOR0_, id),\
++	SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\
++	SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
+ 
+ #define TF_REG_LIST_SH_MASK_DCN20(mask_sh)\
+ 	TF_REG_LIST_SH_MASK_DCN(mask_sh), \
+@@ -554,7 +556,9 @@
+ 	TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \
+ 	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \
+ 	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \
+-	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh)
++	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\
++	TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\
++	TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh)
+ 
+ #define TF_REG_FIELD_LIST_DCN2_0(type) \
+ 	TF_REG_FIELD_LIST(type) \
+@@ -585,7 +589,9 @@
+ 	type COLOR_KEYER_BLUE_HIGH; \
+ 	type CUR0_PIX_INV_MODE; \
+ 	type CUR0_PIXEL_ALPHA_MOD_EN; \
+-	type CUR0_ROM_EN
++	type CUR0_ROM_EN;\
++	type OBUF_MEM_PWR_FORCE;\
++	type LUT_MEM_PWR_FORCE
+ 
+ struct dcn2_dpp_shift {
+ 	TF_REG_FIELD_LIST_DCN2_0(uint8_t);
+@@ -609,7 +615,9 @@ struct dcn2_dpp_mask {
+ 	uint32_t COLOR_KEYER_ALPHA; \
+ 	uint32_t COLOR_KEYER_RED; \
+ 	uint32_t COLOR_KEYER_GREEN; \
+-	uint32_t COLOR_KEYER_BLUE
++	uint32_t COLOR_KEYER_BLUE; \
++	uint32_t OBUF_MEM_PWR_CTRL;\
++	uint32_t DSCL_MEM_PWR_CTRL
+ 
+ struct dcn2_dpp_registers {
+ 	DPP_DCN2_REG_VARIABLE_LIST;
+@@ -695,4 +703,7 @@ bool dpp2_construct(struct dcn20_dpp *dpp2,
+ 	const struct dcn2_dpp_shift *tf_shift,
+ 	const struct dcn2_dpp_mask *tf_mask);
+ 
++void dpp2_power_on_obuf(
++		struct dpp *dpp_base,
++	bool power_on);
+ #endif /* __DC_HWSS_DCN20_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 3356795882ed..ea3b874497be 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -631,6 +631,10 @@ void dcn20_program_output_csc(struct dc *dc,
+ {
+ 	struct mpc *mpc = dc->res_pool->mpc;
+ 	enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
++	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
++
++	if (mpc->funcs->power_on_mpc_mem_pwr)
++		mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
+ 
+ 	if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
+ 		if (mpc->funcs->set_output_csc != NULL)
+@@ -660,6 +664,8 @@ bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
+ 	 * if programming for all pipes is required then remove condition
+ 	 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
+ 	 */
++	if (mpc->funcs->power_on_mpc_mem_pwr)
++		mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
+ 	if ((pipe_ctx->top_pipe == NULL || dc_res_is_odm_head_pipe(pipe_ctx))
+ 			&& mpc->funcs->set_output_gamma && stream->out_transfer_func) {
+ 		if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+index 17950d9e53cf..5a188b2bc033 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+@@ -233,14 +233,14 @@ static void mpc2_ogam_get_reg_field(
+ 	reg->masks.exp_resion_start_segment = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
+ }
+ 
+-static void mpc20_power_on_ogam_lut(
++void mpc20_power_on_ogam_lut(
+ 		struct mpc *mpc, int mpcc_id,
+ 		bool power_on)
+ {
+ 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
+ 
+ 	REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0,
+-			MPCC_OGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
++			MPCC_OGAM_MEM_PWR_DIS, power_on == true ? 1:0);
+ 
+ }
+ 
+@@ -509,6 +509,7 @@ const struct mpc_funcs dcn20_mpc_funcs = {
+ 	.set_output_csc = mpc2_set_output_csc,
+ 	.set_ocsc_default = mpc2_set_ocsc_default,
+ 	.set_output_gamma = mpc2_set_output_gamma,
++	.power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut,
+ };
+ 
+ void dcn20_mpc_construct(struct dcn20_mpc *mpc20,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h
+index 9750095d2d73..9f53192da2dc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h
+@@ -159,6 +159,7 @@
+ 	SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_B, mask_sh),\
+ 	SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh),\
+ 	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
++	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
+ 	SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
+ 	SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_WRITE_EN_MASK, mask_sh),\
+ 	SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_RAM_SEL, mask_sh),\
+@@ -173,6 +174,7 @@
+ 	SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
+ 	SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh)
+ 
++
+ #define MPC_REG_FIELD_LIST_DCN2_0(type) \
+ 	MPC_REG_FIELD_LIST(type)\
+ 	type MPCC_BG_BPC;\
+@@ -217,7 +219,8 @@
+ 	type MPC_OUT_DENORM_CLAMP_MIN_G_Y;\
+ 	type MPC_OUT_DENORM_CLAMP_MAX_B_CB;\
+ 	type MPC_OUT_DENORM_CLAMP_MIN_B_CB;\
+-	type MPCC_DISABLED;
++	type MPCC_DISABLED;\
++	type MPCC_OGAM_MEM_PWR_DIS;
+ 
+ struct dcn20_mpc_registers {
+ 	MPC_REG_VARIABLE_LIST_DCN2_0
+@@ -282,4 +285,5 @@ void mpc2_set_output_gamma(
+ 
+ void mpc2_assert_idle_mpcc(struct mpc *mpc, int id);
+ void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id);
++void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+index 9dde88d4571c..58826be81395 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+@@ -254,6 +254,10 @@ struct mpc_funcs {
+ 			struct mpc *mpc,
+ 			int mpcc_id,
+ 			const struct pwl_params *params);
++	void (*power_on_mpc_mem_pwr)(
++			struct mpc *mpc,
++			int mpcc_id,
++			bool power_on);
+ #endif
+ 
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3431-drm-amd-display-Register-VUPDATE_NO_LOCK-interrupts-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3431-drm-amd-display-Register-VUPDATE_NO_LOCK-interrupts-.patch
new file mode 100644
index 00000000..b044daea
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3431-drm-amd-display-Register-VUPDATE_NO_LOCK-interrupts-.patch
@@ -0,0 +1,85 @@
+From 9841069ef0ff2abf559dabc0ab36f9c0666f97b4 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Thu, 25 Jul 2019 11:53:16 -0400
+Subject: [PATCH 3431/4256] drm/amd/display: Register VUPDATE_NO_LOCK
+ interrupts for DCN2
+
+[Why]
+These are needed to send back DRM vblank events in the case where VRR
+is on. Without the interrupt enabled we're deferring the events into the
+vblank queue and userspace is left waiting forever to get back the
+events they need.
+
+Found using igt@kms_vrr - the test fails immediately due to vblank
+timeout.
+
+[How]
+Register them the same way we're handling it for DCN1.
+
+This fixes igt@kms_vrr for DCN2.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: David Francis <David.Francis@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../display/dc/irq/dcn20/irq_service_dcn20.c  | 28 ++++++++++++-------
+ 1 file changed, 18 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
+index 65866d620759..1fdbc9e5f7bc 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
+@@ -165,6 +165,11 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
+ 	.ack = NULL
+ };
+ 
++static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
++	.set = NULL,
++	.ack = NULL
++};
++
+ #undef BASE_INNER
+ #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+ 
+@@ -219,12 +224,15 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
+ 		.funcs = &pflip_irq_info_funcs\
+ 	}
+ 
+-#define vupdate_int_entry(reg_num)\
++/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
++ * of DCE's DC_IRQ_SOURCE_VUPDATEx.
++ */
++#define vupdate_no_lock_int_entry(reg_num)\
+ 	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
+ 		IRQ_REG_ENTRY(OTG, reg_num,\
+-			OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
+-			OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
+-		.funcs = &vblank_irq_info_funcs\
++			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
++			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
++		.funcs = &vupdate_no_lock_irq_info_funcs\
+ 	}
+ 
+ #define vblank_int_entry(reg_num)\
+@@ -331,12 +339,12 @@ irq_source_info_dcn20[DAL_IRQ_SOURCES_NUMBER] = {
+ 	dc_underflow_int_entry(6),
+ 	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
+ 	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
+-	vupdate_int_entry(0),
+-	vupdate_int_entry(1),
+-	vupdate_int_entry(2),
+-	vupdate_int_entry(3),
+-	vupdate_int_entry(4),
+-	vupdate_int_entry(5),
++	vupdate_no_lock_int_entry(0),
++	vupdate_no_lock_int_entry(1),
++	vupdate_no_lock_int_entry(2),
++	vupdate_no_lock_int_entry(3),
++	vupdate_no_lock_int_entry(4),
++	vupdate_no_lock_int_entry(5),
+ 	vblank_int_entry(0),
+ 	vblank_int_entry(1),
+ 	vblank_int_entry(2),
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3432-drm-amd-display-Add-enum-for-H-timing-divider-mode.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3432-drm-amd-display-Add-enum-for-H-timing-divider-mode.patch
new file mode 100644
index 00000000..6bccaa15
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3432-drm-amd-display-Add-enum-for-H-timing-divider-mode.patch
@@ -0,0 +1,63 @@
+From aa03504f3858ddad3064ce53ae4f836c285251ec Mon Sep 17 00:00:00 2001
+From: Qingqing Zhuo <qingqing.zhuo@amd.com>
+Date: Tue, 23 Jul 2019 12:24:24 -0400
+Subject: [PATCH 3432/4256] drm/amd/display: Add enum for H-timing divider mode
+
+Add h_timing_div_mode enum to better reflect possible register
+values. Replace previously programmed values with enum
+
+Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c        | 9 +++++----
+ drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 5 +++++
+ 2 files changed, 10 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+index a96e73baefbd..66d8f6410b53 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+@@ -154,7 +154,7 @@ void optc1_program_timing(
+ 	uint32_t h_sync_polarity, v_sync_polarity;
+ 	uint32_t start_point = 0;
+ 	uint32_t field_num = 0;
+-	uint32_t h_div_2;
++	enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
+ 
+ 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+ 
+@@ -285,10 +285,11 @@ void optc1_program_timing(
+ 	 * of stereo handled in explicit call
+ 	 */
+ 
+-	h_div_2 = optc1_is_two_pixels_per_containter(&patched_crtc_timing);
+-	REG_UPDATE(OTG_H_TIMING_CNTL,
+-			OTG_H_TIMING_DIV_BY2, h_div_2 || optc1->opp_count == 2);
++	if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2)
++		h_div = H_TIMING_DIV_BY2;
+ 
++	REG_UPDATE(OTG_H_TIMING_CNTL,
++		OTG_H_TIMING_DIV_BY2, h_div);
+ }
+ 
+ void optc1_set_vtg_params(struct timing_generator *optc,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+index 1f83cb7c7dd4..f607ef24c766 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+@@ -96,6 +96,11 @@ enum crc_selection {
+ 	INTERSECT_WINDOW_NOT_A_NOT_B,
+ };
+ 
++enum h_timing_div_mode {
++	H_TIMING_NO_DIV,
++	H_TIMING_DIV_BY2,
++};
++
+ struct crc_params {
+ 	/* Regions used to calculate CRC*/
+ 	uint16_t windowa_x_start;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3433-drm-amd-display-Remove-redundant-definition-of-dwb_s.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3433-drm-amd-display-Remove-redundant-definition-of-dwb_s.patch
new file mode 100644
index 00000000..77098e24
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3433-drm-amd-display-Remove-redundant-definition-of-dwb_s.patch
@@ -0,0 +1,46 @@
+From ee831d3f62bc24656ff24fecceab07f9da094c7a Mon Sep 17 00:00:00 2001
+From: Julian Parkin <julian.parkin@amd.com>
+Date: Thu, 25 Jul 2019 16:53:27 -0400
+Subject: [PATCH 3433/4256] drm/amd/display: Remove redundant definition of
+ dwb_source enums
+
+There are repeated (but guarded) definitions of dwb_src enums. There are
+also unused entires. Clean them up.
+
+Signed-off-by: Julian Parkin <julian.parkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 12 ------------
+ 1 file changed, 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
+index a3409294ae0c..ff1a07b35c85 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
+@@ -45,22 +45,10 @@ enum dwb_source {
+ 	dwb_src_scl = 0,	/* for DCE7x/9x, DCN won't support. */
+ 	dwb_src_blnd,		/* for DCE7x/9x */
+ 	dwb_src_fmt,		/* for DCE7x/9x */
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	dwb_src_otg0 = 0x100,	/* for DCN1.x/DCN2.x, register: mmDWB_SOURCE_SELECT */
+ 	dwb_src_otg1,		/* for DCN1.x/DCN2.x */
+ 	dwb_src_otg2,		/* for DCN1.x/DCN2.x */
+ 	dwb_src_otg3,		/* for DCN1.x/DCN2.x */
+-#else
+-	dwb_src_otg0 = 0x100,	/* for DCN1.x, register: mmDWB_SOURCE_SELECT */
+-	dwb_src_otg1,		/* for DCN1.x */
+-	dwb_src_otg2,		/* for DCN1.x */
+-	dwb_src_otg3,		/* for DCN1.x */
+-#endif
+-	dwb_src_mpc0 = 0x200,	/* for DCN2, register: mmMPC_DWB0_MUX, mmMPC_DWB1_MUX, mmMPC_DWB2_MUX */
+-	dwb_src_mpc1,		/* for DCN2 */
+-	dwb_src_mpc2,		/* for DCN2 */
+-	dwb_src_mpc3,		/* for DCN2 */
+-	dwb_src_mpc4,		/* for DCN2 */
+ };
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3434-drm-amd-display-Add-Logging-for-Gamma-Related-inform.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3434-drm-amd-display-Add-Logging-for-Gamma-Related-inform.patch
new file mode 100644
index 00000000..bd669d57
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3434-drm-amd-display-Add-Logging-for-Gamma-Related-inform.patch
@@ -0,0 +1,114 @@
+From 195fb6ba689935a22b42866a98afef7649d9925a Mon Sep 17 00:00:00 2001
+From: Wyatt Wood <wyatt.wood@amd.com>
+Date: Wed, 24 Jul 2019 13:37:08 -0400
+Subject: [PATCH 3434/4256] drm/amd/display: Add Logging for Gamma Related
+ information (2/2)
+
+[Why]
+A recent bug showed that logging would be useful in debugging
+various gamma issues.
+
+[How]
+Add logging in dc.
+
+Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
+Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/dcn10/dcn10_cm_common.c    |  4 +--
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 32 +++++++++++++++++++
+ .../drm/amd/display/include/logger_types.h    |  6 ++++
+ 3 files changed, 40 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+index 8166fdbacd73..01c7e30b9ce1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+@@ -343,8 +343,8 @@ bool cm_helper_translate_curve_to_hw_format(
+ 		region_start = -MAX_LOW_POINT;
+ 		region_end   = NUMBER_REGIONS - MAX_LOW_POINT;
+ 	} else {
+-		/* 10 segments
+-		 * segment is from 2^-10 to 2^0
++		/* 11 segments
++		 * segment is from 2^-10 to 2^1
+ 		 * There are less than 256 points, for optimization
+ 		 */
+ 		seg_distr[0] = 3;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index ee553262039f..2846017a544d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1433,6 +1433,34 @@ static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
+ 	return result;
+ }
+ 
++#define MAX_NUM_HW_POINTS 0x200
++
++static void log_tf(struct dc_context *ctx,
++				struct dc_transfer_func *tf, uint32_t hw_points_num)
++{
++	// DC_LOG_GAMMA is default logging of all hw points
++	// DC_LOG_ALL_GAMMA logs all points, not only hw points
++	// DC_LOG_ALL_TF_POINTS logs all channels of the tf
++	int i = 0;
++
++	DC_LOGGER_INIT(ctx->logger);
++	DC_LOG_GAMMA("Gamma Correction TF");
++	DC_LOG_ALL_GAMMA("Logging all tf points...");
++	DC_LOG_ALL_TF_CHANNELS("Logging all channels...");
++
++	for (i = 0; i < hw_points_num; i++) {
++		DC_LOG_GAMMA("R %d %llu\n", i, tf->tf_pts.red[i].value);
++		DC_LOG_ALL_TF_CHANNELS("G %d, %llu\n", i, tf->tf_pts.green[i].value);
++		DC_LOG_ALL_TF_CHANNELS("B %d, %llu\n", i, tf->tf_pts.blue[i].value);
++	}
++
++	for (i = hw_points_num; i < MAX_NUM_HW_POINTS; i++) {
++		DC_LOG_ALL_GAMMA("R %d %llu\n", i, tf->tf_pts.red[i].value);
++		DC_LOG_ALL_TF_CHANNELS("G %d %llu\n", i, tf->tf_pts.green[i].value);
++		DC_LOG_ALL_TF_CHANNELS("B %d %llu\n", i, tf->tf_pts.blue[i].value);
++	}
++}
++
+ static bool
+ dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
+ 			       const struct dc_stream_state *stream)
+@@ -1461,6 +1489,10 @@ dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
+ 	} else
+ 		dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
+ 
++	log_tf(stream->ctx,
++			stream->out_transfer_func,
++			dpp->regamma_params.hw_points_num);
++
+ 	return true;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h
+index 81650ee40f0b..2b219cdb13ad 100644
+--- a/drivers/gpu/drm/amd/display/include/logger_types.h
++++ b/drivers/gpu/drm/amd/display/include/logger_types.h
+@@ -63,6 +63,9 @@
+ #define DC_LOG_IF_TRACE(...) pr_debug("[IF_TRACE]:"__VA_ARGS__)
+ #define DC_LOG_PERF_TRACE(...) DRM_DEBUG_KMS(__VA_ARGS__)
+ #define DC_LOG_RETIMER_REDRIVER(...) DRM_DEBUG_KMS(__VA_ARGS__)
++#define DC_LOG_GAMMA(...) pr_debug("[GAMMA]:"__VA_ARGS__)
++#define DC_LOG_ALL_GAMMA(...) pr_debug("[GAMMA]:"__VA_ARGS__)
++#define DC_LOG_ALL_TF_CHANNELS(...) pr_debug("[GAMMA]:"__VA_ARGS__)
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #define DC_LOG_DSC(...) DRM_DEBUG_KMS(__VA_ARGS__)
+ #endif
+@@ -118,6 +121,9 @@ enum dc_log_type {
+ #endif
+ 	LOG_DWB,
+ 	LOG_GAMMA_DEBUG,
++	LOG_MAX_HW_POINTS,
++	LOG_ALL_TF_CHANNELS,
++	LOG_SAMPLE_1DLUT,
+ 	LOG_SECTION_TOTAL_COUNT
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3435-drm-amd-display-Add-and-refine-DSC-logs-in-enable-se.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3435-drm-amd-display-Add-and-refine-DSC-logs-in-enable-se.patch
new file mode 100644
index 00000000..48545a13
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3435-drm-amd-display-Add-and-refine-DSC-logs-in-enable-se.patch
@@ -0,0 +1,135 @@
+From 9e8f7a0ff18ca301b3be17010787a9839d23586c Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Thu, 25 Jul 2019 18:46:54 -0400
+Subject: [PATCH 3435/4256] drm/amd/display: Add and refine DSC logs in enable
+ sequence
+
+[why]
+Some logs messages were not precise and some new log messages
+were needed after "get packed PPS" function was introduced
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/core/dc_link_hwss.c    | 34 ++++++++++++++-----
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c  | 14 +++++---
+ 2 files changed, 35 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index af65071b6cf5..35c5467e60e8 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -342,10 +342,22 @@ void dp_retrain_link_dp_test(struct dc_link *link,
+ static void dsc_optc_config_log(struct display_stream_compressor *dsc,
+ 		struct dsc_optc_config *config)
+ {
+-	DC_LOG_DSC("Setting optc DSC config at DSC inst %d", dsc->inst);
+-	DC_LOG_DSC("\n\tbytes_per_pixel %d\n\tis_pixel_format_444 %d\n\tslice_width %d",
+-			config->bytes_per_pixel,
+-			config->is_pixel_format_444, config->slice_width);
++	uint32_t precision = 1 << 28;
++	uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision;
++	uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision;
++	uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod;
++
++	/* 7 fractional digits decimal precision for bytes per pixel is enough because DSC
++	 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is
++	 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal
++	 */
++	ll_bytes_per_pix_fraq *= 10000000;
++	ll_bytes_per_pix_fraq /= precision;
++
++	DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)",
++			config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq);
++	DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444);
++	DC_LOG_DSC("\tslice_width %d", config->slice_width);
+ }
+ 
+ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
+@@ -400,17 +412,21 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ 
+ 		optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
+ 
+-		dsc_optc_config_log(dsc, &dsc_optc_cfg);
+ 		/* Enable DSC in encoder */
+-		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
++		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++			DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id);
++			dsc_optc_config_log(dsc, &dsc_optc_cfg);
+ 			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,
+ 									optc_dsc_mode,
+ 									dsc_optc_cfg.bytes_per_pixel,
+ 									dsc_optc_cfg.slice_width);
+ 
+ 			/* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */
++		}
+ 
+ 		/* Enable DSC in OPTC */
++		DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
++		dsc_optc_config_log(dsc, &dsc_optc_cfg);
+ 		pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
+ 							optc_dsc_mode,
+ 							dsc_optc_cfg.bytes_per_pixel,
+@@ -482,13 +498,15 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
+ 		dsc_cfg.color_depth = stream->timing.display_color_depth;
+ 		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
+ 
++		DC_LOG_DSC(" ");
+ 		dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);
+-		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
++		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++			DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);
+ 			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
+ 									pipe_ctx->stream_res.stream_enc,
+ 									true,
+ 									&dsc_packed_pps[0]);
+-
++		}
+ 	} else {
+ 		/* disable DSC PPS in stream encoder */
+ 		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+index 808f4d154e61..379c9e4ac63b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+@@ -175,11 +175,13 @@ static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const st
+ 
+ static void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config)
+ {
+-	DC_LOG_DSC("\n\tnum_slices_h %d\n\tnum_slices_v %d\n\tbits_per_pixel %d\n\tcolor_depth %d",
+-		config->dc_dsc_cfg.num_slices_h,
+-		config->dc_dsc_cfg.num_slices_v,
++	DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h);
++	DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v);
++	DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)",
+ 		config->dc_dsc_cfg.bits_per_pixel,
+-		config->color_depth);
++		config->dc_dsc_cfg.bits_per_pixel / 16,
++		((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16);
++	DC_LOG_DSC("\tcolor_depth %d", config->color_depth);
+ }
+ 
+ static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
+@@ -188,6 +190,7 @@ static void dsc2_set_config(struct display_stream_compressor *dsc, const struct
+ 	bool is_config_ok;
+ 	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
+ 
++	DC_LOG_DSC(" ");
+ 	DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
+ 	dsc_config_log(dsc, dsc_cfg);
+ 	is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg);
+@@ -204,8 +207,9 @@ static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const str
+ 	struct dsc_reg_values dsc_reg_vals;
+ 	struct dsc_optc_config dsc_optc_cfg;
+ 
+-	DC_LOG_DSC("Packed DSC PPS for DSC Config:");
++	DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
+ 	dsc_config_log(dsc, dsc_cfg);
++	DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
+ 	is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg);
+ 	ASSERT(is_config_ok);
+ 	drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3436-drm-amd-display-3.2.45.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3436-drm-amd-display-3.2.45.patch
new file mode 100644
index 00000000..79358bbc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3436-drm-amd-display-3.2.45.patch
@@ -0,0 +1,27 @@
+From c4430eb614ab73e4cbd680c4f8309c2ddefd1deb Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Sat, 27 Jul 2019 15:10:54 -0400
+Subject: [PATCH 3436/4256] drm/amd/display: 3.2.45
+
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index a5cb2a246a0c..0ba04dc5af1d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -42,7 +42,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.44"
++#define DC_VER "3.2.45"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3437-drm-amd-display-fix-dcn20-global-sync-dml-param-extr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3437-drm-amd-display-fix-dcn20-global-sync-dml-param-extr.patch
new file mode 100644
index 00000000..45e15147
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3437-drm-amd-display-fix-dcn20-global-sync-dml-param-extr.patch
@@ -0,0 +1,313 @@
+From e968ce47ce80d4e980840165657f083425aa7ca5 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Fri, 26 Jul 2019 17:32:02 -0400
+Subject: [PATCH 3437/4256] drm/amd/display: fix dcn20 global sync dml param
+ extraction
+
+Currently the paremeters are extracted as if dml is calculating
+using pipes as we pass them in. in reality, dml internally merges
+pipes into planes if pipe split is detected.
+
+This change adds reverse logic to dcn20_calculate_dlg_params so
+that the global sync parameters can be correctly extracted for
+all the pipes when pipe split is enabled.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 229 ++++++++++--------
+ .../gpu/drm/amd/display/dc/inc/core_types.h   |   1 -
+ 2 files changed, 131 insertions(+), 99 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index bdd3478f80ee..000b2bfe54fb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2436,100 +2436,100 @@ void dcn20_calculate_wm(
+ 	int pipe_cnt, i, pipe_idx;
+ 
+ 	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
+-			if (!context->res_ctx.pipe_ctx[i].stream)
+-				continue;
+-
+-			pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
+-			pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
+-
+-			if (pipe_split_from[i] < 0) {
+-				pipes[pipe_cnt].clks_cfg.dppclk_mhz =
+-						context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
+-				if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
+-					pipes[pipe_cnt].pipe.dest.odm_combine =
+-							context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
+-				else
+-					pipes[pipe_cnt].pipe.dest.odm_combine = 0;
+-				pipe_idx++;
+-			} else {
+-				pipes[pipe_cnt].clks_cfg.dppclk_mhz =
+-						context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
+-				if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
+-					pipes[pipe_cnt].pipe.dest.odm_combine =
+-							context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]];
+-				else
+-					pipes[pipe_cnt].pipe.dest.odm_combine = 0;
+-			}
+-
+-			if (dc->config.forced_clocks) {
+-				pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
+-				pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
+-			}
+-			if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
+-				pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
+-			if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
+-				pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
++		if (!context->res_ctx.pipe_ctx[i].stream)
++			continue;
+ 
+-			pipe_cnt++;
+-		}
++		pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
++		pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
+ 
+-		if (pipe_cnt != pipe_idx) {
+-			if (dc->res_pool->funcs->populate_dml_pipes)
+-				pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
+-					&context->res_ctx, pipes);
++		if (pipe_split_from[i] < 0) {
++			pipes[pipe_cnt].clks_cfg.dppclk_mhz =
++					context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
++			if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
++				pipes[pipe_cnt].pipe.dest.odm_combine =
++						context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
+ 			else
+-				pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
+-					&context->res_ctx, pipes);
++				pipes[pipe_cnt].pipe.dest.odm_combine = 0;
++			pipe_idx++;
++		} else {
++			pipes[pipe_cnt].clks_cfg.dppclk_mhz =
++					context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
++			if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
++				pipes[pipe_cnt].pipe.dest.odm_combine =
++						context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]];
++			else
++				pipes[pipe_cnt].pipe.dest.odm_combine = 0;
+ 		}
+ 
+-		*out_pipe_cnt = pipe_cnt;
++		if (dc->config.forced_clocks) {
++			pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
++			pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
++		}
++		if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
++			pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
++		if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
++			pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
+ 
+-		pipes[0].clks_cfg.voltage = vlevel;
+-		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
+-		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
++		pipe_cnt++;
++	}
+ 
+-		/* only pipe 0 is read for voltage and dcf/soc clocks */
+-		if (vlevel < 1) {
+-			pipes[0].clks_cfg.voltage = 1;
+-			pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
+-			pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
+-		}
+-		context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-		context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-		context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-		context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-		context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-
+-		if (vlevel < 2) {
+-			pipes[0].clks_cfg.voltage = 2;
+-			pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
+-			pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
+-		}
+-		context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-		context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-		context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-		context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-		context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-
+-		if (vlevel < 3) {
+-			pipes[0].clks_cfg.voltage = 3;
+-			pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
+-			pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
+-		}
+-		context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-		context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-		context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-		context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-		context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-
+-		pipes[0].clks_cfg.voltage = vlevel;
+-		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
+-		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
+-		context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+-		context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	if (pipe_cnt != pipe_idx) {
++		if (dc->res_pool->funcs->populate_dml_pipes)
++			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
++				&context->res_ctx, pipes);
++		else
++			pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
++				&context->res_ctx, pipes);
++	}
++
++	*out_pipe_cnt = pipe_cnt;
++
++	pipes[0].clks_cfg.voltage = vlevel;
++	pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
++	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
++
++	/* only pipe 0 is read for voltage and dcf/soc clocks */
++	if (vlevel < 1) {
++		pipes[0].clks_cfg.voltage = 1;
++		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
++		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
++	}
++	context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++
++	if (vlevel < 2) {
++		pipes[0].clks_cfg.voltage = 2;
++		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
++		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
++	}
++	context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++
++	if (vlevel < 3) {
++		pipes[0].clks_cfg.voltage = 3;
++		pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
++		pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
++	}
++	context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++
++	pipes[0].clks_cfg.voltage = vlevel;
++	pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
++	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
++	context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ }
+ 
+ void dcn20_calculate_dlg_params(
+@@ -2538,7 +2538,8 @@ void dcn20_calculate_dlg_params(
+ 		int pipe_cnt,
+ 		int vlevel)
+ {
+-	int i, pipe_idx;
++	int i, j, pipe_idx, pipe_idx_unsplit;
++	bool visited[MAX_PIPES] = { 0 };
+ 
+ 	/* Writeback MCIF_WB arbitration parameters */
+ 	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
+@@ -2554,31 +2555,63 @@ void dcn20_calculate_dlg_params(
+ 							!= dm_dram_clock_change_unsupported;
+ 	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
+ 
++	/*
++	 * An artifact of dml pipe split/odm is that pipes get merged back together for
++	 * calculation. Therefore we need to only extract for first pipe in ascending index order
++	 * and copy into the other split half.
++	 */
++	for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) {
++		if (!context->res_ctx.pipe_ctx[i].stream)
++			continue;
+ 
++		if (!visited[pipe_idx]) {
++			display_pipe_source_params_st *src = &pipes[pipe_idx_unsplit].pipe.src;
++			display_pipe_dest_params_st *dst = &pipes[pipe_idx_unsplit].pipe.dest;
++
++			dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
++			dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
++			dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
++			dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
++			/*
++			 * j iterates inside pipes array, unlike i which iterates inside
++			 * pipe_ctx array
++			 */
++			if (src->is_hsplit)
++				for (j = pipe_idx + 1; j < pipe_cnt; j++) {
++					display_pipe_source_params_st *src_j = &pipes[j].pipe.src;
++					display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest;
++
++					if (src_j->is_hsplit && !visited[j]
++							&& src->hsplit_grp == src_j->hsplit_grp) {
++						dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
++						dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
++						dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
++						dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
++						visited[j] = true;
++					}
++				}
++			visited[pipe_idx] = true;
++			pipe_idx_unsplit++;
++		}
++		pipe_idx++;
++	}
+ 
+ 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+ 		if (!context->res_ctx.pipe_ctx[i].stream)
+ 			continue;
+-		pipes[pipe_idx].pipe.dest.vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx];
+-		pipes[pipe_idx].pipe.dest.vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx];
+-		pipes[pipe_idx].pipe.dest.vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx];
+-		pipes[pipe_idx].pipe.dest.vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx];
+ 		if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
+ 			context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
+ 		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
+ 						pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-		context->res_ctx.pipe_ctx[i].stream_res.dscclk_khz =
+-				context->bw_ctx.dml.vba.DSCCLK_calculated[pipe_idx] * 1000;
+-#endif
++		ASSERT(visited[pipe_idx]);
+ 		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
+ 		pipe_idx++;
+ 	}
+ 	/*save a original dppclock copy*/
+ 	context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
+ 	context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
+-	context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz*1000;
+-	context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz*1000;
++	context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
++	context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
+ 
+ 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+ 		bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index 1d66c4b09612..74186cf1c285 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -234,7 +234,6 @@ struct stream_resource {
+ 	struct output_pixel_processor *opp;
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	struct display_stream_compressor *dsc;
+-	int dscclk_khz;
+ #endif
+ 	struct timing_generator *tg;
+ 	struct stream_encoder *stream_enc;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3438-drm-amd-display-3.2.46.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3438-drm-amd-display-3.2.46.patch
new file mode 100644
index 00000000..3e47179f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3438-drm-amd-display-3.2.46.patch
@@ -0,0 +1,27 @@
+From 75c92ab758bea17d949315e12debd0aa747d4eae Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Mon, 29 Jul 2019 12:17:30 -0400
+Subject: [PATCH 3438/4256] drm/amd/display: 3.2.46
+
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 0ba04dc5af1d..4ce260aea985 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -42,7 +42,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.45"
++#define DC_VER "3.2.46"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3439-drm-amd-display-enable-dcn_mem_pwr-as-golden-setting.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3439-drm-amd-display-enable-dcn_mem_pwr-as-golden-setting.patch
new file mode 100644
index 00000000..e9433cb9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3439-drm-amd-display-enable-dcn_mem_pwr-as-golden-setting.patch
@@ -0,0 +1,32 @@
+From 606d584baefb7d28887ed4ada3c7932db27f3eb0 Mon Sep 17 00:00:00 2001
+From: Charlene Liu <charlene.liu@amd.com>
+Date: Mon, 29 Jul 2019 11:59:33 -0400
+Subject: [PATCH 3439/4256] drm/amd/display: enable dcn_mem_pwr as golden
+ setting updates
+
+Enable dcn_mem_pwr as golden setting updates
+
+Signed-off-by: Charlene Liu <charlene.liu@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index ea3b874497be..c4fced4103bf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -142,8 +142,7 @@ void dcn20_display_init(struct dc *dc)
+ 	/* DCCG */
+ 	dcn20_dccg_init(hws);
+ 
+-	/* Disable all memory low power mode. All memories are enabled. */
+-	REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 1);
++	REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 0);
+ 
+ 	/* DCHUB/MMHUBBUB
+ 	 * set global timer refclk divider
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3440-drm-amd-display-check-hpd-before-retry-verify-link-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3440-drm-amd-display-check-hpd-before-retry-verify-link-c.patch
new file mode 100644
index 00000000..f5abd36c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3440-drm-amd-display-check-hpd-before-retry-verify-link-c.patch
@@ -0,0 +1,129 @@
+From 17bb08b1420d8cb71ef456d6e4a2038ec0dad2dc Mon Sep 17 00:00:00 2001
+From: Wenjing Liu <Wenjing.Liu@amd.com>
+Date: Fri, 26 Jul 2019 14:53:20 -0400
+Subject: [PATCH 3440/4256] drm/amd/display: check hpd before retry verify link
+ cap
+
+[why]
+During detection link training if a display is disconnected,
+the current code will retry 3 times of link training
+on disconnected link before giving up.
+
+[how]
+Before each retry check for HPD status, only retry
+verify link cap when HPD is still high.
+Also put a 10ms delay between each retry to improve
+the chance of success.
+
+Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 27 +++++--------------
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 27 +++++++++++++++++++
+ .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |  5 ++++
+ 3 files changed, 38 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 429c1ad59089..c953f6d2770a 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -852,16 +852,9 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
+ 					dc_sink_release(prev_sink);
+ 				} else {
+ 					/* Empty dongle plug in */
+-					for (i = 0; i < LINK_TRAINING_MAX_VERIFY_RETRY; i++) {
+-						int fail_count = 0;
+-
+-						dp_verify_link_cap(link,
+-								  &link->reported_link_cap,
+-								  &fail_count);
+-
+-						if (fail_count == 0)
+-							break;
+-					}
++					dp_verify_link_cap_with_retries(link,
++							&link->reported_link_cap,
++							LINK_TRAINING_MAX_VERIFY_RETRY);
+ 				}
+ 				return true;
+ 			}
+@@ -965,17 +958,9 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
+ 			 */
+ 
+ 			/* deal with non-mst cases */
+-			for (i = 0; i < LINK_TRAINING_MAX_VERIFY_RETRY; i++) {
+-				int fail_count = 0;
+-
+-				dp_verify_link_cap(link,
+-						  &link->reported_link_cap,
+-						  &fail_count);
+-
+-				if (fail_count == 0)
+-					break;
+-			}
+-
++			dp_verify_link_cap_with_retries(link,
++					&link->reported_link_cap,
++					LINK_TRAINING_MAX_VERIFY_RETRY);
+ 		} else {
+ 			// If edid is the same, then discard new sink and revert back to original sink
+ 			if (same_edid) {
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 8e66b2e9d6af..2e87942b3e9c 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -1643,6 +1643,33 @@ bool dp_verify_link_cap(
+ 	return success;
+ }
+ 
++bool dp_verify_link_cap_with_retries(
++	struct dc_link *link,
++	struct dc_link_settings *known_limit_link_setting,
++	int attempts)
++{
++	uint8_t i = 0;
++	bool success = false;
++
++	for (i = 0; i < attempts; i++) {
++		int fail_count = 0;
++		enum dc_connection_type type;
++
++		memset(&link->verified_link_cap, 0,
++				sizeof(struct dc_link_settings));
++		if (!dc_link_detect_sink(link, &type)) {
++			break;
++		} else if (dp_verify_link_cap(link,
++				&link->reported_link_cap,
++				&fail_count) && fail_count == 0) {
++			success = true;
++			break;
++		}
++		msleep(10);
++	}
++	return success;
++}
++
+ static struct dc_link_settings get_common_supported_link_settings(
+ 		struct dc_link_settings link_setting_a,
+ 		struct dc_link_settings link_setting_b)
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+index b4e7b0c56f83..08a4df2c61a8 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+@@ -38,6 +38,11 @@ bool dp_verify_link_cap(
+ 	struct dc_link_settings *known_limit_link_setting,
+ 	int *fail_count);
+ 
++bool dp_verify_link_cap_with_retries(
++	struct dc_link *link,
++	struct dc_link_settings *known_limit_link_setting,
++	int attempts);
++
+ bool dp_validate_mode_timing(
+ 	struct dc_link *link,
+ 	const struct dc_crtc_timing *timing);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3441-drm-amd-display-audio-cannot-switch-to-internal-when.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3441-drm-amd-display-audio-cannot-switch-to-internal-when.patch
new file mode 100644
index 00000000..6f093d52
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3441-drm-amd-display-audio-cannot-switch-to-internal-when.patch
@@ -0,0 +1,47 @@
+From 18a0409a6bae5c4df971e8423d2dbc3067354c9b Mon Sep 17 00:00:00 2001
+From: yanyan kang <Yanyan.Kang@amd.com>
+Date: Mon, 29 Jul 2019 17:46:44 +0800
+Subject: [PATCH 3441/4256] drm/amd/display: audio cannot switch to internal
+ when display turns off
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+[why]
+disable_az_endpoint has been skipped because
+dc->debug.az_endpoint_mute_only = true.
+
+[how]
+set dc->debug.az_endpoint_mute_only false when PPLIB’s PME notification function
+ pointer is not NULL at the dcn10_resource construct function,because right now
+ SMU/PPLIB and DAL all have the AZ D3 force PME notification implemented. AZ D3 should work.
+
+Signed-off-by: yanyan kang <Yanyan.Kang@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index cd223603a0a8..2fb56dbefbda 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -1414,6 +1414,14 @@ static bool construct(
+ 
+ 	pool->base.pp_smu = dcn10_pp_smu_create(ctx);
+ 
++	/*
++	 * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification *
++	 * implemented. So AZ D3 should work.For issue 197007.                   *
++	 */
++	if (pool->base.pp_smu != NULL
++			&& pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL)
++		dc->debug.az_endpoint_mute_only = false;
++
+ 	if (!dc->debug.disable_pplib_clock_request)
+ 		dcn_bw_update_from_pplib(dc);
+ 	dcn_bw_sync_calcs_and_dml(dc);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3442-drm-amd-display-Enable-MPO-with-pre-blend-color-proc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3442-drm-amd-display-Enable-MPO-with-pre-blend-color-proc.patch
new file mode 100644
index 00000000..496b6adc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3442-drm-amd-display-Enable-MPO-with-pre-blend-color-proc.patch
@@ -0,0 +1,153 @@
+From b3a26e04b16a28610b08eb914b7e1b8980a28760 Mon Sep 17 00:00:00 2001
+From: Michael Strauss <michael.strauss@amd.com>
+Date: Fri, 26 Jul 2019 12:04:12 -0400
+Subject: [PATCH 3442/4256] drm/amd/display: Enable MPO with pre-blend color
+ processing (RGB)
+
+[Why]
+DCN10 performs color processing before MPC combination, causes color
+shift in RGB colorspaces when positive brightness offset is applied
+However, YCbCr is still unfixed and remains disabled
+
+[How]
+Add layerIndex to dc_plane_state and dc_plane_info structs
+Re-enable MPO when brightness is adjusted and colorspace is not YCbCr
+Set rear plane's brightness offset to 0 when front plane visible
+
+Signed-off-by: Michael Strauss <michael.strauss@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 ++
+ drivers/gpu/drm/amd/display/dc/core/dc.c      |  2 +
+ drivers/gpu/drm/amd/display/dc/dc.h           |  2 +
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 51 ++++++++++++++++++-
+ 4 files changed, 56 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index a1ee74584913..474eb6849dc7 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -3089,6 +3089,8 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
+         plane_info->visible = true;
+         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
+ 
++	plane_info->layer_index = 0;
++
+         ret = fill_plane_color_attributes(plane_state, plane_info->format,
+                                           &plane_info->color_space);
+         if (ret)
+@@ -3154,6 +3156,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
+         dc_plane_state->global_alpha = plane_info.global_alpha;
+         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
+         dc_plane_state->dcc = plane_info.dcc;
++	dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
+ 
+ 	/*
+ 	 * Always set input transfer function, since plane state is refreshed
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 90c860d8e449..541c94fba481 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1701,6 +1701,8 @@ static void copy_surface_update_to_plane(
+ 				srf_update->plane_info->dcc;
+ 		surface->sdr_white_level =
+ 				srf_update->plane_info->sdr_white_level;
++		surface->layer_index =
++				srf_update->plane_info->layer_index;
+ 	}
+ 
+ 	if (srf_update->gamma &&
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 4ce260aea985..85863dcf8456 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -764,6 +764,7 @@ struct dc_plane_state {
+ 	bool visible;
+ 	bool flip_immediate;
+ 	bool horizontal_mirror;
++	int layer_index;
+ 
+ 	union surface_update_flags update_flags;
+ 	/* private to DC core */
+@@ -793,6 +794,7 @@ struct dc_plane_info {
+ 	bool global_alpha;
+ 	int  global_alpha_value;
+ 	bool input_csc_enabled;
++	int layer_index;
+ };
+ 
+ struct dc_scaling_info {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 2846017a544d..1835157b9fad 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1903,6 +1903,36 @@ static void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)
+ 	pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
+ }
+ 
++
++static bool dcn10_is_rear_mpo_fix_required(struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace)
++{
++	if (pipe_ctx->plane_state && pipe_ctx->plane_state->layer_index > 0 && is_rgb_cspace(colorspace)) {
++		if (pipe_ctx->top_pipe) {
++			struct pipe_ctx *top = pipe_ctx->top_pipe;
++
++			while (top->top_pipe)
++				top = top->top_pipe; // Traverse to top pipe_ctx
++			if (top->plane_state && top->plane_state->layer_index == 0)
++				return true; // Front MPO plane not hidden
++		}
++	}
++	return false;
++}
++
++static void dcn10_set_csc_adjustment_rgb_mpo_fix(struct pipe_ctx *pipe_ctx, uint16_t *matrix)
++{
++	// Override rear plane RGB bias to fix MPO brightness
++	uint16_t rgb_bias = matrix[3];
++
++	matrix[3] = 0;
++	matrix[7] = 0;
++	matrix[11] = 0;
++	pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
++	matrix[3] = rgb_bias;
++	matrix[7] = rgb_bias;
++	matrix[11] = rgb_bias;
++}
++
+ static void dcn10_program_output_csc(struct dc *dc,
+ 		struct pipe_ctx *pipe_ctx,
+ 		enum dc_color_space colorspace,
+@@ -1910,8 +1940,25 @@ static void dcn10_program_output_csc(struct dc *dc,
+ 		int opp_id)
+ {
+ 	if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
+-		if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
+-			pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
++		if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) {
++
++			/* MPO is broken with RGB colorspaces when OCSC matrix
++			 * brightness offset >= 0 on DCN1 due to OCSC before MPC
++			 * Blending adds offsets from front + rear to rear plane
++			 *
++			 * Fix is to set RGB bias to 0 on rear plane, top plane
++			 * black value pixels add offset instead of rear + front
++			 */
++
++			int16_t rgb_bias = matrix[3];
++			// matrix[3/7/11] are all the same offset value
++
++			if (rgb_bias > 0 && dcn10_is_rear_mpo_fix_required(pipe_ctx, colorspace)) {
++				dcn10_set_csc_adjustment_rgb_mpo_fix(pipe_ctx, matrix);
++			} else {
++				pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
++			}
++		}
+ 	} else {
+ 		if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
+ 			pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3443-drm-amd-display-Load-NV12-SOC-BB-from-firmware.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3443-drm-amd-display-Load-NV12-SOC-BB-from-firmware.patch
new file mode 100644
index 00000000..c9d65b9e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3443-drm-amd-display-Load-NV12-SOC-BB-from-firmware.patch
@@ -0,0 +1,311 @@
+From e3cde02f51794051497381012ddf9353a865c19d Mon Sep 17 00:00:00 2001
+From: Leo Li <sunpeng.li@amd.com>
+Date: Tue, 6 Aug 2019 13:50:28 -0400
+Subject: [PATCH 3443/4256] drm/amd/display: Load NV12 SOC BB from firmware
+
+[Why]
+
+Previous SOC bounding box firmware loading logic was for NV10, when we
+still had it in firmware. Now that it's brought into driver code, and
+NV12 BB is in firmware, this logic needs to be repurposed for NV12.
+
+[How]
+
+Set SOC_BOUNDING_BOX_VALID to false, and add the dcn_2_0_nv12_soc BB
+struct. In init_soc_bounding_box, load firmware to nv12 BB instead.
+
+In addition, conditionally update and patch the BB, depending on ASIC
+REV.
+
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 156 +++++++++++-------
+ 1 file changed, 96 insertions(+), 60 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 000b2bfe54fb..c59f31dcdc0d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -80,7 +80,8 @@
+ 
+ #include "amdgpu_socbb.h"
+ 
+-#define SOC_BOUNDING_BOX_VALID true
++/* NV12 SOC BB is currently in FW, mark SW bounding box invalid. */
++#define SOC_BOUNDING_BOX_VALID false
+ #define DC_LOGGER_INIT(logger)
+ 
+ struct _vcs_dpi_ip_params_st dcn2_0_ip = {
+@@ -266,6 +267,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
+ 	.use_urgent_burst_bw = 0
+ };
+ 
++struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
+ 
+ #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
+ 	#define mmDP0_DP_DPHY_INTERNAL_CTRL		0x210f
+@@ -3042,6 +3044,27 @@ static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
+ 	kernel_fpu_end();
+ }
+ 
++static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
++	uint32_t hw_internal_rev)
++{
++	if (ASICREV_IS_NAVI12_P(hw_internal_rev))
++		return &dcn2_0_nv12_soc;
++
++	return &dcn2_0_soc;
++}
++
++static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
++	uint32_t hw_internal_rev)
++{
++	/* NV12 and NV10 */
++	return &dcn2_0_ip;
++}
++
++static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
++{
++	return DML_PROJECT_NAVI10v2;
++}
++
+ #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
+ #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
+ 
+@@ -3049,6 +3072,11 @@ static bool init_soc_bounding_box(struct dc *dc,
+ 				  struct dcn20_resource_pool *pool)
+ {
+ 	const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
++	struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
++			get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
++	struct _vcs_dpi_ip_params_st *loaded_ip =
++			get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
++
+ 	DC_LOGGER_INIT(dc->ctx->logger);
+ 
+ 	if (!bb && !SOC_BOUNDING_BOX_VALID) {
+@@ -3059,101 +3087,103 @@ static bool init_soc_bounding_box(struct dc *dc,
+ 	if (bb && !SOC_BOUNDING_BOX_VALID) {
+ 		int i;
+ 
+-		dcn2_0_soc.sr_exit_time_us =
++		dcn2_0_nv12_soc.sr_exit_time_us =
+ 				fixed16_to_double_to_cpu(bb->sr_exit_time_us);
+-		dcn2_0_soc.sr_enter_plus_exit_time_us =
++		dcn2_0_nv12_soc.sr_enter_plus_exit_time_us =
+ 				fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
+-		dcn2_0_soc.urgent_latency_us =
++		dcn2_0_nv12_soc.urgent_latency_us =
+ 				fixed16_to_double_to_cpu(bb->urgent_latency_us);
+-		dcn2_0_soc.urgent_latency_pixel_data_only_us =
++		dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us =
+ 				fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
+-		dcn2_0_soc.urgent_latency_pixel_mixed_with_vm_data_us =
++		dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us =
+ 				fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
+-		dcn2_0_soc.urgent_latency_vm_data_only_us =
++		dcn2_0_nv12_soc.urgent_latency_vm_data_only_us =
+ 				fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
+-		dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
++		dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
+ 				le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
+-		dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
++		dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
+ 				le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
+-		dcn2_0_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
++		dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
+ 				le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
+-		dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
++		dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
+ 				fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
+-		dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
++		dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
+ 				fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
+-		dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
++		dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
+ 				fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
+-		dcn2_0_soc.max_avg_sdp_bw_use_normal_percent =
++		dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent =
+ 				fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
+-		dcn2_0_soc.max_avg_dram_bw_use_normal_percent =
++		dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent =
+ 				fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
+-		dcn2_0_soc.writeback_latency_us =
++		dcn2_0_nv12_soc.writeback_latency_us =
+ 				fixed16_to_double_to_cpu(bb->writeback_latency_us);
+-		dcn2_0_soc.ideal_dram_bw_after_urgent_percent =
++		dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent =
+ 				fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
+-		dcn2_0_soc.max_request_size_bytes =
++		dcn2_0_nv12_soc.max_request_size_bytes =
+ 				le32_to_cpu(bb->max_request_size_bytes);
+-		dcn2_0_soc.dram_channel_width_bytes =
++		dcn2_0_nv12_soc.dram_channel_width_bytes =
+ 				le32_to_cpu(bb->dram_channel_width_bytes);
+-		dcn2_0_soc.fabric_datapath_to_dcn_data_return_bytes =
++		dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes =
+ 				le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
+-		dcn2_0_soc.dcn_downspread_percent =
++		dcn2_0_nv12_soc.dcn_downspread_percent =
+ 				fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
+-		dcn2_0_soc.downspread_percent =
++		dcn2_0_nv12_soc.downspread_percent =
+ 				fixed16_to_double_to_cpu(bb->downspread_percent);
+-		dcn2_0_soc.dram_page_open_time_ns =
++		dcn2_0_nv12_soc.dram_page_open_time_ns =
+ 				fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
+-		dcn2_0_soc.dram_rw_turnaround_time_ns =
++		dcn2_0_nv12_soc.dram_rw_turnaround_time_ns =
+ 				fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
+-		dcn2_0_soc.dram_return_buffer_per_channel_bytes =
++		dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes =
+ 				le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
+-		dcn2_0_soc.round_trip_ping_latency_dcfclk_cycles =
++		dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles =
+ 				le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
+-		dcn2_0_soc.urgent_out_of_order_return_per_channel_bytes =
++		dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes =
+ 				le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
+-		dcn2_0_soc.channel_interleave_bytes =
++		dcn2_0_nv12_soc.channel_interleave_bytes =
+ 				le32_to_cpu(bb->channel_interleave_bytes);
+-		dcn2_0_soc.num_banks =
++		dcn2_0_nv12_soc.num_banks =
+ 				le32_to_cpu(bb->num_banks);
+-		dcn2_0_soc.num_chans =
++		dcn2_0_nv12_soc.num_chans =
+ 				le32_to_cpu(bb->num_chans);
+-		dcn2_0_soc.vmm_page_size_bytes =
++		dcn2_0_nv12_soc.vmm_page_size_bytes =
+ 				le32_to_cpu(bb->vmm_page_size_bytes);
+-		dcn2_0_soc.dram_clock_change_latency_us =
++		dcn2_0_nv12_soc.dram_clock_change_latency_us =
+ 				fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
+-		dcn2_0_soc.writeback_dram_clock_change_latency_us =
++		// HACK!! Lower uclock latency switch time so we don't switch
++		dcn2_0_nv12_soc.dram_clock_change_latency_us = 10;
++		dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us =
+ 				fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
+-		dcn2_0_soc.return_bus_width_bytes =
++		dcn2_0_nv12_soc.return_bus_width_bytes =
+ 				le32_to_cpu(bb->return_bus_width_bytes);
+-		dcn2_0_soc.dispclk_dppclk_vco_speed_mhz =
++		dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz =
+ 				le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
+-		dcn2_0_soc.xfc_bus_transport_time_us =
++		dcn2_0_nv12_soc.xfc_bus_transport_time_us =
+ 				le32_to_cpu(bb->xfc_bus_transport_time_us);
+-		dcn2_0_soc.xfc_xbuf_latency_tolerance_us =
++		dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us =
+ 				le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
+-		dcn2_0_soc.use_urgent_burst_bw =
++		dcn2_0_nv12_soc.use_urgent_burst_bw =
+ 				le32_to_cpu(bb->use_urgent_burst_bw);
+-		dcn2_0_soc.num_states =
++		dcn2_0_nv12_soc.num_states =
+ 				le32_to_cpu(bb->num_states);
+ 
+-		for (i = 0; i < dcn2_0_soc.num_states; i++) {
+-			dcn2_0_soc.clock_limits[i].state =
++		for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) {
++			dcn2_0_nv12_soc.clock_limits[i].state =
+ 					le32_to_cpu(bb->clock_limits[i].state);
+-			dcn2_0_soc.clock_limits[i].dcfclk_mhz =
++			dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz =
+ 					fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
+-			dcn2_0_soc.clock_limits[i].fabricclk_mhz =
++			dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz =
+ 					fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
+-			dcn2_0_soc.clock_limits[i].dispclk_mhz =
++			dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz =
+ 					fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
+-			dcn2_0_soc.clock_limits[i].dppclk_mhz =
++			dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz =
+ 					fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
+-			dcn2_0_soc.clock_limits[i].phyclk_mhz =
++			dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz =
+ 					fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
+-			dcn2_0_soc.clock_limits[i].socclk_mhz =
++			dcn2_0_nv12_soc.clock_limits[i].socclk_mhz =
+ 					fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
+-			dcn2_0_soc.clock_limits[i].dscclk_mhz =
++			dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz =
+ 					fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
+-			dcn2_0_soc.clock_limits[i].dram_speed_mts =
++			dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts =
+ 					fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
+ 		}
+ 	}
+@@ -3184,14 +3214,14 @@ static bool init_soc_bounding_box(struct dc *dc,
+ 		}
+ 
+ 		if (clock_limits_available && uclk_states_available && num_states)
+-			update_bounding_box(dc, &dcn2_0_soc, &max_clocks, uclk_states, num_states);
++			update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
+ 		else if (clock_limits_available)
+-			cap_soc_clocks(&dcn2_0_soc, max_clocks);
++			cap_soc_clocks(loaded_bb, max_clocks);
+ 	}
+ 
+-	dcn2_0_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
+-	dcn2_0_ip.max_num_dpp = pool->base.pipe_count;
+-	patch_bounding_box(dc, &dcn2_0_soc);
++	loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
++	loaded_ip->max_num_dpp = pool->base.pipe_count;
++	patch_bounding_box(dc, loaded_bb);
+ 
+ 	return true;
+ }
+@@ -3204,6 +3234,12 @@ static bool construct(
+ 	int i;
+ 	struct dc_context *ctx = dc->ctx;
+ 	struct irq_service_init_data init_data;
++	struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
++			get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
++	struct _vcs_dpi_ip_params_st *loaded_ip =
++			get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
++	enum dml_project dml_project_version =
++			get_dml_project_version(ctx->asic_id.hw_internal_rev);
+ 
+ 	ctx->dc_bios->regs = &bios_regs;
+ 	pool->base.funcs = &dcn20_res_pool_funcs;
+@@ -3327,7 +3363,7 @@ static bool construct(
+ 		goto create_fail;
+ 	}
+ 
+-	dml_init_instance(&dc->dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10v2);
++	dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
+ 
+ 	if (!dc->debug.disable_pplib_wm_range) {
+ 		struct pp_smu_wm_range_sets ranges = {0};
+@@ -3335,7 +3371,7 @@ static bool construct(
+ 
+ 		ranges.num_reader_wm_sets = 0;
+ 
+-		if (dcn2_0_soc.num_states == 1) {
++		if (loaded_bb->num_states == 1) {
+ 			ranges.reader_wm_sets[0].wm_inst = i;
+ 			ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+ 			ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+@@ -3343,13 +3379,13 @@ static bool construct(
+ 			ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+ 
+ 			ranges.num_reader_wm_sets = 1;
+-		} else if (dcn2_0_soc.num_states > 1) {
+-			for (i = 0; i < 4 && i < dcn2_0_soc.num_states; i++) {
++		} else if (loaded_bb->num_states > 1) {
++			for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
+ 				ranges.reader_wm_sets[i].wm_inst = i;
+ 				ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+ 				ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+-				ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (dcn2_0_soc.clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
+-				ranges.reader_wm_sets[i].max_fill_clk_mhz = dcn2_0_soc.clock_limits[i].dram_speed_mts / 16;
++				ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
++				ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
+ 
+ 				ranges.num_reader_wm_sets = i + 1;
+ 			}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3444-drm-amdkfd-add-debug-notification.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3444-drm-amdkfd-add-debug-notification.patch
new file mode 100644
index 00000000..69b42ac6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3444-drm-amdkfd-add-debug-notification.patch
@@ -0,0 +1,577 @@
+From 149171bf2e15568cb3d7169d6e4c6dbd5fbaa8cb Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Thu, 9 May 2019 20:49:29 -0400
+Subject: [PATCH 3444/4256] drm/amdkfd: add debug notification
+
+User space adds trace to process.  Ring buffer entry is flagged by IH and
+process info is sent to debug event handler by kernel.  Kernel updates queue
+debug event status as pending event by doorbell id and updates fifo data
+accessible by user space after kernel sends wake signal on polling fd.  Fifo
+data records debug event history as fifo string where 't' is trap and 'v'
+is vm fault.
+
+User space can query pending events by target queue id or find the first
+queue with a pending event.  User space also has option of clearing pending
+event status on target (or first found) queue.  Kernel will report queried
+pending event type (trap or vm fault) and suspend status of queue.
+
+Change-Id: Ied5b7c21306638c8cfdaac8d8b9bae342b235b47
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/Makefile           |   3 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c      |  18 ++
+ drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c | 285 ++++++++++++++++++
+ drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h |  40 +++
+ .../gpu/drm/amd/amdkfd/kfd_int_process_v9.c   |  27 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h         |  11 +
+ include/uapi/linux/kfd_ioctl.h                |  21 +-
+ 7 files changed, 396 insertions(+), 9 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
+ create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile
+index dad236a68a25..aa951107a895 100644
+--- a/drivers/gpu/drm/amd/amdkfd/Makefile
++++ b/drivers/gpu/drm/amd/amdkfd/Makefile
+@@ -59,7 +59,8 @@ AMDKFD_FILES	:= $(AMDKFD_PATH)/kfd_module.o \
+ 		$(AMDKFD_PATH)/kfd_rdma.o \
+ 		$(AMDKFD_PATH)/kfd_peerdirect.o \
+ 		$(AMDKFD_PATH)/kfd_ipc.o \
+-		$(AMDKFD_PATH)/kfd_trace.o
++		$(AMDKFD_PATH)/kfd_trace.o \
++		$(AMDKFD_PATH)/kfd_debug_events.o
+ 
+ ifneq ($(CONFIG_AMD_IOMMU_V2),)
+ AMDKFD_FILES += $(AMDKFD_PATH)/kfd_iommu.o
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index e96aa4eaaa66..44a9803f26f3 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -42,6 +42,7 @@
+ #include "kfd_priv.h"
+ #include "kfd_device_queue_manager.h"
+ #include "kfd_dbgmgr.h"
++#include "kfd_debug_events.h"
+ #include "kfd_ipc.h"
+ #include "kfd_trace.h"
+ 
+@@ -2736,6 +2737,18 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 			r = dev->kfd2kgd->enable_debug_trap(dev->kgd,
+ 					pdd->trap_debug_wave_launch_mode,
+ 					dev->vm_info.last_vmid_kfd);
++			if (r)
++				break;
++
++			r = kfd_dbg_ev_enable(pdd);
++			if (r >= 0) {
++				args->data3 = r;
++				r = 0;
++			} else {
++				pdd->debug_trap_enabled = false;
++				dev->kfd2kgd->disable_debug_trap(dev->kgd);
++			}
++
+ 			break;
+ 		default:
+ 			pr_err("Invalid trap enable option: %i\n",
+@@ -2783,6 +2796,11 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 		if (r)
+ 			goto unlock_out;
+ 		break;
++	case KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT:
++		r = kfd_dbg_ev_query_debug_event(pdd, &args->data1,
++						 args->data2,
++						 &args->data3);
++		break;
+ 	default:
+ 		pr_err("Invalid option: %i\n", debug_trap_action);
+ 		r = -EINVAL;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
+new file mode 100644
+index 000000000000..210cccdeed81
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
+@@ -0,0 +1,285 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include <linux/kfifo.h>
++#include <linux/poll.h>
++#include <linux/wait.h>
++#include <linux/anon_inodes.h>
++#include <uapi/linux/kfd_ioctl.h>
++#include "kfd_debug_events.h"
++#include "kfd_priv.h"
++#include "kfd_topology.h"
++
++/* poll and read functions */
++static __poll_t kfd_dbg_ev_poll(struct file *, struct poll_table_struct *);
++static ssize_t kfd_dbg_ev_read(struct file *, char __user *, size_t, loff_t *);
++static int kfd_dbg_ev_release(struct inode *, struct file *);
++
++/* fd name */
++static const char kfd_dbg_name[] = "kfd_debug";
++
++/* fops for polling, read and ioctl */
++static const struct file_operations kfd_dbg_ev_fops = {
++	.owner = THIS_MODULE,
++	.poll = kfd_dbg_ev_poll,
++	.read = kfd_dbg_ev_read,
++	.release = kfd_dbg_ev_release
++};
++
++/* poll on wait queue of file */
++static __poll_t kfd_dbg_ev_poll(struct file *filep,
++				struct poll_table_struct *wait)
++{
++
++	struct kfd_debug_process_device *dpd = filep->private_data;
++
++	__poll_t mask = 0;
++
++	/* pending event have been queue'd via interrupt */
++	poll_wait(filep, &dpd->wait_queue, wait);
++	mask |= !kfifo_is_empty(&dpd->fifo) ? POLLIN | POLLRDNORM : mask;
++
++	return mask;
++}
++
++/* read based on wait entries and return types found */
++static ssize_t kfd_dbg_ev_read(struct file *filep, char __user *user,
++			       size_t size, loff_t *offset)
++{
++	int ret, copied;
++	struct kfd_debug_process_device *dpd = filep->private_data;
++
++	ret = kfifo_to_user(&dpd->fifo, user, size, &copied);
++
++	if (ret) {
++		pr_debug("KFD DEBUG EVENT: Failed to read poll fd (%i)\n", ret);
++		return ret;
++	}
++
++	return copied;
++}
++
++static int kfd_dbg_ev_release(struct inode *inode, struct file *filep)
++{
++	struct kfd_debug_process_device *dpd = filep->private_data;
++
++	kfifo_free(&dpd->fifo);
++
++	return 0;
++}
++
++/* query pending events and return queue_id, event_type and is_suspended */
++#define KFD_DBG_EV_SET_SUSPEND_STATE(x, s)			\
++	((x) = (s) ? (x) | KFD_DBG_EV_STATUS_SUSPENDED :	\
++		(x) & ~KFD_DBG_EV_STATUS_SUSPENDED)
++
++#define KFD_DBG_EV_SET_EVENT_TYPE(x, e)				\
++	((x) = ((x) & ~(KFD_DBG_EV_STATUS_TRAP			\
++		| KFD_DBG_EV_STATUS_VMFAULT)) | (e))
++
++int kfd_dbg_ev_query_debug_event(struct kfd_process_device *pdd,
++		      unsigned int *queue_id,
++		      unsigned int flags,
++		      uint32_t *event_status)
++{
++	struct process_queue_manager *pqm;
++	struct process_queue_node *pqn;
++	struct queue *q;
++	int ret = 0;
++
++	if (!pdd || !pdd->process)
++		return -ENODATA;
++
++	/* lock process events to update event queues */
++	mutex_lock(&pdd->process->event_mutex);
++	pqm = &pdd->process->pqm;
++
++	if (*queue_id != KFD_INVALID_QUEUEID) {
++		q = pqm_get_user_queue(pqm, *queue_id);
++
++		if (!q) {
++			ret = -EINVAL;
++			goto out;
++		}
++
++		KFD_DBG_EV_SET_EVENT_TYPE(*event_status,
++					  q->properties.debug_event_type);
++		KFD_DBG_EV_SET_SUSPEND_STATE(*event_status,
++					  q->properties.is_suspended);
++		if (flags & KFD_DBG_EV_FLAG_CLEAR_STATUS)
++			q->properties.debug_event_type = 0;
++		goto out;
++
++	} else {
++		list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
++			if (pqn->q &&
++				 (pqn->q->properties.debug_event_type
++					== KFD_DBG_EV_STATUS_TRAP
++				|| pqn->q->properties.debug_event_type
++					== KFD_DBG_EV_STATUS_VMFAULT)) {
++				*queue_id = pqn->q->properties.queue_id;
++				KFD_DBG_EV_SET_EVENT_TYPE(*event_status,
++					pqn->q->properties.debug_event_type);
++				KFD_DBG_EV_SET_SUSPEND_STATE(*event_status,
++					pqn->q->properties.is_suspended);
++				if (flags & KFD_DBG_EV_FLAG_CLEAR_STATUS)
++					pqn->q->properties.debug_event_type
++									= 0;
++				goto out;
++			}
++		}
++		ret = -EAGAIN;
++	}
++
++out:
++	mutex_unlock(&pdd->process->event_mutex);
++	return ret;
++}
++
++/* create event queue struct associated with process per device */
++static int kfd_create_event_queue(struct kfd_process_device *pdd)
++{
++	struct process_queue_manager *pqm;
++	struct process_queue_node *pqn;
++	struct kfd_topology_device *tdev;
++	int ret;
++
++	if (!pdd || !pdd->process)
++		return -ESRCH;
++
++	tdev = kfd_topology_device_by_id(pdd->dev->id);
++
++	pdd->dpd.max_debug_events = tdev->node_props.simd_count
++				* tdev->node_props.max_waves_per_simd;
++
++	ret = kfifo_alloc(&pdd->dpd.fifo, pdd->dpd.max_debug_events,
++			  GFP_KERNEL);
++
++	if (ret)
++		return ret;
++
++	init_waitqueue_head(&pdd->dpd.wait_queue);
++
++	pqm = &pdd->process->pqm;
++
++	/* to reset queue pending status - TBD need init in queue creation */
++	list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
++		if (pqn->q->device == pdd->dev)
++			pqn->q->properties.debug_event_type = 0;
++	}
++
++	return ret;
++}
++
++/* update process device, write to kfifo and wake up wait queue  */
++static void kfd_dbg_ev_update_event_queue(struct kfd_process_device *pdd,
++					  unsigned int doorbell_id,
++					  bool is_vmfault)
++{
++	struct process_queue_manager *pqm;
++	struct process_queue_node *pqn;
++	char fifo_output;
++
++	if (!pdd->debug_trap_enabled)
++		return;
++
++	pqm = &pdd->process->pqm;
++
++	/* iterate through each queue */
++	list_for_each_entry(pqn, &pqm->queues,
++				process_queue_list) {
++
++		if (!pqn->q)
++			continue;
++
++		if (pqn->q->device != pdd->dev)
++			continue;
++
++		if (pqn->q->doorbell_id != doorbell_id && !is_vmfault)
++			continue;
++
++		pqn->q->properties.debug_event_type |=
++			is_vmfault ? KFD_DBG_EV_STATUS_VMFAULT :
++					KFD_DBG_EV_STATUS_TRAP;
++
++		fifo_output = is_vmfault ? 'v' : 't';
++
++		kfifo_in(&pdd->dpd.fifo, &fifo_output, 1);
++
++		wake_up_all(&pdd->dpd.wait_queue);
++
++		if (!is_vmfault)
++			break;
++	}
++}
++
++/* set pending event queue entry from ring entry  */
++void kfd_set_dbg_ev_from_interrupt(struct kfd_dev *dev,
++				   unsigned int pasid,
++				   uint32_t doorbell_id,
++				   bool is_vmfault)
++{
++	struct kfd_process *p;
++	struct kfd_process_device *pdd;
++
++	p = kfd_lookup_process_by_pasid(pasid);
++
++	if (!p)
++		return;
++
++	pdd = kfd_get_process_device_data(dev, p);
++
++	if (!pdd) {
++		kfd_unref_process(p);
++		return;
++	}
++
++	mutex_lock(&p->event_mutex);
++
++	kfd_dbg_ev_update_event_queue(pdd, doorbell_id, is_vmfault);
++
++	mutex_unlock(&p->event_mutex);
++
++	kfd_unref_process(p);
++}
++
++/* enable debug and return file pointer struct */
++int kfd_dbg_ev_enable(struct kfd_process_device *pdd)
++{
++	int ret;
++
++	if (!pdd || !pdd->process)
++		return -ESRCH;
++
++	mutex_lock(&pdd->process->event_mutex);
++
++	ret = kfd_create_event_queue(pdd);
++
++	mutex_unlock(&pdd->process->event_mutex);
++
++	if (ret)
++		return ret;
++
++	return anon_inode_getfd(kfd_dbg_name, &kfd_dbg_ev_fops,
++				(void *)&pdd->dpd, 0);
++}
++
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h
+new file mode 100644
+index 000000000000..5b035a4321c6
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h
+@@ -0,0 +1,40 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef KFD_DEBUG_EVENTS_H_INCLUDED
++#define KFD_DEBUG_EVENTS_H_INCLUDED
++
++#include "kfd_priv.h"
++
++int kfd_dbg_ev_query_debug_event(struct kfd_process_device *pdd,
++		      unsigned int *queue_id,
++		      unsigned int flags,
++		      uint32_t *event_status);
++
++void kfd_set_dbg_ev_from_interrupt(struct kfd_dev *dev,
++				   unsigned int pasid,
++				   uint32_t doorbell_id,
++				   bool is_vmfault);
++
++int kfd_dbg_ev_enable(struct kfd_process_device *pdd);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
+index 3ef67d2e0d9f..ab8a695c4a3c 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
+@@ -22,9 +22,13 @@
+ 
+ #include "kfd_priv.h"
+ #include "kfd_events.h"
++#include "kfd_debug_events.h"
+ #include "soc15_int.h"
+ #include "kfd_device_queue_manager.h"
+ 
++#define KFD_CONTEXT_ID_DEBUG_TRAP_MASK		0x000080
++#define KFD_CONTEXT_ID_DEBUG_DOORBELL_MASK	0x0003ff
++
+ static bool event_interrupt_isr_v9(struct kfd_dev *dev,
+ 					const uint32_t *ih_ring_entry,
+ 					uint32_t *patched_ihre,
+@@ -88,21 +92,29 @@ static void event_interrupt_wq_v9(struct kfd_dev *dev,
+ 					const uint32_t *ih_ring_entry)
+ {
+ 	uint16_t source_id, client_id, pasid, vmid;
+-	uint32_t context_id;
++	uint32_t context_id0, context_id1;
+ 
+ 	source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry);
+ 	client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry);
+ 	pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry);
+ 	vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
+-	context_id = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry);
++	context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry);
++	context_id1 = SOC15_CONTEXT_ID1_FROM_IH_ENTRY(ih_ring_entry);
+ 
+ 	if (source_id == SOC15_INTSRC_CP_END_OF_PIPE)
+-		kfd_signal_event_interrupt(pasid, context_id, 32);
++		kfd_signal_event_interrupt(pasid, context_id0, 32);
+ 	else if (source_id == SOC15_INTSRC_SDMA_TRAP)
+-		kfd_signal_event_interrupt(pasid, context_id & 0xfffffff, 28);
+-	else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG)
+-		kfd_signal_event_interrupt(pasid, context_id & 0xffffff, 24);
+-	else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE)
++		kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28);
++	else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) {
++		if (context_id1 & KFD_CONTEXT_ID_DEBUG_TRAP_MASK) {
++			kfd_set_dbg_ev_from_interrupt(dev, pasid,
++					context_id0 &
++					KFD_CONTEXT_ID_DEBUG_DOORBELL_MASK,
++					false);
++		} else
++			kfd_signal_event_interrupt(pasid,
++						   context_id0 & 0xffffff, 24);
++	} else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE)
+ 		kfd_signal_hw_exception_event(pasid);
+ 	else if (client_id == SOC15_IH_CLIENTID_VMC ||
+ 		client_id == SOC15_IH_CLIENTID_VMC1 ||
+@@ -118,6 +130,7 @@ static void event_interrupt_wq_v9(struct kfd_dev *dev,
+ 		info.prot_read  = ring_id & 0x10;
+ 		info.prot_write = ring_id & 0x20;
+ 
++		kfd_set_dbg_ev_from_interrupt(dev, pasid, -1, true);
+ 		kfd_process_vm_fault(dev->dqm, pasid);
+ 		kfd_signal_vm_fault_event(dev, pasid, &info);
+ 	}
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index 40c2b0d5a954..73aa6a3330eb 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -510,6 +510,7 @@ struct queue_properties {
+ 	/* Relevant for CU */
+ 	uint32_t cu_mask_count; /* Must be a multiple of 32 */
+ 	uint32_t *cu_mask;
++	unsigned int debug_event_type;
+ };
+ 
+ #define QUEUE_IS_ACTIVE(q) ((q).queue_size > 0 &&	\
+@@ -696,6 +697,13 @@ enum kfd_pdd_bound {
+ 	PDD_BOUND_SUSPENDED,
+ };
+ 
++struct kfd_debug_process_device {
++	struct kfifo fifo;
++	wait_queue_head_t wait_queue;
++	int max_debug_events;
++};
++
++
+ /* Data that is per-process-per device. */
+ struct kfd_process_device {
+ 	/*
+@@ -710,6 +718,9 @@ struct kfd_process_device {
+ 	/* The process that owns this kfd_process_device. */
+ 	struct kfd_process *process;
+ 
++	/* per-process-per device debug event info */
++	struct kfd_debug_process_device dpd;
++
+ 	/* per-process-per device QCM data structure */
+ 	struct qcm_process_device qpd;
+ 
+diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
+index 8c2862565444..617c07047d55 100644
+--- a/include/uapi/linux/kfd_ioctl.h
++++ b/include/uapi/linux/kfd_ioctl.h
+@@ -187,11 +187,19 @@ struct kfd_ioctl_dbg_wave_control_args {
+ 	__u32 buf_size_in_bytes;	/*including gpu_id and buf_size */
+ };
+ 
++/* mapping event types to API spec */
++#define	KFD_DBG_EV_STATUS_TRAP		1
++#define	KFD_DBG_EV_STATUS_VMFAULT	2
++#define	KFD_DBG_EV_STATUS_SUSPENDED	4
++#define	KFD_DBG_EV_FLAG_CLEAR_STATUS	1
++
++#define KFD_INVALID_QUEUEID	0xffffffff
++
+ /* KFD_IOC_DBG_TRAP_ENABLE:
+  * ptr:   unused
+  * data1: 0=disable, 1=enable
+  * data2: queue ID (for future use)
+- * data3: unused
++ * data3: return value for fd
+  */
+ #define KFD_IOC_DBG_TRAP_ENABLE 0
+ 
+@@ -235,6 +243,14 @@ struct kfd_ioctl_dbg_wave_control_args {
+  */
+ #define KFD_IOC_DBG_TRAP_NODE_RESUME 5
+ 
++/* KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT:
++ * ptr: unused
++ * data1: queue id (IN/OUT)
++ * data2: flags (IN)
++ * data3: suspend[2:2], event type [1:0] (OUT)
++ */
++#define KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT 6
++
+ struct kfd_ioctl_dbg_trap_args {
+ 	__u64 ptr;     /* to KFD -- used for pointer arguments: queue arrays */
+ 	__u32 pid;     /* to KFD */
+@@ -657,6 +673,9 @@ struct kfd_ioctl_cross_memory_copy_args {
+ #define AMDKFD_IOC_IPC_EXPORT_HANDLE		\
+ 		AMDKFD_IOWR(0x20, struct kfd_ioctl_ipc_export_handle_args)
+ 
++#define AMDKFD_IOC_DBG_TRAP			\
++		AMDKFD_IOWR(0x21, struct kfd_ioctl_dbg_trap_args)
++
+ #define AMDKFD_IOC_CROSS_MEMORY_COPY		\
+ 		AMDKFD_IOWR(0x22, struct kfd_ioctl_cross_memory_copy_args)
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3445-Revert-drm-amdkfd-add-debug-notification.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3445-Revert-drm-amdkfd-add-debug-notification.patch
new file mode 100644
index 00000000..124bb56b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3445-Revert-drm-amdkfd-add-debug-notification.patch
@@ -0,0 +1,565 @@
+From 0ffeab32aca5b181f96841ddd0a558e076d76a3c Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Wed, 14 Aug 2019 17:22:03 +0800
+Subject: [PATCH 3445/4256] Revert "drm/amdkfd: add debug notification"
+
+Change-Id: I4fc086e2f866dd8ea54eee996d8b7d2ab3d2be0e
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/Makefile           |   3 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c      |  18 --
+ drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c | 285 ------------------
+ drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h |  40 ---
+ .../gpu/drm/amd/amdkfd/kfd_int_process_v9.c   |  27 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h         |  11 -
+ include/uapi/linux/kfd_ioctl.h                |  21 +-
+ 7 files changed, 9 insertions(+), 396 deletions(-)
+ delete mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
+ delete mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile
+index aa951107a895..dad236a68a25 100644
+--- a/drivers/gpu/drm/amd/amdkfd/Makefile
++++ b/drivers/gpu/drm/amd/amdkfd/Makefile
+@@ -59,8 +59,7 @@ AMDKFD_FILES	:= $(AMDKFD_PATH)/kfd_module.o \
+ 		$(AMDKFD_PATH)/kfd_rdma.o \
+ 		$(AMDKFD_PATH)/kfd_peerdirect.o \
+ 		$(AMDKFD_PATH)/kfd_ipc.o \
+-		$(AMDKFD_PATH)/kfd_trace.o \
+-		$(AMDKFD_PATH)/kfd_debug_events.o
++		$(AMDKFD_PATH)/kfd_trace.o
+ 
+ ifneq ($(CONFIG_AMD_IOMMU_V2),)
+ AMDKFD_FILES += $(AMDKFD_PATH)/kfd_iommu.o
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index 44a9803f26f3..e96aa4eaaa66 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -42,7 +42,6 @@
+ #include "kfd_priv.h"
+ #include "kfd_device_queue_manager.h"
+ #include "kfd_dbgmgr.h"
+-#include "kfd_debug_events.h"
+ #include "kfd_ipc.h"
+ #include "kfd_trace.h"
+ 
+@@ -2737,18 +2736,6 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 			r = dev->kfd2kgd->enable_debug_trap(dev->kgd,
+ 					pdd->trap_debug_wave_launch_mode,
+ 					dev->vm_info.last_vmid_kfd);
+-			if (r)
+-				break;
+-
+-			r = kfd_dbg_ev_enable(pdd);
+-			if (r >= 0) {
+-				args->data3 = r;
+-				r = 0;
+-			} else {
+-				pdd->debug_trap_enabled = false;
+-				dev->kfd2kgd->disable_debug_trap(dev->kgd);
+-			}
+-
+ 			break;
+ 		default:
+ 			pr_err("Invalid trap enable option: %i\n",
+@@ -2796,11 +2783,6 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 		if (r)
+ 			goto unlock_out;
+ 		break;
+-	case KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT:
+-		r = kfd_dbg_ev_query_debug_event(pdd, &args->data1,
+-						 args->data2,
+-						 &args->data3);
+-		break;
+ 	default:
+ 		pr_err("Invalid option: %i\n", debug_trap_action);
+ 		r = -EINVAL;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
+deleted file mode 100644
+index 210cccdeed81..000000000000
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
++++ /dev/null
+@@ -1,285 +0,0 @@
+-/*
+- * Copyright 2019 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included in
+- * all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+- */
+-
+-#include <linux/kfifo.h>
+-#include <linux/poll.h>
+-#include <linux/wait.h>
+-#include <linux/anon_inodes.h>
+-#include <uapi/linux/kfd_ioctl.h>
+-#include "kfd_debug_events.h"
+-#include "kfd_priv.h"
+-#include "kfd_topology.h"
+-
+-/* poll and read functions */
+-static __poll_t kfd_dbg_ev_poll(struct file *, struct poll_table_struct *);
+-static ssize_t kfd_dbg_ev_read(struct file *, char __user *, size_t, loff_t *);
+-static int kfd_dbg_ev_release(struct inode *, struct file *);
+-
+-/* fd name */
+-static const char kfd_dbg_name[] = "kfd_debug";
+-
+-/* fops for polling, read and ioctl */
+-static const struct file_operations kfd_dbg_ev_fops = {
+-	.owner = THIS_MODULE,
+-	.poll = kfd_dbg_ev_poll,
+-	.read = kfd_dbg_ev_read,
+-	.release = kfd_dbg_ev_release
+-};
+-
+-/* poll on wait queue of file */
+-static __poll_t kfd_dbg_ev_poll(struct file *filep,
+-				struct poll_table_struct *wait)
+-{
+-
+-	struct kfd_debug_process_device *dpd = filep->private_data;
+-
+-	__poll_t mask = 0;
+-
+-	/* pending event have been queue'd via interrupt */
+-	poll_wait(filep, &dpd->wait_queue, wait);
+-	mask |= !kfifo_is_empty(&dpd->fifo) ? POLLIN | POLLRDNORM : mask;
+-
+-	return mask;
+-}
+-
+-/* read based on wait entries and return types found */
+-static ssize_t kfd_dbg_ev_read(struct file *filep, char __user *user,
+-			       size_t size, loff_t *offset)
+-{
+-	int ret, copied;
+-	struct kfd_debug_process_device *dpd = filep->private_data;
+-
+-	ret = kfifo_to_user(&dpd->fifo, user, size, &copied);
+-
+-	if (ret) {
+-		pr_debug("KFD DEBUG EVENT: Failed to read poll fd (%i)\n", ret);
+-		return ret;
+-	}
+-
+-	return copied;
+-}
+-
+-static int kfd_dbg_ev_release(struct inode *inode, struct file *filep)
+-{
+-	struct kfd_debug_process_device *dpd = filep->private_data;
+-
+-	kfifo_free(&dpd->fifo);
+-
+-	return 0;
+-}
+-
+-/* query pending events and return queue_id, event_type and is_suspended */
+-#define KFD_DBG_EV_SET_SUSPEND_STATE(x, s)			\
+-	((x) = (s) ? (x) | KFD_DBG_EV_STATUS_SUSPENDED :	\
+-		(x) & ~KFD_DBG_EV_STATUS_SUSPENDED)
+-
+-#define KFD_DBG_EV_SET_EVENT_TYPE(x, e)				\
+-	((x) = ((x) & ~(KFD_DBG_EV_STATUS_TRAP			\
+-		| KFD_DBG_EV_STATUS_VMFAULT)) | (e))
+-
+-int kfd_dbg_ev_query_debug_event(struct kfd_process_device *pdd,
+-		      unsigned int *queue_id,
+-		      unsigned int flags,
+-		      uint32_t *event_status)
+-{
+-	struct process_queue_manager *pqm;
+-	struct process_queue_node *pqn;
+-	struct queue *q;
+-	int ret = 0;
+-
+-	if (!pdd || !pdd->process)
+-		return -ENODATA;
+-
+-	/* lock process events to update event queues */
+-	mutex_lock(&pdd->process->event_mutex);
+-	pqm = &pdd->process->pqm;
+-
+-	if (*queue_id != KFD_INVALID_QUEUEID) {
+-		q = pqm_get_user_queue(pqm, *queue_id);
+-
+-		if (!q) {
+-			ret = -EINVAL;
+-			goto out;
+-		}
+-
+-		KFD_DBG_EV_SET_EVENT_TYPE(*event_status,
+-					  q->properties.debug_event_type);
+-		KFD_DBG_EV_SET_SUSPEND_STATE(*event_status,
+-					  q->properties.is_suspended);
+-		if (flags & KFD_DBG_EV_FLAG_CLEAR_STATUS)
+-			q->properties.debug_event_type = 0;
+-		goto out;
+-
+-	} else {
+-		list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
+-			if (pqn->q &&
+-				 (pqn->q->properties.debug_event_type
+-					== KFD_DBG_EV_STATUS_TRAP
+-				|| pqn->q->properties.debug_event_type
+-					== KFD_DBG_EV_STATUS_VMFAULT)) {
+-				*queue_id = pqn->q->properties.queue_id;
+-				KFD_DBG_EV_SET_EVENT_TYPE(*event_status,
+-					pqn->q->properties.debug_event_type);
+-				KFD_DBG_EV_SET_SUSPEND_STATE(*event_status,
+-					pqn->q->properties.is_suspended);
+-				if (flags & KFD_DBG_EV_FLAG_CLEAR_STATUS)
+-					pqn->q->properties.debug_event_type
+-									= 0;
+-				goto out;
+-			}
+-		}
+-		ret = -EAGAIN;
+-	}
+-
+-out:
+-	mutex_unlock(&pdd->process->event_mutex);
+-	return ret;
+-}
+-
+-/* create event queue struct associated with process per device */
+-static int kfd_create_event_queue(struct kfd_process_device *pdd)
+-{
+-	struct process_queue_manager *pqm;
+-	struct process_queue_node *pqn;
+-	struct kfd_topology_device *tdev;
+-	int ret;
+-
+-	if (!pdd || !pdd->process)
+-		return -ESRCH;
+-
+-	tdev = kfd_topology_device_by_id(pdd->dev->id);
+-
+-	pdd->dpd.max_debug_events = tdev->node_props.simd_count
+-				* tdev->node_props.max_waves_per_simd;
+-
+-	ret = kfifo_alloc(&pdd->dpd.fifo, pdd->dpd.max_debug_events,
+-			  GFP_KERNEL);
+-
+-	if (ret)
+-		return ret;
+-
+-	init_waitqueue_head(&pdd->dpd.wait_queue);
+-
+-	pqm = &pdd->process->pqm;
+-
+-	/* to reset queue pending status - TBD need init in queue creation */
+-	list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
+-		if (pqn->q->device == pdd->dev)
+-			pqn->q->properties.debug_event_type = 0;
+-	}
+-
+-	return ret;
+-}
+-
+-/* update process device, write to kfifo and wake up wait queue  */
+-static void kfd_dbg_ev_update_event_queue(struct kfd_process_device *pdd,
+-					  unsigned int doorbell_id,
+-					  bool is_vmfault)
+-{
+-	struct process_queue_manager *pqm;
+-	struct process_queue_node *pqn;
+-	char fifo_output;
+-
+-	if (!pdd->debug_trap_enabled)
+-		return;
+-
+-	pqm = &pdd->process->pqm;
+-
+-	/* iterate through each queue */
+-	list_for_each_entry(pqn, &pqm->queues,
+-				process_queue_list) {
+-
+-		if (!pqn->q)
+-			continue;
+-
+-		if (pqn->q->device != pdd->dev)
+-			continue;
+-
+-		if (pqn->q->doorbell_id != doorbell_id && !is_vmfault)
+-			continue;
+-
+-		pqn->q->properties.debug_event_type |=
+-			is_vmfault ? KFD_DBG_EV_STATUS_VMFAULT :
+-					KFD_DBG_EV_STATUS_TRAP;
+-
+-		fifo_output = is_vmfault ? 'v' : 't';
+-
+-		kfifo_in(&pdd->dpd.fifo, &fifo_output, 1);
+-
+-		wake_up_all(&pdd->dpd.wait_queue);
+-
+-		if (!is_vmfault)
+-			break;
+-	}
+-}
+-
+-/* set pending event queue entry from ring entry  */
+-void kfd_set_dbg_ev_from_interrupt(struct kfd_dev *dev,
+-				   unsigned int pasid,
+-				   uint32_t doorbell_id,
+-				   bool is_vmfault)
+-{
+-	struct kfd_process *p;
+-	struct kfd_process_device *pdd;
+-
+-	p = kfd_lookup_process_by_pasid(pasid);
+-
+-	if (!p)
+-		return;
+-
+-	pdd = kfd_get_process_device_data(dev, p);
+-
+-	if (!pdd) {
+-		kfd_unref_process(p);
+-		return;
+-	}
+-
+-	mutex_lock(&p->event_mutex);
+-
+-	kfd_dbg_ev_update_event_queue(pdd, doorbell_id, is_vmfault);
+-
+-	mutex_unlock(&p->event_mutex);
+-
+-	kfd_unref_process(p);
+-}
+-
+-/* enable debug and return file pointer struct */
+-int kfd_dbg_ev_enable(struct kfd_process_device *pdd)
+-{
+-	int ret;
+-
+-	if (!pdd || !pdd->process)
+-		return -ESRCH;
+-
+-	mutex_lock(&pdd->process->event_mutex);
+-
+-	ret = kfd_create_event_queue(pdd);
+-
+-	mutex_unlock(&pdd->process->event_mutex);
+-
+-	if (ret)
+-		return ret;
+-
+-	return anon_inode_getfd(kfd_dbg_name, &kfd_dbg_ev_fops,
+-				(void *)&pdd->dpd, 0);
+-}
+-
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h
+deleted file mode 100644
+index 5b035a4321c6..000000000000
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h
++++ /dev/null
+@@ -1,40 +0,0 @@
+-/*
+- * Copyright 2019 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included in
+- * all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+- */
+-
+-#ifndef KFD_DEBUG_EVENTS_H_INCLUDED
+-#define KFD_DEBUG_EVENTS_H_INCLUDED
+-
+-#include "kfd_priv.h"
+-
+-int kfd_dbg_ev_query_debug_event(struct kfd_process_device *pdd,
+-		      unsigned int *queue_id,
+-		      unsigned int flags,
+-		      uint32_t *event_status);
+-
+-void kfd_set_dbg_ev_from_interrupt(struct kfd_dev *dev,
+-				   unsigned int pasid,
+-				   uint32_t doorbell_id,
+-				   bool is_vmfault);
+-
+-int kfd_dbg_ev_enable(struct kfd_process_device *pdd);
+-
+-#endif
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
+index ab8a695c4a3c..3ef67d2e0d9f 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
+@@ -22,13 +22,9 @@
+ 
+ #include "kfd_priv.h"
+ #include "kfd_events.h"
+-#include "kfd_debug_events.h"
+ #include "soc15_int.h"
+ #include "kfd_device_queue_manager.h"
+ 
+-#define KFD_CONTEXT_ID_DEBUG_TRAP_MASK		0x000080
+-#define KFD_CONTEXT_ID_DEBUG_DOORBELL_MASK	0x0003ff
+-
+ static bool event_interrupt_isr_v9(struct kfd_dev *dev,
+ 					const uint32_t *ih_ring_entry,
+ 					uint32_t *patched_ihre,
+@@ -92,29 +88,21 @@ static void event_interrupt_wq_v9(struct kfd_dev *dev,
+ 					const uint32_t *ih_ring_entry)
+ {
+ 	uint16_t source_id, client_id, pasid, vmid;
+-	uint32_t context_id0, context_id1;
++	uint32_t context_id;
+ 
+ 	source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry);
+ 	client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry);
+ 	pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry);
+ 	vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
+-	context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry);
+-	context_id1 = SOC15_CONTEXT_ID1_FROM_IH_ENTRY(ih_ring_entry);
++	context_id = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry);
+ 
+ 	if (source_id == SOC15_INTSRC_CP_END_OF_PIPE)
+-		kfd_signal_event_interrupt(pasid, context_id0, 32);
++		kfd_signal_event_interrupt(pasid, context_id, 32);
+ 	else if (source_id == SOC15_INTSRC_SDMA_TRAP)
+-		kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28);
+-	else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) {
+-		if (context_id1 & KFD_CONTEXT_ID_DEBUG_TRAP_MASK) {
+-			kfd_set_dbg_ev_from_interrupt(dev, pasid,
+-					context_id0 &
+-					KFD_CONTEXT_ID_DEBUG_DOORBELL_MASK,
+-					false);
+-		} else
+-			kfd_signal_event_interrupt(pasid,
+-						   context_id0 & 0xffffff, 24);
+-	} else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE)
++		kfd_signal_event_interrupt(pasid, context_id & 0xfffffff, 28);
++	else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG)
++		kfd_signal_event_interrupt(pasid, context_id & 0xffffff, 24);
++	else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE)
+ 		kfd_signal_hw_exception_event(pasid);
+ 	else if (client_id == SOC15_IH_CLIENTID_VMC ||
+ 		client_id == SOC15_IH_CLIENTID_VMC1 ||
+@@ -130,7 +118,6 @@ static void event_interrupt_wq_v9(struct kfd_dev *dev,
+ 		info.prot_read  = ring_id & 0x10;
+ 		info.prot_write = ring_id & 0x20;
+ 
+-		kfd_set_dbg_ev_from_interrupt(dev, pasid, -1, true);
+ 		kfd_process_vm_fault(dev->dqm, pasid);
+ 		kfd_signal_vm_fault_event(dev, pasid, &info);
+ 	}
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index 73aa6a3330eb..40c2b0d5a954 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -510,7 +510,6 @@ struct queue_properties {
+ 	/* Relevant for CU */
+ 	uint32_t cu_mask_count; /* Must be a multiple of 32 */
+ 	uint32_t *cu_mask;
+-	unsigned int debug_event_type;
+ };
+ 
+ #define QUEUE_IS_ACTIVE(q) ((q).queue_size > 0 &&	\
+@@ -697,13 +696,6 @@ enum kfd_pdd_bound {
+ 	PDD_BOUND_SUSPENDED,
+ };
+ 
+-struct kfd_debug_process_device {
+-	struct kfifo fifo;
+-	wait_queue_head_t wait_queue;
+-	int max_debug_events;
+-};
+-
+-
+ /* Data that is per-process-per device. */
+ struct kfd_process_device {
+ 	/*
+@@ -718,9 +710,6 @@ struct kfd_process_device {
+ 	/* The process that owns this kfd_process_device. */
+ 	struct kfd_process *process;
+ 
+-	/* per-process-per device debug event info */
+-	struct kfd_debug_process_device dpd;
+-
+ 	/* per-process-per device QCM data structure */
+ 	struct qcm_process_device qpd;
+ 
+diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
+index 617c07047d55..8c2862565444 100644
+--- a/include/uapi/linux/kfd_ioctl.h
++++ b/include/uapi/linux/kfd_ioctl.h
+@@ -187,19 +187,11 @@ struct kfd_ioctl_dbg_wave_control_args {
+ 	__u32 buf_size_in_bytes;	/*including gpu_id and buf_size */
+ };
+ 
+-/* mapping event types to API spec */
+-#define	KFD_DBG_EV_STATUS_TRAP		1
+-#define	KFD_DBG_EV_STATUS_VMFAULT	2
+-#define	KFD_DBG_EV_STATUS_SUSPENDED	4
+-#define	KFD_DBG_EV_FLAG_CLEAR_STATUS	1
+-
+-#define KFD_INVALID_QUEUEID	0xffffffff
+-
+ /* KFD_IOC_DBG_TRAP_ENABLE:
+  * ptr:   unused
+  * data1: 0=disable, 1=enable
+  * data2: queue ID (for future use)
+- * data3: return value for fd
++ * data3: unused
+  */
+ #define KFD_IOC_DBG_TRAP_ENABLE 0
+ 
+@@ -243,14 +235,6 @@ struct kfd_ioctl_dbg_wave_control_args {
+  */
+ #define KFD_IOC_DBG_TRAP_NODE_RESUME 5
+ 
+-/* KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT:
+- * ptr: unused
+- * data1: queue id (IN/OUT)
+- * data2: flags (IN)
+- * data3: suspend[2:2], event type [1:0] (OUT)
+- */
+-#define KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT 6
+-
+ struct kfd_ioctl_dbg_trap_args {
+ 	__u64 ptr;     /* to KFD -- used for pointer arguments: queue arrays */
+ 	__u32 pid;     /* to KFD */
+@@ -673,9 +657,6 @@ struct kfd_ioctl_cross_memory_copy_args {
+ #define AMDKFD_IOC_IPC_EXPORT_HANDLE		\
+ 		AMDKFD_IOWR(0x20, struct kfd_ioctl_ipc_export_handle_args)
+ 
+-#define AMDKFD_IOC_DBG_TRAP			\
+-		AMDKFD_IOWR(0x21, struct kfd_ioctl_dbg_trap_args)
+-
+ #define AMDKFD_IOC_CROSS_MEMORY_COPY		\
+ 		AMDKFD_IOWR(0x22, struct kfd_ioctl_cross_memory_copy_args)
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3446-drm-amd-powerplay-add-smu-if-version-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3446-drm-amd-powerplay-add-smu-if-version-for-navi12.patch
new file mode 100644
index 00000000..ae57fa1b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3446-drm-amd-powerplay-add-smu-if-version-for-navi12.patch
@@ -0,0 +1,41 @@
+From aed7bc97514c239275826d4e112e8bf8ca496f60 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 14 Aug 2019 15:28:02 +0800
+Subject: [PATCH 3446/4256] drm/amd/powerplay: add smu if version for navi12
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 1 +
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 3 +++
+ 2 files changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 3e571016df80..5fbf082be091 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -29,6 +29,7 @@
+ #define SMU11_DRIVER_IF_VERSION_VG20 0x13
+ #define SMU11_DRIVER_IF_VERSION_ARCT 0x08
+ #define SMU11_DRIVER_IF_VERSION_NV10 0x33
++#define SMU11_DRIVER_IF_VERSION_NV12 0x33
+ #define SMU11_DRIVER_IF_VERSION_NV14 0x33
+ 
+ /* MP Apertures */
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 3a081acdf1a8..4a51de4ff162 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -281,6 +281,9 @@ static int smu_v11_0_check_fw_version(struct smu_context *smu)
+ 	case CHIP_NAVI10:
+ 		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV10;
+ 		break;
++	case CHIP_NAVI12:
++		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV12;
++		break;
+ 	case CHIP_NAVI14:
+ 		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV14;
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3447-drm-amd-powerplay-disable-gfxoff-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3447-drm-amd-powerplay-disable-gfxoff-for-navi12.patch
new file mode 100644
index 00000000..f685190b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3447-drm-amd-powerplay-disable-gfxoff-for-navi12.patch
@@ -0,0 +1,29 @@
+From 49a2ead41c9ebf911786fd9f81c66ffcbaac455d Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Mon, 13 May 2019 17:02:12 +0800
+Subject: [PATCH 3447/4256] drm/amd/powerplay: disable gfxoff for navi12
+
+gfxoff doesn't work on navi12 yet, so disable it for now
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 066ba593af23..d644669e5d93 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -580,6 +580,7 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
+ {
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
++	case CHIP_NAVI12:
+ 		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ 		break;
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3448-Revert-drm-amd-display-Make-init_hw-and-init_pipes-g.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3448-Revert-drm-amd-display-Make-init_hw-and-init_pipes-g.patch
new file mode 100644
index 00000000..77fa18c1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3448-Revert-drm-amd-display-Make-init_hw-and-init_pipes-g.patch
@@ -0,0 +1,1074 @@
+From 5f2256ec065b65c4b5c0efdd2e10ebd27313e513 Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Thu, 15 Aug 2019 18:41:15 +0800
+Subject: [PATCH 3448/4256] Revert "drm/amd/display: Make init_hw and
+ init_pipes generic for seamless boot"
+
+Change-Id: I43c34c78601b73a3a52131c2d7bf34facdf0b4d2
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+---
+ .../display/dc/dce110/dce110_hw_sequencer.c   |  12 +-
+ .../display/dc/dce110/dce110_hw_sequencer.h   |   6 +-
+ .../drm/amd/display/dc/dcn10/dcn10_hubbub.c   |   4 +-
+ .../drm/amd/display/dc/dcn10/dcn10_hubbub.h   |   2 +-
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 182 +++------
+ .../drm/amd/display/dc/dcn20/dcn20_hubbub.c   |   2 +-
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 383 +++++++++++-------
+ .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h  |   4 -
+ .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  32 --
+ 9 files changed, 313 insertions(+), 314 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 5a046e5bc756..919647166bce 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -728,7 +728,7 @@ static enum bp_result link_transmitter_control(
+  * @brief
+  * eDP only.
+  */
+-void dce110_edp_wait_for_hpd_ready(
++void hwss_edp_wait_for_hpd_ready(
+ 		struct dc_link *link,
+ 		bool power_up)
+ {
+@@ -796,7 +796,7 @@ void dce110_edp_wait_for_hpd_ready(
+ 	}
+ }
+ 
+-void dce110_edp_power_control(
++void hwss_edp_power_control(
+ 		struct dc_link *link,
+ 		bool power_up)
+ {
+@@ -878,7 +878,7 @@ void dce110_edp_power_control(
+  * @brief
+  * eDP only. Control the backlight of the eDP panel
+  */
+-void dce110_edp_backlight_control(
++void hwss_edp_backlight_control(
+ 		struct dc_link *link,
+ 		bool enable)
+ {
+@@ -2755,9 +2755,9 @@ static const struct hw_sequencer_funcs dce110_funcs = {
+ 	.setup_stereo = NULL,
+ 	.set_avmute = dce110_set_avmute,
+ 	.wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
+-	.edp_backlight_control = dce110_edp_backlight_control,
+-	.edp_power_control = dce110_edp_power_control,
+-	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
++	.edp_backlight_control = hwss_edp_backlight_control,
++	.edp_power_control = hwss_edp_power_control,
++	.edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
+ 	.set_cursor_position = dce110_set_cursor_position,
+ 	.set_cursor_attribute = dce110_set_cursor_attribute
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+index 668feb0d169d..cd3e36d52a52 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+@@ -73,15 +73,15 @@ void dce110_optimize_bandwidth(
+ 
+ void dp_receiver_power_ctrl(struct dc_link *link, bool on);
+ 
+-void dce110_edp_power_control(
++void hwss_edp_power_control(
+ 		struct dc_link *link,
+ 		bool power_up);
+ 
+-void dce110_edp_backlight_control(
++void hwss_edp_backlight_control(
+ 	struct dc_link *link,
+ 	bool enable);
+ 
+-void dce110_edp_wait_for_hpd_ready(
++void hwss_edp_wait_for_hpd_ready(
+ 		struct dc_link *link,
+ 		bool power_up);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+index 90c30a21bd09..0ab391446d3d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+@@ -102,7 +102,7 @@ void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow)
+ 			DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, !allow);
+ }
+ 
+-bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
++bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
+ {
+ 	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
+ 	uint32_t enable = 0;
+@@ -943,8 +943,6 @@ static const struct hubbub_funcs hubbub1_funcs = {
+ 	.get_dcc_compression_cap = hubbub1_get_dcc_compression_cap,
+ 	.wm_read_state = hubbub1_wm_read_state,
+ 	.program_watermarks = hubbub1_program_watermarks,
+-	.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
+-	.allow_self_refresh_control = hubbub1_allow_self_refresh_control,
+ };
+ 
+ void hubbub1_construct(struct hubbub *hubbub,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+index 70e5d84fc69a..7c2559c9ae23 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+@@ -247,7 +247,7 @@ void hubbub1_program_watermarks(
+ 
+ void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow);
+ 
+-bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubub);
++bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubub);
+ 
+ void hubbub1_toggle_watermark_change_req(
+ 		struct hubbub *hubbub);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 1835157b9fad..5390f8d84b2a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -437,7 +437,7 @@ bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	return false;
+ }
+ 
+-static void dcn10_enable_power_gating_plane(
++static void enable_power_gating_plane(
+ 	struct dce_hwseq *hws,
+ 	bool enable)
+ {
+@@ -459,7 +459,7 @@ static void dcn10_enable_power_gating_plane(
+ 	REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
+ }
+ 
+-static void dcn10_disable_vga(
++static void disable_vga(
+ 	struct dce_hwseq *hws)
+ {
+ 	unsigned int in_vga1_mode = 0;
+@@ -492,7 +492,7 @@ static void dcn10_disable_vga(
+ 	REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
+ }
+ 
+-static void dcn10_dpp_pg_control(
++static void dpp_pg_control(
+ 		struct dce_hwseq *hws,
+ 		unsigned int dpp_inst,
+ 		bool power_on)
+@@ -544,7 +544,7 @@ static void dcn10_dpp_pg_control(
+ 	}
+ }
+ 
+-static void dcn10_hubp_pg_control(
++static void hubp_pg_control(
+ 		struct dce_hwseq *hws,
+ 		unsigned int hubp_inst,
+ 		bool power_on)
+@@ -604,8 +604,8 @@ static void power_on_plane(
+ 	if (REG(DC_IP_REQUEST_CNTL)) {
+ 		REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 				IP_REQUEST_EN, 1);
+-		hws->ctx->dc->hwss.dpp_pg_control(hws, plane_id, true);
+-		hws->ctx->dc->hwss.hubp_pg_control(hws, plane_id, true);
++		dpp_pg_control(hws, plane_id, true);
++		hubp_pg_control(hws, plane_id, true);
+ 		REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 				IP_REQUEST_EN, 0);
+ 		DC_LOG_DEBUG(
+@@ -626,7 +626,7 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc)
+ 	REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 			IP_REQUEST_EN, 1);
+ 
+-	dc->hwss.hubp_pg_control(hws, 0, false);
++	hubp_pg_control(hws, 0, false);
+ 	REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 			IP_REQUEST_EN, 0);
+ 
+@@ -655,7 +655,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc)
+ 	REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 			IP_REQUEST_EN, 1);
+ 
+-	dc->hwss.hubp_pg_control(hws, 0, true);
++	hubp_pg_control(hws, 0, true);
+ 	REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 			IP_REQUEST_EN, 0);
+ 
+@@ -663,23 +663,10 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc)
+ 	hws->wa_state.DEGVIDCN10_253_applied = true;
+ }
+ 
+-static void dcn10_bios_golden_init(struct dc *dc)
++static void bios_golden_init(struct dc *dc)
+ {
+ 	struct dc_bios *bp = dc->ctx->dc_bios;
+ 	int i;
+-	bool allow_self_fresh_force_enable = true;
+-
+-	if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)
+-		allow_self_fresh_force_enable =
+-				dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);
+-
+-
+-	/* WA for making DF sleep when idle after resume from S0i3.
+-	 * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
+-	 * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
+-	 * before calling command table and it changed to 1 after,
+-	 * it should be set back to 0.
+-	 */
+ 
+ 	/* initialize dcn global */
+ 	bp->funcs->enable_disp_power_gating(bp,
+@@ -690,12 +677,6 @@ static void dcn10_bios_golden_init(struct dc *dc)
+ 		bp->funcs->enable_disp_power_gating(bp,
+ 				CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
+ 	}
+-
+-	if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
+-		if (allow_self_fresh_force_enable == false &&
+-				dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub))
+-			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, true);
+-
+ }
+ 
+ static void false_optc_underflow_wa(
+@@ -990,7 +971,7 @@ void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 		dcn10_verify_allow_pstate_change_high(dc);
+ }
+ 
+-static void dcn10_plane_atomic_power_down(struct dc *dc,
++static void plane_atomic_power_down(struct dc *dc,
+ 		struct dpp *dpp,
+ 		struct hubp *hubp)
+ {
+@@ -1000,8 +981,8 @@ static void dcn10_plane_atomic_power_down(struct dc *dc,
+ 	if (REG(DC_IP_REQUEST_CNTL)) {
+ 		REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 				IP_REQUEST_EN, 1);
+-		dc->hwss.dpp_pg_control(hws, dpp->inst, false);
+-		dc->hwss.hubp_pg_control(hws, hubp->inst, false);
++		dpp_pg_control(hws, dpp->inst, false);
++		hubp_pg_control(hws, hubp->inst, false);
+ 		dpp->funcs->dpp_reset(dpp);
+ 		REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 				IP_REQUEST_EN, 0);
+@@ -1013,7 +994,7 @@ static void dcn10_plane_atomic_power_down(struct dc *dc,
+ /* disable HW used by plane.
+  * note:  cannot disable until disconnect is complete
+  */
+-static void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
++static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
+@@ -1033,7 +1014,7 @@ static void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	hubp->power_gated = true;
+ 	dc->optimized_required = false; /* We're powering off, no need to optimize */
+ 
+-	dc->hwss.plane_atomic_power_down(dc,
++	plane_atomic_power_down(dc,
+ 			pipe_ctx->plane_res.dpp,
+ 			pipe_ctx->plane_res.hubp);
+ 
+@@ -1052,7 +1033,7 @@ static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
+ 		return;
+ 
+-	dc->hwss.plane_atomic_disable(dc, pipe_ctx);
++	plane_atomic_disable(dc, pipe_ctx);
+ 
+ 	apply_DEGVIDCN10_253_wa(dc);
+ 
+@@ -1087,14 +1068,9 @@ static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
+ 		 * command table.
+ 		 */
+ 		if (tg->funcs->is_tg_enabled(tg)) {
+-			if (dc->hwss.init_blank != NULL) {
+-				dc->hwss.init_blank(dc, tg);
+-				tg->funcs->lock(tg);
+-			} else {
+-				tg->funcs->lock(tg);
+-				tg->funcs->set_blank(tg, true);
+-				hwss_wait_for_blank_complete(tg);
+-			}
++			tg->funcs->lock(tg);
++			tg->funcs->set_blank(tg, true);
++			hwss_wait_for_blank_complete(tg);
+ 		}
+ 	}
+ 
+@@ -1145,12 +1121,12 @@ static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
+ 		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
+ 		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
+ 
+-		dc->hwss.plane_atomic_disconnect(dc, pipe_ctx);
++		hwss1_plane_atomic_disconnect(dc, pipe_ctx);
+ 
+ 		if (tg->funcs->is_tg_enabled(tg))
+ 			tg->funcs->unlock(tg);
+ 
+-		dc->hwss.disable_plane(dc, pipe_ctx);
++		dcn10_disable_plane(dc, pipe_ctx);
+ 
+ 		pipe_ctx->stream_res.tg = NULL;
+ 		pipe_ctx->plane_res.hubp = NULL;
+@@ -1166,17 +1142,8 @@ static void dcn10_init_hw(struct dc *dc)
+ 	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 	struct dce_hwseq *hws = dc->hwseq;
+ 	struct dc_bios *dcb = dc->ctx->dc_bios;
+-	struct resource_pool *res_pool = dc->res_pool;
+-
+-	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
+-		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
+-
+-	// Initialize the dccg
+-	if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)
+-		dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);
+ 
+ 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+-
+ 		REG_WRITE(REFCLK_CNTL, 0);
+ 		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
+ 		REG_WRITE(DIO_MEM_PWR_CTRL, 0);
+@@ -1190,39 +1157,30 @@ static void dcn10_init_hw(struct dc *dc)
+ 			REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
+ 		}
+ 
+-		//Enable ability to power gate / don't force power on permanently
+-		dc->hwss.enable_power_gating_plane(hws, true);
++		enable_power_gating_plane(dc->hwseq, true);
+ 
++		/* end of FPGA. Below if real ASIC */
+ 		return;
+ 	}
+ 
+ 	if (!dcb->funcs->is_accelerated_mode(dcb)) {
+-		dc->hwss.bios_golden_init(dc);
+-		if (dc->ctx->dc_bios->fw_info_valid) {
+-			res_pool->ref_clocks.xtalin_clock_inKhz =
+-					dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
+-
+-			if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+-				if (res_pool->dccg && res_pool->hubbub) {
+-
+-					(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+-							dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
+-							&res_pool->ref_clocks.dccg_ref_clock_inKhz);
+-
+-					(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+-							res_pool->ref_clocks.dccg_ref_clock_inKhz,
+-							&res_pool->ref_clocks.dchub_ref_clock_inKhz);
+-				} else {
+-					// Not all ASICs have DCCG sw component
+-					res_pool->ref_clocks.dccg_ref_clock_inKhz =
+-							res_pool->ref_clocks.xtalin_clock_inKhz;
+-					res_pool->ref_clocks.dchub_ref_clock_inKhz =
+-							res_pool->ref_clocks.xtalin_clock_inKhz;
+-				}
+-			}
+-		} else
+-			ASSERT_CRITICAL(false);
+-		dc->hwss.disable_vga(dc->hwseq);
++		bool allow_self_fresh_force_enable =
++			hububu1_is_allow_self_refresh_enabled(
++						dc->res_pool->hubbub);
++
++		bios_golden_init(dc);
++
++		/* WA for making DF sleep when idle after resume from S0i3.
++		 * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
++		 * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
++		 * before calling command table and it changed to 1 after,
++		 * it should be set back to 0.
++		 */
++		if (allow_self_fresh_force_enable == false &&
++				hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub))
++			hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, true);
++
++		disable_vga(dc->hwseq);
+ 	}
+ 
+ 	for (i = 0; i < dc->link_count; i++) {
+@@ -1240,13 +1198,6 @@ static void dcn10_init_hw(struct dc *dc)
+ 			link->link_status.link_active = true;
+ 	}
+ 
+-	/* Power gate DSCs */
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
+-		if (dc->hwss.dsc_pg_control != NULL)
+-			dc->hwss.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
+-#endif
+-
+ 	/* If taking control over from VBIOS, we may want to optimize our first
+ 	 * mode set, so we need to skip powering down pipes until we know which
+ 	 * pipes we want to use.
+@@ -1255,21 +1206,10 @@ static void dcn10_init_hw(struct dc *dc)
+ 	 */
+ 	if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
+ 		dc->hwss.init_pipes(dc, dc->current_state);
+-		for (i = 0; i < res_pool->pipe_count; i++) {
+-			struct hubp *hubp = res_pool->hubps[i];
+-			struct dpp *dpp = res_pool->dpps[i];
+-
+-			hubp->funcs->hubp_init(hubp);
+-			res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
+-			dc->hwss.plane_atomic_power_down(dc, dpp, hubp);
+-		}
+-
+-		apply_DEGVIDCN10_253_wa(dc);
+ 	}
+ 
+-
+-	for (i = 0; i < res_pool->audio_count; i++) {
+-		struct audio *audio = res_pool->audios[i];
++	for (i = 0; i < dc->res_pool->audio_count; i++) {
++		struct audio *audio = dc->res_pool->audios[i];
+ 
+ 		audio->funcs->hw_init(audio);
+ 	}
+@@ -1297,7 +1237,7 @@ static void dcn10_init_hw(struct dc *dc)
+ 		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
+ 	}
+ 
+-	dc->hwss.enable_power_gating_plane(dc->hwseq, true);
++	enable_power_gating_plane(dc->hwseq, true);
+ }
+ 
+ static void dcn10_reset_hw_ctx_wrap(
+@@ -1885,7 +1825,7 @@ static void dcn10_enable_plane(
+ 	}
+ }
+ 
+-static void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)
++static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
+ {
+ 	int i = 0;
+ 	struct dpp_grph_csc_adjustment adjust;
+@@ -2363,7 +2303,7 @@ void update_dchubp_dpp(
+ 
+ 	if (plane_state->update_flags.bits.full_update) {
+ 		/*gamut remap*/
+-		dc->hwss.program_gamut_remap(pipe_ctx);
++		program_gamut_remap(pipe_ctx);
+ 
+ 		dc->hwss.program_output_csc(dc,
+ 				pipe_ctx,
+@@ -2600,7 +2540,7 @@ static void dcn10_apply_ctx_for_surface(
+ 			if (old_pipe_ctx->stream_res.tg == tg &&
+ 			    old_pipe_ctx->plane_res.hubp &&
+ 			    old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID)
+-				dc->hwss.disable_plane(dc, old_pipe_ctx);
++				dcn10_disable_plane(dc, old_pipe_ctx);
+ 		}
+ 
+ 		if ((!pipe_ctx->plane_state ||
+@@ -2648,7 +2588,7 @@ static void dcn10_apply_ctx_for_surface(
+ 
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++)
+ 		if (removed_pipe[i])
+-			dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
++			dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
+ 
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++)
+ 		if (removed_pipe[i]) {
+@@ -2740,7 +2680,7 @@ static void dcn10_optimize_bandwidth(
+ 		dcn10_verify_allow_pstate_change_high(dc);
+ }
+ 
+-static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
++static void set_drr(struct pipe_ctx **pipe_ctx,
+ 		int num_pipes, int vmin, int vmax)
+ {
+ 	int i = 0;
+@@ -2765,7 +2705,7 @@ static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
+ 	}
+ }
+ 
+-static void dcn10_get_position(struct pipe_ctx **pipe_ctx,
++static void get_position(struct pipe_ctx **pipe_ctx,
+ 		int num_pipes,
+ 		struct crtc_position *position)
+ {
+@@ -2777,7 +2717,7 @@ static void dcn10_get_position(struct pipe_ctx **pipe_ctx,
+ 		pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
+ }
+ 
+-static void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
++static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
+ 		int num_pipes, const struct dc_static_screen_events *events)
+ {
+ 	unsigned int i;
+@@ -3264,7 +3204,7 @@ static void dcn10_get_clock(struct dc *dc,
+ }
+ 
+ static const struct hw_sequencer_funcs dcn10_funcs = {
+-	.program_gamut_remap = dcn10_program_gamut_remap,
++	.program_gamut_remap = program_gamut_remap,
+ 	.init_hw = dcn10_init_hw,
+ 	.init_pipes = dcn10_init_pipes,
+ 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+@@ -3297,18 +3237,18 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
+ 	.optimize_bandwidth = dcn10_optimize_bandwidth,
+ 	.reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
+ 	.enable_stream_timing = dcn10_enable_stream_timing,
+-	.set_drr = dcn10_set_drr,
+-	.get_position = dcn10_get_position,
+-	.set_static_screen_control = dcn10_set_static_screen_control,
++	.set_drr = set_drr,
++	.get_position = get_position,
++	.set_static_screen_control = set_static_screen_control,
+ 	.setup_stereo = dcn10_setup_stereo,
+ 	.set_avmute = dce110_set_avmute,
+ 	.log_hw_state = dcn10_log_hw_state,
+ 	.get_hw_state = dcn10_get_hw_state,
+ 	.clear_status_bits = dcn10_clear_status_bits,
+ 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+-	.edp_backlight_control = dce110_edp_backlight_control,
+-	.edp_power_control = dce110_edp_power_control,
+-	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
++	.edp_backlight_control = hwss_edp_backlight_control,
++	.edp_power_control = hwss_edp_power_control,
++	.edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
+ 	.set_cursor_position = dcn10_set_cursor_position,
+ 	.set_cursor_attribute = dcn10_set_cursor_attribute,
+ 	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
+@@ -3318,16 +3258,6 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
+ 	.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
+ 	.set_clock = dcn10_set_clock,
+ 	.get_clock = dcn10_get_clock,
+-	.did_underflow_occur = dcn10_did_underflow_occur,
+-	.init_blank = NULL,
+-	.disable_vga = dcn10_disable_vga,
+-	.bios_golden_init = dcn10_bios_golden_init,
+-	.plane_atomic_disable = dcn10_plane_atomic_disable,
+-	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
+-	.enable_power_gating_plane = dcn10_enable_power_gating_plane,
+-	.dpp_pg_control = dcn10_dpp_pg_control,
+-	.hubp_pg_control = dcn10_hubp_pg_control,
+-	.dsc_pg_control = NULL,
+ };
+ 
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+index f13e039f8ef4..2b7859dfc089 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+@@ -595,7 +595,7 @@ static const struct hubbub_funcs hubbub2_funcs = {
+ 	.get_dcc_compression_cap = hubbub2_get_dcc_compression_cap,
+ 	.wm_read_state = hubbub2_wm_read_state,
+ 	.get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
+-	.program_watermarks = hubbub2_program_watermarks
++	.program_watermarks = hubbub2_program_watermarks,
+ };
+ 
+ void hubbub2_construct(struct dcn20_hubbub *hubbub,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index c4fced4103bf..bc9da43881cf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -64,7 +64,23 @@
+ #define FN(reg_name, field_name) \
+ 	hws->shifts->field_name, hws->masks->field_name
+ 
+-static void dcn20_enable_power_gating_plane(
++static void bios_golden_init(struct dc *dc)
++{
++	struct dc_bios *bp = dc->ctx->dc_bios;
++	int i;
++
++	/* initialize dcn global */
++	bp->funcs->enable_disp_power_gating(bp,
++			CONTROLLER_ID_D0, ASIC_PIPE_INIT);
++
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
++		/* initialize dcn per pipe */
++		bp->funcs->enable_disp_power_gating(bp,
++				CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
++	}
++}
++
++static void enable_power_gating_plane(
+ 	struct dce_hwseq *hws,
+ 	bool enable)
+ {
+@@ -167,7 +183,7 @@ void dcn20_display_init(struct dc *dc)
+ 	REG_WRITE(AZALIA_CONTROLLER_CLOCK_GATING, 0x1);
+ }
+ 
+-void dcn20_disable_vga(
++static void disable_vga(
+ 	struct dce_hwseq *hws)
+ {
+ 	REG_WRITE(D1VGA_CONTROL, 0);
+@@ -470,6 +486,29 @@ static void dcn20_hubp_pg_control(
+ }
+ 
+ 
++
++static void dcn20_plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx)
++{
++	struct dce_hwseq *hws = dc->hwseq;
++	struct dpp *dpp = pipe_ctx->plane_res.dpp;
++
++	DC_LOGGER_INIT(dc->ctx->logger);
++
++	if (REG(DC_IP_REQUEST_CNTL)) {
++		REG_SET(DC_IP_REQUEST_CNTL, 0,
++				IP_REQUEST_EN, 1);
++		dcn20_dpp_pg_control(hws, dpp->inst, false);
++		dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false);
++		dpp->funcs->dpp_reset(dpp);
++		REG_SET(DC_IP_REQUEST_CNTL, 0,
++				IP_REQUEST_EN, 0);
++		DC_LOG_DEBUG(
++				"Power gated front end %d\n", pipe_ctx->pipe_idx);
++	}
++}
++
++
++
+ /* disable HW used by plane.
+  * note:  cannot disable until disconnect is complete
+  */
+@@ -495,9 +534,7 @@ static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	hubp->power_gated = true;
+ 	dc->optimized_required = false; /* We're powering off, no need to optimize */
+ 
+-	dc->hwss.plane_atomic_power_down(dc,
+-			pipe_ctx->plane_res.dpp,
+-			pipe_ctx->plane_res.hubp);
++	dcn20_plane_atomic_power_down(dc, pipe_ctx);
+ 
+ 	pipe_ctx->stream = NULL;
+ 	memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
+@@ -521,6 +558,204 @@ void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 					pipe_ctx->pipe_idx);
+ }
+ 
++static void dcn20_init_hw(struct dc *dc)
++{
++	int i, j;
++	struct abm *abm = dc->res_pool->abm;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
++	struct dce_hwseq *hws = dc->hwseq;
++	struct dc_bios *dcb = dc->ctx->dc_bios;
++	struct resource_pool *res_pool = dc->res_pool;
++	struct dc_state  *context = dc->current_state;
++
++	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
++		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
++
++	// Initialize the dccg
++	if (res_pool->dccg->funcs->dccg_init)
++		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
++
++	//Enable ability to power gate / don't force power on permanently
++	enable_power_gating_plane(dc->hwseq, true);
++
++	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
++		REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
++		REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
++
++		dcn20_dccg_init(hws);
++
++		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
++		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
++		REG_WRITE(REFCLK_CNTL, 0);
++	} else {
++		if (!dcb->funcs->is_accelerated_mode(dcb)) {
++			bios_golden_init(dc);
++			if (dc->ctx->dc_bios->fw_info_valid) {
++				res_pool->ref_clocks.xtalin_clock_inKhz =
++						dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
++
++				if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
++					if (res_pool->dccg && res_pool->hubbub) {
++
++						(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
++								dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
++								&res_pool->ref_clocks.dccg_ref_clock_inKhz);
++
++						(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
++								res_pool->ref_clocks.dccg_ref_clock_inKhz,
++								&res_pool->ref_clocks.dchub_ref_clock_inKhz);
++					} else {
++						// Not all ASICs have DCCG sw component
++						res_pool->ref_clocks.dccg_ref_clock_inKhz =
++								res_pool->ref_clocks.xtalin_clock_inKhz;
++						res_pool->ref_clocks.dchub_ref_clock_inKhz =
++								res_pool->ref_clocks.xtalin_clock_inKhz;
++					}
++				}
++			} else
++				ASSERT_CRITICAL(false);
++			disable_vga(dc->hwseq);
++		}
++
++		for (i = 0; i < dc->link_count; i++) {
++			/* Power up AND update implementation according to the
++			 * required signal (which may be different from the
++			 * default signal on connector).
++			 */
++			struct dc_link *link = dc->links[i];
++
++			link->link_enc->funcs->hw_init(link->link_enc);
++		}
++	}
++
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	/* Power gate DSCs */
++	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
++		dcn20_dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
++#endif
++
++	/* Blank pixel data with OPP DPG */
++	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
++		struct timing_generator *tg = dc->res_pool->timing_generators[i];
++
++		if (tg->funcs->is_tg_enabled(tg)) {
++			dcn20_init_blank(dc, tg);
++		}
++	}
++
++	for (i = 0; i < res_pool->timing_generator_count; i++) {
++		struct timing_generator *tg = dc->res_pool->timing_generators[i];
++
++		if (tg->funcs->is_tg_enabled(tg))
++			tg->funcs->lock(tg);
++	}
++
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
++		struct dpp *dpp = res_pool->dpps[i];
++
++		dpp->funcs->dpp_reset(dpp);
++	}
++
++	/* Reset all MPCC muxes */
++	res_pool->mpc->funcs->mpc_init(res_pool->mpc);
++
++	/* initialize OPP mpc_tree parameter */
++	for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
++		res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
++		res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
++		for (j = 0; j < MAX_PIPES; j++)
++			res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
++	}
++
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
++		struct timing_generator *tg = dc->res_pool->timing_generators[i];
++		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
++		struct hubp *hubp = dc->res_pool->hubps[i];
++		struct dpp *dpp = dc->res_pool->dpps[i];
++
++		pipe_ctx->stream_res.tg = tg;
++		pipe_ctx->pipe_idx = i;
++
++		pipe_ctx->plane_res.hubp = hubp;
++		pipe_ctx->plane_res.dpp = dpp;
++		pipe_ctx->plane_res.mpcc_inst = dpp->inst;
++		hubp->mpcc_id = dpp->inst;
++		hubp->opp_id = OPP_ID_INVALID;
++		hubp->power_gated = false;
++		pipe_ctx->stream_res.opp = NULL;
++
++		hubp->funcs->hubp_init(hubp);
++
++		//dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
++		//dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
++		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
++		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
++		/*to do*/
++		hwss1_plane_atomic_disconnect(dc, pipe_ctx);
++	}
++
++	/* initialize DWB pointer to MCIF_WB */
++	for (i = 0; i < res_pool->res_cap->num_dwb; i++)
++		res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
++
++	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
++		struct timing_generator *tg = dc->res_pool->timing_generators[i];
++
++		if (tg->funcs->is_tg_enabled(tg))
++			tg->funcs->unlock(tg);
++	}
++
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
++		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
++
++		dc->hwss.disable_plane(dc, pipe_ctx);
++
++		pipe_ctx->stream_res.tg = NULL;
++		pipe_ctx->plane_res.hubp = NULL;
++	}
++
++	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
++		struct timing_generator *tg = dc->res_pool->timing_generators[i];
++
++		tg->funcs->tg_init(tg);
++	}
++
++	/* end of FPGA. Below if real ASIC */
++	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
++		return;
++
++
++	for (i = 0; i < res_pool->audio_count; i++) {
++		struct audio *audio = res_pool->audios[i];
++
++		audio->funcs->hw_init(audio);
++	}
++
++	if (abm != NULL) {
++		abm->funcs->init_backlight(abm);
++		abm->funcs->abm_init(abm);
++	}
++
++	if (dmcu != NULL)
++		dmcu->funcs->dmcu_init(dmcu);
++
++	if (abm != NULL && dmcu != NULL)
++		abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
++
++	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
++	REG_WRITE(DIO_MEM_PWR_CTRL, 0);
++
++	if (!dc->debug.disable_clock_gate) {
++		/* enable all DCN clock gating */
++		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
++
++		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
++
++		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
++	}
++
++}
++
+ enum dc_status dcn20_enable_stream_timing(
+ 		struct pipe_ctx *pipe_ctx,
+ 		struct dc_state *context,
+@@ -1183,7 +1418,7 @@ static void dcn20_apply_ctx_for_surface(
+ 			if (old_pipe_ctx->stream_res.tg == tg &&
+ 			    old_pipe_ctx->plane_res.hubp &&
+ 			    old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID)
+-				dc->hwss.disable_plane(dc, old_pipe_ctx);
++				dcn20_disable_plane(dc, old_pipe_ctx);
+ 		}
+ 
+ 		if ((!pipe_ctx->plane_state ||
+@@ -1943,126 +2178,14 @@ static void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
+ 						hubp->inst, mode);
+ }
+ 
+-static void dcn20_fpga_init_hw(struct dc *dc)
+-{
+-	int i, j;
+-	struct dce_hwseq *hws = dc->hwseq;
+-	struct resource_pool *res_pool = dc->res_pool;
+-	struct dc_state  *context = dc->current_state;
+-
+-	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
+-		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
+-
+-	// Initialize the dccg
+-	if (res_pool->dccg->funcs->dccg_init)
+-		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
+-
+-	//Enable ability to power gate / don't force power on permanently
+-	dc->hwss.enable_power_gating_plane(hws, true);
+-
+-	// Specific to FPGA dccg and registers
+-	REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
+-	REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
+-
+-	dcn20_dccg_init(hws);
+-
+-	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
+-	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
+-	REG_WRITE(REFCLK_CNTL, 0);
+-	//
+-
+-
+-	/* Blank pixel data with OPP DPG */
+-	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
+-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+-
+-		if (tg->funcs->is_tg_enabled(tg))
+-			dcn20_init_blank(dc, tg);
+-	}
+-
+-	for (i = 0; i < res_pool->timing_generator_count; i++) {
+-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+-
+-		if (tg->funcs->is_tg_enabled(tg))
+-			tg->funcs->lock(tg);
+-	}
+-
+-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+-		struct dpp *dpp = res_pool->dpps[i];
+-
+-		dpp->funcs->dpp_reset(dpp);
+-	}
+-
+-	/* Reset all MPCC muxes */
+-	res_pool->mpc->funcs->mpc_init(res_pool->mpc);
+-
+-	/* initialize OPP mpc_tree parameter */
+-	for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
+-		res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
+-		res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
+-		for (j = 0; j < MAX_PIPES; j++)
+-			res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
+-	}
+-
+-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+-		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+-		struct hubp *hubp = dc->res_pool->hubps[i];
+-		struct dpp *dpp = dc->res_pool->dpps[i];
+-
+-		pipe_ctx->stream_res.tg = tg;
+-		pipe_ctx->pipe_idx = i;
+-
+-		pipe_ctx->plane_res.hubp = hubp;
+-		pipe_ctx->plane_res.dpp = dpp;
+-		pipe_ctx->plane_res.mpcc_inst = dpp->inst;
+-		hubp->mpcc_id = dpp->inst;
+-		hubp->opp_id = OPP_ID_INVALID;
+-		hubp->power_gated = false;
+-		pipe_ctx->stream_res.opp = NULL;
+-
+-		hubp->funcs->hubp_init(hubp);
+-
+-		//dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
+-		//dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
+-		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
+-		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
+-		/*to do*/
+-		hwss1_plane_atomic_disconnect(dc, pipe_ctx);
+-	}
+-
+-	/* initialize DWB pointer to MCIF_WB */
+-	for (i = 0; i < res_pool->res_cap->num_dwb; i++)
+-		res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
+-
+-	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
+-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+-
+-		if (tg->funcs->is_tg_enabled(tg))
+-			tg->funcs->unlock(tg);
+-	}
+-
+-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+-		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+-
+-		dc->hwss.disable_plane(dc, pipe_ctx);
+-
+-		pipe_ctx->stream_res.tg = NULL;
+-		pipe_ctx->plane_res.hubp = NULL;
+-	}
+-
+-	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
+-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+-
+-		tg->funcs->tg_init(tg);
+-	}
+-}
+-
+ void dcn20_hw_sequencer_construct(struct dc *dc)
+ {
+ 	dcn10_hw_sequencer_construct(dc);
++	dc->hwss.init_hw = dcn20_init_hw;
++	dc->hwss.init_pipes = NULL;
+ 	dc->hwss.unblank_stream = dcn20_unblank_stream;
+ 	dc->hwss.update_plane_addr = dcn20_update_plane_addr;
++	dc->hwss.disable_plane = dcn20_disable_plane,
+ 	dc->hwss.enable_stream_timing = dcn20_enable_stream_timing;
+ 	dc->hwss.program_triplebuffer = dcn20_program_tripleBuffer;
+ 	dc->hwss.set_input_transfer_func = dcn20_set_input_transfer_func;
+@@ -2090,21 +2213,5 @@ void dcn20_hw_sequencer_construct(struct dc *dc)
+ 	dc->hwss.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap;
+ 	dc->hwss.update_mpcc = dcn20_update_mpcc;
+ 	dc->hwss.set_flip_control_gsl = dcn20_set_flip_control_gsl;
+-	dc->hwss.init_blank = dcn20_init_blank;
+-	dc->hwss.disable_plane = dcn20_disable_plane;
+-	dc->hwss.plane_atomic_disable = dcn20_plane_atomic_disable;
+-	dc->hwss.enable_power_gating_plane = dcn20_enable_power_gating_plane;
+-	dc->hwss.dpp_pg_control = dcn20_dpp_pg_control;
+-	dc->hwss.hubp_pg_control = dcn20_hubp_pg_control;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-	dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
+-#endif
+-	dc->hwss.disable_vga = dcn20_disable_vga;
+-
+-	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+-		dc->hwss.init_hw = dcn20_fpga_init_hw;
+-		dc->hwss.init_pipes = NULL;
+-	}
+-
+-
++	dc->hwss.did_underflow_occur = dcn10_did_underflow_occur;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+index c1f29b1654d9..9502478c4a1b 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+@@ -141,10 +141,6 @@ struct hubbub_funcs {
+ 			struct dcn_watermark_set *watermarks,
+ 			unsigned int refclk_mhz,
+ 			bool safe_to_lower);
+-
+-	bool (*is_allow_self_refresh_enabled)(struct hubbub *hubbub);
+-	void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow);
+-
+ };
+ 
+ struct hubbub {
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index 80de2febd7cb..28645e10f854 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -78,8 +78,6 @@ struct stream_resource;
+ struct dc_phy_addr_space_config;
+ struct dc_virtual_addr_space_config;
+ #endif
+-struct hubp;
+-struct dpp;
+ 
+ struct hw_sequencer_funcs {
+ 
+@@ -282,36 +280,6 @@ struct hw_sequencer_funcs {
+ 	void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx);
+ 	bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+ 
+-	void (*init_blank)(struct dc *dc, struct timing_generator *tg);
+-	void (*disable_vga)(struct dce_hwseq *hws);
+-	void (*bios_golden_init)(struct dc *dc);
+-	void (*plane_atomic_power_down)(struct dc *dc,
+-			struct dpp *dpp,
+-			struct hubp *hubp);
+-
+-	void (*plane_atomic_disable)(
+-			struct dc *dc, struct pipe_ctx *pipe_ctx);
+-
+-	void (*enable_power_gating_plane)(
+-		struct dce_hwseq *hws,
+-		bool enable);
+-
+-	void (*dpp_pg_control)(
+-			struct dce_hwseq *hws,
+-			unsigned int dpp_inst,
+-			bool power_on);
+-
+-	void (*hubp_pg_control)(
+-			struct dce_hwseq *hws,
+-			unsigned int hubp_inst,
+-			bool power_on);
+-
+-	void (*dsc_pg_control)(
+-			struct dce_hwseq *hws,
+-			unsigned int dsc_inst,
+-			bool power_on);
+-
+-
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
+ 	void (*program_all_writeback_pipes_in_tree)(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3449-Revert-drm-amd-display-make-firmware-info-only-load-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3449-Revert-drm-amd-display-make-firmware-info-only-load-.patch
new file mode 100644
index 00000000..6d50fd61
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3449-Revert-drm-amd-display-make-firmware-info-only-load-.patch
@@ -0,0 +1,446 @@
+From 9a506817f77080f092e0530dcaba63a428ef09e5 Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Thu, 15 Aug 2019 18:56:07 +0800
+Subject: [PATCH 3449/4256] Revert "drm/amd/display: make firmware info only
+ load once during dc_bios create"
+
+Change-Id: I0df28763c7b73a29d0adeb0fe4df9aa61d3f8642
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+---
+ .../gpu/drm/amd/display/dc/bios/bios_parser.c |  3 +-
+ .../drm/amd/display/dc/bios/bios_parser2.c    |  3 +-
+ .../display/dc/clk_mgr/dce100/dce_clk_mgr.c   | 17 ++++++----
+ .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c    |  6 ++--
+ .../gpu/drm/amd/display/dc/core/dc_resource.c |  7 ++--
+ .../gpu/drm/amd/display/dc/dc_bios_types.h    |  5 +--
+ .../drm/amd/display/dc/dce/dce_clock_source.c | 32 ++++++++++++-------
+ .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c   | 13 +++++++-
+ .../amd/display/dc/dce100/dce100_resource.c   |  4 ++-
+ .../amd/display/dc/dce110/dce110_resource.c   |  4 ++-
+ .../drm/amd/display/dc/dce80/dce80_resource.c | 12 +++++--
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  9 +++---
+ 12 files changed, 79 insertions(+), 36 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+index 207f6084525c..a4c97d32e751 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+@@ -2794,6 +2794,8 @@ static const struct dc_vbios_funcs vbios_funcs = {
+ 
+ 	.get_device_tag = bios_parser_get_device_tag,
+ 
++	.get_firmware_info = bios_parser_get_firmware_info,
++
+ 	.get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
+ 
+ 	.get_ss_entry_number = bios_parser_get_ss_entry_number,
+@@ -2918,7 +2920,6 @@ static bool bios_parser_construct(
+ 	dal_bios_parser_init_cmd_tbl_helper(&bp->cmd_helper, dce_version);
+ 
+ 	bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
+-	bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
+ 
+ 	return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index c9f65c4df530..99f40b8a231c 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -1879,6 +1879,8 @@ static const struct dc_vbios_funcs vbios_funcs = {
+ 
+ 	.get_device_tag = bios_parser_get_device_tag,
+ 
++	.get_firmware_info = bios_parser_get_firmware_info,
++
+ 	.get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
+ 
+ 	.get_ss_entry_number = bios_parser_get_ss_entry_number,
+@@ -1994,7 +1996,6 @@ static bool bios_parser_construct(
+ 	dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
+ 
+ 	bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
+-	bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
+ 
+ 	return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+index 7634982a6bb0..6a0dd78ab65a 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+@@ -270,12 +270,18 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)
+ {
+ 	struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;
+ 	struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
++	struct integrated_info info = { { { 0 } } };
++	struct dc_firmware_info fw_info = { { 0 } };
+ 	int i;
+ 
+ 	if (bp->integrated_info)
+-		clk_mgr_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
++		info = *bp->integrated_info;
++
++	clk_mgr_dce->dentist_vco_freq_khz = info.dentist_vco_freq;
+ 	if (clk_mgr_dce->dentist_vco_freq_khz == 0) {
+-		clk_mgr_dce->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
++		bp->funcs->get_firmware_info(bp, &fw_info);
++		clk_mgr_dce->dentist_vco_freq_khz =
++			fw_info.smu_gpu_pll_output_freq;
+ 		if (clk_mgr_dce->dentist_vco_freq_khz == 0)
+ 			clk_mgr_dce->dentist_vco_freq_khz = 3600000;
+ 	}
+@@ -308,10 +314,9 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)
+ 
+ 		/*Do not allow bad VBIOS/SBIOS to override with invalid values,
+ 		 * check for > 100MHz*/
+-		if (bp->integrated_info)
+-			if (bp->integrated_info->disp_clk_voltage[i].max_supported_clk >= 100000)
+-				clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =
+-					bp->integrated_info->disp_clk_voltage[i].max_supported_clk;
++		if (info.disp_clk_voltage[i].max_supported_clk >= 100000)
++			clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =
++				info.disp_clk_voltage[i].max_supported_clk;
+ 	}
+ 
+ 	if (!debug->disable_dfs_bypass && bp->integrated_info)
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+index d00ee9fa04e4..a12a9606788f 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+@@ -254,6 +254,7 @@ void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_
+ {
+ 	struct dc_debug_options *debug = &ctx->dc->debug;
+ 	struct dc_bios *bp = ctx->dc_bios;
++	struct dc_firmware_info fw_info = { { 0 } };
+ 
+ 	clk_mgr->base.ctx = ctx;
+ 	clk_mgr->pp_smu = pp_smu;
+@@ -269,8 +270,9 @@ void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_
+ 
+ 	if (bp->integrated_info)
+ 		clk_mgr->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
+-	if (bp->fw_info_valid && clk_mgr->dentist_vco_freq_khz == 0) {
+-		clk_mgr->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
++	if (clk_mgr->dentist_vco_freq_khz == 0) {
++		bp->funcs->get_firmware_info(bp, &fw_info);
++		clk_mgr->dentist_vco_freq_khz = fw_info.smu_gpu_pll_output_freq;
+ 		if (clk_mgr->dentist_vco_freq_khz == 0)
+ 			clk_mgr->dentist_vco_freq_khz = 3600000;
+ 	}
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index fa94dfc04dce..601020c9b03e 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -170,9 +170,12 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
+ 		break;
+ 	}
+ 	if (res_pool != NULL) {
+-		if (dc->ctx->dc_bios->fw_info_valid) {
++		struct dc_firmware_info fw_info = { { 0 } };
++
++		if (dc->ctx->dc_bios->funcs->get_firmware_info(dc->ctx->dc_bios,
++				&fw_info) == BP_RESULT_OK) {
+ 			res_pool->ref_clocks.xtalin_clock_inKhz =
+-				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
++				fw_info.pll_info.crystal_frequency;
+ 			/* initialize with firmware data first, no all
+ 			 * ASIC have DCCG SW component. FPGA or
+ 			 * simulation need initialization of
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+index b1dd0d60d98e..78c3b300ec45 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+@@ -61,6 +61,9 @@ struct dc_vbios_funcs {
+ 		struct graphics_object_id connector_object_id,
+ 		uint32_t device_tag_index,
+ 		struct connector_device_tag_info *info);
++	enum bp_result (*get_firmware_info)(
++		struct dc_bios *bios,
++		struct dc_firmware_info *info);
+ 	enum bp_result (*get_spread_spectrum_info)(
+ 		struct dc_bios *bios,
+ 		enum as_signal_type signal,
+@@ -149,8 +152,6 @@ struct dc_bios {
+ 	struct dc_context *ctx;
+ 	const struct bios_registers *regs;
+ 	struct integrated_info *integrated_info;
+-	struct dc_firmware_info fw_info;
+-	bool fw_info_valid;
+ };
+ 
+ #endif /* DC_BIOS_TYPES_H */
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+index 990481b35682..09c4dd806525 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+@@ -1233,35 +1233,37 @@ static bool calc_pll_max_vco_construct(
+ 			struct calc_pll_clock_source_init_data *init_data)
+ {
+ 	uint32_t i;
+-	struct dc_firmware_info *fw_info = &init_data->bp->fw_info;
++	struct dc_firmware_info fw_info = { { 0 } };
+ 	if (calc_pll_cs == NULL ||
+ 			init_data == NULL ||
+ 			init_data->bp == NULL)
+ 		return false;
+ 
+-	if (init_data->bp->fw_info_valid)
++	if (init_data->bp->funcs->get_firmware_info(
++				init_data->bp,
++				&fw_info) != BP_RESULT_OK)
+ 		return false;
+ 
+ 	calc_pll_cs->ctx = init_data->ctx;
+-	calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency;
++	calc_pll_cs->ref_freq_khz = fw_info.pll_info.crystal_frequency;
+ 	calc_pll_cs->min_vco_khz =
+-			fw_info->pll_info.min_output_pxl_clk_pll_frequency;
++			fw_info.pll_info.min_output_pxl_clk_pll_frequency;
+ 	calc_pll_cs->max_vco_khz =
+-			fw_info->pll_info.max_output_pxl_clk_pll_frequency;
++			fw_info.pll_info.max_output_pxl_clk_pll_frequency;
+ 
+ 	if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0)
+ 		calc_pll_cs->max_pll_input_freq_khz =
+ 			init_data->max_override_input_pxl_clk_pll_freq_khz;
+ 	else
+ 		calc_pll_cs->max_pll_input_freq_khz =
+-			fw_info->pll_info.max_input_pxl_clk_pll_frequency;
++			fw_info.pll_info.max_input_pxl_clk_pll_frequency;
+ 
+ 	if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0)
+ 		calc_pll_cs->min_pll_input_freq_khz =
+ 			init_data->min_override_input_pxl_clk_pll_freq_khz;
+ 	else
+ 		calc_pll_cs->min_pll_input_freq_khz =
+-			fw_info->pll_info.min_input_pxl_clk_pll_frequency;
++			fw_info.pll_info.min_input_pxl_clk_pll_frequency;
+ 
+ 	calc_pll_cs->min_pix_clock_pll_post_divider =
+ 			init_data->min_pix_clk_pll_post_divider;
+@@ -1313,6 +1315,7 @@ bool dce110_clk_src_construct(
+ 	const struct dce110_clk_src_shift *cs_shift,
+ 	const struct dce110_clk_src_mask *cs_mask)
+ {
++	struct dc_firmware_info fw_info = { { 0 } };
+ 	struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi;
+ 	struct calc_pll_clock_source_init_data calc_pll_cs_init_data;
+ 
+@@ -1325,12 +1328,14 @@ bool dce110_clk_src_construct(
+ 	clk_src->cs_shift = cs_shift;
+ 	clk_src->cs_mask = cs_mask;
+ 
+-	if (!clk_src->bios->fw_info_valid) {
++	if (clk_src->bios->funcs->get_firmware_info(
++			clk_src->bios, &fw_info) != BP_RESULT_OK) {
+ 		ASSERT_CRITICAL(false);
+ 		goto unexpected_failure;
+ 	}
+ 
+-	clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
++	clk_src->ext_clk_khz =
++			fw_info.external_clock_source_frequency_for_dp;
+ 
+ 	/* structure normally used with PLL ranges from ATOMBIOS; DS on by default */
+ 	calc_pll_cs_init_data.bp = bios;
+@@ -1370,7 +1375,7 @@ bool dce110_clk_src_construct(
+ 			FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
+ 	calc_pll_cs_init_data_hdmi.ctx = ctx;
+ 
+-	clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency;
++	clk_src->ref_freq_khz = fw_info.pll_info.crystal_frequency;
+ 
+ 	if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL)
+ 		return true;
+@@ -1413,6 +1418,8 @@ bool dce112_clk_src_construct(
+ 	const struct dce110_clk_src_shift *cs_shift,
+ 	const struct dce110_clk_src_mask *cs_mask)
+ {
++	struct dc_firmware_info fw_info = { { 0 } };
++
+ 	clk_src->base.ctx = ctx;
+ 	clk_src->bios = bios;
+ 	clk_src->base.id = id;
+@@ -1422,12 +1429,13 @@ bool dce112_clk_src_construct(
+ 	clk_src->cs_shift = cs_shift;
+ 	clk_src->cs_mask = cs_mask;
+ 
+-	if (!clk_src->bios->fw_info_valid) {
++	if (clk_src->bios->funcs->get_firmware_info(
++			clk_src->bios, &fw_info) != BP_RESULT_OK) {
+ 		ASSERT_CRITICAL(false);
+ 		return false;
+ 	}
+ 
+-	clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
++	clk_src->ext_clk_khz = fw_info.external_clock_source_frequency_for_dp;
+ 
+ 	return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+index caace5229826..b2786a704708 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+@@ -96,6 +96,17 @@ static uint32_t get_hw_buffer_available_size(
+ 			dce_i2c_hw->buffer_used_bytes;
+ }
+ 
++uint32_t get_reference_clock(
++		struct dc_bios *bios)
++{
++	struct dc_firmware_info info = { { 0 } };
++
++	if (bios->funcs->get_firmware_info(bios, &info) != BP_RESULT_OK)
++		return 0;
++
++	return info.pll_info.crystal_frequency;
++}
++
+ static uint32_t get_speed(
+ 	const struct dce_i2c_hw *dce_i2c_hw)
+ {
+@@ -618,7 +629,7 @@ void dce_i2c_hw_construct(
+ {
+ 	dce_i2c_hw->ctx = ctx;
+ 	dce_i2c_hw->engine_id = engine_id;
+-	dce_i2c_hw->reference_frequency = (ctx->dc_bios->fw_info.pll_info.crystal_frequency) >> 1;
++	dce_i2c_hw->reference_frequency = get_reference_clock(ctx->dc_bios) >> 1;
+ 	dce_i2c_hw->regs = regs;
+ 	dce_i2c_hw->shifts = shifts;
+ 	dce_i2c_hw->masks = masks;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+index 9de2a0bda38a..bb199534ea3b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+@@ -907,6 +907,7 @@ static bool construct(
+ {
+ 	unsigned int i;
+ 	struct dc_context *ctx = dc->ctx;
++	struct dc_firmware_info info;
+ 	struct dc_bios *bp;
+ 
+ 	ctx->dc_bios->regs = &bios_regs;
+@@ -917,7 +918,8 @@ static bool construct(
+ 
+ 	bp = ctx->dc_bios;
+ 
+-	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
++	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
++		info.external_clock_source_frequency_for_dp != 0) {
+ 		pool->base.dp_clock_source =
+ 				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index dc1764f2f8c2..ae89721c3a99 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -1272,6 +1272,7 @@ static bool construct(
+ {
+ 	unsigned int i;
+ 	struct dc_context *ctx = dc->ctx;
++	struct dc_firmware_info info;
+ 	struct dc_bios *bp;
+ 
+ 	ctx->dc_bios->regs = &bios_regs;
+@@ -1297,7 +1298,8 @@ static bool construct(
+ 
+ 	bp = ctx->dc_bios;
+ 
+-	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
++	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
++		info.external_clock_source_frequency_for_dp != 0) {
+ 		pool->base.dp_clock_source =
+ 				dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+index 8e4effb1f439..2f224e1ae5f2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -877,6 +877,7 @@ static bool dce80_construct(
+ {
+ 	unsigned int i;
+ 	struct dc_context *ctx = dc->ctx;
++	struct dc_firmware_info info;
+ 	struct dc_bios *bp;
+ 
+ 	ctx->dc_bios->regs = &bios_regs;
+@@ -902,7 +903,8 @@ static bool dce80_construct(
+ 
+ 	bp = ctx->dc_bios;
+ 
+-	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
++	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
++		info.external_clock_source_frequency_for_dp != 0) {
+ 		pool->base.dp_clock_source =
+ 				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+ 
+@@ -1074,6 +1076,7 @@ static bool dce81_construct(
+ {
+ 	unsigned int i;
+ 	struct dc_context *ctx = dc->ctx;
++	struct dc_firmware_info info;
+ 	struct dc_bios *bp;
+ 
+ 	ctx->dc_bios->regs = &bios_regs;
+@@ -1099,7 +1102,8 @@ static bool dce81_construct(
+ 
+ 	bp = ctx->dc_bios;
+ 
+-	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
++	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
++		info.external_clock_source_frequency_for_dp != 0) {
+ 		pool->base.dp_clock_source =
+ 				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+ 
+@@ -1271,6 +1275,7 @@ static bool dce83_construct(
+ {
+ 	unsigned int i;
+ 	struct dc_context *ctx = dc->ctx;
++	struct dc_firmware_info info;
+ 	struct dc_bios *bp;
+ 
+ 	ctx->dc_bios->regs = &bios_regs;
+@@ -1296,7 +1301,8 @@ static bool dce83_construct(
+ 
+ 	bp = ctx->dc_bios;
+ 
+-	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
++	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
++		info.external_clock_source_frequency_for_dp != 0) {
+ 		pool->base.dp_clock_source =
+ 				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index bc9da43881cf..75c670d4443a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -567,6 +567,7 @@ static void dcn20_init_hw(struct dc *dc)
+ 	struct dc_bios *dcb = dc->ctx->dc_bios;
+ 	struct resource_pool *res_pool = dc->res_pool;
+ 	struct dc_state  *context = dc->current_state;
++	struct dc_firmware_info fw_info = { { 0 } };
+ 
+ 	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
+ 		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
+@@ -590,15 +591,15 @@ static void dcn20_init_hw(struct dc *dc)
+ 	} else {
+ 		if (!dcb->funcs->is_accelerated_mode(dcb)) {
+ 			bios_golden_init(dc);
+-			if (dc->ctx->dc_bios->fw_info_valid) {
+-				res_pool->ref_clocks.xtalin_clock_inKhz =
+-						dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
++			if (dc->ctx->dc_bios->funcs->get_firmware_info(
++					dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
++				res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency;
+ 
+ 				if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 					if (res_pool->dccg && res_pool->hubbub) {
+ 
+ 						(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+-								dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
++								fw_info.pll_info.crystal_frequency,
+ 								&res_pool->ref_clocks.dccg_ref_clock_inKhz);
+ 
+ 						(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3450-drm-amdgpu-Set-no-retry-as-default.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3450-drm-amdgpu-Set-no-retry-as-default.patch
new file mode 100644
index 00000000..9c14f633
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3450-drm-amdgpu-Set-no-retry-as-default.patch
@@ -0,0 +1,38 @@
+From 98fa0937670ded8ef5ea3a1b571cd6dd39f04c9f Mon Sep 17 00:00:00 2001
+From: Feifei Xu <Feifei.Xu@amd.com>
+Date: Fri, 16 Aug 2019 11:08:52 +0800
+Subject: [PATCH 3450/4256] drm/amdgpu: Set no-retry as default.
+
+This is to improve performance.
+
+Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
+Tested-by: Candice Li <candice.li@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 73d5ede4329d..0db64bcbe22e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -146,7 +146,7 @@ int amdgpu_async_gfx_ring = 1;
+ int amdgpu_mcbp = 0;
+ int amdgpu_discovery = -1;
+ int amdgpu_mes = 0;
+-int amdgpu_noretry;
++int amdgpu_noretry = 1;
+ 
+ struct amdgpu_mgpu_info mgpu_info = {
+ 	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
+@@ -623,7 +623,7 @@ MODULE_PARM_DESC(mes,
+ module_param_named(mes, amdgpu_mes, int, 0444);
+ 
+ MODULE_PARM_DESC(noretry,
+-	"Disable retry faults (0 = retry enabled (default), 1 = retry disabled)");
++	"Disable retry faults (0 = retry enabled, 1 = retry disabled (default))");
+ module_param_named(noretry, amdgpu_noretry, int, 0644);
+ 
+ #ifdef CONFIG_HSA_AMD
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3451-drm-amdgpu-Add-printing-for-RW-extracted-from-VM_L2_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3451-drm-amdgpu-Add-printing-for-RW-extracted-from-VM_L2_.patch
new file mode 100644
index 00000000..b993bc0d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3451-drm-amdgpu-Add-printing-for-RW-extracted-from-VM_L2_.patch
@@ -0,0 +1,35 @@
+From 2ec3a4a42ea7a944575102f52ab9abb7e44ac553 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Tue, 13 Aug 2019 14:04:26 -0400
+Subject: [PATCH 3451/4256] drm/amdgpu: Add printing for RW extracted from
+ VM_L2_PROTECTION_FAULT_STATUS
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+RW is also useful in most cases.
+
+Change-Id: Icf4bd65ea168e5965a6a8ebe32ce9327a2de2851
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index e42c2a4dadac..cfb3273bc07f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -387,6 +387,9 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
+ 			dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
+ 				REG_GET_FIELD(status,
+ 				VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
++			dev_err(adev->dev, "\t RW: 0x%lx\n",
++				REG_GET_FIELD(status,
++				VM_L2_PROTECTION_FAULT_STATUS, RW));
+ 
+ 		}
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3452-drm-amdgpu-Add-more-page-fault-info-printing-for-GFX.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3452-drm-amdgpu-Add-more-page-fault-info-printing-for-GFX.patch
new file mode 100644
index 00000000..fb57ff0e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3452-drm-amdgpu-Add-more-page-fault-info-printing-for-GFX.patch
@@ -0,0 +1,72 @@
+From cc05d43cd9b7e0a33c7bb2bcf745d038758caf8c Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 7 Aug 2019 16:21:09 -0400
+Subject: [PATCH 3452/4256] drm/amdgpu: Add more page fault info printing for
+ GFX10
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The printing we did for GFX9 was not propogated to GFX10 somehow, so fix
+it now.
+
+Change-Id: Ic0b8381134340b83cd69c3fe186ac7a8a97b1bca
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 33 ++++++++++++++++++++++----
+ 1 file changed, 28 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index 4e3ac1084a94..ead2d3bf8a8d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -140,17 +140,40 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
+ 	}
+ 
+ 	if (printk_ratelimit()) {
++		struct amdgpu_task_info task_info;
++
++		memset(&task_info, 0, sizeof(struct amdgpu_task_info));
++		amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
++
+ 		dev_err(adev->dev,
+-			"[%s] VMC page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n",
++			"[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
++			"for process %s pid %d thread %s pid %d)\n",
+ 			entry->vmid_src ? "mmhub" : "gfxhub",
+ 			entry->src_id, entry->ring_id, entry->vmid,
+-			entry->pasid);
+-		dev_err(adev->dev, "  at page 0x%016llx from %d\n",
++			entry->pasid, task_info.process_name, task_info.tgid,
++			task_info.task_name, task_info.pid);
++		dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
+ 			addr, entry->client_id);
+-		if (!amdgpu_sriov_vf(adev))
++		if (!amdgpu_sriov_vf(adev)) {
+ 			dev_err(adev->dev,
+-				"VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
++				"GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
+ 				status);
++			dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
++				REG_GET_FIELD(status,
++				GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
++			dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
++				REG_GET_FIELD(status,
++				GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
++			dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
++				REG_GET_FIELD(status,
++				GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
++			dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
++				REG_GET_FIELD(status,
++				GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
++			dev_err(adev->dev, "\t RW: 0x%lx\n",
++				REG_GET_FIELD(status,
++				GCVM_L2_PROTECTION_FAULT_STATUS, RW));
++		}
+ 	}
+ 
+ 	return 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3453-drm-amdgpu-Set-VM_L2_CNTL.PDE_FAULT_CLASSIFICATION-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3453-drm-amdgpu-Set-VM_L2_CNTL.PDE_FAULT_CLASSIFICATION-t.patch
new file mode 100644
index 00000000..4e6d4662
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3453-drm-amdgpu-Set-VM_L2_CNTL.PDE_FAULT_CLASSIFICATION-t.patch
@@ -0,0 +1,58 @@
+From 2c458c0a56b4cf6da708847f1c1b7e4512d2865d Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Tue, 13 Aug 2019 14:38:03 -0400
+Subject: [PATCH 3453/4256] drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION
+ to 0 for GFX10
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We have done this for pre-GFX10 asics, but GFX10 did not pick up the
+new change. The below is the commit message for that change.
+
+This is recommended by HW designers. Previously when it was set to 1,
+the PDE walk error in VM fault will be treated as
+PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected OTHER_FAULT.
+As a result, the retry control in VM_CONTEXT*_CNTL will change accordingly.
+
+The above behavior is kind of abnormal. Furthermore, the
+PDE_FAULT_CLASSIFICATION == 1 feature was targeted for very old ASICs
+and it never made it way to production. Therefore, we should set it to 0.
+
+Change-Id: If1beedb631d16b85d072aa96657a7a75fa378480
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c  | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+index 8ce5bf5feb45..8b789f750b72 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+@@ -140,7 +140,7 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
+ 	/* XXX for emulation, Refer to closed source code.*/
+ 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
+ 			    L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
+-	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
++	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
+ 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
+ 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
+ 	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+index 8ee1225d1a18..3542c203c3c8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+@@ -126,7 +126,7 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
+ 	/* XXX for emulation, Refer to closed source code.*/
+ 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
+ 			    0);
+-	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
++	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
+ 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
+ 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
+ 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3454-drm-amd-amdgpu-Update-VM-function-pointer.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3454-drm-amd-amdgpu-Update-VM-function-pointer.patch
new file mode 100644
index 00000000..99d5e263
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3454-drm-amd-amdgpu-Update-VM-function-pointer.patch
@@ -0,0 +1,36 @@
+From 20352d2851d0702e665a42985f9ab52b6c45837e Mon Sep 17 00:00:00 2001
+From: Gang Ba <gaba@amd.com>
+Date: Wed, 14 Aug 2019 11:00:19 -0400
+Subject: [PATCH 3454/4256] drm/amd/amdgpu: Update VM function pointer
+
+When VM state changed and system in large bar mode,
+make sure to use CPU update function, otherwise use
+SDMA function.
+
+Change-Id: Ibcfada560a00c9aeebfd922ae48de920e44a5866
+Signed-off-by: Gang Ba <gaba@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 3ed870f294f5..c55e7aba2f99 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -2815,6 +2815,13 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+ 	WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)),
+ 		  "CPU update of VM recommended only for large BAR system\n");
+ 
++	if (vm->use_cpu_for_update)
++		vm->update_funcs = &amdgpu_vm_cpu_funcs;
++	else
++		vm->update_funcs = &amdgpu_vm_sdma_funcs;
++	dma_fence_put(vm->last_update);
++	vm->last_update = NULL;
++
+ 	if (vm->pasid) {
+ 		unsigned long flags;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3455-drm-amdkfd-add-debug-notification.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3455-drm-amdkfd-add-debug-notification.patch
new file mode 100644
index 00000000..127d8f0f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3455-drm-amdkfd-add-debug-notification.patch
@@ -0,0 +1,577 @@
+From 44c4a363ca1dd628d741e0b08ba1bcaf1e762819 Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Thu, 9 May 2019 20:49:29 -0400
+Subject: [PATCH 3455/4256] drm/amdkfd: add debug notification
+
+User space adds trace to process.  Ring buffer entry is flagged by IH and
+process info is sent to debug event handler by kernel.  Kernel updates queue
+debug event status as pending event by doorbell id and updates fifo data
+accessible by user space after kernel sends wake signal on polling fd.  Fifo
+data records debug event history as fifo string where 't' is trap and 'v'
+is vm fault.
+
+User space can query pending events by target queue id or find the first
+queue with a pending event.  User space also has option of clearing pending
+event status on target (or first found) queue.  Kernel will report queried
+pending event type (trap or vm fault) and suspend status of queue.
+
+Change-Id: Iddfe5a342afdc9682bc66826f026be7e4776638c
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/Makefile           |   3 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c      |  18 ++
+ drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c | 285 ++++++++++++++++++
+ drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h |  40 +++
+ .../gpu/drm/amd/amdkfd/kfd_int_process_v9.c   |  27 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h         |  11 +
+ include/uapi/linux/kfd_ioctl.h                |  21 +-
+ 7 files changed, 396 insertions(+), 9 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
+ create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile
+index dad236a68a25..aa951107a895 100644
+--- a/drivers/gpu/drm/amd/amdkfd/Makefile
++++ b/drivers/gpu/drm/amd/amdkfd/Makefile
+@@ -59,7 +59,8 @@ AMDKFD_FILES	:= $(AMDKFD_PATH)/kfd_module.o \
+ 		$(AMDKFD_PATH)/kfd_rdma.o \
+ 		$(AMDKFD_PATH)/kfd_peerdirect.o \
+ 		$(AMDKFD_PATH)/kfd_ipc.o \
+-		$(AMDKFD_PATH)/kfd_trace.o
++		$(AMDKFD_PATH)/kfd_trace.o \
++		$(AMDKFD_PATH)/kfd_debug_events.o
+ 
+ ifneq ($(CONFIG_AMD_IOMMU_V2),)
+ AMDKFD_FILES += $(AMDKFD_PATH)/kfd_iommu.o
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index e96aa4eaaa66..44a9803f26f3 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -42,6 +42,7 @@
+ #include "kfd_priv.h"
+ #include "kfd_device_queue_manager.h"
+ #include "kfd_dbgmgr.h"
++#include "kfd_debug_events.h"
+ #include "kfd_ipc.h"
+ #include "kfd_trace.h"
+ 
+@@ -2736,6 +2737,18 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 			r = dev->kfd2kgd->enable_debug_trap(dev->kgd,
+ 					pdd->trap_debug_wave_launch_mode,
+ 					dev->vm_info.last_vmid_kfd);
++			if (r)
++				break;
++
++			r = kfd_dbg_ev_enable(pdd);
++			if (r >= 0) {
++				args->data3 = r;
++				r = 0;
++			} else {
++				pdd->debug_trap_enabled = false;
++				dev->kfd2kgd->disable_debug_trap(dev->kgd);
++			}
++
+ 			break;
+ 		default:
+ 			pr_err("Invalid trap enable option: %i\n",
+@@ -2783,6 +2796,11 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 		if (r)
+ 			goto unlock_out;
+ 		break;
++	case KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT:
++		r = kfd_dbg_ev_query_debug_event(pdd, &args->data1,
++						 args->data2,
++						 &args->data3);
++		break;
+ 	default:
+ 		pr_err("Invalid option: %i\n", debug_trap_action);
+ 		r = -EINVAL;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
+new file mode 100644
+index 000000000000..210cccdeed81
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
+@@ -0,0 +1,285 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include <linux/kfifo.h>
++#include <linux/poll.h>
++#include <linux/wait.h>
++#include <linux/anon_inodes.h>
++#include <uapi/linux/kfd_ioctl.h>
++#include "kfd_debug_events.h"
++#include "kfd_priv.h"
++#include "kfd_topology.h"
++
++/* poll and read functions */
++static __poll_t kfd_dbg_ev_poll(struct file *, struct poll_table_struct *);
++static ssize_t kfd_dbg_ev_read(struct file *, char __user *, size_t, loff_t *);
++static int kfd_dbg_ev_release(struct inode *, struct file *);
++
++/* fd name */
++static const char kfd_dbg_name[] = "kfd_debug";
++
++/* fops for polling, read and ioctl */
++static const struct file_operations kfd_dbg_ev_fops = {
++	.owner = THIS_MODULE,
++	.poll = kfd_dbg_ev_poll,
++	.read = kfd_dbg_ev_read,
++	.release = kfd_dbg_ev_release
++};
++
++/* poll on wait queue of file */
++static __poll_t kfd_dbg_ev_poll(struct file *filep,
++				struct poll_table_struct *wait)
++{
++
++	struct kfd_debug_process_device *dpd = filep->private_data;
++
++	__poll_t mask = 0;
++
++	/* pending event have been queue'd via interrupt */
++	poll_wait(filep, &dpd->wait_queue, wait);
++	mask |= !kfifo_is_empty(&dpd->fifo) ? POLLIN | POLLRDNORM : mask;
++
++	return mask;
++}
++
++/* read based on wait entries and return types found */
++static ssize_t kfd_dbg_ev_read(struct file *filep, char __user *user,
++			       size_t size, loff_t *offset)
++{
++	int ret, copied;
++	struct kfd_debug_process_device *dpd = filep->private_data;
++
++	ret = kfifo_to_user(&dpd->fifo, user, size, &copied);
++
++	if (ret) {
++		pr_debug("KFD DEBUG EVENT: Failed to read poll fd (%i)\n", ret);
++		return ret;
++	}
++
++	return copied;
++}
++
++static int kfd_dbg_ev_release(struct inode *inode, struct file *filep)
++{
++	struct kfd_debug_process_device *dpd = filep->private_data;
++
++	kfifo_free(&dpd->fifo);
++
++	return 0;
++}
++
++/* query pending events and return queue_id, event_type and is_suspended */
++#define KFD_DBG_EV_SET_SUSPEND_STATE(x, s)			\
++	((x) = (s) ? (x) | KFD_DBG_EV_STATUS_SUSPENDED :	\
++		(x) & ~KFD_DBG_EV_STATUS_SUSPENDED)
++
++#define KFD_DBG_EV_SET_EVENT_TYPE(x, e)				\
++	((x) = ((x) & ~(KFD_DBG_EV_STATUS_TRAP			\
++		| KFD_DBG_EV_STATUS_VMFAULT)) | (e))
++
++int kfd_dbg_ev_query_debug_event(struct kfd_process_device *pdd,
++		      unsigned int *queue_id,
++		      unsigned int flags,
++		      uint32_t *event_status)
++{
++	struct process_queue_manager *pqm;
++	struct process_queue_node *pqn;
++	struct queue *q;
++	int ret = 0;
++
++	if (!pdd || !pdd->process)
++		return -ENODATA;
++
++	/* lock process events to update event queues */
++	mutex_lock(&pdd->process->event_mutex);
++	pqm = &pdd->process->pqm;
++
++	if (*queue_id != KFD_INVALID_QUEUEID) {
++		q = pqm_get_user_queue(pqm, *queue_id);
++
++		if (!q) {
++			ret = -EINVAL;
++			goto out;
++		}
++
++		KFD_DBG_EV_SET_EVENT_TYPE(*event_status,
++					  q->properties.debug_event_type);
++		KFD_DBG_EV_SET_SUSPEND_STATE(*event_status,
++					  q->properties.is_suspended);
++		if (flags & KFD_DBG_EV_FLAG_CLEAR_STATUS)
++			q->properties.debug_event_type = 0;
++		goto out;
++
++	} else {
++		list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
++			if (pqn->q &&
++				 (pqn->q->properties.debug_event_type
++					== KFD_DBG_EV_STATUS_TRAP
++				|| pqn->q->properties.debug_event_type
++					== KFD_DBG_EV_STATUS_VMFAULT)) {
++				*queue_id = pqn->q->properties.queue_id;
++				KFD_DBG_EV_SET_EVENT_TYPE(*event_status,
++					pqn->q->properties.debug_event_type);
++				KFD_DBG_EV_SET_SUSPEND_STATE(*event_status,
++					pqn->q->properties.is_suspended);
++				if (flags & KFD_DBG_EV_FLAG_CLEAR_STATUS)
++					pqn->q->properties.debug_event_type
++									= 0;
++				goto out;
++			}
++		}
++		ret = -EAGAIN;
++	}
++
++out:
++	mutex_unlock(&pdd->process->event_mutex);
++	return ret;
++}
++
++/* create event queue struct associated with process per device */
++static int kfd_create_event_queue(struct kfd_process_device *pdd)
++{
++	struct process_queue_manager *pqm;
++	struct process_queue_node *pqn;
++	struct kfd_topology_device *tdev;
++	int ret;
++
++	if (!pdd || !pdd->process)
++		return -ESRCH;
++
++	tdev = kfd_topology_device_by_id(pdd->dev->id);
++
++	pdd->dpd.max_debug_events = tdev->node_props.simd_count
++				* tdev->node_props.max_waves_per_simd;
++
++	ret = kfifo_alloc(&pdd->dpd.fifo, pdd->dpd.max_debug_events,
++			  GFP_KERNEL);
++
++	if (ret)
++		return ret;
++
++	init_waitqueue_head(&pdd->dpd.wait_queue);
++
++	pqm = &pdd->process->pqm;
++
++	/* to reset queue pending status - TBD need init in queue creation */
++	list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
++		if (pqn->q->device == pdd->dev)
++			pqn->q->properties.debug_event_type = 0;
++	}
++
++	return ret;
++}
++
++/* update process device, write to kfifo and wake up wait queue  */
++static void kfd_dbg_ev_update_event_queue(struct kfd_process_device *pdd,
++					  unsigned int doorbell_id,
++					  bool is_vmfault)
++{
++	struct process_queue_manager *pqm;
++	struct process_queue_node *pqn;
++	char fifo_output;
++
++	if (!pdd->debug_trap_enabled)
++		return;
++
++	pqm = &pdd->process->pqm;
++
++	/* iterate through each queue */
++	list_for_each_entry(pqn, &pqm->queues,
++				process_queue_list) {
++
++		if (!pqn->q)
++			continue;
++
++		if (pqn->q->device != pdd->dev)
++			continue;
++
++		if (pqn->q->doorbell_id != doorbell_id && !is_vmfault)
++			continue;
++
++		pqn->q->properties.debug_event_type |=
++			is_vmfault ? KFD_DBG_EV_STATUS_VMFAULT :
++					KFD_DBG_EV_STATUS_TRAP;
++
++		fifo_output = is_vmfault ? 'v' : 't';
++
++		kfifo_in(&pdd->dpd.fifo, &fifo_output, 1);
++
++		wake_up_all(&pdd->dpd.wait_queue);
++
++		if (!is_vmfault)
++			break;
++	}
++}
++
++/* set pending event queue entry from ring entry  */
++void kfd_set_dbg_ev_from_interrupt(struct kfd_dev *dev,
++				   unsigned int pasid,
++				   uint32_t doorbell_id,
++				   bool is_vmfault)
++{
++	struct kfd_process *p;
++	struct kfd_process_device *pdd;
++
++	p = kfd_lookup_process_by_pasid(pasid);
++
++	if (!p)
++		return;
++
++	pdd = kfd_get_process_device_data(dev, p);
++
++	if (!pdd) {
++		kfd_unref_process(p);
++		return;
++	}
++
++	mutex_lock(&p->event_mutex);
++
++	kfd_dbg_ev_update_event_queue(pdd, doorbell_id, is_vmfault);
++
++	mutex_unlock(&p->event_mutex);
++
++	kfd_unref_process(p);
++}
++
++/* enable debug and return file pointer struct */
++int kfd_dbg_ev_enable(struct kfd_process_device *pdd)
++{
++	int ret;
++
++	if (!pdd || !pdd->process)
++		return -ESRCH;
++
++	mutex_lock(&pdd->process->event_mutex);
++
++	ret = kfd_create_event_queue(pdd);
++
++	mutex_unlock(&pdd->process->event_mutex);
++
++	if (ret)
++		return ret;
++
++	return anon_inode_getfd(kfd_dbg_name, &kfd_dbg_ev_fops,
++				(void *)&pdd->dpd, 0);
++}
++
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h
+new file mode 100644
+index 000000000000..5b035a4321c6
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h
+@@ -0,0 +1,40 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef KFD_DEBUG_EVENTS_H_INCLUDED
++#define KFD_DEBUG_EVENTS_H_INCLUDED
++
++#include "kfd_priv.h"
++
++int kfd_dbg_ev_query_debug_event(struct kfd_process_device *pdd,
++		      unsigned int *queue_id,
++		      unsigned int flags,
++		      uint32_t *event_status);
++
++void kfd_set_dbg_ev_from_interrupt(struct kfd_dev *dev,
++				   unsigned int pasid,
++				   uint32_t doorbell_id,
++				   bool is_vmfault);
++
++int kfd_dbg_ev_enable(struct kfd_process_device *pdd);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
+index 3ef67d2e0d9f..ab8a695c4a3c 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
+@@ -22,9 +22,13 @@
+ 
+ #include "kfd_priv.h"
+ #include "kfd_events.h"
++#include "kfd_debug_events.h"
+ #include "soc15_int.h"
+ #include "kfd_device_queue_manager.h"
+ 
++#define KFD_CONTEXT_ID_DEBUG_TRAP_MASK		0x000080
++#define KFD_CONTEXT_ID_DEBUG_DOORBELL_MASK	0x0003ff
++
+ static bool event_interrupt_isr_v9(struct kfd_dev *dev,
+ 					const uint32_t *ih_ring_entry,
+ 					uint32_t *patched_ihre,
+@@ -88,21 +92,29 @@ static void event_interrupt_wq_v9(struct kfd_dev *dev,
+ 					const uint32_t *ih_ring_entry)
+ {
+ 	uint16_t source_id, client_id, pasid, vmid;
+-	uint32_t context_id;
++	uint32_t context_id0, context_id1;
+ 
+ 	source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry);
+ 	client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry);
+ 	pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry);
+ 	vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
+-	context_id = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry);
++	context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry);
++	context_id1 = SOC15_CONTEXT_ID1_FROM_IH_ENTRY(ih_ring_entry);
+ 
+ 	if (source_id == SOC15_INTSRC_CP_END_OF_PIPE)
+-		kfd_signal_event_interrupt(pasid, context_id, 32);
++		kfd_signal_event_interrupt(pasid, context_id0, 32);
+ 	else if (source_id == SOC15_INTSRC_SDMA_TRAP)
+-		kfd_signal_event_interrupt(pasid, context_id & 0xfffffff, 28);
+-	else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG)
+-		kfd_signal_event_interrupt(pasid, context_id & 0xffffff, 24);
+-	else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE)
++		kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28);
++	else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) {
++		if (context_id1 & KFD_CONTEXT_ID_DEBUG_TRAP_MASK) {
++			kfd_set_dbg_ev_from_interrupt(dev, pasid,
++					context_id0 &
++					KFD_CONTEXT_ID_DEBUG_DOORBELL_MASK,
++					false);
++		} else
++			kfd_signal_event_interrupt(pasid,
++						   context_id0 & 0xffffff, 24);
++	} else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE)
+ 		kfd_signal_hw_exception_event(pasid);
+ 	else if (client_id == SOC15_IH_CLIENTID_VMC ||
+ 		client_id == SOC15_IH_CLIENTID_VMC1 ||
+@@ -118,6 +130,7 @@ static void event_interrupt_wq_v9(struct kfd_dev *dev,
+ 		info.prot_read  = ring_id & 0x10;
+ 		info.prot_write = ring_id & 0x20;
+ 
++		kfd_set_dbg_ev_from_interrupt(dev, pasid, -1, true);
+ 		kfd_process_vm_fault(dev->dqm, pasid);
+ 		kfd_signal_vm_fault_event(dev, pasid, &info);
+ 	}
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index 40c2b0d5a954..73aa6a3330eb 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -510,6 +510,7 @@ struct queue_properties {
+ 	/* Relevant for CU */
+ 	uint32_t cu_mask_count; /* Must be a multiple of 32 */
+ 	uint32_t *cu_mask;
++	unsigned int debug_event_type;
+ };
+ 
+ #define QUEUE_IS_ACTIVE(q) ((q).queue_size > 0 &&	\
+@@ -696,6 +697,13 @@ enum kfd_pdd_bound {
+ 	PDD_BOUND_SUSPENDED,
+ };
+ 
++struct kfd_debug_process_device {
++	struct kfifo fifo;
++	wait_queue_head_t wait_queue;
++	int max_debug_events;
++};
++
++
+ /* Data that is per-process-per device. */
+ struct kfd_process_device {
+ 	/*
+@@ -710,6 +718,9 @@ struct kfd_process_device {
+ 	/* The process that owns this kfd_process_device. */
+ 	struct kfd_process *process;
+ 
++	/* per-process-per device debug event info */
++	struct kfd_debug_process_device dpd;
++
+ 	/* per-process-per device QCM data structure */
+ 	struct qcm_process_device qpd;
+ 
+diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
+index 8c2862565444..617c07047d55 100644
+--- a/include/uapi/linux/kfd_ioctl.h
++++ b/include/uapi/linux/kfd_ioctl.h
+@@ -187,11 +187,19 @@ struct kfd_ioctl_dbg_wave_control_args {
+ 	__u32 buf_size_in_bytes;	/*including gpu_id and buf_size */
+ };
+ 
++/* mapping event types to API spec */
++#define	KFD_DBG_EV_STATUS_TRAP		1
++#define	KFD_DBG_EV_STATUS_VMFAULT	2
++#define	KFD_DBG_EV_STATUS_SUSPENDED	4
++#define	KFD_DBG_EV_FLAG_CLEAR_STATUS	1
++
++#define KFD_INVALID_QUEUEID	0xffffffff
++
+ /* KFD_IOC_DBG_TRAP_ENABLE:
+  * ptr:   unused
+  * data1: 0=disable, 1=enable
+  * data2: queue ID (for future use)
+- * data3: unused
++ * data3: return value for fd
+  */
+ #define KFD_IOC_DBG_TRAP_ENABLE 0
+ 
+@@ -235,6 +243,14 @@ struct kfd_ioctl_dbg_wave_control_args {
+  */
+ #define KFD_IOC_DBG_TRAP_NODE_RESUME 5
+ 
++/* KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT:
++ * ptr: unused
++ * data1: queue id (IN/OUT)
++ * data2: flags (IN)
++ * data3: suspend[2:2], event type [1:0] (OUT)
++ */
++#define KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT 6
++
+ struct kfd_ioctl_dbg_trap_args {
+ 	__u64 ptr;     /* to KFD -- used for pointer arguments: queue arrays */
+ 	__u32 pid;     /* to KFD */
+@@ -657,6 +673,9 @@ struct kfd_ioctl_cross_memory_copy_args {
+ #define AMDKFD_IOC_IPC_EXPORT_HANDLE		\
+ 		AMDKFD_IOWR(0x20, struct kfd_ioctl_ipc_export_handle_args)
+ 
++#define AMDKFD_IOC_DBG_TRAP			\
++		AMDKFD_IOWR(0x21, struct kfd_ioctl_dbg_trap_args)
++
+ #define AMDKFD_IOC_CROSS_MEMORY_COPY		\
+ 		AMDKFD_IOWR(0x22, struct kfd_ioctl_cross_memory_copy_args)
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3456-drm-amdkfd-Remove-temporary-hack-to-enable-notificat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3456-drm-amdkfd-Remove-temporary-hack-to-enable-notificat.patch
new file mode 100644
index 00000000..ae396bde
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3456-drm-amdkfd-Remove-temporary-hack-to-enable-notificat.patch
@@ -0,0 +1,111 @@
+From 0aa0298f87c949ec54c5a282e90760c68a6cbad4 Mon Sep 17 00:00:00 2001
+From: Laurent Morichetti <laurent.morichetti@amd.com>
+Date: Fri, 9 Aug 2019 15:05:59 -0700
+Subject: [PATCH 3456/4256] drm/amdkfd: Remove temporary hack to enable
+ notification to debugger
+
+The code that sends a SIGUSR2 to the debugger when events signal
+in the debugged process is no longer needed. The debugger now uses
+the new notification mechanism.
+
+Change-Id: Ic3fe4a0f6d7f08029d98126b727ad326cb546b79
+Signed-off-by: Laurent Morichetti <laurent.morichetti@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_events.c | 42 +------------------------
+ 1 file changed, 1 insertion(+), 41 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+index 88c05303a30d..b5a7b6bb4a60 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+@@ -32,7 +32,6 @@
+ #include "kfd_events.h"
+ #include "kfd_iommu.h"
+ #include <linux/device.h>
+-#include <linux/ptrace.h>
+ 
+ /*
+  * Wrapper around wait_queue_entry_t
+@@ -453,36 +452,6 @@ static void acknowledge_signal(struct kfd_process *p, struct kfd_event *ev)
+ 	page_slots(p->signal_page)[ev->event_id] = UNSIGNALED_EVENT_SLOT;
+ }
+ 
+-/* HACK: Temporary hack to enable signaling to debuggers running in a
+- * separate process. Remove this when the real signaling mechanism is
+- * implemented.
+- */
+-static void signal_event_to_debugger(struct kfd_process *p)
+-{
+-	struct kfd_process_device *pdd;
+-	struct task_struct *tracer;
+-
+-	/* Check that a debugger is attached to the process */
+-	rcu_read_lock();
+-	tracer = ptrace_parent(p->lead_thread);
+-	if (tracer)
+-		get_task_struct(tracer);
+-	rcu_read_unlock();
+-	if (!tracer)
+-		return;
+-
+-	/* Check that GPU debugging is enabled for at least one device
+-	 * for this process
+-	 */
+-	list_for_each_entry(pdd, &p->per_device_data, per_device_list)
+-		if (pdd->is_debugging_enabled) {
+-			send_sig(SIGUSR2, tracer, 0);
+-			break;
+-		}
+-
+-	put_task_struct(tracer);
+-}
+-
+ static void set_event_from_interrupt(struct kfd_process *p,
+ 					struct kfd_event *ev)
+ {
+@@ -495,7 +464,6 @@ static void set_event_from_interrupt(struct kfd_process *p,
+ void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id,
+ 				uint32_t valid_id_bits)
+ {
+-	bool debug_events_signaled = false;
+ 	struct kfd_event *ev = NULL;
+ 
+ 	/*
+@@ -515,7 +483,6 @@ void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id,
+ 							 valid_id_bits);
+ 	if (ev) {
+ 		set_event_from_interrupt(p, ev);
+-		debug_events_signaled |= (ev->type == KFD_EVENT_TYPE_DEBUG);
+ 	} else if (p->signal_page) {
+ 		/*
+ 		 * Partial ID lookup failed. Assume that the event ID
+@@ -537,11 +504,8 @@ void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id,
+ 				if (id >= KFD_SIGNAL_EVENT_LIMIT)
+ 					break;
+ 
+-				if (slots[id] != UNSIGNALED_EVENT_SLOT) {
++				if (slots[id] != UNSIGNALED_EVENT_SLOT)
+ 					set_event_from_interrupt(p, ev);
+-					debug_events_signaled |=
+-					(ev->type == KFD_EVENT_TYPE_DEBUG);
+-				}
+ 			}
+ 		} else {
+ 			/* With relatively many events, it's faster to
+@@ -552,13 +516,9 @@ void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id,
+ 				if (slots[id] != UNSIGNALED_EVENT_SLOT) {
+ 					ev = lookup_event_by_id(p, id);
+ 					set_event_from_interrupt(p, ev);
+-					debug_events_signaled |=
+-					(ev->type == KFD_EVENT_TYPE_DEBUG);
+ 				}
+ 		}
+ 	}
+-	if (debug_events_signaled)
+-		signal_event_to_debugger(p);
+ 
+ 	mutex_unlock(&p->event_mutex);
+ 	kfd_unref_process(p);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3457-drm-amd-powerplay-smu7-enforce-minimal-VBITimeout-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3457-drm-amd-powerplay-smu7-enforce-minimal-VBITimeout-v2.patch
new file mode 100644
index 00000000..4a3da714
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3457-drm-amd-powerplay-smu7-enforce-minimal-VBITimeout-v2.patch
@@ -0,0 +1,37 @@
+From f852a6de91f596e6653e8c8bc2faf84e20967107 Mon Sep 17 00:00:00 2001
+From: Ahzo <Ahzo@tutanota.com>
+Date: Mon, 5 Aug 2019 21:14:18 +0200
+Subject: [PATCH 3457/4256] drm/amd/powerplay/smu7: enforce minimal VBITimeout
+ (v2)
+
+This fixes screen corruption/flickering on 75 Hz displays.
+
+v2: make print statement debug only (Alex)
+
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102646
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Ahzo <Ahzo@tutanota.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+index 10d66e3c7a9f..b468f634ffa1 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -4067,6 +4067,11 @@ static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
+ 
+ 	data->frame_time_x2 = frame_time_in_us * 2 / 100;
+ 
++	if (data->frame_time_x2 < 280) {
++		pr_debug("%s: enforce minimal VBITimeout: %d -> 280\n", __func__, data->frame_time_x2);
++		data->frame_time_x2 = 280;
++	}
++
+ 	display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
+ 
+ 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3458-dmr-amdgpu-Fix-compile-error-with-CONFIG_DRM_AMDGPU_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3458-dmr-amdgpu-Fix-compile-error-with-CONFIG_DRM_AMDGPU_.patch
new file mode 100644
index 00000000..d69f2539
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3458-dmr-amdgpu-Fix-compile-error-with-CONFIG_DRM_AMDGPU_.patch
@@ -0,0 +1,33 @@
+From 6443dfd4eca783e2055e9ae01740e021e8fcfb03 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Wed, 14 Aug 2019 15:44:14 -0400
+Subject: [PATCH 3458/4256] dmr/amdgpu: Fix compile error with
+ CONFIG_DRM_AMDGPU_GART_DEBUGFS
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Double defintion of 'i'
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+index 9a212aa4c177..c040e9f4f5c3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+@@ -305,7 +305,7 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
+ 		     uint64_t flags)
+ {
+ #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
+-	unsigned i,t,p;
++	unsigned t,p;
+ #endif
+ 	int r;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3459-drm-amd-powerplay-Fix-meaning-of-0x1E-PPSMC_MSG.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3459-drm-amd-powerplay-Fix-meaning-of-0x1E-PPSMC_MSG.patch
new file mode 100644
index 00000000..65cdb9ef
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3459-drm-amd-powerplay-Fix-meaning-of-0x1E-PPSMC_MSG.patch
@@ -0,0 +1,28 @@
+From 215d85d704e0e6a25f4e58699070a70c21d73bb8 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Fri, 26 Jul 2019 14:03:56 -0400
+Subject: [PATCH 3459/4256] drm/amd/powerplay: Fix meaning of 0x1E PPSMC_MSG
+
+By comparing to windows it means ASIC reset.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
+index 90879e4092a3..df4677da736c 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
+@@ -59,7 +59,7 @@
+ #define PPSMC_MSG_SetDriverDramAddrLow          0x1B
+ #define PPSMC_MSG_TransferTableSmu2Dram         0x1C
+ #define PPSMC_MSG_TransferTableDram2Smu         0x1D
+-#define PPSMC_MSG_ControlGfxRM                  0x1E
++#define PPSMC_MSG_DeviceDriverReset             0x1E
+ #define PPSMC_MSG_SetGfxclkOverdriveByFreqVid   0x1F
+ #define PPSMC_MSG_SetHardMinDcefclkByFreq       0x20
+ #define PPSMC_MSG_SetHardMinSocclkByFreq        0x21
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3460-drm-amd-powerplay-add-mode2-reset-callback-for-pp_sm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3460-drm-amd-powerplay-add-mode2-reset-callback-for-pp_sm.patch
new file mode 100644
index 00000000..1db4d759
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3460-drm-amd-powerplay-add-mode2-reset-callback-for-pp_sm.patch
@@ -0,0 +1,45 @@
+From c85f9a88ca197481661880f8d3433f257ae8bdd2 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Wed, 14 Aug 2019 16:16:52 -0400
+Subject: [PATCH 3460/4256] drm/amd/powerplay: add mode2 reset callback for
+ pp_smu_mgr
+
+Also define reset modes (0, 1 and 2)
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+index 07fd64aad2ae..abeff1570277 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+@@ -189,6 +189,14 @@ struct phm_vce_clock_voltage_dependency_table {
+ 	struct phm_vce_clock_voltage_dependency_record entries[1];
+ };
+ 
++
++enum SMU_ASIC_RESET_MODE
++{
++    SMU_ASIC_RESET_MODE_0,
++    SMU_ASIC_RESET_MODE_1,
++    SMU_ASIC_RESET_MODE_2,
++};
++
+ struct pp_smumgr_func {
+ 	char *name;
+ 	int (*smu_init)(struct pp_hwmgr  *hwmgr);
+@@ -345,6 +353,7 @@ struct pp_hwmgr_func {
+ 	int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
+ 	int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
+ 	int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
++	int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
+ };
+ 
+ struct pp_table_func {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3461-drm-amd-powerpay-Implement-mode2-reset-callback-for-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3461-drm-amd-powerpay-Implement-mode2-reset-callback-for-.patch
new file mode 100644
index 00000000..0f794cac
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3461-drm-amd-powerpay-Implement-mode2-reset-callback-for-.patch
@@ -0,0 +1,43 @@
+From 75e54877124b4a594c868f0ca6f581b5489cc32f Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Wed, 14 Aug 2019 16:21:44 -0400
+Subject: [PATCH 3461/4256] drm/amd/powerpay: Implement mode2 reset callback
+ for SMU10
+
+Add implmenetion.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+index 18e780f566fa..1115761982a7 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+@@ -1311,6 +1311,12 @@ static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uin
+ 	return 0;
+ }
+ 
++static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode)
++{
++	return smum_send_msg_to_smc_with_parameter(hwmgr,
++						   PPSMC_MSG_DeviceDriverReset,
++						   mode);
++}
+ 
+ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
+ 	.backend_init = smu10_hwmgr_backend_init,
+@@ -1355,6 +1361,7 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
+ 	.set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq,
+ 	.get_power_profile_mode = smu10_get_power_profile_mode,
+ 	.set_power_profile_mode = smu10_set_power_profile_mode,
++	.asic_reset = smu10_asic_reset,
+ };
+ 
+ int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3462-drm-amd-poweplay-Add-amd_pm_funcs-callback-for-mode-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3462-drm-amd-poweplay-Add-amd_pm_funcs-callback-for-mode-.patch
new file mode 100644
index 00000000..be7b7a7c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3462-drm-amd-poweplay-Add-amd_pm_funcs-callback-for-mode-.patch
@@ -0,0 +1,68 @@
+From b9973f32e47890f20711299ef00bae5835fbac63 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Wed, 14 Aug 2019 16:26:35 -0400
+Subject: [PATCH 3462/4256] drm/amd/poweplay: Add amd_pm_funcs callback for
+ mode 2
+
+Add callback tyo call the new mode2 reset interface.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ .../gpu/drm/amd/include/kgd_pp_interface.h    |  1 +
+ drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 21 +++++++++++++++++++
+ 2 files changed, 22 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+index bba1291ae405..0de4e37fe7da 100644
+--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
++++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+@@ -310,6 +310,7 @@ struct amd_pm_funcs {
+ 	int (*set_asic_baco_state)(void *handle, int state);
+ 	int (*get_ppfeature_status)(void *handle, char *buf);
+ 	int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
++	int (*asic_reset_mode_2)(void *handle);
+ };
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+index 2e3d9ef625bf..7ef202761998 100644
+--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+@@ -1508,6 +1508,26 @@ static int pp_set_ppfeature_status(void *handle, uint64_t ppfeature_masks)
+ 	return ret;
+ }
+ 
++static int pp_asic_reset_mode_2(void *handle)
++{
++	struct pp_hwmgr *hwmgr = handle;
++		int ret = 0;
++
++	if (!hwmgr || !hwmgr->pm_en)
++		return -EINVAL;
++
++	if (hwmgr->hwmgr_func->asic_reset == NULL) {
++		pr_info_ratelimited("%s was not implemented.\n", __func__);
++		return -EINVAL;
++	}
++
++	mutex_lock(&hwmgr->smu_lock);
++	ret = hwmgr->hwmgr_func->asic_reset(hwmgr, SMU_ASIC_RESET_MODE_2);
++	mutex_unlock(&hwmgr->smu_lock);
++
++	return ret;
++}
++
+ static const struct amd_pm_funcs pp_dpm_funcs = {
+ 	.load_firmware = pp_dpm_load_fw,
+ 	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
+@@ -1564,4 +1584,5 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
+ 	.set_asic_baco_state = pp_set_asic_baco_state,
+ 	.get_ppfeature_status = pp_get_ppfeature_status,
+ 	.set_ppfeature_status = pp_set_ppfeature_status,
++	.asic_reset_mode_2 = pp_asic_reset_mode_2,
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3463-drm-amdgpu-Use-new-mode2-reset-interface-for-RV.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3463-drm-amdgpu-Use-new-mode2-reset-interface-for-RV.patch
new file mode 100644
index 00000000..54a59cd3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3463-drm-amdgpu-Use-new-mode2-reset-interface-for-RV.patch
@@ -0,0 +1,76 @@
+From 36201e2c16c04fc7419b964c53ad5ff29b7185ec Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Fri, 26 Jul 2019 14:07:42 -0400
+Subject: [PATCH 3463/4256] drm/amdgpu: Use new mode2 reset interface for RV.
+
+Integrate the mode2 reset into rest sequence.
+
+v2:
+Check ppfuncs pointer for NULL
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  1 +
+ drivers/gpu/drm/amd/amdgpu/soc15.c         | 25 +++++++++++++++-------
+ 2 files changed, 18 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 80904cb6bccc..ba49073131d0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3510,6 +3510,7 @@ bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
+ 		case CHIP_VEGA20:
+ 		case CHIP_VEGA10:
+ 		case CHIP_VEGA12:
++		case CHIP_RAVEN:
+ 			break;
+ 		default:
+ 			goto disabled;
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index c2d324d8da75..77e679920c1c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -508,6 +508,15 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
++static int soc15_mode2_reset(struct amdgpu_device *adev)
++{
++	if (!adev->powerplay.pp_funcs ||
++	    !adev->powerplay.pp_funcs->asic_reset_mode_2)
++		return -ENOENT;
++
++	return adev->powerplay.pp_funcs->asic_reset_mode_2(adev->powerplay.pp_handle);
++}
++
+ static enum amd_reset_method
+ soc15_asic_reset_method(struct amdgpu_device *adev)
+ {
+@@ -546,14 +555,14 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
+ 
+ static int soc15_asic_reset(struct amdgpu_device *adev)
+ {
+-	int ret;
+-
+-	if (soc15_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
+-		ret = soc15_asic_baco_reset(adev);
+-	else
+-		ret = soc15_asic_mode1_reset(adev);
+-
+-	return ret;
++	switch (soc15_asic_reset_method(adev)) {
++		case AMD_RESET_METHOD_BACO:
++			return soc15_asic_baco_reset(adev);
++		case AMD_RESET_METHOD_MODE2:
++			return soc15_mode2_reset(adev);
++		default:
++			return soc15_asic_mode1_reset(adev);
++	}
+ }
+ 
+ /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3464-drm-amdgpu-remove-special-autoload-handling-for-navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3464-drm-amdgpu-remove-special-autoload-handling-for-navi.patch
new file mode 100644
index 00000000..a0a0eb8d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3464-drm-amdgpu-remove-special-autoload-handling-for-navi.patch
@@ -0,0 +1,32 @@
+From 6536112325de5d1bd1e0463c912a5285f61af071 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 15 Aug 2019 15:08:02 +0800
+Subject: [PATCH 3464/4256] drm/amdgpu: remove special autoload handling for
+ navi12
+
+s/r list in rlc firmware is ready, so remove the special autoload handling
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 60e421d5aae4..72c269078564 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1036,8 +1036,7 @@ static int psp_np_fw_load(struct psp_context *psp)
+ 			return ret;
+ 
+ 		/* Start rlc autoload after psp recieved all the gfx firmware */
+-		if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM ||
+-		    (adev->asic_type == CHIP_NAVI12 && ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G)) {
++		if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
+ 			ret = psp_rlc_autoload(psp);
+ 			if (ret) {
+ 				DRM_ERROR("Failed to start rlc autoload\n");
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3465-drm-amdgpu-fix-debug-level-for-ppt-offset-size.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3465-drm-amdgpu-fix-debug-level-for-ppt-offset-size.patch
new file mode 100644
index 00000000..02686163
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3465-drm-amdgpu-fix-debug-level-for-ppt-offset-size.patch
@@ -0,0 +1,29 @@
+From a1c21459439765ce6deb3c043b1e3495fe8a3a73 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 15 Aug 2019 17:43:36 +0800
+Subject: [PATCH 3465/4256] drm/amdgpu: fix debug level for ppt offset/size
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+index 35fd46bdfc53..82f6b413718b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+@@ -83,8 +83,8 @@ void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
+ 		const struct smc_firmware_header_v2_0 *v2_hdr =
+ 			container_of(v1_hdr, struct smc_firmware_header_v2_0, v1_0);
+ 
+-		DRM_INFO("ppt_offset_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_offset_bytes));
+-		DRM_INFO("ppt_size_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_size_bytes));
++		DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_offset_bytes));
++		DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_size_bytes));
+ 	} else {
+ 		DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3466-drm-amdgpu-remove-redundant-argument-for-psp_funcs-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3466-drm-amdgpu-remove-redundant-argument-for-psp_funcs-c.patch
new file mode 100644
index 00000000..8f162693
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3466-drm-amdgpu-remove-redundant-argument-for-psp_funcs-c.patch
@@ -0,0 +1,105 @@
+From a5267ed2f1c8a92ae8543a500c833dff53c4d5a7 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Fri, 16 Aug 2019 18:00:54 +0800
+Subject: [PATCH 3466/4256] drm/amdgpu: remove redundant argument for
+ psp_funcs::cmd_submit callback
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 5 ++---
+ drivers/gpu/drm/amd/amdgpu/psp_v10_0.c  | 1 -
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c  | 1 -
+ drivers/gpu/drm/amd/amdgpu/psp_v12_0.c  | 1 -
+ drivers/gpu/drm/amd/amdgpu/psp_v3_1.c   | 1 -
+ 6 files changed, 3 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 72c269078564..2d5cf18f2241 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -145,8 +145,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
+ 	memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
+ 
+ 	index = atomic_inc_return(&psp->fence_value);
+-	ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
+-			     fence_mc_addr, index);
++	ret = psp_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
+         if (ret) {
+                 atomic_dec(&psp->fence_value);
+ 		mutex_unlock(&psp->mutex);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+index 0029fa2b2ff9..b73d4aa28fba 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+@@ -90,7 +90,6 @@ struct psp_funcs
+ 	int (*ring_destroy)(struct psp_context *psp,
+ 			    enum psp_ring_type ring_type);
+ 	int (*cmd_submit)(struct psp_context *psp,
+-			  struct amdgpu_firmware_info *ucode,
+ 			  uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+ 			  int index);
+ 	bool (*compare_sram_data)(struct psp_context *psp,
+@@ -223,8 +222,8 @@ struct amdgpu_psp_funcs {
+ #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
+ #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
+ #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
+-#define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \
+-		(psp)->funcs->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index))
++#define psp_cmd_submit(psp, cmd_mc, fence_mc, index) \
++		(psp)->funcs->cmd_submit((psp), (cmd_mc), (fence_mc), (index))
+ #define psp_compare_sram_data(psp, ucode, type) \
+ 		(psp)->funcs->compare_sram_data((psp), (ucode), (type))
+ #define psp_init_microcode(psp) \
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+index 70a5a9eaf037..216af0af255a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+@@ -190,7 +190,6 @@ static int psp_v10_0_ring_destroy(struct psp_context *psp,
+ }
+ 
+ static int psp_v10_0_cmd_submit(struct psp_context *psp,
+-				struct amdgpu_firmware_info *ucode,
+ 				uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+ 				int index)
+ {
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index 4954b1d7d3d0..247a7aebb273 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -506,7 +506,6 @@ static int psp_v11_0_ring_destroy(struct psp_context *psp,
+ }
+ 
+ static int psp_v11_0_cmd_submit(struct psp_context *psp,
+-			       struct amdgpu_firmware_info *ucode,
+ 			       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+ 			       int index)
+ {
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+index f37b8af4b986..fd55baa6ea31 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+@@ -334,7 +334,6 @@ static int psp_v12_0_ring_destroy(struct psp_context *psp,
+ }
+ 
+ static int psp_v12_0_cmd_submit(struct psp_context *psp,
+-			       struct amdgpu_firmware_info *ucode,
+ 			       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+ 			       int index)
+ {
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+index ba327581f301..4a02058682f5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+@@ -409,7 +409,6 @@ static int psp_v3_1_ring_destroy(struct psp_context *psp,
+ }
+ 
+ static int psp_v3_1_cmd_submit(struct psp_context *psp,
+-			       struct amdgpu_firmware_info *ucode,
+ 			       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+ 			       int index)
+ {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3467-drm-amdgpu-gfx9-update-pg_flags-after-determining-if.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3467-drm-amdgpu-gfx9-update-pg_flags-after-determining-if.patch
new file mode 100644
index 00000000..5d580f7c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3467-drm-amdgpu-gfx9-update-pg_flags-after-determining-if.patch
@@ -0,0 +1,56 @@
+From 0dd6f0b7dbf79233a263b6d0e2493e978cc253a7 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 15 Aug 2019 08:27:09 -0500
+Subject: [PATCH 3467/4256] drm/amdgpu/gfx9: update pg_flags after determining
+ if gfx off is possible
+
+We need to set certain power gating flags after we determine
+if the firmware version is sufficient to support gfxoff.
+Previously we set the pg flags in early init, but we later
+we might have disabled gfxoff if the firmware versions didn't
+support it.  Move adding the additional pg flags after we
+determine whether or not to support gfxoff.
+
+Fixes: 005440066f92 ("drm/amdgpu: enable gfxoff again on raven series (v2)")
+Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++++
+ drivers/gpu/drm/amd/amdgpu/soc15.c    | 5 -----
+ 2 files changed, 4 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 5c8107dc8803..155a8699adb8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -1037,6 +1037,10 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
+ 		    (adev->gfx.rlc_feature_version < 1) ||
+ 		    !adev->gfx.rlc.is_rlc_v2_1)
+ 			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
++		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
++			adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
++				AMD_PG_SUPPORT_CP |
++				AMD_PG_SUPPORT_RLC_SMU_HS;
+ 		break;
+ 	default:
+ 		break;
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 77e679920c1c..2cf61946f3f1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1133,11 +1133,6 @@ static int soc15_common_early_init(void *handle)
+ 
+ 			adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
+ 		}
+-
+-		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+-			adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
+-				AMD_PG_SUPPORT_CP |
+-				AMD_PG_SUPPORT_RLC_SMU_HS;
+ 		break;
+ 	case CHIP_ARCTURUS:
+ 		adev->asic_funcs = &vega20_asic_funcs;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3468-drm-amdgpu-Fix-a-typo-in-the-include-header-guard-of.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3468-drm-amdgpu-Fix-a-typo-in-the-include-header-guard-of.patch
new file mode 100644
index 00000000..dc7b6d57
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3468-drm-amdgpu-Fix-a-typo-in-the-include-header-guard-of.patch
@@ -0,0 +1,34 @@
+From 3c879ac6998fc30d5d1326a1e6b036f5102e645b Mon Sep 17 00:00:00 2001
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Date: Sun, 18 Aug 2019 17:59:57 +0200
+Subject: [PATCH 3468/4256] drm/amdgpu: Fix a typo in the include header guard
+ of 'navi12_ip_offset.h'
+
+'_navi10_ip_offset_HEADER' is already used in 'navi10_ip_offset.h', so use
+'_navi12_ip_offset_HEADER' instead here.
+
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/navi12_ip_offset.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/include/navi12_ip_offset.h b/drivers/gpu/drm/amd/include/navi12_ip_offset.h
+index 229e8fddfcc1..6c2cc6296c06 100644
+--- a/drivers/gpu/drm/amd/include/navi12_ip_offset.h
++++ b/drivers/gpu/drm/amd/include/navi12_ip_offset.h
+@@ -18,8 +18,8 @@
+  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+  */
+-#ifndef _navi10_ip_offset_HEADER
+-#define _navi10_ip_offset_HEADER
++#ifndef _navi12_ip_offset_HEADER
++#define _navi12_ip_offset_HEADER
+ 
+ #define MAX_INSTANCE                                       7
+ #define MAX_SEGMENT                                        5
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3469-drm-amdkfd-Fill-the-name-field-in-node-topology-with.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3469-drm-amdkfd-Fill-the-name-field-in-node-topology-with.patch
new file mode 100644
index 00000000..871cad96
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3469-drm-amdkfd-Fill-the-name-field-in-node-topology-with.patch
@@ -0,0 +1,186 @@
+From c0d3e2b82e2c01411a4911d6a6b0c56e63d84340 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Thu, 1 Aug 2019 22:55:50 -0400
+Subject: [PATCH 3469/4256] drm/amdkfd: Fill the name field in node topology
+ with asic name v2
+
+The name field in node topology has not been used. We re-purpose it to
+hold the asic name, which can be queried by user space applications
+through sysfs.
+
+Change-Id: I74f4f5487db169004a9d27ea15abe99261c86220
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 36 ++++++++++++-------------
+ 1 file changed, 18 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index b333e81061f5..6c0f16bcb1aa 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -42,7 +42,7 @@ static atomic_t kfd_locked = ATOMIC_INIT(0);
+ #ifdef KFD_SUPPORT_IOMMU_V2
+ static const struct kfd_device_info kaveri_device_info = {
+ 	.asic_family = CHIP_KAVERI,
+-	.asic_name = "Kaveri",
++	.asic_name = "kaveri",
+ 	.max_pasid_bits = 16,
+ 	/* max num of queues for KV.TODO should be a dynamic value */
+ 	.max_no_of_hqd	= 24,
+@@ -61,7 +61,7 @@ static const struct kfd_device_info kaveri_device_info = {
+ 
+ static const struct kfd_device_info carrizo_device_info = {
+ 	.asic_family = CHIP_CARRIZO,
+-	.asic_name = "Carrizo",
++	.asic_name = "carrizo",
+ 	.max_pasid_bits = 16,
+ 	/* max num of queues for CZ.TODO should be a dynamic value */
+ 	.max_no_of_hqd	= 24,
+@@ -80,7 +80,7 @@ static const struct kfd_device_info carrizo_device_info = {
+ 
+ static const struct kfd_device_info raven_device_info = {
+ 	.asic_family = CHIP_RAVEN,
+-	.asic_name = "Raven",
++	.asic_name = "raven",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 8,
+@@ -99,7 +99,7 @@ static const struct kfd_device_info raven_device_info = {
+ 
+ static const struct kfd_device_info hawaii_device_info = {
+ 	.asic_family = CHIP_HAWAII,
+-	.asic_name = "Hawaii",
++	.asic_name = "hawaii",
+ 	.max_pasid_bits = 16,
+ 	/* max num of queues for KV.TODO should be a dynamic value */
+ 	.max_no_of_hqd	= 24,
+@@ -118,7 +118,7 @@ static const struct kfd_device_info hawaii_device_info = {
+ 
+ static const struct kfd_device_info tonga_device_info = {
+ 	.asic_family = CHIP_TONGA,
+-	.asic_name = "Tonga",
++	.asic_name = "tonga",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 4,
+@@ -136,7 +136,7 @@ static const struct kfd_device_info tonga_device_info = {
+ 
+ static const struct kfd_device_info fiji_device_info = {
+ 	.asic_family = CHIP_FIJI,
+-	.asic_name = "Fiji",
++	.asic_name = "fiji",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 4,
+@@ -154,7 +154,7 @@ static const struct kfd_device_info fiji_device_info = {
+ 
+ static const struct kfd_device_info fiji_vf_device_info = {
+ 	.asic_family = CHIP_FIJI,
+-	.asic_name = "Fiji",
++	.asic_name = "fiji",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 4,
+@@ -173,7 +173,7 @@ static const struct kfd_device_info fiji_vf_device_info = {
+ 
+ static const struct kfd_device_info polaris10_device_info = {
+ 	.asic_family = CHIP_POLARIS10,
+-	.asic_name = "Polaris10",
++	.asic_name = "polaris10",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 4,
+@@ -191,7 +191,7 @@ static const struct kfd_device_info polaris10_device_info = {
+ 
+ static const struct kfd_device_info polaris10_vf_device_info = {
+ 	.asic_family = CHIP_POLARIS10,
+-	.asic_name = "Polaris10",
++	.asic_name = "polaris10",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 4,
+@@ -209,7 +209,7 @@ static const struct kfd_device_info polaris10_vf_device_info = {
+ 
+ static const struct kfd_device_info polaris11_device_info = {
+ 	.asic_family = CHIP_POLARIS11,
+-	.asic_name = "Polaris11",
++	.asic_name = "polaris11",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 4,
+@@ -227,7 +227,7 @@ static const struct kfd_device_info polaris11_device_info = {
+ 
+ static const struct kfd_device_info polaris12_device_info = {
+ 	.asic_family = CHIP_POLARIS12,
+-	.asic_name = "Polaris12",
++	.asic_name = "polaris12",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 4,
+@@ -245,7 +245,7 @@ static const struct kfd_device_info polaris12_device_info = {
+ 
+ static const struct kfd_device_info vegam_device_info = {
+ 	.asic_family = CHIP_VEGAM,
+-	.asic_name = "VegaM",
++	.asic_name = "vegam",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 4,
+@@ -263,7 +263,7 @@ static const struct kfd_device_info vegam_device_info = {
+ 
+ static const struct kfd_device_info vega10_device_info = {
+ 	.asic_family = CHIP_VEGA10,
+-	.asic_name = "Vega10",
++	.asic_name = "vega10",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 8,
+@@ -281,7 +281,7 @@ static const struct kfd_device_info vega10_device_info = {
+ 
+ static const struct kfd_device_info vega10_vf_device_info = {
+ 	.asic_family = CHIP_VEGA10,
+-	.asic_name = "Vega10",
++	.asic_name = "vega10",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 8,
+@@ -299,7 +299,7 @@ static const struct kfd_device_info vega10_vf_device_info = {
+ 
+ static const struct kfd_device_info vega12_device_info = {
+ 	.asic_family = CHIP_VEGA12,
+-	.asic_name = "Vega12",
++	.asic_name = "vega12",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 8,
+@@ -317,7 +317,7 @@ static const struct kfd_device_info vega12_device_info = {
+ 
+ static const struct kfd_device_info vega20_device_info = {
+ 	.asic_family = CHIP_VEGA20,
+-	.asic_name = "Vega20",
++	.asic_name = "vega20",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd	= 24,
+ 	.doorbell_size	= 8,
+@@ -335,7 +335,7 @@ static const struct kfd_device_info vega20_device_info = {
+ 
+ static const struct kfd_device_info arcturus_device_info = {
+ 	.asic_family = CHIP_ARCTURUS,
+-	.asic_name = "Arcturus",
++	.asic_name = "arcturus",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd	= 24,
+ 	.doorbell_size	= 8,
+@@ -353,7 +353,7 @@ static const struct kfd_device_info arcturus_device_info = {
+ 
+ static const struct kfd_device_info navi10_device_info = {
+ 	.asic_family = CHIP_NAVI10,
+-	.asic_name = "Navi10",
++	.asic_name = "navi10",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 8,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3470-drm-amd-powerplay-add-smu_smc_read_sensor-support-fo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3470-drm-amd-powerplay-add-smu_smc_read_sensor-support-fo.patch
new file mode 100644
index 00000000..d30716e7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3470-drm-amd-powerplay-add-smu_smc_read_sensor-support-fo.patch
@@ -0,0 +1,44 @@
+From 36b36bf0367af51cade1e9ee243f9d4ce6f250e6 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Fri, 16 Aug 2019 15:17:42 +0800
+Subject: [PATCH 3470/4256] drm/amd/powerplay: add smu_smc_read_sensor support
+ for arcturus
+
+the bellow patch refine the sensor read sequence,
+but missed to add arcuturs support. (arcuturs_ppt.c)
+it will cause some sensor is not supported in arcturus.
+
+drm/amd/powerplay: change smu_read_sensor sequence in smu
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index fdf5b2c47cd0..5443403f9eea 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -1022,6 +1022,9 @@ static int arcturus_read_sensor(struct smu_context *smu,
+ 	PPTable_t *pptable = table_context->driver_pptable;
+ 	int ret = 0;
+ 
++	if (!data || !size)
++		return -EINVAL;
++
+ 	switch (sensor) {
+ 	case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
+ 		*(uint32_t *)data = pptable->FanMaximumRpm;
+@@ -1046,7 +1049,7 @@ static int arcturus_read_sensor(struct smu_context *smu,
+ 		*size = 4;
+ 		break;
+ 	default:
+-		return -EINVAL;
++		ret = smu_smc_read_sensor(smu, sensor, data, size);
+ 	}
+ 
+ 	return ret;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3471-drm-amd-powerplay-fix-variable-type-errors-in-smu_v1.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3471-drm-amd-powerplay-fix-variable-type-errors-in-smu_v1.patch
new file mode 100644
index 00000000..dcdfa211
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3471-drm-amd-powerplay-fix-variable-type-errors-in-smu_v1.patch
@@ -0,0 +1,50 @@
+From bd80417958d63acfc61b977eb2209c94d0df5e1f Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Mon, 19 Aug 2019 23:38:02 +0800
+Subject: [PATCH 3471/4256] drm/amd/powerplay: fix variable type errors in
+ smu_v11_0_setup_pptable
+
+fix size type errors, from uint32_t to uint16_t.
+it will cause only initializes the highest 16 bits in
+smu_get_atom_data_table function.
+
+bug report:
+This fixes the following static checker warning.
+        drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:390 smu_v11_0_setup_pptable()
+        warn: passing casted pointer '&size' to 'smu_get_atom_data_table()' 32 vs 16.
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 4a51de4ff162..4cdbed3b7a83 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -360,6 +360,7 @@ static int smu_v11_0_setup_pptable(struct smu_context *smu)
+ 	const struct smc_firmware_header_v1_0 *hdr;
+ 	int ret, index;
+ 	uint32_t size;
++	uint16_t atom_table_size;
+ 	uint8_t frev, crev;
+ 	void *table;
+ 	uint16_t version_major, version_minor;
+@@ -387,10 +388,11 @@ static int smu_v11_0_setup_pptable(struct smu_context *smu)
+ 		index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+ 						    powerplayinfo);
+ 
+-		ret = smu_get_atom_data_table(smu, index, (uint16_t *)&size, &frev, &crev,
++		ret = smu_get_atom_data_table(smu, index, &atom_table_size, &frev, &crev,
+ 					      (uint8_t **)&table);
+ 		if (ret)
+ 			return ret;
++		size = atom_table_size;
+ 	}
+ 
+ 	if (!smu->smu_table.power_play_table)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3472-drm-amd-powerplay-remove-duplicate-macro-smu_get_ucl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3472-drm-amd-powerplay-remove-duplicate-macro-smu_get_ucl.patch
new file mode 100644
index 00000000..0b9043ab
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3472-drm-amd-powerplay-remove-duplicate-macro-smu_get_ucl.patch
@@ -0,0 +1,39 @@
+From a108d3462fe8a984e7df4e6c6073b24f20fe5e36 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Tue, 20 Aug 2019 13:28:51 +0800
+Subject: [PATCH 3472/4256] drm/amd/powerplay: remove duplicate macro
+ smu_get_uclk_dpm_states in amdgpu_smu.h
+
+remove duplicate macro smu_get_uclk_dpm_states in amdgpu_smu.h
+
+"
+ #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
+         ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
+ #define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
+         ((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
+ #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
+         ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
+"
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index ca9b9ec39de8..fc59d9686e61 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -730,8 +730,6 @@ struct smu_funcs
+ 	((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
+ #define smu_set_azalia_d3_pme(smu) \
+ 	((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs->set_azalia_d3_pme((smu)) : 0)
+-#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
+-	((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
+ #define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
+ 	((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
+ #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3473-drm-amd-powerplay-update-Arcturus-smc-fw-and-driver-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3473-drm-amd-powerplay-update-Arcturus-smc-fw-and-driver-.patch
new file mode 100644
index 00000000..94b27d99
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3473-drm-amd-powerplay-update-Arcturus-smc-fw-and-driver-.patch
@@ -0,0 +1,89 @@
+From 27c875fecb21d5ebe846371c8c8f384e5f5d7010 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 16 Aug 2019 10:55:21 +0800
+Subject: [PATCH 3473/4256] drm/amd/powerplay: update Arcturus smc fw and
+ driver interface header
+
+Update smc fw and driver interface header.
+
+Change-Id: If4ac09c41b1309f746b757f78880fffb491d50f8
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ .../powerplay/inc/smu11_driver_if_arcturus.h    | 17 +++++++++++------
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h   |  2 +-
+ 2 files changed, 12 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+index b99e98c40720..e02950b505fa 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+@@ -27,7 +27,7 @@
+ // *** IMPORTANT ***
+ // SMU TEAM: Always increment the interface version if
+ // any structure is changed in this file
+-//#define SMU11_DRIVER_IF_VERSION 0x08
++//#define SMU11_DRIVER_IF_VERSION 0x09
+ 
+ #define PPTABLE_ARCTURUS_SMU_VERSION 4
+ 
+@@ -691,7 +691,12 @@ typedef struct {
+   uint16_t          XgmiFclkFreq    [NUM_XGMI_PSTATE_LEVELS];
+   uint16_t          XgmiSocVoltage  [NUM_XGMI_PSTATE_LEVELS];
+ 
+-  uint32_t     BoardReserved[10];
++  // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
++  uint8_t      GpioI2cScl;          // Serial Clock
++  uint8_t      GpioI2cSda;          // Serial Data
++  uint16_t     GpioPadding;
++
++  uint32_t     BoardReserved[9];
+ 
+   // Padding for MMHUB - do not modify this
+   uint32_t     MmHubPadding[8]; // SMU internal use
+@@ -738,7 +743,7 @@ typedef struct {
+   uint32_t Padding[4];
+ 
+   // Padding - ignore
+-  uint32_t     MmHubPadding[7]; // SMU internal use
++  uint32_t     MmHubPadding[8]; // SMU internal use
+ } SmuMetrics_t;
+ 
+ 
+@@ -748,7 +753,7 @@ typedef struct {
+   float    avgPsmVoltage[75];
+   float    minPsmVoltage[75];
+ 
+-  uint32_t MmHubPadding[3]; // SMU internal use
++  uint32_t MmHubPadding[8]; // SMU internal use
+ } AvfsDebugTable_t;
+ 
+ typedef struct {
+@@ -797,9 +802,9 @@ typedef struct {
+ 
+   uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units
+ 
+-  uint32_t EnabledAvfsModules;
++  uint32_t EnabledAvfsModules[2];
+ 
+-  uint32_t MmHubPadding[7]; // SMU internal use
++  uint32_t MmHubPadding[8]; // SMU internal use
+ } AvfsFuseOverride_t;
+ 
+ /* NOT CURRENTLY USED
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 5fbf082be091..0a22fa48ff5a 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -27,7 +27,7 @@
+ 
+ #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
+ #define SMU11_DRIVER_IF_VERSION_VG20 0x13
+-#define SMU11_DRIVER_IF_VERSION_ARCT 0x08
++#define SMU11_DRIVER_IF_VERSION_ARCT 0x09
+ #define SMU11_DRIVER_IF_VERSION_NV10 0x33
+ #define SMU11_DRIVER_IF_VERSION_NV12 0x33
+ #define SMU11_DRIVER_IF_VERSION_NV14 0x33
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3474-drm-amd-powerplay-expose-supported-clock-domains-onl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3474-drm-amd-powerplay-expose-supported-clock-domains-onl.patch
new file mode 100644
index 00000000..086d6081
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3474-drm-amd-powerplay-expose-supported-clock-domains-onl.patch
@@ -0,0 +1,71 @@
+From 1e7a25ed9b24ef78b28905e387fc494d10bcace6 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 16 Aug 2019 11:34:12 +0800
+Subject: [PATCH 3474/4256] drm/amd/powerplay: expose supported clock domains
+ only through sysfs
+
+Do not expose those unsupported clock domains through sysfs on
+Arcturus.
+
+Change-Id: I526e7bd457fdcd8c79d4581bb9b77e5cb57f5844
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 26 ++++++++++++++++----------
+ 1 file changed, 16 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index 6cff61802400..6a651b0480c0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -2826,10 +2826,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
+ 			DRM_ERROR("failed to create device file pp_dpm_socclk\n");
+ 			return ret;
+ 		}
+-		ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
+-		if (ret) {
+-			DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
+-			return ret;
++		if (adev->asic_type != CHIP_ARCTURUS) {
++			ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
++			if (ret) {
++				DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
++				return ret;
++			}
+ 		}
+ 	}
+ 	if (adev->asic_type >= CHIP_VEGA20) {
+@@ -2839,10 +2841,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
+ 			return ret;
+ 		}
+ 	}
+-	ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
+-	if (ret) {
+-		DRM_ERROR("failed to create device file pp_dpm_pcie\n");
+-		return ret;
++	if (adev->asic_type != CHIP_ARCTURUS) {
++		ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
++		if (ret) {
++			DRM_ERROR("failed to create device file pp_dpm_pcie\n");
++			return ret;
++		}
+ 	}
+ 	ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
+ 	if (ret) {
+@@ -2946,9 +2950,11 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
+ 	device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
+ 	if (adev->asic_type >= CHIP_VEGA10) {
+ 		device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
+-		device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
++		if (adev->asic_type != CHIP_ARCTURUS)
++			device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
+ 	}
+-	device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
++	if (adev->asic_type != CHIP_ARCTURUS)
++		device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
+ 	if (adev->asic_type >= CHIP_VEGA20)
+ 		device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
+ 	device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3475-drm-amd-powerplay-get-bootup-fclk-value.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3475-drm-amd-powerplay-get-bootup-fclk-value.patch
new file mode 100644
index 00000000..b9d7e2e7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3475-drm-amd-powerplay-get-bootup-fclk-value.patch
@@ -0,0 +1,71 @@
+From 778aca4eea500d4be59e80f73a2c5994459f60dd Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 16 Aug 2019 13:47:01 +0800
+Subject: [PATCH 3475/4256] drm/amd/powerplay: get bootup fclk value
+
+This is available with firmwareinfo table v3.2 or later.
+
+Change-Id: I223edf3c616b9e3e2527c752214fef5ab53d1cea
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  3 +++
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 21 +++++++++++++++++++
+ 2 files changed, 24 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index fc59d9686e61..e80c81552d29 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -222,6 +222,9 @@ struct smu_bios_boot_up_values
+ 	uint16_t			vdd_gfx;
+ 	uint8_t				cooling_id;
+ 	uint32_t			pp_table_id;
++	uint32_t			format_revision;
++	uint32_t			content_revision;
++	uint32_t			fclk;
+ };
+ 
+ enum smu_table_id
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 4cdbed3b7a83..16d7768dca9b 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -570,6 +570,9 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
+ 		smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
+ 	}
+ 
++	smu->smu_table.boot_values.format_revision = header->format_revision;
++	smu->smu_table.boot_values.content_revision = header->content_revision;
++
+ 	return 0;
+ }
+ 
+@@ -649,6 +652,24 @@ static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
+ 	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
+ 	smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
+ 
++	if ((smu->smu_table.boot_values.format_revision == 3) &&
++	    (smu->smu_table.boot_values.content_revision >= 2)) {
++		memset(&input, 0, sizeof(input));
++		input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
++		input.syspll_id = SMU11_SYSPLL1_2_ID;
++		input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
++		index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
++						    getsmuclockinfo);
++
++		ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
++						(uint32_t *)&input);
++		if (ret)
++			return -EINVAL;
++
++		output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
++		smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
++	}
++
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3476-drm-amd-powerplay-set-Arcturus-default-fclk-as-bootu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3476-drm-amd-powerplay-set-Arcturus-default-fclk-as-bootu.patch
new file mode 100644
index 00000000..3b966c09
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3476-drm-amd-powerplay-set-Arcturus-default-fclk-as-bootu.patch
@@ -0,0 +1,33 @@
+From 45de763d0ccb9f209d68652d51c6999e09405404 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 16 Aug 2019 13:52:26 +0800
+Subject: [PATCH 3476/4256] drm/amd/powerplay: set Arcturus default fclk as
+ bootup value on dpm disabled
+
+On fclk dpm disabled, the default dpm table will be setup with only one
+level and clock frequency as bootup value.
+
+Change-Id: Iecf74aa5bd10c9aa7839bc32877cfa99bcbef4b3
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 5443403f9eea..0eb85702f7ed 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -463,7 +463,8 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu)
+ 			return ret;
+ 		}
+ 	} else {
+-		single_dpm_table->count = 0;
++		single_dpm_table->count = 1;
++		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
+ 	}
+ 	arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3477-drm-amd-powerplay-correct-SW-smu11-thermal-range-set.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3477-drm-amd-powerplay-correct-SW-smu11-thermal-range-set.patch
new file mode 100644
index 00000000..37b73f64
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3477-drm-amd-powerplay-correct-SW-smu11-thermal-range-set.patch
@@ -0,0 +1,220 @@
+From 493b140ed92cbdec7f7476b9d5fa5f9c82c2d5eb Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 16 Aug 2019 17:11:46 +0800
+Subject: [PATCH 3477/4256] drm/amd/powerplay: correct SW smu11 thermal range
+ settings
+
+Problems with current settings:
+1. The min value was overrided to 0 on Vega20 & Navi10. While
+   the expected should be -273.15 C.
+2. The thermal min/max threshold was output in wrong unit on
+   Navi10 & Arcturus. As TEMP_RANGE_MIN/MAX is already in
+   millicelsius. And "*1000" in smu_v11_0_start_thermal_control
+   makes the output wrongly.
+
+Change-Id: I2f1866edd1baf264f521310343f492eaede26c33
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  | 10 ----
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  6 +++
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    |  5 +-
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 51 +++++++------------
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 20 +++++---
+ 5 files changed, 38 insertions(+), 54 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 0eb85702f7ed..58fc5d0c126b 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -878,23 +878,14 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
+ 	return ret;
+ }
+ 
+-static const struct smu_temperature_range arcturus_thermal_policy[] =
+-{
+-	{-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
+-	{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
+-};
+-
+ static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
+ 						struct smu_temperature_range *range)
+ {
+-
+ 	PPTable_t *pptable = smu->smu_table.driver_pptable;
+ 
+ 	if (!range)
+ 		return -EINVAL;
+ 
+-	memcpy(range, &arcturus_thermal_policy[0], sizeof(struct smu_temperature_range));
+-
+ 	range->max = pptable->TedgeLimit *
+ 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ 	range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
+@@ -908,7 +899,6 @@ static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
+ 	range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
+ 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ 
+-
+ 	return 0;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 0a22fa48ff5a..59b2045e37e4 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -64,6 +64,12 @@
+ #define WORKLOAD_MAP(profile, workload) \
+ 	[profile] = {1, (workload)}
+ 
++static const struct smu_temperature_range smu11_thermal_policy[] =
++{
++	{-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
++	{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
++};
++
+ struct smu_11_0_cmn2aisc_mapping {
+ 	int	valid_mapping;
+ 	int	map_to;
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 920156e9fb9d..2d908afbf525 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1503,9 +1503,8 @@ static int navi10_get_thermal_temperature_range(struct smu_context *smu,
+ 	if (!range || !powerplay_table)
+ 		return -EINVAL;
+ 
+-	/* The unit is temperature */
+-	range->min = 0;
+-	range->max = powerplay_table->software_shutdown_temp;
++	range->max = powerplay_table->software_shutdown_temp *
++		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ 
+ 	return 0;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 16d7768dca9b..f5efe8b5e96c 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1127,23 +1127,17 @@ static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
+ }
+ 
+ static int smu_v11_0_set_thermal_range(struct smu_context *smu,
+-				       struct smu_temperature_range *range)
++				       struct smu_temperature_range range)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+ 	int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
+ 	int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
+ 	uint32_t val;
+ 
+-	if (!range)
+-		return -EINVAL;
+-
+-	if (low < range->min)
+-		low = range->min;
+-	if (high > range->max)
+-		high = range->max;
+-
+-	low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, range->min);
+-	high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, range->max);
++	low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
++			range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
++	high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
++			range.max / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
+ 
+ 	if (low > high)
+ 		return -EINVAL;
+@@ -1179,27 +1173,20 @@ static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
+ static int smu_v11_0_start_thermal_control(struct smu_context *smu)
+ {
+ 	int ret = 0;
+-	struct smu_temperature_range range = {
+-		TEMP_RANGE_MIN,
+-		TEMP_RANGE_MAX,
+-		TEMP_RANGE_MAX,
+-		TEMP_RANGE_MIN,
+-		TEMP_RANGE_MAX,
+-		TEMP_RANGE_MAX,
+-		TEMP_RANGE_MIN,
+-		TEMP_RANGE_MAX,
+-		TEMP_RANGE_MAX};
++	struct smu_temperature_range range;
+ 	struct amdgpu_device *adev = smu->adev;
+ 
+ 	if (!smu->pm_enabled)
+ 		return ret;
+ 
++	memcpy(&range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
++
+ 	ret = smu_get_thermal_temperature_range(smu, &range);
+ 	if (ret)
+ 		return ret;
+ 
+ 	if (smu->smu_table.thermal_controller_type) {
+-		ret = smu_v11_0_set_thermal_range(smu, &range);
++		ret = smu_v11_0_set_thermal_range(smu, range);
+ 		if (ret)
+ 			return ret;
+ 
+@@ -1212,17 +1199,15 @@ static int smu_v11_0_start_thermal_control(struct smu_context *smu)
+ 			return ret;
+ 	}
+ 
+-	adev->pm.dpm.thermal.min_temp = range.min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+-	adev->pm.dpm.thermal.max_temp = range.max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+-	adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+-	adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+-	adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+-	adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+-	adev->pm.dpm.thermal.min_mem_temp = range.mem_min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+-	adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+-	adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+-	adev->pm.dpm.thermal.min_temp = range.min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+-	adev->pm.dpm.thermal.max_temp = range.max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	adev->pm.dpm.thermal.min_temp = range.min;
++	adev->pm.dpm.thermal.max_temp = range.max;
++	adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
++	adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
++	adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
++	adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
++	adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
++	adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
++	adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
+ 
+ 	return ret;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index acf075393c13..e14363182691 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -3113,14 +3113,18 @@ static int vega20_get_thermal_temperature_range(struct smu_context *smu,
+ 	if (!range || !powerplay_table)
+ 		return -EINVAL;
+ 
+-	/* The unit is temperature */
+-	range->min = 0;
+-	range->max = powerplay_table->usSoftwareShutdownTemp;
+-	range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE);
+-	range->hotspot_crit_max = pptable->ThotspotLimit;
+-	range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT);
+-	range->mem_crit_max = pptable->ThbmLimit;
+-	range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM);
++	range->max = powerplay_table->usSoftwareShutdownTemp *
++		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
++		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	range->hotspot_crit_max = pptable->ThotspotLimit *
++		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
++		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	range->mem_crit_max = pptable->ThbmLimit *
++		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++	range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM) *
++		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ 
+ 
+ 	return 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3478-drm-amd-powerplay-correct-typo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3478-drm-amd-powerplay-correct-typo.patch
new file mode 100644
index 00000000..35529927
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3478-drm-amd-powerplay-correct-typo.patch
@@ -0,0 +1,30 @@
+From e1f2a884da822efa62e3104d9138807e3f33e359 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 20 Aug 2019 12:22:16 +0800
+Subject: [PATCH 3478/4256] drm/amd/powerplay: correct typo
+
+"COMPUTE" was wrongly spelled as "CUSTOM".
+
+Change-Id: I11693c0e55c2ce5c889d57bb7411fdf9795a8739
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 58fc5d0c126b..9e2c1ce7df1f 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -181,7 +181,7 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFI
+ 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,	WORKLOAD_PPLIB_DEFAULT_BIT),
+ 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,		WORKLOAD_PPLIB_POWER_SAVING_BIT),
+ 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,		WORKLOAD_PPLIB_VIDEO_BIT),
+-	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,		WORKLOAD_PPLIB_CUSTOM_BIT),
++	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,		WORKLOAD_PPLIB_COMPUTE_BIT),
+ 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3479-drm-amd-amdgpu-disable-MMHUB-PG-for-navi10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3479-drm-amd-amdgpu-disable-MMHUB-PG-for-navi10.patch
new file mode 100644
index 00000000..3919fdc6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3479-drm-amd-amdgpu-disable-MMHUB-PG-for-navi10.patch
@@ -0,0 +1,29 @@
+From 18c77d7ab3b1d1b996b562c14c86bacd1a144e27 Mon Sep 17 00:00:00 2001
+From: Kenneth Feng <kenneth.feng@amd.com>
+Date: Tue, 20 Aug 2019 15:11:37 +0800
+Subject: [PATCH 3479/4256] drm/amd/amdgpu: disable MMHUB PG for navi10
+
+Disable MMHUB PG for navi10 according to the production requirement.
+
+Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index d4a2012b4832..46f402a52408 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -616,7 +616,6 @@ static int nv_common_early_init(void *handle)
+ 			AMD_CG_SUPPORT_BIF_LS;
+ 		adev->pg_flags = AMD_PG_SUPPORT_VCN |
+ 			AMD_PG_SUPPORT_VCN_DPG |
+-			AMD_PG_SUPPORT_MMHUB |
+ 			AMD_PG_SUPPORT_ATHUB;
+ 		adev->external_rev_id = adev->rev_id + 0x1;
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3480-drm-amdkfd-fix-kfd-SWDEV-200283-test-issue.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3480-drm-amdkfd-fix-kfd-SWDEV-200283-test-issue.patch
new file mode 100644
index 00000000..ca127d36
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3480-drm-amdkfd-fix-kfd-SWDEV-200283-test-issue.patch
@@ -0,0 +1,172 @@
+From 423eb437f13dab64aec713218132b7f4972e5ab5 Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Tue, 20 Aug 2019 19:13:46 +0800
+Subject: [PATCH 3480/4256] drm/amdkfd: fix kfd SWDEV-200283 test issue
+
+Change-Id: I4db96b1e066b62d83cc2d83553a09bf24ad1a369
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+---
+ .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c   |  7 +++++
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 27 ++++++++++---------
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h | 20 ++++++++++++++
+ include/uapi/linux/kfd_ioctl.h                |  3 ---
+ 4 files changed, 41 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+index 4d9101834ba7..7ef62f62abf9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+@@ -315,6 +315,13 @@ static const struct kfd2kgd_calls kfd2kgd = {
+ 	.invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs,
+ 	.invalidate_tlbs_vmid = kgd_gfx_v9_invalidate_tlbs_vmid,
+ 	.get_hive_id = amdgpu_amdkfd_get_hive_id,
++	.enable_debug_trap = kgd_gfx_v9_enable_debug_trap,
++	.disable_debug_trap = kgd_gfx_v9_disable_debug_trap,
++	.set_debug_trap_data = kgd_gfx_v9_set_debug_trap_data,
++	.set_wave_launch_trap_override = kgd_gfx_v9_set_wave_launch_trap_override,
++	.set_wave_launch_mode = kgd_gfx_v9_set_wave_launch_mode,
++	.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,
++	.build_grace_period_packet_info = kgd_gfx_v9_build_grace_period_packet_info,
+ };
+ 
+ struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+index c98b57a5e9b2..8d80e6b7d684 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+@@ -68,12 +68,6 @@ static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = {
+ 	mmTCP_WATCH3_ADDR_H, mmTCP_WATCH3_ADDR_L, mmTCP_WATCH3_CNTL
+ };
+ 
+-static void kgd_build_grace_period_packet_info(struct kgd_dev *kgd,
+-		uint32_t wait_times,
+-		uint32_t grace_period,
+-		uint32_t *reg_offset,
+-		uint32_t *reg_data);
+-
+ /* Because of REG_GET_FIELD() being used, we put this function in the
+  * asic specific file.
+  */
+@@ -842,7 +836,7 @@ uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd,
+ 		watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
+ }
+ 
+-static uint32_t kgd_enable_debug_trap(struct kgd_dev *kgd,
++uint32_t kgd_gfx_v9_enable_debug_trap(struct kgd_dev *kgd,
+ 				uint32_t trap_debug_wave_launch_mode,
+ 				uint32_t vmid)
+ {
+@@ -876,7 +870,7 @@ static uint32_t kgd_enable_debug_trap(struct kgd_dev *kgd,
+ 	return 0;
+ }
+ 
+-static uint32_t kgd_disable_debug_trap(struct kgd_dev *kgd)
++uint32_t kgd_gfx_v9_disable_debug_trap(struct kgd_dev *kgd)
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 
+@@ -892,7 +886,7 @@ static uint32_t kgd_disable_debug_trap(struct kgd_dev *kgd)
+ 	return 0;
+ }
+ 
+-static uint32_t kgd_set_debug_trap_data(struct kgd_dev *kgd,
++uint32_t kgd_gfx_v9_set_debug_trap_data(struct kgd_dev *kgd,
+ 					int trap_data0,
+ 					int trap_data1)
+ {
+@@ -907,7 +901,7 @@ static uint32_t kgd_set_debug_trap_data(struct kgd_dev *kgd,
+ 	return 0;
+ }
+ 
+-static uint32_t kgd_set_wave_launch_trap_override(struct kgd_dev *kgd,
++uint32_t kgd_gfx_v9_set_wave_launch_trap_override(struct kgd_dev *kgd,
+ 						uint32_t trap_override,
+ 						uint32_t trap_mask)
+ {
+@@ -936,7 +930,7 @@ static uint32_t kgd_set_wave_launch_trap_override(struct kgd_dev *kgd,
+ 	return 0;
+ }
+ 
+-static uint32_t kgd_set_wave_launch_mode(struct kgd_dev *kgd,
++uint32_t kgd_gfx_v9_set_wave_launch_mode(struct kgd_dev *kgd,
+ 					uint8_t wave_launch_mode,
+ 					uint32_t vmid)
+ {
+@@ -980,7 +974,7 @@ static uint32_t kgd_set_wave_launch_mode(struct kgd_dev *kgd,
+  *     sem_rearm_wait_time      -- Wait Count for Semaphore re-arm.
+  *     deq_retry_wait_time      -- Wait Count for Global Wave Syncs.
+  */
+-static void kgd_get_iq_wait_times(struct kgd_dev *kgd,
++void kgd_gfx_v9_get_iq_wait_times(struct kgd_dev *kgd,
+ 					uint32_t *wait_times)
+ 
+ {
+@@ -1023,7 +1017,7 @@ void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmi
+ 	gfxhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base);
+ }
+ 
+-static void kgd_build_grace_period_packet_info(struct kgd_dev *kgd,
++void kgd_gfx_v9_build_grace_period_packet_info(struct kgd_dev *kgd,
+ 		uint32_t wait_times,
+ 		uint32_t grace_period,
+ 		uint32_t *reg_offset,
+@@ -1065,6 +1059,13 @@ static const struct kfd2kgd_calls kfd2kgd = {
+ 	.invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs,
+ 	.invalidate_tlbs_vmid = kgd_gfx_v9_invalidate_tlbs_vmid,
+ 	.get_hive_id = amdgpu_amdkfd_get_hive_id,
++	.enable_debug_trap = kgd_gfx_v9_enable_debug_trap,
++	.disable_debug_trap = kgd_gfx_v9_disable_debug_trap,
++	.set_debug_trap_data = kgd_gfx_v9_set_debug_trap_data,
++	.set_wave_launch_trap_override = kgd_gfx_v9_set_wave_launch_trap_override,
++	.set_wave_launch_mode = kgd_gfx_v9_set_wave_launch_mode,
++	.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,
++	.build_grace_period_packet_info = kgd_gfx_v9_build_grace_period_packet_info,
+ };
+ 
+ struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
+index 26d8879bff9d..a1c5789b5c36 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
+@@ -67,3 +67,23 @@ int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
+ int kgd_gfx_v9_invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
+ int kgd_gfx_v9_get_tile_config(struct kgd_dev *kgd,
+ 		struct tile_config *config);
++uint32_t kgd_gfx_v9_enable_debug_trap(struct kgd_dev *kgd,
++									  uint32_t trap_debug_wave_launch_mode,
++									  uint32_t vmid);
++uint32_t kgd_gfx_v9_disable_debug_trap(struct kgd_dev *kgd);
++uint32_t kgd_gfx_v9_set_debug_trap_data(struct kgd_dev *kgd,
++										int trap_data0,
++										int trap_data1);
++uint32_t kgd_gfx_v9_set_wave_launch_trap_override(struct kgd_dev *kgd,
++												  uint32_t trap_override,
++												  uint32_t trap_mask);
++uint32_t kgd_gfx_v9_set_wave_launch_mode(struct kgd_dev *kgd,
++										 uint8_t wave_launch_mode,
++										 uint32_t vmid);
++void kgd_gfx_v9_get_iq_wait_times(struct kgd_dev *kgd,
++								  uint32_t *wait_times);
++void kgd_gfx_v9_build_grace_period_packet_info(struct kgd_dev *kgd,
++											   uint32_t wait_times,
++											   uint32_t grace_period,
++											   uint32_t *reg_offset,
++											   uint32_t *reg_data);
+diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
+index 617c07047d55..42551e2c6d59 100644
+--- a/include/uapi/linux/kfd_ioctl.h
++++ b/include/uapi/linux/kfd_ioctl.h
+@@ -679,9 +679,6 @@ struct kfd_ioctl_cross_memory_copy_args {
+ #define AMDKFD_IOC_CROSS_MEMORY_COPY		\
+ 		AMDKFD_IOWR(0x22, struct kfd_ioctl_cross_memory_copy_args)
+ 
+-#define AMDKFD_IOC_DBG_TRAP			\
+-		AMDKFD_IOW(0x21, struct kfd_ioctl_dbg_trap_args)
+-
+ #define AMDKFD_COMMAND_START		0x01
+ #define AMDKFD_COMMAND_END		0x23
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3481-drm-amdkfd-Report-domain-with-topology.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3481-drm-amdkfd-Report-domain-with-topology.patch
new file mode 100644
index 00000000..5b2728f2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3481-drm-amdkfd-Report-domain-with-topology.patch
@@ -0,0 +1,55 @@
+From 3d055610d63e24e38636e16857aed8fd32dfc853 Mon Sep 17 00:00:00 2001
+From: Ori Messinger <Ori.Messinger@amd.com>
+Date: Wed, 21 Aug 2019 10:48:43 -0400
+Subject: [PATCH 3481/4256] drm/amdkfd: Report domain with topology
+
+PCI domain has moved to 32-bits to accommodate virtualization,
+so a 32-bit integer is exposed for domain to reflect this change.
+
+Domain can be found in here:
+/sys/class/kfd/kfd/topology/nodes/X/properties
+Where X is the card number
+
+Change-Id: I984a24bbc97832c983f7c5464f4b7996e79ddd35
+Signed-off-by: Ori Messinger <Ori.Messinger@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 3 +++
+ drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 1 +
+ 2 files changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+index 39ea6a104d63..c618c5595c4c 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+@@ -495,6 +495,8 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr,
+ 			dev->node_props.device_id);
+ 	sysfs_show_32bit_prop(buffer, "location_id",
+ 			dev->node_props.location_id);
++	sysfs_show_32bit_prop(buffer, "domain",
++			dev->node_props.domain);
+ 	sysfs_show_32bit_prop(buffer, "drm_render_minor",
+ 			dev->node_props.drm_render_minor);
+ 	sysfs_show_64bit_prop(buffer, "hive_id",
+@@ -1349,6 +1351,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
+ 	dev->node_props.device_id = gpu->pdev->device;
+ 	dev->node_props.location_id = PCI_DEVID(gpu->pdev->bus->number,
+ 		gpu->pdev->devfn);
++	dev->node_props.domain = pci_domain_nr(gpu->pdev->bus);
+ 	dev->node_props.max_engine_clk_fcompute =
+ 		amdgpu_amdkfd_get_max_engine_clock_in_mhz(dev->gpu->kgd);
+ 	dev->node_props.max_engine_clk_ccompute =
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
+index ba0c62084cc6..b5001785e371 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
+@@ -82,6 +82,7 @@ struct kfd_node_properties {
+ 	uint32_t vendor_id;
+ 	uint32_t device_id;
+ 	uint32_t location_id;
++	uint32_t domain;
+ 	uint32_t max_engine_clk_fcompute;
+ 	uint32_t max_engine_clk_ccompute;
+ 	int32_t  drm_render_minor;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3482-drm-amd-display-Check-return-code-for-CRC-drm_crtc_v.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3482-drm-amd-display-Check-return-code-for-CRC-drm_crtc_v.patch
new file mode 100644
index 00000000..f95d11f6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3482-drm-amd-display-Check-return-code-for-CRC-drm_crtc_v.patch
@@ -0,0 +1,55 @@
+From 8d7a3ec3354df8a293c4c2ab1a6462afdef8e7b3 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 20 Aug 2019 12:58:37 -0400
+Subject: [PATCH 3482/4256] drm/amd/display: Check return code for CRC
+ drm_crtc_vblank_get
+
+[Why]
+The call to drm_crtc_vblank_get can fail if vblank is disabled and
+we try to increment the reference.
+
+Since drm_crtc_vblank_get internally drops the reference when it fails
+it means the subsequent drm_crtc_vblank_put(...) when closing the file
+drops a zero reference.
+
+This was found via igt@kms_plane@pixel-format-pipe-A-planes.
+
+[How]
+Check the return code and return it on failure.
+
+We wouldn't have been able to enable CRC reading anyway since vblank
+wasn't enabled.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: David Francis <David.Francis@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+index e9a2c432e4d0..54c754524d68 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+@@ -106,6 +106,7 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+ 	struct drm_dp_aux *aux = NULL;
+ 	bool enable = false;
+ 	bool enabled = false;
++	int ret;
+ 
+ 	enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
+ 
+@@ -177,7 +178,10 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+ 	 */
+ 	enabled = amdgpu_dm_is_valid_crc_source(crtc_state->crc_src);
+ 	if (!enabled && enable) {
+-		drm_crtc_vblank_get(crtc);
++		ret = drm_crtc_vblank_get(crtc);
++		if (ret)
++			return ret;
++
+ 		if (dm_is_crc_source_dprx(source)) {
+ 			if (drm_dp_start_crc(aux, crtc)) {
+ 				DRM_DEBUG_DRIVER("dp start crc failed\n");
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3483-drm-amd-display-Use-connector-list-for-finding-DPRX-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3483-drm-amd-display-Use-connector-list-for-finding-DPRX-.patch
new file mode 100644
index 00000000..c1757bc7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3483-drm-amd-display-Use-connector-list-for-finding-DPRX-.patch
@@ -0,0 +1,61 @@
+From 30cb2f6c583651634c6a7a44c9c0d83f821c7577 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 20 Aug 2019 10:10:08 -0400
+Subject: [PATCH 3483/4256] drm/amd/display: Use connector list for finding
+ DPRX CRC aux
+
+[Why]
+This change is a refactor in preparation for adding locking and removing
+the requirement for a stream state on the CRTC for enabling CRC capture
+to fix igt@kms_plane_multiple@* warnings.
+
+[How]
+We can get the aux by finding the matching connector for the CRTC
+with the assumption that we're not doing cloning.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: David Francis <David.Francis@amd.com>
+---
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 19 +++++++++++++++----
+ 1 file changed, 15 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+index 54c754524d68..422d9ac3b83d 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+@@ -102,7 +102,6 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+ 	struct amdgpu_device *adev = crtc->dev->dev_private;
+ 	struct dm_crtc_state *crtc_state = to_dm_crtc_state(crtc->state);
+ 	struct dc_stream_state *stream_state = crtc_state->stream;
+-	struct amdgpu_dm_connector *aconn;
+ 	struct drm_dp_aux *aux = NULL;
+ 	bool enable = false;
+ 	bool enabled = false;
+@@ -139,9 +138,21 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+          * DPRX DITHER  | XXXX        | Enable DPRX CRC, need 'aux', set dither
+          */
+ 	if (dm_is_crc_source_dprx(source) ||
+-                (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE &&
+-		 dm_is_crc_source_dprx(crtc_state->crc_src))) {
+-                aconn = stream_state->link->priv;
++            (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE &&
++             dm_is_crc_source_dprx(crtc_state->crc_src))) {
++                struct amdgpu_dm_connector *aconn = NULL;
++                struct drm_connector *connector;
++                struct drm_connector_list_iter conn_iter;
++
++                drm_connector_list_iter_begin(crtc->dev, &conn_iter);
++                drm_for_each_connector_iter(connector, &conn_iter) {
++                        if (!connector->state || connector->state->crtc != crtc)
++                                continue;
++
++                        aconn = to_amdgpu_dm_connector(connector);
++                        break;
++                }
++                drm_connector_list_iter_end(&conn_iter);
+ 
+                 if (!aconn) {
+                         DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3484-drm-amd-display-Split-out-DC-programming-for-CRC-cap.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3484-drm-amd-display-Split-out-DC-programming-for-CRC-cap.patch
new file mode 100644
index 00000000..ba763291
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3484-drm-amd-display-Split-out-DC-programming-for-CRC-cap.patch
@@ -0,0 +1,213 @@
+From d91c8aa3df7acd7c4b51cc926c7bc45f9b4a7781 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 20 Aug 2019 10:16:14 -0400
+Subject: [PATCH 3484/4256] drm/amd/display: Split out DC programming for CRC
+ capture
+
+[Why]
+Calling amdgpu_dm_crtc_set_crc_source in amdgpu_dm directly has the
+consequence of adding additional vblank references or starting DPRX
+CRC capture more than once without calling stop first.
+
+Vblank references for CRC capture should be managed entirely by opening
+and closing the CRC file from userspace.
+
+Stream state also shouldn't be required on the CRC so we can close the
+file after the CRTC has been disabled.
+
+[How]
+Do DC programming required for configuring CRC capture separately from
+setting the source. Whenever we re-enable or reset a CRC this
+programming should be reapplied.
+
+CRC vblank reference handling in amdgpu_dm can be entirely dropped after
+this.
+
+Stream state also no longer needs to be required since we can just defer
+the programming to when the stream is actually enabled.
+
+Change-Id: Icc9a42f2e91cf2873704b45fbff4694a457219e5
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: David Francis <David.Francis@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 25 ++------
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 63 ++++++++++++-------
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h |  6 ++
+ 3 files changed, 49 insertions(+), 45 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 474eb6849dc7..76708b620892 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -5982,11 +5982,9 @@ static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev,
+ 		/* The stream has changed so CRC capture needs to re-enabled. */
+                 source = dm_new_crtc_state->crc_src;
+                 if (amdgpu_dm_is_valid_crc_source(source)) {
+-                        dm_new_crtc_state->crc_src = AMDGPU_DM_PIPE_CRC_SOURCE_NONE;
+-                        if (source == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC)
+-                                amdgpu_dm_crtc_set_crc_source(crtc, "crtc");
+-                        else if (source == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX)
+-                                amdgpu_dm_crtc_set_crc_source(crtc, "dprx");
++			amdgpu_dm_crtc_configure_crc_source(
++					crtc, dm_new_crtc_state,
++					dm_new_crtc_state->crc_src);
+ 		}
+ #endif
+ 	}
+@@ -6037,23 +6035,8 @@ static int amdgpu_dm_atomic_commit(struct drm_device *dev,
+ 
+                 if (dm_old_crtc_state->interrupts_enabled &&
+                     (!dm_new_crtc_state->interrupts_enabled ||
+-                     drm_atomic_crtc_needs_modeset(new_crtc_state))) {
+-			/*
+-                         * Drop the extra vblank reference added by CRC
+-                         * capture if applicable.
+-                         */
+-			if (amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src))
+-                                drm_crtc_vblank_put(crtc);
+-
+-                        /*
+-                         * Only keep CRC capture enabled if there's
+-                         * still a stream for the CRTC.
+-                         */
+-                        if (!dm_new_crtc_state->stream)
+-				dm_new_crtc_state->crc_src = AMDGPU_DM_PIPE_CRC_SOURCE_NONE;
+-
++		     drm_atomic_crtc_needs_modeset(new_crtc_state)))
+ 			manage_dm_interrupts(adev, acrtc, false);
+-		}
+ 	}
+ 	/* Add check here for SoC's that support hardware cursor plane, to
+ 	 * unset legacy_cursor_update */
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+index 422d9ac3b83d..d2099d649028 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+@@ -97,11 +97,47 @@ amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
+ 	return 0;
+ }
+ 
++int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
++                                        struct dm_crtc_state *dm_crtc_state,
++                                        enum amdgpu_dm_pipe_crc_source source)
++{
++        struct amdgpu_device *adev = crtc->dev->dev_private;
++        struct dc_stream_state *stream_state = dm_crtc_state->stream;
++        bool enable = amdgpu_dm_is_valid_crc_source(source);
++        int ret = 0;
++
++        /* Configuration will be deferred to stream enable. */
++        if (!stream_state)
++                return 0;
++
++        mutex_lock(&adev->dm.dc_lock);
++
++        /* Enable CRTC CRC generation if necessary. */
++        if (dm_is_crc_source_crtc(source)) {
++                if (!dc_stream_configure_crc(stream_state->ctx->dc,
++                                             stream_state, enable, enable)) {
++                        ret = -EINVAL;
++                        goto unlock;
++                }
++        }
++
++        /* Configure dithering */
++        if (!dm_need_crc_dither(source))
++                dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8);
++        else
++                dc_stream_set_dither_option(stream_state,
++                                            DITHER_OPTION_DEFAULT);
++
++unlock:
++        mutex_unlock(&adev->dm.dc_lock);
++
++        return ret;
++}
++
+ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+ {
+ 	struct amdgpu_device *adev = crtc->dev->dev_private;
+ 	struct dm_crtc_state *crtc_state = to_dm_crtc_state(crtc->state);
+-	struct dc_stream_state *stream_state = crtc_state->stream;
+ 	struct drm_dp_aux *aux = NULL;
+ 	bool enable = false;
+ 	bool enabled = false;
+@@ -115,15 +151,8 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+ 		return -EINVAL;
+ 	}
+ 
+-	if (!stream_state) {
+-		DRM_ERROR("No stream state for CRTC%d\n", crtc->index);
+-		return -EINVAL;
+-	}
+-
+ 	enable = amdgpu_dm_is_valid_crc_source(source);
+ 
+-	mutex_lock(&adev->dm.dc_lock);
+-
+         /*
+          * USER REQ SRC | CURRENT SRC | BEHAVIOR
+          * -----------------------------
+@@ -156,7 +185,6 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+ 
+                 if (!aconn) {
+                         DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index);
+-                        mutex_unlock(&adev->dm.dc_lock);
+                         return -EINVAL;
+                 }
+ 
+@@ -164,25 +192,12 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+ 
+                 if (!aux) {
+                         DRM_DEBUG_DRIVER("No dp aux for amd connector\n");
+-                        mutex_unlock(&adev->dm.dc_lock);
+-                        return -EINVAL;
+-                }
+-	} else if (dm_is_crc_source_crtc(source)) {
+-                if (!dc_stream_configure_crc(stream_state->ctx->dc, stream_state,
+-                                             enable, enable)) {
+-                        mutex_unlock(&adev->dm.dc_lock);
+                         return -EINVAL;
+                 }
+         }
+ 
+-        /* configure dithering */
+-        if (!dm_need_crc_dither(source))
+-                dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8);
+-        else if (!dm_need_crc_dither(crtc_state->crc_src))
+-                dc_stream_set_dither_option(stream_state, DITHER_OPTION_DEFAULT);
+-
+-	mutex_unlock(&adev->dm.dc_lock);
+-
++	if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source))
++		return -EINVAL;
+ 	/*
+ 	 * Reading the CRC requires the vblank interrupt handler to be
+ 	 * enabled. Keep a reference until CRC capture stops.
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
+index 14de7301c28d..cc415ecc2c1a 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
+@@ -26,6 +26,9 @@
+ #ifndef AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
+ #define AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
+ 
++struct drm_crtc;
++struct dm_crtc_state;
++
+ enum amdgpu_dm_pipe_crc_source {
+ 	AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
+ 	AMDGPU_DM_PIPE_CRC_SOURCE_CRTC,
+@@ -44,6 +47,9 @@ static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source
+ 
+ /* amdgpu_dm_crc.c */
+ #ifdef CONFIG_DEBUG_FS
++int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
++                                        struct dm_crtc_state *dm_crtc_state,
++                                        enum amdgpu_dm_pipe_crc_source source);
+ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
+ int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
+ 				     const char *src_name,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3485-drm-amd-display-Lock-the-CRTC-when-setting-CRC-sourc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3485-drm-amd-display-Lock-the-CRTC-when-setting-CRC-sourc.patch
new file mode 100644
index 00000000..be6012ad
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3485-drm-amd-display-Lock-the-CRTC-when-setting-CRC-sourc.patch
@@ -0,0 +1,156 @@
+From 2337db2b3bc16f762b86c51ee50660c58b2c5135 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 20 Aug 2019 13:15:25 -0400
+Subject: [PATCH 3485/4256] drm/amd/display: Lock the CRTC when setting CRC
+ source
+
+[Why]
+We need to ensure that we're holding the lock on the CRTC when setting
+the CRC source since we're modifying the CRTC state directly.
+
+We also need to wait for any outstanding non-blocking commits to finish
+so they aren't reading state that's potentially being modified -
+non-blocking commits don't hold the CRTC lock while doing commit tail
+work.
+
+[How]
+Lock the CRTC using its mutex. While holding the lock check if there's
+any commit active on the CRTC - if there is, it's non-blocking and
+we should wait until it's finished by waiting for hw_done to be
+signaled since that's the last point where we touch CRTC state.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: David Francis <David.Francis@amd.com>
+---
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 63 +++++++++++++++----
+ 1 file changed, 51 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+index d2099d649028..fa8e2c3ddf9d 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+@@ -137,13 +137,13 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
+ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+ {
+ 	struct amdgpu_device *adev = crtc->dev->dev_private;
+-	struct dm_crtc_state *crtc_state = to_dm_crtc_state(crtc->state);
++	enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
++        struct drm_crtc_commit *commit;
++        struct dm_crtc_state *crtc_state;
+ 	struct drm_dp_aux *aux = NULL;
+ 	bool enable = false;
+ 	bool enabled = false;
+-	int ret;
+-
+-	enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
++	int ret = 0;
+ 
+ 	if (source < 0) {
+ 		DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
+@@ -151,7 +151,33 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+ 		return -EINVAL;
+ 	}
+ 
++	ret = drm_modeset_lock(&crtc->mutex, NULL);
++	if (ret)
++		return ret;
++
++	spin_lock(&crtc->commit_lock);
++	commit = list_first_entry_or_null(&crtc->commit_list,
++					  struct drm_crtc_commit, commit_entry);
++	if (commit)
++		drm_crtc_commit_get(commit);
++	spin_unlock(&crtc->commit_lock);
++
++	if (commit) {
++		/*
++		 * Need to wait for all outstanding programming to complete
++		 * in commit tail since it can modify CRC related fields and
++		 * hardware state. Since we're holding the CRTC lock we're
++		 * guaranteed that no other commit work can be queued off
++		 * before we modify the state below.
++		 */
++		ret = wait_for_completion_interruptible_timeout(
++			&commit->hw_done, 10 * HZ);
++		if (ret)
++			goto cleanup;
++	}
++
+ 	enable = amdgpu_dm_is_valid_crc_source(source);
++	crtc_state = to_dm_crtc_state(crtc->state);
+ 
+         /*
+          * USER REQ SRC | CURRENT SRC | BEHAVIOR
+@@ -185,19 +211,23 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+ 
+                 if (!aconn) {
+                         DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index);
+-                        return -EINVAL;
++                        ret = -EINVAL;
++			goto cleanup;
+                 }
+ 
+                 aux = &aconn->dm_dp_aux.aux;
+ 
+                 if (!aux) {
+                         DRM_DEBUG_DRIVER("No dp aux for amd connector\n");
+-                        return -EINVAL;
++                        ret = -EINVAL;
++			goto cleanup;
+                 }
+         }
+ 
+-	if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source))
+-		return -EINVAL;
++	if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) {
++		ret = -EINVAL;
++		goto cleanup;
++	}
+ 	/*
+ 	 * Reading the CRC requires the vblank interrupt handler to be
+ 	 * enabled. Keep a reference until CRC capture stops.
+@@ -206,12 +236,13 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+ 	if (!enabled && enable) {
+ 		ret = drm_crtc_vblank_get(crtc);
+ 		if (ret)
+-			return ret;
++			goto cleanup;
+ 
+ 		if (dm_is_crc_source_dprx(source)) {
+ 			if (drm_dp_start_crc(aux, crtc)) {
+ 				DRM_DEBUG_DRIVER("dp start crc failed\n");
+-				return -EINVAL;
++				ret = -EINVAL;
++				goto cleanup;
+ 			}
+ 		}
+ 	} else if (enabled && !enable) {
+@@ -219,7 +250,8 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+ 		if (dm_is_crc_source_dprx(source)) {
+ 			if (drm_dp_stop_crc(aux)) {
+ 				DRM_DEBUG_DRIVER("dp stop crc failed\n");
+-				return -EINVAL;
++				ret = -EINVAL;
++				goto cleanup;
+ 			}
+ 		}
+ 	}
+@@ -228,7 +260,14 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
+ 
+ 	/* Reset crc_skipped on dm state */
+ 	crtc_state->crc_skip_count = 0;
+-	return 0;
++
++cleanup:
++	if (commit)
++		drm_crtc_commit_put(commit);
++
++	drm_modeset_unlock(&crtc->mutex);
++
++	return ret;
+ }
+ 
+ /**
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3486-drm-amdgpu-prevent-memory-leaks-in-AMDGPU_CS-ioctl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3486-drm-amdgpu-prevent-memory-leaks-in-AMDGPU_CS-ioctl.patch
new file mode 100644
index 00000000..e83d45e6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3486-drm-amdgpu-prevent-memory-leaks-in-AMDGPU_CS-ioctl.patch
@@ -0,0 +1,55 @@
+From cfc32ce2925ac6d13c10913c514efaecedb2ecff Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= <nicolai.haehnle@amd.com>
+Date: Tue, 20 Aug 2019 15:39:53 +0200
+Subject: [PATCH 3486/4256] drm/amdgpu: prevent memory leaks in AMDGPU_CS ioctl
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Error out if the AMDGPU_CS ioctl is called with multiple SYNCOBJ_OUT and/or
+TIMELINE_SIGNAL chunks, since otherwise the last chunk wins while the
+allocated array as well as the reference counts of sync objects are leaked.
+
+Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+index e745432315be..e06702390278 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+@@ -1130,6 +1130,9 @@ static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
+ 	num_deps = chunk->length_dw * 4 /
+ 		sizeof(struct drm_amdgpu_cs_chunk_sem);
+ 
++	if (p->post_deps)
++		return -EINVAL;
++
+ 	p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
+ 				     GFP_KERNEL);
+ 	p->num_post_deps = 0;
+@@ -1153,8 +1156,7 @@ static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
+ 
+ 
+ static int amdgpu_cs_process_syncobj_timeline_out_dep(struct amdgpu_cs_parser *p,
+-						      struct amdgpu_cs_chunk
+-						      *chunk)
++						      struct amdgpu_cs_chunk *chunk)
+ {
+ 	struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
+ 	unsigned num_deps;
+@@ -1164,6 +1166,9 @@ static int amdgpu_cs_process_syncobj_timeline_out_dep(struct amdgpu_cs_parser *p
+ 	num_deps = chunk->length_dw * 4 /
+ 		sizeof(struct drm_amdgpu_cs_chunk_syncobj);
+ 
++	if (p->post_deps)
++		return -EINVAL;
++
+ 	p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
+ 				     GFP_KERNEL);
+ 	p->num_post_deps = 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3487-drm-amd-display-Calculate-bpc-based-on-max_requested.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3487-drm-amd-display-Calculate-bpc-based-on-max_requested.patch
new file mode 100644
index 00000000..1e3da675
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3487-drm-amd-display-Calculate-bpc-based-on-max_requested.patch
@@ -0,0 +1,43 @@
+From a1261bed085d28247ce6977e0f94b3f7a00c3440 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Wed, 21 Aug 2019 11:27:13 -0400
+Subject: [PATCH 3487/4256] drm/amd/display: Calculate bpc based on
+ max_requested_bpc
+
+[Why]
+The only place where state->max_bpc is updated on the connector is
+at the start of atomic check during drm_atomic_connector_check. It
+isn't updated when adding the connectors to the atomic state after
+the fact. It also doesn't necessarily reflect the right value when
+called in amdgpu during mode validation outside of atomic check.
+
+This can cause the wrong bpc to be used even if the max_requested_bpc
+is the correct value.
+
+[How]
+Don't rely on state->max_bpc reflecting the real bpc value and just
+do the min(...) based on display info bpc and max_requested_bpc.
+
+Fixes: 01933ba42d3d ("drm/amd/display: Use current connector state if NULL when checking bpc")
+Change-Id: Ic8ff6beaf00dd6c2b9dd82bc503e5c7ce281ed1b
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
+index cc415ecc2c1a..48fd259cd33f 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
+@@ -58,6 +58,7 @@ const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
+ 						  size_t *count);
+ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
+ #else
++#define amdgpu_dm_crtc_configure_crc_source NULL
+ #define amdgpu_dm_crtc_set_crc_source NULL
+ #define amdgpu_dm_crtc_verify_crc_source NULL
+ #define amdgpu_dm_crtc_get_crc_sources NULL
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3488-drm-amd-display-Fix-32-bit-divide-error-in-wait_for_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3488-drm-amd-display-Fix-32-bit-divide-error-in-wait_for_.patch
new file mode 100644
index 00000000..277166e7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3488-drm-amd-display-Fix-32-bit-divide-error-in-wait_for_.patch
@@ -0,0 +1,52 @@
+From 8afef59a7782d448a790d34394d6ee6ba1b86006 Mon Sep 17 00:00:00 2001
+From: Nathan Chancellor <natechancellor@gmail.com>
+Date: Tue, 20 Aug 2019 16:57:13 -0700
+Subject: [PATCH 3488/4256] drm/amd/display: Fix 32-bit divide error in
+ wait_for_alt_mode
+
+When building arm32 allyesconfig:
+
+ld.lld: error: undefined symbol: __aeabi_uldivmod
+>>> referenced by dc_link.c
+>>> gpu/drm/amd/display/dc/core/dc_link.o:(wait_for_alt_mode) in archive drivers/built-in.a
+>>> referenced by dc_link.c
+>>> gpu/drm/amd/display/dc/core/dc_link.o:(wait_for_alt_mode) in archive drivers/built-in.a
+
+time_taken_in_ns is of type unsigned long long so we need to use div_u64
+to avoid this error.
+
+Fixes: b5b1f4554904 ("drm/amd/display: Enable type C hotplug")
+Reported-by: Randy Dunlap <rdunlap@infradead.org>
+Acked-by: Randy Dunlap <rdunlap@infradead.org> # build-tested
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index c953f6d2770a..8ec4fa3ed675 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -719,7 +719,7 @@ bool wait_for_alt_mode(struct dc_link *link)
+ 			time_taken_in_ns = dm_get_elapse_time_in_ns(
+ 				link->ctx, finish_timestamp, enter_timestamp);
+ 			DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
+-				       time_taken_in_ns / 1000000);
++				       div_u64(time_taken_in_ns, 1000000));
+ 			return true;
+ 		}
+ 
+@@ -728,7 +728,7 @@ bool wait_for_alt_mode(struct dc_link *link)
+ 	time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
+ 						    enter_timestamp);
+ 	DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
+-			time_taken_in_ns / 1000000);
++			div_u64(time_taken_in_ns, 1000000));
+ 	return false;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3489-drm-amdgpu-remove-set-but-not-used-variable-psp_enab.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3489-drm-amdgpu-remove-set-but-not-used-variable-psp_enab.patch
new file mode 100644
index 00000000..cb65a4b3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3489-drm-amdgpu-remove-set-but-not-used-variable-psp_enab.patch
@@ -0,0 +1,47 @@
+From 67014dea2f04c2140b77d664010c75288c44b6ec Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Thu, 27 Jun 2019 07:53:50 +0000
+Subject: [PATCH 3489/4256] drm/amdgpu: remove set but not used variable
+ 'psp_enabled'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/nv.c: In function 'nv_common_early_init':
+drivers/gpu/drm/amd/amdgpu/nv.c:471:7: warning:
+ variable 'psp_enabled' set but not used [-Wunused-but-set-variable]
+
+It's not used since inroduction in
+commit c6b6a42175f5 ("drm/amdgpu: add navi10 common ip block (v3)")
+
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 5 -----
+ 1 file changed, 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 46f402a52408..a3d99f2ddf6b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -575,7 +575,6 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
+ 
+ static int nv_common_early_init(void *handle)
+ {
+-	bool psp_enabled = false;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
+ 	adev->smc_rreg = NULL;
+@@ -592,10 +591,6 @@ static int nv_common_early_init(void *handle)
+ 
+ 	adev->asic_funcs = &nv_asic_funcs;
+ 
+-	if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) &&
+-	    (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
+-		psp_enabled = true;
+-
+ 	adev->rev_id = nv_get_rev_id(adev);
+ 	adev->external_rev_id = 0xff;
+ 	switch (adev->asic_type) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3490-drm-amdgpu-remove-duplicated-include-from-gfx_v9_0.c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3490-drm-amdgpu-remove-duplicated-include-from-gfx_v9_0.c.patch
new file mode 100644
index 00000000..af1f5379
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3490-drm-amdgpu-remove-duplicated-include-from-gfx_v9_0.c.patch
@@ -0,0 +1,29 @@
+From 52ac59205487e178749aed68e89ff1aaf53e9ff9 Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Wed, 10 Jul 2019 01:57:20 +0000
+Subject: [PATCH 3490/4256] drm/amdgpu: remove duplicated include from
+ gfx_v9_0.c
+
+Remove duplicated include.
+
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 155a8699adb8..2a43ec2f7bad 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -36,7 +36,6 @@
+ #include "vega10_enum.h"
+ #include "hdp/hdp_4_0_offset.h"
+ 
+-#include "soc15.h"
+ #include "soc15_common.h"
+ #include "clearstate_gfx9.h"
+ #include "v9_structs.h"
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3491-drm-amd-display-remove-duplicated-include-from-dc_li.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3491-drm-amd-display-remove-duplicated-include-from-dc_li.patch
new file mode 100644
index 00000000..b597e6e6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3491-drm-amd-display-remove-duplicated-include-from-dc_li.patch
@@ -0,0 +1,33 @@
+From 90d395d8de946fd902a81f22205e9a841d3398c5 Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Fri, 26 Jul 2019 15:51:31 +0800
+Subject: [PATCH 3491/4256] drm/amd/display: remove duplicated include from
+ dc_link.c
+
+Remove duplicated include.
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 8ec4fa3ed675..0ccf0cd0a44d 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -43,10 +43,6 @@
+ #include "dpcd_defs.h"
+ #include "dmcu.h"
+ #include "hw/clk_mgr.h"
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+-#include "resource.h"
+-#endif
+-#include "hw/clk_mgr.h"
+ 
+ #define DC_LOGGER_INIT(logger)
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3492-drm-amdkfd-remove-set-but-not-used-variable-pdd.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3492-drm-amdkfd-remove-set-but-not-used-variable-pdd.patch
new file mode 100644
index 00000000..49a6bec9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3492-drm-amdkfd-remove-set-but-not-used-variable-pdd.patch
@@ -0,0 +1,55 @@
+From 6a910457afbbc7b3f3c098da67b8412e37721174 Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Fri, 26 Jul 2019 22:00:54 +0800
+Subject: [PATCH 3492/4256] drm/amdkfd: remove set but not used variable 'pdd'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.c: In function restore_process_worker:
+drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.c:949:29: warning:
+ variable pdd set but not used [-Wunused-but-set-variable]
+
+It is not used since
+commit 5b87245faf57 ("drm/amdkfd: Simplify kfd2kgd interface")
+
+Change-Id: Ie7fcd56d6ce44f753d1bebb7e93fc40a8a763447
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 11 +----------
+ 1 file changed, 1 insertion(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+index 04a621a76822..9446cc45d80f 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+@@ -1297,7 +1297,6 @@ static void restore_process_worker(struct work_struct *work)
+ {
+ 	struct delayed_work *dwork;
+ 	struct kfd_process *p;
+-	struct kfd_process_device *pdd;
+ 	int ret = 0;
+ 
+ 	dwork = to_delayed_work(work);
+@@ -1306,16 +1305,8 @@ static void restore_process_worker(struct work_struct *work)
+ 	 * lifetime of this thread, kfd_process p will be valid
+ 	 */
+ 	p = container_of(dwork, struct kfd_process, restore_work);
+-	trace_kfd_restore_process_worker_start(p);
+ 
+-	/* Call restore_process_bos on the first KGD device. This function
+-	 * takes care of restoring the whole process including other devices.
+-	 * Restore can fail if enough memory is not available. If so,
+-	 * reschedule again.
+-	 */
+-	pdd = list_first_entry(&p->per_device_data,
+-			       struct kfd_process_device,
+-			       per_device_list);
++	trace_kfd_restore_process_worker_start(p);
+ 
+ 	pr_info("Started restoring pasid %d\n", p->pasid);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3493-drm-amdgpu-disable-agp-for-sriov.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3493-drm-amdgpu-disable-agp-for-sriov.patch
new file mode 100644
index 00000000..e82e8487
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3493-drm-amdgpu-disable-agp-for-sriov.patch
@@ -0,0 +1,53 @@
+From 16437e94cede603eba9fa11622aaacc30c7c4e21 Mon Sep 17 00:00:00 2001
+From: "Frank.Min" <Frank.Min@amd.com>
+Date: Wed, 21 Aug 2019 17:20:34 +0800
+Subject: [PATCH 3493/4256] drm/amdgpu: disable agp for sriov
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Since agp is not used for sriov, just disable it
+
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Frank.Min <Frank.Min@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 8 ++++++++
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 3 +--
+ 2 files changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+index 250d9212cc38..6094990dcbee 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+@@ -218,6 +218,14 @@ void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
+ 	const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1);
+ 	u64 size_af, size_bf;
+ 
++	if (amdgpu_sriov_vf(adev)) {
++		mc->agp_start = 0xffffffff;
++		mc->agp_end = 0x0;
++		mc->agp_size = 0;
++
++		return;
++	}
++
+ 	if (mc->fb_start > mc->gart_start) {
+ 		size_bf = (mc->fb_start & sixteen_gb_mask) -
+ 			ALIGN(mc->gart_end + 1, sixteen_gb);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index cfb3273bc07f..ec962ab50b1f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -926,8 +926,7 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
+ 	base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
+ 	amdgpu_gmc_vram_location(adev, mc, base);
+ 	amdgpu_gmc_gart_location(adev, mc);
+-	if (!amdgpu_sriov_vf(adev))
+-		amdgpu_gmc_agp_location(adev, mc);
++	amdgpu_gmc_agp_location(adev, mc);
+ 	/* base offset of vram pages */
+ 	adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3494-drm-amdgpu-unity-mc-base-address-for-arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3494-drm-amdgpu-unity-mc-base-address-for-arcturus.patch
new file mode 100644
index 00000000..40f0b28e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3494-drm-amdgpu-unity-mc-base-address-for-arcturus.patch
@@ -0,0 +1,42 @@
+From 5a77fa814feccb5282546b944ea415fd4feb7ad0 Mon Sep 17 00:00:00 2001
+From: "Frank.Min" <Frank.Min@amd.com>
+Date: Wed, 21 Aug 2019 11:05:04 +0800
+Subject: [PATCH 3494/4256] drm/amdgpu: unity mc base address for arcturus
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+arcturus for sriov would use the unified mc base address
+
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Frank.Min <Frank.Min@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index ec962ab50b1f..746aedb7fb99 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -916,12 +916,12 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
+ 					struct amdgpu_gmc *mc)
+ {
+ 	u64 base = 0;
+-	if (!amdgpu_sriov_vf(adev)) {
+-		if (adev->asic_type == CHIP_ARCTURUS)
+-			base = mmhub_v9_4_get_fb_location(adev);
+-		else
+-			base = mmhub_v1_0_get_fb_location(adev);
+-	}
++
++	if (adev->asic_type == CHIP_ARCTURUS)
++		base = mmhub_v9_4_get_fb_location(adev);
++	else if (!amdgpu_sriov_vf(adev))
++		base = mmhub_v1_0_get_fb_location(adev);
++
+ 	/* add the xgmi offset of the physical node */
+ 	base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
+ 	amdgpu_gmc_vram_location(adev, mc, base);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3495-amd-amdgpu-add-Arcturus-vf-DID-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3495-amd-amdgpu-add-Arcturus-vf-DID-support.patch
new file mode 100644
index 00000000..cbd1338a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3495-amd-amdgpu-add-Arcturus-vf-DID-support.patch
@@ -0,0 +1,26 @@
+From f82fca93fbc762a2126cdd329e5d7a9245def14f Mon Sep 17 00:00:00 2001
+From: "Frank.Min" <Frank.Min@amd.com>
+Date: Fri, 16 Aug 2019 15:07:32 +0800
+Subject: [PATCH 3495/4256] amd/amdgpu: add Arcturus vf DID support
+
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Frank.Min <Frank.Min@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 0db64bcbe22e..23fce40922e9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1037,6 +1037,7 @@ static const struct pci_device_id pciidlist[] = {
+ 	{0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
+ 	{0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
+ 	{0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
++	{0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
+ 	/* Navi10 */
+ 	{0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
+ 	{0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3496-drm-powerplay-Fix-Vega20-Average-Power-value-v4.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3496-drm-powerplay-Fix-Vega20-Average-Power-value-v4.patch
new file mode 100644
index 00000000..59f67215
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3496-drm-powerplay-Fix-Vega20-Average-Power-value-v4.patch
@@ -0,0 +1,68 @@
+From 62aa9820cac841649f67624a387420b8471f42d2 Mon Sep 17 00:00:00 2001
+From: Kent Russell <kent.russell@amd.com>
+Date: Thu, 22 Aug 2019 08:17:40 -0400
+Subject: [PATCH 3496/4256] drm/powerplay: Fix Vega20 Average Power value v4
+
+The SMU changed reading from CurrSocketPower to AverageSocketPower, so
+reflect this accordingly. This fixes the issue where Average Power
+Consumption was being reported as 0 from SMU 40.46-onward
+
+v2: Fixed headline prefix
+v3: Add check for SMU version for proper compatibility
+v4: Style fix
+
+Change-Id: I471f93316820f1401cb497eefe29da68376a4bb9
+Signed-off-by: Kent Russell <kent.russell@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c |  5 ++++-
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c         | 10 +++++++++-
+ 2 files changed, 13 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+index 0516c294b377..9f50a12f5c03 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+@@ -2101,7 +2101,10 @@ static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
+ 	if (ret)
+ 		return ret;
+ 
+-	*query = metrics_table.CurrSocketPower << 8;
++	if (hwmgr->smu_version < 0x282e00)
++		*query = metrics_table.CurrSocketPower << 8;
++	else
++		*query = metrics_table.AverageSocketPower << 8;
+ 
+ 	return ret;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index e14363182691..0fac824490d7 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -2917,6 +2917,7 @@ static int vega20_get_fan_speed_percent(struct smu_context *smu,
+ 
+ static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)
+ {
++	uint32_t smu_version;
+ 	int ret = 0;
+ 	SmuMetrics_t metrics;
+ 
+@@ -2927,7 +2928,14 @@ static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)
+ 	if (ret)
+ 		return ret;
+ 
+-	*value = metrics.CurrSocketPower << 8;
++	ret = smu_get_smc_version(smu, NULL, &smu_version);
++	if (ret)
++		return ret;
++
++	if (smu_version < 0x282e00)
++		*value = metrics.CurrSocketPower << 8;
++	else
++		*value = metrics.AverageSocketPower << 8;
+ 
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3497-Revert-drm-amd-display-skip-dsc-config-for-navi10-br.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3497-Revert-drm-amd-display-skip-dsc-config-for-navi10-br.patch
new file mode 100644
index 00000000..9a865cdb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3497-Revert-drm-amd-display-skip-dsc-config-for-navi10-br.patch
@@ -0,0 +1,50 @@
+From 7db61d72405847d0e2d5ba0e5fa1d43c8b81e68f Mon Sep 17 00:00:00 2001
+From: David Francis <David.Francis@amd.com>
+Date: Thu, 28 Mar 2019 13:52:00 -0400
+Subject: [PATCH 3497/4256] Revert "drm/amd/display: skip dsc config for navi10
+ bring up"
+
+This reverts commit 55ad81f3510ec1a1c19e6a4d8a6319812d07d256.
+
+optc dsc config was causing warnings due to missing register
+definitions. With the registers restored, the function can
+be re-enabled
+
+The reverted commit also disabled sanity checks and dsc
+power gating. The sanity check warnings are not associated
+with dsc, and power gating on dsc still has an issue on
+non-dsc monitors where the dsc hardware block is never init
+and so cannot respond to power gating requests. Therefore,
+those are left as is
+
+Signed-off-by: David Francis <David.Francis@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 9 ---------
+ 1 file changed, 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+index aedf9de1c947..99070e93020b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+@@ -191,15 +191,6 @@ void optc2_set_dsc_config(struct timing_generator *optc,
+ 					uint32_t dsc_slice_width)
+ {
+ 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+-	uint32_t data_format = 0;
+-	/* skip if dsc mode is not changed */
+-	data_format = dm_read_reg(CTX, REG(OPTC_DATA_FORMAT_CONTROL));
+-
+-	data_format = data_format & 0x30; /* bit5:4 */
+-	data_format = data_format >> 4;
+-
+-	if (data_format == dsc_mode)
+-		return;
+ 
+ 	REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
+ 		OPTC_DSC_MODE, dsc_mode);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3498-drm-amdgpu-fix-dma_fence_wait-without-reference.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3498-drm-amdgpu-fix-dma_fence_wait-without-reference.patch
new file mode 100644
index 00000000..8813b00a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3498-drm-amdgpu-fix-dma_fence_wait-without-reference.patch
@@ -0,0 +1,60 @@
+From 00542cdf235ad60a9e54fc953814e137b95af2c4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Fri, 16 Aug 2019 14:56:35 +0200
+Subject: [PATCH 3498/4256] drm/amdgpu: fix dma_fence_wait without reference
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We need to grab a reference to the fence we wait for.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 27 ++++++++++++++-----------
+ 1 file changed, 15 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+index 54b9b955f12f..acd44860c7d5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+@@ -547,21 +547,24 @@ int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
+ 			       struct drm_sched_entity *entity)
+ {
+ 	struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity);
+-	unsigned idx = centity->sequence & (amdgpu_sched_jobs - 1);
+-	struct dma_fence *other = centity->fences[idx];
++	struct dma_fence *other;
++	unsigned idx;
++	long r;
+ 
+-	if (other) {
+-		signed long r;
+-		r = dma_fence_wait(other, true);
+-		if (r < 0) {
+-			if (r != -ERESTARTSYS)
+-				DRM_ERROR("Error (%ld) waiting for fence!\n", r);
++	spin_lock(&ctx->ring_lock);
++	idx = centity->sequence & (amdgpu_sched_jobs - 1);
++	other = dma_fence_get(centity->fences[idx]);
++	spin_unlock(&ctx->ring_lock);
+ 
+-			return r;
+-		}
+-	}
++	if (!other)
++		return 0;
+ 
+-	return 0;
++	r = dma_fence_wait(other, true);
++	if (r < 0 && r != -ERESTARTSYS)
++		DRM_ERROR("Error (%ld) waiting for fence!\n", r);
++
++	dma_fence_put(other);
++	return r;
+ }
+ 
+ void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3499-Revert-drm-amd-display-navi10-bring-up-skip-dsc-enco.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3499-Revert-drm-amd-display-navi10-bring-up-skip-dsc-enco.patch
new file mode 100644
index 00000000..feff95be
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3499-Revert-drm-amd-display-navi10-bring-up-skip-dsc-enco.patch
@@ -0,0 +1,42 @@
+From 077678abe5a4a68d53aeaea30c031e034962ef05 Mon Sep 17 00:00:00 2001
+From: David Francis <David.Francis@amd.com>
+Date: Thu, 28 Mar 2019 09:58:11 -0400
+Subject: [PATCH 3499/4256] Revert "drm/amd/display: navi10 bring up skip dsc
+ encoder config"
+
+This reverts commit 5f2fd347eeff7d4ce271920efd47baaa18fe968c.
+
+Re-enable enc2_dp_set_dsc_config. This function caused warnings
+due to missing register definitions. With the registers added,
+this now works
+
+Signed-off-by: David Francis <David.Francis@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c   | 8 --------
+ 1 file changed, 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+index 6d54942ab98b..a4e67286cdad 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+@@ -277,14 +277,6 @@ static void enc2_dp_set_dsc_config(struct stream_encoder *enc,
+ 					uint32_t dsc_slice_width)
+ {
+ 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+-	uint32_t dsc_value = 0;
+-
+-	dsc_value = REG_READ(DP_DSC_CNTL);
+-
+-	/* dsc disable skip */
+-	if ((dsc_value & 0x3) == 0x0)
+-		return;
+-
+ 
+ 	REG_UPDATE_2(DP_DSC_CNTL,
+ 			DP_DSC_MODE, dsc_mode,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3500-Revert-drm-amd-display-add-global-master-update-lock.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3500-Revert-drm-amd-display-add-global-master-update-lock.patch
new file mode 100644
index 00000000..8cd611e1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3500-Revert-drm-amd-display-add-global-master-update-lock.patch
@@ -0,0 +1,150 @@
+From 98da34992358a815deebf1e899d6f7915e7539f2 Mon Sep 17 00:00:00 2001
+From: David Francis <David.Francis@amd.com>
+Date: Thu, 23 May 2019 14:06:08 -0400
+Subject: [PATCH 3500/4256] Revert "drm/amd/display: add global master update
+ lock for DCN2"
+
+This reverts commit 55a6f5bbcf00a49565946c0a9b8c716313dc6c05.
+
+This commit was accidentally promoted twice
+
+Signed-off-by: David Francis <David.Francis@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  4 --
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 63 +------------------
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |  3 -
+ .../amd/display/dc/inc/hw/timing_generator.h  |  2 -
+ 4 files changed, 1 insertion(+), 71 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 75c670d4443a..abbae9fb8eff 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -811,10 +811,6 @@ enum dc_status dcn20_enable_stream_timing(
+ 			pipe_ctx->stream->signal,
+ 			true);
+ 
+-	if (pipe_ctx->stream_res.tg->funcs->setup_global_lock)
+-		pipe_ctx->stream_res.tg->funcs->setup_global_lock(
+-				pipe_ctx->stream_res.tg);
+-
+ 	if (odm_pipe)
+ 		odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
+ 				odm_pipe->stream_res.opp,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+index 99070e93020b..2137e2be2140 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+@@ -333,65 +333,6 @@ void optc2_triplebuffer_unlock(struct timing_generator *optc)
+ 
+ }
+ 
+-
+-void optc2_setup_global_lock(struct timing_generator *optc)
+-{
+-	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+-	uint32_t v_blank_start = 0;
+-	uint32_t h_blank_start = 0, h_total = 0;
+-
+-	REG_SET(OTG_GLOBAL_CONTROL1, 0, MASTER_UPDATE_LOCK_DB_EN, 1);
+-
+-	REG_SET(OTG_GLOBAL_CONTROL2, 0, DIG_UPDATE_LOCATION, 20);
+-
+-	REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start);
+-
+-	REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start);
+-
+-	REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &h_total);
+-	REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
+-			MASTER_UPDATE_LOCK_DB_X,
+-			h_blank_start - 200 - 1,
+-			MASTER_UPDATE_LOCK_DB_Y,
+-			v_blank_start - 1);
+-}
+-
+-void optc2_lock_global(struct timing_generator *optc)
+-{
+-	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+-
+-	REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1);
+-
+-	REG_SET(OTG_GLOBAL_CONTROL0, 0,
+-			OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
+-	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+-			OTG_MASTER_UPDATE_LOCK, 1);
+-
+-	/* Should be fast, status does not update on maximus */
+-	if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
+-		REG_WAIT(OTG_MASTER_UPDATE_LOCK,
+-				UPDATE_LOCK_STATUS, 1,
+-				1, 10);
+-}
+-
+-void optc2_lock(struct timing_generator *optc)
+-{
+-	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+-
+-	REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0);
+-
+-	REG_SET(OTG_GLOBAL_CONTROL0, 0,
+-			OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
+-	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+-			OTG_MASTER_UPDATE_LOCK, 1);
+-
+-	/* Should be fast, status does not update on maximus */
+-	if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
+-		REG_WAIT(OTG_MASTER_UPDATE_LOCK,
+-				UPDATE_LOCK_STATUS, 1,
+-				1, 10);
+-}
+-
+ void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
+ {
+ 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+@@ -486,10 +427,8 @@ static struct timing_generator_funcs dcn20_tg_funcs = {
+ 		.triplebuffer_lock = optc2_triplebuffer_lock,
+ 		.triplebuffer_unlock = optc2_triplebuffer_unlock,
+ 		.disable_reset_trigger = optc1_disable_reset_trigger,
+-		.lock = optc2_lock,
++		.lock = optc1_lock,
+ 		.unlock = optc1_unlock,
+-		.lock_global = optc2_lock_global,
+-		.setup_global_lock = optc2_setup_global_lock,
+ 		.lock_doublebuffer_enable = optc2_lock_doublebuffer_enable,
+ 		.lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
+ 		.enable_optc_clock = optc1_enable_optc_clock,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+index 47cb4de1564c..32a58431fd09 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+@@ -106,9 +106,6 @@ void optc2_get_optc_source(struct timing_generator *optc,
+ 
+ void optc2_triplebuffer_lock(struct timing_generator *optc);
+ void optc2_triplebuffer_unlock(struct timing_generator *optc);
+-void optc2_lock(struct timing_generator *optc);
+-void optc2_lock_global(struct timing_generator *optc);
+-void optc2_setup_global_lock(struct timing_generator *optc);
+ void optc2_lock_doublebuffer_disable(struct timing_generator *optc);
+ void optc2_lock_doublebuffer_enable(struct timing_generator *optc);
+ void optc2_program_manual_trigger(struct timing_generator *optc);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+index f607ef24c766..e0713d6d6c8d 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+@@ -189,10 +189,8 @@ struct timing_generator_funcs {
+ 	bool (*did_triggered_reset_occur)(struct timing_generator *tg);
+ 	void (*setup_global_swap_lock)(struct timing_generator *tg,
+ 							const struct dcp_gsl_params *gsl_params);
+-	void (*setup_global_lock)(struct timing_generator *tg);
+ 	void (*unlock)(struct timing_generator *tg);
+ 	void (*lock)(struct timing_generator *tg);
+-	void (*lock_global)(struct timing_generator *tg);
+ 	void (*lock_doublebuffer_disable)(struct timing_generator *tg);
+ 	void (*lock_doublebuffer_enable)(struct timing_generator *tg);
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3501-Revert-drm-amd-display-Fix-underscan-not-using-prope.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3501-Revert-drm-amd-display-Fix-underscan-not-using-prope.patch
new file mode 100644
index 00000000..1f720f20
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3501-Revert-drm-amd-display-Fix-underscan-not-using-prope.patch
@@ -0,0 +1,54 @@
+From 8a4a80171174b42ef9414e56a2a1698d225fc344 Mon Sep 17 00:00:00 2001
+From: David Francis <David.Francis@amd.com>
+Date: Thu, 23 May 2019 14:25:35 -0400
+Subject: [PATCH 3501/4256] Revert "drm/amd/display: Fix underscan not using
+ proper scaling"
+
+This reverts commit 80e80ec817f161560b4159608fb41bd289abede3.
+
+This commit fixed an issue with underscan commits not updating all
+needed timing values, but through various refactors it is no longer
+necessary. It causes corruption on odm combine by
+overwriting the halved h_active in the stream timing
+
+Signed-off-by: David Francis <David.Francis@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 12 +-----------
+ 1 file changed, 1 insertion(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 541c94fba481..af2586b5c238 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -2138,7 +2138,7 @@ void dc_commit_updates_for_stream(struct dc *dc,
+ 	enum surface_update_type update_type;
+ 	struct dc_state *context;
+ 	struct dc_context *dc_ctx = dc->ctx;
+-	int i, j;
++	int i;
+ 
+ 	stream_status = dc_stream_get_status(stream);
+ 	context = dc->current_state;
+@@ -2176,16 +2176,6 @@ void dc_commit_updates_for_stream(struct dc *dc,
+ 
+ 		copy_surface_update_to_plane(surface, &srf_updates[i]);
+ 
+-		if (update_type >= UPDATE_TYPE_MED) {
+-			for (j = 0; j < dc->res_pool->pipe_count; j++) {
+-				struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
+-
+-				if (pipe_ctx->plane_state != surface)
+-					continue;
+-
+-				resource_build_scaling_params(pipe_ctx);
+-			}
+-		}
+ 	}
+ 
+ 	copy_stream_update_to_stream(dc, context, stream, stream_update);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3502-drm-amd-display-Enable-SST-DSC-in-DM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3502-drm-amd-display-Enable-SST-DSC-in-DM.patch
new file mode 100644
index 00000000..330b423f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3502-drm-amd-display-Enable-SST-DSC-in-DM.patch
@@ -0,0 +1,88 @@
+From c08e0e873d9ba38c5882afbf3c99f209f5791361 Mon Sep 17 00:00:00 2001
+From: David Francis <David.Francis@amd.com>
+Date: Wed, 19 Jun 2019 14:30:59 -0400
+Subject: [PATCH 3502/4256] drm/amd/display: Enable SST DSC in DM
+
+In create_stream_for_sink, check for SST DP connectors
+
+Parse DSC caps to DC format, then, if DSC is supported,
+compute the config
+
+DSC hardware will be programmed by dc_commit_state
+
+Tested-by: Mikita Lipski <Mikita.Lipski@amd.com>
+Signed-off-by: David Francis <David.Francis@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 ++++++++++++-------
+ .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  4 ++-
+ 2 files changed, 24 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 76708b620892..4bec6ffb3940 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -3587,6 +3587,10 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ 	bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
+ 	int mode_refresh;
+ 	int preferred_refresh = 0;
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	struct dsc_dec_dpcd_caps dsc_caps;
++	uint32_t link_bandwidth_kbps;
++#endif
+ 
+ 	struct dc_sink *sink = NULL;
+ 	if (aconnector == NULL) {
+@@ -3658,17 +3662,23 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ 			&mode, &aconnector->base, con_state, old_stream);
+ 
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-	/* stream->timing.flags.DSC = 0; */
+-        /*  */
+-	/* if (aconnector->dc_link && */
+-	/* 		aconnector->dc_link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT #<{(|&& */
+-	/* 		aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.is_dsc_supported|)}>#) */
+-	/* 	if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc, */
+-	/* 			&aconnector->dc_link->dpcd_caps.dsc_caps, */
+-	/* 			dc_link_bandwidth_kbps(aconnector->dc_link, dc_link_get_link_cap(aconnector->dc_link)), */
+-	/* 			&stream->timing, */
+-	/* 			&stream->timing.dsc_cfg)) */
+-	/* 		stream->timing.flags.DSC = 1; */
++	stream->timing.flags.DSC = 0;
++
++	if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
++		dc_dsc_parse_dsc_dpcd(aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
++				      aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
++				      &dsc_caps);
++		link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
++							     dc_link_get_link_cap(aconnector->dc_link));
++
++		if (dsc_caps.is_dsc_supported)
++			if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc,
++						  &dsc_caps,
++						  link_bandwidth_kbps,
++						  &stream->timing,
++						  &stream->timing.dsc_cfg))
++				stream->timing.flags.DSC = 1;
++	}
+ #endif
+ 
+ 	update_stream_scaling_settings(&mode, dm_state, stream);
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+index 9f8597280814..9328882230d8 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+@@ -549,7 +549,9 @@ bool dm_helpers_dp_write_dsc_enable(
+ 		bool enable
+ )
+ {
+-	return false;
++	uint8_t enable_dsc = enable ? 1 : 0;
++
++	return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, &enable_dsc, 1);
+ }
+ #endif
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3503-drm-amdgpu-sdma5-fix-number-of-sdma5-trap-irq-types-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3503-drm-amdgpu-sdma5-fix-number-of-sdma5-trap-irq-types-.patch
new file mode 100644
index 00000000..3a6a2222
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3503-drm-amdgpu-sdma5-fix-number-of-sdma5-trap-irq-types-.patch
@@ -0,0 +1,43 @@
+From 132b291a63f30c18caf45ea6a6ced456fe8f2f4a Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 21 Aug 2019 21:00:29 +0800
+Subject: [PATCH 3503/4256] drm/amdgpu/sdma5: fix number of sdma5 trap irq
+ types for navi1x
+
+v2: set num_types based on num_instances
+
+navi1x has 2 sdma engines but commit
+"e7b58d03b678 drm/amdgpu: reorganize sdma v4 code to support more instances"
+changes the max number of sdma irq types (AMDGPU_SDMA_IRQ_LAST) from 2 to 8
+which causes amdgpu_irq_gpu_reset_resume_helper() to recover irq of sdma
+engines with following logic:
+
+(enable irq for sdma0) * 1 time
+(enable irq for sdma1) * 1 time
+(disable irq for sdma1) * 6 times
+
+as a result, after gpu reset, interrupt for sdma1 is lost.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+index 41932d8b88c3..89174e778d2f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+@@ -1625,7 +1625,8 @@ static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
+ 
+ static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
+ {
+-	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
++	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
++					adev->sdma.num_instances;
+ 	adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
+ 	adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3504-drm-amdkfd-Make-deallocate_hiq_sdma_mqd-static.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3504-drm-amdkfd-Make-deallocate_hiq_sdma_mqd-static.patch
new file mode 100644
index 00000000..afca020c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3504-drm-amdkfd-Make-deallocate_hiq_sdma_mqd-static.patch
@@ -0,0 +1,34 @@
+From 9ae8c4cb6255d95d42634a69e968268fc1761e8f Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Sat, 25 May 2019 20:51:09 +0800
+Subject: [PATCH 3504/4256] drm/amdkfd: Make deallocate_hiq_sdma_mqd static
+
+Fix sparse warning:
+
+drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.c:1846:6:
+ warning: symbol 'deallocate_hiq_sdma_mqd' was not declared. Should it be static?
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index d8418e6bec86..53862d66d065 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -1907,7 +1907,8 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
+ 	return NULL;
+ }
+ 
+-void deallocate_hiq_sdma_mqd(struct kfd_dev *dev, struct kfd_mem_obj *mqd)
++static void deallocate_hiq_sdma_mqd(struct kfd_dev *dev,
++				    struct kfd_mem_obj *mqd)
+ {
+ 	WARN(!mqd, "No hiq sdma mqd trunk to free");
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3505-drm-amdgpu-powerplay-remove-redundant-assignment-to-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3505-drm-amdgpu-powerplay-remove-redundant-assignment-to-.patch
new file mode 100644
index 00000000..46ec1a2a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3505-drm-amdgpu-powerplay-remove-redundant-assignment-to-.patch
@@ -0,0 +1,32 @@
+From 1c743ecb2edbb3f664bbf42d713390f9d2eca757 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Thu, 22 Aug 2019 14:09:48 +0100
+Subject: [PATCH 3505/4256] drm/amdgpu/powerplay: remove redundant assignment
+ to variable baco_state
+
+Variable baco_state is initialized to a value that is never read and it is
+re-assigned later. The initialization is redundant and can be removed.
+
+Addresses-Coverity: ("Unused Value")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index f5efe8b5e96c..62bfde0ab0ee 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1672,7 +1672,7 @@ static bool smu_v11_0_baco_is_support(struct smu_context *smu)
+ static enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
+ {
+ 	struct smu_baco_context *smu_baco = &smu->smu_baco;
+-	enum smu_baco_state baco_state = SMU_BACO_STATE_EXIT;
++	enum smu_baco_state baco_state;
+ 
+ 	mutex_lock(&smu_baco->mutex);
+ 	baco_state = smu_baco->state;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3506-drm-amdgpu-powerplay-silence-a-warning-in-smu_v11_0_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3506-drm-amdgpu-powerplay-silence-a-warning-in-smu_v11_0_.patch
new file mode 100644
index 00000000..5138051f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3506-drm-amdgpu-powerplay-silence-a-warning-in-smu_v11_0_.patch
@@ -0,0 +1,31 @@
+From dd50154ed1be847716ca799e7c1cc1b6dca3960c Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 21 Aug 2019 22:23:18 -0500
+Subject: [PATCH 3506/4256] drm/amdgpu/powerplay: silence a warning in
+ smu_v11_0_setup_pptable
+
+I think gcc is confused as I don't see how size could be used
+uninitialized, but go ahead and silence the warning.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 62bfde0ab0ee..1ec42903a250 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -359,7 +359,7 @@ static int smu_v11_0_setup_pptable(struct smu_context *smu)
+ 	struct amdgpu_device *adev = smu->adev;
+ 	const struct smc_firmware_header_v1_0 *hdr;
+ 	int ret, index;
+-	uint32_t size;
++	uint32_t size = 0;
+ 	uint16_t atom_table_size;
+ 	uint8_t frev, crev;
+ 	void *table;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3507-drm-amdgpu-powerplay-Add-smu_v12_0_ppsmc.h-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3507-drm-amdgpu-powerplay-Add-smu_v12_0_ppsmc.h-v2.patch
new file mode 100644
index 00000000..48a7919b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3507-drm-amdgpu-powerplay-Add-smu_v12_0_ppsmc.h-v2.patch
@@ -0,0 +1,130 @@
+From 373978ce8c848df1d02c210f0b9b073ec13558cd Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 25 Jul 2019 15:42:52 -0500
+Subject: [PATCH 3507/4256] drm/amdgpu/powerplay: Add smu_v12_0_ppsmc.h (v2)
+
+This is the SMU v12 driver message interface.
+
+v2: squash in updates
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/powerplay/inc/smu_v12_0_ppsmc.h   | 106 ++++++++++++++++++
+ 1 file changed, 106 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h
+new file mode 100644
+index 000000000000..9ac9f3bd3664
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h
+@@ -0,0 +1,106 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef SMU_12_0_PPSMC_H
++#define SMU_12_0_PPSMC_H
++
++// SMU Response Codes:
++#define PPSMC_Result_OK                    0x1
++#define PPSMC_Result_Failed                0xFF
++#define PPSMC_Result_UnknownCmd            0xFE
++#define PPSMC_Result_CmdRejectedPrereq     0xFD
++#define PPSMC_Result_CmdRejectedBusy       0xFC
++
++
++// Message Definitions:
++#define PPSMC_MSG_TestMessage                   0x1
++#define PPSMC_MSG_GetSmuVersion                 0x2
++#define PPSMC_MSG_GetDriverIfVersion            0x3
++#define PPSMC_MSG_PowerUpGfx                    0x6
++#define PPSMC_MSG_EnableGfxOff                  0x7
++#define PPSMC_MSG_DisableGfxOff                 0x8
++#define PPSMC_MSG_PowerDownIspByTile            0x9 // ISP is power gated by default
++#define PPSMC_MSG_PowerUpIspByTile              0xA
++#define PPSMC_MSG_PowerDownVcn                  0xB // VCN is power gated by default
++#define PPSMC_MSG_PowerUpVcn                    0xC
++#define PPSMC_MSG_PowerDownSdma                 0xD // SDMA is power gated by default
++#define PPSMC_MSG_PowerUpSdma                   0xE
++#define PPSMC_MSG_SetHardMinIspclkByFreq        0xF
++#define PPSMC_MSG_SetHardMinVcn                 0x10 // For wireless display
++#define PPSMC_MSG_spare1                        0x11
++#define PPSMC_MSG_spare2                        0x12
++#define PPSMC_MSG_SetAllowFclkSwitch            0x13
++#define PPSMC_MSG_SetMinVideoGfxclkFreq         0x14
++#define PPSMC_MSG_ActiveProcessNotify           0x15
++#define PPSMC_MSG_SetCustomPolicy               0x16
++#define PPSMC_MSG_SetVideoFps                   0x17
++#define PPSMC_MSG_SetDisplayCount               0x18 // Moved to VBIOS
++#define PPSMC_MSG_QueryPowerLimit               0x19 //Driver to look up sustainable clocks for VQ
++#define PPSMC_MSG_SetDriverDramAddrHigh         0x1A
++#define PPSMC_MSG_SetDriverDramAddrLow          0x1B
++#define PPSMC_MSG_TransferTableSmu2Dram         0x1C
++#define PPSMC_MSG_TransferTableDram2Smu         0x1D
++#define PPSMC_MSG_GfxDeviceDriverReset          0x1E
++#define PPSMC_MSG_SetGfxclkOverdriveByFreqVid   0x1F
++#define PPSMC_MSG_SetHardMinDcfclkByFreq        0x20 // Moved to VBIOS
++#define PPSMC_MSG_SetHardMinSocclkByFreq        0x21
++#define PPSMC_MSG_ControlIgpuATS                0x22
++#define PPSMC_MSG_SetMinVideoFclkFreq           0x23
++#define PPSMC_MSG_SetMinDeepSleepDcfclk         0x24 // Moved to VBIOS
++#define PPSMC_MSG_ForcePowerDownGfx             0x25
++#define PPSMC_MSG_SetPhyclkVoltageByFreq        0x26 // Moved to VBIOS
++#define PPSMC_MSG_SetDppclkVoltageByFreq        0x27 // Moved to VBIOS and is SetDppclkFreq
++#define PPSMC_MSG_SetSoftMinVcn                 0x28
++#define PPSMC_MSG_EnablePostCode                0x29
++#define PPSMC_MSG_GetGfxclkFrequency            0x2A
++#define PPSMC_MSG_GetFclkFrequency              0x2B
++#define PPSMC_MSG_GetMinGfxclkFrequency         0x2C
++#define PPSMC_MSG_GetMaxGfxclkFrequency         0x2D
++#define PPSMC_MSG_SoftReset                     0x2E // Not supported
++#define PPSMC_MSG_SetGfxCGPG                    0x2F
++#define PPSMC_MSG_SetSoftMaxGfxClk              0x30
++#define PPSMC_MSG_SetHardMinGfxClk              0x31
++#define PPSMC_MSG_SetSoftMaxSocclkByFreq        0x32
++#define PPSMC_MSG_SetSoftMaxFclkByFreq          0x33
++#define PPSMC_MSG_SetSoftMaxVcn                 0x34
++#define PPSMC_MSG_PowerGateMmHub                0x35
++#define PPSMC_MSG_UpdatePmeRestore              0x36 // Moved to VBIOS
++#define PPSMC_MSG_GpuChangeState                0x37
++#define PPSMC_MSG_SetPowerLimitPercentage       0x38
++#define PPSMC_MSG_ForceGfxContentSave           0x39
++#define PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown  0x3A // Moved to VBIOS
++#define PPSMC_MSG_PowerDownJpeg                 0x3B
++#define PPSMC_MSG_PowerUpJpeg                   0x3C
++#define PPSMC_MSG_PowerGateAtHub                0x3D
++#define PPSMC_MSG_SetSoftMinJpeg                0x3E
++#define PPSMC_MSG_SetHardMinFclkByFreq          0x3F
++#define PPSMC_Message_Count                     0x40
++
++
++//Argument for  PPSMC_MSG_GpuChangeState
++enum {
++  eGpuChangeState_D0Entry = 1,
++  eGpuChangeState_D3Entry,
++};
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3508-drm-amd-powerplay-add-smu12_driver_if.h-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3508-drm-amd-powerplay-add-smu12_driver_if.h-v3.patch
new file mode 100644
index 00000000..1e4fbe25
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3508-drm-amd-powerplay-add-smu12_driver_if.h-v3.patch
@@ -0,0 +1,245 @@
+From b5c6164e84c99143c3429cc1fd547a4edf639045 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Mon, 15 Jul 2019 13:53:32 +0800
+Subject: [PATCH 3508/4256] drm/amd/powerplay: add smu12_driver_if.h (v3)
+
+This patch adds smu12_driver_if.h
+
+v2: squash in updates (Alex)
+v3: more updates (Alex)
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/powerplay/inc/smu12_driver_if.h   | 217 ++++++++++++++++++
+ 1 file changed, 217 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h
+new file mode 100644
+index 000000000000..c27c82851468
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h
+@@ -0,0 +1,217 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef SMU12_DRIVER_IF_H
++#define SMU12_DRIVER_IF_H
++
++// *** IMPORTANT ***
++// SMU TEAM: Always increment the interface version if 
++// any structure is changed in this file
++#define SMU12_DRIVER_IF_VERSION 10
++
++typedef struct {
++  int32_t value;
++  uint32_t numFractionalBits;
++} FloatInIntFormat_t;
++
++typedef enum {
++  DSPCLK_DCFCLK = 0,
++  DSPCLK_DISPCLK,
++  DSPCLK_PIXCLK,
++  DSPCLK_PHYCLK,
++  DSPCLK_COUNT,
++} DSPCLK_e;
++
++typedef struct {
++  uint16_t Freq; // in MHz
++  uint16_t Vid;  // min voltage in SVI2 VID
++} DisplayClockTable_t;
++
++typedef struct {
++  uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
++  uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
++  uint16_t MinMclk;
++  uint16_t MaxMclk;
++
++  uint8_t  WmSetting;
++  uint8_t  WmType;  // Used for normal pstate change or memory retraining
++  uint8_t  Padding[2];
++} WatermarkRowGeneric_t;
++
++#define NUM_WM_RANGES 4
++#define WM_PSTATE_CHG 0
++#define WM_RETRAINING 1
++
++typedef enum {
++  WM_SOCCLK = 0,
++  WM_DCFCLK,
++  WM_COUNT,
++} WM_CLOCK_e;
++
++typedef struct {
++  // Watermarks
++  WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
++
++  uint32_t     MmHubPadding[7]; // SMU internal use
++} Watermarks_t;
++
++typedef enum {
++  CUSTOM_DPM_SETTING_GFXCLK,
++  CUSTOM_DPM_SETTING_CCLK,
++  CUSTOM_DPM_SETTING_FCLK_CCX,
++  CUSTOM_DPM_SETTING_FCLK_GFX,
++  CUSTOM_DPM_SETTING_FCLK_STALLS,
++  CUSTOM_DPM_SETTING_LCLK,
++  CUSTOM_DPM_SETTING_COUNT,
++} CUSTOM_DPM_SETTING_e;
++
++typedef struct {
++  uint8_t             ActiveHystLimit;
++  uint8_t             IdleHystLimit;
++  uint8_t             FPS;
++  uint8_t             MinActiveFreqType;
++  FloatInIntFormat_t  MinActiveFreq;
++  FloatInIntFormat_t  PD_Data_limit;
++  FloatInIntFormat_t  PD_Data_time_constant;
++  FloatInIntFormat_t  PD_Data_error_coeff;
++  FloatInIntFormat_t  PD_Data_error_rate_coeff;
++} DpmActivityMonitorCoeffExt_t;
++
++typedef struct {
++  DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
++} CustomDpmSettings_t;
++
++
++#define NUM_DCFCLK_DPM_LEVELS 8
++#define NUM_SOCCLK_DPM_LEVELS 8
++#define NUM_FCLK_DPM_LEVELS   4
++#define NUM_MEMCLK_DPM_LEVELS 4
++#define NUM_VCN_DPM_LEVELS    8
++
++typedef struct {
++  uint32_t Freq;    // In MHz
++  uint32_t Vol;     // Millivolts with 2 fractional bits
++} DpmClock_t;
++
++typedef struct {
++  DpmClock_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
++  DpmClock_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
++  DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS];
++  DpmClock_t MemClocks[NUM_MEMCLK_DPM_LEVELS];
++  DpmClock_t VClocks[NUM_VCN_DPM_LEVELS];
++  DpmClock_t DClocks[NUM_VCN_DPM_LEVELS];
++
++  uint8_t NumDcfClkDpmEnabled;
++  uint8_t NumSocClkDpmEnabled;
++  uint8_t NumFClkDpmEnabled;
++  uint8_t NumMemClkDpmEnabled;
++  uint8_t NumVClkDpmEnabled;
++  uint8_t NumDClkDpmEnabled;
++  uint8_t spare[2];
++} DpmClocks_t;
++
++
++typedef enum {
++  CLOCK_SMNCLK = 0,
++  CLOCK_SOCCLK,
++  CLOCK_MP0CLK,
++  CLOCK_MP1CLK,
++  CLOCK_MP2CLK,
++  CLOCK_VCLK,
++  CLOCK_LCLK,
++  CLOCK_DCLK,
++  CLOCK_ACLK,
++  CLOCK_ISPCLK,
++  CLOCK_SHUBCLK,
++  CLOCK_DISPCLK,
++  CLOCK_DPPCLK,
++  CLOCK_DPREFCLK,
++  CLOCK_DCFCLK,
++  CLOCK_FCLK,
++  CLOCK_UMCCLK,
++  CLOCK_GFXCLK,
++  CLOCK_COUNT,
++} CLOCK_IDs_e;
++
++// Throttler Status Bitmask
++#define THROTTLER_STATUS_BIT_SPL        0
++#define THROTTLER_STATUS_BIT_FPPT       1
++#define THROTTLER_STATUS_BIT_SPPT       2
++#define THROTTLER_STATUS_BIT_SPPT_APU   3
++#define THROTTLER_STATUS_BIT_THM_CORE   4
++#define THROTTLER_STATUS_BIT_THM_GFX    5
++#define THROTTLER_STATUS_BIT_THM_SOC    6
++#define THROTTLER_STATUS_BIT_TDC_VDD    7
++#define THROTTLER_STATUS_BIT_TDC_SOC    8
++
++typedef struct {
++  uint16_t ClockFrequency[CLOCK_COUNT]; //[MHz]
++
++  uint16_t AverageGfxclkFrequency;      //[MHz]
++  uint16_t AverageSocclkFrequency;      //[MHz]
++  uint16_t AverageVclkFrequency;        //[MHz]
++  uint16_t AverageFclkFrequency;        //[MHz]
++
++  uint16_t AverageGfxActivity;          //[centi]
++  uint16_t AverageUvdActivity;          //[centi]
++
++  uint16_t Voltage[2];                  //[mV] indices: VDDCR_VDD, VDDCR_SOC
++  uint16_t Current[2];                  //[mA] indices: VDDCR_VDD, VDDCR_SOC
++  uint16_t Power[2];                    //[mW] indices: VDDCR_VDD, VDDCR_SOC
++
++  uint16_t FanPwm;                      //[milli]
++  uint16_t CurrentSocketPower;          //[mW]
++
++  uint16_t CoreFrequency[8];            //[MHz]
++  uint16_t CorePower[8];                //[mW]
++  uint16_t CoreTemperature[8];          //[centi-Celsius]
++  uint16_t L3Frequency[2];              //[MHz]
++  uint16_t L3Temperature[2];            //[centi-Celsius]
++
++  uint16_t GfxTemperature;              //[centi-Celsius]
++  uint16_t SocTemperature;              //[centi-Celsius]
++  uint16_t ThrottlerStatus;
++  uint16_t spare;
++} SmuMetrics_t;
++
++
++// Workload bits
++#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
++#define WORKLOAD_PPLIB_VIDEO_BIT          2
++#define WORKLOAD_PPLIB_VR_BIT             3
++#define WORKLOAD_PPLIB_COMPUTE_BIT        4
++#define WORKLOAD_PPLIB_CUSTOM_BIT         5
++#define WORKLOAD_PPLIB_COUNT              6
++
++#define TABLE_BIOS_IF            0 // Called by BIOS
++#define TABLE_WATERMARKS         1 // Called by Driver
++#define TABLE_CUSTOM_DPM         2 // Called by Driver
++#define TABLE_SPARE1             3
++#define TABLE_DPMCLOCKS          4 // Called by Driver
++#define TABLE_MOMENTARY_PM       5 // Called by Tools
++#define TABLE_MODERN_STDBY       6 // Called by Tools for Modern Standby Log
++#define TABLE_SMU_METRICS        7 // Called by Driver
++#define TABLE_COUNT              8
++
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3509-drm-amdgpu-powerplay-add-initial-renoir_ppt.c-for-re.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3509-drm-amdgpu-powerplay-add-initial-renoir_ppt.c-for-re.patch
new file mode 100644
index 00000000..47666c15
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3509-drm-amdgpu-powerplay-add-initial-renoir_ppt.c-for-re.patch
@@ -0,0 +1,241 @@
+From b996cf0674196707819d03480365f15ba3e1eeb4 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Thu, 8 Aug 2019 15:18:30 -0500
+Subject: [PATCH 3509/4256] drm/amdgpu/powerplay: add initial renoir_ppt.c for
+ renoir (v3)
+
+Add renoir_ppt and map ppsmc to amdgpu_smu.h
+
+v2: squash in ppsmc updates (Alex)
+v3: squash in driver_if updates (Alex)
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu_types.h |  44 +++++++
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c    | 121 ++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.h    |  28 ++++
+ 3 files changed, 193 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+ create mode 100644 drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+index 72962e842d69..052aecc2827a 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+@@ -124,6 +124,50 @@
+        __SMU_DUMMY_MAP(PowerDownVcn0),               \
+        __SMU_DUMMY_MAP(PowerUpVcn1),                  \
+        __SMU_DUMMY_MAP(PowerDownVcn1),                \
++       __SMU_DUMMY_MAP(PowerUpGfx),                   \
++       __SMU_DUMMY_MAP(PowerDownIspByTile),           \
++       __SMU_DUMMY_MAP(PowerUpIspByTile),             \
++       __SMU_DUMMY_MAP(PowerDownSdma),                \
++	__SMU_DUMMY_MAP(PowerUpSdma),                 \
++	__SMU_DUMMY_MAP(SetHardMinIspclkByFreq),      \
++	__SMU_DUMMY_MAP(SetHardMinVcn),               \
++	__SMU_DUMMY_MAP(Spare1),                      \
++	__SMU_DUMMY_MAP(Spare2),           	      \
++	__SMU_DUMMY_MAP(SetAllowFclkSwitch),          \
++	__SMU_DUMMY_MAP(SetMinVideoGfxclkFreq),       \
++	__SMU_DUMMY_MAP(ActiveProcessNotify),         \
++	__SMU_DUMMY_MAP(SetCustomPolicy),             \
++	__SMU_DUMMY_MAP(QueryPowerLimit),             \
++	__SMU_DUMMY_MAP(SetGfxclkOverdriveByFreqVid), \
++	__SMU_DUMMY_MAP(SetHardMinDcfclkByFreq),      \
++	__SMU_DUMMY_MAP(SetHardMinSocclkByFreq),      \
++	__SMU_DUMMY_MAP(ControlIgpuATS),              \
++	__SMU_DUMMY_MAP(SetMinVideoFclkFreq),         \
++	__SMU_DUMMY_MAP(SetMinDeepSleepDcfclk),       \
++	__SMU_DUMMY_MAP(ForcePowerDownGfx),           \
++	__SMU_DUMMY_MAP(SetPhyclkVoltageByFreq),      \
++	__SMU_DUMMY_MAP(SetDppclkVoltageByFreq),      \
++	__SMU_DUMMY_MAP(SetSoftMinVcn),               \
++	__SMU_DUMMY_MAP(EnablePostCode),              \
++	__SMU_DUMMY_MAP(GetGfxclkFrequency),          \
++	__SMU_DUMMY_MAP(GetFclkFrequency),            \
++	__SMU_DUMMY_MAP(GetMinGfxclkFrequency),       \
++	__SMU_DUMMY_MAP(GetMaxGfxclkFrequency),       \
++	__SMU_DUMMY_MAP(SetGfxCGPG),                  \
++	__SMU_DUMMY_MAP(SetSoftMaxGfxClk),            \
++	__SMU_DUMMY_MAP(SetHardMinGfxClk),            \
++	__SMU_DUMMY_MAP(SetSoftMaxSocclkByFreq),      \
++	__SMU_DUMMY_MAP(SetSoftMaxFclkByFreq),        \
++	__SMU_DUMMY_MAP(SetSoftMaxVcn),               \
++	__SMU_DUMMY_MAP(PowerGateMmHub),              \
++	__SMU_DUMMY_MAP(UpdatePmeRestore),            \
++	__SMU_DUMMY_MAP(GpuChangeState),              \
++	__SMU_DUMMY_MAP(SetPowerLimitPercentage),     \
++	__SMU_DUMMY_MAP(ForceGfxContentSave),         \
++	__SMU_DUMMY_MAP(EnableTmdp48MHzRefclkPwrDown), \
++	__SMU_DUMMY_MAP(PowerGateAtHub),              \
++	__SMU_DUMMY_MAP(SetSoftMinJpeg),              \
++	__SMU_DUMMY_MAP(SetHardMinFclkByFreq),        \
+ 
+ #undef __SMU_DUMMY_MAP
+ #define __SMU_DUMMY_MAP(type)	SMU_MSG_##type
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+new file mode 100644
+index 000000000000..dd270600962b
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -0,0 +1,121 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include "amdgpu.h"
++#include "amdgpu_smu.h"
++#include "soc15_common.h"
++#include "smu_v12_0_ppsmc.h"
++#include "renoir_ppt.h"
++
++
++#define MSG_MAP(msg, index) \
++	[SMU_MSG_##msg] = index
++
++static int renoir_message_map[SMU_MSG_MAX_COUNT] = {
++	MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
++	MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
++	MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
++	MSG_MAP(PowerUpGfx,                     PPSMC_MSG_PowerUpGfx),
++	MSG_MAP(AllowGfxOff,                    PPSMC_MSG_EnableGfxOff),
++	MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisableGfxOff),
++	MSG_MAP(PowerDownIspByTile,             PPSMC_MSG_PowerDownIspByTile),
++	MSG_MAP(PowerUpIspByTile,               PPSMC_MSG_PowerUpIspByTile),
++	MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn),
++	MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn),
++	MSG_MAP(PowerDownSdma,                  PPSMC_MSG_PowerDownSdma),
++	MSG_MAP(PowerUpSdma,                    PPSMC_MSG_PowerUpSdma),
++	MSG_MAP(SetHardMinIspclkByFreq,         PPSMC_MSG_SetHardMinIspclkByFreq),
++	MSG_MAP(SetHardMinVcn,                  PPSMC_MSG_SetHardMinVcn),
++	MSG_MAP(Spare1,                         PPSMC_MSG_spare1),
++	MSG_MAP(Spare2,                         PPSMC_MSG_spare2),
++	MSG_MAP(SetAllowFclkSwitch,             PPSMC_MSG_SetAllowFclkSwitch),
++	MSG_MAP(SetMinVideoGfxclkFreq,          PPSMC_MSG_SetMinVideoGfxclkFreq),
++	MSG_MAP(ActiveProcessNotify,            PPSMC_MSG_ActiveProcessNotify),
++	MSG_MAP(SetCustomPolicy,                PPSMC_MSG_SetCustomPolicy),
++	MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
++	MSG_MAP(NumOfDisplays,                  PPSMC_MSG_SetDisplayCount),
++	MSG_MAP(QueryPowerLimit,                PPSMC_MSG_QueryPowerLimit),
++	MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
++	MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
++	MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
++	MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
++	MSG_MAP(GfxDeviceDriverReset,           PPSMC_MSG_GfxDeviceDriverReset),
++	MSG_MAP(SetGfxclkOverdriveByFreqVid,    PPSMC_MSG_SetGfxclkOverdriveByFreqVid),
++	MSG_MAP(SetHardMinDcfclkByFreq,         PPSMC_MSG_SetHardMinDcfclkByFreq),
++	MSG_MAP(SetHardMinSocclkByFreq,         PPSMC_MSG_SetHardMinSocclkByFreq),
++	MSG_MAP(ControlIgpuATS,                 PPSMC_MSG_ControlIgpuATS),
++	MSG_MAP(SetMinVideoFclkFreq,            PPSMC_MSG_SetMinVideoFclkFreq),
++	MSG_MAP(SetMinDeepSleepDcfclk,          PPSMC_MSG_SetMinDeepSleepDcfclk),
++	MSG_MAP(ForcePowerDownGfx,              PPSMC_MSG_ForcePowerDownGfx),
++	MSG_MAP(SetPhyclkVoltageByFreq,         PPSMC_MSG_SetPhyclkVoltageByFreq),
++	MSG_MAP(SetDppclkVoltageByFreq,         PPSMC_MSG_SetDppclkVoltageByFreq),
++	MSG_MAP(SetSoftMinVcn,                  PPSMC_MSG_SetSoftMinVcn),
++	MSG_MAP(EnablePostCode,                 PPSMC_MSG_EnablePostCode),
++	MSG_MAP(GetGfxclkFrequency,             PPSMC_MSG_GetGfxclkFrequency),
++	MSG_MAP(GetFclkFrequency,               PPSMC_MSG_GetFclkFrequency),
++	MSG_MAP(GetMinGfxclkFrequency,          PPSMC_MSG_GetMinGfxclkFrequency),
++	MSG_MAP(GetMaxGfxclkFrequency,          PPSMC_MSG_GetMaxGfxclkFrequency),
++	MSG_MAP(SoftReset,                      PPSMC_MSG_SoftReset),
++	MSG_MAP(SetGfxCGPG,                     PPSMC_MSG_SetGfxCGPG),
++	MSG_MAP(SetSoftMaxGfxClk,               PPSMC_MSG_SetSoftMaxGfxClk),
++	MSG_MAP(SetHardMinGfxClk,               PPSMC_MSG_SetHardMinGfxClk),
++	MSG_MAP(SetSoftMaxSocclkByFreq,         PPSMC_MSG_SetSoftMaxSocclkByFreq),
++	MSG_MAP(SetSoftMaxFclkByFreq,           PPSMC_MSG_SetSoftMaxFclkByFreq),
++	MSG_MAP(SetSoftMaxVcn,                  PPSMC_MSG_SetSoftMaxVcn),
++	MSG_MAP(PowerGateMmHub,                 PPSMC_MSG_PowerGateMmHub),
++	MSG_MAP(UpdatePmeRestore,               PPSMC_MSG_UpdatePmeRestore),
++	MSG_MAP(GpuChangeState,                 PPSMC_MSG_GpuChangeState),
++	MSG_MAP(SetPowerLimitPercentage,        PPSMC_MSG_SetPowerLimitPercentage),
++	MSG_MAP(ForceGfxContentSave,            PPSMC_MSG_ForceGfxContentSave),
++	MSG_MAP(EnableTmdp48MHzRefclkPwrDown,   PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown),
++	MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg),
++	MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg),
++	MSG_MAP(PowerGateAtHub,                 PPSMC_MSG_PowerGateAtHub),
++	MSG_MAP(SetSoftMinJpeg,                 PPSMC_MSG_SetSoftMinJpeg),
++	MSG_MAP(SetHardMinFclkByFreq,           PPSMC_MSG_SetHardMinFclkByFreq),
++};
++
++static int renoir_get_smu_msg_index(struct smu_context *smc, uint32_t index)
++{
++	int val;
++
++	if (index >= SMU_MSG_MAX_COUNT)
++		return -EINVAL;
++
++	val = renoir_message_map[index];
++	if (val > PPSMC_Message_Count)
++		return -EINVAL;
++
++	return val;
++}
++
++
++static const struct pptable_funcs renoir_ppt_funcs = {
++	.get_smu_msg_index = renoir_get_smu_msg_index,
++	.set_power_state = NULL,
++};
++
++void renoir_set_ppt_funcs(struct smu_context *smu)
++{
++	smu->ppt_funcs = &renoir_ppt_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+new file mode 100644
+index 000000000000..e9b7237c0f7f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+@@ -0,0 +1,28 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __RENOIR_PPT_H__
++#define __RENOIR_PPT_H__
++
++extern void renoir_set_ppt_funcs(struct smu_context *smu);
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3510-drm-amdgpu-powerplay-add-smu_v12_0.c-smu_v12_0.h-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3510-drm-amdgpu-powerplay-add-smu_v12_0.c-smu_v12_0.h-for.patch
new file mode 100644
index 00000000..a28930b8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3510-drm-amdgpu-powerplay-add-smu_v12_0.c-smu_v12_0.h-for.patch
@@ -0,0 +1,240 @@
+From 787ef46152d6d95298accbcb7fc99137a1a321fa Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Wed, 22 May 2019 19:16:27 +0800
+Subject: [PATCH 3510/4256] drm/amdgpu/powerplay: add smu_v12_0.c & smu_v12_0.h
+ for renoir
+
+add smu_v12_0.c & smu_v12_0.h for renoir
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h |  37 ++++
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c     | 170 ++++++++++++++++++
+ 2 files changed, 207 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+ create mode 100644 drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+new file mode 100644
+index 000000000000..278cdc2c0d47
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+@@ -0,0 +1,37 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __SMU_V12_0_H__
++#define __SMU_V12_0_H__
++
++#include "amdgpu_smu.h"
++
++/* MP Apertures */
++#define MP0_Public			0x03800000
++#define MP0_SRAM			0x03900000
++#define MP1_Public			0x03b00000
++#define MP1_SRAM			0x03c00004
++
++
++void smu_v12_0_set_smu_funcs(struct smu_context *smu);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+new file mode 100644
+index 000000000000..fdafa2306c29
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -0,0 +1,170 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include "pp_debug.h"
++#include <linux/firmware.h>
++#include "amdgpu.h"
++#include "amdgpu_smu.h"
++#include "atomfirmware.h"
++#include "amdgpu_atomfirmware.h"
++#include "smu_v12_0.h"
++#include "soc15_common.h"
++#include "atom.h"
++#include "renoir_ppt.h"
++
++#include "asic_reg/mp/mp_12_0_0_offset.h"
++#include "asic_reg/mp/mp_12_0_0_sh_mask.h"
++
++#define smnMP1_FIRMWARE_FLAGS                                0x3010024
++
++static int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
++					      uint16_t msg)
++{
++	struct amdgpu_device *adev = smu->adev;
++
++	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
++	return 0;
++}
++
++static int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg)
++{
++	struct amdgpu_device *adev = smu->adev;
++
++	*arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
++	return 0;
++}
++
++static int smu_v12_0_wait_for_response(struct smu_context *smu)
++{
++	struct amdgpu_device *adev = smu->adev;
++	uint32_t cur_value, i;
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
++		if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
++			break;
++		udelay(1);
++	}
++
++	/* timeout means wrong logic */
++	if (i == adev->usec_timeout)
++		return -ETIME;
++
++	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
++}
++
++static int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
++{
++	struct amdgpu_device *adev = smu->adev;
++	int ret = 0, index = 0;
++
++	index = smu_msg_get_index(smu, msg);
++	if (index < 0)
++		return index;
++
++	smu_v12_0_wait_for_response(smu);
++
++	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
++
++	smu_v12_0_send_msg_without_waiting(smu, (uint16_t)index);
++
++	ret = smu_v12_0_wait_for_response(smu);
++
++	if (ret)
++		pr_err("Failed to send message 0x%x, response 0x%x\n", index,
++		       ret);
++
++	return ret;
++
++}
++
++static int
++smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
++			      uint32_t param)
++{
++
++	struct amdgpu_device *adev = smu->adev;
++	int ret = 0, index = 0;
++
++	index = smu_msg_get_index(smu, msg);
++	if (index < 0)
++		return index;
++
++	ret = smu_v12_0_wait_for_response(smu);
++	if (ret)
++		pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
++		       index, ret, param);
++
++	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
++
++	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
++
++	smu_v12_0_send_msg_without_waiting(smu, (uint16_t)index);
++
++	ret = smu_v12_0_wait_for_response(smu);
++	if (ret)
++		pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
++		       index, ret, param);
++
++	return ret;
++}
++
++static int smu_v12_0_check_fw_version(struct smu_context *smu)
++{
++	uint32_t smu_version = 0xff;
++	int ret = 0;
++
++	ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
++	if (ret)
++		goto err;
++
++	ret = smu_read_smc_arg(smu, &smu_version);
++	if (ret)
++		goto err;
++
++	if (smu_version != smu->smc_if_version)
++		ret = -EINVAL;
++err:
++	return ret;
++}
++
++static const struct smu_funcs smu_v12_0_funcs = {
++	.check_fw_version = smu_v12_0_check_fw_version,
++	.send_smc_msg = smu_v12_0_send_msg,
++	.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
++	.read_smc_arg = smu_v12_0_read_arg,
++};
++
++void smu_v12_0_set_smu_funcs(struct smu_context *smu)
++{
++	struct amdgpu_device *adev = smu->adev;
++
++	smu->funcs = &smu_v12_0_funcs;
++
++	switch (adev->asic_type) {
++	case CHIP_RENOIR:
++		renoir_set_ppt_funcs(smu);
++		break;
++	default:
++		pr_warn("Unknown asic for smu12\n");
++	}
++}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3511-drm-amdgpu-powerplay-add-smu-ip-block-for-renoir-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3511-drm-amdgpu-powerplay-add-smu-ip-block-for-renoir-v2.patch
new file mode 100644
index 00000000..d44f5294
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3511-drm-amdgpu-powerplay-add-smu-ip-block-for-renoir-v2.patch
@@ -0,0 +1,110 @@
+From 5054202acfdaa9cf089c1df111290e11df26bd2d Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Wed, 24 Jul 2019 14:00:01 -0500
+Subject: [PATCH 3511/4256] drm/amdgpu/powerplay: add smu ip block for renoir
+ (v2)
+
+add swSMU [smu_v12_0] for renoir
+
+v2: whitespace fixes (Alex)
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c            |  2 ++
+ drivers/gpu/drm/amd/powerplay/Makefile        |  2 +-
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 19 +++++++++++++++++++
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  2 ++
+ 4 files changed, 24 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 2cf61946f3f1..3040e30eb970 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -761,6 +761,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ 			amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
++		if (is_support_sw_smu(adev))
++			amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
+ 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+ 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
+diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile
+index e05a7e3d6d8d..390345f2d601 100644
+--- a/drivers/gpu/drm/amd/powerplay/Makefile
++++ b/drivers/gpu/drm/amd/powerplay/Makefile
+@@ -35,7 +35,7 @@ AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/powerplay/,$(
+ 
+ include $(AMD_POWERPLAY)
+ 
+-POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o vega20_ppt.o arcturus_ppt.o navi10_ppt.o
++POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o smu_v12_0.o vega20_ppt.o arcturus_ppt.o navi10_ppt.o renoir_ppt.o
+ 
+ AMD_PP_POWER = $(addprefix $(AMD_PP_PATH)/,$(POWER_MGR))
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 4df7fb6eaf3c..54424babc8ca 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -27,6 +27,7 @@
+ #include "amdgpu_smu.h"
+ #include "soc15_common.h"
+ #include "smu_v11_0.h"
++#include "smu_v12_0.h"
+ #include "atom.h"
+ #include "amd_pcie.h"
+ 
+@@ -735,6 +736,12 @@ static int smu_set_funcs(struct amdgpu_device *adev)
+ 			smu->od_enabled = true;
+ 		smu_v11_0_set_smu_funcs(smu);
+ 		break;
++	case CHIP_RENOIR:
++		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
++		if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
++			smu->od_enabled = true;
++		smu_v12_0_set_smu_funcs(smu);
++		break;
+ 	default:
+ 		return -EINVAL;
+ 	}
+@@ -1031,6 +1038,9 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ 	struct amdgpu_device *adev = smu->adev;
+ 	int ret;
+ 
++	if (adev->flags & AMD_IS_APU)
++		return 0;
++
+ 	if (smu_is_dpm_running(smu) && adev->in_suspend) {
+ 		pr_info("dpm has been enabled\n");
+ 		return 0;
+@@ -1790,3 +1800,12 @@ const struct amdgpu_ip_block_version smu_v11_0_ip_block =
+ 	.rev = 0,
+ 	.funcs = &smu_ip_funcs,
+ };
++
++const struct amdgpu_ip_block_version smu_v12_0_ip_block =
++{
++	.type = AMD_IP_BLOCK_TYPE_SMC,
++	.major = 12,
++	.minor = 0,
++	.rev = 0,
++	.funcs = &smu_ip_funcs,
++};
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index e80c81552d29..61d453f83f88 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -755,6 +755,8 @@ extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
+ extern const struct amd_ip_funcs smu_ip_funcs;
+ 
+ extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
++extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
++
+ extern int smu_feature_init_dpm(struct smu_context *smu);
+ 
+ extern int smu_feature_is_enabled(struct smu_context *smu,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3512-drm-amdgpu-powerplay-add-power-up-down-SDMA-interfac.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3512-drm-amdgpu-powerplay-add-power-up-down-SDMA-interfac.patch
new file mode 100644
index 00000000..1f1d715d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3512-drm-amdgpu-powerplay-add-power-up-down-SDMA-interfac.patch
@@ -0,0 +1,155 @@
+From bd4ea38929a57a6dad4ed00315367458b650c226 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Fri, 9 Aug 2019 10:34:40 -0500
+Subject: [PATCH 3512/4256] drm/amdgpu/powerplay: add power up/down SDMA
+ interfaces for renoir
+
+1.Implement PowerUpSDMA/PowerDownSDMA interfaces in the swSMU for renoir
+2.adjust smu ip block ahead of gfx&sdma ip block
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c            |  4 +--
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  6 ++++
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  3 ++
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c     | 35 ++++++++++++++++---
+ 4 files changed, 42 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 3040e30eb970..b226883039e4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -759,10 +759,10 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ 		amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
+ 		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+ 			amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
+-		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
+-		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
+ 		if (is_support_sw_smu(adev))
+ 			amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
++		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
++		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
+ 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+ 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 54424babc8ca..d6c66216eb95 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1263,6 +1263,9 @@ static int smu_hw_init(void *handle)
+ 		return ret;
+ 	}
+ 
++	if (adev->asic_type == CHIP_RENOIR)
++		smu_powergate_sdma(&adev->smu, false);
++
+ 	if (!smu->pm_enabled)
+ 		return 0;
+ 
+@@ -1310,6 +1313,9 @@ static int smu_hw_fini(void *handle)
+ 	struct smu_table_context *table_context = &smu->smu_table;
+ 	int ret = 0;
+ 
++	if (adev->asic_type == CHIP_RENOIR)
++		smu_powergate_sdma(&adev->smu, true);
++
+ 	kfree(table_context->driver_pptable);
+ 	table_context->driver_pptable = NULL;
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 61d453f83f88..536f547f01c5 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -473,6 +473,7 @@ struct smu_funcs
+ 	int (*parse_pptable)(struct smu_context *smu);
+ 	int (*populate_smc_pptable)(struct smu_context *smu);
+ 	int (*check_fw_version)(struct smu_context *smu);
++	int (*powergate_sdma)(struct smu_context *smu, bool gate);
+ 	int (*write_pptable)(struct smu_context *smu);
+ 	int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
+ 	int (*set_tool_table_location)(struct smu_context *smu);
+@@ -549,6 +550,8 @@ struct smu_funcs
+ 	((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
+ #define smu_setup_pptable(smu) \
+ 	((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
++#define smu_powergate_sdma(smu, gate) \
++	((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
+ #define smu_get_vbios_bootup_values(smu) \
+ 	((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
+ #define smu_get_clk_info_from_vbios(smu) \
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index fdafa2306c29..cba8507a02af 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -101,7 +101,6 @@ static int
+ smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
+ 			      uint32_t param)
+ {
+-
+ 	struct amdgpu_device *adev = smu->adev;
+ 	int ret = 0, index = 0;
+ 
+@@ -128,27 +127,55 @@ smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
+ 	return ret;
+ }
+ 
++static int smu_v12_0_check_fw_status(struct smu_context *smu)
++{
++	struct amdgpu_device *adev = smu->adev;
++	uint32_t mp1_fw_flags;
++
++	mp1_fw_flags = RREG32_PCIE(MP1_Public |
++		(smnMP1_FIRMWARE_FLAGS & 0xffffffff));
++
++	if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
++		MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
++		return 0;
++
++	return -EIO;
++}
++
+ static int smu_v12_0_check_fw_version(struct smu_context *smu)
+ {
+-	uint32_t smu_version = 0xff;
++	uint32_t smc_if_version = 0xff;
+ 	int ret = 0;
+ 
+ 	ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
+ 	if (ret)
+ 		goto err;
+ 
+-	ret = smu_read_smc_arg(smu, &smu_version);
++	ret = smu_read_smc_arg(smu, &smc_if_version);
+ 	if (ret)
+ 		goto err;
+ 
+-	if (smu_version != smu->smc_if_version)
++	if (smc_if_version != smu->smc_if_version)
+ 		ret = -EINVAL;
+ err:
+ 	return ret;
+ }
+ 
++static int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
++{
++	if (!(smu->adev->flags & AMD_IS_APU))
++		return 0;
++
++	if (gate)
++		return smu_send_smc_msg(smu, SMU_MSG_PowerDownSdma);
++	else
++		return smu_send_smc_msg(smu, SMU_MSG_PowerUpSdma);
++}
++
+ static const struct smu_funcs smu_v12_0_funcs = {
++	.check_fw_status = smu_v12_0_check_fw_status,
+ 	.check_fw_version = smu_v12_0_check_fw_version,
++	.powergate_sdma = smu_v12_0_powergate_sdma,
+ 	.send_smc_msg = smu_v12_0_send_msg,
+ 	.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
+ 	.read_smc_arg = smu_v12_0_read_arg,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3513-drm-amdgpu-skip-dpm-init-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3513-drm-amdgpu-skip-dpm-init-for-renoir.patch
new file mode 100644
index 00000000..981b9d99
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3513-drm-amdgpu-skip-dpm-init-for-renoir.patch
@@ -0,0 +1,45 @@
+From 241d08305e3243992851e8aaea973a4fedc42aee Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Wed, 24 Jul 2019 14:05:11 -0500
+Subject: [PATCH 3513/4256] drm/amdgpu: skip dpm init for renoir
+
+Renoir DPM is not functional so far, we skip it for the comment.
+Will revert this patch once SMU 12 is functional.
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index d6c66216eb95..5ab3e7b8c68a 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -768,6 +768,11 @@ static int smu_late_init(void *handle)
+ 
+ 	if (!smu->pm_enabled)
+ 		return 0;
++
++	/* To be removed after dpm is enabled */
++	if (adev->asic_type == CHIP_RENOIR)
++		return 0;
++
+ 	mutex_lock(&smu->mutex);
+ 	smu_handle_task(&adev->smu,
+ 			smu->smu_dpm.dpm_level,
+@@ -1269,6 +1274,10 @@ static int smu_hw_init(void *handle)
+ 	if (!smu->pm_enabled)
+ 		return 0;
+ 
++	/* To be removed after dpm is enabled */
++	if (adev->asic_type == CHIP_RENOIR)
++		return 0;
++
+ 	ret = smu_feature_init_dpm(smu);
+ 	if (ret)
+ 		goto failed;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3514-drm-amdgpu-powerplay-add-Renoir-VCN-power-management.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3514-drm-amdgpu-powerplay-add-Renoir-VCN-power-management.patch
new file mode 100644
index 00000000..fa41c341
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3514-drm-amdgpu-powerplay-add-Renoir-VCN-power-management.patch
@@ -0,0 +1,99 @@
+From 9495a1532b66ff7e9415501d5208fed83e679a71 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Thu, 8 Aug 2019 15:21:44 -0500
+Subject: [PATCH 3514/4256] drm/amdgpu/powerplay: add Renoir VCN power
+ management
+
+Thus VCN can be powered up for normal operations
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     |  8 ++++++--
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  3 +++
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c      | 12 ++++++++++++
+ 3 files changed, 21 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 5ab3e7b8c68a..022507eacf1a 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1268,8 +1268,10 @@ static int smu_hw_init(void *handle)
+ 		return ret;
+ 	}
+ 
+-	if (adev->asic_type == CHIP_RENOIR)
++	if (adev->asic_type == CHIP_RENOIR) {
+ 		smu_powergate_sdma(&adev->smu, false);
++		smu_powergate_vcn(&adev->smu, false);
++	}
+ 
+ 	if (!smu->pm_enabled)
+ 		return 0;
+@@ -1322,8 +1324,10 @@ static int smu_hw_fini(void *handle)
+ 	struct smu_table_context *table_context = &smu->smu_table;
+ 	int ret = 0;
+ 
+-	if (adev->asic_type == CHIP_RENOIR)
++	if (adev->asic_type == CHIP_RENOIR) {
+ 		smu_powergate_sdma(&adev->smu, true);
++		smu_powergate_vcn(&adev->smu, true);
++	}
+ 
+ 	kfree(table_context->driver_pptable);
+ 	table_context->driver_pptable = NULL;
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 536f547f01c5..605767e79996 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -474,6 +474,7 @@ struct smu_funcs
+ 	int (*populate_smc_pptable)(struct smu_context *smu);
+ 	int (*check_fw_version)(struct smu_context *smu);
+ 	int (*powergate_sdma)(struct smu_context *smu, bool gate);
++	int (*powergate_vcn)(struct smu_context *smu, bool gate);
+ 	int (*write_pptable)(struct smu_context *smu);
+ 	int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
+ 	int (*set_tool_table_location)(struct smu_context *smu);
+@@ -552,6 +553,8 @@ struct smu_funcs
+ 	((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
+ #define smu_powergate_sdma(smu, gate) \
+ 	((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
++#define smu_powergate_vcn(smu, gate) \
++	((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
+ #define smu_get_vbios_bootup_values(smu) \
+ 	((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
+ #define smu_get_clk_info_from_vbios(smu) \
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index cba8507a02af..583fe7da4a4b 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -172,10 +172,22 @@ static int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
+ 		return smu_send_smc_msg(smu, SMU_MSG_PowerUpSdma);
+ }
+ 
++static int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
++{
++	if (!(smu->adev->flags & AMD_IS_APU))
++		return 0;
++
++	if (gate)
++		return smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
++	else
++		return smu_send_smc_msg(smu, SMU_MSG_PowerUpVcn);
++}
++
+ static const struct smu_funcs smu_v12_0_funcs = {
+ 	.check_fw_status = smu_v12_0_check_fw_status,
+ 	.check_fw_version = smu_v12_0_check_fw_version,
+ 	.powergate_sdma = smu_v12_0_powergate_sdma,
++	.powergate_vcn = smu_v12_0_powergate_vcn,
+ 	.send_smc_msg = smu_v12_0_send_msg,
+ 	.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
+ 	.read_smc_arg = smu_v12_0_read_arg,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3515-drm-amd-powerplay-powerup-sdma-vcn-for-all-apu-serie.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3515-drm-amd-powerplay-powerup-sdma-vcn-for-all-apu-serie.patch
new file mode 100644
index 00000000..009ffa94
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3515-drm-amd-powerplay-powerup-sdma-vcn-for-all-apu-serie.patch
@@ -0,0 +1,40 @@
+From a5cf5ff9b7a777316e164278f84a6803dc7fe9b7 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Thu, 8 Aug 2019 15:23:17 -0500
+Subject: [PATCH 3515/4256] drm/amd/powerplay: powerup sdma/vcn for all apu
+ series
+
+All apu series need powerup sdma and vcn via smu messages.
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 022507eacf1a..85f52401d5a1 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1268,7 +1268,7 @@ static int smu_hw_init(void *handle)
+ 		return ret;
+ 	}
+ 
+-	if (adev->asic_type == CHIP_RENOIR) {
++	if (adev->flags & AMD_IS_APU) {
+ 		smu_powergate_sdma(&adev->smu, false);
+ 		smu_powergate_vcn(&adev->smu, false);
+ 	}
+@@ -1324,7 +1324,7 @@ static int smu_hw_fini(void *handle)
+ 	struct smu_table_context *table_context = &smu->smu_table;
+ 	int ret = 0;
+ 
+-	if (adev->asic_type == CHIP_RENOIR) {
++	if (adev->flags & AMD_IS_APU) {
+ 		smu_powergate_sdma(&adev->smu, true);
+ 		smu_powergate_vcn(&adev->smu, true);
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3516-drm-amd-powerplay-udpate-smu_v12_0_check_fw_version-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3516-drm-amd-powerplay-udpate-smu_v12_0_check_fw_version-.patch
new file mode 100644
index 00000000..cdcdd3e8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3516-drm-amd-powerplay-udpate-smu_v12_0_check_fw_version-.patch
@@ -0,0 +1,91 @@
+From c8dbc592cd404620b4abfd8fdb8afb68a834e353 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Tue, 23 Jul 2019 10:39:38 +0800
+Subject: [PATCH 3516/4256] drm/amd/powerplay: udpate
+ smu_v12_0_check_fw_version (v2)
+
+This interface support SMU_MSG_GetDriverIfVersion
+and SMU_MSG_GetSmuVersion checking.
+
+v2: squash in driver_if changes (Alex)
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c |  2 ++
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c  | 35 +++++++++++++++-------
+ 2 files changed, 27 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index dd270600962b..af8bb1cc5d9a 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -25,6 +25,7 @@
+ #include "amdgpu_smu.h"
+ #include "soc15_common.h"
+ #include "smu_v12_0_ppsmc.h"
++#include "smu12_driver_if.h"
+ #include "renoir_ppt.h"
+ 
+ 
+@@ -118,4 +119,5 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ void renoir_set_ppt_funcs(struct smu_context *smu)
+ {
+ 	smu->ppt_funcs = &renoir_ppt_funcs;
++	smu->smc_if_version = SMU12_DRIVER_IF_VERSION;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 583fe7da4a4b..695b9af8662b 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -144,20 +144,35 @@ static int smu_v12_0_check_fw_status(struct smu_context *smu)
+ 
+ static int smu_v12_0_check_fw_version(struct smu_context *smu)
+ {
+-	uint32_t smc_if_version = 0xff;
++	uint32_t if_version = 0xff, smu_version = 0xff;
++	uint16_t smu_major;
++	uint8_t smu_minor, smu_debug;
+ 	int ret = 0;
+ 
+-	ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
++	ret = smu_get_smc_version(smu, &if_version, &smu_version);
+ 	if (ret)
+-		goto err;
+-
+-	ret = smu_read_smc_arg(smu, &smc_if_version);
+-	if (ret)
+-		goto err;
++		return ret;
++
++	smu_major = (smu_version >> 16) & 0xffff;
++	smu_minor = (smu_version >> 8) & 0xff;
++	smu_debug = (smu_version >> 0) & 0xff;
++
++	/*
++	 * 1. if_version mismatch is not critical as our fw is designed
++	 * to be backward compatible.
++	 * 2. New fw usually brings some optimizations. But that's visible
++	 * only on the paired driver.
++	 * Considering above, we just leave user a warning message instead
++	 * of halt driver loading.
++	 */
++	if (if_version != smu->smc_if_version) {
++		pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
++			"smu fw version = 0x%08x (%d.%d.%d)\n",
++			smu->smc_if_version, if_version,
++			smu_version, smu_major, smu_minor, smu_debug);
++		pr_warn("SMU driver if version not matched\n");
++	}
+ 
+-	if (smc_if_version != smu->smc_if_version)
+-		ret = -EINVAL;
+-err:
+ 	return ret;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3517-drm-amdgpu-add-set_gfx_cgpg-implement-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3517-drm-amdgpu-add-set_gfx_cgpg-implement-v2.patch
new file mode 100644
index 00000000..57b80a6d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3517-drm-amdgpu-add-set_gfx_cgpg-implement-v2.patch
@@ -0,0 +1,94 @@
+From b1f78d62b5eaea1166c89685ca8a4d36b3f6ab8f Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Tue, 16 Jul 2019 17:21:17 +0800
+Subject: [PATCH 3517/4256] drm/amdgpu: add set_gfx_cgpg implement (v2)
+
+add set_gfx_cgpg implement
+
+v2: check if using sw_smu (Alex)
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c          |  5 +++++
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  3 +++
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c      | 10 ++++++++++
+ 3 files changed, 18 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 2a43ec2f7bad..b3defa07b7c8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4561,6 +4561,9 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
+ {
+ 	amdgpu_gfx_rlc_enter_safe_mode(adev);
+ 
++	if (is_support_sw_smu(adev) && !enable)
++		smu_set_gfx_cgpg(&adev->smu, enable);
++
+ 	if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
+ 		gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
+ 		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
+@@ -4836,6 +4839,8 @@ static int gfx_v9_0_set_powergating_state(void *handle,
+ 			gfx_v9_0_enable_cp_power_gating(adev, false);
+ 
+ 		/* update gfx cgpg state */
++		if (is_support_sw_smu(adev) && enable)
++			smu_set_gfx_cgpg(&adev->smu, enable);
+ 		gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
+ 
+ 		/* update mgcg state */
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 605767e79996..7b352c5a451e 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -475,6 +475,7 @@ struct smu_funcs
+ 	int (*check_fw_version)(struct smu_context *smu);
+ 	int (*powergate_sdma)(struct smu_context *smu, bool gate);
+ 	int (*powergate_vcn)(struct smu_context *smu, bool gate);
++	int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
+ 	int (*write_pptable)(struct smu_context *smu);
+ 	int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
+ 	int (*set_tool_table_location)(struct smu_context *smu);
+@@ -555,6 +556,8 @@ struct smu_funcs
+ 	((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
+ #define smu_powergate_vcn(smu, gate) \
+ 	((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
++#define smu_set_gfx_cgpg(smu, enabled) \
++	((smu)->funcs->set_gfx_cgpg ? (smu)->funcs->set_gfx_cgpg((smu), (enabled)) : 0)
+ #define smu_get_vbios_bootup_values(smu) \
+ 	((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
+ #define smu_get_clk_info_from_vbios(smu) \
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 695b9af8662b..cf523b8b2aeb 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -198,6 +198,15 @@ static int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
+ 		return smu_send_smc_msg(smu, SMU_MSG_PowerUpVcn);
+ }
+ 
++static int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
++{
++	if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
++		return 0;
++
++	return smu_v12_0_send_msg_with_param(smu,
++		SMU_MSG_SetGfxCGPG, enable ? 1 : 0);
++}
++
+ static const struct smu_funcs smu_v12_0_funcs = {
+ 	.check_fw_status = smu_v12_0_check_fw_status,
+ 	.check_fw_version = smu_v12_0_check_fw_version,
+@@ -206,6 +215,7 @@ static const struct smu_funcs smu_v12_0_funcs = {
+ 	.send_smc_msg = smu_v12_0_send_msg,
+ 	.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
+ 	.read_smc_arg = smu_v12_0_read_arg,
++	.set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
+ };
+ 
+ void smu_v12_0_set_smu_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3518-drm-amdgpu-add-and-enable-gfxoff-feature.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3518-drm-amdgpu-add-and-enable-gfxoff-feature.patch
new file mode 100644
index 00000000..f6616056
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3518-drm-amdgpu-add-and-enable-gfxoff-feature.patch
@@ -0,0 +1,118 @@
+From db742088f435d1dc229de1350dc6f1b67c6c6ec8 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Tue, 16 Jul 2019 17:33:47 +0800
+Subject: [PATCH 3518/4256] drm/amdgpu: add and enable gfxoff feature
+
+This patch updates gfxoff feature.
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c         |  5 +++
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c |  1 -
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c  | 44 ++++++++++++++++++++++
+ 3 files changed, 49 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index b226883039e4..c092be45f5e2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1157,6 +1157,11 @@ static int soc15_common_early_init(void *handle)
+ 		adev->cg_flags = 0;
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x91;
++
++		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
++			adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
++				AMD_PG_SUPPORT_CP |
++				AMD_PG_SUPPORT_RLC_SMU_HS;
+ 		break;
+ 	default:
+ 		/* FIXME: not supported yet */
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 85f52401d5a1..6505690cfa76 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -737,7 +737,6 @@ static int smu_set_funcs(struct amdgpu_device *adev)
+ 		smu_v11_0_set_smu_funcs(smu);
+ 		break;
+ 	case CHIP_RENOIR:
+-		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ 		if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
+ 			smu->od_enabled = true;
+ 		smu_v12_0_set_smu_funcs(smu);
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index cf523b8b2aeb..7d4e966cc9f0 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -36,6 +36,13 @@
+ 
+ #define smnMP1_FIRMWARE_FLAGS                                0x3010024
+ 
++#define mmPWR_MISC_CNTL_STATUS					0x0183
++#define mmPWR_MISC_CNTL_STATUS_BASE_IDX				0
++#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT	0x0
++#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT		0x1
++#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK		0x00000001L
++#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK		0x00000006L
++
+ static int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
+ 					      uint16_t msg)
+ {
+@@ -207,6 +214,42 @@ static int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
+ 		SMU_MSG_SetGfxCGPG, enable ? 1 : 0);
+ }
+ 
++static bool smu_v12_0_is_gfx_on(struct smu_context *smu)
++{
++	uint32_t reg;
++	struct amdgpu_device *adev = smu->adev;
++
++	reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);
++	if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) ==
++	    (0x2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT))
++		return true;
++
++	return false;
++}
++
++static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
++{
++	int ret = 0, timeout = 10;
++
++	if (enable) {
++		ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
++	} else {
++		ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
++
++		/* confirm gfx is back to "on" state */
++		while (!smu_v12_0_is_gfx_on(smu)) {
++			msleep(1);
++			timeout--;
++			if (timeout == 0) {
++				DRM_ERROR("disable gfxoff timeout and failed!\n");
++				break;
++			}
++		}
++	}
++
++	return ret;
++}
++
+ static const struct smu_funcs smu_v12_0_funcs = {
+ 	.check_fw_status = smu_v12_0_check_fw_status,
+ 	.check_fw_version = smu_v12_0_check_fw_version,
+@@ -216,6 +259,7 @@ static const struct smu_funcs smu_v12_0_funcs = {
+ 	.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
+ 	.read_smc_arg = smu_v12_0_read_arg,
+ 	.set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
++	.gfx_off_control = smu_v12_0_gfx_off_control,
+ };
+ 
+ void smu_v12_0_set_smu_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3519-drm-amd-powerplay-fix-checking-gfxoff-status-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3519-drm-amd-powerplay-fix-checking-gfxoff-status-for-rn.patch
new file mode 100644
index 00000000..52e5424f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3519-drm-amd-powerplay-fix-checking-gfxoff-status-for-rn.patch
@@ -0,0 +1,111 @@
+From cb47b0f65a9fdfe5f3a7b9fbb98361f8f854241c Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Fri, 26 Jul 2019 10:51:32 +0800
+Subject: [PATCH 3519/4256] drm/amd/powerplay: fix checking gfxoff status for
+ rn
+
+For renoir, it should use mmSMUIO_GFX_MISC_CNTL to check
+gfxoff status. For the first time to enter gfxoff status,
+it maybe takes about one second more. So just set the max
+timeout to 5s.
+
+GFXOFF_STATUS(bits 2:1)'s description is below:
+0=GFXOFF(default).
+1=Transition out of GFX State.
+2=Not in GFXOFF.
+3=Transition into GFXOFF.
+
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 50 ++++++++++++++++-------
+ 1 file changed, 35 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 7d4e966cc9f0..363a5a76b6a6 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -36,12 +36,10 @@
+ 
+ #define smnMP1_FIRMWARE_FLAGS                                0x3010024
+ 
+-#define mmPWR_MISC_CNTL_STATUS					0x0183
+-#define mmPWR_MISC_CNTL_STATUS_BASE_IDX				0
+-#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT	0x0
+-#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT		0x1
+-#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK		0x00000001L
+-#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK		0x00000006L
++#define mmSMUIO_GFX_MISC_CNTL                                0x00c8
++#define mmSMUIO_GFX_MISC_CNTL_BASE_IDX                       0
++#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK          0x00000006L
++#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT        0x1
+ 
+ static int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
+ 					      uint16_t msg)
+@@ -214,30 +212,52 @@ static int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
+ 		SMU_MSG_SetGfxCGPG, enable ? 1 : 0);
+ }
+ 
+-static bool smu_v12_0_is_gfx_on(struct smu_context *smu)
++/**
++ * smu_v12_0_get_gfxoff_status - get gfxoff status
++ *
++ * @smu: amdgpu_device pointer
++ *
++ * This function will be used to get gfxoff status
++ *
++ * Returns 0=GFXOFF(default).
++ * Returns 1=Transition out of GFX State.
++ * Returns 2=Not in GFXOFF.
++ * Returns 3=Transition into GFXOFF.
++ */
++static uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
+ {
+ 	uint32_t reg;
++	uint32_t gfxOff_Status = 0;
+ 	struct amdgpu_device *adev = smu->adev;
+ 
+-	reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);
+-	if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) ==
+-	    (0x2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT))
+-		return true;
++	reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);
++	gfxOff_Status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
++		>> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
+ 
+-	return false;
++	return gfxOff_Status;
+ }
+ 
+ static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
+ {
+-	int ret = 0, timeout = 10;
++	int ret = 0, timeout = 500;
+ 
+ 	if (enable) {
+ 		ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
++
++		/* confirm gfx is back to "off" state, timeout is 5 seconds */
++		while (!(smu_v12_0_get_gfxoff_status(smu) == 0)) {
++			msleep(10);
++			timeout--;
++			if (timeout == 0) {
++				DRM_ERROR("enable gfxoff timeout and failed!\n");
++				break;
++			}
++		}
+ 	} else {
+ 		ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
+ 
+-		/* confirm gfx is back to "on" state */
+-		while (!smu_v12_0_is_gfx_on(smu)) {
++		/* confirm gfx is back to "on" state, timeout is 0.5 second */
++		while (!(smu_v12_0_get_gfxoff_status(smu) == 2)) {
+ 			msleep(1);
+ 			timeout--;
+ 			if (timeout == 0) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3520-drm-amd-powerplay-using-valid-mapping-check-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3520-drm-amd-powerplay-using-valid-mapping-check-for-rn.patch
new file mode 100644
index 00000000..9fa5848a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3520-drm-amd-powerplay-using-valid-mapping-check-for-rn.patch
@@ -0,0 +1,78 @@
+From 3b894e81dd820a0f479434bb646b9e9c90c9775a Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Wed, 21 Aug 2019 16:45:52 -0500
+Subject: [PATCH 3520/4256] drm/amd/powerplay: using valid mapping check for rn
+
+Check whether the message mapping is valid
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h |  5 +++++
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c    | 13 +++++++------
+ 2 files changed, 12 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+index 278cdc2c0d47..acf3db12f59f 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+@@ -32,6 +32,11 @@
+ #define MP1_SRAM			0x03c00004
+ 
+ 
++struct smu_12_0_cmn2aisc_mapping {
++	int	valid_mapping;
++	int	map_to;
++};
++
+ void smu_v12_0_set_smu_funcs(struct smu_context *smu);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index af8bb1cc5d9a..2580383ff49b 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -26,13 +26,14 @@
+ #include "soc15_common.h"
+ #include "smu_v12_0_ppsmc.h"
+ #include "smu12_driver_if.h"
++#include "smu_v12_0.h"
+ #include "renoir_ppt.h"
+ 
+ 
+ #define MSG_MAP(msg, index) \
+-	[SMU_MSG_##msg] = index
++	[SMU_MSG_##msg] = {1, (index)}
+ 
+-static int renoir_message_map[SMU_MSG_MAX_COUNT] = {
++static struct smu_12_0_cmn2aisc_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
+ 	MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
+ 	MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
+ 	MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
+@@ -98,16 +99,16 @@ static int renoir_message_map[SMU_MSG_MAX_COUNT] = {
+ 
+ static int renoir_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+ {
+-	int val;
++	struct smu_12_0_cmn2aisc_mapping mapping;
+ 
+ 	if (index >= SMU_MSG_MAX_COUNT)
+ 		return -EINVAL;
+ 
+-	val = renoir_message_map[index];
+-	if (val > PPSMC_Message_Count)
++	mapping = renoir_message_map[index];
++	if (!(mapping.valid_mapping))
+ 		return -EINVAL;
+ 
+-	return val;
++	return mapping.map_to;
+ }
+ 
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3521-drm-amd-powerplay-add-smu-tables-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3521-drm-amd-powerplay-add-smu-tables-for-rn.patch
new file mode 100644
index 00000000..a4dd52ec
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3521-drm-amd-powerplay-add-smu-tables-for-rn.patch
@@ -0,0 +1,88 @@
+From 45f01db674f732670c595bcec8c0a5d3162fb1ee Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Tue, 30 Jul 2019 10:50:44 +0800
+Subject: [PATCH 3521/4256] drm/amd/powerplay: add smu tables for rn
+
+add and map smu tables for renoir
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  2 ++
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c    | 27 +++++++++++++++++++
+ 2 files changed, 29 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 7b352c5a451e..4d156e5ab2e8 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -231,6 +231,8 @@ enum smu_table_id
+ {
+ 	SMU_TABLE_PPTABLE = 0,
+ 	SMU_TABLE_WATERMARKS,
++	SMU_TABLE_CUSTOM_DPM,
++	SMU_TABLE_DPMCLOCKS,
+ 	SMU_TABLE_AVFS,
+ 	SMU_TABLE_AVFS_PSM_DEBUG,
+ 	SMU_TABLE_AVFS_FUSE_OVERRIDE,
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 2580383ff49b..7c3dc150eaa3 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -33,6 +33,12 @@
+ #define MSG_MAP(msg, index) \
+ 	[SMU_MSG_##msg] = {1, (index)}
+ 
++#define TAB_MAP_VALID(tab) \
++	[SMU_TABLE_##tab] = {1, TABLE_##tab}
++
++#define TAB_MAP_INVALID(tab) \
++	[SMU_TABLE_##tab] = {0, TABLE_##tab}
++
+ static struct smu_12_0_cmn2aisc_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
+ 	MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
+ 	MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
+@@ -97,6 +103,13 @@ static struct smu_12_0_cmn2aisc_mapping renoir_message_map[SMU_MSG_MAX_COUNT] =
+ 	MSG_MAP(SetHardMinFclkByFreq,           PPSMC_MSG_SetHardMinFclkByFreq),
+ };
+ 
++static struct smu_12_0_cmn2aisc_mapping renoir_table_map[SMU_TABLE_COUNT] = {
++	TAB_MAP_VALID(WATERMARKS),
++	TAB_MAP_INVALID(CUSTOM_DPM),
++	TAB_MAP_VALID(DPMCLOCKS),
++	TAB_MAP_VALID(SMU_METRICS),
++};
++
+ static int renoir_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+ {
+ 	struct smu_12_0_cmn2aisc_mapping mapping;
+@@ -111,9 +124,23 @@ static int renoir_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+ 	return mapping.map_to;
+ }
+ 
++static int renoir_get_smu_table_index(struct smu_context *smc, uint32_t index)
++{
++	struct smu_12_0_cmn2aisc_mapping mapping;
++
++	if (index >= SMU_TABLE_COUNT)
++		return -EINVAL;
++
++	mapping = renoir_table_map[index];
++	if (!(mapping.valid_mapping))
++		return -EINVAL;
++
++	return mapping.map_to;
++}
+ 
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_smu_msg_index = renoir_get_smu_msg_index,
++	.get_smu_table_index = renoir_get_smu_table_index,
+ 	.set_power_state = NULL,
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3522-drm-amd-powerplay-init-smu-tables-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3522-drm-amd-powerplay-init-smu-tables-for-rn.patch
new file mode 100644
index 00000000..b8348ab4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3522-drm-amd-powerplay-init-smu-tables-for-rn.patch
@@ -0,0 +1,106 @@
+From d77323c16f263db2a0d2135285d2bcbae899dcf5 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Tue, 30 Jul 2019 11:04:58 +0800
+Subject: [PATCH 3522/4256] drm/amd/powerplay: init smu tables for rn
+
+Initialize smu tables for renoir:
+WATERMARKS/DPMCLOCKS/SMU_METRICS
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 16 +++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c  | 32 ++++++++++++++++++++++
+ 2 files changed, 48 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 7c3dc150eaa3..c8e0d79de43e 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -138,14 +138,30 @@ static int renoir_get_smu_table_index(struct smu_context *smc, uint32_t index)
+ 	return mapping.map_to;
+ }
+ 
++static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
++{
++	SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
++		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
++	SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
++		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
++	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
++		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
++
++	return 0;
++}
++
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_smu_msg_index = renoir_get_smu_msg_index,
+ 	.get_smu_table_index = renoir_get_smu_table_index,
++	.tables_init = renoir_tables_init,
+ 	.set_power_state = NULL,
+ };
+ 
+ void renoir_set_ppt_funcs(struct smu_context *smu)
+ {
++	struct smu_table_context *smu_table = &smu->smu_table;
++
+ 	smu->ppt_funcs = &renoir_ppt_funcs;
+ 	smu->smc_if_version = SMU12_DRIVER_IF_VERSION;
++	smu_table->table_count = TABLE_COUNT;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 363a5a76b6a6..76a6c4b7b63c 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -270,6 +270,36 @@ static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
+ 	return ret;
+ }
+ 
++static int smu_v12_0_init_smc_tables(struct smu_context *smu)
++{
++	struct smu_table_context *smu_table = &smu->smu_table;
++	struct smu_table *tables = NULL;
++
++	if (smu_table->tables || smu_table->table_count == 0)
++		return -EINVAL;
++
++	tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
++			 GFP_KERNEL);
++	if (!tables)
++		return -ENOMEM;
++
++	smu_table->tables = tables;
++
++	return smu_tables_init(smu, tables);
++}
++
++static int smu_v12_0_fini_smc_tables(struct smu_context *smu)
++{
++	struct smu_table_context *smu_table = &smu->smu_table;
++
++	if (!smu_table->tables || smu_table->table_count == 0)
++		return -EINVAL;
++
++	kfree(smu_table->tables);
++	smu_table->tables = NULL;
++
++	return 0;
++}
+ static const struct smu_funcs smu_v12_0_funcs = {
+ 	.check_fw_status = smu_v12_0_check_fw_status,
+ 	.check_fw_version = smu_v12_0_check_fw_version,
+@@ -280,6 +310,8 @@ static const struct smu_funcs smu_v12_0_funcs = {
+ 	.read_smc_arg = smu_v12_0_read_arg,
+ 	.set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
+ 	.gfx_off_control = smu_v12_0_gfx_off_control,
++	.init_smc_tables = smu_v12_0_init_smc_tables,
++	.fini_smc_tables = smu_v12_0_fini_smc_tables,
+ };
+ 
+ void smu_v12_0_set_smu_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3523-drm-amd-powerplay-add-DPMCLOCKS-table-implementation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3523-drm-amd-powerplay-add-DPMCLOCKS-table-implementation.patch
new file mode 100644
index 00000000..e6a0f723
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3523-drm-amd-powerplay-add-DPMCLOCKS-table-implementation.patch
@@ -0,0 +1,150 @@
+From 6604c2d6d5ab826ebc52cd23d7cb1f0a6fb7019a Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Tue, 30 Jul 2019 11:28:27 +0800
+Subject: [PATCH 3523/4256] drm/amd/powerplay: add DPMCLOCKS table
+ implementation
+
+This patch adds add DPMCLOCKS table implementation
+Rename smu_populate_smc_pptable to smu_populate_smc_tables
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  2 +-
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  7 ++++---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c    |  6 ++++++
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     |  2 +-
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c     | 20 +++++++++++++++++++
+ 5 files changed, 32 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 6505690cfa76..ebfd631521c8 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1150,7 +1150,7 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ 	 * type of clks.
+ 	 */
+ 	if (initialize) {
+-		ret = smu_populate_smc_pptable(smu);
++		ret = smu_populate_smc_tables(smu);
+ 		if (ret)
+ 			return ret;
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 4d156e5ab2e8..c42691a9afd3 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -253,6 +253,7 @@ struct smu_table_context
+ 	void				*hardcode_pptable;
+ 	unsigned long			metrics_time;
+ 	void				*metrics_table;
++	void				*clocks_table;
+ 
+ 	void				*max_sustainable_clocks;
+ 	struct smu_bios_boot_up_values	boot_values;
+@@ -473,7 +474,7 @@ struct smu_funcs
+ 	int (*get_clk_info_from_vbios)(struct smu_context *smu);
+ 	int (*check_pptable)(struct smu_context *smu);
+ 	int (*parse_pptable)(struct smu_context *smu);
+-	int (*populate_smc_pptable)(struct smu_context *smu);
++	int (*populate_smc_tables)(struct smu_context *smu);
+ 	int (*check_fw_version)(struct smu_context *smu);
+ 	int (*powergate_sdma)(struct smu_context *smu, bool gate);
+ 	int (*powergate_vcn)(struct smu_context *smu, bool gate);
+@@ -568,8 +569,8 @@ struct smu_funcs
+ 	((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
+ #define smu_parse_pptable(smu) \
+ 	((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
+-#define smu_populate_smc_pptable(smu) \
+-	((smu)->funcs->populate_smc_pptable ? (smu)->funcs->populate_smc_pptable((smu)) : 0)
++#define smu_populate_smc_tables(smu) \
++	((smu)->funcs->populate_smc_tables ? (smu)->funcs->populate_smc_tables((smu)) : 0)
+ #define smu_check_fw_version(smu) \
+ 	((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
+ #define smu_write_pptable(smu) \
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index c8e0d79de43e..de43159564a5 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -140,6 +140,8 @@ static int renoir_get_smu_table_index(struct smu_context *smc, uint32_t index)
+ 
+ static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
+ {
++	struct smu_table_context *smu_table = &smu->smu_table;
++
+ 	SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
+ 		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ 	SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
+@@ -147,6 +149,10 @@ static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
+ 	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
+ 		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ 
++	smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
++	if (!smu_table->clocks_table)
++		return -ENOMEM;
++
+ 	return 0;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 1ec42903a250..d3500a5ef720 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1744,7 +1744,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
+ 	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+ 	.check_pptable = smu_v11_0_check_pptable,
+ 	.parse_pptable = smu_v11_0_parse_pptable,
+-	.populate_smc_pptable = smu_v11_0_populate_smc_pptable,
++	.populate_smc_tables = smu_v11_0_populate_smc_pptable,
+ 	.write_pptable = smu_v11_0_write_pptable,
+ 	.write_watermarks_table = smu_v11_0_write_watermarks_table,
+ 	.set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 76a6c4b7b63c..0f5d08ae71ae 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -295,11 +295,30 @@ static int smu_v12_0_fini_smc_tables(struct smu_context *smu)
+ 	if (!smu_table->tables || smu_table->table_count == 0)
+ 		return -EINVAL;
+ 
++	kfree(smu_table->clocks_table);
+ 	kfree(smu_table->tables);
++
++	smu_table->clocks_table = NULL;
+ 	smu_table->tables = NULL;
+ 
+ 	return 0;
+ }
++
++static int smu_v12_0_populate_smc_tables(struct smu_context *smu)
++{
++	struct smu_table_context *smu_table = &smu->smu_table;
++	struct smu_table *table = NULL;
++
++	table = &smu_table->tables[SMU_TABLE_DPMCLOCKS];
++	if (!table)
++		return -EINVAL;
++
++	if (!table->cpu_addr)
++		return -EINVAL;
++
++	return smu_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
++}
++
+ static const struct smu_funcs smu_v12_0_funcs = {
+ 	.check_fw_status = smu_v12_0_check_fw_status,
+ 	.check_fw_version = smu_v12_0_check_fw_version,
+@@ -312,6 +331,7 @@ static const struct smu_funcs smu_v12_0_funcs = {
+ 	.gfx_off_control = smu_v12_0_gfx_off_control,
+ 	.init_smc_tables = smu_v12_0_init_smc_tables,
+ 	.fini_smc_tables = smu_v12_0_fini_smc_tables,
++	.populate_smc_tables = smu_v12_0_populate_smc_tables,
+ };
+ 
+ void smu_v12_0_set_smu_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3524-drm-amdgpu-enable-gfx-clock-gating-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3524-drm-amdgpu-enable-gfx-clock-gating-for-rn.patch
new file mode 100644
index 00000000..12455e20
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3524-drm-amdgpu-enable-gfx-clock-gating-for-rn.patch
@@ -0,0 +1,36 @@
+From 6a7dca8e4714a78040a4ac9aa99d3ed86b52bdf7 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Thu, 1 Aug 2019 16:21:07 +0800
+Subject: [PATCH 3524/4256] drm/amdgpu: enable gfx clock gating for rn
+
+Enable gfx cg/mg/cp etc clock gating.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index c092be45f5e2..d4cb7a66024e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1154,7 +1154,13 @@ static int soc15_common_early_init(void *handle)
+ 		break;
+ 	case CHIP_RENOIR:
+ 		adev->asic_funcs = &soc15_asic_funcs;
+-		adev->cg_flags = 0;
++		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
++				 AMD_CG_SUPPORT_GFX_MGLS |
++				 AMD_CG_SUPPORT_GFX_3D_CGCG |
++				 AMD_CG_SUPPORT_GFX_3D_CGLS |
++				 AMD_CG_SUPPORT_GFX_CGCG |
++				 AMD_CG_SUPPORT_GFX_CGLS |
++				 AMD_CG_SUPPORT_GFX_CP_LS;
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x91;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3525-drm-amdgpu-enable-mmhub-clock-gating-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3525-drm-amdgpu-enable-mmhub-clock-gating-for-rn.patch
new file mode 100644
index 00000000..74cc42c6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3525-drm-amdgpu-enable-mmhub-clock-gating-for-rn.patch
@@ -0,0 +1,32 @@
+From f757aff979a1eec2c8f8c17ab5bce27a75a40781 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Fri, 2 Aug 2019 15:04:27 +0800
+Subject: [PATCH 3525/4256] drm/amdgpu: enable mmhub clock gating for rn
+
+Enable mmhub midle grain and light sleep clock gating.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index d4cb7a66024e..7a7100a5dc1a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1160,7 +1160,9 @@ static int soc15_common_early_init(void *handle)
+ 				 AMD_CG_SUPPORT_GFX_3D_CGLS |
+ 				 AMD_CG_SUPPORT_GFX_CGCG |
+ 				 AMD_CG_SUPPORT_GFX_CGLS |
+-				 AMD_CG_SUPPORT_GFX_CP_LS;
++				 AMD_CG_SUPPORT_GFX_CP_LS |
++				 AMD_CG_SUPPORT_MC_MGCG |
++				 AMD_CG_SUPPORT_MC_LS;
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x91;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3526-drm-amdgpu-enable-sdma-clock-gating-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3526-drm-amdgpu-enable-sdma-clock-gating-for-rn.patch
new file mode 100644
index 00000000..39a4b64d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3526-drm-amdgpu-enable-sdma-clock-gating-for-rn.patch
@@ -0,0 +1,32 @@
+From ce71f69fe708d17f74eab44714507d1b01d24b22 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Fri, 2 Aug 2019 15:10:45 +0800
+Subject: [PATCH 3526/4256] drm/amdgpu: enable sdma clock gating for rn
+
+Enable sdma middle grain and light sleep clock gating.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 7a7100a5dc1a..6751c5f57913 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1162,7 +1162,9 @@ static int soc15_common_early_init(void *handle)
+ 				 AMD_CG_SUPPORT_GFX_CGLS |
+ 				 AMD_CG_SUPPORT_GFX_CP_LS |
+ 				 AMD_CG_SUPPORT_MC_MGCG |
+-				 AMD_CG_SUPPORT_MC_LS;
++				 AMD_CG_SUPPORT_MC_LS |
++				 AMD_CG_SUPPORT_SDMA_MGCG |
++				 AMD_CG_SUPPORT_SDMA_LS;
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x91;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3527-drm-amdgpu-enable-BIF-clock-gating-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3527-drm-amdgpu-enable-BIF-clock-gating-for-rn.patch
new file mode 100644
index 00000000..d73296b6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3527-drm-amdgpu-enable-BIF-clock-gating-for-rn.patch
@@ -0,0 +1,31 @@
+From 47266aa4ffae12e94bbe7822eb5368973375d566 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Fri, 2 Aug 2019 15:14:54 +0800
+Subject: [PATCH 3527/4256] drm/amdgpu: enable BIF clock gating for rn
+
+Enable BIF light sleep clock gating.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 6751c5f57913..25f55c793feb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1164,7 +1164,8 @@ static int soc15_common_early_init(void *handle)
+ 				 AMD_CG_SUPPORT_MC_MGCG |
+ 				 AMD_CG_SUPPORT_MC_LS |
+ 				 AMD_CG_SUPPORT_SDMA_MGCG |
+-				 AMD_CG_SUPPORT_SDMA_LS;
++				 AMD_CG_SUPPORT_SDMA_LS |
++				 AMD_CG_SUPPORT_BIF_LS;
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x91;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3528-drm-amdgpu-enable-HDP-clock-gating-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3528-drm-amdgpu-enable-HDP-clock-gating-for-rn.patch
new file mode 100644
index 00000000..f0fe6ff3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3528-drm-amdgpu-enable-HDP-clock-gating-for-rn.patch
@@ -0,0 +1,31 @@
+From c8d4108d1bffbb9dfb0855e1f9b691d5591814b9 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Fri, 2 Aug 2019 15:18:24 +0800
+Subject: [PATCH 3528/4256] drm/amdgpu: enable HDP clock gating for rn
+
+Enable HDP light sleep clock gating.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 25f55c793feb..ce101bcbe02c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1165,7 +1165,8 @@ static int soc15_common_early_init(void *handle)
+ 				 AMD_CG_SUPPORT_MC_LS |
+ 				 AMD_CG_SUPPORT_SDMA_MGCG |
+ 				 AMD_CG_SUPPORT_SDMA_LS |
+-				 AMD_CG_SUPPORT_BIF_LS;
++				 AMD_CG_SUPPORT_BIF_LS |
++				 AMD_CG_SUPPORT_HDP_LS;
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x91;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3529-drm-amdgpu-enable-rom-clock-gating-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3529-drm-amdgpu-enable-rom-clock-gating-for-rn.patch
new file mode 100644
index 00000000..5eace37d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3529-drm-amdgpu-enable-rom-clock-gating-for-rn.patch
@@ -0,0 +1,31 @@
+From ec971319eeb381c2c1b3a14780b920853170ac3e Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Fri, 2 Aug 2019 15:21:46 +0800
+Subject: [PATCH 3529/4256] drm/amdgpu: enable rom clock gating for rn
+
+Enable rom light sleep clock gating.
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index ce101bcbe02c..20d3120c6bc2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1166,7 +1166,8 @@ static int soc15_common_early_init(void *handle)
+ 				 AMD_CG_SUPPORT_SDMA_MGCG |
+ 				 AMD_CG_SUPPORT_SDMA_LS |
+ 				 AMD_CG_SUPPORT_BIF_LS |
+-				 AMD_CG_SUPPORT_HDP_LS;
++				 AMD_CG_SUPPORT_HDP_LS |
++				 AMD_CG_SUPPORT_ROM_MGCG;
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x91;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3530-drm-amdgpu-enable-vcn-clock-gating-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3530-drm-amdgpu-enable-vcn-clock-gating-for-rn.patch
new file mode 100644
index 00000000..441fe054
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3530-drm-amdgpu-enable-vcn-clock-gating-for-rn.patch
@@ -0,0 +1,31 @@
+From 4e4a4bd62aae4541b02149188d97ae874c40b03a Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Fri, 2 Aug 2019 15:24:45 +0800
+Subject: [PATCH 3530/4256] drm/amdgpu: enable vcn clock gating for rn
+
+Enable VCN middle grain clock gating.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 20d3120c6bc2..3b92da4ff69c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1167,7 +1167,8 @@ static int soc15_common_early_init(void *handle)
+ 				 AMD_CG_SUPPORT_SDMA_LS |
+ 				 AMD_CG_SUPPORT_BIF_LS |
+ 				 AMD_CG_SUPPORT_HDP_LS |
+-				 AMD_CG_SUPPORT_ROM_MGCG;
++				 AMD_CG_SUPPORT_ROM_MGCG |
++				 AMD_CG_SUPPORT_VCN_MGCG;
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x91;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3531-drm-amdgpu-enable-IH-clock-gating-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3531-drm-amdgpu-enable-IH-clock-gating-for-rn.patch
new file mode 100644
index 00000000..913a3c97
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3531-drm-amdgpu-enable-IH-clock-gating-for-rn.patch
@@ -0,0 +1,31 @@
+From a2b5c017df2546c6a51f5df90cc0ecbaff33dbf9 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Fri, 2 Aug 2019 15:27:11 +0800
+Subject: [PATCH 3531/4256] drm/amdgpu: enable IH clock gating for rn
+
+Enable IH clock gating during IH block initialized.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 3b92da4ff69c..81dd1ac6086d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1168,7 +1168,8 @@ static int soc15_common_early_init(void *handle)
+ 				 AMD_CG_SUPPORT_BIF_LS |
+ 				 AMD_CG_SUPPORT_HDP_LS |
+ 				 AMD_CG_SUPPORT_ROM_MGCG |
+-				 AMD_CG_SUPPORT_VCN_MGCG;
++				 AMD_CG_SUPPORT_VCN_MGCG |
++				 AMD_CG_SUPPORT_IH_CG;
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x91;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3532-drm-amdgpu-enable-athub-clock-gating-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3532-drm-amdgpu-enable-athub-clock-gating-for-rn.patch
new file mode 100644
index 00000000..0f70d87a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3532-drm-amdgpu-enable-athub-clock-gating-for-rn.patch
@@ -0,0 +1,32 @@
+From 4646bfd00c573733737ef88420ae81cb8e882706 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Fri, 2 Aug 2019 15:29:26 +0800
+Subject: [PATCH 3532/4256] drm/amdgpu: enable athub clock gating for rn
+
+Enable athub MG and LS clock gating.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 81dd1ac6086d..0552942ee732 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1169,7 +1169,9 @@ static int soc15_common_early_init(void *handle)
+ 				 AMD_CG_SUPPORT_HDP_LS |
+ 				 AMD_CG_SUPPORT_ROM_MGCG |
+ 				 AMD_CG_SUPPORT_VCN_MGCG |
+-				 AMD_CG_SUPPORT_IH_CG;
++				 AMD_CG_SUPPORT_IH_CG |
++				 AMD_CG_SUPPORT_ATHUB_LS |
++				 AMD_CG_SUPPORT_ATHUB_MGCG;
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x91;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3533-drm-amdgpu-enable-DF-clock-gating-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3533-drm-amdgpu-enable-DF-clock-gating-for-rn.patch
new file mode 100644
index 00000000..3f6270e6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3533-drm-amdgpu-enable-DF-clock-gating-for-rn.patch
@@ -0,0 +1,31 @@
+From 7d18887cc87dd111423aa679bc2853a67a7f5e46 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Fri, 2 Aug 2019 15:32:57 +0800
+Subject: [PATCH 3533/4256] drm/amdgpu: enable DF clock gating for rn
+
+Enable DF clock gating during DF IP early init.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 0552942ee732..6ab444d6be72 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1171,7 +1171,8 @@ static int soc15_common_early_init(void *handle)
+ 				 AMD_CG_SUPPORT_VCN_MGCG |
+ 				 AMD_CG_SUPPORT_IH_CG |
+ 				 AMD_CG_SUPPORT_ATHUB_LS |
+-				 AMD_CG_SUPPORT_ATHUB_MGCG;
++				 AMD_CG_SUPPORT_ATHUB_MGCG |
++				 AMD_CG_SUPPORT_DF_MGCG;
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x91;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3534-drm-amdgpu-mmhub1-set-mmhub-clock-gating-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3534-drm-amdgpu-mmhub1-set-mmhub-clock-gating-for-rn.patch
new file mode 100644
index 00000000..0065d79a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3534-drm-amdgpu-mmhub1-set-mmhub-clock-gating-for-rn.patch
@@ -0,0 +1,27 @@
+From 85d458ab1ccd445d31f5805c41d8761510d72733 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Mon, 29 Jul 2019 15:13:42 +0800
+Subject: [PATCH 3534/4256] drm/amdgpu/mmhub1: set mmhub clock gating for rn
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index 86b19a3e9b91..c476c9a1124d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -516,6 +516,7 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
+ 	case CHIP_VEGA12:
+ 	case CHIP_VEGA20:
+ 	case CHIP_RAVEN:
++	case CHIP_RENOIR:
+ 		mmhub_v1_0_update_medium_grain_clock_gating(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+ 		mmhub_v1_0_update_medium_grain_light_sleep(adev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3535-drm-amdgpu-sdma4-set-sdma-clock-gating-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3535-drm-amdgpu-sdma4-set-sdma-clock-gating-for-rn.patch
new file mode 100644
index 00000000..ca12f2e1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3535-drm-amdgpu-sdma4-set-sdma-clock-gating-for-rn.patch
@@ -0,0 +1,29 @@
+From fe4218c18e22e6c9403cacf7745dcb75bb7b655c Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Mon, 12 Aug 2019 15:25:18 -0500
+Subject: [PATCH 3535/4256] drm/amdgpu/sdma4: set sdma clock gating for rn
+
+Add support for SDMA clockgating on RN.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index e336dae8be33..528d8d026cc0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -2180,6 +2180,7 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
+ 	case CHIP_VEGA20:
+ 	case CHIP_RAVEN:
+ 	case CHIP_ARCTURUS:
++	case CHIP_RENOIR:
+ 		sdma_v4_0_update_medium_grain_clock_gating(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+ 		sdma_v4_0_update_medium_grain_light_sleep(adev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3536-drm-amdgpu-enable-SDMA-power-gating-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3536-drm-amdgpu-enable-SDMA-power-gating-for-rn.patch
new file mode 100644
index 00000000..f67bd793
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3536-drm-amdgpu-enable-SDMA-power-gating-for-rn.patch
@@ -0,0 +1,30 @@
+From 67cffba468e5fa7ad2a8a76f86aedf175bcd82f7 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Fri, 2 Aug 2019 15:42:41 +0800
+Subject: [PATCH 3536/4256] drm/amdgpu: enable SDMA power gating for rn
+
+Enable SDMA PG flag during device ip early init.
+
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 6ab444d6be72..5c211fa03328 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1173,7 +1173,7 @@ static int soc15_common_early_init(void *handle)
+ 				 AMD_CG_SUPPORT_ATHUB_LS |
+ 				 AMD_CG_SUPPORT_ATHUB_MGCG |
+ 				 AMD_CG_SUPPORT_DF_MGCG;
+-		adev->pg_flags = 0;
++		adev->pg_flags = AMD_PG_SUPPORT_SDMA;
+ 		adev->external_rev_id = adev->rev_id + 0x91;
+ 
+ 		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3537-drm-amd-powerplay-enable-renoir-dpm-feature.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3537-drm-amd-powerplay-enable-renoir-dpm-feature.patch
new file mode 100644
index 00000000..12723e8a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3537-drm-amd-powerplay-enable-renoir-dpm-feature.patch
@@ -0,0 +1,43 @@
+From 39a5fae0d6ae89236efc6549ffa0e65c3838025f Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Thu, 25 Jul 2019 13:56:51 +0800
+Subject: [PATCH 3537/4256] drm/amd/powerplay: enable renoir dpm feature
+
+enable the dpm feature for the renoir.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Aaron Liu <aaron.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 --------
+ 1 file changed, 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index ebfd631521c8..808c8e02a650 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -768,10 +768,6 @@ static int smu_late_init(void *handle)
+ 	if (!smu->pm_enabled)
+ 		return 0;
+ 
+-	/* To be removed after dpm is enabled */
+-	if (adev->asic_type == CHIP_RENOIR)
+-		return 0;
+-
+ 	mutex_lock(&smu->mutex);
+ 	smu_handle_task(&adev->smu,
+ 			smu->smu_dpm.dpm_level,
+@@ -1275,10 +1271,6 @@ static int smu_hw_init(void *handle)
+ 	if (!smu->pm_enabled)
+ 		return 0;
+ 
+-	/* To be removed after dpm is enabled */
+-	if (adev->asic_type == CHIP_RENOIR)
+-		return 0;
+-
+ 	ret = smu_feature_init_dpm(smu);
+ 	if (ret)
+ 		goto failed;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3538-drm-amd-powerplay-Disable-renoir-smu-feature-retrive.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3538-drm-amd-powerplay-Disable-renoir-smu-feature-retrive.patch
new file mode 100644
index 00000000..0272245c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3538-drm-amd-powerplay-Disable-renoir-smu-feature-retrive.patch
@@ -0,0 +1,38 @@
+From 5c97579c6865838d476e61ea7c21a672f0358ec0 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Fri, 9 Aug 2019 14:17:40 +0800
+Subject: [PATCH 3538/4256] drm/amd/powerplay: Disable renoir smu feature
+ retrive for the moment
+
+To avoid the dpm frequence range get failed when DPM enabled and it
+will be enabled later once handle well the feature bit map struct.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 808c8e02a650..6f435d60fe86 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -630,10 +630,14 @@ int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_ma
+ 
+ int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
+ {
++	struct amdgpu_device *adev = smu->adev;
+ 	struct smu_feature *feature = &smu->smu_feature;
+ 	int feature_id;
+ 	int ret = 0;
+ 
++	if (adev->flags & AMD_IS_APU)
++		return 0;
++
+ 	feature_id = smu_feature_get_index(smu, mask);
+ 	if (feature_id < 0)
+ 		return 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3539-drm-amdgpu-update-gc-sdma-goldensetting-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3539-drm-amdgpu-update-gc-sdma-goldensetting-for-rn.patch
new file mode 100644
index 00000000..e803f609
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3539-drm-amdgpu-update-gc-sdma-goldensetting-for-rn.patch
@@ -0,0 +1,61 @@
+From 39bd031030db80e16649e1d64a251f312515721f Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Wed, 7 Aug 2019 09:57:08 +0800
+Subject: [PATCH 3539/4256] drm/amdgpu: update gc/sdma goldensetting for rn
+
+This patch updates gc/sdma goldensetting for renoir
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 7 +++----
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
+ 2 files changed, 5 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index b3defa07b7c8..2762ae45f3af 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -619,12 +619,11 @@ static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] =
+ 
+ static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] =
+ {
+-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
+-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22010042),
+-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22010042),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
+@@ -782,7 +781,7 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
+ 		soc15_program_register_sequence(adev,
+ 						golden_settings_gc_9_1_rn,
+ 						ARRAY_SIZE(golden_settings_gc_9_1_rn));
+-		break;
++		return; /* for renoir, don't need common goldensetting */
+ 	default:
+ 		break;
+ 	}
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 528d8d026cc0..d06371f7791f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -244,8 +244,8 @@ static const struct soc15_reg_golden golden_settings_sdma_arct[] =
+ static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
+ 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
+ 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
+-	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003002),
+-	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003002),
++	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
++	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002),
+ 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+ 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
+ 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3540-drm-amdgpu-enable-VCN-DPG-for-Renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3540-drm-amdgpu-enable-VCN-DPG-for-Renoir.patch
new file mode 100644
index 00000000..f50cd059
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3540-drm-amdgpu-enable-VCN-DPG-for-Renoir.patch
@@ -0,0 +1,33 @@
+From e5c038ce34f2cd91d0451a52ed930af85474c49f Mon Sep 17 00:00:00 2001
+From: Thong Thai <thong.thai@amd.com>
+Date: Thu, 15 Aug 2019 14:00:30 -0400
+Subject: [PATCH 3540/4256] drm/amdgpu: enable VCN DPG for Renoir
+
+This will enable indirect SRAM loading for VCN DPG mode initialization.
+
+Signed-off-by: Thong Thai <thong.thai@amd.com>
+Reviewed-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Prike Liang <Prike.Liang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 5c211fa03328..fe2212df12a3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1173,7 +1173,9 @@ static int soc15_common_early_init(void *handle)
+ 				 AMD_CG_SUPPORT_ATHUB_LS |
+ 				 AMD_CG_SUPPORT_ATHUB_MGCG |
+ 				 AMD_CG_SUPPORT_DF_MGCG;
+-		adev->pg_flags = AMD_PG_SUPPORT_SDMA;
++		adev->pg_flags = AMD_PG_SUPPORT_SDMA |
++				 AMD_PG_SUPPORT_VCN |
++				 AMD_PG_SUPPORT_VCN_DPG;
+ 		adev->external_rev_id = adev->rev_id + 0x91;
+ 
+ 		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3541-drm-amdgpu-correct-ras-error-count-type.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3541-drm-amdgpu-correct-ras-error-count-type.patch
new file mode 100644
index 00000000..ef33cf35
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3541-drm-amdgpu-correct-ras-error-count-type.patch
@@ -0,0 +1,93 @@
+From f53d8dd9e21fd2833db36302e1d4205fb2cc9a05 Mon Sep 17 00:00:00 2001
+From: Guchun Chen <guchun.chen@amd.com>
+Date: Fri, 16 Aug 2019 15:06:52 +0800
+Subject: [PATCH 3541/4256] drm/amdgpu: correct ras error count type
+
+Use unsigned long type for the same ras count variable.
+This will avoid overflow on 64 bit system.
+
+Change-Id: I011406d81bad69a65433b63960e1691c4959bbc5
+Signed-off-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 +++---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 2 +-
+ 4 files changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+index acd44860c7d5..0c52d1d5f011 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+@@ -357,7 +357,7 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev,
+ {
+ 	struct amdgpu_ctx *ctx;
+ 	struct amdgpu_ctx_mgr *mgr;
+-	uint32_t ras_counter;
++	unsigned long ras_counter;
+ 
+ 	if (!fpriv)
+ 		return -EINVAL;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
+index f22da13dfffd..442ee4c9e53e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
+@@ -51,8 +51,8 @@ struct amdgpu_ctx {
+ 	enum drm_sched_priority		override_priority;
+ 	struct mutex			lock;
+ 	atomic_t			guilty;
+-	uint32_t			ras_counter_ce;
+-	uint32_t			ras_counter_ue;
++	unsigned long			ras_counter_ce;
++	unsigned long			ras_counter_ue;
+ };
+ 
+ struct amdgpu_ctx_mgr {
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 50c13b02d234..df4b9ae39c5e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -686,7 +686,7 @@ int amdgpu_ras_error_cure(struct amdgpu_device *adev,
+ }
+ 
+ /* get the total error counts on all IPs */
+-int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
++unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
+ 		bool is_ce)
+ {
+ 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+@@ -694,7 +694,7 @@ int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
+ 	struct ras_err_data data = {0, 0};
+ 
+ 	if (!con)
+-		return -EINVAL;
++		return 0;
+ 
+ 	list_for_each_entry(obj, &con->head, node) {
+ 		struct ras_query_if info = {
+@@ -702,7 +702,7 @@ int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
+ 		};
+ 
+ 		if (amdgpu_ras_error_query(adev, &info))
+-			return -EINVAL;
++			return 0;
+ 
+ 		data.ce_count += info.ce_count;
+ 		data.ue_count += info.ue_count;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index 2765f2dbb1e6..02a51e3dfa14 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -484,7 +484,7 @@ int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
+ void amdgpu_ras_resume(struct amdgpu_device *adev);
+ void amdgpu_ras_suspend(struct amdgpu_device *adev);
+ 
+-int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
++unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
+ 		bool is_ce);
+ 
+ /* error handling functions */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3542-drm-amdkfd-updated-read-to-set-errno-to-eagain.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3542-drm-amdkfd-updated-read-to-set-errno-to-eagain.patch
new file mode 100644
index 00000000..27c34ee4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3542-drm-amdkfd-updated-read-to-set-errno-to-eagain.patch
@@ -0,0 +1,35 @@
+From 7c5a4b52de95b3b49f5cc40a9a3b7ddb0e3d063e Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Mon, 12 Aug 2019 11:47:28 -0400
+Subject: [PATCH 3542/4256] drm/amdkfd: updated read to set errno to eagain
+
+User space requries -1 and errno set to EAGAIN on kfifo_to_user
+failure or 0 bytes copy.
+
+Change-Id: I34985ff641b21568e12bf5534bd39d1d5d744364
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
+index 210cccdeed81..df42b1dd8b4b 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
+@@ -70,9 +70,10 @@ static ssize_t kfd_dbg_ev_read(struct file *filep, char __user *user,
+ 
+ 	ret = kfifo_to_user(&dpd->fifo, user, size, &copied);
+ 
+-	if (ret) {
+-		pr_debug("KFD DEBUG EVENT: Failed to read poll fd (%i)\n", ret);
+-		return ret;
++	if (ret || !copied) {
++		pr_debug("KFD DEBUG EVENT: Failed to read poll fd (%i) (%i)\n",
++								ret, copied);
++		return ret ? ret : -EAGAIN;
+ 	}
+ 
+ 	return copied;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3543-drm-amdkfd-add-new-queue-status.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3543-drm-amdkfd-add-new-queue-status.patch
new file mode 100644
index 00000000..b3cc259a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3543-drm-amdkfd-add-new-queue-status.patch
@@ -0,0 +1,100 @@
+From e247f8244befaab5656bf6f5ec0dc873bc1f809b Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Wed, 7 Aug 2019 11:22:18 -0400
+Subject: [PATCH 3543/4256] drm/amdkfd: add new queue status
+
+add new queue status to avoid aba problem for debugger
+
+Change-Id: Ibf1c07758512b56cf5ad2a49b46006cffab0f905
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c    | 16 ++++++++++++++--
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h            |  1 +
+ .../drm/amd/amdkfd/kfd_process_queue_manager.c   |  1 +
+ include/uapi/linux/kfd_ioctl.h                   |  1 +
+ 4 files changed, 17 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
+index df42b1dd8b4b..1681107a2aa6 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
+@@ -97,6 +97,10 @@ static int kfd_dbg_ev_release(struct inode *inode, struct file *filep)
+ 	((x) = ((x) & ~(KFD_DBG_EV_STATUS_TRAP			\
+ 		| KFD_DBG_EV_STATUS_VMFAULT)) | (e))
+ 
++#define KFD_DBG_EV_SET_NEW_QUEUE_STATE(x, n)			\
++	((x) = (n) ? (x) | KFD_DBG_EV_STATUS_NEW_QUEUE :	\
++		(x) & ~KFD_DBG_EV_STATUS_NEW_QUEUE)
++
+ int kfd_dbg_ev_query_debug_event(struct kfd_process_device *pdd,
+ 		      unsigned int *queue_id,
+ 		      unsigned int flags,
+@@ -126,8 +130,12 @@ int kfd_dbg_ev_query_debug_event(struct kfd_process_device *pdd,
+ 					  q->properties.debug_event_type);
+ 		KFD_DBG_EV_SET_SUSPEND_STATE(*event_status,
+ 					  q->properties.is_suspended);
+-		if (flags & KFD_DBG_EV_FLAG_CLEAR_STATUS)
++		KFD_DBG_EV_SET_NEW_QUEUE_STATE(*event_status,
++					  q->properties.is_new);
++		if (flags & KFD_DBG_EV_FLAG_CLEAR_STATUS) {
++			q->properties.is_new = false;
+ 			q->properties.debug_event_type = 0;
++		}
+ 		goto out;
+ 
+ 	} else {
+@@ -142,9 +150,13 @@ int kfd_dbg_ev_query_debug_event(struct kfd_process_device *pdd,
+ 					pqn->q->properties.debug_event_type);
+ 				KFD_DBG_EV_SET_SUSPEND_STATE(*event_status,
+ 					pqn->q->properties.is_suspended);
+-				if (flags & KFD_DBG_EV_FLAG_CLEAR_STATUS)
++				KFD_DBG_EV_SET_NEW_QUEUE_STATE(*event_status,
++					pqn->q->properties.is_new);
++				if (flags & KFD_DBG_EV_FLAG_CLEAR_STATUS) {
++					pqn->q->properties.is_new = false;
+ 					pqn->q->properties.debug_event_type
+ 									= 0;
++				}
+ 				goto out;
+ 			}
+ 		}
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index 73aa6a3330eb..5d3cffc9d0ec 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -493,6 +493,7 @@ struct queue_properties {
+ 	bool is_evicted;
+ 	bool is_suspended;
+ 	bool is_active;
++	bool is_new;
+ 	/* Not relevant for user mode queues in cp scheduling */
+ 	unsigned int vmid;
+ 	/* Relevant only for sdma queues*/
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+index 7a61a5b09ed8..d47ab53d613b 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+@@ -318,6 +318,7 @@ int pqm_create_queue(struct process_queue_manager *pqm,
+ 
+ 	if (q) {
+ 		pr_debug("PQM done creating queue\n");
++		q->properties.is_new = true;
+ 		print_queue_properties(&q->properties);
+ 	}
+ 
+diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
+index 42551e2c6d59..86805463e1d3 100644
+--- a/include/uapi/linux/kfd_ioctl.h
++++ b/include/uapi/linux/kfd_ioctl.h
+@@ -191,6 +191,7 @@ struct kfd_ioctl_dbg_wave_control_args {
+ #define	KFD_DBG_EV_STATUS_TRAP		1
+ #define	KFD_DBG_EV_STATUS_VMFAULT	2
+ #define	KFD_DBG_EV_STATUS_SUSPENDED	4
++#define KFD_DBG_EV_STATUS_NEW_QUEUE	8
+ #define	KFD_DBG_EV_FLAG_CLEAR_STATUS	1
+ 
+ #define KFD_INVALID_QUEUEID	0xffffffff
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3544-drm-amd-powerplay-fix-message-of-SetHardMinByFreq-fa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3544-drm-amd-powerplay-fix-message-of-SetHardMinByFreq-fa.patch
new file mode 100644
index 00000000..6e4c82d0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3544-drm-amd-powerplay-fix-message-of-SetHardMinByFreq-fa.patch
@@ -0,0 +1,57 @@
+From 3d04de493f2365082964bb9f9701daef269e17fb Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Tue, 13 Aug 2019 10:25:25 +0800
+Subject: [PATCH 3544/4256] drm/amd/powerplay: fix message of SetHardMinByFreq
+ failed when feature is disabled
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+the direct send message to smc to set hard clokc will failed
+when smc clock dpm feature is disabled.
+so use function of smu_set_hard_freq_range to replace it.
+the function will check feature enablement.
+
+eg: when uclk (mclk) dpm feature is disabled on navi10
+[  300.675901] amdgpu: [powerplay] failed send message: SetHardMinByFreq(28)
+   param: 0x00020064 response 0xfffffffb
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 11 +----------
+ 1 file changed, 1 insertion(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index d3500a5ef720..46d905daab38 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1282,7 +1282,6 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
+ 	int ret = 0;
+ 	enum smu_clk_type clk_select = 0;
+ 	uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
+-	int clk_id;
+ 
+ 	if (!smu->pm_enabled)
+ 		return -EINVAL;
+@@ -1317,16 +1316,8 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
+ 		if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
+ 			return 0;
+ 
+-		clk_id = smu_clk_get_index(smu, clk_select);
+-		if (clk_id < 0) {
+-			ret = -EINVAL;
+-			goto failed;
+-		}
+-
+-
+ 		mutex_lock(&smu->mutex);
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
+-			(clk_id << 16) | clk_freq);
++		ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0);
+ 		mutex_unlock(&smu->mutex);
+ 
+ 		if(clk_select == SMU_UCLK)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3545-drm-amdgpu-fix-typo-error-amdgput-amdgpu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3545-drm-amdgpu-fix-typo-error-amdgput-amdgpu.patch
new file mode 100644
index 00000000..d138bcba
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3545-drm-amdgpu-fix-typo-error-amdgput-amdgpu.patch
@@ -0,0 +1,79 @@
+From ccd737f9d243d418b8964597e54b19b20bd8f02f Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Tue, 13 Aug 2019 16:48:28 +0800
+Subject: [PATCH 3545/4256] drm/amdgpu: fix typo error amdgput -> amdgpu
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+fix typo error:
+change function name from "amdgput_ctx_total_num_entities" to
+"amdgpu_ctx_total_num_entities".
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+index 0c52d1d5f011..c32e62c86113 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+@@ -43,7 +43,7 @@ const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = {
+ 	[AMDGPU_HW_IP_VCN_JPEG]	=	1,
+ };
+ 
+-static int amdgput_ctx_total_num_entities(void)
++static int amdgpu_ctx_total_num_entities(void)
+ {
+ 	unsigned i, num_entities = 0;
+ 
+@@ -74,7 +74,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
+ 			   struct drm_file *filp,
+ 			   struct amdgpu_ctx *ctx)
+ {
+-	unsigned num_entities = amdgput_ctx_total_num_entities();
++	unsigned num_entities = amdgpu_ctx_total_num_entities();
+ 	unsigned i, j, k;
+ 	int r;
+ 
+@@ -210,7 +210,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
+ static void amdgpu_ctx_fini(struct kref *ref)
+ {
+ 	struct amdgpu_ctx *ctx = container_of(ref, struct amdgpu_ctx, refcount);
+-	unsigned num_entities = amdgput_ctx_total_num_entities();
++	unsigned num_entities = amdgpu_ctx_total_num_entities();
+ 	struct amdgpu_device *adev = ctx->adev;
+ 	unsigned i, j;
+ 
+@@ -527,7 +527,7 @@ struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
+ void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
+ 				  enum drm_sched_priority priority)
+ {
+-	unsigned num_entities = amdgput_ctx_total_num_entities();
++	unsigned num_entities = amdgpu_ctx_total_num_entities();
+ 	enum drm_sched_priority ctx_prio;
+ 	unsigned i;
+ 
+@@ -575,7 +575,7 @@ void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
+ 
+ long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout)
+ {
+-	unsigned num_entities = amdgput_ctx_total_num_entities();
++	unsigned num_entities = amdgpu_ctx_total_num_entities();
+ 	struct amdgpu_ctx *ctx;
+ 	struct idr *idp;
+ 	uint32_t id, i;
+@@ -597,7 +597,7 @@ long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout)
+ 
+ void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr)
+ {
+-	unsigned num_entities = amdgput_ctx_total_num_entities();
++	unsigned num_entities = amdgpu_ctx_total_num_entities();
+ 	struct amdgpu_ctx *ctx;
+ 	struct idr *idp;
+ 	uint32_t id, i;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3546-drm-amdgpu-use-exiting-amdgpu_ctx_total_num_entities.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3546-drm-amdgpu-use-exiting-amdgpu_ctx_total_num_entities.patch
new file mode 100644
index 00000000..e222f84b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3546-drm-amdgpu-use-exiting-amdgpu_ctx_total_num_entities.patch
@@ -0,0 +1,36 @@
+From f29d3ae78e349cfc26b38fa284bbdd398ad6ded6 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Tue, 13 Aug 2019 16:52:04 +0800
+Subject: [PATCH 3546/4256] drm/amdgpu: use exiting
+ amdgpu_ctx_total_num_entities function
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+simplify driver code.
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 5 +----
+ 1 file changed, 1 insertion(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+index c32e62c86113..22097a3a5bc5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+@@ -292,10 +292,7 @@ static void amdgpu_ctx_do_release(struct kref *ref)
+ 
+ 	ctx = container_of(ref, struct amdgpu_ctx, refcount);
+ 
+-	num_entities = 0;
+-	for (i = 0; i < AMDGPU_HW_IP_NUM; i++)
+-		num_entities += amdgpu_ctx_num_entities[i];
+-
++	num_entities = amdgpu_ctx_total_num_entities();
+ 	for (i = 0; i < num_entities; i++)
+ 		drm_sched_entity_destroy(&ctx->entities[0][i].entity);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3547-drm-amdgpu-implement-querying-ras-error-count-for-mm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3547-drm-amdgpu-implement-querying-ras-error-count-for-mm.patch
new file mode 100644
index 00000000..03d32bff
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3547-drm-amdgpu-implement-querying-ras-error-count-for-mm.patch
@@ -0,0 +1,369 @@
+From 3bb263d93e87ba5c1ec31e7aa1d8b9265f86a2db Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Tue, 13 Aug 2019 15:46:03 +0800
+Subject: [PATCH 3547/4256] drm/amdgpu: implement querying ras error count for
+ mmhub
+
+get mmhub ea ras error count by accessing EDC_CNT register
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c       |  55 +++++
+ .../asic_reg/mmhub/mmhub_9_4_0_offset.h       |  21 ++
+ .../asic_reg/mmhub/mmhub_9_4_0_sh_mask.h      | 222 ++++++++++++++++++
+ 3 files changed, 298 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index c476c9a1124d..732aba77ab73 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -21,11 +21,13 @@
+  *
+  */
+ #include "amdgpu.h"
++#include "amdgpu_ras.h"
+ #include "mmhub_v1_0.h"
+ 
+ #include "mmhub/mmhub_1_0_offset.h"
+ #include "mmhub/mmhub_1_0_sh_mask.h"
+ #include "mmhub/mmhub_1_0_default.h"
++#include "mmhub/mmhub_9_4_0_offset.h"
+ #include "vega10_enum.h"
+ 
+ #include "soc15_common.h"
+@@ -33,6 +35,9 @@
+ #define mmDAGB0_CNTL_MISC2_RV 0x008f
+ #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
+ 
++#define EA_EDC_CNT_MASK 0x3
++#define EA_EDC_CNT_SHIFT 0x2
++
+ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
+ {
+ 	u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);
+@@ -558,6 +563,56 @@ void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
+ static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev,
+ 					   void *ras_error_status)
+ {
++	int i;
++	uint32_t ea0_edc_cnt, ea0_edc_cnt2;
++	uint32_t ea1_edc_cnt, ea1_edc_cnt2;
++	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
++
++	/* EDC CNT will be cleared automatically after read */
++	ea0_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT_VG20);
++	ea0_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20);
++	ea1_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT_VG20);
++	ea1_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20);
++
++	/* error count of each error type is recorded by 2 bits,
++	 * ce and ue count in EDC_CNT
++	 */
++	for (i = 0; i < 5; i++) {
++		err_data->ce_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
++		err_data->ce_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
++		ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
++		ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
++		err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
++		err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
++		ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
++		ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
++	}
++	/* successive ue count in EDC_CNT */
++	for (i = 0; i < 5; i++) {
++		err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
++		err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
++		ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
++		ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
++	}
++
++	/* ce and ue count in EDC_CNT2 */
++	for (i = 0; i < 3; i++) {
++		err_data->ce_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
++		err_data->ce_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
++		ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
++		ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
++		err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
++		err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
++		ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
++		ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
++	}
++	/* successive ue count in EDC_CNT2 */
++	for (i = 0; i < 6; i++) {
++		err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
++		err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
++		ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
++		ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
++	}
+ }
+ 
+ const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h
+index 8f515875a34d..f2ae3a58949e 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h
+@@ -21,6 +21,27 @@
+ #ifndef _mmhub_9_4_0_OFFSET_HEADER
+ #define _mmhub_9_4_0_OFFSET_HEADER
+ 
++/* MMEA */
++#define mmMMEA0_SDP_ARB_FINAL_VG20                                                                     0x01ee
++#define mmMMEA0_SDP_ARB_FINAL_VG20_BASE_IDX                                                            0
++#define mmMMEA0_EDC_CNT_VG20                                                                           0x0206
++#define mmMMEA0_EDC_CNT_VG20_BASE_IDX                                                                  0
++#define mmMMEA0_EDC_CNT2_VG20                                                                          0x0207
++#define mmMMEA0_EDC_CNT2_VG20_BASE_IDX                                                                 0
++#define mmMMEA0_EDC_MODE_VG20                                                                          0x0210
++#define mmMMEA0_EDC_MODE_VG20_BASE_IDX                                                                 0
++#define mmMMEA0_ERR_STATUS_VG20                                                                        0x0211
++#define mmMMEA0_ERR_STATUS_VG20_BASE_IDX                                                               0
++#define mmMMEA1_SDP_ARB_FINAL_VG20                                                                     0x032e
++#define mmMMEA1_SDP_ARB_FINAL_VG20_BASE_IDX                                                            0
++#define mmMMEA1_EDC_CNT_VG20                                                                           0x0346
++#define mmMMEA1_EDC_CNT_VG20_BASE_IDX                                                                  0
++#define mmMMEA1_EDC_CNT2_VG20                                                                          0x0347
++#define mmMMEA1_EDC_CNT2_VG20_BASE_IDX                                                                 0
++#define mmMMEA1_EDC_MODE_VG20                                                                          0x0350
++#define mmMMEA1_EDC_MODE_VG20_BASE_IDX                                                                 0
++#define mmMMEA1_ERR_STATUS_VG20                                                                        0x0351
++#define mmMMEA1_ERR_STATUS_VG20_BASE_IDX                                                               0
+ 
+ // addressBlock: mmhub_utcl2_vmsharedpfdec
+ // base address: 0x6a040
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h
+index 0a6b072d191e..c24259ed12a1 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h
+@@ -21,6 +21,228 @@
+ #ifndef _mmhub_9_4_0_SH_MASK_HEADER
+ #define _mmhub_9_4_0_SH_MASK_HEADER
+ 
++//MMEA0_SDP_ARB_FINAL
++#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
++#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
++#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
++#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
++#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
++#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
++#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
++#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
++#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
++#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
++#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
++#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
++#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
++//MMEA0_EDC_CNT
++#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
++#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
++#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
++#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
++#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
++#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
++#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
++#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
++#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
++#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
++#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
++#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
++#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
++#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
++#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
++#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
++#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
++#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
++#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
++#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
++#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
++#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
++#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
++#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
++#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
++#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
++#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
++#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
++#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
++#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
++//MMEA0_EDC_CNT2
++#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
++#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
++#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
++#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
++#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
++#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
++#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
++#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
++#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT                                                            0x10
++#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT                                                            0x12
++#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT                                                            0x14
++#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT                                                            0x16
++#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
++#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
++#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
++#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
++#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
++#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
++#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
++#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
++#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK                                                              0x00030000L
++#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK                                                              0x000C0000L
++#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK                                                              0x00300000L
++#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK                                                              0x00C00000L
++//MMEA0_EDC_MODE
++#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
++#define MMEA0_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
++#define MMEA0_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
++#define MMEA0_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
++#define MMEA0_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
++#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
++#define MMEA0_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
++#define MMEA0_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
++#define MMEA0_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
++#define MMEA0_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
++//MMEA0_ERR_STATUS
++#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
++#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
++#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
++#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
++#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
++#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
++#define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
++#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
++#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
++#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
++#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
++#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
++#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
++#define MMEA0_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
++//MMEA1_SDP_ARB_FINAL
++#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
++#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
++#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
++#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
++#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
++#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
++#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
++#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
++#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
++#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
++#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
++#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
++#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
++//MMEA1_EDC_CNT
++#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
++#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
++#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
++#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
++#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
++#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
++#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
++#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
++#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
++#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
++#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
++#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
++#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
++#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
++#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
++#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
++#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
++#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
++#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
++#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
++#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
++#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
++#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
++#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
++#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
++#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
++#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
++#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
++#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
++#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
++//MMEA1_EDC_CNT2
++#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
++#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
++#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
++#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
++#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
++#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
++#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
++#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
++#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT                                                            0x10
++#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT                                                            0x12
++#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT                                                            0x14
++#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT                                                            0x16
++#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
++#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
++#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
++#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
++#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
++#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
++#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
++#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
++#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK                                                              0x00030000L
++#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK                                                              0x000C0000L
++#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK                                                              0x00300000L
++#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK                                                              0x00C00000L
++//MMEA1_EDC_MODE
++#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
++#define MMEA1_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
++#define MMEA1_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
++#define MMEA1_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
++#define MMEA1_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
++#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
++#define MMEA1_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
++#define MMEA1_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
++#define MMEA1_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
++#define MMEA1_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
++//MMEA1_ERR_STATUS
++#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
++#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
++#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
++#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
++#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
++#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
++#define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
++#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
++#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
++#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
++#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
++#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
++#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
++#define MMEA1_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
+ 
+ // addressBlock: mmhub_utcl2_vmsharedpfdec
+ //MC_VM_XGMI_LFB_CNTL
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3548-drm-amdgpu-powerplay-fix-spelling-mistake-unsuported.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3548-drm-amdgpu-powerplay-fix-spelling-mistake-unsuported.patch
new file mode 100644
index 00000000..e3cf97ea
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3548-drm-amdgpu-powerplay-fix-spelling-mistake-unsuported.patch
@@ -0,0 +1,31 @@
+From 70b095ce1966a4731e205986ce7fbb93e23ff3ab Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Tue, 13 Aug 2019 11:33:40 +0100
+Subject: [PATCH 3548/4256] drm/amdgpu/powerplay: fix spelling mistake
+ "unsuported" -> "unsupported"
+
+There is a spelling mistake in a pr_err error message. Fix it. Also
+add a space after a comma to clean up a checkpatch warning.
+
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 46d905daab38..deca9f85764c 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -288,7 +288,7 @@ static int smu_v11_0_check_fw_version(struct smu_context *smu)
+ 		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV14;
+ 		break;
+ 	default:
+-		pr_err("smu unsuported asic type:%d.\n",smu->adev->asic_type);
++		pr_err("smu unsupported asic type:%d.\n", smu->adev->asic_type);
+ 		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_INV;
+ 		break;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3549-drm-amdgpu-MODULE_FIRMWARE-requires-linux-module.h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3549-drm-amdgpu-MODULE_FIRMWARE-requires-linux-module.h.patch
new file mode 100644
index 00000000..fa9bbbf4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3549-drm-amdgpu-MODULE_FIRMWARE-requires-linux-module.h.patch
@@ -0,0 +1,28 @@
+From d004179a83d95de96febc2e6a27025c9f92561db Mon Sep 17 00:00:00 2001
+From: Stephen Rothwell <sfr@canb.auug.org.au>
+Date: Tue, 13 Aug 2019 18:10:38 +1000
+Subject: [PATCH 3549/4256] drm/amdgpu: MODULE_FIRMWARE requires linux/module.h
+
+Fixes: 6a7a0bdbfa0c ("drm/amdgpu: add psp_v12_0 for renoir (v2)")
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+index fd55baa6ea31..c72e43f8e0be 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+@@ -21,6 +21,7 @@
+  */
+ 
+ #include <linux/firmware.h>
++#include <linux/module.h>
+ #include "amdgpu.h"
+ #include "amdgpu_psp.h"
+ #include "amdgpu_ucode.h"
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3550-drm-scheduler-use-job-count-instead-of-peek.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3550-drm-scheduler-use-job-count-instead-of-peek.patch
new file mode 100644
index 00000000..4cfe026d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3550-drm-scheduler-use-job-count-instead-of-peek.patch
@@ -0,0 +1,45 @@
+From e7009d24434c1bd93ac221b2d872911e79fa1fd6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Fri, 9 Aug 2019 17:27:21 +0200
+Subject: [PATCH 3550/4256] drm/scheduler: use job count instead of peek
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The spsc_queue_peek function is accessing queue->head which belongs to
+the consumer thread and shouldn't be accessed by the producer
+
+This is fixing a rare race condition when destroying entities.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Monk.liu@amd.com
+---
+ drivers/gpu/drm/scheduler/sched_entity.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c
+index 35ddbec1375a..671c90f34ede 100644
+--- a/drivers/gpu/drm/scheduler/sched_entity.c
++++ b/drivers/gpu/drm/scheduler/sched_entity.c
+@@ -95,7 +95,7 @@ static bool drm_sched_entity_is_idle(struct drm_sched_entity *entity)
+ 	rmb(); /* for list_empty to work without lock */
+ 
+ 	if (list_empty(&entity->list) ||
+-	    spsc_queue_peek(&entity->job_queue) == NULL)
++	    spsc_queue_count(&entity->job_queue) == 0)
+ 		return true;
+ 
+ 	return false;
+@@ -281,7 +281,7 @@ void drm_sched_entity_fini(struct drm_sched_entity *entity)
+ 	/* Consumption of existing IBs wasn't completed. Forcefully
+ 	 * remove them here.
+ 	 */
+-	if (spsc_queue_peek(&entity->job_queue)) {
++	if (spsc_queue_count(&entity->job_queue)) {
+ 		if (sched) {
+ 			/* Park the kernel for a moment to make sure it isn't processing
+ 			 * our enity.
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3551-drm-amd-display-Add-PIXEL_RATE-control-regs-for-more.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3551-drm-amd-display-Add-PIXEL_RATE-control-regs-for-more.patch
new file mode 100644
index 00000000..b2616465
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3551-drm-amd-display-Add-PIXEL_RATE-control-regs-for-more.patch
@@ -0,0 +1,79 @@
+From a8ff8f2b90598b4ab827dc8d35703c5d03869499 Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Sat, 22 Jun 2019 18:52:41 -0400
+Subject: [PATCH 3551/4256] drm/amd/display: Add PIXEL_RATE control regs for
+ more instances
+
+For use by future ASICs
+
+(cherry picked from commit 08a026f1ae782884b18dfa108de019a5a985e92a)
+Signed-off-by: Sung Lee <sung.lee@amd.com>
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dce/dce_hwseq.h    | 25 +++++++++++++++----
+ 1 file changed, 20 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+index 245b80b92681..f62eb2e43d7f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+@@ -62,6 +62,10 @@
+ 	SRII(BLND_CONTROL, BLND, 4), \
+ 	SRII(BLND_CONTROL, BLND, 5)
+ 
++#define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \
++	SRII(PIXEL_RATE_CNTL, blk, inst), \
++	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst)
++
+ #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \
+ 	SRII(PIXEL_RATE_CNTL, blk, 0), \
+ 	SRII(PIXEL_RATE_CNTL, blk, 1), \
+@@ -151,7 +155,10 @@
+ 	SR(DCCG_GATE_DISABLE_CNTL2), \
+ 	SR(DCFCLK_CNTL),\
+ 	SR(DCFCLK_CNTL), \
+-	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
++	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
++
++
++#define MMHUB_DCN_REG_LIST()\
+ 	/* todo:  get these from GVM instead of reading registers ourselves */\
+ 	MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
+ 	MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
+@@ -166,10 +173,14 @@
+ 	MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
+ 	MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
+ 
++
+ #define HWSEQ_DCN1_REG_LIST()\
+ 	HWSEQ_DCN_REG_LIST(), \
+-	HWSEQ_PIXEL_RATE_REG_LIST(OTG), \
+-	HWSEQ_PHYPLL_REG_LIST(OTG), \
++	MMHUB_DCN_REG_LIST(), \
++	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
++	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
++	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
++	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
+ 	SR(DCHUBBUB_SDPIF_FB_BASE),\
+ 	SR(DCHUBBUB_SDPIF_FB_OFFSET),\
+ 	SR(DCHUBBUB_SDPIF_AGP_BASE),\
+@@ -202,8 +213,12 @@
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define HWSEQ_DCN2_REG_LIST()\
+ 	HWSEQ_DCN_REG_LIST(), \
+-	HWSEQ_PIXEL_RATE_REG_LIST(OTG), \
+-	HWSEQ_PHYPLL_REG_LIST(OTG), \
++	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
++	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
++	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
++	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
++	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \
++	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \
+ 	SR(MICROSECOND_TIME_BASE_DIV), \
+ 	SR(MILLISECOND_TIME_BASE_DIV), \
+ 	SR(DISPCLK_FREQ_CHANGE_CNTL), \
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3552-drm-amd-display-Add-DFS-reference-clock-field.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3552-drm-amd-display-Add-DFS-reference-clock-field.patch
new file mode 100644
index 00000000..f9897098
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3552-drm-amd-display-Add-DFS-reference-clock-field.patch
@@ -0,0 +1,30 @@
+From f397a2e1a2e2d8e3857b5ba18de2c5a1a0bafc4a Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Tue, 25 Jun 2019 19:08:50 -0400
+Subject: [PATCH 3552/4256] drm/amd/display: Add DFS reference clock field
+
+Add to clk_mgr_internal struct, for future use.
+
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+index 9b6c885c0bba..7dd46eb96d67 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+@@ -216,6 +216,8 @@ struct clk_mgr_internal {
+ 	bool dfs_bypass_enabled;
+ 	/* True if the DFS-bypass feature is enabled and active. */
+ 	bool dfs_bypass_active;
++
++	uint32_t dfs_ref_freq_khz;
+ 	/*
+ 	 * Cache the display clock returned by VBIOS if DFS-bypass is enabled.
+ 	 * This is basically "Crystal Frequency In KHz" (XTALIN) frequency
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3553-drm-amd-powerpaly-fix-navi-series-custom-peak-level-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3553-drm-amd-powerpaly-fix-navi-series-custom-peak-level-.patch
new file mode 100644
index 00000000..f350e7ca
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3553-drm-amd-powerpaly-fix-navi-series-custom-peak-level-.patch
@@ -0,0 +1,37 @@
+From ccdce3d0f18ce47fe7659ea5e1060e12d776e1df Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Wed, 21 Aug 2019 10:58:19 +0800
+Subject: [PATCH 3553/4256] drm/amd/powerpaly: fix navi series custom peak
+ level value error
+
+fix other navi asic set peak performance level error.
+because the navi10_ppt.c will handle navi12 14 asic,
+it will use navi10 peak value to set other asic, it is not correct.
+
+after patch:
+only navi10 use custom peak value, other asic will used default value.
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 2d908afbf525..462c98f212ee 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1481,6 +1481,10 @@ static int navi10_set_peak_clock_by_device(struct smu_context *smu)
+ static int navi10_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
+ {
+ 	int ret = 0;
++	struct amdgpu_device *adev = smu->adev;
++
++	if (adev->asic_type != CHIP_NAVI10)
++		return -EINVAL;
+ 
+ 	switch (level) {
+ 	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3554-drm-amd-display-make-firmware-info-only-load-once-du.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3554-drm-amd-display-make-firmware-info-only-load-once-du.patch
new file mode 100644
index 00000000..519a4cc5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3554-drm-amd-display-make-firmware-info-only-load-once-du.patch
@@ -0,0 +1,455 @@
+From 538c3c6a1023bec8655011f2f81678915024ab8e Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Fri, 12 Jul 2019 15:06:06 -0400
+Subject: [PATCH 3554/4256] drm/amd/display: make firmware info only load once
+ during dc_bios create
+
+Currently every time DC wants to access firmware info we make a call
+into VBIOS. This makes no sense as there is nothing that can change
+runtime inside fw info and can cause issues when calling unstable
+bios during bringup.
+
+This change eliminate this behavior by only calling bios once for fw
+info and keeping it stored as part of dc_bios.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Chris Park <Chris.Park@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/bios/bios_parser.c |  3 +-
+ .../drm/amd/display/dc/bios/bios_parser2.c    |  3 +-
+ .../display/dc/clk_mgr/dce100/dce_clk_mgr.c   | 17 ++++------
+ .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c    |  6 ++--
+ .../gpu/drm/amd/display/dc/core/dc_resource.c |  7 ++--
+ .../gpu/drm/amd/display/dc/dc_bios_types.h    |  5 ++-
+ .../drm/amd/display/dc/dce/dce_clock_source.c | 32 +++++++------------
+ .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c   | 13 +-------
+ .../amd/display/dc/dce100/dce100_resource.c   |  4 +--
+ .../amd/display/dc/dce110/dce110_resource.c   |  4 +--
+ .../drm/amd/display/dc/dce80/dce80_resource.c | 12 ++-----
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  9 +++---
+ 12 files changed, 36 insertions(+), 79 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+index a4c97d32e751..207f6084525c 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+@@ -2794,8 +2794,6 @@ static const struct dc_vbios_funcs vbios_funcs = {
+ 
+ 	.get_device_tag = bios_parser_get_device_tag,
+ 
+-	.get_firmware_info = bios_parser_get_firmware_info,
+-
+ 	.get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
+ 
+ 	.get_ss_entry_number = bios_parser_get_ss_entry_number,
+@@ -2920,6 +2918,7 @@ static bool bios_parser_construct(
+ 	dal_bios_parser_init_cmd_tbl_helper(&bp->cmd_helper, dce_version);
+ 
+ 	bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
++	bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
+ 
+ 	return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index 99f40b8a231c..c9f65c4df530 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -1879,8 +1879,6 @@ static const struct dc_vbios_funcs vbios_funcs = {
+ 
+ 	.get_device_tag = bios_parser_get_device_tag,
+ 
+-	.get_firmware_info = bios_parser_get_firmware_info,
+-
+ 	.get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
+ 
+ 	.get_ss_entry_number = bios_parser_get_ss_entry_number,
+@@ -1996,6 +1994,7 @@ static bool bios_parser_construct(
+ 	dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
+ 
+ 	bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
++	bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
+ 
+ 	return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+index 6a0dd78ab65a..7634982a6bb0 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+@@ -270,18 +270,12 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)
+ {
+ 	struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;
+ 	struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
+-	struct integrated_info info = { { { 0 } } };
+-	struct dc_firmware_info fw_info = { { 0 } };
+ 	int i;
+ 
+ 	if (bp->integrated_info)
+-		info = *bp->integrated_info;
+-
+-	clk_mgr_dce->dentist_vco_freq_khz = info.dentist_vco_freq;
++		clk_mgr_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
+ 	if (clk_mgr_dce->dentist_vco_freq_khz == 0) {
+-		bp->funcs->get_firmware_info(bp, &fw_info);
+-		clk_mgr_dce->dentist_vco_freq_khz =
+-			fw_info.smu_gpu_pll_output_freq;
++		clk_mgr_dce->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
+ 		if (clk_mgr_dce->dentist_vco_freq_khz == 0)
+ 			clk_mgr_dce->dentist_vco_freq_khz = 3600000;
+ 	}
+@@ -314,9 +308,10 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)
+ 
+ 		/*Do not allow bad VBIOS/SBIOS to override with invalid values,
+ 		 * check for > 100MHz*/
+-		if (info.disp_clk_voltage[i].max_supported_clk >= 100000)
+-			clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =
+-				info.disp_clk_voltage[i].max_supported_clk;
++		if (bp->integrated_info)
++			if (bp->integrated_info->disp_clk_voltage[i].max_supported_clk >= 100000)
++				clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =
++					bp->integrated_info->disp_clk_voltage[i].max_supported_clk;
+ 	}
+ 
+ 	if (!debug->disable_dfs_bypass && bp->integrated_info)
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+index a12a9606788f..d00ee9fa04e4 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+@@ -254,7 +254,6 @@ void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_
+ {
+ 	struct dc_debug_options *debug = &ctx->dc->debug;
+ 	struct dc_bios *bp = ctx->dc_bios;
+-	struct dc_firmware_info fw_info = { { 0 } };
+ 
+ 	clk_mgr->base.ctx = ctx;
+ 	clk_mgr->pp_smu = pp_smu;
+@@ -270,9 +269,8 @@ void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_
+ 
+ 	if (bp->integrated_info)
+ 		clk_mgr->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
+-	if (clk_mgr->dentist_vco_freq_khz == 0) {
+-		bp->funcs->get_firmware_info(bp, &fw_info);
+-		clk_mgr->dentist_vco_freq_khz = fw_info.smu_gpu_pll_output_freq;
++	if (bp->fw_info_valid && clk_mgr->dentist_vco_freq_khz == 0) {
++		clk_mgr->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
+ 		if (clk_mgr->dentist_vco_freq_khz == 0)
+ 			clk_mgr->dentist_vco_freq_khz = 3600000;
+ 	}
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 601020c9b03e..fa94dfc04dce 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -170,12 +170,9 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
+ 		break;
+ 	}
+ 	if (res_pool != NULL) {
+-		struct dc_firmware_info fw_info = { { 0 } };
+-
+-		if (dc->ctx->dc_bios->funcs->get_firmware_info(dc->ctx->dc_bios,
+-				&fw_info) == BP_RESULT_OK) {
++		if (dc->ctx->dc_bios->fw_info_valid) {
+ 			res_pool->ref_clocks.xtalin_clock_inKhz =
+-				fw_info.pll_info.crystal_frequency;
++				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
+ 			/* initialize with firmware data first, no all
+ 			 * ASIC have DCCG SW component. FPGA or
+ 			 * simulation need initialization of
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+index 78c3b300ec45..b1dd0d60d98e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+@@ -61,9 +61,6 @@ struct dc_vbios_funcs {
+ 		struct graphics_object_id connector_object_id,
+ 		uint32_t device_tag_index,
+ 		struct connector_device_tag_info *info);
+-	enum bp_result (*get_firmware_info)(
+-		struct dc_bios *bios,
+-		struct dc_firmware_info *info);
+ 	enum bp_result (*get_spread_spectrum_info)(
+ 		struct dc_bios *bios,
+ 		enum as_signal_type signal,
+@@ -152,6 +149,8 @@ struct dc_bios {
+ 	struct dc_context *ctx;
+ 	const struct bios_registers *regs;
+ 	struct integrated_info *integrated_info;
++	struct dc_firmware_info fw_info;
++	bool fw_info_valid;
+ };
+ 
+ #endif /* DC_BIOS_TYPES_H */
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+index 09c4dd806525..990481b35682 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+@@ -1233,37 +1233,35 @@ static bool calc_pll_max_vco_construct(
+ 			struct calc_pll_clock_source_init_data *init_data)
+ {
+ 	uint32_t i;
+-	struct dc_firmware_info fw_info = { { 0 } };
++	struct dc_firmware_info *fw_info = &init_data->bp->fw_info;
+ 	if (calc_pll_cs == NULL ||
+ 			init_data == NULL ||
+ 			init_data->bp == NULL)
+ 		return false;
+ 
+-	if (init_data->bp->funcs->get_firmware_info(
+-				init_data->bp,
+-				&fw_info) != BP_RESULT_OK)
++	if (init_data->bp->fw_info_valid)
+ 		return false;
+ 
+ 	calc_pll_cs->ctx = init_data->ctx;
+-	calc_pll_cs->ref_freq_khz = fw_info.pll_info.crystal_frequency;
++	calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency;
+ 	calc_pll_cs->min_vco_khz =
+-			fw_info.pll_info.min_output_pxl_clk_pll_frequency;
++			fw_info->pll_info.min_output_pxl_clk_pll_frequency;
+ 	calc_pll_cs->max_vco_khz =
+-			fw_info.pll_info.max_output_pxl_clk_pll_frequency;
++			fw_info->pll_info.max_output_pxl_clk_pll_frequency;
+ 
+ 	if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0)
+ 		calc_pll_cs->max_pll_input_freq_khz =
+ 			init_data->max_override_input_pxl_clk_pll_freq_khz;
+ 	else
+ 		calc_pll_cs->max_pll_input_freq_khz =
+-			fw_info.pll_info.max_input_pxl_clk_pll_frequency;
++			fw_info->pll_info.max_input_pxl_clk_pll_frequency;
+ 
+ 	if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0)
+ 		calc_pll_cs->min_pll_input_freq_khz =
+ 			init_data->min_override_input_pxl_clk_pll_freq_khz;
+ 	else
+ 		calc_pll_cs->min_pll_input_freq_khz =
+-			fw_info.pll_info.min_input_pxl_clk_pll_frequency;
++			fw_info->pll_info.min_input_pxl_clk_pll_frequency;
+ 
+ 	calc_pll_cs->min_pix_clock_pll_post_divider =
+ 			init_data->min_pix_clk_pll_post_divider;
+@@ -1315,7 +1313,6 @@ bool dce110_clk_src_construct(
+ 	const struct dce110_clk_src_shift *cs_shift,
+ 	const struct dce110_clk_src_mask *cs_mask)
+ {
+-	struct dc_firmware_info fw_info = { { 0 } };
+ 	struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi;
+ 	struct calc_pll_clock_source_init_data calc_pll_cs_init_data;
+ 
+@@ -1328,14 +1325,12 @@ bool dce110_clk_src_construct(
+ 	clk_src->cs_shift = cs_shift;
+ 	clk_src->cs_mask = cs_mask;
+ 
+-	if (clk_src->bios->funcs->get_firmware_info(
+-			clk_src->bios, &fw_info) != BP_RESULT_OK) {
++	if (!clk_src->bios->fw_info_valid) {
+ 		ASSERT_CRITICAL(false);
+ 		goto unexpected_failure;
+ 	}
+ 
+-	clk_src->ext_clk_khz =
+-			fw_info.external_clock_source_frequency_for_dp;
++	clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
+ 
+ 	/* structure normally used with PLL ranges from ATOMBIOS; DS on by default */
+ 	calc_pll_cs_init_data.bp = bios;
+@@ -1375,7 +1370,7 @@ bool dce110_clk_src_construct(
+ 			FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
+ 	calc_pll_cs_init_data_hdmi.ctx = ctx;
+ 
+-	clk_src->ref_freq_khz = fw_info.pll_info.crystal_frequency;
++	clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency;
+ 
+ 	if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL)
+ 		return true;
+@@ -1418,8 +1413,6 @@ bool dce112_clk_src_construct(
+ 	const struct dce110_clk_src_shift *cs_shift,
+ 	const struct dce110_clk_src_mask *cs_mask)
+ {
+-	struct dc_firmware_info fw_info = { { 0 } };
+-
+ 	clk_src->base.ctx = ctx;
+ 	clk_src->bios = bios;
+ 	clk_src->base.id = id;
+@@ -1429,13 +1422,12 @@ bool dce112_clk_src_construct(
+ 	clk_src->cs_shift = cs_shift;
+ 	clk_src->cs_mask = cs_mask;
+ 
+-	if (clk_src->bios->funcs->get_firmware_info(
+-			clk_src->bios, &fw_info) != BP_RESULT_OK) {
++	if (!clk_src->bios->fw_info_valid) {
+ 		ASSERT_CRITICAL(false);
+ 		return false;
+ 	}
+ 
+-	clk_src->ext_clk_khz = fw_info.external_clock_source_frequency_for_dp;
++	clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
+ 
+ 	return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+index b2786a704708..caace5229826 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+@@ -96,17 +96,6 @@ static uint32_t get_hw_buffer_available_size(
+ 			dce_i2c_hw->buffer_used_bytes;
+ }
+ 
+-uint32_t get_reference_clock(
+-		struct dc_bios *bios)
+-{
+-	struct dc_firmware_info info = { { 0 } };
+-
+-	if (bios->funcs->get_firmware_info(bios, &info) != BP_RESULT_OK)
+-		return 0;
+-
+-	return info.pll_info.crystal_frequency;
+-}
+-
+ static uint32_t get_speed(
+ 	const struct dce_i2c_hw *dce_i2c_hw)
+ {
+@@ -629,7 +618,7 @@ void dce_i2c_hw_construct(
+ {
+ 	dce_i2c_hw->ctx = ctx;
+ 	dce_i2c_hw->engine_id = engine_id;
+-	dce_i2c_hw->reference_frequency = get_reference_clock(ctx->dc_bios) >> 1;
++	dce_i2c_hw->reference_frequency = (ctx->dc_bios->fw_info.pll_info.crystal_frequency) >> 1;
+ 	dce_i2c_hw->regs = regs;
+ 	dce_i2c_hw->shifts = shifts;
+ 	dce_i2c_hw->masks = masks;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+index bb199534ea3b..9de2a0bda38a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+@@ -907,7 +907,6 @@ static bool construct(
+ {
+ 	unsigned int i;
+ 	struct dc_context *ctx = dc->ctx;
+-	struct dc_firmware_info info;
+ 	struct dc_bios *bp;
+ 
+ 	ctx->dc_bios->regs = &bios_regs;
+@@ -918,8 +917,7 @@ static bool construct(
+ 
+ 	bp = ctx->dc_bios;
+ 
+-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
+-		info.external_clock_source_frequency_for_dp != 0) {
++	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
+ 		pool->base.dp_clock_source =
+ 				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index ae89721c3a99..dc1764f2f8c2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -1272,7 +1272,6 @@ static bool construct(
+ {
+ 	unsigned int i;
+ 	struct dc_context *ctx = dc->ctx;
+-	struct dc_firmware_info info;
+ 	struct dc_bios *bp;
+ 
+ 	ctx->dc_bios->regs = &bios_regs;
+@@ -1298,8 +1297,7 @@ static bool construct(
+ 
+ 	bp = ctx->dc_bios;
+ 
+-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
+-		info.external_clock_source_frequency_for_dp != 0) {
++	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
+ 		pool->base.dp_clock_source =
+ 				dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+index 2f224e1ae5f2..8e4effb1f439 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -877,7 +877,6 @@ static bool dce80_construct(
+ {
+ 	unsigned int i;
+ 	struct dc_context *ctx = dc->ctx;
+-	struct dc_firmware_info info;
+ 	struct dc_bios *bp;
+ 
+ 	ctx->dc_bios->regs = &bios_regs;
+@@ -903,8 +902,7 @@ static bool dce80_construct(
+ 
+ 	bp = ctx->dc_bios;
+ 
+-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
+-		info.external_clock_source_frequency_for_dp != 0) {
++	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
+ 		pool->base.dp_clock_source =
+ 				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+ 
+@@ -1076,7 +1074,6 @@ static bool dce81_construct(
+ {
+ 	unsigned int i;
+ 	struct dc_context *ctx = dc->ctx;
+-	struct dc_firmware_info info;
+ 	struct dc_bios *bp;
+ 
+ 	ctx->dc_bios->regs = &bios_regs;
+@@ -1102,8 +1099,7 @@ static bool dce81_construct(
+ 
+ 	bp = ctx->dc_bios;
+ 
+-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
+-		info.external_clock_source_frequency_for_dp != 0) {
++	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
+ 		pool->base.dp_clock_source =
+ 				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+ 
+@@ -1275,7 +1271,6 @@ static bool dce83_construct(
+ {
+ 	unsigned int i;
+ 	struct dc_context *ctx = dc->ctx;
+-	struct dc_firmware_info info;
+ 	struct dc_bios *bp;
+ 
+ 	ctx->dc_bios->regs = &bios_regs;
+@@ -1301,8 +1296,7 @@ static bool dce83_construct(
+ 
+ 	bp = ctx->dc_bios;
+ 
+-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
+-		info.external_clock_source_frequency_for_dp != 0) {
++	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
+ 		pool->base.dp_clock_source =
+ 				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index abbae9fb8eff..91357271e360 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -567,7 +567,6 @@ static void dcn20_init_hw(struct dc *dc)
+ 	struct dc_bios *dcb = dc->ctx->dc_bios;
+ 	struct resource_pool *res_pool = dc->res_pool;
+ 	struct dc_state  *context = dc->current_state;
+-	struct dc_firmware_info fw_info = { { 0 } };
+ 
+ 	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
+ 		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
+@@ -591,15 +590,15 @@ static void dcn20_init_hw(struct dc *dc)
+ 	} else {
+ 		if (!dcb->funcs->is_accelerated_mode(dcb)) {
+ 			bios_golden_init(dc);
+-			if (dc->ctx->dc_bios->funcs->get_firmware_info(
+-					dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
+-				res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency;
++			if (dc->ctx->dc_bios->fw_info_valid) {
++				res_pool->ref_clocks.xtalin_clock_inKhz =
++						dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
+ 
+ 				if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 					if (res_pool->dccg && res_pool->hubbub) {
+ 
+ 						(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+-								fw_info.pll_info.crystal_frequency,
++								dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
+ 								&res_pool->ref_clocks.dccg_ref_clock_inKhz);
+ 
+ 						(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3555-drm-amd-display-Make-init_hw-and-init_pipes-generic-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3555-drm-amd-display-Make-init_hw-and-init_pipes-generic-.patch
new file mode 100644
index 00000000..ef02eddb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3555-drm-amd-display-Make-init_hw-and-init_pipes-generic-.patch
@@ -0,0 +1,1086 @@
+From b794722e64e6d98fce6b19921a2da22d2326233e Mon Sep 17 00:00:00 2001
+From: Martin Leung <martin.leung@amd.com>
+Date: Tue, 9 Jul 2019 15:15:17 -0400
+Subject: [PATCH 3555/4256] drm/amd/display: Make init_hw and init_pipes
+ generic for seamless boot
+
+[Why]
+For seamless boot the init_hw sequence must be split into
+actual hardware vs pipes, in order to defer pipe initialization to set mode
+and skip of pipe-destructive sequences
+
+[How]
+made dcn10_init_hw and dcn10_init_pipes generic for future dcns to inherit
+deleted dcn20 specific versions. This is part 1 of a 2 partimplementation
+of seamless boot
+
+Change-Id: I66fe630d9742a3fcfa1ce02c49da6411f0e95ca1
+Signed-off-by: Martin Leung <martin.leung@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../display/dc/dce110/dce110_hw_sequencer.c   |  12 +-
+ .../display/dc/dce110/dce110_hw_sequencer.h   |   6 +-
+ .../drm/amd/display/dc/dcn10/dcn10_hubbub.c   |   4 +-
+ .../drm/amd/display/dc/dcn10/dcn10_hubbub.h   |   2 +-
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 182 ++++++---
+ .../drm/amd/display/dc/dcn20/dcn20_hubbub.c   |   2 +-
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 383 +++++++-----------
+ .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h  |   4 +
+ .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  32 ++
+ 9 files changed, 314 insertions(+), 313 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 919647166bce..5a046e5bc756 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -728,7 +728,7 @@ static enum bp_result link_transmitter_control(
+  * @brief
+  * eDP only.
+  */
+-void hwss_edp_wait_for_hpd_ready(
++void dce110_edp_wait_for_hpd_ready(
+ 		struct dc_link *link,
+ 		bool power_up)
+ {
+@@ -796,7 +796,7 @@ void hwss_edp_wait_for_hpd_ready(
+ 	}
+ }
+ 
+-void hwss_edp_power_control(
++void dce110_edp_power_control(
+ 		struct dc_link *link,
+ 		bool power_up)
+ {
+@@ -878,7 +878,7 @@ void hwss_edp_power_control(
+  * @brief
+  * eDP only. Control the backlight of the eDP panel
+  */
+-void hwss_edp_backlight_control(
++void dce110_edp_backlight_control(
+ 		struct dc_link *link,
+ 		bool enable)
+ {
+@@ -2755,9 +2755,9 @@ static const struct hw_sequencer_funcs dce110_funcs = {
+ 	.setup_stereo = NULL,
+ 	.set_avmute = dce110_set_avmute,
+ 	.wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
+-	.edp_backlight_control = hwss_edp_backlight_control,
+-	.edp_power_control = hwss_edp_power_control,
+-	.edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
++	.edp_backlight_control = dce110_edp_backlight_control,
++	.edp_power_control = dce110_edp_power_control,
++	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+ 	.set_cursor_position = dce110_set_cursor_position,
+ 	.set_cursor_attribute = dce110_set_cursor_attribute
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+index cd3e36d52a52..668feb0d169d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+@@ -73,15 +73,15 @@ void dce110_optimize_bandwidth(
+ 
+ void dp_receiver_power_ctrl(struct dc_link *link, bool on);
+ 
+-void hwss_edp_power_control(
++void dce110_edp_power_control(
+ 		struct dc_link *link,
+ 		bool power_up);
+ 
+-void hwss_edp_backlight_control(
++void dce110_edp_backlight_control(
+ 	struct dc_link *link,
+ 	bool enable);
+ 
+-void hwss_edp_wait_for_hpd_ready(
++void dce110_edp_wait_for_hpd_ready(
+ 		struct dc_link *link,
+ 		bool power_up);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+index 0ab391446d3d..90c30a21bd09 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+@@ -102,7 +102,7 @@ void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow)
+ 			DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, !allow);
+ }
+ 
+-bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
++bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
+ {
+ 	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
+ 	uint32_t enable = 0;
+@@ -943,6 +943,8 @@ static const struct hubbub_funcs hubbub1_funcs = {
+ 	.get_dcc_compression_cap = hubbub1_get_dcc_compression_cap,
+ 	.wm_read_state = hubbub1_wm_read_state,
+ 	.program_watermarks = hubbub1_program_watermarks,
++	.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
++	.allow_self_refresh_control = hubbub1_allow_self_refresh_control,
+ };
+ 
+ void hubbub1_construct(struct hubbub *hubbub,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+index 7c2559c9ae23..70e5d84fc69a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+@@ -247,7 +247,7 @@ void hubbub1_program_watermarks(
+ 
+ void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow);
+ 
+-bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubub);
++bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubub);
+ 
+ void hubbub1_toggle_watermark_change_req(
+ 		struct hubbub *hubbub);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 5390f8d84b2a..1835157b9fad 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -437,7 +437,7 @@ bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	return false;
+ }
+ 
+-static void enable_power_gating_plane(
++static void dcn10_enable_power_gating_plane(
+ 	struct dce_hwseq *hws,
+ 	bool enable)
+ {
+@@ -459,7 +459,7 @@ static void enable_power_gating_plane(
+ 	REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
+ }
+ 
+-static void disable_vga(
++static void dcn10_disable_vga(
+ 	struct dce_hwseq *hws)
+ {
+ 	unsigned int in_vga1_mode = 0;
+@@ -492,7 +492,7 @@ static void disable_vga(
+ 	REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
+ }
+ 
+-static void dpp_pg_control(
++static void dcn10_dpp_pg_control(
+ 		struct dce_hwseq *hws,
+ 		unsigned int dpp_inst,
+ 		bool power_on)
+@@ -544,7 +544,7 @@ static void dpp_pg_control(
+ 	}
+ }
+ 
+-static void hubp_pg_control(
++static void dcn10_hubp_pg_control(
+ 		struct dce_hwseq *hws,
+ 		unsigned int hubp_inst,
+ 		bool power_on)
+@@ -604,8 +604,8 @@ static void power_on_plane(
+ 	if (REG(DC_IP_REQUEST_CNTL)) {
+ 		REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 				IP_REQUEST_EN, 1);
+-		dpp_pg_control(hws, plane_id, true);
+-		hubp_pg_control(hws, plane_id, true);
++		hws->ctx->dc->hwss.dpp_pg_control(hws, plane_id, true);
++		hws->ctx->dc->hwss.hubp_pg_control(hws, plane_id, true);
+ 		REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 				IP_REQUEST_EN, 0);
+ 		DC_LOG_DEBUG(
+@@ -626,7 +626,7 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc)
+ 	REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 			IP_REQUEST_EN, 1);
+ 
+-	hubp_pg_control(hws, 0, false);
++	dc->hwss.hubp_pg_control(hws, 0, false);
+ 	REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 			IP_REQUEST_EN, 0);
+ 
+@@ -655,7 +655,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc)
+ 	REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 			IP_REQUEST_EN, 1);
+ 
+-	hubp_pg_control(hws, 0, true);
++	dc->hwss.hubp_pg_control(hws, 0, true);
+ 	REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 			IP_REQUEST_EN, 0);
+ 
+@@ -663,10 +663,23 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc)
+ 	hws->wa_state.DEGVIDCN10_253_applied = true;
+ }
+ 
+-static void bios_golden_init(struct dc *dc)
++static void dcn10_bios_golden_init(struct dc *dc)
+ {
+ 	struct dc_bios *bp = dc->ctx->dc_bios;
+ 	int i;
++	bool allow_self_fresh_force_enable = true;
++
++	if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)
++		allow_self_fresh_force_enable =
++				dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);
++
++
++	/* WA for making DF sleep when idle after resume from S0i3.
++	 * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
++	 * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
++	 * before calling command table and it changed to 1 after,
++	 * it should be set back to 0.
++	 */
+ 
+ 	/* initialize dcn global */
+ 	bp->funcs->enable_disp_power_gating(bp,
+@@ -677,6 +690,12 @@ static void bios_golden_init(struct dc *dc)
+ 		bp->funcs->enable_disp_power_gating(bp,
+ 				CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
+ 	}
++
++	if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
++		if (allow_self_fresh_force_enable == false &&
++				dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub))
++			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, true);
++
+ }
+ 
+ static void false_optc_underflow_wa(
+@@ -971,7 +990,7 @@ void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 		dcn10_verify_allow_pstate_change_high(dc);
+ }
+ 
+-static void plane_atomic_power_down(struct dc *dc,
++static void dcn10_plane_atomic_power_down(struct dc *dc,
+ 		struct dpp *dpp,
+ 		struct hubp *hubp)
+ {
+@@ -981,8 +1000,8 @@ static void plane_atomic_power_down(struct dc *dc,
+ 	if (REG(DC_IP_REQUEST_CNTL)) {
+ 		REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 				IP_REQUEST_EN, 1);
+-		dpp_pg_control(hws, dpp->inst, false);
+-		hubp_pg_control(hws, hubp->inst, false);
++		dc->hwss.dpp_pg_control(hws, dpp->inst, false);
++		dc->hwss.hubp_pg_control(hws, hubp->inst, false);
+ 		dpp->funcs->dpp_reset(dpp);
+ 		REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 				IP_REQUEST_EN, 0);
+@@ -994,7 +1013,7 @@ static void plane_atomic_power_down(struct dc *dc,
+ /* disable HW used by plane.
+  * note:  cannot disable until disconnect is complete
+  */
+-static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
++static void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
+@@ -1014,7 +1033,7 @@ static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	hubp->power_gated = true;
+ 	dc->optimized_required = false; /* We're powering off, no need to optimize */
+ 
+-	plane_atomic_power_down(dc,
++	dc->hwss.plane_atomic_power_down(dc,
+ 			pipe_ctx->plane_res.dpp,
+ 			pipe_ctx->plane_res.hubp);
+ 
+@@ -1033,7 +1052,7 @@ static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
+ 		return;
+ 
+-	plane_atomic_disable(dc, pipe_ctx);
++	dc->hwss.plane_atomic_disable(dc, pipe_ctx);
+ 
+ 	apply_DEGVIDCN10_253_wa(dc);
+ 
+@@ -1068,9 +1087,14 @@ static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
+ 		 * command table.
+ 		 */
+ 		if (tg->funcs->is_tg_enabled(tg)) {
+-			tg->funcs->lock(tg);
+-			tg->funcs->set_blank(tg, true);
+-			hwss_wait_for_blank_complete(tg);
++			if (dc->hwss.init_blank != NULL) {
++				dc->hwss.init_blank(dc, tg);
++				tg->funcs->lock(tg);
++			} else {
++				tg->funcs->lock(tg);
++				tg->funcs->set_blank(tg, true);
++				hwss_wait_for_blank_complete(tg);
++			}
+ 		}
+ 	}
+ 
+@@ -1121,12 +1145,12 @@ static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
+ 		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
+ 		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
+ 
+-		hwss1_plane_atomic_disconnect(dc, pipe_ctx);
++		dc->hwss.plane_atomic_disconnect(dc, pipe_ctx);
+ 
+ 		if (tg->funcs->is_tg_enabled(tg))
+ 			tg->funcs->unlock(tg);
+ 
+-		dcn10_disable_plane(dc, pipe_ctx);
++		dc->hwss.disable_plane(dc, pipe_ctx);
+ 
+ 		pipe_ctx->stream_res.tg = NULL;
+ 		pipe_ctx->plane_res.hubp = NULL;
+@@ -1142,8 +1166,17 @@ static void dcn10_init_hw(struct dc *dc)
+ 	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 	struct dce_hwseq *hws = dc->hwseq;
+ 	struct dc_bios *dcb = dc->ctx->dc_bios;
++	struct resource_pool *res_pool = dc->res_pool;
++
++	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
++		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
++
++	// Initialize the dccg
++	if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)
++		dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);
+ 
+ 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
++
+ 		REG_WRITE(REFCLK_CNTL, 0);
+ 		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
+ 		REG_WRITE(DIO_MEM_PWR_CTRL, 0);
+@@ -1157,30 +1190,39 @@ static void dcn10_init_hw(struct dc *dc)
+ 			REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
+ 		}
+ 
+-		enable_power_gating_plane(dc->hwseq, true);
++		//Enable ability to power gate / don't force power on permanently
++		dc->hwss.enable_power_gating_plane(hws, true);
+ 
+-		/* end of FPGA. Below if real ASIC */
+ 		return;
+ 	}
+ 
+ 	if (!dcb->funcs->is_accelerated_mode(dcb)) {
+-		bool allow_self_fresh_force_enable =
+-			hububu1_is_allow_self_refresh_enabled(
+-						dc->res_pool->hubbub);
+-
+-		bios_golden_init(dc);
+-
+-		/* WA for making DF sleep when idle after resume from S0i3.
+-		 * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
+-		 * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
+-		 * before calling command table and it changed to 1 after,
+-		 * it should be set back to 0.
+-		 */
+-		if (allow_self_fresh_force_enable == false &&
+-				hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub))
+-			hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, true);
+-
+-		disable_vga(dc->hwseq);
++		dc->hwss.bios_golden_init(dc);
++		if (dc->ctx->dc_bios->fw_info_valid) {
++			res_pool->ref_clocks.xtalin_clock_inKhz =
++					dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
++
++			if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
++				if (res_pool->dccg && res_pool->hubbub) {
++
++					(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
++							dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
++							&res_pool->ref_clocks.dccg_ref_clock_inKhz);
++
++					(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
++							res_pool->ref_clocks.dccg_ref_clock_inKhz,
++							&res_pool->ref_clocks.dchub_ref_clock_inKhz);
++				} else {
++					// Not all ASICs have DCCG sw component
++					res_pool->ref_clocks.dccg_ref_clock_inKhz =
++							res_pool->ref_clocks.xtalin_clock_inKhz;
++					res_pool->ref_clocks.dchub_ref_clock_inKhz =
++							res_pool->ref_clocks.xtalin_clock_inKhz;
++				}
++			}
++		} else
++			ASSERT_CRITICAL(false);
++		dc->hwss.disable_vga(dc->hwseq);
+ 	}
+ 
+ 	for (i = 0; i < dc->link_count; i++) {
+@@ -1198,6 +1240,13 @@ static void dcn10_init_hw(struct dc *dc)
+ 			link->link_status.link_active = true;
+ 	}
+ 
++	/* Power gate DSCs */
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
++		if (dc->hwss.dsc_pg_control != NULL)
++			dc->hwss.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
++#endif
++
+ 	/* If taking control over from VBIOS, we may want to optimize our first
+ 	 * mode set, so we need to skip powering down pipes until we know which
+ 	 * pipes we want to use.
+@@ -1206,10 +1255,21 @@ static void dcn10_init_hw(struct dc *dc)
+ 	 */
+ 	if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
+ 		dc->hwss.init_pipes(dc, dc->current_state);
++		for (i = 0; i < res_pool->pipe_count; i++) {
++			struct hubp *hubp = res_pool->hubps[i];
++			struct dpp *dpp = res_pool->dpps[i];
++
++			hubp->funcs->hubp_init(hubp);
++			res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
++			dc->hwss.plane_atomic_power_down(dc, dpp, hubp);
++		}
++
++		apply_DEGVIDCN10_253_wa(dc);
+ 	}
+ 
+-	for (i = 0; i < dc->res_pool->audio_count; i++) {
+-		struct audio *audio = dc->res_pool->audios[i];
++
++	for (i = 0; i < res_pool->audio_count; i++) {
++		struct audio *audio = res_pool->audios[i];
+ 
+ 		audio->funcs->hw_init(audio);
+ 	}
+@@ -1237,7 +1297,7 @@ static void dcn10_init_hw(struct dc *dc)
+ 		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
+ 	}
+ 
+-	enable_power_gating_plane(dc->hwseq, true);
++	dc->hwss.enable_power_gating_plane(dc->hwseq, true);
+ }
+ 
+ static void dcn10_reset_hw_ctx_wrap(
+@@ -1825,7 +1885,7 @@ static void dcn10_enable_plane(
+ 	}
+ }
+ 
+-static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
++static void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)
+ {
+ 	int i = 0;
+ 	struct dpp_grph_csc_adjustment adjust;
+@@ -2303,7 +2363,7 @@ void update_dchubp_dpp(
+ 
+ 	if (plane_state->update_flags.bits.full_update) {
+ 		/*gamut remap*/
+-		program_gamut_remap(pipe_ctx);
++		dc->hwss.program_gamut_remap(pipe_ctx);
+ 
+ 		dc->hwss.program_output_csc(dc,
+ 				pipe_ctx,
+@@ -2540,7 +2600,7 @@ static void dcn10_apply_ctx_for_surface(
+ 			if (old_pipe_ctx->stream_res.tg == tg &&
+ 			    old_pipe_ctx->plane_res.hubp &&
+ 			    old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID)
+-				dcn10_disable_plane(dc, old_pipe_ctx);
++				dc->hwss.disable_plane(dc, old_pipe_ctx);
+ 		}
+ 
+ 		if ((!pipe_ctx->plane_state ||
+@@ -2588,7 +2648,7 @@ static void dcn10_apply_ctx_for_surface(
+ 
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++)
+ 		if (removed_pipe[i])
+-			dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
++			dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
+ 
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++)
+ 		if (removed_pipe[i]) {
+@@ -2680,7 +2740,7 @@ static void dcn10_optimize_bandwidth(
+ 		dcn10_verify_allow_pstate_change_high(dc);
+ }
+ 
+-static void set_drr(struct pipe_ctx **pipe_ctx,
++static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
+ 		int num_pipes, int vmin, int vmax)
+ {
+ 	int i = 0;
+@@ -2705,7 +2765,7 @@ static void set_drr(struct pipe_ctx **pipe_ctx,
+ 	}
+ }
+ 
+-static void get_position(struct pipe_ctx **pipe_ctx,
++static void dcn10_get_position(struct pipe_ctx **pipe_ctx,
+ 		int num_pipes,
+ 		struct crtc_position *position)
+ {
+@@ -2717,7 +2777,7 @@ static void get_position(struct pipe_ctx **pipe_ctx,
+ 		pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
+ }
+ 
+-static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
++static void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
+ 		int num_pipes, const struct dc_static_screen_events *events)
+ {
+ 	unsigned int i;
+@@ -3204,7 +3264,7 @@ static void dcn10_get_clock(struct dc *dc,
+ }
+ 
+ static const struct hw_sequencer_funcs dcn10_funcs = {
+-	.program_gamut_remap = program_gamut_remap,
++	.program_gamut_remap = dcn10_program_gamut_remap,
+ 	.init_hw = dcn10_init_hw,
+ 	.init_pipes = dcn10_init_pipes,
+ 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+@@ -3237,18 +3297,18 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
+ 	.optimize_bandwidth = dcn10_optimize_bandwidth,
+ 	.reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
+ 	.enable_stream_timing = dcn10_enable_stream_timing,
+-	.set_drr = set_drr,
+-	.get_position = get_position,
+-	.set_static_screen_control = set_static_screen_control,
++	.set_drr = dcn10_set_drr,
++	.get_position = dcn10_get_position,
++	.set_static_screen_control = dcn10_set_static_screen_control,
+ 	.setup_stereo = dcn10_setup_stereo,
+ 	.set_avmute = dce110_set_avmute,
+ 	.log_hw_state = dcn10_log_hw_state,
+ 	.get_hw_state = dcn10_get_hw_state,
+ 	.clear_status_bits = dcn10_clear_status_bits,
+ 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+-	.edp_backlight_control = hwss_edp_backlight_control,
+-	.edp_power_control = hwss_edp_power_control,
+-	.edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
++	.edp_backlight_control = dce110_edp_backlight_control,
++	.edp_power_control = dce110_edp_power_control,
++	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+ 	.set_cursor_position = dcn10_set_cursor_position,
+ 	.set_cursor_attribute = dcn10_set_cursor_attribute,
+ 	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
+@@ -3258,6 +3318,16 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
+ 	.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
+ 	.set_clock = dcn10_set_clock,
+ 	.get_clock = dcn10_get_clock,
++	.did_underflow_occur = dcn10_did_underflow_occur,
++	.init_blank = NULL,
++	.disable_vga = dcn10_disable_vga,
++	.bios_golden_init = dcn10_bios_golden_init,
++	.plane_atomic_disable = dcn10_plane_atomic_disable,
++	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
++	.enable_power_gating_plane = dcn10_enable_power_gating_plane,
++	.dpp_pg_control = dcn10_dpp_pg_control,
++	.hubp_pg_control = dcn10_hubp_pg_control,
++	.dsc_pg_control = NULL,
+ };
+ 
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+index 2b7859dfc089..f13e039f8ef4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+@@ -595,7 +595,7 @@ static const struct hubbub_funcs hubbub2_funcs = {
+ 	.get_dcc_compression_cap = hubbub2_get_dcc_compression_cap,
+ 	.wm_read_state = hubbub2_wm_read_state,
+ 	.get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
+-	.program_watermarks = hubbub2_program_watermarks,
++	.program_watermarks = hubbub2_program_watermarks
+ };
+ 
+ void hubbub2_construct(struct dcn20_hubbub *hubbub,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 91357271e360..57d9645659d8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -64,23 +64,7 @@
+ #define FN(reg_name, field_name) \
+ 	hws->shifts->field_name, hws->masks->field_name
+ 
+-static void bios_golden_init(struct dc *dc)
+-{
+-	struct dc_bios *bp = dc->ctx->dc_bios;
+-	int i;
+-
+-	/* initialize dcn global */
+-	bp->funcs->enable_disp_power_gating(bp,
+-			CONTROLLER_ID_D0, ASIC_PIPE_INIT);
+-
+-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+-		/* initialize dcn per pipe */
+-		bp->funcs->enable_disp_power_gating(bp,
+-				CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
+-	}
+-}
+-
+-static void enable_power_gating_plane(
++static void dcn20_enable_power_gating_plane(
+ 	struct dce_hwseq *hws,
+ 	bool enable)
+ {
+@@ -183,7 +167,7 @@ void dcn20_display_init(struct dc *dc)
+ 	REG_WRITE(AZALIA_CONTROLLER_CLOCK_GATING, 0x1);
+ }
+ 
+-static void disable_vga(
++void dcn20_disable_vga(
+ 	struct dce_hwseq *hws)
+ {
+ 	REG_WRITE(D1VGA_CONTROL, 0);
+@@ -486,29 +470,6 @@ static void dcn20_hubp_pg_control(
+ }
+ 
+ 
+-
+-static void dcn20_plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx)
+-{
+-	struct dce_hwseq *hws = dc->hwseq;
+-	struct dpp *dpp = pipe_ctx->plane_res.dpp;
+-
+-	DC_LOGGER_INIT(dc->ctx->logger);
+-
+-	if (REG(DC_IP_REQUEST_CNTL)) {
+-		REG_SET(DC_IP_REQUEST_CNTL, 0,
+-				IP_REQUEST_EN, 1);
+-		dcn20_dpp_pg_control(hws, dpp->inst, false);
+-		dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false);
+-		dpp->funcs->dpp_reset(dpp);
+-		REG_SET(DC_IP_REQUEST_CNTL, 0,
+-				IP_REQUEST_EN, 0);
+-		DC_LOG_DEBUG(
+-				"Power gated front end %d\n", pipe_ctx->pipe_idx);
+-	}
+-}
+-
+-
+-
+ /* disable HW used by plane.
+  * note:  cannot disable until disconnect is complete
+  */
+@@ -534,7 +495,9 @@ static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	hubp->power_gated = true;
+ 	dc->optimized_required = false; /* We're powering off, no need to optimize */
+ 
+-	dcn20_plane_atomic_power_down(dc, pipe_ctx);
++	dc->hwss.plane_atomic_power_down(dc,
++			pipe_ctx->plane_res.dpp,
++			pipe_ctx->plane_res.hubp);
+ 
+ 	pipe_ctx->stream = NULL;
+ 	memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
+@@ -558,204 +521,6 @@ void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 					pipe_ctx->pipe_idx);
+ }
+ 
+-static void dcn20_init_hw(struct dc *dc)
+-{
+-	int i, j;
+-	struct abm *abm = dc->res_pool->abm;
+-	struct dmcu *dmcu = dc->res_pool->dmcu;
+-	struct dce_hwseq *hws = dc->hwseq;
+-	struct dc_bios *dcb = dc->ctx->dc_bios;
+-	struct resource_pool *res_pool = dc->res_pool;
+-	struct dc_state  *context = dc->current_state;
+-
+-	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
+-		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
+-
+-	// Initialize the dccg
+-	if (res_pool->dccg->funcs->dccg_init)
+-		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
+-
+-	//Enable ability to power gate / don't force power on permanently
+-	enable_power_gating_plane(dc->hwseq, true);
+-
+-	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+-		REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
+-		REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
+-
+-		dcn20_dccg_init(hws);
+-
+-		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
+-		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
+-		REG_WRITE(REFCLK_CNTL, 0);
+-	} else {
+-		if (!dcb->funcs->is_accelerated_mode(dcb)) {
+-			bios_golden_init(dc);
+-			if (dc->ctx->dc_bios->fw_info_valid) {
+-				res_pool->ref_clocks.xtalin_clock_inKhz =
+-						dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
+-
+-				if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+-					if (res_pool->dccg && res_pool->hubbub) {
+-
+-						(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+-								dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
+-								&res_pool->ref_clocks.dccg_ref_clock_inKhz);
+-
+-						(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+-								res_pool->ref_clocks.dccg_ref_clock_inKhz,
+-								&res_pool->ref_clocks.dchub_ref_clock_inKhz);
+-					} else {
+-						// Not all ASICs have DCCG sw component
+-						res_pool->ref_clocks.dccg_ref_clock_inKhz =
+-								res_pool->ref_clocks.xtalin_clock_inKhz;
+-						res_pool->ref_clocks.dchub_ref_clock_inKhz =
+-								res_pool->ref_clocks.xtalin_clock_inKhz;
+-					}
+-				}
+-			} else
+-				ASSERT_CRITICAL(false);
+-			disable_vga(dc->hwseq);
+-		}
+-
+-		for (i = 0; i < dc->link_count; i++) {
+-			/* Power up AND update implementation according to the
+-			 * required signal (which may be different from the
+-			 * default signal on connector).
+-			 */
+-			struct dc_link *link = dc->links[i];
+-
+-			link->link_enc->funcs->hw_init(link->link_enc);
+-		}
+-	}
+-
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-	/* Power gate DSCs */
+-	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
+-		dcn20_dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
+-#endif
+-
+-	/* Blank pixel data with OPP DPG */
+-	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
+-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+-
+-		if (tg->funcs->is_tg_enabled(tg)) {
+-			dcn20_init_blank(dc, tg);
+-		}
+-	}
+-
+-	for (i = 0; i < res_pool->timing_generator_count; i++) {
+-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+-
+-		if (tg->funcs->is_tg_enabled(tg))
+-			tg->funcs->lock(tg);
+-	}
+-
+-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+-		struct dpp *dpp = res_pool->dpps[i];
+-
+-		dpp->funcs->dpp_reset(dpp);
+-	}
+-
+-	/* Reset all MPCC muxes */
+-	res_pool->mpc->funcs->mpc_init(res_pool->mpc);
+-
+-	/* initialize OPP mpc_tree parameter */
+-	for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
+-		res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
+-		res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
+-		for (j = 0; j < MAX_PIPES; j++)
+-			res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
+-	}
+-
+-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+-		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+-		struct hubp *hubp = dc->res_pool->hubps[i];
+-		struct dpp *dpp = dc->res_pool->dpps[i];
+-
+-		pipe_ctx->stream_res.tg = tg;
+-		pipe_ctx->pipe_idx = i;
+-
+-		pipe_ctx->plane_res.hubp = hubp;
+-		pipe_ctx->plane_res.dpp = dpp;
+-		pipe_ctx->plane_res.mpcc_inst = dpp->inst;
+-		hubp->mpcc_id = dpp->inst;
+-		hubp->opp_id = OPP_ID_INVALID;
+-		hubp->power_gated = false;
+-		pipe_ctx->stream_res.opp = NULL;
+-
+-		hubp->funcs->hubp_init(hubp);
+-
+-		//dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
+-		//dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
+-		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
+-		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
+-		/*to do*/
+-		hwss1_plane_atomic_disconnect(dc, pipe_ctx);
+-	}
+-
+-	/* initialize DWB pointer to MCIF_WB */
+-	for (i = 0; i < res_pool->res_cap->num_dwb; i++)
+-		res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
+-
+-	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
+-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+-
+-		if (tg->funcs->is_tg_enabled(tg))
+-			tg->funcs->unlock(tg);
+-	}
+-
+-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+-		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+-
+-		dc->hwss.disable_plane(dc, pipe_ctx);
+-
+-		pipe_ctx->stream_res.tg = NULL;
+-		pipe_ctx->plane_res.hubp = NULL;
+-	}
+-
+-	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
+-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
+-
+-		tg->funcs->tg_init(tg);
+-	}
+-
+-	/* end of FPGA. Below if real ASIC */
+-	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+-		return;
+-
+-
+-	for (i = 0; i < res_pool->audio_count; i++) {
+-		struct audio *audio = res_pool->audios[i];
+-
+-		audio->funcs->hw_init(audio);
+-	}
+-
+-	if (abm != NULL) {
+-		abm->funcs->init_backlight(abm);
+-		abm->funcs->abm_init(abm);
+-	}
+-
+-	if (dmcu != NULL)
+-		dmcu->funcs->dmcu_init(dmcu);
+-
+-	if (abm != NULL && dmcu != NULL)
+-		abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
+-
+-	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
+-	REG_WRITE(DIO_MEM_PWR_CTRL, 0);
+-
+-	if (!dc->debug.disable_clock_gate) {
+-		/* enable all DCN clock gating */
+-		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
+-
+-		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
+-
+-		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
+-	}
+-
+-}
+-
+ enum dc_status dcn20_enable_stream_timing(
+ 		struct pipe_ctx *pipe_ctx,
+ 		struct dc_state *context,
+@@ -1414,7 +1179,7 @@ static void dcn20_apply_ctx_for_surface(
+ 			if (old_pipe_ctx->stream_res.tg == tg &&
+ 			    old_pipe_ctx->plane_res.hubp &&
+ 			    old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID)
+-				dcn20_disable_plane(dc, old_pipe_ctx);
++				dc->hwss.disable_plane(dc, old_pipe_ctx);
+ 		}
+ 
+ 		if ((!pipe_ctx->plane_state ||
+@@ -2174,14 +1939,126 @@ static void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
+ 						hubp->inst, mode);
+ }
+ 
++static void dcn20_fpga_init_hw(struct dc *dc)
++{
++	int i, j;
++	struct dce_hwseq *hws = dc->hwseq;
++	struct resource_pool *res_pool = dc->res_pool;
++	struct dc_state  *context = dc->current_state;
++
++	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
++		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
++
++	// Initialize the dccg
++	if (res_pool->dccg->funcs->dccg_init)
++		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
++
++	//Enable ability to power gate / don't force power on permanently
++	dc->hwss.enable_power_gating_plane(hws, true);
++
++	// Specific to FPGA dccg and registers
++	REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
++	REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
++
++	dcn20_dccg_init(hws);
++
++	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
++	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
++	REG_WRITE(REFCLK_CNTL, 0);
++	//
++
++
++	/* Blank pixel data with OPP DPG */
++	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
++		struct timing_generator *tg = dc->res_pool->timing_generators[i];
++
++		if (tg->funcs->is_tg_enabled(tg))
++			dcn20_init_blank(dc, tg);
++	}
++
++	for (i = 0; i < res_pool->timing_generator_count; i++) {
++		struct timing_generator *tg = dc->res_pool->timing_generators[i];
++
++		if (tg->funcs->is_tg_enabled(tg))
++			tg->funcs->lock(tg);
++	}
++
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
++		struct dpp *dpp = res_pool->dpps[i];
++
++		dpp->funcs->dpp_reset(dpp);
++	}
++
++	/* Reset all MPCC muxes */
++	res_pool->mpc->funcs->mpc_init(res_pool->mpc);
++
++	/* initialize OPP mpc_tree parameter */
++	for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
++		res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
++		res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
++		for (j = 0; j < MAX_PIPES; j++)
++			res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
++	}
++
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
++		struct timing_generator *tg = dc->res_pool->timing_generators[i];
++		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
++		struct hubp *hubp = dc->res_pool->hubps[i];
++		struct dpp *dpp = dc->res_pool->dpps[i];
++
++		pipe_ctx->stream_res.tg = tg;
++		pipe_ctx->pipe_idx = i;
++
++		pipe_ctx->plane_res.hubp = hubp;
++		pipe_ctx->plane_res.dpp = dpp;
++		pipe_ctx->plane_res.mpcc_inst = dpp->inst;
++		hubp->mpcc_id = dpp->inst;
++		hubp->opp_id = OPP_ID_INVALID;
++		hubp->power_gated = false;
++		pipe_ctx->stream_res.opp = NULL;
++
++		hubp->funcs->hubp_init(hubp);
++
++		//dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
++		//dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
++		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
++		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
++		/*to do*/
++		hwss1_plane_atomic_disconnect(dc, pipe_ctx);
++	}
++
++	/* initialize DWB pointer to MCIF_WB */
++	for (i = 0; i < res_pool->res_cap->num_dwb; i++)
++		res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
++
++	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
++		struct timing_generator *tg = dc->res_pool->timing_generators[i];
++
++		if (tg->funcs->is_tg_enabled(tg))
++			tg->funcs->unlock(tg);
++	}
++
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
++		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
++
++		dc->hwss.disable_plane(dc, pipe_ctx);
++
++		pipe_ctx->stream_res.tg = NULL;
++		pipe_ctx->plane_res.hubp = NULL;
++	}
++
++	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
++		struct timing_generator *tg = dc->res_pool->timing_generators[i];
++
++		tg->funcs->tg_init(tg);
++	}
++}
++
+ void dcn20_hw_sequencer_construct(struct dc *dc)
+ {
+ 	dcn10_hw_sequencer_construct(dc);
+-	dc->hwss.init_hw = dcn20_init_hw;
+-	dc->hwss.init_pipes = NULL;
+ 	dc->hwss.unblank_stream = dcn20_unblank_stream;
+ 	dc->hwss.update_plane_addr = dcn20_update_plane_addr;
+-	dc->hwss.disable_plane = dcn20_disable_plane,
+ 	dc->hwss.enable_stream_timing = dcn20_enable_stream_timing;
+ 	dc->hwss.program_triplebuffer = dcn20_program_tripleBuffer;
+ 	dc->hwss.set_input_transfer_func = dcn20_set_input_transfer_func;
+@@ -2209,5 +2086,21 @@ void dcn20_hw_sequencer_construct(struct dc *dc)
+ 	dc->hwss.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap;
+ 	dc->hwss.update_mpcc = dcn20_update_mpcc;
+ 	dc->hwss.set_flip_control_gsl = dcn20_set_flip_control_gsl;
+-	dc->hwss.did_underflow_occur = dcn10_did_underflow_occur;
++	dc->hwss.init_blank = dcn20_init_blank;
++	dc->hwss.disable_plane = dcn20_disable_plane;
++	dc->hwss.plane_atomic_disable = dcn20_plane_atomic_disable;
++	dc->hwss.enable_power_gating_plane = dcn20_enable_power_gating_plane;
++	dc->hwss.dpp_pg_control = dcn20_dpp_pg_control;
++	dc->hwss.hubp_pg_control = dcn20_hubp_pg_control;
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
++#endif
++	dc->hwss.disable_vga = dcn20_disable_vga;
++
++	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
++		dc->hwss.init_hw = dcn20_fpga_init_hw;
++		dc->hwss.init_pipes = NULL;
++	}
++
++
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+index 9502478c4a1b..c1f29b1654d9 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+@@ -141,6 +141,10 @@ struct hubbub_funcs {
+ 			struct dcn_watermark_set *watermarks,
+ 			unsigned int refclk_mhz,
+ 			bool safe_to_lower);
++
++	bool (*is_allow_self_refresh_enabled)(struct hubbub *hubbub);
++	void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow);
++
+ };
+ 
+ struct hubbub {
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index 28645e10f854..80de2febd7cb 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -78,6 +78,8 @@ struct stream_resource;
+ struct dc_phy_addr_space_config;
+ struct dc_virtual_addr_space_config;
+ #endif
++struct hubp;
++struct dpp;
+ 
+ struct hw_sequencer_funcs {
+ 
+@@ -280,6 +282,36 @@ struct hw_sequencer_funcs {
+ 	void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx);
+ 	bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+ 
++	void (*init_blank)(struct dc *dc, struct timing_generator *tg);
++	void (*disable_vga)(struct dce_hwseq *hws);
++	void (*bios_golden_init)(struct dc *dc);
++	void (*plane_atomic_power_down)(struct dc *dc,
++			struct dpp *dpp,
++			struct hubp *hubp);
++
++	void (*plane_atomic_disable)(
++			struct dc *dc, struct pipe_ctx *pipe_ctx);
++
++	void (*enable_power_gating_plane)(
++		struct dce_hwseq *hws,
++		bool enable);
++
++	void (*dpp_pg_control)(
++			struct dce_hwseq *hws,
++			unsigned int dpp_inst,
++			bool power_on);
++
++	void (*hubp_pg_control)(
++			struct dce_hwseq *hws,
++			unsigned int hubp_inst,
++			bool power_on);
++
++	void (*dsc_pg_control)(
++			struct dce_hwseq *hws,
++			unsigned int dsc_inst,
++			bool power_on);
++
++
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
+ 	void (*program_all_writeback_pipes_in_tree)(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3556-drm-amd-display-fix-a-potential-null-pointer-derefer.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3556-drm-amd-display-fix-a-potential-null-pointer-derefer.patch
new file mode 100644
index 00000000..dcbfaa00
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3556-drm-amd-display-fix-a-potential-null-pointer-derefer.patch
@@ -0,0 +1,44 @@
+From 77fb10b27547ff1f7bc5800011f01aca541339e4 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Fri, 16 Aug 2019 23:10:11 +0100
+Subject: [PATCH 3556/4256] drm/amd/display: fix a potential null pointer
+ dereference
+
+Currently the pointer init_data is dereferenced on the assignment
+of fw_info before init_data is sanity checked to see if it is null.
+Fix te potential null pointer dereference on init_data by only
+performing dereference after it is null checked.
+
+Addresses-Coverity: ("Dereference before null check")
+Fixes: 9adc8050bf3c ("drm/amd/display: make firmware info only load once during dc_bios create")
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+index 990481b35682..5933a704847e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+@@ -1233,7 +1233,7 @@ static bool calc_pll_max_vco_construct(
+ 			struct calc_pll_clock_source_init_data *init_data)
+ {
+ 	uint32_t i;
+-	struct dc_firmware_info *fw_info = &init_data->bp->fw_info;
++	struct dc_firmware_info *fw_info;
+ 	if (calc_pll_cs == NULL ||
+ 			init_data == NULL ||
+ 			init_data->bp == NULL)
+@@ -1242,6 +1242,7 @@ static bool calc_pll_max_vco_construct(
+ 	if (init_data->bp->fw_info_valid)
+ 		return false;
+ 
++	fw_info = &init_data->bp->fw_info;
+ 	calc_pll_cs->ctx = init_data->ctx;
+ 	calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency;
+ 	calc_pll_cs->min_vco_khz =
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3557-amd-amdkfd-add-Arcturus-vf-DID-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3557-amd-amdkfd-add-Arcturus-vf-DID-support.patch
new file mode 100644
index 00000000..934d1402
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3557-amd-amdkfd-add-Arcturus-vf-DID-support.patch
@@ -0,0 +1,26 @@
+From 9bde131594679b887c90d70ca13da57d49c39ce7 Mon Sep 17 00:00:00 2001
+From: "Frank.Min" <Frank.Min@amd.com>
+Date: Fri, 16 Aug 2019 15:08:31 +0800
+Subject: [PATCH 3557/4256] amd/amdkfd: add Arcturus vf DID support
+
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Frank.Min <Frank.Min@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index 6c0f16bcb1aa..d8344f9dc7e0 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -490,6 +490,7 @@ static const struct kfd_deviceid supported_devices[] = {
+ 	{ 0x738C, &arcturus_device_info },	/* Arcturus */
+ 	{ 0x7388, &arcturus_device_info },	/* Arcturus */
+ 	{ 0x738E, &arcturus_device_info },	/* Arcturus */
++	{ 0x7390, &arcturus_device_info },	/* Arcturus vf */
+ 	{ 0x7310, &navi10_device_info },	/* Navi10 */
+ 	{ 0x7312, &navi10_device_info },	/* Navi10 */
+ 	{ 0x7318, &navi10_device_info },	/* Navi10 */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3558-drm-powerplay-Fix-Vega20-power-reading-again.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3558-drm-powerplay-Fix-Vega20-power-reading-again.patch
new file mode 100644
index 00000000..3f9e58a1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3558-drm-powerplay-Fix-Vega20-power-reading-again.patch
@@ -0,0 +1,60 @@
+From fc663a90c06aae37be13fc66ac880c64c49a33ff Mon Sep 17 00:00:00 2001
+From: Kent Russell <kent.russell@amd.com>
+Date: Fri, 23 Aug 2019 09:13:18 -0400
+Subject: [PATCH 3558/4256] drm/powerplay: Fix Vega20 power reading again
+
+For the 40.46 SMU release, they changed CurrSocketPower to
+AverageSocketPower, but this was changed back in 40.47 so just check if
+it's 40.46 and make the appropriate change
+
+Tested with 40.45, 40.46 and 40.47 successfully
+
+Change-Id: Icbbe6fd3381b8ad6298c2d0852a726ffac98f93a
+Signed-off-by: Kent Russell <kent.russell@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 7 ++++---
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c         | 7 ++++---
+ 2 files changed, 8 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+index 9f50a12f5c03..98a6f5305974 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+@@ -2101,10 +2101,11 @@ static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
+ 	if (ret)
+ 		return ret;
+ 
+-	if (hwmgr->smu_version < 0x282e00)
+-		*query = metrics_table.CurrSocketPower << 8;
+-	else
++	/* For the 40.46 release, they changed the value name */
++	if (hwmgr->smu_version == 0x282e00)
+ 		*query = metrics_table.AverageSocketPower << 8;
++	else
++		*query = metrics_table.CurrSocketPower << 8;
+ 
+ 	return ret;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 0fac824490d7..899bf96b23e1 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -2932,10 +2932,11 @@ static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)
+ 	if (ret)
+ 		return ret;
+ 
+-	if (smu_version < 0x282e00)
+-		*value = metrics.CurrSocketPower << 8;
+-	else
++	/* For the 40.46 release, they changed the value name */
++	if (smu_version == 0x282e00)
+ 		*value = metrics.AverageSocketPower << 8;
++	else
++		*value = metrics.CurrSocketPower << 8;
+ 
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3559-drm-amdgpu-powerplay-smu7-enable-mclk-switching-if-m.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3559-drm-amdgpu-powerplay-smu7-enable-mclk-switching-if-m.patch
new file mode 100644
index 00000000..07f8418b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3559-drm-amdgpu-powerplay-smu7-enable-mclk-switching-if-m.patch
@@ -0,0 +1,36 @@
+From 79bc28dea98505da9aaaf4f0e9bb8303fa0848af Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 8 Aug 2019 00:47:49 -0500
+Subject: [PATCH 3559/4256] drm/amdgpu/powerplay/smu7: enable mclk switching if
+ monitors are synced
+
+If DC has synced the displays, we can enable mclk switching to
+save power.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+index b468f634ffa1..25e68f245dba 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -2955,9 +2955,10 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
+ 	if (hwmgr->display_config->num_display == 0)
+ 		disable_mclk_switching = false;
+ 	else
+-		disable_mclk_switching = ((1 < hwmgr->display_config->num_display) ||
+-					  disable_mclk_switching_for_frame_lock ||
+-					  smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time));
++		disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
++					  !hwmgr->display_config->multi_monitor_in_sync) ||
++			disable_mclk_switching_for_frame_lock ||
++			smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time);
+ 
+ 	sclk = smu7_ps->performance_levels[0].engine_clock;
+ 	mclk = smu7_ps->performance_levels[0].memory_clock;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3560-drm-amdgpu-powerplay-vega10-enable-mclk-switching-if.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3560-drm-amdgpu-powerplay-vega10-enable-mclk-switching-if.patch
new file mode 100644
index 00000000..ee538d60
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3560-drm-amdgpu-powerplay-vega10-enable-mclk-switching-if.patch
@@ -0,0 +1,32 @@
+From 81f7097613b3b13134f0c58bd41c5b49591cbed4 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 8 Aug 2019 00:48:58 -0500
+Subject: [PATCH 3560/4256] drm/amdgpu/powerplay/vega10: enable mclk switching
+ if monitors are synced
+
+If DC has synced the displays, we can enable mclk switching to
+save power.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+index 3ac4745708cf..ccceaba5914a 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+@@ -3219,7 +3219,8 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
+ 	if (hwmgr->display_config->num_display == 0)
+ 		disable_mclk_switching = false;
+ 	else
+-		disable_mclk_switching = (hwmgr->display_config->num_display > 1) ||
++		disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
++					  !hwmgr->display_config->multi_monitor_in_sync) ||
+ 			disable_mclk_switching_for_frame_lock ||
+ 			disable_mclk_switching_for_vr ||
+ 			force_mclk_high;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3561-drm-amd-display-update-bw_calcs-to-take-pipe-sync-in.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3561-drm-amd-display-update-bw_calcs-to-take-pipe-sync-in.patch
new file mode 100644
index 00000000..940be956
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3561-drm-amd-display-update-bw_calcs-to-take-pipe-sync-in.patch
@@ -0,0 +1,78 @@
+From 8f5936be8109638a1ce825df8f835040edb60984 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 8 Aug 2019 09:03:46 -0500
+Subject: [PATCH 3561/4256] drm/amd/display: update bw_calcs to take pipe sync
+ into account (v3)
+
+Properly set all_displays_in_sync so that when the data is
+propagated to powerplay, it's set properly and we can enable
+mclk switching when all monitors are in sync.
+
+v2: fix logic, clean up
+v3: check for blending chains, simplify logic
+
+Acked-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/display/dc/calcs/dce_calcs.c  | 30 +++++++++++++++++--
+ 1 file changed, 28 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+index fdab16ea0a2e..562489fdbc22 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
++++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+@@ -23,6 +23,7 @@
+  *
+  */
+ 
++#include "resource.h"
+ #include "dm_services.h"
+ #include "dce_calcs.h"
+ #include "dc.h"
+@@ -2975,6 +2976,32 @@ static void populate_initial_data(
+ 	data->number_of_displays = num_displays;
+ }
+ 
++static bool all_displays_in_sync(const struct pipe_ctx pipe[],
++				 int pipe_count)
++{
++	const struct pipe_ctx *active_pipes[MAX_PIPES];
++	int i, num_active_pipes = 0;
++
++	for (i = 0; i < pipe_count; i++) {
++		if (!pipe[i].stream || pipe[i].top_pipe)
++			continue;
++
++		active_pipes[num_active_pipes++] = &pipe[i];
++	}
++
++	if (!num_active_pipes)
++		return false;
++
++	for (i = 1; i < num_active_pipes; ++i) {
++		if (!resource_are_streams_timing_synchronizable(
++			    active_pipes[0]->stream, active_pipes[i]->stream)) {
++			return false;
++		}
++	}
++
++	return true;
++}
++
+ /**
+  * Return:
+  *	true -	Display(s) configuration supported.
+@@ -2996,8 +3023,7 @@ bool bw_calcs(struct dc_context *ctx,
+ 
+ 	populate_initial_data(pipe, pipe_count, data);
+ 
+-	/*TODO: this should be taken out calcs output and assigned during timing sync for pplib use*/
+-	calcs_output->all_displays_in_sync = false;
++	calcs_output->all_displays_in_sync = all_displays_in_sync(pipe, pipe_count);
+ 
+ 	if (data->number_of_displays != 0) {
+ 		uint8_t yclk_lvl, sclk_lvl;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3562-drm-amdgpu-display-add-flag-for-multi-display-mclk-s.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3562-drm-amdgpu-display-add-flag-for-multi-display-mclk-s.patch
new file mode 100644
index 00000000..1dcda113
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3562-drm-amdgpu-display-add-flag-for-multi-display-mclk-s.patch
@@ -0,0 +1,80 @@
+From 76c9008510e07b498564da8fd69f035537d1007a Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 22 Aug 2019 14:17:57 -0500
+Subject: [PATCH 3562/4256] drm/amdgpu/display: add flag for multi-display mclk
+ switching
+
+Add a dcfeaturemask flag for mclk switching.  Disable by default;
+enable once the feature has seen more testing.
+
+Set amdgpu.dcfeaturemask=2 on the kernel command line in grub
+to enable this.
+
+Acked-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
+ drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c  | 5 ++++-
+ drivers/gpu/drm/amd/display/dc/dc.h               | 2 +-
+ drivers/gpu/drm/amd/include/amd_shared.h          | 1 +
+ 4 files changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 4bec6ffb3940..1171949361af 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -692,6 +692,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ 	if (amdgpu_dc_feature_mask & DC_FBC_MASK)
+ 		init_data.flags.fbc_support = true;
+ 
++	if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
++		init_data.flags.multi_mon_pp_mclk_switch = true;
++
+ 	init_data.flags.power_down_display_on_boot = true;
+ 
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+index 562489fdbc22..dfec7ebb4db8 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
++++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+@@ -3023,7 +3023,10 @@ bool bw_calcs(struct dc_context *ctx,
+ 
+ 	populate_initial_data(pipe, pipe_count, data);
+ 
+-	calcs_output->all_displays_in_sync = all_displays_in_sync(pipe, pipe_count);
++	if (ctx->dc->config.multi_mon_pp_mclk_switch)
++		calcs_output->all_displays_in_sync = all_displays_in_sync(pipe, pipe_count);
++	else
++		calcs_output->all_displays_in_sync = false;
+ 
+ 	if (data->number_of_displays != 0) {
+ 		uint8_t yclk_lvl, sclk_lvl;
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 85863dcf8456..81b986acbae6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -223,7 +223,7 @@ struct dc_config {
+ 	bool power_down_display_on_boot;
+ 	bool edp_not_connected;
+ 	bool forced_clocks;
+-
++	bool multi_mon_pp_mclk_switch;
+ };
+ 
+ enum visual_confirm {
+diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
+index a0a7211438f2..8889aaceec60 100644
+--- a/drivers/gpu/drm/amd/include/amd_shared.h
++++ b/drivers/gpu/drm/amd/include/amd_shared.h
+@@ -142,6 +142,7 @@ enum PP_FEATURE_MASK {
+ 
+ enum DC_FEATURE_MASK {
+ 	DC_FBC_MASK = 0x1,
++	DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,
+ };
+ 
+ enum amd_dpm_forced_level;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3563-drm-amdgpu-set-adev-num_vmhubs-for-gmc6-7-8.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3563-drm-amdgpu-set-adev-num_vmhubs-for-gmc6-7-8.patch
new file mode 100644
index 00000000..cc163afa
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3563-drm-amdgpu-set-adev-num_vmhubs-for-gmc6-7-8.patch
@@ -0,0 +1,58 @@
+From 1a4d6534b2c2625d93548988ce7354ce71e832c8 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 23 Aug 2019 09:42:33 -0500
+Subject: [PATCH 3563/4256] drm/amdgpu: set adev->num_vmhubs for gmc6,7,8
+
+So that we properly handle them on older asics.
+
+Fixes: 3ff985485b29 ("drm/amdgpu: Export function to flush TLB of specific vm hub")
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 ++
+ drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 ++
+ drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 ++
+ 3 files changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+index 2edb7fc84398..cdcac811a85f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+@@ -839,6 +839,8 @@ static int gmc_v6_0_sw_init(void *handle)
+ 	int dma_bits;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
++	adev->num_vmhubs = 1;
++
+ 	if (adev->flags & AMD_IS_APU) {
+ 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
+ 	} else {
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+index 655bc4690958..26508a767582 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+@@ -960,6 +960,8 @@ static int gmc_v7_0_sw_init(void *handle)
+ 	int dma_bits;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
++	adev->num_vmhubs = 1;
++
+ 	if (adev->flags & AMD_IS_APU) {
+ 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
+ 	} else {
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+index a27a5ae75438..43ee4bc47f43 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+@@ -1085,6 +1085,8 @@ static int gmc_v8_0_sw_init(void *handle)
+ 	int dma_bits;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
++	adev->num_vmhubs = 1;
++
+ 	if (adev->flags & AMD_IS_APU) {
+ 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
+ 	} else {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3564-drm-amd-display-re-structure-odm-to-allow-4-to-1-sup.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3564-drm-amd-display-re-structure-odm-to-allow-4-to-1-sup.patch
new file mode 100644
index 00000000..3a24bee8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3564-drm-amd-display-re-structure-odm-to-allow-4-to-1-sup.patch
@@ -0,0 +1,1142 @@
+From 2141ed4abbffcf5e3b7adbd7381bdfd572f138c0 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Tue, 6 Aug 2019 17:17:28 -0400
+Subject: [PATCH 3564/4256] drm/amd/display: re structure odm to allow 4 to 1
+ support
+
+Currently odm is handled using top_bottom pipe by special casing
+the differing opps to differentiate from mpc combine.
+
+Since top/bottom pipe list was made to track mpc muxing this creates
+difficulties in adding a 4 pipe odm case support.
+
+Rather than continue using mpc combine list, this change reworks odm
+to use it's own linked list to keep track of odm combine pipes. This
+also opens up options for using mpo with odm, if a practical use case
+is ever found.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c      |  10 +-
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  33 ++-
+ .../drm/amd/display/dc/core/dc_link_hwss.c    |  36 +--
+ .../gpu/drm/amd/display/dc/core/dc_resource.c | 150 ++++-------
+ .../display/dc/dce110/dce110_hw_sequencer.c   |   7 +-
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   2 +-
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  90 ++++---
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 244 ++++++++++++------
+ .../display/dc/dcn20/dcn20_stream_encoder.c   |   2 +-
+ .../gpu/drm/amd/display/dc/inc/core_types.h   |   2 +
+ .../amd/display/dc/inc/hw/stream_encoder.h    |   2 +-
+ drivers/gpu/drm/amd/display/dc/inc/resource.h |   3 -
+ 12 files changed, 316 insertions(+), 265 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index af2586b5c238..bc713677faa9 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1869,9 +1869,7 @@ static void commit_planes_do_stream_update(struct dc *dc,
+ 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
+ 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
+ 
+-		if (!pipe_ctx->top_pipe &&
+-			pipe_ctx->stream &&
+-			pipe_ctx->stream == stream) {
++		if (!pipe_ctx->top_pipe &&  !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
+ 
+ 			if (stream_update->periodic_interrupt0 &&
+ 					dc->hwss.setup_periodic_interrupt)
+@@ -1897,7 +1895,7 @@ static void commit_planes_do_stream_update(struct dc *dc,
+ 
+ 			if (stream_update->dither_option) {
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+-				struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
++				struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
+ #endif
+ 				resource_build_bit_depth_reduction_params(pipe_ctx->stream,
+ 									&pipe_ctx->stream->bit_depth_params);
+@@ -1905,10 +1903,12 @@ static void commit_planes_do_stream_update(struct dc *dc,
+ 						&stream->bit_depth_params,
+ 						&stream->clamping);
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+-				if (odm_pipe)
++				while (odm_pipe) {
+ 					odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
+ 							&stream->bit_depth_params,
+ 							&stream->clamping);
++					odm_pipe = odm_pipe->next_odm_pipe;
++				}
+ #endif
+ 			}
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 2e87942b3e9c..2aa44b28b673 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -3095,14 +3095,19 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ 				controller_test_pattern, color_depth);
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 		else if (opp->funcs->opp_set_disp_pattern_generator) {
+-			struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
++			struct pipe_ctx *odm_pipe;
++			int opp_cnt = 1;
+ 
+-			if (bot_odm_pipe) {
+-				struct output_pixel_processor *bot_opp = bot_odm_pipe->stream_res.opp;
++			for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
++				opp_cnt++;
+ 
+-				bot_opp->funcs->opp_program_bit_depth_reduction(bot_opp, &params);
+-				width /= 2;
+-				bot_opp->funcs->opp_set_disp_pattern_generator(bot_opp,
++			width /= opp_cnt;
++
++			for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
++				struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
++
++				odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
++				odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
+ 					controller_test_pattern,
+ 					color_depth,
+ 					NULL,
+@@ -3131,14 +3136,18 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ 				color_depth);
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 		else if (opp->funcs->opp_set_disp_pattern_generator) {
+-			struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
++			struct pipe_ctx *odm_pipe;
++			int opp_cnt = 1;
++
++			for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
++				opp_cnt++;
+ 
+-			if (bot_odm_pipe) {
+-				struct output_pixel_processor *bot_opp = bot_odm_pipe->stream_res.opp;
++			width /= opp_cnt;
++			for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
++				struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
+ 
+-				bot_opp->funcs->opp_program_bit_depth_reduction(bot_opp, &params);
+-				width /= 2;
+-				bot_opp->funcs->opp_set_disp_pattern_generator(bot_opp,
++				odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
++				odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
+ 					CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
+ 					color_depth,
+ 					NULL,
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index 35c5467e60e8..fe9a4e4b9d1f 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -275,7 +275,7 @@ void dp_retrain_link_dp_test(struct dc_link *link,
+ 
+ 	for (i = 0; i < MAX_PIPES; i++) {
+ 		if (pipes[i].stream != NULL &&
+-			!pipes[i].top_pipe &&
++			!pipes[i].top_pipe && !pipes[i].prev_odm_pipe &&
+ 			pipes[i].stream->link != NULL &&
+ 			pipes[i].stream_res.stream_enc != NULL) {
+ 			udelay(100);
+@@ -381,7 +381,11 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ 	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
+ 	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+-	struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
++	struct pipe_ctx *odm_pipe;
++	int opp_cnt = 1;
++
++	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
++		opp_cnt++;
+ 
+ 	if (enable) {
+ 		struct dsc_config dsc_cfg;
+@@ -389,26 +393,24 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ 		enum optc_dsc_mode optc_dsc_mode;
+ 
+ 		/* Enable DSC hw block */
+-		dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
++		dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
+ 		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
+ 		dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
+ 		dsc_cfg.color_depth = stream->timing.display_color_depth;
+ 		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
++		ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
++		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
++
++		dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
++		dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
++		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
++			struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
+ 
+-		if (odm_pipe) {
+-			struct display_stream_compressor *bot_dsc = odm_pipe->stream_res.dsc;
+-
+-			dsc_cfg.pic_width /= 2;
+-			ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % 2 == 0);
+-			dsc_cfg.dc_dsc_cfg.num_slices_h /= 2;
+-			dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
+-			bot_dsc->funcs->dsc_set_config(bot_dsc, &dsc_cfg, &dsc_optc_cfg);
+-			dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
+-			bot_dsc->funcs->dsc_enable(bot_dsc, odm_pipe->stream_res.opp->inst);
+-		} else {
+-			dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
+-			dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
++			odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
++			odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
+ 		}
++		dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
++		dsc_cfg.pic_width *= opp_cnt;
+ 
+ 		optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
+ 
+@@ -449,7 +451,7 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ 
+ 		/* disable DSC block */
+ 		pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
+-		if (odm_pipe)
++		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
+ 			odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
+ 	}
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index fa94dfc04dce..1464f4c60089 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -1114,8 +1114,9 @@ struct pipe_ctx *resource_get_head_pipe_for_stream(
+ {
+ 	int i;
+ 	for (i = 0; i < MAX_PIPES; i++) {
+-		if (res_ctx->pipe_ctx[i].stream == stream &&
+-				!res_ctx->pipe_ctx[i].top_pipe) {
++		if (res_ctx->pipe_ctx[i].stream == stream
++				&& !res_ctx->pipe_ctx[i].top_pipe
++				&& !res_ctx->pipe_ctx[i].prev_odm_pipe) {
+ 			return &res_ctx->pipe_ctx[i];
+ 			break;
+ 		}
+@@ -1123,15 +1124,11 @@ struct pipe_ctx *resource_get_head_pipe_for_stream(
+ 	return NULL;
+ }
+ 
+-static struct pipe_ctx *resource_get_tail_pipe_for_stream(
++static struct pipe_ctx *resource_get_tail_pipe(
+ 		struct resource_context *res_ctx,
+-		struct dc_stream_state *stream)
++		struct pipe_ctx *head_pipe)
+ {
+-	struct pipe_ctx *head_pipe, *tail_pipe;
+-	head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
+-
+-	if (!head_pipe)
+-		return NULL;
++	struct pipe_ctx *tail_pipe;
+ 
+ 	tail_pipe = head_pipe->bottom_pipe;
+ 
+@@ -1147,31 +1144,20 @@ static struct pipe_ctx *resource_get_tail_pipe_for_stream(
+  * A free_pipe for a stream is defined here as a pipe
+  * that has no surface attached yet
+  */
+-static struct pipe_ctx *acquire_free_pipe_for_stream(
++static struct pipe_ctx *acquire_free_pipe_for_head(
+ 		struct dc_state *context,
+ 		const struct resource_pool *pool,
+-		struct dc_stream_state *stream)
++		struct pipe_ctx *head_pipe)
+ {
+ 	int i;
+ 	struct resource_context *res_ctx = &context->res_ctx;
+ 
+-	struct pipe_ctx *head_pipe = NULL;
+-
+-	/* Find head pipe, which has the back end set up*/
+-
+-	head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
+-
+-	if (!head_pipe) {
+-		ASSERT(0);
+-		return NULL;
+-	}
+-
+ 	if (!head_pipe->plane_state)
+ 		return head_pipe;
+ 
+ 	/* Re-use pipe already acquired for this stream if available*/
+ 	for (i = pool->pipe_count - 1; i >= 0; i--) {
+-		if (res_ctx->pipe_ctx[i].stream == stream &&
++		if (res_ctx->pipe_ctx[i].stream == head_pipe->stream &&
+ 				!res_ctx->pipe_ctx[i].plane_state) {
+ 			return &res_ctx->pipe_ctx[i];
+ 		}
+@@ -1185,8 +1171,7 @@ static struct pipe_ctx *acquire_free_pipe_for_stream(
+ 	if (!pool->funcs->acquire_idle_pipe_for_layer)
+ 		return NULL;
+ 
+-	return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
+-
++	return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
+ }
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+@@ -1200,7 +1185,7 @@ static int acquire_first_split_pipe(
+ 	for (i = 0; i < pool->pipe_count; i++) {
+ 		struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
+ 
+-		if (split_pipe->top_pipe && !dc_res_is_odm_head_pipe(split_pipe) &&
++		if (split_pipe->top_pipe &&
+ 				split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
+ 			split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
+ 			if (split_pipe->bottom_pipe)
+@@ -1261,39 +1246,41 @@ bool dc_add_plane_to_context(
+ 		return false;
+ 	}
+ 
+-	tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
+-	ASSERT(tail_pipe);
++	/* retain new surface, but only once per stream */
++	dc_plane_state_retain(plane_state);
+ 
+-	free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
++	while (head_pipe) {
++		tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
++		ASSERT(tail_pipe);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+-	if (!free_pipe) {
+-		int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
+-		if (pipe_idx >= 0)
+-			free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
+-	}
+-#endif
+-	if (!free_pipe)
+-		return false;
++		free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
+ 
+-	/* retain new surfaces */
+-	dc_plane_state_retain(plane_state);
+-	free_pipe->plane_state = plane_state;
+-
+-	if (head_pipe != free_pipe) {
+-		free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
+-		free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
+-		free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
+-		free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
+-		free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
+-		free_pipe->clock_source = tail_pipe->clock_source;
+-		free_pipe->top_pipe = tail_pipe;
+-		tail_pipe->bottom_pipe = free_pipe;
+-	} else if (free_pipe->bottom_pipe && free_pipe->bottom_pipe->plane_state == NULL) {
+-		ASSERT(free_pipe->bottom_pipe->stream_res.opp != free_pipe->stream_res.opp);
+-		free_pipe->bottom_pipe->plane_state = plane_state;
+-	}
++	#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
++		if (!free_pipe) {
++			int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
++			if (pipe_idx >= 0)
++				free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
++		}
++	#endif
++		if (!free_pipe) {
++			dc_plane_state_release(plane_state);
++			return false;
++		}
+ 
++		free_pipe->plane_state = plane_state;
++
++		if (head_pipe != free_pipe) {
++			free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
++			free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
++			free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
++			free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
++			free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
++			free_pipe->clock_source = tail_pipe->clock_source;
++			free_pipe->top_pipe = tail_pipe;
++			tail_pipe->bottom_pipe = free_pipe;
++		}
++		head_pipe = head_pipe->next_odm_pipe;
++	}
+ 	/* assign new surfaces*/
+ 	stream_status->plane_states[stream_status->plane_count] = plane_state;
+ 
+@@ -1302,35 +1289,6 @@ bool dc_add_plane_to_context(
+ 	return true;
+ }
+ 
+-struct pipe_ctx *dc_res_get_odm_bottom_pipe(struct pipe_ctx *pipe_ctx)
+-{
+-	struct pipe_ctx *bottom_pipe = pipe_ctx->bottom_pipe;
+-
+-	/* ODM should only be updated once per otg */
+-	if (pipe_ctx->top_pipe)
+-		return NULL;
+-
+-	while (bottom_pipe) {
+-		if (bottom_pipe->stream_res.opp != pipe_ctx->stream_res.opp)
+-			break;
+-		bottom_pipe = bottom_pipe->bottom_pipe;
+-	}
+-
+-	return bottom_pipe;
+-}
+-
+-bool dc_res_is_odm_head_pipe(struct pipe_ctx *pipe_ctx)
+-{
+-	struct pipe_ctx *top_pipe = pipe_ctx->top_pipe;
+-
+-	if (!top_pipe)
+-		return false;
+-	if (top_pipe && top_pipe->stream_res.opp == pipe_ctx->stream_res.opp)
+-		return false;
+-
+-	return true;
+-}
+-
+ bool dc_remove_plane_from_context(
+ 		const struct dc *dc,
+ 		struct dc_stream_state *stream,
+@@ -1357,12 +1315,6 @@ bool dc_remove_plane_from_context(
+ 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+ 
+ 		if (pipe_ctx->plane_state == plane_state) {
+-			if (dc_res_is_odm_head_pipe(pipe_ctx)) {
+-				pipe_ctx->plane_state = NULL;
+-				pipe_ctx->bottom_pipe = NULL;
+-				continue;
+-			}
+-
+ 			if (pipe_ctx->top_pipe)
+ 				pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
+ 
+@@ -1377,13 +1329,10 @@ bool dc_remove_plane_from_context(
+ 			 * For head pipe detach surfaces from pipe for tail
+ 			 * pipe just zero it out
+ 			 */
+-			if (!pipe_ctx->top_pipe) {
++			if (!pipe_ctx->top_pipe)
+ 				pipe_ctx->plane_state = NULL;
+-				if (!dc_res_get_odm_bottom_pipe(pipe_ctx))
+-					pipe_ctx->bottom_pipe = NULL;
+-			} else {
++			else
+ 				memset(pipe_ctx, 0, sizeof(*pipe_ctx));
+-			}
+ 		}
+ 	}
+ 
+@@ -1752,9 +1701,6 @@ enum dc_status dc_remove_stream_from_ctx(
+ 	for (i = 0; i < MAX_PIPES; i++) {
+ 		if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
+ 				!new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
+-			struct pipe_ctx *odm_pipe =
+-					dc_res_get_odm_bottom_pipe(&new_ctx->res_ctx.pipe_ctx[i]);
+-
+ 			del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
+ 
+ 			ASSERT(del_pipe->stream_res.stream_enc);
+@@ -1779,8 +1725,6 @@ enum dc_status dc_remove_stream_from_ctx(
+ 				dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
+ 
+ 			memset(del_pipe, 0, sizeof(*del_pipe));
+-			if (odm_pipe)
+-				memset(odm_pipe, 0, sizeof(*odm_pipe));
+ 
+ 			break;
+ 		}
+@@ -2494,6 +2438,12 @@ void dc_resource_state_copy_construct(
+ 
+ 		if (cur_pipe->bottom_pipe)
+ 			cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
++
++		if (cur_pipe->next_odm_pipe)
++			cur_pipe->next_odm_pipe =  &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
++
++		if (cur_pipe->prev_odm_pipe)
++			cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
+ 	}
+ 
+ 	for (i = 0; i < dst_ctx->stream_count; i++) {
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 5a046e5bc756..2693404cab1a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -1338,7 +1338,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ 	struct drr_params params = {0};
+ 	unsigned int event_triggers = 0;
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+-	struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
++	struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
+ #endif
+ 
+ 	if (dc->hwss.disable_stream_gating) {
+@@ -1406,7 +1406,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ 		&stream->bit_depth_params,
+ 		&stream->clamping);
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+-	if (odm_pipe) {
++	while (odm_pipe) {
+ 		odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
+ 				odm_pipe->stream_res.opp,
+ 				COLOR_SPACE_YCBCR601,
+@@ -1417,6 +1417,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ 				odm_pipe->stream_res.opp,
+ 				&stream->bit_depth_params,
+ 				&stream->clamping);
++		odm_pipe = odm_pipe->next_odm_pipe;
+ 	}
+ #endif
+ 
+@@ -2076,7 +2077,7 @@ enum dc_status dce110_apply_ctx_to_hw(
+ 		if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
+ 			continue;
+ 
+-		if (pipe_ctx->top_pipe)
++		if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
+ 			continue;
+ 
+ 		status = apply_single_controller_ctx_to_hw(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 1835157b9fad..344190be93ae 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2535,7 +2535,7 @@ struct pipe_ctx *find_top_pipe_for_stream(
+ 		if (pipe_ctx->stream != stream)
+ 			continue;
+ 
+-		if (!pipe_ctx->top_pipe)
++		if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
+ 			return pipe_ctx;
+ 	}
+ 	return NULL;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 57d9645659d8..c8c17fac2e24 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -529,11 +529,9 @@ enum dc_status dcn20_enable_stream_timing(
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	struct drr_params params = {0};
+ 	unsigned int event_triggers = 0;
+-
+-
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+-	struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
+-#endif
++	struct pipe_ctx *odm_pipe;
++	int opp_cnt = 1;
++	int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
+ 
+ 	/* by upper caller loop, pipe0 is parent pipe and be called first.
+ 	 * back end is set up by for pipe0. Other children pipe share back end
+@@ -544,14 +542,17 @@ enum dc_status dcn20_enable_stream_timing(
+ 
+ 	/* TODO check if timing_changed, disable stream if timing changed */
+ 
+-	if (odm_pipe) {
+-		int opp_inst[2] = { pipe_ctx->stream_res.opp->inst, odm_pipe->stream_res.opp->inst };
++	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
++		opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
++		opp_cnt++;
++	}
+ 
++	if (opp_cnt > 1)
+ 		pipe_ctx->stream_res.tg->funcs->set_odm_combine(
+ 				pipe_ctx->stream_res.tg,
+-				opp_inst, 2,
++				opp_inst, opp_cnt,
+ 				&pipe_ctx->stream->timing);
+-	}
++
+ 	/* HW program guide assume display already disable
+ 	 * by unplug sequence. OTG assume stop.
+ 	 */
+@@ -575,7 +576,7 @@ enum dc_status dcn20_enable_stream_timing(
+ 			pipe_ctx->stream->signal,
+ 			true);
+ 
+-	if (odm_pipe)
++	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
+ 		odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
+ 				odm_pipe->stream_res.opp,
+ 				true);
+@@ -661,7 +662,7 @@ bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
+ 	 */
+ 	if (mpc->funcs->power_on_mpc_mem_pwr)
+ 		mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
+-	if ((pipe_ctx->top_pipe == NULL || dc_res_is_odm_head_pipe(pipe_ctx))
++	if (pipe_ctx->top_pipe == NULL
+ 			&& mpc->funcs->set_output_gamma && stream->out_transfer_func) {
+ 		if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
+ 			params = &stream->out_transfer_func->pwl;
+@@ -823,17 +824,21 @@ bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
+ 
+ static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
+ {
+-	struct pipe_ctx *combine_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
++	struct pipe_ctx *odm_pipe;
++	int opp_cnt = 1;
++	int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
+ 
+-	if (combine_pipe) {
+-		int opp_inst[2] = { pipe_ctx->stream_res.opp->inst,
+-				combine_pipe->stream_res.opp->inst };
++	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
++		opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
++		opp_cnt++;
++	}
+ 
++	if (opp_cnt > 1)
+ 		pipe_ctx->stream_res.tg->funcs->set_odm_combine(
+ 				pipe_ctx->stream_res.tg,
+-				opp_inst, 2,
++				opp_inst, opp_cnt,
+ 				&pipe_ctx->stream->timing);
+-	} else
++	else
+ 		pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
+ 				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+ }
+@@ -848,7 +853,8 @@ void dcn20_blank_pixel_data(
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	enum dc_color_space color_space = stream->output_color_space;
+ 	enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
+-	struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
++	struct pipe_ctx *odm_pipe;
++	int odm_cnt = 1;
+ 
+ 	int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
+ 	int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
+@@ -856,8 +862,10 @@ void dcn20_blank_pixel_data(
+ 	/* get opp dpg blank color */
+ 	color_space_to_black_color(dc, color_space, &black_color);
+ 
+-	if (bot_odm_pipe)
+-		width = width / 2;
++	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
++		odm_cnt++;
++
++	width = width / odm_cnt;
+ 
+ 	if (blank) {
+ 		if (stream_res->abm)
+@@ -877,9 +885,9 @@ void dcn20_blank_pixel_data(
+ 			width,
+ 			height);
+ 
+-	if (bot_odm_pipe) {
+-		bot_odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
+-				bot_odm_pipe->stream_res.opp,
++	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
++		odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
++				odm_pipe->stream_res.opp,
+ 				dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE ?
+ 						CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
+ 				stream->timing.display_color_depth,
+@@ -1021,7 +1029,7 @@ static void dcn20_program_all_pipe_in_tree(
+ 		struct pipe_ctx *pipe_ctx,
+ 		struct dc_state *context)
+ {
+-	if (pipe_ctx->top_pipe == NULL) {
++	if (pipe_ctx->top_pipe == NULL && !pipe_ctx->prev_odm_pipe) {
+ 		bool blank = !is_pipe_tree_visible(pipe_ctx);
+ 
+ 		pipe_ctx->stream_res.tg->funcs->program_global_sync(
+@@ -1312,8 +1320,8 @@ bool dcn20_update_bandwidth(
+ 
+ 			pipe_ctx->stream_res.tg->funcs->set_vtg_params(
+ 					pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+-
+-			dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
++			if (pipe_ctx->prev_odm_pipe == NULL)
++				dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
+ 		}
+ 
+ 		pipe_ctx->plane_res.hubp->funcs->hubp_setup(
+@@ -1403,12 +1411,15 @@ static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx
+ {
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	struct dce_hwseq *hws = dc->hwseq;
+-	struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
+ 
+ 	if (pipe_ctx->stream_res.dsc) {
++		struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
++
+ 		dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
+-		if (bot_odm_pipe)
+-			dcn20_dsc_pg_control(hws, bot_odm_pipe->stream_res.dsc->inst, true);
++		while (odm_pipe) {
++			dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
++			odm_pipe = odm_pipe->next_odm_pipe;
++		}
+ 	}
+ #endif
+ }
+@@ -1417,12 +1428,15 @@ static void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	struct dce_hwseq *hws = dc->hwseq;
+-	struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
+ 
+ 	if (pipe_ctx->stream_res.dsc) {
++		struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
++
+ 		dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
+-		if (bot_odm_pipe)
+-			dcn20_dsc_pg_control(hws, bot_odm_pipe->stream_res.dsc->inst, false);
++		while (odm_pipe) {
++			dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
++			odm_pipe = odm_pipe->next_odm_pipe;
++		}
+ 	}
+ #endif
+ }
+@@ -1552,18 +1566,22 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
+ 	struct encoder_unblank_param params = { { 0 } };
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	struct dc_link *link = stream->link;
+-	params.odm = dc_res_get_odm_bottom_pipe(pipe_ctx);
++	struct pipe_ctx *odm_pipe;
+ 
++	params.opp_cnt = 1;
++	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
++		params.opp_cnt++;
++	}
+ 	/* only 3 items below are used by unblank */
+ 	params.timing = pipe_ctx->stream->timing;
+ 
+ 	params.link_settings.link_rate = link_settings->link_rate;
+ 
+ 	if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
+-		if (optc1_is_two_pixels_per_containter(&stream->timing) || params.odm)
++		if (optc1_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt)
+ 			params.timing.pix_clk_100hz /= 2;
+ 		pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
+-				pipe_ctx->stream_res.stream_enc, params.odm);
++				pipe_ctx->stream_res.stream_enc, params.opp_cnt);
+ 		pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
+ 	}
+ 
+@@ -1654,7 +1672,7 @@ static void dcn20_reset_hw_ctx_wrap(
+ 		if (!pipe_ctx_old->stream)
+ 			continue;
+ 
+-		if (pipe_ctx_old->top_pipe)
++		if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
+ 			continue;
+ 
+ 		if (!pipe_ctx->stream ||
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index c59f31dcdc0d..aa1342ccf8b4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1317,7 +1317,11 @@ static void get_pixel_clock_parameters(
+ 	struct pixel_clk_params *pixel_clk_params)
+ {
+ 	const struct dc_stream_state *stream = pipe_ctx->stream;
+-	bool odm_combine = dc_res_get_odm_bottom_pipe(pipe_ctx) != NULL;
++	struct pipe_ctx *odm_pipe;
++	int opp_cnt = 1;
++
++	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
++		opp_cnt++;
+ 
+ 	pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
+ 	pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
+@@ -1335,7 +1339,9 @@ static void get_pixel_clock_parameters(
+ 	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
+ 		pixel_clk_params->color_depth = COLOR_DEPTH_888;
+ 
+-	if (optc1_is_two_pixels_per_containter(&stream->timing) || odm_combine)
++	if (opp_cnt == 4)
++		pixel_clk_params->requested_pix_clk_100hz /= 4;
++	else if (optc1_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
+ 		pixel_clk_params->requested_pix_clk_100hz /= 2;
+ 
+ 	if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
+@@ -1479,22 +1485,16 @@ static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
+ 	for (i = 0; i < MAX_PIPES; i++) {
+ 		if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
+ 			pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
+-			break;
++
++			if (pipe_ctx->stream_res.dsc)
++				release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
+ 		}
+ 	}
+ 
+ 	if (!pipe_ctx)
+ 		return DC_ERROR_UNEXPECTED;
+-
+-	if (pipe_ctx->stream_res.dsc) {
+-		struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
+-
+-		release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
+-		if (odm_pipe)
+-			release_dsc(&new_ctx->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
+-	}
+-
+-	return DC_OK;
++	else
++		return DC_OK;
+ }
+ #endif
+ 
+@@ -1593,17 +1593,94 @@ static void swizzle_to_dml_params(
+ 	}
+ }
+ 
+-static bool dcn20_split_stream_for_combine(
++static bool dcn20_split_stream_for_odm(
++		struct resource_context *res_ctx,
++		const struct resource_pool *pool,
++		struct pipe_ctx *prev_odm_pipe,
++		struct pipe_ctx *next_odm_pipe)
++{
++	int pipe_idx = next_odm_pipe->pipe_idx;
++	struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
++	struct pipe_ctx *sec_next_pipe = next_odm_pipe->next_odm_pipe;
++	int new_width;
++
++	*next_odm_pipe = *prev_odm_pipe;
++	next_odm_pipe->next_odm_pipe = sec_next_pipe;
++
++	next_odm_pipe->pipe_idx = pipe_idx;
++	next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
++	next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
++	next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
++	next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
++	next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
++	next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	next_odm_pipe->stream_res.dsc = NULL;
++#endif
++	if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
++		ASSERT(!next_odm_pipe->next_odm_pipe);
++		next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
++		next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
++	}
++	prev_odm_pipe->next_odm_pipe = next_odm_pipe;
++	next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
++	ASSERT(next_odm_pipe->top_pipe == NULL);
++
++	if (prev_odm_pipe->plane_state) {
++		/* HACTIVE halved for odm combine */
++		sd->h_active /= 2;
++		/* Copy scl_data to secondary pipe */
++		next_odm_pipe->plane_res.scl_data = *sd;
++
++		/* Calculate new vp and recout for left pipe */
++		/* Need at least 16 pixels width per side */
++		if (sd->recout.x + 16 >= sd->h_active)
++			return false;
++		new_width = sd->h_active - sd->recout.x;
++		sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
++				sd->ratios.horz, sd->recout.width - new_width));
++		sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
++				sd->ratios.horz_c, sd->recout.width - new_width));
++		sd->recout.width = new_width;
++
++		/* Calculate new vp and recout for right pipe */
++		sd = &next_odm_pipe->plane_res.scl_data;
++		new_width = sd->recout.width + sd->recout.x - sd->h_active;
++		/* Need at least 16 pixels width per side */
++		if (new_width <= 16)
++			return false;
++		sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
++				sd->ratios.horz, sd->recout.width - new_width));
++		sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
++				sd->ratios.horz_c, sd->recout.width - new_width));
++		sd->recout.width = new_width;
++		sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
++				sd->ratios.horz, sd->h_active - sd->recout.x));
++		sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
++				sd->ratios.horz_c, sd->h_active - sd->recout.x));
++		sd->recout.x = 0;
++	}
++	next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	if (next_odm_pipe->stream->timing.flags.DSC == 1) {
++		acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc);
++		ASSERT(next_odm_pipe->stream_res.dsc);
++		if (next_odm_pipe->stream_res.dsc == NULL)
++			return false;
++	}
++#endif
++
++	return true;
++}
++
++static void dcn20_split_stream_for_mpc(
+ 		struct resource_context *res_ctx,
+ 		const struct resource_pool *pool,
+ 		struct pipe_ctx *primary_pipe,
+-		struct pipe_ctx *secondary_pipe,
+-		bool is_odm_combine)
++		struct pipe_ctx *secondary_pipe)
+ {
+ 	int pipe_idx = secondary_pipe->pipe_idx;
+-	struct scaler_data *sd = &primary_pipe->plane_res.scl_data;
+ 	struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
+-	int new_width;
+ 
+ 	*secondary_pipe = *primary_pipe;
+ 	secondary_pipe->bottom_pipe = sec_bot_pipe;
+@@ -1626,57 +1703,9 @@ static bool dcn20_split_stream_for_combine(
+ 	primary_pipe->bottom_pipe = secondary_pipe;
+ 	secondary_pipe->top_pipe = primary_pipe;
+ 
+-	if (is_odm_combine) {
+-		if (primary_pipe->plane_state) {
+-			/* HACTIVE halved for odm combine */
+-			sd->h_active /= 2;
+-			/* Copy scl_data to secondary pipe */
+-			secondary_pipe->plane_res.scl_data = *sd;
+-
+-			/* Calculate new vp and recout for left pipe */
+-			/* Need at least 16 pixels width per side */
+-			if (sd->recout.x + 16 >= sd->h_active)
+-				return false;
+-			new_width = sd->h_active - sd->recout.x;
+-			sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
+-					sd->ratios.horz, sd->recout.width - new_width));
+-			sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
+-					sd->ratios.horz_c, sd->recout.width - new_width));
+-			sd->recout.width = new_width;
+-
+-			/* Calculate new vp and recout for right pipe */
+-			sd = &secondary_pipe->plane_res.scl_data;
+-			new_width = sd->recout.width + sd->recout.x - sd->h_active;
+-			/* Need at least 16 pixels width per side */
+-			if (new_width <= 16)
+-				return false;
+-			sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
+-					sd->ratios.horz, sd->recout.width - new_width));
+-			sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
+-					sd->ratios.horz_c, sd->recout.width - new_width));
+-			sd->recout.width = new_width;
+-			sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
+-					sd->ratios.horz, sd->h_active - sd->recout.x));
+-			sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
+-					sd->ratios.horz_c, sd->h_active - sd->recout.x));
+-			sd->recout.x = 0;
+-		}
+-		secondary_pipe->stream_res.opp = pool->opps[secondary_pipe->pipe_idx];
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-		if (secondary_pipe->stream->timing.flags.DSC == 1) {
+-			acquire_dsc(res_ctx, pool, &secondary_pipe->stream_res.dsc);
+-			ASSERT(secondary_pipe->stream_res.dsc);
+-			if (secondary_pipe->stream_res.dsc == NULL)
+-				return false;
+-		}
+-#endif
+-	} else {
+-		ASSERT(primary_pipe->plane_state);
+-		resource_build_scaling_params(primary_pipe);
+-		resource_build_scaling_params(secondary_pipe);
+-	}
+-
+-	return true;
++	ASSERT(primary_pipe->plane_state);
++	resource_build_scaling_params(primary_pipe);
++	resource_build_scaling_params(secondary_pipe);
+ }
+ 
+ void dcn20_populate_dml_writeback_from_context(
+@@ -2106,20 +2135,24 @@ static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
+ 		struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
+ 		struct dc_stream_state *stream = pipe_ctx->stream;
+ 		struct dsc_config dsc_cfg;
++		struct pipe_ctx *odm_pipe;
++		int opp_cnt = 1;
++
++		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
++			opp_cnt++;
+ 
+ 		/* Only need to validate top pipe */
+-		if (pipe_ctx->top_pipe || !stream || !stream->timing.flags.DSC)
++		if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
+ 			continue;
+ 
+-		dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left
+-				+ stream->timing.h_border_right;
++		dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
++				+ stream->timing.h_border_right) / opp_cnt;
+ 		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
+ 				+ stream->timing.v_border_bottom;
+-		if (dc_res_get_odm_bottom_pipe(pipe_ctx))
+-			dsc_cfg.pic_width /= 2;
+ 		dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
+ 		dsc_cfg.color_depth = stream->timing.display_color_depth;
+ 		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
++		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
+ 
+ 		if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
+ 			return false;
+@@ -2143,6 +2176,8 @@ static struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
+ 		 * if this primary pipe has a bottom pipe in prev. state
+ 		 * and if the bottom pipe is still available (which it should be),
+ 		 * pick that pipe as secondary
++		 * Same logic applies for ODM pipes. Since mpo is not allowed with odm
++		 * check in else case.
+ 		 */
+ 		if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
+ 			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
+@@ -2150,6 +2185,12 @@ static struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
+ 				secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
+ 				secondary_pipe->pipe_idx = preferred_pipe_idx;
+ 			}
++		} else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
++			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
++			if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
++				secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
++				secondary_pipe->pipe_idx = preferred_pipe_idx;
++			}
+ 		}
+ 
+ 		/*
+@@ -2220,6 +2261,38 @@ bool dcn20_fast_validate_bw(
+ 	if (!pipes)
+ 		return false;
+ 
++	/* merge previously split odm pipes since mode support needs to make the decision */
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
++		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
++		struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
++
++		if (pipe->prev_odm_pipe)
++			continue;
++
++		pipe->next_odm_pipe = NULL;
++		while (odm_pipe) {
++			struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
++
++			odm_pipe->plane_state = NULL;
++			odm_pipe->stream = NULL;
++			odm_pipe->top_pipe = NULL;
++			odm_pipe->bottom_pipe = NULL;
++			odm_pipe->prev_odm_pipe = NULL;
++			odm_pipe->next_odm_pipe = NULL;
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++			if (odm_pipe->stream_res.dsc)
++				release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
++#endif
++			/* Clear plane_res and stream_res */
++			memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
++			memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
++			odm_pipe = next_odm_pipe;
++		}
++		if (pipe->plane_state)
++			resource_build_scaling_params(pipe);
++	}
++
++	/* merge previously mpc split pipes since mode support needs to make the decision */
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ 		struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
+@@ -2227,7 +2300,6 @@ bool dcn20_fast_validate_bw(
+ 		if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
+ 			continue;
+ 
+-		/* merge previously split pipe since mode support needs to make the decision */
+ 		pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
+ 		if (hsplit_pipe->bottom_pipe)
+ 			hsplit_pipe->bottom_pipe->top_pipe = pipe;
+@@ -2235,10 +2307,7 @@ bool dcn20_fast_validate_bw(
+ 		hsplit_pipe->stream = NULL;
+ 		hsplit_pipe->top_pipe = NULL;
+ 		hsplit_pipe->bottom_pipe = NULL;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-		if (hsplit_pipe->stream_res.dsc && hsplit_pipe->stream_res.dsc != pipe->stream_res.dsc)
+-			release_dsc(&context->res_ctx, dc->res_pool, &hsplit_pipe->stream_res.dsc);
+-#endif
++
+ 		/* Clear plane_res and stream_res */
+ 		memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
+ 		memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
+@@ -2351,10 +2420,9 @@ bool dcn20_fast_validate_bw(
+ 		if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
+ 			hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
+ 			ASSERT(hsplit_pipe);
+-			if (!dcn20_split_stream_for_combine(
++			if (!dcn20_split_stream_for_odm(
+ 					&context->res_ctx, dc->res_pool,
+-					pipe, hsplit_pipe,
+-					true))
++					pipe, hsplit_pipe))
+ 				goto validate_fail;
+ 			pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
+ 			dcn20_build_mapped_resource(dc, context, pipe->stream);
+@@ -2395,11 +2463,15 @@ bool dcn20_fast_validate_bw(
+ 				if (!hsplit_pipe)
+ 					continue;
+ 
+-				if (!dcn20_split_stream_for_combine(
++				if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
++					if (!dcn20_split_stream_for_odm(
++							&context->res_ctx, dc->res_pool,
++							pipe, hsplit_pipe))
++						goto validate_fail;
++				} else
++					dcn20_split_stream_for_mpc(
+ 						&context->res_ctx, dc->res_pool,
+-						pipe, hsplit_pipe,
+-						context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]))
+-					goto validate_fail;
++						pipe, hsplit_pipe);
+ 				pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
+ 			}
+ 		} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+index a4e67286cdad..9cfc69ccdb39 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+@@ -458,7 +458,7 @@ void enc2_stream_encoder_dp_unblank(
+ 		uint64_t m_vid_l = n_vid;
+ 
+ 		/* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
+-		if (is_two_pixels_per_containter(&param->timing) || param->odm) {
++		if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt) {
+ 			/*this logic should be the same in get_pixel_clock_parameters() */
+ 			n_multiply = 1;
+ 		}
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index 74186cf1c285..bfe0d06d1c20 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -297,6 +297,8 @@ struct pipe_ctx {
+ 
+ 	struct pipe_ctx *top_pipe;
+ 	struct pipe_ctx *bottom_pipe;
++	struct pipe_ctx *next_odm_pipe;
++	struct pipe_ctx *prev_odm_pipe;
+ 
+ #ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ 	struct _vcs_dpi_display_dlg_regs_st dlg_regs;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+index 8bb3e3d56ac9..fe9b7a10a1c3 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+@@ -91,7 +91,7 @@ struct encoder_unblank_param {
+ 	struct dc_link_settings link_settings;
+ 	struct dc_crtc_timing timing;
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+-	bool odm;
++	int opp_cnt;
+ #endif
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
+index 47f81072d7e9..1cc1c8ce633b 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
+@@ -179,7 +179,4 @@ void update_audio_usage(
+ 
+ unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format);
+ 
+-struct pipe_ctx *dc_res_get_odm_bottom_pipe(struct pipe_ctx *pipe_ctx);
+-bool dc_res_is_odm_head_pipe(struct pipe_ctx *pipe_ctx);
+-
+ #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3565-drm-amd-display-Delete-dead-code-in-command_table_he.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3565-drm-amd-display-Delete-dead-code-in-command_table_he.patch
new file mode 100644
index 00000000..dffe74cd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3565-drm-amd-display-Delete-dead-code-in-command_table_he.patch
@@ -0,0 +1,169 @@
+From 36e6f7d0a6a380615c38ff582b261c243ee7326d Mon Sep 17 00:00:00 2001
+From: Julian Parkin <julian.parkin@amd.com>
+Date: Fri, 26 Jul 2019 17:13:46 -0400
+Subject: [PATCH 3565/4256] drm/amd/display: Delete dead code in
+ command_table_helper
+
+[Why]
+dig_encoder_sel_to_atom will always return zero on any ASIC version
+past DCE80 since programming of the FE selection is handled by
+driver, but the translation code was left in the function, making
+it look like a coding error.
+
+[How]
+Remove code that has no effect, and replace with a comment describing
+why it returns zero.
+
+Signed-off-by: Julian Parkin <julian.parkin@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../bios/dce110/command_table_helper_dce110.c | 36 +++----------------
+ .../dce112/command_table_helper2_dce112.c     | 36 +++----------------
+ .../bios/dce112/command_table_helper_dce112.c | 36 +++----------------
+ 3 files changed, 12 insertions(+), 96 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c b/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c
+index ca24154468c7..11bf247bb180 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c
+@@ -153,38 +153,10 @@ static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
+ 
+ static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
+ {
+-	uint8_t atom_dig_encoder_sel = 0;
+-
+-	switch (id) {
+-	case ENGINE_ID_DIGA:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
+-		break;
+-	case ENGINE_ID_DIGB:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGB_SEL;
+-		break;
+-	case ENGINE_ID_DIGC:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGC_SEL;
+-		break;
+-	case ENGINE_ID_DIGD:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGD_SEL;
+-		break;
+-	case ENGINE_ID_DIGE:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGE_SEL;
+-		break;
+-	case ENGINE_ID_DIGF:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGF_SEL;
+-		break;
+-	case ENGINE_ID_DIGG:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGG_SEL;
+-		break;
+-	case ENGINE_ID_UNKNOWN:
+-		 /* No DIG_FRONT is associated to DIG_BACKEND */
+-		atom_dig_encoder_sel = 0;
+-		break;
+-	default:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
+-		break;
+-	}
++	/* On any ASIC after DCE80, we manually program the DIG_FE
++	 * selection (see connect_dig_be_to_fe function of the link
++	 * encoder), so translation should always return 0 (no FE).
++	 */
+ 
+ 	return 0;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
+index 0237ae575068..755b6e33140a 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
+@@ -150,38 +150,10 @@ static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
+ 
+ static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
+ {
+-	uint8_t atom_dig_encoder_sel = 0;
+-
+-	switch (id) {
+-	case ENGINE_ID_DIGA:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
+-		break;
+-	case ENGINE_ID_DIGB:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGB_SEL;
+-		break;
+-	case ENGINE_ID_DIGC:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGC_SEL;
+-		break;
+-	case ENGINE_ID_DIGD:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGD_SEL;
+-		break;
+-	case ENGINE_ID_DIGE:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGE_SEL;
+-		break;
+-	case ENGINE_ID_DIGF:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGF_SEL;
+-		break;
+-	case ENGINE_ID_DIGG:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGG_SEL;
+-		break;
+-	case ENGINE_ID_UNKNOWN:
+-		/* No DIG_FRONT is associated to DIG_BACKEND */
+-		atom_dig_encoder_sel = 0;
+-		break;
+-	default:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
+-		break;
+-	}
++	/* On any ASIC after DCE80, we manually program the DIG_FE
++	 * selection (see connect_dig_be_to_fe function of the link
++	 * encoder), so translation should always return 0 (no FE).
++	 */
+ 
+ 	return 0;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
+index 452034f83e4c..06b4f7fa4a50 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
+@@ -150,38 +150,10 @@ static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
+ 
+ static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
+ {
+-	uint8_t atom_dig_encoder_sel = 0;
+-
+-	switch (id) {
+-	case ENGINE_ID_DIGA:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
+-		break;
+-	case ENGINE_ID_DIGB:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGB_SEL;
+-		break;
+-	case ENGINE_ID_DIGC:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGC_SEL;
+-		break;
+-	case ENGINE_ID_DIGD:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGD_SEL;
+-		break;
+-	case ENGINE_ID_DIGE:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGE_SEL;
+-		break;
+-	case ENGINE_ID_DIGF:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGF_SEL;
+-		break;
+-	case ENGINE_ID_DIGG:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGG_SEL;
+-		break;
+-	case ENGINE_ID_UNKNOWN:
+-		/* No DIG_FRONT is associated to DIG_BACKEND */
+-		atom_dig_encoder_sel = 0;
+-		break;
+-	default:
+-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
+-		break;
+-	}
++	/* On any ASIC after DCE80, we manually program the DIG_FE
++	 * selection (see connect_dig_be_to_fe function of the link
++	 * encoder), so translation should always return 0 (no FE).
++	 */
+ 
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3566-drm-amd-display-fix-audio-endpoint-not-getting-disab.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3566-drm-amd-display-fix-audio-endpoint-not-getting-disab.patch
new file mode 100644
index 00000000..874b5207
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3566-drm-amd-display-fix-audio-endpoint-not-getting-disab.patch
@@ -0,0 +1,337 @@
+From befdded6f23fe1dcab77243770596fa8ee85e322 Mon Sep 17 00:00:00 2001
+From: Su Sung Chung <Su.Chung@amd.com>
+Date: Thu, 25 Jul 2019 14:43:55 -0400
+Subject: [PATCH 3566/4256] drm/amd/display: fix audio endpoint not getting
+ disabled issue
+
+[Why]
+Disable_audio_stream gets enum option as a paramenter which will decide
+if we free acquired resources or not. However checks for the option is
+guarded by the other condition which check if audio stream is getting
+diabled more than once. With both conditions combined, if we attempt to
+disable audio stream twice in a row, first with keep and second with
+free as an option, we will never free any resources, which will make
+system think there is audio endpoint connected even after we plug out
+the device
+
+[How]
+Get rid of option as parameter to disable_audio_stream and move the part
+of the code that free acquired resources to outside where to keep or to
+free resources is actually determined
+
+Signed-off-by: Su Sung Chung <Su.Chung@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c      |  6 ++-
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c |  4 +-
+ .../drm/amd/display/dc/core/dc_link_hwss.c    |  4 +-
+ .../display/dc/dce110/dce110_hw_sequencer.c   | 40 +++++++++++--------
+ .../display/dc/dce110/dce110_hw_sequencer.h   |  4 +-
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 20 ++++++++--
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 24 ++++++++---
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.h    |  2 +-
+ .../gpu/drm/amd/display/dc/inc/core_types.h   |  7 +---
+ .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  5 +--
+ 10 files changed, 74 insertions(+), 42 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index bc713677faa9..f7959e122348 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1927,7 +1927,11 @@ static void commit_planes_do_stream_update(struct dc *dc,
+ 				dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
+ 
+ 				if (*stream_update->dpms_off) {
+-					core_link_disable_stream(pipe_ctx, KEEP_ACQUIRED_RESOURCE);
++					core_link_disable_stream(pipe_ctx);
++					/* for dpms, keep acquired resources*/
++					if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
++						pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
++
+ 					dc->hwss.optimize_bandwidth(dc, dc->current_state);
+ 				} else {
+ 					if (!dc->optimize_seamless_boot)
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 0ccf0cd0a44d..3dfebfd4c130 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2802,7 +2802,7 @@ void core_link_enable_stream(
+ #endif
+ }
+ 
+-void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
++void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+ {
+ 	struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+@@ -2837,7 +2837,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
+ 			write_i2c_redriver_setting(pipe_ctx, false);
+ 		}
+ 	}
+-	core_dc->hwss.disable_stream(pipe_ctx, option);
++	core_dc->hwss.disable_stream(pipe_ctx);
+ 
+ 	disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index fe9a4e4b9d1f..79438c4f1e20 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -289,7 +289,9 @@ void dp_retrain_link_dp_test(struct dc_link *link,
+ 
+ 			dp_receiver_power_ctrl(link, false);
+ 
+-			link->dc->hwss.disable_stream(&pipes[i], KEEP_ACQUIRED_RESOURCE);
++			link->dc->hwss.disable_stream(&pipes[i]);
++			if ((&pipes[i])->stream_res.audio && !link->dc->debug.az_endpoint_mute_only)
++				(&pipes[i])->stream_res.audio->funcs->az_disable((&pipes[i])->stream_res.audio);
+ 
+ 			link->link_enc->funcs->disable_output(
+ 					link->link_enc,
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 2693404cab1a..c2d026ba269f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -978,7 +978,7 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
+ 	}
+ }
+ 
+-void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
++void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
+ {
+ 	struct dc *dc;
+ 	struct pp_smu_funcs *pp_smu = NULL;
+@@ -1001,24 +1001,13 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
+ 		if (dc->res_pool->pp_smu)
+ 			pp_smu = dc->res_pool->pp_smu;
+ 
+-		if (option != KEEP_ACQUIRED_RESOURCE ||
+-				!dc->debug.az_endpoint_mute_only)
+-			/*only disalbe az_endpoint if power down or free*/
+-			pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
+-
+ 		if (dc_is_dp_signal(pipe_ctx->stream->signal))
+ 			pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
+ 					pipe_ctx->stream_res.stream_enc);
+ 		else
+ 			pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
+ 					pipe_ctx->stream_res.stream_enc);
+-		/*don't free audio if it is from retrain or internal disable stream*/
+-		if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) {
+-			/*we have to dynamic arbitrate the audio endpoints*/
+-			/*we free the resource, need reset is_audio_acquired*/
+-			update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
+-			pipe_ctx->stream_res.audio = NULL;
+-		}
++
+ 		if (clk_mgr->funcs->enable_pme_wa)
+ 			/*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
+ 			clk_mgr->funcs->enable_pme_wa(clk_mgr);
+@@ -1031,7 +1020,7 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
+ 	}
+ }
+ 
+-void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
++void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
+ {
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	struct dc_link *link = stream->link;
+@@ -1048,7 +1037,7 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
+ 		pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
+ 			pipe_ctx->stream_res.stream_enc);
+ 
+-	dc->hwss.disable_audio_stream(pipe_ctx, option);
++	dc->hwss.disable_audio_stream(pipe_ctx);
+ 
+ 	link->link_enc->funcs->connect_dig_be_to_fe(
+ 			link->link_enc,
+@@ -1911,8 +1900,25 @@ static void dce110_reset_hw_ctx_wrap(
+ 			/* Disable if new stream is null. O/w, if stream is
+ 			 * disabled already, no need to disable again.
+ 			 */
+-			if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off)
+-				core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE);
++			if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {
++				core_link_disable_stream(pipe_ctx_old);
++
++				/* free acquired resources*/
++				if (pipe_ctx_old->stream_res.audio) {
++					/*disable az_endpoint*/
++					pipe_ctx_old->stream_res.audio->funcs->
++							az_disable(pipe_ctx_old->stream_res.audio);
++
++					/*free audio*/
++					if (dc->caps.dynamic_audio == true) {
++						/*we have to dynamic arbitrate the audio endpoints*/
++						/*we free the resource, need reset is_audio_acquired*/
++						update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
++								pipe_ctx_old->stream_res.audio, false);
++						pipe_ctx_old->stream_res.audio = NULL;
++					}
++				}
++			}
+ 
+ 			pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
+ 			if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+index 668feb0d169d..2f9b7dbdf415 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+@@ -42,7 +42,7 @@ enum dc_status dce110_apply_ctx_to_hw(
+ 
+ void dce110_enable_stream(struct pipe_ctx *pipe_ctx);
+ 
+-void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option);
++void dce110_disable_stream(struct pipe_ctx *pipe_ctx);
+ 
+ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
+ 		struct dc_link_settings *link_settings);
+@@ -50,7 +50,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
+ void dce110_blank_stream(struct pipe_ctx *pipe_ctx);
+ 
+ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);
+-void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option);
++void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);
+ 
+ void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 344190be93ae..fd721edbb9f4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -827,11 +827,23 @@ static void dcn10_reset_back_end_for_pipe(
+ 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 		/* DPMS may already disable */
+ 		if (!pipe_ctx->stream->dpms_off)
+-			core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
+-		else if (pipe_ctx->stream_res.audio) {
+-			dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
++			core_link_disable_stream(pipe_ctx);
++		else if (pipe_ctx->stream_res.audio)
++			dc->hwss.disable_audio_stream(pipe_ctx);
++
++		if (pipe_ctx->stream_res.audio) {
++			/*disable az_endpoint*/
++			pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
++
++			/*free audio*/
++			if (dc->caps.dynamic_audio == true) {
++				/*we have to dynamic arbitrate the audio endpoints*/
++				/*we free the resource, need reset is_audio_acquired*/
++				update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
++						pipe_ctx->stream_res.audio, false);
++				pipe_ctx->stream_res.audio = NULL;
++			}
+ 		}
+-
+ 	}
+ 
+ 	/* by upper caller loop, parent pipe: pipe0, will be reset last.
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index c8c17fac2e24..56c4df262dc0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1461,9 +1461,9 @@ void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
+ 	hubp->funcs->dmdata_set_attributes(hubp, &attr);
+ }
+ 
+-void dcn20_disable_stream(struct pipe_ctx *pipe_ctx, int option)
++void dcn20_disable_stream(struct pipe_ctx *pipe_ctx)
+ {
+-	dce110_disable_stream(pipe_ctx, option);
++	dce110_disable_stream(pipe_ctx);
+ }
+ 
+ static void dcn20_init_vm_ctx(
+@@ -1617,9 +1617,23 @@ static void dcn20_reset_back_end_for_pipe(
+ 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 		/* DPMS may already disable */
+ 		if (!pipe_ctx->stream->dpms_off)
+-			core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
+-		else if (pipe_ctx->stream_res.audio) {
+-			dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
++			core_link_disable_stream(pipe_ctx);
++		else if (pipe_ctx->stream_res.audio)
++			dc->hwss.disable_audio_stream(pipe_ctx);
++
++		/* free acquired resources */
++		if (pipe_ctx->stream_res.audio) {
++			/*disable az_endpoint*/
++			pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
++
++			/*free audio*/
++			if (dc->caps.dynamic_audio == true) {
++				/*we have to dynamic arbitrate the audio endpoints*/
++				/*we free the resource, need reset is_audio_acquired*/
++				update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
++						pipe_ctx->stream_res.audio, false);
++				pipe_ctx->stream_res.audio = NULL;
++			}
+ 		}
+ 	}
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+index 689c2765b071..92ab3dd91814 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+@@ -75,7 +75,7 @@ bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx);
+ 
+ void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);
+ 
+-void dcn20_disable_stream(struct pipe_ctx *pipe_ctx, int option);
++void dcn20_disable_stream(struct pipe_ctx *pipe_ctx);
+ 
+ void dcn20_program_tripleBuffer(
+ 		const struct dc *dc,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index bfe0d06d1c20..df28fbc4c63c 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -63,11 +63,6 @@ struct link_init_data {
+ 				TODO: remove it when DC is complete. */
+ };
+ 
+-enum {
+-	FREE_ACQUIRED_RESOURCE = 0,
+-	KEEP_ACQUIRED_RESOURCE = 1,
+-};
+-
+ struct dc_link *link_create(const struct link_init_data *init_params);
+ void link_destroy(struct dc_link **link);
+ 
+@@ -82,7 +77,7 @@ void core_link_enable_stream(
+ 		struct dc_state *state,
+ 		struct pipe_ctx *pipe_ctx);
+ 
+-void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option);
++void core_link_disable_stream(struct pipe_ctx *pipe_ctx);
+ 
+ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
+ /********** DAL Core*********************/
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index 80de2febd7cb..68b1185f0636 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -196,8 +196,7 @@ struct hw_sequencer_funcs {
+ 
+ 	void (*enable_stream)(struct pipe_ctx *pipe_ctx);
+ 
+-	void (*disable_stream)(struct pipe_ctx *pipe_ctx,
+-			int option);
++	void (*disable_stream)(struct pipe_ctx *pipe_ctx);
+ 
+ 	void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
+ 			struct dc_link_settings *link_settings);
+@@ -206,7 +205,7 @@ struct hw_sequencer_funcs {
+ 
+ 	void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx);
+ 
+-	void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx, int option);
++	void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx);
+ 
+ 	void (*pipe_control_lock)(
+ 				struct dc *dc,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3567-drm-amd-display-fix-MPO-HUBP-underflow-with-Scatter-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3567-drm-amd-display-fix-MPO-HUBP-underflow-with-Scatter-.patch
new file mode 100644
index 00000000..c85f9d54
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3567-drm-amd-display-fix-MPO-HUBP-underflow-with-Scatter-.patch
@@ -0,0 +1,39 @@
+From 0136be1777af316f53129c830348541868b37e3f Mon Sep 17 00:00:00 2001
+From: Zi Yu Liao <ziyu.liao@amd.com>
+Date: Tue, 30 Jul 2019 15:36:53 -0400
+Subject: [PATCH 3567/4256] drm/amd/display: fix MPO HUBP underflow with
+ Scatter Gather
+
+[why]
+With Scatter Gather enabled, HUBP underflows during MPO enabled video
+playback. hubp_init has a register write that fixes this problem, but
+the register is cleared when HUBP gets power gated.
+
+[how]
+Make a call to hubp_init during enable_plane, so that the fix can
+be applied after HUBP powers back on again.
+
+Signed-off-by: Zi Yu Liao <ziyu.liao@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 56c4df262dc0..125c466ebffa 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -934,6 +934,9 @@ void dcn20_enable_plane(
+ 	/* enable DCFCLK current DCHUB */
+ 	pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
+ 
++	/* initialize HUBP on power up */
++	pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
++
+ 	/* make sure OPP_PIPE_CLOCK_EN = 1 */
+ 	pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
+ 			pipe_ctx->stream_res.opp,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3568-drm-amd-display-load-iram-for-abm-2.3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3568-drm-amd-display-load-iram-for-abm-2.3.patch
new file mode 100644
index 00000000..cbbc29ba
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3568-drm-amd-display-load-iram-for-abm-2.3.patch
@@ -0,0 +1,180 @@
+From beb0ecb435b3f954da723d81ddf4609e0399e4df Mon Sep 17 00:00:00 2001
+From: Josip Pavic <Josip.Pavic@amd.com>
+Date: Tue, 30 Jul 2019 16:56:14 -0400
+Subject: [PATCH 3568/4256] drm/amd/display: load iram for abm 2.3
+
+[Why]
+ABM 2.3 firmware expects information in iRAM that differs from previous
+versions of ABM, so a mechanism is required to provide it with that
+information.
+
+[How]
+Extend the existing iRAM definition to include parameters added by
+ABM 2.3, and load it if DMCU is running ABM 2.3.
+
+Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../amd/display/modules/power/power_helpers.c | 121 ++++++++++++++++--
+ 1 file changed, 109 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+index b3810b864676..05e2be856037 100644
+--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
++++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+@@ -66,6 +66,39 @@ static const unsigned char abm_config[abm_defines_max_config][abm_defines_max_le
+ {       3,              6,              10,             12      },	/* Alt #3  - Super aggressiveness */
+ };
+ 
++struct abm_parameters {
++	unsigned char min_reduction;
++	unsigned char max_reduction;
++	unsigned char bright_pos_gain;
++	unsigned char dark_pos_gain;
++	unsigned char brightness_gain;
++	unsigned char contrast_factor;
++	unsigned char deviation_gain;
++	unsigned char min_knee;
++	unsigned char max_knee;
++};
++
++static const struct abm_parameters abm_settings_config0[abm_defines_max_level] = {
++//  min_red  max_red  bright_pos  dark_pos  brightness_gain  contrast  deviation  min_knee  max_knee
++	{0xff,   0xbf,    0x20,       0x00,     0xff,            0x99,     0xb3,      0x40,     0xE0},
++	{0xff,   0x85,    0x20,       0x00,     0xff,            0x90,     0xa8,      0x40,     0xE0},
++	{0xff,   0x40,    0x20,       0x00,     0xff,            0x90,     0x68,      0x40,     0xE0},
++	{0x82,   0x4d,    0x20,       0x00,     0x00,            0x90,     0xb3,      0x70,     0x70},
++};
++
++static const struct abm_parameters abm_settings_config1[abm_defines_max_level] = {
++//  min_red  max_red  bright_pos  dark_pos  brightness_gain  contrast  deviation  min_knee  max_knee
++	{0xf0,   0xd9,    0x20,       0x00,     0x00,            0xa8,     0xb3,      0x70,     0x70},
++	{0xcd,   0xa5,    0x20,       0x00,     0x00,            0xa8,     0xb3,      0x70,     0x70},
++	{0x99,   0x65,    0x20,       0x00,     0x00,            0xa8,     0xb3,      0x70,     0x70},
++	{0x82,   0x4d,    0x20,       0x00,     0x00,            0xa8,     0xb3,      0x70,     0x70},
++};
++
++static const struct abm_parameters * const abm_settings[] = {
++	abm_settings_config0,
++	abm_settings_config1,
++};
++
+ #define NUM_AMBI_LEVEL    5
+ #define NUM_AGGR_LEVEL    4
+ #define NUM_POWER_FN_SEGS 8
+@@ -131,11 +164,13 @@ struct iram_table_v_2_2 {
+ 	uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];		/* 0x16 U0.8 */
+ 	uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];	/* 0x2a U2.6 */
+ 	uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];		/* 0x3e U2.6 */
+-	uint8_t hybridFactor[NUM_AGGR_LEVEL];						/* 0x52 U0.8 */
+-	uint8_t contrastFactor[NUM_AGGR_LEVEL];						/* 0x56 U0.8 */
++	uint8_t hybrid_factor[NUM_AGGR_LEVEL];						/* 0x52 U0.8 */
++	uint8_t contrast_factor[NUM_AGGR_LEVEL];					/* 0x56 U0.8 */
+ 	uint8_t deviation_gain[NUM_AGGR_LEVEL];						/* 0x5a U0.8 */
+ 	uint8_t iir_curve[NUM_AMBI_LEVEL];							/* 0x5e U0.8 */
+-	uint8_t pad[29];											/* 0x63 U0.8 */
++	uint8_t min_knee[NUM_AGGR_LEVEL];							/* 0x63 U0.8 */
++	uint8_t max_knee[NUM_AGGR_LEVEL];							/* 0x67 U0.8 */
++	uint8_t pad[21];											/* 0x6b U0.8 */
+ 
+ 	/* parameters for crgb conversion */
+ 	uint16_t crgb_thresh[NUM_POWER_FN_SEGS];					/* 0x80 U3.13 */
+@@ -501,15 +536,72 @@ void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parame
+ 	ram_table->dark_pos_gain[4][2] = 0x00;
+ 	ram_table->dark_pos_gain[4][3] = 0x00;
+ 
+-	ram_table->hybridFactor[0] = 0xff;
+-	ram_table->hybridFactor[1] = 0xff;
+-	ram_table->hybridFactor[2] = 0xff;
+-	ram_table->hybridFactor[3] = 0xc0;
++	ram_table->hybrid_factor[0] = 0xff;
++	ram_table->hybrid_factor[1] = 0xff;
++	ram_table->hybrid_factor[2] = 0xff;
++	ram_table->hybrid_factor[3] = 0xc0;
+ 
+-	ram_table->contrastFactor[0] = 0x99;
+-	ram_table->contrastFactor[1] = 0x99;
+-	ram_table->contrastFactor[2] = 0x90;
+-	ram_table->contrastFactor[3] = 0x80;
++	ram_table->contrast_factor[0] = 0x99;
++	ram_table->contrast_factor[1] = 0x99;
++	ram_table->contrast_factor[2] = 0x90;
++	ram_table->contrast_factor[3] = 0x80;
++
++	ram_table->iir_curve[0] = 0x65;
++	ram_table->iir_curve[1] = 0x65;
++	ram_table->iir_curve[2] = 0x65;
++	ram_table->iir_curve[3] = 0x65;
++	ram_table->iir_curve[4] = 0x65;
++
++	//Gamma 2.2
++	ram_table->crgb_thresh[0] = cpu_to_be16(0x127c);
++	ram_table->crgb_thresh[1] = cpu_to_be16(0x151b);
++	ram_table->crgb_thresh[2] = cpu_to_be16(0x17d5);
++	ram_table->crgb_thresh[3] = cpu_to_be16(0x1a56);
++	ram_table->crgb_thresh[4] = cpu_to_be16(0x1c83);
++	ram_table->crgb_thresh[5] = cpu_to_be16(0x1e72);
++	ram_table->crgb_thresh[6] = cpu_to_be16(0x20f0);
++	ram_table->crgb_thresh[7] = cpu_to_be16(0x232b);
++	ram_table->crgb_offset[0] = cpu_to_be16(0x2999);
++	ram_table->crgb_offset[1] = cpu_to_be16(0x3999);
++	ram_table->crgb_offset[2] = cpu_to_be16(0x4666);
++	ram_table->crgb_offset[3] = cpu_to_be16(0x5999);
++	ram_table->crgb_offset[4] = cpu_to_be16(0x6333);
++	ram_table->crgb_offset[5] = cpu_to_be16(0x7800);
++	ram_table->crgb_offset[6] = cpu_to_be16(0x8c00);
++	ram_table->crgb_offset[7] = cpu_to_be16(0xa000);
++	ram_table->crgb_slope[0]  = cpu_to_be16(0x3609);
++	ram_table->crgb_slope[1]  = cpu_to_be16(0x2dfa);
++	ram_table->crgb_slope[2]  = cpu_to_be16(0x27ea);
++	ram_table->crgb_slope[3]  = cpu_to_be16(0x235d);
++	ram_table->crgb_slope[4]  = cpu_to_be16(0x2042);
++	ram_table->crgb_slope[5]  = cpu_to_be16(0x1dc3);
++	ram_table->crgb_slope[6]  = cpu_to_be16(0x1b1a);
++	ram_table->crgb_slope[7]  = cpu_to_be16(0x1910);
++
++	fill_backlight_transform_table_v_2_2(
++			params, ram_table);
++}
++
++void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params)
++{
++	unsigned int i, j;
++	unsigned int set = params.set;
++
++	ram_table->flags = 0x0;
++	for (i = 0; i < NUM_AGGR_LEVEL; i++) {
++		ram_table->hybrid_factor[i] = abm_settings[set][i].brightness_gain;
++		ram_table->contrast_factor[i] = abm_settings[set][i].contrast_factor;
++		ram_table->deviation_gain[i] = abm_settings[set][i].deviation_gain;
++		ram_table->min_knee[i] = abm_settings[set][i].min_knee;
++		ram_table->max_knee[i] = abm_settings[set][i].max_knee;
++
++		for (j = 0; j < NUM_AMBI_LEVEL; j++) {
++			ram_table->min_reduction[j][i] = abm_settings[set][i].min_reduction;
++			ram_table->max_reduction[j][i] = abm_settings[set][i].max_reduction;
++			ram_table->bright_pos_gain[j][i] = abm_settings[set][i].bright_pos_gain;
++			ram_table->dark_pos_gain[j][i] = abm_settings[set][i].dark_pos_gain;
++		}
++	}
+ 
+ 	ram_table->iir_curve[0] = 0x65;
+ 	ram_table->iir_curve[1] = 0x65;
+@@ -561,7 +653,12 @@ bool dmcu_load_iram(struct dmcu *dmcu,
+ 
+ 	memset(&ram_table, 0, sizeof(ram_table));
+ 
+-	if (dmcu->dmcu_version.abm_version == 0x22) {
++	if (dmcu->dmcu_version.abm_version == 0x23) {
++		fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params);
++
++		result = dmcu->funcs->load_iram(
++				dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
++	} else if (dmcu->dmcu_version.abm_version == 0x22) {
+ 		fill_iram_v_2_2((struct iram_table_v_2_2 *)ram_table, params);
+ 
+ 		result = dmcu->funcs->load_iram(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3569-drm-amd-display-fix-dp-stream-enable.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3569-drm-amd-display-fix-dp-stream-enable.patch
new file mode 100644
index 00000000..064c5bc1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3569-drm-amd-display-fix-dp-stream-enable.patch
@@ -0,0 +1,52 @@
+From bf45b96d8d332f785f6458adb98ee68afaffc323 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 31 Jul 2019 14:08:45 -0400
+Subject: [PATCH 3569/4256] drm/amd/display: fix dp stream enable
+
+A previous odm change broke stream enable by always setting
+n_multiply as if odm was on.
+
+This fixes the check for odm by making sure opp count is >1
+rather than not 0.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c          | 4 ++--
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 2 +-
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 125c466ebffa..3bc75176bf2d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1581,10 +1581,10 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
+ 	params.link_settings.link_rate = link_settings->link_rate;
+ 
+ 	if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
+-		if (optc1_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt)
++		if (optc1_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
+ 			params.timing.pix_clk_100hz /= 2;
+ 		pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
+-				pipe_ctx->stream_res.stream_enc, params.opp_cnt);
++				pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
+ 		pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+index 9cfc69ccdb39..b7d977b4b0d5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+@@ -458,7 +458,7 @@ void enc2_stream_encoder_dp_unblank(
+ 		uint64_t m_vid_l = n_vid;
+ 
+ 		/* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
+-		if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt) {
++		if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1) {
+ 			/*this logic should be the same in get_pixel_clock_parameters() */
+ 			n_multiply = 1;
+ 		}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3570-drm-amd-display-set-Hratio-and-VRatio-in-dml.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3570-drm-amd-display-set-Hratio-and-VRatio-in-dml.patch
new file mode 100644
index 00000000..abe7a8f9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3570-drm-amd-display-set-Hratio-and-VRatio-in-dml.patch
@@ -0,0 +1,32 @@
+From 2635065f8ecb1eefa46b3a0734d2e54975928935 Mon Sep 17 00:00:00 2001
+From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Date: Tue, 30 Jul 2019 18:30:40 -0400
+Subject: [PATCH 3570/4256] drm/amd/display: set Hratio and VRatio in dml
+
+Set the writeback Hratio and Vratio in dml.
+
+Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+index bd634dce6f3a..65cf4edddaff 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+@@ -466,6 +466,10 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
+ 				dout->wb.wb_dst_width;
+ 		mode_lib->vba.WritebackDestinationHeight[mode_lib->vba.NumberOfActivePlanes] =
+ 				dout->wb.wb_dst_height;
++		mode_lib->vba.WritebackHRatio[mode_lib->vba.NumberOfActivePlanes] =
++				dout->wb.wb_hratio;
++		mode_lib->vba.WritebackVRatio[mode_lib->vba.NumberOfActivePlanes] =
++				dout->wb.wb_vratio;
+ 		mode_lib->vba.WritebackPixelFormat[mode_lib->vba.NumberOfActivePlanes] =
+ 				(enum source_format_class) (dout->wb.wb_pixel_format);
+ 		mode_lib->vba.WritebackHTaps[mode_lib->vba.NumberOfActivePlanes] =
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3571-drm-amd-display-add-null-checks-before-logging.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3571-drm-amd-display-add-null-checks-before-logging.patch
new file mode 100644
index 00000000..b2b2d217
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3571-drm-amd-display-add-null-checks-before-logging.patch
@@ -0,0 +1,39 @@
+From 2e7df5bb8785aec4c5291cf5321d2217376b01cf Mon Sep 17 00:00:00 2001
+From: Wyatt Wood <wyatt.wood@amd.com>
+Date: Wed, 31 Jul 2019 15:52:46 -0400
+Subject: [PATCH 3571/4256] drm/amd/display: add null checks before logging
+
+Adding NULL checks to various parameters in log_tf, to avoid
+nullptr errors
+
+Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Acked-by: Nikola Cornij <Nikola.Cornij@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c    | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index fd721edbb9f4..b1cd13c6911c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1501,9 +1501,12 @@ dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
+ 	} else
+ 		dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
+ 
+-	log_tf(stream->ctx,
+-			stream->out_transfer_func,
+-			dpp->regamma_params.hw_points_num);
++	if (stream != NULL && stream->ctx != NULL &&
++			stream->out_transfer_func != NULL) {
++		log_tf(stream->ctx,
++				stream->out_transfer_func,
++				dpp->regamma_params.hw_points_num);
++	}
+ 
+ 	return true;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3572-drm-amd-display-Implement-voltage-limitation-stub.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3572-drm-amd-display-Implement-voltage-limitation-stub.patch
new file mode 100644
index 00000000..448d3e49
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3572-drm-amd-display-Implement-voltage-limitation-stub.patch
@@ -0,0 +1,57 @@
+From 118861171fb634dca6ceb8637e19a92699a7e95a Mon Sep 17 00:00:00 2001
+From: Joseph Gravenor <joseph.gravenor@amd.com>
+Date: Tue, 30 Jul 2019 16:37:35 -0400
+Subject: [PATCH 3572/4256] drm/amd/display: Implement voltage limitation stub
+
+add new function to get the voltage at the end of
+dcn_validate_bandwidth, to check against the
+highest voltage we allow.
+
+Created a stub to allow for optimizations
+
+Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Acked-by: Sun peng Li <Sunpeng.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+index 061c6e3a3088..383f4f8db8f4 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+@@ -705,6 +705,13 @@ static void hack_bounding_box(struct dcn_bw_internal_vars *v,
+ 		hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
+ }
+ 
++
++unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev)
++{
++	/* we are ok with all levels */
++	return 4;
++}
++
+ bool dcn_validate_bandwidth(
+ 		struct dc *dc,
+ 		struct dc_state *context,
+@@ -732,6 +739,7 @@ bool dcn_validate_bandwidth(
+ 
+ 	memset(v, 0, sizeof(*v));
+ 	kernel_fpu_begin();
++
+ 	v->sr_exit_time = dc->dcn_soc->sr_exit_time;
+ 	v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
+ 	v->urgent_latency = dc->dcn_soc->urgent_latency;
+@@ -1268,7 +1276,7 @@ bool dcn_validate_bandwidth(
+ 	PERFORMANCE_TRACE_END();
+ 	BW_VAL_TRACE_FINISH();
+ 
+-	if (bw_limit_pass && v->voltage_level != 5)
++	if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->ctx->asic_id.hw_internal_rev))
+ 		return true;
+ 	else
+ 		return false;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3573-drm-amd-display-Zero-out-dsc-init-regs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3573-drm-amd-display-Zero-out-dsc-init-regs.patch
new file mode 100644
index 00000000..cfc419bd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3573-drm-amd-display-Zero-out-dsc-init-regs.patch
@@ -0,0 +1,46 @@
+From aae213cf382fa9a3cf10f708ac18d6cb08f5f50d Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Thu, 1 Aug 2019 15:52:58 -0400
+Subject: [PATCH 3573/4256] drm/amd/display: Zero-out dsc init regs
+
+[why]
+Before a statically allocated PPS data structure, that did
+get zeroed-out at startup, had been re-used for making packed PPS
+SDP. With S3 fix, using a non-initialized PPS data structure was
+introduced, while wrongly assuming it'd get initialized before it's
+populated. As a consequence 'vbr_enable' and perhaps some other
+fields are left uninitialized when making packed PPS SDP. This can
+affect 'simple_422' as well because of the way PPS SDP packing is
+done (the fields are not masked first, only shifted). The behavior
+will be different, depending on the content of uninitialized data.
+
+[how]
+Zero-out PPS data structure at initialization time before it's
+populated
+
+Fixes:  3b87378c604e929015385e5cc76d0bbd55c05347
+	drm/amd/display: Set DSC before DIG front-end is connected to its back-end
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+index 379c9e4ac63b..c4f861e6bd53 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+@@ -447,6 +447,8 @@ static void dsc_init_reg_values(struct dsc_reg_values *reg_vals)
+ {
+ 	int i;
+ 
++	memset(reg_vals, 0, sizeof(struct dsc_reg_values));
++
+ 	/* Non-PPS values */
+ 	reg_vals->dsc_clock_enable            = 1;
+ 	reg_vals->dsc_clock_gating_disable    = 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3574-drm-amd-display-refactor-Device-ID-for-external-chip.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3574-drm-amd-display-refactor-Device-ID-for-external-chip.patch
new file mode 100644
index 00000000..571064d9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3574-drm-amd-display-refactor-Device-ID-for-external-chip.patch
@@ -0,0 +1,105 @@
+From 8b1d1ae016a9d4ecde8b859fab967a4233e9d694 Mon Sep 17 00:00:00 2001
+From: Qingqing Zhuo <qingqing.zhuo@amd.com>
+Date: Wed, 31 Jul 2019 18:11:16 -0400
+Subject: [PATCH 3574/4256] drm/amd/display: refactor Device ID for external
+ chips
+
+IEEE OUI will now be used while referring to certain vendors.
+instead of normal index
+
+Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |  2 +-
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 21 ++++++++++++++-----
+ .../amd/display/include/ddc_service_types.h   | 10 +++++----
+ 3 files changed, 23 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+index 94064d8ce303..7fd2d1358f1b 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+@@ -292,7 +292,7 @@ static uint32_t defer_delay_converter_wa(
+ {
+ 	struct dc_link *link = ddc->link;
+ 
+-	if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_4 &&
++	if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
+ 		!memcmp(link->dpcd_caps.branch_dev_name,
+ 			DP_DVI_CONVERTER_ID_4,
+ 			sizeof(link->dpcd_caps.branch_dev_name)))
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 2aa44b28b673..40067403b043 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2684,13 +2684,13 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
+ 
+ 	if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
+ 		switch (link->dpcd_caps.branch_dev_id) {
+-		/* Some active dongles (DP-VGA, DP-DLDVI converters) power down
++		/* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
+ 		 * all internal circuits including AUX communication preventing
+ 		 * reading DPCD table and EDID (spec violation).
+ 		 * Encoder will skip DP RX power down on disable_output to
+ 		 * keep receiver powered all the time.*/
+-		case DP_BRANCH_DEVICE_ID_1:
+-		case DP_BRANCH_DEVICE_ID_4:
++		case DP_BRANCH_DEVICE_ID_0010FA:
++		case DP_BRANCH_DEVICE_ID_0080E1:
+ 			link->wa_flags.dp_keep_receiver_powered = true;
+ 			break;
+ 
+@@ -3394,7 +3394,13 @@ enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
+ 	if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
+ 
+ 		switch (link->dpcd_caps.branch_dev_id) {
+-		case DP_BRANCH_DEVICE_ID_2:
++		case DP_BRANCH_DEVICE_ID_0022B9:
++			/* alternate scrambler reset is required for Travis
++			 * for the case when external chip does not
++			 * provide sink device id, alternate scrambler
++			 * scheme will  be overriden later by querying
++			 * Encoder features
++			 */
+ 			if (strncmp(
+ 				link->dpcd_caps.branch_dev_name,
+ 				DP_VGA_LVDS_CONVERTER_ID_2,
+@@ -3404,7 +3410,12 @@ enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
+ 					return DP_PANEL_MODE_SPECIAL;
+ 			}
+ 			break;
+-		case DP_BRANCH_DEVICE_ID_3:
++		case DP_BRANCH_DEVICE_ID_00001A:
++			/* alternate scrambler reset is required for Travis
++			 * for the case when external chip does not provide
++			 * sink device id, alternate scrambler scheme will
++			 * be overriden later by querying Encoder feature
++			 */
+ 			if (strncmp(link->dpcd_caps.branch_dev_name,
+ 				DP_VGA_LVDS_CONVERTER_ID_3,
+ 				sizeof(
+diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+index d968956a10cd..18961707db23 100644
+--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
++++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+@@ -25,10 +25,12 @@
+ #ifndef __DAL_DDC_SERVICE_TYPES_H__
+ #define __DAL_DDC_SERVICE_TYPES_H__
+ 
+-#define DP_BRANCH_DEVICE_ID_1 0x0010FA
+-#define DP_BRANCH_DEVICE_ID_2 0x0022B9
+-#define DP_BRANCH_DEVICE_ID_3 0x00001A
+-#define DP_BRANCH_DEVICE_ID_4 0x0080e1
++/* 0010FA dongles (ST Micro) external converter chip id */
++#define DP_BRANCH_DEVICE_ID_0010FA 0x0010FA
++/* 0022B9 external converter chip id */
++#define DP_BRANCH_DEVICE_ID_0022B9 0x0022B9
++#define DP_BRANCH_DEVICE_ID_00001A 0x00001A
++#define DP_BRANCH_DEVICE_ID_0080E1 0x0080e1
+ 
+ enum ddc_result {
+ 	DDC_RESULT_UNKNOWN = 0,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3575-drm-amd-display-Add-VM-page-fault-handle-implementat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3575-drm-amd-display-Add-VM-page-fault-handle-implementat.patch
new file mode 100644
index 00000000..431dcf22
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3575-drm-amd-display-Add-VM-page-fault-handle-implementat.patch
@@ -0,0 +1,128 @@
+From cfcafa39153dc47ec051920fb9940f1097418c86 Mon Sep 17 00:00:00 2001
+From: Jaehyun Chung <jaehyun.chung@amd.com>
+Date: Mon, 29 Jul 2019 14:48:32 -0400
+Subject: [PATCH 3575/4256] drm/amd/display: Add VM page fault handle
+ implementation
+
+[How] Allocate memory for default page and program memory block addr
+into default page addr register.
+
+Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h                 | 1 +
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h | 6 +++++-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 5 +++++
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h | 9 +++++++--
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c  | 1 +
+ drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h    | 2 ++
+ 6 files changed, 21 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 81b986acbae6..f95fb13f14de 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -426,6 +426,7 @@ struct dc_phy_addr_space_config {
+ 	} gart_config;
+ 
+ 	bool valid;
++	uint64_t page_table_default_page_addr;
+ };
+ 
+ struct dc_virtual_addr_space_config {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+index 70e5d84fc69a..c8ae3023fda2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+@@ -119,6 +119,8 @@ struct dcn_hubbub_registers {
+ 	uint32_t DCN_VM_AGP_BOT;
+ 	uint32_t DCN_VM_AGP_TOP;
+ 	uint32_t DCN_VM_AGP_BASE;
++	uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
++	uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
+ };
+ 
+ /* set field name */
+@@ -196,7 +198,9 @@ struct dcn_hubbub_registers {
+ 		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\
+ 		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\
+ 		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\
+-		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D
++		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\
++		type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
++		type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB
+ 
+ #define HUBBUB_STUTTER_REG_FIELD_LIST(type) \
+ 		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+index f13e039f8ef4..b83c022e2c6f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+@@ -380,6 +380,11 @@ int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub,
+ 	REG_SET(DCN_VM_AGP_BASE, 0,
+ 			AGP_BASE, pa_config->system_aperture.agp_base >> 24);
+ 
++	REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
++			DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, (pa_config->page_table_default_page_addr >> 44) & 0xF);
++	REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
++			DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, (pa_config->page_table_default_page_addr >> 12) & 0xFFFFFFFF);
++
+ 	if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
+ 		phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
+ 		phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
+index caf7273ca240..0d0caa6de935 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
+@@ -45,7 +45,10 @@
+ #define HUBBUB_REG_LIST_DCN20(id)\
+ 	HUBBUB_REG_LIST_DCN20_COMMON(), \
+ 	HUBBUB_SR_WATERMARK_REG_LIST(), \
+-	HUBBUB_VM_REG_LIST()
++	HUBBUB_VM_REG_LIST(),\
++	SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB),\
++	SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB)
++
+ 
+ #define HUBBUB_MASK_SH_LIST_DCN20(mask_sh)\
+ 	HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
+@@ -56,7 +59,9 @@
+ 	HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
+ 	HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
+ 	HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
+-	HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh)
++	HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \
++	HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh), \
++	HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh)
+ 
+ struct dcn20_hubbub {
+ 	struct hubbub base;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 3bc75176bf2d..18de1aeaa51f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1504,6 +1504,7 @@ static int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_ph
+ 	config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
+ 	config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
+ 	config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
++	config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
+ 
+ 	return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+index c1f29b1654d9..a6297219d7fc 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+@@ -80,6 +80,8 @@ struct dcn_hubbub_phys_addr_config {
+ 		uint64_t page_table_end_addr;
+ 		uint64_t page_table_base_addr;
+ 	} gart_config;
++
++	uint64_t page_table_default_page_addr;
+ };
+ 
+ struct dcn_hubbub_virt_addr_config {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3576-drm-amd-display-cleaned-up-coding-error-in-init_hw.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3576-drm-amd-display-cleaned-up-coding-error-in-init_hw.patch
new file mode 100644
index 00000000..9a1e7a11
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3576-drm-amd-display-cleaned-up-coding-error-in-init_hw.patch
@@ -0,0 +1,48 @@
+From b8a97ac3fb929f77ef808d311da876df2bbdb7d1 Mon Sep 17 00:00:00 2001
+From: Martin Leung <martin.leung@amd.com>
+Date: Fri, 2 Aug 2019 11:01:05 -0400
+Subject: [PATCH 3576/4256] drm/amd/display: cleaned up coding error in init_hw
+
+[why]
+during a refactor a redundant code that has unknown behaviour was added.
+
+[how]
+removed old bad code
+
+Fixes:  7b0b6ee982ab018ecce70f661e676d059bfe8270
+	drm/amd/display: Make init_hw and init_pipes generic for seamless boot
+
+Signed-off-by: Martin Leung <martin.leung@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 11 -----------
+ 1 file changed, 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index b1cd13c6911c..0cbd344ca447 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1267,19 +1267,8 @@ static void dcn10_init_hw(struct dc *dc)
+ 	 */
+ 	if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
+ 		dc->hwss.init_pipes(dc, dc->current_state);
+-		for (i = 0; i < res_pool->pipe_count; i++) {
+-			struct hubp *hubp = res_pool->hubps[i];
+-			struct dpp *dpp = res_pool->dpps[i];
+-
+-			hubp->funcs->hubp_init(hubp);
+-			res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
+-			dc->hwss.plane_atomic_power_down(dc, dpp, hubp);
+-		}
+-
+-		apply_DEGVIDCN10_253_wa(dc);
+ 	}
+ 
+-
+ 	for (i = 0; i < res_pool->audio_count; i++) {
+ 		struct audio *audio = res_pool->audios[i];
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3577-drm-amd-display-remove-unused-function.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3577-drm-amd-display-remove-unused-function.patch
new file mode 100644
index 00000000..e6ec0dfa
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3577-drm-amd-display-remove-unused-function.patch
@@ -0,0 +1,51 @@
+From fc1814a2f43a3e8075b4dfe84e9530122e40feb8 Mon Sep 17 00:00:00 2001
+From: Qingqing Zhuo <qingqing.zhuo@amd.com>
+Date: Fri, 2 Aug 2019 14:10:33 -0400
+Subject: [PATCH 3577/4256] drm/amd/display: remove unused function
+
+[Why]
+This function is not being used, it was left in
+when introducing DCN2
+
+[How]
+Remove the function
+
+Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
+Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c | 1 -
+ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h      | 5 -----
+ 2 files changed, 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
+index d9e7c711a71c..40164ed015ea 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
+@@ -332,7 +332,6 @@ static struct opp_funcs dcn20_opp_funcs = {
+ 		.opp_set_disp_pattern_generator = opp2_set_disp_pattern_generator,
+ 		.dpg_is_blanked = opp2_dpg_is_blanked,
+ 		.opp_dpg_set_blank_color = opp2_dpg_set_blank_color,
+-		.opp_convert_pti = NULL,
+ 		.opp_destroy = opp1_destroy,
+ 		.opp_program_left_edge_extra_pixel = opp2_program_left_edge_extra_pixel,
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+index 5d8a7bcccc6f..957e9047381a 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+@@ -316,11 +316,6 @@ struct opp_funcs {
+ 	bool (*dpg_is_blanked)(
+ 			struct output_pixel_processor *opp);
+ 
+-	void (*opp_convert_pti)(
+-		struct output_pixel_processor *opp,
+-		bool enable,
+-		bool polarity);
+-
+ 	void (*opp_dpg_set_blank_color)(
+ 			struct output_pixel_processor *opp,
+ 			const struct tg_color *color);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3578-drm-amd-display-3.2.47.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3578-drm-amd-display-3.2.47.patch
new file mode 100644
index 00000000..96bf9140
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3578-drm-amd-display-3.2.47.patch
@@ -0,0 +1,28 @@
+From 27611f323fc5c5442fc7a5e1d4946f1b2003a050 Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Tue, 6 Aug 2019 00:48:04 -0400
+Subject: [PATCH 3578/4256] drm/amd/display: 3.2.47
+
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index f95fb13f14de..49bc1e9b3362 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -42,7 +42,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.46"
++#define DC_VER "3.2.47"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3579-drm-amd-display-Refactoring-VTEM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3579-drm-amd-display-Refactoring-VTEM.patch
new file mode 100644
index 00000000..b52c7626
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3579-drm-amd-display-Refactoring-VTEM.patch
@@ -0,0 +1,487 @@
+From 96f668dd02414abc609f16d010d768ce2351198f Mon Sep 17 00:00:00 2001
+From: Ahmad Othman <ahmad.othman@amd.com>
+Date: Thu, 1 Aug 2019 15:05:27 -0400
+Subject: [PATCH 3579/4256] drm/amd/display: Refactoring VTEM
+
+[Why]
+Video Timing Extended Metadata packet (VTEM) is not
+specific to freesync. So move it out of freesync module
+
+[How]
+- Moved VTEM from freesync module to info_packet module
+- Created new structure for VTEM parameters that can be used for VRR
+and FVA
+
+Signed-off-by: Ahmad Othman <ahmad.othman@amd.com>
+Reviewed-by: Chris Park <Chris.Park@amd.com>
+Acked-by: Ahmad Othman <Ahmad.Othman@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../amd/display/modules/freesync/freesync.c   | 276 ++++--------------
+ .../amd/display/modules/inc/mod_freesync.h    |   2 +
+ .../amd/display/modules/inc/mod_info_packet.h |   2 +-
+ .../display/modules/info_packet/info_packet.c |  88 ++++++
+ 4 files changed, 148 insertions(+), 220 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+index 000a9db9dad8..107d81ea689b 100644
+--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
++++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+@@ -50,93 +50,6 @@ struct core_freesync {
+ 	struct dc *dc;
+ };
+ 
+-void setFieldWithMask(unsigned char *dest, unsigned int mask, unsigned int value)
+-{
+-	unsigned int shift = 0;
+-
+-	if (!mask || !dest)
+-		return;
+-
+-	while (!((mask >> shift) & 1))
+-		shift++;
+-
+-	//reset
+-	*dest = *dest & ~mask;
+-	//set
+-	//dont let value span past mask
+-	value = value & (mask >> shift);
+-	//insert value
+-	*dest = *dest | (value << shift);
+-}
+-
+-// VTEM Byte Offset
+-#define VRR_VTEM_PB0		0
+-#define VRR_VTEM_PB1		1
+-#define VRR_VTEM_PB2		2
+-#define VRR_VTEM_PB3		3
+-#define VRR_VTEM_PB4		4
+-#define VRR_VTEM_PB5		5
+-#define VRR_VTEM_PB6		6
+-
+-#define VRR_VTEM_MD0		7
+-#define VRR_VTEM_MD1		8
+-#define VRR_VTEM_MD2		9
+-#define VRR_VTEM_MD3		10
+-
+-
+-// VTEM Byte Masks
+-//PB0
+-#define MASK__VRR_VTEM_PB0__RESERVED0  0x01
+-#define MASK__VRR_VTEM_PB0__SYNC       0x02
+-#define MASK__VRR_VTEM_PB0__VFR        0x04
+-#define MASK__VRR_VTEM_PB0__AFR        0x08
+-#define MASK__VRR_VTEM_PB0__DS_TYPE    0x30
+-	//0: Periodic pseudo-static EM Data Set
+-	//1: Periodic dynamic EM Data Set
+-	//2: Unique EM Data Set
+-	//3: Reserved
+-#define MASK__VRR_VTEM_PB0__END        0x40
+-#define MASK__VRR_VTEM_PB0__NEW        0x80
+-
+-//PB1
+-#define MASK__VRR_VTEM_PB1__RESERVED1 0xFF
+-
+-//PB2
+-#define MASK__VRR_VTEM_PB2__ORGANIZATION_ID 0xFF
+-	//0: This is a Vendor Specific EM Data Set
+-	//1: This EM Data Set is defined by This Specification (HDMI 2.1 r102.clean)
+-	//2: This EM Data Set is defined by CTA-861-G
+-	//3: This EM Data Set is defined by VESA
+-//PB3
+-#define MASK__VRR_VTEM_PB3__DATA_SET_TAG_MSB    0xFF
+-//PB4
+-#define MASK__VRR_VTEM_PB4__DATA_SET_TAG_LSB    0xFF
+-//PB5
+-#define MASK__VRR_VTEM_PB5__DATA_SET_LENGTH_MSB 0xFF
+-//PB6
+-#define MASK__VRR_VTEM_PB6__DATA_SET_LENGTH_LSB 0xFF
+-
+-
+-
+-//PB7-27 (20 bytes):
+-//PB7 = MD0
+-#define MASK__VRR_VTEM_MD0__VRR_EN         0x01
+-#define MASK__VRR_VTEM_MD0__M_CONST        0x02
+-#define MASK__VRR_VTEM_MD0__RESERVED2      0x0C
+-#define MASK__VRR_VTEM_MD0__FVA_FACTOR_M1  0xF0
+-
+-//MD1
+-#define MASK__VRR_VTEM_MD1__BASE_VFRONT    0xFF
+-
+-//MD2
+-#define MASK__VRR_VTEM_MD2__BASE_REFRESH_RATE_98  0x03
+-#define MASK__VRR_VTEM_MD2__RB                    0x04
+-#define MASK__VRR_VTEM_MD2__RESERVED3             0xF8
+-
+-//MD3
+-#define MASK__VRR_VTEM_MD3__BASE_REFRESH_RATE_07  0xFF
+-
+-
+ #define MOD_FREESYNC_TO_CORE(mod_freesync)\
+ 		container_of(mod_freesync, struct core_freesync, public)
+ 
+@@ -572,22 +485,64 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
+ 	return false;
+ }
+ 
+-static void build_vrr_infopacket_header_vtem(enum signal_type signal,
++static void build_vrr_infopacket_data(const struct mod_vrr_params *vrr,
+ 		struct dc_info_packet *infopacket)
+ {
+-	// HEADER
+-
+-	// HB0, HB1, HB2 indicates PacketType VTEMPacket
+-	infopacket->hb0 = 0x7F;
+-	infopacket->hb1 = 0xC0;
+-	infopacket->hb2 = 0x00; //sequence_index
+-
+-	setFieldWithMask(&infopacket->sb[VRR_VTEM_PB0], MASK__VRR_VTEM_PB0__VFR, 1);
+-	setFieldWithMask(&infopacket->sb[VRR_VTEM_PB2], MASK__VRR_VTEM_PB2__ORGANIZATION_ID, 1);
+-	setFieldWithMask(&infopacket->sb[VRR_VTEM_PB3], MASK__VRR_VTEM_PB3__DATA_SET_TAG_MSB, 0);
+-	setFieldWithMask(&infopacket->sb[VRR_VTEM_PB4], MASK__VRR_VTEM_PB4__DATA_SET_TAG_LSB, 1);
+-	setFieldWithMask(&infopacket->sb[VRR_VTEM_PB5], MASK__VRR_VTEM_PB5__DATA_SET_LENGTH_MSB, 0);
+-	setFieldWithMask(&infopacket->sb[VRR_VTEM_PB6], MASK__VRR_VTEM_PB6__DATA_SET_LENGTH_LSB, 4);
++	/* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
++	infopacket->sb[1] = 0x1A;
++
++	/* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
++	infopacket->sb[2] = 0x00;
++
++	/* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
++	infopacket->sb[3] = 0x00;
++
++	/* PB4 = Reserved */
++
++	/* PB5 = Reserved */
++
++	/* PB6 = [Bits 7:3 = Reserved] */
++
++	/* PB6 = [Bit 0 = FreeSync Supported] */
++	if (vrr->state != VRR_STATE_UNSUPPORTED)
++		infopacket->sb[6] |= 0x01;
++
++	/* PB6 = [Bit 1 = FreeSync Enabled] */
++	if (vrr->state != VRR_STATE_DISABLED &&
++			vrr->state != VRR_STATE_UNSUPPORTED)
++		infopacket->sb[6] |= 0x02;
++
++	/* PB6 = [Bit 2 = FreeSync Active] */
++	if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
++			vrr->state == VRR_STATE_ACTIVE_FIXED)
++		infopacket->sb[6] |= 0x04;
++
++	/* PB7 = FreeSync Minimum refresh rate (Hz) */
++	infopacket->sb[7] = (unsigned char)(vrr->min_refresh_in_uhz / 1000000);
++
++	/* PB8 = FreeSync Maximum refresh rate (Hz)
++	 * Note: We should never go above the field rate of the mode timing set.
++	 */
++	infopacket->sb[8] = (unsigned char)(vrr->max_refresh_in_uhz / 1000000);
++
++
++	//FreeSync HDR
++	infopacket->sb[9] = 0;
++	infopacket->sb[10] = 0;
++}
++
++static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,
++		struct dc_info_packet *infopacket)
++{
++	if (app_tf != TRANSFER_FUNC_UNKNOWN) {
++		infopacket->valid = true;
++
++		infopacket->sb[6] |= 0x08;  // PB6 = [Bit 3 = Native Color Active]
++
++		if (app_tf == TRANSFER_FUNC_GAMMA_22) {
++			infopacket->sb[9] |= 0x04;  // PB6 = [Bit 2 = Gamma 2.2 EOTF Active]
++		}
++	}
+ }
+ 
+ static void build_vrr_infopacket_header_v1(enum signal_type signal,
+@@ -688,105 +643,6 @@ static void build_vrr_infopacket_header_v2(enum signal_type signal,
+ 	}
+ }
+ 
+-static void build_vrr_vtem_infopacket_data(const struct dc_stream_state *stream,
+-		const struct mod_vrr_params *vrr,
+-		struct dc_info_packet *infopacket)
+-{
+-	unsigned int fieldRateInHz;
+-
+-	if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
+-				vrr->state == VRR_STATE_ACTIVE_FIXED) {
+-		setFieldWithMask(&infopacket->sb[VRR_VTEM_MD0], MASK__VRR_VTEM_MD0__VRR_EN, 1);
+-	} else {
+-		setFieldWithMask(&infopacket->sb[VRR_VTEM_MD0], MASK__VRR_VTEM_MD0__VRR_EN, 0);
+-	}
+-
+-	if (!stream->timing.vic) {
+-		setFieldWithMask(&infopacket->sb[VRR_VTEM_MD1], MASK__VRR_VTEM_MD1__BASE_VFRONT,
+-				stream->timing.v_front_porch);
+-
+-
+-		/* TODO: In dal2, we check mode flags for a reduced blanking timing.
+-		 * Need a way to relay that information to this function.
+-		 * if("ReducedBlanking")
+-		 * {
+-		 *   setFieldWithMask(&infopacket->sb[VRR_VTEM_MD2], MASK__VRR_VTEM_MD2__RB, 1;
+-		 * }
+-		 */
+-
+-		//TODO: DAL2 does FixPoint and rounding. Here we might need to account for that
+-		fieldRateInHz = (stream->timing.pix_clk_100hz * 100)/
+-			(stream->timing.h_total * stream->timing.v_total);
+-
+-		setFieldWithMask(&infopacket->sb[VRR_VTEM_MD2],  MASK__VRR_VTEM_MD2__BASE_REFRESH_RATE_98,
+-				fieldRateInHz >> 8);
+-		setFieldWithMask(&infopacket->sb[VRR_VTEM_MD3], MASK__VRR_VTEM_MD3__BASE_REFRESH_RATE_07,
+-				fieldRateInHz);
+-
+-	}
+-	infopacket->valid = true;
+-}
+-
+-static void build_vrr_infopacket_data(const struct mod_vrr_params *vrr,
+-		struct dc_info_packet *infopacket)
+-{
+-	/* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
+-	infopacket->sb[1] = 0x1A;
+-
+-	/* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
+-	infopacket->sb[2] = 0x00;
+-
+-	/* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
+-	infopacket->sb[3] = 0x00;
+-
+-	/* PB4 = Reserved */
+-
+-	/* PB5 = Reserved */
+-
+-	/* PB6 = [Bits 7:3 = Reserved] */
+-
+-	/* PB6 = [Bit 0 = FreeSync Supported] */
+-	if (vrr->state != VRR_STATE_UNSUPPORTED)
+-		infopacket->sb[6] |= 0x01;
+-
+-	/* PB6 = [Bit 1 = FreeSync Enabled] */
+-	if (vrr->state != VRR_STATE_DISABLED &&
+-			vrr->state != VRR_STATE_UNSUPPORTED)
+-		infopacket->sb[6] |= 0x02;
+-
+-	/* PB6 = [Bit 2 = FreeSync Active] */
+-	if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
+-			vrr->state == VRR_STATE_ACTIVE_FIXED)
+-		infopacket->sb[6] |= 0x04;
+-
+-	/* PB7 = FreeSync Minimum refresh rate (Hz) */
+-	infopacket->sb[7] = (unsigned char)(vrr->min_refresh_in_uhz / 1000000);
+-
+-	/* PB8 = FreeSync Maximum refresh rate (Hz)
+-	 * Note: We should never go above the field rate of the mode timing set.
+-	 */
+-	infopacket->sb[8] = (unsigned char)(vrr->max_refresh_in_uhz / 1000000);
+-
+-
+-	//FreeSync HDR
+-	infopacket->sb[9] = 0;
+-	infopacket->sb[10] = 0;
+-}
+-
+-static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,
+-		struct dc_info_packet *infopacket)
+-{
+-	if (app_tf != TRANSFER_FUNC_UNKNOWN) {
+-		infopacket->valid = true;
+-
+-		infopacket->sb[6] |= 0x08;  // PB6 = [Bit 3 = Native Color Active]
+-
+-		if (app_tf == TRANSFER_FUNC_GAMMA_22) {
+-			infopacket->sb[9] |= 0x04;  // PB6 = [Bit 2 = Gamma 2.2 EOTF Active]
+-		}
+-	}
+-}
+-
+ static void build_vrr_infopacket_checksum(unsigned int *payload_size,
+ 		struct dc_info_packet *infopacket)
+ {
+@@ -839,21 +695,6 @@ static void build_vrr_infopacket_v2(enum signal_type signal,
+ 	infopacket->valid = true;
+ }
+ 
+-static void build_vrr_infopacket_vtem(const struct dc_stream_state *stream,
+-		const struct mod_vrr_params *vrr,
+-		struct dc_info_packet *infopacket)
+-{
+-	//VTEM info packet for HdmiVrr
+-
+-	memset(infopacket, 0, sizeof(struct dc_info_packet));
+-
+-	//VTEM Packet is structured differently
+-	build_vrr_infopacket_header_vtem(stream->signal, infopacket);
+-	build_vrr_vtem_infopacket_data(stream, vrr, infopacket);
+-
+-	infopacket->valid = true;
+-}
+-
+ void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
+ 		const struct dc_stream_state *stream,
+ 		const struct mod_vrr_params *vrr,
+@@ -866,16 +707,13 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
+ 	 * Check if Freesync is supported. Return if false. If true,
+ 	 * set the corresponding bit in the info packet
+ 	 */
+-	if (!vrr->supported || (!vrr->send_info_frame && packet_type != PACKET_TYPE_VTEM))
++	if (!vrr->supported || (!vrr->send_info_frame))
+ 		return;
+ 
+ 	switch (packet_type) {
+ 	case PACKET_TYPE_FS2:
+ 		build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket);
+ 		break;
+-	case PACKET_TYPE_VTEM:
+-		build_vrr_infopacket_vtem(stream, vrr, infopacket);
+-		break;
+ 	case PACKET_TYPE_VRR:
+ 	case PACKET_TYPE_FS1:
+ 	default:
+diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+index dcef85994c45..dc187844d10b 100644
+--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+@@ -173,4 +173,6 @@ bool mod_freesync_is_valid_range(struct mod_freesync *mod_freesync,
+ 		uint32_t min_refresh_request_in_uhz,
+ 		uint32_t max_refresh_request_in_uhz);
+ 
++
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
+index 5b1c9a4c7643..d930bdecb117 100644
+--- a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
+@@ -27,10 +27,10 @@
+ #define MOD_INFO_PACKET_H_
+ 
+ #include "mod_shared.h"
+-
+ //Forward Declarations
+ struct dc_stream_state;
+ struct dc_info_packet;
++struct mod_vrr_params;
+ 
+ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
+ 		struct dc_info_packet *info_packet);
+diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
+index bc13c552797f..5f4b98df3d92 100644
+--- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
++++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
+@@ -27,9 +27,78 @@
+ #include "core_types.h"
+ #include "dc_types.h"
+ #include "mod_shared.h"
++#include "mod_freesync.h"
++#include "dc.h"
+ 
+ #define HDMI_INFOFRAME_TYPE_VENDOR 0x81
+ 
++// VTEM Byte Offset
++#define VTEM_PB0		0
++#define VTEM_PB1		1
++#define VTEM_PB2		2
++#define VTEM_PB3		3
++#define VTEM_PB4		4
++#define VTEM_PB5		5
++#define VTEM_PB6		6
++
++#define VTEM_MD0		7
++#define VTEM_MD1		8
++#define VTEM_MD2		9
++#define VTEM_MD3		10
++
++
++// VTEM Byte Masks
++//PB0
++#define MASK_VTEM_PB0__RESERVED0  0x01
++#define MASK_VTEM_PB0__SYNC       0x02
++#define MASK_VTEM_PB0__VFR        0x04
++#define MASK_VTEM_PB0__AFR        0x08
++#define MASK_VTEM_PB0__DS_TYPE    0x30
++	//0: Periodic pseudo-static EM Data Set
++	//1: Periodic dynamic EM Data Set
++	//2: Unique EM Data Set
++	//3: Reserved
++#define MASK_VTEM_PB0__END        0x40
++#define MASK_VTEM_PB0__NEW        0x80
++
++//PB1
++#define MASK_VTEM_PB1__RESERVED1 0xFF
++
++//PB2
++#define MASK_VTEM_PB2__ORGANIZATION_ID 0xFF
++	//0: This is a Vendor Specific EM Data Set
++	//1: This EM Data Set is defined by This Specification (HDMI 2.1 r102.clean)
++	//2: This EM Data Set is defined by CTA-861-G
++	//3: This EM Data Set is defined by VESA
++//PB3
++#define MASK_VTEM_PB3__DATA_SET_TAG_MSB    0xFF
++//PB4
++#define MASK_VTEM_PB4__DATA_SET_TAG_LSB    0xFF
++//PB5
++#define MASK_VTEM_PB5__DATA_SET_LENGTH_MSB 0xFF
++//PB6
++#define MASK_VTEM_PB6__DATA_SET_LENGTH_LSB 0xFF
++
++
++
++//PB7-27 (20 bytes):
++//PB7 = MD0
++#define MASK_VTEM_MD0__VRR_EN         0x01
++#define MASK_VTEM_MD0__M_CONST        0x02
++#define MASK_VTEM_MD0__RESERVED2      0x0C
++#define MASK_VTEM_MD0__FVA_FACTOR_M1  0xF0
++
++//MD1
++#define MASK_VTEM_MD1__BASE_VFRONT    0xFF
++
++//MD2
++#define MASK_VTEM_MD2__BASE_REFRESH_RATE_98  0x03
++#define MASK_VTEM_MD2__RB                    0x04
++#define MASK_VTEM_MD2__RESERVED3             0xF8
++
++//MD3
++#define MASK_VTEM_MD3__BASE_REFRESH_RATE_07  0xFF
++
+ enum ColorimetryRGBDP {
+ 	ColorimetryRGB_DP_sRGB               = 0,
+ 	ColorimetryRGB_DP_AdobeRGB           = 3,
+@@ -45,6 +114,25 @@ enum ColorimetryYCCDP {
+ 	ColorimetryYCC_DP_ITU2020YCbCr  = 7,
+ };
+ 
++void setFieldWithMask(unsigned char *dest, unsigned int mask, unsigned int value)
++{
++	unsigned int shift = 0;
++
++	if (!mask || !dest)
++		return;
++
++	while (!((mask >> shift) & 1))
++		shift++;
++
++	//reset
++	*dest = *dest & ~mask;
++	//set
++	//dont let value span past mask
++	value = value & (mask >> shift);
++	//insert value
++	*dest = *dest | (value << shift);
++}
++
+ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
+ 		struct dc_info_packet *info_packet)
+ {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3580-drm-amd-display-support-spdif.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3580-drm-amd-display-support-spdif.patch
new file mode 100644
index 00000000..dab81543
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3580-drm-amd-display-support-spdif.patch
@@ -0,0 +1,101 @@
+From 81c03ac6b17d9e56a71d511dc00c37a334ffd40a Mon Sep 17 00:00:00 2001
+From: Charlene Liu <charlene.liu@amd.com>
+Date: Fri, 2 Aug 2019 14:49:58 -0400
+Subject: [PATCH 3580/4256] drm/amd/display: support spdif
+
+[Description]
+port spdif fix to staging:
+ spdif hardwired to afmt inst 1.
+ spdif func pointer
+ spdif resource allocation (reserve last audio endpoint for spdif only)
+
+Signed-off-by: Charlene Liu <charlene.liu@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_resource.c   | 17 ++++++++---------
+ drivers/gpu/drm/amd/display/dc/dce/dce_audio.c  |  4 ++--
+ 2 files changed, 10 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 1464f4c60089..953ba4d02a1e 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -259,12 +259,10 @@ bool resource_construct(
+ 				DC_ERR("DC: failed to create audio!\n");
+ 				return false;
+ 			}
+-
+ 			if (!aud->funcs->endpoint_valid(aud)) {
+ 				aud->funcs->destroy(&aud);
+ 				break;
+ 			}
+-
+ 			pool->audios[i] = aud;
+ 			pool->audio_count++;
+ 		}
+@@ -1618,24 +1616,25 @@ static struct audio *find_first_free_audio(
+ 		const struct resource_pool *pool,
+ 		enum engine_id id)
+ {
+-	int i;
+-	for (i = 0; i < pool->audio_count; i++) {
++	int i, available_audio_count;
++
++	available_audio_count = pool->audio_count;
++
++	for (i = 0; i < available_audio_count; i++) {
+ 		if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
+ 			/*we have enough audio endpoint, find the matching inst*/
+ 			if (id != i)
+ 				continue;
+-
+ 			return pool->audios[i];
+ 		}
+ 	}
+ 
+-    /* use engine id to find free audio */
+-	if ((id < pool->audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
++	/* use engine id to find free audio */
++	if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
+ 		return pool->audios[id];
+ 	}
+-
+ 	/*not found the matching one, first come first serve*/
+-	for (i = 0; i < pool->audio_count; i++) {
++	for (i = 0; i < available_audio_count; i++) {
+ 		if (res_ctx->is_audio_acquired[i] == false) {
+ 			return pool->audios[i];
+ 		}
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+index b7d63ca126df..bdcc3c8a6a91 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+@@ -611,6 +611,8 @@ void dce_aud_az_configure(
+ 
+ 	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
+ 		value);
++	DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, displayName %s: \n",
++		audio->inst, value, audio_info->display_name);
+ 
+ 	/*
+ 	*write the port ID:
+@@ -920,7 +922,6 @@ static const struct audio_funcs funcs = {
+ 	.az_configure = dce_aud_az_configure,
+ 	.destroy = dce_aud_destroy,
+ };
+-
+ void dce_aud_destroy(struct audio **audio)
+ {
+ 	struct dce_audio *aud = DCE_AUD(*audio);
+@@ -951,7 +952,6 @@ struct audio *dce_audio_create(
+ 	audio->regs = reg;
+ 	audio->shifts = shifts;
+ 	audio->masks = masks;
+-
+ 	return &audio->base;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3581-drm-amd-display-fix-stuck-test-pattern-on-right-half.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3581-drm-amd-display-fix-stuck-test-pattern-on-right-half.patch
new file mode 100644
index 00000000..fbdc5391
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3581-drm-amd-display-fix-stuck-test-pattern-on-right-half.patch
@@ -0,0 +1,38 @@
+From 622763bbfe824cd42c86fbdb3d52af3d09342cc6 Mon Sep 17 00:00:00 2001
+From: Zi Yu Liao <ziyu.liao@amd.com>
+Date: Tue, 6 Aug 2019 11:58:09 -0400
+Subject: [PATCH 3581/4256] drm/amd/display: fix stuck test pattern on right
+ half of display
+
+[why]
+With visual confirm enabled, displays where ODM combine is enabled
+has a test pattern stuck on the right half of the display even
+though the display is unblanked.
+
+[how]
+Add a condition to not show the colour ramp test pattern when the
+display is unblanked.
+
+Signed-off-by: Zi Yu Liao <ziyu.liao@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 18de1aeaa51f..aa6e5ddc89b6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -888,7 +888,7 @@ void dcn20_blank_pixel_data(
+ 	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+ 		odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
+ 				odm_pipe->stream_res.opp,
+-				dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE ?
++				dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
+ 						CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
+ 				stream->timing.display_color_depth,
+ 				&black_color,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3582-drm-amd-display-fix-odm-pipe-copy.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3582-drm-amd-display-fix-odm-pipe-copy.patch
new file mode 100644
index 00000000..d27defd6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3582-drm-amd-display-fix-odm-pipe-copy.patch
@@ -0,0 +1,48 @@
+From 5f0e2dd46b572ba571b7ebd1cbb8f34fe9885bce Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Fri, 2 Aug 2019 16:32:13 -0400
+Subject: [PATCH 3582/4256] drm/amd/display: fix odm pipe copy
+
+ODM next and prev pipe were missing from dc_copy_state
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c         | 6 ++++++
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
+ 2 files changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index f7959e122348..ba8de868606d 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1239,6 +1239,12 @@ struct dc_state *dc_copy_state(struct dc_state *src_ctx)
+ 			if (cur_pipe->bottom_pipe)
+ 				cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
+ 
++			if (cur_pipe->prev_odm_pipe)
++				cur_pipe->prev_odm_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
++
++			if (cur_pipe->next_odm_pipe)
++				cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
++
+ 	}
+ 
+ 	for (i = 0; i < new_ctx->stream_count; i++) {
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 40067403b043..f5742719b5d9 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -3188,7 +3188,7 @@ bool dc_link_dp_set_test_pattern(
+ 	memset(&training_pattern, 0, sizeof(training_pattern));
+ 
+ 	for (i = 0; i < MAX_PIPES; i++) {
+-		if (pipes[i].stream->link == link) {
++		if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
+ 			pipe_ctx = &pipes[i];
+ 			break;
+ 		}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3583-drm-amd-display-Fix-number-of-slices-not-being-check.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3583-drm-amd-display-Fix-number-of-slices-not-being-check.patch
new file mode 100644
index 00000000..d7271e31
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3583-drm-amd-display-Fix-number-of-slices-not-being-check.patch
@@ -0,0 +1,35 @@
+From 990123f13321bb657120fb5658ba8f5977363fc0 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Tue, 6 Aug 2019 13:23:17 -0400
+Subject: [PATCH 3583/4256] drm/amd/display: Fix number of slices not being
+ checked for dsc
+
+[why]
+num_slices_h was not being checked
+
+[How]
+Fix the typo and check num_slices_h
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+index c4f861e6bd53..1b419407af94 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+@@ -322,7 +322,7 @@ static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_
+ 		    dsc_cfg->dc_dsc_cfg.linebuf_depth == 0)));
+ 	ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375
+ 
+-	if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_v ||
++	if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h ||
+ 		!(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) ||
+ 		!dsc_cfg->pic_width || !dsc_cfg->pic_height ||
+ 		!((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3584-drm-amd-display-fix-dcn20-odm-dpp-programming.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3584-drm-amd-display-fix-dcn20-odm-dpp-programming.patch
new file mode 100644
index 00000000..db985a59
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3584-drm-amd-display-fix-dcn20-odm-dpp-programming.patch
@@ -0,0 +1,52 @@
+From 313389cbdb0be06fa7fec79ccfb74ea93d020204 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Tue, 6 Aug 2019 15:10:33 -0400
+Subject: [PATCH 3584/4256] drm/amd/display: fix dcn20 odm dpp programming
+
+dcn20 requires special casing for odm.
+This change treats odm as alternative to mpc tree on dcn20.
+
+This is planned to be fixed in a future refactor
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c           | 1 +
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 7 ++++++-
+ 2 files changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index ba8de868606d..bae845dfd069 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -2035,6 +2035,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
+ 
+ 		if (!pipe_ctx->top_pipe &&
++			!pipe_ctx->prev_odm_pipe &&
+ 			pipe_ctx->stream &&
+ 			pipe_ctx->stream == stream) {
+ 			struct dc_stream_status *stream_status = NULL;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index aa6e5ddc89b6..230a4216c2ae 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1054,8 +1054,13 @@ static void dcn20_program_all_pipe_in_tree(
+ 	if (pipe_ctx->plane_state != NULL)
+ 		dcn20_program_pipe(dc, pipe_ctx, context);
+ 
+-	if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
++	if (pipe_ctx->bottom_pipe != NULL) {
++		ASSERT(pipe_ctx->bottom_pipe != pipe_ctx);
+ 		dcn20_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
++	} else if (pipe_ctx->next_odm_pipe != NULL) {
++		ASSERT(pipe_ctx->next_odm_pipe != pipe_ctx);
++		dcn20_program_all_pipe_in_tree(dc, pipe_ctx->next_odm_pipe, context);
++	}
+ }
+ 
+ void dcn20_pipe_control_lock_global(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3585-drm-amd-display-fix-odm-stream-release.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3585-drm-amd-display-fix-odm-stream-release.patch
new file mode 100644
index 00000000..a813cac2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3585-drm-amd-display-fix-odm-stream-release.patch
@@ -0,0 +1,113 @@
+From 3d7069a8dfa061d2a7e9c238aad770d07bb3a5fe Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Tue, 6 Aug 2019 16:09:07 -0400
+Subject: [PATCH 3585/4256] drm/amd/display: fix odm stream release
+
+Need to memset all odm pipes when calling dc_remove_stream_from_ctx
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_resource.c | 65 +++++++++----------
+ 1 file changed, 32 insertions(+), 33 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 953ba4d02a1e..6e88cb0fffce 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -1111,13 +1111,12 @@ struct pipe_ctx *resource_get_head_pipe_for_stream(
+ 		struct dc_stream_state *stream)
+ {
+ 	int i;
++
+ 	for (i = 0; i < MAX_PIPES; i++) {
+ 		if (res_ctx->pipe_ctx[i].stream == stream
+ 				&& !res_ctx->pipe_ctx[i].top_pipe
+-				&& !res_ctx->pipe_ctx[i].prev_odm_pipe) {
++				&& !res_ctx->pipe_ctx[i].prev_odm_pipe)
+ 			return &res_ctx->pipe_ctx[i];
+-			break;
+-		}
+ 	}
+ 	return NULL;
+ }
+@@ -1694,45 +1693,45 @@ enum dc_status dc_remove_stream_from_ctx(
+ {
+ 	int i;
+ 	struct dc_context *dc_ctx = dc->ctx;
+-	struct pipe_ctx *del_pipe = NULL;
++	struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream);
++	struct pipe_ctx *odm_pipe;
+ 
+-	/* Release primary pipe */
+-	for (i = 0; i < MAX_PIPES; i++) {
+-		if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
+-				!new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
+-			del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
++	if (!del_pipe) {
++		DC_ERROR("Pipe not found for stream %p !\n", stream);
++		return DC_ERROR_UNEXPECTED;
++	}
+ 
+-			ASSERT(del_pipe->stream_res.stream_enc);
+-			update_stream_engine_usage(
+-					&new_ctx->res_ctx,
+-						dc->res_pool,
+-					del_pipe->stream_res.stream_enc,
+-					false);
++	odm_pipe = del_pipe->next_odm_pipe;
+ 
+-			if (del_pipe->stream_res.audio)
+-				update_audio_usage(
+-					&new_ctx->res_ctx,
+-					dc->res_pool,
+-					del_pipe->stream_res.audio,
+-					false);
++	/* Release primary pipe */
++	ASSERT(del_pipe->stream_res.stream_enc);
++	update_stream_engine_usage(
++			&new_ctx->res_ctx,
++				dc->res_pool,
++			del_pipe->stream_res.stream_enc,
++			false);
+ 
+-			resource_unreference_clock_source(&new_ctx->res_ctx,
+-							  dc->res_pool,
+-							  del_pipe->clock_source);
++	if (del_pipe->stream_res.audio)
++		update_audio_usage(
++			&new_ctx->res_ctx,
++			dc->res_pool,
++			del_pipe->stream_res.audio,
++			false);
+ 
+-			if (dc->res_pool->funcs->remove_stream_from_ctx)
+-				dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
++	resource_unreference_clock_source(&new_ctx->res_ctx,
++					  dc->res_pool,
++					  del_pipe->clock_source);
+ 
+-			memset(del_pipe, 0, sizeof(*del_pipe));
++	if (dc->res_pool->funcs->remove_stream_from_ctx)
++		dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
+ 
+-			break;
+-		}
+-	}
++	while (odm_pipe) {
++		struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
+ 
+-	if (!del_pipe) {
+-		DC_ERROR("Pipe not found for stream %p !\n", stream);
+-		return DC_ERROR_UNEXPECTED;
++		memset(odm_pipe, 0, sizeof(*odm_pipe));
++		odm_pipe = next_odm_pipe;
+ 	}
++	memset(del_pipe, 0, sizeof(*del_pipe));
+ 
+ 	for (i = 0; i < new_ctx->stream_count; i++)
+ 		if (new_ctx->streams[i] == stream)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3586-drm-amd-display-fix-odm-validation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3586-drm-amd-display-fix-odm-validation.patch
new file mode 100644
index 00000000..2830a6c2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3586-drm-amd-display-fix-odm-validation.patch
@@ -0,0 +1,118 @@
+From bf139b37f2d0b90b5601d03d6cc41fbdefdde746 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Tue, 6 Aug 2019 12:17:57 -0400
+Subject: [PATCH 3586/4256] drm/amd/display: fix odm validation
+
+Update bw validation to use prev and next odm pipe pointers
+for populating dml inputs.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 40 +++++++++----------
+ 1 file changed, 19 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index aa1342ccf8b4..477885816854 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1600,12 +1600,8 @@ static bool dcn20_split_stream_for_odm(
+ 		struct pipe_ctx *next_odm_pipe)
+ {
+ 	int pipe_idx = next_odm_pipe->pipe_idx;
+-	struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
+-	struct pipe_ctx *sec_next_pipe = next_odm_pipe->next_odm_pipe;
+-	int new_width;
+ 
+ 	*next_odm_pipe = *prev_odm_pipe;
+-	next_odm_pipe->next_odm_pipe = sec_next_pipe;
+ 
+ 	next_odm_pipe->pipe_idx = pipe_idx;
+ 	next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
+@@ -1627,11 +1623,11 @@ static bool dcn20_split_stream_for_odm(
+ 	ASSERT(next_odm_pipe->top_pipe == NULL);
+ 
+ 	if (prev_odm_pipe->plane_state) {
++		struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
++		int new_width;
++
+ 		/* HACTIVE halved for odm combine */
+ 		sd->h_active /= 2;
+-		/* Copy scl_data to secondary pipe */
+-		next_odm_pipe->plane_res.scl_data = *sd;
+-
+ 		/* Calculate new vp and recout for left pipe */
+ 		/* Need at least 16 pixels width per side */
+ 		if (sd->recout.x + 16 >= sd->h_active)
+@@ -1645,10 +1641,12 @@ static bool dcn20_split_stream_for_odm(
+ 
+ 		/* Calculate new vp and recout for right pipe */
+ 		sd = &next_odm_pipe->plane_res.scl_data;
+-		new_width = sd->recout.width + sd->recout.x - sd->h_active;
++		/* HACTIVE halved for odm combine */
++		sd->h_active /= 2;
+ 		/* Need at least 16 pixels width per side */
+ 		if (new_width <= 16)
+ 			return false;
++		new_width = sd->recout.width + sd->recout.x - sd->h_active;
+ 		sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
+ 				sd->ratios.horz, sd->recout.width - new_width));
+ 		sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
+@@ -1818,6 +1816,19 @@ int dcn20_populate_dml_pipes_from_context(
+ 		pipes[pipe_cnt].dout.dp_lanes = 4;
+ 		pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
+ 		pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
++		pipes[pipe_cnt].pipe.dest.odm_combine = res_ctx->pipe_ctx[i].prev_odm_pipe
++							|| res_ctx->pipe_ctx[i].next_odm_pipe;
++		pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
++		if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
++				== res_ctx->pipe_ctx[i].plane_state)
++			pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
++		else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
++			struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
++
++			while (first_pipe->prev_odm_pipe)
++				first_pipe = first_pipe->prev_odm_pipe;
++			pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
++		}
+ 
+ 		switch (res_ctx->pipe_ctx[i].stream->signal) {
+ 		case SIGNAL_TYPE_DISPLAY_PORT_MST:
+@@ -1870,7 +1881,6 @@ int dcn20_populate_dml_pipes_from_context(
+ 			break;
+ 		}
+ 
+-
+ 		switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
+ 		case PIXEL_ENCODING_RGB:
+ 		case PIXEL_ENCODING_YCBCR444:
+@@ -1892,10 +1902,6 @@ int dcn20_populate_dml_pipes_from_context(
+ 			pipes[pipe_cnt].dout.output_format = dm_444;
+ 			pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
+ 		}
+-		pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
+-		if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
+-				== res_ctx->pipe_ctx[i].plane_state)
+-			pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
+ 
+ 		/* todo: default max for now, until there is logic reflecting this in dc*/
+ 		pipes[pipe_cnt].dout.output_bpc = 12;
+@@ -1944,14 +1950,6 @@ int dcn20_populate_dml_pipes_from_context(
+ 					&& res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
+ 					|| (res_ctx->pipe_ctx[i].top_pipe
+ 					&& res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
+-			pipes[pipe_cnt].pipe.dest.odm_combine = (res_ctx->pipe_ctx[i].bottom_pipe
+-					&& res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln
+-					&& res_ctx->pipe_ctx[i].bottom_pipe->stream_res.opp
+-						!= res_ctx->pipe_ctx[i].stream_res.opp)
+-				|| (res_ctx->pipe_ctx[i].top_pipe
+-					&& res_ctx->pipe_ctx[i].top_pipe->plane_state == pln
+-					&& res_ctx->pipe_ctx[i].top_pipe->stream_res.opp
+-						!= res_ctx->pipe_ctx[i].stream_res.opp);
+ 			pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
+ 					|| pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
+ 			pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3587-drm-amd-display-add-Cursor-Degamma-logic-for-DCN2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3587-drm-amd-display-add-Cursor-Degamma-logic-for-DCN2.patch
new file mode 100644
index 00000000..5e015d41
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3587-drm-amd-display-add-Cursor-Degamma-logic-for-DCN2.patch
@@ -0,0 +1,135 @@
+From b7517e55ceac4631bdb32256fbf8daa158228186 Mon Sep 17 00:00:00 2001
+From: Bayan Zabihiyan <bayan.zabihiyan@amd.com>
+Date: Fri, 26 Jul 2019 11:10:11 -0400
+Subject: [PATCH 3587/4256] drm/amd/display: add Cursor Degamma logic for DCN2
+
+[Why]
+We need to have the ability to to tell us set degamma on the cursor.
+
+[How]
+Pass a flag down to register programming that tells us if the
+current surface format needs cursor degamma.
+
+Signed-off-by: Bayan Zabihiyan <bayan.zabihiyan@amd.com>
+Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc_hw_types.h           |  3 ++-
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c       |  3 ++-
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h       |  2 +-
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  2 +-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c       | 10 +++++++---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h       |  2 +-
+ drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h            |  2 +-
+ 7 files changed, 15 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+index 929c4eadc1dc..f35826d5d1e5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+@@ -516,7 +516,8 @@ union dc_cursor_attribute_flags {
+ 		uint32_t INVERT_PIXEL_DATA:1;
+ 		uint32_t ZERO_EXPANSION:1;
+ 		uint32_t MIN_MAX_INVERT:1;
+-		uint32_t RESERVED:25;
++		uint32_t ENABLE_CURSOR_DEGAMMA:1;
++		uint32_t RESERVED:24;
+ 	} bits;
+ 	uint32_t value;
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+index b95ec73fcae3..23b2361cec62 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+@@ -426,8 +426,9 @@ void dpp1_cnv_setup (
+ 
+ void dpp1_set_cursor_attributes(
+ 		struct dpp *dpp_base,
+-		enum dc_cursor_color_format color_format)
++		struct dc_cursor_attributes *cursor_attributes)
+ {
++	enum dc_cursor_color_format color_format = cursor_attributes->color_format;
+ 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
+ 
+ 	REG_UPDATE_2(CURSOR0_CONTROL,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+index 8a5517eebb7c..e2c613611ac9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+@@ -1368,7 +1368,7 @@ enum dcn10_input_csc_select {
+ 
+ void dpp1_set_cursor_attributes(
+ 		struct dpp *dpp_base,
+-		enum dc_cursor_color_format color_format);
++		struct dc_cursor_attributes *cursor_attributes);
+ 
+ void dpp1_set_cursor_position(
+ 		struct dpp *dpp_base,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 0cbd344ca447..808a31c197d2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2985,7 +2985,7 @@ static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
+ 	pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
+ 			pipe_ctx->plane_res.hubp, attributes);
+ 	pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
+-		pipe_ctx->plane_res.dpp, attributes->color_format);
++		pipe_ctx->plane_res.dpp, attributes);
+ }
+ 
+ static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+index db311574f42f..2f5aade1e882 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+@@ -342,14 +342,18 @@ void dpp2_cnv_set_alpha_keyer(
+ 
+ void dpp2_set_cursor_attributes(
+ 		struct dpp *dpp_base,
+-		enum dc_cursor_color_format color_format)
++		struct dc_cursor_attributes *cursor_attributes)
+ {
++	enum dc_cursor_color_format color_format = cursor_attributes->color_format;
+ 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
+ 	int cur_rom_en = 0;
+ 
+ 	if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
+-		color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA)
+-		cur_rom_en = 1;
++		color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
++		if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {
++			cur_rom_en = 1;
++		}
++	}
+ 
+ 	REG_UPDATE_3(CURSOR0_CONTROL,
+ 			CUR0_MODE, color_format,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
+index 1f5d99a6d240..290b2854bd2c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
+@@ -676,7 +676,7 @@ void dscl2_calc_lb_num_partitions(
+ 
+ void dpp2_set_cursor_attributes(
+ 		struct dpp *dpp_base,
+-		enum dc_cursor_color_format color_format);
++		struct dc_cursor_attributes *cursor_attributes);
+ 
+ void dpp2_dummy_program_input_lut(
+ 			struct dpp *dpp_base,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+index 9b69a06ab46f..474c7194a9f8 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+@@ -201,7 +201,7 @@ struct dpp_funcs {
+ 
+ 	void (*set_cursor_attributes)(
+ 			struct dpp *dpp_base,
+-			enum dc_cursor_color_format color_format);
++			struct dc_cursor_attributes *cursor_attributes);
+ 
+ 	void (*set_cursor_position)(
+ 			struct dpp *dpp_base,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3588-drm-amd-display-Enable-HW-rotation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3588-drm-amd-display-Enable-HW-rotation.patch
new file mode 100644
index 00000000..7f800032
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3588-drm-amd-display-Enable-HW-rotation.patch
@@ -0,0 +1,143 @@
+From 252680ecb1b81f5eb52878e54a0fbe0545520127 Mon Sep 17 00:00:00 2001
+From: Jaehyun Chung <jaehyun.chung@amd.com>
+Date: Wed, 7 Aug 2019 11:20:16 -0400
+Subject: [PATCH 3588/4256] drm/amd/display: Enable HW rotation
+
+[Why] HW rotation is not enabled. Calculations for cursor rotation
+are wrong for the values passed to set_cursor_position.
+
+[How] Swap Src rect and height and vertically mirror surface for
+the correct surface rotation direction. Cursor position is rotated
+according to angle. Offset calculations are tweaked for non-rotated
+cursor hotspot and width/height.
+
+Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c  | 13 +++++++
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 34 +++++++++++++++++++
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 18 +++++++---
+ 3 files changed, 60 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+index 23b2361cec62..d8b2da18db39 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+@@ -457,6 +457,19 @@ void dpp1_set_cursor_position(
+ 	int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
+ 	uint32_t cur_en = pos->enable ? 1 : 0;
+ 
++	// Cursor width/height and hotspots need to be rotated for offset calculation
++	if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
++		swap(width, height);
++		if (param->rotation == ROTATION_ANGLE_90) {
++			src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
++			src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
++		}
++	} else if (param->rotation == ROTATION_ANGLE_180) {
++		src_x_offset = pos->x - param->viewport.x;
++		src_y_offset = pos->y - param->viewport.y;
++	}
++
++
+ 	if (src_x_offset >= (int)param->viewport.width)
+ 		cur_en = 0;  /* not visible beyond right edge*/
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 808a31c197d2..24a5d79887c1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2974,6 +2974,40 @@ static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
+ 			== PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
+ 		pos_cpy.enable = false;
+ 
++	// Swap axis and mirror horizontally
++	if (param.rotation == ROTATION_ANGLE_90) {
++		uint32_t temp_x = pos_cpy.x;
++		pos_cpy.x = pipe_ctx->plane_res.scl_data.viewport.width -
++				(pos_cpy.y - pipe_ctx->plane_res.scl_data.viewport.x) + pipe_ctx->plane_res.scl_data.viewport.x;
++		pos_cpy.y = temp_x;
++	}
++	// Swap axis and mirror vertically
++	else if (param.rotation == ROTATION_ANGLE_270) {
++		uint32_t temp_y = pos_cpy.y;
++		if (pos_cpy.x >  pipe_ctx->plane_res.scl_data.viewport.height) {
++			pos_cpy.x = pos_cpy.x - pipe_ctx->plane_res.scl_data.viewport.height;
++			pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x;
++		} else {
++			pos_cpy.y = 2 * pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x;
++		}
++		pos_cpy.x = temp_y;
++	}
++	// Mirror horizontally and vertically
++	else if (param.rotation == ROTATION_ANGLE_180) {
++		if (pos_cpy.x >= pipe_ctx->plane_res.scl_data.viewport.width + pipe_ctx->plane_res.scl_data.viewport.x) {
++			pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.width
++					- pos_cpy.x + 2 * pipe_ctx->plane_res.scl_data.viewport.x;
++		} else {
++			uint32_t temp_x = pos_cpy.x;
++			pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.x - pos_cpy.x;
++			if (temp_x >= pipe_ctx->plane_res.scl_data.viewport.x + (int)hubp->curs_attr.width
++					|| pos_cpy.x <= (int)hubp->curs_attr.width + pipe_ctx->plane_state->src_rect.x) {
++				pos_cpy.x = temp_x + pipe_ctx->plane_res.scl_data.viewport.width;
++			}
++		}
++		pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y;
++	}
++
+ 	hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
+ 	dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+index b4b384c7fa9b..69e2aae42394 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+@@ -945,6 +945,8 @@ void hubp2_cursor_set_position(
+ 	int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
+ 	int x_hotspot = pos->x_hotspot;
+ 	int y_hotspot = pos->y_hotspot;
++	int cursor_height = (int)hubp->curs_attr.height;
++	int cursor_width = (int)hubp->curs_attr.width;
+ 	uint32_t dst_x_offset;
+ 	uint32_t cur_en = pos->enable ? 1 : 0;
+ 
+@@ -958,10 +960,16 @@ void hubp2_cursor_set_position(
+ 	if (hubp->curs_attr.address.quad_part == 0)
+ 		return;
+ 
++	// Rotated cursor width/height and hotspots tweaks for offset calculation
+ 	if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
+-		src_x_offset = pos->y - pos->y_hotspot - param->viewport.x;
+-		y_hotspot = pos->x_hotspot;
+-		x_hotspot = pos->y_hotspot;
++		swap(cursor_height, cursor_width);
++		if (param->rotation == ROTATION_ANGLE_90) {
++			src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
++			src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
++		}
++	} else if (param->rotation == ROTATION_ANGLE_180) {
++		src_x_offset = pos->x - param->viewport.x;
++		src_y_offset = pos->y - param->viewport.y;
+ 	}
+ 
+ 	if (param->mirror) {
+@@ -983,13 +991,13 @@ void hubp2_cursor_set_position(
+ 	if (src_x_offset >= (int)param->viewport.width)
+ 		cur_en = 0;  /* not visible beyond right edge*/
+ 
+-	if (src_x_offset + (int)hubp->curs_attr.width <= 0)
++	if (src_x_offset + cursor_width <= 0)
+ 		cur_en = 0;  /* not visible beyond left edge*/
+ 
+ 	if (src_y_offset >= (int)param->viewport.height)
+ 		cur_en = 0;  /* not visible beyond bottom edge*/
+ 
+-	if (src_y_offset + (int)hubp->curs_attr.height <= 0)
++	if (src_y_offset + cursor_height <= 0)
+ 		cur_en = 0;  /* not visible beyond top edge*/
+ 
+ 	if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3589-drm-amd-display-Add-Logging-for-Gamma-Related-inform.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3589-drm-amd-display-Add-Logging-for-Gamma-Related-inform.patch
new file mode 100644
index 00000000..acb21591
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3589-drm-amd-display-Add-Logging-for-Gamma-Related-inform.patch
@@ -0,0 +1,68 @@
+From e199d3795f1c258061c307218063b40a26a20841 Mon Sep 17 00:00:00 2001
+From: Wyatt Wood <wyatt.wood@amd.com>
+Date: Wed, 7 Aug 2019 13:48:24 -0400
+Subject: [PATCH 3589/4256] drm/amd/display: Add Logging for Gamma Related
+ information
+
+[Why]
+A recent bug showed that logging would be useful in debugging
+various gamma issues.
+
+[How]
+Add logging in dc.
+Fix formatting for easier graphing.
+
+Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c    | 12 ++++++------
+ .../gpu/drm/amd/display/modules/color/color_gamma.c  |  4 ++--
+ 2 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 24a5d79887c1..5057a8946a71 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1450,15 +1450,15 @@ static void log_tf(struct dc_context *ctx,
+ 	DC_LOG_ALL_TF_CHANNELS("Logging all channels...");
+ 
+ 	for (i = 0; i < hw_points_num; i++) {
+-		DC_LOG_GAMMA("R %d %llu\n", i, tf->tf_pts.red[i].value);
+-		DC_LOG_ALL_TF_CHANNELS("G %d, %llu\n", i, tf->tf_pts.green[i].value);
+-		DC_LOG_ALL_TF_CHANNELS("B %d, %llu\n", i, tf->tf_pts.blue[i].value);
++		DC_LOG_GAMMA("R\t%d\t%llu\n", i, tf->tf_pts.red[i].value);
++		DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu\n", i, tf->tf_pts.green[i].value);
++		DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu\n", i, tf->tf_pts.blue[i].value);
+ 	}
+ 
+ 	for (i = hw_points_num; i < MAX_NUM_HW_POINTS; i++) {
+-		DC_LOG_ALL_GAMMA("R %d %llu\n", i, tf->tf_pts.red[i].value);
+-		DC_LOG_ALL_TF_CHANNELS("G %d %llu\n", i, tf->tf_pts.green[i].value);
+-		DC_LOG_ALL_TF_CHANNELS("B %d %llu\n", i, tf->tf_pts.blue[i].value);
++		DC_LOG_ALL_GAMMA("R\t%d\t%llu\n", i, tf->tf_pts.red[i].value);
++		DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu\n", i, tf->tf_pts.green[i].value);
++		DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu\n", i, tf->tf_pts.blue[i].value);
+ 	}
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+index 8f78ea226dae..19475cf5ab72 100644
+--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
++++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+@@ -99,10 +99,10 @@ void log_x_points_distribution(struct dal_logger *logger)
+ 	int i = 0;
+ 
+ 	if (logger != NULL) {
+-		LOG_GAMMA_WRITE("]Log X Distribution\n");
++		LOG_GAMMA_WRITE("Log X Distribution\n");
+ 
+ 		for (i = 0; i < MAX_HW_POINTS; i++)
+-			LOG_GAMMA_WRITE("]%llu\n", coordinates_x[i].x.value);
++			LOG_GAMMA_WRITE("%llu\n", coordinates_x[i].x.value);
+ 	}
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3590-drm-amd-display-set-av_mute-in-hw_init-for-HDMI.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3590-drm-amd-display-set-av_mute-in-hw_init-for-HDMI.patch
new file mode 100644
index 00000000..b69136bc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3590-drm-amd-display-set-av_mute-in-hw_init-for-HDMI.patch
@@ -0,0 +1,97 @@
+From e11914a4d0e8480221c15850fad2011e44aef5d3 Mon Sep 17 00:00:00 2001
+From: Charlene Liu <charlene.liu@amd.com>
+Date: Wed, 7 Aug 2019 17:25:49 -0400
+Subject: [PATCH 3590/4256] drm/amd/display: set av_mute in hw_init for HDMI
+
+[Description]
+OS will reserve HW state in UEFI mode.
+Driver init_hw reset to RGB which caused HDMI green in YCbCr mode.
+read HW blank_color based on acc_mode.
+
+Signed-off-by: Charlene Liu <charlene.liu@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../amd/display/dc/dcn10/dcn10_link_encoder.c | 23 +++++++++++++++++++
+ .../amd/display/dc/dcn10/dcn10_link_encoder.h |  2 ++
+ .../amd/display/dc/dcn20/dcn20_link_encoder.c |  1 +
+ .../drm/amd/display/dc/inc/hw/link_encoder.h  |  2 ++
+ 4 files changed, 28 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+index e4c7ecd87de7..4034f7787a35 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+@@ -86,6 +86,7 @@ static const struct link_encoder_funcs dcn10_lnk_enc_funcs = {
+ 	.disable_hpd = dcn10_link_encoder_disable_hpd,
+ 	.is_dig_enabled = dcn10_is_dig_enabled,
+ 	.get_dig_frontend = dcn10_get_dig_frontend,
++	.get_dig_mode = dcn10_get_dig_mode,
+ 	.destroy = dcn10_link_encoder_destroy
+ };
+ 
+@@ -1394,3 +1395,25 @@ void dcn10_aux_initialize(struct dcn10_link_encoder *enc10)
+ 	AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0,
+ 			AUX_RX_RECEIVE_WINDOW, 0);
+ }
++
++enum signal_type dcn10_get_dig_mode(
++	struct link_encoder *enc)
++{
++	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
++	uint32_t value;
++	REG_GET(DIG_BE_CNTL, DIG_MODE, &value);
++	switch (value) {
++	case 1:
++		return SIGNAL_TYPE_DISPLAY_PORT;
++	case 2:
++		return SIGNAL_TYPE_DVI_SINGLE_LINK;
++	case 3:
++		return SIGNAL_TYPE_HDMI_TYPE_A;
++	case 5:
++		return SIGNAL_TYPE_DISPLAY_PORT_MST;
++	default:
++		return SIGNAL_TYPE_NONE;
++	}
++	return SIGNAL_TYPE_NONE;
++}
++
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+index f3e57343417c..8bf5f0f2301d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+@@ -515,4 +515,6 @@ unsigned int dcn10_get_dig_frontend(struct link_encoder *enc);
+ 
+ void dcn10_aux_initialize(struct dcn10_link_encoder *enc10);
+ 
++enum signal_type dcn10_get_dig_mode(
++	struct link_encoder *enc);
+ #endif /* __DC_LINK_ENCODER__DCN10_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
+index f495582e9e87..e476f27aa3a9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
+@@ -341,6 +341,7 @@ static const struct link_encoder_funcs dcn20_link_enc_funcs = {
+ 	.fec_set_enable = enc2_fec_set_enable,
+ 	.fec_set_ready = enc2_fec_set_ready,
+ 	.fec_is_active = enc2_fec_is_active,
++	.get_dig_mode = dcn10_get_dig_mode,
+ 	.get_dig_frontend = dcn10_get_dig_frontend,
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+index 7001bfbd6681..abb4e4237fb6 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+@@ -184,6 +184,8 @@ struct link_encoder_funcs {
+ 	bool (*fec_is_active)(struct link_encoder *enc);
+ #endif
+ 	bool (*is_in_alt_mode) (struct link_encoder *enc);
++	enum signal_type (*get_dig_mode)(
++		struct link_encoder *enc);
+ };
+ 
+ #endif /* LINK_ENCODER_H_ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3591-drm-amd-display-MST-topology-debugfs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3591-drm-amd-display-MST-topology-debugfs.patch
new file mode 100644
index 00000000..e243c3a3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3591-drm-amd-display-MST-topology-debugfs.patch
@@ -0,0 +1,57 @@
+From b1104f15d61aa3b02845e93d263eb0b117280eb5 Mon Sep 17 00:00:00 2001
+From: David Francis <David.Francis@amd.com>
+Date: Thu, 25 Jul 2019 15:22:16 -0400
+Subject: [PATCH 3591/4256] drm/amd/display: MST topology debugfs
+
+DRM provides drm_dp_mst_dump_topology, which prints
+useful information about MST devices
+
+Hook this up to a debugfs file named amdgpu_mst_topology
+
+Signed-off-by: David Francis <David.Francis@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 24 +++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+index e649280574c0..8fa160378378 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+@@ -1052,9 +1052,33 @@ static int target_backlight_read(struct seq_file *m, void *data)
+ 	return 0;
+ }
+ 
++static int mst_topo(struct seq_file *m, void *unused)
++{
++	struct drm_info_node *node = (struct drm_info_node *)m->private;
++	struct drm_device *dev = node->minor->dev;
++	struct drm_connector *connector;
++	struct drm_connector_list_iter conn_iter;
++	struct amdgpu_dm_connector *aconnector;
++
++	drm_connector_list_iter_begin(dev, &conn_iter);
++	drm_for_each_connector_iter(connector, &conn_iter) {
++		if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
++			continue;
++
++		aconnector = to_amdgpu_dm_connector(connector);
++
++		seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
++		drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
++	}
++	drm_connector_list_iter_end(&conn_iter);
++
++	return 0;
++}
++
+ static const struct drm_info_list amdgpu_dm_debugfs_list[] = {
+ 	{"amdgpu_current_backlight_pwm", &current_backlight_read},
+ 	{"amdgpu_target_backlight_pwm", &target_backlight_read},
++	{"amdgpu_mst_topology", &mst_topo},
+ };
+ 
+ /*
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3592-drm-amd-display-fix-DML-not-calculating-delivery-tim.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3592-drm-amd-display-fix-DML-not-calculating-delivery-tim.patch
new file mode 100644
index 00000000..3bfb041c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3592-drm-amd-display-fix-DML-not-calculating-delivery-tim.patch
@@ -0,0 +1,63 @@
+From 68064bb19a5719108199e242040b678802dba418 Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Wed, 7 Aug 2019 16:24:46 -0400
+Subject: [PATCH 3592/4256] drm/amd/display: fix DML not calculating delivery
+ time
+
+[why]
+Calculating DCFCLK DS time requires calculating
+delivery time for luma/chroma, but this value is
+not calculated in DMLv2, it was inadvertently
+removed when porting DMLv2
+
+[how]
+Add the calculation back
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../dc/dml/dcn20/display_mode_vba_20v2.c      | 27 +++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+index 22455db54980..0fafd693ffb4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+@@ -1475,6 +1475,33 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
+ 							/ mode_lib->vba.ReturnBW;
+ 
+ 	mode_lib->vba.LastPixelOfLineExtraWatermark = 0;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++			if (mode_lib->vba.VRatio[k] <= 1.0)
++				mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] =
++						(double) mode_lib->vba.SwathWidthY[k]
++								* mode_lib->vba.DPPPerPlane[k]
++								/ mode_lib->vba.HRatio[k]
++								/ mode_lib->vba.PixelClock[k];
++			else
++				mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] =
++						(double) mode_lib->vba.SwathWidthY[k]
++								/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
++								/ mode_lib->vba.DPPCLK[k];
++
++			if (mode_lib->vba.BytePerPixelDETC[k] == 0)
++				mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] = 0.0;
++			else if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0)
++				mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] =
++						mode_lib->vba.SwathWidthY[k] / 2.0
++								* mode_lib->vba.DPPPerPlane[k]
++								/ (mode_lib->vba.HRatio[k] / 2.0)
++								/ mode_lib->vba.PixelClock[k];
++			else
++				mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] =
++						mode_lib->vba.SwathWidthY[k] / 2.0
++								/ mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k]
++								/ mode_lib->vba.DPPCLK[k];
++		}
+ 
+ 	mode_lib->vba.UrgentExtraLatency = mode_lib->vba.UrgentRoundTripAndOutOfOrderLatency
+ 			+ (mode_lib->vba.TotalActiveDPP * mode_lib->vba.PixelChunkSizeInKByte
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3593-drm-amd-display-Expose-OTG_V_TOTAL_MID-for-HW-Diags.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3593-drm-amd-display-Expose-OTG_V_TOTAL_MID-for-HW-Diags.patch
new file mode 100644
index 00000000..4869f02f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3593-drm-amd-display-Expose-OTG_V_TOTAL_MID-for-HW-Diags.patch
@@ -0,0 +1,213 @@
+From 9e58c1d3b340644693597dd1a91ef3616f109f27 Mon Sep 17 00:00:00 2001
+From: Bayan Zabihiyan <bayan.zabihiyan@amd.com>
+Date: Thu, 8 Aug 2019 11:08:52 -0400
+Subject: [PATCH 3593/4256] drm/amd/display: Expose OTG_V_TOTAL_MID for HW
+ Diags
+
+[Why]
+Existing HW Features, HW Diags test requested that the
+registers be exposed.
+
+[How]
+Add V_TOTAL_MID to existing DC structures.
+Make sure values are passed down throughout DC
+Add Register definition.
+Program the additional registers
+Add additional Logic for V_TOTAL_CONTROL.
+
+Signed-off-by: Bayan Zabihiyan <bayan.zabihiyan@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c             |  4 +++-
+ drivers/gpu/drm/amd/display/dc/dc_hw_types.h         |  2 ++
+ .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c  |  3 ++-
+ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c    |  5 ++++-
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c    | 12 ++++++++++++
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h    |  8 ++++++++
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c   |  2 ++
+ .../gpu/drm/amd/display/dc/inc/hw/timing_generator.h |  2 ++
+ drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h    |  3 ++-
+ 9 files changed, 37 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index bae845dfd069..8dd9db41bc4a 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -294,7 +294,9 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
+ 			dc->hwss.set_drr(&pipe,
+ 					1,
+ 					adjust->v_total_min,
+-					adjust->v_total_max);
++					adjust->v_total_max,
++					adjust->v_total_mid,
++					adjust->v_total_mid_frame_num);
+ 
+ 			ret = true;
+ 		}
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+index f35826d5d1e5..0b8700a8a94a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+@@ -757,6 +757,8 @@ struct crtc_trigger_info {
+ struct dc_crtc_timing_adjust {
+ 	uint32_t v_total_min;
+ 	uint32_t v_total_max;
++	uint32_t v_total_mid;
++	uint32_t v_total_mid_frame_num;
+ };
+ 
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index c2d026ba269f..c273490ddcab 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -1716,7 +1716,8 @@ void dce110_set_safe_displaymarks(
+  ******************************************************************************/
+ 
+ static void set_drr(struct pipe_ctx **pipe_ctx,
+-		int num_pipes, int vmin, int vmax)
++		int num_pipes, unsigned int vmin, unsigned int vmax,
++		unsigned int vmid, unsigned int vmid_frame_number)
+ {
+ 	int i = 0;
+ 	struct drr_params params = {0};
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 5057a8946a71..b981ea849cc9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2745,7 +2745,8 @@ static void dcn10_optimize_bandwidth(
+ }
+ 
+ static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
+-		int num_pipes, int vmin, int vmax)
++		int num_pipes, unsigned int vmin, unsigned int vmax,
++		unsigned int vmid, unsigned int vmid_frame_number)
+ {
+ 	int i = 0;
+ 	struct drr_params params = {0};
+@@ -2754,6 +2755,8 @@ static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
+ 
+ 	params.vertical_total_max = vmax;
+ 	params.vertical_total_min = vmin;
++	params.vertical_total_mid = vmid;
++	params.vertical_total_mid_frame_num = vmid_frame_number;
+ 
+ 	/* TODO: If multiple pipes are to be supported, you need
+ 	 * some GSL stuff. Static screen triggers may be programmed differently
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+index 66d8f6410b53..f3cade20e45c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+@@ -858,6 +858,18 @@ void optc1_set_drr(
+ 		params->vertical_total_max > 0 &&
+ 		params->vertical_total_min > 0) {
+ 
++		if (params->vertical_total_mid != 0) {
++
++			REG_SET(OTG_V_TOTAL_MID, 0,
++				OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
++
++			REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
++					OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
++					OTG_VTOTAL_MID_FRAME_NUM,
++					(uint8_t)params->vertical_total_mid_frame_num);
++
++		}
++
+ 		REG_SET(OTG_V_TOTAL_MAX, 0,
+ 			OTG_V_TOTAL_MAX, params->vertical_total_max - 1);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+index 82d91ab54ba5..83575599672e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+@@ -54,6 +54,7 @@
+ 	SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
+ 	SRI(OTG_STEREO_STATUS, OTG, inst),\
+ 	SRI(OTG_V_TOTAL_MAX, OTG, inst),\
++	SRI(OTG_V_TOTAL_MID, OTG, inst),\
+ 	SRI(OTG_V_TOTAL_MIN, OTG, inst),\
+ 	SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
+ 	SRI(OTG_TRIGA_CNTL, OTG, inst),\
+@@ -125,6 +126,7 @@ struct dcn_optc_registers {
+ 	uint32_t OTG_3D_STRUCTURE_CONTROL;
+ 	uint32_t OTG_STEREO_STATUS;
+ 	uint32_t OTG_V_TOTAL_MAX;
++	uint32_t OTG_V_TOTAL_MID;
+ 	uint32_t OTG_V_TOTAL_MIN;
+ 	uint32_t OTG_V_TOTAL_CONTROL;
+ 	uint32_t OTG_TRIGA_CNTL;
+@@ -214,12 +216,15 @@ struct dcn_optc_registers {
+ 	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
+ 	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
+ 	SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
++	SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\
+ 	SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
+ 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
+ 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
+ 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
+ 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
+ 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
++	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
++	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\
+ 	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
+ 	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
+ 	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
+@@ -348,9 +353,12 @@ struct dcn_optc_registers {
+ 	type OTG_3D_STRUCTURE_V_UPDATE_MODE;\
+ 	type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\
+ 	type OTG_V_TOTAL_MAX;\
++	type OTG_V_TOTAL_MID;\
+ 	type OTG_V_TOTAL_MIN;\
+ 	type OTG_V_TOTAL_MIN_SEL;\
+ 	type OTG_V_TOTAL_MAX_SEL;\
++	type OTG_VTOTAL_MID_REPLACING_MAX_EN;\
++	type OTG_VTOTAL_MID_FRAME_NUM;\
+ 	type OTG_FORCE_LOCK_ON_EVENT;\
+ 	type OTG_SET_V_TOTAL_MIN_MASK_EN;\
+ 	type OTG_SET_V_TOTAL_MIN_MASK;\
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 230a4216c2ae..adad15eb5d12 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -597,6 +597,8 @@ enum dc_status dcn20_enable_stream_timing(
+ 
+ 	params.vertical_total_min = stream->adjust.v_total_min;
+ 	params.vertical_total_max = stream->adjust.v_total_max;
++	params.vertical_total_mid = stream->adjust.v_total_mid;
++	params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
+ 	if (pipe_ctx->stream_res.tg->funcs->set_drr)
+ 		pipe_ctx->stream_res.tg->funcs->set_drr(
+ 			pipe_ctx->stream_res.tg, &params);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+index e0713d6d6c8d..6196cc32356e 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+@@ -59,6 +59,8 @@ struct gsl_params {
+ struct drr_params {
+ 	uint32_t vertical_total_min;
+ 	uint32_t vertical_total_max;
++	uint32_t vertical_total_mid;
++	uint32_t vertical_total_mid_frame_num;
+ 	bool immediate_flip;
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index 68b1185f0636..732a93df1844 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -237,7 +237,8 @@ struct hw_sequencer_funcs {
+ #endif
+ 
+ 	void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
+-			int vmin, int vmax);
++			unsigned int vmin, unsigned int vmax,
++			unsigned int vmid, unsigned int vmid_frame_number);
+ 
+ 	void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
+ 			struct crtc_position *position);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3594-drm-amd-display-Use-res_cap-to-acquire-i2c-instead-o.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3594-drm-amd-display-Use-res_cap-to-acquire-i2c-instead-o.patch
new file mode 100644
index 00000000..e2461550
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3594-drm-amd-display-Use-res_cap-to-acquire-i2c-instead-o.patch
@@ -0,0 +1,44 @@
+From 9bab5696b2902728416cc43423188acb7c8b18ed Mon Sep 17 00:00:00 2001
+From: Derek Lai <Derek.Lai@amd.com>
+Date: Fri, 2 Aug 2019 16:33:32 +0800
+Subject: [PATCH 3594/4256] drm/amd/display: Use res_cap to acquire i2c instead
+ of pipe count
+
+[Why]
+We should be using the ddc_num from res_caps. As the
+pipe count != number of i2c resources.
+
+[How]
+Use ddc_num from res_cap instead of pipe count.
+
+Signed-off-by: Derek Lai <Derek.Lai@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+index caace5229826..0495a1b5dd74 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+@@ -22,6 +22,7 @@
+  * Authors: AMD
+  *
+  */
++#include "resource.h"
+ #include "dce_i2c.h"
+ #include "dce_i2c_hw.h"
+ #include "reg_helper.h"
+@@ -387,7 +388,7 @@ struct dce_i2c_hw *acquire_i2c_hw_engine(
+ 	if (ddc->hw_info.hw_supported) {
+ 		enum gpio_ddc_line line = dal_ddc_get_line(ddc);
+ 
+-		if (line < pool->pipe_count)
++		if (line < pool->res_cap->num_ddc)
+ 			dce_i2c_hw = pool->hw_i2cs[line];
+ 	}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3595-drm-amd-display-revert-wait-in-pipelock.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3595-drm-amd-display-revert-wait-in-pipelock.patch
new file mode 100644
index 00000000..ce143eec
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3595-drm-amd-display-revert-wait-in-pipelock.patch
@@ -0,0 +1,47 @@
+From 4aff55de536255961069b1589637fed28f6dafed Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Tue, 23 Jul 2019 16:56:03 -0400
+Subject: [PATCH 3595/4256] drm/amd/display: revert wait in pipelock
+
+[why]
+Previous workaround to prevent a vsync flip to be converted
+to immediate flip is no longer needed, and is risky because
+there are cases where it can result in infinite loop.
+
+[how]
+Remove wait loop (which is potentially infinite) before locking
+pipe
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 11 -----------
+ 1 file changed, 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index adad15eb5d12..7f9e48566527 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1103,17 +1103,6 @@ void dcn20_pipe_control_lock(
+ 	if (pipe->plane_state != NULL)
+ 		flip_immediate = pipe->plane_state->flip_immediate;
+ 
+-	if (flip_immediate && lock) {
+-		while (pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp))	{
+-			udelay(1);
+-		}
+-
+-		if (pipe->bottom_pipe != NULL)
+-			while (pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp))	{
+-				udelay(1);
+-			}
+-	}
+-
+ 	/* In flip immediate and pipe splitting case, we need to use GSL
+ 	 * for synchronization. Only do setup on locking and on flip type change.
+ 	 */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3596-drm-amd-display-Properly-read-LVTMA_PWRSEQ_CNTL.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3596-drm-amd-display-Properly-read-LVTMA_PWRSEQ_CNTL.patch
new file mode 100644
index 00000000..ae6a02d1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3596-drm-amd-display-Properly-read-LVTMA_PWRSEQ_CNTL.patch
@@ -0,0 +1,131 @@
+From b2fd66dbcd4221d74390739688d35cb2cfb03ee9 Mon Sep 17 00:00:00 2001
+From: Joshua Aberback <joshua.aberback@amd.com>
+Date: Thu, 8 Aug 2019 13:22:36 -0400
+Subject: [PATCH 3596/4256] drm/amd/display: Properly read LVTMA_PWRSEQ_CNTL
+
+[Why]
+The register LVTMA_PWRSEQ_CNTL is used to determine the power state of the
+embedded display. Currently we do not actually read this register's values,
+so during power down we think that this display is already off, so we skip
+calling into VBIOS to actually turn it off.
+
+[How]
+ - add relevant fields to shift / mask initialization
+
+Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dce/dce_hwseq.h    | 43 ++++++++-----------
+ 1 file changed, 17 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+index f62eb2e43d7f..7d93babaa2fb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+@@ -416,36 +416,34 @@ struct dce_hwseq_registers {
+ 	HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\
+ 	HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)
+ 
++#define HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)\
++	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
++	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\
++	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\
++	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
++
+ #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
+ 	.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
+ 	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
+ 	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
+ 	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
+ 	HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\
+-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
+-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
+-	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
++	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
++	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
+ 
+ #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\
+ 	HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
+ 	HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\
+-	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_), \
+-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
+-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
++	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
++	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
+ 
+ #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\
+ 	HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
+ 	SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
+-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
+-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\
+-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\
+-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
+ 	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
+ 
+ #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\
+ 	HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
+-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
+-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
+ 	HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
+ 
+ #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\
+@@ -453,18 +451,15 @@ struct dce_hwseq_registers {
+ 	SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
+ 	SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
+ 	SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
+-	SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh), \
+-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
+-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
++	SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
+ 
+ #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\
+ 	HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\
+ 	HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\
+ 	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
+ 	HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\
+-	HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh), \
+-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
+-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
++	HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh),\
++	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
+ 
+ #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\
+ 	HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\
+@@ -527,10 +522,7 @@ struct dce_hwseq_registers {
+ 	HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\
+ 	HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
+ 	HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
+-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
+-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh), \
+-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh), \
+-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
++	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\
+@@ -591,8 +583,7 @@ struct dce_hwseq_registers {
+ 	HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \
+ 	HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \
+ 	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
+-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
++	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
+ #endif
+ 
+ #define HWSEQ_REG_FIELD_LIST(type) \
+@@ -627,9 +618,9 @@ struct dce_hwseq_registers {
+ 	type ENABLE_L1_TLB;\
+ 	type SYSTEM_ACCESS_MODE;\
+ 	type LVTMA_BLON;\
+-	type LVTMA_PWRSEQ_TARGET_STATE_R;\
+ 	type LVTMA_DIGON;\
+-	type LVTMA_DIGON_OVRD;
++	type LVTMA_DIGON_OVRD;\
++	type LVTMA_PWRSEQ_TARGET_STATE_R;
+ 
+ #define HWSEQ_DCN_REG_FIELD_LIST(type) \
+ 	type HUBP_VTG_SEL; \
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3597-drm-amd-display-flicking-observed-while-installing-d.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3597-drm-amd-display-flicking-observed-while-installing-d.patch
new file mode 100644
index 00000000..b19cc9de
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3597-drm-amd-display-flicking-observed-while-installing-d.patch
@@ -0,0 +1,106 @@
+From 7dd9326342944b266c07c1abcdabb4e01a5a3fd8 Mon Sep 17 00:00:00 2001
+From: hersen wu <hersenxs.wu@amd.com>
+Date: Fri, 2 Aug 2019 16:01:37 -0400
+Subject: [PATCH 3597/4256] drm/amd/display: flicking observed while installing
+ driver on Navi10 CF
+
+[WHY] value of dchub_ref_clock is decided by dchubbub global timer
+settings which is programmed by vbios command table disp_init.
+for multi-GPU case, vbios is posted only for primary GPU. without
+vbios posted for the secondary GPU, value of dchub_ref_clock is not
+set properly. this value will affect dcn bandwidth calcuation and
+cause underflow. user will see screen flicking during driver
+installation for dual GPU case.
+
+[HOW] dc init_hw always call vbios command table disp_init to
+make sure dchubbub global timer is configured and enable.
+
+Signed-off-by: hersen wu <hersenxs.wu@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_resource.c |  1 +
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 54 +++++++++----------
+ 2 files changed, 28 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 6e88cb0fffce..adbf2d4e1723 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -169,6 +169,7 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
+ 	default:
+ 		break;
+ 	}
++
+ 	if (res_pool != NULL) {
+ 		if (dc->ctx->dc_bios->fw_info_valid) {
+ 			res_pool->ref_clocks.xtalin_clock_inKhz =
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index b981ea849cc9..866705ea45a7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1208,34 +1208,34 @@ static void dcn10_init_hw(struct dc *dc)
+ 		return;
+ 	}
+ 
+-	if (!dcb->funcs->is_accelerated_mode(dcb)) {
+-		dc->hwss.bios_golden_init(dc);
+-		if (dc->ctx->dc_bios->fw_info_valid) {
+-			res_pool->ref_clocks.xtalin_clock_inKhz =
+-					dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
+-
+-			if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+-				if (res_pool->dccg && res_pool->hubbub) {
+-
+-					(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+-							dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
+-							&res_pool->ref_clocks.dccg_ref_clock_inKhz);
+-
+-					(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+-							res_pool->ref_clocks.dccg_ref_clock_inKhz,
+-							&res_pool->ref_clocks.dchub_ref_clock_inKhz);
+-				} else {
+-					// Not all ASICs have DCCG sw component
+-					res_pool->ref_clocks.dccg_ref_clock_inKhz =
+-							res_pool->ref_clocks.xtalin_clock_inKhz;
+-					res_pool->ref_clocks.dchub_ref_clock_inKhz =
+-							res_pool->ref_clocks.xtalin_clock_inKhz;
+-				}
+-			}
+-		} else
+-			ASSERT_CRITICAL(false);
++	if (!dcb->funcs->is_accelerated_mode(dcb))
+ 		dc->hwss.disable_vga(dc->hwseq);
+-	}
++
++	dc->hwss.bios_golden_init(dc);
++	if (dc->ctx->dc_bios->fw_info_valid) {
++		res_pool->ref_clocks.xtalin_clock_inKhz =
++				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
++
++		if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
++			if (res_pool->dccg && res_pool->hubbub) {
++
++				(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
++						dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
++						&res_pool->ref_clocks.dccg_ref_clock_inKhz);
++
++				(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
++						res_pool->ref_clocks.dccg_ref_clock_inKhz,
++						&res_pool->ref_clocks.dchub_ref_clock_inKhz);
++			} else {
++				// Not all ASICs have DCCG sw component
++				res_pool->ref_clocks.dccg_ref_clock_inKhz =
++						res_pool->ref_clocks.xtalin_clock_inKhz;
++				res_pool->ref_clocks.dchub_ref_clock_inKhz =
++						res_pool->ref_clocks.xtalin_clock_inKhz;
++			}
++		}
++	} else
++		ASSERT_CRITICAL(false);
+ 
+ 	for (i = 0; i < dc->link_count; i++) {
+ 		/* Power up AND update implementation according to the
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3598-drm-amd-display-3.2.48.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3598-drm-amd-display-3.2.48.patch
new file mode 100644
index 00000000..0387c3d6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3598-drm-amd-display-3.2.48.patch
@@ -0,0 +1,28 @@
+From 1fe9514f65eee7a71c23f0bf1eeb73a8854f43aa Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Mon, 12 Aug 2019 10:05:39 -0400
+Subject: [PATCH 3598/4256] drm/amd/display: 3.2.48
+
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 49bc1e9b3362..dcb2d4505c58 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -42,7 +42,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.47"
++#define DC_VER "3.2.48"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3599-drm-amd-display-fix-calc_pll_max_vco_construct.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3599-drm-amd-display-fix-calc_pll_max_vco_construct.patch
new file mode 100644
index 00000000..cf830e98
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3599-drm-amd-display-fix-calc_pll_max_vco_construct.patch
@@ -0,0 +1,33 @@
+From fff3ef623ffcb61c88f3d50c77af0822936499ce Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Thu, 15 Aug 2019 12:35:39 -0400
+Subject: [PATCH 3599/4256] drm/amd/display: fix calc_pll_max_vco_construct
+
+This was broken by a previous change switching to cached fw_info.
+Fixed by inverting a valid bool check.
+
+Bug: https://bugs.freedesktop.org/show_bug.cgi?id=111432
+Fixes: 9adc8050bf3c ("drm/amd/display: make firmware info only load once during dc_bios create")
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+index 5933a704847e..accae1089b83 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+@@ -1239,7 +1239,7 @@ static bool calc_pll_max_vco_construct(
+ 			init_data->bp == NULL)
+ 		return false;
+ 
+-	if (init_data->bp->fw_info_valid)
++	if (!init_data->bp->fw_info_valid)
+ 		return false;
+ 
+ 	fw_info = &init_data->bp->fw_info;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3600-drm-amdgpu-fix-commit-4ef9d7d.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3600-drm-amdgpu-fix-commit-4ef9d7d.patch
new file mode 100644
index 00000000..d9b5818d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3600-drm-amdgpu-fix-commit-4ef9d7d.patch
@@ -0,0 +1,46 @@
+From 1cee77d072cd911f866a043f52da987e23747b6b Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Tue, 27 Aug 2019 22:59:45 +0800
+Subject: [PATCH 3600/4256] drm/amdgpu: fix commit 4ef9d7d
+
+For picasso(adev->pdev->device == 0x15d8)&raven2(adev->rev_id >= 0x8),
+firmware is sufficient to support gfxoff.
+In commit 4ef9d7dc2db166cbe83fe4621385f034c9347fd2, for picasso&raven2,
+return directly and cause gfxoff disabled.
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 2762ae45f3af..fd7947ef4c24 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -1027,14 +1027,14 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
+ 	case CHIP_VEGA20:
+ 		break;
+ 	case CHIP_RAVEN:
+-		if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
+-			break;
+-		if ((adev->gfx.rlc_fw_version != 106 &&
+-		     adev->gfx.rlc_fw_version < 531) ||
+-		    (adev->gfx.rlc_fw_version == 53815) ||
+-		    (adev->gfx.rlc_feature_version < 1) ||
+-		    !adev->gfx.rlc.is_rlc_v2_1)
++		if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
++			&&((adev->gfx.rlc_fw_version != 106 &&
++			     adev->gfx.rlc_fw_version < 531) ||
++			    (adev->gfx.rlc_fw_version == 53815) ||
++			    (adev->gfx.rlc_feature_version < 1) ||
++			    !adev->gfx.rlc.is_rlc_v2_1))
+ 			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
++
+ 		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+ 			adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
+ 				AMD_PG_SUPPORT_CP |
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3601-drm-amdgpu-enable-vcn-powergating-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3601-drm-amdgpu-enable-vcn-powergating-for-navi12.patch
new file mode 100644
index 00000000..18736939
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3601-drm-amdgpu-enable-vcn-powergating-for-navi12.patch
@@ -0,0 +1,28 @@
+From 4361cb66238929db0117d4b733320c321895cb4a Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Tue, 27 Aug 2019 11:05:23 +0800
+Subject: [PATCH 3601/4256] drm/amdgpu: enable vcn powergating for navi12
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index a3d99f2ddf6b..9eda82d4430e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -649,7 +649,8 @@ static int nv_common_early_init(void *handle)
+ 			AMD_CG_SUPPORT_ATHUB_MGCG |
+ 			AMD_CG_SUPPORT_ATHUB_LS |
+ 			AMD_CG_SUPPORT_VCN_MGCG;
+-		adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
++		adev->pg_flags = AMD_PG_SUPPORT_VCN |
++			AMD_PG_SUPPORT_VCN_DPG;
+ 		adev->external_rev_id = adev->rev_id + 0xa;
+ 		break;
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3602-drm-amdgpu-enable-athub-powergating-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3602-drm-amdgpu-enable-athub-powergating-for-navi12.patch
new file mode 100644
index 00000000..62bf76e9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3602-drm-amdgpu-enable-athub-powergating-for-navi12.patch
@@ -0,0 +1,28 @@
+From 76b2ea64c97075a4ab74a5e84cd6ab284f1ff424 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Tue, 27 Aug 2019 11:06:13 +0800
+Subject: [PATCH 3602/4256] drm/amdgpu: enable athub powergating for navi12
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 9eda82d4430e..384f8f512fc4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -650,7 +650,8 @@ static int nv_common_early_init(void *handle)
+ 			AMD_CG_SUPPORT_ATHUB_LS |
+ 			AMD_CG_SUPPORT_VCN_MGCG;
+ 		adev->pg_flags = AMD_PG_SUPPORT_VCN |
+-			AMD_PG_SUPPORT_VCN_DPG;
++			AMD_PG_SUPPORT_VCN_DPG |
++			AMD_PG_SUPPORT_ATHUB;
+ 		adev->external_rev_id = adev->rev_id + 0xa;
+ 		break;
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3603-drm-amd-powerplay-enable-jpeg-powergating-for-navi1x.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3603-drm-amd-powerplay-enable-jpeg-powergating-for-navi1x.patch
new file mode 100644
index 00000000..cf58c873
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3603-drm-amd-powerplay-enable-jpeg-powergating-for-navi1x.patch
@@ -0,0 +1,31 @@
+From df12932c07a694b428c8a9f098dc8e5cc0b3d809 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Tue, 27 Aug 2019 14:26:08 +0800
+Subject: [PATCH 3603/4256] drm/amd/powerplay: enable jpeg powergating for
+ navi1x
+
+jpeg pg depends on vcn pg
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 462c98f212ee..72ac3ca59983 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -368,7 +368,8 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
+ 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
+ 
+ 	if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
+-		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
++		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT)
++				| FEATURE_MASK(FEATURE_JPEG_PG_BIT);
+ 
+ 	/* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
+ 	if (is_asic_secure(smu)) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3604-drm-amd-powerplay-correct-Vega20-dpm-level-related-s.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3604-drm-amd-powerplay-correct-Vega20-dpm-level-related-s.patch
new file mode 100644
index 00000000..2420eaae
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3604-drm-amd-powerplay-correct-Vega20-dpm-level-related-s.patch
@@ -0,0 +1,118 @@
+From 4a27f10ef0743e5d526c864dad5b9e0c3978be97 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 19 Aug 2019 13:17:53 +0800
+Subject: [PATCH 3604/4256] drm/amd/powerplay: correct Vega20 dpm level related
+ settings
+
+Correct the settings for auto mode and skip the unnecessary
+settings for dcefclk and fclk.
+
+Change-Id: I7e6ca75ce86b4d5cd44920a9fbc71b6f36ea3c49
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c    | 60 +++++++++++++++++--
+ 1 file changed, 54 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+index 98a6f5305974..2f45c624ea5d 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+@@ -2353,12 +2353,16 @@ static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
+ 		data->dpm_table.soc_table.dpm_state.soft_max_level =
+ 		data->dpm_table.soc_table.dpm_levels[soft_level].value;
+ 
+-	ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
++	ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
++						 FEATURE_DPM_UCLK_MASK |
++						 FEATURE_DPM_SOCCLK_MASK);
+ 	PP_ASSERT_WITH_CODE(!ret,
+ 			"Failed to upload boot level to highest!",
+ 			return ret);
+ 
+-	ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
++	ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
++						 FEATURE_DPM_UCLK_MASK |
++						 FEATURE_DPM_SOCCLK_MASK);
+ 	PP_ASSERT_WITH_CODE(!ret,
+ 			"Failed to upload dpm max level to highest!",
+ 			return ret);
+@@ -2391,12 +2395,16 @@ static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
+ 		data->dpm_table.soc_table.dpm_state.soft_max_level =
+ 		data->dpm_table.soc_table.dpm_levels[soft_level].value;
+ 
+-	ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
++	ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
++						 FEATURE_DPM_UCLK_MASK |
++						 FEATURE_DPM_SOCCLK_MASK);
+ 	PP_ASSERT_WITH_CODE(!ret,
+ 			"Failed to upload boot level to highest!",
+ 			return ret);
+ 
+-	ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
++	ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
++						 FEATURE_DPM_UCLK_MASK |
++						 FEATURE_DPM_SOCCLK_MASK);
+ 	PP_ASSERT_WITH_CODE(!ret,
+ 			"Failed to upload dpm max level to highest!",
+ 			return ret);
+@@ -2407,14 +2415,54 @@ static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
+ 
+ static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
+ {
++	struct vega20_hwmgr *data =
++			(struct vega20_hwmgr *)(hwmgr->backend);
++	uint32_t soft_min_level, soft_max_level;
+ 	int ret = 0;
+ 
+-	ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
++	/* gfxclk soft min/max settings */
++	soft_min_level =
++		vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
++	soft_max_level =
++		vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
++
++	data->dpm_table.gfx_table.dpm_state.soft_min_level =
++		data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
++	data->dpm_table.gfx_table.dpm_state.soft_max_level =
++		data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
++
++	/* uclk soft min/max settings */
++	soft_min_level =
++		vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
++	soft_max_level =
++		vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
++
++	data->dpm_table.mem_table.dpm_state.soft_min_level =
++		data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
++	data->dpm_table.mem_table.dpm_state.soft_max_level =
++		data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
++
++	/* socclk soft min/max settings */
++	soft_min_level =
++		vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
++	soft_max_level =
++		vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
++
++	data->dpm_table.soc_table.dpm_state.soft_min_level =
++		data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
++	data->dpm_table.soc_table.dpm_state.soft_max_level =
++		data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
++
++	ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
++						 FEATURE_DPM_UCLK_MASK |
++						 FEATURE_DPM_SOCCLK_MASK);
+ 	PP_ASSERT_WITH_CODE(!ret,
+ 			"Failed to upload DPM Bootup Levels!",
+ 			return ret);
+ 
+-	ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
++	ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
++						 FEATURE_DPM_UCLK_MASK |
++						 FEATURE_DPM_SOCCLK_MASK);
+ 	PP_ASSERT_WITH_CODE(!ret,
+ 			"Failed to upload DPM Max Levels!",
+ 			return ret);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3605-drm-amd-powerplay-correct-the-pp_feature-output-on-A.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3605-drm-amd-powerplay-correct-the-pp_feature-output-on-A.patch
new file mode 100644
index 00000000..c8daf761
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3605-drm-amd-powerplay-correct-the-pp_feature-output-on-A.patch
@@ -0,0 +1,52 @@
+From 1fe99c96453be6dabdbe0e495a19f24ba7c436bf Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Wed, 21 Aug 2019 16:35:12 +0800
+Subject: [PATCH 3605/4256] drm/amd/powerplay: correct the pp_feature output on
+ Arcturus
+
+Fix for the commit below:
+drm/amd/powerplay: implment sysfs feature status function in smu
+
+Change-Id: Id9a373f8d8866b97450be0aef0ba19d0835d40d8
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  | 2 ++
+ drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 1 +
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 9e2c1ce7df1f..595b1365c008 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -141,6 +141,7 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_CO
+ 	FEA_MAP(DPM_SOCCLK),
+ 	FEA_MAP(DPM_FCLK),
+ 	FEA_MAP(DPM_MP0CLK),
++	ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
+ 	FEA_MAP(DS_GFXCLK),
+ 	FEA_MAP(DS_SOCCLK),
+ 	FEA_MAP(DS_LCLK),
+@@ -149,6 +150,7 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_CO
+ 	FEA_MAP(GFX_ULV),
+ 	ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
+ 	FEA_MAP(RSMU_SMN_CG),
++	FEA_MAP(WAFL_CG),
+ 	FEA_MAP(PPT),
+ 	FEA_MAP(TDC),
+ 	FEA_MAP(APCC_PLUS),
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+index 052aecc2827a..b0dd05d431dd 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+@@ -251,6 +251,7 @@ enum smu_clk_type {
+        __SMU_DUMMY_MAP(TEMP_DEPENDENT_VMIN),           	\
+        __SMU_DUMMY_MAP(MMHUB_PG),                      	\
+        __SMU_DUMMY_MAP(ATHUB_PG),                      	\
++       __SMU_DUMMY_MAP(WAFL_CG),
+ 
+ #undef __SMU_DUMMY_MAP
+ #define __SMU_DUMMY_MAP(feature)	SMU_FEATURE_##feature##_BIT
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3606-drm-amdgpu-Export-function-to-flush-TLB-of-specific-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3606-drm-amdgpu-Export-function-to-flush-TLB-of-specific-.patch
new file mode 100644
index 00000000..e76af493
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3606-drm-amdgpu-Export-function-to-flush-TLB-of-specific-.patch
@@ -0,0 +1,362 @@
+From c62e0d203af4a79337b6423b0bd7c236e82f408c Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Thu, 1 Aug 2019 14:55:45 -0500
+Subject: [PATCH 3606/4256] drm/amdgpu: Export function to flush TLB of
+ specific vm hub
+
+This is for kfd to reuse amdgpu TLB invalidation function.
+On gfx10, kfd only needs to flush TLB on gfx hub but not
+on mm hub. So export a function for KFD flush TLB only on
+specific hub.
+
+Change-Id: I00e9afbf58f725345d0248cd6a092553bfa21696
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Reviewed-by: Christian Konig <christian.koenig@amd.com>
+---
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 11 ++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c      |  9 ++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h       |  6 +-
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c        |  5 +-
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c        | 16 +++--
+ drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c         |  6 +-
+ drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c         |  6 +-
+ drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c         |  6 +-
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c         | 72 ++++++++++---------
+ 9 files changed, 81 insertions(+), 56 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+index 8d80e6b7d684..63c71a010865 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+@@ -688,7 +688,7 @@ static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid,
+ int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
+-	int vmid;
++	int vmid, i;
+ 	struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
+ 	uint32_t flush_type = 0;
+ 
+@@ -707,7 +707,9 @@ int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
+ 		if (kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(kgd, vmid)) {
+ 			if (kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(kgd, vmid)
+ 				== pasid) {
+-				amdgpu_gmc_flush_gpu_tlb(adev, vmid, flush_type);
++				for (i = 0; i < adev->num_vmhubs; i++)
++					amdgpu_gmc_flush_gpu_tlb(adev, vmid,
++							i, flush_type);
+ 				break;
+ 			}
+ 		}
+@@ -719,6 +721,7 @@ int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
+ int kgd_gfx_v9_invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
++	int i;
+ 
+ 	if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
+ 		pr_err("non kfd vmid %d\n", vmid);
+@@ -740,7 +743,9 @@ int kgd_gfx_v9_invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
+ 	 * TODO 2: support range-based invalidation, requires kfg2kgd
+ 	 * interface change
+ 	 */
+-	amdgpu_gmc_flush_gpu_tlb(adev, vmid, 0);
++	for (i = 0; i < adev->num_vmhubs; i++)
++		amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
++
+ 	return 0;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+index c040e9f4f5c3..83f4dcb7926c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+@@ -248,7 +248,9 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
+ 	}
+ 	mb();
+ 	amdgpu_asic_flush_hdp(adev, NULL);
+-	amdgpu_gmc_flush_gpu_tlb(adev, 0, 0);
++	for (i = 0; i < adev->num_vmhubs; i++)
++		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
++
+ 	return 0;
+ }
+ 
+@@ -307,7 +309,7 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
+ #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
+ 	unsigned t,p;
+ #endif
+-	int r;
++	int r, i;
+ 
+ 	if (!adev->gart.ready) {
+ 		WARN(1, "trying to bind memory to uninitialized GART !\n");
+@@ -331,7 +333,8 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
+ 
+ 	mb();
+ 	amdgpu_asic_flush_hdp(adev, NULL);
+-	amdgpu_gmc_flush_gpu_tlb(adev, 0, 0);
++	for (i = 0; i < adev->num_vmhubs; i++)
++		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
+ 	return 0;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+index f614ae0302cb..e03351f0ba5a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+@@ -89,8 +89,8 @@ struct amdgpu_vmhub {
+  */
+ struct amdgpu_gmc_funcs {
+ 	/* flush the vm tlb via mmio */
+-	void (*flush_gpu_tlb)(struct amdgpu_device *adev,
+-			      uint32_t vmid, uint32_t flush_type);
++	void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
++				uint32_t vmhub, uint32_t flush_type);
+ 	/* flush the vm tlb via ring */
+ 	uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
+ 				       uint64_t pd_addr);
+@@ -181,7 +181,7 @@ struct amdgpu_gmc {
+ 	struct ras_common_if    *mmhub_ras_if;
+ };
+ 
+-#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, type) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (type))
++#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
+ #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
+ #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
+ #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index d644669e5d93..c72aad8c360a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1736,9 +1736,12 @@ static void gfx_v10_0_init_csb(struct amdgpu_device *adev)
+ 
+ static void gfx_v10_0_init_pg(struct amdgpu_device *adev)
+ {
++	int i;
++
+ 	gfx_v10_0_init_csb(adev);
+ 
+-	amdgpu_gmc_flush_gpu_tlb(adev, 0, 0);
++	for (i = 0; i < adev->num_vmhubs; i++)
++		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
+ 
+ 	/* TODO: init power gating */
+ 	return;
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index ead2d3bf8a8d..d83d8a6a1fc0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -252,8 +252,8 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
+  *
+  * Flush the TLB for the requested page table.
+  */
+-static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev,
+-				    uint32_t vmid, uint32_t flush_type)
++static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
++					uint32_t vmhub, uint32_t flush_type)
+ {
+ 	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+ 	struct dma_fence *fence;
+@@ -266,7 +266,14 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev,
+ 
+ 	mutex_lock(&adev->mman.gtt_window_lock);
+ 
+-	gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
++	if (vmhub == AMDGPU_MMHUB_0) {
++		gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
++		mutex_unlock(&adev->mman.gtt_window_lock);
++		return;
++	}
++
++	BUG_ON(vmhub != AMDGPU_GFXHUB_0);
++
+ 	if (!adev->mman.buffer_funcs_enabled ||
+ 	    !adev->ib_pool_ready ||
+ 	    adev->asic_type > CHIP_NAVI14 ||
+@@ -796,7 +803,8 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
+ 
+ 	gfxhub_v2_0_set_fault_enable_default(adev, value);
+ 	mmhub_v2_0_set_fault_enable_default(adev, value);
+-	gmc_v10_0_flush_gpu_tlb(adev, 0, 0);
++	gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
++	gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
+ 
+ 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+ 		 (unsigned)(adev->gmc.gart_size >> 20),
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+index cdcac811a85f..e60b6a5f170a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+@@ -359,8 +359,8 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
+-static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev,
+-				uint32_t vmid, uint32_t flush_type)
++static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
++					uint32_t vmhub, uint32_t flush_type)
+ {
+ 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
+ }
+@@ -568,7 +568,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
+ 	else
+ 		gmc_v6_0_set_fault_enable_default(adev, true);
+ 
+-	gmc_v6_0_flush_gpu_tlb(adev, 0, 0);
++	gmc_v6_0_flush_gpu_tlb(adev, 0, 0, 0);
+ 	dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
+ 		 (unsigned)(adev->gmc.gart_size >> 20),
+ 		 (unsigned long long)table_addr);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+index 26508a767582..ef628f7b2a0e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+@@ -430,8 +430,8 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
+  *
+  * Flush the TLB for the requested page table (CIK).
+  */
+-static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev,
+-				uint32_t vmid, uint32_t flush_type)
++static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
++					uint32_t vmhub, uint32_t flush_type)
+ {
+ 	/* bits 0-15 are the VM contexts0-15 */
+ 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
+@@ -674,7 +674,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
+ 		WREG32(mmCHUB_CONTROL, tmp);
+ 	}
+ 
+-	gmc_v7_0_flush_gpu_tlb(adev, 0, 0);
++	gmc_v7_0_flush_gpu_tlb(adev, 0, 0, 0);
+ 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+ 		 (unsigned)(adev->gmc.gart_size >> 20),
+ 		 (unsigned long long)table_addr);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+index 43ee4bc47f43..d42610450807 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+@@ -637,8 +637,8 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
+  *
+  * Flush the TLB for the requested page table (VI).
+  */
+-static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev,
+-				uint32_t vmid, uint32_t flush_type)
++static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
++					uint32_t vmhub, uint32_t flush_type)
+ {
+ 	/* bits 0-15 are the VM contexts0-15 */
+ 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
+@@ -923,7 +923,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
+ 	else
+ 		gmc_v8_0_set_fault_enable_default(adev, true);
+ 
+-	gmc_v8_0_flush_gpu_tlb(adev, 0, 0);
++	gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0);
+ 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+ 		 (unsigned)(adev->gmc.gart_size >> 20),
+ 		 (unsigned long long)table_addr);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 746aedb7fb99..57f0498152be 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -452,41 +452,45 @@ static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
+  *
+  * Flush the TLB for the requested page table using certain type.
+  */
+-static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
+-				uint32_t vmid, uint32_t flush_type)
++static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
++					uint32_t vmhub, uint32_t flush_type)
+ {
+ 	const unsigned eng = 17;
+-	unsigned i, j;
+-
+-	for (i = 0; i < adev->num_vmhubs; ++i) {
+-		struct amdgpu_vmhub *hub = &adev->vmhub[i];
+-		u32 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type);
+-
+-		if (adev->gfx.kiq.ring.sched.ready &&
+-		    (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
+-		    !adev->in_gpu_reset) {
+-			uint32_t req = hub->vm_inv_eng0_req + eng;
+-			uint32_t ack = hub->vm_inv_eng0_ack + eng;
+-
+-			amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp,
+-							   1 << vmid);
+-			continue;
+-		}
+-
+-		spin_lock(&adev->gmc.invalidate_lock);
+-		WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
+-		for (j = 0; j < adev->usec_timeout; j++) {
+-			tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
+-			if (tmp & (1 << vmid))
+-				break;
+-			udelay(1);
+-		}
+-		spin_unlock(&adev->gmc.invalidate_lock);
+-		if (j < adev->usec_timeout)
+-			continue;
++	u32 j, tmp;
++	struct amdgpu_vmhub *hub;
+ 
+-		DRM_ERROR("Timeout waiting for VM flush ACK!\n");
++	BUG_ON(vmhub >= adev->num_vmhubs);
++
++	 hub = &adev->vmhub[vmhub];
++	 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type);
++
++  	 /* This is necessary for a HW workaround under SRIOV as well
++         * as GFXOFF under bare metal
++         */
++        if (adev->gfx.kiq.ring.sched.ready &&
++                        (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
++                        !adev->in_gpu_reset) {
++                uint32_t req = hub->vm_inv_eng0_req + eng;
++                uint32_t ack = hub->vm_inv_eng0_ack + eng;
++
++                amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp,
++                                1 << vmid);
++                return;
++        }
++
++        spin_lock(&adev->gmc.invalidate_lock);
++        WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
++        for (j = 0; j < adev->usec_timeout; j++) {
++                tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
++                if (tmp & (1 << vmid))
++                        break;
++                udelay(1);
+ 	}
++        spin_unlock(&adev->gmc.invalidate_lock);
++        if (j < adev->usec_timeout)
++                return;
++
++        DRM_ERROR("Timeout waiting for VM flush ACK!\n");
+ }
+ 
+ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+@@ -1305,7 +1309,7 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
+  */
+ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
+ {
+-	int r;
++	int r, i;
+ 	bool value;
+ 	u32 tmp;
+ 
+@@ -1362,7 +1366,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
+ 		mmhub_v9_4_set_fault_enable_default(adev, value);
+ 	else
+ 		mmhub_v1_0_set_fault_enable_default(adev, value);
+-	gmc_v9_0_flush_gpu_tlb(adev, 0, 0);
++
++	for (i = 0; i < adev->num_vmhubs; ++i)
++		gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
+ 
+ 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+ 		 (unsigned)(adev->gmc.gart_size >> 20),
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3607-drm-amdkfd-gfx10-Calling-amdgpu-functions-to-invalid.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3607-drm-amdkfd-gfx10-Calling-amdgpu-functions-to-invalid.patch
new file mode 100644
index 00000000..2bb5db11
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3607-drm-amdkfd-gfx10-Calling-amdgpu-functions-to-invalid.patch
@@ -0,0 +1,86 @@
+From 43bb6e7a0eb8ef14ee67fa8399d4051941879232 Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Thu, 1 Aug 2019 14:24:42 -0500
+Subject: [PATCH 3607/4256] drm/amdkfd/gfx10: Calling amdgpu functions to
+ invalidate TLB
+
+Calling amdgpu function to invalidate TLB, instead of using a
+kfd implementation. Delete the kfd local TLB invalidation
+implementation.
+
+Change-Id: I569f716179d9a5d8492140c0cd277cd0e56ca054
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Reviewed-by: Christian Konig <christian.koenig@amd.com>
+---
+ .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c    | 41 ++-----------------
+ 1 file changed, 3 insertions(+), 38 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+index 39ffb078beb4..3aff2b5758e0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+@@ -802,42 +802,6 @@ static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
+ 	return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
+ }
+ 
+-static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid)
+-{
+-	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
+-	uint32_t req = (1 << vmid) |
+-		(0 << GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT) |/* legacy */
+-		GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK |
+-		GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK |
+-		GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK |
+-		GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK |
+-		GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK;
+-
+-	mutex_lock(&adev->srbm_mutex);
+-
+-	/* Use light weight invalidation.
+-	 *
+-	 * TODO 1: agree on the right set of invalidation registers for
+-	 * KFD use. Use the last one for now. Invalidate only GCHUB as
+-	 * SDMA is now moved to GCHUB
+-	 *
+-	 * TODO 2: support range-based invalidation, requires kfg2kgd
+-	 * interface change
+-	 */
+-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32),
+-				0xffffffff);
+-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32),
+-				0x0000001f);
+-
+-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ), req);
+-
+-	while (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK)) &
+-					(1 << vmid)))
+-		cpu_relax();
+-
+-	mutex_unlock(&adev->srbm_mutex);
+-}
+-
+ static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid)
+ {
+ 	signed long r;
+@@ -878,7 +842,8 @@ static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
+ 		if (get_atc_vmid_pasid_mapping_valid(kgd, vmid)) {
+ 			if (get_atc_vmid_pasid_mapping_pasid(kgd, vmid)
+ 				== pasid) {
+-				write_vmid_invalidate_request(kgd, vmid);
++				amdgpu_gmc_flush_gpu_tlb(adev, vmid,
++						AMDGPU_GFXHUB_0, 0);
+ 				break;
+ 			}
+ 		}
+@@ -896,7 +861,7 @@ static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
+ 		return 0;
+ 	}
+ 
+-	write_vmid_invalidate_request(kgd, vmid);
++	amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3608-drm-amdgpu-add-dummy-read-for-some-GCVM-status-regis.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3608-drm-amdgpu-add-dummy-read-for-some-GCVM-status-regis.patch
new file mode 100644
index 00000000..b1d8a50e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3608-drm-amdgpu-add-dummy-read-for-some-GCVM-status-regis.patch
@@ -0,0 +1,116 @@
+From cc09164e9f4f8e3a48ccb6d820f953e38c43b372 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Fri, 16 Aug 2019 16:13:28 +0800
+Subject: [PATCH 3608/4256] drm/amdgpu: add dummy read for some GCVM status
+ registers
+
+The GRBM register interface is now capable of bursting 1 cycle per
+register wr->wr, wr->rd much faster than previous muticycle per
+transaction done interface.  This has caused a problem where status
+registers requiring HW to update have a 1 cycle delay, due to the
+register update having to go through GRBM.
+
+SW may operate on an incorrect value if they write a register and
+immediately check the corresponding status register.
+
+Registers requiring HW to clear or set fields may be delayed by 1 cycle.
+For example,
+
+1. write VM_INVALIDATE_ENG0_REQ mask = 5a
+2. read VM_INVALIDATE_ENG0_ACK till the ack is same as the request mask = 5a
+    a. HW will reset VM_INVALIDATE_ENG0_ACK = 0 until invalidation is complete
+3. write VM_INVALIDATE_ENG0_REQ mask = 5a
+4. read VM_INVALIDATE_ENG0_ACK till the ack is same as the request mask = 5a
+    a. First read of VM_INVALIDATE_ENG0_ACK = 5a instead of 0
+    b. Second read of VM_INVALIDATE_ENG0_ACK = 0 because
+       the remote GRBM h/w register takes one extra cycle to be cleared
+    c. In this case, SW will see a false ACK if they exit on first read
+
+Affected registers (only GC variant)  |  Recommended Dummy Read
+--------------------------------------+----------------------------
+VM_INVALIDATE_ENG*_ACK                |  VM_INVALIDATE_ENG*_REQ
+VM_L2_STATUS                          |  VM_L2_STATUS
+VM_L2_PROTECTION_FAULT_STATUS         |  VM_L2_PROTECTION_FAULT_STATUS
+VM_L2_PROTECTION_FAULT_ADDR_HI/LO32   |  VM_L2_PROTECTION_FAULT_ADDR_HI/LO32
+VM_L2_IH_LOG_BUSY                     |  VM_L2_IH_LOG_BUSY
+MC_VM_L2_PERFCOUNTER_HI/LO            |  MC_VM_L2_PERFCOUNTER_HI/LO
+ATC_L2_PERFCOUNTER_HI/LO              |  ATC_L2_PERFCOUNTER_HI/LO
+ATC_L2_PERFCOUNTER2_HI/LO             |  ATC_L2_PERFCOUNTER2_HI/LO
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 15 +++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 16 ++++++++++++++++
+ 2 files changed, 31 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index d83d8a6a1fc0..56f76a1f32ee 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -135,6 +135,14 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
+ 	addr |= ((u64)entry->src_data[1] & 0xf) << 44;
+ 
+ 	if (!amdgpu_sriov_vf(adev)) {
++		/*
++		 * Issue a dummy read to wait for the status register to
++		 * be updated to avoid reading an incorrect value due to
++		 * the new fast GRBM interface.
++		 */
++		if (entry->vmid_src == AMDGPU_GFXHUB_0)
++			RREG32(hub->vm_l2_pro_fault_status);
++
+ 		status = RREG32(hub->vm_l2_pro_fault_status);
+ 		WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
+ 	}
+@@ -228,6 +236,13 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
+ 
+ 	WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
+ 
++	/*
++	 * Issue a dummy read to wait for the ACK register to be cleared
++	 * to avoid a false ACK due to the new fast GRBM interface.
++	 */
++	if (vmhub == AMDGPU_GFXHUB_0)
++		RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
++
+ 	/* Wait for ACK with a delay.*/
+ 	for (i = 0; i < adev->usec_timeout; i++) {
+ 		tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 57f0498152be..a22fbb8fe1a5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -352,6 +352,14 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
+ 
+ 	/* If it's the first fault for this address, process it normally */
+ 	if (!amdgpu_sriov_vf(adev)) {
++		/*
++		 * Issue a dummy read to wait for the status register to
++		 * be updated to avoid reading an incorrect value due to
++		 * the new fast GRBM interface.
++		 */
++		if (entry->vmid_src == AMDGPU_GFXHUB_0)
++			RREG32(hub->vm_l2_pro_fault_status);
++
+ 		status = RREG32(hub->vm_l2_pro_fault_status);
+ 		WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
+ 	}
+@@ -480,6 +488,14 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
+ 
+         spin_lock(&adev->gmc.invalidate_lock);
+         WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
++
++        /*
++         * Issue a dummy read to wait for the ACK register to be cleared
++         * to avoid a false ACK due to the new fast GRBM interface.
++         */
++        if (vmhub == AMDGPU_GFXHUB_0)
++                RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
++
+         for (j = 0; j < adev->usec_timeout; j++) {
+                 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
+                 if (tmp & (1 << vmid))
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3609-drm-amd-display-Fix-error-message.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3609-drm-amd-display-Fix-error-message.patch
new file mode 100644
index 00000000..da02e4a2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3609-drm-amd-display-Fix-error-message.patch
@@ -0,0 +1,35 @@
+From f2d8e9d01bcd4926440af1b18126110562ad4239 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Mon, 26 Aug 2019 10:11:50 -0400
+Subject: [PATCH 3609/4256] drm/amd/display: Fix error message
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Since reservation_object_wait_timeout_rcu is called with
+interruptable set to false it's wrong to say
+'or interrupted' in the error message.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 1171949361af..2addfae05e39 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -5692,7 +5692,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
+ 							false,
+ 							msecs_to_jiffies(5000));
+ 		if (unlikely(r <= 0))
+-			DRM_ERROR("Waiting for fences timed out or interrupted!");
++			DRM_ERROR("Waiting for fences timed out!");
+ 
+ 		/*
+ 		 * TODO This might fail and hence better not used, wait
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3610-drm-amd-powerplay-Fix-an-off-by-one-in-navi10_get_sm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3610-drm-amd-powerplay-Fix-an-off-by-one-in-navi10_get_sm.patch
new file mode 100644
index 00000000..51449e5b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3610-drm-amd-powerplay-Fix-an-off-by-one-in-navi10_get_sm.patch
@@ -0,0 +1,32 @@
+From 52f2f7dedc96a0cfaec4cd56aead0220df7c6460 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Mon, 26 Aug 2019 16:20:12 +0300
+Subject: [PATCH 3610/4256] drm/amd/powerplay: Fix an off by one in
+ navi10_get_smu_msg_index()
+
+The navi10_message_map[] array has SMU_MSG_MAX_COUNT elements so the ">"
+has to be changed to ">=" to prevent reading one element beyond the end
+of the array.
+
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 72ac3ca59983..744b7501c34d 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -212,7 +212,7 @@ static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+ {
+ 	struct smu_11_0_cmn2aisc_mapping mapping;
+ 
+-	if (index > SMU_MSG_MAX_COUNT)
++	if (index >= SMU_MSG_MAX_COUNT)
+ 		return -EINVAL;
+ 
+ 	mapping = navi10_message_map[index];
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3611-drm-amdgpu-display-fix-build-error-without-CONFIG_DR.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3611-drm-amdgpu-display-fix-build-error-without-CONFIG_DR.patch
new file mode 100644
index 00000000..b5b20a5c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3611-drm-amdgpu-display-fix-build-error-without-CONFIG_DR.patch
@@ -0,0 +1,43 @@
+From 74bd7b456233d7bed7dcad79b1bca7ef9e44a7d7 Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Mon, 26 Aug 2019 16:57:07 +0800
+Subject: [PATCH 3611/4256] drm/amdgpu/display: fix build error without
+ CONFIG_DRM_AMD_DC_DSC_SUPPORT
+
+If CONFIG_DRM_AMD_DC_DSC_SUPPORT is not set, build fails:
+
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c: In function dcn20_hw_sequencer_construct:
+drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:2099:28:
+ error: dcn20_dsc_pg_control undeclared (first use in this function); did you mean dcn20_dpp_pg_control?
+  dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
+                            ^~~~~~~~~~~~~~~~~~~~
+                            dcn20_dpp_pg_control
+
+Use CONFIG_DRM_AMD_DC_DSC_SUPPORT to guard this.
+
+Change-Id: I0776fc06774de41cac1c3d600c84e9f133f7fed3
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Fixes: 8a31820b1218 ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot")
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 7f9e48566527..1212da12c414 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -2126,6 +2126,8 @@ void dcn20_hw_sequencer_construct(struct dc *dc)
+ 	dc->hwss.hubp_pg_control = dcn20_hubp_pg_control;
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
++#else
++	dc->hwss.dsc_pg_control = NULL;
+ #endif
+ 	dc->hwss.disable_vga = dcn20_disable_vga;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3612-Revert-drm-amdgpu-free-up-the-first-paging-queue-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3612-Revert-drm-amdgpu-free-up-the-first-paging-queue-v2.patch
new file mode 100644
index 00000000..4a3b44db
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3612-Revert-drm-amdgpu-free-up-the-first-paging-queue-v2.patch
@@ -0,0 +1,68 @@
+From 5a21a50ec5a23aa08ac13d425eafce32464e1bc6 Mon Sep 17 00:00:00 2001
+From: Gang Ba <gaba@amd.com>
+Date: Fri, 23 Aug 2019 16:01:11 -0400
+Subject: [PATCH 3612/4256] Revert "drm/amdgpu: free up the first paging queue
+ v2"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This reverts commit 4f8bc72fbf10f2dc8bca74d5da08b3a981b2e5cd.
+
+It turned out that a single reserved queue wouldn't be
+sufficient for page fault handling.
+
+Change-Id: I577ba236e0571d11400a51f9d95840234aef678a
+Signed-off-by: Gang Ba <gaba@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 23 ++++++++---------------
+ 1 file changed, 8 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index d06371f7791f..b41e21e67791 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -2502,8 +2502,8 @@ static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
+ static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
+ {
+ 	adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
+-	if (adev->sdma.has_page_queue && adev->sdma.num_instances > 1)
+-		adev->mman.buffer_funcs_ring = &adev->sdma.instance[1].page;
++	if (adev->sdma.has_page_queue)
++		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
+ 	else
+ 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+ }
+@@ -2522,22 +2522,15 @@ static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
+ 	unsigned i;
+ 
+ 	adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
+-	if (adev->sdma.has_page_queue && adev->sdma.num_instances > 1) {
+-		for (i = 1; i < adev->sdma.num_instances; i++) {
++	for (i = 0; i < adev->sdma.num_instances; i++) {
++		if (adev->sdma.has_page_queue)
+ 			sched = &adev->sdma.instance[i].page.sched;
+-			adev->vm_manager.vm_pte_rqs[i - 1] =
+-				&sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+-		}
+-		adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances - 1;
+-		adev->vm_manager.page_fault = &adev->sdma.instance[0].page;
+-	} else {
+-		for (i = 0; i < adev->sdma.num_instances; i++) {
++		else
+ 			sched = &adev->sdma.instance[i].ring.sched;
+-			adev->vm_manager.vm_pte_rqs[i] =
+-				&sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+-		}
+-		adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
++		adev->vm_manager.vm_pte_rqs[i] =
++			&sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
+ 	}
++	adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
+ }
+ 
+ const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3613-drm-amdgpu-Add-RAS-EEPROM-table.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3613-drm-amdgpu-Add-RAS-EEPROM-table.patch
new file mode 100644
index 00000000..fe99f57e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3613-drm-amdgpu-Add-RAS-EEPROM-table.patch
@@ -0,0 +1,665 @@
+From 0216baed6eed09b841ac5de85a1459d49ad27d40 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Thu, 30 May 2019 11:01:26 -0400
+Subject: [PATCH 3613/4256] drm/amdgpu: Add RAS EEPROM table.
+
+Add RAS EEPROM table manager to eanble RAS errors to be stored
+upon appearance and retrived on driver load.
+
+v2: Fix some prints.
+
+v3:
+Fix checksum calculation.
+Make table record and header structs packed to do correct byte value sum.
+Fix record crossing EEPROM page boundry.
+
+v4:
+Fix byte sum val calculation for record - look at sizeof(record).
+Fix some style comments.
+
+v5: Add description to EEPROM_TABLE_RECORD_SIZE and syntax fixes.
+
+Change-Id: I274f405ad6e794d108d75d2e61592b4ab290f63f
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Luben Tuikov <Luben.Tuikov@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile           |   3 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h       |   3 +
+ .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c    | 492 ++++++++++++++++++
+ .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h    |  90 ++++
+ 4 files changed, 587 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index 1b74396c6187..cfe189eb496e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -54,7 +54,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
+ 	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
+ 	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
+ 	amdgpu_sem.o amdgpu_gmc.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o \
+-	amdgpu_vm_cpu.o amdgpu_vm_sdma.o amdgpu_discovery.o
++	amdgpu_vm_cpu.o amdgpu_vm_sdma.o amdgpu_pmu.o amdgpu_discovery.o \
++	amdgpu_ras_eeprom.o
+ 
+ amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index 02a51e3dfa14..6c76bb2a6843 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -29,6 +29,7 @@
+ #include "amdgpu.h"
+ #include "amdgpu_psp.h"
+ #include "ta_ras_if.h"
++#include "amdgpu_ras_eeprom.h"
+ 
+ enum amdgpu_ras_block {
+ 	AMDGPU_RAS_BLOCK__UMC = 0,
+@@ -333,6 +334,8 @@ struct amdgpu_ras {
+ 	struct mutex recovery_lock;
+ 
+ 	uint32_t flags;
++
++	struct amdgpu_ras_eeprom_control eeprom_control;
+ };
+ 
+ struct ras_fs_data {
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+new file mode 100644
+index 000000000000..b544e0a05925
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+@@ -0,0 +1,492 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include "amdgpu_ras_eeprom.h"
++#include "amdgpu.h"
++#include "amdgpu_ras.h"
++#include <linux/bits.h>
++
++#define EEPROM_I2C_TARGET_ADDR 0xA0
++
++/*
++ * The 2 macros bellow represent the actual size in bytes that
++ * those entities occupy in the EEPROM memory.
++ * EEPROM_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which
++ * uses uint64 to store 6b fields such as retired_page.
++ */
++#define EEPROM_TABLE_HEADER_SIZE 20
++#define EEPROM_TABLE_RECORD_SIZE 24
++
++#define EEPROM_ADDRESS_SIZE 0x2
++
++/* Table hdr is 'AMDR' */
++#define EEPROM_TABLE_HDR_VAL 0x414d4452
++#define EEPROM_TABLE_VER 0x00010000
++
++/* Assume 2 Mbit size */
++#define EEPROM_SIZE_BYTES 256000
++#define EEPROM_PAGE__SIZE_BYTES 256
++#define EEPROM_HDR_START 0
++#define EEPROM_RECORD_START (EEPROM_HDR_START + EEPROM_TABLE_HEADER_SIZE)
++#define EEPROM_MAX_RECORD_NUM ((EEPROM_SIZE_BYTES - EEPROM_TABLE_HEADER_SIZE) / EEPROM_TABLE_RECORD_SIZE)
++#define EEPROM_ADDR_MSB_MASK GENMASK(17, 8)
++
++#define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev
++
++static void __encode_table_header_to_buff(struct amdgpu_ras_eeprom_table_header *hdr,
++					  unsigned char *buff)
++{
++	uint32_t *pp = (uint32_t *) buff;
++
++	pp[0] = cpu_to_le32(hdr->header);
++	pp[1] = cpu_to_le32(hdr->version);
++	pp[2] = cpu_to_le32(hdr->first_rec_offset);
++	pp[3] = cpu_to_le32(hdr->tbl_size);
++	pp[4] = cpu_to_le32(hdr->checksum);
++}
++
++static void __decode_table_header_from_buff(struct amdgpu_ras_eeprom_table_header *hdr,
++					  unsigned char *buff)
++{
++	uint32_t *pp = (uint32_t *)buff;
++
++	hdr->header 	      = le32_to_cpu(pp[0]);
++	hdr->version 	      = le32_to_cpu(pp[1]);
++	hdr->first_rec_offset = le32_to_cpu(pp[2]);
++	hdr->tbl_size 	      = le32_to_cpu(pp[3]);
++	hdr->checksum 	      = le32_to_cpu(pp[4]);
++}
++
++static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
++				 unsigned char *buff)
++{
++	int ret = 0;
++	struct i2c_msg msg = {
++			.addr	= EEPROM_I2C_TARGET_ADDR,
++			.flags	= 0,
++			.len	= EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
++			.buf	= buff,
++	};
++
++
++	*(uint16_t *)buff = EEPROM_HDR_START;
++	__encode_table_header_to_buff(&control->tbl_hdr, buff + EEPROM_ADDRESS_SIZE);
++
++	ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);
++	if (ret < 1)
++		DRM_ERROR("Failed to write EEPROM table header, ret:%d", ret);
++
++	return ret;
++}
++
++static uint32_t  __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control);
++
++int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
++{
++	int ret = 0;
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++	unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };
++	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
++	struct i2c_msg msg = {
++			.addr	= EEPROM_I2C_TARGET_ADDR,
++			.flags	= I2C_M_RD,
++			.len	= EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
++			.buf	= buff,
++	};
++
++	mutex_init(&control->tbl_mutex);
++
++	switch (adev->asic_type) {
++	case CHIP_VEGA20:
++	/*TODO Add MI-60 */
++		break;
++
++	default:
++		return 0;
++	}
++
++	if (ret) {
++		DRM_ERROR("Failed to init I2C controller, ret:%d", ret);
++		return ret;
++	}
++
++	/* Read/Create table header from EEPROM address 0 */
++	ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);
++	if (ret < 1) {
++		DRM_ERROR("Failed to read EEPROM table header, ret:%d", ret);
++		return ret;
++	}
++
++	__decode_table_header_from_buff(hdr, &buff[2]);
++
++	if (hdr->header == EEPROM_TABLE_HDR_VAL) {
++		control->num_recs = (hdr->tbl_size - EEPROM_TABLE_HEADER_SIZE) /
++				    EEPROM_TABLE_RECORD_SIZE;
++		DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records",
++				 control->num_recs);
++
++	} else {
++		DRM_INFO("Creating new EEPROM table");
++
++		hdr->header = EEPROM_TABLE_HDR_VAL;
++		hdr->version = EEPROM_TABLE_VER;
++		hdr->first_rec_offset = EEPROM_RECORD_START;
++		hdr->tbl_size = EEPROM_TABLE_HEADER_SIZE;
++
++		adev->psp.ras.ras->eeprom_control.tbl_byte_sum =
++				__calc_hdr_byte_sum(&adev->psp.ras.ras->eeprom_control);
++		ret = __update_table_header(control, buff);
++	}
++
++	/* Start inserting records from here */
++	adev->psp.ras.ras->eeprom_control.next_addr = EEPROM_RECORD_START;
++
++	return ret == 1 ? 0 : -EIO;
++}
++
++void amdgpu_ras_eeprom_fini(struct amdgpu_ras_eeprom_control *control)
++{
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++
++	switch (adev->asic_type) {
++	case CHIP_VEGA20:
++		/*TODO Add MI-60 */
++		break;
++
++	default:
++		return;
++	}
++}
++
++static void __encode_table_record_to_buff(struct amdgpu_ras_eeprom_control *control,
++					  struct eeprom_table_record *record,
++					  unsigned char *buff)
++{
++	__le64 tmp = 0;
++	int i = 0;
++
++	/* Next are all record fields according to EEPROM page spec in LE foramt */
++	buff[i++] = record->err_type;
++
++	buff[i++] = record->bank;
++
++	tmp = cpu_to_le64(record->ts);
++	memcpy(buff + i, &tmp, 8);
++	i += 8;
++
++	tmp = cpu_to_le64((record->offset & 0xffffffffffff));
++	memcpy(buff + i, &tmp, 6);
++	i += 6;
++
++	buff[i++] = record->mem_channel;
++	buff[i++] = record->mcumc_id;
++
++	tmp = cpu_to_le64((record->retired_page & 0xffffffffffff));
++	memcpy(buff + i, &tmp, 6);
++}
++
++static void __decode_table_record_from_buff(struct amdgpu_ras_eeprom_control *control,
++					    struct eeprom_table_record *record,
++					    unsigned char *buff)
++{
++	__le64 tmp = 0;
++	int i =  0;
++
++	/* Next are all record fields according to EEPROM page spec in LE foramt */
++	record->err_type = buff[i++];
++
++	record->bank = buff[i++];
++
++	memcpy(&tmp, buff + i, 8);
++	record->ts = le64_to_cpu(tmp);
++	i += 8;
++
++	memcpy(&tmp, buff + i, 6);
++	record->offset = (le64_to_cpu(tmp) & 0xffffffffffff);
++	i += 6;
++
++	buff[i++] = record->mem_channel;
++	buff[i++] = record->mcumc_id;
++
++	memcpy(&tmp, buff + i,  6);
++	record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff);
++}
++
++/*
++ * When reaching end of EEPROM memory jump back to 0 record address
++ * When next record access will go beyond EEPROM page boundary modify bits A17/A8
++ * in I2C selector to go to next page
++ */
++static uint32_t __correct_eeprom_dest_address(uint32_t curr_address)
++{
++	uint32_t next_address = curr_address + EEPROM_TABLE_RECORD_SIZE;
++
++	/* When all EEPROM memory used jump back to 0 address */
++	if (next_address > EEPROM_SIZE_BYTES) {
++		DRM_INFO("Reached end of EEPROM memory, jumping to 0 "
++			 "and overriding old record");
++		return EEPROM_RECORD_START;
++	}
++
++	/*
++	 * To check if we overflow page boundary  compare next address with
++	 * current and see if bits 17/8 of the EEPROM address will change
++	 * If they do start from the next 256b page
++	 *
++	 * https://www.st.com/resource/en/datasheet/m24m02-dr.pdf sec. 5.1.2
++	 */
++	if ((curr_address & EEPROM_ADDR_MSB_MASK) != (next_address & EEPROM_ADDR_MSB_MASK)) {
++		DRM_DEBUG_DRIVER("Reached end of EEPROM memory page, jumpimng to next: %lx",
++				(next_address & EEPROM_ADDR_MSB_MASK));
++
++		return  (next_address & EEPROM_ADDR_MSB_MASK);
++	}
++
++	return curr_address;
++}
++
++
++static uint32_t  __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control)
++{
++	int i;
++	uint32_t tbl_sum = 0;
++
++	/* Header checksum, skip checksum field in the calculation */
++	for (i = 0; i < sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); i++)
++		tbl_sum += *(((unsigned char *)&control->tbl_hdr) + i);
++
++	return tbl_sum;
++}
++
++static uint32_t  __calc_recs_byte_sum(struct eeprom_table_record *records,
++				      int num)
++{
++	int i, j;
++	uint32_t tbl_sum = 0;
++
++	/* Records checksum */
++	for (i = 0; i < num; i++) {
++		struct eeprom_table_record *record = &records[i];
++
++		for (j = 0; j < sizeof(*record); j++) {
++			tbl_sum += *(((unsigned char *)record) + j);
++		}
++	}
++
++	return tbl_sum;
++}
++
++static inline uint32_t  __calc_tbl_byte_sum(struct amdgpu_ras_eeprom_control *control,
++				  struct eeprom_table_record *records, int num)
++{
++	return __calc_hdr_byte_sum(control) + __calc_recs_byte_sum(records, num);
++}
++
++/* Checksum = 256 -((sum of all table entries) mod 256) */
++static void __update_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
++				  struct eeprom_table_record *records, int num,
++				  uint32_t old_hdr_byte_sum)
++{
++	/*
++	 * This will update the table sum with new records.
++	 *
++	 * TODO: What happens when the EEPROM table is to be wrapped around
++	 * and old records from start will get overridden.
++	 */
++
++	/* need to recalculate updated header byte sum */
++	control->tbl_byte_sum -= old_hdr_byte_sum;
++	control->tbl_byte_sum += __calc_tbl_byte_sum(control, records, num);
++
++	control->tbl_hdr.checksum = 256 - (control->tbl_byte_sum % 256);
++}
++
++/* table sum mod 256 + checksum must equals 256 */
++static bool __validate_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
++			    struct eeprom_table_record *records, int num)
++{
++	control->tbl_byte_sum = __calc_tbl_byte_sum(control, records, num);
++
++	if (control->tbl_hdr.checksum + (control->tbl_byte_sum % 256) != 256) {
++		DRM_WARN("Checksum mismatch, checksum: %u ", control->tbl_hdr.checksum);
++		return false;
++	}
++
++	return true;
++}
++
++int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
++					    struct eeprom_table_record *records,
++					    bool write,
++					    int num)
++{
++	int i, ret = 0;
++	struct i2c_msg *msgs;
++	unsigned char *buffs;
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++
++	if (adev->asic_type != CHIP_VEGA20)
++		return 0;
++
++	buffs = kcalloc(num, EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE,
++			 GFP_KERNEL);
++	if (!buffs)
++		return -ENOMEM;
++
++	mutex_lock(&control->tbl_mutex);
++
++	msgs = kcalloc(num, sizeof(*msgs), GFP_KERNEL);
++	if (!msgs) {
++		ret = -ENOMEM;
++		goto free_buff;
++	}
++
++	/* In case of overflow just start from beginning to not lose newest records */
++	if (write && (control->next_addr + EEPROM_TABLE_RECORD_SIZE * num > EEPROM_SIZE_BYTES))
++		control->next_addr = EEPROM_RECORD_START;
++
++
++	/*
++	 * TODO Currently makes EEPROM writes for each record, this creates
++	 * internal fragmentation. Optimized the code to do full page write of
++	 * 256b
++	 */
++	for (i = 0; i < num; i++) {
++		unsigned char *buff = &buffs[i * (EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
++		struct eeprom_table_record *record = &records[i];
++		struct i2c_msg *msg = &msgs[i];
++
++		control->next_addr = __correct_eeprom_dest_address(control->next_addr);
++
++		/*
++		 * Update bits 16,17 of EEPROM address in I2C address by setting them
++		 * to bits 1,2 of Device address byte
++		 */
++		msg->addr = EEPROM_I2C_TARGET_ADDR |
++			       ((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15);
++		msg->flags	= write ? 0 : I2C_M_RD;
++		msg->len	= EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE;
++		msg->buf	= buff;
++
++		/* Insert the EEPROM dest addess, bits 0-15 */
++		buff[0] = ((control->next_addr >> 8) & 0xff);
++		buff[1] = (control->next_addr & 0xff);
++
++		/* EEPROM table content is stored in LE format */
++		if (write)
++			__encode_table_record_to_buff(control, record, buff + EEPROM_ADDRESS_SIZE);
++
++		/*
++		 * The destination EEPROM address might need to be corrected to account
++		 * for page or entire memory wrapping
++		 */
++		control->next_addr += EEPROM_TABLE_RECORD_SIZE;
++	}
++
++	ret = i2c_transfer(&control->eeprom_accessor, msgs, num);
++	if (ret < 1) {
++		DRM_ERROR("Failed to process EEPROM table records, ret:%d", ret);
++
++		/* TODO Restore prev next EEPROM address ? */
++		goto free_msgs;
++	}
++
++
++	if (!write) {
++		for (i = 0; i < num; i++) {
++			unsigned char *buff = &buffs[i*(EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
++			struct eeprom_table_record *record = &records[i];
++
++			__decode_table_record_from_buff(control, record, buff + EEPROM_ADDRESS_SIZE);
++		}
++	}
++
++	if (write) {
++		uint32_t old_hdr_byte_sum = __calc_hdr_byte_sum(control);
++
++		/*
++		 * Update table header with size and CRC and account for table
++		 * wrap around where the assumption is that we treat it as empty
++		 * table
++		 *
++		 * TODO - Check the assumption is correct
++		 */
++		control->num_recs += num;
++		control->num_recs %= EEPROM_MAX_RECORD_NUM;
++		control->tbl_hdr.tbl_size += EEPROM_TABLE_RECORD_SIZE * num;
++		if (control->tbl_hdr.tbl_size > EEPROM_SIZE_BYTES)
++			control->tbl_hdr.tbl_size = EEPROM_TABLE_HEADER_SIZE +
++			control->num_recs * EEPROM_TABLE_RECORD_SIZE;
++
++		__update_tbl_checksum(control, records, num, old_hdr_byte_sum);
++
++		__update_table_header(control, buffs);
++	} else if (!__validate_tbl_checksum(control, records, num)) {
++		DRM_WARN("EEPROM Table checksum mismatch!");
++		/* TODO Uncomment when EEPROM read/write is relliable */
++		/* ret = -EIO; */
++	}
++
++free_msgs:
++	kfree(msgs);
++
++free_buff:
++	kfree(buffs);
++
++	mutex_unlock(&control->tbl_mutex);
++
++	return ret == num ? 0 : -EIO;
++}
++
++/* Used for testing if bugs encountered */
++#if 0
++void amdgpu_ras_eeprom_test(struct amdgpu_ras_eeprom_control *control)
++{
++	int i;
++	struct eeprom_table_record *recs = kcalloc(1, sizeof(*recs), GFP_KERNEL);
++
++	if (!recs)
++		return;
++
++	for (i = 0; i < 1 ; i++) {
++		recs[i].address = 0xdeadbeef;
++		recs[i].retired_page = i;
++	}
++
++	if (!amdgpu_ras_eeprom_process_recods(control, recs, true, 1)) {
++
++		memset(recs, 0, sizeof(*recs) * 1);
++
++		control->next_addr = EEPROM_RECORD_START;
++
++		if (!amdgpu_ras_eeprom_process_recods(control, recs, false, 1)) {
++			for (i = 0; i < 1; i++)
++				DRM_INFO("rec.address :0x%llx, rec.retired_page :%llu",
++					 recs[i].address, recs[i].retired_page);
++		} else
++			DRM_ERROR("Failed in reading from table");
++
++	} else
++		DRM_ERROR("Failed in writing to table");
++}
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
+new file mode 100644
+index 000000000000..41f3fcb9a29b
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
+@@ -0,0 +1,90 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef _AMDGPU_RAS_EEPROM_H
++#define _AMDGPU_RAS_EEPROM_H
++
++#include <linux/i2c.h>
++
++struct amdgpu_device;
++
++enum amdgpu_ras_eeprom_err_type{
++	AMDGPU_RAS_EEPROM_ERR_PLACE_HOLDER,
++	AMDGPU_RAS_EEPROM_ERR_RECOVERABLE,
++	AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE
++};
++
++struct amdgpu_ras_eeprom_table_header {
++	uint32_t header;
++	uint32_t version;
++	uint32_t first_rec_offset;
++	uint32_t tbl_size;
++	uint32_t checksum;
++}__attribute__((__packed__));
++
++struct amdgpu_ras_eeprom_control {
++	struct amdgpu_ras_eeprom_table_header tbl_hdr;
++	struct i2c_adapter eeprom_accessor;
++	uint32_t next_addr;
++	unsigned int num_recs;
++	struct mutex tbl_mutex;
++	bool bus_locked;
++	uint32_t tbl_byte_sum;
++};
++
++/*
++ * Represents single table record. Packed to be easily serialized into byte
++ * stream.
++ */
++struct eeprom_table_record {
++
++	union {
++		uint64_t address;
++		uint64_t offset;
++	};
++
++	uint64_t retired_page;
++	uint64_t ts;
++
++	enum amdgpu_ras_eeprom_err_type err_type;
++
++	union {
++		unsigned char bank;
++		unsigned char cu;
++	};
++
++	unsigned char mem_channel;
++	unsigned char mcumc_id;
++}__attribute__((__packed__));
++
++int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control);
++void amdgpu_ras_eeprom_fini(struct amdgpu_ras_eeprom_control *control);
++
++int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
++					    struct eeprom_table_record *records,
++					    bool write,
++					    int num);
++
++void amdgpu_ras_eeprom_test(struct amdgpu_ras_eeprom_control *control);
++
++#endif // _AMDGPU_RAS_EEPROM_H
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3614-drm-amd-Import-smuio_11_0-headres-for-EEPROM-access-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3614-drm-amd-Import-smuio_11_0-headres-for-EEPROM-access-.patch
new file mode 100644
index 00000000..dd870470
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3614-drm-amd-Import-smuio_11_0-headres-for-EEPROM-access-.patch
@@ -0,0 +1,363 @@
+From 6232b2086762b33c441ca7d7bb03bf2ad407e482 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Tue, 30 Apr 2019 13:58:56 -0400
+Subject: [PATCH 3614/4256] drm/amd: Import smuio_11_0 headres for EEPROM
+ access on Vega20
+
+v3: Merge CKSVII2C_IC regs into exsisting headers.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../asic_reg/smuio/smuio_11_0_0_offset.h      |  92 +++++++
+ .../asic_reg/smuio/smuio_11_0_0_sh_mask.h     | 231 ++++++++++++++++++
+ 2 files changed, 323 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h
+index 5df70484bc7d..d3876052562b 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h
+@@ -29,6 +29,98 @@
+ #define mmSMUSVI0_TEL_PLANE0_BASE_IDX                                                                  0
+ #define mmSMUIO_MCM_CONFIG                                                                             0x0024
+ #define mmSMUIO_MCM_CONFIG_BASE_IDX                                                                    0
++#define mmCKSVII2C_IC_CON                                                                              0x0040
++#define mmCKSVII2C_IC_CON_BASE_IDX                                                                     0
++#define mmCKSVII2C_IC_TAR                                                                              0x0041
++#define mmCKSVII2C_IC_TAR_BASE_IDX                                                                     0
++#define mmCKSVII2C_IC_SAR                                                                              0x0042
++#define mmCKSVII2C_IC_SAR_BASE_IDX                                                                     0
++#define mmCKSVII2C_IC_HS_MADDR                                                                         0x0043
++#define mmCKSVII2C_IC_HS_MADDR_BASE_IDX                                                                0
++#define mmCKSVII2C_IC_DATA_CMD                                                                         0x0044
++#define mmCKSVII2C_IC_DATA_CMD_BASE_IDX                                                                0
++#define mmCKSVII2C_IC_SS_SCL_HCNT                                                                      0x0045
++#define mmCKSVII2C_IC_SS_SCL_HCNT_BASE_IDX                                                             0
++#define mmCKSVII2C_IC_SS_SCL_LCNT                                                                      0x0046
++#define mmCKSVII2C_IC_SS_SCL_LCNT_BASE_IDX                                                             0
++#define mmCKSVII2C_IC_FS_SCL_HCNT                                                                      0x0047
++#define mmCKSVII2C_IC_FS_SCL_HCNT_BASE_IDX                                                             0
++#define mmCKSVII2C_IC_FS_SCL_LCNT                                                                      0x0048
++#define mmCKSVII2C_IC_FS_SCL_LCNT_BASE_IDX                                                             0
++#define mmCKSVII2C_IC_HS_SCL_HCNT                                                                      0x0049
++#define mmCKSVII2C_IC_HS_SCL_HCNT_BASE_IDX                                                             0
++#define mmCKSVII2C_IC_HS_SCL_LCNT                                                                      0x004a
++#define mmCKSVII2C_IC_HS_SCL_LCNT_BASE_IDX                                                             0
++#define mmCKSVII2C_IC_INTR_STAT                                                                        0x004b
++#define mmCKSVII2C_IC_INTR_STAT_BASE_IDX                                                               0
++#define mmCKSVII2C_IC_INTR_MASK                                                                        0x004c
++#define mmCKSVII2C_IC_INTR_MASK_BASE_IDX                                                               0
++#define mmCKSVII2C_IC_RAW_INTR_STAT                                                                    0x004d
++#define mmCKSVII2C_IC_RAW_INTR_STAT_BASE_IDX                                                           0
++#define mmCKSVII2C_IC_RX_TL                                                                            0x004e
++#define mmCKSVII2C_IC_RX_TL_BASE_IDX                                                                   0
++#define mmCKSVII2C_IC_TX_TL                                                                            0x004f
++#define mmCKSVII2C_IC_TX_TL_BASE_IDX                                                                   0
++#define mmCKSVII2C_IC_CLR_INTR                                                                         0x0050
++#define mmCKSVII2C_IC_CLR_INTR_BASE_IDX                                                                0
++#define mmCKSVII2C_IC_CLR_RX_UNDER                                                                     0x0051
++#define mmCKSVII2C_IC_CLR_RX_UNDER_BASE_IDX                                                            0
++#define mmCKSVII2C_IC_CLR_RX_OVER                                                                      0x0052
++#define mmCKSVII2C_IC_CLR_RX_OVER_BASE_IDX                                                             0
++#define mmCKSVII2C_IC_CLR_TX_OVER                                                                      0x0053
++#define mmCKSVII2C_IC_CLR_TX_OVER_BASE_IDX                                                             0
++#define mmCKSVII2C_IC_CLR_RD_REQ                                                                       0x0054
++#define mmCKSVII2C_IC_CLR_RD_REQ_BASE_IDX                                                              0
++#define mmCKSVII2C_IC_CLR_TX_ABRT                                                                      0x0055
++#define mmCKSVII2C_IC_CLR_TX_ABRT_BASE_IDX                                                             0
++#define mmCKSVII2C_IC_CLR_RX_DONE                                                                      0x0056
++#define mmCKSVII2C_IC_CLR_RX_DONE_BASE_IDX                                                             0
++#define mmCKSVII2C_IC_CLR_ACTIVITY                                                                     0x0057
++#define mmCKSVII2C_IC_CLR_ACTIVITY_BASE_IDX                                                            0
++#define mmCKSVII2C_IC_CLR_STOP_DET                                                                     0x0058
++#define mmCKSVII2C_IC_CLR_STOP_DET_BASE_IDX                                                            0
++#define mmCKSVII2C_IC_CLR_START_DET                                                                    0x0059
++#define mmCKSVII2C_IC_CLR_START_DET_BASE_IDX                                                           0
++#define mmCKSVII2C_IC_CLR_GEN_CALL                                                                     0x005a
++#define mmCKSVII2C_IC_CLR_GEN_CALL_BASE_IDX                                                            0
++#define mmCKSVII2C_IC_ENABLE                                                                           0x005b
++#define mmCKSVII2C_IC_ENABLE_BASE_IDX                                                                  0
++#define mmCKSVII2C_IC_STATUS                                                                           0x005c
++#define mmCKSVII2C_IC_STATUS_BASE_IDX                                                                  0
++#define mmCKSVII2C_IC_TXFLR                                                                            0x005d
++#define mmCKSVII2C_IC_TXFLR_BASE_IDX                                                                   0
++#define mmCKSVII2C_IC_RXFLR                                                                            0x005e
++#define mmCKSVII2C_IC_RXFLR_BASE_IDX                                                                   0
++#define mmCKSVII2C_IC_SDA_HOLD                                                                         0x005f
++#define mmCKSVII2C_IC_SDA_HOLD_BASE_IDX                                                                0
++#define mmCKSVII2C_IC_TX_ABRT_SOURCE                                                                   0x0060
++#define mmCKSVII2C_IC_TX_ABRT_SOURCE_BASE_IDX                                                          0
++#define mmCKSVII2C_IC_SLV_DATA_NACK_ONLY                                                               0x0061
++#define mmCKSVII2C_IC_SLV_DATA_NACK_ONLY_BASE_IDX                                                      0
++#define mmCKSVII2C_IC_DMA_CR                                                                           0x0062
++#define mmCKSVII2C_IC_DMA_CR_BASE_IDX                                                                  0
++#define mmCKSVII2C_IC_DMA_TDLR                                                                         0x0063
++#define mmCKSVII2C_IC_DMA_TDLR_BASE_IDX                                                                0
++#define mmCKSVII2C_IC_DMA_RDLR                                                                         0x0064
++#define mmCKSVII2C_IC_DMA_RDLR_BASE_IDX                                                                0
++#define mmCKSVII2C_IC_SDA_SETUP                                                                        0x0065
++#define mmCKSVII2C_IC_SDA_SETUP_BASE_IDX                                                               0
++#define mmCKSVII2C_IC_ACK_GENERAL_CALL                                                                 0x0066
++#define mmCKSVII2C_IC_ACK_GENERAL_CALL_BASE_IDX                                                        0
++#define mmCKSVII2C_IC_ENABLE_STATUS                                                                    0x0067
++#define mmCKSVII2C_IC_ENABLE_STATUS_BASE_IDX                                                           0
++#define mmCKSVII2C_IC_FS_SPKLEN                                                                        0x0068
++#define mmCKSVII2C_IC_FS_SPKLEN_BASE_IDX                                                               0
++#define mmCKSVII2C_IC_HS_SPKLEN                                                                        0x0069
++#define mmCKSVII2C_IC_HS_SPKLEN_BASE_IDX                                                               0
++#define mmCKSVII2C_IC_CLR_RESTART_DET                                                                  0x006a
++#define mmCKSVII2C_IC_CLR_RESTART_DET_BASE_IDX                                                         0
++#define mmCKSVII2C_IC_COMP_PARAM_1                                                                     0x006b
++#define mmCKSVII2C_IC_COMP_PARAM_1_BASE_IDX                                                            0
++#define mmCKSVII2C_IC_COMP_VERSION                                                                     0x006c
++#define mmCKSVII2C_IC_COMP_VERSION_BASE_IDX                                                            0
++#define mmCKSVII2C_IC_COMP_TYPE                                                                        0x006d
++#define mmCKSVII2C_IC_COMP_TYPE_BASE_IDX                                                               0
+ #define mmSMUIO_MP_RESET_INTR                                                                          0x00c1
+ #define mmSMUIO_MP_RESET_INTR_BASE_IDX                                                                 0
+ #define mmSMUIO_SOC_HALT                                                                               0x00c2
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h
+index 237961558e89..f8afa3518bf2 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h
+@@ -37,6 +37,237 @@
+ #define SMUIO_MCM_CONFIG__PKG_TYPE_MASK                                                                       0x0000001CL
+ #define SMUIO_MCM_CONFIG__SOCKET_ID_MASK                                                                      0x00000020L
+ #define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK                                                                    0x000000C0L
++//CKSVII2C_IC_CON
++#define CKSVII2C_IC_CON__IC_MASTER_MODE__SHIFT                                                                0x0
++#define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE__SHIFT                                                             0x1
++#define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE__SHIFT                                                            0x3
++#define CKSVII2C_IC_CON__IC_10BITADDR_MASTER__SHIFT                                                           0x4
++#define CKSVII2C_IC_CON__IC_RESTART_EN__SHIFT                                                                 0x5
++#define CKSVII2C_IC_CON__IC_SLAVE_DISABLE__SHIFT                                                              0x6
++#define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED__SHIFT                                                          0x7
++#define CKSVII2C_IC_CON__TX_EMPTY_CTRL__SHIFT                                                                 0x8
++#define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL__SHIFT                                                         0x9
++#define CKSVII2C_IC_CON__IC_MASTER_MODE_MASK                                                                  0x00000001L
++#define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE_MASK                                                               0x00000006L
++#define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE_MASK                                                              0x00000008L
++#define CKSVII2C_IC_CON__IC_10BITADDR_MASTER_MASK                                                             0x00000010L
++#define CKSVII2C_IC_CON__IC_RESTART_EN_MASK                                                                   0x00000020L
++#define CKSVII2C_IC_CON__IC_SLAVE_DISABLE_MASK                                                                0x00000040L
++#define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED_MASK                                                            0x00000080L
++#define CKSVII2C_IC_CON__TX_EMPTY_CTRL_MASK                                                                   0x00000100L
++#define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL_MASK                                                           0x00000200L
++//CKSVII2C_IC_TAR
++#define CKSVII2C_IC_TAR__IC_TAR__SHIFT                                                                        0x0
++#define CKSVII2C_IC_TAR__GC_OR_START__SHIFT                                                                   0xa
++#define CKSVII2C_IC_TAR__SPECIAL__SHIFT                                                                       0xb
++#define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER__SHIFT                                                           0xc
++#define CKSVII2C_IC_TAR__IC_TAR_MASK                                                                          0x000003FFL
++#define CKSVII2C_IC_TAR__GC_OR_START_MASK                                                                     0x00000400L
++#define CKSVII2C_IC_TAR__SPECIAL_MASK                                                                         0x00000800L
++#define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER_MASK                                                             0x00001000L
++//CKSVII2C_IC_SAR
++#define CKSVII2C_IC_SAR__IC_SAR__SHIFT                                                                        0x0
++#define CKSVII2C_IC_SAR__IC_SAR_MASK                                                                          0x000003FFL
++//CKSVII2C_IC_HS_MADDR
++#define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR__SHIFT                                                              0x0
++#define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR_MASK                                                                0x00000007L
++//CKSVII2C_IC_DATA_CMD
++#define CKSVII2C_IC_DATA_CMD__DAT__SHIFT                                                                      0x0
++#define CKSVII2C_IC_DATA_CMD__CMD__SHIFT                                                                      0x8
++#define CKSVII2C_IC_DATA_CMD__STOP__SHIFT                                                                     0x9
++#define CKSVII2C_IC_DATA_CMD__RESTART__SHIFT                                                                  0xa
++#define CKSVII2C_IC_DATA_CMD__DAT_MASK                                                                        0x000000FFL
++#define CKSVII2C_IC_DATA_CMD__CMD_MASK                                                                        0x00000100L
++#define CKSVII2C_IC_DATA_CMD__STOP_MASK                                                                       0x00000200L
++#define CKSVII2C_IC_DATA_CMD__RESTART_MASK                                                                    0x00000400L
++//CKSVII2C_IC_SS_SCL_HCNT
++#define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT__SHIFT                                                        0x0
++#define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT_MASK                                                          0x0000FFFFL
++//CKSVII2C_IC_SS_SCL_LCNT
++#define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT__SHIFT                                                        0x0
++#define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT_MASK                                                          0x0000FFFFL
++//CKSVII2C_IC_FS_SCL_HCNT
++#define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT__SHIFT                                                        0x0
++#define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT_MASK                                                          0x0000FFFFL
++//CKSVII2C_IC_FS_SCL_LCNT
++#define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT__SHIFT                                                        0x0
++#define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT_MASK                                                          0x0000FFFFL
++//CKSVII2C_IC_HS_SCL_HCNT
++#define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT__SHIFT                                                        0x0
++#define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT_MASK                                                          0x0000FFFFL
++//CKSVII2C_IC_HS_SCL_LCNT
++#define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT__SHIFT                                                        0x0
++#define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT_MASK                                                          0x0000FFFFL
++//CKSVII2C_IC_INTR_STAT
++#define CKSVII2C_IC_INTR_STAT__R_RX_UNDER__SHIFT                                                              0x0
++#define CKSVII2C_IC_INTR_STAT__R_RX_OVER__SHIFT                                                               0x1
++#define CKSVII2C_IC_INTR_STAT__R_RX_FULL__SHIFT                                                               0x2
++#define CKSVII2C_IC_INTR_STAT__R_TX_OVER__SHIFT                                                               0x3
++#define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY__SHIFT                                                              0x4
++#define CKSVII2C_IC_INTR_STAT__R_RD_REQ__SHIFT                                                                0x5
++#define CKSVII2C_IC_INTR_STAT__R_TX_ABRT__SHIFT                                                               0x6
++#define CKSVII2C_IC_INTR_STAT__R_RX_DONE__SHIFT                                                               0x7
++#define CKSVII2C_IC_INTR_STAT__R_ACTIVITY__SHIFT                                                              0x8
++#define CKSVII2C_IC_INTR_STAT__R_STOP_DET__SHIFT                                                              0x9
++#define CKSVII2C_IC_INTR_STAT__R_START_DET__SHIFT                                                             0xa
++#define CKSVII2C_IC_INTR_STAT__R_GEN_CALL__SHIFT                                                              0xb
++#define CKSVII2C_IC_INTR_STAT__R_RESTART_DET__SHIFT                                                           0xc
++#define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD__SHIFT                                                           0xd
++#define CKSVII2C_IC_INTR_STAT__R_RX_UNDER_MASK                                                                0x00000001L
++#define CKSVII2C_IC_INTR_STAT__R_RX_OVER_MASK                                                                 0x00000002L
++#define CKSVII2C_IC_INTR_STAT__R_RX_FULL_MASK                                                                 0x00000004L
++#define CKSVII2C_IC_INTR_STAT__R_TX_OVER_MASK                                                                 0x00000008L
++#define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY_MASK                                                                0x00000010L
++#define CKSVII2C_IC_INTR_STAT__R_RD_REQ_MASK                                                                  0x00000020L
++#define CKSVII2C_IC_INTR_STAT__R_TX_ABRT_MASK                                                                 0x00000040L
++#define CKSVII2C_IC_INTR_STAT__R_RX_DONE_MASK                                                                 0x00000080L
++#define CKSVII2C_IC_INTR_STAT__R_ACTIVITY_MASK                                                                0x00000100L
++#define CKSVII2C_IC_INTR_STAT__R_STOP_DET_MASK                                                                0x00000200L
++#define CKSVII2C_IC_INTR_STAT__R_START_DET_MASK                                                               0x00000400L
++#define CKSVII2C_IC_INTR_STAT__R_GEN_CALL_MASK                                                                0x00000800L
++#define CKSVII2C_IC_INTR_STAT__R_RESTART_DET_MASK                                                             0x00001000L
++#define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD_MASK                                                             0x00002000L
++//CKSVII2C_IC_INTR_MASK
++#define CKSVII2C_IC_INTR_MASK__M_RX_UNDER__SHIFT                                                              0x0
++#define CKSVII2C_IC_INTR_MASK__M_RX_OVER__SHIFT                                                               0x1
++#define CKSVII2C_IC_INTR_MASK__M_RX_FULL__SHIFT                                                               0x2
++#define CKSVII2C_IC_INTR_MASK__M_TX_OVER__SHIFT                                                               0x3
++#define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY__SHIFT                                                              0x4
++#define CKSVII2C_IC_INTR_MASK__M_RD_REQ__SHIFT                                                                0x5
++#define CKSVII2C_IC_INTR_MASK__M_TX_ABRT__SHIFT                                                               0x6
++#define CKSVII2C_IC_INTR_MASK__M_RX_DONE__SHIFT                                                               0x7
++#define CKSVII2C_IC_INTR_MASK__M_ACTIVITY__SHIFT                                                              0x8
++#define CKSVII2C_IC_INTR_MASK__M_STOP_DET__SHIFT                                                              0x9
++#define CKSVII2C_IC_INTR_MASK__M_START_DET__SHIFT                                                             0xa
++#define CKSVII2C_IC_INTR_MASK__M_GEN_CALL__SHIFT                                                              0xb
++#define CKSVII2C_IC_INTR_MASK__M_RESTART_DET__SHIFT                                                           0xc
++#define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD__SHIFT                                                           0xd
++#define CKSVII2C_IC_INTR_MASK__M_RX_UNDER_MASK                                                                0x00000001L
++#define CKSVII2C_IC_INTR_MASK__M_RX_OVER_MASK                                                                 0x00000002L
++#define CKSVII2C_IC_INTR_MASK__M_RX_FULL_MASK                                                                 0x00000004L
++#define CKSVII2C_IC_INTR_MASK__M_TX_OVER_MASK                                                                 0x00000008L
++#define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY_MASK                                                                0x00000010L
++#define CKSVII2C_IC_INTR_MASK__M_RD_REQ_MASK                                                                  0x00000020L
++#define CKSVII2C_IC_INTR_MASK__M_TX_ABRT_MASK                                                                 0x00000040L
++#define CKSVII2C_IC_INTR_MASK__M_RX_DONE_MASK                                                                 0x00000080L
++#define CKSVII2C_IC_INTR_MASK__M_ACTIVITY_MASK                                                                0x00000100L
++#define CKSVII2C_IC_INTR_MASK__M_STOP_DET_MASK                                                                0x00000200L
++#define CKSVII2C_IC_INTR_MASK__M_START_DET_MASK                                                               0x00000400L
++#define CKSVII2C_IC_INTR_MASK__M_GEN_CALL_MASK                                                                0x00000800L
++#define CKSVII2C_IC_INTR_MASK__M_RESTART_DET_MASK                                                             0x00001000L
++#define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD_MASK                                                             0x00002000L
++//CKSVII2C_IC_RAW_INTR_STAT
++#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_UNDER__SHIFT                                                              0x0
++#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_OVER__SHIFT                                                               0x1
++#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_FULL__SHIFT                                                               0x2
++#define CKSVII2C_IC_RAW_INTR_STAT__R_TX_OVER__SHIFT                                                               0x3
++#define CKSVII2C_IC__RAW_INTR_STAT__R_TX_EMPTY__SHIFT                                                              0x4
++#define CKSVII2C_IC_RAW_INTR_STAT__R_RD_REQ__SHIFT                                                                0x5
++#define CKSVII2C_IC_RAW_INTR_STAT__R_TX_ABRT__SHIFT                                                               0x6
++#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_DONE__SHIFT                                                               0x7
++#define CKSVII2C_IC_RAW_INTR_STAT__R_ACTIVITY__SHIFT                                                              0x8
++#define CKSVII2C_IC_RAW_INTR_STAT__R_STOP_DET__SHIFT                                                              0x9
++#define CKSVII2C_IC_RAW_INTR_STAT__R_START_DET__SHIFT                                                             0xa
++#define CKSVII2C_IC_RAW_INTR_STAT__R_GEN_CALL__SHIFT                                                              0xb
++#define CKSVII2C_IC_RAW_INTR_STAT__R_RESTART_DET__SHIFT                                                           0xc
++#define CKSVII2C_IC_RAW_INTR_STAT__R_MST_ON_HOLD__SHIFT                                                           0xd
++#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_UNDER_MASK                                                                0x00000001L
++#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_OVER_MASK                                                                 0x00000002L
++#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_FULL_MASK                                                                 0x00000004L
++#define CKSVII2C_IC_RAW_INTR_STAT__R_TX_OVER_MASK                                                                 0x00000008L
++#define CKSVII2C_IC_RAW_INTR_STAT__R_TX_EMPTY_MASK                                                                0x00000010L
++#define CKSVII2C_IC_RAW_INTR_STAT__R_RD_REQ_MASK                                                                  0x00000020L
++#define CKSVII2C_IC_RAW_INTR_STAT__R_TX_ABRT_MASK                                                                 0x00000040L
++#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_DONE_MASK                                                                 0x00000080L
++#define CKSVII2C_IC_RAW_INTR_STAT__R_ACTIVITY_MASK                                                                0x00000100L
++#define CKSVII2C_IC_RAW_INTR_STAT__R_STOP_DET_MASK                                                                0x00000200L
++#define CKSVII2C_IC_RAW_INTR_STAT__R_START_DET_MASK                                                               0x00000400L
++#define CKSVII2C_IC_RAW_INTR_STAT__R_GEN_CALL_MASK                                                                0x00000800L
++#define CKSVII2C_IC_RAW_INTR_STAT__R_RESTART_DET_MASK                                                             0x00001000L
++#define CKSVII2C_IC_RAW_INTR_STAT__R_MST_ON_HOLD_MASK                                                             0x00002000L
++//CKSVII2C_IC_RX_TL
++//CKSVII2C_IC_TX_TL
++//CKSVII2C_IC_CLR_INTR
++//CKSVII2C_IC_CLR_RX_UNDER
++//CKSVII2C_IC_CLR_RX_OVER
++//CKSVII2C_IC_CLR_TX_OVER
++//CKSVII2C_IC_CLR_RD_REQ
++//CKSVII2C_IC_CLR_TX_ABRT
++//CKSVII2C_IC_CLR_RX_DONE
++//CKSVII2C_IC_CLR_ACTIVITY
++#define CKSVII2C_IC_CLR_ACTIVITY__CLR_ACTIVITY__SHIFT                                                         0x0
++#define CKSVII2C_IC_CLR_ACTIVITY__CLR_ACTIVITY_MASK                                                           0x00000001L
++//CKSVII2C_IC_CLR_STOP_DET
++//CKSVII2C_IC_CLR_START_DET
++//CKSVII2C_IC_CLR_GEN_CALL
++//CKSVII2C_IC_ENABLE
++#define CKSVII2C_IC_ENABLE__ENABLE__SHIFT                                                                     0x0
++#define CKSVII2C_IC_ENABLE__ABORT__SHIFT                                                                      0x1
++#define CKSVII2C_IC_ENABLE__ENABLE_MASK                                                                       0x00000001L
++#define CKSVII2C_IC_ENABLE__ABORT_MASK                                                                        0x00000002L
++//CKSVII2C_IC_STATUS
++#define CKSVII2C_IC_STATUS__ACTIVITY__SHIFT                                                                   0x0
++#define CKSVII2C_IC_STATUS__TFNF__SHIFT                                                                       0x1
++#define CKSVII2C_IC_STATUS__TFE__SHIFT                                                                        0x2
++#define CKSVII2C_IC_STATUS__RFNE__SHIFT                                                                       0x3
++#define CKSVII2C_IC_STATUS__RFF__SHIFT                                                                        0x4
++#define CKSVII2C_IC_STATUS__MST_ACTIVITY__SHIFT                                                               0x5
++#define CKSVII2C_IC_STATUS__SLV_ACTIVITY__SHIFT                                                               0x6
++#define CKSVII2C_IC_STATUS__ACTIVITY_MASK                                                                     0x00000001L
++#define CKSVII2C_IC_STATUS__TFNF_MASK                                                                         0x00000002L
++#define CKSVII2C_IC_STATUS__TFE_MASK                                                                          0x00000004L
++#define CKSVII2C_IC_STATUS__RFNE_MASK                                                                         0x00000008L
++#define CKSVII2C_IC_STATUS__RFF_MASK                                                                          0x00000010L
++#define CKSVII2C_IC_STATUS__MST_ACTIVITY_MASK                                                                 0x00000020L
++#define CKSVII2C_IC_STATUS__SLV_ACTIVITY_MASK                                                                 0x00000040L
++//CKSVII2C_IC_TXFLR
++//CKSVII2C_IC_RXFLR
++//CKSVII2C_IC_SDA_HOLD
++#define CKSVII2C_IC_SDA_HOLD__IC_SDA_HOLD__SHIFT                                                              0x0
++#define CKSVII2C_IC_SDA_HOLD__IC_SDA_HOLD_MASK                                                                0x00FFFFFFL
++//CKSVII2C_IC_TX_ABRT_SOURCE
++
++#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_7B_ADDR_NOACK__SHIFT                                                  0x0
++#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR1_NOACK__SHIFT                                                  0x1
++#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR2_NOACK__SHIFT                                                  0x2
++#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_TXDATA_NOACK__SHIFT                                                   0x3
++#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_7B_ADDR_NOACK_MASK                                                   0x00000001L
++#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR1_NOACK_MASK                                                   0x00000002L
++#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR2_NOACK_MASK                                                   0x00000004L
++#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_TXDATA_NOACK_MASK                                                    0x00000008L
++//CKSVII2C_IC_SLV_DATA_NACK_ONLY
++//CKSVII2C_IC_DMA_CR
++//CKSVII2C_IC_DMA_TDLR
++//CKSVII2C_IC_DMA_RDLR
++//CKSVII2C_IC_SDA_SETUP
++#define CKSVII2C_IC_SDA_SETUP__SDA_SETUP__SHIFT                                                               0x0
++#define CKSVII2C_IC_SDA_SETUP__SDA_SETUP_MASK                                                                 0x000000FFL
++//CKSVII2C_IC_ACK_GENERAL_CALL
++#define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL__SHIFT                                                 0x0
++#define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL_MASK                                                   0x00000001L
++//CKSVII2C_IC_ENABLE_STATUS
++#define CKSVII2C_IC_ENABLE_STATUS__IC_EN__SHIFT                                                               0x0
++#define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_ABORTED__SHIFT                                                      0x1
++#define CKSVII2C_IC_ENABLE_STATUS__SLV_FIFO_FILLED_AND_FLUSHED__SHIFT                                         0x2
++#define CKSVII2C_IC_ENABLE_STATUS__IC_EN_MASK                                                                 0x00000001L
++#define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_ABORTED_MASK                                                        0x00000002L
++#define CKSVII2C_IC_ENABLE_STATUS__SLV_FIFO_FILLED_AND_FLUSHED_MASK                                           0x00000004L
++//CKSVII2C_IC_FS_SPKLEN
++#define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN__SHIFT                                                               0x0
++#define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN_MASK                                                                 0x000000FFL
++//CKSVII2C_IC_HS_SPKLEN
++#define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN__SHIFT                                                               0x0
++#define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN_MASK                                                                 0x000000FFL
++//CKSVII2C_IC_CLR_RESTART_DET
++//CKSVII2C_IC_COMP_PARAM_1
++#define CKSVII2C_IC_COMP_PARAM_1__COMP_PARAM_1__SHIFT                                                         0x0
++#define CKSVII2C_IC_COMP_PARAM_1__COMP_PARAM_1_MASK                                                           0xFFFFFFFFL
++//CKSVII2C_IC_COMP_VERSION
++#define CKSVII2C_IC_COMP_VERSION__COMP_VERSION__SHIFT                                                         0x0
++#define CKSVII2C_IC_COMP_VERSION__COMP_VERSION_MASK                                                           0xFFFFFFFFL
++//CKSVII2C_IC_COMP_TYPE
++#define CKSVII2C_IC_COMP_TYPE__COMP_TYPE__SHIFT                                                               0x0
++#define CKSVII2C_IC_COMP_TYPE__COMP_TYPE_MASK                                                                 0xFFFFFFFFL
+ //SMUIO_MP_RESET_INTR
+ #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT                                                       0x0
+ #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK                                                         0x00000001L
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3615-drm-amd-powerplay-Add-interface-to-lock-SMU-HW-I2C.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3615-drm-amd-powerplay-Add-interface-to-lock-SMU-HW-I2C.patch
new file mode 100644
index 00000000..d354430a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3615-drm-amd-powerplay-Add-interface-to-lock-SMU-HW-I2C.patch
@@ -0,0 +1,151 @@
+From 8b238e7e571bf9de964c031acc661e932fa3ccdd Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Wed, 1 May 2019 18:19:48 -0400
+Subject: [PATCH 3615/4256] drm/amd/powerplay: Add interface to lock SMU HW
+ I2C.
+
+v2:
+PPSMC_MSG_RequestI2CBus seems not to work and so to avoid conflict
+over I2C bus and engine disable thermal control access to
+force SMU stop using the I2C bus until the issue is reslolved.
+
+Expose and call vega20_is_smc_ram_running to skip locking when SMU
+FW is not yet loaded.
+
+v3:
+Remove the prevoius hack as the SMU found the bug.
+
+v5: Typo fix
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/include/kgd_pp_interface.h    |  1 +
+ drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 16 ++++++++++++++++
+ .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c    | 19 +++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/inc/hwmgr.h     |  1 +
+ .../drm/amd/powerplay/smumgr/vega20_smumgr.c  |  2 +-
+ .../drm/amd/powerplay/smumgr/vega20_smumgr.h  |  2 ++
+ 6 files changed, 40 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+index 0de4e37fe7da..27cf0afaa0b4 100644
+--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
++++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+@@ -275,6 +275,7 @@ struct amd_pm_funcs {
+ 	int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
+ 	int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
+ 	int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
++	int (*smu_i2c_bus_access)(void *handle, bool acquire);
+ /* export to DC */
+ 	u32 (*get_sclk)(void *handle, bool low);
+ 	u32 (*get_mclk)(void *handle, bool low);
+diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+index 7ef202761998..fa636cb462c1 100644
+--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+@@ -1528,6 +1528,21 @@ static int pp_asic_reset_mode_2(void *handle)
+ 	return ret;
+ }
+ 
++static int pp_smu_i2c_bus_access(void *handle, bool acquire)
++{
++	struct pp_hwmgr *hwmgr = handle;
++
++	if (!hwmgr || !hwmgr->pm_en)
++		return -EINVAL;
++
++	if (hwmgr->hwmgr_func->smu_i2c_bus_access == NULL) {
++		pr_info_ratelimited("%s was not implemented.\n", __func__);
++		return -EINVAL;
++	}
++
++	return hwmgr->hwmgr_func->smu_i2c_bus_access(hwmgr, acquire);
++}
++
+ static const struct amd_pm_funcs pp_dpm_funcs = {
+ 	.load_firmware = pp_dpm_load_fw,
+ 	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
+@@ -1585,4 +1600,5 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
+ 	.get_ppfeature_status = pp_get_ppfeature_status,
+ 	.set_ppfeature_status = pp_set_ppfeature_status,
+ 	.asic_reset_mode_2 = pp_asic_reset_mode_2,
++	.smu_i2c_bus_access = pp_smu_i2c_bus_access,
+ };
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+index 2f45c624ea5d..f5915308e643 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+@@ -4137,6 +4137,24 @@ static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
+ 	return 0;
+ }
+ 
++static int vega20_smu_i2c_bus_access(struct pp_hwmgr *hwmgr, bool acquire)
++{
++	int res;
++
++	/* I2C bus access can happen very early, when SMU not loaded yet */
++	if (!vega20_is_smc_ram_running(hwmgr))
++		return 0;
++
++	res = smum_send_msg_to_smc_with_parameter(hwmgr,
++						  (acquire ?
++						  PPSMC_MSG_RequestI2CBus :
++						  PPSMC_MSG_ReleaseI2CBus),
++						  0);
++
++	PP_ASSERT_WITH_CODE(!res, "[SmuI2CAccessBus] Failed to access bus!", return res);
++	return res;
++}
++
+ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
+ 	/* init/fini related */
+ 	.backend_init = vega20_hwmgr_backend_init,
+@@ -4204,6 +4222,7 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
+ 	.get_asic_baco_state = vega20_baco_get_state,
+ 	.set_asic_baco_state = vega20_baco_set_state,
+ 	.set_mp1_state = vega20_set_mp1_state,
++	.smu_i2c_bus_access = vega20_smu_i2c_bus_access,
+ };
+ 
+ int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+index abeff1570277..7bf9a14bfa0b 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+@@ -354,6 +354,7 @@ struct pp_hwmgr_func {
+ 	int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
+ 	int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
+ 	int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
++	int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire);
+ };
+ 
+ struct pp_table_func {
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
+index 3e97b83950dc..b9089c6bea85 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
+@@ -44,7 +44,7 @@
+ #define smnMP0_FW_INTF			0x30101c0
+ #define smnMP1_PUB_CTRL			0x3010b14
+ 
+-static bool vega20_is_smc_ram_running(struct pp_hwmgr *hwmgr)
++bool vega20_is_smc_ram_running(struct pp_hwmgr *hwmgr)
+ {
+ 	struct amdgpu_device *adev = hwmgr->adev;
+ 	uint32_t mp1_fw_flags;
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h
+index ec953ab13e87..62ebbfd6068f 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h
+@@ -57,5 +57,7 @@ int vega20_get_activity_monitor_coeff(struct pp_hwmgr *hwmgr,
+ 		uint8_t *table, uint16_t workload_type);
+ int vega20_set_pptable_driver_address(struct pp_hwmgr *hwmgr);
+ 
++bool vega20_is_smc_ram_running(struct pp_hwmgr *hwmgr);
++
+ #endif
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3616-drm-amdgpu-Vega20-SMU-I2C-HW-engine-controller.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3616-drm-amdgpu-Vega20-SMU-I2C-HW-engine-controller.patch
new file mode 100644
index 00000000..45dcbe48
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3616-drm-amdgpu-Vega20-SMU-I2C-HW-engine-controller.patch
@@ -0,0 +1,850 @@
+From 9df429b152be558cbeb9f2cc43e0913c7361b8b7 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Wed, 1 May 2019 10:57:14 -0400
+Subject: [PATCH 3616/4256] drm/amdgpu: Vega20 SMU I2C HW engine controller.
+
+Implement HW I2C enigne controller to be used by the RAS EEPROM
+table manager. This is based on code from ATITOOLs.
+
+v2:
+Rename the file and all function prefixes to smu_v11_0_i2c
+
+By Luben's observation always fill the TX fifo to full so
+we don't have garbadge interpreted by the slave as valid data.
+
+v3:
+Remove preemption disable as the HW I2C controller will not
+stop the clock on empty TX fifo and so it's not critical to
+keep not empty queue.
+Switch to fast mode 400 khz SCL clock for faster read and write.
+
+v5:
+Restore clock gating before releasing I2C bus and fix some
+style comments.
+
+Change-Id: Ie309850d274d42223614eb8dc2ba80dbaff59d28
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Luben Tuikov <Luben.Tuikov@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile           |   2 +-
+ .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c    |   5 +-
+ drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c    | 722 ++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h    |  34 +
+ 4 files changed, 760 insertions(+), 3 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index cfe189eb496e..5a38934c5c94 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -55,7 +55,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
+ 	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
+ 	amdgpu_sem.o amdgpu_gmc.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o \
+ 	amdgpu_vm_cpu.o amdgpu_vm_sdma.o amdgpu_pmu.o amdgpu_discovery.o \
+-	amdgpu_ras_eeprom.o
++	amdgpu_ras_eeprom.o smu_v11_0_i2c.o
+ 
+ amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+index b544e0a05925..86110e6095cc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+@@ -25,6 +25,7 @@
+ #include "amdgpu.h"
+ #include "amdgpu_ras.h"
+ #include <linux/bits.h>
++#include "smu_v11_0_i2c.h"
+ 
+ #define EEPROM_I2C_TARGET_ADDR 0xA0
+ 
+@@ -118,7 +119,7 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_VEGA20:
+-	/*TODO Add MI-60 */
++		ret = smu_v11_0_i2c_eeprom_control_init(&control->eeprom_accessor);
+ 		break;
+ 
+ 	default:
+@@ -170,7 +171,7 @@ void amdgpu_ras_eeprom_fini(struct amdgpu_ras_eeprom_control *control)
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_VEGA20:
+-		/*TODO Add MI-60 */
++		smu_v11_0_i2c_eeprom_control_fini(&control->eeprom_accessor);
+ 		break;
+ 
+ 	default:
+diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
+new file mode 100644
+index 000000000000..4cfcef0feff8
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
+@@ -0,0 +1,722 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include "smuio/smuio_11_0_0_offset.h"
++#include "smuio/smuio_11_0_0_sh_mask.h"
++
++#include "smu_v11_0_i2c.h"
++#include "amdgpu.h"
++#include "soc15_common.h"
++#include <drm/drm_fixed.h>
++#include "amdgpu_amdkfd.h"
++#include <linux/i2c.h>
++#include "amdgpu_ras.h"
++
++/* error codes */
++#define I2C_OK                0
++#define I2C_NAK_7B_ADDR_NOACK 1
++#define I2C_NAK_TXDATA_NOACK  2
++#define I2C_TIMEOUT           4
++#define I2C_SW_TIMEOUT        8
++#define I2C_ABORT             0x10
++
++/* I2C transaction flags */
++#define I2C_NO_STOP	1
++#define I2C_RESTART	2
++
++#define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control.eeprom_accessor))->adev
++#define to_eeprom_control(x) container_of(x, struct amdgpu_ras_eeprom_control, eeprom_accessor)
++
++static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en)
++{
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++	uint32_t reg;
++
++	reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0);
++	WREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT, reg);
++}
++
++
++static void smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable)
++{
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++
++	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, enable ? 1 : 0);
++}
++
++static void smu_v11_0_i2c_clear_status(struct i2c_adapter *control)
++{
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++	/* do */
++	{
++		RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR);
++
++	} /* while (reg_CKSVII2C_ic_clr_intr == 0) */
++}
++
++static void smu_v11_0_i2c_configure(struct i2c_adapter *control)
++{
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++	uint32_t reg = 0;
++
++	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1);
++	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_RESTART_EN, 1);
++	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_MASTER, 0);
++	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_SLAVE, 0);
++	/* Standard mode */
++	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MAX_SPEED_MODE, 2);
++	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MASTER_MODE, 1);
++
++	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CON, reg);
++}
++
++static void smu_v11_0_i2c_set_clock(struct i2c_adapter *control)
++{
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++
++	/*
++	 * Standard mode speed, These values are taken from SMUIO MAS,
++	 * but are different from what is given is
++	 * Synopsys spec. The values here are based on assumption
++	 * that refclock is 100MHz
++	 *
++	 * Configuration for standard mode; Speed = 100kbps
++	 * Scale linearly, for now only support standard speed clock
++	 * This will work only with 100M ref clock
++	 *
++	 * TBD:Change the calculation to take into account ref clock values also.
++	 */
++
++	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_FS_SPKLEN, 2);
++	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_HCNT, 120);
++	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_LCNT, 130);
++	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SDA_HOLD, 20);
++}
++
++static void smu_v11_0_i2c_set_address(struct i2c_adapter *control, uint8_t address)
++{
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++
++	/* Convert fromr 8-bit to 7-bit address */
++	address >>= 1;
++	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TAR, (address & 0xFF));
++}
++
++static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control)
++{
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++	uint32_t ret = I2C_OK;
++	uint32_t reg, reg_c_tx_abrt_source;
++
++	/*Check if transmission is completed */
++	unsigned long  timeout_counter = jiffies + msecs_to_jiffies(20);
++
++	do {
++		if (time_after(jiffies, timeout_counter)) {
++			ret |= I2C_SW_TIMEOUT;
++			break;
++		}
++
++		reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
++
++	} while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0);
++
++	if (ret != I2C_OK)
++		return ret;
++
++	/* This only checks if NAK is received and transaction got aborted */
++	reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT);
++
++	if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) {
++		reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);
++		DRM_INFO("TX was terminated, IC_TX_ABRT_SOURCE val is:%x", reg_c_tx_abrt_source);
++
++		/* Check for stop due to NACK */
++		if (REG_GET_FIELD(reg_c_tx_abrt_source,
++				  CKSVII2C_IC_TX_ABRT_SOURCE,
++				  ABRT_TXDATA_NOACK) == 1) {
++
++			ret |= I2C_NAK_TXDATA_NOACK;
++
++		} else if (REG_GET_FIELD(reg_c_tx_abrt_source,
++					 CKSVII2C_IC_TX_ABRT_SOURCE,
++					 ABRT_7B_ADDR_NOACK) == 1) {
++
++			ret |= I2C_NAK_7B_ADDR_NOACK;
++		} else {
++			ret |= I2C_ABORT;
++		}
++
++		smu_v11_0_i2c_clear_status(control);
++	}
++
++	return ret;
++}
++
++static uint32_t smu_v11_0_i2c_poll_rx_status(struct i2c_adapter *control)
++{
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++	uint32_t ret = I2C_OK;
++	uint32_t reg_ic_status, reg_c_tx_abrt_source;
++
++	reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);
++
++	/* If slave is not present */
++	if (REG_GET_FIELD(reg_c_tx_abrt_source,
++			  CKSVII2C_IC_TX_ABRT_SOURCE,
++			  ABRT_7B_ADDR_NOACK) == 1) {
++		ret |= I2C_NAK_7B_ADDR_NOACK;
++
++		smu_v11_0_i2c_clear_status(control);
++	} else {  /* wait till some data is there in RXFIFO */
++		/* Poll for some byte in RXFIFO */
++		unsigned long  timeout_counter = jiffies + msecs_to_jiffies(20);
++
++		do {
++			if (time_after(jiffies, timeout_counter)) {
++				ret |= I2C_SW_TIMEOUT;
++				break;
++			}
++
++			reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
++
++		} while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0);
++	}
++
++	return ret;
++}
++
++
++
++
++/**
++ * smu_v11_0_i2c_transmit - Send a block of data over the I2C bus to a slave device.
++ *
++ * @address: The I2C address of the slave device.
++ * @data: The data to transmit over the bus.
++ * @numbytes: The amount of data to transmit.
++ * @i2c_flag: Flags for transmission
++ *
++ * Returns 0 on success or error.
++ */
++static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter *control,
++				  uint8_t address, uint8_t *data,
++				  uint32_t numbytes, uint32_t i2c_flag)
++{
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++	uint32_t bytes_sent, reg, ret = 0;
++	unsigned long  timeout_counter;
++
++	bytes_sent = 0;
++
++	DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ",
++		 (uint16_t)address, numbytes);
++
++	if (drm_debug & DRM_UT_DRIVER) {
++		print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
++			       16, 1, data, numbytes, false);
++	}
++
++	/* Set the I2C slave address */
++	smu_v11_0_i2c_set_address(control, address);
++	/* Enable I2C */
++	smu_v11_0_i2c_enable(control, true);
++
++	/* Clear status bits */
++	smu_v11_0_i2c_clear_status(control);
++
++
++	timeout_counter = jiffies + msecs_to_jiffies(20);
++
++	while (numbytes > 0) {
++		reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
++		if (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) {
++			do {
++				reg = 0;
++				/*
++				 * Prepare transaction, no need to set RESTART. I2C engine will send
++				 * START as soon as it sees data in TXFIFO
++				 */
++				if (bytes_sent == 0)
++					reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART,
++							    (i2c_flag & I2C_RESTART) ? 1 : 0);
++				reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, data[bytes_sent]);
++
++				/* determine if we need to send STOP bit or not */
++				if (numbytes == 1)
++					/* Final transaction, so send stop unless I2C_NO_STOP */
++					reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP,
++							    (i2c_flag & I2C_NO_STOP) ? 0 : 1);
++				/* Write */
++				reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 0);
++				WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
++
++				/* Record that the bytes were transmitted */
++				bytes_sent++;
++				numbytes--;
++
++				reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
++
++			} while (numbytes &&  REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF));
++		}
++
++		/*
++		 * We waited too long for the transmission FIFO to become not-full.
++		 * Exit the loop with error.
++		 */
++		if (time_after(jiffies, timeout_counter)) {
++			ret |= I2C_SW_TIMEOUT;
++			goto Err;
++		}
++	}
++
++	ret = smu_v11_0_i2c_poll_tx_status(control);
++
++Err:
++	/* Any error, no point in proceeding */
++	if (ret != I2C_OK) {
++		if (ret & I2C_SW_TIMEOUT)
++			DRM_ERROR("TIMEOUT ERROR !!!");
++
++		if (ret & I2C_NAK_7B_ADDR_NOACK)
++			DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!");
++
++
++		if (ret & I2C_NAK_TXDATA_NOACK)
++			DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!");
++	}
++
++	return ret;
++}
++
++
++/**
++ * smu_v11_0_i2c_receive - Receive a block of data over the I2C bus from a slave device.
++ *
++ * @address: The I2C address of the slave device.
++ * @numbytes: The amount of data to transmit.
++ * @i2c_flag: Flags for transmission
++ *
++ * Returns 0 on success or error.
++ */
++static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter *control,
++				 uint8_t address, uint8_t *data,
++				 uint32_t numbytes, uint8_t i2c_flag)
++{
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++	uint32_t bytes_received, ret = I2C_OK;
++
++	bytes_received = 0;
++
++	/* Set the I2C slave address */
++	smu_v11_0_i2c_set_address(control, address);
++
++	/* Enable I2C */
++	smu_v11_0_i2c_enable(control, true);
++
++	while (numbytes > 0) {
++		uint32_t reg = 0;
++
++		smu_v11_0_i2c_clear_status(control);
++
++
++		/* Prepare transaction */
++
++		/* Each time we disable I2C, so this is not a restart */
++		if (bytes_received == 0)
++			reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART,
++					    (i2c_flag & I2C_RESTART) ? 1 : 0);
++
++		reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, 0);
++		/* Read */
++		reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 1);
++
++		/* Transmitting last byte */
++		if (numbytes == 1)
++			/* Final transaction, so send stop if requested */
++			reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP,
++					    (i2c_flag & I2C_NO_STOP) ? 0 : 1);
++
++		WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
++
++		ret = smu_v11_0_i2c_poll_rx_status(control);
++
++		/* Any error, no point in proceeding */
++		if (ret != I2C_OK) {
++			if (ret & I2C_SW_TIMEOUT)
++				DRM_ERROR("TIMEOUT ERROR !!!");
++
++			if (ret & I2C_NAK_7B_ADDR_NOACK)
++				DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!");
++
++			if (ret & I2C_NAK_TXDATA_NOACK)
++				DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!");
++
++			break;
++		}
++
++		reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD);
++		data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT);
++
++		/* Record that the bytes were received */
++		bytes_received++;
++		numbytes--;
++	}
++
++	DRM_DEBUG_DRIVER("I2C_Receive(), address = %x, bytes = %d, data :",
++		  (uint16_t)address, bytes_received);
++
++	if (drm_debug & DRM_UT_DRIVER) {
++		print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
++			       16, 1, data, bytes_received, false);
++	}
++
++	return ret;
++}
++
++static void smu_v11_0_i2c_abort(struct i2c_adapter *control)
++{
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++	uint32_t reg = 0;
++
++	/* Enable I2C engine; */
++	reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1);
++	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg);
++
++	/* Abort previous transaction */
++	reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ABORT, 1);
++	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg);
++
++	DRM_DEBUG_DRIVER("I2C_Abort() Done.");
++}
++
++
++static bool smu_v11_0_i2c_activity_done(struct i2c_adapter *control)
++{
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++
++	const uint32_t IDLE_TIMEOUT = 1024;
++	uint32_t timeout_count = 0;
++	uint32_t reg_ic_enable, reg_ic_enable_status, reg_ic_clr_activity;
++
++	reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);
++	reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);
++
++
++	if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &&
++	    (REG_GET_FIELD(reg_ic_enable_status, CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) {
++		/*
++		 * Nobody is using I2C engine, but engine remains active because
++		 * someone missed to send STOP
++		 */
++		smu_v11_0_i2c_abort(control);
++	} else if (REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) {
++		/* Nobody is using I2C engine */
++		return true;
++	}
++
++	/* Keep reading activity bit until it's cleared */
++	do {
++		reg_ic_clr_activity = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_ACTIVITY);
++
++		if (REG_GET_FIELD(reg_ic_clr_activity,
++		    CKSVII2C_IC_CLR_ACTIVITY, CLR_ACTIVITY) == 0)
++			return true;
++
++		++timeout_count;
++
++	} while (timeout_count < IDLE_TIMEOUT);
++
++	return false;
++}
++
++static void smu_v11_0_i2c_init(struct i2c_adapter *control)
++{
++	/* Disable clock gating */
++	smu_v11_0_i2c_set_clock_gating(control, false);
++
++	if (!smu_v11_0_i2c_activity_done(control))
++		DRM_WARN("I2C busy !");
++
++	/* Disable I2C */
++	smu_v11_0_i2c_enable(control, false);
++
++	/* Configure I2C to operate as master and in standard mode */
++	smu_v11_0_i2c_configure(control);
++
++	/* Initialize the clock to 50 kHz default */
++	smu_v11_0_i2c_set_clock(control);
++
++}
++
++static void smu_v11_0_i2c_fini(struct i2c_adapter *control)
++{
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++	uint32_t reg_ic_enable_status, reg_ic_enable;
++
++	smu_v11_0_i2c_enable(control, false);
++
++	/* Double check if disabled, else force abort */
++	reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);
++	reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);
++
++	if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &&
++	    (REG_GET_FIELD(reg_ic_enable_status,
++			   CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) {
++		/*
++		 * Nobody is using I2C engine, but engine remains active because
++		 * someone missed to send STOP
++		 */
++		smu_v11_0_i2c_abort(control);
++	}
++
++	/* Restore clock gating */
++	smu_v11_0_i2c_set_clock_gating(control, true);
++
++}
++
++static bool smu_v11_0_i2c_bus_lock(struct i2c_adapter *control)
++{
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++
++	/* Send  PPSMC_MSG_RequestI2CBus */
++	if (!adev->powerplay.pp_funcs->smu_i2c_bus_access)
++		goto Fail;
++
++
++	if (!adev->powerplay.pp_funcs->smu_i2c_bus_access(adev->powerplay.pp_handle, true))
++		return true;
++
++Fail:
++	return false;
++}
++
++static bool smu_v11_0_i2c_bus_unlock(struct i2c_adapter *control)
++{
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++
++	/* Send  PPSMC_MSG_RequestI2CBus */
++	if (!adev->powerplay.pp_funcs->smu_i2c_bus_access)
++		goto Fail;
++
++	/* Send  PPSMC_MSG_ReleaseI2CBus */
++	if (!adev->powerplay.pp_funcs->smu_i2c_bus_access(adev->powerplay.pp_handle,
++							     false))
++		return true;
++
++Fail:
++	return false;
++}
++
++/***************************** EEPROM I2C GLUE ****************************/
++
++static uint32_t smu_v11_0_i2c_eeprom_read_data(struct i2c_adapter *control,
++					       uint8_t address,
++					       uint8_t *data,
++					       uint32_t numbytes)
++{
++	uint32_t  ret = 0;
++
++	/* First 2 bytes are dummy write to set EEPROM address */
++	ret = smu_v11_0_i2c_transmit(control, address, data, 2, I2C_NO_STOP);
++	if (ret != I2C_OK)
++		goto Fail;
++
++	/* Now read data starting with that address */
++	ret = smu_v11_0_i2c_receive(control, address, data + 2, numbytes - 2,
++				    I2C_RESTART);
++
++Fail:
++	if (ret != I2C_OK)
++		DRM_ERROR("ReadData() - I2C error occurred :%x", ret);
++
++	return ret;
++}
++
++static uint32_t smu_v11_0_i2c_eeprom_write_data(struct i2c_adapter *control,
++						uint8_t address,
++						uint8_t *data,
++						uint32_t numbytes)
++{
++	uint32_t  ret;
++
++	ret = smu_v11_0_i2c_transmit(control, address, data, numbytes, 0);
++
++	if (ret != I2C_OK)
++		DRM_ERROR("WriteI2CData() - I2C error occurred :%x", ret);
++	else
++		/*
++		 * According to EEPROM spec there is a MAX of 10 ms required for
++		 * EEPROM to flush internal RX buffer after STOP was issued at the
++		 * end of write transaction. During this time the EEPROM will not be
++		 * responsive to any more commands - so wait a bit more.
++		 *
++		 * TODO Improve to wait for first ACK for slave address after
++		 * internal write cycle done.
++		 */
++		msleep(10);
++
++	return ret;
++
++}
++
++static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
++{
++	struct amdgpu_ras_eeprom_control *control = to_eeprom_control(i2c);
++
++	if (!smu_v11_0_i2c_bus_lock(i2c)) {
++		DRM_ERROR("Failed to lock the bus from SMU");
++		return;
++	}
++
++	control->bus_locked = true;
++}
++
++static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
++{
++	WARN_ONCE(1, "This operation not supposed to run in atomic context!");
++	return false;
++}
++
++static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
++{
++	struct amdgpu_ras_eeprom_control *control = to_eeprom_control(i2c);
++
++	if (!smu_v11_0_i2c_bus_unlock(i2c)) {
++		DRM_ERROR("Failed to unlock the bus from SMU");
++		return;
++	}
++
++	control->bus_locked = false;
++}
++
++static const struct i2c_lock_operations smu_v11_0_i2c_i2c_lock_ops = {
++	.lock_bus = lock_bus,
++	.trylock_bus = trylock_bus,
++	.unlock_bus = unlock_bus,
++};
++
++static int smu_v11_0_i2c_eeprom_i2c_xfer(struct i2c_adapter *i2c_adap,
++			      struct i2c_msg *msgs, int num)
++{
++	int i, ret;
++	struct amdgpu_ras_eeprom_control *control = to_eeprom_control(i2c_adap);
++
++	if (!control->bus_locked) {
++		DRM_ERROR("I2C bus unlocked, stopping transaction!");
++		return -EIO;
++	}
++
++	smu_v11_0_i2c_init(i2c_adap);
++
++	for (i = 0; i < num; i++) {
++		if (msgs[i].flags & I2C_M_RD)
++			ret = smu_v11_0_i2c_eeprom_read_data(i2c_adap,
++							(uint8_t)msgs[i].addr,
++							msgs[i].buf, msgs[i].len);
++		else
++			ret = smu_v11_0_i2c_eeprom_write_data(i2c_adap,
++							 (uint8_t)msgs[i].addr,
++							 msgs[i].buf, msgs[i].len);
++
++		if (ret != I2C_OK) {
++			num = -EIO;
++			break;
++		}
++	}
++
++	smu_v11_0_i2c_fini(i2c_adap);
++	return num;
++}
++
++static u32 smu_v11_0_i2c_eeprom_i2c_func(struct i2c_adapter *adap)
++{
++	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
++}
++
++
++static const struct i2c_algorithm smu_v11_0_i2c_eeprom_i2c_algo = {
++	.master_xfer = smu_v11_0_i2c_eeprom_i2c_xfer,
++	.functionality = smu_v11_0_i2c_eeprom_i2c_func,
++};
++
++int smu_v11_0_i2c_eeprom_control_init(struct i2c_adapter *control)
++{
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++	int res;
++
++	control->owner = THIS_MODULE;
++	control->class = I2C_CLASS_SPD;
++	control->dev.parent = &adev->pdev->dev;
++	control->algo = &smu_v11_0_i2c_eeprom_i2c_algo;
++	snprintf(control->name, sizeof(control->name), "RAS EEPROM");
++	control->lock_ops = &smu_v11_0_i2c_i2c_lock_ops;
++
++	res = i2c_add_adapter(control);
++	if (res)
++		DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
++
++	return res;
++}
++
++void smu_v11_0_i2c_eeprom_control_fini(struct i2c_adapter *control)
++{
++	i2c_del_adapter(control);
++}
++
++/*
++ * Keep this for future unit test if bugs arise
++ */
++#if 0
++#define I2C_TARGET_ADDR 0xA0
++
++bool smu_v11_0_i2c_test_bus(struct i2c_adapter *control)
++{
++
++	uint32_t ret = I2C_OK;
++	uint8_t data[6] = {0xf, 0, 0xde, 0xad, 0xbe, 0xef};
++
++
++	DRM_INFO("Begin");
++
++	if (!smu_v11_0_i2c_bus_lock(control)) {
++		DRM_ERROR("Failed to lock the bus!.");
++		return false;
++	}
++
++	smu_v11_0_i2c_init(control);
++
++	/* Write 0xde to address 0x0000 on the EEPROM */
++	ret = smu_v11_0_i2c_eeprom_write_data(control, I2C_TARGET_ADDR, data, 6);
++
++	ret = smu_v11_0_i2c_eeprom_read_data(control, I2C_TARGET_ADDR, data, 6);
++
++	smu_v11_0_i2c_fini(control);
++
++	smu_v11_0_i2c_bus_unlock(control);
++
++
++	DRM_INFO("End");
++	return true;
++}
++#endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h
+new file mode 100644
+index 000000000000..973f28d68e70
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h
+@@ -0,0 +1,34 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef SMU_V11_I2C_CONTROL_H
++#define SMU_V11_I2C_CONTROL_H
++
++#include <linux/types.h>
++
++struct i2c_adapter;
++
++int smu_v11_0_i2c_eeprom_control_init(struct i2c_adapter *control);
++void smu_v11_0_i2c_eeprom_control_fini(struct i2c_adapter *control);
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3617-drm-amdgpu-fix-a-warning-in-smu11-i2c-code.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3617-drm-amdgpu-fix-a-warning-in-smu11-i2c-code.patch
new file mode 100644
index 00000000..d7fa90c7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3617-drm-amdgpu-fix-a-warning-in-smu11-i2c-code.patch
@@ -0,0 +1,29 @@
+From ab54a0488ebc25134d389f3532e0fd0618a39e50 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 26 Aug 2019 13:52:25 -0500
+Subject: [PATCH 3617/4256] drm/amdgpu: fix a warning in smu11 i2c code
+
+make sure reg is initialized in smu_v11_0_i2c_set_clock_gating.
+
+Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
+index 4cfcef0feff8..7d0d4c57b315 100644
+--- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
++++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
+@@ -50,7 +50,7 @@
+ static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en)
+ {
+ 	struct amdgpu_device *adev = to_amdgpu_device(control);
+-	uint32_t reg;
++	uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT);
+ 
+ 	reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0);
+ 	WREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT, reg);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3618-drm-amdgpu-correct-in_suspend-setting-for-navi-serie.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3618-drm-amdgpu-correct-in_suspend-setting-for-navi-serie.patch
new file mode 100644
index 00000000..9899858b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3618-drm-amdgpu-correct-in_suspend-setting-for-navi-serie.patch
@@ -0,0 +1,45 @@
+From 4586a5f8ed696263540dd814e96c718c6b0a8834 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Tue, 27 Aug 2019 17:13:47 +0800
+Subject: [PATCH 3618/4256] drm/amdgpu: correct in_suspend setting for navi
+ series
+
+in_suspend flag should be set in amdgpu_device_suspend/resume in pairs,
+instead of gfx10 ip suspend/resume function.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 12 ++----------
+ 1 file changed, 2 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index c72aad8c360a..c3b48ac398a5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -3769,20 +3769,12 @@ static int gfx_v10_0_hw_fini(void *handle)
+ 
+ static int gfx_v10_0_suspend(void *handle)
+ {
+-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-
+-	adev->in_suspend = true;
+-	return gfx_v10_0_hw_fini(adev);
++	return gfx_v10_0_hw_fini(handle);
+ }
+ 
+ static int gfx_v10_0_resume(void *handle)
+ {
+-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	int r;
+-
+-	r = gfx_v10_0_hw_init(adev);
+-	adev->in_suspend = false;
+-	return r;
++	return gfx_v10_0_hw_init(handle);
+ }
+ 
+ static bool gfx_v10_0_is_idle(void *handle)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3619-drm-amd-display-remove-unused-function-setFieldWithM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3619-drm-amd-display-remove-unused-function-setFieldWithM.patch
new file mode 100644
index 00000000..6a963417
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3619-drm-amd-display-remove-unused-function-setFieldWithM.patch
@@ -0,0 +1,50 @@
+From d22b9adbed311cd1e5545ce68cdd8371d00a8c75 Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Tue, 27 Aug 2019 15:09:25 +0800
+Subject: [PATCH 3619/4256] drm/amd/display: remove unused function
+ setFieldWithMask
+
+After commit a9f54ce3c603 ("drm/amd/display: Refactoring VTEM"),
+there is no caller in tree.
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../display/modules/info_packet/info_packet.c | 19 -------------------
+ 1 file changed, 19 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
+index 5f4b98df3d92..d885d642ed7f 100644
+--- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
++++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
+@@ -114,25 +114,6 @@ enum ColorimetryYCCDP {
+ 	ColorimetryYCC_DP_ITU2020YCbCr  = 7,
+ };
+ 
+-void setFieldWithMask(unsigned char *dest, unsigned int mask, unsigned int value)
+-{
+-	unsigned int shift = 0;
+-
+-	if (!mask || !dest)
+-		return;
+-
+-	while (!((mask >> shift) & 1))
+-		shift++;
+-
+-	//reset
+-	*dest = *dest & ~mask;
+-	//set
+-	//dont let value span past mask
+-	value = value & (mask >> shift);
+-	//insert value
+-	*dest = *dest | (value << shift);
+-}
+-
+ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
+ 		struct dc_info_packet *info_packet)
+ {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3620-drm-amdgpu-Add-APTX-quirk-for-Dell-Latitude-5495.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3620-drm-amdgpu-Add-APTX-quirk-for-Dell-Latitude-5495.patch
new file mode 100644
index 00000000..8396c515
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3620-drm-amdgpu-Add-APTX-quirk-for-Dell-Latitude-5495.patch
@@ -0,0 +1,29 @@
+From 73cef3f49e6d43355ee24fa89c3245a3eacf16e9 Mon Sep 17 00:00:00 2001
+From: Kai-Heng Feng <kai.heng.feng@canonical.com>
+Date: Tue, 27 Aug 2019 17:33:32 +0800
+Subject: [PATCH 3620/4256] drm/amdgpu: Add APTX quirk for Dell Latitude 5495
+
+Needs ATPX rather than _PR3 to really turn off the dGPU. This can save
+~5W when dGPU is runtime-suspended.
+
+Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+index 92b11de19581..354c8b6106dc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+@@ -575,6 +575,7 @@ static const struct amdgpu_px_quirk amdgpu_px_quirk_list[] = {
+ 	{ 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },
+ 	{ 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },
+ 	{ 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },
++	{ 0x1002, 0x699f, 0x1028, 0x0814, AMDGPU_PX_QUIRK_FORCE_ATPX },
+ 	{ 0x1002, 0x6900, 0x1025, 0x125A, AMDGPU_PX_QUIRK_FORCE_ATPX },
+ 	{ 0x1002, 0x6900, 0x17AA, 0x3806, AMDGPU_PX_QUIRK_FORCE_ATPX },
+ 	{ 0, 0, 0, 0, 0 },
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3621-drm-amd-remove-meaningless-descending-into-amd-amdkf.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3621-drm-amd-remove-meaningless-descending-into-amd-amdkf.patch
new file mode 100644
index 00000000..bc5de1ca
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3621-drm-amd-remove-meaningless-descending-into-amd-amdkf.patch
@@ -0,0 +1,31 @@
+From d4163466fc1decfd8b93a45bafdac53b0cc38f38 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Tue, 27 Aug 2019 15:44:25 +0900
+Subject: [PATCH 3621/4256] drm/amd: remove meaningless descending into
+ amd/amdkfd/
+
+Since commit 04d5e2765802 ("drm/amdgpu: Merge amdkfd into amdgpu"),
+drivers/gpu/drm/amd/amdkfd/Makefile does not contain any syntax that
+is understood by the build system.
+
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/Makefile | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
+index 873823206df7..205ffae7fed9 100644
+--- a/drivers/gpu/drm/Makefile
++++ b/drivers/gpu/drm/Makefile
+@@ -54,7 +54,6 @@ obj-$(CONFIG_DRM_TTM)	+= ttm/
+ obj-$(CONFIG_DRM_SCHED)	+= scheduler/
+ obj-$(CONFIG_DRM_TDFX)	+= tdfx/
+ obj-$(CONFIG_DRM_R128)	+= r128/
+-obj-$(CONFIG_HSA_AMD) += amd/amdkfd/
+ obj-$(CONFIG_DRM_RADEON)+= radeon/
+ obj-$(CONFIG_DRM_AMDGPU)+= amd/amdgpu/
+ obj-$(CONFIG_DRM_MGA)	+= mga/
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3622-drm-amdgpu-introduce-vram-lost-for-reset-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3622-drm-amdgpu-introduce-vram-lost-for-reset-v2.patch
new file mode 100644
index 00000000..15577564
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3622-drm-amdgpu-introduce-vram-lost-for-reset-v2.patch
@@ -0,0 +1,95 @@
+From 20dd1c66e248fb981c8329ea14d93aa069a15541 Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Tue, 27 Aug 2019 16:32:55 +0800
+Subject: [PATCH 3622/4256] drm/amdgpu: introduce vram lost for reset (v2)
+
+for SOC15/vega10 the BACO reset & mode1 would introduce vram lost
+in high end address range, current kmd's vram lost checking cannot
+catch it since it only check very ahead visible frame buffer
+
+v2:
+cover NV as well
+
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/nv.c            | 7 +++++--
+ drivers/gpu/drm/amd/amdgpu/soc15.c         | 2 ++
+ 4 files changed, 10 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 0d68005ceef7..02bd4e99906f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1192,6 +1192,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
+ #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
+ #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
+ #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
++#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
+ 
+ /* Common functions */
+ bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index ba49073131d0..ed01af203896 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3468,7 +3468,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
+ 	amdgpu_virt_init_data_exchange(adev);
+ 	amdgpu_virt_release_full_gpu(adev, true);
+ 	if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
+-		atomic_inc(&adev->vram_lost_counter);
++		amdgpu_inc_vram_lost(adev);
+ 		r = amdgpu_device_recover_vram(adev);
+ 	}
+ 
+@@ -3634,7 +3634,7 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
+ 				vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
+ 				if (vram_lost) {
+ 					DRM_INFO("VRAM is lost due to GPU reset!\n");
+-					atomic_inc(&tmp_adev->vram_lost_counter);
++					amdgpu_inc_vram_lost(tmp_adev);
+ 				}
+ 
+ 				r = amdgpu_gtt_mgr_recover(
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 384f8f512fc4..323af1ecfe9c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -315,10 +315,13 @@ static int nv_asic_reset(struct amdgpu_device *adev)
+ 	int ret = 0;
+ 	struct smu_context *smu = &adev->smu;
+ 
+-	if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
++	if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
++		amdgpu_inc_vram_lost(adev);
+ 		ret = smu_baco_reset(smu);
+-	else
++	} else {
++		amdgpu_inc_vram_lost(adev);
+ 		ret = nv_asic_mode1_reset(adev);
++	}
+ 
+ 	return ret;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index fe2212df12a3..8af7501bded1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -557,10 +557,12 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
+ {
+ 	switch (soc15_asic_reset_method(adev)) {
+ 		case AMD_RESET_METHOD_BACO:
++			amdgpu_inc_vram_lost(adev);
+ 			return soc15_asic_baco_reset(adev);
+ 		case AMD_RESET_METHOD_MODE2:
+ 			return soc15_mode2_reset(adev);
+ 		default:
++			amdgpu_inc_vram_lost(adev);
+ 			return soc15_asic_mode1_reset(adev);
+ 	}
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3623-drm-amd-amdgpu-hide-voltage-and-power-sensors-on-SI-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3623-drm-amd-amdgpu-hide-voltage-and-power-sensors-on-SI-.patch
new file mode 100644
index 00000000..799a97af
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3623-drm-amd-amdgpu-hide-voltage-and-power-sensors-on-SI-.patch
@@ -0,0 +1,52 @@
+From 18c72104e07959de36dbaae585d45f0adbfac9b5 Mon Sep 17 00:00:00 2001
+From: Jean Delvare <jdelvare@suse.de>
+Date: Wed, 28 Aug 2019 10:27:29 +0200
+Subject: [PATCH 3623/4256] drm/amd/amdgpu: hide voltage and power sensors on
+ SI and KV parts
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The driver does not support these sensors yet and there is no point in
+creating sysfs attributes which will always return an error.
+
+Signed-off-by: Jean Delvare <jdelvare@suse.de>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: "Christian König" <christian.koenig@amd.com>
+Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index 6a651b0480c0..7842beea7d91 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -2346,7 +2346,9 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
+ 			effective_mode &= ~S_IWUSR;
+ 	}
+ 
+-	if ((adev->flags & AMD_IS_APU) &&
++	if (((adev->flags & AMD_IS_APU) ||
++	     adev->family == AMDGPU_FAMILY_SI ||	/* not implemented yet */
++	     adev->family == AMDGPU_FAMILY_KV) &&	/* not implemented yet */
+ 	    (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
+ 	     attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
+ 	     attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
+@@ -2370,6 +2372,12 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
+ 			return 0;
+ 	}
+ 
++	if ((adev->family == AMDGPU_FAMILY_SI ||	/* not implemented yet */
++	     adev->family == AMDGPU_FAMILY_KV) &&	/* not implemented yet */
++	    (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
++	     attr == &sensor_dev_attr_in0_label.dev_attr.attr))
++		return 0;
++
+ 	/* only APUs have vddnb */
+ 	if (!(adev->flags & AMD_IS_APU) &&
+ 	    (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3624-drm-amdgpu-si-fix-ASIC-tests.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3624-drm-amdgpu-si-fix-ASIC-tests.patch
new file mode 100644
index 00000000..514e8442
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3624-drm-amdgpu-si-fix-ASIC-tests.patch
@@ -0,0 +1,57 @@
+From b9099d3a0d993c9e65e32ce9da6de598c1594c38 Mon Sep 17 00:00:00 2001
+From: Jean Delvare <jdelvare@suse.de>
+Date: Wed, 28 Aug 2019 17:05:57 +0200
+Subject: [PATCH 3624/4256] drm/amdgpu/si: fix ASIC tests
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Comparing adev->family with CHIP constants is not correct.
+adev->family can only be compared with AMDGPU_FAMILY constants and
+adev->asic_type is the struct member to compare with CHIP constants.
+They are separate identification spaces.
+
+Signed-off-by: Jean Delvare <jdelvare@suse.de>
+Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10")
+Cc: Ken Wang <Qingqing.Wang@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: "Christian König" <christian.koenig@amd.com>
+Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/si.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
+index 904361451650..0d2533025227 100644
+--- a/drivers/gpu/drm/amd/amdgpu/si.c
++++ b/drivers/gpu/drm/amd/amdgpu/si.c
+@@ -1887,7 +1887,7 @@ static void si_program_aspm(struct amdgpu_device *adev)
+ 			if (orig != data)
+ 				si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
+ 
+-			if ((adev->family != CHIP_OLAND) && (adev->family != CHIP_HAINAN)) {
++			if ((adev->asic_type != CHIP_OLAND) && (adev->asic_type != CHIP_HAINAN)) {
+ 				orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
+ 				data &= ~PLL_RAMP_UP_TIME_0_MASK;
+ 				if (orig != data)
+@@ -1936,14 +1936,14 @@ static void si_program_aspm(struct amdgpu_device *adev)
+ 
+ 			orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
+ 			data &= ~LS2_EXIT_TIME_MASK;
+-			if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
++			if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN))
+ 				data |= LS2_EXIT_TIME(5);
+ 			if (orig != data)
+ 				si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
+ 
+ 			orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
+ 			data &= ~LS2_EXIT_TIME_MASK;
+-			if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
++			if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN))
+ 				data |= LS2_EXIT_TIME(5);
+ 			if (orig != data)
+ 				si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3625-drm-amdgpu-virtual_dce-drop-error-message-in-hw_init.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3625-drm-amdgpu-virtual_dce-drop-error-message-in-hw_init.patch
new file mode 100644
index 00000000..e66c853f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3625-drm-amdgpu-virtual_dce-drop-error-message-in-hw_init.patch
@@ -0,0 +1,43 @@
+From 8f746f3ef55f1ee6e21fd932bee2476fc94f1ca2 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 28 Aug 2019 08:47:34 -0500
+Subject: [PATCH 3625/4256] drm/amdgpu/virtual_dce: drop error message in
+ hw_init
+
+No need to add new asic cases.  This is a sw display
+implementation, so just drop the error message so when
+we add new asics, all we have to do is add the virtual
+dce IP module.
+
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 11 +----------
+ 1 file changed, 1 insertion(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+index 6dadbed7ce43..fe242cc7c04f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+@@ -452,17 +452,8 @@ static int dce_virtual_hw_init(void *handle)
+ #endif
+ 		/* no DCE */
+ 		break;
+-	case CHIP_VEGA10:
+-	case CHIP_VEGA12:
+-	case CHIP_VEGA20:
+-	case CHIP_ARCTURUS:
+-	case CHIP_RENOIR:
+-	case CHIP_NAVI10:
+-	case CHIP_NAVI14:
+-	case CHIP_NAVI12:
+-		break;
+ 	default:
+-		DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", adev->asic_type);
++		break;
+ 	}
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3626-drm-amdgpu-fix-spelling-mistake-jumpimng-jumping.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3626-drm-amdgpu-fix-spelling-mistake-jumpimng-jumping.patch
new file mode 100644
index 00000000..c3a15b62
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3626-drm-amdgpu-fix-spelling-mistake-jumpimng-jumping.patch
@@ -0,0 +1,31 @@
+From 6b980ad41ecfcc3b8630db493ea10921106782d0 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Thu, 29 Aug 2019 01:51:56 +0100
+Subject: [PATCH 3626/4256] drm/amdgpu: fix spelling mistake "jumpimng" ->
+ "jumping"
+
+There is a spelling mistake in a DRM_DEBUG_DRIVER debug message.
+Fix it.
+
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+index 86110e6095cc..8a32b5c93778 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+@@ -257,7 +257,7 @@ static uint32_t __correct_eeprom_dest_address(uint32_t curr_address)
+ 	 * https://www.st.com/resource/en/datasheet/m24m02-dr.pdf sec. 5.1.2
+ 	 */
+ 	if ((curr_address & EEPROM_ADDR_MSB_MASK) != (next_address & EEPROM_ADDR_MSB_MASK)) {
+-		DRM_DEBUG_DRIVER("Reached end of EEPROM memory page, jumpimng to next: %lx",
++		DRM_DEBUG_DRIVER("Reached end of EEPROM memory page, jumping to next: %lx",
+ 				(next_address & EEPROM_ADDR_MSB_MASK));
+ 
+ 		return  (next_address & EEPROM_ADDR_MSB_MASK);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3627-drm-amdgpu-psp-keep-TMR-in-visible-vram-region-for-S.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3627-drm-amdgpu-psp-keep-TMR-in-visible-vram-region-for-S.patch
new file mode 100644
index 00000000..5c6acdc5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3627-drm-amdgpu-psp-keep-TMR-in-visible-vram-region-for-S.patch
@@ -0,0 +1,65 @@
+From 48f67d4f5384e4106f79bb4939345e6a8f936fee Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Wed, 28 Aug 2019 10:03:40 +0800
+Subject: [PATCH 3627/4256] drm/amdgpu/psp: keep TMR in visible vram region for
+ SRIOV
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fix compute ring test failure in sriov scenario.
+
+Change-Id: I141d3d094e2cba9bcf2f6c96f4d8c4ef43c421c3
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 2d5cf18f2241..d0d8f15e16f1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -242,6 +242,8 @@ static int psp_tmr_init(struct psp_context *psp)
+ {
+ 	int ret;
+ 	int tmr_size;
++	void *tmr_buf;
++	void **pptr;
+ 
+ 	/*
+ 	 * According to HW engineer, they prefer the TMR address be "naturally
+@@ -264,9 +266,10 @@ static int psp_tmr_init(struct psp_context *psp)
+ 		}
+ 	}
+ 
++	pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
+ 	ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
+ 				      AMDGPU_GEM_DOMAIN_VRAM,
+-				      &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
++				      &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
+ 
+ 	return ret;
+ }
+@@ -1153,6 +1156,8 @@ static int psp_hw_fini(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 	struct psp_context *psp = &adev->psp;
++	void *tmr_buf;
++	void **pptr;
+ 
+ 	if (adev->gmc.xgmi.num_physical_nodes > 1 &&
+ 	    psp->xgmi_context.initialized == 1)
+@@ -1163,7 +1168,8 @@ static int psp_hw_fini(void *handle)
+ 
+ 	psp_ring_destroy(psp, PSP_RING_TYPE__KM);
+ 
+-	amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
++	pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
++	amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
+ 	amdgpu_bo_free_kernel(&psp->fw_pri_bo,
+ 			      &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
+ 	amdgpu_bo_free_kernel(&psp->fence_buf_bo,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3628-drm-amd-powerplay-regards-the-APU-always-enable-the-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3628-drm-amd-powerplay-regards-the-APU-always-enable-the-.patch
new file mode 100644
index 00000000..134245c6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3628-drm-amd-powerplay-regards-the-APU-always-enable-the-.patch
@@ -0,0 +1,34 @@
+From 072dd3796b5a2413d725fb7722e0a2f00f32b28c Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Thu, 15 Aug 2019 09:39:06 +0800
+Subject: [PATCH 3628/4256] drm/amd/powerplay: regards the APU always enable
+ the dpm feature mask
+
+There is no driver message to enable/disable feature mask for APU.
+For the sake of APU reusing swSMU interface and assume APU supports all
+the feature.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Aaron Liu <aaron.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 6f435d60fe86..b4f89c3c2b43 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -636,7 +636,7 @@ int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
+ 	int ret = 0;
+ 
+ 	if (adev->flags & AMD_IS_APU)
+-		return 0;
++		return 1;
+ 
+ 	feature_id = smu_feature_get_index(smu, mask);
+ 	if (feature_id < 0)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3629-drm-amd-powerplay-enable-populate-DPM-clocks-table-f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3629-drm-amd-powerplay-enable-populate-DPM-clocks-table-f.patch
new file mode 100644
index 00000000..42969d94
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3629-drm-amd-powerplay-enable-populate-DPM-clocks-table-f.patch
@@ -0,0 +1,34 @@
+From ec6646d3102f9e7e0a841d3568ec65b9fd5231eb Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Fri, 16 Aug 2019 11:22:13 +0800
+Subject: [PATCH 3629/4256] drm/amd/powerplay: enable populate DPM clocks table
+ for swSMU APU
+
+Should populate DPM clocks tables during hw init,otherwise will
+suffer from invalidate table.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Aaron Liu <aaron.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index b4f89c3c2b43..8c61778f8f74 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1042,9 +1042,6 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ 	struct amdgpu_device *adev = smu->adev;
+ 	int ret;
+ 
+-	if (adev->flags & AMD_IS_APU)
+-		return 0;
+-
+ 	if (smu_is_dpm_running(smu) && adev->in_suspend) {
+ 		pr_info("dpm has been enabled\n");
+ 		return 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3630-drm-amd-powerplay-add-the-interface-for-getting-ulti.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3630-drm-amd-powerplay-add-the-interface-for-getting-ulti.patch
new file mode 100644
index 00000000..3ace8410
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3630-drm-amd-powerplay-add-the-interface-for-getting-ulti.patch
@@ -0,0 +1,301 @@
+From 1eefdc5b5a8a6f8d30f00c26b4a2a6850fd966c3 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Thu, 15 Aug 2019 16:53:08 +0800
+Subject: [PATCH 3630/4256] drm/amd/powerplay: add the interface for getting
+ ultimate frequency v3
+
+add the get_dpm_ultimate_freq for supporting different swSMU.
+-v2:
+        Handle the unsupported clock type and read smc message failed case and return error code.
+        Move the smu12 uclk frequency retrieved logic to renoir ppt.
+-v3:
+        Use goto clause to handle invalidate clk index.
+        Add the limited tag for smu_get_dpm_uclk to avoid other likewise interface introduced.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 38 ++----------
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    | 10 ++-
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c    | 22 +++++++
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 38 ++++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c     | 62 +++++++++++++++++++
+ 5 files changed, 137 insertions(+), 33 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 8c61778f8f74..a65c9297e7bd 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -231,9 +231,8 @@ int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ 			   uint32_t *min, uint32_t *max)
+ {
+-	int ret = 0, clk_id = 0;
+-	uint32_t param = 0;
+ 	uint32_t clock_limit;
++	int ret = 0;
+ 
+ 	if (!min && !max)
+ 		return -EINVAL;
+@@ -264,36 +263,11 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ 
+ 		return 0;
+ 	}
+-
+-	mutex_lock(&smu->mutex);
+-	clk_id = smu_clk_get_index(smu, clk_type);
+-	if (clk_id < 0) {
+-		ret = -EINVAL;
+-		goto failed;
+-	}
+-
+-	param = (clk_id & 0xffff) << 16;
+-
+-	if (max) {
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param);
+-		if (ret)
+-			goto failed;
+-		ret = smu_read_smc_arg(smu, max);
+-		if (ret)
+-			goto failed;
+-	}
+-
+-	if (min) {
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param);
+-		if (ret)
+-			goto failed;
+-		ret = smu_read_smc_arg(smu, min);
+-		if (ret)
+-			goto failed;
+-	}
+-
+-failed:
+-	mutex_unlock(&smu->mutex);
++	/*
++	 * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
++	 * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
++	 */
++	ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
+ 	return ret;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index c42691a9afd3..320ac20146fd 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -458,6 +458,7 @@ struct pptable_funcs {
+ 	int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
+ 	void (*dump_pptable)(struct smu_context *smu);
+ 	int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool asic_default);
++	int (*get_dpm_uclk_limited)(struct smu_context *smu, uint32_t *clock, bool max);
+ };
+ 
+ struct smu_funcs
+@@ -536,7 +537,7 @@ struct smu_funcs
+ 	enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
+ 	int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
+ 	int (*baco_reset)(struct smu_context *smu);
+-
++	int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
+ };
+ 
+ #define smu_init_microcode(smu) \
+@@ -745,6 +746,10 @@ struct smu_funcs
+ 	((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
+ #define smu_set_azalia_d3_pme(smu) \
+ 	((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs->set_azalia_d3_pme((smu)) : 0)
++#define smu_get_dpm_ultimate_freq(smu, param, min, max) \
++		((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
++#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
++	((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
+ #define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
+ 	((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
+ #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
+@@ -759,6 +764,9 @@ struct smu_funcs
+ 	((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
+ #define smu_dump_pptable(smu) \
+ 	((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0)
++#define smu_get_dpm_uclk_limited(smu, clock, max) \
++		((smu)->ppt_funcs->get_dpm_uclk_limited ? (smu)->ppt_funcs->get_dpm_uclk_limited((smu), (clock), (max)) : -EINVAL)
++
+ 
+ extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
+ 				   uint16_t *size, uint8_t *frev, uint8_t *crev,
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index de43159564a5..2a6da546fb55 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -156,11 +156,33 @@ static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
+ 	return 0;
+ }
+ 
++/**
++ * This interface just for getting uclk ultimate freq and should't introduce
++ * other likewise function result in overmuch callback.
++ */
++static int renoir_get_dpm_uclk_limited(struct smu_context *smu, uint32_t *clock, bool max)
++{
++
++	DpmClocks_t *table = smu->smu_table.clocks_table;
++
++	if (!clock || !table)
++		return -EINVAL;
++
++	if (max)
++		*clock = table->FClocks[NUM_FCLK_DPM_LEVELS-1].Freq;
++	else
++		*clock = table->FClocks[0].Freq;
++
++	return 0;
++
++}
++
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_smu_msg_index = renoir_get_smu_msg_index,
+ 	.get_smu_table_index = renoir_get_smu_table_index,
+ 	.tables_init = renoir_tables_init,
+ 	.set_power_state = NULL,
++	.get_dpm_uclk_limited = renoir_get_dpm_uclk_limited,
+ };
+ 
+ void renoir_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index deca9f85764c..117988eb7557 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1717,6 +1717,43 @@ static int smu_v11_0_baco_reset(struct smu_context *smu)
+ 	return ret;
+ }
+ 
++static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
++						 uint32_t *min, uint32_t *max)
++{
++	int ret = 0, clk_id = 0;
++	uint32_t param = 0;
++
++	mutex_lock(&smu->mutex);
++	clk_id = smu_clk_get_index(smu, clk_type);
++	if (clk_id < 0) {
++		ret = -EINVAL;
++		goto failed;
++	}
++	param = (clk_id & 0xffff) << 16;
++
++	if (max) {
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param);
++		if (ret)
++			goto failed;
++		ret = smu_read_smc_arg(smu, max);
++		if (ret)
++			goto failed;
++	}
++
++	if (min) {
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param);
++		if (ret)
++			goto failed;
++		ret = smu_read_smc_arg(smu, min);
++		if (ret)
++			goto failed;
++	}
++
++failed:
++	mutex_unlock(&smu->mutex);
++	return ret;
++}
++
+ static const struct smu_funcs smu_v11_0_funcs = {
+ 	.init_microcode = smu_v11_0_init_microcode,
+ 	.load_microcode = smu_v11_0_load_microcode,
+@@ -1766,6 +1803,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
+ 	.baco_get_state = smu_v11_0_baco_get_state,
+ 	.baco_set_state = smu_v11_0_baco_set_state,
+ 	.baco_reset = smu_v11_0_baco_reset,
++	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+ };
+ 
+ void smu_v11_0_set_smu_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 0f5d08ae71ae..9d2280ca1f4b 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -319,6 +319,67 @@ static int smu_v12_0_populate_smc_tables(struct smu_context *smu)
+ 	return smu_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
+ }
+ 
++static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
++						 uint32_t *min, uint32_t *max)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (max) {
++		switch (clk_type) {
++		case SMU_GFXCLK:
++		case SMU_SCLK:
++			ret = smu_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency);
++			if (ret) {
++				pr_err("Attempt to get max GX frequency from SMC Failed !\n");
++				goto failed;
++			}
++			ret = smu_read_smc_arg(smu, max);
++			if (ret)
++				goto failed;
++			break;
++		case SMU_UCLK:
++			ret = smu_get_dpm_uclk_limited(smu, max, true);
++			if (ret)
++				goto failed;
++			break;
++		default:
++			ret = -EINVAL;
++			goto failed;
++
++		}
++	}
++
++	if (min) {
++		switch (clk_type) {
++		case SMU_GFXCLK:
++		case SMU_SCLK:
++			ret = smu_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency);
++			if (ret) {
++				pr_err("Attempt to get min GX frequency from SMC Failed !\n");
++				goto failed;
++			}
++			ret = smu_read_smc_arg(smu, min);
++			if (ret)
++				goto failed;
++			break;
++		case SMU_UCLK:
++			ret = smu_get_dpm_uclk_limited(smu, min, false);
++			if (ret)
++				goto failed;
++			break;
++		default:
++			ret = -EINVAL;
++			goto failed;
++		}
++
++	}
++failed:
++	mutex_unlock(&smu->mutex);
++	return ret;
++}
++
+ static const struct smu_funcs smu_v12_0_funcs = {
+ 	.check_fw_status = smu_v12_0_check_fw_status,
+ 	.check_fw_version = smu_v12_0_check_fw_version,
+@@ -332,6 +393,7 @@ static const struct smu_funcs smu_v12_0_funcs = {
+ 	.init_smc_tables = smu_v12_0_init_smc_tables,
+ 	.fini_smc_tables = smu_v12_0_fini_smc_tables,
+ 	.populate_smc_tables = smu_v12_0_populate_smc_tables,
++	.get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
+ };
+ 
+ void smu_v12_0_set_smu_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3631-drm-amd-display-Add-Renoir-registers-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3631-drm-amd-display-Add-Renoir-registers-v3.patch
new file mode 100644
index 00000000..2a832801
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3631-drm-amd-display-Add-Renoir-registers-v3.patch
@@ -0,0 +1,76063 @@
+From a55a6c0eff95908ce9f2de6fe6251d89af8c99c1 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 25 Jul 2019 15:51:41 -0400
+Subject: [PATCH 3631/4256] drm/amd/display: Add Renoir registers (v3)
+
+add registers for dcn, clk, and renoir ip offsets
+
+v2: header cleanup (Alex)
+v3: Add DPCS registers (Hersen)
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../include/asic_reg/clk/clk_10_0_2_offset.h  |    56 +
+ .../include/asic_reg/clk/clk_10_0_2_sh_mask.h |    73 +
+ .../include/asic_reg/dcn/dcn_2_1_0_offset.h   | 13862 ++++
+ .../include/asic_reg/dcn/dcn_2_1_0_sh_mask.h  | 56638 ++++++++++++++++
+ .../include/asic_reg/dcn/dpcs_2_1_0_offset.h  |   565 +
+ .../include/asic_reg/dcn/dpcs_2_1_0_sh_mask.h |  3430 +
+ .../gpu/drm/amd/include/renoir_ip_offset.h    |  1364 +
+ 7 files changed, 75988 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_offset.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_sh_mask.h
+ create mode 100644 drivers/gpu/drm/amd/include/renoir_ip_offset.h
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h
+new file mode 100644
+index 000000000000..2de450361fb5
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h
+@@ -0,0 +1,56 @@
++/*
++ * Copyright (C) 2019  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _clk_10_0_2_OFFSET_HEADER
++#define _clk_10_0_2_OFFSET_HEADER
++
++
++
++// addressBlock: clk_clk1_0_SmuClkDec
++// base address: 0x5b800
++#define mmCLK1_CLK_PLL_REQ                                                                             0x000f
++#define mmCLK1_CLK_PLL_REQ_BASE_IDX                                                                    1
++#define mmCLK1_CLK0_BYPASS_CNTL                                                                        0x0049
++#define mmCLK1_CLK0_BYPASS_CNTL_BASE_IDX                                                               1
++#define mmCLK1_CLK1_BYPASS_CNTL                                                                        0x0053
++#define mmCLK1_CLK1_BYPASS_CNTL_BASE_IDX                                                               1
++#define mmCLK1_CLK2_BYPASS_CNTL                                                                        0x005d
++#define mmCLK1_CLK2_BYPASS_CNTL_BASE_IDX                                                               1
++#define mmCLK1_CLK2_STATUS                                                                             0x005e
++#define mmCLK1_CLK2_STATUS_BASE_IDX                                                                    1
++#define mmCLK1_CLK3_DFS_CNTL                                                                           0x005f
++#define mmCLK1_CLK3_DFS_CNTL_BASE_IDX                                                                  1
++#define mmCLK1_CLK3_DS_CNTL                                                                            0x0060
++#define mmCLK1_CLK3_DS_CNTL_BASE_IDX                                                                   1
++#define mmCLK1_CLK3_ALLOW_DS                                                                           0x0061
++#define mmCLK1_CLK3_ALLOW_DS_BASE_IDX                                                                  1
++#define mmCLK1_CLK3_BYPASS_CNTL                                                                        0x0067
++#define mmCLK1_CLK3_BYPASS_CNTL_BASE_IDX                                                               1
++#define mmCLK1_CLK0_CURRENT_CNT                                                                        0x008a
++#define mmCLK1_CLK0_CURRENT_CNT_BASE_IDX                                                               1
++#define mmCLK1_CLK1_CURRENT_CNT                                                                        0x008b
++#define mmCLK1_CLK1_CURRENT_CNT_BASE_IDX                                                               1
++#define mmCLK1_CLK2_CURRENT_CNT                                                                        0x008c
++#define mmCLK1_CLK2_CURRENT_CNT_BASE_IDX                                                               1
++#define mmCLK1_CLK3_CURRENT_CNT                                                                        0x008d
++#define mmCLK1_CLK3_CURRENT_CNT_BASE_IDX                                                               1
++
++
++#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h
+new file mode 100644
+index 000000000000..c949d0e662db
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h
+@@ -0,0 +1,73 @@
++/*
++ * Copyright (C) 2019  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _clk_10_0_2_SH_MASK_HEADER
++#define _clk_10_0_2_SH_MASK_HEADER
++
++
++// addressBlock: clk_clk1_0_SmuClkDec
++//CLK1_CLK_PLL_REQ
++#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT                                                                   0x0
++#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT                                                                  0xc
++#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT                                                                  0x10
++#define CLK1_CLK_PLL_REQ__FbMult_int_MASK                                                                     0x000001FFL
++#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK                                                                    0x0000F000L
++#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK                                                                    0xFFFF0000L
++//CLK1_CLK0_BYPASS_CNTL
++#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT                                                         0x0
++#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV__SHIFT                                                         0x10
++#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK                                                           0x00000007L
++#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV_MASK                                                           0x000F0000L
++//CLK1_CLK1_BYPASS_CNTL
++#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT                                                         0x0
++#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV__SHIFT                                                         0x10
++#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK                                                           0x00000007L
++#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV_MASK                                                           0x000F0000L
++//CLK1_CLK2_BYPASS_CNTL
++#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT                                                         0x0
++#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT                                                         0x10
++#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK                                                           0x00000007L
++#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK                                                           0x000F0000L
++//CLK1_CLK3_DS_CNTL
++#define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT                                                              0x0
++#define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK                                                                0x00000007L
++//CLK1_CLK3_ALLOW_DS
++#define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS__SHIFT                                                              0x0
++#define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS_MASK                                                                0x00000001L
++//CLK1_CLK3_BYPASS_CNTL
++#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT                                                         0x0
++#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV__SHIFT                                                         0x10
++#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK                                                           0x00000007L
++#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV_MASK                                                           0x000F0000L
++//CLK1_CLK0_CURRENT_CNT
++#define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0
++#define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL
++//CLK1_CLK1_CURRENT_CNT
++#define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0
++#define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL
++//CLK1_CLK2_CURRENT_CNT
++#define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0
++#define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL
++//CLK1_CLK3_CURRENT_CNT
++#define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0
++#define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL
++
++
++#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
+new file mode 100644
+index 000000000000..be4249adb356
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
+@@ -0,0 +1,13862 @@
++/*
++ * Copyright (C) 2019  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _dcn_2_1_0_OFFSET_HEADER
++#define _dcn_2_1_0_OFFSET_HEADER
++
++
++
++// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
++// base address: 0x48
++#define mmVGA_MEM_WRITE_PAGE_ADDR                                                                      0x0000
++#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX                                                             0
++#define mmVGA_MEM_READ_PAGE_ADDR                                                                       0x0001
++#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX                                                              0
++
++
++// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986]
++// base address: 0x3b4
++#define mmCRTC8_IDX                                                                                    0x002d
++#define mmCRTC8_IDX_BASE_IDX                                                                           1
++#define mmCRTC8_DATA                                                                                   0x002d
++#define mmCRTC8_DATA_BASE_IDX                                                                          1
++#define mmGENFC_WT                                                                                     0x002e
++#define mmGENFC_WT_BASE_IDX                                                                            1
++#define mmGENS1                                                                                        0x002e
++#define mmGENS1_BASE_IDX                                                                               1
++#define mmATTRDW                                                                                       0x0030
++#define mmATTRDW_BASE_IDX                                                                              1
++#define mmATTRX                                                                                        0x0030
++#define mmATTRX_BASE_IDX                                                                               1
++#define mmATTRDR                                                                                       0x0030
++#define mmATTRDR_BASE_IDX                                                                              1
++#define mmGENMO_WT                                                                                     0x0030
++#define mmGENMO_WT_BASE_IDX                                                                            1
++#define mmGENS0                                                                                        0x0030
++#define mmGENS0_BASE_IDX                                                                               1
++#define mmGENENB                                                                                       0x0030
++#define mmGENENB_BASE_IDX                                                                              1
++#define mmSEQ8_IDX                                                                                     0x0031
++#define mmSEQ8_IDX_BASE_IDX                                                                            1
++#define mmSEQ8_DATA                                                                                    0x0031
++#define mmSEQ8_DATA_BASE_IDX                                                                           1
++#define mmDAC_MASK                                                                                     0x0031
++#define mmDAC_MASK_BASE_IDX                                                                            1
++#define mmDAC_R_INDEX                                                                                  0x0031
++#define mmDAC_R_INDEX_BASE_IDX                                                                         1
++#define mmDAC_W_INDEX                                                                                  0x0032
++#define mmDAC_W_INDEX_BASE_IDX                                                                         1
++#define mmDAC_DATA                                                                                     0x0032
++#define mmDAC_DATA_BASE_IDX                                                                            1
++#define mmGENFC_RD                                                                                     0x0032
++#define mmGENFC_RD_BASE_IDX                                                                            1
++#define mmGENMO_RD                                                                                     0x0033
++#define mmGENMO_RD_BASE_IDX                                                                            1
++#define mmGRPH8_IDX                                                                                    0x0033
++#define mmGRPH8_IDX_BASE_IDX                                                                           1
++#define mmGRPH8_DATA                                                                                   0x0033
++#define mmGRPH8_DATA_BASE_IDX                                                                          1
++#define mmCRTC8_IDX_1                                                                                  0x0035
++#define mmCRTC8_IDX_1_BASE_IDX                                                                         1
++#define mmCRTC8_DATA_1                                                                                 0x0035
++#define mmCRTC8_DATA_1_BASE_IDX                                                                        1
++#define mmGENFC_WT_1                                                                                   0x0036
++#define mmGENFC_WT_1_BASE_IDX                                                                          1
++#define mmGENS1_1                                                                                      0x0036
++#define mmGENS1_1_BASE_IDX                                                                             1
++
++
++// addressBlock: dce_dc_mmhubbub_vga_dispdec
++// base address: 0x0
++#define mmVGA_RENDER_CONTROL                                                                           0x0000
++#define mmVGA_RENDER_CONTROL_BASE_IDX                                                                  1
++#define mmVGA_SEQUENCER_RESET_CONTROL                                                                  0x0001
++#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1
++#define mmVGA_MODE_CONTROL                                                                             0x0002
++#define mmVGA_MODE_CONTROL_BASE_IDX                                                                    1
++#define mmVGA_SURFACE_PITCH_SELECT                                                                     0x0003
++#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX                                                            1
++#define mmVGA_MEMORY_BASE_ADDRESS                                                                      0x0004
++#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX                                                             1
++#define mmVGA_TEST_DEBUG_INDEX                                                                         0x0005
++#define mmVGA_TEST_DEBUG_INDEX_BASE_IDX                                                                1
++#define mmVGA_DISPBUF1_SURFACE_ADDR                                                                    0x0006
++#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX                                                           1
++#define mmVGA_TEST_DEBUG_DATA                                                                          0x0007
++#define mmVGA_TEST_DEBUG_DATA_BASE_IDX                                                                 1
++#define mmVGA_DISPBUF2_SURFACE_ADDR                                                                    0x0008
++#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX                                                           1
++#define mmVGA_MEMORY_BASE_ADDRESS_HIGH                                                                 0x0009
++#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX                                                        1
++#define mmVGA_HDP_CONTROL                                                                              0x000a
++#define mmVGA_HDP_CONTROL_BASE_IDX                                                                     1
++#define mmVGA_CACHE_CONTROL                                                                            0x000b
++#define mmVGA_CACHE_CONTROL_BASE_IDX                                                                   1
++#define mmD1VGA_CONTROL                                                                                0x000c
++#define mmD1VGA_CONTROL_BASE_IDX                                                                       1
++#define mmVGA_SECURITY_LEVEL                                                                           0x000d
++#define mmVGA_SECURITY_LEVEL_BASE_IDX                                                                  1
++#define mmD2VGA_CONTROL                                                                                0x000e
++#define mmD2VGA_CONTROL_BASE_IDX                                                                       1
++#define mmVGA_HW_DEBUG                                                                                 0x000f
++#define mmVGA_HW_DEBUG_BASE_IDX                                                                        1
++#define mmVGA_STATUS                                                                                   0x0010
++#define mmVGA_STATUS_BASE_IDX                                                                          1
++#define mmVGA_INTERRUPT_CONTROL                                                                        0x0011
++#define mmVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1
++#define mmVGA_STATUS_CLEAR                                                                             0x0012
++#define mmVGA_STATUS_CLEAR_BASE_IDX                                                                    1
++#define mmVGA_INTERRUPT_STATUS                                                                         0x0013
++#define mmVGA_INTERRUPT_STATUS_BASE_IDX                                                                1
++#define mmVGA_MAIN_CONTROL                                                                             0x0014
++#define mmVGA_MAIN_CONTROL_BASE_IDX                                                                    1
++#define mmVGA_TEST_CONTROL                                                                             0x0015
++#define mmVGA_TEST_CONTROL_BASE_IDX                                                                    1
++#define mmVGA_DEBUG_READBACK_INDEX                                                                     0x0016
++#define mmVGA_DEBUG_READBACK_INDEX_BASE_IDX                                                            1
++#define mmVGA_DEBUG_READBACK_DATA                                                                      0x0017
++#define mmVGA_DEBUG_READBACK_DATA_BASE_IDX                                                             1
++#define mmVGA_QOS_CTRL                                                                                 0x0018
++#define mmVGA_QOS_CTRL_BASE_IDX                                                                        1
++#define mmD3VGA_CONTROL                                                                                0x0038
++#define mmD3VGA_CONTROL_BASE_IDX                                                                       1
++#define mmD4VGA_CONTROL                                                                                0x0039
++#define mmD4VGA_CONTROL_BASE_IDX                                                                       1
++#define mmD5VGA_CONTROL                                                                                0x003a
++#define mmD5VGA_CONTROL_BASE_IDX                                                                       1
++#define mmD6VGA_CONTROL                                                                                0x003b
++#define mmD6VGA_CONTROL_BASE_IDX                                                                       1
++#define mmVGA_SOURCE_SELECT                                                                            0x003c
++#define mmVGA_SOURCE_SELECT_BASE_IDX                                                                   1
++
++
++// addressBlock: dce_dc_dccg_dccg_dispdec
++// base address: 0x0
++#define mmPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040
++#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
++#define mmPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041
++#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
++#define mmPHYPLLC_PIXCLK_RESYNC_CNTL                                                                   0x0042
++#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
++#define mmPHYPLLD_PIXCLK_RESYNC_CNTL                                                                   0x0043
++#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
++#define mmDP_DTO_DBUF_EN                                                                               0x0044
++#define mmDP_DTO_DBUF_EN_BASE_IDX                                                                      1
++#define mmDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048
++#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1
++#define mmREFCLK_CNTL                                                                                  0x0049
++#define mmREFCLK_CNTL_BASE_IDX                                                                         1
++#define mmREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b
++#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
++#define mmPHYPLLE_PIXCLK_RESYNC_CNTL                                                                   0x004c
++#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
++#define mmDCCG_PERFMON_CNTL2                                                                           0x004e
++#define mmDCCG_PERFMON_CNTL2_BASE_IDX                                                                  1
++#define mmDCCG_DS_DTO_INCR                                                                             0x0053
++#define mmDCCG_DS_DTO_INCR_BASE_IDX                                                                    1
++#define mmDCCG_DS_DTO_MODULO                                                                           0x0054
++#define mmDCCG_DS_DTO_MODULO_BASE_IDX                                                                  1
++#define mmDCCG_DS_CNTL                                                                                 0x0055
++#define mmDCCG_DS_CNTL_BASE_IDX                                                                        1
++#define mmDCCG_DS_HW_CAL_INTERVAL                                                                      0x0056
++#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX                                                             1
++#define mmDPREFCLK_CNTL                                                                                0x0058
++#define mmDPREFCLK_CNTL_BASE_IDX                                                                       1
++#define mmDCE_VERSION                                                                                  0x005e
++#define mmDCE_VERSION_BASE_IDX                                                                         1
++#define mmDCCG_GTC_CNTL                                                                                0x0060
++#define mmDCCG_GTC_CNTL_BASE_IDX                                                                       1
++#define mmDCCG_GTC_DTO_INCR                                                                            0x0061
++#define mmDCCG_GTC_DTO_INCR_BASE_IDX                                                                   1
++#define mmDCCG_GTC_DTO_MODULO                                                                          0x0062
++#define mmDCCG_GTC_DTO_MODULO_BASE_IDX                                                                 1
++#define mmDCCG_GTC_CURRENT                                                                             0x0063
++#define mmDCCG_GTC_CURRENT_BASE_IDX                                                                    1
++#define mmDSCCLK0_DTO_PARAM                                                                            0x006c
++#define mmDSCCLK0_DTO_PARAM_BASE_IDX                                                                   1
++#define mmDSCCLK1_DTO_PARAM                                                                            0x006d
++#define mmDSCCLK1_DTO_PARAM_BASE_IDX                                                                   1
++#define mmDSCCLK2_DTO_PARAM                                                                            0x006e
++#define mmDSCCLK2_DTO_PARAM_BASE_IDX                                                                   1
++#define mmMILLISECOND_TIME_BASE_DIV                                                                    0x0070
++#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1
++#define mmDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071
++#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1
++#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072
++#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
++#define mmDCCG_PERFMON_CNTL                                                                            0x0073
++#define mmDCCG_PERFMON_CNTL_BASE_IDX                                                                   1
++#define mmDCCG_GATE_DISABLE_CNTL                                                                       0x0074
++#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1
++#define mmDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075
++#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1
++#define mmSOCCLK_CGTT_BLK_CTRL_REG                                                                     0x0076
++#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
++#define mmDCCG_CAC_STATUS                                                                              0x0077
++#define mmDCCG_CAC_STATUS_BASE_IDX                                                                     1
++#define mmMICROSECOND_TIME_BASE_DIV                                                                    0x007b
++#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1
++#define mmDCCG_GATE_DISABLE_CNTL2                                                                      0x007c
++#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1
++#define mmSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d
++#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
++#define mmDCCG_DISP_CNTL_REG                                                                           0x007f
++#define mmDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1
++#define mmOTG0_PIXEL_RATE_CNTL                                                                         0x0080
++#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX                                                                1
++#define mmDP_DTO0_PHASE                                                                                0x0081
++#define mmDP_DTO0_PHASE_BASE_IDX                                                                       1
++#define mmDP_DTO0_MODULO                                                                               0x0082
++#define mmDP_DTO0_MODULO_BASE_IDX                                                                      1
++#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0083
++#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
++#define mmOTG1_PIXEL_RATE_CNTL                                                                         0x0084
++#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX                                                                1
++#define mmDP_DTO1_PHASE                                                                                0x0085
++#define mmDP_DTO1_PHASE_BASE_IDX                                                                       1
++#define mmDP_DTO1_MODULO                                                                               0x0086
++#define mmDP_DTO1_MODULO_BASE_IDX                                                                      1
++#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0087
++#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
++#define mmOTG2_PIXEL_RATE_CNTL                                                                         0x0088
++#define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX                                                                1
++#define mmDP_DTO2_PHASE                                                                                0x0089
++#define mmDP_DTO2_PHASE_BASE_IDX                                                                       1
++#define mmDP_DTO2_MODULO                                                                               0x008a
++#define mmDP_DTO2_MODULO_BASE_IDX                                                                      1
++#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008b
++#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
++#define mmOTG3_PIXEL_RATE_CNTL                                                                         0x008c
++#define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX                                                                1
++#define mmDP_DTO3_PHASE                                                                                0x008d
++#define mmDP_DTO3_PHASE_BASE_IDX                                                                       1
++#define mmDP_DTO3_MODULO                                                                               0x008e
++#define mmDP_DTO3_MODULO_BASE_IDX                                                                      1
++#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008f
++#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
++#define mmDPPCLK_CGTT_BLK_CTRL_REG                                                                     0x0098
++#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
++#define mmDPPCLK0_DTO_PARAM                                                                            0x0099
++#define mmDPPCLK0_DTO_PARAM_BASE_IDX                                                                   1
++#define mmDPPCLK1_DTO_PARAM                                                                            0x009a
++#define mmDPPCLK1_DTO_PARAM_BASE_IDX                                                                   1
++#define mmDPPCLK2_DTO_PARAM                                                                            0x009b
++#define mmDPPCLK2_DTO_PARAM_BASE_IDX                                                                   1
++#define mmDPPCLK3_DTO_PARAM                                                                            0x009c
++#define mmDPPCLK3_DTO_PARAM_BASE_IDX                                                                   1
++#define mmDCCG_CAC_STATUS2                                                                             0x009f
++#define mmDCCG_CAC_STATUS2_BASE_IDX                                                                    1
++#define mmSYMCLKA_CLOCK_ENABLE                                                                         0x00a0
++#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1
++#define mmSYMCLKB_CLOCK_ENABLE                                                                         0x00a1
++#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1
++#define mmSYMCLKC_CLOCK_ENABLE                                                                         0x00a2
++#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX                                                                1
++#define mmSYMCLKD_CLOCK_ENABLE                                                                         0x00a3
++#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX                                                                1
++#define mmSYMCLKE_CLOCK_ENABLE                                                                         0x00a4
++#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX                                                                1
++#define mmDCCG_SOFT_RESET                                                                              0x00a6
++#define mmDCCG_SOFT_RESET_BASE_IDX                                                                     1
++#define mmDSCCLK_DTO_CTRL                                                                              0x00a7
++#define mmDSCCLK_DTO_CTRL_BASE_IDX                                                                     1
++#define mmDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab
++#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1
++#define mmDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac
++#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1
++#define mmDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad
++#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1
++#define mmDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae
++#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1
++#define mmDCCG_AUDIO_DTO1_MODULE                                                                       0x00af
++#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1
++#define mmDCCG_VSYNC_OTG0_LATCH_VALUE                                                                  0x00b0
++#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX                                                         1
++#define mmDCCG_VSYNC_OTG1_LATCH_VALUE                                                                  0x00b1
++#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX                                                         1
++#define mmDCCG_VSYNC_OTG2_LATCH_VALUE                                                                  0x00b2
++#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX                                                         1
++#define mmDCCG_VSYNC_OTG3_LATCH_VALUE                                                                  0x00b3
++#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX                                                         1
++#define mmDCCG_VSYNC_OTG4_LATCH_VALUE                                                                  0x00b4
++#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX                                                         1
++#define mmDCCG_VSYNC_OTG5_LATCH_VALUE                                                                  0x00b5
++#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX                                                         1
++#define mmDPPCLK_DTO_CTRL                                                                              0x00b6
++#define mmDPPCLK_DTO_CTRL_BASE_IDX                                                                     1
++#define mmDCCG_VSYNC_CNT_CTRL                                                                          0x00b8
++#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX                                                                 1
++#define mmDCCG_VSYNC_CNT_INT_CTRL                                                                      0x00b9
++#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX                                                             1
++#define mmFORCE_SYMCLK_DISABLE                                                                         0x00ba
++#define mmFORCE_SYMCLK_DISABLE_BASE_IDX                                                                1
++#define mmDCCG_TEST_CLK_SEL                                                                            0x00be
++#define mmDCCG_TEST_CLK_SEL_BASE_IDX                                                                   1
++
++
++// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
++// base address: 0x0
++#define mmDENTIST_DISPCLK_CNTL                                                                         0x0064
++#define mmDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1
++
++
++// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
++// base address: 0x0
++#define mmDC_PERFMON0_PERFCOUNTER_CNTL                                                                 0x0000
++#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX                                                        2
++#define mmDC_PERFMON0_PERFCOUNTER_CNTL2                                                                0x0001
++#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
++#define mmDC_PERFMON0_PERFCOUNTER_STATE                                                                0x0002
++#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX                                                       2
++#define mmDC_PERFMON0_PERFMON_CNTL                                                                     0x0003
++#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX                                                            2
++#define mmDC_PERFMON0_PERFMON_CNTL2                                                                    0x0004
++#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX                                                           2
++#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                                          0x0005
++#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
++#define mmDC_PERFMON0_PERFMON_CVALUE_LOW                                                               0x0006
++#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
++#define mmDC_PERFMON0_PERFMON_HI                                                                       0x0007
++#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX                                                              2
++#define mmDC_PERFMON0_PERFMON_LOW                                                                      0x0008
++#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
++// base address: 0x30
++#define mmDC_PERFMON1_PERFCOUNTER_CNTL                                                                 0x000c
++#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX                                                        2
++#define mmDC_PERFMON1_PERFCOUNTER_CNTL2                                                                0x000d
++#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
++#define mmDC_PERFMON1_PERFCOUNTER_STATE                                                                0x000e
++#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX                                                       2
++#define mmDC_PERFMON1_PERFMON_CNTL                                                                     0x000f
++#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX                                                            2
++#define mmDC_PERFMON1_PERFMON_CNTL2                                                                    0x0010
++#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX                                                           2
++#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                                          0x0011
++#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
++#define mmDC_PERFMON1_PERFMON_CVALUE_LOW                                                               0x0012
++#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
++#define mmDC_PERFMON1_PERFMON_HI                                                                       0x0013
++#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX                                                              2
++#define mmDC_PERFMON1_PERFMON_LOW                                                                      0x0014
++#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_dccg_dccg_pll_dispdec
++// base address: 0x0
++#define mmPLL_MACRO_CNTL_RESERVED0                                                                     0x0018
++#define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX                                                            2
++#define mmPLL_MACRO_CNTL_RESERVED1                                                                     0x0019
++#define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX                                                            2
++#define mmPLL_MACRO_CNTL_RESERVED2                                                                     0x001a
++#define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX                                                            2
++#define mmPLL_MACRO_CNTL_RESERVED3                                                                     0x001b
++#define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX                                                            2
++#define mmPLL_MACRO_CNTL_RESERVED4                                                                     0x001c
++#define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX                                                            2
++#define mmPLL_MACRO_CNTL_RESERVED5                                                                     0x001d
++#define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX                                                            2
++#define mmPLL_MACRO_CNTL_RESERVED6                                                                     0x001e
++#define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX                                                            2
++#define mmPLL_MACRO_CNTL_RESERVED7                                                                     0x001f
++#define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX                                                            2
++#define mmPLL_MACRO_CNTL_RESERVED8                                                                     0x0020
++#define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX                                                            2
++#define mmPLL_MACRO_CNTL_RESERVED9                                                                     0x0021
++#define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX                                                            2
++#define mmPLL_MACRO_CNTL_RESERVED10                                                                    0x0022
++#define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED11                                                                    0x0023
++#define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED12                                                                    0x0024
++#define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED13                                                                    0x0025
++#define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED14                                                                    0x0026
++#define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED15                                                                    0x0027
++#define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED16                                                                    0x0028
++#define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED17                                                                    0x0029
++#define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED18                                                                    0x002a
++#define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED19                                                                    0x002b
++#define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED20                                                                    0x002c
++#define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED21                                                                    0x002d
++#define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED22                                                                    0x002e
++#define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED23                                                                    0x002f
++#define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED24                                                                    0x0030
++#define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED25                                                                    0x0031
++#define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED26                                                                    0x0032
++#define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED27                                                                    0x0033
++#define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED28                                                                    0x0034
++#define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED29                                                                    0x0035
++#define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED30                                                                    0x0036
++#define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED31                                                                    0x0037
++#define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED32                                                                    0x0038
++#define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED33                                                                    0x0039
++#define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED34                                                                    0x003a
++#define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED35                                                                    0x003b
++#define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED36                                                                    0x003c
++#define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED37                                                                    0x003d
++#define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED38                                                                    0x003e
++#define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED39                                                                    0x003f
++#define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED40                                                                    0x0040
++#define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX                                                           2
++#define mmPLL_MACRO_CNTL_RESERVED41                                                                    0x0041
++#define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX                                                           2
++
++
++// addressBlock: dce_dc_dmu_rbbmif_dispdec
++// base address: 0x0
++#define mmRBBMIF_TIMEOUT                                                                               0x005b
++#define mmRBBMIF_TIMEOUT_BASE_IDX                                                                      2
++#define mmRBBMIF_STATUS                                                                                0x005c
++#define mmRBBMIF_STATUS_BASE_IDX                                                                       2
++#define mmRBBMIF_STATUS_2                                                                              0x005d
++#define mmRBBMIF_STATUS_2_BASE_IDX                                                                     2
++#define mmRBBMIF_INT_STATUS                                                                            0x005e
++#define mmRBBMIF_INT_STATUS_BASE_IDX                                                                   2
++#define mmRBBMIF_TIMEOUT_DIS                                                                           0x005f
++#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2
++#define mmRBBMIF_TIMEOUT_DIS_2                                                                         0x0060
++#define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX                                                                2
++#define mmRBBMIF_STATUS_FLAG                                                                           0x0061
++#define mmRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2
++
++
++// addressBlock: dce_dc_dmu_dc_pg_dispdec
++// base address: 0x0
++#define mmDOMAIN0_PG_CONFIG                                                                            0x0080
++#define mmDOMAIN0_PG_CONFIG_BASE_IDX                                                                   2
++#define mmDOMAIN0_PG_STATUS                                                                            0x0081
++#define mmDOMAIN0_PG_STATUS_BASE_IDX                                                                   2
++#define mmDOMAIN1_PG_CONFIG                                                                            0x0082
++#define mmDOMAIN1_PG_CONFIG_BASE_IDX                                                                   2
++#define mmDOMAIN1_PG_STATUS                                                                            0x0083
++#define mmDOMAIN1_PG_STATUS_BASE_IDX                                                                   2
++#define mmDOMAIN2_PG_CONFIG                                                                            0x0084
++#define mmDOMAIN2_PG_CONFIG_BASE_IDX                                                                   2
++#define mmDOMAIN2_PG_STATUS                                                                            0x0085
++#define mmDOMAIN2_PG_STATUS_BASE_IDX                                                                   2
++#define mmDOMAIN3_PG_CONFIG                                                                            0x0086
++#define mmDOMAIN3_PG_CONFIG_BASE_IDX                                                                   2
++#define mmDOMAIN3_PG_STATUS                                                                            0x0087
++#define mmDOMAIN3_PG_STATUS_BASE_IDX                                                                   2
++#define mmDOMAIN4_PG_CONFIG                                                                            0x0088
++#define mmDOMAIN4_PG_CONFIG_BASE_IDX                                                                   2
++#define mmDOMAIN4_PG_STATUS                                                                            0x0089
++#define mmDOMAIN4_PG_STATUS_BASE_IDX                                                                   2
++#define mmDOMAIN5_PG_CONFIG                                                                            0x008a
++#define mmDOMAIN5_PG_CONFIG_BASE_IDX                                                                   2
++#define mmDOMAIN5_PG_STATUS                                                                            0x008b
++#define mmDOMAIN5_PG_STATUS_BASE_IDX                                                                   2
++#define mmDOMAIN6_PG_CONFIG                                                                            0x008c
++#define mmDOMAIN6_PG_CONFIG_BASE_IDX                                                                   2
++#define mmDOMAIN6_PG_STATUS                                                                            0x008d
++#define mmDOMAIN6_PG_STATUS_BASE_IDX                                                                   2
++#define mmDOMAIN7_PG_CONFIG                                                                            0x008e
++#define mmDOMAIN7_PG_CONFIG_BASE_IDX                                                                   2
++#define mmDOMAIN7_PG_STATUS                                                                            0x008f
++#define mmDOMAIN7_PG_STATUS_BASE_IDX                                                                   2
++#define mmDOMAIN16_PG_CONFIG                                                                           0x00a1
++#define mmDOMAIN16_PG_CONFIG_BASE_IDX                                                                  2
++#define mmDOMAIN16_PG_STATUS                                                                           0x00a2
++#define mmDOMAIN16_PG_STATUS_BASE_IDX                                                                  2
++#define mmDOMAIN17_PG_CONFIG                                                                           0x00a3
++#define mmDOMAIN17_PG_CONFIG_BASE_IDX                                                                  2
++#define mmDOMAIN17_PG_STATUS                                                                           0x00a4
++#define mmDOMAIN17_PG_STATUS_BASE_IDX                                                                  2
++#define mmDOMAIN18_PG_CONFIG                                                                           0x00a5
++#define mmDOMAIN18_PG_CONFIG_BASE_IDX                                                                  2
++#define mmDOMAIN18_PG_STATUS                                                                           0x00a6
++#define mmDOMAIN18_PG_STATUS_BASE_IDX                                                                  2
++#define mmDCPG_INTERRUPT_STATUS                                                                        0x00ad
++#define mmDCPG_INTERRUPT_STATUS_BASE_IDX                                                               2
++#define mmDCPG_INTERRUPT_STATUS_2                                                                      0x00ae
++#define mmDCPG_INTERRUPT_STATUS_2_BASE_IDX                                                             2
++#define mmDCPG_INTERRUPT_CONTROL_1                                                                     0x00af
++#define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2
++#define mmDCPG_INTERRUPT_CONTROL_2                                                                     0x00b0
++#define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX                                                            2
++#define mmDCPG_INTERRUPT_CONTROL_3                                                                     0x00b1
++#define mmDCPG_INTERRUPT_CONTROL_3_BASE_IDX                                                            2
++#define mmDC_IP_REQUEST_CNTL                                                                           0x00b2
++#define mmDC_IP_REQUEST_CNTL_BASE_IDX                                                                  2
++
++
++// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
++// base address: 0x2f8
++#define mmDC_PERFMON2_PERFCOUNTER_CNTL                                                                 0x00be
++#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX                                                        2
++#define mmDC_PERFMON2_PERFCOUNTER_CNTL2                                                                0x00bf
++#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
++#define mmDC_PERFMON2_PERFCOUNTER_STATE                                                                0x00c0
++#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX                                                       2
++#define mmDC_PERFMON2_PERFMON_CNTL                                                                     0x00c1
++#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX                                                            2
++#define mmDC_PERFMON2_PERFMON_CNTL2                                                                    0x00c2
++#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX                                                           2
++#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                                          0x00c3
++#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
++#define mmDC_PERFMON2_PERFMON_CVALUE_LOW                                                               0x00c4
++#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
++#define mmDC_PERFMON2_PERFMON_HI                                                                       0x00c5
++#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX                                                              2
++#define mmDC_PERFMON2_PERFMON_LOW                                                                      0x00c6
++#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_dmu_dmu_misc_dispdec
++// base address: 0x0
++#define mmCC_DC_PIPE_DIS                                                                               0x00ca
++#define mmCC_DC_PIPE_DIS_BASE_IDX                                                                      2
++#define mmDMU_CLK_CNTL                                                                                 0x00cb
++#define mmDMU_CLK_CNTL_BASE_IDX                                                                        2
++#define mmDMU_MEM_PWR_CNTL                                                                             0x00cc
++#define mmDMU_MEM_PWR_CNTL_BASE_IDX                                                                    2
++#define mmDMCU_SMU_INTERRUPT_CNTL                                                                      0x00cd
++#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX                                                             2
++#define mmSMU_INTERRUPT_CONTROL                                                                        0x00ce
++#define mmSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2
++#define mmDMU_MISC_ALLOW_DS_FORCE                                                                      0x00d6
++#define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_dmu_dmcu_dispdec
++// base address: 0x0
++#define mmDMCU_CTRL                                                                                    0x00da
++#define mmDMCU_CTRL_BASE_IDX                                                                           2
++#define mmDMCU_STATUS                                                                                  0x00db
++#define mmDMCU_STATUS_BASE_IDX                                                                         2
++#define mmDMCU_PC_START_ADDR                                                                           0x00dc
++#define mmDMCU_PC_START_ADDR_BASE_IDX                                                                  2
++#define mmDMCU_FW_START_ADDR                                                                           0x00dd
++#define mmDMCU_FW_START_ADDR_BASE_IDX                                                                  2
++#define mmDMCU_FW_END_ADDR                                                                             0x00de
++#define mmDMCU_FW_END_ADDR_BASE_IDX                                                                    2
++#define mmDMCU_FW_ISR_START_ADDR                                                                       0x00df
++#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX                                                              2
++#define mmDMCU_FW_CS_HI                                                                                0x00e0
++#define mmDMCU_FW_CS_HI_BASE_IDX                                                                       2
++#define mmDMCU_FW_CS_LO                                                                                0x00e1
++#define mmDMCU_FW_CS_LO_BASE_IDX                                                                       2
++#define mmDMCU_RAM_ACCESS_CTRL                                                                         0x00e2
++#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX                                                                2
++#define mmDMCU_ERAM_WR_CTRL                                                                            0x00e3
++#define mmDMCU_ERAM_WR_CTRL_BASE_IDX                                                                   2
++#define mmDMCU_ERAM_WR_DATA                                                                            0x00e4
++#define mmDMCU_ERAM_WR_DATA_BASE_IDX                                                                   2
++#define mmDMCU_ERAM_RD_CTRL                                                                            0x00e5
++#define mmDMCU_ERAM_RD_CTRL_BASE_IDX                                                                   2
++#define mmDMCU_ERAM_RD_DATA                                                                            0x00e6
++#define mmDMCU_ERAM_RD_DATA_BASE_IDX                                                                   2
++#define mmDMCU_IRAM_WR_CTRL                                                                            0x00e7
++#define mmDMCU_IRAM_WR_CTRL_BASE_IDX                                                                   2
++#define mmDMCU_IRAM_WR_DATA                                                                            0x00e8
++#define mmDMCU_IRAM_WR_DATA_BASE_IDX                                                                   2
++#define mmDMCU_IRAM_RD_CTRL                                                                            0x00e9
++#define mmDMCU_IRAM_RD_CTRL_BASE_IDX                                                                   2
++#define mmDMCU_IRAM_RD_DATA                                                                            0x00ea
++#define mmDMCU_IRAM_RD_DATA_BASE_IDX                                                                   2
++#define mmDMCU_EVENT_TRIGGER                                                                           0x00eb
++#define mmDMCU_EVENT_TRIGGER_BASE_IDX                                                                  2
++#define mmDMCU_UC_INTERNAL_INT_STATUS                                                                  0x00ec
++#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX                                                         2
++#define mmDMCU_SS_INTERRUPT_CNTL_STATUS                                                                0x00ed
++#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX                                                       2
++#define mmDMCU_INTERRUPT_STATUS                                                                        0x00ee
++#define mmDMCU_INTERRUPT_STATUS_BASE_IDX                                                               2
++#define mmDMCU_INTERRUPT_STATUS_1                                                                      0x00ef
++#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX                                                             2
++#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK                                                               0x00f0
++#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX                                                      2
++#define mmDMCU_INTERRUPT_TO_UC_EN_MASK                                                                 0x00f1
++#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX                                                        2
++#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1                                                               0x00f2
++#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX                                                      2
++#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL                                                            0x00f3
++#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX                                                   2
++#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1                                                          0x00f4
++#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX                                                 2
++#define mmDC_DMCU_SCRATCH                                                                              0x00f5
++#define mmDC_DMCU_SCRATCH_BASE_IDX                                                                     2
++#define mmDMCU_INT_CNT                                                                                 0x00f6
++#define mmDMCU_INT_CNT_BASE_IDX                                                                        2
++#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS                                                               0x00f7
++#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX                                                      2
++#define mmDMCU_UC_CLK_GATING_CNTL                                                                      0x00f8
++#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX                                                             2
++#define mmMASTER_COMM_DATA_REG1                                                                        0x00f9
++#define mmMASTER_COMM_DATA_REG1_BASE_IDX                                                               2
++#define mmMASTER_COMM_DATA_REG2                                                                        0x00fa
++#define mmMASTER_COMM_DATA_REG2_BASE_IDX                                                               2
++#define mmMASTER_COMM_DATA_REG3                                                                        0x00fb
++#define mmMASTER_COMM_DATA_REG3_BASE_IDX                                                               2
++#define mmMASTER_COMM_CMD_REG                                                                          0x00fc
++#define mmMASTER_COMM_CMD_REG_BASE_IDX                                                                 2
++#define mmMASTER_COMM_CNTL_REG                                                                         0x00fd
++#define mmMASTER_COMM_CNTL_REG_BASE_IDX                                                                2
++#define mmSLAVE_COMM_DATA_REG1                                                                         0x00fe
++#define mmSLAVE_COMM_DATA_REG1_BASE_IDX                                                                2
++#define mmSLAVE_COMM_DATA_REG2                                                                         0x00ff
++#define mmSLAVE_COMM_DATA_REG2_BASE_IDX                                                                2
++#define mmSLAVE_COMM_DATA_REG3                                                                         0x0100
++#define mmSLAVE_COMM_DATA_REG3_BASE_IDX                                                                2
++#define mmSLAVE_COMM_CMD_REG                                                                           0x0101
++#define mmSLAVE_COMM_CMD_REG_BASE_IDX                                                                  2
++#define mmSLAVE_COMM_CNTL_REG                                                                          0x0102
++#define mmSLAVE_COMM_CNTL_REG_BASE_IDX                                                                 2
++#define mmDMCU_PERFMON_INTERRUPT_STATUS1                                                               0x0105
++#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX                                                      2
++#define mmDMCU_PERFMON_INTERRUPT_STATUS2                                                               0x0106
++#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX                                                      2
++#define mmDMCU_PERFMON_INTERRUPT_STATUS3                                                               0x0107
++#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX                                                      2
++#define mmDMCU_PERFMON_INTERRUPT_STATUS4                                                               0x0108
++#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX                                                      2
++#define mmDMCU_PERFMON_INTERRUPT_STATUS5                                                               0x0109
++#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX                                                      2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1                                                        0x010a
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                               2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2                                                        0x010b
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX                                               2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3                                                        0x010c
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX                                               2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4                                                        0x010d
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX                                               2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5                                                        0x010e
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX                                               2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                   0x010f
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                          2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2                                                   0x0110
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX                                          2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3                                                   0x0111
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX                                          2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4                                                   0x0112
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX                                          2
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5                                                   0x0113
++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX                                          2
++#define mmDMCU_DPRX_INTERRUPT_STATUS1                                                                  0x0114
++#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX                                                         2
++#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1                                                           0x0115
++#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                                  2
++#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                      0x0116
++#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                             2
++#define mmDMCU_INTERRUPT_STATUS_CONTINUE                                                               0x0119
++#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
++#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE                                                        0x011a
++#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX                                               2
++#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE                                                   0x011b
++#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX                                          2
++#define mmDMCU_INT_CNT_CONTINUE                                                                        0x011c
++#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX                                                               2
++#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2                                                      0x011d
++#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX                                             2
++#define mmDMCU_INTERRUPT_STATUS_2                                                                      0x011e
++#define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX                                                             2
++#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2                                                               0x011f
++#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX                                                      2
++
++
++// addressBlock: dce_dc_dmu_ihc_dispdec
++// base address: 0x0
++#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x0126
++#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2
++#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP                                                         0x0127
++#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX                                                2
++#define mmDC_GPU_TIMER_READ                                                                            0x0128
++#define mmDC_GPU_TIMER_READ_BASE_IDX                                                                   2
++#define mmDC_GPU_TIMER_READ_CNTL                                                                       0x0129
++#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
++#define mmDISP_INTERRUPT_STATUS                                                                        0x012a
++#define mmDISP_INTERRUPT_STATUS_BASE_IDX                                                               2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE                                                               0x012b
++#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x012c
++#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x012d
++#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x012e
++#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x012f
++#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x0130
++#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x0131
++#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x0132
++#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x0133
++#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x0134
++#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x0135
++#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE12                                                             0x0136
++#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX                                                    2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE13                                                             0x0137
++#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX                                                    2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE14                                                             0x0138
++#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX                                                    2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE15                                                             0x0139
++#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX                                                    2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE16                                                             0x013a
++#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX                                                    2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE17                                                             0x013b
++#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX                                                    2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE18                                                             0x013c
++#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX                                                    2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE19                                                             0x013d
++#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX                                                    2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE20                                                             0x013e
++#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX                                                    2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE21                                                             0x013f
++#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX                                                    2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE22                                                             0x0140
++#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX                                                    2
++#define mmDC_GPU_TIMER_START_POSITION_VREADY                                                           0x0141
++#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX                                                  2
++#define mmDC_GPU_TIMER_START_POSITION_FLIP                                                             0x0142
++#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX                                                    2
++#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK                                                 0x0143
++#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX                                        2
++#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY                                                        0x0144
++#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX                                               2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE23                                                             0x0145
++#define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX                                                    2
++#define mmDISP_INTERRUPT_STATUS_CONTINUE24                                                             0x0146
++#define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX                                                    2
++#define mmDCCG_INTERRUPT_DEST                                                                          0x0147
++#define mmDCCG_INTERRUPT_DEST_BASE_IDX                                                                 2
++#define mmDMU_INTERRUPT_DEST                                                                           0x0148
++#define mmDMU_INTERRUPT_DEST_BASE_IDX                                                                  2
++#define mmDCPG_INTERRUPT_DEST                                                                          0x0149
++#define mmDCPG_INTERRUPT_DEST_BASE_IDX                                                                 2
++#define mmDCPG_INTERRUPT_DEST2                                                                         0x014a
++#define mmDCPG_INTERRUPT_DEST2_BASE_IDX                                                                2
++#define mmMMHUBBUB_INTERRUPT_DEST                                                                      0x014b
++#define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX                                                             2
++#define mmWB_INTERRUPT_DEST                                                                            0x014c
++#define mmWB_INTERRUPT_DEST_BASE_IDX                                                                   2
++#define mmDCHUB_INTERRUPT_DEST                                                                         0x014d
++#define mmDCHUB_INTERRUPT_DEST_BASE_IDX                                                                2
++#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST                                                             0x014e
++#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                    2
++#define mmDCHUB_INTERRUPT_DEST2                                                                        0x014f
++#define mmDCHUB_INTERRUPT_DEST2_BASE_IDX                                                               2
++#define mmDPP_PERFCOUNTER_INTERRUPT_DEST                                                               0x0150
++#define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                      2
++#define mmMPC_INTERRUPT_DEST                                                                           0x0151
++#define mmMPC_INTERRUPT_DEST_BASE_IDX                                                                  2
++#define mmOPP_INTERRUPT_DEST                                                                           0x0152
++#define mmOPP_INTERRUPT_DEST_BASE_IDX                                                                  2
++#define mmOPTC_INTERRUPT_DEST                                                                          0x0153
++#define mmOPTC_INTERRUPT_DEST_BASE_IDX                                                                 2
++#define mmOTG0_INTERRUPT_DEST                                                                          0x0154
++#define mmOTG0_INTERRUPT_DEST_BASE_IDX                                                                 2
++#define mmOTG1_INTERRUPT_DEST                                                                          0x0155
++#define mmOTG1_INTERRUPT_DEST_BASE_IDX                                                                 2
++#define mmOTG2_INTERRUPT_DEST                                                                          0x0156
++#define mmOTG2_INTERRUPT_DEST_BASE_IDX                                                                 2
++#define mmOTG3_INTERRUPT_DEST                                                                          0x0157
++#define mmOTG3_INTERRUPT_DEST_BASE_IDX                                                                 2
++#define mmOTG4_INTERRUPT_DEST                                                                          0x0158
++#define mmOTG4_INTERRUPT_DEST_BASE_IDX                                                                 2
++#define mmOTG5_INTERRUPT_DEST                                                                          0x0159
++#define mmOTG5_INTERRUPT_DEST_BASE_IDX                                                                 2
++#define mmDIG_INTERRUPT_DEST                                                                           0x015a
++#define mmDIG_INTERRUPT_DEST_BASE_IDX                                                                  2
++#define mmI2C_DDC_HPD_INTERRUPT_DEST                                                                   0x015b
++#define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX                                                          2
++#define mmDIO_INTERRUPT_DEST                                                                           0x015d
++#define mmDIO_INTERRUPT_DEST_BASE_IDX                                                                  2
++#define mmDCIO_INTERRUPT_DEST                                                                          0x015e
++#define mmDCIO_INTERRUPT_DEST_BASE_IDX                                                                 2
++#define mmHPD_INTERRUPT_DEST                                                                           0x015f
++#define mmHPD_INTERRUPT_DEST_BASE_IDX                                                                  2
++#define mmAZ_INTERRUPT_DEST                                                                            0x0160
++#define mmAZ_INTERRUPT_DEST_BASE_IDX                                                                   2
++#define mmAUX_INTERRUPT_DEST                                                                           0x0161
++#define mmAUX_INTERRUPT_DEST_BASE_IDX                                                                  2
++#define mmDSC_INTERRUPT_DEST                                                                           0x0162
++#define mmDSC_INTERRUPT_DEST_BASE_IDX                                                                  2
++
++
++// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec
++// base address: 0x0
++#define mmWB_ENABLE                                                                                    0x01da
++#define mmWB_ENABLE_BASE_IDX                                                                           2
++#define mmWB_EC_CONFIG                                                                                 0x01db
++#define mmWB_EC_CONFIG_BASE_IDX                                                                        2
++#define mmCNV_MODE                                                                                     0x01dc
++#define mmCNV_MODE_BASE_IDX                                                                            2
++#define mmCNV_WINDOW_START                                                                             0x01dd
++#define mmCNV_WINDOW_START_BASE_IDX                                                                    2
++#define mmCNV_WINDOW_SIZE                                                                              0x01de
++#define mmCNV_WINDOW_SIZE_BASE_IDX                                                                     2
++#define mmCNV_UPDATE                                                                                   0x01df
++#define mmCNV_UPDATE_BASE_IDX                                                                          2
++#define mmCNV_SOURCE_SIZE                                                                              0x01e0
++#define mmCNV_SOURCE_SIZE_BASE_IDX                                                                     2
++#define mmCNV_TEST_CNTL                                                                                0x01ee
++#define mmCNV_TEST_CNTL_BASE_IDX                                                                       2
++#define mmCNV_TEST_CRC_RED                                                                             0x01ef
++#define mmCNV_TEST_CRC_RED_BASE_IDX                                                                    2
++#define mmCNV_TEST_CRC_GREEN                                                                           0x01f0
++#define mmCNV_TEST_CRC_GREEN_BASE_IDX                                                                  2
++#define mmCNV_TEST_CRC_BLUE                                                                            0x01f1
++#define mmCNV_TEST_CRC_BLUE_BASE_IDX                                                                   2
++#define mmWB_DEBUG_CTRL                                                                                0x01f2
++#define mmWB_DEBUG_CTRL_BASE_IDX                                                                       2
++#define mmWB_DBG_MODE                                                                                  0x01f3
++#define mmWB_DBG_MODE_BASE_IDX                                                                         2
++#define mmWB_HW_DEBUG                                                                                  0x01f4
++#define mmWB_HW_DEBUG_BASE_IDX                                                                         2
++#define mmWB_SOFT_RESET                                                                                0x01f5
++#define mmWB_SOFT_RESET_BASE_IDX                                                                       2
++#define mmWB_WARM_UP_MODE_CTL1                                                                         0x01f6
++#define mmWB_WARM_UP_MODE_CTL1_BASE_IDX                                                                2
++#define mmWB_WARM_UP_MODE_CTL2                                                                         0x01f7
++#define mmWB_WARM_UP_MODE_CTL2_BASE_IDX                                                                2
++#define mmCNV_TEST_DEBUG_INDEX                                                                         0x01f8
++#define mmCNV_TEST_DEBUG_INDEX_BASE_IDX                                                                2
++#define mmCNV_TEST_DEBUG_DATA                                                                          0x01f9
++#define mmCNV_TEST_DEBUG_DATA_BASE_IDX                                                                 2
++
++
++// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec
++// base address: 0x0
++#define mmWBSCL_COEF_RAM_SELECT                                                                        0x020a
++#define mmWBSCL_COEF_RAM_SELECT_BASE_IDX                                                               2
++#define mmWBSCL_COEF_RAM_TAP_DATA                                                                      0x020b
++#define mmWBSCL_COEF_RAM_TAP_DATA_BASE_IDX                                                             2
++#define mmWBSCL_MODE                                                                                   0x020c
++#define mmWBSCL_MODE_BASE_IDX                                                                          2
++#define mmWBSCL_TAP_CONTROL                                                                            0x020d
++#define mmWBSCL_TAP_CONTROL_BASE_IDX                                                                   2
++#define mmWBSCL_DEST_SIZE                                                                              0x020e
++#define mmWBSCL_DEST_SIZE_BASE_IDX                                                                     2
++#define mmWBSCL_HORZ_FILTER_SCALE_RATIO                                                                0x020f
++#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                       2
++#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB                                                                 0x0210
++#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX                                                        2
++#define mmWBSCL_HORZ_FILTER_INIT_CBCR                                                                  0x0211
++#define mmWBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX                                                         2
++#define mmWBSCL_VERT_FILTER_SCALE_RATIO                                                                0x0212
++#define mmWBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                       2
++#define mmWBSCL_VERT_FILTER_INIT_Y_RGB                                                                 0x0213
++#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX                                                        2
++#define mmWBSCL_VERT_FILTER_INIT_CBCR                                                                  0x0214
++#define mmWBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX                                                         2
++#define mmWBSCL_ROUND_OFFSET                                                                           0x0215
++#define mmWBSCL_ROUND_OFFSET_BASE_IDX                                                                  2
++#define mmWBSCL_OVERFLOW_STATUS                                                                        0x0216
++#define mmWBSCL_OVERFLOW_STATUS_BASE_IDX                                                               2
++#define mmWBSCL_COEF_RAM_CONFLICT_STATUS                                                               0x0217
++#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX                                                      2
++#define mmWBSCL_TEST_CNTL                                                                              0x0218
++#define mmWBSCL_TEST_CNTL_BASE_IDX                                                                     2
++#define mmWBSCL_TEST_CRC_RED                                                                           0x0219
++#define mmWBSCL_TEST_CRC_RED_BASE_IDX                                                                  2
++#define mmWBSCL_TEST_CRC_GREEN                                                                         0x021a
++#define mmWBSCL_TEST_CRC_GREEN_BASE_IDX                                                                2
++#define mmWBSCL_TEST_CRC_BLUE                                                                          0x021b
++#define mmWBSCL_TEST_CRC_BLUE_BASE_IDX                                                                 2
++#define mmWBSCL_BACKPRESSURE_CNT_EN                                                                    0x021c
++#define mmWBSCL_BACKPRESSURE_CNT_EN_BASE_IDX                                                           2
++#define mmWB_MCIF_BACKPRESSURE_CNT                                                                     0x021d
++#define mmWB_MCIF_BACKPRESSURE_CNT_BASE_IDX                                                            2
++#define mmWBSCL_CLAMP_Y_RGB                                                                            0x021e
++#define mmWBSCL_CLAMP_Y_RGB_BASE_IDX                                                                   2
++#define mmWBSCL_CLAMP_CBCR                                                                             0x021f
++#define mmWBSCL_CLAMP_CBCR_BASE_IDX                                                                    2
++#define mmWBSCL_OUTSIDE_PIX_STRATEGY                                                                   0x0220
++#define mmWBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX                                                          2
++#define mmWBSCL_OUTSIDE_PIX_STRATEGY_CBCR                                                              0x0221
++#define mmWBSCL_OUTSIDE_PIX_STRATEGY_CBCR_BASE_IDX                                                     2
++#define mmWBSCL_DEBUG                                                                                  0x0222
++#define mmWBSCL_DEBUG_BASE_IDX                                                                         2
++#define mmWBSCL_TEST_DEBUG_INDEX                                                                       0x0223
++#define mmWBSCL_TEST_DEBUG_INDEX_BASE_IDX                                                              2
++#define mmWBSCL_TEST_DEBUG_DATA                                                                        0x0224
++#define mmWBSCL_TEST_DEBUG_DATA_BASE_IDX                                                               2
++
++
++// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
++// base address: 0x8e8
++#define mmDC_PERFMON3_PERFCOUNTER_CNTL                                                                 0x023a
++#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX                                                        2
++#define mmDC_PERFMON3_PERFCOUNTER_CNTL2                                                                0x023b
++#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
++#define mmDC_PERFMON3_PERFCOUNTER_STATE                                                                0x023c
++#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX                                                       2
++#define mmDC_PERFMON3_PERFMON_CNTL                                                                     0x023d
++#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX                                                            2
++#define mmDC_PERFMON3_PERFMON_CNTL2                                                                    0x023e
++#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX                                                           2
++#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                                          0x023f
++#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
++#define mmDC_PERFMON3_PERFMON_CVALUE_LOW                                                               0x0240
++#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
++#define mmDC_PERFMON3_PERFMON_HI                                                                       0x0241
++#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX                                                              2
++#define mmDC_PERFMON3_PERFMON_LOW                                                                      0x0242
++#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
++// base address: 0x0
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x02b2
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                  2
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R                                                           0x02b3
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX                                                  2
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS                                                               0x02b4
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX                                                      2
++#define mmMCIF_WB0_MCIF_WB_BUF_PITCH                                                                   0x02b5
++#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX                                                          2
++#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS                                                                0x02b6
++#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX                                                       2
++#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2                                                               0x02b7
++#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX                                                      2
++#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS                                                                0x02b8
++#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX                                                       2
++#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2                                                               0x02b9
++#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX                                                      2
++#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS                                                                0x02ba
++#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX                                                       2
++#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2                                                               0x02bb
++#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX                                                      2
++#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS                                                                0x02bc
++#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX                                                       2
++#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2                                                               0x02bd
++#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX                                                      2
++#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL                                                         0x02be
++#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                2
++#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE                                                                 0x02bf
++#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX                                                        2
++#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX                                                            0x02c0
++#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                   2
++#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA                                                             0x02c1
++#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                    2
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y                                                                0x02c2
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                       2
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET                                                         0x02c3
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C                                                                0x02c4
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                       2
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET                                                         0x02c5
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y                                                                0x02c6
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                       2
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET                                                         0x02c7
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C                                                                0x02c8
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                       2
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET                                                         0x02c9
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y                                                                0x02ca
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                       2
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET                                                         0x02cb
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C                                                                0x02cc
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                       2
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET                                                         0x02cd
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y                                                                0x02ce
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                       2
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET                                                         0x02cf
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C                                                                0x02d0
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                       2
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET                                                         0x02d1
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL                                                          0x02d2
++#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                 2
++#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                 0x02d3
++#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                        2
++#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL                                                           0x02d4
++#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                  2
++#define mmMCIF_WB0_MCIF_WB_WATERMARK                                                                   0x02d5
++#define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX                                                          2
++#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL                                                         0x02d6
++#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                2
++#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL                                                                0x02d7
++#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX                                                       2
++#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL                                                        0x02d8
++#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                               2
++#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL                                                                0x02d9
++#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX                                                       2
++#define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL                                                              0x02da
++#define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL_BASE_IDX                                                     2
++#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE                                                               0x02db
++#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                      2
++#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE                                                             0x02dc
++#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                    2
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH                                                           0x02dd
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH                                                           0x02de
++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH                                                           0x02df
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH                                                           0x02e0
++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH                                                           0x02e1
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH                                                           0x02e2
++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH                                                           0x02e3
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH                                                           0x02e4
++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB0_MCIF_WB_BUF_1_RESOLUTION                                                            0x02e5
++#define mmMCIF_WB0_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                   2
++#define mmMCIF_WB0_MCIF_WB_BUF_2_RESOLUTION                                                            0x02e6
++#define mmMCIF_WB0_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                   2
++#define mmMCIF_WB0_MCIF_WB_BUF_3_RESOLUTION                                                            0x02e7
++#define mmMCIF_WB0_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                   2
++#define mmMCIF_WB0_MCIF_WB_BUF_4_RESOLUTION                                                            0x02e8
++#define mmMCIF_WB0_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                   2
++
++
++// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec
++// base address: 0x100
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x02f2
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                  2
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R                                                           0x02f3
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX                                                  2
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS                                                               0x02f4
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX                                                      2
++#define mmMCIF_WB1_MCIF_WB_BUF_PITCH                                                                   0x02f5
++#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX                                                          2
++#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS                                                                0x02f6
++#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX                                                       2
++#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2                                                               0x02f7
++#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX                                                      2
++#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS                                                                0x02f8
++#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX                                                       2
++#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2                                                               0x02f9
++#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX                                                      2
++#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS                                                                0x02fa
++#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX                                                       2
++#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2                                                               0x02fb
++#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX                                                      2
++#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS                                                                0x02fc
++#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX                                                       2
++#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2                                                               0x02fd
++#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX                                                      2
++#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL                                                         0x02fe
++#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                2
++#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE                                                                 0x02ff
++#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX                                                        2
++#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX                                                            0x0300
++#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                   2
++#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA                                                             0x0301
++#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                    2
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y                                                                0x0302
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                       2
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET                                                         0x0303
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C                                                                0x0304
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                       2
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET                                                         0x0305
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y                                                                0x0306
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                       2
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET                                                         0x0307
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C                                                                0x0308
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                       2
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET                                                         0x0309
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y                                                                0x030a
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                       2
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET                                                         0x030b
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C                                                                0x030c
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                       2
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET                                                         0x030d
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y                                                                0x030e
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                       2
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET                                                         0x030f
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C                                                                0x0310
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                       2
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET                                                         0x0311
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL                                                          0x0312
++#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                 2
++#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                 0x0313
++#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                        2
++#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL                                                           0x0314
++#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                  2
++#define mmMCIF_WB1_MCIF_WB_WATERMARK                                                                   0x0315
++#define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX                                                          2
++#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL                                                         0x0316
++#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                2
++#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL                                                                0x0317
++#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX                                                       2
++#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL                                                        0x0318
++#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                               2
++#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL                                                                0x0319
++#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX                                                       2
++#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE                                                               0x031b
++#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                      2
++#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE                                                             0x031c
++#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                    2
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH                                                           0x031d
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH                                                           0x031e
++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH                                                           0x031f
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH                                                           0x0320
++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH                                                           0x0321
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH                                                           0x0322
++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH                                                           0x0323
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH                                                           0x0324
++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB1_MCIF_WB_BUF_1_RESOLUTION                                                            0x0325
++#define mmMCIF_WB1_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                   2
++#define mmMCIF_WB1_MCIF_WB_BUF_2_RESOLUTION                                                            0x0326
++#define mmMCIF_WB1_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                   2
++#define mmMCIF_WB1_MCIF_WB_BUF_3_RESOLUTION                                                            0x0327
++#define mmMCIF_WB1_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                   2
++#define mmMCIF_WB1_MCIF_WB_BUF_4_RESOLUTION                                                            0x0328
++#define mmMCIF_WB1_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                   2
++
++
++// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
++// base address: 0x0
++#define mmWBIF0_MISC_CTRL                                                                              0x0333
++#define mmWBIF0_MISC_CTRL_BASE_IDX                                                                     2
++#define mmWBIF0_SMU_WM_CONTROL                                                                         0x0334
++#define mmWBIF0_SMU_WM_CONTROL_BASE_IDX                                                                2
++#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER                                                             0x0335
++#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                    2
++#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER                                                             0x0336
++#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                    2
++#define mmVGA_SRC_SPLIT_CNTL                                                                           0x033f
++#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX                                                                  2
++#define mmMMHUBBUB_MEM_PWR_STATUS                                                                      0x0340
++#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
++#define mmMMHUBBUB_MEM_PWR_CNTL                                                                        0x0341
++#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2
++#define mmMMHUBBUB_CLOCK_CNTL                                                                          0x0342
++#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
++#define mmMMHUBBUB_SOFT_RESET                                                                          0x0343
++#define mmMMHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
++#define mmDMU_IF_ERR_STATUS                                                                            0x0347
++#define mmDMU_IF_ERR_STATUS_BASE_IDX                                                                   2
++#define mmMMHUBBUB_CLIENT_UNIT_ID                                                                      0x0348
++#define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
++// base address: 0x0
++#define mmMCIF_CONTROL                                                                                 0x034a
++#define mmMCIF_CONTROL_BASE_IDX                                                                        2
++#define mmMCIF_WRITE_COMBINE_CONTROL                                                                   0x034b
++#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2
++#define mmMCIF_PHASE0_OUTSTANDING_COUNTER                                                              0x034e
++#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                     2
++#define mmMCIF_PHASE1_OUTSTANDING_COUNTER                                                              0x034f
++#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                     2
++#define mmMCIF_PHASE2_OUTSTANDING_COUNTER                                                              0x0350
++#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX                                                     2
++
++
++// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
++// base address: 0xd48
++#define mmDC_PERFMON4_PERFCOUNTER_CNTL                                                                 0x0352
++#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX                                                        2
++#define mmDC_PERFMON4_PERFCOUNTER_CNTL2                                                                0x0353
++#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
++#define mmDC_PERFMON4_PERFCOUNTER_STATE                                                                0x0354
++#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX                                                       2
++#define mmDC_PERFMON4_PERFMON_CNTL                                                                     0x0355
++#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX                                                            2
++#define mmDC_PERFMON4_PERFMON_CNTL2                                                                    0x0356
++#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX                                                           2
++#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                                          0x0357
++#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
++#define mmDC_PERFMON4_PERFMON_CVALUE_LOW                                                               0x0358
++#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
++#define mmDC_PERFMON4_PERFMON_HI                                                                       0x0359
++#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX                                                              2
++#define mmDC_PERFMON4_PERFMON_LOW                                                                      0x035a
++#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_hda_azf0stream0_dispdec
++// base address: 0x0
++#define mmAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x035e
++#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
++#define mmAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x035f
++#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2
++
++
++// addressBlock: dce_dc_hda_azf0stream1_dispdec
++// base address: 0x8
++#define mmAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x0360
++#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
++#define mmAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x0361
++#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2
++
++
++// addressBlock: dce_dc_hda_azf0stream2_dispdec
++// base address: 0x10
++#define mmAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x0362
++#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
++#define mmAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x0363
++#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2
++
++
++// addressBlock: dce_dc_hda_azf0stream3_dispdec
++// base address: 0x18
++#define mmAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x0364
++#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
++#define mmAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x0365
++#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2
++
++
++// addressBlock: dce_dc_hda_azf0stream4_dispdec
++// base address: 0x20
++#define mmAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0366
++#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
++#define mmAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0367
++#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2
++
++
++// addressBlock: dce_dc_hda_azf0stream5_dispdec
++// base address: 0x28
++#define mmAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0368
++#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
++#define mmAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0369
++#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2
++
++
++// addressBlock: dce_dc_hda_azf0stream6_dispdec
++// base address: 0x30
++#define mmAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x036a
++#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
++#define mmAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x036b
++#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2
++
++
++// addressBlock: dce_dc_hda_azf0stream7_dispdec
++// base address: 0x38
++#define mmAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x036c
++#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
++#define mmAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x036d
++#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2
++
++
++// addressBlock: dce_dc_hda_az_misc_dispdec
++// base address: 0x0
++#define mmAZ_CLOCK_CNTL                                                                                0x0372
++#define mmAZ_CLOCK_CNTL_BASE_IDX                                                                       2
++
++
++// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
++// base address: 0xde8
++#define mmDC_PERFMON5_PERFCOUNTER_CNTL                                                                 0x037a
++#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX                                                        2
++#define mmDC_PERFMON5_PERFCOUNTER_CNTL2                                                                0x037b
++#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
++#define mmDC_PERFMON5_PERFCOUNTER_STATE                                                                0x037c
++#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX                                                       2
++#define mmDC_PERFMON5_PERFMON_CNTL                                                                     0x037d
++#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX                                                            2
++#define mmDC_PERFMON5_PERFMON_CNTL2                                                                    0x037e
++#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX                                                           2
++#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                                          0x037f
++#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
++#define mmDC_PERFMON5_PERFMON_CVALUE_LOW                                                               0x0380
++#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
++#define mmDC_PERFMON5_PERFMON_HI                                                                       0x0381
++#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX                                                              2
++#define mmDC_PERFMON5_PERFMON_LOW                                                                      0x0382
++#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
++// base address: 0x0
++#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0386
++#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
++#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0387
++#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
++
++
++// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
++// base address: 0x18
++#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x038c
++#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
++#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x038d
++#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
++
++
++// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
++// base address: 0x30
++#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0392
++#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
++#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0393
++#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
++
++
++// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
++// base address: 0x48
++#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0398
++#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
++#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0399
++#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
++
++
++// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
++// base address: 0x60
++#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x039e
++#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
++#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x039f
++#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
++
++
++// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
++// base address: 0x78
++#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03a4
++#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
++#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03a5
++#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
++
++
++// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
++// base address: 0x90
++#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03aa
++#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
++#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03ab
++#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
++
++
++// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
++// base address: 0xa8
++#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03b0
++#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
++#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03b1
++#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
++
++
++// addressBlock: dce_dc_hda_azf0controller_dispdec
++// base address: 0x0
++#define mmAZALIA_CONTROLLER_CLOCK_GATING                                                               0x03c2
++#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2
++#define mmAZALIA_AUDIO_DTO                                                                             0x03c3
++#define mmAZALIA_AUDIO_DTO_BASE_IDX                                                                    2
++#define mmAZALIA_AUDIO_DTO_CONTROL                                                                     0x03c4
++#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2
++#define mmAZALIA_SOCCLK_CONTROL                                                                        0x03c5
++#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2
++#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x03c6
++#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2
++#define mmAZALIA_DATA_DMA_CONTROL                                                                      0x03c7
++#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2
++#define mmAZALIA_BDL_DMA_CONTROL                                                                       0x03c8
++#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2
++#define mmAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9
++#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
++#define mmAZALIA_CORB_DMA_CONTROL                                                                      0x03ca
++#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2
++#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                                                 0x03d1
++#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX                                        2
++#define mmAZALIA_CYCLIC_BUFFER_SYNC                                                                    0x03d2
++#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX                                                           2
++#define mmAZALIA_GLOBAL_CAPABILITIES                                                                   0x03d3
++#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2
++#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x03d4
++#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2
++#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x03d5
++#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
++#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x03d6
++#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2
++#define mmAZALIA_INPUT_CRC0_CONTROL0                                                                   0x03d9
++#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2
++#define mmAZALIA_INPUT_CRC0_CONTROL1                                                                   0x03da
++#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2
++#define mmAZALIA_INPUT_CRC0_CONTROL2                                                                   0x03db
++#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2
++#define mmAZALIA_INPUT_CRC0_CONTROL3                                                                   0x03dc
++#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2
++#define mmAZALIA_INPUT_CRC0_RESULT                                                                     0x03dd
++#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2
++#define mmAZALIA_INPUT_CRC1_CONTROL0                                                                   0x03de
++#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
++#define mmAZALIA_INPUT_CRC1_CONTROL1                                                                   0x03df
++#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2
++#define mmAZALIA_INPUT_CRC1_CONTROL2                                                                   0x03e0
++#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2
++#define mmAZALIA_INPUT_CRC1_CONTROL3                                                                   0x03e1
++#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2
++#define mmAZALIA_INPUT_CRC1_RESULT                                                                     0x03e2
++#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2
++#define mmAZALIA_CRC0_CONTROL0                                                                         0x03e3
++#define mmAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2
++#define mmAZALIA_CRC0_CONTROL1                                                                         0x03e4
++#define mmAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
++#define mmAZALIA_CRC0_CONTROL2                                                                         0x03e5
++#define mmAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2
++#define mmAZALIA_CRC0_CONTROL3                                                                         0x03e6
++#define mmAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2
++#define mmAZALIA_CRC0_RESULT                                                                           0x03e7
++#define mmAZALIA_CRC0_RESULT_BASE_IDX                                                                  2
++#define mmAZALIA_CRC1_CONTROL0                                                                         0x03e8
++#define mmAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
++#define mmAZALIA_CRC1_CONTROL1                                                                         0x03e9
++#define mmAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2
++#define mmAZALIA_CRC1_CONTROL2                                                                         0x03ea
++#define mmAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2
++#define mmAZALIA_CRC1_CONTROL3                                                                         0x03eb
++#define mmAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2
++#define mmAZALIA_CRC1_RESULT                                                                           0x03ec
++#define mmAZALIA_CRC1_RESULT_BASE_IDX                                                                  2
++#define mmAZALIA_MEM_PWR_CTRL                                                                          0x03ee
++#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2
++#define mmAZALIA_MEM_PWR_STATUS                                                                        0x03ef
++#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2
++
++
++// addressBlock: dce_dc_hda_azf0root_dispdec
++// base address: 0x0
++#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0406
++#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2
++#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0407
++#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2
++#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408
++#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
++#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0409
++#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x040a
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x040b
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x040c
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x040d
++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x040e
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x040f
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x0410
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x0411
++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2
++#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x0412
++#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2
++#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x0413
++#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2
++#define mmAZALIA_F0_GTC_GROUP_OFFSET0                                                                  0x0415
++#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX                                                         2
++#define mmAZALIA_F0_GTC_GROUP_OFFSET1                                                                  0x0416
++#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX                                                         2
++#define mmAZALIA_F0_GTC_GROUP_OFFSET2                                                                  0x0417
++#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX                                                         2
++#define mmAZALIA_F0_GTC_GROUP_OFFSET3                                                                  0x0418
++#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX                                                         2
++#define mmAZALIA_F0_GTC_GROUP_OFFSET4                                                                  0x0419
++#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX                                                         2
++#define mmAZALIA_F0_GTC_GROUP_OFFSET5                                                                  0x041a
++#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX                                                         2
++#define mmAZALIA_F0_GTC_GROUP_OFFSET6                                                                  0x041b
++#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX                                                         2
++#define mmREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x041c
++#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2
++#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x041d
++#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2
++
++
++// addressBlock: dce_dc_hda_azf0stream8_dispdec
++// base address: 0x320
++#define mmAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0426
++#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
++#define mmAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0427
++#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2
++
++
++// addressBlock: dce_dc_hda_azf0stream9_dispdec
++// base address: 0x328
++#define mmAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0428
++#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
++#define mmAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0429
++#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2
++
++
++// addressBlock: dce_dc_hda_azf0stream10_dispdec
++// base address: 0x330
++#define mmAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x042a
++#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
++#define mmAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x042b
++#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2
++
++
++// addressBlock: dce_dc_hda_azf0stream11_dispdec
++// base address: 0x338
++#define mmAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x042c
++#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
++#define mmAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x042d
++#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2
++
++
++// addressBlock: dce_dc_hda_azf0stream12_dispdec
++// base address: 0x340
++#define mmAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x042e
++#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
++#define mmAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x042f
++#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2
++
++
++// addressBlock: dce_dc_hda_azf0stream13_dispdec
++// base address: 0x348
++#define mmAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x0430
++#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
++#define mmAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x0431
++#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2
++
++
++// addressBlock: dce_dc_hda_azf0stream14_dispdec
++// base address: 0x350
++#define mmAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x0432
++#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
++#define mmAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x0433
++#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2
++
++
++// addressBlock: dce_dc_hda_azf0stream15_dispdec
++// base address: 0x358
++#define mmAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x0434
++#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
++#define mmAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x0435
++#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2
++
++
++// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
++// base address: 0x0
++#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043a
++#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
++#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043b
++#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
++
++
++// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
++// base address: 0x10
++#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043e
++#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
++#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043f
++#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
++
++
++// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
++// base address: 0x20
++#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0442
++#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
++#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0443
++#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
++
++
++// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
++// base address: 0x30
++#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0446
++#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
++#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0447
++#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
++
++
++// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
++// base address: 0x40
++#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044a
++#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
++#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044b
++#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
++
++
++// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
++// base address: 0x50
++#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044e
++#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
++#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044f
++#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
++
++
++// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
++// base address: 0x60
++#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0452
++#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
++#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0453
++#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
++
++
++// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
++// base address: 0x70
++#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0456
++#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
++#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0457
++#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
++
++
++// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
++// base address: 0x0
++#define mmDCHUBBUB_SDPIF_CFG0                                                                          0x048f
++#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX                                                                 2
++#define mmVM_REQUEST_PHYSICAL                                                                          0x0490
++#define mmVM_REQUEST_PHYSICAL_BASE_IDX                                                                 2
++#define mmDCHUBBUB_FORCE_IO_STATUS_0                                                                   0x0491
++#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX                                                          2
++#define mmDCHUBBUB_FORCE_IO_STATUS_1                                                                   0x0492
++#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX                                                          2
++#define mmDCN_VM_FB_LOCATION_BASE                                                                      0x0493
++#define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX                                                             2
++#define mmDCN_VM_FB_LOCATION_TOP                                                                       0x0494
++#define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX                                                              2
++#define mmDCN_VM_FB_OFFSET                                                                             0x0495
++#define mmDCN_VM_FB_OFFSET_BASE_IDX                                                                    2
++#define mmDCN_VM_AGP_BOT                                                                               0x0496
++#define mmDCN_VM_AGP_BOT_BASE_IDX                                                                      2
++#define mmDCN_VM_AGP_TOP                                                                               0x0497
++#define mmDCN_VM_AGP_TOP_BASE_IDX                                                                      2
++#define mmDCN_VM_AGP_BASE                                                                              0x0498
++#define mmDCN_VM_AGP_BASE_BASE_IDX                                                                     2
++#define mmDCN_VM_LOCAL_HBM_ADDRESS_START                                                               0x0499
++#define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                      2
++#define mmDCN_VM_LOCAL_HBM_ADDRESS_END                                                                 0x049a
++#define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                        2
++#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                           0x049b
++#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                  2
++#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL                                                                  0x04b8
++#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX                                                         2
++#define mmDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL                                                           0x04b9
++#define mmDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX                                                  2
++#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL                                                                  0x04ba
++#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX                                                         2
++#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS                                                                0x04bb
++#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX                                                       2
++#define mmDCHUBBUB_SDPIF_CFG1                                                                          0x04bf
++#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX                                                                 2
++#define mmDCHUBBUB_SDPIF_CFG2                                                                          0x04c0
++#define mmDCHUBBUB_SDPIF_CFG2_BASE_IDX                                                                 2
++
++
++// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
++// base address: 0x0
++#define mmDCHUBBUB_RET_PATH_DCC_CFG                                                                    0x04cf
++#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX                                                           2
++#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0                                                                 0x04d0
++#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX                                                        2
++#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1                                                                 0x04d1
++#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX                                                        2
++#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0                                                                 0x04d2
++#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX                                                        2
++#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1                                                                 0x04d3
++#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX                                                        2
++#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0                                                                 0x04d4
++#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX                                                        2
++#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1                                                                 0x04d5
++#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX                                                        2
++#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0                                                                 0x04d6
++#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX                                                        2
++#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1                                                                 0x04d7
++#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX                                                        2
++#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0                                                                 0x04d8
++#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX                                                        2
++#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1                                                                 0x04d9
++#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX                                                        2
++#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0                                                                 0x04da
++#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX                                                        2
++#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1                                                                 0x04db
++#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX                                                        2
++#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0                                                                 0x04dc
++#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX                                                        2
++#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1                                                                 0x04dd
++#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX                                                        2
++#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0                                                                 0x04de
++#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX                                                        2
++#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1                                                                 0x04df
++#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX                                                        2
++#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL                                                               0x04ef
++#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX                                                      2
++#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS                                                             0x04f0
++#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX                                                    2
++#define mmDCHUBBUB_CRC_CTRL                                                                            0x04f1
++#define mmDCHUBBUB_CRC_CTRL_BASE_IDX                                                                   2
++#define mmDCHUBBUB_CRC0_VAL_R_G                                                                        0x04f2
++#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX                                                               2
++#define mmDCHUBBUB_CRC0_VAL_B_A                                                                        0x04f3
++#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX                                                               2
++#define mmDCHUBBUB_CRC1_VAL_R_G                                                                        0x04f4
++#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX                                                               2
++#define mmDCHUBBUB_CRC1_VAL_B_A                                                                        0x04f5
++#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX                                                               2
++
++
++// addressBlock: dce_dc_dchubbub_hubbub_dispdec
++// base address: 0x0
++#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND                                                                 0x0505
++#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX                                                        2
++#define mmDCHUBBUB_ARB_SAT_LEVEL                                                                       0x0506
++#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX                                                              2
++#define mmDCHUBBUB_ARB_QOS_FORCE                                                                       0x0507
++#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX                                                              2
++#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL                                                                 0x0508
++#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX                                                        2
++#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A                                                        0x0509
++#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX                                               2
++#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A                                                     0x050a
++#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX                                            2
++#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A                                                      0x050b
++#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX                                             2
++#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A                                                       0x050c
++#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX                                              2
++#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A                                               0x050d
++#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX                                      2
++#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B                                                        0x050e
++#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX                                               2
++#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B                                                     0x050f
++#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX                                            2
++#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B                                                      0x0510
++#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX                                             2
++#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B                                                       0x0511
++#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX                                              2
++#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B                                               0x0512
++#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX                                      2
++#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C                                                        0x0513
++#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX                                               2
++#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C                                                     0x0514
++#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX                                            2
++#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C                                                      0x0515
++#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX                                             2
++#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C                                                       0x0516
++#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX                                              2
++#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C                                               0x0517
++#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX                                      2
++#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D                                                        0x0518
++#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX                                               2
++#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D                                                     0x0519
++#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX                                            2
++#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D                                                      0x051a
++#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX                                             2
++#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D                                                       0x051b
++#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX                                              2
++#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D                                               0x051c
++#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX                                      2
++#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL                                                           0x051d
++#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX                                                  2
++#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE                                                                  0x051e
++#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX                                                         2
++#define mmDCHUBBUB_GLOBAL_TIMER_CNTL                                                                   0x051f
++#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX                                                          2
++#define mmSURFACE_CHECK0_ADDRESS_LSB                                                                   0x0520
++#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX                                                          2
++#define mmSURFACE_CHECK0_ADDRESS_MSB                                                                   0x0521
++#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX                                                          2
++#define mmSURFACE_CHECK1_ADDRESS_LSB                                                                   0x0522
++#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX                                                          2
++#define mmSURFACE_CHECK1_ADDRESS_MSB                                                                   0x0523
++#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX                                                          2
++#define mmSURFACE_CHECK2_ADDRESS_LSB                                                                   0x0524
++#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX                                                          2
++#define mmSURFACE_CHECK2_ADDRESS_MSB                                                                   0x0525
++#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX                                                          2
++#define mmSURFACE_CHECK3_ADDRESS_LSB                                                                   0x0526
++#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX                                                          2
++#define mmSURFACE_CHECK3_ADDRESS_MSB                                                                   0x0527
++#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX                                                          2
++#define mmVTG0_CONTROL                                                                                 0x0528
++#define mmVTG0_CONTROL_BASE_IDX                                                                        2
++#define mmVTG1_CONTROL                                                                                 0x0529
++#define mmVTG1_CONTROL_BASE_IDX                                                                        2
++#define mmVTG2_CONTROL                                                                                 0x052a
++#define mmVTG2_CONTROL_BASE_IDX                                                                        2
++#define mmVTG3_CONTROL                                                                                 0x052b
++#define mmVTG3_CONTROL_BASE_IDX                                                                        2
++#define mmDCHUBBUB_SOFT_RESET                                                                          0x052e
++#define mmDCHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
++#define mmDCHUBBUB_CLOCK_CNTL                                                                          0x052f
++#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
++#define mmDCFCLK_CNTL                                                                                  0x0530
++#define mmDCFCLK_CNTL_BASE_IDX                                                                         2
++#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL                                                        0x0531
++#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX                                               2
++#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2                                                       0x0532
++#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX                                              2
++#define mmDCHUBBUB_VLINE_SNAPSHOT                                                                      0x0533
++#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2
++#define mmDCHUBBUB_CTRL_STATUS                                                                         0x0534
++#define mmDCHUBBUB_CTRL_STATUS_BASE_IDX                                                                2
++#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1                                                             0x053a
++#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX                                                    2
++#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2                                                             0x053b
++#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX                                                    2
++#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS                                                            0x053c
++#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2
++#define mmDCHUBBUB_TEST_DEBUG_INDEX                                                                    0x053d
++#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX                                                           2
++#define mmDCHUBBUB_TEST_DEBUG_DATA                                                                     0x053e
++#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX                                                            2
++#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A                                                               0x053f
++#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX                                                      2
++#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A                                                              0x0540
++#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX                                                     2
++#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B                                                               0x0541
++#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX                                                      2
++#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B                                                              0x0542
++#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX                                                     2
++#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C                                                               0x0543
++#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX                                                      2
++#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C                                                              0x0544
++#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX                                                     2
++#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D                                                               0x0545
++#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX                                                      2
++#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D                                                              0x0546
++#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX                                                     2
++#define mmDCHUBBUB_ARB_HOSTVM_CNTL                                                                     0x0547
++#define mmDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX                                                            2
++#define mmFMON_CTRL                                                                                    0x0548
++#define mmFMON_CTRL_BASE_IDX                                                                           2
++
++
++// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
++// base address: 0x1534
++#define mmDC_PERFMON6_PERFCOUNTER_CNTL                                                                 0x054d
++#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX                                                        2
++#define mmDC_PERFMON6_PERFCOUNTER_CNTL2                                                                0x054e
++#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
++#define mmDC_PERFMON6_PERFCOUNTER_STATE                                                                0x054f
++#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX                                                       2
++#define mmDC_PERFMON6_PERFMON_CNTL                                                                     0x0550
++#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX                                                            2
++#define mmDC_PERFMON6_PERFMON_CNTL2                                                                    0x0551
++#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX                                                           2
++#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                                          0x0552
++#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
++#define mmDC_PERFMON6_PERFMON_CVALUE_LOW                                                               0x0553
++#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
++#define mmDC_PERFMON6_PERFMON_HI                                                                       0x0554
++#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX                                                              2
++#define mmDC_PERFMON6_PERFMON_LOW                                                                      0x0555
++#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec
++// base address: 0x0
++#define mmDCN_VM_CONTEXT0_CNTL                                                                         0x0559
++#define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX                                                                2
++#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                    0x055a
++#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                    0x055b
++#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                   0x055c
++#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                   0x055d
++#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                     0x055e
++#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                     0x055f
++#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT1_CNTL                                                                         0x0560
++#define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX                                                                2
++#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0561
++#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0562
++#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                   0x0563
++#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                   0x0564
++#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                     0x0565
++#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                     0x0566
++#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT2_CNTL                                                                         0x0567
++#define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX                                                                2
++#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0568
++#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0569
++#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                   0x056a
++#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                   0x056b
++#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                     0x056c
++#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                     0x056d
++#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT3_CNTL                                                                         0x056e
++#define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX                                                                2
++#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                    0x056f
++#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0570
++#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                   0x0571
++#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                   0x0572
++#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                     0x0573
++#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                     0x0574
++#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT4_CNTL                                                                         0x0575
++#define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX                                                                2
++#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0576
++#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0577
++#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                   0x0578
++#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                   0x0579
++#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                     0x057a
++#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                     0x057b
++#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT5_CNTL                                                                         0x057c
++#define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX                                                                2
++#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                    0x057d
++#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                    0x057e
++#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                   0x057f
++#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                   0x0580
++#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                     0x0581
++#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                     0x0582
++#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT6_CNTL                                                                         0x0583
++#define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX                                                                2
++#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0584
++#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0585
++#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                   0x0586
++#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                   0x0587
++#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                     0x0588
++#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                     0x0589
++#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT7_CNTL                                                                         0x058a
++#define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX                                                                2
++#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                    0x058b
++#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                    0x058c
++#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                   0x058d
++#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                   0x058e
++#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                     0x058f
++#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                     0x0590
++#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT8_CNTL                                                                         0x0591
++#define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX                                                                2
++#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0592
++#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0593
++#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                   0x0594
++#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                   0x0595
++#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                     0x0596
++#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                     0x0597
++#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT9_CNTL                                                                         0x0598
++#define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX                                                                2
++#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0599
++#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                    0x059a
++#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                   0x059b
++#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                   0x059c
++#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                     0x059d
++#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                     0x059e
++#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
++#define mmDCN_VM_CONTEXT10_CNTL                                                                        0x059f
++#define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX                                                               2
++#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a0
++#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a1
++#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                  0x05a2
++#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
++#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                  0x05a3
++#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
++#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                    0x05a4
++#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                    0x05a5
++#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT11_CNTL                                                                        0x05a6
++#define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX                                                               2
++#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a7
++#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a8
++#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                  0x05a9
++#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
++#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                  0x05aa
++#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
++#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                    0x05ab
++#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                    0x05ac
++#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT12_CNTL                                                                        0x05ad
++#define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX                                                               2
++#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05ae
++#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05af
++#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                  0x05b0
++#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
++#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                  0x05b1
++#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
++#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                    0x05b2
++#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                    0x05b3
++#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT13_CNTL                                                                        0x05b4
++#define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX                                                               2
++#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05b5
++#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05b6
++#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                  0x05b7
++#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
++#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                  0x05b8
++#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
++#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                    0x05b9
++#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                    0x05ba
++#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT14_CNTL                                                                        0x05bb
++#define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX                                                               2
++#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05bc
++#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05bd
++#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                  0x05be
++#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
++#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                  0x05bf
++#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
++#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                    0x05c0
++#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                    0x05c1
++#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT15_CNTL                                                                        0x05c2
++#define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX                                                               2
++#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05c3
++#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05c4
++#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
++#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                  0x05c5
++#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
++#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                  0x05c6
++#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
++#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                    0x05c7
++#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
++#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                    0x05c8
++#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
++#define mmDCN_VM_DEFAULT_ADDR_MSB                                                                      0x05c9
++#define mmDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX                                                             2
++#define mmDCN_VM_DEFAULT_ADDR_LSB                                                                      0x05ca
++#define mmDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX                                                             2
++#define mmDCN_VM_FAULT_CNTL                                                                            0x05cb
++#define mmDCN_VM_FAULT_CNTL_BASE_IDX                                                                   2
++#define mmDCN_VM_FAULT_STATUS                                                                          0x05cc
++#define mmDCN_VM_FAULT_STATUS_BASE_IDX                                                                 2
++#define mmDCN_VM_FAULT_ADDR_MSB                                                                        0x05cd
++#define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX                                                               2
++#define mmDCN_VM_FAULT_ADDR_LSB                                                                        0x05ce
++#define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX                                                               2
++
++
++// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
++// base address: 0x0
++#define mmHUBP0_DCSURF_SURFACE_CONFIG                                                                  0x05e5
++#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
++#define mmHUBP0_DCSURF_ADDR_CONFIG                                                                     0x05e6
++#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
++#define mmHUBP0_DCSURF_TILING_CONFIG                                                                   0x05e7
++#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
++#define mmHUBP0_DCSURF_PRI_VIEWPORT_START                                                              0x05e9
++#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
++#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x05ea
++#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
++#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C                                                            0x05eb
++#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
++#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x05ec
++#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
++#define mmHUBP0_DCSURF_SEC_VIEWPORT_START                                                              0x05ed
++#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
++#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x05ee
++#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
++#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C                                                            0x05ef
++#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
++#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x05f0
++#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
++#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG                                                                 0x05f1
++#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
++#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x05f2
++#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
++#define mmHUBP0_DCHUBP_CNTL                                                                            0x05f3
++#define mmHUBP0_DCHUBP_CNTL_BASE_IDX                                                                   2
++#define mmHUBP0_HUBP_CLK_CNTL                                                                          0x05f4
++#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX                                                                 2
++#define mmHUBP0_DCHUBP_VMPG_CONFIG                                                                     0x05f5
++#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
++#define mmHUBP0_HUBPREQ_DEBUG_DB                                                                       0x05f6
++#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
++#define mmHUBP0_HUBPREQ_DEBUG                                                                          0x05f7
++#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX                                                                 2
++#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x05fb
++#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
++#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x05fc
++#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
++
++
++// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
++// base address: 0x0
++#define mmHUBPREQ0_DCSURF_SURFACE_PITCH                                                                0x0607
++#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
++#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C                                                              0x0608
++#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
++#define mmHUBPREQ0_VMID_SETTINGS_0                                                                     0x0609
++#define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX                                                            2
++#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x060a
++#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
++#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x060b
++#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
++#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x060c
++#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
++#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x060d
++#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
++#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x060e
++#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
++#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x060f
++#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
++#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0610
++#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
++#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0611
++#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
++#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0612
++#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
++#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0613
++#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
++#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0614
++#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
++#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0615
++#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
++#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0616
++#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
++#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0617
++#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
++#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0618
++#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
++#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0619
++#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
++#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL                                                              0x061a
++#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
++#define mmHUBPREQ0_DCSURF_FLIP_CONTROL                                                                 0x061b
++#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
++#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2                                                                0x061c
++#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
++#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x0620
++#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
++#define mmHUBPREQ0_DCSURF_SURFACE_INUSE                                                                0x0621
++#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
++#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH                                                           0x0622
++#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
++#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C                                                              0x0623
++#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
++#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0624
++#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
++#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0625
++#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
++#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0626
++#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
++#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0627
++#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
++#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0628
++#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
++#define mmHUBPREQ0_DCN_EXPANSION_MODE                                                                  0x062c
++#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX                                                         2
++#define mmHUBPREQ0_DCN_TTU_QOS_WM                                                                      0x062d
++#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX                                                             2
++#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL                                                                 0x062e
++#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
++#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0                                                                 0x062f
++#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
++#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1                                                                 0x0630
++#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
++#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0                                                                 0x0631
++#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
++#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1                                                                 0x0632
++#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
++#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0                                                                  0x0633
++#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
++#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1                                                                  0x0634
++#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
++#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0                                                                  0x0635
++#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
++#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1                                                                  0x0636
++#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
++#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0637
++#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
++#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0638
++#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
++#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL                                                               0x0645
++#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
++#define mmHUBPREQ0_BLANK_OFFSET_0                                                                      0x0646
++#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX                                                             2
++#define mmHUBPREQ0_BLANK_OFFSET_1                                                                      0x0647
++#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX                                                             2
++#define mmHUBPREQ0_DST_DIMENSIONS                                                                      0x0648
++#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX                                                             2
++#define mmHUBPREQ0_DST_AFTER_SCALER                                                                    0x0649
++#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX                                                           2
++#define mmHUBPREQ0_PREFETCH_SETTINGS                                                                   0x064a
++#define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX                                                          2
++#define mmHUBPREQ0_PREFETCH_SETTINGS_C                                                                 0x064b
++#define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
++#define mmHUBPREQ0_VBLANK_PARAMETERS_0                                                                 0x064c
++#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
++#define mmHUBPREQ0_VBLANK_PARAMETERS_1                                                                 0x064d
++#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
++#define mmHUBPREQ0_VBLANK_PARAMETERS_2                                                                 0x064e
++#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
++#define mmHUBPREQ0_VBLANK_PARAMETERS_3                                                                 0x064f
++#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
++#define mmHUBPREQ0_VBLANK_PARAMETERS_4                                                                 0x0650
++#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
++#define mmHUBPREQ0_FLIP_PARAMETERS_0                                                                   0x0651
++#define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX                                                          2
++#define mmHUBPREQ0_FLIP_PARAMETERS_1                                                                   0x0652
++#define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX                                                          2
++#define mmHUBPREQ0_FLIP_PARAMETERS_2                                                                   0x0653
++#define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX                                                          2
++#define mmHUBPREQ0_NOM_PARAMETERS_0                                                                    0x0654
++#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX                                                           2
++#define mmHUBPREQ0_NOM_PARAMETERS_1                                                                    0x0655
++#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX                                                           2
++#define mmHUBPREQ0_NOM_PARAMETERS_2                                                                    0x0656
++#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX                                                           2
++#define mmHUBPREQ0_NOM_PARAMETERS_3                                                                    0x0657
++#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX                                                           2
++#define mmHUBPREQ0_NOM_PARAMETERS_4                                                                    0x0658
++#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX                                                           2
++#define mmHUBPREQ0_NOM_PARAMETERS_5                                                                    0x0659
++#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX                                                           2
++#define mmHUBPREQ0_NOM_PARAMETERS_6                                                                    0x065a
++#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX                                                           2
++#define mmHUBPREQ0_NOM_PARAMETERS_7                                                                    0x065b
++#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX                                                           2
++#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE                                                               0x065c
++#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
++#define mmHUBPREQ0_PER_LINE_DELIVERY                                                                   0x065d
++#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX                                                          2
++#define mmHUBPREQ0_CURSOR_SETTINGS                                                                     0x065e
++#define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX                                                            2
++#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ                                                                0x065f
++#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
++#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT                                                               0x0660
++#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
++#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL                                                                0x0661
++#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
++#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS                                                              0x0662
++#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
++#define mmHUBPREQ0_VBLANK_PARAMETERS_5                                                                 0x0665
++#define mmHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
++#define mmHUBPREQ0_VBLANK_PARAMETERS_6                                                                 0x0666
++#define mmHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
++#define mmHUBPREQ0_FLIP_PARAMETERS_3                                                                   0x0667
++#define mmHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX                                                          2
++#define mmHUBPREQ0_FLIP_PARAMETERS_4                                                                   0x0668
++#define mmHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX                                                          2
++#define mmHUBPREQ0_FLIP_PARAMETERS_5                                                                   0x0669
++#define mmHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX                                                          2
++#define mmHUBPREQ0_FLIP_PARAMETERS_6                                                                   0x066a
++#define mmHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
++// base address: 0x0
++#define mmHUBPRET0_HUBPRET_CONTROL                                                                     0x066c
++#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX                                                            2
++#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL                                                                0x066d
++#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
++#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS                                                              0x066e
++#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
++#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0                                                             0x066f
++#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
++#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1                                                             0x0670
++#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
++#define mmHUBPRET0_HUBPRET_READ_LINE0                                                                  0x0671
++#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX                                                         2
++#define mmHUBPRET0_HUBPRET_READ_LINE1                                                                  0x0672
++#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX                                                         2
++#define mmHUBPRET0_HUBPRET_INTERRUPT                                                                   0x0673
++#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX                                                          2
++#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE                                                             0x0674
++#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
++#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS                                                            0x0675
++#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
++
++
++// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
++// base address: 0x0
++#define mmCURSOR0_0_CURSOR_CONTROL                                                                     0x0678
++#define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX                                                            2
++#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS                                                             0x0679
++#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
++#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x067a
++#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
++#define mmCURSOR0_0_CURSOR_SIZE                                                                        0x067b
++#define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX                                                               2
++#define mmCURSOR0_0_CURSOR_POSITION                                                                    0x067c
++#define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX                                                           2
++#define mmCURSOR0_0_CURSOR_HOT_SPOT                                                                    0x067d
++#define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX                                                           2
++#define mmCURSOR0_0_CURSOR_STEREO_CONTROL                                                              0x067e
++#define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
++#define mmCURSOR0_0_CURSOR_DST_OFFSET                                                                  0x067f
++#define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX                                                         2
++#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL                                                                0x0680
++#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
++#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS                                                              0x0681
++#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
++#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH                                                                0x0682
++#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
++#define mmCURSOR0_0_DMDATA_ADDRESS_LOW                                                                 0x0683
++#define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
++#define mmCURSOR0_0_DMDATA_CNTL                                                                        0x0684
++#define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX                                                               2
++#define mmCURSOR0_0_DMDATA_QOS_CNTL                                                                    0x0685
++#define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX                                                           2
++#define mmCURSOR0_0_DMDATA_STATUS                                                                      0x0686
++#define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX                                                             2
++#define mmCURSOR0_0_DMDATA_SW_CNTL                                                                     0x0687
++#define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX                                                            2
++#define mmCURSOR0_0_DMDATA_SW_DATA                                                                     0x0688
++#define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
++// base address: 0x1a74
++#define mmDC_PERFMON7_PERFCOUNTER_CNTL                                                                 0x069d
++#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX                                                        2
++#define mmDC_PERFMON7_PERFCOUNTER_CNTL2                                                                0x069e
++#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
++#define mmDC_PERFMON7_PERFCOUNTER_STATE                                                                0x069f
++#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX                                                       2
++#define mmDC_PERFMON7_PERFMON_CNTL                                                                     0x06a0
++#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX                                                            2
++#define mmDC_PERFMON7_PERFMON_CNTL2                                                                    0x06a1
++#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX                                                           2
++#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                                          0x06a2
++#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
++#define mmDC_PERFMON7_PERFMON_CVALUE_LOW                                                               0x06a3
++#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
++#define mmDC_PERFMON7_PERFMON_HI                                                                       0x06a4
++#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX                                                              2
++#define mmDC_PERFMON7_PERFMON_LOW                                                                      0x06a5
++#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
++// base address: 0x370
++#define mmHUBP1_DCSURF_SURFACE_CONFIG                                                                  0x06c1
++#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
++#define mmHUBP1_DCSURF_ADDR_CONFIG                                                                     0x06c2
++#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
++#define mmHUBP1_DCSURF_TILING_CONFIG                                                                   0x06c3
++#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
++#define mmHUBP1_DCSURF_PRI_VIEWPORT_START                                                              0x06c5
++#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
++#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x06c6
++#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
++#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C                                                            0x06c7
++#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
++#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x06c8
++#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
++#define mmHUBP1_DCSURF_SEC_VIEWPORT_START                                                              0x06c9
++#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
++#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x06ca
++#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
++#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C                                                            0x06cb
++#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
++#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x06cc
++#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
++#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG                                                                 0x06cd
++#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
++#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x06ce
++#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
++#define mmHUBP1_DCHUBP_CNTL                                                                            0x06cf
++#define mmHUBP1_DCHUBP_CNTL_BASE_IDX                                                                   2
++#define mmHUBP1_HUBP_CLK_CNTL                                                                          0x06d0
++#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX                                                                 2
++#define mmHUBP1_DCHUBP_VMPG_CONFIG                                                                     0x06d1
++#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
++#define mmHUBP1_HUBPREQ_DEBUG_DB                                                                       0x06d2
++#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
++#define mmHUBP1_HUBPREQ_DEBUG                                                                          0x06d3
++#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX                                                                 2
++#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x06d7
++#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
++#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x06d8
++#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
++
++
++// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
++// base address: 0x370
++#define mmHUBPREQ1_DCSURF_SURFACE_PITCH                                                                0x06e3
++#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
++#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C                                                              0x06e4
++#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
++#define mmHUBPREQ1_VMID_SETTINGS_0                                                                     0x06e5
++#define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX                                                            2
++#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x06e6
++#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
++#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x06e7
++#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
++#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x06e8
++#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
++#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x06e9
++#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
++#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x06ea
++#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
++#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x06eb
++#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
++#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x06ec
++#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
++#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x06ed
++#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
++#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x06ee
++#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
++#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x06ef
++#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
++#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x06f0
++#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
++#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x06f1
++#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
++#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x06f2
++#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
++#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x06f3
++#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
++#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x06f4
++#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
++#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x06f5
++#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
++#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL                                                              0x06f6
++#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
++#define mmHUBPREQ1_DCSURF_FLIP_CONTROL                                                                 0x06f7
++#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
++#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2                                                                0x06f8
++#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
++#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x06fc
++#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
++#define mmHUBPREQ1_DCSURF_SURFACE_INUSE                                                                0x06fd
++#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
++#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH                                                           0x06fe
++#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
++#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C                                                              0x06ff
++#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
++#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0700
++#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
++#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0701
++#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
++#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0702
++#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
++#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0703
++#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
++#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0704
++#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
++#define mmHUBPREQ1_DCN_EXPANSION_MODE                                                                  0x0708
++#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX                                                         2
++#define mmHUBPREQ1_DCN_TTU_QOS_WM                                                                      0x0709
++#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX                                                             2
++#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL                                                                 0x070a
++#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
++#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0                                                                 0x070b
++#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
++#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1                                                                 0x070c
++#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
++#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0                                                                 0x070d
++#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
++#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1                                                                 0x070e
++#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
++#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0                                                                  0x070f
++#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
++#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1                                                                  0x0710
++#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
++#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0                                                                  0x0711
++#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
++#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1                                                                  0x0712
++#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
++#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0713
++#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
++#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0714
++#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
++#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL                                                               0x0721
++#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
++#define mmHUBPREQ1_BLANK_OFFSET_0                                                                      0x0722
++#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX                                                             2
++#define mmHUBPREQ1_BLANK_OFFSET_1                                                                      0x0723
++#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX                                                             2
++#define mmHUBPREQ1_DST_DIMENSIONS                                                                      0x0724
++#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX                                                             2
++#define mmHUBPREQ1_DST_AFTER_SCALER                                                                    0x0725
++#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX                                                           2
++#define mmHUBPREQ1_PREFETCH_SETTINGS                                                                   0x0726
++#define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX                                                          2
++#define mmHUBPREQ1_PREFETCH_SETTINGS_C                                                                 0x0727
++#define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
++#define mmHUBPREQ1_VBLANK_PARAMETERS_0                                                                 0x0728
++#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
++#define mmHUBPREQ1_VBLANK_PARAMETERS_1                                                                 0x0729
++#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
++#define mmHUBPREQ1_VBLANK_PARAMETERS_2                                                                 0x072a
++#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
++#define mmHUBPREQ1_VBLANK_PARAMETERS_3                                                                 0x072b
++#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
++#define mmHUBPREQ1_VBLANK_PARAMETERS_4                                                                 0x072c
++#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
++#define mmHUBPREQ1_FLIP_PARAMETERS_0                                                                   0x072d
++#define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX                                                          2
++#define mmHUBPREQ1_FLIP_PARAMETERS_1                                                                   0x072e
++#define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX                                                          2
++#define mmHUBPREQ1_FLIP_PARAMETERS_2                                                                   0x072f
++#define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX                                                          2
++#define mmHUBPREQ1_NOM_PARAMETERS_0                                                                    0x0730
++#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX                                                           2
++#define mmHUBPREQ1_NOM_PARAMETERS_1                                                                    0x0731
++#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX                                                           2
++#define mmHUBPREQ1_NOM_PARAMETERS_2                                                                    0x0732
++#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX                                                           2
++#define mmHUBPREQ1_NOM_PARAMETERS_3                                                                    0x0733
++#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX                                                           2
++#define mmHUBPREQ1_NOM_PARAMETERS_4                                                                    0x0734
++#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX                                                           2
++#define mmHUBPREQ1_NOM_PARAMETERS_5                                                                    0x0735
++#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX                                                           2
++#define mmHUBPREQ1_NOM_PARAMETERS_6                                                                    0x0736
++#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX                                                           2
++#define mmHUBPREQ1_NOM_PARAMETERS_7                                                                    0x0737
++#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX                                                           2
++#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE                                                               0x0738
++#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
++#define mmHUBPREQ1_PER_LINE_DELIVERY                                                                   0x0739
++#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX                                                          2
++#define mmHUBPREQ1_CURSOR_SETTINGS                                                                     0x073a
++#define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX                                                            2
++#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ                                                                0x073b
++#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
++#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT                                                               0x073c
++#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
++#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL                                                                0x073d
++#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
++#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS                                                              0x073e
++#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
++#define mmHUBPREQ1_VBLANK_PARAMETERS_5                                                                 0x0741
++#define mmHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
++#define mmHUBPREQ1_VBLANK_PARAMETERS_6                                                                 0x0742
++#define mmHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
++#define mmHUBPREQ1_FLIP_PARAMETERS_3                                                                   0x0743
++#define mmHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX                                                          2
++#define mmHUBPREQ1_FLIP_PARAMETERS_4                                                                   0x0744
++#define mmHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX                                                          2
++#define mmHUBPREQ1_FLIP_PARAMETERS_5                                                                   0x0745
++#define mmHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX                                                          2
++#define mmHUBPREQ1_FLIP_PARAMETERS_6                                                                   0x0746
++#define mmHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
++// base address: 0x370
++#define mmHUBPRET1_HUBPRET_CONTROL                                                                     0x0748
++#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX                                                            2
++#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL                                                                0x0749
++#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
++#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS                                                              0x074a
++#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
++#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0                                                             0x074b
++#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
++#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1                                                             0x074c
++#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
++#define mmHUBPRET1_HUBPRET_READ_LINE0                                                                  0x074d
++#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX                                                         2
++#define mmHUBPRET1_HUBPRET_READ_LINE1                                                                  0x074e
++#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX                                                         2
++#define mmHUBPRET1_HUBPRET_INTERRUPT                                                                   0x074f
++#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX                                                          2
++#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE                                                             0x0750
++#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
++#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS                                                            0x0751
++#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
++
++
++// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
++// base address: 0x370
++#define mmCURSOR0_1_CURSOR_CONTROL                                                                     0x0754
++#define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX                                                            2
++#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS                                                             0x0755
++#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
++#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0756
++#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
++#define mmCURSOR0_1_CURSOR_SIZE                                                                        0x0757
++#define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX                                                               2
++#define mmCURSOR0_1_CURSOR_POSITION                                                                    0x0758
++#define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX                                                           2
++#define mmCURSOR0_1_CURSOR_HOT_SPOT                                                                    0x0759
++#define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX                                                           2
++#define mmCURSOR0_1_CURSOR_STEREO_CONTROL                                                              0x075a
++#define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
++#define mmCURSOR0_1_CURSOR_DST_OFFSET                                                                  0x075b
++#define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX                                                         2
++#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL                                                                0x075c
++#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
++#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS                                                              0x075d
++#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
++#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH                                                                0x075e
++#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
++#define mmCURSOR0_1_DMDATA_ADDRESS_LOW                                                                 0x075f
++#define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
++#define mmCURSOR0_1_DMDATA_CNTL                                                                        0x0760
++#define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX                                                               2
++#define mmCURSOR0_1_DMDATA_QOS_CNTL                                                                    0x0761
++#define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX                                                           2
++#define mmCURSOR0_1_DMDATA_STATUS                                                                      0x0762
++#define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX                                                             2
++#define mmCURSOR0_1_DMDATA_SW_CNTL                                                                     0x0763
++#define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX                                                            2
++#define mmCURSOR0_1_DMDATA_SW_DATA                                                                     0x0764
++#define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
++// base address: 0x1de4
++#define mmDC_PERFMON8_PERFCOUNTER_CNTL                                                                 0x0779
++#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX                                                        2
++#define mmDC_PERFMON8_PERFCOUNTER_CNTL2                                                                0x077a
++#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
++#define mmDC_PERFMON8_PERFCOUNTER_STATE                                                                0x077b
++#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX                                                       2
++#define mmDC_PERFMON8_PERFMON_CNTL                                                                     0x077c
++#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX                                                            2
++#define mmDC_PERFMON8_PERFMON_CNTL2                                                                    0x077d
++#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX                                                           2
++#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                                          0x077e
++#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
++#define mmDC_PERFMON8_PERFMON_CVALUE_LOW                                                               0x077f
++#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
++#define mmDC_PERFMON8_PERFMON_HI                                                                       0x0780
++#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX                                                              2
++#define mmDC_PERFMON8_PERFMON_LOW                                                                      0x0781
++#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
++// base address: 0x6e0
++#define mmHUBP2_DCSURF_SURFACE_CONFIG                                                                  0x079d
++#define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
++#define mmHUBP2_DCSURF_ADDR_CONFIG                                                                     0x079e
++#define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
++#define mmHUBP2_DCSURF_TILING_CONFIG                                                                   0x079f
++#define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
++#define mmHUBP2_DCSURF_PRI_VIEWPORT_START                                                              0x07a1
++#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
++#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x07a2
++#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
++#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C                                                            0x07a3
++#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
++#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x07a4
++#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
++#define mmHUBP2_DCSURF_SEC_VIEWPORT_START                                                              0x07a5
++#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
++#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x07a6
++#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
++#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C                                                            0x07a7
++#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
++#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x07a8
++#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
++#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG                                                                 0x07a9
++#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
++#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x07aa
++#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
++#define mmHUBP2_DCHUBP_CNTL                                                                            0x07ab
++#define mmHUBP2_DCHUBP_CNTL_BASE_IDX                                                                   2
++#define mmHUBP2_HUBP_CLK_CNTL                                                                          0x07ac
++#define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX                                                                 2
++#define mmHUBP2_DCHUBP_VMPG_CONFIG                                                                     0x07ad
++#define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
++#define mmHUBP2_HUBPREQ_DEBUG_DB                                                                       0x07ae
++#define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
++#define mmHUBP2_HUBPREQ_DEBUG                                                                          0x07af
++#define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX                                                                 2
++#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x07b3
++#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
++#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x07b4
++#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
++
++
++// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
++// base address: 0x6e0
++#define mmHUBPREQ2_DCSURF_SURFACE_PITCH                                                                0x07bf
++#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
++#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C                                                              0x07c0
++#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
++#define mmHUBPREQ2_VMID_SETTINGS_0                                                                     0x07c1
++#define mmHUBPREQ2_VMID_SETTINGS_0_BASE_IDX                                                            2
++#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x07c2
++#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
++#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x07c3
++#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
++#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x07c4
++#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
++#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x07c5
++#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
++#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x07c6
++#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
++#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x07c7
++#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
++#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x07c8
++#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
++#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x07c9
++#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
++#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x07ca
++#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
++#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x07cb
++#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
++#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x07cc
++#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
++#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x07cd
++#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
++#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x07ce
++#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
++#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x07cf
++#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
++#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x07d0
++#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
++#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x07d1
++#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
++#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL                                                              0x07d2
++#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
++#define mmHUBPREQ2_DCSURF_FLIP_CONTROL                                                                 0x07d3
++#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
++#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2                                                                0x07d4
++#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
++#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x07d8
++#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
++#define mmHUBPREQ2_DCSURF_SURFACE_INUSE                                                                0x07d9
++#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
++#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH                                                           0x07da
++#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
++#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C                                                              0x07db
++#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
++#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x07dc
++#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
++#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x07dd
++#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
++#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x07de
++#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
++#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x07df
++#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
++#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x07e0
++#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
++#define mmHUBPREQ2_DCN_EXPANSION_MODE                                                                  0x07e4
++#define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX                                                         2
++#define mmHUBPREQ2_DCN_TTU_QOS_WM                                                                      0x07e5
++#define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX                                                             2
++#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL                                                                 0x07e6
++#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
++#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0                                                                 0x07e7
++#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
++#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1                                                                 0x07e8
++#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
++#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0                                                                 0x07e9
++#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
++#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1                                                                 0x07ea
++#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
++#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0                                                                  0x07eb
++#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
++#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1                                                                  0x07ec
++#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
++#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0                                                                  0x07ed
++#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
++#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1                                                                  0x07ee
++#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
++#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x07ef
++#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
++#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x07f0
++#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
++#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL                                                               0x07fd
++#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
++#define mmHUBPREQ2_BLANK_OFFSET_0                                                                      0x07fe
++#define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX                                                             2
++#define mmHUBPREQ2_BLANK_OFFSET_1                                                                      0x07ff
++#define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX                                                             2
++#define mmHUBPREQ2_DST_DIMENSIONS                                                                      0x0800
++#define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX                                                             2
++#define mmHUBPREQ2_DST_AFTER_SCALER                                                                    0x0801
++#define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX                                                           2
++#define mmHUBPREQ2_PREFETCH_SETTINGS                                                                   0x0802
++#define mmHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX                                                          2
++#define mmHUBPREQ2_PREFETCH_SETTINGS_C                                                                 0x0803
++#define mmHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
++#define mmHUBPREQ2_VBLANK_PARAMETERS_0                                                                 0x0804
++#define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
++#define mmHUBPREQ2_VBLANK_PARAMETERS_1                                                                 0x0805
++#define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
++#define mmHUBPREQ2_VBLANK_PARAMETERS_2                                                                 0x0806
++#define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
++#define mmHUBPREQ2_VBLANK_PARAMETERS_3                                                                 0x0807
++#define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
++#define mmHUBPREQ2_VBLANK_PARAMETERS_4                                                                 0x0808
++#define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
++#define mmHUBPREQ2_FLIP_PARAMETERS_0                                                                   0x0809
++#define mmHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX                                                          2
++#define mmHUBPREQ2_FLIP_PARAMETERS_1                                                                   0x080a
++#define mmHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX                                                          2
++#define mmHUBPREQ2_FLIP_PARAMETERS_2                                                                   0x080b
++#define mmHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX                                                          2
++#define mmHUBPREQ2_NOM_PARAMETERS_0                                                                    0x080c
++#define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX                                                           2
++#define mmHUBPREQ2_NOM_PARAMETERS_1                                                                    0x080d
++#define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX                                                           2
++#define mmHUBPREQ2_NOM_PARAMETERS_2                                                                    0x080e
++#define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX                                                           2
++#define mmHUBPREQ2_NOM_PARAMETERS_3                                                                    0x080f
++#define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX                                                           2
++#define mmHUBPREQ2_NOM_PARAMETERS_4                                                                    0x0810
++#define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX                                                           2
++#define mmHUBPREQ2_NOM_PARAMETERS_5                                                                    0x0811
++#define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX                                                           2
++#define mmHUBPREQ2_NOM_PARAMETERS_6                                                                    0x0812
++#define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX                                                           2
++#define mmHUBPREQ2_NOM_PARAMETERS_7                                                                    0x0813
++#define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX                                                           2
++#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE                                                               0x0814
++#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
++#define mmHUBPREQ2_PER_LINE_DELIVERY                                                                   0x0815
++#define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX                                                          2
++#define mmHUBPREQ2_CURSOR_SETTINGS                                                                     0x0816
++#define mmHUBPREQ2_CURSOR_SETTINGS_BASE_IDX                                                            2
++#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ                                                                0x0817
++#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
++#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT                                                               0x0818
++#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
++#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL                                                                0x0819
++#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
++#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS                                                              0x081a
++#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
++#define mmHUBPREQ2_VBLANK_PARAMETERS_5                                                                 0x081d
++#define mmHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
++#define mmHUBPREQ2_VBLANK_PARAMETERS_6                                                                 0x081e
++#define mmHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
++#define mmHUBPREQ2_FLIP_PARAMETERS_3                                                                   0x081f
++#define mmHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX                                                          2
++#define mmHUBPREQ2_FLIP_PARAMETERS_4                                                                   0x0820
++#define mmHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX                                                          2
++#define mmHUBPREQ2_FLIP_PARAMETERS_5                                                                   0x0821
++#define mmHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX                                                          2
++#define mmHUBPREQ2_FLIP_PARAMETERS_6                                                                   0x0822
++#define mmHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
++// base address: 0x6e0
++#define mmHUBPRET2_HUBPRET_CONTROL                                                                     0x0824
++#define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX                                                            2
++#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL                                                                0x0825
++#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
++#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS                                                              0x0826
++#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
++#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0                                                             0x0827
++#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
++#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1                                                             0x0828
++#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
++#define mmHUBPRET2_HUBPRET_READ_LINE0                                                                  0x0829
++#define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX                                                         2
++#define mmHUBPRET2_HUBPRET_READ_LINE1                                                                  0x082a
++#define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX                                                         2
++#define mmHUBPRET2_HUBPRET_INTERRUPT                                                                   0x082b
++#define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX                                                          2
++#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE                                                             0x082c
++#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
++#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS                                                            0x082d
++#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
++
++
++// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
++// base address: 0x6e0
++#define mmCURSOR0_2_CURSOR_CONTROL                                                                     0x0830
++#define mmCURSOR0_2_CURSOR_CONTROL_BASE_IDX                                                            2
++#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS                                                             0x0831
++#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
++#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0832
++#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
++#define mmCURSOR0_2_CURSOR_SIZE                                                                        0x0833
++#define mmCURSOR0_2_CURSOR_SIZE_BASE_IDX                                                               2
++#define mmCURSOR0_2_CURSOR_POSITION                                                                    0x0834
++#define mmCURSOR0_2_CURSOR_POSITION_BASE_IDX                                                           2
++#define mmCURSOR0_2_CURSOR_HOT_SPOT                                                                    0x0835
++#define mmCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX                                                           2
++#define mmCURSOR0_2_CURSOR_STEREO_CONTROL                                                              0x0836
++#define mmCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
++#define mmCURSOR0_2_CURSOR_DST_OFFSET                                                                  0x0837
++#define mmCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX                                                         2
++#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL                                                                0x0838
++#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
++#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS                                                              0x0839
++#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
++#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH                                                                0x083a
++#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
++#define mmCURSOR0_2_DMDATA_ADDRESS_LOW                                                                 0x083b
++#define mmCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
++#define mmCURSOR0_2_DMDATA_CNTL                                                                        0x083c
++#define mmCURSOR0_2_DMDATA_CNTL_BASE_IDX                                                               2
++#define mmCURSOR0_2_DMDATA_QOS_CNTL                                                                    0x083d
++#define mmCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX                                                           2
++#define mmCURSOR0_2_DMDATA_STATUS                                                                      0x083e
++#define mmCURSOR0_2_DMDATA_STATUS_BASE_IDX                                                             2
++#define mmCURSOR0_2_DMDATA_SW_CNTL                                                                     0x083f
++#define mmCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX                                                            2
++#define mmCURSOR0_2_DMDATA_SW_DATA                                                                     0x0840
++#define mmCURSOR0_2_DMDATA_SW_DATA_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
++// base address: 0x2154
++#define mmDC_PERFMON9_PERFCOUNTER_CNTL                                                                 0x0855
++#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX                                                        2
++#define mmDC_PERFMON9_PERFCOUNTER_CNTL2                                                                0x0856
++#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
++#define mmDC_PERFMON9_PERFCOUNTER_STATE                                                                0x0857
++#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX                                                       2
++#define mmDC_PERFMON9_PERFMON_CNTL                                                                     0x0858
++#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX                                                            2
++#define mmDC_PERFMON9_PERFMON_CNTL2                                                                    0x0859
++#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX                                                           2
++#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                                          0x085a
++#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
++#define mmDC_PERFMON9_PERFMON_CVALUE_LOW                                                               0x085b
++#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
++#define mmDC_PERFMON9_PERFMON_HI                                                                       0x085c
++#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX                                                              2
++#define mmDC_PERFMON9_PERFMON_LOW                                                                      0x085d
++#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
++// base address: 0xa50
++#define mmHUBP3_DCSURF_SURFACE_CONFIG                                                                  0x0879
++#define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
++#define mmHUBP3_DCSURF_ADDR_CONFIG                                                                     0x087a
++#define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
++#define mmHUBP3_DCSURF_TILING_CONFIG                                                                   0x087b
++#define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
++#define mmHUBP3_DCSURF_PRI_VIEWPORT_START                                                              0x087d
++#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
++#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x087e
++#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
++#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C                                                            0x087f
++#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
++#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x0880
++#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
++#define mmHUBP3_DCSURF_SEC_VIEWPORT_START                                                              0x0881
++#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
++#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x0882
++#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
++#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C                                                            0x0883
++#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
++#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0884
++#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
++#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0885
++#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
++#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0886
++#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
++#define mmHUBP3_DCHUBP_CNTL                                                                            0x0887
++#define mmHUBP3_DCHUBP_CNTL_BASE_IDX                                                                   2
++#define mmHUBP3_HUBP_CLK_CNTL                                                                          0x0888
++#define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX                                                                 2
++#define mmHUBP3_DCHUBP_VMPG_CONFIG                                                                     0x0889
++#define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
++#define mmHUBP3_HUBPREQ_DEBUG_DB                                                                       0x088a
++#define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
++#define mmHUBP3_HUBPREQ_DEBUG                                                                          0x088b
++#define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX                                                                 2
++#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x088f
++#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
++#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0890
++#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
++
++
++// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
++// base address: 0xa50
++#define mmHUBPREQ3_DCSURF_SURFACE_PITCH                                                                0x089b
++#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
++#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C                                                              0x089c
++#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
++#define mmHUBPREQ3_VMID_SETTINGS_0                                                                     0x089d
++#define mmHUBPREQ3_VMID_SETTINGS_0_BASE_IDX                                                            2
++#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x089e
++#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
++#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x089f
++#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
++#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x08a0
++#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
++#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x08a1
++#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
++#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x08a2
++#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
++#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x08a3
++#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
++#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x08a4
++#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
++#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x08a5
++#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
++#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x08a6
++#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
++#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x08a7
++#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
++#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x08a8
++#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
++#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x08a9
++#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
++#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x08aa
++#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
++#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x08ab
++#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
++#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x08ac
++#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
++#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x08ad
++#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
++#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL                                                              0x08ae
++#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
++#define mmHUBPREQ3_DCSURF_FLIP_CONTROL                                                                 0x08af
++#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
++#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2                                                                0x08b0
++#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
++#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x08b4
++#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
++#define mmHUBPREQ3_DCSURF_SURFACE_INUSE                                                                0x08b5
++#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
++#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH                                                           0x08b6
++#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
++#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C                                                              0x08b7
++#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
++#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x08b8
++#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
++#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x08b9
++#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
++#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x08ba
++#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
++#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x08bb
++#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
++#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x08bc
++#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
++#define mmHUBPREQ3_DCN_EXPANSION_MODE                                                                  0x08c0
++#define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX                                                         2
++#define mmHUBPREQ3_DCN_TTU_QOS_WM                                                                      0x08c1
++#define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX                                                             2
++#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL                                                                 0x08c2
++#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
++#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0                                                                 0x08c3
++#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
++#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1                                                                 0x08c4
++#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
++#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0                                                                 0x08c5
++#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
++#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1                                                                 0x08c6
++#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
++#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0                                                                  0x08c7
++#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
++#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1                                                                  0x08c8
++#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
++#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0                                                                  0x08c9
++#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
++#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1                                                                  0x08ca
++#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
++#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x08cb
++#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
++#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x08cc
++#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
++#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL                                                               0x08d9
++#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
++#define mmHUBPREQ3_BLANK_OFFSET_0                                                                      0x08da
++#define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX                                                             2
++#define mmHUBPREQ3_BLANK_OFFSET_1                                                                      0x08db
++#define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX                                                             2
++#define mmHUBPREQ3_DST_DIMENSIONS                                                                      0x08dc
++#define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX                                                             2
++#define mmHUBPREQ3_DST_AFTER_SCALER                                                                    0x08dd
++#define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX                                                           2
++#define mmHUBPREQ3_PREFETCH_SETTINGS                                                                   0x08de
++#define mmHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX                                                          2
++#define mmHUBPREQ3_PREFETCH_SETTINGS_C                                                                 0x08df
++#define mmHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
++#define mmHUBPREQ3_VBLANK_PARAMETERS_0                                                                 0x08e0
++#define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
++#define mmHUBPREQ3_VBLANK_PARAMETERS_1                                                                 0x08e1
++#define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
++#define mmHUBPREQ3_VBLANK_PARAMETERS_2                                                                 0x08e2
++#define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
++#define mmHUBPREQ3_VBLANK_PARAMETERS_3                                                                 0x08e3
++#define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
++#define mmHUBPREQ3_VBLANK_PARAMETERS_4                                                                 0x08e4
++#define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
++#define mmHUBPREQ3_FLIP_PARAMETERS_0                                                                   0x08e5
++#define mmHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX                                                          2
++#define mmHUBPREQ3_FLIP_PARAMETERS_1                                                                   0x08e6
++#define mmHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX                                                          2
++#define mmHUBPREQ3_FLIP_PARAMETERS_2                                                                   0x08e7
++#define mmHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX                                                          2
++#define mmHUBPREQ3_NOM_PARAMETERS_0                                                                    0x08e8
++#define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX                                                           2
++#define mmHUBPREQ3_NOM_PARAMETERS_1                                                                    0x08e9
++#define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX                                                           2
++#define mmHUBPREQ3_NOM_PARAMETERS_2                                                                    0x08ea
++#define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX                                                           2
++#define mmHUBPREQ3_NOM_PARAMETERS_3                                                                    0x08eb
++#define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX                                                           2
++#define mmHUBPREQ3_NOM_PARAMETERS_4                                                                    0x08ec
++#define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX                                                           2
++#define mmHUBPREQ3_NOM_PARAMETERS_5                                                                    0x08ed
++#define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX                                                           2
++#define mmHUBPREQ3_NOM_PARAMETERS_6                                                                    0x08ee
++#define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX                                                           2
++#define mmHUBPREQ3_NOM_PARAMETERS_7                                                                    0x08ef
++#define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX                                                           2
++#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE                                                               0x08f0
++#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
++#define mmHUBPREQ3_PER_LINE_DELIVERY                                                                   0x08f1
++#define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX                                                          2
++#define mmHUBPREQ3_CURSOR_SETTINGS                                                                     0x08f2
++#define mmHUBPREQ3_CURSOR_SETTINGS_BASE_IDX                                                            2
++#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ                                                                0x08f3
++#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
++#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT                                                               0x08f4
++#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
++#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL                                                                0x08f5
++#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
++#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS                                                              0x08f6
++#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
++#define mmHUBPREQ3_VBLANK_PARAMETERS_5                                                                 0x08f9
++#define mmHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
++#define mmHUBPREQ3_VBLANK_PARAMETERS_6                                                                 0x08fa
++#define mmHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
++#define mmHUBPREQ3_FLIP_PARAMETERS_3                                                                   0x08fb
++#define mmHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX                                                          2
++#define mmHUBPREQ3_FLIP_PARAMETERS_4                                                                   0x08fc
++#define mmHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX                                                          2
++#define mmHUBPREQ3_FLIP_PARAMETERS_5                                                                   0x08fd
++#define mmHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX                                                          2
++#define mmHUBPREQ3_FLIP_PARAMETERS_6                                                                   0x08fe
++#define mmHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
++// base address: 0xa50
++#define mmHUBPRET3_HUBPRET_CONTROL                                                                     0x0900
++#define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX                                                            2
++#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL                                                                0x0901
++#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
++#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS                                                              0x0902
++#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
++#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0                                                             0x0903
++#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
++#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1                                                             0x0904
++#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
++#define mmHUBPRET3_HUBPRET_READ_LINE0                                                                  0x0905
++#define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX                                                         2
++#define mmHUBPRET3_HUBPRET_READ_LINE1                                                                  0x0906
++#define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX                                                         2
++#define mmHUBPRET3_HUBPRET_INTERRUPT                                                                   0x0907
++#define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX                                                          2
++#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE                                                             0x0908
++#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
++#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS                                                            0x0909
++#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
++
++
++// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
++// base address: 0xa50
++#define mmCURSOR0_3_CURSOR_CONTROL                                                                     0x090c
++#define mmCURSOR0_3_CURSOR_CONTROL_BASE_IDX                                                            2
++#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS                                                             0x090d
++#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
++#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x090e
++#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
++#define mmCURSOR0_3_CURSOR_SIZE                                                                        0x090f
++#define mmCURSOR0_3_CURSOR_SIZE_BASE_IDX                                                               2
++#define mmCURSOR0_3_CURSOR_POSITION                                                                    0x0910
++#define mmCURSOR0_3_CURSOR_POSITION_BASE_IDX                                                           2
++#define mmCURSOR0_3_CURSOR_HOT_SPOT                                                                    0x0911
++#define mmCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX                                                           2
++#define mmCURSOR0_3_CURSOR_STEREO_CONTROL                                                              0x0912
++#define mmCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
++#define mmCURSOR0_3_CURSOR_DST_OFFSET                                                                  0x0913
++#define mmCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX                                                         2
++#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL                                                                0x0914
++#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
++#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS                                                              0x0915
++#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
++#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH                                                                0x0916
++#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
++#define mmCURSOR0_3_DMDATA_ADDRESS_LOW                                                                 0x0917
++#define mmCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
++#define mmCURSOR0_3_DMDATA_CNTL                                                                        0x0918
++#define mmCURSOR0_3_DMDATA_CNTL_BASE_IDX                                                               2
++#define mmCURSOR0_3_DMDATA_QOS_CNTL                                                                    0x0919
++#define mmCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX                                                           2
++#define mmCURSOR0_3_DMDATA_STATUS                                                                      0x091a
++#define mmCURSOR0_3_DMDATA_STATUS_BASE_IDX                                                             2
++#define mmCURSOR0_3_DMDATA_SW_CNTL                                                                     0x091b
++#define mmCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX                                                            2
++#define mmCURSOR0_3_DMDATA_SW_DATA                                                                     0x091c
++#define mmCURSOR0_3_DMDATA_SW_DATA_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
++// base address: 0x24c4
++#define mmDC_PERFMON10_PERFCOUNTER_CNTL                                                                0x0931
++#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX                                                       2
++#define mmDC_PERFMON10_PERFCOUNTER_CNTL2                                                               0x0932
++#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
++#define mmDC_PERFMON10_PERFCOUNTER_STATE                                                               0x0933
++#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX                                                      2
++#define mmDC_PERFMON10_PERFMON_CNTL                                                                    0x0934
++#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX                                                           2
++#define mmDC_PERFMON10_PERFMON_CNTL2                                                                   0x0935
++#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX                                                          2
++#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC                                                         0x0936
++#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
++#define mmDC_PERFMON10_PERFMON_CVALUE_LOW                                                              0x0937
++#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
++#define mmDC_PERFMON10_PERFMON_HI                                                                      0x0938
++#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX                                                             2
++#define mmDC_PERFMON10_PERFMON_LOW                                                                     0x0939
++#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
++// base address: 0x0
++#define mmDPP_TOP0_DPP_CONTROL                                                                         0x0cc5
++#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX                                                                2
++#define mmDPP_TOP0_DPP_SOFT_RESET                                                                      0x0cc6
++#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX                                                             2
++#define mmDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7
++#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
++#define mmDPP_TOP0_DPP_CRC_VAL_B_A                                                                     0x0cc8
++#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
++#define mmDPP_TOP0_DPP_CRC_CTRL                                                                        0x0cc9
++#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2
++#define mmDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca
++#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
++// base address: 0x0
++#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0ccf
++#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
++#define mmCNVC_CFG0_FORMAT_CONTROL                                                                     0x0cd0
++#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX                                                            2
++#define mmCNVC_CFG0_FCNV_FP_BIAS_R                                                                     0x0cd1
++#define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX                                                            2
++#define mmCNVC_CFG0_FCNV_FP_BIAS_G                                                                     0x0cd2
++#define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX                                                            2
++#define mmCNVC_CFG0_FCNV_FP_BIAS_B                                                                     0x0cd3
++#define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX                                                            2
++#define mmCNVC_CFG0_FCNV_FP_SCALE_R                                                                    0x0cd4
++#define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX                                                           2
++#define mmCNVC_CFG0_FCNV_FP_SCALE_G                                                                    0x0cd5
++#define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX                                                           2
++#define mmCNVC_CFG0_FCNV_FP_SCALE_B                                                                    0x0cd6
++#define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX                                                           2
++#define mmCNVC_CFG0_COLOR_KEYER_CONTROL                                                                0x0cd7
++#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
++#define mmCNVC_CFG0_COLOR_KEYER_ALPHA                                                                  0x0cd8
++#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
++#define mmCNVC_CFG0_COLOR_KEYER_RED                                                                    0x0cd9
++#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX                                                           2
++#define mmCNVC_CFG0_COLOR_KEYER_GREEN                                                                  0x0cda
++#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX                                                         2
++#define mmCNVC_CFG0_COLOR_KEYER_BLUE                                                                   0x0cdb
++#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX                                                          2
++#define mmCNVC_CFG0_ALPHA_2BIT_LUT                                                                     0x0cdd
++#define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
++// base address: 0x0
++#define mmCNVC_CUR0_CURSOR0_CONTROL                                                                    0x0ce0
++#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX                                                           2
++#define mmCNVC_CUR0_CURSOR0_COLOR0                                                                     0x0ce1
++#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX                                                            2
++#define mmCNVC_CUR0_CURSOR0_COLOR1                                                                     0x0ce2
++#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX                                                            2
++#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS                                                              0x0ce3
++#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
++
++
++// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
++// base address: 0x0
++#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cea
++#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
++#define mmDSCL0_SCL_COEF_RAM_TAP_DATA                                                                  0x0ceb
++#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
++#define mmDSCL0_SCL_MODE                                                                               0x0cec
++#define mmDSCL0_SCL_MODE_BASE_IDX                                                                      2
++#define mmDSCL0_SCL_TAP_CONTROL                                                                        0x0ced
++#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX                                                               2
++#define mmDSCL0_DSCL_CONTROL                                                                           0x0cee
++#define mmDSCL0_DSCL_CONTROL_BASE_IDX                                                                  2
++#define mmDSCL0_DSCL_2TAP_CONTROL                                                                      0x0cef
++#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
++#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0cf0
++#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
++#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0cf1
++#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
++#define mmDSCL0_SCL_HORZ_FILTER_INIT                                                                   0x0cf2
++#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
++#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0cf3
++#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
++#define mmDSCL0_SCL_HORZ_FILTER_INIT_C                                                                 0x0cf4
++#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
++#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0cf5
++#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
++#define mmDSCL0_SCL_VERT_FILTER_INIT                                                                   0x0cf6
++#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
++#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT                                                               0x0cf7
++#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
++#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0cf8
++#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
++#define mmDSCL0_SCL_VERT_FILTER_INIT_C                                                                 0x0cf9
++#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
++#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0cfa
++#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
++#define mmDSCL0_SCL_BLACK_OFFSET                                                                       0x0cfb
++#define mmDSCL0_SCL_BLACK_OFFSET_BASE_IDX                                                              2
++#define mmDSCL0_DSCL_UPDATE                                                                            0x0cfc
++#define mmDSCL0_DSCL_UPDATE_BASE_IDX                                                                   2
++#define mmDSCL0_DSCL_AUTOCAL                                                                           0x0cfd
++#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX                                                                  2
++#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0cfe
++#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
++#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0cff
++#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
++#define mmDSCL0_OTG_H_BLANK                                                                            0x0d00
++#define mmDSCL0_OTG_H_BLANK_BASE_IDX                                                                   2
++#define mmDSCL0_OTG_V_BLANK                                                                            0x0d01
++#define mmDSCL0_OTG_V_BLANK_BASE_IDX                                                                   2
++#define mmDSCL0_RECOUT_START                                                                           0x0d02
++#define mmDSCL0_RECOUT_START_BASE_IDX                                                                  2
++#define mmDSCL0_RECOUT_SIZE                                                                            0x0d03
++#define mmDSCL0_RECOUT_SIZE_BASE_IDX                                                                   2
++#define mmDSCL0_MPC_SIZE                                                                               0x0d04
++#define mmDSCL0_MPC_SIZE_BASE_IDX                                                                      2
++#define mmDSCL0_LB_DATA_FORMAT                                                                         0x0d05
++#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX                                                                2
++#define mmDSCL0_LB_MEMORY_CTRL                                                                         0x0d06
++#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX                                                                2
++#define mmDSCL0_LB_V_COUNTER                                                                           0x0d07
++#define mmDSCL0_LB_V_COUNTER_BASE_IDX                                                                  2
++#define mmDSCL0_DSCL_MEM_PWR_CTRL                                                                      0x0d08
++#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
++#define mmDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d09
++#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
++#define mmDSCL0_OBUF_CONTROL                                                                           0x0d0a
++#define mmDSCL0_OBUF_CONTROL_BASE_IDX                                                                  2
++#define mmDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d0b
++#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
++// base address: 0x0
++#define mmCM0_CM_CONTROL                                                                               0x0d1a
++#define mmCM0_CM_CONTROL_BASE_IDX                                                                      2
++#define mmCM0_CM_ICSC_CONTROL                                                                          0x0d1b
++#define mmCM0_CM_ICSC_CONTROL_BASE_IDX                                                                 2
++#define mmCM0_CM_ICSC_C11_C12                                                                          0x0d1c
++#define mmCM0_CM_ICSC_C11_C12_BASE_IDX                                                                 2
++#define mmCM0_CM_ICSC_C13_C14                                                                          0x0d1d
++#define mmCM0_CM_ICSC_C13_C14_BASE_IDX                                                                 2
++#define mmCM0_CM_ICSC_C21_C22                                                                          0x0d1e
++#define mmCM0_CM_ICSC_C21_C22_BASE_IDX                                                                 2
++#define mmCM0_CM_ICSC_C23_C24                                                                          0x0d1f
++#define mmCM0_CM_ICSC_C23_C24_BASE_IDX                                                                 2
++#define mmCM0_CM_ICSC_C31_C32                                                                          0x0d20
++#define mmCM0_CM_ICSC_C31_C32_BASE_IDX                                                                 2
++#define mmCM0_CM_ICSC_C33_C34                                                                          0x0d21
++#define mmCM0_CM_ICSC_C33_C34_BASE_IDX                                                                 2
++#define mmCM0_CM_ICSC_B_C11_C12                                                                        0x0d22
++#define mmCM0_CM_ICSC_B_C11_C12_BASE_IDX                                                               2
++#define mmCM0_CM_ICSC_B_C13_C14                                                                        0x0d23
++#define mmCM0_CM_ICSC_B_C13_C14_BASE_IDX                                                               2
++#define mmCM0_CM_ICSC_B_C21_C22                                                                        0x0d24
++#define mmCM0_CM_ICSC_B_C21_C22_BASE_IDX                                                               2
++#define mmCM0_CM_ICSC_B_C23_C24                                                                        0x0d25
++#define mmCM0_CM_ICSC_B_C23_C24_BASE_IDX                                                               2
++#define mmCM0_CM_ICSC_B_C31_C32                                                                        0x0d26
++#define mmCM0_CM_ICSC_B_C31_C32_BASE_IDX                                                               2
++#define mmCM0_CM_ICSC_B_C33_C34                                                                        0x0d27
++#define mmCM0_CM_ICSC_B_C33_C34_BASE_IDX                                                               2
++#define mmCM0_CM_GAMUT_REMAP_CONTROL                                                                   0x0d28
++#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
++#define mmCM0_CM_GAMUT_REMAP_C11_C12                                                                   0x0d29
++#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
++#define mmCM0_CM_GAMUT_REMAP_C13_C14                                                                   0x0d2a
++#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
++#define mmCM0_CM_GAMUT_REMAP_C21_C22                                                                   0x0d2b
++#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
++#define mmCM0_CM_GAMUT_REMAP_C23_C24                                                                   0x0d2c
++#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
++#define mmCM0_CM_GAMUT_REMAP_C31_C32                                                                   0x0d2d
++#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
++#define mmCM0_CM_GAMUT_REMAP_C33_C34                                                                   0x0d2e
++#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
++#define mmCM0_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0d2f
++#define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
++#define mmCM0_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0d30
++#define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
++#define mmCM0_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0d31
++#define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
++#define mmCM0_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0d32
++#define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
++#define mmCM0_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0d33
++#define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
++#define mmCM0_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0d34
++#define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
++#define mmCM0_CM_BIAS_CR_R                                                                             0x0d35
++#define mmCM0_CM_BIAS_CR_R_BASE_IDX                                                                    2
++#define mmCM0_CM_BIAS_Y_G_CB_B                                                                         0x0d36
++#define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
++#define mmCM0_CM_DGAM_CONTROL                                                                          0x0d37
++#define mmCM0_CM_DGAM_CONTROL_BASE_IDX                                                                 2
++#define mmCM0_CM_DGAM_LUT_INDEX                                                                        0x0d38
++#define mmCM0_CM_DGAM_LUT_INDEX_BASE_IDX                                                               2
++#define mmCM0_CM_DGAM_LUT_DATA                                                                         0x0d39
++#define mmCM0_CM_DGAM_LUT_DATA_BASE_IDX                                                                2
++#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK                                                                0x0d3a
++#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                       2
++#define mmCM0_CM_DGAM_RAMA_START_CNTL_B                                                                0x0d3b
++#define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX                                                       2
++#define mmCM0_CM_DGAM_RAMA_START_CNTL_G                                                                0x0d3c
++#define mmCM0_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX                                                       2
++#define mmCM0_CM_DGAM_RAMA_START_CNTL_R                                                                0x0d3d
++#define mmCM0_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX                                                       2
++#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B                                                                0x0d3e
++#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                       2
++#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G                                                                0x0d3f
++#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                       2
++#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R                                                                0x0d40
++#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                       2
++#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x0d41
++#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX                                                        2
++#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B                                                                 0x0d42
++#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX                                                        2
++#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x0d43
++#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        2
++#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G                                                                 0x0d44
++#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX                                                        2
++#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x0d45
++#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX                                                        2
++#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R                                                                 0x0d46
++#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX                                                        2
++#define mmCM0_CM_DGAM_RAMA_REGION_0_1                                                                  0x0d47
++#define mmCM0_CM_DGAM_RAMA_REGION_0_1_BASE_IDX                                                         2
++#define mmCM0_CM_DGAM_RAMA_REGION_2_3                                                                  0x0d48
++#define mmCM0_CM_DGAM_RAMA_REGION_2_3_BASE_IDX                                                         2
++#define mmCM0_CM_DGAM_RAMA_REGION_4_5                                                                  0x0d49
++#define mmCM0_CM_DGAM_RAMA_REGION_4_5_BASE_IDX                                                         2
++#define mmCM0_CM_DGAM_RAMA_REGION_6_7                                                                  0x0d4a
++#define mmCM0_CM_DGAM_RAMA_REGION_6_7_BASE_IDX                                                         2
++#define mmCM0_CM_DGAM_RAMA_REGION_8_9                                                                  0x0d4b
++#define mmCM0_CM_DGAM_RAMA_REGION_8_9_BASE_IDX                                                         2
++#define mmCM0_CM_DGAM_RAMA_REGION_10_11                                                                0x0d4c
++#define mmCM0_CM_DGAM_RAMA_REGION_10_11_BASE_IDX                                                       2
++#define mmCM0_CM_DGAM_RAMA_REGION_12_13                                                                0x0d4d
++#define mmCM0_CM_DGAM_RAMA_REGION_12_13_BASE_IDX                                                       2
++#define mmCM0_CM_DGAM_RAMA_REGION_14_15                                                                0x0d4e
++#define mmCM0_CM_DGAM_RAMA_REGION_14_15_BASE_IDX                                                       2
++#define mmCM0_CM_DGAM_RAMB_START_CNTL_B                                                                0x0d4f
++#define mmCM0_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX                                                       2
++#define mmCM0_CM_DGAM_RAMB_START_CNTL_G                                                                0x0d50
++#define mmCM0_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX                                                       2
++#define mmCM0_CM_DGAM_RAMB_START_CNTL_R                                                                0x0d51
++#define mmCM0_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX                                                       2
++#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B                                                                0x0d52
++#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                       2
++#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G                                                                0x0d53
++#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                       2
++#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R                                                                0x0d54
++#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                       2
++#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B                                                                 0x0d55
++#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX                                                        2
++#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B                                                                 0x0d56
++#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX                                                        2
++#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G                                                                 0x0d57
++#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX                                                        2
++#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G                                                                 0x0d58
++#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX                                                        2
++#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R                                                                 0x0d59
++#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX                                                        2
++#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R                                                                 0x0d5a
++#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX                                                        2
++#define mmCM0_CM_DGAM_RAMB_REGION_0_1                                                                  0x0d5b
++#define mmCM0_CM_DGAM_RAMB_REGION_0_1_BASE_IDX                                                         2
++#define mmCM0_CM_DGAM_RAMB_REGION_2_3                                                                  0x0d5c
++#define mmCM0_CM_DGAM_RAMB_REGION_2_3_BASE_IDX                                                         2
++#define mmCM0_CM_DGAM_RAMB_REGION_4_5                                                                  0x0d5d
++#define mmCM0_CM_DGAM_RAMB_REGION_4_5_BASE_IDX                                                         2
++#define mmCM0_CM_DGAM_RAMB_REGION_6_7                                                                  0x0d5e
++#define mmCM0_CM_DGAM_RAMB_REGION_6_7_BASE_IDX                                                         2
++#define mmCM0_CM_DGAM_RAMB_REGION_8_9                                                                  0x0d5f
++#define mmCM0_CM_DGAM_RAMB_REGION_8_9_BASE_IDX                                                         2
++#define mmCM0_CM_DGAM_RAMB_REGION_10_11                                                                0x0d60
++#define mmCM0_CM_DGAM_RAMB_REGION_10_11_BASE_IDX                                                       2
++#define mmCM0_CM_DGAM_RAMB_REGION_12_13                                                                0x0d61
++#define mmCM0_CM_DGAM_RAMB_REGION_12_13_BASE_IDX                                                       2
++#define mmCM0_CM_DGAM_RAMB_REGION_14_15                                                                0x0d62
++#define mmCM0_CM_DGAM_RAMB_REGION_14_15_BASE_IDX                                                       2
++#define mmCM0_CM_BLNDGAM_CONTROL                                                                       0x0d63
++#define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
++#define mmCM0_CM_BLNDGAM_LUT_INDEX                                                                     0x0d64
++#define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
++#define mmCM0_CM_BLNDGAM_LUT_DATA                                                                      0x0d65
++#define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
++#define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK                                                             0x0d66
++#define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x0d67
++#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0d68
++#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x0d69
++#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B                                                             0x0d6a
++#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G                                                             0x0d6b
++#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R                                                             0x0d6c
++#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0d6d
++#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
++#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x0d6e
++#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
++#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0d6f
++#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
++#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x0d70
++#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
++#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0d71
++#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
++#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0d72
++#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x0d73
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x0d74
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x0d75
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x0d76
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x0d77
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x0d78
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x0d79
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x0d7a
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x0d7b
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x0d7c
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x0d7d
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x0d7e
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x0d7f
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x0d80
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x0d81
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x0d82
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x0d83
++#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x0d84
++#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x0d85
++#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x0d86
++#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B                                                             0x0d87
++#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G                                                             0x0d88
++#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R                                                             0x0d89
++#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x0d8a
++#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
++#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x0d8b
++#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
++#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x0d8c
++#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
++#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x0d8d
++#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
++#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x0d8e
++#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
++#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x0d8f
++#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x0d90
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x0d91
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x0d92
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x0d93
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x0d94
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x0d95
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x0d96
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x0d97
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x0d98
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x0d99
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x0d9a
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x0d9b
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x0d9c
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x0d9d
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x0d9e
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x0d9f
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x0da0
++#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
++#define mmCM0_CM_HDR_MULT_COEF                                                                         0x0da1
++#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX                                                                2
++#define mmCM0_CM_MEM_PWR_CTRL                                                                          0x0da2
++#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
++#define mmCM0_CM_MEM_PWR_STATUS                                                                        0x0da3
++#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
++#define mmCM0_CM_DEALPHA                                                                               0x0da5
++#define mmCM0_CM_DEALPHA_BASE_IDX                                                                      2
++#define mmCM0_CM_COEF_FORMAT                                                                           0x0da6
++#define mmCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2
++#define mmCM0_CM_SHAPER_CONTROL                                                                        0x0da7
++#define mmCM0_CM_SHAPER_CONTROL_BASE_IDX                                                               2
++#define mmCM0_CM_SHAPER_OFFSET_R                                                                       0x0da8
++#define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
++#define mmCM0_CM_SHAPER_OFFSET_G                                                                       0x0da9
++#define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
++#define mmCM0_CM_SHAPER_OFFSET_B                                                                       0x0daa
++#define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
++#define mmCM0_CM_SHAPER_SCALE_R                                                                        0x0dab
++#define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
++#define mmCM0_CM_SHAPER_SCALE_G_B                                                                      0x0dac
++#define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
++#define mmCM0_CM_SHAPER_LUT_INDEX                                                                      0x0dad
++#define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
++#define mmCM0_CM_SHAPER_LUT_DATA                                                                       0x0dae
++#define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
++#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x0daf
++#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B                                                              0x0db0
++#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G                                                              0x0db1
++#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R                                                              0x0db2
++#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B                                                                0x0db3
++#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
++#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G                                                                0x0db4
++#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
++#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R                                                                0x0db5
++#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
++#define mmCM0_CM_SHAPER_RAMA_REGION_0_1                                                                0x0db6
++#define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
++#define mmCM0_CM_SHAPER_RAMA_REGION_2_3                                                                0x0db7
++#define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
++#define mmCM0_CM_SHAPER_RAMA_REGION_4_5                                                                0x0db8
++#define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
++#define mmCM0_CM_SHAPER_RAMA_REGION_6_7                                                                0x0db9
++#define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
++#define mmCM0_CM_SHAPER_RAMA_REGION_8_9                                                                0x0dba
++#define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
++#define mmCM0_CM_SHAPER_RAMA_REGION_10_11                                                              0x0dbb
++#define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMA_REGION_12_13                                                              0x0dbc
++#define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMA_REGION_14_15                                                              0x0dbd
++#define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMA_REGION_16_17                                                              0x0dbe
++#define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMA_REGION_18_19                                                              0x0dbf
++#define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMA_REGION_20_21                                                              0x0dc0
++#define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMA_REGION_22_23                                                              0x0dc1
++#define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMA_REGION_24_25                                                              0x0dc2
++#define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMA_REGION_26_27                                                              0x0dc3
++#define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMA_REGION_28_29                                                              0x0dc4
++#define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMA_REGION_30_31                                                              0x0dc5
++#define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMA_REGION_32_33                                                              0x0dc6
++#define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B                                                              0x0dc7
++#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G                                                              0x0dc8
++#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R                                                              0x0dc9
++#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B                                                                0x0dca
++#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
++#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G                                                                0x0dcb
++#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
++#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R                                                                0x0dcc
++#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
++#define mmCM0_CM_SHAPER_RAMB_REGION_0_1                                                                0x0dcd
++#define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
++#define mmCM0_CM_SHAPER_RAMB_REGION_2_3                                                                0x0dce
++#define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
++#define mmCM0_CM_SHAPER_RAMB_REGION_4_5                                                                0x0dcf
++#define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
++#define mmCM0_CM_SHAPER_RAMB_REGION_6_7                                                                0x0dd0
++#define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
++#define mmCM0_CM_SHAPER_RAMB_REGION_8_9                                                                0x0dd1
++#define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
++#define mmCM0_CM_SHAPER_RAMB_REGION_10_11                                                              0x0dd2
++#define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMB_REGION_12_13                                                              0x0dd3
++#define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMB_REGION_14_15                                                              0x0dd4
++#define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMB_REGION_16_17                                                              0x0dd5
++#define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMB_REGION_18_19                                                              0x0dd6
++#define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMB_REGION_20_21                                                              0x0dd7
++#define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMB_REGION_22_23                                                              0x0dd8
++#define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMB_REGION_24_25                                                              0x0dd9
++#define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMB_REGION_26_27                                                              0x0dda
++#define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMB_REGION_28_29                                                              0x0ddb
++#define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMB_REGION_30_31                                                              0x0ddc
++#define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
++#define mmCM0_CM_SHAPER_RAMB_REGION_32_33                                                              0x0ddd
++#define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
++#define mmCM0_CM_MEM_PWR_CTRL2                                                                         0x0dde
++#define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
++#define mmCM0_CM_MEM_PWR_STATUS2                                                                       0x0ddf
++#define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
++#define mmCM0_CM_3DLUT_MODE                                                                            0x0de0
++#define mmCM0_CM_3DLUT_MODE_BASE_IDX                                                                   2
++#define mmCM0_CM_3DLUT_INDEX                                                                           0x0de1
++#define mmCM0_CM_3DLUT_INDEX_BASE_IDX                                                                  2
++#define mmCM0_CM_3DLUT_DATA                                                                            0x0de2
++#define mmCM0_CM_3DLUT_DATA_BASE_IDX                                                                   2
++#define mmCM0_CM_3DLUT_DATA_30BIT                                                                      0x0de3
++#define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
++#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL                                                              0x0de4
++#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
++#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x0de5
++#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
++#define mmCM0_CM_3DLUT_OUT_OFFSET_R                                                                    0x0de6
++#define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
++#define mmCM0_CM_3DLUT_OUT_OFFSET_G                                                                    0x0de7
++#define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
++#define mmCM0_CM_3DLUT_OUT_OFFSET_B                                                                    0x0de8
++#define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
++#define mmCM0_CM_TEST_DEBUG_INDEX                                                                      0x0de9
++#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
++#define mmCM0_CM_TEST_DEBUG_DATA                                                                       0x0dea
++#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
++
++
++// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
++// base address: 0x3890
++#define mmDC_PERFMON11_PERFCOUNTER_CNTL                                                                0x0e24
++#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX                                                       2
++#define mmDC_PERFMON11_PERFCOUNTER_CNTL2                                                               0x0e25
++#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
++#define mmDC_PERFMON11_PERFCOUNTER_STATE                                                               0x0e26
++#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX                                                      2
++#define mmDC_PERFMON11_PERFMON_CNTL                                                                    0x0e27
++#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX                                                           2
++#define mmDC_PERFMON11_PERFMON_CNTL2                                                                   0x0e28
++#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX                                                          2
++#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC                                                         0x0e29
++#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
++#define mmDC_PERFMON11_PERFMON_CVALUE_LOW                                                              0x0e2a
++#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
++#define mmDC_PERFMON11_PERFMON_HI                                                                      0x0e2b
++#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX                                                             2
++#define mmDC_PERFMON11_PERFMON_LOW                                                                     0x0e2c
++#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
++// base address: 0x5ac
++#define mmDPP_TOP1_DPP_CONTROL                                                                         0x0e30
++#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX                                                                2
++#define mmDPP_TOP1_DPP_SOFT_RESET                                                                      0x0e31
++#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX                                                             2
++#define mmDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32
++#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
++#define mmDPP_TOP1_DPP_CRC_VAL_B_A                                                                     0x0e33
++#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
++#define mmDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34
++#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX                                                               2
++#define mmDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35
++#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
++// base address: 0x5ac
++#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0e3a
++#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
++#define mmCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b
++#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2
++#define mmCNVC_CFG1_FCNV_FP_BIAS_R                                                                     0x0e3c
++#define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX                                                            2
++#define mmCNVC_CFG1_FCNV_FP_BIAS_G                                                                     0x0e3d
++#define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX                                                            2
++#define mmCNVC_CFG1_FCNV_FP_BIAS_B                                                                     0x0e3e
++#define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX                                                            2
++#define mmCNVC_CFG1_FCNV_FP_SCALE_R                                                                    0x0e3f
++#define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX                                                           2
++#define mmCNVC_CFG1_FCNV_FP_SCALE_G                                                                    0x0e40
++#define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX                                                           2
++#define mmCNVC_CFG1_FCNV_FP_SCALE_B                                                                    0x0e41
++#define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX                                                           2
++#define mmCNVC_CFG1_COLOR_KEYER_CONTROL                                                                0x0e42
++#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
++#define mmCNVC_CFG1_COLOR_KEYER_ALPHA                                                                  0x0e43
++#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
++#define mmCNVC_CFG1_COLOR_KEYER_RED                                                                    0x0e44
++#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX                                                           2
++#define mmCNVC_CFG1_COLOR_KEYER_GREEN                                                                  0x0e45
++#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX                                                         2
++#define mmCNVC_CFG1_COLOR_KEYER_BLUE                                                                   0x0e46
++#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX                                                          2
++#define mmCNVC_CFG1_ALPHA_2BIT_LUT                                                                     0x0e48
++#define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
++// base address: 0x5ac
++#define mmCNVC_CUR1_CURSOR0_CONTROL                                                                    0x0e4b
++#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2
++#define mmCNVC_CUR1_CURSOR0_COLOR0                                                                     0x0e4c
++#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX                                                            2
++#define mmCNVC_CUR1_CURSOR0_COLOR1                                                                     0x0e4d
++#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX                                                            2
++#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS                                                              0x0e4e
++#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
++
++
++// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
++// base address: 0x5ac
++#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT                                                                0x0e55
++#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
++#define mmDSCL1_SCL_COEF_RAM_TAP_DATA                                                                  0x0e56
++#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
++#define mmDSCL1_SCL_MODE                                                                               0x0e57
++#define mmDSCL1_SCL_MODE_BASE_IDX                                                                      2
++#define mmDSCL1_SCL_TAP_CONTROL                                                                        0x0e58
++#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2
++#define mmDSCL1_DSCL_CONTROL                                                                           0x0e59
++#define mmDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2
++#define mmDSCL1_DSCL_2TAP_CONTROL                                                                      0x0e5a
++#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
++#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0e5b
++#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
++#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0e5c
++#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
++#define mmDSCL1_SCL_HORZ_FILTER_INIT                                                                   0x0e5d
++#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
++#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0e5e
++#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
++#define mmDSCL1_SCL_HORZ_FILTER_INIT_C                                                                 0x0e5f
++#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
++#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0e60
++#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
++#define mmDSCL1_SCL_VERT_FILTER_INIT                                                                   0x0e61
++#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
++#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT                                                               0x0e62
++#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
++#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0e63
++#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
++#define mmDSCL1_SCL_VERT_FILTER_INIT_C                                                                 0x0e64
++#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
++#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0e65
++#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
++#define mmDSCL1_SCL_BLACK_OFFSET                                                                       0x0e66
++#define mmDSCL1_SCL_BLACK_OFFSET_BASE_IDX                                                              2
++#define mmDSCL1_DSCL_UPDATE                                                                            0x0e67
++#define mmDSCL1_DSCL_UPDATE_BASE_IDX                                                                   2
++#define mmDSCL1_DSCL_AUTOCAL                                                                           0x0e68
++#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX                                                                  2
++#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0e69
++#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
++#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0e6a
++#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
++#define mmDSCL1_OTG_H_BLANK                                                                            0x0e6b
++#define mmDSCL1_OTG_H_BLANK_BASE_IDX                                                                   2
++#define mmDSCL1_OTG_V_BLANK                                                                            0x0e6c
++#define mmDSCL1_OTG_V_BLANK_BASE_IDX                                                                   2
++#define mmDSCL1_RECOUT_START                                                                           0x0e6d
++#define mmDSCL1_RECOUT_START_BASE_IDX                                                                  2
++#define mmDSCL1_RECOUT_SIZE                                                                            0x0e6e
++#define mmDSCL1_RECOUT_SIZE_BASE_IDX                                                                   2
++#define mmDSCL1_MPC_SIZE                                                                               0x0e6f
++#define mmDSCL1_MPC_SIZE_BASE_IDX                                                                      2
++#define mmDSCL1_LB_DATA_FORMAT                                                                         0x0e70
++#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX                                                                2
++#define mmDSCL1_LB_MEMORY_CTRL                                                                         0x0e71
++#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX                                                                2
++#define mmDSCL1_LB_V_COUNTER                                                                           0x0e72
++#define mmDSCL1_LB_V_COUNTER_BASE_IDX                                                                  2
++#define mmDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e73
++#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
++#define mmDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e74
++#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
++#define mmDSCL1_OBUF_CONTROL                                                                           0x0e75
++#define mmDSCL1_OBUF_CONTROL_BASE_IDX                                                                  2
++#define mmDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e76
++#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
++// base address: 0x5ac
++#define mmCM1_CM_CONTROL                                                                               0x0e85
++#define mmCM1_CM_CONTROL_BASE_IDX                                                                      2
++#define mmCM1_CM_ICSC_CONTROL                                                                          0x0e86
++#define mmCM1_CM_ICSC_CONTROL_BASE_IDX                                                                 2
++#define mmCM1_CM_ICSC_C11_C12                                                                          0x0e87
++#define mmCM1_CM_ICSC_C11_C12_BASE_IDX                                                                 2
++#define mmCM1_CM_ICSC_C13_C14                                                                          0x0e88
++#define mmCM1_CM_ICSC_C13_C14_BASE_IDX                                                                 2
++#define mmCM1_CM_ICSC_C21_C22                                                                          0x0e89
++#define mmCM1_CM_ICSC_C21_C22_BASE_IDX                                                                 2
++#define mmCM1_CM_ICSC_C23_C24                                                                          0x0e8a
++#define mmCM1_CM_ICSC_C23_C24_BASE_IDX                                                                 2
++#define mmCM1_CM_ICSC_C31_C32                                                                          0x0e8b
++#define mmCM1_CM_ICSC_C31_C32_BASE_IDX                                                                 2
++#define mmCM1_CM_ICSC_C33_C34                                                                          0x0e8c
++#define mmCM1_CM_ICSC_C33_C34_BASE_IDX                                                                 2
++#define mmCM1_CM_ICSC_B_C11_C12                                                                        0x0e8d
++#define mmCM1_CM_ICSC_B_C11_C12_BASE_IDX                                                               2
++#define mmCM1_CM_ICSC_B_C13_C14                                                                        0x0e8e
++#define mmCM1_CM_ICSC_B_C13_C14_BASE_IDX                                                               2
++#define mmCM1_CM_ICSC_B_C21_C22                                                                        0x0e8f
++#define mmCM1_CM_ICSC_B_C21_C22_BASE_IDX                                                               2
++#define mmCM1_CM_ICSC_B_C23_C24                                                                        0x0e90
++#define mmCM1_CM_ICSC_B_C23_C24_BASE_IDX                                                               2
++#define mmCM1_CM_ICSC_B_C31_C32                                                                        0x0e91
++#define mmCM1_CM_ICSC_B_C31_C32_BASE_IDX                                                               2
++#define mmCM1_CM_ICSC_B_C33_C34                                                                        0x0e92
++#define mmCM1_CM_ICSC_B_C33_C34_BASE_IDX                                                               2
++#define mmCM1_CM_GAMUT_REMAP_CONTROL                                                                   0x0e93
++#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
++#define mmCM1_CM_GAMUT_REMAP_C11_C12                                                                   0x0e94
++#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
++#define mmCM1_CM_GAMUT_REMAP_C13_C14                                                                   0x0e95
++#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
++#define mmCM1_CM_GAMUT_REMAP_C21_C22                                                                   0x0e96
++#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
++#define mmCM1_CM_GAMUT_REMAP_C23_C24                                                                   0x0e97
++#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
++#define mmCM1_CM_GAMUT_REMAP_C31_C32                                                                   0x0e98
++#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
++#define mmCM1_CM_GAMUT_REMAP_C33_C34                                                                   0x0e99
++#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
++#define mmCM1_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0e9a
++#define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
++#define mmCM1_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0e9b
++#define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
++#define mmCM1_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0e9c
++#define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
++#define mmCM1_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0e9d
++#define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
++#define mmCM1_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0e9e
++#define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
++#define mmCM1_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0e9f
++#define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
++#define mmCM1_CM_BIAS_CR_R                                                                             0x0ea0
++#define mmCM1_CM_BIAS_CR_R_BASE_IDX                                                                    2
++#define mmCM1_CM_BIAS_Y_G_CB_B                                                                         0x0ea1
++#define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
++#define mmCM1_CM_DGAM_CONTROL                                                                          0x0ea2
++#define mmCM1_CM_DGAM_CONTROL_BASE_IDX                                                                 2
++#define mmCM1_CM_DGAM_LUT_INDEX                                                                        0x0ea3
++#define mmCM1_CM_DGAM_LUT_INDEX_BASE_IDX                                                               2
++#define mmCM1_CM_DGAM_LUT_DATA                                                                         0x0ea4
++#define mmCM1_CM_DGAM_LUT_DATA_BASE_IDX                                                                2
++#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK                                                                0x0ea5
++#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                       2
++#define mmCM1_CM_DGAM_RAMA_START_CNTL_B                                                                0x0ea6
++#define mmCM1_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX                                                       2
++#define mmCM1_CM_DGAM_RAMA_START_CNTL_G                                                                0x0ea7
++#define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX                                                       2
++#define mmCM1_CM_DGAM_RAMA_START_CNTL_R                                                                0x0ea8
++#define mmCM1_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX                                                       2
++#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B                                                                0x0ea9
++#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                       2
++#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G                                                                0x0eaa
++#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                       2
++#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R                                                                0x0eab
++#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                       2
++#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x0eac
++#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX                                                        2
++#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B                                                                 0x0ead
++#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX                                                        2
++#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x0eae
++#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        2
++#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G                                                                 0x0eaf
++#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX                                                        2
++#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x0eb0
++#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX                                                        2
++#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R                                                                 0x0eb1
++#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX                                                        2
++#define mmCM1_CM_DGAM_RAMA_REGION_0_1                                                                  0x0eb2
++#define mmCM1_CM_DGAM_RAMA_REGION_0_1_BASE_IDX                                                         2
++#define mmCM1_CM_DGAM_RAMA_REGION_2_3                                                                  0x0eb3
++#define mmCM1_CM_DGAM_RAMA_REGION_2_3_BASE_IDX                                                         2
++#define mmCM1_CM_DGAM_RAMA_REGION_4_5                                                                  0x0eb4
++#define mmCM1_CM_DGAM_RAMA_REGION_4_5_BASE_IDX                                                         2
++#define mmCM1_CM_DGAM_RAMA_REGION_6_7                                                                  0x0eb5
++#define mmCM1_CM_DGAM_RAMA_REGION_6_7_BASE_IDX                                                         2
++#define mmCM1_CM_DGAM_RAMA_REGION_8_9                                                                  0x0eb6
++#define mmCM1_CM_DGAM_RAMA_REGION_8_9_BASE_IDX                                                         2
++#define mmCM1_CM_DGAM_RAMA_REGION_10_11                                                                0x0eb7
++#define mmCM1_CM_DGAM_RAMA_REGION_10_11_BASE_IDX                                                       2
++#define mmCM1_CM_DGAM_RAMA_REGION_12_13                                                                0x0eb8
++#define mmCM1_CM_DGAM_RAMA_REGION_12_13_BASE_IDX                                                       2
++#define mmCM1_CM_DGAM_RAMA_REGION_14_15                                                                0x0eb9
++#define mmCM1_CM_DGAM_RAMA_REGION_14_15_BASE_IDX                                                       2
++#define mmCM1_CM_DGAM_RAMB_START_CNTL_B                                                                0x0eba
++#define mmCM1_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX                                                       2
++#define mmCM1_CM_DGAM_RAMB_START_CNTL_G                                                                0x0ebb
++#define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX                                                       2
++#define mmCM1_CM_DGAM_RAMB_START_CNTL_R                                                                0x0ebc
++#define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX                                                       2
++#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B                                                                0x0ebd
++#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                       2
++#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G                                                                0x0ebe
++#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                       2
++#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R                                                                0x0ebf
++#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                       2
++#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B                                                                 0x0ec0
++#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX                                                        2
++#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B                                                                 0x0ec1
++#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX                                                        2
++#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G                                                                 0x0ec2
++#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX                                                        2
++#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G                                                                 0x0ec3
++#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX                                                        2
++#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R                                                                 0x0ec4
++#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX                                                        2
++#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R                                                                 0x0ec5
++#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX                                                        2
++#define mmCM1_CM_DGAM_RAMB_REGION_0_1                                                                  0x0ec6
++#define mmCM1_CM_DGAM_RAMB_REGION_0_1_BASE_IDX                                                         2
++#define mmCM1_CM_DGAM_RAMB_REGION_2_3                                                                  0x0ec7
++#define mmCM1_CM_DGAM_RAMB_REGION_2_3_BASE_IDX                                                         2
++#define mmCM1_CM_DGAM_RAMB_REGION_4_5                                                                  0x0ec8
++#define mmCM1_CM_DGAM_RAMB_REGION_4_5_BASE_IDX                                                         2
++#define mmCM1_CM_DGAM_RAMB_REGION_6_7                                                                  0x0ec9
++#define mmCM1_CM_DGAM_RAMB_REGION_6_7_BASE_IDX                                                         2
++#define mmCM1_CM_DGAM_RAMB_REGION_8_9                                                                  0x0eca
++#define mmCM1_CM_DGAM_RAMB_REGION_8_9_BASE_IDX                                                         2
++#define mmCM1_CM_DGAM_RAMB_REGION_10_11                                                                0x0ecb
++#define mmCM1_CM_DGAM_RAMB_REGION_10_11_BASE_IDX                                                       2
++#define mmCM1_CM_DGAM_RAMB_REGION_12_13                                                                0x0ecc
++#define mmCM1_CM_DGAM_RAMB_REGION_12_13_BASE_IDX                                                       2
++#define mmCM1_CM_DGAM_RAMB_REGION_14_15                                                                0x0ecd
++#define mmCM1_CM_DGAM_RAMB_REGION_14_15_BASE_IDX                                                       2
++#define mmCM1_CM_BLNDGAM_CONTROL                                                                       0x0ece
++#define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
++#define mmCM1_CM_BLNDGAM_LUT_INDEX                                                                     0x0ecf
++#define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
++#define mmCM1_CM_BLNDGAM_LUT_DATA                                                                      0x0ed0
++#define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
++#define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK                                                             0x0ed1
++#define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x0ed2
++#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0ed3
++#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x0ed4
++#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B                                                             0x0ed5
++#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G                                                             0x0ed6
++#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R                                                             0x0ed7
++#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0ed8
++#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
++#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x0ed9
++#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
++#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0eda
++#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
++#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x0edb
++#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
++#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0edc
++#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
++#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0edd
++#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x0ede
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x0edf
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x0ee0
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x0ee1
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x0ee2
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x0ee3
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x0ee4
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x0ee5
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x0ee6
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x0ee7
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x0ee8
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x0ee9
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x0eea
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x0eeb
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x0eec
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x0eed
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x0eee
++#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x0eef
++#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x0ef0
++#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x0ef1
++#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B                                                             0x0ef2
++#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G                                                             0x0ef3
++#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R                                                             0x0ef4
++#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x0ef5
++#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
++#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x0ef6
++#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
++#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x0ef7
++#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
++#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x0ef8
++#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
++#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x0ef9
++#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
++#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x0efa
++#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x0efb
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x0efc
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x0efd
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x0efe
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x0eff
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x0f00
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x0f01
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x0f02
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x0f03
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x0f04
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x0f05
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x0f06
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x0f07
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x0f08
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x0f09
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x0f0a
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x0f0b
++#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
++#define mmCM1_CM_HDR_MULT_COEF                                                                         0x0f0c
++#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX                                                                2
++#define mmCM1_CM_MEM_PWR_CTRL                                                                          0x0f0d
++#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
++#define mmCM1_CM_MEM_PWR_STATUS                                                                        0x0f0e
++#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
++#define mmCM1_CM_DEALPHA                                                                               0x0f10
++#define mmCM1_CM_DEALPHA_BASE_IDX                                                                      2
++#define mmCM1_CM_COEF_FORMAT                                                                           0x0f11
++#define mmCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2
++#define mmCM1_CM_SHAPER_CONTROL                                                                        0x0f12
++#define mmCM1_CM_SHAPER_CONTROL_BASE_IDX                                                               2
++#define mmCM1_CM_SHAPER_OFFSET_R                                                                       0x0f13
++#define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
++#define mmCM1_CM_SHAPER_OFFSET_G                                                                       0x0f14
++#define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
++#define mmCM1_CM_SHAPER_OFFSET_B                                                                       0x0f15
++#define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
++#define mmCM1_CM_SHAPER_SCALE_R                                                                        0x0f16
++#define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
++#define mmCM1_CM_SHAPER_SCALE_G_B                                                                      0x0f17
++#define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
++#define mmCM1_CM_SHAPER_LUT_INDEX                                                                      0x0f18
++#define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
++#define mmCM1_CM_SHAPER_LUT_DATA                                                                       0x0f19
++#define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
++#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x0f1a
++#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B                                                              0x0f1b
++#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G                                                              0x0f1c
++#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R                                                              0x0f1d
++#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B                                                                0x0f1e
++#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
++#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G                                                                0x0f1f
++#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
++#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R                                                                0x0f20
++#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
++#define mmCM1_CM_SHAPER_RAMA_REGION_0_1                                                                0x0f21
++#define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
++#define mmCM1_CM_SHAPER_RAMA_REGION_2_3                                                                0x0f22
++#define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
++#define mmCM1_CM_SHAPER_RAMA_REGION_4_5                                                                0x0f23
++#define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
++#define mmCM1_CM_SHAPER_RAMA_REGION_6_7                                                                0x0f24
++#define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
++#define mmCM1_CM_SHAPER_RAMA_REGION_8_9                                                                0x0f25
++#define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
++#define mmCM1_CM_SHAPER_RAMA_REGION_10_11                                                              0x0f26
++#define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMA_REGION_12_13                                                              0x0f27
++#define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMA_REGION_14_15                                                              0x0f28
++#define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMA_REGION_16_17                                                              0x0f29
++#define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMA_REGION_18_19                                                              0x0f2a
++#define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMA_REGION_20_21                                                              0x0f2b
++#define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMA_REGION_22_23                                                              0x0f2c
++#define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMA_REGION_24_25                                                              0x0f2d
++#define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMA_REGION_26_27                                                              0x0f2e
++#define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMA_REGION_28_29                                                              0x0f2f
++#define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMA_REGION_30_31                                                              0x0f30
++#define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMA_REGION_32_33                                                              0x0f31
++#define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B                                                              0x0f32
++#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G                                                              0x0f33
++#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R                                                              0x0f34
++#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B                                                                0x0f35
++#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
++#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G                                                                0x0f36
++#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
++#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R                                                                0x0f37
++#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
++#define mmCM1_CM_SHAPER_RAMB_REGION_0_1                                                                0x0f38
++#define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
++#define mmCM1_CM_SHAPER_RAMB_REGION_2_3                                                                0x0f39
++#define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
++#define mmCM1_CM_SHAPER_RAMB_REGION_4_5                                                                0x0f3a
++#define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
++#define mmCM1_CM_SHAPER_RAMB_REGION_6_7                                                                0x0f3b
++#define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
++#define mmCM1_CM_SHAPER_RAMB_REGION_8_9                                                                0x0f3c
++#define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
++#define mmCM1_CM_SHAPER_RAMB_REGION_10_11                                                              0x0f3d
++#define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMB_REGION_12_13                                                              0x0f3e
++#define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMB_REGION_14_15                                                              0x0f3f
++#define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMB_REGION_16_17                                                              0x0f40
++#define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMB_REGION_18_19                                                              0x0f41
++#define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMB_REGION_20_21                                                              0x0f42
++#define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMB_REGION_22_23                                                              0x0f43
++#define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMB_REGION_24_25                                                              0x0f44
++#define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMB_REGION_26_27                                                              0x0f45
++#define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMB_REGION_28_29                                                              0x0f46
++#define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMB_REGION_30_31                                                              0x0f47
++#define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
++#define mmCM1_CM_SHAPER_RAMB_REGION_32_33                                                              0x0f48
++#define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
++#define mmCM1_CM_MEM_PWR_CTRL2                                                                         0x0f49
++#define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
++#define mmCM1_CM_MEM_PWR_STATUS2                                                                       0x0f4a
++#define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
++#define mmCM1_CM_3DLUT_MODE                                                                            0x0f4b
++#define mmCM1_CM_3DLUT_MODE_BASE_IDX                                                                   2
++#define mmCM1_CM_3DLUT_INDEX                                                                           0x0f4c
++#define mmCM1_CM_3DLUT_INDEX_BASE_IDX                                                                  2
++#define mmCM1_CM_3DLUT_DATA                                                                            0x0f4d
++#define mmCM1_CM_3DLUT_DATA_BASE_IDX                                                                   2
++#define mmCM1_CM_3DLUT_DATA_30BIT                                                                      0x0f4e
++#define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
++#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL                                                              0x0f4f
++#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
++#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x0f50
++#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
++#define mmCM1_CM_3DLUT_OUT_OFFSET_R                                                                    0x0f51
++#define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
++#define mmCM1_CM_3DLUT_OUT_OFFSET_G                                                                    0x0f52
++#define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
++#define mmCM1_CM_3DLUT_OUT_OFFSET_B                                                                    0x0f53
++#define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
++#define mmCM1_CM_TEST_DEBUG_INDEX                                                                      0x0f54
++#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
++#define mmCM1_CM_TEST_DEBUG_DATA                                                                       0x0f55
++#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
++
++
++// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
++// base address: 0x3e3c
++#define mmDC_PERFMON12_PERFCOUNTER_CNTL                                                                0x0f8f
++#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX                                                       2
++#define mmDC_PERFMON12_PERFCOUNTER_CNTL2                                                               0x0f90
++#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
++#define mmDC_PERFMON12_PERFCOUNTER_STATE                                                               0x0f91
++#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX                                                      2
++#define mmDC_PERFMON12_PERFMON_CNTL                                                                    0x0f92
++#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX                                                           2
++#define mmDC_PERFMON12_PERFMON_CNTL2                                                                   0x0f93
++#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX                                                          2
++#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC                                                         0x0f94
++#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
++#define mmDC_PERFMON12_PERFMON_CVALUE_LOW                                                              0x0f95
++#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
++#define mmDC_PERFMON12_PERFMON_HI                                                                      0x0f96
++#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX                                                             2
++#define mmDC_PERFMON12_PERFMON_LOW                                                                     0x0f97
++#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
++// base address: 0xb58
++#define mmDPP_TOP2_DPP_CONTROL                                                                         0x0f9b
++#define mmDPP_TOP2_DPP_CONTROL_BASE_IDX                                                                2
++#define mmDPP_TOP2_DPP_SOFT_RESET                                                                      0x0f9c
++#define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX                                                             2
++#define mmDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0f9d
++#define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
++#define mmDPP_TOP2_DPP_CRC_VAL_B_A                                                                     0x0f9e
++#define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
++#define mmDPP_TOP2_DPP_CRC_CTRL                                                                        0x0f9f
++#define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX                                                               2
++#define mmDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0
++#define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
++// base address: 0xb58
++#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0fa5
++#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
++#define mmCNVC_CFG2_FORMAT_CONTROL                                                                     0x0fa6
++#define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX                                                            2
++#define mmCNVC_CFG2_FCNV_FP_BIAS_R                                                                     0x0fa7
++#define mmCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX                                                            2
++#define mmCNVC_CFG2_FCNV_FP_BIAS_G                                                                     0x0fa8
++#define mmCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX                                                            2
++#define mmCNVC_CFG2_FCNV_FP_BIAS_B                                                                     0x0fa9
++#define mmCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX                                                            2
++#define mmCNVC_CFG2_FCNV_FP_SCALE_R                                                                    0x0faa
++#define mmCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX                                                           2
++#define mmCNVC_CFG2_FCNV_FP_SCALE_G                                                                    0x0fab
++#define mmCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX                                                           2
++#define mmCNVC_CFG2_FCNV_FP_SCALE_B                                                                    0x0fac
++#define mmCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX                                                           2
++#define mmCNVC_CFG2_COLOR_KEYER_CONTROL                                                                0x0fad
++#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
++#define mmCNVC_CFG2_COLOR_KEYER_ALPHA                                                                  0x0fae
++#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
++#define mmCNVC_CFG2_COLOR_KEYER_RED                                                                    0x0faf
++#define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX                                                           2
++#define mmCNVC_CFG2_COLOR_KEYER_GREEN                                                                  0x0fb0
++#define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX                                                         2
++#define mmCNVC_CFG2_COLOR_KEYER_BLUE                                                                   0x0fb1
++#define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX                                                          2
++#define mmCNVC_CFG2_ALPHA_2BIT_LUT                                                                     0x0fb3
++#define mmCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
++// base address: 0xb58
++#define mmCNVC_CUR2_CURSOR0_CONTROL                                                                    0x0fb6
++#define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX                                                           2
++#define mmCNVC_CUR2_CURSOR0_COLOR0                                                                     0x0fb7
++#define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX                                                            2
++#define mmCNVC_CUR2_CURSOR0_COLOR1                                                                     0x0fb8
++#define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX                                                            2
++#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS                                                              0x0fb9
++#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
++
++
++// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
++// base address: 0xb58
++#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT                                                                0x0fc0
++#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
++#define mmDSCL2_SCL_COEF_RAM_TAP_DATA                                                                  0x0fc1
++#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
++#define mmDSCL2_SCL_MODE                                                                               0x0fc2
++#define mmDSCL2_SCL_MODE_BASE_IDX                                                                      2
++#define mmDSCL2_SCL_TAP_CONTROL                                                                        0x0fc3
++#define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX                                                               2
++#define mmDSCL2_DSCL_CONTROL                                                                           0x0fc4
++#define mmDSCL2_DSCL_CONTROL_BASE_IDX                                                                  2
++#define mmDSCL2_DSCL_2TAP_CONTROL                                                                      0x0fc5
++#define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
++#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0fc6
++#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
++#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0fc7
++#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
++#define mmDSCL2_SCL_HORZ_FILTER_INIT                                                                   0x0fc8
++#define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
++#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0fc9
++#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
++#define mmDSCL2_SCL_HORZ_FILTER_INIT_C                                                                 0x0fca
++#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
++#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0fcb
++#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
++#define mmDSCL2_SCL_VERT_FILTER_INIT                                                                   0x0fcc
++#define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
++#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT                                                               0x0fcd
++#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
++#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0fce
++#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
++#define mmDSCL2_SCL_VERT_FILTER_INIT_C                                                                 0x0fcf
++#define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
++#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0fd0
++#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
++#define mmDSCL2_SCL_BLACK_OFFSET                                                                       0x0fd1
++#define mmDSCL2_SCL_BLACK_OFFSET_BASE_IDX                                                              2
++#define mmDSCL2_DSCL_UPDATE                                                                            0x0fd2
++#define mmDSCL2_DSCL_UPDATE_BASE_IDX                                                                   2
++#define mmDSCL2_DSCL_AUTOCAL                                                                           0x0fd3
++#define mmDSCL2_DSCL_AUTOCAL_BASE_IDX                                                                  2
++#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0fd4
++#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
++#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0fd5
++#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
++#define mmDSCL2_OTG_H_BLANK                                                                            0x0fd6
++#define mmDSCL2_OTG_H_BLANK_BASE_IDX                                                                   2
++#define mmDSCL2_OTG_V_BLANK                                                                            0x0fd7
++#define mmDSCL2_OTG_V_BLANK_BASE_IDX                                                                   2
++#define mmDSCL2_RECOUT_START                                                                           0x0fd8
++#define mmDSCL2_RECOUT_START_BASE_IDX                                                                  2
++#define mmDSCL2_RECOUT_SIZE                                                                            0x0fd9
++#define mmDSCL2_RECOUT_SIZE_BASE_IDX                                                                   2
++#define mmDSCL2_MPC_SIZE                                                                               0x0fda
++#define mmDSCL2_MPC_SIZE_BASE_IDX                                                                      2
++#define mmDSCL2_LB_DATA_FORMAT                                                                         0x0fdb
++#define mmDSCL2_LB_DATA_FORMAT_BASE_IDX                                                                2
++#define mmDSCL2_LB_MEMORY_CTRL                                                                         0x0fdc
++#define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX                                                                2
++#define mmDSCL2_LB_V_COUNTER                                                                           0x0fdd
++#define mmDSCL2_LB_V_COUNTER_BASE_IDX                                                                  2
++#define mmDSCL2_DSCL_MEM_PWR_CTRL                                                                      0x0fde
++#define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
++#define mmDSCL2_DSCL_MEM_PWR_STATUS                                                                    0x0fdf
++#define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
++#define mmDSCL2_OBUF_CONTROL                                                                           0x0fe0
++#define mmDSCL2_OBUF_CONTROL_BASE_IDX                                                                  2
++#define mmDSCL2_OBUF_MEM_PWR_CTRL                                                                      0x0fe1
++#define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
++// base address: 0xb58
++#define mmCM2_CM_CONTROL                                                                               0x0ff0
++#define mmCM2_CM_CONTROL_BASE_IDX                                                                      2
++#define mmCM2_CM_ICSC_CONTROL                                                                          0x0ff1
++#define mmCM2_CM_ICSC_CONTROL_BASE_IDX                                                                 2
++#define mmCM2_CM_ICSC_C11_C12                                                                          0x0ff2
++#define mmCM2_CM_ICSC_C11_C12_BASE_IDX                                                                 2
++#define mmCM2_CM_ICSC_C13_C14                                                                          0x0ff3
++#define mmCM2_CM_ICSC_C13_C14_BASE_IDX                                                                 2
++#define mmCM2_CM_ICSC_C21_C22                                                                          0x0ff4
++#define mmCM2_CM_ICSC_C21_C22_BASE_IDX                                                                 2
++#define mmCM2_CM_ICSC_C23_C24                                                                          0x0ff5
++#define mmCM2_CM_ICSC_C23_C24_BASE_IDX                                                                 2
++#define mmCM2_CM_ICSC_C31_C32                                                                          0x0ff6
++#define mmCM2_CM_ICSC_C31_C32_BASE_IDX                                                                 2
++#define mmCM2_CM_ICSC_C33_C34                                                                          0x0ff7
++#define mmCM2_CM_ICSC_C33_C34_BASE_IDX                                                                 2
++#define mmCM2_CM_ICSC_B_C11_C12                                                                        0x0ff8
++#define mmCM2_CM_ICSC_B_C11_C12_BASE_IDX                                                               2
++#define mmCM2_CM_ICSC_B_C13_C14                                                                        0x0ff9
++#define mmCM2_CM_ICSC_B_C13_C14_BASE_IDX                                                               2
++#define mmCM2_CM_ICSC_B_C21_C22                                                                        0x0ffa
++#define mmCM2_CM_ICSC_B_C21_C22_BASE_IDX                                                               2
++#define mmCM2_CM_ICSC_B_C23_C24                                                                        0x0ffb
++#define mmCM2_CM_ICSC_B_C23_C24_BASE_IDX                                                               2
++#define mmCM2_CM_ICSC_B_C31_C32                                                                        0x0ffc
++#define mmCM2_CM_ICSC_B_C31_C32_BASE_IDX                                                               2
++#define mmCM2_CM_ICSC_B_C33_C34                                                                        0x0ffd
++#define mmCM2_CM_ICSC_B_C33_C34_BASE_IDX                                                               2
++#define mmCM2_CM_GAMUT_REMAP_CONTROL                                                                   0x0ffe
++#define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
++#define mmCM2_CM_GAMUT_REMAP_C11_C12                                                                   0x0fff
++#define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
++#define mmCM2_CM_GAMUT_REMAP_C13_C14                                                                   0x1000
++#define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
++#define mmCM2_CM_GAMUT_REMAP_C21_C22                                                                   0x1001
++#define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
++#define mmCM2_CM_GAMUT_REMAP_C23_C24                                                                   0x1002
++#define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
++#define mmCM2_CM_GAMUT_REMAP_C31_C32                                                                   0x1003
++#define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
++#define mmCM2_CM_GAMUT_REMAP_C33_C34                                                                   0x1004
++#define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
++#define mmCM2_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1005
++#define mmCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
++#define mmCM2_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1006
++#define mmCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
++#define mmCM2_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1007
++#define mmCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
++#define mmCM2_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1008
++#define mmCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
++#define mmCM2_CM_GAMUT_REMAP_B_C31_C32                                                                 0x1009
++#define mmCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
++#define mmCM2_CM_GAMUT_REMAP_B_C33_C34                                                                 0x100a
++#define mmCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
++#define mmCM2_CM_BIAS_CR_R                                                                             0x100b
++#define mmCM2_CM_BIAS_CR_R_BASE_IDX                                                                    2
++#define mmCM2_CM_BIAS_Y_G_CB_B                                                                         0x100c
++#define mmCM2_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
++#define mmCM2_CM_DGAM_CONTROL                                                                          0x100d
++#define mmCM2_CM_DGAM_CONTROL_BASE_IDX                                                                 2
++#define mmCM2_CM_DGAM_LUT_INDEX                                                                        0x100e
++#define mmCM2_CM_DGAM_LUT_INDEX_BASE_IDX                                                               2
++#define mmCM2_CM_DGAM_LUT_DATA                                                                         0x100f
++#define mmCM2_CM_DGAM_LUT_DATA_BASE_IDX                                                                2
++#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK                                                                0x1010
++#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                       2
++#define mmCM2_CM_DGAM_RAMA_START_CNTL_B                                                                0x1011
++#define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX                                                       2
++#define mmCM2_CM_DGAM_RAMA_START_CNTL_G                                                                0x1012
++#define mmCM2_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX                                                       2
++#define mmCM2_CM_DGAM_RAMA_START_CNTL_R                                                                0x1013
++#define mmCM2_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX                                                       2
++#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B                                                                0x1014
++#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                       2
++#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G                                                                0x1015
++#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                       2
++#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R                                                                0x1016
++#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                       2
++#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x1017
++#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX                                                        2
++#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B                                                                 0x1018
++#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX                                                        2
++#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x1019
++#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        2
++#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G                                                                 0x101a
++#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX                                                        2
++#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x101b
++#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX                                                        2
++#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R                                                                 0x101c
++#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX                                                        2
++#define mmCM2_CM_DGAM_RAMA_REGION_0_1                                                                  0x101d
++#define mmCM2_CM_DGAM_RAMA_REGION_0_1_BASE_IDX                                                         2
++#define mmCM2_CM_DGAM_RAMA_REGION_2_3                                                                  0x101e
++#define mmCM2_CM_DGAM_RAMA_REGION_2_3_BASE_IDX                                                         2
++#define mmCM2_CM_DGAM_RAMA_REGION_4_5                                                                  0x101f
++#define mmCM2_CM_DGAM_RAMA_REGION_4_5_BASE_IDX                                                         2
++#define mmCM2_CM_DGAM_RAMA_REGION_6_7                                                                  0x1020
++#define mmCM2_CM_DGAM_RAMA_REGION_6_7_BASE_IDX                                                         2
++#define mmCM2_CM_DGAM_RAMA_REGION_8_9                                                                  0x1021
++#define mmCM2_CM_DGAM_RAMA_REGION_8_9_BASE_IDX                                                         2
++#define mmCM2_CM_DGAM_RAMA_REGION_10_11                                                                0x1022
++#define mmCM2_CM_DGAM_RAMA_REGION_10_11_BASE_IDX                                                       2
++#define mmCM2_CM_DGAM_RAMA_REGION_12_13                                                                0x1023
++#define mmCM2_CM_DGAM_RAMA_REGION_12_13_BASE_IDX                                                       2
++#define mmCM2_CM_DGAM_RAMA_REGION_14_15                                                                0x1024
++#define mmCM2_CM_DGAM_RAMA_REGION_14_15_BASE_IDX                                                       2
++#define mmCM2_CM_DGAM_RAMB_START_CNTL_B                                                                0x1025
++#define mmCM2_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX                                                       2
++#define mmCM2_CM_DGAM_RAMB_START_CNTL_G                                                                0x1026
++#define mmCM2_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX                                                       2
++#define mmCM2_CM_DGAM_RAMB_START_CNTL_R                                                                0x1027
++#define mmCM2_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX                                                       2
++#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B                                                                0x1028
++#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                       2
++#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G                                                                0x1029
++#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                       2
++#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R                                                                0x102a
++#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                       2
++#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B                                                                 0x102b
++#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX                                                        2
++#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B                                                                 0x102c
++#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX                                                        2
++#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G                                                                 0x102d
++#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX                                                        2
++#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G                                                                 0x102e
++#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX                                                        2
++#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R                                                                 0x102f
++#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX                                                        2
++#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R                                                                 0x1030
++#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX                                                        2
++#define mmCM2_CM_DGAM_RAMB_REGION_0_1                                                                  0x1031
++#define mmCM2_CM_DGAM_RAMB_REGION_0_1_BASE_IDX                                                         2
++#define mmCM2_CM_DGAM_RAMB_REGION_2_3                                                                  0x1032
++#define mmCM2_CM_DGAM_RAMB_REGION_2_3_BASE_IDX                                                         2
++#define mmCM2_CM_DGAM_RAMB_REGION_4_5                                                                  0x1033
++#define mmCM2_CM_DGAM_RAMB_REGION_4_5_BASE_IDX                                                         2
++#define mmCM2_CM_DGAM_RAMB_REGION_6_7                                                                  0x1034
++#define mmCM2_CM_DGAM_RAMB_REGION_6_7_BASE_IDX                                                         2
++#define mmCM2_CM_DGAM_RAMB_REGION_8_9                                                                  0x1035
++#define mmCM2_CM_DGAM_RAMB_REGION_8_9_BASE_IDX                                                         2
++#define mmCM2_CM_DGAM_RAMB_REGION_10_11                                                                0x1036
++#define mmCM2_CM_DGAM_RAMB_REGION_10_11_BASE_IDX                                                       2
++#define mmCM2_CM_DGAM_RAMB_REGION_12_13                                                                0x1037
++#define mmCM2_CM_DGAM_RAMB_REGION_12_13_BASE_IDX                                                       2
++#define mmCM2_CM_DGAM_RAMB_REGION_14_15                                                                0x1038
++#define mmCM2_CM_DGAM_RAMB_REGION_14_15_BASE_IDX                                                       2
++#define mmCM2_CM_BLNDGAM_CONTROL                                                                       0x1039
++#define mmCM2_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
++#define mmCM2_CM_BLNDGAM_LUT_INDEX                                                                     0x103a
++#define mmCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
++#define mmCM2_CM_BLNDGAM_LUT_DATA                                                                      0x103b
++#define mmCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
++#define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK                                                             0x103c
++#define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x103d
++#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x103e
++#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x103f
++#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B                                                             0x1040
++#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G                                                             0x1041
++#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R                                                             0x1042
++#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x1043
++#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
++#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x1044
++#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
++#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x1045
++#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
++#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x1046
++#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
++#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x1047
++#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
++#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x1048
++#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x1049
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x104a
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x104b
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x104c
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x104d
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x104e
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x104f
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x1050
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x1051
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x1052
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x1053
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x1054
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x1055
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x1056
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x1057
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x1058
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x1059
++#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x105a
++#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x105b
++#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x105c
++#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B                                                             0x105d
++#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G                                                             0x105e
++#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R                                                             0x105f
++#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x1060
++#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
++#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x1061
++#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
++#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x1062
++#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
++#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x1063
++#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
++#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x1064
++#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
++#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x1065
++#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x1066
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x1067
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x1068
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x1069
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x106a
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x106b
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x106c
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x106d
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x106e
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x106f
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x1070
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x1071
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x1072
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x1073
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x1074
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x1075
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x1076
++#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
++#define mmCM2_CM_HDR_MULT_COEF                                                                         0x1077
++#define mmCM2_CM_HDR_MULT_COEF_BASE_IDX                                                                2
++#define mmCM2_CM_MEM_PWR_CTRL                                                                          0x1078
++#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
++#define mmCM2_CM_MEM_PWR_STATUS                                                                        0x1079
++#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
++#define mmCM2_CM_DEALPHA                                                                               0x107b
++#define mmCM2_CM_DEALPHA_BASE_IDX                                                                      2
++#define mmCM2_CM_COEF_FORMAT                                                                           0x107c
++#define mmCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2
++#define mmCM2_CM_SHAPER_CONTROL                                                                        0x107d
++#define mmCM2_CM_SHAPER_CONTROL_BASE_IDX                                                               2
++#define mmCM2_CM_SHAPER_OFFSET_R                                                                       0x107e
++#define mmCM2_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
++#define mmCM2_CM_SHAPER_OFFSET_G                                                                       0x107f
++#define mmCM2_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
++#define mmCM2_CM_SHAPER_OFFSET_B                                                                       0x1080
++#define mmCM2_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
++#define mmCM2_CM_SHAPER_SCALE_R                                                                        0x1081
++#define mmCM2_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
++#define mmCM2_CM_SHAPER_SCALE_G_B                                                                      0x1082
++#define mmCM2_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
++#define mmCM2_CM_SHAPER_LUT_INDEX                                                                      0x1083
++#define mmCM2_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
++#define mmCM2_CM_SHAPER_LUT_DATA                                                                       0x1084
++#define mmCM2_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
++#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x1085
++#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B                                                              0x1086
++#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G                                                              0x1087
++#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R                                                              0x1088
++#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B                                                                0x1089
++#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
++#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G                                                                0x108a
++#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
++#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R                                                                0x108b
++#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
++#define mmCM2_CM_SHAPER_RAMA_REGION_0_1                                                                0x108c
++#define mmCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
++#define mmCM2_CM_SHAPER_RAMA_REGION_2_3                                                                0x108d
++#define mmCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
++#define mmCM2_CM_SHAPER_RAMA_REGION_4_5                                                                0x108e
++#define mmCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
++#define mmCM2_CM_SHAPER_RAMA_REGION_6_7                                                                0x108f
++#define mmCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
++#define mmCM2_CM_SHAPER_RAMA_REGION_8_9                                                                0x1090
++#define mmCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
++#define mmCM2_CM_SHAPER_RAMA_REGION_10_11                                                              0x1091
++#define mmCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMA_REGION_12_13                                                              0x1092
++#define mmCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMA_REGION_14_15                                                              0x1093
++#define mmCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMA_REGION_16_17                                                              0x1094
++#define mmCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMA_REGION_18_19                                                              0x1095
++#define mmCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMA_REGION_20_21                                                              0x1096
++#define mmCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMA_REGION_22_23                                                              0x1097
++#define mmCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMA_REGION_24_25                                                              0x1098
++#define mmCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMA_REGION_26_27                                                              0x1099
++#define mmCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMA_REGION_28_29                                                              0x109a
++#define mmCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMA_REGION_30_31                                                              0x109b
++#define mmCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMA_REGION_32_33                                                              0x109c
++#define mmCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B                                                              0x109d
++#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G                                                              0x109e
++#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R                                                              0x109f
++#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B                                                                0x10a0
++#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
++#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G                                                                0x10a1
++#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
++#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R                                                                0x10a2
++#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
++#define mmCM2_CM_SHAPER_RAMB_REGION_0_1                                                                0x10a3
++#define mmCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
++#define mmCM2_CM_SHAPER_RAMB_REGION_2_3                                                                0x10a4
++#define mmCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
++#define mmCM2_CM_SHAPER_RAMB_REGION_4_5                                                                0x10a5
++#define mmCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
++#define mmCM2_CM_SHAPER_RAMB_REGION_6_7                                                                0x10a6
++#define mmCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
++#define mmCM2_CM_SHAPER_RAMB_REGION_8_9                                                                0x10a7
++#define mmCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
++#define mmCM2_CM_SHAPER_RAMB_REGION_10_11                                                              0x10a8
++#define mmCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMB_REGION_12_13                                                              0x10a9
++#define mmCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMB_REGION_14_15                                                              0x10aa
++#define mmCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMB_REGION_16_17                                                              0x10ab
++#define mmCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMB_REGION_18_19                                                              0x10ac
++#define mmCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMB_REGION_20_21                                                              0x10ad
++#define mmCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMB_REGION_22_23                                                              0x10ae
++#define mmCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMB_REGION_24_25                                                              0x10af
++#define mmCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMB_REGION_26_27                                                              0x10b0
++#define mmCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMB_REGION_28_29                                                              0x10b1
++#define mmCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMB_REGION_30_31                                                              0x10b2
++#define mmCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
++#define mmCM2_CM_SHAPER_RAMB_REGION_32_33                                                              0x10b3
++#define mmCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
++#define mmCM2_CM_MEM_PWR_CTRL2                                                                         0x10b4
++#define mmCM2_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
++#define mmCM2_CM_MEM_PWR_STATUS2                                                                       0x10b5
++#define mmCM2_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
++#define mmCM2_CM_3DLUT_MODE                                                                            0x10b6
++#define mmCM2_CM_3DLUT_MODE_BASE_IDX                                                                   2
++#define mmCM2_CM_3DLUT_INDEX                                                                           0x10b7
++#define mmCM2_CM_3DLUT_INDEX_BASE_IDX                                                                  2
++#define mmCM2_CM_3DLUT_DATA                                                                            0x10b8
++#define mmCM2_CM_3DLUT_DATA_BASE_IDX                                                                   2
++#define mmCM2_CM_3DLUT_DATA_30BIT                                                                      0x10b9
++#define mmCM2_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
++#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL                                                              0x10ba
++#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
++#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x10bb
++#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
++#define mmCM2_CM_3DLUT_OUT_OFFSET_R                                                                    0x10bc
++#define mmCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
++#define mmCM2_CM_3DLUT_OUT_OFFSET_G                                                                    0x10bd
++#define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
++#define mmCM2_CM_3DLUT_OUT_OFFSET_B                                                                    0x10be
++#define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
++#define mmCM2_CM_TEST_DEBUG_INDEX                                                                      0x10bf
++#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
++#define mmCM2_CM_TEST_DEBUG_DATA                                                                       0x10c0
++#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
++
++
++// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
++// base address: 0x43e8
++#define mmDC_PERFMON13_PERFCOUNTER_CNTL                                                                0x10fa
++#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX                                                       2
++#define mmDC_PERFMON13_PERFCOUNTER_CNTL2                                                               0x10fb
++#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
++#define mmDC_PERFMON13_PERFCOUNTER_STATE                                                               0x10fc
++#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX                                                      2
++#define mmDC_PERFMON13_PERFMON_CNTL                                                                    0x10fd
++#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX                                                           2
++#define mmDC_PERFMON13_PERFMON_CNTL2                                                                   0x10fe
++#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX                                                          2
++#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC                                                         0x10ff
++#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
++#define mmDC_PERFMON13_PERFMON_CVALUE_LOW                                                              0x1100
++#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
++#define mmDC_PERFMON13_PERFMON_HI                                                                      0x1101
++#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX                                                             2
++#define mmDC_PERFMON13_PERFMON_LOW                                                                     0x1102
++#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
++// base address: 0x1104
++#define mmDPP_TOP3_DPP_CONTROL                                                                         0x1106
++#define mmDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2
++#define mmDPP_TOP3_DPP_SOFT_RESET                                                                      0x1107
++#define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX                                                             2
++#define mmDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x1108
++#define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
++#define mmDPP_TOP3_DPP_CRC_VAL_B_A                                                                     0x1109
++#define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
++#define mmDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a
++#define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX                                                               2
++#define mmDPP_TOP3_HOST_READ_CONTROL                                                                   0x110b
++#define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
++// base address: 0x1104
++#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT                                                          0x1110
++#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
++#define mmCNVC_CFG3_FORMAT_CONTROL                                                                     0x1111
++#define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX                                                            2
++#define mmCNVC_CFG3_FCNV_FP_BIAS_R                                                                     0x1112
++#define mmCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX                                                            2
++#define mmCNVC_CFG3_FCNV_FP_BIAS_G                                                                     0x1113
++#define mmCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX                                                            2
++#define mmCNVC_CFG3_FCNV_FP_BIAS_B                                                                     0x1114
++#define mmCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX                                                            2
++#define mmCNVC_CFG3_FCNV_FP_SCALE_R                                                                    0x1115
++#define mmCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX                                                           2
++#define mmCNVC_CFG3_FCNV_FP_SCALE_G                                                                    0x1116
++#define mmCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX                                                           2
++#define mmCNVC_CFG3_FCNV_FP_SCALE_B                                                                    0x1117
++#define mmCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX                                                           2
++#define mmCNVC_CFG3_COLOR_KEYER_CONTROL                                                                0x1118
++#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
++#define mmCNVC_CFG3_COLOR_KEYER_ALPHA                                                                  0x1119
++#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
++#define mmCNVC_CFG3_COLOR_KEYER_RED                                                                    0x111a
++#define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX                                                           2
++#define mmCNVC_CFG3_COLOR_KEYER_GREEN                                                                  0x111b
++#define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX                                                         2
++#define mmCNVC_CFG3_COLOR_KEYER_BLUE                                                                   0x111c
++#define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX                                                          2
++#define mmCNVC_CFG3_ALPHA_2BIT_LUT                                                                     0x111e
++#define mmCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
++// base address: 0x1104
++#define mmCNVC_CUR3_CURSOR0_CONTROL                                                                    0x1121
++#define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX                                                           2
++#define mmCNVC_CUR3_CURSOR0_COLOR0                                                                     0x1122
++#define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX                                                            2
++#define mmCNVC_CUR3_CURSOR0_COLOR1                                                                     0x1123
++#define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX                                                            2
++#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS                                                              0x1124
++#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
++
++
++// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
++// base address: 0x1104
++#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT                                                                0x112b
++#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
++#define mmDSCL3_SCL_COEF_RAM_TAP_DATA                                                                  0x112c
++#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
++#define mmDSCL3_SCL_MODE                                                                               0x112d
++#define mmDSCL3_SCL_MODE_BASE_IDX                                                                      2
++#define mmDSCL3_SCL_TAP_CONTROL                                                                        0x112e
++#define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX                                                               2
++#define mmDSCL3_DSCL_CONTROL                                                                           0x112f
++#define mmDSCL3_DSCL_CONTROL_BASE_IDX                                                                  2
++#define mmDSCL3_DSCL_2TAP_CONTROL                                                                      0x1130
++#define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
++#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL                                                           0x1131
++#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
++#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x1132
++#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
++#define mmDSCL3_SCL_HORZ_FILTER_INIT                                                                   0x1133
++#define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
++#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x1134
++#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
++#define mmDSCL3_SCL_HORZ_FILTER_INIT_C                                                                 0x1135
++#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
++#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO                                                            0x1136
++#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
++#define mmDSCL3_SCL_VERT_FILTER_INIT                                                                   0x1137
++#define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
++#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT                                                               0x1138
++#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
++#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x1139
++#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
++#define mmDSCL3_SCL_VERT_FILTER_INIT_C                                                                 0x113a
++#define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
++#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C                                                             0x113b
++#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
++#define mmDSCL3_SCL_BLACK_OFFSET                                                                       0x113c
++#define mmDSCL3_SCL_BLACK_OFFSET_BASE_IDX                                                              2
++#define mmDSCL3_DSCL_UPDATE                                                                            0x113d
++#define mmDSCL3_DSCL_UPDATE_BASE_IDX                                                                   2
++#define mmDSCL3_DSCL_AUTOCAL                                                                           0x113e
++#define mmDSCL3_DSCL_AUTOCAL_BASE_IDX                                                                  2
++#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x113f
++#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
++#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x1140
++#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
++#define mmDSCL3_OTG_H_BLANK                                                                            0x1141
++#define mmDSCL3_OTG_H_BLANK_BASE_IDX                                                                   2
++#define mmDSCL3_OTG_V_BLANK                                                                            0x1142
++#define mmDSCL3_OTG_V_BLANK_BASE_IDX                                                                   2
++#define mmDSCL3_RECOUT_START                                                                           0x1143
++#define mmDSCL3_RECOUT_START_BASE_IDX                                                                  2
++#define mmDSCL3_RECOUT_SIZE                                                                            0x1144
++#define mmDSCL3_RECOUT_SIZE_BASE_IDX                                                                   2
++#define mmDSCL3_MPC_SIZE                                                                               0x1145
++#define mmDSCL3_MPC_SIZE_BASE_IDX                                                                      2
++#define mmDSCL3_LB_DATA_FORMAT                                                                         0x1146
++#define mmDSCL3_LB_DATA_FORMAT_BASE_IDX                                                                2
++#define mmDSCL3_LB_MEMORY_CTRL                                                                         0x1147
++#define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX                                                                2
++#define mmDSCL3_LB_V_COUNTER                                                                           0x1148
++#define mmDSCL3_LB_V_COUNTER_BASE_IDX                                                                  2
++#define mmDSCL3_DSCL_MEM_PWR_CTRL                                                                      0x1149
++#define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
++#define mmDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x114a
++#define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
++#define mmDSCL3_OBUF_CONTROL                                                                           0x114b
++#define mmDSCL3_OBUF_CONTROL_BASE_IDX                                                                  2
++#define mmDSCL3_OBUF_MEM_PWR_CTRL                                                                      0x114c
++#define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
++// base address: 0x1104
++#define mmCM3_CM_CONTROL                                                                               0x115b
++#define mmCM3_CM_CONTROL_BASE_IDX                                                                      2
++#define mmCM3_CM_ICSC_CONTROL                                                                          0x115c
++#define mmCM3_CM_ICSC_CONTROL_BASE_IDX                                                                 2
++#define mmCM3_CM_ICSC_C11_C12                                                                          0x115d
++#define mmCM3_CM_ICSC_C11_C12_BASE_IDX                                                                 2
++#define mmCM3_CM_ICSC_C13_C14                                                                          0x115e
++#define mmCM3_CM_ICSC_C13_C14_BASE_IDX                                                                 2
++#define mmCM3_CM_ICSC_C21_C22                                                                          0x115f
++#define mmCM3_CM_ICSC_C21_C22_BASE_IDX                                                                 2
++#define mmCM3_CM_ICSC_C23_C24                                                                          0x1160
++#define mmCM3_CM_ICSC_C23_C24_BASE_IDX                                                                 2
++#define mmCM3_CM_ICSC_C31_C32                                                                          0x1161
++#define mmCM3_CM_ICSC_C31_C32_BASE_IDX                                                                 2
++#define mmCM3_CM_ICSC_C33_C34                                                                          0x1162
++#define mmCM3_CM_ICSC_C33_C34_BASE_IDX                                                                 2
++#define mmCM3_CM_ICSC_B_C11_C12                                                                        0x1163
++#define mmCM3_CM_ICSC_B_C11_C12_BASE_IDX                                                               2
++#define mmCM3_CM_ICSC_B_C13_C14                                                                        0x1164
++#define mmCM3_CM_ICSC_B_C13_C14_BASE_IDX                                                               2
++#define mmCM3_CM_ICSC_B_C21_C22                                                                        0x1165
++#define mmCM3_CM_ICSC_B_C21_C22_BASE_IDX                                                               2
++#define mmCM3_CM_ICSC_B_C23_C24                                                                        0x1166
++#define mmCM3_CM_ICSC_B_C23_C24_BASE_IDX                                                               2
++#define mmCM3_CM_ICSC_B_C31_C32                                                                        0x1167
++#define mmCM3_CM_ICSC_B_C31_C32_BASE_IDX                                                               2
++#define mmCM3_CM_ICSC_B_C33_C34                                                                        0x1168
++#define mmCM3_CM_ICSC_B_C33_C34_BASE_IDX                                                               2
++#define mmCM3_CM_GAMUT_REMAP_CONTROL                                                                   0x1169
++#define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
++#define mmCM3_CM_GAMUT_REMAP_C11_C12                                                                   0x116a
++#define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
++#define mmCM3_CM_GAMUT_REMAP_C13_C14                                                                   0x116b
++#define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
++#define mmCM3_CM_GAMUT_REMAP_C21_C22                                                                   0x116c
++#define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
++#define mmCM3_CM_GAMUT_REMAP_C23_C24                                                                   0x116d
++#define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
++#define mmCM3_CM_GAMUT_REMAP_C31_C32                                                                   0x116e
++#define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
++#define mmCM3_CM_GAMUT_REMAP_C33_C34                                                                   0x116f
++#define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
++#define mmCM3_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1170
++#define mmCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
++#define mmCM3_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1171
++#define mmCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
++#define mmCM3_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1172
++#define mmCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
++#define mmCM3_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1173
++#define mmCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
++#define mmCM3_CM_GAMUT_REMAP_B_C31_C32                                                                 0x1174
++#define mmCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
++#define mmCM3_CM_GAMUT_REMAP_B_C33_C34                                                                 0x1175
++#define mmCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
++#define mmCM3_CM_BIAS_CR_R                                                                             0x1176
++#define mmCM3_CM_BIAS_CR_R_BASE_IDX                                                                    2
++#define mmCM3_CM_BIAS_Y_G_CB_B                                                                         0x1177
++#define mmCM3_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
++#define mmCM3_CM_DGAM_CONTROL                                                                          0x1178
++#define mmCM3_CM_DGAM_CONTROL_BASE_IDX                                                                 2
++#define mmCM3_CM_DGAM_LUT_INDEX                                                                        0x1179
++#define mmCM3_CM_DGAM_LUT_INDEX_BASE_IDX                                                               2
++#define mmCM3_CM_DGAM_LUT_DATA                                                                         0x117a
++#define mmCM3_CM_DGAM_LUT_DATA_BASE_IDX                                                                2
++#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK                                                                0x117b
++#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                       2
++#define mmCM3_CM_DGAM_RAMA_START_CNTL_B                                                                0x117c
++#define mmCM3_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX                                                       2
++#define mmCM3_CM_DGAM_RAMA_START_CNTL_G                                                                0x117d
++#define mmCM3_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX                                                       2
++#define mmCM3_CM_DGAM_RAMA_START_CNTL_R                                                                0x117e
++#define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX                                                       2
++#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B                                                                0x117f
++#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                       2
++#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G                                                                0x1180
++#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                       2
++#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R                                                                0x1181
++#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                       2
++#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x1182
++#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX                                                        2
++#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B                                                                 0x1183
++#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX                                                        2
++#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x1184
++#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        2
++#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G                                                                 0x1185
++#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX                                                        2
++#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x1186
++#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX                                                        2
++#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R                                                                 0x1187
++#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX                                                        2
++#define mmCM3_CM_DGAM_RAMA_REGION_0_1                                                                  0x1188
++#define mmCM3_CM_DGAM_RAMA_REGION_0_1_BASE_IDX                                                         2
++#define mmCM3_CM_DGAM_RAMA_REGION_2_3                                                                  0x1189
++#define mmCM3_CM_DGAM_RAMA_REGION_2_3_BASE_IDX                                                         2
++#define mmCM3_CM_DGAM_RAMA_REGION_4_5                                                                  0x118a
++#define mmCM3_CM_DGAM_RAMA_REGION_4_5_BASE_IDX                                                         2
++#define mmCM3_CM_DGAM_RAMA_REGION_6_7                                                                  0x118b
++#define mmCM3_CM_DGAM_RAMA_REGION_6_7_BASE_IDX                                                         2
++#define mmCM3_CM_DGAM_RAMA_REGION_8_9                                                                  0x118c
++#define mmCM3_CM_DGAM_RAMA_REGION_8_9_BASE_IDX                                                         2
++#define mmCM3_CM_DGAM_RAMA_REGION_10_11                                                                0x118d
++#define mmCM3_CM_DGAM_RAMA_REGION_10_11_BASE_IDX                                                       2
++#define mmCM3_CM_DGAM_RAMA_REGION_12_13                                                                0x118e
++#define mmCM3_CM_DGAM_RAMA_REGION_12_13_BASE_IDX                                                       2
++#define mmCM3_CM_DGAM_RAMA_REGION_14_15                                                                0x118f
++#define mmCM3_CM_DGAM_RAMA_REGION_14_15_BASE_IDX                                                       2
++#define mmCM3_CM_DGAM_RAMB_START_CNTL_B                                                                0x1190
++#define mmCM3_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX                                                       2
++#define mmCM3_CM_DGAM_RAMB_START_CNTL_G                                                                0x1191
++#define mmCM3_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX                                                       2
++#define mmCM3_CM_DGAM_RAMB_START_CNTL_R                                                                0x1192
++#define mmCM3_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX                                                       2
++#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B                                                                0x1193
++#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                       2
++#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G                                                                0x1194
++#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                       2
++#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R                                                                0x1195
++#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                       2
++#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B                                                                 0x1196
++#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX                                                        2
++#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B                                                                 0x1197
++#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX                                                        2
++#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G                                                                 0x1198
++#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX                                                        2
++#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G                                                                 0x1199
++#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX                                                        2
++#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R                                                                 0x119a
++#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX                                                        2
++#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R                                                                 0x119b
++#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX                                                        2
++#define mmCM3_CM_DGAM_RAMB_REGION_0_1                                                                  0x119c
++#define mmCM3_CM_DGAM_RAMB_REGION_0_1_BASE_IDX                                                         2
++#define mmCM3_CM_DGAM_RAMB_REGION_2_3                                                                  0x119d
++#define mmCM3_CM_DGAM_RAMB_REGION_2_3_BASE_IDX                                                         2
++#define mmCM3_CM_DGAM_RAMB_REGION_4_5                                                                  0x119e
++#define mmCM3_CM_DGAM_RAMB_REGION_4_5_BASE_IDX                                                         2
++#define mmCM3_CM_DGAM_RAMB_REGION_6_7                                                                  0x119f
++#define mmCM3_CM_DGAM_RAMB_REGION_6_7_BASE_IDX                                                         2
++#define mmCM3_CM_DGAM_RAMB_REGION_8_9                                                                  0x11a0
++#define mmCM3_CM_DGAM_RAMB_REGION_8_9_BASE_IDX                                                         2
++#define mmCM3_CM_DGAM_RAMB_REGION_10_11                                                                0x11a1
++#define mmCM3_CM_DGAM_RAMB_REGION_10_11_BASE_IDX                                                       2
++#define mmCM3_CM_DGAM_RAMB_REGION_12_13                                                                0x11a2
++#define mmCM3_CM_DGAM_RAMB_REGION_12_13_BASE_IDX                                                       2
++#define mmCM3_CM_DGAM_RAMB_REGION_14_15                                                                0x11a3
++#define mmCM3_CM_DGAM_RAMB_REGION_14_15_BASE_IDX                                                       2
++#define mmCM3_CM_BLNDGAM_CONTROL                                                                       0x11a4
++#define mmCM3_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
++#define mmCM3_CM_BLNDGAM_LUT_INDEX                                                                     0x11a5
++#define mmCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
++#define mmCM3_CM_BLNDGAM_LUT_DATA                                                                      0x11a6
++#define mmCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
++#define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK                                                             0x11a7
++#define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x11a8
++#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x11a9
++#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x11aa
++#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B                                                             0x11ab
++#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G                                                             0x11ac
++#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R                                                             0x11ad
++#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x11ae
++#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
++#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x11af
++#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
++#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x11b0
++#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
++#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x11b1
++#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
++#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x11b2
++#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
++#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x11b3
++#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x11b4
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x11b5
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x11b6
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x11b7
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x11b8
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x11b9
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x11ba
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x11bb
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x11bc
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x11bd
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x11be
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x11bf
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x11c0
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x11c1
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x11c2
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x11c3
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x11c4
++#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x11c5
++#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x11c6
++#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x11c7
++#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B                                                             0x11c8
++#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G                                                             0x11c9
++#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R                                                             0x11ca
++#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x11cb
++#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
++#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x11cc
++#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
++#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x11cd
++#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
++#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x11ce
++#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
++#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x11cf
++#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
++#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x11d0
++#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x11d1
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x11d2
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x11d3
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x11d4
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x11d5
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x11d6
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x11d7
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x11d8
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x11d9
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x11da
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x11db
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x11dc
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x11dd
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x11de
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x11df
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x11e0
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x11e1
++#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
++#define mmCM3_CM_HDR_MULT_COEF                                                                         0x11e2
++#define mmCM3_CM_HDR_MULT_COEF_BASE_IDX                                                                2
++#define mmCM3_CM_MEM_PWR_CTRL                                                                          0x11e3
++#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
++#define mmCM3_CM_MEM_PWR_STATUS                                                                        0x11e4
++#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
++#define mmCM3_CM_DEALPHA                                                                               0x11e6
++#define mmCM3_CM_DEALPHA_BASE_IDX                                                                      2
++#define mmCM3_CM_COEF_FORMAT                                                                           0x11e7
++#define mmCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2
++#define mmCM3_CM_SHAPER_CONTROL                                                                        0x11e8
++#define mmCM3_CM_SHAPER_CONTROL_BASE_IDX                                                               2
++#define mmCM3_CM_SHAPER_OFFSET_R                                                                       0x11e9
++#define mmCM3_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
++#define mmCM3_CM_SHAPER_OFFSET_G                                                                       0x11ea
++#define mmCM3_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
++#define mmCM3_CM_SHAPER_OFFSET_B                                                                       0x11eb
++#define mmCM3_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
++#define mmCM3_CM_SHAPER_SCALE_R                                                                        0x11ec
++#define mmCM3_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
++#define mmCM3_CM_SHAPER_SCALE_G_B                                                                      0x11ed
++#define mmCM3_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
++#define mmCM3_CM_SHAPER_LUT_INDEX                                                                      0x11ee
++#define mmCM3_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
++#define mmCM3_CM_SHAPER_LUT_DATA                                                                       0x11ef
++#define mmCM3_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
++#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x11f0
++#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B                                                              0x11f1
++#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G                                                              0x11f2
++#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R                                                              0x11f3
++#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B                                                                0x11f4
++#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
++#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G                                                                0x11f5
++#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
++#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R                                                                0x11f6
++#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
++#define mmCM3_CM_SHAPER_RAMA_REGION_0_1                                                                0x11f7
++#define mmCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
++#define mmCM3_CM_SHAPER_RAMA_REGION_2_3                                                                0x11f8
++#define mmCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
++#define mmCM3_CM_SHAPER_RAMA_REGION_4_5                                                                0x11f9
++#define mmCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
++#define mmCM3_CM_SHAPER_RAMA_REGION_6_7                                                                0x11fa
++#define mmCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
++#define mmCM3_CM_SHAPER_RAMA_REGION_8_9                                                                0x11fb
++#define mmCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
++#define mmCM3_CM_SHAPER_RAMA_REGION_10_11                                                              0x11fc
++#define mmCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMA_REGION_12_13                                                              0x11fd
++#define mmCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMA_REGION_14_15                                                              0x11fe
++#define mmCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMA_REGION_16_17                                                              0x11ff
++#define mmCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMA_REGION_18_19                                                              0x1200
++#define mmCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMA_REGION_20_21                                                              0x1201
++#define mmCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMA_REGION_22_23                                                              0x1202
++#define mmCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMA_REGION_24_25                                                              0x1203
++#define mmCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMA_REGION_26_27                                                              0x1204
++#define mmCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMA_REGION_28_29                                                              0x1205
++#define mmCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMA_REGION_30_31                                                              0x1206
++#define mmCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMA_REGION_32_33                                                              0x1207
++#define mmCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B                                                              0x1208
++#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G                                                              0x1209
++#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R                                                              0x120a
++#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B                                                                0x120b
++#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
++#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G                                                                0x120c
++#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
++#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R                                                                0x120d
++#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
++#define mmCM3_CM_SHAPER_RAMB_REGION_0_1                                                                0x120e
++#define mmCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
++#define mmCM3_CM_SHAPER_RAMB_REGION_2_3                                                                0x120f
++#define mmCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
++#define mmCM3_CM_SHAPER_RAMB_REGION_4_5                                                                0x1210
++#define mmCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
++#define mmCM3_CM_SHAPER_RAMB_REGION_6_7                                                                0x1211
++#define mmCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
++#define mmCM3_CM_SHAPER_RAMB_REGION_8_9                                                                0x1212
++#define mmCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
++#define mmCM3_CM_SHAPER_RAMB_REGION_10_11                                                              0x1213
++#define mmCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMB_REGION_12_13                                                              0x1214
++#define mmCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMB_REGION_14_15                                                              0x1215
++#define mmCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMB_REGION_16_17                                                              0x1216
++#define mmCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMB_REGION_18_19                                                              0x1217
++#define mmCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMB_REGION_20_21                                                              0x1218
++#define mmCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMB_REGION_22_23                                                              0x1219
++#define mmCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMB_REGION_24_25                                                              0x121a
++#define mmCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMB_REGION_26_27                                                              0x121b
++#define mmCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMB_REGION_28_29                                                              0x121c
++#define mmCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMB_REGION_30_31                                                              0x121d
++#define mmCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
++#define mmCM3_CM_SHAPER_RAMB_REGION_32_33                                                              0x121e
++#define mmCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
++#define mmCM3_CM_MEM_PWR_CTRL2                                                                         0x121f
++#define mmCM3_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
++#define mmCM3_CM_MEM_PWR_STATUS2                                                                       0x1220
++#define mmCM3_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
++#define mmCM3_CM_3DLUT_MODE                                                                            0x1221
++#define mmCM3_CM_3DLUT_MODE_BASE_IDX                                                                   2
++#define mmCM3_CM_3DLUT_INDEX                                                                           0x1222
++#define mmCM3_CM_3DLUT_INDEX_BASE_IDX                                                                  2
++#define mmCM3_CM_3DLUT_DATA                                                                            0x1223
++#define mmCM3_CM_3DLUT_DATA_BASE_IDX                                                                   2
++#define mmCM3_CM_3DLUT_DATA_30BIT                                                                      0x1224
++#define mmCM3_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
++#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL                                                              0x1225
++#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
++#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x1226
++#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
++#define mmCM3_CM_3DLUT_OUT_OFFSET_R                                                                    0x1227
++#define mmCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
++#define mmCM3_CM_3DLUT_OUT_OFFSET_G                                                                    0x1228
++#define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
++#define mmCM3_CM_3DLUT_OUT_OFFSET_B                                                                    0x1229
++#define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
++#define mmCM3_CM_TEST_DEBUG_INDEX                                                                      0x122a
++#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
++#define mmCM3_CM_TEST_DEBUG_DATA                                                                       0x122b
++#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
++
++
++// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
++// base address: 0x4994
++#define mmDC_PERFMON14_PERFCOUNTER_CNTL                                                                0x1265
++#define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX                                                       2
++#define mmDC_PERFMON14_PERFCOUNTER_CNTL2                                                               0x1266
++#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
++#define mmDC_PERFMON14_PERFCOUNTER_STATE                                                               0x1267
++#define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX                                                      2
++#define mmDC_PERFMON14_PERFMON_CNTL                                                                    0x1268
++#define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX                                                           2
++#define mmDC_PERFMON14_PERFMON_CNTL2                                                                   0x1269
++#define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX                                                          2
++#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC                                                         0x126a
++#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
++#define mmDC_PERFMON14_PERFMON_CVALUE_LOW                                                              0x126b
++#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
++#define mmDC_PERFMON14_PERFMON_HI                                                                      0x126c
++#define mmDC_PERFMON14_PERFMON_HI_BASE_IDX                                                             2
++#define mmDC_PERFMON14_PERFMON_LOW                                                                     0x126d
++#define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_mpc_mpcc0_dispdec
++// base address: 0x0
++#define mmMPCC0_MPCC_TOP_SEL                                                                           0x1271
++#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX                                                                  2
++#define mmMPCC0_MPCC_BOT_SEL                                                                           0x1272
++#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX                                                                  2
++#define mmMPCC0_MPCC_OPP_ID                                                                            0x1273
++#define mmMPCC0_MPCC_OPP_ID_BASE_IDX                                                                   2
++#define mmMPCC0_MPCC_CONTROL                                                                           0x1274
++#define mmMPCC0_MPCC_CONTROL_BASE_IDX                                                                  2
++#define mmMPCC0_MPCC_SM_CONTROL                                                                        0x1275
++#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               2
++#define mmMPCC0_MPCC_UPDATE_LOCK_SEL                                                                   0x1276
++#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
++#define mmMPCC0_MPCC_TOP_GAIN                                                                          0x1277
++#define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX                                                                 2
++#define mmMPCC0_MPCC_BOT_GAIN_INSIDE                                                                   0x1278
++#define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
++#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE                                                                  0x1279
++#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
++#define mmMPCC0_MPCC_BG_R_CR                                                                           0x127a
++#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX                                                                  2
++#define mmMPCC0_MPCC_BG_G_Y                                                                            0x127b
++#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX                                                                   2
++#define mmMPCC0_MPCC_BG_B_CB                                                                           0x127c
++#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX                                                                  2
++#define mmMPCC0_MPCC_MEM_PWR_CTRL                                                                      0x127d
++#define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
++#define mmMPCC0_MPCC_STALL_STATUS                                                                      0x127e
++#define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX                                                             2
++#define mmMPCC0_MPCC_STATUS                                                                            0x127f
++#define mmMPCC0_MPCC_STATUS_BASE_IDX                                                                   2
++
++
++// addressBlock: dce_dc_mpc_mpcc1_dispdec
++// base address: 0x6c
++#define mmMPCC1_MPCC_TOP_SEL                                                                           0x128c
++#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX                                                                  2
++#define mmMPCC1_MPCC_BOT_SEL                                                                           0x128d
++#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX                                                                  2
++#define mmMPCC1_MPCC_OPP_ID                                                                            0x128e
++#define mmMPCC1_MPCC_OPP_ID_BASE_IDX                                                                   2
++#define mmMPCC1_MPCC_CONTROL                                                                           0x128f
++#define mmMPCC1_MPCC_CONTROL_BASE_IDX                                                                  2
++#define mmMPCC1_MPCC_SM_CONTROL                                                                        0x1290
++#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX                                                               2
++#define mmMPCC1_MPCC_UPDATE_LOCK_SEL                                                                   0x1291
++#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
++#define mmMPCC1_MPCC_TOP_GAIN                                                                          0x1292
++#define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX                                                                 2
++#define mmMPCC1_MPCC_BOT_GAIN_INSIDE                                                                   0x1293
++#define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
++#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE                                                                  0x1294
++#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
++#define mmMPCC1_MPCC_BG_R_CR                                                                           0x1295
++#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX                                                                  2
++#define mmMPCC1_MPCC_BG_G_Y                                                                            0x1296
++#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX                                                                   2
++#define mmMPCC1_MPCC_BG_B_CB                                                                           0x1297
++#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX                                                                  2
++#define mmMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x1298
++#define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
++#define mmMPCC1_MPCC_STALL_STATUS                                                                      0x1299
++#define mmMPCC1_MPCC_STALL_STATUS_BASE_IDX                                                             2
++#define mmMPCC1_MPCC_STATUS                                                                            0x129a
++#define mmMPCC1_MPCC_STATUS_BASE_IDX                                                                   2
++
++
++// addressBlock: dce_dc_mpc_mpcc2_dispdec
++// base address: 0xd8
++#define mmMPCC2_MPCC_TOP_SEL                                                                           0x12a7
++#define mmMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  2
++#define mmMPCC2_MPCC_BOT_SEL                                                                           0x12a8
++#define mmMPCC2_MPCC_BOT_SEL_BASE_IDX                                                                  2
++#define mmMPCC2_MPCC_OPP_ID                                                                            0x12a9
++#define mmMPCC2_MPCC_OPP_ID_BASE_IDX                                                                   2
++#define mmMPCC2_MPCC_CONTROL                                                                           0x12aa
++#define mmMPCC2_MPCC_CONTROL_BASE_IDX                                                                  2
++#define mmMPCC2_MPCC_SM_CONTROL                                                                        0x12ab
++#define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX                                                               2
++#define mmMPCC2_MPCC_UPDATE_LOCK_SEL                                                                   0x12ac
++#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
++#define mmMPCC2_MPCC_TOP_GAIN                                                                          0x12ad
++#define mmMPCC2_MPCC_TOP_GAIN_BASE_IDX                                                                 2
++#define mmMPCC2_MPCC_BOT_GAIN_INSIDE                                                                   0x12ae
++#define mmMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
++#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE                                                                  0x12af
++#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
++#define mmMPCC2_MPCC_BG_R_CR                                                                           0x12b0
++#define mmMPCC2_MPCC_BG_R_CR_BASE_IDX                                                                  2
++#define mmMPCC2_MPCC_BG_G_Y                                                                            0x12b1
++#define mmMPCC2_MPCC_BG_G_Y_BASE_IDX                                                                   2
++#define mmMPCC2_MPCC_BG_B_CB                                                                           0x12b2
++#define mmMPCC2_MPCC_BG_B_CB_BASE_IDX                                                                  2
++#define mmMPCC2_MPCC_MEM_PWR_CTRL                                                                      0x12b3
++#define mmMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
++#define mmMPCC2_MPCC_STALL_STATUS                                                                      0x12b4
++#define mmMPCC2_MPCC_STALL_STATUS_BASE_IDX                                                             2
++#define mmMPCC2_MPCC_STATUS                                                                            0x12b5
++#define mmMPCC2_MPCC_STATUS_BASE_IDX                                                                   2
++
++
++// addressBlock: dce_dc_mpc_mpcc3_dispdec
++// base address: 0x144
++#define mmMPCC3_MPCC_TOP_SEL                                                                           0x12c2
++#define mmMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  2
++#define mmMPCC3_MPCC_BOT_SEL                                                                           0x12c3
++#define mmMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  2
++#define mmMPCC3_MPCC_OPP_ID                                                                            0x12c4
++#define mmMPCC3_MPCC_OPP_ID_BASE_IDX                                                                   2
++#define mmMPCC3_MPCC_CONTROL                                                                           0x12c5
++#define mmMPCC3_MPCC_CONTROL_BASE_IDX                                                                  2
++#define mmMPCC3_MPCC_SM_CONTROL                                                                        0x12c6
++#define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX                                                               2
++#define mmMPCC3_MPCC_UPDATE_LOCK_SEL                                                                   0x12c7
++#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
++#define mmMPCC3_MPCC_TOP_GAIN                                                                          0x12c8
++#define mmMPCC3_MPCC_TOP_GAIN_BASE_IDX                                                                 2
++#define mmMPCC3_MPCC_BOT_GAIN_INSIDE                                                                   0x12c9
++#define mmMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
++#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE                                                                  0x12ca
++#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
++#define mmMPCC3_MPCC_BG_R_CR                                                                           0x12cb
++#define mmMPCC3_MPCC_BG_R_CR_BASE_IDX                                                                  2
++#define mmMPCC3_MPCC_BG_G_Y                                                                            0x12cc
++#define mmMPCC3_MPCC_BG_G_Y_BASE_IDX                                                                   2
++#define mmMPCC3_MPCC_BG_B_CB                                                                           0x12cd
++#define mmMPCC3_MPCC_BG_B_CB_BASE_IDX                                                                  2
++#define mmMPCC3_MPCC_MEM_PWR_CTRL                                                                      0x12ce
++#define mmMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
++#define mmMPCC3_MPCC_STALL_STATUS                                                                      0x12cf
++#define mmMPCC3_MPCC_STALL_STATUS_BASE_IDX                                                             2
++#define mmMPCC3_MPCC_STATUS                                                                            0x12d0
++#define mmMPCC3_MPCC_STATUS_BASE_IDX                                                                   2
++
++
++// addressBlock: dce_dc_mpc_mpcc4_dispdec
++// base address: 0x1b0
++#define mmMPCC4_MPCC_TOP_SEL                                                                           0x12dd
++#define mmMPCC4_MPCC_TOP_SEL_BASE_IDX                                                                  2
++#define mmMPCC4_MPCC_BOT_SEL                                                                           0x12de
++#define mmMPCC4_MPCC_BOT_SEL_BASE_IDX                                                                  2
++#define mmMPCC4_MPCC_OPP_ID                                                                            0x12df
++#define mmMPCC4_MPCC_OPP_ID_BASE_IDX                                                                   2
++#define mmMPCC4_MPCC_CONTROL                                                                           0x12e0
++#define mmMPCC4_MPCC_CONTROL_BASE_IDX                                                                  2
++#define mmMPCC4_MPCC_SM_CONTROL                                                                        0x12e1
++#define mmMPCC4_MPCC_SM_CONTROL_BASE_IDX                                                               2
++#define mmMPCC4_MPCC_UPDATE_LOCK_SEL                                                                   0x12e2
++#define mmMPCC4_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
++#define mmMPCC4_MPCC_TOP_GAIN                                                                          0x12e3
++#define mmMPCC4_MPCC_TOP_GAIN_BASE_IDX                                                                 2
++#define mmMPCC4_MPCC_BOT_GAIN_INSIDE                                                                   0x12e4
++#define mmMPCC4_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
++#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE                                                                  0x12e5
++#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
++#define mmMPCC4_MPCC_BG_R_CR                                                                           0x12e6
++#define mmMPCC4_MPCC_BG_R_CR_BASE_IDX                                                                  2
++#define mmMPCC4_MPCC_BG_G_Y                                                                            0x12e7
++#define mmMPCC4_MPCC_BG_G_Y_BASE_IDX                                                                   2
++#define mmMPCC4_MPCC_BG_B_CB                                                                           0x12e8
++#define mmMPCC4_MPCC_BG_B_CB_BASE_IDX                                                                  2
++#define mmMPCC4_MPCC_MEM_PWR_CTRL                                                                      0x12e9
++#define mmMPCC4_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
++#define mmMPCC4_MPCC_STALL_STATUS                                                                      0x12ea
++#define mmMPCC4_MPCC_STALL_STATUS_BASE_IDX                                                             2
++#define mmMPCC4_MPCC_STATUS                                                                            0x12eb
++#define mmMPCC4_MPCC_STATUS_BASE_IDX                                                                   2
++
++
++// addressBlock: dce_dc_mpc_mpcc5_dispdec
++// base address: 0x21c
++#define mmMPCC5_MPCC_TOP_SEL                                                                           0x12f8
++#define mmMPCC5_MPCC_TOP_SEL_BASE_IDX                                                                  2
++#define mmMPCC5_MPCC_BOT_SEL                                                                           0x12f9
++#define mmMPCC5_MPCC_BOT_SEL_BASE_IDX                                                                  2
++#define mmMPCC5_MPCC_OPP_ID                                                                            0x12fa
++#define mmMPCC5_MPCC_OPP_ID_BASE_IDX                                                                   2
++#define mmMPCC5_MPCC_CONTROL                                                                           0x12fb
++#define mmMPCC5_MPCC_CONTROL_BASE_IDX                                                                  2
++#define mmMPCC5_MPCC_SM_CONTROL                                                                        0x12fc
++#define mmMPCC5_MPCC_SM_CONTROL_BASE_IDX                                                               2
++#define mmMPCC5_MPCC_UPDATE_LOCK_SEL                                                                   0x12fd
++#define mmMPCC5_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
++#define mmMPCC5_MPCC_TOP_GAIN                                                                          0x12fe
++#define mmMPCC5_MPCC_TOP_GAIN_BASE_IDX                                                                 2
++#define mmMPCC5_MPCC_BOT_GAIN_INSIDE                                                                   0x12ff
++#define mmMPCC5_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
++#define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE                                                                  0x1300
++#define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
++#define mmMPCC5_MPCC_BG_R_CR                                                                           0x1301
++#define mmMPCC5_MPCC_BG_R_CR_BASE_IDX                                                                  2
++#define mmMPCC5_MPCC_BG_G_Y                                                                            0x1302
++#define mmMPCC5_MPCC_BG_G_Y_BASE_IDX                                                                   2
++#define mmMPCC5_MPCC_BG_B_CB                                                                           0x1303
++#define mmMPCC5_MPCC_BG_B_CB_BASE_IDX                                                                  2
++#define mmMPCC5_MPCC_MEM_PWR_CTRL                                                                      0x1304
++#define mmMPCC5_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
++#define mmMPCC5_MPCC_STALL_STATUS                                                                      0x1305
++#define mmMPCC5_MPCC_STALL_STATUS_BASE_IDX                                                             2
++#define mmMPCC5_MPCC_STATUS                                                                            0x1306
++#define mmMPCC5_MPCC_STATUS_BASE_IDX                                                                   2
++
++
++// addressBlock: dce_dc_mpc_mpcc6_dispdec
++// base address: 0x288
++#define mmMPCC6_MPCC_TOP_SEL                                                                           0x1313
++#define mmMPCC6_MPCC_TOP_SEL_BASE_IDX                                                                  2
++#define mmMPCC6_MPCC_BOT_SEL                                                                           0x1314
++#define mmMPCC6_MPCC_BOT_SEL_BASE_IDX                                                                  2
++#define mmMPCC6_MPCC_OPP_ID                                                                            0x1315
++#define mmMPCC6_MPCC_OPP_ID_BASE_IDX                                                                   2
++#define mmMPCC6_MPCC_CONTROL                                                                           0x1316
++#define mmMPCC6_MPCC_CONTROL_BASE_IDX                                                                  2
++#define mmMPCC6_MPCC_SM_CONTROL                                                                        0x1317
++#define mmMPCC6_MPCC_SM_CONTROL_BASE_IDX                                                               2
++#define mmMPCC6_MPCC_UPDATE_LOCK_SEL                                                                   0x1318
++#define mmMPCC6_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
++#define mmMPCC6_MPCC_TOP_GAIN                                                                          0x1319
++#define mmMPCC6_MPCC_TOP_GAIN_BASE_IDX                                                                 2
++#define mmMPCC6_MPCC_BOT_GAIN_INSIDE                                                                   0x131a
++#define mmMPCC6_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
++#define mmMPCC6_MPCC_BOT_GAIN_OUTSIDE                                                                  0x131b
++#define mmMPCC6_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
++#define mmMPCC6_MPCC_BG_R_CR                                                                           0x131c
++#define mmMPCC6_MPCC_BG_R_CR_BASE_IDX                                                                  2
++#define mmMPCC6_MPCC_BG_G_Y                                                                            0x131d
++#define mmMPCC6_MPCC_BG_G_Y_BASE_IDX                                                                   2
++#define mmMPCC6_MPCC_BG_B_CB                                                                           0x131e
++#define mmMPCC6_MPCC_BG_B_CB_BASE_IDX                                                                  2
++#define mmMPCC6_MPCC_MEM_PWR_CTRL                                                                      0x131f
++#define mmMPCC6_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
++#define mmMPCC6_MPCC_STALL_STATUS                                                                      0x1320
++#define mmMPCC6_MPCC_STALL_STATUS_BASE_IDX                                                             2
++#define mmMPCC6_MPCC_STATUS                                                                            0x1321
++#define mmMPCC6_MPCC_STATUS_BASE_IDX                                                                   2
++
++
++// addressBlock: dce_dc_mpc_mpcc7_dispdec
++// base address: 0x2f4
++#define mmMPCC7_MPCC_TOP_SEL                                                                           0x132e
++#define mmMPCC7_MPCC_TOP_SEL_BASE_IDX                                                                  2
++#define mmMPCC7_MPCC_BOT_SEL                                                                           0x132f
++#define mmMPCC7_MPCC_BOT_SEL_BASE_IDX                                                                  2
++#define mmMPCC7_MPCC_OPP_ID                                                                            0x1330
++#define mmMPCC7_MPCC_OPP_ID_BASE_IDX                                                                   2
++#define mmMPCC7_MPCC_CONTROL                                                                           0x1331
++#define mmMPCC7_MPCC_CONTROL_BASE_IDX                                                                  2
++#define mmMPCC7_MPCC_SM_CONTROL                                                                        0x1332
++#define mmMPCC7_MPCC_SM_CONTROL_BASE_IDX                                                               2
++#define mmMPCC7_MPCC_UPDATE_LOCK_SEL                                                                   0x1333
++#define mmMPCC7_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
++#define mmMPCC7_MPCC_TOP_GAIN                                                                          0x1334
++#define mmMPCC7_MPCC_TOP_GAIN_BASE_IDX                                                                 2
++#define mmMPCC7_MPCC_BOT_GAIN_INSIDE                                                                   0x1335
++#define mmMPCC7_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
++#define mmMPCC7_MPCC_BOT_GAIN_OUTSIDE                                                                  0x1336
++#define mmMPCC7_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
++#define mmMPCC7_MPCC_BG_R_CR                                                                           0x1337
++#define mmMPCC7_MPCC_BG_R_CR_BASE_IDX                                                                  2
++#define mmMPCC7_MPCC_BG_G_Y                                                                            0x1338
++#define mmMPCC7_MPCC_BG_G_Y_BASE_IDX                                                                   2
++#define mmMPCC7_MPCC_BG_B_CB                                                                           0x1339
++#define mmMPCC7_MPCC_BG_B_CB_BASE_IDX                                                                  2
++#define mmMPCC7_MPCC_MEM_PWR_CTRL                                                                      0x133a
++#define mmMPCC7_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
++#define mmMPCC7_MPCC_STALL_STATUS                                                                      0x133b
++#define mmMPCC7_MPCC_STALL_STATUS_BASE_IDX                                                             2
++#define mmMPCC7_MPCC_STATUS                                                                            0x133c
++#define mmMPCC7_MPCC_STATUS_BASE_IDX                                                                   2
++
++
++// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
++// base address: 0x0
++#define mmMPC_CLOCK_CONTROL                                                                            0x1349
++#define mmMPC_CLOCK_CONTROL_BASE_IDX                                                                   2
++#define mmMPC_SOFT_RESET                                                                               0x134a
++#define mmMPC_SOFT_RESET_BASE_IDX                                                                      2
++#define mmMPC_CRC_CTRL                                                                                 0x134b
++#define mmMPC_CRC_CTRL_BASE_IDX                                                                        2
++#define mmMPC_CRC_SEL_CONTROL                                                                          0x134c
++#define mmMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 2
++#define mmMPC_CRC_RESULT_AR                                                                            0x134d
++#define mmMPC_CRC_RESULT_AR_BASE_IDX                                                                   2
++#define mmMPC_CRC_RESULT_GB                                                                            0x134e
++#define mmMPC_CRC_RESULT_GB_BASE_IDX                                                                   2
++#define mmMPC_CRC_RESULT_C                                                                             0x134f
++#define mmMPC_CRC_RESULT_C_BASE_IDX                                                                    2
++#define mmMPC_PERFMON_EVENT_CTRL                                                                       0x1352
++#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX                                                              2
++#define mmMPC_BYPASS_BG_AR                                                                             0x1353
++#define mmMPC_BYPASS_BG_AR_BASE_IDX                                                                    2
++#define mmMPC_BYPASS_BG_GB                                                                             0x1354
++#define mmMPC_BYPASS_BG_GB_BASE_IDX                                                                    2
++#define mmMPC_STALL_GRACE_WINDOW                                                                       0x1355
++#define mmMPC_STALL_GRACE_WINDOW_BASE_IDX                                                              2
++#define mmMPC_HOST_READ_CONTROL                                                                        0x1356
++#define mmMPC_HOST_READ_CONTROL_BASE_IDX                                                               2
++#define mmMPC_PENDING_TAKEN_STATUS_REG1                                                                0x1357
++#define mmMPC_PENDING_TAKEN_STATUS_REG1_BASE_IDX                                                       2
++#define mmMPC_PENDING_TAKEN_STATUS_REG3                                                                0x1359
++#define mmMPC_PENDING_TAKEN_STATUS_REG3_BASE_IDX                                                       2
++#define mmMPC_UPDATE_ACK_REG5                                                                          0x135b
++#define mmMPC_UPDATE_ACK_REG5_BASE_IDX                                                                 2
++#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0                                                                0x135d
++#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX                                                       2
++#define mmADR_CFG_VUPDATE_LOCK_SET0                                                                    0x135e
++#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX                                                           2
++#define mmADR_VUPDATE_LOCK_SET0                                                                        0x135f
++#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX                                                               2
++#define mmCFG_VUPDATE_LOCK_SET0                                                                        0x1360
++#define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX                                                               2
++#define mmCUR_VUPDATE_LOCK_SET0                                                                        0x1361
++#define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX                                                               2
++#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1                                                                0x1362
++#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX                                                       2
++#define mmADR_CFG_VUPDATE_LOCK_SET1                                                                    0x1363
++#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX                                                           2
++#define mmADR_VUPDATE_LOCK_SET1                                                                        0x1364
++#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX                                                               2
++#define mmCFG_VUPDATE_LOCK_SET1                                                                        0x1365
++#define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX                                                               2
++#define mmCUR_VUPDATE_LOCK_SET1                                                                        0x1366
++#define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX                                                               2
++#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2                                                                0x1367
++#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX                                                       2
++#define mmADR_CFG_VUPDATE_LOCK_SET2                                                                    0x1368
++#define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX                                                           2
++#define mmADR_VUPDATE_LOCK_SET2                                                                        0x1369
++#define mmADR_VUPDATE_LOCK_SET2_BASE_IDX                                                               2
++#define mmCFG_VUPDATE_LOCK_SET2                                                                        0x136a
++#define mmCFG_VUPDATE_LOCK_SET2_BASE_IDX                                                               2
++#define mmCUR_VUPDATE_LOCK_SET2                                                                        0x136b
++#define mmCUR_VUPDATE_LOCK_SET2_BASE_IDX                                                               2
++#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3                                                                0x136c
++#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX                                                       2
++#define mmADR_CFG_VUPDATE_LOCK_SET3                                                                    0x136d
++#define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX                                                           2
++#define mmADR_VUPDATE_LOCK_SET3                                                                        0x136e
++#define mmADR_VUPDATE_LOCK_SET3_BASE_IDX                                                               2
++#define mmCFG_VUPDATE_LOCK_SET3                                                                        0x136f
++#define mmCFG_VUPDATE_LOCK_SET3_BASE_IDX                                                               2
++#define mmCUR_VUPDATE_LOCK_SET3                                                                        0x1370
++#define mmCUR_VUPDATE_LOCK_SET3_BASE_IDX                                                               2
++#define mmMPC_OUT0_MUX                                                                                 0x1385
++#define mmMPC_OUT0_MUX_BASE_IDX                                                                        2
++#define mmMPC_OUT0_DENORM_CONTROL                                                                      0x1386
++#define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX                                                             2
++#define mmMPC_OUT0_DENORM_CLAMP_G_Y                                                                    0x1387
++#define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX                                                           2
++#define mmMPC_OUT0_DENORM_CLAMP_B_CB                                                                   0x1388
++#define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX                                                          2
++#define mmMPC_OUT1_MUX                                                                                 0x1389
++#define mmMPC_OUT1_MUX_BASE_IDX                                                                        2
++#define mmMPC_OUT1_DENORM_CONTROL                                                                      0x138a
++#define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX                                                             2
++#define mmMPC_OUT1_DENORM_CLAMP_G_Y                                                                    0x138b
++#define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX                                                           2
++#define mmMPC_OUT1_DENORM_CLAMP_B_CB                                                                   0x138c
++#define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX                                                          2
++#define mmMPC_OUT2_MUX                                                                                 0x138d
++#define mmMPC_OUT2_MUX_BASE_IDX                                                                        2
++#define mmMPC_OUT2_DENORM_CONTROL                                                                      0x138e
++#define mmMPC_OUT2_DENORM_CONTROL_BASE_IDX                                                             2
++#define mmMPC_OUT2_DENORM_CLAMP_G_Y                                                                    0x138f
++#define mmMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX                                                           2
++#define mmMPC_OUT2_DENORM_CLAMP_B_CB                                                                   0x1390
++#define mmMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX                                                          2
++#define mmMPC_OUT3_MUX                                                                                 0x1391
++#define mmMPC_OUT3_MUX_BASE_IDX                                                                        2
++#define mmMPC_OUT3_DENORM_CONTROL                                                                      0x1392
++#define mmMPC_OUT3_DENORM_CONTROL_BASE_IDX                                                             2
++#define mmMPC_OUT3_DENORM_CLAMP_G_Y                                                                    0x1393
++#define mmMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX                                                           2
++#define mmMPC_OUT3_DENORM_CLAMP_B_CB                                                                   0x1394
++#define mmMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
++// base address: 0x0
++#define mmMPCC_OGAM0_MPCC_OGAM_MODE                                                                    0x13ae
++#define mmMPCC_OGAM0_MPCC_OGAM_MODE_BASE_IDX                                                           2
++#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX                                                               0x13af
++#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
++#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA                                                                0x13b0
++#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
++#define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x13b1
++#define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x13b2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x13b3
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x13b4
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x13b5
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x13b6
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x13b7
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x13b8
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x13b9
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x13ba
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x13bb
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x13bc
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x13bd
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1                                                         0x13be
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3                                                         0x13bf
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5                                                         0x13c0
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7                                                         0x13c1
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9                                                         0x13c2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11                                                       0x13c3
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13                                                       0x13c4
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15                                                       0x13c5
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17                                                       0x13c6
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19                                                       0x13c7
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21                                                       0x13c8
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23                                                       0x13c9
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25                                                       0x13ca
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27                                                       0x13cb
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29                                                       0x13cc
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31                                                       0x13cd
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33                                                       0x13ce
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x13cf
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x13d0
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x13d1
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x13d2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x13d3
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x13d4
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x13d5
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x13d6
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x13d7
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x13d8
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x13d9
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x13da
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1                                                         0x13db
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3                                                         0x13dc
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5                                                         0x13dd
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7                                                         0x13de
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9                                                         0x13df
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11                                                       0x13e0
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13                                                       0x13e1
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15                                                       0x13e2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17                                                       0x13e3
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19                                                       0x13e4
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21                                                       0x13e5
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23                                                       0x13e6
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25                                                       0x13e7
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27                                                       0x13e8
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29                                                       0x13e9
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31                                                       0x13ea
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33                                                       0x13eb
++#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
++
++
++// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
++// base address: 0x104
++#define mmMPCC_OGAM1_MPCC_OGAM_MODE                                                                    0x13ef
++#define mmMPCC_OGAM1_MPCC_OGAM_MODE_BASE_IDX                                                           2
++#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX                                                               0x13f0
++#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
++#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA                                                                0x13f1
++#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
++#define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x13f2
++#define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x13f3
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x13f4
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x13f5
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x13f6
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x13f7
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x13f8
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x13f9
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x13fa
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x13fb
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x13fc
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x13fd
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x13fe
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1                                                         0x13ff
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3                                                         0x1400
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5                                                         0x1401
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7                                                         0x1402
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9                                                         0x1403
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11                                                       0x1404
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13                                                       0x1405
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15                                                       0x1406
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17                                                       0x1407
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19                                                       0x1408
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21                                                       0x1409
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23                                                       0x140a
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25                                                       0x140b
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27                                                       0x140c
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29                                                       0x140d
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31                                                       0x140e
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33                                                       0x140f
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x1410
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x1411
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x1412
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x1413
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x1414
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x1415
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x1416
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x1417
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x1418
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x1419
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x141a
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x141b
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1                                                         0x141c
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3                                                         0x141d
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5                                                         0x141e
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7                                                         0x141f
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9                                                         0x1420
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11                                                       0x1421
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13                                                       0x1422
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15                                                       0x1423
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17                                                       0x1424
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19                                                       0x1425
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21                                                       0x1426
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23                                                       0x1427
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25                                                       0x1428
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27                                                       0x1429
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29                                                       0x142a
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31                                                       0x142b
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33                                                       0x142c
++#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
++
++
++// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
++// base address: 0x208
++#define mmMPCC_OGAM2_MPCC_OGAM_MODE                                                                    0x1430
++#define mmMPCC_OGAM2_MPCC_OGAM_MODE_BASE_IDX                                                           2
++#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX                                                               0x1431
++#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
++#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA                                                                0x1432
++#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
++#define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x1433
++#define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x1434
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x1435
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x1436
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x1437
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x1438
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x1439
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x143a
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x143b
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x143c
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x143d
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x143e
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x143f
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1                                                         0x1440
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3                                                         0x1441
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5                                                         0x1442
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7                                                         0x1443
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9                                                         0x1444
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11                                                       0x1445
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13                                                       0x1446
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15                                                       0x1447
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17                                                       0x1448
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19                                                       0x1449
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21                                                       0x144a
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23                                                       0x144b
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25                                                       0x144c
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27                                                       0x144d
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29                                                       0x144e
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31                                                       0x144f
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33                                                       0x1450
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x1451
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x1452
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x1453
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x1454
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x1455
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x1456
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x1457
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x1458
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x1459
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x145a
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x145b
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x145c
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1                                                         0x145d
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3                                                         0x145e
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5                                                         0x145f
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7                                                         0x1460
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9                                                         0x1461
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11                                                       0x1462
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13                                                       0x1463
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15                                                       0x1464
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17                                                       0x1465
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19                                                       0x1466
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21                                                       0x1467
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23                                                       0x1468
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25                                                       0x1469
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27                                                       0x146a
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29                                                       0x146b
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31                                                       0x146c
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33                                                       0x146d
++#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
++
++
++// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
++// base address: 0x30c
++#define mmMPCC_OGAM3_MPCC_OGAM_MODE                                                                    0x1471
++#define mmMPCC_OGAM3_MPCC_OGAM_MODE_BASE_IDX                                                           2
++#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX                                                               0x1472
++#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
++#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA                                                                0x1473
++#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
++#define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x1474
++#define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x1475
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x1476
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x1477
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x1478
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x1479
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x147a
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x147b
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x147c
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x147d
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x147e
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x147f
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x1480
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1                                                         0x1481
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3                                                         0x1482
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5                                                         0x1483
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7                                                         0x1484
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9                                                         0x1485
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11                                                       0x1486
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13                                                       0x1487
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15                                                       0x1488
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17                                                       0x1489
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19                                                       0x148a
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21                                                       0x148b
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23                                                       0x148c
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25                                                       0x148d
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27                                                       0x148e
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29                                                       0x148f
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31                                                       0x1490
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33                                                       0x1491
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x1492
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x1493
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x1494
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x1495
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x1496
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x1497
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x1498
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x1499
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x149a
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x149b
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x149c
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x149d
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1                                                         0x149e
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3                                                         0x149f
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5                                                         0x14a0
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7                                                         0x14a1
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9                                                         0x14a2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11                                                       0x14a3
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13                                                       0x14a4
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15                                                       0x14a5
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17                                                       0x14a6
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19                                                       0x14a7
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21                                                       0x14a8
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23                                                       0x14a9
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25                                                       0x14aa
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27                                                       0x14ab
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29                                                       0x14ac
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31                                                       0x14ad
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33                                                       0x14ae
++#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
++
++
++// addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec
++// base address: 0x410
++#define mmMPCC_OGAM4_MPCC_OGAM_MODE                                                                    0x14b2
++#define mmMPCC_OGAM4_MPCC_OGAM_MODE_BASE_IDX                                                           2
++#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX                                                               0x14b3
++#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
++#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA                                                                0x14b4
++#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
++#define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x14b5
++#define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x14b6
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x14b7
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x14b8
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x14b9
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x14ba
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x14bb
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x14bc
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x14bd
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x14be
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x14bf
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x14c0
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x14c1
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1                                                         0x14c2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3                                                         0x14c3
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5                                                         0x14c4
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7                                                         0x14c5
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9                                                         0x14c6
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11                                                       0x14c7
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13                                                       0x14c8
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15                                                       0x14c9
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17                                                       0x14ca
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19                                                       0x14cb
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21                                                       0x14cc
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23                                                       0x14cd
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25                                                       0x14ce
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27                                                       0x14cf
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29                                                       0x14d0
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31                                                       0x14d1
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33                                                       0x14d2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x14d3
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x14d4
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x14d5
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x14d6
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x14d7
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x14d8
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x14d9
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x14da
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x14db
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x14dc
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x14dd
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x14de
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1                                                         0x14df
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3                                                         0x14e0
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5                                                         0x14e1
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7                                                         0x14e2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9                                                         0x14e3
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11                                                       0x14e4
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13                                                       0x14e5
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15                                                       0x14e6
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17                                                       0x14e7
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19                                                       0x14e8
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21                                                       0x14e9
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23                                                       0x14ea
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25                                                       0x14eb
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27                                                       0x14ec
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29                                                       0x14ed
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31                                                       0x14ee
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33                                                       0x14ef
++#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
++
++
++// addressBlock: dce_dc_mpc_mpcc_ogam5_dispdec
++// base address: 0x514
++#define mmMPCC_OGAM5_MPCC_OGAM_MODE                                                                    0x14f3
++#define mmMPCC_OGAM5_MPCC_OGAM_MODE_BASE_IDX                                                           2
++#define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX                                                               0x14f4
++#define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
++#define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA                                                                0x14f5
++#define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
++#define mmMPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x14f6
++#define mmMPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x14f7
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x14f8
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x14f9
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x14fa
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x14fb
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x14fc
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x14fd
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x14fe
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x14ff
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x1500
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x1501
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x1502
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1                                                         0x1503
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3                                                         0x1504
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5                                                         0x1505
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7                                                         0x1506
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9                                                         0x1507
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11                                                       0x1508
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13                                                       0x1509
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15                                                       0x150a
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17                                                       0x150b
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19                                                       0x150c
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21                                                       0x150d
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23                                                       0x150e
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25                                                       0x150f
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27                                                       0x1510
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29                                                       0x1511
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31                                                       0x1512
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33                                                       0x1513
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x1514
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x1515
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x1516
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x1517
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x1518
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x1519
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x151a
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x151b
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x151c
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x151d
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x151e
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x151f
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1                                                         0x1520
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3                                                         0x1521
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5                                                         0x1522
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7                                                         0x1523
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9                                                         0x1524
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11                                                       0x1525
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13                                                       0x1526
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15                                                       0x1527
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17                                                       0x1528
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19                                                       0x1529
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21                                                       0x152a
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23                                                       0x152b
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25                                                       0x152c
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27                                                       0x152d
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29                                                       0x152e
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31                                                       0x152f
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33                                                       0x1530
++#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
++
++
++// addressBlock: dce_dc_mpc_mpcc_ogam6_dispdec
++// base address: 0x618
++#define mmMPCC_OGAM6_MPCC_OGAM_MODE                                                                    0x1534
++#define mmMPCC_OGAM6_MPCC_OGAM_MODE_BASE_IDX                                                           2
++#define mmMPCC_OGAM6_MPCC_OGAM_LUT_INDEX                                                               0x1535
++#define mmMPCC_OGAM6_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
++#define mmMPCC_OGAM6_MPCC_OGAM_LUT_DATA                                                                0x1536
++#define mmMPCC_OGAM6_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
++#define mmMPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x1537
++#define mmMPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x1538
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x1539
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x153a
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x153b
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x153c
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x153d
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x153e
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x153f
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x1540
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x1541
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x1542
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x1543
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1                                                         0x1544
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3                                                         0x1545
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5                                                         0x1546
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7                                                         0x1547
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9                                                         0x1548
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11                                                       0x1549
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13                                                       0x154a
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15                                                       0x154b
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17                                                       0x154c
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19                                                       0x154d
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21                                                       0x154e
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23                                                       0x154f
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25                                                       0x1550
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27                                                       0x1551
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29                                                       0x1552
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31                                                       0x1553
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33                                                       0x1554
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x1555
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x1556
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x1557
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x1558
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x1559
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x155a
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x155b
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x155c
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x155d
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x155e
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x155f
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x1560
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1                                                         0x1561
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3                                                         0x1562
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5                                                         0x1563
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7                                                         0x1564
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9                                                         0x1565
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11                                                       0x1566
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13                                                       0x1567
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15                                                       0x1568
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17                                                       0x1569
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19                                                       0x156a
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21                                                       0x156b
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23                                                       0x156c
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25                                                       0x156d
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27                                                       0x156e
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29                                                       0x156f
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31                                                       0x1570
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33                                                       0x1571
++#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
++
++
++// addressBlock: dce_dc_mpc_mpcc_ogam7_dispdec
++// base address: 0x71c
++#define mmMPCC_OGAM7_MPCC_OGAM_MODE                                                                    0x1575
++#define mmMPCC_OGAM7_MPCC_OGAM_MODE_BASE_IDX                                                           2
++#define mmMPCC_OGAM7_MPCC_OGAM_LUT_INDEX                                                               0x1576
++#define mmMPCC_OGAM7_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
++#define mmMPCC_OGAM7_MPCC_OGAM_LUT_DATA                                                                0x1577
++#define mmMPCC_OGAM7_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
++#define mmMPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x1578
++#define mmMPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x1579
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x157a
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x157b
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x157c
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x157d
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x157e
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x157f
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x1580
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x1581
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x1582
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x1583
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x1584
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1                                                         0x1585
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3                                                         0x1586
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5                                                         0x1587
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7                                                         0x1588
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9                                                         0x1589
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11                                                       0x158a
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13                                                       0x158b
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15                                                       0x158c
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17                                                       0x158d
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19                                                       0x158e
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21                                                       0x158f
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23                                                       0x1590
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25                                                       0x1591
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27                                                       0x1592
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29                                                       0x1593
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31                                                       0x1594
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33                                                       0x1595
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x1596
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x1597
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x1598
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x1599
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x159a
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x159b
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x159c
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x159d
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x159e
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x159f
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x15a0
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x15a1
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1                                                         0x15a2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3                                                         0x15a3
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5                                                         0x15a4
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7                                                         0x15a5
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9                                                         0x15a6
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11                                                       0x15a7
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13                                                       0x15a8
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15                                                       0x15a9
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17                                                       0x15aa
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19                                                       0x15ab
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21                                                       0x15ac
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23                                                       0x15ad
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25                                                       0x15ae
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27                                                       0x15af
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29                                                       0x15b0
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31                                                       0x15b1
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33                                                       0x15b2
++#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
++
++
++// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
++// base address: 0x0
++#define mmMPC_OUT_CSC_COEF_FORMAT                                                                      0x15b6
++#define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX                                                             2
++#define mmMPC_OUT0_CSC_MODE                                                                            0x15b7
++#define mmMPC_OUT0_CSC_MODE_BASE_IDX                                                                   2
++#define mmMPC_OUT0_CSC_C11_C12_A                                                                       0x15b8
++#define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX                                                              2
++#define mmMPC_OUT0_CSC_C13_C14_A                                                                       0x15b9
++#define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX                                                              2
++#define mmMPC_OUT0_CSC_C21_C22_A                                                                       0x15ba
++#define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX                                                              2
++#define mmMPC_OUT0_CSC_C23_C24_A                                                                       0x15bb
++#define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX                                                              2
++#define mmMPC_OUT0_CSC_C31_C32_A                                                                       0x15bc
++#define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX                                                              2
++#define mmMPC_OUT0_CSC_C33_C34_A                                                                       0x15bd
++#define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX                                                              2
++#define mmMPC_OUT0_CSC_C11_C12_B                                                                       0x15be
++#define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX                                                              2
++#define mmMPC_OUT0_CSC_C13_C14_B                                                                       0x15bf
++#define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX                                                              2
++#define mmMPC_OUT0_CSC_C21_C22_B                                                                       0x15c0
++#define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX                                                              2
++#define mmMPC_OUT0_CSC_C23_C24_B                                                                       0x15c1
++#define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX                                                              2
++#define mmMPC_OUT0_CSC_C31_C32_B                                                                       0x15c2
++#define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX                                                              2
++#define mmMPC_OUT0_CSC_C33_C34_B                                                                       0x15c3
++#define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX                                                              2
++#define mmMPC_OUT1_CSC_MODE                                                                            0x15c4
++#define mmMPC_OUT1_CSC_MODE_BASE_IDX                                                                   2
++#define mmMPC_OUT1_CSC_C11_C12_A                                                                       0x15c5
++#define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX                                                              2
++#define mmMPC_OUT1_CSC_C13_C14_A                                                                       0x15c6
++#define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX                                                              2
++#define mmMPC_OUT1_CSC_C21_C22_A                                                                       0x15c7
++#define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX                                                              2
++#define mmMPC_OUT1_CSC_C23_C24_A                                                                       0x15c8
++#define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX                                                              2
++#define mmMPC_OUT1_CSC_C31_C32_A                                                                       0x15c9
++#define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX                                                              2
++#define mmMPC_OUT1_CSC_C33_C34_A                                                                       0x15ca
++#define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX                                                              2
++#define mmMPC_OUT1_CSC_C11_C12_B                                                                       0x15cb
++#define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX                                                              2
++#define mmMPC_OUT1_CSC_C13_C14_B                                                                       0x15cc
++#define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX                                                              2
++#define mmMPC_OUT1_CSC_C21_C22_B                                                                       0x15cd
++#define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX                                                              2
++#define mmMPC_OUT1_CSC_C23_C24_B                                                                       0x15ce
++#define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX                                                              2
++#define mmMPC_OUT1_CSC_C31_C32_B                                                                       0x15cf
++#define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX                                                              2
++#define mmMPC_OUT1_CSC_C33_C34_B                                                                       0x15d0
++#define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX                                                              2
++#define mmMPC_OUT2_CSC_MODE                                                                            0x15d1
++#define mmMPC_OUT2_CSC_MODE_BASE_IDX                                                                   2
++#define mmMPC_OUT2_CSC_C11_C12_A                                                                       0x15d2
++#define mmMPC_OUT2_CSC_C11_C12_A_BASE_IDX                                                              2
++#define mmMPC_OUT2_CSC_C13_C14_A                                                                       0x15d3
++#define mmMPC_OUT2_CSC_C13_C14_A_BASE_IDX                                                              2
++#define mmMPC_OUT2_CSC_C21_C22_A                                                                       0x15d4
++#define mmMPC_OUT2_CSC_C21_C22_A_BASE_IDX                                                              2
++#define mmMPC_OUT2_CSC_C23_C24_A                                                                       0x15d5
++#define mmMPC_OUT2_CSC_C23_C24_A_BASE_IDX                                                              2
++#define mmMPC_OUT2_CSC_C31_C32_A                                                                       0x15d6
++#define mmMPC_OUT2_CSC_C31_C32_A_BASE_IDX                                                              2
++#define mmMPC_OUT2_CSC_C33_C34_A                                                                       0x15d7
++#define mmMPC_OUT2_CSC_C33_C34_A_BASE_IDX                                                              2
++#define mmMPC_OUT2_CSC_C11_C12_B                                                                       0x15d8
++#define mmMPC_OUT2_CSC_C11_C12_B_BASE_IDX                                                              2
++#define mmMPC_OUT2_CSC_C13_C14_B                                                                       0x15d9
++#define mmMPC_OUT2_CSC_C13_C14_B_BASE_IDX                                                              2
++#define mmMPC_OUT2_CSC_C21_C22_B                                                                       0x15da
++#define mmMPC_OUT2_CSC_C21_C22_B_BASE_IDX                                                              2
++#define mmMPC_OUT2_CSC_C23_C24_B                                                                       0x15db
++#define mmMPC_OUT2_CSC_C23_C24_B_BASE_IDX                                                              2
++#define mmMPC_OUT2_CSC_C31_C32_B                                                                       0x15dc
++#define mmMPC_OUT2_CSC_C31_C32_B_BASE_IDX                                                              2
++#define mmMPC_OUT2_CSC_C33_C34_B                                                                       0x15dd
++#define mmMPC_OUT2_CSC_C33_C34_B_BASE_IDX                                                              2
++#define mmMPC_OUT3_CSC_MODE                                                                            0x15de
++#define mmMPC_OUT3_CSC_MODE_BASE_IDX                                                                   2
++#define mmMPC_OUT3_CSC_C11_C12_A                                                                       0x15df
++#define mmMPC_OUT3_CSC_C11_C12_A_BASE_IDX                                                              2
++#define mmMPC_OUT3_CSC_C13_C14_A                                                                       0x15e0
++#define mmMPC_OUT3_CSC_C13_C14_A_BASE_IDX                                                              2
++#define mmMPC_OUT3_CSC_C21_C22_A                                                                       0x15e1
++#define mmMPC_OUT3_CSC_C21_C22_A_BASE_IDX                                                              2
++#define mmMPC_OUT3_CSC_C23_C24_A                                                                       0x15e2
++#define mmMPC_OUT3_CSC_C23_C24_A_BASE_IDX                                                              2
++#define mmMPC_OUT3_CSC_C31_C32_A                                                                       0x15e3
++#define mmMPC_OUT3_CSC_C31_C32_A_BASE_IDX                                                              2
++#define mmMPC_OUT3_CSC_C33_C34_A                                                                       0x15e4
++#define mmMPC_OUT3_CSC_C33_C34_A_BASE_IDX                                                              2
++#define mmMPC_OUT3_CSC_C11_C12_B                                                                       0x15e5
++#define mmMPC_OUT3_CSC_C11_C12_B_BASE_IDX                                                              2
++#define mmMPC_OUT3_CSC_C13_C14_B                                                                       0x15e6
++#define mmMPC_OUT3_CSC_C13_C14_B_BASE_IDX                                                              2
++#define mmMPC_OUT3_CSC_C21_C22_B                                                                       0x15e7
++#define mmMPC_OUT3_CSC_C21_C22_B_BASE_IDX                                                              2
++#define mmMPC_OUT3_CSC_C23_C24_B                                                                       0x15e8
++#define mmMPC_OUT3_CSC_C23_C24_B_BASE_IDX                                                              2
++#define mmMPC_OUT3_CSC_C31_C32_B                                                                       0x15e9
++#define mmMPC_OUT3_CSC_C31_C32_B_BASE_IDX                                                              2
++#define mmMPC_OUT3_CSC_C33_C34_B                                                                       0x15ea
++#define mmMPC_OUT3_CSC_C33_C34_B_BASE_IDX                                                              2
++
++
++// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
++// base address: 0x5964
++#define mmDC_PERFMON15_PERFCOUNTER_CNTL                                                                0x1659
++#define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX                                                       2
++#define mmDC_PERFMON15_PERFCOUNTER_CNTL2                                                               0x165a
++#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
++#define mmDC_PERFMON15_PERFCOUNTER_STATE                                                               0x165b
++#define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX                                                      2
++#define mmDC_PERFMON15_PERFMON_CNTL                                                                    0x165c
++#define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX                                                           2
++#define mmDC_PERFMON15_PERFMON_CNTL2                                                                   0x165d
++#define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX                                                          2
++#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC                                                         0x165e
++#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
++#define mmDC_PERFMON15_PERFMON_CVALUE_LOW                                                              0x165f
++#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
++#define mmDC_PERFMON15_PERFMON_HI                                                                      0x1660
++#define mmDC_PERFMON15_PERFMON_HI_BASE_IDX                                                             2
++#define mmDC_PERFMON15_PERFMON_LOW                                                                     0x1661
++#define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_opp_abm0_dispdec
++// base address: 0x0
++#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL                                                                  0x17b0
++#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                         2
++#define mmBL1_PWM_USER_LEVEL                                                                           0x17b1
++#define mmBL1_PWM_USER_LEVEL_BASE_IDX                                                                  2
++#define mmBL1_PWM_TARGET_ABM_LEVEL                                                                     0x17b2
++#define mmBL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                            2
++#define mmBL1_PWM_CURRENT_ABM_LEVEL                                                                    0x17b3
++#define mmBL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                           2
++#define mmBL1_PWM_FINAL_DUTY_CYCLE                                                                     0x17b4
++#define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                            2
++#define mmBL1_PWM_MINIMUM_DUTY_CYCLE                                                                   0x17b5
++#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                          2
++#define mmBL1_PWM_ABM_CNTL                                                                             0x17b6
++#define mmBL1_PWM_ABM_CNTL_BASE_IDX                                                                    2
++#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE                                                                0x17b7
++#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                       2
++#define mmBL1_PWM_GRP2_REG_LOCK                                                                        0x17b8
++#define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                               2
++#define mmDC_ABM1_CNTL                                                                                 0x17b9
++#define mmDC_ABM1_CNTL_BASE_IDX                                                                        2
++#define mmDC_ABM1_IPCSC_COEFF_SEL                                                                      0x17ba
++#define mmDC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                             2
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_0                                                                   0x17bb
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                          2
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_1                                                                   0x17bc
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                          2
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_2                                                                   0x17bd
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                          2
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_3                                                                   0x17be
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                          2
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_4                                                                   0x17bf
++#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                          2
++#define mmDC_ABM1_ACE_THRES_12                                                                         0x17c0
++#define mmDC_ABM1_ACE_THRES_12_BASE_IDX                                                                2
++#define mmDC_ABM1_ACE_THRES_34                                                                         0x17c1
++#define mmDC_ABM1_ACE_THRES_34_BASE_IDX                                                                2
++#define mmDC_ABM1_ACE_CNTL_MISC                                                                        0x17c2
++#define mmDC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                               2
++#define mmDC_ABM1_HGLS_REG_READ_PROGRESS                                                               0x17c4
++#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                      2
++#define mmDC_ABM1_HG_MISC_CTRL                                                                         0x17c5
++#define mmDC_ABM1_HG_MISC_CTRL_BASE_IDX                                                                2
++#define mmDC_ABM1_LS_SUM_OF_LUMA                                                                       0x17c6
++#define mmDC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                              2
++#define mmDC_ABM1_LS_MIN_MAX_LUMA                                                                      0x17c7
++#define mmDC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                             2
++#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                             0x17c8
++#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                                    2
++#define mmDC_ABM1_LS_PIXEL_COUNT                                                                       0x17c9
++#define mmDC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                              2
++#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                         0x17ca
++#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                                2
++#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                             0x17cb
++#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                                    2
++#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                             0x17cc
++#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                                    2
++#define mmDC_ABM1_HG_SAMPLE_RATE                                                                       0x17cd
++#define mmDC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                              2
++#define mmDC_ABM1_LS_SAMPLE_RATE                                                                       0x17ce
++#define mmDC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                              2
++#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                               0x17cf
++#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                      2
++#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                               0x17d0
++#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                      2
++#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                              0x17d1
++#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                     2
++#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                             0x17d2
++#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                                    2
++#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                             0x17d3
++#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                                    2
++#define mmDC_ABM1_HG_RESULT_1                                                                          0x17d4
++#define mmDC_ABM1_HG_RESULT_1_BASE_IDX                                                                 2
++#define mmDC_ABM1_HG_RESULT_2                                                                          0x17d5
++#define mmDC_ABM1_HG_RESULT_2_BASE_IDX                                                                 2
++#define mmDC_ABM1_HG_RESULT_3                                                                          0x17d6
++#define mmDC_ABM1_HG_RESULT_3_BASE_IDX                                                                 2
++#define mmDC_ABM1_HG_RESULT_4                                                                          0x17d7
++#define mmDC_ABM1_HG_RESULT_4_BASE_IDX                                                                 2
++#define mmDC_ABM1_HG_RESULT_5                                                                          0x17d8
++#define mmDC_ABM1_HG_RESULT_5_BASE_IDX                                                                 2
++#define mmDC_ABM1_HG_RESULT_6                                                                          0x17d9
++#define mmDC_ABM1_HG_RESULT_6_BASE_IDX                                                                 2
++#define mmDC_ABM1_HG_RESULT_7                                                                          0x17da
++#define mmDC_ABM1_HG_RESULT_7_BASE_IDX                                                                 2
++#define mmDC_ABM1_HG_RESULT_8                                                                          0x17db
++#define mmDC_ABM1_HG_RESULT_8_BASE_IDX                                                                 2
++#define mmDC_ABM1_HG_RESULT_9                                                                          0x17dc
++#define mmDC_ABM1_HG_RESULT_9_BASE_IDX                                                                 2
++#define mmDC_ABM1_HG_RESULT_10                                                                         0x17dd
++#define mmDC_ABM1_HG_RESULT_10_BASE_IDX                                                                2
++#define mmDC_ABM1_HG_RESULT_11                                                                         0x17de
++#define mmDC_ABM1_HG_RESULT_11_BASE_IDX                                                                2
++#define mmDC_ABM1_HG_RESULT_12                                                                         0x17df
++#define mmDC_ABM1_HG_RESULT_12_BASE_IDX                                                                2
++#define mmDC_ABM1_HG_RESULT_13                                                                         0x17e0
++#define mmDC_ABM1_HG_RESULT_13_BASE_IDX                                                                2
++#define mmDC_ABM1_HG_RESULT_14                                                                         0x17e1
++#define mmDC_ABM1_HG_RESULT_14_BASE_IDX                                                                2
++#define mmDC_ABM1_HG_RESULT_15                                                                         0x17e2
++#define mmDC_ABM1_HG_RESULT_15_BASE_IDX                                                                2
++#define mmDC_ABM1_HG_RESULT_16                                                                         0x17e3
++#define mmDC_ABM1_HG_RESULT_16_BASE_IDX                                                                2
++#define mmDC_ABM1_HG_RESULT_17                                                                         0x17e4
++#define mmDC_ABM1_HG_RESULT_17_BASE_IDX                                                                2
++#define mmDC_ABM1_HG_RESULT_18                                                                         0x17e5
++#define mmDC_ABM1_HG_RESULT_18_BASE_IDX                                                                2
++#define mmDC_ABM1_HG_RESULT_19                                                                         0x17e6
++#define mmDC_ABM1_HG_RESULT_19_BASE_IDX                                                                2
++#define mmDC_ABM1_HG_RESULT_20                                                                         0x17e7
++#define mmDC_ABM1_HG_RESULT_20_BASE_IDX                                                                2
++#define mmDC_ABM1_HG_RESULT_21                                                                         0x17e8
++#define mmDC_ABM1_HG_RESULT_21_BASE_IDX                                                                2
++#define mmDC_ABM1_HG_RESULT_22                                                                         0x17e9
++#define mmDC_ABM1_HG_RESULT_22_BASE_IDX                                                                2
++#define mmDC_ABM1_HG_RESULT_23                                                                         0x17ea
++#define mmDC_ABM1_HG_RESULT_23_BASE_IDX                                                                2
++#define mmDC_ABM1_HG_RESULT_24                                                                         0x17eb
++#define mmDC_ABM1_HG_RESULT_24_BASE_IDX                                                                2
++#define mmDC_ABM1_BL_MASTER_LOCK                                                                       0x17ec
++#define mmDC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                              2
++
++
++// addressBlock: dce_dc_opp_fmt0_dispdec
++// base address: 0x0
++#define mmFMT0_FMT_CLAMP_COMPONENT_R                                                                   0x183c
++#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
++#define mmFMT0_FMT_CLAMP_COMPONENT_G                                                                   0x183d
++#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
++#define mmFMT0_FMT_CLAMP_COMPONENT_B                                                                   0x183e
++#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
++#define mmFMT0_FMT_DYNAMIC_EXP_CNTL                                                                    0x183f
++#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
++#define mmFMT0_FMT_CONTROL                                                                             0x1840
++#define mmFMT0_FMT_CONTROL_BASE_IDX                                                                    2
++#define mmFMT0_FMT_BIT_DEPTH_CONTROL                                                                   0x1841
++#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
++#define mmFMT0_FMT_DITHER_RAND_R_SEED                                                                  0x1842
++#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
++#define mmFMT0_FMT_DITHER_RAND_G_SEED                                                                  0x1843
++#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
++#define mmFMT0_FMT_DITHER_RAND_B_SEED                                                                  0x1844
++#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
++#define mmFMT0_FMT_CLAMP_CNTL                                                                          0x1845
++#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
++#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1846
++#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
++#define mmFMT0_FMT_MAP420_MEMORY_CONTROL                                                               0x1847
++#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
++#define mmFMT0_FMT_422_CONTROL                                                                         0x1849
++#define mmFMT0_FMT_422_CONTROL_BASE_IDX                                                                2
++
++
++// addressBlock: dce_dc_opp_dpg0_dispdec
++// base address: 0x0
++#define mmDPG0_DPG_CONTROL                                                                             0x1854
++#define mmDPG0_DPG_CONTROL_BASE_IDX                                                                    2
++#define mmDPG0_DPG_RAMP_CONTROL                                                                        0x1855
++#define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX                                                               2
++#define mmDPG0_DPG_DIMENSIONS                                                                          0x1856
++#define mmDPG0_DPG_DIMENSIONS_BASE_IDX                                                                 2
++#define mmDPG0_DPG_COLOUR_R_CR                                                                         0x1857
++#define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX                                                                2
++#define mmDPG0_DPG_COLOUR_G_Y                                                                          0x1858
++#define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
++#define mmDPG0_DPG_COLOUR_B_CB                                                                         0x1859
++#define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX                                                                2
++#define mmDPG0_DPG_OFFSET_SEGMENT                                                                      0x185a
++#define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
++#define mmDPG0_DPG_STATUS                                                                              0x185b
++#define mmDPG0_DPG_STATUS_BASE_IDX                                                                     2
++
++
++// addressBlock: dce_dc_opp_oppbuf0_dispdec
++// base address: 0x0
++#define mmOPPBUF0_OPPBUF_CONTROL                                                                       0x1884
++#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX                                                              2
++#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0                                                               0x1885
++#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
++#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1                                                               0x1886
++#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
++#define mmOPPBUF0_OPPBUF_CONTROL1                                                                      0x1889
++#define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_opp_opp_pipe0_dispdec
++// base address: 0x0
++#define mmOPP_PIPE0_OPP_PIPE_CONTROL                                                                   0x188c
++#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
++// base address: 0x0
++#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL                                                           0x1891
++#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
++#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK                                                              0x1892
++#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
++#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0                                                           0x1893
++#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
++#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1                                                           0x1894
++#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
++#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2                                                           0x1895
++#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
++
++
++// addressBlock: dce_dc_opp_fmt1_dispdec
++// base address: 0x168
++#define mmFMT1_FMT_CLAMP_COMPONENT_R                                                                   0x1896
++#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
++#define mmFMT1_FMT_CLAMP_COMPONENT_G                                                                   0x1897
++#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
++#define mmFMT1_FMT_CLAMP_COMPONENT_B                                                                   0x1898
++#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
++#define mmFMT1_FMT_DYNAMIC_EXP_CNTL                                                                    0x1899
++#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
++#define mmFMT1_FMT_CONTROL                                                                             0x189a
++#define mmFMT1_FMT_CONTROL_BASE_IDX                                                                    2
++#define mmFMT1_FMT_BIT_DEPTH_CONTROL                                                                   0x189b
++#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
++#define mmFMT1_FMT_DITHER_RAND_R_SEED                                                                  0x189c
++#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
++#define mmFMT1_FMT_DITHER_RAND_G_SEED                                                                  0x189d
++#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
++#define mmFMT1_FMT_DITHER_RAND_B_SEED                                                                  0x189e
++#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
++#define mmFMT1_FMT_CLAMP_CNTL                                                                          0x189f
++#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
++#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18a0
++#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
++#define mmFMT1_FMT_MAP420_MEMORY_CONTROL                                                               0x18a1
++#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
++#define mmFMT1_FMT_422_CONTROL                                                                         0x18a3
++#define mmFMT1_FMT_422_CONTROL_BASE_IDX                                                                2
++
++
++// addressBlock: dce_dc_opp_dpg1_dispdec
++// base address: 0x168
++#define mmDPG1_DPG_CONTROL                                                                             0x18ae
++#define mmDPG1_DPG_CONTROL_BASE_IDX                                                                    2
++#define mmDPG1_DPG_RAMP_CONTROL                                                                        0x18af
++#define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX                                                               2
++#define mmDPG1_DPG_DIMENSIONS                                                                          0x18b0
++#define mmDPG1_DPG_DIMENSIONS_BASE_IDX                                                                 2
++#define mmDPG1_DPG_COLOUR_R_CR                                                                         0x18b1
++#define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX                                                                2
++#define mmDPG1_DPG_COLOUR_G_Y                                                                          0x18b2
++#define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
++#define mmDPG1_DPG_COLOUR_B_CB                                                                         0x18b3
++#define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX                                                                2
++#define mmDPG1_DPG_OFFSET_SEGMENT                                                                      0x18b4
++#define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
++#define mmDPG1_DPG_STATUS                                                                              0x18b5
++#define mmDPG1_DPG_STATUS_BASE_IDX                                                                     2
++
++
++// addressBlock: dce_dc_opp_oppbuf1_dispdec
++// base address: 0x168
++#define mmOPPBUF1_OPPBUF_CONTROL                                                                       0x18de
++#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX                                                              2
++#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0                                                               0x18df
++#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
++#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1                                                               0x18e0
++#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
++#define mmOPPBUF1_OPPBUF_CONTROL1                                                                      0x18e3
++#define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_opp_opp_pipe1_dispdec
++// base address: 0x168
++#define mmOPP_PIPE1_OPP_PIPE_CONTROL                                                                   0x18e6
++#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
++// base address: 0x168
++#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL                                                           0x18eb
++#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
++#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK                                                              0x18ec
++#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
++#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0                                                           0x18ed
++#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
++#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1                                                           0x18ee
++#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
++#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2                                                           0x18ef
++#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
++
++
++// addressBlock: dce_dc_opp_fmt2_dispdec
++// base address: 0x2d0
++#define mmFMT2_FMT_CLAMP_COMPONENT_R                                                                   0x18f0
++#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
++#define mmFMT2_FMT_CLAMP_COMPONENT_G                                                                   0x18f1
++#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
++#define mmFMT2_FMT_CLAMP_COMPONENT_B                                                                   0x18f2
++#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
++#define mmFMT2_FMT_DYNAMIC_EXP_CNTL                                                                    0x18f3
++#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
++#define mmFMT2_FMT_CONTROL                                                                             0x18f4
++#define mmFMT2_FMT_CONTROL_BASE_IDX                                                                    2
++#define mmFMT2_FMT_BIT_DEPTH_CONTROL                                                                   0x18f5
++#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
++#define mmFMT2_FMT_DITHER_RAND_R_SEED                                                                  0x18f6
++#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
++#define mmFMT2_FMT_DITHER_RAND_G_SEED                                                                  0x18f7
++#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
++#define mmFMT2_FMT_DITHER_RAND_B_SEED                                                                  0x18f8
++#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
++#define mmFMT2_FMT_CLAMP_CNTL                                                                          0x18f9
++#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
++#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18fa
++#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
++#define mmFMT2_FMT_MAP420_MEMORY_CONTROL                                                               0x18fb
++#define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
++#define mmFMT2_FMT_422_CONTROL                                                                         0x18fd
++#define mmFMT2_FMT_422_CONTROL_BASE_IDX                                                                2
++
++
++// addressBlock: dce_dc_opp_dpg2_dispdec
++// base address: 0x2d0
++#define mmDPG2_DPG_CONTROL                                                                             0x1908
++#define mmDPG2_DPG_CONTROL_BASE_IDX                                                                    2
++#define mmDPG2_DPG_RAMP_CONTROL                                                                        0x1909
++#define mmDPG2_DPG_RAMP_CONTROL_BASE_IDX                                                               2
++#define mmDPG2_DPG_DIMENSIONS                                                                          0x190a
++#define mmDPG2_DPG_DIMENSIONS_BASE_IDX                                                                 2
++#define mmDPG2_DPG_COLOUR_R_CR                                                                         0x190b
++#define mmDPG2_DPG_COLOUR_R_CR_BASE_IDX                                                                2
++#define mmDPG2_DPG_COLOUR_G_Y                                                                          0x190c
++#define mmDPG2_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
++#define mmDPG2_DPG_COLOUR_B_CB                                                                         0x190d
++#define mmDPG2_DPG_COLOUR_B_CB_BASE_IDX                                                                2
++#define mmDPG2_DPG_OFFSET_SEGMENT                                                                      0x190e
++#define mmDPG2_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
++#define mmDPG2_DPG_STATUS                                                                              0x190f
++#define mmDPG2_DPG_STATUS_BASE_IDX                                                                     2
++
++
++// addressBlock: dce_dc_opp_oppbuf2_dispdec
++// base address: 0x2d0
++#define mmOPPBUF2_OPPBUF_CONTROL                                                                       0x1938
++#define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX                                                              2
++#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0                                                               0x1939
++#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
++#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1                                                               0x193a
++#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
++#define mmOPPBUF2_OPPBUF_CONTROL1                                                                      0x193d
++#define mmOPPBUF2_OPPBUF_CONTROL1_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_opp_opp_pipe2_dispdec
++// base address: 0x2d0
++#define mmOPP_PIPE2_OPP_PIPE_CONTROL                                                                   0x1940
++#define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
++// base address: 0x2d0
++#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL                                                           0x1945
++#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
++#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK                                                              0x1946
++#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
++#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0                                                           0x1947
++#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
++#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1                                                           0x1948
++#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
++#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2                                                           0x1949
++#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
++
++
++// addressBlock: dce_dc_opp_fmt3_dispdec
++// base address: 0x438
++#define mmFMT3_FMT_CLAMP_COMPONENT_R                                                                   0x194a
++#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
++#define mmFMT3_FMT_CLAMP_COMPONENT_G                                                                   0x194b
++#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
++#define mmFMT3_FMT_CLAMP_COMPONENT_B                                                                   0x194c
++#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
++#define mmFMT3_FMT_DYNAMIC_EXP_CNTL                                                                    0x194d
++#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
++#define mmFMT3_FMT_CONTROL                                                                             0x194e
++#define mmFMT3_FMT_CONTROL_BASE_IDX                                                                    2
++#define mmFMT3_FMT_BIT_DEPTH_CONTROL                                                                   0x194f
++#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
++#define mmFMT3_FMT_DITHER_RAND_R_SEED                                                                  0x1950
++#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
++#define mmFMT3_FMT_DITHER_RAND_G_SEED                                                                  0x1951
++#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
++#define mmFMT3_FMT_DITHER_RAND_B_SEED                                                                  0x1952
++#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
++#define mmFMT3_FMT_CLAMP_CNTL                                                                          0x1953
++#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
++#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1954
++#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
++#define mmFMT3_FMT_MAP420_MEMORY_CONTROL                                                               0x1955
++#define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
++#define mmFMT3_FMT_422_CONTROL                                                                         0x1957
++#define mmFMT3_FMT_422_CONTROL_BASE_IDX                                                                2
++
++
++// addressBlock: dce_dc_opp_dpg3_dispdec
++// base address: 0x438
++#define mmDPG3_DPG_CONTROL                                                                             0x1962
++#define mmDPG3_DPG_CONTROL_BASE_IDX                                                                    2
++#define mmDPG3_DPG_RAMP_CONTROL                                                                        0x1963
++#define mmDPG3_DPG_RAMP_CONTROL_BASE_IDX                                                               2
++#define mmDPG3_DPG_DIMENSIONS                                                                          0x1964
++#define mmDPG3_DPG_DIMENSIONS_BASE_IDX                                                                 2
++#define mmDPG3_DPG_COLOUR_R_CR                                                                         0x1965
++#define mmDPG3_DPG_COLOUR_R_CR_BASE_IDX                                                                2
++#define mmDPG3_DPG_COLOUR_G_Y                                                                          0x1966
++#define mmDPG3_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
++#define mmDPG3_DPG_COLOUR_B_CB                                                                         0x1967
++#define mmDPG3_DPG_COLOUR_B_CB_BASE_IDX                                                                2
++#define mmDPG3_DPG_OFFSET_SEGMENT                                                                      0x1968
++#define mmDPG3_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
++#define mmDPG3_DPG_STATUS                                                                              0x1969
++#define mmDPG3_DPG_STATUS_BASE_IDX                                                                     2
++
++
++// addressBlock: dce_dc_opp_oppbuf3_dispdec
++// base address: 0x438
++#define mmOPPBUF3_OPPBUF_CONTROL                                                                       0x1992
++#define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX                                                              2
++#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0                                                               0x1993
++#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
++#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1                                                               0x1994
++#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
++#define mmOPPBUF3_OPPBUF_CONTROL1                                                                      0x1997
++#define mmOPPBUF3_OPPBUF_CONTROL1_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_opp_opp_pipe3_dispdec
++// base address: 0x438
++#define mmOPP_PIPE3_OPP_PIPE_CONTROL                                                                   0x199a
++#define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
++// base address: 0x438
++#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL                                                           0x199f
++#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
++#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK                                                              0x19a0
++#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
++#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0                                                           0x19a1
++#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
++#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1                                                           0x19a2
++#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
++#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2                                                           0x19a3
++#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
++
++
++// addressBlock: dce_dc_opp_fmt4_dispdec
++// base address: 0x5a0
++#define mmFMT4_FMT_CLAMP_COMPONENT_R                                                                   0x19a4
++#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
++#define mmFMT4_FMT_CLAMP_COMPONENT_G                                                                   0x19a5
++#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
++#define mmFMT4_FMT_CLAMP_COMPONENT_B                                                                   0x19a6
++#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
++#define mmFMT4_FMT_DYNAMIC_EXP_CNTL                                                                    0x19a7
++#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
++#define mmFMT4_FMT_CONTROL                                                                             0x19a8
++#define mmFMT4_FMT_CONTROL_BASE_IDX                                                                    2
++#define mmFMT4_FMT_BIT_DEPTH_CONTROL                                                                   0x19a9
++#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
++#define mmFMT4_FMT_DITHER_RAND_R_SEED                                                                  0x19aa
++#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
++#define mmFMT4_FMT_DITHER_RAND_G_SEED                                                                  0x19ab
++#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
++#define mmFMT4_FMT_DITHER_RAND_B_SEED                                                                  0x19ac
++#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
++#define mmFMT4_FMT_CLAMP_CNTL                                                                          0x19ad
++#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
++#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x19ae
++#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
++#define mmFMT4_FMT_MAP420_MEMORY_CONTROL                                                               0x19af
++#define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
++#define mmFMT4_FMT_422_CONTROL                                                                         0x19b1
++#define mmFMT4_FMT_422_CONTROL_BASE_IDX                                                                2
++
++
++// addressBlock: dce_dc_opp_dpg4_dispdec
++// base address: 0x5a0
++#define mmDPG4_DPG_CONTROL                                                                             0x19bc
++#define mmDPG4_DPG_CONTROL_BASE_IDX                                                                    2
++#define mmDPG4_DPG_RAMP_CONTROL                                                                        0x19bd
++#define mmDPG4_DPG_RAMP_CONTROL_BASE_IDX                                                               2
++#define mmDPG4_DPG_DIMENSIONS                                                                          0x19be
++#define mmDPG4_DPG_DIMENSIONS_BASE_IDX                                                                 2
++#define mmDPG4_DPG_COLOUR_R_CR                                                                         0x19bf
++#define mmDPG4_DPG_COLOUR_R_CR_BASE_IDX                                                                2
++#define mmDPG4_DPG_COLOUR_G_Y                                                                          0x19c0
++#define mmDPG4_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
++#define mmDPG4_DPG_COLOUR_B_CB                                                                         0x19c1
++#define mmDPG4_DPG_COLOUR_B_CB_BASE_IDX                                                                2
++#define mmDPG4_DPG_OFFSET_SEGMENT                                                                      0x19c2
++#define mmDPG4_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
++#define mmDPG4_DPG_STATUS                                                                              0x19c3
++#define mmDPG4_DPG_STATUS_BASE_IDX                                                                     2
++
++
++// addressBlock: dce_dc_opp_oppbuf4_dispdec
++// base address: 0x5a0
++#define mmOPPBUF4_OPPBUF_CONTROL                                                                       0x19ec
++#define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX                                                              2
++#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0                                                               0x19ed
++#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
++#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1                                                               0x19ee
++#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
++#define mmOPPBUF4_OPPBUF_CONTROL1                                                                      0x19f1
++#define mmOPPBUF4_OPPBUF_CONTROL1_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_opp_opp_pipe4_dispdec
++// base address: 0x5a0
++#define mmOPP_PIPE4_OPP_PIPE_CONTROL                                                                   0x19f4
++#define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec
++// base address: 0x5a0
++#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL                                                           0x19f9
++#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
++#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK                                                              0x19fa
++#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
++#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0                                                           0x19fb
++#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
++#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1                                                           0x19fc
++#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
++#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2                                                           0x19fd
++#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
++
++
++// addressBlock: dce_dc_opp_fmt5_dispdec
++// base address: 0x708
++#define mmFMT5_FMT_CLAMP_COMPONENT_R                                                                   0x19fe
++#define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
++#define mmFMT5_FMT_CLAMP_COMPONENT_G                                                                   0x19ff
++#define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
++#define mmFMT5_FMT_CLAMP_COMPONENT_B                                                                   0x1a00
++#define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
++#define mmFMT5_FMT_DYNAMIC_EXP_CNTL                                                                    0x1a01
++#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
++#define mmFMT5_FMT_CONTROL                                                                             0x1a02
++#define mmFMT5_FMT_CONTROL_BASE_IDX                                                                    2
++#define mmFMT5_FMT_BIT_DEPTH_CONTROL                                                                   0x1a03
++#define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
++#define mmFMT5_FMT_DITHER_RAND_R_SEED                                                                  0x1a04
++#define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
++#define mmFMT5_FMT_DITHER_RAND_G_SEED                                                                  0x1a05
++#define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
++#define mmFMT5_FMT_DITHER_RAND_B_SEED                                                                  0x1a06
++#define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
++#define mmFMT5_FMT_CLAMP_CNTL                                                                          0x1a07
++#define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
++#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1a08
++#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
++#define mmFMT5_FMT_MAP420_MEMORY_CONTROL                                                               0x1a09
++#define mmFMT5_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
++#define mmFMT5_FMT_422_CONTROL                                                                         0x1a0b
++#define mmFMT5_FMT_422_CONTROL_BASE_IDX                                                                2
++
++
++// addressBlock: dce_dc_opp_dpg5_dispdec
++// base address: 0x708
++#define mmDPG5_DPG_CONTROL                                                                             0x1a16
++#define mmDPG5_DPG_CONTROL_BASE_IDX                                                                    2
++#define mmDPG5_DPG_RAMP_CONTROL                                                                        0x1a17
++#define mmDPG5_DPG_RAMP_CONTROL_BASE_IDX                                                               2
++#define mmDPG5_DPG_DIMENSIONS                                                                          0x1a18
++#define mmDPG5_DPG_DIMENSIONS_BASE_IDX                                                                 2
++#define mmDPG5_DPG_COLOUR_R_CR                                                                         0x1a19
++#define mmDPG5_DPG_COLOUR_R_CR_BASE_IDX                                                                2
++#define mmDPG5_DPG_COLOUR_G_Y                                                                          0x1a1a
++#define mmDPG5_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
++#define mmDPG5_DPG_COLOUR_B_CB                                                                         0x1a1b
++#define mmDPG5_DPG_COLOUR_B_CB_BASE_IDX                                                                2
++#define mmDPG5_DPG_OFFSET_SEGMENT                                                                      0x1a1c
++#define mmDPG5_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
++#define mmDPG5_DPG_STATUS                                                                              0x1a1d
++#define mmDPG5_DPG_STATUS_BASE_IDX                                                                     2
++
++
++// addressBlock: dce_dc_opp_oppbuf5_dispdec
++// base address: 0x708
++#define mmOPPBUF5_OPPBUF_CONTROL                                                                       0x1a46
++#define mmOPPBUF5_OPPBUF_CONTROL_BASE_IDX                                                              2
++#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0                                                               0x1a47
++#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
++#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1                                                               0x1a48
++#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
++#define mmOPPBUF5_OPPBUF_CONTROL1                                                                      0x1a4b
++#define mmOPPBUF5_OPPBUF_CONTROL1_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_opp_opp_pipe5_dispdec
++// base address: 0x708
++#define mmOPP_PIPE5_OPP_PIPE_CONTROL                                                                   0x1a4e
++#define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec
++// base address: 0x708
++#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL                                                           0x1a53
++#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
++#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK                                                              0x1a54
++#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
++#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0                                                           0x1a55
++#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
++#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1                                                           0x1a56
++#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
++#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2                                                           0x1a57
++#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
++
++
++// addressBlock: dce_dc_opp_opp_top_dispdec
++// base address: 0x0
++#define mmOPP_TOP_CLK_CONTROL                                                                          0x1a5e
++#define mmOPP_TOP_CLK_CONTROL_BASE_IDX                                                                 2
++
++
++// addressBlock: dce_dc_opp_dscrm0_dispdec
++// base address: 0x0
++#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a64
++#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
++
++
++// addressBlock: dce_dc_opp_dscrm1_dispdec
++// base address: 0x4
++#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a65
++#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
++
++
++// addressBlock: dce_dc_opp_dscrm2_dispdec
++// base address: 0x8
++#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a66
++#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
++
++
++// addressBlock: dce_dc_opp_dscrm3_dispdec
++// base address: 0xc
++#define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a67
++#define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
++
++
++// addressBlock: dce_dc_opp_dscrm4_dispdec
++// base address: 0x10
++#define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a68
++#define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
++
++
++// addressBlock: dce_dc_opp_dscrm5_dispdec
++// base address: 0x14
++#define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a69
++#define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
++
++
++// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
++// base address: 0x6af8
++#define mmDC_PERFMON16_PERFCOUNTER_CNTL                                                                0x1abe
++#define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX                                                       2
++#define mmDC_PERFMON16_PERFCOUNTER_CNTL2                                                               0x1abf
++#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
++#define mmDC_PERFMON16_PERFCOUNTER_STATE                                                               0x1ac0
++#define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX                                                      2
++#define mmDC_PERFMON16_PERFMON_CNTL                                                                    0x1ac1
++#define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX                                                           2
++#define mmDC_PERFMON16_PERFMON_CNTL2                                                                   0x1ac2
++#define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX                                                          2
++#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC                                                         0x1ac3
++#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
++#define mmDC_PERFMON16_PERFMON_CVALUE_LOW                                                              0x1ac4
++#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
++#define mmDC_PERFMON16_PERFMON_HI                                                                      0x1ac5
++#define mmDC_PERFMON16_PERFMON_HI_BASE_IDX                                                             2
++#define mmDC_PERFMON16_PERFMON_LOW                                                                     0x1ac6
++#define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_optc_odm0_dispdec
++// base address: 0x0
++#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aca
++#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
++#define mmODM0_OPTC_DATA_SOURCE_SELECT                                                                 0x1acb
++#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
++#define mmODM0_OPTC_DATA_FORMAT_CONTROL                                                                0x1acc
++#define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
++#define mmODM0_OPTC_BYTES_PER_PIXEL                                                                    0x1acd
++#define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
++#define mmODM0_OPTC_WIDTH_CONTROL                                                                      0x1ace
++#define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
++#define mmODM0_OPTC_INPUT_CLOCK_CONTROL                                                                0x1acf
++#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
++#define mmODM0_OPTC_MEMORY_CONFIG                                                                      0x1ad0
++#define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
++#define mmODM0_OPTC_INPUT_SPARE_REGISTER                                                               0x1ad1
++#define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
++
++
++// addressBlock: dce_dc_optc_odm1_dispdec
++// base address: 0x40
++#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1ada
++#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
++#define mmODM1_OPTC_DATA_SOURCE_SELECT                                                                 0x1adb
++#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
++#define mmODM1_OPTC_DATA_FORMAT_CONTROL                                                                0x1adc
++#define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
++#define mmODM1_OPTC_BYTES_PER_PIXEL                                                                    0x1add
++#define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
++#define mmODM1_OPTC_WIDTH_CONTROL                                                                      0x1ade
++#define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
++#define mmODM1_OPTC_INPUT_CLOCK_CONTROL                                                                0x1adf
++#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
++#define mmODM1_OPTC_MEMORY_CONFIG                                                                      0x1ae0
++#define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
++#define mmODM1_OPTC_INPUT_SPARE_REGISTER                                                               0x1ae1
++#define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
++
++
++// addressBlock: dce_dc_optc_odm2_dispdec
++// base address: 0x80
++#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aea
++#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
++#define mmODM2_OPTC_DATA_SOURCE_SELECT                                                                 0x1aeb
++#define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
++#define mmODM2_OPTC_DATA_FORMAT_CONTROL                                                                0x1aec
++#define mmODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
++#define mmODM2_OPTC_BYTES_PER_PIXEL                                                                    0x1aed
++#define mmODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
++#define mmODM2_OPTC_WIDTH_CONTROL                                                                      0x1aee
++#define mmODM2_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
++#define mmODM2_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aef
++#define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
++#define mmODM2_OPTC_MEMORY_CONFIG                                                                      0x1af0
++#define mmODM2_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
++#define mmODM2_OPTC_INPUT_SPARE_REGISTER                                                               0x1af1
++#define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
++
++
++// addressBlock: dce_dc_optc_odm3_dispdec
++// base address: 0xc0
++#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1afa
++#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
++#define mmODM3_OPTC_DATA_SOURCE_SELECT                                                                 0x1afb
++#define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
++#define mmODM3_OPTC_DATA_FORMAT_CONTROL                                                                0x1afc
++#define mmODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
++#define mmODM3_OPTC_BYTES_PER_PIXEL                                                                    0x1afd
++#define mmODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
++#define mmODM3_OPTC_WIDTH_CONTROL                                                                      0x1afe
++#define mmODM3_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
++#define mmODM3_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aff
++#define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
++#define mmODM3_OPTC_MEMORY_CONFIG                                                                      0x1b00
++#define mmODM3_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
++#define mmODM3_OPTC_INPUT_SPARE_REGISTER                                                               0x1b01
++#define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
++
++
++// addressBlock: dce_dc_optc_odm4_dispdec
++// base address: 0x100
++#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1b0a
++#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
++#define mmODM4_OPTC_DATA_SOURCE_SELECT                                                                 0x1b0b
++#define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
++#define mmODM4_OPTC_DATA_FORMAT_CONTROL                                                                0x1b0c
++#define mmODM4_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
++#define mmODM4_OPTC_BYTES_PER_PIXEL                                                                    0x1b0d
++#define mmODM4_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
++#define mmODM4_OPTC_WIDTH_CONTROL                                                                      0x1b0e
++#define mmODM4_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
++#define mmODM4_OPTC_INPUT_CLOCK_CONTROL                                                                0x1b0f
++#define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
++#define mmODM4_OPTC_MEMORY_CONFIG                                                                      0x1b10
++#define mmODM4_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
++#define mmODM4_OPTC_INPUT_SPARE_REGISTER                                                               0x1b11
++#define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
++
++
++// addressBlock: dce_dc_optc_odm5_dispdec
++// base address: 0x140
++#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1b1a
++#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
++#define mmODM5_OPTC_DATA_SOURCE_SELECT                                                                 0x1b1b
++#define mmODM5_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
++#define mmODM5_OPTC_DATA_FORMAT_CONTROL                                                                0x1b1c
++#define mmODM5_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
++#define mmODM5_OPTC_BYTES_PER_PIXEL                                                                    0x1b1d
++#define mmODM5_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
++#define mmODM5_OPTC_WIDTH_CONTROL                                                                      0x1b1e
++#define mmODM5_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
++#define mmODM5_OPTC_INPUT_CLOCK_CONTROL                                                                0x1b1f
++#define mmODM5_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
++#define mmODM5_OPTC_MEMORY_CONFIG                                                                      0x1b20
++#define mmODM5_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
++#define mmODM5_OPTC_INPUT_SPARE_REGISTER                                                               0x1b21
++#define mmODM5_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
++
++
++// addressBlock: dce_dc_optc_otg0_dispdec
++// base address: 0x0
++#define mmOTG0_OTG_H_TOTAL                                                                             0x1b2a
++#define mmOTG0_OTG_H_TOTAL_BASE_IDX                                                                    2
++#define mmOTG0_OTG_H_BLANK_START_END                                                                   0x1b2b
++#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX                                                          2
++#define mmOTG0_OTG_H_SYNC_A                                                                            0x1b2c
++#define mmOTG0_OTG_H_SYNC_A_BASE_IDX                                                                   2
++#define mmOTG0_OTG_H_SYNC_A_CNTL                                                                       0x1b2d
++#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
++#define mmOTG0_OTG_H_TIMING_CNTL                                                                       0x1b2e
++#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
++#define mmOTG0_OTG_V_TOTAL                                                                             0x1b2f
++#define mmOTG0_OTG_V_TOTAL_BASE_IDX                                                                    2
++#define mmOTG0_OTG_V_TOTAL_MIN                                                                         0x1b30
++#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
++#define mmOTG0_OTG_V_TOTAL_MAX                                                                         0x1b31
++#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
++#define mmOTG0_OTG_V_TOTAL_MID                                                                         0x1b32
++#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX                                                                2
++#define mmOTG0_OTG_V_TOTAL_CONTROL                                                                     0x1b33
++#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
++#define mmOTG0_OTG_V_TOTAL_INT_STATUS                                                                  0x1b34
++#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
++#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS                                                                0x1b35
++#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
++#define mmOTG0_OTG_V_BLANK_START_END                                                                   0x1b36
++#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX                                                          2
++#define mmOTG0_OTG_V_SYNC_A                                                                            0x1b37
++#define mmOTG0_OTG_V_SYNC_A_BASE_IDX                                                                   2
++#define mmOTG0_OTG_V_SYNC_A_CNTL                                                                       0x1b38
++#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
++#define mmOTG0_OTG_TRIGA_CNTL                                                                          0x1b39
++#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
++#define mmOTG0_OTG_TRIGA_MANUAL_TRIG                                                                   0x1b3a
++#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
++#define mmOTG0_OTG_TRIGB_CNTL                                                                          0x1b3b
++#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
++#define mmOTG0_OTG_TRIGB_MANUAL_TRIG                                                                   0x1b3c
++#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
++#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1b3d
++#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
++#define mmOTG0_OTG_FLOW_CONTROL                                                                        0x1b3e
++#define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX                                                               2
++#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1b3f
++#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
++#define mmOTG0_OTG_CONTROL                                                                             0x1b41
++#define mmOTG0_OTG_CONTROL_BASE_IDX                                                                    2
++#define mmOTG0_OTG_BLANK_CONTROL                                                                       0x1b42
++#define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX                                                              2
++#define mmOTG0_OTG_PIPE_ABORT_CONTROL                                                                  0x1b43
++#define mmOTG0_OTG_PIPE_ABORT_CONTROL_BASE_IDX                                                         2
++#define mmOTG0_OTG_INTERLACE_CONTROL                                                                   0x1b44
++#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
++#define mmOTG0_OTG_INTERLACE_STATUS                                                                    0x1b45
++#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
++#define mmOTG0_OTG_PIXEL_DATA_READBACK0                                                                0x1b47
++#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
++#define mmOTG0_OTG_PIXEL_DATA_READBACK1                                                                0x1b48
++#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
++#define mmOTG0_OTG_STATUS                                                                              0x1b49
++#define mmOTG0_OTG_STATUS_BASE_IDX                                                                     2
++#define mmOTG0_OTG_STATUS_POSITION                                                                     0x1b4a
++#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX                                                            2
++#define mmOTG0_OTG_NOM_VERT_POSITION                                                                   0x1b4b
++#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
++#define mmOTG0_OTG_STATUS_FRAME_COUNT                                                                  0x1b4c
++#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
++#define mmOTG0_OTG_STATUS_VF_COUNT                                                                     0x1b4d
++#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
++#define mmOTG0_OTG_STATUS_HV_COUNT                                                                     0x1b4e
++#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
++#define mmOTG0_OTG_COUNT_CONTROL                                                                       0x1b4f
++#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX                                                              2
++#define mmOTG0_OTG_COUNT_RESET                                                                         0x1b50
++#define mmOTG0_OTG_COUNT_RESET_BASE_IDX                                                                2
++#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1b51
++#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
++#define mmOTG0_OTG_VERT_SYNC_CONTROL                                                                   0x1b52
++#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
++#define mmOTG0_OTG_STEREO_STATUS                                                                       0x1b53
++#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX                                                              2
++#define mmOTG0_OTG_STEREO_CONTROL                                                                      0x1b54
++#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX                                                             2
++#define mmOTG0_OTG_SNAPSHOT_STATUS                                                                     0x1b55
++#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
++#define mmOTG0_OTG_SNAPSHOT_CONTROL                                                                    0x1b56
++#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
++#define mmOTG0_OTG_SNAPSHOT_POSITION                                                                   0x1b57
++#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
++#define mmOTG0_OTG_SNAPSHOT_FRAME                                                                      0x1b58
++#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
++#define mmOTG0_OTG_INTERRUPT_CONTROL                                                                   0x1b59
++#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
++#define mmOTG0_OTG_UPDATE_LOCK                                                                         0x1b5a
++#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX                                                                2
++#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1b5b
++#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
++#define mmOTG0_OTG_MASTER_EN                                                                           0x1b5c
++#define mmOTG0_OTG_MASTER_EN_BASE_IDX                                                                  2
++#define mmOTG0_OTG_BLANK_DATA_COLOR                                                                    0x1b5e
++#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
++#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT                                                                0x1b5f
++#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
++#define mmOTG0_OTG_BLACK_COLOR                                                                         0x1b60
++#define mmOTG0_OTG_BLACK_COLOR_BASE_IDX                                                                2
++#define mmOTG0_OTG_BLACK_COLOR_EXT                                                                     0x1b61
++#define mmOTG0_OTG_BLACK_COLOR_EXT_BASE_IDX                                                            2
++#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1b62
++#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
++#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1b63
++#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
++#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1b64
++#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
++#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1b65
++#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
++#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1b66
++#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
++#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1b67
++#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
++#define mmOTG0_OTG_CRC_CNTL                                                                            0x1b68
++#define mmOTG0_OTG_CRC_CNTL_BASE_IDX                                                                   2
++#define mmOTG0_OTG_CRC_CNTL2                                                                           0x1b69
++#define mmOTG0_OTG_CRC_CNTL2_BASE_IDX                                                                  2
++#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1b6a
++#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1b6b
++#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1b6c
++#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1b6d
++#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG0_OTG_CRC0_DATA_RG                                                                        0x1b6e
++#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
++#define mmOTG0_OTG_CRC0_DATA_B                                                                         0x1b6f
++#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX                                                                2
++#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1b70
++#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1b71
++#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1b72
++#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1b73
++#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG0_OTG_CRC1_DATA_RG                                                                        0x1b74
++#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
++#define mmOTG0_OTG_CRC1_DATA_B                                                                         0x1b75
++#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX                                                                2
++#define mmOTG0_OTG_CRC2_DATA_RG                                                                        0x1b76
++#define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
++#define mmOTG0_OTG_CRC2_DATA_B                                                                         0x1b77
++#define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX                                                                2
++#define mmOTG0_OTG_CRC3_DATA_RG                                                                        0x1b78
++#define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
++#define mmOTG0_OTG_CRC3_DATA_B                                                                         0x1b79
++#define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX                                                                2
++#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1b7a
++#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
++#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1b7b
++#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
++#define mmOTG0_OTG_STATIC_SCREEN_CONTROL                                                               0x1b82
++#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
++#define mmOTG0_OTG_3D_STRUCTURE_CONTROL                                                                0x1b83
++#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
++#define mmOTG0_OTG_GSL_VSYNC_GAP                                                                       0x1b84
++#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
++#define mmOTG0_OTG_MASTER_UPDATE_MODE                                                                  0x1b85
++#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
++#define mmOTG0_OTG_CLOCK_CONTROL                                                                       0x1b86
++#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
++#define mmOTG0_OTG_VSTARTUP_PARAM                                                                      0x1b87
++#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
++#define mmOTG0_OTG_VUPDATE_PARAM                                                                       0x1b88
++#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
++#define mmOTG0_OTG_VREADY_PARAM                                                                        0x1b89
++#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX                                                               2
++#define mmOTG0_OTG_GLOBAL_SYNC_STATUS                                                                  0x1b8a
++#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
++#define mmOTG0_OTG_MASTER_UPDATE_LOCK                                                                  0x1b8b
++#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
++#define mmOTG0_OTG_GSL_CONTROL                                                                         0x1b8c
++#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX                                                                2
++#define mmOTG0_OTG_GSL_WINDOW_X                                                                        0x1b8d
++#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
++#define mmOTG0_OTG_GSL_WINDOW_Y                                                                        0x1b8e
++#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
++#define mmOTG0_OTG_VUPDATE_KEEPOUT                                                                     0x1b8f
++#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
++#define mmOTG0_OTG_GLOBAL_CONTROL0                                                                     0x1b90
++#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
++#define mmOTG0_OTG_GLOBAL_CONTROL1                                                                     0x1b91
++#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
++#define mmOTG0_OTG_GLOBAL_CONTROL2                                                                     0x1b92
++#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
++#define mmOTG0_OTG_GLOBAL_CONTROL3                                                                     0x1b93
++#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
++#define mmOTG0_OTG_TRIG_MANUAL_CONTROL                                                                 0x1b94
++#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
++#define mmOTG0_OTG_MANUAL_FLOW_CONTROL                                                                 0x1b95
++#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
++#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS                                                             0x1b96
++#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX                                                    2
++#define mmOTG0_OTG_DRR_CONTROL                                                                         0x1b97
++#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX                                                                2
++#define mmOTG0_OTG_REQUEST_CONTROL                                                                     0x1b98
++#define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
++#define mmOTG0_OTG_DSC_START_POSITION                                                                  0x1b99
++#define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX                                                         2
++#define mmOTG0_OTG_PIPE_UPDATE_STATUS                                                                  0x1b9a
++#define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
++#define mmOTG0_OTG_SPARE_REGISTER                                                                      0x1b9c
++#define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_optc_otg1_dispdec
++// base address: 0x200
++#define mmOTG1_OTG_H_TOTAL                                                                             0x1baa
++#define mmOTG1_OTG_H_TOTAL_BASE_IDX                                                                    2
++#define mmOTG1_OTG_H_BLANK_START_END                                                                   0x1bab
++#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX                                                          2
++#define mmOTG1_OTG_H_SYNC_A                                                                            0x1bac
++#define mmOTG1_OTG_H_SYNC_A_BASE_IDX                                                                   2
++#define mmOTG1_OTG_H_SYNC_A_CNTL                                                                       0x1bad
++#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
++#define mmOTG1_OTG_H_TIMING_CNTL                                                                       0x1bae
++#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
++#define mmOTG1_OTG_V_TOTAL                                                                             0x1baf
++#define mmOTG1_OTG_V_TOTAL_BASE_IDX                                                                    2
++#define mmOTG1_OTG_V_TOTAL_MIN                                                                         0x1bb0
++#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
++#define mmOTG1_OTG_V_TOTAL_MAX                                                                         0x1bb1
++#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
++#define mmOTG1_OTG_V_TOTAL_MID                                                                         0x1bb2
++#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX                                                                2
++#define mmOTG1_OTG_V_TOTAL_CONTROL                                                                     0x1bb3
++#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
++#define mmOTG1_OTG_V_TOTAL_INT_STATUS                                                                  0x1bb4
++#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
++#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS                                                                0x1bb5
++#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
++#define mmOTG1_OTG_V_BLANK_START_END                                                                   0x1bb6
++#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX                                                          2
++#define mmOTG1_OTG_V_SYNC_A                                                                            0x1bb7
++#define mmOTG1_OTG_V_SYNC_A_BASE_IDX                                                                   2
++#define mmOTG1_OTG_V_SYNC_A_CNTL                                                                       0x1bb8
++#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
++#define mmOTG1_OTG_TRIGA_CNTL                                                                          0x1bb9
++#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
++#define mmOTG1_OTG_TRIGA_MANUAL_TRIG                                                                   0x1bba
++#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
++#define mmOTG1_OTG_TRIGB_CNTL                                                                          0x1bbb
++#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
++#define mmOTG1_OTG_TRIGB_MANUAL_TRIG                                                                   0x1bbc
++#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
++#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1bbd
++#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
++#define mmOTG1_OTG_FLOW_CONTROL                                                                        0x1bbe
++#define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX                                                               2
++#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1bbf
++#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
++#define mmOTG1_OTG_CONTROL                                                                             0x1bc1
++#define mmOTG1_OTG_CONTROL_BASE_IDX                                                                    2
++#define mmOTG1_OTG_BLANK_CONTROL                                                                       0x1bc2
++#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX                                                              2
++#define mmOTG1_OTG_PIPE_ABORT_CONTROL                                                                  0x1bc3
++#define mmOTG1_OTG_PIPE_ABORT_CONTROL_BASE_IDX                                                         2
++#define mmOTG1_OTG_INTERLACE_CONTROL                                                                   0x1bc4
++#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
++#define mmOTG1_OTG_INTERLACE_STATUS                                                                    0x1bc5
++#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
++#define mmOTG1_OTG_PIXEL_DATA_READBACK0                                                                0x1bc7
++#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
++#define mmOTG1_OTG_PIXEL_DATA_READBACK1                                                                0x1bc8
++#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
++#define mmOTG1_OTG_STATUS                                                                              0x1bc9
++#define mmOTG1_OTG_STATUS_BASE_IDX                                                                     2
++#define mmOTG1_OTG_STATUS_POSITION                                                                     0x1bca
++#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX                                                            2
++#define mmOTG1_OTG_NOM_VERT_POSITION                                                                   0x1bcb
++#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
++#define mmOTG1_OTG_STATUS_FRAME_COUNT                                                                  0x1bcc
++#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
++#define mmOTG1_OTG_STATUS_VF_COUNT                                                                     0x1bcd
++#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
++#define mmOTG1_OTG_STATUS_HV_COUNT                                                                     0x1bce
++#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
++#define mmOTG1_OTG_COUNT_CONTROL                                                                       0x1bcf
++#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX                                                              2
++#define mmOTG1_OTG_COUNT_RESET                                                                         0x1bd0
++#define mmOTG1_OTG_COUNT_RESET_BASE_IDX                                                                2
++#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1bd1
++#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
++#define mmOTG1_OTG_VERT_SYNC_CONTROL                                                                   0x1bd2
++#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
++#define mmOTG1_OTG_STEREO_STATUS                                                                       0x1bd3
++#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX                                                              2
++#define mmOTG1_OTG_STEREO_CONTROL                                                                      0x1bd4
++#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX                                                             2
++#define mmOTG1_OTG_SNAPSHOT_STATUS                                                                     0x1bd5
++#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
++#define mmOTG1_OTG_SNAPSHOT_CONTROL                                                                    0x1bd6
++#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
++#define mmOTG1_OTG_SNAPSHOT_POSITION                                                                   0x1bd7
++#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
++#define mmOTG1_OTG_SNAPSHOT_FRAME                                                                      0x1bd8
++#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
++#define mmOTG1_OTG_INTERRUPT_CONTROL                                                                   0x1bd9
++#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
++#define mmOTG1_OTG_UPDATE_LOCK                                                                         0x1bda
++#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX                                                                2
++#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1bdb
++#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
++#define mmOTG1_OTG_MASTER_EN                                                                           0x1bdc
++#define mmOTG1_OTG_MASTER_EN_BASE_IDX                                                                  2
++#define mmOTG1_OTG_BLANK_DATA_COLOR                                                                    0x1bde
++#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
++#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT                                                                0x1bdf
++#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
++#define mmOTG1_OTG_BLACK_COLOR                                                                         0x1be0
++#define mmOTG1_OTG_BLACK_COLOR_BASE_IDX                                                                2
++#define mmOTG1_OTG_BLACK_COLOR_EXT                                                                     0x1be1
++#define mmOTG1_OTG_BLACK_COLOR_EXT_BASE_IDX                                                            2
++#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1be2
++#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
++#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1be3
++#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
++#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1be4
++#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
++#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1be5
++#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
++#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1be6
++#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
++#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1be7
++#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
++#define mmOTG1_OTG_CRC_CNTL                                                                            0x1be8
++#define mmOTG1_OTG_CRC_CNTL_BASE_IDX                                                                   2
++#define mmOTG1_OTG_CRC_CNTL2                                                                           0x1be9
++#define mmOTG1_OTG_CRC_CNTL2_BASE_IDX                                                                  2
++#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1bea
++#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1beb
++#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1bec
++#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1bed
++#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG1_OTG_CRC0_DATA_RG                                                                        0x1bee
++#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
++#define mmOTG1_OTG_CRC0_DATA_B                                                                         0x1bef
++#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX                                                                2
++#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1bf0
++#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1bf1
++#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1bf2
++#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1bf3
++#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG1_OTG_CRC1_DATA_RG                                                                        0x1bf4
++#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
++#define mmOTG1_OTG_CRC1_DATA_B                                                                         0x1bf5
++#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX                                                                2
++#define mmOTG1_OTG_CRC2_DATA_RG                                                                        0x1bf6
++#define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
++#define mmOTG1_OTG_CRC2_DATA_B                                                                         0x1bf7
++#define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX                                                                2
++#define mmOTG1_OTG_CRC3_DATA_RG                                                                        0x1bf8
++#define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
++#define mmOTG1_OTG_CRC3_DATA_B                                                                         0x1bf9
++#define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX                                                                2
++#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1bfa
++#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
++#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1bfb
++#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
++#define mmOTG1_OTG_STATIC_SCREEN_CONTROL                                                               0x1c02
++#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
++#define mmOTG1_OTG_3D_STRUCTURE_CONTROL                                                                0x1c03
++#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
++#define mmOTG1_OTG_GSL_VSYNC_GAP                                                                       0x1c04
++#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
++#define mmOTG1_OTG_MASTER_UPDATE_MODE                                                                  0x1c05
++#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
++#define mmOTG1_OTG_CLOCK_CONTROL                                                                       0x1c06
++#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
++#define mmOTG1_OTG_VSTARTUP_PARAM                                                                      0x1c07
++#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
++#define mmOTG1_OTG_VUPDATE_PARAM                                                                       0x1c08
++#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
++#define mmOTG1_OTG_VREADY_PARAM                                                                        0x1c09
++#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX                                                               2
++#define mmOTG1_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c0a
++#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
++#define mmOTG1_OTG_MASTER_UPDATE_LOCK                                                                  0x1c0b
++#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
++#define mmOTG1_OTG_GSL_CONTROL                                                                         0x1c0c
++#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX                                                                2
++#define mmOTG1_OTG_GSL_WINDOW_X                                                                        0x1c0d
++#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
++#define mmOTG1_OTG_GSL_WINDOW_Y                                                                        0x1c0e
++#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
++#define mmOTG1_OTG_VUPDATE_KEEPOUT                                                                     0x1c0f
++#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
++#define mmOTG1_OTG_GLOBAL_CONTROL0                                                                     0x1c10
++#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
++#define mmOTG1_OTG_GLOBAL_CONTROL1                                                                     0x1c11
++#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
++#define mmOTG1_OTG_GLOBAL_CONTROL2                                                                     0x1c12
++#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
++#define mmOTG1_OTG_GLOBAL_CONTROL3                                                                     0x1c13
++#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
++#define mmOTG1_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c14
++#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
++#define mmOTG1_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c15
++#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
++#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS                                                             0x1c16
++#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX                                                    2
++#define mmOTG1_OTG_DRR_CONTROL                                                                         0x1c17
++#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX                                                                2
++#define mmOTG1_OTG_REQUEST_CONTROL                                                                     0x1c18
++#define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
++#define mmOTG1_OTG_DSC_START_POSITION                                                                  0x1c19
++#define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX                                                         2
++#define mmOTG1_OTG_PIPE_UPDATE_STATUS                                                                  0x1c1a
++#define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
++#define mmOTG1_OTG_SPARE_REGISTER                                                                      0x1c1c
++#define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_optc_otg2_dispdec
++// base address: 0x400
++#define mmOTG2_OTG_H_TOTAL                                                                             0x1c2a
++#define mmOTG2_OTG_H_TOTAL_BASE_IDX                                                                    2
++#define mmOTG2_OTG_H_BLANK_START_END                                                                   0x1c2b
++#define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX                                                          2
++#define mmOTG2_OTG_H_SYNC_A                                                                            0x1c2c
++#define mmOTG2_OTG_H_SYNC_A_BASE_IDX                                                                   2
++#define mmOTG2_OTG_H_SYNC_A_CNTL                                                                       0x1c2d
++#define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
++#define mmOTG2_OTG_H_TIMING_CNTL                                                                       0x1c2e
++#define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
++#define mmOTG2_OTG_V_TOTAL                                                                             0x1c2f
++#define mmOTG2_OTG_V_TOTAL_BASE_IDX                                                                    2
++#define mmOTG2_OTG_V_TOTAL_MIN                                                                         0x1c30
++#define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
++#define mmOTG2_OTG_V_TOTAL_MAX                                                                         0x1c31
++#define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
++#define mmOTG2_OTG_V_TOTAL_MID                                                                         0x1c32
++#define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX                                                                2
++#define mmOTG2_OTG_V_TOTAL_CONTROL                                                                     0x1c33
++#define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
++#define mmOTG2_OTG_V_TOTAL_INT_STATUS                                                                  0x1c34
++#define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
++#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS                                                                0x1c35
++#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
++#define mmOTG2_OTG_V_BLANK_START_END                                                                   0x1c36
++#define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX                                                          2
++#define mmOTG2_OTG_V_SYNC_A                                                                            0x1c37
++#define mmOTG2_OTG_V_SYNC_A_BASE_IDX                                                                   2
++#define mmOTG2_OTG_V_SYNC_A_CNTL                                                                       0x1c38
++#define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
++#define mmOTG2_OTG_TRIGA_CNTL                                                                          0x1c39
++#define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
++#define mmOTG2_OTG_TRIGA_MANUAL_TRIG                                                                   0x1c3a
++#define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
++#define mmOTG2_OTG_TRIGB_CNTL                                                                          0x1c3b
++#define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
++#define mmOTG2_OTG_TRIGB_MANUAL_TRIG                                                                   0x1c3c
++#define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
++#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1c3d
++#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
++#define mmOTG2_OTG_FLOW_CONTROL                                                                        0x1c3e
++#define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX                                                               2
++#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1c3f
++#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
++#define mmOTG2_OTG_CONTROL                                                                             0x1c41
++#define mmOTG2_OTG_CONTROL_BASE_IDX                                                                    2
++#define mmOTG2_OTG_BLANK_CONTROL                                                                       0x1c42
++#define mmOTG2_OTG_BLANK_CONTROL_BASE_IDX                                                              2
++#define mmOTG2_OTG_PIPE_ABORT_CONTROL                                                                  0x1c43
++#define mmOTG2_OTG_PIPE_ABORT_CONTROL_BASE_IDX                                                         2
++#define mmOTG2_OTG_INTERLACE_CONTROL                                                                   0x1c44
++#define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
++#define mmOTG2_OTG_INTERLACE_STATUS                                                                    0x1c45
++#define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
++#define mmOTG2_OTG_PIXEL_DATA_READBACK0                                                                0x1c47
++#define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
++#define mmOTG2_OTG_PIXEL_DATA_READBACK1                                                                0x1c48
++#define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
++#define mmOTG2_OTG_STATUS                                                                              0x1c49
++#define mmOTG2_OTG_STATUS_BASE_IDX                                                                     2
++#define mmOTG2_OTG_STATUS_POSITION                                                                     0x1c4a
++#define mmOTG2_OTG_STATUS_POSITION_BASE_IDX                                                            2
++#define mmOTG2_OTG_NOM_VERT_POSITION                                                                   0x1c4b
++#define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
++#define mmOTG2_OTG_STATUS_FRAME_COUNT                                                                  0x1c4c
++#define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
++#define mmOTG2_OTG_STATUS_VF_COUNT                                                                     0x1c4d
++#define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
++#define mmOTG2_OTG_STATUS_HV_COUNT                                                                     0x1c4e
++#define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
++#define mmOTG2_OTG_COUNT_CONTROL                                                                       0x1c4f
++#define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX                                                              2
++#define mmOTG2_OTG_COUNT_RESET                                                                         0x1c50
++#define mmOTG2_OTG_COUNT_RESET_BASE_IDX                                                                2
++#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1c51
++#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
++#define mmOTG2_OTG_VERT_SYNC_CONTROL                                                                   0x1c52
++#define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
++#define mmOTG2_OTG_STEREO_STATUS                                                                       0x1c53
++#define mmOTG2_OTG_STEREO_STATUS_BASE_IDX                                                              2
++#define mmOTG2_OTG_STEREO_CONTROL                                                                      0x1c54
++#define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX                                                             2
++#define mmOTG2_OTG_SNAPSHOT_STATUS                                                                     0x1c55
++#define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
++#define mmOTG2_OTG_SNAPSHOT_CONTROL                                                                    0x1c56
++#define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
++#define mmOTG2_OTG_SNAPSHOT_POSITION                                                                   0x1c57
++#define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
++#define mmOTG2_OTG_SNAPSHOT_FRAME                                                                      0x1c58
++#define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
++#define mmOTG2_OTG_INTERRUPT_CONTROL                                                                   0x1c59
++#define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
++#define mmOTG2_OTG_UPDATE_LOCK                                                                         0x1c5a
++#define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX                                                                2
++#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1c5b
++#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
++#define mmOTG2_OTG_MASTER_EN                                                                           0x1c5c
++#define mmOTG2_OTG_MASTER_EN_BASE_IDX                                                                  2
++#define mmOTG2_OTG_BLANK_DATA_COLOR                                                                    0x1c5e
++#define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
++#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT                                                                0x1c5f
++#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
++#define mmOTG2_OTG_BLACK_COLOR                                                                         0x1c60
++#define mmOTG2_OTG_BLACK_COLOR_BASE_IDX                                                                2
++#define mmOTG2_OTG_BLACK_COLOR_EXT                                                                     0x1c61
++#define mmOTG2_OTG_BLACK_COLOR_EXT_BASE_IDX                                                            2
++#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1c62
++#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
++#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1c63
++#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
++#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1c64
++#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
++#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1c65
++#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
++#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1c66
++#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
++#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1c67
++#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
++#define mmOTG2_OTG_CRC_CNTL                                                                            0x1c68
++#define mmOTG2_OTG_CRC_CNTL_BASE_IDX                                                                   2
++#define mmOTG2_OTG_CRC_CNTL2                                                                           0x1c69
++#define mmOTG2_OTG_CRC_CNTL2_BASE_IDX                                                                  2
++#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1c6a
++#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1c6b
++#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1c6c
++#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1c6d
++#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG2_OTG_CRC0_DATA_RG                                                                        0x1c6e
++#define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
++#define mmOTG2_OTG_CRC0_DATA_B                                                                         0x1c6f
++#define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX                                                                2
++#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1c70
++#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1c71
++#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1c72
++#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1c73
++#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG2_OTG_CRC1_DATA_RG                                                                        0x1c74
++#define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
++#define mmOTG2_OTG_CRC1_DATA_B                                                                         0x1c75
++#define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX                                                                2
++#define mmOTG2_OTG_CRC2_DATA_RG                                                                        0x1c76
++#define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
++#define mmOTG2_OTG_CRC2_DATA_B                                                                         0x1c77
++#define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX                                                                2
++#define mmOTG2_OTG_CRC3_DATA_RG                                                                        0x1c78
++#define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
++#define mmOTG2_OTG_CRC3_DATA_B                                                                         0x1c79
++#define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX                                                                2
++#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1c7a
++#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
++#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1c7b
++#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
++#define mmOTG2_OTG_STATIC_SCREEN_CONTROL                                                               0x1c82
++#define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
++#define mmOTG2_OTG_3D_STRUCTURE_CONTROL                                                                0x1c83
++#define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
++#define mmOTG2_OTG_GSL_VSYNC_GAP                                                                       0x1c84
++#define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
++#define mmOTG2_OTG_MASTER_UPDATE_MODE                                                                  0x1c85
++#define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
++#define mmOTG2_OTG_CLOCK_CONTROL                                                                       0x1c86
++#define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
++#define mmOTG2_OTG_VSTARTUP_PARAM                                                                      0x1c87
++#define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
++#define mmOTG2_OTG_VUPDATE_PARAM                                                                       0x1c88
++#define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
++#define mmOTG2_OTG_VREADY_PARAM                                                                        0x1c89
++#define mmOTG2_OTG_VREADY_PARAM_BASE_IDX                                                               2
++#define mmOTG2_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c8a
++#define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
++#define mmOTG2_OTG_MASTER_UPDATE_LOCK                                                                  0x1c8b
++#define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
++#define mmOTG2_OTG_GSL_CONTROL                                                                         0x1c8c
++#define mmOTG2_OTG_GSL_CONTROL_BASE_IDX                                                                2
++#define mmOTG2_OTG_GSL_WINDOW_X                                                                        0x1c8d
++#define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
++#define mmOTG2_OTG_GSL_WINDOW_Y                                                                        0x1c8e
++#define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
++#define mmOTG2_OTG_VUPDATE_KEEPOUT                                                                     0x1c8f
++#define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
++#define mmOTG2_OTG_GLOBAL_CONTROL0                                                                     0x1c90
++#define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
++#define mmOTG2_OTG_GLOBAL_CONTROL1                                                                     0x1c91
++#define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
++#define mmOTG2_OTG_GLOBAL_CONTROL2                                                                     0x1c92
++#define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
++#define mmOTG2_OTG_GLOBAL_CONTROL3                                                                     0x1c93
++#define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
++#define mmOTG2_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c94
++#define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
++#define mmOTG2_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c95
++#define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
++#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS                                                             0x1c96
++#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX                                                    2
++#define mmOTG2_OTG_DRR_CONTROL                                                                         0x1c97
++#define mmOTG2_OTG_DRR_CONTROL_BASE_IDX                                                                2
++#define mmOTG2_OTG_REQUEST_CONTROL                                                                     0x1c98
++#define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
++#define mmOTG2_OTG_DSC_START_POSITION                                                                  0x1c99
++#define mmOTG2_OTG_DSC_START_POSITION_BASE_IDX                                                         2
++#define mmOTG2_OTG_PIPE_UPDATE_STATUS                                                                  0x1c9a
++#define mmOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
++#define mmOTG2_OTG_SPARE_REGISTER                                                                      0x1c9c
++#define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_optc_otg3_dispdec
++// base address: 0x600
++#define mmOTG3_OTG_H_TOTAL                                                                             0x1caa
++#define mmOTG3_OTG_H_TOTAL_BASE_IDX                                                                    2
++#define mmOTG3_OTG_H_BLANK_START_END                                                                   0x1cab
++#define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX                                                          2
++#define mmOTG3_OTG_H_SYNC_A                                                                            0x1cac
++#define mmOTG3_OTG_H_SYNC_A_BASE_IDX                                                                   2
++#define mmOTG3_OTG_H_SYNC_A_CNTL                                                                       0x1cad
++#define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
++#define mmOTG3_OTG_H_TIMING_CNTL                                                                       0x1cae
++#define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
++#define mmOTG3_OTG_V_TOTAL                                                                             0x1caf
++#define mmOTG3_OTG_V_TOTAL_BASE_IDX                                                                    2
++#define mmOTG3_OTG_V_TOTAL_MIN                                                                         0x1cb0
++#define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
++#define mmOTG3_OTG_V_TOTAL_MAX                                                                         0x1cb1
++#define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
++#define mmOTG3_OTG_V_TOTAL_MID                                                                         0x1cb2
++#define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX                                                                2
++#define mmOTG3_OTG_V_TOTAL_CONTROL                                                                     0x1cb3
++#define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
++#define mmOTG3_OTG_V_TOTAL_INT_STATUS                                                                  0x1cb4
++#define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
++#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS                                                                0x1cb5
++#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
++#define mmOTG3_OTG_V_BLANK_START_END                                                                   0x1cb6
++#define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX                                                          2
++#define mmOTG3_OTG_V_SYNC_A                                                                            0x1cb7
++#define mmOTG3_OTG_V_SYNC_A_BASE_IDX                                                                   2
++#define mmOTG3_OTG_V_SYNC_A_CNTL                                                                       0x1cb8
++#define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
++#define mmOTG3_OTG_TRIGA_CNTL                                                                          0x1cb9
++#define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
++#define mmOTG3_OTG_TRIGA_MANUAL_TRIG                                                                   0x1cba
++#define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
++#define mmOTG3_OTG_TRIGB_CNTL                                                                          0x1cbb
++#define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
++#define mmOTG3_OTG_TRIGB_MANUAL_TRIG                                                                   0x1cbc
++#define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
++#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1cbd
++#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
++#define mmOTG3_OTG_FLOW_CONTROL                                                                        0x1cbe
++#define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX                                                               2
++#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1cbf
++#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
++#define mmOTG3_OTG_CONTROL                                                                             0x1cc1
++#define mmOTG3_OTG_CONTROL_BASE_IDX                                                                    2
++#define mmOTG3_OTG_BLANK_CONTROL                                                                       0x1cc2
++#define mmOTG3_OTG_BLANK_CONTROL_BASE_IDX                                                              2
++#define mmOTG3_OTG_PIPE_ABORT_CONTROL                                                                  0x1cc3
++#define mmOTG3_OTG_PIPE_ABORT_CONTROL_BASE_IDX                                                         2
++#define mmOTG3_OTG_INTERLACE_CONTROL                                                                   0x1cc4
++#define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
++#define mmOTG3_OTG_INTERLACE_STATUS                                                                    0x1cc5
++#define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
++#define mmOTG3_OTG_PIXEL_DATA_READBACK0                                                                0x1cc7
++#define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
++#define mmOTG3_OTG_PIXEL_DATA_READBACK1                                                                0x1cc8
++#define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
++#define mmOTG3_OTG_STATUS                                                                              0x1cc9
++#define mmOTG3_OTG_STATUS_BASE_IDX                                                                     2
++#define mmOTG3_OTG_STATUS_POSITION                                                                     0x1cca
++#define mmOTG3_OTG_STATUS_POSITION_BASE_IDX                                                            2
++#define mmOTG3_OTG_NOM_VERT_POSITION                                                                   0x1ccb
++#define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
++#define mmOTG3_OTG_STATUS_FRAME_COUNT                                                                  0x1ccc
++#define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
++#define mmOTG3_OTG_STATUS_VF_COUNT                                                                     0x1ccd
++#define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
++#define mmOTG3_OTG_STATUS_HV_COUNT                                                                     0x1cce
++#define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
++#define mmOTG3_OTG_COUNT_CONTROL                                                                       0x1ccf
++#define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX                                                              2
++#define mmOTG3_OTG_COUNT_RESET                                                                         0x1cd0
++#define mmOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2
++#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1cd1
++#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
++#define mmOTG3_OTG_VERT_SYNC_CONTROL                                                                   0x1cd2
++#define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
++#define mmOTG3_OTG_STEREO_STATUS                                                                       0x1cd3
++#define mmOTG3_OTG_STEREO_STATUS_BASE_IDX                                                              2
++#define mmOTG3_OTG_STEREO_CONTROL                                                                      0x1cd4
++#define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX                                                             2
++#define mmOTG3_OTG_SNAPSHOT_STATUS                                                                     0x1cd5
++#define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
++#define mmOTG3_OTG_SNAPSHOT_CONTROL                                                                    0x1cd6
++#define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
++#define mmOTG3_OTG_SNAPSHOT_POSITION                                                                   0x1cd7
++#define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
++#define mmOTG3_OTG_SNAPSHOT_FRAME                                                                      0x1cd8
++#define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
++#define mmOTG3_OTG_INTERRUPT_CONTROL                                                                   0x1cd9
++#define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
++#define mmOTG3_OTG_UPDATE_LOCK                                                                         0x1cda
++#define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX                                                                2
++#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1cdb
++#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
++#define mmOTG3_OTG_MASTER_EN                                                                           0x1cdc
++#define mmOTG3_OTG_MASTER_EN_BASE_IDX                                                                  2
++#define mmOTG3_OTG_BLANK_DATA_COLOR                                                                    0x1cde
++#define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
++#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT                                                                0x1cdf
++#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
++#define mmOTG3_OTG_BLACK_COLOR                                                                         0x1ce0
++#define mmOTG3_OTG_BLACK_COLOR_BASE_IDX                                                                2
++#define mmOTG3_OTG_BLACK_COLOR_EXT                                                                     0x1ce1
++#define mmOTG3_OTG_BLACK_COLOR_EXT_BASE_IDX                                                            2
++#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1ce2
++#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
++#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1ce3
++#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
++#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1ce4
++#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
++#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1ce5
++#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
++#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1ce6
++#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
++#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1ce7
++#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
++#define mmOTG3_OTG_CRC_CNTL                                                                            0x1ce8
++#define mmOTG3_OTG_CRC_CNTL_BASE_IDX                                                                   2
++#define mmOTG3_OTG_CRC_CNTL2                                                                           0x1ce9
++#define mmOTG3_OTG_CRC_CNTL2_BASE_IDX                                                                  2
++#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1cea
++#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1ceb
++#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1cec
++#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1ced
++#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG3_OTG_CRC0_DATA_RG                                                                        0x1cee
++#define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
++#define mmOTG3_OTG_CRC0_DATA_B                                                                         0x1cef
++#define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX                                                                2
++#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1cf0
++#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1cf1
++#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1cf2
++#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1cf3
++#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG3_OTG_CRC1_DATA_RG                                                                        0x1cf4
++#define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
++#define mmOTG3_OTG_CRC1_DATA_B                                                                         0x1cf5
++#define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX                                                                2
++#define mmOTG3_OTG_CRC2_DATA_RG                                                                        0x1cf6
++#define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
++#define mmOTG3_OTG_CRC2_DATA_B                                                                         0x1cf7
++#define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX                                                                2
++#define mmOTG3_OTG_CRC3_DATA_RG                                                                        0x1cf8
++#define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
++#define mmOTG3_OTG_CRC3_DATA_B                                                                         0x1cf9
++#define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX                                                                2
++#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1cfa
++#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
++#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1cfb
++#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
++#define mmOTG3_OTG_STATIC_SCREEN_CONTROL                                                               0x1d02
++#define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
++#define mmOTG3_OTG_3D_STRUCTURE_CONTROL                                                                0x1d03
++#define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
++#define mmOTG3_OTG_GSL_VSYNC_GAP                                                                       0x1d04
++#define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
++#define mmOTG3_OTG_MASTER_UPDATE_MODE                                                                  0x1d05
++#define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
++#define mmOTG3_OTG_CLOCK_CONTROL                                                                       0x1d06
++#define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
++#define mmOTG3_OTG_VSTARTUP_PARAM                                                                      0x1d07
++#define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
++#define mmOTG3_OTG_VUPDATE_PARAM                                                                       0x1d08
++#define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
++#define mmOTG3_OTG_VREADY_PARAM                                                                        0x1d09
++#define mmOTG3_OTG_VREADY_PARAM_BASE_IDX                                                               2
++#define mmOTG3_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d0a
++#define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
++#define mmOTG3_OTG_MASTER_UPDATE_LOCK                                                                  0x1d0b
++#define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
++#define mmOTG3_OTG_GSL_CONTROL                                                                         0x1d0c
++#define mmOTG3_OTG_GSL_CONTROL_BASE_IDX                                                                2
++#define mmOTG3_OTG_GSL_WINDOW_X                                                                        0x1d0d
++#define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
++#define mmOTG3_OTG_GSL_WINDOW_Y                                                                        0x1d0e
++#define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
++#define mmOTG3_OTG_VUPDATE_KEEPOUT                                                                     0x1d0f
++#define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
++#define mmOTG3_OTG_GLOBAL_CONTROL0                                                                     0x1d10
++#define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
++#define mmOTG3_OTG_GLOBAL_CONTROL1                                                                     0x1d11
++#define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
++#define mmOTG3_OTG_GLOBAL_CONTROL2                                                                     0x1d12
++#define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
++#define mmOTG3_OTG_GLOBAL_CONTROL3                                                                     0x1d13
++#define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
++#define mmOTG3_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d14
++#define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
++#define mmOTG3_OTG_MANUAL_FLOW_CONTROL                                                                 0x1d15
++#define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
++#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS                                                             0x1d16
++#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX                                                    2
++#define mmOTG3_OTG_DRR_CONTROL                                                                         0x1d17
++#define mmOTG3_OTG_DRR_CONTROL_BASE_IDX                                                                2
++#define mmOTG3_OTG_REQUEST_CONTROL                                                                     0x1d18
++#define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
++#define mmOTG3_OTG_DSC_START_POSITION                                                                  0x1d19
++#define mmOTG3_OTG_DSC_START_POSITION_BASE_IDX                                                         2
++#define mmOTG3_OTG_PIPE_UPDATE_STATUS                                                                  0x1d1a
++#define mmOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
++#define mmOTG3_OTG_SPARE_REGISTER                                                                      0x1d1c
++#define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_optc_otg4_dispdec
++// base address: 0x800
++#define mmOTG4_OTG_H_TOTAL                                                                             0x1d2a
++#define mmOTG4_OTG_H_TOTAL_BASE_IDX                                                                    2
++#define mmOTG4_OTG_H_BLANK_START_END                                                                   0x1d2b
++#define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX                                                          2
++#define mmOTG4_OTG_H_SYNC_A                                                                            0x1d2c
++#define mmOTG4_OTG_H_SYNC_A_BASE_IDX                                                                   2
++#define mmOTG4_OTG_H_SYNC_A_CNTL                                                                       0x1d2d
++#define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
++#define mmOTG4_OTG_H_TIMING_CNTL                                                                       0x1d2e
++#define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
++#define mmOTG4_OTG_V_TOTAL                                                                             0x1d2f
++#define mmOTG4_OTG_V_TOTAL_BASE_IDX                                                                    2
++#define mmOTG4_OTG_V_TOTAL_MIN                                                                         0x1d30
++#define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
++#define mmOTG4_OTG_V_TOTAL_MAX                                                                         0x1d31
++#define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
++#define mmOTG4_OTG_V_TOTAL_MID                                                                         0x1d32
++#define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX                                                                2
++#define mmOTG4_OTG_V_TOTAL_CONTROL                                                                     0x1d33
++#define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
++#define mmOTG4_OTG_V_TOTAL_INT_STATUS                                                                  0x1d34
++#define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
++#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS                                                                0x1d35
++#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
++#define mmOTG4_OTG_V_BLANK_START_END                                                                   0x1d36
++#define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX                                                          2
++#define mmOTG4_OTG_V_SYNC_A                                                                            0x1d37
++#define mmOTG4_OTG_V_SYNC_A_BASE_IDX                                                                   2
++#define mmOTG4_OTG_V_SYNC_A_CNTL                                                                       0x1d38
++#define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
++#define mmOTG4_OTG_TRIGA_CNTL                                                                          0x1d39
++#define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
++#define mmOTG4_OTG_TRIGA_MANUAL_TRIG                                                                   0x1d3a
++#define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
++#define mmOTG4_OTG_TRIGB_CNTL                                                                          0x1d3b
++#define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
++#define mmOTG4_OTG_TRIGB_MANUAL_TRIG                                                                   0x1d3c
++#define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
++#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1d3d
++#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
++#define mmOTG4_OTG_FLOW_CONTROL                                                                        0x1d3e
++#define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX                                                               2
++#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1d3f
++#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
++#define mmOTG4_OTG_CONTROL                                                                             0x1d41
++#define mmOTG4_OTG_CONTROL_BASE_IDX                                                                    2
++#define mmOTG4_OTG_BLANK_CONTROL                                                                       0x1d42
++#define mmOTG4_OTG_BLANK_CONTROL_BASE_IDX                                                              2
++#define mmOTG4_OTG_PIPE_ABORT_CONTROL                                                                  0x1d43
++#define mmOTG4_OTG_PIPE_ABORT_CONTROL_BASE_IDX                                                         2
++#define mmOTG4_OTG_INTERLACE_CONTROL                                                                   0x1d44
++#define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
++#define mmOTG4_OTG_INTERLACE_STATUS                                                                    0x1d45
++#define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
++#define mmOTG4_OTG_PIXEL_DATA_READBACK0                                                                0x1d47
++#define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
++#define mmOTG4_OTG_PIXEL_DATA_READBACK1                                                                0x1d48
++#define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
++#define mmOTG4_OTG_STATUS                                                                              0x1d49
++#define mmOTG4_OTG_STATUS_BASE_IDX                                                                     2
++#define mmOTG4_OTG_STATUS_POSITION                                                                     0x1d4a
++#define mmOTG4_OTG_STATUS_POSITION_BASE_IDX                                                            2
++#define mmOTG4_OTG_NOM_VERT_POSITION                                                                   0x1d4b
++#define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
++#define mmOTG4_OTG_STATUS_FRAME_COUNT                                                                  0x1d4c
++#define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
++#define mmOTG4_OTG_STATUS_VF_COUNT                                                                     0x1d4d
++#define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
++#define mmOTG4_OTG_STATUS_HV_COUNT                                                                     0x1d4e
++#define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
++#define mmOTG4_OTG_COUNT_CONTROL                                                                       0x1d4f
++#define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX                                                              2
++#define mmOTG4_OTG_COUNT_RESET                                                                         0x1d50
++#define mmOTG4_OTG_COUNT_RESET_BASE_IDX                                                                2
++#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1d51
++#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
++#define mmOTG4_OTG_VERT_SYNC_CONTROL                                                                   0x1d52
++#define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
++#define mmOTG4_OTG_STEREO_STATUS                                                                       0x1d53
++#define mmOTG4_OTG_STEREO_STATUS_BASE_IDX                                                              2
++#define mmOTG4_OTG_STEREO_CONTROL                                                                      0x1d54
++#define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX                                                             2
++#define mmOTG4_OTG_SNAPSHOT_STATUS                                                                     0x1d55
++#define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
++#define mmOTG4_OTG_SNAPSHOT_CONTROL                                                                    0x1d56
++#define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
++#define mmOTG4_OTG_SNAPSHOT_POSITION                                                                   0x1d57
++#define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
++#define mmOTG4_OTG_SNAPSHOT_FRAME                                                                      0x1d58
++#define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
++#define mmOTG4_OTG_INTERRUPT_CONTROL                                                                   0x1d59
++#define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
++#define mmOTG4_OTG_UPDATE_LOCK                                                                         0x1d5a
++#define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX                                                                2
++#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1d5b
++#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
++#define mmOTG4_OTG_MASTER_EN                                                                           0x1d5c
++#define mmOTG4_OTG_MASTER_EN_BASE_IDX                                                                  2
++#define mmOTG4_OTG_BLANK_DATA_COLOR                                                                    0x1d5e
++#define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
++#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT                                                                0x1d5f
++#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
++#define mmOTG4_OTG_BLACK_COLOR                                                                         0x1d60
++#define mmOTG4_OTG_BLACK_COLOR_BASE_IDX                                                                2
++#define mmOTG4_OTG_BLACK_COLOR_EXT                                                                     0x1d61
++#define mmOTG4_OTG_BLACK_COLOR_EXT_BASE_IDX                                                            2
++#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1d62
++#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
++#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1d63
++#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
++#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1d64
++#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
++#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1d65
++#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
++#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1d66
++#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
++#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1d67
++#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
++#define mmOTG4_OTG_CRC_CNTL                                                                            0x1d68
++#define mmOTG4_OTG_CRC_CNTL_BASE_IDX                                                                   2
++#define mmOTG4_OTG_CRC_CNTL2                                                                           0x1d69
++#define mmOTG4_OTG_CRC_CNTL2_BASE_IDX                                                                  2
++#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1d6a
++#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1d6b
++#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1d6c
++#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1d6d
++#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG4_OTG_CRC0_DATA_RG                                                                        0x1d6e
++#define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
++#define mmOTG4_OTG_CRC0_DATA_B                                                                         0x1d6f
++#define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX                                                                2
++#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1d70
++#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1d71
++#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1d72
++#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1d73
++#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG4_OTG_CRC1_DATA_RG                                                                        0x1d74
++#define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
++#define mmOTG4_OTG_CRC1_DATA_B                                                                         0x1d75
++#define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX                                                                2
++#define mmOTG4_OTG_CRC2_DATA_RG                                                                        0x1d76
++#define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
++#define mmOTG4_OTG_CRC2_DATA_B                                                                         0x1d77
++#define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX                                                                2
++#define mmOTG4_OTG_CRC3_DATA_RG                                                                        0x1d78
++#define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
++#define mmOTG4_OTG_CRC3_DATA_B                                                                         0x1d79
++#define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX                                                                2
++#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1d7a
++#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
++#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1d7b
++#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
++#define mmOTG4_OTG_STATIC_SCREEN_CONTROL                                                               0x1d82
++#define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
++#define mmOTG4_OTG_3D_STRUCTURE_CONTROL                                                                0x1d83
++#define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
++#define mmOTG4_OTG_GSL_VSYNC_GAP                                                                       0x1d84
++#define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
++#define mmOTG4_OTG_MASTER_UPDATE_MODE                                                                  0x1d85
++#define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
++#define mmOTG4_OTG_CLOCK_CONTROL                                                                       0x1d86
++#define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
++#define mmOTG4_OTG_VSTARTUP_PARAM                                                                      0x1d87
++#define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
++#define mmOTG4_OTG_VUPDATE_PARAM                                                                       0x1d88
++#define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
++#define mmOTG4_OTG_VREADY_PARAM                                                                        0x1d89
++#define mmOTG4_OTG_VREADY_PARAM_BASE_IDX                                                               2
++#define mmOTG4_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d8a
++#define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
++#define mmOTG4_OTG_MASTER_UPDATE_LOCK                                                                  0x1d8b
++#define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
++#define mmOTG4_OTG_GSL_CONTROL                                                                         0x1d8c
++#define mmOTG4_OTG_GSL_CONTROL_BASE_IDX                                                                2
++#define mmOTG4_OTG_GSL_WINDOW_X                                                                        0x1d8d
++#define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
++#define mmOTG4_OTG_GSL_WINDOW_Y                                                                        0x1d8e
++#define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
++#define mmOTG4_OTG_VUPDATE_KEEPOUT                                                                     0x1d8f
++#define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
++#define mmOTG4_OTG_GLOBAL_CONTROL0                                                                     0x1d90
++#define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
++#define mmOTG4_OTG_GLOBAL_CONTROL1                                                                     0x1d91
++#define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
++#define mmOTG4_OTG_GLOBAL_CONTROL2                                                                     0x1d92
++#define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
++#define mmOTG4_OTG_GLOBAL_CONTROL3                                                                     0x1d93
++#define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
++#define mmOTG4_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d94
++#define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
++#define mmOTG4_OTG_MANUAL_FLOW_CONTROL                                                                 0x1d95
++#define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
++#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS                                                             0x1d96
++#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX                                                    2
++#define mmOTG4_OTG_DRR_CONTROL                                                                         0x1d97
++#define mmOTG4_OTG_DRR_CONTROL_BASE_IDX                                                                2
++#define mmOTG4_OTG_REQUEST_CONTROL                                                                     0x1d98
++#define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
++#define mmOTG4_OTG_DSC_START_POSITION                                                                  0x1d99
++#define mmOTG4_OTG_DSC_START_POSITION_BASE_IDX                                                         2
++#define mmOTG4_OTG_PIPE_UPDATE_STATUS                                                                  0x1d9a
++#define mmOTG4_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
++#define mmOTG4_OTG_SPARE_REGISTER                                                                      0x1d9c
++#define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_optc_otg5_dispdec
++// base address: 0xa00
++#define mmOTG5_OTG_H_TOTAL                                                                             0x1daa
++#define mmOTG5_OTG_H_TOTAL_BASE_IDX                                                                    2
++#define mmOTG5_OTG_H_BLANK_START_END                                                                   0x1dab
++#define mmOTG5_OTG_H_BLANK_START_END_BASE_IDX                                                          2
++#define mmOTG5_OTG_H_SYNC_A                                                                            0x1dac
++#define mmOTG5_OTG_H_SYNC_A_BASE_IDX                                                                   2
++#define mmOTG5_OTG_H_SYNC_A_CNTL                                                                       0x1dad
++#define mmOTG5_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
++#define mmOTG5_OTG_H_TIMING_CNTL                                                                       0x1dae
++#define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
++#define mmOTG5_OTG_V_TOTAL                                                                             0x1daf
++#define mmOTG5_OTG_V_TOTAL_BASE_IDX                                                                    2
++#define mmOTG5_OTG_V_TOTAL_MIN                                                                         0x1db0
++#define mmOTG5_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
++#define mmOTG5_OTG_V_TOTAL_MAX                                                                         0x1db1
++#define mmOTG5_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
++#define mmOTG5_OTG_V_TOTAL_MID                                                                         0x1db2
++#define mmOTG5_OTG_V_TOTAL_MID_BASE_IDX                                                                2
++#define mmOTG5_OTG_V_TOTAL_CONTROL                                                                     0x1db3
++#define mmOTG5_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
++#define mmOTG5_OTG_V_TOTAL_INT_STATUS                                                                  0x1db4
++#define mmOTG5_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
++#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS                                                                0x1db5
++#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
++#define mmOTG5_OTG_V_BLANK_START_END                                                                   0x1db6
++#define mmOTG5_OTG_V_BLANK_START_END_BASE_IDX                                                          2
++#define mmOTG5_OTG_V_SYNC_A                                                                            0x1db7
++#define mmOTG5_OTG_V_SYNC_A_BASE_IDX                                                                   2
++#define mmOTG5_OTG_V_SYNC_A_CNTL                                                                       0x1db8
++#define mmOTG5_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
++#define mmOTG5_OTG_TRIGA_CNTL                                                                          0x1db9
++#define mmOTG5_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
++#define mmOTG5_OTG_TRIGA_MANUAL_TRIG                                                                   0x1dba
++#define mmOTG5_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
++#define mmOTG5_OTG_TRIGB_CNTL                                                                          0x1dbb
++#define mmOTG5_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
++#define mmOTG5_OTG_TRIGB_MANUAL_TRIG                                                                   0x1dbc
++#define mmOTG5_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
++#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1dbd
++#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
++#define mmOTG5_OTG_FLOW_CONTROL                                                                        0x1dbe
++#define mmOTG5_OTG_FLOW_CONTROL_BASE_IDX                                                               2
++#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1dbf
++#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
++#define mmOTG5_OTG_CONTROL                                                                             0x1dc1
++#define mmOTG5_OTG_CONTROL_BASE_IDX                                                                    2
++#define mmOTG5_OTG_BLANK_CONTROL                                                                       0x1dc2
++#define mmOTG5_OTG_BLANK_CONTROL_BASE_IDX                                                              2
++#define mmOTG5_OTG_PIPE_ABORT_CONTROL                                                                  0x1dc3
++#define mmOTG5_OTG_PIPE_ABORT_CONTROL_BASE_IDX                                                         2
++#define mmOTG5_OTG_INTERLACE_CONTROL                                                                   0x1dc4
++#define mmOTG5_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
++#define mmOTG5_OTG_INTERLACE_STATUS                                                                    0x1dc5
++#define mmOTG5_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
++#define mmOTG5_OTG_PIXEL_DATA_READBACK0                                                                0x1dc7
++#define mmOTG5_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
++#define mmOTG5_OTG_PIXEL_DATA_READBACK1                                                                0x1dc8
++#define mmOTG5_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
++#define mmOTG5_OTG_STATUS                                                                              0x1dc9
++#define mmOTG5_OTG_STATUS_BASE_IDX                                                                     2
++#define mmOTG5_OTG_STATUS_POSITION                                                                     0x1dca
++#define mmOTG5_OTG_STATUS_POSITION_BASE_IDX                                                            2
++#define mmOTG5_OTG_NOM_VERT_POSITION                                                                   0x1dcb
++#define mmOTG5_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
++#define mmOTG5_OTG_STATUS_FRAME_COUNT                                                                  0x1dcc
++#define mmOTG5_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
++#define mmOTG5_OTG_STATUS_VF_COUNT                                                                     0x1dcd
++#define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
++#define mmOTG5_OTG_STATUS_HV_COUNT                                                                     0x1dce
++#define mmOTG5_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
++#define mmOTG5_OTG_COUNT_CONTROL                                                                       0x1dcf
++#define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX                                                              2
++#define mmOTG5_OTG_COUNT_RESET                                                                         0x1dd0
++#define mmOTG5_OTG_COUNT_RESET_BASE_IDX                                                                2
++#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1dd1
++#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
++#define mmOTG5_OTG_VERT_SYNC_CONTROL                                                                   0x1dd2
++#define mmOTG5_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
++#define mmOTG5_OTG_STEREO_STATUS                                                                       0x1dd3
++#define mmOTG5_OTG_STEREO_STATUS_BASE_IDX                                                              2
++#define mmOTG5_OTG_STEREO_CONTROL                                                                      0x1dd4
++#define mmOTG5_OTG_STEREO_CONTROL_BASE_IDX                                                             2
++#define mmOTG5_OTG_SNAPSHOT_STATUS                                                                     0x1dd5
++#define mmOTG5_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
++#define mmOTG5_OTG_SNAPSHOT_CONTROL                                                                    0x1dd6
++#define mmOTG5_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
++#define mmOTG5_OTG_SNAPSHOT_POSITION                                                                   0x1dd7
++#define mmOTG5_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
++#define mmOTG5_OTG_SNAPSHOT_FRAME                                                                      0x1dd8
++#define mmOTG5_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
++#define mmOTG5_OTG_INTERRUPT_CONTROL                                                                   0x1dd9
++#define mmOTG5_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
++#define mmOTG5_OTG_UPDATE_LOCK                                                                         0x1dda
++#define mmOTG5_OTG_UPDATE_LOCK_BASE_IDX                                                                2
++#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1ddb
++#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
++#define mmOTG5_OTG_MASTER_EN                                                                           0x1ddc
++#define mmOTG5_OTG_MASTER_EN_BASE_IDX                                                                  2
++#define mmOTG5_OTG_BLANK_DATA_COLOR                                                                    0x1dde
++#define mmOTG5_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
++#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT                                                                0x1ddf
++#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
++#define mmOTG5_OTG_BLACK_COLOR                                                                         0x1de0
++#define mmOTG5_OTG_BLACK_COLOR_BASE_IDX                                                                2
++#define mmOTG5_OTG_BLACK_COLOR_EXT                                                                     0x1de1
++#define mmOTG5_OTG_BLACK_COLOR_EXT_BASE_IDX                                                            2
++#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1de2
++#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
++#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1de3
++#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
++#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1de4
++#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
++#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1de5
++#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
++#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1de6
++#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
++#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1de7
++#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
++#define mmOTG5_OTG_CRC_CNTL                                                                            0x1de8
++#define mmOTG5_OTG_CRC_CNTL_BASE_IDX                                                                   2
++#define mmOTG5_OTG_CRC_CNTL2                                                                           0x1de9
++#define mmOTG5_OTG_CRC_CNTL2_BASE_IDX                                                                  2
++#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1dea
++#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1deb
++#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1dec
++#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1ded
++#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG5_OTG_CRC0_DATA_RG                                                                        0x1dee
++#define mmOTG5_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
++#define mmOTG5_OTG_CRC0_DATA_B                                                                         0x1def
++#define mmOTG5_OTG_CRC0_DATA_B_BASE_IDX                                                                2
++#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1df0
++#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1df1
++#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1df2
++#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
++#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1df3
++#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
++#define mmOTG5_OTG_CRC1_DATA_RG                                                                        0x1df4
++#define mmOTG5_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
++#define mmOTG5_OTG_CRC1_DATA_B                                                                         0x1df5
++#define mmOTG5_OTG_CRC1_DATA_B_BASE_IDX                                                                2
++#define mmOTG5_OTG_CRC2_DATA_RG                                                                        0x1df6
++#define mmOTG5_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
++#define mmOTG5_OTG_CRC2_DATA_B                                                                         0x1df7
++#define mmOTG5_OTG_CRC2_DATA_B_BASE_IDX                                                                2
++#define mmOTG5_OTG_CRC3_DATA_RG                                                                        0x1df8
++#define mmOTG5_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
++#define mmOTG5_OTG_CRC3_DATA_B                                                                         0x1df9
++#define mmOTG5_OTG_CRC3_DATA_B_BASE_IDX                                                                2
++#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1dfa
++#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
++#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1dfb
++#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
++#define mmOTG5_OTG_STATIC_SCREEN_CONTROL                                                               0x1e02
++#define mmOTG5_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
++#define mmOTG5_OTG_3D_STRUCTURE_CONTROL                                                                0x1e03
++#define mmOTG5_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
++#define mmOTG5_OTG_GSL_VSYNC_GAP                                                                       0x1e04
++#define mmOTG5_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
++#define mmOTG5_OTG_MASTER_UPDATE_MODE                                                                  0x1e05
++#define mmOTG5_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
++#define mmOTG5_OTG_CLOCK_CONTROL                                                                       0x1e06
++#define mmOTG5_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
++#define mmOTG5_OTG_VSTARTUP_PARAM                                                                      0x1e07
++#define mmOTG5_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
++#define mmOTG5_OTG_VUPDATE_PARAM                                                                       0x1e08
++#define mmOTG5_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
++#define mmOTG5_OTG_VREADY_PARAM                                                                        0x1e09
++#define mmOTG5_OTG_VREADY_PARAM_BASE_IDX                                                               2
++#define mmOTG5_OTG_GLOBAL_SYNC_STATUS                                                                  0x1e0a
++#define mmOTG5_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
++#define mmOTG5_OTG_MASTER_UPDATE_LOCK                                                                  0x1e0b
++#define mmOTG5_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
++#define mmOTG5_OTG_GSL_CONTROL                                                                         0x1e0c
++#define mmOTG5_OTG_GSL_CONTROL_BASE_IDX                                                                2
++#define mmOTG5_OTG_GSL_WINDOW_X                                                                        0x1e0d
++#define mmOTG5_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
++#define mmOTG5_OTG_GSL_WINDOW_Y                                                                        0x1e0e
++#define mmOTG5_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
++#define mmOTG5_OTG_VUPDATE_KEEPOUT                                                                     0x1e0f
++#define mmOTG5_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
++#define mmOTG5_OTG_GLOBAL_CONTROL0                                                                     0x1e10
++#define mmOTG5_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
++#define mmOTG5_OTG_GLOBAL_CONTROL1                                                                     0x1e11
++#define mmOTG5_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
++#define mmOTG5_OTG_GLOBAL_CONTROL2                                                                     0x1e12
++#define mmOTG5_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
++#define mmOTG5_OTG_GLOBAL_CONTROL3                                                                     0x1e13
++#define mmOTG5_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
++#define mmOTG5_OTG_TRIG_MANUAL_CONTROL                                                                 0x1e14
++#define mmOTG5_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
++#define mmOTG5_OTG_MANUAL_FLOW_CONTROL                                                                 0x1e15
++#define mmOTG5_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
++#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS                                                             0x1e16
++#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX                                                    2
++#define mmOTG5_OTG_DRR_CONTROL                                                                         0x1e17
++#define mmOTG5_OTG_DRR_CONTROL_BASE_IDX                                                                2
++#define mmOTG5_OTG_REQUEST_CONTROL                                                                     0x1e18
++#define mmOTG5_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
++#define mmOTG5_OTG_DSC_START_POSITION                                                                  0x1e19
++#define mmOTG5_OTG_DSC_START_POSITION_BASE_IDX                                                         2
++#define mmOTG5_OTG_PIPE_UPDATE_STATUS                                                                  0x1e1a
++#define mmOTG5_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
++#define mmOTG5_OTG_SPARE_REGISTER                                                                      0x1e1c
++#define mmOTG5_OTG_SPARE_REGISTER_BASE_IDX                                                             2
++
++
++// addressBlock: dce_dc_optc_optc_misc_dispdec
++// base address: 0x0
++#define mmDWB_SOURCE_SELECT                                                                            0x1e2a
++#define mmDWB_SOURCE_SELECT_BASE_IDX                                                                   2
++#define mmGSL_SOURCE_SELECT                                                                            0x1e2b
++#define mmGSL_SOURCE_SELECT_BASE_IDX                                                                   2
++#define mmOPTC_CLOCK_CONTROL                                                                           0x1e2c
++#define mmOPTC_CLOCK_CONTROL_BASE_IDX                                                                  2
++#define mmODM_MEM_PWR_CTRL                                                                             0x1e2d
++#define mmODM_MEM_PWR_CTRL_BASE_IDX                                                                    2
++#define mmODM_MEM_PWR_CTRL2                                                                            0x1e2e
++#define mmODM_MEM_PWR_CTRL2_BASE_IDX                                                                   2
++#define mmODM_MEM_PWR_CTRL3                                                                            0x1e2f
++#define mmODM_MEM_PWR_CTRL3_BASE_IDX                                                                   2
++#define mmODM_MEM_PWR_STATUS                                                                           0x1e30
++#define mmODM_MEM_PWR_STATUS_BASE_IDX                                                                  2
++#define mmOPTC_MISC_SPARE_REGISTER                                                                     0x1e31
++#define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
++// base address: 0x79a8
++#define mmDC_PERFMON17_PERFCOUNTER_CNTL                                                                0x1e6a
++#define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX                                                       2
++#define mmDC_PERFMON17_PERFCOUNTER_CNTL2                                                               0x1e6b
++#define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
++#define mmDC_PERFMON17_PERFCOUNTER_STATE                                                               0x1e6c
++#define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX                                                      2
++#define mmDC_PERFMON17_PERFMON_CNTL                                                                    0x1e6d
++#define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX                                                           2
++#define mmDC_PERFMON17_PERFMON_CNTL2                                                                   0x1e6e
++#define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX                                                          2
++#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC                                                         0x1e6f
++#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
++#define mmDC_PERFMON17_PERFMON_CVALUE_LOW                                                              0x1e70
++#define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
++#define mmDC_PERFMON17_PERFMON_HI                                                                      0x1e71
++#define mmDC_PERFMON17_PERFMON_HI_BASE_IDX                                                             2
++#define mmDC_PERFMON17_PERFMON_LOW                                                                     0x1e72
++#define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dio_dout_i2c_dispdec
++// base address: 0x0
++#define mmDC_I2C_CONTROL                                                                               0x1e98
++#define mmDC_I2C_CONTROL_BASE_IDX                                                                      2
++#define mmDC_I2C_ARBITRATION                                                                           0x1e99
++#define mmDC_I2C_ARBITRATION_BASE_IDX                                                                  2
++#define mmDC_I2C_INTERRUPT_CONTROL                                                                     0x1e9a
++#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                            2
++#define mmDC_I2C_SW_STATUS                                                                             0x1e9b
++#define mmDC_I2C_SW_STATUS_BASE_IDX                                                                    2
++#define mmDC_I2C_DDC1_HW_STATUS                                                                        0x1e9c
++#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX                                                               2
++#define mmDC_I2C_DDC2_HW_STATUS                                                                        0x1e9d
++#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX                                                               2
++#define mmDC_I2C_DDC3_HW_STATUS                                                                        0x1e9e
++#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX                                                               2
++#define mmDC_I2C_DDC4_HW_STATUS                                                                        0x1e9f
++#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX                                                               2
++#define mmDC_I2C_DDC5_HW_STATUS                                                                        0x1ea0
++#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX                                                               2
++#define mmDC_I2C_DDC1_SPEED                                                                            0x1ea2
++#define mmDC_I2C_DDC1_SPEED_BASE_IDX                                                                   2
++#define mmDC_I2C_DDC1_SETUP                                                                            0x1ea3
++#define mmDC_I2C_DDC1_SETUP_BASE_IDX                                                                   2
++#define mmDC_I2C_DDC2_SPEED                                                                            0x1ea4
++#define mmDC_I2C_DDC2_SPEED_BASE_IDX                                                                   2
++#define mmDC_I2C_DDC2_SETUP                                                                            0x1ea5
++#define mmDC_I2C_DDC2_SETUP_BASE_IDX                                                                   2
++#define mmDC_I2C_DDC3_SPEED                                                                            0x1ea6
++#define mmDC_I2C_DDC3_SPEED_BASE_IDX                                                                   2
++#define mmDC_I2C_DDC3_SETUP                                                                            0x1ea7
++#define mmDC_I2C_DDC3_SETUP_BASE_IDX                                                                   2
++#define mmDC_I2C_DDC4_SPEED                                                                            0x1ea8
++#define mmDC_I2C_DDC4_SPEED_BASE_IDX                                                                   2
++#define mmDC_I2C_DDC4_SETUP                                                                            0x1ea9
++#define mmDC_I2C_DDC4_SETUP_BASE_IDX                                                                   2
++#define mmDC_I2C_DDC5_SPEED                                                                            0x1eaa
++#define mmDC_I2C_DDC5_SPEED_BASE_IDX                                                                   2
++#define mmDC_I2C_DDC5_SETUP                                                                            0x1eab
++#define mmDC_I2C_DDC5_SETUP_BASE_IDX                                                                   2
++#define mmDC_I2C_TRANSACTION0                                                                          0x1eae
++#define mmDC_I2C_TRANSACTION0_BASE_IDX                                                                 2
++#define mmDC_I2C_TRANSACTION1                                                                          0x1eaf
++#define mmDC_I2C_TRANSACTION1_BASE_IDX                                                                 2
++#define mmDC_I2C_TRANSACTION2                                                                          0x1eb0
++#define mmDC_I2C_TRANSACTION2_BASE_IDX                                                                 2
++#define mmDC_I2C_TRANSACTION3                                                                          0x1eb1
++#define mmDC_I2C_TRANSACTION3_BASE_IDX                                                                 2
++#define mmDC_I2C_DATA                                                                                  0x1eb2
++#define mmDC_I2C_DATA_BASE_IDX                                                                         2
++#define mmDC_I2C_EDID_DETECT_CTRL                                                                      0x1eb6
++#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX                                                             2
++#define mmDC_I2C_READ_REQUEST_INTERRUPT                                                                0x1eb7
++#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX                                                       2
++
++
++// addressBlock: dce_dc_dio_dio_misc_dispdec
++// base address: 0x0
++#define mmDIO_SCRATCH0                                                                                 0x1eca
++#define mmDIO_SCRATCH0_BASE_IDX                                                                        2
++#define mmDIO_SCRATCH1                                                                                 0x1ecb
++#define mmDIO_SCRATCH1_BASE_IDX                                                                        2
++#define mmDIO_SCRATCH2                                                                                 0x1ecc
++#define mmDIO_SCRATCH2_BASE_IDX                                                                        2
++#define mmDIO_SCRATCH3                                                                                 0x1ecd
++#define mmDIO_SCRATCH3_BASE_IDX                                                                        2
++#define mmDIO_SCRATCH4                                                                                 0x1ece
++#define mmDIO_SCRATCH4_BASE_IDX                                                                        2
++#define mmDIO_SCRATCH5                                                                                 0x1ecf
++#define mmDIO_SCRATCH5_BASE_IDX                                                                        2
++#define mmDIO_SCRATCH6                                                                                 0x1ed0
++#define mmDIO_SCRATCH6_BASE_IDX                                                                        2
++#define mmDIO_SCRATCH7                                                                                 0x1ed1
++#define mmDIO_SCRATCH7_BASE_IDX                                                                        2
++#define mmDCE_VCE_CONTROL                                                                              0x1ed2
++#define mmDCE_VCE_CONTROL_BASE_IDX                                                                     2
++#define mmDIO_MEM_PWR_STATUS                                                                           0x1edd
++#define mmDIO_MEM_PWR_STATUS_BASE_IDX                                                                  2
++#define mmDIO_MEM_PWR_CTRL                                                                             0x1ede
++#define mmDIO_MEM_PWR_CTRL_BASE_IDX                                                                    2
++#define mmDIO_MEM_PWR_CTRL2                                                                            0x1edf
++#define mmDIO_MEM_PWR_CTRL2_BASE_IDX                                                                   2
++#define mmDIO_CLK_CNTL                                                                                 0x1ee0
++#define mmDIO_CLK_CNTL_BASE_IDX                                                                        2
++#define mmDIO_MEM_PWR_CTRL3                                                                            0x1ee1
++#define mmDIO_MEM_PWR_CTRL3_BASE_IDX                                                                   2
++#define mmDIO_POWER_MANAGEMENT_CNTL                                                                    0x1ee4
++#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX                                                           2
++#define mmDIG_SOFT_RESET                                                                               0x1eee
++#define mmDIG_SOFT_RESET_BASE_IDX                                                                      2
++#define mmDIO_MEM_PWR_STATUS1                                                                          0x1ef0
++#define mmDIO_MEM_PWR_STATUS1_BASE_IDX                                                                 2
++#define mmDIO_CLK_CNTL2                                                                                0x1ef2
++#define mmDIO_CLK_CNTL2_BASE_IDX                                                                       2
++#define mmDIO_CLK_CNTL3                                                                                0x1ef3
++#define mmDIO_CLK_CNTL3_BASE_IDX                                                                       2
++#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL                                                              0x1eff
++#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX                                                     2
++#define mmDIO_PSP_INTERRUPT_STATUS                                                                     0x1f00
++#define mmDIO_PSP_INTERRUPT_STATUS_BASE_IDX                                                            2
++#define mmDIO_PSP_INTERRUPT_CLEAR                                                                      0x1f01
++#define mmDIO_PSP_INTERRUPT_CLEAR_BASE_IDX                                                             2
++#define mmDIO_GENERIC_INTERRUPT_MESSAGE                                                                0x1f02
++#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX                                                       2
++#define mmDIO_GENERIC_INTERRUPT_CLEAR                                                                  0x1f03
++#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX                                                         2
++
++
++// addressBlock: dce_dc_dio_hpd0_dispdec
++// base address: 0x0
++#define mmHPD0_DC_HPD_INT_STATUS                                                                       0x1f14
++#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX                                                              2
++#define mmHPD0_DC_HPD_INT_CONTROL                                                                      0x1f15
++#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
++#define mmHPD0_DC_HPD_CONTROL                                                                          0x1f16
++#define mmHPD0_DC_HPD_CONTROL_BASE_IDX                                                                 2
++#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f17
++#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
++#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f18
++#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
++
++
++// addressBlock: dce_dc_dio_hpd1_dispdec
++// base address: 0x20
++#define mmHPD1_DC_HPD_INT_STATUS                                                                       0x1f1c
++#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX                                                              2
++#define mmHPD1_DC_HPD_INT_CONTROL                                                                      0x1f1d
++#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
++#define mmHPD1_DC_HPD_CONTROL                                                                          0x1f1e
++#define mmHPD1_DC_HPD_CONTROL_BASE_IDX                                                                 2
++#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f1f
++#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
++#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f20
++#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
++
++
++// addressBlock: dce_dc_dio_hpd2_dispdec
++// base address: 0x40
++#define mmHPD2_DC_HPD_INT_STATUS                                                                       0x1f24
++#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX                                                              2
++#define mmHPD2_DC_HPD_INT_CONTROL                                                                      0x1f25
++#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
++#define mmHPD2_DC_HPD_CONTROL                                                                          0x1f26
++#define mmHPD2_DC_HPD_CONTROL_BASE_IDX                                                                 2
++#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f27
++#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
++#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f28
++#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
++
++
++// addressBlock: dce_dc_dio_hpd3_dispdec
++// base address: 0x60
++#define mmHPD3_DC_HPD_INT_STATUS                                                                       0x1f2c
++#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX                                                              2
++#define mmHPD3_DC_HPD_INT_CONTROL                                                                      0x1f2d
++#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
++#define mmHPD3_DC_HPD_CONTROL                                                                          0x1f2e
++#define mmHPD3_DC_HPD_CONTROL_BASE_IDX                                                                 2
++#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f2f
++#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
++#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f30
++#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
++
++
++// addressBlock: dce_dc_dio_hpd4_dispdec
++// base address: 0x80
++#define mmHPD4_DC_HPD_INT_STATUS                                                                       0x1f34
++#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX                                                              2
++#define mmHPD4_DC_HPD_INT_CONTROL                                                                      0x1f35
++#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
++#define mmHPD4_DC_HPD_CONTROL                                                                          0x1f36
++#define mmHPD4_DC_HPD_CONTROL_BASE_IDX                                                                 2
++#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f37
++#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
++#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f38
++#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
++
++
++// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
++// base address: 0x7d10
++#define mmDC_PERFMON18_PERFCOUNTER_CNTL                                                                0x1f44
++#define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX                                                       2
++#define mmDC_PERFMON18_PERFCOUNTER_CNTL2                                                               0x1f45
++#define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
++#define mmDC_PERFMON18_PERFCOUNTER_STATE                                                               0x1f46
++#define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX                                                      2
++#define mmDC_PERFMON18_PERFMON_CNTL                                                                    0x1f47
++#define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX                                                           2
++#define mmDC_PERFMON18_PERFMON_CNTL2                                                                   0x1f48
++#define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX                                                          2
++#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC                                                         0x1f49
++#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
++#define mmDC_PERFMON18_PERFMON_CVALUE_LOW                                                              0x1f4a
++#define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
++#define mmDC_PERFMON18_PERFMON_HI                                                                      0x1f4b
++#define mmDC_PERFMON18_PERFMON_HI_BASE_IDX                                                             2
++#define mmDC_PERFMON18_PERFMON_LOW                                                                     0x1f4c
++#define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dio_dp_aux0_dispdec
++// base address: 0x0
++#define mmDP_AUX0_AUX_CONTROL                                                                          0x1f50
++#define mmDP_AUX0_AUX_CONTROL_BASE_IDX                                                                 2
++#define mmDP_AUX0_AUX_SW_CONTROL                                                                       0x1f51
++#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX                                                              2
++#define mmDP_AUX0_AUX_ARB_CONTROL                                                                      0x1f52
++#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX                                                             2
++#define mmDP_AUX0_AUX_INTERRUPT_CONTROL                                                                0x1f53
++#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
++#define mmDP_AUX0_AUX_SW_STATUS                                                                        0x1f54
++#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX                                                               2
++#define mmDP_AUX0_AUX_LS_STATUS                                                                        0x1f55
++#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX                                                               2
++#define mmDP_AUX0_AUX_SW_DATA                                                                          0x1f56
++#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX                                                                 2
++#define mmDP_AUX0_AUX_LS_DATA                                                                          0x1f57
++#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX                                                                 2
++#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                                              0x1f58
++#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
++#define mmDP_AUX0_AUX_DPHY_TX_CONTROL                                                                  0x1f59
++#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
++#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0                                                                 0x1f5a
++#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
++#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1                                                                 0x1f5b
++#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
++#define mmDP_AUX0_AUX_DPHY_TX_STATUS                                                                   0x1f5c
++#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
++#define mmDP_AUX0_AUX_DPHY_RX_STATUS                                                                   0x1f5d
++#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
++#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL                                                                 0x1f5e
++#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
++#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f5f
++#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
++#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f60
++#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
++#define mmDP_AUX0_AUX_GTC_SYNC_STATUS                                                                  0x1f61
++#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
++#define mmDP_AUX0_AUX_PHY_WAKE_CNTL                                                                    0x1f66
++#define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
++
++
++// addressBlock: dce_dc_dio_dp_aux1_dispdec
++// base address: 0x70
++#define mmDP_AUX1_AUX_CONTROL                                                                          0x1f6c
++#define mmDP_AUX1_AUX_CONTROL_BASE_IDX                                                                 2
++#define mmDP_AUX1_AUX_SW_CONTROL                                                                       0x1f6d
++#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX                                                              2
++#define mmDP_AUX1_AUX_ARB_CONTROL                                                                      0x1f6e
++#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX                                                             2
++#define mmDP_AUX1_AUX_INTERRUPT_CONTROL                                                                0x1f6f
++#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
++#define mmDP_AUX1_AUX_SW_STATUS                                                                        0x1f70
++#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX                                                               2
++#define mmDP_AUX1_AUX_LS_STATUS                                                                        0x1f71
++#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX                                                               2
++#define mmDP_AUX1_AUX_SW_DATA                                                                          0x1f72
++#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX                                                                 2
++#define mmDP_AUX1_AUX_LS_DATA                                                                          0x1f73
++#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX                                                                 2
++#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                                              0x1f74
++#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
++#define mmDP_AUX1_AUX_DPHY_TX_CONTROL                                                                  0x1f75
++#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
++#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0                                                                 0x1f76
++#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
++#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1                                                                 0x1f77
++#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
++#define mmDP_AUX1_AUX_DPHY_TX_STATUS                                                                   0x1f78
++#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
++#define mmDP_AUX1_AUX_DPHY_RX_STATUS                                                                   0x1f79
++#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
++#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL                                                                 0x1f7a
++#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
++#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f7b
++#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
++#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f7c
++#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
++#define mmDP_AUX1_AUX_GTC_SYNC_STATUS                                                                  0x1f7d
++#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
++#define mmDP_AUX1_AUX_PHY_WAKE_CNTL                                                                    0x1f82
++#define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
++
++
++// addressBlock: dce_dc_dio_dp_aux2_dispdec
++// base address: 0xe0
++#define mmDP_AUX2_AUX_CONTROL                                                                          0x1f88
++#define mmDP_AUX2_AUX_CONTROL_BASE_IDX                                                                 2
++#define mmDP_AUX2_AUX_SW_CONTROL                                                                       0x1f89
++#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX                                                              2
++#define mmDP_AUX2_AUX_ARB_CONTROL                                                                      0x1f8a
++#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX                                                             2
++#define mmDP_AUX2_AUX_INTERRUPT_CONTROL                                                                0x1f8b
++#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
++#define mmDP_AUX2_AUX_SW_STATUS                                                                        0x1f8c
++#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX                                                               2
++#define mmDP_AUX2_AUX_LS_STATUS                                                                        0x1f8d
++#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX                                                               2
++#define mmDP_AUX2_AUX_SW_DATA                                                                          0x1f8e
++#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX                                                                 2
++#define mmDP_AUX2_AUX_LS_DATA                                                                          0x1f8f
++#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX                                                                 2
++#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                                              0x1f90
++#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
++#define mmDP_AUX2_AUX_DPHY_TX_CONTROL                                                                  0x1f91
++#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
++#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0                                                                 0x1f92
++#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
++#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1                                                                 0x1f93
++#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
++#define mmDP_AUX2_AUX_DPHY_TX_STATUS                                                                   0x1f94
++#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
++#define mmDP_AUX2_AUX_DPHY_RX_STATUS                                                                   0x1f95
++#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
++#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL                                                                 0x1f96
++#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
++#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f97
++#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
++#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f98
++#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
++#define mmDP_AUX2_AUX_GTC_SYNC_STATUS                                                                  0x1f99
++#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
++#define mmDP_AUX2_AUX_PHY_WAKE_CNTL                                                                    0x1f9e
++#define mmDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
++
++
++// addressBlock: dce_dc_dio_dp_aux3_dispdec
++// base address: 0x150
++#define mmDP_AUX3_AUX_CONTROL                                                                          0x1fa4
++#define mmDP_AUX3_AUX_CONTROL_BASE_IDX                                                                 2
++#define mmDP_AUX3_AUX_SW_CONTROL                                                                       0x1fa5
++#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX                                                              2
++#define mmDP_AUX3_AUX_ARB_CONTROL                                                                      0x1fa6
++#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX                                                             2
++#define mmDP_AUX3_AUX_INTERRUPT_CONTROL                                                                0x1fa7
++#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
++#define mmDP_AUX3_AUX_SW_STATUS                                                                        0x1fa8
++#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX                                                               2
++#define mmDP_AUX3_AUX_LS_STATUS                                                                        0x1fa9
++#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX                                                               2
++#define mmDP_AUX3_AUX_SW_DATA                                                                          0x1faa
++#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX                                                                 2
++#define mmDP_AUX3_AUX_LS_DATA                                                                          0x1fab
++#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX                                                                 2
++#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                                              0x1fac
++#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
++#define mmDP_AUX3_AUX_DPHY_TX_CONTROL                                                                  0x1fad
++#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
++#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0                                                                 0x1fae
++#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
++#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1                                                                 0x1faf
++#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
++#define mmDP_AUX3_AUX_DPHY_TX_STATUS                                                                   0x1fb0
++#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
++#define mmDP_AUX3_AUX_DPHY_RX_STATUS                                                                   0x1fb1
++#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
++#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL                                                                 0x1fb2
++#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
++#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fb3
++#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
++#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fb4
++#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
++#define mmDP_AUX3_AUX_GTC_SYNC_STATUS                                                                  0x1fb5
++#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
++#define mmDP_AUX3_AUX_PHY_WAKE_CNTL                                                                    0x1fba
++#define mmDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
++
++
++// addressBlock: dce_dc_dio_dp_aux4_dispdec
++// base address: 0x1c0
++#define mmDP_AUX4_AUX_CONTROL                                                                          0x1fc0
++#define mmDP_AUX4_AUX_CONTROL_BASE_IDX                                                                 2
++#define mmDP_AUX4_AUX_SW_CONTROL                                                                       0x1fc1
++#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX                                                              2
++#define mmDP_AUX4_AUX_ARB_CONTROL                                                                      0x1fc2
++#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX                                                             2
++#define mmDP_AUX4_AUX_INTERRUPT_CONTROL                                                                0x1fc3
++#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
++#define mmDP_AUX4_AUX_SW_STATUS                                                                        0x1fc4
++#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX                                                               2
++#define mmDP_AUX4_AUX_LS_STATUS                                                                        0x1fc5
++#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX                                                               2
++#define mmDP_AUX4_AUX_SW_DATA                                                                          0x1fc6
++#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX                                                                 2
++#define mmDP_AUX4_AUX_LS_DATA                                                                          0x1fc7
++#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX                                                                 2
++#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                                              0x1fc8
++#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
++#define mmDP_AUX4_AUX_DPHY_TX_CONTROL                                                                  0x1fc9
++#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
++#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0                                                                 0x1fca
++#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
++#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1                                                                 0x1fcb
++#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
++#define mmDP_AUX4_AUX_DPHY_TX_STATUS                                                                   0x1fcc
++#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
++#define mmDP_AUX4_AUX_DPHY_RX_STATUS                                                                   0x1fcd
++#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
++#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL                                                                 0x1fce
++#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
++#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fcf
++#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
++#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fd0
++#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
++#define mmDP_AUX4_AUX_GTC_SYNC_STATUS                                                                  0x1fd1
++#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
++#define mmDP_AUX4_AUX_PHY_WAKE_CNTL                                                                    0x1fd6
++#define mmDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
++
++
++// addressBlock: dce_dc_dio_dig0_dispdec
++// base address: 0x0
++#define mmDIG0_DIG_FE_CNTL                                                                             0x2068
++#define mmDIG0_DIG_FE_CNTL_BASE_IDX                                                                    2
++#define mmDIG0_DIG_OUTPUT_CRC_CNTL                                                                     0x2069
++#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
++#define mmDIG0_DIG_OUTPUT_CRC_RESULT                                                                   0x206a
++#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
++#define mmDIG0_DIG_CLOCK_PATTERN                                                                       0x206b
++#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
++#define mmDIG0_DIG_TEST_PATTERN                                                                        0x206c
++#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX                                                               2
++#define mmDIG0_DIG_RANDOM_PATTERN_SEED                                                                 0x206d
++#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
++#define mmDIG0_DIG_FIFO_STATUS                                                                         0x206e
++#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX                                                                2
++#define mmDIG0_HDMI_METADATA_PACKET_CONTROL                                                            0x206f
++#define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2070
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
++#define mmDIG0_HDMI_CONTROL                                                                            0x2071
++#define mmDIG0_HDMI_CONTROL_BASE_IDX                                                                   2
++#define mmDIG0_HDMI_STATUS                                                                             0x2072
++#define mmDIG0_HDMI_STATUS_BASE_IDX                                                                    2
++#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL                                                               0x2073
++#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
++#define mmDIG0_HDMI_ACR_PACKET_CONTROL                                                                 0x2074
++#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
++#define mmDIG0_HDMI_VBI_PACKET_CONTROL                                                                 0x2075
++#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
++#define mmDIG0_HDMI_INFOFRAME_CONTROL0                                                                 0x2076
++#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
++#define mmDIG0_HDMI_INFOFRAME_CONTROL1                                                                 0x2077
++#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2078
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
++#define mmDIG0_AFMT_INTERRUPT_STATUS                                                                   0x2079
++#define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
++#define mmDIG0_HDMI_GC                                                                                 0x207b
++#define mmDIG0_HDMI_GC_BASE_IDX                                                                        2
++#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2                                                              0x207c
++#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
++#define mmDIG0_AFMT_ISRC1_0                                                                            0x207d
++#define mmDIG0_AFMT_ISRC1_0_BASE_IDX                                                                   2
++#define mmDIG0_AFMT_ISRC1_1                                                                            0x207e
++#define mmDIG0_AFMT_ISRC1_1_BASE_IDX                                                                   2
++#define mmDIG0_AFMT_ISRC1_2                                                                            0x207f
++#define mmDIG0_AFMT_ISRC1_2_BASE_IDX                                                                   2
++#define mmDIG0_AFMT_ISRC1_3                                                                            0x2080
++#define mmDIG0_AFMT_ISRC1_3_BASE_IDX                                                                   2
++#define mmDIG0_AFMT_ISRC1_4                                                                            0x2081
++#define mmDIG0_AFMT_ISRC1_4_BASE_IDX                                                                   2
++#define mmDIG0_AFMT_ISRC2_0                                                                            0x2082
++#define mmDIG0_AFMT_ISRC2_0_BASE_IDX                                                                   2
++#define mmDIG0_AFMT_ISRC2_1                                                                            0x2083
++#define mmDIG0_AFMT_ISRC2_1_BASE_IDX                                                                   2
++#define mmDIG0_AFMT_ISRC2_2                                                                            0x2084
++#define mmDIG0_AFMT_ISRC2_2_BASE_IDX                                                                   2
++#define mmDIG0_AFMT_ISRC2_3                                                                            0x2085
++#define mmDIG0_AFMT_ISRC2_3_BASE_IDX                                                                   2
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2086
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2087
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
++#define mmDIG0_HDMI_DB_CONTROL                                                                         0x2088
++#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX                                                                2
++#define mmDIG0_DME_CONTROL                                                                             0x2089
++#define mmDIG0_DME_CONTROL_BASE_IDX                                                                    2
++#define mmDIG0_AFMT_MPEG_INFO0                                                                         0x208a
++#define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX                                                                2
++#define mmDIG0_AFMT_MPEG_INFO1                                                                         0x208b
++#define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX                                                                2
++#define mmDIG0_AFMT_GENERIC_HDR                                                                        0x208c
++#define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX                                                               2
++#define mmDIG0_AFMT_GENERIC_0                                                                          0x208d
++#define mmDIG0_AFMT_GENERIC_0_BASE_IDX                                                                 2
++#define mmDIG0_AFMT_GENERIC_1                                                                          0x208e
++#define mmDIG0_AFMT_GENERIC_1_BASE_IDX                                                                 2
++#define mmDIG0_AFMT_GENERIC_2                                                                          0x208f
++#define mmDIG0_AFMT_GENERIC_2_BASE_IDX                                                                 2
++#define mmDIG0_AFMT_GENERIC_3                                                                          0x2090
++#define mmDIG0_AFMT_GENERIC_3_BASE_IDX                                                                 2
++#define mmDIG0_AFMT_GENERIC_4                                                                          0x2091
++#define mmDIG0_AFMT_GENERIC_4_BASE_IDX                                                                 2
++#define mmDIG0_AFMT_GENERIC_5                                                                          0x2092
++#define mmDIG0_AFMT_GENERIC_5_BASE_IDX                                                                 2
++#define mmDIG0_AFMT_GENERIC_6                                                                          0x2093
++#define mmDIG0_AFMT_GENERIC_6_BASE_IDX                                                                 2
++#define mmDIG0_AFMT_GENERIC_7                                                                          0x2094
++#define mmDIG0_AFMT_GENERIC_7_BASE_IDX                                                                 2
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2095
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
++#define mmDIG0_HDMI_ACR_32_0                                                                           0x2096
++#define mmDIG0_HDMI_ACR_32_0_BASE_IDX                                                                  2
++#define mmDIG0_HDMI_ACR_32_1                                                                           0x2097
++#define mmDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2
++#define mmDIG0_HDMI_ACR_44_0                                                                           0x2098
++#define mmDIG0_HDMI_ACR_44_0_BASE_IDX                                                                  2
++#define mmDIG0_HDMI_ACR_44_1                                                                           0x2099
++#define mmDIG0_HDMI_ACR_44_1_BASE_IDX                                                                  2
++#define mmDIG0_HDMI_ACR_48_0                                                                           0x209a
++#define mmDIG0_HDMI_ACR_48_0_BASE_IDX                                                                  2
++#define mmDIG0_HDMI_ACR_48_1                                                                           0x209b
++#define mmDIG0_HDMI_ACR_48_1_BASE_IDX                                                                  2
++#define mmDIG0_HDMI_ACR_STATUS_0                                                                       0x209c
++#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
++#define mmDIG0_HDMI_ACR_STATUS_1                                                                       0x209d
++#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
++#define mmDIG0_AFMT_AUDIO_INFO0                                                                        0x209e
++#define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
++#define mmDIG0_AFMT_AUDIO_INFO1                                                                        0x209f
++#define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
++#define mmDIG0_AFMT_60958_0                                                                            0x20a0
++#define mmDIG0_AFMT_60958_0_BASE_IDX                                                                   2
++#define mmDIG0_AFMT_60958_1                                                                            0x20a1
++#define mmDIG0_AFMT_60958_1_BASE_IDX                                                                   2
++#define mmDIG0_AFMT_AUDIO_CRC_CONTROL                                                                  0x20a2
++#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
++#define mmDIG0_AFMT_RAMP_CONTROL0                                                                      0x20a3
++#define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
++#define mmDIG0_AFMT_RAMP_CONTROL1                                                                      0x20a4
++#define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
++#define mmDIG0_AFMT_RAMP_CONTROL2                                                                      0x20a5
++#define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
++#define mmDIG0_AFMT_RAMP_CONTROL3                                                                      0x20a6
++#define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
++#define mmDIG0_AFMT_60958_2                                                                            0x20a7
++#define mmDIG0_AFMT_60958_2_BASE_IDX                                                                   2
++#define mmDIG0_AFMT_AUDIO_CRC_RESULT                                                                   0x20a8
++#define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
++#define mmDIG0_AFMT_STATUS                                                                             0x20a9
++#define mmDIG0_AFMT_STATUS_BASE_IDX                                                                    2
++#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL                                                               0x20aa
++#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
++#define mmDIG0_AFMT_VBI_PACKET_CONTROL                                                                 0x20ab
++#define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
++#define mmDIG0_AFMT_INFOFRAME_CONTROL0                                                                 0x20ac
++#define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
++#define mmDIG0_AFMT_AUDIO_SRC_CONTROL                                                                  0x20ad
++#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
++#define mmDIG0_DIG_BE_CNTL                                                                             0x20af
++#define mmDIG0_DIG_BE_CNTL_BASE_IDX                                                                    2
++#define mmDIG0_DIG_BE_EN_CNTL                                                                          0x20b0
++#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
++#define mmDIG0_TMDS_CNTL                                                                               0x20d3
++#define mmDIG0_TMDS_CNTL_BASE_IDX                                                                      2
++#define mmDIG0_TMDS_CONTROL_CHAR                                                                       0x20d4
++#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
++#define mmDIG0_TMDS_CONTROL0_FEEDBACK                                                                  0x20d5
++#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
++#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL                                                                 0x20d6
++#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
++#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x20d7
++#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
++#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x20d8
++#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
++#define mmDIG0_TMDS_CTL_BITS                                                                           0x20da
++#define mmDIG0_TMDS_CTL_BITS_BASE_IDX                                                                  2
++#define mmDIG0_TMDS_DCBALANCER_CONTROL                                                                 0x20db
++#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
++#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR                                                                0x20dc
++#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
++#define mmDIG0_TMDS_CTL0_1_GEN_CNTL                                                                    0x20dd
++#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
++#define mmDIG0_TMDS_CTL2_3_GEN_CNTL                                                                    0x20de
++#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
++#define mmDIG0_DIG_VERSION                                                                             0x20e0
++#define mmDIG0_DIG_VERSION_BASE_IDX                                                                    2
++#define mmDIG0_DIG_LANE_ENABLE                                                                         0x20e1
++#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX                                                                2
++#define mmDIG0_AFMT_CNTL                                                                               0x20e6
++#define mmDIG0_AFMT_CNTL_BASE_IDX                                                                      2
++#define mmDIG0_AFMT_VBI_PACKET_CONTROL1                                                                0x20e7
++#define mmDIG0_AFMT_VBI_PACKET_CONTROL1_BASE_IDX                                                       2
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5                                                            0x20f6
++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
++#define mmDIG0_FORCE_DIG_DISABLE                                                                       0x20f7
++#define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX                                                              2
++
++
++// addressBlock: dce_dc_dio_dp0_dispdec
++// base address: 0x0
++#define mmDP0_DP_LINK_CNTL                                                                             0x2108
++#define mmDP0_DP_LINK_CNTL_BASE_IDX                                                                    2
++#define mmDP0_DP_PIXEL_FORMAT                                                                          0x2109
++#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
++#define mmDP0_DP_MSA_COLORIMETRY                                                                       0x210a
++#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
++#define mmDP0_DP_CONFIG                                                                                0x210b
++#define mmDP0_DP_CONFIG_BASE_IDX                                                                       2
++#define mmDP0_DP_VID_STREAM_CNTL                                                                       0x210c
++#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
++#define mmDP0_DP_STEER_FIFO                                                                            0x210d
++#define mmDP0_DP_STEER_FIFO_BASE_IDX                                                                   2
++#define mmDP0_DP_MSA_MISC                                                                              0x210e
++#define mmDP0_DP_MSA_MISC_BASE_IDX                                                                     2
++#define mmDP0_DP_VID_TIMING                                                                            0x2110
++#define mmDP0_DP_VID_TIMING_BASE_IDX                                                                   2
++#define mmDP0_DP_VID_N                                                                                 0x2111
++#define mmDP0_DP_VID_N_BASE_IDX                                                                        2
++#define mmDP0_DP_VID_M                                                                                 0x2112
++#define mmDP0_DP_VID_M_BASE_IDX                                                                        2
++#define mmDP0_DP_LINK_FRAMING_CNTL                                                                     0x2113
++#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
++#define mmDP0_DP_HBR2_EYE_PATTERN                                                                      0x2114
++#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
++#define mmDP0_DP_VID_MSA_VBID                                                                          0x2115
++#define mmDP0_DP_VID_MSA_VBID_BASE_IDX                                                                 2
++#define mmDP0_DP_VID_INTERRUPT_CNTL                                                                    0x2116
++#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
++#define mmDP0_DP_DPHY_CNTL                                                                             0x2117
++#define mmDP0_DP_DPHY_CNTL_BASE_IDX                                                                    2
++#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2118
++#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
++#define mmDP0_DP_DPHY_SYM0                                                                             0x2119
++#define mmDP0_DP_DPHY_SYM0_BASE_IDX                                                                    2
++#define mmDP0_DP_DPHY_SYM1                                                                             0x211a
++#define mmDP0_DP_DPHY_SYM1_BASE_IDX                                                                    2
++#define mmDP0_DP_DPHY_SYM2                                                                             0x211b
++#define mmDP0_DP_DPHY_SYM2_BASE_IDX                                                                    2
++#define mmDP0_DP_DPHY_8B10B_CNTL                                                                       0x211c
++#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
++#define mmDP0_DP_DPHY_PRBS_CNTL                                                                        0x211d
++#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
++#define mmDP0_DP_DPHY_SCRAM_CNTL                                                                       0x211e
++#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
++#define mmDP0_DP_DPHY_CRC_EN                                                                           0x211f
++#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
++#define mmDP0_DP_DPHY_CRC_CNTL                                                                         0x2120
++#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
++#define mmDP0_DP_DPHY_CRC_RESULT                                                                       0x2121
++#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
++#define mmDP0_DP_DPHY_CRC_MST_CNTL                                                                     0x2122
++#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
++#define mmDP0_DP_DPHY_CRC_MST_STATUS                                                                   0x2123
++#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
++#define mmDP0_DP_DPHY_FAST_TRAINING                                                                    0x2124
++#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
++#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2125
++#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
++#define mmDP0_DP_SEC_CNTL                                                                              0x212b
++#define mmDP0_DP_SEC_CNTL_BASE_IDX                                                                     2
++#define mmDP0_DP_SEC_CNTL1                                                                             0x212c
++#define mmDP0_DP_SEC_CNTL1_BASE_IDX                                                                    2
++#define mmDP0_DP_SEC_FRAMING1                                                                          0x212d
++#define mmDP0_DP_SEC_FRAMING1_BASE_IDX                                                                 2
++#define mmDP0_DP_SEC_FRAMING2                                                                          0x212e
++#define mmDP0_DP_SEC_FRAMING2_BASE_IDX                                                                 2
++#define mmDP0_DP_SEC_FRAMING3                                                                          0x212f
++#define mmDP0_DP_SEC_FRAMING3_BASE_IDX                                                                 2
++#define mmDP0_DP_SEC_FRAMING4                                                                          0x2130
++#define mmDP0_DP_SEC_FRAMING4_BASE_IDX                                                                 2
++#define mmDP0_DP_SEC_AUD_N                                                                             0x2131
++#define mmDP0_DP_SEC_AUD_N_BASE_IDX                                                                    2
++#define mmDP0_DP_SEC_AUD_N_READBACK                                                                    0x2132
++#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
++#define mmDP0_DP_SEC_AUD_M                                                                             0x2133
++#define mmDP0_DP_SEC_AUD_M_BASE_IDX                                                                    2
++#define mmDP0_DP_SEC_AUD_M_READBACK                                                                    0x2134
++#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
++#define mmDP0_DP_SEC_TIMESTAMP                                                                         0x2135
++#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
++#define mmDP0_DP_SEC_PACKET_CNTL                                                                       0x2136
++#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
++#define mmDP0_DP_MSE_RATE_CNTL                                                                         0x2137
++#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
++#define mmDP0_DP_MSE_RATE_UPDATE                                                                       0x2139
++#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
++#define mmDP0_DP_MSE_SAT0                                                                              0x213a
++#define mmDP0_DP_MSE_SAT0_BASE_IDX                                                                     2
++#define mmDP0_DP_MSE_SAT1                                                                              0x213b
++#define mmDP0_DP_MSE_SAT1_BASE_IDX                                                                     2
++#define mmDP0_DP_MSE_SAT2                                                                              0x213c
++#define mmDP0_DP_MSE_SAT2_BASE_IDX                                                                     2
++#define mmDP0_DP_MSE_SAT_UPDATE                                                                        0x213d
++#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
++#define mmDP0_DP_MSE_LINK_TIMING                                                                       0x213e
++#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
++#define mmDP0_DP_MSE_MISC_CNTL                                                                         0x213f
++#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
++#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2144
++#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
++#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2145
++#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
++#define mmDP0_DP_MSE_SAT0_STATUS                                                                       0x2147
++#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
++#define mmDP0_DP_MSE_SAT1_STATUS                                                                       0x2148
++#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
++#define mmDP0_DP_MSE_SAT2_STATUS                                                                       0x2149
++#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
++#define mmDP0_DP_MSA_TIMING_PARAM1                                                                     0x214c
++#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
++#define mmDP0_DP_MSA_TIMING_PARAM2                                                                     0x214d
++#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
++#define mmDP0_DP_MSA_TIMING_PARAM3                                                                     0x214e
++#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
++#define mmDP0_DP_MSA_TIMING_PARAM4                                                                     0x214f
++#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
++#define mmDP0_DP_MSO_CNTL                                                                              0x2150
++#define mmDP0_DP_MSO_CNTL_BASE_IDX                                                                     2
++#define mmDP0_DP_MSO_CNTL1                                                                             0x2151
++#define mmDP0_DP_MSO_CNTL1_BASE_IDX                                                                    2
++#define mmDP0_DP_DSC_CNTL                                                                              0x2152
++#define mmDP0_DP_DSC_CNTL_BASE_IDX                                                                     2
++#define mmDP0_DP_SEC_CNTL2                                                                             0x2153
++#define mmDP0_DP_SEC_CNTL2_BASE_IDX                                                                    2
++#define mmDP0_DP_SEC_CNTL3                                                                             0x2154
++#define mmDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2
++#define mmDP0_DP_SEC_CNTL4                                                                             0x2155
++#define mmDP0_DP_SEC_CNTL4_BASE_IDX                                                                    2
++#define mmDP0_DP_SEC_CNTL5                                                                             0x2156
++#define mmDP0_DP_SEC_CNTL5_BASE_IDX                                                                    2
++#define mmDP0_DP_SEC_CNTL6                                                                             0x2157
++#define mmDP0_DP_SEC_CNTL6_BASE_IDX                                                                    2
++#define mmDP0_DP_SEC_CNTL7                                                                             0x2158
++#define mmDP0_DP_SEC_CNTL7_BASE_IDX                                                                    2
++#define mmDP0_DP_DB_CNTL                                                                               0x2159
++#define mmDP0_DP_DB_CNTL_BASE_IDX                                                                      2
++#define mmDP0_DP_MSA_VBID_MISC                                                                         0x215a
++#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX                                                                2
++#define mmDP0_DP_SEC_METADATA_TRANSMISSION                                                             0x215b
++#define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
++#define mmDP0_DP_DSC_BYTES_PER_PIXEL                                                                   0x215c
++#define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
++#define mmDP0_DP_ALPM_CNTL                                                                             0x215d
++#define mmDP0_DP_ALPM_CNTL_BASE_IDX                                                                    2
++
++
++// addressBlock: dce_dc_dio_dig1_dispdec
++// base address: 0x400
++#define mmDIG1_DIG_FE_CNTL                                                                             0x2168
++#define mmDIG1_DIG_FE_CNTL_BASE_IDX                                                                    2
++#define mmDIG1_DIG_OUTPUT_CRC_CNTL                                                                     0x2169
++#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
++#define mmDIG1_DIG_OUTPUT_CRC_RESULT                                                                   0x216a
++#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
++#define mmDIG1_DIG_CLOCK_PATTERN                                                                       0x216b
++#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
++#define mmDIG1_DIG_TEST_PATTERN                                                                        0x216c
++#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX                                                               2
++#define mmDIG1_DIG_RANDOM_PATTERN_SEED                                                                 0x216d
++#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
++#define mmDIG1_DIG_FIFO_STATUS                                                                         0x216e
++#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX                                                                2
++#define mmDIG1_HDMI_METADATA_PACKET_CONTROL                                                            0x216f
++#define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2170
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
++#define mmDIG1_HDMI_CONTROL                                                                            0x2171
++#define mmDIG1_HDMI_CONTROL_BASE_IDX                                                                   2
++#define mmDIG1_HDMI_STATUS                                                                             0x2172
++#define mmDIG1_HDMI_STATUS_BASE_IDX                                                                    2
++#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL                                                               0x2173
++#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
++#define mmDIG1_HDMI_ACR_PACKET_CONTROL                                                                 0x2174
++#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
++#define mmDIG1_HDMI_VBI_PACKET_CONTROL                                                                 0x2175
++#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
++#define mmDIG1_HDMI_INFOFRAME_CONTROL0                                                                 0x2176
++#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
++#define mmDIG1_HDMI_INFOFRAME_CONTROL1                                                                 0x2177
++#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2178
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
++#define mmDIG1_AFMT_INTERRUPT_STATUS                                                                   0x2179
++#define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
++#define mmDIG1_HDMI_GC                                                                                 0x217b
++#define mmDIG1_HDMI_GC_BASE_IDX                                                                        2
++#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2                                                              0x217c
++#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
++#define mmDIG1_AFMT_ISRC1_0                                                                            0x217d
++#define mmDIG1_AFMT_ISRC1_0_BASE_IDX                                                                   2
++#define mmDIG1_AFMT_ISRC1_1                                                                            0x217e
++#define mmDIG1_AFMT_ISRC1_1_BASE_IDX                                                                   2
++#define mmDIG1_AFMT_ISRC1_2                                                                            0x217f
++#define mmDIG1_AFMT_ISRC1_2_BASE_IDX                                                                   2
++#define mmDIG1_AFMT_ISRC1_3                                                                            0x2180
++#define mmDIG1_AFMT_ISRC1_3_BASE_IDX                                                                   2
++#define mmDIG1_AFMT_ISRC1_4                                                                            0x2181
++#define mmDIG1_AFMT_ISRC1_4_BASE_IDX                                                                   2
++#define mmDIG1_AFMT_ISRC2_0                                                                            0x2182
++#define mmDIG1_AFMT_ISRC2_0_BASE_IDX                                                                   2
++#define mmDIG1_AFMT_ISRC2_1                                                                            0x2183
++#define mmDIG1_AFMT_ISRC2_1_BASE_IDX                                                                   2
++#define mmDIG1_AFMT_ISRC2_2                                                                            0x2184
++#define mmDIG1_AFMT_ISRC2_2_BASE_IDX                                                                   2
++#define mmDIG1_AFMT_ISRC2_3                                                                            0x2185
++#define mmDIG1_AFMT_ISRC2_3_BASE_IDX                                                                   2
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2186
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2187
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
++#define mmDIG1_HDMI_DB_CONTROL                                                                         0x2188
++#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX                                                                2
++#define mmDIG1_DME_CONTROL                                                                             0x2189
++#define mmDIG1_DME_CONTROL_BASE_IDX                                                                    2
++#define mmDIG1_AFMT_MPEG_INFO0                                                                         0x218a
++#define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX                                                                2
++#define mmDIG1_AFMT_MPEG_INFO1                                                                         0x218b
++#define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX                                                                2
++#define mmDIG1_AFMT_GENERIC_HDR                                                                        0x218c
++#define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX                                                               2
++#define mmDIG1_AFMT_GENERIC_0                                                                          0x218d
++#define mmDIG1_AFMT_GENERIC_0_BASE_IDX                                                                 2
++#define mmDIG1_AFMT_GENERIC_1                                                                          0x218e
++#define mmDIG1_AFMT_GENERIC_1_BASE_IDX                                                                 2
++#define mmDIG1_AFMT_GENERIC_2                                                                          0x218f
++#define mmDIG1_AFMT_GENERIC_2_BASE_IDX                                                                 2
++#define mmDIG1_AFMT_GENERIC_3                                                                          0x2190
++#define mmDIG1_AFMT_GENERIC_3_BASE_IDX                                                                 2
++#define mmDIG1_AFMT_GENERIC_4                                                                          0x2191
++#define mmDIG1_AFMT_GENERIC_4_BASE_IDX                                                                 2
++#define mmDIG1_AFMT_GENERIC_5                                                                          0x2192
++#define mmDIG1_AFMT_GENERIC_5_BASE_IDX                                                                 2
++#define mmDIG1_AFMT_GENERIC_6                                                                          0x2193
++#define mmDIG1_AFMT_GENERIC_6_BASE_IDX                                                                 2
++#define mmDIG1_AFMT_GENERIC_7                                                                          0x2194
++#define mmDIG1_AFMT_GENERIC_7_BASE_IDX                                                                 2
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2195
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
++#define mmDIG1_HDMI_ACR_32_0                                                                           0x2196
++#define mmDIG1_HDMI_ACR_32_0_BASE_IDX                                                                  2
++#define mmDIG1_HDMI_ACR_32_1                                                                           0x2197
++#define mmDIG1_HDMI_ACR_32_1_BASE_IDX                                                                  2
++#define mmDIG1_HDMI_ACR_44_0                                                                           0x2198
++#define mmDIG1_HDMI_ACR_44_0_BASE_IDX                                                                  2
++#define mmDIG1_HDMI_ACR_44_1                                                                           0x2199
++#define mmDIG1_HDMI_ACR_44_1_BASE_IDX                                                                  2
++#define mmDIG1_HDMI_ACR_48_0                                                                           0x219a
++#define mmDIG1_HDMI_ACR_48_0_BASE_IDX                                                                  2
++#define mmDIG1_HDMI_ACR_48_1                                                                           0x219b
++#define mmDIG1_HDMI_ACR_48_1_BASE_IDX                                                                  2
++#define mmDIG1_HDMI_ACR_STATUS_0                                                                       0x219c
++#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
++#define mmDIG1_HDMI_ACR_STATUS_1                                                                       0x219d
++#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
++#define mmDIG1_AFMT_AUDIO_INFO0                                                                        0x219e
++#define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
++#define mmDIG1_AFMT_AUDIO_INFO1                                                                        0x219f
++#define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
++#define mmDIG1_AFMT_60958_0                                                                            0x21a0
++#define mmDIG1_AFMT_60958_0_BASE_IDX                                                                   2
++#define mmDIG1_AFMT_60958_1                                                                            0x21a1
++#define mmDIG1_AFMT_60958_1_BASE_IDX                                                                   2
++#define mmDIG1_AFMT_AUDIO_CRC_CONTROL                                                                  0x21a2
++#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
++#define mmDIG1_AFMT_RAMP_CONTROL0                                                                      0x21a3
++#define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
++#define mmDIG1_AFMT_RAMP_CONTROL1                                                                      0x21a4
++#define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
++#define mmDIG1_AFMT_RAMP_CONTROL2                                                                      0x21a5
++#define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
++#define mmDIG1_AFMT_RAMP_CONTROL3                                                                      0x21a6
++#define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
++#define mmDIG1_AFMT_60958_2                                                                            0x21a7
++#define mmDIG1_AFMT_60958_2_BASE_IDX                                                                   2
++#define mmDIG1_AFMT_AUDIO_CRC_RESULT                                                                   0x21a8
++#define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
++#define mmDIG1_AFMT_STATUS                                                                             0x21a9
++#define mmDIG1_AFMT_STATUS_BASE_IDX                                                                    2
++#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL                                                               0x21aa
++#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
++#define mmDIG1_AFMT_VBI_PACKET_CONTROL                                                                 0x21ab
++#define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
++#define mmDIG1_AFMT_INFOFRAME_CONTROL0                                                                 0x21ac
++#define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
++#define mmDIG1_AFMT_AUDIO_SRC_CONTROL                                                                  0x21ad
++#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
++#define mmDIG1_DIG_BE_CNTL                                                                             0x21af
++#define mmDIG1_DIG_BE_CNTL_BASE_IDX                                                                    2
++#define mmDIG1_DIG_BE_EN_CNTL                                                                          0x21b0
++#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
++#define mmDIG1_TMDS_CNTL                                                                               0x21d3
++#define mmDIG1_TMDS_CNTL_BASE_IDX                                                                      2
++#define mmDIG1_TMDS_CONTROL_CHAR                                                                       0x21d4
++#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
++#define mmDIG1_TMDS_CONTROL0_FEEDBACK                                                                  0x21d5
++#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
++#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL                                                                 0x21d6
++#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
++#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x21d7
++#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
++#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x21d8
++#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
++#define mmDIG1_TMDS_CTL_BITS                                                                           0x21da
++#define mmDIG1_TMDS_CTL_BITS_BASE_IDX                                                                  2
++#define mmDIG1_TMDS_DCBALANCER_CONTROL                                                                 0x21db
++#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
++#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR                                                                0x21dc
++#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
++#define mmDIG1_TMDS_CTL0_1_GEN_CNTL                                                                    0x21dd
++#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
++#define mmDIG1_TMDS_CTL2_3_GEN_CNTL                                                                    0x21de
++#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
++#define mmDIG1_DIG_VERSION                                                                             0x21e0
++#define mmDIG1_DIG_VERSION_BASE_IDX                                                                    2
++#define mmDIG1_DIG_LANE_ENABLE                                                                         0x21e1
++#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX                                                                2
++#define mmDIG1_AFMT_CNTL                                                                               0x21e6
++#define mmDIG1_AFMT_CNTL_BASE_IDX                                                                      2
++#define mmDIG1_AFMT_VBI_PACKET_CONTROL1                                                                0x21e7
++#define mmDIG1_AFMT_VBI_PACKET_CONTROL1_BASE_IDX                                                       2
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5                                                            0x21f6
++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
++#define mmDIG1_FORCE_DIG_DISABLE                                                                       0x21f7
++#define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX                                                              2
++
++
++// addressBlock: dce_dc_dio_dp1_dispdec
++// base address: 0x400
++#define mmDP1_DP_LINK_CNTL                                                                             0x2208
++#define mmDP1_DP_LINK_CNTL_BASE_IDX                                                                    2
++#define mmDP1_DP_PIXEL_FORMAT                                                                          0x2209
++#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
++#define mmDP1_DP_MSA_COLORIMETRY                                                                       0x220a
++#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
++#define mmDP1_DP_CONFIG                                                                                0x220b
++#define mmDP1_DP_CONFIG_BASE_IDX                                                                       2
++#define mmDP1_DP_VID_STREAM_CNTL                                                                       0x220c
++#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
++#define mmDP1_DP_STEER_FIFO                                                                            0x220d
++#define mmDP1_DP_STEER_FIFO_BASE_IDX                                                                   2
++#define mmDP1_DP_MSA_MISC                                                                              0x220e
++#define mmDP1_DP_MSA_MISC_BASE_IDX                                                                     2
++#define mmDP1_DP_VID_TIMING                                                                            0x2210
++#define mmDP1_DP_VID_TIMING_BASE_IDX                                                                   2
++#define mmDP1_DP_VID_N                                                                                 0x2211
++#define mmDP1_DP_VID_N_BASE_IDX                                                                        2
++#define mmDP1_DP_VID_M                                                                                 0x2212
++#define mmDP1_DP_VID_M_BASE_IDX                                                                        2
++#define mmDP1_DP_LINK_FRAMING_CNTL                                                                     0x2213
++#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
++#define mmDP1_DP_HBR2_EYE_PATTERN                                                                      0x2214
++#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
++#define mmDP1_DP_VID_MSA_VBID                                                                          0x2215
++#define mmDP1_DP_VID_MSA_VBID_BASE_IDX                                                                 2
++#define mmDP1_DP_VID_INTERRUPT_CNTL                                                                    0x2216
++#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
++#define mmDP1_DP_DPHY_CNTL                                                                             0x2217
++#define mmDP1_DP_DPHY_CNTL_BASE_IDX                                                                    2
++#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2218
++#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
++#define mmDP1_DP_DPHY_SYM0                                                                             0x2219
++#define mmDP1_DP_DPHY_SYM0_BASE_IDX                                                                    2
++#define mmDP1_DP_DPHY_SYM1                                                                             0x221a
++#define mmDP1_DP_DPHY_SYM1_BASE_IDX                                                                    2
++#define mmDP1_DP_DPHY_SYM2                                                                             0x221b
++#define mmDP1_DP_DPHY_SYM2_BASE_IDX                                                                    2
++#define mmDP1_DP_DPHY_8B10B_CNTL                                                                       0x221c
++#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
++#define mmDP1_DP_DPHY_PRBS_CNTL                                                                        0x221d
++#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
++#define mmDP1_DP_DPHY_SCRAM_CNTL                                                                       0x221e
++#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
++#define mmDP1_DP_DPHY_CRC_EN                                                                           0x221f
++#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
++#define mmDP1_DP_DPHY_CRC_CNTL                                                                         0x2220
++#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
++#define mmDP1_DP_DPHY_CRC_RESULT                                                                       0x2221
++#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
++#define mmDP1_DP_DPHY_CRC_MST_CNTL                                                                     0x2222
++#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
++#define mmDP1_DP_DPHY_CRC_MST_STATUS                                                                   0x2223
++#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
++#define mmDP1_DP_DPHY_FAST_TRAINING                                                                    0x2224
++#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
++#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2225
++#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
++#define mmDP1_DP_SEC_CNTL                                                                              0x222b
++#define mmDP1_DP_SEC_CNTL_BASE_IDX                                                                     2
++#define mmDP1_DP_SEC_CNTL1                                                                             0x222c
++#define mmDP1_DP_SEC_CNTL1_BASE_IDX                                                                    2
++#define mmDP1_DP_SEC_FRAMING1                                                                          0x222d
++#define mmDP1_DP_SEC_FRAMING1_BASE_IDX                                                                 2
++#define mmDP1_DP_SEC_FRAMING2                                                                          0x222e
++#define mmDP1_DP_SEC_FRAMING2_BASE_IDX                                                                 2
++#define mmDP1_DP_SEC_FRAMING3                                                                          0x222f
++#define mmDP1_DP_SEC_FRAMING3_BASE_IDX                                                                 2
++#define mmDP1_DP_SEC_FRAMING4                                                                          0x2230
++#define mmDP1_DP_SEC_FRAMING4_BASE_IDX                                                                 2
++#define mmDP1_DP_SEC_AUD_N                                                                             0x2231
++#define mmDP1_DP_SEC_AUD_N_BASE_IDX                                                                    2
++#define mmDP1_DP_SEC_AUD_N_READBACK                                                                    0x2232
++#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
++#define mmDP1_DP_SEC_AUD_M                                                                             0x2233
++#define mmDP1_DP_SEC_AUD_M_BASE_IDX                                                                    2
++#define mmDP1_DP_SEC_AUD_M_READBACK                                                                    0x2234
++#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
++#define mmDP1_DP_SEC_TIMESTAMP                                                                         0x2235
++#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
++#define mmDP1_DP_SEC_PACKET_CNTL                                                                       0x2236
++#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
++#define mmDP1_DP_MSE_RATE_CNTL                                                                         0x2237
++#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
++#define mmDP1_DP_MSE_RATE_UPDATE                                                                       0x2239
++#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
++#define mmDP1_DP_MSE_SAT0                                                                              0x223a
++#define mmDP1_DP_MSE_SAT0_BASE_IDX                                                                     2
++#define mmDP1_DP_MSE_SAT1                                                                              0x223b
++#define mmDP1_DP_MSE_SAT1_BASE_IDX                                                                     2
++#define mmDP1_DP_MSE_SAT2                                                                              0x223c
++#define mmDP1_DP_MSE_SAT2_BASE_IDX                                                                     2
++#define mmDP1_DP_MSE_SAT_UPDATE                                                                        0x223d
++#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
++#define mmDP1_DP_MSE_LINK_TIMING                                                                       0x223e
++#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
++#define mmDP1_DP_MSE_MISC_CNTL                                                                         0x223f
++#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
++#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2244
++#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
++#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2245
++#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
++#define mmDP1_DP_MSE_SAT0_STATUS                                                                       0x2247
++#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
++#define mmDP1_DP_MSE_SAT1_STATUS                                                                       0x2248
++#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
++#define mmDP1_DP_MSE_SAT2_STATUS                                                                       0x2249
++#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
++#define mmDP1_DP_MSA_TIMING_PARAM1                                                                     0x224c
++#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
++#define mmDP1_DP_MSA_TIMING_PARAM2                                                                     0x224d
++#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
++#define mmDP1_DP_MSA_TIMING_PARAM3                                                                     0x224e
++#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
++#define mmDP1_DP_MSA_TIMING_PARAM4                                                                     0x224f
++#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
++#define mmDP1_DP_MSO_CNTL                                                                              0x2250
++#define mmDP1_DP_MSO_CNTL_BASE_IDX                                                                     2
++#define mmDP1_DP_MSO_CNTL1                                                                             0x2251
++#define mmDP1_DP_MSO_CNTL1_BASE_IDX                                                                    2
++#define mmDP1_DP_DSC_CNTL                                                                              0x2252
++#define mmDP1_DP_DSC_CNTL_BASE_IDX                                                                     2
++#define mmDP1_DP_SEC_CNTL2                                                                             0x2253
++#define mmDP1_DP_SEC_CNTL2_BASE_IDX                                                                    2
++#define mmDP1_DP_SEC_CNTL3                                                                             0x2254
++#define mmDP1_DP_SEC_CNTL3_BASE_IDX                                                                    2
++#define mmDP1_DP_SEC_CNTL4                                                                             0x2255
++#define mmDP1_DP_SEC_CNTL4_BASE_IDX                                                                    2
++#define mmDP1_DP_SEC_CNTL5                                                                             0x2256
++#define mmDP1_DP_SEC_CNTL5_BASE_IDX                                                                    2
++#define mmDP1_DP_SEC_CNTL6                                                                             0x2257
++#define mmDP1_DP_SEC_CNTL6_BASE_IDX                                                                    2
++#define mmDP1_DP_SEC_CNTL7                                                                             0x2258
++#define mmDP1_DP_SEC_CNTL7_BASE_IDX                                                                    2
++#define mmDP1_DP_DB_CNTL                                                                               0x2259
++#define mmDP1_DP_DB_CNTL_BASE_IDX                                                                      2
++#define mmDP1_DP_MSA_VBID_MISC                                                                         0x225a
++#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX                                                                2
++#define mmDP1_DP_SEC_METADATA_TRANSMISSION                                                             0x225b
++#define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
++#define mmDP1_DP_DSC_BYTES_PER_PIXEL                                                                   0x225c
++#define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
++#define mmDP1_DP_ALPM_CNTL                                                                             0x225d
++#define mmDP1_DP_ALPM_CNTL_BASE_IDX                                                                    2
++
++
++// addressBlock: dce_dc_dio_dig2_dispdec
++// base address: 0x800
++#define mmDIG2_DIG_FE_CNTL                                                                             0x2268
++#define mmDIG2_DIG_FE_CNTL_BASE_IDX                                                                    2
++#define mmDIG2_DIG_OUTPUT_CRC_CNTL                                                                     0x2269
++#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
++#define mmDIG2_DIG_OUTPUT_CRC_RESULT                                                                   0x226a
++#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
++#define mmDIG2_DIG_CLOCK_PATTERN                                                                       0x226b
++#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
++#define mmDIG2_DIG_TEST_PATTERN                                                                        0x226c
++#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX                                                               2
++#define mmDIG2_DIG_RANDOM_PATTERN_SEED                                                                 0x226d
++#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
++#define mmDIG2_DIG_FIFO_STATUS                                                                         0x226e
++#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX                                                                2
++#define mmDIG2_HDMI_METADATA_PACKET_CONTROL                                                            0x226f
++#define mmDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2270
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
++#define mmDIG2_HDMI_CONTROL                                                                            0x2271
++#define mmDIG2_HDMI_CONTROL_BASE_IDX                                                                   2
++#define mmDIG2_HDMI_STATUS                                                                             0x2272
++#define mmDIG2_HDMI_STATUS_BASE_IDX                                                                    2
++#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL                                                               0x2273
++#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
++#define mmDIG2_HDMI_ACR_PACKET_CONTROL                                                                 0x2274
++#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
++#define mmDIG2_HDMI_VBI_PACKET_CONTROL                                                                 0x2275
++#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
++#define mmDIG2_HDMI_INFOFRAME_CONTROL0                                                                 0x2276
++#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
++#define mmDIG2_HDMI_INFOFRAME_CONTROL1                                                                 0x2277
++#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2278
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
++#define mmDIG2_AFMT_INTERRUPT_STATUS                                                                   0x2279
++#define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
++#define mmDIG2_HDMI_GC                                                                                 0x227b
++#define mmDIG2_HDMI_GC_BASE_IDX                                                                        2
++#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2                                                              0x227c
++#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
++#define mmDIG2_AFMT_ISRC1_0                                                                            0x227d
++#define mmDIG2_AFMT_ISRC1_0_BASE_IDX                                                                   2
++#define mmDIG2_AFMT_ISRC1_1                                                                            0x227e
++#define mmDIG2_AFMT_ISRC1_1_BASE_IDX                                                                   2
++#define mmDIG2_AFMT_ISRC1_2                                                                            0x227f
++#define mmDIG2_AFMT_ISRC1_2_BASE_IDX                                                                   2
++#define mmDIG2_AFMT_ISRC1_3                                                                            0x2280
++#define mmDIG2_AFMT_ISRC1_3_BASE_IDX                                                                   2
++#define mmDIG2_AFMT_ISRC1_4                                                                            0x2281
++#define mmDIG2_AFMT_ISRC1_4_BASE_IDX                                                                   2
++#define mmDIG2_AFMT_ISRC2_0                                                                            0x2282
++#define mmDIG2_AFMT_ISRC2_0_BASE_IDX                                                                   2
++#define mmDIG2_AFMT_ISRC2_1                                                                            0x2283
++#define mmDIG2_AFMT_ISRC2_1_BASE_IDX                                                                   2
++#define mmDIG2_AFMT_ISRC2_2                                                                            0x2284
++#define mmDIG2_AFMT_ISRC2_2_BASE_IDX                                                                   2
++#define mmDIG2_AFMT_ISRC2_3                                                                            0x2285
++#define mmDIG2_AFMT_ISRC2_3_BASE_IDX                                                                   2
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2286
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2287
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
++#define mmDIG2_HDMI_DB_CONTROL                                                                         0x2288
++#define mmDIG2_HDMI_DB_CONTROL_BASE_IDX                                                                2
++#define mmDIG2_DME_CONTROL                                                                             0x2289
++#define mmDIG2_DME_CONTROL_BASE_IDX                                                                    2
++#define mmDIG2_AFMT_MPEG_INFO0                                                                         0x228a
++#define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX                                                                2
++#define mmDIG2_AFMT_MPEG_INFO1                                                                         0x228b
++#define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX                                                                2
++#define mmDIG2_AFMT_GENERIC_HDR                                                                        0x228c
++#define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX                                                               2
++#define mmDIG2_AFMT_GENERIC_0                                                                          0x228d
++#define mmDIG2_AFMT_GENERIC_0_BASE_IDX                                                                 2
++#define mmDIG2_AFMT_GENERIC_1                                                                          0x228e
++#define mmDIG2_AFMT_GENERIC_1_BASE_IDX                                                                 2
++#define mmDIG2_AFMT_GENERIC_2                                                                          0x228f
++#define mmDIG2_AFMT_GENERIC_2_BASE_IDX                                                                 2
++#define mmDIG2_AFMT_GENERIC_3                                                                          0x2290
++#define mmDIG2_AFMT_GENERIC_3_BASE_IDX                                                                 2
++#define mmDIG2_AFMT_GENERIC_4                                                                          0x2291
++#define mmDIG2_AFMT_GENERIC_4_BASE_IDX                                                                 2
++#define mmDIG2_AFMT_GENERIC_5                                                                          0x2292
++#define mmDIG2_AFMT_GENERIC_5_BASE_IDX                                                                 2
++#define mmDIG2_AFMT_GENERIC_6                                                                          0x2293
++#define mmDIG2_AFMT_GENERIC_6_BASE_IDX                                                                 2
++#define mmDIG2_AFMT_GENERIC_7                                                                          0x2294
++#define mmDIG2_AFMT_GENERIC_7_BASE_IDX                                                                 2
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2295
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
++#define mmDIG2_HDMI_ACR_32_0                                                                           0x2296
++#define mmDIG2_HDMI_ACR_32_0_BASE_IDX                                                                  2
++#define mmDIG2_HDMI_ACR_32_1                                                                           0x2297
++#define mmDIG2_HDMI_ACR_32_1_BASE_IDX                                                                  2
++#define mmDIG2_HDMI_ACR_44_0                                                                           0x2298
++#define mmDIG2_HDMI_ACR_44_0_BASE_IDX                                                                  2
++#define mmDIG2_HDMI_ACR_44_1                                                                           0x2299
++#define mmDIG2_HDMI_ACR_44_1_BASE_IDX                                                                  2
++#define mmDIG2_HDMI_ACR_48_0                                                                           0x229a
++#define mmDIG2_HDMI_ACR_48_0_BASE_IDX                                                                  2
++#define mmDIG2_HDMI_ACR_48_1                                                                           0x229b
++#define mmDIG2_HDMI_ACR_48_1_BASE_IDX                                                                  2
++#define mmDIG2_HDMI_ACR_STATUS_0                                                                       0x229c
++#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
++#define mmDIG2_HDMI_ACR_STATUS_1                                                                       0x229d
++#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
++#define mmDIG2_AFMT_AUDIO_INFO0                                                                        0x229e
++#define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
++#define mmDIG2_AFMT_AUDIO_INFO1                                                                        0x229f
++#define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
++#define mmDIG2_AFMT_60958_0                                                                            0x22a0
++#define mmDIG2_AFMT_60958_0_BASE_IDX                                                                   2
++#define mmDIG2_AFMT_60958_1                                                                            0x22a1
++#define mmDIG2_AFMT_60958_1_BASE_IDX                                                                   2
++#define mmDIG2_AFMT_AUDIO_CRC_CONTROL                                                                  0x22a2
++#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
++#define mmDIG2_AFMT_RAMP_CONTROL0                                                                      0x22a3
++#define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
++#define mmDIG2_AFMT_RAMP_CONTROL1                                                                      0x22a4
++#define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
++#define mmDIG2_AFMT_RAMP_CONTROL2                                                                      0x22a5
++#define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
++#define mmDIG2_AFMT_RAMP_CONTROL3                                                                      0x22a6
++#define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
++#define mmDIG2_AFMT_60958_2                                                                            0x22a7
++#define mmDIG2_AFMT_60958_2_BASE_IDX                                                                   2
++#define mmDIG2_AFMT_AUDIO_CRC_RESULT                                                                   0x22a8
++#define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
++#define mmDIG2_AFMT_STATUS                                                                             0x22a9
++#define mmDIG2_AFMT_STATUS_BASE_IDX                                                                    2
++#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL                                                               0x22aa
++#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
++#define mmDIG2_AFMT_VBI_PACKET_CONTROL                                                                 0x22ab
++#define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
++#define mmDIG2_AFMT_INFOFRAME_CONTROL0                                                                 0x22ac
++#define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
++#define mmDIG2_AFMT_AUDIO_SRC_CONTROL                                                                  0x22ad
++#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
++#define mmDIG2_DIG_BE_CNTL                                                                             0x22af
++#define mmDIG2_DIG_BE_CNTL_BASE_IDX                                                                    2
++#define mmDIG2_DIG_BE_EN_CNTL                                                                          0x22b0
++#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
++#define mmDIG2_TMDS_CNTL                                                                               0x22d3
++#define mmDIG2_TMDS_CNTL_BASE_IDX                                                                      2
++#define mmDIG2_TMDS_CONTROL_CHAR                                                                       0x22d4
++#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
++#define mmDIG2_TMDS_CONTROL0_FEEDBACK                                                                  0x22d5
++#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
++#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL                                                                 0x22d6
++#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
++#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x22d7
++#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
++#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x22d8
++#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
++#define mmDIG2_TMDS_CTL_BITS                                                                           0x22da
++#define mmDIG2_TMDS_CTL_BITS_BASE_IDX                                                                  2
++#define mmDIG2_TMDS_DCBALANCER_CONTROL                                                                 0x22db
++#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
++#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR                                                                0x22dc
++#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
++#define mmDIG2_TMDS_CTL0_1_GEN_CNTL                                                                    0x22dd
++#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
++#define mmDIG2_TMDS_CTL2_3_GEN_CNTL                                                                    0x22de
++#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
++#define mmDIG2_DIG_VERSION                                                                             0x22e0
++#define mmDIG2_DIG_VERSION_BASE_IDX                                                                    2
++#define mmDIG2_DIG_LANE_ENABLE                                                                         0x22e1
++#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX                                                                2
++#define mmDIG2_AFMT_CNTL                                                                               0x22e6
++#define mmDIG2_AFMT_CNTL_BASE_IDX                                                                      2
++#define mmDIG2_AFMT_VBI_PACKET_CONTROL1                                                                0x22e7
++#define mmDIG2_AFMT_VBI_PACKET_CONTROL1_BASE_IDX                                                       2
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5                                                            0x22f6
++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
++#define mmDIG2_FORCE_DIG_DISABLE                                                                       0x22f7
++#define mmDIG2_FORCE_DIG_DISABLE_BASE_IDX                                                              2
++
++
++// addressBlock: dce_dc_dio_dp2_dispdec
++// base address: 0x800
++#define mmDP2_DP_LINK_CNTL                                                                             0x2308
++#define mmDP2_DP_LINK_CNTL_BASE_IDX                                                                    2
++#define mmDP2_DP_PIXEL_FORMAT                                                                          0x2309
++#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
++#define mmDP2_DP_MSA_COLORIMETRY                                                                       0x230a
++#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
++#define mmDP2_DP_CONFIG                                                                                0x230b
++#define mmDP2_DP_CONFIG_BASE_IDX                                                                       2
++#define mmDP2_DP_VID_STREAM_CNTL                                                                       0x230c
++#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
++#define mmDP2_DP_STEER_FIFO                                                                            0x230d
++#define mmDP2_DP_STEER_FIFO_BASE_IDX                                                                   2
++#define mmDP2_DP_MSA_MISC                                                                              0x230e
++#define mmDP2_DP_MSA_MISC_BASE_IDX                                                                     2
++#define mmDP2_DP_VID_TIMING                                                                            0x2310
++#define mmDP2_DP_VID_TIMING_BASE_IDX                                                                   2
++#define mmDP2_DP_VID_N                                                                                 0x2311
++#define mmDP2_DP_VID_N_BASE_IDX                                                                        2
++#define mmDP2_DP_VID_M                                                                                 0x2312
++#define mmDP2_DP_VID_M_BASE_IDX                                                                        2
++#define mmDP2_DP_LINK_FRAMING_CNTL                                                                     0x2313
++#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
++#define mmDP2_DP_HBR2_EYE_PATTERN                                                                      0x2314
++#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
++#define mmDP2_DP_VID_MSA_VBID                                                                          0x2315
++#define mmDP2_DP_VID_MSA_VBID_BASE_IDX                                                                 2
++#define mmDP2_DP_VID_INTERRUPT_CNTL                                                                    0x2316
++#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
++#define mmDP2_DP_DPHY_CNTL                                                                             0x2317
++#define mmDP2_DP_DPHY_CNTL_BASE_IDX                                                                    2
++#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2318
++#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
++#define mmDP2_DP_DPHY_SYM0                                                                             0x2319
++#define mmDP2_DP_DPHY_SYM0_BASE_IDX                                                                    2
++#define mmDP2_DP_DPHY_SYM1                                                                             0x231a
++#define mmDP2_DP_DPHY_SYM1_BASE_IDX                                                                    2
++#define mmDP2_DP_DPHY_SYM2                                                                             0x231b
++#define mmDP2_DP_DPHY_SYM2_BASE_IDX                                                                    2
++#define mmDP2_DP_DPHY_8B10B_CNTL                                                                       0x231c
++#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
++#define mmDP2_DP_DPHY_PRBS_CNTL                                                                        0x231d
++#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
++#define mmDP2_DP_DPHY_SCRAM_CNTL                                                                       0x231e
++#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
++#define mmDP2_DP_DPHY_CRC_EN                                                                           0x231f
++#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
++#define mmDP2_DP_DPHY_CRC_CNTL                                                                         0x2320
++#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
++#define mmDP2_DP_DPHY_CRC_RESULT                                                                       0x2321
++#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
++#define mmDP2_DP_DPHY_CRC_MST_CNTL                                                                     0x2322
++#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
++#define mmDP2_DP_DPHY_CRC_MST_STATUS                                                                   0x2323
++#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
++#define mmDP2_DP_DPHY_FAST_TRAINING                                                                    0x2324
++#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
++#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2325
++#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
++#define mmDP2_DP_SEC_CNTL                                                                              0x232b
++#define mmDP2_DP_SEC_CNTL_BASE_IDX                                                                     2
++#define mmDP2_DP_SEC_CNTL1                                                                             0x232c
++#define mmDP2_DP_SEC_CNTL1_BASE_IDX                                                                    2
++#define mmDP2_DP_SEC_FRAMING1                                                                          0x232d
++#define mmDP2_DP_SEC_FRAMING1_BASE_IDX                                                                 2
++#define mmDP2_DP_SEC_FRAMING2                                                                          0x232e
++#define mmDP2_DP_SEC_FRAMING2_BASE_IDX                                                                 2
++#define mmDP2_DP_SEC_FRAMING3                                                                          0x232f
++#define mmDP2_DP_SEC_FRAMING3_BASE_IDX                                                                 2
++#define mmDP2_DP_SEC_FRAMING4                                                                          0x2330
++#define mmDP2_DP_SEC_FRAMING4_BASE_IDX                                                                 2
++#define mmDP2_DP_SEC_AUD_N                                                                             0x2331
++#define mmDP2_DP_SEC_AUD_N_BASE_IDX                                                                    2
++#define mmDP2_DP_SEC_AUD_N_READBACK                                                                    0x2332
++#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
++#define mmDP2_DP_SEC_AUD_M                                                                             0x2333
++#define mmDP2_DP_SEC_AUD_M_BASE_IDX                                                                    2
++#define mmDP2_DP_SEC_AUD_M_READBACK                                                                    0x2334
++#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
++#define mmDP2_DP_SEC_TIMESTAMP                                                                         0x2335
++#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
++#define mmDP2_DP_SEC_PACKET_CNTL                                                                       0x2336
++#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
++#define mmDP2_DP_MSE_RATE_CNTL                                                                         0x2337
++#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
++#define mmDP2_DP_MSE_RATE_UPDATE                                                                       0x2339
++#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
++#define mmDP2_DP_MSE_SAT0                                                                              0x233a
++#define mmDP2_DP_MSE_SAT0_BASE_IDX                                                                     2
++#define mmDP2_DP_MSE_SAT1                                                                              0x233b
++#define mmDP2_DP_MSE_SAT1_BASE_IDX                                                                     2
++#define mmDP2_DP_MSE_SAT2                                                                              0x233c
++#define mmDP2_DP_MSE_SAT2_BASE_IDX                                                                     2
++#define mmDP2_DP_MSE_SAT_UPDATE                                                                        0x233d
++#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
++#define mmDP2_DP_MSE_LINK_TIMING                                                                       0x233e
++#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
++#define mmDP2_DP_MSE_MISC_CNTL                                                                         0x233f
++#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
++#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2344
++#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
++#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2345
++#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
++#define mmDP2_DP_MSE_SAT0_STATUS                                                                       0x2347
++#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
++#define mmDP2_DP_MSE_SAT1_STATUS                                                                       0x2348
++#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
++#define mmDP2_DP_MSE_SAT2_STATUS                                                                       0x2349
++#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
++#define mmDP2_DP_MSA_TIMING_PARAM1                                                                     0x234c
++#define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
++#define mmDP2_DP_MSA_TIMING_PARAM2                                                                     0x234d
++#define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
++#define mmDP2_DP_MSA_TIMING_PARAM3                                                                     0x234e
++#define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
++#define mmDP2_DP_MSA_TIMING_PARAM4                                                                     0x234f
++#define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
++#define mmDP2_DP_MSO_CNTL                                                                              0x2350
++#define mmDP2_DP_MSO_CNTL_BASE_IDX                                                                     2
++#define mmDP2_DP_MSO_CNTL1                                                                             0x2351
++#define mmDP2_DP_MSO_CNTL1_BASE_IDX                                                                    2
++#define mmDP2_DP_DSC_CNTL                                                                              0x2352
++#define mmDP2_DP_DSC_CNTL_BASE_IDX                                                                     2
++#define mmDP2_DP_SEC_CNTL2                                                                             0x2353
++#define mmDP2_DP_SEC_CNTL2_BASE_IDX                                                                    2
++#define mmDP2_DP_SEC_CNTL3                                                                             0x2354
++#define mmDP2_DP_SEC_CNTL3_BASE_IDX                                                                    2
++#define mmDP2_DP_SEC_CNTL4                                                                             0x2355
++#define mmDP2_DP_SEC_CNTL4_BASE_IDX                                                                    2
++#define mmDP2_DP_SEC_CNTL5                                                                             0x2356
++#define mmDP2_DP_SEC_CNTL5_BASE_IDX                                                                    2
++#define mmDP2_DP_SEC_CNTL6                                                                             0x2357
++#define mmDP2_DP_SEC_CNTL6_BASE_IDX                                                                    2
++#define mmDP2_DP_SEC_CNTL7                                                                             0x2358
++#define mmDP2_DP_SEC_CNTL7_BASE_IDX                                                                    2
++#define mmDP2_DP_DB_CNTL                                                                               0x2359
++#define mmDP2_DP_DB_CNTL_BASE_IDX                                                                      2
++#define mmDP2_DP_MSA_VBID_MISC                                                                         0x235a
++#define mmDP2_DP_MSA_VBID_MISC_BASE_IDX                                                                2
++#define mmDP2_DP_SEC_METADATA_TRANSMISSION                                                             0x235b
++#define mmDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
++#define mmDP2_DP_DSC_BYTES_PER_PIXEL                                                                   0x235c
++#define mmDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
++#define mmDP2_DP_ALPM_CNTL                                                                             0x235d
++#define mmDP2_DP_ALPM_CNTL_BASE_IDX                                                                    2
++
++
++// addressBlock: dce_dc_dio_dig3_dispdec
++// base address: 0xc00
++#define mmDIG3_DIG_FE_CNTL                                                                             0x2368
++#define mmDIG3_DIG_FE_CNTL_BASE_IDX                                                                    2
++#define mmDIG3_DIG_OUTPUT_CRC_CNTL                                                                     0x2369
++#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
++#define mmDIG3_DIG_OUTPUT_CRC_RESULT                                                                   0x236a
++#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
++#define mmDIG3_DIG_CLOCK_PATTERN                                                                       0x236b
++#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
++#define mmDIG3_DIG_TEST_PATTERN                                                                        0x236c
++#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX                                                               2
++#define mmDIG3_DIG_RANDOM_PATTERN_SEED                                                                 0x236d
++#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
++#define mmDIG3_DIG_FIFO_STATUS                                                                         0x236e
++#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX                                                                2
++#define mmDIG3_HDMI_METADATA_PACKET_CONTROL                                                            0x236f
++#define mmDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2370
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
++#define mmDIG3_HDMI_CONTROL                                                                            0x2371
++#define mmDIG3_HDMI_CONTROL_BASE_IDX                                                                   2
++#define mmDIG3_HDMI_STATUS                                                                             0x2372
++#define mmDIG3_HDMI_STATUS_BASE_IDX                                                                    2
++#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL                                                               0x2373
++#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
++#define mmDIG3_HDMI_ACR_PACKET_CONTROL                                                                 0x2374
++#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
++#define mmDIG3_HDMI_VBI_PACKET_CONTROL                                                                 0x2375
++#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
++#define mmDIG3_HDMI_INFOFRAME_CONTROL0                                                                 0x2376
++#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
++#define mmDIG3_HDMI_INFOFRAME_CONTROL1                                                                 0x2377
++#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2378
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
++#define mmDIG3_AFMT_INTERRUPT_STATUS                                                                   0x2379
++#define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
++#define mmDIG3_HDMI_GC                                                                                 0x237b
++#define mmDIG3_HDMI_GC_BASE_IDX                                                                        2
++#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2                                                              0x237c
++#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
++#define mmDIG3_AFMT_ISRC1_0                                                                            0x237d
++#define mmDIG3_AFMT_ISRC1_0_BASE_IDX                                                                   2
++#define mmDIG3_AFMT_ISRC1_1                                                                            0x237e
++#define mmDIG3_AFMT_ISRC1_1_BASE_IDX                                                                   2
++#define mmDIG3_AFMT_ISRC1_2                                                                            0x237f
++#define mmDIG3_AFMT_ISRC1_2_BASE_IDX                                                                   2
++#define mmDIG3_AFMT_ISRC1_3                                                                            0x2380
++#define mmDIG3_AFMT_ISRC1_3_BASE_IDX                                                                   2
++#define mmDIG3_AFMT_ISRC1_4                                                                            0x2381
++#define mmDIG3_AFMT_ISRC1_4_BASE_IDX                                                                   2
++#define mmDIG3_AFMT_ISRC2_0                                                                            0x2382
++#define mmDIG3_AFMT_ISRC2_0_BASE_IDX                                                                   2
++#define mmDIG3_AFMT_ISRC2_1                                                                            0x2383
++#define mmDIG3_AFMT_ISRC2_1_BASE_IDX                                                                   2
++#define mmDIG3_AFMT_ISRC2_2                                                                            0x2384
++#define mmDIG3_AFMT_ISRC2_2_BASE_IDX                                                                   2
++#define mmDIG3_AFMT_ISRC2_3                                                                            0x2385
++#define mmDIG3_AFMT_ISRC2_3_BASE_IDX                                                                   2
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2386
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2387
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
++#define mmDIG3_HDMI_DB_CONTROL                                                                         0x2388
++#define mmDIG3_HDMI_DB_CONTROL_BASE_IDX                                                                2
++#define mmDIG3_DME_CONTROL                                                                             0x2389
++#define mmDIG3_DME_CONTROL_BASE_IDX                                                                    2
++#define mmDIG3_AFMT_MPEG_INFO0                                                                         0x238a
++#define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX                                                                2
++#define mmDIG3_AFMT_MPEG_INFO1                                                                         0x238b
++#define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX                                                                2
++#define mmDIG3_AFMT_GENERIC_HDR                                                                        0x238c
++#define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX                                                               2
++#define mmDIG3_AFMT_GENERIC_0                                                                          0x238d
++#define mmDIG3_AFMT_GENERIC_0_BASE_IDX                                                                 2
++#define mmDIG3_AFMT_GENERIC_1                                                                          0x238e
++#define mmDIG3_AFMT_GENERIC_1_BASE_IDX                                                                 2
++#define mmDIG3_AFMT_GENERIC_2                                                                          0x238f
++#define mmDIG3_AFMT_GENERIC_2_BASE_IDX                                                                 2
++#define mmDIG3_AFMT_GENERIC_3                                                                          0x2390
++#define mmDIG3_AFMT_GENERIC_3_BASE_IDX                                                                 2
++#define mmDIG3_AFMT_GENERIC_4                                                                          0x2391
++#define mmDIG3_AFMT_GENERIC_4_BASE_IDX                                                                 2
++#define mmDIG3_AFMT_GENERIC_5                                                                          0x2392
++#define mmDIG3_AFMT_GENERIC_5_BASE_IDX                                                                 2
++#define mmDIG3_AFMT_GENERIC_6                                                                          0x2393
++#define mmDIG3_AFMT_GENERIC_6_BASE_IDX                                                                 2
++#define mmDIG3_AFMT_GENERIC_7                                                                          0x2394
++#define mmDIG3_AFMT_GENERIC_7_BASE_IDX                                                                 2
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2395
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
++#define mmDIG3_HDMI_ACR_32_0                                                                           0x2396
++#define mmDIG3_HDMI_ACR_32_0_BASE_IDX                                                                  2
++#define mmDIG3_HDMI_ACR_32_1                                                                           0x2397
++#define mmDIG3_HDMI_ACR_32_1_BASE_IDX                                                                  2
++#define mmDIG3_HDMI_ACR_44_0                                                                           0x2398
++#define mmDIG3_HDMI_ACR_44_0_BASE_IDX                                                                  2
++#define mmDIG3_HDMI_ACR_44_1                                                                           0x2399
++#define mmDIG3_HDMI_ACR_44_1_BASE_IDX                                                                  2
++#define mmDIG3_HDMI_ACR_48_0                                                                           0x239a
++#define mmDIG3_HDMI_ACR_48_0_BASE_IDX                                                                  2
++#define mmDIG3_HDMI_ACR_48_1                                                                           0x239b
++#define mmDIG3_HDMI_ACR_48_1_BASE_IDX                                                                  2
++#define mmDIG3_HDMI_ACR_STATUS_0                                                                       0x239c
++#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
++#define mmDIG3_HDMI_ACR_STATUS_1                                                                       0x239d
++#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
++#define mmDIG3_AFMT_AUDIO_INFO0                                                                        0x239e
++#define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
++#define mmDIG3_AFMT_AUDIO_INFO1                                                                        0x239f
++#define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
++#define mmDIG3_AFMT_60958_0                                                                            0x23a0
++#define mmDIG3_AFMT_60958_0_BASE_IDX                                                                   2
++#define mmDIG3_AFMT_60958_1                                                                            0x23a1
++#define mmDIG3_AFMT_60958_1_BASE_IDX                                                                   2
++#define mmDIG3_AFMT_AUDIO_CRC_CONTROL                                                                  0x23a2
++#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
++#define mmDIG3_AFMT_RAMP_CONTROL0                                                                      0x23a3
++#define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
++#define mmDIG3_AFMT_RAMP_CONTROL1                                                                      0x23a4
++#define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
++#define mmDIG3_AFMT_RAMP_CONTROL2                                                                      0x23a5
++#define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
++#define mmDIG3_AFMT_RAMP_CONTROL3                                                                      0x23a6
++#define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
++#define mmDIG3_AFMT_60958_2                                                                            0x23a7
++#define mmDIG3_AFMT_60958_2_BASE_IDX                                                                   2
++#define mmDIG3_AFMT_AUDIO_CRC_RESULT                                                                   0x23a8
++#define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
++#define mmDIG3_AFMT_STATUS                                                                             0x23a9
++#define mmDIG3_AFMT_STATUS_BASE_IDX                                                                    2
++#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL                                                               0x23aa
++#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
++#define mmDIG3_AFMT_VBI_PACKET_CONTROL                                                                 0x23ab
++#define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
++#define mmDIG3_AFMT_INFOFRAME_CONTROL0                                                                 0x23ac
++#define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
++#define mmDIG3_AFMT_AUDIO_SRC_CONTROL                                                                  0x23ad
++#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
++#define mmDIG3_DIG_BE_CNTL                                                                             0x23af
++#define mmDIG3_DIG_BE_CNTL_BASE_IDX                                                                    2
++#define mmDIG3_DIG_BE_EN_CNTL                                                                          0x23b0
++#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
++#define mmDIG3_TMDS_CNTL                                                                               0x23d3
++#define mmDIG3_TMDS_CNTL_BASE_IDX                                                                      2
++#define mmDIG3_TMDS_CONTROL_CHAR                                                                       0x23d4
++#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
++#define mmDIG3_TMDS_CONTROL0_FEEDBACK                                                                  0x23d5
++#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
++#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL                                                                 0x23d6
++#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
++#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x23d7
++#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
++#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x23d8
++#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
++#define mmDIG3_TMDS_CTL_BITS                                                                           0x23da
++#define mmDIG3_TMDS_CTL_BITS_BASE_IDX                                                                  2
++#define mmDIG3_TMDS_DCBALANCER_CONTROL                                                                 0x23db
++#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
++#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR                                                                0x23dc
++#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
++#define mmDIG3_TMDS_CTL0_1_GEN_CNTL                                                                    0x23dd
++#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
++#define mmDIG3_TMDS_CTL2_3_GEN_CNTL                                                                    0x23de
++#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
++#define mmDIG3_DIG_VERSION                                                                             0x23e0
++#define mmDIG3_DIG_VERSION_BASE_IDX                                                                    2
++#define mmDIG3_DIG_LANE_ENABLE                                                                         0x23e1
++#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX                                                                2
++#define mmDIG3_AFMT_CNTL                                                                               0x23e6
++#define mmDIG3_AFMT_CNTL_BASE_IDX                                                                      2
++#define mmDIG3_AFMT_VBI_PACKET_CONTROL1                                                                0x23e7
++#define mmDIG3_AFMT_VBI_PACKET_CONTROL1_BASE_IDX                                                       2
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5                                                            0x23f6
++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
++#define mmDIG3_FORCE_DIG_DISABLE                                                                       0x23f7
++#define mmDIG3_FORCE_DIG_DISABLE_BASE_IDX                                                              2
++
++
++// addressBlock: dce_dc_dio_dp3_dispdec
++// base address: 0xc00
++#define mmDP3_DP_LINK_CNTL                                                                             0x2408
++#define mmDP3_DP_LINK_CNTL_BASE_IDX                                                                    2
++#define mmDP3_DP_PIXEL_FORMAT                                                                          0x2409
++#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
++#define mmDP3_DP_MSA_COLORIMETRY                                                                       0x240a
++#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
++#define mmDP3_DP_CONFIG                                                                                0x240b
++#define mmDP3_DP_CONFIG_BASE_IDX                                                                       2
++#define mmDP3_DP_VID_STREAM_CNTL                                                                       0x240c
++#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
++#define mmDP3_DP_STEER_FIFO                                                                            0x240d
++#define mmDP3_DP_STEER_FIFO_BASE_IDX                                                                   2
++#define mmDP3_DP_MSA_MISC                                                                              0x240e
++#define mmDP3_DP_MSA_MISC_BASE_IDX                                                                     2
++#define mmDP3_DP_VID_TIMING                                                                            0x2410
++#define mmDP3_DP_VID_TIMING_BASE_IDX                                                                   2
++#define mmDP3_DP_VID_N                                                                                 0x2411
++#define mmDP3_DP_VID_N_BASE_IDX                                                                        2
++#define mmDP3_DP_VID_M                                                                                 0x2412
++#define mmDP3_DP_VID_M_BASE_IDX                                                                        2
++#define mmDP3_DP_LINK_FRAMING_CNTL                                                                     0x2413
++#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
++#define mmDP3_DP_HBR2_EYE_PATTERN                                                                      0x2414
++#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
++#define mmDP3_DP_VID_MSA_VBID                                                                          0x2415
++#define mmDP3_DP_VID_MSA_VBID_BASE_IDX                                                                 2
++#define mmDP3_DP_VID_INTERRUPT_CNTL                                                                    0x2416
++#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
++#define mmDP3_DP_DPHY_CNTL                                                                             0x2417
++#define mmDP3_DP_DPHY_CNTL_BASE_IDX                                                                    2
++#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2418
++#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
++#define mmDP3_DP_DPHY_SYM0                                                                             0x2419
++#define mmDP3_DP_DPHY_SYM0_BASE_IDX                                                                    2
++#define mmDP3_DP_DPHY_SYM1                                                                             0x241a
++#define mmDP3_DP_DPHY_SYM1_BASE_IDX                                                                    2
++#define mmDP3_DP_DPHY_SYM2                                                                             0x241b
++#define mmDP3_DP_DPHY_SYM2_BASE_IDX                                                                    2
++#define mmDP3_DP_DPHY_8B10B_CNTL                                                                       0x241c
++#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
++#define mmDP3_DP_DPHY_PRBS_CNTL                                                                        0x241d
++#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
++#define mmDP3_DP_DPHY_SCRAM_CNTL                                                                       0x241e
++#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
++#define mmDP3_DP_DPHY_CRC_EN                                                                           0x241f
++#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
++#define mmDP3_DP_DPHY_CRC_CNTL                                                                         0x2420
++#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
++#define mmDP3_DP_DPHY_CRC_RESULT                                                                       0x2421
++#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
++#define mmDP3_DP_DPHY_CRC_MST_CNTL                                                                     0x2422
++#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
++#define mmDP3_DP_DPHY_CRC_MST_STATUS                                                                   0x2423
++#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
++#define mmDP3_DP_DPHY_FAST_TRAINING                                                                    0x2424
++#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
++#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2425
++#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
++#define mmDP3_DP_SEC_CNTL                                                                              0x242b
++#define mmDP3_DP_SEC_CNTL_BASE_IDX                                                                     2
++#define mmDP3_DP_SEC_CNTL1                                                                             0x242c
++#define mmDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2
++#define mmDP3_DP_SEC_FRAMING1                                                                          0x242d
++#define mmDP3_DP_SEC_FRAMING1_BASE_IDX                                                                 2
++#define mmDP3_DP_SEC_FRAMING2                                                                          0x242e
++#define mmDP3_DP_SEC_FRAMING2_BASE_IDX                                                                 2
++#define mmDP3_DP_SEC_FRAMING3                                                                          0x242f
++#define mmDP3_DP_SEC_FRAMING3_BASE_IDX                                                                 2
++#define mmDP3_DP_SEC_FRAMING4                                                                          0x2430
++#define mmDP3_DP_SEC_FRAMING4_BASE_IDX                                                                 2
++#define mmDP3_DP_SEC_AUD_N                                                                             0x2431
++#define mmDP3_DP_SEC_AUD_N_BASE_IDX                                                                    2
++#define mmDP3_DP_SEC_AUD_N_READBACK                                                                    0x2432
++#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
++#define mmDP3_DP_SEC_AUD_M                                                                             0x2433
++#define mmDP3_DP_SEC_AUD_M_BASE_IDX                                                                    2
++#define mmDP3_DP_SEC_AUD_M_READBACK                                                                    0x2434
++#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
++#define mmDP3_DP_SEC_TIMESTAMP                                                                         0x2435
++#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
++#define mmDP3_DP_SEC_PACKET_CNTL                                                                       0x2436
++#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
++#define mmDP3_DP_MSE_RATE_CNTL                                                                         0x2437
++#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
++#define mmDP3_DP_MSE_RATE_UPDATE                                                                       0x2439
++#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
++#define mmDP3_DP_MSE_SAT0                                                                              0x243a
++#define mmDP3_DP_MSE_SAT0_BASE_IDX                                                                     2
++#define mmDP3_DP_MSE_SAT1                                                                              0x243b
++#define mmDP3_DP_MSE_SAT1_BASE_IDX                                                                     2
++#define mmDP3_DP_MSE_SAT2                                                                              0x243c
++#define mmDP3_DP_MSE_SAT2_BASE_IDX                                                                     2
++#define mmDP3_DP_MSE_SAT_UPDATE                                                                        0x243d
++#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
++#define mmDP3_DP_MSE_LINK_TIMING                                                                       0x243e
++#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
++#define mmDP3_DP_MSE_MISC_CNTL                                                                         0x243f
++#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
++#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2444
++#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
++#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2445
++#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
++#define mmDP3_DP_MSE_SAT0_STATUS                                                                       0x2447
++#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
++#define mmDP3_DP_MSE_SAT1_STATUS                                                                       0x2448
++#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
++#define mmDP3_DP_MSE_SAT2_STATUS                                                                       0x2449
++#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
++#define mmDP3_DP_MSA_TIMING_PARAM1                                                                     0x244c
++#define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
++#define mmDP3_DP_MSA_TIMING_PARAM2                                                                     0x244d
++#define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
++#define mmDP3_DP_MSA_TIMING_PARAM3                                                                     0x244e
++#define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
++#define mmDP3_DP_MSA_TIMING_PARAM4                                                                     0x244f
++#define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
++#define mmDP3_DP_MSO_CNTL                                                                              0x2450
++#define mmDP3_DP_MSO_CNTL_BASE_IDX                                                                     2
++#define mmDP3_DP_MSO_CNTL1                                                                             0x2451
++#define mmDP3_DP_MSO_CNTL1_BASE_IDX                                                                    2
++#define mmDP3_DP_DSC_CNTL                                                                              0x2452
++#define mmDP3_DP_DSC_CNTL_BASE_IDX                                                                     2
++#define mmDP3_DP_SEC_CNTL2                                                                             0x2453
++#define mmDP3_DP_SEC_CNTL2_BASE_IDX                                                                    2
++#define mmDP3_DP_SEC_CNTL3                                                                             0x2454
++#define mmDP3_DP_SEC_CNTL3_BASE_IDX                                                                    2
++#define mmDP3_DP_SEC_CNTL4                                                                             0x2455
++#define mmDP3_DP_SEC_CNTL4_BASE_IDX                                                                    2
++#define mmDP3_DP_SEC_CNTL5                                                                             0x2456
++#define mmDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2
++#define mmDP3_DP_SEC_CNTL6                                                                             0x2457
++#define mmDP3_DP_SEC_CNTL6_BASE_IDX                                                                    2
++#define mmDP3_DP_SEC_CNTL7                                                                             0x2458
++#define mmDP3_DP_SEC_CNTL7_BASE_IDX                                                                    2
++#define mmDP3_DP_DB_CNTL                                                                               0x2459
++#define mmDP3_DP_DB_CNTL_BASE_IDX                                                                      2
++#define mmDP3_DP_MSA_VBID_MISC                                                                         0x245a
++#define mmDP3_DP_MSA_VBID_MISC_BASE_IDX                                                                2
++#define mmDP3_DP_SEC_METADATA_TRANSMISSION                                                             0x245b
++#define mmDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
++#define mmDP3_DP_DSC_BYTES_PER_PIXEL                                                                   0x245c
++#define mmDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
++#define mmDP3_DP_ALPM_CNTL                                                                             0x245d
++#define mmDP3_DP_ALPM_CNTL_BASE_IDX                                                                    2
++
++
++// addressBlock: dce_dc_dio_dig4_dispdec
++// base address: 0x1000
++#define mmDIG4_DIG_FE_CNTL                                                                             0x2468
++#define mmDIG4_DIG_FE_CNTL_BASE_IDX                                                                    2
++#define mmDIG4_DIG_OUTPUT_CRC_CNTL                                                                     0x2469
++#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
++#define mmDIG4_DIG_OUTPUT_CRC_RESULT                                                                   0x246a
++#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
++#define mmDIG4_DIG_CLOCK_PATTERN                                                                       0x246b
++#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
++#define mmDIG4_DIG_TEST_PATTERN                                                                        0x246c
++#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX                                                               2
++#define mmDIG4_DIG_RANDOM_PATTERN_SEED                                                                 0x246d
++#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
++#define mmDIG4_DIG_FIFO_STATUS                                                                         0x246e
++#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX                                                                2
++#define mmDIG4_HDMI_METADATA_PACKET_CONTROL                                                            0x246f
++#define mmDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2470
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
++#define mmDIG4_HDMI_CONTROL                                                                            0x2471
++#define mmDIG4_HDMI_CONTROL_BASE_IDX                                                                   2
++#define mmDIG4_HDMI_STATUS                                                                             0x2472
++#define mmDIG4_HDMI_STATUS_BASE_IDX                                                                    2
++#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL                                                               0x2473
++#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
++#define mmDIG4_HDMI_ACR_PACKET_CONTROL                                                                 0x2474
++#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
++#define mmDIG4_HDMI_VBI_PACKET_CONTROL                                                                 0x2475
++#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
++#define mmDIG4_HDMI_INFOFRAME_CONTROL0                                                                 0x2476
++#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
++#define mmDIG4_HDMI_INFOFRAME_CONTROL1                                                                 0x2477
++#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2478
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
++#define mmDIG4_AFMT_INTERRUPT_STATUS                                                                   0x2479
++#define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
++#define mmDIG4_HDMI_GC                                                                                 0x247b
++#define mmDIG4_HDMI_GC_BASE_IDX                                                                        2
++#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2                                                              0x247c
++#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
++#define mmDIG4_AFMT_ISRC1_0                                                                            0x247d
++#define mmDIG4_AFMT_ISRC1_0_BASE_IDX                                                                   2
++#define mmDIG4_AFMT_ISRC1_1                                                                            0x247e
++#define mmDIG4_AFMT_ISRC1_1_BASE_IDX                                                                   2
++#define mmDIG4_AFMT_ISRC1_2                                                                            0x247f
++#define mmDIG4_AFMT_ISRC1_2_BASE_IDX                                                                   2
++#define mmDIG4_AFMT_ISRC1_3                                                                            0x2480
++#define mmDIG4_AFMT_ISRC1_3_BASE_IDX                                                                   2
++#define mmDIG4_AFMT_ISRC1_4                                                                            0x2481
++#define mmDIG4_AFMT_ISRC1_4_BASE_IDX                                                                   2
++#define mmDIG4_AFMT_ISRC2_0                                                                            0x2482
++#define mmDIG4_AFMT_ISRC2_0_BASE_IDX                                                                   2
++#define mmDIG4_AFMT_ISRC2_1                                                                            0x2483
++#define mmDIG4_AFMT_ISRC2_1_BASE_IDX                                                                   2
++#define mmDIG4_AFMT_ISRC2_2                                                                            0x2484
++#define mmDIG4_AFMT_ISRC2_2_BASE_IDX                                                                   2
++#define mmDIG4_AFMT_ISRC2_3                                                                            0x2485
++#define mmDIG4_AFMT_ISRC2_3_BASE_IDX                                                                   2
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2486
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2487
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
++#define mmDIG4_HDMI_DB_CONTROL                                                                         0x2488
++#define mmDIG4_HDMI_DB_CONTROL_BASE_IDX                                                                2
++#define mmDIG4_DME_CONTROL                                                                             0x2489
++#define mmDIG4_DME_CONTROL_BASE_IDX                                                                    2
++#define mmDIG4_AFMT_MPEG_INFO0                                                                         0x248a
++#define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX                                                                2
++#define mmDIG4_AFMT_MPEG_INFO1                                                                         0x248b
++#define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX                                                                2
++#define mmDIG4_AFMT_GENERIC_HDR                                                                        0x248c
++#define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX                                                               2
++#define mmDIG4_AFMT_GENERIC_0                                                                          0x248d
++#define mmDIG4_AFMT_GENERIC_0_BASE_IDX                                                                 2
++#define mmDIG4_AFMT_GENERIC_1                                                                          0x248e
++#define mmDIG4_AFMT_GENERIC_1_BASE_IDX                                                                 2
++#define mmDIG4_AFMT_GENERIC_2                                                                          0x248f
++#define mmDIG4_AFMT_GENERIC_2_BASE_IDX                                                                 2
++#define mmDIG4_AFMT_GENERIC_3                                                                          0x2490
++#define mmDIG4_AFMT_GENERIC_3_BASE_IDX                                                                 2
++#define mmDIG4_AFMT_GENERIC_4                                                                          0x2491
++#define mmDIG4_AFMT_GENERIC_4_BASE_IDX                                                                 2
++#define mmDIG4_AFMT_GENERIC_5                                                                          0x2492
++#define mmDIG4_AFMT_GENERIC_5_BASE_IDX                                                                 2
++#define mmDIG4_AFMT_GENERIC_6                                                                          0x2493
++#define mmDIG4_AFMT_GENERIC_6_BASE_IDX                                                                 2
++#define mmDIG4_AFMT_GENERIC_7                                                                          0x2494
++#define mmDIG4_AFMT_GENERIC_7_BASE_IDX                                                                 2
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2495
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
++#define mmDIG4_HDMI_ACR_32_0                                                                           0x2496
++#define mmDIG4_HDMI_ACR_32_0_BASE_IDX                                                                  2
++#define mmDIG4_HDMI_ACR_32_1                                                                           0x2497
++#define mmDIG4_HDMI_ACR_32_1_BASE_IDX                                                                  2
++#define mmDIG4_HDMI_ACR_44_0                                                                           0x2498
++#define mmDIG4_HDMI_ACR_44_0_BASE_IDX                                                                  2
++#define mmDIG4_HDMI_ACR_44_1                                                                           0x2499
++#define mmDIG4_HDMI_ACR_44_1_BASE_IDX                                                                  2
++#define mmDIG4_HDMI_ACR_48_0                                                                           0x249a
++#define mmDIG4_HDMI_ACR_48_0_BASE_IDX                                                                  2
++#define mmDIG4_HDMI_ACR_48_1                                                                           0x249b
++#define mmDIG4_HDMI_ACR_48_1_BASE_IDX                                                                  2
++#define mmDIG4_HDMI_ACR_STATUS_0                                                                       0x249c
++#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
++#define mmDIG4_HDMI_ACR_STATUS_1                                                                       0x249d
++#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
++#define mmDIG4_AFMT_AUDIO_INFO0                                                                        0x249e
++#define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
++#define mmDIG4_AFMT_AUDIO_INFO1                                                                        0x249f
++#define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
++#define mmDIG4_AFMT_60958_0                                                                            0x24a0
++#define mmDIG4_AFMT_60958_0_BASE_IDX                                                                   2
++#define mmDIG4_AFMT_60958_1                                                                            0x24a1
++#define mmDIG4_AFMT_60958_1_BASE_IDX                                                                   2
++#define mmDIG4_AFMT_AUDIO_CRC_CONTROL                                                                  0x24a2
++#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
++#define mmDIG4_AFMT_RAMP_CONTROL0                                                                      0x24a3
++#define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
++#define mmDIG4_AFMT_RAMP_CONTROL1                                                                      0x24a4
++#define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
++#define mmDIG4_AFMT_RAMP_CONTROL2                                                                      0x24a5
++#define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
++#define mmDIG4_AFMT_RAMP_CONTROL3                                                                      0x24a6
++#define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
++#define mmDIG4_AFMT_60958_2                                                                            0x24a7
++#define mmDIG4_AFMT_60958_2_BASE_IDX                                                                   2
++#define mmDIG4_AFMT_AUDIO_CRC_RESULT                                                                   0x24a8
++#define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
++#define mmDIG4_AFMT_STATUS                                                                             0x24a9
++#define mmDIG4_AFMT_STATUS_BASE_IDX                                                                    2
++#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL                                                               0x24aa
++#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
++#define mmDIG4_AFMT_VBI_PACKET_CONTROL                                                                 0x24ab
++#define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
++#define mmDIG4_AFMT_INFOFRAME_CONTROL0                                                                 0x24ac
++#define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
++#define mmDIG4_AFMT_AUDIO_SRC_CONTROL                                                                  0x24ad
++#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
++#define mmDIG4_DIG_BE_CNTL                                                                             0x24af
++#define mmDIG4_DIG_BE_CNTL_BASE_IDX                                                                    2
++#define mmDIG4_DIG_BE_EN_CNTL                                                                          0x24b0
++#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
++#define mmDIG4_TMDS_CNTL                                                                               0x24d3
++#define mmDIG4_TMDS_CNTL_BASE_IDX                                                                      2
++#define mmDIG4_TMDS_CONTROL_CHAR                                                                       0x24d4
++#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
++#define mmDIG4_TMDS_CONTROL0_FEEDBACK                                                                  0x24d5
++#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
++#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL                                                                 0x24d6
++#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
++#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x24d7
++#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
++#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x24d8
++#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
++#define mmDIG4_TMDS_CTL_BITS                                                                           0x24da
++#define mmDIG4_TMDS_CTL_BITS_BASE_IDX                                                                  2
++#define mmDIG4_TMDS_DCBALANCER_CONTROL                                                                 0x24db
++#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
++#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR                                                                0x24dc
++#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
++#define mmDIG4_TMDS_CTL0_1_GEN_CNTL                                                                    0x24dd
++#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
++#define mmDIG4_TMDS_CTL2_3_GEN_CNTL                                                                    0x24de
++#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
++#define mmDIG4_DIG_VERSION                                                                             0x24e0
++#define mmDIG4_DIG_VERSION_BASE_IDX                                                                    2
++#define mmDIG4_DIG_LANE_ENABLE                                                                         0x24e1
++#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX                                                                2
++#define mmDIG4_AFMT_CNTL                                                                               0x24e6
++#define mmDIG4_AFMT_CNTL_BASE_IDX                                                                      2
++#define mmDIG4_AFMT_VBI_PACKET_CONTROL1                                                                0x24e7
++#define mmDIG4_AFMT_VBI_PACKET_CONTROL1_BASE_IDX                                                       2
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5                                                            0x24f6
++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
++#define mmDIG4_FORCE_DIG_DISABLE                                                                       0x24f7
++#define mmDIG4_FORCE_DIG_DISABLE_BASE_IDX                                                              2
++
++
++// addressBlock: dce_dc_dio_dp4_dispdec
++// base address: 0x1000
++#define mmDP4_DP_LINK_CNTL                                                                             0x2508
++#define mmDP4_DP_LINK_CNTL_BASE_IDX                                                                    2
++#define mmDP4_DP_PIXEL_FORMAT                                                                          0x2509
++#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
++#define mmDP4_DP_MSA_COLORIMETRY                                                                       0x250a
++#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
++#define mmDP4_DP_CONFIG                                                                                0x250b
++#define mmDP4_DP_CONFIG_BASE_IDX                                                                       2
++#define mmDP4_DP_VID_STREAM_CNTL                                                                       0x250c
++#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
++#define mmDP4_DP_STEER_FIFO                                                                            0x250d
++#define mmDP4_DP_STEER_FIFO_BASE_IDX                                                                   2
++#define mmDP4_DP_MSA_MISC                                                                              0x250e
++#define mmDP4_DP_MSA_MISC_BASE_IDX                                                                     2
++#define mmDP4_DP_VID_TIMING                                                                            0x2510
++#define mmDP4_DP_VID_TIMING_BASE_IDX                                                                   2
++#define mmDP4_DP_VID_N                                                                                 0x2511
++#define mmDP4_DP_VID_N_BASE_IDX                                                                        2
++#define mmDP4_DP_VID_M                                                                                 0x2512
++#define mmDP4_DP_VID_M_BASE_IDX                                                                        2
++#define mmDP4_DP_LINK_FRAMING_CNTL                                                                     0x2513
++#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
++#define mmDP4_DP_HBR2_EYE_PATTERN                                                                      0x2514
++#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
++#define mmDP4_DP_VID_MSA_VBID                                                                          0x2515
++#define mmDP4_DP_VID_MSA_VBID_BASE_IDX                                                                 2
++#define mmDP4_DP_VID_INTERRUPT_CNTL                                                                    0x2516
++#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
++#define mmDP4_DP_DPHY_CNTL                                                                             0x2517
++#define mmDP4_DP_DPHY_CNTL_BASE_IDX                                                                    2
++#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2518
++#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
++#define mmDP4_DP_DPHY_SYM0                                                                             0x2519
++#define mmDP4_DP_DPHY_SYM0_BASE_IDX                                                                    2
++#define mmDP4_DP_DPHY_SYM1                                                                             0x251a
++#define mmDP4_DP_DPHY_SYM1_BASE_IDX                                                                    2
++#define mmDP4_DP_DPHY_SYM2                                                                             0x251b
++#define mmDP4_DP_DPHY_SYM2_BASE_IDX                                                                    2
++#define mmDP4_DP_DPHY_8B10B_CNTL                                                                       0x251c
++#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
++#define mmDP4_DP_DPHY_PRBS_CNTL                                                                        0x251d
++#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
++#define mmDP4_DP_DPHY_SCRAM_CNTL                                                                       0x251e
++#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
++#define mmDP4_DP_DPHY_CRC_EN                                                                           0x251f
++#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
++#define mmDP4_DP_DPHY_CRC_CNTL                                                                         0x2520
++#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
++#define mmDP4_DP_DPHY_CRC_RESULT                                                                       0x2521
++#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
++#define mmDP4_DP_DPHY_CRC_MST_CNTL                                                                     0x2522
++#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
++#define mmDP4_DP_DPHY_CRC_MST_STATUS                                                                   0x2523
++#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
++#define mmDP4_DP_DPHY_FAST_TRAINING                                                                    0x2524
++#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
++#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2525
++#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
++#define mmDP4_DP_SEC_CNTL                                                                              0x252b
++#define mmDP4_DP_SEC_CNTL_BASE_IDX                                                                     2
++#define mmDP4_DP_SEC_CNTL1                                                                             0x252c
++#define mmDP4_DP_SEC_CNTL1_BASE_IDX                                                                    2
++#define mmDP4_DP_SEC_FRAMING1                                                                          0x252d
++#define mmDP4_DP_SEC_FRAMING1_BASE_IDX                                                                 2
++#define mmDP4_DP_SEC_FRAMING2                                                                          0x252e
++#define mmDP4_DP_SEC_FRAMING2_BASE_IDX                                                                 2
++#define mmDP4_DP_SEC_FRAMING3                                                                          0x252f
++#define mmDP4_DP_SEC_FRAMING3_BASE_IDX                                                                 2
++#define mmDP4_DP_SEC_FRAMING4                                                                          0x2530
++#define mmDP4_DP_SEC_FRAMING4_BASE_IDX                                                                 2
++#define mmDP4_DP_SEC_AUD_N                                                                             0x2531
++#define mmDP4_DP_SEC_AUD_N_BASE_IDX                                                                    2
++#define mmDP4_DP_SEC_AUD_N_READBACK                                                                    0x2532
++#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
++#define mmDP4_DP_SEC_AUD_M                                                                             0x2533
++#define mmDP4_DP_SEC_AUD_M_BASE_IDX                                                                    2
++#define mmDP4_DP_SEC_AUD_M_READBACK                                                                    0x2534
++#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
++#define mmDP4_DP_SEC_TIMESTAMP                                                                         0x2535
++#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
++#define mmDP4_DP_SEC_PACKET_CNTL                                                                       0x2536
++#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
++#define mmDP4_DP_MSE_RATE_CNTL                                                                         0x2537
++#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
++#define mmDP4_DP_MSE_RATE_UPDATE                                                                       0x2539
++#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
++#define mmDP4_DP_MSE_SAT0                                                                              0x253a
++#define mmDP4_DP_MSE_SAT0_BASE_IDX                                                                     2
++#define mmDP4_DP_MSE_SAT1                                                                              0x253b
++#define mmDP4_DP_MSE_SAT1_BASE_IDX                                                                     2
++#define mmDP4_DP_MSE_SAT2                                                                              0x253c
++#define mmDP4_DP_MSE_SAT2_BASE_IDX                                                                     2
++#define mmDP4_DP_MSE_SAT_UPDATE                                                                        0x253d
++#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
++#define mmDP4_DP_MSE_LINK_TIMING                                                                       0x253e
++#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
++#define mmDP4_DP_MSE_MISC_CNTL                                                                         0x253f
++#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
++#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2544
++#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
++#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2545
++#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
++#define mmDP4_DP_MSE_SAT0_STATUS                                                                       0x2547
++#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
++#define mmDP4_DP_MSE_SAT1_STATUS                                                                       0x2548
++#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
++#define mmDP4_DP_MSE_SAT2_STATUS                                                                       0x2549
++#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
++#define mmDP4_DP_MSA_TIMING_PARAM1                                                                     0x254c
++#define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
++#define mmDP4_DP_MSA_TIMING_PARAM2                                                                     0x254d
++#define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
++#define mmDP4_DP_MSA_TIMING_PARAM3                                                                     0x254e
++#define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
++#define mmDP4_DP_MSA_TIMING_PARAM4                                                                     0x254f
++#define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
++#define mmDP4_DP_MSO_CNTL                                                                              0x2550
++#define mmDP4_DP_MSO_CNTL_BASE_IDX                                                                     2
++#define mmDP4_DP_MSO_CNTL1                                                                             0x2551
++#define mmDP4_DP_MSO_CNTL1_BASE_IDX                                                                    2
++#define mmDP4_DP_DSC_CNTL                                                                              0x2552
++#define mmDP4_DP_DSC_CNTL_BASE_IDX                                                                     2
++#define mmDP4_DP_SEC_CNTL2                                                                             0x2553
++#define mmDP4_DP_SEC_CNTL2_BASE_IDX                                                                    2
++#define mmDP4_DP_SEC_CNTL3                                                                             0x2554
++#define mmDP4_DP_SEC_CNTL3_BASE_IDX                                                                    2
++#define mmDP4_DP_SEC_CNTL4                                                                             0x2555
++#define mmDP4_DP_SEC_CNTL4_BASE_IDX                                                                    2
++#define mmDP4_DP_SEC_CNTL5                                                                             0x2556
++#define mmDP4_DP_SEC_CNTL5_BASE_IDX                                                                    2
++#define mmDP4_DP_SEC_CNTL6                                                                             0x2557
++#define mmDP4_DP_SEC_CNTL6_BASE_IDX                                                                    2
++#define mmDP4_DP_SEC_CNTL7                                                                             0x2558
++#define mmDP4_DP_SEC_CNTL7_BASE_IDX                                                                    2
++#define mmDP4_DP_DB_CNTL                                                                               0x2559
++#define mmDP4_DP_DB_CNTL_BASE_IDX                                                                      2
++#define mmDP4_DP_MSA_VBID_MISC                                                                         0x255a
++#define mmDP4_DP_MSA_VBID_MISC_BASE_IDX                                                                2
++#define mmDP4_DP_SEC_METADATA_TRANSMISSION                                                             0x255b
++#define mmDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
++#define mmDP4_DP_DSC_BYTES_PER_PIXEL                                                                   0x255c
++#define mmDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
++#define mmDP4_DP_ALPM_CNTL                                                                             0x255d
++#define mmDP4_DP_ALPM_CNTL_BASE_IDX                                                                    2
++
++
++// addressBlock: dce_dc_dcio_dcio_dispdec
++// base address: 0x0
++#define mmDC_GENERICA                                                                                  0x2868
++#define mmDC_GENERICA_BASE_IDX                                                                         2
++#define mmDC_GENERICB                                                                                  0x2869
++#define mmDC_GENERICB_BASE_IDX                                                                         2
++#define mmDC_REF_CLK_CNTL                                                                              0x286b
++#define mmDC_REF_CLK_CNTL_BASE_IDX                                                                     2
++#define mmUNIPHYA_LINK_CNTL                                                                            0x286d
++#define mmUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2
++#define mmUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e
++#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
++#define mmUNIPHYB_LINK_CNTL                                                                            0x286f
++#define mmUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2
++#define mmUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870
++#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
++#define mmUNIPHYC_LINK_CNTL                                                                            0x2871
++#define mmUNIPHYC_LINK_CNTL_BASE_IDX                                                                   2
++#define mmUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872
++#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
++#define mmUNIPHYD_LINK_CNTL                                                                            0x2873
++#define mmUNIPHYD_LINK_CNTL_BASE_IDX                                                                   2
++#define mmUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874
++#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
++#define mmUNIPHYE_LINK_CNTL                                                                            0x2875
++#define mmUNIPHYE_LINK_CNTL_BASE_IDX                                                                   2
++#define mmUNIPHYE_CHANNEL_XBAR_CNTL                                                                    0x2876
++#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
++#define mmDCIO_WRCMD_DELAY                                                                             0x287e
++#define mmDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
++#define mmDC_PINSTRAPS                                                                                 0x2880
++#define mmDC_PINSTRAPS_BASE_IDX                                                                        2
++#define mmLVTMA_PWRSEQ_CNTL                                                                            0x2883
++#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX                                                                   2
++#define mmLVTMA_PWRSEQ_STATE                                                                           0x2884
++#define mmLVTMA_PWRSEQ_STATE_BASE_IDX                                                                  2
++#define mmLVTMA_PWRSEQ_REF_DIV                                                                         0x2885
++#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX                                                                2
++#define mmLVTMA_PWRSEQ_DELAY1                                                                          0x2886
++#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX                                                                 2
++#define mmLVTMA_PWRSEQ_DELAY2                                                                          0x2887
++#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX                                                                 2
++#define mmBL_PWM_CNTL                                                                                  0x2888
++#define mmBL_PWM_CNTL_BASE_IDX                                                                         2
++#define mmBL_PWM_CNTL2                                                                                 0x2889
++#define mmBL_PWM_CNTL2_BASE_IDX                                                                        2
++#define mmBL_PWM_PERIOD_CNTL                                                                           0x288a
++#define mmBL_PWM_PERIOD_CNTL_BASE_IDX                                                                  2
++#define mmBL_PWM_GRP1_REG_LOCK                                                                         0x288b
++#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX                                                                2
++#define mmDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
++#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
++#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d
++#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2
++#define mmDCIO_CLOCK_CNTL                                                                              0x2895
++#define mmDCIO_CLOCK_CNTL_BASE_IDX                                                                     2
++#define mmDCIO_SOFT_RESET                                                                              0x289e
++#define mmDCIO_SOFT_RESET_BASE_IDX                                                                     2
++
++
++// addressBlock: dce_dc_dcio_dcio_chip_dispdec
++// base address: 0x0
++#define mmDC_GPIO_GENERIC_MASK                                                                         0x28c8
++#define mmDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2
++#define mmDC_GPIO_GENERIC_A                                                                            0x28c9
++#define mmDC_GPIO_GENERIC_A_BASE_IDX                                                                   2
++#define mmDC_GPIO_GENERIC_EN                                                                           0x28ca
++#define mmDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2
++#define mmDC_GPIO_GENERIC_Y                                                                            0x28cb
++#define mmDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2
++#define mmDC_GPIO_DDC1_MASK                                                                            0x28d0
++#define mmDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2
++#define mmDC_GPIO_DDC1_A                                                                               0x28d1
++#define mmDC_GPIO_DDC1_A_BASE_IDX                                                                      2
++#define mmDC_GPIO_DDC1_EN                                                                              0x28d2
++#define mmDC_GPIO_DDC1_EN_BASE_IDX                                                                     2
++#define mmDC_GPIO_DDC1_Y                                                                               0x28d3
++#define mmDC_GPIO_DDC1_Y_BASE_IDX                                                                      2
++#define mmDC_GPIO_DDC2_MASK                                                                            0x28d4
++#define mmDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2
++#define mmDC_GPIO_DDC2_A                                                                               0x28d5
++#define mmDC_GPIO_DDC2_A_BASE_IDX                                                                      2
++#define mmDC_GPIO_DDC2_EN                                                                              0x28d6
++#define mmDC_GPIO_DDC2_EN_BASE_IDX                                                                     2
++#define mmDC_GPIO_DDC2_Y                                                                               0x28d7
++#define mmDC_GPIO_DDC2_Y_BASE_IDX                                                                      2
++#define mmDC_GPIO_DDC3_MASK                                                                            0x28d8
++#define mmDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2
++#define mmDC_GPIO_DDC3_A                                                                               0x28d9
++#define mmDC_GPIO_DDC3_A_BASE_IDX                                                                      2
++#define mmDC_GPIO_DDC3_EN                                                                              0x28da
++#define mmDC_GPIO_DDC3_EN_BASE_IDX                                                                     2
++#define mmDC_GPIO_DDC3_Y                                                                               0x28db
++#define mmDC_GPIO_DDC3_Y_BASE_IDX                                                                      2
++#define mmDC_GPIO_DDC4_MASK                                                                            0x28dc
++#define mmDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2
++#define mmDC_GPIO_DDC4_A                                                                               0x28dd
++#define mmDC_GPIO_DDC4_A_BASE_IDX                                                                      2
++#define mmDC_GPIO_DDC4_EN                                                                              0x28de
++#define mmDC_GPIO_DDC4_EN_BASE_IDX                                                                     2
++#define mmDC_GPIO_DDC4_Y                                                                               0x28df
++#define mmDC_GPIO_DDC4_Y_BASE_IDX                                                                      2
++#define mmDC_GPIO_DDC5_MASK                                                                            0x28e0
++#define mmDC_GPIO_DDC5_MASK_BASE_IDX                                                                   2
++#define mmDC_GPIO_DDC5_A                                                                               0x28e1
++#define mmDC_GPIO_DDC5_A_BASE_IDX                                                                      2
++#define mmDC_GPIO_DDC5_EN                                                                              0x28e2
++#define mmDC_GPIO_DDC5_EN_BASE_IDX                                                                     2
++#define mmDC_GPIO_DDC5_Y                                                                               0x28e3
++#define mmDC_GPIO_DDC5_Y_BASE_IDX                                                                      2
++#define mmDC_GPIO_DDCVGA_MASK                                                                          0x28e8
++#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2
++#define mmDC_GPIO_DDCVGA_A                                                                             0x28e9
++#define mmDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2
++#define mmDC_GPIO_DDCVGA_EN                                                                            0x28ea
++#define mmDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2
++#define mmDC_GPIO_DDCVGA_Y                                                                             0x28eb
++#define mmDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2
++#define mmDC_GPIO_GENLK_MASK                                                                           0x28f0
++#define mmDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2
++#define mmDC_GPIO_GENLK_A                                                                              0x28f1
++#define mmDC_GPIO_GENLK_A_BASE_IDX                                                                     2
++#define mmDC_GPIO_GENLK_EN                                                                             0x28f2
++#define mmDC_GPIO_GENLK_EN_BASE_IDX                                                                    2
++#define mmDC_GPIO_GENLK_Y                                                                              0x28f3
++#define mmDC_GPIO_GENLK_Y_BASE_IDX                                                                     2
++#define mmDC_GPIO_HPD_MASK                                                                             0x28f4
++#define mmDC_GPIO_HPD_MASK_BASE_IDX                                                                    2
++#define mmDC_GPIO_HPD_A                                                                                0x28f5
++#define mmDC_GPIO_HPD_A_BASE_IDX                                                                       2
++#define mmDC_GPIO_HPD_EN                                                                               0x28f6
++#define mmDC_GPIO_HPD_EN_BASE_IDX                                                                      2
++#define mmDC_GPIO_HPD_Y                                                                                0x28f7
++#define mmDC_GPIO_HPD_Y_BASE_IDX                                                                       2
++#define mmDC_GPIO_PWRSEQ_MASK                                                                          0x28f8
++#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX                                                                 2
++#define mmDC_GPIO_PWRSEQ_A                                                                             0x28f9
++#define mmDC_GPIO_PWRSEQ_A_BASE_IDX                                                                    2
++#define mmDC_GPIO_PWRSEQ_EN                                                                            0x28fa
++#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX                                                                   2
++#define mmDC_GPIO_PWRSEQ_Y                                                                             0x28fb
++#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX                                                                    2
++#define mmDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc
++#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2
++#define mmDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd
++#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2
++#define mmPHY_AUX_CNTL                                                                                 0x28ff
++#define mmPHY_AUX_CNTL_BASE_IDX                                                                        2
++#define mmDC_GPIO_TX12_EN                                                                              0x2915
++#define mmDC_GPIO_TX12_EN_BASE_IDX                                                                     2
++#define mmDC_GPIO_AUX_CTRL_0                                                                           0x2916
++#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2
++#define mmDC_GPIO_AUX_CTRL_1                                                                           0x2917
++#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2
++#define mmDC_GPIO_AUX_CTRL_2                                                                           0x2918
++#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
++#define mmDC_GPIO_RXEN                                                                                 0x2919
++#define mmDC_GPIO_RXEN_BASE_IDX                                                                        2
++#define mmDC_GPIO_PULLUPEN                                                                             0x291a
++#define mmDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
++#define mmDC_GPIO_AUX_CTRL_3                                                                           0x291b
++#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
++#define mmDC_GPIO_AUX_CTRL_4                                                                           0x291c
++#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
++#define mmDC_GPIO_AUX_CTRL_5                                                                           0x291d
++#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
++#define mmAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e
++#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2
++
++// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
++// base address: 0x0
++#define mmDSC_TOP0_DSC_TOP_CONTROL                                                                     0x3000
++#define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX                                                            2
++#define mmDSC_TOP0_DSC_DEBUG_CONTROL                                                                   0x3001
++#define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
++// base address: 0x0
++#define mmDSCCIF0_DSCCIF_CONFIG0                                                                       0x3005
++#define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX                                                              2
++#define mmDSCCIF0_DSCCIF_CONFIG1                                                                       0x3006
++#define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX                                                              2
++
++
++// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
++// base address: 0x0
++#define mmDSCC0_DSCC_CONFIG0                                                                           0x300a
++#define mmDSCC0_DSCC_CONFIG0_BASE_IDX                                                                  2
++#define mmDSCC0_DSCC_CONFIG1                                                                           0x300b
++#define mmDSCC0_DSCC_CONFIG1_BASE_IDX                                                                  2
++#define mmDSCC0_DSCC_STATUS                                                                            0x300c
++#define mmDSCC0_DSCC_STATUS_BASE_IDX                                                                   2
++#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x300d
++#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
++#define mmDSCC0_DSCC_PPS_CONFIG0                                                                       0x300e
++#define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
++#define mmDSCC0_DSCC_PPS_CONFIG1                                                                       0x300f
++#define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
++#define mmDSCC0_DSCC_PPS_CONFIG2                                                                       0x3010
++#define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
++#define mmDSCC0_DSCC_PPS_CONFIG3                                                                       0x3011
++#define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
++#define mmDSCC0_DSCC_PPS_CONFIG4                                                                       0x3012
++#define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
++#define mmDSCC0_DSCC_PPS_CONFIG5                                                                       0x3013
++#define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
++#define mmDSCC0_DSCC_PPS_CONFIG6                                                                       0x3014
++#define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
++#define mmDSCC0_DSCC_PPS_CONFIG7                                                                       0x3015
++#define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
++#define mmDSCC0_DSCC_PPS_CONFIG8                                                                       0x3016
++#define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
++#define mmDSCC0_DSCC_PPS_CONFIG9                                                                       0x3017
++#define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
++#define mmDSCC0_DSCC_PPS_CONFIG10                                                                      0x3018
++#define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
++#define mmDSCC0_DSCC_PPS_CONFIG11                                                                      0x3019
++#define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
++#define mmDSCC0_DSCC_PPS_CONFIG12                                                                      0x301a
++#define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
++#define mmDSCC0_DSCC_PPS_CONFIG13                                                                      0x301b
++#define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
++#define mmDSCC0_DSCC_PPS_CONFIG14                                                                      0x301c
++#define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
++#define mmDSCC0_DSCC_PPS_CONFIG15                                                                      0x301d
++#define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
++#define mmDSCC0_DSCC_PPS_CONFIG16                                                                      0x301e
++#define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
++#define mmDSCC0_DSCC_PPS_CONFIG17                                                                      0x301f
++#define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
++#define mmDSCC0_DSCC_PPS_CONFIG18                                                                      0x3020
++#define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
++#define mmDSCC0_DSCC_PPS_CONFIG19                                                                      0x3021
++#define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
++#define mmDSCC0_DSCC_PPS_CONFIG20                                                                      0x3022
++#define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
++#define mmDSCC0_DSCC_PPS_CONFIG21                                                                      0x3023
++#define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
++#define mmDSCC0_DSCC_PPS_CONFIG22                                                                      0x3024
++#define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
++#define mmDSCC0_DSCC_MEM_POWER_CONTROL                                                                 0x3025
++#define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
++#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3026
++#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
++#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3027
++#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
++#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3028
++#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
++#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3029
++#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
++#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x302a
++#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
++#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x302b
++#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
++#define mmDSCC0_DSCC_MAX_ABS_ERROR0                                                                    0x302c
++#define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
++#define mmDSCC0_DSCC_MAX_ABS_ERROR1                                                                    0x302d
++#define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
++#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x302e
++#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x302f
++#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3030
++#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3031
++#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3032
++#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3033
++#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3034
++#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035
++#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x303a
++#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
++
++
++// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
++// base address: 0xc140
++#define mmDC_PERFMON19_PERFCOUNTER_CNTL                                                                0x3050
++#define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX                                                       2
++#define mmDC_PERFMON19_PERFCOUNTER_CNTL2                                                               0x3051
++#define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
++#define mmDC_PERFMON19_PERFCOUNTER_STATE                                                               0x3052
++#define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX                                                      2
++#define mmDC_PERFMON19_PERFMON_CNTL                                                                    0x3053
++#define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX                                                           2
++#define mmDC_PERFMON19_PERFMON_CNTL2                                                                   0x3054
++#define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX                                                          2
++#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC                                                         0x3055
++#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
++#define mmDC_PERFMON19_PERFMON_CVALUE_LOW                                                              0x3056
++#define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
++#define mmDC_PERFMON19_PERFMON_HI                                                                      0x3057
++#define mmDC_PERFMON19_PERFMON_HI_BASE_IDX                                                             2
++#define mmDC_PERFMON19_PERFMON_LOW                                                                     0x3058
++#define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
++// base address: 0x170
++#define mmDSC_TOP1_DSC_TOP_CONTROL                                                                     0x305c
++#define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX                                                            2
++#define mmDSC_TOP1_DSC_DEBUG_CONTROL                                                                   0x305d
++#define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
++// base address: 0x170
++#define mmDSCCIF1_DSCCIF_CONFIG0                                                                       0x3061
++#define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX                                                              2
++#define mmDSCCIF1_DSCCIF_CONFIG1                                                                       0x3062
++#define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX                                                              2
++
++
++// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
++// base address: 0x170
++#define mmDSCC1_DSCC_CONFIG0                                                                           0x3066
++#define mmDSCC1_DSCC_CONFIG0_BASE_IDX                                                                  2
++#define mmDSCC1_DSCC_CONFIG1                                                                           0x3067
++#define mmDSCC1_DSCC_CONFIG1_BASE_IDX                                                                  2
++#define mmDSCC1_DSCC_STATUS                                                                            0x3068
++#define mmDSCC1_DSCC_STATUS_BASE_IDX                                                                   2
++#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3069
++#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
++#define mmDSCC1_DSCC_PPS_CONFIG0                                                                       0x306a
++#define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
++#define mmDSCC1_DSCC_PPS_CONFIG1                                                                       0x306b
++#define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
++#define mmDSCC1_DSCC_PPS_CONFIG2                                                                       0x306c
++#define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
++#define mmDSCC1_DSCC_PPS_CONFIG3                                                                       0x306d
++#define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
++#define mmDSCC1_DSCC_PPS_CONFIG4                                                                       0x306e
++#define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
++#define mmDSCC1_DSCC_PPS_CONFIG5                                                                       0x306f
++#define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
++#define mmDSCC1_DSCC_PPS_CONFIG6                                                                       0x3070
++#define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
++#define mmDSCC1_DSCC_PPS_CONFIG7                                                                       0x3071
++#define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
++#define mmDSCC1_DSCC_PPS_CONFIG8                                                                       0x3072
++#define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
++#define mmDSCC1_DSCC_PPS_CONFIG9                                                                       0x3073
++#define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
++#define mmDSCC1_DSCC_PPS_CONFIG10                                                                      0x3074
++#define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
++#define mmDSCC1_DSCC_PPS_CONFIG11                                                                      0x3075
++#define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
++#define mmDSCC1_DSCC_PPS_CONFIG12                                                                      0x3076
++#define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
++#define mmDSCC1_DSCC_PPS_CONFIG13                                                                      0x3077
++#define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
++#define mmDSCC1_DSCC_PPS_CONFIG14                                                                      0x3078
++#define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
++#define mmDSCC1_DSCC_PPS_CONFIG15                                                                      0x3079
++#define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
++#define mmDSCC1_DSCC_PPS_CONFIG16                                                                      0x307a
++#define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
++#define mmDSCC1_DSCC_PPS_CONFIG17                                                                      0x307b
++#define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
++#define mmDSCC1_DSCC_PPS_CONFIG18                                                                      0x307c
++#define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
++#define mmDSCC1_DSCC_PPS_CONFIG19                                                                      0x307d
++#define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
++#define mmDSCC1_DSCC_PPS_CONFIG20                                                                      0x307e
++#define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
++#define mmDSCC1_DSCC_PPS_CONFIG21                                                                      0x307f
++#define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
++#define mmDSCC1_DSCC_PPS_CONFIG22                                                                      0x3080
++#define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
++#define mmDSCC1_DSCC_MEM_POWER_CONTROL                                                                 0x3081
++#define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
++#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3082
++#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
++#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3083
++#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
++#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3084
++#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
++#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3085
++#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
++#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x3086
++#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
++#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x3087
++#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
++#define mmDSCC1_DSCC_MAX_ABS_ERROR0                                                                    0x3088
++#define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
++#define mmDSCC1_DSCC_MAX_ABS_ERROR1                                                                    0x3089
++#define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
++#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x308a
++#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x308b
++#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x308c
++#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x308d
++#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x308e
++#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x308f
++#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3090
++#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091
++#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3096
++#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
++
++
++// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
++// base address: 0xc2b0
++#define mmDC_PERFMON20_PERFCOUNTER_CNTL                                                                0x30ac
++#define mmDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX                                                       2
++#define mmDC_PERFMON20_PERFCOUNTER_CNTL2                                                               0x30ad
++#define mmDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
++#define mmDC_PERFMON20_PERFCOUNTER_STATE                                                               0x30ae
++#define mmDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX                                                      2
++#define mmDC_PERFMON20_PERFMON_CNTL                                                                    0x30af
++#define mmDC_PERFMON20_PERFMON_CNTL_BASE_IDX                                                           2
++#define mmDC_PERFMON20_PERFMON_CNTL2                                                                   0x30b0
++#define mmDC_PERFMON20_PERFMON_CNTL2_BASE_IDX                                                          2
++#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC                                                         0x30b1
++#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
++#define mmDC_PERFMON20_PERFMON_CVALUE_LOW                                                              0x30b2
++#define mmDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
++#define mmDC_PERFMON20_PERFMON_HI                                                                      0x30b3
++#define mmDC_PERFMON20_PERFMON_HI_BASE_IDX                                                             2
++#define mmDC_PERFMON20_PERFMON_LOW                                                                     0x30b4
++#define mmDC_PERFMON20_PERFMON_LOW_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
++// base address: 0x2e0
++#define mmDSC_TOP2_DSC_TOP_CONTROL                                                                     0x30b8
++#define mmDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX                                                            2
++#define mmDSC_TOP2_DSC_DEBUG_CONTROL                                                                   0x30b9
++#define mmDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
++// base address: 0x2e0
++#define mmDSCCIF2_DSCCIF_CONFIG0                                                                       0x30bd
++#define mmDSCCIF2_DSCCIF_CONFIG0_BASE_IDX                                                              2
++#define mmDSCCIF2_DSCCIF_CONFIG1                                                                       0x30be
++#define mmDSCCIF2_DSCCIF_CONFIG1_BASE_IDX                                                              2
++
++
++// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
++// base address: 0x2e0
++#define mmDSCC2_DSCC_CONFIG0                                                                           0x30c2
++#define mmDSCC2_DSCC_CONFIG0_BASE_IDX                                                                  2
++#define mmDSCC2_DSCC_CONFIG1                                                                           0x30c3
++#define mmDSCC2_DSCC_CONFIG1_BASE_IDX                                                                  2
++#define mmDSCC2_DSCC_STATUS                                                                            0x30c4
++#define mmDSCC2_DSCC_STATUS_BASE_IDX                                                                   2
++#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x30c5
++#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
++#define mmDSCC2_DSCC_PPS_CONFIG0                                                                       0x30c6
++#define mmDSCC2_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
++#define mmDSCC2_DSCC_PPS_CONFIG1                                                                       0x30c7
++#define mmDSCC2_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
++#define mmDSCC2_DSCC_PPS_CONFIG2                                                                       0x30c8
++#define mmDSCC2_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
++#define mmDSCC2_DSCC_PPS_CONFIG3                                                                       0x30c9
++#define mmDSCC2_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
++#define mmDSCC2_DSCC_PPS_CONFIG4                                                                       0x30ca
++#define mmDSCC2_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
++#define mmDSCC2_DSCC_PPS_CONFIG5                                                                       0x30cb
++#define mmDSCC2_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
++#define mmDSCC2_DSCC_PPS_CONFIG6                                                                       0x30cc
++#define mmDSCC2_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
++#define mmDSCC2_DSCC_PPS_CONFIG7                                                                       0x30cd
++#define mmDSCC2_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
++#define mmDSCC2_DSCC_PPS_CONFIG8                                                                       0x30ce
++#define mmDSCC2_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
++#define mmDSCC2_DSCC_PPS_CONFIG9                                                                       0x30cf
++#define mmDSCC2_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
++#define mmDSCC2_DSCC_PPS_CONFIG10                                                                      0x30d0
++#define mmDSCC2_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
++#define mmDSCC2_DSCC_PPS_CONFIG11                                                                      0x30d1
++#define mmDSCC2_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
++#define mmDSCC2_DSCC_PPS_CONFIG12                                                                      0x30d2
++#define mmDSCC2_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
++#define mmDSCC2_DSCC_PPS_CONFIG13                                                                      0x30d3
++#define mmDSCC2_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
++#define mmDSCC2_DSCC_PPS_CONFIG14                                                                      0x30d4
++#define mmDSCC2_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
++#define mmDSCC2_DSCC_PPS_CONFIG15                                                                      0x30d5
++#define mmDSCC2_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
++#define mmDSCC2_DSCC_PPS_CONFIG16                                                                      0x30d6
++#define mmDSCC2_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
++#define mmDSCC2_DSCC_PPS_CONFIG17                                                                      0x30d7
++#define mmDSCC2_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
++#define mmDSCC2_DSCC_PPS_CONFIG18                                                                      0x30d8
++#define mmDSCC2_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
++#define mmDSCC2_DSCC_PPS_CONFIG19                                                                      0x30d9
++#define mmDSCC2_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
++#define mmDSCC2_DSCC_PPS_CONFIG20                                                                      0x30da
++#define mmDSCC2_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
++#define mmDSCC2_DSCC_PPS_CONFIG21                                                                      0x30db
++#define mmDSCC2_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
++#define mmDSCC2_DSCC_PPS_CONFIG22                                                                      0x30dc
++#define mmDSCC2_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
++#define mmDSCC2_DSCC_MEM_POWER_CONTROL                                                                 0x30dd
++#define mmDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
++#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x30de
++#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
++#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x30df
++#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
++#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x30e0
++#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
++#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x30e1
++#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
++#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x30e2
++#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
++#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x30e3
++#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
++#define mmDSCC2_DSCC_MAX_ABS_ERROR0                                                                    0x30e4
++#define mmDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
++#define mmDSCC2_DSCC_MAX_ABS_ERROR1                                                                    0x30e5
++#define mmDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
++#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x30e6
++#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x30e7
++#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x30e8
++#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x30e9
++#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x30ea
++#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x30eb
++#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x30ec
++#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed
++#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x30f2
++#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
++
++
++// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
++// base address: 0xc420
++#define mmDC_PERFMON21_PERFCOUNTER_CNTL                                                                0x3108
++#define mmDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX                                                       2
++#define mmDC_PERFMON21_PERFCOUNTER_CNTL2                                                               0x3109
++#define mmDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
++#define mmDC_PERFMON21_PERFCOUNTER_STATE                                                               0x310a
++#define mmDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX                                                      2
++#define mmDC_PERFMON21_PERFMON_CNTL                                                                    0x310b
++#define mmDC_PERFMON21_PERFMON_CNTL_BASE_IDX                                                           2
++#define mmDC_PERFMON21_PERFMON_CNTL2                                                                   0x310c
++#define mmDC_PERFMON21_PERFMON_CNTL2_BASE_IDX                                                          2
++#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC                                                         0x310d
++#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
++#define mmDC_PERFMON21_PERFMON_CVALUE_LOW                                                              0x310e
++#define mmDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
++#define mmDC_PERFMON21_PERFMON_HI                                                                      0x310f
++#define mmDC_PERFMON21_PERFMON_HI_BASE_IDX                                                             2
++#define mmDC_PERFMON21_PERFMON_LOW                                                                     0x3110
++#define mmDC_PERFMON21_PERFMON_LOW_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec
++// base address: 0x450
++#define mmDSC_TOP3_DSC_TOP_CONTROL                                                                     0x3114
++#define mmDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX                                                            2
++#define mmDSC_TOP3_DSC_DEBUG_CONTROL                                                                   0x3115
++#define mmDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec
++// base address: 0x450
++#define mmDSCCIF3_DSCCIF_CONFIG0                                                                       0x3119
++#define mmDSCCIF3_DSCCIF_CONFIG0_BASE_IDX                                                              2
++#define mmDSCCIF3_DSCCIF_CONFIG1                                                                       0x311a
++#define mmDSCCIF3_DSCCIF_CONFIG1_BASE_IDX                                                              2
++
++
++// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec
++// base address: 0x450
++#define mmDSCC3_DSCC_CONFIG0                                                                           0x311e
++#define mmDSCC3_DSCC_CONFIG0_BASE_IDX                                                                  2
++#define mmDSCC3_DSCC_CONFIG1                                                                           0x311f
++#define mmDSCC3_DSCC_CONFIG1_BASE_IDX                                                                  2
++#define mmDSCC3_DSCC_STATUS                                                                            0x3120
++#define mmDSCC3_DSCC_STATUS_BASE_IDX                                                                   2
++#define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3121
++#define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
++#define mmDSCC3_DSCC_PPS_CONFIG0                                                                       0x3122
++#define mmDSCC3_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
++#define mmDSCC3_DSCC_PPS_CONFIG1                                                                       0x3123
++#define mmDSCC3_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
++#define mmDSCC3_DSCC_PPS_CONFIG2                                                                       0x3124
++#define mmDSCC3_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
++#define mmDSCC3_DSCC_PPS_CONFIG3                                                                       0x3125
++#define mmDSCC3_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
++#define mmDSCC3_DSCC_PPS_CONFIG4                                                                       0x3126
++#define mmDSCC3_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
++#define mmDSCC3_DSCC_PPS_CONFIG5                                                                       0x3127
++#define mmDSCC3_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
++#define mmDSCC3_DSCC_PPS_CONFIG6                                                                       0x3128
++#define mmDSCC3_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
++#define mmDSCC3_DSCC_PPS_CONFIG7                                                                       0x3129
++#define mmDSCC3_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
++#define mmDSCC3_DSCC_PPS_CONFIG8                                                                       0x312a
++#define mmDSCC3_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
++#define mmDSCC3_DSCC_PPS_CONFIG9                                                                       0x312b
++#define mmDSCC3_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
++#define mmDSCC3_DSCC_PPS_CONFIG10                                                                      0x312c
++#define mmDSCC3_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
++#define mmDSCC3_DSCC_PPS_CONFIG11                                                                      0x312d
++#define mmDSCC3_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
++#define mmDSCC3_DSCC_PPS_CONFIG12                                                                      0x312e
++#define mmDSCC3_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
++#define mmDSCC3_DSCC_PPS_CONFIG13                                                                      0x312f
++#define mmDSCC3_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
++#define mmDSCC3_DSCC_PPS_CONFIG14                                                                      0x3130
++#define mmDSCC3_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
++#define mmDSCC3_DSCC_PPS_CONFIG15                                                                      0x3131
++#define mmDSCC3_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
++#define mmDSCC3_DSCC_PPS_CONFIG16                                                                      0x3132
++#define mmDSCC3_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
++#define mmDSCC3_DSCC_PPS_CONFIG17                                                                      0x3133
++#define mmDSCC3_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
++#define mmDSCC3_DSCC_PPS_CONFIG18                                                                      0x3134
++#define mmDSCC3_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
++#define mmDSCC3_DSCC_PPS_CONFIG19                                                                      0x3135
++#define mmDSCC3_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
++#define mmDSCC3_DSCC_PPS_CONFIG20                                                                      0x3136
++#define mmDSCC3_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
++#define mmDSCC3_DSCC_PPS_CONFIG21                                                                      0x3137
++#define mmDSCC3_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
++#define mmDSCC3_DSCC_PPS_CONFIG22                                                                      0x3138
++#define mmDSCC3_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
++#define mmDSCC3_DSCC_MEM_POWER_CONTROL                                                                 0x3139
++#define mmDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
++#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x313a
++#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
++#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x313b
++#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
++#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x313c
++#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
++#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x313d
++#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
++#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x313e
++#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
++#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x313f
++#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
++#define mmDSCC3_DSCC_MAX_ABS_ERROR0                                                                    0x3140
++#define mmDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
++#define mmDSCC3_DSCC_MAX_ABS_ERROR1                                                                    0x3141
++#define mmDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
++#define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x3142
++#define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x3143
++#define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3144
++#define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3145
++#define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3146
++#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3147
++#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3148
++#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3149
++#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x314e
++#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
++
++// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
++// base address: 0xc590
++#define mmDC_PERFMON22_PERFCOUNTER_CNTL                                                                0x3164
++#define mmDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX                                                       2
++#define mmDC_PERFMON22_PERFCOUNTER_CNTL2                                                               0x3165
++#define mmDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
++#define mmDC_PERFMON22_PERFCOUNTER_STATE                                                               0x3166
++#define mmDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX                                                      2
++#define mmDC_PERFMON22_PERFMON_CNTL                                                                    0x3167
++#define mmDC_PERFMON22_PERFMON_CNTL_BASE_IDX                                                           2
++#define mmDC_PERFMON22_PERFMON_CNTL2                                                                   0x3168
++#define mmDC_PERFMON22_PERFMON_CNTL2_BASE_IDX                                                          2
++#define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC                                                         0x3169
++#define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
++#define mmDC_PERFMON22_PERFMON_CVALUE_LOW                                                              0x316a
++#define mmDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
++#define mmDC_PERFMON22_PERFMON_HI                                                                      0x316b
++#define mmDC_PERFMON22_PERFMON_HI_BASE_IDX                                                             2
++#define mmDC_PERFMON22_PERFMON_LOW                                                                     0x316c
++#define mmDC_PERFMON22_PERFMON_LOW_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dsc4_dispdec_dsc_top_dispdec
++// base address: 0x5c0
++#define mmDSC_TOP4_DSC_TOP_CONTROL                                                                     0x3170
++#define mmDSC_TOP4_DSC_TOP_CONTROL_BASE_IDX                                                            2
++#define mmDSC_TOP4_DSC_DEBUG_CONTROL                                                                   0x3171
++#define mmDSC_TOP4_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_dsc4_dispdec_dsccif_dispdec
++// base address: 0x5c0
++#define mmDSCCIF4_DSCCIF_CONFIG0                                                                       0x3175
++#define mmDSCCIF4_DSCCIF_CONFIG0_BASE_IDX                                                              2
++#define mmDSCCIF4_DSCCIF_CONFIG1                                                                       0x3176
++#define mmDSCCIF4_DSCCIF_CONFIG1_BASE_IDX                                                              2
++
++
++// addressBlock: dce_dc_dsc4_dispdec_dscc_dispdec
++// base address: 0x5c0
++#define mmDSCC4_DSCC_CONFIG0                                                                           0x317a
++#define mmDSCC4_DSCC_CONFIG0_BASE_IDX                                                                  2
++#define mmDSCC4_DSCC_CONFIG1                                                                           0x317b
++#define mmDSCC4_DSCC_CONFIG1_BASE_IDX                                                                  2
++#define mmDSCC4_DSCC_STATUS                                                                            0x317c
++#define mmDSCC4_DSCC_STATUS_BASE_IDX                                                                   2
++#define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x317d
++#define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
++#define mmDSCC4_DSCC_PPS_CONFIG0                                                                       0x317e
++#define mmDSCC4_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
++#define mmDSCC4_DSCC_PPS_CONFIG1                                                                       0x317f
++#define mmDSCC4_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
++#define mmDSCC4_DSCC_PPS_CONFIG2                                                                       0x3180
++#define mmDSCC4_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
++#define mmDSCC4_DSCC_PPS_CONFIG3                                                                       0x3181
++#define mmDSCC4_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
++#define mmDSCC4_DSCC_PPS_CONFIG4                                                                       0x3182
++#define mmDSCC4_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
++#define mmDSCC4_DSCC_PPS_CONFIG5                                                                       0x3183
++#define mmDSCC4_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
++#define mmDSCC4_DSCC_PPS_CONFIG6                                                                       0x3184
++#define mmDSCC4_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
++#define mmDSCC4_DSCC_PPS_CONFIG7                                                                       0x3185
++#define mmDSCC4_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
++#define mmDSCC4_DSCC_PPS_CONFIG8                                                                       0x3186
++#define mmDSCC4_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
++#define mmDSCC4_DSCC_PPS_CONFIG9                                                                       0x3187
++#define mmDSCC4_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
++#define mmDSCC4_DSCC_PPS_CONFIG10                                                                      0x3188
++#define mmDSCC4_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
++#define mmDSCC4_DSCC_PPS_CONFIG11                                                                      0x3189
++#define mmDSCC4_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
++#define mmDSCC4_DSCC_PPS_CONFIG12                                                                      0x318a
++#define mmDSCC4_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
++#define mmDSCC4_DSCC_PPS_CONFIG13                                                                      0x318b
++#define mmDSCC4_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
++#define mmDSCC4_DSCC_PPS_CONFIG14                                                                      0x318c
++#define mmDSCC4_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
++#define mmDSCC4_DSCC_PPS_CONFIG15                                                                      0x318d
++#define mmDSCC4_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
++#define mmDSCC4_DSCC_PPS_CONFIG16                                                                      0x318e
++#define mmDSCC4_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
++#define mmDSCC4_DSCC_PPS_CONFIG17                                                                      0x318f
++#define mmDSCC4_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
++#define mmDSCC4_DSCC_PPS_CONFIG18                                                                      0x3190
++#define mmDSCC4_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
++#define mmDSCC4_DSCC_PPS_CONFIG19                                                                      0x3191
++#define mmDSCC4_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
++#define mmDSCC4_DSCC_PPS_CONFIG20                                                                      0x3192
++#define mmDSCC4_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
++#define mmDSCC4_DSCC_PPS_CONFIG21                                                                      0x3193
++#define mmDSCC4_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
++#define mmDSCC4_DSCC_PPS_CONFIG22                                                                      0x3194
++#define mmDSCC4_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
++#define mmDSCC4_DSCC_MEM_POWER_CONTROL                                                                 0x3195
++#define mmDSCC4_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
++#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3196
++#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
++#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3197
++#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
++#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3198
++#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
++#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3199
++#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
++#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x319a
++#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
++#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x319b
++#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
++#define mmDSCC4_DSCC_MAX_ABS_ERROR0                                                                    0x319c
++#define mmDSCC4_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
++#define mmDSCC4_DSCC_MAX_ABS_ERROR1                                                                    0x319d
++#define mmDSCC4_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
++#define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x319e
++#define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x319f
++#define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x31a0
++#define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x31a1
++#define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x31a2
++#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x31a3
++#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x31a4
++#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x31a5
++#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x31aa
++#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
++
++// addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
++// base address: 0xc700
++#define mmDC_PERFMON23_PERFCOUNTER_CNTL                                                                0x31c0
++#define mmDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX                                                       2
++#define mmDC_PERFMON23_PERFCOUNTER_CNTL2                                                               0x31c1
++#define mmDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
++#define mmDC_PERFMON23_PERFCOUNTER_STATE                                                               0x31c2
++#define mmDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX                                                      2
++#define mmDC_PERFMON23_PERFMON_CNTL                                                                    0x31c3
++#define mmDC_PERFMON23_PERFMON_CNTL_BASE_IDX                                                           2
++#define mmDC_PERFMON23_PERFMON_CNTL2                                                                   0x31c4
++#define mmDC_PERFMON23_PERFMON_CNTL2_BASE_IDX                                                          2
++#define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC                                                         0x31c5
++#define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
++#define mmDC_PERFMON23_PERFMON_CVALUE_LOW                                                              0x31c6
++#define mmDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
++#define mmDC_PERFMON23_PERFMON_HI                                                                      0x31c7
++#define mmDC_PERFMON23_PERFMON_HI_BASE_IDX                                                             2
++#define mmDC_PERFMON23_PERFMON_LOW                                                                     0x31c8
++#define mmDC_PERFMON23_PERFMON_LOW_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dsc5_dispdec_dsc_top_dispdec
++// base address: 0x730
++#define mmDSC_TOP5_DSC_TOP_CONTROL                                                                     0x31cc
++#define mmDSC_TOP5_DSC_TOP_CONTROL_BASE_IDX                                                            2
++#define mmDSC_TOP5_DSC_DEBUG_CONTROL                                                                   0x31cd
++#define mmDSC_TOP5_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
++
++
++// addressBlock: dce_dc_dsc5_dispdec_dsccif_dispdec
++// base address: 0x730
++#define mmDSCCIF5_DSCCIF_CONFIG0                                                                       0x31d1
++#define mmDSCCIF5_DSCCIF_CONFIG0_BASE_IDX                                                              2
++#define mmDSCCIF5_DSCCIF_CONFIG1                                                                       0x31d2
++#define mmDSCCIF5_DSCCIF_CONFIG1_BASE_IDX                                                              2
++
++
++// addressBlock: dce_dc_dsc5_dispdec_dscc_dispdec
++// base address: 0x730
++#define mmDSCC5_DSCC_CONFIG0                                                                           0x31d6
++#define mmDSCC5_DSCC_CONFIG0_BASE_IDX                                                                  2
++#define mmDSCC5_DSCC_CONFIG1                                                                           0x31d7
++#define mmDSCC5_DSCC_CONFIG1_BASE_IDX                                                                  2
++#define mmDSCC5_DSCC_STATUS                                                                            0x31d8
++#define mmDSCC5_DSCC_STATUS_BASE_IDX                                                                   2
++#define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x31d9
++#define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
++#define mmDSCC5_DSCC_PPS_CONFIG0                                                                       0x31da
++#define mmDSCC5_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
++#define mmDSCC5_DSCC_PPS_CONFIG1                                                                       0x31db
++#define mmDSCC5_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
++#define mmDSCC5_DSCC_PPS_CONFIG2                                                                       0x31dc
++#define mmDSCC5_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
++#define mmDSCC5_DSCC_PPS_CONFIG3                                                                       0x31dd
++#define mmDSCC5_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
++#define mmDSCC5_DSCC_PPS_CONFIG4                                                                       0x31de
++#define mmDSCC5_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
++#define mmDSCC5_DSCC_PPS_CONFIG5                                                                       0x31df
++#define mmDSCC5_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
++#define mmDSCC5_DSCC_PPS_CONFIG6                                                                       0x31e0
++#define mmDSCC5_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
++#define mmDSCC5_DSCC_PPS_CONFIG7                                                                       0x31e1
++#define mmDSCC5_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
++#define mmDSCC5_DSCC_PPS_CONFIG8                                                                       0x31e2
++#define mmDSCC5_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
++#define mmDSCC5_DSCC_PPS_CONFIG9                                                                       0x31e3
++#define mmDSCC5_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
++#define mmDSCC5_DSCC_PPS_CONFIG10                                                                      0x31e4
++#define mmDSCC5_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
++#define mmDSCC5_DSCC_PPS_CONFIG11                                                                      0x31e5
++#define mmDSCC5_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
++#define mmDSCC5_DSCC_PPS_CONFIG12                                                                      0x31e6
++#define mmDSCC5_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
++#define mmDSCC5_DSCC_PPS_CONFIG13                                                                      0x31e7
++#define mmDSCC5_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
++#define mmDSCC5_DSCC_PPS_CONFIG14                                                                      0x31e8
++#define mmDSCC5_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
++#define mmDSCC5_DSCC_PPS_CONFIG15                                                                      0x31e9
++#define mmDSCC5_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
++#define mmDSCC5_DSCC_PPS_CONFIG16                                                                      0x31ea
++#define mmDSCC5_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
++#define mmDSCC5_DSCC_PPS_CONFIG17                                                                      0x31eb
++#define mmDSCC5_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
++#define mmDSCC5_DSCC_PPS_CONFIG18                                                                      0x31ec
++#define mmDSCC5_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
++#define mmDSCC5_DSCC_PPS_CONFIG19                                                                      0x31ed
++#define mmDSCC5_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
++#define mmDSCC5_DSCC_PPS_CONFIG20                                                                      0x31ee
++#define mmDSCC5_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
++#define mmDSCC5_DSCC_PPS_CONFIG21                                                                      0x31ef
++#define mmDSCC5_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
++#define mmDSCC5_DSCC_PPS_CONFIG22                                                                      0x31f0
++#define mmDSCC5_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
++#define mmDSCC5_DSCC_MEM_POWER_CONTROL                                                                 0x31f1
++#define mmDSCC5_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
++#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x31f2
++#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
++#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x31f3
++#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
++#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x31f4
++#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
++#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x31f5
++#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
++#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x31f6
++#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
++#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x31f7
++#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
++#define mmDSCC5_DSCC_MAX_ABS_ERROR0                                                                    0x31f8
++#define mmDSCC5_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
++#define mmDSCC5_DSCC_MAX_ABS_ERROR1                                                                    0x31f9
++#define mmDSCC5_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
++#define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x31fa
++#define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x31fb
++#define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x31fc
++#define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x31fd
++#define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
++#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x31fe
++#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x31ff
++#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3200
++#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3201
++#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
++#define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3206
++#define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
++
++
++// addressBlock: dce_dc_dsc5_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
++// base address: 0xc870
++#define mmDC_PERFMON24_PERFCOUNTER_CNTL                                                                0x321c
++#define mmDC_PERFMON24_PERFCOUNTER_CNTL_BASE_IDX                                                       2
++#define mmDC_PERFMON24_PERFCOUNTER_CNTL2                                                               0x321d
++#define mmDC_PERFMON24_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
++#define mmDC_PERFMON24_PERFCOUNTER_STATE                                                               0x321e
++#define mmDC_PERFMON24_PERFCOUNTER_STATE_BASE_IDX                                                      2
++#define mmDC_PERFMON24_PERFMON_CNTL                                                                    0x321f
++#define mmDC_PERFMON24_PERFMON_CNTL_BASE_IDX                                                           2
++#define mmDC_PERFMON24_PERFMON_CNTL2                                                                   0x3220
++#define mmDC_PERFMON24_PERFMON_CNTL2_BASE_IDX                                                          2
++#define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC                                                         0x3221
++#define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
++#define mmDC_PERFMON24_PERFMON_CVALUE_LOW                                                              0x3222
++#define mmDC_PERFMON24_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
++#define mmDC_PERFMON24_PERFMON_HI                                                                      0x3223
++#define mmDC_PERFMON24_PERFMON_HI_BASE_IDX                                                             2
++#define mmDC_PERFMON24_PERFMON_LOW                                                                     0x3224
++#define mmDC_PERFMON24_PERFMON_LOW_BASE_IDX                                                            2
++
++
++// addressBlock: dce_dc_dmu_dmcub_dispdec
++// base address: 0x0
++#define mmDMCUB_REGION0_OFFSET                                                                         0x3238
++#define mmDMCUB_REGION0_OFFSET_BASE_IDX                                                                2
++#define mmDMCUB_REGION0_OFFSET_HIGH                                                                    0x3239
++#define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX                                                           2
++#define mmDMCUB_REGION1_OFFSET                                                                         0x323a
++#define mmDMCUB_REGION1_OFFSET_BASE_IDX                                                                2
++#define mmDMCUB_REGION1_OFFSET_HIGH                                                                    0x323b
++#define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX                                                           2
++#define mmDMCUB_REGION2_OFFSET                                                                         0x323c
++#define mmDMCUB_REGION2_OFFSET_BASE_IDX                                                                2
++#define mmDMCUB_REGION2_OFFSET_HIGH                                                                    0x323d
++#define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX                                                           2
++#define mmDMCUB_REGION4_OFFSET                                                                         0x3240
++#define mmDMCUB_REGION4_OFFSET_BASE_IDX                                                                2
++#define mmDMCUB_REGION4_OFFSET_HIGH                                                                    0x3241
++#define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX                                                           2
++#define mmDMCUB_REGION5_OFFSET                                                                         0x3242
++#define mmDMCUB_REGION5_OFFSET_BASE_IDX                                                                2
++#define mmDMCUB_REGION5_OFFSET_HIGH                                                                    0x3243
++#define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX                                                           2
++#define mmDMCUB_REGION6_OFFSET                                                                         0x3244
++#define mmDMCUB_REGION6_OFFSET_BASE_IDX                                                                2
++#define mmDMCUB_REGION6_OFFSET_HIGH                                                                    0x3245
++#define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX                                                           2
++#define mmDMCUB_REGION7_OFFSET                                                                         0x3246
++#define mmDMCUB_REGION7_OFFSET_BASE_IDX                                                                2
++#define mmDMCUB_REGION7_OFFSET_HIGH                                                                    0x3247
++#define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX                                                           2
++#define mmDMCUB_REGION0_TOP_ADDRESS                                                                    0x3248
++#define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX                                                           2
++#define mmDMCUB_REGION1_TOP_ADDRESS                                                                    0x3249
++#define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX                                                           2
++#define mmDMCUB_REGION2_TOP_ADDRESS                                                                    0x324a
++#define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX                                                           2
++#define mmDMCUB_REGION4_TOP_ADDRESS                                                                    0x324b
++#define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX                                                           2
++#define mmDMCUB_REGION5_TOP_ADDRESS                                                                    0x324c
++#define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX                                                           2
++#define mmDMCUB_REGION6_TOP_ADDRESS                                                                    0x324d
++#define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX                                                           2
++#define mmDMCUB_REGION7_TOP_ADDRESS                                                                    0x324e
++#define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX                                                           2
++#define mmDMCUB_REGION3_CW0_BASE_ADDRESS                                                               0x324f
++#define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX                                                      2
++#define mmDMCUB_REGION3_CW1_BASE_ADDRESS                                                               0x3250
++#define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX                                                      2
++#define mmDMCUB_REGION3_CW2_BASE_ADDRESS                                                               0x3251
++#define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX                                                      2
++#define mmDMCUB_REGION3_CW3_BASE_ADDRESS                                                               0x3252
++#define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX                                                      2
++#define mmDMCUB_REGION3_CW4_BASE_ADDRESS                                                               0x3253
++#define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX                                                      2
++#define mmDMCUB_REGION3_CW5_BASE_ADDRESS                                                               0x3254
++#define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX                                                      2
++#define mmDMCUB_REGION3_CW6_BASE_ADDRESS                                                               0x3255
++#define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX                                                      2
++#define mmDMCUB_REGION3_CW7_BASE_ADDRESS                                                               0x3256
++#define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX                                                      2
++#define mmDMCUB_REGION3_CW0_TOP_ADDRESS                                                                0x3257
++#define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX                                                       2
++#define mmDMCUB_REGION3_CW1_TOP_ADDRESS                                                                0x3258
++#define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX                                                       2
++#define mmDMCUB_REGION3_CW2_TOP_ADDRESS                                                                0x3259
++#define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX                                                       2
++#define mmDMCUB_REGION3_CW3_TOP_ADDRESS                                                                0x325a
++#define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX                                                       2
++#define mmDMCUB_REGION3_CW4_TOP_ADDRESS                                                                0x325b
++#define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX                                                       2
++#define mmDMCUB_REGION3_CW5_TOP_ADDRESS                                                                0x325c
++#define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX                                                       2
++#define mmDMCUB_REGION3_CW6_TOP_ADDRESS                                                                0x325d
++#define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX                                                       2
++#define mmDMCUB_REGION3_CW7_TOP_ADDRESS                                                                0x325e
++#define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX                                                       2
++#define mmDMCUB_REGION3_CW0_OFFSET                                                                     0x325f
++#define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX                                                            2
++#define mmDMCUB_REGION3_CW0_OFFSET_HIGH                                                                0x3260
++#define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX                                                       2
++#define mmDMCUB_REGION3_CW1_OFFSET                                                                     0x3261
++#define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX                                                            2
++#define mmDMCUB_REGION3_CW1_OFFSET_HIGH                                                                0x3262
++#define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX                                                       2
++#define mmDMCUB_REGION3_CW2_OFFSET                                                                     0x3263
++#define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX                                                            2
++#define mmDMCUB_REGION3_CW2_OFFSET_HIGH                                                                0x3264
++#define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX                                                       2
++#define mmDMCUB_REGION3_CW3_OFFSET                                                                     0x3265
++#define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX                                                            2
++#define mmDMCUB_REGION3_CW3_OFFSET_HIGH                                                                0x3266
++#define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX                                                       2
++#define mmDMCUB_REGION3_CW4_OFFSET                                                                     0x3267
++#define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX                                                            2
++#define mmDMCUB_REGION3_CW4_OFFSET_HIGH                                                                0x3268
++#define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX                                                       2
++#define mmDMCUB_REGION3_CW5_OFFSET                                                                     0x3269
++#define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX                                                            2
++#define mmDMCUB_REGION3_CW5_OFFSET_HIGH                                                                0x326a
++#define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX                                                       2
++#define mmDMCUB_REGION3_CW6_OFFSET                                                                     0x326b
++#define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX                                                            2
++#define mmDMCUB_REGION3_CW6_OFFSET_HIGH                                                                0x326c
++#define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX                                                       2
++#define mmDMCUB_REGION3_CW7_OFFSET                                                                     0x326d
++#define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX                                                            2
++#define mmDMCUB_REGION3_CW7_OFFSET_HIGH                                                                0x326e
++#define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX                                                       2
++#define mmDMCUB_INTERRUPT_ENABLE                                                                       0x326f
++#define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX                                                              2
++#define mmDMCUB_INTERRUPT_ACK                                                                          0x3270
++#define mmDMCUB_INTERRUPT_ACK_BASE_IDX                                                                 2
++#define mmDMCUB_INTERRUPT_STATUS                                                                       0x3271
++#define mmDMCUB_INTERRUPT_STATUS_BASE_IDX                                                              2
++#define mmDMCUB_INTERRUPT_TYPE                                                                         0x3272
++#define mmDMCUB_INTERRUPT_TYPE_BASE_IDX                                                                2
++#define mmDMCUB_EXT_INTERRUPT_STATUS                                                                   0x3273
++#define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX                                                          2
++#define mmDMCUB_EXT_INTERRUPT_CTXID                                                                    0x3274
++#define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX                                                           2
++#define mmDMCUB_EXT_INTERRUPT_ACK                                                                      0x3275
++#define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX                                                             2
++#define mmDMCUB_INST_FETCH_FAULT_ADDR                                                                  0x3276
++#define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX                                                         2
++#define mmDMCUB_DATA_WRITE_FAULT_ADDR                                                                  0x3277
++#define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX                                                         2
++#define mmDMCUB_SEC_CNTL                                                                               0x3278
++#define mmDMCUB_SEC_CNTL_BASE_IDX                                                                      2
++#define mmDMCUB_MEM_CNTL                                                                               0x3279
++#define mmDMCUB_MEM_CNTL_BASE_IDX                                                                      2
++#define mmDMCUB_INBOX0_BASE_ADDRESS                                                                    0x327a
++#define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX                                                           2
++#define mmDMCUB_INBOX0_SIZE                                                                            0x327b
++#define mmDMCUB_INBOX0_SIZE_BASE_IDX                                                                   2
++#define mmDMCUB_INBOX0_WPTR                                                                            0x327c
++#define mmDMCUB_INBOX0_WPTR_BASE_IDX                                                                   2
++#define mmDMCUB_INBOX0_RPTR                                                                            0x327d
++#define mmDMCUB_INBOX0_RPTR_BASE_IDX                                                                   2
++#define mmDMCUB_INBOX1_BASE_ADDRESS                                                                    0x327e
++#define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX                                                           2
++#define mmDMCUB_INBOX1_SIZE                                                                            0x327f
++#define mmDMCUB_INBOX1_SIZE_BASE_IDX                                                                   2
++#define mmDMCUB_INBOX1_WPTR                                                                            0x3280
++#define mmDMCUB_INBOX1_WPTR_BASE_IDX                                                                   2
++#define mmDMCUB_INBOX1_RPTR                                                                            0x3281
++#define mmDMCUB_INBOX1_RPTR_BASE_IDX                                                                   2
++#define mmDMCUB_OUTBOX0_BASE_ADDRESS                                                                   0x3282
++#define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX                                                          2
++#define mmDMCUB_OUTBOX0_SIZE                                                                           0x3283
++#define mmDMCUB_OUTBOX0_SIZE_BASE_IDX                                                                  2
++#define mmDMCUB_OUTBOX0_WPTR                                                                           0x3284
++#define mmDMCUB_OUTBOX0_WPTR_BASE_IDX                                                                  2
++#define mmDMCUB_OUTBOX0_RPTR                                                                           0x3285
++#define mmDMCUB_OUTBOX0_RPTR_BASE_IDX                                                                  2
++#define mmDMCUB_OUTBOX1_BASE_ADDRESS                                                                   0x3286
++#define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX                                                          2
++#define mmDMCUB_OUTBOX1_SIZE                                                                           0x3287
++#define mmDMCUB_OUTBOX1_SIZE_BASE_IDX                                                                  2
++#define mmDMCUB_OUTBOX1_WPTR                                                                           0x3288
++#define mmDMCUB_OUTBOX1_WPTR_BASE_IDX                                                                  2
++#define mmDMCUB_OUTBOX1_RPTR                                                                           0x3289
++#define mmDMCUB_OUTBOX1_RPTR_BASE_IDX                                                                  2
++#define mmDMCUB_TIMER_TRIGGER0                                                                         0x328a
++#define mmDMCUB_TIMER_TRIGGER0_BASE_IDX                                                                2
++#define mmDMCUB_TIMER_TRIGGER1                                                                         0x328b
++#define mmDMCUB_TIMER_TRIGGER1_BASE_IDX                                                                2
++#define mmDMCUB_TIMER_WINDOW                                                                           0x328c
++#define mmDMCUB_TIMER_WINDOW_BASE_IDX                                                                  2
++#define mmDMCUB_SCRATCH0                                                                               0x328d
++#define mmDMCUB_SCRATCH0_BASE_IDX                                                                      2
++#define mmDMCUB_SCRATCH1                                                                               0x328e
++#define mmDMCUB_SCRATCH1_BASE_IDX                                                                      2
++#define mmDMCUB_SCRATCH2                                                                               0x328f
++#define mmDMCUB_SCRATCH2_BASE_IDX                                                                      2
++#define mmDMCUB_SCRATCH3                                                                               0x3290
++#define mmDMCUB_SCRATCH3_BASE_IDX                                                                      2
++#define mmDMCUB_SCRATCH4                                                                               0x3291
++#define mmDMCUB_SCRATCH4_BASE_IDX                                                                      2
++#define mmDMCUB_SCRATCH5                                                                               0x3292
++#define mmDMCUB_SCRATCH5_BASE_IDX                                                                      2
++#define mmDMCUB_SCRATCH6                                                                               0x3293
++#define mmDMCUB_SCRATCH6_BASE_IDX                                                                      2
++#define mmDMCUB_SCRATCH7                                                                               0x3294
++#define mmDMCUB_SCRATCH7_BASE_IDX                                                                      2
++#define mmDMCUB_SCRATCH8                                                                               0x3295
++#define mmDMCUB_SCRATCH8_BASE_IDX                                                                      2
++#define mmDMCUB_SCRATCH9                                                                               0x3296
++#define mmDMCUB_SCRATCH9_BASE_IDX                                                                      2
++#define mmDMCUB_SCRATCH10                                                                              0x3297
++#define mmDMCUB_SCRATCH10_BASE_IDX                                                                     2
++#define mmDMCUB_SCRATCH11                                                                              0x3298
++#define mmDMCUB_SCRATCH11_BASE_IDX                                                                     2
++#define mmDMCUB_SCRATCH12                                                                              0x3299
++#define mmDMCUB_SCRATCH12_BASE_IDX                                                                     2
++#define mmDMCUB_SCRATCH13                                                                              0x329a
++#define mmDMCUB_SCRATCH13_BASE_IDX                                                                     2
++#define mmDMCUB_SCRATCH14                                                                              0x329b
++#define mmDMCUB_SCRATCH14_BASE_IDX                                                                     2
++#define mmDMCUB_SCRATCH15                                                                              0x329c
++#define mmDMCUB_SCRATCH15_BASE_IDX                                                                     2
++#define mmDMCUB_CNTL                                                                                   0x32a0
++#define mmDMCUB_CNTL_BASE_IDX                                                                          2
++#define mmDMCUB_GPINT_DATAIN0                                                                          0x32a1
++#define mmDMCUB_GPINT_DATAIN0_BASE_IDX                                                                 2
++#define mmDMCUB_GPINT_DATAIN1                                                                          0x32a2
++#define mmDMCUB_GPINT_DATAIN1_BASE_IDX                                                                 2
++#define mmDMCUB_GPINT_DATAOUT                                                                          0x32a3
++#define mmDMCUB_GPINT_DATAOUT_BASE_IDX                                                                 2
++#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR                                                           0x32a4
++#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX                                                  2
++#define mmDMCUB_LS_WAKE_INT_ENABLE                                                                     0x32a5
++#define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX                                                            2
++#define mmDMCUB_MEM_PWR_CNTL                                                                           0x32a6
++#define mmDMCUB_MEM_PWR_CNTL_BASE_IDX                                                                  2
++#define mmDMCUB_TIMER_CURRENT                                                                          0x32a7
++#define mmDMCUB_TIMER_CURRENT_BASE_IDX                                                                 2
++#define mmDMCUB_PROC_ID                                                                                0x32a9
++#define mmDMCUB_PROC_ID_BASE_IDX                                                                       2
++
++
++// addressBlock: dce_dc_mmhubbub_mcif_wb2_dispdec
++// base address: 0xc6b8
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x3460
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                  2
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R                                                           0x3461
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX                                                  2
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS                                                               0x3462
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_BASE_IDX                                                      2
++#define mmMCIF_WB2_MCIF_WB_BUF_PITCH                                                                   0x3463
++#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_BASE_IDX                                                          2
++#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS                                                                0x3464
++#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_BASE_IDX                                                       2
++#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2                                                               0x3465
++#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_BASE_IDX                                                      2
++#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS                                                                0x3466
++#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_BASE_IDX                                                       2
++#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2                                                               0x3467
++#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_BASE_IDX                                                      2
++#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS                                                                0x3468
++#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_BASE_IDX                                                       2
++#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2                                                               0x3469
++#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_BASE_IDX                                                      2
++#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS                                                                0x346a
++#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_BASE_IDX                                                       2
++#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2                                                               0x346b
++#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_BASE_IDX                                                      2
++#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL                                                         0x346c
++#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                2
++#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE                                                                 0x346d
++#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_BASE_IDX                                                        2
++#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX                                                            0x346e
++#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                   2
++#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA                                                             0x346f
++#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                    2
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y                                                                0x3470
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                       2
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET                                                         0x3471
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C                                                                0x3472
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                       2
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET                                                         0x3473
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y                                                                0x3474
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                       2
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET                                                         0x3475
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C                                                                0x3476
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                       2
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET                                                         0x3477
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y                                                                0x3478
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                       2
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET                                                         0x3479
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C                                                                0x347a
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                       2
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET                                                         0x347b
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y                                                                0x347c
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                       2
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET                                                         0x347d
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C                                                                0x347e
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                       2
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET                                                         0x347f
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX                                                2
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL                                                          0x3480
++#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                 2
++#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                 0x3481
++#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                        2
++#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL                                                           0x3482
++#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                  2
++#define mmMCIF_WB2_MCIF_WB_WATERMARK                                                                   0x3483
++#define mmMCIF_WB2_MCIF_WB_WATERMARK_BASE_IDX                                                          2
++#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL                                                         0x3484
++#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                2
++#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL                                                                0x3485
++#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_BASE_IDX                                                       2
++#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL                                                        0x3486
++#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                               2
++#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL                                                                0x3487
++#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_BASE_IDX                                                       2
++#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE                                                               0x3489
++#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                      2
++#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE                                                             0x348a
++#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                    2
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH                                                           0x348b
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH                                                           0x348c
++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH                                                           0x348d
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH                                                           0x348e
++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH                                                           0x348f
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH                                                           0x3490
++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH                                                           0x3491
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH                                                           0x3492
++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                  2
++#define mmMCIF_WB2_MCIF_WB_BUF_1_RESOLUTION                                                            0x3493
++#define mmMCIF_WB2_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                   2
++#define mmMCIF_WB2_MCIF_WB_BUF_2_RESOLUTION                                                            0x3494
++#define mmMCIF_WB2_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                   2
++#define mmMCIF_WB2_MCIF_WB_BUF_3_RESOLUTION                                                            0x3495
++#define mmMCIF_WB2_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                   2
++#define mmMCIF_WB2_MCIF_WB_BUF_4_RESOLUTION                                                            0x3496
++#define mmMCIF_WB2_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                   2
++
++
++// addressBlock: dce_dc_dchvm_hvm_dispdec
++// base address: 0x0
++#define mmDCHVM_CTRL0                                                                                  0x016b
++#define mmDCHVM_CTRL0_BASE_IDX                                                                         3
++#define mmDCHVM_CTRL1                                                                                  0x016c
++#define mmDCHVM_CTRL1_BASE_IDX                                                                         3
++#define mmDCHVM_CLK_CTRL                                                                               0x016d
++#define mmDCHVM_CLK_CTRL_BASE_IDX                                                                      3
++#define mmDCHVM_MEM_CTRL                                                                               0x016e
++#define mmDCHVM_MEM_CTRL_BASE_IDX                                                                      3
++#define mmDCHVM_RIOMMU_CTRL0                                                                           0x016f
++#define mmDCHVM_RIOMMU_CTRL0_BASE_IDX                                                                  3
++#define mmDCHVM_RIOMMU_STAT0                                                                           0x0170
++#define mmDCHVM_RIOMMU_STAT0_BASE_IDX                                                                  3
++
++
++// addressBlock: vga_vgaseqind
++// base address: 0x0
++#define ixSEQ00                                                                                        0x0000
++#define ixSEQ01                                                                                        0x0001
++#define ixSEQ02                                                                                        0x0002
++#define ixSEQ03                                                                                        0x0003
++#define ixSEQ04                                                                                        0x0004
++
++
++// addressBlock: vga_vgacrtind
++// base address: 0x0
++#define ixCRT00                                                                                        0x0000
++#define ixCRT01                                                                                        0x0001
++#define ixCRT02                                                                                        0x0002
++#define ixCRT03                                                                                        0x0003
++#define ixCRT04                                                                                        0x0004
++#define ixCRT05                                                                                        0x0005
++#define ixCRT06                                                                                        0x0006
++#define ixCRT07                                                                                        0x0007
++#define ixCRT08                                                                                        0x0008
++#define ixCRT09                                                                                        0x0009
++#define ixCRT0A                                                                                        0x000a
++#define ixCRT0B                                                                                        0x000b
++#define ixCRT0C                                                                                        0x000c
++#define ixCRT0D                                                                                        0x000d
++#define ixCRT0E                                                                                        0x000e
++#define ixCRT0F                                                                                        0x000f
++#define ixCRT10                                                                                        0x0010
++#define ixCRT11                                                                                        0x0011
++#define ixCRT12                                                                                        0x0012
++#define ixCRT13                                                                                        0x0013
++#define ixCRT14                                                                                        0x0014
++#define ixCRT15                                                                                        0x0015
++#define ixCRT16                                                                                        0x0016
++#define ixCRT17                                                                                        0x0017
++#define ixCRT18                                                                                        0x0018
++#define ixCRT1E                                                                                        0x001e
++#define ixCRT1F                                                                                        0x001f
++#define ixCRT22                                                                                        0x0022
++
++
++// addressBlock: vga_vgagrphind
++// base address: 0x0
++#define ixGRA00                                                                                        0x0000
++#define ixGRA01                                                                                        0x0001
++#define ixGRA02                                                                                        0x0002
++#define ixGRA03                                                                                        0x0003
++#define ixGRA04                                                                                        0x0004
++#define ixGRA05                                                                                        0x0005
++#define ixGRA06                                                                                        0x0006
++#define ixGRA07                                                                                        0x0007
++#define ixGRA08                                                                                        0x0008
++
++
++// addressBlock: vga_vgaattrind
++// base address: 0x0
++#define ixATTR00                                                                                       0x0000
++#define ixATTR01                                                                                       0x0001
++#define ixATTR02                                                                                       0x0002
++#define ixATTR03                                                                                       0x0003
++#define ixATTR04                                                                                       0x0004
++#define ixATTR05                                                                                       0x0005
++#define ixATTR06                                                                                       0x0006
++#define ixATTR07                                                                                       0x0007
++#define ixATTR08                                                                                       0x0008
++#define ixATTR09                                                                                       0x0009
++#define ixATTR0A                                                                                       0x000a
++#define ixATTR0B                                                                                       0x000b
++#define ixATTR0C                                                                                       0x000c
++#define ixATTR0D                                                                                       0x000d
++#define ixATTR0E                                                                                       0x000e
++#define ixATTR0F                                                                                       0x000f
++#define ixATTR10                                                                                       0x0010
++#define ixATTR11                                                                                       0x0011
++#define ixATTR12                                                                                       0x0012
++#define ixATTR13                                                                                       0x0013
++#define ixATTR14                                                                                       0x0014
++
++
++// addressBlock: azendpoint_f2codecind
++// base address: 0x0
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                                           0x2200
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                          0x2706
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                                          0x270d
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                                        0x270e
++#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                                                     0x2724
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                                        0x273e
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                                                  0x2770
++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                              0x2771
++#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x2f09
++#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                                     0x2f0a
++#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                                           0x2f0b
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY                                   0x3702
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                                                   0x3707
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                                             0x3708
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                               0x3709
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                                   0x371c
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                                 0x371d
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                                 0x371e
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                                 0x371f
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION                                      0x3770
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                                               0x3771
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                                                    0x3772
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                                                 0x3776
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                                            0x3776
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                                            0x3777
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                                            0x3778
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                                            0x3779
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                                            0x377a
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                                          0x377b
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                                            0x3780
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                                             0x3781
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                                             0x3785
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                                             0x3786
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                                             0x3787
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                                             0x3788
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                                0x3789
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                                    0x378a
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                                    0x378b
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                                    0x378c
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                                    0x378d
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                                    0x378e
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                                    0x378f
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                                    0x3790
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                                    0x3791
++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                                    0x3792
++#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                                         0x3793
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                                            0x3797
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                            0x3798
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                                             0x3799
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                              0x379a
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                                                      0x379b
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                                                   0x379c
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                                  0x379d
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                                 0x379e
++#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                      0x3f09
++#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                                                   0x3f0c
++#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                                         0x3f0e
++
++
++// addressBlock: azendpoint_descriptorind
++// base address: 0x0
++#define ixAUDIO_DESCRIPTOR0                                                                            0x0001
++#define ixAUDIO_DESCRIPTOR1                                                                            0x0002
++#define ixAUDIO_DESCRIPTOR2                                                                            0x0003
++#define ixAUDIO_DESCRIPTOR3                                                                            0x0004
++#define ixAUDIO_DESCRIPTOR4                                                                            0x0005
++#define ixAUDIO_DESCRIPTOR5                                                                            0x0006
++#define ixAUDIO_DESCRIPTOR6                                                                            0x0007
++#define ixAUDIO_DESCRIPTOR7                                                                            0x0008
++#define ixAUDIO_DESCRIPTOR8                                                                            0x0009
++#define ixAUDIO_DESCRIPTOR9                                                                            0x000a
++#define ixAUDIO_DESCRIPTOR10                                                                           0x000b
++#define ixAUDIO_DESCRIPTOR11                                                                           0x000c
++#define ixAUDIO_DESCRIPTOR12                                                                           0x000d
++#define ixAUDIO_DESCRIPTOR13                                                                           0x000e
++
++
++// addressBlock: azendpoint_sinkinfoind
++// base address: 0x0
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                                                  0x0000
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                                       0x0001
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                                             0x0002
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                                          0x0003
++#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                                          0x0004
++#define ixSINK_DESCRIPTION0                                                                            0x0005
++#define ixSINK_DESCRIPTION1                                                                            0x0006
++#define ixSINK_DESCRIPTION2                                                                            0x0007
++#define ixSINK_DESCRIPTION3                                                                            0x0008
++#define ixSINK_DESCRIPTION4                                                                            0x0009
++#define ixSINK_DESCRIPTION5                                                                            0x000a
++#define ixSINK_DESCRIPTION6                                                                            0x000b
++#define ixSINK_DESCRIPTION7                                                                            0x000c
++#define ixSINK_DESCRIPTION8                                                                            0x000d
++#define ixSINK_DESCRIPTION9                                                                            0x000e
++#define ixSINK_DESCRIPTION10                                                                           0x000f
++#define ixSINK_DESCRIPTION11                                                                           0x0010
++#define ixSINK_DESCRIPTION12                                                                           0x0011
++#define ixSINK_DESCRIPTION13                                                                           0x0012
++#define ixSINK_DESCRIPTION14                                                                           0x0013
++#define ixSINK_DESCRIPTION15                                                                           0x0014
++#define ixSINK_DESCRIPTION16                                                                           0x0015
++#define ixSINK_DESCRIPTION17                                                                           0x0016
++
++
++// addressBlock: azf0controller_azinputcrc0resultind
++// base address: 0x0
++#define ixAZALIA_INPUT_CRC0_CHANNEL0                                                                   0x0000
++#define ixAZALIA_INPUT_CRC0_CHANNEL1                                                                   0x0001
++#define ixAZALIA_INPUT_CRC0_CHANNEL2                                                                   0x0002
++#define ixAZALIA_INPUT_CRC0_CHANNEL3                                                                   0x0003
++#define ixAZALIA_INPUT_CRC0_CHANNEL4                                                                   0x0004
++#define ixAZALIA_INPUT_CRC0_CHANNEL5                                                                   0x0005
++#define ixAZALIA_INPUT_CRC0_CHANNEL6                                                                   0x0006
++#define ixAZALIA_INPUT_CRC0_CHANNEL7                                                                   0x0007
++
++
++// addressBlock: azf0controller_azinputcrc1resultind
++// base address: 0x0
++#define ixAZALIA_INPUT_CRC1_CHANNEL0                                                                   0x0000
++#define ixAZALIA_INPUT_CRC1_CHANNEL1                                                                   0x0001
++#define ixAZALIA_INPUT_CRC1_CHANNEL2                                                                   0x0002
++#define ixAZALIA_INPUT_CRC1_CHANNEL3                                                                   0x0003
++#define ixAZALIA_INPUT_CRC1_CHANNEL4                                                                   0x0004
++#define ixAZALIA_INPUT_CRC1_CHANNEL5                                                                   0x0005
++#define ixAZALIA_INPUT_CRC1_CHANNEL6                                                                   0x0006
++#define ixAZALIA_INPUT_CRC1_CHANNEL7                                                                   0x0007
++
++
++// addressBlock: azf0controller_azcrc0resultind
++// base address: 0x0
++#define ixAZALIA_CRC0_CHANNEL0                                                                         0x0000
++#define ixAZALIA_CRC0_CHANNEL1                                                                         0x0001
++#define ixAZALIA_CRC0_CHANNEL2                                                                         0x0002
++#define ixAZALIA_CRC0_CHANNEL3                                                                         0x0003
++#define ixAZALIA_CRC0_CHANNEL4                                                                         0x0004
++#define ixAZALIA_CRC0_CHANNEL5                                                                         0x0005
++#define ixAZALIA_CRC0_CHANNEL6                                                                         0x0006
++#define ixAZALIA_CRC0_CHANNEL7                                                                         0x0007
++
++
++// addressBlock: azf0controller_azcrc1resultind
++// base address: 0x0
++#define ixAZALIA_CRC1_CHANNEL0                                                                         0x0000
++#define ixAZALIA_CRC1_CHANNEL1                                                                         0x0001
++#define ixAZALIA_CRC1_CHANNEL2                                                                         0x0002
++#define ixAZALIA_CRC1_CHANNEL3                                                                         0x0003
++#define ixAZALIA_CRC1_CHANNEL4                                                                         0x0004
++#define ixAZALIA_CRC1_CHANNEL5                                                                         0x0005
++#define ixAZALIA_CRC1_CHANNEL6                                                                         0x0006
++#define ixAZALIA_CRC1_CHANNEL7                                                                         0x0007
++
++
++// addressBlock: azinputendpoint_f2codecind
++// base address: 0x0
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                                     0x6200
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                    0x6706
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                                    0x670d
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                          0x6f09
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                               0x6f0a
++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                                     0x6f0b
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                                             0x7707
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                                       0x7708
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                                         0x7709
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                             0x771c
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                           0x771d
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                           0x771e
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                           0x771f
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                                         0x7771
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                                       0x7777
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                                       0x7778
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                                       0x7779
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                                       0x777a
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                                        0x777c
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                                       0x7785
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                                       0x7786
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                                       0x7787
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                                       0x7788
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                      0x7798
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                                       0x7799
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                        0x779a
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                                       0x779b
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                                                  0x779c
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                                           0x779d
++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                                           0x779e
++#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x7f09
++#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                                             0x7f0c
++
++
++// addressBlock: azroot_f2codecind
++// base address: 0x0
++#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0f00
++#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0f02
++#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                                        0x0f04
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x1705
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x1720
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2                                     0x1721
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3                                     0x1722
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4                                     0x1723
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x1770
++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                                       0x17ff
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT                                    0x1f04
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x1f05
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x1f0a
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x1f0b
++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x1f0f
++
++
++// addressBlock: azf0stream0_streamind
++// base address: 0x0
++#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
++#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
++#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
++#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
++#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
++
++
++// addressBlock: azf0stream1_streamind
++// base address: 0x0
++#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
++#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
++#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
++#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
++#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
++
++
++// addressBlock: azf0stream2_streamind
++// base address: 0x0
++#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
++#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
++#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
++#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
++#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
++
++
++// addressBlock: azf0stream3_streamind
++// base address: 0x0
++#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
++#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
++#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
++#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
++#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
++
++
++// addressBlock: azf0stream4_streamind
++// base address: 0x0
++#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
++#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
++#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
++#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
++#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
++
++
++// addressBlock: azf0stream5_streamind
++// base address: 0x0
++#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
++#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
++#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
++#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
++#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
++
++
++// addressBlock: azf0stream6_streamind
++// base address: 0x0
++#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
++#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
++#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
++#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
++#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
++
++
++// addressBlock: azf0stream7_streamind
++// base address: 0x0
++#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
++#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
++#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
++#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
++#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
++
++
++// addressBlock: azf0stream8_streamind
++// base address: 0x0
++#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
++#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
++#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
++#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
++#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
++
++
++// addressBlock: azf0stream9_streamind
++// base address: 0x0
++#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
++#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
++#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
++#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
++#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
++
++
++// addressBlock: azf0stream10_streamind
++// base address: 0x0
++#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
++#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
++#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
++#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
++#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
++
++
++// addressBlock: azf0stream11_streamind
++// base address: 0x0
++#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
++#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
++#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
++#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
++#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
++
++
++// addressBlock: azf0stream12_streamind
++// base address: 0x0
++#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
++#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
++#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
++#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
++#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
++
++
++// addressBlock: azf0stream13_streamind
++// base address: 0x0
++#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
++#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
++#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
++#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
++#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
++
++
++// addressBlock: azf0stream14_streamind
++// base address: 0x0
++#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
++#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
++#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
++#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
++#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
++
++
++// addressBlock: azf0stream15_streamind
++// base address: 0x0
++#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
++#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
++#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
++#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
++#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
++
++
++// addressBlock: azf0endpoint0_endpointind
++// base address: 0x0
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
++#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
++#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
++#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
++#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
++#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
++#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
++#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
++#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
++#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
++#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
++#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
++#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
++#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
++#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
++
++
++// addressBlock: azf0endpoint1_endpointind
++// base address: 0x0
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
++#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
++#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
++#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
++#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
++#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
++#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
++#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
++#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
++#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
++#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
++#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
++#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
++#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
++#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
++
++
++// addressBlock: azf0endpoint2_endpointind
++// base address: 0x0
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
++#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
++#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
++#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
++#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
++#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
++#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
++#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
++#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
++#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
++#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
++#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
++#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
++#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
++#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
++
++
++// addressBlock: azf0endpoint3_endpointind
++// base address: 0x0
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
++#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
++#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
++#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
++#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
++#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
++#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
++#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
++#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
++#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
++#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
++#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
++#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
++#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
++#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
++
++
++// addressBlock: azf0endpoint4_endpointind
++// base address: 0x0
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
++#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
++#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
++#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
++#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
++#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
++#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
++#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
++#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
++#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
++#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
++#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
++#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
++#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
++#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
++
++
++// addressBlock: azf0endpoint5_endpointind
++// base address: 0x0
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
++#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
++#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
++#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
++#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
++#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
++#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
++#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
++#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
++#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
++#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
++#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
++#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
++#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
++#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
++
++
++// addressBlock: azf0endpoint6_endpointind
++// base address: 0x0
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
++#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
++#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
++#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
++#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
++#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
++#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
++#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
++#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
++#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
++#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
++#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
++#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
++#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
++#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
++
++
++// addressBlock: azf0endpoint7_endpointind
++// base address: 0x0
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
++#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
++#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
++#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
++#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
++#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
++#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
++#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
++#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
++#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
++#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
++#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
++#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
++#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
++#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
++
++
++// addressBlock: azf0inputendpoint0_inputendpointind
++// base address: 0x0
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
++#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
++
++
++// addressBlock: azf0inputendpoint1_inputendpointind
++// base address: 0x0
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
++#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
++
++
++// addressBlock: azf0inputendpoint2_inputendpointind
++// base address: 0x0
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
++#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
++
++
++// addressBlock: azf0inputendpoint3_inputendpointind
++// base address: 0x0
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
++#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
++
++
++// addressBlock: azf0inputendpoint4_inputendpointind
++// base address: 0x0
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
++#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
++
++
++// addressBlock: azf0inputendpoint5_inputendpointind
++// base address: 0x0
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
++#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
++
++
++// addressBlock: azf0inputendpoint6_inputendpointind
++// base address: 0x0
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
++#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
++
++
++// addressBlock: azf0inputendpoint7_inputendpointind
++// base address: 0x0
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
++#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
++
++
++#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h
+new file mode 100644
+index 000000000000..faa0e76e32b4
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h
+@@ -0,0 +1,56638 @@
++/*
++ * Copyright (C) 2019  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _dcn_2_1_0_SH_MASK_HEADER
++#define _dcn_2_1_0_SH_MASK_HEADER
++
++
++// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
++//VGA_MEM_WRITE_PAGE_ADDR
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT                                              0x0
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT                                              0x10
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK                                                0x000003FFL
++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK                                                0x03FF0000L
++//VGA_MEM_READ_PAGE_ADDR
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT                                                0x0
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT                                                0x10
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK                                                  0x000003FFL
++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK                                                  0x03FF0000L
++// addressBlock: dce_dc_mmhubbub_vga_dispdec
++//VGA_RENDER_CONTROL
++#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT                                                             0x0
++#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT                                                             0x5
++#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT                                                    0x7
++#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT                                                 0x8
++#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT                                                           0x10
++#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT                                                              0x18
++#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT                                           0x19
++#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK                                                               0x0000001FL
++#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK                                                               0x00000060L
++#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK                                                      0x00000080L
++#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK                                                   0x00000100L
++#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK                                                             0x00030000L
++#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK                                                                0x01000000L
++#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK                                             0x02000000L
++//VGA_SEQUENCER_RESET_CONTROL
++#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x0
++#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x1
++#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x2
++#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x3
++#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x4
++#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x5
++#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0x8
++#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0x9
++#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xa
++#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xb
++#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xc
++#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xd
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT                                      0x10
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT                             0x11
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT                                0x12
++#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000001L
++#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000002L
++#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000004L
++#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000008L
++#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000010L
++#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000020L
++#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000100L
++#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000200L
++#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000400L
++#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000800L
++#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00001000L
++#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00002000L
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK                                        0x00010000L
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK                               0x00020000L
++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK                                  0x00FC0000L
++//VGA_MODE_CONTROL
++#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT                                                               0x0
++#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT                                                  0x4
++#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT                                                     0x8
++#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT                                                      0x10
++#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT                                                    0x18
++#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK                                                                 0x00000001L
++#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK                                                    0x00000030L
++#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK                                                       0x00000100L
++#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK                                                        0x00010000L
++#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK                                                      0x01000000L
++//VGA_SURFACE_PITCH_SELECT
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT                                             0x0
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT                                            0x8
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK                                               0x00000003L
++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK                                              0x00000300L
++//VGA_MEMORY_BASE_ADDRESS
++#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT                                               0x0
++#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK                                                 0xFFFFFFFFL
++//VGA_DISPBUF1_SURFACE_ADDR
++#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT                                           0x0
++#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK                                             0x01FFFFFFL
++//VGA_DISPBUF2_SURFACE_ADDR
++#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT                                           0x0
++#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK                                             0x01FFFFFFL
++//VGA_MEMORY_BASE_ADDRESS_HIGH
++#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT                                     0x0
++#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK                                       0x0000FFFFL
++//VGA_HDP_CONTROL
++#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT                                                        0x0
++#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT                                                            0x4
++#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT                                                         0x8
++#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT                                                                0x10
++#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT                                                        0x18
++#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK                                                          0x00000001L
++#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK                                                              0x00000010L
++#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK                                                           0x00000100L
++#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK                                                                  0x00010000L
++#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK                                                          0x01000000L
++//VGA_CACHE_CONTROL
++#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT                                                 0x0
++#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT                                                      0x8
++#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT                                                  0x10
++#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT                                                          0x14
++#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT                                                        0x18
++#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK                                                   0x00000001L
++#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK                                                        0x00000100L
++#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK                                                    0x00010000L
++#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK                                                            0x00100000L
++#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK                                                          0x3F000000L
++//D1VGA_CONTROL
++#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT                                                               0x0
++#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT                                                             0x8
++#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
++#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
++#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT                                                                    0x18
++#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK                                                                 0x00000001L
++#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK                                                               0x00000100L
++#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
++#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
++#define D1VGA_CONTROL__D1VGA_ROTATE_MASK                                                                      0x03000000L
++//D2VGA_CONTROL
++#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT                                                               0x0
++#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT                                                             0x8
++#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
++#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
++#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT                                                                    0x18
++#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK                                                                 0x00000001L
++#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK                                                               0x00000100L
++#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
++#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
++#define D2VGA_CONTROL__D2VGA_ROTATE_MASK                                                                      0x03000000L
++//VGA_STATUS
++#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT                                                              0x0
++#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT                                                              0x1
++#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT                                                          0x2
++#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT                                                       0x3
++#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK                                                                0x00000001L
++#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK                                                                0x00000002L
++#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK                                                            0x00000004L
++#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK                                                         0x00000008L
++//VGA_INTERRUPT_CONTROL
++#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT                                                 0x0
++#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT                                                 0x8
++#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT                                             0x10
++#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT                                          0x18
++#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK                                                   0x00000001L
++#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK                                                   0x00000100L
++#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK                                               0x00010000L
++#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK                                            0x01000000L
++//VGA_STATUS_CLEAR
++#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT                                                     0x0
++#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT                                                     0x8
++#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT                                                 0x10
++#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT                                              0x18
++#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK                                                       0x00000001L
++#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK                                                       0x00000100L
++#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK                                                   0x00010000L
++#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK                                                0x01000000L
++//VGA_INTERRUPT_STATUS
++#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT                                                0x0
++#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT                                                0x1
++#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT                                            0x2
++#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT                                         0x3
++#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK                                                  0x00000001L
++#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK                                                  0x00000002L
++#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK                                              0x00000004L
++#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK                                           0x00000008L
++//VGA_MAIN_CONTROL
++#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT                                                             0x0
++#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT                                                     0x3
++#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT                                        0x5
++#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT                                       0x8
++#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT                                                0xc
++#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT                                        0x10
++#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT                                          0x18
++#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT                                             0x1a
++#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT                                                       0x1d
++#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT                                0x1f
++#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK                                                               0x00000003L
++#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK                                                       0x00000018L
++#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK                                          0x000000E0L
++#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK                                         0x00000300L
++#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK                                                  0x0000F000L
++#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK                                          0x00030000L
++#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK                                            0x03000000L
++#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK                                               0x04000000L
++#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK                                                         0x20000000L
++#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK                                  0x80000000L
++//VGA_TEST_CONTROL
++#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT                                                              0x0
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT                                                        0x8
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT                                                         0x10
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT                                               0x18
++#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK                                                                0x00000001L
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK                                                          0x00000100L
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK                                                           0x00010000L
++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK                                                 0x01000000L
++//VGA_QOS_CTRL
++#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT                                                                     0x0
++#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT                                                                    0x4
++#define VGA_QOS_CTRL__VGA_READ_QOS_MASK                                                                       0x0000000FL
++#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK                                                                      0x000000F0L
++//D3VGA_CONTROL
++#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT                                                               0x0
++#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT                                                             0x8
++#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
++#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
++#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT                                                                    0x18
++#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK                                                                 0x00000001L
++#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK                                                               0x00000100L
++#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
++#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
++#define D3VGA_CONTROL__D3VGA_ROTATE_MASK                                                                      0x03000000L
++//D4VGA_CONTROL
++#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT                                                               0x0
++#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT                                                             0x8
++#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
++#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
++#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT                                                                    0x18
++#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK                                                                 0x00000001L
++#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK                                                               0x00000100L
++#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
++#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
++#define D4VGA_CONTROL__D4VGA_ROTATE_MASK                                                                      0x03000000L
++//D5VGA_CONTROL
++#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT                                                               0x0
++#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT                                                             0x8
++#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
++#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
++#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT                                                                    0x18
++#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK                                                                 0x00000001L
++#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK                                                               0x00000100L
++#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
++#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
++#define D5VGA_CONTROL__D5VGA_ROTATE_MASK                                                                      0x03000000L
++//D6VGA_CONTROL
++#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT                                                               0x0
++#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT                                                             0x8
++#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
++#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
++#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT                                                                    0x18
++#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK                                                                 0x00000001L
++#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK                                                               0x00000100L
++#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
++#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
++#define D6VGA_CONTROL__D6VGA_ROTATE_MASK                                                                      0x03000000L
++//VGA_SOURCE_SELECT
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT                                                            0x0
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT                                                            0x8
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK                                                              0x00000007L
++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK                                                              0x00000700L
++
++
++// addressBlock: dce_dc_dccg_dccg_dispdec
++//PHYPLLA_PIXCLK_RESYNC_CNTL
++#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
++#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
++#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT                                              0x8
++#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
++#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
++#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
++#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK                                                0x00000100L
++#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
++//PHYPLLB_PIXCLK_RESYNC_CNTL
++#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
++#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
++#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT                                              0x8
++#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
++#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
++#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
++#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK                                                0x00000100L
++#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
++//PHYPLLC_PIXCLK_RESYNC_CNTL
++#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
++#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
++#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT                                              0x8
++#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
++#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
++#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
++#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK                                                0x00000100L
++#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
++//PHYPLLD_PIXCLK_RESYNC_CNTL
++#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
++#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
++#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT                                              0x8
++#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
++#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
++#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
++#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK                                                0x00000100L
++#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
++//DP_DTO_DBUF_EN
++#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT                                                                0x0
++#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT                                                                0x1
++#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT                                                                0x2
++#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT                                                                0x3
++#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT                                                                0x4
++#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT                                                                0x5
++#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT                                                                0x6
++#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT                                                                0x7
++#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK                                                                  0x00000001L
++#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK                                                                  0x00000002L
++#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK                                                                  0x00000004L
++#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK                                                                  0x00000008L
++#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK                                                                  0x00000010L
++#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK                                                                  0x00000020L
++#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK                                                                  0x00000040L
++#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK                                                                  0x00000080L
++//DPREFCLK_CGTT_BLK_CTRL_REG
++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT                                             0x0
++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT                                            0x4
++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK                                               0x0000000FL
++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK                                              0x00000FF0L
++//REFCLK_CNTL
++#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT                                                                   0x0
++#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT                                                                    0x1
++#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK                                                                     0x00000001L
++#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK                                                                      0x00000002L
++//REFCLK_CGTT_BLK_CTRL_REG
++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT                                                 0x0
++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT                                                0x4
++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
++//PHYPLLE_PIXCLK_RESYNC_CNTL
++#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
++#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
++#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT                                              0x8
++#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
++#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
++#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
++#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK                                                0x00000100L
++#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
++//DCCG_PERFMON_CNTL2
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT                                                    0x0
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT                                                    0x1
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT                                                   0x2
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT                                                   0x3
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT                                            0x4
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT                                            0x5
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT                                            0x6
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT                                            0x7
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT                                            0x8
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK                                                      0x00000001L
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK                                                      0x00000002L
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK                                                     0x00000004L
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK                                                     0x00000008L
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK                                              0x00000010L
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK                                              0x00000020L
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK                                              0x00000040L
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK                                              0x00000080L
++#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK                                              0x00000100L
++//DCCG_DS_DTO_INCR
++#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT                                                             0x0
++#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK                                                               0xFFFFFFFFL
++//DCCG_DS_DTO_MODULO
++#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT                                                         0x0
++#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK                                                           0xFFFFFFFFL
++//DCCG_DS_CNTL
++#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT                                                                   0x0
++#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT                                                                  0x4
++#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT                                                            0x8
++#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT                                                           0x9
++#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT                                                          0x10
++#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT                                                        0x18
++#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT                                                           0x19
++#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK                                                                     0x00000001L
++#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK                                                                    0x00000030L
++#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK                                                              0x00000100L
++#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK                                                             0x00000200L
++#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK                                                            0x00030000L
++#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK                                                          0x01000000L
++#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK                                                             0x02000000L
++//DCCG_DS_HW_CAL_INTERVAL
++#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT                                               0x0
++#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK                                                 0xFFFFFFFFL
++//DPREFCLK_CNTL
++#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT                                                                0x0
++#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK                                                                  0x00000007L
++//DCE_VERSION
++#define DCE_VERSION__MAJOR_VERSION__SHIFT                                                                     0x0
++#define DCE_VERSION__MINOR_VERSION__SHIFT                                                                     0x8
++#define DCE_VERSION__MAJOR_VERSION_MASK                                                                       0x000000FFL
++#define DCE_VERSION__MINOR_VERSION_MASK                                                                       0x0000FF00L
++//DCCG_GTC_CNTL
++#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT                                                                 0x0
++#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK                                                                   0x00000001L
++//DCCG_GTC_DTO_INCR
++#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT                                                           0x0
++#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK                                                             0xFFFFFFFFL
++//DCCG_GTC_DTO_MODULO
++#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT                                                       0x0
++#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK                                                         0xFFFFFFFFL
++//DCCG_GTC_CURRENT
++#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT                                                             0x0
++#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK                                                               0xFFFFFFFFL
++//DSCCLK0_DTO_PARAM
++#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT                                                           0x0
++#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT                                                          0x10
++#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK                                                             0x000000FFL
++#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK                                                            0x00FF0000L
++//DSCCLK1_DTO_PARAM
++#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT                                                           0x0
++#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT                                                          0x10
++#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK                                                             0x000000FFL
++#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK                                                            0x00FF0000L
++//DSCCLK2_DTO_PARAM
++#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT                                                           0x0
++#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT                                                          0x10
++#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK                                                             0x000000FFL
++#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK                                                            0x00FF0000L
++//MILLISECOND_TIME_BASE_DIV
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT                                           0x0
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK                                             0x0001FFFFL
++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L
++//DISPCLK_FREQ_CHANGE_CNTL
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT                                                   0x0
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT                                                    0x10
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT                                               0x14
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT                                            0x19
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT                                               0x1c
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT                                               0x1d
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT                                              0x1e
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT                                         0x1f
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK                                                     0x00003FFFL
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK                                                      0x000F0000L
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK                                                 0x00100000L
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK                                              0x0E000000L
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK                                                 0x10000000L
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK                                                 0x20000000L
++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK                                                0x40000000L
++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK                                           0x80000000L
++//DC_MEM_GLOBAL_PWR_REQ_CNTL
++#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT                                          0x0
++#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK                                            0x00000001L
++//DCCG_PERFMON_CNTL
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT                                                    0x0
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT                                                   0x1
++#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT                                             0x2
++#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT                                             0x3
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT                                                    0x4
++#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT                                                               0x5
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT                                                        0x6
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT                                                        0x7
++#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL__SHIFT                                                           0x8
++#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT                                                  0xb
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK                                                      0x00000001L
++#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK                                                     0x00000002L
++#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK                                               0x00000004L
++#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK                                               0x00000008L
++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK                                                      0x00000010L
++#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK                                                                 0x00000020L
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK                                                          0x00000040L
++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK                                                          0x00000080L
++#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL_MASK                                                             0x00000700L
++#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK                                                    0xFFFFF800L
++//DCCG_GATE_DISABLE_CNTL
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT                                              0x0
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT                                            0x1
++#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT                                                    0x2
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT                                                  0x3
++#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT                                                   0x4
++#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT                                                   0x6
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT                                           0x8
++#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT                                                    0x9
++#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT                                             0xa
++#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT                                                    0xb
++#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE__SHIFT                                                  0xc
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT                                                   0x11
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT                                                   0x12
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT                                                   0x13
++#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT                                            0x15
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT                                              0x16
++#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT                                                    0x1a
++#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT                                              0x1b
++#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT                                                    0x1c
++#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT                                                   0x1d
++#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT                                                    0x1e
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK                                                0x00000001L
++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK                                              0x00000002L
++#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK                                                      0x00000004L
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK                                                    0x00000008L
++#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK                                                     0x00000010L
++#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK                                                     0x00000040L
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK                                             0x00000100L
++#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK                                                      0x00000200L
++#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK                                               0x00000400L
++#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK                                                      0x00000800L
++#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE_MASK                                                    0x00001000L
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK                                                     0x00020000L
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK                                                     0x00040000L
++#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK                                                     0x00080000L
++#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK                                              0x00200000L
++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK                                                0x00400000L
++#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK                                                      0x04000000L
++#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK                                                0x08000000L
++#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK                                                      0x10000000L
++#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK                                                     0x20000000L
++#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK                                                      0x40000000L
++//DISPCLK_CGTT_BLK_CTRL_REG
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT                                               0x0
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT                                              0x4
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK                                                 0x0000000FL
++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK                                                0x00000FF0L
++//SOCCLK_CGTT_BLK_CTRL_REG
++#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT                                                 0x0
++#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT                                                0x4
++#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
++#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
++//DCCG_CAC_STATUS
++#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT                                                             0x0
++#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK                                                               0xFFFFFFFFL
++//MICROSECOND_TIME_BASE_DIV
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT                                           0x0
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT                                                        0x8
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT                                                        0x10
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT                                           0x11
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK                                             0x0000007FL
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK                                                          0x00007F00L
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK                                                          0x00010000L
++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK                                             0x00020000L
++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L
++//DCCG_GATE_DISABLE_CNTL2
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT                                               0x0
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT                                               0x1
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT                                               0x2
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT                                               0x3
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT                                               0x4
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT                                               0x5
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT                                               0x6
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT                                                  0x10
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT                                                  0x11
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT                                                  0x12
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT                                                  0x13
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT                                                  0x14
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT                                                  0x15
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT                                                  0x16
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK                                                 0x00000001L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK                                                 0x00000002L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK                                                 0x00000004L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK                                                 0x00000008L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK                                                 0x00000010L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK                                                 0x00000020L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK                                                 0x00000040L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK                                                    0x00010000L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK                                                    0x00020000L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK                                                    0x00040000L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK                                                    0x00080000L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK                                                    0x00100000L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK                                                    0x00200000L
++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK                                                    0x00400000L
++//SYMCLK_CGTT_BLK_CTRL_REG
++#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT                                                 0x0
++#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT                                                0x4
++#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
++#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
++//DCCG_DISP_CNTL_REG
++#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT                                                      0x8
++#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK                                                        0x00000100L
++//OTG0_PIXEL_RATE_CNTL
++#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
++#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT                                                           0x4
++#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT                                                       0x5
++#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT                                                           0x8
++#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT                                                          0x9
++#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
++#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT                                                      0xe
++#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT                                                     0x10
++#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
++#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK                                                             0x00000010L
++#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK                                                         0x00000020L
++#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK                                                             0x00000100L
++#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK                                                            0x00000200L
++#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
++#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
++#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
++//DP_DTO0_PHASE
++#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT                                                                   0x0
++#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK                                                                     0xFFFFFFFFL
++//DP_DTO0_MODULO
++#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT                                                                 0x0
++#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK                                                                   0xFFFFFFFFL
++//OTG0_PHYPLL_PIXEL_RATE_CNTL
++#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
++#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
++#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
++#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
++//OTG1_PIXEL_RATE_CNTL
++#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
++#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT                                                           0x4
++#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT                                                       0x5
++#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT                                                           0x8
++#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT                                                          0x9
++#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
++#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT                                                      0xe
++#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT                                                     0x10
++#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
++#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK                                                             0x00000010L
++#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK                                                         0x00000020L
++#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK                                                             0x00000100L
++#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK                                                            0x00000200L
++#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
++#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
++#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
++//DP_DTO1_PHASE
++#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT                                                                   0x0
++#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK                                                                     0xFFFFFFFFL
++//DP_DTO1_MODULO
++#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT                                                                 0x0
++#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK                                                                   0xFFFFFFFFL
++//OTG1_PHYPLL_PIXEL_RATE_CNTL
++#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
++#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
++#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
++#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
++//OTG2_PIXEL_RATE_CNTL
++#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
++#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT                                                           0x4
++#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT                                                       0x5
++#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT                                                           0x8
++#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT                                                          0x9
++#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
++#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT                                                      0xe
++#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT                                                     0x10
++#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
++#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK                                                             0x00000010L
++#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK                                                         0x00000020L
++#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK                                                             0x00000100L
++#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK                                                            0x00000200L
++#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
++#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
++#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
++//DP_DTO2_PHASE
++#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT                                                                   0x0
++#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK                                                                     0xFFFFFFFFL
++//DP_DTO2_MODULO
++#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT                                                                 0x0
++#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK                                                                   0xFFFFFFFFL
++//OTG2_PHYPLL_PIXEL_RATE_CNTL
++#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
++#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
++#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
++#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
++//OTG3_PIXEL_RATE_CNTL
++#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
++#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT                                                           0x4
++#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT                                                       0x5
++#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT                                                           0x8
++#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT                                                          0x9
++#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
++#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT                                                      0xe
++#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT                                                     0x10
++#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
++#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK                                                             0x00000010L
++#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK                                                         0x00000020L
++#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK                                                             0x00000100L
++#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK                                                            0x00000200L
++#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
++#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
++#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
++//DP_DTO3_PHASE
++#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT                                                                   0x0
++#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK                                                                     0xFFFFFFFFL
++//DP_DTO3_MODULO
++#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT                                                                 0x0
++#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK                                                                   0xFFFFFFFFL
++//OTG3_PHYPLL_PIXEL_RATE_CNTL
++#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
++#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
++#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
++#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
++//DPPCLK_CGTT_BLK_CTRL_REG
++#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT                                                 0x0
++#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT                                                0x4
++#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
++#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
++//DPPCLK0_DTO_PARAM
++#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT                                                           0x0
++#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT                                                          0x10
++#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK                                                             0x000000FFL
++#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK                                                            0x00FF0000L
++//DPPCLK1_DTO_PARAM
++#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT                                                           0x0
++#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT                                                          0x10
++#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK                                                             0x000000FFL
++#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK                                                            0x00FF0000L
++//DPPCLK2_DTO_PARAM
++#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT                                                           0x0
++#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT                                                          0x10
++#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK                                                             0x000000FFL
++#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK                                                            0x00FF0000L
++//DPPCLK3_DTO_PARAM
++#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT                                                           0x0
++#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT                                                          0x10
++#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK                                                             0x000000FFL
++#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK                                                            0x00FF0000L
++//DCCG_CAC_STATUS2
++#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT                                                           0x0
++#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK                                                             0x0000007FL
++//SYMCLKA_CLOCK_ENABLE
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT                                                     0x0
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT                                                      0x4
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT                                                     0x8
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK                                                       0x00000001L
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK                                                        0x00000010L
++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK                                                       0x00000700L
++//SYMCLKB_CLOCK_ENABLE
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT                                                     0x0
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT                                                      0x4
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT                                                     0x8
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK                                                       0x00000001L
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK                                                        0x00000010L
++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK                                                       0x00000700L
++//SYMCLKC_CLOCK_ENABLE
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT                                                     0x0
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT                                                      0x4
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT                                                     0x8
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK                                                       0x00000001L
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK                                                        0x00000010L
++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK                                                       0x00000700L
++//SYMCLKD_CLOCK_ENABLE
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT                                                     0x0
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT                                                      0x4
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT                                                     0x8
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK                                                       0x00000001L
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK                                                        0x00000010L
++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK                                                       0x00000700L
++//SYMCLKE_CLOCK_ENABLE
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT                                                     0x0
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT                                                      0x4
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT                                                     0x8
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK                                                       0x00000001L
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK                                                        0x00000010L
++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK                                                       0x00000700L
++//DCCG_SOFT_RESET
++#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT                                                             0x0
++#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT                                                        0x1
++#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT                                                                0x2
++#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT                                                                0x3
++#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT                                                     0x4
++#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT                                                           0x8
++#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT                                                             0xc
++#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT                                                             0xd
++#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xe
++#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xf
++#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x10
++#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x11
++#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x12
++#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x13
++#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x14
++#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x15
++#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK                                                               0x00000001L
++#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK                                                          0x00000002L
++#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK                                                                  0x00000004L
++#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK                                                                  0x00000008L
++#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK                                                       0x00000010L
++#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK                                                             0x00000100L
++#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK                                                               0x00001000L
++#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK                                                               0x00002000L
++#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00004000L
++#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00008000L
++#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00010000L
++#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00020000L
++#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00040000L
++#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00080000L
++#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00100000L
++#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00200000L
++//DSCCLK_DTO_CTRL
++#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE__SHIFT                                                            0x0
++#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE__SHIFT                                                            0x1
++#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE__SHIFT                                                            0x2
++#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE__SHIFT                                                            0x3
++#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE__SHIFT                                                            0x4
++#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE__SHIFT                                                            0x5
++#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_ENABLE__SHIFT                                                            0x6
++#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT                                                             0x8
++#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT                                                             0x9
++#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT                                                             0xa
++#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT                                                             0xb
++#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT                                                             0xc
++#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT                                                             0xd
++#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_DB_EN__SHIFT                                                             0xe
++#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE_MASK                                                              0x00000001L
++#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE_MASK                                                              0x00000002L
++#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE_MASK                                                              0x00000004L
++#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE_MASK                                                              0x00000008L
++#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE_MASK                                                              0x00000010L
++#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE_MASK                                                              0x00000020L
++#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_ENABLE_MASK                                                              0x00000040L
++#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK                                                               0x00000100L
++#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK                                                               0x00000200L
++#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK                                                               0x00000400L
++#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK                                                               0x00000800L
++#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK                                                               0x00001000L
++#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK                                                               0x00002000L
++#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_DB_EN_MASK                                                               0x00004000L
++//DCCG_AUDIO_DTO_SOURCE
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT                                              0x0
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT                                                      0x4
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT                                              0xc
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT                                                0x10
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT                                          0x14
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT                                          0x18
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT                                          0x1c
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK                                                0x00000007L
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK                                                        0x00000030L
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK                                                0x00003000L
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK                                                  0x00010000L
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK                                            0x00100000L
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK                                            0x01000000L
++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK                                            0x10000000L
++//DCCG_AUDIO_DTO0_PHASE
++#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT                                                   0x0
++#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK                                                     0xFFFFFFFFL
++//DCCG_AUDIO_DTO0_MODULE
++#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT                                                 0x0
++#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK                                                   0xFFFFFFFFL
++//DCCG_AUDIO_DTO1_PHASE
++#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT                                                   0x0
++#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK                                                     0xFFFFFFFFL
++//DCCG_AUDIO_DTO1_MODULE
++#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT                                                 0x0
++#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK                                                   0xFFFFFFFFL
++//DCCG_VSYNC_OTG0_LATCH_VALUE
++#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT                                   0x0
++#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK                                     0xFFFFFFFFL
++//DCCG_VSYNC_OTG1_LATCH_VALUE
++#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT                                   0x0
++#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK                                     0xFFFFFFFFL
++//DCCG_VSYNC_OTG2_LATCH_VALUE
++#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT                                   0x0
++#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK                                     0xFFFFFFFFL
++//DCCG_VSYNC_OTG3_LATCH_VALUE
++#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT                                   0x0
++#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK                                     0xFFFFFFFFL
++//DCCG_VSYNC_OTG4_LATCH_VALUE
++#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT                                   0x0
++#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK                                     0xFFFFFFFFL
++//DCCG_VSYNC_OTG5_LATCH_VALUE
++#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT                                   0x0
++#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK                                     0xFFFFFFFFL
++//DPPCLK_DTO_CTRL
++#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE__SHIFT                                                            0x0
++#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT                                                             0x1
++#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE__SHIFT                                                            0x4
++#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT                                                             0x5
++#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE__SHIFT                                                            0x8
++#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT                                                             0x9
++#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE__SHIFT                                                            0xc
++#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT                                                             0xd
++#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE__SHIFT                                                            0x10
++#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT                                                             0x11
++#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE__SHIFT                                                            0x14
++#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT                                                             0x15
++#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE_MASK                                                              0x00000001L
++#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK                                                               0x00000002L
++#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE_MASK                                                              0x00000010L
++#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK                                                               0x00000020L
++#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE_MASK                                                              0x00000100L
++#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK                                                               0x00000200L
++#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE_MASK                                                              0x00001000L
++#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK                                                               0x00002000L
++#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE_MASK                                                              0x00010000L
++#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK                                                               0x00020000L
++#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE_MASK                                                              0x00100000L
++#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK                                                               0x00200000L
++//DCCG_VSYNC_CNT_CTRL
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT                                                     0x0
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL__SHIFT                                                 0x1
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT                                                   0x2
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT                                                  0x3
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT                                               0x4
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT                                                  0x8
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT                                                  0x10
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT                                                  0x11
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT                                                  0x12
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT                                                  0x13
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT                                                  0x14
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT                                                  0x15
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT                                            0x18
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT                                            0x19
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT                                            0x1a
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT                                            0x1b
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT                                            0x1c
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT                                            0x1d
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK                                                       0x00000001L
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL_MASK                                                   0x00000002L
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK                                                     0x00000004L
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK                                                    0x00000008L
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK                                                 0x000000F0L
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK                                                    0x00000F00L
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK                                                    0x00010000L
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK                                                    0x00020000L
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK                                                    0x00040000L
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK                                                    0x00080000L
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK                                                    0x00100000L
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK                                                    0x00200000L
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK                                              0x01000000L
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK                                              0x02000000L
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK                                              0x04000000L
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK                                              0x08000000L
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK                                              0x10000000L
++#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK                                              0x20000000L
++//DCCG_VSYNC_CNT_INT_CTRL
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT                                   0x0
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT                             0x0
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT                                   0x1
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT                             0x1
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT                                   0x2
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT                             0x2
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT                                   0x3
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT                             0x3
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT                                   0x4
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT                             0x4
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT                                   0x5
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT                             0x5
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT                                        0x8
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT                                        0x9
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT                                        0xa
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT                                        0xb
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT                                        0xc
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT                                        0xd
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK                                     0x00000001L
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK                               0x00000001L
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK                                     0x00000002L
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK                               0x00000002L
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK                                     0x00000004L
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK                               0x00000004L
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK                                     0x00000008L
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK                               0x00000008L
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK                                     0x00000010L
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK                               0x00000010L
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK                                     0x00000020L
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK                               0x00000020L
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK                                          0x00000100L
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK                                          0x00000200L
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK                                          0x00000400L
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK                                          0x00000800L
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK                                          0x00001000L
++#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK                                          0x00002000L
++//FORCE_SYMCLK_DISABLE
++#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT                                                    0x0
++#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT                                                    0x1
++#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT                                                    0x2
++#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT                                                    0x3
++#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT                                                    0x4
++#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT                                                    0x5
++#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT                                                    0x6
++#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK                                                      0x00000001L
++#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK                                                      0x00000002L
++#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK                                                      0x00000004L
++#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK                                                      0x00000008L
++#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK                                                      0x00000010L
++#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK                                                      0x00000020L
++#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK                                                      0x00000040L
++//DCCG_TEST_CLK_SEL
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT                                                  0x0
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT                                                  0xc
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL__SHIFT                                              0xe
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT                                                  0x10
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT                                                  0x1c
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK                                                    0x000001FFL
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK                                                    0x00001000L
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL_MASK                                                0x0000C000L
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK                                                    0x01FF0000L
++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK                                                    0x10000000L
++
++
++// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
++//DENTIST_DISPCLK_CNTL
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT                                                 0x0
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT                                                 0x8
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT                                                 0xf
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT                                                   0x11
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT                                                  0x12
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT                                                 0x13
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT                                                  0x14
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT                                                    0x15
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT                                                   0x16
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT                                                  0x18
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK                                                   0x0000007FL
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK                                                   0x00007F00L
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK                                                   0x00018000L
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK                                                     0x00020000L
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK                                                    0x00040000L
++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK                                                   0x00080000L
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK                                                    0x00100000L
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK                                                      0x00200000L
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK                                                     0x00400000L
++#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK                                                    0x7F000000L
++
++
++// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
++//DC_PERFMON0_PERFCOUNTER_CNTL
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
++#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
++//DC_PERFMON0_PERFCOUNTER_CNTL2
++#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
++#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
++#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
++#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
++#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
++#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
++#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
++#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
++#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
++#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
++//DC_PERFMON0_PERFCOUNTER_STATE
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
++#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
++//DC_PERFMON0_PERFMON_CNTL
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
++#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
++//DC_PERFMON0_PERFMON_CNTL2
++#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
++#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
++#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
++#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
++#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
++#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
++#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
++#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
++//DC_PERFMON0_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
++#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
++//DC_PERFMON0_PERFMON_CVALUE_LOW
++#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
++#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
++//DC_PERFMON0_PERFMON_HI
++#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
++#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
++#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
++#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
++//DC_PERFMON0_PERFMON_LOW
++#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
++#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
++//DC_PERFMON1_PERFCOUNTER_CNTL
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
++#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
++//DC_PERFMON1_PERFCOUNTER_CNTL2
++#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
++#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
++#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
++#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
++#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
++#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
++#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
++#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
++#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
++#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
++//DC_PERFMON1_PERFCOUNTER_STATE
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
++#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
++//DC_PERFMON1_PERFMON_CNTL
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
++#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
++//DC_PERFMON1_PERFMON_CNTL2
++#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
++#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
++#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
++#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
++#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
++#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
++#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
++#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
++//DC_PERFMON1_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
++#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
++//DC_PERFMON1_PERFMON_CVALUE_LOW
++#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
++#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
++//DC_PERFMON1_PERFMON_HI
++#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
++#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
++#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
++#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
++//DC_PERFMON1_PERFMON_LOW
++#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
++#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dccg_dccg_pll_dispdec
++//PLL_MACRO_CNTL_RESERVED0
++#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
++#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED1
++#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
++#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED2
++#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
++#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED3
++#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
++#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED4
++#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
++#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED5
++#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
++#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED6
++#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
++#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED7
++#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
++#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED8
++#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
++#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED9
++#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
++#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED10
++#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED11
++#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED12
++#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED13
++#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED14
++#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED15
++#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED16
++#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED17
++#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED18
++#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED19
++#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED20
++#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED21
++#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED22
++#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED23
++#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED24
++#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED25
++#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED26
++#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED27
++#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED28
++#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED29
++#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED30
++#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED31
++#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED32
++#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED33
++#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED34
++#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED35
++#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED36
++#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED37
++#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED38
++#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED39
++#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED40
++#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++//PLL_MACRO_CNTL_RESERVED41
++#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
++#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dmu_rbbmif_dispdec
++//RBBMIF_TIMEOUT
++#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT                                                           0x0
++#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT                                                     0x14
++#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK                                                             0x000FFFFFL
++#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK                                                       0xFFF00000L
++//RBBMIF_STATUS
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT                                                      0x0
++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK                                                        0xFFFFFFFFL
++//RBBMIF_STATUS_2
++#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT                                                  0x0
++#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK                                                    0x0000003FL
++//RBBMIF_INT_STATUS
++#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT                                                         0x2
++#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT                                                           0x1c
++#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT                                                  0x1d
++#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT                                                          0x1e
++#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT                                                         0x1f
++#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK                                                           0x0003FFFCL
++#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK                                                             0x10000000L
++#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK                                                    0x20000000L
++#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK                                                            0x40000000L
++#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK                                                           0x80000000L
++//RBBMIF_TIMEOUT_DIS
++#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT                                                        0x0
++#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT                                                        0x1
++#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT                                                        0x2
++#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT                                                        0x3
++#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT                                                        0x4
++#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT                                                        0x5
++#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT                                                        0x6
++#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT                                                        0x7
++#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT                                                        0x8
++#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT                                                        0x9
++#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT                                                       0xa
++#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT                                                       0xb
++#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT                                                       0xc
++#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT                                                       0xd
++#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT                                                       0xe
++#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT                                                       0xf
++#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT                                                       0x10
++#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT                                                       0x11
++#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT                                                       0x12
++#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT                                                       0x13
++#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT                                                       0x14
++#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT                                                       0x15
++#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT                                                       0x16
++#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT                                                       0x17
++#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT                                                       0x18
++#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT                                                       0x19
++#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT                                                       0x1a
++#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT                                                       0x1b
++#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT                                                       0x1c
++#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT                                                       0x1d
++#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT                                                       0x1e
++#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT                                                       0x1f
++#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK                                                          0x00000001L
++#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK                                                          0x00000002L
++#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK                                                          0x00000004L
++#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK                                                          0x00000008L
++#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK                                                          0x00000010L
++#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK                                                          0x00000020L
++#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK                                                          0x00000040L
++#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK                                                          0x00000080L
++#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK                                                          0x00000100L
++#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK                                                          0x00000200L
++#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK                                                         0x00000400L
++#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK                                                         0x00000800L
++#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK                                                         0x00001000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK                                                         0x00002000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK                                                         0x00004000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK                                                         0x00008000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK                                                         0x00010000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK                                                         0x00020000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK                                                         0x00040000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK                                                         0x00080000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK                                                         0x00100000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK                                                         0x00200000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK                                                         0x00400000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK                                                         0x00800000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK                                                         0x01000000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK                                                         0x02000000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK                                                         0x04000000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK                                                         0x08000000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK                                                         0x10000000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK                                                         0x20000000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK                                                         0x40000000L
++#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK                                                         0x80000000L
++//RBBMIF_TIMEOUT_DIS_2
++#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT                                                     0x0
++#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT                                                     0x1
++#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT                                                     0x2
++#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT                                                     0x3
++#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT                                                     0x4
++#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT                                                     0x5
++#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK                                                       0x00000001L
++#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK                                                       0x00000002L
++#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK                                                       0x00000004L
++#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK                                                       0x00000008L
++#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK                                                       0x00000010L
++#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK                                                       0x00000020L
++//RBBMIF_STATUS_FLAG
++#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT                                                               0x0
++#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT                                                        0x4
++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT                                                          0x5
++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT                                                           0x6
++#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT                                                 0x8
++#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT                                                 0x9
++#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT                                                 0x10
++#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK                                                                 0x00000003L
++#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK                                                          0x00000010L
++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK                                                            0x00000020L
++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK                                                             0x00000040L
++#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK                                                   0x00000100L
++#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK                                                   0x00000E00L
++#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK                                                   0xFFFF0000L
++
++
++// addressBlock: dce_dc_dmu_dc_pg_dispdec
++//DOMAIN0_PG_CONFIG
++#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_FORCEON__SHIFT                                                       0x0
++#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_GATE__SHIFT                                                          0x8
++#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_FORCEON_MASK                                                         0x00000001L
++#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_GATE_MASK                                                            0x00000100L
++//DOMAIN0_PG_STATUS
++#define DOMAIN0_PG_STATUS__DOMAIN0_DESIRED_PWR_STATE__SHIFT                                                   0x1c
++#define DOMAIN0_PG_STATUS__DOMAIN0_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
++#define DOMAIN0_PG_STATUS__DOMAIN0_DESIRED_PWR_STATE_MASK                                                     0x10000000L
++#define DOMAIN0_PG_STATUS__DOMAIN0_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
++//DOMAIN1_PG_CONFIG
++#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_FORCEON__SHIFT                                                       0x0
++#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_GATE__SHIFT                                                          0x8
++#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_FORCEON_MASK                                                         0x00000001L
++#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_GATE_MASK                                                            0x00000100L
++//DOMAIN1_PG_STATUS
++#define DOMAIN1_PG_STATUS__DOMAIN1_DESIRED_PWR_STATE__SHIFT                                                   0x1c
++#define DOMAIN1_PG_STATUS__DOMAIN1_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
++#define DOMAIN1_PG_STATUS__DOMAIN1_DESIRED_PWR_STATE_MASK                                                     0x10000000L
++#define DOMAIN1_PG_STATUS__DOMAIN1_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
++//DOMAIN2_PG_CONFIG
++#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_FORCEON__SHIFT                                                       0x0
++#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_GATE__SHIFT                                                          0x8
++#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_FORCEON_MASK                                                         0x00000001L
++#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_GATE_MASK                                                            0x00000100L
++//DOMAIN2_PG_STATUS
++#define DOMAIN2_PG_STATUS__DOMAIN2_DESIRED_PWR_STATE__SHIFT                                                   0x1c
++#define DOMAIN2_PG_STATUS__DOMAIN2_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
++#define DOMAIN2_PG_STATUS__DOMAIN2_DESIRED_PWR_STATE_MASK                                                     0x10000000L
++#define DOMAIN2_PG_STATUS__DOMAIN2_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
++//DOMAIN3_PG_CONFIG
++#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_FORCEON__SHIFT                                                       0x0
++#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_GATE__SHIFT                                                          0x8
++#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_FORCEON_MASK                                                         0x00000001L
++#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_GATE_MASK                                                            0x00000100L
++//DOMAIN3_PG_STATUS
++#define DOMAIN3_PG_STATUS__DOMAIN3_DESIRED_PWR_STATE__SHIFT                                                   0x1c
++#define DOMAIN3_PG_STATUS__DOMAIN3_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
++#define DOMAIN3_PG_STATUS__DOMAIN3_DESIRED_PWR_STATE_MASK                                                     0x10000000L
++#define DOMAIN3_PG_STATUS__DOMAIN3_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
++//DOMAIN4_PG_CONFIG
++#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_FORCEON__SHIFT                                                       0x0
++#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_GATE__SHIFT                                                          0x8
++#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_FORCEON_MASK                                                         0x00000001L
++#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_GATE_MASK                                                            0x00000100L
++//DOMAIN4_PG_STATUS
++#define DOMAIN4_PG_STATUS__DOMAIN4_DESIRED_PWR_STATE__SHIFT                                                   0x1c
++#define DOMAIN4_PG_STATUS__DOMAIN4_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
++#define DOMAIN4_PG_STATUS__DOMAIN4_DESIRED_PWR_STATE_MASK                                                     0x10000000L
++#define DOMAIN4_PG_STATUS__DOMAIN4_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
++//DOMAIN5_PG_CONFIG
++#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_FORCEON__SHIFT                                                       0x0
++#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_GATE__SHIFT                                                          0x8
++#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_FORCEON_MASK                                                         0x00000001L
++#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_GATE_MASK                                                            0x00000100L
++//DOMAIN5_PG_STATUS
++#define DOMAIN5_PG_STATUS__DOMAIN5_DESIRED_PWR_STATE__SHIFT                                                   0x1c
++#define DOMAIN5_PG_STATUS__DOMAIN5_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
++#define DOMAIN5_PG_STATUS__DOMAIN5_DESIRED_PWR_STATE_MASK                                                     0x10000000L
++#define DOMAIN5_PG_STATUS__DOMAIN5_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
++//DOMAIN6_PG_CONFIG
++#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_FORCEON__SHIFT                                                       0x0
++#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_GATE__SHIFT                                                          0x8
++#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_FORCEON_MASK                                                         0x00000001L
++#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_GATE_MASK                                                            0x00000100L
++//DOMAIN6_PG_STATUS
++#define DOMAIN6_PG_STATUS__DOMAIN6_DESIRED_PWR_STATE__SHIFT                                                   0x1c
++#define DOMAIN6_PG_STATUS__DOMAIN6_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
++#define DOMAIN6_PG_STATUS__DOMAIN6_DESIRED_PWR_STATE_MASK                                                     0x10000000L
++#define DOMAIN6_PG_STATUS__DOMAIN6_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
++//DOMAIN7_PG_CONFIG
++#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_FORCEON__SHIFT                                                       0x0
++#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_GATE__SHIFT                                                          0x8
++#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_FORCEON_MASK                                                         0x00000001L
++#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_GATE_MASK                                                            0x00000100L
++//DOMAIN7_PG_STATUS
++#define DOMAIN7_PG_STATUS__DOMAIN7_DESIRED_PWR_STATE__SHIFT                                                   0x1c
++#define DOMAIN7_PG_STATUS__DOMAIN7_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
++#define DOMAIN7_PG_STATUS__DOMAIN7_DESIRED_PWR_STATE_MASK                                                     0x10000000L
++#define DOMAIN7_PG_STATUS__DOMAIN7_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
++//DOMAIN16_PG_CONFIG
++#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_FORCEON__SHIFT                                                     0x0
++#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_GATE__SHIFT                                                        0x8
++#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_FORCEON_MASK                                                       0x00000001L
++#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_GATE_MASK                                                          0x00000100L
++//DOMAIN16_PG_STATUS
++#define DOMAIN16_PG_STATUS__DOMAIN16_DESIRED_PWR_STATE__SHIFT                                                 0x1c
++#define DOMAIN16_PG_STATUS__DOMAIN16_PGFSM_PWR_STATUS__SHIFT                                                  0x1e
++#define DOMAIN16_PG_STATUS__DOMAIN16_DESIRED_PWR_STATE_MASK                                                   0x10000000L
++#define DOMAIN16_PG_STATUS__DOMAIN16_PGFSM_PWR_STATUS_MASK                                                    0xC0000000L
++//DOMAIN17_PG_CONFIG
++#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_FORCEON__SHIFT                                                     0x0
++#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_GATE__SHIFT                                                        0x8
++#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_FORCEON_MASK                                                       0x00000001L
++#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_GATE_MASK                                                          0x00000100L
++//DOMAIN17_PG_STATUS
++#define DOMAIN17_PG_STATUS__DOMAIN17_DESIRED_PWR_STATE__SHIFT                                                 0x1c
++#define DOMAIN17_PG_STATUS__DOMAIN17_PGFSM_PWR_STATUS__SHIFT                                                  0x1e
++#define DOMAIN17_PG_STATUS__DOMAIN17_DESIRED_PWR_STATE_MASK                                                   0x10000000L
++#define DOMAIN17_PG_STATUS__DOMAIN17_PGFSM_PWR_STATUS_MASK                                                    0xC0000000L
++//DOMAIN18_PG_CONFIG
++#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_FORCEON__SHIFT                                                     0x0
++#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_GATE__SHIFT                                                        0x8
++#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_FORCEON_MASK                                                       0x00000001L
++#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_GATE_MASK                                                          0x00000100L
++//DOMAIN18_PG_STATUS
++#define DOMAIN18_PG_STATUS__DOMAIN18_DESIRED_PWR_STATE__SHIFT                                                 0x1c
++#define DOMAIN18_PG_STATUS__DOMAIN18_PGFSM_PWR_STATUS__SHIFT                                                  0x1e
++#define DOMAIN18_PG_STATUS__DOMAIN18_DESIRED_PWR_STATE_MASK                                                   0x10000000L
++#define DOMAIN18_PG_STATUS__DOMAIN18_PGFSM_PWR_STATUS_MASK                                                    0xC0000000L
++//DCPG_INTERRUPT_STATUS
++#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT                                           0x0
++#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x1
++#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT                                           0x2
++#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x3
++#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT                                           0x4
++#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x5
++#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT                                           0x6
++#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x7
++#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT                                           0x8
++#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x9
++#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT                                           0xa
++#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT                                         0xb
++#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT                                           0xc
++#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT                                         0xd
++#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT                                           0xe
++#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT                                         0xf
++#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT                                           0x10
++#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x11
++#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT                                           0x12
++#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x13
++#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT                                          0x14
++#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT                                        0x15
++#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT                                          0x16
++#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT                                        0x17
++#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT                                          0x18
++#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT                                        0x19
++#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT                                          0x1a
++#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT                                        0x1b
++#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT                                          0x1c
++#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT                                        0x1d
++#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT                                          0x1e
++#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT                                        0x1f
++#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK                                             0x00000001L
++#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000002L
++#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK                                             0x00000004L
++#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000008L
++#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK                                             0x00000010L
++#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000020L
++#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK                                             0x00000040L
++#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000080L
++#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_UP_INT_OCCURRED_MASK                                             0x00000100L
++#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000200L
++#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_UP_INT_OCCURRED_MASK                                             0x00000400L
++#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000800L
++#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_UP_INT_OCCURRED_MASK                                             0x00001000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK                                           0x00002000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_UP_INT_OCCURRED_MASK                                             0x00004000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK                                           0x00008000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_UP_INT_OCCURRED_MASK                                             0x00010000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK                                           0x00020000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_UP_INT_OCCURRED_MASK                                             0x00040000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK                                           0x00080000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_UP_INT_OCCURRED_MASK                                            0x00100000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK                                          0x00200000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_UP_INT_OCCURRED_MASK                                            0x00400000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK                                          0x00800000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_UP_INT_OCCURRED_MASK                                            0x01000000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK                                          0x02000000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_UP_INT_OCCURRED_MASK                                            0x04000000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK                                          0x08000000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_UP_INT_OCCURRED_MASK                                            0x10000000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK                                          0x20000000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_UP_INT_OCCURRED_MASK                                            0x40000000L
++#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK                                          0x80000000L
++//DCPG_INTERRUPT_STATUS_2
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT                                        0x0
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x1
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT                                        0x2
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x3
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT                                        0x4
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x5
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT                                        0x6
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x7
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_UP_INT_OCCURRED__SHIFT                                        0x8
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x9
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_UP_INT_OCCURRED__SHIFT                                        0xa
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_DOWN_INT_OCCURRED__SHIFT                                      0xb
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK                                          0x00000001L
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000002L
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK                                          0x00000004L
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000008L
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK                                          0x00000010L
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000020L
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED_MASK                                          0x00000040L
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000080L
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_UP_INT_OCCURRED_MASK                                          0x00000100L
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000200L
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_UP_INT_OCCURRED_MASK                                          0x00000400L
++#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000800L
++//DCPG_INTERRUPT_CONTROL_1
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT                                            0x0
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT                                           0x1
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT                                          0x2
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT                                         0x3
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT                                            0x4
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT                                           0x5
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT                                          0x6
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT                                         0x7
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT                                            0x8
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT                                           0x9
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT                                          0xa
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT                                         0xb
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT                                            0xc
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT                                           0xd
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT                                          0xe
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT                                         0xf
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_MASK__SHIFT                                            0x10
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_CLEAR__SHIFT                                           0x11
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_MASK__SHIFT                                          0x12
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT                                         0x13
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_MASK__SHIFT                                            0x14
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_CLEAR__SHIFT                                           0x15
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_MASK__SHIFT                                          0x16
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT                                         0x17
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_MASK__SHIFT                                            0x18
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_CLEAR__SHIFT                                           0x19
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_MASK__SHIFT                                          0x1a
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT                                         0x1b
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_MASK__SHIFT                                            0x1c
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_CLEAR__SHIFT                                           0x1d
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_MASK__SHIFT                                          0x1e
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT                                         0x1f
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK                                              0x00000001L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK                                             0x00000002L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK                                            0x00000004L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK                                           0x00000008L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK                                              0x00000010L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK                                             0x00000020L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK                                            0x00000040L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK                                           0x00000080L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK                                              0x00000100L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK                                             0x00000200L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK                                            0x00000400L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK                                           0x00000800L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK                                              0x00001000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK                                             0x00002000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK                                            0x00004000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK                                           0x00008000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_MASK_MASK                                              0x00010000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_CLEAR_MASK                                             0x00020000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_MASK_MASK                                            0x00040000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_CLEAR_MASK                                           0x00080000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_MASK_MASK                                              0x00100000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_CLEAR_MASK                                             0x00200000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_MASK_MASK                                            0x00400000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_CLEAR_MASK                                           0x00800000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_MASK_MASK                                              0x01000000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_CLEAR_MASK                                             0x02000000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_MASK_MASK                                            0x04000000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_CLEAR_MASK                                           0x08000000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_MASK_MASK                                              0x10000000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_CLEAR_MASK                                             0x20000000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_MASK_MASK                                            0x40000000L
++#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_CLEAR_MASK                                           0x80000000L
++//DCPG_INTERRUPT_CONTROL_2
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_MASK__SHIFT                                            0x0
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_CLEAR__SHIFT                                           0x1
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_MASK__SHIFT                                          0x2
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT                                         0x3
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_MASK__SHIFT                                            0x4
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_CLEAR__SHIFT                                           0x5
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_MASK__SHIFT                                          0x6
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT                                         0x7
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_MASK__SHIFT                                           0x8
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_CLEAR__SHIFT                                          0x9
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_MASK__SHIFT                                         0xa
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT                                        0xb
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_MASK__SHIFT                                           0xc
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_CLEAR__SHIFT                                          0xd
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_MASK__SHIFT                                         0xe
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT                                        0xf
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_MASK__SHIFT                                           0x10
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_CLEAR__SHIFT                                          0x11
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_MASK__SHIFT                                         0x12
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT                                        0x13
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_MASK__SHIFT                                           0x14
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_CLEAR__SHIFT                                          0x15
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_MASK__SHIFT                                         0x16
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT                                        0x17
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_MASK__SHIFT                                           0x18
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_CLEAR__SHIFT                                          0x19
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_MASK__SHIFT                                         0x1a
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT                                        0x1b
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_MASK__SHIFT                                           0x1c
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_CLEAR__SHIFT                                          0x1d
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_MASK__SHIFT                                         0x1e
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT                                        0x1f
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_MASK_MASK                                              0x00000001L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_CLEAR_MASK                                             0x00000002L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_MASK_MASK                                            0x00000004L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_CLEAR_MASK                                           0x00000008L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_MASK_MASK                                              0x00000010L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_CLEAR_MASK                                             0x00000020L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_MASK_MASK                                            0x00000040L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_CLEAR_MASK                                           0x00000080L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_MASK_MASK                                             0x00000100L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_CLEAR_MASK                                            0x00000200L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_MASK_MASK                                           0x00000400L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_CLEAR_MASK                                          0x00000800L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_MASK_MASK                                             0x00001000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_CLEAR_MASK                                            0x00002000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_MASK_MASK                                           0x00004000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_CLEAR_MASK                                          0x00008000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_MASK_MASK                                             0x00010000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_CLEAR_MASK                                            0x00020000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_MASK_MASK                                           0x00040000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_CLEAR_MASK                                          0x00080000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_MASK_MASK                                             0x00100000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_CLEAR_MASK                                            0x00200000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_MASK_MASK                                           0x00400000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_CLEAR_MASK                                          0x00800000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_MASK_MASK                                             0x01000000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_CLEAR_MASK                                            0x02000000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_MASK_MASK                                           0x04000000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_CLEAR_MASK                                          0x08000000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_MASK_MASK                                             0x10000000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_CLEAR_MASK                                            0x20000000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_MASK_MASK                                           0x40000000L
++#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_CLEAR_MASK                                          0x80000000L
++//DCPG_INTERRUPT_CONTROL_3
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK__SHIFT                                           0x0
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT                                          0x1
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT                                         0x2
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT                                        0x3
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK__SHIFT                                           0x4
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT                                          0x5
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT                                         0x6
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT                                        0x7
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK__SHIFT                                           0x8
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT                                          0x9
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT                                         0xa
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT                                        0xb
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK__SHIFT                                           0xc
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR__SHIFT                                          0xd
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK__SHIFT                                         0xe
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT                                        0xf
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_MASK__SHIFT                                           0x10
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_CLEAR__SHIFT                                          0x11
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_MASK__SHIFT                                         0x12
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_CLEAR__SHIFT                                        0x13
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_MASK__SHIFT                                           0x14
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_CLEAR__SHIFT                                          0x15
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_MASK__SHIFT                                         0x16
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_CLEAR__SHIFT                                        0x17
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK_MASK                                             0x00000001L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR_MASK                                            0x00000002L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK_MASK                                           0x00000004L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK                                          0x00000008L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK_MASK                                             0x00000010L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR_MASK                                            0x00000020L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK_MASK                                           0x00000040L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK                                          0x00000080L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK_MASK                                             0x00000100L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR_MASK                                            0x00000200L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK_MASK                                           0x00000400L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK                                          0x00000800L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK_MASK                                             0x00001000L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR_MASK                                            0x00002000L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK_MASK                                           0x00004000L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR_MASK                                          0x00008000L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_MASK_MASK                                             0x00010000L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_CLEAR_MASK                                            0x00020000L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_MASK_MASK                                           0x00040000L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_CLEAR_MASK                                          0x00080000L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_MASK_MASK                                             0x00100000L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_CLEAR_MASK                                            0x00200000L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_MASK_MASK                                           0x00400000L
++#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_CLEAR_MASK                                          0x00800000L
++//DC_IP_REQUEST_CNTL
++#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT                                                              0x0
++#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK                                                                0x00000001L
++
++
++// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON2_PERFCOUNTER_CNTL
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
++#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
++//DC_PERFMON2_PERFCOUNTER_CNTL2
++#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
++#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
++#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
++#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
++#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
++#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
++#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
++#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
++#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
++#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
++//DC_PERFMON2_PERFCOUNTER_STATE
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
++#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
++//DC_PERFMON2_PERFMON_CNTL
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
++#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
++//DC_PERFMON2_PERFMON_CNTL2
++#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
++#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
++#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
++#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
++#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
++#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
++#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
++#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
++//DC_PERFMON2_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
++#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
++//DC_PERFMON2_PERFMON_CVALUE_LOW
++#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
++#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
++//DC_PERFMON2_PERFMON_HI
++#define DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
++#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
++#define DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
++#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
++//DC_PERFMON2_PERFMON_LOW
++#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
++#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dmu_dmu_misc_dispdec
++//CC_DC_PIPE_DIS
++#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT                                                                    0x0
++#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT                                                                0x10
++#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK                                                                      0x000000FFL
++#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK                                                                  0x00010000L
++//DMU_CLK_CNTL
++#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT                                                                 0x0
++#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT                                                           0x4
++#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT                                                          0x5
++#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT                                                        0x6
++#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT                                                               0x8
++#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON__SHIFT                                                          0x9
++#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT                                                        0xa
++#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK                                                                   0x0000000FL
++#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK                                                             0x00000010L
++#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK                                                            0x00000020L
++#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK                                                          0x00000040L
++#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK                                                                 0x00000100L
++#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON_MASK                                                            0x00000200L
++#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK                                                          0x00000400L
++//DMU_MEM_PWR_CNTL
++#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT                                                   0x0
++#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT                                                      0x1
++#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT                                                        0x3
++#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE__SHIFT                                                      0x4
++#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT                                                      0x8
++#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT                                                        0x9
++#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT                                                      0xa
++#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK                                                     0x00000001L
++#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK                                                        0x00000006L
++#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK                                                          0x00000008L
++#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK                                                        0x00000030L
++#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK                                                        0x00000100L
++#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK                                                          0x00000200L
++#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK                                                        0x00000400L
++//DMCU_SMU_INTERRUPT_CNTL
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT                                            0x0
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT                                         0x10
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK                                              0x00000001L
++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK                                           0xFFFF0000L
++//SMU_INTERRUPT_CONTROL
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT                                                       0x0
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT                                                       0x4
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT                                                        0x10
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK                                                         0x00000001L
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK                                                         0x00000010L
++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK                                                          0xFFFF0000L
++//DMU_MISC_ALLOW_DS_FORCE
++#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT                                            0x0
++#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT                                         0x4
++#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK                                              0x00000001L
++#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK                                           0x00000010L
++
++
++// addressBlock: dce_dc_dmu_dmcu_dispdec
++//DMCU_CTRL
++#define DMCU_CTRL__RESET_UC__SHIFT                                                                            0x0
++#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT                                                                       0x1
++#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT                                                                   0x2
++#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT                                                                  0x3
++#define DMCU_CTRL__DMCU_ENABLE__SHIFT                                                                         0x4
++#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT                                                              0x8
++#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT                                                                   0x10
++#define DMCU_CTRL__RESET_UC_MASK                                                                              0x00000001L
++#define DMCU_CTRL__IGNORE_PWRMGT_MASK                                                                         0x00000002L
++#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK                                                                     0x00000004L
++#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK                                                                    0x00000008L
++#define DMCU_CTRL__DMCU_ENABLE_MASK                                                                           0x00000010L
++#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK                                                                0x00000100L
++#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK                                                                     0xFFFF0000L
++//DMCU_STATUS
++#define DMCU_STATUS__UC_IN_RESET__SHIFT                                                                       0x0
++#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT                                                                   0x1
++#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT                                                                   0x2
++#define DMCU_STATUS__UC_IN_RESET_MASK                                                                         0x00000001L
++#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK                                                                     0x00000002L
++#define DMCU_STATUS__UC_IN_STOP_MODE_MASK                                                                     0x00000004L
++//DMCU_PC_START_ADDR
++#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT                                                          0x0
++#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT                                                          0x8
++#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK                                                            0x000000FFL
++#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK                                                            0x0000FF00L
++//DMCU_FW_START_ADDR
++#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT                                                          0x0
++#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT                                                          0x8
++#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK                                                            0x000000FFL
++#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK                                                            0x0000FF00L
++//DMCU_FW_END_ADDR
++#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT                                                              0x0
++#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT                                                              0x8
++#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK                                                                0x000000FFL
++#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK                                                                0x0000FF00L
++//DMCU_FW_ISR_START_ADDR
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT                                                  0x0
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT                                                  0x8
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK                                                    0x000000FFL
++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK                                                    0x0000FF00L
++//DMCU_FW_CS_HI
++#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT                                                                  0x0
++#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK                                                                    0xFFFFFFFFL
++//DMCU_FW_CS_LO
++#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT                                                                  0x0
++#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK                                                                    0xFFFFFFFFL
++//DMCU_RAM_ACCESS_CTRL
++#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT                                                    0x0
++#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT                                                    0x1
++#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT                                                    0x2
++#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT                                                    0x3
++#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT                                                      0x4
++#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT                                                      0x5
++#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK                                                      0x00000001L
++#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK                                                      0x00000002L
++#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK                                                      0x00000004L
++#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK                                                      0x00000008L
++#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK                                                        0x00000010L
++#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK                                                        0x00000020L
++//DMCU_ERAM_WR_CTRL
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT                                                                0x0
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT                                                                  0x10
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT                                                           0x14
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK                                                                  0x0000FFFFL
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK                                                                    0x000F0000L
++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK                                                             0x00100000L
++//DMCU_ERAM_WR_DATA
++#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT                                                                0x0
++#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK                                                                  0xFFFFFFFFL
++//DMCU_ERAM_RD_CTRL
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT                                                                0x0
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT                                                                  0x10
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT                                                           0x14
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK                                                                  0x0000FFFFL
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK                                                                    0x000F0000L
++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK                                                             0x00100000L
++//DMCU_ERAM_RD_DATA
++#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT                                                                0x0
++#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK                                                                  0xFFFFFFFFL
++//DMCU_IRAM_WR_CTRL
++#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT                                                                0x0
++#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK                                                                  0x000003FFL
++//DMCU_IRAM_WR_DATA
++#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT                                                                0x0
++#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK                                                                  0x000000FFL
++//DMCU_IRAM_RD_CTRL
++#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT                                                                0x0
++#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK                                                                  0x000003FFL
++//DMCU_IRAM_RD_DATA
++#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT                                                                0x0
++#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK                                                                  0x000000FFL
++//DMCU_EVENT_TRIGGER
++#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT                                                           0x0
++#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT                                                       0x10
++#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT                                                0x17
++#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK                                                             0x00000001L
++#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK                                                         0x007F0000L
++#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK                                                  0x00800000L
++//DMCU_UC_INTERNAL_INT_STATUS
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT                                                  0x0
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT                                                 0x1
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT                                         0x2
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT                                        0x3
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT                                     0x4
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT                                     0x5
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT                                     0x6
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT                                     0x7
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT                                             0x8
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT                                        0x9
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT                     0xa
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT                                      0xb
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT                                      0xc
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT                                      0xd
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT                               0xe
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT                                 0xf
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK                                                    0x00000001L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK                                                   0x00000002L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK                                           0x00000004L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK                                          0x00000008L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK                                       0x00000010L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK                                       0x00000020L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK                                       0x00000040L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK                                       0x00000080L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK                                               0x00000100L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK                                          0x00000200L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK                       0x00000400L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK                                        0x00000800L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK                                        0x00001000L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK                                        0x00002000L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK                                 0x00004000L
++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK                                   0x00008000L
++//DMCU_SS_INTERRUPT_CNTL_STATUS
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT                                       0xd
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT                                     0xe
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT                                        0xe
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT                                       0xf
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT                                     0x10
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT                                        0x10
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT                                       0x11
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT                                     0x12
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT                                        0x12
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT                                       0x13
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT                                     0x14
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT                                        0x14
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT                                       0x15
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT                                     0x16
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT                                        0x16
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT                                       0x17
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT                                     0x18
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT                                        0x18
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK                                         0x00002000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK                                       0x00004000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK                                          0x00004000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK                                         0x00008000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK                                       0x00010000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK                                          0x00010000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK                                         0x00020000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK                                       0x00040000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK                                          0x00040000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK                                         0x00080000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK                                       0x00100000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK                                          0x00100000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK                                         0x00200000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK                                       0x00400000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK                                          0x00400000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK                                         0x00800000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK                                       0x01000000L
++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK                                          0x01000000L
++//DMCU_INTERRUPT_STATUS
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT                                              0x0
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT                                                 0x0
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT                                              0x1
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT                                                 0x1
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT                                             0x2
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT                                                0x2
++#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT                                                        0x3
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT                                                0x8
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT                                                   0x8
++#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT                                                        0x9
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT                                                0xa
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT                                                   0xa
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT                                          0xb
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT                                             0xb
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT                                  0xc
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR__SHIFT                                     0xc
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT                                  0xd
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR__SHIFT                                     0xd
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT                                  0xe
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR__SHIFT                                     0xe
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT                                  0xf
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR__SHIFT                                     0xf
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT                                  0x10
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR__SHIFT                                     0x10
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT                                  0x11
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR__SHIFT                                     0x11
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT                                0x12
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT                                   0x12
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT                                0x13
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT                                   0x13
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT                                0x14
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT                                   0x14
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT                                0x15
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT                                   0x15
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT                                0x16
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT                                   0x16
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT                                0x17
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT                                   0x17
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT                                                    0x18
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT                                                       0x18
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT                                                    0x19
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT                                                       0x19
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT                                                    0x1a
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT                                                       0x1a
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT                                                    0x1b
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT                                                       0x1b
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT                                                    0x1c
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT                                                       0x1c
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT                                                    0x1d
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT                                                       0x1d
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK                                                0x00000001L
++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK                                                   0x00000001L
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK                                                0x00000002L
++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK                                                   0x00000002L
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK                                               0x00000004L
++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK                                                  0x00000004L
++#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK                                                          0x00000008L
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK                                                  0x00000100L
++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK                                                     0x00000100L
++#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK                                                          0x00000200L
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK                                                  0x00000400L
++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK                                                     0x00000400L
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK                                            0x00000800L
++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK                                               0x00000800L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED_MASK                                    0x00001000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR_MASK                                       0x00001000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED_MASK                                    0x00002000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR_MASK                                       0x00002000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED_MASK                                    0x00004000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR_MASK                                       0x00004000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED_MASK                                    0x00008000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR_MASK                                       0x00008000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED_MASK                                    0x00010000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR_MASK                                       0x00010000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED_MASK                                    0x00020000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR_MASK                                       0x00020000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK                                  0x00040000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR_MASK                                     0x00040000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK                                  0x00080000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR_MASK                                     0x00080000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK                                  0x00100000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR_MASK                                     0x00100000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK                                  0x00200000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR_MASK                                     0x00200000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK                                  0x00400000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR_MASK                                     0x00400000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK                                  0x00800000L
++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR_MASK                                     0x00800000L
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK                                                      0x01000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK                                                         0x01000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK                                                      0x02000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK                                                         0x02000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK                                                      0x04000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK                                                         0x04000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK                                                      0x08000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK                                                         0x08000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK                                                      0x10000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK                                                         0x10000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK                                                      0x20000000L
++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK                                                         0x20000000L
++//DMCU_INTERRUPT_STATUS_1
++#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x6
++#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x6
++#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x7
++#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x7
++#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x8
++#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x8
++#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x9
++#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x9
++#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0xa
++#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0xa
++#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0xb
++#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0xb
++#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT                                       0xd
++#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT                                          0xd
++#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000040L
++#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000040L
++#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000080L
++#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000080L
++#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000100L
++#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000100L
++#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000200L
++#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000200L
++#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000400L
++#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000400L
++#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000800L
++#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000800L
++#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK                                         0x00002000L
++#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK                                            0x00002000L
++//DMCU_INTERRUPT_TO_HOST_EN_MASK
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK__SHIFT                                         0x0
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK__SHIFT                                         0x1
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK__SHIFT                                        0x2
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT                                         0x3
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT                                         0x4
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT                                        0x5
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT                                                   0x9
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT                                           0xa
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT                                     0xb
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK_MASK                                           0x00000001L
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK_MASK                                           0x00000002L
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK_MASK                                          0x00000004L
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK                                           0x00000008L
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK                                           0x00000010L
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK                                          0x00000020L
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK                                                     0x00000200L
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK                                             0x00000400L
++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK                                       0x00000800L
++//DMCU_INTERRUPT_TO_UC_EN_MASK
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT                                       0x0
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT                                       0x1
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT                                      0x2
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT                                                 0x3
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT                                      0x6
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT                                      0x7
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT                                         0x8
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT                                      0x9
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT                                      0xa
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT                                      0xb
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN__SHIFT                           0xc
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN__SHIFT                           0xd
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN__SHIFT                           0xe
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN__SHIFT                           0xf
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN__SHIFT                           0x10
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN__SHIFT                           0x11
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x12
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x13
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x14
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x15
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x16
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x17
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT                                             0x18
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT                                             0x19
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT                                             0x1a
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT                                             0x1b
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT                                             0x1c
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT                                             0x1d
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT                                      0x1e
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK                                         0x00000001L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK                                         0x00000002L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK                                        0x00000004L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK                                                   0x00000008L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK                                        0x00000040L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK                                        0x00000080L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK                                           0x00000100L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK                                        0x00000200L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK                                        0x00000400L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK                                        0x00000800L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN_MASK                             0x00001000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN_MASK                             0x00002000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN_MASK                             0x00004000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN_MASK                             0x00008000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN_MASK                             0x00010000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN_MASK                             0x00020000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00040000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00080000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00100000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00200000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00400000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00800000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK                                               0x01000000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK                                               0x02000000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK                                               0x04000000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK                                               0x08000000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK                                               0x10000000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK                                               0x20000000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK                                        0x40000000L
++//DMCU_INTERRUPT_TO_UC_EN_MASK_1
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x6
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x7
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x8
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x9
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0xa
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0xb
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT                                      0xd
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000040L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000080L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000100L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000200L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000400L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000800L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK                                        0x00002000L
++//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT                              0x0
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT                              0x1
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                             0x2
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT                                        0x3
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT                             0x6
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT                             0x7
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT                                0x8
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT                             0x9
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT                             0xa
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT                             0xb
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xc
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xd
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xe
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xf
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0x10
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0x11
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x12
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x13
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x14
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x15
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x16
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x17
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT                                    0x18
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT                                    0x19
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1a
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1b
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1c
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1d
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT                             0x1e
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK                                0x00000001L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK                                0x00000002L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK                               0x00000004L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK                                          0x00000008L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK                               0x00000040L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK                               0x00000080L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK                                  0x00000100L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK                               0x00000200L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK                               0x00000400L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK                               0x00000800L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00001000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00002000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00004000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00008000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00010000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00020000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00040000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00080000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00100000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00200000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00400000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00800000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK                                      0x01000000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK                                      0x02000000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK                                      0x04000000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK                                      0x08000000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK                                      0x10000000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK                                      0x20000000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK                               0x40000000L
++//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x6
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x7
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x8
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x9
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0xa
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0xb
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT                             0xd
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000040L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000080L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000100L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000200L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000400L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000800L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK                               0x00002000L
++//DC_DMCU_SCRATCH
++#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT                                                                  0x0
++#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK                                                                    0xFFFFFFFFL
++//DMCU_INT_CNT
++#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT                                                       0x0
++#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT                                                       0x8
++#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT                                                      0x10
++#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK                                                         0x000000FFL
++#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK                                                         0x0000FF00L
++#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK                                                        0x00FF0000L
++//DMCU_FW_CHECKSUM_SMPL_BYTE_POS
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT                              0x0
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT                              0x2
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK                                0x00000003L
++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK                                0x0000000CL
++//DMCU_UC_CLK_GATING_CNTL
++#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT                                                      0x0
++#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT                                                      0x8
++#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT                                              0x10
++#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK                                                        0x00000007L
++#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK                                                        0x00000700L
++#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK                                                0x00010000L
++//MASTER_COMM_DATA_REG1
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT                                             0x0
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT                                             0x8
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT                                             0x10
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT                                             0x18
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK                                               0x000000FFL
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK                                               0x0000FF00L
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK                                               0x00FF0000L
++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK                                               0xFF000000L
++//MASTER_COMM_DATA_REG2
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT                                             0x0
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT                                             0x8
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT                                             0x10
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT                                             0x18
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK                                               0x000000FFL
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK                                               0x0000FF00L
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK                                               0x00FF0000L
++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK                                               0xFF000000L
++//MASTER_COMM_DATA_REG3
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT                                             0x0
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT                                             0x8
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT                                             0x10
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT                                             0x18
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK                                               0x000000FFL
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK                                               0x0000FF00L
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK                                               0x00FF0000L
++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK                                               0xFF000000L
++//MASTER_COMM_CMD_REG
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT                                                 0x0
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT                                                 0x8
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT                                                 0x10
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT                                                 0x18
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK                                                   0x000000FFL
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK                                                   0x0000FF00L
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK                                                   0x00FF0000L
++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK                                                   0xFF000000L
++//MASTER_COMM_CNTL_REG
++#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT                                                    0x0
++#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK                                                      0x00000001L
++//SLAVE_COMM_DATA_REG1
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT                                               0x0
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT                                               0x8
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT                                               0x10
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT                                               0x18
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK                                                 0x000000FFL
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK                                                 0x0000FF00L
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK                                                 0x00FF0000L
++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK                                                 0xFF000000L
++//SLAVE_COMM_DATA_REG2
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT                                               0x0
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT                                               0x8
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT                                               0x10
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT                                               0x18
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK                                                 0x000000FFL
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK                                                 0x0000FF00L
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK                                                 0x00FF0000L
++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK                                                 0xFF000000L
++//SLAVE_COMM_DATA_REG3
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT                                               0x0
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT                                               0x8
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT                                               0x10
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT                                               0x18
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK                                                 0x000000FFL
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK                                                 0x0000FF00L
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK                                                 0x00FF0000L
++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK                                                 0xFF000000L
++//SLAVE_COMM_CMD_REG
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT                                                   0x0
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT                                                   0x8
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT                                                   0x10
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT                                                   0x18
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK                                                     0x000000FFL
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK                                                     0x0000FF00L
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK                                                     0x00FF0000L
++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK                                                     0xFF000000L
++//SLAVE_COMM_CNTL_REG
++#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT                                                      0x0
++#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT                                         0x8
++#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK                                                        0x00000001L
++#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK                                           0x00000100L
++//DMCU_PERFMON_INTERRUPT_STATUS1
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000004L
++//DMCU_PERFMON_INTERRUPT_STATUS2
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT                            0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT                               0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000008L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000008L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000010L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000010L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000020L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000020L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000040L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000040L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000080L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000080L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK                              0x00000100L
++#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK                                 0x00000100L
++//DMCU_PERFMON_INTERRUPT_STATUS3
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000008L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000008L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000010L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000010L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000020L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000020L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000040L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000040L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000080L
++#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000080L
++//DMCU_PERFMON_INTERRUPT_STATUS4
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED__SHIFT                             0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR__SHIFT                                0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT                          0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT                             0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED_MASK                               0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR_MASK                                  0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK                            0x00000008L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK                               0x00000008L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000010L
++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000010L
++//DMCU_PERFMON_INTERRUPT_STATUS5
++#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x0
++#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x1
++#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x2
++#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x3
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x4
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x5
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x6
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x7
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x8
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x9
++#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000001L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000002L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000004L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000008L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000010L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000010L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000020L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000020L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000040L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000040L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000080L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000080L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000100L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000100L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000200L
++#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000200L
++//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000004L
++//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                     0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000004L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000008L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000010L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000020L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000040L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000080L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK                       0x00000100L
++//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000004L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000008L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000010L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000020L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000040L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000080L
++//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN__SHIFT                      0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                   0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN_MASK                        0x00000004L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK                     0x00000008L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000010L
++//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000004L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000008L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000010L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000020L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000040L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000080L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000100L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000200L
++//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000004L
++//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT            0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000004L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000008L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000010L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000020L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000040L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000080L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK              0x00000100L
++//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000004L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000008L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000010L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000020L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000040L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000080L
++//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT          0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000004L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK            0x00000008L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000010L
++//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x0
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x1
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x2
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x3
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x4
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x5
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x6
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x7
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x8
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x9
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000001L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000002L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000004L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000008L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000010L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000020L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000040L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000080L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000100L
++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000200L
++//DMCU_DPRX_INTERRUPT_STATUS1
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT                              0x0
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT                                 0x0
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT            0x1
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT               0x1
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT                                 0x2
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT                                    0x2
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT                                 0x3
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT                                    0x3
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT                              0x4
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT                                 0x4
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT                              0x5
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT                                 0x5
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT            0x6
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT               0x6
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT                                 0x7
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT                                    0x7
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT                                 0x8
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT                                    0x8
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT                              0x9
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT                                 0x9
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT       0xa
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT          0xa
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT       0xb
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT          0xb
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT            0xc
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT               0xc
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT         0xd
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT            0xd
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT          0xe
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT             0xe
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT      0xf
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT         0xf
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT               0x10
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT                  0x10
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT                          0x11
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT                             0x11
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT                           0x12
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT                              0x12
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT                          0x13
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT                             0x13
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT                         0x14
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT                            0x14
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT                    0x15
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT                       0x15
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT                                      0x16
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT                                         0x16
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT                                      0x17
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT                                         0x17
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT                                      0x18
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT                                         0x18
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT                             0x19
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT                                0x19
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT                             0x1a
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT                                0x1a
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT                             0x1b
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT                                0x1b
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT                             0x1c
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT                                0x1c
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK                                0x00000001L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK                                   0x00000001L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK              0x00000002L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK                 0x00000002L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK                                   0x00000004L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK                                      0x00000004L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK                                   0x00000008L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK                                      0x00000008L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK                                0x00000010L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK                                   0x00000010L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK                                0x00000020L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK                                   0x00000020L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK              0x00000040L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK                 0x00000040L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK                                   0x00000080L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK                                      0x00000080L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK                                   0x00000100L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK                                      0x00000100L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK                                0x00000200L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK                                   0x00000200L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK         0x00000400L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK            0x00000400L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK         0x00000800L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK            0x00000800L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK              0x00001000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK                 0x00001000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK           0x00002000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK              0x00002000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK            0x00004000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK               0x00004000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK        0x00008000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK           0x00008000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK                 0x00010000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK                    0x00010000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK                            0x00020000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK                               0x00020000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK                             0x00040000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK                                0x00040000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK                            0x00080000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK                               0x00080000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK                           0x00100000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK                              0x00100000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK                      0x00200000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK                         0x00200000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK                                        0x00400000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK                                           0x00400000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK                                        0x00800000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK                                           0x00800000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK                                        0x01000000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK                                           0x01000000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK                               0x02000000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK                                  0x02000000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK                               0x04000000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK                                  0x04000000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK                               0x08000000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK                                  0x08000000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK                               0x10000000L
++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK                                  0x10000000L
++//DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT                       0x0
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT     0x1
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT                          0x2
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT                          0x3
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT                       0x4
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT                       0x5
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT     0x6
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT                          0x7
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT                          0x8
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT                       0x9
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xa
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xb
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT     0xc
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xd
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT   0xe
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xf
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT        0x10
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT                   0x11
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT                    0x12
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT                   0x13
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT                  0x14
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT             0x15
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT                               0x16
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT                               0x17
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT                               0x18
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x19
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x1a
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x1b
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x1c
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK                         0x00000001L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK       0x00000002L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK                            0x00000004L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK                            0x00000008L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK                         0x00000010L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK                         0x00000020L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK       0x00000040L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK                            0x00000080L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK                            0x00000100L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK                         0x00000200L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK  0x00000400L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK  0x00000800L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK       0x00001000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK    0x00002000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK     0x00004000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK  0x00008000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK          0x00010000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK                     0x00020000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK                      0x00040000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK                     0x00080000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK                    0x00100000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK               0x00200000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK                                 0x00400000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK                                 0x00800000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK                                 0x01000000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK                        0x02000000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK                        0x04000000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK                        0x08000000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK                        0x10000000L
++//DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x0
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT  0x1
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT                 0x2
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT                 0x3
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x4
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x5
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT  0x6
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT                 0x7
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT                 0x8
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x9
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xa
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xb
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xc
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xd
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xe
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xf
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0x10
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT          0x11
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT           0x12
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT          0x13
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT         0x14
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT    0x15
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT                      0x16
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT                      0x17
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT                      0x18
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x19
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x1a
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x1b
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x1c
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000001L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK  0x00000002L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK                   0x00000004L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK                   0x00000008L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000010L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000020L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK  0x00000040L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK                   0x00000080L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK                   0x00000100L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000200L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00000400L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00000800L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00001000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00002000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00004000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00008000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00010000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK            0x00020000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK             0x00040000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK            0x00080000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK           0x00100000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK      0x00200000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK                        0x00400000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK                        0x00800000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK                        0x01000000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x02000000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x04000000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x08000000L
++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x10000000L
++//DMCU_INTERRUPT_STATUS_CONTINUE
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT                         0x0
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR__SHIFT                            0x0
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT                         0x1
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR__SHIFT                            0x1
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT                         0x2
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR__SHIFT                            0x2
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT                         0x3
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR__SHIFT                            0x3
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT                        0x4
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR__SHIFT                           0x4
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT                        0x5
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR__SHIFT                           0x5
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT                        0x6
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR__SHIFT                           0x6
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT                        0x7
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR__SHIFT                           0x7
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT                        0x8
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR__SHIFT                           0x8
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT                        0x9
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR__SHIFT                           0x9
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT                       0xa
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT                          0xa
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT                       0xb
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT                          0xb
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT                       0xc
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT                          0xc
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT                       0xd
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT                          0xd
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT                      0xe
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT                         0xe
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT                      0xf
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT                         0xf
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT                      0x10
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT                         0x10
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT                      0x11
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT                         0x11
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT                      0x12
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT                         0x12
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT                      0x13
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT                         0x13
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED__SHIFT                          0x14
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR__SHIFT                             0x14
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED__SHIFT                          0x15
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR__SHIFT                             0x15
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED__SHIFT                          0x16
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR__SHIFT                             0x16
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED__SHIFT                          0x17
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR__SHIFT                             0x17
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED__SHIFT                          0x18
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR__SHIFT                             0x18
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED__SHIFT                          0x19
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR__SHIFT                             0x19
++#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED__SHIFT                                     0x1a
++#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR__SHIFT                                        0x1a
++#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED__SHIFT                                     0x1b
++#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR__SHIFT                                        0x1b
++#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED__SHIFT                                    0x1c
++#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR__SHIFT                                       0x1c
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED_MASK                           0x00000001L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR_MASK                              0x00000001L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED_MASK                           0x00000002L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR_MASK                              0x00000002L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED_MASK                           0x00000004L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR_MASK                              0x00000004L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED_MASK                           0x00000008L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR_MASK                              0x00000008L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED_MASK                          0x00000010L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR_MASK                             0x00000010L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED_MASK                          0x00000020L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR_MASK                             0x00000020L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED_MASK                          0x00000040L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR_MASK                             0x00000040L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED_MASK                          0x00000080L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR_MASK                             0x00000080L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED_MASK                          0x00000100L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR_MASK                             0x00000100L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED_MASK                          0x00000200L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR_MASK                             0x00000200L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK                         0x00000400L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR_MASK                            0x00000400L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK                         0x00000800L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR_MASK                            0x00000800L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK                         0x00001000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR_MASK                            0x00001000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK                         0x00002000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR_MASK                            0x00002000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK                        0x00004000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR_MASK                           0x00004000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK                        0x00008000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR_MASK                           0x00008000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK                        0x00010000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR_MASK                           0x00010000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK                        0x00020000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR_MASK                           0x00020000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK                        0x00040000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR_MASK                           0x00040000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK                        0x00080000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR_MASK                           0x00080000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED_MASK                            0x00100000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR_MASK                               0x00100000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED_MASK                            0x00200000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR_MASK                               0x00200000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED_MASK                            0x00400000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR_MASK                               0x00400000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED_MASK                            0x00800000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR_MASK                               0x00800000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED_MASK                            0x01000000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR_MASK                               0x01000000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED_MASK                            0x02000000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR_MASK                               0x02000000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED_MASK                                       0x04000000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR_MASK                                          0x04000000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED_MASK                                       0x08000000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR_MASK                                          0x08000000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED_MASK                                      0x10000000L
++#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR_MASK                                         0x10000000L
++//DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN__SHIFT                  0x0
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN__SHIFT                  0x1
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN__SHIFT                  0x2
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN__SHIFT                  0x3
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN__SHIFT                 0x4
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN__SHIFT                 0x5
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN__SHIFT                 0x6
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN__SHIFT                 0x7
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN__SHIFT                 0x8
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN__SHIFT                 0x9
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xa
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xb
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xc
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xd
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN__SHIFT               0xe
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN__SHIFT               0xf
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x10
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x11
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x12
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x13
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN__SHIFT                   0x14
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN__SHIFT                   0x15
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN__SHIFT                   0x16
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN__SHIFT                   0x17
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN__SHIFT                   0x18
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN__SHIFT                   0x19
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN__SHIFT                              0x1a
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN__SHIFT                              0x1b
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN__SHIFT                             0x1c
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN_MASK                    0x00000001L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN_MASK                    0x00000002L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN_MASK                    0x00000004L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN_MASK                    0x00000008L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN_MASK                   0x00000010L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN_MASK                   0x00000020L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN_MASK                   0x00000040L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN_MASK                   0x00000080L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN_MASK                   0x00000100L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN_MASK                   0x00000200L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00000400L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00000800L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00001000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00002000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00004000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00008000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00010000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00020000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00040000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00080000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN_MASK                     0x00100000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN_MASK                     0x00200000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN_MASK                     0x00400000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN_MASK                     0x00800000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN_MASK                     0x01000000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN_MASK                     0x02000000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN_MASK                                0x04000000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN_MASK                                0x08000000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN_MASK                               0x10000000L
++//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x0
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x1
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x2
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x3
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x4
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x5
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x6
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x7
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x8
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x9
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xa
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xb
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xc
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xd
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0xe
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0xf
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x10
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x11
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x12
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x13
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL__SHIFT          0x14
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL__SHIFT          0x15
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL__SHIFT          0x16
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL__SHIFT          0x17
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL__SHIFT          0x18
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL__SHIFT          0x19
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT                     0x1a
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT                     0x1b
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                    0x1c
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000001L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000002L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000004L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000008L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000010L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000020L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000040L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000080L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000100L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000200L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00000400L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00000800L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00001000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00002000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00004000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00008000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00010000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00020000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00040000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00080000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL_MASK            0x00100000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL_MASK            0x00200000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL_MASK            0x00400000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL_MASK            0x00800000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL_MASK            0x01000000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL_MASK            0x02000000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL_MASK                       0x04000000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL_MASK                       0x08000000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK                      0x10000000L
++//DMCU_INT_CNT_CONTINUE
++#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT__SHIFT                                              0x0
++#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT__SHIFT                                              0x8
++#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT__SHIFT                                             0x10
++#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT_MASK                                                0x000000FFL
++#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT_MASK                                                0x0000FF00L
++#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT_MASK                                               0x00FF0000L
++//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x0
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x1
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x2
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x3
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x4
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x5
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x6
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x7
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x8
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x9
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0xa
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0xb
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL__SHIFT                        0x10
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL__SHIFT                        0x11
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL__SHIFT                        0x12
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL__SHIFT                        0x13
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL__SHIFT                        0x14
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL__SHIFT                        0x15
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL__SHIFT                        0x16
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000001L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000002L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000004L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000008L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000010L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000020L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000040L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000080L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000100L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000200L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000400L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000800L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL_MASK                          0x00010000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL_MASK                          0x00020000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL_MASK                          0x00040000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL_MASK                          0x00080000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL_MASK                          0x00100000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL_MASK                          0x00200000L
++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL_MASK                          0x00400000L
++//DMCU_INTERRUPT_STATUS_2
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT                               0x0
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR__SHIFT                                  0x0
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT                               0x1
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR__SHIFT                                  0x1
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT                               0x2
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR__SHIFT                                  0x2
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT                               0x3
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR__SHIFT                                  0x3
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED__SHIFT                               0x4
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR__SHIFT                                  0x4
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED__SHIFT                               0x5
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR__SHIFT                                  0x5
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT                             0x6
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT                                0x6
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT                             0x7
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT                                0x7
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT                             0x8
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT                                0x8
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT                             0x9
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT                                0x9
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED__SHIFT                             0xa
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR__SHIFT                                0xa
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED__SHIFT                             0xb
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR__SHIFT                                0xb
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED__SHIFT                                            0x10
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR__SHIFT                                               0x10
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED__SHIFT                                            0x11
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR__SHIFT                                               0x11
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED__SHIFT                                            0x12
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR__SHIFT                                               0x12
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED__SHIFT                                            0x13
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR__SHIFT                                               0x13
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED__SHIFT                                            0x14
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR__SHIFT                                               0x14
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED__SHIFT                                            0x15
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR__SHIFT                                               0x15
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED__SHIFT                                            0x16
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR__SHIFT                                               0x16
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED_MASK                                 0x00000001L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR_MASK                                    0x00000001L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED_MASK                                 0x00000002L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR_MASK                                    0x00000002L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED_MASK                                 0x00000004L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR_MASK                                    0x00000004L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED_MASK                                 0x00000008L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR_MASK                                    0x00000008L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED_MASK                                 0x00000010L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR_MASK                                    0x00000010L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED_MASK                                 0x00000020L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR_MASK                                    0x00000020L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK                               0x00000040L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR_MASK                                  0x00000040L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK                               0x00000080L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR_MASK                                  0x00000080L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK                               0x00000100L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR_MASK                                  0x00000100L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK                               0x00000200L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR_MASK                                  0x00000200L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED_MASK                               0x00000400L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR_MASK                                  0x00000400L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED_MASK                               0x00000800L
++#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR_MASK                                  0x00000800L
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED_MASK                                              0x00010000L
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR_MASK                                                 0x00010000L
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED_MASK                                              0x00020000L
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR_MASK                                                 0x00020000L
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED_MASK                                              0x00040000L
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR_MASK                                                 0x00040000L
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED_MASK                                              0x00080000L
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR_MASK                                                 0x00080000L
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED_MASK                                              0x00100000L
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR_MASK                                                 0x00100000L
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED_MASK                                              0x00200000L
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR_MASK                                                 0x00200000L
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED_MASK                                              0x00400000L
++#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR_MASK                                                 0x00400000L
++//DMCU_INTERRUPT_TO_UC_EN_MASK_2
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN__SHIFT                        0x0
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN__SHIFT                        0x1
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN__SHIFT                        0x2
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN__SHIFT                        0x3
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN__SHIFT                        0x4
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN__SHIFT                        0x5
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x6
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x7
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x8
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x9
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0xa
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0xb
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN__SHIFT                                     0x10
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN__SHIFT                                     0x11
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN__SHIFT                                     0x12
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN__SHIFT                                     0x13
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN__SHIFT                                     0x14
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN__SHIFT                                     0x15
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN__SHIFT                                     0x16
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN_MASK                          0x00000001L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN_MASK                          0x00000002L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN_MASK                          0x00000004L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN_MASK                          0x00000008L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN_MASK                          0x00000010L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN_MASK                          0x00000020L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000040L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000080L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000100L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000200L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000400L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000800L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN_MASK                                       0x00010000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN_MASK                                       0x00020000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN_MASK                                       0x00040000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN_MASK                                       0x00080000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN_MASK                                       0x00100000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN_MASK                                       0x00200000L
++#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN_MASK                                       0x00400000L
++
++
++// addressBlock: dce_dc_dmu_ihc_dispdec
++//DC_GPU_TIMER_START_POSITION_V_UPDATE
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT                  0x0
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT                  0x4
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT                  0x8
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT                  0xc
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT                  0x10
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT                  0x14
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK                    0x00000007L
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK                    0x00000070L
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK                    0x00000700L
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK                    0x00007000L
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK                    0x00070000L
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK                    0x00700000L
++//DC_GPU_TIMER_START_POSITION_VSTARTUP
++#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT                  0x0
++#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT                  0x4
++#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT                  0x8
++#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT                  0xc
++#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT                  0x10
++#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT                  0x14
++#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK                    0x00000007L
++#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK                    0x00000070L
++#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK                    0x00000700L
++#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK                    0x00007000L
++#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK                    0x00070000L
++#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK                    0x00700000L
++//DC_GPU_TIMER_READ
++#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT                                                           0x0
++#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK                                                             0xFFFFFFFFL
++//DC_GPU_TIMER_READ_CNTL
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT                                               0x0
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT                               0x8
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT                               0xb
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT                               0xe
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT                               0x11
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT                               0x14
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT                               0x17
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK                                                 0x0000007FL
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK                                 0x00000700L
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK                                 0x00003800L
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK                                 0x0001C000L
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK                                 0x000E0000L
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK                                 0x00700000L
++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK                                 0x03800000L
++//DISP_INTERRUPT_STATUS
++#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT                                          0x1
++#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT                                             0x4
++#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                                0x5
++#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                                      0x6
++#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT                                                0x7
++#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT                                                0x8
++#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                            0x9
++#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                              0xa
++#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                                0xf
++#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                                    0x10
++#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT                                                       0x11
++#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT                                                    0x12
++#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT                                                  0x13
++#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT                                                  0x14
++#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_GENERITE_INTERRUPT__SHIFT                                      0x16
++#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT                                            0x17
++#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT                                                0x18
++#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT                                                    0x1a
++#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT                                                            0x1b
++#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT                                                       0x1c
++#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT                                                       0x1d
++#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT                                                      0x1e
++#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT                                          0x1f
++#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK                                            0x00000002L
++#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK                                               0x00000010L
++#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                                  0x00000020L
++#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                                        0x00000040L
++#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK                                                  0x00000080L
++#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK                                                  0x00000100L
++#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK                                              0x00000200L
++#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                                0x00000400L
++#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                                  0x00008000L
++#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                                      0x00010000L
++#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK                                                         0x00020000L
++#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK                                                      0x00040000L
++#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK                                                    0x00080000L
++#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK                                                    0x00100000L
++#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_GENERITE_INTERRUPT_MASK                                        0x00400000L
++#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK                                              0x00800000L
++#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK                                                  0x01000000L
++#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK                                                      0x04000000L
++#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK                                                              0x08000000L
++#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK                                                         0x10000000L
++#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK                                                         0x20000000L
++#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK                                                        0x40000000L
++#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK                                            0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE
++#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT                                 0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT                                    0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                       0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                             0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT                                       0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT                                       0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                   0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                     0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                       0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                           0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT                                              0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT                                           0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT                                         0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT                                         0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT                        0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT                             0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT                      0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT                                   0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT                                   0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT                                   0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT                                0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK                                   0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK                                      0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                         0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                               0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK                                         0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK                                         0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK                                     0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                       0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                         0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                             0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK                                                0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK                                             0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK                                           0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK                                           0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK                          0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK                               0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK                        0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK                                     0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK                                     0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK                                     0x40000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK                                  0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE2
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT                                             0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT                                          0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT                                        0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT                                        0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT                       0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT                            0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT                     0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT                               0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK                                               0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK                                            0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK                                          0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK                                          0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK                         0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK                              0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK                       0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK                                 0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE3
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT                                             0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT                                          0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT                                        0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT                                        0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_HOST_CONFLICT_INTERRUPT__SHIFT                                0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT                       0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT                            0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT                     0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT                               0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK                                               0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK                                            0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK                                          0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK                                          0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_HOST_CONFLICT_INTERRUPT_MASK                                  0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK                                  0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK                         0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK                              0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK                       0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK                                 0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE4
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT                                             0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT                                          0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT                                        0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT                                        0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT                       0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT                            0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT                     0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT                       0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT                            0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT                     0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT                               0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK                                               0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK                                            0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK                                          0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK                                          0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK                         0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK                              0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK                       0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK                         0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK                              0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK                       0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK                                 0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE5
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT                                             0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT                                          0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT                                        0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT                                        0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT                       0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT                            0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT                     0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT                               0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK                                               0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK                                            0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK                                          0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK                                          0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK                         0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK                              0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK                       0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK                                    0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK                                    0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK                                    0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK                                 0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE6
++#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT                                      0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT                                      0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT                                      0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT                                      0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT                                      0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT                               0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK                                        0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK                                        0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK                                        0x00000800L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK                                        0x00001000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK                                        0x00002000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00200000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK                                 0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE7
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT                               0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK                                 0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE8
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT                               0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK                                 0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE9
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_HOST_CONFLICT_INTERRUPT__SHIFT                                0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_HOST_CONFLICT_INTERRUPT__SHIFT                                0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT                              0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_HOST_CONFLICT_INTERRUPT_MASK                                  0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK                                  0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_HOST_CONFLICT_INTERRUPT_MASK                                  0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK                                  0x40000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK                                0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE10
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT                                0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT                                0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT                                0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT                                0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT                                0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT                                0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT                             0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT                             0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_RANGE_TIMING_UPDATE__SHIFT                                 0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_RANGE_TIMING_UPDATE__SHIFT                                 0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_RANGE_TIMING_UPDATE__SHIFT                                 0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_RANGE_TIMING_UPDATE__SHIFT                                 0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_RANGE_TIMING_UPDATE__SHIFT                                 0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_RANGE_TIMING_UPDATE__SHIFT                                 0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT                             0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK                                  0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK                                  0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK                                  0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK                                  0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK                                  0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK                                  0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK                               0x00001000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK                               0x00002000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_RANGE_TIMING_UPDATE_MASK                                   0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_RANGE_TIMING_UPDATE_MASK                                   0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_RANGE_TIMING_UPDATE_MASK                                   0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_RANGE_TIMING_UPDATE_MASK                                   0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_RANGE_TIMING_UPDATE_MASK                                   0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_RANGE_TIMING_UPDATE_MASK                                   0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK                               0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE11
++#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT                                        0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT                                        0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT                                        0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT                                        0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT                                        0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT                                        0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT                                        0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT                                        0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT                                    0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT                             0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK                                          0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK                                          0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK                                          0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK                                          0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK                                          0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK                                          0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK                                          0x00200000L
++#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK                                          0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK                                      0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK                               0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE12
++#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT                             0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK                               0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE13
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT                            0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT                            0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT                                0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT                                 0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT                          0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT                          0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT                          0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT                          0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT                          0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT                          0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT                          0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT                          0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT                             0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK                              0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK                              0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK                                  0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK                                   0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK                            0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK                            0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK                            0x00000800L
++#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK                            0x00001000L
++#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK                            0x00002000L
++#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK                            0x00004000L
++#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK                            0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK                            0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK                               0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE14
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT                             0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK                               0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE15
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
++#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT                             0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK                               0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE16
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT                                   0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT                                    0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT                                   0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT                                   0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT                                    0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT                                   0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT                                   0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT                                    0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT                                   0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT                                   0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT                                    0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT                                   0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT                                   0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT                                    0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT                                   0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT                             0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK                                     0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK                                      0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK                                     0x00000800L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK                                     0x00001000L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK                                      0x00002000L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK                                     0x00004000L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK                                     0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK                                      0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK                                     0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK                                     0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK                                      0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK                                     0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK                                     0x00200000L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK                                      0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK                                     0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK                                    0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK                                    0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK                                    0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK                                    0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK                                    0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK                               0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE17
++#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT                                     0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT                                     0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT                                     0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT                                     0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT                                     0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT                                     0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT                                     0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT                                     0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT                          0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT                          0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT                             0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK                                       0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK                                       0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK                                       0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK                                       0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK                                       0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK                                       0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK                                       0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK                                       0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000800L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK                            0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK                            0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00200000L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK                               0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE18
++#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_IHC_RXSENSE_INTERRUPT__SHIFT                                   0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT                            0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT                            0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT                            0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT                            0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT                            0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT                            0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT                            0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT                            0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT                        0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT                        0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT                        0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT                        0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT                        0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT                        0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT                        0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT                        0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT                             0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_IHC_RXSENSE_INTERRUPT_MASK                                     0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK                              0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK                              0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK                              0x00000800L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK                              0x00001000L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK                              0x00002000L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK                              0x00004000L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK                              0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK                              0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK                          0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK                          0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK                          0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK                          0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK                          0x00200000L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK                          0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK                          0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK                          0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK                               0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE19
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT                           0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT                           0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT                           0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT                           0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT                           0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT                           0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT                           0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT                           0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT                          0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT                          0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT                          0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT                          0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT                          0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT                          0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT                          0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT                          0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT                             0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK                             0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK                             0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK                             0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK                             0x00000800L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK                             0x00001000L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK                             0x00002000L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK                             0x00004000L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK                             0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK                            0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK                            0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK                            0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK                            0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK                            0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK                            0x00200000L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK                            0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK                            0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK                               0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE20
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT                                    0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT                                    0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT                                    0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT                                    0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT                                    0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT                                    0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT                             0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000800L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00001000L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00002000L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00004000L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00200000L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK                                      0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK                                      0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK                                      0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK                                      0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK                                      0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK                                      0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK                               0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE21
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT                          0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT                          0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT                          0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT                          0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT                          0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT                          0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT                        0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT                           0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT                           0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT                           0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT                           0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT                           0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT                           0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT                            0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT__SHIFT                        0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT                             0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK                            0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK                            0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK                            0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK                            0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK                            0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK                            0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK                          0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK                             0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK                             0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK                             0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK                             0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK                             0x00000800L
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK                             0x00001000L
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK                              0x00002000L
++#define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT_MASK                          0x00004000L
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK                               0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE22
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT__SHIFT                          0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT__SHIFT                          0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT__SHIFT                         0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT__SHIFT                         0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT__SHIFT                         0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT__SHIFT                         0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT__SHIFT                         0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT__SHIFT                         0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT__SHIFT                        0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT__SHIFT                        0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT__SHIFT                       0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT__SHIFT                       0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT__SHIFT                       0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT__SHIFT                       0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT__SHIFT                       0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT__SHIFT                       0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT__SHIFT                                            0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT__SHIFT                                            0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT__SHIFT                                           0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT                             0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_MASK                            0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_MASK                            0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_MASK                           0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_MASK                           0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_MASK                           0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_MASK                           0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_MASK                           0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_MASK                           0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_MASK                          0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_MASK                          0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_MASK                         0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_MASK                         0x00000800L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_MASK                         0x00001000L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_MASK                         0x00002000L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_MASK                         0x00004000L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_MASK                         0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT_MASK                                              0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT_MASK                                              0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT_MASK                                             0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00200000L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK                               0x80000000L
++//DC_GPU_TIMER_START_POSITION_VREADY
++#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT                      0x0
++#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT                      0x4
++#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT                      0x8
++#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT                      0xc
++#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT                      0x10
++#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT                      0x14
++#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK                        0x00000007L
++#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK                        0x00000070L
++#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK                        0x00000700L
++#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK                        0x00007000L
++#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK                        0x00070000L
++#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK                        0x00700000L
++//DC_GPU_TIMER_START_POSITION_FLIP
++#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT                          0x0
++#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT                          0x4
++#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT                          0x8
++#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT                          0xc
++#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT                          0x10
++#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT                          0x14
++#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT                          0x18
++#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT                          0x1c
++#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK                            0x00000007L
++#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK                            0x00000070L
++#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK                            0x00000700L
++#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK                            0x00007000L
++#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK                            0x00070000L
++#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK                            0x00700000L
++#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK                            0x07000000L
++#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK                            0x70000000L
++//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT  0x0
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT  0x4
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT  0x8
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT  0xc
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT  0x10
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT  0x14
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK    0x00000007L
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK    0x00000070L
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK    0x00000700L
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK    0x00007000L
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK    0x00070000L
++#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK    0x00700000L
++//DC_GPU_TIMER_START_POSITION_FLIP_AWAY
++#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT                0x0
++#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT                0x4
++#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT                0x8
++#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT                0xc
++#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT                0x10
++#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT                0x14
++#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT                0x18
++#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT                0x1c
++#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK                  0x00000007L
++#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK                  0x00000070L
++#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK                  0x00000700L
++#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK                  0x00007000L
++#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK                  0x00070000L
++#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK                  0x00700000L
++#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK                  0x07000000L
++#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK                  0x70000000L
++//DISP_INTERRUPT_STATUS_CONTINUE23
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT                         0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT                         0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT                         0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT                         0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT                         0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT                         0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT                       0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT                       0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT                       0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT                       0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT                       0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT                       0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x1a
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x1b
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT                             0x1f
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK                           0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK                           0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK                           0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK                           0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK                           0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK                           0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK                         0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK                         0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK                         0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK                         0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK                         0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK                         0x00000800L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00200000L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x02000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x04000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x08000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK                               0x80000000L
++//DISP_INTERRUPT_STATUS_CONTINUE24
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x0
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x1
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x2
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x3
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x4
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x5
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x6
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x7
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x8
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x9
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0xa
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xb
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT                          0xc
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT                           0xd
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                    0xe
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                     0xf
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                     0x10
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                      0x11
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                   0x12
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                    0x13
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                    0x14
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                     0x15
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT                              0x16
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT                              0x17
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT                              0x18
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT                      0x19
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000001L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000002L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000004L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000008L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000010L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000020L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000040L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000080L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000100L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000200L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000400L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000800L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK                            0x00001000L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK                             0x00002000L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                      0x00004000L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                       0x00008000L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                       0x00010000L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                        0x00020000L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                     0x00040000L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                      0x00080000L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                      0x00100000L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                       0x00200000L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK                                0x00400000L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK                                0x00800000L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK                                0x01000000L
++#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK                        0x02000000L
++//DCCG_INTERRUPT_DEST
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT                                        0x0
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT                                        0x1
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT                                        0x2
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT                                        0x3
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT                                        0x4
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT                                        0x5
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                  0xc
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                  0xd
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST__SHIFT                                 0xe
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST__SHIFT                                 0xf
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK                                          0x00000001L
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK                                          0x00000002L
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK                                          0x00000004L
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK                                          0x00000008L
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK                                          0x00000010L
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK                                          0x00000020L
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                    0x00001000L
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                    0x00002000L
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST_MASK                                   0x00004000L
++#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST_MASK                                   0x00008000L
++//DMU_INTERRUPT_DEST
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT                                                  0x0
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT                                                  0x1
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT                                                  0x2
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT                                                  0x3
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT                                            0x4
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT                                             0x5
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT                                            0x6
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT                                             0x7
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT                                           0x8
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT                                            0x9
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT                                           0xa
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT                                            0xb
++#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
++#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
++#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST__SHIFT                                      0xe
++#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST__SHIFT                                      0xf
++#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST__SHIFT                                     0x10
++#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST__SHIFT                                      0x11
++#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST__SHIFT                                      0x12
++#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST__SHIFT                                     0x13
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT                                                  0x18
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT                                 0x19
++#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                          0x1a
++#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST__SHIFT                                      0x1b
++#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST__SHIFT                                                0x1c
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK                                                    0x00000001L
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK                                                    0x00000002L
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK                                                    0x00000004L
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK                                                    0x00000008L
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK                                              0x00000010L
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK                                               0x00000020L
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK                                              0x00000040L
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK                                               0x00000080L
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK                                             0x00000100L
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK                                              0x00000200L
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK                                             0x00000400L
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK                                              0x00000800L
++#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
++#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
++#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST_MASK                                        0x00004000L
++#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST_MASK                                        0x00008000L
++#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST_MASK                                       0x00010000L
++#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST_MASK                                        0x00020000L
++#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST_MASK                                        0x00040000L
++#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST_MASK                                       0x00080000L
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK                                                    0x01000000L
++#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK                                   0x02000000L
++#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                            0x04000000L
++#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST_MASK                                        0x08000000L
++#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST_MASK                                                  0x10000000L
++//DCPG_INTERRUPT_DEST
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x0
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x1
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x2
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x3
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x4
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x5
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x6
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x7
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x8
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x9
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xa
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xb
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xc
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xd
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xe
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xf
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x10
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x11
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x12
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x13
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x14
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x15
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x16
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x17
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x18
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x19
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1a
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1b
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1c
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1d
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1e
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1f
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000001L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000002L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000004L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000008L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000010L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000020L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000040L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000080L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000100L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000200L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_DEST_MASK                                   0x00000400L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_DEST_MASK                                   0x00000800L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_DEST_MASK                                   0x00001000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_DEST_MASK                                   0x00002000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_DEST_MASK                                   0x00004000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_DEST_MASK                                   0x00008000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00010000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00020000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00040000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00080000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00100000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00200000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00400000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00800000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x01000000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x02000000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x04000000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x08000000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x10000000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x20000000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x40000000L
++#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x80000000L
++//DCPG_INTERRUPT_DEST2
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT                                0x0
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT                                0x1
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT                                0x2
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT                                0x3
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT                                0x4
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT                                0x5
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x6
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x7
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x8
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x9
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xa
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xb
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000001L
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000002L
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000004L
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000008L
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000010L
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000020L
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000040L
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000080L
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000100L
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000200L
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000400L
++#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000800L
++//MMHUBBUB_INTERRUPT_DEST
++#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST__SHIFT                                        0x0
++#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x1
++#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x2
++#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x3
++#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x4
++#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT                                       0x5
++#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                          0xc
++#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                          0xd
++#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST_MASK                                          0x00000001L
++#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000002L
++#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000004L
++#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000008L
++#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000010L
++#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK                                         0x00000020L
++#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                            0x00001000L
++#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                            0x00002000L
++//WB_INTERRUPT_DEST
++#define WB_INTERRUPT_DEST__WBSCL0_IHIF_HOST_CONFLICT_INTERRUPT_DEST__SHIFT                                    0x0
++#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x1
++#define WB_INTERRUPT_DEST__WBSCL1_IHIF_HOST_CONFLICT_INTERRUPT_DEST__SHIFT                                    0x8
++#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x9
++#define WB_INTERRUPT_DEST__WBSCL2_IHIF_HOST_CONFLICT_INTERRUPT_DEST__SHIFT                                    0xa
++#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0xb
++#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0xc
++#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0xd
++#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0xe
++#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0xf
++#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0x10
++#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0x11
++#define WB_INTERRUPT_DEST__WBSCL0_IHIF_HOST_CONFLICT_INTERRUPT_DEST_MASK                                      0x00000001L
++#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000002L
++#define WB_INTERRUPT_DEST__WBSCL1_IHIF_HOST_CONFLICT_INTERRUPT_DEST_MASK                                      0x00000100L
++#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000200L
++#define WB_INTERRUPT_DEST__WBSCL2_IHIF_HOST_CONFLICT_INTERRUPT_DEST_MASK                                      0x00000400L
++#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000800L
++#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00001000L
++#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00002000L
++#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00004000L
++#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00008000L
++#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00010000L
++#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00020000L
++//DCHUB_INTERRUPT_DEST
++#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x0
++#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1
++#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x2
++#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x3
++#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x4
++#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x5
++#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x6
++#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x7
++#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x8
++#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x9
++#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xa
++#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xb
++#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0xc
++#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0xd
++#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xe
++#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xf
++#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x10
++#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x11
++#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x12
++#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x13
++#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x14
++#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x15
++#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x16
++#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x17
++#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x18
++#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x19
++#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1a
++#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1b
++#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x1c
++#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1d
++#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1e
++#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1f
++#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000001L
++#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000002L
++#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000004L
++#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000008L
++#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000010L
++#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000020L
++#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000040L
++#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000080L
++#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000100L
++#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000200L
++#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000400L
++#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000800L
++#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00001000L
++#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00002000L
++#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00004000L
++#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00008000L
++#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00010000L
++#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00020000L
++#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00040000L
++#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00080000L
++#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00100000L
++#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00200000L
++#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00400000L
++#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00800000L
++#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x01000000L
++#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x02000000L
++#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x04000000L
++#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x08000000L
++#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x10000000L
++#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x20000000L
++#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x40000000L
++#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x80000000L
++//DCHUB_PERFCOUNTER_INTERRUPT_DEST
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                   0xc
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                   0xd
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0xe
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0xf
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x10
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x11
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x12
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x13
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x14
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x15
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x16
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x17
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x18
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x19
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x1a
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x1b
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x1c
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x1d
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                     0x00001000L
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                     0x00002000L
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00004000L
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00008000L
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00010000L
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00020000L
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00040000L
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00080000L
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00100000L
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00200000L
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00400000L
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00800000L
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x01000000L
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x02000000L
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x04000000L
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x08000000L
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x10000000L
++#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x20000000L
++//DCHUB_INTERRUPT_DEST2
++#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x0
++#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x1
++#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x2
++#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x3
++#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x4
++#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x5
++#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x6
++#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x7
++#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x8
++#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x9
++#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xa
++#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xb
++#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xc
++#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xd
++#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xe
++#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xf
++#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT                                      0x18
++#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                       0x19
++#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000001L
++#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000002L
++#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000004L
++#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000008L
++#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000010L
++#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000020L
++#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000040L
++#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000080L
++#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000100L
++#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000200L
++#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000400L
++#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000800L
++#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00001000L
++#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00002000L
++#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00004000L
++#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00008000L
++#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK                                        0x01000000L
++#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                         0x02000000L
++//DPP_PERFCOUNTER_INTERRUPT_DEST
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0xc
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0xd
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0xe
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0xf
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x10
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x11
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x12
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x13
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x14
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x15
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x16
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x17
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x18
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x19
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x1a
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x1b
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00001000L
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00002000L
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00004000L
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00008000L
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00010000L
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00020000L
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00040000L
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00080000L
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00100000L
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00200000L
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00400000L
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00800000L
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x01000000L
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x02000000L
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x04000000L
++#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x08000000L
++//MPC_INTERRUPT_DEST
++#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT                                                 0x0
++#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT                                                 0x1
++#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT                                                 0x2
++#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT                                                 0x3
++#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT                                                 0x4
++#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT                                                 0x5
++#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT                                                 0x6
++#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT                                                 0x7
++#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
++#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
++#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK                                                   0x00000001L
++#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK                                                   0x00000002L
++#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK                                                   0x00000004L
++#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK                                                   0x00000008L
++#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK                                                   0x00000010L
++#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK                                                   0x00000020L
++#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK                                                   0x00000040L
++#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK                                                   0x00000080L
++#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
++#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
++//OPP_INTERRUPT_DEST
++#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
++#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
++#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
++#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
++//OPTC_INTERRUPT_DEST
++#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                  0xc
++#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                  0xd
++#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x18
++#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x19
++#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1a
++#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1b
++#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1c
++#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1d
++#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                    0x00001000L
++#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                    0x00002000L
++#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x01000000L
++#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x02000000L
++#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x04000000L
++#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x08000000L
++#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x10000000L
++#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x20000000L
++//OTG0_INTERRUPT_DEST
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT                                      0x1
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT                          0xc
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT                               0xd
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT                        0xe
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK                                        0x00000002L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK                            0x00001000L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK                                 0x00002000L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK                          0x00004000L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
++#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
++//OTG1_INTERRUPT_DEST
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT                                      0x1
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT                          0xc
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT                               0xd
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT                        0xe
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK                                        0x00000002L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK                            0x00001000L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK                                 0x00002000L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK                          0x00004000L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
++#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
++//OTG2_INTERRUPT_DEST
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT                                      0x1
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT                          0xc
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT                               0xd
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT                        0xe
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK                                        0x00000002L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK                            0x00001000L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK                                 0x00002000L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK                          0x00004000L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
++#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
++//OTG3_INTERRUPT_DEST
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT                                      0x1
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT                          0xc
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT                               0xd
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT                        0xe
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK                                        0x00000002L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK                            0x00001000L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK                                 0x00002000L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK                          0x00004000L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
++#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
++//OTG4_INTERRUPT_DEST
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT                                      0x1
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT                          0xc
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT                               0xd
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT                        0xe
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK                                        0x00000002L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK                            0x00001000L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK                                 0x00002000L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK                          0x00004000L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
++#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
++//OTG5_INTERRUPT_DEST
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT                                      0x1
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT                          0xc
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT                               0xd
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT                        0xe
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK                                        0x00000002L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK                            0x00001000L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK                                 0x00002000L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK                          0x00004000L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
++#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
++//DIG_INTERRUPT_DEST
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x0
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x1
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x2
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x3
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x4
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x5
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x6
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x7
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x8
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x9
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xa
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xb
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xc
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xd
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xe
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xf
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000001L
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000002L
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000004L
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000008L
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000010L
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000020L
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000040L
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000080L
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000100L
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000200L
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000400L
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000800L
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00001000L
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00002000L
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00004000L
++#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00008000L
++//I2C_DDC_HPD_INTERRUPT_DEST
++#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT                                0x0
++#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT                           0x1
++#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT                           0x2
++#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT                           0x3
++#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT                           0x4
++#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT                           0x5
++#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT                           0x6
++#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT                         0x7
++#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x10
++#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x11
++#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x12
++#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x13
++#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x14
++#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x15
++#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT                          0x16
++#define I2C_DDC_HPD_INTERRUPT_DEST__GENERIC_I2C_DDC_READ_REQUEST_INTERRPUT_DEST__SHIFT                        0x17
++#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK                                  0x00000001L
++#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK                             0x00000002L
++#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK                             0x00000004L
++#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK                             0x00000008L
++#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK                             0x00000010L
++#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK                             0x00000020L
++#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK                             0x00000040L
++#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK                           0x00000080L
++#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00010000L
++#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00020000L
++#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00040000L
++#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00080000L
++#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00100000L
++#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00200000L
++#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK                            0x00400000L
++#define I2C_DDC_HPD_INTERRUPT_DEST__GENERIC_I2C_DDC_READ_REQUEST_INTERRPUT_DEST_MASK                          0x00800000L
++//DIO_INTERRUPT_DEST
++#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
++#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
++#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
++#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
++//DCIO_INTERRUPT_DEST
++#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x0
++#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x1
++#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x2
++#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x3
++#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x4
++#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x5
++#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x6
++#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x10
++#define DCIO_INTERRUPT_DEST__DCIO_IHC_RXSENSE_INTERRUPT_DEST__SHIFT                                           0x18
++#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000001L
++#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000002L
++#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000004L
++#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000008L
++#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000010L
++#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000020L
++#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000040L
++#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00010000L
++#define DCIO_INTERRUPT_DEST__DCIO_IHC_RXSENSE_INTERRUPT_DEST_MASK                                             0x01000000L
++//HPD_INTERRUPT_DEST
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT                                               0x0
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT                                               0x1
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT                                               0x2
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT                                               0x3
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT                                               0x4
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT                                               0x5
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT                                            0x8
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT                                            0x9
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT                                            0xa
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT                                            0xb
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT                                            0xc
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT                                            0xd
++#define HPD_INTERRUPT_DEST__DOUT_IHC_DACA_AUTODETECT_GENERATE_INTERRUPT_DEST__SHIFT                           0xe
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK                                                 0x00000001L
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK                                                 0x00000002L
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK                                                 0x00000004L
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK                                                 0x00000008L
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK                                                 0x00000010L
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK                                                 0x00000020L
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK                                              0x00000100L
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK                                              0x00000200L
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK                                              0x00000400L
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK                                              0x00000800L
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK                                              0x00001000L
++#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK                                              0x00002000L
++#define HPD_INTERRUPT_DEST__DOUT_IHC_DACA_AUTODETECT_GENERATE_INTERRUPT_DEST_MASK                             0x00004000L
++//AZ_INTERRUPT_DEST
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x0
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x1
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x2
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x3
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x4
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x5
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x6
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x7
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x8
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x9
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xa
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xb
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xc
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xd
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xe
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xf
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x10
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x11
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x12
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x13
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x14
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x15
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x16
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x17
++#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                      0x1e
++#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                      0x1f
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000001L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000002L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000004L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000008L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000010L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000020L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000040L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000080L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000100L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000200L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000400L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000800L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK                                       0x00001000L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK                                       0x00002000L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK                                       0x00004000L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK                                       0x00008000L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK                                      0x00010000L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK                                      0x00020000L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK                                      0x00040000L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK                                      0x00080000L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK                                      0x00100000L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK                                      0x00200000L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK                                      0x00400000L
++#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK                                      0x00800000L
++#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                        0x40000000L
++#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                        0x80000000L
++//AUX_INTERRUPT_DEST
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x0
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x1
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x2
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x3
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x4
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x5
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x6
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x7
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x8
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x9
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT                                       0xa
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT                                       0xb
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x10
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x11
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x12
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x13
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x14
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x15
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x16
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x17
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x18
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x19
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x1a
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x1b
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000001L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000002L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000004L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000008L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000010L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000020L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000040L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000080L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000100L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000200L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000400L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000800L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00010000L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00020000L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00040000L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00080000L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00100000L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00200000L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00400000L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00800000L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x01000000L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x02000000L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x04000000L
++#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x08000000L
++//DSC_INTERRUPT_DEST
++#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x0
++#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x1
++#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x2
++#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x3
++#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x4
++#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x5
++#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x6
++#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x7
++#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x8
++#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x9
++#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0xa
++#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0xb
++#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0xc
++#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0xd
++#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0xe
++#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0xf
++#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x10
++#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x11
++#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x12
++#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x13
++#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x14
++#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x15
++#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x16
++#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x17
++#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000001L
++#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000002L
++#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000004L
++#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000008L
++#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000010L
++#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000020L
++#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000040L
++#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000080L
++#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000100L
++#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000200L
++#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000400L
++#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000800L
++#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00001000L
++#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00002000L
++#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00004000L
++#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00008000L
++#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00010000L
++#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00020000L
++#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00040000L
++#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00080000L
++#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00100000L
++#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00200000L
++#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00400000L
++#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00800000L
++
++
++// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec
++//WB_ENABLE
++#define WB_ENABLE__WB_ENABLE__SHIFT                                                                           0x0
++#define WB_ENABLE__WB_ENABLE_MASK                                                                             0x00000001L
++//WB_EC_CONFIG
++#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT                                                            0x0
++#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT                                                            0x1
++#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT                                                         0x2
++#define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT                                                                  0x3
++#define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT                                                                     0x7
++#define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT                                                                     0x8
++#define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT                                                                    0x9
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT                                                        0xc
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT                                                             0xe
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT                                                           0xf
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT                                                           0x15
++#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT                                                              0x17
++#define WB_EC_CONFIG__WBSCL_LUT_MEM_PWR_STATE__SHIFT                                                          0x18
++#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK                                                              0x00000001L
++#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK                                                              0x00000002L
++#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK                                                           0x00000004L
++#define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK                                                                    0x00000078L
++#define WB_EC_CONFIG__WB_LB_LS_DIS_MASK                                                                       0x00000080L
++#define WB_EC_CONFIG__WB_LB_SD_DIS_MASK                                                                       0x00000100L
++#define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK                                                                      0x00000200L
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK                                                          0x00003000L
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK                                                               0x00004000L
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK                                                             0x00018000L
++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK                                                             0x00600000L
++#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK                                                                0x00800000L
++#define WB_EC_CONFIG__WBSCL_LUT_MEM_PWR_STATE_MASK                                                            0x03000000L
++//CNV_MODE
++#define CNV_MODE__CNV_OUT_BPC__SHIFT                                                                          0x4
++#define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT                                                               0x8
++#define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT                                                                   0xc
++#define CNV_MODE__CNV_STEREO_TYPE__SHIFT                                                                      0xd
++#define CNV_MODE__CNV_INTERLACED_MODE__SHIFT                                                                  0xf
++#define CNV_MODE__CNV_EYE_SELECTION__SHIFT                                                                    0x10
++#define CNV_MODE__CNV_STEREO_POLARITY__SHIFT                                                                  0x12
++#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT                                                           0x13
++#define CNV_MODE__CNV_STEREO_SPLIT__SHIFT                                                                     0x14
++#define CNV_MODE__CNV_NEW_CONTENT__SHIFT                                                                      0x18
++#define CNV_MODE__CNV_FRAME_CAPTURE_EN_CURRENT__SHIFT                                                         0x1e
++#define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT                                                                 0x1f
++#define CNV_MODE__CNV_OUT_BPC_MASK                                                                            0x00000010L
++#define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK                                                                 0x00000300L
++#define CNV_MODE__CNV_WINDOW_CROP_EN_MASK                                                                     0x00001000L
++#define CNV_MODE__CNV_STEREO_TYPE_MASK                                                                        0x00006000L
++#define CNV_MODE__CNV_INTERLACED_MODE_MASK                                                                    0x00008000L
++#define CNV_MODE__CNV_EYE_SELECTION_MASK                                                                      0x00030000L
++#define CNV_MODE__CNV_STEREO_POLARITY_MASK                                                                    0x00040000L
++#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK                                                             0x00080000L
++#define CNV_MODE__CNV_STEREO_SPLIT_MASK                                                                       0x00100000L
++#define CNV_MODE__CNV_NEW_CONTENT_MASK                                                                        0x01000000L
++#define CNV_MODE__CNV_FRAME_CAPTURE_EN_CURRENT_MASK                                                           0x40000000L
++#define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK                                                                   0x80000000L
++//CNV_WINDOW_START
++#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT                                                           0x0
++#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT                                                           0x10
++#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK                                                             0x00000FFFL
++#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK                                                             0x0FFF0000L
++//CNV_WINDOW_SIZE
++#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT                                                              0x0
++#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT                                                             0x10
++#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK                                                                0x00000FFFL
++#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK                                                               0x0FFF0000L
++//CNV_UPDATE
++#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT                                                                 0x0
++#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT                                                                   0x8
++#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT                                                                    0x10
++#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK                                                                   0x00000001L
++#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK                                                                     0x00000100L
++#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK                                                                      0x00010000L
++//CNV_SOURCE_SIZE
++#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT                                                              0x0
++#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT                                                             0x10
++#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK                                                                0x00007FFFL
++#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK                                                               0x7FFF0000L
++//CNV_TEST_CNTL
++#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT                                                                 0x4
++#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT                                                            0x8
++#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK                                                                   0x00000010L
++#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK                                                              0x00000100L
++//CNV_TEST_CRC_RED
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT                                                        0x4
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT                                                         0x10
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK                                                          0x0000FFF0L
++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK                                                           0xFFFF0000L
++//CNV_TEST_CRC_GREEN
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT                                                    0x4
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT                                                     0x10
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK                                                      0x0000FFF0L
++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK                                                       0xFFFF0000L
++//CNV_TEST_CRC_BLUE
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT                                                      0x4
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT                                                       0x10
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK                                                        0x0000FFF0L
++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK                                                         0xFFFF0000L
++//WB_DEBUG_CTRL
++#define WB_DEBUG_CTRL__WB_DEBUG_EN__SHIFT                                                                     0x0
++#define WB_DEBUG_CTRL__WB_DEBUG_SEL__SHIFT                                                                    0x6
++#define WB_DEBUG_CTRL__WB_DEBUG_EN_MASK                                                                       0x00000001L
++#define WB_DEBUG_CTRL__WB_DEBUG_SEL_MASK                                                                      0x000000C0L
++//WB_DBG_MODE
++#define WB_DBG_MODE__WB_DBG_MODE_EN__SHIFT                                                                    0x0
++#define WB_DBG_MODE__WB_DBG_DIN_FMT__SHIFT                                                                    0x1
++#define WB_DBG_MODE__WB_DBG_36MODE__SHIFT                                                                     0x2
++#define WB_DBG_MODE__WB_DBG_CMAP__SHIFT                                                                       0x3
++#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR__SHIFT                                                              0x8
++#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH__SHIFT                                                               0x10
++#define WB_DBG_MODE__WB_DBG_MODE_EN_MASK                                                                      0x00000001L
++#define WB_DBG_MODE__WB_DBG_DIN_FMT_MASK                                                                      0x00000002L
++#define WB_DBG_MODE__WB_DBG_36MODE_MASK                                                                       0x00000004L
++#define WB_DBG_MODE__WB_DBG_CMAP_MASK                                                                         0x00000008L
++#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR_MASK                                                                0x00000100L
++#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH_MASK                                                                 0x7FFF0000L
++//WB_HW_DEBUG
++#define WB_HW_DEBUG__WB_HW_DEBUG__SHIFT                                                                       0x0
++#define WB_HW_DEBUG__WB_HW_DEBUG_MASK                                                                         0xFFFFFFFFL
++//WB_SOFT_RESET
++#define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT                                                                   0x0
++#define WB_SOFT_RESET__WB_SOFT_RESET_MASK                                                                     0x00000001L
++//WB_WARM_UP_MODE_CTL1
++#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP__SHIFT                                                             0x0
++#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP__SHIFT                                                            0x10
++#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE__SHIFT                                                       0x1f
++#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP_MASK                                                               0x00007FFFL
++#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP_MASK                                                              0x7FFF0000L
++#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE_MASK                                                         0x80000000L
++//WB_WARM_UP_MODE_CTL2
++#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP__SHIFT                                                        0x0
++#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP__SHIFT                                                              0x10
++#define WB_WARM_UP_MODE_CTL2__DATA_DEPTH_WARMUP__SHIFT                                                        0x14
++#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP_MASK                                                          0x000003FFL
++#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP_MASK                                                                0x00010000L
++#define WB_WARM_UP_MODE_CTL2__DATA_DEPTH_WARMUP_MASK                                                          0x00100000L
++//CNV_TEST_DEBUG_INDEX
++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT                                                     0x0
++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT                                                  0x8
++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK                                                       0x000000FFL
++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK                                                    0x00000100L
++//CNV_TEST_DEBUG_DATA
++#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT                                                       0x0
++#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK                                                         0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec
++//WBSCL_COEF_RAM_SELECT
++#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                             0x0
++#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE__SHIFT                                                    0x8
++#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE__SHIFT                                              0x10
++#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX_MASK                                               0x00000007L
++#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE_MASK                                                      0x00000F00L
++#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE_MASK                                                0x00030000L
++//WBSCL_COEF_RAM_TAP_DATA
++#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                          0x0
++#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                       0xf
++#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                           0x10
++#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                        0x1f
++#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_MASK                                            0x00003FFFL
++#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                         0x00008000L
++#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_MASK                                             0x3FFF0000L
++#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                          0x80000000L
++//WBSCL_MODE
++#define WBSCL_MODE__WBSCL_MODE__SHIFT                                                                         0x0
++#define WBSCL_MODE__WBSCL_OUT_BIT_DEPTH__SHIFT                                                                0x4
++#define WBSCL_MODE__WBSCL_MODE_MASK                                                                           0x00000003L
++#define WBSCL_MODE__WBSCL_OUT_BIT_DEPTH_MASK                                                                  0x00000010L
++//WBSCL_TAP_CONTROL
++#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB__SHIFT                                                   0x0
++#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR__SHIFT                                                    0x4
++#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB__SHIFT                                                   0x8
++#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR__SHIFT                                                    0xc
++#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB_MASK                                                     0x0000000FL
++#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR_MASK                                                      0x000000F0L
++#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB_MASK                                                     0x00000F00L
++#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR_MASK                                                      0x0000F000L
++//WBSCL_DEST_SIZE
++#define WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT__SHIFT                                                             0x0
++#define WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH__SHIFT                                                              0x10
++#define WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT_MASK                                                               0x00007FFFL
++#define WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH_MASK                                                                0x7FFF0000L
++//WBSCL_HORZ_FILTER_SCALE_RATIO
++#define WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO__SHIFT                                             0x0
++#define WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO_MASK                                               0x07FFFFFFL
++//WBSCL_HORZ_FILTER_INIT_Y_RGB
++#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB__SHIFT                                          0x0
++#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB__SHIFT                                           0x18
++#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB_MASK                                            0x00FFFFFFL
++#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB_MASK                                             0x1F000000L
++//WBSCL_HORZ_FILTER_INIT_CBCR
++#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR__SHIFT                                            0x0
++#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR__SHIFT                                             0x18
++#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR_MASK                                              0x00FFFFFFL
++#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR_MASK                                               0x1F000000L
++//WBSCL_VERT_FILTER_SCALE_RATIO
++#define WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO__SHIFT                                             0x0
++#define WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO_MASK                                               0x07FFFFFFL
++//WBSCL_VERT_FILTER_INIT_Y_RGB
++#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB__SHIFT                                          0x0
++#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB__SHIFT                                           0x18
++#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB_MASK                                            0x00FFFFFFL
++#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB_MASK                                             0x1F000000L
++//WBSCL_VERT_FILTER_INIT_CBCR
++#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR__SHIFT                                            0x0
++#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR__SHIFT                                             0x18
++#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR_MASK                                              0x00FFFFFFL
++#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR_MASK                                               0x1F000000L
++//WBSCL_ROUND_OFFSET
++#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB__SHIFT                                                   0x0
++#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR__SHIFT                                                    0x10
++#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB_MASK                                                     0x000003FFL
++#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR_MASK                                                      0x03FF0000L
++//WBSCL_OVERFLOW_STATUS
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG__SHIFT                                                0x0
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK__SHIFT                                                 0x8
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK__SHIFT                                                0xc
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS__SHIFT                                          0x10
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE__SHIFT                                            0x14
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG_MASK                                                  0x00000001L
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK_MASK                                                   0x00000100L
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK_MASK                                                  0x00001000L
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS_MASK                                            0x00010000L
++#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE_MASK                                              0x00100000L
++//WBSCL_COEF_RAM_CONFLICT_STATUS
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG__SHIFT                                       0x0
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK__SHIFT                                        0x8
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK__SHIFT                                       0xc
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS__SHIFT                                 0x10
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE__SHIFT                                   0x14
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG_MASK                                         0x00000001L
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK_MASK                                          0x00000100L
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK_MASK                                         0x00001000L
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS_MASK                                   0x00010000L
++#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE_MASK                                     0x00100000L
++//WBSCL_TEST_CNTL
++#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN__SHIFT                                                             0x4
++#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN__SHIFT                                                        0x8
++#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN_MASK                                                               0x00000010L
++#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN_MASK                                                          0x00000100L
++//WBSCL_TEST_CRC_RED
++#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK__SHIFT                                                    0x0
++#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED__SHIFT                                                     0x10
++#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK_MASK                                                      0x000003FFL
++#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED_MASK                                                       0xFFFF0000L
++//WBSCL_TEST_CRC_GREEN
++#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK__SHIFT                                                0x0
++#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN__SHIFT                                                 0x10
++#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK_MASK                                                  0x0000FFFFL
++#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN_MASK                                                   0xFFFF0000L
++//WBSCL_TEST_CRC_BLUE
++#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK__SHIFT                                                  0x0
++#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE__SHIFT                                                   0x10
++#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK_MASK                                                    0x000003FFL
++#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE_MASK                                                     0xFFFF0000L
++//WBSCL_BACKPRESSURE_CNT_EN
++#define WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN__SHIFT                                           0x0
++#define WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN_MASK                                             0x00000001L
++//WB_MCIF_BACKPRESSURE_CNT
++#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE__SHIFT                                           0x0
++#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE__SHIFT                                           0x10
++#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE_MASK                                             0x0000FFFFL
++#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE_MASK                                             0xFFFF0000L
++//WBSCL_CLAMP_Y_RGB
++#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_UPPER_Y_RGB__SHIFT                                                     0x0
++#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_LOWER_Y_RGB__SHIFT                                                     0x10
++#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_UPPER_Y_RGB_MASK                                                       0x000003FFL
++#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_LOWER_Y_RGB_MASK                                                       0x03FF0000L
++//WBSCL_CLAMP_CBCR
++#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_UPPER_CBCR__SHIFT                                                       0x0
++#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_LOWER_CBCR__SHIFT                                                       0x10
++#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_UPPER_CBCR_MASK                                                         0x000003FFL
++#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_LOWER_CBCR_MASK                                                         0x03FF0000L
++//WBSCL_OUTSIDE_PIX_STRATEGY
++#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY__SHIFT                                         0x0
++#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y__SHIFT                                              0x10
++#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY_MASK                                           0x00000001L
++#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y_MASK                                                0x03FF0000L
++//WBSCL_OUTSIDE_PIX_STRATEGY_CBCR
++#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_B_CB__SHIFT                                        0x0
++#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_R_CR__SHIFT                                        0x10
++#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_B_CB_MASK                                          0x000003FFL
++#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_R_CR_MASK                                          0x03FF0000L
++//WBSCL_DEBUG
++#define WBSCL_DEBUG__WBSCL_DEBUG__SHIFT                                                                       0x0
++#define WBSCL_DEBUG__WBSCL_DEBUG_MASK                                                                         0xFFFFFFFFL
++//WBSCL_TEST_DEBUG_INDEX
++#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_INDEX__SHIFT                                                 0x0
++#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_WRITE_EN__SHIFT                                              0x8
++#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_INDEX_MASK                                                   0x000000FFL
++#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_WRITE_EN_MASK                                                0x00000100L
++//WBSCL_TEST_DEBUG_DATA
++#define WBSCL_TEST_DEBUG_DATA__WBSCL_TEST_DEBUG_DATA__SHIFT                                                   0x0
++#define WBSCL_TEST_DEBUG_DATA__WBSCL_TEST_DEBUG_DATA_MASK                                                     0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON3_PERFCOUNTER_CNTL
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
++#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
++//DC_PERFMON3_PERFCOUNTER_CNTL2
++#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
++#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
++#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
++#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
++#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
++#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
++#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
++#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
++#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
++#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
++//DC_PERFMON3_PERFCOUNTER_STATE
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
++#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
++//DC_PERFMON3_PERFMON_CNTL
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
++#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
++//DC_PERFMON3_PERFMON_CNTL2
++#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
++#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
++#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
++#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
++#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
++#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
++#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
++#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
++//DC_PERFMON3_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
++#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
++//DC_PERFMON3_PERFMON_CVALUE_LOW
++#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
++#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
++//DC_PERFMON3_PERFMON_HI
++#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
++#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
++#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
++#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
++//DC_PERFMON3_PERFMON_LOW
++#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
++#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
++//MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT                                      0x0
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT                                   0x1
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT                                   0x4
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT                                  0x5
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT                             0x6
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT                           0x7
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT                                     0x8
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT                                             0x10
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT                                  0x18
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK                                        0x00000001L
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK                                     0x00000002L
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK                                     0x00000010L
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK                                    0x00000020L
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK                               0x00000040L
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK                             0x00000080L
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK                                       0x00000F00L
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK                                               0x000F0000L
++#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK                                    0x01000000L
++//MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R
++#define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT                                  0x0
++#define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK                                    0x00001FFFL
++//MCIF_WB0_MCIF_WB_BUFMGR_STATUS
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT                                  0x0
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT                                   0x1
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT                           0x2
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT                                         0x4
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT                                    0x7
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT                                          0x8
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT                                      0xc
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT                                        0x1c
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK                                    0x00000001L
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK                                     0x00000002L
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK                             0x00000004L
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK                                           0x00000070L
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK                                      0x00000080L
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK                                            0x00000F00L
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK                                        0x01FFF000L
++#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK                                          0x70000000L
++//MCIF_WB0_MCIF_WB_BUF_PITCH
++#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT                                             0x8
++#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT                                           0x18
++#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK                                               0x0000FF00L
++#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK                                             0xFF000000L
++//MCIF_WB0_MCIF_WB_BUF_1_STATUS
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT                                            0x0
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT                                         0x1
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT                                        0x2
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT                                          0x3
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT                                           0x4
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT                                              0x5
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT                                            0x8
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT                                           0xc
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT                                             0xf
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT                                        0x10
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT                                   0x1d
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT                                  0x1e
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT                                0x1f
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK                                              0x00000001L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK                                           0x00000002L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK                                          0x00000004L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK                                            0x00000008L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK                                             0x00000010L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK                                                0x000000E0L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK                                              0x00000F00L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK                                             0x00007000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK                                               0x00008000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK                                          0x1FFF0000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK                                     0x20000000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK                                    0x40000000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
++//MCIF_WB0_MCIF_WB_BUF_1_STATUS2
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT                                       0x0
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT                                      0xd
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT                                      0xe
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT                                  0xf
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT                                              0x10
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT                                        0x11
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT                                        0x12
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT                                         0x13
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK                                         0x00001FFFL
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK                                        0x00002000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK                                        0x00004000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK                                                0x00010000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK                                          0x00020000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK                                          0x00040000L
++#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK                                           0x00080000L
++//MCIF_WB0_MCIF_WB_BUF_2_STATUS
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT                                            0x0
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT                                         0x1
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT                                        0x2
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT                                          0x3
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT                                           0x4
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT                                              0x5
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT                                            0x8
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT                                           0xc
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT                                             0xf
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT                                        0x10
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT                                   0x1d
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT                                  0x1e
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT                                0x1f
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK                                              0x00000001L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK                                           0x00000002L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK                                          0x00000004L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK                                            0x00000008L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK                                             0x00000010L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK                                                0x000000E0L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK                                              0x00000F00L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK                                             0x00007000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK                                               0x00008000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK                                          0x1FFF0000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK                                     0x20000000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK                                    0x40000000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
++//MCIF_WB0_MCIF_WB_BUF_2_STATUS2
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT                                       0x0
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT                                      0xd
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT                                      0xe
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT                                  0xf
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT                                              0x10
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT                                        0x11
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT                                        0x12
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT                                         0x13
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK                                         0x00001FFFL
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK                                        0x00002000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK                                        0x00004000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK                                                0x00010000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK                                          0x00020000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK                                          0x00040000L
++#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK                                           0x00080000L
++//MCIF_WB0_MCIF_WB_BUF_3_STATUS
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT                                            0x0
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT                                         0x1
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT                                        0x2
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT                                          0x3
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT                                           0x4
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT                                              0x5
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT                                            0x8
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT                                           0xc
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT                                             0xf
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT                                        0x10
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT                                   0x1d
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT                                  0x1e
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT                                0x1f
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK                                              0x00000001L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK                                           0x00000002L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK                                          0x00000004L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK                                            0x00000008L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK                                             0x00000010L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK                                                0x000000E0L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK                                              0x00000F00L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK                                             0x00007000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK                                               0x00008000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK                                          0x1FFF0000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK                                     0x20000000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK                                    0x40000000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
++//MCIF_WB0_MCIF_WB_BUF_3_STATUS2
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT                                       0x0
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT                                      0xd
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT                                      0xe
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT                                  0xf
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT                                              0x10
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT                                        0x11
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT                                        0x12
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT                                         0x13
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK                                         0x00001FFFL
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK                                        0x00002000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK                                        0x00004000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK                                                0x00010000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK                                          0x00020000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK                                          0x00040000L
++#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK                                           0x00080000L
++//MCIF_WB0_MCIF_WB_BUF_4_STATUS
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT                                            0x0
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT                                         0x1
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT                                        0x2
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT                                          0x3
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT                                           0x4
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT                                              0x5
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT                                            0x8
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT                                           0xc
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT                                             0xf
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT                                        0x10
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT                                   0x1d
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT                                  0x1e
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT                                0x1f
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK                                              0x00000001L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK                                           0x00000002L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK                                          0x00000004L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK                                            0x00000008L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK                                             0x00000010L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK                                                0x000000E0L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK                                              0x00000F00L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK                                             0x00007000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK                                               0x00008000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK                                          0x1FFF0000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK                                     0x20000000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK                                    0x40000000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
++//MCIF_WB0_MCIF_WB_BUF_4_STATUS2
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT                                       0x0
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT                                      0xd
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT                                      0xe
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT                                  0xf
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT                                              0x10
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT                                        0x11
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT                                        0x12
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT                                         0x13
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK                                         0x00001FFFL
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK                                        0x00002000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK                                        0x00004000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK                                                0x00010000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK                                          0x00020000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK                                          0x00040000L
++#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK                                           0x00080000L
++//MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL
++#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT                         0x0
++#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT                                   0x16
++#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK                           0x00000003L
++#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK                                     0xFFC00000L
++//MCIF_WB0_MCIF_WB_SCLK_CHANGE
++#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT                                           0x0
++#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT                                       0x1
++#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK                                             0x00000001L
++#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK                                         0x0000000EL
++//MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX
++#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT                                    0x0
++#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT                                 0x8
++#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK                                      0x000000FFL
++#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK                                   0x00000100L
++//MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA
++#define MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT                                      0x0
++#define MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK                                        0xFFFFFFFFL
++//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT                                            0x0
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK                                              0xFFFFFFFFL
++//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT                              0x0
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT                                            0x0
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK                                              0xFFFFFFFFL
++//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT                              0x0
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT                                            0x0
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK                                              0xFFFFFFFFL
++//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT                              0x0
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT                                            0x0
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK                                              0xFFFFFFFFL
++//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT                              0x0
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT                                            0x0
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK                                              0xFFFFFFFFL
++//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT                              0x0
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT                                            0x0
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK                                              0xFFFFFFFFL
++//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT                              0x0
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT                                            0x0
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK                                              0xFFFFFFFFL
++//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT                              0x0
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT                                            0x0
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK                                              0xFFFFFFFFL
++//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT                              0x0
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT                            0x0
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT                                 0x4
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT                                0x5
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT                           0x6
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT                                   0x8
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT                                 0x10
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK                              0x00000001L
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK                                   0x00000010L
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK                                  0x00000020L
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK                             0x00000040L
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK                                     0x00000F00L
++#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK                                   0x1FFF0000L
++//MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT               0x0
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK                 0x0007FFFFL
++//MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT                     0x0
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT                                  0x1
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT                                 0x2
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT                            0x4
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK                       0x00000001L
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK                                    0x00000002L
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK                                   0x00000004L
++#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK                              0x00000070L
++//MCIF_WB0_MCIF_WB_WATERMARK
++#define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT                                              0x0
++#define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK                                                0x0000FFFFL
++//MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL
++#define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT                         0x0
++#define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK                           0x00000001L
++//MCIF_WB0_MCIF_WB_WARM_UP_CNTL
++#define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT                                       0x8
++#define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK                                         0x0000FF00L
++//MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL
++#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT                                0x0
++#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT                                   0x1
++#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK                                  0x00000001L
++#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK                                     0x00000002L
++//MCIF_WB0_MULTI_LEVEL_QOS_CTRL
++#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT                                       0x0
++#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK                                         0x003FFFFFL
++//MCIF_WB0_MCIF_WB_SECURITY_LEVEL
++#define MCIF_WB0_MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL__SHIFT                                        0x0
++#define MCIF_WB0_MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL_MASK                                          0x00000007L
++//MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE
++#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT                                          0x0
++#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK                                            0x000FFFFFL
++//MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE
++#define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT                                      0x0
++#define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK                                        0x000FFFFFL
++//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT                                  0x0
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK                                    0x000000FFL
++//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT                                  0x0
++#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK                                    0x000000FFL
++//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT                                  0x0
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK                                    0x000000FFL
++//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT                                  0x0
++#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK                                    0x000000FFL
++//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT                                  0x0
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK                                    0x000000FFL
++//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT                                  0x0
++#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK                                    0x000000FFL
++//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT                                  0x0
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK                                    0x000000FFL
++//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT                                  0x0
++#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK                                    0x000000FFL
++//MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION
++#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT                              0x0
++#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT                             0x10
++#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK                                0x00001FFFL
++#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
++//MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION
++#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT                              0x0
++#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT                             0x10
++#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK                                0x00001FFFL
++#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
++//MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION
++#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT                              0x0
++#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT                             0x10
++#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK                                0x00001FFFL
++#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
++//MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION
++#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT                              0x0
++#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT                             0x10
++#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK                                0x00001FFFL
++#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
++
++
++// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec
++//MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT                                      0x0
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT                                   0x1
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT                                   0x4
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT                                  0x5
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT                             0x6
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT                           0x7
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT                                     0x8
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT                                             0x10
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT                                  0x18
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK                                        0x00000001L
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK                                     0x00000002L
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK                                     0x00000010L
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK                                    0x00000020L
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK                               0x00000040L
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK                             0x00000080L
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK                                       0x00000F00L
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK                                               0x000F0000L
++#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK                                    0x01000000L
++//MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R
++#define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT                                  0x0
++#define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK                                    0x00001FFFL
++//MCIF_WB1_MCIF_WB_BUFMGR_STATUS
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT                                  0x0
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT                                   0x1
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT                           0x2
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT                                         0x4
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT                                    0x7
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT                                          0x8
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT                                      0xc
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT                                        0x1c
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK                                    0x00000001L
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK                                     0x00000002L
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK                             0x00000004L
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK                                           0x00000070L
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK                                      0x00000080L
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK                                            0x00000F00L
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK                                        0x01FFF000L
++#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK                                          0x70000000L
++//MCIF_WB1_MCIF_WB_BUF_PITCH
++#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT                                             0x8
++#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT                                           0x18
++#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK                                               0x0000FF00L
++#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK                                             0xFF000000L
++//MCIF_WB1_MCIF_WB_BUF_1_STATUS
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT                                            0x0
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT                                         0x1
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT                                        0x2
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT                                          0x3
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT                                           0x4
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT                                              0x5
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT                                            0x8
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT                                           0xc
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT                                             0xf
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT                                        0x10
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT                                   0x1d
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT                                  0x1e
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT                                0x1f
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK                                              0x00000001L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK                                           0x00000002L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK                                          0x00000004L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK                                            0x00000008L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK                                             0x00000010L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK                                                0x000000E0L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK                                              0x00000F00L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK                                             0x00007000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK                                               0x00008000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK                                          0x1FFF0000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK                                     0x20000000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK                                    0x40000000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
++//MCIF_WB1_MCIF_WB_BUF_1_STATUS2
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT                                       0x0
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT                                      0xd
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT                                      0xe
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT                                  0xf
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT                                              0x10
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT                                        0x11
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT                                        0x12
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT                                         0x13
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK                                         0x00001FFFL
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK                                        0x00002000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK                                        0x00004000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK                                                0x00010000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK                                          0x00020000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK                                          0x00040000L
++#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK                                           0x00080000L
++//MCIF_WB1_MCIF_WB_BUF_2_STATUS
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT                                            0x0
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT                                         0x1
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT                                        0x2
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT                                          0x3
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT                                           0x4
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT                                              0x5
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT                                            0x8
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT                                           0xc
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT                                             0xf
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT                                        0x10
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT                                   0x1d
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT                                  0x1e
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT                                0x1f
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK                                              0x00000001L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK                                           0x00000002L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK                                          0x00000004L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK                                            0x00000008L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK                                             0x00000010L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK                                                0x000000E0L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK                                              0x00000F00L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK                                             0x00007000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK                                               0x00008000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK                                          0x1FFF0000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK                                     0x20000000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK                                    0x40000000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
++//MCIF_WB1_MCIF_WB_BUF_2_STATUS2
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT                                       0x0
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT                                      0xd
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT                                      0xe
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT                                  0xf
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT                                              0x10
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT                                        0x11
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT                                        0x12
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT                                         0x13
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK                                         0x00001FFFL
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK                                        0x00002000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK                                        0x00004000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK                                                0x00010000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK                                          0x00020000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK                                          0x00040000L
++#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK                                           0x00080000L
++//MCIF_WB1_MCIF_WB_BUF_3_STATUS
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT                                            0x0
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT                                         0x1
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT                                        0x2
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT                                          0x3
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT                                           0x4
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT                                              0x5
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT                                            0x8
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT                                           0xc
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT                                             0xf
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT                                        0x10
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT                                   0x1d
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT                                  0x1e
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT                                0x1f
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK                                              0x00000001L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK                                           0x00000002L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK                                          0x00000004L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK                                            0x00000008L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK                                             0x00000010L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK                                                0x000000E0L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK                                              0x00000F00L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK                                             0x00007000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK                                               0x00008000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK                                          0x1FFF0000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK                                     0x20000000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK                                    0x40000000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
++//MCIF_WB1_MCIF_WB_BUF_3_STATUS2
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT                                       0x0
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT                                      0xd
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT                                      0xe
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT                                  0xf
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT                                              0x10
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT                                        0x11
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT                                        0x12
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT                                         0x13
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK                                         0x00001FFFL
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK                                        0x00002000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK                                        0x00004000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK                                                0x00010000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK                                          0x00020000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK                                          0x00040000L
++#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK                                           0x00080000L
++//MCIF_WB1_MCIF_WB_BUF_4_STATUS
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT                                            0x0
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT                                         0x1
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT                                        0x2
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT                                          0x3
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT                                           0x4
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT                                              0x5
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT                                            0x8
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT                                           0xc
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT                                             0xf
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT                                        0x10
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT                                   0x1d
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT                                  0x1e
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT                                0x1f
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK                                              0x00000001L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK                                           0x00000002L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK                                          0x00000004L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK                                            0x00000008L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK                                             0x00000010L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK                                                0x000000E0L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK                                              0x00000F00L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK                                             0x00007000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK                                               0x00008000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK                                          0x1FFF0000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK                                     0x20000000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK                                    0x40000000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
++//MCIF_WB1_MCIF_WB_BUF_4_STATUS2
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT                                       0x0
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT                                      0xd
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT                                      0xe
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT                                  0xf
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT                                              0x10
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT                                        0x11
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT                                        0x12
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT                                         0x13
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK                                         0x00001FFFL
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK                                        0x00002000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK                                        0x00004000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK                                                0x00010000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK                                          0x00020000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK                                          0x00040000L
++#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK                                           0x00080000L
++//MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL
++#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT                         0x0
++#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT                                   0x16
++#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK                           0x00000003L
++#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK                                     0xFFC00000L
++//MCIF_WB1_MCIF_WB_SCLK_CHANGE
++#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT                                           0x0
++#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT                                       0x1
++#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK                                             0x00000001L
++#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK                                         0x0000000EL
++//MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX
++#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT                                    0x0
++#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT                                 0x8
++#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK                                      0x000000FFL
++#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK                                   0x00000100L
++//MCIF_WB1_MCIF_WB_TEST_DEBUG_DATA
++#define MCIF_WB1_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT                                      0x0
++#define MCIF_WB1_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK                                        0xFFFFFFFFL
++//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT                                            0x0
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK                                              0xFFFFFFFFL
++//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT                              0x0
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT                                            0x0
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK                                              0xFFFFFFFFL
++//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT                              0x0
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT                                            0x0
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK                                              0xFFFFFFFFL
++//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT                              0x0
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT                                            0x0
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK                                              0xFFFFFFFFL
++//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT                              0x0
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT                                            0x0
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK                                              0xFFFFFFFFL
++//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT                              0x0
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT                                            0x0
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK                                              0xFFFFFFFFL
++//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT                              0x0
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT                                            0x0
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK                                              0xFFFFFFFFL
++//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT                              0x0
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT                                            0x0
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK                                              0xFFFFFFFFL
++//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT                              0x0
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT                            0x0
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT                                 0x4
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT                                0x5
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT                           0x6
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT                                   0x8
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT                                 0x10
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK                              0x00000001L
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK                                   0x00000010L
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK                                  0x00000020L
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK                             0x00000040L
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK                                     0x00000F00L
++#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK                                   0x1FFF0000L
++//MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT               0x0
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK                 0x0007FFFFL
++//MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT                     0x0
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT                                  0x1
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT                                 0x2
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT                            0x4
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK                       0x00000001L
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK                                    0x00000002L
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK                                   0x00000004L
++#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK                              0x00000070L
++//MCIF_WB1_MCIF_WB_WATERMARK
++#define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT                                              0x0
++#define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK                                                0x0000FFFFL
++//MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL
++#define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT                         0x0
++#define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK                           0x00000001L
++//MCIF_WB1_MCIF_WB_WARM_UP_CNTL
++#define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT                                       0x8
++#define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK                                         0x0000FF00L
++//MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL
++#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT                                0x0
++#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT                                   0x1
++#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK                                  0x00000001L
++#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK                                     0x00000002L
++//MCIF_WB1_MULTI_LEVEL_QOS_CTRL
++#define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT                                       0x0
++#define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK                                         0x003FFFFFL
++//MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE
++#define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT                                          0x0
++#define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK                                            0x000FFFFFL
++//MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE
++#define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT                                      0x0
++#define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK                                        0x000FFFFFL
++//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT                                  0x0
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK                                    0x000000FFL
++//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT                                  0x0
++#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK                                    0x000000FFL
++//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT                                  0x0
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK                                    0x000000FFL
++//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT                                  0x0
++#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK                                    0x000000FFL
++//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT                                  0x0
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK                                    0x000000FFL
++//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT                                  0x0
++#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK                                    0x000000FFL
++//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT                                  0x0
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK                                    0x000000FFL
++//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT                                  0x0
++#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK                                    0x000000FFL
++//MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION
++#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT                              0x0
++#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT                             0x10
++#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK                                0x00001FFFL
++#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
++//MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION
++#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT                              0x0
++#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT                             0x10
++#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK                                0x00001FFFL
++#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
++//MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION
++#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT                              0x0
++#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT                             0x10
++#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK                                0x00001FFFL
++#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
++//MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION
++#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT                              0x0
++#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT                             0x10
++#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK                                0x00001FFFL
++#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
++
++
++// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
++//WBIF0_MISC_CTRL
++#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT                                             0x0
++#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT                                                     0x10
++#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK                                               0x000003FFL
++#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK                                                       0x00010000L
++//WBIF0_SMU_WM_CONTROL
++#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_SEL__SHIFT                                                      0x14
++#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_REQ__SHIFT                                                      0x16
++#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT                                              0x18
++#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT                                           0x19
++#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_SEL_MASK                                                        0x00300000L
++#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_REQ_MASK                                                        0x00400000L
++#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK                                                0x01000000L
++#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK                                             0x02000000L
++//WBIF0_PHASE0_OUTSTANDING_COUNTER
++#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT                          0x0
++#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL
++//WBIF0_PHASE1_OUTSTANDING_COUNTER
++#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT                          0x0
++#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL
++//VGA_SRC_SPLIT_CNTL
++#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT                                                              0x0
++#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK                                                                0x00000003L
++//MMHUBBUB_MEM_PWR_STATUS
++#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT                                         0x0
++#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT                                         0x2
++#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT                                       0x4
++#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT                                       0x6
++#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT                                                     0x1f
++#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK                                           0x00000003L
++#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK                                           0x0000000CL
++#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK                                         0x00000030L
++#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK                                         0x000000C0L
++#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK                                                       0x80000000L
++//MMHUBBUB_MEM_PWR_CNTL
++#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT                                                       0x0
++#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT                                                         0x1
++#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT                                                 0x2
++#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT                                                   0x4
++#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT                                              0x5
++#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT                                               0x7
++#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT                                             0x8
++#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK                                                         0x00000001L
++#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK                                                           0x00000002L
++#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK                                                   0x0000000CL
++#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK                                                     0x00000010L
++#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK                                                0x00000060L
++#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK                                                 0x00000080L
++#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK                                               0x00000100L
++//MMHUBBUB_CLOCK_CNTL
++#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0
++#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT                                               0x5
++#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS__SHIFT                                                  0x6
++#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS__SHIFT                                                   0x7
++#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT                                                    0x8
++#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT                                                  0x9
++#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT                                                   0xa
++#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL
++#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK                                                 0x00000020L
++#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS_MASK                                                    0x00000040L
++#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS_MASK                                                     0x00000080L
++#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK                                                      0x00000100L
++#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK                                                    0x00000200L
++#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK                                                     0x00000400L
++//MMHUBBUB_SOFT_RESET
++#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET__SHIFT                                                            0x0
++#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET__SHIFT                                                          0x1
++#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT                                                          0x2
++#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT                                                          0x8
++#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET_MASK                                                              0x00000001L
++#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET_MASK                                                            0x00000002L
++#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK                                                            0x00000004L
++#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK                                                            0x00000100L
++//DMU_IF_ERR_STATUS
++#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT                                                      0x0
++#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT                                                  0x4
++#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK                                                        0x00000001L
++#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK                                                    0x00000010L
++//MMHUBBUB_CLIENT_UNIT_ID
++#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID__SHIFT                                                           0x0
++#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT                                                         0x8
++#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID_MASK                                                             0x0000003FL
++#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK                                                           0x00003F00L
++
++
++// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
++//MCIF_CONTROL
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT                                                   0x1e
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT                                              0x1f
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK                                                     0x40000000L
++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK                                                0x80000000L
++//MCIF_WRITE_COMBINE_CONTROL
++#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT                                         0x0
++#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK                                           0x000003FFL
++//MCIF_PHASE0_OUTSTANDING_COUNTER
++#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT                               0x0
++#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
++//MCIF_PHASE1_OUTSTANDING_COUNTER
++#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT                               0x0
++#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
++//MCIF_PHASE2_OUTSTANDING_COUNTER
++#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT                               0x0
++#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
++
++
++// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON4_PERFCOUNTER_CNTL
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
++#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
++//DC_PERFMON4_PERFCOUNTER_CNTL2
++#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
++#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
++#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
++#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
++#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
++#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
++#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
++#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
++#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
++#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
++//DC_PERFMON4_PERFCOUNTER_STATE
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
++#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
++//DC_PERFMON4_PERFMON_CNTL
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
++#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
++//DC_PERFMON4_PERFMON_CNTL2
++#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
++#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
++#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
++#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
++#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
++#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
++#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
++#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
++//DC_PERFMON4_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
++#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
++//DC_PERFMON4_PERFMON_CVALUE_LOW
++#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
++#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
++//DC_PERFMON4_PERFMON_HI
++#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
++#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
++#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
++#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
++//DC_PERFMON4_PERFMON_LOW
++#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
++#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0stream0_dispdec
++//AZF0STREAM0_AZALIA_STREAM_INDEX
++#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
++#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
++#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
++#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
++//AZF0STREAM0_AZALIA_STREAM_DATA
++#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
++#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0stream1_dispdec
++//AZF0STREAM1_AZALIA_STREAM_INDEX
++#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
++#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
++#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
++#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
++//AZF0STREAM1_AZALIA_STREAM_DATA
++#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
++#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0stream2_dispdec
++//AZF0STREAM2_AZALIA_STREAM_INDEX
++#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
++#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
++#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
++#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
++//AZF0STREAM2_AZALIA_STREAM_DATA
++#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
++#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0stream3_dispdec
++//AZF0STREAM3_AZALIA_STREAM_INDEX
++#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
++#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
++#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
++#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
++//AZF0STREAM3_AZALIA_STREAM_DATA
++#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
++#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0stream4_dispdec
++//AZF0STREAM4_AZALIA_STREAM_INDEX
++#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
++#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
++#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
++#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
++//AZF0STREAM4_AZALIA_STREAM_DATA
++#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
++#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0stream5_dispdec
++//AZF0STREAM5_AZALIA_STREAM_INDEX
++#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
++#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
++#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
++#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
++//AZF0STREAM5_AZALIA_STREAM_DATA
++#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
++#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0stream6_dispdec
++//AZF0STREAM6_AZALIA_STREAM_INDEX
++#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
++#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
++#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
++#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
++//AZF0STREAM6_AZALIA_STREAM_DATA
++#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
++#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0stream7_dispdec
++//AZF0STREAM7_AZALIA_STREAM_INDEX
++#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
++#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
++#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
++#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
++//AZF0STREAM7_AZALIA_STREAM_DATA
++#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
++#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_az_misc_dispdec
++//AZ_CLOCK_CNTL
++#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT                                                       0x0
++#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT                                                              0x8
++#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT                                                         0x10
++#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT                                                              0x18
++#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK                                                         0x00000001L
++#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK                                                                0x00000100L
++#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK                                                           0x00010000L
++#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK                                                                0x1F000000L
++
++
++// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON5_PERFCOUNTER_CNTL
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
++#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
++//DC_PERFMON5_PERFCOUNTER_CNTL2
++#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
++#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
++#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
++#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
++#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
++#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
++#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
++#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
++#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
++#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
++//DC_PERFMON5_PERFCOUNTER_STATE
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
++#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
++//DC_PERFMON5_PERFMON_CNTL
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
++#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
++//DC_PERFMON5_PERFMON_CNTL2
++#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
++#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
++#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
++#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
++#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
++#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
++#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
++#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
++//DC_PERFMON5_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
++#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
++//DC_PERFMON5_PERFMON_CVALUE_LOW
++#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
++#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
++//DC_PERFMON5_PERFMON_HI
++#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
++#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
++#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
++#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
++//DC_PERFMON5_PERFMON_LOW
++#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
++#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0controller_dispdec
++//AZALIA_CONTROLLER_CLOCK_GATING
++#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT                                            0x0
++#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT                                                 0x4
++#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK                                              0x00000001L
++#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK                                                   0x00000010L
++//AZALIA_AUDIO_DTO
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT                                                       0x0
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT                                                      0x10
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK                                                         0x0000FFFFL
++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK                                                        0xFFFF0000L
++//AZALIA_AUDIO_DTO_CONTROL
++#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT                                               0x8
++#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK                                                 0x00000300L
++//AZALIA_SOCCLK_CONTROL
++#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT                                  0x1
++#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK                                    0x00000002L
++//AZALIA_UNDERFLOW_FILLER_SAMPLE
++#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT                                 0x0
++#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK                                   0xFFFFFFFFL
++//AZALIA_DATA_DMA_CONTROL
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT                                                    0x0
++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT                                              0x2
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT                                                  0x4
++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT                                            0x6
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT                                          0x10
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT                                              0x11
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK                                                      0x00000003L
++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK                                                0x0000000CL
++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK                                                    0x00000030L
++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK                                              0x000000C0L
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK                                            0x00010000L
++#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK                                                0x00020000L
++//AZALIA_BDL_DMA_CONTROL
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT                                                      0x0
++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT                                                0x2
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT                                                    0x4
++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT                                              0x6
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK                                                        0x00000003L
++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK                                                  0x0000000CL
++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK                                                      0x00000030L
++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK                                                0x000000C0L
++//AZALIA_RIRB_AND_DP_CONTROL
++#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT                                                     0x0
++#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT                                                   0x4
++#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT                                             0x5
++#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK                                                       0x00000001L
++#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK                                                     0x00000010L
++#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK                                               0x000001E0L
++//AZALIA_CORB_DMA_CONTROL
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT                                                    0x0
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT                                                  0x4
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK                                                      0x00000001L
++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK                                                    0x00000010L
++//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER
++#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT            0x0
++#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK              0xFFFFFFFFL
++//AZALIA_CYCLIC_BUFFER_SYNC
++#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT                                           0x0
++#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK                                             0x00000001L
++//AZALIA_GLOBAL_CAPABILITIES
++#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT                               0x1
++#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK                                 0x00000006L
++//AZALIA_OUTPUT_PAYLOAD_CAPABILITY
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                                    0x0
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                                   0x10
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                                      0x0000FFFFL
++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                                     0xFFFF0000L
++//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT                                     0x0
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT                                    0x8
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT                               0x10
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK                                       0x000000FFL
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK                                      0x00000100L
++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK                                 0x00FF0000L
++//AZALIA_INPUT_PAYLOAD_CAPABILITY
++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                                      0x0
++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                                     0x10
++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                        0x0000FFFFL
++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                                       0xFFFF0000L
++//AZALIA_INPUT_CRC0_CONTROL0
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L
++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L
++//AZALIA_INPUT_CRC0_CONTROL1
++#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0
++#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL
++//AZALIA_INPUT_CRC0_CONTROL2
++#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0
++#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL
++//AZALIA_INPUT_CRC0_CONTROL3
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L
++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L
++//AZALIA_INPUT_CRC0_RESULT
++#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0
++#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL
++//AZALIA_INPUT_CRC1_CONTROL0
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L
++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L
++//AZALIA_INPUT_CRC1_CONTROL1
++#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0
++#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL
++//AZALIA_INPUT_CRC1_CONTROL2
++#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0
++#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL
++//AZALIA_INPUT_CRC1_CONTROL3
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L
++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L
++//AZALIA_INPUT_CRC1_RESULT
++#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0
++#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL
++//AZALIA_CRC0_CONTROL0
++#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT                                                                   0x0
++#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4
++#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8
++#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc
++#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK                                                                     0x00000001L
++#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L
++#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L
++#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L
++//AZALIA_CRC0_CONTROL1
++#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0
++#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL
++//AZALIA_CRC0_CONTROL2
++#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0
++#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL
++//AZALIA_CRC0_CONTROL3
++#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0
++#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4
++#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8
++#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L
++#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L
++#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L
++//AZALIA_CRC0_RESULT
++#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT                                                                 0x0
++#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL
++//AZALIA_CRC1_CONTROL0
++#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT                                                                   0x0
++#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4
++#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8
++#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc
++#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK                                                                     0x00000001L
++#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L
++#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L
++#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L
++//AZALIA_CRC1_CONTROL1
++#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0
++#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL
++//AZALIA_CRC1_CONTROL2
++#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0
++#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL
++//AZALIA_CRC1_CONTROL3
++#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0
++#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4
++#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8
++#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L
++#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L
++#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L
++//AZALIA_CRC1_RESULT
++#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT                                                                 0x0
++#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL
++//AZALIA_MEM_PWR_CTRL
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT                                                          0x0
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT                                                            0x2
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT                                            0x3
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT                                              0x5
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT                                            0x6
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT                                              0x8
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT                                            0x9
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT                                              0xb
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT                                            0xc
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT                                              0xe
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT                                            0xf
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT                                              0x11
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT                                            0x12
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT                                              0x14
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT                                                       0x1c
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK                                                            0x00000003L
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK                                                              0x00000004L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK                                              0x00000018L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK                                                0x00000020L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK                                              0x000000C0L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK                                                0x00000100L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK                                              0x00000600L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK                                                0x00000800L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK                                              0x00003000L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK                                                0x00004000L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK                                              0x00018000L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK                                                0x00020000L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK                                              0x000C0000L
++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK                                                0x00100000L
++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK                                                         0x30000000L
++//AZALIA_MEM_PWR_STATUS
++#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT                                                        0x0
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT                                          0x2
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT                                          0x4
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT                                          0x6
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT                                          0x8
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT                                          0xa
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT                                          0xc
++#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK                                                          0x00000003L
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK                                            0x0000000CL
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK                                            0x00000030L
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK                                            0x000000C0L
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK                                            0x00000300L
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK                                            0x00000C00L
++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK                                            0x00003000L
++
++
++// addressBlock: dce_dc_hda_azf0root_dispdec
++//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL
++//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0
++#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL
++//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT                                       0x0
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT                                0x4
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK                                         0x00000007L
++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK                                  0x00000070L
++//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL
++#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT                        0x0
++#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK                          0x0000003FL
++//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL
++//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L
++//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL
++//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L
++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L
++//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L
++//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L
++//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L
++//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0
++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL
++//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT                                           0x0
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                           0x4
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK                                             0x00000007L
++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                             0x00000010L
++//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY
++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT                               0x0
++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT               0x4
++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK                                 0x00000007L
++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                 0x00000010L
++//AZALIA_F0_GTC_GROUP_OFFSET0
++#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT                                                 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK                                                   0xFFFFFFFFL
++//AZALIA_F0_GTC_GROUP_OFFSET1
++#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT                                                 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK                                                   0xFFFFFFFFL
++//AZALIA_F0_GTC_GROUP_OFFSET2
++#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT                                                 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK                                                   0xFFFFFFFFL
++//AZALIA_F0_GTC_GROUP_OFFSET3
++#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT                                                 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK                                                   0xFFFFFFFFL
++//AZALIA_F0_GTC_GROUP_OFFSET4
++#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT                                                 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK                                                   0xFFFFFFFFL
++//AZALIA_F0_GTC_GROUP_OFFSET5
++#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT                                                 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK                                                   0xFFFFFFFFL
++//AZALIA_F0_GTC_GROUP_OFFSET6
++#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT                                                 0x0
++#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK                                                   0xFFFFFFFFL
++//REG_DC_AUDIO_PORT_CONNECTIVITY
++#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT                                          0x0
++#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                          0x4
++#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK                                            0x00000007L
++#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                            0x00000010L
++//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY
++#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT                              0x0
++#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT              0x4
++#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK                                0x00000007L
++#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                0x00000010L
++
++
++// addressBlock: dce_dc_hda_azf0stream8_dispdec
++//AZF0STREAM8_AZALIA_STREAM_INDEX
++#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
++#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
++#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
++#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
++//AZF0STREAM8_AZALIA_STREAM_DATA
++#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
++#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0stream9_dispdec
++//AZF0STREAM9_AZALIA_STREAM_INDEX
++#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
++#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
++#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
++#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
++//AZF0STREAM9_AZALIA_STREAM_DATA
++#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
++#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0stream10_dispdec
++//AZF0STREAM10_AZALIA_STREAM_INDEX
++#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
++#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
++#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
++#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
++//AZF0STREAM10_AZALIA_STREAM_DATA
++#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
++#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0stream11_dispdec
++//AZF0STREAM11_AZALIA_STREAM_INDEX
++#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
++#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
++#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
++#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
++//AZF0STREAM11_AZALIA_STREAM_DATA
++#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
++#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0stream12_dispdec
++//AZF0STREAM12_AZALIA_STREAM_INDEX
++#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
++#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
++#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
++#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
++//AZF0STREAM12_AZALIA_STREAM_DATA
++#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
++#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0stream13_dispdec
++//AZF0STREAM13_AZALIA_STREAM_INDEX
++#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
++#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
++#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
++#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
++//AZF0STREAM13_AZALIA_STREAM_DATA
++#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
++#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0stream14_dispdec
++//AZF0STREAM14_AZALIA_STREAM_INDEX
++#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
++#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
++#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
++#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
++//AZF0STREAM14_AZALIA_STREAM_DATA
++#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
++#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0stream15_dispdec
++//AZF0STREAM15_AZALIA_STREAM_INDEX
++#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
++#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
++#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
++#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
++//AZF0STREAM15_AZALIA_STREAM_DATA
++#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
++#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
++//DCHUBBUB_SDPIF_CFG0
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT                                                  0x0
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT                                                         0x1
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT                                                0x3
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT                                                     0x6
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT                                                    0xa
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT                                               0xb
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT                                              0xc
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT                                                 0xd
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT                                                       0xe
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT                                                        0xf
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT                                             0x19
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK                                                    0x00000001L
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK                                                           0x00000006L
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK                                                  0x00000038L
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK                                                       0x000003C0L
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK                                                      0x00000400L
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK                                                 0x00000800L
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK                                                0x00001000L
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK                                                   0x00002000L
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK                                                         0x00004000L
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK                                                          0x00008000L
++#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK                                               0x7E000000L
++//VM_REQUEST_PHYSICAL
++#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT                                                      0x0
++#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT                                                      0x3
++#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK                                                        0x00000001L
++#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK                                                        0x00000008L
++//DCHUBBUB_FORCE_IO_STATUS_0
++#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT                                              0x0
++#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT                                       0x1
++#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT                                        0x2
++#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT                                      0x3
++#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT                                 0x7
++#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT                                      0xa
++#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK                                                0x00000001L
++#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK                                         0x00000002L
++#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK                                          0x00000004L
++#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK                                        0x00000078L
++#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK                                   0x00000380L
++#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK                                        0xFFFFFC00L
++//DCHUBBUB_FORCE_IO_STATUS_1
++#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT                                      0x0
++#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK                                        0x001FFFFFL
++//DCN_VM_FB_LOCATION_BASE
++#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                               0x0
++#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                 0x00FFFFFFL
++//DCN_VM_FB_LOCATION_TOP
++#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                 0x0
++#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                   0x00FFFFFFL
++//DCN_VM_FB_OFFSET
++#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                    0x0
++#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK                                                                      0x00FFFFFFL
++//DCN_VM_AGP_BOT
++#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT                                                                        0x0
++#define DCN_VM_AGP_BOT__AGP_BOT_MASK                                                                          0x00FFFFFFL
++//DCN_VM_AGP_TOP
++#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT                                                                        0x0
++#define DCN_VM_AGP_TOP__AGP_TOP_MASK                                                                          0x00FFFFFFL
++//DCN_VM_AGP_BASE
++#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT                                                                      0x0
++#define DCN_VM_AGP_BASE__AGP_BASE_MASK                                                                        0x00FFFFFFL
++//DCN_VM_LOCAL_HBM_ADDRESS_START
++#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT                                                  0x0
++#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK                                                    0x000FFFFFL
++//DCN_VM_LOCAL_HBM_ADDRESS_END
++#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT                                                      0x0
++#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK                                                        0x000FFFFFL
++//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
++#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                       0x0
++#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                         0x00000001L
++//DCHUBBUB_SDPIF_PIPE_SEC_LVL
++#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT                                               0x0
++#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT                                               0x3
++#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL__SHIFT                                               0x6
++#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL__SHIFT                                               0x9
++#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK                                                 0x00000007L
++#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK                                                 0x00000038L
++#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL_MASK                                                 0x000001C0L
++#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL_MASK                                                 0x00000E00L
++//DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL
++#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL__SHIFT                                 0x0
++#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL__SHIFT                                 0x3
++#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL__SHIFT                                 0x6
++#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL__SHIFT                                 0x9
++#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL_MASK                                   0x00000007L
++#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL_MASK                                   0x00000038L
++#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL_MASK                                   0x000001C0L
++#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL_MASK                                   0x00000E00L
++//DCHUBBUB_SDPIF_MEM_PWR_CTRL
++#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT                                      0x0
++#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT                                        0x2
++#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK                                        0x00000003L
++#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK                                          0x00000004L
++//DCHUBBUB_SDPIF_MEM_PWR_STATUS
++#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT                                    0x0
++#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK                                      0x00000003L
++//DCHUBBUB_SDPIF_CFG1
++#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT                                                 0x0
++#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT                                                    0x1
++#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT                                              0x2
++#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT                                                         0x8
++#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK                                                   0x00000001L
++#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK                                                      0x00000002L
++#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK                                                0x00000004L
++#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK                                                           0x00000100L
++//DCHUBBUB_SDPIF_CFG2
++#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT                                                         0x0
++#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL__SHIFT                                                      0x8
++#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT                                                     0x10
++#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK                                                           0x00000001L
++#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL_MASK                                                        0x00000700L
++#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK                                                       0x01FF0000L
++
++
++// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
++//DCHUBBUB_RET_PATH_DCC_CFG
++#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN__SHIFT                                                 0x0
++#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN_MASK                                                   0x00000001L
++//DCHUBBUB_RET_PATH_DCC_CFG0_0
++#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0__SHIFT                                              0x0
++#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0_MASK                                                0xFFFFFFFFL
++//DCHUBBUB_RET_PATH_DCC_CFG0_1
++#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1__SHIFT                                              0x0
++#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1_MASK                                                0xFFFFFFFFL
++//DCHUBBUB_RET_PATH_DCC_CFG1_0
++#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0__SHIFT                                              0x0
++#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0_MASK                                                0xFFFFFFFFL
++//DCHUBBUB_RET_PATH_DCC_CFG1_1
++#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1__SHIFT                                              0x0
++#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1_MASK                                                0xFFFFFFFFL
++//DCHUBBUB_RET_PATH_DCC_CFG2_0
++#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0__SHIFT                                              0x0
++#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0_MASK                                                0xFFFFFFFFL
++//DCHUBBUB_RET_PATH_DCC_CFG2_1
++#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1__SHIFT                                              0x0
++#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1_MASK                                                0xFFFFFFFFL
++//DCHUBBUB_RET_PATH_DCC_CFG3_0
++#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0__SHIFT                                              0x0
++#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0_MASK                                                0xFFFFFFFFL
++//DCHUBBUB_RET_PATH_DCC_CFG3_1
++#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1__SHIFT                                              0x0
++#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1_MASK                                                0xFFFFFFFFL
++//DCHUBBUB_RET_PATH_DCC_CFG4_0
++#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0__SHIFT                                              0x0
++#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0_MASK                                                0xFFFFFFFFL
++//DCHUBBUB_RET_PATH_DCC_CFG4_1
++#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1__SHIFT                                              0x0
++#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1_MASK                                                0xFFFFFFFFL
++//DCHUBBUB_RET_PATH_DCC_CFG5_0
++#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0__SHIFT                                              0x0
++#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0_MASK                                                0xFFFFFFFFL
++//DCHUBBUB_RET_PATH_DCC_CFG5_1
++#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1__SHIFT                                              0x0
++#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1_MASK                                                0xFFFFFFFFL
++//DCHUBBUB_RET_PATH_DCC_CFG6_0
++#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0__SHIFT                                              0x0
++#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0_MASK                                                0xFFFFFFFFL
++//DCHUBBUB_RET_PATH_DCC_CFG6_1
++#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1__SHIFT                                              0x0
++#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1_MASK                                                0xFFFFFFFFL
++//DCHUBBUB_RET_PATH_DCC_CFG7_0
++#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0__SHIFT                                              0x0
++#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0_MASK                                                0xFFFFFFFFL
++//DCHUBBUB_RET_PATH_DCC_CFG7_1
++#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1__SHIFT                                              0x0
++#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1_MASK                                                0xFFFFFFFFL
++//DCHUBBUB_RET_PATH_MEM_PWR_CTRL
++#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT                                0x0
++#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT                                  0x2
++#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK                                  0x00000003L
++#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK                                    0x00000004L
++//DCHUBBUB_RET_PATH_MEM_PWR_STATUS
++#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT                              0x0
++#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK                                0x00000003L
++//DCHUBBUB_CRC_CTRL
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT                                                             0x0
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT                                                        0x1
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT                                              0x2
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT                                              0x3
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT                                                       0x4
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT                                                       0x6
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT                                                       0x8
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT                                                       0xc
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_MASK_SURF_SEL_MSB__SHIFT                                              0xf
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT                                                   0x14
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK                                                               0x00000001L
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK                                                          0x00000002L
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK                                                0x00000004L
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK                                                0x00000008L
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK                                                         0x00000030L
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK                                                         0x000000C0L
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK                                                         0x00000F00L
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK                                                         0x00007000L
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_MASK_SURF_SEL_MSB_MASK                                                0x00008000L
++#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK                                                     0x00100000L
++//DCHUBBUB_CRC0_VAL_R_G
++#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT                                                      0x0
++#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT                                                       0x10
++#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK                                                        0x0000FFFFL
++#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK                                                         0xFFFF0000L
++//DCHUBBUB_CRC0_VAL_B_A
++#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT                                                      0x0
++#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT                                                     0x10
++#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK                                                        0x0000FFFFL
++#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK                                                       0xFFFF0000L
++//DCHUBBUB_CRC1_VAL_R_G
++#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT                                                      0x0
++#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT                                                       0x10
++#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK                                                        0x0000FFFFL
++#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK                                                         0xFFFF0000L
++//DCHUBBUB_CRC1_VAL_B_A
++#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT                                                      0x0
++#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT                                                     0x10
++#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK                                                        0x0000FFFFL
++#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK                                                       0xFFFF0000L
++
++
++// addressBlock: dce_dc_dchubbub_hubbub_dispdec
++//DCHUBBUB_ARB_DF_REQ_OUTSTAND
++#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT                                    0x0
++#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT                                    0xc
++#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD__SHIFT                   0x17
++#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK                                      0x000001FFL
++#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK                                      0x001FF000L
++#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD_MASK                     0xFF800000L
++//DCHUBBUB_ARB_SAT_LEVEL
++#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT                                                 0x0
++#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK                                                   0xFFFFFFFFL
++//DCHUBBUB_ARB_QOS_FORCE
++#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT                                           0x0
++#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT                                          0x8
++#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK                                             0x0000000FL
++#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK                                            0x00000100L
++//DCHUBBUB_ARB_DRAM_STATE_CNTL
++#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT                      0x0
++#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT                     0x1
++#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT                     0x4
++#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT                    0x5
++#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST__SHIFT  0x8
++#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL__SHIFT  0x9
++#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK                        0x00000001L
++#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK                       0x00000002L
++#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK                       0x00000010L
++#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK                      0x00000020L
++#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_MASK  0x00000100L
++#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL_MASK  0x00000200L
++//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A
++#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT                   0x0
++#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A__SHIFT                 0x10
++#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK                     0x00003FFFL
++#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A_MASK                   0x3FFF0000L
++//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A
++#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT             0x0
++#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK               0x00003FFFL
++//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A
++#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT               0x0
++#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A__SHIFT        0x10
++#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK                 0x0000FFFFL
++#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A_MASK          0xFFFF0000L
++//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A
++#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT                 0x0
++#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A__SHIFT          0x10
++#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK                   0x0000FFFFL
++#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A_MASK            0xFFFF0000L
++//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A
++#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT  0x0
++#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT  0x10
++#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK   0x0000FFFFL
++#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK  0xFFFF0000L
++//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B
++#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT                   0x0
++#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B__SHIFT                 0x10
++#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK                     0x00003FFFL
++#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B_MASK                   0x3FFF0000L
++//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B
++#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT             0x0
++#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK               0x00003FFFL
++//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B
++#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT               0x0
++#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B__SHIFT        0x10
++#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK                 0x0000FFFFL
++#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B_MASK          0xFFFF0000L
++//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B
++#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT                 0x0
++#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B__SHIFT          0x10
++#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK                   0x0000FFFFL
++#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B_MASK            0xFFFF0000L
++//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B
++#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT  0x0
++#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT  0x10
++#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK   0x0000FFFFL
++#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK  0xFFFF0000L
++//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C
++#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT                   0x0
++#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C__SHIFT                 0x10
++#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK                     0x00003FFFL
++#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C_MASK                   0x3FFF0000L
++//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C
++#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT             0x0
++#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK               0x00003FFFL
++//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C
++#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT               0x0
++#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C__SHIFT        0x10
++#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK                 0x0000FFFFL
++#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C_MASK          0xFFFF0000L
++//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C
++#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT                 0x0
++#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C__SHIFT          0x10
++#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK                   0x0000FFFFL
++#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C_MASK            0xFFFF0000L
++//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C
++#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT  0x0
++#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT  0x10
++#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK   0x0000FFFFL
++#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK  0xFFFF0000L
++//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D
++#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT                   0x0
++#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D__SHIFT                 0x10
++#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK                     0x00003FFFL
++#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D_MASK                   0x3FFF0000L
++//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D
++#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT             0x0
++#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK               0x00003FFFL
++//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D
++#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT               0x0
++#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D__SHIFT        0x10
++#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK                 0x0000FFFFL
++#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D_MASK          0xFFFF0000L
++//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
++#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT                 0x0
++#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D__SHIFT          0x10
++#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK                   0x0000FFFFL
++#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D_MASK            0xFFFF0000L
++//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D
++#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT  0x0
++#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT  0x10
++#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK   0x0000FFFFL
++#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK  0xFFFF0000L
++//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL
++#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT                       0x0
++#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT       0x4
++#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT        0x5
++#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT                      0x8
++#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK                         0x00000003L
++#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK         0x00000010L
++#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK          0x00000020L
++#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK                        0x00000100L
++//DCHUBBUB_ARB_TIMEOUT_ENABLE
++#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT                                       0x0
++#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK                                         0x00000001L
++//DCHUBBUB_GLOBAL_TIMER_CNTL
++#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT                                       0x0
++#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT                                       0xc
++#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT                                         0x10
++#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK                                         0x0000000FL
++#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK                                         0x00001000L
++#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK                                           0xFFFF0000L
++//SURFACE_CHECK0_ADDRESS_LSB
++#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT                                         0x0
++#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
++//SURFACE_CHECK0_ADDRESS_MSB
++#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT                                         0x0
++#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT                                             0x1f
++#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK                                           0x0000FFFFL
++#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK                                               0x80000000L
++//SURFACE_CHECK1_ADDRESS_LSB
++#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT                                         0x0
++#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
++//SURFACE_CHECK1_ADDRESS_MSB
++#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT                                         0x0
++#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT                                             0x1f
++#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK                                           0x0000FFFFL
++#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK                                               0x80000000L
++//SURFACE_CHECK2_ADDRESS_LSB
++#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT                                         0x0
++#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
++//SURFACE_CHECK2_ADDRESS_MSB
++#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT                                         0x0
++#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT                                             0x1f
++#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK                                           0x0000FFFFL
++#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK                                               0x80000000L
++//SURFACE_CHECK3_ADDRESS_LSB
++#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT                                         0x0
++#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
++//SURFACE_CHECK3_ADDRESS_MSB
++#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT                                         0x0
++#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT                                             0x1f
++#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK                                           0x0000FFFFL
++#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK                                               0x80000000L
++//VTG0_CONTROL
++#define VTG0_CONTROL__VTG0_FP2__SHIFT                                                                         0x0
++#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT                                                                 0x10
++#define VTG0_CONTROL__VTG0_ENABLE__SHIFT                                                                      0x1f
++#define VTG0_CONTROL__VTG0_FP2_MASK                                                                           0x00007FFFL
++#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
++#define VTG0_CONTROL__VTG0_ENABLE_MASK                                                                        0x80000000L
++//VTG1_CONTROL
++#define VTG1_CONTROL__VTG1_FP2__SHIFT                                                                         0x0
++#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT                                                                 0x10
++#define VTG1_CONTROL__VTG1_ENABLE__SHIFT                                                                      0x1f
++#define VTG1_CONTROL__VTG1_FP2_MASK                                                                           0x00007FFFL
++#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
++#define VTG1_CONTROL__VTG1_ENABLE_MASK                                                                        0x80000000L
++//VTG2_CONTROL
++#define VTG2_CONTROL__VTG2_FP2__SHIFT                                                                         0x0
++#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT                                                                 0x10
++#define VTG2_CONTROL__VTG2_ENABLE__SHIFT                                                                      0x1f
++#define VTG2_CONTROL__VTG2_FP2_MASK                                                                           0x00007FFFL
++#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
++#define VTG2_CONTROL__VTG2_ENABLE_MASK                                                                        0x80000000L
++//VTG3_CONTROL
++#define VTG3_CONTROL__VTG3_FP2__SHIFT                                                                         0x0
++#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT                                                                 0x10
++#define VTG3_CONTROL__VTG3_ENABLE__SHIFT                                                                      0x1f
++#define VTG3_CONTROL__VTG3_FP2_MASK                                                                           0x00007FFFL
++#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
++#define VTG3_CONTROL__VTG3_ENABLE_MASK                                                                        0x80000000L
++//DCHUBBUB_SOFT_RESET
++#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT                                                0x0
++#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT                                                   0x1
++#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT                                                        0x4
++#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK                                                  0x00000001L
++#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK                                                     0x00000002L
++#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK                                                          0x00000010L
++//DCHUBBUB_CLOCK_CNTL
++#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0
++#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                               0x5
++#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                                0x6
++#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL
++#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK                                                 0x00000020L
++#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK                                                  0x00000040L
++//DCFCLK_CNTL
++#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT                                                              0x0
++#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT                                                             0x4
++#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT                                                                   0x1f
++#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK                                                                0x0000000FL
++#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK                                                               0x00000FF0L
++#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK                                                                     0x80000000L
++//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT                                 0x0
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT                                    0x3
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT                                0x7
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT                                  0xa
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT                                          0xb
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK                                   0x00000001L
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK                                      0x00000078L
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK                                  0x00000380L
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK                                    0x00000400L
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK                                            0x007FF800L
++//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT                          0x0
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT                     0x1
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT                         0x4
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT                                     0xc
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT                                     0x13
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT                               0x1f
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK                            0x00000001L
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK                       0x0000000EL
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK                           0x00000FF0L
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK                                       0x00007000L
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK                                       0x7FF80000L
++#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK                                 0x80000000L
++//DCHUBBUB_VLINE_SNAPSHOT
++#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT                                               0x0
++#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK                                                 0x00000001L
++//DCHUBBUB_CTRL_STATUS
++#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT                                                  0x0
++#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK                                                    0x00000001L
++//DCHUBBUB_TIMEOUT_DETECTION_CTRL1
++#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT                                0x0
++#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT                         0x6
++#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK                                  0x0000003FL
++#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK                           0xFFFFFFC0L
++//DCHUBBUB_TIMEOUT_DETECTION_CTRL2
++#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT                      0x0
++#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT                                0x1b
++#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT                                 0x1c
++#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK                        0x07FFFFFFL
++#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK                                  0x08000000L
++#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK                                   0x10000000L
++//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS
++#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT                                 0x0
++#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT                                 0x1
++#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT                                  0x2
++#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT                                   0x3
++#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK                                   0x00000001L
++#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK                                   0x00000002L
++#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK                                    0x00000004L
++#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK                                     0x000000F8L
++//DCHUBBUB_TEST_DEBUG_INDEX
++#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX__SHIFT                                           0x0
++#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX_MASK                                             0x000000FFL
++//DCHUBBUB_TEST_DEBUG_DATA
++#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA__SHIFT                                             0x0
++#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA_MASK                                               0xFFFFFFFFL
++//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A
++#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT                                 0x0
++#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK                                   0x000003FFL
++//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A
++#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT                               0x0
++#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK                                 0x000003FFL
++//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B
++#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT                                 0x0
++#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK                                   0x000003FFL
++//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B
++#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT                               0x0
++#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK                                 0x000003FFL
++//DCHUBBUB_ARB_FRAC_URG_BW_NOM_C
++#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT                                 0x0
++#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK                                   0x000003FFL
++//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C
++#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT                               0x0
++#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK                                 0x000003FFL
++//DCHUBBUB_ARB_FRAC_URG_BW_NOM_D
++#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT                                 0x0
++#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK                                   0x000003FFL
++//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D
++#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT                               0x0
++#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK                                 0x000003FFL
++//DCHUBBUB_ARB_HOSTVM_CNTL
++#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE__SHIFT                                          0x0
++#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE__SHIFT                                    0x1
++#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK__SHIFT                                                       0x2
++#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS__SHIFT                                                  0x3
++#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS__SHIFT                                                  0x4
++#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS__SHIFT                                           0x5
++#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS__SHIFT                                         0x6
++#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS__SHIFT                                          0x8
++#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES__SHIFT                                           0x10
++#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS__SHIFT                                                           0x18
++#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD__SHIFT                                0x1c
++#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE_MASK                                            0x00000001L
++#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE_MASK                                      0x00000002L
++#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK_MASK                                                         0x00000004L
++#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS_MASK                                                    0x00000008L
++#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS_MASK                                                    0x00000010L
++#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS_MASK                                             0x00000020L
++#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS_MASK                                           0x00000040L
++#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS_MASK                                            0x00003F00L
++#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES_MASK                                             0x00FF0000L
++#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS_MASK                                                             0x0F000000L
++#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD_MASK                                  0xF0000000L
++//FMON_CTRL
++#define FMON_CTRL__FMON_START__SHIFT                                                                          0x0
++#define FMON_CTRL__FMON_MODE__SHIFT                                                                           0x1
++#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT                                                                  0x4
++#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT                                                                  0x5
++#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT                                                               0x6
++#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT                                                                  0x7
++#define FMON_CTRL__FMON_STATE__SHIFT                                                                          0x9
++#define FMON_CTRL__FMON_URG_FILTER__SHIFT                                                                     0xc
++#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT                                                                  0xd
++#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT                                                                   0x11
++#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT                                                                   0x16
++#define FMON_CTRL__FMON_SOF_SEL__SHIFT                                                                        0x1b
++#define FMON_CTRL__FMON_START_MASK                                                                            0x00000001L
++#define FMON_CTRL__FMON_MODE_MASK                                                                             0x00000006L
++#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK                                                                    0x00000010L
++#define FMON_CTRL__FMON_STATUS_IGNORE_MASK                                                                    0x00000020L
++#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK                                                                 0x00000040L
++#define FMON_CTRL__FMON_FILTER_UID_EN_MASK                                                                    0x00000180L
++#define FMON_CTRL__FMON_STATE_MASK                                                                            0x00000600L
++#define FMON_CTRL__FMON_URG_FILTER_MASK                                                                       0x00001000L
++#define FMON_CTRL__FMON_URG_THRESHOLD_MASK                                                                    0x0001E000L
++#define FMON_CTRL__FMON_FILTER_UID_1_MASK                                                                     0x003E0000L
++#define FMON_CTRL__FMON_FILTER_UID_2_MASK                                                                     0x07C00000L
++#define FMON_CTRL__FMON_SOF_SEL_MASK                                                                          0x38000000L
++
++
++// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON6_PERFCOUNTER_CNTL
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
++#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
++//DC_PERFMON6_PERFCOUNTER_CNTL2
++#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
++#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
++#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
++#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
++#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
++#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
++#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
++#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
++#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
++#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
++//DC_PERFMON6_PERFCOUNTER_STATE
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
++#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
++//DC_PERFMON6_PERFMON_CNTL
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
++#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
++//DC_PERFMON6_PERFMON_CNTL2
++#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
++#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
++#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
++#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
++#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
++#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
++#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
++#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
++//DC_PERFMON6_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
++#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
++//DC_PERFMON6_PERFMON_CVALUE_LOW
++#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
++#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
++//DC_PERFMON6_PERFMON_HI
++#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
++#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
++#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
++#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
++//DC_PERFMON6_PERFMON_LOW
++#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
++#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec
++//DCN_VM_CONTEXT0_CNTL
++#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT                                             0x1
++#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
++#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
++#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
++//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
++#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
++#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
++#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
++#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
++#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
++#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
++//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
++#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
++#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
++//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
++#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
++#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
++//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
++#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
++#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT1_CNTL
++#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT                                             0x1
++#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
++#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
++#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
++//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
++#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
++#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
++#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
++#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
++#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
++#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
++//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
++#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
++#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
++//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
++#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
++#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
++//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
++#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
++#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT2_CNTL
++#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT                                             0x1
++#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
++#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
++#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
++//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
++#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
++#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
++#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
++#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
++#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
++#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
++//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
++#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
++#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
++//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
++#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
++#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
++//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
++#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
++#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT3_CNTL
++#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT                                             0x1
++#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
++#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
++#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
++//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
++#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
++#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
++#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
++#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
++#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
++#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
++//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
++#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
++#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
++//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
++#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
++#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
++//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
++#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
++#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT4_CNTL
++#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT                                             0x1
++#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
++#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
++#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
++//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
++#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
++#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
++#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
++#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
++#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
++#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
++//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
++#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
++#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
++//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
++#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
++#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
++//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
++#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
++#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT5_CNTL
++#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT                                             0x1
++#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
++#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
++#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
++//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
++#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
++#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
++#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
++#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
++#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
++#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
++//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
++#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
++#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
++//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
++#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
++#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
++//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
++#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
++#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT6_CNTL
++#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT                                             0x1
++#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
++#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
++#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
++//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
++#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
++#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
++#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
++#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
++#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
++#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
++//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
++#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
++#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
++//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
++#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
++#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
++//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
++#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
++#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT7_CNTL
++#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT                                             0x1
++#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
++#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
++#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
++//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
++#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
++#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
++#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
++#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
++#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
++#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
++//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
++#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
++#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
++//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
++#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
++#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
++//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
++#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
++#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT8_CNTL
++#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT                                             0x1
++#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
++#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
++#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
++//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
++#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
++#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
++#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
++#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
++#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
++#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
++//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
++#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
++#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
++//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
++#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
++#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
++//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
++#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
++#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT9_CNTL
++#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT                                             0x1
++#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
++#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
++#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
++//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
++#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
++#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
++#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
++#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
++//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
++#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
++#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
++//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
++#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
++#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
++//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
++#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
++#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
++//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
++#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
++#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT10_CNTL
++#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT                                           0x1
++#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
++#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
++#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
++//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
++#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
++#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
++#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
++#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
++#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
++#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
++//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
++#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
++#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
++//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
++#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
++#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
++//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
++#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
++#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
++//DCN_VM_CONTEXT11_CNTL
++#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT                                           0x1
++#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
++#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
++#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
++//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
++#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
++#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
++#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
++#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
++#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
++#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
++//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
++#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
++#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
++//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
++#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
++#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
++//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
++#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
++#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
++//DCN_VM_CONTEXT12_CNTL
++#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT                                           0x1
++#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
++#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
++#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
++//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
++#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
++#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
++#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
++#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
++#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
++#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
++//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
++#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
++#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
++//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
++#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
++#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
++//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
++#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
++#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
++//DCN_VM_CONTEXT13_CNTL
++#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT                                           0x1
++#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
++#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
++#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
++//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
++#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
++#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
++#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
++#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
++#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
++#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
++//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
++#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
++#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
++//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
++#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
++#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
++//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
++#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
++#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
++//DCN_VM_CONTEXT14_CNTL
++#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT                                           0x1
++#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
++#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
++#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
++//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
++#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
++#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
++#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
++#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
++#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
++#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
++//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
++#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
++#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
++//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
++#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
++#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
++//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
++#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
++#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
++//DCN_VM_CONTEXT15_CNTL
++#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT                                           0x1
++#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
++#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
++#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
++//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
++#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
++#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
++#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
++#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
++//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
++#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
++#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
++//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
++#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
++#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
++//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
++#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
++#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
++//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
++#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
++#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
++//DCN_VM_DEFAULT_ADDR_MSB
++#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT                                               0x0
++#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT                                                    0x1c
++#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT                                                  0x1d
++#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK                                                 0x0000000FL
++#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK                                                      0x10000000L
++#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK                                                    0x20000000L
++//DCN_VM_DEFAULT_ADDR_LSB
++#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT                                               0x0
++#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK                                                 0xFFFFFFFFL
++//DCN_VM_FAULT_CNTL
++#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT                                                   0x0
++#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT                                                    0x1
++#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT                                               0x2
++#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT                                                  0x8
++#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT                                                    0x9
++#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK                                                     0x00000001L
++#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK                                                      0x00000002L
++#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK                                                 0x00000004L
++#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK                                                    0x00000100L
++#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK                                                      0x00000200L
++//DCN_VM_FAULT_STATUS
++#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT                                                       0x0
++#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT                                                         0x10
++#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT                                                  0x14
++#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT                                                         0x18
++#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT                                             0x1f
++#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK                                                         0x0000FFFFL
++#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK                                                           0x000F0000L
++#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK                                                    0x00300000L
++#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK                                                           0x0F000000L
++#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK                                               0x80000000L
++//DCN_VM_FAULT_ADDR_MSB
++#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT                                                   0x0
++#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK                                                     0x0000000FL
++//DCN_VM_FAULT_ADDR_LSB
++#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT                                                   0x0
++#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK                                                     0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
++//HUBP0_DCSURF_SURFACE_CONFIG
++#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
++#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
++#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
++#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
++#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
++#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
++//HUBP0_DCSURF_ADDR_CONFIG
++#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
++#define HUBP0_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT                                                            0x3
++#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
++#define HUBP0_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT                                                               0x8
++#define HUBP0_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                        0xa
++#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
++#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
++#define HUBP0_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK                                                              0x00000038L
++#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
++#define HUBP0_DCSURF_ADDR_CONFIG__NUM_SE_MASK                                                                 0x00000300L
++#define HUBP0_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                          0x00000C00L
++#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
++//HUBP0_DCSURF_TILING_CONFIG
++#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
++#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
++#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
++#define HUBP0_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT                                                         0xa
++#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
++#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
++#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
++#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
++#define HUBP0_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK                                                           0x00000400L
++#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
++//HUBP0_DCSURF_PRI_VIEWPORT_START
++#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
++#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
++#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
++#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
++//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION
++#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
++#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
++#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
++#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
++//HUBP0_DCSURF_PRI_VIEWPORT_START_C
++#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
++#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
++#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
++#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
++//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C
++#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
++#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
++#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
++#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
++//HUBP0_DCSURF_SEC_VIEWPORT_START
++#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
++#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
++#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
++#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
++//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION
++#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
++#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
++#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
++#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
++//HUBP0_DCSURF_SEC_VIEWPORT_START_C
++#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
++#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
++#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
++#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
++//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C
++#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
++#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
++#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
++#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
++//HUBP0_DCHUBP_REQ_SIZE_CONFIG
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
++//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
++#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
++//HUBP0_DCHUBP_CNTL
++#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
++#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
++#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE__SHIFT                                                                0x2
++#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
++#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
++#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
++#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
++#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
++#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
++#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
++#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
++#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
++#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
++#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
++#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
++#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
++#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
++#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
++#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_MASK                                                                  0x00000004L
++#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
++#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
++#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
++#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
++#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
++#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
++#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
++#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
++#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
++#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
++#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
++#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
++#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
++//HUBP0_HUBP_CLK_CNTL
++#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
++#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
++#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
++#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
++#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
++#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
++#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
++#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
++#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
++#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
++#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
++#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
++#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
++#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
++#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
++#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
++#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
++#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
++#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
++#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
++//HUBP0_DCHUBP_VMPG_CONFIG
++#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
++#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
++//HUBP0_HUBPREQ_DEBUG_DB
++#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
++#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
++//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
++//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
++#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
++
++
++// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
++//HUBPREQ0_DCSURF_SURFACE_PITCH
++#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
++#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
++#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
++#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
++//HUBPREQ0_DCSURF_SURFACE_PITCH_C
++#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
++#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
++#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
++#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
++//HUBPREQ0_VMID_SETTINGS_0
++#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
++#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
++//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS
++#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
++#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
++//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
++#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
++#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
++//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C
++#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
++#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
++//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
++#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
++#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
++//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS
++#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
++#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
++//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
++#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
++#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
++//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C
++#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
++#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
++//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
++#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
++#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
++//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS
++#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
++#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
++//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
++#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
++#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
++//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
++#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
++#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
++//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
++#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
++#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
++//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS
++#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
++#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
++//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
++#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
++#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
++//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
++#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
++#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
++//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
++#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
++#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
++//HUBPREQ0_DCSURF_SURFACE_CONTROL
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT                               0x2
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT                             0x5
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT                             0xa
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT                           0xd
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK                                 0x00000004L
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK                               0x00000020L
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK                               0x00000400L
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK                             0x00002000L
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
++#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
++//HUBPREQ0_DCSURF_FLIP_CONTROL
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
++#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
++//HUBPREQ0_DCSURF_FLIP_CONTROL2
++#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
++#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
++#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
++#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
++#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
++#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
++#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
++#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
++#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
++#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
++//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
++#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
++//HUBPREQ0_DCSURF_SURFACE_INUSE
++#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
++#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
++//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH
++#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
++#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
++//HUBPREQ0_DCSURF_SURFACE_INUSE_C
++#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
++#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
++//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C
++#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
++#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
++//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE
++#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
++#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
++//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
++#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
++#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
++//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C
++#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
++#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
++//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
++#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
++#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
++//HUBPREQ0_DCN_EXPANSION_MODE
++#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
++#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
++#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
++#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
++#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
++#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
++#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
++#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
++//HUBPREQ0_DCN_TTU_QOS_WM
++#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
++#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
++#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
++#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
++//HUBPREQ0_DCN_GLOBAL_TTU_CNTL
++#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
++#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
++#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
++#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
++//HUBPREQ0_DCN_SURF0_TTU_CNTL0
++#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
++#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
++#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
++#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
++#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
++#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
++//HUBPREQ0_DCN_SURF0_TTU_CNTL1
++#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
++#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
++//HUBPREQ0_DCN_SURF1_TTU_CNTL0
++#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
++#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
++#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
++#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
++#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
++#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
++//HUBPREQ0_DCN_SURF1_TTU_CNTL1
++#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
++#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
++//HUBPREQ0_DCN_CUR0_TTU_CNTL0
++#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
++#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
++#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
++#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
++#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
++#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
++//HUBPREQ0_DCN_CUR0_TTU_CNTL1
++#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
++#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
++//HUBPREQ0_DCN_CUR1_TTU_CNTL0
++#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
++#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
++#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
++#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
++#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
++#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
++//HUBPREQ0_DCN_CUR1_TTU_CNTL1
++#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
++#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
++//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
++#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
++#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
++//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
++#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
++#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
++//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL
++#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
++#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
++#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
++#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
++#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
++#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
++#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
++#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
++//HUBPREQ0_BLANK_OFFSET_0
++#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
++#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
++#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
++#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
++//HUBPREQ0_BLANK_OFFSET_1
++#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
++#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
++//HUBPREQ0_DST_DIMENSIONS
++#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
++#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
++//HUBPREQ0_DST_AFTER_SCALER
++#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
++#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
++#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
++#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
++//HUBPREQ0_PREFETCH_SETTINGS
++#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
++#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
++#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
++#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
++//HUBPREQ0_PREFETCH_SETTINGS_C
++#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
++#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
++//HUBPREQ0_VBLANK_PARAMETERS_0
++#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
++#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
++#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
++#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
++//HUBPREQ0_VBLANK_PARAMETERS_1
++#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
++#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
++//HUBPREQ0_VBLANK_PARAMETERS_2
++#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
++#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
++//HUBPREQ0_VBLANK_PARAMETERS_3
++#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
++#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
++//HUBPREQ0_VBLANK_PARAMETERS_4
++#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
++#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
++//HUBPREQ0_FLIP_PARAMETERS_0
++#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
++#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
++#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
++#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
++//HUBPREQ0_FLIP_PARAMETERS_1
++#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
++#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
++//HUBPREQ0_FLIP_PARAMETERS_2
++#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
++#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
++//HUBPREQ0_NOM_PARAMETERS_0
++#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
++#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
++//HUBPREQ0_NOM_PARAMETERS_1
++#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
++#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
++//HUBPREQ0_NOM_PARAMETERS_2
++#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
++#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
++//HUBPREQ0_NOM_PARAMETERS_3
++#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
++#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
++//HUBPREQ0_NOM_PARAMETERS_4
++#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
++#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
++//HUBPREQ0_NOM_PARAMETERS_5
++#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
++#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
++//HUBPREQ0_NOM_PARAMETERS_6
++#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
++#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
++//HUBPREQ0_NOM_PARAMETERS_7
++#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
++#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
++//HUBPREQ0_PER_LINE_DELIVERY_PRE
++#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
++#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
++#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
++#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
++//HUBPREQ0_PER_LINE_DELIVERY
++#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
++#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
++#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
++#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
++//HUBPREQ0_CURSOR_SETTINGS
++#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
++#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
++#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
++#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
++#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
++#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
++#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
++#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
++//HUBPREQ0_REF_FREQ_TO_PIX_FREQ
++#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
++#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
++//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT
++#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
++#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
++//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL
++#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
++#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
++#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
++#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
++#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
++#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
++#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
++#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
++#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
++#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
++#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
++#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
++#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
++#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
++#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
++#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
++//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS
++#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
++#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
++#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
++#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
++#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
++#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
++#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
++#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
++//HUBPREQ0_VBLANK_PARAMETERS_5
++#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
++#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
++//HUBPREQ0_VBLANK_PARAMETERS_6
++#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
++#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
++//HUBPREQ0_FLIP_PARAMETERS_3
++#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
++#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
++//HUBPREQ0_FLIP_PARAMETERS_4
++#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
++#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
++//HUBPREQ0_FLIP_PARAMETERS_5
++#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
++#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
++//HUBPREQ0_FLIP_PARAMETERS_6
++#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
++#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
++
++
++// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
++//HUBPRET0_HUBPRET_CONTROL
++#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x0
++#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xc
++#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
++#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
++#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
++#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
++#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
++#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00000FFFL
++#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00001000L
++#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
++#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
++#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
++#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
++#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
++//HUBPRET0_HUBPRET_MEM_PWR_CTRL
++#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT                                               0x0
++#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT                                                 0x2
++#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                             0x4
++#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
++#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
++#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
++#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
++#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
++#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK                                                 0x00000003L
++#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK                                                   0x00000004L
++#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK                                               0x00000030L
++#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
++#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
++#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
++#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
++#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
++//HUBPRET0_HUBPRET_MEM_PWR_STATUS
++#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT                                             0x0
++#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
++#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
++#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK                                               0x00000003L
++#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
++#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
++//HUBPRET0_HUBPRET_READ_LINE_CTRL0
++#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
++#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
++#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
++#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
++//HUBPRET0_HUBPRET_READ_LINE_CTRL1
++#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
++#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
++#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
++#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
++//HUBPRET0_HUBPRET_READ_LINE0
++#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
++#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
++#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
++#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
++//HUBPRET0_HUBPRET_READ_LINE1
++#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
++#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
++#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
++#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
++//HUBPRET0_HUBPRET_INTERRUPT
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
++#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
++//HUBPRET0_HUBPRET_READ_LINE_VALUE
++#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
++#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
++#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
++#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
++//HUBPRET0_HUBPRET_READ_LINE_STATUS
++#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
++#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
++#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
++#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
++#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
++#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
++#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
++#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
++#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
++#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
++
++
++// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
++//CURSOR0_0_CURSOR_CONTROL
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT                                                         0xd
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT                                                        0xe
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SNOOP_MASK                                                           0x00002000L
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SYSTEM_MASK                                                          0x00004000L
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
++#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
++//CURSOR0_0_CURSOR_SURFACE_ADDRESS
++#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
++#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
++//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH
++#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
++#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
++//CURSOR0_0_CURSOR_SIZE
++#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
++#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
++#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
++#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
++//CURSOR0_0_CURSOR_POSITION
++#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
++#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
++#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
++#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
++//CURSOR0_0_CURSOR_HOT_SPOT
++#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
++#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
++#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
++#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
++//CURSOR0_0_CURSOR_STEREO_CONTROL
++#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
++#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
++#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
++#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
++#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
++#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
++//CURSOR0_0_CURSOR_DST_OFFSET
++#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
++#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
++//CURSOR0_0_CURSOR_MEM_PWR_CTRL
++#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
++#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
++#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
++#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
++#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
++#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
++//CURSOR0_0_CURSOR_MEM_PWR_STATUS
++#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
++#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
++//CURSOR0_0_DMDATA_ADDRESS_HIGH
++#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
++#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT                                                   0x1c
++#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT                                                    0x1d
++#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
++#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
++#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK                                                     0x10000000L
++#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK                                                      0x20000000L
++#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
++//CURSOR0_0_DMDATA_ADDRESS_LOW
++#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
++#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
++//CURSOR0_0_DMDATA_CNTL
++#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
++#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
++#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
++#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
++#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
++#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
++#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
++#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
++//CURSOR0_0_DMDATA_QOS_CNTL
++#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
++#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
++#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
++#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
++#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
++#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
++//CURSOR0_0_DMDATA_STATUS
++#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
++#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
++#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
++#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
++#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
++#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
++//CURSOR0_0_DMDATA_SW_CNTL
++#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
++#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
++#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
++#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
++#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
++#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
++//CURSOR0_0_DMDATA_SW_DATA
++#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
++#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON7_PERFCOUNTER_CNTL
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
++#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
++//DC_PERFMON7_PERFCOUNTER_CNTL2
++#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
++#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
++#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
++#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
++#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
++#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
++#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
++#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
++#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
++#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
++//DC_PERFMON7_PERFCOUNTER_STATE
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
++#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
++//DC_PERFMON7_PERFMON_CNTL
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
++#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
++//DC_PERFMON7_PERFMON_CNTL2
++#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
++#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
++#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
++#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
++#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
++#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
++#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
++#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
++//DC_PERFMON7_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
++#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
++//DC_PERFMON7_PERFMON_CVALUE_LOW
++#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
++#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
++//DC_PERFMON7_PERFMON_HI
++#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
++#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
++#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
++#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
++//DC_PERFMON7_PERFMON_LOW
++#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
++#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
++//HUBP1_DCSURF_SURFACE_CONFIG
++#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
++#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
++#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
++#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
++#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
++#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
++//HUBP1_DCSURF_ADDR_CONFIG
++#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
++#define HUBP1_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT                                                            0x3
++#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
++#define HUBP1_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT                                                               0x8
++#define HUBP1_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                        0xa
++#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
++#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
++#define HUBP1_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK                                                              0x00000038L
++#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
++#define HUBP1_DCSURF_ADDR_CONFIG__NUM_SE_MASK                                                                 0x00000300L
++#define HUBP1_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                          0x00000C00L
++#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
++//HUBP1_DCSURF_TILING_CONFIG
++#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
++#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
++#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
++#define HUBP1_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT                                                         0xa
++#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
++#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
++#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
++#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
++#define HUBP1_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK                                                           0x00000400L
++#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
++//HUBP1_DCSURF_PRI_VIEWPORT_START
++#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
++#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
++#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
++#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
++//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION
++#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
++#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
++#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
++#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
++//HUBP1_DCSURF_PRI_VIEWPORT_START_C
++#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
++#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
++#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
++#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
++//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C
++#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
++#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
++#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
++#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
++//HUBP1_DCSURF_SEC_VIEWPORT_START
++#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
++#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
++#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
++#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
++//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION
++#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
++#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
++#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
++#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
++//HUBP1_DCSURF_SEC_VIEWPORT_START_C
++#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
++#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
++#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
++#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
++//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C
++#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
++#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
++#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
++#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
++//HUBP1_DCHUBP_REQ_SIZE_CONFIG
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
++//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
++#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
++//HUBP1_DCHUBP_CNTL
++#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
++#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
++#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE__SHIFT                                                                0x2
++#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
++#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
++#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
++#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
++#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
++#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
++#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
++#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
++#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
++#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
++#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
++#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
++#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
++#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
++#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
++#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_MASK                                                                  0x00000004L
++#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
++#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
++#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
++#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
++#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
++#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
++#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
++#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
++#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
++#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
++#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
++#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
++#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
++//HUBP1_HUBP_CLK_CNTL
++#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
++#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
++#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
++#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
++#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
++#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
++#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
++#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
++#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
++#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
++#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
++#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
++#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
++#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
++#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
++#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
++#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
++#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
++#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
++#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
++//HUBP1_DCHUBP_VMPG_CONFIG
++#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
++#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
++//HUBP1_HUBPREQ_DEBUG_DB
++#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
++#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
++//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
++//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
++#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
++
++
++// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
++//HUBPREQ1_DCSURF_SURFACE_PITCH
++#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
++#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
++#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
++#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
++//HUBPREQ1_DCSURF_SURFACE_PITCH_C
++#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
++#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
++#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
++#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
++//HUBPREQ1_VMID_SETTINGS_0
++#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
++#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
++//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS
++#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
++#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
++//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
++#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
++#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
++//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C
++#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
++#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
++//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
++#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
++#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
++//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS
++#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
++#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
++//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
++#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
++#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
++//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C
++#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
++#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
++//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
++#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
++#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
++//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS
++#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
++#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
++//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
++#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
++#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
++//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
++#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
++#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
++//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
++#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
++#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
++//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS
++#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
++#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
++//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
++#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
++#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
++//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
++#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
++#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
++//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
++#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
++#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
++//HUBPREQ1_DCSURF_SURFACE_CONTROL
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT                               0x2
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT                             0x5
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT                             0xa
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT                           0xd
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK                                 0x00000004L
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK                               0x00000020L
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK                               0x00000400L
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK                             0x00002000L
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
++#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
++//HUBPREQ1_DCSURF_FLIP_CONTROL
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
++#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
++//HUBPREQ1_DCSURF_FLIP_CONTROL2
++#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
++#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
++#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
++#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
++#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
++#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
++#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
++#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
++#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
++#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
++//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
++#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
++//HUBPREQ1_DCSURF_SURFACE_INUSE
++#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
++#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
++//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH
++#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
++#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
++//HUBPREQ1_DCSURF_SURFACE_INUSE_C
++#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
++#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
++//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C
++#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
++#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
++//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE
++#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
++#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
++//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
++#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
++#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
++//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C
++#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
++#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
++//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
++#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
++#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
++//HUBPREQ1_DCN_EXPANSION_MODE
++#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
++#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
++#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
++#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
++#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
++#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
++#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
++#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
++//HUBPREQ1_DCN_TTU_QOS_WM
++#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
++#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
++#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
++#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
++//HUBPREQ1_DCN_GLOBAL_TTU_CNTL
++#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
++#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
++#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
++#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
++//HUBPREQ1_DCN_SURF0_TTU_CNTL0
++#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
++#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
++#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
++#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
++#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
++#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
++//HUBPREQ1_DCN_SURF0_TTU_CNTL1
++#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
++#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
++//HUBPREQ1_DCN_SURF1_TTU_CNTL0
++#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
++#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
++#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
++#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
++#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
++#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
++//HUBPREQ1_DCN_SURF1_TTU_CNTL1
++#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
++#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
++//HUBPREQ1_DCN_CUR0_TTU_CNTL0
++#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
++#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
++#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
++#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
++#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
++#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
++//HUBPREQ1_DCN_CUR0_TTU_CNTL1
++#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
++#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
++//HUBPREQ1_DCN_CUR1_TTU_CNTL0
++#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
++#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
++#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
++#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
++#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
++#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
++//HUBPREQ1_DCN_CUR1_TTU_CNTL1
++#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
++#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
++//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
++#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
++#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
++//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
++#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
++#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
++//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL
++#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
++#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
++#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
++#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
++#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
++#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
++#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
++#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
++//HUBPREQ1_BLANK_OFFSET_0
++#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
++#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
++#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
++#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
++//HUBPREQ1_BLANK_OFFSET_1
++#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
++#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
++//HUBPREQ1_DST_DIMENSIONS
++#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
++#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
++//HUBPREQ1_DST_AFTER_SCALER
++#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
++#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
++#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
++#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
++//HUBPREQ1_PREFETCH_SETTINGS
++#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
++#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
++#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
++#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
++//HUBPREQ1_PREFETCH_SETTINGS_C
++#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
++#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
++//HUBPREQ1_VBLANK_PARAMETERS_0
++#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
++#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
++#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
++#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
++//HUBPREQ1_VBLANK_PARAMETERS_1
++#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
++#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
++//HUBPREQ1_VBLANK_PARAMETERS_2
++#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
++#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
++//HUBPREQ1_VBLANK_PARAMETERS_3
++#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
++#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
++//HUBPREQ1_VBLANK_PARAMETERS_4
++#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
++#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
++//HUBPREQ1_FLIP_PARAMETERS_0
++#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
++#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
++#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
++#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
++//HUBPREQ1_FLIP_PARAMETERS_1
++#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
++#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
++//HUBPREQ1_FLIP_PARAMETERS_2
++#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
++#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
++//HUBPREQ1_NOM_PARAMETERS_0
++#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
++#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
++//HUBPREQ1_NOM_PARAMETERS_1
++#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
++#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
++//HUBPREQ1_NOM_PARAMETERS_2
++#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
++#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
++//HUBPREQ1_NOM_PARAMETERS_3
++#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
++#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
++//HUBPREQ1_NOM_PARAMETERS_4
++#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
++#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
++//HUBPREQ1_NOM_PARAMETERS_5
++#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
++#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
++//HUBPREQ1_NOM_PARAMETERS_6
++#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
++#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
++//HUBPREQ1_NOM_PARAMETERS_7
++#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
++#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
++//HUBPREQ1_PER_LINE_DELIVERY_PRE
++#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
++#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
++#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
++#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
++//HUBPREQ1_PER_LINE_DELIVERY
++#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
++#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
++#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
++#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
++//HUBPREQ1_CURSOR_SETTINGS
++#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
++#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
++#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
++#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
++#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
++#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
++#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
++#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
++//HUBPREQ1_REF_FREQ_TO_PIX_FREQ
++#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
++#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
++//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT
++#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
++#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
++//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL
++#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
++#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
++#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
++#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
++#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
++#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
++#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
++#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
++#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
++#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
++#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
++#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
++#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
++#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
++#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
++#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
++//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS
++#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
++#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
++#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
++#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
++#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
++#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
++#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
++#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
++//HUBPREQ1_VBLANK_PARAMETERS_5
++#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
++#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
++//HUBPREQ1_VBLANK_PARAMETERS_6
++#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
++#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
++//HUBPREQ1_FLIP_PARAMETERS_3
++#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
++#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
++//HUBPREQ1_FLIP_PARAMETERS_4
++#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
++#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
++//HUBPREQ1_FLIP_PARAMETERS_5
++#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
++#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
++//HUBPREQ1_FLIP_PARAMETERS_6
++#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
++#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
++
++
++// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
++//HUBPRET1_HUBPRET_CONTROL
++#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x0
++#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xc
++#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
++#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
++#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
++#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
++#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
++#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00000FFFL
++#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00001000L
++#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
++#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
++#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
++#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
++#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
++//HUBPRET1_HUBPRET_MEM_PWR_CTRL
++#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT                                               0x0
++#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT                                                 0x2
++#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                             0x4
++#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
++#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
++#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
++#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
++#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
++#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK                                                 0x00000003L
++#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK                                                   0x00000004L
++#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK                                               0x00000030L
++#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
++#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
++#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
++#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
++#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
++//HUBPRET1_HUBPRET_MEM_PWR_STATUS
++#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT                                             0x0
++#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
++#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
++#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK                                               0x00000003L
++#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
++#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
++//HUBPRET1_HUBPRET_READ_LINE_CTRL0
++#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
++#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
++#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
++#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
++//HUBPRET1_HUBPRET_READ_LINE_CTRL1
++#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
++#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
++#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
++#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
++//HUBPRET1_HUBPRET_READ_LINE0
++#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
++#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
++#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
++#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
++//HUBPRET1_HUBPRET_READ_LINE1
++#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
++#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
++#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
++#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
++//HUBPRET1_HUBPRET_INTERRUPT
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
++#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
++//HUBPRET1_HUBPRET_READ_LINE_VALUE
++#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
++#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
++#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
++#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
++//HUBPRET1_HUBPRET_READ_LINE_STATUS
++#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
++#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
++#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
++#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
++#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
++#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
++#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
++#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
++#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
++#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
++
++
++// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
++//CURSOR0_1_CURSOR_CONTROL
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT                                                         0xd
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT                                                        0xe
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SNOOP_MASK                                                           0x00002000L
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SYSTEM_MASK                                                          0x00004000L
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
++#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
++//CURSOR0_1_CURSOR_SURFACE_ADDRESS
++#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
++#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
++//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH
++#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
++#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
++//CURSOR0_1_CURSOR_SIZE
++#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
++#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
++#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
++#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
++//CURSOR0_1_CURSOR_POSITION
++#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
++#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
++#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
++#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
++//CURSOR0_1_CURSOR_HOT_SPOT
++#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
++#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
++#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
++#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
++//CURSOR0_1_CURSOR_STEREO_CONTROL
++#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
++#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
++#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
++#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
++#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
++#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
++//CURSOR0_1_CURSOR_DST_OFFSET
++#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
++#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
++//CURSOR0_1_CURSOR_MEM_PWR_CTRL
++#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
++#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
++#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
++#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
++#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
++#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
++//CURSOR0_1_CURSOR_MEM_PWR_STATUS
++#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
++#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
++//CURSOR0_1_DMDATA_ADDRESS_HIGH
++#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
++#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT                                                   0x1c
++#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT                                                    0x1d
++#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
++#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
++#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK                                                     0x10000000L
++#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK                                                      0x20000000L
++#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
++//CURSOR0_1_DMDATA_ADDRESS_LOW
++#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
++#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
++//CURSOR0_1_DMDATA_CNTL
++#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
++#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
++#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
++#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
++#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
++#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
++#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
++#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
++//CURSOR0_1_DMDATA_QOS_CNTL
++#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
++#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
++#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
++#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
++#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
++#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
++//CURSOR0_1_DMDATA_STATUS
++#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
++#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
++#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
++#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
++#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
++#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
++//CURSOR0_1_DMDATA_SW_CNTL
++#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
++#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
++#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
++#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
++#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
++#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
++//CURSOR0_1_DMDATA_SW_DATA
++#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
++#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON8_PERFCOUNTER_CNTL
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
++#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
++//DC_PERFMON8_PERFCOUNTER_CNTL2
++#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
++#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
++#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
++#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
++#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
++#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
++#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
++#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
++#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
++#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
++//DC_PERFMON8_PERFCOUNTER_STATE
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
++#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
++//DC_PERFMON8_PERFMON_CNTL
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
++#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
++//DC_PERFMON8_PERFMON_CNTL2
++#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
++#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
++#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
++#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
++#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
++#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
++#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
++#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
++//DC_PERFMON8_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
++#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
++//DC_PERFMON8_PERFMON_CVALUE_LOW
++#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
++#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
++//DC_PERFMON8_PERFMON_HI
++#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
++#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
++#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
++#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
++//DC_PERFMON8_PERFMON_LOW
++#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
++#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
++//HUBP2_DCSURF_SURFACE_CONFIG
++#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
++#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
++#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
++#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
++#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
++#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
++//HUBP2_DCSURF_ADDR_CONFIG
++#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
++#define HUBP2_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT                                                            0x3
++#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
++#define HUBP2_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT                                                               0x8
++#define HUBP2_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                        0xa
++#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
++#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
++#define HUBP2_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK                                                              0x00000038L
++#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
++#define HUBP2_DCSURF_ADDR_CONFIG__NUM_SE_MASK                                                                 0x00000300L
++#define HUBP2_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                          0x00000C00L
++#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
++//HUBP2_DCSURF_TILING_CONFIG
++#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
++#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
++#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
++#define HUBP2_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT                                                         0xa
++#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
++#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
++#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
++#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
++#define HUBP2_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK                                                           0x00000400L
++#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
++//HUBP2_DCSURF_PRI_VIEWPORT_START
++#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
++#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
++#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
++#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
++//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION
++#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
++#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
++#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
++#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
++//HUBP2_DCSURF_PRI_VIEWPORT_START_C
++#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
++#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
++#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
++#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
++//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C
++#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
++#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
++#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
++#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
++//HUBP2_DCSURF_SEC_VIEWPORT_START
++#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
++#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
++#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
++#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
++//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION
++#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
++#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
++#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
++#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
++//HUBP2_DCSURF_SEC_VIEWPORT_START_C
++#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
++#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
++#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
++#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
++//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C
++#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
++#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
++#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
++#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
++//HUBP2_DCHUBP_REQ_SIZE_CONFIG
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
++//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
++#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
++//HUBP2_DCHUBP_CNTL
++#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
++#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
++#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE__SHIFT                                                                0x2
++#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
++#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
++#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
++#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
++#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
++#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
++#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
++#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
++#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
++#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
++#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
++#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
++#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
++#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
++#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
++#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_MASK                                                                  0x00000004L
++#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
++#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
++#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
++#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
++#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
++#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
++#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
++#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
++#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
++#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
++#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
++#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
++#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
++//HUBP2_HUBP_CLK_CNTL
++#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
++#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
++#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
++#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
++#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
++#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
++#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
++#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
++#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
++#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
++#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
++#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
++#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
++#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
++#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
++#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
++#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
++#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
++#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
++#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
++//HUBP2_DCHUBP_VMPG_CONFIG
++#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
++#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
++//HUBP2_HUBPREQ_DEBUG_DB
++#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
++#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
++//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
++//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
++#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
++
++
++// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
++//HUBPREQ2_DCSURF_SURFACE_PITCH
++#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
++#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
++#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
++#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
++//HUBPREQ2_DCSURF_SURFACE_PITCH_C
++#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
++#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
++#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
++#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
++//HUBPREQ2_VMID_SETTINGS_0
++#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
++#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
++//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS
++#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
++#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
++//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
++#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
++#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
++//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C
++#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
++#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
++//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
++#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
++#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
++//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS
++#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
++#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
++//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
++#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
++#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
++//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C
++#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
++#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
++//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
++#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
++#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
++//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS
++#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
++#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
++//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
++#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
++#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
++//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
++#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
++#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
++//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
++#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
++#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
++//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS
++#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
++#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
++//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
++#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
++#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
++//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
++#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
++#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
++//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
++#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
++#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
++//HUBPREQ2_DCSURF_SURFACE_CONTROL
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT                               0x2
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT                             0x5
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT                             0xa
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT                           0xd
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK                                 0x00000004L
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK                               0x00000020L
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK                               0x00000400L
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK                             0x00002000L
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
++#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
++//HUBPREQ2_DCSURF_FLIP_CONTROL
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
++#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
++//HUBPREQ2_DCSURF_FLIP_CONTROL2
++#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
++#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
++#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
++#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
++#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
++#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
++#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
++#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
++#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
++#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
++//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
++#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
++//HUBPREQ2_DCSURF_SURFACE_INUSE
++#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
++#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
++//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH
++#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
++#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
++//HUBPREQ2_DCSURF_SURFACE_INUSE_C
++#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
++#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
++//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C
++#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
++#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
++//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE
++#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
++#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
++//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
++#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
++#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
++//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C
++#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
++#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
++//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
++#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
++#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
++//HUBPREQ2_DCN_EXPANSION_MODE
++#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
++#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
++#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
++#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
++#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
++#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
++#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
++#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
++//HUBPREQ2_DCN_TTU_QOS_WM
++#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
++#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
++#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
++#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
++//HUBPREQ2_DCN_GLOBAL_TTU_CNTL
++#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
++#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
++#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
++#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
++//HUBPREQ2_DCN_SURF0_TTU_CNTL0
++#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
++#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
++#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
++#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
++#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
++#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
++//HUBPREQ2_DCN_SURF0_TTU_CNTL1
++#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
++#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
++//HUBPREQ2_DCN_SURF1_TTU_CNTL0
++#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
++#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
++#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
++#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
++#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
++#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
++//HUBPREQ2_DCN_SURF1_TTU_CNTL1
++#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
++#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
++//HUBPREQ2_DCN_CUR0_TTU_CNTL0
++#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
++#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
++#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
++#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
++#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
++#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
++//HUBPREQ2_DCN_CUR0_TTU_CNTL1
++#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
++#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
++//HUBPREQ2_DCN_CUR1_TTU_CNTL0
++#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
++#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
++#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
++#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
++#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
++#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
++//HUBPREQ2_DCN_CUR1_TTU_CNTL1
++#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
++#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
++//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
++#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
++#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
++//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
++#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
++#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
++//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL
++#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
++#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
++#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
++#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
++#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
++#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
++#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
++#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
++//HUBPREQ2_BLANK_OFFSET_0
++#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
++#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
++#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
++#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
++//HUBPREQ2_BLANK_OFFSET_1
++#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
++#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
++//HUBPREQ2_DST_DIMENSIONS
++#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
++#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
++//HUBPREQ2_DST_AFTER_SCALER
++#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
++#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
++#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
++#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
++//HUBPREQ2_PREFETCH_SETTINGS
++#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
++#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
++#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
++#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
++//HUBPREQ2_PREFETCH_SETTINGS_C
++#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
++#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
++//HUBPREQ2_VBLANK_PARAMETERS_0
++#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
++#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
++#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
++#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
++//HUBPREQ2_VBLANK_PARAMETERS_1
++#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
++#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
++//HUBPREQ2_VBLANK_PARAMETERS_2
++#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
++#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
++//HUBPREQ2_VBLANK_PARAMETERS_3
++#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
++#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
++//HUBPREQ2_VBLANK_PARAMETERS_4
++#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
++#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
++//HUBPREQ2_FLIP_PARAMETERS_0
++#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
++#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
++#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
++#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
++//HUBPREQ2_FLIP_PARAMETERS_1
++#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
++#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
++//HUBPREQ2_FLIP_PARAMETERS_2
++#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
++#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
++//HUBPREQ2_NOM_PARAMETERS_0
++#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
++#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
++//HUBPREQ2_NOM_PARAMETERS_1
++#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
++#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
++//HUBPREQ2_NOM_PARAMETERS_2
++#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
++#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
++//HUBPREQ2_NOM_PARAMETERS_3
++#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
++#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
++//HUBPREQ2_NOM_PARAMETERS_4
++#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
++#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
++//HUBPREQ2_NOM_PARAMETERS_5
++#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
++#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
++//HUBPREQ2_NOM_PARAMETERS_6
++#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
++#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
++//HUBPREQ2_NOM_PARAMETERS_7
++#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
++#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
++//HUBPREQ2_PER_LINE_DELIVERY_PRE
++#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
++#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
++#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
++#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
++//HUBPREQ2_PER_LINE_DELIVERY
++#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
++#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
++#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
++#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
++//HUBPREQ2_CURSOR_SETTINGS
++#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
++#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
++#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
++#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
++#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
++#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
++#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
++#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
++//HUBPREQ2_REF_FREQ_TO_PIX_FREQ
++#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
++#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
++//HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT
++#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
++#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
++//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL
++#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
++#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
++#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
++#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
++#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
++#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
++#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
++#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
++#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
++#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
++#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
++#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
++#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
++#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
++#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
++#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
++//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS
++#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
++#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
++#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
++#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
++#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
++#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
++#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
++#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
++//HUBPREQ2_VBLANK_PARAMETERS_5
++#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
++#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
++//HUBPREQ2_VBLANK_PARAMETERS_6
++#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
++#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
++//HUBPREQ2_FLIP_PARAMETERS_3
++#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
++#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
++//HUBPREQ2_FLIP_PARAMETERS_4
++#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
++#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
++//HUBPREQ2_FLIP_PARAMETERS_5
++#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
++#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
++//HUBPREQ2_FLIP_PARAMETERS_6
++#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
++#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
++
++
++// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
++//HUBPRET2_HUBPRET_CONTROL
++#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x0
++#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xc
++#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
++#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
++#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
++#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
++#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
++#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00000FFFL
++#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00001000L
++#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
++#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
++#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
++#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
++#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
++//HUBPRET2_HUBPRET_MEM_PWR_CTRL
++#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT                                               0x0
++#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT                                                 0x2
++#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                             0x4
++#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
++#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
++#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
++#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
++#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
++#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK                                                 0x00000003L
++#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK                                                   0x00000004L
++#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK                                               0x00000030L
++#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
++#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
++#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
++#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
++#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
++//HUBPRET2_HUBPRET_MEM_PWR_STATUS
++#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT                                             0x0
++#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
++#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
++#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK                                               0x00000003L
++#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
++#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
++//HUBPRET2_HUBPRET_READ_LINE_CTRL0
++#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
++#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
++#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
++#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
++//HUBPRET2_HUBPRET_READ_LINE_CTRL1
++#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
++#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
++#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
++#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
++//HUBPRET2_HUBPRET_READ_LINE0
++#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
++#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
++#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
++#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
++//HUBPRET2_HUBPRET_READ_LINE1
++#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
++#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
++#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
++#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
++//HUBPRET2_HUBPRET_INTERRUPT
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
++#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
++//HUBPRET2_HUBPRET_READ_LINE_VALUE
++#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
++#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
++#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
++#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
++//HUBPRET2_HUBPRET_READ_LINE_STATUS
++#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
++#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
++#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
++#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
++#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
++#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
++#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
++#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
++#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
++#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
++
++
++// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
++//CURSOR0_2_CURSOR_CONTROL
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT                                                         0xd
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT                                                        0xe
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SNOOP_MASK                                                           0x00002000L
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SYSTEM_MASK                                                          0x00004000L
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
++#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
++//CURSOR0_2_CURSOR_SURFACE_ADDRESS
++#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
++#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
++//CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH
++#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
++#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
++//CURSOR0_2_CURSOR_SIZE
++#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
++#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
++#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
++#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
++//CURSOR0_2_CURSOR_POSITION
++#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
++#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
++#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
++#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
++//CURSOR0_2_CURSOR_HOT_SPOT
++#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
++#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
++#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
++#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
++//CURSOR0_2_CURSOR_STEREO_CONTROL
++#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
++#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
++#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
++#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
++#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
++#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
++//CURSOR0_2_CURSOR_DST_OFFSET
++#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
++#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
++//CURSOR0_2_CURSOR_MEM_PWR_CTRL
++#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
++#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
++#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
++#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
++#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
++#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
++//CURSOR0_2_CURSOR_MEM_PWR_STATUS
++#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
++#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
++//CURSOR0_2_DMDATA_ADDRESS_HIGH
++#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
++#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT                                                   0x1c
++#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT                                                    0x1d
++#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
++#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
++#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK                                                     0x10000000L
++#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK                                                      0x20000000L
++#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
++//CURSOR0_2_DMDATA_ADDRESS_LOW
++#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
++#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
++//CURSOR0_2_DMDATA_CNTL
++#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
++#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
++#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
++#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
++#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
++#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
++#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
++#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
++//CURSOR0_2_DMDATA_QOS_CNTL
++#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
++#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
++#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
++#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
++#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
++#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
++//CURSOR0_2_DMDATA_STATUS
++#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
++#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
++#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
++#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
++#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
++#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
++//CURSOR0_2_DMDATA_SW_CNTL
++#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
++#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
++#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
++#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
++#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
++#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
++//CURSOR0_2_DMDATA_SW_DATA
++#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
++#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON9_PERFCOUNTER_CNTL
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
++#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
++//DC_PERFMON9_PERFCOUNTER_CNTL2
++#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
++#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
++#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
++#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
++#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
++#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
++#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
++#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
++#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
++#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
++//DC_PERFMON9_PERFCOUNTER_STATE
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
++#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
++//DC_PERFMON9_PERFMON_CNTL
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
++#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
++//DC_PERFMON9_PERFMON_CNTL2
++#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
++#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
++#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
++#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
++#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
++#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
++#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
++#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
++//DC_PERFMON9_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
++#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
++//DC_PERFMON9_PERFMON_CVALUE_LOW
++#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
++#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
++//DC_PERFMON9_PERFMON_HI
++#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
++#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
++#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
++#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
++//DC_PERFMON9_PERFMON_LOW
++#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
++#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
++//HUBP3_DCSURF_SURFACE_CONFIG
++#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
++#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
++#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
++#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
++#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
++#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
++//HUBP3_DCSURF_ADDR_CONFIG
++#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
++#define HUBP3_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT                                                            0x3
++#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
++#define HUBP3_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT                                                               0x8
++#define HUBP3_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                        0xa
++#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
++#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
++#define HUBP3_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK                                                              0x00000038L
++#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
++#define HUBP3_DCSURF_ADDR_CONFIG__NUM_SE_MASK                                                                 0x00000300L
++#define HUBP3_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                          0x00000C00L
++#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
++//HUBP3_DCSURF_TILING_CONFIG
++#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
++#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
++#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
++#define HUBP3_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT                                                         0xa
++#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
++#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
++#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
++#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
++#define HUBP3_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK                                                           0x00000400L
++#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
++//HUBP3_DCSURF_PRI_VIEWPORT_START
++#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
++#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
++#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
++#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
++//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION
++#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
++#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
++#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
++#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
++//HUBP3_DCSURF_PRI_VIEWPORT_START_C
++#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
++#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
++#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
++#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
++//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C
++#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
++#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
++#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
++#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
++//HUBP3_DCSURF_SEC_VIEWPORT_START
++#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
++#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
++#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
++#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
++//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION
++#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
++#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
++#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
++#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
++//HUBP3_DCSURF_SEC_VIEWPORT_START_C
++#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
++#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
++#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
++#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
++//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C
++#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
++#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
++#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
++#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
++//HUBP3_DCHUBP_REQ_SIZE_CONFIG
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
++//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
++#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
++//HUBP3_DCHUBP_CNTL
++#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
++#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
++#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE__SHIFT                                                                0x2
++#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
++#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
++#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
++#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
++#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
++#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
++#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
++#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
++#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
++#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
++#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
++#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
++#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
++#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
++#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
++#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_MASK                                                                  0x00000004L
++#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
++#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
++#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
++#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
++#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
++#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
++#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
++#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
++#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
++#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
++#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
++#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
++#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
++//HUBP3_HUBP_CLK_CNTL
++#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
++#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
++#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
++#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
++#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
++#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
++#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
++#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
++#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
++#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
++#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
++#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
++#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
++#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
++#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
++#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
++#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
++#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
++#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
++#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
++//HUBP3_DCHUBP_VMPG_CONFIG
++#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
++#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
++//HUBP3_HUBPREQ_DEBUG_DB
++#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
++#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
++//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
++//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
++#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
++
++
++// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
++//HUBPREQ3_DCSURF_SURFACE_PITCH
++#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
++#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
++#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
++#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
++//HUBPREQ3_DCSURF_SURFACE_PITCH_C
++#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
++#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
++#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
++#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
++//HUBPREQ3_VMID_SETTINGS_0
++#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
++#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
++//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS
++#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
++#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
++//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
++#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
++#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
++//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C
++#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
++#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
++//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
++#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
++#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
++//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS
++#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
++#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
++//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
++#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
++#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
++//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C
++#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
++#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
++//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
++#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
++#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
++//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS
++#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
++#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
++//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
++#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
++#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
++//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
++#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
++#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
++//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
++#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
++#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
++//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS
++#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
++#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
++//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
++#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
++#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
++//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
++#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
++#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
++//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
++#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
++#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
++//HUBPREQ3_DCSURF_SURFACE_CONTROL
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT                               0x2
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT                             0x5
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT                             0xa
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT                           0xd
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK                                 0x00000004L
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK                               0x00000020L
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK                               0x00000400L
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK                             0x00002000L
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
++#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
++//HUBPREQ3_DCSURF_FLIP_CONTROL
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
++#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
++//HUBPREQ3_DCSURF_FLIP_CONTROL2
++#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
++#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
++#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
++#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
++#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
++#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
++#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
++#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
++#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
++#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
++//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
++#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
++//HUBPREQ3_DCSURF_SURFACE_INUSE
++#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
++#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
++//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH
++#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
++#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
++//HUBPREQ3_DCSURF_SURFACE_INUSE_C
++#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
++#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
++//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C
++#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
++#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
++//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE
++#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
++#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
++//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
++#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
++#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
++//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C
++#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
++#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
++//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
++#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
++#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
++//HUBPREQ3_DCN_EXPANSION_MODE
++#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
++#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
++#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
++#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
++#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
++#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
++#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
++#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
++//HUBPREQ3_DCN_TTU_QOS_WM
++#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
++#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
++#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
++#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
++//HUBPREQ3_DCN_GLOBAL_TTU_CNTL
++#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
++#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
++#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
++#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
++//HUBPREQ3_DCN_SURF0_TTU_CNTL0
++#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
++#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
++#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
++#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
++#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
++#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
++//HUBPREQ3_DCN_SURF0_TTU_CNTL1
++#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
++#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
++//HUBPREQ3_DCN_SURF1_TTU_CNTL0
++#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
++#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
++#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
++#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
++#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
++#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
++//HUBPREQ3_DCN_SURF1_TTU_CNTL1
++#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
++#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
++//HUBPREQ3_DCN_CUR0_TTU_CNTL0
++#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
++#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
++#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
++#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
++#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
++#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
++//HUBPREQ3_DCN_CUR0_TTU_CNTL1
++#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
++#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
++//HUBPREQ3_DCN_CUR1_TTU_CNTL0
++#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
++#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
++#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
++#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
++#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
++#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
++//HUBPREQ3_DCN_CUR1_TTU_CNTL1
++#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
++#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
++//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
++#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
++#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
++//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
++#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
++#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
++//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL
++#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
++#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
++#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
++#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
++#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
++#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
++#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
++#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
++//HUBPREQ3_BLANK_OFFSET_0
++#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
++#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
++#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
++#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
++//HUBPREQ3_BLANK_OFFSET_1
++#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
++#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
++//HUBPREQ3_DST_DIMENSIONS
++#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
++#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
++//HUBPREQ3_DST_AFTER_SCALER
++#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
++#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
++#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
++#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
++//HUBPREQ3_PREFETCH_SETTINGS
++#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
++#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
++#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
++#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
++//HUBPREQ3_PREFETCH_SETTINGS_C
++#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
++#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
++//HUBPREQ3_VBLANK_PARAMETERS_0
++#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
++#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
++#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
++#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
++//HUBPREQ3_VBLANK_PARAMETERS_1
++#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
++#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
++//HUBPREQ3_VBLANK_PARAMETERS_2
++#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
++#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
++//HUBPREQ3_VBLANK_PARAMETERS_3
++#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
++#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
++//HUBPREQ3_VBLANK_PARAMETERS_4
++#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
++#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
++//HUBPREQ3_FLIP_PARAMETERS_0
++#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
++#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
++#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
++#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
++//HUBPREQ3_FLIP_PARAMETERS_1
++#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
++#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
++//HUBPREQ3_FLIP_PARAMETERS_2
++#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
++#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
++//HUBPREQ3_NOM_PARAMETERS_0
++#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
++#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
++//HUBPREQ3_NOM_PARAMETERS_1
++#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
++#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
++//HUBPREQ3_NOM_PARAMETERS_2
++#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
++#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
++//HUBPREQ3_NOM_PARAMETERS_3
++#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
++#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
++//HUBPREQ3_NOM_PARAMETERS_4
++#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
++#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
++//HUBPREQ3_NOM_PARAMETERS_5
++#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
++#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
++//HUBPREQ3_NOM_PARAMETERS_6
++#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
++#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
++//HUBPREQ3_NOM_PARAMETERS_7
++#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
++#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
++//HUBPREQ3_PER_LINE_DELIVERY_PRE
++#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
++#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
++#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
++#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
++//HUBPREQ3_PER_LINE_DELIVERY
++#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
++#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
++#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
++#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
++//HUBPREQ3_CURSOR_SETTINGS
++#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
++#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
++#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
++#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
++#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
++#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
++#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
++#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
++//HUBPREQ3_REF_FREQ_TO_PIX_FREQ
++#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
++#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
++//HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT
++#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
++#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
++//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL
++#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
++#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
++#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
++#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
++#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
++#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
++#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
++#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
++#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
++#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
++#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
++#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
++#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
++#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
++#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
++#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
++//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS
++#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
++#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
++#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
++#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
++#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
++#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
++#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
++#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
++//HUBPREQ3_VBLANK_PARAMETERS_5
++#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
++#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
++//HUBPREQ3_VBLANK_PARAMETERS_6
++#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
++#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
++//HUBPREQ3_FLIP_PARAMETERS_3
++#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
++#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
++//HUBPREQ3_FLIP_PARAMETERS_4
++#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
++#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
++//HUBPREQ3_FLIP_PARAMETERS_5
++#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
++#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
++//HUBPREQ3_FLIP_PARAMETERS_6
++#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
++#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
++
++
++// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
++//HUBPRET3_HUBPRET_CONTROL
++#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x0
++#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xc
++#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
++#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
++#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
++#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
++#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
++#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00000FFFL
++#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00001000L
++#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
++#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
++#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
++#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
++#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
++//HUBPRET3_HUBPRET_MEM_PWR_CTRL
++#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT                                               0x0
++#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT                                                 0x2
++#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                             0x4
++#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
++#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
++#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
++#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
++#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
++#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK                                                 0x00000003L
++#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK                                                   0x00000004L
++#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK                                               0x00000030L
++#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
++#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
++#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
++#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
++#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
++//HUBPRET3_HUBPRET_MEM_PWR_STATUS
++#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT                                             0x0
++#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
++#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
++#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK                                               0x00000003L
++#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
++#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
++//HUBPRET3_HUBPRET_READ_LINE_CTRL0
++#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
++#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
++#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
++#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
++//HUBPRET3_HUBPRET_READ_LINE_CTRL1
++#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
++#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
++#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
++#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
++//HUBPRET3_HUBPRET_READ_LINE0
++#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
++#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
++#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
++#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
++//HUBPRET3_HUBPRET_READ_LINE1
++#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
++#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
++#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
++#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
++//HUBPRET3_HUBPRET_INTERRUPT
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
++#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
++//HUBPRET3_HUBPRET_READ_LINE_VALUE
++#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
++#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
++#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
++#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
++//HUBPRET3_HUBPRET_READ_LINE_STATUS
++#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
++#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
++#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
++#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
++#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
++#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
++#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
++#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
++#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
++#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
++
++
++// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
++//CURSOR0_3_CURSOR_CONTROL
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT                                                         0xd
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT                                                        0xe
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SNOOP_MASK                                                           0x00002000L
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SYSTEM_MASK                                                          0x00004000L
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
++#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
++//CURSOR0_3_CURSOR_SURFACE_ADDRESS
++#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
++#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
++//CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH
++#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
++#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
++//CURSOR0_3_CURSOR_SIZE
++#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
++#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
++#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
++#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
++//CURSOR0_3_CURSOR_POSITION
++#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
++#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
++#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
++#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
++//CURSOR0_3_CURSOR_HOT_SPOT
++#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
++#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
++#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
++#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
++//CURSOR0_3_CURSOR_STEREO_CONTROL
++#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
++#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
++#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
++#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
++#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
++#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
++//CURSOR0_3_CURSOR_DST_OFFSET
++#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
++#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
++//CURSOR0_3_CURSOR_MEM_PWR_CTRL
++#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
++#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
++#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
++#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
++#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
++#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
++//CURSOR0_3_CURSOR_MEM_PWR_STATUS
++#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
++#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
++//CURSOR0_3_DMDATA_ADDRESS_HIGH
++#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
++#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT                                                   0x1c
++#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT                                                    0x1d
++#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
++#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
++#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK                                                     0x10000000L
++#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK                                                      0x20000000L
++#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
++//CURSOR0_3_DMDATA_ADDRESS_LOW
++#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
++#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
++//CURSOR0_3_DMDATA_CNTL
++#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
++#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
++#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
++#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
++#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
++#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
++#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
++#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
++//CURSOR0_3_DMDATA_QOS_CNTL
++#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
++#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
++#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
++#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
++#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
++#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
++//CURSOR0_3_DMDATA_STATUS
++#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
++#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
++#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
++#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
++#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
++#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
++//CURSOR0_3_DMDATA_SW_CNTL
++#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
++#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
++#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
++#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
++#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
++#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
++//CURSOR0_3_DMDATA_SW_DATA
++#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
++#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON10_PERFCOUNTER_CNTL
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
++#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
++//DC_PERFMON10_PERFCOUNTER_CNTL2
++#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
++#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
++#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
++#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
++#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
++#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
++#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
++#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
++#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
++#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
++//DC_PERFMON10_PERFCOUNTER_STATE
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
++#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
++//DC_PERFMON10_PERFMON_CNTL
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
++#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
++//DC_PERFMON10_PERFMON_CNTL2
++#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
++#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
++#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
++#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
++#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
++#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
++#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
++#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
++//DC_PERFMON10_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
++#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
++//DC_PERFMON10_PERFMON_CVALUE_LOW
++#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
++#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
++//DC_PERFMON10_PERFMON_HI
++#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
++#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
++#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
++#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
++//DC_PERFMON10_PERFMON_LOW
++#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
++#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
++//DPP_TOP0_DPP_CONTROL
++#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
++#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
++#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
++#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
++#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT                                         0xe
++#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0x10
++#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x12
++#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x14
++#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
++#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
++#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
++#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
++#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
++#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK                                           0x00004000L
++#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00010000L
++#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00040000L
++#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00100000L
++#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0xF0000000L
++//DPP_TOP0_DPP_SOFT_RESET
++#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
++#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
++#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
++#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
++#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
++#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
++#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
++#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
++//DPP_TOP0_DPP_CRC_VAL_R_G
++#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
++#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
++#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
++#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
++//DPP_TOP0_DPP_CRC_VAL_B_A
++#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
++#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
++#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
++#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
++//DPP_TOP0_DPP_CRC_CTRL
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT                                                 0x6
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x7
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x8
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0xa
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xc
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xf
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK                                                   0x00000040L
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000080L
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000300L
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000C00L
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00007000L
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x00008000L
++#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
++//DPP_TOP0_HOST_READ_CONTROL
++#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
++#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
++
++
++// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
++//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT
++#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
++#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
++//CNVC_CFG0_FORMAT_CONTROL
++#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
++#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
++#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
++#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
++#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
++#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
++#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
++#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
++#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
++#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
++#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
++#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
++#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
++#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
++#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
++#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
++//CNVC_CFG0_FCNV_FP_BIAS_R
++#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
++#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
++//CNVC_CFG0_FCNV_FP_BIAS_G
++#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
++#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
++//CNVC_CFG0_FCNV_FP_BIAS_B
++#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
++#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
++//CNVC_CFG0_FCNV_FP_SCALE_R
++#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
++#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
++//CNVC_CFG0_FCNV_FP_SCALE_G
++#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
++#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
++//CNVC_CFG0_FCNV_FP_SCALE_B
++#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
++#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
++//CNVC_CFG0_COLOR_KEYER_CONTROL
++#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
++#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
++#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
++#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
++//CNVC_CFG0_COLOR_KEYER_ALPHA
++#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
++#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
++#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
++#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
++//CNVC_CFG0_COLOR_KEYER_RED
++#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
++#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
++#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
++#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
++//CNVC_CFG0_COLOR_KEYER_GREEN
++#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
++#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
++#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
++#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
++//CNVC_CFG0_COLOR_KEYER_BLUE
++#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
++#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
++#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
++#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
++//CNVC_CFG0_ALPHA_2BIT_LUT
++#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
++#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
++#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
++#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
++#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
++#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
++#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
++#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
++
++
++// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
++//CNVC_CUR0_CURSOR0_CONTROL
++#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
++#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
++#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
++#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
++#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
++#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
++#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
++#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
++#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
++#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
++#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
++#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
++#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
++#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
++//CNVC_CUR0_CURSOR0_COLOR0
++#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
++#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
++//CNVC_CUR0_CURSOR0_COLOR1
++#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
++#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
++//CNVC_CUR0_CURSOR0_FP_SCALE_BIAS
++#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
++#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
++#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
++#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
++
++
++// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
++//DSCL0_SCL_COEF_RAM_TAP_SELECT
++#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
++#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
++#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
++#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
++#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
++#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
++//DSCL0_SCL_COEF_RAM_TAP_DATA
++#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
++#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
++#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
++#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
++#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
++#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
++#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
++#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
++//DSCL0_SCL_MODE
++#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
++#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
++#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
++#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
++#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
++#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
++#define DSCL0_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
++#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
++#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
++#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
++#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
++#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
++//DSCL0_SCL_TAP_CONTROL
++#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
++#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
++#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
++#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
++#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
++#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
++#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
++#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
++//DSCL0_DSCL_CONTROL
++#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
++#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
++//DSCL0_DSCL_2TAP_CONTROL
++#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
++#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
++#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
++#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
++#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
++#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
++#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
++#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
++#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
++#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
++#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
++#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
++//DSCL0_SCL_MANUAL_REPLICATE_CONTROL
++#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
++#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
++#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
++#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
++//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO
++#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
++#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x03FFFFFFL
++//DSCL0_SCL_HORZ_FILTER_INIT
++#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
++#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
++#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
++#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
++//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C
++#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
++#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x03FFFFFFL
++//DSCL0_SCL_HORZ_FILTER_INIT_C
++#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
++#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
++#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
++#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
++//DSCL0_SCL_VERT_FILTER_SCALE_RATIO
++#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
++#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x03FFFFFFL
++//DSCL0_SCL_VERT_FILTER_INIT
++#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
++#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
++#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
++#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
++//DSCL0_SCL_VERT_FILTER_INIT_BOT
++#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
++#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
++#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
++#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
++//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C
++#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
++#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x03FFFFFFL
++//DSCL0_SCL_VERT_FILTER_INIT_C
++#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
++#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
++#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
++#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
++//DSCL0_SCL_VERT_FILTER_INIT_BOT_C
++#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
++#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
++#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
++#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
++//DSCL0_SCL_BLACK_OFFSET
++#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT                                                 0x0
++#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT                                                  0x10
++#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK                                                   0x0000FFFFL
++#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK                                                    0xFFFF0000L
++//DSCL0_DSCL_UPDATE
++#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
++#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
++//DSCL0_DSCL_AUTOCAL
++#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
++#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
++#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
++#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
++#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
++#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
++//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT
++#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
++#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
++#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
++#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
++//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM
++#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
++#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
++#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
++#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
++//DSCL0_OTG_H_BLANK
++#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
++#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
++#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
++#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
++//DSCL0_OTG_V_BLANK
++#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
++#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
++#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
++#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
++//DSCL0_RECOUT_START
++#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
++#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
++#define DSCL0_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
++#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
++//DSCL0_RECOUT_SIZE
++#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
++#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
++#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
++#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
++//DSCL0_MPC_SIZE
++#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
++#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
++#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
++#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
++//DSCL0_LB_DATA_FORMAT
++#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
++#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
++#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
++#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
++//DSCL0_LB_MEMORY_CTRL
++#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
++#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
++#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
++#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
++#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
++#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
++#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
++#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
++//DSCL0_LB_V_COUNTER
++#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
++#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
++#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
++#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
++//DSCL0_DSCL_MEM_PWR_CTRL
++#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
++#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
++#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
++#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
++#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
++//DSCL0_DSCL_MEM_PWR_STATUS
++#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
++#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
++#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
++#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
++#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
++#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
++#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
++#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
++#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
++#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
++#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
++#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
++#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
++#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
++//DSCL0_OBUF_CONTROL
++#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
++#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x4
++#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0xc
++#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x1c
++#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
++#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000010L
++#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00001000L
++#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0xF0000000L
++//DSCL0_OBUF_MEM_PWR_CTRL
++#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
++#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
++#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
++#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
++#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
++#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
++#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
++#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
++
++
++// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
++//CM0_CM_CONTROL
++#define CM0_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
++#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
++#define CM0_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
++#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
++//CM0_CM_ICSC_CONTROL
++#define CM0_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT                                                              0x0
++#define CM0_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK                                                                0x00000003L
++//CM0_CM_ICSC_C11_C12
++#define CM0_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT                                                               0x0
++#define CM0_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT                                                               0x10
++#define CM0_CM_ICSC_C11_C12__CM_ICSC_C11_MASK                                                                 0x0000FFFFL
++#define CM0_CM_ICSC_C11_C12__CM_ICSC_C12_MASK                                                                 0xFFFF0000L
++//CM0_CM_ICSC_C13_C14
++#define CM0_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT                                                               0x0
++#define CM0_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT                                                               0x10
++#define CM0_CM_ICSC_C13_C14__CM_ICSC_C13_MASK                                                                 0x0000FFFFL
++#define CM0_CM_ICSC_C13_C14__CM_ICSC_C14_MASK                                                                 0xFFFF0000L
++//CM0_CM_ICSC_C21_C22
++#define CM0_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT                                                               0x0
++#define CM0_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT                                                               0x10
++#define CM0_CM_ICSC_C21_C22__CM_ICSC_C21_MASK                                                                 0x0000FFFFL
++#define CM0_CM_ICSC_C21_C22__CM_ICSC_C22_MASK                                                                 0xFFFF0000L
++//CM0_CM_ICSC_C23_C24
++#define CM0_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT                                                               0x0
++#define CM0_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT                                                               0x10
++#define CM0_CM_ICSC_C23_C24__CM_ICSC_C23_MASK                                                                 0x0000FFFFL
++#define CM0_CM_ICSC_C23_C24__CM_ICSC_C24_MASK                                                                 0xFFFF0000L
++//CM0_CM_ICSC_C31_C32
++#define CM0_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT                                                               0x0
++#define CM0_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT                                                               0x10
++#define CM0_CM_ICSC_C31_C32__CM_ICSC_C31_MASK                                                                 0x0000FFFFL
++#define CM0_CM_ICSC_C31_C32__CM_ICSC_C32_MASK                                                                 0xFFFF0000L
++//CM0_CM_ICSC_C33_C34
++#define CM0_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT                                                               0x0
++#define CM0_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT                                                               0x10
++#define CM0_CM_ICSC_C33_C34__CM_ICSC_C33_MASK                                                                 0x0000FFFFL
++#define CM0_CM_ICSC_C33_C34__CM_ICSC_C34_MASK                                                                 0xFFFF0000L
++//CM0_CM_ICSC_B_C11_C12
++#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT                                                           0x0
++#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT                                                           0x10
++#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK                                                             0x0000FFFFL
++#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK                                                             0xFFFF0000L
++//CM0_CM_ICSC_B_C13_C14
++#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT                                                           0x0
++#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT                                                           0x10
++#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK                                                             0x0000FFFFL
++#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK                                                             0xFFFF0000L
++//CM0_CM_ICSC_B_C21_C22
++#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT                                                           0x0
++#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT                                                           0x10
++#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK                                                             0x0000FFFFL
++#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK                                                             0xFFFF0000L
++//CM0_CM_ICSC_B_C23_C24
++#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT                                                           0x0
++#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT                                                           0x10
++#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK                                                             0x0000FFFFL
++#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK                                                             0xFFFF0000L
++//CM0_CM_ICSC_B_C31_C32
++#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT                                                           0x0
++#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT                                                           0x10
++#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK                                                             0x0000FFFFL
++#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK                                                             0xFFFF0000L
++//CM0_CM_ICSC_B_C33_C34
++#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT                                                           0x0
++#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT                                                           0x10
++#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK                                                             0x0000FFFFL
++#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK                                                             0xFFFF0000L
++//CM0_CM_GAMUT_REMAP_CONTROL
++#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
++#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
++//CM0_CM_GAMUT_REMAP_C11_C12
++#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
++#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
++#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
++#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
++//CM0_CM_GAMUT_REMAP_C13_C14
++#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
++#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
++#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
++#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
++//CM0_CM_GAMUT_REMAP_C21_C22
++#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
++#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
++#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
++#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
++//CM0_CM_GAMUT_REMAP_C23_C24
++#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
++#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
++#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
++#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
++//CM0_CM_GAMUT_REMAP_C31_C32
++#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
++#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
++#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
++#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
++//CM0_CM_GAMUT_REMAP_C33_C34
++#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
++#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
++#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
++#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
++//CM0_CM_GAMUT_REMAP_B_C11_C12
++#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
++#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
++#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
++#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
++//CM0_CM_GAMUT_REMAP_B_C13_C14
++#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
++#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
++#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
++#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
++//CM0_CM_GAMUT_REMAP_B_C21_C22
++#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
++#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
++#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
++#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
++//CM0_CM_GAMUT_REMAP_B_C23_C24
++#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
++#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
++#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
++#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
++//CM0_CM_GAMUT_REMAP_B_C31_C32
++#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
++#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
++#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
++#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
++//CM0_CM_GAMUT_REMAP_B_C33_C34
++#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
++#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
++#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
++#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
++//CM0_CM_BIAS_CR_R
++#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
++#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
++//CM0_CM_BIAS_Y_G_CB_B
++#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
++#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
++#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
++#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
++//CM0_CM_DGAM_CONTROL
++#define CM0_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT                                                          0x0
++#define CM0_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK                                                            0x00000007L
++//CM0_CM_DGAM_LUT_INDEX
++#define CM0_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT                                                       0x0
++#define CM0_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK                                                         0x000001FFL
++//CM0_CM_DGAM_LUT_DATA
++#define CM0_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT                                                         0x0
++#define CM0_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK                                                           0x0007FFFFL
++//CM0_CM_DGAM_LUT_WRITE_EN_MASK
++#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT                                       0x0
++#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT                                           0x4
++#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT                                           0x8
++#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT                                     0xc
++#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK                                         0x00000007L
++#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK                                             0x00000010L
++#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK                                             0x00000700L
++#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK                                       0x00001000L
++//CM0_CM_DGAM_RAMA_START_CNTL_B
++#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT                                 0x0
++#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                         0x14
++#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK                                   0x0003FFFFL
++#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                           0x07F00000L
++//CM0_CM_DGAM_RAMA_START_CNTL_G
++#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT                                 0x0
++#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                         0x14
++#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK                                   0x0003FFFFL
++#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                           0x07F00000L
++//CM0_CM_DGAM_RAMA_START_CNTL_R
++#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT                                 0x0
++#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                         0x14
++#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK                                   0x0003FFFFL
++#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                           0x07F00000L
++//CM0_CM_DGAM_RAMA_SLOPE_CNTL_B
++#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT                          0x0
++#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                            0x0003FFFFL
++//CM0_CM_DGAM_RAMA_SLOPE_CNTL_G
++#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT                          0x0
++#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                            0x0003FFFFL
++//CM0_CM_DGAM_RAMA_SLOPE_CNTL_R
++#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT                          0x0
++#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                            0x0003FFFFL
++//CM0_CM_DGAM_RAMA_END_CNTL1_B
++#define CM0_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT                                    0x0
++#define CM0_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK                                      0x0000FFFFL
++//CM0_CM_DGAM_RAMA_END_CNTL2_B
++#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                              0x0
++#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                               0x10
++#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                                0x0000FFFFL
++#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK                                 0xFFFF0000L
++//CM0_CM_DGAM_RAMA_END_CNTL1_G
++#define CM0_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT                                    0x0
++#define CM0_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK                                      0x0000FFFFL
++//CM0_CM_DGAM_RAMA_END_CNTL2_G
++#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                              0x0
++#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                               0x10
++#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                                0x0000FFFFL
++#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK                                 0xFFFF0000L
++//CM0_CM_DGAM_RAMA_END_CNTL1_R
++#define CM0_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT                                    0x0
++#define CM0_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK                                      0x0000FFFFL
++//CM0_CM_DGAM_RAMA_END_CNTL2_R
++#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                              0x0
++#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                               0x10
++#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                                0x0000FFFFL
++#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK                                 0xFFFF0000L
++//CM0_CM_DGAM_RAMA_REGION_0_1
++#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                               0x0
++#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                             0xc
++#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                               0x10
++#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                               0x70000000L
++//CM0_CM_DGAM_RAMA_REGION_2_3
++#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                               0x0
++#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                             0xc
++#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                               0x10
++#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                               0x70000000L
++//CM0_CM_DGAM_RAMA_REGION_4_5
++#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                               0x0
++#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                             0xc
++#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                               0x10
++#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                               0x70000000L
++//CM0_CM_DGAM_RAMA_REGION_6_7
++#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                               0x0
++#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                             0xc
++#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                               0x10
++#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                               0x70000000L
++//CM0_CM_DGAM_RAMA_REGION_8_9
++#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                               0x0
++#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                             0xc
++#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                               0x10
++#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                               0x70000000L
++//CM0_CM_DGAM_RAMA_REGION_10_11
++#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                            0x0
++#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                          0xc
++#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                            0x10
++#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                              0x000001FFL
++#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                            0x70000000L
++//CM0_CM_DGAM_RAMA_REGION_12_13
++#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                            0x0
++#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                          0xc
++#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                            0x10
++#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                              0x000001FFL
++#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                            0x70000000L
++//CM0_CM_DGAM_RAMA_REGION_14_15
++#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                            0x0
++#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                          0xc
++#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                            0x10
++#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                              0x000001FFL
++#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                            0x70000000L
++//CM0_CM_DGAM_RAMB_START_CNTL_B
++#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT                                 0x0
++#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                         0x14
++#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK                                   0x0003FFFFL
++#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                           0x07F00000L
++//CM0_CM_DGAM_RAMB_START_CNTL_G
++#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT                                 0x0
++#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                         0x14
++#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK                                   0x0003FFFFL
++#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                           0x07F00000L
++//CM0_CM_DGAM_RAMB_START_CNTL_R
++#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT                                 0x0
++#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                         0x14
++#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK                                   0x0003FFFFL
++#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                           0x07F00000L
++//CM0_CM_DGAM_RAMB_SLOPE_CNTL_B
++#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT                          0x0
++#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                            0x0003FFFFL
++//CM0_CM_DGAM_RAMB_SLOPE_CNTL_G
++#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT                          0x0
++#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                            0x0003FFFFL
++//CM0_CM_DGAM_RAMB_SLOPE_CNTL_R
++#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT                          0x0
++#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                            0x0003FFFFL
++//CM0_CM_DGAM_RAMB_END_CNTL1_B
++#define CM0_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT                                    0x0
++#define CM0_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK                                      0x0000FFFFL
++//CM0_CM_DGAM_RAMB_END_CNTL2_B
++#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                              0x0
++#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                               0x10
++#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                                0x0000FFFFL
++#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK                                 0xFFFF0000L
++//CM0_CM_DGAM_RAMB_END_CNTL1_G
++#define CM0_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT                                    0x0
++#define CM0_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK                                      0x0000FFFFL
++//CM0_CM_DGAM_RAMB_END_CNTL2_G
++#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                              0x0
++#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                               0x10
++#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                                0x0000FFFFL
++#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK                                 0xFFFF0000L
++//CM0_CM_DGAM_RAMB_END_CNTL1_R
++#define CM0_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT                                    0x0
++#define CM0_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK                                      0x0000FFFFL
++//CM0_CM_DGAM_RAMB_END_CNTL2_R
++#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                              0x0
++#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                               0x10
++#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                                0x0000FFFFL
++#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK                                 0xFFFF0000L
++//CM0_CM_DGAM_RAMB_REGION_0_1
++#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                               0x0
++#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                             0xc
++#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                               0x10
++#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                               0x70000000L
++//CM0_CM_DGAM_RAMB_REGION_2_3
++#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                               0x0
++#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                             0xc
++#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                               0x10
++#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                               0x70000000L
++//CM0_CM_DGAM_RAMB_REGION_4_5
++#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                               0x0
++#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                             0xc
++#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                               0x10
++#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                               0x70000000L
++//CM0_CM_DGAM_RAMB_REGION_6_7
++#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                               0x0
++#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                             0xc
++#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                               0x10
++#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                               0x70000000L
++//CM0_CM_DGAM_RAMB_REGION_8_9
++#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                               0x0
++#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                             0xc
++#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                               0x10
++#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                               0x70000000L
++//CM0_CM_DGAM_RAMB_REGION_10_11
++#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                            0x0
++#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                          0xc
++#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                            0x10
++#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                              0x000001FFL
++#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                            0x70000000L
++//CM0_CM_DGAM_RAMB_REGION_12_13
++#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                            0x0
++#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                          0xc
++#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                            0x10
++#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                              0x000001FFL
++#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                            0x70000000L
++//CM0_CM_DGAM_RAMB_REGION_14_15
++#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                            0x0
++#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                          0xc
++#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                            0x10
++#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                              0x000001FFL
++#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                            0x70000000L
++//CM0_CM_BLNDGAM_CONTROL
++#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT                                                    0x0
++#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK                                                      0x00000003L
++//CM0_CM_BLNDGAM_LUT_INDEX
++#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
++#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
++//CM0_CM_BLNDGAM_LUT_DATA
++#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
++#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0007FFFFL
++//CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK
++#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT                                 0x0
++#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT                                     0x4
++#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT                                     0x8
++#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK                                   0x00000007L
++#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK                                       0x00000010L
++#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK                                       0x00000300L
++//CM0_CM_BLNDGAM_RAMA_START_CNTL_B
++#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
++#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
++#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
++#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
++//CM0_CM_BLNDGAM_RAMA_START_CNTL_G
++#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
++#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
++#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
++#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
++//CM0_CM_BLNDGAM_RAMA_START_CNTL_R
++#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
++#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
++#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
++#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
++//CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B
++#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT                    0x0
++#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                      0x0003FFFFL
++//CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G
++#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT                    0x0
++#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                      0x0003FFFFL
++//CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R
++#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT                    0x0
++#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                      0x0003FFFFL
++//CM0_CM_BLNDGAM_RAMA_END_CNTL1_B
++#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
++#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
++//CM0_CM_BLNDGAM_RAMA_END_CNTL2_B
++#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x0
++#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x10
++#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0x0000FFFFL
++#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0xFFFF0000L
++//CM0_CM_BLNDGAM_RAMA_END_CNTL1_G
++#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
++#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
++//CM0_CM_BLNDGAM_RAMA_END_CNTL2_G
++#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x0
++#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x10
++#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0x0000FFFFL
++#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0xFFFF0000L
++//CM0_CM_BLNDGAM_RAMA_END_CNTL1_R
++#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
++#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
++//CM0_CM_BLNDGAM_RAMA_END_CNTL2_R
++#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x0
++#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x10
++#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0x0000FFFFL
++#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0xFFFF0000L
++//CM0_CM_BLNDGAM_RAMA_REGION_0_1
++#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
++#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
++#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
++#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
++#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
++//CM0_CM_BLNDGAM_RAMA_REGION_2_3
++#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
++#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
++#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
++#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
++#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
++//CM0_CM_BLNDGAM_RAMA_REGION_4_5
++#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
++#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
++#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
++#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
++#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
++//CM0_CM_BLNDGAM_RAMA_REGION_6_7
++#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
++#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
++#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
++#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
++#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
++//CM0_CM_BLNDGAM_RAMA_REGION_8_9
++#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
++#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
++#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
++#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
++#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
++//CM0_CM_BLNDGAM_RAMA_REGION_10_11
++#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMA_REGION_12_13
++#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMA_REGION_14_15
++#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMA_REGION_16_17
++#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMA_REGION_18_19
++#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMA_REGION_20_21
++#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMA_REGION_22_23
++#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMA_REGION_24_25
++#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMA_REGION_26_27
++#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMA_REGION_28_29
++#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMA_REGION_30_31
++#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMA_REGION_32_33
++#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMB_START_CNTL_B
++#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
++#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
++#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
++#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
++//CM0_CM_BLNDGAM_RAMB_START_CNTL_G
++#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
++#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
++#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
++#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
++//CM0_CM_BLNDGAM_RAMB_START_CNTL_R
++#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
++#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
++#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
++#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
++//CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B
++#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT                    0x0
++#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                      0x0003FFFFL
++//CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G
++#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT                    0x0
++#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                      0x0003FFFFL
++//CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R
++#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT                    0x0
++#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                      0x0003FFFFL
++//CM0_CM_BLNDGAM_RAMB_END_CNTL1_B
++#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
++#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
++//CM0_CM_BLNDGAM_RAMB_END_CNTL2_B
++#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x0
++#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x10
++#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0x0000FFFFL
++#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0xFFFF0000L
++//CM0_CM_BLNDGAM_RAMB_END_CNTL1_G
++#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
++#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
++//CM0_CM_BLNDGAM_RAMB_END_CNTL2_G
++#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x0
++#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x10
++#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0x0000FFFFL
++#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0xFFFF0000L
++//CM0_CM_BLNDGAM_RAMB_END_CNTL1_R
++#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
++#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
++//CM0_CM_BLNDGAM_RAMB_END_CNTL2_R
++#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x0
++#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x10
++#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0x0000FFFFL
++#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0xFFFF0000L
++//CM0_CM_BLNDGAM_RAMB_REGION_0_1
++#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
++#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
++#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
++#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
++#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
++//CM0_CM_BLNDGAM_RAMB_REGION_2_3
++#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
++#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
++#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
++#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
++#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
++//CM0_CM_BLNDGAM_RAMB_REGION_4_5
++#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
++#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
++#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
++#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
++#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
++//CM0_CM_BLNDGAM_RAMB_REGION_6_7
++#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
++#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
++#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
++#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
++#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
++//CM0_CM_BLNDGAM_RAMB_REGION_8_9
++#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
++#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
++#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
++#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
++#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
++//CM0_CM_BLNDGAM_RAMB_REGION_10_11
++#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMB_REGION_12_13
++#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMB_REGION_14_15
++#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMB_REGION_16_17
++#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMB_REGION_18_19
++#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMB_REGION_20_21
++#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMB_REGION_22_23
++#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMB_REGION_24_25
++#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMB_REGION_26_27
++#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMB_REGION_28_29
++#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMB_REGION_30_31
++#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_BLNDGAM_RAMB_REGION_32_33
++#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
++#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
++#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
++#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
++#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
++//CM0_CM_HDR_MULT_COEF
++#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
++#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
++//CM0_CM_MEM_PWR_CTRL
++#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT                                                      0x0
++#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT                                                        0x2
++#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
++#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
++#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK                                                        0x00000003L
++#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK                                                          0x00000004L
++#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
++#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
++//CM0_CM_MEM_PWR_STATUS
++#define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT                                                    0x0
++#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
++#define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK                                                      0x00000003L
++#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
++//CM0_CM_DEALPHA
++#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
++#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
++//CM0_CM_COEF_FORMAT
++#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
++#define CM0_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT                                                        0x4
++#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
++#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
++#define CM0_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK                                                          0x00000010L
++#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
++//CM0_CM_SHAPER_CONTROL
++#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
++#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
++//CM0_CM_SHAPER_OFFSET_R
++#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
++#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
++//CM0_CM_SHAPER_OFFSET_G
++#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
++#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
++//CM0_CM_SHAPER_OFFSET_B
++#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
++#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
++//CM0_CM_SHAPER_SCALE_R
++#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
++#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
++//CM0_CM_SHAPER_SCALE_G_B
++#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
++#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
++#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
++#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
++//CM0_CM_SHAPER_LUT_INDEX
++#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
++#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
++//CM0_CM_SHAPER_LUT_DATA
++#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
++#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
++//CM0_CM_SHAPER_LUT_WRITE_EN_MASK
++#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
++#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
++#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT                                       0x8
++#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
++#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
++#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK                                         0x00000300L
++//CM0_CM_SHAPER_RAMA_START_CNTL_B
++#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
++#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
++#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
++#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
++//CM0_CM_SHAPER_RAMA_START_CNTL_G
++#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
++#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
++#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
++#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
++//CM0_CM_SHAPER_RAMA_START_CNTL_R
++#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
++#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
++#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
++#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
++//CM0_CM_SHAPER_RAMA_END_CNTL_B
++#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
++#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
++#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
++#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
++//CM0_CM_SHAPER_RAMA_END_CNTL_G
++#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
++#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
++#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
++#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
++//CM0_CM_SHAPER_RAMA_END_CNTL_R
++#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
++#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
++#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
++#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
++//CM0_CM_SHAPER_RAMA_REGION_0_1
++#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
++#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
++#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
++#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
++#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
++//CM0_CM_SHAPER_RAMA_REGION_2_3
++#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
++#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
++#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
++#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
++#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
++//CM0_CM_SHAPER_RAMA_REGION_4_5
++#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
++#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
++#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
++#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
++#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
++//CM0_CM_SHAPER_RAMA_REGION_6_7
++#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
++#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
++#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
++#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
++#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
++//CM0_CM_SHAPER_RAMA_REGION_8_9
++#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
++#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
++#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
++#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
++#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
++//CM0_CM_SHAPER_RAMA_REGION_10_11
++#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMA_REGION_12_13
++#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMA_REGION_14_15
++#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMA_REGION_16_17
++#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMA_REGION_18_19
++#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMA_REGION_20_21
++#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMA_REGION_22_23
++#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMA_REGION_24_25
++#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMA_REGION_26_27
++#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMA_REGION_28_29
++#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMA_REGION_30_31
++#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMA_REGION_32_33
++#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMB_START_CNTL_B
++#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
++#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
++#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
++#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
++//CM0_CM_SHAPER_RAMB_START_CNTL_G
++#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
++#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
++#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
++#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
++//CM0_CM_SHAPER_RAMB_START_CNTL_R
++#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
++#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
++#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
++#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
++//CM0_CM_SHAPER_RAMB_END_CNTL_B
++#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
++#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
++#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
++#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
++//CM0_CM_SHAPER_RAMB_END_CNTL_G
++#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
++#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
++#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
++#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
++//CM0_CM_SHAPER_RAMB_END_CNTL_R
++#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
++#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
++#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
++#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
++//CM0_CM_SHAPER_RAMB_REGION_0_1
++#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
++#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
++#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
++#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
++#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
++//CM0_CM_SHAPER_RAMB_REGION_2_3
++#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
++#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
++#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
++#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
++#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
++//CM0_CM_SHAPER_RAMB_REGION_4_5
++#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
++#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
++#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
++#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
++#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
++//CM0_CM_SHAPER_RAMB_REGION_6_7
++#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
++#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
++#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
++#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
++#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
++//CM0_CM_SHAPER_RAMB_REGION_8_9
++#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
++#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
++#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
++#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
++#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
++//CM0_CM_SHAPER_RAMB_REGION_10_11
++#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMB_REGION_12_13
++#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMB_REGION_14_15
++#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMB_REGION_16_17
++#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMB_REGION_18_19
++#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMB_REGION_20_21
++#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMB_REGION_22_23
++#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMB_REGION_24_25
++#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMB_REGION_26_27
++#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMB_REGION_28_29
++#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMB_REGION_30_31
++#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_SHAPER_RAMB_REGION_32_33
++#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
++#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
++#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
++#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
++#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
++//CM0_CM_MEM_PWR_CTRL2
++#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
++#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
++#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
++#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
++#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
++#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
++#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
++#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
++//CM0_CM_MEM_PWR_STATUS2
++#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
++#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
++#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
++#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
++//CM0_CM_3DLUT_MODE
++#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
++#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
++#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
++#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
++//CM0_CM_3DLUT_INDEX
++#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
++#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
++//CM0_CM_3DLUT_DATA
++#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
++#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
++#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
++#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
++//CM0_CM_3DLUT_DATA_30BIT
++#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
++#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
++//CM0_CM_3DLUT_READ_WRITE_CONTROL
++#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
++#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
++#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
++#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT                                        0xc
++#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
++#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
++#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
++#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
++#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK                                          0x00003000L
++#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
++//CM0_CM_3DLUT_OUT_NORM_FACTOR
++#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
++#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
++//CM0_CM_3DLUT_OUT_OFFSET_R
++#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
++#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
++#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
++#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
++//CM0_CM_3DLUT_OUT_OFFSET_G
++#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
++#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
++#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
++#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
++//CM0_CM_3DLUT_OUT_OFFSET_B
++#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
++#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
++#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
++#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
++//CM0_CM_TEST_DEBUG_INDEX
++#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
++#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
++#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
++#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
++//CM0_CM_TEST_DEBUG_DATA
++#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
++#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON11_PERFCOUNTER_CNTL
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
++#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
++//DC_PERFMON11_PERFCOUNTER_CNTL2
++#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
++#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
++#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
++#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
++#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
++#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
++#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
++#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
++#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
++#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
++//DC_PERFMON11_PERFCOUNTER_STATE
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
++#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
++//DC_PERFMON11_PERFMON_CNTL
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
++#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
++//DC_PERFMON11_PERFMON_CNTL2
++#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
++#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
++#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
++#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
++#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
++#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
++#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
++#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
++//DC_PERFMON11_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
++#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
++//DC_PERFMON11_PERFMON_CVALUE_LOW
++#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
++#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
++//DC_PERFMON11_PERFMON_HI
++#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
++#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
++#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
++#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
++//DC_PERFMON11_PERFMON_LOW
++#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
++#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
++//DPP_TOP1_DPP_CONTROL
++#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
++#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
++#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
++#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
++#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT                                         0xe
++#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0x10
++#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x12
++#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x14
++#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
++#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
++#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
++#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
++#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
++#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK                                           0x00004000L
++#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00010000L
++#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00040000L
++#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00100000L
++#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0xF0000000L
++//DPP_TOP1_DPP_SOFT_RESET
++#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
++#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
++#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
++#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
++#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
++#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
++#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
++#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
++//DPP_TOP1_DPP_CRC_VAL_R_G
++#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
++#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
++#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
++#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
++//DPP_TOP1_DPP_CRC_VAL_B_A
++#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
++#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
++#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
++#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
++//DPP_TOP1_DPP_CRC_CTRL
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT                                                 0x6
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x7
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x8
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0xa
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xc
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xf
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK                                                   0x00000040L
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000080L
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000300L
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000C00L
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00007000L
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x00008000L
++#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
++//DPP_TOP1_HOST_READ_CONTROL
++#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
++#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
++
++
++// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
++//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT
++#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
++#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
++//CNVC_CFG1_FORMAT_CONTROL
++#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
++#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
++#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
++#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
++#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
++#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
++#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
++#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
++#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
++#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
++#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
++#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
++#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
++#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
++#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
++#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
++//CNVC_CFG1_FCNV_FP_BIAS_R
++#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
++#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
++//CNVC_CFG1_FCNV_FP_BIAS_G
++#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
++#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
++//CNVC_CFG1_FCNV_FP_BIAS_B
++#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
++#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
++//CNVC_CFG1_FCNV_FP_SCALE_R
++#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
++#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
++//CNVC_CFG1_FCNV_FP_SCALE_G
++#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
++#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
++//CNVC_CFG1_FCNV_FP_SCALE_B
++#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
++#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
++//CNVC_CFG1_COLOR_KEYER_CONTROL
++#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
++#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
++#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
++#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
++//CNVC_CFG1_COLOR_KEYER_ALPHA
++#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
++#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
++#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
++#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
++//CNVC_CFG1_COLOR_KEYER_RED
++#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
++#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
++#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
++#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
++//CNVC_CFG1_COLOR_KEYER_GREEN
++#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
++#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
++#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
++#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
++//CNVC_CFG1_COLOR_KEYER_BLUE
++#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
++#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
++#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
++#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
++//CNVC_CFG1_ALPHA_2BIT_LUT
++#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
++#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
++#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
++#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
++#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
++#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
++#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
++#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
++
++
++// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
++//CNVC_CUR1_CURSOR0_CONTROL
++#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
++#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
++#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
++#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
++#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
++#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
++#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
++#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
++#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
++#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
++#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
++#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
++#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
++#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
++//CNVC_CUR1_CURSOR0_COLOR0
++#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
++#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
++//CNVC_CUR1_CURSOR0_COLOR1
++#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
++#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
++//CNVC_CUR1_CURSOR0_FP_SCALE_BIAS
++#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
++#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
++#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
++#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
++
++
++// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
++//DSCL1_SCL_COEF_RAM_TAP_SELECT
++#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
++#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
++#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
++#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
++#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
++#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
++//DSCL1_SCL_COEF_RAM_TAP_DATA
++#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
++#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
++#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
++#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
++#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
++#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
++#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
++#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
++//DSCL1_SCL_MODE
++#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
++#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
++#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
++#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
++#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
++#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
++#define DSCL1_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
++#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
++#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
++#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
++#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
++#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
++//DSCL1_SCL_TAP_CONTROL
++#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
++#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
++#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
++#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
++#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
++#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
++#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
++#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
++//DSCL1_DSCL_CONTROL
++#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
++#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
++//DSCL1_DSCL_2TAP_CONTROL
++#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
++#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
++#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
++#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
++#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
++#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
++#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
++#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
++#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
++#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
++#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
++#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
++//DSCL1_SCL_MANUAL_REPLICATE_CONTROL
++#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
++#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
++#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
++#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
++//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO
++#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
++#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x03FFFFFFL
++//DSCL1_SCL_HORZ_FILTER_INIT
++#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
++#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
++#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
++#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
++//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C
++#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
++#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x03FFFFFFL
++//DSCL1_SCL_HORZ_FILTER_INIT_C
++#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
++#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
++#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
++#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
++//DSCL1_SCL_VERT_FILTER_SCALE_RATIO
++#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
++#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x03FFFFFFL
++//DSCL1_SCL_VERT_FILTER_INIT
++#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
++#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
++#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
++#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
++//DSCL1_SCL_VERT_FILTER_INIT_BOT
++#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
++#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
++#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
++#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
++//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C
++#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
++#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x03FFFFFFL
++//DSCL1_SCL_VERT_FILTER_INIT_C
++#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
++#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
++#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
++#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
++//DSCL1_SCL_VERT_FILTER_INIT_BOT_C
++#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
++#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
++#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
++#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
++//DSCL1_SCL_BLACK_OFFSET
++#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT                                                 0x0
++#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT                                                  0x10
++#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK                                                   0x0000FFFFL
++#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK                                                    0xFFFF0000L
++//DSCL1_DSCL_UPDATE
++#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
++#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
++//DSCL1_DSCL_AUTOCAL
++#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
++#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
++#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
++#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
++#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
++#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
++//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT
++#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
++#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
++#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
++#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
++//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM
++#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
++#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
++#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
++#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
++//DSCL1_OTG_H_BLANK
++#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
++#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
++#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
++#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
++//DSCL1_OTG_V_BLANK
++#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
++#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
++#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
++#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
++//DSCL1_RECOUT_START
++#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
++#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
++#define DSCL1_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
++#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
++//DSCL1_RECOUT_SIZE
++#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
++#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
++#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
++#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
++//DSCL1_MPC_SIZE
++#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
++#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
++#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
++#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
++//DSCL1_LB_DATA_FORMAT
++#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
++#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
++#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
++#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
++//DSCL1_LB_MEMORY_CTRL
++#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
++#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
++#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
++#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
++#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
++#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
++#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
++#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
++//DSCL1_LB_V_COUNTER
++#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
++#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
++#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
++#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
++//DSCL1_DSCL_MEM_PWR_CTRL
++#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
++#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
++#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
++#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
++#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
++//DSCL1_DSCL_MEM_PWR_STATUS
++#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
++#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
++#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
++#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
++#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
++#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
++#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
++#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
++#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
++#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
++#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
++#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
++#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
++#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
++//DSCL1_OBUF_CONTROL
++#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
++#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x4
++#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0xc
++#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x1c
++#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
++#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000010L
++#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00001000L
++#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0xF0000000L
++//DSCL1_OBUF_MEM_PWR_CTRL
++#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
++#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
++#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
++#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
++#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
++#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
++#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
++#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
++
++
++// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
++//CM1_CM_CONTROL
++#define CM1_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
++#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
++#define CM1_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
++#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
++//CM1_CM_ICSC_CONTROL
++#define CM1_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT                                                              0x0
++#define CM1_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK                                                                0x00000003L
++//CM1_CM_ICSC_C11_C12
++#define CM1_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT                                                               0x0
++#define CM1_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT                                                               0x10
++#define CM1_CM_ICSC_C11_C12__CM_ICSC_C11_MASK                                                                 0x0000FFFFL
++#define CM1_CM_ICSC_C11_C12__CM_ICSC_C12_MASK                                                                 0xFFFF0000L
++//CM1_CM_ICSC_C13_C14
++#define CM1_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT                                                               0x0
++#define CM1_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT                                                               0x10
++#define CM1_CM_ICSC_C13_C14__CM_ICSC_C13_MASK                                                                 0x0000FFFFL
++#define CM1_CM_ICSC_C13_C14__CM_ICSC_C14_MASK                                                                 0xFFFF0000L
++//CM1_CM_ICSC_C21_C22
++#define CM1_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT                                                               0x0
++#define CM1_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT                                                               0x10
++#define CM1_CM_ICSC_C21_C22__CM_ICSC_C21_MASK                                                                 0x0000FFFFL
++#define CM1_CM_ICSC_C21_C22__CM_ICSC_C22_MASK                                                                 0xFFFF0000L
++//CM1_CM_ICSC_C23_C24
++#define CM1_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT                                                               0x0
++#define CM1_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT                                                               0x10
++#define CM1_CM_ICSC_C23_C24__CM_ICSC_C23_MASK                                                                 0x0000FFFFL
++#define CM1_CM_ICSC_C23_C24__CM_ICSC_C24_MASK                                                                 0xFFFF0000L
++//CM1_CM_ICSC_C31_C32
++#define CM1_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT                                                               0x0
++#define CM1_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT                                                               0x10
++#define CM1_CM_ICSC_C31_C32__CM_ICSC_C31_MASK                                                                 0x0000FFFFL
++#define CM1_CM_ICSC_C31_C32__CM_ICSC_C32_MASK                                                                 0xFFFF0000L
++//CM1_CM_ICSC_C33_C34
++#define CM1_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT                                                               0x0
++#define CM1_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT                                                               0x10
++#define CM1_CM_ICSC_C33_C34__CM_ICSC_C33_MASK                                                                 0x0000FFFFL
++#define CM1_CM_ICSC_C33_C34__CM_ICSC_C34_MASK                                                                 0xFFFF0000L
++//CM1_CM_ICSC_B_C11_C12
++#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT                                                           0x0
++#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT                                                           0x10
++#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK                                                             0x0000FFFFL
++#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK                                                             0xFFFF0000L
++//CM1_CM_ICSC_B_C13_C14
++#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT                                                           0x0
++#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT                                                           0x10
++#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK                                                             0x0000FFFFL
++#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK                                                             0xFFFF0000L
++//CM1_CM_ICSC_B_C21_C22
++#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT                                                           0x0
++#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT                                                           0x10
++#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK                                                             0x0000FFFFL
++#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK                                                             0xFFFF0000L
++//CM1_CM_ICSC_B_C23_C24
++#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT                                                           0x0
++#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT                                                           0x10
++#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK                                                             0x0000FFFFL
++#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK                                                             0xFFFF0000L
++//CM1_CM_ICSC_B_C31_C32
++#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT                                                           0x0
++#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT                                                           0x10
++#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK                                                             0x0000FFFFL
++#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK                                                             0xFFFF0000L
++//CM1_CM_ICSC_B_C33_C34
++#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT                                                           0x0
++#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT                                                           0x10
++#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK                                                             0x0000FFFFL
++#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK                                                             0xFFFF0000L
++//CM1_CM_GAMUT_REMAP_CONTROL
++#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
++#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
++//CM1_CM_GAMUT_REMAP_C11_C12
++#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
++#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
++#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
++#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
++//CM1_CM_GAMUT_REMAP_C13_C14
++#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
++#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
++#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
++#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
++//CM1_CM_GAMUT_REMAP_C21_C22
++#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
++#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
++#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
++#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
++//CM1_CM_GAMUT_REMAP_C23_C24
++#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
++#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
++#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
++#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
++//CM1_CM_GAMUT_REMAP_C31_C32
++#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
++#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
++#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
++#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
++//CM1_CM_GAMUT_REMAP_C33_C34
++#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
++#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
++#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
++#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
++//CM1_CM_GAMUT_REMAP_B_C11_C12
++#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
++#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
++#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
++#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
++//CM1_CM_GAMUT_REMAP_B_C13_C14
++#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
++#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
++#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
++#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
++//CM1_CM_GAMUT_REMAP_B_C21_C22
++#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
++#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
++#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
++#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
++//CM1_CM_GAMUT_REMAP_B_C23_C24
++#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
++#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
++#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
++#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
++//CM1_CM_GAMUT_REMAP_B_C31_C32
++#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
++#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
++#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
++#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
++//CM1_CM_GAMUT_REMAP_B_C33_C34
++#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
++#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
++#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
++#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
++//CM1_CM_BIAS_CR_R
++#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
++#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
++//CM1_CM_BIAS_Y_G_CB_B
++#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
++#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
++#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
++#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
++//CM1_CM_DGAM_CONTROL
++#define CM1_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT                                                          0x0
++#define CM1_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK                                                            0x00000007L
++//CM1_CM_DGAM_LUT_INDEX
++#define CM1_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT                                                       0x0
++#define CM1_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK                                                         0x000001FFL
++//CM1_CM_DGAM_LUT_DATA
++#define CM1_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT                                                         0x0
++#define CM1_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK                                                           0x0007FFFFL
++//CM1_CM_DGAM_LUT_WRITE_EN_MASK
++#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT                                       0x0
++#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT                                           0x4
++#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT                                           0x8
++#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT                                     0xc
++#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK                                         0x00000007L
++#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK                                             0x00000010L
++#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK                                             0x00000700L
++#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK                                       0x00001000L
++//CM1_CM_DGAM_RAMA_START_CNTL_B
++#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT                                 0x0
++#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                         0x14
++#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK                                   0x0003FFFFL
++#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                           0x07F00000L
++//CM1_CM_DGAM_RAMA_START_CNTL_G
++#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT                                 0x0
++#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                         0x14
++#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK                                   0x0003FFFFL
++#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                           0x07F00000L
++//CM1_CM_DGAM_RAMA_START_CNTL_R
++#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT                                 0x0
++#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                         0x14
++#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK                                   0x0003FFFFL
++#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                           0x07F00000L
++//CM1_CM_DGAM_RAMA_SLOPE_CNTL_B
++#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT                          0x0
++#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                            0x0003FFFFL
++//CM1_CM_DGAM_RAMA_SLOPE_CNTL_G
++#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT                          0x0
++#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                            0x0003FFFFL
++//CM1_CM_DGAM_RAMA_SLOPE_CNTL_R
++#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT                          0x0
++#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                            0x0003FFFFL
++//CM1_CM_DGAM_RAMA_END_CNTL1_B
++#define CM1_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT                                    0x0
++#define CM1_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK                                      0x0000FFFFL
++//CM1_CM_DGAM_RAMA_END_CNTL2_B
++#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                              0x0
++#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                               0x10
++#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                                0x0000FFFFL
++#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK                                 0xFFFF0000L
++//CM1_CM_DGAM_RAMA_END_CNTL1_G
++#define CM1_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT                                    0x0
++#define CM1_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK                                      0x0000FFFFL
++//CM1_CM_DGAM_RAMA_END_CNTL2_G
++#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                              0x0
++#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                               0x10
++#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                                0x0000FFFFL
++#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK                                 0xFFFF0000L
++//CM1_CM_DGAM_RAMA_END_CNTL1_R
++#define CM1_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT                                    0x0
++#define CM1_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK                                      0x0000FFFFL
++//CM1_CM_DGAM_RAMA_END_CNTL2_R
++#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                              0x0
++#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                               0x10
++#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                                0x0000FFFFL
++#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK                                 0xFFFF0000L
++//CM1_CM_DGAM_RAMA_REGION_0_1
++#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                               0x0
++#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                             0xc
++#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                               0x10
++#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                               0x70000000L
++//CM1_CM_DGAM_RAMA_REGION_2_3
++#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                               0x0
++#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                             0xc
++#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                               0x10
++#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                               0x70000000L
++//CM1_CM_DGAM_RAMA_REGION_4_5
++#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                               0x0
++#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                             0xc
++#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                               0x10
++#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                               0x70000000L
++//CM1_CM_DGAM_RAMA_REGION_6_7
++#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                               0x0
++#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                             0xc
++#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                               0x10
++#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                               0x70000000L
++//CM1_CM_DGAM_RAMA_REGION_8_9
++#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                               0x0
++#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                             0xc
++#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                               0x10
++#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                               0x70000000L
++//CM1_CM_DGAM_RAMA_REGION_10_11
++#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                            0x0
++#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                          0xc
++#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                            0x10
++#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                              0x000001FFL
++#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                            0x70000000L
++//CM1_CM_DGAM_RAMA_REGION_12_13
++#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                            0x0
++#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                          0xc
++#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                            0x10
++#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                              0x000001FFL
++#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                            0x70000000L
++//CM1_CM_DGAM_RAMA_REGION_14_15
++#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                            0x0
++#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                          0xc
++#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                            0x10
++#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                              0x000001FFL
++#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                            0x70000000L
++//CM1_CM_DGAM_RAMB_START_CNTL_B
++#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT                                 0x0
++#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                         0x14
++#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK                                   0x0003FFFFL
++#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                           0x07F00000L
++//CM1_CM_DGAM_RAMB_START_CNTL_G
++#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT                                 0x0
++#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                         0x14
++#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK                                   0x0003FFFFL
++#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                           0x07F00000L
++//CM1_CM_DGAM_RAMB_START_CNTL_R
++#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT                                 0x0
++#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                         0x14
++#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK                                   0x0003FFFFL
++#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                           0x07F00000L
++//CM1_CM_DGAM_RAMB_SLOPE_CNTL_B
++#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT                          0x0
++#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                            0x0003FFFFL
++//CM1_CM_DGAM_RAMB_SLOPE_CNTL_G
++#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT                          0x0
++#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                            0x0003FFFFL
++//CM1_CM_DGAM_RAMB_SLOPE_CNTL_R
++#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT                          0x0
++#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                            0x0003FFFFL
++//CM1_CM_DGAM_RAMB_END_CNTL1_B
++#define CM1_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT                                    0x0
++#define CM1_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK                                      0x0000FFFFL
++//CM1_CM_DGAM_RAMB_END_CNTL2_B
++#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                              0x0
++#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                               0x10
++#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                                0x0000FFFFL
++#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK                                 0xFFFF0000L
++//CM1_CM_DGAM_RAMB_END_CNTL1_G
++#define CM1_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT                                    0x0
++#define CM1_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK                                      0x0000FFFFL
++//CM1_CM_DGAM_RAMB_END_CNTL2_G
++#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                              0x0
++#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                               0x10
++#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                                0x0000FFFFL
++#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK                                 0xFFFF0000L
++//CM1_CM_DGAM_RAMB_END_CNTL1_R
++#define CM1_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT                                    0x0
++#define CM1_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK                                      0x0000FFFFL
++//CM1_CM_DGAM_RAMB_END_CNTL2_R
++#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                              0x0
++#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                               0x10
++#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                                0x0000FFFFL
++#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK                                 0xFFFF0000L
++//CM1_CM_DGAM_RAMB_REGION_0_1
++#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                               0x0
++#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                             0xc
++#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                               0x10
++#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                               0x70000000L
++//CM1_CM_DGAM_RAMB_REGION_2_3
++#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                               0x0
++#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                             0xc
++#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                               0x10
++#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                               0x70000000L
++//CM1_CM_DGAM_RAMB_REGION_4_5
++#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                               0x0
++#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                             0xc
++#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                               0x10
++#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                               0x70000000L
++//CM1_CM_DGAM_RAMB_REGION_6_7
++#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                               0x0
++#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                             0xc
++#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                               0x10
++#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                               0x70000000L
++//CM1_CM_DGAM_RAMB_REGION_8_9
++#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                               0x0
++#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                             0xc
++#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                               0x10
++#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                               0x70000000L
++//CM1_CM_DGAM_RAMB_REGION_10_11
++#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                            0x0
++#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                          0xc
++#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                            0x10
++#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                              0x000001FFL
++#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                            0x70000000L
++//CM1_CM_DGAM_RAMB_REGION_12_13
++#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                            0x0
++#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                          0xc
++#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                            0x10
++#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                              0x000001FFL
++#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                            0x70000000L
++//CM1_CM_DGAM_RAMB_REGION_14_15
++#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                            0x0
++#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                          0xc
++#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                            0x10
++#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                              0x000001FFL
++#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                            0x70000000L
++//CM1_CM_BLNDGAM_CONTROL
++#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT                                                    0x0
++#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK                                                      0x00000003L
++//CM1_CM_BLNDGAM_LUT_INDEX
++#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
++#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
++//CM1_CM_BLNDGAM_LUT_DATA
++#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
++#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0007FFFFL
++//CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK
++#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT                                 0x0
++#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT                                     0x4
++#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT                                     0x8
++#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK                                   0x00000007L
++#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK                                       0x00000010L
++#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK                                       0x00000300L
++//CM1_CM_BLNDGAM_RAMA_START_CNTL_B
++#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
++#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
++#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
++#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
++//CM1_CM_BLNDGAM_RAMA_START_CNTL_G
++#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
++#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
++#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
++#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
++//CM1_CM_BLNDGAM_RAMA_START_CNTL_R
++#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
++#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
++#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
++#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
++//CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B
++#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT                    0x0
++#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                      0x0003FFFFL
++//CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G
++#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT                    0x0
++#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                      0x0003FFFFL
++//CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R
++#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT                    0x0
++#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                      0x0003FFFFL
++//CM1_CM_BLNDGAM_RAMA_END_CNTL1_B
++#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
++#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
++//CM1_CM_BLNDGAM_RAMA_END_CNTL2_B
++#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x0
++#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x10
++#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0x0000FFFFL
++#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0xFFFF0000L
++//CM1_CM_BLNDGAM_RAMA_END_CNTL1_G
++#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
++#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
++//CM1_CM_BLNDGAM_RAMA_END_CNTL2_G
++#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x0
++#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x10
++#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0x0000FFFFL
++#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0xFFFF0000L
++//CM1_CM_BLNDGAM_RAMA_END_CNTL1_R
++#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
++#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
++//CM1_CM_BLNDGAM_RAMA_END_CNTL2_R
++#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x0
++#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x10
++#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0x0000FFFFL
++#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0xFFFF0000L
++//CM1_CM_BLNDGAM_RAMA_REGION_0_1
++#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
++#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
++#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
++#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
++#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
++//CM1_CM_BLNDGAM_RAMA_REGION_2_3
++#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
++#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
++#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
++#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
++#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
++//CM1_CM_BLNDGAM_RAMA_REGION_4_5
++#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
++#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
++#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
++#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
++#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
++//CM1_CM_BLNDGAM_RAMA_REGION_6_7
++#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
++#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
++#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
++#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
++#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
++//CM1_CM_BLNDGAM_RAMA_REGION_8_9
++#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
++#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
++#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
++#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
++#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
++//CM1_CM_BLNDGAM_RAMA_REGION_10_11
++#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMA_REGION_12_13
++#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMA_REGION_14_15
++#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMA_REGION_16_17
++#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMA_REGION_18_19
++#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMA_REGION_20_21
++#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMA_REGION_22_23
++#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMA_REGION_24_25
++#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMA_REGION_26_27
++#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMA_REGION_28_29
++#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMA_REGION_30_31
++#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMA_REGION_32_33
++#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMB_START_CNTL_B
++#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
++#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
++#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
++#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
++//CM1_CM_BLNDGAM_RAMB_START_CNTL_G
++#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
++#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
++#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
++#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
++//CM1_CM_BLNDGAM_RAMB_START_CNTL_R
++#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
++#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
++#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
++#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
++//CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B
++#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT                    0x0
++#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                      0x0003FFFFL
++//CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G
++#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT                    0x0
++#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                      0x0003FFFFL
++//CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R
++#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT                    0x0
++#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                      0x0003FFFFL
++//CM1_CM_BLNDGAM_RAMB_END_CNTL1_B
++#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
++#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
++//CM1_CM_BLNDGAM_RAMB_END_CNTL2_B
++#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x0
++#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x10
++#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0x0000FFFFL
++#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0xFFFF0000L
++//CM1_CM_BLNDGAM_RAMB_END_CNTL1_G
++#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
++#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
++//CM1_CM_BLNDGAM_RAMB_END_CNTL2_G
++#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x0
++#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x10
++#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0x0000FFFFL
++#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0xFFFF0000L
++//CM1_CM_BLNDGAM_RAMB_END_CNTL1_R
++#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
++#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
++//CM1_CM_BLNDGAM_RAMB_END_CNTL2_R
++#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x0
++#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x10
++#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0x0000FFFFL
++#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0xFFFF0000L
++//CM1_CM_BLNDGAM_RAMB_REGION_0_1
++#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
++#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
++#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
++#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
++#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
++//CM1_CM_BLNDGAM_RAMB_REGION_2_3
++#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
++#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
++#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
++#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
++#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
++//CM1_CM_BLNDGAM_RAMB_REGION_4_5
++#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
++#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
++#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
++#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
++#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
++//CM1_CM_BLNDGAM_RAMB_REGION_6_7
++#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
++#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
++#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
++#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
++#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
++//CM1_CM_BLNDGAM_RAMB_REGION_8_9
++#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
++#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
++#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
++#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
++#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
++//CM1_CM_BLNDGAM_RAMB_REGION_10_11
++#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMB_REGION_12_13
++#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMB_REGION_14_15
++#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMB_REGION_16_17
++#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMB_REGION_18_19
++#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMB_REGION_20_21
++#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMB_REGION_22_23
++#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMB_REGION_24_25
++#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMB_REGION_26_27
++#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMB_REGION_28_29
++#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMB_REGION_30_31
++#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_BLNDGAM_RAMB_REGION_32_33
++#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
++#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
++#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
++#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
++#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
++//CM1_CM_HDR_MULT_COEF
++#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
++#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
++//CM1_CM_MEM_PWR_CTRL
++#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT                                                      0x0
++#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT                                                        0x2
++#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
++#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
++#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK                                                        0x00000003L
++#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK                                                          0x00000004L
++#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
++#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
++//CM1_CM_MEM_PWR_STATUS
++#define CM1_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT                                                    0x0
++#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
++#define CM1_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK                                                      0x00000003L
++#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
++//CM1_CM_DEALPHA
++#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
++#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
++//CM1_CM_COEF_FORMAT
++#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
++#define CM1_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT                                                        0x4
++#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
++#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
++#define CM1_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK                                                          0x00000010L
++#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
++//CM1_CM_SHAPER_CONTROL
++#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
++#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
++//CM1_CM_SHAPER_OFFSET_R
++#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
++#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
++//CM1_CM_SHAPER_OFFSET_G
++#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
++#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
++//CM1_CM_SHAPER_OFFSET_B
++#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
++#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
++//CM1_CM_SHAPER_SCALE_R
++#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
++#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
++//CM1_CM_SHAPER_SCALE_G_B
++#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
++#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
++#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
++#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
++//CM1_CM_SHAPER_LUT_INDEX
++#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
++#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
++//CM1_CM_SHAPER_LUT_DATA
++#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
++#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
++//CM1_CM_SHAPER_LUT_WRITE_EN_MASK
++#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
++#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
++#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT                                       0x8
++#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
++#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
++#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK                                         0x00000300L
++//CM1_CM_SHAPER_RAMA_START_CNTL_B
++#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
++#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
++#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
++#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
++//CM1_CM_SHAPER_RAMA_START_CNTL_G
++#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
++#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
++#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
++#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
++//CM1_CM_SHAPER_RAMA_START_CNTL_R
++#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
++#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
++#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
++#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
++//CM1_CM_SHAPER_RAMA_END_CNTL_B
++#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
++#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
++#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
++#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
++//CM1_CM_SHAPER_RAMA_END_CNTL_G
++#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
++#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
++#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
++#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
++//CM1_CM_SHAPER_RAMA_END_CNTL_R
++#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
++#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
++#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
++#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
++//CM1_CM_SHAPER_RAMA_REGION_0_1
++#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
++#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
++#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
++#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
++#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
++//CM1_CM_SHAPER_RAMA_REGION_2_3
++#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
++#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
++#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
++#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
++#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
++//CM1_CM_SHAPER_RAMA_REGION_4_5
++#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
++#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
++#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
++#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
++#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
++//CM1_CM_SHAPER_RAMA_REGION_6_7
++#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
++#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
++#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
++#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
++#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
++//CM1_CM_SHAPER_RAMA_REGION_8_9
++#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
++#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
++#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
++#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
++#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
++//CM1_CM_SHAPER_RAMA_REGION_10_11
++#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMA_REGION_12_13
++#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMA_REGION_14_15
++#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMA_REGION_16_17
++#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMA_REGION_18_19
++#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMA_REGION_20_21
++#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMA_REGION_22_23
++#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMA_REGION_24_25
++#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMA_REGION_26_27
++#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMA_REGION_28_29
++#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMA_REGION_30_31
++#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMA_REGION_32_33
++#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMB_START_CNTL_B
++#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
++#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
++#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
++#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
++//CM1_CM_SHAPER_RAMB_START_CNTL_G
++#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
++#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
++#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
++#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
++//CM1_CM_SHAPER_RAMB_START_CNTL_R
++#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
++#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
++#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
++#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
++//CM1_CM_SHAPER_RAMB_END_CNTL_B
++#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
++#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
++#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
++#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
++//CM1_CM_SHAPER_RAMB_END_CNTL_G
++#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
++#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
++#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
++#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
++//CM1_CM_SHAPER_RAMB_END_CNTL_R
++#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
++#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
++#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
++#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
++//CM1_CM_SHAPER_RAMB_REGION_0_1
++#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
++#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
++#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
++#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
++#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
++//CM1_CM_SHAPER_RAMB_REGION_2_3
++#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
++#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
++#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
++#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
++#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
++//CM1_CM_SHAPER_RAMB_REGION_4_5
++#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
++#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
++#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
++#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
++#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
++//CM1_CM_SHAPER_RAMB_REGION_6_7
++#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
++#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
++#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
++#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
++#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
++//CM1_CM_SHAPER_RAMB_REGION_8_9
++#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
++#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
++#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
++#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
++#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
++//CM1_CM_SHAPER_RAMB_REGION_10_11
++#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMB_REGION_12_13
++#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMB_REGION_14_15
++#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMB_REGION_16_17
++#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMB_REGION_18_19
++#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMB_REGION_20_21
++#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMB_REGION_22_23
++#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMB_REGION_24_25
++#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMB_REGION_26_27
++#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMB_REGION_28_29
++#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMB_REGION_30_31
++#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_SHAPER_RAMB_REGION_32_33
++#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
++#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
++#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
++#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
++#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
++//CM1_CM_MEM_PWR_CTRL2
++#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
++#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
++#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
++#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
++#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
++#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
++#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
++#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
++//CM1_CM_MEM_PWR_STATUS2
++#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
++#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
++#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
++#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
++//CM1_CM_3DLUT_MODE
++#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
++#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
++#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
++#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
++//CM1_CM_3DLUT_INDEX
++#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
++#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
++//CM1_CM_3DLUT_DATA
++#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
++#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
++#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
++#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
++//CM1_CM_3DLUT_DATA_30BIT
++#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
++#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
++//CM1_CM_3DLUT_READ_WRITE_CONTROL
++#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
++#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
++#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
++#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT                                        0xc
++#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
++#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
++#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
++#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
++#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK                                          0x00003000L
++#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
++//CM1_CM_3DLUT_OUT_NORM_FACTOR
++#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
++#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
++//CM1_CM_3DLUT_OUT_OFFSET_R
++#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
++#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
++#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
++#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
++//CM1_CM_3DLUT_OUT_OFFSET_G
++#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
++#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
++#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
++#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
++//CM1_CM_3DLUT_OUT_OFFSET_B
++#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
++#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
++#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
++#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
++//CM1_CM_TEST_DEBUG_INDEX
++#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
++#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
++#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
++#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
++//CM1_CM_TEST_DEBUG_DATA
++#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
++#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON12_PERFCOUNTER_CNTL
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
++#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
++//DC_PERFMON12_PERFCOUNTER_CNTL2
++#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
++#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
++#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
++#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
++#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
++#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
++#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
++#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
++#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
++#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
++//DC_PERFMON12_PERFCOUNTER_STATE
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
++#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
++//DC_PERFMON12_PERFMON_CNTL
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
++#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
++//DC_PERFMON12_PERFMON_CNTL2
++#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
++#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
++#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
++#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
++#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
++#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
++#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
++#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
++//DC_PERFMON12_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
++#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
++//DC_PERFMON12_PERFMON_CVALUE_LOW
++#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
++#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
++//DC_PERFMON12_PERFMON_HI
++#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
++#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
++#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
++#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
++//DC_PERFMON12_PERFMON_LOW
++#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
++#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
++//DPP_TOP2_DPP_CONTROL
++#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
++#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
++#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
++#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
++#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT                                         0xe
++#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0x10
++#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x12
++#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x14
++#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
++#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
++#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
++#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
++#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
++#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK                                           0x00004000L
++#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00010000L
++#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00040000L
++#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00100000L
++#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0xF0000000L
++//DPP_TOP2_DPP_SOFT_RESET
++#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
++#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
++#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
++#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
++#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
++#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
++#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
++#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
++//DPP_TOP2_DPP_CRC_VAL_R_G
++#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
++#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
++#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
++#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
++//DPP_TOP2_DPP_CRC_VAL_B_A
++#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
++#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
++#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
++#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
++//DPP_TOP2_DPP_CRC_CTRL
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT                                                 0x6
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x7
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x8
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0xa
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xc
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xf
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK                                                   0x00000040L
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000080L
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000300L
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000C00L
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00007000L
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x00008000L
++#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
++//DPP_TOP2_HOST_READ_CONTROL
++#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
++#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
++
++
++// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
++//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT
++#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
++#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
++//CNVC_CFG2_FORMAT_CONTROL
++#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
++#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
++#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
++#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
++#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
++#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
++#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
++#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
++#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
++#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
++#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
++#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
++#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
++#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
++#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
++#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
++//CNVC_CFG2_FCNV_FP_BIAS_R
++#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
++#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
++//CNVC_CFG2_FCNV_FP_BIAS_G
++#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
++#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
++//CNVC_CFG2_FCNV_FP_BIAS_B
++#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
++#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
++//CNVC_CFG2_FCNV_FP_SCALE_R
++#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
++#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
++//CNVC_CFG2_FCNV_FP_SCALE_G
++#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
++#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
++//CNVC_CFG2_FCNV_FP_SCALE_B
++#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
++#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
++//CNVC_CFG2_COLOR_KEYER_CONTROL
++#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
++#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
++#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
++#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
++//CNVC_CFG2_COLOR_KEYER_ALPHA
++#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
++#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
++#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
++#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
++//CNVC_CFG2_COLOR_KEYER_RED
++#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
++#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
++#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
++#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
++//CNVC_CFG2_COLOR_KEYER_GREEN
++#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
++#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
++#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
++#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
++//CNVC_CFG2_COLOR_KEYER_BLUE
++#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
++#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
++#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
++#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
++//CNVC_CFG2_ALPHA_2BIT_LUT
++#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
++#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
++#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
++#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
++#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
++#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
++#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
++#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
++
++
++// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
++//CNVC_CUR2_CURSOR0_CONTROL
++#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
++#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
++#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
++#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
++#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
++#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
++#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
++#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
++#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
++#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
++#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
++#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
++#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
++#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
++//CNVC_CUR2_CURSOR0_COLOR0
++#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
++#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
++//CNVC_CUR2_CURSOR0_COLOR1
++#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
++#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
++//CNVC_CUR2_CURSOR0_FP_SCALE_BIAS
++#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
++#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
++#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
++#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
++
++
++// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
++//DSCL2_SCL_COEF_RAM_TAP_SELECT
++#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
++#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
++#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
++#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
++#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
++#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
++//DSCL2_SCL_COEF_RAM_TAP_DATA
++#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
++#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
++#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
++#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
++#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
++#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
++#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
++#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
++//DSCL2_SCL_MODE
++#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
++#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
++#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
++#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
++#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
++#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
++#define DSCL2_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
++#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
++#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
++#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
++#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
++#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
++//DSCL2_SCL_TAP_CONTROL
++#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
++#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
++#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
++#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
++#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
++#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
++#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
++#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
++//DSCL2_DSCL_CONTROL
++#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
++#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
++//DSCL2_DSCL_2TAP_CONTROL
++#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
++#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
++#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
++#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
++#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
++#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
++#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
++#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
++#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
++#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
++#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
++#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
++//DSCL2_SCL_MANUAL_REPLICATE_CONTROL
++#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
++#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
++#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
++#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
++//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO
++#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
++#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x03FFFFFFL
++//DSCL2_SCL_HORZ_FILTER_INIT
++#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
++#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
++#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
++#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
++//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C
++#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
++#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x03FFFFFFL
++//DSCL2_SCL_HORZ_FILTER_INIT_C
++#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
++#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
++#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
++#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
++//DSCL2_SCL_VERT_FILTER_SCALE_RATIO
++#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
++#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x03FFFFFFL
++//DSCL2_SCL_VERT_FILTER_INIT
++#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
++#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
++#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
++#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
++//DSCL2_SCL_VERT_FILTER_INIT_BOT
++#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
++#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
++#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
++#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
++//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C
++#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
++#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x03FFFFFFL
++//DSCL2_SCL_VERT_FILTER_INIT_C
++#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
++#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
++#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
++#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
++//DSCL2_SCL_VERT_FILTER_INIT_BOT_C
++#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
++#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
++#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
++#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
++//DSCL2_SCL_BLACK_OFFSET
++#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT                                                 0x0
++#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT                                                  0x10
++#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK                                                   0x0000FFFFL
++#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK                                                    0xFFFF0000L
++//DSCL2_DSCL_UPDATE
++#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
++#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
++//DSCL2_DSCL_AUTOCAL
++#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
++#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
++#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
++#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
++#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
++#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
++//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT
++#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
++#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
++#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
++#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
++//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM
++#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
++#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
++#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
++#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
++//DSCL2_OTG_H_BLANK
++#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
++#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
++#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
++#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
++//DSCL2_OTG_V_BLANK
++#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
++#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
++#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
++#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
++//DSCL2_RECOUT_START
++#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
++#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
++#define DSCL2_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
++#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
++//DSCL2_RECOUT_SIZE
++#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
++#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
++#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
++#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
++//DSCL2_MPC_SIZE
++#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
++#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
++#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
++#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
++//DSCL2_LB_DATA_FORMAT
++#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
++#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
++#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
++#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
++//DSCL2_LB_MEMORY_CTRL
++#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
++#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
++#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
++#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
++#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
++#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
++#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
++#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
++//DSCL2_LB_V_COUNTER
++#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
++#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
++#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
++#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
++//DSCL2_DSCL_MEM_PWR_CTRL
++#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
++#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
++#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
++#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
++#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
++//DSCL2_DSCL_MEM_PWR_STATUS
++#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
++#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
++#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
++#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
++#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
++#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
++#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
++#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
++#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
++#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
++#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
++#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
++#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
++#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
++//DSCL2_OBUF_CONTROL
++#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
++#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x4
++#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0xc
++#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x1c
++#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
++#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000010L
++#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00001000L
++#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0xF0000000L
++//DSCL2_OBUF_MEM_PWR_CTRL
++#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
++#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
++#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
++#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
++#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
++#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
++#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
++#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
++
++
++// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
++//CM2_CM_CONTROL
++#define CM2_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
++#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
++#define CM2_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
++#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
++//CM2_CM_ICSC_CONTROL
++#define CM2_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT                                                              0x0
++#define CM2_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK                                                                0x00000003L
++//CM2_CM_ICSC_C11_C12
++#define CM2_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT                                                               0x0
++#define CM2_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT                                                               0x10
++#define CM2_CM_ICSC_C11_C12__CM_ICSC_C11_MASK                                                                 0x0000FFFFL
++#define CM2_CM_ICSC_C11_C12__CM_ICSC_C12_MASK                                                                 0xFFFF0000L
++//CM2_CM_ICSC_C13_C14
++#define CM2_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT                                                               0x0
++#define CM2_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT                                                               0x10
++#define CM2_CM_ICSC_C13_C14__CM_ICSC_C13_MASK                                                                 0x0000FFFFL
++#define CM2_CM_ICSC_C13_C14__CM_ICSC_C14_MASK                                                                 0xFFFF0000L
++//CM2_CM_ICSC_C21_C22
++#define CM2_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT                                                               0x0
++#define CM2_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT                                                               0x10
++#define CM2_CM_ICSC_C21_C22__CM_ICSC_C21_MASK                                                                 0x0000FFFFL
++#define CM2_CM_ICSC_C21_C22__CM_ICSC_C22_MASK                                                                 0xFFFF0000L
++//CM2_CM_ICSC_C23_C24
++#define CM2_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT                                                               0x0
++#define CM2_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT                                                               0x10
++#define CM2_CM_ICSC_C23_C24__CM_ICSC_C23_MASK                                                                 0x0000FFFFL
++#define CM2_CM_ICSC_C23_C24__CM_ICSC_C24_MASK                                                                 0xFFFF0000L
++//CM2_CM_ICSC_C31_C32
++#define CM2_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT                                                               0x0
++#define CM2_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT                                                               0x10
++#define CM2_CM_ICSC_C31_C32__CM_ICSC_C31_MASK                                                                 0x0000FFFFL
++#define CM2_CM_ICSC_C31_C32__CM_ICSC_C32_MASK                                                                 0xFFFF0000L
++//CM2_CM_ICSC_C33_C34
++#define CM2_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT                                                               0x0
++#define CM2_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT                                                               0x10
++#define CM2_CM_ICSC_C33_C34__CM_ICSC_C33_MASK                                                                 0x0000FFFFL
++#define CM2_CM_ICSC_C33_C34__CM_ICSC_C34_MASK                                                                 0xFFFF0000L
++//CM2_CM_ICSC_B_C11_C12
++#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT                                                           0x0
++#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT                                                           0x10
++#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK                                                             0x0000FFFFL
++#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK                                                             0xFFFF0000L
++//CM2_CM_ICSC_B_C13_C14
++#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT                                                           0x0
++#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT                                                           0x10
++#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK                                                             0x0000FFFFL
++#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK                                                             0xFFFF0000L
++//CM2_CM_ICSC_B_C21_C22
++#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT                                                           0x0
++#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT                                                           0x10
++#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK                                                             0x0000FFFFL
++#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK                                                             0xFFFF0000L
++//CM2_CM_ICSC_B_C23_C24
++#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT                                                           0x0
++#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT                                                           0x10
++#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK                                                             0x0000FFFFL
++#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK                                                             0xFFFF0000L
++//CM2_CM_ICSC_B_C31_C32
++#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT                                                           0x0
++#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT                                                           0x10
++#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK                                                             0x0000FFFFL
++#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK                                                             0xFFFF0000L
++//CM2_CM_ICSC_B_C33_C34
++#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT                                                           0x0
++#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT                                                           0x10
++#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK                                                             0x0000FFFFL
++#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK                                                             0xFFFF0000L
++//CM2_CM_GAMUT_REMAP_CONTROL
++#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
++#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
++//CM2_CM_GAMUT_REMAP_C11_C12
++#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
++#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
++#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
++#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
++//CM2_CM_GAMUT_REMAP_C13_C14
++#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
++#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
++#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
++#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
++//CM2_CM_GAMUT_REMAP_C21_C22
++#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
++#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
++#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
++#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
++//CM2_CM_GAMUT_REMAP_C23_C24
++#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
++#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
++#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
++#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
++//CM2_CM_GAMUT_REMAP_C31_C32
++#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
++#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
++#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
++#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
++//CM2_CM_GAMUT_REMAP_C33_C34
++#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
++#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
++#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
++#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
++//CM2_CM_GAMUT_REMAP_B_C11_C12
++#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
++#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
++#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
++#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
++//CM2_CM_GAMUT_REMAP_B_C13_C14
++#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
++#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
++#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
++#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
++//CM2_CM_GAMUT_REMAP_B_C21_C22
++#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
++#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
++#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
++#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
++//CM2_CM_GAMUT_REMAP_B_C23_C24
++#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
++#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
++#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
++#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
++//CM2_CM_GAMUT_REMAP_B_C31_C32
++#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
++#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
++#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
++#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
++//CM2_CM_GAMUT_REMAP_B_C33_C34
++#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
++#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
++#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
++#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
++//CM2_CM_BIAS_CR_R
++#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
++#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
++//CM2_CM_BIAS_Y_G_CB_B
++#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
++#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
++#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
++#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
++//CM2_CM_DGAM_CONTROL
++#define CM2_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT                                                          0x0
++#define CM2_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK                                                            0x00000007L
++//CM2_CM_DGAM_LUT_INDEX
++#define CM2_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT                                                       0x0
++#define CM2_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK                                                         0x000001FFL
++//CM2_CM_DGAM_LUT_DATA
++#define CM2_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT                                                         0x0
++#define CM2_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK                                                           0x0007FFFFL
++//CM2_CM_DGAM_LUT_WRITE_EN_MASK
++#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT                                       0x0
++#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT                                           0x4
++#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT                                           0x8
++#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT                                     0xc
++#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK                                         0x00000007L
++#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK                                             0x00000010L
++#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK                                             0x00000700L
++#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK                                       0x00001000L
++//CM2_CM_DGAM_RAMA_START_CNTL_B
++#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT                                 0x0
++#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                         0x14
++#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK                                   0x0003FFFFL
++#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                           0x07F00000L
++//CM2_CM_DGAM_RAMA_START_CNTL_G
++#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT                                 0x0
++#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                         0x14
++#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK                                   0x0003FFFFL
++#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                           0x07F00000L
++//CM2_CM_DGAM_RAMA_START_CNTL_R
++#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT                                 0x0
++#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                         0x14
++#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK                                   0x0003FFFFL
++#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                           0x07F00000L
++//CM2_CM_DGAM_RAMA_SLOPE_CNTL_B
++#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT                          0x0
++#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                            0x0003FFFFL
++//CM2_CM_DGAM_RAMA_SLOPE_CNTL_G
++#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT                          0x0
++#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                            0x0003FFFFL
++//CM2_CM_DGAM_RAMA_SLOPE_CNTL_R
++#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT                          0x0
++#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                            0x0003FFFFL
++//CM2_CM_DGAM_RAMA_END_CNTL1_B
++#define CM2_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT                                    0x0
++#define CM2_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK                                      0x0000FFFFL
++//CM2_CM_DGAM_RAMA_END_CNTL2_B
++#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                              0x0
++#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                               0x10
++#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                                0x0000FFFFL
++#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK                                 0xFFFF0000L
++//CM2_CM_DGAM_RAMA_END_CNTL1_G
++#define CM2_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT                                    0x0
++#define CM2_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK                                      0x0000FFFFL
++//CM2_CM_DGAM_RAMA_END_CNTL2_G
++#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                              0x0
++#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                               0x10
++#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                                0x0000FFFFL
++#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK                                 0xFFFF0000L
++//CM2_CM_DGAM_RAMA_END_CNTL1_R
++#define CM2_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT                                    0x0
++#define CM2_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK                                      0x0000FFFFL
++//CM2_CM_DGAM_RAMA_END_CNTL2_R
++#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                              0x0
++#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                               0x10
++#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                                0x0000FFFFL
++#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK                                 0xFFFF0000L
++//CM2_CM_DGAM_RAMA_REGION_0_1
++#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                               0x0
++#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                             0xc
++#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                               0x10
++#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                               0x70000000L
++//CM2_CM_DGAM_RAMA_REGION_2_3
++#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                               0x0
++#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                             0xc
++#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                               0x10
++#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                               0x70000000L
++//CM2_CM_DGAM_RAMA_REGION_4_5
++#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                               0x0
++#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                             0xc
++#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                               0x10
++#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                               0x70000000L
++//CM2_CM_DGAM_RAMA_REGION_6_7
++#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                               0x0
++#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                             0xc
++#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                               0x10
++#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                               0x70000000L
++//CM2_CM_DGAM_RAMA_REGION_8_9
++#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                               0x0
++#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                             0xc
++#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                               0x10
++#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                               0x70000000L
++//CM2_CM_DGAM_RAMA_REGION_10_11
++#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                            0x0
++#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                          0xc
++#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                            0x10
++#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                              0x000001FFL
++#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                            0x70000000L
++//CM2_CM_DGAM_RAMA_REGION_12_13
++#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                            0x0
++#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                          0xc
++#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                            0x10
++#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                              0x000001FFL
++#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                            0x70000000L
++//CM2_CM_DGAM_RAMA_REGION_14_15
++#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                            0x0
++#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                          0xc
++#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                            0x10
++#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                              0x000001FFL
++#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                            0x70000000L
++//CM2_CM_DGAM_RAMB_START_CNTL_B
++#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT                                 0x0
++#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                         0x14
++#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK                                   0x0003FFFFL
++#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                           0x07F00000L
++//CM2_CM_DGAM_RAMB_START_CNTL_G
++#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT                                 0x0
++#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                         0x14
++#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK                                   0x0003FFFFL
++#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                           0x07F00000L
++//CM2_CM_DGAM_RAMB_START_CNTL_R
++#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT                                 0x0
++#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                         0x14
++#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK                                   0x0003FFFFL
++#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                           0x07F00000L
++//CM2_CM_DGAM_RAMB_SLOPE_CNTL_B
++#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT                          0x0
++#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                            0x0003FFFFL
++//CM2_CM_DGAM_RAMB_SLOPE_CNTL_G
++#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT                          0x0
++#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                            0x0003FFFFL
++//CM2_CM_DGAM_RAMB_SLOPE_CNTL_R
++#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT                          0x0
++#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                            0x0003FFFFL
++//CM2_CM_DGAM_RAMB_END_CNTL1_B
++#define CM2_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT                                    0x0
++#define CM2_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK                                      0x0000FFFFL
++//CM2_CM_DGAM_RAMB_END_CNTL2_B
++#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                              0x0
++#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                               0x10
++#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                                0x0000FFFFL
++#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK                                 0xFFFF0000L
++//CM2_CM_DGAM_RAMB_END_CNTL1_G
++#define CM2_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT                                    0x0
++#define CM2_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK                                      0x0000FFFFL
++//CM2_CM_DGAM_RAMB_END_CNTL2_G
++#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                              0x0
++#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                               0x10
++#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                                0x0000FFFFL
++#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK                                 0xFFFF0000L
++//CM2_CM_DGAM_RAMB_END_CNTL1_R
++#define CM2_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT                                    0x0
++#define CM2_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK                                      0x0000FFFFL
++//CM2_CM_DGAM_RAMB_END_CNTL2_R
++#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                              0x0
++#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                               0x10
++#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                                0x0000FFFFL
++#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK                                 0xFFFF0000L
++//CM2_CM_DGAM_RAMB_REGION_0_1
++#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                               0x0
++#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                             0xc
++#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                               0x10
++#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                               0x70000000L
++//CM2_CM_DGAM_RAMB_REGION_2_3
++#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                               0x0
++#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                             0xc
++#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                               0x10
++#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                               0x70000000L
++//CM2_CM_DGAM_RAMB_REGION_4_5
++#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                               0x0
++#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                             0xc
++#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                               0x10
++#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                               0x70000000L
++//CM2_CM_DGAM_RAMB_REGION_6_7
++#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                               0x0
++#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                             0xc
++#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                               0x10
++#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                               0x70000000L
++//CM2_CM_DGAM_RAMB_REGION_8_9
++#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                               0x0
++#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                             0xc
++#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                               0x10
++#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                               0x70000000L
++//CM2_CM_DGAM_RAMB_REGION_10_11
++#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                            0x0
++#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                          0xc
++#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                            0x10
++#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                              0x000001FFL
++#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                            0x70000000L
++//CM2_CM_DGAM_RAMB_REGION_12_13
++#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                            0x0
++#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                          0xc
++#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                            0x10
++#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                              0x000001FFL
++#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                            0x70000000L
++//CM2_CM_DGAM_RAMB_REGION_14_15
++#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                            0x0
++#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                          0xc
++#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                            0x10
++#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                              0x000001FFL
++#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                            0x70000000L
++//CM2_CM_BLNDGAM_CONTROL
++#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT                                                    0x0
++#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK                                                      0x00000003L
++//CM2_CM_BLNDGAM_LUT_INDEX
++#define CM2_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
++#define CM2_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
++//CM2_CM_BLNDGAM_LUT_DATA
++#define CM2_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
++#define CM2_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0007FFFFL
++//CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK
++#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT                                 0x0
++#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT                                     0x4
++#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT                                     0x8
++#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK                                   0x00000007L
++#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK                                       0x00000010L
++#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK                                       0x00000300L
++//CM2_CM_BLNDGAM_RAMA_START_CNTL_B
++#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
++#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
++#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
++#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
++//CM2_CM_BLNDGAM_RAMA_START_CNTL_G
++#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
++#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
++#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
++#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
++//CM2_CM_BLNDGAM_RAMA_START_CNTL_R
++#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
++#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
++#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
++#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
++//CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B
++#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT                    0x0
++#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                      0x0003FFFFL
++//CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G
++#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT                    0x0
++#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                      0x0003FFFFL
++//CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R
++#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT                    0x0
++#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                      0x0003FFFFL
++//CM2_CM_BLNDGAM_RAMA_END_CNTL1_B
++#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
++#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
++//CM2_CM_BLNDGAM_RAMA_END_CNTL2_B
++#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x0
++#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x10
++#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0x0000FFFFL
++#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0xFFFF0000L
++//CM2_CM_BLNDGAM_RAMA_END_CNTL1_G
++#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
++#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
++//CM2_CM_BLNDGAM_RAMA_END_CNTL2_G
++#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x0
++#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x10
++#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0x0000FFFFL
++#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0xFFFF0000L
++//CM2_CM_BLNDGAM_RAMA_END_CNTL1_R
++#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
++#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
++//CM2_CM_BLNDGAM_RAMA_END_CNTL2_R
++#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x0
++#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x10
++#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0x0000FFFFL
++#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0xFFFF0000L
++//CM2_CM_BLNDGAM_RAMA_REGION_0_1
++#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
++#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
++#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
++#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
++#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
++//CM2_CM_BLNDGAM_RAMA_REGION_2_3
++#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
++#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
++#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
++#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
++#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
++//CM2_CM_BLNDGAM_RAMA_REGION_4_5
++#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
++#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
++#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
++#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
++#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
++//CM2_CM_BLNDGAM_RAMA_REGION_6_7
++#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
++#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
++#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
++#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
++#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
++//CM2_CM_BLNDGAM_RAMA_REGION_8_9
++#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
++#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
++#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
++#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
++#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
++//CM2_CM_BLNDGAM_RAMA_REGION_10_11
++#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMA_REGION_12_13
++#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMA_REGION_14_15
++#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMA_REGION_16_17
++#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMA_REGION_18_19
++#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMA_REGION_20_21
++#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMA_REGION_22_23
++#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMA_REGION_24_25
++#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMA_REGION_26_27
++#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMA_REGION_28_29
++#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMA_REGION_30_31
++#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMA_REGION_32_33
++#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMB_START_CNTL_B
++#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
++#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
++#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
++#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
++//CM2_CM_BLNDGAM_RAMB_START_CNTL_G
++#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
++#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
++#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
++#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
++//CM2_CM_BLNDGAM_RAMB_START_CNTL_R
++#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
++#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
++#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
++#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
++//CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B
++#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT                    0x0
++#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                      0x0003FFFFL
++//CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G
++#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT                    0x0
++#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                      0x0003FFFFL
++//CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R
++#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT                    0x0
++#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                      0x0003FFFFL
++//CM2_CM_BLNDGAM_RAMB_END_CNTL1_B
++#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
++#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
++//CM2_CM_BLNDGAM_RAMB_END_CNTL2_B
++#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x0
++#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x10
++#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0x0000FFFFL
++#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0xFFFF0000L
++//CM2_CM_BLNDGAM_RAMB_END_CNTL1_G
++#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
++#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
++//CM2_CM_BLNDGAM_RAMB_END_CNTL2_G
++#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x0
++#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x10
++#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0x0000FFFFL
++#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0xFFFF0000L
++//CM2_CM_BLNDGAM_RAMB_END_CNTL1_R
++#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
++#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
++//CM2_CM_BLNDGAM_RAMB_END_CNTL2_R
++#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x0
++#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x10
++#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0x0000FFFFL
++#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0xFFFF0000L
++//CM2_CM_BLNDGAM_RAMB_REGION_0_1
++#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
++#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
++#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
++#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
++#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
++//CM2_CM_BLNDGAM_RAMB_REGION_2_3
++#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
++#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
++#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
++#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
++#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
++//CM2_CM_BLNDGAM_RAMB_REGION_4_5
++#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
++#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
++#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
++#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
++#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
++//CM2_CM_BLNDGAM_RAMB_REGION_6_7
++#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
++#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
++#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
++#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
++#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
++//CM2_CM_BLNDGAM_RAMB_REGION_8_9
++#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
++#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
++#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
++#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
++#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
++//CM2_CM_BLNDGAM_RAMB_REGION_10_11
++#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMB_REGION_12_13
++#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMB_REGION_14_15
++#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMB_REGION_16_17
++#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMB_REGION_18_19
++#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMB_REGION_20_21
++#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMB_REGION_22_23
++#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMB_REGION_24_25
++#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMB_REGION_26_27
++#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMB_REGION_28_29
++#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMB_REGION_30_31
++#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_BLNDGAM_RAMB_REGION_32_33
++#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
++#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
++#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
++#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
++#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
++//CM2_CM_HDR_MULT_COEF
++#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
++#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
++//CM2_CM_MEM_PWR_CTRL
++#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT                                                      0x0
++#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT                                                        0x2
++#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
++#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
++#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK                                                        0x00000003L
++#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK                                                          0x00000004L
++#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
++#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
++//CM2_CM_MEM_PWR_STATUS
++#define CM2_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT                                                    0x0
++#define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
++#define CM2_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK                                                      0x00000003L
++#define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
++//CM2_CM_DEALPHA
++#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
++#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
++//CM2_CM_COEF_FORMAT
++#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
++#define CM2_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT                                                        0x4
++#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
++#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
++#define CM2_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK                                                          0x00000010L
++#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
++//CM2_CM_SHAPER_CONTROL
++#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
++#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
++//CM2_CM_SHAPER_OFFSET_R
++#define CM2_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
++#define CM2_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
++//CM2_CM_SHAPER_OFFSET_G
++#define CM2_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
++#define CM2_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
++//CM2_CM_SHAPER_OFFSET_B
++#define CM2_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
++#define CM2_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
++//CM2_CM_SHAPER_SCALE_R
++#define CM2_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
++#define CM2_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
++//CM2_CM_SHAPER_SCALE_G_B
++#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
++#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
++#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
++#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
++//CM2_CM_SHAPER_LUT_INDEX
++#define CM2_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
++#define CM2_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
++//CM2_CM_SHAPER_LUT_DATA
++#define CM2_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
++#define CM2_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
++//CM2_CM_SHAPER_LUT_WRITE_EN_MASK
++#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
++#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
++#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT                                       0x8
++#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
++#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
++#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK                                         0x00000300L
++//CM2_CM_SHAPER_RAMA_START_CNTL_B
++#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
++#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
++#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
++#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
++//CM2_CM_SHAPER_RAMA_START_CNTL_G
++#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
++#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
++#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
++#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
++//CM2_CM_SHAPER_RAMA_START_CNTL_R
++#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
++#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
++#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
++#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
++//CM2_CM_SHAPER_RAMA_END_CNTL_B
++#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
++#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
++#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
++#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
++//CM2_CM_SHAPER_RAMA_END_CNTL_G
++#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
++#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
++#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
++#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
++//CM2_CM_SHAPER_RAMA_END_CNTL_R
++#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
++#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
++#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
++#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
++//CM2_CM_SHAPER_RAMA_REGION_0_1
++#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
++#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
++#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
++#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
++#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
++//CM2_CM_SHAPER_RAMA_REGION_2_3
++#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
++#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
++#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
++#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
++#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
++//CM2_CM_SHAPER_RAMA_REGION_4_5
++#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
++#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
++#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
++#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
++#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
++//CM2_CM_SHAPER_RAMA_REGION_6_7
++#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
++#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
++#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
++#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
++#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
++//CM2_CM_SHAPER_RAMA_REGION_8_9
++#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
++#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
++#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
++#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
++#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
++//CM2_CM_SHAPER_RAMA_REGION_10_11
++#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMA_REGION_12_13
++#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMA_REGION_14_15
++#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMA_REGION_16_17
++#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMA_REGION_18_19
++#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMA_REGION_20_21
++#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMA_REGION_22_23
++#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMA_REGION_24_25
++#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMA_REGION_26_27
++#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMA_REGION_28_29
++#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMA_REGION_30_31
++#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMA_REGION_32_33
++#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMB_START_CNTL_B
++#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
++#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
++#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
++#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
++//CM2_CM_SHAPER_RAMB_START_CNTL_G
++#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
++#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
++#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
++#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
++//CM2_CM_SHAPER_RAMB_START_CNTL_R
++#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
++#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
++#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
++#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
++//CM2_CM_SHAPER_RAMB_END_CNTL_B
++#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
++#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
++#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
++#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
++//CM2_CM_SHAPER_RAMB_END_CNTL_G
++#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
++#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
++#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
++#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
++//CM2_CM_SHAPER_RAMB_END_CNTL_R
++#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
++#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
++#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
++#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
++//CM2_CM_SHAPER_RAMB_REGION_0_1
++#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
++#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
++#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
++#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
++#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
++//CM2_CM_SHAPER_RAMB_REGION_2_3
++#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
++#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
++#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
++#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
++#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
++//CM2_CM_SHAPER_RAMB_REGION_4_5
++#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
++#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
++#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
++#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
++#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
++//CM2_CM_SHAPER_RAMB_REGION_6_7
++#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
++#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
++#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
++#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
++#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
++//CM2_CM_SHAPER_RAMB_REGION_8_9
++#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
++#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
++#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
++#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
++#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
++//CM2_CM_SHAPER_RAMB_REGION_10_11
++#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMB_REGION_12_13
++#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMB_REGION_14_15
++#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMB_REGION_16_17
++#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMB_REGION_18_19
++#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMB_REGION_20_21
++#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMB_REGION_22_23
++#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMB_REGION_24_25
++#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMB_REGION_26_27
++#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMB_REGION_28_29
++#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMB_REGION_30_31
++#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_SHAPER_RAMB_REGION_32_33
++#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
++#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
++#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
++#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
++#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
++//CM2_CM_MEM_PWR_CTRL2
++#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
++#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
++#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
++#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
++#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
++#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
++#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
++#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
++//CM2_CM_MEM_PWR_STATUS2
++#define CM2_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
++#define CM2_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
++#define CM2_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
++#define CM2_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
++//CM2_CM_3DLUT_MODE
++#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
++#define CM2_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
++#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
++#define CM2_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
++//CM2_CM_3DLUT_INDEX
++#define CM2_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
++#define CM2_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
++//CM2_CM_3DLUT_DATA
++#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
++#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
++#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
++#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
++//CM2_CM_3DLUT_DATA_30BIT
++#define CM2_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
++#define CM2_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
++//CM2_CM_3DLUT_READ_WRITE_CONTROL
++#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
++#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
++#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
++#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT                                        0xc
++#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
++#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
++#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
++#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
++#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK                                          0x00003000L
++#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
++//CM2_CM_3DLUT_OUT_NORM_FACTOR
++#define CM2_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
++#define CM2_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
++//CM2_CM_3DLUT_OUT_OFFSET_R
++#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
++#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
++#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
++#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
++//CM2_CM_3DLUT_OUT_OFFSET_G
++#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
++#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
++#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
++#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
++//CM2_CM_3DLUT_OUT_OFFSET_B
++#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
++#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
++#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
++#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
++//CM2_CM_TEST_DEBUG_INDEX
++#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
++#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
++#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
++#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
++//CM2_CM_TEST_DEBUG_DATA
++#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
++#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON13_PERFCOUNTER_CNTL
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
++#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
++//DC_PERFMON13_PERFCOUNTER_CNTL2
++#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
++#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
++#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
++#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
++#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
++#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
++#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
++#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
++#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
++#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
++//DC_PERFMON13_PERFCOUNTER_STATE
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
++#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
++//DC_PERFMON13_PERFMON_CNTL
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
++#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
++//DC_PERFMON13_PERFMON_CNTL2
++#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
++#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
++#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
++#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
++#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
++#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
++#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
++#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
++//DC_PERFMON13_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
++#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
++//DC_PERFMON13_PERFMON_CVALUE_LOW
++#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
++#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
++//DC_PERFMON13_PERFMON_HI
++#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
++#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
++#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
++#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
++//DC_PERFMON13_PERFMON_LOW
++#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
++#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
++//DPP_TOP3_DPP_CONTROL
++#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
++#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
++#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
++#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
++#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT                                         0xe
++#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0x10
++#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x12
++#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x14
++#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
++#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
++#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
++#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
++#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
++#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK                                           0x00004000L
++#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00010000L
++#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00040000L
++#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00100000L
++#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0xF0000000L
++//DPP_TOP3_DPP_SOFT_RESET
++#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
++#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
++#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
++#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
++#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
++#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
++#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
++#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
++//DPP_TOP3_DPP_CRC_VAL_R_G
++#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
++#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
++#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
++#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
++//DPP_TOP3_DPP_CRC_VAL_B_A
++#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
++#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
++#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
++#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
++//DPP_TOP3_DPP_CRC_CTRL
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT                                                 0x6
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x7
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x8
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0xa
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xc
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xf
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK                                                   0x00000040L
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000080L
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000300L
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000C00L
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00007000L
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x00008000L
++#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
++//DPP_TOP3_HOST_READ_CONTROL
++#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
++#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
++
++
++// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
++//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT
++#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
++#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
++//CNVC_CFG3_FORMAT_CONTROL
++#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
++#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
++#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
++#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
++#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
++#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
++#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
++#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
++#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
++#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
++#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
++#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
++#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
++#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
++#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
++#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
++//CNVC_CFG3_FCNV_FP_BIAS_R
++#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
++#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
++//CNVC_CFG3_FCNV_FP_BIAS_G
++#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
++#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
++//CNVC_CFG3_FCNV_FP_BIAS_B
++#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
++#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
++//CNVC_CFG3_FCNV_FP_SCALE_R
++#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
++#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
++//CNVC_CFG3_FCNV_FP_SCALE_G
++#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
++#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
++//CNVC_CFG3_FCNV_FP_SCALE_B
++#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
++#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
++//CNVC_CFG3_COLOR_KEYER_CONTROL
++#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
++#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
++#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
++#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
++//CNVC_CFG3_COLOR_KEYER_ALPHA
++#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
++#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
++#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
++#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
++//CNVC_CFG3_COLOR_KEYER_RED
++#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
++#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
++#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
++#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
++//CNVC_CFG3_COLOR_KEYER_GREEN
++#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
++#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
++#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
++#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
++//CNVC_CFG3_COLOR_KEYER_BLUE
++#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
++#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
++#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
++#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
++//CNVC_CFG3_ALPHA_2BIT_LUT
++#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
++#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
++#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
++#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
++#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
++#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
++#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
++#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
++
++
++// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
++//CNVC_CUR3_CURSOR0_CONTROL
++#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
++#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
++#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
++#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
++#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
++#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
++#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
++#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
++#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
++#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
++#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
++#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
++#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
++#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
++//CNVC_CUR3_CURSOR0_COLOR0
++#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
++#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
++//CNVC_CUR3_CURSOR0_COLOR1
++#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
++#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
++//CNVC_CUR3_CURSOR0_FP_SCALE_BIAS
++#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
++#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
++#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
++#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
++
++
++// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
++//DSCL3_SCL_COEF_RAM_TAP_SELECT
++#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
++#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
++#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
++#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
++#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
++#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
++//DSCL3_SCL_COEF_RAM_TAP_DATA
++#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
++#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
++#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
++#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
++#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
++#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
++#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
++#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
++//DSCL3_SCL_MODE
++#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
++#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
++#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
++#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
++#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
++#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
++#define DSCL3_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
++#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
++#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
++#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
++#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
++#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
++//DSCL3_SCL_TAP_CONTROL
++#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
++#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
++#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
++#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
++#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
++#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
++#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
++#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
++//DSCL3_DSCL_CONTROL
++#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
++#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
++//DSCL3_DSCL_2TAP_CONTROL
++#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
++#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
++#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
++#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
++#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
++#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
++#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
++#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
++#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
++#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
++#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
++#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
++//DSCL3_SCL_MANUAL_REPLICATE_CONTROL
++#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
++#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
++#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
++#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
++//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO
++#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
++#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x03FFFFFFL
++//DSCL3_SCL_HORZ_FILTER_INIT
++#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
++#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
++#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
++#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
++//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C
++#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
++#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x03FFFFFFL
++//DSCL3_SCL_HORZ_FILTER_INIT_C
++#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
++#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
++#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
++#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
++//DSCL3_SCL_VERT_FILTER_SCALE_RATIO
++#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
++#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x03FFFFFFL
++//DSCL3_SCL_VERT_FILTER_INIT
++#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
++#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
++#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
++#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
++//DSCL3_SCL_VERT_FILTER_INIT_BOT
++#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
++#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
++#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
++#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
++//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C
++#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
++#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x03FFFFFFL
++//DSCL3_SCL_VERT_FILTER_INIT_C
++#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
++#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
++#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
++#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
++//DSCL3_SCL_VERT_FILTER_INIT_BOT_C
++#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
++#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
++#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
++#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
++//DSCL3_SCL_BLACK_OFFSET
++#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT                                                 0x0
++#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT                                                  0x10
++#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK                                                   0x0000FFFFL
++#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK                                                    0xFFFF0000L
++//DSCL3_DSCL_UPDATE
++#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
++#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
++//DSCL3_DSCL_AUTOCAL
++#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
++#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
++#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
++#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
++#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
++#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
++//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT
++#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
++#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
++#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
++#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
++//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM
++#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
++#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
++#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
++#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
++//DSCL3_OTG_H_BLANK
++#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
++#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
++#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
++#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
++//DSCL3_OTG_V_BLANK
++#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
++#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
++#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
++#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
++//DSCL3_RECOUT_START
++#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
++#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
++#define DSCL3_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
++#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
++//DSCL3_RECOUT_SIZE
++#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
++#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
++#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
++#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
++//DSCL3_MPC_SIZE
++#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
++#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
++#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
++#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
++//DSCL3_LB_DATA_FORMAT
++#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
++#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
++#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
++#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
++//DSCL3_LB_MEMORY_CTRL
++#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
++#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
++#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
++#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
++#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
++#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
++#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
++#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
++//DSCL3_LB_V_COUNTER
++#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
++#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
++#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
++#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
++//DSCL3_DSCL_MEM_PWR_CTRL
++#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
++#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
++#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
++#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
++#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
++//DSCL3_DSCL_MEM_PWR_STATUS
++#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
++#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
++#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
++#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
++#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
++#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
++#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
++#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
++#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
++#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
++#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
++#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
++#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
++#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
++//DSCL3_OBUF_CONTROL
++#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
++#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x4
++#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0xc
++#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x1c
++#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
++#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000010L
++#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00001000L
++#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0xF0000000L
++//DSCL3_OBUF_MEM_PWR_CTRL
++#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
++#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
++#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
++#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
++#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
++#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
++#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
++#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
++
++
++// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
++//CM3_CM_CONTROL
++#define CM3_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
++#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
++#define CM3_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
++#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
++//CM3_CM_ICSC_CONTROL
++#define CM3_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT                                                              0x0
++#define CM3_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK                                                                0x00000003L
++//CM3_CM_ICSC_C11_C12
++#define CM3_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT                                                               0x0
++#define CM3_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT                                                               0x10
++#define CM3_CM_ICSC_C11_C12__CM_ICSC_C11_MASK                                                                 0x0000FFFFL
++#define CM3_CM_ICSC_C11_C12__CM_ICSC_C12_MASK                                                                 0xFFFF0000L
++//CM3_CM_ICSC_C13_C14
++#define CM3_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT                                                               0x0
++#define CM3_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT                                                               0x10
++#define CM3_CM_ICSC_C13_C14__CM_ICSC_C13_MASK                                                                 0x0000FFFFL
++#define CM3_CM_ICSC_C13_C14__CM_ICSC_C14_MASK                                                                 0xFFFF0000L
++//CM3_CM_ICSC_C21_C22
++#define CM3_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT                                                               0x0
++#define CM3_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT                                                               0x10
++#define CM3_CM_ICSC_C21_C22__CM_ICSC_C21_MASK                                                                 0x0000FFFFL
++#define CM3_CM_ICSC_C21_C22__CM_ICSC_C22_MASK                                                                 0xFFFF0000L
++//CM3_CM_ICSC_C23_C24
++#define CM3_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT                                                               0x0
++#define CM3_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT                                                               0x10
++#define CM3_CM_ICSC_C23_C24__CM_ICSC_C23_MASK                                                                 0x0000FFFFL
++#define CM3_CM_ICSC_C23_C24__CM_ICSC_C24_MASK                                                                 0xFFFF0000L
++//CM3_CM_ICSC_C31_C32
++#define CM3_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT                                                               0x0
++#define CM3_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT                                                               0x10
++#define CM3_CM_ICSC_C31_C32__CM_ICSC_C31_MASK                                                                 0x0000FFFFL
++#define CM3_CM_ICSC_C31_C32__CM_ICSC_C32_MASK                                                                 0xFFFF0000L
++//CM3_CM_ICSC_C33_C34
++#define CM3_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT                                                               0x0
++#define CM3_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT                                                               0x10
++#define CM3_CM_ICSC_C33_C34__CM_ICSC_C33_MASK                                                                 0x0000FFFFL
++#define CM3_CM_ICSC_C33_C34__CM_ICSC_C34_MASK                                                                 0xFFFF0000L
++//CM3_CM_ICSC_B_C11_C12
++#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT                                                           0x0
++#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT                                                           0x10
++#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK                                                             0x0000FFFFL
++#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK                                                             0xFFFF0000L
++//CM3_CM_ICSC_B_C13_C14
++#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT                                                           0x0
++#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT                                                           0x10
++#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK                                                             0x0000FFFFL
++#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK                                                             0xFFFF0000L
++//CM3_CM_ICSC_B_C21_C22
++#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT                                                           0x0
++#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT                                                           0x10
++#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK                                                             0x0000FFFFL
++#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK                                                             0xFFFF0000L
++//CM3_CM_ICSC_B_C23_C24
++#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT                                                           0x0
++#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT                                                           0x10
++#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK                                                             0x0000FFFFL
++#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK                                                             0xFFFF0000L
++//CM3_CM_ICSC_B_C31_C32
++#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT                                                           0x0
++#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT                                                           0x10
++#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK                                                             0x0000FFFFL
++#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK                                                             0xFFFF0000L
++//CM3_CM_ICSC_B_C33_C34
++#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT                                                           0x0
++#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT                                                           0x10
++#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK                                                             0x0000FFFFL
++#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK                                                             0xFFFF0000L
++//CM3_CM_GAMUT_REMAP_CONTROL
++#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
++#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
++//CM3_CM_GAMUT_REMAP_C11_C12
++#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
++#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
++#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
++#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
++//CM3_CM_GAMUT_REMAP_C13_C14
++#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
++#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
++#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
++#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
++//CM3_CM_GAMUT_REMAP_C21_C22
++#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
++#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
++#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
++#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
++//CM3_CM_GAMUT_REMAP_C23_C24
++#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
++#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
++#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
++#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
++//CM3_CM_GAMUT_REMAP_C31_C32
++#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
++#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
++#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
++#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
++//CM3_CM_GAMUT_REMAP_C33_C34
++#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
++#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
++#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
++#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
++//CM3_CM_GAMUT_REMAP_B_C11_C12
++#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
++#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
++#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
++#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
++//CM3_CM_GAMUT_REMAP_B_C13_C14
++#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
++#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
++#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
++#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
++//CM3_CM_GAMUT_REMAP_B_C21_C22
++#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
++#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
++#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
++#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
++//CM3_CM_GAMUT_REMAP_B_C23_C24
++#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
++#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
++#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
++#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
++//CM3_CM_GAMUT_REMAP_B_C31_C32
++#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
++#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
++#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
++#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
++//CM3_CM_GAMUT_REMAP_B_C33_C34
++#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
++#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
++#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
++#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
++//CM3_CM_BIAS_CR_R
++#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
++#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
++//CM3_CM_BIAS_Y_G_CB_B
++#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
++#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
++#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
++#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
++//CM3_CM_DGAM_CONTROL
++#define CM3_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT                                                          0x0
++#define CM3_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK                                                            0x00000007L
++//CM3_CM_DGAM_LUT_INDEX
++#define CM3_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT                                                       0x0
++#define CM3_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK                                                         0x000001FFL
++//CM3_CM_DGAM_LUT_DATA
++#define CM3_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT                                                         0x0
++#define CM3_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK                                                           0x0007FFFFL
++//CM3_CM_DGAM_LUT_WRITE_EN_MASK
++#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT                                       0x0
++#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT                                           0x4
++#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT                                           0x8
++#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT                                     0xc
++#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK                                         0x00000007L
++#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK                                             0x00000010L
++#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK                                             0x00000700L
++#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK                                       0x00001000L
++//CM3_CM_DGAM_RAMA_START_CNTL_B
++#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT                                 0x0
++#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                         0x14
++#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK                                   0x0003FFFFL
++#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                           0x07F00000L
++//CM3_CM_DGAM_RAMA_START_CNTL_G
++#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT                                 0x0
++#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                         0x14
++#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK                                   0x0003FFFFL
++#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                           0x07F00000L
++//CM3_CM_DGAM_RAMA_START_CNTL_R
++#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT                                 0x0
++#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                         0x14
++#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK                                   0x0003FFFFL
++#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                           0x07F00000L
++//CM3_CM_DGAM_RAMA_SLOPE_CNTL_B
++#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT                          0x0
++#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                            0x0003FFFFL
++//CM3_CM_DGAM_RAMA_SLOPE_CNTL_G
++#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT                          0x0
++#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                            0x0003FFFFL
++//CM3_CM_DGAM_RAMA_SLOPE_CNTL_R
++#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT                          0x0
++#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                            0x0003FFFFL
++//CM3_CM_DGAM_RAMA_END_CNTL1_B
++#define CM3_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT                                    0x0
++#define CM3_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK                                      0x0000FFFFL
++//CM3_CM_DGAM_RAMA_END_CNTL2_B
++#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                              0x0
++#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                               0x10
++#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                                0x0000FFFFL
++#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK                                 0xFFFF0000L
++//CM3_CM_DGAM_RAMA_END_CNTL1_G
++#define CM3_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT                                    0x0
++#define CM3_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK                                      0x0000FFFFL
++//CM3_CM_DGAM_RAMA_END_CNTL2_G
++#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                              0x0
++#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                               0x10
++#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                                0x0000FFFFL
++#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK                                 0xFFFF0000L
++//CM3_CM_DGAM_RAMA_END_CNTL1_R
++#define CM3_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT                                    0x0
++#define CM3_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK                                      0x0000FFFFL
++//CM3_CM_DGAM_RAMA_END_CNTL2_R
++#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                              0x0
++#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                               0x10
++#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                                0x0000FFFFL
++#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK                                 0xFFFF0000L
++//CM3_CM_DGAM_RAMA_REGION_0_1
++#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                               0x0
++#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                             0xc
++#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                               0x10
++#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                               0x70000000L
++//CM3_CM_DGAM_RAMA_REGION_2_3
++#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                               0x0
++#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                             0xc
++#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                               0x10
++#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                               0x70000000L
++//CM3_CM_DGAM_RAMA_REGION_4_5
++#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                               0x0
++#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                             0xc
++#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                               0x10
++#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                               0x70000000L
++//CM3_CM_DGAM_RAMA_REGION_6_7
++#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                               0x0
++#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                             0xc
++#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                               0x10
++#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                               0x70000000L
++//CM3_CM_DGAM_RAMA_REGION_8_9
++#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                               0x0
++#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                             0xc
++#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                               0x10
++#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                               0x70000000L
++//CM3_CM_DGAM_RAMA_REGION_10_11
++#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                            0x0
++#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                          0xc
++#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                            0x10
++#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                              0x000001FFL
++#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                            0x70000000L
++//CM3_CM_DGAM_RAMA_REGION_12_13
++#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                            0x0
++#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                          0xc
++#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                            0x10
++#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                              0x000001FFL
++#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                            0x70000000L
++//CM3_CM_DGAM_RAMA_REGION_14_15
++#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                            0x0
++#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                          0xc
++#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                            0x10
++#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                              0x000001FFL
++#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                            0x70000000L
++//CM3_CM_DGAM_RAMB_START_CNTL_B
++#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT                                 0x0
++#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                         0x14
++#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK                                   0x0003FFFFL
++#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                           0x07F00000L
++//CM3_CM_DGAM_RAMB_START_CNTL_G
++#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT                                 0x0
++#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                         0x14
++#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK                                   0x0003FFFFL
++#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                           0x07F00000L
++//CM3_CM_DGAM_RAMB_START_CNTL_R
++#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT                                 0x0
++#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                         0x14
++#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK                                   0x0003FFFFL
++#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                           0x07F00000L
++//CM3_CM_DGAM_RAMB_SLOPE_CNTL_B
++#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT                          0x0
++#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                            0x0003FFFFL
++//CM3_CM_DGAM_RAMB_SLOPE_CNTL_G
++#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT                          0x0
++#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                            0x0003FFFFL
++//CM3_CM_DGAM_RAMB_SLOPE_CNTL_R
++#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT                          0x0
++#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                            0x0003FFFFL
++//CM3_CM_DGAM_RAMB_END_CNTL1_B
++#define CM3_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT                                    0x0
++#define CM3_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK                                      0x0000FFFFL
++//CM3_CM_DGAM_RAMB_END_CNTL2_B
++#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                              0x0
++#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                               0x10
++#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                                0x0000FFFFL
++#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK                                 0xFFFF0000L
++//CM3_CM_DGAM_RAMB_END_CNTL1_G
++#define CM3_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT                                    0x0
++#define CM3_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK                                      0x0000FFFFL
++//CM3_CM_DGAM_RAMB_END_CNTL2_G
++#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                              0x0
++#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                               0x10
++#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                                0x0000FFFFL
++#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK                                 0xFFFF0000L
++//CM3_CM_DGAM_RAMB_END_CNTL1_R
++#define CM3_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT                                    0x0
++#define CM3_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK                                      0x0000FFFFL
++//CM3_CM_DGAM_RAMB_END_CNTL2_R
++#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                              0x0
++#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                               0x10
++#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                                0x0000FFFFL
++#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK                                 0xFFFF0000L
++//CM3_CM_DGAM_RAMB_REGION_0_1
++#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                               0x0
++#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                             0xc
++#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                               0x10
++#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                               0x70000000L
++//CM3_CM_DGAM_RAMB_REGION_2_3
++#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                               0x0
++#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                             0xc
++#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                               0x10
++#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                               0x70000000L
++//CM3_CM_DGAM_RAMB_REGION_4_5
++#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                               0x0
++#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                             0xc
++#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                               0x10
++#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                               0x70000000L
++//CM3_CM_DGAM_RAMB_REGION_6_7
++#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                               0x0
++#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                             0xc
++#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                               0x10
++#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                               0x70000000L
++//CM3_CM_DGAM_RAMB_REGION_8_9
++#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                               0x0
++#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                             0xc
++#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                               0x10
++#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                             0x1c
++#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                                 0x000001FFL
++#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                               0x00007000L
++#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                                 0x01FF0000L
++#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                               0x70000000L
++//CM3_CM_DGAM_RAMB_REGION_10_11
++#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                            0x0
++#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                          0xc
++#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                            0x10
++#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                              0x000001FFL
++#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                            0x70000000L
++//CM3_CM_DGAM_RAMB_REGION_12_13
++#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                            0x0
++#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                          0xc
++#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                            0x10
++#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                              0x000001FFL
++#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                            0x70000000L
++//CM3_CM_DGAM_RAMB_REGION_14_15
++#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                            0x0
++#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                          0xc
++#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                            0x10
++#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                          0x1c
++#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                              0x000001FFL
++#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                            0x00007000L
++#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                              0x01FF0000L
++#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                            0x70000000L
++//CM3_CM_BLNDGAM_CONTROL
++#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT                                                    0x0
++#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK                                                      0x00000003L
++//CM3_CM_BLNDGAM_LUT_INDEX
++#define CM3_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
++#define CM3_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
++//CM3_CM_BLNDGAM_LUT_DATA
++#define CM3_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
++#define CM3_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0007FFFFL
++//CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK
++#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT                                 0x0
++#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT                                     0x4
++#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT                                     0x8
++#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK                                   0x00000007L
++#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK                                       0x00000010L
++#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK                                       0x00000300L
++//CM3_CM_BLNDGAM_RAMA_START_CNTL_B
++#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
++#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
++#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
++#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
++//CM3_CM_BLNDGAM_RAMA_START_CNTL_G
++#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
++#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
++#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
++#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
++//CM3_CM_BLNDGAM_RAMA_START_CNTL_R
++#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
++#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
++#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
++#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
++//CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B
++#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT                    0x0
++#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                      0x0003FFFFL
++//CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G
++#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT                    0x0
++#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                      0x0003FFFFL
++//CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R
++#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT                    0x0
++#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                      0x0003FFFFL
++//CM3_CM_BLNDGAM_RAMA_END_CNTL1_B
++#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
++#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
++//CM3_CM_BLNDGAM_RAMA_END_CNTL2_B
++#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x0
++#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x10
++#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0x0000FFFFL
++#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0xFFFF0000L
++//CM3_CM_BLNDGAM_RAMA_END_CNTL1_G
++#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
++#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
++//CM3_CM_BLNDGAM_RAMA_END_CNTL2_G
++#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x0
++#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x10
++#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0x0000FFFFL
++#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0xFFFF0000L
++//CM3_CM_BLNDGAM_RAMA_END_CNTL1_R
++#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
++#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
++//CM3_CM_BLNDGAM_RAMA_END_CNTL2_R
++#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x0
++#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x10
++#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0x0000FFFFL
++#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0xFFFF0000L
++//CM3_CM_BLNDGAM_RAMA_REGION_0_1
++#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
++#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
++#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
++#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
++#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
++//CM3_CM_BLNDGAM_RAMA_REGION_2_3
++#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
++#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
++#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
++#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
++#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
++//CM3_CM_BLNDGAM_RAMA_REGION_4_5
++#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
++#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
++#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
++#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
++#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
++//CM3_CM_BLNDGAM_RAMA_REGION_6_7
++#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
++#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
++#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
++#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
++#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
++//CM3_CM_BLNDGAM_RAMA_REGION_8_9
++#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
++#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
++#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
++#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
++#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
++//CM3_CM_BLNDGAM_RAMA_REGION_10_11
++#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMA_REGION_12_13
++#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMA_REGION_14_15
++#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMA_REGION_16_17
++#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMA_REGION_18_19
++#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMA_REGION_20_21
++#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMA_REGION_22_23
++#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMA_REGION_24_25
++#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMA_REGION_26_27
++#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMA_REGION_28_29
++#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMA_REGION_30_31
++#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMA_REGION_32_33
++#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMB_START_CNTL_B
++#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
++#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
++#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
++#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
++//CM3_CM_BLNDGAM_RAMB_START_CNTL_G
++#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
++#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
++#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
++#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
++//CM3_CM_BLNDGAM_RAMB_START_CNTL_R
++#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
++#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
++#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
++#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
++//CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B
++#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT                    0x0
++#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                      0x0003FFFFL
++//CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G
++#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT                    0x0
++#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                      0x0003FFFFL
++//CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R
++#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT                    0x0
++#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                      0x0003FFFFL
++//CM3_CM_BLNDGAM_RAMB_END_CNTL1_B
++#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
++#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
++//CM3_CM_BLNDGAM_RAMB_END_CNTL2_B
++#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x0
++#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x10
++#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0x0000FFFFL
++#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0xFFFF0000L
++//CM3_CM_BLNDGAM_RAMB_END_CNTL1_G
++#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
++#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
++//CM3_CM_BLNDGAM_RAMB_END_CNTL2_G
++#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x0
++#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x10
++#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0x0000FFFFL
++#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0xFFFF0000L
++//CM3_CM_BLNDGAM_RAMB_END_CNTL1_R
++#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
++#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
++//CM3_CM_BLNDGAM_RAMB_END_CNTL2_R
++#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x0
++#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x10
++#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0x0000FFFFL
++#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0xFFFF0000L
++//CM3_CM_BLNDGAM_RAMB_REGION_0_1
++#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
++#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
++#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
++#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
++#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
++//CM3_CM_BLNDGAM_RAMB_REGION_2_3
++#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
++#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
++#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
++#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
++#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
++//CM3_CM_BLNDGAM_RAMB_REGION_4_5
++#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
++#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
++#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
++#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
++#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
++//CM3_CM_BLNDGAM_RAMB_REGION_6_7
++#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
++#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
++#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
++#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
++#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
++//CM3_CM_BLNDGAM_RAMB_REGION_8_9
++#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
++#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
++#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
++#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
++#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
++#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
++//CM3_CM_BLNDGAM_RAMB_REGION_10_11
++#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMB_REGION_12_13
++#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMB_REGION_14_15
++#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMB_REGION_16_17
++#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMB_REGION_18_19
++#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMB_REGION_20_21
++#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMB_REGION_22_23
++#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMB_REGION_24_25
++#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMB_REGION_26_27
++#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMB_REGION_28_29
++#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMB_REGION_30_31
++#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_BLNDGAM_RAMB_REGION_32_33
++#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
++#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
++#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
++#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
++#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
++#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
++#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
++//CM3_CM_HDR_MULT_COEF
++#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
++#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
++//CM3_CM_MEM_PWR_CTRL
++#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT                                                      0x0
++#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT                                                        0x2
++#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
++#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
++#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK                                                        0x00000003L
++#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK                                                          0x00000004L
++#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
++#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
++//CM3_CM_MEM_PWR_STATUS
++#define CM3_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT                                                    0x0
++#define CM3_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
++#define CM3_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK                                                      0x00000003L
++#define CM3_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
++//CM3_CM_DEALPHA
++#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
++#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
++//CM3_CM_COEF_FORMAT
++#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
++#define CM3_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT                                                        0x4
++#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
++#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
++#define CM3_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK                                                          0x00000010L
++#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
++//CM3_CM_SHAPER_CONTROL
++#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
++#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
++//CM3_CM_SHAPER_OFFSET_R
++#define CM3_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
++#define CM3_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
++//CM3_CM_SHAPER_OFFSET_G
++#define CM3_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
++#define CM3_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
++//CM3_CM_SHAPER_OFFSET_B
++#define CM3_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
++#define CM3_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
++//CM3_CM_SHAPER_SCALE_R
++#define CM3_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
++#define CM3_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
++//CM3_CM_SHAPER_SCALE_G_B
++#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
++#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
++#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
++#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
++//CM3_CM_SHAPER_LUT_INDEX
++#define CM3_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
++#define CM3_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
++//CM3_CM_SHAPER_LUT_DATA
++#define CM3_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
++#define CM3_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
++//CM3_CM_SHAPER_LUT_WRITE_EN_MASK
++#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
++#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
++#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT                                       0x8
++#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
++#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
++#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK                                         0x00000300L
++//CM3_CM_SHAPER_RAMA_START_CNTL_B
++#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
++#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
++#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
++#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
++//CM3_CM_SHAPER_RAMA_START_CNTL_G
++#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
++#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
++#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
++#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
++//CM3_CM_SHAPER_RAMA_START_CNTL_R
++#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
++#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
++#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
++#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
++//CM3_CM_SHAPER_RAMA_END_CNTL_B
++#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
++#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
++#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
++#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
++//CM3_CM_SHAPER_RAMA_END_CNTL_G
++#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
++#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
++#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
++#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
++//CM3_CM_SHAPER_RAMA_END_CNTL_R
++#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
++#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
++#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
++#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
++//CM3_CM_SHAPER_RAMA_REGION_0_1
++#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
++#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
++#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
++#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
++#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
++//CM3_CM_SHAPER_RAMA_REGION_2_3
++#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
++#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
++#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
++#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
++#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
++//CM3_CM_SHAPER_RAMA_REGION_4_5
++#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
++#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
++#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
++#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
++#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
++//CM3_CM_SHAPER_RAMA_REGION_6_7
++#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
++#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
++#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
++#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
++#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
++//CM3_CM_SHAPER_RAMA_REGION_8_9
++#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
++#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
++#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
++#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
++#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
++//CM3_CM_SHAPER_RAMA_REGION_10_11
++#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMA_REGION_12_13
++#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMA_REGION_14_15
++#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMA_REGION_16_17
++#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMA_REGION_18_19
++#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMA_REGION_20_21
++#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMA_REGION_22_23
++#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMA_REGION_24_25
++#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMA_REGION_26_27
++#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMA_REGION_28_29
++#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMA_REGION_30_31
++#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMA_REGION_32_33
++#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMB_START_CNTL_B
++#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
++#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
++#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
++#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
++//CM3_CM_SHAPER_RAMB_START_CNTL_G
++#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
++#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
++#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
++#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
++//CM3_CM_SHAPER_RAMB_START_CNTL_R
++#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
++#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
++#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
++#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
++//CM3_CM_SHAPER_RAMB_END_CNTL_B
++#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
++#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
++#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
++#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
++//CM3_CM_SHAPER_RAMB_END_CNTL_G
++#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
++#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
++#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
++#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
++//CM3_CM_SHAPER_RAMB_END_CNTL_R
++#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
++#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
++#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
++#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
++//CM3_CM_SHAPER_RAMB_REGION_0_1
++#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
++#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
++#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
++#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
++#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
++//CM3_CM_SHAPER_RAMB_REGION_2_3
++#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
++#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
++#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
++#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
++#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
++//CM3_CM_SHAPER_RAMB_REGION_4_5
++#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
++#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
++#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
++#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
++#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
++//CM3_CM_SHAPER_RAMB_REGION_6_7
++#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
++#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
++#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
++#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
++#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
++//CM3_CM_SHAPER_RAMB_REGION_8_9
++#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
++#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
++#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
++#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
++#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
++#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
++#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
++#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
++//CM3_CM_SHAPER_RAMB_REGION_10_11
++#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMB_REGION_12_13
++#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMB_REGION_14_15
++#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMB_REGION_16_17
++#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMB_REGION_18_19
++#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMB_REGION_20_21
++#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMB_REGION_22_23
++#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMB_REGION_24_25
++#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMB_REGION_26_27
++#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMB_REGION_28_29
++#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMB_REGION_30_31
++#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_SHAPER_RAMB_REGION_32_33
++#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
++#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
++#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
++#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
++#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
++#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
++#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
++#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
++//CM3_CM_MEM_PWR_CTRL2
++#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
++#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
++#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
++#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
++#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
++#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
++#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
++#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
++//CM3_CM_MEM_PWR_STATUS2
++#define CM3_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
++#define CM3_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
++#define CM3_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
++#define CM3_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
++//CM3_CM_3DLUT_MODE
++#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
++#define CM3_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
++#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
++#define CM3_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
++//CM3_CM_3DLUT_INDEX
++#define CM3_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
++#define CM3_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
++//CM3_CM_3DLUT_DATA
++#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
++#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
++#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
++#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
++//CM3_CM_3DLUT_DATA_30BIT
++#define CM3_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
++#define CM3_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
++//CM3_CM_3DLUT_READ_WRITE_CONTROL
++#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
++#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
++#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
++#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT                                        0xc
++#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
++#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
++#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
++#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
++#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK                                          0x00003000L
++#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
++//CM3_CM_3DLUT_OUT_NORM_FACTOR
++#define CM3_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
++#define CM3_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
++//CM3_CM_3DLUT_OUT_OFFSET_R
++#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
++#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
++#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
++#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
++//CM3_CM_3DLUT_OUT_OFFSET_G
++#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
++#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
++#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
++#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
++//CM3_CM_3DLUT_OUT_OFFSET_B
++#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
++#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
++#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
++#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
++//CM3_CM_TEST_DEBUG_INDEX
++#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
++#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
++#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
++#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
++//CM3_CM_TEST_DEBUG_DATA
++#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
++#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON14_PERFCOUNTER_CNTL
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
++#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
++//DC_PERFMON14_PERFCOUNTER_CNTL2
++#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
++#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
++#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
++#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
++#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
++#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
++#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
++#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
++#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
++#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
++//DC_PERFMON14_PERFCOUNTER_STATE
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
++#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
++//DC_PERFMON14_PERFMON_CNTL
++#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
++#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
++#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
++#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
++#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
++#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
++#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
++#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
++#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
++#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
++#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
++#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
++//DC_PERFMON14_PERFMON_CNTL2
++#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
++#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
++#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
++#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
++#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
++#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
++#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
++#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
++//DC_PERFMON14_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
++#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
++//DC_PERFMON14_PERFMON_CVALUE_LOW
++#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
++#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
++//DC_PERFMON14_PERFMON_HI
++#define DC_PERFMON14_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
++#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
++#define DC_PERFMON14_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
++#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
++//DC_PERFMON14_PERFMON_LOW
++#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
++#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_mpc_mpcc0_dispdec
++//MPCC0_MPCC_TOP_SEL
++#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
++#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
++//MPCC0_MPCC_BOT_SEL
++#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
++#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
++//MPCC0_MPCC_OPP_ID
++#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
++#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
++//MPCC0_MPCC_CONTROL
++#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
++#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
++#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
++#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
++#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
++#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
++#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
++#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
++#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
++#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
++#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
++#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
++#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
++#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
++#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
++#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
++//MPCC0_MPCC_SM_CONTROL
++#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
++#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
++#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
++#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
++#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
++#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
++#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
++#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
++#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
++#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
++#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
++#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
++#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
++#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
++//MPCC0_MPCC_UPDATE_LOCK_SEL
++#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
++#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
++#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
++#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
++//MPCC0_MPCC_TOP_GAIN
++#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
++#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
++//MPCC0_MPCC_BOT_GAIN_INSIDE
++#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
++#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
++//MPCC0_MPCC_BOT_GAIN_OUTSIDE
++#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
++#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
++//MPCC0_MPCC_BG_R_CR
++#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
++#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
++//MPCC0_MPCC_BG_G_Y
++#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
++#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
++//MPCC0_MPCC_BG_B_CB
++#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
++#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
++//MPCC0_MPCC_MEM_PWR_CTRL
++#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
++#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
++#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x4
++#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
++#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
++#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000030L
++//MPCC0_MPCC_STALL_STATUS
++#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT                                                0x0
++#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT                                                   0x4
++#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT                                                    0x8
++#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT                                                   0xc
++#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK                                                  0x00000001L
++#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK                                                     0x00000010L
++#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK                                                      0x00000100L
++#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK                                                     0x00001000L
++//MPCC0_MPCC_STATUS
++#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
++#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
++#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
++#define MPCC0_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT                                                     0x1d
++#define MPCC0_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT                                                 0x1e
++#define MPCC0_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT                                                      0x1f
++#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
++#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
++#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
++#define MPCC0_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK                                                       0x20000000L
++#define MPCC0_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK                                                   0x40000000L
++#define MPCC0_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK                                                        0x80000000L
++
++
++// addressBlock: dce_dc_mpc_mpcc1_dispdec
++//MPCC1_MPCC_TOP_SEL
++#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
++#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
++//MPCC1_MPCC_BOT_SEL
++#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
++#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
++//MPCC1_MPCC_OPP_ID
++#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
++#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
++//MPCC1_MPCC_CONTROL
++#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
++#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
++#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
++#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
++#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
++#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
++#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
++#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
++#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
++#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
++#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
++#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
++#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
++#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
++#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
++#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
++//MPCC1_MPCC_SM_CONTROL
++#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
++#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
++#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
++#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
++#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
++#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
++#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
++#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
++#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
++#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
++#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
++#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
++#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
++#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
++//MPCC1_MPCC_UPDATE_LOCK_SEL
++#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
++#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
++#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
++#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
++//MPCC1_MPCC_TOP_GAIN
++#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
++#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
++//MPCC1_MPCC_BOT_GAIN_INSIDE
++#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
++#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
++//MPCC1_MPCC_BOT_GAIN_OUTSIDE
++#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
++#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
++//MPCC1_MPCC_BG_R_CR
++#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
++#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
++//MPCC1_MPCC_BG_G_Y
++#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
++#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
++//MPCC1_MPCC_BG_B_CB
++#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
++#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
++//MPCC1_MPCC_MEM_PWR_CTRL
++#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
++#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
++#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x4
++#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
++#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
++#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000030L
++//MPCC1_MPCC_STALL_STATUS
++#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT                                                0x0
++#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT                                                   0x4
++#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT                                                    0x8
++#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT                                                   0xc
++#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK                                                  0x00000001L
++#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK                                                     0x00000010L
++#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK                                                      0x00000100L
++#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK                                                     0x00001000L
++//MPCC1_MPCC_STATUS
++#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
++#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
++#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
++#define MPCC1_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT                                                     0x1d
++#define MPCC1_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT                                                 0x1e
++#define MPCC1_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT                                                      0x1f
++#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
++#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
++#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
++#define MPCC1_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK                                                       0x20000000L
++#define MPCC1_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK                                                   0x40000000L
++#define MPCC1_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK                                                        0x80000000L
++
++
++// addressBlock: dce_dc_mpc_mpcc2_dispdec
++//MPCC2_MPCC_TOP_SEL
++#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
++#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
++//MPCC2_MPCC_BOT_SEL
++#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
++#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
++//MPCC2_MPCC_OPP_ID
++#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
++#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
++//MPCC2_MPCC_CONTROL
++#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
++#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
++#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
++#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
++#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
++#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
++#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
++#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
++#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
++#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
++#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
++#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
++#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
++#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
++#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
++#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
++//MPCC2_MPCC_SM_CONTROL
++#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
++#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
++#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
++#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
++#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
++#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
++#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
++#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
++#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
++#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
++#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
++#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
++#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
++#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
++//MPCC2_MPCC_UPDATE_LOCK_SEL
++#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
++#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
++#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
++#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
++//MPCC2_MPCC_TOP_GAIN
++#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
++#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
++//MPCC2_MPCC_BOT_GAIN_INSIDE
++#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
++#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
++//MPCC2_MPCC_BOT_GAIN_OUTSIDE
++#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
++#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
++//MPCC2_MPCC_BG_R_CR
++#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
++#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
++//MPCC2_MPCC_BG_G_Y
++#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
++#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
++//MPCC2_MPCC_BG_B_CB
++#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
++#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
++//MPCC2_MPCC_MEM_PWR_CTRL
++#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
++#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
++#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x4
++#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
++#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
++#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000030L
++//MPCC2_MPCC_STALL_STATUS
++#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT                                                0x0
++#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT                                                   0x4
++#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT                                                    0x8
++#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT                                                   0xc
++#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK                                                  0x00000001L
++#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK                                                     0x00000010L
++#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK                                                      0x00000100L
++#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK                                                     0x00001000L
++//MPCC2_MPCC_STATUS
++#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
++#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
++#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
++#define MPCC2_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT                                                     0x1d
++#define MPCC2_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT                                                 0x1e
++#define MPCC2_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT                                                      0x1f
++#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
++#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
++#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
++#define MPCC2_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK                                                       0x20000000L
++#define MPCC2_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK                                                   0x40000000L
++#define MPCC2_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK                                                        0x80000000L
++
++
++// addressBlock: dce_dc_mpc_mpcc3_dispdec
++//MPCC3_MPCC_TOP_SEL
++#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
++#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
++//MPCC3_MPCC_BOT_SEL
++#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
++#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
++//MPCC3_MPCC_OPP_ID
++#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
++#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
++//MPCC3_MPCC_CONTROL
++#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
++#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
++#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
++#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
++#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
++#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
++#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
++#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
++#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
++#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
++#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
++#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
++#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
++#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
++#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
++#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
++//MPCC3_MPCC_SM_CONTROL
++#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
++#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
++#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
++#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
++#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
++#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
++#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
++#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
++#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
++#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
++#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
++#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
++#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
++#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
++//MPCC3_MPCC_UPDATE_LOCK_SEL
++#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
++#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
++#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
++#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
++//MPCC3_MPCC_TOP_GAIN
++#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
++#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
++//MPCC3_MPCC_BOT_GAIN_INSIDE
++#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
++#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
++//MPCC3_MPCC_BOT_GAIN_OUTSIDE
++#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
++#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
++//MPCC3_MPCC_BG_R_CR
++#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
++#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
++//MPCC3_MPCC_BG_G_Y
++#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
++#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
++//MPCC3_MPCC_BG_B_CB
++#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
++#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
++//MPCC3_MPCC_MEM_PWR_CTRL
++#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
++#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
++#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x4
++#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
++#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
++#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000030L
++//MPCC3_MPCC_STALL_STATUS
++#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT                                                0x0
++#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT                                                   0x4
++#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT                                                    0x8
++#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT                                                   0xc
++#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK                                                  0x00000001L
++#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK                                                     0x00000010L
++#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK                                                      0x00000100L
++#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK                                                     0x00001000L
++//MPCC3_MPCC_STATUS
++#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
++#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
++#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
++#define MPCC3_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT                                                     0x1d
++#define MPCC3_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT                                                 0x1e
++#define MPCC3_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT                                                      0x1f
++#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
++#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
++#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
++#define MPCC3_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK                                                       0x20000000L
++#define MPCC3_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK                                                   0x40000000L
++#define MPCC3_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK                                                        0x80000000L
++
++
++// addressBlock: dce_dc_mpc_mpcc4_dispdec
++//MPCC4_MPCC_TOP_SEL
++#define MPCC4_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
++#define MPCC4_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
++//MPCC4_MPCC_BOT_SEL
++#define MPCC4_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
++#define MPCC4_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
++//MPCC4_MPCC_OPP_ID
++#define MPCC4_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
++#define MPCC4_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
++//MPCC4_MPCC_CONTROL
++#define MPCC4_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
++#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
++#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
++#define MPCC4_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
++#define MPCC4_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
++#define MPCC4_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
++#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
++#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
++#define MPCC4_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
++#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
++#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
++#define MPCC4_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
++#define MPCC4_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
++#define MPCC4_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
++#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
++#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
++//MPCC4_MPCC_SM_CONTROL
++#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
++#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
++#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
++#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
++#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
++#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
++#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
++#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
++#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
++#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
++#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
++#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
++#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
++#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
++//MPCC4_MPCC_UPDATE_LOCK_SEL
++#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
++#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
++#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
++#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
++//MPCC4_MPCC_TOP_GAIN
++#define MPCC4_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
++#define MPCC4_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
++//MPCC4_MPCC_BOT_GAIN_INSIDE
++#define MPCC4_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
++#define MPCC4_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
++//MPCC4_MPCC_BOT_GAIN_OUTSIDE
++#define MPCC4_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
++#define MPCC4_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
++//MPCC4_MPCC_BG_R_CR
++#define MPCC4_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
++#define MPCC4_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
++//MPCC4_MPCC_BG_G_Y
++#define MPCC4_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
++#define MPCC4_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
++//MPCC4_MPCC_BG_B_CB
++#define MPCC4_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
++#define MPCC4_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
++//MPCC4_MPCC_MEM_PWR_CTRL
++#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
++#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
++#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x4
++#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
++#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
++#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000030L
++//MPCC4_MPCC_STALL_STATUS
++#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT                                                0x0
++#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT                                                   0x4
++#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT                                                    0x8
++#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT                                                   0xc
++#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK                                                  0x00000001L
++#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK                                                     0x00000010L
++#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK                                                      0x00000100L
++#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK                                                     0x00001000L
++//MPCC4_MPCC_STATUS
++#define MPCC4_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
++#define MPCC4_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
++#define MPCC4_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
++#define MPCC4_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT                                                     0x1d
++#define MPCC4_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT                                                 0x1e
++#define MPCC4_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT                                                      0x1f
++#define MPCC4_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
++#define MPCC4_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
++#define MPCC4_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
++#define MPCC4_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK                                                       0x20000000L
++#define MPCC4_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK                                                   0x40000000L
++#define MPCC4_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK                                                        0x80000000L
++
++
++// addressBlock: dce_dc_mpc_mpcc5_dispdec
++//MPCC5_MPCC_TOP_SEL
++#define MPCC5_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
++#define MPCC5_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
++//MPCC5_MPCC_BOT_SEL
++#define MPCC5_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
++#define MPCC5_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
++//MPCC5_MPCC_OPP_ID
++#define MPCC5_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
++#define MPCC5_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
++//MPCC5_MPCC_CONTROL
++#define MPCC5_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
++#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
++#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
++#define MPCC5_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
++#define MPCC5_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
++#define MPCC5_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
++#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
++#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
++#define MPCC5_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
++#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
++#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
++#define MPCC5_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
++#define MPCC5_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
++#define MPCC5_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
++#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
++#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
++//MPCC5_MPCC_SM_CONTROL
++#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
++#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
++#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
++#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
++#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
++#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
++#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
++#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
++#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
++#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
++#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
++#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
++#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
++#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
++//MPCC5_MPCC_UPDATE_LOCK_SEL
++#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
++#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
++#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
++#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
++//MPCC5_MPCC_TOP_GAIN
++#define MPCC5_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
++#define MPCC5_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
++//MPCC5_MPCC_BOT_GAIN_INSIDE
++#define MPCC5_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
++#define MPCC5_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
++//MPCC5_MPCC_BOT_GAIN_OUTSIDE
++#define MPCC5_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
++#define MPCC5_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
++//MPCC5_MPCC_BG_R_CR
++#define MPCC5_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
++#define MPCC5_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
++//MPCC5_MPCC_BG_G_Y
++#define MPCC5_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
++#define MPCC5_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
++//MPCC5_MPCC_BG_B_CB
++#define MPCC5_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
++#define MPCC5_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
++//MPCC5_MPCC_MEM_PWR_CTRL
++#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
++#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
++#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x4
++#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
++#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
++#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000030L
++//MPCC5_MPCC_STALL_STATUS
++#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT                                                0x0
++#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT                                                   0x4
++#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT                                                    0x8
++#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT                                                   0xc
++#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK                                                  0x00000001L
++#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK                                                     0x00000010L
++#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK                                                      0x00000100L
++#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK                                                     0x00001000L
++//MPCC5_MPCC_STATUS
++#define MPCC5_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
++#define MPCC5_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
++#define MPCC5_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
++#define MPCC5_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT                                                     0x1d
++#define MPCC5_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT                                                 0x1e
++#define MPCC5_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT                                                      0x1f
++#define MPCC5_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
++#define MPCC5_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
++#define MPCC5_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
++#define MPCC5_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK                                                       0x20000000L
++#define MPCC5_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK                                                   0x40000000L
++#define MPCC5_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK                                                        0x80000000L
++
++
++// addressBlock: dce_dc_mpc_mpcc6_dispdec
++//MPCC6_MPCC_TOP_SEL
++#define MPCC6_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
++#define MPCC6_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
++//MPCC6_MPCC_BOT_SEL
++#define MPCC6_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
++#define MPCC6_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
++//MPCC6_MPCC_OPP_ID
++#define MPCC6_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
++#define MPCC6_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
++//MPCC6_MPCC_CONTROL
++#define MPCC6_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
++#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
++#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
++#define MPCC6_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
++#define MPCC6_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
++#define MPCC6_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
++#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
++#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
++#define MPCC6_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
++#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
++#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
++#define MPCC6_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
++#define MPCC6_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
++#define MPCC6_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
++#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
++#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
++//MPCC6_MPCC_SM_CONTROL
++#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
++#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
++#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
++#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
++#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
++#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
++#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
++#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
++#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
++#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
++#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
++#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
++#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
++#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
++//MPCC6_MPCC_UPDATE_LOCK_SEL
++#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
++#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
++#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
++#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
++//MPCC6_MPCC_TOP_GAIN
++#define MPCC6_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
++#define MPCC6_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
++//MPCC6_MPCC_BOT_GAIN_INSIDE
++#define MPCC6_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
++#define MPCC6_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
++//MPCC6_MPCC_BOT_GAIN_OUTSIDE
++#define MPCC6_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
++#define MPCC6_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
++//MPCC6_MPCC_BG_R_CR
++#define MPCC6_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
++#define MPCC6_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
++//MPCC6_MPCC_BG_G_Y
++#define MPCC6_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
++#define MPCC6_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
++//MPCC6_MPCC_BG_B_CB
++#define MPCC6_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
++#define MPCC6_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
++//MPCC6_MPCC_MEM_PWR_CTRL
++#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
++#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
++#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x4
++#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
++#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
++#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000030L
++//MPCC6_MPCC_STALL_STATUS
++#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT                                                0x0
++#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT                                                   0x4
++#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT                                                    0x8
++#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT                                                   0xc
++#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK                                                  0x00000001L
++#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK                                                     0x00000010L
++#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK                                                      0x00000100L
++#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK                                                     0x00001000L
++//MPCC6_MPCC_STATUS
++#define MPCC6_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
++#define MPCC6_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
++#define MPCC6_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
++#define MPCC6_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT                                                     0x1d
++#define MPCC6_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT                                                 0x1e
++#define MPCC6_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT                                                      0x1f
++#define MPCC6_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
++#define MPCC6_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
++#define MPCC6_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
++#define MPCC6_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK                                                       0x20000000L
++#define MPCC6_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK                                                   0x40000000L
++#define MPCC6_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK                                                        0x80000000L
++
++
++// addressBlock: dce_dc_mpc_mpcc7_dispdec
++//MPCC7_MPCC_TOP_SEL
++#define MPCC7_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
++#define MPCC7_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
++//MPCC7_MPCC_BOT_SEL
++#define MPCC7_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
++#define MPCC7_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
++//MPCC7_MPCC_OPP_ID
++#define MPCC7_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
++#define MPCC7_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
++//MPCC7_MPCC_CONTROL
++#define MPCC7_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
++#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
++#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
++#define MPCC7_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
++#define MPCC7_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
++#define MPCC7_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
++#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
++#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
++#define MPCC7_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
++#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
++#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
++#define MPCC7_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
++#define MPCC7_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
++#define MPCC7_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
++#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
++#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
++//MPCC7_MPCC_SM_CONTROL
++#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
++#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
++#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
++#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
++#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
++#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
++#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
++#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
++#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
++#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
++#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
++#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
++#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
++#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
++//MPCC7_MPCC_UPDATE_LOCK_SEL
++#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
++#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
++#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
++#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
++//MPCC7_MPCC_TOP_GAIN
++#define MPCC7_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
++#define MPCC7_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
++//MPCC7_MPCC_BOT_GAIN_INSIDE
++#define MPCC7_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
++#define MPCC7_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
++//MPCC7_MPCC_BOT_GAIN_OUTSIDE
++#define MPCC7_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
++#define MPCC7_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
++//MPCC7_MPCC_BG_R_CR
++#define MPCC7_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
++#define MPCC7_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
++//MPCC7_MPCC_BG_G_Y
++#define MPCC7_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
++#define MPCC7_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
++//MPCC7_MPCC_BG_B_CB
++#define MPCC7_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
++#define MPCC7_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
++//MPCC7_MPCC_MEM_PWR_CTRL
++#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
++#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
++#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x4
++#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
++#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
++#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000030L
++//MPCC7_MPCC_STALL_STATUS
++#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT                                                0x0
++#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT                                                   0x4
++#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT                                                    0x8
++#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT                                                   0xc
++#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK                                                  0x00000001L
++#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK                                                     0x00000010L
++#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK                                                      0x00000100L
++#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK                                                     0x00001000L
++//MPCC7_MPCC_STATUS
++#define MPCC7_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
++#define MPCC7_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
++#define MPCC7_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
++#define MPCC7_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT                                                     0x1d
++#define MPCC7_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT                                                 0x1e
++#define MPCC7_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT                                                      0x1f
++#define MPCC7_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
++#define MPCC7_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
++#define MPCC7_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
++#define MPCC7_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK                                                       0x20000000L
++#define MPCC7_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK                                                   0x40000000L
++#define MPCC7_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK                                                        0x80000000L
++
++
++// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
++//MPC_CLOCK_CONTROL
++#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                      0x1
++#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT                                                            0x4
++#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                        0x00000002L
++#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK                                                              0x00000030L
++//MPC_SOFT_RESET
++#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT                                                               0x0
++#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT                                                               0x1
++#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT                                                               0x2
++#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT                                                               0x3
++#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT                                                            0xa
++#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT                                                            0xb
++#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT                                                            0xc
++#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT                                                            0xd
++#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT                                                            0x14
++#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT                                                            0x15
++#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT                                                            0x16
++#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT                                                            0x17
++#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT                                                                 0x1f
++#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK                                                                 0x00000001L
++#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK                                                                 0x00000002L
++#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK                                                                 0x00000004L
++#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK                                                                 0x00000008L
++#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK                                                              0x00000400L
++#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK                                                              0x00000800L
++#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK                                                              0x00001000L
++#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK                                                              0x00002000L
++#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK                                                              0x00100000L
++#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK                                                              0x00200000L
++#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK                                                              0x00400000L
++#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK                                                              0x00800000L
++#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK                                                                   0x80000000L
++//MPC_CRC_CTRL
++#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT                                                                       0x0
++#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT                                                                  0x4
++#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT                                                              0x8
++#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT                                                                0xa
++#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT                                                           0xc
++#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT                                                                  0x18
++#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT                                                         0x1c
++#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT                                                           0x1e
++#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT                                                              0x1f
++#define MPC_CRC_CTRL__MPC_CRC_EN_MASK                                                                         0x00000001L
++#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK                                                                    0x00000010L
++#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK                                                                0x00000300L
++#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK                                                                  0x00000400L
++#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK                                                             0x00003000L
++#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK                                                                    0x03000000L
++#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK                                                           0x10000000L
++#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK                                                             0x40000000L
++#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK                                                                0x80000000L
++//MPC_CRC_SEL_CONTROL
++#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT                                                           0x0
++#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT                                                           0x4
++#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT                                                              0x10
++#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK                                                             0x0000000FL
++#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK                                                             0x000000F0L
++#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK                                                                0xFFFF0000L
++//MPC_CRC_RESULT_AR
++#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT                                                            0x0
++#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT                                                            0x10
++#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK                                                              0x0000FFFFL
++#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK                                                              0xFFFF0000L
++//MPC_CRC_RESULT_GB
++#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT                                                            0x0
++#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT                                                            0x10
++#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK                                                              0x0000FFFFL
++#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK                                                              0xFFFF0000L
++//MPC_CRC_RESULT_C
++#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT                                                             0x0
++#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK                                                               0x0000FFFFL
++//MPC_PERFMON_EVENT_CTRL
++#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN__SHIFT                                                   0x0
++#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN_MASK                                                     0x00000001L
++//MPC_BYPASS_BG_AR
++#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT                                                          0x0
++#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT                                                           0x10
++#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK                                                            0x0000FFFFL
++#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK                                                             0xFFFF0000L
++//MPC_BYPASS_BG_GB
++#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT                                                            0x0
++#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT                                                           0x10
++#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK                                                              0x0000FFFFL
++#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK                                                             0xFFFF0000L
++//MPC_STALL_GRACE_WINDOW
++#define MPC_STALL_GRACE_WINDOW__MPC_STALL_GRACE_WINDOW_PERIOD__SHIFT                                          0x0
++#define MPC_STALL_GRACE_WINDOW__MPC_STALL_GRACE_WINDOW_PERIOD_MASK                                            0x000000FFL
++//MPC_HOST_READ_CONTROL
++#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                                  0x0
++#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                                    0x000000FFL
++//MPC_PENDING_TAKEN_STATUS_REG1
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT                                  0x0
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_TAKEN__SHIFT                                    0x1
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT                                   0x2
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_TAKEN__SHIFT                                     0x3
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT                                   0x4
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_TAKEN__SHIFT                                     0x5
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT                                  0x6
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_TAKEN__SHIFT                                    0x7
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT                                   0x8
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_TAKEN__SHIFT                                     0x9
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT                                   0xa
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_TAKEN__SHIFT                                     0xb
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT                                  0xc
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_TAKEN__SHIFT                                    0xd
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT                                   0xe
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_TAKEN__SHIFT                                     0xf
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT                                   0x10
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_TAKEN__SHIFT                                     0x11
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT                                  0x12
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_TAKEN__SHIFT                                    0x13
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT                                   0x14
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_TAKEN__SHIFT                                     0x15
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT                                   0x16
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_TAKEN__SHIFT                                     0x17
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_PENDING_MASK                                    0x00000001L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_TAKEN_MASK                                      0x00000002L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_PENDING_MASK                                     0x00000004L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_TAKEN_MASK                                       0x00000008L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_PENDING_MASK                                     0x00000010L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_TAKEN_MASK                                       0x00000020L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_PENDING_MASK                                    0x00000040L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_TAKEN_MASK                                      0x00000080L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_PENDING_MASK                                     0x00000100L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_TAKEN_MASK                                       0x00000200L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_PENDING_MASK                                     0x00000400L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_TAKEN_MASK                                       0x00000800L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_PENDING_MASK                                    0x00001000L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_TAKEN_MASK                                      0x00002000L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_PENDING_MASK                                     0x00004000L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_TAKEN_MASK                                       0x00008000L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_PENDING_MASK                                     0x00010000L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_TAKEN_MASK                                       0x00020000L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_PENDING_MASK                                    0x00040000L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_TAKEN_MASK                                      0x00080000L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_PENDING_MASK                                     0x00100000L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_TAKEN_MASK                                       0x00200000L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_PENDING_MASK                                     0x00400000L
++#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_TAKEN_MASK                                       0x00800000L
++//MPC_PENDING_TAKEN_STATUS_REG3
++#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT                                  0x0
++#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_TAKEN__SHIFT                                    0x1
++#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT                                  0x2
++#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_TAKEN__SHIFT                                    0x3
++#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT                                  0x4
++#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_TAKEN__SHIFT                                    0x5
++#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT                                  0x6
++#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_TAKEN__SHIFT                                    0x7
++#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_PENDING__SHIFT                                     0xc
++#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_TAKEN__SHIFT                                       0xd
++#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_PENDING__SHIFT                                     0xe
++#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_TAKEN__SHIFT                                       0xf
++#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_PENDING__SHIFT                                     0x10
++#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_TAKEN__SHIFT                                       0x11
++#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_PENDING__SHIFT                                     0x12
++#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_TAKEN__SHIFT                                       0x13
++#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK                                    0x00000001L
++#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_TAKEN_MASK                                      0x00000002L
++#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK                                    0x00000004L
++#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_TAKEN_MASK                                      0x00000008L
++#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK                                    0x00000010L
++#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_TAKEN_MASK                                      0x00000020L
++#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK                                    0x00000040L
++#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_TAKEN_MASK                                      0x00000080L
++#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_PENDING_MASK                                       0x00001000L
++#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_TAKEN_MASK                                         0x00002000L
++#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_PENDING_MASK                                       0x00004000L
++#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_TAKEN_MASK                                         0x00008000L
++#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_PENDING_MASK                                       0x00010000L
++#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_TAKEN_MASK                                         0x00020000L
++#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_PENDING_MASK                                       0x00040000L
++#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_TAKEN_MASK                                         0x00080000L
++//MPC_UPDATE_ACK_REG5
++#define MPC_UPDATE_ACK_REG5__IN_DPP0_SURFACE_UPDATE_ACK__SHIFT                                                0x0
++#define MPC_UPDATE_ACK_REG5__IN_DPP0_CONFIG_UPDATE_ACK__SHIFT                                                 0x1
++#define MPC_UPDATE_ACK_REG5__IN_DPP0_CURSOR_UPDATE_ACK__SHIFT                                                 0x2
++#define MPC_UPDATE_ACK_REG5__IN_DPP1_SURFACE_UPDATE_ACK__SHIFT                                                0x3
++#define MPC_UPDATE_ACK_REG5__IN_DPP1_CONFIG_UPDATE_ACK__SHIFT                                                 0x4
++#define MPC_UPDATE_ACK_REG5__IN_DPP1_CURSOR_UPDATE_ACK__SHIFT                                                 0x5
++#define MPC_UPDATE_ACK_REG5__IN_DPP2_SURFACE_UPDATE_ACK__SHIFT                                                0x6
++#define MPC_UPDATE_ACK_REG5__IN_DPP2_CONFIG_UPDATE_ACK__SHIFT                                                 0x7
++#define MPC_UPDATE_ACK_REG5__IN_DPP2_CURSOR_UPDATE_ACK__SHIFT                                                 0x8
++#define MPC_UPDATE_ACK_REG5__IN_DPP3_SURFACE_UPDATE_ACK__SHIFT                                                0x9
++#define MPC_UPDATE_ACK_REG5__IN_DPP3_CONFIG_UPDATE_ACK__SHIFT                                                 0xa
++#define MPC_UPDATE_ACK_REG5__IN_DPP3_CURSOR_UPDATE_ACK__SHIFT                                                 0xb
++#define MPC_UPDATE_ACK_REG5__MPCC0_CONFIG_UPDATE_ACK__SHIFT                                                   0xf
++#define MPC_UPDATE_ACK_REG5__MPCC1_CONFIG_UPDATE_ACK__SHIFT                                                   0x10
++#define MPC_UPDATE_ACK_REG5__MPCC2_CONFIG_UPDATE_ACK__SHIFT                                                   0x11
++#define MPC_UPDATE_ACK_REG5__MPCC3_CONFIG_UPDATE_ACK__SHIFT                                                   0x12
++#define MPC_UPDATE_ACK_REG5__OUT_OPP0_CONFIG_UPDATE_ACK__SHIFT                                                0x14
++#define MPC_UPDATE_ACK_REG5__OUT_OPP1_CONFIG_UPDATE_ACK__SHIFT                                                0x15
++#define MPC_UPDATE_ACK_REG5__OUT_OPP2_CONFIG_UPDATE_ACK__SHIFT                                                0x16
++#define MPC_UPDATE_ACK_REG5__OUT_OPP3_CONFIG_UPDATE_ACK__SHIFT                                                0x17
++#define MPC_UPDATE_ACK_REG5__IN_DPP0_SURFACE_UPDATE_ACK_MASK                                                  0x00000001L
++#define MPC_UPDATE_ACK_REG5__IN_DPP0_CONFIG_UPDATE_ACK_MASK                                                   0x00000002L
++#define MPC_UPDATE_ACK_REG5__IN_DPP0_CURSOR_UPDATE_ACK_MASK                                                   0x00000004L
++#define MPC_UPDATE_ACK_REG5__IN_DPP1_SURFACE_UPDATE_ACK_MASK                                                  0x00000008L
++#define MPC_UPDATE_ACK_REG5__IN_DPP1_CONFIG_UPDATE_ACK_MASK                                                   0x00000010L
++#define MPC_UPDATE_ACK_REG5__IN_DPP1_CURSOR_UPDATE_ACK_MASK                                                   0x00000020L
++#define MPC_UPDATE_ACK_REG5__IN_DPP2_SURFACE_UPDATE_ACK_MASK                                                  0x00000040L
++#define MPC_UPDATE_ACK_REG5__IN_DPP2_CONFIG_UPDATE_ACK_MASK                                                   0x00000080L
++#define MPC_UPDATE_ACK_REG5__IN_DPP2_CURSOR_UPDATE_ACK_MASK                                                   0x00000100L
++#define MPC_UPDATE_ACK_REG5__IN_DPP3_SURFACE_UPDATE_ACK_MASK                                                  0x00000200L
++#define MPC_UPDATE_ACK_REG5__IN_DPP3_CONFIG_UPDATE_ACK_MASK                                                   0x00000400L
++#define MPC_UPDATE_ACK_REG5__IN_DPP3_CURSOR_UPDATE_ACK_MASK                                                   0x00000800L
++#define MPC_UPDATE_ACK_REG5__MPCC0_CONFIG_UPDATE_ACK_MASK                                                     0x00008000L
++#define MPC_UPDATE_ACK_REG5__MPCC1_CONFIG_UPDATE_ACK_MASK                                                     0x00010000L
++#define MPC_UPDATE_ACK_REG5__MPCC2_CONFIG_UPDATE_ACK_MASK                                                     0x00020000L
++#define MPC_UPDATE_ACK_REG5__MPCC3_CONFIG_UPDATE_ACK_MASK                                                     0x00040000L
++#define MPC_UPDATE_ACK_REG5__OUT_OPP0_CONFIG_UPDATE_ACK_MASK                                                  0x00100000L
++#define MPC_UPDATE_ACK_REG5__OUT_OPP1_CONFIG_UPDATE_ACK_MASK                                                  0x00200000L
++#define MPC_UPDATE_ACK_REG5__OUT_OPP2_CONFIG_UPDATE_ACK_MASK                                                  0x00400000L
++#define MPC_UPDATE_ACK_REG5__OUT_OPP3_CONFIG_UPDATE_ACK_MASK                                                  0x00800000L
++//ADR_CFG_CUR_VUPDATE_LOCK_SET0
++#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
++#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
++//ADR_CFG_VUPDATE_LOCK_SET0
++#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
++#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
++//ADR_VUPDATE_LOCK_SET0
++#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
++#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
++//CFG_VUPDATE_LOCK_SET0
++#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
++#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
++//CUR_VUPDATE_LOCK_SET0
++#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
++#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
++//ADR_CFG_CUR_VUPDATE_LOCK_SET1
++#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
++#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
++//ADR_CFG_VUPDATE_LOCK_SET1
++#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
++#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
++//ADR_VUPDATE_LOCK_SET1
++#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
++#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
++//CFG_VUPDATE_LOCK_SET1
++#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
++#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
++//CUR_VUPDATE_LOCK_SET1
++#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
++#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
++//ADR_CFG_CUR_VUPDATE_LOCK_SET2
++#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
++#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
++//ADR_CFG_VUPDATE_LOCK_SET2
++#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
++#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
++//ADR_VUPDATE_LOCK_SET2
++#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
++#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
++//CFG_VUPDATE_LOCK_SET2
++#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
++#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
++//CUR_VUPDATE_LOCK_SET2
++#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
++#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
++//ADR_CFG_CUR_VUPDATE_LOCK_SET3
++#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
++#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
++//ADR_CFG_VUPDATE_LOCK_SET3
++#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
++#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
++//ADR_VUPDATE_LOCK_SET3
++#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
++#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
++//CFG_VUPDATE_LOCK_SET3
++#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
++#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
++//CUR_VUPDATE_LOCK_SET3
++#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
++#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
++//MPC_OUT0_MUX
++#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
++#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
++//MPC_OUT0_DENORM_CONTROL
++#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
++#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
++#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
++#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
++#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
++#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
++//MPC_OUT0_DENORM_CLAMP_G_Y
++#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
++#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
++#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
++#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
++//MPC_OUT0_DENORM_CLAMP_B_CB
++#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
++#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
++#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
++#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
++//MPC_OUT1_MUX
++#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
++#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
++//MPC_OUT1_DENORM_CONTROL
++#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
++#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
++#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
++#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
++#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
++#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
++//MPC_OUT1_DENORM_CLAMP_G_Y
++#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
++#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
++#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
++#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
++//MPC_OUT1_DENORM_CLAMP_B_CB
++#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
++#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
++#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
++#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
++//MPC_OUT2_MUX
++#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
++#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
++//MPC_OUT2_DENORM_CONTROL
++#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
++#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
++#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
++#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
++#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
++#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
++//MPC_OUT2_DENORM_CLAMP_G_Y
++#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
++#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
++#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
++#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
++//MPC_OUT2_DENORM_CLAMP_B_CB
++#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
++#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
++#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
++#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
++//MPC_OUT3_MUX
++#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
++#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
++//MPC_OUT3_DENORM_CONTROL
++#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
++#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
++#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
++#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
++#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
++#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
++//MPC_OUT3_DENORM_CLAMP_G_Y
++#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
++#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
++#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
++#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
++//MPC_OUT3_DENORM_CLAMP_B_CB
++#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
++#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
++#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
++#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
++
++
++// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
++//MPCC_OGAM0_MPCC_OGAM_MODE
++#define MPCC_OGAM0_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT                                                      0x0
++#define MPCC_OGAM0_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK                                                        0x00000003L
++//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX
++#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
++#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
++//MPCC_OGAM0_MPCC_OGAM_LUT_DATA
++#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
++#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0007FFFFL
++//MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL
++#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                              0x0
++#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT                                    0x3
++#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT                                  0x4
++#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                                0x00000007L
++#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK                                      0x00000008L
++#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK                                    0x00000030L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
++//MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
++//MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
++//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
++//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
++//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
++//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
++//MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
++//MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
++//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
++//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
++//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
++//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
++
++
++// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
++//MPCC_OGAM1_MPCC_OGAM_MODE
++#define MPCC_OGAM1_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT                                                      0x0
++#define MPCC_OGAM1_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK                                                        0x00000003L
++//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX
++#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
++#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
++//MPCC_OGAM1_MPCC_OGAM_LUT_DATA
++#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
++#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0007FFFFL
++//MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL
++#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                              0x0
++#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT                                    0x3
++#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT                                  0x4
++#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                                0x00000007L
++#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK                                      0x00000008L
++#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK                                    0x00000030L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
++//MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
++//MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
++//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
++//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
++//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
++//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
++//MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
++//MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
++//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
++//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
++//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
++//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
++
++
++// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
++//MPCC_OGAM2_MPCC_OGAM_MODE
++#define MPCC_OGAM2_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT                                                      0x0
++#define MPCC_OGAM2_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK                                                        0x00000003L
++//MPCC_OGAM2_MPCC_OGAM_LUT_INDEX
++#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
++#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
++//MPCC_OGAM2_MPCC_OGAM_LUT_DATA
++#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
++#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0007FFFFL
++//MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL
++#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                              0x0
++#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT                                    0x3
++#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT                                  0x4
++#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                                0x00000007L
++#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK                                      0x00000008L
++#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK                                    0x00000030L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
++//MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
++//MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
++//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
++//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
++//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
++//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
++//MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
++//MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
++//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
++//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
++//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
++//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
++
++
++// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
++//MPCC_OGAM3_MPCC_OGAM_MODE
++#define MPCC_OGAM3_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT                                                      0x0
++#define MPCC_OGAM3_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK                                                        0x00000003L
++//MPCC_OGAM3_MPCC_OGAM_LUT_INDEX
++#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
++#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
++//MPCC_OGAM3_MPCC_OGAM_LUT_DATA
++#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
++#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0007FFFFL
++//MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL
++#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                              0x0
++#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT                                    0x3
++#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT                                  0x4
++#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                                0x00000007L
++#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK                                      0x00000008L
++#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK                                    0x00000030L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
++//MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
++//MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
++//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
++//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
++//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
++//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
++//MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
++//MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
++//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
++//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
++//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
++//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
++
++
++// addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec
++//MPCC_OGAM4_MPCC_OGAM_MODE
++#define MPCC_OGAM4_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT                                                      0x0
++#define MPCC_OGAM4_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK                                                        0x00000003L
++//MPCC_OGAM4_MPCC_OGAM_LUT_INDEX
++#define MPCC_OGAM4_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
++#define MPCC_OGAM4_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
++//MPCC_OGAM4_MPCC_OGAM_LUT_DATA
++#define MPCC_OGAM4_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
++#define MPCC_OGAM4_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0007FFFFL
++//MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL
++#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                              0x0
++#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT                                    0x3
++#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT                                  0x4
++#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                                0x00000007L
++#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK                                      0x00000008L
++#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK                                    0x00000030L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
++//MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
++//MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
++//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
++//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
++//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
++//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
++//MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
++//MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
++//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
++//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
++//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
++//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
++
++
++// addressBlock: dce_dc_mpc_mpcc_ogam5_dispdec
++//MPCC_OGAM5_MPCC_OGAM_MODE
++#define MPCC_OGAM5_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT                                                      0x0
++#define MPCC_OGAM5_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK                                                        0x00000003L
++//MPCC_OGAM5_MPCC_OGAM_LUT_INDEX
++#define MPCC_OGAM5_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
++#define MPCC_OGAM5_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
++//MPCC_OGAM5_MPCC_OGAM_LUT_DATA
++#define MPCC_OGAM5_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
++#define MPCC_OGAM5_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0007FFFFL
++//MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL
++#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                              0x0
++#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT                                    0x3
++#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT                                  0x4
++#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                                0x00000007L
++#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK                                      0x00000008L
++#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK                                    0x00000030L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
++//MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
++//MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
++//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
++//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
++//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
++//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
++//MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
++//MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
++//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
++//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
++//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
++//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
++
++
++// addressBlock: dce_dc_mpc_mpcc_ogam6_dispdec
++//MPCC_OGAM6_MPCC_OGAM_MODE
++#define MPCC_OGAM6_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT                                                      0x0
++#define MPCC_OGAM6_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK                                                        0x00000003L
++//MPCC_OGAM6_MPCC_OGAM_LUT_INDEX
++#define MPCC_OGAM6_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
++#define MPCC_OGAM6_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
++//MPCC_OGAM6_MPCC_OGAM_LUT_DATA
++#define MPCC_OGAM6_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
++#define MPCC_OGAM6_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0007FFFFL
++//MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL
++#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                              0x0
++#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT                                    0x3
++#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT                                  0x4
++#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                                0x00000007L
++#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK                                      0x00000008L
++#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK                                    0x00000030L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
++//MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
++//MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
++//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
++//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
++//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
++//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
++//MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
++//MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
++//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
++//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
++//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
++//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
++
++
++// addressBlock: dce_dc_mpc_mpcc_ogam7_dispdec
++//MPCC_OGAM7_MPCC_OGAM_MODE
++#define MPCC_OGAM7_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT                                                      0x0
++#define MPCC_OGAM7_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK                                                        0x00000003L
++//MPCC_OGAM7_MPCC_OGAM_LUT_INDEX
++#define MPCC_OGAM7_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
++#define MPCC_OGAM7_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
++//MPCC_OGAM7_MPCC_OGAM_LUT_DATA
++#define MPCC_OGAM7_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
++#define MPCC_OGAM7_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0007FFFFL
++//MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL
++#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                              0x0
++#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT                                    0x3
++#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT                                  0x4
++#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                                0x00000007L
++#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK                                      0x00000008L
++#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK                                    0x00000030L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
++//MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
++//MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
++//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
++//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
++//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
++//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
++//MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
++//MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
++//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
++//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
++//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
++//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
++//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
++#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
++
++
++// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
++//MPC_OUT_CSC_COEF_FORMAT
++#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT                                                 0x0
++#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT                                                 0x1
++#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT                                                 0x2
++#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT                                                 0x3
++#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK                                                   0x00000001L
++#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK                                                   0x00000002L
++#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK                                                   0x00000004L
++#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK                                                   0x00000008L
++//MPC_OUT0_CSC_MODE
++#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
++#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
++//MPC_OUT0_CSC_C11_C12_A
++#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
++#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
++#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
++//MPC_OUT0_CSC_C13_C14_A
++#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
++#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
++#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
++//MPC_OUT0_CSC_C21_C22_A
++#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
++#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
++#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
++//MPC_OUT0_CSC_C23_C24_A
++#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
++#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
++#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
++//MPC_OUT0_CSC_C31_C32_A
++#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
++#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
++#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
++//MPC_OUT0_CSC_C33_C34_A
++#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
++#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
++#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
++//MPC_OUT0_CSC_C11_C12_B
++#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
++#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
++#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
++//MPC_OUT0_CSC_C13_C14_B
++#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
++#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
++#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
++//MPC_OUT0_CSC_C21_C22_B
++#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
++#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
++#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
++//MPC_OUT0_CSC_C23_C24_B
++#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
++#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
++#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
++//MPC_OUT0_CSC_C31_C32_B
++#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
++#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
++#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
++//MPC_OUT0_CSC_C33_C34_B
++#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
++#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
++#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
++//MPC_OUT1_CSC_MODE
++#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
++#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
++//MPC_OUT1_CSC_C11_C12_A
++#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
++#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
++#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
++//MPC_OUT1_CSC_C13_C14_A
++#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
++#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
++#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
++//MPC_OUT1_CSC_C21_C22_A
++#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
++#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
++#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
++//MPC_OUT1_CSC_C23_C24_A
++#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
++#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
++#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
++//MPC_OUT1_CSC_C31_C32_A
++#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
++#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
++#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
++//MPC_OUT1_CSC_C33_C34_A
++#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
++#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
++#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
++//MPC_OUT1_CSC_C11_C12_B
++#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
++#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
++#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
++//MPC_OUT1_CSC_C13_C14_B
++#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
++#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
++#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
++//MPC_OUT1_CSC_C21_C22_B
++#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
++#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
++#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
++//MPC_OUT1_CSC_C23_C24_B
++#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
++#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
++#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
++//MPC_OUT1_CSC_C31_C32_B
++#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
++#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
++#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
++//MPC_OUT1_CSC_C33_C34_B
++#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
++#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
++#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
++//MPC_OUT2_CSC_MODE
++#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
++#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
++//MPC_OUT2_CSC_C11_C12_A
++#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
++#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
++#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
++//MPC_OUT2_CSC_C13_C14_A
++#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
++#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
++#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
++//MPC_OUT2_CSC_C21_C22_A
++#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
++#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
++#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
++//MPC_OUT2_CSC_C23_C24_A
++#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
++#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
++#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
++//MPC_OUT2_CSC_C31_C32_A
++#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
++#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
++#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
++//MPC_OUT2_CSC_C33_C34_A
++#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
++#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
++#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
++//MPC_OUT2_CSC_C11_C12_B
++#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
++#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
++#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
++//MPC_OUT2_CSC_C13_C14_B
++#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
++#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
++#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
++//MPC_OUT2_CSC_C21_C22_B
++#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
++#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
++#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
++//MPC_OUT2_CSC_C23_C24_B
++#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
++#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
++#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
++//MPC_OUT2_CSC_C31_C32_B
++#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
++#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
++#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
++//MPC_OUT2_CSC_C33_C34_B
++#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
++#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
++#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
++//MPC_OUT3_CSC_MODE
++#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
++#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
++//MPC_OUT3_CSC_C11_C12_A
++#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
++#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
++#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
++//MPC_OUT3_CSC_C13_C14_A
++#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
++#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
++#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
++//MPC_OUT3_CSC_C21_C22_A
++#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
++#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
++#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
++//MPC_OUT3_CSC_C23_C24_A
++#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
++#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
++#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
++//MPC_OUT3_CSC_C31_C32_A
++#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
++#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
++#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
++//MPC_OUT3_CSC_C33_C34_A
++#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
++#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
++#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
++#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
++//MPC_OUT3_CSC_C11_C12_B
++#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
++#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
++#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
++//MPC_OUT3_CSC_C13_C14_B
++#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
++#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
++#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
++//MPC_OUT3_CSC_C21_C22_B
++#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
++#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
++#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
++//MPC_OUT3_CSC_C23_C24_B
++#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
++#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
++#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
++//MPC_OUT3_CSC_C31_C32_B
++#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
++#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
++#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
++//MPC_OUT3_CSC_C33_C34_B
++#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
++#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
++#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
++#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
++
++
++// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON15_PERFCOUNTER_CNTL
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
++#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
++//DC_PERFMON15_PERFCOUNTER_CNTL2
++#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
++#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
++#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
++#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
++#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
++#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
++#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
++#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
++#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
++#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
++//DC_PERFMON15_PERFCOUNTER_STATE
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
++#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
++//DC_PERFMON15_PERFMON_CNTL
++#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
++#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
++#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
++#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
++#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
++#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
++#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
++#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
++#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
++#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
++#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
++#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
++//DC_PERFMON15_PERFMON_CNTL2
++#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
++#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
++#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
++#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
++#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
++#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
++#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
++#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
++//DC_PERFMON15_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
++#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
++//DC_PERFMON15_PERFMON_CVALUE_LOW
++#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
++#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
++//DC_PERFMON15_PERFMON_HI
++#define DC_PERFMON15_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
++#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
++#define DC_PERFMON15_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
++#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
++//DC_PERFMON15_PERFMON_LOW
++#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
++#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_opp_abm0_dispdec
++//BL1_PWM_AMBIENT_LIGHT_LEVEL
++#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                       0x0
++#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                         0x0001FFFFL
++//BL1_PWM_USER_LEVEL
++#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                         0x0
++#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                           0x0001FFFFL
++//BL1_PWM_TARGET_ABM_LEVEL
++#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                             0x0
++#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                               0x0001FFFFL
++//BL1_PWM_CURRENT_ABM_LEVEL
++#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                           0x0
++#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                             0x0001FFFFL
++//BL1_PWM_FINAL_DUTY_CYCLE
++#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                             0x0
++#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                               0x0001FFFFL
++//BL1_PWM_MINIMUM_DUTY_CYCLE
++#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                         0x0
++#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                           0x0001FFFFL
++//BL1_PWM_ABM_CNTL
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                           0x0
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                                 0x1
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                     0x2
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                        0x3
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                                    0x10
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                             0x00000001L
++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                                   0x00000002L
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                       0x00000004L
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                          0x00000008L
++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                      0xFFFF0000L
++//BL1_PWM_BL_UPDATE_SAMPLE_RATE
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                          0x0
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT               0x1
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                       0x8
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT    0x10
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                              0x1f
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                            0x00000001L
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                 0x00000002L
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                         0x0000FF00L
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK      0x00FF0000L
++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                0x80000000L
++//BL1_PWM_GRP2_REG_LOCK
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                                   0x0
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                         0x8
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                      0x10
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                       0x11
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x18
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1f
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                     0x00000001L
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                           0x00000100L
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                        0x00010000L
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                         0x000E0000L
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                     0x01000000L
++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                        0x80000000L
++//DC_ABM1_CNTL
++#define DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                          0x0
++#define DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                           0x4
++#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT                                                               0x8
++#define DC_ABM1_CNTL__ABM1_EN_MASK                                                                            0x00000001L
++#define DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                             0x00000010L
++#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK                                                                 0x00000700L
++//DC_ABM1_IPCSC_COEFF_SEL
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                                0x0
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                                0x8
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                                0x10
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                                    0x1f
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                                  0x0000000FL
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                                  0x00000F00L
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                                  0x000F0000L
++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                      0x80000000L
++//DC_ABM1_ACE_OFFSET_SLOPE_0
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                                   0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                                  0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                      0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                     0x00007FFFL
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                                    0x07FF0000L
++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                        0x80000000L
++//DC_ABM1_ACE_OFFSET_SLOPE_1
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                                   0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                                  0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                      0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                     0x00007FFFL
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                                    0x07FF0000L
++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                        0x80000000L
++//DC_ABM1_ACE_OFFSET_SLOPE_2
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                                   0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                                  0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                      0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                     0x00007FFFL
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                                    0x07FF0000L
++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                        0x80000000L
++//DC_ABM1_ACE_OFFSET_SLOPE_3
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                                   0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                                  0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                      0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                     0x00007FFFL
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                                    0x07FF0000L
++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                        0x80000000L
++//DC_ABM1_ACE_OFFSET_SLOPE_4
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                                   0x0
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                                  0x10
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                      0x1f
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                     0x00007FFFL
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                                    0x07FF0000L
++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                        0x80000000L
++//DC_ABM1_ACE_THRES_12
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                         0x0
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                         0x10
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                            0x1f
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                           0x000003FFL
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                           0x03FF0000L
++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                              0x80000000L
++//DC_ABM1_ACE_THRES_34
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                         0x0
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                         0x10
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                           0x1c
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                        0x1d
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                         0x1e
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                            0x1f
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                           0x000003FFL
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                           0x03FF0000L
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                             0x10000000L
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                          0x20000000L
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                           0x40000000L
++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                              0x80000000L
++//DC_ABM1_ACE_CNTL_MISC
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                            0x0
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                      0x8
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                              0x00000001L
++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                        0x00000100L
++//DC_ABM1_HGLS_REG_READ_PROGRESS
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                                   0x0
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                                   0x1
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                                   0x2
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                                  0x8
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                                  0x9
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                                  0xa
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                            0x10
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                            0x18
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                            0x1f
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                     0x00000001L
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                     0x00000002L
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                     0x00000004L
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                                    0x00000100L
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                                    0x00000200L
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                                    0x00000400L
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                              0x00010000L
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                              0x01000000L
++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                              0x80000000L
++//DC_ABM1_HG_MISC_CTRL
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                                  0x0
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                         0x8
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                                0xc
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                            0x10
++#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                           0x14
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                                  0x17
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                                  0x18
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                                 0x1c
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                          0x1d
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                        0x1e
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                       0x1f
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                                    0x00000003L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                           0x00000100L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                                  0x00001000L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                              0x00030000L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                             0x00100000L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                                    0x00800000L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                                    0x07000000L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                                   0x10000000L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                            0x20000000L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                          0x40000000L
++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                         0x80000000L
++//DC_ABM1_LS_SUM_OF_LUMA
++#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                                    0x0
++#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                      0xFFFFFFFFL
++//DC_ABM1_LS_MIN_MAX_LUMA
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                      0x0
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                      0x10
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                        0x000003FFL
++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                        0x03FF0000L
++//DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                                    0x0
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                                    0x10
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                      0x000003FFL
++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                      0x03FF0000L
++//DC_ABM1_LS_PIXEL_COUNT
++#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                                    0x0
++#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                                0x18
++#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                      0x00FFFFFFL
++#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                                  0xFF000000L
++//DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                            0x0
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                            0x10
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                       0x1f
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                              0x000003FFL
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                              0x03FF0000L
++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                         0x80000000L
++//DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
++#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                                0x0
++#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                                  0x00FFFFFFL
++//DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
++#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                                0x0
++#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                                  0x00FFFFFFL
++//DC_ABM1_HG_SAMPLE_RATE
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                           0x0
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                                0x1
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                        0x8
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                     0x10
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                     0x1f
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                             0x00000001L
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                                  0x00000002L
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                          0x0000FF00L
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                       0x00FF0000L
++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                       0x80000000L
++//DC_ABM1_LS_SAMPLE_RATE
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                           0x0
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                                0x1
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                        0x8
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                     0x10
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                     0x1f
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                             0x00000001L
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                                  0x00000002L
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                          0x0000FF00L
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                       0x00FF0000L
++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                       0x80000000L
++//DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
++#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                                    0x0
++#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                      0xFFFFFFFFL
++//DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
++#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                                    0x0
++#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                      0xFFFFFFFFL
++//DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
++#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                                  0x0
++#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                                    0xFFFFFFFFL
++//DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
++#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                                0x0
++#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                                  0xFFFFFFFFL
++//DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
++#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                                0x0
++#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                                  0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_1
++#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                          0x0
++#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                            0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_2
++#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                          0x0
++#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                            0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_3
++#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                          0x0
++#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                            0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_4
++#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                          0x0
++#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                            0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_5
++#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                          0x0
++#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                            0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_6
++#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                          0x0
++#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                            0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_7
++#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                          0x0
++#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                            0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_8
++#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                          0x0
++#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                            0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_9
++#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                          0x0
++#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                            0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_10
++#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                        0x0
++#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                          0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_11
++#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                        0x0
++#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                          0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_12
++#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                        0x0
++#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                          0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_13
++#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                        0x0
++#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                          0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_14
++#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                        0x0
++#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                          0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_15
++#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                        0x0
++#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                          0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_16
++#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                        0x0
++#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                          0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_17
++#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                        0x0
++#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                          0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_18
++#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                        0x0
++#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                          0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_19
++#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                        0x0
++#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                          0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_20
++#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                        0x0
++#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                          0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_21
++#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                        0x0
++#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                          0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_22
++#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                        0x0
++#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                          0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_23
++#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                        0x0
++#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                          0xFFFFFFFFL
++//DC_ABM1_HG_RESULT_24
++#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                        0x0
++#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                          0xFFFFFFFFL
++//DC_ABM1_BL_MASTER_LOCK
++#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                                    0x1f
++#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                      0x80000000L
++
++
++// addressBlock: dce_dc_opp_fmt0_dispdec
++//FMT0_FMT_CLAMP_COMPONENT_R
++#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
++#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
++#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
++#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
++//FMT0_FMT_CLAMP_COMPONENT_G
++#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
++#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
++#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
++#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
++//FMT0_FMT_CLAMP_COMPONENT_B
++#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
++#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
++#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
++#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
++//FMT0_FMT_DYNAMIC_EXP_CNTL
++#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
++#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
++#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
++#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
++//FMT0_FMT_CONTROL
++#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
++#define FMT0_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT                                                       0x4
++#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
++#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
++#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
++#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
++#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
++#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
++#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
++#define FMT0_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT                                                               0x1c
++#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
++#define FMT0_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK                                                         0x00000010L
++#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
++#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
++#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
++#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
++#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
++#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
++#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
++#define FMT0_FMT_CONTROL__FMT_PTI_ENABLE_MASK                                                                 0x10000000L
++//FMT0_FMT_BIT_DEPTH_CONTROL
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
++#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
++//FMT0_FMT_DITHER_RAND_R_SEED
++#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
++#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
++#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
++#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
++//FMT0_FMT_DITHER_RAND_G_SEED
++#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
++#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
++#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
++#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
++//FMT0_FMT_DITHER_RAND_B_SEED
++#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
++#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
++#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
++#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
++//FMT0_FMT_CLAMP_CNTL
++#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
++#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
++#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
++#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
++//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL
++#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
++#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
++//FMT0_FMT_MAP420_MEMORY_CONTROL
++#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
++#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
++#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
++#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
++#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
++#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
++#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
++#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
++//FMT0_FMT_422_CONTROL
++#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
++#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
++
++
++// addressBlock: dce_dc_opp_dpg0_dispdec
++//DPG0_DPG_CONTROL
++#define DPG0_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
++#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
++#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
++#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
++#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
++#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
++#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
++#define DPG0_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
++#define DPG0_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
++#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
++#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
++#define DPG0_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
++#define DPG0_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
++#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
++//DPG0_DPG_RAMP_CONTROL
++#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
++#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
++#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
++#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
++#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
++#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
++//DPG0_DPG_DIMENSIONS
++#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
++#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
++#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
++#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
++//DPG0_DPG_COLOUR_R_CR
++#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
++#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
++#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
++#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
++//DPG0_DPG_COLOUR_G_Y
++#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
++#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
++#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
++#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
++//DPG0_DPG_COLOUR_B_CB
++#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
++#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
++#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
++#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
++//DPG0_DPG_OFFSET_SEGMENT
++#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
++#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
++#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
++#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
++//DPG0_DPG_STATUS
++#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
++#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
++
++
++// addressBlock: dce_dc_opp_oppbuf0_dispdec
++//OPPBUF0_OPPBUF_CONTROL
++#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
++#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
++#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
++#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
++#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
++#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
++#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
++#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
++#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
++#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
++//OPPBUF0_OPPBUF_3D_PARAMETERS_0
++#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
++#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
++#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
++#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
++#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
++#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
++//OPPBUF0_OPPBUF_3D_PARAMETERS_1
++#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
++#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
++#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
++#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
++//OPPBUF0_OPPBUF_CONTROL1
++#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
++#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
++
++
++// addressBlock: dce_dc_opp_opp_pipe0_dispdec
++//OPP_PIPE0_OPP_PIPE_CONTROL
++#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
++#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
++#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
++#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
++#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
++#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
++
++
++// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
++//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
++//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
++//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
++//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
++//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
++#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
++
++
++// addressBlock: dce_dc_opp_fmt1_dispdec
++//FMT1_FMT_CLAMP_COMPONENT_R
++#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
++#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
++#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
++#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
++//FMT1_FMT_CLAMP_COMPONENT_G
++#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
++#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
++#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
++#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
++//FMT1_FMT_CLAMP_COMPONENT_B
++#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
++#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
++#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
++#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
++//FMT1_FMT_DYNAMIC_EXP_CNTL
++#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
++#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
++#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
++#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
++//FMT1_FMT_CONTROL
++#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
++#define FMT1_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT                                                       0x4
++#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
++#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
++#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
++#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
++#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
++#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
++#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
++#define FMT1_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT                                                               0x1c
++#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
++#define FMT1_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK                                                         0x00000010L
++#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
++#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
++#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
++#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
++#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
++#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
++#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
++#define FMT1_FMT_CONTROL__FMT_PTI_ENABLE_MASK                                                                 0x10000000L
++//FMT1_FMT_BIT_DEPTH_CONTROL
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
++#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
++//FMT1_FMT_DITHER_RAND_R_SEED
++#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
++#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
++#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
++#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
++//FMT1_FMT_DITHER_RAND_G_SEED
++#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
++#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
++#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
++#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
++//FMT1_FMT_DITHER_RAND_B_SEED
++#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
++#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
++#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
++#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
++//FMT1_FMT_CLAMP_CNTL
++#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
++#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
++#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
++#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
++//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL
++#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
++#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
++//FMT1_FMT_MAP420_MEMORY_CONTROL
++#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
++#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
++#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
++#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
++#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
++#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
++#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
++#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
++//FMT1_FMT_422_CONTROL
++#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
++#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
++
++
++// addressBlock: dce_dc_opp_dpg1_dispdec
++//DPG1_DPG_CONTROL
++#define DPG1_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
++#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
++#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
++#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
++#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
++#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
++#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
++#define DPG1_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
++#define DPG1_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
++#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
++#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
++#define DPG1_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
++#define DPG1_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
++#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
++//DPG1_DPG_RAMP_CONTROL
++#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
++#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
++#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
++#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
++#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
++#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
++//DPG1_DPG_DIMENSIONS
++#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
++#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
++#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
++#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
++//DPG1_DPG_COLOUR_R_CR
++#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
++#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
++#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
++#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
++//DPG1_DPG_COLOUR_G_Y
++#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
++#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
++#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
++#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
++//DPG1_DPG_COLOUR_B_CB
++#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
++#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
++#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
++#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
++//DPG1_DPG_OFFSET_SEGMENT
++#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
++#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
++#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
++#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
++//DPG1_DPG_STATUS
++#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
++#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
++
++
++// addressBlock: dce_dc_opp_oppbuf1_dispdec
++//OPPBUF1_OPPBUF_CONTROL
++#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
++#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
++#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
++#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
++#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
++#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
++#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
++#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
++#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
++#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
++//OPPBUF1_OPPBUF_3D_PARAMETERS_0
++#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
++#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
++#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
++#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
++#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
++#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
++//OPPBUF1_OPPBUF_3D_PARAMETERS_1
++#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
++#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
++#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
++#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
++//OPPBUF1_OPPBUF_CONTROL1
++#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
++#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
++
++
++// addressBlock: dce_dc_opp_opp_pipe1_dispdec
++//OPP_PIPE1_OPP_PIPE_CONTROL
++#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
++#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
++#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
++#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
++#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
++#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
++
++
++// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
++//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
++//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
++//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
++//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
++//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
++#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
++
++
++// addressBlock: dce_dc_opp_fmt2_dispdec
++//FMT2_FMT_CLAMP_COMPONENT_R
++#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
++#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
++#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
++#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
++//FMT2_FMT_CLAMP_COMPONENT_G
++#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
++#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
++#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
++#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
++//FMT2_FMT_CLAMP_COMPONENT_B
++#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
++#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
++#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
++#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
++//FMT2_FMT_DYNAMIC_EXP_CNTL
++#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
++#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
++#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
++#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
++//FMT2_FMT_CONTROL
++#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
++#define FMT2_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT                                                       0x4
++#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
++#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
++#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
++#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
++#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
++#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
++#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
++#define FMT2_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT                                                               0x1c
++#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
++#define FMT2_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK                                                         0x00000010L
++#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
++#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
++#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
++#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
++#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
++#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
++#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
++#define FMT2_FMT_CONTROL__FMT_PTI_ENABLE_MASK                                                                 0x10000000L
++//FMT2_FMT_BIT_DEPTH_CONTROL
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
++#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
++//FMT2_FMT_DITHER_RAND_R_SEED
++#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
++#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
++#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
++#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
++//FMT2_FMT_DITHER_RAND_G_SEED
++#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
++#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
++#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
++#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
++//FMT2_FMT_DITHER_RAND_B_SEED
++#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
++#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
++#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
++#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
++//FMT2_FMT_CLAMP_CNTL
++#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
++#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
++#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
++#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
++//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL
++#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
++#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
++//FMT2_FMT_MAP420_MEMORY_CONTROL
++#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
++#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
++#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
++#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
++#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
++#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
++#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
++#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
++//FMT2_FMT_422_CONTROL
++#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
++#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
++
++
++// addressBlock: dce_dc_opp_dpg2_dispdec
++//DPG2_DPG_CONTROL
++#define DPG2_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
++#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
++#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
++#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
++#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
++#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
++#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
++#define DPG2_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
++#define DPG2_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
++#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
++#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
++#define DPG2_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
++#define DPG2_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
++#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
++//DPG2_DPG_RAMP_CONTROL
++#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
++#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
++#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
++#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
++#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
++#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
++//DPG2_DPG_DIMENSIONS
++#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
++#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
++#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
++#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
++//DPG2_DPG_COLOUR_R_CR
++#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
++#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
++#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
++#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
++//DPG2_DPG_COLOUR_G_Y
++#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
++#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
++#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
++#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
++//DPG2_DPG_COLOUR_B_CB
++#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
++#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
++#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
++#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
++//DPG2_DPG_OFFSET_SEGMENT
++#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
++#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
++#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
++#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
++//DPG2_DPG_STATUS
++#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
++#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
++
++
++// addressBlock: dce_dc_opp_oppbuf2_dispdec
++//OPPBUF2_OPPBUF_CONTROL
++#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
++#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
++#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
++#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
++#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
++#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
++#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
++#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
++#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
++#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
++//OPPBUF2_OPPBUF_3D_PARAMETERS_0
++#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
++#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
++#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
++#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
++#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
++#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
++//OPPBUF2_OPPBUF_3D_PARAMETERS_1
++#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
++#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
++#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
++#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
++//OPPBUF2_OPPBUF_CONTROL1
++#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
++#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
++
++
++// addressBlock: dce_dc_opp_opp_pipe2_dispdec
++//OPP_PIPE2_OPP_PIPE_CONTROL
++#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
++#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
++#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
++#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
++#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
++#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
++
++
++// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
++//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
++//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
++//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
++//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
++//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
++#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
++
++
++// addressBlock: dce_dc_opp_fmt3_dispdec
++//FMT3_FMT_CLAMP_COMPONENT_R
++#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
++#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
++#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
++#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
++//FMT3_FMT_CLAMP_COMPONENT_G
++#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
++#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
++#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
++#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
++//FMT3_FMT_CLAMP_COMPONENT_B
++#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
++#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
++#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
++#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
++//FMT3_FMT_DYNAMIC_EXP_CNTL
++#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
++#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
++#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
++#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
++//FMT3_FMT_CONTROL
++#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
++#define FMT3_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT                                                       0x4
++#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
++#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
++#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
++#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
++#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
++#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
++#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
++#define FMT3_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT                                                               0x1c
++#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
++#define FMT3_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK                                                         0x00000010L
++#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
++#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
++#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
++#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
++#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
++#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
++#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
++#define FMT3_FMT_CONTROL__FMT_PTI_ENABLE_MASK                                                                 0x10000000L
++//FMT3_FMT_BIT_DEPTH_CONTROL
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
++#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
++//FMT3_FMT_DITHER_RAND_R_SEED
++#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
++#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
++#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
++#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
++//FMT3_FMT_DITHER_RAND_G_SEED
++#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
++#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
++#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
++#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
++//FMT3_FMT_DITHER_RAND_B_SEED
++#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
++#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
++#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
++#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
++//FMT3_FMT_CLAMP_CNTL
++#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
++#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
++#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
++#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
++//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL
++#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
++#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
++//FMT3_FMT_MAP420_MEMORY_CONTROL
++#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
++#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
++#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
++#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
++#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
++#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
++#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
++#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
++//FMT3_FMT_422_CONTROL
++#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
++#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
++
++
++// addressBlock: dce_dc_opp_dpg3_dispdec
++//DPG3_DPG_CONTROL
++#define DPG3_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
++#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
++#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
++#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
++#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
++#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
++#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
++#define DPG3_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
++#define DPG3_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
++#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
++#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
++#define DPG3_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
++#define DPG3_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
++#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
++//DPG3_DPG_RAMP_CONTROL
++#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
++#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
++#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
++#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
++#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
++#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
++//DPG3_DPG_DIMENSIONS
++#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
++#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
++#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
++#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
++//DPG3_DPG_COLOUR_R_CR
++#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
++#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
++#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
++#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
++//DPG3_DPG_COLOUR_G_Y
++#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
++#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
++#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
++#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
++//DPG3_DPG_COLOUR_B_CB
++#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
++#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
++#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
++#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
++//DPG3_DPG_OFFSET_SEGMENT
++#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
++#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
++#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
++#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
++//DPG3_DPG_STATUS
++#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
++#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
++
++
++// addressBlock: dce_dc_opp_oppbuf3_dispdec
++//OPPBUF3_OPPBUF_CONTROL
++#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
++#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
++#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
++#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
++#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
++#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
++#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
++#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
++#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
++#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
++//OPPBUF3_OPPBUF_3D_PARAMETERS_0
++#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
++#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
++#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
++#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
++#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
++#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
++//OPPBUF3_OPPBUF_3D_PARAMETERS_1
++#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
++#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
++#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
++#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
++//OPPBUF3_OPPBUF_CONTROL1
++#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
++#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
++
++
++// addressBlock: dce_dc_opp_opp_pipe3_dispdec
++//OPP_PIPE3_OPP_PIPE_CONTROL
++#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
++#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
++#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
++#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
++#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
++#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
++
++
++// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
++//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
++//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
++//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
++//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
++//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
++#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
++
++
++// addressBlock: dce_dc_opp_fmt4_dispdec
++//FMT4_FMT_CLAMP_COMPONENT_R
++#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
++#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
++#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
++#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
++//FMT4_FMT_CLAMP_COMPONENT_G
++#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
++#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
++#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
++#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
++//FMT4_FMT_CLAMP_COMPONENT_B
++#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
++#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
++#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
++#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
++//FMT4_FMT_DYNAMIC_EXP_CNTL
++#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
++#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
++#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
++#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
++//FMT4_FMT_CONTROL
++#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
++#define FMT4_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT                                                       0x4
++#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
++#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
++#define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
++#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
++#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
++#define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
++#define FMT4_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
++#define FMT4_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT                                                               0x1c
++#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
++#define FMT4_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK                                                         0x00000010L
++#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
++#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
++#define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
++#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
++#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
++#define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
++#define FMT4_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
++#define FMT4_FMT_CONTROL__FMT_PTI_ENABLE_MASK                                                                 0x10000000L
++//FMT4_FMT_BIT_DEPTH_CONTROL
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
++#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
++//FMT4_FMT_DITHER_RAND_R_SEED
++#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
++#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
++#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
++#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
++//FMT4_FMT_DITHER_RAND_G_SEED
++#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
++#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
++#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
++#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
++//FMT4_FMT_DITHER_RAND_B_SEED
++#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
++#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
++#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
++#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
++//FMT4_FMT_CLAMP_CNTL
++#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
++#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
++#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
++#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
++//FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL
++#define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
++#define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
++//FMT4_FMT_MAP420_MEMORY_CONTROL
++#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
++#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
++#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
++#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
++#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
++#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
++#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
++#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
++//FMT4_FMT_422_CONTROL
++#define FMT4_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
++#define FMT4_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
++
++
++// addressBlock: dce_dc_opp_dpg4_dispdec
++//DPG4_DPG_CONTROL
++#define DPG4_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
++#define DPG4_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
++#define DPG4_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
++#define DPG4_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
++#define DPG4_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
++#define DPG4_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
++#define DPG4_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
++#define DPG4_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
++#define DPG4_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
++#define DPG4_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
++#define DPG4_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
++#define DPG4_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
++#define DPG4_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
++#define DPG4_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
++//DPG4_DPG_RAMP_CONTROL
++#define DPG4_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
++#define DPG4_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
++#define DPG4_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
++#define DPG4_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
++#define DPG4_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
++#define DPG4_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
++//DPG4_DPG_DIMENSIONS
++#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
++#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
++#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
++#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
++//DPG4_DPG_COLOUR_R_CR
++#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
++#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
++#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
++#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
++//DPG4_DPG_COLOUR_G_Y
++#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
++#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
++#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
++#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
++//DPG4_DPG_COLOUR_B_CB
++#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
++#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
++#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
++#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
++//DPG4_DPG_OFFSET_SEGMENT
++#define DPG4_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
++#define DPG4_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
++#define DPG4_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
++#define DPG4_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
++//DPG4_DPG_STATUS
++#define DPG4_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
++#define DPG4_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
++
++
++// addressBlock: dce_dc_opp_oppbuf4_dispdec
++//OPPBUF4_OPPBUF_CONTROL
++#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
++#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
++#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
++#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
++#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
++#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
++#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
++#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
++#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
++#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
++//OPPBUF4_OPPBUF_3D_PARAMETERS_0
++#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
++#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
++#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
++#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
++#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
++#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
++//OPPBUF4_OPPBUF_3D_PARAMETERS_1
++#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
++#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
++#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
++#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
++//OPPBUF4_OPPBUF_CONTROL1
++#define OPPBUF4_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
++#define OPPBUF4_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
++
++
++// addressBlock: dce_dc_opp_opp_pipe4_dispdec
++//OPP_PIPE4_OPP_PIPE_CONTROL
++#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
++#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
++#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
++#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
++#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
++#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
++
++
++// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec
++//OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
++//OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
++//OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
++//OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
++//OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
++#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
++
++
++// addressBlock: dce_dc_opp_fmt5_dispdec
++//FMT5_FMT_CLAMP_COMPONENT_R
++#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
++#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
++#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
++#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
++//FMT5_FMT_CLAMP_COMPONENT_G
++#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
++#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
++#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
++#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
++//FMT5_FMT_CLAMP_COMPONENT_B
++#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
++#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
++#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
++#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
++//FMT5_FMT_DYNAMIC_EXP_CNTL
++#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
++#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
++#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
++#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
++//FMT5_FMT_CONTROL
++#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
++#define FMT5_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT                                                       0x4
++#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
++#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
++#define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
++#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
++#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
++#define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
++#define FMT5_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
++#define FMT5_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT                                                               0x1c
++#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
++#define FMT5_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK                                                         0x00000010L
++#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
++#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
++#define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
++#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
++#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
++#define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
++#define FMT5_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
++#define FMT5_FMT_CONTROL__FMT_PTI_ENABLE_MASK                                                                 0x10000000L
++//FMT5_FMT_BIT_DEPTH_CONTROL
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
++#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
++//FMT5_FMT_DITHER_RAND_R_SEED
++#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
++#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
++#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
++#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
++//FMT5_FMT_DITHER_RAND_G_SEED
++#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
++#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
++#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
++#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
++//FMT5_FMT_DITHER_RAND_B_SEED
++#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
++#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
++#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
++#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
++//FMT5_FMT_CLAMP_CNTL
++#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
++#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
++#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
++#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
++//FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL
++#define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
++#define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
++//FMT5_FMT_MAP420_MEMORY_CONTROL
++#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
++#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
++#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
++#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
++#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
++#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
++#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
++#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
++//FMT5_FMT_422_CONTROL
++#define FMT5_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
++#define FMT5_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
++
++
++// addressBlock: dce_dc_opp_dpg5_dispdec
++//DPG5_DPG_CONTROL
++#define DPG5_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
++#define DPG5_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
++#define DPG5_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
++#define DPG5_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
++#define DPG5_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
++#define DPG5_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
++#define DPG5_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
++#define DPG5_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
++#define DPG5_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
++#define DPG5_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
++#define DPG5_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
++#define DPG5_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
++#define DPG5_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
++#define DPG5_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
++//DPG5_DPG_RAMP_CONTROL
++#define DPG5_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
++#define DPG5_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
++#define DPG5_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
++#define DPG5_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
++#define DPG5_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
++#define DPG5_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
++//DPG5_DPG_DIMENSIONS
++#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
++#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
++#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
++#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
++//DPG5_DPG_COLOUR_R_CR
++#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
++#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
++#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
++#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
++//DPG5_DPG_COLOUR_G_Y
++#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
++#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
++#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
++#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
++//DPG5_DPG_COLOUR_B_CB
++#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
++#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
++#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
++#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
++//DPG5_DPG_OFFSET_SEGMENT
++#define DPG5_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
++#define DPG5_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
++#define DPG5_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
++#define DPG5_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
++//DPG5_DPG_STATUS
++#define DPG5_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
++#define DPG5_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
++
++
++// addressBlock: dce_dc_opp_oppbuf5_dispdec
++//OPPBUF5_OPPBUF_CONTROL
++#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
++#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
++#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
++#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
++#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
++#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
++#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
++#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
++#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
++#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
++//OPPBUF5_OPPBUF_3D_PARAMETERS_0
++#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
++#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
++#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
++#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
++#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
++#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
++//OPPBUF5_OPPBUF_3D_PARAMETERS_1
++#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
++#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
++#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
++#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
++//OPPBUF5_OPPBUF_CONTROL1
++#define OPPBUF5_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
++#define OPPBUF5_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
++
++
++// addressBlock: dce_dc_opp_opp_pipe5_dispdec
++//OPP_PIPE5_OPP_PIPE_CONTROL
++#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
++#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
++#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
++#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
++#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
++#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
++
++
++// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec
++//OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
++//OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
++//OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
++//OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
++//OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
++#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
++
++
++// addressBlock: dce_dc_opp_opp_top_dispdec
++//OPP_TOP_CLK_CONTROL
++#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0
++#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT                                                0x4
++#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT                                                          0x8
++#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT                                                         0xc
++#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT                                                         0xd
++#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L
++#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK                                                  0x00000010L
++#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK                                                            0x00000F00L
++#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK                                                           0x00001000L
++#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK                                                           0x00002000L
++
++
++// addressBlock: dce_dc_opp_dscrm0_dispdec
++//DSCRM0_DSCRM_DSC_FORWARD_CONFIG
++#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
++#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
++#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
++#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
++#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
++#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
++#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
++#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
++
++
++// addressBlock: dce_dc_opp_dscrm1_dispdec
++//DSCRM1_DSCRM_DSC_FORWARD_CONFIG
++#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
++#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
++#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
++#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
++#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
++#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
++#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
++#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
++
++
++// addressBlock: dce_dc_opp_dscrm2_dispdec
++//DSCRM2_DSCRM_DSC_FORWARD_CONFIG
++#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
++#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
++#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
++#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
++#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
++#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
++#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
++#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
++
++
++// addressBlock: dce_dc_opp_dscrm3_dispdec
++//DSCRM3_DSCRM_DSC_FORWARD_CONFIG
++#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
++#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
++#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
++#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
++#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
++#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
++#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
++#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
++
++
++// addressBlock: dce_dc_opp_dscrm4_dispdec
++//DSCRM4_DSCRM_DSC_FORWARD_CONFIG
++#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
++#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
++#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
++#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
++#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
++#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
++#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
++#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
++
++
++// addressBlock: dce_dc_opp_dscrm5_dispdec
++//DSCRM5_DSCRM_DSC_FORWARD_CONFIG
++#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
++#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
++#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
++#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
++#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
++#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
++#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
++#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
++
++
++// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON16_PERFCOUNTER_CNTL
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
++#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
++//DC_PERFMON16_PERFCOUNTER_CNTL2
++#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
++#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
++#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
++#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
++#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
++#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
++#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
++#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
++#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
++#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
++//DC_PERFMON16_PERFCOUNTER_STATE
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
++#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
++//DC_PERFMON16_PERFMON_CNTL
++#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
++#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
++#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
++#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
++#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
++#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
++#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
++#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
++#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
++#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
++#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
++#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
++//DC_PERFMON16_PERFMON_CNTL2
++#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
++#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
++#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
++#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
++#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
++#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
++#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
++#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
++//DC_PERFMON16_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
++#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
++//DC_PERFMON16_PERFMON_CVALUE_LOW
++#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
++#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
++//DC_PERFMON16_PERFMON_HI
++#define DC_PERFMON16_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
++#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
++#define DC_PERFMON16_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
++#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
++//DC_PERFMON16_PERFMON_LOW
++#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
++#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_optc_odm0_dispdec
++//ODM0_OPTC_INPUT_GLOBAL_CONTROL
++#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
++#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
++#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
++#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
++#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
++#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
++#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
++#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
++#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
++#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
++#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
++#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
++#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
++#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
++#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
++#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
++//ODM0_OPTC_DATA_SOURCE_SELECT
++#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
++#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x2
++#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x8
++#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0xc
++#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000001L
++#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x0000000CL
++#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x00000F00L
++#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x0000F000L
++//ODM0_OPTC_DATA_FORMAT_CONTROL
++#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
++#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
++#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
++#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
++//ODM0_OPTC_BYTES_PER_PIXEL
++#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
++#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
++//ODM0_OPTC_WIDTH_CONTROL
++#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
++#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
++#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
++#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
++//ODM0_OPTC_INPUT_CLOCK_CONTROL
++#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
++#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
++#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
++#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
++#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
++#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
++//ODM0_OPTC_MEMORY_CONFIG
++#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
++#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
++//ODM0_OPTC_INPUT_SPARE_REGISTER
++#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
++#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_optc_odm1_dispdec
++//ODM1_OPTC_INPUT_GLOBAL_CONTROL
++#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
++#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
++#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
++#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
++#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
++#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
++#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
++#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
++#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
++#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
++#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
++#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
++#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
++#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
++#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
++#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
++//ODM1_OPTC_DATA_SOURCE_SELECT
++#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
++#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x2
++#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x8
++#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0xc
++#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000001L
++#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x0000000CL
++#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x00000F00L
++#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x0000F000L
++//ODM1_OPTC_DATA_FORMAT_CONTROL
++#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
++#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
++#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
++#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
++//ODM1_OPTC_BYTES_PER_PIXEL
++#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
++#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
++//ODM1_OPTC_WIDTH_CONTROL
++#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
++#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
++#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
++#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
++//ODM1_OPTC_INPUT_CLOCK_CONTROL
++#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
++#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
++#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
++#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
++#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
++#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
++//ODM1_OPTC_MEMORY_CONFIG
++#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
++#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
++//ODM1_OPTC_INPUT_SPARE_REGISTER
++#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
++#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_optc_odm2_dispdec
++//ODM2_OPTC_INPUT_GLOBAL_CONTROL
++#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
++#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
++#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
++#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
++#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
++#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
++#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
++#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
++#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
++#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
++#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
++#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
++#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
++#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
++#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
++#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
++//ODM2_OPTC_DATA_SOURCE_SELECT
++#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
++#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x2
++#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x8
++#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0xc
++#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000001L
++#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x0000000CL
++#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x00000F00L
++#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x0000F000L
++//ODM2_OPTC_DATA_FORMAT_CONTROL
++#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
++#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
++#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
++#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
++//ODM2_OPTC_BYTES_PER_PIXEL
++#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
++#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
++//ODM2_OPTC_WIDTH_CONTROL
++#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
++#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
++#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
++#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
++//ODM2_OPTC_INPUT_CLOCK_CONTROL
++#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
++#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
++#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
++#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
++#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
++#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
++//ODM2_OPTC_MEMORY_CONFIG
++#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
++#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
++//ODM2_OPTC_INPUT_SPARE_REGISTER
++#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
++#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_optc_odm3_dispdec
++//ODM3_OPTC_INPUT_GLOBAL_CONTROL
++#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
++#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
++#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
++#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
++#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
++#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
++#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
++#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
++#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
++#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
++#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
++#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
++#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
++#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
++#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
++#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
++//ODM3_OPTC_DATA_SOURCE_SELECT
++#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
++#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x2
++#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x8
++#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0xc
++#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000001L
++#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x0000000CL
++#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x00000F00L
++#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x0000F000L
++//ODM3_OPTC_DATA_FORMAT_CONTROL
++#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
++#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
++#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
++#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
++//ODM3_OPTC_BYTES_PER_PIXEL
++#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
++#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
++//ODM3_OPTC_WIDTH_CONTROL
++#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
++#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
++#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
++#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
++//ODM3_OPTC_INPUT_CLOCK_CONTROL
++#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
++#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
++#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
++#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
++#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
++#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
++//ODM3_OPTC_MEMORY_CONFIG
++#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
++#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
++//ODM3_OPTC_INPUT_SPARE_REGISTER
++#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
++#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_optc_odm4_dispdec
++//ODM4_OPTC_INPUT_GLOBAL_CONTROL
++#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
++#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
++#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
++#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
++#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
++#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
++#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
++#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
++#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
++#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
++#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
++#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
++#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
++#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
++#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
++#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
++//ODM4_OPTC_DATA_SOURCE_SELECT
++#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
++#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x2
++#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x8
++#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0xc
++#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000001L
++#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x0000000CL
++#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x00000F00L
++#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x0000F000L
++//ODM4_OPTC_DATA_FORMAT_CONTROL
++#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
++#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
++#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
++#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
++//ODM4_OPTC_BYTES_PER_PIXEL
++#define ODM4_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
++#define ODM4_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
++//ODM4_OPTC_WIDTH_CONTROL
++#define ODM4_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
++#define ODM4_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
++#define ODM4_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
++#define ODM4_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
++//ODM4_OPTC_INPUT_CLOCK_CONTROL
++#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
++#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
++#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
++#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
++#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
++#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
++//ODM4_OPTC_MEMORY_CONFIG
++#define ODM4_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
++#define ODM4_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
++//ODM4_OPTC_INPUT_SPARE_REGISTER
++#define ODM4_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
++#define ODM4_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_optc_odm5_dispdec
++//ODM5_OPTC_INPUT_GLOBAL_CONTROL
++#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
++#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
++#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
++#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
++#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
++#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
++#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
++#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
++#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
++#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
++#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
++#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
++#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
++#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
++#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
++#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
++//ODM5_OPTC_DATA_SOURCE_SELECT
++#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
++#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x2
++#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x8
++#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0xc
++#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000001L
++#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x0000000CL
++#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x00000F00L
++#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x0000F000L
++//ODM5_OPTC_DATA_FORMAT_CONTROL
++#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
++#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
++#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
++#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
++//ODM5_OPTC_BYTES_PER_PIXEL
++#define ODM5_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
++#define ODM5_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
++//ODM5_OPTC_WIDTH_CONTROL
++#define ODM5_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
++#define ODM5_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
++#define ODM5_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
++#define ODM5_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
++//ODM5_OPTC_INPUT_CLOCK_CONTROL
++#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
++#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
++#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
++#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
++#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
++#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
++//ODM5_OPTC_MEMORY_CONFIG
++#define ODM5_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
++#define ODM5_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
++//ODM5_OPTC_INPUT_SPARE_REGISTER
++#define ODM5_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
++#define ODM5_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_optc_otg0_dispdec
++//OTG0_OTG_H_TOTAL
++#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
++#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
++//OTG0_OTG_H_BLANK_START_END
++#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
++#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
++#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
++#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
++//OTG0_OTG_H_SYNC_A
++#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
++#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
++#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
++#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
++//OTG0_OTG_H_SYNC_A_CNTL
++#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
++#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
++#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
++#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
++#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
++#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
++//OTG0_OTG_H_TIMING_CNTL
++#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT                                                   0x0
++#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT                                       0x8
++#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK                                                     0x00000001L
++#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK                                         0x00000100L
++//OTG0_OTG_V_TOTAL
++#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
++#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
++//OTG0_OTG_V_TOTAL_MIN
++#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
++#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
++//OTG0_OTG_V_TOTAL_MAX
++#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
++#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
++//OTG0_OTG_V_TOTAL_MID
++#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
++#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
++//OTG0_OTG_V_TOTAL_CONTROL
++#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
++#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
++#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
++#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
++#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
++#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
++#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT                                          0x7
++#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
++#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
++#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
++#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
++#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
++#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
++#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
++#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
++#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK                                            0x00000080L
++#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
++#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
++//OTG0_OTG_V_TOTAL_INT_STATUS
++#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
++#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
++#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
++#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
++#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
++#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
++#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
++#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
++//OTG0_OTG_VSYNC_NOM_INT_STATUS
++#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
++#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
++#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
++#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
++//OTG0_OTG_V_BLANK_START_END
++#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
++#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
++#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
++#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
++//OTG0_OTG_V_SYNC_A
++#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
++#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
++#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
++#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
++//OTG0_OTG_V_SYNC_A_CNTL
++#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
++#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
++//OTG0_OTG_TRIGA_CNTL
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
++#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
++//OTG0_OTG_TRIGA_MANUAL_TRIG
++#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
++#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
++//OTG0_OTG_TRIGB_CNTL
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
++#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
++//OTG0_OTG_TRIGB_MANUAL_TRIG
++#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
++#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
++//OTG0_OTG_FORCE_COUNT_NOW_CNTL
++#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
++#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
++#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
++#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
++#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
++#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
++#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
++#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
++#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
++#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
++//OTG0_OTG_FLOW_CONTROL
++#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
++#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
++#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
++#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
++#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
++#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
++#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
++#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
++//OTG0_OTG_STEREO_FORCE_NEXT_EYE
++#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
++#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT                                       0x8
++#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT                                        0x10
++#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
++#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK                                         0x0000FF00L
++#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK                                          0x1FFF0000L
++//OTG0_OTG_CONTROL
++#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
++#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
++#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
++#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
++#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
++#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
++#define OTG0_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT                                                0x18
++#define OTG0_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT                                                     0x1e
++#define OTG0_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT                                                0x1f
++#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
++#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
++#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
++#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
++#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
++#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
++#define OTG0_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK                                                  0x01000000L
++#define OTG0_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK                                                       0x40000000L
++#define OTG0_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK                                                  0x80000000L
++//OTG0_OTG_BLANK_CONTROL
++#define OTG0_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT                                                0x0
++#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT                                                      0x8
++#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT                                                      0x10
++#define OTG0_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK                                                  0x00000001L
++#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK                                                        0x00000100L
++#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK                                                        0x00010000L
++//OTG0_OTG_PIPE_ABORT_CONTROL
++#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT                                                    0x0
++#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT                                               0x8
++#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK                                                      0x00000001L
++#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK                                                 0x00000100L
++//OTG0_OTG_INTERLACE_CONTROL
++#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
++#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
++#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
++#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
++//OTG0_OTG_INTERLACE_STATUS
++#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
++#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
++#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
++#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
++//OTG0_OTG_PIXEL_DATA_READBACK0
++#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
++#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
++#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
++#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
++//OTG0_OTG_PIXEL_DATA_READBACK1
++#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
++#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
++//OTG0_OTG_STATUS
++#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
++#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
++#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
++#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
++#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
++#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
++#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
++#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
++#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
++#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
++#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
++#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
++#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
++#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
++#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
++#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
++//OTG0_OTG_STATUS_POSITION
++#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
++#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
++#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
++#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
++//OTG0_OTG_NOM_VERT_POSITION
++#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
++#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
++//OTG0_OTG_STATUS_FRAME_COUNT
++#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
++#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
++//OTG0_OTG_STATUS_VF_COUNT
++#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
++#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
++//OTG0_OTG_STATUS_HV_COUNT
++#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
++#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
++//OTG0_OTG_COUNT_CONTROL
++#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
++#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
++#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
++#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
++//OTG0_OTG_COUNT_RESET
++#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
++#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
++//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
++#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
++#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
++//OTG0_OTG_VERT_SYNC_CONTROL
++#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
++#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
++#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
++#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
++#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
++#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
++//OTG0_OTG_STEREO_STATUS
++#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
++#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
++#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
++#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
++#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
++#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
++#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
++#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
++#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
++#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
++#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
++#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
++#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
++#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
++//OTG0_OTG_STEREO_CONTROL
++#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
++#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
++#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
++#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
++#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
++#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
++#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
++#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
++#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
++#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
++#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
++#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
++#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
++#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
++#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
++#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
++//OTG0_OTG_SNAPSHOT_STATUS
++#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
++#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
++#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
++#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
++#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
++#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
++//OTG0_OTG_SNAPSHOT_CONTROL
++#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
++#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
++//OTG0_OTG_SNAPSHOT_POSITION
++#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
++#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
++#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
++#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
++//OTG0_OTG_SNAPSHOT_FRAME
++#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
++#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
++//OTG0_OTG_INTERRUPT_CONTROL
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
++#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
++//OTG0_OTG_UPDATE_LOCK
++#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
++#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
++//OTG0_OTG_DOUBLE_BUFFER_CONTROL
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT                         0x2
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT                               0x3
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT                           0x4
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT                                0x10
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT                              0x18
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK                           0x00000004L
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK                                 0x00000008L
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK                             0x00000010L
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK                                  0x00010000L
++#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK                                0x03000000L
++//OTG0_OTG_MASTER_EN
++#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
++#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
++//OTG0_OTG_BLANK_DATA_COLOR
++#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT                                        0x0
++#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT                                        0xa
++#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT                                         0x14
++#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK                                          0x000003FFL
++#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK                                          0x000FFC00L
++#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK                                           0x3FF00000L
++//OTG0_OTG_BLANK_DATA_COLOR_EXT
++#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT                                0x0
++#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT                                0x8
++#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT                                 0x10
++#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK                                  0x0000003FL
++#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK                                  0x00003F00L
++#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK                                   0x003F0000L
++//OTG0_OTG_BLACK_COLOR
++#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT                                                     0x0
++#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT                                                      0xa
++#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT                                                     0x14
++#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK                                                       0x000003FFL
++#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK                                                        0x000FFC00L
++#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK                                                       0x3FF00000L
++//OTG0_OTG_BLACK_COLOR_EXT
++#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT                                             0x0
++#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT                                              0x8
++#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT                                             0x10
++#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK                                               0x0000003FL
++#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK                                                0x00003F00L
++#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK                                               0x003F0000L
++//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION
++#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
++#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
++#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
++#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
++//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL
++#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
++#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
++#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
++#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
++#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
++#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
++#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
++#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
++#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
++#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
++#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
++#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
++//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION
++#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
++#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
++//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL
++#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
++#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
++#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
++#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
++#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
++#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
++#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
++#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
++#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
++#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
++//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION
++#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
++#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
++//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL
++#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
++#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
++#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
++#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
++#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
++#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
++#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
++#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
++#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
++#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
++//OTG0_OTG_CRC_CNTL
++#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
++#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
++#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
++#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
++#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
++#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
++#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
++#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
++#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
++#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
++#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
++#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
++#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
++#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
++#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
++#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
++#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
++#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
++#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
++#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
++#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
++#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
++#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
++#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
++#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
++#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
++#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
++#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
++#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
++#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
++//OTG0_OTG_CRC_CNTL2
++#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
++#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
++#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
++#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
++#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
++#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
++#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
++#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
++//OTG0_OTG_CRC0_WINDOWA_X_CONTROL
++#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
++#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
++#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
++#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
++//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL
++#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
++#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
++#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
++#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
++//OTG0_OTG_CRC0_WINDOWB_X_CONTROL
++#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
++#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
++#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
++#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
++//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL
++#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
++#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
++#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
++#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
++//OTG0_OTG_CRC0_DATA_RG
++#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
++#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
++#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
++//OTG0_OTG_CRC0_DATA_B
++#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
++#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
++#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
++//OTG0_OTG_CRC1_WINDOWA_X_CONTROL
++#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
++#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
++#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
++#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
++//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL
++#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
++#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
++#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
++#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
++//OTG0_OTG_CRC1_WINDOWB_X_CONTROL
++#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
++#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
++#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
++#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
++//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL
++#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
++#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
++#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
++#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
++//OTG0_OTG_CRC1_DATA_RG
++#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
++#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
++#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
++//OTG0_OTG_CRC1_DATA_B
++#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
++#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
++#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
++//OTG0_OTG_CRC2_DATA_RG
++#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
++#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
++#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
++//OTG0_OTG_CRC2_DATA_B
++#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
++#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
++#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
++//OTG0_OTG_CRC3_DATA_RG
++#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
++#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
++#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
++//OTG0_OTG_CRC3_DATA_B
++#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
++#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
++#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
++//OTG0_OTG_CRC_SIG_RED_GREEN_MASK
++#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
++#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
++#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
++#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
++//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK
++#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
++#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
++#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
++#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
++//OTG0_OTG_STATIC_SCREEN_CONTROL
++#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
++#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
++#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
++#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
++#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
++#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
++#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
++#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
++#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
++#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
++#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
++#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
++#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
++#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
++#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
++#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
++#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
++#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
++//OTG0_OTG_3D_STRUCTURE_CONTROL
++#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
++#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
++#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
++#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
++#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
++#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
++#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
++#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
++#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
++#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
++#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
++#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
++//OTG0_OTG_GSL_VSYNC_GAP
++#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
++#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
++#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
++#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
++#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
++#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
++#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
++#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
++#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
++#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
++#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
++#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
++#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
++#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
++#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
++#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
++//OTG0_OTG_MASTER_UPDATE_MODE
++#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
++#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
++//OTG0_OTG_CLOCK_CONTROL
++#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
++#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
++#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
++#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
++#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
++#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
++#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
++#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
++#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
++#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
++//OTG0_OTG_VSTARTUP_PARAM
++#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
++#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
++//OTG0_OTG_VUPDATE_PARAM
++#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
++#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
++#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
++#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
++//OTG0_OTG_VREADY_PARAM
++#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
++#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
++//OTG0_OTG_GLOBAL_SYNC_STATUS
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
++#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
++//OTG0_OTG_MASTER_UPDATE_LOCK
++#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
++#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
++#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
++#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
++//OTG0_OTG_GSL_CONTROL
++#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
++#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
++#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
++#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
++#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
++#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
++#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
++#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
++#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
++#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
++#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
++#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
++#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
++#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
++#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
++#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
++#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
++#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
++//OTG0_OTG_GSL_WINDOW_X
++#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
++#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
++#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
++#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
++//OTG0_OTG_GSL_WINDOW_Y
++#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
++#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
++#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
++#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
++//OTG0_OTG_VUPDATE_KEEPOUT
++#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
++#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
++#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
++#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
++#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
++#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
++//OTG0_OTG_GLOBAL_CONTROL0
++#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT                                0x0
++#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT                             0x8
++#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
++#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK                                  0x000000FFL
++#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK                               0x00000100L
++#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
++//OTG0_OTG_GLOBAL_CONTROL1
++#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT                                              0x0
++#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT                                              0x10
++#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
++#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK                                                0x00007FFFL
++#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK                                                0x7FFF0000L
++#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
++//OTG0_OTG_GLOBAL_CONTROL2
++#define OTG0_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT                                                  0x0
++#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
++#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
++#define OTG0_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT                                        0x1d
++#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
++#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
++#define OTG0_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK                                                    0x000003FFL
++#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
++#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
++#define OTG0_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK                                          0x20000000L
++#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
++#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
++//OTG0_OTG_GLOBAL_CONTROL3
++#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
++#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
++#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT                          0x8
++#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
++#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
++#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK                            0x00000100L
++//OTG0_OTG_TRIG_MANUAL_CONTROL
++#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
++#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
++//OTG0_OTG_MANUAL_FLOW_CONTROL
++#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
++#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
++//OTG0_OTG_RANGE_TIMING_INT_STATUS
++#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                             0x0
++#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT                         0x4
++#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                       0x8
++#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                     0xc
++#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                    0x10
++#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK                               0x00000001L
++#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK                           0x00000010L
++#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK                         0x00000100L
++#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                       0x00001000L
++#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                      0x00010000L
++//OTG0_OTG_DRR_CONTROL
++#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
++#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
++#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000007L
++#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
++//OTG0_OTG_REQUEST_CONTROL
++#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
++#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
++//OTG0_OTG_DSC_START_POSITION
++#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
++#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
++#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
++#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
++//OTG0_OTG_PIPE_UPDATE_STATUS
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT                                                    0x1
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT                                              0x2
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT                                           0x5
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT                                     0x6
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT                                           0x9
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT                                     0xa
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK                                                      0x00000002L
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK                                                0x00000004L
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK                                             0x00000020L
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK                                       0x00000040L
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK                                             0x00000200L
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK                                       0x00000400L
++#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
++//OTG0_OTG_SPARE_REGISTER
++#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
++#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_optc_otg1_dispdec
++//OTG1_OTG_H_TOTAL
++#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
++#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
++//OTG1_OTG_H_BLANK_START_END
++#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
++#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
++#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
++#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
++//OTG1_OTG_H_SYNC_A
++#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
++#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
++#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
++#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
++//OTG1_OTG_H_SYNC_A_CNTL
++#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
++#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
++#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
++#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
++#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
++#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
++//OTG1_OTG_H_TIMING_CNTL
++#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT                                                   0x0
++#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT                                       0x8
++#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK                                                     0x00000001L
++#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK                                         0x00000100L
++//OTG1_OTG_V_TOTAL
++#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
++#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
++//OTG1_OTG_V_TOTAL_MIN
++#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
++#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
++//OTG1_OTG_V_TOTAL_MAX
++#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
++#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
++//OTG1_OTG_V_TOTAL_MID
++#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
++#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
++//OTG1_OTG_V_TOTAL_CONTROL
++#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
++#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
++#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
++#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
++#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
++#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
++#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT                                          0x7
++#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
++#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
++#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
++#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
++#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
++#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
++#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
++#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
++#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK                                            0x00000080L
++#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
++#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
++//OTG1_OTG_V_TOTAL_INT_STATUS
++#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
++#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
++#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
++#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
++#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
++#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
++#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
++#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
++//OTG1_OTG_VSYNC_NOM_INT_STATUS
++#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
++#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
++#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
++#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
++//OTG1_OTG_V_BLANK_START_END
++#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
++#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
++#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
++#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
++//OTG1_OTG_V_SYNC_A
++#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
++#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
++#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
++#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
++//OTG1_OTG_V_SYNC_A_CNTL
++#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
++#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
++//OTG1_OTG_TRIGA_CNTL
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
++#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
++//OTG1_OTG_TRIGA_MANUAL_TRIG
++#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
++#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
++//OTG1_OTG_TRIGB_CNTL
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
++#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
++//OTG1_OTG_TRIGB_MANUAL_TRIG
++#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
++#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
++//OTG1_OTG_FORCE_COUNT_NOW_CNTL
++#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
++#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
++#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
++#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
++#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
++#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
++#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
++#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
++#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
++#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
++//OTG1_OTG_FLOW_CONTROL
++#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
++#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
++#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
++#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
++#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
++#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
++#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
++#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
++//OTG1_OTG_STEREO_FORCE_NEXT_EYE
++#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
++#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT                                       0x8
++#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT                                        0x10
++#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
++#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK                                         0x0000FF00L
++#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK                                          0x1FFF0000L
++//OTG1_OTG_CONTROL
++#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
++#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
++#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
++#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
++#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
++#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
++#define OTG1_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT                                                0x18
++#define OTG1_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT                                                     0x1e
++#define OTG1_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT                                                0x1f
++#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
++#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
++#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
++#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
++#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
++#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
++#define OTG1_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK                                                  0x01000000L
++#define OTG1_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK                                                       0x40000000L
++#define OTG1_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK                                                  0x80000000L
++//OTG1_OTG_BLANK_CONTROL
++#define OTG1_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT                                                0x0
++#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT                                                      0x8
++#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT                                                      0x10
++#define OTG1_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK                                                  0x00000001L
++#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK                                                        0x00000100L
++#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK                                                        0x00010000L
++//OTG1_OTG_PIPE_ABORT_CONTROL
++#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT                                                    0x0
++#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT                                               0x8
++#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK                                                      0x00000001L
++#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK                                                 0x00000100L
++//OTG1_OTG_INTERLACE_CONTROL
++#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
++#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
++#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
++#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
++//OTG1_OTG_INTERLACE_STATUS
++#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
++#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
++#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
++#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
++//OTG1_OTG_PIXEL_DATA_READBACK0
++#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
++#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
++#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
++#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
++//OTG1_OTG_PIXEL_DATA_READBACK1
++#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
++#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
++//OTG1_OTG_STATUS
++#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
++#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
++#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
++#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
++#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
++#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
++#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
++#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
++#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
++#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
++#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
++#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
++#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
++#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
++#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
++#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
++//OTG1_OTG_STATUS_POSITION
++#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
++#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
++#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
++#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
++//OTG1_OTG_NOM_VERT_POSITION
++#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
++#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
++//OTG1_OTG_STATUS_FRAME_COUNT
++#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
++#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
++//OTG1_OTG_STATUS_VF_COUNT
++#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
++#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
++//OTG1_OTG_STATUS_HV_COUNT
++#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
++#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
++//OTG1_OTG_COUNT_CONTROL
++#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
++#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
++#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
++#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
++//OTG1_OTG_COUNT_RESET
++#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
++#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
++//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
++#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
++#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
++//OTG1_OTG_VERT_SYNC_CONTROL
++#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
++#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
++#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
++#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
++#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
++#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
++//OTG1_OTG_STEREO_STATUS
++#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
++#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
++#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
++#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
++#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
++#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
++#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
++#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
++#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
++#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
++#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
++#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
++#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
++#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
++//OTG1_OTG_STEREO_CONTROL
++#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
++#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
++#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
++#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
++#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
++#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
++#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
++#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
++#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
++#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
++#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
++#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
++#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
++#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
++#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
++#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
++//OTG1_OTG_SNAPSHOT_STATUS
++#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
++#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
++#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
++#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
++#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
++#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
++//OTG1_OTG_SNAPSHOT_CONTROL
++#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
++#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
++//OTG1_OTG_SNAPSHOT_POSITION
++#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
++#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
++#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
++#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
++//OTG1_OTG_SNAPSHOT_FRAME
++#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
++#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
++//OTG1_OTG_INTERRUPT_CONTROL
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
++#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
++//OTG1_OTG_UPDATE_LOCK
++#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
++#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
++//OTG1_OTG_DOUBLE_BUFFER_CONTROL
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT                         0x2
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT                               0x3
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT                           0x4
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT                                0x10
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT                              0x18
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK                           0x00000004L
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK                                 0x00000008L
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK                             0x00000010L
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK                                  0x00010000L
++#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK                                0x03000000L
++//OTG1_OTG_MASTER_EN
++#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
++#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
++//OTG1_OTG_BLANK_DATA_COLOR
++#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT                                        0x0
++#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT                                        0xa
++#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT                                         0x14
++#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK                                          0x000003FFL
++#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK                                          0x000FFC00L
++#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK                                           0x3FF00000L
++//OTG1_OTG_BLANK_DATA_COLOR_EXT
++#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT                                0x0
++#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT                                0x8
++#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT                                 0x10
++#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK                                  0x0000003FL
++#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK                                  0x00003F00L
++#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK                                   0x003F0000L
++//OTG1_OTG_BLACK_COLOR
++#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT                                                     0x0
++#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT                                                      0xa
++#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT                                                     0x14
++#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK                                                       0x000003FFL
++#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK                                                        0x000FFC00L
++#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK                                                       0x3FF00000L
++//OTG1_OTG_BLACK_COLOR_EXT
++#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT                                             0x0
++#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT                                              0x8
++#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT                                             0x10
++#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK                                               0x0000003FL
++#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK                                                0x00003F00L
++#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK                                               0x003F0000L
++//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION
++#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
++#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
++#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
++#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
++//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL
++#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
++#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
++#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
++#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
++#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
++#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
++#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
++#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
++#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
++#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
++#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
++#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
++//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION
++#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
++#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
++//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL
++#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
++#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
++#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
++#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
++#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
++#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
++#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
++#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
++#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
++#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
++//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION
++#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
++#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
++//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL
++#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
++#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
++#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
++#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
++#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
++#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
++#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
++#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
++#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
++#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
++//OTG1_OTG_CRC_CNTL
++#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
++#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
++#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
++#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
++#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
++#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
++#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
++#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
++#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
++#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
++#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
++#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
++#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
++#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
++#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
++#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
++#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
++#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
++#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
++#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
++#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
++#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
++#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
++#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
++#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
++#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
++#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
++#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
++#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
++#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
++//OTG1_OTG_CRC_CNTL2
++#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
++#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
++#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
++#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
++#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
++#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
++#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
++#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
++//OTG1_OTG_CRC0_WINDOWA_X_CONTROL
++#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
++#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
++#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
++#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
++//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL
++#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
++#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
++#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
++#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
++//OTG1_OTG_CRC0_WINDOWB_X_CONTROL
++#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
++#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
++#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
++#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
++//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL
++#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
++#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
++#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
++#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
++//OTG1_OTG_CRC0_DATA_RG
++#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
++#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
++#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
++//OTG1_OTG_CRC0_DATA_B
++#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
++#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
++#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
++//OTG1_OTG_CRC1_WINDOWA_X_CONTROL
++#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
++#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
++#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
++#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
++//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL
++#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
++#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
++#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
++#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
++//OTG1_OTG_CRC1_WINDOWB_X_CONTROL
++#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
++#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
++#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
++#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
++//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL
++#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
++#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
++#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
++#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
++//OTG1_OTG_CRC1_DATA_RG
++#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
++#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
++#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
++//OTG1_OTG_CRC1_DATA_B
++#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
++#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
++#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
++//OTG1_OTG_CRC2_DATA_RG
++#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
++#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
++#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
++//OTG1_OTG_CRC2_DATA_B
++#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
++#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
++#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
++//OTG1_OTG_CRC3_DATA_RG
++#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
++#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
++#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
++//OTG1_OTG_CRC3_DATA_B
++#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
++#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
++#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
++//OTG1_OTG_CRC_SIG_RED_GREEN_MASK
++#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
++#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
++#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
++#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
++//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK
++#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
++#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
++#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
++#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
++//OTG1_OTG_STATIC_SCREEN_CONTROL
++#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
++#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
++#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
++#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
++#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
++#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
++#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
++#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
++#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
++#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
++#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
++#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
++#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
++#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
++#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
++#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
++#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
++#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
++//OTG1_OTG_3D_STRUCTURE_CONTROL
++#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
++#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
++#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
++#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
++#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
++#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
++#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
++#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
++#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
++#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
++#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
++#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
++//OTG1_OTG_GSL_VSYNC_GAP
++#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
++#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
++#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
++#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
++#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
++#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
++#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
++#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
++#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
++#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
++#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
++#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
++#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
++#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
++#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
++#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
++//OTG1_OTG_MASTER_UPDATE_MODE
++#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
++#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
++//OTG1_OTG_CLOCK_CONTROL
++#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
++#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
++#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
++#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
++#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
++#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
++#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
++#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
++#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
++#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
++//OTG1_OTG_VSTARTUP_PARAM
++#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
++#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
++//OTG1_OTG_VUPDATE_PARAM
++#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
++#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
++#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
++#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
++//OTG1_OTG_VREADY_PARAM
++#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
++#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
++//OTG1_OTG_GLOBAL_SYNC_STATUS
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
++#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
++//OTG1_OTG_MASTER_UPDATE_LOCK
++#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
++#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
++#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
++#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
++//OTG1_OTG_GSL_CONTROL
++#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
++#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
++#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
++#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
++#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
++#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
++#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
++#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
++#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
++#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
++#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
++#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
++#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
++#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
++#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
++#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
++#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
++#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
++//OTG1_OTG_GSL_WINDOW_X
++#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
++#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
++#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
++#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
++//OTG1_OTG_GSL_WINDOW_Y
++#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
++#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
++#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
++#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
++//OTG1_OTG_VUPDATE_KEEPOUT
++#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
++#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
++#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
++#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
++#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
++#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
++//OTG1_OTG_GLOBAL_CONTROL0
++#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT                                0x0
++#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT                             0x8
++#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
++#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK                                  0x000000FFL
++#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK                               0x00000100L
++#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
++//OTG1_OTG_GLOBAL_CONTROL1
++#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT                                              0x0
++#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT                                              0x10
++#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
++#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK                                                0x00007FFFL
++#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK                                                0x7FFF0000L
++#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
++//OTG1_OTG_GLOBAL_CONTROL2
++#define OTG1_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT                                                  0x0
++#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
++#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
++#define OTG1_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT                                        0x1d
++#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
++#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
++#define OTG1_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK                                                    0x000003FFL
++#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
++#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
++#define OTG1_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK                                          0x20000000L
++#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
++#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
++//OTG1_OTG_GLOBAL_CONTROL3
++#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
++#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
++#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT                          0x8
++#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
++#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
++#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK                            0x00000100L
++//OTG1_OTG_TRIG_MANUAL_CONTROL
++#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
++#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
++//OTG1_OTG_MANUAL_FLOW_CONTROL
++#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
++#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
++//OTG1_OTG_RANGE_TIMING_INT_STATUS
++#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                             0x0
++#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT                         0x4
++#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                       0x8
++#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                     0xc
++#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                    0x10
++#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK                               0x00000001L
++#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK                           0x00000010L
++#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK                         0x00000100L
++#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                       0x00001000L
++#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                      0x00010000L
++//OTG1_OTG_DRR_CONTROL
++#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
++#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
++#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000007L
++#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
++//OTG1_OTG_REQUEST_CONTROL
++#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
++#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
++//OTG1_OTG_DSC_START_POSITION
++#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
++#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
++#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
++#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
++//OTG1_OTG_PIPE_UPDATE_STATUS
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT                                                    0x1
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT                                              0x2
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT                                           0x5
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT                                     0x6
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT                                           0x9
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT                                     0xa
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK                                                      0x00000002L
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK                                                0x00000004L
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK                                             0x00000020L
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK                                       0x00000040L
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK                                             0x00000200L
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK                                       0x00000400L
++#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
++//OTG1_OTG_SPARE_REGISTER
++#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
++#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_optc_otg2_dispdec
++//OTG2_OTG_H_TOTAL
++#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
++#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
++//OTG2_OTG_H_BLANK_START_END
++#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
++#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
++#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
++#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
++//OTG2_OTG_H_SYNC_A
++#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
++#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
++#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
++#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
++//OTG2_OTG_H_SYNC_A_CNTL
++#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
++#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
++#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
++#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
++#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
++#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
++//OTG2_OTG_H_TIMING_CNTL
++#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT                                                   0x0
++#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT                                       0x8
++#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK                                                     0x00000001L
++#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK                                         0x00000100L
++//OTG2_OTG_V_TOTAL
++#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
++#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
++//OTG2_OTG_V_TOTAL_MIN
++#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
++#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
++//OTG2_OTG_V_TOTAL_MAX
++#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
++#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
++//OTG2_OTG_V_TOTAL_MID
++#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
++#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
++//OTG2_OTG_V_TOTAL_CONTROL
++#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
++#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
++#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
++#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
++#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
++#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
++#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT                                          0x7
++#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
++#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
++#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
++#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
++#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
++#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
++#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
++#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
++#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK                                            0x00000080L
++#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
++#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
++//OTG2_OTG_V_TOTAL_INT_STATUS
++#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
++#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
++#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
++#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
++#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
++#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
++#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
++#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
++//OTG2_OTG_VSYNC_NOM_INT_STATUS
++#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
++#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
++#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
++#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
++//OTG2_OTG_V_BLANK_START_END
++#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
++#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
++#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
++#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
++//OTG2_OTG_V_SYNC_A
++#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
++#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
++#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
++#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
++//OTG2_OTG_V_SYNC_A_CNTL
++#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
++#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
++//OTG2_OTG_TRIGA_CNTL
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
++#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
++//OTG2_OTG_TRIGA_MANUAL_TRIG
++#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
++#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
++//OTG2_OTG_TRIGB_CNTL
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
++#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
++//OTG2_OTG_TRIGB_MANUAL_TRIG
++#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
++#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
++//OTG2_OTG_FORCE_COUNT_NOW_CNTL
++#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
++#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
++#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
++#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
++#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
++#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
++#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
++#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
++#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
++#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
++//OTG2_OTG_FLOW_CONTROL
++#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
++#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
++#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
++#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
++#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
++#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
++#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
++#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
++//OTG2_OTG_STEREO_FORCE_NEXT_EYE
++#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
++#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT                                       0x8
++#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT                                        0x10
++#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
++#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK                                         0x0000FF00L
++#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK                                          0x1FFF0000L
++//OTG2_OTG_CONTROL
++#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
++#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
++#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
++#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
++#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
++#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
++#define OTG2_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT                                                0x18
++#define OTG2_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT                                                     0x1e
++#define OTG2_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT                                                0x1f
++#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
++#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
++#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
++#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
++#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
++#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
++#define OTG2_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK                                                  0x01000000L
++#define OTG2_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK                                                       0x40000000L
++#define OTG2_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK                                                  0x80000000L
++//OTG2_OTG_BLANK_CONTROL
++#define OTG2_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT                                                0x0
++#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT                                                      0x8
++#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT                                                      0x10
++#define OTG2_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK                                                  0x00000001L
++#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK                                                        0x00000100L
++#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK                                                        0x00010000L
++//OTG2_OTG_PIPE_ABORT_CONTROL
++#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT                                                    0x0
++#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT                                               0x8
++#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK                                                      0x00000001L
++#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK                                                 0x00000100L
++//OTG2_OTG_INTERLACE_CONTROL
++#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
++#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
++#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
++#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
++//OTG2_OTG_INTERLACE_STATUS
++#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
++#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
++#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
++#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
++//OTG2_OTG_PIXEL_DATA_READBACK0
++#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
++#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
++#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
++#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
++//OTG2_OTG_PIXEL_DATA_READBACK1
++#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
++#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
++//OTG2_OTG_STATUS
++#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
++#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
++#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
++#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
++#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
++#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
++#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
++#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
++#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
++#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
++#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
++#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
++#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
++#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
++#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
++#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
++//OTG2_OTG_STATUS_POSITION
++#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
++#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
++#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
++#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
++//OTG2_OTG_NOM_VERT_POSITION
++#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
++#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
++//OTG2_OTG_STATUS_FRAME_COUNT
++#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
++#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
++//OTG2_OTG_STATUS_VF_COUNT
++#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
++#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
++//OTG2_OTG_STATUS_HV_COUNT
++#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
++#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
++//OTG2_OTG_COUNT_CONTROL
++#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
++#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
++#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
++#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
++//OTG2_OTG_COUNT_RESET
++#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
++#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
++//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
++#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
++#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
++//OTG2_OTG_VERT_SYNC_CONTROL
++#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
++#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
++#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
++#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
++#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
++#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
++//OTG2_OTG_STEREO_STATUS
++#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
++#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
++#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
++#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
++#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
++#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
++#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
++#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
++#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
++#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
++#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
++#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
++#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
++#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
++//OTG2_OTG_STEREO_CONTROL
++#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
++#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
++#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
++#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
++#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
++#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
++#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
++#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
++#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
++#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
++#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
++#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
++#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
++#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
++#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
++#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
++//OTG2_OTG_SNAPSHOT_STATUS
++#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
++#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
++#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
++#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
++#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
++#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
++//OTG2_OTG_SNAPSHOT_CONTROL
++#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
++#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
++//OTG2_OTG_SNAPSHOT_POSITION
++#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
++#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
++#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
++#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
++//OTG2_OTG_SNAPSHOT_FRAME
++#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
++#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
++//OTG2_OTG_INTERRUPT_CONTROL
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
++#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
++//OTG2_OTG_UPDATE_LOCK
++#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
++#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
++//OTG2_OTG_DOUBLE_BUFFER_CONTROL
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT                         0x2
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT                               0x3
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT                           0x4
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT                                0x10
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT                              0x18
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK                           0x00000004L
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK                                 0x00000008L
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK                             0x00000010L
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK                                  0x00010000L
++#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK                                0x03000000L
++//OTG2_OTG_MASTER_EN
++#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
++#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
++//OTG2_OTG_BLANK_DATA_COLOR
++#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT                                        0x0
++#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT                                        0xa
++#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT                                         0x14
++#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK                                          0x000003FFL
++#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK                                          0x000FFC00L
++#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK                                           0x3FF00000L
++//OTG2_OTG_BLANK_DATA_COLOR_EXT
++#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT                                0x0
++#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT                                0x8
++#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT                                 0x10
++#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK                                  0x0000003FL
++#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK                                  0x00003F00L
++#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK                                   0x003F0000L
++//OTG2_OTG_BLACK_COLOR
++#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT                                                     0x0
++#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT                                                      0xa
++#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT                                                     0x14
++#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK                                                       0x000003FFL
++#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK                                                        0x000FFC00L
++#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK                                                       0x3FF00000L
++//OTG2_OTG_BLACK_COLOR_EXT
++#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT                                             0x0
++#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT                                              0x8
++#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT                                             0x10
++#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK                                               0x0000003FL
++#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK                                                0x00003F00L
++#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK                                               0x003F0000L
++//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION
++#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
++#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
++#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
++#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
++//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL
++#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
++#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
++#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
++#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
++#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
++#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
++#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
++#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
++#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
++#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
++#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
++#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
++//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION
++#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
++#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
++//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL
++#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
++#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
++#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
++#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
++#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
++#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
++#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
++#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
++#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
++#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
++//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION
++#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
++#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
++//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL
++#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
++#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
++#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
++#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
++#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
++#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
++#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
++#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
++#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
++#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
++//OTG2_OTG_CRC_CNTL
++#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
++#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
++#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
++#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
++#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
++#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
++#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
++#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
++#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
++#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
++#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
++#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
++#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
++#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
++#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
++#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
++#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
++#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
++#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
++#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
++#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
++#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
++#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
++#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
++#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
++#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
++#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
++#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
++#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
++#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
++//OTG2_OTG_CRC_CNTL2
++#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
++#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
++#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
++#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
++#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
++#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
++#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
++#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
++//OTG2_OTG_CRC0_WINDOWA_X_CONTROL
++#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
++#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
++#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
++#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
++//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL
++#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
++#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
++#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
++#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
++//OTG2_OTG_CRC0_WINDOWB_X_CONTROL
++#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
++#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
++#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
++#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
++//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL
++#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
++#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
++#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
++#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
++//OTG2_OTG_CRC0_DATA_RG
++#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
++#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
++#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
++//OTG2_OTG_CRC0_DATA_B
++#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
++#define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
++#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
++//OTG2_OTG_CRC1_WINDOWA_X_CONTROL
++#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
++#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
++#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
++#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
++//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL
++#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
++#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
++#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
++#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
++//OTG2_OTG_CRC1_WINDOWB_X_CONTROL
++#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
++#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
++#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
++#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
++//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL
++#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
++#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
++#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
++#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
++//OTG2_OTG_CRC1_DATA_RG
++#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
++#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
++#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
++//OTG2_OTG_CRC1_DATA_B
++#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
++#define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
++#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
++//OTG2_OTG_CRC2_DATA_RG
++#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
++#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
++#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
++//OTG2_OTG_CRC2_DATA_B
++#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
++#define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
++#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
++//OTG2_OTG_CRC3_DATA_RG
++#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
++#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
++#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
++//OTG2_OTG_CRC3_DATA_B
++#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
++#define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
++#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
++//OTG2_OTG_CRC_SIG_RED_GREEN_MASK
++#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
++#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
++#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
++#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
++//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK
++#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
++#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
++#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
++#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
++//OTG2_OTG_STATIC_SCREEN_CONTROL
++#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
++#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
++#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
++#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
++#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
++#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
++#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
++#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
++#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
++#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
++#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
++#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
++#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
++#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
++#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
++#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
++#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
++#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
++//OTG2_OTG_3D_STRUCTURE_CONTROL
++#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
++#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
++#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
++#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
++#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
++#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
++#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
++#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
++#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
++#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
++#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
++#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
++//OTG2_OTG_GSL_VSYNC_GAP
++#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
++#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
++#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
++#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
++#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
++#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
++#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
++#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
++#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
++#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
++#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
++#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
++#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
++#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
++#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
++#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
++//OTG2_OTG_MASTER_UPDATE_MODE
++#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
++#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
++//OTG2_OTG_CLOCK_CONTROL
++#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
++#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
++#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
++#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
++#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
++#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
++#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
++#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
++#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
++#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
++//OTG2_OTG_VSTARTUP_PARAM
++#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
++#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
++//OTG2_OTG_VUPDATE_PARAM
++#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
++#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
++#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
++#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
++//OTG2_OTG_VREADY_PARAM
++#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
++#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
++//OTG2_OTG_GLOBAL_SYNC_STATUS
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
++#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
++//OTG2_OTG_MASTER_UPDATE_LOCK
++#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
++#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
++#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
++#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
++//OTG2_OTG_GSL_CONTROL
++#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
++#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
++#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
++#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
++#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
++#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
++#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
++#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
++#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
++#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
++#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
++#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
++#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
++#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
++#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
++#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
++#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
++#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
++//OTG2_OTG_GSL_WINDOW_X
++#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
++#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
++#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
++#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
++//OTG2_OTG_GSL_WINDOW_Y
++#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
++#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
++#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
++#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
++//OTG2_OTG_VUPDATE_KEEPOUT
++#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
++#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
++#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
++#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
++#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
++#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
++//OTG2_OTG_GLOBAL_CONTROL0
++#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT                                0x0
++#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT                             0x8
++#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
++#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK                                  0x000000FFL
++#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK                               0x00000100L
++#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
++//OTG2_OTG_GLOBAL_CONTROL1
++#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT                                              0x0
++#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT                                              0x10
++#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
++#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK                                                0x00007FFFL
++#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK                                                0x7FFF0000L
++#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
++//OTG2_OTG_GLOBAL_CONTROL2
++#define OTG2_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT                                                  0x0
++#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
++#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
++#define OTG2_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT                                        0x1d
++#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
++#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
++#define OTG2_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK                                                    0x000003FFL
++#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
++#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
++#define OTG2_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK                                          0x20000000L
++#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
++#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
++//OTG2_OTG_GLOBAL_CONTROL3
++#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
++#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
++#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT                          0x8
++#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
++#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
++#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK                            0x00000100L
++//OTG2_OTG_TRIG_MANUAL_CONTROL
++#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
++#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
++//OTG2_OTG_MANUAL_FLOW_CONTROL
++#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
++#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
++//OTG2_OTG_RANGE_TIMING_INT_STATUS
++#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                             0x0
++#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT                         0x4
++#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                       0x8
++#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                     0xc
++#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                    0x10
++#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK                               0x00000001L
++#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK                           0x00000010L
++#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK                         0x00000100L
++#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                       0x00001000L
++#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                      0x00010000L
++//OTG2_OTG_DRR_CONTROL
++#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
++#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
++#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000007L
++#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
++//OTG2_OTG_REQUEST_CONTROL
++#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
++#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
++//OTG2_OTG_DSC_START_POSITION
++#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
++#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
++#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
++#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
++//OTG2_OTG_PIPE_UPDATE_STATUS
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT                                                    0x1
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT                                              0x2
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT                                           0x5
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT                                     0x6
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT                                           0x9
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT                                     0xa
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK                                                      0x00000002L
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK                                                0x00000004L
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK                                             0x00000020L
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK                                       0x00000040L
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK                                             0x00000200L
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK                                       0x00000400L
++#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
++//OTG2_OTG_SPARE_REGISTER
++#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
++#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_optc_otg3_dispdec
++//OTG3_OTG_H_TOTAL
++#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
++#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
++//OTG3_OTG_H_BLANK_START_END
++#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
++#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
++#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
++#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
++//OTG3_OTG_H_SYNC_A
++#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
++#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
++#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
++#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
++//OTG3_OTG_H_SYNC_A_CNTL
++#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
++#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
++#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
++#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
++#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
++#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
++//OTG3_OTG_H_TIMING_CNTL
++#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT                                                   0x0
++#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT                                       0x8
++#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK                                                     0x00000001L
++#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK                                         0x00000100L
++//OTG3_OTG_V_TOTAL
++#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
++#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
++//OTG3_OTG_V_TOTAL_MIN
++#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
++#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
++//OTG3_OTG_V_TOTAL_MAX
++#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
++#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
++//OTG3_OTG_V_TOTAL_MID
++#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
++#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
++//OTG3_OTG_V_TOTAL_CONTROL
++#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
++#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
++#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
++#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
++#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
++#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
++#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT                                          0x7
++#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
++#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
++#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
++#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
++#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
++#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
++#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
++#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
++#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK                                            0x00000080L
++#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
++#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
++//OTG3_OTG_V_TOTAL_INT_STATUS
++#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
++#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
++#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
++#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
++#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
++#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
++#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
++#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
++//OTG3_OTG_VSYNC_NOM_INT_STATUS
++#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
++#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
++#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
++#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
++//OTG3_OTG_V_BLANK_START_END
++#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
++#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
++#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
++#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
++//OTG3_OTG_V_SYNC_A
++#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
++#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
++#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
++#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
++//OTG3_OTG_V_SYNC_A_CNTL
++#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
++#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
++//OTG3_OTG_TRIGA_CNTL
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
++#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
++//OTG3_OTG_TRIGA_MANUAL_TRIG
++#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
++#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
++//OTG3_OTG_TRIGB_CNTL
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
++#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
++//OTG3_OTG_TRIGB_MANUAL_TRIG
++#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
++#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
++//OTG3_OTG_FORCE_COUNT_NOW_CNTL
++#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
++#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
++#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
++#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
++#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
++#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
++#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
++#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
++#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
++#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
++//OTG3_OTG_FLOW_CONTROL
++#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
++#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
++#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
++#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
++#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
++#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
++#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
++#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
++//OTG3_OTG_STEREO_FORCE_NEXT_EYE
++#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
++#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT                                       0x8
++#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT                                        0x10
++#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
++#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK                                         0x0000FF00L
++#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK                                          0x1FFF0000L
++//OTG3_OTG_CONTROL
++#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
++#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
++#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
++#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
++#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
++#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
++#define OTG3_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT                                                0x18
++#define OTG3_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT                                                     0x1e
++#define OTG3_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT                                                0x1f
++#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
++#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
++#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
++#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
++#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
++#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
++#define OTG3_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK                                                  0x01000000L
++#define OTG3_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK                                                       0x40000000L
++#define OTG3_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK                                                  0x80000000L
++//OTG3_OTG_BLANK_CONTROL
++#define OTG3_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT                                                0x0
++#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT                                                      0x8
++#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT                                                      0x10
++#define OTG3_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK                                                  0x00000001L
++#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK                                                        0x00000100L
++#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK                                                        0x00010000L
++//OTG3_OTG_PIPE_ABORT_CONTROL
++#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT                                                    0x0
++#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT                                               0x8
++#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK                                                      0x00000001L
++#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK                                                 0x00000100L
++//OTG3_OTG_INTERLACE_CONTROL
++#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
++#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
++#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
++#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
++//OTG3_OTG_INTERLACE_STATUS
++#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
++#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
++#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
++#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
++//OTG3_OTG_PIXEL_DATA_READBACK0
++#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
++#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
++#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
++#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
++//OTG3_OTG_PIXEL_DATA_READBACK1
++#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
++#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
++//OTG3_OTG_STATUS
++#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
++#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
++#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
++#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
++#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
++#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
++#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
++#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
++#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
++#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
++#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
++#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
++#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
++#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
++#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
++#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
++//OTG3_OTG_STATUS_POSITION
++#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
++#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
++#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
++#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
++//OTG3_OTG_NOM_VERT_POSITION
++#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
++#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
++//OTG3_OTG_STATUS_FRAME_COUNT
++#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
++#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
++//OTG3_OTG_STATUS_VF_COUNT
++#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
++#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
++//OTG3_OTG_STATUS_HV_COUNT
++#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
++#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
++//OTG3_OTG_COUNT_CONTROL
++#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
++#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
++#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
++#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
++//OTG3_OTG_COUNT_RESET
++#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
++#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
++//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
++#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
++#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
++//OTG3_OTG_VERT_SYNC_CONTROL
++#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
++#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
++#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
++#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
++#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
++#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
++//OTG3_OTG_STEREO_STATUS
++#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
++#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
++#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
++#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
++#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
++#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
++#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
++#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
++#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
++#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
++#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
++#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
++#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
++#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
++//OTG3_OTG_STEREO_CONTROL
++#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
++#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
++#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
++#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
++#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
++#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
++#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
++#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
++#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
++#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
++#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
++#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
++#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
++#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
++#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
++#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
++//OTG3_OTG_SNAPSHOT_STATUS
++#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
++#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
++#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
++#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
++#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
++#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
++//OTG3_OTG_SNAPSHOT_CONTROL
++#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
++#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
++//OTG3_OTG_SNAPSHOT_POSITION
++#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
++#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
++#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
++#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
++//OTG3_OTG_SNAPSHOT_FRAME
++#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
++#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
++//OTG3_OTG_INTERRUPT_CONTROL
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
++#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
++//OTG3_OTG_UPDATE_LOCK
++#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
++#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
++//OTG3_OTG_DOUBLE_BUFFER_CONTROL
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT                         0x2
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT                               0x3
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT                           0x4
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT                                0x10
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT                              0x18
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK                           0x00000004L
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK                                 0x00000008L
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK                             0x00000010L
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK                                  0x00010000L
++#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK                                0x03000000L
++//OTG3_OTG_MASTER_EN
++#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
++#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
++//OTG3_OTG_BLANK_DATA_COLOR
++#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT                                        0x0
++#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT                                        0xa
++#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT                                         0x14
++#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK                                          0x000003FFL
++#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK                                          0x000FFC00L
++#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK                                           0x3FF00000L
++//OTG3_OTG_BLANK_DATA_COLOR_EXT
++#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT                                0x0
++#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT                                0x8
++#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT                                 0x10
++#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK                                  0x0000003FL
++#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK                                  0x00003F00L
++#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK                                   0x003F0000L
++//OTG3_OTG_BLACK_COLOR
++#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT                                                     0x0
++#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT                                                      0xa
++#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT                                                     0x14
++#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK                                                       0x000003FFL
++#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK                                                        0x000FFC00L
++#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK                                                       0x3FF00000L
++//OTG3_OTG_BLACK_COLOR_EXT
++#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT                                             0x0
++#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT                                              0x8
++#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT                                             0x10
++#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK                                               0x0000003FL
++#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK                                                0x00003F00L
++#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK                                               0x003F0000L
++//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION
++#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
++#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
++#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
++#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
++//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL
++#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
++#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
++#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
++#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
++#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
++#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
++#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
++#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
++#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
++#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
++#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
++#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
++//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION
++#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
++#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
++//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL
++#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
++#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
++#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
++#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
++#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
++#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
++#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
++#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
++#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
++#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
++//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION
++#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
++#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
++//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL
++#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
++#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
++#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
++#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
++#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
++#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
++#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
++#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
++#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
++#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
++//OTG3_OTG_CRC_CNTL
++#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
++#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
++#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
++#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
++#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
++#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
++#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
++#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
++#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
++#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
++#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
++#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
++#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
++#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
++#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
++#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
++#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
++#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
++#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
++#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
++#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
++#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
++#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
++#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
++#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
++#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
++#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
++#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
++#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
++#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
++//OTG3_OTG_CRC_CNTL2
++#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
++#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
++#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
++#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
++#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
++#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
++#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
++#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
++//OTG3_OTG_CRC0_WINDOWA_X_CONTROL
++#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
++#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
++#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
++#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
++//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL
++#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
++#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
++#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
++#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
++//OTG3_OTG_CRC0_WINDOWB_X_CONTROL
++#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
++#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
++#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
++#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
++//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL
++#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
++#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
++#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
++#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
++//OTG3_OTG_CRC0_DATA_RG
++#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
++#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
++#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
++//OTG3_OTG_CRC0_DATA_B
++#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
++#define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
++#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
++//OTG3_OTG_CRC1_WINDOWA_X_CONTROL
++#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
++#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
++#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
++#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
++//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL
++#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
++#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
++#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
++#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
++//OTG3_OTG_CRC1_WINDOWB_X_CONTROL
++#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
++#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
++#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
++#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
++//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL
++#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
++#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
++#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
++#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
++//OTG3_OTG_CRC1_DATA_RG
++#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
++#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
++#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
++//OTG3_OTG_CRC1_DATA_B
++#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
++#define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
++#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
++//OTG3_OTG_CRC2_DATA_RG
++#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
++#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
++#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
++//OTG3_OTG_CRC2_DATA_B
++#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
++#define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
++#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
++//OTG3_OTG_CRC3_DATA_RG
++#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
++#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
++#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
++//OTG3_OTG_CRC3_DATA_B
++#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
++#define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
++#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
++//OTG3_OTG_CRC_SIG_RED_GREEN_MASK
++#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
++#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
++#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
++#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
++//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK
++#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
++#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
++#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
++#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
++//OTG3_OTG_STATIC_SCREEN_CONTROL
++#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
++#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
++#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
++#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
++#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
++#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
++#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
++#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
++#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
++#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
++#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
++#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
++#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
++#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
++#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
++#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
++#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
++#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
++//OTG3_OTG_3D_STRUCTURE_CONTROL
++#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
++#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
++#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
++#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
++#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
++#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
++#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
++#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
++#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
++#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
++#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
++#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
++//OTG3_OTG_GSL_VSYNC_GAP
++#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
++#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
++#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
++#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
++#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
++#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
++#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
++#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
++#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
++#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
++#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
++#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
++#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
++#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
++#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
++#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
++//OTG3_OTG_MASTER_UPDATE_MODE
++#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
++#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
++//OTG3_OTG_CLOCK_CONTROL
++#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
++#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
++#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
++#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
++#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
++#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
++#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
++#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
++#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
++#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
++//OTG3_OTG_VSTARTUP_PARAM
++#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
++#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
++//OTG3_OTG_VUPDATE_PARAM
++#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
++#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
++#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
++#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
++//OTG3_OTG_VREADY_PARAM
++#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
++#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
++//OTG3_OTG_GLOBAL_SYNC_STATUS
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
++#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
++//OTG3_OTG_MASTER_UPDATE_LOCK
++#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
++#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
++#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
++#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
++//OTG3_OTG_GSL_CONTROL
++#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
++#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
++#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
++#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
++#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
++#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
++#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
++#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
++#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
++#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
++#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
++#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
++#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
++#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
++#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
++#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
++#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
++#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
++//OTG3_OTG_GSL_WINDOW_X
++#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
++#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
++#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
++#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
++//OTG3_OTG_GSL_WINDOW_Y
++#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
++#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
++#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
++#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
++//OTG3_OTG_VUPDATE_KEEPOUT
++#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
++#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
++#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
++#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
++#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
++#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
++//OTG3_OTG_GLOBAL_CONTROL0
++#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT                                0x0
++#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT                             0x8
++#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
++#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK                                  0x000000FFL
++#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK                               0x00000100L
++#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
++//OTG3_OTG_GLOBAL_CONTROL1
++#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT                                              0x0
++#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT                                              0x10
++#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
++#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK                                                0x00007FFFL
++#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK                                                0x7FFF0000L
++#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
++//OTG3_OTG_GLOBAL_CONTROL2
++#define OTG3_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT                                                  0x0
++#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
++#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
++#define OTG3_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT                                        0x1d
++#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
++#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
++#define OTG3_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK                                                    0x000003FFL
++#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
++#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
++#define OTG3_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK                                          0x20000000L
++#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
++#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
++//OTG3_OTG_GLOBAL_CONTROL3
++#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
++#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
++#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT                          0x8
++#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
++#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
++#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK                            0x00000100L
++//OTG3_OTG_TRIG_MANUAL_CONTROL
++#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
++#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
++//OTG3_OTG_MANUAL_FLOW_CONTROL
++#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
++#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
++//OTG3_OTG_RANGE_TIMING_INT_STATUS
++#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                             0x0
++#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT                         0x4
++#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                       0x8
++#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                     0xc
++#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                    0x10
++#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK                               0x00000001L
++#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK                           0x00000010L
++#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK                         0x00000100L
++#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                       0x00001000L
++#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                      0x00010000L
++//OTG3_OTG_DRR_CONTROL
++#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
++#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
++#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000007L
++#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
++//OTG3_OTG_REQUEST_CONTROL
++#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
++#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
++//OTG3_OTG_DSC_START_POSITION
++#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
++#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
++#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
++#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
++//OTG3_OTG_PIPE_UPDATE_STATUS
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT                                                    0x1
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT                                              0x2
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT                                           0x5
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT                                     0x6
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT                                           0x9
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT                                     0xa
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK                                                      0x00000002L
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK                                                0x00000004L
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK                                             0x00000020L
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK                                       0x00000040L
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK                                             0x00000200L
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK                                       0x00000400L
++#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
++//OTG3_OTG_SPARE_REGISTER
++#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
++#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_optc_otg4_dispdec
++//OTG4_OTG_H_TOTAL
++#define OTG4_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
++#define OTG4_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
++//OTG4_OTG_H_BLANK_START_END
++#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
++#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
++#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
++#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
++//OTG4_OTG_H_SYNC_A
++#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
++#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
++#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
++#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
++//OTG4_OTG_H_SYNC_A_CNTL
++#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
++#define OTG4_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
++#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
++#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
++#define OTG4_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
++#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
++//OTG4_OTG_H_TIMING_CNTL
++#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT                                                   0x0
++#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT                                       0x8
++#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK                                                     0x00000001L
++#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK                                         0x00000100L
++//OTG4_OTG_V_TOTAL
++#define OTG4_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
++#define OTG4_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
++//OTG4_OTG_V_TOTAL_MIN
++#define OTG4_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
++#define OTG4_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
++//OTG4_OTG_V_TOTAL_MAX
++#define OTG4_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
++#define OTG4_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
++//OTG4_OTG_V_TOTAL_MID
++#define OTG4_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
++#define OTG4_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
++//OTG4_OTG_V_TOTAL_CONTROL
++#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
++#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
++#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
++#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
++#define OTG4_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
++#define OTG4_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
++#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT                                          0x7
++#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
++#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
++#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
++#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
++#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
++#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
++#define OTG4_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
++#define OTG4_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
++#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK                                            0x00000080L
++#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
++#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
++//OTG4_OTG_V_TOTAL_INT_STATUS
++#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
++#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
++#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
++#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
++#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
++#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
++#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
++#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
++//OTG4_OTG_VSYNC_NOM_INT_STATUS
++#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
++#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
++#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
++#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
++//OTG4_OTG_V_BLANK_START_END
++#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
++#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
++#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
++#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
++//OTG4_OTG_V_SYNC_A
++#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
++#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
++#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
++#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
++//OTG4_OTG_V_SYNC_A_CNTL
++#define OTG4_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
++#define OTG4_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
++//OTG4_OTG_TRIGA_CNTL
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
++#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
++//OTG4_OTG_TRIGA_MANUAL_TRIG
++#define OTG4_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
++#define OTG4_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
++//OTG4_OTG_TRIGB_CNTL
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
++#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
++//OTG4_OTG_TRIGB_MANUAL_TRIG
++#define OTG4_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
++#define OTG4_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
++//OTG4_OTG_FORCE_COUNT_NOW_CNTL
++#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
++#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
++#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
++#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
++#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
++#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
++#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
++#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
++#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
++#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
++//OTG4_OTG_FLOW_CONTROL
++#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
++#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
++#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
++#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
++#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
++#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
++#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
++#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
++//OTG4_OTG_STEREO_FORCE_NEXT_EYE
++#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
++#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT                                       0x8
++#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT                                        0x10
++#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
++#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK                                         0x0000FF00L
++#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK                                          0x1FFF0000L
++//OTG4_OTG_CONTROL
++#define OTG4_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
++#define OTG4_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
++#define OTG4_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
++#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
++#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
++#define OTG4_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
++#define OTG4_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT                                                0x18
++#define OTG4_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT                                                     0x1e
++#define OTG4_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT                                                0x1f
++#define OTG4_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
++#define OTG4_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
++#define OTG4_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
++#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
++#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
++#define OTG4_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
++#define OTG4_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK                                                  0x01000000L
++#define OTG4_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK                                                       0x40000000L
++#define OTG4_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK                                                  0x80000000L
++//OTG4_OTG_BLANK_CONTROL
++#define OTG4_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT                                                0x0
++#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT                                                      0x8
++#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT                                                      0x10
++#define OTG4_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK                                                  0x00000001L
++#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK                                                        0x00000100L
++#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK                                                        0x00010000L
++//OTG4_OTG_PIPE_ABORT_CONTROL
++#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT                                                    0x0
++#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT                                               0x8
++#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK                                                      0x00000001L
++#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK                                                 0x00000100L
++//OTG4_OTG_INTERLACE_CONTROL
++#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
++#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
++#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
++#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
++//OTG4_OTG_INTERLACE_STATUS
++#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
++#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
++#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
++#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
++//OTG4_OTG_PIXEL_DATA_READBACK0
++#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
++#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
++#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
++#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
++//OTG4_OTG_PIXEL_DATA_READBACK1
++#define OTG4_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
++#define OTG4_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
++//OTG4_OTG_STATUS
++#define OTG4_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
++#define OTG4_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
++#define OTG4_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
++#define OTG4_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
++#define OTG4_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
++#define OTG4_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
++#define OTG4_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
++#define OTG4_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
++#define OTG4_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
++#define OTG4_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
++#define OTG4_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
++#define OTG4_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
++#define OTG4_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
++#define OTG4_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
++#define OTG4_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
++#define OTG4_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
++//OTG4_OTG_STATUS_POSITION
++#define OTG4_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
++#define OTG4_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
++#define OTG4_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
++#define OTG4_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
++//OTG4_OTG_NOM_VERT_POSITION
++#define OTG4_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
++#define OTG4_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
++//OTG4_OTG_STATUS_FRAME_COUNT
++#define OTG4_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
++#define OTG4_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
++//OTG4_OTG_STATUS_VF_COUNT
++#define OTG4_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
++#define OTG4_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
++//OTG4_OTG_STATUS_HV_COUNT
++#define OTG4_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
++#define OTG4_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
++//OTG4_OTG_COUNT_CONTROL
++#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
++#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
++#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
++#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
++//OTG4_OTG_COUNT_RESET
++#define OTG4_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
++#define OTG4_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
++//OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
++#define OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
++#define OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
++//OTG4_OTG_VERT_SYNC_CONTROL
++#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
++#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
++#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
++#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
++#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
++#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
++//OTG4_OTG_STEREO_STATUS
++#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
++#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
++#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
++#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
++#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
++#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
++#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
++#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
++#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
++#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
++#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
++#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
++#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
++#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
++//OTG4_OTG_STEREO_CONTROL
++#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
++#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
++#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
++#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
++#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
++#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
++#define OTG4_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
++#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
++#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
++#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
++#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
++#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
++#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
++#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
++#define OTG4_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
++#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
++//OTG4_OTG_SNAPSHOT_STATUS
++#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
++#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
++#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
++#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
++#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
++#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
++//OTG4_OTG_SNAPSHOT_CONTROL
++#define OTG4_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
++#define OTG4_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
++//OTG4_OTG_SNAPSHOT_POSITION
++#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
++#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
++#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
++#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
++//OTG4_OTG_SNAPSHOT_FRAME
++#define OTG4_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
++#define OTG4_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
++//OTG4_OTG_INTERRUPT_CONTROL
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
++#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
++//OTG4_OTG_UPDATE_LOCK
++#define OTG4_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
++#define OTG4_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
++//OTG4_OTG_DOUBLE_BUFFER_CONTROL
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT                         0x2
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT                               0x3
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT                           0x4
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT                                0x10
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT                              0x18
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK                           0x00000004L
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK                                 0x00000008L
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK                             0x00000010L
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK                                  0x00010000L
++#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK                                0x03000000L
++//OTG4_OTG_MASTER_EN
++#define OTG4_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
++#define OTG4_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
++//OTG4_OTG_BLANK_DATA_COLOR
++#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT                                        0x0
++#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT                                        0xa
++#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT                                         0x14
++#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK                                          0x000003FFL
++#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK                                          0x000FFC00L
++#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK                                           0x3FF00000L
++//OTG4_OTG_BLANK_DATA_COLOR_EXT
++#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT                                0x0
++#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT                                0x8
++#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT                                 0x10
++#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK                                  0x0000003FL
++#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK                                  0x00003F00L
++#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK                                   0x003F0000L
++//OTG4_OTG_BLACK_COLOR
++#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT                                                     0x0
++#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT                                                      0xa
++#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT                                                     0x14
++#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK                                                       0x000003FFL
++#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK                                                        0x000FFC00L
++#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK                                                       0x3FF00000L
++//OTG4_OTG_BLACK_COLOR_EXT
++#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT                                             0x0
++#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT                                              0x8
++#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT                                             0x10
++#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK                                               0x0000003FL
++#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK                                                0x00003F00L
++#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK                                               0x003F0000L
++//OTG4_OTG_VERTICAL_INTERRUPT0_POSITION
++#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
++#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
++#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
++#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
++//OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL
++#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
++#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
++#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
++#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
++#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
++#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
++#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
++#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
++#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
++#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
++#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
++#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
++//OTG4_OTG_VERTICAL_INTERRUPT1_POSITION
++#define OTG4_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
++#define OTG4_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
++//OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL
++#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
++#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
++#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
++#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
++#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
++#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
++#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
++#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
++#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
++#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
++//OTG4_OTG_VERTICAL_INTERRUPT2_POSITION
++#define OTG4_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
++#define OTG4_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
++//OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL
++#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
++#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
++#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
++#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
++#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
++#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
++#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
++#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
++#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
++#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
++//OTG4_OTG_CRC_CNTL
++#define OTG4_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
++#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
++#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
++#define OTG4_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
++#define OTG4_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
++#define OTG4_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
++#define OTG4_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
++#define OTG4_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
++#define OTG4_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
++#define OTG4_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
++#define OTG4_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
++#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
++#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
++#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
++#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
++#define OTG4_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
++#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
++#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
++#define OTG4_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
++#define OTG4_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
++#define OTG4_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
++#define OTG4_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
++#define OTG4_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
++#define OTG4_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
++#define OTG4_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
++#define OTG4_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
++#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
++#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
++#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
++#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
++//OTG4_OTG_CRC_CNTL2
++#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
++#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
++#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
++#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
++#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
++#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
++#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
++#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
++//OTG4_OTG_CRC0_WINDOWA_X_CONTROL
++#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
++#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
++#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
++#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
++//OTG4_OTG_CRC0_WINDOWA_Y_CONTROL
++#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
++#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
++#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
++#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
++//OTG4_OTG_CRC0_WINDOWB_X_CONTROL
++#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
++#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
++#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
++#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
++//OTG4_OTG_CRC0_WINDOWB_Y_CONTROL
++#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
++#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
++#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
++#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
++//OTG4_OTG_CRC0_DATA_RG
++#define OTG4_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
++#define OTG4_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
++#define OTG4_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG4_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
++//OTG4_OTG_CRC0_DATA_B
++#define OTG4_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
++#define OTG4_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
++#define OTG4_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG4_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
++//OTG4_OTG_CRC1_WINDOWA_X_CONTROL
++#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
++#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
++#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
++#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
++//OTG4_OTG_CRC1_WINDOWA_Y_CONTROL
++#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
++#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
++#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
++#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
++//OTG4_OTG_CRC1_WINDOWB_X_CONTROL
++#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
++#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
++#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
++#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
++//OTG4_OTG_CRC1_WINDOWB_Y_CONTROL
++#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
++#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
++#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
++#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
++//OTG4_OTG_CRC1_DATA_RG
++#define OTG4_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
++#define OTG4_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
++#define OTG4_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG4_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
++//OTG4_OTG_CRC1_DATA_B
++#define OTG4_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
++#define OTG4_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
++#define OTG4_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG4_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
++//OTG4_OTG_CRC2_DATA_RG
++#define OTG4_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
++#define OTG4_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
++#define OTG4_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG4_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
++//OTG4_OTG_CRC2_DATA_B
++#define OTG4_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
++#define OTG4_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
++#define OTG4_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG4_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
++//OTG4_OTG_CRC3_DATA_RG
++#define OTG4_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
++#define OTG4_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
++#define OTG4_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG4_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
++//OTG4_OTG_CRC3_DATA_B
++#define OTG4_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
++#define OTG4_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
++#define OTG4_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG4_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
++//OTG4_OTG_CRC_SIG_RED_GREEN_MASK
++#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
++#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
++#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
++#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
++//OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK
++#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
++#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
++#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
++#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
++//OTG4_OTG_STATIC_SCREEN_CONTROL
++#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
++#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
++#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
++#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
++#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
++#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
++#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
++#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
++#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
++#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
++#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
++#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
++#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
++#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
++#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
++#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
++#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
++#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
++//OTG4_OTG_3D_STRUCTURE_CONTROL
++#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
++#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
++#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
++#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
++#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
++#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
++#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
++#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
++#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
++#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
++#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
++#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
++//OTG4_OTG_GSL_VSYNC_GAP
++#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
++#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
++#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
++#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
++#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
++#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
++#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
++#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
++#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
++#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
++#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
++#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
++#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
++#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
++#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
++#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
++//OTG4_OTG_MASTER_UPDATE_MODE
++#define OTG4_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
++#define OTG4_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
++//OTG4_OTG_CLOCK_CONTROL
++#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
++#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
++#define OTG4_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
++#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
++#define OTG4_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
++#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
++#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
++#define OTG4_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
++#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
++#define OTG4_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
++//OTG4_OTG_VSTARTUP_PARAM
++#define OTG4_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
++#define OTG4_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
++//OTG4_OTG_VUPDATE_PARAM
++#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
++#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
++#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
++#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
++//OTG4_OTG_VREADY_PARAM
++#define OTG4_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
++#define OTG4_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
++//OTG4_OTG_GLOBAL_SYNC_STATUS
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
++#define OTG4_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
++//OTG4_OTG_MASTER_UPDATE_LOCK
++#define OTG4_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
++#define OTG4_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
++#define OTG4_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
++#define OTG4_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
++//OTG4_OTG_GSL_CONTROL
++#define OTG4_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
++#define OTG4_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
++#define OTG4_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
++#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
++#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
++#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
++#define OTG4_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
++#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
++#define OTG4_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
++#define OTG4_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
++#define OTG4_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
++#define OTG4_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
++#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
++#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
++#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
++#define OTG4_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
++#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
++#define OTG4_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
++//OTG4_OTG_GSL_WINDOW_X
++#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
++#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
++#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
++#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
++//OTG4_OTG_GSL_WINDOW_Y
++#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
++#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
++#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
++#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
++//OTG4_OTG_VUPDATE_KEEPOUT
++#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
++#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
++#define OTG4_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
++#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
++#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
++#define OTG4_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
++//OTG4_OTG_GLOBAL_CONTROL0
++#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT                                0x0
++#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT                             0x8
++#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
++#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK                                  0x000000FFL
++#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK                               0x00000100L
++#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
++//OTG4_OTG_GLOBAL_CONTROL1
++#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT                                              0x0
++#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT                                              0x10
++#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
++#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK                                                0x00007FFFL
++#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK                                                0x7FFF0000L
++#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
++//OTG4_OTG_GLOBAL_CONTROL2
++#define OTG4_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT                                                  0x0
++#define OTG4_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
++#define OTG4_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
++#define OTG4_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT                                        0x1d
++#define OTG4_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
++#define OTG4_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
++#define OTG4_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK                                                    0x000003FFL
++#define OTG4_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
++#define OTG4_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
++#define OTG4_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK                                          0x20000000L
++#define OTG4_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
++#define OTG4_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
++//OTG4_OTG_GLOBAL_CONTROL3
++#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
++#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
++#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT                          0x8
++#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
++#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
++#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK                            0x00000100L
++//OTG4_OTG_TRIG_MANUAL_CONTROL
++#define OTG4_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
++#define OTG4_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
++//OTG4_OTG_MANUAL_FLOW_CONTROL
++#define OTG4_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
++#define OTG4_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
++//OTG4_OTG_RANGE_TIMING_INT_STATUS
++#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                             0x0
++#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT                         0x4
++#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                       0x8
++#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                     0xc
++#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                    0x10
++#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK                               0x00000001L
++#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK                           0x00000010L
++#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK                         0x00000100L
++#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                       0x00001000L
++#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                      0x00010000L
++//OTG4_OTG_DRR_CONTROL
++#define OTG4_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
++#define OTG4_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
++#define OTG4_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000007L
++#define OTG4_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
++//OTG4_OTG_REQUEST_CONTROL
++#define OTG4_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
++#define OTG4_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
++//OTG4_OTG_DSC_START_POSITION
++#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
++#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
++#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
++#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
++//OTG4_OTG_PIPE_UPDATE_STATUS
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT                                                    0x1
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT                                              0x2
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT                                           0x5
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT                                     0x6
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT                                           0x9
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT                                     0xa
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK                                                      0x00000002L
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK                                                0x00000004L
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK                                             0x00000020L
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK                                       0x00000040L
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK                                             0x00000200L
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK                                       0x00000400L
++#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
++//OTG4_OTG_SPARE_REGISTER
++#define OTG4_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
++#define OTG4_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_optc_otg5_dispdec
++//OTG5_OTG_H_TOTAL
++#define OTG5_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
++#define OTG5_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
++//OTG5_OTG_H_BLANK_START_END
++#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
++#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
++#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
++#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
++//OTG5_OTG_H_SYNC_A
++#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
++#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
++#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
++#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
++//OTG5_OTG_H_SYNC_A_CNTL
++#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
++#define OTG5_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
++#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
++#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
++#define OTG5_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
++#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
++//OTG5_OTG_H_TIMING_CNTL
++#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT                                                   0x0
++#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT                                       0x8
++#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK                                                     0x00000001L
++#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK                                         0x00000100L
++//OTG5_OTG_V_TOTAL
++#define OTG5_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
++#define OTG5_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
++//OTG5_OTG_V_TOTAL_MIN
++#define OTG5_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
++#define OTG5_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
++//OTG5_OTG_V_TOTAL_MAX
++#define OTG5_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
++#define OTG5_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
++//OTG5_OTG_V_TOTAL_MID
++#define OTG5_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
++#define OTG5_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
++//OTG5_OTG_V_TOTAL_CONTROL
++#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
++#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
++#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
++#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
++#define OTG5_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
++#define OTG5_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
++#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT                                          0x7
++#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
++#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
++#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
++#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
++#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
++#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
++#define OTG5_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
++#define OTG5_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
++#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK                                            0x00000080L
++#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
++#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
++//OTG5_OTG_V_TOTAL_INT_STATUS
++#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
++#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
++#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
++#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
++#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
++#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
++#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
++#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
++//OTG5_OTG_VSYNC_NOM_INT_STATUS
++#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
++#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
++#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
++#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
++//OTG5_OTG_V_BLANK_START_END
++#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
++#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
++#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
++#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
++//OTG5_OTG_V_SYNC_A
++#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
++#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
++#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
++#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
++//OTG5_OTG_V_SYNC_A_CNTL
++#define OTG5_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
++#define OTG5_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
++//OTG5_OTG_TRIGA_CNTL
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
++#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
++//OTG5_OTG_TRIGA_MANUAL_TRIG
++#define OTG5_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
++#define OTG5_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
++//OTG5_OTG_TRIGB_CNTL
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
++#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
++//OTG5_OTG_TRIGB_MANUAL_TRIG
++#define OTG5_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
++#define OTG5_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
++//OTG5_OTG_FORCE_COUNT_NOW_CNTL
++#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
++#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
++#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
++#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
++#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
++#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
++#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
++#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
++#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
++#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
++//OTG5_OTG_FLOW_CONTROL
++#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
++#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
++#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
++#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
++#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
++#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
++#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
++#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
++//OTG5_OTG_STEREO_FORCE_NEXT_EYE
++#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
++#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT                                       0x8
++#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT                                        0x10
++#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
++#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK                                         0x0000FF00L
++#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK                                          0x1FFF0000L
++//OTG5_OTG_CONTROL
++#define OTG5_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
++#define OTG5_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
++#define OTG5_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
++#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
++#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
++#define OTG5_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
++#define OTG5_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT                                                0x18
++#define OTG5_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT                                                     0x1e
++#define OTG5_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT                                                0x1f
++#define OTG5_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
++#define OTG5_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
++#define OTG5_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
++#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
++#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
++#define OTG5_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
++#define OTG5_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK                                                  0x01000000L
++#define OTG5_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK                                                       0x40000000L
++#define OTG5_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK                                                  0x80000000L
++//OTG5_OTG_BLANK_CONTROL
++#define OTG5_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT                                                0x0
++#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT                                                      0x8
++#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT                                                      0x10
++#define OTG5_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK                                                  0x00000001L
++#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK                                                        0x00000100L
++#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK                                                        0x00010000L
++//OTG5_OTG_PIPE_ABORT_CONTROL
++#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT                                                    0x0
++#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT                                               0x8
++#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK                                                      0x00000001L
++#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK                                                 0x00000100L
++//OTG5_OTG_INTERLACE_CONTROL
++#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
++#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
++#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
++#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
++//OTG5_OTG_INTERLACE_STATUS
++#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
++#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
++#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
++#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
++//OTG5_OTG_PIXEL_DATA_READBACK0
++#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
++#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
++#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
++#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
++//OTG5_OTG_PIXEL_DATA_READBACK1
++#define OTG5_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
++#define OTG5_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
++//OTG5_OTG_STATUS
++#define OTG5_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
++#define OTG5_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
++#define OTG5_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
++#define OTG5_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
++#define OTG5_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
++#define OTG5_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
++#define OTG5_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
++#define OTG5_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
++#define OTG5_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
++#define OTG5_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
++#define OTG5_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
++#define OTG5_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
++#define OTG5_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
++#define OTG5_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
++#define OTG5_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
++#define OTG5_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
++//OTG5_OTG_STATUS_POSITION
++#define OTG5_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
++#define OTG5_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
++#define OTG5_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
++#define OTG5_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
++//OTG5_OTG_NOM_VERT_POSITION
++#define OTG5_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
++#define OTG5_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
++//OTG5_OTG_STATUS_FRAME_COUNT
++#define OTG5_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
++#define OTG5_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
++//OTG5_OTG_STATUS_VF_COUNT
++#define OTG5_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
++#define OTG5_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
++//OTG5_OTG_STATUS_HV_COUNT
++#define OTG5_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
++#define OTG5_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
++//OTG5_OTG_COUNT_CONTROL
++#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
++#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
++#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
++#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
++//OTG5_OTG_COUNT_RESET
++#define OTG5_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
++#define OTG5_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
++//OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
++#define OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
++#define OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
++//OTG5_OTG_VERT_SYNC_CONTROL
++#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
++#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
++#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
++#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
++#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
++#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
++//OTG5_OTG_STEREO_STATUS
++#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
++#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
++#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
++#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
++#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
++#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
++#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
++#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
++#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
++#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
++#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
++#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
++#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
++#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
++//OTG5_OTG_STEREO_CONTROL
++#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
++#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
++#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
++#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
++#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
++#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
++#define OTG5_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
++#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
++#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
++#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
++#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
++#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
++#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
++#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
++#define OTG5_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
++#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
++//OTG5_OTG_SNAPSHOT_STATUS
++#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
++#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
++#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
++#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
++#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
++#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
++//OTG5_OTG_SNAPSHOT_CONTROL
++#define OTG5_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
++#define OTG5_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
++//OTG5_OTG_SNAPSHOT_POSITION
++#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
++#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
++#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
++#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
++//OTG5_OTG_SNAPSHOT_FRAME
++#define OTG5_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
++#define OTG5_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
++//OTG5_OTG_INTERRUPT_CONTROL
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
++#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
++//OTG5_OTG_UPDATE_LOCK
++#define OTG5_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
++#define OTG5_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
++//OTG5_OTG_DOUBLE_BUFFER_CONTROL
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT                         0x2
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT                               0x3
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT                           0x4
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT                                0x10
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT                              0x18
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK                           0x00000004L
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK                                 0x00000008L
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK                             0x00000010L
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK                                  0x00010000L
++#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK                                0x03000000L
++//OTG5_OTG_MASTER_EN
++#define OTG5_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
++#define OTG5_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
++//OTG5_OTG_BLANK_DATA_COLOR
++#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT                                        0x0
++#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT                                        0xa
++#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT                                         0x14
++#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK                                          0x000003FFL
++#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK                                          0x000FFC00L
++#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK                                           0x3FF00000L
++//OTG5_OTG_BLANK_DATA_COLOR_EXT
++#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT                                0x0
++#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT                                0x8
++#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT                                 0x10
++#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK                                  0x0000003FL
++#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK                                  0x00003F00L
++#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK                                   0x003F0000L
++//OTG5_OTG_BLACK_COLOR
++#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT                                                     0x0
++#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT                                                      0xa
++#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT                                                     0x14
++#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK                                                       0x000003FFL
++#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK                                                        0x000FFC00L
++#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK                                                       0x3FF00000L
++//OTG5_OTG_BLACK_COLOR_EXT
++#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT                                             0x0
++#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT                                              0x8
++#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT                                             0x10
++#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK                                               0x0000003FL
++#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK                                                0x00003F00L
++#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK                                               0x003F0000L
++//OTG5_OTG_VERTICAL_INTERRUPT0_POSITION
++#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
++#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
++#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
++#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
++//OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL
++#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
++#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
++#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
++#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
++#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
++#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
++#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
++#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
++#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
++#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
++#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
++#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
++//OTG5_OTG_VERTICAL_INTERRUPT1_POSITION
++#define OTG5_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
++#define OTG5_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
++//OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL
++#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
++#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
++#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
++#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
++#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
++#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
++#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
++#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
++#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
++#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
++//OTG5_OTG_VERTICAL_INTERRUPT2_POSITION
++#define OTG5_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
++#define OTG5_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
++//OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL
++#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
++#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
++#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
++#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
++#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
++#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
++#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
++#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
++#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
++#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
++//OTG5_OTG_CRC_CNTL
++#define OTG5_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
++#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
++#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
++#define OTG5_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
++#define OTG5_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
++#define OTG5_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
++#define OTG5_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
++#define OTG5_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
++#define OTG5_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
++#define OTG5_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
++#define OTG5_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
++#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
++#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
++#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
++#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
++#define OTG5_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
++#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
++#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
++#define OTG5_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
++#define OTG5_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
++#define OTG5_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
++#define OTG5_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
++#define OTG5_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
++#define OTG5_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
++#define OTG5_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
++#define OTG5_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
++#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
++#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
++#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
++#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
++//OTG5_OTG_CRC_CNTL2
++#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
++#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
++#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
++#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
++#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
++#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
++#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
++#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
++//OTG5_OTG_CRC0_WINDOWA_X_CONTROL
++#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
++#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
++#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
++#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
++//OTG5_OTG_CRC0_WINDOWA_Y_CONTROL
++#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
++#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
++#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
++#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
++//OTG5_OTG_CRC0_WINDOWB_X_CONTROL
++#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
++#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
++#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
++#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
++//OTG5_OTG_CRC0_WINDOWB_Y_CONTROL
++#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
++#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
++#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
++#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
++//OTG5_OTG_CRC0_DATA_RG
++#define OTG5_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
++#define OTG5_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
++#define OTG5_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG5_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
++//OTG5_OTG_CRC0_DATA_B
++#define OTG5_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
++#define OTG5_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
++#define OTG5_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG5_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
++//OTG5_OTG_CRC1_WINDOWA_X_CONTROL
++#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
++#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
++#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
++#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
++//OTG5_OTG_CRC1_WINDOWA_Y_CONTROL
++#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
++#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
++#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
++#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
++//OTG5_OTG_CRC1_WINDOWB_X_CONTROL
++#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
++#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
++#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
++#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
++//OTG5_OTG_CRC1_WINDOWB_Y_CONTROL
++#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
++#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
++#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
++#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
++//OTG5_OTG_CRC1_DATA_RG
++#define OTG5_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
++#define OTG5_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
++#define OTG5_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG5_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
++//OTG5_OTG_CRC1_DATA_B
++#define OTG5_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
++#define OTG5_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
++#define OTG5_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG5_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
++//OTG5_OTG_CRC2_DATA_RG
++#define OTG5_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
++#define OTG5_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
++#define OTG5_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG5_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
++//OTG5_OTG_CRC2_DATA_B
++#define OTG5_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
++#define OTG5_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
++#define OTG5_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG5_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
++//OTG5_OTG_CRC3_DATA_RG
++#define OTG5_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
++#define OTG5_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
++#define OTG5_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
++#define OTG5_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
++//OTG5_OTG_CRC3_DATA_B
++#define OTG5_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
++#define OTG5_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
++#define OTG5_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
++#define OTG5_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
++//OTG5_OTG_CRC_SIG_RED_GREEN_MASK
++#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
++#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
++#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
++#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
++//OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK
++#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
++#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
++#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
++#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
++//OTG5_OTG_STATIC_SCREEN_CONTROL
++#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
++#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
++#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
++#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
++#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
++#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
++#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
++#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
++#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
++#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
++#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
++#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
++#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
++#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
++#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
++#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
++#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
++#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
++//OTG5_OTG_3D_STRUCTURE_CONTROL
++#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
++#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
++#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
++#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
++#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
++#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
++#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
++#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
++#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
++#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
++#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
++#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
++//OTG5_OTG_GSL_VSYNC_GAP
++#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
++#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
++#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
++#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
++#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
++#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
++#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
++#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
++#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
++#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
++#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
++#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
++#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
++#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
++#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
++#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
++//OTG5_OTG_MASTER_UPDATE_MODE
++#define OTG5_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
++#define OTG5_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
++//OTG5_OTG_CLOCK_CONTROL
++#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
++#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
++#define OTG5_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
++#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
++#define OTG5_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
++#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
++#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
++#define OTG5_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
++#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
++#define OTG5_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
++//OTG5_OTG_VSTARTUP_PARAM
++#define OTG5_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
++#define OTG5_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
++//OTG5_OTG_VUPDATE_PARAM
++#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
++#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
++#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
++#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
++//OTG5_OTG_VREADY_PARAM
++#define OTG5_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
++#define OTG5_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
++//OTG5_OTG_GLOBAL_SYNC_STATUS
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
++#define OTG5_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
++//OTG5_OTG_MASTER_UPDATE_LOCK
++#define OTG5_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
++#define OTG5_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
++#define OTG5_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
++#define OTG5_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
++//OTG5_OTG_GSL_CONTROL
++#define OTG5_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
++#define OTG5_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
++#define OTG5_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
++#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
++#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
++#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
++#define OTG5_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
++#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
++#define OTG5_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
++#define OTG5_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
++#define OTG5_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
++#define OTG5_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
++#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
++#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
++#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
++#define OTG5_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
++#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
++#define OTG5_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
++//OTG5_OTG_GSL_WINDOW_X
++#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
++#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
++#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
++#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
++//OTG5_OTG_GSL_WINDOW_Y
++#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
++#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
++#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
++#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
++//OTG5_OTG_VUPDATE_KEEPOUT
++#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
++#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
++#define OTG5_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
++#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
++#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
++#define OTG5_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
++//OTG5_OTG_GLOBAL_CONTROL0
++#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT                                0x0
++#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT                             0x8
++#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
++#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK                                  0x000000FFL
++#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK                               0x00000100L
++#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
++//OTG5_OTG_GLOBAL_CONTROL1
++#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT                                              0x0
++#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT                                              0x10
++#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
++#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK                                                0x00007FFFL
++#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK                                                0x7FFF0000L
++#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
++//OTG5_OTG_GLOBAL_CONTROL2
++#define OTG5_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT                                                  0x0
++#define OTG5_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
++#define OTG5_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
++#define OTG5_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT                                        0x1d
++#define OTG5_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
++#define OTG5_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
++#define OTG5_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK                                                    0x000003FFL
++#define OTG5_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
++#define OTG5_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
++#define OTG5_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK                                          0x20000000L
++#define OTG5_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
++#define OTG5_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
++//OTG5_OTG_GLOBAL_CONTROL3
++#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
++#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
++#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT                          0x8
++#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
++#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
++#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK                            0x00000100L
++//OTG5_OTG_TRIG_MANUAL_CONTROL
++#define OTG5_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
++#define OTG5_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
++//OTG5_OTG_MANUAL_FLOW_CONTROL
++#define OTG5_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
++#define OTG5_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
++//OTG5_OTG_RANGE_TIMING_INT_STATUS
++#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                             0x0
++#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT                         0x4
++#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                       0x8
++#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                     0xc
++#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                    0x10
++#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK                               0x00000001L
++#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK                           0x00000010L
++#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK                         0x00000100L
++#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                       0x00001000L
++#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                      0x00010000L
++//OTG5_OTG_DRR_CONTROL
++#define OTG5_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
++#define OTG5_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
++#define OTG5_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000007L
++#define OTG5_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
++//OTG5_OTG_REQUEST_CONTROL
++#define OTG5_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
++#define OTG5_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
++//OTG5_OTG_DSC_START_POSITION
++#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
++#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
++#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
++#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
++//OTG5_OTG_PIPE_UPDATE_STATUS
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT                                                    0x1
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT                                              0x2
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT                                           0x5
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT                                     0x6
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT                                           0x9
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT                                     0xa
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK                                                      0x00000002L
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK                                                0x00000004L
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK                                             0x00000020L
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK                                       0x00000040L
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK                                             0x00000200L
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK                                       0x00000400L
++#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
++//OTG5_OTG_SPARE_REGISTER
++#define OTG5_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
++#define OTG5_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_optc_optc_misc_dispdec
++//DWB_SOURCE_SELECT
++#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT__SHIFT                                                     0x0
++#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT__SHIFT                                                     0x3
++#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT__SHIFT                                                     0x6
++#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT_MASK                                                       0x00000007L
++#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT_MASK                                                       0x00000038L
++#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT_MASK                                                       0x000001C0L
++//GSL_SOURCE_SELECT
++#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT                                                       0x0
++#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT                                                       0x4
++#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT                                                       0x8
++#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT                                                         0x10
++#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK                                                         0x00000007L
++#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK                                                         0x00000070L
++#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK                                                         0x00000700L
++#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK                                                           0x00070000L
++//OPTC_CLOCK_CONTROL
++#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0
++#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT                                                    0x1
++#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT                                                          0x8
++#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L
++#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK                                                      0x00000002L
++#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK                                                            0x00000F00L
++//ODM_MEM_PWR_CTRL
++#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT                                                           0x0
++#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT                                                             0x2
++#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT                                                           0x4
++#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT                                                             0x6
++#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT                                                           0x8
++#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT                                                             0xa
++#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT                                                           0xc
++#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT                                                             0xe
++#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT                                                           0x10
++#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT                                                             0x12
++#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT                                                           0x14
++#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT                                                             0x16
++#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT                                                           0x18
++#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT                                                             0x1a
++#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT                                                           0x1c
++#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT                                                             0x1e
++#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK                                                             0x00000003L
++#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK                                                               0x00000004L
++#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK                                                             0x00000030L
++#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK                                                               0x00000040L
++#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK                                                             0x00000300L
++#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK                                                               0x00000400L
++#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK                                                             0x00003000L
++#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK                                                               0x00004000L
++#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK                                                             0x00030000L
++#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK                                                               0x00040000L
++#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK                                                             0x00300000L
++#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK                                                               0x00400000L
++#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK                                                             0x03000000L
++#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK                                                               0x04000000L
++#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK                                                             0x30000000L
++#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK                                                               0x40000000L
++//ODM_MEM_PWR_CTRL2
++#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_FORCE__SHIFT                                                          0x0
++#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_DIS__SHIFT                                                            0x2
++#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_FORCE__SHIFT                                                          0x4
++#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_DIS__SHIFT                                                            0x6
++#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_FORCE__SHIFT                                                         0x8
++#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_DIS__SHIFT                                                           0xa
++#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_FORCE__SHIFT                                                         0xc
++#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_DIS__SHIFT                                                           0xe
++#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_FORCE_MASK                                                            0x00000003L
++#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_DIS_MASK                                                              0x00000004L
++#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_FORCE_MASK                                                            0x00000030L
++#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_DIS_MASK                                                              0x00000040L
++#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_FORCE_MASK                                                           0x00000300L
++#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_DIS_MASK                                                             0x00000400L
++#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_FORCE_MASK                                                           0x00003000L
++#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_DIS_MASK                                                             0x00004000L
++//ODM_MEM_PWR_CTRL3
++#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT                                                 0x0
++#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT                                                     0x2
++#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK                                                   0x00000003L
++#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK                                                       0x0000000CL
++//ODM_MEM_PWR_STATUS
++#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT                                                         0x0
++#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT                                                         0x2
++#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT                                                         0x4
++#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT                                                         0x6
++#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT                                                         0x8
++#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT                                                         0xa
++#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT                                                         0xc
++#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT                                                         0xe
++#define ODM_MEM_PWR_STATUS__ODM_MEM8_PWR_STATE__SHIFT                                                         0x10
++#define ODM_MEM_PWR_STATUS__ODM_MEM9_PWR_STATE__SHIFT                                                         0x12
++#define ODM_MEM_PWR_STATUS__ODM_MEM10_PWR_STATE__SHIFT                                                        0x14
++#define ODM_MEM_PWR_STATUS__ODM_MEM11_PWR_STATE__SHIFT                                                        0x16
++#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK                                                           0x00000003L
++#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK                                                           0x0000000CL
++#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK                                                           0x00000030L
++#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK                                                           0x000000C0L
++#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK                                                           0x00000300L
++#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK                                                           0x00000C00L
++#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK                                                           0x00003000L
++#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK                                                           0x0000C000L
++#define ODM_MEM_PWR_STATUS__ODM_MEM8_PWR_STATE_MASK                                                           0x00030000L
++#define ODM_MEM_PWR_STATUS__ODM_MEM9_PWR_STATE_MASK                                                           0x000C0000L
++#define ODM_MEM_PWR_STATUS__ODM_MEM10_PWR_STATE_MASK                                                          0x00300000L
++#define ODM_MEM_PWR_STATUS__ODM_MEM11_PWR_STATE_MASK                                                          0x00C00000L
++//OPTC_MISC_SPARE_REGISTER
++#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT                                                  0x0
++#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK                                                    0x000000FFL
++
++
++// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON17_PERFCOUNTER_CNTL
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
++#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
++//DC_PERFMON17_PERFCOUNTER_CNTL2
++#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
++#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
++#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
++#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
++#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
++#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
++#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
++#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
++#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
++#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
++//DC_PERFMON17_PERFCOUNTER_STATE
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
++#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
++//DC_PERFMON17_PERFMON_CNTL
++#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
++#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
++#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
++#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
++#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
++#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
++#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
++#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
++#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
++#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
++#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
++#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
++//DC_PERFMON17_PERFMON_CNTL2
++#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
++#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
++#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
++#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
++#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
++#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
++#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
++#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
++//DC_PERFMON17_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
++#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
++//DC_PERFMON17_PERFMON_CVALUE_LOW
++#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
++#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
++//DC_PERFMON17_PERFMON_HI
++#define DC_PERFMON17_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
++#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
++#define DC_PERFMON17_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
++#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
++//DC_PERFMON17_PERFMON_LOW
++#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
++#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dio_dout_i2c_dispdec
++//DC_I2C_CONTROL
++#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT                                                                      0x0
++#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT                                                              0x1
++#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT                                                              0x2
++#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT                                                         0x3
++#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT                                                              0x8
++#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT                                                       0x14
++#define DC_I2C_CONTROL__DC_I2C_GO_MASK                                                                        0x00000001L
++#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK                                                                0x00000002L
++#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK                                                                0x00000004L
++#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK                                                           0x00000008L
++#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK                                                                0x00000700L
++#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK                                                         0x00300000L
++//DC_I2C_ARBITRATION
++#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT                                                         0x0
++#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT                                                  0x2
++#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT                                                     0x4
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT                                                       0x8
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT                                                       0xc
++#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT                                                  0x14
++#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT                                               0x15
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT                                                0x18
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT                                             0x19
++#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK                                                           0x00000003L
++#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK                                                    0x0000000CL
++#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK                                                       0x00000010L
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK                                                         0x00000100L
++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK                                                         0x00001000L
++#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK                                                    0x00100000L
++#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK                                                 0x00200000L
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK                                                  0x01000000L
++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK                                               0x02000000L
++//DC_I2C_INTERRUPT_CONTROL
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT                                                   0x0
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT                                                   0x1
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT                                                  0x2
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT                                              0x4
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT                                              0x5
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT                                             0x6
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT                                              0x8
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT                                              0x9
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT                                             0xa
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT                                              0xc
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT                                              0xd
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT                                             0xe
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT                                              0x10
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT                                              0x11
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT                                             0x12
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT                                              0x14
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT                                              0x15
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT                                             0x16
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT                                              0x18
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT                                              0x19
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT                                             0x1a
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT                                            0x1b
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT                                            0x1c
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT                                           0x1d
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK                                                     0x00000001L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK                                                     0x00000002L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK                                                    0x00000004L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK                                                0x00000010L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK                                                0x00000020L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK                                               0x00000040L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK                                                0x00000100L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK                                                0x00000200L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK                                               0x00000400L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK                                                0x00001000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK                                                0x00002000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK                                               0x00004000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK                                                0x00010000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK                                                0x00020000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK                                               0x00040000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK                                                0x00100000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK                                                0x00200000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK                                               0x00400000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK                                                0x01000000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK                                                0x02000000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK                                               0x04000000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK                                              0x08000000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK                                              0x10000000L
++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK                                             0x20000000L
++//DC_I2C_SW_STATUS
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT                                                             0x0
++#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT                                                               0x2
++#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT                                                            0x4
++#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT                                                            0x5
++#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT                                                        0x6
++#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT                                                    0x7
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT                                                    0x8
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT                                                              0xc
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT                                                              0xd
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT                                                              0xe
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT                                                              0xf
++#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT                                                                0x12
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK                                                               0x00000003L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK                                                                 0x00000004L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK                                                              0x00000010L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK                                                              0x00000020L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK                                                          0x00000040L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK                                                      0x00000080L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK                                                      0x00000100L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK                                                                0x00001000L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK                                                                0x00002000L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK                                                                0x00004000L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK                                                                0x00008000L
++#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK                                                                  0x00040000L
++//DC_I2C_DDC1_HW_STATUS
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT                                                   0x0
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT                                                     0x3
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT                                                      0x10
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT                                                      0x11
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT                                          0x14
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT                                           0x1c
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK                                                     0x00000003L
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK                                                       0x00000008L
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK                                                        0x00010000L
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK                                                        0x00020000L
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK                                            0x00100000L
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK                                             0x70000000L
++//DC_I2C_DDC2_HW_STATUS
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT                                                   0x0
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT                                                     0x3
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT                                                      0x10
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT                                                      0x11
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT                                          0x14
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT                                           0x1c
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK                                                     0x00000003L
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK                                                       0x00000008L
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK                                                        0x00010000L
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK                                                        0x00020000L
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK                                            0x00100000L
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK                                             0x70000000L
++//DC_I2C_DDC3_HW_STATUS
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT                                                   0x0
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT                                                     0x3
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT                                                      0x10
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT                                                      0x11
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT                                          0x14
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT                                           0x1c
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK                                                     0x00000003L
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK                                                       0x00000008L
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK                                                        0x00010000L
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK                                                        0x00020000L
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK                                            0x00100000L
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK                                             0x70000000L
++//DC_I2C_DDC4_HW_STATUS
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT                                                   0x0
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT                                                     0x3
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT                                                      0x10
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT                                                      0x11
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT                                          0x14
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT                                           0x1c
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK                                                     0x00000003L
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK                                                       0x00000008L
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK                                                        0x00010000L
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK                                                        0x00020000L
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK                                            0x00100000L
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK                                             0x70000000L
++//DC_I2C_DDC5_HW_STATUS
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT                                                   0x0
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT                                                     0x3
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT                                                      0x10
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT                                                      0x11
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT                                          0x14
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT                                           0x1c
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK                                                     0x00000003L
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK                                                       0x00000008L
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK                                                        0x00010000L
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK                                                        0x00020000L
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK                                            0x00100000L
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK                                             0x70000000L
++//DC_I2C_DDC1_SPEED
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT                                                       0x0
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT                                          0x8
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT                                                        0x10
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK                                                         0x00000003L
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK                                                          0xFFFF0000L
++//DC_I2C_DDC1_SETUP
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT                                                   0x0
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT                                                  0x1
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT                                               0x2
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT                                              0x4
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT                                                0x5
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT                                                          0x6
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT                                                    0x7
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT                                                0x8
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT                                                      0x18
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK                                                     0x00000001L
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK                                                    0x00000002L
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK                                                 0x00000004L
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK                                                0x00000010L
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK                                                  0x00000020L
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK                                                            0x00000040L
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK                                                      0x00000080L
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK                                                        0xFF000000L
++//DC_I2C_DDC2_SPEED
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT                                                       0x0
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT                                          0x8
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT                                                        0x10
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK                                                         0x00000003L
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK                                                          0xFFFF0000L
++//DC_I2C_DDC2_SETUP
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT                                                   0x0
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT                                                  0x1
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT                                               0x2
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT                                              0x4
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT                                                0x5
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT                                                          0x6
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT                                                    0x7
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT                                                0x8
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT                                                      0x18
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK                                                     0x00000001L
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK                                                    0x00000002L
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK                                                 0x00000004L
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK                                                0x00000010L
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK                                                  0x00000020L
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK                                                            0x00000040L
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK                                                      0x00000080L
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK                                                        0xFF000000L
++//DC_I2C_DDC3_SPEED
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT                                                       0x0
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT                                          0x8
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT                                                        0x10
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK                                                         0x00000003L
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK                                                          0xFFFF0000L
++//DC_I2C_DDC3_SETUP
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT                                                   0x0
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT                                                  0x1
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT                                               0x2
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT                                              0x4
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT                                                0x5
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT                                                          0x6
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT                                                    0x7
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT                                                0x8
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT                                                      0x18
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK                                                     0x00000001L
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK                                                    0x00000002L
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK                                                 0x00000004L
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK                                                0x00000010L
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK                                                  0x00000020L
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK                                                            0x00000040L
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK                                                      0x00000080L
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK                                                        0xFF000000L
++//DC_I2C_DDC4_SPEED
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT                                                       0x0
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT                                          0x8
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT                                                        0x10
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK                                                         0x00000003L
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK                                                          0xFFFF0000L
++//DC_I2C_DDC4_SETUP
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT                                                   0x0
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT                                                  0x1
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT                                               0x2
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT                                              0x4
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT                                                0x5
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT                                                          0x6
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT                                                    0x7
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT                                                0x8
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT                                                      0x18
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK                                                     0x00000001L
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK                                                    0x00000002L
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK                                                 0x00000004L
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK                                                0x00000010L
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK                                                  0x00000020L
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK                                                            0x00000040L
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK                                                      0x00000080L
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK                                                        0xFF000000L
++//DC_I2C_DDC5_SPEED
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT                                                       0x0
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT                                          0x8
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT                                                        0x10
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK                                                         0x00000003L
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK                                                          0xFFFF0000L
++//DC_I2C_DDC5_SETUP
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT                                                   0x0
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT                                                  0x1
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT                                               0x2
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT                                              0x4
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT                                                0x5
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT                                                          0x6
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT                                                    0x7
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT                                                0x8
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT                                                      0x18
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK                                                     0x00000001L
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK                                                    0x00000002L
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK                                                 0x00000004L
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK                                                0x00000010L
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK                                                  0x00000020L
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK                                                            0x00000040L
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK                                                      0x00000080L
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK                                                        0xFF000000L
++//DC_I2C_TRANSACTION0
++#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT                                                                0x0
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT                                                      0x8
++#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT                                                             0xc
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT                                                              0xd
++#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT                                                             0x10
++#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK                                                                  0x00000001L
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK                                                        0x00000100L
++#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK                                                               0x00001000L
++#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK                                                                0x00002000L
++#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK                                                               0x03FF0000L
++//DC_I2C_TRANSACTION1
++#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT                                                                0x0
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT                                                      0x8
++#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT                                                             0xc
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT                                                              0xd
++#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT                                                             0x10
++#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK                                                                  0x00000001L
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK                                                        0x00000100L
++#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK                                                               0x00001000L
++#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK                                                                0x00002000L
++#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK                                                               0x03FF0000L
++//DC_I2C_TRANSACTION2
++#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT                                                                0x0
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT                                                      0x8
++#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT                                                             0xc
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT                                                              0xd
++#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT                                                             0x10
++#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK                                                                  0x00000001L
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK                                                        0x00000100L
++#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK                                                               0x00001000L
++#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK                                                                0x00002000L
++#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK                                                               0x03FF0000L
++//DC_I2C_TRANSACTION3
++#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT                                                                0x0
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT                                                      0x8
++#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT                                                             0xc
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT                                                              0xd
++#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT                                                             0x10
++#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK                                                                  0x00000001L
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK                                                        0x00000100L
++#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK                                                               0x00001000L
++#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK                                                                0x00002000L
++#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK                                                               0x03FF0000L
++//DC_I2C_DATA
++#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT                                                                    0x0
++#define DC_I2C_DATA__DC_I2C_DATA__SHIFT                                                                       0x8
++#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT                                                                      0x10
++#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT                                                                0x1f
++#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK                                                                      0x00000001L
++#define DC_I2C_DATA__DC_I2C_DATA_MASK                                                                         0x0000FF00L
++#define DC_I2C_DATA__DC_I2C_INDEX_MASK                                                                        0x03FF0000L
++#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK                                                                  0x80000000L
++//DC_I2C_EDID_DETECT_CTRL
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT                                          0x0
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT                              0x14
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT                                         0x1c
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK                                            0x0000FFFFL
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK                                0x00F00000L
++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK                                           0x10000000L
++//DC_I2C_READ_REQUEST_INTERRUPT
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT                               0x0
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT                                    0x1
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT                                    0x2
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT                                   0x3
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT                               0x4
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT                                    0x5
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT                                    0x6
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT                                   0x7
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT                               0x8
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT                                    0x9
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT                                    0xa
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT                                   0xb
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT                               0xc
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT                                    0xd
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT                                    0xe
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT                                   0xf
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT                               0x10
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT                                    0x11
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT                                    0x12
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT                                   0x13
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT                               0x14
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT                                    0x15
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT                                    0x16
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT                                   0x17
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT                             0x18
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT                                  0x19
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT                                  0x1a
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT                                 0x1b
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT                              0x1e
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT                                0x1f
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK                                 0x00000001L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK                                      0x00000002L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK                                      0x00000004L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK                                     0x00000008L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK                                 0x00000010L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK                                      0x00000020L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK                                      0x00000040L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK                                     0x00000080L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK                                 0x00000100L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK                                      0x00000200L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK                                      0x00000400L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK                                     0x00000800L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK                                 0x00001000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK                                      0x00002000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK                                      0x00004000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK                                     0x00008000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK                                 0x00010000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK                                      0x00020000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK                                      0x00040000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK                                     0x00080000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK                                 0x00100000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK                                      0x00200000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK                                      0x00400000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK                                     0x00800000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK                               0x01000000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK                                    0x02000000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK                                    0x04000000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK                                   0x08000000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK                                0x40000000L
++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK                                  0x80000000L
++
++
++//DIG_SOFT_RESET
++#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT                                                             0x0
++#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT                                                             0x1
++#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT                                                             0x4
++#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT                                                             0x5
++#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT                                                             0x8
++#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT                                                             0x9
++#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT                                                             0xc
++#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT                                                             0xd
++#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT                                                             0x10
++#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT                                                             0x11
++#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT                                                             0x14
++#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT                                                             0x15
++#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT                                                             0x18
++#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT                                                             0x19
++#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK                                                               0x00000001L
++#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK                                                               0x00000002L
++#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK                                                               0x00000010L
++#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK                                                               0x00000020L
++#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK                                                               0x00000100L
++#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK                                                               0x00000200L
++#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK                                                               0x00001000L
++#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK                                                               0x00002000L
++#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK                                                               0x00010000L
++#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK                                                               0x00020000L
++#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK                                                               0x00100000L
++#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK                                                               0x00200000L
++#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK                                                               0x01000000L
++#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK                                                               0x02000000L
++//DIO_MEM_PWR_STATUS1
++#define DIO_MEM_PWR_STATUS1__AFMT0_MEM_PWR_STATE__SHIFT                                                       0x0
++#define DIO_MEM_PWR_STATUS1__AFMT1_MEM_PWR_STATE__SHIFT                                                       0x2
++#define DIO_MEM_PWR_STATUS1__AFMT2_MEM_PWR_STATE__SHIFT                                                       0x4
++#define DIO_MEM_PWR_STATUS1__AFMT3_MEM_PWR_STATE__SHIFT                                                       0x6
++#define DIO_MEM_PWR_STATUS1__AFMT4_MEM_PWR_STATE__SHIFT                                                       0x8
++#define DIO_MEM_PWR_STATUS1__AFMT5_MEM_PWR_STATE__SHIFT                                                       0xa
++#define DIO_MEM_PWR_STATUS1__DME0_MEM_PWR_STATE__SHIFT                                                        0x10
++#define DIO_MEM_PWR_STATUS1__DME1_MEM_PWR_STATE__SHIFT                                                        0x12
++#define DIO_MEM_PWR_STATUS1__DME2_MEM_PWR_STATE__SHIFT                                                        0x14
++#define DIO_MEM_PWR_STATUS1__DME3_MEM_PWR_STATE__SHIFT                                                        0x16
++#define DIO_MEM_PWR_STATUS1__DME4_MEM_PWR_STATE__SHIFT                                                        0x18
++#define DIO_MEM_PWR_STATUS1__DME5_MEM_PWR_STATE__SHIFT                                                        0x1a
++#define DIO_MEM_PWR_STATUS1__AFMT0_MEM_PWR_STATE_MASK                                                         0x00000001L
++#define DIO_MEM_PWR_STATUS1__AFMT1_MEM_PWR_STATE_MASK                                                         0x00000004L
++#define DIO_MEM_PWR_STATUS1__AFMT2_MEM_PWR_STATE_MASK                                                         0x00000010L
++#define DIO_MEM_PWR_STATUS1__AFMT3_MEM_PWR_STATE_MASK                                                         0x00000040L
++#define DIO_MEM_PWR_STATUS1__AFMT4_MEM_PWR_STATE_MASK                                                         0x00000100L
++#define DIO_MEM_PWR_STATUS1__AFMT5_MEM_PWR_STATE_MASK                                                         0x00000400L
++#define DIO_MEM_PWR_STATUS1__DME0_MEM_PWR_STATE_MASK                                                          0x00030000L
++#define DIO_MEM_PWR_STATUS1__DME1_MEM_PWR_STATE_MASK                                                          0x000C0000L
++#define DIO_MEM_PWR_STATUS1__DME2_MEM_PWR_STATE_MASK                                                          0x00300000L
++#define DIO_MEM_PWR_STATUS1__DME3_MEM_PWR_STATE_MASK                                                          0x00C00000L
++#define DIO_MEM_PWR_STATUS1__DME4_MEM_PWR_STATE_MASK                                                          0x03000000L
++#define DIO_MEM_PWR_STATUS1__DME5_MEM_PWR_STATE_MASK                                                          0x0C000000L
++//DIO_CLK_CNTL2
++#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT                                                                0x0
++#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT                                                         0x7
++#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT                                                         0x8
++#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT                                                         0x9
++#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT                                                         0xa
++#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT                                                         0xb
++#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT                                                         0xc
++#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT                                                         0xd
++#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x11
++#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x12
++#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x13
++#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x14
++#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x15
++#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x16
++#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x17
++#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK                                                                  0x0000007FL
++#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK                                                           0x00000080L
++#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK                                                           0x00000100L
++#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK                                                           0x00000200L
++#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK                                                           0x00000400L
++#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK                                                           0x00000800L
++#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK                                                           0x00001000L
++#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK                                                           0x00002000L
++#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK                                                        0x00020000L
++#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK                                                        0x00040000L
++#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK                                                        0x00080000L
++#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK                                                        0x00100000L
++#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK                                                        0x00200000L
++#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK                                                        0x00400000L
++#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK                                                        0x00800000L
++//DIO_CLK_CNTL3
++#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x0
++#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x1
++#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x2
++#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x3
++#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x4
++#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x5
++#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x6
++#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT                                                         0xa
++#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT                                                         0xb
++#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT                                                         0xc
++#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT                                                         0xd
++#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT                                                         0xe
++#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT                                                         0xf
++#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT                                                         0x10
++#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000001L
++#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000002L
++#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000004L
++#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000008L
++#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000010L
++#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000020L
++#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000040L
++#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK                                                           0x00000400L
++#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK                                                           0x00000800L
++#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK                                                           0x00001000L
++#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK                                                           0x00002000L
++#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK                                                           0x00004000L
++#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK                                                           0x00008000L
++#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK                                                           0x00010000L
++//DIO_HDMI_RXSTATUS_TIMER_CONTROL
++#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT                                0x0
++#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT                                  0x4
++#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT                                0x8
++#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT                                  0xc
++#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT                              0x10
++#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK                                  0x00000001L
++#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK                                    0x00000010L
++#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK                                  0x00000100L
++#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK                                    0x00001000L
++#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK                                0x0FFF0000L
++//DIO_PSP_INTERRUPT_STATUS
++#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS__SHIFT                                             0x0
++#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE__SHIFT                                            0x1
++#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS_MASK                                               0x00000001L
++#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE_MASK                                              0xFFFFFFFEL
++//DIO_PSP_INTERRUPT_CLEAR
++#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR__SHIFT                                               0x0
++#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR_MASK                                                 0x00000001L
++//DIO_GENERIC_INTERRUPT_MESSAGE
++#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS__SHIFT                                    0x0
++#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE__SHIFT                                   0x1
++#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS_MASK                                      0x00000001L
++#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE_MASK                                     0xFFFFFFFEL
++//DIO_GENERIC_INTERRUPT_CLEAR
++#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR__SHIFT                                       0x0
++#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR_MASK                                         0x00000001L
++
++
++// addressBlock: dce_dc_dio_hpd0_dispdec
++//HPD0_DC_HPD_INT_STATUS
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
++#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
++//HPD0_DC_HPD_INT_CONTROL
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
++#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
++//HPD0_DC_HPD_CONTROL
++#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
++#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
++#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
++#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
++#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
++#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
++//HPD0_DC_HPD_FAST_TRAIN_CNTL
++#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
++#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
++#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
++#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
++#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
++#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
++#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
++#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
++//HPD0_DC_HPD_TOGGLE_FILT_CNTL
++#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
++#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
++#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
++#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
++
++
++// addressBlock: dce_dc_dio_hpd1_dispdec
++//HPD1_DC_HPD_INT_STATUS
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
++#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
++//HPD1_DC_HPD_INT_CONTROL
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
++#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
++//HPD1_DC_HPD_CONTROL
++#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
++#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
++#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
++#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
++#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
++#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
++//HPD1_DC_HPD_FAST_TRAIN_CNTL
++#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
++#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
++#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
++#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
++#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
++#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
++#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
++#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
++//HPD1_DC_HPD_TOGGLE_FILT_CNTL
++#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
++#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
++#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
++#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
++
++
++// addressBlock: dce_dc_dio_hpd2_dispdec
++//HPD2_DC_HPD_INT_STATUS
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
++#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
++//HPD2_DC_HPD_INT_CONTROL
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
++#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
++//HPD2_DC_HPD_CONTROL
++#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
++#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
++#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
++#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
++#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
++#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
++//HPD2_DC_HPD_FAST_TRAIN_CNTL
++#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
++#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
++#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
++#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
++#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
++#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
++#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
++#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
++//HPD2_DC_HPD_TOGGLE_FILT_CNTL
++#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
++#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
++#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
++#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
++
++
++// addressBlock: dce_dc_dio_hpd3_dispdec
++//HPD3_DC_HPD_INT_STATUS
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
++#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
++//HPD3_DC_HPD_INT_CONTROL
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
++#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
++//HPD3_DC_HPD_CONTROL
++#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
++#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
++#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
++#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
++#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
++#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
++//HPD3_DC_HPD_FAST_TRAIN_CNTL
++#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
++#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
++#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
++#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
++#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
++#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
++#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
++#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
++//HPD3_DC_HPD_TOGGLE_FILT_CNTL
++#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
++#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
++#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
++#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
++
++
++// addressBlock: dce_dc_dio_hpd4_dispdec
++//HPD4_DC_HPD_INT_STATUS
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
++#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
++//HPD4_DC_HPD_INT_CONTROL
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
++#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
++//HPD4_DC_HPD_CONTROL
++#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
++#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
++#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
++#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
++#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
++#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
++//HPD4_DC_HPD_FAST_TRAIN_CNTL
++#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
++#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
++#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
++#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
++#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
++#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
++#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
++#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
++//HPD4_DC_HPD_TOGGLE_FILT_CNTL
++#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
++#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
++#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
++#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
++
++
++// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON18_PERFCOUNTER_CNTL
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
++#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
++//DC_PERFMON18_PERFCOUNTER_CNTL2
++#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
++#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
++#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
++#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
++#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
++#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
++#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
++#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
++#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
++#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
++//DC_PERFMON18_PERFCOUNTER_STATE
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
++#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
++//DC_PERFMON18_PERFMON_CNTL
++#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
++#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
++#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
++#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
++#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
++#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
++#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
++#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
++#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
++#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
++#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
++#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
++//DC_PERFMON18_PERFMON_CNTL2
++#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
++#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
++#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
++#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
++#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
++#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
++#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
++#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
++//DC_PERFMON18_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
++#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
++//DC_PERFMON18_PERFMON_CVALUE_LOW
++#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
++#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
++//DC_PERFMON18_PERFMON_HI
++#define DC_PERFMON18_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
++#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
++#define DC_PERFMON18_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
++#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
++//DC_PERFMON18_PERFMON_LOW
++#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
++#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dio_dp_aux0_dispdec
++//DP_AUX0_AUX_CONTROL
++#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
++#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
++#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
++#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
++#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
++#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
++#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
++#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
++#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
++#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
++#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
++#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
++#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
++#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
++#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
++#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
++#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
++#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
++#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
++#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
++#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
++#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
++#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
++#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
++#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
++#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
++//DP_AUX0_AUX_SW_CONTROL
++#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
++#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
++#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
++#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
++#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
++#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
++#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
++#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
++//DP_AUX0_AUX_ARB_CONTROL
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
++#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
++//DP_AUX0_AUX_INTERRUPT_CONTROL
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
++#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
++//DP_AUX0_AUX_SW_STATUS
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
++#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
++#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
++#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
++//DP_AUX0_AUX_LS_STATUS
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
++#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
++//DP_AUX0_AUX_SW_DATA
++#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
++#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
++#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
++#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
++#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
++#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
++#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
++#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
++//DP_AUX0_AUX_LS_DATA
++#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
++#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
++#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
++#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
++//DP_AUX0_AUX_DPHY_TX_REF_CONTROL
++#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
++#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
++#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
++#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
++#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
++#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
++//DP_AUX0_AUX_DPHY_TX_CONTROL
++#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
++#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
++#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
++#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
++#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
++#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
++#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
++#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
++#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
++#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
++//DP_AUX0_AUX_DPHY_RX_CONTROL0
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
++#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
++//DP_AUX0_AUX_DPHY_RX_CONTROL1
++#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
++#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
++#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
++#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
++#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
++#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
++//DP_AUX0_AUX_DPHY_TX_STATUS
++#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
++#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
++#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
++#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
++#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
++#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
++//DP_AUX0_AUX_DPHY_RX_STATUS
++#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
++#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
++#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
++#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
++#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
++#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
++#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
++#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
++//DP_AUX0_AUX_GTC_SYNC_CONTROL
++#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
++#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
++#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
++#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
++#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
++#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
++#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
++#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
++#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
++#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
++//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL
++#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
++#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
++#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
++#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
++#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
++#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
++#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
++#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
++//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
++#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
++//DP_AUX0_AUX_GTC_SYNC_STATUS
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
++#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
++//DP_AUX0_AUX_PHY_WAKE_CNTL
++#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
++#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
++#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
++#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
++#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
++#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
++#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
++#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
++
++
++// addressBlock: dce_dc_dio_dp_aux1_dispdec
++//DP_AUX1_AUX_CONTROL
++#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
++#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
++#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
++#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
++#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
++#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
++#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
++#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
++#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
++#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
++#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
++#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
++#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
++#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
++#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
++#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
++#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
++#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
++#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
++#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
++#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
++#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
++#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
++#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
++#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
++#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
++//DP_AUX1_AUX_SW_CONTROL
++#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
++#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
++#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
++#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
++#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
++#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
++#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
++#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
++//DP_AUX1_AUX_ARB_CONTROL
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
++#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
++//DP_AUX1_AUX_INTERRUPT_CONTROL
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
++#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
++//DP_AUX1_AUX_SW_STATUS
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
++#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
++#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
++#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
++//DP_AUX1_AUX_LS_STATUS
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
++#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
++//DP_AUX1_AUX_SW_DATA
++#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
++#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
++#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
++#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
++#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
++#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
++#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
++#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
++//DP_AUX1_AUX_LS_DATA
++#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
++#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
++#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
++#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
++//DP_AUX1_AUX_DPHY_TX_REF_CONTROL
++#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
++#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
++#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
++#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
++#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
++#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
++//DP_AUX1_AUX_DPHY_TX_CONTROL
++#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
++#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
++#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
++#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
++#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
++#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
++#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
++#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
++#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
++#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
++//DP_AUX1_AUX_DPHY_RX_CONTROL0
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
++#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
++//DP_AUX1_AUX_DPHY_RX_CONTROL1
++#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
++#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
++#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
++#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
++#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
++#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
++//DP_AUX1_AUX_DPHY_TX_STATUS
++#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
++#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
++#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
++#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
++#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
++#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
++//DP_AUX1_AUX_DPHY_RX_STATUS
++#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
++#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
++#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
++#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
++#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
++#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
++#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
++#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
++//DP_AUX1_AUX_GTC_SYNC_CONTROL
++#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
++#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
++#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
++#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
++#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
++#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
++#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
++#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
++#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
++#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
++//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL
++#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
++#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
++#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
++#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
++#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
++#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
++#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
++#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
++//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
++#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
++//DP_AUX1_AUX_GTC_SYNC_STATUS
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
++#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
++//DP_AUX1_AUX_PHY_WAKE_CNTL
++#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
++#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
++#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
++#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
++#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
++#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
++#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
++#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
++
++
++// addressBlock: dce_dc_dio_dp_aux2_dispdec
++//DP_AUX2_AUX_CONTROL
++#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
++#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
++#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
++#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
++#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
++#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
++#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
++#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
++#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
++#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
++#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
++#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
++#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
++#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
++#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
++#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
++#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
++#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
++#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
++#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
++#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
++#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
++#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
++#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
++#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
++#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
++//DP_AUX2_AUX_SW_CONTROL
++#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
++#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
++#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
++#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
++#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
++#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
++#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
++#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
++//DP_AUX2_AUX_ARB_CONTROL
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
++#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
++//DP_AUX2_AUX_INTERRUPT_CONTROL
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
++#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
++//DP_AUX2_AUX_SW_STATUS
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
++#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
++#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
++#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
++//DP_AUX2_AUX_LS_STATUS
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
++#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
++//DP_AUX2_AUX_SW_DATA
++#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
++#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
++#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
++#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
++#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
++#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
++#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
++#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
++//DP_AUX2_AUX_LS_DATA
++#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
++#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
++#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
++#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
++//DP_AUX2_AUX_DPHY_TX_REF_CONTROL
++#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
++#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
++#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
++#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
++#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
++#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
++//DP_AUX2_AUX_DPHY_TX_CONTROL
++#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
++#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
++#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
++#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
++#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
++#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
++#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
++#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
++#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
++#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
++//DP_AUX2_AUX_DPHY_RX_CONTROL0
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
++#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
++//DP_AUX2_AUX_DPHY_RX_CONTROL1
++#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
++#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
++#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
++#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
++#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
++#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
++//DP_AUX2_AUX_DPHY_TX_STATUS
++#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
++#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
++#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
++#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
++#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
++#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
++//DP_AUX2_AUX_DPHY_RX_STATUS
++#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
++#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
++#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
++#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
++#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
++#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
++#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
++#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
++//DP_AUX2_AUX_GTC_SYNC_CONTROL
++#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
++#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
++#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
++#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
++#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
++#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
++#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
++#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
++#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
++#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
++//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL
++#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
++#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
++#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
++#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
++#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
++#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
++#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
++#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
++//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
++#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
++//DP_AUX2_AUX_GTC_SYNC_STATUS
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
++#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
++//DP_AUX2_AUX_PHY_WAKE_CNTL
++#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
++#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
++#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
++#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
++#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
++#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
++#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
++#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
++
++
++// addressBlock: dce_dc_dio_dp_aux3_dispdec
++//DP_AUX3_AUX_CONTROL
++#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
++#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
++#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
++#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
++#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
++#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
++#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
++#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
++#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
++#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
++#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
++#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
++#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
++#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
++#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
++#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
++#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
++#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
++#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
++#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
++#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
++#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
++#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
++#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
++#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
++#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
++//DP_AUX3_AUX_SW_CONTROL
++#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
++#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
++#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
++#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
++#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
++#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
++#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
++#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
++//DP_AUX3_AUX_ARB_CONTROL
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
++#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
++//DP_AUX3_AUX_INTERRUPT_CONTROL
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
++#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
++//DP_AUX3_AUX_SW_STATUS
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
++#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
++#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
++#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
++//DP_AUX3_AUX_LS_STATUS
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
++#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
++//DP_AUX3_AUX_SW_DATA
++#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
++#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
++#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
++#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
++#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
++#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
++#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
++#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
++//DP_AUX3_AUX_LS_DATA
++#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
++#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
++#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
++#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
++//DP_AUX3_AUX_DPHY_TX_REF_CONTROL
++#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
++#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
++#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
++#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
++#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
++#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
++//DP_AUX3_AUX_DPHY_TX_CONTROL
++#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
++#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
++#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
++#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
++#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
++#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
++#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
++#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
++#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
++#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
++//DP_AUX3_AUX_DPHY_RX_CONTROL0
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
++#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
++//DP_AUX3_AUX_DPHY_RX_CONTROL1
++#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
++#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
++#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
++#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
++#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
++#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
++//DP_AUX3_AUX_DPHY_TX_STATUS
++#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
++#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
++#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
++#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
++#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
++#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
++//DP_AUX3_AUX_DPHY_RX_STATUS
++#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
++#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
++#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
++#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
++#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
++#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
++#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
++#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
++//DP_AUX3_AUX_GTC_SYNC_CONTROL
++#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
++#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
++#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
++#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
++#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
++#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
++#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
++#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
++#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
++#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
++//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL
++#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
++#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
++#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
++#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
++#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
++#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
++#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
++#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
++//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
++#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
++//DP_AUX3_AUX_GTC_SYNC_STATUS
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
++#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
++//DP_AUX3_AUX_PHY_WAKE_CNTL
++#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
++#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
++#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
++#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
++#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
++#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
++#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
++#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
++
++
++// addressBlock: dce_dc_dio_dp_aux4_dispdec
++//DP_AUX4_AUX_CONTROL
++#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
++#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
++#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
++#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
++#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
++#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
++#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
++#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
++#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
++#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
++#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
++#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
++#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
++#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
++#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
++#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
++#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
++#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
++#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
++#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
++#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
++#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
++#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
++#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
++#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
++#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
++//DP_AUX4_AUX_SW_CONTROL
++#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
++#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
++#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
++#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
++#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
++#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
++#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
++#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
++//DP_AUX4_AUX_ARB_CONTROL
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
++#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
++//DP_AUX4_AUX_INTERRUPT_CONTROL
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
++#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
++//DP_AUX4_AUX_SW_STATUS
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
++#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
++#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
++#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
++//DP_AUX4_AUX_LS_STATUS
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
++#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
++//DP_AUX4_AUX_SW_DATA
++#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
++#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
++#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
++#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
++#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
++#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
++#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
++#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
++//DP_AUX4_AUX_LS_DATA
++#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
++#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
++#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
++#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
++//DP_AUX4_AUX_DPHY_TX_REF_CONTROL
++#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
++#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
++#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
++#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
++#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
++#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
++//DP_AUX4_AUX_DPHY_TX_CONTROL
++#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
++#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
++#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
++#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
++#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
++#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
++#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
++#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
++#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
++#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
++//DP_AUX4_AUX_DPHY_RX_CONTROL0
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
++#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
++//DP_AUX4_AUX_DPHY_RX_CONTROL1
++#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
++#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
++#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
++#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
++#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
++#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
++//DP_AUX4_AUX_DPHY_TX_STATUS
++#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
++#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
++#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
++#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
++#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
++#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
++//DP_AUX4_AUX_DPHY_RX_STATUS
++#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
++#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
++#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
++#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
++#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
++#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
++#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
++#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
++//DP_AUX4_AUX_GTC_SYNC_CONTROL
++#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
++#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
++#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
++#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
++#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
++#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
++#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
++#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
++#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
++#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
++//DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL
++#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
++#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
++#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
++#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
++#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
++#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
++#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
++#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
++//DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
++#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
++//DP_AUX4_AUX_GTC_SYNC_STATUS
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
++#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
++//DP_AUX4_AUX_PHY_WAKE_CNTL
++#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
++#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
++#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
++#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
++#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
++#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
++#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
++#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
++
++
++// addressBlock: dce_dc_dio_dig0_dispdec
++//DIG0_DIG_FE_CNTL
++#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
++#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
++#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
++#define DIG0_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
++#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
++#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
++#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
++#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
++#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
++#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
++#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
++#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
++#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
++#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
++#define DIG0_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
++#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
++#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
++#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
++#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
++#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
++#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
++#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
++//DIG0_DIG_OUTPUT_CRC_CNTL
++#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
++#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
++#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
++#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
++#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
++#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
++//DIG0_DIG_OUTPUT_CRC_RESULT
++#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
++#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
++//DIG0_DIG_CLOCK_PATTERN
++#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
++#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
++//DIG0_DIG_TEST_PATTERN
++#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
++#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
++#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
++#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
++#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
++#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
++#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
++#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
++#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
++#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
++#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
++#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
++//DIG0_DIG_RANDOM_PATTERN_SEED
++#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
++#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
++#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
++#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
++//DIG0_DIG_FIFO_STATUS
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                   0x10
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                     0x001F0000L
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
++#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
++//DIG0_HDMI_METADATA_PACKET_CONTROL
++#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
++#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
++#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
++#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
++#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
++#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
++#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
++#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
++//DIG0_HDMI_GENERIC_PACKET_CONTROL4
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
++//DIG0_HDMI_CONTROL
++#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
++#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
++#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
++#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
++#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
++#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
++#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
++#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
++#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
++#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
++#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
++#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
++#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
++#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
++#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
++#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
++#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
++#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
++#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
++#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
++//DIG0_HDMI_STATUS
++#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
++#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
++#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
++#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
++#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
++#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
++#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
++#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
++//DIG0_HDMI_AUDIO_PACKET_CONTROL
++#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
++#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                    0x8
++#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                    0x10
++#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
++#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                      0x00000100L
++#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK                                      0x001F0000L
++//DIG0_HDMI_ACR_PACKET_CONTROL
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
++#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
++//DIG0_HDMI_VBI_PACKET_CONTROL
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
++#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
++//DIG0_HDMI_INFOFRAME_CONTROL0
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
++#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
++//DIG0_HDMI_INFOFRAME_CONTROL1
++#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
++#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
++#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
++#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
++//DIG0_HDMI_GENERIC_PACKET_CONTROL0
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
++//DIG0_HDMI_GC
++#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
++#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
++#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
++#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
++#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
++#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
++#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
++#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
++#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
++#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
++//DIG0_AFMT_AUDIO_PACKET_CONTROL2
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                        0x0
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                      0x1
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                     0x8
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                       0x10
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                          0x18
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                           0x1c
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                          0x00000001L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                        0x00000002L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                       0x0000FF00L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                         0x00FF0000L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                            0x01000000L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                             0x10000000L
++//DIG0_AFMT_ISRC1_0
++#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT                                                            0x0
++#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT                                                          0x6
++#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT                                                             0x7
++#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK                                                              0x00000007L
++#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK                                                            0x00000040L
++#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK                                                               0x00000080L
++//DIG0_AFMT_ISRC1_1
++#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT                                                          0x0
++#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT                                                          0x8
++#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT                                                          0x10
++#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT                                                          0x18
++#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK                                                            0x000000FFL
++#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK                                                            0x0000FF00L
++#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK                                                            0x00FF0000L
++#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK                                                            0xFF000000L
++//DIG0_AFMT_ISRC1_2
++#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT                                                          0x0
++#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT                                                          0x8
++#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT                                                          0x10
++#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT                                                          0x18
++#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK                                                            0x000000FFL
++#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK                                                            0x0000FF00L
++#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK                                                            0x00FF0000L
++#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK                                                            0xFF000000L
++//DIG0_AFMT_ISRC1_3
++#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT                                                          0x0
++#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT                                                          0x8
++#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT                                                         0x10
++#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT                                                         0x18
++#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK                                                            0x000000FFL
++#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK                                                            0x0000FF00L
++#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK                                                           0x00FF0000L
++#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK                                                           0xFF000000L
++//DIG0_AFMT_ISRC1_4
++#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT                                                         0x0
++#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT                                                         0x8
++#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT                                                         0x10
++#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT                                                         0x18
++#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK                                                           0x000000FFL
++#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK                                                           0x0000FF00L
++#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK                                                           0x00FF0000L
++#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK                                                           0xFF000000L
++//DIG0_AFMT_ISRC2_0
++#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT                                                         0x0
++#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT                                                         0x8
++#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT                                                         0x10
++#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT                                                         0x18
++#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK                                                           0x000000FFL
++#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK                                                           0x0000FF00L
++#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK                                                           0x00FF0000L
++#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK                                                           0xFF000000L
++//DIG0_AFMT_ISRC2_1
++#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT                                                         0x0
++#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT                                                         0x8
++#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT                                                         0x10
++#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT                                                         0x18
++#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK                                                           0x000000FFL
++#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK                                                           0x0000FF00L
++#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK                                                           0x00FF0000L
++#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK                                                           0xFF000000L
++//DIG0_AFMT_ISRC2_2
++#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT                                                         0x0
++#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT                                                         0x8
++#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT                                                         0x10
++#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT                                                         0x18
++#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK                                                           0x000000FFL
++#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK                                                           0x0000FF00L
++#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK                                                           0x00FF0000L
++#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK                                                           0xFF000000L
++//DIG0_AFMT_ISRC2_3
++#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT                                                         0x0
++#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT                                                         0x8
++#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT                                                         0x10
++#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT                                                         0x18
++#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK                                                           0x000000FFL
++#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK                                                           0x0000FF00L
++#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK                                                           0x00FF0000L
++#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK                                                           0xFF000000L
++//DIG0_HDMI_GENERIC_PACKET_CONTROL2
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
++//DIG0_HDMI_GENERIC_PACKET_CONTROL3
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
++//DIG0_HDMI_DB_CONTROL
++#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
++#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
++#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
++#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
++#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
++#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
++#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
++#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
++#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
++#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
++#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
++#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
++#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
++#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
++#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
++#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
++//DIG0_DME_CONTROL
++#define DIG0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
++#define DIG0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
++#define DIG0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
++#define DIG0_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
++#define DIG0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
++#define DIG0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
++#define DIG0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
++#define DIG0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
++#define DIG0_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
++#define DIG0_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
++#define DIG0_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
++#define DIG0_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
++#define DIG0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
++#define DIG0_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
++//DIG0_AFMT_MPEG_INFO0
++#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT                                                  0x0
++#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT                                                       0x8
++#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT                                                       0x10
++#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT                                                       0x18
++#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK                                                    0x000000FFL
++#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK                                                         0x0000FF00L
++#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK                                                         0x00FF0000L
++#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK                                                         0xFF000000L
++//DIG0_AFMT_MPEG_INFO1
++#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT                                                       0x0
++#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT                                                        0x8
++#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT                                                        0xc
++#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK                                                         0x000000FFL
++#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK                                                          0x00000300L
++#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK                                                          0x00001000L
++//DIG0_AFMT_GENERIC_HDR
++#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT                                                        0x0
++#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT                                                        0x8
++#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT                                                        0x10
++#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT                                                        0x18
++#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK                                                          0x000000FFL
++#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK                                                          0x0000FF00L
++#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK                                                          0x00FF0000L
++#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK                                                          0xFF000000L
++//DIG0_AFMT_GENERIC_0
++#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT                                                        0x0
++#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT                                                        0x8
++#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT                                                        0x10
++#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT                                                        0x18
++#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK                                                          0x000000FFL
++#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK                                                          0x0000FF00L
++#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK                                                          0x00FF0000L
++#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK                                                          0xFF000000L
++//DIG0_AFMT_GENERIC_1
++#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT                                                        0x0
++#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT                                                        0x8
++#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT                                                        0x10
++#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT                                                        0x18
++#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK                                                          0x000000FFL
++#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK                                                          0x0000FF00L
++#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK                                                          0x00FF0000L
++#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK                                                          0xFF000000L
++//DIG0_AFMT_GENERIC_2
++#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT                                                        0x0
++#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT                                                        0x8
++#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT                                                       0x10
++#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT                                                       0x18
++#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK                                                          0x000000FFL
++#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK                                                          0x0000FF00L
++#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK                                                         0x00FF0000L
++#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK                                                         0xFF000000L
++//DIG0_AFMT_GENERIC_3
++#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT                                                       0x0
++#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT                                                       0x8
++#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT                                                       0x10
++#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT                                                       0x18
++#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK                                                         0x000000FFL
++#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK                                                         0x0000FF00L
++#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK                                                         0x00FF0000L
++#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK                                                         0xFF000000L
++//DIG0_AFMT_GENERIC_4
++#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT                                                       0x0
++#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT                                                       0x8
++#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT                                                       0x10
++#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT                                                       0x18
++#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK                                                         0x000000FFL
++#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK                                                         0x0000FF00L
++#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK                                                         0x00FF0000L
++#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK                                                         0xFF000000L
++//DIG0_AFMT_GENERIC_5
++#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT                                                       0x0
++#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT                                                       0x8
++#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT                                                       0x10
++#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT                                                       0x18
++#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK                                                         0x000000FFL
++#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK                                                         0x0000FF00L
++#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK                                                         0x00FF0000L
++#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK                                                         0xFF000000L
++//DIG0_AFMT_GENERIC_6
++#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT                                                       0x0
++#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT                                                       0x8
++#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT                                                       0x10
++#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT                                                       0x18
++#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK                                                         0x000000FFL
++#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK                                                         0x0000FF00L
++#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK                                                         0x00FF0000L
++#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK                                                         0xFF000000L
++//DIG0_AFMT_GENERIC_7
++#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT                                                       0x0
++#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT                                                       0x8
++#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT                                                       0x10
++#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT                                                       0x18
++#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK                                                         0x000000FFL
++#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK                                                         0x0000FF00L
++#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK                                                         0x00FF0000L
++#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK                                                         0xFF000000L
++//DIG0_HDMI_GENERIC_PACKET_CONTROL1
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
++//DIG0_HDMI_ACR_32_0
++#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
++#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
++//DIG0_HDMI_ACR_32_1
++#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
++#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
++//DIG0_HDMI_ACR_44_0
++#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
++#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
++//DIG0_HDMI_ACR_44_1
++#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
++#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
++//DIG0_HDMI_ACR_48_0
++#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
++#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
++//DIG0_HDMI_ACR_48_1
++#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
++#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
++//DIG0_HDMI_ACR_STATUS_0
++#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
++#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
++//DIG0_HDMI_ACR_STATUS_1
++#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
++#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
++//DIG0_AFMT_AUDIO_INFO0
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                                0x0
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                      0x8
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                      0xb
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                         0x10
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                     0x18
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                  0x000000FFL
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                        0x00000700L
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                        0x00007800L
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                           0x00FF0000L
++#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                       0x1F000000L
++//DIG0_AFMT_AUDIO_INFO1
++#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                      0x0
++#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                     0xb
++#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                  0xf
++#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                  0x10
++#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                        0x000000FFL
++#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                       0x00007800L
++#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                    0x00008000L
++#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                    0x00030000L
++//DIG0_AFMT_60958_0
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                             0x0
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                             0x1
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                             0x2
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                             0x3
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                          0x6
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                 0x8
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                 0x10
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                              0x14
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                            0x18
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                                0x1c
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                               0x00000001L
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                               0x00000002L
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                               0x00000004L
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                               0x00000038L
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                            0x000000C0L
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                   0x0000FF00L
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                   0x000F0000L
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                                0x00F00000L
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                              0x0F000000L
++#define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                  0x30000000L
++//DIG0_AFMT_60958_1
++#define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                   0x0
++#define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                   0x4
++#define DIG0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                          0x10
++#define DIG0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                          0x12
++#define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                              0x14
++#define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                     0x0000000FL
++#define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                     0x000000F0L
++#define DIG0_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                            0x00010000L
++#define DIG0_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                            0x00040000L
++#define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                                0x00F00000L
++//DIG0_AFMT_AUDIO_CRC_CONTROL
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                 0x0
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                               0x4
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                             0x8
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                             0xc
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                              0x10
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                   0x00000001L
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                 0x00000010L
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                               0x00000100L
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                               0x0000F000L
++#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                                0xFFFF0000L
++//DIG0_AFMT_RAMP_CONTROL0
++#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                   0x0
++#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                   0x1f
++#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                     0x00FFFFFFL
++#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                     0x80000000L
++//DIG0_AFMT_RAMP_CONTROL1
++#define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                   0x0
++#define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                            0x18
++#define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                     0x00FFFFFFL
++#define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                              0xFF000000L
++//DIG0_AFMT_RAMP_CONTROL2
++#define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                   0x0
++#define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                     0x00FFFFFFL
++//DIG0_AFMT_RAMP_CONTROL3
++#define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                   0x0
++#define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                     0x00FFFFFFL
++//DIG0_AFMT_60958_2
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                              0x0
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                              0x4
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                              0x8
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                              0xc
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                              0x10
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                              0x14
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                                0x0000000FL
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                                0x000000F0L
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                                0x00000F00L
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                                0x0000F000L
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                                0x000F0000L
++#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                                0x00F00000L
++//DIG0_AFMT_AUDIO_CRC_RESULT
++#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                                0x0
++#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                     0x8
++#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                  0x00000001L
++#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                       0xFFFFFF00L
++//DIG0_AFMT_STATUS
++#define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                            0x4
++#define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                           0x8
++#define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                     0x18
++#define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                     0x1e
++#define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                              0x00000010L
++#define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                             0x00000100L
++#define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                       0x01000000L
++#define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                       0x40000000L
++//DIG0_AFMT_AUDIO_PACKET_CONTROL
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                         0x0
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                 0xb
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                             0xc
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                           0xe
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                   0x17
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                        0x18
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                           0x1a
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                   0x1e
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                                0x1f
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                           0x00000001L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                   0x00000800L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                               0x00001000L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                             0x00004000L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                     0x00800000L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                          0x01000000L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                             0x04000000L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                     0x40000000L
++#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                  0x80000000L
++//DIG0_AFMT_VBI_PACKET_CONTROL
++#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT                                         0x8
++#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT                                            0x10
++#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT                                        0x11
++#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT                                               0x1c
++#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK                                           0x00000100L
++#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK                                              0x00010000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK                                          0x00020000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK                                                 0xF0000000L
++//DIG0_AFMT_INFOFRAME_CONTROL0
++#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                           0x6
++#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                           0x7
++#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT                                            0xa
++#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                             0x00000040L
++#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                             0x00000080L
++#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK                                              0x00000400L
++//DIG0_AFMT_AUDIO_SRC_CONTROL
++#define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                             0x0
++#define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                               0x00000007L
++//DIG0_DIG_BE_CNTL
++#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
++#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
++#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
++#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
++#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
++#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
++#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
++#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
++#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
++#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
++#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
++#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
++//DIG0_DIG_BE_EN_CNTL
++#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
++#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
++#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
++#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
++//DIG0_TMDS_CNTL
++#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
++#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
++//DIG0_TMDS_CONTROL_CHAR
++#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
++#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
++#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
++#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
++#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
++#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
++#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
++#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
++//DIG0_TMDS_CONTROL0_FEEDBACK
++#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
++#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
++#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
++#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
++//DIG0_TMDS_STEREOSYNC_CTL_SEL
++#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
++#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
++//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1
++#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
++#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
++#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
++#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
++//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3
++#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
++#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
++#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
++#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
++//DIG0_TMDS_CTL_BITS
++#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
++#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
++#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
++#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
++#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
++#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
++#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
++#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
++//DIG0_TMDS_DCBALANCER_CONTROL
++#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
++#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
++#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
++#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
++#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
++#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
++#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
++#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
++#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
++#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
++//DIG0_TMDS_SYNC_DCBALANCE_CHAR
++#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
++#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
++#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
++#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
++//DIG0_TMDS_CTL0_1_GEN_CNTL
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
++#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
++//DIG0_TMDS_CTL2_3_GEN_CNTL
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
++#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
++//DIG0_DIG_VERSION
++#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
++#define DIG0_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
++//DIG0_DIG_LANE_ENABLE
++#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT                                                              0x0
++#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT                                                              0x1
++#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT                                                              0x2
++#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT                                                              0x3
++#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT                                                               0x8
++#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN_MASK                                                                0x00000001L
++#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN_MASK                                                                0x00000002L
++#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN_MASK                                                                0x00000004L
++#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN_MASK                                                                0x00000008L
++#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN_MASK                                                                 0x00000100L
++//DIG0_AFMT_CNTL
++#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
++#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
++#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
++#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
++//DIG0_AFMT_VBI_PACKET_CONTROL1
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x1
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT                                  0x2
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x3
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT                                      0x4
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x5
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT                                  0x6
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x7
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT                                      0x8
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x9
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT                                  0xa
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xb
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT                                      0xc
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0xd
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT                                  0xe
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xf
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT                                      0x10
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x11
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT                                  0x12
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x13
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT                                      0x14
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT                                  0x16
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x17
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT                                      0x18
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x19
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT                                  0x1a
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1b
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT                                      0x1c
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x1d
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT                                  0x1e
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1f
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00000002L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK                                    0x00000004L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000008L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK                                        0x00000010L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00000020L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK                                    0x00000040L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000080L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK                                        0x00000100L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00000200L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK                                    0x00000400L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000800L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK                                        0x00001000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00002000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK                                    0x00004000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                            0x00008000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK                                        0x00010000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00020000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK                                    0x00040000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                            0x00080000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK                                        0x00100000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK                                    0x00400000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                            0x00800000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK                                        0x01000000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x02000000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK                                    0x04000000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                            0x08000000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK                                        0x10000000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x20000000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK                                    0x40000000L
++#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                            0x80000000L
++//DIG0_HDMI_GENERIC_PACKET_CONTROL5
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
++#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
++//DIG0_FORCE_DIG_DISABLE
++#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
++#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
++
++
++// addressBlock: dce_dc_dio_dp0_dispdec
++//DP0_DP_LINK_CNTL
++#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
++#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
++#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
++#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
++#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
++#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
++//DP0_DP_PIXEL_FORMAT
++#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
++#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
++#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
++#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
++#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
++#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
++//DP0_DP_MSA_COLORIMETRY
++#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
++#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
++//DP0_DP_CONFIG
++#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
++#define DP0_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
++//DP0_DP_VID_STREAM_CNTL
++#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
++#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
++#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
++#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
++#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
++#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
++#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
++#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
++//DP0_DP_STEER_FIFO
++#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
++#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
++#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
++#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
++#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
++#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
++#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
++#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
++#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
++#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
++#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
++#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
++#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
++#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
++//DP0_DP_MSA_MISC
++#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
++#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
++#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
++#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
++#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
++#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
++#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
++#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
++//DP0_DP_VID_TIMING
++#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
++#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
++#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
++#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
++#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
++#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
++#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
++#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
++#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
++#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
++//DP0_DP_VID_N
++#define DP0_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
++#define DP0_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
++//DP0_DP_VID_M
++#define DP0_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
++#define DP0_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
++//DP0_DP_LINK_FRAMING_CNTL
++#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
++#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
++#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
++#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
++#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
++#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
++//DP0_DP_HBR2_EYE_PATTERN
++#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
++#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
++//DP0_DP_VID_MSA_VBID
++#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
++#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
++#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
++#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
++//DP0_DP_VID_INTERRUPT_CNTL
++#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
++#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
++#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
++#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
++#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
++#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
++//DP0_DP_DPHY_CNTL
++#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
++#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
++#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
++#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
++#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
++#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
++#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
++#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
++#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
++#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
++#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
++#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
++#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
++#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
++#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
++#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
++#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
++#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
++//DP0_DP_DPHY_TRAINING_PATTERN_SEL
++#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
++#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
++//DP0_DP_DPHY_SYM0
++#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
++#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
++#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
++#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
++#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
++#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
++//DP0_DP_DPHY_SYM1
++#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
++#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
++#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
++#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
++#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
++#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
++//DP0_DP_DPHY_SYM2
++#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
++#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
++#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
++#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
++//DP0_DP_DPHY_8B10B_CNTL
++#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
++#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
++#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
++#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
++#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
++#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
++//DP0_DP_DPHY_PRBS_CNTL
++#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
++#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
++#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
++#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
++#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
++#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
++//DP0_DP_DPHY_SCRAM_CNTL
++#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
++#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
++#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
++#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
++#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
++#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
++#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
++#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
++//DP0_DP_DPHY_CRC_EN
++#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
++#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
++#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
++#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
++#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
++#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
++//DP0_DP_DPHY_CRC_CNTL
++#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
++#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
++#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
++#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
++#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
++#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
++//DP0_DP_DPHY_CRC_RESULT
++#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
++#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
++#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
++#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
++#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
++#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
++#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
++#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
++//DP0_DP_DPHY_CRC_MST_CNTL
++#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
++#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
++#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
++#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
++//DP0_DP_DPHY_CRC_MST_STATUS
++#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
++#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
++#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
++#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
++#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
++#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
++//DP0_DP_DPHY_FAST_TRAINING
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
++#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
++//DP0_DP_DPHY_FAST_TRAINING_STATUS
++#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
++#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
++#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
++#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
++#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
++#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
++#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
++#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
++//DP0_DP_SEC_CNTL
++#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
++#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
++#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
++#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
++#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
++#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
++#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
++#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
++#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
++#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
++#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
++#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
++#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
++//DP0_DP_SEC_CNTL1
++#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
++#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
++#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP0_DP_SEC_FRAMING1
++#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
++#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
++#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
++#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
++//DP0_DP_SEC_FRAMING2
++#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
++#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
++#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
++#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
++//DP0_DP_SEC_FRAMING3
++#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
++#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
++#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
++#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
++//DP0_DP_SEC_FRAMING4
++#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
++#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
++#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
++#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
++#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
++#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
++#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
++#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
++#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
++#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
++//DP0_DP_SEC_AUD_N
++#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
++#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
++//DP0_DP_SEC_AUD_N_READBACK
++#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
++#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
++//DP0_DP_SEC_AUD_M
++#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
++#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
++//DP0_DP_SEC_AUD_M_READBACK
++#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
++#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
++//DP0_DP_SEC_TIMESTAMP
++#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
++#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
++//DP0_DP_SEC_PACKET_CNTL
++#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
++#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
++#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
++#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
++#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
++#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
++#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
++#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
++//DP0_DP_MSE_RATE_CNTL
++#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
++#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
++#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
++#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
++//DP0_DP_MSE_RATE_UPDATE
++#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
++#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
++//DP0_DP_MSE_SAT0
++#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
++#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
++#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
++#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
++#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
++#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
++#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
++#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
++//DP0_DP_MSE_SAT1
++#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
++#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
++#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
++#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
++#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
++#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
++#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
++#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
++//DP0_DP_MSE_SAT2
++#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
++#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
++#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
++#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
++#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
++#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
++#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
++#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
++//DP0_DP_MSE_SAT_UPDATE
++#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
++#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
++#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
++#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
++//DP0_DP_MSE_LINK_TIMING
++#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
++#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
++#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
++#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
++//DP0_DP_MSE_MISC_CNTL
++#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
++#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
++#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
++#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
++#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
++#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
++//DP0_DP_DPHY_BS_SR_SWAP_CNTL
++#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
++#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
++#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
++#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
++#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
++#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
++//DP0_DP_DPHY_HBR2_PATTERN_CONTROL
++#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
++#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
++//DP0_DP_MSE_SAT0_STATUS
++#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
++#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
++#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
++#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
++#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
++#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
++#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
++#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
++//DP0_DP_MSE_SAT1_STATUS
++#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
++#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
++#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
++#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
++#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
++#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
++#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
++#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
++//DP0_DP_MSE_SAT2_STATUS
++#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
++#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
++#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
++#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
++#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
++#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
++#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
++#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
++//DP0_DP_MSA_TIMING_PARAM1
++#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
++#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
++#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
++#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
++//DP0_DP_MSA_TIMING_PARAM2
++#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
++#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
++#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
++#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
++//DP0_DP_MSA_TIMING_PARAM3
++#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
++#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
++#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
++#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
++#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
++#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
++#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
++#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
++//DP0_DP_MSA_TIMING_PARAM4
++#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
++#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
++#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
++#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
++//DP0_DP_MSO_CNTL
++#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
++#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
++#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
++#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
++#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
++#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
++#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
++#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
++#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
++#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
++#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
++#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
++#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
++#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
++#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
++#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
++//DP0_DP_MSO_CNTL1
++#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
++#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
++#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
++#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
++#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
++#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
++#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
++#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
++#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
++#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
++#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
++#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
++#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
++#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
++#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
++#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
++//DP0_DP_DSC_CNTL
++#define DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
++#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
++#define DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
++#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
++//DP0_DP_SEC_CNTL2
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT                                                              0x1c
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
++#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK                                                                0x10000000L
++//DP0_DP_SEC_CNTL3
++#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
++#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
++#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
++#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP0_DP_SEC_CNTL4
++#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
++#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
++#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
++#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP0_DP_SEC_CNTL5
++#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
++#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
++#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
++#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP0_DP_SEC_CNTL6
++#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
++#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
++//DP0_DP_SEC_CNTL7
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
++#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
++//DP0_DP_DB_CNTL
++#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
++#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
++#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
++#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
++#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
++#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
++#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
++#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
++#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
++#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
++#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
++#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
++#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
++#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
++#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
++#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
++//DP0_DP_MSA_VBID_MISC
++#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
++#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
++#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
++#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
++#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
++#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
++#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
++#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
++#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
++#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
++#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
++#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
++#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
++#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
++#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
++#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
++//DP0_DP_SEC_METADATA_TRANSMISSION
++#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
++#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
++#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
++#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
++#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
++#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
++#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
++#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
++//DP0_DP_DSC_BYTES_PER_PIXEL
++#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
++#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
++//DP0_DP_ALPM_CNTL
++#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
++#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
++#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
++#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
++#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
++#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
++#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
++#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
++#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
++#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
++#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
++#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
++#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
++#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
++
++
++// addressBlock: dce_dc_dio_dig1_dispdec
++//DIG1_DIG_FE_CNTL
++#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
++#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
++#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
++#define DIG1_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
++#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
++#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
++#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
++#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
++#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
++#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
++#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
++#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
++#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
++#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
++#define DIG1_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
++#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
++#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
++#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
++#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
++#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
++#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
++#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
++//DIG1_DIG_OUTPUT_CRC_CNTL
++#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
++#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
++#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
++#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
++#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
++#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
++//DIG1_DIG_OUTPUT_CRC_RESULT
++#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
++#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
++//DIG1_DIG_CLOCK_PATTERN
++#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
++#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
++//DIG1_DIG_TEST_PATTERN
++#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
++#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
++#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
++#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
++#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
++#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
++#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
++#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
++#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
++#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
++#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
++#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
++//DIG1_DIG_RANDOM_PATTERN_SEED
++#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
++#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
++#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
++#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
++//DIG1_DIG_FIFO_STATUS
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                   0x10
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                     0x001F0000L
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
++#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
++//DIG1_HDMI_METADATA_PACKET_CONTROL
++#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
++#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
++#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
++#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
++#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
++#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
++#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
++#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
++//DIG1_HDMI_GENERIC_PACKET_CONTROL4
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
++//DIG1_HDMI_CONTROL
++#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
++#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
++#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
++#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
++#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
++#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
++#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
++#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
++#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
++#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
++#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
++#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
++#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
++#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
++#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
++#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
++#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
++#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
++#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
++#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
++//DIG1_HDMI_STATUS
++#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
++#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
++#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
++#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
++#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
++#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
++#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
++#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
++//DIG1_HDMI_AUDIO_PACKET_CONTROL
++#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
++#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                    0x8
++#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                    0x10
++#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
++#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                      0x00000100L
++#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK                                      0x001F0000L
++//DIG1_HDMI_ACR_PACKET_CONTROL
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
++#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
++//DIG1_HDMI_VBI_PACKET_CONTROL
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
++#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
++//DIG1_HDMI_INFOFRAME_CONTROL0
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
++#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
++//DIG1_HDMI_INFOFRAME_CONTROL1
++#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
++#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
++#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
++#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
++//DIG1_HDMI_GENERIC_PACKET_CONTROL0
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
++//DIG1_HDMI_GC
++#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
++#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
++#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
++#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
++#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
++#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
++#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
++#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
++#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
++#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
++//DIG1_AFMT_AUDIO_PACKET_CONTROL2
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                        0x0
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                      0x1
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                     0x8
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                       0x10
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                          0x18
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                           0x1c
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                          0x00000001L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                        0x00000002L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                       0x0000FF00L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                         0x00FF0000L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                            0x01000000L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                             0x10000000L
++//DIG1_AFMT_ISRC1_0
++#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT                                                            0x0
++#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT                                                          0x6
++#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT                                                             0x7
++#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK                                                              0x00000007L
++#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK                                                            0x00000040L
++#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK                                                               0x00000080L
++//DIG1_AFMT_ISRC1_1
++#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT                                                          0x0
++#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT                                                          0x8
++#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT                                                          0x10
++#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT                                                          0x18
++#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK                                                            0x000000FFL
++#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK                                                            0x0000FF00L
++#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK                                                            0x00FF0000L
++#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK                                                            0xFF000000L
++//DIG1_AFMT_ISRC1_2
++#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT                                                          0x0
++#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT                                                          0x8
++#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT                                                          0x10
++#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT                                                          0x18
++#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK                                                            0x000000FFL
++#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK                                                            0x0000FF00L
++#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK                                                            0x00FF0000L
++#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK                                                            0xFF000000L
++//DIG1_AFMT_ISRC1_3
++#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT                                                          0x0
++#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT                                                          0x8
++#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT                                                         0x10
++#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT                                                         0x18
++#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK                                                            0x000000FFL
++#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK                                                            0x0000FF00L
++#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK                                                           0x00FF0000L
++#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK                                                           0xFF000000L
++//DIG1_AFMT_ISRC1_4
++#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT                                                         0x0
++#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT                                                         0x8
++#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT                                                         0x10
++#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT                                                         0x18
++#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK                                                           0x000000FFL
++#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK                                                           0x0000FF00L
++#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK                                                           0x00FF0000L
++#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK                                                           0xFF000000L
++//DIG1_AFMT_ISRC2_0
++#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT                                                         0x0
++#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT                                                         0x8
++#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT                                                         0x10
++#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT                                                         0x18
++#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK                                                           0x000000FFL
++#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK                                                           0x0000FF00L
++#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK                                                           0x00FF0000L
++#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK                                                           0xFF000000L
++//DIG1_AFMT_ISRC2_1
++#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT                                                         0x0
++#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT                                                         0x8
++#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT                                                         0x10
++#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT                                                         0x18
++#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK                                                           0x000000FFL
++#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK                                                           0x0000FF00L
++#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK                                                           0x00FF0000L
++#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK                                                           0xFF000000L
++//DIG1_AFMT_ISRC2_2
++#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT                                                         0x0
++#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT                                                         0x8
++#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT                                                         0x10
++#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT                                                         0x18
++#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK                                                           0x000000FFL
++#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK                                                           0x0000FF00L
++#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK                                                           0x00FF0000L
++#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK                                                           0xFF000000L
++//DIG1_AFMT_ISRC2_3
++#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT                                                         0x0
++#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT                                                         0x8
++#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT                                                         0x10
++#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT                                                         0x18
++#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK                                                           0x000000FFL
++#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK                                                           0x0000FF00L
++#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK                                                           0x00FF0000L
++#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK                                                           0xFF000000L
++//DIG1_HDMI_GENERIC_PACKET_CONTROL2
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
++//DIG1_HDMI_GENERIC_PACKET_CONTROL3
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
++//DIG1_HDMI_DB_CONTROL
++#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
++#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
++#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
++#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
++#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
++#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
++#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
++#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
++#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
++#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
++#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
++#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
++#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
++#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
++#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
++#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
++//DIG1_DME_CONTROL
++#define DIG1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
++#define DIG1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
++#define DIG1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
++#define DIG1_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
++#define DIG1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
++#define DIG1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
++#define DIG1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
++#define DIG1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
++#define DIG1_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
++#define DIG1_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
++#define DIG1_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
++#define DIG1_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
++#define DIG1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
++#define DIG1_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
++//DIG1_AFMT_MPEG_INFO0
++#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT                                                  0x0
++#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT                                                       0x8
++#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT                                                       0x10
++#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT                                                       0x18
++#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK                                                    0x000000FFL
++#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK                                                         0x0000FF00L
++#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK                                                         0x00FF0000L
++#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK                                                         0xFF000000L
++//DIG1_AFMT_MPEG_INFO1
++#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT                                                       0x0
++#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT                                                        0x8
++#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT                                                        0xc
++#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK                                                         0x000000FFL
++#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK                                                          0x00000300L
++#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK                                                          0x00001000L
++//DIG1_AFMT_GENERIC_HDR
++#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT                                                        0x0
++#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT                                                        0x8
++#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT                                                        0x10
++#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT                                                        0x18
++#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK                                                          0x000000FFL
++#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK                                                          0x0000FF00L
++#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK                                                          0x00FF0000L
++#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK                                                          0xFF000000L
++//DIG1_AFMT_GENERIC_0
++#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT                                                        0x0
++#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT                                                        0x8
++#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT                                                        0x10
++#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT                                                        0x18
++#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK                                                          0x000000FFL
++#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK                                                          0x0000FF00L
++#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK                                                          0x00FF0000L
++#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK                                                          0xFF000000L
++//DIG1_AFMT_GENERIC_1
++#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT                                                        0x0
++#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT                                                        0x8
++#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT                                                        0x10
++#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT                                                        0x18
++#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK                                                          0x000000FFL
++#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK                                                          0x0000FF00L
++#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK                                                          0x00FF0000L
++#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK                                                          0xFF000000L
++//DIG1_AFMT_GENERIC_2
++#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT                                                        0x0
++#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT                                                        0x8
++#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT                                                       0x10
++#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT                                                       0x18
++#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK                                                          0x000000FFL
++#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK                                                          0x0000FF00L
++#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK                                                         0x00FF0000L
++#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK                                                         0xFF000000L
++//DIG1_AFMT_GENERIC_3
++#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT                                                       0x0
++#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT                                                       0x8
++#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT                                                       0x10
++#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT                                                       0x18
++#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK                                                         0x000000FFL
++#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK                                                         0x0000FF00L
++#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK                                                         0x00FF0000L
++#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK                                                         0xFF000000L
++//DIG1_AFMT_GENERIC_4
++#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT                                                       0x0
++#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT                                                       0x8
++#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT                                                       0x10
++#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT                                                       0x18
++#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK                                                         0x000000FFL
++#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK                                                         0x0000FF00L
++#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK                                                         0x00FF0000L
++#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK                                                         0xFF000000L
++//DIG1_AFMT_GENERIC_5
++#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT                                                       0x0
++#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT                                                       0x8
++#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT                                                       0x10
++#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT                                                       0x18
++#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK                                                         0x000000FFL
++#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK                                                         0x0000FF00L
++#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK                                                         0x00FF0000L
++#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK                                                         0xFF000000L
++//DIG1_AFMT_GENERIC_6
++#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT                                                       0x0
++#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT                                                       0x8
++#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT                                                       0x10
++#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT                                                       0x18
++#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK                                                         0x000000FFL
++#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK                                                         0x0000FF00L
++#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK                                                         0x00FF0000L
++#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK                                                         0xFF000000L
++//DIG1_AFMT_GENERIC_7
++#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT                                                       0x0
++#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT                                                       0x8
++#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT                                                       0x10
++#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT                                                       0x18
++#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK                                                         0x000000FFL
++#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK                                                         0x0000FF00L
++#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK                                                         0x00FF0000L
++#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK                                                         0xFF000000L
++//DIG1_HDMI_GENERIC_PACKET_CONTROL1
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
++//DIG1_HDMI_ACR_32_0
++#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
++#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
++//DIG1_HDMI_ACR_32_1
++#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
++#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
++//DIG1_HDMI_ACR_44_0
++#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
++#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
++//DIG1_HDMI_ACR_44_1
++#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
++#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
++//DIG1_HDMI_ACR_48_0
++#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
++#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
++//DIG1_HDMI_ACR_48_1
++#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
++#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
++//DIG1_HDMI_ACR_STATUS_0
++#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
++#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
++//DIG1_HDMI_ACR_STATUS_1
++#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
++#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
++//DIG1_AFMT_AUDIO_INFO0
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                                0x0
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                      0x8
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                      0xb
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                         0x10
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                     0x18
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                  0x000000FFL
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                        0x00000700L
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                        0x00007800L
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                           0x00FF0000L
++#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                       0x1F000000L
++//DIG1_AFMT_AUDIO_INFO1
++#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                      0x0
++#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                     0xb
++#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                  0xf
++#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                  0x10
++#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                        0x000000FFL
++#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                       0x00007800L
++#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                    0x00008000L
++#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                    0x00030000L
++//DIG1_AFMT_60958_0
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                             0x0
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                             0x1
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                             0x2
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                             0x3
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                          0x6
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                 0x8
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                 0x10
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                              0x14
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                            0x18
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                                0x1c
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                               0x00000001L
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                               0x00000002L
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                               0x00000004L
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                               0x00000038L
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                            0x000000C0L
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                   0x0000FF00L
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                   0x000F0000L
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                                0x00F00000L
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                              0x0F000000L
++#define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                  0x30000000L
++//DIG1_AFMT_60958_1
++#define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                   0x0
++#define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                   0x4
++#define DIG1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                          0x10
++#define DIG1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                          0x12
++#define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                              0x14
++#define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                     0x0000000FL
++#define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                     0x000000F0L
++#define DIG1_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                            0x00010000L
++#define DIG1_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                            0x00040000L
++#define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                                0x00F00000L
++//DIG1_AFMT_AUDIO_CRC_CONTROL
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                 0x0
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                               0x4
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                             0x8
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                             0xc
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                              0x10
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                   0x00000001L
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                 0x00000010L
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                               0x00000100L
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                               0x0000F000L
++#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                                0xFFFF0000L
++//DIG1_AFMT_RAMP_CONTROL0
++#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                   0x0
++#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                   0x1f
++#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                     0x00FFFFFFL
++#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                     0x80000000L
++//DIG1_AFMT_RAMP_CONTROL1
++#define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                   0x0
++#define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                            0x18
++#define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                     0x00FFFFFFL
++#define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                              0xFF000000L
++//DIG1_AFMT_RAMP_CONTROL2
++#define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                   0x0
++#define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                     0x00FFFFFFL
++//DIG1_AFMT_RAMP_CONTROL3
++#define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                   0x0
++#define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                     0x00FFFFFFL
++//DIG1_AFMT_60958_2
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                              0x0
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                              0x4
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                              0x8
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                              0xc
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                              0x10
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                              0x14
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                                0x0000000FL
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                                0x000000F0L
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                                0x00000F00L
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                                0x0000F000L
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                                0x000F0000L
++#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                                0x00F00000L
++//DIG1_AFMT_AUDIO_CRC_RESULT
++#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                                0x0
++#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                     0x8
++#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                  0x00000001L
++#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                       0xFFFFFF00L
++//DIG1_AFMT_STATUS
++#define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                            0x4
++#define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                           0x8
++#define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                     0x18
++#define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                     0x1e
++#define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                              0x00000010L
++#define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                             0x00000100L
++#define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                       0x01000000L
++#define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                       0x40000000L
++//DIG1_AFMT_AUDIO_PACKET_CONTROL
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                         0x0
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                 0xb
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                             0xc
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                           0xe
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                   0x17
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                        0x18
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                           0x1a
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                   0x1e
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                                0x1f
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                           0x00000001L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                   0x00000800L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                               0x00001000L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                             0x00004000L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                     0x00800000L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                          0x01000000L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                             0x04000000L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                     0x40000000L
++#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                  0x80000000L
++//DIG1_AFMT_VBI_PACKET_CONTROL
++#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT                                         0x8
++#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT                                            0x10
++#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT                                        0x11
++#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT                                               0x1c
++#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK                                           0x00000100L
++#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK                                              0x00010000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK                                          0x00020000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK                                                 0xF0000000L
++//DIG1_AFMT_INFOFRAME_CONTROL0
++#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                           0x6
++#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                           0x7
++#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT                                            0xa
++#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                             0x00000040L
++#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                             0x00000080L
++#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK                                              0x00000400L
++//DIG1_AFMT_AUDIO_SRC_CONTROL
++#define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                             0x0
++#define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                               0x00000007L
++//DIG1_DIG_BE_CNTL
++#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
++#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
++#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
++#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
++#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
++#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
++#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
++#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
++#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
++#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
++#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
++#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
++//DIG1_DIG_BE_EN_CNTL
++#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
++#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
++#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
++#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
++//DIG1_TMDS_CNTL
++#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
++#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
++//DIG1_TMDS_CONTROL_CHAR
++#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
++#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
++#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
++#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
++#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
++#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
++#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
++#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
++//DIG1_TMDS_CONTROL0_FEEDBACK
++#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
++#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
++#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
++#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
++//DIG1_TMDS_STEREOSYNC_CTL_SEL
++#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
++#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
++//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1
++#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
++#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
++#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
++#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
++//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3
++#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
++#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
++#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
++#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
++//DIG1_TMDS_CTL_BITS
++#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
++#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
++#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
++#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
++#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
++#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
++#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
++#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
++//DIG1_TMDS_DCBALANCER_CONTROL
++#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
++#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
++#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
++#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
++#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
++#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
++#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
++#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
++#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
++#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
++//DIG1_TMDS_SYNC_DCBALANCE_CHAR
++#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
++#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
++#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
++#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
++//DIG1_TMDS_CTL0_1_GEN_CNTL
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
++#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
++//DIG1_TMDS_CTL2_3_GEN_CNTL
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
++#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
++//DIG1_DIG_VERSION
++#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
++#define DIG1_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
++//DIG1_DIG_LANE_ENABLE
++#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT                                                              0x0
++#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT                                                              0x1
++#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT                                                              0x2
++#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT                                                              0x3
++#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT                                                               0x8
++#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN_MASK                                                                0x00000001L
++#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN_MASK                                                                0x00000002L
++#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN_MASK                                                                0x00000004L
++#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN_MASK                                                                0x00000008L
++#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN_MASK                                                                 0x00000100L
++//DIG1_AFMT_CNTL
++#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
++#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
++#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
++#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
++//DIG1_AFMT_VBI_PACKET_CONTROL1
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x1
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT                                  0x2
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x3
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT                                      0x4
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x5
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT                                  0x6
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x7
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT                                      0x8
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x9
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT                                  0xa
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xb
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT                                      0xc
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0xd
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT                                  0xe
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xf
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT                                      0x10
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x11
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT                                  0x12
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x13
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT                                      0x14
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT                                  0x16
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x17
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT                                      0x18
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x19
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT                                  0x1a
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1b
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT                                      0x1c
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x1d
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT                                  0x1e
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1f
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00000002L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK                                    0x00000004L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000008L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK                                        0x00000010L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00000020L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK                                    0x00000040L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000080L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK                                        0x00000100L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00000200L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK                                    0x00000400L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000800L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK                                        0x00001000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00002000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK                                    0x00004000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                            0x00008000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK                                        0x00010000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00020000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK                                    0x00040000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                            0x00080000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK                                        0x00100000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK                                    0x00400000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                            0x00800000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK                                        0x01000000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x02000000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK                                    0x04000000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                            0x08000000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK                                        0x10000000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x20000000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK                                    0x40000000L
++#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                            0x80000000L
++//DIG1_HDMI_GENERIC_PACKET_CONTROL5
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
++#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
++//DIG1_FORCE_DIG_DISABLE
++#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
++#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
++
++
++// addressBlock: dce_dc_dio_dp1_dispdec
++//DP1_DP_LINK_CNTL
++#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
++#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
++#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
++#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
++#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
++#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
++//DP1_DP_PIXEL_FORMAT
++#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
++#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
++#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
++#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
++#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
++#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
++//DP1_DP_MSA_COLORIMETRY
++#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
++#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
++//DP1_DP_CONFIG
++#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
++#define DP1_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
++//DP1_DP_VID_STREAM_CNTL
++#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
++#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
++#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
++#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
++#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
++#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
++#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
++#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
++//DP1_DP_STEER_FIFO
++#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
++#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
++#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
++#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
++#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
++#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
++#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
++#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
++#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
++#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
++#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
++#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
++#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
++#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
++//DP1_DP_MSA_MISC
++#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
++#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
++#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
++#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
++#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
++#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
++#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
++#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
++//DP1_DP_VID_TIMING
++#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
++#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
++#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
++#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
++#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
++#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
++#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
++#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
++#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
++#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
++//DP1_DP_VID_N
++#define DP1_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
++#define DP1_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
++//DP1_DP_VID_M
++#define DP1_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
++#define DP1_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
++//DP1_DP_LINK_FRAMING_CNTL
++#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
++#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
++#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
++#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
++#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
++#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
++//DP1_DP_HBR2_EYE_PATTERN
++#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
++#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
++//DP1_DP_VID_MSA_VBID
++#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
++#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
++#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
++#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
++//DP1_DP_VID_INTERRUPT_CNTL
++#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
++#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
++#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
++#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
++#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
++#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
++//DP1_DP_DPHY_CNTL
++#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
++#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
++#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
++#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
++#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
++#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
++#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
++#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
++#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
++#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
++#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
++#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
++#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
++#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
++#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
++#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
++#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
++#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
++//DP1_DP_DPHY_TRAINING_PATTERN_SEL
++#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
++#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
++//DP1_DP_DPHY_SYM0
++#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
++#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
++#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
++#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
++#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
++#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
++//DP1_DP_DPHY_SYM1
++#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
++#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
++#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
++#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
++#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
++#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
++//DP1_DP_DPHY_SYM2
++#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
++#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
++#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
++#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
++//DP1_DP_DPHY_8B10B_CNTL
++#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
++#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
++#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
++#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
++#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
++#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
++//DP1_DP_DPHY_PRBS_CNTL
++#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
++#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
++#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
++#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
++#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
++#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
++//DP1_DP_DPHY_SCRAM_CNTL
++#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
++#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
++#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
++#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
++#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
++#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
++#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
++#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
++//DP1_DP_DPHY_CRC_EN
++#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
++#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
++#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
++#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
++#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
++#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
++//DP1_DP_DPHY_CRC_CNTL
++#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
++#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
++#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
++#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
++#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
++#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
++//DP1_DP_DPHY_CRC_RESULT
++#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
++#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
++#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
++#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
++#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
++#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
++#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
++#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
++//DP1_DP_DPHY_CRC_MST_CNTL
++#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
++#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
++#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
++#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
++//DP1_DP_DPHY_CRC_MST_STATUS
++#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
++#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
++#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
++#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
++#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
++#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
++//DP1_DP_DPHY_FAST_TRAINING
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
++#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
++//DP1_DP_DPHY_FAST_TRAINING_STATUS
++#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
++#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
++#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
++#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
++#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
++#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
++#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
++#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
++//DP1_DP_SEC_CNTL
++#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
++#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
++#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
++#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
++#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
++#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
++#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
++#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
++#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
++#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
++#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
++#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
++#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
++//DP1_DP_SEC_CNTL1
++#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
++#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
++#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP1_DP_SEC_FRAMING1
++#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
++#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
++#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
++#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
++//DP1_DP_SEC_FRAMING2
++#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
++#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
++#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
++#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
++//DP1_DP_SEC_FRAMING3
++#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
++#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
++#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
++#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
++//DP1_DP_SEC_FRAMING4
++#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
++#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
++#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
++#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
++#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
++#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
++#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
++#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
++#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
++#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
++//DP1_DP_SEC_AUD_N
++#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
++#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
++//DP1_DP_SEC_AUD_N_READBACK
++#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
++#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
++//DP1_DP_SEC_AUD_M
++#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
++#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
++//DP1_DP_SEC_AUD_M_READBACK
++#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
++#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
++//DP1_DP_SEC_TIMESTAMP
++#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
++#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
++//DP1_DP_SEC_PACKET_CNTL
++#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
++#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
++#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
++#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
++#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
++#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
++#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
++#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
++//DP1_DP_MSE_RATE_CNTL
++#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
++#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
++#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
++#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
++//DP1_DP_MSE_RATE_UPDATE
++#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
++#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
++//DP1_DP_MSE_SAT0
++#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
++#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
++#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
++#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
++#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
++#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
++#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
++#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
++//DP1_DP_MSE_SAT1
++#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
++#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
++#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
++#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
++#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
++#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
++#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
++#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
++//DP1_DP_MSE_SAT2
++#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
++#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
++#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
++#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
++#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
++#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
++#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
++#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
++//DP1_DP_MSE_SAT_UPDATE
++#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
++#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
++#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
++#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
++//DP1_DP_MSE_LINK_TIMING
++#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
++#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
++#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
++#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
++//DP1_DP_MSE_MISC_CNTL
++#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
++#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
++#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
++#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
++#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
++#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
++//DP1_DP_DPHY_BS_SR_SWAP_CNTL
++#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
++#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
++#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
++#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
++#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
++#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
++//DP1_DP_DPHY_HBR2_PATTERN_CONTROL
++#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
++#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
++//DP1_DP_MSE_SAT0_STATUS
++#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
++#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
++#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
++#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
++#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
++#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
++#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
++#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
++//DP1_DP_MSE_SAT1_STATUS
++#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
++#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
++#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
++#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
++#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
++#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
++#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
++#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
++//DP1_DP_MSE_SAT2_STATUS
++#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
++#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
++#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
++#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
++#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
++#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
++#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
++#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
++//DP1_DP_MSA_TIMING_PARAM1
++#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
++#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
++#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
++#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
++//DP1_DP_MSA_TIMING_PARAM2
++#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
++#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
++#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
++#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
++//DP1_DP_MSA_TIMING_PARAM3
++#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
++#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
++#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
++#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
++#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
++#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
++#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
++#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
++//DP1_DP_MSA_TIMING_PARAM4
++#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
++#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
++#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
++#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
++//DP1_DP_MSO_CNTL
++#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
++#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
++#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
++#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
++#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
++#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
++#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
++#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
++#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
++#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
++#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
++#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
++#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
++#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
++#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
++#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
++//DP1_DP_MSO_CNTL1
++#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
++#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
++#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
++#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
++#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
++#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
++#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
++#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
++#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
++#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
++#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
++#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
++#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
++#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
++#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
++#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
++//DP1_DP_DSC_CNTL
++#define DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
++#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
++#define DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
++#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
++//DP1_DP_SEC_CNTL2
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT                                                              0x1c
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
++#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK                                                                0x10000000L
++//DP1_DP_SEC_CNTL3
++#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
++#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
++#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
++#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP1_DP_SEC_CNTL4
++#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
++#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
++#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
++#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP1_DP_SEC_CNTL5
++#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
++#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
++#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
++#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP1_DP_SEC_CNTL6
++#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
++#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
++//DP1_DP_SEC_CNTL7
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
++#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
++//DP1_DP_DB_CNTL
++#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
++#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
++#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
++#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
++#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
++#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
++#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
++#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
++#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
++#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
++#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
++#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
++#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
++#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
++#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
++#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
++//DP1_DP_MSA_VBID_MISC
++#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
++#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
++#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
++#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
++#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
++#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
++#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
++#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
++#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
++#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
++#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
++#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
++#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
++#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
++#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
++#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
++//DP1_DP_SEC_METADATA_TRANSMISSION
++#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
++#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
++#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
++#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
++#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
++#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
++#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
++#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
++//DP1_DP_DSC_BYTES_PER_PIXEL
++#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
++#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
++//DP1_DP_ALPM_CNTL
++#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
++#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
++#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
++#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
++#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
++#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
++#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
++#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
++#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
++#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
++#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
++#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
++#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
++#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
++
++
++// addressBlock: dce_dc_dio_dig2_dispdec
++//DIG2_DIG_FE_CNTL
++#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
++#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
++#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
++#define DIG2_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
++#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
++#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
++#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
++#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
++#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
++#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
++#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
++#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
++#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
++#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
++#define DIG2_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
++#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
++#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
++#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
++#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
++#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
++#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
++#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
++//DIG2_DIG_OUTPUT_CRC_CNTL
++#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
++#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
++#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
++#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
++#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
++#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
++//DIG2_DIG_OUTPUT_CRC_RESULT
++#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
++#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
++//DIG2_DIG_CLOCK_PATTERN
++#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
++#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
++//DIG2_DIG_TEST_PATTERN
++#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
++#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
++#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
++#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
++#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
++#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
++#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
++#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
++#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
++#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
++#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
++#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
++//DIG2_DIG_RANDOM_PATTERN_SEED
++#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
++#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
++#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
++#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
++//DIG2_DIG_FIFO_STATUS
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                   0x10
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                     0x001F0000L
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
++#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
++//DIG2_HDMI_METADATA_PACKET_CONTROL
++#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
++#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
++#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
++#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
++#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
++#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
++#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
++#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
++//DIG2_HDMI_GENERIC_PACKET_CONTROL4
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
++//DIG2_HDMI_CONTROL
++#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
++#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
++#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
++#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
++#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
++#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
++#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
++#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
++#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
++#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
++#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
++#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
++#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
++#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
++#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
++#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
++#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
++#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
++#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
++#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
++//DIG2_HDMI_STATUS
++#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
++#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
++#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
++#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
++#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
++#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
++#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
++#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
++//DIG2_HDMI_AUDIO_PACKET_CONTROL
++#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
++#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                    0x8
++#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                    0x10
++#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
++#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                      0x00000100L
++#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK                                      0x001F0000L
++//DIG2_HDMI_ACR_PACKET_CONTROL
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
++#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
++//DIG2_HDMI_VBI_PACKET_CONTROL
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
++#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
++//DIG2_HDMI_INFOFRAME_CONTROL0
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
++#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
++//DIG2_HDMI_INFOFRAME_CONTROL1
++#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
++#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
++#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
++#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
++//DIG2_HDMI_GENERIC_PACKET_CONTROL0
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
++//DIG2_HDMI_GC
++#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
++#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
++#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
++#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
++#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
++#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
++#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
++#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
++#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
++#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
++//DIG2_AFMT_AUDIO_PACKET_CONTROL2
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                        0x0
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                      0x1
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                     0x8
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                       0x10
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                          0x18
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                           0x1c
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                          0x00000001L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                        0x00000002L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                       0x0000FF00L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                         0x00FF0000L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                            0x01000000L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                             0x10000000L
++//DIG2_AFMT_ISRC1_0
++#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT                                                            0x0
++#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT                                                          0x6
++#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT                                                             0x7
++#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK                                                              0x00000007L
++#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK                                                            0x00000040L
++#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK                                                               0x00000080L
++//DIG2_AFMT_ISRC1_1
++#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT                                                          0x0
++#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT                                                          0x8
++#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT                                                          0x10
++#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT                                                          0x18
++#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK                                                            0x000000FFL
++#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK                                                            0x0000FF00L
++#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK                                                            0x00FF0000L
++#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK                                                            0xFF000000L
++//DIG2_AFMT_ISRC1_2
++#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT                                                          0x0
++#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT                                                          0x8
++#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT                                                          0x10
++#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT                                                          0x18
++#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK                                                            0x000000FFL
++#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK                                                            0x0000FF00L
++#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK                                                            0x00FF0000L
++#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK                                                            0xFF000000L
++//DIG2_AFMT_ISRC1_3
++#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT                                                          0x0
++#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT                                                          0x8
++#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT                                                         0x10
++#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT                                                         0x18
++#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK                                                            0x000000FFL
++#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK                                                            0x0000FF00L
++#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK                                                           0x00FF0000L
++#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK                                                           0xFF000000L
++//DIG2_AFMT_ISRC1_4
++#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT                                                         0x0
++#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT                                                         0x8
++#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT                                                         0x10
++#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT                                                         0x18
++#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK                                                           0x000000FFL
++#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK                                                           0x0000FF00L
++#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK                                                           0x00FF0000L
++#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK                                                           0xFF000000L
++//DIG2_AFMT_ISRC2_0
++#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT                                                         0x0
++#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT                                                         0x8
++#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT                                                         0x10
++#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT                                                         0x18
++#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK                                                           0x000000FFL
++#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK                                                           0x0000FF00L
++#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK                                                           0x00FF0000L
++#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK                                                           0xFF000000L
++//DIG2_AFMT_ISRC2_1
++#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT                                                         0x0
++#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT                                                         0x8
++#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT                                                         0x10
++#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT                                                         0x18
++#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK                                                           0x000000FFL
++#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK                                                           0x0000FF00L
++#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK                                                           0x00FF0000L
++#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK                                                           0xFF000000L
++//DIG2_AFMT_ISRC2_2
++#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT                                                         0x0
++#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT                                                         0x8
++#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT                                                         0x10
++#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT                                                         0x18
++#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK                                                           0x000000FFL
++#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK                                                           0x0000FF00L
++#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK                                                           0x00FF0000L
++#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK                                                           0xFF000000L
++//DIG2_AFMT_ISRC2_3
++#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT                                                         0x0
++#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT                                                         0x8
++#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT                                                         0x10
++#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT                                                         0x18
++#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK                                                           0x000000FFL
++#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK                                                           0x0000FF00L
++#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK                                                           0x00FF0000L
++#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK                                                           0xFF000000L
++//DIG2_HDMI_GENERIC_PACKET_CONTROL2
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
++//DIG2_HDMI_GENERIC_PACKET_CONTROL3
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
++//DIG2_HDMI_DB_CONTROL
++#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
++#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
++#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
++#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
++#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
++#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
++#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
++#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
++#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
++#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
++#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
++#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
++#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
++#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
++#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
++#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
++//DIG2_DME_CONTROL
++#define DIG2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
++#define DIG2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
++#define DIG2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
++#define DIG2_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
++#define DIG2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
++#define DIG2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
++#define DIG2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
++#define DIG2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
++#define DIG2_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
++#define DIG2_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
++#define DIG2_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
++#define DIG2_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
++#define DIG2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
++#define DIG2_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
++//DIG2_AFMT_MPEG_INFO0
++#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT                                                  0x0
++#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT                                                       0x8
++#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT                                                       0x10
++#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT                                                       0x18
++#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK                                                    0x000000FFL
++#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK                                                         0x0000FF00L
++#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK                                                         0x00FF0000L
++#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK                                                         0xFF000000L
++//DIG2_AFMT_MPEG_INFO1
++#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT                                                       0x0
++#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT                                                        0x8
++#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT                                                        0xc
++#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK                                                         0x000000FFL
++#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK                                                          0x00000300L
++#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK                                                          0x00001000L
++//DIG2_AFMT_GENERIC_HDR
++#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT                                                        0x0
++#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT                                                        0x8
++#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT                                                        0x10
++#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT                                                        0x18
++#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK                                                          0x000000FFL
++#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK                                                          0x0000FF00L
++#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK                                                          0x00FF0000L
++#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK                                                          0xFF000000L
++//DIG2_AFMT_GENERIC_0
++#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT                                                        0x0
++#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT                                                        0x8
++#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT                                                        0x10
++#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT                                                        0x18
++#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK                                                          0x000000FFL
++#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK                                                          0x0000FF00L
++#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK                                                          0x00FF0000L
++#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK                                                          0xFF000000L
++//DIG2_AFMT_GENERIC_1
++#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT                                                        0x0
++#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT                                                        0x8
++#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT                                                        0x10
++#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT                                                        0x18
++#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK                                                          0x000000FFL
++#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK                                                          0x0000FF00L
++#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK                                                          0x00FF0000L
++#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK                                                          0xFF000000L
++//DIG2_AFMT_GENERIC_2
++#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT                                                        0x0
++#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT                                                        0x8
++#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT                                                       0x10
++#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT                                                       0x18
++#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK                                                          0x000000FFL
++#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK                                                          0x0000FF00L
++#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK                                                         0x00FF0000L
++#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK                                                         0xFF000000L
++//DIG2_AFMT_GENERIC_3
++#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT                                                       0x0
++#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT                                                       0x8
++#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT                                                       0x10
++#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT                                                       0x18
++#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK                                                         0x000000FFL
++#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK                                                         0x0000FF00L
++#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK                                                         0x00FF0000L
++#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK                                                         0xFF000000L
++//DIG2_AFMT_GENERIC_4
++#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT                                                       0x0
++#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT                                                       0x8
++#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT                                                       0x10
++#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT                                                       0x18
++#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK                                                         0x000000FFL
++#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK                                                         0x0000FF00L
++#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK                                                         0x00FF0000L
++#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK                                                         0xFF000000L
++//DIG2_AFMT_GENERIC_5
++#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT                                                       0x0
++#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT                                                       0x8
++#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT                                                       0x10
++#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT                                                       0x18
++#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK                                                         0x000000FFL
++#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK                                                         0x0000FF00L
++#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK                                                         0x00FF0000L
++#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK                                                         0xFF000000L
++//DIG2_AFMT_GENERIC_6
++#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT                                                       0x0
++#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT                                                       0x8
++#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT                                                       0x10
++#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT                                                       0x18
++#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK                                                         0x000000FFL
++#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK                                                         0x0000FF00L
++#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK                                                         0x00FF0000L
++#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK                                                         0xFF000000L
++//DIG2_AFMT_GENERIC_7
++#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT                                                       0x0
++#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT                                                       0x8
++#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT                                                       0x10
++#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT                                                       0x18
++#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK                                                         0x000000FFL
++#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK                                                         0x0000FF00L
++#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK                                                         0x00FF0000L
++#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK                                                         0xFF000000L
++//DIG2_HDMI_GENERIC_PACKET_CONTROL1
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
++//DIG2_HDMI_ACR_32_0
++#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
++#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
++//DIG2_HDMI_ACR_32_1
++#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
++#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
++//DIG2_HDMI_ACR_44_0
++#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
++#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
++//DIG2_HDMI_ACR_44_1
++#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
++#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
++//DIG2_HDMI_ACR_48_0
++#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
++#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
++//DIG2_HDMI_ACR_48_1
++#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
++#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
++//DIG2_HDMI_ACR_STATUS_0
++#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
++#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
++//DIG2_HDMI_ACR_STATUS_1
++#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
++#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
++//DIG2_AFMT_AUDIO_INFO0
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                                0x0
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                      0x8
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                      0xb
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                         0x10
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                     0x18
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                  0x000000FFL
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                        0x00000700L
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                        0x00007800L
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                           0x00FF0000L
++#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                       0x1F000000L
++//DIG2_AFMT_AUDIO_INFO1
++#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                      0x0
++#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                     0xb
++#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                  0xf
++#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                  0x10
++#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                        0x000000FFL
++#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                       0x00007800L
++#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                    0x00008000L
++#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                    0x00030000L
++//DIG2_AFMT_60958_0
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                             0x0
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                             0x1
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                             0x2
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                             0x3
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                          0x6
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                 0x8
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                 0x10
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                              0x14
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                            0x18
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                                0x1c
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                               0x00000001L
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                               0x00000002L
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                               0x00000004L
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                               0x00000038L
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                            0x000000C0L
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                   0x0000FF00L
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                   0x000F0000L
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                                0x00F00000L
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                              0x0F000000L
++#define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                  0x30000000L
++//DIG2_AFMT_60958_1
++#define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                   0x0
++#define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                   0x4
++#define DIG2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                          0x10
++#define DIG2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                          0x12
++#define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                              0x14
++#define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                     0x0000000FL
++#define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                     0x000000F0L
++#define DIG2_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                            0x00010000L
++#define DIG2_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                            0x00040000L
++#define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                                0x00F00000L
++//DIG2_AFMT_AUDIO_CRC_CONTROL
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                 0x0
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                               0x4
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                             0x8
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                             0xc
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                              0x10
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                   0x00000001L
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                 0x00000010L
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                               0x00000100L
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                               0x0000F000L
++#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                                0xFFFF0000L
++//DIG2_AFMT_RAMP_CONTROL0
++#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                   0x0
++#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                   0x1f
++#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                     0x00FFFFFFL
++#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                     0x80000000L
++//DIG2_AFMT_RAMP_CONTROL1
++#define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                   0x0
++#define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                            0x18
++#define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                     0x00FFFFFFL
++#define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                              0xFF000000L
++//DIG2_AFMT_RAMP_CONTROL2
++#define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                   0x0
++#define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                     0x00FFFFFFL
++//DIG2_AFMT_RAMP_CONTROL3
++#define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                   0x0
++#define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                     0x00FFFFFFL
++//DIG2_AFMT_60958_2
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                              0x0
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                              0x4
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                              0x8
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                              0xc
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                              0x10
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                              0x14
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                                0x0000000FL
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                                0x000000F0L
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                                0x00000F00L
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                                0x0000F000L
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                                0x000F0000L
++#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                                0x00F00000L
++//DIG2_AFMT_AUDIO_CRC_RESULT
++#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                                0x0
++#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                     0x8
++#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                  0x00000001L
++#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                       0xFFFFFF00L
++//DIG2_AFMT_STATUS
++#define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                            0x4
++#define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                           0x8
++#define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                     0x18
++#define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                     0x1e
++#define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                              0x00000010L
++#define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                             0x00000100L
++#define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                       0x01000000L
++#define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                       0x40000000L
++//DIG2_AFMT_AUDIO_PACKET_CONTROL
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                         0x0
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                 0xb
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                             0xc
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                           0xe
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                   0x17
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                        0x18
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                           0x1a
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                   0x1e
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                                0x1f
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                           0x00000001L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                   0x00000800L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                               0x00001000L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                             0x00004000L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                     0x00800000L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                          0x01000000L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                             0x04000000L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                     0x40000000L
++#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                  0x80000000L
++//DIG2_AFMT_VBI_PACKET_CONTROL
++#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT                                         0x8
++#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT                                            0x10
++#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT                                        0x11
++#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT                                               0x1c
++#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK                                           0x00000100L
++#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK                                              0x00010000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK                                          0x00020000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK                                                 0xF0000000L
++//DIG2_AFMT_INFOFRAME_CONTROL0
++#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                           0x6
++#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                           0x7
++#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT                                            0xa
++#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                             0x00000040L
++#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                             0x00000080L
++#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK                                              0x00000400L
++//DIG2_AFMT_AUDIO_SRC_CONTROL
++#define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                             0x0
++#define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                               0x00000007L
++//DIG2_DIG_BE_CNTL
++#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
++#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
++#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
++#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
++#define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
++#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
++#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
++#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
++#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
++#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
++#define DIG2_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
++#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
++//DIG2_DIG_BE_EN_CNTL
++#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
++#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
++#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
++#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
++//DIG2_TMDS_CNTL
++#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
++#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
++//DIG2_TMDS_CONTROL_CHAR
++#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
++#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
++#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
++#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
++#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
++#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
++#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
++#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
++//DIG2_TMDS_CONTROL0_FEEDBACK
++#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
++#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
++#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
++#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
++//DIG2_TMDS_STEREOSYNC_CTL_SEL
++#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
++#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
++//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1
++#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
++#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
++#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
++#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
++//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3
++#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
++#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
++#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
++#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
++//DIG2_TMDS_CTL_BITS
++#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
++#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
++#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
++#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
++#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
++#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
++#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
++#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
++//DIG2_TMDS_DCBALANCER_CONTROL
++#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
++#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
++#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
++#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
++#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
++#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
++#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
++#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
++#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
++#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
++//DIG2_TMDS_SYNC_DCBALANCE_CHAR
++#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
++#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
++#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
++#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
++//DIG2_TMDS_CTL0_1_GEN_CNTL
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
++#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
++//DIG2_TMDS_CTL2_3_GEN_CNTL
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
++#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
++//DIG2_DIG_VERSION
++#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
++#define DIG2_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
++//DIG2_DIG_LANE_ENABLE
++#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT                                                              0x0
++#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT                                                              0x1
++#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT                                                              0x2
++#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT                                                              0x3
++#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT                                                               0x8
++#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN_MASK                                                                0x00000001L
++#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN_MASK                                                                0x00000002L
++#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN_MASK                                                                0x00000004L
++#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN_MASK                                                                0x00000008L
++#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN_MASK                                                                 0x00000100L
++//DIG2_AFMT_CNTL
++#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
++#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
++#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
++#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
++//DIG2_AFMT_VBI_PACKET_CONTROL1
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x1
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT                                  0x2
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x3
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT                                      0x4
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x5
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT                                  0x6
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x7
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT                                      0x8
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x9
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT                                  0xa
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xb
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT                                      0xc
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0xd
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT                                  0xe
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xf
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT                                      0x10
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x11
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT                                  0x12
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x13
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT                                      0x14
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT                                  0x16
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x17
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT                                      0x18
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x19
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT                                  0x1a
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1b
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT                                      0x1c
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x1d
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT                                  0x1e
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1f
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00000002L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK                                    0x00000004L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000008L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK                                        0x00000010L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00000020L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK                                    0x00000040L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000080L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK                                        0x00000100L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00000200L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK                                    0x00000400L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000800L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK                                        0x00001000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00002000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK                                    0x00004000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                            0x00008000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK                                        0x00010000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00020000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK                                    0x00040000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                            0x00080000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK                                        0x00100000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK                                    0x00400000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                            0x00800000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK                                        0x01000000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x02000000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK                                    0x04000000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                            0x08000000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK                                        0x10000000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x20000000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK                                    0x40000000L
++#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                            0x80000000L
++//DIG2_HDMI_GENERIC_PACKET_CONTROL5
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
++#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
++//DIG2_FORCE_DIG_DISABLE
++#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
++#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
++
++
++// addressBlock: dce_dc_dio_dp2_dispdec
++//DP2_DP_LINK_CNTL
++#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
++#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
++#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
++#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
++#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
++#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
++//DP2_DP_PIXEL_FORMAT
++#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
++#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
++#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
++#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
++#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
++#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
++//DP2_DP_MSA_COLORIMETRY
++#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
++#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
++//DP2_DP_CONFIG
++#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
++#define DP2_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
++//DP2_DP_VID_STREAM_CNTL
++#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
++#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
++#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
++#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
++#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
++#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
++#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
++#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
++//DP2_DP_STEER_FIFO
++#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
++#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
++#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
++#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
++#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
++#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
++#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
++#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
++#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
++#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
++#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
++#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
++#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
++#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
++//DP2_DP_MSA_MISC
++#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
++#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
++#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
++#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
++#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
++#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
++#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
++#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
++//DP2_DP_VID_TIMING
++#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
++#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
++#define DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
++#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
++#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
++#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
++#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
++#define DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
++#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
++#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
++//DP2_DP_VID_N
++#define DP2_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
++#define DP2_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
++//DP2_DP_VID_M
++#define DP2_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
++#define DP2_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
++//DP2_DP_LINK_FRAMING_CNTL
++#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
++#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
++#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
++#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
++#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
++#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
++//DP2_DP_HBR2_EYE_PATTERN
++#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
++#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
++//DP2_DP_VID_MSA_VBID
++#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
++#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
++#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
++#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
++//DP2_DP_VID_INTERRUPT_CNTL
++#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
++#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
++#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
++#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
++#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
++#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
++//DP2_DP_DPHY_CNTL
++#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
++#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
++#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
++#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
++#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
++#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
++#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
++#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
++#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
++#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
++#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
++#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
++#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
++#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
++#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
++#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
++#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
++#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
++//DP2_DP_DPHY_TRAINING_PATTERN_SEL
++#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
++#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
++//DP2_DP_DPHY_SYM0
++#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
++#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
++#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
++#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
++#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
++#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
++//DP2_DP_DPHY_SYM1
++#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
++#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
++#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
++#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
++#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
++#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
++//DP2_DP_DPHY_SYM2
++#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
++#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
++#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
++#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
++//DP2_DP_DPHY_8B10B_CNTL
++#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
++#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
++#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
++#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
++#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
++#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
++//DP2_DP_DPHY_PRBS_CNTL
++#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
++#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
++#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
++#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
++#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
++#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
++//DP2_DP_DPHY_SCRAM_CNTL
++#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
++#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
++#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
++#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
++#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
++#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
++#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
++#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
++//DP2_DP_DPHY_CRC_EN
++#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
++#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
++#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
++#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
++#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
++#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
++//DP2_DP_DPHY_CRC_CNTL
++#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
++#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
++#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
++#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
++#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
++#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
++//DP2_DP_DPHY_CRC_RESULT
++#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
++#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
++#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
++#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
++#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
++#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
++#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
++#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
++//DP2_DP_DPHY_CRC_MST_CNTL
++#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
++#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
++#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
++#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
++//DP2_DP_DPHY_CRC_MST_STATUS
++#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
++#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
++#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
++#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
++#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
++#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
++//DP2_DP_DPHY_FAST_TRAINING
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
++#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
++//DP2_DP_DPHY_FAST_TRAINING_STATUS
++#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
++#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
++#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
++#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
++#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
++#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
++#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
++#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
++//DP2_DP_SEC_CNTL
++#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
++#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
++#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
++#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
++#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
++#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
++#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
++#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
++#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
++#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
++#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
++#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
++#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
++//DP2_DP_SEC_CNTL1
++#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
++#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
++#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP2_DP_SEC_FRAMING1
++#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
++#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
++#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
++#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
++//DP2_DP_SEC_FRAMING2
++#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
++#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
++#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
++#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
++//DP2_DP_SEC_FRAMING3
++#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
++#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
++#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
++#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
++//DP2_DP_SEC_FRAMING4
++#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
++#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
++#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
++#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
++#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
++#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
++#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
++#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
++#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
++#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
++//DP2_DP_SEC_AUD_N
++#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
++#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
++//DP2_DP_SEC_AUD_N_READBACK
++#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
++#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
++//DP2_DP_SEC_AUD_M
++#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
++#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
++//DP2_DP_SEC_AUD_M_READBACK
++#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
++#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
++//DP2_DP_SEC_TIMESTAMP
++#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
++#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
++//DP2_DP_SEC_PACKET_CNTL
++#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
++#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
++#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
++#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
++#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
++#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
++#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
++#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
++//DP2_DP_MSE_RATE_CNTL
++#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
++#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
++#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
++#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
++//DP2_DP_MSE_RATE_UPDATE
++#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
++#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
++//DP2_DP_MSE_SAT0
++#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
++#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
++#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
++#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
++#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
++#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
++#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
++#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
++//DP2_DP_MSE_SAT1
++#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
++#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
++#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
++#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
++#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
++#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
++#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
++#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
++//DP2_DP_MSE_SAT2
++#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
++#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
++#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
++#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
++#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
++#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
++#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
++#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
++//DP2_DP_MSE_SAT_UPDATE
++#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
++#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
++#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
++#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
++//DP2_DP_MSE_LINK_TIMING
++#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
++#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
++#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
++#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
++//DP2_DP_MSE_MISC_CNTL
++#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
++#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
++#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
++#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
++#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
++#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
++//DP2_DP_DPHY_BS_SR_SWAP_CNTL
++#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
++#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
++#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
++#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
++#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
++#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
++//DP2_DP_DPHY_HBR2_PATTERN_CONTROL
++#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
++#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
++//DP2_DP_MSE_SAT0_STATUS
++#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
++#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
++#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
++#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
++#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
++#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
++#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
++#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
++//DP2_DP_MSE_SAT1_STATUS
++#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
++#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
++#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
++#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
++#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
++#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
++#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
++#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
++//DP2_DP_MSE_SAT2_STATUS
++#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
++#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
++#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
++#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
++#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
++#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
++#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
++#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
++//DP2_DP_MSA_TIMING_PARAM1
++#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
++#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
++#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
++#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
++//DP2_DP_MSA_TIMING_PARAM2
++#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
++#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
++#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
++#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
++//DP2_DP_MSA_TIMING_PARAM3
++#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
++#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
++#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
++#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
++#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
++#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
++#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
++#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
++//DP2_DP_MSA_TIMING_PARAM4
++#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
++#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
++#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
++#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
++//DP2_DP_MSO_CNTL
++#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
++#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
++#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
++#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
++#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
++#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
++#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
++#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
++#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
++#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
++#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
++#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
++#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
++#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
++#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
++#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
++//DP2_DP_MSO_CNTL1
++#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
++#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
++#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
++#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
++#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
++#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
++#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
++#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
++#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
++#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
++#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
++#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
++#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
++#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
++#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
++#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
++//DP2_DP_DSC_CNTL
++#define DP2_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
++#define DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
++#define DP2_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
++#define DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
++//DP2_DP_SEC_CNTL2
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT                                                              0x1c
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
++#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK                                                                0x10000000L
++//DP2_DP_SEC_CNTL3
++#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
++#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
++#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
++#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP2_DP_SEC_CNTL4
++#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
++#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
++#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
++#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP2_DP_SEC_CNTL5
++#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
++#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
++#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
++#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP2_DP_SEC_CNTL6
++#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
++#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
++//DP2_DP_SEC_CNTL7
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
++#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
++//DP2_DP_DB_CNTL
++#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
++#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
++#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
++#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
++#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
++#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
++#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
++#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
++#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
++#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
++#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
++#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
++#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
++#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
++#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
++#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
++//DP2_DP_MSA_VBID_MISC
++#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
++#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
++#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
++#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
++#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
++#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
++#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
++#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
++#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
++#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
++#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
++#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
++#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
++#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
++#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
++#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
++//DP2_DP_SEC_METADATA_TRANSMISSION
++#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
++#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
++#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
++#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
++#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
++#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
++#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
++#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
++//DP2_DP_DSC_BYTES_PER_PIXEL
++#define DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
++#define DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
++//DP2_DP_ALPM_CNTL
++#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
++#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
++#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
++#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
++#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
++#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
++#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
++#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
++#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
++#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
++#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
++#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
++#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
++#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
++
++
++// addressBlock: dce_dc_dio_dig3_dispdec
++//DIG3_DIG_FE_CNTL
++#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
++#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
++#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
++#define DIG3_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
++#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
++#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
++#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
++#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
++#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
++#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
++#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
++#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
++#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
++#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
++#define DIG3_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
++#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
++#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
++#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
++#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
++#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
++#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
++#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
++//DIG3_DIG_OUTPUT_CRC_CNTL
++#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
++#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
++#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
++#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
++#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
++#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
++//DIG3_DIG_OUTPUT_CRC_RESULT
++#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
++#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
++//DIG3_DIG_CLOCK_PATTERN
++#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
++#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
++//DIG3_DIG_TEST_PATTERN
++#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
++#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
++#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
++#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
++#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
++#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
++#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
++#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
++#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
++#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
++#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
++#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
++//DIG3_DIG_RANDOM_PATTERN_SEED
++#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
++#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
++#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
++#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
++//DIG3_DIG_FIFO_STATUS
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                   0x10
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                     0x001F0000L
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
++#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
++//DIG3_HDMI_METADATA_PACKET_CONTROL
++#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
++#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
++#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
++#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
++#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
++#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
++#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
++#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
++//DIG3_HDMI_GENERIC_PACKET_CONTROL4
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
++//DIG3_HDMI_CONTROL
++#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
++#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
++#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
++#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
++#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
++#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
++#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
++#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
++#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
++#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
++#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
++#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
++#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
++#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
++#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
++#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
++#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
++#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
++#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
++#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
++//DIG3_HDMI_STATUS
++#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
++#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
++#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
++#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
++#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
++#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
++#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
++#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
++//DIG3_HDMI_AUDIO_PACKET_CONTROL
++#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
++#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                    0x8
++#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                    0x10
++#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
++#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                      0x00000100L
++#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK                                      0x001F0000L
++//DIG3_HDMI_ACR_PACKET_CONTROL
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
++#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
++//DIG3_HDMI_VBI_PACKET_CONTROL
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
++#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
++//DIG3_HDMI_INFOFRAME_CONTROL0
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
++#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
++//DIG3_HDMI_INFOFRAME_CONTROL1
++#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
++#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
++#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
++#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
++//DIG3_HDMI_GENERIC_PACKET_CONTROL0
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
++//DIG3_HDMI_GC
++#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
++#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
++#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
++#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
++#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
++#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
++#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
++#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
++#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
++#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
++//DIG3_AFMT_AUDIO_PACKET_CONTROL2
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                        0x0
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                      0x1
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                     0x8
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                       0x10
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                          0x18
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                           0x1c
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                          0x00000001L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                        0x00000002L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                       0x0000FF00L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                         0x00FF0000L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                            0x01000000L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                             0x10000000L
++//DIG3_AFMT_ISRC1_0
++#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT                                                            0x0
++#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT                                                          0x6
++#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT                                                             0x7
++#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK                                                              0x00000007L
++#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK                                                            0x00000040L
++#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK                                                               0x00000080L
++//DIG3_AFMT_ISRC1_1
++#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT                                                          0x0
++#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT                                                          0x8
++#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT                                                          0x10
++#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT                                                          0x18
++#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK                                                            0x000000FFL
++#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK                                                            0x0000FF00L
++#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK                                                            0x00FF0000L
++#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK                                                            0xFF000000L
++//DIG3_AFMT_ISRC1_2
++#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT                                                          0x0
++#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT                                                          0x8
++#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT                                                          0x10
++#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT                                                          0x18
++#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK                                                            0x000000FFL
++#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK                                                            0x0000FF00L
++#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK                                                            0x00FF0000L
++#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK                                                            0xFF000000L
++//DIG3_AFMT_ISRC1_3
++#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT                                                          0x0
++#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT                                                          0x8
++#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT                                                         0x10
++#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT                                                         0x18
++#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK                                                            0x000000FFL
++#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK                                                            0x0000FF00L
++#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK                                                           0x00FF0000L
++#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK                                                           0xFF000000L
++//DIG3_AFMT_ISRC1_4
++#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT                                                         0x0
++#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT                                                         0x8
++#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT                                                         0x10
++#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT                                                         0x18
++#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK                                                           0x000000FFL
++#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK                                                           0x0000FF00L
++#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK                                                           0x00FF0000L
++#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK                                                           0xFF000000L
++//DIG3_AFMT_ISRC2_0
++#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT                                                         0x0
++#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT                                                         0x8
++#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT                                                         0x10
++#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT                                                         0x18
++#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK                                                           0x000000FFL
++#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK                                                           0x0000FF00L
++#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK                                                           0x00FF0000L
++#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK                                                           0xFF000000L
++//DIG3_AFMT_ISRC2_1
++#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT                                                         0x0
++#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT                                                         0x8
++#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT                                                         0x10
++#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT                                                         0x18
++#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK                                                           0x000000FFL
++#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK                                                           0x0000FF00L
++#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK                                                           0x00FF0000L
++#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK                                                           0xFF000000L
++//DIG3_AFMT_ISRC2_2
++#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT                                                         0x0
++#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT                                                         0x8
++#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT                                                         0x10
++#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT                                                         0x18
++#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK                                                           0x000000FFL
++#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK                                                           0x0000FF00L
++#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK                                                           0x00FF0000L
++#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK                                                           0xFF000000L
++//DIG3_AFMT_ISRC2_3
++#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT                                                         0x0
++#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT                                                         0x8
++#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT                                                         0x10
++#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT                                                         0x18
++#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK                                                           0x000000FFL
++#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK                                                           0x0000FF00L
++#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK                                                           0x00FF0000L
++#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK                                                           0xFF000000L
++//DIG3_HDMI_GENERIC_PACKET_CONTROL2
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
++//DIG3_HDMI_GENERIC_PACKET_CONTROL3
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
++//DIG3_HDMI_DB_CONTROL
++#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
++#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
++#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
++#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
++#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
++#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
++#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
++#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
++#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
++#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
++#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
++#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
++#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
++#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
++#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
++#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
++//DIG3_DME_CONTROL
++#define DIG3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
++#define DIG3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
++#define DIG3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
++#define DIG3_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
++#define DIG3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
++#define DIG3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
++#define DIG3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
++#define DIG3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
++#define DIG3_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
++#define DIG3_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
++#define DIG3_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
++#define DIG3_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
++#define DIG3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
++#define DIG3_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
++//DIG3_AFMT_MPEG_INFO0
++#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT                                                  0x0
++#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT                                                       0x8
++#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT                                                       0x10
++#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT                                                       0x18
++#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK                                                    0x000000FFL
++#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK                                                         0x0000FF00L
++#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK                                                         0x00FF0000L
++#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK                                                         0xFF000000L
++//DIG3_AFMT_MPEG_INFO1
++#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT                                                       0x0
++#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT                                                        0x8
++#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT                                                        0xc
++#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK                                                         0x000000FFL
++#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK                                                          0x00000300L
++#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK                                                          0x00001000L
++//DIG3_AFMT_GENERIC_HDR
++#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT                                                        0x0
++#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT                                                        0x8
++#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT                                                        0x10
++#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT                                                        0x18
++#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK                                                          0x000000FFL
++#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK                                                          0x0000FF00L
++#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK                                                          0x00FF0000L
++#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK                                                          0xFF000000L
++//DIG3_AFMT_GENERIC_0
++#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT                                                        0x0
++#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT                                                        0x8
++#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT                                                        0x10
++#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT                                                        0x18
++#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK                                                          0x000000FFL
++#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK                                                          0x0000FF00L
++#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK                                                          0x00FF0000L
++#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK                                                          0xFF000000L
++//DIG3_AFMT_GENERIC_1
++#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT                                                        0x0
++#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT                                                        0x8
++#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT                                                        0x10
++#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT                                                        0x18
++#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK                                                          0x000000FFL
++#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK                                                          0x0000FF00L
++#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK                                                          0x00FF0000L
++#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK                                                          0xFF000000L
++//DIG3_AFMT_GENERIC_2
++#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT                                                        0x0
++#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT                                                        0x8
++#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT                                                       0x10
++#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT                                                       0x18
++#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK                                                          0x000000FFL
++#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK                                                          0x0000FF00L
++#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK                                                         0x00FF0000L
++#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK                                                         0xFF000000L
++//DIG3_AFMT_GENERIC_3
++#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT                                                       0x0
++#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT                                                       0x8
++#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT                                                       0x10
++#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT                                                       0x18
++#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK                                                         0x000000FFL
++#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK                                                         0x0000FF00L
++#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK                                                         0x00FF0000L
++#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK                                                         0xFF000000L
++//DIG3_AFMT_GENERIC_4
++#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT                                                       0x0
++#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT                                                       0x8
++#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT                                                       0x10
++#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT                                                       0x18
++#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK                                                         0x000000FFL
++#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK                                                         0x0000FF00L
++#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK                                                         0x00FF0000L
++#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK                                                         0xFF000000L
++//DIG3_AFMT_GENERIC_5
++#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT                                                       0x0
++#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT                                                       0x8
++#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT                                                       0x10
++#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT                                                       0x18
++#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK                                                         0x000000FFL
++#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK                                                         0x0000FF00L
++#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK                                                         0x00FF0000L
++#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK                                                         0xFF000000L
++//DIG3_AFMT_GENERIC_6
++#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT                                                       0x0
++#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT                                                       0x8
++#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT                                                       0x10
++#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT                                                       0x18
++#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK                                                         0x000000FFL
++#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK                                                         0x0000FF00L
++#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK                                                         0x00FF0000L
++#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK                                                         0xFF000000L
++//DIG3_AFMT_GENERIC_7
++#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT                                                       0x0
++#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT                                                       0x8
++#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT                                                       0x10
++#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT                                                       0x18
++#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK                                                         0x000000FFL
++#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK                                                         0x0000FF00L
++#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK                                                         0x00FF0000L
++#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK                                                         0xFF000000L
++//DIG3_HDMI_GENERIC_PACKET_CONTROL1
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
++//DIG3_HDMI_ACR_32_0
++#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
++#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
++//DIG3_HDMI_ACR_32_1
++#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
++#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
++//DIG3_HDMI_ACR_44_0
++#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
++#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
++//DIG3_HDMI_ACR_44_1
++#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
++#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
++//DIG3_HDMI_ACR_48_0
++#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
++#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
++//DIG3_HDMI_ACR_48_1
++#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
++#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
++//DIG3_HDMI_ACR_STATUS_0
++#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
++#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
++//DIG3_HDMI_ACR_STATUS_1
++#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
++#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
++//DIG3_AFMT_AUDIO_INFO0
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                                0x0
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                      0x8
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                      0xb
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                         0x10
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                     0x18
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                  0x000000FFL
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                        0x00000700L
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                        0x00007800L
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                           0x00FF0000L
++#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                       0x1F000000L
++//DIG3_AFMT_AUDIO_INFO1
++#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                      0x0
++#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                     0xb
++#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                  0xf
++#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                  0x10
++#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                        0x000000FFL
++#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                       0x00007800L
++#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                    0x00008000L
++#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                    0x00030000L
++//DIG3_AFMT_60958_0
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                             0x0
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                             0x1
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                             0x2
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                             0x3
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                          0x6
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                 0x8
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                 0x10
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                              0x14
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                            0x18
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                                0x1c
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                               0x00000001L
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                               0x00000002L
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                               0x00000004L
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                               0x00000038L
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                            0x000000C0L
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                   0x0000FF00L
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                   0x000F0000L
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                                0x00F00000L
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                              0x0F000000L
++#define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                  0x30000000L
++//DIG3_AFMT_60958_1
++#define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                   0x0
++#define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                   0x4
++#define DIG3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                          0x10
++#define DIG3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                          0x12
++#define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                              0x14
++#define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                     0x0000000FL
++#define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                     0x000000F0L
++#define DIG3_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                            0x00010000L
++#define DIG3_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                            0x00040000L
++#define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                                0x00F00000L
++//DIG3_AFMT_AUDIO_CRC_CONTROL
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                 0x0
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                               0x4
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                             0x8
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                             0xc
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                              0x10
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                   0x00000001L
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                 0x00000010L
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                               0x00000100L
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                               0x0000F000L
++#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                                0xFFFF0000L
++//DIG3_AFMT_RAMP_CONTROL0
++#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                   0x0
++#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                   0x1f
++#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                     0x00FFFFFFL
++#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                     0x80000000L
++//DIG3_AFMT_RAMP_CONTROL1
++#define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                   0x0
++#define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                            0x18
++#define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                     0x00FFFFFFL
++#define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                              0xFF000000L
++//DIG3_AFMT_RAMP_CONTROL2
++#define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                   0x0
++#define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                     0x00FFFFFFL
++//DIG3_AFMT_RAMP_CONTROL3
++#define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                   0x0
++#define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                     0x00FFFFFFL
++//DIG3_AFMT_60958_2
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                              0x0
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                              0x4
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                              0x8
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                              0xc
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                              0x10
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                              0x14
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                                0x0000000FL
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                                0x000000F0L
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                                0x00000F00L
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                                0x0000F000L
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                                0x000F0000L
++#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                                0x00F00000L
++//DIG3_AFMT_AUDIO_CRC_RESULT
++#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                                0x0
++#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                     0x8
++#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                  0x00000001L
++#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                       0xFFFFFF00L
++//DIG3_AFMT_STATUS
++#define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                            0x4
++#define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                           0x8
++#define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                     0x18
++#define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                     0x1e
++#define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                              0x00000010L
++#define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                             0x00000100L
++#define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                       0x01000000L
++#define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                       0x40000000L
++//DIG3_AFMT_AUDIO_PACKET_CONTROL
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                         0x0
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                 0xb
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                             0xc
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                           0xe
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                   0x17
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                        0x18
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                           0x1a
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                   0x1e
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                                0x1f
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                           0x00000001L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                   0x00000800L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                               0x00001000L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                             0x00004000L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                     0x00800000L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                          0x01000000L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                             0x04000000L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                     0x40000000L
++#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                  0x80000000L
++//DIG3_AFMT_VBI_PACKET_CONTROL
++#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT                                         0x8
++#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT                                            0x10
++#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT                                        0x11
++#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT                                               0x1c
++#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK                                           0x00000100L
++#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK                                              0x00010000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK                                          0x00020000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK                                                 0xF0000000L
++//DIG3_AFMT_INFOFRAME_CONTROL0
++#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                           0x6
++#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                           0x7
++#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT                                            0xa
++#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                             0x00000040L
++#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                             0x00000080L
++#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK                                              0x00000400L
++//DIG3_AFMT_AUDIO_SRC_CONTROL
++#define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                             0x0
++#define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                               0x00000007L
++//DIG3_DIG_BE_CNTL
++#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
++#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
++#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
++#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
++#define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
++#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
++#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
++#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
++#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
++#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
++#define DIG3_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
++#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
++//DIG3_DIG_BE_EN_CNTL
++#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
++#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
++#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
++#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
++//DIG3_TMDS_CNTL
++#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
++#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
++//DIG3_TMDS_CONTROL_CHAR
++#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
++#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
++#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
++#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
++#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
++#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
++#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
++#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
++//DIG3_TMDS_CONTROL0_FEEDBACK
++#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
++#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
++#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
++#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
++//DIG3_TMDS_STEREOSYNC_CTL_SEL
++#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
++#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
++//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1
++#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
++#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
++#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
++#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
++//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3
++#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
++#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
++#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
++#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
++//DIG3_TMDS_CTL_BITS
++#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
++#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
++#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
++#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
++#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
++#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
++#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
++#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
++//DIG3_TMDS_DCBALANCER_CONTROL
++#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
++#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
++#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
++#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
++#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
++#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
++#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
++#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
++#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
++#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
++//DIG3_TMDS_SYNC_DCBALANCE_CHAR
++#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
++#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
++#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
++#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
++//DIG3_TMDS_CTL0_1_GEN_CNTL
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
++#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
++//DIG3_TMDS_CTL2_3_GEN_CNTL
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
++#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
++//DIG3_DIG_VERSION
++#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
++#define DIG3_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
++//DIG3_DIG_LANE_ENABLE
++#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT                                                              0x0
++#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT                                                              0x1
++#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT                                                              0x2
++#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT                                                              0x3
++#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT                                                               0x8
++#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN_MASK                                                                0x00000001L
++#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN_MASK                                                                0x00000002L
++#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN_MASK                                                                0x00000004L
++#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN_MASK                                                                0x00000008L
++#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN_MASK                                                                 0x00000100L
++//DIG3_AFMT_CNTL
++#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
++#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
++#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
++#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
++//DIG3_AFMT_VBI_PACKET_CONTROL1
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x1
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT                                  0x2
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x3
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT                                      0x4
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x5
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT                                  0x6
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x7
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT                                      0x8
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x9
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT                                  0xa
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xb
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT                                      0xc
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0xd
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT                                  0xe
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xf
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT                                      0x10
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x11
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT                                  0x12
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x13
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT                                      0x14
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT                                  0x16
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x17
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT                                      0x18
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x19
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT                                  0x1a
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1b
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT                                      0x1c
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x1d
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT                                  0x1e
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1f
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00000002L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK                                    0x00000004L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000008L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK                                        0x00000010L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00000020L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK                                    0x00000040L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000080L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK                                        0x00000100L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00000200L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK                                    0x00000400L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000800L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK                                        0x00001000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00002000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK                                    0x00004000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                            0x00008000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK                                        0x00010000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00020000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK                                    0x00040000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                            0x00080000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK                                        0x00100000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK                                    0x00400000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                            0x00800000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK                                        0x01000000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x02000000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK                                    0x04000000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                            0x08000000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK                                        0x10000000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x20000000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK                                    0x40000000L
++#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                            0x80000000L
++//DIG3_HDMI_GENERIC_PACKET_CONTROL5
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
++#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
++//DIG3_FORCE_DIG_DISABLE
++#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
++#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
++
++
++// addressBlock: dce_dc_dio_dp3_dispdec
++//DP3_DP_LINK_CNTL
++#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
++#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
++#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
++#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
++#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
++#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
++//DP3_DP_PIXEL_FORMAT
++#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
++#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
++#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
++#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
++#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
++#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
++//DP3_DP_MSA_COLORIMETRY
++#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
++#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
++//DP3_DP_CONFIG
++#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
++#define DP3_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
++//DP3_DP_VID_STREAM_CNTL
++#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
++#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
++#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
++#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
++#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
++#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
++#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
++#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
++//DP3_DP_STEER_FIFO
++#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
++#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
++#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
++#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
++#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
++#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
++#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
++#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
++#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
++#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
++#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
++#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
++#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
++#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
++//DP3_DP_MSA_MISC
++#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
++#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
++#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
++#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
++#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
++#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
++#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
++#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
++//DP3_DP_VID_TIMING
++#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
++#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
++#define DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
++#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
++#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
++#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
++#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
++#define DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
++#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
++#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
++//DP3_DP_VID_N
++#define DP3_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
++#define DP3_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
++//DP3_DP_VID_M
++#define DP3_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
++#define DP3_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
++//DP3_DP_LINK_FRAMING_CNTL
++#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
++#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
++#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
++#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
++#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
++#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
++//DP3_DP_HBR2_EYE_PATTERN
++#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
++#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
++//DP3_DP_VID_MSA_VBID
++#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
++#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
++#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
++#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
++//DP3_DP_VID_INTERRUPT_CNTL
++#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
++#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
++#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
++#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
++#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
++#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
++//DP3_DP_DPHY_CNTL
++#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
++#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
++#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
++#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
++#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
++#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
++#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
++#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
++#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
++#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
++#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
++#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
++#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
++#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
++#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
++#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
++#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
++#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
++//DP3_DP_DPHY_TRAINING_PATTERN_SEL
++#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
++#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
++//DP3_DP_DPHY_SYM0
++#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
++#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
++#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
++#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
++#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
++#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
++//DP3_DP_DPHY_SYM1
++#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
++#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
++#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
++#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
++#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
++#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
++//DP3_DP_DPHY_SYM2
++#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
++#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
++#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
++#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
++//DP3_DP_DPHY_8B10B_CNTL
++#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
++#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
++#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
++#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
++#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
++#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
++//DP3_DP_DPHY_PRBS_CNTL
++#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
++#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
++#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
++#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
++#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
++#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
++//DP3_DP_DPHY_SCRAM_CNTL
++#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
++#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
++#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
++#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
++#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
++#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
++#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
++#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
++//DP3_DP_DPHY_CRC_EN
++#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
++#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
++#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
++#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
++#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
++#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
++//DP3_DP_DPHY_CRC_CNTL
++#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
++#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
++#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
++#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
++#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
++#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
++//DP3_DP_DPHY_CRC_RESULT
++#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
++#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
++#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
++#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
++#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
++#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
++#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
++#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
++//DP3_DP_DPHY_CRC_MST_CNTL
++#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
++#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
++#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
++#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
++//DP3_DP_DPHY_CRC_MST_STATUS
++#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
++#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
++#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
++#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
++#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
++#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
++//DP3_DP_DPHY_FAST_TRAINING
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
++#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
++//DP3_DP_DPHY_FAST_TRAINING_STATUS
++#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
++#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
++#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
++#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
++#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
++#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
++#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
++#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
++//DP3_DP_SEC_CNTL
++#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
++#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
++#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
++#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
++#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
++#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
++#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
++#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
++#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
++#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
++#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
++#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
++#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
++//DP3_DP_SEC_CNTL1
++#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
++#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
++#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP3_DP_SEC_FRAMING1
++#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
++#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
++#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
++#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
++//DP3_DP_SEC_FRAMING2
++#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
++#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
++#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
++#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
++//DP3_DP_SEC_FRAMING3
++#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
++#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
++#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
++#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
++//DP3_DP_SEC_FRAMING4
++#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
++#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
++#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
++#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
++#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
++#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
++#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
++#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
++#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
++#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
++//DP3_DP_SEC_AUD_N
++#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
++#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
++//DP3_DP_SEC_AUD_N_READBACK
++#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
++#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
++//DP3_DP_SEC_AUD_M
++#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
++#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
++//DP3_DP_SEC_AUD_M_READBACK
++#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
++#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
++//DP3_DP_SEC_TIMESTAMP
++#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
++#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
++//DP3_DP_SEC_PACKET_CNTL
++#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
++#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
++#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
++#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
++#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
++#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
++#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
++#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
++//DP3_DP_MSE_RATE_CNTL
++#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
++#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
++#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
++#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
++//DP3_DP_MSE_RATE_UPDATE
++#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
++#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
++//DP3_DP_MSE_SAT0
++#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
++#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
++#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
++#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
++#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
++#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
++#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
++#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
++//DP3_DP_MSE_SAT1
++#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
++#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
++#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
++#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
++#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
++#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
++#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
++#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
++//DP3_DP_MSE_SAT2
++#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
++#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
++#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
++#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
++#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
++#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
++#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
++#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
++//DP3_DP_MSE_SAT_UPDATE
++#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
++#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
++#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
++#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
++//DP3_DP_MSE_LINK_TIMING
++#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
++#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
++#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
++#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
++//DP3_DP_MSE_MISC_CNTL
++#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
++#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
++#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
++#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
++#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
++#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
++//DP3_DP_DPHY_BS_SR_SWAP_CNTL
++#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
++#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
++#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
++#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
++#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
++#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
++//DP3_DP_DPHY_HBR2_PATTERN_CONTROL
++#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
++#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
++//DP3_DP_MSE_SAT0_STATUS
++#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
++#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
++#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
++#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
++#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
++#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
++#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
++#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
++//DP3_DP_MSE_SAT1_STATUS
++#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
++#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
++#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
++#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
++#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
++#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
++#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
++#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
++//DP3_DP_MSE_SAT2_STATUS
++#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
++#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
++#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
++#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
++#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
++#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
++#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
++#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
++//DP3_DP_MSA_TIMING_PARAM1
++#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
++#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
++#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
++#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
++//DP3_DP_MSA_TIMING_PARAM2
++#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
++#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
++#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
++#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
++//DP3_DP_MSA_TIMING_PARAM3
++#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
++#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
++#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
++#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
++#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
++#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
++#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
++#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
++//DP3_DP_MSA_TIMING_PARAM4
++#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
++#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
++#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
++#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
++//DP3_DP_MSO_CNTL
++#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
++#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
++#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
++#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
++#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
++#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
++#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
++#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
++#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
++#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
++#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
++#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
++#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
++#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
++#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
++#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
++//DP3_DP_MSO_CNTL1
++#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
++#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
++#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
++#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
++#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
++#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
++#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
++#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
++#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
++#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
++#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
++#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
++#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
++#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
++#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
++#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
++//DP3_DP_DSC_CNTL
++#define DP3_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
++#define DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
++#define DP3_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
++#define DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
++//DP3_DP_SEC_CNTL2
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT                                                              0x1c
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
++#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK                                                                0x10000000L
++//DP3_DP_SEC_CNTL3
++#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
++#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
++#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
++#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP3_DP_SEC_CNTL4
++#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
++#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
++#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
++#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP3_DP_SEC_CNTL5
++#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
++#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
++#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
++#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP3_DP_SEC_CNTL6
++#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
++#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
++//DP3_DP_SEC_CNTL7
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
++#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
++//DP3_DP_DB_CNTL
++#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
++#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
++#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
++#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
++#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
++#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
++#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
++#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
++#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
++#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
++#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
++#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
++#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
++#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
++#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
++#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
++//DP3_DP_MSA_VBID_MISC
++#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
++#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
++#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
++#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
++#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
++#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
++#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
++#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
++#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
++#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
++#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
++#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
++#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
++#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
++#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
++#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
++//DP3_DP_SEC_METADATA_TRANSMISSION
++#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
++#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
++#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
++#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
++#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
++#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
++#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
++#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
++//DP3_DP_DSC_BYTES_PER_PIXEL
++#define DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
++#define DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
++//DP3_DP_ALPM_CNTL
++#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
++#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
++#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
++#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
++#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
++#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
++#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
++#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
++#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
++#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
++#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
++#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
++#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
++#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
++
++
++// addressBlock: dce_dc_dio_dig4_dispdec
++//DIG4_DIG_FE_CNTL
++#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
++#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
++#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
++#define DIG4_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
++#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
++#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
++#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
++#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
++#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
++#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
++#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
++#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
++#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
++#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
++#define DIG4_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
++#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
++#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
++#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
++#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
++#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
++#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
++#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
++//DIG4_DIG_OUTPUT_CRC_CNTL
++#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
++#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
++#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
++#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
++#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
++#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
++//DIG4_DIG_OUTPUT_CRC_RESULT
++#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
++#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
++//DIG4_DIG_CLOCK_PATTERN
++#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
++#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
++//DIG4_DIG_TEST_PATTERN
++#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
++#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
++#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
++#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
++#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
++#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
++#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
++#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
++#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
++#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
++#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
++#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
++//DIG4_DIG_RANDOM_PATTERN_SEED
++#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
++#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
++#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
++#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
++//DIG4_DIG_FIFO_STATUS
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                   0x10
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                     0x001F0000L
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
++#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
++//DIG4_HDMI_METADATA_PACKET_CONTROL
++#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
++#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
++#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
++#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
++#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
++#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
++#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
++#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
++//DIG4_HDMI_GENERIC_PACKET_CONTROL4
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
++//DIG4_HDMI_CONTROL
++#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
++#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
++#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
++#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
++#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
++#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
++#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
++#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
++#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
++#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
++#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
++#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
++#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
++#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
++#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
++#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
++#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
++#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
++#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
++#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
++//DIG4_HDMI_STATUS
++#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
++#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
++#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
++#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
++#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
++#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
++#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
++#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
++//DIG4_HDMI_AUDIO_PACKET_CONTROL
++#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
++#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                    0x8
++#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                    0x10
++#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
++#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                      0x00000100L
++#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK                                      0x001F0000L
++//DIG4_HDMI_ACR_PACKET_CONTROL
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
++#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
++//DIG4_HDMI_VBI_PACKET_CONTROL
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
++#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
++//DIG4_HDMI_INFOFRAME_CONTROL0
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
++#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
++//DIG4_HDMI_INFOFRAME_CONTROL1
++#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
++#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
++#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
++#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
++//DIG4_HDMI_GENERIC_PACKET_CONTROL0
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
++//DIG4_HDMI_GC
++#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
++#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
++#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
++#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
++#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
++#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
++#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
++#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
++#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
++#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
++//DIG4_AFMT_AUDIO_PACKET_CONTROL2
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                        0x0
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                      0x1
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                     0x8
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                       0x10
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                          0x18
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                           0x1c
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                          0x00000001L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                        0x00000002L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                       0x0000FF00L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                         0x00FF0000L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                            0x01000000L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                             0x10000000L
++//DIG4_AFMT_ISRC1_0
++#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT                                                            0x0
++#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT                                                          0x6
++#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT                                                             0x7
++#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK                                                              0x00000007L
++#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK                                                            0x00000040L
++#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK                                                               0x00000080L
++//DIG4_AFMT_ISRC1_1
++#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT                                                          0x0
++#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT                                                          0x8
++#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT                                                          0x10
++#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT                                                          0x18
++#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK                                                            0x000000FFL
++#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK                                                            0x0000FF00L
++#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK                                                            0x00FF0000L
++#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK                                                            0xFF000000L
++//DIG4_AFMT_ISRC1_2
++#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT                                                          0x0
++#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT                                                          0x8
++#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT                                                          0x10
++#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT                                                          0x18
++#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK                                                            0x000000FFL
++#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK                                                            0x0000FF00L
++#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK                                                            0x00FF0000L
++#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK                                                            0xFF000000L
++//DIG4_AFMT_ISRC1_3
++#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT                                                          0x0
++#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT                                                          0x8
++#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT                                                         0x10
++#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT                                                         0x18
++#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK                                                            0x000000FFL
++#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK                                                            0x0000FF00L
++#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK                                                           0x00FF0000L
++#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK                                                           0xFF000000L
++//DIG4_AFMT_ISRC1_4
++#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT                                                         0x0
++#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT                                                         0x8
++#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT                                                         0x10
++#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT                                                         0x18
++#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK                                                           0x000000FFL
++#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK                                                           0x0000FF00L
++#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK                                                           0x00FF0000L
++#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK                                                           0xFF000000L
++//DIG4_AFMT_ISRC2_0
++#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT                                                         0x0
++#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT                                                         0x8
++#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT                                                         0x10
++#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT                                                         0x18
++#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK                                                           0x000000FFL
++#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK                                                           0x0000FF00L
++#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK                                                           0x00FF0000L
++#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK                                                           0xFF000000L
++//DIG4_AFMT_ISRC2_1
++#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT                                                         0x0
++#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT                                                         0x8
++#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT                                                         0x10
++#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT                                                         0x18
++#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK                                                           0x000000FFL
++#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK                                                           0x0000FF00L
++#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK                                                           0x00FF0000L
++#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK                                                           0xFF000000L
++//DIG4_AFMT_ISRC2_2
++#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT                                                         0x0
++#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT                                                         0x8
++#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT                                                         0x10
++#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT                                                         0x18
++#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK                                                           0x000000FFL
++#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK                                                           0x0000FF00L
++#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK                                                           0x00FF0000L
++#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK                                                           0xFF000000L
++//DIG4_AFMT_ISRC2_3
++#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT                                                         0x0
++#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT                                                         0x8
++#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT                                                         0x10
++#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT                                                         0x18
++#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK                                                           0x000000FFL
++#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK                                                           0x0000FF00L
++#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK                                                           0x00FF0000L
++#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK                                                           0xFF000000L
++//DIG4_HDMI_GENERIC_PACKET_CONTROL2
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
++//DIG4_HDMI_GENERIC_PACKET_CONTROL3
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
++//DIG4_HDMI_DB_CONTROL
++#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
++#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
++#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
++#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
++#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
++#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
++#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
++#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
++#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
++#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
++#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
++#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
++#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
++#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
++#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
++#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
++//DIG4_DME_CONTROL
++#define DIG4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
++#define DIG4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
++#define DIG4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
++#define DIG4_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
++#define DIG4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
++#define DIG4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
++#define DIG4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
++#define DIG4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
++#define DIG4_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
++#define DIG4_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
++#define DIG4_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
++#define DIG4_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
++#define DIG4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
++#define DIG4_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
++//DIG4_AFMT_MPEG_INFO0
++#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT                                                  0x0
++#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT                                                       0x8
++#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT                                                       0x10
++#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT                                                       0x18
++#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK                                                    0x000000FFL
++#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK                                                         0x0000FF00L
++#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK                                                         0x00FF0000L
++#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK                                                         0xFF000000L
++//DIG4_AFMT_MPEG_INFO1
++#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT                                                       0x0
++#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT                                                        0x8
++#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT                                                        0xc
++#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK                                                         0x000000FFL
++#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK                                                          0x00000300L
++#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK                                                          0x00001000L
++//DIG4_AFMT_GENERIC_HDR
++#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT                                                        0x0
++#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT                                                        0x8
++#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT                                                        0x10
++#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT                                                        0x18
++#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK                                                          0x000000FFL
++#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK                                                          0x0000FF00L
++#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK                                                          0x00FF0000L
++#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK                                                          0xFF000000L
++//DIG4_AFMT_GENERIC_0
++#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT                                                        0x0
++#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT                                                        0x8
++#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT                                                        0x10
++#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT                                                        0x18
++#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK                                                          0x000000FFL
++#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK                                                          0x0000FF00L
++#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK                                                          0x00FF0000L
++#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK                                                          0xFF000000L
++//DIG4_AFMT_GENERIC_1
++#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT                                                        0x0
++#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT                                                        0x8
++#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT                                                        0x10
++#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT                                                        0x18
++#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK                                                          0x000000FFL
++#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK                                                          0x0000FF00L
++#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK                                                          0x00FF0000L
++#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK                                                          0xFF000000L
++//DIG4_AFMT_GENERIC_2
++#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT                                                        0x0
++#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT                                                        0x8
++#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT                                                       0x10
++#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT                                                       0x18
++#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK                                                          0x000000FFL
++#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK                                                          0x0000FF00L
++#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK                                                         0x00FF0000L
++#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK                                                         0xFF000000L
++//DIG4_AFMT_GENERIC_3
++#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT                                                       0x0
++#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT                                                       0x8
++#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT                                                       0x10
++#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT                                                       0x18
++#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK                                                         0x000000FFL
++#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK                                                         0x0000FF00L
++#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK                                                         0x00FF0000L
++#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK                                                         0xFF000000L
++//DIG4_AFMT_GENERIC_4
++#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT                                                       0x0
++#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT                                                       0x8
++#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT                                                       0x10
++#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT                                                       0x18
++#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK                                                         0x000000FFL
++#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK                                                         0x0000FF00L
++#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK                                                         0x00FF0000L
++#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK                                                         0xFF000000L
++//DIG4_AFMT_GENERIC_5
++#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT                                                       0x0
++#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT                                                       0x8
++#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT                                                       0x10
++#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT                                                       0x18
++#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK                                                         0x000000FFL
++#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK                                                         0x0000FF00L
++#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK                                                         0x00FF0000L
++#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK                                                         0xFF000000L
++//DIG4_AFMT_GENERIC_6
++#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT                                                       0x0
++#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT                                                       0x8
++#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT                                                       0x10
++#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT                                                       0x18
++#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK                                                         0x000000FFL
++#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK                                                         0x0000FF00L
++#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK                                                         0x00FF0000L
++#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK                                                         0xFF000000L
++//DIG4_AFMT_GENERIC_7
++#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT                                                       0x0
++#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT                                                       0x8
++#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT                                                       0x10
++#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT                                                       0x18
++#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK                                                         0x000000FFL
++#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK                                                         0x0000FF00L
++#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK                                                         0x00FF0000L
++#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK                                                         0xFF000000L
++//DIG4_HDMI_GENERIC_PACKET_CONTROL1
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
++//DIG4_HDMI_ACR_32_0
++#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
++#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
++//DIG4_HDMI_ACR_32_1
++#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
++#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
++//DIG4_HDMI_ACR_44_0
++#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
++#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
++//DIG4_HDMI_ACR_44_1
++#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
++#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
++//DIG4_HDMI_ACR_48_0
++#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
++#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
++//DIG4_HDMI_ACR_48_1
++#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
++#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
++//DIG4_HDMI_ACR_STATUS_0
++#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
++#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
++//DIG4_HDMI_ACR_STATUS_1
++#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
++#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
++//DIG4_AFMT_AUDIO_INFO0
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                                0x0
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                      0x8
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                      0xb
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                         0x10
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                     0x18
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                  0x000000FFL
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                        0x00000700L
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                        0x00007800L
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                           0x00FF0000L
++#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                       0x1F000000L
++//DIG4_AFMT_AUDIO_INFO1
++#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                      0x0
++#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                     0xb
++#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                  0xf
++#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                  0x10
++#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                        0x000000FFL
++#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                       0x00007800L
++#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                    0x00008000L
++#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                    0x00030000L
++//DIG4_AFMT_60958_0
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                             0x0
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                             0x1
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                             0x2
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                             0x3
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                          0x6
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                 0x8
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                 0x10
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                              0x14
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                            0x18
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                                0x1c
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                               0x00000001L
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                               0x00000002L
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                               0x00000004L
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                               0x00000038L
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                            0x000000C0L
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                   0x0000FF00L
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                   0x000F0000L
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                                0x00F00000L
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                              0x0F000000L
++#define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                  0x30000000L
++//DIG4_AFMT_60958_1
++#define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                   0x0
++#define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                   0x4
++#define DIG4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                          0x10
++#define DIG4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                          0x12
++#define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                              0x14
++#define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                     0x0000000FL
++#define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                     0x000000F0L
++#define DIG4_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                            0x00010000L
++#define DIG4_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                            0x00040000L
++#define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                                0x00F00000L
++//DIG4_AFMT_AUDIO_CRC_CONTROL
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                 0x0
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                               0x4
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                             0x8
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                             0xc
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                              0x10
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                   0x00000001L
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                 0x00000010L
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                               0x00000100L
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                               0x0000F000L
++#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                                0xFFFF0000L
++//DIG4_AFMT_RAMP_CONTROL0
++#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                   0x0
++#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                   0x1f
++#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                     0x00FFFFFFL
++#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                     0x80000000L
++//DIG4_AFMT_RAMP_CONTROL1
++#define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                   0x0
++#define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                            0x18
++#define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                     0x00FFFFFFL
++#define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                              0xFF000000L
++//DIG4_AFMT_RAMP_CONTROL2
++#define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                   0x0
++#define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                     0x00FFFFFFL
++//DIG4_AFMT_RAMP_CONTROL3
++#define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                   0x0
++#define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                     0x00FFFFFFL
++//DIG4_AFMT_60958_2
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                              0x0
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                              0x4
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                              0x8
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                              0xc
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                              0x10
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                              0x14
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                                0x0000000FL
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                                0x000000F0L
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                                0x00000F00L
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                                0x0000F000L
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                                0x000F0000L
++#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                                0x00F00000L
++//DIG4_AFMT_AUDIO_CRC_RESULT
++#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                                0x0
++#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                     0x8
++#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                  0x00000001L
++#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                       0xFFFFFF00L
++//DIG4_AFMT_STATUS
++#define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                            0x4
++#define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                           0x8
++#define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                     0x18
++#define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                     0x1e
++#define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                              0x00000010L
++#define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                             0x00000100L
++#define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                       0x01000000L
++#define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                       0x40000000L
++//DIG4_AFMT_AUDIO_PACKET_CONTROL
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                         0x0
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                 0xb
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                             0xc
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                           0xe
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                   0x17
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                        0x18
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                           0x1a
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                   0x1e
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                                0x1f
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                           0x00000001L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                   0x00000800L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                               0x00001000L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                             0x00004000L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                     0x00800000L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                          0x01000000L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                             0x04000000L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                     0x40000000L
++#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                  0x80000000L
++//DIG4_AFMT_VBI_PACKET_CONTROL
++#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT                                         0x8
++#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT                                            0x10
++#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT                                        0x11
++#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT                                               0x1c
++#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK                                           0x00000100L
++#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK                                              0x00010000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK                                          0x00020000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK                                                 0xF0000000L
++//DIG4_AFMT_INFOFRAME_CONTROL0
++#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                           0x6
++#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                           0x7
++#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT                                            0xa
++#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                             0x00000040L
++#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                             0x00000080L
++#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK                                              0x00000400L
++//DIG4_AFMT_AUDIO_SRC_CONTROL
++#define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                             0x0
++#define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                               0x00000007L
++//DIG4_DIG_BE_CNTL
++#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
++#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
++#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
++#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
++#define DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
++#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
++#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
++#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
++#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
++#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
++#define DIG4_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
++#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
++//DIG4_DIG_BE_EN_CNTL
++#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
++#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
++#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
++#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
++//DIG4_TMDS_CNTL
++#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
++#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
++//DIG4_TMDS_CONTROL_CHAR
++#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
++#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
++#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
++#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
++#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
++#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
++#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
++#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
++//DIG4_TMDS_CONTROL0_FEEDBACK
++#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
++#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
++#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
++#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
++//DIG4_TMDS_STEREOSYNC_CTL_SEL
++#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
++#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
++//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1
++#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
++#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
++#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
++#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
++//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3
++#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
++#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
++#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
++#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
++//DIG4_TMDS_CTL_BITS
++#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
++#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
++#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
++#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
++#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
++#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
++#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
++#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
++//DIG4_TMDS_DCBALANCER_CONTROL
++#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
++#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
++#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
++#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
++#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
++#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
++#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
++#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
++#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
++#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
++//DIG4_TMDS_SYNC_DCBALANCE_CHAR
++#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
++#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
++#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
++#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
++//DIG4_TMDS_CTL0_1_GEN_CNTL
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
++#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
++//DIG4_TMDS_CTL2_3_GEN_CNTL
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
++#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
++//DIG4_DIG_VERSION
++#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
++#define DIG4_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
++//DIG4_DIG_LANE_ENABLE
++#define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT                                                              0x0
++#define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT                                                              0x1
++#define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT                                                              0x2
++#define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT                                                              0x3
++#define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT                                                               0x8
++#define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN_MASK                                                                0x00000001L
++#define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN_MASK                                                                0x00000002L
++#define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN_MASK                                                                0x00000004L
++#define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN_MASK                                                                0x00000008L
++#define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN_MASK                                                                 0x00000100L
++//DIG4_AFMT_CNTL
++#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
++#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
++#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
++#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
++//DIG4_AFMT_VBI_PACKET_CONTROL1
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x1
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT                                  0x2
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x3
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT                                      0x4
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x5
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT                                  0x6
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x7
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT                                      0x8
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x9
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT                                  0xa
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xb
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT                                      0xc
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0xd
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT                                  0xe
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xf
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT                                      0x10
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x11
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT                                  0x12
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x13
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT                                      0x14
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT                                  0x16
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x17
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT                                      0x18
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x19
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT                                  0x1a
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1b
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT                                      0x1c
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x1d
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT                                  0x1e
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1f
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00000002L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK                                    0x00000004L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000008L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK                                        0x00000010L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00000020L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK                                    0x00000040L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000080L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK                                        0x00000100L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00000200L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK                                    0x00000400L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000800L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK                                        0x00001000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00002000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK                                    0x00004000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                            0x00008000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK                                        0x00010000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00020000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK                                    0x00040000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                            0x00080000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK                                        0x00100000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK                                    0x00400000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                            0x00800000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK                                        0x01000000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x02000000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK                                    0x04000000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                            0x08000000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK                                        0x10000000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x20000000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK                                    0x40000000L
++#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                            0x80000000L
++//DIG4_HDMI_GENERIC_PACKET_CONTROL5
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
++#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
++//DIG4_FORCE_DIG_DISABLE
++#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
++#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
++
++
++// addressBlock: dce_dc_dio_dp4_dispdec
++//DP4_DP_LINK_CNTL
++#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
++#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
++#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
++#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
++#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
++#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
++//DP4_DP_PIXEL_FORMAT
++#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
++#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
++#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
++#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
++#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
++#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
++//DP4_DP_MSA_COLORIMETRY
++#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
++#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
++//DP4_DP_CONFIG
++#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
++#define DP4_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
++//DP4_DP_VID_STREAM_CNTL
++#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
++#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
++#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
++#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
++#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
++#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
++#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
++#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
++//DP4_DP_STEER_FIFO
++#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
++#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
++#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
++#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
++#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
++#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
++#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
++#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
++#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
++#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
++#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
++#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
++#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
++#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
++//DP4_DP_MSA_MISC
++#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
++#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
++#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
++#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
++#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
++#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
++#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
++#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
++//DP4_DP_VID_TIMING
++#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
++#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
++#define DP4_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
++#define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
++#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
++#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
++#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
++#define DP4_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
++#define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
++#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
++//DP4_DP_VID_N
++#define DP4_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
++#define DP4_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
++//DP4_DP_VID_M
++#define DP4_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
++#define DP4_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
++//DP4_DP_LINK_FRAMING_CNTL
++#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
++#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
++#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
++#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
++#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
++#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
++//DP4_DP_HBR2_EYE_PATTERN
++#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
++#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
++//DP4_DP_VID_MSA_VBID
++#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
++#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
++#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
++#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
++//DP4_DP_VID_INTERRUPT_CNTL
++#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
++#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
++#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
++#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
++#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
++#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
++//DP4_DP_DPHY_CNTL
++#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
++#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
++#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
++#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
++#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
++#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
++#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
++#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
++#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
++#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
++#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
++#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
++#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
++#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
++#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
++#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
++#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
++#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
++//DP4_DP_DPHY_TRAINING_PATTERN_SEL
++#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
++#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
++//DP4_DP_DPHY_SYM0
++#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
++#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
++#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
++#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
++#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
++#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
++//DP4_DP_DPHY_SYM1
++#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
++#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
++#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
++#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
++#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
++#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
++//DP4_DP_DPHY_SYM2
++#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
++#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
++#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
++#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
++//DP4_DP_DPHY_8B10B_CNTL
++#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
++#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
++#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
++#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
++#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
++#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
++//DP4_DP_DPHY_PRBS_CNTL
++#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
++#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
++#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
++#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
++#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
++#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
++//DP4_DP_DPHY_SCRAM_CNTL
++#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
++#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
++#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
++#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
++#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
++#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
++#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
++#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
++//DP4_DP_DPHY_CRC_EN
++#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
++#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
++#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
++#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
++#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
++#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
++//DP4_DP_DPHY_CRC_CNTL
++#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
++#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
++#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
++#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
++#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
++#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
++//DP4_DP_DPHY_CRC_RESULT
++#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
++#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
++#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
++#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
++#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
++#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
++#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
++#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
++//DP4_DP_DPHY_CRC_MST_CNTL
++#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
++#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
++#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
++#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
++//DP4_DP_DPHY_CRC_MST_STATUS
++#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
++#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
++#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
++#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
++#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
++#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
++//DP4_DP_DPHY_FAST_TRAINING
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
++#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
++//DP4_DP_DPHY_FAST_TRAINING_STATUS
++#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
++#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
++#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
++#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
++#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
++#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
++#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
++#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
++//DP4_DP_SEC_CNTL
++#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
++#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
++#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
++#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
++#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
++#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
++#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
++#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
++#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
++#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
++#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
++#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
++#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
++//DP4_DP_SEC_CNTL1
++#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
++#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
++#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP4_DP_SEC_FRAMING1
++#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
++#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
++#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
++#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
++//DP4_DP_SEC_FRAMING2
++#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
++#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
++#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
++#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
++//DP4_DP_SEC_FRAMING3
++#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
++#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
++#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
++#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
++//DP4_DP_SEC_FRAMING4
++#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
++#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
++#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
++#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
++#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
++#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
++#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
++#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
++#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
++#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
++//DP4_DP_SEC_AUD_N
++#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
++#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
++//DP4_DP_SEC_AUD_N_READBACK
++#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
++#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
++//DP4_DP_SEC_AUD_M
++#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
++#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
++//DP4_DP_SEC_AUD_M_READBACK
++#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
++#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
++//DP4_DP_SEC_TIMESTAMP
++#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
++#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
++//DP4_DP_SEC_PACKET_CNTL
++#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
++#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
++#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
++#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
++#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
++#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
++#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
++#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
++//DP4_DP_MSE_RATE_CNTL
++#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
++#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
++#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
++#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
++//DP4_DP_MSE_RATE_UPDATE
++#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
++#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
++//DP4_DP_MSE_SAT0
++#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
++#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
++#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
++#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
++#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
++#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
++#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
++#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
++//DP4_DP_MSE_SAT1
++#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
++#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
++#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
++#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
++#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
++#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
++#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
++#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
++//DP4_DP_MSE_SAT2
++#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
++#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
++#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
++#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
++#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
++#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
++#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
++#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
++//DP4_DP_MSE_SAT_UPDATE
++#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
++#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
++#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
++#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
++//DP4_DP_MSE_LINK_TIMING
++#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
++#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
++#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
++#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
++//DP4_DP_MSE_MISC_CNTL
++#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
++#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
++#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
++#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
++#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
++#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
++//DP4_DP_DPHY_BS_SR_SWAP_CNTL
++#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
++#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
++#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
++#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
++#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
++#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
++//DP4_DP_DPHY_HBR2_PATTERN_CONTROL
++#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
++#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
++//DP4_DP_MSE_SAT0_STATUS
++#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
++#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
++#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
++#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
++#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
++#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
++#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
++#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
++//DP4_DP_MSE_SAT1_STATUS
++#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
++#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
++#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
++#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
++#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
++#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
++#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
++#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
++//DP4_DP_MSE_SAT2_STATUS
++#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
++#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
++#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
++#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
++#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
++#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
++#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
++#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
++//DP4_DP_MSA_TIMING_PARAM1
++#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
++#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
++#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
++#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
++//DP4_DP_MSA_TIMING_PARAM2
++#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
++#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
++#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
++#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
++//DP4_DP_MSA_TIMING_PARAM3
++#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
++#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
++#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
++#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
++#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
++#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
++#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
++#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
++//DP4_DP_MSA_TIMING_PARAM4
++#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
++#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
++#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
++#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
++//DP4_DP_MSO_CNTL
++#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
++#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
++#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
++#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
++#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
++#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
++#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
++#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
++#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
++#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
++#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
++#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
++#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
++#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
++#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
++#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
++//DP4_DP_MSO_CNTL1
++#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
++#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
++#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
++#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
++#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
++#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
++#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
++#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
++#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
++#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
++#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
++#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
++#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
++#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
++#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
++#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
++//DP4_DP_DSC_CNTL
++#define DP4_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
++#define DP4_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
++#define DP4_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
++#define DP4_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
++//DP4_DP_SEC_CNTL2
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT                                                              0x1c
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
++#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK                                                                0x10000000L
++//DP4_DP_SEC_CNTL3
++#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
++#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
++#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
++#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP4_DP_SEC_CNTL4
++#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
++#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
++#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
++#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP4_DP_SEC_CNTL5
++#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
++#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
++#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
++#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
++//DP4_DP_SEC_CNTL6
++#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
++#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
++//DP4_DP_SEC_CNTL7
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
++#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
++//DP4_DP_DB_CNTL
++#define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
++#define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
++#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
++#define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
++#define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
++#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
++#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
++#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
++#define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
++#define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
++#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
++#define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
++#define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
++#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
++#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
++#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
++//DP4_DP_MSA_VBID_MISC
++#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
++#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
++#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
++#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
++#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
++#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
++#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
++#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
++#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
++#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
++#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
++#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
++#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
++#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
++#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
++#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
++//DP4_DP_SEC_METADATA_TRANSMISSION
++#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
++#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
++#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
++#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
++#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
++#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
++#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
++#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
++//DP4_DP_DSC_BYTES_PER_PIXEL
++#define DP4_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
++#define DP4_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
++//DP4_DP_ALPM_CNTL
++#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
++#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
++#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
++#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
++#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
++#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
++#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
++#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
++#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
++#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
++#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
++#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
++#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
++#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
++
++
++// addressBlock: dce_dc_dcio_dcio_dispdec
++//DC_GENERICA
++#define DC_GENERICA__GENERICA_EN__SHIFT                                                                       0x0
++#define DC_GENERICA__GENERICA_SEL__SHIFT                                                                      0x7
++#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
++#define DC_GENERICA__GENERICA_EN_MASK                                                                         0x00000001L
++#define DC_GENERICA__GENERICA_SEL_MASK                                                                        0x00000F80L
++#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
++//DC_GENERICB
++#define DC_GENERICB__GENERICB_EN__SHIFT                                                                       0x0
++#define DC_GENERICB__GENERICB_SEL__SHIFT                                                                      0x8
++#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
++#define DC_GENERICB__GENERICB_EN_MASK                                                                         0x00000001L
++#define DC_GENERICB__GENERICB_SEL_MASK                                                                        0x00000F00L
++#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
++//DC_REF_CLK_CNTL
++#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT                                                             0x0
++#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8
++#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK                                                               0x00000003L
++#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK                                                            0x00000300L
++//UNIPHYA_LINK_CNTL
++#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT                                                             0x0
++#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT                                                         0x4
++#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT                                          0x8
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
++#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT                                                   0x14
++#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT                                                 0x18
++#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK                                                               0x00000001L
++#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK                                                           0x00000010L
++#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK                                            0x00000700L
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
++#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK                                                     0x00700000L
++#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK                                                   0x03000000L
++//UNIPHYA_CHANNEL_XBAR_CNTL
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT                                                  0x1c
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK                                                    0x10000000L
++//UNIPHYB_LINK_CNTL
++#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT                                                             0x0
++#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT                                                         0x4
++#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT                                          0x8
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
++#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT                                                   0x14
++#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT                                                 0x18
++#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK                                                               0x00000001L
++#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK                                                           0x00000010L
++#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK                                            0x00000700L
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
++#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK                                                     0x00700000L
++#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK                                                   0x03000000L
++//UNIPHYB_CHANNEL_XBAR_CNTL
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT                                                  0x1c
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK                                                    0x10000000L
++//UNIPHYC_LINK_CNTL
++#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT                                                             0x0
++#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT                                                         0x4
++#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT                                          0x8
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
++#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT                                                   0x14
++#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT                                                 0x18
++#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK                                                               0x00000001L
++#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK                                                           0x00000010L
++#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK                                            0x00000700L
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
++#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK                                                     0x00700000L
++#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK                                                   0x03000000L
++//UNIPHYC_CHANNEL_XBAR_CNTL
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT                                                  0x1c
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK                                                    0x10000000L
++//UNIPHYD_LINK_CNTL
++#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT                                                             0x0
++#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT                                                         0x4
++#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT                                          0x8
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
++#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT                                                   0x14
++#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT                                                 0x18
++#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK                                                               0x00000001L
++#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK                                                           0x00000010L
++#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK                                            0x00000700L
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
++#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK                                                     0x00700000L
++#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK                                                   0x03000000L
++//UNIPHYD_CHANNEL_XBAR_CNTL
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT                                                  0x1c
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK                                                    0x10000000L
++//UNIPHYE_LINK_CNTL
++#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT                                                             0x0
++#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT                                                         0x4
++#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT                                          0x8
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
++#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT                                                   0x14
++#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT                                                 0x18
++#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK                                                               0x00000001L
++#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK                                                           0x00000010L
++#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK                                            0x00000700L
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
++#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK                                                     0x00700000L
++#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK                                                   0x03000000L
++//UNIPHYE_CHANNEL_XBAR_CNTL
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT                                                  0x1c
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK                                                    0x10000000L
++//DCIO_WRCMD_DELAY
++#define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT                                                                    0x4
++#define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT                                                                   0x8
++#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT                                                                0xc
++#define DCIO_WRCMD_DELAY__ZCAL_DELAY__SHIFT                                                                   0x10
++#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT                                                                 0x18
++#define DCIO_WRCMD_DELAY__DAC_DELAY_MASK                                                                      0x000000F0L
++#define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK                                                                     0x00000F00L
++#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK                                                                  0x0000F000L
++#define DCIO_WRCMD_DELAY__ZCAL_DELAY_MASK                                                                     0x000F0000L
++#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK                                                                   0xFF000000L
++//DC_PINSTRAPS
++#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT                                                         0xd
++#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT                                                               0xe
++#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT                                                            0x10
++#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT                                                        0x11
++#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK                                                           0x00002000L
++#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK                                                                 0x0000C000L
++#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK                                                              0x00010000L
++#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK                                                          0x000E0000L
++//LVTMA_PWRSEQ_CNTL
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT                                                             0x0
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT                                0x1
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT                                                   0x4
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT                                                                0x8
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT                                                           0x9
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT                                                            0xa
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT                                                                 0x10
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT                                                            0x11
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT                                                             0x12
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT                                                                  0x18
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT                                                             0x19
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT                                                              0x1a
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK                                                               0x00000001L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK                                  0x00000002L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK                                                     0x00000010L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK                                                                  0x00000100L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK                                                             0x00000200L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK                                                              0x00000400L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK                                                                   0x00010000L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK                                                              0x00020000L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK                                                               0x00040000L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK                                                                    0x01000000L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK                                                               0x02000000L
++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK                                                                0x04000000L
++//LVTMA_PWRSEQ_STATE
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT                                                0x0
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT                                                         0x1
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT                                                        0x2
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT                                                          0x3
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT                                                          0x4
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT                                                         0x8
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK                                                  0x00000001L
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK                                                           0x00000002L
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK                                                          0x00000004L
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK                                                            0x00000008L
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK                                                            0x00000010L
++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK                                                           0x00000F00L
++//LVTMA_PWRSEQ_REF_DIV
++#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT                                                     0x0
++#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT                                                           0x10
++#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK                                                       0x00000FFFL
++#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK                                                             0xFFFF0000L
++//LVTMA_PWRSEQ_DELAY1
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT                                                        0x0
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT                                                        0x8
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT                                                        0x10
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT                                                        0x18
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK                                                          0x000000FFL
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK                                                          0x0000FF00L
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK                                                          0x00FF0000L
++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK                                                          0xFF000000L
++//LVTMA_PWRSEQ_DELAY2
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT                                                    0x0
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT                                                        0x8
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT                                                        0x10
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT                                                 0x18
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK                                                      0x000000FFL
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK                                                          0x0000FF00L
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK                                                          0x00FF0000L
++#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK                                                   0x01000000L
++//BL_PWM_CNTL
++#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                            0x0
++#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                              0x1e
++#define BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                         0x1f
++#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                              0x0000FFFFL
++#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                                0x40000000L
++#define BL_PWM_CNTL__BL_PWM_EN_MASK                                                                           0x80000000L
++//BL_PWM_CNTL2
++#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                                      0x0
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                                    0x1e
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT                                                  0x1f
++#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                        0x0000FFFFL
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                                      0x40000000L
++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK                                                    0x80000000L
++//BL_PWM_PERIOD_CNTL
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                              0x0
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                                       0x10
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                                0x0000FFFFL
++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                         0x000F0000L
++//BL_PWM_GRP1_REG_LOCK
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                                     0x0
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                           0x8
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                        0x10
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT                                         0x11
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                                     0x18
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                        0x1f
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                                       0x00000001L
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                             0x00000100L
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                          0x00010000L
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK                                           0x000E0000L
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                                       0x01000000L
++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                          0x80000000L
++//DCIO_GSL_GENLK_PAD_CNTL
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT                                     0x4
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT                                               0x8
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT                                   0x14
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT                                             0x18
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK                                       0x00000030L
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK                                                 0x00000300L
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK                                     0x00300000L
++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK                                               0x03000000L
++//DCIO_GSL_SWAPLOCK_PAD_CNTL
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT                                 0x4
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT                                           0x8
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT                                 0x14
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT                                           0x18
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK                                   0x00000030L
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK                                             0x00000300L
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK                                   0x00300000L
++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK                                             0x03000000L
++//DCIO_CLOCK_CNTL
++#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT                                                             0x0
++#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT                                                       0x5
++#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK                                                               0x0000001FL
++#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK                                                         0x00000020L
++//DCIO_SOFT_RESET
++#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT                                                            0x0
++#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT                                                             0x1
++#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT                                                            0x2
++#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT                                                             0x3
++#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT                                                            0x4
++#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT                                                             0x5
++#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT                                                            0x6
++#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT                                                             0x7
++#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT                                                            0x8
++#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT                                                             0x9
++#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT                                                            0xa
++#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT                                                             0xb
++#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT                                                            0xc
++#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT                                                             0xd
++#define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT                                                               0x10
++#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT                                                            0x14
++#define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT                                                               0x18
++#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET__SHIFT                                                               0x1a
++#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK                                                              0x00000001L
++#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK                                                               0x00000002L
++#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK                                                              0x00000004L
++#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK                                                               0x00000008L
++#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK                                                              0x00000010L
++#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK                                                               0x00000020L
++#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK                                                              0x00000040L
++#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK                                                               0x00000080L
++#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK                                                              0x00000100L
++#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK                                                               0x00000200L
++#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK                                                              0x00000400L
++#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK                                                               0x00000800L
++#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK                                                              0x00001000L
++#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK                                                               0x00002000L
++#define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK                                                                 0x00010000L
++#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK                                                              0x00100000L
++#define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK                                                                 0x01000000L
++#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET_MASK                                                                 0x04000000L
++
++
++// addressBlock: dce_dc_dcio_dcio_chip_dispdec
++//DC_GPIO_GENERIC_MASK
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT                                                    0x0
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT                                                  0x1
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT                                                    0x2
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT                                                    0x4
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT                                                  0x5
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT                                                    0x6
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT                                                    0x8
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT                                                  0x9
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT                                                    0xa
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT                                                    0xc
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT                                                  0xd
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT                                                    0xe
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT                                                    0x10
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT                                                  0x11
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT                                                    0x12
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT                                                    0x14
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT                                                  0x15
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT                                                    0x16
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT                                                    0x18
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT                                                  0x19
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT                                                    0x1a
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK                                                      0x00000001L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK                                                    0x00000002L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK                                                      0x0000000CL
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK                                                      0x00000010L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK                                                    0x00000020L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK                                                      0x000000C0L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK                                                      0x00000100L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK                                                    0x00000200L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK                                                      0x00000C00L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK                                                      0x00001000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK                                                    0x00002000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK                                                      0x0000C000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK                                                      0x00010000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK                                                    0x00020000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK                                                      0x000C0000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK                                                      0x00100000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK                                                    0x00200000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK                                                      0x00C00000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK                                                      0x01000000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK                                                    0x02000000L
++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK                                                      0x0C000000L
++//DC_GPIO_GENERIC_A
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT                                                          0x0
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT                                                          0x8
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT                                                          0x10
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT                                                          0x14
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT                                                          0x15
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT                                                          0x16
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT                                                          0x17
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK                                                            0x00000001L
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK                                                            0x00000100L
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK                                                            0x00010000L
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK                                                            0x00100000L
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK                                                            0x00200000L
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK                                                            0x00400000L
++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK                                                            0x00800000L
++//DC_GPIO_GENERIC_EN
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT                                                        0x0
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT                                                        0x8
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT                                                        0x10
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT                                                        0x14
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT                                                        0x15
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT                                                        0x16
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT                                                        0x17
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK                                                          0x00000001L
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK                                                          0x00000100L
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK                                                          0x00010000L
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK                                                          0x00100000L
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK                                                          0x00200000L
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK                                                          0x00400000L
++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK                                                          0x00800000L
++//DC_GPIO_GENERIC_Y
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT                                                          0x0
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT                                                          0x8
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT                                                          0x10
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT                                                          0x14
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT                                                          0x15
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT                                                          0x16
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT                                                          0x17
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK                                                            0x00000001L
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK                                                            0x00000100L
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK                                                            0x00010000L
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK                                                            0x00100000L
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK                                                            0x00200000L
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK                                                            0x00400000L
++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK                                                            0x00800000L
++//DC_GPIO_DDC1_MASK
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT                                                        0x0
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT                                                       0x4
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT                                                        0x6
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT                                                       0x8
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT                                                      0xc
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT                                                       0xe
++#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT                                                               0x10
++#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT                                                                    0x14
++#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT                                                         0x16
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT                                                         0x18
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT                                                        0x1c
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK                                                          0x00000001L
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK                                                         0x00000010L
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK                                                          0x00000040L
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK                                                         0x00000100L
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK                                                        0x00001000L
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK                                                         0x00004000L
++#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK                                                                 0x00010000L
++#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK                                                                      0x00100000L
++#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK                                                           0x00400000L
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK                                                           0x0F000000L
++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK                                                          0xF0000000L
++//DC_GPIO_DDC1_A
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT                                                              0x0
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT                                                             0x8
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK                                                                0x00000001L
++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK                                                               0x00000100L
++//DC_GPIO_DDC1_EN
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT                                                            0x0
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT                                                           0x8
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK                                                              0x00000001L
++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK                                                             0x00000100L
++//DC_GPIO_DDC1_Y
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT                                                              0x0
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT                                                             0x8
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK                                                                0x00000001L
++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK                                                               0x00000100L
++//DC_GPIO_DDC2_MASK
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT                                                        0x0
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT                                                       0x4
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT                                                        0x6
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT                                                       0x8
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT                                                      0xc
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT                                                       0xe
++#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT                                                               0x10
++#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT                                                                    0x14
++#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT                                                         0x16
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT                                                         0x18
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT                                                        0x1c
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK                                                          0x00000001L
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK                                                         0x00000010L
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK                                                          0x00000040L
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK                                                         0x00000100L
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK                                                        0x00001000L
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK                                                         0x00004000L
++#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK                                                                 0x00010000L
++#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK                                                                      0x00100000L
++#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK                                                           0x00400000L
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK                                                           0x0F000000L
++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK                                                          0xF0000000L
++//DC_GPIO_DDC2_A
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT                                                              0x0
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT                                                             0x8
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK                                                                0x00000001L
++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK                                                               0x00000100L
++//DC_GPIO_DDC2_EN
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT                                                            0x0
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT                                                           0x8
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK                                                              0x00000001L
++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK                                                             0x00000100L
++//DC_GPIO_DDC2_Y
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT                                                              0x0
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT                                                             0x8
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK                                                                0x00000001L
++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK                                                               0x00000100L
++//DC_GPIO_DDC3_MASK
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT                                                        0x0
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT                                                       0x4
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT                                                        0x6
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT                                                       0x8
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT                                                      0xc
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT                                                       0xe
++#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT                                                               0x10
++#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT                                                                    0x14
++#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT                                                         0x16
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT                                                         0x18
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT                                                        0x1c
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK                                                          0x00000001L
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK                                                         0x00000010L
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK                                                          0x00000040L
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK                                                         0x00000100L
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK                                                        0x00001000L
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK                                                         0x00004000L
++#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK                                                                 0x00010000L
++#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK                                                                      0x00100000L
++#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK                                                           0x00400000L
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK                                                           0x0F000000L
++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK                                                          0xF0000000L
++//DC_GPIO_DDC3_A
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT                                                              0x0
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT                                                             0x8
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK                                                                0x00000001L
++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK                                                               0x00000100L
++//DC_GPIO_DDC3_EN
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT                                                            0x0
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT                                                           0x8
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK                                                              0x00000001L
++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK                                                             0x00000100L
++//DC_GPIO_DDC3_Y
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT                                                              0x0
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT                                                             0x8
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK                                                                0x00000001L
++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK                                                               0x00000100L
++//DC_GPIO_DDC4_MASK
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT                                                        0x0
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT                                                       0x4
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT                                                        0x6
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT                                                       0x8
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT                                                      0xc
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT                                                       0xe
++#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT                                                               0x10
++#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT                                                                    0x14
++#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT                                                         0x16
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT                                                         0x18
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT                                                        0x1c
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK                                                          0x00000001L
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK                                                         0x00000010L
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK                                                          0x00000040L
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK                                                         0x00000100L
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK                                                        0x00001000L
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK                                                         0x00004000L
++#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK                                                                 0x00010000L
++#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK                                                                      0x00100000L
++#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK                                                           0x00400000L
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK                                                           0x0F000000L
++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK                                                          0xF0000000L
++//DC_GPIO_DDC4_A
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT                                                              0x0
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT                                                             0x8
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK                                                                0x00000001L
++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK                                                               0x00000100L
++//DC_GPIO_DDC4_EN
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT                                                            0x0
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT                                                           0x8
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK                                                              0x00000001L
++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK                                                             0x00000100L
++//DC_GPIO_DDC4_Y
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT                                                              0x0
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT                                                             0x8
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK                                                                0x00000001L
++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK                                                               0x00000100L
++//DC_GPIO_DDC5_MASK
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT                                                        0x0
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT                                                       0x4
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT                                                        0x6
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT                                                       0x8
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT                                                      0xc
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT                                                       0xe
++#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT                                                               0x10
++#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT                                                                    0x14
++#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT                                                         0x16
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT                                                         0x18
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT                                                        0x1c
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK                                                          0x00000001L
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK                                                         0x00000010L
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK                                                          0x00000040L
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK                                                         0x00000100L
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK                                                        0x00001000L
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK                                                         0x00004000L
++#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK                                                                 0x00010000L
++#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK                                                                      0x00100000L
++#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK                                                           0x00400000L
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK                                                           0x0F000000L
++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK                                                          0xF0000000L
++//DC_GPIO_DDC5_A
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT                                                              0x0
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT                                                             0x8
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK                                                                0x00000001L
++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK                                                               0x00000100L
++//DC_GPIO_DDC5_EN
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT                                                            0x0
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT                                                           0x8
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK                                                              0x00000001L
++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK                                                             0x00000100L
++//DC_GPIO_DDC5_Y
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT                                                              0x0
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT                                                             0x8
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK                                                                0x00000001L
++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK                                                               0x00000100L
++//DC_GPIO_DDCVGA_MASK
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT                                                    0x0
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT                                                    0x6
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT                                                   0x8
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT                                                  0xc
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT                                                   0xe
++#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT                                                           0x10
++#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT                                                                0x14
++#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT                                                     0x16
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT                                                     0x18
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT                                                    0x1c
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK                                                      0x00000001L
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK                                                      0x00000040L
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK                                                     0x00000100L
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK                                                    0x00001000L
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK                                                     0x00004000L
++#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK                                                             0x00010000L
++#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK                                                                  0x00100000L
++#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK                                                       0x00400000L
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK                                                       0x0F000000L
++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK                                                      0xF0000000L
++//DC_GPIO_DDCVGA_A
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT                                                          0x0
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT                                                         0x8
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK                                                            0x00000001L
++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK                                                           0x00000100L
++//DC_GPIO_DDCVGA_EN
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT                                                        0x0
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT                                                       0x8
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK                                                          0x00000001L
++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK                                                         0x00000100L
++//DC_GPIO_DDCVGA_Y
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT                                                          0x0
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT                                                         0x8
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK                                                            0x00000001L
++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK                                                           0x00000100L
++//DC_GPIO_GENLK_MASK
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT                                                     0x0
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT                                                   0x1
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT                                                    0x3
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT                                                     0x4
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT                                                   0x8
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT                                                 0x9
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT                                                  0xb
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT                                                   0xc
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT                                                    0x10
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT                                                  0x11
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT                                                   0x13
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT                                                    0x14
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT                                                    0x18
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT                                                  0x19
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT                                                   0x1b
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT                                                    0x1c
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK                                                       0x00000001L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK                                                     0x00000002L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK                                                      0x00000008L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK                                                       0x00000030L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK                                                     0x00000100L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK                                                   0x00000200L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK                                                    0x00000800L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK                                                     0x00003000L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK                                                      0x00010000L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK                                                    0x00020000L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK                                                     0x00080000L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK                                                      0x00300000L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK                                                      0x01000000L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK                                                    0x02000000L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK                                                     0x08000000L
++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK                                                      0x30000000L
++//DC_GPIO_GENLK_A
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT                                                           0x0
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT                                                         0x8
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT                                                          0x10
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT                                                          0x18
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK                                                             0x00000001L
++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK                                                           0x00000100L
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK                                                            0x00010000L
++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK                                                            0x01000000L
++//DC_GPIO_GENLK_EN
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT                                                         0x0
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT                                                       0x8
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT                                                        0x10
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT                                                        0x18
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK                                                           0x00000001L
++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK                                                         0x00000100L
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK                                                          0x00010000L
++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK                                                          0x01000000L
++//DC_GPIO_GENLK_Y
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT                                                           0x0
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT                                                         0x8
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT                                                          0x10
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT                                                          0x18
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK                                                             0x00000001L
++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK                                                           0x00000100L
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK                                                            0x00010000L
++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK                                                            0x01000000L
++//DC_GPIO_HPD_MASK
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT                                                            0x0
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT                                                          0x1
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT                                                        0x2
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT                                                        0x3
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT                                                          0x4
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT                                                            0x6
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT                                                            0x8
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT                                                          0x9
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT                                                            0xa
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT                                                            0x10
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT                                                          0x11
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT                                                            0x12
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT                                                            0x14
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT                                                          0x15
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT                                                            0x16
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT                                                            0x18
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT                                                          0x19
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT                                                            0x1a
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT                                                            0x1c
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT                                                          0x1d
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT                                                            0x1e
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK                                                              0x00000001L
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK                                                            0x00000002L
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK                                                          0x00000004L
++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK                                                          0x00000008L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK                                                            0x00000010L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK                                                              0x000000C0L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK                                                              0x00000100L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK                                                            0x00000200L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK                                                              0x00000C00L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK                                                              0x00010000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK                                                            0x00020000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK                                                              0x000C0000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK                                                              0x00100000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK                                                            0x00200000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK                                                              0x00C00000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK                                                              0x01000000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK                                                            0x02000000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK                                                              0x0C000000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK                                                              0x10000000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK                                                            0x20000000L
++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK                                                              0xC0000000L
++//DC_GPIO_HPD_A
++#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT                                                                  0x0
++#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT                                                                  0x8
++#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT                                                                  0x10
++#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT                                                                  0x18
++#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT                                                                  0x1a
++#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT                                                                  0x1c
++#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK                                                                    0x00000001L
++#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK                                                                    0x00000100L
++#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK                                                                    0x00010000L
++#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK                                                                    0x01000000L
++#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK                                                                    0x04000000L
++#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK                                                                    0x10000000L
++//DC_GPIO_HPD_EN
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT                                                                0x0
++#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT                                                                 0x1
++#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT                                                                 0x2
++#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT                                                               0x3
++#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT                                                               0x4
++#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT                                                                   0x5
++#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT                                                                      0x6
++#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT                                                                    0x7
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT                                                                0x8
++#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT                                                                 0x9
++#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT                                                                   0xa
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT                                                                0x10
++#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT                                                                 0x11
++#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT                                                                   0x12
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT                                                                0x14
++#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT                                                                 0x15
++#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT                                                                   0x16
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT                                                                0x18
++#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT                                                                 0x19
++#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT                                                                   0x1a
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT                                                                0x1c
++#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT                                                                 0x1d
++#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT                                                                   0x1e
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK                                                                  0x00000001L
++#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK                                                                   0x00000002L
++#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK                                                                   0x00000004L
++#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK                                                                 0x00000008L
++#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK                                                                 0x00000010L
++#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK                                                                     0x00000020L
++#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK                                                                        0x00000040L
++#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK                                                                      0x00000080L
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK                                                                  0x00000100L
++#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK                                                                   0x00000200L
++#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK                                                                     0x00000400L
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK                                                                  0x00010000L
++#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK                                                                   0x00020000L
++#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK                                                                     0x00040000L
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK                                                                  0x00100000L
++#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK                                                                   0x00200000L
++#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK                                                                     0x00400000L
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK                                                                  0x01000000L
++#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK                                                                   0x02000000L
++#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK                                                                     0x04000000L
++#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK                                                                  0x10000000L
++#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK                                                                   0x20000000L
++#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK                                                                     0x40000000L
++//DC_GPIO_HPD_Y
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT                                                                  0x0
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT                                                                  0x8
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT                                                                  0x10
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT                                                                  0x18
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT                                                                  0x1a
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT                                                                  0x1c
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK                                                                    0x00000001L
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK                                                                    0x00000100L
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK                                                                    0x00010000L
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK                                                                    0x01000000L
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK                                                                    0x04000000L
++#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK                                                                    0x10000000L
++//DC_GPIO_PWRSEQ_MASK
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                         0x0
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                                       0x4
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                         0x6
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                        0x8
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                                      0xc
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                        0xe
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT                                                       0x10
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT                                                     0x14
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT                                                       0x16
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT                                                     0x18
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT                                                   0x19
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT                                                     0x1a
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT                                                     0x1c
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT                                                   0x1d
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT                                                     0x1e
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                           0x00000001L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                         0x00000010L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                           0x000000C0L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                          0x00000100L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                        0x00001000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                          0x0000C000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK                                                         0x00010000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK                                                       0x00100000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK                                                         0x00C00000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK                                                       0x01000000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK                                                     0x02000000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK                                                       0x04000000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK                                                       0x10000000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK                                                     0x20000000L
++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK                                                       0x40000000L
++//DC_GPIO_PWRSEQ_A
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT                                                               0x0
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT                                                              0x8
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT                                                             0x10
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT                                                           0x18
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT                                                           0x1f
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK                                                                 0x00000001L
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK                                                                0x00000100L
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK                                                               0x00010000L
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK                                                             0x01000000L
++#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK                                                             0x80000000L
++//DC_GPIO_PWRSEQ_EN
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                             0x0
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                 0x1
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                            0x8
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT                                                           0x10
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT                                                         0x18
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT                                                         0x1f
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                               0x00000001L
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                   0x00000002L
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                              0x00000100L
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK                                                             0x00010000L
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK                                                           0x01000000L
++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK                                                           0x80000000L
++//DC_GPIO_PWRSEQ_Y
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT                                                               0x0
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT                                                              0x8
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT                                                             0x10
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT                                                             0x18
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT                                                             0x1f
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK                                                                 0x00000001L
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK                                                                0x00000100L
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK                                                               0x00010000L
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK                                                               0x01000000L
++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK                                                               0x80000000L
++//DC_GPIO_PAD_STRENGTH_1
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT                                                      0x0
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT                                                      0x4
++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT                                                     0x8
++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT                                                     0xc
++#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT                                                     0x10
++#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT                                                     0x14
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT                                                       0x18
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT                                                       0x1c
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK                                                        0x0000000FL
++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK                                                        0x000000F0L
++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK                                                       0x00000F00L
++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK                                                       0x0000F000L
++#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK                                                       0x000F0000L
++#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK                                                       0x00F00000L
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK                                                         0x0F000000L
++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK                                                         0xF0000000L
++//DC_GPIO_PAD_STRENGTH_2
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT                                                            0x0
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT                                                            0x4
++#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT                                                  0x8
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT                                                     0xc
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT                                                     0x10
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT                                                     0x14
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT                                                         0x1e
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK                                                              0x0000000FL
++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK                                                              0x000000F0L
++#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK                                                    0x00000700L
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK                                                       0x00007000L
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK                                                       0x000F0000L
++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK                                                       0x00F00000L
++#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK                                                           0xC0000000L
++//PHY_AUX_CNTL
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT                                                               0x0
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT                                                                0x1
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT                                                               0x2
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT                                                                0x3
++#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT                                                              0x4
++#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT                                                                 0x5
++#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT                                                               0x6
++#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT                                                                  0x7
++#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT                                                               0x8
++#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT                                                                     0x9
++#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT                                                                   0xa
++#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT                                                                   0xc
++#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT                                                                   0xe
++#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT                                                                   0x10
++#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT                                                                   0x12
++#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT                                                                   0x14
++#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN__SHIFT                                                                0x17
++#define PHY_AUX_CNTL__AUX_CAL_SPARE__SHIFT                                                                    0x18
++#define PHY_AUX_CNTL__AUX_CAL_BIASENTST__SHIFT                                                                0x1c
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK                                                                 0x00000001L
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK                                                                  0x00000002L
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK                                                                 0x00000004L
++#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK                                                                  0x00000008L
++#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK                                                                0x00000010L
++#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK                                                                   0x00000020L
++#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK                                                                 0x00000040L
++#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK                                                                    0x00000080L
++#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK                                                                 0x00000100L
++#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK                                                                       0x00000200L
++#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK                                                                     0x00000C00L
++#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK                                                                     0x00003000L
++#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK                                                                     0x0000C000L
++#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK                                                                     0x00030000L
++#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK                                                                     0x000C0000L
++#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK                                                                     0x00300000L
++#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN_MASK                                                                  0x00800000L
++#define PHY_AUX_CNTL__AUX_CAL_SPARE_MASK                                                                      0x03000000L
++#define PHY_AUX_CNTL__AUX_CAL_BIASENTST_MASK                                                                  0x70000000L
++//DC_GPIO_TX12_EN
++#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN__SHIFT                                                          0x0
++#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN__SHIFT                                                         0x1
++#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN__SHIFT                                                        0x2
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT                                                      0x3
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT                                                      0x4
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT                                                      0x5
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT                                                      0x6
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT                                                      0x7
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT                                                      0x8
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT                                                      0x9
++#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN_MASK                                                            0x00000001L
++#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN_MASK                                                           0x00000002L
++#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN_MASK                                                          0x00000004L
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK                                                        0x00000008L
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK                                                        0x00000010L
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK                                                        0x00000020L
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK                                                        0x00000040L
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK                                                        0x00000080L
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK                                                        0x00000100L
++#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK                                                        0x00000200L
++//DC_GPIO_AUX_CTRL_0
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT                                                   0x0
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT                                                   0x2
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT                                                   0x4
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT                                                   0x6
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT                                                   0x8
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT                                                   0xa
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT                                                 0xc
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT                                                     0x10
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT                                                     0x11
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT                                                     0x12
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT                                                     0x13
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT                                                     0x14
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT                                                     0x15
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT                                                   0x16
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT                                                    0x18
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT                                                    0x19
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT                                                    0x1a
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT                                                    0x1b
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT                                                    0x1c
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT                                                    0x1d
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT                                                  0x1e
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK                                                     0x00000003L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK                                                     0x0000000CL
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK                                                     0x00000030L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK                                                     0x000000C0L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK                                                     0x00000300L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK                                                     0x00000C00L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK                                                   0x00003000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK                                                       0x00010000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK                                                       0x00020000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK                                                       0x00040000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK                                                       0x00080000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK                                                       0x00100000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK                                                       0x00200000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK                                                     0x00400000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK                                                      0x01000000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK                                                      0x02000000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK                                                      0x04000000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK                                                      0x08000000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK                                                      0x10000000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK                                                      0x20000000L
++#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK                                                    0x40000000L
++//DC_GPIO_AUX_CTRL_1
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT                                                       0x0
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT                                                       0x1
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT                                                       0x2
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT                                                       0x3
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT                                                       0x4
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT                                                       0x5
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT                                                       0x6
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT                                                       0x7
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT                                                      0x8
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT                                                      0x9
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT                                                      0xa
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT                                                      0xb
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT                                                       0xc
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT                                                       0xe
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT                                                       0x12
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT                                                       0x14
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT                                                       0x19
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT                                                       0x1a
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT                                                       0x1b
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT                                                       0x1c
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT                                                       0x1d
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT                                                     0x1e
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK                                                         0x00000001L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK                                                         0x00000002L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK                                                         0x00000004L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK                                                         0x00000008L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK                                                         0x00000010L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK                                                         0x00000020L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK                                                         0x00000040L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK                                                         0x00000080L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK                                                        0x00000100L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK                                                        0x00000200L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK                                                        0x00000400L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK                                                        0x00000800L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK                                                         0x00001000L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK                                                         0x0000C000L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK                                                         0x00040000L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK                                                         0x00300000L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK                                                         0x02000000L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK                                                         0x04000000L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK                                                         0x08000000L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK                                                         0x10000000L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK                                                         0x20000000L
++#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK                                                       0x40000000L
++//DC_GPIO_AUX_CTRL_2
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT                                                  0x0
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT                                                  0x2
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT                                                  0x4
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT                                                    0x8
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT                                                    0x9
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT                                                    0xa
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT                                                   0xc
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT                                                   0xd
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT                                                   0xe
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT                                                       0x10
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT                                                       0x11
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT                                                       0x12
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT                                                       0x13
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT                                                      0x14
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT                                                        0x18
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT                                                        0x19
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT                                                        0x1a
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT                                                      0x1b
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT                                                      0x1c
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT                                                      0x1d
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT                                                      0x1e
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK                                                    0x00000003L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK                                                    0x0000000CL
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK                                                    0x00000030L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK                                                      0x00000100L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK                                                      0x00000200L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK                                                      0x00000400L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK                                                     0x00001000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK                                                     0x00002000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK                                                     0x00004000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK                                                         0x00010000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK                                                         0x00020000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK                                                         0x00040000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK                                                         0x00080000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK                                                        0x00100000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK                                                          0x01000000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK                                                          0x02000000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK                                                          0x04000000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK                                                        0x08000000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK                                                        0x10000000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK                                                        0x20000000L
++#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK                                                        0x40000000L
++//DC_GPIO_RXEN
++#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT                                                            0x0
++#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT                                                            0x1
++#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT                                                            0x2
++#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT                                                            0x3
++#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT                                                            0x4
++#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT                                                            0x5
++#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT                                                            0x6
++#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT                                                              0x8
++#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT                                                              0x9
++#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT                                                           0xa
++#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT                                                         0xb
++#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT                                                          0xc
++#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT                                                          0xd
++#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT                                                                0xe
++#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT                                                                0xf
++#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT                                                                0x10
++#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT                                                                0x11
++#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT                                                                0x12
++#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT                                                                0x13
++#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN__SHIFT                                                                0x14
++#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN__SHIFT                                                               0x15
++#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN__SHIFT                                                              0x16
++#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK                                                              0x00000001L
++#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK                                                              0x00000002L
++#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK                                                              0x00000004L
++#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK                                                              0x00000008L
++#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK                                                              0x00000010L
++#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK                                                              0x00000020L
++#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK                                                              0x00000040L
++#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK                                                                0x00000100L
++#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK                                                                0x00000200L
++#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK                                                             0x00000400L
++#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK                                                           0x00000800L
++#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK                                                            0x00001000L
++#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK                                                            0x00002000L
++#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK                                                                  0x00004000L
++#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK                                                                  0x00008000L
++#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK                                                                  0x00010000L
++#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK                                                                  0x00020000L
++#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK                                                                  0x00040000L
++#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK                                                                  0x00080000L
++#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN_MASK                                                                  0x00100000L
++#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN_MASK                                                                 0x00200000L
++#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN_MASK                                                                0x00400000L
++//DC_GPIO_PULLUPEN
++#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT                                                       0x0
++#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT                                                       0x1
++#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT                                                       0x2
++#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT                                                       0x3
++#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT                                                       0x4
++#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT                                                       0x5
++#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT                                                       0x6
++#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT                                                         0x8
++#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT                                                         0x9
++#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT                                                           0xe
++#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT                                                           0xf
++#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT                                                           0x10
++#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT                                                           0x11
++#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT                                                           0x12
++#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT                                                           0x13
++#define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN__SHIFT                                                           0x14
++#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN__SHIFT                                                          0x15
++#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN__SHIFT                                                         0x16
++#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK                                                         0x00000001L
++#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK                                                         0x00000002L
++#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK                                                         0x00000004L
++#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK                                                         0x00000008L
++#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK                                                         0x00000010L
++#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK                                                         0x00000020L
++#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK                                                         0x00000040L
++#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK                                                           0x00000100L
++#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK                                                           0x00000200L
++#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK                                                             0x00004000L
++#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK                                                             0x00008000L
++#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK                                                             0x00010000L
++#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK                                                             0x00020000L
++#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK                                                             0x00040000L
++#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK                                                             0x00080000L
++#define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN_MASK                                                             0x00100000L
++#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN_MASK                                                            0x00200000L
++#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN_MASK                                                           0x00400000L
++//DC_GPIO_AUX_CTRL_3
++#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT                                                             0x0
++#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT                                                             0x1
++#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT                                                             0x2
++#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT                                                             0x3
++#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT                                                             0x4
++#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT                                                             0x5
++#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT                                                            0x8
++#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT                                                            0x9
++#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT                                                            0xa
++#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT                                                            0xb
++#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT                                                            0xc
++#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT                                                            0xd
++#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT                                                              0x10
++#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT                                                              0x12
++#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT                                                              0x14
++#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT                                                              0x16
++#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT                                                              0x18
++#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT                                                              0x1a
++#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK                                                               0x00000001L
++#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK                                                               0x00000002L
++#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK                                                               0x00000004L
++#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK                                                               0x00000008L
++#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK                                                               0x00000010L
++#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK                                                               0x00000020L
++#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK                                                              0x00000100L
++#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK                                                              0x00000200L
++#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK                                                              0x00000400L
++#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK                                                              0x00000800L
++#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK                                                              0x00001000L
++#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK                                                              0x00002000L
++#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK                                                                0x00030000L
++#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK                                                                0x000C0000L
++#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK                                                                0x00300000L
++#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK                                                                0x00C00000L
++#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK                                                                0x03000000L
++#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK                                                                0x0C000000L
++//DC_GPIO_AUX_CTRL_4
++#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT                                                              0x0
++#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT                                                              0x4
++#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT                                                              0x8
++#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT                                                              0xc
++#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT                                                              0x10
++#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT                                                              0x14
++#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK                                                                0x0000000FL
++#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK                                                                0x000000F0L
++#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK                                                                0x00000F00L
++#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK                                                                0x0000F000L
++#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK                                                                0x000F0000L
++#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK                                                                0x00F00000L
++//DC_GPIO_AUX_CTRL_5
++#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT                                                              0x0
++#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT                                                              0x2
++#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT                                                              0x4
++#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT                                                              0x6
++#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT                                                              0x8
++#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT                                                              0xa
++#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT                                                           0xc
++#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT                                                           0xd
++#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT                                                           0xe
++#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT                                                           0xf
++#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT                                                           0x10
++#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT                                                           0x11
++#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT                                                        0x12
++#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT                                                        0x13
++#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT                                                        0x14
++#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT                                                        0x15
++#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT                                                        0x16
++#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT                                                        0x17
++#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT                                                          0x18
++#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT                                                          0x19
++#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT                                                          0x1a
++#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT                                                          0x1b
++#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT                                                          0x1c
++#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT                                                          0x1d
++#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK                                                                0x00000003L
++#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK                                                                0x0000000CL
++#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK                                                                0x00000030L
++#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK                                                                0x000000C0L
++#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK                                                                0x00000300L
++#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK                                                                0x00000C00L
++#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK                                                             0x00001000L
++#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK                                                             0x00002000L
++#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK                                                             0x00004000L
++#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK                                                             0x00008000L
++#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK                                                             0x00010000L
++#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK                                                             0x00020000L
++#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK                                                          0x00040000L
++#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK                                                          0x00080000L
++#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK                                                          0x00100000L
++#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK                                                          0x00200000L
++#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK                                                          0x00400000L
++#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK                                                          0x00800000L
++#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK                                                            0x01000000L
++#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK                                                            0x02000000L
++#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK                                                            0x04000000L
++#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK                                                            0x08000000L
++#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK                                                            0x10000000L
++#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK                                                            0x20000000L
++//AUXI2C_PAD_ALL_PWR_OK
++#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT                                                  0x0
++#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT                                                  0x1
++#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT                                                  0x2
++#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT                                                  0x3
++#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT                                                  0x4
++#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT                                                  0x5
++#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK                                                    0x00000001L
++#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK                                                    0x00000002L
++#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK                                                    0x00000004L
++#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK                                                    0x00000008L
++#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK                                                    0x00000010L
++#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK                                                    0x00000020L
++
++// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
++//DSC_TOP0_DSC_TOP_CONTROL
++#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
++#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
++#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
++#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
++#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
++#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
++//DSC_TOP0_DSC_DEBUG_CONTROL
++#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
++#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
++#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
++#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
++
++
++// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
++//DSCCIF0_DSCCIF_CONFIG0
++#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
++#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
++#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
++#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
++#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
++#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
++#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
++#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
++#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
++#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
++#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
++#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
++//DSCCIF0_DSCCIF_CONFIG1
++#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
++#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
++#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
++#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
++
++
++// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
++//DSCC0_DSCC_CONFIG0
++#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
++#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
++#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
++#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
++#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
++#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
++#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
++#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
++//DSCC0_DSCC_CONFIG1
++#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
++#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
++#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
++#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
++//DSCC0_DSCC_STATUS
++#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
++#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
++//DSCC0_DSCC_INTERRUPT_CONTROL_STATUS
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
++#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
++//DSCC0_DSCC_PPS_CONFIG0
++#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
++#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
++#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
++#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
++#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
++#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
++#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
++#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
++#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
++#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
++//DSCC0_DSCC_PPS_CONFIG1
++#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
++#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
++#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
++#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
++#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
++#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
++#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
++#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
++#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
++#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
++#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
++#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
++#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
++#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
++#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
++#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
++//DSCC0_DSCC_PPS_CONFIG2
++#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
++#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
++#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
++#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
++//DSCC0_DSCC_PPS_CONFIG3
++#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
++#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
++#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
++#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
++//DSCC0_DSCC_PPS_CONFIG4
++#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
++#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
++#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
++#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
++//DSCC0_DSCC_PPS_CONFIG5
++#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
++#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
++#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
++#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
++//DSCC0_DSCC_PPS_CONFIG6
++#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
++#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
++#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
++#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
++#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
++#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
++//DSCC0_DSCC_PPS_CONFIG7
++#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
++#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
++#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
++#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
++//DSCC0_DSCC_PPS_CONFIG8
++#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
++#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
++#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
++#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
++//DSCC0_DSCC_PPS_CONFIG9
++#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
++#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
++#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
++#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
++//DSCC0_DSCC_PPS_CONFIG10
++#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
++#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
++#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
++#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
++#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
++#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
++//DSCC0_DSCC_PPS_CONFIG11
++#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
++#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
++#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
++#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
++#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
++#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
++#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
++#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
++#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
++#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
++//DSCC0_DSCC_PPS_CONFIG12
++#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
++#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
++#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
++#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
++#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
++#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
++#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
++#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
++//DSCC0_DSCC_PPS_CONFIG13
++#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
++#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
++#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
++#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
++#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
++#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
++#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
++#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
++//DSCC0_DSCC_PPS_CONFIG14
++#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
++#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
++#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
++#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
++#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
++#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
++#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
++#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
++//DSCC0_DSCC_PPS_CONFIG15
++#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
++#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
++#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
++#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
++#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
++#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
++#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
++#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
++#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
++#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
++//DSCC0_DSCC_PPS_CONFIG16
++#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
++#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
++#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
++#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
++#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
++#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
++#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
++#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
++#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
++#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
++#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
++#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
++//DSCC0_DSCC_PPS_CONFIG17
++#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
++#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
++#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
++#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
++#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
++#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
++#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
++#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
++#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
++#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
++#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
++#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
++//DSCC0_DSCC_PPS_CONFIG18
++#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
++#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
++#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
++#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
++#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
++#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
++#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
++#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
++#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
++#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
++#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
++#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
++//DSCC0_DSCC_PPS_CONFIG19
++#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
++#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
++#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
++#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
++#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
++#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
++#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
++#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
++#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
++#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
++#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
++#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
++//DSCC0_DSCC_PPS_CONFIG20
++#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
++#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
++#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
++#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
++#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
++#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
++#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
++#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
++#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
++#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
++#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
++#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
++//DSCC0_DSCC_PPS_CONFIG21
++#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
++#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
++#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
++#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
++#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
++#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
++#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
++#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
++#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
++#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
++#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
++#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
++//DSCC0_DSCC_PPS_CONFIG22
++#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
++#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
++#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
++#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
++#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
++#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
++#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
++#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
++#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
++#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
++#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
++#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
++//DSCC0_DSCC_MEM_POWER_CONTROL
++#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
++#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
++#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
++#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
++#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
++#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
++#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
++#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
++#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
++#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
++#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
++#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
++#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
++#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
++//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER
++#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
++#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
++//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER
++#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
++#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
++//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER
++#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
++#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
++//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER
++#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
++#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
++//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER
++#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
++#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
++//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER
++#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
++#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
++//DSCC0_DSCC_MAX_ABS_ERROR0
++#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
++#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
++#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
++#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
++//DSCC0_DSCC_MAX_ABS_ERROR1
++#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
++#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
++//DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
++#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
++#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
++#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
++#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
++#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
++#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
++#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
++#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE
++#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
++#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
++#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
++#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
++#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
++#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
++#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
++#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
++
++
++// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON19_PERFCOUNTER_CNTL
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
++#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
++//DC_PERFMON19_PERFCOUNTER_CNTL2
++#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
++#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
++#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
++#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
++#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
++#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
++#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
++#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
++#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
++#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
++//DC_PERFMON19_PERFCOUNTER_STATE
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
++#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
++//DC_PERFMON19_PERFMON_CNTL
++#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
++#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
++#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
++#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
++#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
++#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
++#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
++#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
++#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
++#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
++#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
++#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
++//DC_PERFMON19_PERFMON_CNTL2
++#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
++#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
++#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
++#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
++#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
++#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
++#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
++#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
++//DC_PERFMON19_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
++#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
++//DC_PERFMON19_PERFMON_CVALUE_LOW
++#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
++#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
++//DC_PERFMON19_PERFMON_HI
++#define DC_PERFMON19_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
++#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
++#define DC_PERFMON19_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
++#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
++//DC_PERFMON19_PERFMON_LOW
++#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
++#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
++//DSC_TOP1_DSC_TOP_CONTROL
++#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
++#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
++#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
++#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
++#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
++#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
++//DSC_TOP1_DSC_DEBUG_CONTROL
++#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
++#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
++#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
++#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
++
++
++// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
++//DSCCIF1_DSCCIF_CONFIG0
++#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
++#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
++#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
++#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
++#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
++#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
++#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
++#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
++#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
++#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
++#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
++#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
++//DSCCIF1_DSCCIF_CONFIG1
++#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
++#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
++#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
++#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
++
++
++// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
++//DSCC1_DSCC_CONFIG0
++#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
++#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
++#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
++#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
++#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
++#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
++#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
++#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
++//DSCC1_DSCC_CONFIG1
++#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
++#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
++#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
++#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
++//DSCC1_DSCC_STATUS
++#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
++#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
++//DSCC1_DSCC_INTERRUPT_CONTROL_STATUS
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
++#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
++//DSCC1_DSCC_PPS_CONFIG0
++#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
++#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
++#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
++#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
++#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
++#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
++#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
++#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
++#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
++#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
++//DSCC1_DSCC_PPS_CONFIG1
++#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
++#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
++#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
++#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
++#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
++#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
++#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
++#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
++#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
++#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
++#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
++#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
++#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
++#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
++#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
++#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
++//DSCC1_DSCC_PPS_CONFIG2
++#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
++#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
++#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
++#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
++//DSCC1_DSCC_PPS_CONFIG3
++#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
++#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
++#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
++#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
++//DSCC1_DSCC_PPS_CONFIG4
++#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
++#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
++#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
++#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
++//DSCC1_DSCC_PPS_CONFIG5
++#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
++#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
++#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
++#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
++//DSCC1_DSCC_PPS_CONFIG6
++#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
++#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
++#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
++#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
++#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
++#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
++//DSCC1_DSCC_PPS_CONFIG7
++#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
++#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
++#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
++#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
++//DSCC1_DSCC_PPS_CONFIG8
++#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
++#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
++#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
++#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
++//DSCC1_DSCC_PPS_CONFIG9
++#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
++#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
++#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
++#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
++//DSCC1_DSCC_PPS_CONFIG10
++#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
++#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
++#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
++#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
++#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
++#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
++//DSCC1_DSCC_PPS_CONFIG11
++#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
++#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
++#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
++#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
++#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
++#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
++#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
++#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
++#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
++#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
++//DSCC1_DSCC_PPS_CONFIG12
++#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
++#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
++#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
++#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
++#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
++#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
++#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
++#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
++//DSCC1_DSCC_PPS_CONFIG13
++#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
++#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
++#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
++#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
++#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
++#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
++#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
++#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
++//DSCC1_DSCC_PPS_CONFIG14
++#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
++#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
++#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
++#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
++#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
++#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
++#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
++#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
++//DSCC1_DSCC_PPS_CONFIG15
++#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
++#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
++#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
++#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
++#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
++#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
++#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
++#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
++#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
++#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
++//DSCC1_DSCC_PPS_CONFIG16
++#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
++#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
++#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
++#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
++#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
++#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
++#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
++#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
++#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
++#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
++#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
++#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
++//DSCC1_DSCC_PPS_CONFIG17
++#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
++#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
++#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
++#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
++#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
++#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
++#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
++#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
++#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
++#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
++#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
++#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
++//DSCC1_DSCC_PPS_CONFIG18
++#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
++#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
++#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
++#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
++#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
++#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
++#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
++#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
++#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
++#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
++#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
++#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
++//DSCC1_DSCC_PPS_CONFIG19
++#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
++#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
++#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
++#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
++#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
++#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
++#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
++#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
++#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
++#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
++#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
++#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
++//DSCC1_DSCC_PPS_CONFIG20
++#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
++#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
++#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
++#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
++#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
++#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
++#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
++#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
++#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
++#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
++#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
++#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
++//DSCC1_DSCC_PPS_CONFIG21
++#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
++#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
++#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
++#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
++#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
++#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
++#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
++#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
++#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
++#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
++#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
++#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
++//DSCC1_DSCC_PPS_CONFIG22
++#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
++#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
++#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
++#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
++#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
++#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
++#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
++#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
++#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
++#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
++#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
++#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
++//DSCC1_DSCC_MEM_POWER_CONTROL
++#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
++#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
++#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
++#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
++#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
++#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
++#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
++#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
++#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
++#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
++#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
++#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
++#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
++#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
++//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER
++#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
++#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
++//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER
++#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
++#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
++//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER
++#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
++#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
++//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER
++#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
++#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
++//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER
++#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
++#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
++//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER
++#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
++#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
++//DSCC1_DSCC_MAX_ABS_ERROR0
++#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
++#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
++#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
++#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
++//DSCC1_DSCC_MAX_ABS_ERROR1
++#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
++#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
++//DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
++#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
++#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
++#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
++#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
++#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
++#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
++#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
++#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE
++#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
++#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
++#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
++#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
++#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
++#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
++#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
++#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
++
++
++// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON20_PERFCOUNTER_CNTL
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
++#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
++//DC_PERFMON20_PERFCOUNTER_CNTL2
++#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
++#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
++#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
++#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
++#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
++#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
++#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
++#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
++#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
++#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
++//DC_PERFMON20_PERFCOUNTER_STATE
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
++#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
++//DC_PERFMON20_PERFMON_CNTL
++#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
++#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
++#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
++#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
++#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
++#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
++#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
++#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
++#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
++#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
++#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
++#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
++//DC_PERFMON20_PERFMON_CNTL2
++#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
++#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
++#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
++#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
++#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
++#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
++#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
++#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
++//DC_PERFMON20_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
++#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
++//DC_PERFMON20_PERFMON_CVALUE_LOW
++#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
++#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
++//DC_PERFMON20_PERFMON_HI
++#define DC_PERFMON20_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
++#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
++#define DC_PERFMON20_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
++#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
++//DC_PERFMON20_PERFMON_LOW
++#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
++#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
++//DSC_TOP2_DSC_TOP_CONTROL
++#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
++#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
++#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
++#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
++#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
++#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
++//DSC_TOP2_DSC_DEBUG_CONTROL
++#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
++#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
++#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
++#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
++
++
++// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
++//DSCCIF2_DSCCIF_CONFIG0
++#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
++#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
++#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
++#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
++#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
++#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
++#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
++#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
++#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
++#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
++#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
++#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
++//DSCCIF2_DSCCIF_CONFIG1
++#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
++#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
++#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
++#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
++
++
++// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
++//DSCC2_DSCC_CONFIG0
++#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
++#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
++#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
++#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
++#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
++#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
++#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
++#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
++//DSCC2_DSCC_CONFIG1
++#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
++#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
++#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
++#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
++//DSCC2_DSCC_STATUS
++#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
++#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
++//DSCC2_DSCC_INTERRUPT_CONTROL_STATUS
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
++#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
++//DSCC2_DSCC_PPS_CONFIG0
++#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
++#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
++#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
++#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
++#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
++#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
++#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
++#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
++#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
++#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
++//DSCC2_DSCC_PPS_CONFIG1
++#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
++#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
++#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
++#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
++#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
++#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
++#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
++#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
++#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
++#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
++#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
++#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
++#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
++#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
++#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
++#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
++//DSCC2_DSCC_PPS_CONFIG2
++#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
++#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
++#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
++#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
++//DSCC2_DSCC_PPS_CONFIG3
++#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
++#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
++#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
++#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
++//DSCC2_DSCC_PPS_CONFIG4
++#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
++#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
++#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
++#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
++//DSCC2_DSCC_PPS_CONFIG5
++#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
++#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
++#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
++#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
++//DSCC2_DSCC_PPS_CONFIG6
++#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
++#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
++#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
++#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
++#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
++#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
++//DSCC2_DSCC_PPS_CONFIG7
++#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
++#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
++#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
++#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
++//DSCC2_DSCC_PPS_CONFIG8
++#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
++#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
++#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
++#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
++//DSCC2_DSCC_PPS_CONFIG9
++#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
++#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
++#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
++#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
++//DSCC2_DSCC_PPS_CONFIG10
++#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
++#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
++#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
++#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
++#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
++#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
++//DSCC2_DSCC_PPS_CONFIG11
++#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
++#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
++#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
++#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
++#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
++#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
++#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
++#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
++#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
++#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
++//DSCC2_DSCC_PPS_CONFIG12
++#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
++#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
++#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
++#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
++#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
++#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
++#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
++#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
++//DSCC2_DSCC_PPS_CONFIG13
++#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
++#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
++#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
++#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
++#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
++#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
++#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
++#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
++//DSCC2_DSCC_PPS_CONFIG14
++#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
++#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
++#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
++#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
++#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
++#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
++#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
++#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
++//DSCC2_DSCC_PPS_CONFIG15
++#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
++#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
++#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
++#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
++#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
++#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
++#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
++#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
++#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
++#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
++//DSCC2_DSCC_PPS_CONFIG16
++#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
++#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
++#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
++#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
++#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
++#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
++#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
++#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
++#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
++#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
++#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
++#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
++//DSCC2_DSCC_PPS_CONFIG17
++#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
++#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
++#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
++#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
++#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
++#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
++#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
++#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
++#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
++#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
++#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
++#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
++//DSCC2_DSCC_PPS_CONFIG18
++#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
++#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
++#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
++#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
++#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
++#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
++#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
++#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
++#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
++#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
++#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
++#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
++//DSCC2_DSCC_PPS_CONFIG19
++#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
++#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
++#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
++#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
++#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
++#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
++#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
++#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
++#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
++#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
++#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
++#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
++//DSCC2_DSCC_PPS_CONFIG20
++#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
++#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
++#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
++#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
++#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
++#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
++#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
++#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
++#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
++#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
++#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
++#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
++//DSCC2_DSCC_PPS_CONFIG21
++#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
++#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
++#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
++#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
++#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
++#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
++#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
++#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
++#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
++#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
++#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
++#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
++//DSCC2_DSCC_PPS_CONFIG22
++#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
++#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
++#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
++#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
++#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
++#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
++#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
++#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
++#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
++#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
++#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
++#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
++//DSCC2_DSCC_MEM_POWER_CONTROL
++#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
++#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
++#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
++#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
++#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
++#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
++#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
++#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
++#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
++#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
++#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
++#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
++#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
++#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
++//DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER
++#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
++#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
++//DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER
++#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
++#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
++//DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER
++#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
++#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
++//DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER
++#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
++#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
++//DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER
++#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
++#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
++//DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER
++#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
++#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
++//DSCC2_DSCC_MAX_ABS_ERROR0
++#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
++#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
++#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
++#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
++//DSCC2_DSCC_MAX_ABS_ERROR1
++#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
++#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
++//DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
++#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
++#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
++#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
++#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
++#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
++#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
++#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
++#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE
++#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
++#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
++#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
++#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
++#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
++#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
++#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
++#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
++
++
++// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON21_PERFCOUNTER_CNTL
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
++#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
++//DC_PERFMON21_PERFCOUNTER_CNTL2
++#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
++#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
++#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
++#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
++#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
++#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
++#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
++#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
++#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
++#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
++//DC_PERFMON21_PERFCOUNTER_STATE
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
++#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
++//DC_PERFMON21_PERFMON_CNTL
++#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
++#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
++#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
++#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
++#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
++#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
++#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
++#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
++#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
++#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
++#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
++#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
++//DC_PERFMON21_PERFMON_CNTL2
++#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
++#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
++#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
++#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
++#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
++#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
++#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
++#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
++//DC_PERFMON21_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
++#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
++//DC_PERFMON21_PERFMON_CVALUE_LOW
++#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
++#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
++//DC_PERFMON21_PERFMON_HI
++#define DC_PERFMON21_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
++#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
++#define DC_PERFMON21_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
++#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
++//DC_PERFMON21_PERFMON_LOW
++#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
++#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec
++//DSC_TOP3_DSC_TOP_CONTROL
++#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
++#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
++#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
++#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
++#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
++#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
++//DSC_TOP3_DSC_DEBUG_CONTROL
++#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
++#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
++#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
++#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
++
++
++// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec
++//DSCCIF3_DSCCIF_CONFIG0
++#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
++#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
++#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
++#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
++#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
++#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
++#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
++#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
++#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
++#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
++#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
++#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
++//DSCCIF3_DSCCIF_CONFIG1
++#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
++#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
++#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
++#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
++
++
++// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec
++//DSCC3_DSCC_CONFIG0
++#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
++#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
++#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
++#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
++#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
++#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
++#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
++#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
++//DSCC3_DSCC_CONFIG1
++#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
++#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
++#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
++#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
++//DSCC3_DSCC_STATUS
++#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
++#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
++//DSCC3_DSCC_INTERRUPT_CONTROL_STATUS
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
++#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
++//DSCC3_DSCC_PPS_CONFIG0
++#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
++#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
++#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
++#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
++#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
++#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
++#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
++#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
++#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
++#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
++//DSCC3_DSCC_PPS_CONFIG1
++#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
++#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
++#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
++#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
++#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
++#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
++#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
++#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
++#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
++#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
++#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
++#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
++#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
++#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
++#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
++#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
++//DSCC3_DSCC_PPS_CONFIG2
++#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
++#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
++#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
++#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
++//DSCC3_DSCC_PPS_CONFIG3
++#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
++#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
++#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
++#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
++//DSCC3_DSCC_PPS_CONFIG4
++#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
++#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
++#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
++#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
++//DSCC3_DSCC_PPS_CONFIG5
++#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
++#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
++#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
++#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
++//DSCC3_DSCC_PPS_CONFIG6
++#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
++#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
++#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
++#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
++#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
++#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
++//DSCC3_DSCC_PPS_CONFIG7
++#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
++#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
++#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
++#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
++//DSCC3_DSCC_PPS_CONFIG8
++#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
++#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
++#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
++#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
++//DSCC3_DSCC_PPS_CONFIG9
++#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
++#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
++#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
++#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
++//DSCC3_DSCC_PPS_CONFIG10
++#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
++#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
++#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
++#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
++#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
++#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
++//DSCC3_DSCC_PPS_CONFIG11
++#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
++#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
++#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
++#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
++#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
++#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
++#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
++#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
++#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
++#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
++//DSCC3_DSCC_PPS_CONFIG12
++#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
++#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
++#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
++#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
++#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
++#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
++#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
++#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
++//DSCC3_DSCC_PPS_CONFIG13
++#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
++#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
++#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
++#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
++#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
++#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
++#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
++#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
++//DSCC3_DSCC_PPS_CONFIG14
++#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
++#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
++#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
++#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
++#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
++#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
++#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
++#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
++//DSCC3_DSCC_PPS_CONFIG15
++#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
++#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
++#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
++#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
++#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
++#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
++#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
++#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
++#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
++#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
++//DSCC3_DSCC_PPS_CONFIG16
++#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
++#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
++#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
++#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
++#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
++#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
++#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
++#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
++#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
++#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
++#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
++#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
++//DSCC3_DSCC_PPS_CONFIG17
++#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
++#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
++#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
++#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
++#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
++#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
++#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
++#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
++#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
++#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
++#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
++#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
++//DSCC3_DSCC_PPS_CONFIG18
++#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
++#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
++#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
++#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
++#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
++#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
++#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
++#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
++#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
++#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
++#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
++#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
++//DSCC3_DSCC_PPS_CONFIG19
++#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
++#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
++#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
++#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
++#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
++#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
++#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
++#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
++#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
++#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
++#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
++#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
++//DSCC3_DSCC_PPS_CONFIG20
++#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
++#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
++#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
++#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
++#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
++#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
++#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
++#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
++#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
++#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
++#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
++#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
++//DSCC3_DSCC_PPS_CONFIG21
++#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
++#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
++#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
++#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
++#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
++#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
++#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
++#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
++#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
++#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
++#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
++#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
++//DSCC3_DSCC_PPS_CONFIG22
++#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
++#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
++#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
++#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
++#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
++#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
++#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
++#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
++#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
++#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
++#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
++#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
++//DSCC3_DSCC_MEM_POWER_CONTROL
++#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
++#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
++#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
++#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
++#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
++#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
++#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
++#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
++#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
++#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
++#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
++#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
++#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
++#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
++//DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER
++#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
++#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
++//DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER
++#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
++#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
++//DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER
++#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
++#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
++//DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER
++#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
++#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
++//DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER
++#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
++#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
++//DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER
++#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
++#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
++//DSCC3_DSCC_MAX_ABS_ERROR0
++#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
++#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
++#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
++#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
++//DSCC3_DSCC_MAX_ABS_ERROR1
++#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
++#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
++//DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
++#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
++#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
++#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
++#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
++#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
++#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
++#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
++#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE
++#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
++#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
++#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
++#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
++#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
++#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
++#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
++#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
++
++
++// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON22_PERFCOUNTER_CNTL
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
++#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
++//DC_PERFMON22_PERFCOUNTER_CNTL2
++#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
++#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
++#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
++#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
++#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
++#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
++#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
++#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
++#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
++#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
++//DC_PERFMON22_PERFCOUNTER_STATE
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
++#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
++//DC_PERFMON22_PERFMON_CNTL
++#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
++#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
++#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
++#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
++#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
++#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
++#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
++#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
++#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
++#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
++#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
++#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
++//DC_PERFMON22_PERFMON_CNTL2
++#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
++#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
++#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
++#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
++#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
++#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
++#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
++#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
++//DC_PERFMON22_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
++#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
++//DC_PERFMON22_PERFMON_CVALUE_LOW
++#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
++#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
++//DC_PERFMON22_PERFMON_HI
++#define DC_PERFMON22_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
++#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
++#define DC_PERFMON22_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
++#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
++//DC_PERFMON22_PERFMON_LOW
++#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
++#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dsc4_dispdec_dsc_top_dispdec
++//DSC_TOP4_DSC_TOP_CONTROL
++#define DSC_TOP4_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
++#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
++#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
++#define DSC_TOP4_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
++#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
++#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
++//DSC_TOP4_DSC_DEBUG_CONTROL
++#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
++#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
++#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
++#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
++
++
++// addressBlock: dce_dc_dsc4_dispdec_dsccif_dispdec
++//DSCCIF4_DSCCIF_CONFIG0
++#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
++#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
++#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
++#define DSCCIF4_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
++#define DSCCIF4_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
++#define DSCCIF4_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
++#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
++#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
++#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
++#define DSCCIF4_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
++#define DSCCIF4_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
++#define DSCCIF4_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
++//DSCCIF4_DSCCIF_CONFIG1
++#define DSCCIF4_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
++#define DSCCIF4_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
++#define DSCCIF4_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
++#define DSCCIF4_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
++
++
++// addressBlock: dce_dc_dsc4_dispdec_dscc_dispdec
++//DSCC4_DSCC_CONFIG0
++#define DSCC4_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
++#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
++#define DSCC4_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
++#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
++#define DSCC4_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
++#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
++#define DSCC4_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
++#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
++//DSCC4_DSCC_CONFIG1
++#define DSCC4_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
++#define DSCC4_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
++#define DSCC4_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
++#define DSCC4_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
++//DSCC4_DSCC_STATUS
++#define DSCC4_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
++#define DSCC4_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
++//DSCC4_DSCC_INTERRUPT_CONTROL_STATUS
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
++#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
++//DSCC4_DSCC_PPS_CONFIG0
++#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
++#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
++#define DSCC4_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
++#define DSCC4_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
++#define DSCC4_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
++#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
++#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
++#define DSCC4_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
++#define DSCC4_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
++#define DSCC4_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
++//DSCC4_DSCC_PPS_CONFIG1
++#define DSCC4_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
++#define DSCC4_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
++#define DSCC4_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
++#define DSCC4_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
++#define DSCC4_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
++#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
++#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
++#define DSCC4_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
++#define DSCC4_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
++#define DSCC4_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
++#define DSCC4_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
++#define DSCC4_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
++#define DSCC4_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
++#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
++#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
++#define DSCC4_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
++//DSCC4_DSCC_PPS_CONFIG2
++#define DSCC4_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
++#define DSCC4_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
++#define DSCC4_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
++#define DSCC4_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
++//DSCC4_DSCC_PPS_CONFIG3
++#define DSCC4_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
++#define DSCC4_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
++#define DSCC4_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
++#define DSCC4_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
++//DSCC4_DSCC_PPS_CONFIG4
++#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
++#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
++#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
++#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
++//DSCC4_DSCC_PPS_CONFIG5
++#define DSCC4_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
++#define DSCC4_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
++#define DSCC4_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
++#define DSCC4_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
++//DSCC4_DSCC_PPS_CONFIG6
++#define DSCC4_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
++#define DSCC4_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
++#define DSCC4_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
++#define DSCC4_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
++#define DSCC4_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
++#define DSCC4_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
++//DSCC4_DSCC_PPS_CONFIG7
++#define DSCC4_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
++#define DSCC4_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
++#define DSCC4_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
++#define DSCC4_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
++//DSCC4_DSCC_PPS_CONFIG8
++#define DSCC4_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
++#define DSCC4_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
++#define DSCC4_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
++#define DSCC4_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
++//DSCC4_DSCC_PPS_CONFIG9
++#define DSCC4_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
++#define DSCC4_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
++#define DSCC4_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
++#define DSCC4_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
++//DSCC4_DSCC_PPS_CONFIG10
++#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
++#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
++#define DSCC4_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
++#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
++#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
++#define DSCC4_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
++//DSCC4_DSCC_PPS_CONFIG11
++#define DSCC4_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
++#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
++#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
++#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
++#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
++#define DSCC4_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
++#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
++#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
++#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
++#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
++//DSCC4_DSCC_PPS_CONFIG12
++#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
++#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
++#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
++#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
++#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
++#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
++#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
++#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
++//DSCC4_DSCC_PPS_CONFIG13
++#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
++#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
++#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
++#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
++#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
++#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
++#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
++#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
++//DSCC4_DSCC_PPS_CONFIG14
++#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
++#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
++#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
++#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
++#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
++#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
++#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
++#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
++//DSCC4_DSCC_PPS_CONFIG15
++#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
++#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
++#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
++#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
++#define DSCC4_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
++#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
++#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
++#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
++#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
++#define DSCC4_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
++//DSCC4_DSCC_PPS_CONFIG16
++#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
++#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
++#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
++#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
++#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
++#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
++#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
++#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
++#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
++#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
++#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
++#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
++//DSCC4_DSCC_PPS_CONFIG17
++#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
++#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
++#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
++#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
++#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
++#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
++#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
++#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
++#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
++#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
++#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
++#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
++//DSCC4_DSCC_PPS_CONFIG18
++#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
++#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
++#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
++#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
++#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
++#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
++#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
++#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
++#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
++#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
++#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
++#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
++//DSCC4_DSCC_PPS_CONFIG19
++#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
++#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
++#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
++#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
++#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
++#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
++#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
++#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
++#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
++#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
++#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
++#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
++//DSCC4_DSCC_PPS_CONFIG20
++#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
++#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
++#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
++#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
++#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
++#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
++#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
++#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
++#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
++#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
++#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
++#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
++//DSCC4_DSCC_PPS_CONFIG21
++#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
++#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
++#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
++#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
++#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
++#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
++#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
++#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
++#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
++#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
++#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
++#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
++//DSCC4_DSCC_PPS_CONFIG22
++#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
++#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
++#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
++#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
++#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
++#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
++#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
++#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
++#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
++#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
++#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
++#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
++//DSCC4_DSCC_MEM_POWER_CONTROL
++#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
++#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
++#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
++#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
++#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
++#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
++#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
++#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
++#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
++#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
++#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
++#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
++#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
++#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
++//DSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER
++#define DSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
++#define DSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
++//DSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER
++#define DSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
++#define DSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
++//DSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER
++#define DSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
++#define DSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
++//DSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER
++#define DSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
++#define DSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
++//DSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER
++#define DSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
++#define DSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
++//DSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER
++#define DSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
++#define DSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
++//DSCC4_DSCC_MAX_ABS_ERROR0
++#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
++#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
++#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
++#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
++//DSCC4_DSCC_MAX_ABS_ERROR1
++#define DSCC4_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
++#define DSCC4_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
++//DSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
++#define DSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
++#define DSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
++#define DSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
++#define DSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
++#define DSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
++#define DSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
++#define DSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
++#define DSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE
++#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
++#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
++#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
++#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
++#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
++#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
++#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
++#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
++
++
++// addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON23_PERFCOUNTER_CNTL
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
++#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
++//DC_PERFMON23_PERFCOUNTER_CNTL2
++#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
++#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
++#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
++#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
++#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
++#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
++#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
++#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
++#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
++#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
++//DC_PERFMON23_PERFCOUNTER_STATE
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
++#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
++//DC_PERFMON23_PERFMON_CNTL
++#define DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
++#define DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
++#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
++#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
++#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
++#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
++#define DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
++#define DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
++#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
++#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
++#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
++#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
++//DC_PERFMON23_PERFMON_CNTL2
++#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
++#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
++#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
++#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
++#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
++#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
++#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
++#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
++//DC_PERFMON23_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
++#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
++//DC_PERFMON23_PERFMON_CVALUE_LOW
++#define DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
++#define DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
++//DC_PERFMON23_PERFMON_HI
++#define DC_PERFMON23_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
++#define DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
++#define DC_PERFMON23_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
++#define DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
++//DC_PERFMON23_PERFMON_LOW
++#define DC_PERFMON23_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
++#define DC_PERFMON23_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dsc5_dispdec_dsc_top_dispdec
++//DSC_TOP5_DSC_TOP_CONTROL
++#define DSC_TOP5_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
++#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
++#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
++#define DSC_TOP5_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
++#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
++#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
++//DSC_TOP5_DSC_DEBUG_CONTROL
++#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
++#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
++#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
++#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
++
++
++// addressBlock: dce_dc_dsc5_dispdec_dsccif_dispdec
++//DSCCIF5_DSCCIF_CONFIG0
++#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
++#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
++#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
++#define DSCCIF5_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
++#define DSCCIF5_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
++#define DSCCIF5_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
++#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
++#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
++#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
++#define DSCCIF5_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
++#define DSCCIF5_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
++#define DSCCIF5_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
++//DSCCIF5_DSCCIF_CONFIG1
++#define DSCCIF5_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
++#define DSCCIF5_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
++#define DSCCIF5_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
++#define DSCCIF5_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
++
++
++// addressBlock: dce_dc_dsc5_dispdec_dscc_dispdec
++//DSCC5_DSCC_CONFIG0
++#define DSCC5_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
++#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
++#define DSCC5_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
++#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
++#define DSCC5_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
++#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
++#define DSCC5_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
++#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
++//DSCC5_DSCC_CONFIG1
++#define DSCC5_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
++#define DSCC5_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
++#define DSCC5_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
++#define DSCC5_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
++//DSCC5_DSCC_STATUS
++#define DSCC5_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
++#define DSCC5_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
++//DSCC5_DSCC_INTERRUPT_CONTROL_STATUS
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
++#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
++//DSCC5_DSCC_PPS_CONFIG0
++#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
++#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
++#define DSCC5_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
++#define DSCC5_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
++#define DSCC5_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
++#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
++#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
++#define DSCC5_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
++#define DSCC5_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
++#define DSCC5_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
++//DSCC5_DSCC_PPS_CONFIG1
++#define DSCC5_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
++#define DSCC5_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
++#define DSCC5_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
++#define DSCC5_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
++#define DSCC5_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
++#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
++#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
++#define DSCC5_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
++#define DSCC5_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
++#define DSCC5_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
++#define DSCC5_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
++#define DSCC5_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
++#define DSCC5_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
++#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
++#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
++#define DSCC5_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
++//DSCC5_DSCC_PPS_CONFIG2
++#define DSCC5_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
++#define DSCC5_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
++#define DSCC5_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
++#define DSCC5_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
++//DSCC5_DSCC_PPS_CONFIG3
++#define DSCC5_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
++#define DSCC5_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
++#define DSCC5_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
++#define DSCC5_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
++//DSCC5_DSCC_PPS_CONFIG4
++#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
++#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
++#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
++#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
++//DSCC5_DSCC_PPS_CONFIG5
++#define DSCC5_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
++#define DSCC5_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
++#define DSCC5_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
++#define DSCC5_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
++//DSCC5_DSCC_PPS_CONFIG6
++#define DSCC5_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
++#define DSCC5_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
++#define DSCC5_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
++#define DSCC5_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
++#define DSCC5_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
++#define DSCC5_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
++//DSCC5_DSCC_PPS_CONFIG7
++#define DSCC5_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
++#define DSCC5_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
++#define DSCC5_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
++#define DSCC5_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
++//DSCC5_DSCC_PPS_CONFIG8
++#define DSCC5_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
++#define DSCC5_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
++#define DSCC5_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
++#define DSCC5_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
++//DSCC5_DSCC_PPS_CONFIG9
++#define DSCC5_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
++#define DSCC5_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
++#define DSCC5_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
++#define DSCC5_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
++//DSCC5_DSCC_PPS_CONFIG10
++#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
++#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
++#define DSCC5_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
++#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
++#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
++#define DSCC5_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
++//DSCC5_DSCC_PPS_CONFIG11
++#define DSCC5_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
++#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
++#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
++#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
++#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
++#define DSCC5_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
++#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
++#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
++#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
++#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
++//DSCC5_DSCC_PPS_CONFIG12
++#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
++#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
++#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
++#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
++#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
++#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
++#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
++#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
++//DSCC5_DSCC_PPS_CONFIG13
++#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
++#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
++#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
++#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
++#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
++#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
++#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
++#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
++//DSCC5_DSCC_PPS_CONFIG14
++#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
++#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
++#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
++#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
++#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
++#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
++#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
++#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
++//DSCC5_DSCC_PPS_CONFIG15
++#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
++#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
++#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
++#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
++#define DSCC5_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
++#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
++#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
++#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
++#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
++#define DSCC5_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
++//DSCC5_DSCC_PPS_CONFIG16
++#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
++#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
++#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
++#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
++#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
++#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
++#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
++#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
++#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
++#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
++#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
++#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
++//DSCC5_DSCC_PPS_CONFIG17
++#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
++#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
++#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
++#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
++#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
++#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
++#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
++#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
++#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
++#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
++#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
++#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
++//DSCC5_DSCC_PPS_CONFIG18
++#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
++#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
++#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
++#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
++#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
++#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
++#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
++#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
++#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
++#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
++#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
++#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
++//DSCC5_DSCC_PPS_CONFIG19
++#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
++#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
++#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
++#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
++#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
++#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
++#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
++#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
++#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
++#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
++#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
++#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
++//DSCC5_DSCC_PPS_CONFIG20
++#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
++#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
++#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
++#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
++#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
++#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
++#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
++#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
++#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
++#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
++#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
++#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
++//DSCC5_DSCC_PPS_CONFIG21
++#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
++#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
++#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
++#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
++#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
++#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
++#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
++#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
++#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
++#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
++#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
++#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
++//DSCC5_DSCC_PPS_CONFIG22
++#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
++#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
++#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
++#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
++#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
++#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
++#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
++#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
++#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
++#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
++#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
++#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
++//DSCC5_DSCC_MEM_POWER_CONTROL
++#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
++#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
++#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
++#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
++#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
++#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
++#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
++#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
++#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
++#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
++#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
++#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
++#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
++#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
++//DSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER
++#define DSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
++#define DSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
++//DSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER
++#define DSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
++#define DSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
++//DSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER
++#define DSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
++#define DSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
++//DSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER
++#define DSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
++#define DSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
++//DSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER
++#define DSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
++#define DSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
++//DSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER
++#define DSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
++#define DSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
++//DSCC5_DSCC_MAX_ABS_ERROR0
++#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
++#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
++#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
++#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
++//DSCC5_DSCC_MAX_ABS_ERROR1
++#define DSCC5_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
++#define DSCC5_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
++//DSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
++#define DSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
++#define DSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
++#define DSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
++#define DSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
++#define DSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
++//DSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
++#define DSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
++#define DSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
++#define DSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
++#define DSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
++#define DSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
++//DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE
++#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
++#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
++#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
++#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
++#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
++#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
++#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
++#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
++
++
++// addressBlock: dce_dc_dsc5_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
++//DC_PERFMON24_PERFCOUNTER_CNTL
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
++#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
++//DC_PERFMON24_PERFCOUNTER_CNTL2
++#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
++#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
++#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
++#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
++#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
++#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
++#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
++#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
++#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
++#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
++//DC_PERFMON24_PERFCOUNTER_STATE
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
++#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
++//DC_PERFMON24_PERFMON_CNTL
++#define DC_PERFMON24_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
++#define DC_PERFMON24_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
++#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
++#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
++#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
++#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
++#define DC_PERFMON24_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
++#define DC_PERFMON24_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
++#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
++#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
++#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
++#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
++//DC_PERFMON24_PERFMON_CNTL2
++#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
++#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
++#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
++#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
++#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
++#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
++#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
++#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
++//DC_PERFMON24_PERFMON_CVALUE_INT_MISC
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
++#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
++//DC_PERFMON24_PERFMON_CVALUE_LOW
++#define DC_PERFMON24_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
++#define DC_PERFMON24_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
++//DC_PERFMON24_PERFMON_HI
++#define DC_PERFMON24_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
++#define DC_PERFMON24_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
++#define DC_PERFMON24_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
++#define DC_PERFMON24_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
++//DC_PERFMON24_PERFMON_LOW
++#define DC_PERFMON24_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
++#define DC_PERFMON24_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
++
++
++// addressBlock: dce_dc_dmu_dmcub_dispdec
++//DMCUB_REGION0_OFFSET
++#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT                                                     0x8
++#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK                                                       0xFFFFFF00L
++//DMCUB_REGION0_OFFSET_HIGH
++#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT                                           0x0
++#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK                                             0x0000FFFFL
++//DMCUB_REGION1_OFFSET
++#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT                                                     0x8
++#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK                                                       0xFFFFFF00L
++//DMCUB_REGION1_OFFSET_HIGH
++#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT                                           0x0
++#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK                                             0x0000FFFFL
++//DMCUB_REGION2_OFFSET
++#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT                                                     0x8
++#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK                                                       0xFFFFFF00L
++//DMCUB_REGION2_OFFSET_HIGH
++#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT                                           0x0
++#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK                                             0x0000FFFFL
++//DMCUB_REGION4_OFFSET
++#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT                                                     0x8
++#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK                                                       0xFFFFFF00L
++//DMCUB_REGION4_OFFSET_HIGH
++#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT                                           0x0
++#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK                                             0x0000FFFFL
++//DMCUB_REGION5_OFFSET
++#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT                                                     0x8
++#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK                                                       0xFFFFFF00L
++//DMCUB_REGION5_OFFSET_HIGH
++#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT                                           0x0
++#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK                                             0x0000FFFFL
++//DMCUB_REGION6_OFFSET
++#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT                                                     0x8
++#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK                                                       0xFFFFFF00L
++//DMCUB_REGION6_OFFSET_HIGH
++#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT                                           0x0
++#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK                                             0x0000FFFFL
++//DMCUB_REGION7_OFFSET
++#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT                                                     0x8
++#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK                                                       0xFFFFFF00L
++//DMCUB_REGION7_OFFSET_HIGH
++#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT                                           0x0
++#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK                                             0x0000FFFFL
++//DMCUB_REGION0_TOP_ADDRESS
++#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT                                           0x0
++#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT                                                0x1f
++#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
++#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK                                                  0x80000000L
++//DMCUB_REGION1_TOP_ADDRESS
++#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT                                           0x0
++#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT                                                0x1f
++#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
++#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK                                                  0x80000000L
++//DMCUB_REGION2_TOP_ADDRESS
++#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT                                           0x0
++#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT                                                0x1f
++#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
++#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK                                                  0x80000000L
++//DMCUB_REGION4_TOP_ADDRESS
++#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT                                           0x0
++#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT                                                0x1f
++#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
++#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK                                                  0x80000000L
++//DMCUB_REGION5_TOP_ADDRESS
++#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT                                           0x0
++#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT                                                0x1f
++#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
++#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK                                                  0x80000000L
++//DMCUB_REGION6_TOP_ADDRESS
++#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT                                           0x0
++#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT                                                0x1f
++#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
++#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK                                                  0x80000000L
++//DMCUB_REGION7_TOP_ADDRESS
++#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT                                           0x0
++#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT                                                0x1f
++#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
++#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK                                                  0x80000000L
++//DMCUB_REGION3_CW0_BASE_ADDRESS
++#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT                                 0x0
++#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
++//DMCUB_REGION3_CW1_BASE_ADDRESS
++#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT                                 0x0
++#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
++//DMCUB_REGION3_CW2_BASE_ADDRESS
++#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT                                 0x0
++#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
++//DMCUB_REGION3_CW3_BASE_ADDRESS
++#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT                                 0x0
++#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
++//DMCUB_REGION3_CW4_BASE_ADDRESS
++#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT                                 0x0
++#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
++//DMCUB_REGION3_CW5_BASE_ADDRESS
++#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT                                 0x0
++#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
++//DMCUB_REGION3_CW6_BASE_ADDRESS
++#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT                                 0x0
++#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
++//DMCUB_REGION3_CW7_BASE_ADDRESS
++#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT                                 0x0
++#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
++//DMCUB_REGION3_CW0_TOP_ADDRESS
++#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT                                   0x0
++#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT                                        0x1f
++#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
++#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK                                          0x80000000L
++//DMCUB_REGION3_CW1_TOP_ADDRESS
++#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT                                   0x0
++#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT                                        0x1f
++#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
++#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK                                          0x80000000L
++//DMCUB_REGION3_CW2_TOP_ADDRESS
++#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT                                   0x0
++#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT                                        0x1f
++#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
++#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK                                          0x80000000L
++//DMCUB_REGION3_CW3_TOP_ADDRESS
++#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT                                   0x0
++#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT                                        0x1f
++#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
++#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK                                          0x80000000L
++//DMCUB_REGION3_CW4_TOP_ADDRESS
++#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT                                   0x0
++#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT                                        0x1f
++#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
++#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK                                          0x80000000L
++//DMCUB_REGION3_CW5_TOP_ADDRESS
++#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT                                   0x0
++#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT                                        0x1f
++#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
++#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK                                          0x80000000L
++//DMCUB_REGION3_CW6_TOP_ADDRESS
++#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT                                   0x0
++#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT                                        0x1f
++#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
++#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK                                          0x80000000L
++//DMCUB_REGION3_CW7_TOP_ADDRESS
++#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT                                   0x0
++#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT                                        0x1f
++#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
++#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK                                          0x80000000L
++//DMCUB_REGION3_CW0_OFFSET
++#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT                                             0x8
++#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK                                               0xFFFFFF00L
++//DMCUB_REGION3_CW0_OFFSET_HIGH
++#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT                                   0x0
++#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK                                     0x0000FFFFL
++//DMCUB_REGION3_CW1_OFFSET
++#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT                                             0x8
++#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK                                               0xFFFFFF00L
++//DMCUB_REGION3_CW1_OFFSET_HIGH
++#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT                                   0x0
++#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK                                     0x0000FFFFL
++//DMCUB_REGION3_CW2_OFFSET
++#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT                                             0x8
++#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK                                               0xFFFFFF00L
++//DMCUB_REGION3_CW2_OFFSET_HIGH
++#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT                                   0x0
++#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK                                     0x0000FFFFL
++//DMCUB_REGION3_CW3_OFFSET
++#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT                                             0x8
++#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK                                               0xFFFFFF00L
++//DMCUB_REGION3_CW3_OFFSET_HIGH
++#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT                                   0x0
++#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK                                     0x0000FFFFL
++//DMCUB_REGION3_CW4_OFFSET
++#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT                                             0x8
++#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK                                               0xFFFFFF00L
++//DMCUB_REGION3_CW4_OFFSET_HIGH
++#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT                                   0x0
++#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK                                     0x0000FFFFL
++//DMCUB_REGION3_CW5_OFFSET
++#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT                                             0x8
++#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK                                               0xFFFFFF00L
++//DMCUB_REGION3_CW5_OFFSET_HIGH
++#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT                                   0x0
++#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK                                     0x0000FFFFL
++//DMCUB_REGION3_CW6_OFFSET
++#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT                                             0x8
++#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK                                               0xFFFFFF00L
++//DMCUB_REGION3_CW6_OFFSET_HIGH
++#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT                                   0x0
++#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK                                     0x0000FFFFL
++//DMCUB_REGION3_CW7_OFFSET
++#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT                                             0x8
++#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK                                               0xFFFFFF00L
++//DMCUB_REGION3_CW7_OFFSET_HIGH
++#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT                                   0x0
++#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK                                     0x0000FFFFL
++//DMCUB_INTERRUPT_ENABLE
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT                                                    0x0
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT                                                    0x1
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT                                              0x2
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT                                               0x3
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT                                              0x4
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT                                               0x5
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT                                             0x6
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT                                              0x7
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT                                             0x8
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT                                              0x9
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT                                                    0xa
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT                                                    0xb
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT                                                    0xc
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT                                   0xd
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK                                                      0x00000001L
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK                                                      0x00000002L
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK                                                0x00000004L
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK                                                 0x00000008L
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK                                                0x00000010L
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK                                                 0x00000020L
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK                                               0x00000040L
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK                                                0x00000080L
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK                                               0x00000100L
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK                                                0x00000200L
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK                                                      0x00000400L
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK                                                      0x00000800L
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK                                                      0x00001000L
++#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK                                     0x00002000L
++//DMCUB_INTERRUPT_ACK
++#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT                                                      0x0
++#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT                                                      0x1
++#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT                                                0x2
++#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT                                                 0x3
++#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT                                                0x4
++#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT                                                 0x5
++#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT                                               0x6
++#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT                                                0x7
++#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT                                               0x8
++#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT                                                0x9
++#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT                                                      0xa
++#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT                                                      0xb
++#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT                                                      0xc
++#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT                                         0xd
++#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK                                                        0x00000001L
++#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK                                                        0x00000002L
++#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK                                                  0x00000004L
++#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK                                                   0x00000008L
++#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK                                                  0x00000010L
++#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK                                                   0x00000020L
++#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK                                                 0x00000040L
++#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK                                                  0x00000080L
++#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK                                                 0x00000100L
++#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK                                                  0x00000200L
++#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK                                                        0x00000400L
++#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK                                                        0x00000800L
++#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK                                                        0x00001000L
++#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK                                           0x00002000L
++//DMCUB_INTERRUPT_STATUS
++#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT                                                  0x0
++#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT                                                  0x1
++#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT                                            0x2
++#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT                                             0x3
++#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT                                            0x4
++#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT                                             0x5
++#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT                                           0x6
++#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT                                            0x7
++#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT                                           0x8
++#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT                                            0x9
++#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT                                                  0xa
++#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT                                                  0xb
++#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT                                                  0xc
++#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT                                          0xd
++#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT                                                 0xe
++#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT                                                 0xf
++#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK                                                    0x00000001L
++#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK                                                    0x00000002L
++#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK                                              0x00000004L
++#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK                                               0x00000008L
++#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK                                              0x00000010L
++#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK                                               0x00000020L
++#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK                                             0x00000040L
++#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK                                              0x00000080L
++#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK                                             0x00000100L
++#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK                                              0x00000200L
++#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK                                                    0x00000400L
++#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK                                                    0x00000800L
++#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK                                                    0x00001000L
++#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK                                            0x00002000L
++#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK                                                   0x00004000L
++#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK                                                   0x00008000L
++//DMCUB_INTERRUPT_TYPE
++#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT                                                    0x0
++#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT                                                    0x1
++#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT                                              0x2
++#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT                                               0x3
++#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT                                              0x4
++#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT                                               0x5
++#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT                                             0x6
++#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT                                              0x7
++#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT                                             0x8
++#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT                                              0x9
++#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT                                                    0xa
++#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT                                                    0xb
++#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT                                                    0xc
++#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT                                   0xd
++#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK                                                      0x00000001L
++#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK                                                      0x00000002L
++#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK                                                0x00000004L
++#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK                                                 0x00000008L
++#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK                                                0x00000010L
++#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK                                                 0x00000020L
++#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK                                               0x00000040L
++#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK                                                0x00000080L
++#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK                                               0x00000100L
++#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK                                                0x00000200L
++#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK                                                      0x00000400L
++#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK                                                      0x00000800L
++#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK                                                      0x00001000L
++#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK                                     0x00002000L
++//DMCUB_EXT_INTERRUPT_STATUS
++#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT                                          0x0
++#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT                                             0x8
++#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK                                            0x000000FFL
++#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK                                               0x0000FF00L
++//DMCUB_EXT_INTERRUPT_CTXID
++#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT                                           0x0
++#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK                                             0x0FFFFFFFL
++//DMCUB_EXT_INTERRUPT_ACK
++#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT                                               0x0
++#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK                                                 0x00000001L
++//DMCUB_INST_FETCH_FAULT_ADDR
++#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT                                       0x0
++#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK                                         0xFFFFFFFFL
++//DMCUB_DATA_WRITE_FAULT_ADDR
++#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT                                       0x0
++#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK                                         0xFFFFFFFFL
++//DMCUB_SEC_CNTL
++#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL__SHIFT                                                              0x0
++#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT                                                              0x8
++#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT                                                                0x10
++#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT                                                   0x11
++#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT                                                        0x14
++#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT                                                         0x15
++#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT                                                   0x18
++#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT                                                   0x19
++#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL_MASK                                                                0x00000007L
++#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK                                                                0x00003F00L
++#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK                                                                  0x00010000L
++#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK                                                     0x00020000L
++#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK                                                          0x00100000L
++#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK                                                           0x00200000L
++#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK                                                     0x01000000L
++#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK                                                     0x02000000L
++//DMCUB_MEM_CNTL
++#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT                                                            0x0
++#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT                                                             0x4
++#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE__SHIFT                                                          0x8
++#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE__SHIFT                                                           0xc
++#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK                                                              0x0000000FL
++#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK                                                               0x000000F0L
++#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE_MASK                                                            0x00000700L
++#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE_MASK                                                             0x00007000L
++//DMCUB_INBOX0_BASE_ADDRESS
++#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT                                           0x0
++#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK                                             0xFFFFFFFFL
++//DMCUB_INBOX0_SIZE
++#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT                                                           0x0
++#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK                                                             0xFFFFFFFFL
++//DMCUB_INBOX0_WPTR
++#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT                                                           0x0
++#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK                                                             0xFFFFFFFFL
++//DMCUB_INBOX0_RPTR
++#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT                                                           0x0
++#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK                                                             0xFFFFFFFFL
++//DMCUB_INBOX1_BASE_ADDRESS
++#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT                                           0x0
++#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK                                             0xFFFFFFFFL
++//DMCUB_INBOX1_SIZE
++#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT                                                           0x0
++#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK                                                             0xFFFFFFFFL
++//DMCUB_INBOX1_WPTR
++#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT                                                           0x0
++#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK                                                             0xFFFFFFFFL
++//DMCUB_INBOX1_RPTR
++#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT                                                           0x0
++#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK                                                             0xFFFFFFFFL
++//DMCUB_OUTBOX0_BASE_ADDRESS
++#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT                                         0x0
++#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK                                           0xFFFFFFFFL
++//DMCUB_OUTBOX0_SIZE
++#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT                                                         0x0
++#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK                                                           0xFFFFFFFFL
++//DMCUB_OUTBOX0_WPTR
++#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT                                                         0x0
++#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK                                                           0xFFFFFFFFL
++//DMCUB_OUTBOX0_RPTR
++#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT                                                         0x0
++#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK                                                           0xFFFFFFFFL
++//DMCUB_OUTBOX1_BASE_ADDRESS
++#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT                                         0x0
++#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK                                           0xFFFFFFFFL
++//DMCUB_OUTBOX1_SIZE
++#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT                                                         0x0
++#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK                                                           0xFFFFFFFFL
++//DMCUB_OUTBOX1_WPTR
++#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT                                                         0x0
++#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK                                                           0xFFFFFFFFL
++//DMCUB_OUTBOX1_RPTR
++#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT                                                         0x0
++#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK                                                           0xFFFFFFFFL
++//DMCUB_TIMER_TRIGGER0
++#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT                                                     0x0
++#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK                                                       0xFFFFFFFFL
++//DMCUB_TIMER_TRIGGER1
++#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT                                                     0x0
++#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK                                                       0xFFFFFFFFL
++//DMCUB_TIMER_WINDOW
++#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT                                                         0x0
++#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK                                                           0x00000007L
++//DMCUB_SCRATCH0
++#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT                                                                 0x0
++#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK                                                                   0xFFFFFFFFL
++//DMCUB_SCRATCH1
++#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT                                                                 0x0
++#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK                                                                   0xFFFFFFFFL
++//DMCUB_SCRATCH2
++#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT                                                                 0x0
++#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK                                                                   0xFFFFFFFFL
++//DMCUB_SCRATCH3
++#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT                                                                 0x0
++#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK                                                                   0xFFFFFFFFL
++//DMCUB_SCRATCH4
++#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT                                                                 0x0
++#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK                                                                   0xFFFFFFFFL
++//DMCUB_SCRATCH5
++#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT                                                                 0x0
++#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK                                                                   0xFFFFFFFFL
++//DMCUB_SCRATCH6
++#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT                                                                 0x0
++#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK                                                                   0xFFFFFFFFL
++//DMCUB_SCRATCH7
++#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT                                                                 0x0
++#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK                                                                   0xFFFFFFFFL
++//DMCUB_SCRATCH8
++#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT                                                                 0x0
++#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK                                                                   0xFFFFFFFFL
++//DMCUB_SCRATCH9
++#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT                                                                 0x0
++#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK                                                                   0xFFFFFFFFL
++//DMCUB_SCRATCH10
++#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT                                                               0x0
++#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK                                                                 0xFFFFFFFFL
++//DMCUB_SCRATCH11
++#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT                                                               0x0
++#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK                                                                 0xFFFFFFFFL
++//DMCUB_SCRATCH12
++#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT                                                               0x0
++#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK                                                                 0xFFFFFFFFL
++//DMCUB_SCRATCH13
++#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT                                                               0x0
++#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK                                                                 0xFFFFFFFFL
++//DMCUB_SCRATCH14
++#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT                                                               0x0
++#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK                                                                 0xFFFFFFFFL
++//DMCUB_SCRATCH15
++#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT                                                               0x0
++#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK                                                                 0xFFFFFFFFL
++//DMCUB_CNTL
++#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT                                                                0x0
++#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT                                                          0x8
++#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT                                                                       0x10
++#define DMCUB_CNTL__DMCUB_SOFT_RESET__SHIFT                                                                   0x11
++#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT                                                      0x12
++#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT                                                                 0x13
++#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT                                                            0x14
++#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK                                                                  0x000000FFL
++#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK                                                            0x00000100L
++#define DMCUB_CNTL__DMCUB_ENABLE_MASK                                                                         0x00010000L
++#define DMCUB_CNTL__DMCUB_SOFT_RESET_MASK                                                                     0x00020000L
++#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK                                                        0x00040000L
++#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK                                                                   0x00080000L
++#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK                                                              0x00100000L
++//DMCUB_GPINT_DATAIN0
++#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT                                                       0x0
++#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK                                                         0xFFFFFFFFL
++//DMCUB_GPINT_DATAIN1
++#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT                                                       0x0
++#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK                                                         0xFFFFFFFFL
++//DMCUB_GPINT_DATAOUT
++#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT                                                       0x0
++#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK                                                         0xFFFFFFFFL
++//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR
++#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT                         0x0
++#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK                           0xFFFFFFFFL
++//DMCUB_LS_WAKE_INT_ENABLE
++#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT                                             0x0
++#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK                                               0xFFFFFFFFL
++//DMCUB_MEM_PWR_CNTL
++#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT                                                        0x1
++#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT                                                          0x3
++#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT                                                        0x4
++#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK                                                          0x00000006L
++#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK                                                            0x00000008L
++#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK                                                          0x00000030L
++//DMCUB_TIMER_CURRENT
++#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT                                                       0x0
++#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK                                                         0xFFFFFFFFL
++//DMCUB_PROC_ID
++#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT                                                                   0x0
++#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK                                                                     0x0000FFFFL
++
++
++// addressBlock: dce_dc_mmhubbub_mcif_wb2_dispdec
++//MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT                                      0x0
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT                                   0x1
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT                                   0x4
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT                                  0x5
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT                             0x6
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT                           0x7
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT                                     0x8
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT                                             0x10
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT                                  0x18
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK                                        0x00000001L
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK                                     0x00000002L
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK                                     0x00000010L
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK                                    0x00000020L
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK                               0x00000040L
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK                             0x00000080L
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK                                       0x00000F00L
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK                                               0x000F0000L
++#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK                                    0x01000000L
++//MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R
++#define MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT                                  0x0
++#define MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK                                    0x00001FFFL
++//MCIF_WB2_MCIF_WB_BUFMGR_STATUS
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT                                  0x0
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT                                   0x1
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT                           0x2
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT                                         0x4
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT                                    0x7
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT                                          0x8
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT                                      0xc
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT                                        0x1c
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK                                    0x00000001L
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK                                     0x00000002L
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK                             0x00000004L
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK                                           0x00000070L
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK                                      0x00000080L
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK                                            0x00000F00L
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK                                        0x01FFF000L
++#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK                                          0x70000000L
++//MCIF_WB2_MCIF_WB_BUF_PITCH
++#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT                                             0x8
++#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT                                           0x18
++#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK                                               0x0000FF00L
++#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK                                             0xFF000000L
++//MCIF_WB2_MCIF_WB_BUF_1_STATUS
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT                                            0x0
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT                                         0x1
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT                                        0x2
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT                                          0x3
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT                                           0x4
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT                                              0x5
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT                                            0x8
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT                                           0xc
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT                                             0xf
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT                                        0x10
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT                                   0x1d
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT                                  0x1e
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT                                0x1f
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK                                              0x00000001L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK                                           0x00000002L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK                                          0x00000004L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK                                            0x00000008L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK                                             0x00000010L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK                                                0x000000E0L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK                                              0x00000F00L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK                                             0x00007000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK                                               0x00008000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK                                          0x1FFF0000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK                                     0x20000000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK                                    0x40000000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
++//MCIF_WB2_MCIF_WB_BUF_1_STATUS2
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT                                       0x0
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT                                      0xd
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT                                      0xe
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT                                  0xf
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT                                              0x10
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT                                        0x11
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT                                        0x12
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT                                         0x13
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK                                         0x00001FFFL
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK                                        0x00002000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK                                        0x00004000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK                                                0x00010000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK                                          0x00020000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK                                          0x00040000L
++#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK                                           0x00080000L
++//MCIF_WB2_MCIF_WB_BUF_2_STATUS
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT                                            0x0
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT                                         0x1
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT                                        0x2
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT                                          0x3
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT                                           0x4
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT                                              0x5
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT                                            0x8
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT                                           0xc
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT                                             0xf
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT                                        0x10
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT                                   0x1d
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT                                  0x1e
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT                                0x1f
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK                                              0x00000001L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK                                           0x00000002L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK                                          0x00000004L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK                                            0x00000008L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK                                             0x00000010L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK                                                0x000000E0L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK                                              0x00000F00L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK                                             0x00007000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK                                               0x00008000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK                                          0x1FFF0000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK                                     0x20000000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK                                    0x40000000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
++//MCIF_WB2_MCIF_WB_BUF_2_STATUS2
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT                                       0x0
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT                                      0xd
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT                                      0xe
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT                                  0xf
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT                                              0x10
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT                                        0x11
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT                                        0x12
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT                                         0x13
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK                                         0x00001FFFL
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK                                        0x00002000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK                                        0x00004000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK                                                0x00010000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK                                          0x00020000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK                                          0x00040000L
++#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK                                           0x00080000L
++//MCIF_WB2_MCIF_WB_BUF_3_STATUS
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT                                            0x0
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT                                         0x1
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT                                        0x2
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT                                          0x3
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT                                           0x4
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT                                              0x5
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT                                            0x8
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT                                           0xc
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT                                             0xf
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT                                        0x10
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT                                   0x1d
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT                                  0x1e
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT                                0x1f
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK                                              0x00000001L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK                                           0x00000002L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK                                          0x00000004L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK                                            0x00000008L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK                                             0x00000010L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK                                                0x000000E0L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK                                              0x00000F00L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK                                             0x00007000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK                                               0x00008000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK                                          0x1FFF0000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK                                     0x20000000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK                                    0x40000000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
++//MCIF_WB2_MCIF_WB_BUF_3_STATUS2
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT                                       0x0
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT                                      0xd
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT                                      0xe
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT                                  0xf
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT                                              0x10
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT                                        0x11
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT                                        0x12
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT                                         0x13
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK                                         0x00001FFFL
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK                                        0x00002000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK                                        0x00004000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK                                                0x00010000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK                                          0x00020000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK                                          0x00040000L
++#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK                                           0x00080000L
++//MCIF_WB2_MCIF_WB_BUF_4_STATUS
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT                                            0x0
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT                                         0x1
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT                                        0x2
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT                                          0x3
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT                                           0x4
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT                                              0x5
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT                                            0x8
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT                                           0xc
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT                                             0xf
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT                                        0x10
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT                                   0x1d
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT                                  0x1e
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT                                0x1f
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK                                              0x00000001L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK                                           0x00000002L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK                                          0x00000004L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK                                            0x00000008L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK                                             0x00000010L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK                                                0x000000E0L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK                                              0x00000F00L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK                                             0x00007000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK                                               0x00008000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK                                          0x1FFF0000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK                                     0x20000000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK                                    0x40000000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
++//MCIF_WB2_MCIF_WB_BUF_4_STATUS2
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT                                       0x0
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT                                      0xd
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT                                      0xe
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT                                  0xf
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT                                              0x10
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT                                        0x11
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT                                        0x12
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT                                         0x13
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK                                         0x00001FFFL
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK                                        0x00002000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK                                        0x00004000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK                                                0x00010000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK                                          0x00020000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK                                          0x00040000L
++#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK                                           0x00080000L
++//MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL
++#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT                         0x0
++#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT                                   0x16
++#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK                           0x00000003L
++#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK                                     0xFFC00000L
++//MCIF_WB2_MCIF_WB_SCLK_CHANGE
++#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT                                           0x0
++#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT                                       0x1
++#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK                                             0x00000001L
++#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK                                         0x0000000EL
++//MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX
++#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT                                    0x0
++#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT                                 0x8
++#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK                                      0x000000FFL
++#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK                                   0x00000100L
++//MCIF_WB2_MCIF_WB_TEST_DEBUG_DATA
++#define MCIF_WB2_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT                                      0x0
++#define MCIF_WB2_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK                                        0xFFFFFFFFL
++//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT                                            0x0
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK                                              0xFFFFFFFFL
++//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT                              0x0
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT                                            0x0
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK                                              0xFFFFFFFFL
++//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT                              0x0
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT                                            0x0
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK                                              0xFFFFFFFFL
++//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT                              0x0
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT                                            0x0
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK                                              0xFFFFFFFFL
++//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT                              0x0
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT                                            0x0
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK                                              0xFFFFFFFFL
++//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT                              0x0
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT                                            0x0
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK                                              0xFFFFFFFFL
++//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT                              0x0
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT                                            0x0
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK                                              0xFFFFFFFFL
++//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT                              0x0
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT                                            0x0
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK                                              0xFFFFFFFFL
++//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT                              0x0
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK                                0x0003FFFFL
++//MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT                            0x0
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT                                 0x4
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT                                0x5
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT                           0x6
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT                                   0x8
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT                                 0x10
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK                              0x00000001L
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK                                   0x00000010L
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK                                  0x00000020L
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK                             0x00000040L
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK                                     0x00000F00L
++#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK                                   0x1FFF0000L
++//MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT               0x0
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK                 0x0007FFFFL
++//MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT                     0x0
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT                                  0x1
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT                                 0x2
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT                            0x4
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK                       0x00000001L
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK                                    0x00000002L
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK                                   0x00000004L
++#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK                              0x00000070L
++//MCIF_WB2_MCIF_WB_WATERMARK
++#define MCIF_WB2_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT                                              0x0
++#define MCIF_WB2_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK                                                0x0000FFFFL
++//MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL
++#define MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT                         0x0
++#define MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK                           0x00000001L
++//MCIF_WB2_MCIF_WB_WARM_UP_CNTL
++#define MCIF_WB2_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT                                       0x8
++#define MCIF_WB2_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK                                         0x0000FF00L
++//MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL
++#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT                                0x0
++#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT                                   0x1
++#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK                                  0x00000001L
++#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK                                     0x00000002L
++//MCIF_WB2_MULTI_LEVEL_QOS_CTRL
++#define MCIF_WB2_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT                                       0x0
++#define MCIF_WB2_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK                                         0x003FFFFFL
++//MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE
++#define MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT                                          0x0
++#define MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK                                            0x000FFFFFL
++//MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE
++#define MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT                                      0x0
++#define MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK                                        0x000FFFFFL
++//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT                                  0x0
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK                                    0x000000FFL
++//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT                                  0x0
++#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK                                    0x000000FFL
++//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT                                  0x0
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK                                    0x000000FFL
++//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT                                  0x0
++#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK                                    0x000000FFL
++//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT                                  0x0
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK                                    0x000000FFL
++//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT                                  0x0
++#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK                                    0x000000FFL
++//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT                                  0x0
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK                                    0x000000FFL
++//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT                                  0x0
++#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK                                    0x000000FFL
++//MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION
++#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT                              0x0
++#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT                             0x10
++#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK                                0x00001FFFL
++#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
++//MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION
++#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT                              0x0
++#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT                             0x10
++#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK                                0x00001FFFL
++#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
++//MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION
++#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT                              0x0
++#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT                             0x10
++#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK                                0x00001FFFL
++#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
++//MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION
++#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT                              0x0
++#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT                             0x10
++#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK                                0x00001FFFL
++#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
++
++
++// addressBlock: dce_dc_dchvm_hvm_dispdec
++//DCHVM_CTRL0
++#define DCHVM_CTRL0__HOSTVM_INIT_REQ__SHIFT                                                                   0x0
++#define DCHVM_CTRL0__HOSTVM_INIT_REQ_MASK                                                                     0x00000001L
++//DCHVM_CTRL1
++#define DCHVM_CTRL1__DUMMY1__SHIFT                                                                            0x0
++#define DCHVM_CTRL1__DUMMY1_MASK                                                                              0xFFFFFFFFL
++//DCHVM_CLK_CTRL
++#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS__SHIFT                                                         0x0
++#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS__SHIFT                                                         0x1
++#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS__SHIFT                                                          0x4
++#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS__SHIFT                                                          0x5
++#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE__SHIFT                                                          0x8
++#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE__SHIFT                                                         0xa
++#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS_MASK                                                           0x00000001L
++#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS_MASK                                                           0x00000002L
++#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS_MASK                                                            0x00000010L
++#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS_MASK                                                            0x00000020L
++#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE_MASK                                                            0x00000300L
++#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE_MASK                                                           0x00000C00L
++//DCHVM_MEM_CTRL
++#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS__SHIFT                                                       0x0
++#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ__SHIFT                                                         0x2
++#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS__SHIFT                                                      0x4
++#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS_MASK                                                         0x00000001L
++#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ_MASK                                                           0x0000000CL
++#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS_MASK                                                        0x00000030L
++//DCHVM_RIOMMU_CTRL0
++#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ__SHIFT                                                        0x0
++#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS__SHIFT                                                         0x1
++#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ_MASK                                                          0x00000001L
++#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS_MASK                                                           0x00000002L
++//DCHVM_RIOMMU_STAT0
++#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE__SHIFT                                                              0x0
++#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE__SHIFT                                                       0x1
++#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE_MASK                                                                0x00000001L
++#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE_MASK                                                         0x00000002L
++
++
++// addressBlock: vga_vgaseqind
++//SEQ00
++#define SEQ00__SEQ_RST0B__SHIFT                                                                               0x0
++#define SEQ00__SEQ_RST1B__SHIFT                                                                               0x1
++#define SEQ00__SEQ_RST0B_MASK                                                                                 0x01L
++#define SEQ00__SEQ_RST1B_MASK                                                                                 0x02L
++//SEQ01
++#define SEQ01__SEQ_DOT8__SHIFT                                                                                0x0
++#define SEQ01__SEQ_SHIFT2__SHIFT                                                                              0x2
++#define SEQ01__SEQ_PCLKBY2__SHIFT                                                                             0x3
++#define SEQ01__SEQ_SHIFT4__SHIFT                                                                              0x4
++#define SEQ01__SEQ_MAXBW__SHIFT                                                                               0x5
++#define SEQ01__SEQ_DOT8_MASK                                                                                  0x01L
++#define SEQ01__SEQ_SHIFT2_MASK                                                                                0x04L
++#define SEQ01__SEQ_PCLKBY2_MASK                                                                               0x08L
++#define SEQ01__SEQ_SHIFT4_MASK                                                                                0x10L
++#define SEQ01__SEQ_MAXBW_MASK                                                                                 0x20L
++//SEQ02
++#define SEQ02__SEQ_MAP0_EN__SHIFT                                                                             0x0
++#define SEQ02__SEQ_MAP1_EN__SHIFT                                                                             0x1
++#define SEQ02__SEQ_MAP2_EN__SHIFT                                                                             0x2
++#define SEQ02__SEQ_MAP3_EN__SHIFT                                                                             0x3
++#define SEQ02__SEQ_MAP0_EN_MASK                                                                               0x01L
++#define SEQ02__SEQ_MAP1_EN_MASK                                                                               0x02L
++#define SEQ02__SEQ_MAP2_EN_MASK                                                                               0x04L
++#define SEQ02__SEQ_MAP3_EN_MASK                                                                               0x08L
++//SEQ03
++#define SEQ03__SEQ_FONT_B1__SHIFT                                                                             0x0
++#define SEQ03__SEQ_FONT_B2__SHIFT                                                                             0x1
++#define SEQ03__SEQ_FONT_A1__SHIFT                                                                             0x2
++#define SEQ03__SEQ_FONT_A2__SHIFT                                                                             0x3
++#define SEQ03__SEQ_FONT_B0__SHIFT                                                                             0x4
++#define SEQ03__SEQ_FONT_A0__SHIFT                                                                             0x5
++#define SEQ03__SEQ_FONT_B1_MASK                                                                               0x01L
++#define SEQ03__SEQ_FONT_B2_MASK                                                                               0x02L
++#define SEQ03__SEQ_FONT_A1_MASK                                                                               0x04L
++#define SEQ03__SEQ_FONT_A2_MASK                                                                               0x08L
++#define SEQ03__SEQ_FONT_B0_MASK                                                                               0x10L
++#define SEQ03__SEQ_FONT_A0_MASK                                                                               0x20L
++//SEQ04
++#define SEQ04__SEQ_256K__SHIFT                                                                                0x1
++#define SEQ04__SEQ_ODDEVEN__SHIFT                                                                             0x2
++#define SEQ04__SEQ_CHAIN__SHIFT                                                                               0x3
++#define SEQ04__SEQ_256K_MASK                                                                                  0x02L
++#define SEQ04__SEQ_ODDEVEN_MASK                                                                               0x04L
++#define SEQ04__SEQ_CHAIN_MASK                                                                                 0x08L
++
++
++// addressBlock: vga_vgacrtind
++//CRT00
++#define CRT00__H_TOTAL__SHIFT                                                                                 0x0
++#define CRT00__H_TOTAL_MASK                                                                                   0xFFL
++//CRT01
++#define CRT01__H_DISP_END__SHIFT                                                                              0x0
++#define CRT01__H_DISP_END_MASK                                                                                0xFFL
++//CRT02
++#define CRT02__H_BLANK_START__SHIFT                                                                           0x0
++#define CRT02__H_BLANK_START_MASK                                                                             0xFFL
++//CRT03
++#define CRT03__H_BLANK_END__SHIFT                                                                             0x0
++#define CRT03__H_DE_SKEW__SHIFT                                                                               0x5
++#define CRT03__CR10CR11_R_DIS_B__SHIFT                                                                        0x7
++#define CRT03__H_BLANK_END_MASK                                                                               0x1FL
++#define CRT03__H_DE_SKEW_MASK                                                                                 0x60L
++#define CRT03__CR10CR11_R_DIS_B_MASK                                                                          0x80L
++//CRT04
++#define CRT04__H_SYNC_START__SHIFT                                                                            0x0
++#define CRT04__H_SYNC_START_MASK                                                                              0xFFL
++//CRT05
++#define CRT05__H_SYNC_END__SHIFT                                                                              0x0
++#define CRT05__H_SYNC_SKEW__SHIFT                                                                             0x5
++#define CRT05__H_BLANK_END_B5__SHIFT                                                                          0x7
++#define CRT05__H_SYNC_END_MASK                                                                                0x1FL
++#define CRT05__H_SYNC_SKEW_MASK                                                                               0x60L
++#define CRT05__H_BLANK_END_B5_MASK                                                                            0x80L
++//CRT06
++#define CRT06__V_TOTAL__SHIFT                                                                                 0x0
++#define CRT06__V_TOTAL_MASK                                                                                   0xFFL
++//CRT07
++#define CRT07__V_TOTAL_B8__SHIFT                                                                              0x0
++#define CRT07__V_DISP_END_B8__SHIFT                                                                           0x1
++#define CRT07__V_SYNC_START_B8__SHIFT                                                                         0x2
++#define CRT07__V_BLANK_START_B8__SHIFT                                                                        0x3
++#define CRT07__LINE_CMP_B8__SHIFT                                                                             0x4
++#define CRT07__V_TOTAL_B9__SHIFT                                                                              0x5
++#define CRT07__V_DISP_END_B9__SHIFT                                                                           0x6
++#define CRT07__V_SYNC_START_B9__SHIFT                                                                         0x7
++#define CRT07__V_TOTAL_B8_MASK                                                                                0x01L
++#define CRT07__V_DISP_END_B8_MASK                                                                             0x02L
++#define CRT07__V_SYNC_START_B8_MASK                                                                           0x04L
++#define CRT07__V_BLANK_START_B8_MASK                                                                          0x08L
++#define CRT07__LINE_CMP_B8_MASK                                                                               0x10L
++#define CRT07__V_TOTAL_B9_MASK                                                                                0x20L
++#define CRT07__V_DISP_END_B9_MASK                                                                             0x40L
++#define CRT07__V_SYNC_START_B9_MASK                                                                           0x80L
++//CRT08
++#define CRT08__ROW_SCAN_START__SHIFT                                                                          0x0
++#define CRT08__BYTE_PAN__SHIFT                                                                                0x5
++#define CRT08__ROW_SCAN_START_MASK                                                                            0x1FL
++#define CRT08__BYTE_PAN_MASK                                                                                  0x60L
++//CRT09
++#define CRT09__MAX_ROW_SCAN__SHIFT                                                                            0x0
++#define CRT09__V_BLANK_START_B9__SHIFT                                                                        0x5
++#define CRT09__LINE_CMP_B9__SHIFT                                                                             0x6
++#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT                                                                      0x7
++#define CRT09__MAX_ROW_SCAN_MASK                                                                              0x1FL
++#define CRT09__V_BLANK_START_B9_MASK                                                                          0x20L
++#define CRT09__LINE_CMP_B9_MASK                                                                               0x40L
++#define CRT09__DOUBLE_CHAR_HEIGHT_MASK                                                                        0x80L
++//CRT0A
++#define CRT0A__CURSOR_START__SHIFT                                                                            0x0
++#define CRT0A__CURSOR_DISABLE__SHIFT                                                                          0x5
++#define CRT0A__CURSOR_START_MASK                                                                              0x1FL
++#define CRT0A__CURSOR_DISABLE_MASK                                                                            0x20L
++//CRT0B
++#define CRT0B__CURSOR_END__SHIFT                                                                              0x0
++#define CRT0B__CURSOR_SKEW__SHIFT                                                                             0x5
++#define CRT0B__CURSOR_END_MASK                                                                                0x1FL
++#define CRT0B__CURSOR_SKEW_MASK                                                                               0x60L
++//CRT0C
++#define CRT0C__DISP_START__SHIFT                                                                              0x0
++#define CRT0C__DISP_START_MASK                                                                                0xFFL
++//CRT0D
++#define CRT0D__DISP_START__SHIFT                                                                              0x0
++#define CRT0D__DISP_START_MASK                                                                                0xFFL
++//CRT0E
++#define CRT0E__CURSOR_LOC_HI__SHIFT                                                                           0x0
++#define CRT0E__CURSOR_LOC_HI_MASK                                                                             0xFFL
++//CRT0F
++#define CRT0F__CURSOR_LOC_LO__SHIFT                                                                           0x0
++#define CRT0F__CURSOR_LOC_LO_MASK                                                                             0xFFL
++//CRT10
++#define CRT10__V_SYNC_START__SHIFT                                                                            0x0
++#define CRT10__V_SYNC_START_MASK                                                                              0xFFL
++//CRT11
++#define CRT11__V_SYNC_END__SHIFT                                                                              0x0
++#define CRT11__V_INTR_CLR__SHIFT                                                                              0x4
++#define CRT11__V_INTR_EN__SHIFT                                                                               0x5
++#define CRT11__SEL5_REFRESH_CYC__SHIFT                                                                        0x6
++#define CRT11__C0T7_WR_ONLY__SHIFT                                                                            0x7
++#define CRT11__V_SYNC_END_MASK                                                                                0x0FL
++#define CRT11__V_INTR_CLR_MASK                                                                                0x10L
++#define CRT11__V_INTR_EN_MASK                                                                                 0x20L
++#define CRT11__SEL5_REFRESH_CYC_MASK                                                                          0x40L
++#define CRT11__C0T7_WR_ONLY_MASK                                                                              0x80L
++//CRT12
++#define CRT12__V_DISP_END__SHIFT                                                                              0x0
++#define CRT12__V_DISP_END_MASK                                                                                0xFFL
++//CRT13
++#define CRT13__DISP_PITCH__SHIFT                                                                              0x0
++#define CRT13__DISP_PITCH_MASK                                                                                0xFFL
++//CRT14
++#define CRT14__UNDRLN_LOC__SHIFT                                                                              0x0
++#define CRT14__ADDR_CNT_BY4__SHIFT                                                                            0x5
++#define CRT14__DOUBLE_WORD__SHIFT                                                                             0x6
++#define CRT14__UNDRLN_LOC_MASK                                                                                0x1FL
++#define CRT14__ADDR_CNT_BY4_MASK                                                                              0x20L
++#define CRT14__DOUBLE_WORD_MASK                                                                               0x40L
++//CRT15
++#define CRT15__V_BLANK_START__SHIFT                                                                           0x0
++#define CRT15__V_BLANK_START_MASK                                                                             0xFFL
++//CRT16
++#define CRT16__V_BLANK_END__SHIFT                                                                             0x0
++#define CRT16__V_BLANK_END_MASK                                                                               0xFFL
++//CRT17
++#define CRT17__RA0_AS_A13B__SHIFT                                                                             0x0
++#define CRT17__RA1_AS_A14B__SHIFT                                                                             0x1
++#define CRT17__VCOUNT_BY2__SHIFT                                                                              0x2
++#define CRT17__ADDR_CNT_BY2__SHIFT                                                                            0x3
++#define CRT17__WRAP_A15TOA0__SHIFT                                                                            0x5
++#define CRT17__BYTE_MODE__SHIFT                                                                               0x6
++#define CRT17__CRTC_SYNC_EN__SHIFT                                                                            0x7
++#define CRT17__RA0_AS_A13B_MASK                                                                               0x01L
++#define CRT17__RA1_AS_A14B_MASK                                                                               0x02L
++#define CRT17__VCOUNT_BY2_MASK                                                                                0x04L
++#define CRT17__ADDR_CNT_BY2_MASK                                                                              0x08L
++#define CRT17__WRAP_A15TOA0_MASK                                                                              0x20L
++#define CRT17__BYTE_MODE_MASK                                                                                 0x40L
++#define CRT17__CRTC_SYNC_EN_MASK                                                                              0x80L
++//CRT18
++#define CRT18__LINE_CMP__SHIFT                                                                                0x0
++#define CRT18__LINE_CMP_MASK                                                                                  0xFFL
++//CRT1E
++#define CRT1E__GRPH_DEC_RD1__SHIFT                                                                            0x1
++#define CRT1E__GRPH_DEC_RD1_MASK                                                                              0x02L
++//CRT1F
++#define CRT1F__GRPH_DEC_RD0__SHIFT                                                                            0x0
++#define CRT1F__GRPH_DEC_RD0_MASK                                                                              0xFFL
++//CRT22
++#define CRT22__GRPH_LATCH_DATA__SHIFT                                                                         0x0
++#define CRT22__GRPH_LATCH_DATA_MASK                                                                           0xFFL
++
++
++// addressBlock: vga_vgagrphind
++//GRA00
++#define GRA00__GRPH_SET_RESET0__SHIFT                                                                         0x0
++#define GRA00__GRPH_SET_RESET1__SHIFT                                                                         0x1
++#define GRA00__GRPH_SET_RESET2__SHIFT                                                                         0x2
++#define GRA00__GRPH_SET_RESET3__SHIFT                                                                         0x3
++#define GRA00__GRPH_SET_RESET0_MASK                                                                           0x01L
++#define GRA00__GRPH_SET_RESET1_MASK                                                                           0x02L
++#define GRA00__GRPH_SET_RESET2_MASK                                                                           0x04L
++#define GRA00__GRPH_SET_RESET3_MASK                                                                           0x08L
++//GRA01
++#define GRA01__GRPH_SET_RESET_ENA0__SHIFT                                                                     0x0
++#define GRA01__GRPH_SET_RESET_ENA1__SHIFT                                                                     0x1
++#define GRA01__GRPH_SET_RESET_ENA2__SHIFT                                                                     0x2
++#define GRA01__GRPH_SET_RESET_ENA3__SHIFT                                                                     0x3
++#define GRA01__GRPH_SET_RESET_ENA0_MASK                                                                       0x01L
++#define GRA01__GRPH_SET_RESET_ENA1_MASK                                                                       0x02L
++#define GRA01__GRPH_SET_RESET_ENA2_MASK                                                                       0x04L
++#define GRA01__GRPH_SET_RESET_ENA3_MASK                                                                       0x08L
++//GRA02
++#define GRA02__GRPH_CCOMP__SHIFT                                                                              0x0
++#define GRA02__GRPH_CCOMP_MASK                                                                                0x0FL
++//GRA03
++#define GRA03__GRPH_ROTATE__SHIFT                                                                             0x0
++#define GRA03__GRPH_FN_SEL__SHIFT                                                                             0x3
++#define GRA03__GRPH_ROTATE_MASK                                                                               0x07L
++#define GRA03__GRPH_FN_SEL_MASK                                                                               0x18L
++//GRA04
++#define GRA04__GRPH_RMAP__SHIFT                                                                               0x0
++#define GRA04__GRPH_RMAP_MASK                                                                                 0x03L
++//GRA05
++#define GRA05__GRPH_WRITE_MODE__SHIFT                                                                         0x0
++#define GRA05__GRPH_READ1__SHIFT                                                                              0x3
++#define GRA05__CGA_ODDEVEN__SHIFT                                                                             0x4
++#define GRA05__GRPH_OES__SHIFT                                                                                0x5
++#define GRA05__GRPH_PACK__SHIFT                                                                               0x6
++#define GRA05__GRPH_WRITE_MODE_MASK                                                                           0x03L
++#define GRA05__GRPH_READ1_MASK                                                                                0x08L
++#define GRA05__CGA_ODDEVEN_MASK                                                                               0x10L
++#define GRA05__GRPH_OES_MASK                                                                                  0x20L
++#define GRA05__GRPH_PACK_MASK                                                                                 0x40L
++//GRA06
++#define GRA06__GRPH_GRAPHICS__SHIFT                                                                           0x0
++#define GRA06__GRPH_ODDEVEN__SHIFT                                                                            0x1
++#define GRA06__GRPH_ADRSEL__SHIFT                                                                             0x2
++#define GRA06__GRPH_GRAPHICS_MASK                                                                             0x01L
++#define GRA06__GRPH_ODDEVEN_MASK                                                                              0x02L
++#define GRA06__GRPH_ADRSEL_MASK                                                                               0x0CL
++//GRA07
++#define GRA07__GRPH_XCARE0__SHIFT                                                                             0x0
++#define GRA07__GRPH_XCARE1__SHIFT                                                                             0x1
++#define GRA07__GRPH_XCARE2__SHIFT                                                                             0x2
++#define GRA07__GRPH_XCARE3__SHIFT                                                                             0x3
++#define GRA07__GRPH_XCARE0_MASK                                                                               0x01L
++#define GRA07__GRPH_XCARE1_MASK                                                                               0x02L
++#define GRA07__GRPH_XCARE2_MASK                                                                               0x04L
++#define GRA07__GRPH_XCARE3_MASK                                                                               0x08L
++//GRA08
++#define GRA08__GRPH_BMSK__SHIFT                                                                               0x0
++#define GRA08__GRPH_BMSK_MASK                                                                                 0xFFL
++
++
++// addressBlock: vga_vgaattrind
++//ATTR00
++#define ATTR00__ATTR_PAL__SHIFT                                                                               0x0
++#define ATTR00__ATTR_PAL_MASK                                                                                 0x3FL
++//ATTR01
++#define ATTR01__ATTR_PAL__SHIFT                                                                               0x0
++#define ATTR01__ATTR_PAL_MASK                                                                                 0x3FL
++//ATTR02
++#define ATTR02__ATTR_PAL__SHIFT                                                                               0x0
++#define ATTR02__ATTR_PAL_MASK                                                                                 0x3FL
++//ATTR03
++#define ATTR03__ATTR_PAL__SHIFT                                                                               0x0
++#define ATTR03__ATTR_PAL_MASK                                                                                 0x3FL
++//ATTR04
++#define ATTR04__ATTR_PAL__SHIFT                                                                               0x0
++#define ATTR04__ATTR_PAL_MASK                                                                                 0x3FL
++//ATTR05
++#define ATTR05__ATTR_PAL__SHIFT                                                                               0x0
++#define ATTR05__ATTR_PAL_MASK                                                                                 0x3FL
++//ATTR06
++#define ATTR06__ATTR_PAL__SHIFT                                                                               0x0
++#define ATTR06__ATTR_PAL_MASK                                                                                 0x3FL
++//ATTR07
++#define ATTR07__ATTR_PAL__SHIFT                                                                               0x0
++#define ATTR07__ATTR_PAL_MASK                                                                                 0x3FL
++//ATTR08
++#define ATTR08__ATTR_PAL__SHIFT                                                                               0x0
++#define ATTR08__ATTR_PAL_MASK                                                                                 0x3FL
++//ATTR09
++#define ATTR09__ATTR_PAL__SHIFT                                                                               0x0
++#define ATTR09__ATTR_PAL_MASK                                                                                 0x3FL
++//ATTR0A
++#define ATTR0A__ATTR_PAL__SHIFT                                                                               0x0
++#define ATTR0A__ATTR_PAL_MASK                                                                                 0x3FL
++//ATTR0B
++#define ATTR0B__ATTR_PAL__SHIFT                                                                               0x0
++#define ATTR0B__ATTR_PAL_MASK                                                                                 0x3FL
++//ATTR0C
++#define ATTR0C__ATTR_PAL__SHIFT                                                                               0x0
++#define ATTR0C__ATTR_PAL_MASK                                                                                 0x3FL
++//ATTR0D
++#define ATTR0D__ATTR_PAL__SHIFT                                                                               0x0
++#define ATTR0D__ATTR_PAL_MASK                                                                                 0x3FL
++//ATTR0E
++#define ATTR0E__ATTR_PAL__SHIFT                                                                               0x0
++#define ATTR0E__ATTR_PAL_MASK                                                                                 0x3FL
++//ATTR0F
++#define ATTR0F__ATTR_PAL__SHIFT                                                                               0x0
++#define ATTR0F__ATTR_PAL_MASK                                                                                 0x3FL
++//ATTR10
++#define ATTR10__ATTR_GRPH_MODE__SHIFT                                                                         0x0
++#define ATTR10__ATTR_MONO_EN__SHIFT                                                                           0x1
++#define ATTR10__ATTR_LGRPH_EN__SHIFT                                                                          0x2
++#define ATTR10__ATTR_BLINK_EN__SHIFT                                                                          0x3
++#define ATTR10__ATTR_PANTOPONLY__SHIFT                                                                        0x5
++#define ATTR10__ATTR_PCLKBY2__SHIFT                                                                           0x6
++#define ATTR10__ATTR_CSEL_EN__SHIFT                                                                           0x7
++#define ATTR10__ATTR_GRPH_MODE_MASK                                                                           0x01L
++#define ATTR10__ATTR_MONO_EN_MASK                                                                             0x02L
++#define ATTR10__ATTR_LGRPH_EN_MASK                                                                            0x04L
++#define ATTR10__ATTR_BLINK_EN_MASK                                                                            0x08L
++#define ATTR10__ATTR_PANTOPONLY_MASK                                                                          0x20L
++#define ATTR10__ATTR_PCLKBY2_MASK                                                                             0x40L
++#define ATTR10__ATTR_CSEL_EN_MASK                                                                             0x80L
++//ATTR11
++#define ATTR11__ATTR_OVSC__SHIFT                                                                              0x0
++#define ATTR11__ATTR_OVSC_MASK                                                                                0xFFL
++//ATTR12
++#define ATTR12__ATTR_MAP_EN__SHIFT                                                                            0x0
++#define ATTR12__ATTR_VSMUX__SHIFT                                                                             0x4
++#define ATTR12__ATTR_MAP_EN_MASK                                                                              0x0FL
++#define ATTR12__ATTR_VSMUX_MASK                                                                               0x30L
++//ATTR13
++#define ATTR13__ATTR_PPAN__SHIFT                                                                              0x0
++#define ATTR13__ATTR_PPAN_MASK                                                                                0x0FL
++//ATTR14
++#define ATTR14__ATTR_CSEL1__SHIFT                                                                             0x0
++#define ATTR14__ATTR_CSEL2__SHIFT                                                                             0x2
++#define ATTR14__ATTR_CSEL1_MASK                                                                               0x03L
++#define ATTR14__ATTR_CSEL2_MASK                                                                               0x0CL
++
++
++// addressBlock: azendpoint_f2codecind
++//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                         0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                            0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                        0x8
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                       0xb
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                           0xe
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                                0xf
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT                              0xf
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                           0x0000000FL
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                              0x00000070L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                          0x00000700L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                         0x00003800L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                             0x00004000L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                                  0x00008000L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK                                0x00008000L
++//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                                0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                                 0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                                  0x0000000FL
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                                   0x000000F0L
++//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                                     0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                         0x1
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                      0x2
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                       0x3
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                      0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                                 0x5
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                       0x6
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                         0x7
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                        0x8
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                                 0x17
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                       0x00000001L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                           0x00000002L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                        0x00000004L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                         0x00000008L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                        0x00000010L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                                   0x00000020L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                         0x00000040L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                           0x00000080L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                          0x00007F00L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                                   0x00800000L
++//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT                                      0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK                                        0x0000007FL
++//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                                       0x0
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                                    0x14
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                                         0x00000003L
++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                                      0x00700000L
++//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT                               0x7
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK                                 0x00000080L
++//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                                         0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                                           0x000000FFL
++//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT            0x0
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT              0x1
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT             0x4
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK              0x00000001L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK                0x00000002L
++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK               0x00000070L
++//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT                 0x4
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK                   0x00000010L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L
++//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT              0x0
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT               0x10
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                0x00000FFFL
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                 0x001F0000L
++//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                             0x0
++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                               0xFFFFFFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT              0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK                0xFFFFFFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL
++#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                                         0x6
++#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                                           0x00000040L
++//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                          0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                       0x7
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                            0x0000003FL
++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                         0x00000080L
++//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                                0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                                0x1f
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                                  0x7FFFFFFFL
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                                  0x80000000L
++//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                           0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT                0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                               0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                              0xc
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT                    0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT                     0x14
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                           0x18
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT                  0x1e
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                             0x0000000FL
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK                  0x000000F0L
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                                 0x00000F00L
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                                0x0000F000L
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                      0x000F0000L
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                       0x00F00000L
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                             0x3F000000L
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK                    0xC0000000L
++//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                             0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                            0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                               0x0000000FL
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                              0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT                  0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT                   0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK                    0x0000000FL
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK                     0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                         0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT                0x6
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                           0x0000003FL
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK                  0x000000C0L
++//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT                    0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT                       0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT                         0x9
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT                 0xa
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK                      0x0000007FL
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK                         0x00000100L
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK                           0x00000200L
++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK                   0x0000FC00L
++//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                             0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                               0x000000FFL
++//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT                                  0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT                                         0x3
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT                                    0x7
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK                                    0x00000003L
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK                                           0x00000078L
++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK                                      0x00000080L
++//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT                                     0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT                                      0x3
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT                            0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT                                0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT                     0x18
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK                                       0x00000007L
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK                                        0x00000078L
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK                              0x0000FF00L
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK                                  0x00FF0000L
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK                       0xFF000000L
++//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT                                  0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK                                    0xFFFFFFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT                       0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT                         0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT                   0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK                         0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK                           0x00000002L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK                     0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT                       0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT                         0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT                   0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK                         0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK                           0x00000002L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK                     0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT                       0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT                         0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT                   0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK                         0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK                           0x00000002L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK                     0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT                       0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT                         0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT                   0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK                         0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK                           0x00000002L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK                     0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT                                             0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT                                             0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK                                               0x000000FFL
++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK                                               0x0000FF00L
++//AZALIA_F2_CODEC_PIN_CONTROL_HBR
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                                   0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                                    0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                                     0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                      0x00000010L
++//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT                             0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK                               0x000000FFL
++//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT                                    0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK                                      0xFFFFFFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                         0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                           0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT                     0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                           0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                             0x00000002L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                       0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                         0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                           0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT                     0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                           0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                             0x00000002L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                       0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                         0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                           0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT                     0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                           0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                             0x00000002L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                       0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                         0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                           0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT                     0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                           0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                             0x00000002L
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                       0x000000F0L
++//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                               0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                                 0x00000001L
++//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                                   0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT                          0x2
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                                     0x00000003L
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK                            0x0000003CL
++//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT                         0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT                0x2
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT                            0x3
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT                   0x7
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK                           0x00000003L
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK                  0x00000004L
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                              0x00000078L
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK                     0x00000080L
++//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT                     0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT            0x6
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK                       0x0000003FL
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK              0x00000040L
++//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT            0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT   0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK              0x0000000FL
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK     0x00000010L
++//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT               0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT                     0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                                 0x5
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT                           0x7
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK                 0x0000000FL
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK                       0x00000010L
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                                   0x00000060L
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK                             0x00000080L
++//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT                       0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT                       0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK                         0x0000000FL
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK                         0x000000F0L
++//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT                       0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT                       0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK                         0x0000000FL
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK                         0x000000F0L
++//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT                       0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT                       0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK                         0x0000000FL
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK                         0x000000F0L
++//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT                       0x0
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT                       0x4
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK                         0x0000000FL
++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK                         0x000000F0L
++//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO
++#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                                         0x0
++#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                                           0xFFFFFFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
++#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                               0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                                 0x00000001L
++//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                          0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT                    0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                            0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                      0x0000FF00L
++//AZALIA_F2_CODEC_PIN_CONTROL_LPIB
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                                         0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                                           0xFFFFFFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                           0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                             0xFFFFFFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE
++#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                                           0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                                             0x000000FFL
++//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                                     0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT                       0x1
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                               0x8
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT                             0x10
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                                       0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK                         0x00000002L
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                                 0x0000FF00L
++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                               0x00FF0000L
++//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
++#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT   0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK     0x00000003L
++//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT                         0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT                     0x4
++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK                           0x00000001L
++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK                       0x00000010L
++//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT            0x0
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT               0x1
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT              0x2
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT          0x3
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                                0x5
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT                     0x6
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT       0x7
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                       0x8
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                               0x9
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                         0xa
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                               0xb
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT       0x10
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                                  0x14
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK              0x00000001L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK                 0x00000002L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK                0x00000004L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK            0x00000008L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                                  0x00000020L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                       0x00000040L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK         0x00000080L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                         0x00000100L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                                 0x00000200L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                           0x00000400L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                                 0x00000800L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK         0x000F0000L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                                    0x00F00000L
++//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                            0x0
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                                   0x1
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                          0x2
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                            0x3
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                                     0x4
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                      0x5
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                                  0x6
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                               0x7
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                       0x8
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                       0x10
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                                 0x18
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                              0x00000001L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                                     0x00000002L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                            0x00000004L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                              0x00000008L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                       0x00000010L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                        0x00000020L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                                    0x00000040L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                                 0x00000080L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                         0x0000FF00L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                         0x00010000L
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                                   0x01000000L
++//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT                   0x0
++#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK                     0xFFFFFFFFL
++
++
++// addressBlock: azendpoint_descriptorind
++//AUDIO_DESCRIPTOR0
++#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                                                                0x0
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
++#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
++#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                                                                  0x00000007L
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
++#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
++//AUDIO_DESCRIPTOR1
++#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                                                                0x0
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
++#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
++#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                                                                  0x00000007L
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
++#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
++//AUDIO_DESCRIPTOR2
++#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                                                                0x0
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
++#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
++#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                                                                  0x00000007L
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
++#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
++//AUDIO_DESCRIPTOR3
++#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                                                                0x0
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
++#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
++#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                                                                  0x00000007L
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
++#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
++//AUDIO_DESCRIPTOR4
++#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                                                                0x0
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
++#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
++#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                                                                  0x00000007L
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
++#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
++//AUDIO_DESCRIPTOR5
++#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                                                                0x0
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
++#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
++#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                                                                  0x00000007L
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
++#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
++//AUDIO_DESCRIPTOR6
++#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                                                                0x0
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
++#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
++#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                                                                  0x00000007L
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
++#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
++//AUDIO_DESCRIPTOR7
++#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                                                                0x0
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
++#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
++#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                                                                  0x00000007L
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
++#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
++//AUDIO_DESCRIPTOR8
++#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                                                                0x0
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
++#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
++#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                                                                  0x00000007L
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
++#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
++//AUDIO_DESCRIPTOR9
++#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                                                                0x0
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
++#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
++#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                                                                  0x00000007L
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
++#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
++//AUDIO_DESCRIPTOR10
++#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                                                               0x0
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
++#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
++#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                                                                 0x00000007L
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
++#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
++//AUDIO_DESCRIPTOR11
++#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                                                               0x0
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
++#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
++#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                                                                 0x00000007L
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
++#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
++//AUDIO_DESCRIPTOR12
++#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                                                               0x0
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
++#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
++#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                                                                 0x00000007L
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
++#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
++//AUDIO_DESCRIPTOR13
++#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                                                               0x0
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
++#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
++#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                                                                 0x00000007L
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
++#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
++
++
++// addressBlock: azendpoint_sinkinfoind
++//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID
++#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT                                   0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK                                     0x0000FFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID
++#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT                                             0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK                                               0x0000FFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN
++#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT                         0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK                           0x000000FFL
++//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT                                                    0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK                                                      0xFFFFFFFFL
++//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT                                                    0x0
++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK                                                      0xFFFFFFFFL
++//SINK_DESCRIPTION0
++#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT                                                                 0x0
++#define SINK_DESCRIPTION0__DESCRIPTION_MASK                                                                   0x000000FFL
++//SINK_DESCRIPTION1
++#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT                                                                 0x0
++#define SINK_DESCRIPTION1__DESCRIPTION_MASK                                                                   0x000000FFL
++//SINK_DESCRIPTION2
++#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT                                                                 0x0
++#define SINK_DESCRIPTION2__DESCRIPTION_MASK                                                                   0x000000FFL
++//SINK_DESCRIPTION3
++#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT                                                                 0x0
++#define SINK_DESCRIPTION3__DESCRIPTION_MASK                                                                   0x000000FFL
++//SINK_DESCRIPTION4
++#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT                                                                 0x0
++#define SINK_DESCRIPTION4__DESCRIPTION_MASK                                                                   0x000000FFL
++//SINK_DESCRIPTION5
++#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT                                                                 0x0
++#define SINK_DESCRIPTION5__DESCRIPTION_MASK                                                                   0x000000FFL
++//SINK_DESCRIPTION6
++#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT                                                                 0x0
++#define SINK_DESCRIPTION6__DESCRIPTION_MASK                                                                   0x000000FFL
++//SINK_DESCRIPTION7
++#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT                                                                 0x0
++#define SINK_DESCRIPTION7__DESCRIPTION_MASK                                                                   0x000000FFL
++//SINK_DESCRIPTION8
++#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT                                                                 0x0
++#define SINK_DESCRIPTION8__DESCRIPTION_MASK                                                                   0x000000FFL
++//SINK_DESCRIPTION9
++#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT                                                                 0x0
++#define SINK_DESCRIPTION9__DESCRIPTION_MASK                                                                   0x000000FFL
++//SINK_DESCRIPTION10
++#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT                                                                0x0
++#define SINK_DESCRIPTION10__DESCRIPTION_MASK                                                                  0x000000FFL
++//SINK_DESCRIPTION11
++#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT                                                                0x0
++#define SINK_DESCRIPTION11__DESCRIPTION_MASK                                                                  0x000000FFL
++//SINK_DESCRIPTION12
++#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT                                                                0x0
++#define SINK_DESCRIPTION12__DESCRIPTION_MASK                                                                  0x000000FFL
++//SINK_DESCRIPTION13
++#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT                                                                0x0
++#define SINK_DESCRIPTION13__DESCRIPTION_MASK                                                                  0x000000FFL
++//SINK_DESCRIPTION14
++#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT                                                                0x0
++#define SINK_DESCRIPTION14__DESCRIPTION_MASK                                                                  0x000000FFL
++//SINK_DESCRIPTION15
++#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT                                                                0x0
++#define SINK_DESCRIPTION15__DESCRIPTION_MASK                                                                  0x000000FFL
++//SINK_DESCRIPTION16
++#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT                                                                0x0
++#define SINK_DESCRIPTION16__DESCRIPTION_MASK                                                                  0x000000FFL
++//SINK_DESCRIPTION17
++#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT                                                                0x0
++#define SINK_DESCRIPTION17__DESCRIPTION_MASK                                                                  0x000000FFL
++
++
++// addressBlock: azf0controller_azinputcrc0resultind
++//AZALIA_INPUT_CRC0_CHANNEL0
++#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL
++//AZALIA_INPUT_CRC0_CHANNEL1
++#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL
++//AZALIA_INPUT_CRC0_CHANNEL2
++#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL
++//AZALIA_INPUT_CRC0_CHANNEL3
++#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL
++//AZALIA_INPUT_CRC0_CHANNEL4
++#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL
++//AZALIA_INPUT_CRC0_CHANNEL5
++#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL
++//AZALIA_INPUT_CRC0_CHANNEL6
++#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL
++//AZALIA_INPUT_CRC0_CHANNEL7
++#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0
++#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL
++
++
++// addressBlock: azf0controller_azinputcrc1resultind
++//AZALIA_INPUT_CRC1_CHANNEL0
++#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL
++//AZALIA_INPUT_CRC1_CHANNEL1
++#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL
++//AZALIA_INPUT_CRC1_CHANNEL2
++#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL
++//AZALIA_INPUT_CRC1_CHANNEL3
++#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL
++//AZALIA_INPUT_CRC1_CHANNEL4
++#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL
++//AZALIA_INPUT_CRC1_CHANNEL5
++#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL
++//AZALIA_INPUT_CRC1_CHANNEL6
++#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL
++//AZALIA_INPUT_CRC1_CHANNEL7
++#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0
++#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL
++
++
++// addressBlock: azf0controller_azcrc0resultind
++//AZALIA_CRC0_CHANNEL0
++#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0
++#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL
++//AZALIA_CRC0_CHANNEL1
++#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0
++#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL
++//AZALIA_CRC0_CHANNEL2
++#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0
++#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL
++//AZALIA_CRC0_CHANNEL3
++#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0
++#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL
++//AZALIA_CRC0_CHANNEL4
++#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0
++#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL
++//AZALIA_CRC0_CHANNEL5
++#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0
++#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL
++//AZALIA_CRC0_CHANNEL6
++#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0
++#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL
++//AZALIA_CRC0_CHANNEL7
++#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0
++#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL
++
++
++// addressBlock: azf0controller_azcrc1resultind
++//AZALIA_CRC1_CHANNEL0
++#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0
++#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL
++//AZALIA_CRC1_CHANNEL1
++#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0
++#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL
++//AZALIA_CRC1_CHANNEL2
++#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0
++#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL
++//AZALIA_CRC1_CHANNEL3
++#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0
++#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL
++//AZALIA_CRC1_CHANNEL4
++#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0
++#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL
++//AZALIA_CRC1_CHANNEL5
++#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0
++#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL
++//AZALIA_CRC1_CHANNEL6
++#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0
++#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL
++//AZALIA_CRC1_CHANNEL7
++#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0
++#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL
++
++
++// addressBlock: azinputendpoint_f2codecind
++//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                   0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                      0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                  0x8
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                 0xb
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                     0xe
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                          0xf
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                     0x0000000FL
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                        0x00000070L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                    0x00000700L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                   0x00003800L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                       0x00004000L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                            0x00008000L
++//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                          0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                           0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                            0x0000000FL
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                             0x000000F0L
++//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                               0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                   0x1
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                0x2
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                 0x3
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                           0x5
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                 0x6
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                   0x7
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                  0x8
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                           0x17
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                 0x00000001L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                     0x00000002L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                  0x00000004L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                   0x00000008L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                  0x00000010L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                             0x00000020L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                   0x00000040L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                     0x00000080L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                    0x00007F00L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                             0x00800000L
++//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT   0x1
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT           0x4
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                    0x5
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT         0x6
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT           0x8
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                   0x9
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT             0xa
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                   0xb
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                      0x14
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK     0x00000002L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK    0x00000004L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK             0x00000010L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                      0x00000020L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK           0x00000040L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK             0x00000100L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                     0x00000200L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK               0x00000400L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                     0x00000800L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                        0x00F00000L
++//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT        0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT         0x10
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK          0x00000FFFL
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK           0x001F0000L
++//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                       0x0
++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                         0xFFFFFFFFL
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                                    0x5
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                                      0x00000020L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                    0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                 0x7
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                      0x0000003FL
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                   0x00000080L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                          0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                          0x1f
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                            0x7FFFFFFFL
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                            0x80000000L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                     0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT          0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                         0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                        0xc
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT              0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT               0x14
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                     0x18
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT            0x1e
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                       0x0000000FL
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK            0x000000F0L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                           0x00000F00L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                          0x0000F000L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                0x000F0000L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                 0x00F00000L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                       0x3F000000L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK              0xC0000000L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                       0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                      0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                         0x0000000FL
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                        0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT            0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT             0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK              0x0000000FL
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK               0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                   0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT          0x6
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                     0x0000003FL
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK            0x000000C0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                       0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                         0x000000FFL
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT                   0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT                     0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT               0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK                     0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK                       0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK                 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT                   0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT                     0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT               0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK                     0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK                       0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK                 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT                   0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT                     0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT               0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK                     0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK                       0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK                 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT                   0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT                     0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT               0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK                     0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK                       0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK                 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                             0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                              0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                               0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                0x00000010L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                   0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                     0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT               0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                     0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                       0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                   0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                     0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT               0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                     0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                       0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                   0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                     0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT               0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                     0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                       0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                   0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                     0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT               0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                     0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                       0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                 0x000000F0L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                    0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT              0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                      0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                0x0000FF00L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                                   0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                                     0xFFFFFFFFL
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                     0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                       0xFFFFFFFFL
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT                         0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT                         0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT               0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK                           0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK                           0x00000006L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK                 0x00000010L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK   0x00000020L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                                     0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT                                0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT                                  0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                                   0x1f
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                                       0x00000007L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK                                  0x0000FF00L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                                    0x00FF0000L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                                     0x80000000L
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT                           0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK                             0xFFFFFFFFL
++//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT                           0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK                             0xFFFFFFFFL
++//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L
++//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                      0x0
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                             0x1
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                    0x2
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                      0x3
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                               0x4
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                0x5
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                            0x6
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                         0x7
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                 0x8
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                 0x10
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                           0x18
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                        0x00000001L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                               0x00000002L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                      0x00000004L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                        0x00000008L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                 0x00000010L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                  0x00000020L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                              0x00000040L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                           0x00000080L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                   0x0000FF00L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                   0x00010000L
++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                                             0x01000000L
++
++
++// addressBlock: azroot_f2codecind
++//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL
++//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL
++//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0
++#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL
++//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L
++//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L
++//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT                   0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK                     0x000000FFL
++//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT                   0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK                     0x000000FFL
++//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT                   0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK                     0x000000FFL
++//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL
++//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0
++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L
++//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL
++//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL
++//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L
++//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL
++//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L
++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L
++
++
++// addressBlock: azf0stream0_streamind
++//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
++#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
++#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
++#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
++#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
++#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
++//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
++#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
++//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
++#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
++//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
++#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
++//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
++#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
++
++
++// addressBlock: azf0stream1_streamind
++//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
++#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
++#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
++#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
++#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
++#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
++//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
++#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
++//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
++#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
++//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
++#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
++//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
++#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
++
++
++// addressBlock: azf0stream2_streamind
++//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
++#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
++#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
++#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
++#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
++#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
++//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
++#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
++//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
++#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
++//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
++#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
++//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
++#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
++
++
++// addressBlock: azf0stream3_streamind
++//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
++#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
++#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
++#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
++#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
++#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
++//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
++#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
++//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
++#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
++//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
++#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
++//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
++#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
++
++
++// addressBlock: azf0stream4_streamind
++//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
++#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
++#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
++#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
++#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
++#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
++//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
++#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
++//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
++#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
++//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
++#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
++//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
++#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
++
++
++// addressBlock: azf0stream5_streamind
++//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
++#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
++#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
++#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
++#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
++#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
++//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
++#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
++//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
++#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
++//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
++#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
++//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
++#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
++
++
++// addressBlock: azf0stream6_streamind
++//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
++#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
++#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
++#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
++#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
++#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
++//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
++#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
++//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
++#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
++//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
++#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
++//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
++#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
++
++
++// addressBlock: azf0stream7_streamind
++//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
++#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
++#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
++#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
++#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
++#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
++//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
++#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
++//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
++#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
++//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
++#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
++//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
++#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
++
++
++// addressBlock: azf0stream8_streamind
++//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
++#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
++#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
++#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
++#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
++#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
++//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
++#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
++//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
++#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
++//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
++#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
++//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
++#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
++
++
++// addressBlock: azf0stream9_streamind
++//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
++#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
++#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
++#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
++#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
++#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
++//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
++#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
++//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
++#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
++//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
++#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
++//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
++#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
++
++
++// addressBlock: azf0stream10_streamind
++//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
++#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
++#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
++#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
++#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
++#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
++//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
++#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
++//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
++#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
++//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
++#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
++//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
++#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
++
++
++// addressBlock: azf0stream11_streamind
++//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
++#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
++#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
++#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
++#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
++#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
++//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
++#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
++//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
++#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
++//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
++#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
++//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
++#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
++
++
++// addressBlock: azf0stream12_streamind
++//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
++#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
++#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
++#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
++#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
++#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
++//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
++#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
++//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
++#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
++//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
++#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
++//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
++#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
++
++
++// addressBlock: azf0stream13_streamind
++//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
++#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
++#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
++#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
++#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
++#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
++//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
++#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
++//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
++#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
++//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
++#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
++//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
++#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
++
++
++// addressBlock: azf0stream14_streamind
++//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
++#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
++#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
++#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
++#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
++#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
++//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
++#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
++//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
++#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
++//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
++#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
++//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
++#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
++
++
++// addressBlock: azf0stream15_streamind
++//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL
++#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
++#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
++#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
++#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
++#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
++#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
++//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL
++#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
++#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
++//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT
++#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
++#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
++//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT
++#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
++#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
++//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT
++#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
++#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
++
++
++// addressBlock: azf0endpoint0_endpointind
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
++//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
++//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
++//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
++//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
++//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
++//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
++//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
++//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
++//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
++#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
++//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
++//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
++//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
++//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
++//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
++#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
++
++
++// addressBlock: azf0endpoint1_endpointind
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
++//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
++//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
++//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
++//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
++//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
++//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
++//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
++//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
++//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
++#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
++//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
++//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
++//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
++//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
++//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
++#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
++
++
++// addressBlock: azf0endpoint2_endpointind
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
++//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
++//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
++//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
++//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
++//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
++//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
++//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
++//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
++//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
++#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
++//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
++//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
++//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
++//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
++//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
++#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
++
++
++// addressBlock: azf0endpoint3_endpointind
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
++//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
++//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
++//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
++//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
++//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
++//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
++//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
++//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
++//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
++#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
++//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
++//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
++//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
++//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
++//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
++#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
++
++
++// addressBlock: azf0endpoint4_endpointind
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
++//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
++//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
++//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
++//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
++//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
++//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
++//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
++//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
++//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
++#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
++//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
++//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
++//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
++//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
++//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
++#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
++
++
++// addressBlock: azf0endpoint5_endpointind
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
++//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
++//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
++//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
++//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
++//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
++//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
++//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
++//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
++//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
++#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
++//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
++//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
++//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
++//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
++//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
++#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
++
++
++// addressBlock: azf0endpoint6_endpointind
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
++//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
++//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
++//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
++//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
++//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
++//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
++//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
++//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
++//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
++#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
++//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
++//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
++//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
++//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
++//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
++#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
++
++
++// addressBlock: azf0endpoint7_endpointind
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
++//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
++//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
++//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
++//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
++//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
++//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
++//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
++//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
++//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
++#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
++//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
++//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
++//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
++//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
++//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
++#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
++
++
++// addressBlock: azf0inputendpoint0_inputendpointind
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
++//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
++#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
++
++
++// addressBlock: azf0inputendpoint1_inputendpointind
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
++//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
++#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
++
++
++// addressBlock: azf0inputendpoint2_inputendpointind
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
++//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
++#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
++
++
++// addressBlock: azf0inputendpoint3_inputendpointind
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
++//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
++#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
++
++
++// addressBlock: azf0inputendpoint4_inputendpointind
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
++//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
++#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
++
++
++// addressBlock: azf0inputendpoint5_inputendpointind
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
++//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
++#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
++
++
++// addressBlock: azf0inputendpoint6_inputendpointind
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
++//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
++#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
++
++
++// addressBlock: azf0inputendpoint7_inputendpointind
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
++//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
++#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
++
++
++#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_offset.h
+new file mode 100644
+index 000000000000..945bb6101a9d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_offset.h
+@@ -0,0 +1,565 @@
++/*
++ * Copyright (C) 2019  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _dpcs_2_1_0_OFFSET_HEADER
++#define _dpcs_2_1_0_OFFSET_HEADER
++
++
++
++// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
++// base address: 0x0
++#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL                                                                 0x2928
++#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
++#define mmDPCSTX0_DPCSTX_TX_CNTL                                                                       0x2929
++#define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX                                                              2
++#define mmDPCSTX0_DPCSTX_CBUS_CNTL                                                                     0x292a
++#define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
++#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL                                                                0x292b
++#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
++#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR                                                               0x292c
++#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
++#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA                                                               0x292d
++#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
++#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG                                                                  0x292e
++#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
++
++
++// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
++// base address: 0x0
++#define mmRDPCSTX0_RDPCSTX_CNTL                                                                        0x2930
++#define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX                                                               2
++#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL                                                                  0x2931
++#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
++#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL                                                           0x2932
++#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
++#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA                                                             0x2933
++#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
++#define mmRDPCSTX0_RDPCS_TX_CR_ADDR                                                                    0x2934
++#define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
++#define mmRDPCSTX0_RDPCS_TX_CR_DATA                                                                    0x2935
++#define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
++#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL                                                                  0x2936
++#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
++#define mmRDPCSTX0_RDPCSTX_SCRATCH                                                                     0x2937
++#define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX                                                            2
++#define mmRDPCSTX0_RDPCSTX_SPARE                                                                       0x2938
++#define mmRDPCSTX0_RDPCSTX_SPARE_BASE_IDX                                                              2
++#define mmRDPCSTX0_RDPCSTX_CNTL2                                                                       0x2939
++#define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX                                                              2
++#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x293c
++#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
++#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG                                                                0x293d
++#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0                                                                   0x2940
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1                                                                   0x2941
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2                                                                   0x2942
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3                                                                   0x2943
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4                                                                   0x2944
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5                                                                   0x2945
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6                                                                   0x2946
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7                                                                   0x2947
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8                                                                   0x2948
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9                                                                   0x2949
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10                                                                  0x294a
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11                                                                  0x294b
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12                                                                  0x294c
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13                                                                  0x294d
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14                                                                  0x294e
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
++#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0                                                                   0x294f
++#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
++#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1                                                                   0x2950
++#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
++#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2                                                                   0x2951
++#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
++#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3                                                                   0x2952
++#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
++#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL                                                               0x2953
++#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
++#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2954
++#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
++#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2955
++#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
++#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG                                                           0x2956
++#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL15                                                                  0x2958
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL16                                                                  0x2959
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL17                                                                  0x295a
++#define mmRDPCSTX0_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
++#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG2                                                               0x295b
++#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
++
++
++// addressBlock: dpcssys_dpcssys_cr0_dispdec
++// base address: 0x0
++#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR                                                                  0x2934
++#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
++#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA                                                                  0x2935
++#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX                                                         2
++
++
++// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec
++// base address: 0x360
++#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL                                                                 0x2a00
++#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
++#define mmDPCSTX1_DPCSTX_TX_CNTL                                                                       0x2a01
++#define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX                                                              2
++#define mmDPCSTX1_DPCSTX_CBUS_CNTL                                                                     0x2a02
++#define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
++#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL                                                                0x2a03
++#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
++#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR                                                               0x2a04
++#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
++#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA                                                               0x2a05
++#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
++#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG                                                                  0x2a06
++#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
++
++
++// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
++// base address: 0x360
++#define mmRDPCSTX1_RDPCSTX_CNTL                                                                        0x2a08
++#define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX                                                               2
++#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL                                                                  0x2a09
++#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
++#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL                                                           0x2a0a
++#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
++#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA                                                             0x2a0b
++#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
++#define mmRDPCSTX1_RDPCS_TX_CR_ADDR                                                                    0x2a0c
++#define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
++#define mmRDPCSTX1_RDPCS_TX_CR_DATA                                                                    0x2a0d
++#define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
++#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL                                                                  0x2a0e
++#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
++#define mmRDPCSTX1_RDPCSTX_SCRATCH                                                                     0x2a0f
++#define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX                                                            2
++#define mmRDPCSTX1_RDPCSTX_SPARE                                                                       0x2a10
++#define mmRDPCSTX1_RDPCSTX_SPARE_BASE_IDX                                                              2
++#define mmRDPCSTX1_RDPCSTX_CNTL2                                                                       0x2a11
++#define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX                                                              2
++#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2a14
++#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
++#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG                                                                0x2a15
++#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0                                                                   0x2a18
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1                                                                   0x2a19
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2                                                                   0x2a1a
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3                                                                   0x2a1b
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4                                                                   0x2a1c
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5                                                                   0x2a1d
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6                                                                   0x2a1e
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7                                                                   0x2a1f
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8                                                                   0x2a20
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9                                                                   0x2a21
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10                                                                  0x2a22
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11                                                                  0x2a23
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12                                                                  0x2a24
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13                                                                  0x2a25
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14                                                                  0x2a26
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
++#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0                                                                   0x2a27
++#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
++#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1                                                                   0x2a28
++#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
++#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2                                                                   0x2a29
++#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
++#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3                                                                   0x2a2a
++#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
++#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL                                                               0x2a2b
++#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
++#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2a2c
++#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
++#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2a2d
++#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
++#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG                                                           0x2a2e
++#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL15                                                                  0x2a30
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL16                                                                  0x2a31
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL17                                                                  0x2a32
++#define mmRDPCSTX1_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
++#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG2                                                               0x2a33
++#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
++
++
++// addressBlock: dpcssys_dpcssys_cr1_dispdec
++// base address: 0x360
++#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR                                                                  0x2a0c
++#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
++#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA                                                                  0x2a0d
++#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX                                                         2
++
++
++// addressBlock: dpcssys_dpcs0_dpcstx2_dispdec
++// base address: 0x6c0
++#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL                                                                 0x2ad8
++#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
++#define mmDPCSTX2_DPCSTX_TX_CNTL                                                                       0x2ad9
++#define mmDPCSTX2_DPCSTX_TX_CNTL_BASE_IDX                                                              2
++#define mmDPCSTX2_DPCSTX_CBUS_CNTL                                                                     0x2ada
++#define mmDPCSTX2_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
++#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL                                                                0x2adb
++#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
++#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR                                                               0x2adc
++#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
++#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA                                                               0x2add
++#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
++#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG                                                                  0x2ade
++#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
++
++
++// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
++// base address: 0x6c0
++#define mmRDPCSTX2_RDPCSTX_CNTL                                                                        0x2ae0
++#define mmRDPCSTX2_RDPCSTX_CNTL_BASE_IDX                                                               2
++#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL                                                                  0x2ae1
++#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
++#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL                                                           0x2ae2
++#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
++#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA                                                             0x2ae3
++#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
++#define mmRDPCSTX2_RDPCS_TX_CR_ADDR                                                                    0x2ae4
++#define mmRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
++#define mmRDPCSTX2_RDPCS_TX_CR_DATA                                                                    0x2ae5
++#define mmRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
++#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL                                                                  0x2ae6
++#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
++#define mmRDPCSTX2_RDPCSTX_SCRATCH                                                                     0x2ae7
++#define mmRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX                                                            2
++#define mmRDPCSTX2_RDPCSTX_SPARE                                                                       0x2ae8
++#define mmRDPCSTX2_RDPCSTX_SPARE_BASE_IDX                                                              2
++#define mmRDPCSTX2_RDPCSTX_CNTL2                                                                       0x2ae9
++#define mmRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX                                                              2
++#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2aec
++#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
++#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG                                                                0x2aed
++#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0                                                                   0x2af0
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1                                                                   0x2af1
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2                                                                   0x2af2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3                                                                   0x2af3
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4                                                                   0x2af4
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5                                                                   0x2af5
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6                                                                   0x2af6
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7                                                                   0x2af7
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8                                                                   0x2af8
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9                                                                   0x2af9
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10                                                                  0x2afa
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11                                                                  0x2afb
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12                                                                  0x2afc
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13                                                                  0x2afd
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14                                                                  0x2afe
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
++#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0                                                                   0x2aff
++#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
++#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1                                                                   0x2b00
++#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
++#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2                                                                   0x2b01
++#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
++#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3                                                                   0x2b02
++#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
++#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL                                                               0x2b03
++#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
++#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2b04
++#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
++#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2b05
++#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
++#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG                                                           0x2b06
++#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL15                                                                  0x2b08
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL16                                                                  0x2b09
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL17                                                                  0x2b0a
++#define mmRDPCSTX2_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
++#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG2                                                               0x2b0b
++#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
++
++
++// addressBlock: dpcssys_dpcssys_cr2_dispdec
++// base address: 0x6c0
++#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR                                                                  0x2ae4
++#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
++#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA                                                                  0x2ae5
++#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX                                                         2
++
++
++// addressBlock: dpcssys_dpcs0_dpcstx3_dispdec
++// base address: 0xa20
++#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL                                                                 0x2bb0
++#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
++#define mmDPCSTX3_DPCSTX_TX_CNTL                                                                       0x2bb1
++#define mmDPCSTX3_DPCSTX_TX_CNTL_BASE_IDX                                                              2
++#define mmDPCSTX3_DPCSTX_CBUS_CNTL                                                                     0x2bb2
++#define mmDPCSTX3_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
++#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL                                                                0x2bb3
++#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
++#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR                                                               0x2bb4
++#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
++#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA                                                               0x2bb5
++#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
++#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG                                                                  0x2bb6
++#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
++
++
++// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
++// base address: 0xa20
++#define mmRDPCSTX3_RDPCSTX_CNTL                                                                        0x2bb8
++#define mmRDPCSTX3_RDPCSTX_CNTL_BASE_IDX                                                               2
++#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL                                                                  0x2bb9
++#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
++#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL                                                           0x2bba
++#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
++#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA                                                             0x2bbb
++#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
++#define mmRDPCSTX3_RDPCS_TX_CR_ADDR                                                                    0x2bbc
++#define mmRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
++#define mmRDPCSTX3_RDPCS_TX_CR_DATA                                                                    0x2bbd
++#define mmRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
++#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL                                                                  0x2bbe
++#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
++#define mmRDPCSTX3_RDPCSTX_SCRATCH                                                                     0x2bbf
++#define mmRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX                                                            2
++#define mmRDPCSTX3_RDPCSTX_SPARE                                                                       0x2bc0
++#define mmRDPCSTX3_RDPCSTX_SPARE_BASE_IDX                                                              2
++#define mmRDPCSTX3_RDPCSTX_CNTL2                                                                       0x2bc1
++#define mmRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX                                                              2
++#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2bc4
++#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
++#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG                                                                0x2bc5
++#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0                                                                   0x2bc8
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1                                                                   0x2bc9
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2                                                                   0x2bca
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3                                                                   0x2bcb
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4                                                                   0x2bcc
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5                                                                   0x2bcd
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6                                                                   0x2bce
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7                                                                   0x2bcf
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8                                                                   0x2bd0
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9                                                                   0x2bd1
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10                                                                  0x2bd2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11                                                                  0x2bd3
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12                                                                  0x2bd4
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13                                                                  0x2bd5
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14                                                                  0x2bd6
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
++#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0                                                                   0x2bd7
++#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
++#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1                                                                   0x2bd8
++#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
++#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2                                                                   0x2bd9
++#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
++#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3                                                                   0x2bda
++#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
++#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL                                                               0x2bdb
++#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
++#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2bdc
++#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
++#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2bdd
++#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
++#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG                                                           0x2bde
++#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL15                                                                  0x2be0
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL16                                                                  0x2be1
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL17                                                                  0x2be2
++#define mmRDPCSTX3_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
++#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG2                                                               0x2be3
++#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
++
++
++// addressBlock: dpcssys_dpcssys_cr3_dispdec
++// base address: 0xa20
++#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR                                                                  0x2bbc
++#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
++#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA                                                                  0x2bbd
++#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX                                                         2
++
++
++// addressBlock: dpcssys_dpcs0_dpcstx4_dispdec
++// base address: 0xd80
++#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL                                                                 0x2c88
++#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
++#define mmDPCSTX4_DPCSTX_TX_CNTL                                                                       0x2c89
++#define mmDPCSTX4_DPCSTX_TX_CNTL_BASE_IDX                                                              2
++#define mmDPCSTX4_DPCSTX_CBUS_CNTL                                                                     0x2c8a
++#define mmDPCSTX4_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
++#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL                                                                0x2c8b
++#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
++#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR                                                               0x2c8c
++#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
++#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA                                                               0x2c8d
++#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
++#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG                                                                  0x2c8e
++#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
++
++
++// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
++// base address: 0xd80
++#define mmRDPCSTX4_RDPCSTX_CNTL                                                                        0x2c90
++#define mmRDPCSTX4_RDPCSTX_CNTL_BASE_IDX                                                               2
++#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL                                                                  0x2c91
++#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
++#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL                                                           0x2c92
++#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
++#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA                                                             0x2c93
++#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
++#define mmRDPCSTX4_RDPCS_TX_CR_ADDR                                                                    0x2c94
++#define mmRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
++#define mmRDPCSTX4_RDPCS_TX_CR_DATA                                                                    0x2c95
++#define mmRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
++#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL                                                                  0x2c96
++#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
++#define mmRDPCSTX4_RDPCSTX_SCRATCH                                                                     0x2c97
++#define mmRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX                                                            2
++#define mmRDPCSTX4_RDPCSTX_SPARE                                                                       0x2c98
++#define mmRDPCSTX4_RDPCSTX_SPARE_BASE_IDX                                                              2
++#define mmRDPCSTX4_RDPCSTX_CNTL2                                                                       0x2c99
++#define mmRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX                                                              2
++#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2c9c
++#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
++#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG                                                                0x2c9d
++#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0                                                                   0x2ca0
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1                                                                   0x2ca1
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2                                                                   0x2ca2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3                                                                   0x2ca3
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4                                                                   0x2ca4
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5                                                                   0x2ca5
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6                                                                   0x2ca6
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7                                                                   0x2ca7
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8                                                                   0x2ca8
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9                                                                   0x2ca9
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10                                                                  0x2caa
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11                                                                  0x2cab
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12                                                                  0x2cac
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13                                                                  0x2cad
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14                                                                  0x2cae
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
++#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0                                                                   0x2caf
++#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
++#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1                                                                   0x2cb0
++#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
++#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2                                                                   0x2cb1
++#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
++#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3                                                                   0x2cb2
++#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
++#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL                                                               0x2cb3
++#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
++#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2cb4
++#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
++#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2cb5
++#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
++#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG                                                           0x2cb6
++#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL15                                                                  0x2cb8
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL16                                                                  0x2cb9
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL17                                                                  0x2cba
++#define mmRDPCSTX4_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
++#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG2                                                               0x2cbb
++#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
++
++
++// addressBlock: dpcssys_dpcssys_cr4_dispdec
++// base address: 0xd80
++#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR                                                                  0x2c94
++#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
++#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA                                                                  0x2c95
++#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX                                                         2
++
++#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_sh_mask.h
+new file mode 100644
+index 000000000000..6e039f2208e1
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_sh_mask.h
+@@ -0,0 +1,3430 @@
++/*
++ * Copyright (C) 2019  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _dpcs_2_1_0_SH_MASK_HEADER
++#define _dpcs_2_1_0_SH_MASK_HEADER
++
++
++// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
++//DPCSTX0_DPCSTX_TX_CLOCK_CNTL
++#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT                                             0x0
++#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT                                                   0x1
++#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT                                             0x2
++#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0x3
++#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK                                               0x00000001L
++#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK                                                     0x00000002L
++#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK                                               0x00000004L
++#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000008L
++//DPCSTX0_DPCSTX_TX_CNTL
++#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0xc
++#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xd
++#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT                                                      0xe
++#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT                                              0xf
++#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT                                                        0x10
++#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT                                                     0x11
++#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
++#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
++#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00001000L
++#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00002000L
++#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK                                                        0x00004000L
++#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK                                                0x00008000L
++#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK                                                          0x00010000L
++#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK                                                       0x00020000L
++#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x00F00000L
++#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
++//DPCSTX0_DPCSTX_CBUS_CNTL
++#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT                                               0x0
++#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT                                                 0x1f
++#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK                                                 0x000000FFL
++#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK                                                   0x80000000L
++//DPCSTX0_DPCSTX_INTERRUPT_CNTL
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT                                          0x0
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT                                              0x1
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT                                        0x4
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT                                             0x8
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT                                             0x9
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT                                             0xa
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT                                             0xb
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT                                               0xc
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT                                         0x10
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT                                             0x14
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK                                            0x00000001L
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK                                                0x00000002L
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK                                          0x00000010L
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK                                               0x00000100L
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK                                               0x00000200L
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK                                               0x00000400L
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK                                               0x00000800L
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK                                                 0x00001000L
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK                                           0x00010000L
++#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK                                               0x00100000L
++//DPCSTX0_DPCSTX_PLL_UPDATE_ADDR
++#define DPCSTX0_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT                                           0x0
++#define DPCSTX0_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK                                             0x0003FFFFL
++//DPCSTX0_DPCSTX_PLL_UPDATE_DATA
++#define DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT                                           0x0
++#define DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK                                             0xFFFFFFFFL
++//DPCSTX0_DPCSTX_DEBUG_CONFIG
++#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT                                                       0x0
++#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT                                               0x1
++#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT                                            0x4
++#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT                                       0x8
++#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT                                                 0xe
++#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT                                          0x10
++#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT                                             0x18
++#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK                                                         0x00000001L
++#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK                                                 0x0000000EL
++#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK                                              0x00000070L
++#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK                                         0x00000700L
++#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK                                                   0x00004000L
++#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK                                            0x00010000L
++#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK                                               0xFF000000L
++
++
++
++// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
++//RDPCSTX0_RDPCSTX_CNTL
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x4
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x10
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x11
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1a
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000010L
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x00010000L
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x00020000L
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x04000000L
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
++#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
++//RDPCSTX0_RDPCSTX_CLOCK_CNTL
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT                                          0x4
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT                                          0x5
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT                                          0x6
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT                                          0x7
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT                                        0x8
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT                                              0x9
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0xa
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK                                            0x00000010L
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK                                            0x00000020L
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK                                            0x00000040L
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK                                            0x00000080L
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK                                          0x00000100L
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK                                                0x00000200L
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000400L
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
++#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
++//RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
++#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
++//RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA
++#define RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                        0x0
++#define RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                          0x00000001L
++//RDPCSTX0_RDPCS_TX_CR_ADDR
++#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
++#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
++//RDPCSTX0_RDPCS_TX_CR_DATA
++#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
++#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
++//RDPCSTX0_RDPCS_TX_SRAM_CNTL
++#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
++#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
++#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
++#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
++#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
++#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
++//RDPCSTX0_RDPCSTX_SCRATCH
++#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
++#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
++//RDPCSTX0_RDPCSTX_SPARE
++#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
++#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
++//RDPCSTX0_RDPCSTX_CNTL2
++#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
++#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
++#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
++#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
++//RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT              0x4
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK                0x00000010L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
++//RDPCSTX0_RDPCSTX_DEBUG_CONFIG
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT                                                    0x0
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT                                        0x4
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT                                        0x7
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT                                          0x8
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT                                       0xf
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT                                          0x10
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT                                              0x18
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK                                                      0x00000001L
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK                                          0x00000070L
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK                                          0x00000080L
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK                                            0x00001F00L
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK                                         0x00008000L
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK                                            0x00FF0000L
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK                                                0xFF000000L
++//RDPCSTX0_RDPCSTX_PHY_CNTL0
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
++//RDPCSTX0_RDPCSTX_PHY_CNTL1
++#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
++#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
++#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
++#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
++#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
++#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
++#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
++#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
++#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
++//RDPCSTX0_RDPCSTX_PHY_CNTL2
++#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
++#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
++#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
++#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
++#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
++#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
++#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
++#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
++#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
++#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
++//RDPCSTX0_RDPCSTX_PHY_CNTL3
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
++//RDPCSTX0_RDPCSTX_PHY_CNTL4
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
++//RDPCSTX0_RDPCSTX_PHY_CNTL5
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
++//RDPCSTX0_RDPCSTX_PHY_CNTL6
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
++//RDPCSTX0_RDPCSTX_PHY_CNTL7
++#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
++#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
++#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
++#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
++//RDPCSTX0_RDPCSTX_PHY_CNTL8
++#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
++#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
++//RDPCSTX0_RDPCSTX_PHY_CNTL9
++#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
++#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
++#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
++#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
++//RDPCSTX0_RDPCSTX_PHY_CNTL10
++#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
++#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
++//RDPCSTX0_RDPCSTX_PHY_CNTL11
++#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
++#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
++#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
++#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
++#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
++//RDPCSTX0_RDPCSTX_PHY_CNTL12
++#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
++#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
++#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
++#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
++#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
++#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
++//RDPCSTX0_RDPCSTX_PHY_CNTL13
++#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
++#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
++#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
++#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
++#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
++//RDPCSTX0_RDPCSTX_PHY_CNTL14
++#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
++#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
++#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
++#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
++//RDPCSTX0_RDPCSTX_PHY_FUSE0
++#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
++#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
++#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
++#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
++#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
++#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
++#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
++#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
++//RDPCSTX0_RDPCSTX_PHY_FUSE1
++#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
++#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
++#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
++#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
++//RDPCSTX0_RDPCSTX_PHY_FUSE2
++#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
++#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
++//RDPCSTX0_RDPCSTX_PHY_FUSE3
++#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
++#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
++#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
++#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
++#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
++#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
++#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
++#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
++//RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL
++#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
++#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
++#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
++#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
++//RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
++//RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
++#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
++//RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG
++#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
++#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
++#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
++#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
++#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
++#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
++//RDPCSTX0_RDPCSTX_PHY_CNTL15
++#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
++#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
++#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
++#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
++#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
++#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
++#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
++//RDPCSTX0_RDPCSTX_PHY_CNTL16
++#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
++#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
++#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
++#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
++#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
++#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
++#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
++//RDPCSTX0_RDPCSTX_PHY_CNTL17
++#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
++#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
++#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
++#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
++#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
++#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
++#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
++#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
++//RDPCSTX0_RDPCSTX_DEBUG_CONFIG2
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT                                            0x0
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT                                            0x4
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT                                            0x8
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT                                            0xc
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT                               0x10
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK                                              0x00000007L
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK                                              0x00000070L
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK                                              0x00000700L
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK                                              0x00007000L
++#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK                                 0x00010000L
++
++
++// addressBlock: dpcssys_dpcssys_cr0_dispdec
++//DPCSSYS_CR0_DPCSSYS_CR_ADDR
++#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
++#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
++//DPCSSYS_CR0_DPCSSYS_CR_DATA
++#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
++#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
++
++
++// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec
++//DPCSTX1_DPCSTX_TX_CLOCK_CNTL
++#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT                                             0x0
++#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT                                                   0x1
++#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT                                             0x2
++#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0x3
++#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK                                               0x00000001L
++#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK                                                     0x00000002L
++#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK                                               0x00000004L
++#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000008L
++//DPCSTX1_DPCSTX_TX_CNTL
++#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0xc
++#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xd
++#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT                                                      0xe
++#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT                                              0xf
++#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT                                                        0x10
++#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT                                                     0x11
++#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
++#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
++#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00001000L
++#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00002000L
++#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK                                                        0x00004000L
++#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK                                                0x00008000L
++#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK                                                          0x00010000L
++#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK                                                       0x00020000L
++#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x00F00000L
++#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
++//DPCSTX1_DPCSTX_CBUS_CNTL
++#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT                                               0x0
++#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT                                                 0x1f
++#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK                                                 0x000000FFL
++#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK                                                   0x80000000L
++//DPCSTX1_DPCSTX_INTERRUPT_CNTL
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT                                          0x0
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT                                              0x1
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT                                        0x4
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT                                             0x8
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT                                             0x9
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT                                             0xa
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT                                             0xb
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT                                               0xc
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT                                         0x10
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT                                             0x14
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK                                            0x00000001L
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK                                                0x00000002L
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK                                          0x00000010L
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK                                               0x00000100L
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK                                               0x00000200L
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK                                               0x00000400L
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK                                               0x00000800L
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK                                                 0x00001000L
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK                                           0x00010000L
++#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK                                               0x00100000L
++//DPCSTX1_DPCSTX_PLL_UPDATE_ADDR
++#define DPCSTX1_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT                                           0x0
++#define DPCSTX1_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK                                             0x0003FFFFL
++//DPCSTX1_DPCSTX_PLL_UPDATE_DATA
++#define DPCSTX1_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT                                           0x0
++#define DPCSTX1_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK                                             0xFFFFFFFFL
++//DPCSTX1_DPCSTX_DEBUG_CONFIG
++#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT                                                       0x0
++#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT                                               0x1
++#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT                                            0x4
++#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT                                       0x8
++#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT                                                 0xe
++#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT                                          0x10
++#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT                                             0x18
++#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK                                                         0x00000001L
++#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK                                                 0x0000000EL
++#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK                                              0x00000070L
++#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK                                         0x00000700L
++#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK                                                   0x00004000L
++#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK                                            0x00010000L
++#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK                                               0xFF000000L
++
++
++// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
++//RDPCSTX1_RDPCSTX_CNTL
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x4
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x10
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x11
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1a
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000010L
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x00010000L
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x00020000L
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x04000000L
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
++#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
++//RDPCSTX1_RDPCSTX_CLOCK_CNTL
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT                                          0x4
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT                                          0x5
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT                                          0x6
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT                                          0x7
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT                                        0x8
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT                                              0x9
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0xa
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK                                            0x00000010L
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK                                            0x00000020L
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK                                            0x00000040L
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK                                            0x00000080L
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK                                          0x00000100L
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK                                                0x00000200L
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000400L
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
++#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
++//RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
++#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
++//RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA
++#define RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                        0x0
++#define RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                          0x00000001L
++//RDPCSTX1_RDPCS_TX_CR_ADDR
++#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
++#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
++//RDPCSTX1_RDPCS_TX_CR_DATA
++#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
++#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
++//RDPCSTX1_RDPCS_TX_SRAM_CNTL
++#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
++#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
++#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
++#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
++#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
++#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
++//RDPCSTX1_RDPCSTX_SCRATCH
++#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
++#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
++//RDPCSTX1_RDPCSTX_SPARE
++#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
++#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
++//RDPCSTX1_RDPCSTX_CNTL2
++#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
++#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
++#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
++#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
++//RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT              0x4
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK                0x00000010L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
++//RDPCSTX1_RDPCSTX_DEBUG_CONFIG
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT                                                    0x0
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT                                        0x4
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT                                        0x7
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT                                          0x8
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT                                       0xf
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT                                          0x10
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT                                              0x18
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK                                                      0x00000001L
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK                                          0x00000070L
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK                                          0x00000080L
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK                                            0x00001F00L
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK                                         0x00008000L
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK                                            0x00FF0000L
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK                                                0xFF000000L
++//RDPCSTX1_RDPCSTX_PHY_CNTL0
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
++//RDPCSTX1_RDPCSTX_PHY_CNTL1
++#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
++#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
++#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
++#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
++#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
++#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
++#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
++#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
++#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
++//RDPCSTX1_RDPCSTX_PHY_CNTL2
++#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
++#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
++#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
++#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
++#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
++#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
++#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
++#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
++#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
++#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
++//RDPCSTX1_RDPCSTX_PHY_CNTL3
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
++//RDPCSTX1_RDPCSTX_PHY_CNTL4
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
++//RDPCSTX1_RDPCSTX_PHY_CNTL5
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
++//RDPCSTX1_RDPCSTX_PHY_CNTL6
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
++//RDPCSTX1_RDPCSTX_PHY_CNTL7
++#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
++#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
++#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
++#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
++//RDPCSTX1_RDPCSTX_PHY_CNTL8
++#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
++#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
++//RDPCSTX1_RDPCSTX_PHY_CNTL9
++#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
++#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
++#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
++#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
++//RDPCSTX1_RDPCSTX_PHY_CNTL10
++#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
++#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
++//RDPCSTX1_RDPCSTX_PHY_CNTL11
++#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
++#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
++#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
++#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
++#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
++//RDPCSTX1_RDPCSTX_PHY_CNTL12
++#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
++#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
++#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
++#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
++#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
++#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
++//RDPCSTX1_RDPCSTX_PHY_CNTL13
++#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
++#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
++#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
++#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
++#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
++//RDPCSTX1_RDPCSTX_PHY_CNTL14
++#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
++#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
++#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
++#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
++//RDPCSTX1_RDPCSTX_PHY_FUSE0
++#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
++#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
++#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
++#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
++#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
++#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
++#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
++#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
++//RDPCSTX1_RDPCSTX_PHY_FUSE1
++#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
++#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
++#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
++#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
++//RDPCSTX1_RDPCSTX_PHY_FUSE2
++#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
++#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
++//RDPCSTX1_RDPCSTX_PHY_FUSE3
++#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
++#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
++#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
++#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
++#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
++#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
++#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
++#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
++//RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL
++#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
++#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
++#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
++#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
++//RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
++//RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
++#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
++//RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG
++#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
++#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
++#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
++#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
++#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
++#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
++//RDPCSTX1_RDPCSTX_PHY_CNTL15
++#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
++#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
++#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
++#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
++#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
++#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
++#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
++//RDPCSTX1_RDPCSTX_PHY_CNTL16
++#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
++#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
++#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
++#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
++#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
++#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
++#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
++//RDPCSTX1_RDPCSTX_PHY_CNTL17
++#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
++#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
++#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
++#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
++#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
++#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
++#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
++#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
++//RDPCSTX1_RDPCSTX_DEBUG_CONFIG2
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT                                            0x0
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT                                            0x4
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT                                            0x8
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT                                            0xc
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT                               0x10
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK                                              0x00000007L
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK                                              0x00000070L
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK                                              0x00000700L
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK                                              0x00007000L
++#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK                                 0x00010000L
++
++
++// addressBlock: dpcssys_dpcssys_cr1_dispdec
++//DPCSSYS_CR1_DPCSSYS_CR_ADDR
++#define DPCSSYS_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
++#define DPCSSYS_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
++//DPCSSYS_CR1_DPCSSYS_CR_DATA
++#define DPCSSYS_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
++#define DPCSSYS_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
++
++
++// addressBlock: dpcssys_dpcs0_dpcstx2_dispdec
++//DPCSTX2_DPCSTX_TX_CLOCK_CNTL
++#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT                                             0x0
++#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT                                                   0x1
++#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT                                             0x2
++#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0x3
++#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK                                               0x00000001L
++#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK                                                     0x00000002L
++#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK                                               0x00000004L
++#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000008L
++//DPCSTX2_DPCSTX_TX_CNTL
++#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0xc
++#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xd
++#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT                                                      0xe
++#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT                                              0xf
++#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT                                                        0x10
++#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT                                                     0x11
++#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
++#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
++#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00001000L
++#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00002000L
++#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK                                                        0x00004000L
++#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK                                                0x00008000L
++#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK                                                          0x00010000L
++#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK                                                       0x00020000L
++#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x00F00000L
++#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
++//DPCSTX2_DPCSTX_CBUS_CNTL
++#define DPCSTX2_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT                                               0x0
++#define DPCSTX2_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT                                                 0x1f
++#define DPCSTX2_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK                                                 0x000000FFL
++#define DPCSTX2_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK                                                   0x80000000L
++//DPCSTX2_DPCSTX_INTERRUPT_CNTL
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT                                          0x0
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT                                              0x1
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT                                        0x4
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT                                             0x8
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT                                             0x9
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT                                             0xa
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT                                             0xb
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT                                               0xc
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT                                         0x10
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT                                             0x14
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK                                            0x00000001L
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK                                                0x00000002L
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK                                          0x00000010L
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK                                               0x00000100L
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK                                               0x00000200L
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK                                               0x00000400L
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK                                               0x00000800L
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK                                                 0x00001000L
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK                                           0x00010000L
++#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK                                               0x00100000L
++//DPCSTX2_DPCSTX_PLL_UPDATE_ADDR
++#define DPCSTX2_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT                                           0x0
++#define DPCSTX2_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK                                             0x0003FFFFL
++//DPCSTX2_DPCSTX_PLL_UPDATE_DATA
++#define DPCSTX2_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT                                           0x0
++#define DPCSTX2_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK                                             0xFFFFFFFFL
++//DPCSTX2_DPCSTX_DEBUG_CONFIG
++#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT                                                       0x0
++#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT                                               0x1
++#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT                                            0x4
++#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT                                       0x8
++#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT                                                 0xe
++#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT                                          0x10
++#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT                                             0x18
++#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK                                                         0x00000001L
++#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK                                                 0x0000000EL
++#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK                                              0x00000070L
++#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK                                         0x00000700L
++#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK                                                   0x00004000L
++#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK                                            0x00010000L
++#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK                                               0xFF000000L
++
++
++// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
++//RDPCSTX2_RDPCSTX_CNTL
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x4
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x10
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x11
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1a
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000010L
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x00010000L
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x00020000L
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x04000000L
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
++#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
++//RDPCSTX2_RDPCSTX_CLOCK_CNTL
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT                                          0x4
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT                                          0x5
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT                                          0x6
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT                                          0x7
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT                                        0x8
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT                                              0x9
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0xa
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK                                            0x00000010L
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK                                            0x00000020L
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK                                            0x00000040L
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK                                            0x00000080L
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK                                          0x00000100L
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK                                                0x00000200L
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000400L
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
++#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
++//RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
++#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
++//RDPCSTX2_RDPCSTX_PLL_UPDATE_DATA
++#define RDPCSTX2_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                        0x0
++#define RDPCSTX2_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                          0x00000001L
++//RDPCSTX2_RDPCS_TX_CR_ADDR
++#define RDPCSTX2_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
++#define RDPCSTX2_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
++//RDPCSTX2_RDPCS_TX_CR_DATA
++#define RDPCSTX2_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
++#define RDPCSTX2_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
++//RDPCSTX2_RDPCS_TX_SRAM_CNTL
++#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
++#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
++#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
++#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
++#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
++#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
++//RDPCSTX2_RDPCSTX_SCRATCH
++#define RDPCSTX2_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
++#define RDPCSTX2_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
++//RDPCSTX2_RDPCSTX_SPARE
++#define RDPCSTX2_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
++#define RDPCSTX2_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
++//RDPCSTX2_RDPCSTX_CNTL2
++#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
++#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
++#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
++#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
++//RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT              0x4
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK                0x00000010L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
++//RDPCSTX2_RDPCSTX_DEBUG_CONFIG
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT                                                    0x0
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT                                        0x4
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT                                        0x7
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT                                          0x8
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT                                       0xf
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT                                          0x10
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT                                              0x18
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK                                                      0x00000001L
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK                                          0x00000070L
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK                                          0x00000080L
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK                                            0x00001F00L
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK                                         0x00008000L
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK                                            0x00FF0000L
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK                                                0xFF000000L
++//RDPCSTX2_RDPCSTX_PHY_CNTL0
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
++//RDPCSTX2_RDPCSTX_PHY_CNTL1
++#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
++#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
++#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
++#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
++#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
++#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
++#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
++#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
++#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
++//RDPCSTX2_RDPCSTX_PHY_CNTL2
++#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
++#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
++#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
++#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
++#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
++#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
++#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
++#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
++#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
++#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
++//RDPCSTX2_RDPCSTX_PHY_CNTL3
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
++//RDPCSTX2_RDPCSTX_PHY_CNTL4
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
++//RDPCSTX2_RDPCSTX_PHY_CNTL5
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
++//RDPCSTX2_RDPCSTX_PHY_CNTL6
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
++//RDPCSTX2_RDPCSTX_PHY_CNTL7
++#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
++#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
++#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
++#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
++//RDPCSTX2_RDPCSTX_PHY_CNTL8
++#define RDPCSTX2_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
++#define RDPCSTX2_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
++//RDPCSTX2_RDPCSTX_PHY_CNTL9
++#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
++#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
++#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
++#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
++//RDPCSTX2_RDPCSTX_PHY_CNTL10
++#define RDPCSTX2_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
++#define RDPCSTX2_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
++//RDPCSTX2_RDPCSTX_PHY_CNTL11
++#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
++#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
++#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
++#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
++#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
++//RDPCSTX2_RDPCSTX_PHY_CNTL12
++#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
++#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
++#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
++#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
++#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
++#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
++//RDPCSTX2_RDPCSTX_PHY_CNTL13
++#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
++#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
++#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
++#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
++#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
++//RDPCSTX2_RDPCSTX_PHY_CNTL14
++#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
++#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
++#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
++#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
++//RDPCSTX2_RDPCSTX_PHY_FUSE0
++#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
++#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
++#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
++#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
++#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
++#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
++#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
++#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
++//RDPCSTX2_RDPCSTX_PHY_FUSE1
++#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
++#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
++#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
++#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
++//RDPCSTX2_RDPCSTX_PHY_FUSE2
++#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
++#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
++//RDPCSTX2_RDPCSTX_PHY_FUSE3
++#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
++#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
++#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
++#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
++#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
++#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
++#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
++#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
++//RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL
++#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
++#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
++#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
++#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
++//RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
++//RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
++#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
++//RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG
++#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
++#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
++#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
++#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
++#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
++#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
++//RDPCSTX2_RDPCSTX_PHY_CNTL15
++#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
++#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
++#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
++#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
++#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
++#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
++#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
++//RDPCSTX2_RDPCSTX_PHY_CNTL16
++#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
++#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
++#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
++#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
++#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
++#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
++#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
++//RDPCSTX2_RDPCSTX_PHY_CNTL17
++#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
++#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
++#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
++#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
++#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
++#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
++#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
++#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
++//RDPCSTX2_RDPCSTX_DEBUG_CONFIG2
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT                                            0x0
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT                                            0x4
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT                                            0x8
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT                                            0xc
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT                               0x10
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK                                              0x00000007L
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK                                              0x00000070L
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK                                              0x00000700L
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK                                              0x00007000L
++#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK                                 0x00010000L
++
++
++// addressBlock: dpcssys_dpcssys_cr2_dispdec
++//DPCSSYS_CR2_DPCSSYS_CR_ADDR
++#define DPCSSYS_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
++#define DPCSSYS_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
++//DPCSSYS_CR2_DPCSSYS_CR_DATA
++#define DPCSSYS_CR2_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
++#define DPCSSYS_CR2_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
++
++
++// addressBlock: dpcssys_dpcs0_dpcstx3_dispdec
++//DPCSTX3_DPCSTX_TX_CLOCK_CNTL
++#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT                                             0x0
++#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT                                                   0x1
++#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT                                             0x2
++#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0x3
++#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK                                               0x00000001L
++#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK                                                     0x00000002L
++#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK                                               0x00000004L
++#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000008L
++//DPCSTX3_DPCSTX_TX_CNTL
++#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0xc
++#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xd
++#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT                                                      0xe
++#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT                                              0xf
++#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT                                                        0x10
++#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT                                                     0x11
++#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
++#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
++#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00001000L
++#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00002000L
++#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK                                                        0x00004000L
++#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK                                                0x00008000L
++#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK                                                          0x00010000L
++#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK                                                       0x00020000L
++#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x00F00000L
++#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
++//DPCSTX3_DPCSTX_CBUS_CNTL
++#define DPCSTX3_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT                                               0x0
++#define DPCSTX3_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT                                                 0x1f
++#define DPCSTX3_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK                                                 0x000000FFL
++#define DPCSTX3_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK                                                   0x80000000L
++//DPCSTX3_DPCSTX_INTERRUPT_CNTL
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT                                          0x0
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT                                              0x1
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT                                        0x4
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT                                             0x8
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT                                             0x9
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT                                             0xa
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT                                             0xb
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT                                               0xc
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT                                         0x10
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT                                             0x14
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK                                            0x00000001L
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK                                                0x00000002L
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK                                          0x00000010L
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK                                               0x00000100L
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK                                               0x00000200L
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK                                               0x00000400L
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK                                               0x00000800L
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK                                                 0x00001000L
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK                                           0x00010000L
++#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK                                               0x00100000L
++//DPCSTX3_DPCSTX_PLL_UPDATE_ADDR
++#define DPCSTX3_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT                                           0x0
++#define DPCSTX3_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK                                             0x0003FFFFL
++//DPCSTX3_DPCSTX_PLL_UPDATE_DATA
++#define DPCSTX3_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT                                           0x0
++#define DPCSTX3_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK                                             0xFFFFFFFFL
++//DPCSTX3_DPCSTX_DEBUG_CONFIG
++#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT                                                       0x0
++#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT                                               0x1
++#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT                                            0x4
++#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT                                       0x8
++#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT                                                 0xe
++#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT                                          0x10
++#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT                                             0x18
++#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK                                                         0x00000001L
++#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK                                                 0x0000000EL
++#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK                                              0x00000070L
++#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK                                         0x00000700L
++#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK                                                   0x00004000L
++#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK                                            0x00010000L
++#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK                                               0xFF000000L
++
++
++// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
++//RDPCSTX3_RDPCSTX_CNTL
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x4
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x10
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x11
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1a
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000010L
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x00010000L
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x00020000L
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x04000000L
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
++#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
++//RDPCSTX3_RDPCSTX_CLOCK_CNTL
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT                                          0x4
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT                                          0x5
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT                                          0x6
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT                                          0x7
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT                                        0x8
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT                                              0x9
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0xa
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK                                            0x00000010L
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK                                            0x00000020L
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK                                            0x00000040L
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK                                            0x00000080L
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK                                          0x00000100L
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK                                                0x00000200L
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000400L
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
++#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
++//RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
++#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
++//RDPCSTX3_RDPCSTX_PLL_UPDATE_DATA
++#define RDPCSTX3_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                        0x0
++#define RDPCSTX3_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                          0x00000001L
++//RDPCSTX3_RDPCS_TX_CR_ADDR
++#define RDPCSTX3_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
++#define RDPCSTX3_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
++//RDPCSTX3_RDPCS_TX_CR_DATA
++#define RDPCSTX3_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
++#define RDPCSTX3_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
++//RDPCSTX3_RDPCS_TX_SRAM_CNTL
++#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
++#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
++#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
++#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
++#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
++#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
++//RDPCSTX3_RDPCSTX_SCRATCH
++#define RDPCSTX3_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
++#define RDPCSTX3_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
++//RDPCSTX3_RDPCSTX_SPARE
++#define RDPCSTX3_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
++#define RDPCSTX3_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
++//RDPCSTX3_RDPCSTX_CNTL2
++#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
++#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
++#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
++#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
++//RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT              0x4
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK                0x00000010L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
++//RDPCSTX3_RDPCSTX_DEBUG_CONFIG
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT                                                    0x0
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT                                        0x4
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT                                        0x7
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT                                          0x8
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT                                       0xf
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT                                          0x10
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT                                              0x18
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK                                                      0x00000001L
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK                                          0x00000070L
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK                                          0x00000080L
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK                                            0x00001F00L
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK                                         0x00008000L
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK                                            0x00FF0000L
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK                                                0xFF000000L
++//RDPCSTX3_RDPCSTX_PHY_CNTL0
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
++//RDPCSTX3_RDPCSTX_PHY_CNTL1
++#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
++#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
++#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
++#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
++#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
++#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
++#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
++#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
++#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
++//RDPCSTX3_RDPCSTX_PHY_CNTL2
++#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
++#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
++#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
++#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
++#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
++#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
++#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
++#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
++#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
++#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
++//RDPCSTX3_RDPCSTX_PHY_CNTL3
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
++//RDPCSTX3_RDPCSTX_PHY_CNTL4
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
++//RDPCSTX3_RDPCSTX_PHY_CNTL5
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
++//RDPCSTX3_RDPCSTX_PHY_CNTL6
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
++//RDPCSTX3_RDPCSTX_PHY_CNTL7
++#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
++#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
++#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
++#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
++//RDPCSTX3_RDPCSTX_PHY_CNTL8
++#define RDPCSTX3_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
++#define RDPCSTX3_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
++//RDPCSTX3_RDPCSTX_PHY_CNTL9
++#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
++#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
++#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
++#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
++//RDPCSTX3_RDPCSTX_PHY_CNTL10
++#define RDPCSTX3_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
++#define RDPCSTX3_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
++//RDPCSTX3_RDPCSTX_PHY_CNTL11
++#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
++#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
++#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
++#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
++#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
++//RDPCSTX3_RDPCSTX_PHY_CNTL12
++#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
++#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
++#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
++#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
++#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
++#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
++//RDPCSTX3_RDPCSTX_PHY_CNTL13
++#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
++#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
++#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
++#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
++#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
++//RDPCSTX3_RDPCSTX_PHY_CNTL14
++#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
++#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
++#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
++#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
++//RDPCSTX3_RDPCSTX_PHY_FUSE0
++#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
++#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
++#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
++#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
++#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
++#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
++#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
++#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
++//RDPCSTX3_RDPCSTX_PHY_FUSE1
++#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
++#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
++#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
++#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
++//RDPCSTX3_RDPCSTX_PHY_FUSE2
++#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
++#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
++//RDPCSTX3_RDPCSTX_PHY_FUSE3
++#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
++#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
++#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
++#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
++#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
++#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
++#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
++#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
++//RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL
++#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
++#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
++#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
++#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
++//RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
++//RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
++#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
++//RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG
++#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
++#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
++#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
++#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
++#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
++#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
++//RDPCSTX3_RDPCSTX_PHY_CNTL15
++#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
++#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
++#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
++#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
++#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
++#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
++#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
++//RDPCSTX3_RDPCSTX_PHY_CNTL16
++#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
++#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
++#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
++#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
++#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
++#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
++#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
++//RDPCSTX3_RDPCSTX_PHY_CNTL17
++#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
++#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
++#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
++#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
++#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
++#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
++#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
++#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
++//RDPCSTX3_RDPCSTX_DEBUG_CONFIG2
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT                                            0x0
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT                                            0x4
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT                                            0x8
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT                                            0xc
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT                               0x10
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK                                              0x00000007L
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK                                              0x00000070L
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK                                              0x00000700L
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK                                              0x00007000L
++#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK                                 0x00010000L
++
++
++// addressBlock: dpcssys_dpcssys_cr3_dispdec
++//DPCSSYS_CR3_DPCSSYS_CR_ADDR
++#define DPCSSYS_CR3_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
++#define DPCSSYS_CR3_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
++//DPCSSYS_CR3_DPCSSYS_CR_DATA
++#define DPCSSYS_CR3_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
++#define DPCSSYS_CR3_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
++
++
++// addressBlock: dpcssys_dpcs0_dpcstx4_dispdec
++//DPCSTX4_DPCSTX_TX_CLOCK_CNTL
++#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT                                             0x0
++#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT                                                   0x1
++#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT                                             0x2
++#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0x3
++#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK                                               0x00000001L
++#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK                                                     0x00000002L
++#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK                                               0x00000004L
++#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000008L
++//DPCSTX4_DPCSTX_TX_CNTL
++#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0xc
++#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xd
++#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT                                                      0xe
++#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT                                              0xf
++#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT                                                        0x10
++#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT                                                     0x11
++#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
++#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
++#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00001000L
++#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00002000L
++#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK                                                        0x00004000L
++#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK                                                0x00008000L
++#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK                                                          0x00010000L
++#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK                                                       0x00020000L
++#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x00F00000L
++#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
++//DPCSTX4_DPCSTX_CBUS_CNTL
++#define DPCSTX4_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT                                               0x0
++#define DPCSTX4_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT                                                 0x1f
++#define DPCSTX4_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK                                                 0x000000FFL
++#define DPCSTX4_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK                                                   0x80000000L
++//DPCSTX4_DPCSTX_INTERRUPT_CNTL
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT                                          0x0
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT                                              0x1
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT                                        0x4
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT                                             0x8
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT                                             0x9
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT                                             0xa
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT                                             0xb
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT                                               0xc
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT                                         0x10
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT                                             0x14
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK                                            0x00000001L
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK                                                0x00000002L
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK                                          0x00000010L
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK                                               0x00000100L
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK                                               0x00000200L
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK                                               0x00000400L
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK                                               0x00000800L
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK                                                 0x00001000L
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK                                           0x00010000L
++#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK                                               0x00100000L
++//DPCSTX4_DPCSTX_PLL_UPDATE_ADDR
++#define DPCSTX4_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT                                           0x0
++#define DPCSTX4_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK                                             0x0003FFFFL
++//DPCSTX4_DPCSTX_PLL_UPDATE_DATA
++#define DPCSTX4_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT                                           0x0
++#define DPCSTX4_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK                                             0xFFFFFFFFL
++//DPCSTX4_DPCSTX_DEBUG_CONFIG
++#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT                                                       0x0
++#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT                                               0x1
++#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT                                            0x4
++#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT                                       0x8
++#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT                                                 0xe
++#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT                                          0x10
++#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT                                             0x18
++#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK                                                         0x00000001L
++#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK                                                 0x0000000EL
++#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK                                              0x00000070L
++#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK                                         0x00000700L
++#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK                                                   0x00004000L
++#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK                                            0x00010000L
++#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK                                               0xFF000000L
++
++
++// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
++//RDPCSTX4_RDPCSTX_CNTL
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x4
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x10
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x11
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1a
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000010L
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x00010000L
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x00020000L
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x04000000L
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
++#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
++//RDPCSTX4_RDPCSTX_CLOCK_CNTL
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT                                          0x4
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT                                          0x5
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT                                          0x6
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT                                          0x7
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT                                        0x8
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT                                              0x9
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0xa
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK                                            0x00000010L
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK                                            0x00000020L
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK                                            0x00000040L
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK                                            0x00000080L
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK                                          0x00000100L
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK                                                0x00000200L
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000400L
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
++#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
++//RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
++#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
++//RDPCSTX4_RDPCSTX_PLL_UPDATE_DATA
++#define RDPCSTX4_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                        0x0
++#define RDPCSTX4_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                          0x00000001L
++//RDPCSTX4_RDPCS_TX_CR_ADDR
++#define RDPCSTX4_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
++#define RDPCSTX4_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
++//RDPCSTX4_RDPCS_TX_CR_DATA
++#define RDPCSTX4_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
++#define RDPCSTX4_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
++//RDPCSTX4_RDPCS_TX_SRAM_CNTL
++#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
++#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
++#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
++#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
++#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
++#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
++//RDPCSTX4_RDPCSTX_SCRATCH
++#define RDPCSTX4_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
++#define RDPCSTX4_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
++//RDPCSTX4_RDPCSTX_SPARE
++#define RDPCSTX4_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
++#define RDPCSTX4_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
++//RDPCSTX4_RDPCSTX_CNTL2
++#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
++#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
++#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
++#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
++//RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT              0x4
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK                0x00000010L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
++//RDPCSTX4_RDPCSTX_DEBUG_CONFIG
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT                                                    0x0
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT                                        0x4
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT                                        0x7
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT                                          0x8
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT                                       0xf
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT                                          0x10
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT                                              0x18
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK                                                      0x00000001L
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK                                          0x00000070L
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK                                          0x00000080L
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK                                            0x00001F00L
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK                                         0x00008000L
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK                                            0x00FF0000L
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK                                                0xFF000000L
++//RDPCSTX4_RDPCSTX_PHY_CNTL0
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
++//RDPCSTX4_RDPCSTX_PHY_CNTL1
++#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
++#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
++#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
++#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
++#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
++#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
++#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
++#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
++#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
++//RDPCSTX4_RDPCSTX_PHY_CNTL2
++#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
++#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
++#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
++#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
++#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
++#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
++#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
++#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
++#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
++#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
++//RDPCSTX4_RDPCSTX_PHY_CNTL3
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
++//RDPCSTX4_RDPCSTX_PHY_CNTL4
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
++//RDPCSTX4_RDPCSTX_PHY_CNTL5
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
++//RDPCSTX4_RDPCSTX_PHY_CNTL6
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
++//RDPCSTX4_RDPCSTX_PHY_CNTL7
++#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
++#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
++#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
++#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
++//RDPCSTX4_RDPCSTX_PHY_CNTL8
++#define RDPCSTX4_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
++#define RDPCSTX4_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
++//RDPCSTX4_RDPCSTX_PHY_CNTL9
++#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
++#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
++#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
++#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
++//RDPCSTX4_RDPCSTX_PHY_CNTL10
++#define RDPCSTX4_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
++#define RDPCSTX4_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
++//RDPCSTX4_RDPCSTX_PHY_CNTL11
++#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
++#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
++#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
++#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
++#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
++//RDPCSTX4_RDPCSTX_PHY_CNTL12
++#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
++#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
++#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
++#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
++#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
++#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
++//RDPCSTX4_RDPCSTX_PHY_CNTL13
++#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
++#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
++#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
++#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
++#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
++//RDPCSTX4_RDPCSTX_PHY_CNTL14
++#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
++#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
++#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
++#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
++//RDPCSTX4_RDPCSTX_PHY_FUSE0
++#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
++#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
++#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
++#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
++#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
++#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
++#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
++#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
++//RDPCSTX4_RDPCSTX_PHY_FUSE1
++#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
++#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
++#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
++#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
++//RDPCSTX4_RDPCSTX_PHY_FUSE2
++#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
++#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
++//RDPCSTX4_RDPCSTX_PHY_FUSE3
++#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
++#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
++#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
++#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
++#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
++#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
++#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
++#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
++#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
++#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
++#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
++#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
++#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
++#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
++//RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL
++#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
++#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
++#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
++#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
++//RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
++//RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
++#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
++//RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG
++#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
++#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
++#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
++#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
++#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
++#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
++//RDPCSTX4_RDPCSTX_PHY_CNTL15
++#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
++#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
++#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
++#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
++#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
++#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
++#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
++//RDPCSTX4_RDPCSTX_PHY_CNTL16
++#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
++#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
++#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
++#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
++#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
++#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
++#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
++//RDPCSTX4_RDPCSTX_PHY_CNTL17
++#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
++#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
++#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
++#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
++#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
++#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
++#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
++#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
++//RDPCSTX4_RDPCSTX_DEBUG_CONFIG2
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT                                            0x0
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT                                            0x4
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT                                            0x8
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT                                            0xc
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT                               0x10
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK                                              0x00000007L
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK                                              0x00000070L
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK                                              0x00000700L
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK                                              0x00007000L
++#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK                                 0x00010000L
++
++
++// addressBlock: dpcssys_dpcssys_cr4_dispdec
++//DPCSSYS_CR4_DPCSSYS_CR_ADDR
++#define DPCSSYS_CR4_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
++#define DPCSSYS_CR4_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
++//DPCSSYS_CR4_DPCSSYS_CR_DATA
++#define DPCSSYS_CR4_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
++#define DPCSSYS_CR4_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
++
++#endif
+diff --git a/drivers/gpu/drm/amd/include/renoir_ip_offset.h b/drivers/gpu/drm/amd/include/renoir_ip_offset.h
+new file mode 100644
+index 000000000000..554714c8e000
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/renoir_ip_offset.h
+@@ -0,0 +1,1364 @@
++/*
++ * Copyright (C) 2019  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _renoir_ip_offset_HEADER
++#define _renoir_ip_offset_HEADER
++
++#define MAX_INSTANCE                                       7
++#define MAX_SEGMENT                                        5
++
++
++struct IP_BASE_INSTANCE
++{
++    unsigned int segment[MAX_SEGMENT];
++};
++
++struct IP_BASE
++{
++    struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
++};
++
++
++static const struct IP_BASE ACP_BASE ={ { { { 0x02403800, 0x00480000, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x02408C00, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017E00, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE DBGU_IO0_BASE ={ { { { 0x000001E0, 0x0240B400, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x02402C00, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE HDA_BASE ={ { { { 0x02404800, 0x004C0000, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE IOHC0_BASE ={ { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE ISP_BASE ={ { { { 0x00018000, 0x0240B000, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE L2IMU0_BASE ={ { { { 0x00007DC0, 0x02407000, 0x00900000, 0x04FC0000, 0x055C0000 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE MP1_BASE ={ { { { 0x00016200, 0x02400400, 0x00E80000, 0x00EC0000, 0x00F00000 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x0240A800, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },
++                                        { { 0x00054000, 0x02425C00, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
++
++
++#define ACP_BASE__INST0_SEG0                       0x02403800
++#define ACP_BASE__INST0_SEG1                       0x00480000
++#define ACP_BASE__INST0_SEG2                       0
++#define ACP_BASE__INST0_SEG3                       0
++#define ACP_BASE__INST0_SEG4                       0
++
++#define ACP_BASE__INST1_SEG0                       0
++#define ACP_BASE__INST1_SEG1                       0
++#define ACP_BASE__INST1_SEG2                       0
++#define ACP_BASE__INST1_SEG3                       0
++#define ACP_BASE__INST1_SEG4                       0
++
++#define ACP_BASE__INST2_SEG0                       0
++#define ACP_BASE__INST2_SEG1                       0
++#define ACP_BASE__INST2_SEG2                       0
++#define ACP_BASE__INST2_SEG3                       0
++#define ACP_BASE__INST2_SEG4                       0
++
++#define ACP_BASE__INST3_SEG0                       0
++#define ACP_BASE__INST3_SEG1                       0
++#define ACP_BASE__INST3_SEG2                       0
++#define ACP_BASE__INST3_SEG3                       0
++#define ACP_BASE__INST3_SEG4                       0
++
++#define ACP_BASE__INST4_SEG0                       0
++#define ACP_BASE__INST4_SEG1                       0
++#define ACP_BASE__INST4_SEG2                       0
++#define ACP_BASE__INST4_SEG3                       0
++#define ACP_BASE__INST4_SEG4                       0
++
++#define ACP_BASE__INST5_SEG0                       0
++#define ACP_BASE__INST5_SEG1                       0
++#define ACP_BASE__INST5_SEG2                       0
++#define ACP_BASE__INST5_SEG3                       0
++#define ACP_BASE__INST5_SEG4                       0
++
++#define ACP_BASE__INST6_SEG0                       0
++#define ACP_BASE__INST6_SEG1                       0
++#define ACP_BASE__INST6_SEG2                       0
++#define ACP_BASE__INST6_SEG3                       0
++#define ACP_BASE__INST6_SEG4                       0
++
++#define ATHUB_BASE__INST0_SEG0                     0x00000C20
++#define ATHUB_BASE__INST0_SEG1                     0x02408C00
++#define ATHUB_BASE__INST0_SEG2                     0
++#define ATHUB_BASE__INST0_SEG3                     0
++#define ATHUB_BASE__INST0_SEG4                     0
++
++#define ATHUB_BASE__INST1_SEG0                     0
++#define ATHUB_BASE__INST1_SEG1                     0
++#define ATHUB_BASE__INST1_SEG2                     0
++#define ATHUB_BASE__INST1_SEG3                     0
++#define ATHUB_BASE__INST1_SEG4                     0
++
++#define ATHUB_BASE__INST2_SEG0                     0
++#define ATHUB_BASE__INST2_SEG1                     0
++#define ATHUB_BASE__INST2_SEG2                     0
++#define ATHUB_BASE__INST2_SEG3                     0
++#define ATHUB_BASE__INST2_SEG4                     0
++
++#define ATHUB_BASE__INST3_SEG0                     0
++#define ATHUB_BASE__INST3_SEG1                     0
++#define ATHUB_BASE__INST3_SEG2                     0
++#define ATHUB_BASE__INST3_SEG3                     0
++#define ATHUB_BASE__INST3_SEG4                     0
++
++#define ATHUB_BASE__INST4_SEG0                     0
++#define ATHUB_BASE__INST4_SEG1                     0
++#define ATHUB_BASE__INST4_SEG2                     0
++#define ATHUB_BASE__INST4_SEG3                     0
++#define ATHUB_BASE__INST4_SEG4                     0
++
++#define ATHUB_BASE__INST5_SEG0                     0
++#define ATHUB_BASE__INST5_SEG1                     0
++#define ATHUB_BASE__INST5_SEG2                     0
++#define ATHUB_BASE__INST5_SEG3                     0
++#define ATHUB_BASE__INST5_SEG4                     0
++
++#define ATHUB_BASE__INST6_SEG0                     0
++#define ATHUB_BASE__INST6_SEG1                     0
++#define ATHUB_BASE__INST6_SEG2                     0
++#define ATHUB_BASE__INST6_SEG3                     0
++#define ATHUB_BASE__INST6_SEG4                     0
++
++#define CLK_BASE__INST0_SEG0                       0x00016C00
++#define CLK_BASE__INST0_SEG1                       0x00016E00
++#define CLK_BASE__INST0_SEG2                       0x00017000
++#define CLK_BASE__INST0_SEG3                       0x00017E00
++#define CLK_BASE__INST0_SEG4                       0
++
++#define CLK_BASE__INST1_SEG0                       0
++#define CLK_BASE__INST1_SEG1                       0
++#define CLK_BASE__INST1_SEG2                       0
++#define CLK_BASE__INST1_SEG3                       0
++#define CLK_BASE__INST1_SEG4                       0
++
++#define CLK_BASE__INST2_SEG0                       0
++#define CLK_BASE__INST2_SEG1                       0
++#define CLK_BASE__INST2_SEG2                       0
++#define CLK_BASE__INST2_SEG3                       0
++#define CLK_BASE__INST2_SEG4                       0
++
++#define CLK_BASE__INST3_SEG0                       0
++#define CLK_BASE__INST3_SEG1                       0
++#define CLK_BASE__INST3_SEG2                       0
++#define CLK_BASE__INST3_SEG3                       0
++#define CLK_BASE__INST3_SEG4                       0
++
++#define CLK_BASE__INST4_SEG0                       0
++#define CLK_BASE__INST4_SEG1                       0
++#define CLK_BASE__INST4_SEG2                       0
++#define CLK_BASE__INST4_SEG3                       0
++#define CLK_BASE__INST4_SEG4                       0
++
++#define CLK_BASE__INST5_SEG0                       0
++#define CLK_BASE__INST5_SEG1                       0
++#define CLK_BASE__INST5_SEG2                       0
++#define CLK_BASE__INST5_SEG3                       0
++#define CLK_BASE__INST5_SEG4                       0
++
++#define CLK_BASE__INST6_SEG0                       0
++#define CLK_BASE__INST6_SEG1                       0
++#define CLK_BASE__INST6_SEG2                       0
++#define CLK_BASE__INST6_SEG3                       0
++#define CLK_BASE__INST6_SEG4                       0
++
++#define DBGU_IO0_BASE__INST0_SEG0                  0x000001E0
++#define DBGU_IO0_BASE__INST0_SEG1                  0x0240B400
++#define DBGU_IO0_BASE__INST0_SEG2                  0
++#define DBGU_IO0_BASE__INST0_SEG3                  0
++#define DBGU_IO0_BASE__INST0_SEG4                  0
++
++#define DBGU_IO0_BASE__INST1_SEG0                  0
++#define DBGU_IO0_BASE__INST1_SEG1                  0
++#define DBGU_IO0_BASE__INST1_SEG2                  0
++#define DBGU_IO0_BASE__INST1_SEG3                  0
++#define DBGU_IO0_BASE__INST1_SEG4                  0
++
++#define DBGU_IO0_BASE__INST2_SEG0                  0
++#define DBGU_IO0_BASE__INST2_SEG1                  0
++#define DBGU_IO0_BASE__INST2_SEG2                  0
++#define DBGU_IO0_BASE__INST2_SEG3                  0
++#define DBGU_IO0_BASE__INST2_SEG4                  0
++
++#define DBGU_IO0_BASE__INST3_SEG0                  0
++#define DBGU_IO0_BASE__INST3_SEG1                  0
++#define DBGU_IO0_BASE__INST3_SEG2                  0
++#define DBGU_IO0_BASE__INST3_SEG3                  0
++#define DBGU_IO0_BASE__INST3_SEG4                  0
++
++#define DBGU_IO0_BASE__INST4_SEG0                  0
++#define DBGU_IO0_BASE__INST4_SEG1                  0
++#define DBGU_IO0_BASE__INST4_SEG2                  0
++#define DBGU_IO0_BASE__INST4_SEG3                  0
++#define DBGU_IO0_BASE__INST4_SEG4                  0
++
++#define DBGU_IO0_BASE__INST5_SEG0                  0
++#define DBGU_IO0_BASE__INST5_SEG1                  0
++#define DBGU_IO0_BASE__INST5_SEG2                  0
++#define DBGU_IO0_BASE__INST5_SEG3                  0
++#define DBGU_IO0_BASE__INST5_SEG4                  0
++
++#define DBGU_IO0_BASE__INST6_SEG0                  0
++#define DBGU_IO0_BASE__INST6_SEG1                  0
++#define DBGU_IO0_BASE__INST6_SEG2                  0
++#define DBGU_IO0_BASE__INST6_SEG3                  0
++#define DBGU_IO0_BASE__INST6_SEG4                  0
++
++#define DF_BASE__INST0_SEG0                        0x00007000
++#define DF_BASE__INST0_SEG1                        0x0240B800
++#define DF_BASE__INST0_SEG2                        0
++#define DF_BASE__INST0_SEG3                        0
++#define DF_BASE__INST0_SEG4                        0
++
++#define DF_BASE__INST1_SEG0                        0
++#define DF_BASE__INST1_SEG1                        0
++#define DF_BASE__INST1_SEG2                        0
++#define DF_BASE__INST1_SEG3                        0
++#define DF_BASE__INST1_SEG4                        0
++
++#define DF_BASE__INST2_SEG0                        0
++#define DF_BASE__INST2_SEG1                        0
++#define DF_BASE__INST2_SEG2                        0
++#define DF_BASE__INST2_SEG3                        0
++#define DF_BASE__INST2_SEG4                        0
++
++#define DF_BASE__INST3_SEG0                        0
++#define DF_BASE__INST3_SEG1                        0
++#define DF_BASE__INST3_SEG2                        0
++#define DF_BASE__INST3_SEG3                        0
++#define DF_BASE__INST3_SEG4                        0
++
++#define DF_BASE__INST4_SEG0                        0
++#define DF_BASE__INST4_SEG1                        0
++#define DF_BASE__INST4_SEG2                        0
++#define DF_BASE__INST4_SEG3                        0
++#define DF_BASE__INST4_SEG4                        0
++
++#define DF_BASE__INST5_SEG0                        0
++#define DF_BASE__INST5_SEG1                        0
++#define DF_BASE__INST5_SEG2                        0
++#define DF_BASE__INST5_SEG3                        0
++#define DF_BASE__INST5_SEG4                        0
++
++#define DF_BASE__INST6_SEG0                        0
++#define DF_BASE__INST6_SEG1                        0
++#define DF_BASE__INST6_SEG2                        0
++#define DF_BASE__INST6_SEG3                        0
++#define DF_BASE__INST6_SEG4                        0
++
++#define DIO_BASE__INST0_SEG0                       0x02404000
++#define DIO_BASE__INST0_SEG1                       0
++#define DIO_BASE__INST0_SEG2                       0
++#define DIO_BASE__INST0_SEG3                       0
++#define DIO_BASE__INST0_SEG4                       0
++
++#define DIO_BASE__INST1_SEG0                       0
++#define DIO_BASE__INST1_SEG1                       0
++#define DIO_BASE__INST1_SEG2                       0
++#define DIO_BASE__INST1_SEG3                       0
++#define DIO_BASE__INST1_SEG4                       0
++
++#define DIO_BASE__INST2_SEG0                       0
++#define DIO_BASE__INST2_SEG1                       0
++#define DIO_BASE__INST2_SEG2                       0
++#define DIO_BASE__INST2_SEG3                       0
++#define DIO_BASE__INST2_SEG4                       0
++
++#define DIO_BASE__INST3_SEG0                       0
++#define DIO_BASE__INST3_SEG1                       0
++#define DIO_BASE__INST3_SEG2                       0
++#define DIO_BASE__INST3_SEG3                       0
++#define DIO_BASE__INST3_SEG4                       0
++
++#define DIO_BASE__INST4_SEG0                       0
++#define DIO_BASE__INST4_SEG1                       0
++#define DIO_BASE__INST4_SEG2                       0
++#define DIO_BASE__INST4_SEG3                       0
++#define DIO_BASE__INST4_SEG4                       0
++
++#define DIO_BASE__INST5_SEG0                       0
++#define DIO_BASE__INST5_SEG1                       0
++#define DIO_BASE__INST5_SEG2                       0
++#define DIO_BASE__INST5_SEG3                       0
++#define DIO_BASE__INST5_SEG4                       0
++
++#define DIO_BASE__INST6_SEG0                       0
++#define DIO_BASE__INST6_SEG1                       0
++#define DIO_BASE__INST6_SEG2                       0
++#define DIO_BASE__INST6_SEG3                       0
++#define DIO_BASE__INST6_SEG4                       0
++
++#define DMU_BASE__INST0_SEG0                       0x00000012
++#define DMU_BASE__INST0_SEG1                       0x000000C0
++#define DMU_BASE__INST0_SEG2                       0x000034C0
++#define DMU_BASE__INST0_SEG3                       0x00009000
++#define DMU_BASE__INST0_SEG4                       0x02403C00
++
++#define DMU_BASE__INST1_SEG0                       0
++#define DMU_BASE__INST1_SEG1                       0
++#define DMU_BASE__INST1_SEG2                       0
++#define DMU_BASE__INST1_SEG3                       0
++#define DMU_BASE__INST1_SEG4                       0
++
++#define DMU_BASE__INST2_SEG0                       0
++#define DMU_BASE__INST2_SEG1                       0
++#define DMU_BASE__INST2_SEG2                       0
++#define DMU_BASE__INST2_SEG3                       0
++#define DMU_BASE__INST2_SEG4                       0
++
++#define DMU_BASE__INST3_SEG0                       0
++#define DMU_BASE__INST3_SEG1                       0
++#define DMU_BASE__INST3_SEG2                       0
++#define DMU_BASE__INST3_SEG3                       0
++#define DMU_BASE__INST3_SEG4                       0
++
++#define DMU_BASE__INST4_SEG0                       0
++#define DMU_BASE__INST4_SEG1                       0
++#define DMU_BASE__INST4_SEG2                       0
++#define DMU_BASE__INST4_SEG3                       0
++#define DMU_BASE__INST4_SEG4                       0
++
++#define DMU_BASE__INST5_SEG0                       0
++#define DMU_BASE__INST5_SEG1                       0
++#define DMU_BASE__INST5_SEG2                       0
++#define DMU_BASE__INST5_SEG3                       0
++#define DMU_BASE__INST5_SEG4                       0
++
++#define DMU_BASE__INST6_SEG0                       0
++#define DMU_BASE__INST6_SEG1                       0
++#define DMU_BASE__INST6_SEG2                       0
++#define DMU_BASE__INST6_SEG3                       0
++#define DMU_BASE__INST6_SEG4                       0
++
++#define DPCS_BASE__INST0_SEG0                      0x00000012
++#define DPCS_BASE__INST0_SEG1                      0x000000C0
++#define DPCS_BASE__INST0_SEG2                      0x000034C0
++#define DPCS_BASE__INST0_SEG3                      0x00009000
++#define DPCS_BASE__INST0_SEG4                      0x02403C00
++
++#define DPCS_BASE__INST1_SEG0                      0
++#define DPCS_BASE__INST1_SEG1                      0
++#define DPCS_BASE__INST1_SEG2                      0
++#define DPCS_BASE__INST1_SEG3                      0
++#define DPCS_BASE__INST1_SEG4                      0
++
++#define DPCS_BASE__INST2_SEG0                      0
++#define DPCS_BASE__INST2_SEG1                      0
++#define DPCS_BASE__INST2_SEG2                      0
++#define DPCS_BASE__INST2_SEG3                      0
++#define DPCS_BASE__INST2_SEG4                      0
++
++#define DPCS_BASE__INST3_SEG0                      0
++#define DPCS_BASE__INST3_SEG1                      0
++#define DPCS_BASE__INST3_SEG2                      0
++#define DPCS_BASE__INST3_SEG3                      0
++#define DPCS_BASE__INST3_SEG4                      0
++
++#define DPCS_BASE__INST4_SEG0                      0
++#define DPCS_BASE__INST4_SEG1                      0
++#define DPCS_BASE__INST4_SEG2                      0
++#define DPCS_BASE__INST4_SEG3                      0
++#define DPCS_BASE__INST4_SEG4                      0
++
++#define DPCS_BASE__INST5_SEG0                      0
++#define DPCS_BASE__INST5_SEG1                      0
++#define DPCS_BASE__INST5_SEG2                      0
++#define DPCS_BASE__INST5_SEG3                      0
++#define DPCS_BASE__INST5_SEG4                      0
++
++#define DPCS_BASE__INST6_SEG0                      0
++#define DPCS_BASE__INST6_SEG1                      0
++#define DPCS_BASE__INST6_SEG2                      0
++#define DPCS_BASE__INST6_SEG3                      0
++#define DPCS_BASE__INST6_SEG4                      0
++
++#define FUSE_BASE__INST0_SEG0                      0x00017400
++#define FUSE_BASE__INST0_SEG1                      0x02401400
++#define FUSE_BASE__INST0_SEG2                      0
++#define FUSE_BASE__INST0_SEG3                      0
++#define FUSE_BASE__INST0_SEG4                      0
++
++#define FUSE_BASE__INST1_SEG0                      0
++#define FUSE_BASE__INST1_SEG1                      0
++#define FUSE_BASE__INST1_SEG2                      0
++#define FUSE_BASE__INST1_SEG3                      0
++#define FUSE_BASE__INST1_SEG4                      0
++
++#define FUSE_BASE__INST2_SEG0                      0
++#define FUSE_BASE__INST2_SEG1                      0
++#define FUSE_BASE__INST2_SEG2                      0
++#define FUSE_BASE__INST2_SEG3                      0
++#define FUSE_BASE__INST2_SEG4                      0
++
++#define FUSE_BASE__INST3_SEG0                      0
++#define FUSE_BASE__INST3_SEG1                      0
++#define FUSE_BASE__INST3_SEG2                      0
++#define FUSE_BASE__INST3_SEG3                      0
++#define FUSE_BASE__INST3_SEG4                      0
++
++#define FUSE_BASE__INST4_SEG0                      0
++#define FUSE_BASE__INST4_SEG1                      0
++#define FUSE_BASE__INST4_SEG2                      0
++#define FUSE_BASE__INST4_SEG3                      0
++#define FUSE_BASE__INST4_SEG4                      0
++
++#define FUSE_BASE__INST5_SEG0                      0
++#define FUSE_BASE__INST5_SEG1                      0
++#define FUSE_BASE__INST5_SEG2                      0
++#define FUSE_BASE__INST5_SEG3                      0
++#define FUSE_BASE__INST5_SEG4                      0
++
++#define FUSE_BASE__INST6_SEG0                      0
++#define FUSE_BASE__INST6_SEG1                      0
++#define FUSE_BASE__INST6_SEG2                      0
++#define FUSE_BASE__INST6_SEG3                      0
++#define FUSE_BASE__INST6_SEG4                      0
++
++#define GC_BASE__INST0_SEG0                        0x00002000
++#define GC_BASE__INST0_SEG1                        0x0000A000
++#define GC_BASE__INST0_SEG2                        0x02402C00
++#define GC_BASE__INST0_SEG3                        0
++#define GC_BASE__INST0_SEG4                        0
++
++#define GC_BASE__INST1_SEG0                        0
++#define GC_BASE__INST1_SEG1                        0
++#define GC_BASE__INST1_SEG2                        0
++#define GC_BASE__INST1_SEG3                        0
++#define GC_BASE__INST1_SEG4                        0
++
++#define GC_BASE__INST2_SEG0                        0
++#define GC_BASE__INST2_SEG1                        0
++#define GC_BASE__INST2_SEG2                        0
++#define GC_BASE__INST2_SEG3                        0
++#define GC_BASE__INST2_SEG4                        0
++
++#define GC_BASE__INST3_SEG0                        0
++#define GC_BASE__INST3_SEG1                        0
++#define GC_BASE__INST3_SEG2                        0
++#define GC_BASE__INST3_SEG3                        0
++#define GC_BASE__INST3_SEG4                        0
++
++#define GC_BASE__INST4_SEG0                        0
++#define GC_BASE__INST4_SEG1                        0
++#define GC_BASE__INST4_SEG2                        0
++#define GC_BASE__INST4_SEG3                        0
++#define GC_BASE__INST4_SEG4                        0
++
++#define GC_BASE__INST5_SEG0                        0
++#define GC_BASE__INST5_SEG1                        0
++#define GC_BASE__INST5_SEG2                        0
++#define GC_BASE__INST5_SEG3                        0
++#define GC_BASE__INST5_SEG4                        0
++
++#define GC_BASE__INST6_SEG0                        0
++#define GC_BASE__INST6_SEG1                        0
++#define GC_BASE__INST6_SEG2                        0
++#define GC_BASE__INST6_SEG3                        0
++#define GC_BASE__INST6_SEG4                        0
++
++#define HDA_BASE__INST0_SEG0                       0x02404800
++#define HDA_BASE__INST0_SEG1                       0x004C0000
++#define HDA_BASE__INST0_SEG2                       0
++#define HDA_BASE__INST0_SEG3                       0
++#define HDA_BASE__INST0_SEG4                       0
++
++#define HDA_BASE__INST1_SEG0                       0
++#define HDA_BASE__INST1_SEG1                       0
++#define HDA_BASE__INST1_SEG2                       0
++#define HDA_BASE__INST1_SEG3                       0
++#define HDA_BASE__INST1_SEG4                       0
++
++#define HDA_BASE__INST2_SEG0                       0
++#define HDA_BASE__INST2_SEG1                       0
++#define HDA_BASE__INST2_SEG2                       0
++#define HDA_BASE__INST2_SEG3                       0
++#define HDA_BASE__INST2_SEG4                       0
++
++#define HDA_BASE__INST3_SEG0                       0
++#define HDA_BASE__INST3_SEG1                       0
++#define HDA_BASE__INST3_SEG2                       0
++#define HDA_BASE__INST3_SEG3                       0
++#define HDA_BASE__INST3_SEG4                       0
++
++#define HDA_BASE__INST4_SEG0                       0
++#define HDA_BASE__INST4_SEG1                       0
++#define HDA_BASE__INST4_SEG2                       0
++#define HDA_BASE__INST4_SEG3                       0
++#define HDA_BASE__INST4_SEG4                       0
++
++#define HDA_BASE__INST5_SEG0                       0
++#define HDA_BASE__INST5_SEG1                       0
++#define HDA_BASE__INST5_SEG2                       0
++#define HDA_BASE__INST5_SEG3                       0
++#define HDA_BASE__INST5_SEG4                       0
++
++#define HDA_BASE__INST6_SEG0                       0
++#define HDA_BASE__INST6_SEG1                       0
++#define HDA_BASE__INST6_SEG2                       0
++#define HDA_BASE__INST6_SEG3                       0
++#define HDA_BASE__INST6_SEG4                       0
++
++#define HDP_BASE__INST0_SEG0                       0x00000F20
++#define HDP_BASE__INST0_SEG1                       0x0240A400
++#define HDP_BASE__INST0_SEG2                       0
++#define HDP_BASE__INST0_SEG3                       0
++#define HDP_BASE__INST0_SEG4                       0
++
++#define HDP_BASE__INST1_SEG0                       0
++#define HDP_BASE__INST1_SEG1                       0
++#define HDP_BASE__INST1_SEG2                       0
++#define HDP_BASE__INST1_SEG3                       0
++#define HDP_BASE__INST1_SEG4                       0
++
++#define HDP_BASE__INST2_SEG0                       0
++#define HDP_BASE__INST2_SEG1                       0
++#define HDP_BASE__INST2_SEG2                       0
++#define HDP_BASE__INST2_SEG3                       0
++#define HDP_BASE__INST2_SEG4                       0
++
++#define HDP_BASE__INST3_SEG0                       0
++#define HDP_BASE__INST3_SEG1                       0
++#define HDP_BASE__INST3_SEG2                       0
++#define HDP_BASE__INST3_SEG3                       0
++#define HDP_BASE__INST3_SEG4                       0
++
++#define HDP_BASE__INST4_SEG0                       0
++#define HDP_BASE__INST4_SEG1                       0
++#define HDP_BASE__INST4_SEG2                       0
++#define HDP_BASE__INST4_SEG3                       0
++#define HDP_BASE__INST4_SEG4                       0
++
++#define HDP_BASE__INST5_SEG0                       0
++#define HDP_BASE__INST5_SEG1                       0
++#define HDP_BASE__INST5_SEG2                       0
++#define HDP_BASE__INST5_SEG3                       0
++#define HDP_BASE__INST5_SEG4                       0
++
++#define HDP_BASE__INST6_SEG0                       0
++#define HDP_BASE__INST6_SEG1                       0
++#define HDP_BASE__INST6_SEG2                       0
++#define HDP_BASE__INST6_SEG3                       0
++#define HDP_BASE__INST6_SEG4                       0
++
++#define IOHC0_BASE__INST0_SEG0                     0x00010000
++#define IOHC0_BASE__INST0_SEG1                     0x02406000
++#define IOHC0_BASE__INST0_SEG2                     0x04EC0000
++#define IOHC0_BASE__INST0_SEG3                     0
++#define IOHC0_BASE__INST0_SEG4                     0
++
++#define IOHC0_BASE__INST1_SEG0                     0
++#define IOHC0_BASE__INST1_SEG1                     0
++#define IOHC0_BASE__INST1_SEG2                     0
++#define IOHC0_BASE__INST1_SEG3                     0
++#define IOHC0_BASE__INST1_SEG4                     0
++
++#define IOHC0_BASE__INST2_SEG0                     0
++#define IOHC0_BASE__INST2_SEG1                     0
++#define IOHC0_BASE__INST2_SEG2                     0
++#define IOHC0_BASE__INST2_SEG3                     0
++#define IOHC0_BASE__INST2_SEG4                     0
++
++#define IOHC0_BASE__INST3_SEG0                     0
++#define IOHC0_BASE__INST3_SEG1                     0
++#define IOHC0_BASE__INST3_SEG2                     0
++#define IOHC0_BASE__INST3_SEG3                     0
++#define IOHC0_BASE__INST3_SEG4                     0
++
++#define IOHC0_BASE__INST4_SEG0                     0
++#define IOHC0_BASE__INST4_SEG1                     0
++#define IOHC0_BASE__INST4_SEG2                     0
++#define IOHC0_BASE__INST4_SEG3                     0
++#define IOHC0_BASE__INST4_SEG4                     0
++
++#define IOHC0_BASE__INST5_SEG0                     0
++#define IOHC0_BASE__INST5_SEG1                     0
++#define IOHC0_BASE__INST5_SEG2                     0
++#define IOHC0_BASE__INST5_SEG3                     0
++#define IOHC0_BASE__INST5_SEG4                     0
++
++#define IOHC0_BASE__INST6_SEG0                     0
++#define IOHC0_BASE__INST6_SEG1                     0
++#define IOHC0_BASE__INST6_SEG2                     0
++#define IOHC0_BASE__INST6_SEG3                     0
++#define IOHC0_BASE__INST6_SEG4                     0
++
++#define ISP_BASE__INST0_SEG0                       0x00018000
++#define ISP_BASE__INST0_SEG1                       0x0240B000
++#define ISP_BASE__INST0_SEG2                       0
++#define ISP_BASE__INST0_SEG3                       0
++#define ISP_BASE__INST0_SEG4                       0
++
++#define ISP_BASE__INST1_SEG0                       0
++#define ISP_BASE__INST1_SEG1                       0
++#define ISP_BASE__INST1_SEG2                       0
++#define ISP_BASE__INST1_SEG3                       0
++#define ISP_BASE__INST1_SEG4                       0
++
++#define ISP_BASE__INST2_SEG0                       0
++#define ISP_BASE__INST2_SEG1                       0
++#define ISP_BASE__INST2_SEG2                       0
++#define ISP_BASE__INST2_SEG3                       0
++#define ISP_BASE__INST2_SEG4                       0
++
++#define ISP_BASE__INST3_SEG0                       0
++#define ISP_BASE__INST3_SEG1                       0
++#define ISP_BASE__INST3_SEG2                       0
++#define ISP_BASE__INST3_SEG3                       0
++#define ISP_BASE__INST3_SEG4                       0
++
++#define ISP_BASE__INST4_SEG0                       0
++#define ISP_BASE__INST4_SEG1                       0
++#define ISP_BASE__INST4_SEG2                       0
++#define ISP_BASE__INST4_SEG3                       0
++#define ISP_BASE__INST4_SEG4                       0
++
++#define ISP_BASE__INST5_SEG0                       0
++#define ISP_BASE__INST5_SEG1                       0
++#define ISP_BASE__INST5_SEG2                       0
++#define ISP_BASE__INST5_SEG3                       0
++#define ISP_BASE__INST5_SEG4                       0
++
++#define ISP_BASE__INST6_SEG0                       0
++#define ISP_BASE__INST6_SEG1                       0
++#define ISP_BASE__INST6_SEG2                       0
++#define ISP_BASE__INST6_SEG3                       0
++#define ISP_BASE__INST6_SEG4                       0
++
++#define L2IMU0_BASE__INST0_SEG0                    0x00007DC0
++#define L2IMU0_BASE__INST0_SEG1                    0x02407000
++#define L2IMU0_BASE__INST0_SEG2                    0x00900000
++#define L2IMU0_BASE__INST0_SEG3                    0x04FC0000
++#define L2IMU0_BASE__INST0_SEG4                    0x055C0000
++
++#define L2IMU0_BASE__INST1_SEG0                    0
++#define L2IMU0_BASE__INST1_SEG1                    0
++#define L2IMU0_BASE__INST1_SEG2                    0
++#define L2IMU0_BASE__INST1_SEG3                    0
++#define L2IMU0_BASE__INST1_SEG4                    0
++
++#define L2IMU0_BASE__INST2_SEG0                    0
++#define L2IMU0_BASE__INST2_SEG1                    0
++#define L2IMU0_BASE__INST2_SEG2                    0
++#define L2IMU0_BASE__INST2_SEG3                    0
++#define L2IMU0_BASE__INST2_SEG4                    0
++
++#define L2IMU0_BASE__INST3_SEG0                    0
++#define L2IMU0_BASE__INST3_SEG1                    0
++#define L2IMU0_BASE__INST3_SEG2                    0
++#define L2IMU0_BASE__INST3_SEG3                    0
++#define L2IMU0_BASE__INST3_SEG4                    0
++
++#define L2IMU0_BASE__INST4_SEG0                    0
++#define L2IMU0_BASE__INST4_SEG1                    0
++#define L2IMU0_BASE__INST4_SEG2                    0
++#define L2IMU0_BASE__INST4_SEG3                    0
++#define L2IMU0_BASE__INST4_SEG4                    0
++
++#define L2IMU0_BASE__INST5_SEG0                    0
++#define L2IMU0_BASE__INST5_SEG1                    0
++#define L2IMU0_BASE__INST5_SEG2                    0
++#define L2IMU0_BASE__INST5_SEG3                    0
++#define L2IMU0_BASE__INST5_SEG4                    0
++
++#define L2IMU0_BASE__INST6_SEG0                    0
++#define L2IMU0_BASE__INST6_SEG1                    0
++#define L2IMU0_BASE__INST6_SEG2                    0
++#define L2IMU0_BASE__INST6_SEG3                    0
++#define L2IMU0_BASE__INST6_SEG4                    0
++
++#define MMHUB_BASE__INST0_SEG0                     0x0001A000
++#define MMHUB_BASE__INST0_SEG1                     0x02408800
++#define MMHUB_BASE__INST0_SEG2                     0
++#define MMHUB_BASE__INST0_SEG3                     0
++#define MMHUB_BASE__INST0_SEG4                     0
++
++#define MMHUB_BASE__INST1_SEG0                     0
++#define MMHUB_BASE__INST1_SEG1                     0
++#define MMHUB_BASE__INST1_SEG2                     0
++#define MMHUB_BASE__INST1_SEG3                     0
++#define MMHUB_BASE__INST1_SEG4                     0
++
++#define MMHUB_BASE__INST2_SEG0                     0
++#define MMHUB_BASE__INST2_SEG1                     0
++#define MMHUB_BASE__INST2_SEG2                     0
++#define MMHUB_BASE__INST2_SEG3                     0
++#define MMHUB_BASE__INST2_SEG4                     0
++
++#define MMHUB_BASE__INST3_SEG0                     0
++#define MMHUB_BASE__INST3_SEG1                     0
++#define MMHUB_BASE__INST3_SEG2                     0
++#define MMHUB_BASE__INST3_SEG3                     0
++#define MMHUB_BASE__INST3_SEG4                     0
++
++#define MMHUB_BASE__INST4_SEG0                     0
++#define MMHUB_BASE__INST4_SEG1                     0
++#define MMHUB_BASE__INST4_SEG2                     0
++#define MMHUB_BASE__INST4_SEG3                     0
++#define MMHUB_BASE__INST4_SEG4                     0
++
++#define MMHUB_BASE__INST5_SEG0                     0
++#define MMHUB_BASE__INST5_SEG1                     0
++#define MMHUB_BASE__INST5_SEG2                     0
++#define MMHUB_BASE__INST5_SEG3                     0
++#define MMHUB_BASE__INST5_SEG4                     0
++
++#define MMHUB_BASE__INST6_SEG0                     0
++#define MMHUB_BASE__INST6_SEG1                     0
++#define MMHUB_BASE__INST6_SEG2                     0
++#define MMHUB_BASE__INST6_SEG3                     0
++#define MMHUB_BASE__INST6_SEG4                     0
++
++#define MP0_BASE__INST0_SEG0                       0x00016000
++#define MP0_BASE__INST0_SEG1                       0x0243FC00
++#define MP0_BASE__INST0_SEG2                       0x00DC0000
++#define MP0_BASE__INST0_SEG3                       0x00E00000
++#define MP0_BASE__INST0_SEG4                       0x00E40000
++
++#define MP0_BASE__INST1_SEG0                       0
++#define MP0_BASE__INST1_SEG1                       0
++#define MP0_BASE__INST1_SEG2                       0
++#define MP0_BASE__INST1_SEG3                       0
++#define MP0_BASE__INST1_SEG4                       0
++
++#define MP0_BASE__INST2_SEG0                       0
++#define MP0_BASE__INST2_SEG1                       0
++#define MP0_BASE__INST2_SEG2                       0
++#define MP0_BASE__INST2_SEG3                       0
++#define MP0_BASE__INST2_SEG4                       0
++
++#define MP0_BASE__INST3_SEG0                       0
++#define MP0_BASE__INST3_SEG1                       0
++#define MP0_BASE__INST3_SEG2                       0
++#define MP0_BASE__INST3_SEG3                       0
++#define MP0_BASE__INST3_SEG4                       0
++
++#define MP0_BASE__INST4_SEG0                       0
++#define MP0_BASE__INST4_SEG1                       0
++#define MP0_BASE__INST4_SEG2                       0
++#define MP0_BASE__INST4_SEG3                       0
++#define MP0_BASE__INST4_SEG4                       0
++
++#define MP0_BASE__INST5_SEG0                       0
++#define MP0_BASE__INST5_SEG1                       0
++#define MP0_BASE__INST5_SEG2                       0
++#define MP0_BASE__INST5_SEG3                       0
++#define MP0_BASE__INST5_SEG4                       0
++
++#define MP0_BASE__INST6_SEG0                       0
++#define MP0_BASE__INST6_SEG1                       0
++#define MP0_BASE__INST6_SEG2                       0
++#define MP0_BASE__INST6_SEG3                       0
++#define MP0_BASE__INST6_SEG4                       0
++
++#define MP1_BASE__INST0_SEG0                       0x00016200
++#define MP1_BASE__INST0_SEG1                       0x02400400
++#define MP1_BASE__INST0_SEG2                       0x00E80000
++#define MP1_BASE__INST0_SEG3                       0x00EC0000
++#define MP1_BASE__INST0_SEG4                       0x00F00000
++
++#define MP1_BASE__INST1_SEG0                       0
++#define MP1_BASE__INST1_SEG1                       0
++#define MP1_BASE__INST1_SEG2                       0
++#define MP1_BASE__INST1_SEG3                       0
++#define MP1_BASE__INST1_SEG4                       0
++
++#define MP1_BASE__INST2_SEG0                       0
++#define MP1_BASE__INST2_SEG1                       0
++#define MP1_BASE__INST2_SEG2                       0
++#define MP1_BASE__INST2_SEG3                       0
++#define MP1_BASE__INST2_SEG4                       0
++
++#define MP1_BASE__INST3_SEG0                       0
++#define MP1_BASE__INST3_SEG1                       0
++#define MP1_BASE__INST3_SEG2                       0
++#define MP1_BASE__INST3_SEG3                       0
++#define MP1_BASE__INST3_SEG4                       0
++
++#define MP1_BASE__INST4_SEG0                       0
++#define MP1_BASE__INST4_SEG1                       0
++#define MP1_BASE__INST4_SEG2                       0
++#define MP1_BASE__INST4_SEG3                       0
++#define MP1_BASE__INST4_SEG4                       0
++
++#define MP1_BASE__INST5_SEG0                       0
++#define MP1_BASE__INST5_SEG1                       0
++#define MP1_BASE__INST5_SEG2                       0
++#define MP1_BASE__INST5_SEG3                       0
++#define MP1_BASE__INST5_SEG4                       0
++
++#define MP1_BASE__INST6_SEG0                       0
++#define MP1_BASE__INST6_SEG1                       0
++#define MP1_BASE__INST6_SEG2                       0
++#define MP1_BASE__INST6_SEG3                       0
++#define MP1_BASE__INST6_SEG4                       0
++
++#define NBIF0_BASE__INST0_SEG0                     0x00000000
++#define NBIF0_BASE__INST0_SEG1                     0x00000014
++#define NBIF0_BASE__INST0_SEG2                     0x00000D20
++#define NBIF0_BASE__INST0_SEG3                     0x00010400
++#define NBIF0_BASE__INST0_SEG4                     0x0241B000
++
++#define NBIF0_BASE__INST1_SEG0                     0
++#define NBIF0_BASE__INST1_SEG1                     0
++#define NBIF0_BASE__INST1_SEG2                     0
++#define NBIF0_BASE__INST1_SEG3                     0
++#define NBIF0_BASE__INST1_SEG4                     0
++
++#define NBIF0_BASE__INST2_SEG0                     0
++#define NBIF0_BASE__INST2_SEG1                     0
++#define NBIF0_BASE__INST2_SEG2                     0
++#define NBIF0_BASE__INST2_SEG3                     0
++#define NBIF0_BASE__INST2_SEG4                     0
++
++#define NBIF0_BASE__INST3_SEG0                     0
++#define NBIF0_BASE__INST3_SEG1                     0
++#define NBIF0_BASE__INST3_SEG2                     0
++#define NBIF0_BASE__INST3_SEG3                     0
++#define NBIF0_BASE__INST3_SEG4                     0
++
++#define NBIF0_BASE__INST4_SEG0                     0
++#define NBIF0_BASE__INST4_SEG1                     0
++#define NBIF0_BASE__INST4_SEG2                     0
++#define NBIF0_BASE__INST4_SEG3                     0
++#define NBIF0_BASE__INST4_SEG4                     0
++
++#define NBIF0_BASE__INST5_SEG0                     0
++#define NBIF0_BASE__INST5_SEG1                     0
++#define NBIF0_BASE__INST5_SEG2                     0
++#define NBIF0_BASE__INST5_SEG3                     0
++#define NBIF0_BASE__INST5_SEG4                     0
++
++#define NBIF0_BASE__INST6_SEG0                     0
++#define NBIF0_BASE__INST6_SEG1                     0
++#define NBIF0_BASE__INST6_SEG2                     0
++#define NBIF0_BASE__INST6_SEG3                     0
++#define NBIF0_BASE__INST6_SEG4                     0
++
++#define OSSSYS_BASE__INST0_SEG0                    0x000010A0
++#define OSSSYS_BASE__INST0_SEG1                    0x0240A000
++#define OSSSYS_BASE__INST0_SEG2                    0
++#define OSSSYS_BASE__INST0_SEG3                    0
++#define OSSSYS_BASE__INST0_SEG4                    0
++
++#define OSSSYS_BASE__INST1_SEG0                    0
++#define OSSSYS_BASE__INST1_SEG1                    0
++#define OSSSYS_BASE__INST1_SEG2                    0
++#define OSSSYS_BASE__INST1_SEG3                    0
++#define OSSSYS_BASE__INST1_SEG4                    0
++
++#define OSSSYS_BASE__INST2_SEG0                    0
++#define OSSSYS_BASE__INST2_SEG1                    0
++#define OSSSYS_BASE__INST2_SEG2                    0
++#define OSSSYS_BASE__INST2_SEG3                    0
++#define OSSSYS_BASE__INST2_SEG4                    0
++
++#define OSSSYS_BASE__INST3_SEG0                    0
++#define OSSSYS_BASE__INST3_SEG1                    0
++#define OSSSYS_BASE__INST3_SEG2                    0
++#define OSSSYS_BASE__INST3_SEG3                    0
++#define OSSSYS_BASE__INST3_SEG4                    0
++
++#define OSSSYS_BASE__INST4_SEG0                    0
++#define OSSSYS_BASE__INST4_SEG1                    0
++#define OSSSYS_BASE__INST4_SEG2                    0
++#define OSSSYS_BASE__INST4_SEG3                    0
++#define OSSSYS_BASE__INST4_SEG4                    0
++
++#define OSSSYS_BASE__INST5_SEG0                    0
++#define OSSSYS_BASE__INST5_SEG1                    0
++#define OSSSYS_BASE__INST5_SEG2                    0
++#define OSSSYS_BASE__INST5_SEG3                    0
++#define OSSSYS_BASE__INST5_SEG4                    0
++
++#define OSSSYS_BASE__INST6_SEG0                    0
++#define OSSSYS_BASE__INST6_SEG1                    0
++#define OSSSYS_BASE__INST6_SEG2                    0
++#define OSSSYS_BASE__INST6_SEG3                    0
++#define OSSSYS_BASE__INST6_SEG4                    0
++
++#define PCIE0_BASE__INST0_SEG0                     0x02411800
++#define PCIE0_BASE__INST0_SEG1                     0x04440000
++#define PCIE0_BASE__INST0_SEG2                     0
++#define PCIE0_BASE__INST0_SEG3                     0
++#define PCIE0_BASE__INST0_SEG4                     0
++
++#define PCIE0_BASE__INST1_SEG0                     0
++#define PCIE0_BASE__INST1_SEG1                     0
++#define PCIE0_BASE__INST1_SEG2                     0
++#define PCIE0_BASE__INST1_SEG3                     0
++#define PCIE0_BASE__INST1_SEG4                     0
++
++#define PCIE0_BASE__INST2_SEG0                     0
++#define PCIE0_BASE__INST2_SEG1                     0
++#define PCIE0_BASE__INST2_SEG2                     0
++#define PCIE0_BASE__INST2_SEG3                     0
++#define PCIE0_BASE__INST2_SEG4                     0
++
++#define PCIE0_BASE__INST3_SEG0                     0
++#define PCIE0_BASE__INST3_SEG1                     0
++#define PCIE0_BASE__INST3_SEG2                     0
++#define PCIE0_BASE__INST3_SEG3                     0
++#define PCIE0_BASE__INST3_SEG4                     0
++
++#define PCIE0_BASE__INST4_SEG0                     0
++#define PCIE0_BASE__INST4_SEG1                     0
++#define PCIE0_BASE__INST4_SEG2                     0
++#define PCIE0_BASE__INST4_SEG3                     0
++#define PCIE0_BASE__INST4_SEG4                     0
++
++#define PCIE0_BASE__INST5_SEG0                     0
++#define PCIE0_BASE__INST5_SEG1                     0
++#define PCIE0_BASE__INST5_SEG2                     0
++#define PCIE0_BASE__INST5_SEG3                     0
++#define PCIE0_BASE__INST5_SEG4                     0
++
++#define PCIE0_BASE__INST6_SEG0                     0
++#define PCIE0_BASE__INST6_SEG1                     0
++#define PCIE0_BASE__INST6_SEG2                     0
++#define PCIE0_BASE__INST6_SEG3                     0
++#define PCIE0_BASE__INST6_SEG4                     0
++
++#define SDMA0_BASE__INST0_SEG0                     0x00001260
++#define SDMA0_BASE__INST0_SEG1                     0x0240A800
++#define SDMA0_BASE__INST0_SEG2                     0
++#define SDMA0_BASE__INST0_SEG3                     0
++#define SDMA0_BASE__INST0_SEG4                     0
++
++#define SDMA0_BASE__INST1_SEG0                     0
++#define SDMA0_BASE__INST1_SEG1                     0
++#define SDMA0_BASE__INST1_SEG2                     0
++#define SDMA0_BASE__INST1_SEG3                     0
++#define SDMA0_BASE__INST1_SEG4                     0
++
++#define SDMA0_BASE__INST2_SEG0                     0
++#define SDMA0_BASE__INST2_SEG1                     0
++#define SDMA0_BASE__INST2_SEG2                     0
++#define SDMA0_BASE__INST2_SEG3                     0
++#define SDMA0_BASE__INST2_SEG4                     0
++
++#define SDMA0_BASE__INST3_SEG0                     0
++#define SDMA0_BASE__INST3_SEG1                     0
++#define SDMA0_BASE__INST3_SEG2                     0
++#define SDMA0_BASE__INST3_SEG3                     0
++#define SDMA0_BASE__INST3_SEG4                     0
++
++#define SDMA0_BASE__INST4_SEG0                     0
++#define SDMA0_BASE__INST4_SEG1                     0
++#define SDMA0_BASE__INST4_SEG2                     0
++#define SDMA0_BASE__INST4_SEG3                     0
++#define SDMA0_BASE__INST4_SEG4                     0
++
++#define SDMA0_BASE__INST5_SEG0                     0
++#define SDMA0_BASE__INST5_SEG1                     0
++#define SDMA0_BASE__INST5_SEG2                     0
++#define SDMA0_BASE__INST5_SEG3                     0
++#define SDMA0_BASE__INST5_SEG4                     0
++
++#define SDMA0_BASE__INST6_SEG0                     0
++#define SDMA0_BASE__INST6_SEG1                     0
++#define SDMA0_BASE__INST6_SEG2                     0
++#define SDMA0_BASE__INST6_SEG3                     0
++#define SDMA0_BASE__INST6_SEG4                     0
++
++#define SMUIO_BASE__INST0_SEG0                     0x00016800
++#define SMUIO_BASE__INST0_SEG1                     0x00016A00
++#define SMUIO_BASE__INST0_SEG2                     0x02401000
++#define SMUIO_BASE__INST0_SEG3                     0x00440000
++#define SMUIO_BASE__INST0_SEG4                     0
++
++#define SMUIO_BASE__INST1_SEG0                     0
++#define SMUIO_BASE__INST1_SEG1                     0
++#define SMUIO_BASE__INST1_SEG2                     0
++#define SMUIO_BASE__INST1_SEG3                     0
++#define SMUIO_BASE__INST1_SEG4                     0
++
++#define SMUIO_BASE__INST2_SEG0                     0
++#define SMUIO_BASE__INST2_SEG1                     0
++#define SMUIO_BASE__INST2_SEG2                     0
++#define SMUIO_BASE__INST2_SEG3                     0
++#define SMUIO_BASE__INST2_SEG4                     0
++
++#define SMUIO_BASE__INST3_SEG0                     0
++#define SMUIO_BASE__INST3_SEG1                     0
++#define SMUIO_BASE__INST3_SEG2                     0
++#define SMUIO_BASE__INST3_SEG3                     0
++#define SMUIO_BASE__INST3_SEG4                     0
++
++#define SMUIO_BASE__INST4_SEG0                     0
++#define SMUIO_BASE__INST4_SEG1                     0
++#define SMUIO_BASE__INST4_SEG2                     0
++#define SMUIO_BASE__INST4_SEG3                     0
++#define SMUIO_BASE__INST4_SEG4                     0
++
++#define SMUIO_BASE__INST5_SEG0                     0
++#define SMUIO_BASE__INST5_SEG1                     0
++#define SMUIO_BASE__INST5_SEG2                     0
++#define SMUIO_BASE__INST5_SEG3                     0
++#define SMUIO_BASE__INST5_SEG4                     0
++
++#define SMUIO_BASE__INST6_SEG0                     0
++#define SMUIO_BASE__INST6_SEG1                     0
++#define SMUIO_BASE__INST6_SEG2                     0
++#define SMUIO_BASE__INST6_SEG3                     0
++#define SMUIO_BASE__INST6_SEG4                     0
++
++#define THM_BASE__INST0_SEG0                       0x00016600
++#define THM_BASE__INST0_SEG1                       0x02400C00
++#define THM_BASE__INST0_SEG2                       0
++#define THM_BASE__INST0_SEG3                       0
++#define THM_BASE__INST0_SEG4                       0
++
++#define THM_BASE__INST1_SEG0                       0
++#define THM_BASE__INST1_SEG1                       0
++#define THM_BASE__INST1_SEG2                       0
++#define THM_BASE__INST1_SEG3                       0
++#define THM_BASE__INST1_SEG4                       0
++
++#define THM_BASE__INST2_SEG0                       0
++#define THM_BASE__INST2_SEG1                       0
++#define THM_BASE__INST2_SEG2                       0
++#define THM_BASE__INST2_SEG3                       0
++#define THM_BASE__INST2_SEG4                       0
++
++#define THM_BASE__INST3_SEG0                       0
++#define THM_BASE__INST3_SEG1                       0
++#define THM_BASE__INST3_SEG2                       0
++#define THM_BASE__INST3_SEG3                       0
++#define THM_BASE__INST3_SEG4                       0
++
++#define THM_BASE__INST4_SEG0                       0
++#define THM_BASE__INST4_SEG1                       0
++#define THM_BASE__INST4_SEG2                       0
++#define THM_BASE__INST4_SEG3                       0
++#define THM_BASE__INST4_SEG4                       0
++
++#define THM_BASE__INST5_SEG0                       0
++#define THM_BASE__INST5_SEG1                       0
++#define THM_BASE__INST5_SEG2                       0
++#define THM_BASE__INST5_SEG3                       0
++#define THM_BASE__INST5_SEG4                       0
++
++#define THM_BASE__INST6_SEG0                       0
++#define THM_BASE__INST6_SEG1                       0
++#define THM_BASE__INST6_SEG2                       0
++#define THM_BASE__INST6_SEG3                       0
++#define THM_BASE__INST6_SEG4                       0
++
++#define UMC_BASE__INST0_SEG0                       0x00014000
++#define UMC_BASE__INST0_SEG1                       0x02425800
++#define UMC_BASE__INST0_SEG2                       0
++#define UMC_BASE__INST0_SEG3                       0
++#define UMC_BASE__INST0_SEG4                       0
++
++#define UMC_BASE__INST1_SEG0                       0x00054000
++#define UMC_BASE__INST1_SEG1                       0x02425C00
++#define UMC_BASE__INST1_SEG2                       0
++#define UMC_BASE__INST1_SEG3                       0
++#define UMC_BASE__INST1_SEG4                       0
++
++#define UMC_BASE__INST2_SEG0                       0
++#define UMC_BASE__INST2_SEG1                       0
++#define UMC_BASE__INST2_SEG2                       0
++#define UMC_BASE__INST2_SEG3                       0
++#define UMC_BASE__INST2_SEG4                       0
++
++#define UMC_BASE__INST3_SEG0                       0
++#define UMC_BASE__INST3_SEG1                       0
++#define UMC_BASE__INST3_SEG2                       0
++#define UMC_BASE__INST3_SEG3                       0
++#define UMC_BASE__INST3_SEG4                       0
++
++#define UMC_BASE__INST4_SEG0                       0
++#define UMC_BASE__INST4_SEG1                       0
++#define UMC_BASE__INST4_SEG2                       0
++#define UMC_BASE__INST4_SEG3                       0
++#define UMC_BASE__INST4_SEG4                       0
++
++#define UMC_BASE__INST5_SEG0                       0
++#define UMC_BASE__INST5_SEG1                       0
++#define UMC_BASE__INST5_SEG2                       0
++#define UMC_BASE__INST5_SEG3                       0
++#define UMC_BASE__INST5_SEG4                       0
++
++#define UMC_BASE__INST6_SEG0                       0
++#define UMC_BASE__INST6_SEG1                       0
++#define UMC_BASE__INST6_SEG2                       0
++#define UMC_BASE__INST6_SEG3                       0
++#define UMC_BASE__INST6_SEG4                       0
++
++#define USB0_BASE__INST0_SEG0                      0x0242A800
++#define USB0_BASE__INST0_SEG1                      0x05B00000
++#define USB0_BASE__INST0_SEG2                      0
++#define USB0_BASE__INST0_SEG3                      0
++#define USB0_BASE__INST0_SEG4                      0
++
++#define USB0_BASE__INST1_SEG0                      0
++#define USB0_BASE__INST1_SEG1                      0
++#define USB0_BASE__INST1_SEG2                      0
++#define USB0_BASE__INST1_SEG3                      0
++#define USB0_BASE__INST1_SEG4                      0
++
++#define USB0_BASE__INST2_SEG0                      0
++#define USB0_BASE__INST2_SEG1                      0
++#define USB0_BASE__INST2_SEG2                      0
++#define USB0_BASE__INST2_SEG3                      0
++#define USB0_BASE__INST2_SEG4                      0
++
++#define USB0_BASE__INST3_SEG0                      0
++#define USB0_BASE__INST3_SEG1                      0
++#define USB0_BASE__INST3_SEG2                      0
++#define USB0_BASE__INST3_SEG3                      0
++#define USB0_BASE__INST3_SEG4                      0
++
++#define USB0_BASE__INST4_SEG0                      0
++#define USB0_BASE__INST4_SEG1                      0
++#define USB0_BASE__INST4_SEG2                      0
++#define USB0_BASE__INST4_SEG3                      0
++#define USB0_BASE__INST4_SEG4                      0
++
++#define USB0_BASE__INST5_SEG0                      0
++#define USB0_BASE__INST5_SEG1                      0
++#define USB0_BASE__INST5_SEG2                      0
++#define USB0_BASE__INST5_SEG3                      0
++#define USB0_BASE__INST5_SEG4                      0
++
++#define USB0_BASE__INST6_SEG0                      0
++#define USB0_BASE__INST6_SEG1                      0
++#define USB0_BASE__INST6_SEG2                      0
++#define USB0_BASE__INST6_SEG3                      0
++#define USB0_BASE__INST6_SEG4                      0
++
++#define UVD0_BASE__INST0_SEG0                      0x00007800
++#define UVD0_BASE__INST0_SEG1                      0x00007E00
++#define UVD0_BASE__INST0_SEG2                      0x02403000
++#define UVD0_BASE__INST0_SEG3                      0
++#define UVD0_BASE__INST0_SEG4                      0
++
++#define UVD0_BASE__INST1_SEG0                      0
++#define UVD0_BASE__INST1_SEG1                      0
++#define UVD0_BASE__INST1_SEG2                      0
++#define UVD0_BASE__INST1_SEG3                      0
++#define UVD0_BASE__INST1_SEG4                      0
++
++#define UVD0_BASE__INST2_SEG0                      0
++#define UVD0_BASE__INST2_SEG1                      0
++#define UVD0_BASE__INST2_SEG2                      0
++#define UVD0_BASE__INST2_SEG3                      0
++#define UVD0_BASE__INST2_SEG4                      0
++
++#define UVD0_BASE__INST3_SEG0                      0
++#define UVD0_BASE__INST3_SEG1                      0
++#define UVD0_BASE__INST3_SEG2                      0
++#define UVD0_BASE__INST3_SEG3                      0
++#define UVD0_BASE__INST3_SEG4                      0
++
++#define UVD0_BASE__INST4_SEG0                      0
++#define UVD0_BASE__INST4_SEG1                      0
++#define UVD0_BASE__INST4_SEG2                      0
++#define UVD0_BASE__INST4_SEG3                      0
++#define UVD0_BASE__INST4_SEG4                      0
++
++#define UVD0_BASE__INST5_SEG0                      0
++#define UVD0_BASE__INST5_SEG1                      0
++#define UVD0_BASE__INST5_SEG2                      0
++#define UVD0_BASE__INST5_SEG3                      0
++#define UVD0_BASE__INST5_SEG4                      0
++
++#define UVD0_BASE__INST6_SEG0                      0
++#define UVD0_BASE__INST6_SEG1                      0
++#define UVD0_BASE__INST6_SEG2                      0
++#define UVD0_BASE__INST6_SEG3                      0
++#define UVD0_BASE__INST6_SEG4                      0
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3632-drm-amd-display-Add-Renoir-clock-registers-list.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3632-drm-amd-display-Add-Renoir-clock-registers-list.patch
new file mode 100644
index 00000000..cd579fbb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3632-drm-amd-display-Add-Renoir-clock-registers-list.patch
@@ -0,0 +1,45 @@
+From 361fe908a646059f025ac00c83c7c59bdd187c84 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 25 Jul 2019 15:51:09 -0400
+Subject: [PATCH 3632/4256] drm/amd/display: Add Renoir clock registers list
+
+These are the registers used to program the clock hw.
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/display/dc/dce/dce_clock_source.h   | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+index adae03b1f3a7..43c1bf60b83c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+@@ -78,6 +78,23 @@
+ 		SRII(PIXEL_RATE_CNTL, OTG, 5)
+ #endif
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++#define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \
++		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
++		SRII(PHASE, DP_DTO, 0),\
++		SRII(PHASE, DP_DTO, 1),\
++		SRII(PHASE, DP_DTO, 2),\
++		SRII(PHASE, DP_DTO, 3),\
++		SRII(MODULO, DP_DTO, 0),\
++		SRII(MODULO, DP_DTO, 1),\
++		SRII(MODULO, DP_DTO, 2),\
++		SRII(MODULO, DP_DTO, 3),\
++		SRII(PIXEL_RATE_CNTL, OTG, 0),\
++		SRII(PIXEL_RATE_CNTL, OTG, 1),\
++		SRII(PIXEL_RATE_CNTL, OTG, 2),\
++		SRII(PIXEL_RATE_CNTL, OTG, 3)
++#endif
++
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
+ 	CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3633-drm-amd-display-Add-Renoir-hw_seq-register-list.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3633-drm-amd-display-Add-Renoir-hw_seq-register-list.patch
new file mode 100644
index 00000000..e2654fbe
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3633-drm-amd-display-Add-Renoir-hw_seq-register-list.patch
@@ -0,0 +1,133 @@
+From cee093cb188e99e4d7156b37e897d8145bea8afa Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 21 Aug 2019 16:56:52 -0500
+Subject: [PATCH 3633/4256] drm/amd/display: Add Renoir hw_seq register list
+
+These are the registers used to for the hw sequences
+for modesetting.
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dce/dce_hwseq.h    | 97 +++++++++++++++++++
+ 1 file changed, 97 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+index 7d93babaa2fb..b7767d6be1b4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+@@ -278,6 +278,59 @@
+ 	BL_REG_LIST()
+ #endif
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++#define HWSEQ_DCN21_REG_LIST()\
++	HWSEQ_DCN_REG_LIST(), \
++	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
++	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
++	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
++	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
++	MMHUB_DCN_REG_LIST(), \
++	SR(MICROSECOND_TIME_BASE_DIV), \
++	SR(MILLISECOND_TIME_BASE_DIV), \
++	SR(DISPCLK_FREQ_CHANGE_CNTL), \
++	SR(RBBMIF_TIMEOUT_DIS), \
++	SR(RBBMIF_TIMEOUT_DIS_2), \
++	SR(DCHUBBUB_CRC_CTRL), \
++	SR(DPP_TOP0_DPP_CRC_CTRL), \
++	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
++	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
++	SR(MPC_CRC_CTRL), \
++	SR(MPC_CRC_RESULT_GB), \
++	SR(MPC_CRC_RESULT_C), \
++	SR(MPC_CRC_RESULT_AR), \
++	SR(DOMAIN0_PG_CONFIG), \
++	SR(DOMAIN1_PG_CONFIG), \
++	SR(DOMAIN2_PG_CONFIG), \
++	SR(DOMAIN3_PG_CONFIG), \
++	SR(DOMAIN4_PG_CONFIG), \
++	SR(DOMAIN5_PG_CONFIG), \
++	SR(DOMAIN6_PG_CONFIG), \
++	SR(DOMAIN7_PG_CONFIG), \
++	SR(DOMAIN16_PG_CONFIG), \
++	SR(DOMAIN17_PG_CONFIG), \
++	SR(DOMAIN18_PG_CONFIG), \
++	SR(DOMAIN0_PG_STATUS), \
++	SR(DOMAIN1_PG_STATUS), \
++	SR(DOMAIN2_PG_STATUS), \
++	SR(DOMAIN3_PG_STATUS), \
++	SR(DOMAIN4_PG_STATUS), \
++	SR(DOMAIN5_PG_STATUS), \
++	SR(DOMAIN6_PG_STATUS), \
++	SR(DOMAIN7_PG_STATUS), \
++	SR(DOMAIN16_PG_STATUS), \
++	SR(DOMAIN17_PG_STATUS), \
++	SR(DOMAIN18_PG_STATUS), \
++	SR(D1VGA_CONTROL), \
++	SR(D2VGA_CONTROL), \
++	SR(D3VGA_CONTROL), \
++	SR(D4VGA_CONTROL), \
++	SR(D5VGA_CONTROL), \
++	SR(D6VGA_CONTROL), \
++	SR(DC_IP_REQUEST_CNTL), \
++	BL_REG_LIST()
++#endif
++
+ struct dce_hwseq_registers {
+ 
+ 		/* Backlight registers */
+@@ -586,6 +639,50 @@ struct dce_hwseq_registers {
+ 	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
+ #endif
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++#define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\
++	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
++	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
++	HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
++	HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
++	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
++	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
++	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
++	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
++	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
++	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
++	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
++	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
++	HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
++	HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
++	HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
++	HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
++	HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
++	HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
++	HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
++	HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
++	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \
++	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \
++	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \
++	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \
++	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \
++	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \
++	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
++	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
++	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
++	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
++	HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
++	HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
++	HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
++	HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
++	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \
++	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
++	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
++	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
++	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
++	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
++#endif
++
+ #define HWSEQ_REG_FIELD_LIST(type) \
+ 	type DCFE_CLOCK_ENABLE; \
+ 	type DCFEV_CLOCK_ENABLE; \
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3634-drm-amd-display-Add-pp_smu-functions-for-Renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3634-drm-amd-display-Add-pp_smu-functions-for-Renoir.patch
new file mode 100644
index 00000000..e2c2d7ee
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3634-drm-amd-display-Add-pp_smu-functions-for-Renoir.patch
@@ -0,0 +1,90 @@
+From d354716729becd3e83a6b15119ac73badd8c7fac Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 25 Jul 2019 15:58:18 -0400
+Subject: [PATCH 3634/4256] drm/amd/display: Add pp_smu functions for Renoir
+
+This defines the interface for communicating requirements
+between DC and powerplay.
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 47 ++++++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+index 825e097e4bab..6aa1686f59ab 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+@@ -44,6 +44,9 @@ enum pp_smu_ver {
+ #ifndef CONFIG_TRIM_DRM_AMD_DC_DCN2_0
+ 	PP_SMU_VER_NV,
+ #endif
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	PP_SMU_VER_RN,
++#endif
+ 
+ 	PP_SMU_VER_MAX
+ };
+@@ -240,6 +243,47 @@ struct pp_smu_funcs_nv {
+ };
+ #endif
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++
++#define PP_SMU_NUM_SOCCLK_DPM_LEVELS  8
++#define PP_SMU_NUM_DCFCLK_DPM_LEVELS  4
++#define PP_SMU_NUM_FCLK_DPM_LEVELS    4
++#define PP_SMU_NUM_MEMCLK_DPM_LEVELS  4
++
++struct dpm_clock {
++  uint32_t  Freq;    // In MHz
++  uint32_t  Vol;     // Millivolts with 2 fractional bits
++};
++
++
++/* this is a copy of the structure defined in smuxx_driver_if.h*/
++struct dpm_clocks {
++	struct dpm_clock DcfClocks[PP_SMU_NUM_DCFCLK_DPM_LEVELS];
++	struct dpm_clock SocClocks[PP_SMU_NUM_SOCCLK_DPM_LEVELS];
++	struct dpm_clock FClocks[PP_SMU_NUM_FCLK_DPM_LEVELS];
++	struct dpm_clock MemClocks[PP_SMU_NUM_MEMCLK_DPM_LEVELS];
++};
++
++
++struct pp_smu_funcs_rn {
++	struct pp_smu pp_smu;
++
++	/*
++	 * reader and writer WM's are sent together as part of one table
++	 *
++	 * PPSMC_MSG_SetDriverDramAddrHigh
++	 * PPSMC_MSG_SetDriverDramAddrLow
++	 * PPSMC_MSG_TransferTableDram2Smu
++	 *
++	 */
++	enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
++			struct pp_smu_wm_range_sets *ranges);
++
++	enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
++			struct dpm_clocks *clock_table);
++};
++#endif
++
+ struct pp_smu_funcs {
+ 	struct pp_smu ctx;
+ 	union {
+@@ -247,6 +291,9 @@ struct pp_smu_funcs {
+ #ifndef CONFIG_TRIM_DRM_AMD_DC_DCN2_0
+ 		struct pp_smu_funcs_nv nv_funcs;
+ #endif
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++		struct pp_smu_funcs_rn rn_funcs;
++#endif
+ 
+ 	};
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3635-drm-amd-display-Add-Renoir-irq_services.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3635-drm-amd-display-Add-Renoir-irq_services.patch
new file mode 100644
index 00000000..c772892a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3635-drm-amd-display-Add-Renoir-irq_services.patch
@@ -0,0 +1,457 @@
+From bfff02069b9e5724ff69b2edba3bee7fe56a9643 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 25 Jul 2019 16:00:15 -0400
+Subject: [PATCH 3635/4256] drm/amd/display: Add Renoir irq_services
+
+Provides the interface to configure display interrrupts on renoir.
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/irq/Makefile   |  10 +
+ .../display/dc/irq/dcn21/irq_service_dcn21.c  | 372 ++++++++++++++++++
+ .../display/dc/irq/dcn21/irq_service_dcn21.h  |  34 ++
+ 3 files changed, 416 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile
+index ad87c2f093e2..ea75420fc876 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
+@@ -77,3 +77,13 @@ AMD_DAL_IRQ_DCN2 = $(addprefix $(AMDDALPATH)/dc/irq/dcn20/,$(IRQ_DCN2))
+ 
+ AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN2)
+ endif
++###############################################################################
++# DCN 21
++###############################################################################
++ifdef CONFIG_DRM_AMD_DC_DCN2_1
++IRQ_DCN21 = irq_service_dcn21.o
++
++AMD_DAL_IRQ_DCN21= $(addprefix $(AMDDALPATH)/dc/irq/dcn21/,$(IRQ_DCN21))
++
++AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN21)
++endif
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
+new file mode 100644
+index 000000000000..2794c0598f1e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
+@@ -0,0 +1,372 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "dm_services.h"
++
++#include "include/logger_interface.h"
++
++#include "../dce110/irq_service_dce110.h"
++
++#include "dcn/dcn_2_1_0_offset.h"
++#include "dcn/dcn_2_1_0_sh_mask.h"
++#include "renoir_ip_offset.h"
++
++
++#include "irq_service_dcn21.h"
++
++#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
++
++enum dc_irq_source to_dal_irq_source_dcn21(
++		struct irq_service *irq_service,
++		uint32_t src_id,
++		uint32_t ext_id)
++{
++	switch (src_id) {
++	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
++		return DC_IRQ_SOURCE_VBLANK1;
++	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
++		return DC_IRQ_SOURCE_VBLANK2;
++	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
++		return DC_IRQ_SOURCE_VBLANK3;
++	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
++		return DC_IRQ_SOURCE_VBLANK4;
++	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
++		return DC_IRQ_SOURCE_VBLANK5;
++	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
++		return DC_IRQ_SOURCE_VBLANK6;
++	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
++		return DC_IRQ_SOURCE_PFLIP1;
++	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
++		return DC_IRQ_SOURCE_PFLIP2;
++	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
++		return DC_IRQ_SOURCE_PFLIP3;
++	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
++		return DC_IRQ_SOURCE_PFLIP4;
++	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
++		return DC_IRQ_SOURCE_PFLIP5;
++	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
++		return DC_IRQ_SOURCE_PFLIP6;
++	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
++		return DC_IRQ_SOURCE_VUPDATE1;
++	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
++		return DC_IRQ_SOURCE_VUPDATE2;
++	case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
++		return DC_IRQ_SOURCE_VUPDATE3;
++	case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
++		return DC_IRQ_SOURCE_VUPDATE4;
++	case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
++		return DC_IRQ_SOURCE_VUPDATE5;
++	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
++		return DC_IRQ_SOURCE_VUPDATE6;
++
++	case DCN_1_0__SRCID__DC_HPD1_INT:
++		/* generic src_id for all HPD and HPDRX interrupts */
++		switch (ext_id) {
++		case DCN_1_0__CTXID__DC_HPD1_INT:
++			return DC_IRQ_SOURCE_HPD1;
++		case DCN_1_0__CTXID__DC_HPD2_INT:
++			return DC_IRQ_SOURCE_HPD2;
++		case DCN_1_0__CTXID__DC_HPD3_INT:
++			return DC_IRQ_SOURCE_HPD3;
++		case DCN_1_0__CTXID__DC_HPD4_INT:
++			return DC_IRQ_SOURCE_HPD4;
++		case DCN_1_0__CTXID__DC_HPD5_INT:
++			return DC_IRQ_SOURCE_HPD5;
++		case DCN_1_0__CTXID__DC_HPD6_INT:
++			return DC_IRQ_SOURCE_HPD6;
++		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
++			return DC_IRQ_SOURCE_HPD1RX;
++		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
++			return DC_IRQ_SOURCE_HPD2RX;
++		case DCN_1_0__CTXID__DC_HPD3_RX_INT:
++			return DC_IRQ_SOURCE_HPD3RX;
++		case DCN_1_0__CTXID__DC_HPD4_RX_INT:
++			return DC_IRQ_SOURCE_HPD4RX;
++		case DCN_1_0__CTXID__DC_HPD5_RX_INT:
++			return DC_IRQ_SOURCE_HPD5RX;
++		case DCN_1_0__CTXID__DC_HPD6_RX_INT:
++			return DC_IRQ_SOURCE_HPD6RX;
++		default:
++			return DC_IRQ_SOURCE_INVALID;
++		}
++		break;
++
++	default:
++		break;
++	}
++	return DC_IRQ_SOURCE_INVALID;
++}
++
++static bool hpd_ack(
++	struct irq_service *irq_service,
++	const struct irq_source_info *info)
++{
++	uint32_t addr = info->status_reg;
++	uint32_t value = dm_read_reg(irq_service->ctx, addr);
++	uint32_t current_status =
++		get_reg_field_value(
++			value,
++			HPD0_DC_HPD_INT_STATUS,
++			DC_HPD_SENSE_DELAYED);
++
++	dal_irq_service_ack_generic(irq_service, info);
++
++	value = dm_read_reg(irq_service->ctx, info->enable_reg);
++
++	set_reg_field_value(
++		value,
++		current_status ? 0 : 1,
++		HPD0_DC_HPD_INT_CONTROL,
++		DC_HPD_INT_POLARITY);
++
++	dm_write_reg(irq_service->ctx, info->enable_reg, value);
++
++	return true;
++}
++
++static const struct irq_source_info_funcs hpd_irq_info_funcs = {
++	.set = NULL,
++	.ack = hpd_ack
++};
++
++static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
++	.set = NULL,
++	.ack = NULL
++};
++
++static const struct irq_source_info_funcs pflip_irq_info_funcs = {
++	.set = NULL,
++	.ack = NULL
++};
++
++static const struct irq_source_info_funcs vblank_irq_info_funcs = {
++	.set = NULL,
++	.ack = NULL
++};
++
++#undef BASE_INNER
++#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
++
++/* compile time expand base address. */
++#define BASE(seg) \
++	BASE_INNER(seg)
++
++
++#define SRI(reg_name, block, id)\
++	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
++			mm ## block ## id ## _ ## reg_name
++
++
++#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
++	.enable_reg = SRI(reg1, block, reg_num),\
++	.enable_mask = \
++		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
++	.enable_value = {\
++		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
++		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
++	},\
++	.ack_reg = SRI(reg2, block, reg_num),\
++	.ack_mask = \
++		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
++	.ack_value = \
++		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
++
++
++
++#define hpd_int_entry(reg_num)\
++	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
++		IRQ_REG_ENTRY(HPD, reg_num,\
++			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
++			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
++		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
++		.funcs = &hpd_irq_info_funcs\
++	}
++
++#define hpd_rx_int_entry(reg_num)\
++	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
++		IRQ_REG_ENTRY(HPD, reg_num,\
++			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
++			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
++		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
++		.funcs = &hpd_rx_irq_info_funcs\
++	}
++#define pflip_int_entry(reg_num)\
++	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
++		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
++			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
++			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
++		.funcs = &pflip_irq_info_funcs\
++	}
++
++#define vupdate_int_entry(reg_num)\
++	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
++		IRQ_REG_ENTRY(OTG, reg_num,\
++			OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
++			OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
++		.funcs = &vblank_irq_info_funcs\
++	}
++
++#define vblank_int_entry(reg_num)\
++	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
++		IRQ_REG_ENTRY(OTG, reg_num,\
++			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
++			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
++		.funcs = &vblank_irq_info_funcs\
++	}
++
++#define dummy_irq_entry() \
++	{\
++		.funcs = &dummy_irq_info_funcs\
++	}
++
++#define i2c_int_entry(reg_num) \
++	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
++
++#define dp_sink_int_entry(reg_num) \
++	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
++
++#define gpio_pad_int_entry(reg_num) \
++	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
++
++#define dc_underflow_int_entry(reg_num) \
++	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
++
++static const struct irq_source_info_funcs dummy_irq_info_funcs = {
++	.set = dal_irq_service_dummy_set,
++	.ack = dal_irq_service_dummy_ack
++};
++
++static const struct irq_source_info
++irq_source_info_dcn21[DAL_IRQ_SOURCES_NUMBER] = {
++	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
++	hpd_int_entry(0),
++	hpd_int_entry(1),
++	hpd_int_entry(2),
++	hpd_int_entry(3),
++	hpd_int_entry(4),
++	hpd_rx_int_entry(0),
++	hpd_rx_int_entry(1),
++	hpd_rx_int_entry(2),
++	hpd_rx_int_entry(3),
++	hpd_rx_int_entry(4),
++	i2c_int_entry(1),
++	i2c_int_entry(2),
++	i2c_int_entry(3),
++	i2c_int_entry(4),
++	i2c_int_entry(5),
++	i2c_int_entry(6),
++	dp_sink_int_entry(1),
++	dp_sink_int_entry(2),
++	dp_sink_int_entry(3),
++	dp_sink_int_entry(4),
++	dp_sink_int_entry(5),
++	dp_sink_int_entry(6),
++	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
++	pflip_int_entry(0),
++	pflip_int_entry(1),
++	pflip_int_entry(2),
++	pflip_int_entry(3),
++	[DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
++	[DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
++	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
++	gpio_pad_int_entry(0),
++	gpio_pad_int_entry(1),
++	gpio_pad_int_entry(2),
++	gpio_pad_int_entry(3),
++	gpio_pad_int_entry(4),
++	gpio_pad_int_entry(5),
++	gpio_pad_int_entry(6),
++	gpio_pad_int_entry(7),
++	gpio_pad_int_entry(8),
++	gpio_pad_int_entry(9),
++	gpio_pad_int_entry(10),
++	gpio_pad_int_entry(11),
++	gpio_pad_int_entry(12),
++	gpio_pad_int_entry(13),
++	gpio_pad_int_entry(14),
++	gpio_pad_int_entry(15),
++	gpio_pad_int_entry(16),
++	gpio_pad_int_entry(17),
++	gpio_pad_int_entry(18),
++	gpio_pad_int_entry(19),
++	gpio_pad_int_entry(20),
++	gpio_pad_int_entry(21),
++	gpio_pad_int_entry(22),
++	gpio_pad_int_entry(23),
++	gpio_pad_int_entry(24),
++	gpio_pad_int_entry(25),
++	gpio_pad_int_entry(26),
++	gpio_pad_int_entry(27),
++	gpio_pad_int_entry(28),
++	gpio_pad_int_entry(29),
++	gpio_pad_int_entry(30),
++	dc_underflow_int_entry(1),
++	dc_underflow_int_entry(2),
++	dc_underflow_int_entry(3),
++	dc_underflow_int_entry(4),
++	dc_underflow_int_entry(5),
++	dc_underflow_int_entry(6),
++	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
++	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
++	vupdate_int_entry(0),
++	vupdate_int_entry(1),
++	vupdate_int_entry(2),
++	vupdate_int_entry(3),
++	vupdate_int_entry(4),
++	vupdate_int_entry(5),
++	vblank_int_entry(0),
++	vblank_int_entry(1),
++	vblank_int_entry(2),
++	vblank_int_entry(3),
++	vblank_int_entry(4),
++	vblank_int_entry(5),
++};
++
++static const struct irq_service_funcs irq_service_funcs_dcn21 = {
++		.to_dal_irq_source = to_dal_irq_source_dcn21
++};
++
++static void construct(
++	struct irq_service *irq_service,
++	struct irq_service_init_data *init_data)
++{
++	dal_irq_service_construct(irq_service, init_data);
++
++	irq_service->info = irq_source_info_dcn21;
++	irq_service->funcs = &irq_service_funcs_dcn21;
++}
++
++struct irq_service *dal_irq_service_dcn21_create(
++	struct irq_service_init_data *init_data)
++{
++	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
++						  GFP_KERNEL);
++
++	if (!irq_service)
++		return NULL;
++
++	construct(irq_service, init_data);
++	return irq_service;
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h
+new file mode 100644
+index 000000000000..da2bd0e93d7a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h
+@@ -0,0 +1,34 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DAL_IRQ_SERVICE_DCN21_H__
++#define __DAL_IRQ_SERVICE_DCN21_H__
++
++#include "../irq_service.h"
++
++struct irq_service *dal_irq_service_dcn21_create(
++	struct irq_service_init_data *init_data);
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3636-drm-amd-display-Add-hubp-block-for-Renoir-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3636-drm-amd-display-Add-hubp-block-for-Renoir-v2.patch
new file mode 100644
index 00000000..788180f4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3636-drm-amd-display-Add-hubp-block-for-Renoir-v2.patch
@@ -0,0 +1,429 @@
+From c41288f75ad59393c15d6894277b83be90e782f6 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 25 Jul 2019 16:19:17 -0400
+Subject: [PATCH 3636/4256] drm/amd/display: Add hubp block for Renoir (v2)
+
+This provides the interface to memory for the display hw.
+
+v2: minor cleanup (Alex)
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/Makefile |  10 +
+ .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 244 ++++++++++++++++++
+ .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h | 133 ++++++++++
+ 3 files changed, 387 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+new file mode 100644
+index 000000000000..d43f866930be
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+@@ -0,0 +1,10 @@
++#
++# Makefile for DCN21.
++
++DCN21 = dcn21_hubp.o
++
++CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
++
++AMD_DAL_DCN21 = $(addprefix $(AMDDALPATH)/dc/dcn21/,$(DCN21))
++
++AMD_DISPLAY_FILES += $(AMD_DAL_DCN21)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+new file mode 100644
+index 000000000000..a00af513aa2b
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+@@ -0,0 +1,244 @@
++/*
++* Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++#include "dcn21_hubp.h"
++
++#include "dm_services.h"
++#include "reg_helper.h"
++
++#define REG(reg)\
++	hubp21->hubp_regs->reg
++
++#define CTX \
++	hubp21->base.ctx
++
++#undef FN
++#define FN(reg_name, field_name) \
++	hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name
++
++/*
++ * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL.
++ * As a result, if S/W updates any of these registers during a mode change,
++ * the current frame before the mode change will use the new value right away
++ * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior.
++ *
++ * REFCYC_PER_VM_GROUP_FLIP[22:0]
++ * REFCYC_PER_VM_GROUP_VBLANK[22:0]
++ * REFCYC_PER_VM_REQ_FLIP[22:0]
++ * REFCYC_PER_VM_REQ_VBLANK[22:0]
++ *
++ * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated
++ * when flipping to a new surface
++ *
++ * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated
++ * during prefetch  period of a frame. The prefetch starts at a pre-determined
++ * number of lines before the display active per frame
++ *
++ * DCN may underflow due to incorrectly programming these registers
++ * during VM stage of prefetch/iflip. First lines of display active
++ * or a sub-region of active using a new surface will be corrupted
++ * until the VM data returns at flip/mode change transitions
++ *
++ * Work around:
++ * workaround is always opt to use the more aggressive settings.
++ * On any mode switch, if the new reg values are smaller than the current values,
++ * then update the regs with the new values.
++ *
++ * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142
++ *
++ */
++void apply_DEDCN21_142_wa_for_hostvm_deadline(
++		struct hubp *hubp,
++		struct _vcs_dpi_display_dlg_regs_st *dlg_attr)
++{
++	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
++	uint32_t cur_value;
++
++	REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value);
++	if (cur_value > dlg_attr->refcyc_per_vm_group_vblank)
++		REG_SET(VBLANK_PARAMETERS_5, 0,
++				REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank);
++
++	REG_GET(VBLANK_PARAMETERS_6,
++			REFCYC_PER_VM_REQ_VBLANK,
++			&cur_value);
++	if (cur_value > dlg_attr->refcyc_per_vm_req_vblank)
++		REG_SET(VBLANK_PARAMETERS_6, 0,
++				REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank);
++
++	REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value);
++	if (cur_value > dlg_attr->refcyc_per_vm_group_flip)
++		REG_SET(FLIP_PARAMETERS_3, 0,
++				REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip);
++
++	REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value);
++	if (cur_value > dlg_attr->refcyc_per_vm_req_flip)
++		REG_SET(FLIP_PARAMETERS_4, 0,
++					REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip);
++
++	REG_SET(FLIP_PARAMETERS_5, 0,
++			REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c);
++	REG_SET(FLIP_PARAMETERS_6, 0,
++			REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c);
++}
++
++void hubp21_program_deadline(
++		struct hubp *hubp,
++		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
++		struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
++{
++	hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
++
++	apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr);
++}
++
++void hubp21_program_requestor(
++		struct hubp *hubp,
++		struct _vcs_dpi_display_rq_regs_st *rq_regs)
++{
++	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
++
++	REG_UPDATE(HUBPRET_CONTROL,
++			DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
++	REG_SET_4(DCN_EXPANSION_MODE, 0,
++			DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
++			PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
++			MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
++			CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
++	REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
++		CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
++		MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
++		META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
++		MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
++		DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
++		VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
++		SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
++		PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
++	REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0,
++		CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
++		MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
++		META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
++		MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
++		DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
++		SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
++		PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
++}
++
++static void hubp21_setup(
++		struct hubp *hubp,
++		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
++		struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
++		struct _vcs_dpi_display_rq_regs_st *rq_regs,
++		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
++{
++	/* otg is locked when this func is called. Register are double buffered.
++	 * disable the requestors is not needed
++	 */
++
++	hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
++	hubp21_program_requestor(hubp, rq_regs);
++	hubp21_program_deadline(hubp, dlg_attr, ttu_attr);
++
++}
++
++void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,
++		struct vm_system_aperture_param *apt)
++{
++	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
++
++	PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
++	PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
++	PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
++
++	// The format of default addr is 48:12 of the 48 bit addr
++	mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
++
++	// The format of high/low are 48:18 of the 48 bit addr
++	mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
++	mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
++
++	REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
++			MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
++
++	REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
++			MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
++
++	REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
++			ENABLE_L1_TLB, 1,
++			SYSTEM_ACCESS_MODE, 0x3);
++}
++
++void hubp21_init(struct hubp *hubp)
++{
++	// DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta
++	// This is a chicken bit to enable the ECO fix.
++
++	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
++	//hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1;
++	REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
++}
++static struct hubp_funcs dcn21_hubp_funcs = {
++	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
++	.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
++	.hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr,
++	.hubp_program_surface_config = hubp2_program_surface_config,
++	.hubp_is_flip_pending = hubp1_is_flip_pending,
++	.hubp_setup = hubp21_setup,
++	.hubp_setup_interdependent = hubp2_setup_interdependent,
++	.hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings,
++	.set_blank = hubp1_set_blank,
++	.dcc_control = hubp1_dcc_control,
++	.mem_program_viewport = min_set_viewport,
++	.set_cursor_attributes	= hubp2_cursor_set_attributes,
++	.set_cursor_position	= hubp1_cursor_set_position,
++	.hubp_clk_cntl = hubp1_clk_cntl,
++	.hubp_vtg_sel = hubp1_vtg_sel,
++	.dmdata_set_attributes = hubp2_dmdata_set_attributes,
++	.dmdata_load = hubp2_dmdata_load,
++	.dmdata_status_done = hubp2_dmdata_status_done,
++	.hubp_read_state = hubp1_read_state,
++	.hubp_clear_underflow = hubp1_clear_underflow,
++	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
++	.hubp_init = hubp21_init,
++};
++
++bool hubp21_construct(
++	struct dcn21_hubp *hubp21,
++	struct dc_context *ctx,
++	uint32_t inst,
++	const struct dcn_hubp2_registers *hubp_regs,
++	const struct dcn_hubp2_shift *hubp_shift,
++	const struct dcn_hubp2_mask *hubp_mask)
++{
++	hubp21->base.funcs = &dcn21_hubp_funcs;
++	hubp21->base.ctx = ctx;
++	hubp21->hubp_regs = hubp_regs;
++	hubp21->hubp_shift = hubp_shift;
++	hubp21->hubp_mask = hubp_mask;
++	hubp21->base.inst = inst;
++	hubp21->base.opp_id = OPP_ID_INVALID;
++	hubp21->base.mpcc_id = 0xf;
++
++	return true;
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h
+new file mode 100644
+index 000000000000..aeda719a2a13
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h
+@@ -0,0 +1,133 @@
++/*
++* Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef DAL_DC_DCN21_DCN21_HUBP_H_
++#define DAL_DC_DCN21_DCN21_HUBP_H_
++
++#include "../dcn20/dcn20_hubp.h"
++#include "../dcn10/dcn10_hubp.h"
++
++#define TO_DCN21_HUBP(hubp)\
++	container_of(hubp, struct dcn21_hubp, base)
++
++#define HUBP_REG_LIST_DCN21(id)\
++	HUBP_REG_LIST_DCN2_COMMON(id),\
++	SRI(FLIP_PARAMETERS_3, HUBPREQ, id),\
++	SRI(FLIP_PARAMETERS_4, HUBPREQ, id),\
++	SRI(FLIP_PARAMETERS_5, HUBPREQ, id),\
++	SRI(FLIP_PARAMETERS_6, HUBPREQ, id),\
++	SRI(VBLANK_PARAMETERS_5, HUBPREQ, id),\
++	SRI(VBLANK_PARAMETERS_6, HUBPREQ, id)
++
++#define HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh)\
++	HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\
++	HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
++	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
++	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
++	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\
++	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\
++	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
++	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\
++	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\
++	HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
++	HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
++	HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
++	HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
++	HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
++	HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
++	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
++	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
++	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
++	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
++	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
++	HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
++	HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
++	HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
++	HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
++	HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
++	HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \
++	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
++	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \
++	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \
++	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
++	HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \
++	HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \
++	HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \
++	HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \
++	HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \
++	HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \
++	HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\
++	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\
++	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\
++	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\
++	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\
++	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
++	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\
++	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\
++	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\
++	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
++	HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
++	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, mask_sh),\
++	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, mask_sh),\
++	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_5, REFCYC_PER_PTE_GROUP_FLIP_C, mask_sh),\
++	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\
++	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\
++	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\
++	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh)
++
++#define HUBP_MASK_SH_LIST_DCN21(mask_sh)\
++	HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh),\
++	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh)
++
++
++struct dcn21_hubp {
++	struct hubp base;
++	struct dcn_hubp_state state;
++	const struct dcn_hubp2_registers *hubp_regs;
++	const struct dcn_hubp2_shift *hubp_shift;
++	const struct dcn_hubp2_mask *hubp_mask;
++};
++
++bool hubp21_construct(
++	struct dcn21_hubp *hubp21,
++	struct dc_context *ctx,
++	uint32_t inst,
++	const struct dcn_hubp2_registers *hubp_regs,
++	const struct dcn_hubp2_shift *hubp_shift,
++	const struct dcn_hubp2_mask *hubp_mask);
++
++void apply_DEDCN21_142_wa_for_hostvm_deadline(
++		struct hubp *hubp,
++		struct _vcs_dpi_display_dlg_regs_st *dlg_attr);
++
++void hubp21_program_deadline(
++		struct hubp *hubp,
++		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
++		struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
++
++void hubp21_program_requestor(
++		struct hubp *hubp,
++		struct _vcs_dpi_display_rq_regs_st *rq_regs);
++#endif /* DAL_DC_DCN21_DCN21_HUBP_H_ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3637-drm-amd-display-Add-Renoir-hubbub-registers-list.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3637-drm-amd-display-Add-Renoir-hubbub-registers-list.patch
new file mode 100644
index 00000000..2510309a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3637-drm-amd-display-Add-Renoir-hubbub-registers-list.patch
@@ -0,0 +1,204 @@
+From 672c8be27830ad644001ced55606725784bbdb15 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 28 Aug 2019 10:22:02 -0500
+Subject: [PATCH 3637/4256] drm/amd/display: Add Renoir hubbub registers list
+
+These are the registers used to program the hubbub hw.
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/display/dc/dcn10/dcn10_hubbub.h   | 73 +++++++++++++++++++
+ .../drm/amd/display/dc/dcn20/dcn20_hubbub.h   | 10 +++
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 35 +++++++++
+ 3 files changed, 118 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+index c8ae3023fda2..69d903d68661 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+@@ -121,6 +121,26 @@ struct dcn_hubbub_registers {
+ 	uint32_t DCN_VM_AGP_BASE;
+ 	uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
+ 	uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;
++	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;
++	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;
++	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;
++	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;
++	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;
++	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;
++	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;
++	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;
++	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;
++	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;
++	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;
++	uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;
++	uint32_t DCHVM_CTRL0;
++	uint32_t DCHVM_MEM_CTRL;
++	uint32_t DCHVM_CLK_CTRL;
++	uint32_t DCHVM_RIOMMU_CTRL0;
++	uint32_t DCHVM_RIOMMU_STAT0;
++#endif
+ };
+ 
+ /* set field name */
+@@ -212,15 +232,68 @@ struct dcn_hubbub_registers {
+ 		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;\
+ 		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++#define HUBBUB_HVM_REG_FIELD_LIST(type) \
++		type DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD;\
++		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A;\
++		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B;\
++		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C;\
++		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D;\
++		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A;\
++		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B;\
++		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C;\
++		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D;\
++		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A;\
++		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B;\
++		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C;\
++		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D;\
++		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\
++		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\
++		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\
++		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\
++		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;\
++		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;\
++		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;\
++		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;\
++		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;\
++		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;\
++		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;\
++		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;\
++		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;\
++		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;\
++		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;\
++		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;\
++		type DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD;\
++		type HOSTVM_INIT_REQ; \
++		type HVM_GPUVMRET_PWR_REQ_DIS; \
++		type HVM_GPUVMRET_FORCE_REQ; \
++		type HVM_GPUVMRET_POWER_STATUS; \
++		type HVM_DISPCLK_R_GATE_DIS; \
++		type HVM_DISPCLK_G_GATE_DIS; \
++		type HVM_DCFCLK_R_GATE_DIS; \
++		type HVM_DCFCLK_G_GATE_DIS; \
++		type TR_REQ_REQCLKREQ_MODE; \
++		type TW_RSP_COMPCLKREQ_MODE; \
++		type HOSTVM_PREFETCH_REQ; \
++		type HOSTVM_POWERSTATUS; \
++		type RIOMMU_ACTIVE; \
++		type HOSTVM_PREFETCH_DONE
++#endif
+ 
+ struct dcn_hubbub_shift {
+ 	DCN_HUBBUB_REG_FIELD_LIST(uint8_t);
+ 	HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	HUBBUB_HVM_REG_FIELD_LIST(uint8_t);
++#endif
+ };
+ 
+ struct dcn_hubbub_mask {
+ 	DCN_HUBBUB_REG_FIELD_LIST(uint32_t);
+ 	HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	HUBBUB_HVM_REG_FIELD_LIST(uint32_t);
++#endif
+ };
+ 
+ struct dc;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
+index 0d0caa6de935..626117d3b4e9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
+@@ -29,6 +29,16 @@
+ #include "dcn10/dcn10_hubbub.h"
+ #include "dcn20_vmid.h"
+ 
++#define HUBBUB_REG_LIST_DCN20_COMMON()\
++	HUBBUB_REG_LIST_DCN_COMMON(), \
++	SR(DCHUBBUB_CRC_CTRL), \
++	SR(DCN_VM_FB_LOCATION_BASE),\
++	SR(DCN_VM_FB_LOCATION_TOP),\
++	SR(DCN_VM_FB_OFFSET),\
++	SR(DCN_VM_AGP_BOT),\
++	SR(DCN_VM_AGP_TOP),\
++	SR(DCN_VM_AGP_BASE)
++
+ #define TO_DCN20_HUBBUB(hubbub)\
+ 	container_of(hubbub, struct dcn20_hubbub, base)
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+index c4ed8f1b9424..d5c8615af45e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+@@ -148,6 +148,17 @@
+ 	uint32_t VMID_SETTINGS_0
+ 
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++#define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \
++	DCN2_HUBP_REG_COMMON_VARIABLE_LIST; \
++	uint32_t FLIP_PARAMETERS_3;\
++	uint32_t FLIP_PARAMETERS_4;\
++	uint32_t FLIP_PARAMETERS_5;\
++	uint32_t FLIP_PARAMETERS_6;\
++	uint32_t VBLANK_PARAMETERS_5;\
++	uint32_t VBLANK_PARAMETERS_6
++#endif
++
+ #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
+ 	DCN_HUBP_REG_FIELD_BASE_LIST(type); \
+ 	type DMDATA_ADDRESS_HIGH;\
+@@ -173,17 +184,41 @@
+ 	type SURFACE_TRIPLE_BUFFER_ENABLE;\
+ 	type VMID
+ 
++#ifdef CONFIG_DRM_AMD_DC_DCN2_1
++#define DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type) \
++	DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type);\
++	type REFCYC_PER_VM_GROUP_FLIP;\
++	type REFCYC_PER_VM_REQ_FLIP;\
++	type REFCYC_PER_VM_GROUP_VBLANK;\
++	type REFCYC_PER_VM_REQ_VBLANK;\
++	type REFCYC_PER_PTE_GROUP_FLIP_C; \
++	type REFCYC_PER_META_CHUNK_FLIP_C; \
++	type VM_GROUP_SIZE
++#endif
++
+ 
+ struct dcn_hubp2_registers {
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	DCN21_HUBP_REG_COMMON_VARIABLE_LIST;
++#else
+ 	DCN2_HUBP_REG_COMMON_VARIABLE_LIST;
++#endif
+ };
+ 
+ struct dcn_hubp2_shift {
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
++#else
+ 	DCN2_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
++#endif
+ };
+ 
+ struct dcn_hubp2_mask {
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
++#else
+ 	DCN2_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
++#endif
+ };
+ 
+ struct dcn20_hubp {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3638-drm-amd-display-Add-Renoir-Hubbub-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3638-drm-amd-display-Add-Renoir-Hubbub-v2.patch
new file mode 100644
index 00000000..f5b8cc56
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3638-drm-amd-display-Add-Renoir-Hubbub-v2.patch
@@ -0,0 +1,775 @@
+From dd880233bc85bb1d8dc42317fd7d909eb0546e50 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 25 Jul 2019 16:31:50 -0400
+Subject: [PATCH 3638/4256] drm/amd/display: Add Renoir Hubbub (v2)
+
+Controls the display hw's interface to memory.
+
+v2: rebase (Alex)
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   2 +-
+ .../drm/amd/display/dc/dcn21/dcn21_hubbub.c   | 595 ++++++++++++++++++
+ .../drm/amd/display/dc/dcn21/dcn21_hubbub.h   | 132 ++++
+ 3 files changed, 728 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+index d43f866930be..32764714e2b0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+@@ -1,7 +1,7 @@
+ #
+ # Makefile for DCN21.
+ 
+-DCN21 = dcn21_hubp.o
++DCN21 = dcn21_hubp.o dcn21_hubbub.o
+ 
+ CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+new file mode 100644
+index 000000000000..d1266741763b
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+@@ -0,0 +1,595 @@
++/*
++* Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++#include "dm_services.h"
++#include "dcn20/dcn20_hubbub.h"
++#include "dcn21_hubbub.h"
++#include "reg_helper.h"
++
++#define REG(reg)\
++	hubbub1->regs->reg
++#define DC_LOGGER \
++	hubbub1->base.ctx->logger
++#define CTX \
++	hubbub1->base.ctx
++
++#undef FN
++#define FN(reg_name, field_name) \
++	hubbub1->shifts->field_name, hubbub1->masks->field_name
++
++#define REG(reg)\
++	hubbub1->regs->reg
++
++#define CTX \
++	hubbub1->base.ctx
++
++#undef FN
++#define FN(reg_name, field_name) \
++	hubbub1->shifts->field_name, hubbub1->masks->field_name
++
++#ifdef NUM_VMID
++#undef NUM_VMID
++#endif
++#define NUM_VMID 1
++
++static uint32_t convert_and_clamp(
++	uint32_t wm_ns,
++	uint32_t refclk_mhz,
++	uint32_t clamp_value)
++{
++	uint32_t ret_val = 0;
++	ret_val = wm_ns * refclk_mhz;
++	ret_val /= 1000;
++
++	if (ret_val > clamp_value)
++		ret_val = clamp_value;
++
++	return ret_val;
++}
++
++void dcn21_dchvm_init(struct hubbub *hubbub)
++{
++	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
++
++	//Init DCHVM block
++	REG_UPDATE(DCHVM_CTRL0, HOSTVM_INIT_REQ, 1);
++
++	//Poll until RIOMMU_ACTIVE = 1
++	//TODO: Figure out interval us and retry count
++	REG_WAIT(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, 1, 5, 100);
++
++	//Reflect the power status of DCHUBBUB
++	REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1);
++
++	//Start rIOMMU prefetching
++	REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1);
++
++	// Enable dynamic clock gating
++	REG_UPDATE_4(DCHVM_CLK_CTRL,
++					HVM_DISPCLK_R_GATE_DIS, 0,
++					HVM_DISPCLK_G_GATE_DIS, 0,
++					HVM_DCFCLK_R_GATE_DIS, 0,
++					HVM_DCFCLK_G_GATE_DIS, 0);
++
++	//Poll until HOSTVM_PREFETCH_DONE = 1
++	//TODO: Figure out interval us and retry count
++	REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);
++}
++
++static int hubbub21_init_dchub(struct hubbub *hubbub,
++		struct dcn_hubbub_phys_addr_config *pa_config)
++{
++	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
++
++	REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
++		FB_BASE, pa_config->system_aperture.fb_base);
++	REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
++			FB_TOP, pa_config->system_aperture.fb_top);
++	REG_SET(DCN_VM_FB_OFFSET, 0,
++			FB_OFFSET, pa_config->system_aperture.fb_offset);
++	REG_SET(DCN_VM_AGP_BOT, 0,
++			AGP_BOT, pa_config->system_aperture.agp_bot);
++	REG_SET(DCN_VM_AGP_TOP, 0,
++			AGP_TOP, pa_config->system_aperture.agp_top);
++	REG_SET(DCN_VM_AGP_BASE, 0,
++			AGP_BASE, pa_config->system_aperture.agp_base);
++
++	dcn21_dchvm_init(hubbub);
++
++	return NUM_VMID;
++}
++
++static void hubbub21_program_urgent_watermarks(
++		struct hubbub *hubbub,
++		struct dcn_watermark_set *watermarks,
++		unsigned int refclk_mhz,
++		bool safe_to_lower)
++{
++	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
++	uint32_t prog_wm_value;
++
++	/* Repeat for water mark set A, B, C and D. */
++	/* clock state A */
++	if (safe_to_lower || watermarks->a.urgent_ns > hubbub1->watermarks.a.urgent_ns) {
++		hubbub1->watermarks.a.urgent_ns = watermarks->a.urgent_ns;
++		prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
++				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value,
++				DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, prog_wm_value);
++
++		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_A calculated =%d\n"
++			"HW register value = 0x%x\n",
++			watermarks->a.urgent_ns, prog_wm_value);
++	}
++
++	/* determine the transfer time for a quantity of data for a particular requestor.*/
++	if (safe_to_lower || watermarks->a.frac_urg_bw_flip
++			> hubbub1->watermarks.a.frac_urg_bw_flip) {
++		hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip;
++
++		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0,
++				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks->a.frac_urg_bw_flip);
++	}
++
++	if (safe_to_lower || watermarks->a.frac_urg_bw_nom
++			> hubbub1->watermarks.a.frac_urg_bw_nom) {
++		hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom;
++
++		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,
++				DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, watermarks->a.frac_urg_bw_nom);
++	}
++
++	/* clock state B */
++	if (safe_to_lower || watermarks->b.urgent_ns > hubbub1->watermarks.b.urgent_ns) {
++		hubbub1->watermarks.b.urgent_ns = watermarks->b.urgent_ns;
++		prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,
++				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value,
++				DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B, prog_wm_value);
++
++		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_B calculated =%d\n"
++			"HW register value = 0x%x\n",
++			watermarks->b.urgent_ns, prog_wm_value);
++	}
++
++	/* determine the transfer time for a quantity of data for a particular requestor.*/
++	if (safe_to_lower || watermarks->a.frac_urg_bw_flip
++			> hubbub1->watermarks.a.frac_urg_bw_flip) {
++		hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip;
++
++		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0,
++				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, watermarks->a.frac_urg_bw_flip);
++	}
++
++	if (safe_to_lower || watermarks->a.frac_urg_bw_nom
++			> hubbub1->watermarks.a.frac_urg_bw_nom) {
++		hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom;
++
++		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0,
++				DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, watermarks->a.frac_urg_bw_nom);
++	}
++
++	/* clock state C */
++	if (safe_to_lower || watermarks->c.urgent_ns > hubbub1->watermarks.c.urgent_ns) {
++		hubbub1->watermarks.c.urgent_ns = watermarks->c.urgent_ns;
++		prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0,
++				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value,
++				DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C, prog_wm_value);
++
++		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_C calculated =%d\n"
++			"HW register value = 0x%x\n",
++			watermarks->c.urgent_ns, prog_wm_value);
++	}
++
++	/* determine the transfer time for a quantity of data for a particular requestor.*/
++	if (safe_to_lower || watermarks->a.frac_urg_bw_flip
++			> hubbub1->watermarks.a.frac_urg_bw_flip) {
++		hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip;
++
++		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0,
++				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, watermarks->a.frac_urg_bw_flip);
++	}
++
++	if (safe_to_lower || watermarks->a.frac_urg_bw_nom
++			> hubbub1->watermarks.a.frac_urg_bw_nom) {
++		hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom;
++
++		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0,
++				DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, watermarks->a.frac_urg_bw_nom);
++	}
++
++	/* clock state D */
++	if (safe_to_lower || watermarks->d.urgent_ns > hubbub1->watermarks.d.urgent_ns) {
++		hubbub1->watermarks.d.urgent_ns = watermarks->d.urgent_ns;
++		prog_wm_value = convert_and_clamp(watermarks->d.urgent_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0,
++				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value,
++				DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D, prog_wm_value);
++
++		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_D calculated =%d\n"
++			"HW register value = 0x%x\n",
++			watermarks->d.urgent_ns, prog_wm_value);
++	}
++
++	/* determine the transfer time for a quantity of data for a particular requestor.*/
++	if (safe_to_lower || watermarks->a.frac_urg_bw_flip
++			> hubbub1->watermarks.a.frac_urg_bw_flip) {
++		hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip;
++
++		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0,
++				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, watermarks->a.frac_urg_bw_flip);
++	}
++
++	if (safe_to_lower || watermarks->a.frac_urg_bw_nom
++			> hubbub1->watermarks.a.frac_urg_bw_nom) {
++		hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom;
++
++		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0,
++				DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, watermarks->a.frac_urg_bw_nom);
++	}
++}
++
++static void hubbub21_program_stutter_watermarks(
++		struct hubbub *hubbub,
++		struct dcn_watermark_set *watermarks,
++		unsigned int refclk_mhz,
++		bool safe_to_lower)
++{
++	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
++	uint32_t prog_wm_value;
++
++	/* clock state A */
++	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns
++			> hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) {
++		hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
++				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns;
++		prog_wm_value = convert_and_clamp(
++				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0,
++				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value,
++				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
++		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
++			"HW register value = 0x%x\n",
++			watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
++	}
++
++	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_ns
++			> hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns) {
++		hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns =
++				watermarks->a.cstate_pstate.cstate_exit_ns;
++		prog_wm_value = convert_and_clamp(
++				watermarks->a.cstate_pstate.cstate_exit_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0,
++				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value,
++				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
++		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n"
++			"HW register value = 0x%x\n",
++			watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
++	}
++
++	/* clock state B */
++	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns
++			> hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) {
++		hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
++				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns;
++		prog_wm_value = convert_and_clamp(
++				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0,
++				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value,
++				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
++		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n"
++			"HW register value = 0x%x\n",
++			watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
++	}
++
++	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_ns
++			> hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns) {
++		hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns =
++				watermarks->b.cstate_pstate.cstate_exit_ns;
++		prog_wm_value = convert_and_clamp(
++				watermarks->b.cstate_pstate.cstate_exit_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0,
++				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value,
++				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
++		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n"
++			"HW register value = 0x%x\n",
++			watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
++	}
++
++	/* clock state C */
++	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns
++			> hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) {
++		hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
++				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns;
++		prog_wm_value = convert_and_clamp(
++				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0,
++				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value,
++				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
++		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_C calculated =%d\n"
++			"HW register value = 0x%x\n",
++			watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
++	}
++
++	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_ns
++			> hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns) {
++		hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns =
++				watermarks->c.cstate_pstate.cstate_exit_ns;
++		prog_wm_value = convert_and_clamp(
++				watermarks->c.cstate_pstate.cstate_exit_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0,
++				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value,
++				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
++		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n"
++			"HW register value = 0x%x\n",
++			watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
++	}
++
++	/* clock state D */
++	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns
++			> hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) {
++		hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
++				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns;
++		prog_wm_value = convert_and_clamp(
++				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0,
++				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value,
++				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
++		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_D calculated =%d\n"
++			"HW register value = 0x%x\n",
++			watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
++	}
++
++	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_ns
++			> hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns) {
++		hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns =
++				watermarks->d.cstate_pstate.cstate_exit_ns;
++		prog_wm_value = convert_and_clamp(
++				watermarks->d.cstate_pstate.cstate_exit_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0,
++				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value,
++				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
++		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n"
++			"HW register value = 0x%x\n",
++			watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
++	}
++}
++
++static void hubbub21_program_pstate_watermarks(
++		struct hubbub *hubbub,
++		struct dcn_watermark_set *watermarks,
++		unsigned int refclk_mhz,
++		bool safe_to_lower)
++{
++	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
++	uint32_t prog_wm_value;
++
++	/* clock state A */
++	if (safe_to_lower || watermarks->a.cstate_pstate.pstate_change_ns
++			> hubbub1->watermarks.a.cstate_pstate.pstate_change_ns) {
++		hubbub1->watermarks.a.cstate_pstate.pstate_change_ns =
++				watermarks->a.cstate_pstate.pstate_change_ns;
++		prog_wm_value = convert_and_clamp(
++				watermarks->a.cstate_pstate.pstate_change_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, 0,
++				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value,
++				DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
++		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
++			"HW register value = 0x%x\n\n",
++			watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
++	}
++
++	/* clock state B */
++	if (safe_to_lower || watermarks->b.cstate_pstate.pstate_change_ns
++			> hubbub1->watermarks.b.cstate_pstate.pstate_change_ns) {
++		hubbub1->watermarks.b.cstate_pstate.pstate_change_ns =
++				watermarks->b.cstate_pstate.pstate_change_ns;
++		prog_wm_value = convert_and_clamp(
++				watermarks->b.cstate_pstate.pstate_change_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, 0,
++				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value,
++				DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
++		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n"
++			"HW register value = 0x%x\n\n",
++			watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
++	}
++
++	/* clock state C */
++	if (safe_to_lower || watermarks->c.cstate_pstate.pstate_change_ns
++			> hubbub1->watermarks.c.cstate_pstate.pstate_change_ns) {
++		hubbub1->watermarks.c.cstate_pstate.pstate_change_ns =
++				watermarks->c.cstate_pstate.pstate_change_ns;
++		prog_wm_value = convert_and_clamp(
++				watermarks->c.cstate_pstate.pstate_change_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, 0,
++				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value,
++				DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
++		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n"
++			"HW register value = 0x%x\n\n",
++			watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
++	}
++
++	/* clock state D */
++	if (safe_to_lower || watermarks->d.cstate_pstate.pstate_change_ns
++			> hubbub1->watermarks.d.cstate_pstate.pstate_change_ns) {
++		hubbub1->watermarks.d.cstate_pstate.pstate_change_ns =
++				watermarks->d.cstate_pstate.pstate_change_ns;
++		prog_wm_value = convert_and_clamp(
++				watermarks->d.cstate_pstate.pstate_change_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, 0,
++				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value,
++				DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
++		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
++			"HW register value = 0x%x\n\n",
++			watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
++	}
++}
++
++void hubbub21_program_watermarks(
++		struct hubbub *hubbub,
++		struct dcn_watermark_set *watermarks,
++		unsigned int refclk_mhz,
++		bool safe_to_lower)
++{
++	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
++
++	hubbub21_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
++	hubbub21_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
++	hubbub21_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
++
++	/*
++	 * The DCHub arbiter has a mechanism to dynamically rate limit the DCHub request stream to the fabric.
++	 * If the memory controller is fully utilized and the DCHub requestors are
++	 * well ahead of their amortized schedule, then it is safe to prevent the next winner
++	 * from being committed and sent to the fabric.
++	 * The utilization of the memory controller is approximated by ensuring that
++	 * the number of outstanding requests is greater than a threshold specified
++	 * by the ARB_MIN_REQ_OUTSTANDING. To determine that the DCHub requestors are well ahead of the amortized schedule,
++	 * the slack of the next winner is compared with the ARB_SAT_LEVEL in DLG RefClk cycles.
++	 *
++	 * TODO: Revisit request limit after figure out right number. request limit for Renoir isn't decided yet, set maximum value (0x1FF)
++	 * to turn off it for now.
++	 */
++	REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
++			DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
++	REG_UPDATE_2(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
++			DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF,
++			DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, 0xA);
++	REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL,
++			DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, 0xF);
++
++	hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
++}
++
++void hubbub21_wm_read_state(struct hubbub *hubbub,
++		struct dcn_hubbub_wm *wm)
++{
++	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
++	struct dcn_hubbub_wm_set *s;
++
++	memset(wm, 0, sizeof(struct dcn_hubbub_wm));
++
++	s = &wm->sets[0];
++	s->wm_set = 0;
++	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A,
++			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, &s->data_urgent);
++
++	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A,
++			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, &s->sr_enter);
++
++	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A,
++			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, &s->sr_exit);
++
++	REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A,
++			 DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, &s->dram_clk_chanage);
++
++	s = &wm->sets[1];
++	s->wm_set = 1;
++	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B,
++			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, &s->data_urgent);
++
++	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B,
++			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, &s->sr_enter);
++
++	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B,
++			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, &s->sr_exit);
++
++	REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B,
++			DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, &s->dram_clk_chanage);
++
++	s = &wm->sets[2];
++	s->wm_set = 2;
++	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C,
++			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, &s->data_urgent);
++
++	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C,
++			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, &s->sr_enter);
++
++	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C,
++			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, &s->sr_exit);
++
++	REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C,
++			DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, &s->dram_clk_chanage);
++
++	s = &wm->sets[3];
++	s->wm_set = 3;
++	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D,
++			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, &s->data_urgent);
++
++	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D,
++			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, &s->sr_enter);
++
++	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D,
++			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, &s->sr_exit);
++
++	REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D,
++			DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, &s->dram_clk_chanage);
++}
++
++
++static const struct hubbub_funcs hubbub21_funcs = {
++	.update_dchub = hubbub2_update_dchub,
++	.init_dchub_sys_ctx = hubbub21_init_dchub,
++	.init_vm_ctx = NULL,
++	.dcc_support_swizzle = hubbub2_dcc_support_swizzle,
++	.dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,
++	.get_dcc_compression_cap = hubbub2_get_dcc_compression_cap,
++	.wm_read_state = hubbub21_wm_read_state,
++	.get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
++	.program_watermarks = hubbub21_program_watermarks,
++};
++
++void hubbub21_construct(struct dcn20_hubbub *hubbub,
++	struct dc_context *ctx,
++	const struct dcn_hubbub_registers *hubbub_regs,
++	const struct dcn_hubbub_shift *hubbub_shift,
++	const struct dcn_hubbub_mask *hubbub_mask)
++{
++	hubbub->base.ctx = ctx;
++
++	hubbub->base.funcs = &hubbub21_funcs;
++
++	hubbub->regs = hubbub_regs;
++	hubbub->shifts = hubbub_shift;
++	hubbub->masks = hubbub_mask;
++
++	hubbub->debug_test_index_pstate = 0xB;
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
+new file mode 100644
+index 000000000000..6ff3cdb89178
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
+@@ -0,0 +1,132 @@
++/*
++* Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++#ifndef DAL_DC_DCN21_DCN21_HUBBUB_H_
++#define DAL_DC_DCN21_DCN21_HUBBUB_H_
++
++#include "dcn20/dcn20_hubbub.h"
++
++#define HUBBUB_HVM_REG_LIST() \
++	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\
++	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\
++	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\
++	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\
++	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\
++	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
++	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
++	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
++	SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
++	SR(DCHVM_CTRL0), \
++	SR(DCHVM_MEM_CTRL), \
++	SR(DCHVM_CLK_CTRL), \
++	SR(DCHVM_RIOMMU_CTRL0), \
++	SR(DCHVM_RIOMMU_STAT0)
++
++#define HUBBUB_REG_LIST_DCN21()\
++	HUBBUB_REG_LIST_DCN_COMMON(), \
++	HUBBUB_SR_WATERMARK_REG_LIST(), \
++	HUBBUB_HVM_REG_LIST(), \
++	SR(DCHUBBUB_CRC_CTRL), \
++	SR(DCN_VM_FB_LOCATION_BASE),\
++	SR(DCN_VM_FB_LOCATION_TOP),\
++	SR(DCN_VM_FB_OFFSET),\
++	SR(DCN_VM_AGP_BOT),\
++	SR(DCN_VM_AGP_TOP),\
++	SR(DCN_VM_AGP_BASE)
++
++#define HUBBUB_MASK_SH_LIST_HVM(mask_sh) \
++	HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, mask_sh), \
++	HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh), \
++	HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh), \
++	HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh), \
++	HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh), \
++	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh), \
++	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh), \
++	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh), \
++	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh), \
++	HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh), \
++	HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh), \
++	HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh), \
++	HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh), \
++	HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh), \
++	HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \
++	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh)
++
++#define HUBBUB_MASK_SH_LIST_DCN21(mask_sh)\
++	HUBBUB_MASK_SH_LIST_HVM(mask_sh),\
++	HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
++	HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
++	HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
++	HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \
++	HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \
++	HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
++	HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
++	HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
++	HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh)
++
++void dcn21_dchvm_init(struct hubbub *hubbub);
++void hubbub21_program_watermarks(
++		struct hubbub *hubbub,
++		struct dcn_watermark_set *watermarks,
++		unsigned int refclk_mhz,
++		bool safe_to_lower);
++
++void hubbub21_wm_read_state(struct hubbub *hubbub,
++		struct dcn_hubbub_wm *wm);
++
++void hubbub21_construct(struct dcn20_hubbub *hubbub,
++	struct dc_context *ctx,
++	const struct dcn_hubbub_registers *hubbub_regs,
++	const struct dcn_hubbub_shift *hubbub_shift,
++	const struct dcn_hubbub_mask *hubbub_mask);
++
++#endif /* DAL_DC_DCN21_DCN21_HUBBUB_H_ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3639-drm-amd-display-Add-Renoir-clock-manager.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3639-drm-amd-display-Add-Renoir-clock-manager.patch
new file mode 100644
index 00000000..8ba38253
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3639-drm-amd-display-Add-Renoir-clock-manager.patch
@@ -0,0 +1,1109 @@
+From 9206f7bf48408ca14dd0bc4709fe302962b104b1 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 26 Jul 2019 16:43:53 -0400
+Subject: [PATCH 3639/4256] drm/amd/display: Add Renoir clock manager
+
+Controls display clocks and interfaces with powerplay for
+clock and power requirements.
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/display/dc/clk_mgr/Makefile   |  10 +
+ .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  |   9 +
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 590 ++++++++++++++++++
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h |  39 ++
+ .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c   | 200 ++++++
+ .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h   |  40 ++
+ .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   | 125 ++++
+ 7 files changed, 1013 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+index 003c27767e9c..b864869cc7e3 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+@@ -85,3 +85,13 @@ AMD_DAL_CLK_MGR_DCN20 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn20/,$(CLK_MGR_DC
+ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN20)
+ endif
+ 
++ifdef CONFIG_DRM_AMD_DC_DCN2_1
++###############################################################################
++# DCN21
++###############################################################################
++CLK_MGR_DCN21 = rn_clk_mgr.o rn_clk_mgr_vbios_smu.o
++
++AMD_DAL_CLK_MGR_DCN21 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn21/,$(CLK_MGR_DCN21))
++
++AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN21)
++endif
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+index 06e73ce45ed0..66277a9a4ec2 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+@@ -35,6 +35,9 @@
+ #include "dcn10/rv1_clk_mgr.h"
+ #include "dcn10/rv2_clk_mgr.h"
+ #include "dcn20/dcn20_clk_mgr.h"
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++#include "dcn21/rn_clk_mgr.h"
++#endif
+ 
+ 
+ int clk_mgr_helper_get_active_display_cnt(
+@@ -115,6 +118,12 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
+ 			rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu);
+ 			break;
+ 		}
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++		if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) {
++			rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
++			break;
++		}
++#endif	/* DCN2_1 */
+ 		break;
+ #endif	/* Family RV */
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+new file mode 100644
+index 000000000000..787f94d815f4
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -0,0 +1,590 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "dccg.h"
++#include "clk_mgr_internal.h"
++
++
++#include "dcn20/dcn20_clk_mgr.h"
++#include "rn_clk_mgr.h"
++
++
++#include "dce100/dce_clk_mgr.h"
++#include "rn_clk_mgr_vbios_smu.h"
++#include "reg_helper.h"
++#include "core_types.h"
++#include "dm_helpers.h"
++
++#include "atomfirmware.h"
++#include "clk/clk_10_0_2_offset.h"
++#include "clk/clk_10_0_2_sh_mask.h"
++#include "renoir_ip_offset.h"
++
++
++/* Constants */
++
++#define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
++
++/* Macros */
++
++#define REG(reg_name) \
++	(CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
++
++void rn_update_clocks(struct clk_mgr *clk_mgr_base,
++			struct dc_state *context,
++			bool safe_to_lower)
++{
++	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
++	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
++	struct dc *dc = clk_mgr_base->ctx->dc;
++	int display_count;
++	bool update_dppclk = false;
++	bool update_dispclk = false;
++	bool enter_display_off = false;
++	bool dpp_clock_lowered = false;
++	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
++
++	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
++
++	if (display_count == 0)
++		enter_display_off = true;
++
++	if (enter_display_off == safe_to_lower) {
++		rn_vbios_smu_set_display_count(clk_mgr, display_count);
++	}
++
++	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
++		clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
++		rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz);
++	}
++
++	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
++		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
++		rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
++	}
++
++	if (should_set_clock(safe_to_lower,
++			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
++		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
++		rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
++	}
++
++	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
++		if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
++			dpp_clock_lowered = true;
++		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
++		update_dppclk = true;
++	}
++
++	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
++		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
++		rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
++
++		update_dispclk = true;
++	}
++
++	if (dpp_clock_lowered) {
++		// if clock is being lowered, increase DTO before lowering refclk
++		dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
++		rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
++	} else {
++		// if clock is being raised, increase refclk before lowering DTO
++		if (update_dppclk || update_dispclk)
++			rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
++		if (update_dppclk)
++			dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
++	}
++
++	if (update_dispclk &&
++			dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
++		/*update dmcu for wait_loop count*/
++		dmcu->funcs->set_psr_wait_loop(dmcu,
++			clk_mgr_base->clks.dispclk_khz / 1000 / 7);
++	}
++}
++
++
++static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
++{
++	/* get FbMult value */
++	struct fixed31_32 pll_req;
++	unsigned int fbmult_frac_val = 0;
++	unsigned int fbmult_int_val = 0;
++
++
++	/*
++	 * Register value of fbmult is in 8.16 format, we are converting to 31.32
++	 * to leverage the fix point operations available in driver
++	 */
++
++	REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
++	REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
++
++	pll_req = dc_fixpt_from_int(fbmult_int_val);
++
++	/*
++	 * since fractional part is only 16 bit in register definition but is 32 bit
++	 * in our fix point definiton, need to shift left by 16 to obtain correct value
++	 */
++	pll_req.value |= fbmult_frac_val << 16;
++
++	/* multiply by REFCLK period */
++	pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
++
++	/* integer part is now VCO frequency in kHz */
++	return dc_fixpt_floor(pll_req);
++}
++
++static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base)
++{
++	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
++
++	internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);
++	internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL);
++
++	internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL);	//dcf deep sleep divider
++	internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS);
++
++	internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);
++	internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL);
++
++	internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);
++	internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL);
++
++	internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);
++	internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL);
++}
++
++/* This function collect raw clk register values */
++static void rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
++		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
++{
++	struct rn_clk_internal internal = {0};
++	char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
++	unsigned int chars_printed = 0;
++	unsigned int remaining_buffer = log_info->bufSize;
++
++	rn_dump_clk_registers_internal(&internal, clk_mgr_base);
++
++	regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
++	regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
++	regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;
++	regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
++	regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
++	regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
++
++	regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
++	if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
++		regs_and_bypass->dppclk_bypass = 0;
++	regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
++	if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
++		regs_and_bypass->dcfclk_bypass = 0;
++	regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
++	if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
++		regs_and_bypass->dispclk_bypass = 0;
++	regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
++	if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
++		regs_and_bypass->dprefclk_bypass = 0;
++
++	if (log_info->enabled) {
++		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
++		remaining_buffer -= chars_printed;
++		*log_info->sum_chars_printed += chars_printed;
++		log_info->pBuf += chars_printed;
++
++		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n",
++			regs_and_bypass->dcfclk,
++			regs_and_bypass->dcf_deep_sleep_divider,
++			regs_and_bypass->dcf_deep_sleep_allow,
++			bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
++		remaining_buffer -= chars_printed;
++		*log_info->sum_chars_printed += chars_printed;
++		log_info->pBuf += chars_printed;
++
++		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n",
++			regs_and_bypass->dprefclk,
++			bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
++		remaining_buffer -= chars_printed;
++		*log_info->sum_chars_printed += chars_printed;
++		log_info->pBuf += chars_printed;
++
++		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
++			regs_and_bypass->dispclk,
++			bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
++		remaining_buffer -= chars_printed;
++		*log_info->sum_chars_printed += chars_printed;
++		log_info->pBuf += chars_printed;
++
++		//split
++		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n");
++		remaining_buffer -= chars_printed;
++		*log_info->sum_chars_printed += chars_printed;
++		log_info->pBuf += chars_printed;
++
++		// REGISTER VALUES
++		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n");
++		remaining_buffer -= chars_printed;
++		*log_info->sum_chars_printed += chars_printed;
++		log_info->pBuf += chars_printed;
++
++		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n",
++				internal.CLK1_CLK3_CURRENT_CNT);
++		remaining_buffer -= chars_printed;
++		*log_info->sum_chars_printed += chars_printed;
++		log_info->pBuf += chars_printed;
++
++		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
++					internal.CLK1_CLK3_DS_CNTL);
++		remaining_buffer -= chars_printed;
++		*log_info->sum_chars_printed += chars_printed;
++		log_info->pBuf += chars_printed;
++
++		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n",
++					internal.CLK1_CLK3_ALLOW_DS);
++		remaining_buffer -= chars_printed;
++		*log_info->sum_chars_printed += chars_printed;
++		log_info->pBuf += chars_printed;
++
++		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n",
++					internal.CLK1_CLK2_CURRENT_CNT);
++		remaining_buffer -= chars_printed;
++		*log_info->sum_chars_printed += chars_printed;
++		log_info->pBuf += chars_printed;
++
++		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
++					internal.CLK1_CLK0_CURRENT_CNT);
++		remaining_buffer -= chars_printed;
++		*log_info->sum_chars_printed += chars_printed;
++		log_info->pBuf += chars_printed;
++
++		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",
++					internal.CLK1_CLK1_CURRENT_CNT);
++		remaining_buffer -= chars_printed;
++		*log_info->sum_chars_printed += chars_printed;
++		log_info->pBuf += chars_printed;
++
++		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n",
++					internal.CLK1_CLK3_BYPASS_CNTL);
++		remaining_buffer -= chars_printed;
++		*log_info->sum_chars_printed += chars_printed;
++		log_info->pBuf += chars_printed;
++
++		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n",
++					internal.CLK1_CLK2_BYPASS_CNTL);
++		remaining_buffer -= chars_printed;
++		*log_info->sum_chars_printed += chars_printed;
++		log_info->pBuf += chars_printed;
++
++		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n",
++					internal.CLK1_CLK0_BYPASS_CNTL);
++		remaining_buffer -= chars_printed;
++		*log_info->sum_chars_printed += chars_printed;
++		log_info->pBuf += chars_printed;
++
++		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n",
++					internal.CLK1_CLK1_BYPASS_CNTL);
++		remaining_buffer -= chars_printed;
++		*log_info->sum_chars_printed += chars_printed;
++		log_info->pBuf += chars_printed;
++	}
++}
++
++/* This function produce translated logical clk state values*/
++void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
++{
++	struct clk_state_registers_and_bypass sb = { 0 };
++	struct clk_log_info log_info = { 0 };
++
++	rn_dump_clk_registers(&sb, clk_mgr_base, &log_info);
++
++	s->dprefclk_khz = sb.dprefclk;
++}
++
++void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
++{
++	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
++
++	rn_vbios_smu_enable_pme_wa(clk_mgr);
++}
++
++static struct clk_mgr_funcs dcn21_funcs = {
++	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
++	.update_clocks = rn_update_clocks,
++	.init_clocks = dcn2_init_clocks,
++	.enable_pme_wa = rn_enable_pme_wa,
++	/* .dump_clk_registers = rn_dump_clk_registers */
++};
++
++struct clk_bw_params rn_bw_params = {
++	.vram_type = Ddr4MemType,
++	.num_channels = 1,
++	.clk_table = {
++		.entries = {
++			{
++				.voltage = 0,
++				.dcfclk_mhz = 400,
++				.fclk_mhz = 400,
++				.memclk_mhz = 800,
++				.socclk_mhz = 0,
++			},
++			{
++				.voltage = 0,
++				.dcfclk_mhz = 483,
++				.fclk_mhz = 800,
++				.memclk_mhz = 1600,
++				.socclk_mhz = 0,
++			},
++			{
++				.voltage = 0,
++				.dcfclk_mhz = 602,
++				.fclk_mhz = 1067,
++				.memclk_mhz = 1067,
++				.socclk_mhz = 0,
++			},
++			{
++				.voltage = 0,
++				.dcfclk_mhz = 738,
++				.fclk_mhz = 1333,
++				.memclk_mhz = 1600,
++				.socclk_mhz = 0,
++			},
++		},
++
++		.num_entries = 4,
++	},
++
++	.wm_table = {
++		.entries = {
++			{
++				.wm_inst = WM_A,
++				.wm_type = WM_TYPE_PSTATE_CHG,
++				.pstate_latency_us = 23.84,
++				.valid = true,
++			},
++			{
++				.wm_inst = WM_B,
++				.wm_type = WM_TYPE_PSTATE_CHG,
++				.pstate_latency_us = 23.84,
++				.valid = true,
++			},
++			{
++				.wm_inst = WM_C,
++				.wm_type = WM_TYPE_PSTATE_CHG,
++				.pstate_latency_us = 23.84,
++				.valid = true,
++			},
++			{
++				.wm_inst = WM_D,
++				.wm_type = WM_TYPE_PSTATE_CHG,
++				.pstate_latency_us = 23.84,
++				.valid = true,
++			},
++		},
++	}
++};
++
++void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
++{
++	int i, num_valid_sets;
++
++	num_valid_sets = 0;
++
++	for (i = 0; i < WM_SET_COUNT; i++) {
++		/* skip empty entries, the smu array has no holes*/
++		if (!bw_params->wm_table.entries[i].valid)
++			continue;
++
++		ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
++		ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;;
++		/* We will not select WM based on dcfclk, so leave it as unconstrained */
++		ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
++		ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++		/* fclk wil be used to select WM*/
++
++		if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) {
++			if (i == 0)
++				ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = 0;
++			else {
++				/* add 1 to make it non-overlapping with next lvl */
++				ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = bw_params->clk_table.entries[i - 1].fclk_mhz + 1;
++			}
++			ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
++
++		} else {
++			/* unconstrained for memory retraining */
++			ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
++			ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++
++			/* Modify previous watermark range to cover up to max */
++			ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++		}
++		num_valid_sets++;
++	}
++
++	ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
++	ranges->num_reader_wm_sets = num_valid_sets;
++
++	/* modify the min and max to make sure we cover the whole range*/
++	ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
++	ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
++	ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++	ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++
++	/* This is for writeback only, does not matter currently as no writeback support*/
++	ranges->num_writer_wm_sets = 1;
++	ranges->writer_wm_sets[0].wm_inst = WM_A;
++	ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
++	ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++	ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
++	ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++
++}
++
++void clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
++{
++	int i;
++
++	ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
++
++	for (i = 0; i < PP_SMU_NUM_FCLK_DPM_LEVELS; i++) {
++		if (clock_table->FClocks[i].Freq == 0)
++			break;
++
++		bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i].Freq;
++		bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[i].Freq;
++		bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[i].Freq;
++		bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i].Freq;
++		bw_params->clk_table.entries[i].voltage = clock_table->FClocks[i].Vol;
++	}
++	bw_params->clk_table.num_entries = i;
++
++	bw_params->vram_type = asic_id->vram_type;
++	bw_params->num_channels = asic_id->vram_width / DDR4_DRAM_WIDTH;
++
++	for (i = 0; i < WM_SET_COUNT; i++) {
++		bw_params->wm_table.entries[i].wm_inst = i;
++
++		if (clock_table->FClocks[i].Freq == 0) {
++			bw_params->wm_table.entries[i].valid = false;
++			continue;
++		}
++
++		bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
++		bw_params->wm_table.entries[i].valid = true;
++	}
++
++	if (bw_params->vram_type == LpDdr4MemType) {
++		/*
++		 * WM set D will be re-purposed for memory retraining
++		 */
++		bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;
++		bw_params->wm_table.entries[WM_D].wm_inst = WM_D;
++		bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
++		bw_params->wm_table.entries[WM_D].valid = true;
++	}
++
++}
++
++void rn_clk_mgr_construct(
++		struct dc_context *ctx,
++		struct clk_mgr_internal *clk_mgr,
++		struct pp_smu_funcs *pp_smu,
++		struct dccg *dccg)
++{
++	struct dc_debug_options *debug = &ctx->dc->debug;
++	struct dpm_clocks clock_table = { 0 };
++	struct clk_state_registers_and_bypass s = { 0 };
++
++	clk_mgr->base.ctx = ctx;
++	clk_mgr->base.funcs = &dcn21_funcs;
++
++	clk_mgr->pp_smu = pp_smu;
++
++	clk_mgr->dccg = dccg;
++	clk_mgr->dfs_bypass_disp_clk = 0;
++
++	clk_mgr->dprefclk_ss_percentage = 0;
++	clk_mgr->dprefclk_ss_divider = 1000;
++	clk_mgr->ss_on_dprefclk = false;
++	clk_mgr->dfs_ref_freq_khz = 48000;
++
++	clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr);
++
++	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
++		dcn21_funcs.update_clocks = dcn2_update_clocks_fpga;
++		clk_mgr->dentist_vco_freq_khz = 3600000;
++		clk_mgr->base.dprefclk_khz = 600000;
++	} else {
++		struct clk_log_info log_info = {0};
++
++		/* TODO: Check we get what we expect during bringup */
++		clk_mgr->dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
++
++		/* in case we don't get a value from the register, use default */
++		if (clk_mgr->dentist_vco_freq_khz == 0)
++			clk_mgr->dentist_vco_freq_khz = 3600000;
++
++		rn_dump_clk_registers(&s, &clk_mgr->base, &log_info);
++		clk_mgr->base.dprefclk_khz = s.dprefclk;
++
++		if (clk_mgr->base.dprefclk_khz != 600000) {
++			clk_mgr->base.dprefclk_khz = 600000;
++			ASSERT(1); //TODO: Renoir follow up.
++		}
++
++		/* in case we don't get a value from the register, use default */
++		if (clk_mgr->base.dprefclk_khz == 0)
++			clk_mgr->base.dprefclk_khz = 600000;
++	}
++
++	dce_clock_read_ss_info(clk_mgr);
++
++	clk_mgr->base.bw_params = &rn_bw_params;
++
++	if (pp_smu) {
++		pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table);
++		clk_mgr_helper_populate_bw_params(clk_mgr->base.bw_params, &clock_table, &ctx->asic_id);
++	}
++
++	/*
++	 * Notify SMU which set of WM should be selected for different ranges of fclk
++	 * On Renoir there is a maximumum of 4 DF pstates supported, could be less
++	 * depending on DDR speed and fused maximum fclk.
++	 */
++	if (!debug->disable_pplib_wm_range) {
++		struct pp_smu_wm_range_sets ranges = {0};
++
++		build_watermark_ranges(clk_mgr->base.bw_params, &ranges);
++
++		/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
++		if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)
++			pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges);
++	}
++
++	/* enable powerfeatures when displaycount goes to 0 */
++	if (!debug->disable_48mhz_pwrdwn)
++		rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr);
++}
++
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
+new file mode 100644
+index 000000000000..aadec06fde10
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
+@@ -0,0 +1,39 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __RN_CLK_MGR_H__
++#define __RN_CLK_MGR_H__
++
++struct rn_clk_registers {
++	uint32_t CLK1_CLK0_CURRENT_CNT; /* DPREFCLK */
++};
++
++
++void rn_clk_mgr_construct(struct dc_context *ctx,
++		struct clk_mgr_internal *clk_mgr,
++		struct pp_smu_funcs *pp_smu,
++		struct dccg *dccg);
++
++#endif //__RN_CLK_MGR_H__
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+new file mode 100644
+index 000000000000..50984c1811bb
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+@@ -0,0 +1,200 @@
++/*
++ * Copyright 2012-16 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "core_types.h"
++#include "clk_mgr_internal.h"
++#include "reg_helper.h"
++
++#include "renoir_ip_offset.h"
++
++#include "mp/mp_12_0_0_offset.h"
++#include "mp/mp_12_0_0_sh_mask.h"
++
++#define REG(reg_name) \
++	(MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
++
++#define FN(reg_name, field) \
++	FD(reg_name##__##field)
++
++#define VBIOSSMC_MSG_TestMessage                  0x1
++#define VBIOSSMC_MSG_GetSmuVersion                0x2
++#define VBIOSSMC_MSG_PowerUpGfx                   0x3
++#define VBIOSSMC_MSG_SetDispclkFreq               0x4
++#define VBIOSSMC_MSG_SetDprefclkFreq              0x5
++#define VBIOSSMC_MSG_PowerDownGfx                 0x6
++#define VBIOSSMC_MSG_SetDppclkFreq                0x7
++#define VBIOSSMC_MSG_SetHardMinDcfclkByFreq       0x8
++#define VBIOSSMC_MSG_SetMinDeepSleepDcfclk        0x9
++#define VBIOSSMC_MSG_SetPhyclkVoltageByFreq       0xA
++#define VBIOSSMC_MSG_GetFclkFrequency             0xB
++#define VBIOSSMC_MSG_SetDisplayCount              0xC
++#define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xD
++#define VBIOSSMC_MSG_UpdatePmeRestore			  0xE
++
++int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param)
++{
++	/* First clear response register */
++	REG_WRITE(MP1_SMN_C2PMSG_91, 0);
++
++	/* Set the parameter register for the SMU message, unit is Mhz */
++	REG_WRITE(MP1_SMN_C2PMSG_83, param);
++
++	/* Trigger the message transaction by writing the message ID */
++	REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
++
++	REG_WAIT(MP1_SMN_C2PMSG_91, CONTENT, 1, 10, 200000);
++
++	/* Actual dispclk set is returned in the parameter register */
++	return REG_READ(MP1_SMN_C2PMSG_83);
++}
++
++int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
++{
++	return rn_vbios_smu_send_msg_with_param(
++			clk_mgr,
++			VBIOSSMC_MSG_GetSmuVersion,
++			0);
++}
++
++
++int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
++{
++	int actual_dispclk_set_mhz = -1;
++	struct dc *core_dc = clk_mgr->base.ctx->dc;
++	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	uint32_t clk = requested_dispclk_khz / 1000;
++
++	if (clk <= 100)
++		clk = 101;
++
++	/*  Unit of SMU msg parameter is Mhz */
++	actual_dispclk_set_mhz = rn_vbios_smu_send_msg_with_param(
++			clk_mgr,
++			VBIOSSMC_MSG_SetDispclkFreq,
++			clk);
++
++	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
++			if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
++				dmcu->funcs->set_psr_wait_loop(dmcu,
++						actual_dispclk_set_mhz / 7);
++		}
++	}
++
++	return actual_dispclk_set_mhz * 1000;
++}
++
++int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
++{
++	int actual_dprefclk_set_mhz = -1;
++
++	actual_dprefclk_set_mhz = rn_vbios_smu_send_msg_with_param(
++			clk_mgr,
++			VBIOSSMC_MSG_SetDprefclkFreq,
++			clk_mgr->base.dprefclk_khz / 1000);
++
++	/* TODO: add code for programing DP DTO, currently this is down by command table */
++
++	return actual_dprefclk_set_mhz * 1000;
++}
++
++int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
++{
++	int actual_dcfclk_set_mhz = -1;
++
++	if (clk_mgr->smu_ver < 0xFFFFFFFF)
++		return actual_dcfclk_set_mhz;
++
++	actual_dcfclk_set_mhz = rn_vbios_smu_send_msg_with_param(
++			clk_mgr,
++			VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
++			requested_dcfclk_khz / 1000);
++
++	return actual_dcfclk_set_mhz * 1000;
++}
++
++int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
++{
++	int actual_min_ds_dcfclk_mhz = -1;
++
++	if (clk_mgr->smu_ver < 0xFFFFFFFF)
++		return actual_min_ds_dcfclk_mhz;
++
++	actual_min_ds_dcfclk_mhz = rn_vbios_smu_send_msg_with_param(
++			clk_mgr,
++			VBIOSSMC_MSG_SetMinDeepSleepDcfclk,
++			requested_min_ds_dcfclk_khz / 1000);
++
++	return actual_min_ds_dcfclk_mhz * 1000;
++}
++
++void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz)
++{
++	rn_vbios_smu_send_msg_with_param(
++			clk_mgr,
++			VBIOSSMC_MSG_SetPhyclkVoltageByFreq,
++			requested_phyclk_khz / 1000);
++}
++
++int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
++{
++	int actual_dppclk_set_mhz = -1;
++
++	uint32_t clk = requested_dpp_khz / 1000;
++
++	if (clk <= 100)
++		clk = 101;
++
++	actual_dppclk_set_mhz = rn_vbios_smu_send_msg_with_param(
++			clk_mgr,
++			VBIOSSMC_MSG_SetDppclkFreq,
++			clk);
++
++	return actual_dppclk_set_mhz * 1000;
++}
++
++void rn_vbios_smu_set_display_count(struct clk_mgr_internal *clk_mgr, int display_count)
++{
++	rn_vbios_smu_send_msg_with_param(
++			clk_mgr,
++			VBIOSSMC_MSG_SetDisplayCount,
++			display_count);
++}
++
++void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr)
++{
++	rn_vbios_smu_send_msg_with_param(
++			clk_mgr,
++			VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown,
++			0);
++}
++
++void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
++{
++	rn_vbios_smu_send_msg_with_param(
++			clk_mgr,
++			VBIOSSMC_MSG_UpdatePmeRestore,
++			0);
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h
+new file mode 100644
+index 000000000000..da3a49487c6d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h
+@@ -0,0 +1,40 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef DAL_DC_RN_CLK_MGR_VBIOS_SMU_H_
++#define DAL_DC_RN_CLK_MGR_VBIOS_SMU_H_
++
++int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
++int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
++int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
++int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
++int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
++void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
++int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
++void rn_vbios_smu_set_display_count(struct clk_mgr_internal *clk_mgr, int display_count);
++void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr);
++void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
++
++#endif /* DAL_DC_DCN10_RV1_CLK_MGR_VBIOS_SMU_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+index 938bdc5c21a1..76f9ad1b23df 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+@@ -31,6 +31,128 @@
+ #define DCN_MINIMUM_DISPCLK_Khz 100000
+ #define DCN_MINIMUM_DPPCLK_Khz 100000
+ 
++#ifdef CONFIG_DRM_AMD_DC_DCN2_1
++/* Constants */
++#define DDR4_DRAM_WIDTH   64
++#define WM_A 0
++#define WM_B 1
++#define WM_C 2
++#define WM_D 3
++#define WM_SET_COUNT 4
++#endif
++
++#define DCN_MINIMUM_DISPCLK_Khz 100000
++#define DCN_MINIMUM_DPPCLK_Khz 100000
++
++#ifdef CONFIG_DRM_AMD_DC_DCN2_1
++/* Will these bw structures be ASIC specific? */
++
++#define MAX_NUM_DPM_LVL		4
++#define WM_SET_COUNT 		4
++
++
++struct clk_limit_table_entry {
++	unsigned int voltage; /* milivolts withh 2 fractional bits */
++	unsigned int dcfclk_mhz;
++	unsigned int fclk_mhz;
++	unsigned int memclk_mhz;
++	unsigned int socclk_mhz;
++};
++
++/* This table is contiguous */
++struct clk_limit_table {
++	struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL];
++	unsigned int num_entries;
++};
++
++struct wm_range_table_entry {
++	unsigned int wm_inst;
++	unsigned int wm_type;
++	double pstate_latency_us;
++	bool valid;
++};
++
++
++struct clk_log_info {
++	bool enabled;
++	char *pBuf;
++	unsigned int bufSize;
++	unsigned int *sum_chars_printed;
++};
++
++struct clk_state_registers_and_bypass {
++	uint32_t dcfclk;
++	uint32_t dcf_deep_sleep_divider;
++	uint32_t dcf_deep_sleep_allow;
++	uint32_t dprefclk;
++	uint32_t dispclk;
++	uint32_t dppclk;
++
++	uint32_t dppclk_bypass;
++	uint32_t dcfclk_bypass;
++	uint32_t dprefclk_bypass;
++	uint32_t dispclk_bypass;
++};
++
++struct rv1_clk_internal {
++	uint32_t CLK0_CLK8_CURRENT_CNT;  //dcfclk
++	uint32_t CLK0_CLK8_DS_CNTL;		 //dcf_deep_sleep_divider
++	uint32_t CLK0_CLK8_ALLOW_DS;	 //dcf_deep_sleep_allow
++	uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
++	uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
++
++	uint32_t CLK0_CLK8_BYPASS_CNTL;  //dcfclk bypass
++	uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass
++	uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass
++};
++
++struct rn_clk_internal {
++	uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
++	uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
++	uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
++	uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
++	uint32_t CLK1_CLK3_DS_CNTL;		//dcf_deep_sleep_divider
++	uint32_t CLK1_CLK3_ALLOW_DS;	//dcf_deep_sleep_allow
++
++	uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
++	uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
++	uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
++	uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
++
++};
++
++/* For dtn logging and debugging */
++struct clk_state_registers {
++		uint32_t CLK0_CLK8_CURRENT_CNT;  //dcfclk
++		uint32_t CLK0_CLK8_DS_CNTL;		 //dcf_deep_sleep_divider
++		uint32_t CLK0_CLK8_ALLOW_DS;	 //dcf_deep_sleep_allow
++		uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
++		uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
++};
++
++/* TODO: combine this with the above */
++struct clk_bypass {
++	uint32_t dcfclk_bypass;
++	uint32_t dispclk_pypass;
++	uint32_t dprefclk_bypass;
++};
++/*
++ * This table is not contiguous, can have holes, each
++ * entry correspond to one set of WM. For example if
++ * we have 2 DPM and LPDDR, we will WM set A, B and
++ * D occupied, C will be emptry.
++ */
++struct wm_table {
++	struct wm_range_table_entry entries[WM_SET_COUNT];
++};
++
++struct clk_bw_params {
++	unsigned int vram_type;
++	unsigned int num_channels;
++	struct clk_limit_table clk_table;
++	struct wm_table wm_table;
++};
++#endif
+ /* Public interfaces */
+ 
+ struct clk_states {
+@@ -65,6 +187,9 @@ struct clk_mgr {
+ 	struct clk_mgr_funcs *funcs;
+ 	struct dc_clocks clks;
+ 	int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
++#ifdef CONFIG_DRM_AMD_DC_DCN2_1
++	struct clk_bw_params *bw_params;
++#endif
+ };
+ 
+ /* forward declarations */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3640-drm-amd-display-Add-Renoir-resource-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3640-drm-amd-display-Add-Renoir-resource-v2.patch
new file mode 100644
index 00000000..ced95ba7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3640-drm-amd-display-Add-Renoir-resource-v2.patch
@@ -0,0 +1,1773 @@
+From 06e43b345c7e2d550aeda2596e35d3a2cc355e50 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 26 Jul 2019 16:46:46 -0400
+Subject: [PATCH 3640/4256] drm/amd/display: Add Renoir resource (v2)
+
+Manages the renoir display resources (crtcs, phys, plls, etc.).
+
+v2: rebase (Alex)
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/Makefile |    2 +-
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 1680 +++++++++++++++++
+ .../drm/amd/display/dc/dcn21/dcn21_resource.h |   45 +
+ 3 files changed, 1726 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+index 32764714e2b0..b2b39090fb57 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+@@ -1,7 +1,7 @@
+ #
+ # Makefile for DCN21.
+ 
+-DCN21 = dcn21_hubp.o dcn21_hubbub.o
++DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o
+ 
+ CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+new file mode 100644
+index 000000000000..3ca5139f1273
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -0,0 +1,1680 @@
++/*
++* Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "dm_services.h"
++#include "dc.h"
++
++#include "resource.h"
++#include "include/irq_service_interface.h"
++#include "dcn20/dcn20_resource.h"
++
++#include "clk_mgr.h"
++#include "dcn10/dcn10_hubp.h"
++#include "dcn10/dcn10_ipp.h"
++#include "dcn20/dcn20_hubbub.h"
++#include "dcn20/dcn20_mpc.h"
++#include "dcn20/dcn20_hubp.h"
++#include "dcn21_hubp.h"
++#include "irq/dcn21/irq_service_dcn21.h"
++#include "dcn20/dcn20_dpp.h"
++#include "dcn20/dcn20_optc.h"
++#include "dcn20/dcn20_hwseq.h"
++#include "dce110/dce110_hw_sequencer.h"
++#include "dcn20/dcn20_opp.h"
++#include "dcn20/dcn20_dsc.h"
++#include "dcn20/dcn20_link_encoder.h"
++#include "dcn20/dcn20_stream_encoder.h"
++#include "dce/dce_clock_source.h"
++#include "dce/dce_audio.h"
++#include "dce/dce_hwseq.h"
++#include "virtual/virtual_stream_encoder.h"
++#include "dce110/dce110_resource.h"
++#include "dml/display_mode_vba.h"
++#include "dcn20/dcn20_dccg.h"
++#include "dcn21_hubbub.h"
++#include "dcn10/dcn10_resource.h"
++
++#include "dcn20/dcn20_dwb.h"
++#include "dcn20/dcn20_mmhubbub.h"
++
++#include "renoir_ip_offset.h"
++#include "dcn/dcn_2_1_0_offset.h"
++#include "dcn/dcn_2_1_0_sh_mask.h"
++
++#include "nbio/nbio_7_0_offset.h"
++
++#include "mmhub/mmhub_2_0_0_offset.h"
++#include "mmhub/mmhub_2_0_0_sh_mask.h"
++
++#include "reg_helper.h"
++#include "dce/dce_abm.h"
++#include "dce/dce_dmcu.h"
++#include "dce/dce_aux.h"
++#include "dce/dce_i2c.h"
++#include "dcn21_resource.h"
++#include "vm_helper.h"
++#include "dcn20/dcn20_vmid.h"
++
++#define SOC_BOUNDING_BOX_VALID false
++#define DC_LOGGER_INIT(logger)
++
++
++struct _vcs_dpi_ip_params_st dcn2_1_ip = {
++	.gpuvm_enable = 0,
++	.hostvm_enable = 0,
++	.gpuvm_max_page_table_levels = 1,
++	.hostvm_max_page_table_levels = 4,
++	.hostvm_cached_page_table_levels = 2,
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	.num_dsc = 3,
++#else
++	.num_dsc = 0,
++#endif
++	.rob_buffer_size_kbytes = 168,
++	.det_buffer_size_kbytes = 164,
++	.dpte_buffer_size_in_pte_reqs_luma = 44,
++	.dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
++	.dpp_output_buffer_pixels = 2560,
++	.opp_output_buffer_lines = 1,
++	.pixel_chunk_size_kbytes = 8,
++	.pte_enable = 1,
++	.max_page_table_levels = 4,
++	.pte_chunk_size_kbytes = 2,
++	.meta_chunk_size_kbytes = 2,
++	.writeback_chunk_size_kbytes = 2,
++	.line_buffer_size_bits = 789504,
++	.is_line_buffer_bpp_fixed = 0,
++	.line_buffer_fixed_bpp = 0,
++	.dcc_supported = true,
++	.max_line_buffer_lines = 12,
++	.writeback_luma_buffer_size_kbytes = 12,
++	.writeback_chroma_buffer_size_kbytes = 8,
++	.writeback_chroma_line_buffer_width_pixels = 4,
++	.writeback_max_hscl_ratio = 1,
++	.writeback_max_vscl_ratio = 1,
++	.writeback_min_hscl_ratio = 1,
++	.writeback_min_vscl_ratio = 1,
++	.writeback_max_hscl_taps = 12,
++	.writeback_max_vscl_taps = 12,
++	.writeback_line_buffer_luma_buffer_size = 0,
++	.writeback_line_buffer_chroma_buffer_size = 14643,
++	.cursor_buffer_size = 8,
++	.cursor_chunk_size = 2,
++	.max_num_otg = 4,
++	.max_num_dpp = 4,
++	.max_num_wb = 1,
++	.max_dchub_pscl_bw_pix_per_clk = 4,
++	.max_pscl_lb_bw_pix_per_clk = 2,
++	.max_lb_vscl_bw_pix_per_clk = 4,
++	.max_vscl_hscl_bw_pix_per_clk = 4,
++	.max_hscl_ratio = 4,
++	.max_vscl_ratio = 4,
++	.hscl_mults = 4,
++	.vscl_mults = 4,
++	.max_hscl_taps = 8,
++	.max_vscl_taps = 8,
++	.dispclk_ramp_margin_percent = 1,
++	.underscan_factor = 1.10,
++	.min_vblank_lines = 32, //
++	.dppclk_delay_subtotal = 77, //
++	.dppclk_delay_scl_lb_only = 16,
++	.dppclk_delay_scl = 50,
++	.dppclk_delay_cnvc_formatter = 8,
++	.dppclk_delay_cnvc_cursor = 6,
++	.dispclk_delay_subtotal = 87, //
++	.dcfclk_cstate_latency = 10, // SRExitTime
++	.max_inter_dcn_tile_repeaters = 8,
++
++	.xfc_supported = false,
++	.xfc_fill_bw_overhead_percent = 10.0,
++	.xfc_fill_constant_bytes = 0,
++	.ptoi_supported = 0
++};
++
++struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
++	.clock_limits = {
++			{
++				.state = 0,
++				.dcfclk_mhz = 304.0,
++				.fabricclk_mhz = 600.0,
++				.dispclk_mhz = 618.0,
++				.dppclk_mhz = 440.0,
++				.phyclk_mhz = 600.0,
++				.socclk_mhz = 278.0,
++				.dscclk_mhz = 205.67,
++				.dram_speed_mts = 1600.0,
++			},
++			{
++				.state = 1,
++				.dcfclk_mhz = 304.0,
++				.fabricclk_mhz = 600.0,
++				.dispclk_mhz = 618.0,
++				.dppclk_mhz = 618.0,
++				.phyclk_mhz = 600.0,
++				.socclk_mhz = 278.0,
++				.dscclk_mhz = 205.67,
++				.dram_speed_mts = 1600.0,
++			},
++			{
++				.state = 2,
++				.dcfclk_mhz = 608.0,
++				.fabricclk_mhz = 1066.0,
++				.dispclk_mhz = 888.0,
++				.dppclk_mhz = 888.0,
++				.phyclk_mhz = 810.0,
++				.socclk_mhz = 278.0,
++				.dscclk_mhz = 287.67,
++				.dram_speed_mts = 2133.0,
++			},
++			{
++				.state = 3,
++				.dcfclk_mhz = 676.0,
++				.fabricclk_mhz = 1600.0,
++				.dispclk_mhz = 1015.0,
++				.dppclk_mhz = 1015.0,
++				.phyclk_mhz = 810.0,
++				.socclk_mhz = 715.0,
++				.dscclk_mhz = 318.334,
++				.dram_speed_mts = 4266.0,
++			},
++			{
++				.state = 4,
++				.dcfclk_mhz = 810.0,
++				.fabricclk_mhz = 1600.0,
++				.dispclk_mhz = 1015.0,
++				.dppclk_mhz = 1015.0,
++				.phyclk_mhz = 810.0,
++				.socclk_mhz = 953.0,
++				.dscclk_mhz = 318.334,
++				.dram_speed_mts = 4266.0,
++			},
++			/*Extra state, no dispclk ramping*/
++			{
++				.state = 5,
++				.dcfclk_mhz = 810.0,
++				.fabricclk_mhz = 1600.0,
++				.dispclk_mhz = 1015.0,
++				.dppclk_mhz = 1015.0,
++				.phyclk_mhz = 810.0,
++				.socclk_mhz = 953.0,
++				.dscclk_mhz = 318.334,
++				.dram_speed_mts = 4266.0,
++			},
++
++		},
++
++	.sr_exit_time_us = 9.0,
++	.sr_enter_plus_exit_time_us = 11.0,
++	.urgent_latency_us = 4.0,
++	.urgent_latency_pixel_data_only_us = 4.0,
++	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
++	.urgent_latency_vm_data_only_us = 4.0,
++	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
++	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
++	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
++	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
++	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
++	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
++	.max_avg_sdp_bw_use_normal_percent = 60.0,
++	.max_avg_dram_bw_use_normal_percent = 100.0,
++	.writeback_latency_us = 12.0,
++	.max_request_size_bytes = 256,
++	.dram_channel_width_bytes = 4,
++	.fabric_datapath_to_dcn_data_return_bytes = 32,
++	.dcn_downspread_percent = 0.5,
++	.downspread_percent = 0.5,
++	.dram_page_open_time_ns = 50.0,
++	.dram_rw_turnaround_time_ns = 17.5,
++	.dram_return_buffer_per_channel_bytes = 8192,
++	.round_trip_ping_latency_dcfclk_cycles = 128,
++	.urgent_out_of_order_return_per_channel_bytes = 4096,
++	.channel_interleave_bytes = 256,
++	.num_banks = 8,
++	.num_chans = 4,
++	.vmm_page_size_bytes = 4096,
++	.dram_clock_change_latency_us = 23.84,
++	.return_bus_width_bytes = 64,
++	.dispclk_dppclk_vco_speed_mhz = 3550,
++	.xfc_bus_transport_time_us = 4,
++	.xfc_xbuf_latency_tolerance_us = 4,
++	.use_urgent_burst_bw = 1,
++	.num_states = 5
++};
++
++#ifndef MAX
++#define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
++#endif
++#ifndef MIN
++#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
++#endif
++
++/* begin *********************
++ * macros to expend register list macro defined in HW object header file */
++
++/* DCN */
++/* TODO awful hack. fixup dcn20_dwb.h */
++#undef BASE_INNER
++#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
++
++#define BASE(seg) BASE_INNER(seg)
++
++#define SR(reg_name)\
++		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
++					mm ## reg_name
++
++#define SRI(reg_name, block, id)\
++	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
++					mm ## block ## id ## _ ## reg_name
++
++#define SRIR(var_name, reg_name, block, id)\
++	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
++					mm ## block ## id ## _ ## reg_name
++
++#define SRII(reg_name, block, id)\
++	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
++					mm ## block ## id ## _ ## reg_name
++
++#define DCCG_SRII(reg_name, block, id)\
++	.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
++					mm ## block ## id ## _ ## reg_name
++
++/* NBIO */
++#define NBIO_BASE_INNER(seg) \
++	NBIF0_BASE__INST0_SEG ## seg
++
++#define NBIO_BASE(seg) \
++	NBIO_BASE_INNER(seg)
++
++#define NBIO_SR(reg_name)\
++		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
++					mm ## reg_name
++
++/* MMHUB */
++#define MMHUB_BASE_INNER(seg) \
++	MMHUB_BASE__INST0_SEG ## seg
++
++#define MMHUB_BASE(seg) \
++	MMHUB_BASE_INNER(seg)
++
++#define MMHUB_SR(reg_name)\
++		.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
++					mmMM ## reg_name
++
++#define clk_src_regs(index, pllid)\
++[index] = {\
++	CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
++}
++
++static const struct dce110_clk_src_regs clk_src_regs[] = {
++	clk_src_regs(0, A),
++	clk_src_regs(1, B),
++	clk_src_regs(2, C),
++	clk_src_regs(3, D),
++	clk_src_regs(4, E),
++};
++
++static const struct dce110_clk_src_shift cs_shift = {
++		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
++};
++
++static const struct dce110_clk_src_mask cs_mask = {
++		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
++};
++
++static const struct bios_registers bios_regs = {
++		NBIO_SR(BIOS_SCRATCH_3),
++		NBIO_SR(BIOS_SCRATCH_6)
++};
++
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++static const struct dcn21_dmcub_registers dmcub_regs = {
++		DMCUB_REG_LIST_DCN()
++};
++
++static const struct dcn21_dmcub_shift dmcub_shift = {
++		DMCUB_COMMON_MASK_SH_LIST_BASE(__SHIFT)
++};
++
++static const struct dcn21_dmcub_mask dmcub_mask = {
++		DMCUB_COMMON_MASK_SH_LIST_BASE(_MASK)
++};
++#endif
++
++#define audio_regs(id)\
++[id] = {\
++		AUD_COMMON_REG_LIST(id)\
++}
++
++static const struct dce_audio_registers audio_regs[] = {
++	audio_regs(0),
++	audio_regs(1),
++	audio_regs(2),
++	audio_regs(3),
++	audio_regs(4),
++	audio_regs(5),
++};
++
++#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
++		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
++		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
++		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
++
++static const struct dce_audio_shift audio_shift = {
++		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dce_audio_mask audio_mask = {
++		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
++};
++
++static const struct dccg_registers dccg_regs = {
++		DCCG_COMMON_REG_LIST_DCN_BASE()
++};
++
++static const struct dccg_shift dccg_shift = {
++		DCCG_MASK_SH_LIST_DCN2(__SHIFT)
++};
++
++static const struct dccg_mask dccg_mask = {
++		DCCG_MASK_SH_LIST_DCN2(_MASK)
++};
++
++#define opp_regs(id)\
++[id] = {\
++	OPP_REG_LIST_DCN20(id),\
++}
++
++static const struct dcn20_opp_registers opp_regs[] = {
++	opp_regs(0),
++	opp_regs(1),
++	opp_regs(2),
++	opp_regs(3),
++	opp_regs(4),
++	opp_regs(5),
++};
++
++static const struct dcn20_opp_shift opp_shift = {
++		OPP_MASK_SH_LIST_DCN20(__SHIFT)
++};
++
++static const struct dcn20_opp_mask opp_mask = {
++		OPP_MASK_SH_LIST_DCN20(_MASK)
++};
++
++#define tg_regs(id)\
++[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
++
++static const struct dcn_optc_registers tg_regs[] = {
++	tg_regs(0),
++	tg_regs(1),
++	tg_regs(2),
++	tg_regs(3)
++};
++
++static const struct dcn_optc_shift tg_shift = {
++	TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
++};
++
++static const struct dcn_optc_mask tg_mask = {
++	TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
++};
++
++static const struct dcn20_mpc_registers mpc_regs = {
++		MPC_REG_LIST_DCN2_0(0),
++		MPC_REG_LIST_DCN2_0(1),
++		MPC_REG_LIST_DCN2_0(2),
++		MPC_REG_LIST_DCN2_0(3),
++		MPC_REG_LIST_DCN2_0(4),
++		MPC_REG_LIST_DCN2_0(5),
++		MPC_OUT_MUX_REG_LIST_DCN2_0(0),
++		MPC_OUT_MUX_REG_LIST_DCN2_0(1),
++		MPC_OUT_MUX_REG_LIST_DCN2_0(2),
++		MPC_OUT_MUX_REG_LIST_DCN2_0(3)
++};
++
++static const struct dcn20_mpc_shift mpc_shift = {
++	MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
++};
++
++static const struct dcn20_mpc_mask mpc_mask = {
++	MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
++};
++
++#define hubp_regs(id)\
++[id] = {\
++	HUBP_REG_LIST_DCN21(id)\
++}
++
++static const struct dcn_hubp2_registers hubp_regs[] = {
++		hubp_regs(0),
++		hubp_regs(1),
++		hubp_regs(2),
++		hubp_regs(3)
++};
++
++static const struct dcn_hubp2_shift hubp_shift = {
++		HUBP_MASK_SH_LIST_DCN21(__SHIFT)
++};
++
++static const struct dcn_hubp2_mask hubp_mask = {
++		HUBP_MASK_SH_LIST_DCN21(_MASK)
++};
++
++static const struct dcn_hubbub_registers hubbub_reg = {
++		HUBBUB_REG_LIST_DCN21()
++};
++
++static const struct dcn_hubbub_shift hubbub_shift = {
++		HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
++};
++
++static const struct dcn_hubbub_mask hubbub_mask = {
++		HUBBUB_MASK_SH_LIST_DCN21(_MASK)
++};
++
++
++#define vmid_regs(id)\
++[id] = {\
++		DCN20_VMID_REG_LIST(id)\
++}
++
++static const struct dcn_vmid_registers vmid_regs[] = {
++	vmid_regs(0),
++	vmid_regs(1),
++	vmid_regs(2),
++	vmid_regs(3),
++	vmid_regs(4),
++	vmid_regs(5),
++	vmid_regs(6),
++	vmid_regs(7),
++	vmid_regs(8),
++	vmid_regs(9),
++	vmid_regs(10),
++	vmid_regs(11),
++	vmid_regs(12),
++	vmid_regs(13),
++	vmid_regs(14),
++	vmid_regs(15)
++};
++
++static const struct dcn20_vmid_shift vmid_shifts = {
++		DCN20_VMID_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dcn20_vmid_mask vmid_masks = {
++		DCN20_VMID_MASK_SH_LIST(_MASK)
++};
++
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++#define dsc_regsDCN20(id)\
++[id] = {\
++	DSC_REG_LIST_DCN20(id)\
++}
++
++static const struct dcn20_dsc_registers dsc_regs[] = {
++	dsc_regsDCN20(0),
++	dsc_regsDCN20(1),
++	dsc_regsDCN20(2),
++	dsc_regsDCN20(3),
++	dsc_regsDCN20(4),
++	dsc_regsDCN20(5)
++};
++
++static const struct dcn20_dsc_shift dsc_shift = {
++	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
++};
++
++static const struct dcn20_dsc_mask dsc_mask = {
++	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
++};
++#endif
++
++#define ipp_regs(id)\
++[id] = {\
++	IPP_REG_LIST_DCN20(id),\
++}
++
++static const struct dcn10_ipp_registers ipp_regs[] = {
++	ipp_regs(0),
++	ipp_regs(1),
++	ipp_regs(2),
++	ipp_regs(3),
++};
++
++static const struct dcn10_ipp_shift ipp_shift = {
++		IPP_MASK_SH_LIST_DCN20(__SHIFT)
++};
++
++static const struct dcn10_ipp_mask ipp_mask = {
++		IPP_MASK_SH_LIST_DCN20(_MASK),
++};
++
++#define opp_regs(id)\
++[id] = {\
++	OPP_REG_LIST_DCN20(id),\
++}
++
++
++#define aux_engine_regs(id)\
++[id] = {\
++	AUX_COMMON_REG_LIST0(id), \
++	.AUXN_IMPCAL = 0, \
++	.AUXP_IMPCAL = 0, \
++	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
++}
++
++static const struct dce110_aux_registers aux_engine_regs[] = {
++		aux_engine_regs(0),
++		aux_engine_regs(1),
++		aux_engine_regs(2),
++		aux_engine_regs(3),
++		aux_engine_regs(4),
++};
++
++#define tf_regs(id)\
++[id] = {\
++	TF_REG_LIST_DCN20(id),\
++}
++
++static const struct dcn2_dpp_registers tf_regs[] = {
++	tf_regs(0),
++	tf_regs(1),
++	tf_regs(2),
++	tf_regs(3),
++};
++
++static const struct dcn2_dpp_shift tf_shift = {
++		TF_REG_LIST_SH_MASK_DCN20(__SHIFT)
++};
++
++static const struct dcn2_dpp_mask tf_mask = {
++		TF_REG_LIST_SH_MASK_DCN20(_MASK)
++};
++
++#define stream_enc_regs(id)\
++[id] = {\
++	SE_DCN2_REG_LIST(id)\
++}
++
++static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
++	stream_enc_regs(0),
++	stream_enc_regs(1),
++	stream_enc_regs(2),
++	stream_enc_regs(3),
++	stream_enc_regs(4),
++};
++
++static const struct dcn10_stream_encoder_shift se_shift = {
++		SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
++};
++
++static const struct dcn10_stream_encoder_mask se_mask = {
++		SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
++};
++
++static struct input_pixel_processor *dcn21_ipp_create(
++	struct dc_context *ctx, uint32_t inst)
++{
++	struct dcn10_ipp *ipp =
++		kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
++
++	if (!ipp) {
++		BREAK_TO_DEBUGGER();
++		return NULL;
++	}
++
++	dcn20_ipp_construct(ipp, ctx, inst,
++			&ipp_regs[inst], &ipp_shift, &ipp_mask);
++	return &ipp->base;
++}
++
++static struct dpp *dcn21_dpp_create(
++	struct dc_context *ctx,
++	uint32_t inst)
++{
++	struct dcn20_dpp *dpp =
++		kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
++
++	if (!dpp)
++		return NULL;
++
++	if (dpp2_construct(dpp, ctx, inst,
++			&tf_regs[inst], &tf_shift, &tf_mask))
++		return &dpp->base;
++
++	BREAK_TO_DEBUGGER();
++	kfree(dpp);
++	return NULL;
++}
++
++static struct dce_aux *dcn21_aux_engine_create(
++	struct dc_context *ctx,
++	uint32_t inst)
++{
++	struct aux_engine_dce110 *aux_engine =
++		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
++
++	if (!aux_engine)
++		return NULL;
++
++	dce110_aux_engine_construct(aux_engine, ctx, inst,
++				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
++				    &aux_engine_regs[inst]);
++
++	return &aux_engine->base;
++}
++
++#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
++
++static const struct dce_i2c_registers i2c_hw_regs[] = {
++		i2c_inst_regs(1),
++		i2c_inst_regs(2),
++		i2c_inst_regs(3),
++		i2c_inst_regs(4),
++		i2c_inst_regs(5),
++};
++
++static const struct dce_i2c_shift i2c_shifts = {
++		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
++};
++
++static const struct dce_i2c_mask i2c_masks = {
++		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
++};
++
++struct dce_i2c_hw *dcn21_i2c_hw_create(
++	struct dc_context *ctx,
++	uint32_t inst)
++{
++	struct dce_i2c_hw *dce_i2c_hw =
++		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
++
++	if (!dce_i2c_hw)
++		return NULL;
++
++	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
++				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
++
++	return dce_i2c_hw;
++}
++
++static const struct resource_caps res_cap_rn = {
++		.num_timing_generator = 4,
++		.num_opp = 4,
++		.num_video_plane = 4,
++		.num_audio = 6, // 6 audio endpoints.  4 audio streams
++		.num_stream_encoder = 5,
++		.num_pll = 5,  // maybe 3 because the last two used for USB-c
++		.num_dwb = 1,
++		.num_ddc = 5,
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++		.num_dsc = 3,
++#endif
++};
++
++#ifdef DIAGS_BUILD
++static const struct resource_caps res_cap_rn_FPGA_4pipe = {
++		.num_timing_generator = 4,
++		.num_opp = 4,
++		.num_video_plane = 4,
++		.num_audio = 7,
++		.num_stream_encoder = 4,
++		.num_pll = 4,
++		.num_dwb = 1,
++		.num_ddc = 4,
++		.num_dsc = 0,
++};
++
++static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
++		.num_timing_generator = 2,
++		.num_opp = 2,
++		.num_video_plane = 2,
++		.num_audio = 7,
++		.num_stream_encoder = 2,
++		.num_pll = 4,
++		.num_dwb = 1,
++		.num_ddc = 4,
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++		.num_dsc = 2,
++#endif
++};
++#endif
++
++static const struct dc_plane_cap plane_cap = {
++	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
++	.blends_with_above = true,
++	.blends_with_below = true,
++	.per_pixel_alpha = true,
++
++	.pixel_format_support = {
++			.argb8888 = true,
++			.nv12 = true,
++			.fp16 = true
++	},
++
++	.max_upscale_factor = {
++			.argb8888 = 16000,
++			.nv12 = 16000,
++			.fp16 = 16000
++	},
++
++	.max_downscale_factor = {
++			.argb8888 = 250,
++			.nv12 = 250,
++			.fp16 = 250
++	}
++};
++
++static const struct dc_debug_options debug_defaults_drv = {
++		.disable_dmcu = true,
++		.force_abm_enable = false,
++		.timing_trace = false,
++		.clock_trace = true,
++		.disable_pplib_clock_request = true,
++		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
++		.force_single_disp_pipe_split = true,
++		.disable_dcc = DCC_ENABLE,
++		.vsr_support = true,
++		.performance_trace = false,
++		.max_downscale_src_width = 5120,/*upto 5K*/
++		.disable_pplib_wm_range = false,
++		.scl_reset_length10 = true,
++		.sanity_checks = true,
++		.disable_48mhz_pwrdwn = true,
++};
++
++static const struct dc_debug_options debug_defaults_diags = {
++		.disable_dmcu = true,
++		.force_abm_enable = false,
++		.timing_trace = true,
++		.clock_trace = true,
++		.disable_dpp_power_gate = true,
++		.disable_hubp_power_gate = true,
++		.disable_clock_gate = true,
++		.disable_pplib_clock_request = true,
++		.disable_pplib_wm_range = true,
++		.disable_stutter = true,
++		.disable_48mhz_pwrdwn = true,
++};
++
++enum dcn20_clk_src_array_id {
++	DCN20_CLK_SRC_PLL0,
++	DCN20_CLK_SRC_PLL1,
++	DCN20_CLK_SRC_TOTAL_DCN21
++};
++
++static void destruct(struct dcn21_resource_pool *pool)
++{
++	unsigned int i;
++
++	for (i = 0; i < pool->base.stream_enc_count; i++) {
++		if (pool->base.stream_enc[i] != NULL) {
++			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
++			pool->base.stream_enc[i] = NULL;
++		}
++	}
++
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
++		if (pool->base.dscs[i] != NULL)
++			dcn20_dsc_destroy(&pool->base.dscs[i]);
++	}
++#endif
++
++	if (pool->base.mpc != NULL) {
++		kfree(TO_DCN20_MPC(pool->base.mpc));
++		pool->base.mpc = NULL;
++	}
++	if (pool->base.hubbub != NULL) {
++		kfree(pool->base.hubbub);
++		pool->base.hubbub = NULL;
++	}
++	for (i = 0; i < pool->base.pipe_count; i++) {
++		if (pool->base.dpps[i] != NULL)
++			dcn20_dpp_destroy(&pool->base.dpps[i]);
++
++		if (pool->base.ipps[i] != NULL)
++			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
++
++		if (pool->base.hubps[i] != NULL) {
++			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
++			pool->base.hubps[i] = NULL;
++		}
++
++		if (pool->base.irqs != NULL) {
++			dal_irq_service_destroy(&pool->base.irqs);
++		}
++	}
++
++	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
++		if (pool->base.engines[i] != NULL)
++			dce110_engine_destroy(&pool->base.engines[i]);
++		if (pool->base.hw_i2cs[i] != NULL) {
++			kfree(pool->base.hw_i2cs[i]);
++			pool->base.hw_i2cs[i] = NULL;
++		}
++		if (pool->base.sw_i2cs[i] != NULL) {
++			kfree(pool->base.sw_i2cs[i]);
++			pool->base.sw_i2cs[i] = NULL;
++		}
++	}
++
++	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
++		if (pool->base.opps[i] != NULL)
++			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
++	}
++
++	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
++		if (pool->base.timing_generators[i] != NULL)	{
++			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
++			pool->base.timing_generators[i] = NULL;
++		}
++	}
++
++	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
++		if (pool->base.dwbc[i] != NULL) {
++			kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
++			pool->base.dwbc[i] = NULL;
++		}
++		if (pool->base.mcif_wb[i] != NULL) {
++			kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
++			pool->base.mcif_wb[i] = NULL;
++		}
++	}
++
++	for (i = 0; i < pool->base.audio_count; i++) {
++		if (pool->base.audios[i])
++			dce_aud_destroy(&pool->base.audios[i]);
++	}
++
++	for (i = 0; i < pool->base.clk_src_count; i++) {
++		if (pool->base.clock_sources[i] != NULL) {
++			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
++			pool->base.clock_sources[i] = NULL;
++		}
++	}
++
++	if (pool->base.dp_clock_source != NULL) {
++		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
++		pool->base.dp_clock_source = NULL;
++	}
++
++
++	if (pool->base.abm != NULL)
++		dce_abm_destroy(&pool->base.abm);
++
++	if (pool->base.dmcu != NULL)
++		dce_dmcu_destroy(&pool->base.dmcu);
++
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	if (pool->base.dmcub != NULL)
++		dcn21_dmcub_destroy(&pool->base.dmcub);
++#endif
++
++	if (pool->base.dccg != NULL)
++		dcn_dccg_destroy(&pool->base.dccg);
++
++	if (pool->base.pp_smu != NULL)
++		dcn20_pp_smu_destroy(&pool->base.pp_smu);
++}
++
++
++static void calculate_wm_set_for_vlevel(
++		int vlevel,
++		struct wm_range_table_entry *table_entry,
++		struct dcn_watermarks *wm_set,
++		struct display_mode_lib *dml,
++		display_e2e_pipe_params_st *pipes,
++		int pipe_cnt)
++{
++	double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
++
++	ASSERT(vlevel < dml->soc.num_states);
++	/* only pipe 0 is read for voltage and dcf/soc clocks */
++	pipes[0].clks_cfg.voltage = vlevel;
++	pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
++	pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
++
++	dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
++
++	wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
++	wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
++	wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
++	wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
++	wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
++	wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
++#endif
++	dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
++
++}
++
++void dcn21_calculate_wm(
++		struct dc *dc, struct dc_state *context,
++		display_e2e_pipe_params_st *pipes,
++		int *out_pipe_cnt,
++		int *pipe_split_from,
++		int vlevel_req)
++{
++	int pipe_cnt, i, pipe_idx;
++	int vlevel, vlevel_max;
++	struct wm_range_table_entry *table_entry;
++	struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
++
++	ASSERT(bw_params);
++
++	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
++			if (!context->res_ctx.pipe_ctx[i].stream)
++				continue;
++
++			pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
++			pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
++
++			if (pipe_split_from[i] < 0) {
++				pipes[pipe_cnt].clks_cfg.dppclk_mhz =
++						context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
++				if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
++					pipes[pipe_cnt].pipe.dest.odm_combine =
++							context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
++				else
++					pipes[pipe_cnt].pipe.dest.odm_combine = 0;
++				pipe_idx++;
++			} else {
++				pipes[pipe_cnt].clks_cfg.dppclk_mhz =
++						context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
++				if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
++					pipes[pipe_cnt].pipe.dest.odm_combine =
++							context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
++				else
++					pipes[pipe_cnt].pipe.dest.odm_combine = 0;
++			}
++			pipe_cnt++;
++	}
++
++	if (pipe_cnt != pipe_idx) {
++		if (dc->res_pool->funcs->populate_dml_pipes)
++			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
++				&context->res_ctx, pipes);
++		else
++			pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
++				&context->res_ctx, pipes);
++	}
++
++	*out_pipe_cnt = pipe_cnt;
++
++	vlevel_max = bw_params->clk_table.num_entries - 1;
++
++
++	/* WM Set D */
++	table_entry = &bw_params->wm_table.entries[WM_D];
++	if (table_entry->wm_type == WM_TYPE_RETRAINING)
++		vlevel = 0;
++	else
++		vlevel = vlevel_max;
++	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
++						&context->bw_ctx.dml, pipes, pipe_cnt);
++	/* WM Set C */
++	table_entry = &bw_params->wm_table.entries[WM_C];
++	vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
++	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
++						&context->bw_ctx.dml, pipes, pipe_cnt);
++	/* WM Set B */
++	table_entry = &bw_params->wm_table.entries[WM_B];
++	vlevel = MIN(MAX(vlevel_req, 1), vlevel_max);
++	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
++						&context->bw_ctx.dml, pipes, pipe_cnt);
++
++	/* WM Set A */
++	table_entry = &bw_params->wm_table.entries[WM_A];
++	vlevel = MIN(vlevel_req, vlevel_max);
++	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
++						&context->bw_ctx.dml, pipes, pipe_cnt);
++}
++
++
++bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
++		bool fast_validate)
++{
++	bool out = false;
++
++	BW_VAL_TRACE_SETUP();
++
++	int vlevel = 0;
++	int pipe_split_from[MAX_PIPES];
++	int pipe_cnt = 0;
++	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
++	DC_LOGGER_INIT(dc->ctx->logger);
++
++	BW_VAL_TRACE_COUNT();
++
++	out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
++
++	if (pipe_cnt == 0)
++		goto validate_out;
++
++	if (!out)
++		goto validate_fail;
++
++	BW_VAL_TRACE_END_VOLTAGE_LEVEL();
++
++	if (fast_validate) {
++		BW_VAL_TRACE_SKIP(fast);
++		goto validate_out;
++	}
++
++	dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
++	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
++
++	BW_VAL_TRACE_END_WATERMARKS();
++
++	goto validate_out;
++
++validate_fail:
++	DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
++		dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
++
++	BW_VAL_TRACE_SKIP(fail);
++	out = false;
++
++validate_out:
++	kfree(pipes);
++
++	BW_VAL_TRACE_FINISH();
++
++	return out;
++}
++static void dcn21_destroy_resource_pool(struct resource_pool **pool)
++{
++	struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
++
++	destruct(dcn21_pool);
++	kfree(dcn21_pool);
++	*pool = NULL;
++}
++
++static struct clock_source *dcn21_clock_source_create(
++		struct dc_context *ctx,
++		struct dc_bios *bios,
++		enum clock_source_id id,
++		const struct dce110_clk_src_regs *regs,
++		bool dp_clk_src)
++{
++	struct dce110_clk_src *clk_src =
++		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
++
++	if (!clk_src)
++		return NULL;
++
++	if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
++			regs, &cs_shift, &cs_mask)) {
++		clk_src->base.dp_clk_src = dp_clk_src;
++		return &clk_src->base;
++	}
++
++	BREAK_TO_DEBUGGER();
++	return NULL;
++}
++
++static struct hubp *dcn21_hubp_create(
++	struct dc_context *ctx,
++	uint32_t inst)
++{
++	struct dcn21_hubp *hubp21 =
++		kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
++
++	if (!hubp21)
++		return NULL;
++
++	if (hubp21_construct(hubp21, ctx, inst,
++			&hubp_regs[inst], &hubp_shift, &hubp_mask))
++		return &hubp21->base;
++
++	BREAK_TO_DEBUGGER();
++	kfree(hubp21);
++	return NULL;
++}
++
++static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
++{
++	int i;
++
++	struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
++					  GFP_KERNEL);
++
++	if (!hubbub)
++		return NULL;
++
++	hubbub21_construct(hubbub, ctx,
++			&hubbub_reg,
++			&hubbub_shift,
++			&hubbub_mask);
++
++	for (i = 0; i < res_cap_rn.num_vmid; i++) {
++		struct dcn20_vmid *vmid = &hubbub->vmid[i];
++
++		vmid->ctx = ctx;
++
++		vmid->regs = &vmid_regs[i];
++		vmid->shifts = &vmid_shifts;
++		vmid->masks = &vmid_masks;
++	}
++
++	return &hubbub->base;
++}
++
++struct output_pixel_processor *dcn21_opp_create(
++	struct dc_context *ctx, uint32_t inst)
++{
++	struct dcn20_opp *opp =
++		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
++
++	if (!opp) {
++		BREAK_TO_DEBUGGER();
++		return NULL;
++	}
++
++	dcn20_opp_construct(opp, ctx, inst,
++			&opp_regs[inst], &opp_shift, &opp_mask);
++	return &opp->base;
++}
++
++struct timing_generator *dcn21_timing_generator_create(
++		struct dc_context *ctx,
++		uint32_t instance)
++{
++	struct optc *tgn10 =
++		kzalloc(sizeof(struct optc), GFP_KERNEL);
++
++	if (!tgn10)
++		return NULL;
++
++	tgn10->base.inst = instance;
++	tgn10->base.ctx = ctx;
++
++	tgn10->tg_regs = &tg_regs[instance];
++	tgn10->tg_shift = &tg_shift;
++	tgn10->tg_mask = &tg_mask;
++
++	dcn20_timing_generator_init(tgn10);
++
++	return &tgn10->base;
++}
++
++struct mpc *dcn21_mpc_create(struct dc_context *ctx)
++{
++	struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
++					  GFP_KERNEL);
++
++	if (!mpc20)
++		return NULL;
++
++	dcn20_mpc_construct(mpc20, ctx,
++			&mpc_regs,
++			&mpc_shift,
++			&mpc_mask,
++			6);
++
++	return &mpc20->base;
++}
++
++static void read_dce_straps(
++	struct dc_context *ctx,
++	struct resource_straps *straps)
++{
++	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
++		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
++
++}
++
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++
++struct display_stream_compressor *dcn21_dsc_create(
++	struct dc_context *ctx, uint32_t inst)
++{
++	struct dcn20_dsc *dsc =
++		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
++
++	if (!dsc) {
++		BREAK_TO_DEBUGGER();
++		return NULL;
++	}
++
++	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
++	return &dsc->base;
++}
++#endif
++
++static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
++{
++	struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
++	struct clk_limit_table *clk_table = &bw_params->clk_table;
++	int i;
++
++	dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
++	dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
++	dcn2_1_soc.num_chans = bw_params->num_channels;
++	dcn2_1_soc.num_states = 0;
++
++	for (i = 0; i < clk_table->num_entries; i++) {
++
++		dcn2_1_soc.clock_limits[i].state = i;
++		dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
++		dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
++		dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
++		/* This is probably wrong, TODO: find correct calculation */
++		dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 16 / 1000;
++		dcn2_1_soc.num_states++;
++	}
++}
++
++/* Temporary Place holder until we can get them from fuse */
++static struct dpm_clocks dummy_clocks = {
++		.DcfClocks = {
++				{.Freq = 400, .Vol = 1},
++				{.Freq = 483, .Vol = 1},
++				{.Freq = 602, .Vol = 1},
++				{.Freq = 738, .Vol = 1} },
++		.SocClocks = {
++				{.Freq = 300, .Vol = 1},
++				{.Freq = 400, .Vol = 1},
++				{.Freq = 400, .Vol = 1},
++				{.Freq = 400, .Vol = 1} },
++		.FClocks = {
++				{.Freq = 400, .Vol = 1},
++				{.Freq = 800, .Vol = 1},
++				{.Freq = 1067, .Vol = 1},
++				{.Freq = 1600, .Vol = 1} },
++		.MemClocks = {
++				{.Freq = 800, .Vol = 1},
++				{.Freq = 1600, .Vol = 1},
++				{.Freq = 1067, .Vol = 1},
++				{.Freq = 1600, .Vol = 1} },
++
++};
++
++enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
++		struct pp_smu_wm_range_sets *ranges)
++{
++	return PP_SMU_RESULT_OK;
++}
++
++enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
++		struct dpm_clocks *clock_table)
++{
++	*clock_table = dummy_clocks;
++	return PP_SMU_RESULT_OK;
++}
++
++struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
++{
++	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
++
++	pp_smu->ctx.ver = PP_SMU_VER_RN;
++
++	pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
++	pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
++
++	return pp_smu;
++}
++
++void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
++{
++	if (pp_smu && *pp_smu) {
++		kfree(*pp_smu);
++		*pp_smu = NULL;
++	}
++}
++
++static struct audio *dcn21_create_audio(
++		struct dc_context *ctx, unsigned int inst)
++{
++	return dce_audio_create(ctx, inst,
++			&audio_regs[inst], &audio_shift, &audio_mask);
++}
++
++static struct dc_cap_funcs cap_funcs = {
++	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
++};
++
++struct stream_encoder *dcn21_stream_encoder_create(
++	enum engine_id eng_id,
++	struct dc_context *ctx)
++{
++	struct dcn10_stream_encoder *enc1 =
++		kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
++
++	if (!enc1)
++		return NULL;
++
++	dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
++					&stream_enc_regs[eng_id],
++					&se_shift, &se_mask);
++
++	return &enc1->base;
++}
++
++static const struct dce_hwseq_registers hwseq_reg = {
++		HWSEQ_DCN21_REG_LIST()
++};
++
++static const struct dce_hwseq_shift hwseq_shift = {
++		HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dce_hwseq_mask hwseq_mask = {
++		HWSEQ_DCN21_MASK_SH_LIST(_MASK)
++};
++
++static struct dce_hwseq *dcn21_hwseq_create(
++	struct dc_context *ctx)
++{
++	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
++
++	if (hws) {
++		hws->ctx = ctx;
++		hws->regs = &hwseq_reg;
++		hws->shifts = &hwseq_shift;
++		hws->masks = &hwseq_mask;
++	}
++	return hws;
++}
++
++static const struct resource_create_funcs res_create_funcs = {
++	.read_dce_straps = read_dce_straps,
++	.create_audio = dcn21_create_audio,
++	.create_stream_encoder = dcn21_stream_encoder_create,
++	.create_hwseq = dcn21_hwseq_create,
++};
++
++static const struct resource_create_funcs res_create_maximus_funcs = {
++	.read_dce_straps = NULL,
++	.create_audio = NULL,
++	.create_stream_encoder = NULL,
++	.create_hwseq = dcn21_hwseq_create,
++};
++
++static struct resource_funcs dcn21_res_pool_funcs = {
++	.destroy = dcn21_destroy_resource_pool,
++	.link_enc_create = dcn20_link_encoder_create,
++	.validate_bandwidth = dcn21_validate_bandwidth,
++	.add_stream_to_ctx = dcn20_add_stream_to_ctx,
++	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
++	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
++	.populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
++	.get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
++	.set_mcif_arb_params = dcn20_set_mcif_arb_params,
++	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
++	.update_bw_bounding_box = update_bw_bounding_box
++};
++
++static bool construct(
++	uint8_t num_virtual_links,
++	struct dc *dc,
++	struct dcn21_resource_pool *pool)
++{
++	int i;
++	struct dc_context *ctx = dc->ctx;
++	struct irq_service_init_data init_data;
++
++	ctx->dc_bios->regs = &bios_regs;
++
++	pool->base.res_cap = &res_cap_rn;
++#ifdef DIAGS_BUILD
++	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
++		//pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
++		pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
++#endif
++
++	pool->base.funcs = &dcn21_res_pool_funcs;
++
++	/*************************************************
++	 *  Resource + asic cap harcoding                *
++	 *************************************************/
++	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
++
++	pool->base.pipe_count = 4;
++	dc->caps.max_downscale_ratio = 200;
++	dc->caps.i2c_speed_in_khz = 100;
++	dc->caps.max_cursor_size = 256;
++	dc->caps.dmdata_alloc_size = 2048;
++	dc->caps.hw_3d_lut = true;
++
++	dc->caps.max_slave_planes = 1;
++	dc->caps.post_blend_color_processing = true;
++	dc->caps.force_dp_tps4_for_cp2520 = true;
++
++	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
++		dc->debug = debug_defaults_drv;
++	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
++		pool->base.pipe_count = 4;
++		dc->debug = debug_defaults_diags;
++	} else
++		dc->debug = debug_defaults_diags;
++
++	// Init the vm_helper
++	if (dc->vm_helper)
++		vm_helper_init(dc->vm_helper, 16);
++
++	/*************************************************
++	 *  Create resources                             *
++	 *************************************************/
++
++	pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
++			dcn21_clock_source_create(ctx, ctx->dc_bios,
++				CLOCK_SOURCE_COMBO_PHY_PLL0,
++				&clk_src_regs[0], false);
++	pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
++			dcn21_clock_source_create(ctx, ctx->dc_bios,
++				CLOCK_SOURCE_COMBO_PHY_PLL1,
++				&clk_src_regs[1], false);
++
++	pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
++
++	/* todo: not reuse phy_pll registers */
++	pool->base.dp_clock_source =
++			dcn21_clock_source_create(ctx, ctx->dc_bios,
++				CLOCK_SOURCE_ID_DP_DTO,
++				&clk_src_regs[0], true);
++
++	for (i = 0; i < pool->base.clk_src_count; i++) {
++		if (pool->base.clock_sources[i] == NULL) {
++			dm_error("DC: failed to create clock sources!\n");
++			BREAK_TO_DEBUGGER();
++			goto create_fail;
++		}
++	}
++
++	pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
++	if (pool->base.dccg == NULL) {
++		dm_error("DC: failed to create dccg!\n");
++		BREAK_TO_DEBUGGER();
++		goto create_fail;
++	}
++
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	pool->base.dmcub = dcn21_dmcub_create(ctx,
++			&dmcub_regs,
++			&dmcub_shift,
++			&dmcub_mask);
++	if (pool->base.dmcub == NULL) {
++		dm_error("DC: failed to create dmcub!\n");
++		BREAK_TO_DEBUGGER();
++		goto create_fail;
++	}
++#endif
++
++	pool->base.pp_smu = dcn21_pp_smu_create(ctx);
++
++	dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
++
++	init_data.ctx = dc->ctx;
++	pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
++	if (!pool->base.irqs)
++		goto create_fail;
++
++	/* mem input -> ipp -> dpp -> opp -> TG */
++	for (i = 0; i < pool->base.pipe_count; i++) {
++		pool->base.hubps[i] = dcn21_hubp_create(ctx, i);
++		if (pool->base.hubps[i] == NULL) {
++			BREAK_TO_DEBUGGER();
++			dm_error(
++				"DC: failed to create memory input!\n");
++			goto create_fail;
++		}
++
++		pool->base.ipps[i] = dcn21_ipp_create(ctx, i);
++		if (pool->base.ipps[i] == NULL) {
++			BREAK_TO_DEBUGGER();
++			dm_error(
++				"DC: failed to create input pixel processor!\n");
++			goto create_fail;
++		}
++
++		pool->base.dpps[i] = dcn21_dpp_create(ctx, i);
++		if (pool->base.dpps[i] == NULL) {
++			BREAK_TO_DEBUGGER();
++			dm_error(
++				"DC: failed to create dpps!\n");
++			goto create_fail;
++		}
++	}
++
++	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
++		pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
++		if (pool->base.engines[i] == NULL) {
++			BREAK_TO_DEBUGGER();
++			dm_error(
++				"DC:failed to create aux engine!!\n");
++			goto create_fail;
++		}
++		pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
++		if (pool->base.hw_i2cs[i] == NULL) {
++			BREAK_TO_DEBUGGER();
++			dm_error(
++				"DC:failed to create hw i2c!!\n");
++			goto create_fail;
++		}
++		pool->base.sw_i2cs[i] = NULL;
++	}
++
++	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
++		pool->base.opps[i] = dcn21_opp_create(ctx, i);
++		if (pool->base.opps[i] == NULL) {
++			BREAK_TO_DEBUGGER();
++			dm_error(
++				"DC: failed to create output pixel processor!\n");
++			goto create_fail;
++		}
++	}
++
++	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
++		pool->base.timing_generators[i] = dcn21_timing_generator_create(
++				ctx, i);
++		if (pool->base.timing_generators[i] == NULL) {
++			BREAK_TO_DEBUGGER();
++			dm_error("DC: failed to create tg!\n");
++			goto create_fail;
++		}
++	}
++
++	pool->base.timing_generator_count = i;
++
++	pool->base.mpc = dcn21_mpc_create(ctx);
++	if (pool->base.mpc == NULL) {
++		BREAK_TO_DEBUGGER();
++		dm_error("DC: failed to create mpc!\n");
++		goto create_fail;
++	}
++
++	pool->base.hubbub = dcn21_hubbub_create(ctx);
++	if (pool->base.hubbub == NULL) {
++		BREAK_TO_DEBUGGER();
++		dm_error("DC: failed to create hubbub!\n");
++		goto create_fail;
++	}
++
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
++		pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
++		if (pool->base.dscs[i] == NULL) {
++			BREAK_TO_DEBUGGER();
++			dm_error("DC: failed to create display stream compressor %d!\n", i);
++			goto create_fail;
++		}
++	}
++#endif
++
++	if (!dcn20_dwbc_create(ctx, &pool->base)) {
++		BREAK_TO_DEBUGGER();
++		dm_error("DC: failed to create dwbc!\n");
++		goto create_fail;
++	}
++	if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
++		BREAK_TO_DEBUGGER();
++		dm_error("DC: failed to create mcif_wb!\n");
++		goto create_fail;
++	}
++
++	if (!resource_construct(num_virtual_links, dc, &pool->base,
++			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
++			&res_create_funcs : &res_create_maximus_funcs)))
++			goto create_fail;
++
++	dcn20_hw_sequencer_construct(dc);
++
++	dc->caps.max_planes =  pool->base.pipe_count;
++
++	for (i = 0; i < dc->caps.max_planes; ++i)
++		dc->caps.planes[i] = plane_cap;
++
++	dc->cap_funcs = cap_funcs;
++
++	return true;
++
++create_fail:
++
++	destruct(pool);
++
++	return false;
++}
++
++struct resource_pool *dcn21_create_resource_pool(
++		const struct dc_init_data *init_data,
++		struct dc *dc)
++{
++	struct dcn21_resource_pool *pool =
++		kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
++
++	if (!pool)
++		return NULL;
++
++	if (construct(init_data->num_virtual_links, dc, pool))
++		return &pool->base;
++
++	BREAK_TO_DEBUGGER();
++	kfree(pool);
++	return NULL;
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h
+new file mode 100644
+index 000000000000..a27355171bca
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h
+@@ -0,0 +1,45 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DCN21_RESOURCE_H_
++#define _DCN21_RESOURCE_H_
++
++#include "core_types.h"
++
++#define TO_DCN21_RES_POOL(pool)\
++	container_of(pool, struct dcn21_resource_pool, base)
++
++struct dc;
++struct resource_pool;
++struct _vcs_dpi_display_pipe_params_st;
++
++struct dcn21_resource_pool {
++	struct resource_pool base;
++};
++struct resource_pool *dcn21_create_resource_pool(
++		const struct dc_init_data *init_data,
++		struct dc *dc);
++
++#endif /* _DCN21_RESOURCE_H_ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3641-drm-amd-display-Add-Renoir-GPIO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3641-drm-amd-display-Add-Renoir-GPIO.patch
new file mode 100644
index 00000000..80e16bcb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3641-drm-amd-display-Add-Renoir-GPIO.patch
@@ -0,0 +1,785 @@
+From 7fc223c60615a18aa9c0faf6e5dc1160ff10c136 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 26 Jul 2019 16:47:47 -0400
+Subject: [PATCH 3641/4256] drm/amd/display: Add Renoir GPIO
+
+Misc display related configuration details.
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/gpio/Makefile  |   7 +
+ .../display/dc/gpio/dcn21/hw_factory_dcn21.c  | 210 ++++++++++
+ .../display/dc/gpio/dcn21/hw_factory_dcn21.h  |  33 ++
+ .../dc/gpio/dcn21/hw_translate_dcn21.c        | 386 ++++++++++++++++++
+ .../dc/gpio/dcn21/hw_translate_dcn21.h        |  35 ++
+ .../gpu/drm/amd/display/dc/gpio/hw_factory.c  |   8 +
+ .../drm/amd/display/dc/gpio/hw_translate.c    |   8 +
+ 7 files changed, 687 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+index 113affea49bf..b3062275711e 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+@@ -80,6 +80,13 @@ AMD_DAL_GPIO_DCN20 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn20/,$(GPIO_DCN20))
+ AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN20)
+ endif
+ 
++ifdef CONFIG_DRM_AMD_DC_DCN2_1
++GPIO_DCN21 = hw_translate_dcn21.o hw_factory_dcn21.o
++
++AMD_DAL_GPIO_DCN21 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn21/,$(GPIO_DCN21))
++
++AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN21)
++endif
+ ###############################################################################
+ # Diagnostics on FPGA
+ ###############################################################################
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
+new file mode 100644
+index 000000000000..34485d9de78a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
+@@ -0,0 +1,210 @@
++/*
++ * Copyright 2013-15 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++#include "dm_services.h"
++#include "include/gpio_types.h"
++#include "../hw_factory.h"
++
++
++#include "../hw_gpio.h"
++#include "../hw_ddc.h"
++#include "../hw_hpd.h"
++#include "../hw_generic.h"
++
++#include "hw_factory_dcn21.h"
++
++
++#include "dcn/dcn_2_1_0_offset.h"
++#include "dcn/dcn_2_1_0_sh_mask.h"
++#include "renoir_ip_offset.h"
++
++
++#include "reg_helper.h"
++#include "../hpd_regs.h"
++/* begin *********************
++ * macros to expend register list macro defined in HW object header file */
++
++/* DCN */
++#define block HPD
++#define reg_num 0
++
++#undef BASE_INNER
++#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
++
++#define BASE(seg) BASE_INNER(seg)
++
++
++
++#define REG(reg_name)\
++		BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
++
++#define SF_HPD(reg_name, field_name, post_fix)\
++	.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
++
++#define REGI(reg_name, block, id)\
++	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
++				mm ## block ## id ## _ ## reg_name
++
++#define SF(reg_name, field_name, post_fix)\
++	.field_name = reg_name ## __ ## field_name ## post_fix
++
++/* macros to expend register list macro defined in HW object header file
++ * end *********************/
++
++
++
++#define hpd_regs(id) \
++{\
++	HPD_REG_LIST(id)\
++}
++
++static const struct hpd_registers hpd_regs[] = {
++	hpd_regs(0),
++	hpd_regs(1),
++	hpd_regs(2),
++	hpd_regs(3),
++	hpd_regs(4),
++};
++
++static const struct hpd_sh_mask hpd_shift = {
++		HPD_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct hpd_sh_mask hpd_mask = {
++		HPD_MASK_SH_LIST(_MASK)
++};
++
++#include "../ddc_regs.h"
++
++ /* set field name */
++#define SF_DDC(reg_name, field_name, post_fix)\
++	.field_name = reg_name ## __ ## field_name ## post_fix
++
++static const struct ddc_registers ddc_data_regs_dcn[] = {
++	ddc_data_regs_dcn2(1),
++	ddc_data_regs_dcn2(2),
++	ddc_data_regs_dcn2(3),
++	ddc_data_regs_dcn2(4),
++	ddc_data_regs_dcn2(5),
++};
++
++static const struct ddc_registers ddc_clk_regs_dcn[] = {
++	ddc_clk_regs_dcn2(1),
++	ddc_clk_regs_dcn2(2),
++	ddc_clk_regs_dcn2(3),
++	ddc_clk_regs_dcn2(4),
++	ddc_clk_regs_dcn2(5),
++};
++
++static const struct ddc_sh_mask ddc_shift[] = {
++	DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),
++	DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),
++	DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
++	DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
++	DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
++	DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
++};
++
++static const struct ddc_sh_mask ddc_mask[] = {
++	DDC_MASK_SH_LIST_DCN2(_MASK, 1),
++	DDC_MASK_SH_LIST_DCN2(_MASK, 2),
++	DDC_MASK_SH_LIST_DCN2(_MASK, 3),
++	DDC_MASK_SH_LIST_DCN2(_MASK, 4),
++	DDC_MASK_SH_LIST_DCN2(_MASK, 5),
++	DDC_MASK_SH_LIST_DCN2(_MASK, 6)
++};
++
++static void define_ddc_registers(
++		struct hw_gpio_pin *pin,
++		uint32_t en)
++{
++	struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
++
++	switch (pin->id) {
++	case GPIO_ID_DDC_DATA:
++		ddc->regs = &ddc_data_regs_dcn[en];
++		ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
++		break;
++	case GPIO_ID_DDC_CLOCK:
++		ddc->regs = &ddc_clk_regs_dcn[en];
++		ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
++		break;
++	default:
++		ASSERT_CRITICAL(false);
++		return;
++	}
++
++	ddc->shifts = &ddc_shift[en];
++	ddc->masks = &ddc_mask[en];
++
++}
++
++static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
++{
++	struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
++
++	hpd->regs = &hpd_regs[en];
++	hpd->shifts = &hpd_shift;
++	hpd->masks = &hpd_mask;
++	hpd->base.regs = &hpd_regs[en].gpio;
++}
++
++
++/* fucntion table */
++static const struct hw_factory_funcs funcs = {
++	.init_ddc_data = dal_hw_ddc_init,
++	.init_generic = dal_hw_generic_init,
++	.init_hpd = dal_hw_hpd_init,
++	.get_ddc_pin = dal_hw_ddc_get_pin,
++	.get_hpd_pin = dal_hw_hpd_get_pin,
++	.get_generic_pin = dal_hw_generic_get_pin,
++	.define_hpd_registers = define_hpd_registers,
++	.define_ddc_registers = define_ddc_registers
++};
++/*
++ * dal_hw_factory_dcn10_init
++ *
++ * @brief
++ * Initialize HW factory function pointers and pin info
++ *
++ * @param
++ * struct hw_factory *factory - [out] struct of function pointers
++ */
++void dal_hw_factory_dcn21_init(struct hw_factory *factory)
++{
++	/*TODO check ASIC CAPs*/
++	factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
++	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
++	factory->number_of_pins[GPIO_ID_GENERIC] = 4;
++	factory->number_of_pins[GPIO_ID_HPD] = 6;
++	factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
++	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
++	factory->number_of_pins[GPIO_ID_SYNC] = 0;
++	factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/
++
++	factory->funcs = &funcs;
++}
++
++#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.h
+new file mode 100644
+index 000000000000..2443f9e7afbf
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.h
+@@ -0,0 +1,33 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++#ifndef __DAL_HW_FACTORY_DCN21_H__
++#define __DAL_HW_FACTORY_DCN21_H__
++
++/* Initialize HW factory function pointers and pin info */
++void dal_hw_factory_dcn21_init(struct hw_factory *factory);
++
++#endif /* __DAL_HW_FACTORY_DCN20_H__ */
++#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
+new file mode 100644
+index 000000000000..ad7c43746291
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
+@@ -0,0 +1,386 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++/*
++ * Pre-requisites: headers required by header of this unit
++ */
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++#include "hw_translate_dcn21.h"
++
++#include "dm_services.h"
++#include "include/gpio_types.h"
++#include "../hw_translate.h"
++
++#include "dcn/dcn_2_1_0_offset.h"
++#include "dcn/dcn_2_1_0_sh_mask.h"
++#include "renoir_ip_offset.h"
++
++
++
++
++/* begin *********************
++ * macros to expend register list macro defined in HW object header file */
++
++/* DCN */
++#define block HPD
++#define reg_num 0
++
++#undef BASE_INNER
++#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
++
++#define BASE(seg) BASE_INNER(seg)
++
++#undef REG
++#define REG(reg_name)\
++		BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
++#define SF_HPD(reg_name, field_name, post_fix)\
++	.field_name = reg_name ## __ ## field_name ## post_fix
++
++
++/* macros to expend register list macro defined in HW object header file
++ * end *********************/
++
++
++static bool offset_to_id(
++	uint32_t offset,
++	uint32_t mask,
++	enum gpio_id *id,
++	uint32_t *en)
++{
++	switch (offset) {
++	/* GENERIC */
++	case REG(DC_GENERICA):
++		*id = GPIO_ID_GENERIC;
++		switch (mask) {
++		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
++			*en = GPIO_GENERIC_A;
++			return true;
++		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
++			*en = GPIO_GENERIC_B;
++			return true;
++		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
++			*en = GPIO_GENERIC_C;
++			return true;
++		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
++			*en = GPIO_GENERIC_D;
++			return true;
++		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
++			*en = GPIO_GENERIC_E;
++			return true;
++		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
++			*en = GPIO_GENERIC_F;
++			return true;
++		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
++			*en = GPIO_GENERIC_G;
++			return true;
++		default:
++			ASSERT_CRITICAL(false);
++#ifdef PALLADIUM_SUPPORTED
++		*en = GPIO_DDC_LINE_DDC1;
++		return true;
++#endif
++			return false;
++		}
++	break;
++	/* HPD */
++	case REG(DC_GPIO_HPD_A):
++		*id = GPIO_ID_HPD;
++		switch (mask) {
++		case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
++			*en = GPIO_HPD_1;
++			return true;
++		case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
++			*en = GPIO_HPD_2;
++			return true;
++		case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
++			*en = GPIO_HPD_3;
++			return true;
++		case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
++			*en = GPIO_HPD_4;
++			return true;
++		case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
++			*en = GPIO_HPD_5;
++			return true;
++		case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
++			*en = GPIO_HPD_6;
++			return true;
++		default:
++			ASSERT_CRITICAL(false);
++			return false;
++		}
++	break;
++	/* REG(DC_GPIO_GENLK_MASK */
++	case REG(DC_GPIO_GENLK_A):
++		*id = GPIO_ID_GSL;
++		switch (mask) {
++		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
++			*en = GPIO_GSL_GENLOCK_CLOCK;
++			return true;
++		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
++			*en = GPIO_GSL_GENLOCK_VSYNC;
++			return true;
++		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
++			*en = GPIO_GSL_SWAPLOCK_A;
++			return true;
++		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
++			*en = GPIO_GSL_SWAPLOCK_B;
++			return true;
++		default:
++			ASSERT_CRITICAL(false);
++			return false;
++		}
++	break;
++	/* DDC */
++	/* we don't care about the GPIO_ID for DDC
++	 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
++	 * directly in the create method */
++	case REG(DC_GPIO_DDC1_A):
++		*en = GPIO_DDC_LINE_DDC1;
++		return true;
++	case REG(DC_GPIO_DDC2_A):
++		*en = GPIO_DDC_LINE_DDC2;
++		return true;
++	case REG(DC_GPIO_DDC3_A):
++		*en = GPIO_DDC_LINE_DDC3;
++		return true;
++	case REG(DC_GPIO_DDC4_A):
++		*en = GPIO_DDC_LINE_DDC4;
++		return true;
++	case REG(DC_GPIO_DDC5_A):
++		*en = GPIO_DDC_LINE_DDC5;
++		return true;
++	case REG(DC_GPIO_DDCVGA_A):
++		*en = GPIO_DDC_LINE_DDC_VGA;
++		return true;
++
++//	case REG(DC_GPIO_I2CPAD_A): not exit
++//	case REG(DC_GPIO_PWRSEQ_A):
++//	case REG(DC_GPIO_PAD_STRENGTH_1):
++//	case REG(DC_GPIO_PAD_STRENGTH_2):
++//	case REG(DC_GPIO_DEBUG):
++	/* UNEXPECTED */
++	default:
++//	case REG(DC_GPIO_SYNCA_A): not exist
++#ifdef PALLADIUM_SUPPORTED
++		*id = GPIO_ID_HPD;
++		*en = GPIO_DDC_LINE_DDC1;
++		return true;
++#endif
++		ASSERT_CRITICAL(false);
++		return false;
++	}
++}
++
++static bool id_to_offset(
++	enum gpio_id id,
++	uint32_t en,
++	struct gpio_pin_info *info)
++{
++	bool result = true;
++
++	switch (id) {
++	case GPIO_ID_DDC_DATA:
++		info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK;
++		switch (en) {
++		case GPIO_DDC_LINE_DDC1:
++			info->offset = REG(DC_GPIO_DDC1_A);
++		break;
++		case GPIO_DDC_LINE_DDC2:
++			info->offset = REG(DC_GPIO_DDC2_A);
++		break;
++		case GPIO_DDC_LINE_DDC3:
++			info->offset = REG(DC_GPIO_DDC3_A);
++		break;
++		case GPIO_DDC_LINE_DDC4:
++			info->offset = REG(DC_GPIO_DDC4_A);
++		break;
++		case GPIO_DDC_LINE_DDC5:
++			info->offset = REG(DC_GPIO_DDC5_A);
++		break;
++		case GPIO_DDC_LINE_DDC_VGA:
++			info->offset = REG(DC_GPIO_DDCVGA_A);
++		break;
++		case GPIO_DDC_LINE_I2C_PAD:
++		default:
++			ASSERT_CRITICAL(false);
++			result = false;
++		}
++	break;
++	case GPIO_ID_DDC_CLOCK:
++		info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK;
++		switch (en) {
++		case GPIO_DDC_LINE_DDC1:
++			info->offset = REG(DC_GPIO_DDC1_A);
++		break;
++		case GPIO_DDC_LINE_DDC2:
++			info->offset = REG(DC_GPIO_DDC2_A);
++		break;
++		case GPIO_DDC_LINE_DDC3:
++			info->offset = REG(DC_GPIO_DDC3_A);
++		break;
++		case GPIO_DDC_LINE_DDC4:
++			info->offset = REG(DC_GPIO_DDC4_A);
++		break;
++		case GPIO_DDC_LINE_DDC5:
++			info->offset = REG(DC_GPIO_DDC5_A);
++		break;
++		case GPIO_DDC_LINE_DDC_VGA:
++			info->offset = REG(DC_GPIO_DDCVGA_A);
++		break;
++		case GPIO_DDC_LINE_I2C_PAD:
++		default:
++			ASSERT_CRITICAL(false);
++			result = false;
++		}
++	break;
++	case GPIO_ID_GENERIC:
++		info->offset = REG(DC_GPIO_GENERIC_A);
++		switch (en) {
++		case GPIO_GENERIC_A:
++			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
++		break;
++		case GPIO_GENERIC_B:
++			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
++		break;
++		case GPIO_GENERIC_C:
++			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
++		break;
++		case GPIO_GENERIC_D:
++			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
++		break;
++		case GPIO_GENERIC_E:
++			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
++		break;
++		case GPIO_GENERIC_F:
++			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
++		break;
++		case GPIO_GENERIC_G:
++			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
++		break;
++		default:
++			ASSERT_CRITICAL(false);
++			result = false;
++		}
++	break;
++	case GPIO_ID_HPD:
++		info->offset = REG(DC_GPIO_HPD_A);
++		switch (en) {
++		case GPIO_HPD_1:
++			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
++		break;
++		case GPIO_HPD_2:
++			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
++		break;
++		case GPIO_HPD_3:
++			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
++		break;
++		case GPIO_HPD_4:
++			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
++		break;
++		case GPIO_HPD_5:
++			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
++		break;
++		case GPIO_HPD_6:
++			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
++		break;
++		default:
++			ASSERT_CRITICAL(false);
++#ifdef PALLADIUM_SUPPORTED
++			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
++			result = true;
++#endif
++			result = false;
++		}
++	break;
++	case GPIO_ID_GSL:
++		switch (en) {
++		case GPIO_GSL_GENLOCK_CLOCK:
++				/*not implmented*/
++			ASSERT_CRITICAL(false);
++			result = false;
++		break;
++		case GPIO_GSL_GENLOCK_VSYNC:
++			/*not implmented*/
++			ASSERT_CRITICAL(false);
++			result = false;
++		break;
++		case GPIO_GSL_SWAPLOCK_A:
++			/*not implmented*/
++			ASSERT_CRITICAL(false);
++			result = false;
++		break;
++		case GPIO_GSL_SWAPLOCK_B:
++			/*not implmented*/
++			ASSERT_CRITICAL(false);
++			result = false;
++
++		break;
++		default:
++			ASSERT_CRITICAL(false);
++			result = false;
++		}
++	break;
++	case GPIO_ID_SYNC:
++	case GPIO_ID_VIP_PAD:
++	default:
++		ASSERT_CRITICAL(false);
++		result = false;
++	}
++
++	if (result) {
++		info->offset_y = info->offset + 2;
++		info->offset_en = info->offset + 1;
++		info->offset_mask = info->offset - 1;
++
++		info->mask_y = info->mask;
++		info->mask_en = info->mask;
++		info->mask_mask = info->mask;
++	}
++
++	return result;
++}
++
++/* function table */
++static const struct hw_translate_funcs funcs = {
++	.offset_to_id = offset_to_id,
++	.id_to_offset = id_to_offset,
++};
++
++/*
++ * dal_hw_translate_dcn10_init
++ *
++ * @brief
++ * Initialize Hw translate function pointers.
++ *
++ * @param
++ * struct hw_translate *tr - [out] struct of function pointers
++ *
++ */
++void dal_hw_translate_dcn21_init(struct hw_translate *tr)
++{
++	tr->funcs = &funcs;
++}
++
++#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.h
+new file mode 100644
+index 000000000000..2bfaac24c574
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.h
+@@ -0,0 +1,35 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++#ifndef __DAL_HW_TRANSLATE_DCN21_H__
++#define __DAL_HW_TRANSLATE_DCN21_H__
++
++struct hw_translate;
++
++/* Initialize Hw translate function pointers */
++void dal_hw_translate_dcn21_init(struct hw_translate *tr);
++
++#endif /* __DAL_HW_TRANSLATE_DCN21_H__ */
++#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+index f90205bfbe76..cb5857c8c7e9 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+@@ -49,6 +49,9 @@
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "dcn20/hw_factory_dcn20.h"
+ #endif
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++#include "dcn21/hw_factory_dcn21.h"
++#endif
+ 
+ #include "diagnostics/hw_factory_diag.h"
+ 
+@@ -97,6 +100,11 @@ bool dal_hw_factory_init(
+ 		dal_hw_factory_dcn20_init(factory);
+ 		return true;
+ #endif
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	case DCN_VERSION_2_1:
++		dal_hw_factory_dcn21_init(factory);
++		return true;
++#endif
+ 
+ 	default:
+ 		ASSERT_CRITICAL(false);
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+index c35fe201d335..f2046f55d6a8 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+@@ -49,6 +49,9 @@
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "dcn20/hw_translate_dcn20.h"
+ #endif
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++#include "dcn21/hw_translate_dcn21.h"
++#endif
+ 
+ #include "diagnostics/hw_translate_diag.h"
+ 
+@@ -94,6 +97,11 @@ bool dal_hw_translate_init(
+ 		dal_hw_translate_dcn20_init(translate);
+ 		return true;
+ #endif
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	case DCN_VERSION_2_1:
++		dal_hw_translate_dcn21_init(translate);
++		return true;
++#endif
+ 
+ 	default:
+ 		BREAK_TO_DEBUGGER();
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3642-drm-amd-display-Add-Renoir-DML.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3642-drm-amd-display-Add-Renoir-DML.patch
new file mode 100644
index 00000000..ed24a880
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3642-drm-amd-display-Add-Renoir-DML.patch
@@ -0,0 +1,8131 @@
+From 847b6b99af63802da2d600fe136ba893f75b0288 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 26 Jul 2019 16:52:06 -0400
+Subject: [PATCH 3642/4256] drm/amd/display: Add Renoir DML
+
+DML provides the display configuration validation as provided
+by the hw teams.
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dml/Makefile   |    4 +
+ .../dc/dml/dcn21/display_mode_vba_21.c        | 6123 +++++++++++++++++
+ .../dc/dml/dcn21/display_mode_vba_21.h        |   32 +
+ .../dc/dml/dcn21/display_rq_dlg_calc_21.c     | 1823 +++++
+ .../dc/dml/dcn21/display_rq_dlg_calc_21.h     |   73 +
+ .../drm/amd/display/dc/dml/display_mode_lib.h |    3 +
+ 6 files changed, 8058 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+index 95fd2beca80c..b267c0fc64e7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+@@ -45,6 +45,10 @@ CFLAGS_display_rq_dlg_calc_20.o := $(dml_ccflags)
+ CFLAGS_display_mode_vba_20v2.o := $(dml_ccflags)
+ CFLAGS_display_rq_dlg_calc_20v2.o := $(dml_ccflags)
+ endif
++ifdef CONFIG_DRM_AMD_DC_DCN2_1
++CFLAGS_display_mode_vba_21.o := $(dml_ccflags)
++CFLAGS_display_rq_dlg_calc_21.o := $(dml_ccflags)
++endif
+ ifdef CONFIG_DRM_AMD_DCN3AG
+ CFLAGS_display_mode_vba_3ag.o := $(dml_ccflags)
+ endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+new file mode 100644
+index 000000000000..456cd0e3289c
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+@@ -0,0 +1,6123 @@
++/*
++ * Copyright 2017 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifdef CONFIG_DRM_AMD_DC_DCN2_0
++
++#include "../display_mode_lib.h"
++#include "../dml_inline_defs.h"
++#include "../display_mode_vba.h"
++#include "display_mode_vba_21.h"
++
++
++/*
++ * NOTE:
++ *   This file is gcc-parsable HW gospel, coming straight from HW engineers.
++ *
++ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
++ * ways. Unless there is something clearly wrong with it the code should
++ * remain as-is as it provides us with a guarantee from HW that it is correct.
++ */
++
++typedef unsigned int uint;
++
++typedef struct {
++	double DPPCLK;
++	double DISPCLK;
++	double PixelClock;
++	double DCFCLKDeepSleep;
++	unsigned int DPPPerPlane;
++	bool ScalerEnabled;
++	enum scan_direction_class SourceScan;
++	unsigned int BlockWidth256BytesY;
++	unsigned int BlockHeight256BytesY;
++	unsigned int BlockWidth256BytesC;
++	unsigned int BlockHeight256BytesC;
++	unsigned int InterlaceEnable;
++	unsigned int NumberOfCursors;
++	unsigned int VBlank;
++	unsigned int HTotal;
++} Pipe;
++
++typedef struct {
++	bool Enable;
++	unsigned int MaxPageTableLevels;
++	unsigned int CachedPageTableLevels;
++} HostVM;
++
++#define BPP_INVALID 0
++#define BPP_BLENDED_PIPE 0xffffffff
++
++static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib);
++static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
++		struct display_mode_lib *mode_lib);
++static unsigned int dscceComputeDelay(
++		unsigned int bpc,
++		double bpp,
++		unsigned int sliceWidth,
++		unsigned int numSlices,
++		enum output_format_class pixelFormat);
++static unsigned int dscComputeDelay(enum output_format_class pixelFormat);
++// Super monster function with some 45 argument
++static bool CalculatePrefetchSchedule(
++		struct display_mode_lib *mode_lib,
++		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
++		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
++		Pipe *myPipe,
++		unsigned int DSCDelay,
++		double DPPCLKDelaySubtotal,
++		double DPPCLKDelaySCL,
++		double DPPCLKDelaySCLLBOnly,
++		double DPPCLKDelayCNVCFormater,
++		double DPPCLKDelayCNVCCursor,
++		double DISPCLKDelaySubtotal,
++		unsigned int ScalerRecoutWidth,
++		enum output_format_class OutputFormat,
++		unsigned int MaxInterDCNTileRepeaters,
++		unsigned int VStartup,
++		unsigned int MaxVStartup,
++		unsigned int GPUVMPageTableLevels,
++		bool GPUVMEnable,
++		HostVM *myHostVM,
++		bool DynamicMetadataEnable,
++		int DynamicMetadataLinesBeforeActiveRequired,
++		unsigned int DynamicMetadataTransmittedBytes,
++		bool DCCEnable,
++		double UrgentLatency,
++		double UrgentExtraLatency,
++		double TCalc,
++		unsigned int PDEAndMetaPTEBytesFrame,
++		unsigned int MetaRowByte,
++		unsigned int PixelPTEBytesPerRow,
++		double PrefetchSourceLinesY,
++		unsigned int SwathWidthY,
++		double BytePerPixelDETY,
++		double VInitPreFillY,
++		unsigned int MaxNumSwathY,
++		double PrefetchSourceLinesC,
++		double BytePerPixelDETC,
++		double VInitPreFillC,
++		unsigned int MaxNumSwathC,
++		unsigned int SwathHeightY,
++		unsigned int SwathHeightC,
++		double TWait,
++		bool XFCEnabled,
++		double XFCRemoteSurfaceFlipDelay,
++		bool ProgressiveToInterlaceUnitInOPP,
++		double *DSTXAfterScaler,
++		double *DSTYAfterScaler,
++		double *DestinationLinesForPrefetch,
++		double *PrefetchBandwidth,
++		double *DestinationLinesToRequestVMInVBlank,
++		double *DestinationLinesToRequestRowInVBlank,
++		double *VRatioPrefetchY,
++		double *VRatioPrefetchC,
++		double *RequiredPrefetchPixDataBWLuma,
++		double *RequiredPrefetchPixDataBWChroma,
++		unsigned int *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata,
++		double *Tno_bw,
++		double *prefetch_vmrow_bw,
++		unsigned int *swath_width_luma_ub,
++		unsigned int *swath_width_chroma_ub,
++		unsigned int *VUpdateOffsetPix,
++		double *VUpdateWidthPix,
++		double *VReadyOffsetPix);
++static double RoundToDFSGranularityUp(double Clock, double VCOSpeed);
++static double RoundToDFSGranularityDown(double Clock, double VCOSpeed);
++static double CalculateDCCConfiguration(
++		bool                 DCCEnabled,
++		bool                 DCCProgrammingAssumesScanDirectionUnknown,
++		unsigned int         ViewportWidth,
++		unsigned int         ViewportHeight,
++		double               DETBufferSize,
++		unsigned int         RequestHeight256Byte,
++		unsigned int         SwathHeight,
++		enum dm_swizzle_mode TilingFormat,
++		unsigned int         BytePerPixel,
++		enum scan_direction_class ScanOrientation,
++		unsigned int        *MaxUncompressedBlock,
++		unsigned int        *MaxCompressedBlock,
++		unsigned int        *Independent64ByteBlock);
++static double CalculatePrefetchSourceLines(
++		struct display_mode_lib *mode_lib,
++		double VRatio,
++		double vtaps,
++		bool Interlace,
++		bool ProgressiveToInterlaceUnitInOPP,
++		unsigned int SwathHeight,
++		unsigned int ViewportYStart,
++		double *VInitPreFill,
++		unsigned int *MaxNumSwath);
++static unsigned int CalculateVMAndRowBytes(
++		struct display_mode_lib *mode_lib,
++		bool DCCEnable,
++		unsigned int BlockHeight256Bytes,
++		unsigned int BlockWidth256Bytes,
++		enum source_format_class SourcePixelFormat,
++		unsigned int SurfaceTiling,
++		unsigned int BytePerPixel,
++		enum scan_direction_class ScanDirection,
++		unsigned int ViewportWidth,
++		unsigned int ViewportHeight,
++		unsigned int SwathWidthY,
++		bool GPUVMEnable,
++		bool HostVMEnable,
++		unsigned int HostVMMaxPageTableLevels,
++		unsigned int HostVMCachedPageTableLevels,
++		unsigned int VMMPageSize,
++		unsigned int PTEBufferSizeInRequests,
++		unsigned int Pitch,
++		unsigned int DCCMetaPitch,
++		unsigned int *MacroTileWidth,
++		unsigned int *MetaRowByte,
++		unsigned int *PixelPTEBytesPerRow,
++		bool *PTEBufferSizeNotExceeded,
++		unsigned int *dpte_row_width_ub,
++		unsigned int *dpte_row_height,
++		unsigned int *MetaRequestWidth,
++		unsigned int *MetaRequestHeight,
++		unsigned int *meta_row_width,
++		unsigned int *meta_row_height,
++		unsigned int *vm_group_bytes,
++		long         *dpte_group_bytes,
++		unsigned int *PixelPTEReqWidth,
++		unsigned int *PixelPTEReqHeight,
++		unsigned int *PTERequestSize,
++		unsigned int *DPDE0BytesFrame,
++		unsigned int *MetaPTEBytesFrame);
++
++static double CalculateTWait(
++		unsigned int PrefetchMode,
++		double DRAMClockChangeLatency,
++		double UrgentLatency,
++		double SREnterPlusExitTime);
++static double CalculateRemoteSurfaceFlipDelay(
++		struct display_mode_lib *mode_lib,
++		double VRatio,
++		double SwathWidth,
++		double Bpp,
++		double LineTime,
++		double XFCTSlvVupdateOffset,
++		double XFCTSlvVupdateWidth,
++		double XFCTSlvVreadyOffset,
++		double XFCXBUFLatencyTolerance,
++		double XFCFillBWOverhead,
++		double XFCSlvChunkSize,
++		double XFCBusTransportTime,
++		double TCalc,
++		double TWait,
++		double *SrcActiveDrainRate,
++		double *TInitXFill,
++		double *TslvChk);
++static void CalculateActiveRowBandwidth(
++		bool GPUVMEnable,
++		enum source_format_class SourcePixelFormat,
++		double VRatio,
++		bool DCCEnable,
++		double LineTime,
++		unsigned int MetaRowByteLuma,
++		unsigned int MetaRowByteChroma,
++		unsigned int meta_row_height_luma,
++		unsigned int meta_row_height_chroma,
++		unsigned int PixelPTEBytesPerRowLuma,
++		unsigned int PixelPTEBytesPerRowChroma,
++		unsigned int dpte_row_height_luma,
++		unsigned int dpte_row_height_chroma,
++		double *meta_row_bw,
++		double *dpte_row_bw);
++static void CalculateFlipSchedule(
++		struct display_mode_lib *mode_lib,
++		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
++		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
++		double UrgentExtraLatency,
++		double UrgentLatency,
++		unsigned int GPUVMMaxPageTableLevels,
++		bool HostVMEnable,
++		unsigned int HostVMMaxPageTableLevels,
++		unsigned int HostVMCachedPageTableLevels,
++		bool GPUVMEnable,
++		double PDEAndMetaPTEBytesPerFrame,
++		double MetaRowBytes,
++		double DPTEBytesPerRow,
++		double BandwidthAvailableForImmediateFlip,
++		unsigned int TotImmediateFlipBytes,
++		enum source_format_class SourcePixelFormat,
++		double LineTime,
++		double VRatio,
++		double Tno_bw,
++		bool DCCEnable,
++		unsigned int dpte_row_height,
++		unsigned int meta_row_height,
++		unsigned int dpte_row_height_chroma,
++		unsigned int meta_row_height_chroma,
++		double *DestinationLinesToRequestVMInImmediateFlip,
++		double *DestinationLinesToRequestRowInImmediateFlip,
++		double *final_flip_bw,
++		bool *ImmediateFlipSupportedForPipe);
++static double CalculateWriteBackDelay(
++		enum source_format_class WritebackPixelFormat,
++		double WritebackHRatio,
++		double WritebackVRatio,
++		unsigned int WritebackLumaHTaps,
++		unsigned int WritebackLumaVTaps,
++		unsigned int WritebackChromaHTaps,
++		unsigned int WritebackChromaVTaps,
++		unsigned int WritebackDestinationWidth);
++static void CalculateWatermarksAndDRAMSpeedChangeSupport(
++		struct display_mode_lib *mode_lib,
++		unsigned int PrefetchMode,
++		unsigned int NumberOfActivePlanes,
++		unsigned int MaxLineBufferLines,
++		unsigned int LineBufferSize,
++		unsigned int DPPOutputBufferPixels,
++		double DETBufferSizeInKByte,
++		unsigned int WritebackInterfaceLumaBufferSize,
++		unsigned int WritebackInterfaceChromaBufferSize,
++		double DCFCLK,
++		double UrgentOutOfOrderReturn,
++		double ReturnBW,
++		bool GPUVMEnable,
++		long dpte_group_bytes[],
++		unsigned int MetaChunkSize,
++		double UrgentLatency,
++		double ExtraLatency,
++		double WritebackLatency,
++		double WritebackChunkSize,
++		double SOCCLK,
++		double DRAMClockChangeLatency,
++		double SRExitTime,
++		double SREnterPlusExitTime,
++		double DCFCLKDeepSleep,
++		int DPPPerPlane[],
++		bool DCCEnable[],
++		double DPPCLK[],
++		unsigned int SwathWidthSingleDPPY[],
++		unsigned int SwathHeightY[],
++		double ReadBandwidthPlaneLuma[],
++		unsigned int SwathHeightC[],
++		double ReadBandwidthPlaneChroma[],
++		unsigned int LBBitPerPixel[],
++		unsigned int SwathWidthY[],
++		double HRatio[],
++		unsigned int vtaps[],
++		unsigned int VTAPsChroma[],
++		double VRatio[],
++		unsigned int HTotal[],
++		double PixelClock[],
++		unsigned int BlendingAndTiming[],
++		double BytePerPixelDETY[],
++		double BytePerPixelDETC[],
++		bool WritebackEnable[],
++		enum source_format_class WritebackPixelFormat[],
++		double WritebackDestinationWidth[],
++		double WritebackDestinationHeight[],
++		double WritebackSourceHeight[],
++		enum clock_change_support *DRAMClockChangeSupport,
++		double *UrgentWatermark,
++		double *WritebackUrgentWatermark,
++		double *DRAMClockChangeWatermark,
++		double *WritebackDRAMClockChangeWatermark,
++		double *StutterExitWatermark,
++		double *StutterEnterPlusExitWatermark,
++		double *MinActiveDRAMClockChangeLatencySupported);
++static void CalculateDCFCLKDeepSleep(
++		struct display_mode_lib *mode_lib,
++		unsigned int NumberOfActivePlanes,
++		double BytePerPixelDETY[],
++		double BytePerPixelDETC[],
++		double VRatio[],
++		unsigned int SwathWidthY[],
++		int DPPPerPlane[],
++		double HRatio[],
++		double PixelClock[],
++		double PSCL_THROUGHPUT[],
++		double PSCL_THROUGHPUT_CHROMA[],
++		double DPPCLK[],
++		double *DCFCLKDeepSleep);
++static void CalculateDETBufferSize(
++		double DETBufferSizeInKByte,
++		unsigned int SwathHeightY,
++		unsigned int SwathHeightC,
++		double *DETBufferSizeY,
++		double *DETBufferSizeC);
++static void CalculateUrgentBurstFactor(
++		unsigned int DETBufferSizeInKByte,
++		unsigned int SwathHeightY,
++		unsigned int SwathHeightC,
++		unsigned int SwathWidthY,
++		double LineTime,
++		double UrgentLatency,
++		double CursorBufferSize,
++		unsigned int CursorWidth,
++		unsigned int CursorBPP,
++		double VRatio,
++		double VRatioPreY,
++		double VRatioPreC,
++		double BytePerPixelInDETY,
++		double BytePerPixelInDETC,
++		double *UrgentBurstFactorCursor,
++		double *UrgentBurstFactorCursorPre,
++		double *UrgentBurstFactorLuma,
++		double *UrgentBurstFactorLumaPre,
++		double *UrgentBurstFactorChroma,
++		double *UrgentBurstFactorChromaPre,
++		unsigned int *NotEnoughUrgentLatencyHiding,
++		unsigned int *NotEnoughUrgentLatencyHidingPre);
++
++static void CalculatePixelDeliveryTimes(
++		unsigned int           NumberOfActivePlanes,
++		double                 VRatio[],
++		double                 VRatioPrefetchY[],
++		double                 VRatioPrefetchC[],
++		unsigned int           swath_width_luma_ub[],
++		unsigned int           swath_width_chroma_ub[],
++		int                    DPPPerPlane[],
++		double                 HRatio[],
++		double                 PixelClock[],
++		double                 PSCL_THROUGHPUT[],
++		double                 PSCL_THROUGHPUT_CHROMA[],
++		double                 DPPCLK[],
++		double                 BytePerPixelDETC[],
++		enum scan_direction_class SourceScan[],
++		unsigned int           BlockWidth256BytesY[],
++		unsigned int           BlockHeight256BytesY[],
++		unsigned int           BlockWidth256BytesC[],
++		unsigned int           BlockHeight256BytesC[],
++		double                 DisplayPipeLineDeliveryTimeLuma[],
++		double                 DisplayPipeLineDeliveryTimeChroma[],
++		double                 DisplayPipeLineDeliveryTimeLumaPrefetch[],
++		double                 DisplayPipeLineDeliveryTimeChromaPrefetch[],
++		double                 DisplayPipeRequestDeliveryTimeLuma[],
++		double                 DisplayPipeRequestDeliveryTimeChroma[],
++		double                 DisplayPipeRequestDeliveryTimeLumaPrefetch[],
++		double                 DisplayPipeRequestDeliveryTimeChromaPrefetch[]);
++
++static void CalculateMetaAndPTETimes(
++		unsigned int           NumberOfActivePlanes,
++		bool                   GPUVMEnable,
++		unsigned int           MetaChunkSize,
++		unsigned int           MinMetaChunkSizeBytes,
++		unsigned int           GPUVMMaxPageTableLevels,
++		unsigned int           HTotal[],
++		double                 VRatio[],
++		double                 VRatioPrefetchY[],
++		double                 VRatioPrefetchC[],
++		double                 DestinationLinesToRequestRowInVBlank[],
++		double                 DestinationLinesToRequestRowInImmediateFlip[],
++		double                 DestinationLinesToRequestVMInVBlank[],
++		double                 DestinationLinesToRequestVMInImmediateFlip[],
++		bool                   DCCEnable[],
++		double                 PixelClock[],
++		double                 BytePerPixelDETY[],
++		double                 BytePerPixelDETC[],
++		enum scan_direction_class SourceScan[],
++		unsigned int           dpte_row_height[],
++		unsigned int           dpte_row_height_chroma[],
++		unsigned int           meta_row_width[],
++		unsigned int           meta_row_height[],
++		unsigned int           meta_req_width[],
++		unsigned int           meta_req_height[],
++		long                   dpte_group_bytes[],
++		unsigned int           PTERequestSizeY[],
++		unsigned int           PTERequestSizeC[],
++		unsigned int           PixelPTEReqWidthY[],
++		unsigned int           PixelPTEReqHeightY[],
++		unsigned int           PixelPTEReqWidthC[],
++		unsigned int           PixelPTEReqHeightC[],
++		unsigned int           dpte_row_width_luma_ub[],
++		unsigned int           dpte_row_width_chroma_ub[],
++		unsigned int           vm_group_bytes[],
++		unsigned int           dpde0_bytes_per_frame_ub_l[],
++		unsigned int           dpde0_bytes_per_frame_ub_c[],
++		unsigned int           meta_pte_bytes_per_frame_ub_l[],
++		unsigned int           meta_pte_bytes_per_frame_ub_c[],
++		double                 DST_Y_PER_PTE_ROW_NOM_L[],
++		double                 DST_Y_PER_PTE_ROW_NOM_C[],
++		double                 DST_Y_PER_META_ROW_NOM_L[],
++		double                 TimePerMetaChunkNominal[],
++		double                 TimePerMetaChunkVBlank[],
++		double                 TimePerMetaChunkFlip[],
++		double                 time_per_pte_group_nom_luma[],
++		double                 time_per_pte_group_vblank_luma[],
++		double                 time_per_pte_group_flip_luma[],
++		double                 time_per_pte_group_nom_chroma[],
++		double                 time_per_pte_group_vblank_chroma[],
++		double                 time_per_pte_group_flip_chroma[],
++		double                 TimePerVMGroupVBlank[],
++		double                 TimePerVMGroupFlip[],
++		double                 TimePerVMRequestVBlank[],
++		double                 TimePerVMRequestFlip[]);
++
++static double CalculateExtraLatency(
++		double UrgentRoundTripAndOutOfOrderLatency,
++		int TotalNumberOfActiveDPP,
++		int PixelChunkSizeInKByte,
++		int TotalNumberOfDCCActiveDPP,
++		int MetaChunkSize,
++		double ReturnBW,
++		bool GPUVMEnable,
++		bool HostVMEnable,
++		int NumberOfActivePlanes,
++		int NumberOfDPP[],
++		long dpte_group_bytes[],
++		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
++		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
++		int HostVMMaxPageTableLevels,
++		int HostVMCachedPageTableLevels);
++
++void dml21_recalculate(struct display_mode_lib *mode_lib)
++{
++	ModeSupportAndSystemConfiguration(mode_lib);
++	PixelClockAdjustmentForProgressiveToInterlaceUnit(mode_lib);
++	DisplayPipeConfiguration(mode_lib);
++	DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(mode_lib);
++}
++
++static unsigned int dscceComputeDelay(
++		unsigned int bpc,
++		double bpp,
++		unsigned int sliceWidth,
++		unsigned int numSlices,
++		enum output_format_class pixelFormat)
++{
++	// valid bpc         = source bits per component in the set of {8, 10, 12}
++	// valid bpp         = increments of 1/16 of a bit
++	//                    min = 6/7/8 in N420/N422/444, respectively
++	//                    max = such that compression is 1:1
++	//valid sliceWidth  = number of pixels per slice line, must be less than or equal to 5184/numSlices (or 4096/numSlices in 420 mode)
++	//valid numSlices   = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4}
++	//valid pixelFormat = pixel/color format in the set of {:N444_RGB, :S422, :N422, :N420}
++
++	// fixed value
++	unsigned int rcModelSize = 8192;
++
++	// N422/N420 operate at 2 pixels per clock
++	unsigned int pixelsPerClock, lstall, D, initalXmitDelay, w, S, ix, wx, p, l0, a, ax, l,
++			Delay, pixels;
++
++	if (pixelFormat == dm_n422 || pixelFormat == dm_420)
++		pixelsPerClock = 2;
++	// #all other modes operate at 1 pixel per clock
++	else
++		pixelsPerClock = 1;
++
++	//initial transmit delay as per PPS
++	initalXmitDelay = dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock);
++
++	//compute ssm delay
++	if (bpc == 8)
++		D = 81;
++	else if (bpc == 10)
++		D = 89;
++	else
++		D = 113;
++
++	//divide by pixel per cycle to compute slice width as seen by DSC
++	w = sliceWidth / pixelsPerClock;
++
++	//422 mode has an additional cycle of delay
++	if (pixelFormat == dm_s422)
++		S = 1;
++	else
++		S = 0;
++
++	//main calculation for the dscce
++	ix = initalXmitDelay + 45;
++	wx = (w + 2) / 3;
++	p = 3 * wx - w;
++	l0 = ix / w;
++	a = ix + p * l0;
++	ax = (a + 2) / 3 + D + 6 + 1;
++	l = (ax + wx - 1) / wx;
++	if ((ix % w) == 0 && p != 0)
++		lstall = 1;
++	else
++		lstall = 0;
++	Delay = l * wx * (numSlices - 1) + ax + S + lstall + 22;
++
++	//dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels
++	pixels = Delay * 3 * pixelsPerClock;
++	return pixels;
++}
++
++static unsigned int dscComputeDelay(enum output_format_class pixelFormat)
++{
++	unsigned int Delay = 0;
++
++	if (pixelFormat == dm_420) {
++		//   sfr
++		Delay = Delay + 2;
++		//   dsccif
++		Delay = Delay + 0;
++		//   dscc - input deserializer
++		Delay = Delay + 3;
++		//   dscc gets pixels every other cycle
++		Delay = Delay + 2;
++		//   dscc - input cdc fifo
++		Delay = Delay + 12;
++		//   dscc gets pixels every other cycle
++		Delay = Delay + 13;
++		//   dscc - cdc uncertainty
++		Delay = Delay + 2;
++		//   dscc - output cdc fifo
++		Delay = Delay + 7;
++		//   dscc gets pixels every other cycle
++		Delay = Delay + 3;
++		//   dscc - cdc uncertainty
++		Delay = Delay + 2;
++		//   dscc - output serializer
++		Delay = Delay + 1;
++		//   sft
++		Delay = Delay + 1;
++	} else if (pixelFormat == dm_n422) {
++		//   sfr
++		Delay = Delay + 2;
++		//   dsccif
++		Delay = Delay + 1;
++		//   dscc - input deserializer
++		Delay = Delay + 5;
++		//  dscc - input cdc fifo
++		Delay = Delay + 25;
++		//   dscc - cdc uncertainty
++		Delay = Delay + 2;
++		//   dscc - output cdc fifo
++		Delay = Delay + 10;
++		//   dscc - cdc uncertainty
++		Delay = Delay + 2;
++		//   dscc - output serializer
++		Delay = Delay + 1;
++		//   sft
++		Delay = Delay + 1;
++	} else {
++		//   sfr
++		Delay = Delay + 2;
++		//   dsccif
++		Delay = Delay + 0;
++		//   dscc - input deserializer
++		Delay = Delay + 3;
++		//   dscc - input cdc fifo
++		Delay = Delay + 12;
++		//   dscc - cdc uncertainty
++		Delay = Delay + 2;
++		//   dscc - output cdc fifo
++		Delay = Delay + 7;
++		//   dscc - output serializer
++		Delay = Delay + 1;
++		//   dscc - cdc uncertainty
++		Delay = Delay + 2;
++		//   sft
++		Delay = Delay + 1;
++	}
++
++	return Delay;
++}
++
++static bool CalculatePrefetchSchedule(
++		struct display_mode_lib *mode_lib,
++		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
++		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
++		Pipe *myPipe,
++		unsigned int DSCDelay,
++		double DPPCLKDelaySubtotal,
++		double DPPCLKDelaySCL,
++		double DPPCLKDelaySCLLBOnly,
++		double DPPCLKDelayCNVCFormater,
++		double DPPCLKDelayCNVCCursor,
++		double DISPCLKDelaySubtotal,
++		unsigned int ScalerRecoutWidth,
++		enum output_format_class OutputFormat,
++		unsigned int MaxInterDCNTileRepeaters,
++		unsigned int VStartup,
++		unsigned int MaxVStartup,
++		unsigned int GPUVMPageTableLevels,
++		bool GPUVMEnable,
++		HostVM *myHostVM,
++		bool DynamicMetadataEnable,
++		int DynamicMetadataLinesBeforeActiveRequired,
++		unsigned int DynamicMetadataTransmittedBytes,
++		bool DCCEnable,
++		double UrgentLatency,
++		double UrgentExtraLatency,
++		double TCalc,
++		unsigned int PDEAndMetaPTEBytesFrame,
++		unsigned int MetaRowByte,
++		unsigned int PixelPTEBytesPerRow,
++		double PrefetchSourceLinesY,
++		unsigned int SwathWidthY,
++		double BytePerPixelDETY,
++		double VInitPreFillY,
++		unsigned int MaxNumSwathY,
++		double PrefetchSourceLinesC,
++		double BytePerPixelDETC,
++		double VInitPreFillC,
++		unsigned int MaxNumSwathC,
++		unsigned int SwathHeightY,
++		unsigned int SwathHeightC,
++		double TWait,
++		bool XFCEnabled,
++		double XFCRemoteSurfaceFlipDelay,
++		bool ProgressiveToInterlaceUnitInOPP,
++		double *DSTXAfterScaler,
++		double *DSTYAfterScaler,
++		double *DestinationLinesForPrefetch,
++		double *PrefetchBandwidth,
++		double *DestinationLinesToRequestVMInVBlank,
++		double *DestinationLinesToRequestRowInVBlank,
++		double *VRatioPrefetchY,
++		double *VRatioPrefetchC,
++		double *RequiredPrefetchPixDataBWLuma,
++		double *RequiredPrefetchPixDataBWChroma,
++		unsigned int *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata,
++		double *Tno_bw,
++		double *prefetch_vmrow_bw,
++		unsigned int *swath_width_luma_ub,
++		unsigned int *swath_width_chroma_ub,
++		unsigned int *VUpdateOffsetPix,
++		double *VUpdateWidthPix,
++		double *VReadyOffsetPix)
++{
++	bool MyError = false;
++	unsigned int DPPCycles, DISPCLKCycles;
++	double DSTTotalPixelsAfterScaler, TotalRepeaterDelayTime;
++	double Tdm, LineTime, Tsetup;
++	double dst_y_prefetch_equ;
++	double Tsw_oto;
++	double prefetch_bw_oto;
++	double Tvm_oto;
++	double Tr0_oto;
++	double Tvm_oto_lines;
++	double Tr0_oto_lines;
++	double Tsw_oto_lines;
++	double dst_y_prefetch_oto;
++	double TimeForFetchingMetaPTE = 0;
++	double TimeForFetchingRowInVBlank = 0;
++	double LinesToRequestPrefetchPixelData = 0;
++	double HostVMInefficiencyFactor;
++	unsigned int HostVMDynamicLevels;
++
++	if (GPUVMEnable == true && myHostVM->Enable == true) {
++		HostVMInefficiencyFactor =
++				PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData
++						/ PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly;
++		HostVMDynamicLevels = myHostVM->MaxPageTableLevels
++				- myHostVM->CachedPageTableLevels;
++	} else {
++		HostVMInefficiencyFactor = 1;
++		HostVMDynamicLevels = 0;
++	}
++
++	if (myPipe->ScalerEnabled)
++		DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCL;
++	else
++		DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly;
++
++	DPPCycles = DPPCycles + DPPCLKDelayCNVCFormater + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor;
++
++	DISPCLKCycles = DISPCLKDelaySubtotal;
++
++	if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0)
++		return true;
++
++	*DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK
++			+ DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK + DSCDelay;
++
++	if (myPipe->DPPPerPlane > 1)
++		*DSTXAfterScaler = *DSTXAfterScaler + ScalerRecoutWidth;
++
++	if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && ProgressiveToInterlaceUnitInOPP))
++		*DSTYAfterScaler = 1;
++	else
++		*DSTYAfterScaler = 0;
++
++	DSTTotalPixelsAfterScaler = ((double) (*DSTYAfterScaler * myPipe->HTotal)) + *DSTXAfterScaler;
++	*DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / myPipe->HTotal, 1);
++	*DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * myPipe->HTotal));
++
++	*VUpdateOffsetPix = dml_ceil(myPipe->HTotal / 4.0, 1);
++	TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / myPipe->DPPCLK + 3.0 / myPipe->DISPCLK);
++	*VUpdateWidthPix = (14.0 / myPipe->DCFCLKDeepSleep + 12.0 / myPipe->DPPCLK + TotalRepeaterDelayTime)
++			* myPipe->PixelClock;
++
++	*VReadyOffsetPix = dml_max(
++			150.0 / myPipe->DPPCLK,
++			TotalRepeaterDelayTime + 20.0 / myPipe->DCFCLKDeepSleep + 10.0 / myPipe->DPPCLK)
++			* myPipe->PixelClock;
++
++	Tsetup = (double) (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / myPipe->PixelClock;
++
++	LineTime = (double) myPipe->HTotal / myPipe->PixelClock;
++
++	if (DynamicMetadataEnable) {
++		double Tdmbf, Tdmec, Tdmsks;
++
++		Tdm = dml_max(0.0, UrgentExtraLatency - TCalc);
++		Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / myPipe->DISPCLK;
++		Tdmec = LineTime;
++		if (DynamicMetadataLinesBeforeActiveRequired == -1)
++			Tdmsks = myPipe->VBlank * LineTime / 2.0;
++		else
++			Tdmsks = DynamicMetadataLinesBeforeActiveRequired * LineTime;
++		if (myPipe->InterlaceEnable && !ProgressiveToInterlaceUnitInOPP)
++			Tdmsks = Tdmsks / 2;
++		if (VStartup * LineTime
++				< Tsetup + TWait + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) {
++			MyError = true;
++			*VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = (Tsetup + TWait
++					+ UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) / LineTime;
++		} else
++			*VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = 0.0;
++	} else
++		Tdm = 0;
++
++	if (GPUVMEnable) {
++		if (GPUVMPageTableLevels >= 3)
++			*Tno_bw = UrgentExtraLatency + UrgentLatency * ((GPUVMPageTableLevels - 2) * (myHostVM->MaxPageTableLevels + 1) - 1);
++		else
++			*Tno_bw = 0;
++	} else if (!DCCEnable)
++		*Tno_bw = LineTime;
++	else
++		*Tno_bw = LineTime / 4;
++
++	dst_y_prefetch_equ = VStartup - dml_max(TCalc + TWait, XFCRemoteSurfaceFlipDelay) / LineTime
++			- (Tsetup + Tdm) / LineTime
++			- (*DSTYAfterScaler + *DSTXAfterScaler / myPipe->HTotal);
++
++	Tsw_oto = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime;
++
++	if (myPipe->SourceScan == dm_horz) {
++		*swath_width_luma_ub = dml_ceil(SwathWidthY - 1, myPipe->BlockWidth256BytesY) + myPipe->BlockWidth256BytesY;
++		*swath_width_chroma_ub = dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockWidth256BytesC) + myPipe->BlockWidth256BytesC;
++	} else {
++		*swath_width_luma_ub = dml_ceil(SwathWidthY - 1, myPipe->BlockHeight256BytesY) + myPipe->BlockHeight256BytesY;
++		*swath_width_chroma_ub = dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockHeight256BytesC) + myPipe->BlockHeight256BytesC;
++	}
++
++	prefetch_bw_oto = (PrefetchSourceLinesY * *swath_width_luma_ub * dml_ceil(BytePerPixelDETY, 1) + PrefetchSourceLinesC * *swath_width_chroma_ub * dml_ceil(BytePerPixelDETC, 2)) / Tsw_oto;
++
++
++	if (GPUVMEnable == true) {
++		Tvm_oto = dml_max(*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto,
++				dml_max(UrgentExtraLatency + UrgentLatency * (GPUVMPageTableLevels * (HostVMDynamicLevels + 1) - 1),
++					LineTime / 4.0));
++	} else
++		Tvm_oto = LineTime / 4.0;
++
++	if ((GPUVMEnable == true || DCCEnable == true)) {
++		Tr0_oto = dml_max(
++				(MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto,
++				dml_max(UrgentLatency * (HostVMDynamicLevels + 1), dml_max(LineTime - Tvm_oto, LineTime / 4)));
++	} else
++		Tr0_oto = (LineTime - Tvm_oto) / 2.0;
++
++	Tvm_oto_lines = dml_ceil(4 * Tvm_oto / LineTime, 1) / 4.0;
++	Tr0_oto_lines = dml_ceil(4 * Tr0_oto / LineTime, 1) / 4.0;
++	Tsw_oto_lines = dml_ceil(4 * Tsw_oto / LineTime, 1) / 4.0;
++	dst_y_prefetch_oto = Tvm_oto_lines + 2 * Tr0_oto_lines + Tsw_oto_lines + 0.75;
++
++	dst_y_prefetch_equ = dml_floor(4.0 * (dst_y_prefetch_equ + 0.125), 1) / 4.0;
++
++	if (dst_y_prefetch_oto < dst_y_prefetch_equ)
++		*DestinationLinesForPrefetch = dst_y_prefetch_oto;
++	else
++		*DestinationLinesForPrefetch = dst_y_prefetch_equ;
++
++	dml_print("DML: VStartup: %d\n", VStartup);
++	dml_print("DML: TCalc: %f\n", TCalc);
++	dml_print("DML: TWait: %f\n", TWait);
++	dml_print("DML: XFCRemoteSurfaceFlipDelay: %f\n", XFCRemoteSurfaceFlipDelay);
++	dml_print("DML: LineTime: %f\n", LineTime);
++	dml_print("DML: Tsetup: %f\n", Tsetup);
++	dml_print("DML: Tdm: %f\n", Tdm);
++	dml_print("DML: DSTYAfterScaler: %f\n", *DSTYAfterScaler);
++	dml_print("DML: DSTXAfterScaler: %f\n", *DSTXAfterScaler);
++	dml_print("DML: HTotal: %d\n", myPipe->HTotal);
++
++	*PrefetchBandwidth = 0;
++	*DestinationLinesToRequestVMInVBlank = 0;
++	*DestinationLinesToRequestRowInVBlank = 0;
++	*VRatioPrefetchY = 0;
++	*VRatioPrefetchC = 0;
++	*RequiredPrefetchPixDataBWLuma = 0;
++	if (*DestinationLinesForPrefetch > 1) {
++		double PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte
++				+ 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor
++				+ PrefetchSourceLinesY * *swath_width_luma_ub * dml_ceil(BytePerPixelDETY, 1)
++				+ PrefetchSourceLinesC * *swath_width_chroma_ub * dml_ceil(BytePerPixelDETC, 2))
++				/ (*DestinationLinesForPrefetch * LineTime - *Tno_bw);
++
++		double PrefetchBandwidth2 = (PDEAndMetaPTEBytesFrame *
++				HostVMInefficiencyFactor + PrefetchSourceLinesY *
++				*swath_width_luma_ub * dml_ceil(BytePerPixelDETY, 1) +
++				PrefetchSourceLinesC * *swath_width_chroma_ub *
++				dml_ceil(BytePerPixelDETC, 2)) /
++				(*DestinationLinesForPrefetch * LineTime - *Tno_bw - 2 *
++				UrgentLatency * (1 + HostVMDynamicLevels));
++
++		double PrefetchBandwidth3 = (2 * MetaRowByte + 2 * PixelPTEBytesPerRow
++				* HostVMInefficiencyFactor + PrefetchSourceLinesY *
++				*swath_width_luma_ub * dml_ceil(BytePerPixelDETY, 1) +
++				PrefetchSourceLinesC * *swath_width_chroma_ub *
++				dml_ceil(BytePerPixelDETC, 2)) /
++				(*DestinationLinesForPrefetch * LineTime -
++				UrgentExtraLatency - UrgentLatency * (GPUVMPageTableLevels
++				* (HostVMDynamicLevels + 1) - 1));
++
++		double PrefetchBandwidth4 = (PrefetchSourceLinesY * *swath_width_luma_ub *
++				dml_ceil(BytePerPixelDETY, 1) + PrefetchSourceLinesC *
++				*swath_width_chroma_ub * dml_ceil(BytePerPixelDETC, 2)) /
++				(*DestinationLinesForPrefetch * LineTime -
++				UrgentExtraLatency - UrgentLatency * (GPUVMPageTableLevels
++				* (HostVMDynamicLevels + 1) - 1) - 2 * UrgentLatency *
++				(1 + HostVMDynamicLevels));
++
++		if (VStartup == MaxVStartup && (PrefetchBandwidth1 > 4 * prefetch_bw_oto) && (*DestinationLinesForPrefetch - dml_ceil(Tsw_oto_lines, 1) / 4.0 - 0.75) * LineTime - *Tno_bw > 0) {
++			PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor) / ((*DestinationLinesForPrefetch - dml_ceil(Tsw_oto_lines, 1) / 4.0 - 0.75) * LineTime - *Tno_bw);
++		}
++		if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth1 >= UrgentExtraLatency + UrgentLatency * (GPUVMPageTableLevels * (HostVMDynamicLevels + 1) - 1) && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth1 >= UrgentLatency * (1 + HostVMDynamicLevels)) {
++			*PrefetchBandwidth = PrefetchBandwidth1;
++		} else if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth2 >= UrgentExtraLatency + UrgentLatency * (GPUVMPageTableLevels * (HostVMDynamicLevels + 1) - 1) && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth2 < UrgentLatency * (1 + HostVMDynamicLevels)) {
++			*PrefetchBandwidth = PrefetchBandwidth2;
++		} else if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth3 < UrgentExtraLatency + UrgentLatency * (GPUVMPageTableLevels * (HostVMDynamicLevels + 1) - 1) && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth3 >= UrgentLatency * (1 + HostVMDynamicLevels)) {
++			*PrefetchBandwidth = PrefetchBandwidth3;
++		} else {
++			*PrefetchBandwidth = PrefetchBandwidth4;
++		}
++
++		if (GPUVMEnable) {
++			TimeForFetchingMetaPTE = dml_max(*Tno_bw + (double) PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / *PrefetchBandwidth,
++					dml_max(UrgentExtraLatency + UrgentLatency * (GPUVMPageTableLevels * (HostVMDynamicLevels + 1) - 1), LineTime / 4));
++		} else {
++// 5/30/2018 - This was an optimization requested from Sy but now NumberOfCursors is no longer a factor
++//             so if this needs to be reinstated, then it should be officially done in the VBA code as well.
++//			if (mode_lib->NumberOfCursors > 0 || XFCEnabled)
++				TimeForFetchingMetaPTE = LineTime / 4;
++//			else
++//				TimeForFetchingMetaPTE = 0.0;
++		}
++
++		if ((GPUVMEnable == true || DCCEnable == true)) {
++			TimeForFetchingRowInVBlank =
++					dml_max(
++							(MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor)
++									/ *PrefetchBandwidth,
++							dml_max(
++									UrgentLatency * (1 + HostVMDynamicLevels),
++									dml_max(
++											(LineTime
++													- TimeForFetchingMetaPTE) / 2.0,
++											LineTime
++													/ 4.0)));
++		} else {
++// See note above dated 5/30/2018
++//			if (NumberOfCursors > 0 || XFCEnabled)
++				TimeForFetchingRowInVBlank = (LineTime - TimeForFetchingMetaPTE) / 2.0;
++//			else // TODO: Did someone else add this??
++//				TimeForFetchingRowInVBlank = 0.0;
++		}
++
++		*DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0;
++
++		*DestinationLinesToRequestRowInVBlank = dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0) / 4.0;
++
++		LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch
++// See note above dated 5/30/2018
++//						- ((NumberOfCursors > 0 || GPUVMEnable || DCCEnable) ?
++						- ((GPUVMEnable || DCCEnable) ?
++								(*DestinationLinesToRequestVMInVBlank + 2 * *DestinationLinesToRequestRowInVBlank) :
++								0.0); // TODO: Did someone else add this??
++
++		if (LinesToRequestPrefetchPixelData > 0) {
++
++			*VRatioPrefetchY = (double) PrefetchSourceLinesY
++					/ LinesToRequestPrefetchPixelData;
++			*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
++			if ((SwathHeightY > 4) && (VInitPreFillY > 3)) {
++				if (LinesToRequestPrefetchPixelData > (VInitPreFillY - 3.0) / 2.0) {
++					*VRatioPrefetchY =
++							dml_max(
++									(double) PrefetchSourceLinesY
++											/ LinesToRequestPrefetchPixelData,
++									(double) MaxNumSwathY
++											* SwathHeightY
++											/ (LinesToRequestPrefetchPixelData
++													- (VInitPreFillY
++															- 3.0)
++															/ 2.0));
++					*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
++				} else {
++					MyError = true;
++					*VRatioPrefetchY = 0;
++				}
++			}
++
++			*VRatioPrefetchC = (double) PrefetchSourceLinesC
++					/ LinesToRequestPrefetchPixelData;
++			*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
++
++			if ((SwathHeightC > 4)) {
++				if (LinesToRequestPrefetchPixelData > (VInitPreFillC - 3.0) / 2.0) {
++					*VRatioPrefetchC =
++							dml_max(
++									*VRatioPrefetchC,
++									(double) MaxNumSwathC
++											* SwathHeightC
++											/ (LinesToRequestPrefetchPixelData
++													- (VInitPreFillC
++															- 3.0)
++															/ 2.0));
++					*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
++				} else {
++					MyError = true;
++					*VRatioPrefetchC = 0;
++				}
++			}
++
++			*RequiredPrefetchPixDataBWLuma = myPipe->DPPPerPlane
++					* (double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData
++					* dml_ceil(BytePerPixelDETY, 1)
++					* *swath_width_luma_ub / LineTime;
++			*RequiredPrefetchPixDataBWChroma = myPipe->DPPPerPlane
++					* (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData
++					* dml_ceil(BytePerPixelDETC, 2)
++					* *swath_width_chroma_ub / LineTime;
++		} else {
++			MyError = true;
++			*VRatioPrefetchY = 0;
++			*VRatioPrefetchC = 0;
++			*RequiredPrefetchPixDataBWLuma = 0;
++			*RequiredPrefetchPixDataBWChroma = 0;
++		}
++
++		dml_print("DML: Tvm: %fus\n", TimeForFetchingMetaPTE);
++		dml_print("DML: Tr0: %fus\n", TimeForFetchingRowInVBlank);
++		dml_print("DML: Tsw: %fus\n", (double)(*DestinationLinesForPrefetch) * LineTime - TimeForFetchingMetaPTE - TimeForFetchingRowInVBlank);
++		dml_print("DML: Tpre: %fus\n", (double)(*DestinationLinesForPrefetch) * LineTime);
++		dml_print("DML: row_bytes = dpte_row_bytes (per_pipe) = PixelPTEBytesPerRow = : %d\n", PixelPTEBytesPerRow);
++
++	} else {
++		MyError = true;
++	}
++
++	{
++		double prefetch_vm_bw;
++		double prefetch_row_bw;
++
++		if (PDEAndMetaPTEBytesFrame == 0) {
++			prefetch_vm_bw = 0;
++		} else if (*DestinationLinesToRequestVMInVBlank > 0) {
++			prefetch_vm_bw = PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / (*DestinationLinesToRequestVMInVBlank * LineTime);
++		} else {
++			prefetch_vm_bw = 0;
++			MyError = true;
++		}
++		if (MetaRowByte + PixelPTEBytesPerRow == 0) {
++			prefetch_row_bw = 0;
++		} else if (*DestinationLinesToRequestRowInVBlank > 0) {
++			prefetch_row_bw = (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / (*DestinationLinesToRequestRowInVBlank * LineTime);
++		} else {
++			prefetch_row_bw = 0;
++			MyError = true;
++		}
++
++		*prefetch_vmrow_bw = dml_max(prefetch_vm_bw, prefetch_row_bw);
++	}
++
++	if (MyError) {
++		*PrefetchBandwidth = 0;
++		TimeForFetchingMetaPTE = 0;
++		TimeForFetchingRowInVBlank = 0;
++		*DestinationLinesToRequestVMInVBlank = 0;
++		*DestinationLinesToRequestRowInVBlank = 0;
++		*DestinationLinesForPrefetch = 0;
++		LinesToRequestPrefetchPixelData = 0;
++		*VRatioPrefetchY = 0;
++		*VRatioPrefetchC = 0;
++		*RequiredPrefetchPixDataBWLuma = 0;
++		*RequiredPrefetchPixDataBWChroma = 0;
++	}
++
++	return MyError;
++}
++
++static double RoundToDFSGranularityUp(double Clock, double VCOSpeed)
++{
++	return VCOSpeed * 4 / dml_floor(VCOSpeed * 4 / Clock, 1);
++}
++
++static double RoundToDFSGranularityDown(double Clock, double VCOSpeed)
++{
++	return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4 / Clock, 1);
++}
++
++static double CalculateDCCConfiguration(
++		bool DCCEnabled,
++		bool DCCProgrammingAssumesScanDirectionUnknown,
++		unsigned int ViewportWidth,
++		unsigned int ViewportHeight,
++		double DETBufferSize,
++		unsigned int RequestHeight256Byte,
++		unsigned int SwathHeight,
++		enum dm_swizzle_mode TilingFormat,
++		unsigned int BytePerPixel,
++		enum scan_direction_class ScanOrientation,
++		unsigned int *MaxUncompressedBlock,
++		unsigned int *MaxCompressedBlock,
++		unsigned int *Independent64ByteBlock)
++{
++	double MaximumDCCCompressionSurface = 0.0;
++	enum {
++		REQ_256Bytes,
++		REQ_128BytesNonContiguous,
++		REQ_128BytesContiguous,
++		REQ_NA
++	} Request = REQ_NA;
++
++	if (DCCEnabled == true) {
++		if (DCCProgrammingAssumesScanDirectionUnknown == true) {
++			if (DETBufferSize >= RequestHeight256Byte * ViewportWidth * BytePerPixel
++					&& DETBufferSize
++							>= 256 / RequestHeight256Byte
++									* ViewportHeight) {
++				Request = REQ_256Bytes;
++			} else if ((DETBufferSize
++					< RequestHeight256Byte * ViewportWidth * BytePerPixel
++					&& (BytePerPixel == 2 || BytePerPixel == 4))
++					|| (DETBufferSize
++							< 256 / RequestHeight256Byte
++									* ViewportHeight
++							&& BytePerPixel == 8
++							&& (TilingFormat == dm_sw_4kb_d
++									|| TilingFormat
++											== dm_sw_4kb_d_x
++									|| TilingFormat
++											== dm_sw_var_d
++									|| TilingFormat
++											== dm_sw_var_d_x
++									|| TilingFormat
++											== dm_sw_64kb_d
++									|| TilingFormat
++											== dm_sw_64kb_d_x
++									|| TilingFormat
++											== dm_sw_64kb_d_t
++									|| TilingFormat
++											== dm_sw_64kb_r_x))) {
++				Request = REQ_128BytesNonContiguous;
++			} else {
++				Request = REQ_128BytesContiguous;
++			}
++		} else {
++			if (BytePerPixel == 1) {
++				if (ScanOrientation == dm_vert || SwathHeight == 16) {
++					Request = REQ_256Bytes;
++				} else {
++					Request = REQ_128BytesContiguous;
++				}
++			} else if (BytePerPixel == 2) {
++				if ((ScanOrientation == dm_vert && SwathHeight == 16) || (ScanOrientation != dm_vert && SwathHeight == 8)) {
++					Request = REQ_256Bytes;
++				} else if (ScanOrientation == dm_vert) {
++					Request = REQ_128BytesContiguous;
++				} else {
++					Request = REQ_128BytesNonContiguous;
++				}
++			} else if (BytePerPixel == 4) {
++				if (SwathHeight == 8) {
++					Request = REQ_256Bytes;
++				} else if (ScanOrientation == dm_vert) {
++					Request = REQ_128BytesContiguous;
++				} else {
++					Request = REQ_128BytesNonContiguous;
++				}
++			} else if (BytePerPixel == 8) {
++				if (TilingFormat == dm_sw_4kb_d || TilingFormat == dm_sw_4kb_d_x
++						|| TilingFormat == dm_sw_var_d
++						|| TilingFormat == dm_sw_var_d_x
++						|| TilingFormat == dm_sw_64kb_d
++						|| TilingFormat == dm_sw_64kb_d_x
++						|| TilingFormat == dm_sw_64kb_d_t
++						|| TilingFormat == dm_sw_64kb_r_x) {
++					if ((ScanOrientation == dm_vert && SwathHeight == 8)
++							|| (ScanOrientation != dm_vert
++									&& SwathHeight == 4)) {
++						Request = REQ_256Bytes;
++					} else if (ScanOrientation != dm_vert) {
++						Request = REQ_128BytesContiguous;
++					} else {
++						Request = REQ_128BytesNonContiguous;
++					}
++				} else {
++					if (ScanOrientation != dm_vert || SwathHeight == 8) {
++						Request = REQ_256Bytes;
++					} else {
++						Request = REQ_128BytesContiguous;
++					}
++				}
++			}
++		}
++	} else {
++		Request = REQ_NA;
++	}
++
++	if (Request == REQ_256Bytes) {
++		*MaxUncompressedBlock = 256;
++		*MaxCompressedBlock = 256;
++		*Independent64ByteBlock = false;
++		MaximumDCCCompressionSurface = 4.0;
++	} else if (Request == REQ_128BytesContiguous) {
++		*MaxUncompressedBlock = 128;
++		*MaxCompressedBlock = 128;
++		*Independent64ByteBlock = false;
++		MaximumDCCCompressionSurface = 2.0;
++	} else if (Request == REQ_128BytesNonContiguous) {
++		*MaxUncompressedBlock = 256;
++		*MaxCompressedBlock = 64;
++		*Independent64ByteBlock = true;
++		MaximumDCCCompressionSurface = 4.0;
++	} else {
++		*MaxUncompressedBlock = 0;
++		*MaxCompressedBlock = 0;
++		*Independent64ByteBlock = 0;
++		MaximumDCCCompressionSurface = 0.0;
++	}
++
++	return MaximumDCCCompressionSurface;
++}
++
++static double CalculatePrefetchSourceLines(
++		struct display_mode_lib *mode_lib,
++		double VRatio,
++		double vtaps,
++		bool Interlace,
++		bool ProgressiveToInterlaceUnitInOPP,
++		unsigned int SwathHeight,
++		unsigned int ViewportYStart,
++		double *VInitPreFill,
++		unsigned int *MaxNumSwath)
++{
++	unsigned int MaxPartialSwath;
++
++	if (ProgressiveToInterlaceUnitInOPP)
++		*VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1);
++	else
++		*VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1);
++
++	if (!mode_lib->vba.IgnoreViewportPositioning) {
++
++		*MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0;
++
++		if (*VInitPreFill > 1.0)
++			MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight;
++		else
++			MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2)
++					% SwathHeight;
++		MaxPartialSwath = dml_max(1U, MaxPartialSwath);
++
++	} else {
++
++		if (ViewportYStart != 0)
++			dml_print(
++					"WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n");
++
++		*MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1);
++
++		if (*VInitPreFill > 1.0)
++			MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight;
++		else
++			MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 1)
++					% SwathHeight;
++	}
++
++	return *MaxNumSwath * SwathHeight + MaxPartialSwath;
++}
++
++static unsigned int CalculateVMAndRowBytes(
++		struct display_mode_lib *mode_lib,
++		bool DCCEnable,
++		unsigned int BlockHeight256Bytes,
++		unsigned int BlockWidth256Bytes,
++		enum source_format_class SourcePixelFormat,
++		unsigned int SurfaceTiling,
++		unsigned int BytePerPixel,
++		enum scan_direction_class ScanDirection,
++		unsigned int ViewportWidth,
++		unsigned int ViewportHeight,
++		unsigned int SwathWidth,
++		bool GPUVMEnable,
++		bool HostVMEnable,
++		unsigned int HostVMMaxPageTableLevels,
++		unsigned int HostVMCachedPageTableLevels,
++		unsigned int VMMPageSize,
++		unsigned int PTEBufferSizeInRequests,
++		unsigned int Pitch,
++		unsigned int DCCMetaPitch,
++		unsigned int *MacroTileWidth,
++		unsigned int *MetaRowByte,
++		unsigned int *PixelPTEBytesPerRow,
++		bool *PTEBufferSizeNotExceeded,
++		unsigned int *dpte_row_width_ub,
++		unsigned int *dpte_row_height,
++		unsigned int *MetaRequestWidth,
++		unsigned int *MetaRequestHeight,
++		unsigned int *meta_row_width,
++		unsigned int *meta_row_height,
++		unsigned int *vm_group_bytes,
++		long         *dpte_group_bytes,
++		unsigned int *PixelPTEReqWidth,
++		unsigned int *PixelPTEReqHeight,
++		unsigned int *PTERequestSize,
++		unsigned int *DPDE0BytesFrame,
++		unsigned int *MetaPTEBytesFrame)
++{
++	unsigned int MPDEBytesFrame;
++	unsigned int DCCMetaSurfaceBytes;
++	unsigned int MacroTileSizeBytes;
++	unsigned int MacroTileHeight;
++	unsigned int ExtraDPDEBytesFrame;
++	unsigned int PDEAndMetaPTEBytesFrame;
++	unsigned int PixelPTEReqHeightPTEs;
++
++	if (DCCEnable == true) {
++		*MetaRequestHeight = 8 * BlockHeight256Bytes;
++		*MetaRequestWidth = 8 * BlockWidth256Bytes;
++		if (ScanDirection == dm_horz) {
++			*meta_row_height = *MetaRequestHeight;
++			*meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestWidth)
++					+ *MetaRequestWidth;
++			*MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0;
++		} else {
++			*meta_row_height = *MetaRequestWidth;
++			*meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestHeight)
++					+ *MetaRequestHeight;
++			*MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0;
++		}
++		if (ScanDirection == dm_horz) {
++			DCCMetaSurfaceBytes = DCCMetaPitch
++					* (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes)
++							+ 64 * BlockHeight256Bytes) * BytePerPixel
++					/ 256;
++		} else {
++			DCCMetaSurfaceBytes = DCCMetaPitch
++					* (dml_ceil(
++							(double) ViewportHeight - 1,
++							64 * BlockHeight256Bytes)
++							+ 64 * BlockHeight256Bytes) * BytePerPixel
++					/ 256;
++		}
++		if (GPUVMEnable == true) {
++			*MetaPTEBytesFrame = (dml_ceil(
++					(double) (DCCMetaSurfaceBytes - VMMPageSize)
++							/ (8 * VMMPageSize),
++					1) + 1) * 64;
++			MPDEBytesFrame = 128 * ((mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxPageTableLevels + 1) - 2);
++		} else {
++			*MetaPTEBytesFrame = 0;
++			MPDEBytesFrame = 0;
++		}
++	} else {
++		*MetaPTEBytesFrame = 0;
++		MPDEBytesFrame = 0;
++		*MetaRowByte = 0;
++	}
++
++	if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_lvp) {
++		MacroTileSizeBytes = 256;
++		MacroTileHeight = BlockHeight256Bytes;
++	} else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x
++			|| SurfaceTiling == dm_sw_4kb_d || SurfaceTiling == dm_sw_4kb_d_x) {
++		MacroTileSizeBytes = 4096;
++		MacroTileHeight = 4 * BlockHeight256Bytes;
++	} else if (SurfaceTiling == dm_sw_64kb_s || SurfaceTiling == dm_sw_64kb_s_t
++			|| SurfaceTiling == dm_sw_64kb_s_x || SurfaceTiling == dm_sw_64kb_d
++			|| SurfaceTiling == dm_sw_64kb_d_t || SurfaceTiling == dm_sw_64kb_d_x
++			|| SurfaceTiling == dm_sw_64kb_r_x) {
++		MacroTileSizeBytes = 65536;
++		MacroTileHeight = 16 * BlockHeight256Bytes;
++	} else {
++		MacroTileSizeBytes = 262144;
++		MacroTileHeight = 32 * BlockHeight256Bytes;
++	}
++	*MacroTileWidth = MacroTileSizeBytes / BytePerPixel / MacroTileHeight;
++
++	if (GPUVMEnable == true && (mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxPageTableLevels + 1) > 2) {
++		if (ScanDirection == dm_horz) {
++			*DPDE0BytesFrame = 64 * (dml_ceil(((Pitch * (dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1);
++		} else {
++			*DPDE0BytesFrame = 64 * (dml_ceil(((Pitch * (dml_ceil((double) SwathWidth - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1);
++		}
++		ExtraDPDEBytesFrame = 128 * ((mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxPageTableLevels + 1) - 3);
++	} else {
++		*DPDE0BytesFrame = 0;
++		ExtraDPDEBytesFrame = 0;
++	}
++
++	PDEAndMetaPTEBytesFrame = *MetaPTEBytesFrame + MPDEBytesFrame + *DPDE0BytesFrame
++			+ ExtraDPDEBytesFrame;
++
++	if (HostVMEnable == true) {
++		PDEAndMetaPTEBytesFrame = PDEAndMetaPTEBytesFrame * (1 + 8 * (HostVMMaxPageTableLevels - HostVMCachedPageTableLevels));
++	}
++
++	if (GPUVMEnable == true) {
++		double FractionOfPTEReturnDrop;
++
++		if (SurfaceTiling == dm_sw_linear) {
++			PixelPTEReqHeightPTEs = 1;
++			*PixelPTEReqHeight = 1;
++			*PixelPTEReqWidth = 8.0 * VMMPageSize / BytePerPixel;
++			*PTERequestSize = 64;
++			FractionOfPTEReturnDrop = 0;
++		} else if (MacroTileSizeBytes == 4096) {
++			PixelPTEReqHeightPTEs = 1;
++			*PixelPTEReqHeight = MacroTileHeight;
++			*PixelPTEReqWidth = 8 * *MacroTileWidth;
++			*PTERequestSize = 64;
++			if (ScanDirection == dm_horz)
++				FractionOfPTEReturnDrop = 0;
++			else
++				FractionOfPTEReturnDrop = 7 / 8;
++		} else if (VMMPageSize == 4096 && MacroTileSizeBytes > 4096) {
++			PixelPTEReqHeightPTEs = 16;
++			*PixelPTEReqHeight = 16 * BlockHeight256Bytes;
++			*PixelPTEReqWidth = 16 * BlockWidth256Bytes;
++			*PTERequestSize = 128;
++			FractionOfPTEReturnDrop = 0;
++		} else {
++			PixelPTEReqHeightPTEs = 1;
++			*PixelPTEReqHeight = MacroTileHeight;
++			*PixelPTEReqWidth = 8 * *MacroTileWidth;
++			*PTERequestSize = 64;
++			FractionOfPTEReturnDrop = 0;
++		}
++
++		if (SurfaceTiling == dm_sw_linear) {
++			*dpte_row_height = dml_min(128,
++					1 << (unsigned int) dml_floor(
++						dml_log2(
++							(double) PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch),
++						1));
++			*dpte_row_width_ub = (dml_ceil((double) (Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth;
++			*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize;
++		} else if (ScanDirection == dm_horz) {
++			*dpte_row_height = *PixelPTEReqHeight;
++			*dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth;
++			*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize;
++		} else {
++			*dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth);
++			*dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight;
++			*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize;
++		}
++		if (*PixelPTEBytesPerRow * (1 - FractionOfPTEReturnDrop)
++				<= 64 * PTEBufferSizeInRequests) {
++			*PTEBufferSizeNotExceeded = true;
++		} else {
++			*PTEBufferSizeNotExceeded = false;
++		}
++	} else {
++		*PixelPTEBytesPerRow = 0;
++		*PTEBufferSizeNotExceeded = true;
++	}
++	dml_print("DML: vm_bytes = meta_pte_bytes_per_frame (per_pipe) = MetaPTEBytesFrame = : %d\n", *MetaPTEBytesFrame);
++
++	if (HostVMEnable == true) {
++		*PixelPTEBytesPerRow = *PixelPTEBytesPerRow * (1 + 8 * (HostVMMaxPageTableLevels - HostVMCachedPageTableLevels));
++	}
++
++	if (HostVMEnable == true) {
++		*vm_group_bytes = 512;
++		*dpte_group_bytes = 512;
++	} else if (GPUVMEnable == true) {
++		*vm_group_bytes = 2048;
++		if (SurfaceTiling != dm_sw_linear && PixelPTEReqHeightPTEs == 1 && ScanDirection != dm_horz) {
++			*dpte_group_bytes = 512;
++		} else {
++			*dpte_group_bytes = 2048;
++		}
++	} else {
++		*vm_group_bytes = 0;
++		*dpte_group_bytes = 0;
++	}
++
++	return PDEAndMetaPTEBytesFrame;
++}
++
++static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
++		struct display_mode_lib *mode_lib)
++{
++	struct vba_vars_st *locals = &mode_lib->vba;
++	unsigned int j, k;
++
++	mode_lib->vba.WritebackDISPCLK = 0.0;
++	mode_lib->vba.DISPCLKWithRamping = 0;
++	mode_lib->vba.DISPCLKWithoutRamping = 0;
++	mode_lib->vba.GlobalDPPCLK = 0.0;
++
++	// DISPCLK and DPPCLK Calculation
++	//
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.WritebackEnable[k]) {
++			mode_lib->vba.WritebackDISPCLK =
++					dml_max(
++							mode_lib->vba.WritebackDISPCLK,
++							CalculateWriteBackDISPCLK(
++									mode_lib->vba.WritebackPixelFormat[k],
++									mode_lib->vba.PixelClock[k],
++									mode_lib->vba.WritebackHRatio[k],
++									mode_lib->vba.WritebackVRatio[k],
++									mode_lib->vba.WritebackLumaHTaps[k],
++									mode_lib->vba.WritebackLumaVTaps[k],
++									mode_lib->vba.WritebackChromaHTaps[k],
++									mode_lib->vba.WritebackChromaVTaps[k],
++									mode_lib->vba.WritebackDestinationWidth[k],
++									mode_lib->vba.HTotal[k],
++									mode_lib->vba.WritebackChromaLineBufferWidth));
++		}
++	}
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.HRatio[k] > 1) {
++			locals->PSCL_THROUGHPUT_LUMA[k] = dml_min(
++					mode_lib->vba.MaxDCHUBToPSCLThroughput,
++					mode_lib->vba.MaxPSCLToLBThroughput
++							* mode_lib->vba.HRatio[k]
++							/ dml_ceil(
++									mode_lib->vba.htaps[k]
++											/ 6.0,
++									1));
++		} else {
++			locals->PSCL_THROUGHPUT_LUMA[k] = dml_min(
++					mode_lib->vba.MaxDCHUBToPSCLThroughput,
++					mode_lib->vba.MaxPSCLToLBThroughput);
++		}
++
++		mode_lib->vba.DPPCLKUsingSingleDPPLuma =
++				mode_lib->vba.PixelClock[k]
++						* dml_max(
++								mode_lib->vba.vtaps[k] / 6.0
++										* dml_min(
++												1.0,
++												mode_lib->vba.HRatio[k]),
++								dml_max(
++										mode_lib->vba.HRatio[k]
++												* mode_lib->vba.VRatio[k]
++												/ locals->PSCL_THROUGHPUT_LUMA[k],
++										1.0));
++
++		if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6)
++				&& mode_lib->vba.DPPCLKUsingSingleDPPLuma
++						< 2 * mode_lib->vba.PixelClock[k]) {
++			mode_lib->vba.DPPCLKUsingSingleDPPLuma = 2 * mode_lib->vba.PixelClock[k];
++		}
++
++		if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
++				&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
++			locals->PSCL_THROUGHPUT_CHROMA[k] = 0.0;
++			locals->DPPCLKUsingSingleDPP[k] =
++					mode_lib->vba.DPPCLKUsingSingleDPPLuma;
++		} else {
++			if (mode_lib->vba.HRatio[k] > 1) {
++				locals->PSCL_THROUGHPUT_CHROMA[k] =
++						dml_min(
++								mode_lib->vba.MaxDCHUBToPSCLThroughput,
++								mode_lib->vba.MaxPSCLToLBThroughput
++										* mode_lib->vba.HRatio[k]
++										/ 2
++										/ dml_ceil(
++												mode_lib->vba.HTAPsChroma[k]
++														/ 6.0,
++												1.0));
++			} else {
++				locals->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
++						mode_lib->vba.MaxDCHUBToPSCLThroughput,
++						mode_lib->vba.MaxPSCLToLBThroughput);
++			}
++			mode_lib->vba.DPPCLKUsingSingleDPPChroma =
++					mode_lib->vba.PixelClock[k]
++							* dml_max(
++									mode_lib->vba.VTAPsChroma[k]
++											/ 6.0
++											* dml_min(
++													1.0,
++													mode_lib->vba.HRatio[k]
++															/ 2),
++									dml_max(
++											mode_lib->vba.HRatio[k]
++													* mode_lib->vba.VRatio[k]
++													/ 4
++													/ locals->PSCL_THROUGHPUT_CHROMA[k],
++											1.0));
++
++			if ((mode_lib->vba.HTAPsChroma[k] > 6 || mode_lib->vba.VTAPsChroma[k] > 6)
++					&& mode_lib->vba.DPPCLKUsingSingleDPPChroma
++							< 2 * mode_lib->vba.PixelClock[k]) {
++				mode_lib->vba.DPPCLKUsingSingleDPPChroma = 2
++						* mode_lib->vba.PixelClock[k];
++			}
++
++			locals->DPPCLKUsingSingleDPP[k] = dml_max(
++					mode_lib->vba.DPPCLKUsingSingleDPPLuma,
++					mode_lib->vba.DPPCLKUsingSingleDPPChroma);
++		}
++	}
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.BlendingAndTiming[k] != k)
++			continue;
++		if (mode_lib->vba.ODMCombineEnabled[k]) {
++			mode_lib->vba.DISPCLKWithRamping =
++					dml_max(
++							mode_lib->vba.DISPCLKWithRamping,
++							mode_lib->vba.PixelClock[k] / 2
++									* (1
++											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
++													/ 100)
++									* (1
++											+ mode_lib->vba.DISPCLKRampingMargin
++													/ 100));
++			mode_lib->vba.DISPCLKWithoutRamping =
++					dml_max(
++							mode_lib->vba.DISPCLKWithoutRamping,
++							mode_lib->vba.PixelClock[k] / 2
++									* (1
++											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
++													/ 100));
++		} else if (!mode_lib->vba.ODMCombineEnabled[k]) {
++			mode_lib->vba.DISPCLKWithRamping =
++					dml_max(
++							mode_lib->vba.DISPCLKWithRamping,
++							mode_lib->vba.PixelClock[k]
++									* (1
++											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
++													/ 100)
++									* (1
++											+ mode_lib->vba.DISPCLKRampingMargin
++													/ 100));
++			mode_lib->vba.DISPCLKWithoutRamping =
++					dml_max(
++							mode_lib->vba.DISPCLKWithoutRamping,
++							mode_lib->vba.PixelClock[k]
++									* (1
++											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
++													/ 100));
++		}
++	}
++
++	mode_lib->vba.DISPCLKWithRamping = dml_max(
++			mode_lib->vba.DISPCLKWithRamping,
++			mode_lib->vba.WritebackDISPCLK);
++	mode_lib->vba.DISPCLKWithoutRamping = dml_max(
++			mode_lib->vba.DISPCLKWithoutRamping,
++			mode_lib->vba.WritebackDISPCLK);
++
++	ASSERT(mode_lib->vba.DISPCLKDPPCLKVCOSpeed != 0);
++	mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(
++			mode_lib->vba.DISPCLKWithRamping,
++			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
++	mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(
++			mode_lib->vba.DISPCLKWithoutRamping,
++			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
++	mode_lib->vba.MaxDispclkRoundedToDFSGranularity = RoundToDFSGranularityDown(
++			mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz,
++			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
++	if (mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity
++			> mode_lib->vba.MaxDispclkRoundedToDFSGranularity) {
++		mode_lib->vba.DISPCLK_calculated =
++				mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity;
++	} else if (mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity
++			> mode_lib->vba.MaxDispclkRoundedToDFSGranularity) {
++		mode_lib->vba.DISPCLK_calculated = mode_lib->vba.MaxDispclkRoundedToDFSGranularity;
++	} else {
++		mode_lib->vba.DISPCLK_calculated =
++				mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity;
++	}
++	DTRACE("   dispclk_mhz (calculated) = %f", mode_lib->vba.DISPCLK_calculated);
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		mode_lib->vba.DPPCLK_calculated[k] = locals->DPPCLKUsingSingleDPP[k]
++				/ mode_lib->vba.DPPPerPlane[k]
++				* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100);
++		mode_lib->vba.GlobalDPPCLK = dml_max(
++				mode_lib->vba.GlobalDPPCLK,
++				mode_lib->vba.DPPCLK_calculated[k]);
++	}
++	mode_lib->vba.GlobalDPPCLK = RoundToDFSGranularityUp(
++			mode_lib->vba.GlobalDPPCLK,
++			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.GlobalDPPCLK / 255
++				* dml_ceil(
++						mode_lib->vba.DPPCLK_calculated[k] * 255
++								/ mode_lib->vba.GlobalDPPCLK,
++						1);
++		DTRACE("   dppclk_mhz[%i] (calculated) = %f", k, mode_lib->vba.DPPCLK_calculated[k]);
++	}
++
++	// Urgent and B P-State/DRAM Clock Change Watermark
++	DTRACE("   dcfclk_mhz         = %f", mode_lib->vba.DCFCLK);
++	DTRACE("   return_bw_to_dcn   = %f", mode_lib->vba.ReturnBandwidthToDCN);
++	DTRACE("   return_bus_bw      = %f", mode_lib->vba.ReturnBW);
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		bool MainPlaneDoesODMCombine = false;
++
++		if (mode_lib->vba.SourceScan[k] == dm_horz)
++			locals->SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportWidth[k];
++		else
++			locals->SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportHeight[k];
++
++		if (mode_lib->vba.ODMCombineEnabled[k] == true)
++			MainPlaneDoesODMCombine = true;
++		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j)
++			if (mode_lib->vba.BlendingAndTiming[k] == j
++					&& mode_lib->vba.ODMCombineEnabled[j] == true)
++				MainPlaneDoesODMCombine = true;
++
++		if (MainPlaneDoesODMCombine == true)
++			locals->SwathWidthY[k] = dml_min(
++					(double) locals->SwathWidthSingleDPPY[k],
++					dml_round(
++							mode_lib->vba.HActive[k] / 2.0
++									* mode_lib->vba.HRatio[k]));
++		else
++			locals->SwathWidthY[k] = locals->SwathWidthSingleDPPY[k]
++					/ mode_lib->vba.DPPPerPlane[k];
++	}
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
++			locals->BytePerPixelDETY[k] = 8;
++			locals->BytePerPixelDETC[k] = 0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
++			locals->BytePerPixelDETY[k] = 4;
++			locals->BytePerPixelDETC[k] = 0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16 || mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) {
++			locals->BytePerPixelDETY[k] = 2;
++			locals->BytePerPixelDETC[k] = 0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8 || mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) {
++			locals->BytePerPixelDETY[k] = 1;
++			locals->BytePerPixelDETC[k] = 0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
++			locals->BytePerPixelDETY[k] = 1;
++			locals->BytePerPixelDETC[k] = 2;
++		} else { // dm_420_10
++			locals->BytePerPixelDETY[k] = 4.0 / 3.0;
++			locals->BytePerPixelDETC[k] = 8.0 / 3.0;
++		}
++	}
++
++	mode_lib->vba.TotalDataReadBandwidth = 0.0;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		locals->ReadBandwidthPlaneLuma[k] = locals->SwathWidthSingleDPPY[k]
++				* dml_ceil(locals->BytePerPixelDETY[k], 1)
++				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
++				* mode_lib->vba.VRatio[k];
++		locals->ReadBandwidthPlaneChroma[k] = locals->SwathWidthSingleDPPY[k]
++				/ 2 * dml_ceil(locals->BytePerPixelDETC[k], 2)
++				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
++				* mode_lib->vba.VRatio[k] / 2;
++		DTRACE(
++				"   read_bw[%i] = %fBps",
++				k,
++				locals->ReadBandwidthPlaneLuma[k]
++						+ locals->ReadBandwidthPlaneChroma[k]);
++		mode_lib->vba.TotalDataReadBandwidth += locals->ReadBandwidthPlaneLuma[k]
++				+ locals->ReadBandwidthPlaneChroma[k];
++	}
++
++	// DCFCLK Deep Sleep
++	CalculateDCFCLKDeepSleep(
++		mode_lib,
++		mode_lib->vba.NumberOfActivePlanes,
++		locals->BytePerPixelDETY,
++		locals->BytePerPixelDETC,
++		mode_lib->vba.VRatio,
++		locals->SwathWidthY,
++		mode_lib->vba.DPPPerPlane,
++		mode_lib->vba.HRatio,
++		mode_lib->vba.PixelClock,
++		locals->PSCL_THROUGHPUT_LUMA,
++		locals->PSCL_THROUGHPUT_CHROMA,
++		locals->DPPCLK,
++		&mode_lib->vba.DCFCLKDeepSleep);
++
++	// DSCCLK
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
++			locals->DSCCLK_calculated[k] = 0.0;
++		} else {
++			if (mode_lib->vba.OutputFormat[k] == dm_420
++					|| mode_lib->vba.OutputFormat[k] == dm_n422)
++				mode_lib->vba.DSCFormatFactor = 2;
++			else
++				mode_lib->vba.DSCFormatFactor = 1;
++			if (mode_lib->vba.ODMCombineEnabled[k])
++				locals->DSCCLK_calculated[k] =
++						mode_lib->vba.PixelClockBackEnd[k] / 6
++								/ mode_lib->vba.DSCFormatFactor
++								/ (1
++										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
++												/ 100);
++			else
++				locals->DSCCLK_calculated[k] =
++						mode_lib->vba.PixelClockBackEnd[k] / 3
++								/ mode_lib->vba.DSCFormatFactor
++								/ (1
++										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
++												/ 100);
++		}
++	}
++
++	// DSC Delay
++	// TODO
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		double bpp = mode_lib->vba.OutputBpp[k];
++		unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k];
++
++		if (mode_lib->vba.DSCEnabled[k] && bpp != 0) {
++			if (!mode_lib->vba.ODMCombineEnabled[k]) {
++				locals->DSCDelay[k] =
++						dscceComputeDelay(
++								mode_lib->vba.DSCInputBitPerComponent[k],
++								bpp,
++								dml_ceil(
++										(double) mode_lib->vba.HActive[k]
++												/ mode_lib->vba.NumberOfDSCSlices[k],
++										1),
++								slices,
++								mode_lib->vba.OutputFormat[k])
++								+ dscComputeDelay(
++										mode_lib->vba.OutputFormat[k]);
++			} else {
++				locals->DSCDelay[k] =
++						2
++								* (dscceComputeDelay(
++										mode_lib->vba.DSCInputBitPerComponent[k],
++										bpp,
++										dml_ceil(
++												(double) mode_lib->vba.HActive[k]
++														/ mode_lib->vba.NumberOfDSCSlices[k],
++												1),
++										slices / 2.0,
++										mode_lib->vba.OutputFormat[k])
++										+ dscComputeDelay(
++												mode_lib->vba.OutputFormat[k]));
++			}
++			locals->DSCDelay[k] = locals->DSCDelay[k]
++					* mode_lib->vba.PixelClock[k]
++					/ mode_lib->vba.PixelClockBackEnd[k];
++		} else {
++			locals->DSCDelay[k] = 0;
++		}
++	}
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
++		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) // NumberOfPlanes
++			if (j != k && mode_lib->vba.BlendingAndTiming[k] == j
++					&& mode_lib->vba.DSCEnabled[j])
++				locals->DSCDelay[k] = locals->DSCDelay[j];
++
++	// Prefetch
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		unsigned int PDEAndMetaPTEBytesFrameY;
++		unsigned int PixelPTEBytesPerRowY;
++		unsigned int MetaRowByteY;
++		unsigned int MetaRowByteC;
++		unsigned int PDEAndMetaPTEBytesFrameC;
++		unsigned int PixelPTEBytesPerRowC;
++		bool         PTEBufferSizeNotExceededY;
++		bool         PTEBufferSizeNotExceededC;
++
++		Calculate256BBlockSizes(
++				mode_lib->vba.SourcePixelFormat[k],
++				mode_lib->vba.SurfaceTiling[k],
++				dml_ceil(locals->BytePerPixelDETY[k], 1),
++				dml_ceil(locals->BytePerPixelDETC[k], 2),
++				&locals->BlockHeight256BytesY[k],
++				&locals->BlockHeight256BytesC[k],
++				&locals->BlockWidth256BytesY[k],
++				&locals->BlockWidth256BytesC[k]);
++
++		locals->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
++				mode_lib,
++				mode_lib->vba.VRatio[k],
++				mode_lib->vba.vtaps[k],
++				mode_lib->vba.Interlace[k],
++				mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
++				mode_lib->vba.SwathHeightY[k],
++				mode_lib->vba.ViewportYStartY[k],
++				&locals->VInitPreFillY[k],
++				&locals->MaxNumSwathY[k]);
++
++		if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
++				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
++				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
++				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_8)) {
++			PDEAndMetaPTEBytesFrameC =
++					CalculateVMAndRowBytes(
++							mode_lib,
++							mode_lib->vba.DCCEnable[k],
++							locals->BlockHeight256BytesC[k],
++							locals->BlockWidth256BytesC[k],
++							mode_lib->vba.SourcePixelFormat[k],
++							mode_lib->vba.SurfaceTiling[k],
++							dml_ceil(
++									locals->BytePerPixelDETC[k],
++									2),
++							mode_lib->vba.SourceScan[k],
++							mode_lib->vba.ViewportWidth[k] / 2,
++							mode_lib->vba.ViewportHeight[k] / 2,
++							locals->SwathWidthY[k] / 2,
++							mode_lib->vba.GPUVMEnable,
++							mode_lib->vba.HostVMEnable,
++							mode_lib->vba.HostVMMaxPageTableLevels,
++							mode_lib->vba.HostVMCachedPageTableLevels,
++							mode_lib->vba.VMMPageSize,
++							mode_lib->vba.PTEBufferSizeInRequestsChroma,
++							mode_lib->vba.PitchC[k],
++							mode_lib->vba.DCCMetaPitchC[k],
++							&locals->MacroTileWidthC[k],
++							&MetaRowByteC,
++							&PixelPTEBytesPerRowC,
++							&PTEBufferSizeNotExceededC,
++							&locals->dpte_row_width_chroma_ub[k],
++							&locals->dpte_row_height_chroma[k],
++							&locals->meta_req_width_chroma[k],
++							&locals->meta_req_height_chroma[k],
++							&locals->meta_row_width_chroma[k],
++							&locals->meta_row_height_chroma[k],
++							&locals->vm_group_bytes_chroma,
++							&locals->dpte_group_bytes_chroma,
++							&locals->PixelPTEReqWidthC[k],
++							&locals->PixelPTEReqHeightC[k],
++							&locals->PTERequestSizeC[k],
++							&locals->dpde0_bytes_per_frame_ub_c[k],
++							&locals->meta_pte_bytes_per_frame_ub_c[k]);
++
++			locals->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
++					mode_lib,
++					mode_lib->vba.VRatio[k] / 2,
++					mode_lib->vba.VTAPsChroma[k],
++					mode_lib->vba.Interlace[k],
++					mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
++					mode_lib->vba.SwathHeightC[k],
++					mode_lib->vba.ViewportYStartC[k],
++					&locals->VInitPreFillC[k],
++					&locals->MaxNumSwathC[k]);
++		} else {
++			PixelPTEBytesPerRowC = 0;
++			PDEAndMetaPTEBytesFrameC = 0;
++			MetaRowByteC = 0;
++			locals->MaxNumSwathC[k] = 0;
++			locals->PrefetchSourceLinesC[k] = 0;
++			locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma + mode_lib->vba.PTEBufferSizeInRequestsChroma;
++		}
++
++		PDEAndMetaPTEBytesFrameY = CalculateVMAndRowBytes(
++				mode_lib,
++				mode_lib->vba.DCCEnable[k],
++				locals->BlockHeight256BytesY[k],
++				locals->BlockWidth256BytesY[k],
++				mode_lib->vba.SourcePixelFormat[k],
++				mode_lib->vba.SurfaceTiling[k],
++				dml_ceil(locals->BytePerPixelDETY[k], 1),
++				mode_lib->vba.SourceScan[k],
++				mode_lib->vba.ViewportWidth[k],
++				mode_lib->vba.ViewportHeight[k],
++				locals->SwathWidthY[k],
++				mode_lib->vba.GPUVMEnable,
++				mode_lib->vba.HostVMEnable,
++				mode_lib->vba.HostVMMaxPageTableLevels,
++				mode_lib->vba.HostVMCachedPageTableLevels,
++				mode_lib->vba.VMMPageSize,
++				locals->PTEBufferSizeInRequestsForLuma,
++				mode_lib->vba.PitchY[k],
++				mode_lib->vba.DCCMetaPitchY[k],
++				&locals->MacroTileWidthY[k],
++				&MetaRowByteY,
++				&PixelPTEBytesPerRowY,
++				&PTEBufferSizeNotExceededY,
++				&locals->dpte_row_width_luma_ub[k],
++				&locals->dpte_row_height[k],
++				&locals->meta_req_width[k],
++				&locals->meta_req_height[k],
++				&locals->meta_row_width[k],
++				&locals->meta_row_height[k],
++				&locals->vm_group_bytes[k],
++				&locals->dpte_group_bytes[k],
++				&locals->PixelPTEReqWidthY[k],
++				&locals->PixelPTEReqHeightY[k],
++				&locals->PTERequestSizeY[k],
++				&locals->dpde0_bytes_per_frame_ub_l[k],
++				&locals->meta_pte_bytes_per_frame_ub_l[k]);
++
++		locals->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
++		locals->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY
++				+ PDEAndMetaPTEBytesFrameC;
++		locals->MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
++
++		CalculateActiveRowBandwidth(
++				mode_lib->vba.GPUVMEnable,
++				mode_lib->vba.SourcePixelFormat[k],
++				mode_lib->vba.VRatio[k],
++				mode_lib->vba.DCCEnable[k],
++				mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
++				MetaRowByteY,
++				MetaRowByteC,
++				locals->meta_row_height[k],
++				locals->meta_row_height_chroma[k],
++				PixelPTEBytesPerRowY,
++				PixelPTEBytesPerRowC,
++				locals->dpte_row_height[k],
++				locals->dpte_row_height_chroma[k],
++				&locals->meta_row_bw[k],
++				&locals->dpte_row_bw[k]);
++	}
++
++	mode_lib->vba.TotalDCCActiveDPP = 0;
++	mode_lib->vba.TotalActiveDPP = 0;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP
++				+ mode_lib->vba.DPPPerPlane[k];
++		if (mode_lib->vba.DCCEnable[k])
++			mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP
++					+ mode_lib->vba.DPPPerPlane[k];
++	}
++
++	mode_lib->vba.UrgentOutOfOrderReturnPerChannel = dml_max3(
++			mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly,
++			mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
++			mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly);
++
++	mode_lib->vba.UrgentRoundTripAndOutOfOrderLatency =
++			(mode_lib->vba.RoundTripPingLatencyCycles + 32) / mode_lib->vba.DCFCLK
++					+ mode_lib->vba.UrgentOutOfOrderReturnPerChannel
++							* mode_lib->vba.NumberOfChannels
++							/ mode_lib->vba.ReturnBW;
++
++	mode_lib->vba.UrgentExtraLatency = CalculateExtraLatency(
++			mode_lib->vba.UrgentRoundTripAndOutOfOrderLatency,
++			mode_lib->vba.TotalActiveDPP,
++			mode_lib->vba.PixelChunkSizeInKByte,
++			mode_lib->vba.TotalDCCActiveDPP,
++			mode_lib->vba.MetaChunkSize,
++			mode_lib->vba.ReturnBW,
++			mode_lib->vba.GPUVMEnable,
++			mode_lib->vba.HostVMEnable,
++			mode_lib->vba.NumberOfActivePlanes,
++			mode_lib->vba.DPPPerPlane,
++			locals->dpte_group_bytes,
++			mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
++			mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
++			mode_lib->vba.HostVMMaxPageTableLevels,
++			mode_lib->vba.HostVMCachedPageTableLevels);
++
++
++	mode_lib->vba.TCalc = 24.0 / mode_lib->vba.DCFCLKDeepSleep;
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.BlendingAndTiming[k] == k) {
++			if (mode_lib->vba.WritebackEnable[k] == true) {
++				locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
++						mode_lib->vba.WritebackLatency
++								+ CalculateWriteBackDelay(
++										mode_lib->vba.WritebackPixelFormat[k],
++										mode_lib->vba.WritebackHRatio[k],
++										mode_lib->vba.WritebackVRatio[k],
++										mode_lib->vba.WritebackLumaHTaps[k],
++										mode_lib->vba.WritebackLumaVTaps[k],
++										mode_lib->vba.WritebackChromaHTaps[k],
++										mode_lib->vba.WritebackChromaVTaps[k],
++										mode_lib->vba.WritebackDestinationWidth[k])
++										/ mode_lib->vba.DISPCLK;
++			} else
++				locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0;
++			for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) {
++				if (mode_lib->vba.BlendingAndTiming[j] == k
++						&& mode_lib->vba.WritebackEnable[j] == true) {
++					locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
++							dml_max(
++									locals->WritebackDelay[mode_lib->vba.VoltageLevel][k],
++									mode_lib->vba.WritebackLatency
++											+ CalculateWriteBackDelay(
++													mode_lib->vba.WritebackPixelFormat[j],
++													mode_lib->vba.WritebackHRatio[j],
++													mode_lib->vba.WritebackVRatio[j],
++													mode_lib->vba.WritebackLumaHTaps[j],
++													mode_lib->vba.WritebackLumaVTaps[j],
++													mode_lib->vba.WritebackChromaHTaps[j],
++													mode_lib->vba.WritebackChromaVTaps[j],
++													mode_lib->vba.WritebackDestinationWidth[j])
++													/ mode_lib->vba.DISPCLK);
++				}
++			}
++		}
++	}
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
++		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j)
++			if (mode_lib->vba.BlendingAndTiming[k] == j)
++				locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
++						locals->WritebackDelay[mode_lib->vba.VoltageLevel][j];
++
++	mode_lib->vba.VStartupLines = 13;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		locals->MaxVStartupLines[k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] - dml_max(1.0, dml_ceil(locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1));
++	}
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
++		locals->MaximumMaxVStartupLines = dml_max(locals->MaximumMaxVStartupLines, locals->MaxVStartupLines[k]);
++
++	// We don't really care to iterate between the various prefetch modes
++	//mode_lib->vba.PrefetchERROR = CalculateMinAndMaxPrefetchMode(mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, &mode_lib->vba.MinPrefetchMode, &mode_lib->vba.MaxPrefetchMode);
++	mode_lib->vba.UrgentLatency = dml_max3(mode_lib->vba.UrgentLatencyPixelDataOnly, mode_lib->vba.UrgentLatencyPixelMixedWithVMData, mode_lib->vba.UrgentLatencyVMDataOnly);
++
++	do {
++		double MaxTotalRDBandwidth = 0;
++		double MaxTotalRDBandwidthNoUrgentBurst = 0;
++		bool DestinationLineTimesForPrefetchLessThan2 = false;
++		bool VRatioPrefetchMoreThan4 = false;
++		double TWait = CalculateTWait(
++				mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
++				mode_lib->vba.DRAMClockChangeLatency,
++				mode_lib->vba.UrgentLatency,
++				mode_lib->vba.SREnterPlusExitTime);
++
++		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++			Pipe   myPipe;
++			HostVM myHostVM;
++
++			if (mode_lib->vba.XFCEnabled[k] == true) {
++				mode_lib->vba.XFCRemoteSurfaceFlipDelay =
++						CalculateRemoteSurfaceFlipDelay(
++								mode_lib,
++								mode_lib->vba.VRatio[k],
++								locals->SwathWidthY[k],
++								dml_ceil(
++										locals->BytePerPixelDETY[k],
++										1),
++								mode_lib->vba.HTotal[k]
++										/ mode_lib->vba.PixelClock[k],
++								mode_lib->vba.XFCTSlvVupdateOffset,
++								mode_lib->vba.XFCTSlvVupdateWidth,
++								mode_lib->vba.XFCTSlvVreadyOffset,
++								mode_lib->vba.XFCXBUFLatencyTolerance,
++								mode_lib->vba.XFCFillBWOverhead,
++								mode_lib->vba.XFCSlvChunkSize,
++								mode_lib->vba.XFCBusTransportTime,
++								mode_lib->vba.TCalc,
++								TWait,
++								&mode_lib->vba.SrcActiveDrainRate,
++								&mode_lib->vba.TInitXFill,
++								&mode_lib->vba.TslvChk);
++			} else {
++				mode_lib->vba.XFCRemoteSurfaceFlipDelay = 0;
++			}
++
++			myPipe.DPPCLK = locals->DPPCLK[k];
++			myPipe.DISPCLK = mode_lib->vba.DISPCLK;
++			myPipe.PixelClock = mode_lib->vba.PixelClock[k];
++			myPipe.DCFCLKDeepSleep = mode_lib->vba.DCFCLKDeepSleep;
++			myPipe.DPPPerPlane = mode_lib->vba.DPPPerPlane[k];
++			myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
++			myPipe.SourceScan = mode_lib->vba.SourceScan[k];
++			myPipe.BlockWidth256BytesY = locals->BlockWidth256BytesY[k];
++			myPipe.BlockHeight256BytesY = locals->BlockHeight256BytesY[k];
++			myPipe.BlockWidth256BytesC = locals->BlockWidth256BytesC[k];
++			myPipe.BlockHeight256BytesC = locals->BlockHeight256BytesC[k];
++			myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
++			myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k];
++			myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k];
++			myPipe.HTotal = mode_lib->vba.HTotal[k];
++
++
++			myHostVM.Enable = mode_lib->vba.HostVMEnable;
++			myHostVM.MaxPageTableLevels = mode_lib->vba.HostVMMaxPageTableLevels;
++			myHostVM.CachedPageTableLevels = mode_lib->vba.HostVMCachedPageTableLevels;
++
++			mode_lib->vba.ErrorResult[k] =
++					CalculatePrefetchSchedule(
++							mode_lib,
++							mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
++							mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
++							&myPipe,
++							locals->DSCDelay[k],
++							mode_lib->vba.DPPCLKDelaySubtotal,
++							mode_lib->vba.DPPCLKDelaySCL,
++							mode_lib->vba.DPPCLKDelaySCLLBOnly,
++							mode_lib->vba.DPPCLKDelayCNVCFormater,
++							mode_lib->vba.DPPCLKDelayCNVCCursor,
++							mode_lib->vba.DISPCLKDelaySubtotal,
++							(unsigned int) (locals->SwathWidthY[k]
++									/ mode_lib->vba.HRatio[k]),
++							mode_lib->vba.OutputFormat[k],
++							mode_lib->vba.MaxInterDCNTileRepeaters,
++							dml_min(mode_lib->vba.VStartupLines, locals->MaxVStartupLines[k]),
++							locals->MaxVStartupLines[k],
++							mode_lib->vba.GPUVMMaxPageTableLevels,
++							mode_lib->vba.GPUVMEnable,
++							&myHostVM,
++							mode_lib->vba.DynamicMetadataEnable[k],
++							mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
++							mode_lib->vba.DynamicMetadataTransmittedBytes[k],
++							mode_lib->vba.DCCEnable[k],
++							mode_lib->vba.UrgentLatency,
++							mode_lib->vba.UrgentExtraLatency,
++							mode_lib->vba.TCalc,
++							locals->PDEAndMetaPTEBytesFrame[k],
++							locals->MetaRowByte[k],
++							locals->PixelPTEBytesPerRow[k],
++							locals->PrefetchSourceLinesY[k],
++							locals->SwathWidthY[k],
++							locals->BytePerPixelDETY[k],
++							locals->VInitPreFillY[k],
++							locals->MaxNumSwathY[k],
++							locals->PrefetchSourceLinesC[k],
++							locals->BytePerPixelDETC[k],
++							locals->VInitPreFillC[k],
++							locals->MaxNumSwathC[k],
++							mode_lib->vba.SwathHeightY[k],
++							mode_lib->vba.SwathHeightC[k],
++							TWait,
++							mode_lib->vba.XFCEnabled[k],
++							mode_lib->vba.XFCRemoteSurfaceFlipDelay,
++							mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
++							&locals->DSTXAfterScaler[k],
++							&locals->DSTYAfterScaler[k],
++							&locals->DestinationLinesForPrefetch[k],
++							&locals->PrefetchBandwidth[k],
++							&locals->DestinationLinesToRequestVMInVBlank[k],
++							&locals->DestinationLinesToRequestRowInVBlank[k],
++							&locals->VRatioPrefetchY[k],
++							&locals->VRatioPrefetchC[k],
++							&locals->RequiredPrefetchPixDataBWLuma[k],
++							&locals->RequiredPrefetchPixDataBWChroma[k],
++							&locals->VStartupRequiredWhenNotEnoughTimeForDynamicMetadata,
++							&locals->Tno_bw[k],
++							&locals->prefetch_vmrow_bw[k],
++							&locals->swath_width_luma_ub[k],
++							&locals->swath_width_chroma_ub[k],
++							&mode_lib->vba.VUpdateOffsetPix[k],
++							&mode_lib->vba.VUpdateWidthPix[k],
++							&mode_lib->vba.VReadyOffsetPix[k]);
++			if (mode_lib->vba.BlendingAndTiming[k] == k) {
++				locals->VStartup[k] = dml_min(
++						mode_lib->vba.VStartupLines,
++						locals->MaxVStartupLines[k]);
++				if (locals->VStartupRequiredWhenNotEnoughTimeForDynamicMetadata
++						!= 0) {
++					locals->VStartup[k] =
++							locals->VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
++				}
++			} else {
++				locals->VStartup[k] =
++						dml_min(
++								mode_lib->vba.VStartupLines,
++								locals->MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]);
++			}
++		}
++
++		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++			unsigned int m;
++
++			locals->cursor_bw[k] = 0;
++			locals->cursor_bw_pre[k] = 0;
++			for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) {
++				locals->cursor_bw[k] += mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
++				locals->cursor_bw_pre[k] += mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * locals->VRatioPrefetchY[k];
++			}
++
++			CalculateUrgentBurstFactor(
++					mode_lib->vba.DETBufferSizeInKByte,
++					mode_lib->vba.SwathHeightY[k],
++					mode_lib->vba.SwathHeightC[k],
++					locals->SwathWidthY[k],
++					mode_lib->vba.HTotal[k] /
++					mode_lib->vba.PixelClock[k],
++					mode_lib->vba.UrgentLatency,
++					mode_lib->vba.CursorBufferSize,
++					mode_lib->vba.CursorWidth[k][0] + mode_lib->vba.CursorWidth[k][1],
++					dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]),
++					mode_lib->vba.VRatio[k],
++					locals->VRatioPrefetchY[k],
++					locals->VRatioPrefetchC[k],
++					locals->BytePerPixelDETY[k],
++					locals->BytePerPixelDETC[k],
++					&locals->UrgentBurstFactorCursor[k],
++					&locals->UrgentBurstFactorCursorPre[k],
++					&locals->UrgentBurstFactorLuma[k],
++					&locals->UrgentBurstFactorLumaPre[k],
++					&locals->UrgentBurstFactorChroma[k],
++					&locals->UrgentBurstFactorChromaPre[k],
++					&locals->NotEnoughUrgentLatencyHiding,
++					&locals->NotEnoughUrgentLatencyHidingPre);
++
++			if (mode_lib->vba.UseUrgentBurstBandwidth == false) {
++				locals->UrgentBurstFactorLuma[k] = 1;
++				locals->UrgentBurstFactorChroma[k] = 1;
++				locals->UrgentBurstFactorCursor[k] = 1;
++				locals->UrgentBurstFactorLumaPre[k] = 1;
++				locals->UrgentBurstFactorChromaPre[k] = 1;
++				locals->UrgentBurstFactorCursorPre[k] = 1;
++			}
++
++			MaxTotalRDBandwidth = MaxTotalRDBandwidth +
++				dml_max3(locals->prefetch_vmrow_bw[k],
++					locals->ReadBandwidthPlaneLuma[k] * locals->UrgentBurstFactorLuma[k]
++					+ locals->ReadBandwidthPlaneChroma[k] * locals->UrgentBurstFactorChroma[k] + locals->cursor_bw[k]
++					* locals->UrgentBurstFactorCursor[k] + locals->meta_row_bw[k] + locals->dpte_row_bw[k],
++					locals->RequiredPrefetchPixDataBWLuma[k] * locals->UrgentBurstFactorLumaPre[k] + locals->RequiredPrefetchPixDataBWChroma[k]
++					* locals->UrgentBurstFactorChromaPre[k] + locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
++
++			MaxTotalRDBandwidthNoUrgentBurst = MaxTotalRDBandwidthNoUrgentBurst +
++				dml_max3(locals->prefetch_vmrow_bw[k],
++					locals->ReadBandwidthPlaneLuma[k] + locals->ReadBandwidthPlaneChroma[k] + locals->cursor_bw[k]
++					+ locals->meta_row_bw[k] + locals->dpte_row_bw[k],
++					locals->RequiredPrefetchPixDataBWLuma[k] + locals->RequiredPrefetchPixDataBWChroma[k] + locals->cursor_bw_pre[k]);
++
++			if (locals->DestinationLinesForPrefetch[k] < 2)
++				DestinationLineTimesForPrefetchLessThan2 = true;
++			if (locals->VRatioPrefetchY[k] > 4 || locals->VRatioPrefetchC[k] > 4)
++				VRatioPrefetchMoreThan4 = true;
++		}
++		mode_lib->vba.FractionOfUrgentBandwidth = MaxTotalRDBandwidthNoUrgentBurst / mode_lib->vba.ReturnBW;
++
++		if (MaxTotalRDBandwidth <= mode_lib->vba.ReturnBW && locals->NotEnoughUrgentLatencyHiding == 0 && locals->NotEnoughUrgentLatencyHidingPre == 0 && !VRatioPrefetchMoreThan4
++				&& !DestinationLineTimesForPrefetchLessThan2)
++			mode_lib->vba.PrefetchModeSupported = true;
++		else {
++			mode_lib->vba.PrefetchModeSupported = false;
++			dml_print(
++					"DML: CalculatePrefetchSchedule ***failed***. Bandwidth violation. Results are NOT valid\n");
++		}
++
++		if (mode_lib->vba.PrefetchModeSupported == true) {
++			mode_lib->vba.BandwidthAvailableForImmediateFlip = mode_lib->vba.ReturnBW;
++			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++				mode_lib->vba.BandwidthAvailableForImmediateFlip =
++						mode_lib->vba.BandwidthAvailableForImmediateFlip
++							- dml_max(
++								locals->ReadBandwidthPlaneLuma[k] * locals->UrgentBurstFactorLuma[k]
++								+ locals->ReadBandwidthPlaneChroma[k] * locals->UrgentBurstFactorChroma[k]
++								+ locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k],
++								locals->RequiredPrefetchPixDataBWLuma[k] * locals->UrgentBurstFactorLumaPre[k] +
++								locals->RequiredPrefetchPixDataBWChroma[k] * locals->UrgentBurstFactorChromaPre[k] +
++								locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
++			}
++
++			mode_lib->vba.TotImmediateFlipBytes = 0;
++			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++				mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes + locals->PDEAndMetaPTEBytesFrame[k] + locals->MetaRowByte[k] + locals->PixelPTEBytesPerRow[k];
++			}
++			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++				CalculateFlipSchedule(
++						mode_lib,
++						mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
++						mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
++						mode_lib->vba.UrgentExtraLatency,
++						mode_lib->vba.UrgentLatency,
++						mode_lib->vba.GPUVMMaxPageTableLevels,
++						mode_lib->vba.HostVMEnable,
++						mode_lib->vba.HostVMMaxPageTableLevels,
++						mode_lib->vba.HostVMCachedPageTableLevels,
++						mode_lib->vba.GPUVMEnable,
++						locals->PDEAndMetaPTEBytesFrame[k],
++						locals->MetaRowByte[k],
++						locals->PixelPTEBytesPerRow[k],
++						mode_lib->vba.BandwidthAvailableForImmediateFlip,
++						mode_lib->vba.TotImmediateFlipBytes,
++						mode_lib->vba.SourcePixelFormat[k],
++						mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
++						mode_lib->vba.VRatio[k],
++						locals->Tno_bw[k],
++						mode_lib->vba.DCCEnable[k],
++						locals->dpte_row_height[k],
++						locals->meta_row_height[k],
++						locals->dpte_row_height_chroma[k],
++						locals->meta_row_height_chroma[k],
++						&locals->DestinationLinesToRequestVMInImmediateFlip[k],
++						&locals->DestinationLinesToRequestRowInImmediateFlip[k],
++						&locals->final_flip_bw[k],
++						&locals->ImmediateFlipSupportedForPipe[k]);
++			}
++			mode_lib->vba.total_dcn_read_bw_with_flip = 0.0;
++			mode_lib->vba.total_dcn_read_bw_with_flip_no_urgent_burst = 0.0;
++			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++				mode_lib->vba.total_dcn_read_bw_with_flip =
++						mode_lib->vba.total_dcn_read_bw_with_flip + dml_max3(
++							locals->prefetch_vmrow_bw[k],
++							locals->final_flip_bw[k] + locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k]
++							+ locals->ReadBandwidthChroma[k] * locals->UrgentBurstFactorChroma[k] + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k],
++							locals->final_flip_bw[k] + locals->RequiredPrefetchPixDataBWLuma[k] * locals->UrgentBurstFactorLumaPre[k]
++							+ locals->RequiredPrefetchPixDataBWChroma[k] * locals->UrgentBurstFactorChromaPre[k]
++							+ locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
++				mode_lib->vba.total_dcn_read_bw_with_flip_no_urgent_burst =
++				mode_lib->vba.total_dcn_read_bw_with_flip_no_urgent_burst +
++					dml_max3(locals->prefetch_vmrow_bw[k],
++						locals->final_flip_bw[k] + locals->ReadBandwidthPlaneLuma[k] + locals->ReadBandwidthPlaneChroma[k] + locals->cursor_bw[k],
++						locals->final_flip_bw[k] + locals->RequiredPrefetchPixDataBWLuma[k] + locals->RequiredPrefetchPixDataBWChroma[k] + locals->cursor_bw_pre[k]);
++
++			}
++			mode_lib->vba.FractionOfUrgentBandwidthImmediateFlip = mode_lib->vba.total_dcn_read_bw_with_flip_no_urgent_burst / mode_lib->vba.ReturnBW;
++
++			mode_lib->vba.ImmediateFlipSupported = true;
++			if (mode_lib->vba.total_dcn_read_bw_with_flip > mode_lib->vba.ReturnBW) {
++				mode_lib->vba.ImmediateFlipSupported = false;
++			}
++			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++				if (locals->ImmediateFlipSupportedForPipe[k] == false) {
++					mode_lib->vba.ImmediateFlipSupported = false;
++				}
++			}
++		} else {
++			mode_lib->vba.ImmediateFlipSupported = false;
++		}
++
++		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++			if (mode_lib->vba.ErrorResult[k]) {
++				mode_lib->vba.PrefetchModeSupported = false;
++				dml_print(
++						"DML: CalculatePrefetchSchedule ***failed***. Prefetch schedule violation. Results are NOT valid\n");
++			}
++		}
++
++		mode_lib->vba.VStartupLines = mode_lib->vba.VStartupLines + 1;
++	} while (!((mode_lib->vba.PrefetchModeSupported
++			&& ((!mode_lib->vba.ImmediateFlipSupport && !mode_lib->vba.HostVMEnable)
++					|| mode_lib->vba.ImmediateFlipSupported))
++			|| locals->MaximumMaxVStartupLines < mode_lib->vba.VStartupLines));
++
++	//Watermarks and NB P-State/DRAM Clock Change Support
++	{
++		enum clock_change_support DRAMClockChangeSupport; // dummy
++		CalculateWatermarksAndDRAMSpeedChangeSupport(
++				mode_lib,
++				mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
++				mode_lib->vba.NumberOfActivePlanes,
++				mode_lib->vba.MaxLineBufferLines,
++				mode_lib->vba.LineBufferSize,
++				mode_lib->vba.DPPOutputBufferPixels,
++				mode_lib->vba.DETBufferSizeInKByte,
++				mode_lib->vba.WritebackInterfaceLumaBufferSize,
++				mode_lib->vba.WritebackInterfaceChromaBufferSize,
++				mode_lib->vba.DCFCLK,
++				mode_lib->vba.UrgentOutOfOrderReturnPerChannel * mode_lib->vba.NumberOfChannels,
++				mode_lib->vba.ReturnBW,
++				mode_lib->vba.GPUVMEnable,
++				locals->dpte_group_bytes,
++				mode_lib->vba.MetaChunkSize,
++				mode_lib->vba.UrgentLatency,
++				mode_lib->vba.UrgentExtraLatency,
++				mode_lib->vba.WritebackLatency,
++				mode_lib->vba.WritebackChunkSize,
++				mode_lib->vba.SOCCLK,
++				mode_lib->vba.DRAMClockChangeLatency,
++				mode_lib->vba.SRExitTime,
++				mode_lib->vba.SREnterPlusExitTime,
++				mode_lib->vba.DCFCLKDeepSleep,
++				mode_lib->vba.DPPPerPlane,
++				mode_lib->vba.DCCEnable,
++				locals->DPPCLK,
++				locals->SwathWidthSingleDPPY,
++				mode_lib->vba.SwathHeightY,
++				locals->ReadBandwidthPlaneLuma,
++				mode_lib->vba.SwathHeightC,
++				locals->ReadBandwidthPlaneChroma,
++				mode_lib->vba.LBBitPerPixel,
++				locals->SwathWidthY,
++				mode_lib->vba.HRatio,
++				mode_lib->vba.vtaps,
++				mode_lib->vba.VTAPsChroma,
++				mode_lib->vba.VRatio,
++				mode_lib->vba.HTotal,
++				mode_lib->vba.PixelClock,
++				mode_lib->vba.BlendingAndTiming,
++				locals->BytePerPixelDETY,
++				locals->BytePerPixelDETC,
++				mode_lib->vba.WritebackEnable,
++				mode_lib->vba.WritebackPixelFormat,
++				mode_lib->vba.WritebackDestinationWidth,
++				mode_lib->vba.WritebackDestinationHeight,
++				mode_lib->vba.WritebackSourceHeight,
++				&DRAMClockChangeSupport,
++				&mode_lib->vba.UrgentWatermark,
++				&mode_lib->vba.WritebackUrgentWatermark,
++				&mode_lib->vba.DRAMClockChangeWatermark,
++				&mode_lib->vba.WritebackDRAMClockChangeWatermark,
++				&mode_lib->vba.StutterExitWatermark,
++				&mode_lib->vba.StutterEnterPlusExitWatermark,
++				&mode_lib->vba.MinActiveDRAMClockChangeLatencySupported);
++	}
++
++
++	//Display Pipeline Delivery Time in Prefetch, Groups
++	CalculatePixelDeliveryTimes(
++		mode_lib->vba.NumberOfActivePlanes,
++		mode_lib->vba.VRatio,
++		locals->VRatioPrefetchY,
++		locals->VRatioPrefetchC,
++		locals->swath_width_luma_ub,
++		locals->swath_width_chroma_ub,
++		mode_lib->vba.DPPPerPlane,
++		mode_lib->vba.HRatio,
++		mode_lib->vba.PixelClock,
++		locals->PSCL_THROUGHPUT_LUMA,
++		locals->PSCL_THROUGHPUT_CHROMA,
++		locals->DPPCLK,
++		locals->BytePerPixelDETC,
++		mode_lib->vba.SourceScan,
++		locals->BlockWidth256BytesY,
++		locals->BlockHeight256BytesY,
++		locals->BlockWidth256BytesC,
++		locals->BlockHeight256BytesC,
++		locals->DisplayPipeLineDeliveryTimeLuma,
++		locals->DisplayPipeLineDeliveryTimeChroma,
++		locals->DisplayPipeLineDeliveryTimeLumaPrefetch,
++		locals->DisplayPipeLineDeliveryTimeChromaPrefetch,
++		locals->DisplayPipeRequestDeliveryTimeLuma,
++		locals->DisplayPipeRequestDeliveryTimeChroma,
++		locals->DisplayPipeRequestDeliveryTimeLumaPrefetch,
++		locals->DisplayPipeRequestDeliveryTimeChromaPrefetch);
++
++	CalculateMetaAndPTETimes(
++		mode_lib->vba.NumberOfActivePlanes,
++		mode_lib->vba.GPUVMEnable,
++		mode_lib->vba.MetaChunkSize,
++		mode_lib->vba.MinMetaChunkSizeBytes,
++		mode_lib->vba.GPUVMMaxPageTableLevels,
++		mode_lib->vba.HTotal,
++		mode_lib->vba.VRatio,
++		locals->VRatioPrefetchY,
++		locals->VRatioPrefetchC,
++		locals->DestinationLinesToRequestRowInVBlank,
++		locals->DestinationLinesToRequestRowInImmediateFlip,
++		locals->DestinationLinesToRequestVMInVBlank,
++		locals->DestinationLinesToRequestVMInImmediateFlip,
++		mode_lib->vba.DCCEnable,
++		mode_lib->vba.PixelClock,
++		locals->BytePerPixelDETY,
++		locals->BytePerPixelDETC,
++		mode_lib->vba.SourceScan,
++		locals->dpte_row_height,
++		locals->dpte_row_height_chroma,
++		locals->meta_row_width,
++		locals->meta_row_height,
++		locals->meta_req_width,
++		locals->meta_req_height,
++		locals->dpte_group_bytes,
++		locals->PTERequestSizeY,
++		locals->PTERequestSizeC,
++		locals->PixelPTEReqWidthY,
++		locals->PixelPTEReqHeightY,
++		locals->PixelPTEReqWidthC,
++		locals->PixelPTEReqHeightC,
++		locals->dpte_row_width_luma_ub,
++		locals->dpte_row_width_chroma_ub,
++		locals->vm_group_bytes,
++		locals->dpde0_bytes_per_frame_ub_l,
++		locals->dpde0_bytes_per_frame_ub_c,
++		locals->meta_pte_bytes_per_frame_ub_l,
++		locals->meta_pte_bytes_per_frame_ub_c,
++		locals->DST_Y_PER_PTE_ROW_NOM_L,
++		locals->DST_Y_PER_PTE_ROW_NOM_C,
++		locals->DST_Y_PER_META_ROW_NOM_L,
++		locals->TimePerMetaChunkNominal,
++		locals->TimePerMetaChunkVBlank,
++		locals->TimePerMetaChunkFlip,
++		locals->time_per_pte_group_nom_luma,
++		locals->time_per_pte_group_vblank_luma,
++		locals->time_per_pte_group_flip_luma,
++		locals->time_per_pte_group_nom_chroma,
++		locals->time_per_pte_group_vblank_chroma,
++		locals->time_per_pte_group_flip_chroma,
++		locals->TimePerVMGroupVBlank,
++		locals->TimePerVMGroupFlip,
++		locals->TimePerVMRequestVBlank,
++		locals->TimePerVMRequestFlip);
++
++
++	// Min TTUVBlank
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) {
++			locals->AllowDRAMClockChangeDuringVBlank[k] = true;
++			locals->AllowDRAMSelfRefreshDuringVBlank[k] = true;
++			locals->MinTTUVBlank[k] = dml_max(
++					mode_lib->vba.DRAMClockChangeWatermark,
++					dml_max(
++							mode_lib->vba.StutterEnterPlusExitWatermark,
++							mode_lib->vba.UrgentWatermark));
++		} else if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 1) {
++			locals->AllowDRAMClockChangeDuringVBlank[k] = false;
++			locals->AllowDRAMSelfRefreshDuringVBlank[k] = true;
++			locals->MinTTUVBlank[k] = dml_max(
++					mode_lib->vba.StutterEnterPlusExitWatermark,
++					mode_lib->vba.UrgentWatermark);
++		} else {
++			locals->AllowDRAMClockChangeDuringVBlank[k] = false;
++			locals->AllowDRAMSelfRefreshDuringVBlank[k] = false;
++			locals->MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark;
++		}
++		if (!mode_lib->vba.DynamicMetadataEnable[k])
++			locals->MinTTUVBlank[k] = mode_lib->vba.TCalc
++					+ locals->MinTTUVBlank[k];
++	}
++
++	// DCC Configuration
++	mode_lib->vba.ActiveDPPs = 0;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		locals->MaximumDCCCompressionYSurface[k] = CalculateDCCConfiguration(
++			mode_lib->vba.DCCEnable[k],
++			false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
++			mode_lib->vba.ViewportWidth[k],
++			mode_lib->vba.ViewportHeight[k],
++			mode_lib->vba.DETBufferSizeInKByte * 1024,
++			locals->BlockHeight256BytesY[k],
++			mode_lib->vba.SwathHeightY[k],
++			mode_lib->vba.SurfaceTiling[k],
++			locals->BytePerPixelDETY[k],
++			mode_lib->vba.SourceScan[k],
++			&locals->DCCYMaxUncompressedBlock[k],
++			&locals->DCCYMaxCompressedBlock[k],
++			&locals->DCCYIndependent64ByteBlock[k]);
++	}
++
++	//XFC Parameters:
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.XFCEnabled[k] == true) {
++			double TWait;
++
++			locals->XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset;
++			locals->XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth;
++			locals->XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset;
++			TWait = CalculateTWait(
++					mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
++					mode_lib->vba.DRAMClockChangeLatency,
++					mode_lib->vba.UrgentLatency,
++					mode_lib->vba.SREnterPlusExitTime);
++			mode_lib->vba.XFCRemoteSurfaceFlipDelay = CalculateRemoteSurfaceFlipDelay(
++					mode_lib,
++					mode_lib->vba.VRatio[k],
++					locals->SwathWidthY[k],
++					dml_ceil(locals->BytePerPixelDETY[k], 1),
++					mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
++					mode_lib->vba.XFCTSlvVupdateOffset,
++					mode_lib->vba.XFCTSlvVupdateWidth,
++					mode_lib->vba.XFCTSlvVreadyOffset,
++					mode_lib->vba.XFCXBUFLatencyTolerance,
++					mode_lib->vba.XFCFillBWOverhead,
++					mode_lib->vba.XFCSlvChunkSize,
++					mode_lib->vba.XFCBusTransportTime,
++					mode_lib->vba.TCalc,
++					TWait,
++					&mode_lib->vba.SrcActiveDrainRate,
++					&mode_lib->vba.TInitXFill,
++					&mode_lib->vba.TslvChk);
++					locals->XFCRemoteSurfaceFlipLatency[k] =
++					dml_floor(
++							mode_lib->vba.XFCRemoteSurfaceFlipDelay
++									/ (mode_lib->vba.HTotal[k]
++											/ mode_lib->vba.PixelClock[k]),
++							1);
++			locals->XFCTransferDelay[k] =
++					dml_ceil(
++							mode_lib->vba.XFCBusTransportTime
++									/ (mode_lib->vba.HTotal[k]
++											/ mode_lib->vba.PixelClock[k]),
++							1);
++			locals->XFCPrechargeDelay[k] =
++					dml_ceil(
++							(mode_lib->vba.XFCBusTransportTime
++									+ mode_lib->vba.TInitXFill
++									+ mode_lib->vba.TslvChk)
++									/ (mode_lib->vba.HTotal[k]
++											/ mode_lib->vba.PixelClock[k]),
++							1);
++			mode_lib->vba.InitFillLevel = mode_lib->vba.XFCXBUFLatencyTolerance
++					* mode_lib->vba.SrcActiveDrainRate;
++			mode_lib->vba.FinalFillMargin =
++					(locals->DestinationLinesToRequestVMInVBlank[k]
++							+ locals->DestinationLinesToRequestRowInVBlank[k])
++							* mode_lib->vba.HTotal[k]
++							/ mode_lib->vba.PixelClock[k]
++							* mode_lib->vba.SrcActiveDrainRate
++							+ mode_lib->vba.XFCFillConstant;
++			mode_lib->vba.FinalFillLevel = mode_lib->vba.XFCRemoteSurfaceFlipDelay
++					* mode_lib->vba.SrcActiveDrainRate
++					+ mode_lib->vba.FinalFillMargin;
++			mode_lib->vba.RemainingFillLevel = dml_max(
++					0.0,
++					mode_lib->vba.FinalFillLevel - mode_lib->vba.InitFillLevel);
++			mode_lib->vba.TFinalxFill = mode_lib->vba.RemainingFillLevel
++					/ (mode_lib->vba.SrcActiveDrainRate
++							* mode_lib->vba.XFCFillBWOverhead / 100);
++			locals->XFCPrefetchMargin[k] =
++					mode_lib->vba.XFCRemoteSurfaceFlipDelay
++							+ mode_lib->vba.TFinalxFill
++							+ (locals->DestinationLinesToRequestVMInVBlank[k]
++									+ locals->DestinationLinesToRequestRowInVBlank[k])
++									* mode_lib->vba.HTotal[k]
++									/ mode_lib->vba.PixelClock[k];
++		} else {
++			locals->XFCSlaveVUpdateOffset[k] = 0;
++			locals->XFCSlaveVupdateWidth[k] = 0;
++			locals->XFCSlaveVReadyOffset[k] = 0;
++			locals->XFCRemoteSurfaceFlipLatency[k] = 0;
++			locals->XFCPrechargeDelay[k] = 0;
++			locals->XFCTransferDelay[k] = 0;
++			locals->XFCPrefetchMargin[k] = 0;
++		}
++	}
++
++	// Stutter Efficiency
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		CalculateDETBufferSize(
++			mode_lib->vba.DETBufferSizeInKByte,
++			mode_lib->vba.SwathHeightY[k],
++			mode_lib->vba.SwathHeightC[k],
++			&locals->DETBufferSizeY[k],
++			&locals->DETBufferSizeC[k]);
++
++		locals->LinesInDETY[k] = locals->DETBufferSizeY[k]
++				/ locals->BytePerPixelDETY[k] / locals->SwathWidthY[k];
++		locals->LinesInDETYRoundedDownToSwath[k] = dml_floor(
++				locals->LinesInDETY[k],
++				mode_lib->vba.SwathHeightY[k]);
++		locals->FullDETBufferingTimeY[k] =
++				locals->LinesInDETYRoundedDownToSwath[k]
++						* (mode_lib->vba.HTotal[k]
++								/ mode_lib->vba.PixelClock[k])
++						/ mode_lib->vba.VRatio[k];
++	}
++
++	mode_lib->vba.StutterPeriod = 999999.0;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (locals->FullDETBufferingTimeY[k] < mode_lib->vba.StutterPeriod) {
++			mode_lib->vba.StutterPeriod = locals->FullDETBufferingTimeY[k];
++			mode_lib->vba.FrameTimeForMinFullDETBufferingTime =
++				(double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k]
++				/ mode_lib->vba.PixelClock[k];
++			locals->BytePerPixelYCriticalPlane = dml_ceil(locals->BytePerPixelDETY[k], 1);
++			locals->SwathWidthYCriticalPlane = locals->SwathWidthY[k];
++			locals->LinesToFinishSwathTransferStutterCriticalPlane =
++				mode_lib->vba.SwathHeightY[k] - (locals->LinesInDETY[k] - locals->LinesInDETYRoundedDownToSwath[k]);
++		}
++	}
++
++	mode_lib->vba.AverageReadBandwidth = 0.0;
++	mode_lib->vba.TotalRowReadBandwidth = 0.0;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		unsigned int DCCRateLimit;
++
++		if (mode_lib->vba.DCCEnable[k]) {
++			if (locals->DCCYMaxCompressedBlock[k] == 256)
++				DCCRateLimit = 4;
++			else
++				DCCRateLimit = 2;
++
++			mode_lib->vba.AverageReadBandwidth =
++					mode_lib->vba.AverageReadBandwidth
++							+ (locals->ReadBandwidthPlaneLuma[k] + locals->ReadBandwidthPlaneChroma[k]) /
++								dml_min(mode_lib->vba.DCCRate[k], DCCRateLimit);
++		} else {
++			mode_lib->vba.AverageReadBandwidth =
++					mode_lib->vba.AverageReadBandwidth
++							+ locals->ReadBandwidthPlaneLuma[k]
++							+ locals->ReadBandwidthPlaneChroma[k];
++		}
++		mode_lib->vba.TotalRowReadBandwidth = mode_lib->vba.TotalRowReadBandwidth +
++		locals->meta_row_bw[k] + locals->dpte_row_bw[k];
++	}
++
++	mode_lib->vba.AverageDCCCompressionRate = mode_lib->vba.TotalDataReadBandwidth / mode_lib->vba.AverageReadBandwidth;
++
++	mode_lib->vba.PartOfBurstThatFitsInROB =
++			dml_min(
++					mode_lib->vba.StutterPeriod
++							* mode_lib->vba.TotalDataReadBandwidth,
++					mode_lib->vba.ROBBufferSizeInKByte * 1024
++							* mode_lib->vba.AverageDCCCompressionRate);
++	mode_lib->vba.StutterBurstTime = mode_lib->vba.PartOfBurstThatFitsInROB
++			/ mode_lib->vba.AverageDCCCompressionRate / mode_lib->vba.ReturnBW
++			+ (mode_lib->vba.StutterPeriod * mode_lib->vba.TotalDataReadBandwidth
++					- mode_lib->vba.PartOfBurstThatFitsInROB)
++					/ (mode_lib->vba.DCFCLK * 64)
++					+ mode_lib->vba.StutterPeriod * mode_lib->vba.TotalRowReadBandwidth / mode_lib->vba.ReturnBW;
++	mode_lib->vba.StutterBurstTime = dml_max(
++		mode_lib->vba.StutterBurstTime,
++		(locals->LinesToFinishSwathTransferStutterCriticalPlane * locals->BytePerPixelYCriticalPlane *
++		locals->SwathWidthYCriticalPlane / mode_lib->vba.ReturnBW)
++	);
++
++	mode_lib->vba.TotalActiveWriteback = 0;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.WritebackEnable[k] == true) {
++			mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + 1;
++		}
++	}
++
++	if (mode_lib->vba.TotalActiveWriteback == 0) {
++		mode_lib->vba.StutterEfficiencyNotIncludingVBlank = (1
++				- (mode_lib->vba.SRExitTime + mode_lib->vba.StutterBurstTime)
++						/ mode_lib->vba.StutterPeriod) * 100;
++	} else {
++		mode_lib->vba.StutterEfficiencyNotIncludingVBlank = 0;
++	}
++
++	mode_lib->vba.SmallestVBlank = 999999;
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {
++			mode_lib->vba.VBlankTime = (double) (mode_lib->vba.VTotal[k]
++					- mode_lib->vba.VActive[k]) * mode_lib->vba.HTotal[k]
++					/ mode_lib->vba.PixelClock[k];
++		} else {
++			mode_lib->vba.VBlankTime = 0;
++		}
++		mode_lib->vba.SmallestVBlank = dml_min(
++				mode_lib->vba.SmallestVBlank,
++				mode_lib->vba.VBlankTime);
++	}
++
++	mode_lib->vba.StutterEfficiency = (mode_lib->vba.StutterEfficiencyNotIncludingVBlank / 100
++			* (mode_lib->vba.FrameTimeForMinFullDETBufferingTime
++					- mode_lib->vba.SmallestVBlank)
++			+ mode_lib->vba.SmallestVBlank)
++			/ mode_lib->vba.FrameTimeForMinFullDETBufferingTime * 100;
++}
++
++static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
++{
++	// Display Pipe Configuration
++	double BytePerPixDETY;
++	double BytePerPixDETC;
++	double Read256BytesBlockHeightY;
++	double Read256BytesBlockHeightC;
++	double Read256BytesBlockWidthY;
++	double Read256BytesBlockWidthC;
++	double MaximumSwathHeightY;
++	double MaximumSwathHeightC;
++	double MinimumSwathHeightY;
++	double MinimumSwathHeightC;
++	double SwathWidth;
++	double SwathWidthGranularityY;
++	double SwathWidthGranularityC;
++	double RoundedUpMaxSwathSizeBytesY;
++	double RoundedUpMaxSwathSizeBytesC;
++	unsigned int j, k;
++
++	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++		bool MainPlaneDoesODMCombine = false;
++
++		if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
++			BytePerPixDETY = 8;
++			BytePerPixDETC = 0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
++			BytePerPixDETY = 4;
++			BytePerPixDETC = 0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
++			BytePerPixDETY = 2;
++			BytePerPixDETC = 0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) {
++			BytePerPixDETY = 1;
++			BytePerPixDETC = 0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
++			BytePerPixDETY = 1;
++			BytePerPixDETC = 2;
++		} else {
++			BytePerPixDETY = 4.0 / 3.0;
++			BytePerPixDETC = 8.0 / 3.0;
++		}
++
++		if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
++			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
++				Read256BytesBlockHeightY = 1;
++			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
++				Read256BytesBlockHeightY = 4;
++			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32
++					|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
++				Read256BytesBlockHeightY = 8;
++			} else {
++				Read256BytesBlockHeightY = 16;
++			}
++			Read256BytesBlockWidthY = 256 / dml_ceil(BytePerPixDETY, 1)
++					/ Read256BytesBlockHeightY;
++			Read256BytesBlockHeightC = 0;
++			Read256BytesBlockWidthC = 0;
++		} else {
++			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
++				Read256BytesBlockHeightY = 1;
++				Read256BytesBlockHeightC = 1;
++			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
++				Read256BytesBlockHeightY = 16;
++				Read256BytesBlockHeightC = 8;
++			} else {
++				Read256BytesBlockHeightY = 8;
++				Read256BytesBlockHeightC = 8;
++			}
++			Read256BytesBlockWidthY = 256 / dml_ceil(BytePerPixDETY, 1)
++					/ Read256BytesBlockHeightY;
++			Read256BytesBlockWidthC = 256 / dml_ceil(BytePerPixDETC, 2)
++					/ Read256BytesBlockHeightC;
++		}
++
++		if (mode_lib->vba.SourceScan[k] == dm_horz) {
++			MaximumSwathHeightY = Read256BytesBlockHeightY;
++			MaximumSwathHeightC = Read256BytesBlockHeightC;
++		} else {
++			MaximumSwathHeightY = Read256BytesBlockWidthY;
++			MaximumSwathHeightC = Read256BytesBlockWidthC;
++		}
++
++		if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
++			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
++					|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
++							&& (mode_lib->vba.SurfaceTiling[k]
++									== dm_sw_4kb_s
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_4kb_s_x
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_64kb_s
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_64kb_s_t
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_64kb_s_x
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_var_s
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_var_s_x)
++							&& mode_lib->vba.SourceScan[k] == dm_horz)) {
++				MinimumSwathHeightY = MaximumSwathHeightY;
++			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8
++					&& mode_lib->vba.SourceScan[k] != dm_horz) {
++				MinimumSwathHeightY = MaximumSwathHeightY;
++			} else {
++				MinimumSwathHeightY = MaximumSwathHeightY / 2.0;
++			}
++			MinimumSwathHeightC = MaximumSwathHeightC;
++		} else {
++			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
++				MinimumSwathHeightY = MaximumSwathHeightY;
++				MinimumSwathHeightC = MaximumSwathHeightC;
++			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
++					&& mode_lib->vba.SourceScan[k] == dm_horz) {
++				MinimumSwathHeightY = MaximumSwathHeightY / 2.0;
++				MinimumSwathHeightC = MaximumSwathHeightC;
++			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
++					&& mode_lib->vba.SourceScan[k] == dm_horz) {
++				MinimumSwathHeightC = MaximumSwathHeightC / 2.0;
++				MinimumSwathHeightY = MaximumSwathHeightY;
++			} else {
++				MinimumSwathHeightY = MaximumSwathHeightY;
++				MinimumSwathHeightC = MaximumSwathHeightC;
++			}
++		}
++
++		if (mode_lib->vba.SourceScan[k] == dm_horz) {
++			SwathWidth = mode_lib->vba.ViewportWidth[k];
++		} else {
++			SwathWidth = mode_lib->vba.ViewportHeight[k];
++		}
++
++		if (mode_lib->vba.ODMCombineEnabled[k] == true) {
++			MainPlaneDoesODMCombine = true;
++		}
++		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) {
++			if (mode_lib->vba.BlendingAndTiming[k] == j
++					&& mode_lib->vba.ODMCombineEnabled[j] == true) {
++				MainPlaneDoesODMCombine = true;
++			}
++		}
++
++		if (MainPlaneDoesODMCombine == true) {
++			SwathWidth = dml_min(
++					SwathWidth,
++					mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]);
++		} else {
++			SwathWidth = SwathWidth / mode_lib->vba.DPPPerPlane[k];
++		}
++
++		SwathWidthGranularityY = 256 / dml_ceil(BytePerPixDETY, 1) / MaximumSwathHeightY;
++		RoundedUpMaxSwathSizeBytesY = (dml_ceil(
++				(double) (SwathWidth - 1),
++				SwathWidthGranularityY) + SwathWidthGranularityY) * BytePerPixDETY
++				* MaximumSwathHeightY;
++		if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
++			RoundedUpMaxSwathSizeBytesY = dml_ceil(RoundedUpMaxSwathSizeBytesY, 256)
++					+ 256;
++		}
++		if (MaximumSwathHeightC > 0) {
++			SwathWidthGranularityC = 256.0 / dml_ceil(BytePerPixDETC, 2)
++					/ MaximumSwathHeightC;
++			RoundedUpMaxSwathSizeBytesC = (dml_ceil(
++					(double) (SwathWidth / 2.0 - 1),
++					SwathWidthGranularityC) + SwathWidthGranularityC)
++					* BytePerPixDETC * MaximumSwathHeightC;
++			if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
++				RoundedUpMaxSwathSizeBytesC = dml_ceil(
++						RoundedUpMaxSwathSizeBytesC,
++						256) + 256;
++			}
++		} else
++			RoundedUpMaxSwathSizeBytesC = 0.0;
++
++		if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC
++				<= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) {
++			mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY;
++			mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC;
++		} else {
++			mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY;
++			mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC;
++		}
++
++		CalculateDETBufferSize(
++				mode_lib->vba.DETBufferSizeInKByte,
++				mode_lib->vba.SwathHeightY[k],
++				mode_lib->vba.SwathHeightC[k],
++				&mode_lib->vba.DETBufferSizeY[k],
++				&mode_lib->vba.DETBufferSizeC[k]);
++	}
++}
++
++static double CalculateTWait(
++		unsigned int PrefetchMode,
++		double DRAMClockChangeLatency,
++		double UrgentLatency,
++		double SREnterPlusExitTime)
++{
++	if (PrefetchMode == 0) {
++		return dml_max(
++				DRAMClockChangeLatency + UrgentLatency,
++				dml_max(SREnterPlusExitTime, UrgentLatency));
++	} else if (PrefetchMode == 1) {
++		return dml_max(SREnterPlusExitTime, UrgentLatency);
++	} else {
++		return UrgentLatency;
++	}
++}
++
++static double CalculateRemoteSurfaceFlipDelay(
++		struct display_mode_lib *mode_lib,
++		double VRatio,
++		double SwathWidth,
++		double Bpp,
++		double LineTime,
++		double XFCTSlvVupdateOffset,
++		double XFCTSlvVupdateWidth,
++		double XFCTSlvVreadyOffset,
++		double XFCXBUFLatencyTolerance,
++		double XFCFillBWOverhead,
++		double XFCSlvChunkSize,
++		double XFCBusTransportTime,
++		double TCalc,
++		double TWait,
++		double *SrcActiveDrainRate,
++		double *TInitXFill,
++		double *TslvChk)
++{
++	double TSlvSetup, AvgfillRate, result;
++
++	*SrcActiveDrainRate = VRatio * SwathWidth * Bpp / LineTime;
++	TSlvSetup = XFCTSlvVupdateOffset + XFCTSlvVupdateWidth + XFCTSlvVreadyOffset;
++	*TInitXFill = XFCXBUFLatencyTolerance / (1 + XFCFillBWOverhead / 100);
++	AvgfillRate = *SrcActiveDrainRate * (1 + XFCFillBWOverhead / 100);
++	*TslvChk = XFCSlvChunkSize / AvgfillRate;
++	dml_print(
++			"DML::CalculateRemoteSurfaceFlipDelay: SrcActiveDrainRate: %f\n",
++			*SrcActiveDrainRate);
++	dml_print("DML::CalculateRemoteSurfaceFlipDelay: TSlvSetup: %f\n", TSlvSetup);
++	dml_print("DML::CalculateRemoteSurfaceFlipDelay: TInitXFill: %f\n", *TInitXFill);
++	dml_print("DML::CalculateRemoteSurfaceFlipDelay: AvgfillRate: %f\n", AvgfillRate);
++	dml_print("DML::CalculateRemoteSurfaceFlipDelay: TslvChk: %f\n", *TslvChk);
++	result = 2 * XFCBusTransportTime + TSlvSetup + TCalc + TWait + *TslvChk + *TInitXFill; // TODO: This doesn't seem to match programming guide
++	dml_print("DML::CalculateRemoteSurfaceFlipDelay: RemoteSurfaceFlipDelay: %f\n", result);
++	return result;
++}
++
++static double CalculateWriteBackDelay(
++		enum source_format_class WritebackPixelFormat,
++		double WritebackHRatio,
++		double WritebackVRatio,
++		unsigned int WritebackLumaHTaps,
++		unsigned int WritebackLumaVTaps,
++		unsigned int WritebackChromaHTaps,
++		unsigned int WritebackChromaVTaps,
++		unsigned int WritebackDestinationWidth)
++{
++	double CalculateWriteBackDelay =
++			dml_max(
++					dml_ceil(WritebackLumaHTaps / 4.0, 1) / WritebackHRatio,
++					WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 1)
++							* dml_ceil(
++									WritebackDestinationWidth
++											/ 4.0,
++									1)
++							+ dml_ceil(1.0 / WritebackVRatio, 1)
++									* (dml_ceil(
++											WritebackLumaVTaps
++													/ 4.0,
++											1) + 4));
++
++	if (WritebackPixelFormat != dm_444_32) {
++		CalculateWriteBackDelay =
++				dml_max(
++						CalculateWriteBackDelay,
++						dml_max(
++								dml_ceil(
++										WritebackChromaHTaps
++												/ 2.0,
++										1)
++										/ (2
++												* WritebackHRatio),
++								WritebackChromaVTaps
++										* dml_ceil(
++												1
++														/ (2
++																* WritebackVRatio),
++												1)
++										* dml_ceil(
++												WritebackDestinationWidth
++														/ 2.0
++														/ 2.0,
++												1)
++										+ dml_ceil(
++												1
++														/ (2
++																* WritebackVRatio),
++												1)
++												* (dml_ceil(
++														WritebackChromaVTaps
++																/ 4.0,
++														1)
++														+ 4)));
++	}
++	return CalculateWriteBackDelay;
++}
++
++static void CalculateActiveRowBandwidth(
++		bool GPUVMEnable,
++		enum source_format_class SourcePixelFormat,
++		double VRatio,
++		bool DCCEnable,
++		double LineTime,
++		unsigned int MetaRowByteLuma,
++		unsigned int MetaRowByteChroma,
++		unsigned int meta_row_height_luma,
++		unsigned int meta_row_height_chroma,
++		unsigned int PixelPTEBytesPerRowLuma,
++		unsigned int PixelPTEBytesPerRowChroma,
++		unsigned int dpte_row_height_luma,
++		unsigned int dpte_row_height_chroma,
++		double *meta_row_bw,
++		double *dpte_row_bw)
++{
++	if (DCCEnable != true) {
++		*meta_row_bw = 0;
++	} else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) {
++		*meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime)
++				+ VRatio / 2 * MetaRowByteChroma
++						/ (meta_row_height_chroma * LineTime);
++	} else {
++		*meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime);
++	}
++
++	if (GPUVMEnable != true) {
++		*dpte_row_bw = 0;
++	} else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) {
++		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime)
++				+ VRatio / 2 * PixelPTEBytesPerRowChroma
++						/ (dpte_row_height_chroma * LineTime);
++	} else {
++		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime);
++	}
++}
++
++static void CalculateFlipSchedule(
++		struct display_mode_lib *mode_lib,
++		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
++		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
++		double UrgentExtraLatency,
++		double UrgentLatency,
++		unsigned int GPUVMMaxPageTableLevels,
++		bool HostVMEnable,
++		unsigned int HostVMMaxPageTableLevels,
++		unsigned int HostVMCachedPageTableLevels,
++		bool GPUVMEnable,
++		double PDEAndMetaPTEBytesPerFrame,
++		double MetaRowBytes,
++		double DPTEBytesPerRow,
++		double BandwidthAvailableForImmediateFlip,
++		unsigned int TotImmediateFlipBytes,
++		enum source_format_class SourcePixelFormat,
++		double LineTime,
++		double VRatio,
++		double Tno_bw,
++		bool DCCEnable,
++		unsigned int dpte_row_height,
++		unsigned int meta_row_height,
++		unsigned int dpte_row_height_chroma,
++		unsigned int meta_row_height_chroma,
++		double *DestinationLinesToRequestVMInImmediateFlip,
++		double *DestinationLinesToRequestRowInImmediateFlip,
++		double *final_flip_bw,
++		bool *ImmediateFlipSupportedForPipe)
++{
++	double min_row_time = 0.0;
++	unsigned int HostVMDynamicLevels;
++	double TimeForFetchingMetaPTEImmediateFlip;
++	double TimeForFetchingRowInVBlankImmediateFlip;
++	double ImmediateFlipBW;
++	double HostVMInefficiencyFactor;
++
++	if (GPUVMEnable == true && HostVMEnable == true) {
++		HostVMInefficiencyFactor =
++				PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData
++						/ PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly;
++		HostVMDynamicLevels = HostVMMaxPageTableLevels - HostVMCachedPageTableLevels;
++	} else {
++		HostVMInefficiencyFactor = 1;
++		HostVMDynamicLevels = 0;
++	}
++
++	ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + DPTEBytesPerRow)
++			* BandwidthAvailableForImmediateFlip / TotImmediateFlipBytes;
++
++	if (GPUVMEnable == true) {
++		TimeForFetchingMetaPTEImmediateFlip = dml_max3(
++			Tno_bw + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW,
++			UrgentExtraLatency + UrgentLatency * (GPUVMMaxPageTableLevels * (HostVMDynamicLevels + 1) - 1),
++			LineTime / 4.0);
++	} else {
++		TimeForFetchingMetaPTEImmediateFlip = 0;
++	}
++
++	*DestinationLinesToRequestVMInImmediateFlip = dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1) / 4.0;
++	if ((GPUVMEnable == true || DCCEnable == true)) {
++		TimeForFetchingRowInVBlankImmediateFlip = dml_max3((MetaRowBytes + DPTEBytesPerRow) * HostVMInefficiencyFactor / ImmediateFlipBW, UrgentLatency * (HostVMDynamicLevels + 1), LineTime / 4);
++	} else {
++		TimeForFetchingRowInVBlankImmediateFlip = 0;
++	}
++
++	*DestinationLinesToRequestRowInImmediateFlip = dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1) / 4.0;
++	*final_flip_bw = dml_max(PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (*DestinationLinesToRequestVMInImmediateFlip * LineTime), (MetaRowBytes + DPTEBytesPerRow) * HostVMInefficiencyFactor / (*DestinationLinesToRequestRowInImmediateFlip * LineTime));
++	if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) {
++		if (GPUVMEnable == true && DCCEnable != true) {
++			min_row_time = dml_min(
++					dpte_row_height * LineTime / VRatio,
++					dpte_row_height_chroma * LineTime / (VRatio / 2));
++		} else if (GPUVMEnable != true && DCCEnable == true) {
++			min_row_time = dml_min(
++					meta_row_height * LineTime / VRatio,
++					meta_row_height_chroma * LineTime / (VRatio / 2));
++		} else {
++			min_row_time = dml_min4(
++					dpte_row_height * LineTime / VRatio,
++					meta_row_height * LineTime / VRatio,
++					dpte_row_height_chroma * LineTime / (VRatio / 2),
++					meta_row_height_chroma * LineTime / (VRatio / 2));
++		}
++	} else {
++		if (GPUVMEnable == true && DCCEnable != true) {
++			min_row_time = dpte_row_height * LineTime / VRatio;
++		} else if (GPUVMEnable != true && DCCEnable == true) {
++			min_row_time = meta_row_height * LineTime / VRatio;
++		} else {
++			min_row_time = dml_min(
++					dpte_row_height * LineTime / VRatio,
++					meta_row_height * LineTime / VRatio);
++		}
++	}
++
++	if (*DestinationLinesToRequestVMInImmediateFlip >= 32
++			|| *DestinationLinesToRequestRowInImmediateFlip >= 16
++			|| TimeForFetchingMetaPTEImmediateFlip + 2 * TimeForFetchingRowInVBlankImmediateFlip > min_row_time) {
++		*ImmediateFlipSupportedForPipe = false;
++	} else {
++		*ImmediateFlipSupportedForPipe = true;
++	}
++}
++
++static unsigned int TruncToValidBPP(
++		double DecimalBPP,
++		double DesiredBPP,
++		bool DSCEnabled,
++		enum output_encoder_class Output,
++		enum output_format_class Format,
++		unsigned int DSCInputBitPerComponent)
++{
++	if (Output == dm_hdmi) {
++		if (Format == dm_420) {
++			if (DecimalBPP >= 18 && (DesiredBPP == 0 || DesiredBPP == 18))
++				return 18;
++			else if (DecimalBPP >= 15 && (DesiredBPP == 0 || DesiredBPP == 15))
++				return 15;
++			else if (DecimalBPP >= 12 && (DesiredBPP == 0 || DesiredBPP == 12))
++				return 12;
++			else
++				return BPP_INVALID;
++		} else if (Format == dm_444) {
++			if (DecimalBPP >= 36 && (DesiredBPP == 0 || DesiredBPP == 36))
++				return 36;
++			else if (DecimalBPP >= 30 && (DesiredBPP == 0 || DesiredBPP == 30))
++				return 30;
++			else if (DecimalBPP >= 24 && (DesiredBPP == 0 || DesiredBPP == 24))
++				return 24;
++			else if (DecimalBPP >= 18 && (DesiredBPP == 0 || DesiredBPP == 18))
++				return 18;
++			else
++				return BPP_INVALID;
++		} else {
++			if (DecimalBPP / 1.5 >= 24 && (DesiredBPP == 0 || DesiredBPP == 24))
++				return 24;
++			else if (DecimalBPP / 1.5 >= 20 && (DesiredBPP == 0 || DesiredBPP == 20))
++				return 20;
++			else if (DecimalBPP / 1.5 >= 16 && (DesiredBPP == 0 || DesiredBPP == 16))
++				return 16;
++			else
++				return BPP_INVALID;
++		}
++	} else {
++		if (DSCEnabled) {
++			if (Format == dm_420) {
++				if (DesiredBPP == 0) {
++					if (DecimalBPP < 6)
++						return BPP_INVALID;
++					else if (DecimalBPP >= 1.5 * DSCInputBitPerComponent - 1.0 / 16.0)
++						return 1.5 * DSCInputBitPerComponent - 1.0 / 16.0;
++					else
++						return dml_floor(16 * DecimalBPP, 1) / 16.0;
++				} else {
++					if (DecimalBPP < 6
++							|| DesiredBPP < 6
++							|| DesiredBPP > 1.5 * DSCInputBitPerComponent - 1.0 / 16.0
++							|| DecimalBPP < DesiredBPP) {
++						return BPP_INVALID;
++					} else {
++						return DesiredBPP;
++					}
++				}
++			} else if (Format == dm_n422) {
++				if (DesiredBPP == 0) {
++					if (DecimalBPP < 7)
++						return BPP_INVALID;
++					else if (DecimalBPP >= 2 * DSCInputBitPerComponent - 1.0 / 16.0)
++						return 2 * DSCInputBitPerComponent - 1.0 / 16.0;
++					else
++						return dml_floor(16 * DecimalBPP, 1) / 16.0;
++				} else {
++					if (DecimalBPP < 7
++							|| DesiredBPP < 7
++							|| DesiredBPP > 2 * DSCInputBitPerComponent - 1.0 / 16.0
++							|| DecimalBPP < DesiredBPP) {
++						return BPP_INVALID;
++					} else {
++						return DesiredBPP;
++					}
++				}
++			} else {
++				if (DesiredBPP == 0) {
++					if (DecimalBPP < 8)
++						return BPP_INVALID;
++					else if (DecimalBPP >= 3 * DSCInputBitPerComponent - 1.0 / 16.0)
++						return 3 * DSCInputBitPerComponent - 1.0 / 16.0;
++					else
++						return dml_floor(16 * DecimalBPP, 1) / 16.0;
++				} else {
++					if (DecimalBPP < 8
++							|| DesiredBPP < 8
++							|| DesiredBPP > 3 * DSCInputBitPerComponent - 1.0 / 16.0
++							|| DecimalBPP < DesiredBPP) {
++						return BPP_INVALID;
++					} else {
++						return DesiredBPP;
++					}
++				}
++			}
++		} else if (Format == dm_420) {
++			if (DecimalBPP >= 18 && (DesiredBPP == 0 || DesiredBPP == 18))
++				return 18;
++			else if (DecimalBPP >= 15 && (DesiredBPP == 0 || DesiredBPP == 15))
++				return 15;
++			else if (DecimalBPP >= 12 && (DesiredBPP == 0 || DesiredBPP == 12))
++				return 12;
++			else
++				return BPP_INVALID;
++		} else if (Format == dm_s422 || Format == dm_n422) {
++			if (DecimalBPP >= 24 && (DesiredBPP == 0 || DesiredBPP == 24))
++				return 24;
++			else if (DecimalBPP >= 20 && (DesiredBPP == 0 || DesiredBPP == 20))
++				return 20;
++			else if (DecimalBPP >= 16 && (DesiredBPP == 0 || DesiredBPP == 16))
++				return 16;
++			else
++				return BPP_INVALID;
++		} else {
++			if (DecimalBPP >= 36 && (DesiredBPP == 0 || DesiredBPP == 36))
++				return 36;
++			else if (DecimalBPP >= 30 && (DesiredBPP == 0 || DesiredBPP == 30))
++				return 30;
++			else if (DecimalBPP >= 24 && (DesiredBPP == 0 || DesiredBPP == 24))
++				return 24;
++			else
++				return BPP_INVALID;
++		}
++	}
++}
++
++void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
++{
++	struct vba_vars_st *locals = &mode_lib->vba;
++
++	int i;
++	unsigned int j, k, m;
++
++	/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/
++
++	/*Scale Ratio, taps Support Check*/
++
++	mode_lib->vba.ScaleRatioAndTapsSupport = true;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.ScalerEnabled[k] == false
++				&& ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)
++						|| mode_lib->vba.HRatio[k] != 1.0
++						|| mode_lib->vba.htaps[k] != 1.0
++						|| mode_lib->vba.VRatio[k] != 1.0
++						|| mode_lib->vba.vtaps[k] != 1.0)) {
++			mode_lib->vba.ScaleRatioAndTapsSupport = false;
++		} else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0
++				|| mode_lib->vba.htaps[k] < 1.0 || mode_lib->vba.htaps[k] > 8.0
++				|| (mode_lib->vba.htaps[k] > 1.0
++						&& (mode_lib->vba.htaps[k] % 2) == 1)
++				|| mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio
++				|| mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio
++				|| mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k]
++				|| mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k]
++				|| (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
++						&& (mode_lib->vba.HRatio[k] / 2.0
++								> mode_lib->vba.HTAPsChroma[k]
++								|| mode_lib->vba.VRatio[k] / 2.0
++										> mode_lib->vba.VTAPsChroma[k]))) {
++			mode_lib->vba.ScaleRatioAndTapsSupport = false;
++		}
++	}
++	/*Source Format, Pixel Format and Scan Support Check*/
++
++	mode_lib->vba.SourceFormatPixelAndScanSupport = true;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
++				&& mode_lib->vba.SourceScan[k] != dm_horz)
++				|| ((mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d
++						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d_x
++						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d
++						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_t
++						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_x
++						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d
++						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d_x)
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_64)
++				|| (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x
++						&& (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8
++								|| mode_lib->vba.SourcePixelFormat[k]
++										== dm_420_8
++								|| mode_lib->vba.SourcePixelFormat[k]
++										== dm_420_10))
++				|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
++						|| mode_lib->vba.SurfaceTiling[k]
++								== dm_sw_gfx7_2d_thin_lvp)
++						&& !((mode_lib->vba.SourcePixelFormat[k]
++								== dm_444_64
++								|| mode_lib->vba.SourcePixelFormat[k]
++										== dm_444_32)
++								&& mode_lib->vba.SourceScan[k]
++										== dm_horz
++								&& mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
++										== true
++								&& mode_lib->vba.DCCEnable[k]
++										== false))
++						|| (mode_lib->vba.DCCEnable[k] == true
++								&& (mode_lib->vba.SurfaceTiling[k]
++										== dm_sw_linear
++										|| mode_lib->vba.SourcePixelFormat[k]
++												== dm_420_8
++										|| mode_lib->vba.SourcePixelFormat[k]
++												== dm_420_10)))) {
++			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
++		}
++	}
++	/*Bandwidth Support Check*/
++
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
++			locals->BytePerPixelInDETY[k] = 8.0;
++			locals->BytePerPixelInDETC[k] = 0.0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
++			locals->BytePerPixelInDETY[k] = 4.0;
++			locals->BytePerPixelInDETC[k] = 0.0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) {
++			locals->BytePerPixelInDETY[k] = 2.0;
++			locals->BytePerPixelInDETC[k] = 0.0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) {
++			locals->BytePerPixelInDETY[k] = 1.0;
++			locals->BytePerPixelInDETC[k] = 0.0;
++		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
++			locals->BytePerPixelInDETY[k] = 1.0;
++			locals->BytePerPixelInDETC[k] = 2.0;
++		} else {
++			locals->BytePerPixelInDETY[k] = 4.0 / 3;
++			locals->BytePerPixelInDETC[k] = 8.0 / 3;
++		}
++		if (mode_lib->vba.SourceScan[k] == dm_horz) {
++			locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k];
++		} else {
++			locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k];
++		}
++	}
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		locals->ReadBandwidthLuma[k] = locals->SwathWidthYSingleDPP[k] * dml_ceil(locals->BytePerPixelInDETY[k], 1.0)
++				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
++		locals->ReadBandwidthChroma[k] = locals->SwathWidthYSingleDPP[k] / 2 * dml_ceil(locals->BytePerPixelInDETC[k], 2.0)
++				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] / 2.0;
++		locals->ReadBandwidth[k] = locals->ReadBandwidthLuma[k] + locals->ReadBandwidthChroma[k];
++	}
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.WritebackEnable[k] == true
++				&& mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
++			locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
++					* mode_lib->vba.WritebackDestinationHeight[k]
++					/ (mode_lib->vba.WritebackSourceHeight[k]
++							* mode_lib->vba.HTotal[k]
++							/ mode_lib->vba.PixelClock[k]) * 4.0;
++		} else if (mode_lib->vba.WritebackEnable[k] == true
++				&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
++			locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
++					* mode_lib->vba.WritebackDestinationHeight[k]
++					/ (mode_lib->vba.WritebackSourceHeight[k]
++							* mode_lib->vba.HTotal[k]
++							/ mode_lib->vba.PixelClock[k]) * 3.0;
++		} else if (mode_lib->vba.WritebackEnable[k] == true) {
++			locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
++					* mode_lib->vba.WritebackDestinationHeight[k]
++					/ (mode_lib->vba.WritebackSourceHeight[k]
++							* mode_lib->vba.HTotal[k]
++							/ mode_lib->vba.PixelClock[k]) * 1.5;
++		} else {
++			locals->WriteBandwidth[k] = 0.0;
++		}
++	}
++	mode_lib->vba.DCCEnabledInAnyPlane = false;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.DCCEnable[k] == true) {
++			mode_lib->vba.DCCEnabledInAnyPlane = true;
++		}
++	}
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		locals->IdealSDPPortBandwidthPerState[i] = dml_min3(
++				mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLKPerState[i],
++				mode_lib->vba.DRAMSpeedPerState[i] * mode_lib->vba.NumberOfChannels
++						* mode_lib->vba.DRAMChannelWidth,
++				mode_lib->vba.FabricClockPerState[i]
++						* mode_lib->vba.FabricDatapathToDCNDataReturn);
++		if (mode_lib->vba.HostVMEnable == false) {
++			locals->ReturnBWPerState[i] = locals->IdealSDPPortBandwidthPerState[i]
++					* mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly / 100.0;
++		} else {
++			locals->ReturnBWPerState[i] = locals->IdealSDPPortBandwidthPerState[i]
++					* mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData / 100.0;
++		}
++	}
++	/*Writeback Latency support check*/
++
++	mode_lib->vba.WritebackLatencySupport = true;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.WritebackEnable[k] == true) {
++			if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
++				if (locals->WriteBandwidth[k]
++						> (mode_lib->vba.WritebackInterfaceLumaBufferSize
++								+ mode_lib->vba.WritebackInterfaceChromaBufferSize)
++								/ mode_lib->vba.WritebackLatency) {
++					mode_lib->vba.WritebackLatencySupport = false;
++				}
++			} else {
++				if (locals->WriteBandwidth[k]
++						> 1.5
++								* dml_min(
++										mode_lib->vba.WritebackInterfaceLumaBufferSize,
++										2.0
++												* mode_lib->vba.WritebackInterfaceChromaBufferSize)
++								/ mode_lib->vba.WritebackLatency) {
++					mode_lib->vba.WritebackLatencySupport = false;
++				}
++			}
++		}
++	}
++	/*Re-ordering Buffer Support Check*/
++
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		locals->UrgentRoundTripAndOutOfOrderLatencyPerState[i] =
++				(mode_lib->vba.RoundTripPingLatencyCycles + 32.0) / mode_lib->vba.DCFCLKPerState[i]
++				+ dml_max3(mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly,
++						mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
++						mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly)
++					* mode_lib->vba.NumberOfChannels / locals->ReturnBWPerState[i];
++		if ((mode_lib->vba.ROBBufferSizeInKByte - mode_lib->vba.PixelChunkSizeInKByte) * 1024.0 / locals->ReturnBWPerState[i]
++				> locals->UrgentRoundTripAndOutOfOrderLatencyPerState[i]) {
++			locals->ROBSupport[i] = true;
++		} else {
++			locals->ROBSupport[i] = false;
++		}
++	}
++	/*Writeback Mode Support Check*/
++
++	mode_lib->vba.TotalNumberOfActiveWriteback = 0;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.WritebackEnable[k] == true) {
++			if (mode_lib->vba.ActiveWritebacksPerPlane[k] == 0)
++				mode_lib->vba.ActiveWritebacksPerPlane[k] = 1;
++			mode_lib->vba.TotalNumberOfActiveWriteback =
++					mode_lib->vba.TotalNumberOfActiveWriteback
++							+ mode_lib->vba.ActiveWritebacksPerPlane[k];
++		}
++	}
++	mode_lib->vba.WritebackModeSupport = true;
++	if (mode_lib->vba.TotalNumberOfActiveWriteback > mode_lib->vba.MaxNumWriteback) {
++		mode_lib->vba.WritebackModeSupport = false;
++	}
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.WritebackEnable[k] == true
++				&& mode_lib->vba.Writeback10bpc420Supported != true
++				&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
++			mode_lib->vba.WritebackModeSupport = false;
++		}
++	}
++	/*Writeback Scale Ratio and Taps Support Check*/
++
++	mode_lib->vba.WritebackScaleRatioAndTapsSupport = true;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.WritebackEnable[k] == true) {
++			if (mode_lib->vba.WritebackLumaAndChromaScalingSupported == false
++					&& (mode_lib->vba.WritebackHRatio[k] != 1.0
++							|| mode_lib->vba.WritebackVRatio[k] != 1.0)) {
++				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
++			}
++			if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio
++					|| mode_lib->vba.WritebackVRatio[k]
++							> mode_lib->vba.WritebackMaxVSCLRatio
++					|| mode_lib->vba.WritebackHRatio[k]
++							< mode_lib->vba.WritebackMinHSCLRatio
++					|| mode_lib->vba.WritebackVRatio[k]
++							< mode_lib->vba.WritebackMinVSCLRatio
++					|| mode_lib->vba.WritebackLumaHTaps[k]
++							> mode_lib->vba.WritebackMaxHSCLTaps
++					|| mode_lib->vba.WritebackLumaVTaps[k]
++							> mode_lib->vba.WritebackMaxVSCLTaps
++					|| mode_lib->vba.WritebackHRatio[k]
++							> mode_lib->vba.WritebackLumaHTaps[k]
++					|| mode_lib->vba.WritebackVRatio[k]
++							> mode_lib->vba.WritebackLumaVTaps[k]
++					|| (mode_lib->vba.WritebackLumaHTaps[k] > 2.0
++							&& ((mode_lib->vba.WritebackLumaHTaps[k] % 2)
++									== 1))
++					|| (mode_lib->vba.WritebackPixelFormat[k] != dm_444_32
++							&& (mode_lib->vba.WritebackChromaHTaps[k]
++									> mode_lib->vba.WritebackMaxHSCLTaps
++									|| mode_lib->vba.WritebackChromaVTaps[k]
++											> mode_lib->vba.WritebackMaxVSCLTaps
++									|| 2.0
++											* mode_lib->vba.WritebackHRatio[k]
++											> mode_lib->vba.WritebackChromaHTaps[k]
++									|| 2.0
++											* mode_lib->vba.WritebackVRatio[k]
++											> mode_lib->vba.WritebackChromaVTaps[k]
++									|| (mode_lib->vba.WritebackChromaHTaps[k] > 2.0
++										&& ((mode_lib->vba.WritebackChromaHTaps[k] % 2) == 1))))) {
++				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
++			}
++			if (mode_lib->vba.WritebackVRatio[k] < 1.0) {
++				mode_lib->vba.WritebackLumaVExtra =
++						dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0);
++			} else {
++				mode_lib->vba.WritebackLumaVExtra = -1;
++			}
++			if ((mode_lib->vba.WritebackPixelFormat[k] == dm_444_32
++					&& mode_lib->vba.WritebackLumaVTaps[k]
++							> (mode_lib->vba.WritebackLineBufferLumaBufferSize
++									+ mode_lib->vba.WritebackLineBufferChromaBufferSize)
++									/ 3.0
++									/ mode_lib->vba.WritebackDestinationWidth[k]
++									- mode_lib->vba.WritebackLumaVExtra)
++					|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
++							&& mode_lib->vba.WritebackLumaVTaps[k]
++									> mode_lib->vba.WritebackLineBufferLumaBufferSize
++											* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
++											- mode_lib->vba.WritebackLumaVExtra)
++					|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
++							&& mode_lib->vba.WritebackLumaVTaps[k]
++									> mode_lib->vba.WritebackLineBufferLumaBufferSize
++											* 8.0 / 10.0
++											/ mode_lib->vba.WritebackDestinationWidth[k]
++											- mode_lib->vba.WritebackLumaVExtra)) {
++				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
++			}
++			if (2.0 * mode_lib->vba.WritebackVRatio[k] < 1) {
++				mode_lib->vba.WritebackChromaVExtra = 0.0;
++			} else {
++				mode_lib->vba.WritebackChromaVExtra = -1;
++			}
++			if ((mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
++					&& mode_lib->vba.WritebackChromaVTaps[k]
++							> mode_lib->vba.WritebackLineBufferChromaBufferSize
++									* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
++									- mode_lib->vba.WritebackChromaVExtra)
++					|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
++							&& mode_lib->vba.WritebackChromaVTaps[k]
++									> mode_lib->vba.WritebackLineBufferChromaBufferSize
++											* 8.0 / 10.0
++											/ mode_lib->vba.WritebackDestinationWidth[k]
++											- mode_lib->vba.WritebackChromaVExtra)) {
++				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
++			}
++		}
++	}
++	/*Maximum DISPCLK/DPPCLK Support check*/
++
++	mode_lib->vba.WritebackRequiredDISPCLK = 0.0;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.WritebackEnable[k] == true) {
++			mode_lib->vba.WritebackRequiredDISPCLK =
++					dml_max(
++							mode_lib->vba.WritebackRequiredDISPCLK,
++							CalculateWriteBackDISPCLK(
++									mode_lib->vba.WritebackPixelFormat[k],
++									mode_lib->vba.PixelClock[k],
++									mode_lib->vba.WritebackHRatio[k],
++									mode_lib->vba.WritebackVRatio[k],
++									mode_lib->vba.WritebackLumaHTaps[k],
++									mode_lib->vba.WritebackLumaVTaps[k],
++									mode_lib->vba.WritebackChromaHTaps[k],
++									mode_lib->vba.WritebackChromaVTaps[k],
++									mode_lib->vba.WritebackDestinationWidth[k],
++									mode_lib->vba.HTotal[k],
++									mode_lib->vba.WritebackChromaLineBufferWidth));
++		}
++	}
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.HRatio[k] > 1.0) {
++			locals->PSCL_FACTOR[k] = dml_min(
++					mode_lib->vba.MaxDCHUBToPSCLThroughput,
++					mode_lib->vba.MaxPSCLToLBThroughput
++							* mode_lib->vba.HRatio[k]
++							/ dml_ceil(
++									mode_lib->vba.htaps[k]
++											/ 6.0,
++									1.0));
++		} else {
++			locals->PSCL_FACTOR[k] = dml_min(
++					mode_lib->vba.MaxDCHUBToPSCLThroughput,
++					mode_lib->vba.MaxPSCLToLBThroughput);
++		}
++		if (locals->BytePerPixelInDETC[k] == 0.0) {
++			locals->PSCL_FACTOR_CHROMA[k] = 0.0;
++			locals->MinDPPCLKUsingSingleDPP[k] =
++					mode_lib->vba.PixelClock[k]
++							* dml_max3(
++									mode_lib->vba.vtaps[k] / 6.0
++											* dml_min(
++													1.0,
++													mode_lib->vba.HRatio[k]),
++									mode_lib->vba.HRatio[k]
++											* mode_lib->vba.VRatio[k]
++											/ locals->PSCL_FACTOR[k],
++									1.0);
++			if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0)
++					&& locals->MinDPPCLKUsingSingleDPP[k]
++							< 2.0 * mode_lib->vba.PixelClock[k]) {
++				locals->MinDPPCLKUsingSingleDPP[k] = 2.0
++						* mode_lib->vba.PixelClock[k];
++			}
++		} else {
++			if (mode_lib->vba.HRatio[k] / 2.0 > 1.0) {
++				locals->PSCL_FACTOR_CHROMA[k] =
++						dml_min(
++								mode_lib->vba.MaxDCHUBToPSCLThroughput,
++								mode_lib->vba.MaxPSCLToLBThroughput
++										* mode_lib->vba.HRatio[k]
++										/ 2.0
++										/ dml_ceil(
++												mode_lib->vba.HTAPsChroma[k]
++														/ 6.0,
++												1.0));
++			} else {
++				locals->PSCL_FACTOR_CHROMA[k] = dml_min(
++						mode_lib->vba.MaxDCHUBToPSCLThroughput,
++						mode_lib->vba.MaxPSCLToLBThroughput);
++			}
++			locals->MinDPPCLKUsingSingleDPP[k] =
++					mode_lib->vba.PixelClock[k]
++							* dml_max5(
++									mode_lib->vba.vtaps[k] / 6.0
++											* dml_min(
++													1.0,
++													mode_lib->vba.HRatio[k]),
++									mode_lib->vba.HRatio[k]
++											* mode_lib->vba.VRatio[k]
++											/ locals->PSCL_FACTOR[k],
++									mode_lib->vba.VTAPsChroma[k]
++											/ 6.0
++											* dml_min(
++													1.0,
++													mode_lib->vba.HRatio[k]
++															/ 2.0),
++									mode_lib->vba.HRatio[k]
++											* mode_lib->vba.VRatio[k]
++											/ 4.0
++											/ locals->PSCL_FACTOR_CHROMA[k],
++									1.0);
++			if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0
++					|| mode_lib->vba.HTAPsChroma[k] > 6.0
++					|| mode_lib->vba.VTAPsChroma[k] > 6.0)
++					&& locals->MinDPPCLKUsingSingleDPP[k]
++							< 2.0 * mode_lib->vba.PixelClock[k]) {
++				locals->MinDPPCLKUsingSingleDPP[k] = 2.0
++						* mode_lib->vba.PixelClock[k];
++			}
++		}
++	}
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		Calculate256BBlockSizes(
++				mode_lib->vba.SourcePixelFormat[k],
++				mode_lib->vba.SurfaceTiling[k],
++				dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
++				dml_ceil(locals->BytePerPixelInDETC[k], 2.0),
++				&locals->Read256BlockHeightY[k],
++				&locals->Read256BlockHeightC[k],
++				&locals->Read256BlockWidthY[k],
++				&locals->Read256BlockWidthC[k]);
++		if (mode_lib->vba.SourceScan[k] == dm_horz) {
++			locals->MaxSwathHeightY[k] = locals->Read256BlockHeightY[k];
++			locals->MaxSwathHeightC[k] = locals->Read256BlockHeightC[k];
++		} else {
++			locals->MaxSwathHeightY[k] = locals->Read256BlockWidthY[k];
++			locals->MaxSwathHeightC[k] = locals->Read256BlockWidthC[k];
++		}
++		if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16
++				|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_8)) {
++			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
++					|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
++							&& (mode_lib->vba.SurfaceTiling[k]
++									== dm_sw_4kb_s
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_4kb_s_x
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_64kb_s
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_64kb_s_t
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_64kb_s_x
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_var_s
++									|| mode_lib->vba.SurfaceTiling[k]
++											== dm_sw_var_s_x)
++							&& mode_lib->vba.SourceScan[k] == dm_horz)) {
++				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
++			} else {
++				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
++						/ 2.0;
++			}
++			locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
++		} else {
++			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
++				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
++				locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
++			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
++					&& mode_lib->vba.SourceScan[k] == dm_horz) {
++				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
++						/ 2.0;
++				locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
++			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
++					&& mode_lib->vba.SourceScan[k] == dm_horz) {
++				locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]
++						/ 2.0;
++				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
++			} else {
++				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
++				locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
++			}
++		}
++		if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
++			mode_lib->vba.MaximumSwathWidthSupport = 8192.0;
++		} else {
++			mode_lib->vba.MaximumSwathWidthSupport = 5120.0;
++		}
++		mode_lib->vba.MaximumSwathWidthInDETBuffer =
++				dml_min(
++						mode_lib->vba.MaximumSwathWidthSupport,
++						mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0
++								/ (locals->BytePerPixelInDETY[k]
++										* locals->MinSwathHeightY[k]
++										+ locals->BytePerPixelInDETC[k]
++												/ 2.0
++												* locals->MinSwathHeightC[k]));
++		if (locals->BytePerPixelInDETC[k] == 0.0) {
++			mode_lib->vba.MaximumSwathWidthInLineBuffer =
++					mode_lib->vba.LineBufferSize
++							* dml_max(mode_lib->vba.HRatio[k], 1.0)
++							/ mode_lib->vba.LBBitPerPixel[k]
++							/ (mode_lib->vba.vtaps[k]
++									+ dml_max(
++											dml_ceil(
++													mode_lib->vba.VRatio[k],
++													1.0)
++													- 2,
++											0.0));
++		} else {
++			mode_lib->vba.MaximumSwathWidthInLineBuffer =
++					dml_min(
++							mode_lib->vba.LineBufferSize
++									* dml_max(
++											mode_lib->vba.HRatio[k],
++											1.0)
++									/ mode_lib->vba.LBBitPerPixel[k]
++									/ (mode_lib->vba.vtaps[k]
++											+ dml_max(
++													dml_ceil(
++															mode_lib->vba.VRatio[k],
++															1.0)
++															- 2,
++													0.0)),
++							2.0 * mode_lib->vba.LineBufferSize
++									* dml_max(
++											mode_lib->vba.HRatio[k]
++													/ 2.0,
++											1.0)
++									/ mode_lib->vba.LBBitPerPixel[k]
++									/ (mode_lib->vba.VTAPsChroma[k]
++											+ dml_max(
++													dml_ceil(
++															mode_lib->vba.VRatio[k]
++																	/ 2.0,
++															1.0)
++															- 2,
++													0.0)));
++		}
++		locals->MaximumSwathWidth[k] = dml_min(
++				mode_lib->vba.MaximumSwathWidthInDETBuffer,
++				mode_lib->vba.MaximumSwathWidthInLineBuffer);
++	}
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		for (j = 0; j < 2; j++) {
++			mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(
++				mode_lib->vba.MaxDispclk[i],
++				mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
++			mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(
++				mode_lib->vba.MaxDppclk[i],
++				mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
++			locals->RequiredDISPCLK[i][j] = 0.0;
++			locals->DISPCLK_DPPCLK_Support[i][j] = true;
++			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++				mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine =
++						mode_lib->vba.PixelClock[k]
++								* (1.0
++										+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
++												/ 100.0)
++								* (1.0
++										+ mode_lib->vba.DISPCLKRampingMargin
++												/ 100.0);
++				if (mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine >= mode_lib->vba.MaxDispclk[i]
++						&& i == mode_lib->vba.soc.num_states)
++					mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine = mode_lib->vba.PixelClock[k]
++							* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
++
++				mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
++					* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * (1 + mode_lib->vba.DISPCLKRampingMargin / 100.0);
++				if (mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine >= mode_lib->vba.MaxDispclk[i]
++						&& i == mode_lib->vba.soc.num_states)
++					mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
++							* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
++				if (mode_lib->vba.ODMCapability == false || mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine <= mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
++					locals->ODMCombineEnablePerState[i][k] = false;
++					mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
++				} else {
++					locals->ODMCombineEnablePerState[i][k] = true;
++					mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
++				}
++				if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
++						&& locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]
++						&& locals->ODMCombineEnablePerState[i][k] == false) {
++					locals->NoOfDPP[i][j][k] = 1;
++					locals->RequiredDPPCLK[i][j][k] =
++						locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
++				} else {
++					locals->NoOfDPP[i][j][k] = 2;
++					locals->RequiredDPPCLK[i][j][k] =
++						locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
++				}
++				locals->RequiredDISPCLK[i][j] = dml_max(
++						locals->RequiredDISPCLK[i][j],
++						mode_lib->vba.PlaneRequiredDISPCLK);
++				if ((locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
++						> mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity)
++						|| (mode_lib->vba.PlaneRequiredDISPCLK > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity)) {
++					locals->DISPCLK_DPPCLK_Support[i][j] = false;
++				}
++			}
++			locals->TotalNumberOfActiveDPP[i][j] = 0.0;
++			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
++				locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
++			if (j == 1) {
++				while (locals->TotalNumberOfActiveDPP[i][j] < mode_lib->vba.MaxNumDPP
++						&& locals->TotalNumberOfActiveDPP[i][j] < 2 * mode_lib->vba.NumberOfActivePlanes) {
++					double BWOfNonSplitPlaneOfMaximumBandwidth;
++					unsigned int NumberOfNonSplitPlaneOfMaximumBandwidth;
++
++					BWOfNonSplitPlaneOfMaximumBandwidth = 0;
++					NumberOfNonSplitPlaneOfMaximumBandwidth = 0;
++					for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++						if (locals->ReadBandwidth[k] > BWOfNonSplitPlaneOfMaximumBandwidth && locals->NoOfDPP[i][j][k] == 1) {
++							BWOfNonSplitPlaneOfMaximumBandwidth = locals->ReadBandwidth[k];
++							NumberOfNonSplitPlaneOfMaximumBandwidth = k;
++						}
++					}
++					locals->NoOfDPP[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = 2;
++					locals->RequiredDPPCLK[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] =
++						locals->MinDPPCLKUsingSingleDPP[NumberOfNonSplitPlaneOfMaximumBandwidth]
++							* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100) / 2;
++					locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + 1;
++				}
++			}
++			if (locals->TotalNumberOfActiveDPP[i][j] > mode_lib->vba.MaxNumDPP) {
++				locals->RequiredDISPCLK[i][j] = 0.0;
++				locals->DISPCLK_DPPCLK_Support[i][j] = true;
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					locals->ODMCombineEnablePerState[i][k] = false;
++					if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
++						locals->NoOfDPP[i][j][k] = 1;
++						locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
++							* (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
++					} else {
++						locals->NoOfDPP[i][j][k] = 2;
++						locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
++										* (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
++					}
++					if (i != mode_lib->vba.soc.num_states) {
++						mode_lib->vba.PlaneRequiredDISPCLK =
++								mode_lib->vba.PixelClock[k]
++										* (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
++										* (1.0 + mode_lib->vba.DISPCLKRampingMargin / 100.0);
++					} else {
++						mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PixelClock[k]
++							* (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
++					}
++					locals->RequiredDISPCLK[i][j] = dml_max(
++							locals->RequiredDISPCLK[i][j],
++							mode_lib->vba.PlaneRequiredDISPCLK);
++					if (locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
++							> mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
++							|| mode_lib->vba.PlaneRequiredDISPCLK > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity)
++						locals->DISPCLK_DPPCLK_Support[i][j] = false;
++				}
++				locals->TotalNumberOfActiveDPP[i][j] = 0.0;
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
++					locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
++			}
++			locals->RequiredDISPCLK[i][j] = dml_max(
++					locals->RequiredDISPCLK[i][j],
++					mode_lib->vba.WritebackRequiredDISPCLK);
++			if (mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity
++					< mode_lib->vba.WritebackRequiredDISPCLK) {
++				locals->DISPCLK_DPPCLK_Support[i][j] = false;
++			}
++		}
++	}
++	/*Viewport Size Check*/
++
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		locals->ViewportSizeSupport[i] = true;
++		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++			if (locals->ODMCombineEnablePerState[i][k] == true) {
++				if (dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]))
++						> locals->MaximumSwathWidth[k]) {
++					locals->ViewportSizeSupport[i] = false;
++				}
++			} else {
++				if (locals->SwathWidthYSingleDPP[k] / 2.0 > locals->MaximumSwathWidth[k]) {
++					locals->ViewportSizeSupport[i] = false;
++				}
++			}
++		}
++	}
++	/*Total Available Pipes Support Check*/
++
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		for (j = 0; j < 2; j++) {
++			if (locals->TotalNumberOfActiveDPP[i][j] <= mode_lib->vba.MaxNumDPP)
++				locals->TotalAvailablePipesSupport[i][j] = true;
++			else
++				locals->TotalAvailablePipesSupport[i][j] = false;
++		}
++	}
++	/*Total Available OTG Support Check*/
++
++	mode_lib->vba.TotalNumberOfActiveOTG = 0.0;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.BlendingAndTiming[k] == k) {
++			mode_lib->vba.TotalNumberOfActiveOTG = mode_lib->vba.TotalNumberOfActiveOTG
++					+ 1.0;
++		}
++	}
++	if (mode_lib->vba.TotalNumberOfActiveOTG <= mode_lib->vba.MaxNumOTG) {
++		mode_lib->vba.NumberOfOTGSupport = true;
++	} else {
++		mode_lib->vba.NumberOfOTGSupport = false;
++	}
++	/*Display IO and DSC Support Check*/
++
++	mode_lib->vba.NonsupportedDSCInputBPC = false;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0
++				|| mode_lib->vba.DSCInputBitPerComponent[k] == 10.0
++				|| mode_lib->vba.DSCInputBitPerComponent[k] == 8.0)) {
++			mode_lib->vba.NonsupportedDSCInputBPC = true;
++		}
++	}
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++			locals->RequiresDSC[i][k] = 0;
++			locals->RequiresFEC[i][k] = 0;
++			if (mode_lib->vba.BlendingAndTiming[k] == k) {
++				if (mode_lib->vba.Output[k] == dm_hdmi) {
++					locals->RequiresDSC[i][k] = 0;
++					locals->RequiresFEC[i][k] = 0;
++					locals->OutputBppPerState[i][k] = TruncToValidBPP(
++							dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24,
++							mode_lib->vba.ForcedOutputLinkBPP[k],
++							false,
++							mode_lib->vba.Output[k],
++							mode_lib->vba.OutputFormat[k],
++							mode_lib->vba.DSCInputBitPerComponent[k]);
++				} else if (mode_lib->vba.Output[k] == dm_dp
++						|| mode_lib->vba.Output[k] == dm_edp) {
++					if (mode_lib->vba.Output[k] == dm_edp) {
++						mode_lib->vba.EffectiveFECOverhead = 0.0;
++					} else {
++						mode_lib->vba.EffectiveFECOverhead =
++								mode_lib->vba.FECOverhead;
++					}
++					if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) {
++						mode_lib->vba.Outbpp = TruncToValidBPP(
++								(1.0 - mode_lib->vba.Downspreading / 100.0) * 270.0
++								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
++								mode_lib->vba.ForcedOutputLinkBPP[k],
++								false,
++								mode_lib->vba.Output[k],
++								mode_lib->vba.OutputFormat[k],
++								mode_lib->vba.DSCInputBitPerComponent[k]);
++						mode_lib->vba.OutbppDSC = TruncToValidBPP(
++								(1.0 - mode_lib->vba.Downspreading / 100.0) * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 270.0
++								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
++								mode_lib->vba.ForcedOutputLinkBPP[k],
++								true,
++								mode_lib->vba.Output[k],
++								mode_lib->vba.OutputFormat[k],
++								mode_lib->vba.DSCInputBitPerComponent[k]);
++						if (mode_lib->vba.DSCEnabled[k] == true) {
++							locals->RequiresDSC[i][k] = true;
++							if (mode_lib->vba.Output[k] == dm_dp) {
++								locals->RequiresFEC[i][k] = true;
++							} else {
++								locals->RequiresFEC[i][k] = false;
++							}
++							mode_lib->vba.Outbpp = mode_lib->vba.OutbppDSC;
++						} else {
++							locals->RequiresDSC[i][k] = false;
++							locals->RequiresFEC[i][k] = false;
++						}
++						locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
++					}
++					if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) {
++						mode_lib->vba.Outbpp = TruncToValidBPP(
++								(1.0 - mode_lib->vba.Downspreading / 100.0) * 540.0
++								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
++								mode_lib->vba.ForcedOutputLinkBPP[k],
++									false,
++									mode_lib->vba.Output[k],
++									mode_lib->vba.OutputFormat[k],
++									mode_lib->vba.DSCInputBitPerComponent[k]);
++						mode_lib->vba.OutbppDSC = TruncToValidBPP(
++								(1.0 - mode_lib->vba.Downspreading / 100.0) * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 540.0
++								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
++								mode_lib->vba.ForcedOutputLinkBPP[k],
++								true,
++								mode_lib->vba.Output[k],
++								mode_lib->vba.OutputFormat[k],
++								mode_lib->vba.DSCInputBitPerComponent[k]);
++						if (mode_lib->vba.DSCEnabled[k] == true) {
++							locals->RequiresDSC[i][k] = true;
++							if (mode_lib->vba.Output[k] == dm_dp) {
++								locals->RequiresFEC[i][k] = true;
++							} else {
++								locals->RequiresFEC[i][k] = false;
++							}
++							mode_lib->vba.Outbpp = mode_lib->vba.OutbppDSC;
++						} else {
++							locals->RequiresDSC[i][k] = false;
++							locals->RequiresFEC[i][k] = false;
++						}
++						locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
++					}
++					if (mode_lib->vba.Outbpp == BPP_INVALID
++							&& mode_lib->vba.PHYCLKPerState[i]
++									>= 810.0) {
++						mode_lib->vba.Outbpp = TruncToValidBPP(
++								(1.0 - mode_lib->vba.Downspreading / 100.0) * 810.0
++								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
++								mode_lib->vba.ForcedOutputLinkBPP[k],
++								false,
++								mode_lib->vba.Output[k],
++								mode_lib->vba.OutputFormat[k],
++								mode_lib->vba.DSCInputBitPerComponent[k]);
++						mode_lib->vba.OutbppDSC = TruncToValidBPP(
++								(1.0 - mode_lib->vba.Downspreading / 100.0) * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 810.0
++								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
++								mode_lib->vba.ForcedOutputLinkBPP[k],
++								true,
++								mode_lib->vba.Output[k],
++								mode_lib->vba.OutputFormat[k],
++								mode_lib->vba.DSCInputBitPerComponent[k]);
++						if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) {
++							locals->RequiresDSC[i][k] = true;
++							if (mode_lib->vba.Output[k] == dm_dp) {
++								locals->RequiresFEC[i][k] = true;
++							} else {
++								locals->RequiresFEC[i][k] = false;
++							}
++							mode_lib->vba.Outbpp = mode_lib->vba.OutbppDSC;
++						} else {
++							locals->RequiresDSC[i][k] = false;
++							locals->RequiresFEC[i][k] = false;
++						}
++						locals->OutputBppPerState[i][k] =
++								mode_lib->vba.Outbpp;
++					}
++				}
++			} else {
++				locals->OutputBppPerState[i][k] = BPP_BLENDED_PIPE;
++			}
++		}
++	}
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		locals->DIOSupport[i] = true;
++		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++			if (locals->OutputBppPerState[i][k] == BPP_INVALID
++					|| (mode_lib->vba.OutputFormat[k] == dm_420
++							&& mode_lib->vba.Interlace[k] == true
++							&& mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true)) {
++				locals->DIOSupport[i] = false;
++			}
++		}
++	}
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++			locals->DSCCLKRequiredMoreThanSupported[i] = false;
++			if (mode_lib->vba.BlendingAndTiming[k] == k) {
++				if ((mode_lib->vba.Output[k] == dm_dp
++						|| mode_lib->vba.Output[k] == dm_edp)) {
++					if (mode_lib->vba.OutputFormat[k] == dm_420
++							|| mode_lib->vba.OutputFormat[k]
++									== dm_n422) {
++						mode_lib->vba.DSCFormatFactor = 2;
++					} else {
++						mode_lib->vba.DSCFormatFactor = 1;
++					}
++					if (locals->RequiresDSC[i][k] == true) {
++						if (locals->ODMCombineEnablePerState[i][k]
++								== true) {
++							if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor
++									> (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i]) {
++								locals->DSCCLKRequiredMoreThanSupported[i] =
++										true;
++							}
++						} else {
++							if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor
++									> (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i]) {
++								locals->DSCCLKRequiredMoreThanSupported[i] =
++										true;
++							}
++						}
++					}
++				}
++			}
++		}
++	}
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		locals->NotEnoughDSCUnits[i] = false;
++		mode_lib->vba.TotalDSCUnitsRequired = 0.0;
++		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++			if (locals->RequiresDSC[i][k] == true) {
++				if (locals->ODMCombineEnablePerState[i][k] == true) {
++					mode_lib->vba.TotalDSCUnitsRequired =
++							mode_lib->vba.TotalDSCUnitsRequired + 2.0;
++				} else {
++					mode_lib->vba.TotalDSCUnitsRequired =
++							mode_lib->vba.TotalDSCUnitsRequired + 1.0;
++				}
++			}
++		}
++		if (mode_lib->vba.TotalDSCUnitsRequired > mode_lib->vba.NumberOfDSC) {
++			locals->NotEnoughDSCUnits[i] = true;
++		}
++	}
++	/*DSC Delay per state*/
++
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++			if (mode_lib->vba.BlendingAndTiming[k] != k) {
++				mode_lib->vba.slices = 0;
++			} else if (locals->RequiresDSC[i][k] == 0
++					|| locals->RequiresDSC[i][k] == false) {
++				mode_lib->vba.slices = 0;
++			} else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) {
++				mode_lib->vba.slices = dml_ceil(
++						mode_lib->vba.PixelClockBackEnd[k] / 400.0,
++						4.0);
++			} else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) {
++				mode_lib->vba.slices = 8.0;
++			} else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) {
++				mode_lib->vba.slices = 4.0;
++			} else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) {
++				mode_lib->vba.slices = 2.0;
++			} else {
++				mode_lib->vba.slices = 1.0;
++			}
++			if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE
++					|| locals->OutputBppPerState[i][k] == BPP_INVALID) {
++				mode_lib->vba.bpp = 0.0;
++			} else {
++				mode_lib->vba.bpp = locals->OutputBppPerState[i][k];
++			}
++			if (locals->RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) {
++				if (locals->ODMCombineEnablePerState[i][k] == false) {
++					locals->DSCDelayPerState[i][k] =
++							dscceComputeDelay(
++									mode_lib->vba.DSCInputBitPerComponent[k],
++									mode_lib->vba.bpp,
++									dml_ceil(
++											mode_lib->vba.HActive[k]
++													/ mode_lib->vba.slices,
++											1.0),
++									mode_lib->vba.slices,
++									mode_lib->vba.OutputFormat[k])
++									+ dscComputeDelay(
++											mode_lib->vba.OutputFormat[k]);
++				} else {
++					locals->DSCDelayPerState[i][k] =
++							2.0 * (dscceComputeDelay(
++											mode_lib->vba.DSCInputBitPerComponent[k],
++											mode_lib->vba.bpp,
++											dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0),
++											mode_lib->vba.slices / 2,
++											mode_lib->vba.OutputFormat[k])
++									+ dscComputeDelay(mode_lib->vba.OutputFormat[k]));
++				}
++				locals->DSCDelayPerState[i][k] =
++						locals->DSCDelayPerState[i][k] * mode_lib->vba.PixelClock[k] / mode_lib->vba.PixelClockBackEnd[k];
++			} else {
++				locals->DSCDelayPerState[i][k] = 0.0;
++			}
++		}
++		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++			for (m = 0; m <= mode_lib->vba.NumberOfActivePlanes - 1; m++) {
++				for (j = 0; j <= mode_lib->vba.NumberOfActivePlanes - 1; j++) {
++					if (mode_lib->vba.BlendingAndTiming[k] == m && locals->RequiresDSC[i][m] == true)
++						locals->DSCDelayPerState[i][k] = locals->DSCDelayPerState[i][m];
++				}
++			}
++		}
++	}
++
++	//Prefetch Check
++	for (i = 0; i <= mode_lib->vba.soc.num_states; ++i) {
++		for (j = 0; j <= 1; ++j) {
++			locals->TotalNumberOfDCCActiveDPP[i][j] = 0;
++			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++				if (mode_lib->vba.DCCEnable[k] == true)
++					locals->TotalNumberOfDCCActiveDPP[i][j] = locals->TotalNumberOfDCCActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
++			}
++		}
++	}
++
++	mode_lib->vba.UrgentLatency = dml_max3(
++			mode_lib->vba.UrgentLatencyPixelDataOnly,
++			mode_lib->vba.UrgentLatencyPixelMixedWithVMData,
++			mode_lib->vba.UrgentLatencyVMDataOnly);
++	mode_lib->vba.PrefetchERROR = CalculateMinAndMaxPrefetchMode(
++			mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
++			&mode_lib->vba.MinPrefetchMode,
++			&mode_lib->vba.MaxPrefetchMode);
++
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		for (j = 0; j < 2; j++) {
++			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++				locals->RequiredDPPCLKThisState[k] = locals->RequiredDPPCLK[i][j][k];
++				locals->NoOfDPPThisState[k]        = locals->NoOfDPP[i][j][k];
++				if (locals->ODMCombineEnablePerState[i][k] == true) {
++					locals->SwathWidthYThisState[k] =
++						dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]));
++				} else {
++					locals->SwathWidthYThisState[k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k];
++				}
++				mode_lib->vba.SwathWidthGranularityY = 256.0
++					/ dml_ceil(locals->BytePerPixelInDETY[k], 1.0)
++					/ locals->MaxSwathHeightY[k];
++				mode_lib->vba.RoundedUpMaxSwathSizeBytesY =
++					(dml_ceil(locals->SwathWidthYThisState[k] - 1.0, mode_lib->vba.SwathWidthGranularityY)
++					+ mode_lib->vba.SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k];
++				if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
++					mode_lib->vba.RoundedUpMaxSwathSizeBytesY = dml_ceil(
++							mode_lib->vba.RoundedUpMaxSwathSizeBytesY,
++							256.0) + 256;
++				}
++				if (locals->MaxSwathHeightC[k] > 0.0) {
++					mode_lib->vba.SwathWidthGranularityC = 256.0 / dml_ceil(locals->BytePerPixelInDETC[k], 2.0) / locals->MaxSwathHeightC[k];
++					mode_lib->vba.RoundedUpMaxSwathSizeBytesC = (dml_ceil(locals->SwathWidthYThisState[k] / 2.0 - 1.0, mode_lib->vba.SwathWidthGranularityC)
++							+ mode_lib->vba.SwathWidthGranularityC) * locals->BytePerPixelInDETC[k] * locals->MaxSwathHeightC[k];
++					if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
++						mode_lib->vba.RoundedUpMaxSwathSizeBytesC = dml_ceil(mode_lib->vba.RoundedUpMaxSwathSizeBytesC, 256.0) + 256;
++					}
++				} else {
++					mode_lib->vba.RoundedUpMaxSwathSizeBytesC = 0.0;
++				}
++				if (mode_lib->vba.RoundedUpMaxSwathSizeBytesY + mode_lib->vba.RoundedUpMaxSwathSizeBytesC
++						<= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) {
++					locals->SwathHeightYThisState[k] = locals->MaxSwathHeightY[k];
++					locals->SwathHeightCThisState[k] = locals->MaxSwathHeightC[k];
++				} else {
++					locals->SwathHeightYThisState[k] =
++							locals->MinSwathHeightY[k];
++					locals->SwathHeightCThisState[k] =
++							locals->MinSwathHeightC[k];
++				}
++			}
++
++			CalculateDCFCLKDeepSleep(
++					mode_lib,
++					mode_lib->vba.NumberOfActivePlanes,
++					locals->BytePerPixelInDETY,
++					locals->BytePerPixelInDETC,
++					mode_lib->vba.VRatio,
++					locals->SwathWidthYThisState,
++					locals->NoOfDPPThisState,
++					mode_lib->vba.HRatio,
++					mode_lib->vba.PixelClock,
++					locals->PSCL_FACTOR,
++					locals->PSCL_FACTOR_CHROMA,
++					locals->RequiredDPPCLKThisState,
++					&mode_lib->vba.ProjectedDCFCLKDeepSleep);
++
++			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++				if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
++						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)) {
++					mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = CalculateVMAndRowBytes(
++							mode_lib,
++							mode_lib->vba.DCCEnable[k],
++							locals->Read256BlockHeightC[k],
++							locals->Read256BlockWidthC[k],
++							mode_lib->vba.SourcePixelFormat[k],
++							mode_lib->vba.SurfaceTiling[k],
++							dml_ceil(locals->BytePerPixelInDETC[k], 2.0),
++							mode_lib->vba.SourceScan[k],
++							mode_lib->vba.ViewportWidth[k] / 2.0,
++							mode_lib->vba.ViewportHeight[k] / 2.0,
++							locals->SwathWidthYThisState[k] / 2.0,
++							mode_lib->vba.GPUVMEnable,
++							mode_lib->vba.HostVMEnable,
++							mode_lib->vba.HostVMMaxPageTableLevels,
++							mode_lib->vba.HostVMCachedPageTableLevels,
++							mode_lib->vba.VMMPageSize,
++							mode_lib->vba.PTEBufferSizeInRequestsChroma,
++							mode_lib->vba.PitchC[k],
++							0.0,
++							&locals->MacroTileWidthC[k],
++							&mode_lib->vba.MetaRowBytesC,
++							&mode_lib->vba.DPTEBytesPerRowC,
++							&locals->PTEBufferSizeNotExceededC[i][j][k],
++							locals->dpte_row_width_chroma_ub,
++							&locals->dpte_row_height_chroma[k],
++							&locals->meta_req_width_chroma[k],
++							&locals->meta_req_height_chroma[k],
++							&locals->meta_row_width_chroma[k],
++							&locals->meta_row_height_chroma[k],
++							&locals->vm_group_bytes_chroma,
++							&locals->dpte_group_bytes_chroma,
++							locals->PixelPTEReqWidthC,
++							locals->PixelPTEReqHeightC,
++							locals->PTERequestSizeC,
++							locals->dpde0_bytes_per_frame_ub_c,
++							locals->meta_pte_bytes_per_frame_ub_c);
++					locals->PrefetchLinesC[k] = CalculatePrefetchSourceLines(
++							mode_lib,
++							mode_lib->vba.VRatio[k]/2,
++							mode_lib->vba.VTAPsChroma[k],
++							mode_lib->vba.Interlace[k],
++							mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
++							locals->SwathHeightCThisState[k],
++							mode_lib->vba.ViewportYStartC[k],
++							&locals->PrefillC[k],
++							&locals->MaxNumSwC[k]);
++					locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma;
++				} else {
++					mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = 0.0;
++					mode_lib->vba.MetaRowBytesC = 0.0;
++					mode_lib->vba.DPTEBytesPerRowC = 0.0;
++					locals->PrefetchLinesC[k] = 0.0;
++					locals->PTEBufferSizeNotExceededC[i][j][k] = true;
++					locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma + mode_lib->vba.PTEBufferSizeInRequestsChroma;
++				}
++				mode_lib->vba.PDEAndMetaPTEBytesPerFrameY = CalculateVMAndRowBytes(
++						mode_lib,
++						mode_lib->vba.DCCEnable[k],
++						locals->Read256BlockHeightY[k],
++						locals->Read256BlockWidthY[k],
++						mode_lib->vba.SourcePixelFormat[k],
++						mode_lib->vba.SurfaceTiling[k],
++						dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
++						mode_lib->vba.SourceScan[k],
++						mode_lib->vba.ViewportWidth[k],
++						mode_lib->vba.ViewportHeight[k],
++						locals->SwathWidthYThisState[k],
++						mode_lib->vba.GPUVMEnable,
++						mode_lib->vba.HostVMEnable,
++						mode_lib->vba.HostVMMaxPageTableLevels,
++						mode_lib->vba.HostVMCachedPageTableLevels,
++						mode_lib->vba.VMMPageSize,
++						locals->PTEBufferSizeInRequestsForLuma,
++						mode_lib->vba.PitchY[k],
++						mode_lib->vba.DCCMetaPitchY[k],
++						&locals->MacroTileWidthY[k],
++						&mode_lib->vba.MetaRowBytesY,
++						&mode_lib->vba.DPTEBytesPerRowY,
++						&locals->PTEBufferSizeNotExceededY[i][j][k],
++						locals->dpte_row_width_luma_ub,
++						&locals->dpte_row_height[k],
++						&locals->meta_req_width[k],
++						&locals->meta_req_height[k],
++						&locals->meta_row_width[k],
++						&locals->meta_row_height[k],
++						&locals->vm_group_bytes[k],
++						&locals->dpte_group_bytes[k],
++						locals->PixelPTEReqWidthY,
++						locals->PixelPTEReqHeightY,
++						locals->PTERequestSizeY,
++						locals->dpde0_bytes_per_frame_ub_l,
++						locals->meta_pte_bytes_per_frame_ub_l);
++				locals->PrefetchLinesY[k] = CalculatePrefetchSourceLines(
++						mode_lib,
++						mode_lib->vba.VRatio[k],
++						mode_lib->vba.vtaps[k],
++						mode_lib->vba.Interlace[k],
++						mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
++						locals->SwathHeightYThisState[k],
++						mode_lib->vba.ViewportYStartY[k],
++						&locals->PrefillY[k],
++						&locals->MaxNumSwY[k]);
++				locals->PDEAndMetaPTEBytesPerFrame[k] =
++						mode_lib->vba.PDEAndMetaPTEBytesPerFrameY + mode_lib->vba.PDEAndMetaPTEBytesPerFrameC;
++				locals->MetaRowBytes[k] = mode_lib->vba.MetaRowBytesY + mode_lib->vba.MetaRowBytesC;
++				locals->DPTEBytesPerRow[k] = mode_lib->vba.DPTEBytesPerRowY + mode_lib->vba.DPTEBytesPerRowC;
++
++				CalculateActiveRowBandwidth(
++						mode_lib->vba.GPUVMEnable,
++						mode_lib->vba.SourcePixelFormat[k],
++						mode_lib->vba.VRatio[k],
++						mode_lib->vba.DCCEnable[k],
++						mode_lib->vba.HTotal[k] /
++						mode_lib->vba.PixelClock[k],
++						mode_lib->vba.MetaRowBytesY,
++						mode_lib->vba.MetaRowBytesC,
++						locals->meta_row_height[k],
++						locals->meta_row_height_chroma[k],
++						mode_lib->vba.DPTEBytesPerRowY,
++						mode_lib->vba.DPTEBytesPerRowC,
++						locals->dpte_row_height[k],
++						locals->dpte_row_height_chroma[k],
++						&locals->meta_row_bw[k],
++						&locals->dpte_row_bw[k]);
++			}
++			mode_lib->vba.ExtraLatency = CalculateExtraLatency(
++					locals->UrgentRoundTripAndOutOfOrderLatencyPerState[i],
++					locals->TotalNumberOfActiveDPP[i][j],
++					mode_lib->vba.PixelChunkSizeInKByte,
++					locals->TotalNumberOfDCCActiveDPP[i][j],
++					mode_lib->vba.MetaChunkSize,
++					locals->ReturnBWPerState[i],
++					mode_lib->vba.GPUVMEnable,
++					mode_lib->vba.HostVMEnable,
++					mode_lib->vba.NumberOfActivePlanes,
++					locals->NoOfDPPThisState,
++					locals->dpte_group_bytes,
++					mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
++					mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
++					mode_lib->vba.HostVMMaxPageTableLevels,
++					mode_lib->vba.HostVMCachedPageTableLevels);
++
++			mode_lib->vba.TimeCalc = 24.0 / mode_lib->vba.ProjectedDCFCLKDeepSleep;
++			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++				if (mode_lib->vba.BlendingAndTiming[k] == k) {
++					if (mode_lib->vba.WritebackEnable[k] == true) {
++						locals->WritebackDelay[i][k] = mode_lib->vba.WritebackLatency
++								+ CalculateWriteBackDelay(
++										mode_lib->vba.WritebackPixelFormat[k],
++										mode_lib->vba.WritebackHRatio[k],
++										mode_lib->vba.WritebackVRatio[k],
++										mode_lib->vba.WritebackLumaHTaps[k],
++										mode_lib->vba.WritebackLumaVTaps[k],
++										mode_lib->vba.WritebackChromaHTaps[k],
++										mode_lib->vba.WritebackChromaVTaps[k],
++										mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j];
++					} else {
++						locals->WritebackDelay[i][k] = 0.0;
++					}
++					for (m = 0; m <= mode_lib->vba.NumberOfActivePlanes - 1; m++) {
++						if (mode_lib->vba.BlendingAndTiming[m] == k
++								&& mode_lib->vba.WritebackEnable[m]
++										== true) {
++							locals->WritebackDelay[i][k] = dml_max(locals->WritebackDelay[i][k],
++											mode_lib->vba.WritebackLatency + CalculateWriteBackDelay(
++													mode_lib->vba.WritebackPixelFormat[m],
++													mode_lib->vba.WritebackHRatio[m],
++													mode_lib->vba.WritebackVRatio[m],
++													mode_lib->vba.WritebackLumaHTaps[m],
++													mode_lib->vba.WritebackLumaVTaps[m],
++													mode_lib->vba.WritebackChromaHTaps[m],
++													mode_lib->vba.WritebackChromaVTaps[m],
++													mode_lib->vba.WritebackDestinationWidth[m]) / locals->RequiredDISPCLK[i][j]);
++						}
++					}
++				}
++			}
++			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++				for (m = 0; m <= mode_lib->vba.NumberOfActivePlanes - 1; m++) {
++					if (mode_lib->vba.BlendingAndTiming[k] == m) {
++						locals->WritebackDelay[i][k] = locals->WritebackDelay[i][m];
++					}
++				}
++			}
++			mode_lib->vba.MaxMaxVStartup = 0;
++			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++				locals->MaximumVStartup[k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
++					- dml_max(1.0, dml_ceil(locals->WritebackDelay[i][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0));
++				mode_lib->vba.MaxMaxVStartup = dml_max(mode_lib->vba.MaxMaxVStartup, locals->MaximumVStartup[k]);
++			}
++
++			mode_lib->vba.NextPrefetchMode = mode_lib->vba.MinPrefetchMode;
++			mode_lib->vba.NextMaxVStartup = mode_lib->vba.MaxMaxVStartup;
++			do {
++				mode_lib->vba.PrefetchMode[i][j] = mode_lib->vba.NextPrefetchMode;
++				mode_lib->vba.MaxVStartup = mode_lib->vba.NextMaxVStartup;
++
++				mode_lib->vba.TWait = CalculateTWait(
++						mode_lib->vba.PrefetchMode[i][j],
++						mode_lib->vba.DRAMClockChangeLatency,
++						mode_lib->vba.UrgentLatency,
++						mode_lib->vba.SREnterPlusExitTime);
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					Pipe myPipe;
++					HostVM myHostVM;
++
++					if (mode_lib->vba.XFCEnabled[k] == true) {
++						mode_lib->vba.XFCRemoteSurfaceFlipDelay =
++								CalculateRemoteSurfaceFlipDelay(
++										mode_lib,
++										mode_lib->vba.VRatio[k],
++										locals->SwathWidthYThisState[k],
++										dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
++										mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
++										mode_lib->vba.XFCTSlvVupdateOffset,
++										mode_lib->vba.XFCTSlvVupdateWidth,
++										mode_lib->vba.XFCTSlvVreadyOffset,
++										mode_lib->vba.XFCXBUFLatencyTolerance,
++										mode_lib->vba.XFCFillBWOverhead,
++										mode_lib->vba.XFCSlvChunkSize,
++										mode_lib->vba.XFCBusTransportTime,
++										mode_lib->vba.TimeCalc,
++										mode_lib->vba.TWait,
++										&mode_lib->vba.SrcActiveDrainRate,
++										&mode_lib->vba.TInitXFill,
++										&mode_lib->vba.TslvChk);
++					} else {
++						mode_lib->vba.XFCRemoteSurfaceFlipDelay = 0.0;
++					}
++
++					myPipe.DPPCLK = locals->RequiredDPPCLK[i][j][k];
++					myPipe.DISPCLK = locals->RequiredDISPCLK[i][j];
++					myPipe.PixelClock = mode_lib->vba.PixelClock[k];
++					myPipe.DCFCLKDeepSleep = mode_lib->vba.ProjectedDCFCLKDeepSleep;
++					myPipe.DPPPerPlane = locals->NoOfDPP[i][j][k];
++					myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
++					myPipe.SourceScan = mode_lib->vba.SourceScan[k];
++					myPipe.BlockWidth256BytesY = locals->Read256BlockWidthY[k];
++					myPipe.BlockHeight256BytesY = locals->Read256BlockHeightY[k];
++					myPipe.BlockWidth256BytesC = locals->Read256BlockWidthC[k];
++					myPipe.BlockHeight256BytesC = locals->Read256BlockHeightC[k];
++					myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
++					myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k];
++					myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k];
++					myPipe.HTotal = mode_lib->vba.HTotal[k];
++
++
++					myHostVM.Enable = mode_lib->vba.HostVMEnable;
++					myHostVM.MaxPageTableLevels = mode_lib->vba.HostVMMaxPageTableLevels;
++					myHostVM.CachedPageTableLevels = mode_lib->vba.HostVMCachedPageTableLevels;
++
++
++					mode_lib->vba.IsErrorResult[i][j][k] = CalculatePrefetchSchedule(
++							mode_lib,
++							mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
++							mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
++							&myPipe,
++							locals->DSCDelayPerState[i][k],
++							mode_lib->vba.DPPCLKDelaySubtotal,
++							mode_lib->vba.DPPCLKDelaySCL,
++							mode_lib->vba.DPPCLKDelaySCLLBOnly,
++							mode_lib->vba.DPPCLKDelayCNVCFormater,
++							mode_lib->vba.DPPCLKDelayCNVCCursor,
++							mode_lib->vba.DISPCLKDelaySubtotal,
++							locals->SwathWidthYThisState[k] / mode_lib->vba.HRatio[k],
++							mode_lib->vba.OutputFormat[k],
++							mode_lib->vba.MaxInterDCNTileRepeaters,
++							dml_min(mode_lib->vba.MaxVStartup, locals->MaximumVStartup[k]),
++							locals->MaximumVStartup[k],
++							mode_lib->vba.GPUVMMaxPageTableLevels,
++							mode_lib->vba.GPUVMEnable,
++							&myHostVM,
++							mode_lib->vba.DynamicMetadataEnable[k],
++							mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
++							mode_lib->vba.DynamicMetadataTransmittedBytes[k],
++							mode_lib->vba.DCCEnable[k],
++							mode_lib->vba.UrgentLatency,
++							mode_lib->vba.ExtraLatency,
++							mode_lib->vba.TimeCalc,
++							locals->PDEAndMetaPTEBytesPerFrame[k],
++							locals->MetaRowBytes[k],
++							locals->DPTEBytesPerRow[k],
++							locals->PrefetchLinesY[k],
++							locals->SwathWidthYThisState[k],
++							locals->BytePerPixelInDETY[k],
++							locals->PrefillY[k],
++							locals->MaxNumSwY[k],
++							locals->PrefetchLinesC[k],
++							locals->BytePerPixelInDETC[k],
++							locals->PrefillC[k],
++							locals->MaxNumSwC[k],
++							locals->SwathHeightYThisState[k],
++							locals->SwathHeightCThisState[k],
++							mode_lib->vba.TWait,
++							mode_lib->vba.XFCEnabled[k],
++							mode_lib->vba.XFCRemoteSurfaceFlipDelay,
++							mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
++							&locals->dst_x_after_scaler,
++							&locals->dst_y_after_scaler,
++							&locals->LineTimesForPrefetch[k],
++							&locals->PrefetchBW[k],
++							&locals->LinesForMetaPTE[k],
++							&locals->LinesForMetaAndDPTERow[k],
++							&locals->VRatioPreY[i][j][k],
++							&locals->VRatioPreC[i][j][k],
++							&locals->RequiredPrefetchPixelDataBWLuma[i][j][k],
++							&locals->RequiredPrefetchPixelDataBWChroma[i][j][k],
++							&locals->VStartupRequiredWhenNotEnoughTimeForDynamicMetadata,
++							&locals->Tno_bw[k],
++							&locals->prefetch_vmrow_bw[k],
++							locals->swath_width_luma_ub,
++							locals->swath_width_chroma_ub,
++							&mode_lib->vba.VUpdateOffsetPix[k],
++							&mode_lib->vba.VUpdateWidthPix[k],
++							&mode_lib->vba.VReadyOffsetPix[k]);
++				}
++				mode_lib->vba.MaximumReadBandwidthWithoutPrefetch = 0.0;
++				mode_lib->vba.MaximumReadBandwidthWithPrefetch = 0.0;
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					uint m;
++
++					locals->cursor_bw[k] = 0;
++					locals->cursor_bw_pre[k] = 0;
++					for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) {
++						locals->cursor_bw[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m]
++							/ 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
++						locals->cursor_bw_pre[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m]
++							/ 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * locals->VRatioPreY[i][j][k];
++					}
++
++					CalculateUrgentBurstFactor(
++							mode_lib->vba.DETBufferSizeInKByte,
++							locals->SwathHeightYThisState[k],
++							locals->SwathHeightCThisState[k],
++							locals->SwathWidthYThisState[k],
++							mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
++							mode_lib->vba.UrgentLatency,
++							mode_lib->vba.CursorBufferSize,
++							mode_lib->vba.CursorWidth[k][0] + mode_lib->vba.CursorWidth[k][1],
++							dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]),
++							mode_lib->vba.VRatio[k],
++							locals->VRatioPreY[i][j][k],
++							locals->VRatioPreC[i][j][k],
++							locals->BytePerPixelInDETY[k],
++							locals->BytePerPixelInDETC[k],
++							&locals->UrgentBurstFactorCursor[k],
++							&locals->UrgentBurstFactorCursorPre[k],
++							&locals->UrgentBurstFactorLuma[k],
++							&locals->UrgentBurstFactorLumaPre[k],
++							&locals->UrgentBurstFactorChroma[k],
++							&locals->UrgentBurstFactorChromaPre[k],
++							&locals->NotEnoughUrgentLatencyHiding,
++							&locals->NotEnoughUrgentLatencyHidingPre);
++
++					if (mode_lib->vba.UseUrgentBurstBandwidth == false) {
++						locals->UrgentBurstFactorCursor[k] = 1;
++						locals->UrgentBurstFactorCursorPre[k] = 1;
++						locals->UrgentBurstFactorLuma[k] = 1;
++						locals->UrgentBurstFactorLumaPre[k] = 1;
++						locals->UrgentBurstFactorChroma[k] = 1;
++						locals->UrgentBurstFactorChromaPre[k] = 1;
++					}
++
++					mode_lib->vba.MaximumReadBandwidthWithoutPrefetch = mode_lib->vba.MaximumReadBandwidthWithoutPrefetch
++						+ locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k] + locals->ReadBandwidthLuma[k]
++						* locals->UrgentBurstFactorLuma[k] + locals->ReadBandwidthChroma[k]
++						* locals->UrgentBurstFactorChroma[k] + locals->meta_row_bw[k] + locals->dpte_row_bw[k];
++					mode_lib->vba.MaximumReadBandwidthWithPrefetch = mode_lib->vba.MaximumReadBandwidthWithPrefetch
++						+ dml_max3(locals->prefetch_vmrow_bw[k],
++						locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k] + locals->ReadBandwidthChroma[k]
++						* locals->UrgentBurstFactorChroma[k] + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k]
++						+ locals->meta_row_bw[k] + locals->dpte_row_bw[k],
++						locals->RequiredPrefetchPixelDataBWLuma[i][j][k] * locals->UrgentBurstFactorLumaPre[k]
++						+ locals->RequiredPrefetchPixelDataBWChroma[i][j][k] * locals->UrgentBurstFactorChromaPre[k]
++						+ locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
++				}
++				locals->BandwidthWithoutPrefetchSupported[i] = true;
++				if (mode_lib->vba.MaximumReadBandwidthWithoutPrefetch > locals->ReturnBWPerState[i]
++						|| locals->NotEnoughUrgentLatencyHiding == 1) {
++					locals->BandwidthWithoutPrefetchSupported[i] = false;
++				}
++
++				locals->PrefetchSupported[i][j] = true;
++				if (mode_lib->vba.MaximumReadBandwidthWithPrefetch > locals->ReturnBWPerState[i]
++						|| locals->NotEnoughUrgentLatencyHiding == 1
++						|| locals->NotEnoughUrgentLatencyHidingPre == 1) {
++					locals->PrefetchSupported[i][j] = false;
++				}
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					if (locals->LineTimesForPrefetch[k] < 2.0
++							|| locals->LinesForMetaPTE[k] >= 32.0
++							|| locals->LinesForMetaAndDPTERow[k] >= 16.0
++							|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
++						locals->PrefetchSupported[i][j] = false;
++					}
++				}
++				locals->VRatioInPrefetchSupported[i][j] = true;
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					if (locals->VRatioPreY[i][j][k] > 4.0
++							|| locals->VRatioPreC[i][j][k] > 4.0
++							|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
++						locals->VRatioInPrefetchSupported[i][j] = false;
++					}
++				}
++				mode_lib->vba.AnyLinesForVMOrRowTooLarge = false;
++				for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++					if (locals->LinesForMetaAndDPTERow[k] >= 16 || locals->LinesForMetaPTE[k] >= 32) {
++						mode_lib->vba.AnyLinesForVMOrRowTooLarge = true;
++					}
++				}
++
++				if (mode_lib->vba.MaxVStartup <= 13 || mode_lib->vba.AnyLinesForVMOrRowTooLarge == false) {
++					mode_lib->vba.NextMaxVStartup = mode_lib->vba.MaxMaxVStartup;
++					mode_lib->vba.NextPrefetchMode = mode_lib->vba.NextPrefetchMode + 1;
++				} else {
++					mode_lib->vba.NextMaxVStartup = mode_lib->vba.NextMaxVStartup - 1;
++				}
++			} while ((locals->PrefetchSupported[i][j] != true || locals->VRatioInPrefetchSupported[i][j] != true)
++					&& (mode_lib->vba.NextMaxVStartup != mode_lib->vba.MaxMaxVStartup
++						|| mode_lib->vba.NextPrefetchMode < mode_lib->vba.MaxPrefetchMode));
++
++			if (locals->PrefetchSupported[i][j] == true && locals->VRatioInPrefetchSupported[i][j] == true) {
++				mode_lib->vba.BandwidthAvailableForImmediateFlip = locals->ReturnBWPerState[i];
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					mode_lib->vba.BandwidthAvailableForImmediateFlip = mode_lib->vba.BandwidthAvailableForImmediateFlip
++						- dml_max(locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k]
++							+ locals->ReadBandwidthChroma[k] * locals->UrgentBurstFactorChroma[k]
++							+ locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k],
++							locals->RequiredPrefetchPixelDataBWLuma[i][j][k] * locals->UrgentBurstFactorLumaPre[k]
++							+ locals->RequiredPrefetchPixelDataBWChroma[i][j][k] * locals->UrgentBurstFactorChromaPre[k]
++							+ locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
++				}
++				mode_lib->vba.TotImmediateFlipBytes = 0.0;
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes
++						+ locals->PDEAndMetaPTEBytesPerFrame[k] + locals->MetaRowBytes[k] + locals->DPTEBytesPerRow[k];
++				}
++
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					CalculateFlipSchedule(
++							mode_lib,
++							mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
++							mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
++							mode_lib->vba.ExtraLatency,
++							mode_lib->vba.UrgentLatency,
++							mode_lib->vba.GPUVMMaxPageTableLevels,
++							mode_lib->vba.HostVMEnable,
++							mode_lib->vba.HostVMMaxPageTableLevels,
++							mode_lib->vba.HostVMCachedPageTableLevels,
++							mode_lib->vba.GPUVMEnable,
++							locals->PDEAndMetaPTEBytesPerFrame[k],
++							locals->MetaRowBytes[k],
++							locals->DPTEBytesPerRow[k],
++							mode_lib->vba.BandwidthAvailableForImmediateFlip,
++							mode_lib->vba.TotImmediateFlipBytes,
++							mode_lib->vba.SourcePixelFormat[k],
++							mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
++							mode_lib->vba.VRatio[k],
++							locals->Tno_bw[k],
++							mode_lib->vba.DCCEnable[k],
++							locals->dpte_row_height[k],
++							locals->meta_row_height[k],
++							locals->dpte_row_height_chroma[k],
++							locals->meta_row_height_chroma[k],
++							&locals->DestinationLinesToRequestVMInImmediateFlip[k],
++							&locals->DestinationLinesToRequestRowInImmediateFlip[k],
++							&locals->final_flip_bw[k],
++							&locals->ImmediateFlipSupportedForPipe[k]);
++				}
++				mode_lib->vba.total_dcn_read_bw_with_flip = 0.0;
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					mode_lib->vba.total_dcn_read_bw_with_flip = mode_lib->vba.total_dcn_read_bw_with_flip + dml_max3(
++						locals->prefetch_vmrow_bw[k],
++						locals->final_flip_bw[k] +  locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k]
++						+ locals->ReadBandwidthChroma[k] * locals->UrgentBurstFactorChroma[k]
++						+ locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k],
++						locals->final_flip_bw[k] + locals->RequiredPrefetchPixelDataBWLuma[i][j][k]
++						* locals->UrgentBurstFactorLumaPre[k] + locals->RequiredPrefetchPixelDataBWChroma[i][j][k]
++						* locals->UrgentBurstFactorChromaPre[k] + locals->cursor_bw_pre[k]
++						* locals->UrgentBurstFactorCursorPre[k]);
++				}
++				locals->ImmediateFlipSupportedForState[i][j] = true;
++				if (mode_lib->vba.total_dcn_read_bw_with_flip
++						> locals->ReturnBWPerState[i]) {
++					locals->ImmediateFlipSupportedForState[i][j] = false;
++				}
++				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++					if (locals->ImmediateFlipSupportedForPipe[k] == false) {
++						locals->ImmediateFlipSupportedForState[i][j] = false;
++					}
++				}
++			} else {
++				locals->ImmediateFlipSupportedForState[i][j] = false;
++			}
++			mode_lib->vba.UrgentOutOfOrderReturnPerChannel = dml_max3(
++					mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly,
++					mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
++					mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly);
++			CalculateWatermarksAndDRAMSpeedChangeSupport(
++					mode_lib,
++					mode_lib->vba.PrefetchMode[i][j],
++					mode_lib->vba.NumberOfActivePlanes,
++					mode_lib->vba.MaxLineBufferLines,
++					mode_lib->vba.LineBufferSize,
++					mode_lib->vba.DPPOutputBufferPixels,
++					mode_lib->vba.DETBufferSizeInKByte,
++					mode_lib->vba.WritebackInterfaceLumaBufferSize,
++					mode_lib->vba.WritebackInterfaceChromaBufferSize,
++					mode_lib->vba.DCFCLKPerState[i],
++					mode_lib->vba.UrgentOutOfOrderReturnPerChannel * mode_lib->vba.NumberOfChannels,
++					locals->ReturnBWPerState[i],
++					mode_lib->vba.GPUVMEnable,
++					locals->dpte_group_bytes,
++					mode_lib->vba.MetaChunkSize,
++					mode_lib->vba.UrgentLatency,
++					mode_lib->vba.ExtraLatency,
++					mode_lib->vba.WritebackLatency,
++					mode_lib->vba.WritebackChunkSize,
++					mode_lib->vba.SOCCLKPerState[i],
++					mode_lib->vba.DRAMClockChangeLatency,
++					mode_lib->vba.SRExitTime,
++					mode_lib->vba.SREnterPlusExitTime,
++					mode_lib->vba.ProjectedDCFCLKDeepSleep,
++					locals->NoOfDPPThisState,
++					mode_lib->vba.DCCEnable,
++					locals->RequiredDPPCLKThisState,
++					locals->SwathWidthYSingleDPP,
++					locals->SwathHeightYThisState,
++					locals->ReadBandwidthLuma,
++					locals->SwathHeightCThisState,
++					locals->ReadBandwidthChroma,
++					mode_lib->vba.LBBitPerPixel,
++					locals->SwathWidthYThisState,
++					mode_lib->vba.HRatio,
++					mode_lib->vba.vtaps,
++					mode_lib->vba.VTAPsChroma,
++					mode_lib->vba.VRatio,
++					mode_lib->vba.HTotal,
++					mode_lib->vba.PixelClock,
++					mode_lib->vba.BlendingAndTiming,
++					locals->BytePerPixelInDETY,
++					locals->BytePerPixelInDETC,
++					mode_lib->vba.WritebackEnable,
++					mode_lib->vba.WritebackPixelFormat,
++					mode_lib->vba.WritebackDestinationWidth,
++					mode_lib->vba.WritebackDestinationHeight,
++					mode_lib->vba.WritebackSourceHeight,
++					&locals->DRAMClockChangeSupport[i][j],
++					&mode_lib->vba.UrgentWatermark,
++					&mode_lib->vba.WritebackUrgentWatermark,
++					&mode_lib->vba.DRAMClockChangeWatermark,
++					&mode_lib->vba.WritebackDRAMClockChangeWatermark,
++					&mode_lib->vba.StutterExitWatermark,
++					&mode_lib->vba.StutterEnterPlusExitWatermark,
++					&mode_lib->vba.MinActiveDRAMClockChangeLatencySupported);
++			}
++		}
++
++		/*Vertical Active BW support*/
++		{
++			double MaxTotalVActiveRDBandwidth = 0.0;
++			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
++				MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + locals->ReadBandwidth[k];
++		}
++		for (i = 0; i <= mode_lib->vba.soc.num_states; ++i) {
++			locals->MaxTotalVerticalActiveAvailableBandwidth[i] = dml_min(
++				locals->IdealSDPPortBandwidthPerState[i] *
++				mode_lib->vba.MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation
++				/ 100.0, mode_lib->vba.DRAMSpeedPerState[i] *
++				mode_lib->vba.NumberOfChannels *
++				mode_lib->vba.DRAMChannelWidth *
++				mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation
++				/ 100.0);
++
++			if (MaxTotalVActiveRDBandwidth <= locals->MaxTotalVerticalActiveAvailableBandwidth[i]) {
++				locals->TotalVerticalActiveBandwidthSupport[i] = true;
++			} else {
++				locals->TotalVerticalActiveBandwidthSupport[i] = false;
++			}
++		}
++	}
++
++	/*PTE Buffer Size Check*/
++
++	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		for (j = 0; j < 2; j++) {
++			locals->PTEBufferSizeNotExceeded[i][j] = true;
++			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++				if (locals->PTEBufferSizeNotExceededY[i][j][k] == false
++						|| locals->PTEBufferSizeNotExceededC[i][j][k] == false) {
++					locals->PTEBufferSizeNotExceeded[i][j] = false;
++				}
++			}
++		}
++	}
++	/*Cursor Support Check*/
++
++	mode_lib->vba.CursorSupport = true;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.CursorWidth[k][0] > 0.0) {
++			for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) {
++				if (mode_lib->vba.CursorBPP[k][m] == 64 && mode_lib->vba.Cursor64BppSupport == false) {
++					mode_lib->vba.CursorSupport = false;
++				}
++			}
++		}
++	}
++	/*Valid Pitch Check*/
++
++	mode_lib->vba.PitchSupport = true;
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		locals->AlignedYPitch[k] = dml_ceil(
++				dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]),
++				locals->MacroTileWidthY[k]);
++		if (locals->AlignedYPitch[k] > mode_lib->vba.PitchY[k]) {
++			mode_lib->vba.PitchSupport = false;
++		}
++		if (mode_lib->vba.DCCEnable[k] == true) {
++			locals->AlignedDCCMetaPitch[k] = dml_ceil(
++					dml_max(
++							mode_lib->vba.DCCMetaPitchY[k],
++							mode_lib->vba.ViewportWidth[k]),
++					64.0 * locals->Read256BlockWidthY[k]);
++		} else {
++			locals->AlignedDCCMetaPitch[k] = mode_lib->vba.DCCMetaPitchY[k];
++		}
++		if (locals->AlignedDCCMetaPitch[k] > mode_lib->vba.DCCMetaPitchY[k]) {
++			mode_lib->vba.PitchSupport = false;
++		}
++		if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
++				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
++				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
++				&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
++				&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) {
++			locals->AlignedCPitch[k] = dml_ceil(
++					dml_max(
++							mode_lib->vba.PitchC[k],
++							mode_lib->vba.ViewportWidth[k] / 2.0),
++					locals->MacroTileWidthC[k]);
++		} else {
++			locals->AlignedCPitch[k] = mode_lib->vba.PitchC[k];
++		}
++		if (locals->AlignedCPitch[k] > mode_lib->vba.PitchC[k]) {
++			mode_lib->vba.PitchSupport = false;
++		}
++	}
++	/*Mode Support, Voltage State and SOC Configuration*/
++
++	for (i = mode_lib->vba.soc.num_states; i >= 0; i--) {
++		for (j = 0; j < 2; j++) {
++			enum dm_validation_status status = DML_VALIDATION_OK;
++
++			if (mode_lib->vba.ScaleRatioAndTapsSupport != true) {
++				status = DML_FAIL_SCALE_RATIO_TAP;
++			} else if (mode_lib->vba.SourceFormatPixelAndScanSupport != true) {
++				status = DML_FAIL_SOURCE_PIXEL_FORMAT;
++			} else if (locals->ViewportSizeSupport[i] != true) {
++				status = DML_FAIL_VIEWPORT_SIZE;
++			} else if (locals->DIOSupport[i] != true) {
++				status = DML_FAIL_DIO_SUPPORT;
++			} else if (locals->NotEnoughDSCUnits[i] != false) {
++				status = DML_FAIL_NOT_ENOUGH_DSC;
++			} else if (locals->DSCCLKRequiredMoreThanSupported[i] != false) {
++				status = DML_FAIL_DSC_CLK_REQUIRED;
++			} else if (locals->ROBSupport[i] != true) {
++				status = DML_FAIL_REORDERING_BUFFER;
++			} else if (locals->DISPCLK_DPPCLK_Support[i][j] != true) {
++				status = DML_FAIL_DISPCLK_DPPCLK;
++			} else if (locals->TotalAvailablePipesSupport[i][j] != true) {
++				status = DML_FAIL_TOTAL_AVAILABLE_PIPES;
++			} else if (mode_lib->vba.NumberOfOTGSupport != true) {
++				status = DML_FAIL_NUM_OTG;
++			} else if (mode_lib->vba.WritebackModeSupport != true) {
++				status = DML_FAIL_WRITEBACK_MODE;
++			} else if (mode_lib->vba.WritebackLatencySupport != true) {
++				status = DML_FAIL_WRITEBACK_LATENCY;
++			} else if (mode_lib->vba.WritebackScaleRatioAndTapsSupport != true) {
++				status = DML_FAIL_WRITEBACK_SCALE_RATIO_TAP;
++			} else if (mode_lib->vba.CursorSupport != true) {
++				status = DML_FAIL_CURSOR_SUPPORT;
++			} else if (mode_lib->vba.PitchSupport != true) {
++				status = DML_FAIL_PITCH_SUPPORT;
++			} else if (locals->TotalVerticalActiveBandwidthSupport[i] != true) {
++				status = DML_FAIL_TOTAL_V_ACTIVE_BW;
++			} else if (locals->PTEBufferSizeNotExceeded[i][j] != true) {
++				status = DML_FAIL_PTE_BUFFER_SIZE;
++			} else if (mode_lib->vba.NonsupportedDSCInputBPC != false) {
++				status = DML_FAIL_DSC_INPUT_BPC;
++			} else if ((mode_lib->vba.HostVMEnable != false
++					&& locals->ImmediateFlipSupportedForState[i][j] != true)) {
++				status = DML_FAIL_HOST_VM_IMMEDIATE_FLIP;
++			} else if (locals->PrefetchSupported[i][j] != true) {
++				status = DML_FAIL_PREFETCH_SUPPORT;
++			} else if (locals->VRatioInPrefetchSupported[i][j] != true) {
++				status = DML_FAIL_V_RATIO_PREFETCH;
++			}
++
++			if (status == DML_VALIDATION_OK) {
++				locals->ModeSupport[i][j] = true;
++			} else {
++				locals->ModeSupport[i][j] = false;
++			}
++			locals->ValidationStatus[i] = status;
++		}
++	}
++	{
++		unsigned int MaximumMPCCombine = 0;
++		mode_lib->vba.VoltageLevel = mode_lib->vba.soc.num_states + 1;
++		for (i = mode_lib->vba.VoltageOverrideLevel; i <= mode_lib->vba.soc.num_states; i++) {
++			if (locals->ModeSupport[i][0] == true || locals->ModeSupport[i][1] == true) {
++				mode_lib->vba.VoltageLevel = i;
++				if (locals->ModeSupport[i][1] == true && (locals->ModeSupport[i][0] == false
++						|| mode_lib->vba.WhenToDoMPCCombine == dm_mpc_always_when_possible
++						|| (mode_lib->vba.WhenToDoMPCCombine == dm_mpc_reduce_voltage_and_clocks
++							&& ((locals->DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vactive
++								&& locals->DRAMClockChangeSupport[i][0] != dm_dram_clock_change_vactive)
++							|| (locals->DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vblank
++								&& locals->DRAMClockChangeSupport[i][0] == dm_dram_clock_change_unsupported))))) {
++					MaximumMPCCombine = 1;
++				} else {
++					MaximumMPCCombine = 0;
++				}
++				break;
++			}
++		}
++		mode_lib->vba.ImmediateFlipSupport =
++			locals->ImmediateFlipSupportedForState[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
++		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++			mode_lib->vba.DPPPerPlane[k] = locals->NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
++			locals->DPPCLK[k] = locals->RequiredDPPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
++		}
++		mode_lib->vba.DISPCLK = locals->RequiredDISPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
++		mode_lib->vba.maxMpcComb = MaximumMPCCombine;
++	}
++	mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKPerState[mode_lib->vba.VoltageLevel];
++	mode_lib->vba.DRAMSpeed = mode_lib->vba.DRAMSpeedPerState[mode_lib->vba.VoltageLevel];
++	mode_lib->vba.FabricClock = mode_lib->vba.FabricClockPerState[mode_lib->vba.VoltageLevel];
++	mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel];
++	mode_lib->vba.ReturnBW = locals->ReturnBWPerState[mode_lib->vba.VoltageLevel];
++	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
++		if (mode_lib->vba.BlendingAndTiming[k] == k) {
++			mode_lib->vba.ODMCombineEnabled[k] =
++					locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
++		} else {
++			mode_lib->vba.ODMCombineEnabled[k] = 0;
++		}
++		mode_lib->vba.DSCEnabled[k] =
++				locals->RequiresDSC[mode_lib->vba.VoltageLevel][k];
++		mode_lib->vba.OutputBpp[k] =
++				locals->OutputBppPerState[mode_lib->vba.VoltageLevel][k];
++	}
++}
++
++static void CalculateWatermarksAndDRAMSpeedChangeSupport(
++		struct display_mode_lib *mode_lib,
++		unsigned int PrefetchMode,
++		unsigned int NumberOfActivePlanes,
++		unsigned int MaxLineBufferLines,
++		unsigned int LineBufferSize,
++		unsigned int DPPOutputBufferPixels,
++		double DETBufferSizeInKByte,
++		unsigned int WritebackInterfaceLumaBufferSize,
++		unsigned int WritebackInterfaceChromaBufferSize,
++		double DCFCLK,
++		double UrgentOutOfOrderReturn,
++		double ReturnBW,
++		bool GPUVMEnable,
++		long dpte_group_bytes[],
++		unsigned int MetaChunkSize,
++		double UrgentLatency,
++		double ExtraLatency,
++		double WritebackLatency,
++		double WritebackChunkSize,
++		double SOCCLK,
++		double DRAMClockChangeLatency,
++		double SRExitTime,
++		double SREnterPlusExitTime,
++		double DCFCLKDeepSleep,
++		int DPPPerPlane[],
++		bool DCCEnable[],
++		double DPPCLK[],
++		unsigned int SwathWidthSingleDPPY[],
++		unsigned int SwathHeightY[],
++		double ReadBandwidthPlaneLuma[],
++		unsigned int SwathHeightC[],
++		double ReadBandwidthPlaneChroma[],
++		unsigned int LBBitPerPixel[],
++		unsigned int SwathWidthY[],
++		double HRatio[],
++		unsigned int vtaps[],
++		unsigned int VTAPsChroma[],
++		double VRatio[],
++		unsigned int HTotal[],
++		double PixelClock[],
++		unsigned int BlendingAndTiming[],
++		double BytePerPixelDETY[],
++		double BytePerPixelDETC[],
++		bool WritebackEnable[],
++		enum source_format_class WritebackPixelFormat[],
++		double WritebackDestinationWidth[],
++		double WritebackDestinationHeight[],
++		double WritebackSourceHeight[],
++		enum clock_change_support *DRAMClockChangeSupport,
++		double *UrgentWatermark,
++		double *WritebackUrgentWatermark,
++		double *DRAMClockChangeWatermark,
++		double *WritebackDRAMClockChangeWatermark,
++		double *StutterExitWatermark,
++		double *StutterEnterPlusExitWatermark,
++		double *MinActiveDRAMClockChangeLatencySupported)
++{
++	double EffectiveLBLatencyHidingY;
++	double EffectiveLBLatencyHidingC;
++	double DPPOutputBufferLinesY;
++	double DPPOutputBufferLinesC;
++	double DETBufferSizeY;
++	double DETBufferSizeC;
++	double LinesInDETY[DC__NUM_DPP__MAX];
++	double LinesInDETC;
++	unsigned int LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
++	unsigned int LinesInDETCRoundedDownToSwath;
++	double FullDETBufferingTimeY[DC__NUM_DPP__MAX];
++	double FullDETBufferingTimeC;
++	double ActiveDRAMClockChangeLatencyMarginY;
++	double ActiveDRAMClockChangeLatencyMarginC;
++	double WritebackDRAMClockChangeLatencyMargin;
++	double PlaneWithMinActiveDRAMClockChangeMargin;
++	double SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank;
++	double FullDETBufferingTimeYStutterCriticalPlane = 0;
++	double TimeToFinishSwathTransferStutterCriticalPlane = 0;
++	uint k, j;
++
++	mode_lib->vba.TotalActiveDPP = 0;
++	mode_lib->vba.TotalDCCActiveDPP = 0;
++	for (k = 0; k < NumberOfActivePlanes; ++k) {
++		mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP + DPPPerPlane[k];
++		if (DCCEnable[k] == true) {
++			mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP + DPPPerPlane[k];
++		}
++	}
++
++	mode_lib->vba.TotalDataReadBandwidth = 0;
++	for (k = 0; k < NumberOfActivePlanes; ++k) {
++		mode_lib->vba.TotalDataReadBandwidth = mode_lib->vba.TotalDataReadBandwidth
++				+ ReadBandwidthPlaneLuma[k] + ReadBandwidthPlaneChroma[k];
++	}
++
++	*UrgentWatermark = UrgentLatency + ExtraLatency;
++
++	*DRAMClockChangeWatermark = DRAMClockChangeLatency + *UrgentWatermark;
++
++	mode_lib->vba.TotalActiveWriteback = 0;
++	for (k = 0; k < NumberOfActivePlanes; ++k) {
++		if (WritebackEnable[k] == true) {
++			mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + 1;
++		}
++	}
++
++	if (mode_lib->vba.TotalActiveWriteback <= 1) {
++		*WritebackUrgentWatermark = WritebackLatency;
++	} else {
++		*WritebackUrgentWatermark = WritebackLatency
++				+ WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
++	}
++
++	if (mode_lib->vba.TotalActiveWriteback <= 1) {
++		*WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency;
++	} else {
++		*WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency
++				+ WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
++	}
++
++	for (k = 0; k < NumberOfActivePlanes; ++k) {
++
++		mode_lib->vba.LBLatencyHidingSourceLinesY = dml_min((double) MaxLineBufferLines,
++			dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1))
++				- (vtaps[k] - 1);
++
++		mode_lib->vba.LBLatencyHidingSourceLinesC = dml_min((double) MaxLineBufferLines,
++			dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / 2 / dml_max(HRatio[k] / 2, 1.0)), 1))
++				- (VTAPsChroma[k] - 1);
++
++		EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY / VRatio[k]
++				* (HTotal[k] / PixelClock[k]);
++
++		EffectiveLBLatencyHidingC = mode_lib->vba.LBLatencyHidingSourceLinesC
++				/ (VRatio[k] / 2) * (HTotal[k] / PixelClock[k]);
++
++		if (SwathWidthY[k] > 2 * DPPOutputBufferPixels) {
++			DPPOutputBufferLinesY = (double) DPPOutputBufferPixels / SwathWidthY[k];
++		} else if (SwathWidthY[k] > DPPOutputBufferPixels) {
++			DPPOutputBufferLinesY = 0.5;
++		} else {
++			DPPOutputBufferLinesY = 1;
++		}
++
++		if (SwathWidthY[k] / 2.0 > 2 * DPPOutputBufferPixels) {
++			DPPOutputBufferLinesC = (double) DPPOutputBufferPixels
++					/ (SwathWidthY[k] / 2.0);
++		} else if (SwathWidthY[k] / 2.0 > DPPOutputBufferPixels) {
++			DPPOutputBufferLinesC = 0.5;
++		} else {
++			DPPOutputBufferLinesC = 1;
++		}
++
++		CalculateDETBufferSize(
++				DETBufferSizeInKByte,
++				SwathHeightY[k],
++				SwathHeightC[k],
++				&DETBufferSizeY,
++				&DETBufferSizeC);
++
++		LinesInDETY[k] = DETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k];
++		LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
++		FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k]
++				* (HTotal[k] / PixelClock[k]) / VRatio[k];
++		if (BytePerPixelDETC[k] > 0) {
++			LinesInDETC = DETBufferSizeC / BytePerPixelDETC[k] / (SwathWidthY[k] / 2.0);
++			LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]);
++			FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath
++					* (HTotal[k] / PixelClock[k]) / (VRatio[k] / 2);
++		} else {
++			LinesInDETC = 0;
++			FullDETBufferingTimeC = 999999;
++		}
++
++		ActiveDRAMClockChangeLatencyMarginY = HTotal[k] / PixelClock[k]
++				* DPPOutputBufferLinesY + EffectiveLBLatencyHidingY
++				+ FullDETBufferingTimeY[k] - *DRAMClockChangeWatermark;
++
++		if (NumberOfActivePlanes > 1) {
++			ActiveDRAMClockChangeLatencyMarginY = ActiveDRAMClockChangeLatencyMarginY
++				- (1 - 1.0 / NumberOfActivePlanes) * SwathHeightY[k] * HTotal[k] / PixelClock[k] / VRatio[k];
++		}
++
++		if (BytePerPixelDETC[k] > 0) {
++			ActiveDRAMClockChangeLatencyMarginC = HTotal[k] / PixelClock[k]
++					* DPPOutputBufferLinesC + EffectiveLBLatencyHidingC
++					+ FullDETBufferingTimeC - *DRAMClockChangeWatermark;
++			if (NumberOfActivePlanes > 1) {
++				ActiveDRAMClockChangeLatencyMarginC = ActiveDRAMClockChangeLatencyMarginC
++					- (1 - 1.0 / NumberOfActivePlanes) * SwathHeightC[k] * HTotal[k] / PixelClock[k] / (VRatio[k] / 2);
++			}
++			mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
++					ActiveDRAMClockChangeLatencyMarginY,
++					ActiveDRAMClockChangeLatencyMarginC);
++		} else {
++			mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
++		}
++
++		if (WritebackEnable[k] == true) {
++			if (WritebackPixelFormat[k] == dm_444_32) {
++				WritebackDRAMClockChangeLatencyMargin = (WritebackInterfaceLumaBufferSize
++					+ WritebackInterfaceChromaBufferSize) / (WritebackDestinationWidth[k]
++					* WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k]
++					/ PixelClock[k]) * 4) - *WritebackDRAMClockChangeWatermark;
++			} else {
++				WritebackDRAMClockChangeLatencyMargin = dml_min(
++						WritebackInterfaceLumaBufferSize * 8.0 / 10,
++						2 * WritebackInterfaceChromaBufferSize * 8.0 / 10) / (WritebackDestinationWidth[k]
++							* WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k]))
++						- *WritebackDRAMClockChangeWatermark;
++			}
++			mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
++					mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k],
++					WritebackDRAMClockChangeLatencyMargin);
++		}
++	}
++
++	mode_lib->vba.MinActiveDRAMClockChangeMargin = 999999;
++	PlaneWithMinActiveDRAMClockChangeMargin = 0;
++	for (k = 0; k < NumberOfActivePlanes; ++k) {
++		if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]
++				< mode_lib->vba.MinActiveDRAMClockChangeMargin) {
++			mode_lib->vba.MinActiveDRAMClockChangeMargin =
++					mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
++			if (BlendingAndTiming[k] == k) {
++				PlaneWithMinActiveDRAMClockChangeMargin = k;
++			} else {
++				for (j = 0; j < NumberOfActivePlanes; ++j) {
++					if (BlendingAndTiming[k] == j) {
++						PlaneWithMinActiveDRAMClockChangeMargin = j;
++					}
++				}
++			}
++		}
++	}
++
++	*MinActiveDRAMClockChangeLatencySupported = mode_lib->vba.MinActiveDRAMClockChangeMargin + DRAMClockChangeLatency;
++
++	SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = 999999;
++	for (k = 0; k < NumberOfActivePlanes; ++k) {
++		if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (BlendingAndTiming[k] == k))
++				&& !(BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin)
++				&& mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]
++						< SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) {
++			SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank =
++					mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
++		}
++	}
++
++	mode_lib->vba.TotalNumberOfActiveOTG = 0;
++	for (k = 0; k < NumberOfActivePlanes; ++k) {
++		if (BlendingAndTiming[k] == k) {
++			mode_lib->vba.TotalNumberOfActiveOTG = mode_lib->vba.TotalNumberOfActiveOTG + 1;
++		}
++	}
++
++	if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
++		*DRAMClockChangeSupport = dm_dram_clock_change_vactive;
++	} else if (((mode_lib->vba.SynchronizedVBlank == true
++			|| mode_lib->vba.TotalNumberOfActiveOTG == 1
++			|| SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0)
++			&& PrefetchMode == 0)) {
++		*DRAMClockChangeSupport = dm_dram_clock_change_vblank;
++	} else {
++		*DRAMClockChangeSupport = dm_dram_clock_change_unsupported;
++	}
++
++	FullDETBufferingTimeYStutterCriticalPlane = FullDETBufferingTimeY[0];
++	for (k = 0; k < NumberOfActivePlanes; ++k) {
++		if (FullDETBufferingTimeY[k] <= FullDETBufferingTimeYStutterCriticalPlane) {
++			TimeToFinishSwathTransferStutterCriticalPlane = (SwathHeightY[k]
++					- (LinesInDETY[k] - LinesInDETYRoundedDownToSwath[k]))
++					* (HTotal[k] / PixelClock[k]) / VRatio[k];
++		}
++	}
++
++	*StutterExitWatermark = SRExitTime + mode_lib->vba.LastPixelOfLineExtraWatermark
++			+ ExtraLatency + 10 / DCFCLKDeepSleep;
++	*StutterEnterPlusExitWatermark = dml_max(
++			SREnterPlusExitTime + mode_lib->vba.LastPixelOfLineExtraWatermark
++					+ ExtraLatency + 10 / DCFCLKDeepSleep,
++			TimeToFinishSwathTransferStutterCriticalPlane);
++
++}
++
++static void CalculateDCFCLKDeepSleep(
++		struct display_mode_lib *mode_lib,
++		unsigned int NumberOfActivePlanes,
++		double BytePerPixelDETY[],
++		double BytePerPixelDETC[],
++		double VRatio[],
++		unsigned int SwathWidthY[],
++		int DPPPerPlane[],
++		double HRatio[],
++		double PixelClock[],
++		double PSCL_THROUGHPUT[],
++		double PSCL_THROUGHPUT_CHROMA[],
++		double DPPCLK[],
++		double *DCFCLKDeepSleep)
++{
++	uint k;
++	double DisplayPipeLineDeliveryTimeLuma;
++	double DisplayPipeLineDeliveryTimeChroma;
++	//double   DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
++
++	for (k = 0; k < NumberOfActivePlanes; ++k) {
++		if (VRatio[k] <= 1) {
++			DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerPlane[k]
++					/ HRatio[k] / PixelClock[k];
++		} else {
++			DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k]
++					/ DPPCLK[k];
++		}
++		if (BytePerPixelDETC[k] == 0) {
++			DisplayPipeLineDeliveryTimeChroma = 0;
++		} else {
++			if (VRatio[k] / 2 <= 1) {
++				DisplayPipeLineDeliveryTimeChroma = SwathWidthY[k] / 2.0
++						* DPPPerPlane[k] / (HRatio[k] / 2) / PixelClock[k];
++			} else {
++				DisplayPipeLineDeliveryTimeChroma = SwathWidthY[k] / 2.0
++						/ PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
++			}
++		}
++
++		if (BytePerPixelDETC[k] > 0) {
++			mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(
++					1.1 * SwathWidthY[k] * dml_ceil(BytePerPixelDETY[k], 1)
++							/ 32.0 / DisplayPipeLineDeliveryTimeLuma,
++					1.1 * SwathWidthY[k] / 2.0
++							* dml_ceil(BytePerPixelDETC[k], 2) / 32.0
++							/ DisplayPipeLineDeliveryTimeChroma);
++		} else {
++			mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = 1.1 * SwathWidthY[k]
++					* dml_ceil(BytePerPixelDETY[k], 1) / 64.0
++					/ DisplayPipeLineDeliveryTimeLuma;
++		}
++		mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(
++				mode_lib->vba.DCFCLKDeepSleepPerPlane[k],
++				PixelClock[k] / 16);
++
++	}
++
++	*DCFCLKDeepSleep = 8;
++	for (k = 0; k < NumberOfActivePlanes; ++k) {
++		*DCFCLKDeepSleep = dml_max(
++				*DCFCLKDeepSleep,
++				mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
++	}
++}
++
++static void CalculateDETBufferSize(
++		double DETBufferSizeInKByte,
++		unsigned int SwathHeightY,
++		unsigned int SwathHeightC,
++		double *DETBufferSizeY,
++		double *DETBufferSizeC)
++{
++	if (SwathHeightC == 0) {
++		*DETBufferSizeY = DETBufferSizeInKByte * 1024;
++		*DETBufferSizeC = 0;
++	} else if (SwathHeightY <= SwathHeightC) {
++		*DETBufferSizeY = DETBufferSizeInKByte * 1024 / 2;
++		*DETBufferSizeC = DETBufferSizeInKByte * 1024 / 2;
++	} else {
++		*DETBufferSizeY = DETBufferSizeInKByte * 1024 * 2 / 3;
++		*DETBufferSizeC = DETBufferSizeInKByte * 1024 / 3;
++	}
++}
++
++static void CalculateUrgentBurstFactor(
++		unsigned int DETBufferSizeInKByte,
++		unsigned int SwathHeightY,
++		unsigned int SwathHeightC,
++		unsigned int SwathWidthY,
++		double LineTime,
++		double UrgentLatency,
++		double CursorBufferSize,
++		unsigned int CursorWidth,
++		unsigned int CursorBPP,
++		double VRatio,
++		double VRatioPreY,
++		double VRatioPreC,
++		double BytePerPixelInDETY,
++		double BytePerPixelInDETC,
++		double *UrgentBurstFactorCursor,
++		double *UrgentBurstFactorCursorPre,
++		double *UrgentBurstFactorLuma,
++		double *UrgentBurstFactorLumaPre,
++		double *UrgentBurstFactorChroma,
++		double *UrgentBurstFactorChromaPre,
++		unsigned int *NotEnoughUrgentLatencyHiding,
++		unsigned int *NotEnoughUrgentLatencyHidingPre)
++{
++	double LinesInDETLuma;
++	double LinesInDETChroma;
++	unsigned int LinesInCursorBuffer;
++	double CursorBufferSizeInTime;
++	double CursorBufferSizeInTimePre;
++	double DETBufferSizeInTimeLuma;
++	double DETBufferSizeInTimeLumaPre;
++	double DETBufferSizeInTimeChroma;
++	double DETBufferSizeInTimeChromaPre;
++	double DETBufferSizeY;
++	double DETBufferSizeC;
++
++	*NotEnoughUrgentLatencyHiding = 0;
++	*NotEnoughUrgentLatencyHidingPre = 0;
++
++	if (CursorWidth > 0) {
++		LinesInCursorBuffer = 1 << (unsigned int) dml_floor(
++			dml_log2(CursorBufferSize * 1024.0 / (CursorWidth * CursorBPP / 8.0)), 1.0);
++		CursorBufferSizeInTime = LinesInCursorBuffer * LineTime / VRatio;
++		if (CursorBufferSizeInTime - UrgentLatency <= 0) {
++			*NotEnoughUrgentLatencyHiding = 1;
++			*UrgentBurstFactorCursor = 0;
++		} else {
++			*UrgentBurstFactorCursor = CursorBufferSizeInTime
++					/ (CursorBufferSizeInTime - UrgentLatency);
++		}
++		if (VRatioPreY > 0) {
++			CursorBufferSizeInTimePre = LinesInCursorBuffer * LineTime / VRatioPreY;
++			if (CursorBufferSizeInTimePre - UrgentLatency <= 0) {
++				*NotEnoughUrgentLatencyHidingPre = 1;
++				*UrgentBurstFactorCursorPre = 0;
++			} else {
++				*UrgentBurstFactorCursorPre = CursorBufferSizeInTimePre
++						/ (CursorBufferSizeInTimePre - UrgentLatency);
++			}
++		} else {
++			*UrgentBurstFactorCursorPre = 1;
++		}
++	}
++
++	CalculateDETBufferSize(
++			DETBufferSizeInKByte,
++			SwathHeightY,
++			SwathHeightC,
++			&DETBufferSizeY,
++			&DETBufferSizeC);
++
++	LinesInDETLuma = DETBufferSizeY / BytePerPixelInDETY / SwathWidthY;
++	DETBufferSizeInTimeLuma = dml_floor(LinesInDETLuma, SwathHeightY) * LineTime / VRatio;
++	if (DETBufferSizeInTimeLuma - UrgentLatency <= 0) {
++		*NotEnoughUrgentLatencyHiding = 1;
++		*UrgentBurstFactorLuma = 0;
++	} else {
++		*UrgentBurstFactorLuma = DETBufferSizeInTimeLuma
++				/ (DETBufferSizeInTimeLuma - UrgentLatency);
++	}
++	if (VRatioPreY > 0) {
++		DETBufferSizeInTimeLumaPre = dml_floor(LinesInDETLuma, SwathHeightY) * LineTime
++				/ VRatioPreY;
++		if (DETBufferSizeInTimeLumaPre - UrgentLatency <= 0) {
++			*NotEnoughUrgentLatencyHidingPre = 1;
++			*UrgentBurstFactorLumaPre = 0;
++		} else {
++			*UrgentBurstFactorLumaPre = DETBufferSizeInTimeLumaPre
++					/ (DETBufferSizeInTimeLumaPre - UrgentLatency);
++		}
++	} else {
++		*UrgentBurstFactorLumaPre = 1;
++	}
++
++	if (BytePerPixelInDETC > 0) {
++		LinesInDETChroma = DETBufferSizeC / BytePerPixelInDETC / (SwathWidthY / 2);
++		DETBufferSizeInTimeChroma = dml_floor(LinesInDETChroma, SwathHeightC) * LineTime
++				/ (VRatio / 2);
++		if (DETBufferSizeInTimeChroma - UrgentLatency <= 0) {
++			*NotEnoughUrgentLatencyHiding = 1;
++			*UrgentBurstFactorChroma = 0;
++		} else {
++			*UrgentBurstFactorChroma = DETBufferSizeInTimeChroma
++					/ (DETBufferSizeInTimeChroma - UrgentLatency);
++		}
++		if (VRatioPreC > 0) {
++			DETBufferSizeInTimeChromaPre = dml_floor(LinesInDETChroma, SwathHeightC)
++					* LineTime / VRatioPreC;
++			if (DETBufferSizeInTimeChromaPre - UrgentLatency <= 0) {
++				*NotEnoughUrgentLatencyHidingPre = 1;
++				*UrgentBurstFactorChromaPre = 0;
++			} else {
++				*UrgentBurstFactorChromaPre = DETBufferSizeInTimeChromaPre
++						/ (DETBufferSizeInTimeChromaPre - UrgentLatency);
++			}
++		} else {
++			*UrgentBurstFactorChromaPre = 1;
++		}
++	}
++}
++
++static void CalculatePixelDeliveryTimes(
++		unsigned int NumberOfActivePlanes,
++		double VRatio[],
++		double VRatioPrefetchY[],
++		double VRatioPrefetchC[],
++		unsigned int swath_width_luma_ub[],
++		unsigned int swath_width_chroma_ub[],
++		int DPPPerPlane[],
++		double HRatio[],
++		double PixelClock[],
++		double PSCL_THROUGHPUT[],
++		double PSCL_THROUGHPUT_CHROMA[],
++		double DPPCLK[],
++		double BytePerPixelDETC[],
++		enum scan_direction_class SourceScan[],
++		unsigned int BlockWidth256BytesY[],
++		unsigned int BlockHeight256BytesY[],
++		unsigned int BlockWidth256BytesC[],
++		unsigned int BlockHeight256BytesC[],
++		double DisplayPipeLineDeliveryTimeLuma[],
++		double DisplayPipeLineDeliveryTimeChroma[],
++		double DisplayPipeLineDeliveryTimeLumaPrefetch[],
++		double DisplayPipeLineDeliveryTimeChromaPrefetch[],
++		double DisplayPipeRequestDeliveryTimeLuma[],
++		double DisplayPipeRequestDeliveryTimeChroma[],
++		double DisplayPipeRequestDeliveryTimeLumaPrefetch[],
++		double DisplayPipeRequestDeliveryTimeChromaPrefetch[])
++{
++	double req_per_swath_ub;
++	uint k;
++
++	for (k = 0; k < NumberOfActivePlanes; ++k) {
++		if (VRatio[k] <= 1) {
++			DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * DPPPerPlane[k]
++					/ HRatio[k] / PixelClock[k];
++		} else {
++			DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k]
++					/ PSCL_THROUGHPUT[k] / DPPCLK[k];
++		}
++
++		if (BytePerPixelDETC[k] == 0) {
++			DisplayPipeLineDeliveryTimeChroma[k] = 0;
++		} else {
++			if (VRatio[k] / 2 <= 1) {
++				DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k]
++						* DPPPerPlane[k] / (HRatio[k] / 2) / PixelClock[k];
++			} else {
++				DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k]
++						/ PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
++			}
++		}
++
++		if (VRatioPrefetchY[k] <= 1) {
++			DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k]
++					* DPPPerPlane[k] / HRatio[k] / PixelClock[k];
++		} else {
++			DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k]
++					/ PSCL_THROUGHPUT[k] / DPPCLK[k];
++		}
++
++		if (BytePerPixelDETC[k] == 0) {
++			DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
++		} else {
++			if (VRatioPrefetchC[k] <= 1) {
++				DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
++						swath_width_chroma_ub[k] * DPPPerPlane[k]
++								/ (HRatio[k] / 2) / PixelClock[k];
++			} else {
++				DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
++						swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
++			}
++		}
++	}
++
++	for (k = 0; k < NumberOfActivePlanes; ++k) {
++		if (SourceScan[k] == dm_horz) {
++			req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k];
++		} else {
++			req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k];
++		}
++		DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k]
++				/ req_per_swath_ub;
++		DisplayPipeRequestDeliveryTimeLumaPrefetch[k] =
++				DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub;
++		if (BytePerPixelDETC[k] == 0) {
++			DisplayPipeRequestDeliveryTimeChroma[k] = 0;
++			DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
++		} else {
++			if (SourceScan[k] == dm_horz) {
++				req_per_swath_ub = swath_width_chroma_ub[k]
++						/ BlockWidth256BytesC[k];
++			} else {
++				req_per_swath_ub = swath_width_chroma_ub[k]
++						/ BlockHeight256BytesC[k];
++			}
++			DisplayPipeRequestDeliveryTimeChroma[k] =
++					DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub;
++			DisplayPipeRequestDeliveryTimeChromaPrefetch[k] =
++					DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub;
++		}
++	}
++}
++
++static void CalculateMetaAndPTETimes(
++		unsigned int NumberOfActivePlanes,
++		bool GPUVMEnable,
++		unsigned int MetaChunkSize,
++		unsigned int MinMetaChunkSizeBytes,
++		unsigned int GPUVMMaxPageTableLevels,
++		unsigned int HTotal[],
++		double VRatio[],
++		double VRatioPrefetchY[],
++		double VRatioPrefetchC[],
++		double DestinationLinesToRequestRowInVBlank[],
++		double DestinationLinesToRequestRowInImmediateFlip[],
++		double DestinationLinesToRequestVMInVBlank[],
++		double DestinationLinesToRequestVMInImmediateFlip[],
++		bool DCCEnable[],
++		double PixelClock[],
++		double BytePerPixelDETY[],
++		double BytePerPixelDETC[],
++		enum scan_direction_class SourceScan[],
++		unsigned int dpte_row_height[],
++		unsigned int dpte_row_height_chroma[],
++		unsigned int meta_row_width[],
++		unsigned int meta_row_height[],
++		unsigned int meta_req_width[],
++		unsigned int meta_req_height[],
++		long dpte_group_bytes[],
++		unsigned int PTERequestSizeY[],
++		unsigned int PTERequestSizeC[],
++		unsigned int PixelPTEReqWidthY[],
++		unsigned int PixelPTEReqHeightY[],
++		unsigned int PixelPTEReqWidthC[],
++		unsigned int PixelPTEReqHeightC[],
++		unsigned int dpte_row_width_luma_ub[],
++		unsigned int dpte_row_width_chroma_ub[],
++		unsigned int vm_group_bytes[],
++		unsigned int dpde0_bytes_per_frame_ub_l[],
++		unsigned int dpde0_bytes_per_frame_ub_c[],
++		unsigned int meta_pte_bytes_per_frame_ub_l[],
++		unsigned int meta_pte_bytes_per_frame_ub_c[],
++		double DST_Y_PER_PTE_ROW_NOM_L[],
++		double DST_Y_PER_PTE_ROW_NOM_C[],
++		double DST_Y_PER_META_ROW_NOM_L[],
++		double TimePerMetaChunkNominal[],
++		double TimePerMetaChunkVBlank[],
++		double TimePerMetaChunkFlip[],
++		double time_per_pte_group_nom_luma[],
++		double time_per_pte_group_vblank_luma[],
++		double time_per_pte_group_flip_luma[],
++		double time_per_pte_group_nom_chroma[],
++		double time_per_pte_group_vblank_chroma[],
++		double time_per_pte_group_flip_chroma[],
++		double TimePerVMGroupVBlank[],
++		double TimePerVMGroupFlip[],
++		double TimePerVMRequestVBlank[],
++		double TimePerVMRequestFlip[])
++{
++	unsigned int meta_chunk_width;
++	unsigned int min_meta_chunk_width;
++	unsigned int meta_chunk_per_row_int;
++	unsigned int meta_row_remainder;
++	unsigned int meta_chunk_threshold;
++	unsigned int meta_chunks_per_row_ub;
++	unsigned int dpte_group_width_luma;
++	unsigned int dpte_group_width_chroma;
++	unsigned int dpte_groups_per_row_luma_ub;
++	unsigned int dpte_groups_per_row_chroma_ub;
++	unsigned int num_group_per_lower_vm_stage;
++	unsigned int num_req_per_lower_vm_stage;
++	uint k;
++
++	for (k = 0; k < NumberOfActivePlanes; ++k) {
++		if (GPUVMEnable == true) {
++			DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
++			if (BytePerPixelDETC[k] == 0) {
++				DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
++			} else {
++				DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / (VRatio[k] / 2);
++			}
++		} else {
++			DST_Y_PER_PTE_ROW_NOM_L[k] = 0;
++			DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
++		}
++		if (DCCEnable[k] == true) {
++			DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k];
++		} else {
++			DST_Y_PER_META_ROW_NOM_L[k] = 0;
++		}
++	}
++
++	for (k = 0; k < NumberOfActivePlanes; ++k) {
++		if (DCCEnable[k] == true) {
++			meta_chunk_width = MetaChunkSize * 1024 * 256
++					/ dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k];
++			min_meta_chunk_width = MinMetaChunkSizeBytes * 256
++					/ dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k];
++			meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width;
++			meta_row_remainder = meta_row_width[k] % meta_chunk_width;
++			if (SourceScan[k] == dm_horz) {
++				meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
++			} else {
++				meta_chunk_threshold = 2 * min_meta_chunk_width
++						- meta_req_height[k];
++			}
++			if (meta_row_remainder <= meta_chunk_threshold) {
++				meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
++			} else {
++				meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
++			}
++			TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] * HTotal[k]
++					/ PixelClock[k] / meta_chunks_per_row_ub;
++			TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k]
++					* HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
++			TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k]
++					* HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
++		} else {
++			TimePerMetaChunkNominal[k] = 0;
++			TimePerMetaChunkVBlank[k] = 0;
++			TimePerMetaChunkFlip[k] = 0;
++		}
++	}
++
++	for (k = 0; k < NumberOfActivePlanes; ++k) {
++		if (GPUVMEnable == true) {
++			if (SourceScan[k] == dm_horz) {
++				dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k]
++						* PixelPTEReqWidthY[k];
++			} else {
++				dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k]
++						* PixelPTEReqHeightY[k];
++			}
++			dpte_groups_per_row_luma_ub = dml_ceil(
++					dpte_row_width_luma_ub[k] / dpte_group_width_luma,
++					1);
++			time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k]
++					/ PixelClock[k] / dpte_groups_per_row_luma_ub;
++			time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k]
++					* HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
++			time_per_pte_group_flip_luma[k] =
++					DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k]
++							/ PixelClock[k]
++							/ dpte_groups_per_row_luma_ub;
++			if (BytePerPixelDETC[k] == 0) {
++				time_per_pte_group_nom_chroma[k] = 0;
++				time_per_pte_group_vblank_chroma[k] = 0;
++				time_per_pte_group_flip_chroma[k] = 0;
++			} else {
++				if (SourceScan[k] == dm_horz) {
++					dpte_group_width_chroma = dpte_group_bytes[k]
++							/ PTERequestSizeC[k] * PixelPTEReqWidthC[k];
++				} else {
++					dpte_group_width_chroma = dpte_group_bytes[k]
++							/ PTERequestSizeC[k]
++							* PixelPTEReqHeightC[k];
++				}
++				dpte_groups_per_row_chroma_ub = dml_ceil(
++						dpte_row_width_chroma_ub[k]
++								/ dpte_group_width_chroma,
++						1);
++				time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k]
++						* HTotal[k] / PixelClock[k]
++						/ dpte_groups_per_row_chroma_ub;
++				time_per_pte_group_vblank_chroma[k] =
++						DestinationLinesToRequestRowInVBlank[k] * HTotal[k]
++								/ PixelClock[k]
++								/ dpte_groups_per_row_chroma_ub;
++				time_per_pte_group_flip_chroma[k] =
++						DestinationLinesToRequestRowInImmediateFlip[k]
++								* HTotal[k] / PixelClock[k]
++								/ dpte_groups_per_row_chroma_ub;
++			}
++		} else {
++			time_per_pte_group_nom_luma[k] = 0;
++			time_per_pte_group_vblank_luma[k] = 0;
++			time_per_pte_group_flip_luma[k] = 0;
++			time_per_pte_group_nom_chroma[k] = 0;
++			time_per_pte_group_vblank_chroma[k] = 0;
++			time_per_pte_group_flip_chroma[k] = 0;
++		}
++	}
++
++	for (k = 0; k < NumberOfActivePlanes; ++k) {
++		if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
++			if (DCCEnable[k] == false) {
++				if (BytePerPixelDETC[k] > 0) {
++					num_group_per_lower_vm_stage =
++						dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
++						+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
++				} else {
++					num_group_per_lower_vm_stage =
++							dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
++				}
++			} else {
++				if (GPUVMMaxPageTableLevels == 1) {
++					if (BytePerPixelDETC[k] > 0) {
++						num_group_per_lower_vm_stage =
++							dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
++							+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
++					} else {
++						num_group_per_lower_vm_stage =
++							dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
++					}
++				} else {
++					if (BytePerPixelDETC[k] > 0) {
++						num_group_per_lower_vm_stage =
++							dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
++							+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)
++							+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
++							+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
++					} else {
++						num_group_per_lower_vm_stage =
++							dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
++							+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
++					}
++				}
++			}
++
++			if (DCCEnable[k] == false) {
++				if (BytePerPixelDETC[k] > 0) {
++					num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k]
++							/ 64 + dpde0_bytes_per_frame_ub_c[k] / 64;
++				} else {
++					num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k]
++							/ 64;
++				}
++			} else {
++				if (GPUVMMaxPageTableLevels == 1) {
++					if (BytePerPixelDETC[k] > 0) {
++						num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64
++							+ meta_pte_bytes_per_frame_ub_c[k] / 64;
++					} else {
++						num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64;
++					}
++				} else {
++					if (BytePerPixelDETC[k] > 0) {
++						num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64
++							+ dpde0_bytes_per_frame_ub_c[k] / 64
++							+ meta_pte_bytes_per_frame_ub_l[k] / 64
++							+ meta_pte_bytes_per_frame_ub_c[k] / 64;
++					} else {
++						num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64
++							+ meta_pte_bytes_per_frame_ub_l[k] / 64;
++					}
++				}
++			}
++
++			TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k]
++					/ PixelClock[k] / num_group_per_lower_vm_stage;
++			TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k]
++					* HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
++			TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k]
++					* HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
++			TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k]
++					* HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
++
++			if (GPUVMMaxPageTableLevels > 2) {
++				TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;
++				TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;
++				TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;
++				TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;
++			}
++
++		} else {
++			TimePerVMGroupVBlank[k] = 0;
++			TimePerVMGroupFlip[k] = 0;
++			TimePerVMRequestVBlank[k] = 0;
++			TimePerVMRequestFlip[k] = 0;
++		}
++	}
++}
++
++static double CalculateExtraLatency(
++		double UrgentRoundTripAndOutOfOrderLatency,
++		int TotalNumberOfActiveDPP,
++		int PixelChunkSizeInKByte,
++		int TotalNumberOfDCCActiveDPP,
++		int MetaChunkSize,
++		double ReturnBW,
++		bool GPUVMEnable,
++		bool HostVMEnable,
++		int NumberOfActivePlanes,
++		int NumberOfDPP[],
++		long dpte_group_bytes[],
++		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
++		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
++		int HostVMMaxPageTableLevels,
++		int HostVMCachedPageTableLevels)
++{
++	double CalculateExtraLatency;
++	double HostVMInefficiencyFactor;
++	int HostVMDynamicLevels;
++
++	if (GPUVMEnable && HostVMEnable) {
++		HostVMInefficiencyFactor =
++				PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData
++						/ PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly;
++		HostVMDynamicLevels = HostVMMaxPageTableLevels - HostVMCachedPageTableLevels;
++	} else {
++		HostVMInefficiencyFactor = 1;
++		HostVMDynamicLevels = 0;
++	}
++
++	CalculateExtraLatency = UrgentRoundTripAndOutOfOrderLatency
++			+ (TotalNumberOfActiveDPP * PixelChunkSizeInKByte
++					+ TotalNumberOfDCCActiveDPP * MetaChunkSize) * 1024.0
++					/ ReturnBW;
++
++	if (GPUVMEnable) {
++		int k;
++
++		for (k = 0; k < NumberOfActivePlanes; k++) {
++			CalculateExtraLatency = CalculateExtraLatency
++					+ NumberOfDPP[k] * dpte_group_bytes[k]
++							* (1 + 8 * HostVMDynamicLevels)
++							* HostVMInefficiencyFactor / ReturnBW;
++		}
++	}
++	return CalculateExtraLatency;
++}
++
++#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.h b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.h
+new file mode 100644
+index 000000000000..fb9548a2f894
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.h
+@@ -0,0 +1,32 @@
++/*
++ * Copyright 2017 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DML21_DISPLAY_MODE_VBA_H__
++#define __DML21_DISPLAY_MODE_VBA_H__
++
++void dml21_recalculate(struct display_mode_lib *mode_lib);
++void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);
++
++#endif /* _DML21_DISPLAY_MODE_VBA_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+new file mode 100644
+index 000000000000..a1f207cbb966
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+@@ -0,0 +1,1823 @@
++/*
++ * Copyright 2017 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifdef CONFIG_DRM_AMD_DC_DCN2_0
++
++#include "../display_mode_lib.h"
++#include "../display_mode_vba.h"
++#include "../dml_inline_defs.h"
++#include "display_rq_dlg_calc_21.h"
++
++/*
++ * NOTE:
++ *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
++ *
++ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
++ * ways. Unless there is something clearly wrong with it the code should
++ * remain as-is as it provides us with a guarantee from HW that it is correct.
++ */
++
++static void calculate_ttu_cursor(
++		struct display_mode_lib *mode_lib,
++		double *refcyc_per_req_delivery_pre_cur,
++		double *refcyc_per_req_delivery_cur,
++		double refclk_freq_in_mhz,
++		double ref_freq_to_pix_freq,
++		double hscale_pixel_rate_l,
++		double hscl_ratio,
++		double vratio_pre_l,
++		double vratio_l,
++		unsigned int cur_width,
++		enum cursor_bpp cur_bpp);
++
++static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)
++{
++	unsigned int ret_val = 0;
++
++	if (source_format == dm_444_16) {
++		if (!is_chroma)
++			ret_val = 2;
++	} else if (source_format == dm_444_32) {
++		if (!is_chroma)
++			ret_val = 4;
++	} else if (source_format == dm_444_64) {
++		if (!is_chroma)
++			ret_val = 8;
++	} else if (source_format == dm_420_8) {
++		if (is_chroma)
++			ret_val = 2;
++		else
++			ret_val = 1;
++	} else if (source_format == dm_420_10) {
++		if (is_chroma)
++			ret_val = 4;
++		else
++			ret_val = 2;
++	} else if (source_format == dm_444_8) {
++		ret_val = 1;
++	}
++	return ret_val;
++}
++
++static bool is_dual_plane(enum source_format_class source_format)
++{
++	bool ret_val = 0;
++
++	if ((source_format == dm_420_8) || (source_format == dm_420_10))
++		ret_val = 1;
++
++	return ret_val;
++}
++
++static double get_refcyc_per_delivery(
++		struct display_mode_lib *mode_lib,
++		double refclk_freq_in_mhz,
++		double pclk_freq_in_mhz,
++		bool odm_combine,
++		unsigned int recout_width,
++		unsigned int hactive,
++		double vratio,
++		double hscale_pixel_rate,
++		unsigned int delivery_width,
++		unsigned int req_per_swath_ub)
++{
++	double refcyc_per_delivery = 0.0;
++
++	if (vratio <= 1.0) {
++		if (odm_combine)
++			refcyc_per_delivery = (double) refclk_freq_in_mhz
++					* dml_min((double) recout_width, (double) hactive / 2.0)
++					/ pclk_freq_in_mhz / (double) req_per_swath_ub;
++		else
++			refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width
++					/ pclk_freq_in_mhz / (double) req_per_swath_ub;
++	} else {
++		refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width
++				/ (double) hscale_pixel_rate / (double) req_per_swath_ub;
++	}
++
++	dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz);
++	dml_print("DML_DLG: %s: pclk_freq_in_mhz   = %3.2f\n", __func__, pclk_freq_in_mhz);
++	dml_print("DML_DLG: %s: recout_width       = %d\n", __func__, recout_width);
++	dml_print("DML_DLG: %s: vratio             = %3.2f\n", __func__, vratio);
++	dml_print("DML_DLG: %s: req_per_swath_ub   = %d\n", __func__, req_per_swath_ub);
++	dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery);
++
++	return refcyc_per_delivery;
++
++}
++
++static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size)
++{
++	if (tile_size == dm_256k_tile)
++		return (256 * 1024);
++	else if (tile_size == dm_64k_tile)
++		return (64 * 1024);
++	else
++		return (4 * 1024);
++}
++
++static void extract_rq_sizing_regs(
++		struct display_mode_lib *mode_lib,
++		display_data_rq_regs_st *rq_regs,
++		const display_data_rq_sizing_params_st rq_sizing)
++{
++	dml_print("DML_DLG: %s: rq_sizing param\n", __func__);
++	print__data_rq_sizing_params_st(mode_lib, rq_sizing);
++
++	rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;
++
++	if (rq_sizing.min_chunk_bytes == 0)
++		rq_regs->min_chunk_size = 0;
++	else
++		rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
++
++	rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
++	if (rq_sizing.min_meta_chunk_bytes == 0)
++		rq_regs->min_meta_chunk_size = 0;
++	else
++		rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;
++
++	rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;
++	rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;
++}
++
++static void extract_rq_regs(
++		struct display_mode_lib *mode_lib,
++		display_rq_regs_st *rq_regs,
++		const display_rq_params_st rq_param)
++{
++	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
++	unsigned int detile_buf_plane1_addr = 0;
++
++	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
++
++	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(
++			dml_log2(rq_param.dlg.rq_l.dpte_row_height),
++			1) - 3;
++
++	if (rq_param.yuv420) {
++		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);
++		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(
++				dml_log2(rq_param.dlg.rq_c.dpte_row_height),
++				1) - 3;
++	}
++
++	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
++	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
++
++	// FIXME: take the max between luma, chroma chunk size?
++	// okay for now, as we are setting chunk_bytes to 8kb anyways
++	if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb
++		rq_regs->drq_expansion_mode = 0;
++	} else {
++		rq_regs->drq_expansion_mode = 2;
++	}
++	rq_regs->prq_expansion_mode = 1;
++	rq_regs->mrq_expansion_mode = 1;
++	rq_regs->crq_expansion_mode = 1;
++
++	if (rq_param.yuv420) {
++		if ((double) rq_param.misc.rq_l.stored_swath_bytes
++				/ (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) {
++			detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma
++		} else {
++			detile_buf_plane1_addr = dml_round_to_multiple(
++					(unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0),
++					256,
++					0) / 64.0; // 2/3 to chroma
++		}
++	}
++	rq_regs->plane1_base_address = detile_buf_plane1_addr;
++}
++
++static void handle_det_buf_split(
++		struct display_mode_lib *mode_lib,
++		display_rq_params_st *rq_param,
++		const display_pipe_source_params_st pipe_src_param)
++{
++	unsigned int total_swath_bytes = 0;
++	unsigned int swath_bytes_l = 0;
++	unsigned int swath_bytes_c = 0;
++	unsigned int full_swath_bytes_packed_l = 0;
++	unsigned int full_swath_bytes_packed_c = 0;
++	bool req128_l = 0;
++	bool req128_c = 0;
++	bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
++	bool surf_vert = (pipe_src_param.source_scan == dm_vert);
++	unsigned int log2_swath_height_l = 0;
++	unsigned int log2_swath_height_c = 0;
++	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
++
++	full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes;
++	full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes;
++
++	if (rq_param->yuv420_10bpc) {
++		full_swath_bytes_packed_l = dml_round_to_multiple(
++				rq_param->misc.rq_l.full_swath_bytes * 2 / 3,
++				256,
++				1) + 256;
++		full_swath_bytes_packed_c = dml_round_to_multiple(
++				rq_param->misc.rq_c.full_swath_bytes * 2 / 3,
++				256,
++				1) + 256;
++	}
++
++	if (rq_param->yuv420) {
++		total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c;
++
++		if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request
++			req128_l = 0;
++			req128_c = 0;
++			swath_bytes_l = full_swath_bytes_packed_l;
++			swath_bytes_c = full_swath_bytes_packed_c;
++		} else { //128b request (for luma only for yuv420 8bpc)
++			req128_l = 1;
++			req128_c = 0;
++			swath_bytes_l = full_swath_bytes_packed_l / 2;
++			swath_bytes_c = full_swath_bytes_packed_c;
++		}
++		// Note: assumption, the config that pass in will fit into
++		//       the detiled buffer.
++	} else {
++		total_swath_bytes = 2 * full_swath_bytes_packed_l;
++
++		if (total_swath_bytes <= detile_buf_size_in_bytes)
++			req128_l = 0;
++		else
++			req128_l = 1;
++
++		swath_bytes_l = total_swath_bytes;
++		swath_bytes_c = 0;
++	}
++	rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l;
++	rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c;
++
++	if (surf_linear) {
++		log2_swath_height_l = 0;
++		log2_swath_height_c = 0;
++	} else if (!surf_vert) {
++		log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l;
++		log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c;
++	} else {
++		log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l;
++		log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c;
++	}
++	rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
++	rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
++
++	dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l);
++	dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c);
++	dml_print(
++			"DML_DLG: %s: full_swath_bytes_packed_l = %0d\n",
++			__func__,
++			full_swath_bytes_packed_l);
++	dml_print(
++			"DML_DLG: %s: full_swath_bytes_packed_c = %0d\n",
++			__func__,
++			full_swath_bytes_packed_c);
++}
++
++static void get_meta_and_pte_attr(
++		struct display_mode_lib *mode_lib,
++		display_data_rq_dlg_params_st *rq_dlg_param,
++		display_data_rq_misc_params_st *rq_misc_param,
++		display_data_rq_sizing_params_st *rq_sizing_param,
++		unsigned int vp_width,
++		unsigned int vp_height,
++		unsigned int data_pitch,
++		unsigned int meta_pitch,
++		unsigned int source_format,
++		unsigned int tiling,
++		unsigned int macro_tile_size,
++		unsigned int source_scan,
++		unsigned int hostvm_enable,
++		unsigned int is_chroma)
++{
++	bool surf_linear = (tiling == dm_sw_linear);
++	bool surf_vert = (source_scan == dm_vert);
++
++	unsigned int bytes_per_element;
++	unsigned int bytes_per_element_y = get_bytes_per_element(
++			(enum source_format_class) (source_format),
++			false);
++	unsigned int bytes_per_element_c = get_bytes_per_element(
++			(enum source_format_class) (source_format),
++			true);
++
++	unsigned int blk256_width = 0;
++	unsigned int blk256_height = 0;
++
++	unsigned int blk256_width_y = 0;
++	unsigned int blk256_height_y = 0;
++	unsigned int blk256_width_c = 0;
++	unsigned int blk256_height_c = 0;
++	unsigned int log2_bytes_per_element;
++	unsigned int log2_blk256_width;
++	unsigned int log2_blk256_height;
++	unsigned int blk_bytes;
++	unsigned int log2_blk_bytes;
++	unsigned int log2_blk_height;
++	unsigned int log2_blk_width;
++	unsigned int log2_meta_req_bytes;
++	unsigned int log2_meta_req_height;
++	unsigned int log2_meta_req_width;
++	unsigned int meta_req_width;
++	unsigned int meta_req_height;
++	unsigned int log2_meta_row_height;
++	unsigned int meta_row_width_ub;
++	unsigned int log2_meta_chunk_bytes;
++	unsigned int log2_meta_chunk_height;
++
++	//full sized meta chunk width in unit of data elements
++	unsigned int log2_meta_chunk_width;
++	unsigned int log2_min_meta_chunk_bytes;
++	unsigned int min_meta_chunk_width;
++	unsigned int meta_chunk_width;
++	unsigned int meta_chunk_per_row_int;
++	unsigned int meta_row_remainder;
++	unsigned int meta_chunk_threshold;
++	unsigned int meta_blk_bytes;
++	unsigned int meta_blk_height;
++	unsigned int meta_blk_width;
++	unsigned int meta_surface_bytes;
++	unsigned int vmpg_bytes;
++	unsigned int meta_pte_req_per_frame_ub;
++	unsigned int meta_pte_bytes_per_frame_ub;
++	const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
++	const unsigned int dpte_buf_in_pte_reqs =
++		mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma + mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma;
++	const unsigned int pde_proc_buffer_size_64k_reqs =
++			mode_lib->ip.pde_proc_buffer_size_64k_reqs;
++
++	unsigned int log2_vmpg_height = 0;
++	unsigned int log2_vmpg_width = 0;
++	unsigned int log2_dpte_req_height_ptes = 0;
++	unsigned int log2_dpte_req_height = 0;
++	unsigned int log2_dpte_req_width = 0;
++	unsigned int log2_dpte_row_height_linear = 0;
++	unsigned int log2_dpte_row_height = 0;
++	unsigned int log2_dpte_group_width = 0;
++	unsigned int dpte_row_width_ub = 0;
++	unsigned int dpte_req_height = 0;
++	unsigned int dpte_req_width = 0;
++	unsigned int dpte_group_width = 0;
++	unsigned int log2_dpte_group_bytes = 0;
++	unsigned int log2_dpte_group_length = 0;
++	unsigned int pde_buf_entries;
++	bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10);
++
++	Calculate256BBlockSizes(
++			(enum source_format_class) (source_format),
++			(enum dm_swizzle_mode) (tiling),
++			bytes_per_element_y,
++			bytes_per_element_c,
++			&blk256_height_y,
++			&blk256_height_c,
++			&blk256_width_y,
++			&blk256_width_c);
++
++	if (!is_chroma) {
++		blk256_width = blk256_width_y;
++		blk256_height = blk256_height_y;
++		bytes_per_element = bytes_per_element_y;
++	} else {
++		blk256_width = blk256_width_c;
++		blk256_height = blk256_height_c;
++		bytes_per_element = bytes_per_element_c;
++	}
++
++	log2_bytes_per_element = dml_log2(bytes_per_element);
++
++	dml_print("DML_DLG: %s: surf_linear        = %d\n", __func__, surf_linear);
++	dml_print("DML_DLG: %s: surf_vert          = %d\n", __func__, surf_vert);
++	dml_print("DML_DLG: %s: blk256_width       = %d\n", __func__, blk256_width);
++	dml_print("DML_DLG: %s: blk256_height      = %d\n", __func__, blk256_height);
++
++	log2_blk256_width = dml_log2((double) blk256_width);
++	log2_blk256_height = dml_log2((double) blk256_height);
++	blk_bytes = surf_linear ?
++			256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);
++	log2_blk_bytes = dml_log2((double) blk_bytes);
++	log2_blk_height = 0;
++	log2_blk_width = 0;
++
++	// remember log rule
++	// "+" in log is multiply
++	// "-" in log is divide
++	// "/2" is like square root
++	// blk is vertical biased
++	if (tiling != dm_sw_linear)
++		log2_blk_height = log2_blk256_height
++				+ dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
++	else
++		log2_blk_height = 0;  // blk height of 1
++
++	log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
++
++	if (!surf_vert) {
++		rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1)
++				+ blk256_width;
++		rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width;
++	} else {
++		rq_dlg_param->swath_width_ub = dml_round_to_multiple(
++				vp_height - 1,
++				blk256_height,
++				1) + blk256_height;
++		rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height;
++	}
++
++	if (!surf_vert)
++		rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height
++				* bytes_per_element;
++	else
++		rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width
++				* bytes_per_element;
++
++	rq_misc_param->blk256_height = blk256_height;
++	rq_misc_param->blk256_width = blk256_width;
++
++	// -------
++	// meta
++	// -------
++	log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element
++
++	// each 64b meta request for dcn is 8x8 meta elements and
++	// a meta element covers one 256b block of the the data surface.
++	log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256
++	log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element
++			- log2_meta_req_height;
++	meta_req_width = 1 << log2_meta_req_width;
++	meta_req_height = 1 << log2_meta_req_height;
++	log2_meta_row_height = 0;
++	meta_row_width_ub = 0;
++
++	// the dimensions of a meta row are meta_row_width x meta_row_height in elements.
++	// calculate upper bound of the meta_row_width
++	if (!surf_vert) {
++		log2_meta_row_height = log2_meta_req_height;
++		meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
++				+ meta_req_width;
++		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
++	} else {
++		log2_meta_row_height = log2_meta_req_width;
++		meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1)
++				+ meta_req_height;
++		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height;
++	}
++	rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64;
++
++	rq_dlg_param->meta_row_height = 1 << log2_meta_row_height;
++
++	log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes);
++	log2_meta_chunk_height = log2_meta_row_height;
++
++	//full sized meta chunk width in unit of data elements
++	log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element
++			- log2_meta_chunk_height;
++	log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes);
++	min_meta_chunk_width = 1
++			<< (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element
++					- log2_meta_chunk_height);
++	meta_chunk_width = 1 << log2_meta_chunk_width;
++	meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width);
++	meta_row_remainder = meta_row_width_ub % meta_chunk_width;
++	meta_chunk_threshold = 0;
++	meta_blk_bytes = 4096;
++	meta_blk_height = blk256_height * 64;
++	meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height;
++	meta_surface_bytes = meta_pitch
++			* (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1)
++					+ meta_blk_height) * bytes_per_element / 256;
++	vmpg_bytes = mode_lib->soc.vmm_page_size_bytes;
++	meta_pte_req_per_frame_ub = (dml_round_to_multiple(
++			meta_surface_bytes - vmpg_bytes,
++			8 * vmpg_bytes,
++			1) + 8 * vmpg_bytes) / (8 * vmpg_bytes);
++	meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request
++	rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub;
++
++	dml_print("DML_DLG: %s: meta_blk_height             = %d\n", __func__, meta_blk_height);
++	dml_print("DML_DLG: %s: meta_blk_width              = %d\n", __func__, meta_blk_width);
++	dml_print("DML_DLG: %s: meta_surface_bytes          = %d\n", __func__, meta_surface_bytes);
++	dml_print(
++			"DML_DLG: %s: meta_pte_req_per_frame_ub   = %d\n",
++			__func__,
++			meta_pte_req_per_frame_ub);
++	dml_print(
++			"DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n",
++			__func__,
++			meta_pte_bytes_per_frame_ub);
++
++	if (!surf_vert)
++		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
++	else
++		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
++
++	if (meta_row_remainder <= meta_chunk_threshold)
++		rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
++	else
++		rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
++
++	// ------
++	// dpte
++	// ------
++	if (surf_linear) {
++		log2_vmpg_height = 0;   // one line high
++	} else {
++		log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
++	}
++	log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
++
++	// only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4.
++	if (surf_linear) { //one 64B PTE request returns 8 PTEs
++		log2_dpte_req_height_ptes = 0;
++		log2_dpte_req_width = log2_vmpg_width + 3;
++		log2_dpte_req_height = 0;
++	} else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size
++					   //one 64B req gives 8x1 PTEs for 4KB tile
++		log2_dpte_req_height_ptes = 0;
++		log2_dpte_req_width = log2_blk_width + 3;
++		log2_dpte_req_height = log2_blk_height + 0;
++	} else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB
++									//two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB
++		log2_dpte_req_height_ptes = 4;
++		log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width
++		log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height
++	} else { //64KB page size and must 64KB tile block
++		 //one 64B req gives 8x1 PTEs for 64KB tile
++		log2_dpte_req_height_ptes = 0;
++		log2_dpte_req_width = log2_blk_width + 3;
++		log2_dpte_req_height = log2_blk_height + 0;
++	}
++
++	// The dpte request dimensions in data elements is dpte_req_width x dpte_req_height
++	// log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent
++	// That depends on the pte shape (i.e. 8x1, 4x2, 2x4)
++	//log2_dpte_req_height    = log2_vmpg_height + log2_dpte_req_height_ptes;
++	//log2_dpte_req_width     = log2_vmpg_width + log2_dpte_req_width_ptes;
++	dpte_req_height = 1 << log2_dpte_req_height;
++	dpte_req_width = 1 << log2_dpte_req_width;
++
++	// calculate pitch dpte row buffer can hold
++	// round the result down to a power of two.
++	pde_buf_entries =
++			yuv420 ? (pde_proc_buffer_size_64k_reqs >> 1) : pde_proc_buffer_size_64k_reqs;
++	if (surf_linear) {
++		unsigned int dpte_row_height;
++
++		log2_dpte_row_height_linear = dml_floor(
++				dml_log2(
++						dml_min(
++								64 * 1024 * pde_buf_entries
++										/ bytes_per_element,
++								dpte_buf_in_pte_reqs
++										* dpte_req_width)
++								/ data_pitch),
++				1);
++
++		ASSERT(log2_dpte_row_height_linear >= 3);
++
++		if (log2_dpte_row_height_linear > 7)
++			log2_dpte_row_height_linear = 7;
++
++		log2_dpte_row_height = log2_dpte_row_height_linear;
++		// For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary.
++		// the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
++		dpte_row_height = 1 << log2_dpte_row_height;
++		dpte_row_width_ub = dml_round_to_multiple(
++				data_pitch * dpte_row_height - 1,
++				dpte_req_width,
++				1) + dpte_req_width;
++		rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
++	} else {
++		// the upper bound of the dpte_row_width without dependency on viewport position follows.
++		// for tiled mode, row height is the same as req height and row store up to vp size upper bound
++		if (!surf_vert) {
++			log2_dpte_row_height = log2_dpte_req_height;
++			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
++					+ dpte_req_width;
++			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
++		} else {
++			log2_dpte_row_height =
++					(log2_blk_width < log2_dpte_req_width) ?
++							log2_blk_width : log2_dpte_req_width;
++			dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
++					+ dpte_req_height;
++			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
++		}
++	}
++	if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB
++		rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request
++	else
++		rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request
++
++	rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
++
++	// the dpte_group_bytes is reduced for the specific case of vertical
++	// access of a tile surface that has dpte request of 8x1 ptes.
++
++	if (hostvm_enable)
++		rq_sizing_param->dpte_group_bytes = 512;
++	else {
++		if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group
++			rq_sizing_param->dpte_group_bytes = 512;
++		else
++			//full size
++			rq_sizing_param->dpte_group_bytes = 2048;
++	}
++
++	//since pte request size is 64byte, the number of data pte requests per full sized group is as follows.
++	log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes);
++	log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests
++
++	// full sized data pte group width in elements
++	if (!surf_vert)
++		log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width;
++	else
++		log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height;
++
++	//But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B
++	if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB
++		log2_dpte_group_width = log2_dpte_group_width - 1;
++
++	dpte_group_width = 1 << log2_dpte_group_width;
++
++	// since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
++	// the upper bound for the dpte groups per row is as follows.
++	rq_dlg_param->dpte_groups_per_row_ub = dml_ceil(
++			(double) dpte_row_width_ub / dpte_group_width,
++			1);
++}
++
++static void get_surf_rq_param(
++		struct display_mode_lib *mode_lib,
++		display_data_rq_sizing_params_st *rq_sizing_param,
++		display_data_rq_dlg_params_st *rq_dlg_param,
++		display_data_rq_misc_params_st *rq_misc_param,
++		const display_pipe_params_st pipe_param,
++		bool is_chroma)
++{
++	bool mode_422 = 0;
++	unsigned int vp_width = 0;
++	unsigned int vp_height = 0;
++	unsigned int data_pitch = 0;
++	unsigned int meta_pitch = 0;
++	unsigned int ppe = mode_422 ? 2 : 1;
++
++	// FIXME check if ppe apply for both luma and chroma in 422 case
++	if (is_chroma) {
++		vp_width = pipe_param.src.viewport_width_c / ppe;
++		vp_height = pipe_param.src.viewport_height_c;
++		data_pitch = pipe_param.src.data_pitch_c;
++		meta_pitch = pipe_param.src.meta_pitch_c;
++	} else {
++		vp_width = pipe_param.src.viewport_width / ppe;
++		vp_height = pipe_param.src.viewport_height;
++		data_pitch = pipe_param.src.data_pitch;
++		meta_pitch = pipe_param.src.meta_pitch;
++	}
++
++	if (pipe_param.dest.odm_combine) {
++		unsigned int access_dir;
++		unsigned int full_src_vp_width;
++		unsigned int hactive_half;
++		unsigned int src_hactive_half;
++		access_dir = (pipe_param.src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
++		hactive_half  = pipe_param.dest.hactive / 2;
++		if (is_chroma) {
++			full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio_c * pipe_param.dest.full_recout_width;
++			src_hactive_half  = pipe_param.scale_ratio_depth.hscl_ratio_c * hactive_half;
++		} else {
++			full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio * pipe_param.dest.full_recout_width;
++			src_hactive_half  = pipe_param.scale_ratio_depth.hscl_ratio * hactive_half;
++		}
++
++		if (access_dir == 0) {
++			vp_width = dml_min(full_src_vp_width, src_hactive_half);
++			dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width);
++		} else {
++			vp_height = dml_min(full_src_vp_width, src_hactive_half);
++			dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height);
++
++		}
++		dml_print("DML_DLG: %s: full_src_vp_width = %d\n", __func__, full_src_vp_width);
++		dml_print("DML_DLG: %s: hactive_half = %d\n", __func__, hactive_half);
++		dml_print("DML_DLG: %s: src_hactive_half = %d\n", __func__, src_hactive_half);
++	}
++	rq_sizing_param->chunk_bytes = 8192;
++
++	if (rq_sizing_param->chunk_bytes == 64 * 1024)
++		rq_sizing_param->min_chunk_bytes = 0;
++	else
++		rq_sizing_param->min_chunk_bytes = 1024;
++
++	rq_sizing_param->meta_chunk_bytes = 2048;
++	rq_sizing_param->min_meta_chunk_bytes = 256;
++
++	if (pipe_param.src.hostvm)
++		rq_sizing_param->mpte_group_bytes = 512;
++	else
++		rq_sizing_param->mpte_group_bytes = 2048;
++
++	get_meta_and_pte_attr(
++			mode_lib,
++			rq_dlg_param,
++			rq_misc_param,
++			rq_sizing_param,
++			vp_width,
++			vp_height,
++			data_pitch,
++			meta_pitch,
++			pipe_param.src.source_format,
++			pipe_param.src.sw_mode,
++			pipe_param.src.macro_tile_size,
++			pipe_param.src.source_scan,
++			pipe_param.src.hostvm,
++			is_chroma);
++}
++
++static void dml_rq_dlg_get_rq_params(
++		struct display_mode_lib *mode_lib,
++		display_rq_params_st *rq_param,
++		const display_pipe_params_st pipe_param)
++{
++	// get param for luma surface
++	rq_param->yuv420 = pipe_param.src.source_format == dm_420_8
++			|| pipe_param.src.source_format == dm_420_10;
++	rq_param->yuv420_10bpc = pipe_param.src.source_format == dm_420_10;
++
++	get_surf_rq_param(
++			mode_lib,
++			&(rq_param->sizing.rq_l),
++			&(rq_param->dlg.rq_l),
++			&(rq_param->misc.rq_l),
++			pipe_param,
++			0);
++
++	if (is_dual_plane((enum source_format_class) (pipe_param.src.source_format))) {
++		// get param for chroma surface
++		get_surf_rq_param(
++				mode_lib,
++				&(rq_param->sizing.rq_c),
++				&(rq_param->dlg.rq_c),
++				&(rq_param->misc.rq_c),
++				pipe_param,
++				1);
++	}
++
++	// calculate how to split the det buffer space between luma and chroma
++	handle_det_buf_split(mode_lib, rq_param, pipe_param.src);
++	print__rq_params_st(mode_lib, *rq_param);
++}
++
++void dml21_rq_dlg_get_rq_reg(
++		struct display_mode_lib *mode_lib,
++		display_rq_regs_st *rq_regs,
++		const display_pipe_params_st pipe_param)
++{
++	display_rq_params_st rq_param = {0};
++
++	memset(rq_regs, 0, sizeof(*rq_regs));
++	dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param);
++	extract_rq_regs(mode_lib, rq_regs, rq_param);
++
++	print__rq_regs_st(mode_lib, *rq_regs);
++}
++
++// Note: currently taken in as is.
++// Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma.
++static void dml_rq_dlg_get_dlg_params(
++		struct display_mode_lib *mode_lib,
++		const display_e2e_pipe_params_st *e2e_pipe_param,
++		const unsigned int num_pipes,
++		const unsigned int pipe_idx,
++		display_dlg_regs_st *disp_dlg_regs,
++		display_ttu_regs_st *disp_ttu_regs,
++		const display_rq_dlg_params_st rq_dlg_param,
++		const display_dlg_sys_params_st dlg_sys_param,
++		const bool cstate_en,
++		const bool pstate_en)
++{
++	const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
++	const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
++	const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout;
++	const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
++	const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
++	const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;
++
++	// -------------------------
++	// Section 1.15.2.1: OTG dependent Params
++	// -------------------------
++	// Timing
++	unsigned int htotal = dst->htotal;
++	//    unsigned int hblank_start = dst.hblank_start; // TODO: Remove
++	unsigned int hblank_end = dst->hblank_end;
++	unsigned int vblank_start = dst->vblank_start;
++	unsigned int vblank_end = dst->vblank_end;
++	unsigned int min_vblank = mode_lib->ip.min_vblank_lines;
++
++	double dppclk_freq_in_mhz = clks->dppclk_mhz;
++	double dispclk_freq_in_mhz = clks->dispclk_mhz;
++	double refclk_freq_in_mhz = clks->refclk_mhz;
++	double pclk_freq_in_mhz = dst->pixel_rate_mhz;
++	bool interlaced = dst->interlaced;
++
++	double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
++
++	double min_dcfclk_mhz;
++	double t_calc_us;
++	double min_ttu_vblank;
++
++	double min_dst_y_ttu_vblank;
++	unsigned int dlg_vblank_start;
++	bool dual_plane;
++	bool mode_422;
++	unsigned int access_dir;
++	unsigned int vp_height_l;
++	unsigned int vp_width_l;
++	unsigned int vp_height_c;
++	unsigned int vp_width_c;
++
++	// Scaling
++	unsigned int htaps_l;
++	unsigned int htaps_c;
++	double hratio_l;
++	double hratio_c;
++	double vratio_l;
++	double vratio_c;
++	bool scl_enable;
++
++	double line_time_in_us;
++	//    double vinit_l;
++	//    double vinit_c;
++	//    double vinit_bot_l;
++	//    double vinit_bot_c;
++
++	//    unsigned int swath_height_l;
++	unsigned int swath_width_ub_l;
++	//    unsigned int dpte_bytes_per_row_ub_l;
++	unsigned int dpte_groups_per_row_ub_l;
++	//    unsigned int meta_pte_bytes_per_frame_ub_l;
++	//    unsigned int meta_bytes_per_row_ub_l;
++
++	//    unsigned int swath_height_c;
++	unsigned int swath_width_ub_c;
++	//   unsigned int dpte_bytes_per_row_ub_c;
++	unsigned int dpte_groups_per_row_ub_c;
++
++	unsigned int meta_chunks_per_row_ub_l;
++	unsigned int meta_chunks_per_row_ub_c;
++	unsigned int vupdate_offset;
++	unsigned int vupdate_width;
++	unsigned int vready_offset;
++
++	unsigned int dppclk_delay_subtotal;
++	unsigned int dispclk_delay_subtotal;
++	unsigned int pixel_rate_delay_subtotal;
++
++	unsigned int vstartup_start;
++	unsigned int dst_x_after_scaler;
++	unsigned int dst_y_after_scaler;
++	double line_wait;
++	double dst_y_prefetch;
++	double dst_y_per_vm_vblank;
++	double dst_y_per_row_vblank;
++	double dst_y_per_vm_flip;
++	double dst_y_per_row_flip;
++	double max_dst_y_per_vm_vblank;
++	double max_dst_y_per_row_vblank;
++	double lsw;
++	double vratio_pre_l;
++	double vratio_pre_c;
++	unsigned int req_per_swath_ub_l;
++	unsigned int req_per_swath_ub_c;
++	unsigned int meta_row_height_l;
++	unsigned int meta_row_height_c;
++	unsigned int swath_width_pixels_ub_l;
++	unsigned int swath_width_pixels_ub_c;
++	unsigned int scaler_rec_in_width_l;
++	unsigned int scaler_rec_in_width_c;
++	unsigned int dpte_row_height_l;
++	unsigned int dpte_row_height_c;
++	double hscale_pixel_rate_l;
++	double hscale_pixel_rate_c;
++	double min_hratio_fact_l;
++	double min_hratio_fact_c;
++	double refcyc_per_line_delivery_pre_l;
++	double refcyc_per_line_delivery_pre_c;
++	double refcyc_per_line_delivery_l;
++	double refcyc_per_line_delivery_c;
++
++	double refcyc_per_req_delivery_pre_l;
++	double refcyc_per_req_delivery_pre_c;
++	double refcyc_per_req_delivery_l;
++	double refcyc_per_req_delivery_c;
++
++	unsigned int full_recout_width;
++	double xfc_transfer_delay;
++	double xfc_precharge_delay;
++	double xfc_remote_surface_flip_latency;
++	double xfc_dst_y_delta_drq_limit;
++	double xfc_prefetch_margin;
++	double refcyc_per_req_delivery_pre_cur0;
++	double refcyc_per_req_delivery_cur0;
++	double refcyc_per_req_delivery_pre_cur1;
++	double refcyc_per_req_delivery_cur1;
++
++	memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
++	memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
++
++	dml_print("DML_DLG: %s:  cstate_en = %d\n", __func__, cstate_en);
++	dml_print("DML_DLG: %s:  pstate_en = %d\n", __func__, pstate_en);
++
++	dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n", __func__, dppclk_freq_in_mhz);
++	dml_print("DML_DLG: %s: dispclk_freq_in_mhz    = %3.2f\n", __func__, dispclk_freq_in_mhz);
++	dml_print("DML_DLG: %s: refclk_freq_in_mhz     = %3.2f\n", __func__, refclk_freq_in_mhz);
++	dml_print("DML_DLG: %s: pclk_freq_in_mhz       = %3.2f\n", __func__, pclk_freq_in_mhz);
++	dml_print("DML_DLG: %s: interlaced             = %d\n", __func__, interlaced);
++	ASSERT(ref_freq_to_pix_freq < 4.0);
++
++	disp_dlg_regs->ref_freq_to_pix_freq =
++			(unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
++	disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal
++			* dml_pow(2, 8));
++	disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
++	disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end
++			* (double) ref_freq_to_pix_freq);
++	ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));
++
++	min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;
++	t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes);
++	min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++
++	min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
++	dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
++
++	disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2));
++	ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
++
++	dml_print(
++			"DML_DLG: %s: min_dcfclk_mhz                         = %3.2f\n",
++			__func__,
++			min_dcfclk_mhz);
++	dml_print(
++			"DML_DLG: %s: min_ttu_vblank                         = %3.2f\n",
++			__func__,
++			min_ttu_vblank);
++	dml_print(
++			"DML_DLG: %s: min_dst_y_ttu_vblank                   = %3.2f\n",
++			__func__,
++			min_dst_y_ttu_vblank);
++	dml_print(
++			"DML_DLG: %s: t_calc_us                              = %3.2f\n",
++			__func__,
++			t_calc_us);
++	dml_print(
++			"DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start    = 0x%0x\n",
++			__func__,
++			disp_dlg_regs->min_dst_y_next_start);
++	dml_print(
++			"DML_DLG: %s: ref_freq_to_pix_freq                   = %3.2f\n",
++			__func__,
++			ref_freq_to_pix_freq);
++
++	// -------------------------
++	// Section 1.15.2.2: Prefetch, Active and TTU
++	// -------------------------
++	// Prefetch Calc
++	// Source
++	//             dcc_en              = src.dcc;
++	dual_plane = is_dual_plane((enum source_format_class) (src->source_format));
++	mode_422 = 0; // FIXME
++	access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
++						    //      bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0);
++						    //      bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1);
++	vp_height_l = src->viewport_height;
++	vp_width_l = src->viewport_width;
++	vp_height_c = src->viewport_height_c;
++	vp_width_c = src->viewport_width_c;
++
++	// Scaling
++	htaps_l = taps->htaps;
++	htaps_c = taps->htaps_c;
++	hratio_l = scl->hscl_ratio;
++	hratio_c = scl->hscl_ratio_c;
++	vratio_l = scl->vscl_ratio;
++	vratio_c = scl->vscl_ratio_c;
++	scl_enable = scl->scl_enable;
++
++	line_time_in_us = (htotal / pclk_freq_in_mhz);
++	swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub;
++	dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub;
++	swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub;
++	dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub;
++
++	meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub;
++	meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub;
++	vupdate_offset = dst->vupdate_offset;
++	vupdate_width = dst->vupdate_width;
++	vready_offset = dst->vready_offset;
++
++	dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal;
++	dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal;
++
++	if (scl_enable)
++		dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl;
++	else
++		dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only;
++
++	dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter
++			+ src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor;
++
++	if (dout->dsc_enable) {
++		double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++
++		dispclk_delay_subtotal += dsc_delay;
++	}
++
++	pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz
++			+ dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz;
++
++	vstartup_start = dst->vstartup_start;
++	if (interlaced) {
++		if (vstartup_start / 2.0
++				- (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
++				<= vblank_end / 2.0)
++			disp_dlg_regs->vready_after_vcount0 = 1;
++		else
++			disp_dlg_regs->vready_after_vcount0 = 0;
++	} else {
++		if (vstartup_start
++				- (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
++				<= vblank_end)
++			disp_dlg_regs->vready_after_vcount0 = 1;
++		else
++			disp_dlg_regs->vready_after_vcount0 = 0;
++	}
++
++	// TODO: Where is this coming from?
++	if (interlaced)
++		vstartup_start = vstartup_start / 2;
++
++	// TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp?
++	if (vstartup_start >= min_vblank) {
++		dml_print(
++				"WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n",
++				__func__,
++				vblank_start,
++				vblank_end);
++		dml_print(
++				"WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",
++				__func__,
++				vstartup_start,
++				min_vblank);
++		min_vblank = vstartup_start + 1;
++		dml_print(
++				"WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",
++				__func__,
++				vstartup_start,
++				min_vblank);
++	}
++
++	dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++	dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++
++	dml_print("DML_DLG: %s: htotal                                 = %d\n", __func__, htotal);
++	dml_print(
++			"DML_DLG: %s: pixel_rate_delay_subtotal              = %d\n",
++			__func__,
++			pixel_rate_delay_subtotal);
++	dml_print(
++			"DML_DLG: %s: dst_x_after_scaler                     = %d\n",
++			__func__,
++			dst_x_after_scaler);
++	dml_print(
++			"DML_DLG: %s: dst_y_after_scaler                     = %d\n",
++			__func__,
++			dst_y_after_scaler);
++
++	// Lwait
++	// TODO: Should this be urgent_latency_pixel_mixed_with_vm_data_us?
++	line_wait = mode_lib->soc.urgent_latency_pixel_data_only_us;
++	if (cstate_en)
++		line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait);
++	if (pstate_en)
++		line_wait = dml_max(
++				mode_lib->soc.dram_clock_change_latency_us
++						+ mode_lib->soc.urgent_latency_pixel_data_only_us, // TODO: Should this be urgent_latency_pixel_mixed_with_vm_data_us?
++				line_wait);
++	line_wait = line_wait / line_time_in_us;
++
++	dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++	dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch);
++
++	dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(
++			mode_lib,
++			e2e_pipe_param,
++			num_pipes,
++			pipe_idx);
++	dst_y_per_row_vblank = get_dst_y_per_row_vblank(
++			mode_lib,
++			e2e_pipe_param,
++			num_pipes,
++			pipe_idx);
++	dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++	dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++
++	max_dst_y_per_vm_vblank = 32.0;
++	max_dst_y_per_row_vblank = 16.0;
++
++	// magic!
++	if (htotal <= 75) {
++		min_vblank = 300;
++		max_dst_y_per_vm_vblank = 100.0;
++		max_dst_y_per_row_vblank = 100.0;
++	}
++
++	dml_print("DML_DLG: %s: dst_y_per_vm_flip    = %3.2f\n", __func__, dst_y_per_vm_flip);
++	dml_print("DML_DLG: %s: dst_y_per_row_flip   = %3.2f\n", __func__, dst_y_per_row_flip);
++	dml_print("DML_DLG: %s: dst_y_per_vm_vblank  = %3.2f\n", __func__, dst_y_per_vm_vblank);
++	dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank);
++
++	ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank);
++	ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank);
++
++	ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
++	lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank);
++
++	dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw);
++
++	vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++	vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++
++	dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l);
++	dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c);
++
++	// Active
++	req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub;
++	req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub;
++	meta_row_height_l = rq_dlg_param.rq_l.meta_row_height;
++	meta_row_height_c = rq_dlg_param.rq_c.meta_row_height;
++	swath_width_pixels_ub_l = 0;
++	swath_width_pixels_ub_c = 0;
++	scaler_rec_in_width_l = 0;
++	scaler_rec_in_width_c = 0;
++	dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
++	dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
++
++	if (mode_422) {
++		swath_width_pixels_ub_l = swath_width_ub_l * 2;  // *2 for 2 pixel per element
++		swath_width_pixels_ub_c = swath_width_ub_c * 2;
++	} else {
++		swath_width_pixels_ub_l = swath_width_ub_l * 1;
++		swath_width_pixels_ub_c = swath_width_ub_c * 1;
++	}
++
++	hscale_pixel_rate_l = 0.;
++	hscale_pixel_rate_c = 0.;
++	min_hratio_fact_l = 1.0;
++	min_hratio_fact_c = 1.0;
++
++	if (htaps_l <= 1)
++		min_hratio_fact_l = 2.0;
++	else if (htaps_l <= 6) {
++		if ((hratio_l * 2.0) > 4.0)
++			min_hratio_fact_l = 4.0;
++		else
++			min_hratio_fact_l = hratio_l * 2.0;
++	} else {
++		if (hratio_l > 4.0)
++			min_hratio_fact_l = 4.0;
++		else
++			min_hratio_fact_l = hratio_l;
++	}
++
++	hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;
++
++	if (htaps_c <= 1)
++		min_hratio_fact_c = 2.0;
++	else if (htaps_c <= 6) {
++		if ((hratio_c * 2.0) > 4.0)
++			min_hratio_fact_c = 4.0;
++		else
++			min_hratio_fact_c = hratio_c * 2.0;
++	} else {
++		if (hratio_c > 4.0)
++			min_hratio_fact_c = 4.0;
++		else
++			min_hratio_fact_c = hratio_c;
++	}
++
++	hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz;
++
++	refcyc_per_line_delivery_pre_l = 0.;
++	refcyc_per_line_delivery_pre_c = 0.;
++	refcyc_per_line_delivery_l = 0.;
++	refcyc_per_line_delivery_c = 0.;
++
++	refcyc_per_req_delivery_pre_l = 0.;
++	refcyc_per_req_delivery_pre_c = 0.;
++	refcyc_per_req_delivery_l = 0.;
++	refcyc_per_req_delivery_c = 0.;
++
++	full_recout_width = 0;
++	// In ODM
++	if (src->is_hsplit) {
++		// This "hack"  is only allowed (and valid) for MPC combine. In ODM
++		// combine, you MUST specify the full_recout_width...according to Oswin
++		if (dst->full_recout_width == 0 && !dst->odm_combine) {
++			dml_print(
++					"DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n",
++					__func__);
++			full_recout_width = dst->recout_width * 2; // assume half split for dcn1
++		} else
++			full_recout_width = dst->full_recout_width;
++	} else
++		full_recout_width = dst->recout_width;
++
++	// As of DCN2, mpc_combine and odm_combine are mutually exclusive
++	refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(
++			mode_lib,
++			refclk_freq_in_mhz,
++			pclk_freq_in_mhz,
++			dst->odm_combine,
++			full_recout_width,
++			dst->hactive,
++			vratio_pre_l,
++			hscale_pixel_rate_l,
++			swath_width_pixels_ub_l,
++			1); // per line
++
++	refcyc_per_line_delivery_l = get_refcyc_per_delivery(
++			mode_lib,
++			refclk_freq_in_mhz,
++			pclk_freq_in_mhz,
++			dst->odm_combine,
++			full_recout_width,
++			dst->hactive,
++			vratio_l,
++			hscale_pixel_rate_l,
++			swath_width_pixels_ub_l,
++			1); // per line
++
++	dml_print("DML_DLG: %s: full_recout_width              = %d\n", __func__, full_recout_width);
++	dml_print(
++			"DML_DLG: %s: hscale_pixel_rate_l            = %3.2f\n",
++			__func__,
++			hscale_pixel_rate_l);
++	dml_print(
++			"DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n",
++			__func__,
++			refcyc_per_line_delivery_pre_l);
++	dml_print(
++			"DML_DLG: %s: refcyc_per_line_delivery_l     = %3.2f\n",
++			__func__,
++			refcyc_per_line_delivery_l);
++
++	if (dual_plane) {
++		refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(
++				mode_lib,
++				refclk_freq_in_mhz,
++				pclk_freq_in_mhz,
++				dst->odm_combine,
++				full_recout_width,
++				dst->hactive,
++				vratio_pre_c,
++				hscale_pixel_rate_c,
++				swath_width_pixels_ub_c,
++				1); // per line
++
++		refcyc_per_line_delivery_c = get_refcyc_per_delivery(
++				mode_lib,
++				refclk_freq_in_mhz,
++				pclk_freq_in_mhz,
++				dst->odm_combine,
++				full_recout_width,
++				dst->hactive,
++				vratio_c,
++				hscale_pixel_rate_c,
++				swath_width_pixels_ub_c,
++				1);  // per line
++
++		dml_print(
++				"DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n",
++				__func__,
++				refcyc_per_line_delivery_pre_c);
++		dml_print(
++				"DML_DLG: %s: refcyc_per_line_delivery_c     = %3.2f\n",
++				__func__,
++				refcyc_per_line_delivery_c);
++	}
++
++	// TTU - Luma / Chroma
++	if (access_dir) {  // vertical access
++		scaler_rec_in_width_l = vp_height_l;
++		scaler_rec_in_width_c = vp_height_c;
++	} else {
++		scaler_rec_in_width_l = vp_width_l;
++		scaler_rec_in_width_c = vp_width_c;
++	}
++
++	refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(
++			mode_lib,
++			refclk_freq_in_mhz,
++			pclk_freq_in_mhz,
++			dst->odm_combine,
++			full_recout_width,
++			dst->hactive,
++			vratio_pre_l,
++			hscale_pixel_rate_l,
++			scaler_rec_in_width_l,
++			req_per_swath_ub_l);  // per req
++	refcyc_per_req_delivery_l = get_refcyc_per_delivery(
++			mode_lib,
++			refclk_freq_in_mhz,
++			pclk_freq_in_mhz,
++			dst->odm_combine,
++			full_recout_width,
++			dst->hactive,
++			vratio_l,
++			hscale_pixel_rate_l,
++			scaler_rec_in_width_l,
++			req_per_swath_ub_l);  // per req
++
++	dml_print(
++			"DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n",
++			__func__,
++			refcyc_per_req_delivery_pre_l);
++	dml_print(
++			"DML_DLG: %s: refcyc_per_req_delivery_l     = %3.2f\n",
++			__func__,
++			refcyc_per_req_delivery_l);
++
++	ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
++	ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
++
++	if (dual_plane) {
++		refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(
++				mode_lib,
++				refclk_freq_in_mhz,
++				pclk_freq_in_mhz,
++				dst->odm_combine,
++				full_recout_width,
++				dst->hactive,
++				vratio_pre_c,
++				hscale_pixel_rate_c,
++				scaler_rec_in_width_c,
++				req_per_swath_ub_c);  // per req
++		refcyc_per_req_delivery_c = get_refcyc_per_delivery(
++				mode_lib,
++				refclk_freq_in_mhz,
++				pclk_freq_in_mhz,
++				dst->odm_combine,
++				full_recout_width,
++				dst->hactive,
++				vratio_c,
++				hscale_pixel_rate_c,
++				scaler_rec_in_width_c,
++				req_per_swath_ub_c);  // per req
++
++		dml_print(
++				"DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n",
++				__func__,
++				refcyc_per_req_delivery_pre_c);
++		dml_print(
++				"DML_DLG: %s: refcyc_per_req_delivery_c     = %3.2f\n",
++				__func__,
++				refcyc_per_req_delivery_c);
++
++		ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
++		ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
++	}
++
++	// XFC
++	xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
++	xfc_precharge_delay = get_xfc_precharge_delay(
++			mode_lib,
++			e2e_pipe_param,
++			num_pipes,
++			pipe_idx);
++	xfc_remote_surface_flip_latency = get_xfc_remote_surface_flip_latency(
++			mode_lib,
++			e2e_pipe_param,
++			num_pipes,
++			pipe_idx);
++	xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency;
++	xfc_prefetch_margin = get_xfc_prefetch_margin(
++			mode_lib,
++			e2e_pipe_param,
++			num_pipes,
++			pipe_idx);
++
++	// TTU - Cursor
++	refcyc_per_req_delivery_pre_cur0 = 0.0;
++	refcyc_per_req_delivery_cur0 = 0.0;
++	if (src->num_cursors > 0) {
++		calculate_ttu_cursor(
++				mode_lib,
++				&refcyc_per_req_delivery_pre_cur0,
++				&refcyc_per_req_delivery_cur0,
++				refclk_freq_in_mhz,
++				ref_freq_to_pix_freq,
++				hscale_pixel_rate_l,
++				scl->hscl_ratio,
++				vratio_pre_l,
++				vratio_l,
++				src->cur0_src_width,
++				(enum cursor_bpp) (src->cur0_bpp));
++	}
++
++	refcyc_per_req_delivery_pre_cur1 = 0.0;
++	refcyc_per_req_delivery_cur1 = 0.0;
++	if (src->num_cursors > 1) {
++		calculate_ttu_cursor(
++				mode_lib,
++				&refcyc_per_req_delivery_pre_cur1,
++				&refcyc_per_req_delivery_cur1,
++				refclk_freq_in_mhz,
++				ref_freq_to_pix_freq,
++				hscale_pixel_rate_l,
++				scl->hscl_ratio,
++				vratio_pre_l,
++				vratio_l,
++				src->cur1_src_width,
++				(enum cursor_bpp) (src->cur1_bpp));
++	}
++
++	// TTU - Misc
++	// all hard-coded
++
++	// Assignment to register structures
++	disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line
++	disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk
++	ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));
++	disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
++	disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
++	disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
++	disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));
++	disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
++
++	disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
++	disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
++
++	dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_vblank  = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_vblank);
++	dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_vblank);
++	dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip    = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip);
++	dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip   = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip);
++
++	disp_dlg_regs->refcyc_per_pte_group_vblank_l =
++			(unsigned int) (dst_y_per_row_vblank * (double) htotal
++					* ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
++	ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));
++
++	if (dual_plane) {
++		disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank
++				* (double) htotal * ref_freq_to_pix_freq
++				/ (double) dpte_groups_per_row_ub_c);
++		ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c
++				< (unsigned int)dml_pow(2, 13));
++	}
++
++	disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
++			(unsigned int) (dst_y_per_row_vblank * (double) htotal
++					* ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l);
++	ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));
++
++	disp_dlg_regs->refcyc_per_meta_chunk_vblank_c =
++			disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
++
++	disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
++			* ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l;
++	disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
++			* ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l;
++
++	if (dual_plane) {
++		disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip
++				* htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c;
++		disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip
++				* htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c;
++	}
++
++	disp_dlg_regs->refcyc_per_vm_group_vblank   = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;
++	disp_dlg_regs->refcyc_per_vm_group_flip     = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;
++	disp_dlg_regs->refcyc_per_vm_req_vblank     = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;;
++	disp_dlg_regs->refcyc_per_vm_req_flip       = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;;
++
++	// Clamp to max for now
++	if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23))
++		disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1;
++
++	if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23))
++		disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1;
++
++	if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23))
++		disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1;
++
++	if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23))
++		disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1;
++	disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l
++			/ (double) vratio_l * dml_pow(2, 2));
++	ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));
++
++	if (dual_plane) {
++		disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c
++				/ (double) vratio_c * dml_pow(2, 2));
++		if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {
++			dml_print(
++					"DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n",
++					__func__,
++					disp_dlg_regs->dst_y_per_pte_row_nom_c,
++					(unsigned int)dml_pow(2, 17) - 1);
++		}
++	}
++
++	disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l
++			/ (double) vratio_l * dml_pow(2, 2));
++	ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));
++
++	disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
++
++	dml_print(
++			"DML: Trow: %fus\n",
++			line_time_in_us * (double)dpte_row_height_l / (double)vratio_l);
++
++	disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l
++			/ (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
++			/ (double) dpte_groups_per_row_ub_l);
++	if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
++		disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
++	disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l
++			/ (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
++			/ (double) meta_chunks_per_row_ub_l);
++	if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
++		disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
++
++	if (dual_plane) {
++		disp_dlg_regs->refcyc_per_pte_group_nom_c =
++				(unsigned int) ((double) dpte_row_height_c / (double) vratio_c
++						* (double) htotal * ref_freq_to_pix_freq
++						/ (double) dpte_groups_per_row_ub_c);
++		if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
++			disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
++
++		// TODO: Is this the right calculation? Does htotal need to be halved?
++		disp_dlg_regs->refcyc_per_meta_chunk_nom_c =
++				(unsigned int) ((double) meta_row_height_c / (double) vratio_c
++						* (double) htotal * ref_freq_to_pix_freq
++						/ (double) meta_chunks_per_row_ub_c);
++		if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))
++			disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;
++	}
++
++	disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(
++			refcyc_per_line_delivery_pre_l, 1);
++	disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(
++			refcyc_per_line_delivery_l, 1);
++	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13));
++	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));
++
++	disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(
++			refcyc_per_line_delivery_pre_c, 1);
++	disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(
++			refcyc_per_line_delivery_c, 1);
++	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13));
++	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));
++
++	disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
++	disp_dlg_regs->dst_y_offset_cur0 = 0;
++	disp_dlg_regs->chunk_hdl_adjust_cur1 = 3;
++	disp_dlg_regs->dst_y_offset_cur1 = 0;
++
++	disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay;
++	disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay;
++	disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency;
++	disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(
++			xfc_prefetch_margin * refclk_freq_in_mhz, 1);
++
++	// slave has to have this value also set to off
++	if (src->xfc_enable && !src->xfc_slave)
++		disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
++	else
++		disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
++
++	disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l
++			* dml_pow(2, 10));
++	disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l
++			* dml_pow(2, 10));
++	disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c
++			* dml_pow(2, 10));
++	disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c
++			* dml_pow(2, 10));
++	disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 =
++			(unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
++	disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0
++			* dml_pow(2, 10));
++	disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 =
++			(unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));
++	disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1
++			* dml_pow(2, 10));
++	disp_ttu_regs->qos_level_low_wm = 0;
++	ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
++	disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
++			* ref_freq_to_pix_freq);
++	ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
++
++	disp_ttu_regs->qos_level_flip = 14;
++	disp_ttu_regs->qos_level_fixed_l = 8;
++	disp_ttu_regs->qos_level_fixed_c = 8;
++	disp_ttu_regs->qos_level_fixed_cur0 = 8;
++	disp_ttu_regs->qos_ramp_disable_l = 0;
++	disp_ttu_regs->qos_ramp_disable_c = 0;
++	disp_ttu_regs->qos_ramp_disable_cur0 = 0;
++
++	disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
++	ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
++
++	print__ttu_regs_st(mode_lib, *disp_ttu_regs);
++	print__dlg_regs_st(mode_lib, *disp_dlg_regs);
++}
++
++void dml21_rq_dlg_get_dlg_reg(
++		struct display_mode_lib *mode_lib,
++		display_dlg_regs_st *dlg_regs,
++		display_ttu_regs_st *ttu_regs,
++		display_e2e_pipe_params_st *e2e_pipe_param,
++		const unsigned int num_pipes,
++		const unsigned int pipe_idx,
++		const bool cstate_en,
++		const bool pstate_en,
++		const bool vm_en,
++		const bool ignore_viewport_pos,
++		const bool immediate_flip_support)
++{
++	display_rq_params_st rq_param = {0};
++	display_dlg_sys_params_st dlg_sys_param = {0};
++
++	// Get watermark and Tex.
++	dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes);
++	dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(
++			mode_lib,
++			e2e_pipe_param,
++			num_pipes);
++	dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes);
++	dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes);
++	dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes);
++	dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes);
++	dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(
++			mode_lib,
++			e2e_pipe_param,
++			num_pipes);
++	dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(
++			mode_lib,
++			e2e_pipe_param,
++			num_pipes);
++	dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency
++			/ dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated
++
++	print__dlg_sys_params_st(mode_lib, dlg_sys_param);
++
++	// system parameter calculation done
++
++	dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx);
++	dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe);
++	dml_rq_dlg_get_dlg_params(
++			mode_lib,
++			e2e_pipe_param,
++			num_pipes,
++			pipe_idx,
++			dlg_regs,
++			ttu_regs,
++			rq_param.dlg,
++			dlg_sys_param,
++			cstate_en,
++			pstate_en);
++	dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
++}
++
++void dml_rq_dlg_get_arb_params(struct display_mode_lib *mode_lib, display_arb_params_st *arb_param)
++{
++	memset(arb_param, 0, sizeof(*arb_param));
++	arb_param->max_req_outstanding = 256;
++	arb_param->min_req_outstanding = 68;
++	arb_param->sat_level_us = 60;
++}
++
++static void calculate_ttu_cursor(
++		struct display_mode_lib *mode_lib,
++		double *refcyc_per_req_delivery_pre_cur,
++		double *refcyc_per_req_delivery_cur,
++		double refclk_freq_in_mhz,
++		double ref_freq_to_pix_freq,
++		double hscale_pixel_rate_l,
++		double hscl_ratio,
++		double vratio_pre_l,
++		double vratio_l,
++		unsigned int cur_width,
++		enum cursor_bpp cur_bpp)
++{
++	unsigned int cur_src_width = cur_width;
++	unsigned int cur_req_size = 0;
++	unsigned int cur_req_width = 0;
++	double cur_width_ub = 0.0;
++	double cur_req_per_width = 0.0;
++	double hactive_cur = 0.0;
++
++	ASSERT(cur_src_width <= 256);
++
++	*refcyc_per_req_delivery_pre_cur = 0.0;
++	*refcyc_per_req_delivery_cur = 0.0;
++	if (cur_src_width > 0) {
++		unsigned int cur_bit_per_pixel = 0;
++
++		if (cur_bpp == dm_cur_2bit) {
++			cur_req_size = 64; // byte
++			cur_bit_per_pixel = 2;
++		} else { // 32bit
++			cur_bit_per_pixel = 32;
++			if (cur_src_width >= 1 && cur_src_width <= 16)
++				cur_req_size = 64;
++			else if (cur_src_width >= 17 && cur_src_width <= 31)
++				cur_req_size = 128;
++			else
++				cur_req_size = 256;
++		}
++
++		cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0);
++		cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1)
++				* (double) cur_req_width;
++		cur_req_per_width = cur_width_ub / (double) cur_req_width;
++		hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor
++
++		if (vratio_pre_l <= 1.0) {
++			*refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq
++					/ (double) cur_req_per_width;
++		} else {
++			*refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz
++					* (double) cur_src_width / hscale_pixel_rate_l
++					/ (double) cur_req_per_width;
++		}
++
++		ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
++
++		if (vratio_l <= 1.0) {
++			*refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq
++					/ (double) cur_req_per_width;
++		} else {
++			*refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz
++					* (double) cur_src_width / hscale_pixel_rate_l
++					/ (double) cur_req_per_width;
++		}
++
++		dml_print(
++				"DML_DLG: %s: cur_req_width                     = %d\n",
++				__func__,
++				cur_req_width);
++		dml_print(
++				"DML_DLG: %s: cur_width_ub                      = %3.2f\n",
++				__func__,
++				cur_width_ub);
++		dml_print(
++				"DML_DLG: %s: cur_req_per_width                 = %3.2f\n",
++				__func__,
++				cur_req_per_width);
++		dml_print(
++				"DML_DLG: %s: hactive_cur                       = %3.2f\n",
++				__func__,
++				hactive_cur);
++		dml_print(
++				"DML_DLG: %s: refcyc_per_req_delivery_pre_cur   = %3.2f\n",
++				__func__,
++				*refcyc_per_req_delivery_pre_cur);
++		dml_print(
++				"DML_DLG: %s: refcyc_per_req_delivery_cur       = %3.2f\n",
++				__func__,
++				*refcyc_per_req_delivery_cur);
++
++		ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
++	}
++}
++
++#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
+new file mode 100644
+index 000000000000..83e95f8cbff2
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
+@@ -0,0 +1,73 @@
++/*
++ * Copyright 2017 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DML21_DISPLAY_RQ_DLG_CALC_H__
++#define __DML21_DISPLAY_RQ_DLG_CALC_H__
++
++#include "../dml_common_defs.h"
++#include "../display_rq_dlg_helpers.h"
++
++struct display_mode_lib;
++
++
++// Function: dml_rq_dlg_get_rq_reg
++//  Main entry point for test to get the register values out of this DML class.
++//  This function calls <get_rq_param> and <extract_rq_regs> functions to calculate
++//  and then populate the rq_regs struct
++// Input:
++//  pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
++// Output:
++//  rq_regs - struct that holds all the RQ registers field value.
++//            See also: <display_rq_regs_st>
++void dml21_rq_dlg_get_rq_reg(
++		struct display_mode_lib *mode_lib,
++		display_rq_regs_st *rq_regs,
++		const display_pipe_params_st pipe_param);
++
++// Function: dml_rq_dlg_get_dlg_reg
++//   Calculate and return DLG and TTU register struct given the system setting
++// Output:
++//  dlg_regs - output DLG register struct
++//  ttu_regs - output DLG TTU register struct
++// Input:
++//  e2e_pipe_param - "compacted" array of e2e pipe param struct
++//  num_pipes - num of active "pipe" or "route"
++//  pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
++//  cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
++//           Added for legacy or unrealistic timing tests.
++void dml21_rq_dlg_get_dlg_reg(
++		struct display_mode_lib *mode_lib,
++		display_dlg_regs_st *dlg_regs,
++		display_ttu_regs_st *ttu_regs,
++		display_e2e_pipe_params_st *e2e_pipe_param,
++		const unsigned int num_pipes,
++		const unsigned int pipe_idx,
++		const bool cstate_en,
++		const bool pstate_en,
++		const bool vm_en,
++		const bool ignore_viewport_pos,
++		const bool immediate_flip_support);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+index 870716e3c132..d8c59aa356b6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+@@ -38,6 +38,9 @@ enum dml_project {
+ 	DML_PROJECT_NAVI10,
+ 	DML_PROJECT_NAVI10v2,
+ #endif
++#ifdef CONFIG_DRM_AMD_DC_DCN2_1
++	DML_PROJECT_DCN21,
++#endif
+ };
+ 
+ struct display_mode_lib;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3643-drm-amd-display-Fix-register-names.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3643-drm-amd-display-Fix-register-names.patch
new file mode 100644
index 00000000..05146fe7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3643-drm-amd-display-Fix-register-names.patch
@@ -0,0 +1,33 @@
+From ffe90320bc0191da82351234c452e295bace8b7d Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 26 Jul 2019 16:59:04 -0400
+Subject: [PATCH 3643/4256] drm/amd/display: Fix register names
+
+rename VM_CONTEXT0 to  MMVM_CONTEXT0 as that is the name defined in
+the register files
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+index b7767d6be1b4..ac04d77058f0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+@@ -643,8 +643,8 @@ struct dce_hwseq_registers {
+ #define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\
+ 	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
+ 	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+-	HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
+-	HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
++	HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
++	HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
+ 	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
+ 	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
+ 	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3644-drm-amd-display-Handle-Renoir-in-DC.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3644-drm-amd-display-Handle-Renoir-in-DC.patch
new file mode 100644
index 00000000..23168df3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3644-drm-amd-display-Handle-Renoir-in-DC.patch
@@ -0,0 +1,86 @@
+From 06de19e73d091f20522eeebb62e857ec56befeca Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 26 Jul 2019 17:06:02 -0400
+Subject: [PATCH 3644/4256] drm/amd/display: Handle Renoir in DC
+
+add Renoir DCN version in DC and handle it
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/display/dc/bios/command_table_helper2.c  |  5 +++++
+ drivers/gpu/drm/amd/display/dc/core/dc_resource.c    | 12 ++++++++++++
+ drivers/gpu/drm/amd/display/include/dal_types.h      |  3 +++
+ 3 files changed, 20 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+index f9439dfc7b75..db153ddf0fee 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+@@ -66,6 +66,11 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
+ 	case DCN_VERSION_2_0:
+ 		*h = dal_cmd_tbl_helper_dce112_get_table2();
+ 		return true;
++#endif
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	case DCN_VERSION_2_1:
++		*h = dal_cmd_tbl_helper_dce112_get_table2();
++		return true;
+ #endif
+ 	case DCE_VERSION_12_0:
+ 	case DCE_VERSION_12_1:
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index adbf2d4e1723..2ae883a248da 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -49,6 +49,9 @@
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "dcn20/dcn20_resource.h"
+ #endif
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++#include "dcn21/dcn21_resource.h"
++#endif
+ #include "dce120/dce120_resource.h"
+ 
+ #define DC_LOGGER_INIT(logger)
+@@ -98,6 +101,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
+ 		dc_version = DCN_VERSION_1_0;
+ 		if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
+ 			dc_version = DCN_VERSION_1_01;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++		if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
++			dc_version = DCN_VERSION_2_1;
++#endif
+ 		break;
+ #endif
+ 
+@@ -165,6 +172,11 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
+ 		res_pool = dcn20_create_resource_pool(init_data, dc);
+ 		break;
+ #endif
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	case DCN_VERSION_2_1:
++		res_pool = dcn21_create_resource_pool(init_data, dc);
++		break;
++#endif
+ 
+ 	default:
+ 		break;
+diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
+index 1e3ce4d847ae..fcc42372b6cf 100644
+--- a/drivers/gpu/drm/amd/display/include/dal_types.h
++++ b/drivers/gpu/drm/amd/display/include/dal_types.h
+@@ -48,6 +48,9 @@ enum dce_version {
+ 	DCN_VERSION_1_01,
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	DCN_VERSION_2_0,
++#endif
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	DCN_VERSION_2_1,
+ #endif
+ 	DCN_VERSION_MAX
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3645-drm-amd-display-Handle-Renoir-in-amdgpu_dm-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3645-drm-amd-display-Handle-Renoir-in-amdgpu_dm-v2.patch
new file mode 100644
index 00000000..a0af5c25
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3645-drm-amd-display-Handle-Renoir-in-amdgpu_dm-v2.patch
@@ -0,0 +1,65 @@
+From f5c770e49abda7da0eff3df35ccf3c5f5da0918d Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 26 Jul 2019 17:08:45 -0400
+Subject: [PATCH 3645/4256] drm/amd/display: Handle Renoir in amdgpu_dm (v2)
+
+Hook up renoir support to KMS.
+
+v2: squash in "Fixes for Renoir in amdgpu_dm"
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 2addfae05e39..df3a5ef819dd 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -811,6 +811,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+ 	case CHIP_NAVI12:
++	case CHIP_RENOIR:
+ 		return 0;
+ 	case CHIP_RAVEN:
+ 		if (ASICREV_IS_PICASSO(adev->external_rev_id))
+@@ -2363,6 +2364,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
++#endif
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	case CHIP_RENOIR:
+ #endif
+ 		if (dcn10_register_irq_handlers(dm->adev)) {
+ 			DRM_ERROR("DM: Failed to initialize IRQ\n");
+@@ -2614,6 +2618,13 @@ static int dm_early_init(void *handle)
+ 		adev->mode_info.num_hpd = 5;
+ 		adev->mode_info.num_dig = 5;
+ 		break;
++#endif
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	case CHIP_RENOIR:
++		adev->mode_info.num_crtc = 4;
++		adev->mode_info.num_hpd = 4;
++		adev->mode_info.num_dig = 4;
++		break;
+ #endif
+ 	default:
+ 		DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
+@@ -2911,6 +2922,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
+ 	    adev->asic_type == CHIP_NAVI10 ||
+ 	    adev->asic_type == CHIP_NAVI14 ||
+ 	    adev->asic_type == CHIP_NAVI12 ||
++#endif
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	    adev->asic_type == CHIP_RENOIR ||
+ #endif
+ 	    adev->asic_type == CHIP_RAVEN) {
+ 		/* Fill GFX9 params */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3646-drm-amd-display-call-update_bw_bounding_box.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3646-drm-amd-display-call-update_bw_bounding_box.patch
new file mode 100644
index 00000000..2d1222d1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3646-drm-amd-display-call-update_bw_bounding_box.patch
@@ -0,0 +1,50 @@
+From 8e67ffbb7a50cda9cde8daf475193ad4c0e39896 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 26 Jul 2019 17:09:35 -0400
+Subject: [PATCH 3646/4256] drm/amd/display: call update_bw_bounding_box
+
+call update_bw_bounding_box in DC construct
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c        | 5 +++++
+ drivers/gpu/drm/amd/display/dc/inc/core_types.h | 5 +++++
+ 2 files changed, 10 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 8dd9db41bc4a..d5e4d6337113 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -693,6 +693,11 @@ static bool construct(struct dc *dc,
+ 	if (!dc->clk_mgr)
+ 		goto fail;
+ 
++#ifdef CONFIG_DRM_AMD_DC_DCN2_1
++	if (dc->res_pool->funcs->update_bw_bounding_box)
++		dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
++#endif
++
+ 	/* Creation of current_state must occur after dc->dml
+ 	 * is initialized in dc_create_resource_pool because
+ 	 * on creation it copies the contents of dc->dml
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index df28fbc4c63c..8726bd7dd910 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -142,6 +142,11 @@ struct resource_funcs {
+ 			display_e2e_pipe_params_st *pipes,
+ 			int pipe_cnt);
+ #endif
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	void (*update_bw_bounding_box)(
++			struct dc *dc,
++			struct clk_bw_params *bw_params);
++#endif
+ 
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3647-drm-amd-display-add-dal_asic_id-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3647-drm-amd-display-add-dal_asic_id-for-renoir.patch
new file mode 100644
index 00000000..69f0000e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3647-drm-amd-display-add-dal_asic_id-for-renoir.patch
@@ -0,0 +1,33 @@
+From 8afe70cc1e07acffcb2599cde92c28345cc4431c Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 26 Jul 2019 17:14:34 -0400
+Subject: [PATCH 3647/4256] drm/amd/display: add dal_asic_id for renoir
+
+Add the rev id for renoir.
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/include/dal_asic_id.h | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+index cb9b1873f947..47c156800e1e 100644
+--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
++++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+@@ -160,6 +160,11 @@ enum {
+ #define ASICREV_IS_NAVI12_P(eChipRev)        ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0))
+ #define ASICREV_IS_NAVI14_M(eChipRev)        ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN))
+ #endif
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++#define RENOIR_A0 0x91
++#define DEVICE_ID_RENOIR_1636 0x1636   // Renoir
++#define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < 0xFF))
++#endif
+ 
+ /*
+  * ASIC chip ID
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3648-drm-amd-display-add-dcn21-core-DC-changes.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3648-drm-amd-display-add-dcn21-core-DC-changes.patch
new file mode 100644
index 00000000..ace78808
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3648-drm-amd-display-add-dcn21-core-DC-changes.patch
@@ -0,0 +1,76 @@
+From fb4d04659221573784f9f4d51c125b54a180e48d Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 26 Jul 2019 17:16:47 -0400
+Subject: [PATCH 3648/4256] drm/amd/display: add dcn21 core DC changes
+
+Add missing parameters, to make dcn21 compile
+without errors
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h               | 3 +++
+ drivers/gpu/drm/amd/display/dc/inc/core_types.h   | 3 +++
+ drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 ++++
+ drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 +
+ 4 files changed, 11 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index dcb2d4505c58..9e006ad6fa47 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -388,6 +388,9 @@ struct dc_debug_options {
+ 	struct dc_bw_validation_profile bw_val_profile;
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	bool disable_fec;
++#endif
++#ifdef CONFIG_DRM_AMD_DC_DCN2_1
++	bool disable_48mhz_pwrdwn;
+ #endif
+ 	/* This forces a hard min on the DCFCLK requested to SMU/PP
+ 	 * watermarks are not affected.
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index 8726bd7dd910..f189307750ab 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -87,6 +87,9 @@ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
+ struct resource_pool;
+ struct dc_state;
+ struct resource_context;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++struct clk_bw_params;
++#endif
+ 
+ struct resource_funcs {
+ 	void (*destroy)(struct resource_pool **pool);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+index 7193acfcd779..e8668388581b 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+@@ -40,6 +40,10 @@ struct cstate_pstate_watermarks_st {
+ struct dcn_watermarks {
+ 	uint32_t pte_meta_urgent_ns;
+ 	uint32_t urgent_ns;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	uint32_t frac_urg_bw_nom;
++	uint32_t frac_urg_bw_flip;
++#endif
+ 	struct cstate_pstate_watermarks_st cstate_pstate;
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index 732a93df1844..3a938cd414ea 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -48,6 +48,7 @@ struct dce_hwseq_wa {
+ 	bool DEGVIDCN10_253;
+ 	bool false_optc_underflow;
+ 	bool DEGVIDCN10_254;
++	bool DEGVIDCN21;
+ };
+ 
+ struct hwseq_wa_state {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3649-drm-amd-display-build-dcn21-blocks.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3649-drm-amd-display-build-dcn21-blocks.patch
new file mode 100644
index 00000000..479f92e1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3649-drm-amd-display-build-dcn21-blocks.patch
@@ -0,0 +1,31 @@
+From adebddc23b190c1eb9ff563a6d6d3b0879e509ab Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 26 Jul 2019 17:20:21 -0400
+Subject: [PATCH 3649/4256] drm/amd/display: build dcn21 blocks
+
+Enable the building of dcn21 support.
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/Makefile | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
+index 55ce5b657390..627982cb15d2 100644
+--- a/drivers/gpu/drm/amd/display/dc/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/Makefile
+@@ -37,6 +37,9 @@ endif
+ ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ DC_LIBS += dcn10 dml
+ endif
++ifdef CONFIG_DRM_AMD_DC_DCN2_1
++DC_LIBS += dcn21
++endif
+ 
+ DC_LIBS += dce120
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3650-drm-amd-display-add-Renoir-to-kconfig.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3650-drm-amd-display-add-Renoir-to-kconfig.patch
new file mode 100644
index 00000000..ed9fca4b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3650-drm-amd-display-add-Renoir-to-kconfig.patch
@@ -0,0 +1,36 @@
+From 397d0ef1cb89c3175d6696f98d1bb9e30697a43a Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 26 Jul 2019 17:21:03 -0400
+Subject: [PATCH 3650/4256] drm/amd/display: add Renoir to kconfig
+
+Add a kconfig option to enable renoir.
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/Kconfig | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
+index 48c7423e92da..8154fd637afb 100644
+--- a/drivers/gpu/drm/amd/display/Kconfig
++++ b/drivers/gpu/drm/amd/display/Kconfig
+@@ -25,6 +25,14 @@ config DRM_AMD_DC_DCN2_0
+ 	    Choose this option if you want to have
+ 	    Navi support for display engine
+ 
++config DRM_AMD_DC_DCN2_1
++        bool "DCN 2.1 family"
++        depends on DRM_AMD_DC && X86
++        depends on DRM_AMD_DC_DCN2_0
++        help
++            Choose this option if you want to have
++            Renoir support for display engine
++
+ config DRM_AMD_DC_DSC_SUPPORT
+ 	bool "DSC support"
+ 	default y
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3651-drm-amd-display-Correct-order-of-RV-family-clk-manag.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3651-drm-amd-display-Correct-order-of-RV-family-clk-manag.patch
new file mode 100644
index 00000000..2af0778b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3651-drm-amd-display-Correct-order-of-RV-family-clk-manag.patch
@@ -0,0 +1,48 @@
+From d946392e6b120aee16a1c4ace2187fe2538c6e83 Mon Sep 17 00:00:00 2001
+From: Roman Li <Roman.Li@amd.com>
+Date: Thu, 8 Aug 2019 15:11:37 -0400
+Subject: [PATCH 3651/4256] drm/amd/display: Correct order of RV family clk
+ managers for Renoir
+
+Need to check for renoir first.
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Roman Li <Roman.Li@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+index 66277a9a4ec2..8da1256bc144 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+@@ -109,6 +109,12 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ 	case FAMILY_RV:
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++		if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) {
++			rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
++			break;
++		}
++#endif	/* DCN2_1 */
+ 		if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
+ 			rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
+ 			break;
+@@ -118,12 +124,6 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
+ 			rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu);
+ 			break;
+ 		}
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+-		if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) {
+-			rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+-			break;
+-		}
+-#endif	/* DCN2_1 */
+ 		break;
+ #endif	/* Family RV */
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3652-drm-amd-display-Add-DCN2.1-changes-to-DML.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3652-drm-amd-display-Add-DCN2.1-changes-to-DML.patch
new file mode 100644
index 00000000..bb4ee152
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3652-drm-amd-display-Add-DCN2.1-changes-to-DML.patch
@@ -0,0 +1,77 @@
+From 509a4a79c9089c05320777c8ee54d33c676db771 Mon Sep 17 00:00:00 2001
+From: Roman Li <Roman.Li@amd.com>
+Date: Thu, 8 Aug 2019 15:14:25 -0400
+Subject: [PATCH 3652/4256] drm/amd/display: Add DCN2.1 changes to DML
+
+Hook up the DML changes for renoir.
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Roman Li <Roman.Li@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dml/Makefile   |  4 ++++
+ .../drm/amd/display/dc/dml/display_mode_lib.c | 19 +++++++++++++++++++
+ 2 files changed, 23 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+index b267c0fc64e7..af2a864a6da0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+@@ -63,6 +63,10 @@ ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_20.o
+ DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o
+ endif
++ifdef CONFIG_DRM_AMD_DC_DCN2_1
++DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o
++endif
++
+ 
+ AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+index 96dfcd8c36bc..704efefdcba8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+@@ -31,6 +31,10 @@
+ #include "dcn20/display_mode_vba_20v2.h"
+ #include "dcn20/display_rq_dlg_calc_20v2.h"
+ #endif
++#ifdef CONFIG_DRM_AMD_DC_DCN2_1
++#include "dcn21/display_mode_vba_21.h"
++#include "dcn21/display_rq_dlg_calc_21.h"
++#endif
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ const struct dml_funcs dml20_funcs = {
+@@ -48,6 +52,15 @@ const struct dml_funcs dml20v2_funcs = {
+ };
+ #endif
+ 
++#ifdef CONFIG_DRM_AMD_DC_DCN2_1
++const struct dml_funcs dml21_funcs = {
++        .validate = dml21_ModeSupportAndSystemConfigurationFull,
++        .recalculate = dml21_recalculate,
++        .rq_dlg_get_dlg_reg = dml21_rq_dlg_get_dlg_reg,
++        .rq_dlg_get_rq_reg = dml21_rq_dlg_get_rq_reg
++};
++#endif
++
+ void dml_init_instance(struct display_mode_lib *lib,
+ 		const struct _vcs_dpi_soc_bounding_box_st *soc_bb,
+ 		const struct _vcs_dpi_ip_params_st *ip_params,
+@@ -65,6 +78,12 @@ void dml_init_instance(struct display_mode_lib *lib,
+ 		lib->funcs = dml20v2_funcs;
+ 		break;
+ #endif
++#ifdef CONFIG_DRM_AMD_DC_DCN2_1
++        case DML_PROJECT_DCN21:
++                lib->funcs = dml21_funcs;
++                break;
++#endif
++
+ 	default:
+ 		break;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3653-drm-amdgpu-Enable-DC-on-Renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3653-drm-amdgpu-Enable-DC-on-Renoir.patch
new file mode 100644
index 00000000..5b868ab9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3653-drm-amdgpu-Enable-DC-on-Renoir.patch
@@ -0,0 +1,49 @@
+From 728ca12df0cf7602489245dd4a74485f35da9d13 Mon Sep 17 00:00:00 2001
+From: Roman Li <Roman.Li@amd.com>
+Date: Thu, 8 Aug 2019 16:26:44 -0400
+Subject: [PATCH 3653/4256] drm/amdgpu: Enable DC on Renoir
+
+Enable DC support for renoir.
+
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Roman Li <Roman.Li@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
+ drivers/gpu/drm/amd/amdgpu/soc15.c         | 6 ++++++
+ 2 files changed, 9 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index ed01af203896..20db92980a49 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2495,6 +2495,9 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+ 	case CHIP_NAVI12:
++#endif
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	case CHIP_RENOIR:
+ #endif
+ 		return amdgpu_dc != 0;
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 8af7501bded1..98cdf3eccaec 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -767,6 +767,12 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ 		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
+ 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+ 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
++#if defined(CONFIG_DRM_AMD_DC)
++                else if (amdgpu_device_has_dc_support(adev))
++                        amdgpu_device_ip_block_add(adev, &dm_ip_block);
++#else
++#       warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
++#endif
+ 		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
+ 		break;
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3654-drm-amdgpu-Handle-job-is-NULL-use-case-in-amdgpu_dev.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3654-drm-amdgpu-Handle-job-is-NULL-use-case-in-amdgpu_dev.patch
new file mode 100644
index 00000000..cc5c8264
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3654-drm-amdgpu-Handle-job-is-NULL-use-case-in-amdgpu_dev.patch
@@ -0,0 +1,61 @@
+From 862335880122456c3a9e26072eead13eb60fba3e Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Tue, 27 Aug 2019 12:14:47 -0400
+Subject: [PATCH 3654/4256] drm/amdgpu: Handle job is NULL use case in
+ amdgpu_device_gpu_recover
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This should be checked at all places job is accessed.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 20db92980a49..f10748306462 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3779,14 +3779,14 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 
+ 	if (hive && !mutex_trylock(&hive->reset_lock)) {
+ 		DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
+-			 job->base.id, hive->hive_id);
++			  job ? job->base.id : -1, hive->hive_id);
+ 		return 0;
+ 	}
+ 
+ 	/* Start with adev pre asic reset first for soft reset check.*/
+ 	if (!amdgpu_device_lock_adev(adev, !hive)) {
+ 		DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress",
+-					 job->base.id);
++			  job ? job->base.id : -1);
+ 		return 0;
+ 	}
+ 
+@@ -3827,7 +3827,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 			if (!ring || !ring->sched.thread)
+ 				continue;
+ 
+-			drm_sched_stop(&ring->sched, &job->base);
++			drm_sched_stop(&ring->sched, job ? &job->base : NULL);
+ 		}
+ 	}
+ 
+@@ -3852,9 +3852,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 
+ 
+ 	/* Guilty job will be freed after this*/
+-	r = amdgpu_device_pre_asic_reset(adev,
+-					 job,
+-					 &need_full_reset);
++	r = amdgpu_device_pre_asic_reset(adev, job, &need_full_reset);
+ 	if (r) {
+ 		/*TODO Should we stop ?*/
+ 		DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3655-drm-amdgpu-add-new-amdgpu-nbio-header-file.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3655-drm-amdgpu-add-new-amdgpu-nbio-header-file.patch
new file mode 100644
index 00000000..e71b3e02
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3655-drm-amdgpu-add-new-amdgpu-nbio-header-file.patch
@@ -0,0 +1,111 @@
+From fc1a5c9029e903328833861dc897a5d86a03bf63 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Fri, 23 Aug 2019 19:02:14 +0800
+Subject: [PATCH 3655/4256] drm/amdgpu: add new amdgpu nbio header file
+
+More nbio funcitonalities will be added and nbio could
+be treated as an ip block like gfx/sdma.etc
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 87 ++++++++++++++++++++++++
+ 1 file changed, 87 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+new file mode 100644
+index 000000000000..0563476b1242
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+@@ -0,0 +1,87 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __AMDGPU_NBIO_H__
++#define __AMDGPU_NBIO_H__
++
++/*
++ * amdgpu nbio functions
++ */
++struct nbio_hdp_flush_reg {
++	u32 ref_and_mask_cp0;
++	u32 ref_and_mask_cp1;
++	u32 ref_and_mask_cp2;
++	u32 ref_and_mask_cp3;
++	u32 ref_and_mask_cp4;
++	u32 ref_and_mask_cp5;
++	u32 ref_and_mask_cp6;
++	u32 ref_and_mask_cp7;
++	u32 ref_and_mask_cp8;
++	u32 ref_and_mask_cp9;
++	u32 ref_and_mask_sdma0;
++	u32 ref_and_mask_sdma1;
++	u32 ref_and_mask_sdma2;
++	u32 ref_and_mask_sdma3;
++	u32 ref_and_mask_sdma4;
++	u32 ref_and_mask_sdma5;
++	u32 ref_and_mask_sdma6;
++	u32 ref_and_mask_sdma7;
++};
++
++struct amdgpu_nbio_funcs {
++	const struct nbio_hdp_flush_reg *hdp_flush_reg;
++	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
++	u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
++	u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
++	u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
++	u32 (*get_rev_id)(struct amdgpu_device *adev);
++	void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
++	void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
++	u32 (*get_memsize)(struct amdgpu_device *adev);
++	void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
++			bool use_doorbell, int doorbell_index, int doorbell_size);
++	void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
++				   int doorbell_index, int instance);
++	void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
++					 bool enable);
++	void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
++						  bool enable);
++	void (*ih_doorbell_range)(struct amdgpu_device *adev,
++				  bool use_doorbell, int doorbell_index);
++	void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
++						 bool enable);
++	void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
++						bool enable);
++	void (*get_clockgating_state)(struct amdgpu_device *adev,
++				      u32 *flags);
++	void (*ih_control)(struct amdgpu_device *adev);
++	void (*init_registers)(struct amdgpu_device *adev);
++	void (*detect_hw_virt)(struct amdgpu_device *adev);
++	void (*remap_hdp_registers)(struct amdgpu_device *adev);
++};
++
++struct amdgpu_nbio {
++	const struct nbio_hdp_flush_reg *hdp_flush_reg;
++	const struct amdgpu_nbio_funcs *funcs;
++};
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3656-drm-amdgpu-switch-to-new-amdgpu_nbio-structure.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3656-drm-amdgpu-switch-to-new-amdgpu_nbio-structure.patch
new file mode 100644
index 00000000..f4c83659
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3656-drm-amdgpu-switch-to-new-amdgpu_nbio-structure.patch
@@ -0,0 +1,955 @@
+From dea9d05135ec1a2e0e0f4a4ed29a4c3a0a1382a7 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Fri, 23 Aug 2019 19:39:18 +0800
+Subject: [PATCH 3656/4256] drm/amdgpu: switch to new amdgpu_nbio structure
+
+no functional change, just switch to new structures
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h           | 63 ++--------------
+ drivers/gpu/drm/amd/amdgpu/df_v3_6.c          | 16 ++---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c        | 14 ++--
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c         |  6 +-
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c        |  6 +-
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c         |  4 +-
+ drivers/gpu/drm/amd/amdgpu/navi10_ih.c        |  4 +-
+ drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c        |  1 -
+ drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h        |  1 +
+ drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c        |  3 +-
+ drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h        |  1 +
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c        |  1 -
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h        |  1 +
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c        |  3 +-
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h        |  1 +
+ drivers/gpu/drm/amd/amdgpu/nv.c               | 34 ++++-----
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c        |  6 +-
+ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c        |  8 +--
+ drivers/gpu/drm/amd/amdgpu/soc15.c            | 71 ++++++++++---------
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c         |  2 +-
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c         |  2 +-
+ drivers/gpu/drm/amd/amdgpu/vega10_ih.c        |  2 +-
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  2 +-
+ .../drm/amd/powerplay/smumgr/smu10_smumgr.c   |  2 +-
+ .../drm/amd/powerplay/smumgr/vega10_smumgr.c  |  2 +-
+ .../drm/amd/powerplay/smumgr/vega12_smumgr.c  |  2 +-
+ .../drm/amd/powerplay/smumgr/vega20_smumgr.c  |  4 +-
+ 27 files changed, 108 insertions(+), 154 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 02bd4e99906f..178039b28651 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -74,6 +74,7 @@
+ #include "amdgpu_gmc.h"
+ #include "amdgpu_gfx.h"
+ #include "amdgpu_sdma.h"
++#include "amdgpu_nbio.h"
+ #include "amdgpu_dm.h"
+ #include "amdgpu_virt.h"
+ #include "amdgpu_csa.h"
+@@ -660,69 +661,11 @@ typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
+ typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
+ typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
+ 
+-
+-/*
+- * amdgpu nbio functions
+- *
+- */
+-struct nbio_hdp_flush_reg {
+-	u32 ref_and_mask_cp0;
+-	u32 ref_and_mask_cp1;
+-	u32 ref_and_mask_cp2;
+-	u32 ref_and_mask_cp3;
+-	u32 ref_and_mask_cp4;
+-	u32 ref_and_mask_cp5;
+-	u32 ref_and_mask_cp6;
+-	u32 ref_and_mask_cp7;
+-	u32 ref_and_mask_cp8;
+-	u32 ref_and_mask_cp9;
+-	u32 ref_and_mask_sdma0;
+-	u32 ref_and_mask_sdma1;
+-	u32 ref_and_mask_sdma2;
+-	u32 ref_and_mask_sdma3;
+-	u32 ref_and_mask_sdma4;
+-	u32 ref_and_mask_sdma5;
+-	u32 ref_and_mask_sdma6;
+-	u32 ref_and_mask_sdma7;
+-};
+-
+ struct amdgpu_mmio_remap {
+ 	u32 reg_offset;
+ 	resource_size_t bus_addr;
+ };
+ 
+-struct amdgpu_nbio_funcs {
+-	const struct nbio_hdp_flush_reg *hdp_flush_reg;
+-	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
+-	u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
+-	u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
+-	u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
+-	u32 (*get_rev_id)(struct amdgpu_device *adev);
+-	void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
+-	void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
+-	u32 (*get_memsize)(struct amdgpu_device *adev);
+-	void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
+-			bool use_doorbell, int doorbell_index, int doorbell_size);
+-	void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
+-				   int doorbell_index, int instance);
+-	void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
+-					 bool enable);
+-	void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
+-						  bool enable);
+-	void (*ih_doorbell_range)(struct amdgpu_device *adev,
+-				  bool use_doorbell, int doorbell_index);
+-	void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
+-						 bool enable);
+-	void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
+-						bool enable);
+-	void (*get_clockgating_state)(struct amdgpu_device *adev,
+-				      u32 *flags);
+-	void (*ih_control)(struct amdgpu_device *adev);
+-	void (*init_registers)(struct amdgpu_device *adev);
+-	void (*detect_hw_virt)(struct amdgpu_device *adev);
+-	void (*remap_hdp_registers)(struct amdgpu_device *adev);
+-};
+-
+ struct amdgpu_df_funcs {
+ 	void (*sw_init)(struct amdgpu_device *adev);
+ 	void (*enable_broadcast_mode)(struct amdgpu_device *adev,
+@@ -962,6 +905,9 @@ struct amdgpu_device {
+ 	u32				cg_flags;
+ 	u32				pg_flags;
+ 
++	/* nbio */
++	struct amdgpu_nbio		nbio;
++
+ 	/* gfx */
+ 	struct amdgpu_gfx		gfx;
+ 
+@@ -1015,7 +961,6 @@ struct amdgpu_device {
+ 	/* soc15 register offset based on ip, instance and  segment */
+ 	uint32_t 		*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
+ 
+-	const struct amdgpu_nbio_funcs	*nbio_funcs;
+ 	const struct amdgpu_df_funcs	*df_funcs;
+ 	const struct amdgpu_mmhub_funcs	*mmhub_funcs;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+index 47ba0b31a8a4..7f7896a69d53 100644
+--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
++++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+@@ -99,8 +99,8 @@ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
+ 	unsigned long flags, address, data;
+ 	uint32_t ficadl_val, ficadh_val;
+ 
+-	address = adev->nbio_funcs->get_pcie_index_offset(adev);
+-	data = adev->nbio_funcs->get_pcie_data_offset(adev);
++	address = adev->nbio.funcs->get_pcie_index_offset(adev);
++	data = adev->nbio.funcs->get_pcie_data_offset(adev);
+ 
+ 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ 	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
+@@ -122,8 +122,8 @@ static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
+ {
+ 	unsigned long flags, address, data;
+ 
+-	address = adev->nbio_funcs->get_pcie_index_offset(adev);
+-	data = adev->nbio_funcs->get_pcie_data_offset(adev);
++	address = adev->nbio.funcs->get_pcie_index_offset(adev);
++	data = adev->nbio.funcs->get_pcie_data_offset(adev);
+ 
+ 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ 	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
+@@ -150,8 +150,8 @@ static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev,
+ {
+ 	unsigned long flags, address, data;
+ 
+-	address = adev->nbio_funcs->get_pcie_index_offset(adev);
+-	data = adev->nbio_funcs->get_pcie_data_offset(adev);
++	address = adev->nbio.funcs->get_pcie_index_offset(adev);
++	data = adev->nbio.funcs->get_pcie_data_offset(adev);
+ 
+ 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ 	WREG32(address, lo_addr);
+@@ -172,8 +172,8 @@ static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr,
+ {
+ 	unsigned long flags, address, data;
+ 
+-	address = adev->nbio_funcs->get_pcie_index_offset(adev);
+-	data = adev->nbio_funcs->get_pcie_data_offset(adev);
++	address = adev->nbio.funcs->get_pcie_index_offset(adev);
++	data = adev->nbio.funcs->get_pcie_data_offset(adev);
+ 
+ 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ 	WREG32(address, lo_addr);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index c3b48ac398a5..082a0b3298a9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -2409,7 +2409,7 @@ static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
+ 	}
+ 
+ 	if (amdgpu_emu_mode == 1)
+-		adev->nbio_funcs->hdp_flush(adev, NULL);
++		adev->nbio.funcs->hdp_flush(adev, NULL);
+ 
+ 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
+ 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
+@@ -2479,7 +2479,7 @@ static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
+ 	}
+ 
+ 	if (amdgpu_emu_mode == 1)
+-		adev->nbio_funcs->hdp_flush(adev, NULL);
++		adev->nbio.funcs->hdp_flush(adev, NULL);
+ 
+ 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
+ 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
+@@ -2548,7 +2548,7 @@ static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
+ 	}
+ 
+ 	if (amdgpu_emu_mode == 1)
+-		adev->nbio_funcs->hdp_flush(adev, NULL);
++		adev->nbio.funcs->hdp_flush(adev, NULL);
+ 
+ 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
+ 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
+@@ -2869,7 +2869,7 @@ static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
+         }
+ 
+ 	if (amdgpu_emu_mode == 1)
+-		adev->nbio_funcs->hdp_flush(adev, NULL);
++		adev->nbio.funcs->hdp_flush(adev, NULL);
+ 
+ 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
+ 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
+@@ -4323,7 +4323,7 @@ static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 	u32 ref_and_mask, reg_mem_engine;
+-	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
++	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
+ 
+ 	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
+ 		switch (ring->me) {
+@@ -4343,8 +4343,8 @@ static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+ 	}
+ 
+ 	gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
+-			       adev->nbio_funcs->get_hdp_flush_req_offset(adev),
+-			       adev->nbio_funcs->get_hdp_flush_done_offset(adev),
++			       adev->nbio.funcs->get_hdp_flush_req_offset(adev),
++			       adev->nbio.funcs->get_hdp_flush_done_offset(adev),
+ 			       ref_and_mask, ref_and_mask, 0x20);
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index fd7947ef4c24..78fea99c0d0a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4970,7 +4970,7 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 	u32 ref_and_mask, reg_mem_engine;
+-	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
++	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
+ 
+ 	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
+ 		switch (ring->me) {
+@@ -4990,8 +4990,8 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+ 	}
+ 
+ 	gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
+-			      adev->nbio_funcs->get_hdp_flush_req_offset(adev),
+-			      adev->nbio_funcs->get_hdp_flush_done_offset(adev),
++			      adev->nbio.funcs->get_hdp_flush_req_offset(adev),
++			      adev->nbio.funcs->get_hdp_flush_done_offset(adev),
+ 			      ref_and_mask, ref_and_mask, 0x20);
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index 56f76a1f32ee..46efd4d17a34 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -277,7 +277,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
+ 	int r;
+ 
+ 	/* flush hdp cache */
+-	adev->nbio_funcs->hdp_flush(adev, NULL);
++	adev->nbio.funcs->hdp_flush(adev, NULL);
+ 
+ 	mutex_lock(&adev->mman.gtt_window_lock);
+ 
+@@ -557,7 +557,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
+ 
+ 	/* size in MB on si */
+ 	adev->gmc.mc_vram_size =
+-		adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
++		adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
+ 	adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
+ 	adev->gmc.visible_vram_size = adev->gmc.aper_size;
+ 
+@@ -811,7 +811,7 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
+ 	WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
+ 
+ 	/* Flush HDP after it is initialized */
+-	adev->nbio_funcs->hdp_flush(adev, NULL);
++	adev->nbio.funcs->hdp_flush(adev, NULL);
+ 
+ 	value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
+ 		false : true;
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index a22fbb8fe1a5..b97ea92bda51 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -992,7 +992,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
+ 
+ 	/* size in MB on si */
+ 	adev->gmc.mc_vram_size =
+-		adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
++		adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
+ 	adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
+ 
+ 	if (!(adev->flags & AMD_IS_APU)) {
+@@ -1370,7 +1370,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
+ 	WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
+ 
+ 	/* After HDP is initialized, flush HDP.*/
+-	adev->nbio_funcs->hdp_flush(adev, NULL);
++	adev->nbio.funcs->hdp_flush(adev, NULL);
+ 
+ 	if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
+ 		value = false;
+diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+index e963746be11c..7dc94e730efb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
++++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+@@ -116,7 +116,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
+ 	/* disable irqs */
+ 	navi10_ih_disable_interrupts(adev);
+ 
+-	adev->nbio_funcs->ih_control(adev);
++	adev->nbio.funcs->ih_control(adev);
+ 
+ 	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
+ 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8);
+@@ -161,7 +161,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
+ 	}
+ 	WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
+ 
+-	adev->nbio_funcs->ih_doorbell_range(adev, ih->use_doorbell,
++	adev->nbio.funcs->ih_doorbell_range(adev, ih->use_doorbell,
+ 					    ih->doorbell_index);
+ 
+ 	tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+index f5611c479e28..a5fa741e4aff 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+@@ -311,7 +311,6 @@ static void nbio_v2_3_init_registers(struct amdgpu_device *adev)
+ }
+ 
+ const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
+-	.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg,
+ 	.get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset,
+ 	.get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset,
+ 	.get_pcie_index_offset = nbio_v2_3_get_pcie_index_offset,
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h
+index 5ae52085f6b7..a43b60acf7f6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.h
+@@ -26,6 +26,7 @@
+ 
+ #include "soc15_common.h"
+ 
++extern const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg;
+ extern const struct amdgpu_nbio_funcs nbio_v2_3_funcs;
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+index 6590143c3f75..635d9e1fc0a3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+@@ -226,7 +226,7 @@ static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev)
+ 	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
+ }
+ 
+-static const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
++const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
+ 	.ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
+ 	.ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
+ 	.ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
+@@ -277,7 +277,6 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
+ }
+ 
+ const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
+-	.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg,
+ 	.get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
+ 	.get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
+ 	.get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset,
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
+index 0743a6f016f3..6dc743b73218 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
+@@ -26,6 +26,7 @@
+ 
+ #include "soc15_common.h"
+ 
++extern const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
+ extern const struct amdgpu_nbio_funcs nbio_v6_1_funcs;
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+index 6f3b55d0aa3c..c8eadaa17e95 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+@@ -308,7 +308,6 @@ static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
+ }
+ 
+ const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
+-	.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg,
+ 	.get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
+ 	.get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
+ 	.get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset,
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
+index 508d549c5029..e7aefb252550 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
+@@ -26,6 +26,7 @@
+ 
+ #include "soc15_common.h"
+ 
++extern const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg;
+ extern const struct amdgpu_nbio_funcs nbio_v7_0_funcs;
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index 910fffced43b..c416ab8ab1c3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -266,7 +266,7 @@ static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev)
+ 	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
+ }
+ 
+-static const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
++const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
+ 	.ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
+ 	.ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
+ 	.ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
+@@ -316,7 +316,6 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
+ }
+ 
+ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+-	.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg,
+ 	.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
+ 	.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
+ 	.get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset,
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
+index c442865bac4f..b1ac82872752 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h
+@@ -26,6 +26,7 @@
+ 
+ #include "soc15_common.h"
+ 
++extern const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg;
+ extern const struct amdgpu_nbio_funcs nbio_v7_4_funcs;
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 323af1ecfe9c..585fc7dce39d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -45,6 +45,7 @@
+ #include "gmc_v10_0.h"
+ #include "gfxhub_v2_0.h"
+ #include "mmhub_v2_0.h"
++#include "nbio_v2_3.h"
+ #include "nv.h"
+ #include "navi10_ih.h"
+ #include "gfx_v10_0.h"
+@@ -62,8 +63,8 @@ static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
+ {
+ 	unsigned long flags, address, data;
+ 	u32 r;
+-	address = adev->nbio_funcs->get_pcie_index_offset(adev);
+-	data = adev->nbio_funcs->get_pcie_data_offset(adev);
++	address = adev->nbio.funcs->get_pcie_index_offset(adev);
++	data = adev->nbio.funcs->get_pcie_data_offset(adev);
+ 
+ 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ 	WREG32(address, reg);
+@@ -77,8 +78,8 @@ static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+ {
+ 	unsigned long flags, address, data;
+ 
+-	address = adev->nbio_funcs->get_pcie_index_offset(adev);
+-	data = adev->nbio_funcs->get_pcie_data_offset(adev);
++	address = adev->nbio.funcs->get_pcie_index_offset(adev);
++	data = adev->nbio.funcs->get_pcie_data_offset(adev);
+ 
+ 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ 	WREG32(address, reg);
+@@ -118,7 +119,7 @@ static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+ 
+ static u32 nv_get_config_memsize(struct amdgpu_device *adev)
+ {
+-	return adev->nbio_funcs->get_memsize(adev);
++	return adev->nbio.funcs->get_memsize(adev);
+ }
+ 
+ static u32 nv_get_xclk(struct amdgpu_device *adev)
+@@ -278,7 +279,7 @@ static int nv_asic_mode1_reset(struct amdgpu_device *adev)
+ 
+ 	/* wait for asic to come out of reset */
+ 	for (i = 0; i < adev->usec_timeout; i++) {
+-		u32 memsize = adev->nbio_funcs->get_memsize(adev);
++		u32 memsize = adev->nbio.funcs->get_memsize(adev);
+ 
+ 		if (memsize != 0xffffffff)
+ 			break;
+@@ -365,8 +366,8 @@ static void nv_program_aspm(struct amdgpu_device *adev)
+ static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
+ 					bool enable)
+ {
+-	adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
+-	adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
++	adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
++	adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
+ }
+ 
+ static const struct amdgpu_ip_block_version nv_common_ip_block =
+@@ -420,9 +421,10 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ 	if (r)
+ 		return r;
+ 
+-	adev->nbio_funcs = &nbio_v2_3_funcs;
++	adev->nbio.funcs = &nbio_v2_3_funcs;
++	adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
+ 
+-	adev->nbio_funcs->detect_hw_virt(adev);
++	adev->nbio.funcs->detect_hw_virt(adev);
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+@@ -477,12 +479,12 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ 
+ static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
+ {
+-	return adev->nbio_funcs->get_rev_id(adev);
++	return adev->nbio.funcs->get_rev_id(adev);
+ }
+ 
+ static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
+ {
+-	adev->nbio_funcs->hdp_flush(adev, ring);
++	adev->nbio.funcs->hdp_flush(adev, ring);
+ }
+ 
+ static void nv_invalidate_hdp(struct amdgpu_device *adev,
+@@ -689,7 +691,7 @@ static int nv_common_hw_init(void *handle)
+ 	/* enable aspm */
+ 	nv_program_aspm(adev);
+ 	/* setup nbio registers */
+-	adev->nbio_funcs->init_registers(adev);
++	adev->nbio.funcs->init_registers(adev);
+ 	/* enable the doorbell aperture */
+ 	nv_enable_doorbell_aperture(adev, true);
+ 
+@@ -851,9 +853,9 @@ static int nv_common_set_clockgating_state(void *handle,
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+ 	case CHIP_NAVI12:
+-		adev->nbio_funcs->update_medium_grain_clock_gating(adev,
++		adev->nbio.funcs->update_medium_grain_clock_gating(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+-		adev->nbio_funcs->update_medium_grain_light_sleep(adev,
++		adev->nbio.funcs->update_medium_grain_light_sleep(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+ 		nv_update_hdp_mem_power_gating(adev,
+ 				   state == AMD_CG_STATE_GATE ? true : false);
+@@ -881,7 +883,7 @@ static void nv_common_get_clockgating_state(void *handle, u32 *flags)
+ 	if (amdgpu_sriov_vf(adev))
+ 		*flags = 0;
+ 
+-	adev->nbio_funcs->get_clockgating_state(adev, flags);
++	adev->nbio.funcs->get_clockgating_state(adev, flags);
+ 
+ 	/* AMD_CG_SUPPORT_HDP_MGCG */
+ 	tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index b41e21e67791..5e5b6a3cda2c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -743,13 +743,13 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 	u32 ref_and_mask = 0;
+-	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
++	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
+ 
+ 	ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
+ 
+ 	sdma_v4_0_wait_reg_mem(ring, 0, 1,
+-			       adev->nbio_funcs->get_hdp_flush_done_offset(adev),
+-			       adev->nbio_funcs->get_hdp_flush_req_offset(adev),
++			       adev->nbio.funcs->get_hdp_flush_done_offset(adev),
++			       adev->nbio.funcs->get_hdp_flush_req_offset(adev),
+ 			       ref_and_mask, ref_and_mask, 10);
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+index 89174e778d2f..ad5c3566337c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+@@ -403,7 +403,7 @@ static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 	u32 ref_and_mask = 0;
+-	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
++	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
+ 
+ 	if (ring->me == 0)
+ 		ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
+@@ -413,8 +413,8 @@ static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+ 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
+ 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
+ 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
+-	amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_done_offset(adev)) << 2);
+-	amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_req_offset(adev)) << 2);
++	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
++	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
+ 	amdgpu_ring_write(ring, ref_and_mask); /* reference */
+ 	amdgpu_ring_write(ring, ref_and_mask); /* mask */
+ 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
+@@ -680,7 +680,7 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
+ 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
+ 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
+ 
+-		adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
++		adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
+ 						      ring->doorbell_index, 20);
+ 
+ 		if (amdgpu_sriov_vf(adev))
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 98cdf3eccaec..ae25b0928f3f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -57,6 +57,9 @@
+ #include "mmhub_v1_0.h"
+ #include "df_v1_7.h"
+ #include "df_v3_6.h"
++#include "nbio_v6_1.h"
++#include "nbio_v7_0.h"
++#include "nbio_v7_4.h"
+ #include "vega10_ih.h"
+ #include "sdma_v4_0.h"
+ #include "uvd_v7_0.h"
+@@ -90,8 +93,8 @@ static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
+ {
+ 	unsigned long flags, address, data;
+ 	u32 r;
+-	address = adev->nbio_funcs->get_pcie_index_offset(adev);
+-	data = adev->nbio_funcs->get_pcie_data_offset(adev);
++	address = adev->nbio.funcs->get_pcie_index_offset(adev);
++	data = adev->nbio.funcs->get_pcie_data_offset(adev);
+ 
+ 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ 	WREG32(address, reg);
+@@ -105,8 +108,8 @@ static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+ {
+ 	unsigned long flags, address, data;
+ 
+-	address = adev->nbio_funcs->get_pcie_index_offset(adev);
+-	data = adev->nbio_funcs->get_pcie_data_offset(adev);
++	address = adev->nbio.funcs->get_pcie_index_offset(adev);
++	data = adev->nbio.funcs->get_pcie_data_offset(adev);
+ 
+ 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ 	WREG32(address, reg);
+@@ -120,8 +123,8 @@ static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
+ {
+ 	unsigned long flags, address, data;
+ 	u64 r;
+-	address = adev->nbio_funcs->get_pcie_index_offset(adev);
+-	data = adev->nbio_funcs->get_pcie_data_offset(adev);
++	address = adev->nbio.funcs->get_pcie_index_offset(adev);
++	data = adev->nbio.funcs->get_pcie_data_offset(adev);
+ 
+ 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ 	/* read low 32 bit */
+@@ -141,8 +144,8 @@ static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
+ {
+ 	unsigned long flags, address, data;
+ 
+-	address = adev->nbio_funcs->get_pcie_index_offset(adev);
+-	data = adev->nbio_funcs->get_pcie_data_offset(adev);
++	address = adev->nbio.funcs->get_pcie_index_offset(adev);
++	data = adev->nbio.funcs->get_pcie_data_offset(adev);
+ 
+ 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ 	/* write low 32 bit */
+@@ -261,7 +264,7 @@ static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+ 
+ static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
+ {
+-	return adev->nbio_funcs->get_memsize(adev);
++	return adev->nbio.funcs->get_memsize(adev);
+ }
+ 
+ static u32 soc15_get_xclk(struct amdgpu_device *adev)
+@@ -460,7 +463,7 @@ static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
+ 
+ 	/* wait for asic to come out of reset */
+ 	for (i = 0; i < adev->usec_timeout; i++) {
+-		u32 memsize = adev->nbio_funcs->get_memsize(adev);
++		u32 memsize = adev->nbio.funcs->get_memsize(adev);
+ 
+ 		if (memsize != 0xffffffff)
+ 			break;
+@@ -623,8 +626,8 @@ static void soc15_program_aspm(struct amdgpu_device *adev)
+ static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
+ 					   bool enable)
+ {
+-	adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
+-	adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
++	adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
++	adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
+ }
+ 
+ static const struct amdgpu_ip_block_version vega10_common_ip_block =
+@@ -638,7 +641,7 @@ static const struct amdgpu_ip_block_version vega10_common_ip_block =
+ 
+ static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
+ {
+-	return adev->nbio_funcs->get_rev_id(adev);
++	return adev->nbio.funcs->get_rev_id(adev);
+ }
+ 
+ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+@@ -664,13 +667,17 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ 	if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
+ 		adev->gmc.xgmi.supported = true;
+ 
+-	if (adev->flags & AMD_IS_APU)
+-		adev->nbio_funcs = &nbio_v7_0_funcs;
+-	else if (adev->asic_type == CHIP_VEGA20 ||
+-		adev->asic_type == CHIP_ARCTURUS)
+-		adev->nbio_funcs = &nbio_v7_4_funcs;
+-	else
+-		adev->nbio_funcs = &nbio_v6_1_funcs;
++	if (adev->flags & AMD_IS_APU) {
++		adev->nbio.funcs = &nbio_v7_0_funcs;
++		adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
++	} else if (adev->asic_type == CHIP_VEGA20 ||
++		   adev->asic_type == CHIP_ARCTURUS) {
++		adev->nbio.funcs = &nbio_v7_4_funcs;
++		adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
++	} else {
++		adev->nbio.funcs = &nbio_v6_1_funcs;
++		adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
++	}
+ 
+ 	if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
+ 		adev->df_funcs = &df_v3_6_funcs;
+@@ -678,7 +685,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ 		adev->df_funcs = &df_v1_7_funcs;
+ 
+ 	adev->rev_id = soc15_get_rev_id(adev);
+-	adev->nbio_funcs->detect_hw_virt(adev);
++	adev->nbio.funcs->detect_hw_virt(adev);
+ 
+ 	if (amdgpu_sriov_vf(adev))
+ 		adev->virt.ops = &xgpu_ai_virt_ops;
+@@ -784,7 +791,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ 
+ static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
+ {
+-	adev->nbio_funcs->hdp_flush(adev, ring);
++	adev->nbio.funcs->hdp_flush(adev, ring);
+ }
+ 
+ static void soc15_invalidate_hdp(struct amdgpu_device *adev,
+@@ -1240,12 +1247,12 @@ static void soc15_doorbell_range_init(struct amdgpu_device *adev)
+ 	if (!amdgpu_sriov_vf(adev)) {
+ 		for (i = 0; i < adev->sdma.num_instances; i++) {
+ 			ring = &adev->sdma.instance[i].ring;
+-			adev->nbio_funcs->sdma_doorbell_range(adev, i,
++			adev->nbio.funcs->sdma_doorbell_range(adev, i,
+ 				ring->use_doorbell, ring->doorbell_index,
+ 				adev->doorbell_index.sdma_doorbell_range);
+ 		}
+ 
+-		adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
++		adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
+ 						adev->irq.ih.doorbell_index);
+ 	}
+ }
+@@ -1259,13 +1266,13 @@ static int soc15_common_hw_init(void *handle)
+ 	/* enable aspm */
+ 	soc15_program_aspm(adev);
+ 	/* setup nbio registers */
+-	adev->nbio_funcs->init_registers(adev);
++	adev->nbio.funcs->init_registers(adev);
+ 	/* remap HDP registers to a hole in mmio space,
+ 	 * for the purpose of expose those registers
+ 	 * to process space
+ 	 */
+-	if (adev->nbio_funcs->remap_hdp_registers)
+-		adev->nbio_funcs->remap_hdp_registers(adev);
++	if (adev->nbio.funcs->remap_hdp_registers)
++		adev->nbio.funcs->remap_hdp_registers(adev);
+ 
+ 	/* enable the doorbell aperture */
+ 	soc15_enable_doorbell_aperture(adev, true);
+@@ -1428,9 +1435,9 @@ static int soc15_common_set_clockgating_state(void *handle,
+ 	case CHIP_VEGA10:
+ 	case CHIP_VEGA12:
+ 	case CHIP_VEGA20:
+-		adev->nbio_funcs->update_medium_grain_clock_gating(adev,
++		adev->nbio.funcs->update_medium_grain_clock_gating(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+-		adev->nbio_funcs->update_medium_grain_light_sleep(adev,
++		adev->nbio.funcs->update_medium_grain_light_sleep(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+ 		soc15_update_hdp_light_sleep(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+@@ -1445,9 +1452,9 @@ static int soc15_common_set_clockgating_state(void *handle,
+ 		break;
+ 	case CHIP_RAVEN:
+ 	case CHIP_RENOIR:
+-		adev->nbio_funcs->update_medium_grain_clock_gating(adev,
++		adev->nbio.funcs->update_medium_grain_clock_gating(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+-		adev->nbio_funcs->update_medium_grain_light_sleep(adev,
++		adev->nbio.funcs->update_medium_grain_light_sleep(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+ 		soc15_update_hdp_light_sleep(adev,
+ 				state == AMD_CG_STATE_GATE ? true : false);
+@@ -1476,7 +1483,7 @@ static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
+ 	if (amdgpu_sriov_vf(adev))
+ 		*flags = 0;
+ 
+-	adev->nbio_funcs->get_clockgating_state(adev, flags);
++	adev->nbio.funcs->get_clockgating_state(adev, flags);
+ 
+ 	/* AMD_CG_SUPPORT_HDP_LS */
+ 	data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+index 7528b1b562e1..5a590064bfff 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+@@ -244,7 +244,7 @@ static int vcn_v2_0_hw_init(void *handle)
+ 	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
+ 	int i, r;
+ 
+-	adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell,
++	adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+ 					     ring->doorbell_index, 0);
+ 
+ 	ring->sched.ready = true;
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index 0c84dbc6a62d..247cf7e71e1b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -255,7 +255,7 @@ static int vcn_v2_5_hw_init(void *handle)
+ 			continue;
+ 		ring = &adev->vcn.inst[j].ring_dec;
+ 
+-		adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell,
++		adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+ 						     ring->doorbell_index, j);
+ 
+ 		r = amdgpu_ring_test_ring(ring);
+diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+index f19268aea38d..d92ff25f1ed3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
++++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+@@ -224,7 +224,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
+ 	/* disable irqs */
+ 	vega10_ih_disable_interrupts(adev);
+ 
+-	adev->nbio_funcs->ih_control(adev);
++	adev->nbio.funcs->ih_control(adev);
+ 
+ 	ih = &adev->irq.ih;
+ 	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index a65c9297e7bd..797441894c2f 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -460,7 +460,7 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int
+ 		return ret;
+ 
+ 	/* flush hdp cache */
+-	adev->nbio_funcs->hdp_flush(adev, NULL);
++	adev->nbio.funcs->hdp_flush(adev, NULL);
+ 
+ 	if (!drv2smu)
+ 		memcpy(table_data, table->cpu_addr, table->size);
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
+index 59b11ac5b53b..c2131e930051 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
+@@ -135,7 +135,7 @@ static int smu10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
+ 			priv->smu_tables.entry[table_id].table_id);
+ 
+ 	/* flush hdp cache */
+-	adev->nbio_funcs->hdp_flush(adev, NULL);
++	adev->nbio.funcs->hdp_flush(adev, NULL);
+ 
+ 	memcpy(table, (uint8_t *)priv->smu_tables.entry[table_id].table,
+ 			priv->smu_tables.entry[table_id].size);
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+index 8e07fc1fb9ce..eb024fe606f2 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+@@ -56,7 +56,7 @@ static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
+ 			priv->smu_tables.entry[table_id].table_id);
+ 
+ 	/* flush hdp cache */
+-	adev->nbio_funcs->hdp_flush(adev, NULL);
++	adev->nbio.funcs->hdp_flush(adev, NULL);
+ 
+ 	memcpy(table, priv->smu_tables.entry[table_id].table,
+ 			priv->smu_tables.entry[table_id].size);
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
+index c11dae720a35..cd7058b04f5e 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
+@@ -66,7 +66,7 @@ static int vega12_copy_table_from_smc(struct pp_hwmgr *hwmgr,
+ 			return -EINVAL);
+ 
+ 	/* flush hdp cache */
+-	adev->nbio_funcs->hdp_flush(adev, NULL);
++	adev->nbio.funcs->hdp_flush(adev, NULL);
+ 
+ 	memcpy(table, priv->smu_tables.entry[table_id].table,
+ 			priv->smu_tables.entry[table_id].size);
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
+index b9089c6bea85..f604612f411f 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
+@@ -189,7 +189,7 @@ static int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr,
+ 			return ret);
+ 
+ 	/* flush hdp cache */
+-	adev->nbio_funcs->hdp_flush(adev, NULL);
++	adev->nbio.funcs->hdp_flush(adev, NULL);
+ 
+ 	memcpy(table, priv->smu_tables.entry[table_id].table,
+ 			priv->smu_tables.entry[table_id].size);
+@@ -290,7 +290,7 @@ int vega20_get_activity_monitor_coeff(struct pp_hwmgr *hwmgr,
+ 			return ret);
+ 
+ 	/* flush hdp cache */
+-	adev->nbio_funcs->hdp_flush(adev, NULL);
++	adev->nbio.funcs->hdp_flush(adev, NULL);
+ 
+ 	memcpy(table, priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table,
+ 			priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].size);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3657-drm-amdgpu-nbio-add-functions-to-query-ras-specific-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3657-drm-amdgpu-nbio-add-functions-to-query-ras-specific-.patch
new file mode 100644
index 00000000..897ecf20
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3657-drm-amdgpu-nbio-add-functions-to-query-ras-specific-.patch
@@ -0,0 +1,82 @@
+From cc0ce0007f8ee6749ec5e6ed63532fbfa65c1305 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 30 May 2019 11:57:20 +0800
+Subject: [PATCH 3657/4256] drm/amdgpu/nbio: add functions to query ras
+ specific interrupt status
+
+ras_controller_interrupt and err_event_interrupt are ras specific interrupts.
+add functions to check their status and ack them if they are generated. both
+funcitons should only be invoked in ISR when BIF ring is disabled or even not
+initialized.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h |  2 ++
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c   | 32 ++++++++++++++++++++++++
+ 2 files changed, 34 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+index 0563476b1242..28417e485c58 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+@@ -77,6 +77,8 @@ struct amdgpu_nbio_funcs {
+ 	void (*init_registers)(struct amdgpu_device *adev);
+ 	void (*detect_hw_virt)(struct amdgpu_device *adev);
+ 	void (*remap_hdp_registers)(struct amdgpu_device *adev);
++	void (*handle_ras_controller_intr_no_bifring)(struct amdgpu_device *adev);
++	void (*handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device *adev);
+ };
+ 
+ struct amdgpu_nbio {
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index c416ab8ab1c3..6ecdd5e3ca3f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -315,6 +315,36 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
+ 		WREG32_PCIE(smnPCIE_CI_CNTL, data);
+ }
+ 
++static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
++{
++	uint32_t bif_doorbell_intr_cntl;
++
++	bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
++	if (REG_GET_FIELD(bif_doorbell_intr_cntl,
++		BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
++		/* driver has to clear the interrupt status when bif ring is disabled */
++		bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
++						BIF_DOORBELL_INT_CNTL,
++						RAS_CNTLR_INTERRUPT_CLEAR, 1);
++		WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
++	}
++}
++
++static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev)
++{
++	uint32_t bif_doorbell_intr_cntl;
++
++	bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
++	if (REG_GET_FIELD(bif_doorbell_intr_cntl,
++		BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) {
++		/* driver has to clear the interrupt status when bif ring is disabled */
++		bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
++						BIF_DOORBELL_INT_CNTL,
++						RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);
++		WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
++	}
++}
++
+ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ 	.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
+ 	.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
+@@ -336,4 +366,6 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ 	.init_registers = nbio_v7_4_init_registers,
+ 	.detect_hw_virt = nbio_v7_4_detect_hw_virt,
+ 	.remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
++	.handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring,
++	.handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3658-drm-amdgpu-add-nbif-v7_4-irq-source-header-for-vega2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3658-drm-amdgpu-add-nbif-v7_4-irq-source-header-for-vega2.patch
new file mode 100644
index 00000000..6b0ffeed
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3658-drm-amdgpu-add-nbif-v7_4-irq-source-header-for-vega2.patch
@@ -0,0 +1,66 @@
+From 602d260605221dcfefe3003c58edc2efdbeca7c9 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 29 May 2019 14:00:19 +0800
+Subject: [PATCH 3658/4256] drm/amdgpu: add nbif v7_4 irq source header for
+ vega20
+
+nbif v7_4 interrupt source definition
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../include/ivsrcid/nbio/irqsrcs_nbif_7_4.h   | 42 +++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/nbio/irqsrcs_nbif_7_4.h
+
+diff --git a/drivers/gpu/drm/amd/include/ivsrcid/nbio/irqsrcs_nbif_7_4.h b/drivers/gpu/drm/amd/include/ivsrcid/nbio/irqsrcs_nbif_7_4.h
+new file mode 100644
+index 000000000000..79af4258f259
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/ivsrcid/nbio/irqsrcs_nbif_7_4.h
+@@ -0,0 +1,42 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __IRQSRCS_NBIF_7_4_H__
++#define __IRQSRCS_NBIF_7_4_H__
++
++#define NBIF_7_4__SRCID__CHIP_ERR_INT_EVENT            0x5E        // Error generated
++#define NBIF_7_4__SRCID__DOORBELL_INTERRUPT            0x5F        // Interrupt for doorbell event during VDDGFX off
++#define NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT      0x60        // Interrupt for ras_intr_valid from RAS controller
++#define NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT      0x61        // Interrupt for SDP ErrEvent received from ATHUB
++#define NBIF_7_4__SRCID__PF_VF_MSGBUF_VALID            0x87        // Valid message in PF->VF mailbox message buffer (The interrupt is sent on behalf of PF)
++#define NBIF_7_4__SRCID__PF_VF_MSGBUF_ACK              0x88        // Acknowledge message in PF->VF mailbox message buffer (The interrupt is sent on behalf of VF)
++#define NBIF_7_4__SRCID__VF_PF_MSGBUF_VALID            0x89        // Valid message in VF->PF mailbox message buffer (The interrupt is sent on behalf of VF)
++#define NBIF_7_4__SRCID__VF_PF_MSGBUF_ACK              0x8A        // Acknowledge message in VF->PF mailbox message buffer (The interrupt is sent on behalf of PF)
++#define NBIF_7_4__SRCID__CHIP_DPA_INT_EVENT            0xA0        // BIF_CHIP_DPA_INT_EVENT
++#define NBIF_7_4__SRCID__CHIP_SLOT_POWER_CHG_INT_EVENT 0xA1        // BIF_CHIP_SLOT_POWER_CHG_INT_EVENT
++#define NBIF_7_4__SRCID__ATOMIC_UR_OPCODE              0xCE        // BIF receives unsupported atomic opcode from MC
++#define NBIF_7_4__SRCID__ATOMIC_REQESTEREN_LOW         0xCF        // BIF receive atomic request from MC while AtomicOp Requester is not enabled in PCIE config space
++
++#endif // __IRQSRCS_NBIF_7_4_H__
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3659-drm-amdgpu-update-nbio-v7_4-ip-header-files.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3659-drm-amdgpu-update-nbio-v7_4-ip-header-files.patch
new file mode 100644
index 00000000..9fdabe92
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3659-drm-amdgpu-update-nbio-v7_4-ip-header-files.patch
@@ -0,0 +1,49 @@
+From 7688012a89a9e22cac673f3da3e704c90375703d Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 5 Jun 2019 14:20:38 +0800
+Subject: [PATCH 3659/4256] drm/amdgpu: update nbio v7_4 ip header files
+
+Add mmBIF_INTR_CNTL and its shift mask.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h | 4 ++--
+ .../gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h    | 6 +++---
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h
+index 994e796a28d7..ce5830ebe095 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h
+@@ -2793,8 +2793,8 @@
+ #define mmBIF_DOORBELL_INT_CNTL_BASE_IDX                                                               2
+ #define mmBIF_FB_EN                                                                                    0x00ff
+ #define mmBIF_FB_EN_BASE_IDX                                                                           2
+-#define mmBIF_BUSY_DELAY_CNTR                                                                          0x0100
+-#define mmBIF_BUSY_DELAY_CNTR_BASE_IDX                                                                 2
++#define mmBIF_INTR_CNTL                                                                                0x0100
++#define mmBIF_INTR_CNTL_BASE_IDX                                                                       2
+ #define mmBIF_MST_TRANS_PENDING_VF                                                                     0x0109
+ #define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX                                                            2
+ #define mmBIF_SLV_TRANS_PENDING_VF                                                                     0x010a
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h
+index d467b939c971..f9829f577364 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h
+@@ -20420,9 +20420,9 @@
+ #define BIF_FB_EN__FB_WRITE_EN__SHIFT                                                                         0x1
+ #define BIF_FB_EN__FB_READ_EN_MASK                                                                            0x00000001L
+ #define BIF_FB_EN__FB_WRITE_EN_MASK                                                                           0x00000002L
+-//BIF_BUSY_DELAY_CNTR
+-#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT                                                                 0x0
+-#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK                                                                   0x0000003FL
++//BIF_INTR_CNTL
++#define BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT                                                                0x0
++#define BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK                                                                  0x00000001L
+ //BIF_MST_TRANS_PENDING_VF
+ #define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT                                                0x0
+ #define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK                                                  0x7FFFFFFFL
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3660-drm-amdgpu-add-ras_controller-and-err_event_athub-in.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3660-drm-amdgpu-add-ras_controller-and-err_event_athub-in.patch
new file mode 100644
index 00000000..d858e065
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3660-drm-amdgpu-add-ras_controller-and-err_event_athub-in.patch
@@ -0,0 +1,226 @@
+From 8b13868985c28be8026995b653e78dbf192bd8ba Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 5 Jun 2019 14:57:00 +0800
+Subject: [PATCH 3660/4256] drm/amdgpu: add ras_controller and err_event_athub
+ interrupt support
+
+Ras controller interrupt and Ras err event athub interrupt are two dedicated
+interrupts for RAS support.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h |   4 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c  |  14 +++
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c   | 125 +++++++++++++++++++++++
+ 3 files changed, 143 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+index 28417e485c58..a04c5ea03418 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+@@ -79,10 +79,14 @@ struct amdgpu_nbio_funcs {
+ 	void (*remap_hdp_registers)(struct amdgpu_device *adev);
+ 	void (*handle_ras_controller_intr_no_bifring)(struct amdgpu_device *adev);
+ 	void (*handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device *adev);
++	int (*init_ras_controller_interrupt)(struct amdgpu_device *adev);
++	int (*init_ras_err_event_athub_interrupt)(struct amdgpu_device *adev);
+ };
+ 
+ struct amdgpu_nbio {
+ 	const struct nbio_hdp_flush_reg *hdp_flush_reg;
++	struct amdgpu_irq_src ras_controller_irq;
++	struct amdgpu_irq_src ras_err_event_athub_irq;
+ 	const struct amdgpu_nbio_funcs *funcs;
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index df4b9ae39c5e..230f7e63e4d8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -27,6 +27,7 @@
+ #include "amdgpu.h"
+ #include "amdgpu_ras.h"
+ #include "amdgpu_atomfirmware.h"
++#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
+ 
+ const char *ras_error_string[] = {
+ 	"none",
+@@ -1498,6 +1499,7 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
+ int amdgpu_ras_init(struct amdgpu_device *adev)
+ {
+ 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
++	int r;
+ 
+ 	if (con)
+ 		return 0;
+@@ -1525,6 +1527,18 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
+ 	/* Might need get this flag from vbios. */
+ 	con->flags = RAS_DEFAULT_FLAGS;
+ 
++	if (adev->nbio.funcs->init_ras_controller_interrupt) {
++		r = adev->nbio.funcs->init_ras_controller_interrupt(adev);
++		if (r)
++			return r;
++	}
++
++	if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) {
++		r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev);
++		if (r)
++			return r;
++	}
++
+ 	if (amdgpu_ras_recovery_init(adev))
+ 		goto recovery_out;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index 6ecdd5e3ca3f..faf9300630a5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -27,6 +27,7 @@
+ #include "nbio/nbio_7_4_offset.h"
+ #include "nbio/nbio_7_4_sh_mask.h"
+ #include "nbio/nbio_7_4_0_smn.h"
++#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
+ #include <uapi/linux/kfd_ioctl.h>
+ 
+ #define smnNBIF_MGCG_CTRL_LCLK	0x1013a21c
+@@ -345,6 +346,128 @@ static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_d
+ 	}
+ }
+ 
++
++static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev,
++						  struct amdgpu_irq_src *src,
++						  unsigned type,
++						  enum amdgpu_interrupt_state state)
++{
++	/* The ras_controller_irq enablement should be done in psp bl when it
++	 * tries to enable ras feature. Driver only need to set the correct interrupt
++	 * vector for bare-metal and sriov use case respectively
++	 */
++	uint32_t bif_intr_cntl;
++
++	bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
++	if (state == AMDGPU_IRQ_STATE_ENABLE) {
++		/* set interrupt vector select bit to 0 to select
++		 * vetcor 1 for bare metal case */
++		bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
++					      BIF_INTR_CNTL,
++					      RAS_INTR_VEC_SEL, 0);
++		WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
++	}
++
++	return 0;
++}
++
++static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev,
++						struct amdgpu_irq_src *source,
++						struct amdgpu_iv_entry *entry)
++{
++	/* By design, the ih cookie for ras_controller_irq should be written
++	 * to BIFring instead of general iv ring. However, due to known bif ring
++	 * hw bug, it has to be disabled. There is no chance the process function
++	 * will be involked. Just left it as a dummy one.
++	 */
++	return 0;
++}
++
++static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,
++						       struct amdgpu_irq_src *src,
++						       unsigned type,
++						       enum amdgpu_interrupt_state state)
++{
++	/* The ras_controller_irq enablement should be done in psp bl when it
++	 * tries to enable ras feature. Driver only need to set the correct interrupt
++	 * vector for bare-metal and sriov use case respectively
++	 */
++	uint32_t bif_intr_cntl;
++
++	bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
++	if (state == AMDGPU_IRQ_STATE_ENABLE) {
++		/* set interrupt vector select bit to 0 to select
++		 * vetcor 1 for bare metal case */
++		bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
++					      BIF_INTR_CNTL,
++					      RAS_INTR_VEC_SEL, 0);
++		WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
++	}
++
++	return 0;
++}
++
++static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev,
++						 struct amdgpu_irq_src *source,
++						 struct amdgpu_iv_entry *entry)
++{
++	/* By design, the ih cookie for err_event_athub_irq should be written
++	 * to BIFring instead of general iv ring. However, due to known bif ring
++	 * hw bug, it has to be disabled. There is no chance the process function
++	 * will be involked. Just left it as a dummy one.
++	 */
++	return 0;
++}
++
++static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = {
++	.set = nbio_v7_4_set_ras_controller_irq_state,
++	.process = nbio_v7_4_process_ras_controller_irq,
++};
++
++static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = {
++	.set = nbio_v7_4_set_ras_err_event_athub_irq_state,
++	.process = nbio_v7_4_process_err_event_athub_irq,
++};
++
++static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev)
++{
++	int r;
++
++	/* init the irq funcs */
++	adev->nbio.ras_controller_irq.funcs =
++		&nbio_v7_4_ras_controller_irq_funcs;
++	adev->nbio.ras_controller_irq.num_types = 1;
++
++	/* register ras controller interrupt */
++	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
++			      NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT,
++			      &adev->nbio.ras_controller_irq);
++	if (r)
++		return r;
++
++	return 0;
++}
++
++static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev)
++{
++
++	int r;
++
++	/* init the irq funcs */
++	adev->nbio.ras_err_event_athub_irq.funcs =
++		&nbio_v7_4_ras_err_event_athub_irq_funcs;
++	adev->nbio.ras_err_event_athub_irq.num_types = 1;
++
++	/* register ras err event athub interrupt */
++	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
++			      NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT,
++			      &adev->nbio.ras_err_event_athub_irq);
++	if (r)
++		return r;
++
++	return 0;
++}
++
+ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ 	.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
+ 	.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
+@@ -368,4 +491,6 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ 	.remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
+ 	.handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring,
+ 	.handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
++	.init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,
++	.init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3661-drm-amdgpu-keep-the-stolen-memory-in-visible-vram-re.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3661-drm-amdgpu-keep-the-stolen-memory-in-visible-vram-re.patch
new file mode 100644
index 00000000..8c842421
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3661-drm-amdgpu-keep-the-stolen-memory-in-visible-vram-re.patch
@@ -0,0 +1,75 @@
+From f5d61899743a1b8d27860789c60300c57b00167b Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Wed, 28 Aug 2019 18:51:19 +0800
+Subject: [PATCH 3661/4256] drm/amdgpu: keep the stolen memory in visible vram
+ region
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+stolen memory should be fixed in visible region.
+
+Change-Id: Icbbbd39fd113e93423aad8d2555f4073c08020e5
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 ++++--
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 3 ++-
+ 2 files changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 5b21dae64755..7377bff42335 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -2046,6 +2046,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
+ 	uint64_t gtt_size;
+ 	int r;
+ 	u64 vis_vram_limit;
++	void *stolen_vga_buf;
+ 
+ 	/* initialize global references for vram/gtt */
+ 	r = amdgpu_ttm_global_init(adev);
+@@ -2105,7 +2106,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
+ 	r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
+ 				    AMDGPU_GEM_DOMAIN_VRAM,
+ 				    &adev->stolen_vga_memory,
+-				    NULL, NULL);
++				    NULL, &stolen_vga_buf);
+ 	if (r)
+ 		return r;
+ 	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
+@@ -2174,8 +2175,9 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
+  */
+ void amdgpu_ttm_late_init(struct amdgpu_device *adev)
+ {
++	void *stolen_vga_buf;
+ 	/* return the VGA stolen memory (if any) back to VRAM */
+-	amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
++	amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
+ }
+ 
+ /**
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index b97ea92bda51..e01fe0678243 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -1248,6 +1248,7 @@ static int gmc_v9_0_sw_init(void *handle)
+ static int gmc_v9_0_sw_fini(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	void *stolen_vga_buf;
+ 
+ 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
+ 			adev->gmc.umc_ras_if) {
+@@ -1280,7 +1281,7 @@ static int gmc_v9_0_sw_fini(void *handle)
+ 	amdgpu_vm_manager_fini(adev);
+ 
+ 	if (gmc_v9_0_keep_stolen_memory(adev))
+-		amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
++		amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
+ 
+ 	amdgpu_gart_table_vram_free(adev);
+ 	amdgpu_bo_fini(adev);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3662-drm-amdgpu-Initialize-and-update-SDMA-power-gating.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3662-drm-amdgpu-Initialize-and-update-SDMA-power-gating.patch
new file mode 100644
index 00000000..950e00f4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3662-drm-amdgpu-Initialize-and-update-SDMA-power-gating.patch
@@ -0,0 +1,29 @@
+From d2d9bac7ba30b84cb3553ecd0cd1fa807a54dc73 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Mon, 26 Aug 2019 16:46:34 +0800
+Subject: [PATCH 3662/4256] drm/amdgpu: Initialize and update SDMA power gating
+
+Init SDMA HW base configuration and enable idle INT for rn.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Aaron Liu <aaron.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 5e5b6a3cda2c..7461d52e0b6e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1205,6 +1205,7 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_RAVEN:
++	case CHIP_RENOIR:
+ 		sdma_v4_1_init_power_gating(adev);
+ 		sdma_v4_1_update_power_gating(adev, true);
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3663-drm-amd-powerplay-replace-smu-table_count-with-SMU_T.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3663-drm-amd-powerplay-replace-smu-table_count-with-SMU_T.patch
new file mode 100644
index 00000000..af5ce928
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3663-drm-amd-powerplay-replace-smu-table_count-with-SMU_T.patch
@@ -0,0 +1,186 @@
+From 0fdf4a3d20907052c8d42dd4782d72f759ed3da5 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Tue, 3 Sep 2019 16:02:33 +0800
+Subject: [PATCH 3663/4256] drm/amd/powerplay: replace smu->table_count with
+ SMU_TABLE_COUNT in smu
+
+fix bellow patch issue:
+drm/amd/powerplay: introduce smu table id type to handle the smu table
+for each asic
+----
+"This patch introduces new smu table type, it's to handle the
+ different smu table
+ defines for each asic with the same smu ip."
+
+before:
+use smu->table_count to represent the actual table count in smc firmware
+use actual table count to check smu function parameter about smu table
+after:
+use logic table count "SMU_TABLE_COUNT" to check function parameter
+because table id already mapped in smu driver,
+and smu function will use logic table id not actual table id to check func parameter.
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     | 13 ++++---------
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c   |  1 -
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  1 -
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c     |  1 -
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c     |  1 -
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c      |  5 ++---
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c      |  4 ++--
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c     |  1 -
+ 8 files changed, 8 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 797441894c2f..590d0012bc22 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -436,7 +436,7 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int
+ 	int ret = 0;
+ 	int table_id = smu_table_get_index(smu, table_index);
+ 
+-	if (!table_data || table_id >= smu_table->table_count || table_id < 0)
++	if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0)
+ 		return -EINVAL;
+ 
+ 	table = &smu_table->tables[table_index];
+@@ -914,14 +914,10 @@ static int smu_init_fb_allocations(struct smu_context *smu)
+ 	struct amdgpu_device *adev = smu->adev;
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 	struct smu_table *tables = smu_table->tables;
+-	uint32_t table_count = smu_table->table_count;
+ 	uint32_t i = 0;
+ 	int32_t ret = 0;
+ 
+-	if (table_count <= 0)
+-		return -EINVAL;
+-
+-	for (i = 0 ; i < table_count; i++) {
++	for (i = 0; i < SMU_TABLE_COUNT; i++) {
+ 		if (tables[i].size == 0)
+ 			continue;
+ 		ret = amdgpu_bo_create_kernel(adev,
+@@ -952,13 +948,12 @@ static int smu_fini_fb_allocations(struct smu_context *smu)
+ {
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 	struct smu_table *tables = smu_table->tables;
+-	uint32_t table_count = smu_table->table_count;
+ 	uint32_t i = 0;
+ 
+-	if (table_count == 0 || tables == NULL)
++	if (!tables)
+ 		return 0;
+ 
+-	for (i = 0 ; i < table_count; i++) {
++	for (i = 0; i < SMU_TABLE_COUNT; i++) {
+ 		if (tables[i].size == 0)
+ 			continue;
+ 		amdgpu_bo_free_kernel(&tables[i].bo,
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 595b1365c008..e7ec8d583ea0 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -1934,5 +1934,4 @@ void arcturus_set_ppt_funcs(struct smu_context *smu)
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 
+ 	smu->ppt_funcs = &arcturus_ppt_funcs;
+-	smu_table->table_count = TABLE_COUNT;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 320ac20146fd..32cd2074178d 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -259,7 +259,6 @@ struct smu_table_context
+ 	struct smu_bios_boot_up_values	boot_values;
+ 	void                            *driver_pptable;
+ 	struct smu_table		*tables;
+-	uint32_t			table_count;
+ 	struct smu_table		memory_pool;
+ 	uint8_t                         thermal_controller_type;
+ 	uint16_t			TDPODLimit;
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 744b7501c34d..e3add8b59291 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1633,5 +1633,4 @@ void navi10_set_ppt_funcs(struct smu_context *smu)
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 
+ 	smu->ppt_funcs = &navi10_ppt_funcs;
+-	smu_table->table_count = TABLE_COUNT;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 2a6da546fb55..872598c19a5d 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -191,5 +191,4 @@ void renoir_set_ppt_funcs(struct smu_context *smu)
+ 
+ 	smu->ppt_funcs = &renoir_ppt_funcs;
+ 	smu->smc_if_version = SMU12_DRIVER_IF_VERSION;
+-	smu_table->table_count = TABLE_COUNT;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 117988eb7557..e85f0c8c5dd7 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -439,7 +439,7 @@ static int smu_v11_0_init_smc_tables(struct smu_context *smu)
+ 	struct smu_table *tables = NULL;
+ 	int ret = 0;
+ 
+-	if (smu_table->tables || smu_table->table_count == 0)
++	if (smu_table->tables)
+ 		return -EINVAL;
+ 
+ 	tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
+@@ -465,13 +465,12 @@ static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 	int ret = 0;
+ 
+-	if (!smu_table->tables || smu_table->table_count == 0)
++	if (!smu_table->tables)
+ 		return -EINVAL;
+ 
+ 	kfree(smu_table->tables);
+ 	kfree(smu_table->metrics_table);
+ 	smu_table->tables = NULL;
+-	smu_table->table_count = 0;
+ 	smu_table->metrics_table = NULL;
+ 	smu_table->metrics_time = 0;
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 9d2280ca1f4b..24274c9bb87d 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -275,7 +275,7 @@ static int smu_v12_0_init_smc_tables(struct smu_context *smu)
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 	struct smu_table *tables = NULL;
+ 
+-	if (smu_table->tables || smu_table->table_count == 0)
++	if (smu_table->tables)
+ 		return -EINVAL;
+ 
+ 	tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
+@@ -292,7 +292,7 @@ static int smu_v12_0_fini_smc_tables(struct smu_context *smu)
+ {
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 
+-	if (!smu_table->tables || smu_table->table_count == 0)
++	if (!smu_table->tables)
+ 		return -EINVAL;
+ 
+ 	kfree(smu_table->clocks_table);
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 899bf96b23e1..68548ba9b6ea 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -3189,5 +3189,4 @@ void vega20_set_ppt_funcs(struct smu_context *smu)
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 
+ 	smu->ppt_funcs = &vega20_ppt_funcs;
+-	smu_table->table_count = TABLE_COUNT;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3664-drm-amd-powerplay-SMU_MSG_OverridePcieParameters-is-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3664-drm-amd-powerplay-SMU_MSG_OverridePcieParameters-is-.patch
new file mode 100644
index 00000000..f0fd53a5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3664-drm-amd-powerplay-SMU_MSG_OverridePcieParameters-is-.patch
@@ -0,0 +1,34 @@
+From 0ab580777db7d2f8062ea6c49ed08fa73f559d78 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Fri, 30 Aug 2019 09:53:27 +0800
+Subject: [PATCH 3664/4256] drm/amd/powerplay: SMU_MSG_OverridePcieParameters
+ is unsupport for APU
+
+For apu, SMU_MSG_OverridePcieParameters is unsupport.
+So return directly in smu_override_pcie_parameters function.
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 590d0012bc22..a9cce9985d16 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -970,6 +970,9 @@ static int smu_override_pcie_parameters(struct smu_context *smu)
+ 	uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
+ 	int ret;
+ 
++	if (adev->flags & AMD_IS_APU)
++		return 0;
++
+ 	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
+ 		pcie_gen = 3;
+ 	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3665-drm-amdgpu-update-IH_CHICKEN-in-oss-4.0-IP-header-fo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3665-drm-amdgpu-update-IH_CHICKEN-in-oss-4.0-IP-header-fo.patch
new file mode 100644
index 00000000..50b011c8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3665-drm-amdgpu-update-IH_CHICKEN-in-oss-4.0-IP-header-fo.patch
@@ -0,0 +1,36 @@
+From ad154d9a300dbb2c10699c699afe07e0474eaffa Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Fri, 14 Dec 2018 11:16:36 +0800
+Subject: [PATCH 3665/4256] drm/amdgpu: update IH_CHICKEN in oss 4.0 IP header
+ for VG/RV series
+
+In Renoir's emulator, those chicken bits need to be programmed.
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h
+index 1ee3a2329ee4..dc9895a684fe 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h
+@@ -1109,7 +1109,11 @@
+ #define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK                                                               0x00FF0000L
+ //IH_CHICKEN
+ #define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT                                                          0x0
++#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE__SHIFT                                                               0x3
++#define IH_CHICKEN__MC_SPACE_GPA_ENABLE__SHIFT                                                                0x4
+ #define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE_MASK                                                            0x00000001L
++#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE_MASK                                                                 0x00000008L
++#define IH_CHICKEN__MC_SPACE_GPA_ENABLE_MASK                                                                  0x00000010L
+ //IH_MMHUB_CNTL
+ #define IH_MMHUB_CNTL__UNITID__SHIFT                                                                          0x0
+ #define IH_MMHUB_CNTL__IV_TLVL__SHIFT                                                                         0x8
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3666-drm-amdgpu-fix-no-interrupt-issue-for-renoir-emu-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3666-drm-amdgpu-fix-no-interrupt-issue-for-renoir-emu-v2.patch
new file mode 100644
index 00000000..744830f0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3666-drm-amdgpu-fix-no-interrupt-issue-for-renoir-emu-v2.patch
@@ -0,0 +1,59 @@
+From 3efe1818511639401abd79759daaf1e651ec96a6 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Fri, 14 Dec 2018 11:21:41 +0800
+Subject: [PATCH 3666/4256] drm/amdgpu: fix no interrupt issue for renoir emu
+ (v2)
+
+In renoir's vega10_ih model, there's a security change in mmIH_CHICKEN
+register, that limits IH to use physical address (FBPA, GPA) directly.
+Those chicken bits need to be programmed first.
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 18 ++++++++++--------
+ 1 file changed, 10 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+index d92ff25f1ed3..d7135e5871d4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
++++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+@@ -232,7 +232,13 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
+ 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff);
+ 
+ 	ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
++	ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
+ 	ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
++	if (adev->irq.ih.use_bus_addr) {
++		ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
++	} else {
++		ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, MC_SPACE_FBPA_ENABLE, 1);
++	}
+ 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM,
+ 				   !!adev->irq.msi_enabled);
+ 
+@@ -245,14 +251,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
+ 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
+ 	}
+ 
+-	if ((adev->asic_type == CHIP_ARCTURUS || adev->asic_type == CHIP_RENOIR) &&
+-		adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
+-		if (adev->irq.ih.use_bus_addr) {
+-			ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
+-			ih_chicken |= 0x00000010;
+-			WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
+-		}
+-	}
++	if ((adev->asic_type == CHIP_ARCTURUS
++		&& adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)
++		|| adev->asic_type == CHIP_RENOIR)
++		WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
+ 
+ 	/* set the writeback address whether it's enabled or not */
+ 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3667-drm-amdgpu-Move-null-pointer-dereference-check.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3667-drm-amdgpu-Move-null-pointer-dereference-check.patch
new file mode 100644
index 00000000..3264df52
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3667-drm-amdgpu-Move-null-pointer-dereference-check.patch
@@ -0,0 +1,44 @@
+From a1e43d7e52117904661ac7b0875b7a7279f6176c Mon Sep 17 00:00:00 2001
+From: Austin Kim <austindh.kim@gmail.com>
+Date: Fri, 30 Aug 2019 17:07:04 +0900
+Subject: [PATCH 3667/4256] drm/amdgpu: Move null pointer dereference check
+
+Null pointer dereference check should have been checked,
+ahead of below routine.
+	struct amdgpu_device *adev = hwmgr->adev;
+
+With this commit, it could avoid potential NULL dereference.
+
+Signed-off-by: Austin Kim <austindh.kim@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
+index 8189fe402c6d..4728aa23a818 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
+@@ -722,16 +722,17 @@ static int smu8_request_smu_load_fw(struct pp_hwmgr *hwmgr)
+ 
+ static int smu8_start_smu(struct pp_hwmgr *hwmgr)
+ {
+-	struct amdgpu_device *adev = hwmgr->adev;
++	struct amdgpu_device *adev;
+ 
+ 	uint32_t index = SMN_MP1_SRAM_START_ADDR +
+ 			 SMU8_FIRMWARE_HEADER_LOCATION +
+ 			 offsetof(struct SMU8_Firmware_Header, Version);
+ 
+-
+ 	if (hwmgr == NULL || hwmgr->device == NULL)
+ 		return -EINVAL;
+ 
++	adev = hwmgr->adev;
++
+ 	cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
+ 	hwmgr->smu_version = cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA);
+ 	pr_info("smu version %02d.%02d.%02d\n",
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3668-drm-amdgpu-Remove-unnecessary-TLB-workaround-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3668-drm-amdgpu-Remove-unnecessary-TLB-workaround-v2.patch
new file mode 100644
index 00000000..d0a3bc88
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3668-drm-amdgpu-Remove-unnecessary-TLB-workaround-v2.patch
@@ -0,0 +1,76 @@
+From 8e570139eb21b7db16e953cca590d16ba0f12c8f Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Thu, 29 Aug 2019 21:18:43 -0400
+Subject: [PATCH 3668/4256] drm/amdgpu: Remove unnecessary TLB workaround (v2)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This workaround is better handled in user mode in a way that doesn't
+require allocating extra memory and breaking userptr BOs.
+
+The TLB bug is a performance bug, not a functional or security bug.
+Hence it is safe to remove this kernel part of the workaround to
+allow a better workaround using only virtual address alignments in
+user mode.
+
+v2: Removed VI_BO_SIZE_ALIGN definition
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c    | 17 +----------------
+ 1 file changed, 1 insertion(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index 580f52eda694..7da67e5b3140 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -33,11 +33,6 @@
+ #include "amdgpu_amdkfd.h"
+ #include "amdgpu_dma_buf.h"
+ 
+-/* Special VM and GART address alignment needed for VI pre-Fiji due to
+- * a HW bug.
+- */
+-#define VI_BO_SIZE_ALIGN (0x8000)
+-
+ /* BO flag to indicate a KFD userptr BO */
+ #define AMDGPU_AMDKFD_USERPTR_BO (1ULL << 63)
+ 
+@@ -1138,7 +1133,6 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
+ 	uint64_t user_addr = 0;
+ 	struct amdgpu_bo *bo;
+ 	struct amdgpu_bo_param bp;
+-	int byte_align;
+ 	u32 domain, alloc_domain;
+ 	u64 alloc_flags;
+ 	uint32_t mapping_flags;
+@@ -1201,15 +1195,6 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
+ 	if ((*mem)->aql_queue)
+ 		size = size >> 1;
+ 
+-	/* Workaround for TLB bug on older VI chips */
+-	byte_align = (adev->family == AMDGPU_FAMILY_VI &&
+-			adev->asic_type != CHIP_FIJI &&
+-			adev->asic_type != CHIP_POLARIS10 &&
+-			adev->asic_type != CHIP_POLARIS11 &&
+-			adev->asic_type != CHIP_POLARIS12 &&
+-			adev->asic_type != CHIP_VEGAM) ?
+-			VI_BO_SIZE_ALIGN : 1;
+-
+ 	mapping_flags = AMDGPU_VM_PAGE_READABLE;
+ 	if (flags & ALLOC_MEM_FLAGS_WRITABLE)
+ 		mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
+@@ -1235,7 +1220,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
+ 
+ 	memset(&bp, 0, sizeof(bp));
+ 	bp.size = size;
+-	bp.byte_align = byte_align;
++	bp.byte_align = 1;
+ 	bp.domain = alloc_domain;
+ 	bp.flags = alloc_flags;
+ 	bp.type = bo_type;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3669-drm-amd-powerplay-guard-manual-mode-prerequisite-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3669-drm-amd-powerplay-guard-manual-mode-prerequisite-for.patch
new file mode 100644
index 00000000..50f5a3db
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3669-drm-amd-powerplay-guard-manual-mode-prerequisite-for.patch
@@ -0,0 +1,92 @@
+From fac4d902a25b294c4a595c7c20c2c76f932c504d Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 30 Aug 2019 17:30:46 +0800
+Subject: [PATCH 3669/4256] drm/amd/powerplay: guard manual mode prerequisite
+ for clock level force
+
+Force clock level is for dpm manual mode only.
+
+Change-Id: I3b4caf3fafc72197d65e2b9255c68e40e673e25e
+Reported-by: Candice Li <candice.li@amd.com>
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Jack Gui <Jack.Gui@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     | 18 ++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  5 +++--
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c     |  6 ------
+ 3 files changed, 21 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index a9cce9985d16..04731351b194 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1756,6 +1756,24 @@ int smu_set_display_count(struct smu_context *smu, uint32_t count)
+ 	return ret;
+ }
+ 
++int smu_force_clk_levels(struct smu_context *smu,
++			 enum smu_clk_type clk_type,
++			 uint32_t mask)
++{
++	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
++	int ret = 0;
++
++	if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
++		pr_debug("force clock level is for dpm manual mode only.\n");
++		return -EINVAL;
++	}
++
++	if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
++		ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
++
++	return ret;
++}
++
+ const struct amd_ip_funcs smu_ip_funcs = {
+ 	.name = "smu",
+ 	.early_init = smu_early_init,
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 32cd2074178d..83e35c990300 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -634,8 +634,6 @@ struct smu_funcs
+ 	((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
+ #define smu_print_clk_levels(smu, clk_type, buf) \
+ 	((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (clk_type), (buf)) : 0)
+-#define smu_force_clk_levels(smu, clk_type, level) \
+-	((smu)->ppt_funcs->force_clk_levels ? (smu)->ppt_funcs->force_clk_levels((smu), (clk_type), (level)) : 0)
+ #define smu_get_od_percentage(smu, type) \
+ 	((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
+ #define smu_set_od_percentage(smu, type, value) \
+@@ -833,5 +831,8 @@ const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type
+ const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
+ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
+ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
++int smu_force_clk_levels(struct smu_context *smu,
++			 enum smu_clk_type clk_type,
++			 uint32_t mask);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 68548ba9b6ea..18d1b432f719 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -1274,14 +1274,8 @@ static int vega20_force_clk_levels(struct smu_context *smu,
+ 	struct vega20_dpm_table *dpm_table;
+ 	struct vega20_single_dpm_table *single_dpm_table;
+ 	uint32_t soft_min_level, soft_max_level, hard_min_level;
+-	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+ 	int ret = 0;
+ 
+-	if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
+-		pr_info("force clock level is for dpm manual mode only.\n");
+-		return -EINVAL;
+-	}
+-
+ 	mutex_lock(&(smu->mutex));
+ 
+ 	soft_min_level = mask ? (ffs(mask) - 1) : 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3670-drm-amd-powerplay-update-cached-feature-enablement-s.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3670-drm-amd-powerplay-update-cached-feature-enablement-s.patch
new file mode 100644
index 00000000..4d959bb5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3670-drm-amd-powerplay-update-cached-feature-enablement-s.patch
@@ -0,0 +1,170 @@
+From 0e41fb3b5dfe4983cb245f41d66cff28f4d8f259 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Wed, 21 Aug 2019 17:19:52 +0800
+Subject: [PATCH 3670/4256] drm/amd/powerplay: update cached feature enablement
+ status V3
+
+Need to update in cache feature enablement status after pp_feature
+settings. Another fix for the commit below:
+drm/amd/powerplay: implment sysfs feature status function in smu
+
+V2: update smu_feature_update_enable_state() and relates
+V3: use bitmap_or and bitmap_andnot
+
+Change-Id: I90e29b0d839df26825d5993212f6097c7ad4bebf
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Jack Gui <Jack.Gui@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 101 +++++++++---------
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |   1 -
+ 2 files changed, 49 insertions(+), 53 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 04731351b194..7c5ab9139d0e 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -95,6 +95,52 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
+ 	return size;
+ }
+ 
++static int smu_feature_update_enable_state(struct smu_context *smu,
++					   uint64_t feature_mask,
++					   bool enabled)
++{
++	struct smu_feature *feature = &smu->smu_feature;
++	uint32_t feature_low = 0, feature_high = 0;
++	int ret = 0;
++
++	if (!smu->pm_enabled)
++		return ret;
++
++	feature_low = (feature_mask >> 0 ) & 0xffffffff;
++	feature_high = (feature_mask >> 32) & 0xffffffff;
++
++	if (enabled) {
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
++						  feature_low);
++		if (ret)
++			return ret;
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
++						  feature_high);
++		if (ret)
++			return ret;
++	} else {
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
++						  feature_low);
++		if (ret)
++			return ret;
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
++						  feature_high);
++		if (ret)
++			return ret;
++	}
++
++	mutex_lock(&feature->mutex);
++	if (enabled)
++		bitmap_or(feature->enabled, feature->enabled,
++				(unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
++	else
++		bitmap_andnot(feature->enabled, feature->enabled,
++				(unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
++	mutex_unlock(&feature->mutex);
++
++	return ret;
++}
++
+ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
+ {
+ 	int ret = 0;
+@@ -566,41 +612,7 @@ int smu_feature_init_dpm(struct smu_context *smu)
+ 
+ 	return ret;
+ }
+-int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled)
+-{
+-	uint32_t feature_low = 0, feature_high = 0;
+-	int ret = 0;
+-
+-	if (!smu->pm_enabled)
+-		return ret;
+-
+-	feature_low = (feature_mask >> 0 ) & 0xffffffff;
+-	feature_high = (feature_mask >> 32) & 0xffffffff;
+-
+-	if (enabled) {
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
+-						  feature_low);
+-		if (ret)
+-			return ret;
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
+-						  feature_high);
+-		if (ret)
+-			return ret;
+-
+-	} else {
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
+-						  feature_low);
+-		if (ret)
+-			return ret;
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
+-						  feature_high);
+-		if (ret)
+-			return ret;
+ 
+-	}
+-
+-	return ret;
+-}
+ 
+ int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
+ {
+@@ -630,8 +642,6 @@ int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
+ {
+ 	struct smu_feature *feature = &smu->smu_feature;
+ 	int feature_id;
+-	uint64_t feature_mask = 0;
+-	int ret = 0;
+ 
+ 	feature_id = smu_feature_get_index(smu, mask);
+ 	if (feature_id < 0)
+@@ -639,22 +649,9 @@ int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
+ 
+ 	WARN_ON(feature_id > feature->feature_num);
+ 
+-	feature_mask = 1ULL << feature_id;
+-
+-	mutex_lock(&feature->mutex);
+-	ret = smu_feature_update_enable_state(smu, feature_mask, enable);
+-	if (ret)
+-		goto failed;
+-
+-	if (enable)
+-		test_and_set_bit(feature_id, feature->enabled);
+-	else
+-		test_and_clear_bit(feature_id, feature->enabled);
+-
+-failed:
+-	mutex_unlock(&feature->mutex);
+-
+-	return ret;
++	return smu_feature_update_enable_state(smu,
++					       1ULL << feature_id,
++					       enable);
+ }
+ 
+ int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 83e35c990300..e9b99355bd88 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -826,7 +826,6 @@ enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
+ int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
+ int smu_set_display_count(struct smu_context *smu, uint32_t count);
+ bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
+-int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);
+ const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
+ const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
+ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3671-drm-amd-powerplay-do-proper-cleanups-on-hw_fini.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3671-drm-amd-powerplay-do-proper-cleanups-on-hw_fini.patch
new file mode 100644
index 00000000..eca95798
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3671-drm-amd-powerplay-do-proper-cleanups-on-hw_fini.patch
@@ -0,0 +1,103 @@
+From 4b1bd2bb6cbd46393e84812c01bad445f2226aa3 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 2 Sep 2019 12:37:23 +0800
+Subject: [PATCH 3671/4256] drm/amd/powerplay: do proper cleanups on hw_fini
+
+These are needed for smu_reset support.
+
+Change-Id: If29ede4b99758adb08fd4e16665f44fd893ec99b
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Jack Gui <Jack.Gui@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     | 17 +++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  3 +++
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c      | 10 ++++++++++
+ 3 files changed, 30 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 7c5ab9139d0e..e53ea7b9e8f9 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1278,6 +1278,11 @@ static int smu_hw_init(void *handle)
+ 	return ret;
+ }
+ 
++static int smu_stop_dpms(struct smu_context *smu)
++{
++	return smu_send_smc_msg(smu, SMU_MSG_DisableAllSmuFeatures);
++}
++
+ static int smu_hw_fini(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+@@ -1290,6 +1295,18 @@ static int smu_hw_fini(void *handle)
+ 		smu_powergate_vcn(&adev->smu, true);
+ 	}
+ 
++	ret = smu_stop_thermal_control(smu);
++	if (ret) {
++		pr_warn("Fail to stop thermal control!\n");
++		return ret;
++	}
++
++	ret = smu_stop_dpms(smu);
++	if (ret) {
++		pr_warn("Fail to stop Dpms!\n");
++		return ret;
++	}
++
+ 	kfree(table_context->driver_pptable);
+ 	table_context->driver_pptable = NULL;
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index e9b99355bd88..e1237ea8844c 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -497,6 +497,7 @@ struct smu_funcs
+ 	int (*get_current_clk_freq)(struct smu_context *smu, enum smu_clk_type clk_id, uint32_t *value);
+ 	int (*init_max_sustainable_clocks)(struct smu_context *smu);
+ 	int (*start_thermal_control)(struct smu_context *smu);
++	int (*stop_thermal_control)(struct smu_context *smu);
+ 	int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
+ 			   void *data, uint32_t *size);
+ 	int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);
+@@ -646,6 +647,8 @@ struct smu_funcs
+ 	((smu)->ppt_funcs->set_thermal_fan_table ? (smu)->ppt_funcs->set_thermal_fan_table((smu)) : 0)
+ #define smu_start_thermal_control(smu) \
+ 	((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
++#define smu_stop_thermal_control(smu) \
++	((smu)->funcs->stop_thermal_control? (smu)->funcs->stop_thermal_control((smu)) : 0)
+ #define smu_read_sensor(smu, sensor, data, size) \
+ 	((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
+ #define smu_smc_read_sensor(smu, sensor, data, size) \
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index e85f0c8c5dd7..022b5c8672a1 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1211,6 +1211,15 @@ static int smu_v11_0_start_thermal_control(struct smu_context *smu)
+ 	return ret;
+ }
+ 
++static int smu_v11_0_stop_thermal_control(struct smu_context *smu)
++{
++	struct amdgpu_device *adev = smu->adev;
++
++	WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
++
++	return 0;
++}
++
+ static uint16_t convert_to_vddc(uint8_t vid)
+ {
+ 	return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
+@@ -1785,6 +1794,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
+ 	.get_current_clk_freq = smu_v11_0_get_current_clk_freq,
+ 	.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
+ 	.start_thermal_control = smu_v11_0_start_thermal_control,
++	.stop_thermal_control = smu_v11_0_stop_thermal_control,
+ 	.read_sensor = smu_v11_0_read_sensor,
+ 	.set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
+ 	.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3672-drm-amdgpu-use-moving-fence-instead-of-exclusive-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3672-drm-amdgpu-use-moving-fence-instead-of-exclusive-for.patch
new file mode 100644
index 00000000..b2fdff33
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3672-drm-amdgpu-use-moving-fence-instead-of-exclusive-for.patch
@@ -0,0 +1,35 @@
+From 1c9819c5046f7a096c2d3161980c1a1b190c2278 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Fri, 16 Aug 2019 16:06:51 +0200
+Subject: [PATCH 3672/4256] drm/amdgpu: use moving fence instead of exclusive
+ for VM updates
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Make VM updates depend on the moving fence instead of the exclusive one.
+
+Makes it less likely to actually have a dependency.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index c55e7aba2f99..dd5b5875f874 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -1667,7 +1667,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
+ 			ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
+ 			pages_addr = ttm->dma_address;
+ 		}
+-		exclusive = reservation_object_get_excl(bo->tbo.resv);
++		exclusive = bo->tbo.moving;
+ 	}
+ 
+ 	if (bo) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3673-drm-amdgpu-reserve-at-least-4MB-of-VRAM-for-page-tab.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3673-drm-amdgpu-reserve-at-least-4MB-of-VRAM-for-page-tab.patch
new file mode 100644
index 00000000..9b09e760
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3673-drm-amdgpu-reserve-at-least-4MB-of-VRAM-for-page-tab.patch
@@ -0,0 +1,116 @@
+From 273c0eab5b863779f158147db7f0c09deaa81c35 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Fri, 30 Aug 2019 14:38:37 +0200
+Subject: [PATCH 3673/4256] drm/amdgpu: reserve at least 4MB of VRAM for page
+ tables v2
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This hopefully helps reduce the contention for page tables.
+
+v2: adjust maximum reported VRAM size as well
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c      | 18 ++++++++++++------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h       |  3 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c |  9 +++++++--
+ 3 files changed, 22 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 141b86c1d3db..751c4c8e1cee 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -630,9 +630,12 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
+ 		struct drm_amdgpu_info_vram_gtt vram_gtt;
+ 
+ 		vram_gtt.vram_size = adev->gmc.real_vram_size -
+-			atomic64_read(&adev->vram_pin_size);
+-		vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size -
+-			atomic64_read(&adev->visible_pin_size);
++			atomic64_read(&adev->vram_pin_size) -
++			AMDGPU_VM_RESERVED_VRAM;
++		vram_gtt.vram_cpu_accessible_size =
++			min(adev->gmc.visible_vram_size -
++			    atomic64_read(&adev->visible_pin_size),
++			    vram_gtt.vram_size);
+ 		vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
+ 		vram_gtt.gtt_size *= PAGE_SIZE;
+ 		vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
+@@ -645,15 +648,18 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
+ 		memset(&mem, 0, sizeof(mem));
+ 		mem.vram.total_heap_size = adev->gmc.real_vram_size;
+ 		mem.vram.usable_heap_size = adev->gmc.real_vram_size -
+-			atomic64_read(&adev->vram_pin_size);
++			atomic64_read(&adev->vram_pin_size) -
++			AMDGPU_VM_RESERVED_VRAM;
+ 		mem.vram.heap_usage =
+ 			amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
+ 		mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
+ 
+ 		mem.cpu_accessible_vram.total_heap_size =
+ 			adev->gmc.visible_vram_size;
+-		mem.cpu_accessible_vram.usable_heap_size = adev->gmc.visible_vram_size -
+-			atomic64_read(&adev->visible_pin_size);
++		mem.cpu_accessible_vram.usable_heap_size =
++			min(adev->gmc.visible_vram_size -
++			    atomic64_read(&adev->visible_pin_size),
++			    mem.vram.usable_heap_size);
+ 		mem.cpu_accessible_vram.heap_usage =
+ 			amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
+ 		mem.cpu_accessible_vram.max_allocation =
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+index 6733189db978..269e55082737 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+@@ -99,6 +99,9 @@ struct amdgpu_bo_list_entry;
+ #define AMDGPU_VM_FAULT_STOP_FIRST	1
+ #define AMDGPU_VM_FAULT_STOP_ALWAYS	2
+ 
++/* Reserve 4MB VRAM for page tables */
++#define AMDGPU_VM_RESERVED_VRAM		(4ULL << 20)
++
+ /* max number of VMHUB */
+ #define AMDGPU_MAX_VMHUBS			3
+ #define AMDGPU_GFXHUB_0				0
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+index 1150e34bc28f..59440f71d304 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+@@ -24,6 +24,7 @@
+ 
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
++#include "amdgpu_vm.h"
+ 
+ struct amdgpu_vram_mgr {
+ 	struct drm_mm mm;
+@@ -276,7 +277,7 @@ static int amdgpu_vram_mgr_new(struct ttm_mem_type_manager *man,
+ 	struct drm_mm_node *nodes;
+ 	enum drm_mm_insert_mode mode;
+ 	unsigned long lpfn, num_nodes, pages_per_node, pages_left;
+-	uint64_t vis_usage = 0, mem_bytes;
++	uint64_t vis_usage = 0, mem_bytes, max_bytes;
+ 	unsigned i;
+ 	int r;
+ 
+@@ -284,9 +285,13 @@ static int amdgpu_vram_mgr_new(struct ttm_mem_type_manager *man,
+ 	if (!lpfn)
+ 		lpfn = man->size;
+ 
++	max_bytes = adev->gmc.mc_vram_size;
++	if (tbo->type != ttm_bo_type_kernel)
++		max_bytes -= AMDGPU_VM_RESERVED_VRAM;
++
+ 	/* bail out quickly if there's likely not enough VRAM for this BO */
+ 	mem_bytes = (u64)mem->num_pages << PAGE_SHIFT;
+-	if (atomic64_add_return(mem_bytes, &mgr->usage) > adev->gmc.mc_vram_size) {
++	if (atomic64_add_return(mem_bytes, &mgr->usage) > max_bytes) {
+ 		atomic64_sub(mem_bytes, &mgr->usage);
+ 		mem->mm_node = NULL;
+ 		return 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3674-drm-amdgpu-remove-amdgpu_cs_try_evict.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3674-drm-amdgpu-remove-amdgpu_cs_try_evict.patch
new file mode 100644
index 00000000..5b47df9c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3674-drm-amdgpu-remove-amdgpu_cs_try_evict.patch
@@ -0,0 +1,136 @@
+From d829b7f23c7c05ab59f45bba8e0401987401838b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Fri, 30 Aug 2019 14:42:10 +0200
+Subject: [PATCH 3674/4256] drm/amdgpu: remove amdgpu_cs_try_evict
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Trying to evict things from the current working set doesn't work that
+well anymore because of per VM BOs.
+
+Rely on reserving VRAM for page tables to avoid contention.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  1 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 71 +-------------------------
+ 2 files changed, 1 insertion(+), 71 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 178039b28651..f68d78832a8e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -483,7 +483,6 @@ struct amdgpu_cs_parser {
+ 	uint64_t			bytes_moved_vis_threshold;
+ 	uint64_t			bytes_moved;
+ 	uint64_t			bytes_moved_vis;
+-	struct amdgpu_bo_list_entry	*evictable;
+ 
+ 	/* user fence */
+ 	struct amdgpu_bo_list_entry	uf_entry;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+index e06702390278..55282bfcaa45 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+@@ -448,75 +448,12 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
+ 	return r;
+ }
+ 
+-/* Last resort, try to evict something from the current working set */
+-static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
+-				struct amdgpu_bo *validated)
+-{
+-	uint32_t domain = validated->allowed_domains;
+-	struct ttm_operation_ctx ctx = { true, false };
+-	int r;
+-
+-	if (!p->evictable)
+-		return false;
+-
+-	for (;&p->evictable->tv.head != &p->validated;
+-	     p->evictable = list_prev_entry(p->evictable, tv.head)) {
+-
+-		struct amdgpu_bo_list_entry *candidate = p->evictable;
+-		struct amdgpu_bo *bo = ttm_to_amdgpu_bo(candidate->tv.bo);
+-		struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+-		bool update_bytes_moved_vis;
+-		uint32_t other;
+-
+-		/* If we reached our current BO we can forget it */
+-		if (bo == validated)
+-			break;
+-
+-		/* We can't move pinned BOs here */
+-		if (bo->pin_count)
+-			continue;
+-
+-		other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
+-
+-		/* Check if this BO is in one of the domains we need space for */
+-		if (!(other & domain))
+-			continue;
+-
+-		/* Check if we can move this BO somewhere else */
+-		other = bo->allowed_domains & ~domain;
+-		if (!other)
+-			continue;
+-
+-		/* Good we can try to move this BO somewhere else */
+-		update_bytes_moved_vis =
+-				!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
+-				amdgpu_bo_in_cpu_visible_vram(bo);
+-		amdgpu_bo_placement_from_domain(bo, other);
+-		r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
+-		p->bytes_moved += ctx.bytes_moved;
+-		if (update_bytes_moved_vis)
+-			p->bytes_moved_vis += ctx.bytes_moved;
+-
+-		if (unlikely(r))
+-			break;
+-
+-		p->evictable = list_prev_entry(p->evictable, tv.head);
+-		list_move(&candidate->tv.head, &p->validated);
+-
+-		return true;
+-	}
+-
+-	return false;
+-}
+-
+ static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
+ {
+ 	struct amdgpu_cs_parser *p = param;
+ 	int r;
+ 
+-	do {
+-		r = amdgpu_cs_bo_validate(p, bo);
+-	} while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
++	r = amdgpu_cs_bo_validate(p, bo);
+ 	if (r)
+ 		return r;
+ 
+@@ -555,9 +492,6 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
+ 			binding_userptr = true;
+ 		}
+ 
+-		if (p->evictable == lobj)
+-			p->evictable = NULL;
+-
+ 		r = amdgpu_cs_validate(p, bo);
+ 		if (r)
+ 			return r;
+@@ -656,9 +590,6 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
+ 					  &p->bytes_moved_vis_threshold);
+ 	p->bytes_moved = 0;
+ 	p->bytes_moved_vis = 0;
+-	p->evictable = list_last_entry(&p->validated,
+-				       struct amdgpu_bo_list_entry,
+-				       tv.head);
+ 
+ 	r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
+ 				      amdgpu_cs_validate, p);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3675-drm-amdgpu-Fix-bugs-in-amdgpu_device_gpu_recover-in-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3675-drm-amdgpu-Fix-bugs-in-amdgpu_device_gpu_recover-in-.patch
new file mode 100644
index 00000000..810287e1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3675-drm-amdgpu-Fix-bugs-in-amdgpu_device_gpu_recover-in-.patch
@@ -0,0 +1,95 @@
+From 5186058f12d83bfac377975bb18adeb2c0f28268 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Fri, 30 Aug 2019 10:31:18 -0400
+Subject: [PATCH 3675/4256] drm/amdgpu: Fix bugs in amdgpu_device_gpu_recover
+ in XGMI case.
+
+Issue 1:
+In  XGMI case amdgpu_device_lock_adev for other devices in hive
+was called to late, after access to their repsective schedulers.
+So relocate the lock to the begining of accessing the other devs.
+
+Issue 2:
+Using amdgpu_device_ip_need_full_reset to switch the device list from
+all devices in hive to the single 'master' device who owns this reset
+call is wrong because when stopping schedulers we iterate all the devices
+in hive but when restarting we will only reactivate the 'master' device.
+Also, in case amdgpu_device_pre_asic_reset conlcudes that full reset IS
+needed we then have to stop schedulers for all devices in hive and not
+only the 'master' but with amdgpu_device_ip_need_full_reset  we
+already missed the opprotunity do to so. So just remove this logic and
+always stop and start all schedulers for all devices in hive.
+
+Also minor cleanup and print fix.
+
+v4: Minor coding style fix.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 23 ++++++++++------------
+ 1 file changed, 10 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index f10748306462..648852649fc2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3808,15 +3808,16 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 		device_list_handle = &device_list;
+ 	}
+ 
+-	/*
+-	 * Mark these ASICs to be reseted as untracked first
+-	 * And add them back after reset completed
+-	 */
+-	list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head)
+-		amdgpu_unregister_gpu_instance(tmp_adev);
+-
+ 	/* block all schedulers and reset given job's ring */
+ 	list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
++		if (tmp_adev != adev)
++			amdgpu_device_lock_adev(tmp_adev, false);
++		/*
++		 * Mark these ASICs to be reseted as untracked first
++		 * And add them back after reset completed
++		 */
++		amdgpu_unregister_gpu_instance(tmp_adev);
++
+ 		/* disable ras on ALL IPs */
+ 		if (amdgpu_device_ip_need_full_reset(tmp_adev))
+ 			amdgpu_ras_suspend(tmp_adev);
+@@ -3842,9 +3843,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 	    dma_fence_is_signaled(job->base.s_fence->parent))
+ 		job_signaled = true;
+ 
+-	if (!amdgpu_device_ip_need_full_reset(adev))
+-		device_list_handle = &device_list;
+-
+ 	if (job_signaled) {
+ 		dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
+ 		goto skip_hw_reset;
+@@ -3866,7 +3864,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 		if (tmp_adev == adev)
+ 			continue;
+ 
+-		amdgpu_device_lock_adev(tmp_adev, false);
+ 		r = amdgpu_device_pre_asic_reset(tmp_adev,
+ 						 NULL,
+ 						 &need_full_reset);
+@@ -3915,10 +3912,10 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 
+ 		if (r) {
+ 			/* bad news, how to tell it to userspace ? */
+-			dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
++			dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
+ 			amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
+ 		} else {
+-			dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&adev->gpu_reset_counter));
++			dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
+ 		}
+ 
+ 		amdgpu_device_unlock_adev(tmp_adev);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3676-drm-amd-amdgpu-add-sw_fini-interface-for-df_funcs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3676-drm-amd-amdgpu-add-sw_fini-interface-for-df_funcs.patch
new file mode 100644
index 00000000..27c5a257
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3676-drm-amd-amdgpu-add-sw_fini-interface-for-df_funcs.patch
@@ -0,0 +1,101 @@
+From 763506a37899ac24357dd474d102130b0e01a8bb Mon Sep 17 00:00:00 2001
+From: Jack Zhang <Jack.Zhang1@amd.com>
+Date: Tue, 3 Sep 2019 10:15:23 +0800
+Subject: [PATCH 3676/4256] drm/amd/amdgpu: add sw_fini interface for df_funcs
+
+add sw_fini interface of df_funcs.
+This interface will remove sysfs file of df_cntr_avail
+function.
+
+The old behavior only create sysfs of df_cntr_avail
+in sw_init, but never remove it for lack of sw_fini
+interface. With this,driver will report create
+sysfs fail when it's loaded for the second time.
+
+Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
+Reviewed-by: Jonathan Kim <Jonathan.Kim@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h  | 1 +
+ drivers/gpu/drm/amd/amdgpu/df_v1_7.c | 5 +++++
+ drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 8 ++++++++
+ drivers/gpu/drm/amd/amdgpu/soc15.c   | 3 +++
+ 4 files changed, 17 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index f68d78832a8e..125987f884a9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -667,6 +667,7 @@ struct amdgpu_mmio_remap {
+ 
+ struct amdgpu_df_funcs {
+ 	void (*sw_init)(struct amdgpu_device *adev);
++	void (*sw_fini)(struct amdgpu_device *adev);
+ 	void (*enable_broadcast_mode)(struct amdgpu_device *adev,
+ 				      bool enable);
+ 	u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/df_v1_7.c b/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
+index 844c03868248..d6221298b477 100644
+--- a/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
++++ b/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
+@@ -33,6 +33,10 @@ static void df_v1_7_sw_init(struct amdgpu_device *adev)
+ {
+ }
+ 
++static void df_v1_7_sw_fini(struct amdgpu_device *adev)
++{
++}
++
+ static void df_v1_7_enable_broadcast_mode(struct amdgpu_device *adev,
+                                           bool enable)
+ {
+@@ -111,6 +115,7 @@ static void df_v1_7_enable_ecc_force_par_wr_rmw(struct amdgpu_device *adev,
+ 
+ const struct amdgpu_df_funcs df_v1_7_funcs = {
+ 	.sw_init = df_v1_7_sw_init,
++	.sw_fini = df_v1_7_sw_fini,
+ 	.enable_broadcast_mode = df_v1_7_enable_broadcast_mode,
+ 	.get_fb_channel_number = df_v1_7_get_fb_channel_number,
+ 	.get_hbm_channel_number = df_v1_7_get_hbm_channel_number,
+diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+index 7f7896a69d53..72bfefdbfa65 100644
+--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
++++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+@@ -220,6 +220,13 @@ static void df_v3_6_sw_init(struct amdgpu_device *adev)
+ 		adev->df_perfmon_config_assign_mask[i] = 0;
+ }
+ 
++static void df_v3_6_sw_fini(struct amdgpu_device *adev)
++{
++
++	device_remove_file(adev->dev, &dev_attr_df_cntr_avail);
++
++}
++
+ static void df_v3_6_enable_broadcast_mode(struct amdgpu_device *adev,
+ 					  bool enable)
+ {
+@@ -538,6 +545,7 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
+ 
+ const struct amdgpu_df_funcs df_v3_6_funcs = {
+ 	.sw_init = df_v3_6_sw_init,
++	.sw_fini = df_v3_6_sw_fini,
+ 	.enable_broadcast_mode = df_v3_6_enable_broadcast_mode,
+ 	.get_fb_channel_number = df_v3_6_get_fb_channel_number,
+ 	.get_hbm_channel_number = df_v3_6_get_hbm_channel_number,
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index ae25b0928f3f..45518ef8c656 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1235,6 +1235,9 @@ static int soc15_common_sw_init(void *handle)
+ 
+ static int soc15_common_sw_fini(void *handle)
+ {
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++	adev->df_funcs->sw_fini(adev);
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3677-drm-amdgpu-change-r-type-to-int-in-gmc_v9_0_late_ini.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3677-drm-amdgpu-change-r-type-to-int-in-gmc_v9_0_late_ini.patch
new file mode 100644
index 00000000..a01e2b32
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3677-drm-amdgpu-change-r-type-to-int-in-gmc_v9_0_late_ini.patch
@@ -0,0 +1,34 @@
+From 22b46b14730dbe0af981708a283fca3527b514d9 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Mon, 2 Sep 2019 19:27:23 +0800
+Subject: [PATCH 3677/4256] drm/amdgpu: change r type to int in
+ gmc_v9_0_late_init
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+change r type from bool to int, suitable for both bool and int return
+value
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index e01fe0678243..824babb24de2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -891,7 +891,7 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ static int gmc_v9_0_late_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	bool r;
++	int r;
+ 
+ 	if (!gmc_v9_0_keep_stolen_memory(adev))
+ 		amdgpu_bo_late_init(adev);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3678-drm-amd-display-update-renoir_ip_offset.h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3678-drm-amd-display-update-renoir_ip_offset.h.patch
new file mode 100644
index 00000000..4c4be39b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3678-drm-amd-display-update-renoir_ip_offset.h.patch
@@ -0,0 +1,29 @@
+From 44f6db79244d13a844e16f024db16b6d6691ba2a Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Wed, 4 Sep 2019 13:21:42 +0800
+Subject: [PATCH 3678/4256] drm/amd/display: update renoir_ip_offset.h
+
+This patch updates MP1_BASE in renoir_ip_offset.h
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Acked-by: Roman Li <roman.li@amd.com>
+---
+ drivers/gpu/drm/amd/include/renoir_ip_offset.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/include/renoir_ip_offset.h b/drivers/gpu/drm/amd/include/renoir_ip_offset.h
+index 554714c8e000..094648cac392 100644
+--- a/drivers/gpu/drm/amd/include/renoir_ip_offset.h
++++ b/drivers/gpu/drm/amd/include/renoir_ip_offset.h
+@@ -155,7 +155,7 @@ static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x0243FC00, 0x00DC0000
+                                         { { 0, 0, 0, 0, 0 } },
+                                         { { 0, 0, 0, 0, 0 } },
+                                         { { 0, 0, 0, 0, 0 } } } };
+-static const struct IP_BASE MP1_BASE ={ { { { 0x00016200, 0x02400400, 0x00E80000, 0x00EC0000, 0x00F00000 } },
++static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x02400400, 0x00E80000, 0x00EC0000, 0x00F00000 } },
+                                         { { 0, 0, 0, 0, 0 } },
+                                         { { 0, 0, 0, 0, 0 } },
+                                         { { 0, 0, 0, 0, 0 } },
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3679-drm-amdgpu-disable-stutter-mode-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3679-drm-amdgpu-disable-stutter-mode-for-renoir.patch
new file mode 100644
index 00000000..10a7b282
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3679-drm-amdgpu-disable-stutter-mode-for-renoir.patch
@@ -0,0 +1,31 @@
+From ceaa3e71e014ff952245511678391fd79a9d037d Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Wed, 4 Sep 2019 11:47:48 +0800
+Subject: [PATCH 3679/4256] drm/amdgpu: disable stutter mode for renoir
+
+With stutter mode enabled, NMI prints frequently.
+Disable stutter for the moment because NMI warning storm, and will
+enable it back till the issue is addressed
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Acked-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index df3a5ef819dd..7d2498455d76 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -2381,6 +2381,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
+ 
+ 	if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
+ 		dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
++	if (adev->asic_type == CHIP_RENOIR)
++		dm->dc->debug.disable_stutter = true;
+ 
+ 	return 0;
+ fail:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3680-drm-amd-display-Add-stereo-mux-and-dig-programming-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3680-drm-amd-display-Add-stereo-mux-and-dig-programming-c.patch
new file mode 100644
index 00000000..ce33d7fa
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3680-drm-amd-display-Add-stereo-mux-and-dig-programming-c.patch
@@ -0,0 +1,111 @@
+From 496389f4be1e1851ca46cc2825d13b6b7f8f386b Mon Sep 17 00:00:00 2001
+From: Roman Li <Roman.Li@amd.com>
+Date: Wed, 4 Sep 2019 17:23:11 -0400
+Subject: [PATCH 3680/4256] drm/amd/display: Add stereo mux and dig programming
+ calls for dcn21
+
+[Why]
+The earlier patch "Hook up calls to do stereo mux and dig programming..."
+doesn't include update for dcn21.
+
+[How]
+Align dcn21 gpio settings with updated stereo control interface.
+
+Signed-off-by: Roman Li <Roman.Li@amd.com>
+Acked-by: Aaron Liu <aaron.liu@amd.com>
+---
+ .../display/dc/gpio/dcn21/hw_factory_dcn21.c  | 38 +++++++++++++++++--
+ .../dc/gpio/dcn21/hw_translate_dcn21.c        |  3 +-
+ 2 files changed, 36 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
+index 34485d9de78a..8572678f8d4f 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
+@@ -35,12 +35,10 @@
+ 
+ #include "hw_factory_dcn21.h"
+ 
+-
+ #include "dcn/dcn_2_1_0_offset.h"
+ #include "dcn/dcn_2_1_0_sh_mask.h"
+ #include "renoir_ip_offset.h"
+ 
+-
+ #include "reg_helper.h"
+ #include "../hpd_regs.h"
+ /* begin *********************
+@@ -136,6 +134,39 @@ static const struct ddc_sh_mask ddc_mask[] = {
+ 	DDC_MASK_SH_LIST_DCN2(_MASK, 6)
+ };
+ 
++#include "../generic_regs.h"
++
++/* set field name */
++#define SF_GENERIC(reg_name, field_name, post_fix)\
++	.field_name = reg_name ## __ ## field_name ## post_fix
++
++#define generic_regs(id) \
++{\
++	GENERIC_REG_LIST(id)\
++}
++
++static const struct generic_registers generic_regs[] = {
++	generic_regs(A),
++};
++
++static const struct generic_sh_mask generic_shift[] = {
++	GENERIC_MASK_SH_LIST(__SHIFT, A),
++};
++
++static const struct generic_sh_mask generic_mask[] = {
++	GENERIC_MASK_SH_LIST(_MASK, A),
++};
++
++static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
++{
++	struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
++
++	generic->regs = &generic_regs[en];
++	generic->shifts = &generic_shift[en];
++	generic->masks = &generic_mask[en];
++	generic->base.regs = &generic_regs[en].gpio;
++}
++
+ static void define_ddc_registers(
+ 		struct hw_gpio_pin *pin,
+ 		uint32_t en)
+@@ -181,7 +212,8 @@ static const struct hw_factory_funcs funcs = {
+ 	.get_hpd_pin = dal_hw_hpd_get_pin,
+ 	.get_generic_pin = dal_hw_generic_get_pin,
+ 	.define_hpd_registers = define_hpd_registers,
+-	.define_ddc_registers = define_ddc_registers
++	.define_ddc_registers = define_ddc_registers,
++	.define_generic_registers = define_generic_registers
+ };
+ /*
+  * dal_hw_factory_dcn10_init
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
+index ad7c43746291..fbb58fb8c318 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
+@@ -58,7 +58,6 @@
+ #define SF_HPD(reg_name, field_name, post_fix)\
+ 	.field_name = reg_name ## __ ## field_name ## post_fix
+ 
+-
+ /* macros to expend register list macro defined in HW object header file
+  * end *********************/
+ 
+@@ -71,7 +70,7 @@ static bool offset_to_id(
+ {
+ 	switch (offset) {
+ 	/* GENERIC */
+-	case REG(DC_GENERICA):
++	case REG(DC_GPIO_GENERIC_A):
+ 		*id = GPIO_ID_GENERIC;
+ 		switch (mask) {
+ 		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3681-drm-amdgpu-Determing-PTE-flags-separately-for-each-m.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3681-drm-amdgpu-Determing-PTE-flags-separately-for-each-m.patch
new file mode 100644
index 00000000..1a489960
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3681-drm-amdgpu-Determing-PTE-flags-separately-for-each-m.patch
@@ -0,0 +1,126 @@
+From 91f7a1afdf16e4c32ad768328b24eda0fd3af9c3 Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Mon, 26 Aug 2019 18:39:11 -0400
+Subject: [PATCH 3681/4256] drm/amdgpu: Determing PTE flags separately for each
+ mapping (v3)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The same BO can be mapped with different PTE flags by different GPUs.
+Therefore determine the PTE flags separately for each mapping instead
+of storing them in the KFD buffer object.
+
+Add a helper function to determine the PTE flags to be extended with
+ASIC and memory-type-specific logic in subsequent commits.
+
+v2: Split Arcturus-specific MTYPE changes into separate commit
+v3: Fix return type of get_pte_flags to uint64_t
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h    |  2 +-
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 42 +++++++++++--------
+ 2 files changed, 25 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+index a344f37e48c0..2e66505744ef 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+@@ -57,7 +57,7 @@ struct kgd_mem {
+ 	unsigned int mapped_to_gpu_memory;
+ 	uint64_t va;
+ 
+-	uint32_t mapping_flags;
++	uint32_t alloc_flags;
+ 
+ 	atomic_t invalid;
+ 	struct amdkfd_process_info *process_info;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index 7da67e5b3140..595922f63f47 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -382,6 +382,23 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
+ 	return amdgpu_sync_fence(NULL, sync, vm->last_update, false);
+ }
+ 
++static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
++{
++	bool coherent = mem->alloc_flags & ALLOC_MEM_FLAGS_COHERENT;
++	uint32_t mapping_flags;
++
++	mapping_flags = AMDGPU_VM_PAGE_READABLE;
++	if (mem->alloc_flags & ALLOC_MEM_FLAGS_WRITABLE)
++		mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
++	if (mem->alloc_flags & ALLOC_MEM_FLAGS_EXECUTABLE)
++		mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
++
++	mapping_flags |= coherent ?
++		AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
++
++	return amdgpu_gmc_get_pte_flags(adev, mapping_flags);
++}
++
+ /* add_bo_to_vm - Add a BO to a VM
+  *
+  * Everything that needs to bo done only once when a BO is first added
+@@ -430,8 +447,7 @@ static int add_bo_to_vm(struct amdgpu_device *adev, struct kgd_mem *mem,
+ 	}
+ 
+ 	bo_va_entry->va = va;
+-	bo_va_entry->pte_flags = amdgpu_gmc_get_pte_flags(adev,
+-							 mem->mapping_flags);
++	bo_va_entry->pte_flags = get_pte_flags(adev, mem);
+ 	bo_va_entry->kgd_dev = (void *)adev;
+ 	list_add(&bo_va_entry->bo_list, list_bo_va);
+ 
+@@ -1135,7 +1151,6 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
+ 	struct amdgpu_bo_param bp;
+ 	u32 domain, alloc_domain;
+ 	u64 alloc_flags;
+-	uint32_t mapping_flags;
+ 	int ret;
+ 
+ 	/*
+@@ -1195,16 +1210,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
+ 	if ((*mem)->aql_queue)
+ 		size = size >> 1;
+ 
+-	mapping_flags = AMDGPU_VM_PAGE_READABLE;
+-	if (flags & ALLOC_MEM_FLAGS_WRITABLE)
+-		mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
+-	if (flags & ALLOC_MEM_FLAGS_EXECUTABLE)
+-		mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
+-	if (flags & ALLOC_MEM_FLAGS_COHERENT)
+-		mapping_flags |= AMDGPU_VM_MTYPE_UC;
+-	else
+-		mapping_flags |= AMDGPU_VM_MTYPE_NC;
+-	(*mem)->mapping_flags = mapping_flags;
++	(*mem)->alloc_flags = flags;
+ 
+ 	amdgpu_sync_create(&(*mem)->sync);
+ 
+@@ -1844,13 +1850,13 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
+ 
+ 	INIT_LIST_HEAD(&(*mem)->bo_va_list);
+ 	mutex_init(&(*mem)->lock);
+-
+ 	if (bo->kfd_bo)
+-		(*mem)->mapping_flags = bo->kfd_bo->mapping_flags;
++		(*mem)->alloc_flags = bo->kfd_bo->alloc_flags;
+ 	else
+-		(*mem)->mapping_flags =
+-			AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
+-			AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_NC;
++		(*mem)->alloc_flags =
++			((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
++			 ALLOC_MEM_FLAGS_VRAM : ALLOC_MEM_FLAGS_GTT) |
++			ALLOC_MEM_FLAGS_WRITABLE | ALLOC_MEM_FLAGS_EXECUTABLE;
+ 
+ 	(*mem)->bo = amdgpu_bo_ref(bo);
+ 	(*mem)->va = va;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3682-drm-amdgpu-Support-new-arcturus-mtype.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3682-drm-amdgpu-Support-new-arcturus-mtype.patch
new file mode 100644
index 00000000..0f6e24bf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3682-drm-amdgpu-Support-new-arcturus-mtype.patch
@@ -0,0 +1,62 @@
+From 96c09443d1155d41372a1753574ae3cd738e2ae1 Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Fri, 26 Jul 2019 16:03:11 -0500
+Subject: [PATCH 3682/4256] drm/amdgpu: Support new arcturus mtype
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Arcturus repurposed mtype WC to RW. Modify gmc functions
+to support the new mtype
+
+Change-Id: Idc338e5386a57020f45262025e2664ab4ba9f291
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c     | 3 +++
+ drivers/gpu/drm/amd/include/vega10_enum.h | 1 +
+ include/uapi/drm/amdgpu_drm.h             | 1 +
+ 3 files changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 824babb24de2..b40acca753f0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -603,6 +603,9 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
+ 	case AMDGPU_VM_MTYPE_WC:
+ 		pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
+ 		break;
++	case AMDGPU_VM_MTYPE_RW:
++		pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
++		break;
+ 	case AMDGPU_VM_MTYPE_CC:
+ 		pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
+ 		break;
+diff --git a/drivers/gpu/drm/amd/include/vega10_enum.h b/drivers/gpu/drm/amd/include/vega10_enum.h
+index c14ba65a2415..adf1b754666e 100644
+--- a/drivers/gpu/drm/amd/include/vega10_enum.h
++++ b/drivers/gpu/drm/amd/include/vega10_enum.h
+@@ -1037,6 +1037,7 @@ TCC_CACHE_POLICY_STREAM                  = 0x00000001,
+ typedef enum MTYPE {
+ MTYPE_NC                                 = 0x00000000,
+ MTYPE_WC                                 = 0x00000001,
++MTYPE_RW                                 = 0x00000001,
+ MTYPE_CC                                 = 0x00000002,
+ MTYPE_UC                                 = 0x00000003,
+ } MTYPE;
+diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
+index 6944be414ee0..b07be841d6f5 100644
+--- a/include/uapi/drm/amdgpu_drm.h
++++ b/include/uapi/drm/amdgpu_drm.h
+@@ -559,6 +559,7 @@ struct drm_amdgpu_gem_op {
+ #define AMDGPU_VM_MTYPE_CC		(3 << 5)
+ /* Use UC MTYPE instead of default MTYPE */
+ #define AMDGPU_VM_MTYPE_UC		(4 << 5)
++#define AMDGPU_VM_MTYPE_RW		(5 << 5)
+ 
+ struct drm_amdgpu_gem_va {
+ 	/** GEM object handle */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3683-drm-amdgpu-Extends-amdgpu-vm-definitions-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3683-drm-amdgpu-Extends-amdgpu-vm-definitions-v2.patch
new file mode 100644
index 00000000..a96282d0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3683-drm-amdgpu-Extends-amdgpu-vm-definitions-v2.patch
@@ -0,0 +1,37 @@
+From e2bdf129be74d56f2968e8cce55175c0da6831c5 Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Fri, 26 Jul 2019 15:57:50 -0500
+Subject: [PATCH 3683/4256] drm/amdgpu: Extends amdgpu vm definitions (v2)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add RW mtype introduced for arcturus.
+
+v2:
+* Don't add probe-invalidation bit from UAPI
+* Don't add unused AMDGPU_MTYPE_ definitions
+
+Change-Id: Ic091c850211453b6c74c80807b1948f78addd4f6
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ include/uapi/drm/amdgpu_drm.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
+index b07be841d6f5..65d49a894cbe 100644
+--- a/include/uapi/drm/amdgpu_drm.h
++++ b/include/uapi/drm/amdgpu_drm.h
+@@ -559,6 +559,7 @@ struct drm_amdgpu_gem_op {
+ #define AMDGPU_VM_MTYPE_CC		(3 << 5)
+ /* Use UC MTYPE instead of default MTYPE */
+ #define AMDGPU_VM_MTYPE_UC		(4 << 5)
++/* Use RW MTYPE instead of default MTYPE */
+ #define AMDGPU_VM_MTYPE_RW		(5 << 5)
+ 
+ struct drm_amdgpu_gem_va {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3684-drm-amdgpu-Fix-cherry-pick-and-revert-issues-on-amdg.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3684-drm-amdgpu-Fix-cherry-pick-and-revert-issues-on-amdg.patch
new file mode 100644
index 00000000..6cfb6d7f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3684-drm-amdgpu-Fix-cherry-pick-and-revert-issues-on-amdg.patch
@@ -0,0 +1,66 @@
+From 667002b5f5a17658a56a5c686556eb847b423a44 Mon Sep 17 00:00:00 2001
+From: Adam Yang <Adam1.Yang@amd.com>
+Date: Thu, 5 Sep 2019 14:18:45 +0800
+Subject: [PATCH 3684/4256] drm/amdgpu: Fix cherry-pick and revert issues on
+ amdgpu_amdkfd_gpuvm
+
+After a series of cherry-pick, revert and re-cherry-pick on the following
+4 commits:
+
+d12c8758ea35 drm/amdgpu: Use optimal mtypes and PTE bits for Arcturus
+af441757c60a drm/amdgpu: Determing PTE flags separately for each mapping (v3)
+0d8f49a01988 drm/amdgpu: Support new arcturus mtype
+b2e1a6e14d5a drm/amdgpu: Extends amdgpu vm definitions (v2)
+
+File amdgpu_amdkfd_gpuvm.c is messed up and some of the commits
+become quite fragmented and lost part of the following commit:
+
+53a0d54498fa drm/amdgpu: Remove unnecessary TLB workaround (v2)
+
+Signed-off-by: Adam Yang <Adam1.Yang@amd.com>
+Reviewed-by: Flora Cui <flora.cui@amd.com>
+---
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 20 +++++++++++++++++--
+ 1 file changed, 18 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index 595922f63f47..7d540d5f4f9a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -384,6 +384,7 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
+ 
+ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
+ {
++	struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
+ 	bool coherent = mem->alloc_flags & ALLOC_MEM_FLAGS_COHERENT;
+ 	uint32_t mapping_flags;
+ 
+@@ -393,8 +394,23 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
+ 	if (mem->alloc_flags & ALLOC_MEM_FLAGS_EXECUTABLE)
+ 		mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
+ 
+-	mapping_flags |= coherent ?
+-		AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
++	switch (adev->asic_type) {
++	case CHIP_ARCTURUS:
++		if (mem->alloc_flags & ALLOC_MEM_FLAGS_VRAM) {
++			if (bo_adev == adev)
++				mapping_flags |= coherent ?
++					AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
++			else
++				mapping_flags |= AMDGPU_VM_MTYPE_UC;
++		} else {
++			mapping_flags |= coherent ?
++				AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
++		}
++		break;
++	default:
++		mapping_flags |= coherent ?
++			AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
++	}
+ 
+ 	return amdgpu_gmc_get_pte_flags(adev, mapping_flags);
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3685-drm-amd-powerplay-update-smu11_driver_if_navi10.h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3685-drm-amd-powerplay-update-smu11_driver_if_navi10.h.patch
new file mode 100644
index 00000000..2e36046c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3685-drm-amd-powerplay-update-smu11_driver_if_navi10.h.patch
@@ -0,0 +1,91 @@
+From 9449a714ea59e9b3d2194f90ada2ac4691fd5155 Mon Sep 17 00:00:00 2001
+From: tiancyin <tianci.yin@amd.com>
+Date: Thu, 8 Aug 2019 13:20:40 +0800
+Subject: [PATCH 3685/4256] drm/amd/powerplay: update smu11_driver_if_navi10.h
+
+update the smu11_driver_if_navi10.h since navi14 smu fw
+update to 53.12
+
+Change-Id: If0f729ec87c98f24e1794f0847eac5ba23671e34
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: tiancyin <tianci.yin@amd.com>
+---
+ .../powerplay/inc/smu11_driver_if_navi10.h    | 25 +++++++++++++++----
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  2 +-
+ 2 files changed, 21 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
+index 6d9e79e5bf9d..ac0120e384be 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
+@@ -506,10 +506,11 @@ typedef struct {
+   uint32_t Status;
+ 
+   uint16_t DieTemperature;
+-  uint16_t MemoryTemperature;
++  uint16_t CurrentMemoryTemperature;
+ 
+-  uint16_t SelectedCardPower;
+-  uint16_t Reserved4; 
++  uint16_t MemoryTemperature;
++  uint8_t MemoryHotspotPosition;
++  uint8_t Reserved4;
+ 
+   uint32_t BoardLevelEnergyAccumulator;  
+ } OutOfBandMonitor_t;
+@@ -801,7 +802,12 @@ typedef struct {
+   // Mvdd Svi2 Div Ratio Setting
+   uint32_t     MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
+ 
+-  uint32_t     BoardReserved[9];
++  uint8_t      RenesesLoadLineEnabled;
++  uint8_t      GfxLoadlineResistance;
++  uint8_t      SocLoadlineResistance;
++  uint8_t      Padding8_Loadline;
++
++  uint32_t     BoardReserved[8];
+ 
+   // Padding for MMHUB - do not modify this
+   uint32_t     MmHubPadding[8]; // SMU internal use
+@@ -904,6 +910,15 @@ typedef struct {
+   uint32_t     MmHubPadding[8]; // SMU internal use
+ } Watermarks_t;
+ 
++typedef struct {
++  uint16_t avgPsmCount[28];
++  uint16_t minPsmCount[28];
++  float    avgPsmVoltage[28];
++  float    minPsmVoltage[28];
++
++  uint32_t     MmHubPadding[32]; // SMU internal use
++} AvfsDebugTable_t_NV14;
++
+ typedef struct {
+   uint16_t avgPsmCount[36];
+   uint16_t minPsmCount[36];
+@@ -911,7 +926,7 @@ typedef struct {
+   float    minPsmVoltage[36];
+ 
+   uint32_t     MmHubPadding[8]; // SMU internal use
+-} AvfsDebugTable_t;
++} AvfsDebugTable_t_NV10;
+ 
+ typedef struct {
+   uint8_t  AvfsVersion;
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 59b2045e37e4..196a97832f6d 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -30,7 +30,7 @@
+ #define SMU11_DRIVER_IF_VERSION_ARCT 0x09
+ #define SMU11_DRIVER_IF_VERSION_NV10 0x33
+ #define SMU11_DRIVER_IF_VERSION_NV12 0x33
+-#define SMU11_DRIVER_IF_VERSION_NV14 0x33
++#define SMU11_DRIVER_IF_VERSION_NV14 0x34
+ 
+ /* MP Apertures */
+ #define MP0_Public			0x03800000
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3686-drm-amdgpu-poll-ras_controller_irq-and-err_event_ath.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3686-drm-amdgpu-poll-ras_controller_irq-and-err_event_ath.patch
new file mode 100644
index 00000000..865d3cca
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3686-drm-amdgpu-poll-ras_controller_irq-and-err_event_ath.patch
@@ -0,0 +1,43 @@
+From 9b0c90f7dc3033925e84fa61b04bd66d177e5678 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 5 Jun 2019 14:40:57 +0800
+Subject: [PATCH 3686/4256] drm/amdgpu: poll ras_controller_irq and
+ err_event_athub_irq status
+
+For the hardware that can not enable BIF ring for IH cookies for both
+ras_controller_irq and err_event_athub_irq, the driver has to poll the
+status register in irq handling and ack the hardware properly when there
+is interrupt triggered
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+index 8175a248cf69..f89c81e66ebb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+@@ -150,6 +150,18 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg)
+ 	ret = amdgpu_ih_process(adev, &adev->irq.ih);
+ 	if (ret == IRQ_HANDLED)
+ 		pm_runtime_mark_last_busy(dev->dev);
++
++	/* For the hardware that cannot enable bif ring for both ras_controller_irq
++         * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
++	 * register to check whether the interrupt is triggered or not, and properly
++	 * ack the interrupt if it is there
++	 */
++	if (adev->nbio.funcs->handle_ras_controller_intr_no_bifring)
++		adev->nbio.funcs->handle_ras_controller_intr_no_bifring(adev);
++
++	if (adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring)
++		adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
++
+ 	return ret;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3687-drm-amdgpu-irq-check-if-nbio-funcs-exist.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3687-drm-amdgpu-irq-check-if-nbio-funcs-exist.patch
new file mode 100644
index 00000000..baac8394
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3687-drm-amdgpu-irq-check-if-nbio-funcs-exist.patch
@@ -0,0 +1,36 @@
+From 76309b4cb3c8bf80bb6722092f21948c1fdf3c2d Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Sun, 1 Sep 2019 12:31:42 -0500
+Subject: [PATCH 3687/4256] drm/amdgpu/irq: check if nbio funcs exist
+
+We need to check if the nbios funcs exist before
+checking the individual pointers.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+index f89c81e66ebb..d130a30e9155 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+@@ -156,10 +156,12 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg)
+ 	 * register to check whether the interrupt is triggered or not, and properly
+ 	 * ack the interrupt if it is there
+ 	 */
+-	if (adev->nbio.funcs->handle_ras_controller_intr_no_bifring)
++	if (adev->nbio.funcs &&
++	    adev->nbio.funcs->handle_ras_controller_intr_no_bifring)
+ 		adev->nbio.funcs->handle_ras_controller_intr_no_bifring(adev);
+ 
+-	if (adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring)
++	if (adev->nbio.funcs &&
++	    adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring)
+ 		adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
+ 
+ 	return ret;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3688-drm-amdgpu-add-helper-function-to-do-common-ras_late.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3688-drm-amdgpu-add-helper-function-to-do-common-ras_late.patch
new file mode 100644
index 00000000..244f7274
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3688-drm-amdgpu-add-helper-function-to-do-common-ras_late.patch
@@ -0,0 +1,129 @@
+From df854606ec23fb0ced20f62ce6b71b48e8e98934 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Fri, 30 Aug 2019 13:29:18 +0800
+Subject: [PATCH 3688/4256] drm/amdgpu: add helper function to do common
+ ras_late_init/fini (v3)
+
+In late_init for ras, the helper function will be used to
+1). disable ras feature if the IP block is masked as disabled
+2). send enable feature command if the ip block was masked as enabled
+3). create debugfs/sysfs node per IP block
+4). register interrupt handler
+
+v2: check ih_info.cb to decide add interrupt handler or not
+
+v3: add ras_late_fini for cleanup all the ras fs node and remove
+interrupt handler
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 72 +++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h |  7 +++
+ 2 files changed, 79 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 230f7e63e4d8..2ca3997d4b3a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1564,6 +1564,78 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
+ 	return -EINVAL;
+ }
+ 
++/* helper function to handle common stuff in ip late init phase */
++int amdgpu_ras_late_init(struct amdgpu_device *adev,
++			 struct ras_common_if *ras_block,
++			 struct ras_fs_if *fs_info,
++			 struct ras_ih_if *ih_info)
++{
++	int r;
++
++	/* disable RAS feature per IP block if it is not supported */
++	if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
++		amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
++		return 0;
++	}
++
++	r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
++	if (r) {
++		if (r == -EAGAIN) {
++			/* request gpu reset. will run again */
++			amdgpu_ras_request_reset_on_boot(adev,
++					ras_block->block);
++			return 0;
++		} else if (adev->in_suspend || adev->in_gpu_reset) {
++			/* in resume phase, if fail to enable ras,
++			 * clean up all ras fs nodes, and disable ras */
++			goto cleanup;
++		} else
++			return r;
++	}
++
++	/* in resume phase, no need to create ras fs node */
++	if (adev->in_suspend || adev->in_gpu_reset)
++		return 0;
++
++	if (ih_info->cb) {
++		r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
++		if (r)
++			goto interrupt;
++	}
++
++	amdgpu_ras_debugfs_create(adev, fs_info);
++
++	r = amdgpu_ras_sysfs_create(adev, fs_info);
++	if (r)
++		goto sysfs;
++
++	return 0;
++cleanup:
++	amdgpu_ras_sysfs_remove(adev, ras_block);
++sysfs:
++	amdgpu_ras_debugfs_remove(adev, ras_block);
++	if (ih_info->cb)
++		amdgpu_ras_interrupt_remove_handler(adev, ih_info);
++interrupt:
++	amdgpu_ras_feature_enable(adev, ras_block, 0);
++	return r;
++}
++
++/* helper function to remove ras fs node and interrupt handler */
++void amdgpu_ras_late_fini(struct amdgpu_device *adev,
++			  struct ras_common_if *ras_block,
++			  struct ras_ih_if *ih_info)
++{
++	if (!ras_block || !ih_info)
++		return;
++
++	amdgpu_ras_sysfs_remove(adev, ras_block);
++	amdgpu_ras_debugfs_remove(adev, ras_block);
++	if (ih_info->cb)
++                amdgpu_ras_interrupt_remove_handler(adev, ih_info);
++	amdgpu_ras_feature_enable(adev, ras_block, 0);
++}
++
+ /* do some init work after IP late init as dependence.
+  * and it runs in resume/gpu reset/booting up cases.
+  */
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index 6c76bb2a6843..66b71525446e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -566,6 +566,13 @@ amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
+ int amdgpu_ras_init(struct amdgpu_device *adev);
+ int amdgpu_ras_fini(struct amdgpu_device *adev);
+ int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
++int amdgpu_ras_late_init(struct amdgpu_device *adev,
++			 struct ras_common_if *ras_block,
++			 struct ras_fs_if *fs_info,
++			 struct ras_ih_if *ih_info);
++void amdgpu_ras_late_fini(struct amdgpu_device *adev,
++			  struct ras_common_if *ras_block,
++			  struct ras_ih_if *ih_info);
+ 
+ int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
+ 		struct ras_common_if *head, bool enable);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3689-drm-amdgpu-only-apply-gds-clearing-workaround-when-r.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3689-drm-amdgpu-only-apply-gds-clearing-workaround-when-r.patch
new file mode 100644
index 00000000..b1fa696c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3689-drm-amdgpu-only-apply-gds-clearing-workaround-when-r.patch
@@ -0,0 +1,32 @@
+From ebcd3bb4d8998e34fa6efc8244627cd3bedbcdef Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Sat, 31 Aug 2019 14:27:13 +0800
+Subject: [PATCH 3689/4256] drm/amdgpu: only apply gds clearing workaround when
+ ras is supported
+
+gds clearing workaround should only be applied on asics that support gfx ras
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 78fea99c0d0a..d18ed269d241 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4203,6 +4203,10 @@ static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
+ 	struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
+ 	int i, r;
+ 
++	/* only support when RAS is enabled */
++	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
++		return 0;
++
+ 	r = amdgpu_ring_alloc(ring, 7);
+ 	if (r) {
+ 		DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n",
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3690-drm-amdgpu-add-ras_late_init-callback-function-for-n.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3690-drm-amdgpu-add-ras_late_init-callback-function-for-n.patch
new file mode 100644
index 00000000..b6a13f43
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3690-drm-amdgpu-add-ras_late_init-callback-function-for-n.patch
@@ -0,0 +1,111 @@
+From c265c0567b4c7886912c7d94c93fb4b636cdab83 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 29 Aug 2019 20:57:32 +0800
+Subject: [PATCH 3690/4256] drm/amdgpu: add ras_late_init callback function for
+ nbio v7_4 (v3)
+
+ras_late_init callback function will be used to do common ras
+init in late init phase.
+
+v2: call ras_late_fini to do cleanup when fails to enable interrupt
+
+v3: rename sysfs/debugfs node name to pcie_bif_xxx
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h |  2 ++
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c   | 45 ++++++++++++++++++++++++
+ 2 files changed, 47 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+index a04c5ea03418..51078da6188f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+@@ -81,12 +81,14 @@ struct amdgpu_nbio_funcs {
+ 	void (*handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device *adev);
+ 	int (*init_ras_controller_interrupt)(struct amdgpu_device *adev);
+ 	int (*init_ras_err_event_athub_interrupt)(struct amdgpu_device *adev);
++	int (*ras_late_init)(struct amdgpu_device *adev);
+ };
+ 
+ struct amdgpu_nbio {
+ 	const struct nbio_hdp_flush_reg *hdp_flush_reg;
+ 	struct amdgpu_irq_src ras_controller_irq;
+ 	struct amdgpu_irq_src ras_err_event_athub_irq;
++	struct ras_common_if *ras_if;
+ 	const struct amdgpu_nbio_funcs *funcs;
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index faf9300630a5..5e784bbd2d7f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -23,6 +23,7 @@
+ #include "amdgpu.h"
+ #include "amdgpu_atombios.h"
+ #include "nbio_v7_4.h"
++#include "amdgpu_ras.h"
+ 
+ #include "nbio/nbio_7_4_offset.h"
+ #include "nbio/nbio_7_4_sh_mask.h"
+@@ -468,6 +469,49 @@ static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *a
+ 	return 0;
+ }
+ 
++static int nbio_v7_4_ras_late_init(struct amdgpu_device *adev)
++{
++	int r;
++	struct ras_ih_if ih_info = {
++		.cb = NULL,
++	};
++	struct ras_fs_if fs_info = {
++		.sysfs_name = "pcie_bif_err_count",
++		.debugfs_name = "pcie_bif_err_inject",
++	};
++
++	if (!adev->nbio.ras_if) {
++		adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++		if (!adev->nbio.ras_if)
++			return -ENOMEM;
++		adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF;
++		adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++		adev->nbio.ras_if->sub_block_index = 0;
++		strcpy(adev->nbio.ras_if->name, "pcie_bif");
++	}
++	ih_info.head = fs_info.head = *adev->nbio.ras_if;
++	r = amdgpu_ras_late_init(adev, adev->nbio.ras_if,
++				 &fs_info, &ih_info);
++	if (r)
++		goto free;
++
++	if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
++		r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0);
++		if (r)
++			goto late_fini;
++		r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
++		if (r)
++			goto late_fini;
++	}
++
++	return 0;
++late_fini:
++	amdgpu_ras_late_fini(adev, adev->nbio.ras_if, &ih_info);
++free:
++	kfree(adev->nbio.ras_if);
++	return r;
++}
++
+ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ 	.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
+ 	.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
+@@ -493,4 +537,5 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ 	.handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
+ 	.init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,
+ 	.init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,
++	.ras_late_init = nbio_v7_4_ras_late_init,
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3691-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-gfx-v9.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3691-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-gfx-v9.patch
new file mode 100644
index 00000000..4c2c6047
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3691-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-gfx-v9.patch
@@ -0,0 +1,145 @@
+From 08122062113ca5f4b40a7f7ab32d1d20c76cf282 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 29 Aug 2019 19:15:16 +0800
+Subject: [PATCH 3691/4256] drm/amdgpu: switch to amdgpu_ras_late_init for gfx
+ v9 block (v2)
+
+call helper function in late init phase to handle ras init
+for gfx ip block
+
+v2: call ras_late_fini to do clean up when fail to enable interrupt
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 92 ++++++---------------------
+ 1 file changed, 21 insertions(+), 71 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index d18ed269d241..3f0081ca45e3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4404,7 +4404,6 @@ static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+ static int gfx_v9_0_ecc_late_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	struct ras_common_if **ras_if = &adev->gfx.ras_if;
+ 	struct ras_ih_if ih_info = {
+ 		.cb = gfx_v9_0_process_ras_data_cb,
+ 	};
+@@ -4412,18 +4411,18 @@ static int gfx_v9_0_ecc_late_init(void *handle)
+ 		.sysfs_name = "gfx_err_count",
+ 		.debugfs_name = "gfx_err_inject",
+ 	};
+-	struct ras_common_if ras_block = {
+-		.block = AMDGPU_RAS_BLOCK__GFX,
+-		.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
+-		.sub_block_index = 0,
+-		.name = "gfx",
+-	};
+ 	int r;
+ 
+-	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
+-		amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0);
+-		return 0;
++	if (!adev->gfx.ras_if) {
++		adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++		if (!adev->gfx.ras_if)
++			return -ENOMEM;
++		adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX;
++		adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++		adev->gfx.ras_if->sub_block_index = 0;
++		strcpy(adev->gfx.ras_if->name, "gfx");
+ 	}
++	fs_info.head = ih_info.head = *adev->gfx.ras_if;
+ 
+ 	r = gfx_v9_0_do_edc_gds_workarounds(adev);
+ 	if (r)
+@@ -4434,71 +4433,22 @@ static int gfx_v9_0_ecc_late_init(void *handle)
+ 	if (r)
+ 		return r;
+ 
+-	/* handle resume path. */
+-	if (*ras_if) {
+-		/* resend ras TA enable cmd during resume.
+-		 * prepare to handle failure.
+-		 */
+-		ih_info.head = **ras_if;
+-		r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
+-		if (r) {
+-			if (r == -EAGAIN) {
+-				/* request a gpu reset. will run again. */
+-				amdgpu_ras_request_reset_on_boot(adev,
+-						AMDGPU_RAS_BLOCK__GFX);
+-				return 0;
+-			}
+-			/* fail to enable ras, cleanup all. */
+-			goto irq;
+-		}
+-		/* enable successfully. continue. */
+-		goto resume;
+-	}
+-
+-	*ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
+-	if (!*ras_if)
+-		return -ENOMEM;
+-
+-	**ras_if = ras_block;
+-
+-	r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
+-	if (r) {
+-		if (r == -EAGAIN) {
+-			amdgpu_ras_request_reset_on_boot(adev,
+-					AMDGPU_RAS_BLOCK__GFX);
+-			r = 0;
+-		}
+-		goto feature;
+-	}
+-
+-	ih_info.head = **ras_if;
+-	fs_info.head = **ras_if;
+-
+-	r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
++	r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
++				 &fs_info, &ih_info);
+ 	if (r)
+-		goto interrupt;
++		goto free;
+ 
+-	amdgpu_ras_debugfs_create(adev, &fs_info);
+-
+-	r = amdgpu_ras_sysfs_create(adev, &fs_info);
+-	if (r)
+-		goto sysfs;
+-resume:
+-	r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
+-	if (r)
+-		goto irq;
++	if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) {
++		r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
++		if (r)
++			goto late_fini;
++	}
+ 
+ 	return 0;
+-irq:
+-	amdgpu_ras_sysfs_remove(adev, *ras_if);
+-sysfs:
+-	amdgpu_ras_debugfs_remove(adev, *ras_if);
+-	amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
+-interrupt:
+-	amdgpu_ras_feature_enable(adev, *ras_if, 0);
+-feature:
+-	kfree(*ras_if);
+-	*ras_if = NULL;
++late_fini:
++	amdgpu_ras_late_fini(adev, adev->gfx.ras_if, &ih_info);
++free:
++	kfree(adev->gfx.ras_if);
+ 	return r;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3692-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-gmc-v9.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3692-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-gmc-v9.patch
new file mode 100644
index 00000000..73ffdb50
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3692-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-gmc-v9.patch
@@ -0,0 +1,206 @@
+From 6ff7f722c35e13ee200a21a16ccbca4dfc52474d Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 29 Aug 2019 19:35:50 +0800
+Subject: [PATCH 3692/4256] drm/amdgpu: switch to amdgpu_ras_late_init for gmc
+ v9 block (v2)
+
+call helper function in late init phase to handle ras init
+for gmc ip block
+
+v2: call ras_late_fini to do clean up when fail to enable interrupt
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 159 ++++++++------------------
+ 1 file changed, 47 insertions(+), 112 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index b40acca753f0..786c23397350 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -761,133 +761,68 @@ static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
+-static int gmc_v9_0_ecc_ras_block_late_init(void *handle,
+-			struct ras_fs_if *fs_info, struct ras_common_if *ras_block)
+-{
+-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	struct ras_common_if **ras_if = NULL;
+-	struct ras_ih_if ih_info = {
+-		.cb = gmc_v9_0_process_ras_data_cb,
+-	};
+-	int r;
+-
+-	if (ras_block->block == AMDGPU_RAS_BLOCK__UMC)
+-		ras_if = &adev->gmc.umc_ras_if;
+-	else if (ras_block->block == AMDGPU_RAS_BLOCK__MMHUB)
+-		ras_if = &adev->gmc.mmhub_ras_if;
+-	else
+-		BUG();
+-
+-	if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
+-		amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
+-		return 0;
+-	}
+-
+-	/* handle resume path. */
+-	if (*ras_if) {
+-		/* resend ras TA enable cmd during resume.
+-		 * prepare to handle failure.
+-		 */
+-		ih_info.head = **ras_if;
+-		r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
+-		if (r) {
+-			if (r == -EAGAIN) {
+-				/* request a gpu reset. will run again. */
+-				amdgpu_ras_request_reset_on_boot(adev,
+-						ras_block->block);
+-				return 0;
+-			}
+-			/* fail to enable ras, cleanup all. */
+-			goto irq;
+-		}
+-		/* enable successfully. continue. */
+-		goto resume;
+-	}
+-
+-	*ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
+-	if (!*ras_if)
+-		return -ENOMEM;
+-
+-	**ras_if = *ras_block;
+-
+-	r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
+-	if (r) {
+-		if (r == -EAGAIN) {
+-			amdgpu_ras_request_reset_on_boot(adev,
+-					ras_block->block);
+-			r = 0;
+-		}
+-		goto feature;
+-	}
+-
+-	ih_info.head = **ras_if;
+-	fs_info->head = **ras_if;
+-
+-	if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) {
+-		r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
+-		if (r)
+-			goto interrupt;
+-	}
+-
+-	amdgpu_ras_debugfs_create(adev, fs_info);
+-
+-	r = amdgpu_ras_sysfs_create(adev, fs_info);
+-	if (r)
+-		goto sysfs;
+-resume:
+-	if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) {
+-		r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
+-		if (r)
+-			goto irq;
+-	}
+-
+-	return 0;
+-irq:
+-	amdgpu_ras_sysfs_remove(adev, *ras_if);
+-sysfs:
+-	amdgpu_ras_debugfs_remove(adev, *ras_if);
+-	if (ras_block->block == AMDGPU_RAS_BLOCK__UMC)
+-		amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
+-interrupt:
+-	amdgpu_ras_feature_enable(adev, *ras_if, 0);
+-feature:
+-	kfree(*ras_if);
+-	*ras_if = NULL;
+-	return r;
+-}
+-
+ static int gmc_v9_0_ecc_late_init(void *handle)
+ {
+ 	int r;
+-
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	struct ras_ih_if mmhub_ih_info;
+ 	struct ras_fs_if umc_fs_info = {
+ 		.sysfs_name = "umc_err_count",
+ 		.debugfs_name = "umc_err_inject",
+ 	};
+-	struct ras_common_if umc_ras_block = {
+-		.block = AMDGPU_RAS_BLOCK__UMC,
+-		.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
+-		.sub_block_index = 0,
+-		.name = "umc",
++	struct ras_ih_if umc_ih_info = {
++		.cb = gmc_v9_0_process_ras_data_cb,
+ 	};
+ 	struct ras_fs_if mmhub_fs_info = {
+ 		.sysfs_name = "mmhub_err_count",
+ 		.debugfs_name = "mmhub_err_inject",
+ 	};
+-	struct ras_common_if mmhub_ras_block = {
+-		.block = AMDGPU_RAS_BLOCK__MMHUB,
+-		.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
+-		.sub_block_index = 0,
+-		.name = "mmhub",
+-	};
+ 
+-	r = gmc_v9_0_ecc_ras_block_late_init(handle,
+-			&umc_fs_info, &umc_ras_block);
++	if (!adev->gmc.umc_ras_if) {
++		adev->gmc.umc_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++		if (!adev->gmc.umc_ras_if)
++			return -ENOMEM;
++		adev->gmc.umc_ras_if->block = AMDGPU_RAS_BLOCK__UMC;
++		adev->gmc.umc_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++		adev->gmc.umc_ras_if->sub_block_index = 0;
++		strcpy(adev->gmc.umc_ras_if->name, "umc");
++	}
++	umc_ih_info.head = umc_fs_info.head = *adev->gmc.umc_ras_if;
++
++	r = amdgpu_ras_late_init(adev, adev->gmc.umc_ras_if,
++				 &umc_fs_info, &umc_ih_info);
+ 	if (r)
+-		return r;
++		goto free;
+ 
+-	r = gmc_v9_0_ecc_ras_block_late_init(handle,
+-			&mmhub_fs_info, &mmhub_ras_block);
++	if (amdgpu_ras_is_supported(adev, adev->gmc.umc_ras_if->block)) {
++		r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
++		if (r)
++			goto umc_late_fini;
++	}
++
++	if (!adev->gmc.mmhub_ras_if) {
++		adev->gmc.mmhub_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++		if (!adev->gmc.mmhub_ras_if)
++			return -ENOMEM;
++		adev->gmc.mmhub_ras_if->block = AMDGPU_RAS_BLOCK__MMHUB;
++		adev->gmc.mmhub_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++		adev->gmc.mmhub_ras_if->sub_block_index = 0;
++		strcpy(adev->gmc.mmhub_ras_if->name, "mmhub");
++	}
++	mmhub_ih_info.head = mmhub_fs_info.head = *adev->gmc.mmhub_ras_if;
++	r = amdgpu_ras_late_init(adev, adev->gmc.mmhub_ras_if,
++				 &mmhub_fs_info, &mmhub_ih_info);
++	if (r)
++		goto mmhub_late_fini;
++
++	return 0;
++mmhub_late_fini:
++	amdgpu_ras_late_fini(adev, adev->gmc.mmhub_ras_if, &mmhub_ih_info);
++umc_late_fini:
++	amdgpu_ras_late_fini(adev, adev->gmc.umc_ras_if, &umc_ih_info);
++free:
++	kfree(adev->gmc.umc_ras_if);
++	kfree(adev->gmc.mmhub_ras_if);
+ 	return r;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3693-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-sdma-v.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3693-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-sdma-v.patch
new file mode 100644
index 00000000..233ea4cd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3693-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-sdma-v.patch
@@ -0,0 +1,145 @@
+From 08d3260b2953c907a787a65805b1887e14079784 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 29 Aug 2019 19:30:02 +0800
+Subject: [PATCH 3693/4256] drm/amdgpu: switch to amdgpu_ras_late_init for sdma
+ v4 block (v2)
+
+call helper function in late init phase to handle ras init
+for sdma ip block
+
+v2: call ras_late_fini to do clean up when fail to enable interrupt
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 98 +++++++-------------------
+ 1 file changed, 24 insertions(+), 74 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 7461d52e0b6e..abad7f14610b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1695,7 +1695,6 @@ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
+ static int sdma_v4_0_late_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	struct ras_common_if **ras_if = &adev->sdma.ras_if;
+ 	struct ras_ih_if ih_info = {
+ 		.cb = sdma_v4_0_process_ras_data_cb,
+ 	};
+@@ -1703,87 +1702,38 @@ static int sdma_v4_0_late_init(void *handle)
+ 		.sysfs_name = "sdma_err_count",
+ 		.debugfs_name = "sdma_err_inject",
+ 	};
+-	struct ras_common_if ras_block = {
+-		.block = AMDGPU_RAS_BLOCK__SDMA,
+-		.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
+-		.sub_block_index = 0,
+-		.name = "sdma",
+-	};
+ 	int r, i;
+ 
+-	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
+-		amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0);
+-		return 0;
+-	}
+-
+-	/* handle resume path. */
+-	if (*ras_if) {
+-		/* resend ras TA enable cmd during resume.
+-		 * prepare to handle failure.
+-		 */
+-		ih_info.head = **ras_if;
+-		r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
+-		if (r) {
+-			if (r == -EAGAIN) {
+-				/* request a gpu reset. will run again. */
+-				amdgpu_ras_request_reset_on_boot(adev,
+-						AMDGPU_RAS_BLOCK__SDMA);
+-				return 0;
+-			}
+-			/* fail to enable ras, cleanup all. */
+-			goto irq;
+-		}
+-		/* enable successfully. continue. */
+-		goto resume;
+-	}
+-
+-	*ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
+-	if (!*ras_if)
+-		return -ENOMEM;
+-
+-	**ras_if = ras_block;
+-
+-	r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
+-	if (r) {
+-		if (r == -EAGAIN) {
+-			amdgpu_ras_request_reset_on_boot(adev,
+-					AMDGPU_RAS_BLOCK__SDMA);
+-			r = 0;
+-		}
+-		goto feature;
++	if (!adev->sdma.ras_if) {
++		adev->sdma.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++		if (!adev->sdma.ras_if)
++			return -ENOMEM;
++		adev->sdma.ras_if->block = AMDGPU_RAS_BLOCK__SDMA;
++		adev->sdma.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++		adev->sdma.ras_if->sub_block_index = 0;
++		strcpy(adev->sdma.ras_if->name, "sdma");
+ 	}
++	fs_info.head = ih_info.head = *adev->sdma.ras_if;
+ 
+-	ih_info.head = **ras_if;
+-	fs_info.head = **ras_if;
+-
+-	r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
++	r = amdgpu_ras_late_init(adev, adev->sdma.ras_if,
++				 &fs_info, &ih_info);
+ 	if (r)
+-		goto interrupt;
+-
+-	amdgpu_ras_debugfs_create(adev, &fs_info);
++		goto free;
+ 
+-	r = amdgpu_ras_sysfs_create(adev, &fs_info);
+-	if (r)
+-		goto sysfs;
+-resume:
+-	for (i = 0; i < adev->sdma.num_instances; i++) {
+-		r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq,
+-				   AMDGPU_SDMA_IRQ_INSTANCE0 + i);
+-		if (r)
+-			goto irq;
++	if (amdgpu_ras_is_supported(adev, adev->sdma.ras_if->block)) {
++		for (i = 0; i < adev->sdma.num_instances; i++) {
++			r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq,
++				AMDGPU_SDMA_IRQ_INSTANCE0 + i);
++			if (r)
++				goto late_fini;
++		}
+ 	}
+ 
+-	return 0;
+-irq:
+-	amdgpu_ras_sysfs_remove(adev, *ras_if);
+-sysfs:
+-	amdgpu_ras_debugfs_remove(adev, *ras_if);
+-	amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
+-interrupt:
+-	amdgpu_ras_feature_enable(adev, *ras_if, 0);
+-feature:
+-	kfree(*ras_if);
+-	*ras_if = NULL;
++        return 0;
++late_fini:
++	amdgpu_ras_late_fini(adev, adev->sdma.ras_if, &ih_info);
++free:
++	kfree(adev->sdma.ras_if);
+ 	return r;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3694-drm-amdgpu-add-mmhub-ras_late_init-callback-function.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3694-drm-amdgpu-add-mmhub-ras_late_init-callback-function.patch
new file mode 100644
index 00000000..aed4f313
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3694-drm-amdgpu-add-mmhub-ras_late_init-callback-function.patch
@@ -0,0 +1,141 @@
+From 812eefae55fce429c2b2056c4bbfc7ecbb039560 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Fri, 30 Aug 2019 13:34:38 +0800
+Subject: [PATCH 3694/4256] drm/amdgpu: add mmhub ras_late_init callback
+ function (v2)
+
+The function will be called in late init phase to do mmhub
+ras init
+
+v2: check ras_late_init function pointer before invoking the
+function
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h |  1 +
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c     | 26 +++-----------------
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c   | 30 +++++++++++++++++++++++
+ 3 files changed, 35 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
+index 2d75ecfa199b..df04c718dfab 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
+@@ -23,6 +23,7 @@
+ 
+ struct amdgpu_mmhub_funcs {
+ 	void (*ras_init)(struct amdgpu_device *adev);
++	int (*ras_late_init)(struct amdgpu_device *adev);
+ 	void (*query_ras_error_count)(struct amdgpu_device *adev,
+ 					void *ras_error_status);
+ };
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 786c23397350..baefc8a3a2bb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -765,7 +765,6 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ {
+ 	int r;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	struct ras_ih_if mmhub_ih_info;
+ 	struct ras_fs_if umc_fs_info = {
+ 		.sysfs_name = "umc_err_count",
+ 		.debugfs_name = "umc_err_inject",
+@@ -773,10 +772,6 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ 	struct ras_ih_if umc_ih_info = {
+ 		.cb = gmc_v9_0_process_ras_data_cb,
+ 	};
+-	struct ras_fs_if mmhub_fs_info = {
+-		.sysfs_name = "mmhub_err_count",
+-		.debugfs_name = "mmhub_err_inject",
+-	};
+ 
+ 	if (!adev->gmc.umc_ras_if) {
+ 		adev->gmc.umc_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
+@@ -800,29 +795,16 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ 			goto umc_late_fini;
+ 	}
+ 
+-	if (!adev->gmc.mmhub_ras_if) {
+-		adev->gmc.mmhub_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
+-		if (!adev->gmc.mmhub_ras_if)
+-			return -ENOMEM;
+-		adev->gmc.mmhub_ras_if->block = AMDGPU_RAS_BLOCK__MMHUB;
+-		adev->gmc.mmhub_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
+-		adev->gmc.mmhub_ras_if->sub_block_index = 0;
+-		strcpy(adev->gmc.mmhub_ras_if->name, "mmhub");
++	if (adev->mmhub_funcs->ras_late_init) {
++		r = adev->mmhub_funcs->ras_late_init(adev);
++		if (r)
++			return r;
+ 	}
+-	mmhub_ih_info.head = mmhub_fs_info.head = *adev->gmc.mmhub_ras_if;
+-	r = amdgpu_ras_late_init(adev, adev->gmc.mmhub_ras_if,
+-				 &mmhub_fs_info, &mmhub_ih_info);
+-	if (r)
+-		goto mmhub_late_fini;
+-
+ 	return 0;
+-mmhub_late_fini:
+-	amdgpu_ras_late_fini(adev, adev->gmc.mmhub_ras_if, &mmhub_ih_info);
+ umc_late_fini:
+ 	amdgpu_ras_late_fini(adev, adev->gmc.umc_ras_if, &umc_ih_info);
+ free:
+ 	kfree(adev->gmc.umc_ras_if);
+-	kfree(adev->gmc.mmhub_ras_if);
+ 	return r;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index 732aba77ab73..5793d56fc7ea 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -31,6 +31,7 @@
+ #include "vega10_enum.h"
+ 
+ #include "soc15_common.h"
++#include "amdgpu_ras.h"
+ 
+ #define mmDAGB0_CNTL_MISC2_RV 0x008f
+ #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
+@@ -615,6 +616,35 @@ static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev,
+ 	}
+ }
+ 
++static int mmhub_v1_0_ras_late_init(struct amdgpu_device *adev)
++{
++	int r;
++	struct ras_ih_if mmhub_ih_info = {
++		.cb = NULL,
++	};
++	struct ras_fs_if mmhub_fs_info = {
++		.sysfs_name = "mmhub_err_count",
++		.debugfs_name = "mmhub_err_inject",
++	};
++
++	if (!adev->gmc.mmhub_ras_if) {
++		adev->gmc.mmhub_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++		if (!adev->gmc.mmhub_ras_if)
++			return -ENOMEM;
++		adev->gmc.mmhub_ras_if->block = AMDGPU_RAS_BLOCK__MMHUB;
++		adev->gmc.mmhub_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++		adev->gmc.mmhub_ras_if->sub_block_index = 0;
++		strcpy(adev->gmc.mmhub_ras_if->name, "mmhub");
++	}
++	mmhub_ih_info.head = mmhub_fs_info.head = *adev->gmc.mmhub_ras_if;
++	r = amdgpu_ras_late_init(adev, adev->gmc.mmhub_ras_if,
++				 &mmhub_fs_info, &mmhub_ih_info);
++	if (r)
++		kfree(adev->gmc.mmhub_ras_if);
++	return r;
++}
++
+ const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {
++	.ras_late_init = mmhub_v1_0_ras_late_init,
+ 	.query_ras_error_count = mmhub_v1_0_query_ras_error_count,
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3695-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-nbio-v.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3695-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-nbio-v.patch
new file mode 100644
index 00000000..5042ff06
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3695-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-nbio-v.patch
@@ -0,0 +1,57 @@
+From 91dbf0f415f9f3965df78c1b343e789612689fdc Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Thu, 29 Aug 2019 19:56:44 +0800
+Subject: [PATCH 3695/4256] drm/amdgpu: switch to amdgpu_ras_late_init for nbio
+ v7_4 (v2)
+
+call helper function in late init phase to handle ras init
+for nbio ip block
+
+v2: init local var r to 0 in case the function return failure
+on asics that don't have ras_late_init implementation
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 45518ef8c656..cb22970c0853 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1214,11 +1214,15 @@ static int soc15_common_early_init(void *handle)
+ static int soc15_common_late_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	int r = 0;
+ 
+ 	if (amdgpu_sriov_vf(adev))
+ 		xgpu_ai_mailbox_get_irq(adev);
+ 
+-	return 0;
++	if (adev->nbio.funcs->ras_late_init)
++		r = adev->nbio.funcs->ras_late_init(adev);
++
++	return r;
+ }
+ 
+ static int soc15_common_sw_init(void *handle)
+@@ -1298,6 +1302,13 @@ static int soc15_common_hw_fini(void *handle)
+ 	if (amdgpu_sriov_vf(adev))
+ 		xgpu_ai_mailbox_put_irq(adev);
+ 
++	if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
++		if (adev->nbio.funcs->init_ras_controller_interrupt)
++			amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
++		if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
++			amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
++	}
++
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3696-drm-amdgpu-check-mmhub_funcs-pointer-before-refering.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3696-drm-amdgpu-check-mmhub_funcs-pointer-before-refering.patch
new file mode 100644
index 00000000..e9a91f4d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3696-drm-amdgpu-check-mmhub_funcs-pointer-before-refering.patch
@@ -0,0 +1,30 @@
+From 422e0ecc4fa87e81e570be45cee5471d1ffaaf00 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Sat, 31 Aug 2019 13:18:40 +0800
+Subject: [PATCH 3696/4256] drm/amdgpu: check mmhub_funcs pointer before
+ refering to it
+
+mmhub callback functions are not initialized for all the ASICs
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index baefc8a3a2bb..81352d01fbee 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -795,7 +795,7 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ 			goto umc_late_fini;
+ 	}
+ 
+-	if (adev->mmhub_funcs->ras_late_init) {
++	if (adev->mmhub_funcs && adev->mmhub_funcs->ras_late_init) {
+ 		r = adev->mmhub_funcs->ras_late_init(adev);
+ 		if (r)
+ 			return r;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3697-drm-amdgpu-fix-memory-leak-when-ras-is-not-supported.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3697-drm-amdgpu-fix-memory-leak-when-ras-is-not-supported.patch
new file mode 100644
index 00000000..2eec0b03
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3697-drm-amdgpu-fix-memory-leak-when-ras-is-not-supported.patch
@@ -0,0 +1,75 @@
+From 6426b4c5639b36f5f9e82f349c98bc12f185f286 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Sat, 31 Aug 2019 14:20:38 +0800
+Subject: [PATCH 3697/4256] drm/amdgpu: fix memory leak when ras is not
+ supported on specific ip block
+
+free ras_if if ras is not supported
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c  | 3 ++-
+ 4 files changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 3f0081ca45e3..384fc226ecb5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4442,7 +4442,8 @@ static int gfx_v9_0_ecc_late_init(void *handle)
+ 		r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
+ 		if (r)
+ 			goto late_fini;
+-	}
++	} else
++		kfree(adev->gfx.ras_if);
+ 
+ 	return 0;
+ late_fini:
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 81352d01fbee..4a19647edfea 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -793,7 +793,8 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ 		r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
+ 		if (r)
+ 			goto umc_late_fini;
+-	}
++	} else
++		kfree(adev->gmc.umc_ras_if);
+ 
+ 	if (adev->mmhub_funcs && adev->mmhub_funcs->ras_late_init) {
+ 		r = adev->mmhub_funcs->ras_late_init(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index 5793d56fc7ea..ece27e27658f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -639,7 +639,7 @@ static int mmhub_v1_0_ras_late_init(struct amdgpu_device *adev)
+ 	mmhub_ih_info.head = mmhub_fs_info.head = *adev->gmc.mmhub_ras_if;
+ 	r = amdgpu_ras_late_init(adev, adev->gmc.mmhub_ras_if,
+ 				 &mmhub_fs_info, &mmhub_ih_info);
+-	if (r)
++	if (r || !amdgpu_ras_is_supported(adev, adev->gmc.mmhub_ras_if->block))
+ 		kfree(adev->gmc.mmhub_ras_if);
+ 	return r;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index abad7f14610b..72840582f716 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1727,7 +1727,8 @@ static int sdma_v4_0_late_init(void *handle)
+ 			if (r)
+ 				goto late_fini;
+ 		}
+-	}
++	} else
++		kfree(adev->sdma.ras_if);
+ 
+         return 0;
+ late_fini:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3698-drm-amdgpu-Fix-undefined-dm_ip_block-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3698-drm-amdgpu-Fix-undefined-dm_ip_block-for-navi12.patch
new file mode 100644
index 00000000..16d861f0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3698-drm-amdgpu-Fix-undefined-dm_ip_block-for-navi12.patch
@@ -0,0 +1,33 @@
+From ae25c97b48c92242369c5d4dcb7284cb7871500b Mon Sep 17 00:00:00 2001
+From: Petr Cvek <petrcvekcz@gmail.com>
+Date: Fri, 30 Aug 2019 16:31:58 +0200
+Subject: [PATCH 3698/4256] drm/amdgpu: Fix undefined dm_ip_block for navi12
+
+There is missing "if defined" CONFIG_DRM_AMD_DC block for non DC
+configurations. This will cause link error. The patch is fixing that.
+
+Bug: https://bugs.freedesktop.org/show_bug.cgi?id=110979
+Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 585fc7dce39d..a61f43c0c9df 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -461,8 +461,10 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ 			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+ 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
++#if defined(CONFIG_DRM_AMD_DC)
+ 		else if (amdgpu_device_has_dc_support(adev))
+ 			amdgpu_device_ip_block_add(adev, &dm_ip_block);
++#endif
+ 		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
+ 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3699-drm-amdgpu-psp-move-TMR-to-cpu-invisible-vram-region.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3699-drm-amdgpu-psp-move-TMR-to-cpu-invisible-vram-region.patch
new file mode 100644
index 00000000..83339760
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3699-drm-amdgpu-psp-move-TMR-to-cpu-invisible-vram-region.patch
@@ -0,0 +1,49 @@
+From 2be5d8b7386f0c8e057ba744273efb03898814a4 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Mon, 19 Aug 2019 15:30:22 +0800
+Subject: [PATCH 3699/4256] drm/amdgpu/psp: move TMR to cpu invisible vram
+ region
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+so that more visible vram can be available for umd.
+
+Reviewed-by: Christian König <christian.koenig@amd.com>.
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h    | 1 -
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+index c983b386889c..83df25888e02 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+@@ -267,8 +267,9 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
+ 	bp.size = size;
+ 	bp.byte_align = align;
+ 	bp.domain = domain;
+-	bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+-		AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
++	bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
++		: AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
++	bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+ 	bp.type = ttm_bo_type_kernel;
+ 	bp.resv = NULL;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+index b73d4aa28fba..bc0947f6bc8a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+@@ -171,7 +171,6 @@ struct psp_context
+ 	/* tmr buffer */
+ 	struct amdgpu_bo		*tmr_bo;
+ 	uint64_t			tmr_mc_addr;
+-	void				*tmr_buf;
+ 
+ 	/* asd firmware and buffer */
+ 	const struct firmware		*asd_fw;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3700-drm-amdgpu-clean-up-load-TMR-sequence.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3700-drm-amdgpu-clean-up-load-TMR-sequence.patch
new file mode 100644
index 00000000..9bf2d9c9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3700-drm-amdgpu-clean-up-load-TMR-sequence.patch
@@ -0,0 +1,37 @@
+From 70ba1ec93fc9d2e412476aa9a5259458f8d87f50 Mon Sep 17 00:00:00 2001
+From: John Clements <john.clements@amd.com>
+Date: Wed, 4 Sep 2019 16:23:27 +0800
+Subject: [PATCH 3700/4256] drm/amdgpu: clean up load TMR sequence
+
+Removed redundant goto statement
+
+Change-Id: I480b057f0ca3988c59140df8f5b46d59adf52bdc
+Signed-off-by: John Clements <john.clements@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index d0d8f15e16f1..d92444ac1fc5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -290,15 +290,9 @@ static int psp_tmr_load(struct psp_context *psp)
+ 
+ 	ret = psp_cmd_submit_buf(psp, NULL, cmd,
+ 				 psp->fence_buf_mc_addr);
+-	if (ret)
+-		goto failed;
+ 
+ 	kfree(cmd);
+ 
+-	return 0;
+-
+-failed:
+-	kfree(cmd);
+ 	return ret;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3701-drm-amd-powerplay-implement-sysfs-for-getting-dpm-cl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3701-drm-amd-powerplay-implement-sysfs-for-getting-dpm-cl.patch
new file mode 100644
index 00000000..9bb32cb4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3701-drm-amd-powerplay-implement-sysfs-for-getting-dpm-cl.patch
@@ -0,0 +1,146 @@
+From e36e655f16c39980e58f078dfc0ce1bc4fa41fac Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Wed, 4 Sep 2019 16:34:39 +0800
+Subject: [PATCH 3701/4256] drm/amd/powerplay: implement sysfs for getting dpm
+ clock
+
+With the common interface print_clk_levels can get the following dpm clock:
+
+-pp_dpm_dcefclk
+-pp_dpm_fclk
+-pp_dpm_mclk
+-pp_dpm_sclk
+-pp_dpm_socclk
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 70 ++++++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 25 ++++++++
+ 2 files changed, 95 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 872598c19a5d..b7fa8b158ff2 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -177,12 +177,82 @@ static int renoir_get_dpm_uclk_limited(struct smu_context *smu, uint32_t *clock,
+ 
+ }
+ 
++static int renoir_print_clk_levels(struct smu_context *smu,
++			enum smu_clk_type clk_type, char *buf)
++{
++	int i, size = 0, ret = 0;
++	uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
++	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
++	SmuMetrics_t metrics = {0};
++
++	if (!clk_table || clk_type >= SMU_CLK_COUNT)
++		return -EINVAL;
++
++	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
++			       (void *)&metrics, false);
++	if (ret)
++		return ret;
++
++	switch (clk_type) {
++	case SMU_GFXCLK:
++	case SMU_SCLK:
++		/* retirve table returned paramters unit is MHz */
++		cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
++		ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min, &max);
++		if (!ret) {
++			/* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
++			if (cur_value  == max)
++				i = 2;
++			else if (cur_value == min)
++				i = 0;
++			else
++				i = 1;
++
++			size += sprintf(buf + size, "0: %uMhz %s\n", min,
++					i == 0 ? "*" : "");
++			size += sprintf(buf + size, "1: %uMhz %s\n",
++					i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK,
++					i == 1 ? "*" : "");
++			size += sprintf(buf + size, "2: %uMhz %s\n", max,
++					i == 2 ? "*" : "");
++		}
++		return size;
++	case SMU_SOCCLK:
++		count = NUM_SOCCLK_DPM_LEVELS;
++		cur_value = metrics.ClockFrequency[CLOCK_SOCCLK];
++		break;
++	case SMU_MCLK:
++		count = NUM_MEMCLK_DPM_LEVELS;
++		cur_value = metrics.ClockFrequency[CLOCK_UMCCLK];
++		break;
++	case SMU_DCEFCLK:
++		count = NUM_DCFCLK_DPM_LEVELS;
++		cur_value = metrics.ClockFrequency[CLOCK_DCFCLK];
++		break;
++	case SMU_FCLK:
++		count = NUM_FCLK_DPM_LEVELS;
++		cur_value = metrics.ClockFrequency[CLOCK_FCLK];
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	for (i = 0; i < count; i++) {
++		GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
++		size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
++				cur_value == value ? "*" : "");
++	}
++
++	return size;
++}
++
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_smu_msg_index = renoir_get_smu_msg_index,
+ 	.get_smu_table_index = renoir_get_smu_table_index,
+ 	.tables_init = renoir_tables_init,
+ 	.set_power_state = NULL,
+ 	.get_dpm_uclk_limited = renoir_get_dpm_uclk_limited,
++	.print_clk_levels = renoir_print_clk_levels,
+ };
+ 
+ void renoir_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+index e9b7237c0f7f..2a390ddd37dd 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
+@@ -25,4 +25,29 @@
+ 
+ extern void renoir_set_ppt_funcs(struct smu_context *smu);
+ 
++/* UMD PState Renoir Msg Parameters in MHz */
++#define RENOIR_UMD_PSTATE_GFXCLK       700
++#define RENOIR_UMD_PSTATE_SOCCLK       678
++#define RENOIR_UMD_PSTATE_FCLK         800
++
++#define GET_DPM_CUR_FREQ(table, clk_type, dpm_level, freq)		\
++	do {								\
++		switch (clk_type) {					\
++		case SMU_SOCCLK:					\
++			freq = table->SocClocks[dpm_level].Freq;	\
++			break;						\
++		case SMU_MCLK:						\
++			freq = table->MemClocks[dpm_level].Freq;	\
++			break;						\
++		case SMU_DCEFCLK:					\
++			freq = table->DcfClocks[dpm_level].Freq;	\
++			break;						\
++		case SMU_FCLK:						\
++			freq = table->FClocks[dpm_level].Freq;		\
++			break;						\
++		default:						\
++			break;						\
++		}							\
++	} while (0)
++
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3702-drm-amdgpu-Disable-page-faults-while-reading-user-wp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3702-drm-amdgpu-Disable-page-faults-while-reading-user-wp.patch
new file mode 100644
index 00000000..ccd2aabc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3702-drm-amdgpu-Disable-page-faults-while-reading-user-wp.patch
@@ -0,0 +1,50 @@
+From 34d07e97a265ad0617f503129c3a0ac705a80018 Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Fri, 30 Aug 2019 00:10:34 -0400
+Subject: [PATCH 3702/4256] drm/amdgpu: Disable page faults while reading user
+ wptrs
+
+These wptrs must be pinned and GPU accessible when this is called
+from hqd_load functions. So they should never fault. This resolves
+a circular lock dependency issue involving four locks including the
+DQM lock and mmap_sem.
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Oak Zeng <Oak.Zeng@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+index 2e66505744ef..938952563a62 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+@@ -184,10 +184,17 @@ uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd);
+ uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd);
+ uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src);
+ 
++/* Read user wptr from a specified user address space with page fault
++ * disabled. The memory must be pinned and mapped to the hardware when
++ * this is called in hqd_load functions, so it should never fault in
++ * the first place. This resolves a circular lock dependency involving
++ * four locks, including the DQM lock and mmap_sem.
++ */
+ #define read_user_wptr(mmptr, wptr, dst)				\
+ 	({								\
+ 		bool valid = false;					\
+ 		if ((mmptr) && (wptr)) {				\
++			pagefault_disable();				\
+ 			if ((mmptr) == current->mm) {			\
+ 				valid = !get_user((dst), (wptr));	\
+ 			} else if (current->mm == NULL) {		\
+@@ -195,6 +202,7 @@ uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *s
+ 				valid = !get_user((dst), (wptr));	\
+ 				unuse_mm(mmptr);			\
+ 			}						\
++			pagefault_enable();				\
+ 		}							\
+ 		valid;							\
+ 	})
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3703-drm-amdkfd-Query-kfd-device-info-by-CHIP-id-instead-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3703-drm-amdkfd-Query-kfd-device-info-by-CHIP-id-instead-.patch
new file mode 100644
index 00000000..13055fc7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3703-drm-amdkfd-Query-kfd-device-info-by-CHIP-id-instead-.patch
@@ -0,0 +1,300 @@
+From d789c4c97bc1c3f3778b5de65f43eda65718fcd1 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Tue, 3 Sep 2019 17:55:30 -0400
+Subject: [PATCH 3703/4256] drm/amdkfd: Query kfd device info by CHIP id
+ instead of pci device id
+
+This optimizes out the pci device id usage in KFD and makes the code
+more maintainable.
+
+Change-Id: Ie65d4164b8344fd6116bf9a4140c653090336362
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c |   6 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h |   3 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c    | 177 ++++-----------------
+ include/drm/amd_asic_type.h                |   2 +
+ 5 files changed, 37 insertions(+), 153 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+index 8a1ba9c93e12..9ad94eeda69f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+@@ -70,6 +70,7 @@ void amdgpu_amdkfd_fini(void)
+ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
+ {
+ 	const struct kfd2kgd_calls *kfd2kgd;
++	bool vf = amdgpu_sriov_vf(adev);
+ 
+ 
+ 	switch (adev->asic_type) {
+@@ -108,7 +109,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
+ 	}
+ 
+ 	adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
+-				      adev->pdev, kfd2kgd);
++				      adev->pdev, kfd2kgd, adev->asic_type, vf);
+ 
+ 	if (adev->kfd.dev)
+ 		amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
+@@ -757,7 +758,8 @@ struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions(void)
+ }
+ 
+ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
+-			      const struct kfd2kgd_calls *f2g)
++			      const struct kfd2kgd_calls *f2g,
++			      unsigned int asic_type, bool vf)
+ {
+ 	return NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+index 938952563a62..a41fe657ba2a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+@@ -262,7 +262,8 @@ void amdgpu_amdkfd_debug_mem_fence(struct kgd_dev *kgd);
+ int kgd2kfd_init(void);
+ void kgd2kfd_exit(void);
+ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
+-			      const struct kfd2kgd_calls *f2g);
++			      const struct kfd2kgd_calls *f2g,
++			      unsigned int asic_type, bool vf);
+ bool kgd2kfd_device_init(struct kfd_dev *kfd,
+ 			 struct drm_device *ddev,
+ 			 const struct kgd2kfd_shared_resources *gpu_resources);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 648852649fc2..b7276f9e814b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -77,7 +77,7 @@ MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
+ 
+ #define AMDGPU_RESUME_MS		2000
+ 
+-static const char *amdgpu_asic_name[] = {
++const char *amdgpu_asic_name[] = {
+ 	"TAHITI",
+ 	"PITCAIRN",
+ 	"VERDE",
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index d8344f9dc7e0..51a85fd20475 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -369,133 +369,23 @@ static const struct kfd_device_info navi10_device_info = {
+ 	.num_sdma_queues_per_engine = 8,
+ };
+ 
+-struct kfd_deviceid {
+-	unsigned short did;
+-	const struct kfd_device_info *device_info;
+-};
+-
+-static const struct kfd_deviceid supported_devices[] = {
+-#ifdef KFD_SUPPORT_IOMMU_V2
+-	{ 0x1304, &kaveri_device_info },	/* Kaveri */
+-	{ 0x1305, &kaveri_device_info },	/* Kaveri */
+-	{ 0x1306, &kaveri_device_info },	/* Kaveri */
+-	{ 0x1307, &kaveri_device_info },	/* Kaveri */
+-	{ 0x1309, &kaveri_device_info },	/* Kaveri */
+-	{ 0x130A, &kaveri_device_info },	/* Kaveri */
+-	{ 0x130B, &kaveri_device_info },	/* Kaveri */
+-	{ 0x130C, &kaveri_device_info },	/* Kaveri */
+-	{ 0x130D, &kaveri_device_info },	/* Kaveri */
+-	{ 0x130E, &kaveri_device_info },	/* Kaveri */
+-	{ 0x130F, &kaveri_device_info },	/* Kaveri */
+-	{ 0x1310, &kaveri_device_info },	/* Kaveri */
+-	{ 0x1311, &kaveri_device_info },	/* Kaveri */
+-	{ 0x1312, &kaveri_device_info },	/* Kaveri */
+-	{ 0x1313, &kaveri_device_info },	/* Kaveri */
+-	{ 0x1315, &kaveri_device_info },	/* Kaveri */
+-	{ 0x1316, &kaveri_device_info },	/* Kaveri */
+-	{ 0x1317, &kaveri_device_info },	/* Kaveri */
+-	{ 0x1318, &kaveri_device_info },	/* Kaveri */
+-	{ 0x131B, &kaveri_device_info },	/* Kaveri */
+-	{ 0x131C, &kaveri_device_info },	/* Kaveri */
+-	{ 0x131D, &kaveri_device_info },	/* Kaveri */
+-	{ 0x9870, &carrizo_device_info },	/* Carrizo */
+-	{ 0x9874, &carrizo_device_info },	/* Carrizo */
+-	{ 0x9875, &carrizo_device_info },	/* Carrizo */
+-	{ 0x9876, &carrizo_device_info },	/* Carrizo */
+-	{ 0x9877, &carrizo_device_info },	/* Carrizo */
+-	{ 0x15DD, &raven_device_info },		/* Raven */
+-	{ 0x15D8, &raven_device_info },		/* Raven */
+-#endif
+-	{ 0x67A0, &hawaii_device_info },	/* Hawaii */
+-	{ 0x67A1, &hawaii_device_info },	/* Hawaii */
+-	{ 0x67A2, &hawaii_device_info },	/* Hawaii */
+-	{ 0x67A8, &hawaii_device_info },	/* Hawaii */
+-	{ 0x67A9, &hawaii_device_info },	/* Hawaii */
+-	{ 0x67AA, &hawaii_device_info },	/* Hawaii */
+-	{ 0x67B0, &hawaii_device_info },	/* Hawaii */
+-	{ 0x67B1, &hawaii_device_info },	/* Hawaii */
+-	{ 0x67B8, &hawaii_device_info },	/* Hawaii */
+-	{ 0x67B9, &hawaii_device_info },	/* Hawaii */
+-	{ 0x67BA, &hawaii_device_info },	/* Hawaii */
+-	{ 0x67BE, &hawaii_device_info },	/* Hawaii */
+-	{ 0x6920, &tonga_device_info },		/* Tonga */
+-	{ 0x6921, &tonga_device_info },		/* Tonga */
+-	{ 0x6928, &tonga_device_info },		/* Tonga */
+-	{ 0x6929, &tonga_device_info },		/* Tonga */
+-	{ 0x692B, &tonga_device_info },		/* Tonga */
+-	{ 0x6938, &tonga_device_info },		/* Tonga */
+-	{ 0x6939, &tonga_device_info },		/* Tonga */
+-	{ 0x7300, &fiji_device_info },		/* Fiji */
+-	{ 0x730F, &fiji_vf_device_info },	/* Fiji vf*/
+-	{ 0x67C0, &polaris10_device_info },	/* Polaris10 */
+-	{ 0x67C1, &polaris10_device_info },	/* Polaris10 */
+-	{ 0x67C2, &polaris10_device_info },	/* Polaris10 */
+-	{ 0x67C4, &polaris10_device_info },	/* Polaris10 */
+-	{ 0x67C7, &polaris10_device_info },	/* Polaris10 */
+-	{ 0x67C8, &polaris10_device_info },	/* Polaris10 */
+-	{ 0x67C9, &polaris10_device_info },	/* Polaris10 */
+-	{ 0x67CA, &polaris10_device_info },	/* Polaris10 */
+-	{ 0x67CC, &polaris10_device_info },	/* Polaris10 */
+-	{ 0x67CF, &polaris10_device_info },	/* Polaris10 */
+-	{ 0x67D0, &polaris10_vf_device_info },	/* Polaris10 vf*/
+-	{ 0x67DF, &polaris10_device_info },	/* Polaris10 */
+-	{ 0x6FDF, &polaris10_device_info },	/* Polaris10 */
+-	{ 0x67E0, &polaris11_device_info },	/* Polaris11 */
+-	{ 0x67E1, &polaris11_device_info },	/* Polaris11 */
+-	{ 0x67E3, &polaris11_device_info },	/* Polaris11 */
+-	{ 0x67E7, &polaris11_device_info },	/* Polaris11 */
+-	{ 0x67E8, &polaris11_device_info },	/* Polaris11 */
+-	{ 0x67E9, &polaris11_device_info },	/* Polaris11 */
+-	{ 0x67EB, &polaris11_device_info },	/* Polaris11 */
+-	{ 0x67EF, &polaris11_device_info },	/* Polaris11 */
+-	{ 0x67FF, &polaris11_device_info },	/* Polaris11 */
+-	{ 0x6980, &polaris12_device_info },	/* Polaris12 */
+-	{ 0x6981, &polaris12_device_info },	/* Polaris12 */
+-	{ 0x6985, &polaris12_device_info },	/* Polaris12 */
+-	{ 0x6986, &polaris12_device_info },	/* Polaris12 */
+-	{ 0x6987, &polaris12_device_info },	/* Polaris12 */
+-	{ 0x6995, &polaris12_device_info },	/* Polaris12 */
+-	{ 0x6997, &polaris12_device_info },	/* Polaris12 */
+-	{ 0x699F, &polaris12_device_info },	/* Polaris12 */
+-	{ 0x694C, &vegam_device_info },		/* VegaM */
+-	{ 0x694E, &vegam_device_info },		/* VegaM */
+-	{ 0x694F, &vegam_device_info },		/* VegaM */
+-	{ 0x6860, &vega10_device_info },	/* Vega10 */
+-	{ 0x6861, &vega10_device_info },	/* Vega10 */
+-	{ 0x6862, &vega10_device_info },	/* Vega10 */
+-	{ 0x6863, &vega10_device_info },	/* Vega10 */
+-	{ 0x6864, &vega10_device_info },	/* Vega10 */
+-	{ 0x6867, &vega10_device_info },	/* Vega10 */
+-	{ 0x6868, &vega10_device_info },	/* Vega10 */
+-	{ 0x6869, &vega10_device_info },	/* Vega10 */
+-	{ 0x686A, &vega10_device_info },	/* Vega10 */
+-	{ 0x686B, &vega10_device_info },	/* Vega10 */
+-	{ 0x686C, &vega10_vf_device_info },	/* Vega10  vf*/
+-	{ 0x686D, &vega10_device_info },	/* Vega10 */
+-	{ 0x686E, &vega10_device_info },	/* Vega10 */
+-	{ 0x686F, &vega10_device_info },	/* Vega10 */
+-	{ 0x687F, &vega10_device_info },	/* Vega10 */
+-	{ 0x69A0, &vega12_device_info },	/* Vega12 */
+-	{ 0x69A1, &vega12_device_info },	/* Vega12 */
+-	{ 0x69A2, &vega12_device_info },	/* Vega12 */
+-	{ 0x69A3, &vega12_device_info },	/* Vega12 */
+-	{ 0x69AF, &vega12_device_info },	/* Vega12 */
+-	{ 0x66a0, &vega20_device_info },	/* Vega20 */
+-	{ 0x66a1, &vega20_device_info },	/* Vega20 */
+-	{ 0x66a2, &vega20_device_info },	/* Vega20 */
+-	{ 0x66a3, &vega20_device_info },	/* Vega20 */
+-	{ 0x66a4, &vega20_device_info },	/* Vega20 */
+-	{ 0x66a7, &vega20_device_info },	/* Vega20 */
+-	{ 0x66af, &vega20_device_info },	/* Vega20 */
+-	{ 0x738C, &arcturus_device_info },	/* Arcturus */
+-	{ 0x7388, &arcturus_device_info },	/* Arcturus */
+-	{ 0x738E, &arcturus_device_info },	/* Arcturus */
+-	{ 0x7390, &arcturus_device_info },	/* Arcturus vf */
+-	{ 0x7310, &navi10_device_info },	/* Navi10 */
+-	{ 0x7312, &navi10_device_info },	/* Navi10 */
+-	{ 0x7318, &navi10_device_info },	/* Navi10 */
+-	{ 0x731a, &navi10_device_info },	/* Navi10 */
+-	{ 0x731f, &navi10_device_info },	/* Navi10 */
++/* For each entry, [0] is regular and [1] is virtualisation device. */
++static const struct kfd_device_info *kfd_supported_devices[][2] = {
++	[CHIP_KAVERI] = {&kaveri_device_info, NULL},
++	[CHIP_HAWAII] = {&hawaii_device_info, NULL},
++	[CHIP_TONGA] = {&tonga_device_info, NULL},
++	[CHIP_FIJI] = {&fiji_device_info, &fiji_vf_device_info},
++	[CHIP_CARRIZO] = {&carrizo_device_info, NULL},
++	[CHIP_POLARIS10] = {&polaris10_device_info, &polaris10_vf_device_info},
++	[CHIP_POLARIS11] = {&polaris11_device_info, NULL},
++	[CHIP_POLARIS12] = {&polaris12_device_info, NULL},
++	[CHIP_VEGAM] = {&vegam_device_info, NULL},
++	[CHIP_VEGA10] = {&vega10_device_info, &vega10_vf_device_info},
++	[CHIP_VEGA12] = {&vega12_device_info, NULL},
++	[CHIP_VEGA20] = {&vega20_device_info, NULL},
++	[CHIP_RAVEN] = {&raven_device_info, NULL},
++	[CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info},
++	[CHIP_NAVI10] = {&navi10_device_info, NULL},
+ };
+ 
+ static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
+@@ -504,33 +394,23 @@ static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
+ 
+ static int kfd_resume(struct kfd_dev *kfd);
+ 
+-static const struct kfd_device_info *lookup_device_info(unsigned short did)
++struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
++	struct pci_dev *pdev, const struct kfd2kgd_calls *f2g,
++	unsigned int asic_type, bool vf)
+ {
+-	size_t i;
++	struct kfd_dev *kfd;
++	const struct kfd_device_info *device_info;
+ 
+-	for (i = 0; i < ARRAY_SIZE(supported_devices); i++) {
+-		if (supported_devices[i].did == did) {
+-			WARN_ON(!supported_devices[i].device_info);
+-			return supported_devices[i].device_info;
+-		}
++	if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2)) {
++		dev_err(kfd_device, "asic_type %d out of range\n", asic_type);
++		return NULL; /* asic_type out of range */
+ 	}
+ 
+-	dev_warn(kfd_device, "DID %04x is missing in supported_devices\n",
+-		 did);
+-
+-	return NULL;
+-}
+-
+-#ifdef CONFIG_HSA_AMD
+-struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
+-	struct pci_dev *pdev, const struct kfd2kgd_calls *f2g)
+-{
+-	struct kfd_dev *kfd;
+-	const struct kfd_device_info *device_info =
+-					lookup_device_info(pdev->device);
++	device_info = kfd_supported_devices[asic_type][vf];
+ 
+ 	if (!device_info) {
+-		dev_err(kfd_device, "kgd2kfd_probe failed\n");
++		dev_err(kfd_device, "%s %s not supported in kfd\n",
++			amdgpu_asic_name[asic_type], vf ? "VF" : "");
+ 		return NULL;
+ 	}
+ 
+@@ -567,7 +447,6 @@ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
+ 
+ 	return kfd;
+ }
+-#endif
+ 
+ static void kfd_cwsr_init(struct kfd_dev *kfd)
+ {
+diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
+index f4eda333c11c..a4a80ce18a7a 100644
+--- a/include/drm/amd_asic_type.h
++++ b/include/drm/amd_asic_type.h
+@@ -58,4 +58,6 @@ enum amd_asic_type {
+ 	CHIP_LAST,
+ };
+ 
++extern const char *amdgpu_asic_name[];
++
+ #endif /*__AMD_ASIC_TYPE_H__ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3704-drm-amd-powerplay-fix-unused-variable-compile-warnin.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3704-drm-amd-powerplay-fix-unused-variable-compile-warnin.patch
new file mode 100644
index 00000000..d13a6486
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3704-drm-amd-powerplay-fix-unused-variable-compile-warnin.patch
@@ -0,0 +1,67 @@
+From 7e62e7c9b679b0dae099c33244c657d3eb09c717 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 5 Sep 2019 17:23:57 +0800
+Subject: [PATCH 3704/4256] drm/amd/powerplay: fix 'unused variable' compile
+ warning
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 --
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c   | 2 --
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c   | 2 --
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c   | 2 --
+ 4 files changed, 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index e7ec8d583ea0..f2be65928237 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -1931,7 +1931,5 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 
+ void arcturus_set_ppt_funcs(struct smu_context *smu)
+ {
+-	struct smu_table_context *smu_table = &smu->smu_table;
+-
+ 	smu->ppt_funcs = &arcturus_ppt_funcs;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index e3add8b59291..16634e657589 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1630,7 +1630,5 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ 
+ void navi10_set_ppt_funcs(struct smu_context *smu)
+ {
+-	struct smu_table_context *smu_table = &smu->smu_table;
+-
+ 	smu->ppt_funcs = &navi10_ppt_funcs;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index b7fa8b158ff2..a5cf846b50d4 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -257,8 +257,6 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 
+ void renoir_set_ppt_funcs(struct smu_context *smu)
+ {
+-	struct smu_table_context *smu_table = &smu->smu_table;
+-
+ 	smu->ppt_funcs = &renoir_ppt_funcs;
+ 	smu->smc_if_version = SMU12_DRIVER_IF_VERSION;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 18d1b432f719..929f61891dfa 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -3180,7 +3180,5 @@ static const struct pptable_funcs vega20_ppt_funcs = {
+ 
+ void vega20_set_ppt_funcs(struct smu_context *smu)
+ {
+-	struct smu_table_context *smu_table = &smu->smu_table;
+-
+ 	smu->ppt_funcs = &vega20_ppt_funcs;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3705-drm-amdkfd-Fix-a-building-error-when-KFD_SUPPORT_IOM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3705-drm-amdkfd-Fix-a-building-error-when-KFD_SUPPORT_IOM.patch
new file mode 100644
index 00000000..0d12d1f3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3705-drm-amdkfd-Fix-a-building-error-when-KFD_SUPPORT_IOM.patch
@@ -0,0 +1,46 @@
+From 1a0da72ef84c4c503ffcce2b0a96b6a03398367b Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Thu, 5 Sep 2019 10:49:56 -0400
+Subject: [PATCH 3705/4256] drm/amdkfd: Fix a building error when
+ KFD_SUPPORT_IOMMU_V2 is turned off
+
+The issue was accidentally introduced recently.
+
+Change-Id: I3b21caa1596d4f7de1866bed1cb5d8fe1b51504c
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index 51a85fd20475..cf8fb7dcaccf 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -371,11 +371,14 @@ static const struct kfd_device_info navi10_device_info = {
+ 
+ /* For each entry, [0] is regular and [1] is virtualisation device. */
+ static const struct kfd_device_info *kfd_supported_devices[][2] = {
++#ifdef KFD_SUPPORT_IOMMU_V2
+ 	[CHIP_KAVERI] = {&kaveri_device_info, NULL},
++	[CHIP_CARRIZO] = {&carrizo_device_info, NULL},
++	[CHIP_RAVEN] = {&raven_device_info, NULL},
++#endif
+ 	[CHIP_HAWAII] = {&hawaii_device_info, NULL},
+ 	[CHIP_TONGA] = {&tonga_device_info, NULL},
+ 	[CHIP_FIJI] = {&fiji_device_info, &fiji_vf_device_info},
+-	[CHIP_CARRIZO] = {&carrizo_device_info, NULL},
+ 	[CHIP_POLARIS10] = {&polaris10_device_info, &polaris10_vf_device_info},
+ 	[CHIP_POLARIS11] = {&polaris11_device_info, NULL},
+ 	[CHIP_POLARIS12] = {&polaris12_device_info, NULL},
+@@ -383,7 +386,6 @@ static const struct kfd_device_info *kfd_supported_devices[][2] = {
+ 	[CHIP_VEGA10] = {&vega10_device_info, &vega10_vf_device_info},
+ 	[CHIP_VEGA12] = {&vega12_device_info, NULL},
+ 	[CHIP_VEGA20] = {&vega20_device_info, NULL},
+-	[CHIP_RAVEN] = {&raven_device_info, NULL},
+ 	[CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info},
+ 	[CHIP_NAVI10] = {&navi10_device_info, NULL},
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3706-drm-amd-display-Fix-DML-tests.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3706-drm-amd-display-Fix-DML-tests.patch
new file mode 100644
index 00000000..063346d6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3706-drm-amd-display-Fix-DML-tests.patch
@@ -0,0 +1,34 @@
+From 068ca2168d21d734a8ceed06cb0fab1ddf76bb3a Mon Sep 17 00:00:00 2001
+From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Date: Wed, 7 Aug 2019 13:02:44 -0400
+Subject: [PATCH 3706/4256] drm/amd/display: Fix DML tests
+
+[Why]
+DML diags tests are failing because the struct contents get
+clobbered by a memcpy.
+
+[How]
+Remove the memcpy call.
+
+Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 477885816854..353e3e7cb929 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2798,7 +2798,6 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
+ 	ASSERT(false);
+ 
+ restore_dml_state:
+-	memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
+ 	context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
+ 
+ 	return voltage_supported;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3707-drm-amd-display-refine-i2c-over-aux.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3707-drm-amd-display-refine-i2c-over-aux.patch
new file mode 100644
index 00000000..d2344ba1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3707-drm-amd-display-refine-i2c-over-aux.patch
@@ -0,0 +1,158 @@
+From 7284f93ec90184100341e9e0ea145ad800284482 Mon Sep 17 00:00:00 2001
+From: Lewis Huang <Lewis.Huang@amd.com>
+Date: Wed, 7 Aug 2019 18:05:49 +0800
+Subject: [PATCH 3707/4256] drm/amd/display: refine i2c over aux
+
+[Why]
+When user mode use i2c over aux through ADL or DDI, the function
+dal_ddc_service_query_ddc_data will be called. There are two issues.
+
+1. When read/write length > 16byte, current always return false because
+the DEFAULT_AUX_MAX_DATA_SIZE != length.
+2. When usermode only need to read data through i2c, driver will write
+mot = true at the same address and cause i2c sink confused. Therefore
+the following read command will get garbage.
+
+[How]
+1. Add function dal_dcc_submit_aux_command to handle length > 16 byte.
+2. Check read size and write size when query ddc data.
+
+Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 87 +++++++++++++------
+ .../gpu/drm/amd/display/dc/inc/dc_link_ddc.h  |  3 +
+ 2 files changed, 63 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+index 7fd2d1358f1b..f70137d67c82 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+@@ -494,7 +494,7 @@ bool dal_ddc_service_query_ddc_data(
+ 	uint8_t *read_buf,
+ 	uint32_t read_size)
+ {
+-	bool ret;
++	bool ret = false;
+ 	uint32_t payload_size =
+ 		dal_ddc_service_is_in_aux_transaction_mode(ddc) ?
+ 			DEFAULT_AUX_MAX_DATA_SIZE : EDID_SEGMENT_SIZE;
+@@ -513,34 +513,32 @@ bool dal_ddc_service_query_ddc_data(
+ 	/*TODO: len of payload data for i2c and aux is uint8!!!!,
+ 	 *  but we want to read 256 over i2c!!!!*/
+ 	if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) {
+-		struct aux_payload write_payload = {
+-			.i2c_over_aux = true,
+-			.write = true,
+-			.mot = true,
+-			.address = address,
+-			.length = write_size,
+-			.data = write_buf,
+-			.reply = NULL,
+-			.defer_delay = get_defer_delay(ddc),
+-		};
+-
+-		struct aux_payload read_payload = {
+-			.i2c_over_aux = true,
+-			.write = false,
+-			.mot = false,
+-			.address = address,
+-			.length = read_size,
+-			.data = read_buf,
+-			.reply = NULL,
+-			.defer_delay = get_defer_delay(ddc),
+-		};
+-
+-		ret = dc_link_aux_transfer_with_retries(ddc, &write_payload);
++		struct aux_payload payload;
++		bool read_available = true;
++
++		payload.i2c_over_aux = true;
++		payload.address = address;
++		payload.reply = NULL;
++		payload.defer_delay = get_defer_delay(ddc);
++
++		if (write_size != 0) {
++			payload.write = true;
++			payload.mot = true;
++			payload.length = write_size;
++			payload.data = write_buf;
++
++			ret = dal_ddc_submit_aux_command(ddc, &payload);
++			read_available = ret;
++		}
+ 
+-		if (!ret)
+-			return false;
++		if (read_size != 0 && read_available) {
++			payload.write = false;
++			payload.mot = false;
++			payload.length = read_size;
++			payload.data = read_buf;
+ 
+-		ret = dc_link_aux_transfer_with_retries(ddc, &read_payload);
++			ret = dal_ddc_submit_aux_command(ddc, &payload);
++		}
+ 	} else {
+ 		struct i2c_payloads *payloads =
+ 			dal_ddc_i2c_payloads_create(ddc->ctx, payloads_num);
+@@ -571,6 +569,41 @@ bool dal_ddc_service_query_ddc_data(
+ 	return ret;
+ }
+ 
++bool dal_ddc_submit_aux_command(struct ddc_service *ddc,
++		struct aux_payload *payload)
++{
++	uint8_t retrieved = 0;
++	bool ret = 0;
++
++	if (!ddc)
++		return false;
++
++	if (!payload)
++		return false;
++
++	do {
++		struct aux_payload current_payload;
++		bool is_end_of_payload = (retrieved + DEFAULT_AUX_MAX_DATA_SIZE) >
++			payload->length ? true : false;
++
++		current_payload.address = payload->address;
++		current_payload.data = &payload->data[retrieved];
++		current_payload.defer_delay = payload->defer_delay;
++		current_payload.i2c_over_aux = payload->i2c_over_aux;
++		current_payload.length = is_end_of_payload ?
++			payload->length - retrieved : DEFAULT_AUX_MAX_DATA_SIZE;
++		current_payload.mot = payload->mot ? payload->mot : !is_end_of_payload;
++		current_payload.reply = payload->reply;
++		current_payload.write = payload->write;
++
++		ret = dc_link_aux_transfer_with_retries(ddc, &current_payload);
++
++		retrieved += current_payload.length;
++	} while (retrieved < payload->length && ret == true);
++
++	return ret;
++}
++
+ /* dc_link_aux_transfer_raw() - Attempt to transfer
+  * the given aux payload.  This function does not perform
+  * retries or handle error states.  The reply is returned
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+index b1fab251c09b..7d35d03a2d43 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+@@ -95,6 +95,9 @@ bool dal_ddc_service_query_ddc_data(
+ 		uint8_t *read_buf,
+ 		uint32_t read_size);
+ 
++bool dal_ddc_submit_aux_command(struct ddc_service *ddc,
++		struct aux_payload *payload);
++
+ int dc_link_aux_transfer_raw(struct ddc_service *ddc,
+ 		struct aux_payload *payload,
+ 		enum aux_channel_operation_result *operation_result);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3708-drm-amd-display-Subsample-mode-suboptimal-for-YCbCr4.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3708-drm-amd-display-Subsample-mode-suboptimal-for-YCbCr4.patch
new file mode 100644
index 00000000..1b5bdacf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3708-drm-amd-display-Subsample-mode-suboptimal-for-YCbCr4.patch
@@ -0,0 +1,55 @@
+From c7e03d3cadf2186e6374cd690d271f4ad8b25ca3 Mon Sep 17 00:00:00 2001
+From: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Date: Fri, 9 Aug 2019 17:16:18 -0400
+Subject: [PATCH 3708/4256] drm/amd/display: Subsample mode suboptimal for
+ YCbCr4:2:2
+
+[Why&How]
+Driver defaults to 1-tap subsample mode for 4:2:2.
+DCE11.2 added 3-tap. The policy is:
+DCE8-DCE11 - change to 2-tap, it's better than 1-tap.
+DCE11.2+ - use 3-tap
+
+Note that 4:2:0 was added in DCE11.2 and already uses 3-tap always.
+Note 2 is that DCE not covered on Linux, only DCN+
+
+Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 5 ++++-
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 2 ++
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+index 1168342c7190..7045c00edab9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+@@ -166,7 +166,10 @@ static void opp1_set_pixel_encoding(
+ 		REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);
+ 		break;
+ 	case PIXEL_ENCODING_YCBCR422:
+-		REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 1);
++		REG_UPDATE_3(FMT_CONTROL,
++				FMT_PIXEL_ENCODING, 1,
++				FMT_SUBSAMPLING_MODE, 2,
++				FMT_CBCR_BIT_REDUCTION_BYPASS, 0);
+ 		break;
+ 	case PIXEL_ENCODING_YCBCR420:
+ 		REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
+index 0f10adea000c..2c0ecfa5a643 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
+@@ -116,6 +116,8 @@
+ 	type FMT_RAND_G_SEED; \
+ 	type FMT_RAND_B_SEED; \
+ 	type FMT_PIXEL_ENCODING; \
++	type FMT_SUBSAMPLING_MODE; \
++	type FMT_CBCR_BIT_REDUCTION_BYPASS; \
+ 	type FMT_CLAMP_DATA_EN; \
+ 	type FMT_CLAMP_COLOR_FORMAT; \
+ 	type FMT_DYNAMIC_EXP_EN; \
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3709-drm-amd-display-Don-t-allocate-payloads-if-link-lost.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3709-drm-amd-display-Don-t-allocate-payloads-if-link-lost.patch
new file mode 100644
index 00000000..9c7303a7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3709-drm-amd-display-Don-t-allocate-payloads-if-link-lost.patch
@@ -0,0 +1,184 @@
+From 1333fa165e7f7cf168acd8a297285b92a0ce3468 Mon Sep 17 00:00:00 2001
+From: Alvin Lee <alvin.lee2@amd.com>
+Date: Fri, 2 Aug 2019 13:42:49 -0400
+Subject: [PATCH 3709/4256] drm/amd/display: Don't allocate payloads if link
+ lost
+
+We should not allocate payloads if the link is lost until the link is retrained.
+Some displays require this.
+
+Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c   | 10 +++++-----
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c   | 17 ++++++++++-------
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c    | 11 +++++++++++
+ drivers/gpu/drm/amd/display/dc/dc_link.h        |  1 +
+ drivers/gpu/drm/amd/display/dc/dc_types.h       |  6 ++++++
+ drivers/gpu/drm/amd/display/dc/dm_helpers.h     |  2 +-
+ 6 files changed, 34 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+index 9328882230d8..1f0c8821af53 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+@@ -283,7 +283,7 @@ void dm_helpers_dp_mst_clear_payload_allocation_table(
+  * Polls for ACT (allocation change trigger) handled and sends
+  * ALLOCATE_PAYLOAD message.
+  */
+-bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
++enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(
+ 		struct dc_context *ctx,
+ 		const struct dc_stream_state *stream)
+ {
+@@ -294,19 +294,19 @@ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
+ 	aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
+ 
+ 	if (!aconnector || !aconnector->mst_port)
+-		return false;
++		return ACT_FAILED;
+ 
+ 	mst_mgr = &aconnector->mst_port->mst_mgr;
+ 
+ 	if (!mst_mgr->mst_state)
+-		return false;
++		return ACT_FAILED;
+ 
+ 	ret = drm_dp_check_act_status(mst_mgr);
+ 
+ 	if (ret)
+-		return false;
++		return ACT_FAILED;
+ 
+-	return true;
++	return ACT_SUCCESS;
+ }
+ 
+ bool dm_helpers_dp_mst_send_payload_allocation(
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 3dfebfd4c130..94734c22bbde 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2508,7 +2508,7 @@ static void update_mst_stream_alloc_table(
+ /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
+  * because stream_encoder is not exposed to dm
+  */
+-static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
++enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
+ {
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	struct dc_link *link = stream->link;
+@@ -2519,6 +2519,7 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
+ 	struct fixed31_32 pbn;
+ 	struct fixed31_32 pbn_per_slot;
+ 	uint8_t i;
++	enum act_return_status ret;
+ 	DC_LOGGER_INIT(link->ctx->logger);
+ 
+ 	/* enable_link_dp_mst already check link->enabled_stream_count
+@@ -2566,14 +2567,16 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
+ 		&link->mst_stream_alloc_table);
+ 
+ 	/* send down message */
+-	dm_helpers_dp_mst_poll_for_allocation_change_trigger(
++	ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
+ 			stream->ctx,
+ 			stream);
+ 
+-	dm_helpers_dp_mst_send_payload_allocation(
+-			stream->ctx,
+-			stream,
+-			true);
++	if (ret != ACT_LINK_LOST) {
++		dm_helpers_dp_mst_send_payload_allocation(
++				stream->ctx,
++				stream,
++				true);
++	}
+ 
+ 	/* slot X.Y for only current stream */
+ 	pbn_per_slot = get_pbn_per_slot(stream);
+@@ -2784,7 +2787,7 @@ void core_link_enable_stream(
+ #endif
+ 
+ 		if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
+-			allocate_mst_payload(pipe_ctx);
++			dc_link_allocate_mst_payload(pipe_ctx);
+ 
+ 		core_dc->hwss.unblank_stream(pipe_ctx,
+ 			&pipe_ctx->stream->link->cur_link_settings);
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index f5742719b5d9..7c78caf7a602 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2364,6 +2364,8 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd
+ 	enum dc_status result;
+ 
+ 	bool status = false;
++	struct pipe_ctx *pipe_ctx;
++	int i;
+ 
+ 	if (out_link_loss)
+ 		*out_link_loss = false;
+@@ -2440,6 +2442,15 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd
+ 			&link->cur_link_settings,
+ 			true, LINK_TRAINING_ATTEMPTS);
+ 
++		for (i = 0; i < MAX_PIPES; i++) {
++			pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
++			if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link &&
++					pipe_ctx->stream->dpms_off == false &&
++					pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
++				dc_link_allocate_mst_payload(pipe_ctx);
++			}
++		}
++
+ 		status = false;
+ 		if (out_link_loss)
+ 			*out_link_loss = true;
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
+index 9ea75db3484e..45e6195c5395 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
+@@ -192,6 +192,7 @@ enum dc_detect_reason {
+ 
+ bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason);
+ bool dc_link_get_hpd_state(struct dc_link *dc_link);
++enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx);
+ 
+ /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
+  * Return:
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
+index d93758e919a1..f4ccdb2e3c32 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
+@@ -168,6 +168,12 @@ enum dc_edid_status {
+ 	EDID_THE_SAME,
+ };
+ 
++enum act_return_status {
++	ACT_SUCCESS,
++	ACT_LINK_LOST,
++	ACT_FAILED
++};
++
+ /* audio capability from EDID*/
+ struct dc_cea_audio_mode {
+ 	uint8_t format_code; /* ucData[0] [6:3]*/
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+index b6b4333737f2..94b75e942607 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+@@ -74,7 +74,7 @@ void dm_helpers_dp_mst_clear_payload_allocation_table(
+ /*
+  * Polls for ACT (allocation change trigger) handled and
+  */
+-bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
++enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(
+ 		struct dc_context *ctx,
+ 		const struct dc_stream_state *stream);
+ /*
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3710-drm-amd-display-Add-back-support-for-DSC-4-2-2-Simpl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3710-drm-amd-display-Add-back-support-for-DSC-4-2-2-Simpl.patch
new file mode 100644
index 00000000..80b801c4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3710-drm-amd-display-Add-back-support-for-DSC-4-2-2-Simpl.patch
@@ -0,0 +1,33 @@
+From 2a9cc92740d61a5d5692c9ee496c154c577431e6 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Thu, 15 Aug 2019 11:13:54 -0400
+Subject: [PATCH 3710/4256] drm/amd/display: Add back support for DSC 4:2:2
+ Simple
+
+[why]
+The requirement has been clarified and only DSC 4:2:2 Native has to
+be disabled.
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+index 1b419407af94..63eb377ed9c0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+@@ -118,7 +118,7 @@ static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock
+ 
+ 	dsc_enc_caps->color_formats.bits.RGB = 1;
+ 	dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;
+-	dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 0;
++	dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;
+ 	dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;
+ 	dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3711-drm-amd-display-config-to-override-DSC-start-slice-h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3711-drm-amd-display-config-to-override-DSC-start-slice-h.patch
new file mode 100644
index 00000000..f9c606f0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3711-drm-amd-display-config-to-override-DSC-start-slice-h.patch
@@ -0,0 +1,83 @@
+From 881ac972ea098c8cf5d2dcfa00bcdb9cf2c90433 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Fri, 16 Aug 2019 14:26:56 -0400
+Subject: [PATCH 3711/4256] drm/amd/display: config to override DSC start slice
+ height
+
+[why]
+It's sometimes useful to have this option when debugging
+
+[how]
+Add a config flag. If the flag is not set, use driver default policy.
+If the flag is set, use the value from the flag as the starting DSC slice
+height.
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Martin Leung <Martin.Leung@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h         |  1 +
+ drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 14 ++++++++------
+ 2 files changed, 9 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 9e006ad6fa47..aed84a2d9ff4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -350,6 +350,7 @@ struct dc_debug_options {
+ 	bool disable_hubp_power_gate;
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	bool disable_dsc_power_gate;
++	int dsc_min_slice_height_override;
+ #endif
+ 	bool disable_pplib_wm_range;
+ 	enum wm_report_mode pplib_wm_report_mode;
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+index 5995bcdfed54..929ebd4cfb8c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+@@ -512,6 +512,7 @@ static bool setup_dsc_config(
+ 		const struct dsc_enc_caps *dsc_enc_caps,
+ 		int target_bandwidth_kbps,
+ 		const struct dc_crtc_timing *timing,
++		int min_slice_height_override,
+ 		struct dc_dsc_config *dsc_cfg)
+ {
+ 	struct dsc_enc_caps dsc_common_caps;
+@@ -680,7 +681,10 @@ static bool setup_dsc_config(
+ 
+ 	// Slice height (i.e. number of slices per column): start with policy and pick the first one that height is divisible by.
+ 	// For 4:2:0 make sure the slice height is divisible by 2 as well.
+-	slice_height = min(dsc_policy.min_sice_height, pic_height);
++	if (min_slice_height_override == 0)
++		slice_height = min(dsc_policy.min_sice_height, pic_height);
++	else
++		slice_height = min(min_slice_height_override, pic_height);
+ 
+ 	while (slice_height < pic_height && (pic_height % slice_height != 0 ||
+ 		(timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 && slice_height % 2 != 0)))
+@@ -820,10 +824,8 @@ bool dc_dsc_compute_bandwidth_range(
+ 			timing->pixel_encoding, &dsc_common_caps);
+ 
+ 	if (is_dsc_possible)
+-		is_dsc_possible = setup_dsc_config(dsc_sink_caps,
+-				&dsc_enc_caps,
+-				0,
+-				timing, &config);
++		is_dsc_possible = setup_dsc_config(dsc_sink_caps, &dsc_enc_caps, 0, timing,
++					dc->debug.dsc_min_slice_height_override, &config);
+ 
+ 	if (is_dsc_possible)
+ 		get_dsc_bandwidth_range(min_bpp, max_bpp, &dsc_common_caps, timing, range);
+@@ -845,7 +847,7 @@ bool dc_dsc_compute_config(
+ 	is_dsc_possible = setup_dsc_config(dsc_sink_caps,
+ 			&dsc_enc_caps,
+ 			target_bandwidth_kbps,
+-			timing, dsc_cfg);
++			timing, dc->debug.dsc_min_slice_height_override, dsc_cfg);
+ 	return is_dsc_possible;
+ }
+ #endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3712-drm-amd-display-3.2.49.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3712-drm-amd-display-3.2.49.patch
new file mode 100644
index 00000000..abd91c3c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3712-drm-amd-display-3.2.49.patch
@@ -0,0 +1,28 @@
+From 5f7d422b7708ac2ad248069d99190b2f1a6f6eee Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Mon, 19 Aug 2019 09:22:24 -0400
+Subject: [PATCH 3712/4256] drm/amd/display: 3.2.49
+
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index aed84a2d9ff4..ab1759f08dbd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -42,7 +42,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.48"
++#define DC_VER "3.2.49"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3713-drm-amd-display-Add-missing-surface-address-register.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3713-drm-amd-display-Add-missing-surface-address-register.patch
new file mode 100644
index 00000000..036e0708
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3713-drm-amd-display-Add-missing-surface-address-register.patch
@@ -0,0 +1,80 @@
+From 72237cfcc4f0e8f977b68a248b3740461659d6b7 Mon Sep 17 00:00:00 2001
+From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Date: Fri, 16 Aug 2019 16:33:28 -0400
+Subject: [PATCH 3713/4256] drm/amd/display: Add missing surface address
+ registers
+
+[Why]
+- Need to add missing surface address register definitions.
+- RGBE+A does not work in a stereo configuration because
+  surface addresses are no programmed correctly.
+
+[How]
+Added the register definitions and surface address programming.
+
+Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h    | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+index cb20d10288c0..f8e82ef24c09 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+@@ -57,8 +57,12 @@
+ 	SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
+ 	SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
+ 	SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
++	SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
++	SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
+ 	SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
+ 	SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
++	SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
++	SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
+ 	SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\
+ 	SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\
+ 	SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\
+@@ -160,8 +164,12 @@
+ 	uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS; \
+ 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; \
+ 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; \
++	uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C; \
++	uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_C; \
+ 	uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C; \
+ 	uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C; \
++	uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C; \
++	uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_C; \
+ 	uint32_t DCSURF_SURFACE_INUSE; \
+ 	uint32_t DCSURF_SURFACE_INUSE_HIGH; \
+ 	uint32_t DCSURF_SURFACE_INUSE_C; \
+@@ -289,8 +297,12 @@
+ 	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
++	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, SECONDARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
++	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C, SECONDARY_SURFACE_ADDRESS_C, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
++	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, SECONDARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
++	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, SECONDARY_META_SURFACE_ADDRESS_C, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
+@@ -479,8 +491,12 @@
+ 	type SECONDARY_META_SURFACE_ADDRESS;\
+ 	type PRIMARY_SURFACE_ADDRESS_HIGH_C;\
+ 	type PRIMARY_SURFACE_ADDRESS_C;\
++	type SECONDARY_SURFACE_ADDRESS_HIGH_C;\
++	type SECONDARY_SURFACE_ADDRESS_C;\
+ 	type PRIMARY_META_SURFACE_ADDRESS_HIGH_C;\
+ 	type PRIMARY_META_SURFACE_ADDRESS_C;\
++	type SECONDARY_META_SURFACE_ADDRESS_HIGH_C;\
++	type SECONDARY_META_SURFACE_ADDRESS_C;\
+ 	type SURFACE_INUSE_ADDRESS;\
+ 	type SURFACE_INUSE_ADDRESS_HIGH;\
+ 	type SURFACE_INUSE_ADDRESS_C;\
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3714-drm-amd-display-update-navi-to-use-new-surface-progr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3714-drm-amd-display-update-navi-to-use-new-surface-progr.patch
new file mode 100644
index 00000000..d1519fb1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3714-drm-amd-display-update-navi-to-use-new-surface-progr.patch
@@ -0,0 +1,975 @@
+From 5dc3dc29e75bab941513cdd6e80c5f0213aa9ed7 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Mon, 8 Jul 2019 16:46:41 -0400
+Subject: [PATCH 3714/4256] drm/amd/display: update navi to use new surface
+ programming behaviour
+
+New behaviour will track global updates and update any hw that isn't
+related to current stream being updated.
+
+This should fix any issues caused by pipe split pipes being taken
+by other streams.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   5 +-
+ drivers/gpu/drm/amd/display/dc/core/dc.c      | 105 ++--
+ drivers/gpu/drm/amd/display/dc/dc_stream.h    |  18 +
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 576 +++++++++++++-----
+ .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   3 +
+ 5 files changed, 510 insertions(+), 197 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 7d2498455d76..ad585734095b 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -5830,6 +5830,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
+ 	/* Update the planes if changed or disable if we don't have any. */
+ 	if ((planes_count || acrtc_state->active_planes == 0) &&
+ 		acrtc_state->stream) {
++		bundle->stream_update.stream = acrtc_state->stream;
+ 		if (new_pcrtc_state->mode_changed) {
+ 			bundle->stream_update.src = acrtc_state->stream->src;
+ 			bundle->stream_update.dst = acrtc_state->stream->dst;
+@@ -6239,9 +6240,10 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
+ 				(dm_new_crtc_state->abm_level == dm_old_crtc_state->abm_level))
+ 			continue;
+ 
++		stream_update.stream = dm_new_crtc_state->stream;
+ 		if (is_scaling_state_different(dm_new_con_state, dm_old_con_state)) {
+ 			update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
+-					dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
++					dm_new_con_state, dm_new_crtc_state->stream);
+ 
+ 			stream_update.src = dm_new_crtc_state->stream->src;
+ 			stream_update.dst = dm_new_crtc_state->stream->dst;
+@@ -7094,6 +7096,7 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
+ 		status = dc_stream_get_status_from_state(old_dm_state->context,
+ 							 new_dm_crtc_state->stream);
+ 
++		stream_update.stream = new_dm_crtc_state->stream;
+ 		/*
+ 		 * TODO: DC modifies the surface during this call so we need
+ 		 * to lock here - find a way to do this without locking.
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index d5e4d6337113..17990586e704 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -765,8 +765,13 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 			disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
+ #endif
+-			dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
++			if (dc->hwss.apply_ctx_for_surface)
++				dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
+ 		}
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++		if (dc->hwss.program_front_end_for_ctx)
++			dc->hwss.program_front_end_for_ctx(dc, dangling_context);
++#endif
+ 	}
+ 
+ 	current_ctx = dc->current_state;
+@@ -1082,15 +1087,20 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ 	/* re-program planes for existing stream, in case we need to
+ 	 * free up plane resource for later use
+ 	 */
+-	for (i = 0; i < context->stream_count; i++) {
+-		if (context->streams[i]->mode_changed)
+-			continue;
++	if (dc->hwss.apply_ctx_for_surface)
++		for (i = 0; i < context->stream_count; i++) {
++			if (context->streams[i]->mode_changed)
++				continue;
+ 
+-		dc->hwss.apply_ctx_for_surface(
+-			dc, context->streams[i],
+-			context->stream_status[i].plane_count,
+-			context); /* use new pipe config in new context */
+-	}
++			dc->hwss.apply_ctx_for_surface(
++				dc, context->streams[i],
++				context->stream_status[i].plane_count,
++				context); /* use new pipe config in new context */
++		}
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++	if (dc->hwss.program_front_end_for_ctx)
++		dc->hwss.program_front_end_for_ctx(dc, context);
++#endif
+ 
+ 	/* Program hardware */
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+@@ -1109,16 +1119,21 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ 	}
+ 
+ 	/* Program all planes within new context*/
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++	if (dc->hwss.program_front_end_for_ctx)
++		dc->hwss.program_front_end_for_ctx(dc, context);
++#endif
+ 	for (i = 0; i < context->stream_count; i++) {
+ 		const struct dc_link *link = context->streams[i]->link;
+ 
+ 		if (!context->streams[i]->mode_changed)
+ 			continue;
+ 
+-		dc->hwss.apply_ctx_for_surface(
+-				dc, context->streams[i],
+-				context->stream_status[i].plane_count,
+-				context);
++		if (dc->hwss.apply_ctx_for_surface)
++			dc->hwss.apply_ctx_for_surface(
++					dc, context->streams[i],
++					context->stream_status[i].plane_count,
++					context);
+ 
+ 		/*
+ 		 * enable stereo
+@@ -1501,20 +1516,15 @@ static enum surface_update_type det_surface_update(const struct dc *dc,
+ 	enum surface_update_type overall_type = UPDATE_TYPE_FAST;
+ 	union surface_update_flags *update_flags = &u->surface->update_flags;
+ 
+-	update_flags->raw = 0; // Reset all flags
+-
+ 	if (u->flip_addr)
+ 		update_flags->bits.addr_update = 1;
+ 
+-	if (!is_surface_in_context(context, u->surface)) {
+-		update_flags->bits.new_plane = 1;
++	if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
++		update_flags->raw = 0xFFFFFFFF;
+ 		return UPDATE_TYPE_FULL;
+ 	}
+ 
+-	if (u->surface->force_full_update) {
+-		update_flags->bits.full_update = 1;
+-		return UPDATE_TYPE_FULL;
+-	}
++	update_flags->raw = 0; // Reset all flags
+ 
+ 	type = get_plane_info_update_type(u);
+ 	elevate_update_type(&overall_type, type);
+@@ -1572,40 +1582,43 @@ static enum surface_update_type check_update_surfaces_for_stream(
+ 	enum surface_update_type overall_type = UPDATE_TYPE_FAST;
+ 
+ 	if (stream_status == NULL || stream_status->plane_count != surface_count)
+-		return UPDATE_TYPE_FULL;
++		overall_type = UPDATE_TYPE_FULL;
+ 
+ 	/* some stream updates require passive update */
+ 	if (stream_update) {
+-		if ((stream_update->src.height != 0) &&
+-				(stream_update->src.width != 0))
+-			return UPDATE_TYPE_FULL;
++		union stream_update_flags *su_flags = &stream_update->stream->update_flags;
+ 
+-		if ((stream_update->dst.height != 0) &&
+-				(stream_update->dst.width != 0))
+-			return UPDATE_TYPE_FULL;
++		if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
++				(stream_update->dst.height != 0 && stream_update->dst.width != 0))
++			su_flags->bits.scaling = 1;
+ 
+ 		if (stream_update->out_transfer_func)
+-			return UPDATE_TYPE_FULL;
++			su_flags->bits.out_tf = 1;
+ 
+ 		if (stream_update->abm_level)
+-			return UPDATE_TYPE_FULL;
++			su_flags->bits.abm_level = 1;
+ 
+ 		if (stream_update->dpms_off)
+-			return UPDATE_TYPE_FULL;
++			su_flags->bits.dpms_off = 1;
++
++		if (stream_update->gamut_remap)
++			su_flags->bits.gamut_remap = 1;
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 		if (stream_update->wb_update)
+-			return UPDATE_TYPE_FULL;
++			su_flags->bits.wb_update = 1;
+ #endif
++		if (su_flags->raw != 0)
++			overall_type = UPDATE_TYPE_FULL;
++
++		if (stream_update->output_csc_transform || stream_update->output_color_space)
++			su_flags->bits.out_csc = 1;
+ 	}
+ 
+ 	for (i = 0 ; i < surface_count; i++) {
+ 		enum surface_update_type type =
+ 				det_surface_update(dc, &updates[i]);
+ 
+-		if (type == UPDATE_TYPE_FULL)
+-			return type;
+-
+ 		elevate_update_type(&overall_type, type);
+ 	}
+ 
+@@ -1627,13 +1640,18 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
+ 	int i;
+ 	enum surface_update_type type;
+ 
++	if (stream_update)
++		stream_update->stream->update_flags.raw = 0;
+ 	for (i = 0; i < surface_count; i++)
+ 		updates[i].surface->update_flags.raw = 0;
+ 
+ 	type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
+-	if (type == UPDATE_TYPE_FULL)
++	if (type == UPDATE_TYPE_FULL) {
++		if (stream_update)
++			stream_update->stream->update_flags.raw = 0xFFFFFFFF;
+ 		for (i = 0; i < surface_count; i++)
+ 			updates[i].surface->update_flags.raw = 0xFFFFFFFF;
++	}
+ 
+ 	if (type == UPDATE_TYPE_FAST && memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0)
+ 		dc->optimized_required = true;
+@@ -2009,7 +2027,13 @@ static void commit_planes_for_stream(struct dc *dc,
+ 		 * In case of turning off screen, no need to program front end a second time.
+ 		 * just return after program blank.
+ 		 */
+-		dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
++		if (dc->hwss.apply_ctx_for_surface)
++			dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++		if (dc->hwss.program_front_end_for_ctx)
++			dc->hwss.program_front_end_for_ctx(dc, context);
++#endif
++
+ 		return;
+ 	}
+ 
+@@ -2069,10 +2093,15 @@ static void commit_planes_for_stream(struct dc *dc,
+ 			stream_status =
+ 				stream_get_status(context, pipe_ctx->stream);
+ 
+-			dc->hwss.apply_ctx_for_surface(
++			if (dc->hwss.apply_ctx_for_surface)
++				dc->hwss.apply_ctx_for_surface(
+ 					dc, pipe_ctx->stream, stream_status->plane_count, context);
+ 		}
+ 	}
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++	if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST)
++		dc->hwss.program_front_end_for_ctx(dc, context);
++#endif
+ 
+ 	// Update Type FAST, Surface updates
+ 	if (update_type == UPDATE_TYPE_FAST) {
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+index 0fa1c26bc20d..e2d9e11be4b0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+@@ -113,6 +113,21 @@ struct periodic_interrupt_config {
+ 	int lines_offset;
+ };
+ 
++union stream_update_flags {
++	struct {
++		uint32_t scaling:1;
++		uint32_t out_tf:1;
++		uint32_t out_csc:1;
++		uint32_t abm_level:1;
++		uint32_t dpms_off:1;
++		uint32_t gamut_remap:1;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++		uint32_t wb_update:1;
++#endif
++	} bits;
++
++	uint32_t raw;
++};
+ 
+ struct dc_stream_state {
+ 	// sink is deprecated, new code should not reference
+@@ -214,9 +229,12 @@ struct dc_stream_state {
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	bool is_dsc_enabled;
+ #endif
++	union stream_update_flags update_flags;
+ };
+ 
+ struct dc_stream_update {
++	struct dc_stream_state *stream;
++
+ 	struct rect src;
+ 	struct rect dst;
+ 	struct dc_transfer_func *out_transfer_func;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 1212da12c414..b5b5d9145f6a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -508,7 +508,7 @@ static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ }
+ 
+ 
+-void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
++static void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	DC_LOGGER_INIT(dc->ctx->logger);
+ 
+@@ -923,7 +923,7 @@ static void dcn20_power_on_plane(
+ 	}
+ }
+ 
+-void dcn20_enable_plane(
++static void dcn20_enable_plane(
+ 	struct dc *dc,
+ 	struct pipe_ctx *pipe_ctx,
+ 	struct dc_state *context)
+@@ -999,72 +999,6 @@ void dcn20_enable_plane(
+ }
+ 
+ 
+-static void dcn20_program_pipe(
+-		struct dc *dc,
+-		struct pipe_ctx *pipe_ctx,
+-		struct dc_state *context)
+-{
+-	pipe_ctx->plane_state->update_flags.bits.full_update =
+-			context->commit_hints.full_update_needed ? 1 : pipe_ctx->plane_state->update_flags.bits.full_update;
+-
+-	if (pipe_ctx->plane_state->update_flags.bits.full_update)
+-		dcn20_enable_plane(dc, pipe_ctx, context);
+-
+-	update_dchubp_dpp(dc, pipe_ctx, context);
+-
+-	set_hdr_multiplier(pipe_ctx);
+-
+-	if (pipe_ctx->plane_state->update_flags.bits.full_update ||
+-			pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
+-			pipe_ctx->plane_state->update_flags.bits.gamma_change)
+-		dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
+-
+-	/* dcn10_translate_regamma_to_hw_format takes 750us to finish
+-	 * only do gamma programming for full update.
+-	 * TODO: This can be further optimized/cleaned up
+-	 * Always call this for now since it does memcmp inside before
+-	 * doing heavy calculation and programming
+-	 */
+-	if (pipe_ctx->plane_state->update_flags.bits.full_update)
+-		dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
+-}
+-
+-static void dcn20_program_all_pipe_in_tree(
+-		struct dc *dc,
+-		struct pipe_ctx *pipe_ctx,
+-		struct dc_state *context)
+-{
+-	if (pipe_ctx->top_pipe == NULL && !pipe_ctx->prev_odm_pipe) {
+-		bool blank = !is_pipe_tree_visible(pipe_ctx);
+-
+-		pipe_ctx->stream_res.tg->funcs->program_global_sync(
+-				pipe_ctx->stream_res.tg,
+-				pipe_ctx->pipe_dlg_param.vready_offset,
+-				pipe_ctx->pipe_dlg_param.vstartup_start,
+-				pipe_ctx->pipe_dlg_param.vupdate_offset,
+-				pipe_ctx->pipe_dlg_param.vupdate_width);
+-
+-		pipe_ctx->stream_res.tg->funcs->set_vtg_params(
+-				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+-
+-		dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
+-
+-		if (dc->hwss.update_odm)
+-			dc->hwss.update_odm(dc, context, pipe_ctx);
+-	}
+-
+-	if (pipe_ctx->plane_state != NULL)
+-		dcn20_program_pipe(dc, pipe_ctx, context);
+-
+-	if (pipe_ctx->bottom_pipe != NULL) {
+-		ASSERT(pipe_ctx->bottom_pipe != pipe_ctx);
+-		dcn20_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
+-	} else if (pipe_ctx->next_odm_pipe != NULL) {
+-		ASSERT(pipe_ctx->next_odm_pipe != pipe_ctx);
+-		dcn20_program_all_pipe_in_tree(dc, pipe_ctx->next_odm_pipe, context);
+-	}
+-}
+-
+ void dcn20_pipe_control_lock_global(
+ 		struct dc *dc,
+ 		struct pipe_ctx *pipe,
+@@ -1087,7 +1021,7 @@ void dcn20_pipe_control_lock_global(
+ 	}
+ }
+ 
+-void dcn20_pipe_control_lock(
++static void dcn20_pipe_control_lock(
+ 	struct dc *dc,
+ 	struct pipe_ctx *pipe,
+ 	bool lock)
+@@ -1124,114 +1058,436 @@ void dcn20_pipe_control_lock(
+ 	}
+ }
+ 
+-static void dcn20_apply_ctx_for_surface(
+-		struct dc *dc,
+-		const struct dc_stream_state *stream,
+-		int num_planes,
+-		struct dc_state *context)
++static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)
+ {
+-	const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
+-	int i;
+-	struct timing_generator *tg;
+-	bool removed_pipe[6] = { false };
+-	bool interdependent_update = false;
+-	struct pipe_ctx *top_pipe_to_program =
+-			find_top_pipe_for_stream(dc, context, stream);
+-	struct pipe_ctx *prev_top_pipe_to_program =
+-			find_top_pipe_for_stream(dc, dc->current_state, stream);
+-	DC_LOGGER_INIT(dc->ctx->logger);
++	new_pipe->update_flags.raw = 0;
+ 
+-	if (!top_pipe_to_program)
++	/* Exit on unchanged, unused pipe */
++	if (!old_pipe->plane_state && !new_pipe->plane_state)
+ 		return;
++	/* Detect pipe enable/disable */
++	if (!old_pipe->plane_state && new_pipe->plane_state) {
++		new_pipe->update_flags.bits.enable = 1;
++		new_pipe->update_flags.bits.mpcc = 1;
++		new_pipe->update_flags.bits.dppclk = 1;
++		new_pipe->update_flags.bits.hubp_interdependent = 1;
++		new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
++		new_pipe->update_flags.bits.gamut_remap = 1;
++		new_pipe->update_flags.bits.scaler = 1;
++		new_pipe->update_flags.bits.viewport = 1;
++		if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
++			new_pipe->update_flags.bits.odm = 1;
++			new_pipe->update_flags.bits.global_sync = 1;
++		}
++		return;
++	}
++	if (old_pipe->plane_state && !new_pipe->plane_state) {
++		new_pipe->update_flags.bits.disable = 1;
++		return;
++	}
+ 
+-	/* Carry over GSL groups in case the context is changing. */
+-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+-		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+-		struct pipe_ctx *old_pipe_ctx =
+-			&dc->current_state->res_ctx.pipe_ctx[i];
++	/* Detect top pipe only changes */
++	if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
++		/* Detect odm changes */
++		if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe
++			&& old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx)
++				|| (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe)
++				|| (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe)
++				|| old_pipe->stream_res.opp != new_pipe->stream_res.opp)
++			new_pipe->update_flags.bits.odm = 1;
++
++		/* Detect global sync changes */
++		if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
++				|| old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start
++				|| old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset
++				|| old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width)
++			new_pipe->update_flags.bits.global_sync = 1;
++	}
+ 
+-		if (pipe_ctx->stream == stream &&
+-		    pipe_ctx->stream == old_pipe_ctx->stream)
+-			pipe_ctx->stream_res.gsl_group =
+-				old_pipe_ctx->stream_res.gsl_group;
++	/*
++	 * Detect opp / tg change, only set on change, not on enable
++	 * Assume mpcc inst = pipe index, if not this code needs to be updated
++	 * since mpcc is what is affected by these. In fact all of our sequence
++	 * makes this assumption at the moment with how hubp reset is matched to
++	 * same index mpcc reset.
++	 */
++	if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)
++		new_pipe->update_flags.bits.opp_changed = 1;
++	if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
++		new_pipe->update_flags.bits.tg_changed = 1;
++
++	/* Detect mpcc blending changes, only dpp inst and bot matter here */
++	if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp
++			|| old_pipe->stream_res.opp != new_pipe->stream_res.opp
++			|| (!old_pipe->bottom_pipe && new_pipe->bottom_pipe)
++			|| (old_pipe->bottom_pipe && !new_pipe->bottom_pipe)
++			|| (old_pipe->bottom_pipe && new_pipe->bottom_pipe
++				&& old_pipe->bottom_pipe->plane_res.mpcc_inst
++					!= new_pipe->bottom_pipe->plane_res.mpcc_inst))
++		new_pipe->update_flags.bits.mpcc = 1;
++
++	/* Detect dppclk change */
++	if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
++		new_pipe->update_flags.bits.dppclk = 1;
++
++	/* Check for scl update */
++	if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
++			new_pipe->update_flags.bits.scaler = 1;
++	/* Check for vp update */
++	if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
++			|| memcmp(&old_pipe->plane_res.scl_data.viewport_c,
++				&new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
++		new_pipe->update_flags.bits.viewport = 1;
++
++	/* Detect dlg/ttu/rq updates */
++	{
++		struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs;
++		struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs;
++		struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs;
++		struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs;
++
++		/* Detect pipe interdependent updates */
++		if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch ||
++				old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch ||
++				old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c ||
++				old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank ||
++				old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank ||
++				old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip ||
++				old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip ||
++				old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l ||
++				old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c ||
++				old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l ||
++				old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l ||
++				old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c ||
++				old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l ||
++				old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c ||
++				old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 ||
++				old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 ||
++				old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank ||
++				old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) {
++			old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch;
++			old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch;
++			old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c;
++			old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank;
++			old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank;
++			old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip;
++			old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip;
++			old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l;
++			old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c;
++			old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l;
++			old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l;
++			old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c;
++			old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l;
++			old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c;
++			old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0;
++			old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1;
++			old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank;
++			old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip;
++			new_pipe->update_flags.bits.hubp_interdependent = 1;
++		}
++		/* Detect any other updates to ttu/rq/dlg */
++		if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) ||
++				memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) ||
++				memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs)))
++			new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
+ 	}
++}
+ 
+-	tg = top_pipe_to_program->stream_res.tg;
++static void dcn20_update_dchubp_dpp(
++	struct dc *dc,
++	struct pipe_ctx *pipe_ctx,
++	struct dc_state *context)
++{
++	struct hubp *hubp = pipe_ctx->plane_res.hubp;
++	struct dpp *dpp = pipe_ctx->plane_res.dpp;
++	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+ 
+-	interdependent_update = top_pipe_to_program->plane_state &&
+-		top_pipe_to_program->plane_state->update_flags.bits.full_update;
++	if (pipe_ctx->update_flags.bits.dppclk) {
++		dpp->funcs->dpp_dppclk_control(dpp, false, true);
+ 
+-	if (interdependent_update)
+-		lock_all_pipes(dc, context, true);
+-	else
+-		dcn20_pipe_control_lock(dc, top_pipe_to_program, true);
++		dc->res_pool->dccg->funcs->update_dpp_dto(
++				dc->res_pool->dccg,
++				dpp->inst,
++				pipe_ctx->plane_res.bw.dppclk_khz,
++				false);
++	}
+ 
+-	if (num_planes == 0) {
+-		/* OTG blank before remove all front end */
+-		dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
++	/* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
++	 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
++	 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
++	 */
++	if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {
++		hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
++
++		hubp->funcs->hubp_setup(
++			hubp,
++			&pipe_ctx->dlg_regs,
++			&pipe_ctx->ttu_regs,
++			&pipe_ctx->rq_regs,
++			&pipe_ctx->pipe_dlg_param);
++	}
++	if (pipe_ctx->update_flags.bits.hubp_interdependent)
++		hubp->funcs->hubp_setup_interdependent(
++			hubp,
++			&pipe_ctx->dlg_regs,
++			&pipe_ctx->ttu_regs);
++
++	if (pipe_ctx->update_flags.bits.enable ||
++			plane_state->update_flags.bits.bpp_change ||
++			plane_state->update_flags.bits.input_csc_change ||
++			plane_state->update_flags.bits.color_space_change ||
++			plane_state->update_flags.bits.coeff_reduction_change) {
++		struct dc_bias_and_scale bns_params = {0};
++
++		// program the input csc
++		dpp->funcs->dpp_setup(dpp,
++				plane_state->format,
++				EXPANSION_MODE_ZERO,
++				plane_state->input_csc_color_matrix,
++				plane_state->color_space,
++				NULL);
++
++		if (dpp->funcs->dpp_program_bias_and_scale) {
++			//TODO :for CNVC set scale and bias registers if necessary
++			dcn10_build_prescale_params(&bns_params, plane_state);
++			dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
++		}
+ 	}
+ 
+-	/* Disconnect unused mpcc */
+-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+-		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+-		struct pipe_ctx *old_pipe_ctx =
+-				&dc->current_state->res_ctx.pipe_ctx[i];
+-		/*
+-		 * Powergate reused pipes that are not powergated
+-		 * fairly hacky right now, using opp_id as indicator
+-		 * TODO: After move dc_post to dc_update, this will
+-		 * be removed.
+-		 */
+-		if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
+-			if (old_pipe_ctx->stream_res.tg == tg &&
+-			    old_pipe_ctx->plane_res.hubp &&
+-			    old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID)
+-				dc->hwss.disable_plane(dc, old_pipe_ctx);
++	if (pipe_ctx->update_flags.bits.mpcc
++			|| plane_state->update_flags.bits.global_alpha_change
++			|| plane_state->update_flags.bits.per_pixel_alpha_change) {
++		/* Need mpcc to be idle if changing opp */
++		if (pipe_ctx->update_flags.bits.opp_changed) {
++			struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
++			int mpcc_inst;
++
++			for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
++				if (!old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst])
++					continue;
++				dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
++				old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
++			}
+ 		}
++		dc->hwss.update_mpcc(dc, pipe_ctx);
++	}
+ 
+-		if ((!pipe_ctx->plane_state ||
+-		     pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) &&
+-		     old_pipe_ctx->plane_state &&
+-		     old_pipe_ctx->stream_res.tg == tg) {
++	if (pipe_ctx->update_flags.bits.scaler ||
++			plane_state->update_flags.bits.scaling_change ||
++			plane_state->update_flags.bits.position_change ||
++			plane_state->update_flags.bits.per_pixel_alpha_change ||
++			pipe_ctx->stream->update_flags.bits.scaling) {
++		pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
++		ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP);
++		/* scaler configuration */
++		pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
++				pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
++	}
+ 
+-			dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx);
+-			removed_pipe[i] = true;
++	if (pipe_ctx->update_flags.bits.viewport ||
++			(context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
++			(context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling))
++		hubp->funcs->mem_program_viewport(
++			hubp,
++			&pipe_ctx->plane_res.scl_data.viewport,
++			&pipe_ctx->plane_res.scl_data.viewport_c);
++
++	/* Any updates are handled in dc interface, just need to apply existing for plane enable */
++	if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed)
++			&& pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
++		dc->hwss.set_cursor_position(pipe_ctx);
++		dc->hwss.set_cursor_attribute(pipe_ctx);
++
++		if (dc->hwss.set_cursor_sdr_white_level)
++			dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
++	}
+ 
+-			DC_LOG_DC("Reset mpcc for pipe %d\n",
+-					old_pipe_ctx->pipe_idx);
+-		}
++	/* Any updates are handled in dc interface, just need
++	 * to apply existing for plane enable / opp change */
++	if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
++			|| pipe_ctx->stream->update_flags.bits.gamut_remap
++			|| pipe_ctx->stream->update_flags.bits.out_csc) {
++			/* dpp/cm gamut remap*/
++			dc->hwss.program_gamut_remap(pipe_ctx);
++
++		/*call the dcn2 method which uses mpc csc*/
++		dc->hwss.program_output_csc(dc,
++				pipe_ctx,
++				pipe_ctx->stream->output_color_space,
++				pipe_ctx->stream->csc_color_matrix.matrix,
++				hubp->opp_id);
+ 	}
+ 
+-	if (num_planes > 0)
+-		dcn20_program_all_pipe_in_tree(dc, top_pipe_to_program, context);
++	if (pipe_ctx->update_flags.bits.enable ||
++			pipe_ctx->update_flags.bits.opp_changed ||
++			plane_state->update_flags.bits.pixel_format_change ||
++			plane_state->update_flags.bits.horizontal_mirror_change ||
++			plane_state->update_flags.bits.rotation_change ||
++			plane_state->update_flags.bits.swizzle_change ||
++			plane_state->update_flags.bits.dcc_change ||
++			plane_state->update_flags.bits.bpp_change ||
++			plane_state->update_flags.bits.scaling_change ||
++			plane_state->update_flags.bits.plane_size_change) {
++		struct plane_size size = plane_state->plane_size;
++
++		size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
++		hubp->funcs->hubp_program_surface_config(
++			hubp,
++			plane_state->format,
++			&plane_state->tiling_info,
++			&size,
++			plane_state->rotation,
++			&plane_state->dcc,
++			plane_state->horizontal_mirror,
++			0);
++		hubp->power_gated = false;
++	}
++
++	if (pipe_ctx->update_flags.bits.enable || plane_state->update_flags.bits.addr_update)
++		dc->hwss.update_plane_addr(dc, pipe_ctx);
++
++	if (pipe_ctx->update_flags.bits.enable)
++		hubp->funcs->set_blank(hubp, false);
++}
++
++
++static void dcn20_program_pipe(
++		struct dc *dc,
++		struct pipe_ctx *pipe_ctx,
++		struct dc_state *context)
++{
++	/* Only need to unblank on top pipe */
++	if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
++			&& !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
++		dc->hwss.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
++
++	if (pipe_ctx->update_flags.bits.global_sync)
++		pipe_ctx->stream_res.tg->funcs->program_global_sync(
++				pipe_ctx->stream_res.tg,
++				pipe_ctx->pipe_dlg_param.vready_offset,
++				pipe_ctx->pipe_dlg_param.vstartup_start,
++				pipe_ctx->pipe_dlg_param.vupdate_offset,
++				pipe_ctx->pipe_dlg_param.vupdate_width);
++
++	if (pipe_ctx->update_flags.bits.odm)
++		dc->hwss.update_odm(dc, context, pipe_ctx);
++
++	if (pipe_ctx->update_flags.bits.enable)
++		dcn20_enable_plane(dc, pipe_ctx, context);
++
++	if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw)
++		dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
++
++	if (pipe_ctx->update_flags.bits.enable
++			|| pipe_ctx->plane_state->update_flags.bits.sdr_white_level)
++		set_hdr_multiplier(pipe_ctx);
++
++	if (pipe_ctx->update_flags.bits.enable ||
++			pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
++			pipe_ctx->plane_state->update_flags.bits.gamma_change)
++		dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
++
++	/* dcn10_translate_regamma_to_hw_format takes 750us to finish
++	 * only do gamma programming for powering on, internal memcmp to avoid
++	 * updating on slave planes
++	 */
++	if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf)
++		dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
++}
++
++static bool does_pipe_need_lock(struct pipe_ctx *pipe)
++{
++	if ((pipe->plane_state && pipe->plane_state->update_flags.raw)
++			|| pipe->update_flags.raw)
++		return true;
++	if (pipe->bottom_pipe)
++		return does_pipe_need_lock(pipe->bottom_pipe);
+ 
+-	/* Program secondary blending tree and writeback pipes */
+-	if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree))
+-		dc->hwss.program_all_writeback_pipes_in_tree(dc, stream, context);
++	return false;
++}
+ 
+-	if (interdependent_update)
+-		for (i = 0; i < dc->res_pool->pipe_count; i++) {
++static void dcn20_program_front_end_for_ctx(
++		struct dc *dc,
++		struct dc_state *context)
++{
++	const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
++	int i;
++	bool pipe_locked[MAX_PIPES] = {false};
++	DC_LOGGER_INIT(dc->ctx->logger);
++
++	/* Carry over GSL groups in case the context is changing. */
++	for (i = 0; i < dc->res_pool->pipe_count; i++)
++		if (context->res_ctx.pipe_ctx[i].stream == dc->current_state->res_ctx.pipe_ctx[i].stream)
++			context->res_ctx.pipe_ctx[i].stream_res.gsl_group =
++				dc->current_state->res_ctx.pipe_ctx[i].stream_res.gsl_group;
++
++	/* Set pipe update flags and lock pipes */
++	for (i = 0; i < dc->res_pool->pipe_count; i++)
++		dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
++				&context->res_ctx.pipe_ctx[i]);
++	for (i = 0; i < dc->res_pool->pipe_count; i++)
++		if (!context->res_ctx.pipe_ctx[i].top_pipe &&
++				does_pipe_need_lock(&context->res_ctx.pipe_ctx[i])) {
+ 			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+ 
+-			/* Skip inactive pipes and ones already updated */
+-			if (!pipe_ctx->stream || pipe_ctx->stream == stream ||
+-			    !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg))
+-				continue;
++			if (pipe_ctx->update_flags.bits.tg_changed || pipe_ctx->update_flags.bits.enable)
++				dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
++			if (!pipe_ctx->update_flags.bits.enable)
++				dc->hwss.pipe_control_lock(dc, &dc->current_state->res_ctx.pipe_ctx[i], true);
++			pipe_locked[i] = true;
++		}
+ 
+-			pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent(
+-				pipe_ctx->plane_res.hubp,
+-				&pipe_ctx->dlg_regs,
+-				&pipe_ctx->ttu_regs);
++	/* OTG blank before disabling all front ends */
++	for (i = 0; i < dc->res_pool->pipe_count; i++)
++		if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
++				&& !context->res_ctx.pipe_ctx[i].top_pipe
++				&& !context->res_ctx.pipe_ctx[i].prev_odm_pipe
++				&& context->res_ctx.pipe_ctx[i].stream)
++			dc->hwss.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
++
++	/* Disconnect mpcc */
++	for (i = 0; i < dc->res_pool->pipe_count; i++)
++		if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
++				|| context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
++			dc->hwss.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
++			DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
+ 		}
+ 
+-	if (interdependent_update)
+-		lock_all_pipes(dc, context, false);
+-	else
+-		dcn20_pipe_control_lock(dc, top_pipe_to_program, false);
++	/*
++	 * Program all updated pipes, order matters for mpcc setup. Start with
++	 * top pipe and program all pipes that follow in order
++	 */
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
++		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ 
++		if (pipe->plane_state && !pipe->top_pipe) {
++			while (pipe) {
++				dcn20_program_pipe(dc, pipe, context);
++				pipe = pipe->bottom_pipe;
++			}
++			/* Program secondary blending tree and writeback pipes */
++			pipe = &context->res_ctx.pipe_ctx[i];
++			if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0
++					&& (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw)
++					&& dc->hwss.program_all_writeback_pipes_in_tree)
++				dc->hwss.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
++		}
++	}
++
++	/* Unlock all locked pipes */
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++)
+-		if (removed_pipe[i])
+-			dcn20_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
++		if (pipe_locked[i]) {
++			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
++
++			if (pipe_ctx->update_flags.bits.tg_changed || pipe_ctx->update_flags.bits.enable)
++				dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
++			if (!pipe_ctx->update_flags.bits.enable)
++				dc->hwss.pipe_control_lock(dc, &dc->current_state->res_ctx.pipe_ctx[i], false);
++		}
++
++	for (i = 0; i < dc->res_pool->pipe_count; i++)
++		if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
++			dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
+ 
+ 	/*
+ 	 * If we are enabling a pipe, we need to wait for pending clear as this is a critical
+@@ -1239,13 +1495,16 @@ static void dcn20_apply_ctx_for_surface(
+ 	 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
+ 	 * is unsupported on DCN.
+ 	 */
+-	i = 0;
+-	if (num_planes > 0 && top_pipe_to_program &&
+-			(prev_top_pipe_to_program == NULL || prev_top_pipe_to_program->plane_state == NULL)) {
+-		while (i < TIMEOUT_FOR_PIPE_ENABLE_MS &&
+-				top_pipe_to_program->plane_res.hubp->funcs->hubp_is_flip_pending(top_pipe_to_program->plane_res.hubp)) {
+-			i += 1;
+-			msleep(1);
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
++		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
++
++		if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) {
++			struct hubp *hubp = pipe->plane_res.hubp;
++			int j = 0;
++
++			for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS
++					&& hubp->funcs->hubp_is_flip_pending(hubp); j++)
++				msleep(1);
+ 		}
+ 	}
+ }
+@@ -2095,7 +2354,8 @@ void dcn20_hw_sequencer_construct(struct dc *dc)
+ 	dc->hwss.program_triplebuffer = dcn20_program_tripleBuffer;
+ 	dc->hwss.set_input_transfer_func = dcn20_set_input_transfer_func;
+ 	dc->hwss.set_output_transfer_func = dcn20_set_output_transfer_func;
+-	dc->hwss.apply_ctx_for_surface = dcn20_apply_ctx_for_surface;
++	dc->hwss.apply_ctx_for_surface = NULL;
++	dc->hwss.program_front_end_for_ctx = dcn20_program_front_end_for_ctx;
+ 	dc->hwss.pipe_control_lock = dcn20_pipe_control_lock;
+ 	dc->hwss.pipe_control_lock_global = dcn20_pipe_control_lock_global;
+ 	dc->hwss.optimize_bandwidth = dcn20_optimize_bandwidth;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index 3a938cd414ea..cbac3b61da94 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -114,6 +114,9 @@ struct hw_sequencer_funcs {
+ 			int opp_id);
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++	void (*program_front_end_for_ctx)(
++			struct dc *dc,
++			struct dc_state *context);
+ 	void (*program_triplebuffer)(
+ 		const struct dc *dc,
+ 		struct pipe_ctx *pipe_ctx,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3715-drm-amd-display-remove-temporary-transition-code.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3715-drm-amd-display-remove-temporary-transition-code.patch
new file mode 100644
index 00000000..390d12ca
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3715-drm-amd-display-remove-temporary-transition-code.patch
@@ -0,0 +1,65 @@
+From 973ae2e7255320f22c31018a14262bde3bb26ea3 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 3 Jul 2019 16:37:54 -0400
+Subject: [PATCH 3715/4256] drm/amd/display: remove temporary transition code
+
+Remove code used to allow compilation error free
+interface change.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 29 --------------------
+ 1 file changed, 29 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+index 0b8700a8a94a..dafc19a7b699 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+@@ -124,20 +124,6 @@ struct plane_size {
+ 	int chroma_pitch;
+ 	struct rect surface_size;
+ 	struct rect chroma_size;
+-
+-	union {
+-		struct {
+-			struct rect surface_size;
+-			int surface_pitch;
+-		} grph;
+-
+-		struct {
+-			struct rect luma_size;
+-			int luma_pitch;
+-			struct rect chroma_size;
+-			int chroma_pitch;
+-		} video;
+-	};
+ };
+ 
+ struct dc_plane_dcc_param {
+@@ -148,21 +134,6 @@ struct dc_plane_dcc_param {
+ 
+ 	int meta_pitch_c;
+ 	bool independent_64b_blks_c;
+-
+-	union {
+-		struct {
+-			int meta_pitch;
+-			bool independent_64b_blks;
+-		} grph;
+-
+-		struct {
+-			int meta_pitch_l;
+-			bool independent_64b_blks_l;
+-
+-			int meta_pitch_c;
+-			bool independent_64b_blks_c;
+-		} video;
+-	};
+ };
+ 
+ /*Displayable pixel format in fb*/
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3716-drm-amd-display-Reuse-dcn2-registers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3716-drm-amd-display-Reuse-dcn2-registers.patch
new file mode 100644
index 00000000..d79566b4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3716-drm-amd-display-Reuse-dcn2-registers.patch
@@ -0,0 +1,270 @@
+From 91b58d8cc40d1e05c08d40011c70de7281139d90 Mon Sep 17 00:00:00 2001
+From: Vitaly Prosyak <vitaly.prosyak@amd.com>
+Date: Fri, 9 Aug 2019 12:36:08 -0500
+Subject: [PATCH 3716/4256] drm/amd/display: Reuse dcn2 registers
+
+[Why & How]
+Use dcn2 blender, shaper, 3dlut registers
+
+Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Acked-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h  | 84 +++++++++++--------
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 10 +--
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.h    | 14 ++++
+ 3 files changed, 68 insertions(+), 40 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
+index 290b2854bd2c..f8db8ad593f8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
+@@ -30,16 +30,20 @@
+ #define TO_DCN20_DPP(dpp)\
+ 	container_of(dpp, struct dcn20_dpp, base)
+ 
+-#define TF_REG_LIST_DCN20(id) \
+-	TF_REG_LIST_DCN(id), \
++#define TF_REG_LIST_DCN20_COMMON_UPDATED(id) \
+ 	SRI(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM, id), \
++	SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM, id), \
++	SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM, id), \
++	SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM, id), \
++	SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM, id), \
++	SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM, id), \
++	SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM, id)
++
++#define TF_REG_LIST_DCN20_COMMON(id) \
+ 	SRI(CM_BLNDGAM_CONTROL, CM, id), \
+ 	SRI(CM_BLNDGAM_RAMB_START_CNTL_B, CM, id), \
+ 	SRI(CM_BLNDGAM_RAMB_START_CNTL_G, CM, id), \
+ 	SRI(CM_BLNDGAM_RAMB_START_CNTL_R, CM, id), \
+-	SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM, id), \
+-	SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM, id), \
+-	SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM, id), \
+ 	SRI(CM_BLNDGAM_RAMB_END_CNTL1_B, CM, id), \
+ 	SRI(CM_BLNDGAM_RAMB_END_CNTL2_B, CM, id), \
+ 	SRI(CM_BLNDGAM_RAMB_END_CNTL1_G, CM, id), \
+@@ -66,9 +70,6 @@
+ 	SRI(CM_BLNDGAM_RAMA_START_CNTL_B, CM, id), \
+ 	SRI(CM_BLNDGAM_RAMA_START_CNTL_G, CM, id), \
+ 	SRI(CM_BLNDGAM_RAMA_START_CNTL_R, CM, id), \
+-	SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM, id), \
+-	SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM, id), \
+-	SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM, id), \
+ 	SRI(CM_BLNDGAM_RAMA_END_CNTL1_B, CM, id), \
+ 	SRI(CM_BLNDGAM_RAMA_END_CNTL2_B, CM, id), \
+ 	SRI(CM_BLNDGAM_RAMA_END_CNTL1_G, CM, id), \
+@@ -147,7 +148,12 @@
+ 	SRI(CM_SHAPER_RAMA_REGION_28_29, CM, id), \
+ 	SRI(CM_SHAPER_RAMA_REGION_30_31, CM, id), \
+ 	SRI(CM_SHAPER_RAMA_REGION_32_33, CM, id), \
+-	SRI(CM_SHAPER_LUT_INDEX, CM, id), \
++	SRI(CM_SHAPER_LUT_INDEX, CM, id)
++
++#define TF_REG_LIST_DCN20(id) \
++	TF_REG_LIST_DCN(id), \
++	TF_REG_LIST_DCN20_COMMON(id), \
++	TF_REG_LIST_DCN20_COMMON_UPDATED(id), \
+ 	SRI(CURSOR_CONTROL, CURSOR0_, id), \
+ 	SRI(ALPHA_2BIT_LUT, CNVC_CFG, id), \
+ 	SRI(FCNV_FP_BIAS_R, CNVC_CFG, id), \
+@@ -166,27 +172,41 @@
+ 	SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\
+ 	SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
+ 
+-#define TF_REG_LIST_SH_MASK_DCN20(mask_sh)\
+-	TF_REG_LIST_SH_MASK_DCN(mask_sh), \
++
++#define TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh)\
++	TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
++	TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
++	TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
++	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_B, CM_BLNDGAM_RAMB_EXP_REGION_END_B, mask_sh), \
++	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_G, CM_BLNDGAM_RAMB_EXP_REGION_END_G, mask_sh), \
++	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_R, CM_BLNDGAM_RAMB_EXP_REGION_END_R, mask_sh), \
++	TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
++	TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
++	TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
++	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_B, CM_BLNDGAM_RAMA_EXP_REGION_END_B, mask_sh), \
++	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_G, CM_BLNDGAM_RAMA_EXP_REGION_END_G, mask_sh), \
++	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_R, CM_BLNDGAM_RAMA_EXP_REGION_END_R, mask_sh), \
++	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
++	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
++	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_LUT_MODE, mask_sh), \
++	TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_EN_MASK, mask_sh), \
++	TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_SEL, mask_sh), \
++	TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_CONFIG_STATUS, mask_sh), \
++	TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh)
++
++
++#define TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh)\
++	TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_B, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_G, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_R, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_B, CM_BLNDGAM_RAMB_EXP_REGION_END_B, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_B, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_B, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_G, CM_BLNDGAM_RAMB_EXP_REGION_END_G, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_G, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_G, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_R, CM_BLNDGAM_RAMB_EXP_REGION_END_R, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_R, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_R, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
+@@ -261,18 +281,9 @@
+ 	TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_R, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_B, CM_BLNDGAM_RAMA_EXP_REGION_END_B, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_G, CM_BLNDGAM_RAMA_EXP_REGION_END_G, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_R, CM_BLNDGAM_RAMA_EXP_REGION_END_R, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
+@@ -341,9 +352,6 @@
+ 	TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_EN_MASK, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_SEL, mask_sh), \
+-	TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_CONFIG_STATUS, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_LUT_INDEX, CM_BLNDGAM_LUT_INDEX, mask_sh), \
+ 	TF_SF(CM0_CM_BLNDGAM_LUT_DATA, CM_BLNDGAM_LUT_DATA, mask_sh), \
+ 	TF_SF(CM0_CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, mask_sh), \
+@@ -356,7 +364,6 @@
+ 	TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK, mask_sh), \
+ 	TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_RAM_SEL, mask_sh), \
+ 	TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_30BIT_EN, mask_sh), \
+-	TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_CONFIG_STATUS, mask_sh), \
+ 	TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_READ_SEL, mask_sh), \
+ 	TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh), \
+ 	TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_START_B, mask_sh), \
+@@ -521,9 +528,14 @@
+ 	TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
+ 	TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_EN_MASK, mask_sh), \
+ 	TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_SEL, mask_sh), \
+-	TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_CONFIG_STATUS, mask_sh), \
+ 	TF_SF(CM0_CM_SHAPER_LUT_INDEX, CM_SHAPER_LUT_INDEX, mask_sh), \
+-	TF_SF(CM0_CM_SHAPER_LUT_DATA, CM_SHAPER_LUT_DATA, mask_sh), \
++	TF_SF(CM0_CM_SHAPER_LUT_DATA, CM_SHAPER_LUT_DATA, mask_sh)
++
++
++#define TF_REG_LIST_SH_MASK_DCN20(mask_sh)\
++	TF_REG_LIST_SH_MASK_DCN(mask_sh), \
++	TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh), \
++	TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh), \
+ 	TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_CONFIG_STATUS, mask_sh), \
+ 	TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \
+ 	TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
+@@ -560,6 +572,7 @@
+ 	TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\
+ 	TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh)
+ 
++
+ #define TF_REG_FIELD_LIST_DCN2_0(type) \
+ 	TF_REG_FIELD_LIST(type) \
+ 	type CM_BLNDGAM_LUT_DATA; \
+@@ -593,6 +606,7 @@
+ 	type OBUF_MEM_PWR_FORCE;\
+ 	type LUT_MEM_PWR_FORCE
+ 
++
+ struct dcn2_dpp_shift {
+ 	TF_REG_FIELD_LIST_DCN2_0(uint8_t);
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index b5b5d9145f6a..81740e0c4c4e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -508,7 +508,7 @@ static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ }
+ 
+ 
+-static void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	DC_LOGGER_INIT(dc->ctx->logger);
+ 
+@@ -688,7 +688,7 @@ bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
+ 	return true;
+ }
+ 
+-static bool dcn20_set_blend_lut(
++bool dcn20_set_blend_lut(
+ 	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
+ {
+ 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
+@@ -710,7 +710,7 @@ static bool dcn20_set_blend_lut(
+ 	return result;
+ }
+ 
+-static bool dcn20_set_shaper_3dlut(
++bool dcn20_set_shaper_3dlut(
+ 	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
+ {
+ 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
+@@ -923,7 +923,7 @@ static void dcn20_power_on_plane(
+ 	}
+ }
+ 
+-static void dcn20_enable_plane(
++void dcn20_enable_plane(
+ 	struct dc *dc,
+ 	struct pipe_ctx *pipe_ctx,
+ 	struct dc_state *context)
+@@ -1021,7 +1021,7 @@ void dcn20_pipe_control_lock_global(
+ 	}
+ }
+ 
+-static void dcn20_pipe_control_lock(
++void dcn20_pipe_control_lock(
+ 	struct dc *dc,
+ 	struct pipe_ctx *pipe,
+ 	bool lock)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+index 92ab3dd91814..9dbc2effa4ea 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+@@ -96,4 +96,18 @@ void dcn20_init_blank(
+ 	   struct dc *dc,
+ 	   struct timing_generator *tg);
+ void dcn20_display_init(struct dc *dc);
++void dcn20_pipe_control_lock(
++	struct dc *dc,
++	struct pipe_ctx *pipe,
++	bool lock);
++void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn20_enable_plane(
++	struct dc *dc,
++	struct pipe_ctx *pipe_ctx,
++	struct dc_state *context);
++bool dcn20_set_blend_lut(
++	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
++bool dcn20_set_shaper_3dlut(
++	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
++
+ #endif /* __DC_HWSS_DCN20_H__ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3717-drm-amd-display-remove-hw-access-from-dc_destroy.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3717-drm-amd-display-remove-hw-access-from-dc_destroy.patch
new file mode 100644
index 00000000..9291d42c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3717-drm-amd-display-remove-hw-access-from-dc_destroy.patch
@@ -0,0 +1,204 @@
+From a90d4c92c221200b6b9376d5aca2c1e41e96595e Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Thu, 15 Aug 2019 15:22:34 -0400
+Subject: [PATCH 3717/4256] drm/amd/display: remove hw access from dc_destroy
+
+[why]
+dc_destroy should only clean up SW, this is because GPUs may be
+removed before driver unload, leading to HW to be unavailable.
+
+[how]
+remove GPIO close as part of GPIO destroy, this is unnecessary because
+GPIO is not shared, and GPIOs are generally closed after being opened
+
+Add tracking to HW access during destructor to make future issues
+easier to pinpoint, and block access to prevent hangs.
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c    |  3 +++
+ drivers/gpu/drm/amd/display/dc/core/dc.c      | 20 +++++++++++++------
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c |  1 -
+ drivers/gpu/drm/amd/display/dc/dc.h           |  6 ++----
+ drivers/gpu/drm/amd/display/dc/dc_stream.h    |  2 ++
+ drivers/gpu/drm/amd/display/dc/dce/dce_abm.c  |  3 ---
+ drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c |  3 ---
+ .../gpu/drm/amd/display/dc/gpio/gpio_base.c   |  2 --
+ .../drm/amd/display/dc/gpio/gpio_service.c    |  2 --
+ 9 files changed, 21 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+index d00ee9fa04e4..6e03805e1b87 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+@@ -136,6 +136,9 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
+ 
+ 	ASSERT(clk_mgr->pp_smu);
+ 
++	if (dc->work_arounds.skip_clock_update)
++		return;
++
+ 	pp_smu = &clk_mgr->pp_smu->rv_funcs;
+ 
+ 	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 17990586e704..1139a365aa8d 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1895,6 +1895,7 @@ static void commit_planes_do_stream_update(struct dc *dc,
+ 		struct dc_state *context)
+ {
+ 	int j;
++	bool should_program_abm;
+ 
+ 	// Stream updates
+ 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
+@@ -1975,14 +1976,21 @@ static void commit_planes_do_stream_update(struct dc *dc,
+ 			}
+ 
+ 			if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
+-				if (pipe_ctx->stream_res.tg->funcs->is_blanked) {
+-					// if otg funcs defined check if blanked before programming
+-					if (!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
++				should_program_abm = true;
++
++				// if otg funcs defined check if blanked before programming
++				if (pipe_ctx->stream_res.tg->funcs->is_blanked)
++					if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
++						should_program_abm = false;
++
++				if (should_program_abm) {
++					if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
++						pipe_ctx->stream_res.abm->funcs->set_abm_immediate_disable(pipe_ctx->stream_res.abm);
++					} else {
+ 						pipe_ctx->stream_res.abm->funcs->set_abm_level(
+ 							pipe_ctx->stream_res.abm, stream->abm_level);
+-				} else
+-					pipe_ctx->stream_res.abm->funcs->set_abm_level(
+-						pipe_ctx->stream_res.abm, stream->abm_level);
++					}
++				}
+ 			}
+ 		}
+ 	}
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 94734c22bbde..fcc25eea0d8f 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -77,7 +77,6 @@ static void destruct(struct dc_link *link)
+ 	int i;
+ 
+ 	if (link->hpd_gpio != NULL) {
+-		dal_gpio_close(link->hpd_gpio);
+ 		dal_gpio_destroy_irq(&link->hpd_gpio);
+ 		link->hpd_gpio = NULL;
+ 	}
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index ab1759f08dbd..3bb4d41ffdb4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -120,13 +120,13 @@ struct dc_caps {
+ 	struct dc_plane_cap planes[MAX_PLANES];
+ };
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dc_bug_wa {
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	bool no_connect_phy_config;
+ 	bool dedcn20_305_wa;
++#endif
+ 	bool skip_clock_update;
+ };
+-#endif
+ 
+ struct dc_dcc_surface_param {
+ 	struct dc_size surface_size;
+@@ -466,9 +466,7 @@ struct dc {
+ 	struct dc_config config;
+ 	struct dc_debug_options debug;
+ 	struct dc_bounding_box_overrides bb_overrides;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	struct dc_bug_wa work_arounds;
+-#endif
+ 	struct dc_context *ctx;
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	struct dc_phy_addr_space_config vm_pa_config;
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+index e2d9e11be4b0..3c061d4f214f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+@@ -232,6 +232,8 @@ struct dc_stream_state {
+ 	union stream_update_flags update_flags;
+ };
+ 
++#define ABM_LEVEL_IMMEDIATE_DISABLE 0xFFFFFFFF
++
+ struct dc_stream_update {
+ 	struct dc_stream_state *stream;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+index adde7a5760bc..b5c97b313c54 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+@@ -487,9 +487,6 @@ void dce_abm_destroy(struct abm **abm)
+ {
+ 	struct dce_abm *abm_dce = TO_DCE_ABM(*abm);
+ 
+-	if (abm_dce->base.dmcu_is_running == true)
+-		abm_dce->base.funcs->set_abm_immediate_disable(*abm);
+-
+ 	kfree(abm_dce);
+ 	*abm = NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+index f3b01f0b8ce7..f86ad9865a48 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+@@ -904,9 +904,6 @@ void dce_dmcu_destroy(struct dmcu **dmcu)
+ {
+ 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);
+ 
+-	if (dmcu_dce->base.dmcu_state == DMCU_RUNNING)
+-		dmcu_dce->base.funcs->set_psr_enable(*dmcu, false, true);
+-
+ 	kfree(dmcu_dce);
+ 	*dmcu = NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c
+index c6f1a7c3affd..c85f21bf07d9 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c
+@@ -319,8 +319,6 @@ void dal_gpio_destroy(
+ 		return;
+ 	}
+ 
+-	dal_gpio_close(*gpio);
+-
+ 	switch ((*gpio)->id) {
+ 	case GPIO_ID_DDC_DATA:
+ 		kfree((*gpio)->hw_container.ddc);
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
+index 30028223f8bc..2a153fb9a62a 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
+@@ -167,7 +167,6 @@ void dal_gpio_destroy_generic_mux(
+ 		return;
+ 	}
+ 
+-	dal_gpio_close(*mux);
+ 	dal_gpio_destroy(mux);
+ 	kfree(*mux);
+ 
+@@ -458,7 +457,6 @@ void dal_gpio_destroy_irq(
+ 		return;
+ 	}
+ 
+-	dal_gpio_close(*irq);
+ 	dal_gpio_destroy(irq);
+ 	kfree(*irq);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3718-drm-amd-display-OTC-underflow-fix.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3718-drm-amd-display-OTC-underflow-fix.patch
new file mode 100644
index 00000000..4858bfd0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3718-drm-amd-display-OTC-underflow-fix.patch
@@ -0,0 +1,36 @@
+From dedffd08ed8a6514f28a5c0bb427d6b125d19243 Mon Sep 17 00:00:00 2001
+From: Jaehyun Chung <jaehyun.chung@amd.com>
+Date: Mon, 19 Aug 2019 16:45:05 -0400
+Subject: [PATCH 3718/4256] drm/amd/display: OTC underflow fix
+
+[Why] Underflow occurs on some display setups(repro'd on 3x4K HDR) on boot,
+mode set, and hot-plugs with. Underflow occurs because mem clk
+is not set high after disabling pstate switching. This behaviour occurs
+because some calculations assumed displays were synchronized.
+
+[How] Add a condition to check if timing sync is disabled so that
+synchronized vblank can be set to false.
+
+Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
+Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 353e3e7cb929..62e9a9826c97 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1757,7 +1757,7 @@ int dcn20_populate_dml_pipes_from_context(
+ 			pipe_cnt = i;
+ 			continue;
+ 		}
+-		if (!resource_are_streams_timing_synchronizable(
++		if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable(
+ 				res_ctx->pipe_ctx[pipe_cnt].stream,
+ 				res_ctx->pipe_ctx[i].stream)) {
+ 			synchronized_vblank = false;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3719-drm-amd-display-Isolate-DSC-module-from-driver-depen.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3719-drm-amd-display-Isolate-DSC-module-from-driver-depen.patch
new file mode 100644
index 00000000..0764fc80
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3719-drm-amd-display-Isolate-DSC-module-from-driver-depen.patch
@@ -0,0 +1,399 @@
+From d7ed4b19e517d7da8b66c7ace112b587e968946e Mon Sep 17 00:00:00 2001
+From: Bayan Zabihiyan <bayan.zabihiyan@amd.com>
+Date: Mon, 19 Aug 2019 15:18:43 -0400
+Subject: [PATCH 3719/4256] drm/amd/display: Isolate DSC module from driver
+ dependencies
+
+[Why]
+Edid Utility wishes to include DSC module from driver instead
+of doing it's own logic which will need to be updated every time
+someone modifies the driver logic.
+
+[How]
+Modify some functions such that we dont need to pass the entire
+DC structure as parameter.
+-Remove DC inclusion from module.
+-Filter out problematic types and inclusions
+
+Signed-off-by: Bayan Zabihiyan <bayan.zabihiyan@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 +-
+ drivers/gpu/drm/amd/display/dc/dc_dsc.h       | 14 +++-
+ drivers/gpu/drm/amd/display/dc/dc_hw_types.h  | 57 ++++++++------
+ drivers/gpu/drm/amd/display/dc/dc_types.h     |  9 +++
+ drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c   | 75 ++++++++++++++++---
+ drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h   | 12 ++-
+ 6 files changed, 125 insertions(+), 45 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index ad585734095b..65aff741befb 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -3691,8 +3691,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ 							     dc_link_get_link_cap(aconnector->dc_link));
+ 
+ 		if (dsc_caps.is_dsc_supported)
+-			if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc,
++			if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
+ 						  &dsc_caps,
++						  aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
+ 						  link_bandwidth_kbps,
+ 						  &stream->timing,
+ 						  &stream->timing.dsc_cfg))
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+index 6e42209f0e20..0ed2962add5a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+@@ -30,6 +30,7 @@
+ #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0  0x0a0   /* DP 1.4a SCR */
+ #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1  0x0a1
+ #define DP_DSC_BRANCH_MAX_LINE_WIDTH        0x0a2
++#include "dc_types.h"
+ 
+ struct dc_dsc_bw_range {
+ 	uint32_t min_kbps; /* Bandwidth if min_target_bpp_x16 is used */
+@@ -39,13 +40,21 @@ struct dc_dsc_bw_range {
+ 	uint32_t stream_kbps; /* Uncompressed stream bandwidth */
+ };
+ 
++struct display_stream_compressor {
++	const struct dsc_funcs *funcs;
++#ifndef AMD_EDID_UTILITY
++	struct dc_context *ctx;
++	int inst;
++#endif
++};
+ 
+ bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_basic_data,
+ 		const uint8_t *dpcd_dsc_ext_data,
+ 		struct dsc_dec_dpcd_caps *dsc_sink_caps);
+ 
+ bool dc_dsc_compute_bandwidth_range(
+-		const struct dc *dc,
++		const struct display_stream_compressor *dsc,
++		const uint32_t dsc_min_slice_height_override,
+ 		const uint32_t min_kbps,
+ 		const uint32_t max_kbps,
+ 		const struct dsc_dec_dpcd_caps *dsc_sink_caps,
+@@ -53,8 +62,9 @@ bool dc_dsc_compute_bandwidth_range(
+ 		struct dc_dsc_bw_range *range);
+ 
+ bool dc_dsc_compute_config(
+-		const struct dc *dc,
++		const struct display_stream_compressor *dsc,
+ 		const struct dsc_dec_dpcd_caps *dsc_sink_caps,
++		const uint32_t dsc_min_slice_height_override,
+ 		uint32_t target_bandwidth_kbps,
+ 		const struct dc_crtc_timing *timing,
+ 		struct dc_dsc_config *dsc_cfg);
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+index dafc19a7b699..2869b26d966a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+@@ -26,6 +26,8 @@
+ #ifndef DC_HW_TYPES_H
+ #define DC_HW_TYPES_H
+ 
++#ifndef AMD_EDID_UTILITY
++
+ #include "os_types.h"
+ #include "fixed31_32.h"
+ #include "signal_types.h"
+@@ -587,6 +589,8 @@ struct scaling_taps {
+ 	bool integer_scaling;
+ };
+ 
++#endif /* AMD_EDID_UTILITY */
++
+ enum dc_timing_standard {
+ 	DC_TIMING_STANDARD_UNDEFINED,
+ 	DC_TIMING_STANDARD_DMT,
+@@ -708,30 +712,6 @@ enum dc_timing_3d_format {
+ 	TIMING_3D_FORMAT_MAX,
+ };
+ 
+-enum trigger_delay {
+-	TRIGGER_DELAY_NEXT_PIXEL = 0,
+-	TRIGGER_DELAY_NEXT_LINE,
+-};
+-
+-enum crtc_event {
+-	CRTC_EVENT_VSYNC_RISING = 0,
+-	CRTC_EVENT_VSYNC_FALLING
+-};
+-
+-struct crtc_trigger_info {
+-	bool enabled;
+-	struct dc_stream_state *event_source;
+-	enum crtc_event event;
+-	enum trigger_delay delay;
+-};
+-
+-struct dc_crtc_timing_adjust {
+-	uint32_t v_total_min;
+-	uint32_t v_total_max;
+-	uint32_t v_total_mid;
+-	uint32_t v_total_mid_frame_num;
+-};
+-
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ struct dc_dsc_config {
+ 	uint32_t num_slices_h; /* Number of DSC slices - horizontal */
+@@ -775,6 +755,33 @@ struct dc_crtc_timing {
+ #endif
+ };
+ 
++#ifndef AMD_EDID_UTILITY
++
++enum trigger_delay {
++	TRIGGER_DELAY_NEXT_PIXEL = 0,
++	TRIGGER_DELAY_NEXT_LINE,
++};
++
++enum crtc_event {
++	CRTC_EVENT_VSYNC_RISING = 0,
++	CRTC_EVENT_VSYNC_FALLING
++};
++
++struct crtc_trigger_info {
++	bool enabled;
++	struct dc_stream_state *event_source;
++	enum crtc_event event;
++	enum trigger_delay delay;
++};
++
++struct dc_crtc_timing_adjust {
++	uint32_t v_total_min;
++	uint32_t v_total_max;
++	uint32_t v_total_mid;
++	uint32_t v_total_mid_frame_num;
++};
++
++
+ /* Passed on init */
+ enum vram_type {
+ 	VIDEO_MEMORY_TYPE_GDDR5  = 2,
+@@ -845,5 +852,7 @@ struct tg_color {
+ 	uint16_t color_b_cb;
+ };
+ 
++#endif /* AMD_EDID_UTILITY */
++
+ #endif /* DC_HW_TYPES_H */
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
+index f4ccdb2e3c32..ed60bf011af2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
+@@ -25,6 +25,11 @@
+ #ifndef DC_TYPES_H_
+ #define DC_TYPES_H_
+ 
++#ifndef AMD_EDID_UTILITY
++/* AND EdidUtility only needs a portion
++ * of this file, including the rest only
++ * causes additional issues.
++ */
+ #include "os_types.h"
+ #include "fixed31_32.h"
+ #include "irq_types.h"
+@@ -754,6 +759,9 @@ struct dc_clock_config {
+ 	uint32_t current_clock_khz;/*current clock in use*/
+ };
+ 
++#endif /*AMD_EDID_UTILITY*/
++//AMD EDID UTILITY does not need any of the above structures
++
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* DSC DPCD capabilities */
+ union dsc_slice_caps1 {
+@@ -825,4 +833,5 @@ struct dsc_dec_dpcd_caps {
+ 	uint32_t branch_max_line_width;
+ };
+ #endif
++
+ #endif /* DC_TYPES_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+index 929ebd4cfb8c..e60f760585e4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+@@ -23,8 +23,7 @@
+  */
+ 
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-#include "dc.h"
+-#include "core_types.h"
++#include "dc_hw_types.h"
+ #include "dsc.h"
+ #include <drm/drm_dp_helper.h>
+ 
+@@ -47,6 +46,59 @@ const struct dc_dsc_policy dsc_policy = {
+ 
+ /* This module's internal functions */
+ 
++static uint32_t dc_dsc_bandwidth_in_kbps_from_timing(
++	const struct dc_crtc_timing *timing)
++{
++	uint32_t bits_per_channel = 0;
++	uint32_t kbps;
++
++	if (timing->flags.DSC) {
++		kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel);
++		kbps = kbps / 160 + ((kbps % 160) ? 1 : 0);
++		return kbps;
++	}
++
++	switch (timing->display_color_depth) {
++	case COLOR_DEPTH_666:
++		bits_per_channel = 6;
++		break;
++	case COLOR_DEPTH_888:
++		bits_per_channel = 8;
++		break;
++	case COLOR_DEPTH_101010:
++		bits_per_channel = 10;
++		break;
++	case COLOR_DEPTH_121212:
++		bits_per_channel = 12;
++		break;
++	case COLOR_DEPTH_141414:
++		bits_per_channel = 14;
++		break;
++	case COLOR_DEPTH_161616:
++		bits_per_channel = 16;
++		break;
++	default:
++		break;
++	}
++
++	ASSERT(bits_per_channel != 0);
++
++	kbps = timing->pix_clk_100hz / 10;
++	kbps *= bits_per_channel;
++
++	if (timing->flags.Y_ONLY != 1) {
++		/*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
++		kbps *= 3;
++		if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
++			kbps /= 2;
++		else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
++			kbps = kbps * 2 / 3;
++	}
++
++	return kbps;
++
++}
++
+ static bool dsc_buff_block_size_from_dpcd(int dpcd_buff_block_size, int *buff_block_size)
+ {
+ 
+@@ -178,12 +230,11 @@ static bool dsc_bpp_increment_div_from_dpcd(int bpp_increment_dpcd, uint32_t *bp
+ }
+ 
+ static void get_dsc_enc_caps(
+-	const struct dc *dc,
++	const struct display_stream_compressor *dsc,
+ 	struct dsc_enc_caps *dsc_enc_caps,
+ 	int pixel_clock_100Hz)
+ {
+ 	// This is a static HW query, so we can use any DSC
+-	struct display_stream_compressor *dsc = dc->res_pool->dscs[0];
+ 
+ 	memset(dsc_enc_caps, 0, sizeof(struct dsc_enc_caps));
+ 	if (dsc)
+@@ -290,7 +341,7 @@ static void get_dsc_bandwidth_range(
+ 		struct dc_dsc_bw_range *range)
+ {
+ 	/* native stream bandwidth */
+-	range->stream_kbps = dc_bandwidth_in_kbps_from_timing(timing);
++	range->stream_kbps = dc_dsc_bandwidth_in_kbps_from_timing(timing);
+ 
+ 	/* max dsc target bpp */
+ 	range->max_kbps = dsc_div_by_10_round_up(max_bpp * timing->pix_clk_100hz);
+@@ -806,7 +857,8 @@ bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_basic_data, const uint8_t *dp
+  * If DSC is not possible, leave '*range' untouched.
+  */
+ bool dc_dsc_compute_bandwidth_range(
+-		const struct dc *dc,
++		const struct display_stream_compressor *dsc,
++		const uint32_t dsc_min_slice_height_override,
+ 		const uint32_t min_bpp,
+ 		const uint32_t max_bpp,
+ 		const struct dsc_dec_dpcd_caps *dsc_sink_caps,
+@@ -818,14 +870,14 @@ bool dc_dsc_compute_bandwidth_range(
+ 	struct dsc_enc_caps dsc_common_caps;
+ 	struct dc_dsc_config config;
+ 
+-	get_dsc_enc_caps(dc, &dsc_enc_caps, timing->pix_clk_100hz);
++	get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);
+ 
+ 	is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, &dsc_enc_caps,
+ 			timing->pixel_encoding, &dsc_common_caps);
+ 
+ 	if (is_dsc_possible)
+ 		is_dsc_possible = setup_dsc_config(dsc_sink_caps, &dsc_enc_caps, 0, timing,
+-					dc->debug.dsc_min_slice_height_override, &config);
++				dsc_min_slice_height_override, &config);
+ 
+ 	if (is_dsc_possible)
+ 		get_dsc_bandwidth_range(min_bpp, max_bpp, &dsc_common_caps, timing, range);
+@@ -834,8 +886,9 @@ bool dc_dsc_compute_bandwidth_range(
+ }
+ 
+ bool dc_dsc_compute_config(
+-		const struct dc *dc,
++		const struct display_stream_compressor *dsc,
+ 		const struct dsc_dec_dpcd_caps *dsc_sink_caps,
++		const uint32_t dsc_min_slice_height_override,
+ 		uint32_t target_bandwidth_kbps,
+ 		const struct dc_crtc_timing *timing,
+ 		struct dc_dsc_config *dsc_cfg)
+@@ -843,11 +896,11 @@ bool dc_dsc_compute_config(
+ 	bool is_dsc_possible = false;
+ 	struct dsc_enc_caps dsc_enc_caps;
+ 
+-	get_dsc_enc_caps(dc, &dsc_enc_caps, timing->pix_clk_100hz);
++	get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);
+ 	is_dsc_possible = setup_dsc_config(dsc_sink_caps,
+ 			&dsc_enc_caps,
+ 			target_bandwidth_kbps,
+-			timing, dc->debug.dsc_min_slice_height_override, dsc_cfg);
++			timing, dsc_min_slice_height_override, dsc_cfg);
+ 	return is_dsc_possible;
+ }
+ #endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
+index 1ddb1c6fa149..c6ff3d78b435 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
+@@ -28,7 +28,11 @@
+ 
+ #include "dc_dsc.h"
+ #include "dc_hw_types.h"
+-#include "dc_dp_types.h"
++#include "dc_types.h"
++/* do not include any other headers
++ * or else it might break Edid Utility functionality.
++ */
++
+ 
+ /* Input parameters for configuring DSC from the outside of DSC */
+ struct dsc_config {
+@@ -81,12 +85,6 @@ struct dsc_enc_caps {
+ 	uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
+ };
+ 
+-struct display_stream_compressor {
+-	const struct dsc_funcs *funcs;
+-	struct dc_context *ctx;
+-	int inst;
+-};
+-
+ struct dsc_funcs {
+ 	void (*dsc_get_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
+ 	void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3720-drm-amd-display-dce11.x-dce12-update-formula-input.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3720-drm-amd-display-dce11.x-dce12-update-formula-input.patch
new file mode 100644
index 00000000..bbe5020f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3720-drm-amd-display-dce11.x-dce12-update-formula-input.patch
@@ -0,0 +1,160 @@
+From 7c4645c4d76b06e69ded4643508b563259d0633f Mon Sep 17 00:00:00 2001
+From: Charlene Liu <charlene.liu@amd.com>
+Date: Tue, 20 Aug 2019 20:33:46 -0400
+Subject: [PATCH 3720/4256] drm/amd/display: dce11.x /dce12 update formula
+ input
+
+[Description]
+1. OUTSTANDING_REQUEST_LIMIT update from 0xFF to 0x1F (HW doc update)
+2. using memory type to convert UMC's MCLK to Yclk.
+
+Signed-off-by: Charlene Liu <charlene.liu@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../display/dc/clk_mgr/dce110/dce110_clk_mgr.c   |  7 +++++--
+ .../gpu/drm/amd/display/dc/dce/dce_mem_input.c   |  4 ++--
+ .../drm/amd/display/dc/dce112/dce112_resource.c  | 16 ++++++++++------
+ .../drm/amd/display/dc/dce120/dce120_resource.c  | 11 ++++++++---
+ drivers/gpu/drm/amd/display/dc/inc/resource.h    |  2 ++
+ 5 files changed, 27 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+index 5cc3acccda2a..ee32d2c19305 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+@@ -98,11 +98,14 @@ uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
+ 		struct dc_stream_state *stream = context->streams[j];
+ 		uint32_t vertical_blank_in_pixels = 0;
+ 		uint32_t vertical_blank_time = 0;
++		uint32_t vertical_total_min = stream->timing.v_total;
++		struct dc_crtc_timing_adjust adjust = stream->adjust;
++		if (adjust.v_total_max != adjust.v_total_min)
++			vertical_total_min = adjust.v_total_min;
+ 
+ 		vertical_blank_in_pixels = stream->timing.h_total *
+-			(stream->timing.v_total
++			(vertical_total_min
+ 			 - stream->timing.v_addressable);
+-
+ 		vertical_blank_time = vertical_blank_in_pixels
+ 			* 10000 / stream->timing.pix_clk_100hz;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+index 1488ffddf4e3..31b698bf9cfc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+@@ -148,7 +148,7 @@ static void dce_mi_program_pte_vm(
+ 			pte->min_pte_before_flip_horiz_scan;
+ 
+ 	REG_UPDATE(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT,
+-			GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, 0xff);
++			GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, 0x7f);
+ 
+ 	REG_UPDATE_3(DVMM_PTE_CONTROL,
+ 			DVMM_PAGE_WIDTH, page_width,
+@@ -157,7 +157,7 @@ static void dce_mi_program_pte_vm(
+ 
+ 	REG_UPDATE_2(DVMM_PTE_ARB_CONTROL,
+ 			DVMM_PTE_REQ_PER_CHUNK, pte->pte_req_per_chunk,
+-			DVMM_MAX_PTE_REQ_OUTSTANDING, 0xff);
++			DVMM_MAX_PTE_REQ_OUTSTANDING, 0x7f);
+ }
+ 
+ static void program_urgency_watermark(
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+index e327d98b54ca..65f17bbdef2a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+@@ -985,6 +985,10 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
+ 	struct dm_pp_clock_levels_with_latency mem_clks = {0};
+ 	struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
+ 	struct dm_pp_clock_levels clks = {0};
++	int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
++
++	if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm)
++		memory_type_multiplier = MEMORY_TYPE_HBM;
+ 
+ 	/*do system clock  TODO PPLIB: after PPLIB implement,
+ 	 * then remove old way
+@@ -1024,12 +1028,12 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
+ 				&clks);
+ 
+ 		dc->bw_vbios->low_yclk = bw_frc_to_fixed(
+-			clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000);
++			clks.clocks_in_khz[0] * memory_type_multiplier, 1000);
+ 		dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
+-			clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ,
++			clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier,
+ 			1000);
+ 		dc->bw_vbios->high_yclk = bw_frc_to_fixed(
+-			clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ,
++			clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier,
+ 			1000);
+ 
+ 		return;
+@@ -1065,12 +1069,12 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
+ 	 * YCLK = UMACLK*m_memoryTypeMultiplier
+ 	 */
+ 	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
+-		mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1000);
++		mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);
+ 	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
+-		mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ,
++		mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier,
+ 		1000);
+ 	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
+-		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ,
++		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,
+ 		1000);
+ 
+ 	/* Now notify PPLib/SMU about which Watermarks sets they should select
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index c4588d6462a4..c10392bbcb38 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -845,6 +845,8 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
+ 	int i;
+ 	unsigned int clk;
+ 	unsigned int latency;
++	/*original logic in dal3*/
++	int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
+ 
+ 	/*do system clock*/
+ 	if (!dm_pp_get_clock_levels_by_type_with_latency(
+@@ -903,13 +905,16 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
+ 	 * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
+ 	 * YCLK = UMACLK*m_memoryTypeMultiplier
+ 	 */
++	if (dc->bw_vbios->memory_type == bw_def_hbm)
++		memory_type_multiplier = MEMORY_TYPE_HBM;
++
+ 	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
+-		mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1000);
++		mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);
+ 	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
+-		mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ,
++		mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier,
+ 		1000);
+ 	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
+-		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ,
++		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,
+ 		1000);
+ 
+ 	/* Now notify PPLib/SMU about which Watermarks sets they should select
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
+index 1cc1c8ce633b..bef224bf803e 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
+@@ -31,6 +31,8 @@
+ #include "dm_pp_smu.h"
+ 
+ #define MEMORY_TYPE_MULTIPLIER_CZ 4
++#define MEMORY_TYPE_HBM 2
++
+ 
+ enum dce_version resource_parse_asic_id(
+ 		struct hw_asic_id asic_id);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3721-drm-amd-display-verify-stream-link-before-link-test.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3721-drm-amd-display-verify-stream-link-before-link-test.patch
new file mode 100644
index 00000000..c070e7b8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3721-drm-amd-display-verify-stream-link-before-link-test.patch
@@ -0,0 +1,37 @@
+From da31b0384a98b84fa4ff9d9e7da6e54d34f29f0d Mon Sep 17 00:00:00 2001
+From: Jing Zhou <Jing.Zhou@amd.com>
+Date: Thu, 22 Aug 2019 14:26:33 +0800
+Subject: [PATCH 3721/4256] drm/amd/display: verify stream link before link
+ test
+
+[Why]
+DP1.2 LL CTS test failure.
+
+[How]
+The failure is caused by not verify stream link is equal
+to link, only check stream and link is not null.
+
+Signed-off-by: Jing Zhou <Jing.Zhou@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index 79438c4f1e20..a519dbc5ecb6 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -277,7 +277,8 @@ void dp_retrain_link_dp_test(struct dc_link *link,
+ 		if (pipes[i].stream != NULL &&
+ 			!pipes[i].top_pipe && !pipes[i].prev_odm_pipe &&
+ 			pipes[i].stream->link != NULL &&
+-			pipes[i].stream_res.stream_enc != NULL) {
++			pipes[i].stream_res.stream_enc != NULL &&
++			pipes[i].stream->link == link) {
+ 			udelay(100);
+ 
+ 			pipes[i].stream_res.stream_enc->funcs->dp_blank(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3722-drm-amd-display-replace-FIXME-with-TODO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3722-drm-amd-display-replace-FIXME-with-TODO.patch
new file mode 100644
index 00000000..e0416e4b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3722-drm-amd-display-replace-FIXME-with-TODO.patch
@@ -0,0 +1,146 @@
+From 40c33546d84b5ec1552dcea57f02599cf03a29cc Mon Sep 17 00:00:00 2001
+From: Qingqing Zhuo <qingqing.zhuo@amd.com>
+Date: Thu, 22 Aug 2019 15:28:26 -0400
+Subject: [PATCH 3722/4256] drm/amd/display: replace FIXME with TODO
+
+Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c  |  8 ++++----
+ .../display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c    |  8 ++++----
+ .../drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c  | 10 +++++-----
+ 3 files changed, 13 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
+index 878bf4782ce6..2c7455e22a65 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
+@@ -207,7 +207,7 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib,
+ 	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
+ 	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
+ 
+-	// FIXME: take the max between luma, chroma chunk size?
++	// TODO: take the max between luma, chroma chunk size?
+ 	// okay for now, as we are setting chunk_bytes to 8kb anyways
+ 	if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb
+ 		rq_regs->drq_expansion_mode = 0;
+@@ -677,7 +677,7 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib,
+ 	unsigned int meta_pitch = 0;
+ 	unsigned int ppe = mode_422 ? 2 : 1;
+ 
+-	// FIXME check if ppe apply for both luma and chroma in 422 case
++	// TODO check if ppe apply for both luma and chroma in 422 case
+ 	if (is_chroma) {
+ 		vp_width = pipe_src_param.viewport_width_c / ppe;
+ 		vp_height = pipe_src_param.viewport_height_c;
+@@ -959,7 +959,7 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
+ 	// Source
+ //             dcc_en              = src.dcc;
+ 	dual_plane = is_dual_plane((enum source_format_class)(src->source_format));
+-	mode_422 = 0; // FIXME
++	mode_422 = 0; // TODO
+ 	access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
+ //      bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0);
+ //      bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1);
+@@ -1655,7 +1655,7 @@ static void calculate_ttu_cursor(struct display_mode_lib *mode_lib,
+ 		cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1)
+ 				* (double) cur_req_width;
+ 		cur_req_per_width = cur_width_ub / (double) cur_req_width;
+-		hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor
++		hactive_cur = (double) cur_src_width / hscl_ratio; // TODO: oswin to think about what to do for cursor
+ 
+ 		if (vratio_pre_l <= 1.0) {
+ 			*refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
+index ed8bf5f723c9..1e6aeb1bd2bf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
+@@ -207,7 +207,7 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib,
+ 	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
+ 	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
+ 
+-	// FIXME: take the max between luma, chroma chunk size?
++	// TODO: take the max between luma, chroma chunk size?
+ 	// okay for now, as we are setting chunk_bytes to 8kb anyways
+ 	if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb
+ 		rq_regs->drq_expansion_mode = 0;
+@@ -677,7 +677,7 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib,
+ 	unsigned int meta_pitch = 0;
+ 	unsigned int ppe = mode_422 ? 2 : 1;
+ 
+-	// FIXME check if ppe apply for both luma and chroma in 422 case
++	// TODO check if ppe apply for both luma and chroma in 422 case
+ 	if (is_chroma) {
+ 		vp_width = pipe_src_param.viewport_width_c / ppe;
+ 		vp_height = pipe_src_param.viewport_height_c;
+@@ -959,7 +959,7 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
+ 	// Source
+ //             dcc_en              = src.dcc;
+ 	dual_plane = is_dual_plane((enum source_format_class)(src->source_format));
+-	mode_422 = 0; // FIXME
++	mode_422 = 0; // TODO
+ 	access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
+ //      bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0);
+ //      bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1);
+@@ -1655,7 +1655,7 @@ static void calculate_ttu_cursor(struct display_mode_lib *mode_lib,
+ 		cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1)
+ 				* (double) cur_req_width;
+ 		cur_req_per_width = cur_width_ub / (double) cur_req_width;
+-		hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor
++		hactive_cur = (double) cur_src_width / hscl_ratio; // TODO: oswin to think about what to do for cursor
+ 
+ 		if (vratio_pre_l <= 1.0) {
+ 			*refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
+index ad8571f5a142..4c3e9cc30167 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
+@@ -243,7 +243,7 @@ void dml1_extract_rq_regs(
+ 	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
+ 	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
+ 
+-	/* FIXME: take the max between luma, chroma chunk size?
++	/* TODO: take the max between luma, chroma chunk size?
+ 	 * okay for now, as we are setting chunk_bytes to 8kb anyways
+ 	 */
+ 	if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { /*32kb */
+@@ -602,7 +602,7 @@ static void get_surf_rq_param(
+ 	unsigned int log2_dpte_group_length;
+ 	unsigned int func_meta_row_height, func_dpte_row_height;
+ 
+-	/* FIXME check if ppe apply for both luma and chroma in 422 case */
++	/* TODO check if ppe apply for both luma and chroma in 422 case */
+ 	if (is_chroma) {
+ 		vp_width = pipe_src_param.viewport_width_c / ppe;
+ 		vp_height = pipe_src_param.viewport_height_c;
+@@ -1141,7 +1141,7 @@ void dml1_rq_dlg_get_dlg_params(
+ 	ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));
+ 	disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; /* 15 bits */
+ 
+-	prefetch_xy_calc_in_dcfclk = 24.0; /* FIXME: ip_param */
++	prefetch_xy_calc_in_dcfclk = 24.0; /* TODO: ip_param */
+ 	min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;
+ 	t_calc_us = prefetch_xy_calc_in_dcfclk / min_dcfclk_mhz;
+ 	min_ttu_vblank = dlg_sys_param.t_urg_wm_us;
+@@ -1182,7 +1182,7 @@ void dml1_rq_dlg_get_dlg_params(
+ 	dcc_en = e2e_pipe_param.pipe.src.dcc;
+ 	dual_plane = is_dual_plane(
+ 			(enum source_format_class) e2e_pipe_param.pipe.src.source_format);
+-	mode_422 = 0; /* FIXME */
++	mode_422 = 0; /* TODO */
+ 	access_dir = (e2e_pipe_param.pipe.src.source_scan == dm_vert); /* vp access direction: horizontal or vertical accessed */
+ 	bytes_per_element_l = get_bytes_per_element(
+ 			(enum source_format_class) e2e_pipe_param.pipe.src.source_format,
+@@ -1837,7 +1837,7 @@ void dml1_rq_dlg_get_dlg_params(
+ 		cur0_width_ub = dml_ceil((double) cur0_src_width / (double) cur0_req_width, 1)
+ 				* (double) cur0_req_width;
+ 		cur0_req_per_width = cur0_width_ub / (double) cur0_req_width;
+-		hactive_cur0 = (double) cur0_src_width / hratios_cur0; /* FIXME: oswin to think about what to do for cursor */
++		hactive_cur0 = (double) cur0_src_width / hratios_cur0; /* TODO: oswin to think about what to do for cursor */
+ 
+ 		if (vratio_pre_l <= 1.0) {
+ 			refcyc_per_req_delivery_pre_cur0 = hactive_cur0 * ref_freq_to_pix_freq
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3723-drm-amdgpu-Add-a-kernel-parameter-for-specifying-the.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3723-drm-amdgpu-Add-a-kernel-parameter-for-specifying-the.patch
new file mode 100644
index 00000000..ae36effa
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3723-drm-amdgpu-Add-a-kernel-parameter-for-specifying-the.patch
@@ -0,0 +1,283 @@
+From a72d05380ab34f16462a14fbf7a695ea410b5f77 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 30 Aug 2019 18:09:10 -0400
+Subject: [PATCH 3723/4256] drm/amdgpu: Add a kernel parameter for specifying
+ the asic type
+
+As more and more new asics start to reuse the old device IDs before
+launch, there is a need to quickly override the existing asic type
+corresponding to the reused device ID through a kernel parameter. With
+this, engineers no longer need to rely on local hack patches,
+facilitating cooperation across teams.
+
+Change-Id: Ic948ec8125bf28c9775f2f27673d0b69f2916c71
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h           |  1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |  8 ++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c       | 11 ++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c       |  1 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c        |  4 +-
+ drivers/gpu/drm/amd/amdgpu/psp_v10_0.c        |  3 -
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  2 -
+ drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   |  1 -
+ .../drm/amd/powerplay/hwmgr/processpptables.c |  8 +--
+ include/drm/amd_asic_type.h                   | 55 +++++++++----------
+ 10 files changed, 51 insertions(+), 43 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 125987f884a9..b2999b81f923 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -172,6 +172,7 @@ extern int amdgpu_mcbp;
+ extern int amdgpu_discovery;
+ extern int amdgpu_mes;
+ extern int amdgpu_noretry;
++extern int amdgpu_force_asic_type;
+ 
+ #ifdef CONFIG_DRM_AMDGPU_SI
+ extern int amdgpu_si_support;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index b7276f9e814b..2d65e8eb687d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2489,7 +2489,6 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
+ 	case CHIP_VEGA20:
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ 	case CHIP_RAVEN:
+-	case CHIP_PICASSO:
+ #endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	case CHIP_NAVI10:
+@@ -2560,7 +2559,12 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ 	adev->ddev = ddev;
+ 	adev->pdev = pdev;
+ 	adev->flags = flags;
+-	adev->asic_type = flags & AMD_ASIC_MASK;
++
++	if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
++		adev->asic_type = amdgpu_force_asic_type;
++	else
++		adev->asic_type = flags & AMD_ASIC_MASK;
++
+ 	adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
+ 	if (amdgpu_emu_mode == 1)
+ 		adev->usec_timeout *= 2;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 23fce40922e9..2de8db5e864c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -147,6 +147,7 @@ int amdgpu_mcbp = 0;
+ int amdgpu_discovery = -1;
+ int amdgpu_mes = 0;
+ int amdgpu_noretry = 1;
++int amdgpu_force_asic_type = -1;
+ 
+ struct amdgpu_mgpu_info mgpu_info = {
+ 	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
+@@ -626,6 +627,16 @@ MODULE_PARM_DESC(noretry,
+ 	"Disable retry faults (0 = retry enabled, 1 = retry disabled (default))");
+ module_param_named(noretry, amdgpu_noretry, int, 0644);
+ 
++/**
++ * DOC: force_asic_type (int)
++ * A non negative value used to specify the asic type for all supported GPUs.
++ */
++MODULE_PARM_DESC(force_asic_type,
++	"A non negative value used to specify the asic type for all supported GPUs");
++module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
++
++
++
+ #ifdef CONFIG_HSA_AMD
+ /**
+  * DOC: sched_policy (int)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index d92444ac1fc5..52b02ce626e1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -50,7 +50,6 @@ static int psp_early_init(void *handle)
+ 		psp->autoload_supported = false;
+ 		break;
+ 	case CHIP_RAVEN:
+-	case CHIP_PICASSO:
+ 		psp_v10_0_set_psp_funcs(psp);
+ 		psp->autoload_supported = false;
+ 		break;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index dd5b5875f874..31b25d27e50e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -2660,7 +2660,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ 		vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
+ 						AMDGPU_VM_USE_CPU_FOR_COMPUTE);
+ 
+-		if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO)
++		if (adev->asic_type == CHIP_RAVEN)
+ 			vm->pte_support_ats = true;
+ 	} else {
+ 		vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
+@@ -2785,7 +2785,7 @@ static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
+  */
+ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+ {
+-	bool pte_support_ats = (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO);
++	bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
+ 	int r;
+ 
+ 	r = amdgpu_bo_reserve(vm->root.base.bo, true);
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+index 216af0af255a..e5fff6b30137 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+@@ -57,9 +57,6 @@ static int psp_v10_0_init_microcode(struct psp_context *psp)
+ 		else
+ 			chip_name = "raven";
+ 		break;
+-	case CHIP_PICASSO:
+-		chip_name = "picasso";
+-		break;
+ 	default: BUG();
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 65aff741befb..a0ae950d3a60 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -2360,7 +2360,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
+ 		break;
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ 	case CHIP_RAVEN:
+-	case CHIP_PICASSO:
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+@@ -2602,7 +2601,6 @@ static int dm_early_init(void *handle)
+ 		break;
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ 	case CHIP_RAVEN:
+-	case CHIP_PICASSO:
+ 		adev->mode_info.num_crtc = 4;
+ 		adev->mode_info.num_hpd = 4;
+ 		adev->mode_info.num_dig = 4;
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+index 873bf65e34d4..e8d4292bc4f0 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+@@ -173,7 +173,6 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
+ 	case AMDGPU_FAMILY_RV:
+ 		switch (hwmgr->chip_id) {
+ 		case CHIP_RAVEN:
+-		case CHIP_PICASSO:
+ 			hwmgr->od_enabled = false;
+ 			hwmgr->smumgr_funcs = &smu10_smu_funcs;
+ 			smu10_init_function_pointers(hwmgr);
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
+index f6fe9ce793ad..77c14671866c 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
+@@ -832,7 +832,7 @@ static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table(
+ 	uint16_t size;
+ 
+ 	if (!table_addr) {
+-		if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO) {
++		if (hwmgr->chip_id == CHIP_RAVEN) {
+ 			table_addr = &soft_dummy_pp_table[0];
+ 			hwmgr->soft_pp_table = &soft_dummy_pp_table[0];
+ 			hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table);
+@@ -1055,7 +1055,7 @@ static int init_overdrive_limits(struct pp_hwmgr *hwmgr,
+ 	hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
+ 	hwmgr->platform_descriptor.overdriveVDDCStep = 0;
+ 
+-	if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO)
++	if (hwmgr->chip_id == CHIP_RAVEN)
+ 		return 0;
+ 
+ 	/* We assume here that fw_info is unchanged if this call fails.*/
+@@ -1595,7 +1595,7 @@ static int pp_tables_initialize(struct pp_hwmgr *hwmgr)
+ 	int result;
+ 	const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table;
+ 
+-	if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO)
++	if (hwmgr->chip_id == CHIP_RAVEN)
+ 		return 0;
+ 
+ 	hwmgr->need_pp_table_upload = true;
+@@ -1644,7 +1644,7 @@ static int pp_tables_initialize(struct pp_hwmgr *hwmgr)
+ 
+ static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
+ {
+-	if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO)
++	if (hwmgr->chip_id == CHIP_RAVEN)
+ 		return 0;
+ 
+ 	kfree(hwmgr->dyn_state.vddc_dependency_on_sclk);
+diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
+index a4a80ce18a7a..a26d8bcd1a38 100644
+--- a/include/drm/amd_asic_type.h
++++ b/include/drm/amd_asic_type.h
+@@ -27,34 +27,33 @@
+  */
+ enum amd_asic_type {
+ 	CHIP_TAHITI = 0,
+-	CHIP_PITCAIRN,
+-	CHIP_VERDE,
+-	CHIP_OLAND,
+-	CHIP_HAINAN,
+-	CHIP_BONAIRE,
+-	CHIP_KAVERI,
+-	CHIP_KABINI,
+-	CHIP_HAWAII,
+-	CHIP_MULLINS,
+-	CHIP_TOPAZ,
+-	CHIP_TONGA,
+-	CHIP_FIJI,
+-	CHIP_CARRIZO,
+-	CHIP_STONEY,
+-	CHIP_POLARIS10,
+-	CHIP_POLARIS11,
+-	CHIP_POLARIS12,
+-	CHIP_VEGAM,
+-	CHIP_VEGA10,
+-	CHIP_VEGA12,
+-	CHIP_VEGA20,
+-	CHIP_RAVEN,
+-	CHIP_ARCTURUS,
+-	CHIP_RENOIR,
+-	CHIP_PICASSO,
+-	CHIP_NAVI10,
+-	CHIP_NAVI14,
+-	CHIP_NAVI12,
++        CHIP_PITCAIRN,  /* 1 */
++        CHIP_VERDE,     /* 2 */
++        CHIP_OLAND,     /* 3 */
++        CHIP_HAINAN,    /* 4 */
++        CHIP_BONAIRE,   /* 5 */
++        CHIP_KAVERI,    /* 6 */
++        CHIP_KABINI,    /* 7 */
++        CHIP_HAWAII,    /* 8 */
++        CHIP_MULLINS,   /* 9 */
++        CHIP_TOPAZ,     /* 10 */
++        CHIP_TONGA,     /* 11 */
++        CHIP_FIJI,      /* 12 */
++        CHIP_CARRIZO,   /* 13 */
++        CHIP_STONEY,    /* 14 */
++        CHIP_POLARIS10, /* 15 */
++        CHIP_POLARIS11, /* 16 */
++        CHIP_POLARIS12, /* 17 */
++        CHIP_VEGAM,     /* 18 */
++        CHIP_VEGA10,    /* 19 */
++        CHIP_VEGA12,    /* 20 */
++        CHIP_VEGA20,    /* 21 */
++        CHIP_RAVEN,     /* 22 */
++        CHIP_ARCTURUS,  /* 23 */
++        CHIP_RENOIR,    /* 24 */
++        CHIP_NAVI10,    /* 25 */
++        CHIP_NAVI14,    /* 26 */
++        CHIP_NAVI12,    /* 27 */
+ 	CHIP_LAST,
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3724-drm-amdgpu-Disable-retry-faults-in-VMID0.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3724-drm-amdgpu-Disable-retry-faults-in-VMID0.patch
new file mode 100644
index 00000000..f172ef3b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3724-drm-amdgpu-Disable-retry-faults-in-VMID0.patch
@@ -0,0 +1,86 @@
+From 2a92f59c8b458cc83e755ad613b4928a2e1b311c Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Wed, 4 Sep 2019 19:26:16 -0400
+Subject: [PATCH 3724/4256] drm/amdgpu: Disable retry faults in VMID0
+
+There is no point retrying page faults in VMID0. Those faults are
+always fatal.
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-and-Tested-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 ++
+ drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 2 ++
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 2 ++
+ drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c  | 2 ++
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c  | 2 ++
+ 5 files changed, 10 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+index 052c924952b9..db8baf733508 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+@@ -178,6 +178,8 @@ static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
+ 	tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);
+ 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
+ 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
++			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
+ 	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+index 8b789f750b72..a9238735d361 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+@@ -166,6 +166,8 @@ static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
+ 	tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);
+ 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
+ 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
++	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
++			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
+ 	WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index ece27e27658f..3b28c1c0cf21 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -207,6 +207,8 @@ static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
+ 	tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL);
+ 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
+ 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
++	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
++			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
+ 	WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp);
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+index 3542c203c3c8..86ed8cb915a8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+@@ -152,6 +152,8 @@ static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
+ 	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
+ 	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
+ 	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
++	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
++			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
+ 	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+index 0cf7ef44b4b5..657970f9ebfb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+@@ -240,6 +240,8 @@ static void mmhub_v9_4_enable_system_domain(struct amdgpu_device *adev,
+ 				  hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
+ 	tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
+ 	tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
++	tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL,
++			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
+ 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
+ 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3725-drm-amdkfd-Support-Navi14-in-KFD.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3725-drm-amdkfd-Support-Navi14-in-KFD.patch
new file mode 100644
index 00000000..61ca456e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3725-drm-amdkfd-Support-Navi14-in-KFD.patch
@@ -0,0 +1,132 @@
+From 4e9661a52ce93392c3dd05cc013b3536c5e886df Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Tue, 13 Aug 2019 17:13:27 -0400
+Subject: [PATCH 3725/4256] drm/amdkfd: Support Navi14 in KFD
+
+Initial support of Navi14 in KFD. The device IDs will be added later.
+
+Change-Id: Ie2c6226022ff4d389eaa05b1c84afa7ae4cea0aa
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_crat.c         |  1 +
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c       | 19 +++++++++++++++++++
+ .../drm/amd/amdkfd/kfd_device_queue_manager.c |  1 +
+ drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c  |  1 +
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c |  1 +
+ .../gpu/drm/amd/amdkfd/kfd_packet_manager.c   |  1 +
+ drivers/gpu/drm/amd/amdkfd/kfd_topology.c     |  1 +
+ 7 files changed, 25 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+index 4d6427440758..a95e6bc2f7f9 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+@@ -671,6 +671,7 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
+ 		num_of_cache_types = ARRAY_SIZE(raven_cache_info);
+ 		break;
+ 	case CHIP_NAVI10:
++	case CHIP_NAVI14:
+ 		pcache_info = navi10_cache_info;
+ 		num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
+ 		break;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index cf8fb7dcaccf..63dbe5fe20f0 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -369,6 +369,24 @@ static const struct kfd_device_info navi10_device_info = {
+ 	.num_sdma_queues_per_engine = 8,
+ };
+ 
++static const struct kfd_device_info navi14_device_info = {
++	.asic_family = CHIP_NAVI14,
++	.asic_name = "navi14",
++	.max_pasid_bits = 16,
++	.max_no_of_hqd  = 24,
++	.doorbell_size  = 8,
++	.ih_ring_entry_size = 8 * sizeof(uint32_t),
++	.event_interrupt_class = &event_interrupt_class_v9,
++	.num_of_watch_points = 4,
++	.mqd_size_aligned = MQD_SIZE_ALIGNED,
++	.needs_iommu_device = false,
++	.supports_cwsr = true,
++	.needs_pci_atomics = false,
++	.num_sdma_engines = 2,
++	.num_xgmi_sdma_engines = 0,
++	.num_sdma_queues_per_engine = 8,
++};
++
+ /* For each entry, [0] is regular and [1] is virtualisation device. */
+ static const struct kfd_device_info *kfd_supported_devices[][2] = {
+ #ifdef KFD_SUPPORT_IOMMU_V2
+@@ -388,6 +406,7 @@ static const struct kfd_device_info *kfd_supported_devices[][2] = {
+ 	[CHIP_VEGA20] = {&vega20_device_info, NULL},
+ 	[CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info},
+ 	[CHIP_NAVI10] = {&navi10_device_info, NULL},
++	[CHIP_NAVI14] = {&navi14_device_info, NULL},
+ };
+ 
+ static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 53862d66d065..35dc1d1e0413 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -1883,6 +1883,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
+ 		device_queue_manager_init_v9(&dqm->asic_ops);
+ 		break;
+ 	case CHIP_NAVI10:
++	case CHIP_NAVI14:
+ 		device_queue_manager_init_v10_navi10(&dqm->asic_ops);
+ 		break;
+ 	default:
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+index ee7ff6b0541b..ed4efab0a190 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+@@ -412,6 +412,7 @@ int kfd_init_apertures(struct kfd_process *process)
+ 			case CHIP_RAVEN:
+ 			case CHIP_ARCTURUS:
+ 			case CHIP_NAVI10:
++			case CHIP_NAVI14:
+ 				kfd_init_apertures_v9(pdd, id);
+ 				break;
+ 			default:
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+index 7a3b0482ab1a..1097e047b4bb 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+@@ -368,6 +368,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
+ 		kernel_queue_init_v9(&kq->ops_asic_specific);
+ 		break;
+ 	case CHIP_NAVI10:
++	case CHIP_NAVI14:
+ 		kernel_queue_init_v10(&kq->ops_asic_specific);
+ 		break;
+ 	default:
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+index 6cf12422a7d8..b7828a241981 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+@@ -243,6 +243,7 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
+ 		pm->pmf = &kfd_v9_pm_funcs;
+ 		break;
+ 	case CHIP_NAVI10:
++	case CHIP_NAVI14:
+ 		pm->pmf = &kfd_v10_pm_funcs;
+ 		break;
+ 	default:
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+index c618c5595c4c..e235e4074ce3 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+@@ -1395,6 +1395,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
+ 	case CHIP_RAVEN:
+ 	case CHIP_ARCTURUS:
+ 	case CHIP_NAVI10:
++	case CHIP_NAVI14:
+ 		dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
+ 			HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
+ 			HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3726-drm-amdkfd-enable-renoir-while-device-probes.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3726-drm-amdkfd-enable-renoir-while-device-probes.patch
new file mode 100644
index 00000000..ed8ce66e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3726-drm-amdkfd-enable-renoir-while-device-probes.patch
@@ -0,0 +1,28 @@
+From 40c85ebbfb60733d17e93acceb974dcdd600f65e Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Mon, 2 Sep 2019 22:35:37 +0800
+Subject: [PATCH 3726/4256] drm/amdkfd: enable renoir while device probes
+
+This patch is to add asic flag to enable device probe during kfd init.
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+index 9ad94eeda69f..9a3ab7fde205 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+@@ -93,6 +93,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
+ 	case CHIP_VEGA12:
+ 	case CHIP_VEGA20:
+ 	case CHIP_RAVEN:
++	case CHIP_RENOIR:
+ 		kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
+ 		break;
+ 	case CHIP_ARCTURUS:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3727-drm-amdkfd-add-renoir-kfd-device-info-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3727-drm-amdkfd-add-renoir-kfd-device-info-v2.patch
new file mode 100644
index 00000000..bf3f722f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3727-drm-amdkfd-add-renoir-kfd-device-info-v2.patch
@@ -0,0 +1,55 @@
+From f374ed2a3cc2adc1475a62532e625e127b340364 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Mon, 2 Sep 2019 23:06:58 +0800
+Subject: [PATCH 3727/4256] drm/amdkfd: add renoir kfd device info (v2)
+
+This patch inits renoir kfd device info, so we treat renoir as "dgpu"
+(bypass iommu v2). Will enable needs_iommu_device till renoir iommu is ready.
+
+v2: rebase and align the drm-next
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index 63dbe5fe20f0..3e3fb994bc86 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -351,6 +351,23 @@ static const struct kfd_device_info arcturus_device_info = {
+ 	.num_sdma_queues_per_engine = 8,
+ };
+ 
++static const struct kfd_device_info renoir_device_info = {
++	.asic_family = CHIP_RENOIR,
++	.max_pasid_bits = 16,
++	.max_no_of_hqd  = 24,
++	.doorbell_size  = 8,
++	.ih_ring_entry_size = 8 * sizeof(uint32_t),
++	.event_interrupt_class = &event_interrupt_class_v9,
++	.num_of_watch_points = 4,
++	.mqd_size_aligned = MQD_SIZE_ALIGNED,
++	.supports_cwsr = true,
++	.needs_iommu_device = false,
++	.needs_pci_atomics = false,
++	.num_sdma_engines = 1,
++	.num_xgmi_sdma_engines = 0,
++	.num_sdma_queues_per_engine = 2,
++};
++
+ static const struct kfd_device_info navi10_device_info = {
+ 	.asic_family = CHIP_NAVI10,
+ 	.asic_name = "navi10",
+@@ -404,6 +421,7 @@ static const struct kfd_device_info *kfd_supported_devices[][2] = {
+ 	[CHIP_VEGA10] = {&vega10_device_info, &vega10_vf_device_info},
+ 	[CHIP_VEGA12] = {&vega12_device_info, NULL},
+ 	[CHIP_VEGA20] = {&vega20_device_info, NULL},
++	[CHIP_RENOIR] = {&renoir_device_info, NULL},
+ 	[CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info},
+ 	[CHIP_NAVI10] = {&navi10_device_info, NULL},
+ 	[CHIP_NAVI14] = {&navi14_device_info, NULL},
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3728-drm-amdkfd-add-renoir-cache-info-for-CRAT-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3728-drm-amdkfd-add-renoir-cache-info-for-CRAT-v2.patch
new file mode 100644
index 00000000..c72e607d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3728-drm-amdkfd-add-renoir-cache-info-for-CRAT-v2.patch
@@ -0,0 +1,41 @@
+From 4a9167b03021294bdb3b8bbcc3221c6f2a033583 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Mon, 2 Sep 2019 22:59:01 +0800
+Subject: [PATCH 3728/4256] drm/amdkfd: add renoir cache info for CRAT (v2)
+
+Renoir's cache info should be the same with raven and carrizo's.
+
+v2: fix missed "break"
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+index a95e6bc2f7f9..d9e075d66065 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+@@ -138,6 +138,7 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
+ /* TODO - check & update Vega10 cache details */
+ #define vega10_cache_info carrizo_cache_info
+ #define raven_cache_info carrizo_cache_info
++#define renoir_cache_info carrizo_cache_info
+ /* TODO - check & update Navi10 cache details */
+ #define navi10_cache_info carrizo_cache_info
+ 
+@@ -670,6 +671,10 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
+ 		pcache_info = raven_cache_info;
+ 		num_of_cache_types = ARRAY_SIZE(raven_cache_info);
+ 		break;
++	case CHIP_RENOIR:
++		pcache_info = renoir_cache_info;
++		num_of_cache_types = ARRAY_SIZE(renoir_cache_info);
++		break;
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+ 		pcache_info = navi10_cache_info;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3729-drm-amdkfd-add-renoir-type-for-the-workaround-of-iom.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3729-drm-amdkfd-add-renoir-type-for-the-workaround-of-iom.patch
new file mode 100644
index 00000000..cfbc286a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3729-drm-amdkfd-add-renoir-type-for-the-workaround-of-iom.patch
@@ -0,0 +1,33 @@
+From f2788e9011ed1338fcc8ec00c2d0b0f9a028716c Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Mon, 2 Sep 2019 23:13:26 +0800
+Subject: [PATCH 3729/4256] drm/amdkfd: add renoir type for the workaround of
+ iommu v2 (v2)
+
+Renoir is the same with Raven, will enable iommu event in future.
+
+v2: fix the checking (Thong)
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_events.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+index b5a7b6bb4a60..38a99ba91a88 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+@@ -937,7 +937,8 @@ void kfd_signal_iommu_event(struct kfd_dev *dev, unsigned int pasid,
+ 	 * before IOMMU is able to finish processing all the excessive PPRs
+ 	 * triggered due to HW flaws.
+ 	 */
+-	if (dev->device_info->asic_family != CHIP_RAVEN) {
++	if (dev->device_info->asic_family != CHIP_RAVEN &&
++	    dev->device_info->asic_family != CHIP_RENOIR) {
+ 		mutex_lock(&p->event_mutex);
+ 
+ 		/* Lookup events by type and signal them */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3730-drm-amdgpu-disable-gfxoff-while-use-no-H-W-schedulin.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3730-drm-amdgpu-disable-gfxoff-while-use-no-H-W-schedulin.patch
new file mode 100644
index 00000000..83be5e79
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3730-drm-amdgpu-disable-gfxoff-while-use-no-H-W-schedulin.patch
@@ -0,0 +1,45 @@
+From 7ac454802299ffd3671cd488e5868f8cd21d5652 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Mon, 2 Sep 2019 23:34:32 +0800
+Subject: [PATCH 3730/4256] drm/amdgpu: disable gfxoff while use no H/W
+ scheduling policy
+
+While gfxoff is enabled, the mmVM_XXX registers will be 0xfffffff while the GFX
+is in "off" state. KFD queue creattion doesn't use ring based method, so it will
+trigger a VM fault.
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index b2999b81f923..55e3d3e2e69c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -173,6 +173,7 @@ extern int amdgpu_discovery;
+ extern int amdgpu_mes;
+ extern int amdgpu_noretry;
+ extern int amdgpu_force_asic_type;
++extern int sched_policy;
+ 
+ #ifdef CONFIG_DRM_AMDGPU_SI
+ extern int amdgpu_si_support;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 2d65e8eb687d..be0a06014037 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1622,7 +1622,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
+ 	}
+ 
+ 	adev->pm.pp_feature = amdgpu_pp_feature_mask;
+-	if (amdgpu_sriov_vf(adev))
++	if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
+ 		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ 
+ 	for (i = 0; i < adev->num_ip_blocks; i++) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3731-drm-amdkfd-enable-kfd-device-queue-manager-v9-for-re.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3731-drm-amdkfd-enable-kfd-device-queue-manager-v9-for-re.patch
new file mode 100644
index 00000000..425bf110
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3731-drm-amdkfd-enable-kfd-device-queue-manager-v9-for-re.patch
@@ -0,0 +1,29 @@
+From 371be0c0898f4763997d2977b0226769fbde9eea Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Mon, 2 Sep 2019 23:10:52 +0800
+Subject: [PATCH 3731/4256] drm/amdkfd: enable kfd device queue manager v9 for
+ renoir
+
+Renoir is GFX9, so enable v9 devcie queue manager.
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 35dc1d1e0413..83cddab4d482 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -1879,6 +1879,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
+ 	case CHIP_VEGA12:
+ 	case CHIP_VEGA20:
+ 	case CHIP_RAVEN:
++	case CHIP_RENOIR:
+ 	case CHIP_ARCTURUS:
+ 		device_queue_manager_init_v9(&dqm->asic_ops);
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3732-drm-amdkfd-init-kfd-apertures-v9-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3732-drm-amdkfd-init-kfd-apertures-v9-for-renoir.patch
new file mode 100644
index 00000000..cf4b79f2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3732-drm-amdkfd-init-kfd-apertures-v9-for-renoir.patch
@@ -0,0 +1,28 @@
+From 46ce1fbc90d97dbcb64390677fabc5488a134b4d Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Mon, 2 Sep 2019 23:15:46 +0800
+Subject: [PATCH 3732/4256] drm/amdkfd: init kfd apertures v9 for renoir
+
+Renoir is GMC v9, so init v9 kfd apertures.
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+index ed4efab0a190..ae950633228c 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+@@ -410,6 +410,7 @@ int kfd_init_apertures(struct kfd_process *process)
+ 			case CHIP_VEGA12:
+ 			case CHIP_VEGA20:
+ 			case CHIP_RAVEN:
++			case CHIP_RENOIR:
+ 			case CHIP_ARCTURUS:
+ 			case CHIP_NAVI10:
+ 			case CHIP_NAVI14:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3733-drm-amdkfd-init-kernel-queue-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3733-drm-amdkfd-init-kernel-queue-for-renoir.patch
new file mode 100644
index 00000000..b15078c8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3733-drm-amdkfd-init-kernel-queue-for-renoir.patch
@@ -0,0 +1,28 @@
+From 41a00210706c63463d5d7fd8597f8a3c9c012991 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Mon, 2 Sep 2019 23:19:38 +0800
+Subject: [PATCH 3733/4256] drm/amdkfd: init kernel queue for renoir
+
+Renoir is GFX v9, so init v9 kernel queue.
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+index 1097e047b4bb..9ec62435326e 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+@@ -364,6 +364,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
+ 	case CHIP_VEGA12:
+ 	case CHIP_VEGA20:
+ 	case CHIP_RAVEN:
++	case CHIP_RENOIR:
+ 	case CHIP_ARCTURUS:
+ 		kernel_queue_init_v9(&kq->ops_asic_specific);
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3734-drm-amdkfd-add-renoir-kfd-topology.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3734-drm-amdkfd-add-renoir-kfd-topology.patch
new file mode 100644
index 00000000..51bcd573
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3734-drm-amdkfd-add-renoir-kfd-topology.patch
@@ -0,0 +1,28 @@
+From 260833e08d3c45823d446e9adb90360e33aec1e3 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Mon, 2 Sep 2019 23:25:29 +0800
+Subject: [PATCH 3734/4256] drm/amdkfd: add renoir kfd topology
+
+This patch adds renoir kfd topology which is the same with Raven.
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+index e235e4074ce3..ea6dc5d73c8c 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+@@ -1393,6 +1393,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
+ 	case CHIP_VEGA12:
+ 	case CHIP_VEGA20:
+ 	case CHIP_RAVEN:
++	case CHIP_RENOIR:
+ 	case CHIP_ARCTURUS:
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3735-drm-amdkfd-add-package-manager-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3735-drm-amdkfd-add-package-manager-for-renoir.patch
new file mode 100644
index 00000000..ae4822ad
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3735-drm-amdkfd-add-package-manager-for-renoir.patch
@@ -0,0 +1,28 @@
+From 7193af74ae65bad423368f225f91ef91ffc7c554 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Mon, 2 Sep 2019 23:24:29 +0800
+Subject: [PATCH 3735/4256] drm/amdkfd: add package manager for renoir
+
+Renoir use GFX v9, so adds v9 package manager.
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+index b7828a241981..08d3b38117b5 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+@@ -239,6 +239,7 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
+ 	case CHIP_VEGA12:
+ 	case CHIP_VEGA20:
+ 	case CHIP_RAVEN:
++	case CHIP_RENOIR:
+ 	case CHIP_ARCTURUS:
+ 		pm->pmf = &kfd_v9_pm_funcs;
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3736-dmr-amdgpu-Avoid-HW-GPU-reset-for-RAS.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3736-dmr-amdgpu-Avoid-HW-GPU-reset-for-RAS.patch
new file mode 100644
index 00000000..476de3c3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3736-dmr-amdgpu-Avoid-HW-GPU-reset-for-RAS.patch
@@ -0,0 +1,512 @@
+From 61d5f95e1eca078269c2b3dc74e18b57ad13a064 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Thu, 22 Aug 2019 14:40:00 -0400
+Subject: [PATCH 3736/4256] dmr/amdgpu: Avoid HW GPU reset for RAS.
+
+Problem:
+Under certain conditions, when some IP bocks take a RAS error,
+we can get into a situation where a GPU reset is not possible
+due to issues in RAS in SMU/PSP.
+
+Temporary fix until proper solution in PSP/SMU is ready:
+When uncorrectable error happens the DF will unconditionally
+broadcast error event packets to all its clients/slave upon
+receiving fatal error event and freeze all its outbound queues,
+err_event_athub interrupt  will be triggered.
+In such case and we use this interrupt
+to issue GPU reset. THe GPU reset code is modified for such case to avoid HW
+reset, only stops schedulers, deatches all in progress and not yet scheduled
+job's fences, set error code on them and signals.
+Also reject any new incoming job submissions from user space.
+All this is done to notify the applications of the problem.
+
+v2:
+Extract amdgpu_amdkfd_pre/post_reset from amdgpu_device_lock/unlock_adev
+Move amdgpu_job_stop_all_jobs_on_sched to amdgpu_job.c
+Remove print param from amdgpu_ras_query_error_count
+
+v3:
+Update based on prevoius bug fixing patch to properly call amdgpu_amdkfd_pre_reset
+for other XGMI hive memebers.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c     |  4 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 38 ++++++++++++++++------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c    |  5 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_job.c    | 38 ++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_job.h    |  3 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c    |  6 ++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c    | 22 +++++++++++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h    | 10 ++++++
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c      | 10 +++---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c      | 24 +++++++-------
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c     |  5 +++
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c     | 32 +++++++++---------
+ 12 files changed, 155 insertions(+), 42 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+index 55282bfcaa45..901ce33cc481 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+@@ -34,6 +34,7 @@
+ #include "amdgpu_gmc.h"
+ #include "amdgpu_gem.h"
+ #include "amdgpu_display.h"
++#include "amdgpu_ras.h"
+ 
+ static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
+ 				      struct drm_amdgpu_cs_chunk_fence *data,
+@@ -1278,6 +1279,9 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
+ 	bool reserved_buffers = false;
+ 	int i, r;
+ 
++	if (amdgpu_ras_intr_triggered())
++		return -EHWPOISON;
++
+ 	if (!adev->accel_working)
+ 		return -EBUSY;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index be0a06014037..e30f7ba53aab 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3725,25 +3725,18 @@ static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, bool trylock)
+ 		adev->mp1_state = PP_MP1_STATE_NONE;
+ 		break;
+ 	}
+-	/* Block kfd: SRIOV would do it separately */
+-	if (!amdgpu_sriov_vf(adev))
+-                amdgpu_amdkfd_pre_reset(adev);
+ 
+ 	return true;
+ }
+ 
+ static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
+ {
+-	/*unlock kfd: SRIOV would do it separately */
+-	if (!amdgpu_sriov_vf(adev))
+-                amdgpu_amdkfd_post_reset(adev);
+ 	amdgpu_vf_error_trans_all(adev);
+ 	adev->mp1_state = PP_MP1_STATE_NONE;
+ 	adev->in_gpu_reset = 0;
+ 	mutex_unlock(&adev->lock_reset);
+ }
+ 
+-
+ /**
+  * amdgpu_device_gpu_recover - reset the asic and recover scheduler
+  *
+@@ -3763,11 +3756,12 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 	struct amdgpu_hive_info *hive = NULL;
+ 	struct amdgpu_device *tmp_adev = NULL;
+ 	int i, r = 0;
++	bool in_ras_intr = amdgpu_ras_intr_triggered();
+ 
+ 	need_full_reset = job_signaled = false;
+ 	INIT_LIST_HEAD(&device_list);
+ 
+-	dev_info(adev->dev, "GPU reset begin!\n");
++	dev_info(adev->dev, "GPU %s begin!\n", in_ras_intr ? "jobs stop":"reset");
+ 
+ 	cancel_delayed_work_sync(&adev->delayed_init_work);
+ 
+@@ -3794,9 +3788,16 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 		return 0;
+ 	}
+ 
++	/* Block kfd: SRIOV would do it separately */
++	if (!amdgpu_sriov_vf(adev))
++                amdgpu_amdkfd_pre_reset(adev);
++
+ 	/* Build list of devices to reset */
+ 	if  (adev->gmc.xgmi.num_physical_nodes > 1) {
+ 		if (!hive) {
++			/*unlock kfd: SRIOV would do it separately */
++			if (!amdgpu_sriov_vf(adev))
++		                amdgpu_amdkfd_post_reset(adev);
+ 			amdgpu_device_unlock_adev(adev);
+ 			return -ENODEV;
+ 		}
+@@ -3814,8 +3815,12 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 
+ 	/* block all schedulers and reset given job's ring */
+ 	list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
+-		if (tmp_adev != adev)
++		if (tmp_adev != adev) {
+ 			amdgpu_device_lock_adev(tmp_adev, false);
++			if (!amdgpu_sriov_vf(tmp_adev))
++			                amdgpu_amdkfd_pre_reset(tmp_adev);
++		}
++
+ 		/*
+ 		 * Mark these ASICs to be reseted as untracked first
+ 		 * And add them back after reset completed
+@@ -3823,7 +3828,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 		amdgpu_unregister_gpu_instance(tmp_adev);
+ 
+ 		/* disable ras on ALL IPs */
+-		if (amdgpu_device_ip_need_full_reset(tmp_adev))
++		if (!in_ras_intr && amdgpu_device_ip_need_full_reset(tmp_adev))
+ 			amdgpu_ras_suspend(tmp_adev);
+ 
+ 		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
+@@ -3833,10 +3838,16 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 				continue;
+ 
+ 			drm_sched_stop(&ring->sched, job ? &job->base : NULL);
++
++			if (in_ras_intr)
++				amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
+ 		}
+ 	}
+ 
+ 
++	if (in_ras_intr)
++		goto skip_sched_resume;
++
+ 	/*
+ 	 * Must check guilty signal here since after this point all old
+ 	 * HW fences are force signaled.
+@@ -3895,6 +3906,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 
+ 	/* Post ASIC reset for all devs .*/
+ 	list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
++
+ 		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
+ 			struct amdgpu_ring *ring = tmp_adev->rings[i];
+ 
+@@ -3921,7 +3933,13 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 		} else {
+ 			dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
+ 		}
++	}
+ 
++skip_sched_resume:
++	list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
++		/*unlock kfd: SRIOV would do it separately */
++		if (!in_ras_intr && !amdgpu_sriov_vf(tmp_adev))
++	                amdgpu_amdkfd_post_reset(tmp_adev);
+ 		amdgpu_device_unlock_adev(tmp_adev);
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 2de8db5e864c..3aa7c136d2c3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -40,6 +40,8 @@
+ 
+ #include "amdgpu_amdkfd.h"
+ 
++#include "amdgpu_ras.h"
++
+ /*
+  * KMS wrapper.
+  * - 3.0.0 - initial driver
+@@ -1144,6 +1146,9 @@ amdgpu_pci_shutdown(struct pci_dev *pdev)
+ 	struct drm_device *dev = pci_get_drvdata(pdev);
+ 	struct amdgpu_device *adev = dev->dev_private;
+ 
++	if (amdgpu_ras_intr_triggered())
++		return;
++
+ 	/* if we are running in a VM, make sure the device
+ 	 * torn down properly on reboot/shutdown.
+ 	 * unfortunately we can't detect certain
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+index 7ab1241bd9e5..c043d8f6bb8b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+@@ -246,6 +246,44 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
+ 	return fence;
+ }
+ 
++#define to_drm_sched_job(sched_job)		\
++		container_of((sched_job), struct drm_sched_job, queue_node)
++
++void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched)
++{
++	struct drm_sched_job *s_job;
++	struct drm_sched_entity *s_entity = NULL;
++	int i;
++
++	/* Signal all jobs not yet scheduled */
++	for (i = DRM_SCHED_PRIORITY_MAX - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) {
++		struct drm_sched_rq *rq = &sched->sched_rq[i];
++
++		if (!rq)
++			continue;
++
++		spin_lock(&rq->lock);
++		list_for_each_entry(s_entity, &rq->entities, list) {
++			while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) {
++				struct drm_sched_fence *s_fence = s_job->s_fence;
++
++				dma_fence_signal(&s_fence->scheduled);
++				dma_fence_set_error(&s_fence->finished, -EHWPOISON);
++				dma_fence_signal(&s_fence->finished);
++			}
++		}
++		spin_unlock(&rq->lock);
++	}
++
++	/* Signal all jobs already scheduled to HW */
++	list_for_each_entry(s_job, &sched->ring_mirror_list, node) {
++		struct drm_sched_fence *s_fence = s_job->s_fence;
++
++		dma_fence_set_error(&s_fence->finished, -EHWPOISON);
++		dma_fence_signal(&s_fence->finished);
++	}
++}
++
+ const struct drm_sched_backend_ops amdgpu_sched_ops = {
+ 	.dependency = amdgpu_job_dependency,
+ 	.run_job = amdgpu_job_run,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+index 51e62504c279..dc7ee9358dcd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+@@ -76,4 +76,7 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
+ 		      void *owner, struct dma_fence **f);
+ int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
+ 			     struct dma_fence **fence);
++
++void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 751c4c8e1cee..9d4e71ee8791 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -1030,6 +1030,12 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
+ 	/* Ensure IB tests are run on ring */
+ 	flush_delayed_work(&adev->delayed_init_work);
+ 
++
++	if (amdgpu_ras_intr_triggered()) {
++		DRM_ERROR("RAS Intr triggered, device disabled!!");
++		return -EHWPOISON;
++	}
++
+ 	file_priv->driver_priv = NULL;
+ 
+ 	r = pm_runtime_get_sync(dev->dev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 2ca3997d4b3a..01a66559f04e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -24,6 +24,8 @@
+ #include <linux/debugfs.h>
+ #include <linux/list.h>
+ #include <linux/module.h>
++#include <linux/reboot.h>
++#include <linux/syscalls.h>
+ #include "amdgpu.h"
+ #include "amdgpu_ras.h"
+ #include "amdgpu_atomfirmware.h"
+@@ -64,6 +66,9 @@ const char *ras_block_string[] = {
+ /* inject address is 52 bits */
+ #define	RAS_UMC_INJECT_ADDR_LIMIT	(0x1ULL << 52)
+ 
++
++atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
++
+ static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev,
+ 		uint64_t offset, uint64_t size,
+ 		struct amdgpu_bo **bo_ptr);
+@@ -188,6 +193,10 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
+ 
+ 	return 0;
+ }
++
++static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
++		struct ras_common_if *head);
++
+ /**
+  * DOC: AMDGPU RAS debugfs control interface
+  *
+@@ -627,12 +636,14 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev,
+ 	info->ue_count = obj->err_data.ue_count;
+ 	info->ce_count = obj->err_data.ce_count;
+ 
+-	if (err_data.ce_count)
++	if (err_data.ce_count) {
+ 		dev_info(adev->dev, "%ld correctable errors detected in %s block\n",
+ 			 obj->err_data.ce_count, ras_block_str(info->head.block));
+-	if (err_data.ue_count)
++	}
++	if (err_data.ue_count) {
+ 		dev_info(adev->dev, "%ld uncorrectable errors detected in %s block\n",
+ 			 obj->err_data.ue_count, ras_block_str(info->head.block));
++	}
+ 
+ 	return 0;
+ }
+@@ -1729,3 +1740,10 @@ int amdgpu_ras_fini(struct amdgpu_device *adev)
+ 
+ 	return 0;
+ }
++
++void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
++{
++	if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
++		DRM_WARN("RAS event of type ERREVENT_ATHUB_INTERRUPT detected! Stopping all GPU jobs.\n");
++	}
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index 66b71525446e..6fda96b29f1f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -606,4 +606,14 @@ int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
+ 
+ int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
+ 		struct ras_dispatch_if *info);
++
++extern atomic_t amdgpu_ras_in_intr;
++
++static inline bool amdgpu_ras_intr_triggered(void)
++{
++	return !!atomic_read(&amdgpu_ras_in_intr);
++}
++
++void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 384fc226ecb5..918eaeedb5b9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -5683,10 +5683,12 @@ static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+ 		struct amdgpu_iv_entry *entry)
+ {
+ 	/* TODO ue will trigger an interrupt. */
+-	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
+-	if (adev->gfx.funcs->query_ras_error_count)
+-		adev->gfx.funcs->query_ras_error_count(adev, err_data);
+-	amdgpu_ras_reset_gpu(adev, 0);
++	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
++		kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
++		if (adev->gfx.funcs->query_ras_error_count)
++			adev->gfx.funcs->query_ras_error_count(adev, err_data);
++		amdgpu_ras_reset_gpu(adev, 0);
++	}
+ 	return AMDGPU_RAS_SUCCESS;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 4a19647edfea..617311db7d2e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -243,18 +243,20 @@ static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+ 		struct ras_err_data *err_data,
+ 		struct amdgpu_iv_entry *entry)
+ {
+-	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
+-	if (adev->umc.funcs->query_ras_error_count)
+-		adev->umc.funcs->query_ras_error_count(adev, err_data);
+-	/* umc query_ras_error_address is also responsible for clearing
+-	 * error status
+-	 */
+-	if (adev->umc.funcs->query_ras_error_address)
+-		adev->umc.funcs->query_ras_error_address(adev, err_data);
++	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
++		kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
++		if (adev->umc.funcs->query_ras_error_count)
++			adev->umc.funcs->query_ras_error_count(adev, err_data);
++		/* umc query_ras_error_address is also responsible for clearing
++		 * error status
++		 */
++		if (adev->umc.funcs->query_ras_error_address)
++			adev->umc.funcs->query_ras_error_address(adev, err_data);
+ 
+-	/* only uncorrectable error needs gpu reset */
+-	if (err_data->ue_count)
+-		amdgpu_ras_reset_gpu(adev, 0);
++		/* only uncorrectable error needs gpu reset */
++		if (err_data->ue_count)
++			amdgpu_ras_reset_gpu(adev, 0);
++	}
+ 
+ 	return AMDGPU_RAS_SUCCESS;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index 5e784bbd2d7f..27eeab143ad7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -30,6 +30,7 @@
+ #include "nbio/nbio_7_4_0_smn.h"
+ #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
+ #include <uapi/linux/kfd_ioctl.h>
++#include "amdgpu_ras.h"
+ 
+ #define smnNBIF_MGCG_CTRL_LCLK	0x1013a21c
+ 
+@@ -329,6 +330,8 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device
+ 						BIF_DOORBELL_INT_CNTL,
+ 						RAS_CNTLR_INTERRUPT_CLEAR, 1);
+ 		WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
++
++		amdgpu_ras_global_ras_isr(adev);
+ 	}
+ }
+ 
+@@ -344,6 +347,8 @@ static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_d
+ 						BIF_DOORBELL_INT_CNTL,
+ 						RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);
+ 		WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
++
++		amdgpu_ras_global_ras_isr(adev);
+ 	}
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 72840582f716..6424723e1af0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1978,24 +1978,26 @@ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
+ 	uint32_t err_source;
+ 	int instance;
+ 
+-	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
+-	if (instance < 0)
+-		return 0;
++	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
++		instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
++		if (instance < 0)
++			return 0;
+ 
+-	switch (entry->src_id) {
+-	case SDMA0_4_0__SRCID__SDMA_SRAM_ECC:
+-		err_source = 0;
+-		break;
+-	case SDMA0_4_0__SRCID__SDMA_ECC:
+-		err_source = 1;
+-		break;
+-	default:
+-		return 0;
+-	}
++		switch (entry->src_id) {
++		case SDMA0_4_0__SRCID__SDMA_SRAM_ECC:
++			err_source = 0;
++			break;
++		case SDMA0_4_0__SRCID__SDMA_ECC:
++			err_source = 1;
++			break;
++		default:
++			return 0;
++		}
+ 
+-	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
++		kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
+ 
+-	amdgpu_ras_reset_gpu(adev, 0);
++		amdgpu_ras_reset_gpu(adev, 0);
++	}
+ 
+ 	return AMDGPU_RAS_SUCCESS;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3737-drm-amdgpu-check-if-nbio-ras_if-exist.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3737-drm-amdgpu-check-if-nbio-ras_if-exist.patch
new file mode 100644
index 00000000..6e359599
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3737-drm-amdgpu-check-if-nbio-ras_if-exist.patch
@@ -0,0 +1,141 @@
+From 31873c3b437931c67ffc98c7246c15bf213a46b1 Mon Sep 17 00:00:00 2001
+From: Philip Yang <Philip.Yang@amd.com>
+Date: Fri, 6 Sep 2019 13:20:40 -0400
+Subject: [PATCH 3737/4256] drm/amdgpu: check if nbio->ras_if exist
+
+To avoid NULL function pointer access. This happens on VG10, reboot
+command hangs and have to power off/on to reboot the machine. This is
+serial console log:
+
+[  OK  ] Reached target Unmount All Filesystems.
+[  OK  ] Reached target Final Step.
+         Starting Reboot...
+[  305.696271] systemd-shutdown[1]: Syncing filesystems and block
+devices.
+[  306.947328] systemd-shutdown[1]: Sending SIGTERM to remaining
+processes...
+[  306.963920] systemd-journald[1722]: Received SIGTERM from PID 1
+(systemd-shutdow).
+[  307.322717] systemd-shutdown[1]: Sending SIGKILL to remaining
+processes...
+[  307.336472] systemd-shutdown[1]: Unmounting file systems.
+[  307.454202] EXT4-fs (sda2): re-mounted. Opts: errors=remount-ro
+[  307.480523] systemd-shutdown[1]: All filesystems unmounted.
+[  307.486537] systemd-shutdown[1]: Deactivating swaps.
+[  307.491962] systemd-shutdown[1]: All swaps deactivated.
+[  307.497624] systemd-shutdown[1]: Detaching loop devices.
+[  307.504418] systemd-shutdown[1]: All loop devices detached.
+[  307.510418] systemd-shutdown[1]: Detaching DM devices.
+[  307.565907] sd 2:0:0:0: [sda] Synchronizing SCSI cache
+[  307.731313] BUG: kernel NULL pointer dereference, address:
+0000000000000000
+[  307.738802] #PF: supervisor read access in kernel mode
+[  307.744326] #PF: error_code(0x0000) - not-present page
+[  307.749850] PGD 0 P4D 0
+[  307.752568] Oops: 0000 [#1] SMP PTI
+[  307.756314] CPU: 3 PID: 1 Comm: systemd-shutdow Not tainted
+5.2.0-rc1-kfd-yangp #453
+[  307.764644] Hardware name: ASUS All Series/Z97-PRO(Wi-Fi ac)/USB 3.1,
+BIOS 9001 03/07/2016
+[  307.773580] RIP: 0010:soc15_common_hw_fini+0x33/0xc0 [amdgpu]
+[  307.779760] Code: 89 fb e8 60 f5 ff ff f6 83 50 df 01 00 04 75 3d 48
+8b b3 90 7d 00 00 48 c7 c7 17 b8 530
+[  307.799967] RSP: 0018:ffffac9483153d40 EFLAGS: 00010286
+[  307.805585] RAX: 0000000000000000 RBX: ffff9eb299da0000 RCX:
+0000000000000006
+[  307.813261] RDX: 0000000000000000 RSI: ffff9eb29e3508a0 RDI:
+ffff9eb29e350000
+[  307.820935] RBP: ffff9eb299da0000 R08: 0000000000000000 R09:
+0000000000000000
+[  307.828609] R10: 0000000000000000 R11: 0000000000000000 R12:
+ffff9eb299dbd1f8
+[  307.836284] R13: ffffffffc04f8368 R14: ffff9eb29cebd130 R15:
+0000000000000000
+[  307.843959] FS:  00007f06721c9940(0000) GS:ffff9eb2a18c0000(0000)
+knlGS:0000000000000000
+[  307.852663] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+[  307.858842] CR2: 0000000000000000 CR3: 000000081d798005 CR4:
+00000000001606e0
+[  307.866516] Call Trace:
+[  307.869169]  amdgpu_device_ip_suspend_phase2+0x80/0x110 [amdgpu]
+[  307.875654]  ? amdgpu_device_ip_suspend_phase1+0x4d/0xd0 [amdgpu]
+[  307.882230]  amdgpu_device_ip_suspend+0x2e/0x60 [amdgpu]
+[  307.887966]  amdgpu_pci_shutdown+0x2f/0x40 [amdgpu]
+[  307.893211]  pci_device_shutdown+0x31/0x60
+[  307.897613]  device_shutdown+0x14c/0x1f0
+[  307.901829]  kernel_restart+0xe/0x50
+[  307.905669]  __do_sys_reboot+0x1df/0x210
+[  307.909884]  ? task_work_run+0x73/0xb0
+[  307.913914]  ? trace_hardirqs_off_thunk+0x1a/0x1c
+[  307.918970]  do_syscall_64+0x4a/0x1c0
+[  307.922904]  entry_SYSCALL_64_after_hwframe+0x49/0xbe
+[  307.928336] RIP: 0033:0x7f0671cf8373
+[  307.932176] Code: 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00
+00 0f 1f 44 00 00 89 fa be 69 19 128
+[  307.952384] RSP: 002b:00007ffdd1723d68 EFLAGS: 00000202 ORIG_RAX:
+00000000000000a9
+[  307.960527] RAX: ffffffffffffffda RBX: 0000000001234567 RCX:
+00007f0671cf8373
+[  307.968201] RDX: 0000000001234567 RSI: 0000000028121969 RDI:
+00000000fee1dead
+[  307.975875] RBP: 00007ffdd1723dd0 R08: 0000000000000000 R09:
+0000000000000000
+[  307.983550] R10: 0000000000000002 R11: 0000000000000202 R12:
+00007ffdd1723dd8
+[  307.991224] R13: 0000000000000000 R14: 0000001b00000004 R15:
+00007ffdd17240c8
+[  307.998901] Modules linked in: xt_MASQUERADE nfnetlink iptable_nat
+xt_addrtype xt_conntrack nf_nat nf_cos
+[  308.026505] CR2: 0000000000000000
+[  308.039998] RIP: 0010:soc15_common_hw_fini+0x33/0xc0 [amdgpu]
+[  308.046180] Code: 89 fb e8 60 f5 ff ff f6 83 50 df 01 00 04 75 3d 48
+8b b3 90 7d 00 00 48 c7 c7 17 b8 530
+[  308.066392] RSP: 0018:ffffac9483153d40 EFLAGS: 00010286
+[  308.072013] RAX: 0000000000000000 RBX: ffff9eb299da0000 RCX:
+0000000000000006
+[  308.079689] RDX: 0000000000000000 RSI: ffff9eb29e3508a0 RDI:
+ffff9eb29e350000
+[  308.087366] RBP: ffff9eb299da0000 R08: 0000000000000000 R09:
+0000000000000000
+[  308.095042] R10: 0000000000000000 R11: 0000000000000000 R12:
+ffff9eb299dbd1f8
+[  308.102717] R13: ffffffffc04f8368 R14: ffff9eb29cebd130 R15:
+0000000000000000
+[  308.110394] FS:  00007f06721c9940(0000) GS:ffff9eb2a18c0000(0000)
+knlGS:0000000000000000
+[  308.119099] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+[  308.125280] CR2: 0000000000000000 CR3: 000000081d798005 CR4:
+00000000001606e0
+[  308.135304] printk: systemd-shutdow: 3 output lines suppressed due to
+ratelimiting
+[  308.143518] Kernel panic - not syncing: Attempted to kill init!
+exitcode=0x00000009
+[  308.151798] Kernel Offset: 0x15000000 from 0xffffffff81000000
+(relocation range: 0xffffffff80000000-0xff)
+[  308.171775] ---[ end Kernel panic - not syncing: Attempted to kill
+init! exitcode=0x00000009 ]---
+
+Change-Id: If694f75e893f95c44d594877f552380a77c03ec4
+Signed-off-by: Philip Yang <Philip.Yang@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index cb22970c0853..7c7e9f550c02 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1302,7 +1302,8 @@ static int soc15_common_hw_fini(void *handle)
+ 	if (amdgpu_sriov_vf(adev))
+ 		xgpu_ai_mailbox_put_irq(adev);
+ 
+-	if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
++	if (adev->nbio.ras_if &&
++	    amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
+ 		if (adev->nbio.funcs->init_ras_controller_interrupt)
+ 			amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
+ 		if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3738-dmr-amdgpu-Add-system-auto-reboot-to-RAS.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3738-dmr-amdgpu-Add-system-auto-reboot-to-RAS.patch
new file mode 100644
index 00000000..6ad7b6ae
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3738-dmr-amdgpu-Add-system-auto-reboot-to-RAS.patch
@@ -0,0 +1,167 @@
+From 013f63d334471e85b469aad0bba8ed3c2d256cd0 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Thu, 22 Aug 2019 15:01:37 -0400
+Subject: [PATCH 3738/4256] dmr/amdgpu: Add system auto reboot to RAS.
+
+In case of RAS error allow user configure auto system
+reboot through ras_ctrl.
+This is also part of the temproray work around for the RAS
+hang problem.
+
+v4: Use latest kernel API for disk sync.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 ++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c    |  9 ++++++++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h    |  2 +-
+ include/linux/suspend.h                    |  3 +++
+ include/linux/syscalls.h                   |  2 +-
+ kernel/power/main.c                        | 11 ++++++++++-
+ 6 files changed, 37 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index e30f7ba53aab..b29b26098b8f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -64,6 +64,8 @@
+ #include "amdgpu_ras.h"
+ #include "amdgpu_pmu.h"
+ 
++#include <linux/suspend.h>
++
+ MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
+ MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
+ MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
+@@ -3758,6 +3760,18 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 	int i, r = 0;
+ 	bool in_ras_intr = amdgpu_ras_intr_triggered();
+ 
++	/*
++	 * Flush RAM to disk so that after reboot
++	 * the user can read log and see why the system rebooted.
++	 */
++	if (in_ras_intr && amdgpu_ras_get_context(adev)->reboot) {
++
++		DRM_WARN("Emergency reboot.");
++
++		ksys_sync_helper();
++		emergency_restart();
++	}
++
+ 	need_full_reset = job_signaled = false;
+ 	INIT_LIST_HEAD(&device_list);
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 01a66559f04e..5c2276bb8325 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -154,6 +154,8 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
+ 		op = 1;
+ 	else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
+ 		op = 2;
++	else if (sscanf(str, "reboot %32s", block_name) == 1)
++		op = 3;
+ 	else if (str[0] && str[1] && str[2] && str[3])
+ 		/* ascii string, but commands are not matched. */
+ 		return -EINVAL;
+@@ -287,6 +289,9 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *
+ 		/* data.inject.address is offset instead of absolute gpu address */
+ 		ret = amdgpu_ras_error_inject(adev, &data.inject);
+ 		break;
++	case 3:
++		amdgpu_ras_get_context(adev)->reboot = true;
++		break;
+ 	default:
+ 		ret = -EINVAL;
+ 		break;
+@@ -1744,6 +1749,8 @@ int amdgpu_ras_fini(struct amdgpu_device *adev)
+ void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
+ {
+ 	if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
+-		DRM_WARN("RAS event of type ERREVENT_ATHUB_INTERRUPT detected! Stopping all GPU jobs.\n");
++		DRM_WARN("RAS event of type ERREVENT_ATHUB_INTERRUPT detected!\n");
++
++		amdgpu_ras_reset_gpu(adev, false);
+ 	}
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index 6fda96b29f1f..f487038ba331 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -334,7 +334,7 @@ struct amdgpu_ras {
+ 	struct mutex recovery_lock;
+ 
+ 	uint32_t flags;
+-
++	bool reboot;
+ 	struct amdgpu_ras_eeprom_control eeprom_control;
+ };
+ 
+diff --git a/include/linux/suspend.h b/include/linux/suspend.h
+index 3f529ad9a9d2..6b3ea9ea6a9e 100644
+--- a/include/linux/suspend.h
++++ b/include/linux/suspend.h
+@@ -425,6 +425,7 @@ void restore_processor_state(void);
+ /* kernel/power/main.c */
+ extern int register_pm_notifier(struct notifier_block *nb);
+ extern int unregister_pm_notifier(struct notifier_block *nb);
++extern void ksys_sync_helper(void);
+ 
+ #define pm_notifier(fn, pri) {				\
+ 	static struct notifier_block fn##_nb =			\
+@@ -462,6 +463,8 @@ static inline int unregister_pm_notifier(struct notifier_block *nb)
+ 	return 0;
+ }
+ 
++static inline void ksys_sync_helper(void) {}
++
+ #define pm_notifier(fn, pri)	do { (void)(fn); } while (0)
+ 
+ static inline bool pm_wakeup_pending(void) { return false; }
+diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h
+index 2ff814c92f7f..9dc129a92b31 100644
+--- a/include/linux/syscalls.h
++++ b/include/linux/syscalls.h
+@@ -906,7 +906,7 @@ asmlinkage long sys_statx(int dfd, const char __user *path, unsigned flags,
+ 			  unsigned mask, struct statx __user *buffer);
+ asmlinkage long sys_rseq(struct rseq __user *rseq, uint32_t rseq_len,
+ 			 int flags, uint32_t sig);
+-
++void ksys_sync(void);
+ /*
+  * Architecture-specific system calls
+  */
+diff --git a/kernel/power/main.c b/kernel/power/main.c
+index 35b50823d83b..1f5b1b262ff7 100644
+--- a/kernel/power/main.c
++++ b/kernel/power/main.c
+@@ -16,7 +16,7 @@
+ #include <linux/debugfs.h>
+ #include <linux/seq_file.h>
+ #include <linux/suspend.h>
+-
++#include <linux/syscalls.h>
+ #include "power.h"
+ 
+ #ifdef CONFIG_PM_SLEEP
+@@ -49,6 +49,15 @@ void unlock_system_sleep(void)
+ 	current->flags &= ~PF_FREEZER_SKIP;
+ 	mutex_unlock(&system_transition_mutex);
+ }
++
++void ksys_sync_helper(void)
++{
++        pr_info("Syncing filesystems ... ");
++        ksys_sync();
++        pr_cont("done.\n");
++}
++EXPORT_SYMBOL_GPL(ksys_sync_helper);
++
+ EXPORT_SYMBOL_GPL(unlock_system_sleep);
+ 
+ /* Routines for PM-transition notifications */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3739-drm-amdgpu-fix-ras-parameter-descriptions.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3739-drm-amdgpu-fix-ras-parameter-descriptions.patch
new file mode 100644
index 00000000..ccc5360b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3739-drm-amdgpu-fix-ras-parameter-descriptions.patch
@@ -0,0 +1,90 @@
+From fa640b07a935631c88d0f6abe773890c0e08d913 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 7 Mar 2019 14:46:38 +0800
+Subject: [PATCH 3739/4256] drm/amdgpu: fix ras parameter descriptions
+
+The descriptions of modinfo wrongly show two parameters
+for each feature(see below). This patch can fix this
+incorrect outputs.
+
+parm:           amdgpu_ras_enable:Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
+parm:           ras_enable:int
+parm:           amdgpu_ras_mask:Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
+parm:           ras_mask:uint
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: xinhui pan <xinhui.pan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c     |  8 +++---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.rej | 30 +++++++++++++++++++++
+ 2 files changed, 34 insertions(+), 4 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.rej
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 3aa7c136d2c3..511fd4649796 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -529,18 +529,18 @@ MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
+ module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
+ 
+ /*
+- * DOC: amdgpu_ras_enable (int)
++ * DOC: ras_enable (int)
+  * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
+  */
+-MODULE_PARM_DESC(amdgpu_ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
++MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
+ module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
+ 
+ /**
+- * DOC: amdgpu_ras_mask (uint)
++ * DOC: ras_mask (uint)
+  * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
+  * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+  */
+-MODULE_PARM_DESC(amdgpu_ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
++MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
+ module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
+ 
+ /**
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.rej b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.rej
+new file mode 100644
+index 000000000000..98377b949f17
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.rej
+@@ -0,0 +1,30 @@
++--- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++@@ -527,22 +527,21 @@ module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
++ MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
++ module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
++ 
++-/*
++- * DOC: amdgpu_ras_enable (int)
+++/**
+++ * DOC: ras_enable (int)
++  * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
++  */
++-MODULE_PARM_DESC(amdgpu_ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
+++MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
++ module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
++ 
++ /**
++- * DOC: amdgpu_ras_mask (uint)
+++ * DOC: ras_mask (uint)
++  * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
++  * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++  */
++-MODULE_PARM_DESC(amdgpu_ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
+++MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
++ module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
++ 
++-
++ /**
++  * DOC: si_support (int)
++  * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3740-drm-amdgpu-set-ip-specific-ras-interface-pointer-to-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3740-drm-amdgpu-set-ip-specific-ras-interface-pointer-to-.patch
new file mode 100644
index 00000000..5e0b3669
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3740-drm-amdgpu-set-ip-specific-ras-interface-pointer-to-.patch
@@ -0,0 +1,134 @@
+From e435de2a43a55ec79ddfc88d8f8855b92ca967bb Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Tue, 3 Sep 2019 03:16:47 +0800
+Subject: [PATCH 3740/4256] drm/amdgpu: set ip specific ras interface pointer
+ to NULL after free it
+
+to prevent access to dangling pointers
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 7 +++++--
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 8 ++++++--
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 4 +++-
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c  | 4 ++++
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c  | 8 ++++++--
+ 5 files changed, 24 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 918eaeedb5b9..18272761af53 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4442,14 +4442,17 @@ static int gfx_v9_0_ecc_late_init(void *handle)
+ 		r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
+ 		if (r)
+ 			goto late_fini;
+-	} else
+-		kfree(adev->gfx.ras_if);
++	} else {
++		r = 0;
++		goto free;
++	}
+ 
+ 	return 0;
+ late_fini:
+ 	amdgpu_ras_late_fini(adev, adev->gfx.ras_if, &ih_info);
+ free:
+ 	kfree(adev->gfx.ras_if);
++	adev->gfx.ras_if = NULL;
+ 	return r;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 617311db7d2e..a72c63124d50 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -795,8 +795,11 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ 		r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
+ 		if (r)
+ 			goto umc_late_fini;
+-	} else
+-		kfree(adev->gmc.umc_ras_if);
++	} else {
++		/* free umc ras_if if umc ras is not supported */
++		r = 0;
++		goto free;
++	}
+ 
+ 	if (adev->mmhub_funcs && adev->mmhub_funcs->ras_late_init) {
+ 		r = adev->mmhub_funcs->ras_late_init(adev);
+@@ -808,6 +811,7 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ 	amdgpu_ras_late_fini(adev, adev->gmc.umc_ras_if, &umc_ih_info);
+ free:
+ 	kfree(adev->gmc.umc_ras_if);
++	adev->gmc.umc_ras_if = NULL;
+ 	return r;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index 3b28c1c0cf21..57aae096947d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -641,8 +641,10 @@ static int mmhub_v1_0_ras_late_init(struct amdgpu_device *adev)
+ 	mmhub_ih_info.head = mmhub_fs_info.head = *adev->gmc.mmhub_ras_if;
+ 	r = amdgpu_ras_late_init(adev, adev->gmc.mmhub_ras_if,
+ 				 &mmhub_fs_info, &mmhub_ih_info);
+-	if (r || !amdgpu_ras_is_supported(adev, adev->gmc.mmhub_ras_if->block))
++	if (r || !amdgpu_ras_is_supported(adev, adev->gmc.mmhub_ras_if->block)) {
+ 		kfree(adev->gmc.mmhub_ras_if);
++		adev->gmc.mmhub_ras_if = NULL;
++	}
+ 	return r;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index 27eeab143ad7..f25c6a9c6718 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -507,6 +507,9 @@ static int nbio_v7_4_ras_late_init(struct amdgpu_device *adev)
+ 		r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
+ 		if (r)
+ 			goto late_fini;
++	} else {
++		r = 0;
++		goto free;
+ 	}
+ 
+ 	return 0;
+@@ -514,6 +517,7 @@ static int nbio_v7_4_ras_late_init(struct amdgpu_device *adev)
+ 	amdgpu_ras_late_fini(adev, adev->nbio.ras_if, &ih_info);
+ free:
+ 	kfree(adev->nbio.ras_if);
++	adev->nbio.ras_if = NULL;
+ 	return r;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 6424723e1af0..b837ffd161e6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1727,14 +1727,18 @@ static int sdma_v4_0_late_init(void *handle)
+ 			if (r)
+ 				goto late_fini;
+ 		}
+-	} else
+-		kfree(adev->sdma.ras_if);
++	} else {
++		/* free sdma ras_if if sdma ras is not supported */
++		r = 0;
++		goto free;
++	}
+ 
+         return 0;
+ late_fini:
+ 	amdgpu_ras_late_fini(adev, adev->sdma.ras_if, &ih_info);
+ free:
+ 	kfree(adev->sdma.ras_if);
++	adev->sdma.ras_if = NULL;
+ 	return r;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3741-drm-amdgpu-gmc-switch-to-amdgpu_gmc_ras_late_init-he.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3741-drm-amdgpu-gmc-switch-to-amdgpu_gmc_ras_late_init-he.patch
new file mode 100644
index 00000000..02fb761e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3741-drm-amdgpu-gmc-switch-to-amdgpu_gmc_ras_late_init-he.patch
@@ -0,0 +1,156 @@
+From da203b1ef5606035e1d0ef74c91a1da68cb30806 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Tue, 3 Sep 2019 05:24:35 +0800
+Subject: [PATCH 3741/4256] drm/amdgpu/gmc: switch to amdgpu_gmc_ras_late_init
+ helper function
+
+amdgpu_gmc_ras_late_init is used to init gmc specfic
+ras debugfs/sysfs node and gmc specific interrupt handler.
+It can be shared among gmc generations.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 49 +++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  2 +
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 36 +-----------------
+ 3 files changed, 53 insertions(+), 34 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+index 6094990dcbee..51890b1d8522 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+@@ -25,6 +25,7 @@
+  */
+ 
+ #include "amdgpu.h"
++#include "amdgpu_ras.h"
+ 
+ /**
+  * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
+@@ -303,3 +304,51 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
+ 	gmc->fault_hash[hash].idx = gmc->last_fault++;
+ 	return false;
+ }
++
++int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev,
++			     void *ras_ih_info)
++{
++	int r;
++	struct ras_ih_if *ih_info = (struct ras_ih_if *)ras_ih_info;
++	struct ras_fs_if fs_info = {
++		.sysfs_name = "umc_err_count",
++		.debugfs_name = "umc_err_inject",
++	};
++
++	if (!ih_info)
++		return -EINVAL;
++
++	if (!adev->gmc.umc_ras_if) {
++		adev->gmc.umc_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++		if (!adev->gmc.umc_ras_if)
++			return -ENOMEM;
++		adev->gmc.umc_ras_if->block = AMDGPU_RAS_BLOCK__UMC;
++		adev->gmc.umc_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++		adev->gmc.umc_ras_if->sub_block_index = 0;
++		strcpy(adev->gmc.umc_ras_if->name, "umc");
++	}
++	ih_info->head = fs_info.head = *adev->gmc.umc_ras_if;
++
++	r = amdgpu_ras_late_init(adev, adev->gmc.umc_ras_if,
++				 &fs_info, ih_info);
++	if (r)
++		goto free;
++
++	if (amdgpu_ras_is_supported(adev, adev->gmc.umc_ras_if->block)) {
++		r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
++		if (r)
++			goto late_fini;
++	} else {
++		r = 0;
++		goto free;
++	}
++
++	return 0;
++
++late_fini:
++	amdgpu_ras_late_fini(adev, adev->gmc.umc_ras_if, ih_info);
++free:
++	kfree(adev->gmc.umc_ras_if);
++	adev->gmc.umc_ras_if = NULL;
++	return r;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+index e03351f0ba5a..03687fa01817 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+@@ -230,5 +230,7 @@ void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
+ 			     struct amdgpu_gmc *mc);
+ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
+ 			      uint16_t pasid, uint64_t timestamp);
++int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev,
++			     void *ih_info);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index a72c63124d50..d5c18deb407a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -767,39 +767,13 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ {
+ 	int r;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	struct ras_fs_if umc_fs_info = {
+-		.sysfs_name = "umc_err_count",
+-		.debugfs_name = "umc_err_inject",
+-	};
+ 	struct ras_ih_if umc_ih_info = {
+ 		.cb = gmc_v9_0_process_ras_data_cb,
+ 	};
+ 
+-	if (!adev->gmc.umc_ras_if) {
+-		adev->gmc.umc_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
+-		if (!adev->gmc.umc_ras_if)
+-			return -ENOMEM;
+-		adev->gmc.umc_ras_if->block = AMDGPU_RAS_BLOCK__UMC;
+-		adev->gmc.umc_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
+-		adev->gmc.umc_ras_if->sub_block_index = 0;
+-		strcpy(adev->gmc.umc_ras_if->name, "umc");
+-	}
+-	umc_ih_info.head = umc_fs_info.head = *adev->gmc.umc_ras_if;
+-
+-	r = amdgpu_ras_late_init(adev, adev->gmc.umc_ras_if,
+-				 &umc_fs_info, &umc_ih_info);
++	r = amdgpu_gmc_ras_late_init(adev, &umc_ih_info);
+ 	if (r)
+-		goto free;
+-
+-	if (amdgpu_ras_is_supported(adev, adev->gmc.umc_ras_if->block)) {
+-		r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
+-		if (r)
+-			goto umc_late_fini;
+-	} else {
+-		/* free umc ras_if if umc ras is not supported */
+-		r = 0;
+-		goto free;
+-	}
++		return r;
+ 
+ 	if (adev->mmhub_funcs && adev->mmhub_funcs->ras_late_init) {
+ 		r = adev->mmhub_funcs->ras_late_init(adev);
+@@ -807,12 +781,6 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ 			return r;
+ 	}
+ 	return 0;
+-umc_late_fini:
+-	amdgpu_ras_late_fini(adev, adev->gmc.umc_ras_if, &umc_ih_info);
+-free:
+-	kfree(adev->gmc.umc_ras_if);
+-	adev->gmc.umc_ras_if = NULL;
+-	return r;
+ }
+ 
+ static int gmc_v9_0_late_init(void *handle)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3742-drm-amdgpu-gfx-switch-to-amdgpu_gfx_ras_late_init-he.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3742-drm-amdgpu-gfx-switch-to-amdgpu_gfx_ras_late_init-he.patch
new file mode 100644
index 00000000..d4160a88
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3742-drm-amdgpu-gfx-switch-to-amdgpu_gfx_ras_late_init-he.patch
@@ -0,0 +1,155 @@
+From fd3d679b6c1d5b791fdd5f3d349ffb8ff1c5b11b Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Tue, 3 Sep 2019 06:06:08 +0800
+Subject: [PATCH 3742/4256] drm/amdgpu/gfx: switch to amdgpu_gfx_ras_late_init
+ helper function
+
+amdgpu_gfx_ras_late_init is used to init gfx specfic
+ras debugfs/sysfs node and gfx specific interrupt handler.
+It can be shared among gfx generations
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 49 +++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  3 +-
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 37 ++-----------------
+ 3 files changed, 54 insertions(+), 35 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+index e1fdcb44a7dd..508d521a0e59 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+@@ -26,6 +26,7 @@
+ #include "amdgpu.h"
+ #include "amdgpu_gfx.h"
+ #include "amdgpu_rlc.h"
++#include "amdgpu_ras.h"
+ 
+ /* delay 0.1 second to enable gfx off feature */
+ #define GFX_OFF_DELAY_ENABLE         msecs_to_jiffies(100)
+@@ -569,3 +570,51 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
+ 
+ 	mutex_unlock(&adev->gfx.gfx_off_mutex);
+ }
++
++int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev,
++			     void *ras_ih_info)
++{
++	int r;
++	struct ras_ih_if *ih_info = (struct ras_ih_if *)ras_ih_info;
++	struct ras_fs_if fs_info = {
++		.sysfs_name = "gfx_err_count",
++		.debugfs_name = "gfx_err_inject",
++	};
++
++	if (!ih_info)
++		return -EINVAL;
++
++	if (!adev->gfx.ras_if) {
++		adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++		if (!adev->gfx.ras_if)
++			return -ENOMEM;
++		adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX;
++		adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++		adev->gfx.ras_if->sub_block_index = 0;
++		strcpy(adev->gfx.ras_if->name, "gfx");
++	}
++	fs_info.head = ih_info->head = *adev->gfx.ras_if;
++
++	r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
++				 &fs_info, ih_info);
++	if (r)
++		goto free;
++
++	if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) {
++		r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
++		if (r)
++			goto late_fini;
++	} else {
++		/* free gfx ras_if if ras is not supported */
++		r = 0;
++		goto free;
++	}
++
++	return 0;
++late_fini:
++	amdgpu_ras_late_fini(adev, adev->gfx.ras_if, ih_info);
++free:
++	kfree(adev->gfx.ras_if);
++	adev->gfx.ras_if = NULL;
++	return r;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+index 554a59b3c4a6..6ed0560d7299 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+@@ -383,5 +383,6 @@ void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
+ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
+ 				    int pipe, int queue);
+ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
+-
++int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev,
++			     void *ras_ih_info);
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 18272761af53..3ad97ca9efc5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4407,22 +4407,11 @@ static int gfx_v9_0_ecc_late_init(void *handle)
+ 	struct ras_ih_if ih_info = {
+ 		.cb = gfx_v9_0_process_ras_data_cb,
+ 	};
+-	struct ras_fs_if fs_info = {
+-		.sysfs_name = "gfx_err_count",
+-		.debugfs_name = "gfx_err_inject",
+-	};
+ 	int r;
+ 
+-	if (!adev->gfx.ras_if) {
+-		adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
+-		if (!adev->gfx.ras_if)
+-			return -ENOMEM;
+-		adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX;
+-		adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
+-		adev->gfx.ras_if->sub_block_index = 0;
+-		strcpy(adev->gfx.ras_if->name, "gfx");
+-	}
+-	fs_info.head = ih_info.head = *adev->gfx.ras_if;
++	r = amdgpu_gfx_ras_late_init(adev, &ih_info);
++	if (r)
++		return r;
+ 
+ 	r = gfx_v9_0_do_edc_gds_workarounds(adev);
+ 	if (r)
+@@ -4433,27 +4422,7 @@ static int gfx_v9_0_ecc_late_init(void *handle)
+ 	if (r)
+ 		return r;
+ 
+-	r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
+-				 &fs_info, &ih_info);
+-	if (r)
+-		goto free;
+-
+-	if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) {
+-		r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
+-		if (r)
+-			goto late_fini;
+-	} else {
+-		r = 0;
+-		goto free;
+-	}
+-
+ 	return 0;
+-late_fini:
+-	amdgpu_ras_late_fini(adev, adev->gfx.ras_if, &ih_info);
+-free:
+-	kfree(adev->gfx.ras_if);
+-	adev->gfx.ras_if = NULL;
+-	return r;
+ }
+ 
+ static int gfx_v9_0_late_init(void *handle)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3743-drm-amdgpu-sdma-switch-to-amdgpu_sdma_ras_late_init-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3743-drm-amdgpu-sdma-switch-to-amdgpu_sdma_ras_late_init-.patch
new file mode 100644
index 00000000..9772c158
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3743-drm-amdgpu-sdma-switch-to-amdgpu_sdma_ras_late_init-.patch
@@ -0,0 +1,153 @@
+From 84948b7edd03e91b08875b0d5ef88cf0a596e794 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Tue, 3 Sep 2019 06:02:07 +0800
+Subject: [PATCH 3743/4256] drm/amdgpu/sdma: switch to
+ amdgpu_sdma_ras_late_init helper function
+
+amdgpu_sdma_ras_late_init is used to init sdma specfic
+ras debugfs/sysfs node and sdma specific interrupt handler.
+It can be shared among sdma generations
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 52 ++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h |  2 +
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 42 +------------------
+ 3 files changed, 55 insertions(+), 41 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+index 7ddffbf65999..a25301b75ef7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+@@ -23,6 +23,7 @@
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
+ #include "amdgpu_sdma.h"
++#include "amdgpu_ras.h"
+ 
+ #define AMDGPU_CSA_SDMA_SIZE 64
+ /* SDMA CSA reside in the 3rd page of CSA */
+@@ -83,3 +84,54 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring,
+ 
+ 	return csa_mc_addr;
+ }
++
++int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
++			      void *ras_ih_info)
++{
++	int r, i;
++	struct ras_ih_if *ih_info = (struct ras_ih_if *)ras_ih_info;
++	struct ras_fs_if fs_info = {
++		.sysfs_name = "sdma_err_count",
++		.debugfs_name = "sdma_err_inject",
++	};
++
++	if (!ih_info)
++		return -EINVAL;
++
++	if (!adev->sdma.ras_if) {
++		adev->sdma.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++		if (!adev->sdma.ras_if)
++			return -ENOMEM;
++		adev->sdma.ras_if->block = AMDGPU_RAS_BLOCK__SDMA;
++		adev->sdma.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++		adev->sdma.ras_if->sub_block_index = 0;
++		strcpy(adev->sdma.ras_if->name, "sdma");
++	}
++	fs_info.head = ih_info->head = *adev->sdma.ras_if;
++
++	r = amdgpu_ras_late_init(adev, adev->sdma.ras_if,
++				 &fs_info, ih_info);
++	if (r)
++		goto free;
++
++	if (amdgpu_ras_is_supported(adev, adev->sdma.ras_if->block)) {
++		for (i = 0; i < adev->sdma.num_instances; i++) {
++			r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq,
++				AMDGPU_SDMA_IRQ_INSTANCE0 + i);
++			if (r)
++				goto late_fini;
++		}
++	} else {
++		r = 0;
++		goto free;
++	}
++
++        return 0;
++
++late_fini:
++	amdgpu_ras_late_fini(adev, adev->sdma.ras_if, ih_info);
++free:
++	kfree(adev->sdma.ras_if);
++	adev->sdma.ras_if = NULL;
++	return r;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+index a9ae0d8a0589..79dcb907d00d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+@@ -104,4 +104,6 @@ struct amdgpu_sdma_instance *
+ amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
+ int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
+ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
++int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
++			      void *ras_ih_info);
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index b837ffd161e6..9cf417a76697 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1698,48 +1698,8 @@ static int sdma_v4_0_late_init(void *handle)
+ 	struct ras_ih_if ih_info = {
+ 		.cb = sdma_v4_0_process_ras_data_cb,
+ 	};
+-	struct ras_fs_if fs_info = {
+-		.sysfs_name = "sdma_err_count",
+-		.debugfs_name = "sdma_err_inject",
+-	};
+-	int r, i;
+-
+-	if (!adev->sdma.ras_if) {
+-		adev->sdma.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
+-		if (!adev->sdma.ras_if)
+-			return -ENOMEM;
+-		adev->sdma.ras_if->block = AMDGPU_RAS_BLOCK__SDMA;
+-		adev->sdma.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
+-		adev->sdma.ras_if->sub_block_index = 0;
+-		strcpy(adev->sdma.ras_if->name, "sdma");
+-	}
+-	fs_info.head = ih_info.head = *adev->sdma.ras_if;
+-
+-	r = amdgpu_ras_late_init(adev, adev->sdma.ras_if,
+-				 &fs_info, &ih_info);
+-	if (r)
+-		goto free;
+-
+-	if (amdgpu_ras_is_supported(adev, adev->sdma.ras_if->block)) {
+-		for (i = 0; i < adev->sdma.num_instances; i++) {
+-			r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq,
+-				AMDGPU_SDMA_IRQ_INSTANCE0 + i);
+-			if (r)
+-				goto late_fini;
+-		}
+-	} else {
+-		/* free sdma ras_if if sdma ras is not supported */
+-		r = 0;
+-		goto free;
+-	}
+ 
+-        return 0;
+-late_fini:
+-	amdgpu_ras_late_fini(adev, adev->sdma.ras_if, &ih_info);
+-free:
+-	kfree(adev->sdma.ras_if);
+-	adev->sdma.ras_if = NULL;
+-	return r;
++	return amdgpu_sdma_ras_late_init(adev, &ih_info);
+ }
+ 
+ static int sdma_v4_0_sw_init(void *handle)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3744-drm-amdgpu-mmhub-switch-to-amdgpu_mmhub_ras_late_ini.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3744-drm-amdgpu-mmhub-switch-to-amdgpu_mmhub_ras_late_ini.patch
new file mode 100644
index 00000000..cedd2870
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3744-drm-amdgpu-mmhub-switch-to-amdgpu_mmhub_ras_late_ini.patch
@@ -0,0 +1,157 @@
+From f9a34a087619c677c4cf6c33571ea95af27b6214 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Tue, 3 Sep 2019 06:23:12 +0800
+Subject: [PATCH 3744/4256] drm/amdgpu/mmhub: switch to
+ amdgpu_mmhub_ras_late_init helper function
+
+amdgpu_mmhub_ras_late_init is used to init mmhub specfic
+ras debugfs/sysfs node and mmhub specific interrupt handler.
+It can be shared among mmhub generations
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile       |  6 +--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c | 56 +++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h |  2 +
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c   | 32 +------------
+ 4 files changed, 62 insertions(+), 34 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index 5a38934c5c94..3baa143714ab 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -53,9 +53,9 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
+ 	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
+ 	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
+ 	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
+-	amdgpu_sem.o amdgpu_gmc.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o \
+-	amdgpu_vm_cpu.o amdgpu_vm_sdma.o amdgpu_pmu.o amdgpu_discovery.o \
+-	amdgpu_ras_eeprom.o smu_v11_0_i2c.o
++	amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_sem.o \
++	amdgpu_ras.o amdgpu_vm_cpu.o amdgpu_vm_sdma.o amdgpu_pmu.o \
++	amdgpu_discovery.o amdgpu_ras_eeprom.o smu_v11_0_i2c.o
+ 
+ amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c
+new file mode 100644
+index 000000000000..99ef6b1f8526
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c
+@@ -0,0 +1,56 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include "amdgpu.h"
++#include "amdgpu_ras.h"
++
++int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev)
++{
++	int r;
++	struct ras_ih_if ih_info = {
++		.cb = NULL,
++	};
++	struct ras_fs_if fs_info = {
++		.sysfs_name = "mmhub_err_count",
++		.debugfs_name = "mmhub_err_inject",
++	};
++
++	if (!adev->gmc.mmhub_ras_if) {
++		adev->gmc.mmhub_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++		if (!adev->gmc.mmhub_ras_if)
++			return -ENOMEM;
++		adev->gmc.mmhub_ras_if->block = AMDGPU_RAS_BLOCK__MMHUB;
++		adev->gmc.mmhub_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++		adev->gmc.mmhub_ras_if->sub_block_index = 0;
++		strcpy(adev->gmc.mmhub_ras_if->name, "mmhub");
++	}
++	ih_info.head = fs_info.head = *adev->gmc.mmhub_ras_if;
++	r = amdgpu_ras_late_init(adev, adev->gmc.mmhub_ras_if,
++				 &fs_info, &ih_info);
++	if (r || !amdgpu_ras_is_supported(adev, adev->gmc.mmhub_ras_if->block)) {
++		kfree(adev->gmc.mmhub_ras_if);
++		adev->gmc.mmhub_ras_if = NULL;
++	}
++
++	return r;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
+index df04c718dfab..685e54e58700 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
+@@ -28,5 +28,7 @@ struct amdgpu_mmhub_funcs {
+ 					void *ras_error_status);
+ };
+ 
++int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev);
++
+ #endif
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index 57aae096947d..85fdd47e015f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -618,37 +618,7 @@ static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev,
+ 	}
+ }
+ 
+-static int mmhub_v1_0_ras_late_init(struct amdgpu_device *adev)
+-{
+-	int r;
+-	struct ras_ih_if mmhub_ih_info = {
+-		.cb = NULL,
+-	};
+-	struct ras_fs_if mmhub_fs_info = {
+-		.sysfs_name = "mmhub_err_count",
+-		.debugfs_name = "mmhub_err_inject",
+-	};
+-
+-	if (!adev->gmc.mmhub_ras_if) {
+-		adev->gmc.mmhub_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
+-		if (!adev->gmc.mmhub_ras_if)
+-			return -ENOMEM;
+-		adev->gmc.mmhub_ras_if->block = AMDGPU_RAS_BLOCK__MMHUB;
+-		adev->gmc.mmhub_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
+-		adev->gmc.mmhub_ras_if->sub_block_index = 0;
+-		strcpy(adev->gmc.mmhub_ras_if->name, "mmhub");
+-	}
+-	mmhub_ih_info.head = mmhub_fs_info.head = *adev->gmc.mmhub_ras_if;
+-	r = amdgpu_ras_late_init(adev, adev->gmc.mmhub_ras_if,
+-				 &mmhub_fs_info, &mmhub_ih_info);
+-	if (r || !amdgpu_ras_is_supported(adev, adev->gmc.mmhub_ras_if->block)) {
+-		kfree(adev->gmc.mmhub_ras_if);
+-		adev->gmc.mmhub_ras_if = NULL;
+-	}
+-	return r;
+-}
+-
+ const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {
+-	.ras_late_init = mmhub_v1_0_ras_late_init,
++	.ras_late_init = amdgpu_mmhub_ras_late_init,
+ 	.query_ras_error_count = mmhub_v1_0_query_ras_error_count,
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3745-drm-amdgpu-nbio-switch-to-amdgpu_nbio_ras_late_init-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3745-drm-amdgpu-nbio-switch-to-amdgpu_nbio_ras_late_init-.patch
new file mode 100644
index 00000000..20ade8ee
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3745-drm-amdgpu-nbio-switch-to-amdgpu_nbio_ras_late_init-.patch
@@ -0,0 +1,188 @@
+From 1cf6a881d1889000886c14e105da27e846b89c08 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Tue, 3 Sep 2019 06:48:00 +0800
+Subject: [PATCH 3745/4256] drm/amdgpu/nbio: switch to
+ amdgpu_nbio_ras_late_init helper function
+
+amdgpu_nbio_ras_late_init is used to init nbio specfic
+ras debugfs/sysfs node and nbio specific interrupt handler.
+It can be shared among nbio generations
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile      |  2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c | 70 ++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h |  2 +
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c   | 49 +----------------
+ 4 files changed, 74 insertions(+), 49 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index 3baa143714ab..655e5f0cf7b2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -55,7 +55,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
+ 	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
+ 	amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_sem.o \
+ 	amdgpu_ras.o amdgpu_vm_cpu.o amdgpu_vm_sdma.o amdgpu_pmu.o \
+-	amdgpu_discovery.o amdgpu_ras_eeprom.o smu_v11_0_i2c.o
++	amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o smu_v11_0_i2c.o
+ 
+ amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
+new file mode 100644
+index 000000000000..65373ad03763
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
+@@ -0,0 +1,70 @@
++/*
++ * Copyright (C) 2019  Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include "amdgpu.h"
++#include "amdgpu_ras.h"
++
++int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev)
++{
++	int r;
++	struct ras_ih_if ih_info = {
++		.cb = NULL,
++	};
++	struct ras_fs_if fs_info = {
++		.sysfs_name = "pcie_bif_err_count",
++		.debugfs_name = "pcie_bif_err_inject",
++	};
++
++	if (!adev->nbio.ras_if) {
++		adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++		if (!adev->nbio.ras_if)
++			return -ENOMEM;
++		adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF;
++		adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++		adev->nbio.ras_if->sub_block_index = 0;
++		strcpy(adev->nbio.ras_if->name, "pcie_bif");
++	}
++	ih_info.head = fs_info.head = *adev->nbio.ras_if;
++	r = amdgpu_ras_late_init(adev, adev->nbio.ras_if,
++				 &fs_info, &ih_info);
++	if (r)
++		goto free;
++
++	if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
++		r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0);
++		if (r)
++			goto late_fini;
++		r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
++		if (r)
++			goto late_fini;
++	} else {
++		r = 0;
++		goto free;
++	}
++
++	return 0;
++late_fini:
++	amdgpu_ras_late_fini(adev, adev->nbio.ras_if, &ih_info);
++free:
++	kfree(adev->nbio.ras_if);
++	adev->nbio.ras_if = NULL;
++	return r;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+index 51078da6188f..c5255a7fd65a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+@@ -92,4 +92,6 @@ struct amdgpu_nbio {
+ 	const struct amdgpu_nbio_funcs *funcs;
+ };
+ 
++int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index f25c6a9c6718..bfa919190fb4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -474,53 +474,6 @@ static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *a
+ 	return 0;
+ }
+ 
+-static int nbio_v7_4_ras_late_init(struct amdgpu_device *adev)
+-{
+-	int r;
+-	struct ras_ih_if ih_info = {
+-		.cb = NULL,
+-	};
+-	struct ras_fs_if fs_info = {
+-		.sysfs_name = "pcie_bif_err_count",
+-		.debugfs_name = "pcie_bif_err_inject",
+-	};
+-
+-	if (!adev->nbio.ras_if) {
+-		adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
+-		if (!adev->nbio.ras_if)
+-			return -ENOMEM;
+-		adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF;
+-		adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
+-		adev->nbio.ras_if->sub_block_index = 0;
+-		strcpy(adev->nbio.ras_if->name, "pcie_bif");
+-	}
+-	ih_info.head = fs_info.head = *adev->nbio.ras_if;
+-	r = amdgpu_ras_late_init(adev, adev->nbio.ras_if,
+-				 &fs_info, &ih_info);
+-	if (r)
+-		goto free;
+-
+-	if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
+-		r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0);
+-		if (r)
+-			goto late_fini;
+-		r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
+-		if (r)
+-			goto late_fini;
+-	} else {
+-		r = 0;
+-		goto free;
+-	}
+-
+-	return 0;
+-late_fini:
+-	amdgpu_ras_late_fini(adev, adev->nbio.ras_if, &ih_info);
+-free:
+-	kfree(adev->nbio.ras_if);
+-	adev->nbio.ras_if = NULL;
+-	return r;
+-}
+-
+ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ 	.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
+ 	.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
+@@ -546,5 +499,5 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ 	.handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
+ 	.init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,
+ 	.init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,
+-	.ras_late_init = nbio_v7_4_ras_late_init,
++	.ras_late_init = amdgpu_nbio_ras_late_init,
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3746-drm-amdgpu-init-UMC-RSMU-register-base-address.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3746-drm-amdgpu-init-UMC-RSMU-register-base-address.patch
new file mode 100644
index 00000000..59fa2ca8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3746-drm-amdgpu-init-UMC-RSMU-register-base-address.patch
@@ -0,0 +1,29 @@
+From 6b936a3600c9365173fa189ebee8715c84746e56 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Tue, 3 Sep 2019 03:19:31 +0800
+Subject: [PATCH 3746/4256] drm/amdgpu: init UMC & RSMU register base address
+
+UMC RAS feature requires access to UMC & RSMU registers
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/arct_reg_init.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c b/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c
+index 4853899b1824..e62609d5126b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c
++++ b/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c
+@@ -52,6 +52,8 @@ int arct_reg_base_init(struct amdgpu_device *adev)
+ 		adev->reg_offset[SDMA7_HWIP][i] = (uint32_t *)(&(SDMA7_BASE.instance[i]));
+ 		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
+ 		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
++		adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));
++		adev->reg_offset[RSMU_HWIP][i] = (uint32_t *)(&(RSMU_BASE.instance[i]));
+ 	}
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3747-drm-amdgpu-Add-smu-lock-around-in-pp_smu_i2c_bus_acc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3747-drm-amdgpu-Add-smu-lock-around-in-pp_smu_i2c_bus_acc.patch
new file mode 100644
index 00000000..ba80cf48
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3747-drm-amdgpu-Add-smu-lock-around-in-pp_smu_i2c_bus_acc.patch
@@ -0,0 +1,43 @@
+From ce810fba5402f2d80730733cdeb947c3bcc790a8 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Tue, 3 Sep 2019 16:47:40 -0400
+Subject: [PATCH 3747/4256] drm/amdgpu: Add smu lock around in
+ pp_smu_i2c_bus_access
+
+Protect from concurrent SMU accesses.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-and-tested-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+index fa636cb462c1..fa8ad7db2b3a 100644
+--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+@@ -1531,6 +1531,7 @@ static int pp_asic_reset_mode_2(void *handle)
+ static int pp_smu_i2c_bus_access(void *handle, bool acquire)
+ {
+ 	struct pp_hwmgr *hwmgr = handle;
++	int ret = 0;
+ 
+ 	if (!hwmgr || !hwmgr->pm_en)
+ 		return -EINVAL;
+@@ -1540,7 +1541,11 @@ static int pp_smu_i2c_bus_access(void *handle, bool acquire)
+ 		return -EINVAL;
+ 	}
+ 
+-	return hwmgr->hwmgr_func->smu_i2c_bus_access(hwmgr, acquire);
++	mutex_lock(&hwmgr->smu_lock);
++	ret = hwmgr->hwmgr_func->smu_i2c_bus_access(hwmgr, acquire);
++	mutex_unlock(&hwmgr->smu_lock);
++
++	return ret;
+ }
+ 
+ static const struct amd_pm_funcs pp_dpm_funcs = {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3748-drm-amdgpu-Remove-clock-gating-restore.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3748-drm-amdgpu-Remove-clock-gating-restore.patch
new file mode 100644
index 00000000..56ef8962
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3748-drm-amdgpu-Remove-clock-gating-restore.patch
@@ -0,0 +1,39 @@
+From e1bf1c707aeb54987d85d18ca03dfa7316d85e2a Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Wed, 4 Sep 2019 11:16:24 -0400
+Subject: [PATCH 3748/4256] drm/amdgpu: Remove clock gating restore.
+
+Restoring clock gating break SMU opeartion afterwards, avoid
+this until this further invistigated with SMU.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-and-tested-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
+index 7d0d4c57b315..aad83932dd05 100644
+--- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
++++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
+@@ -491,7 +491,15 @@ static void smu_v11_0_i2c_fini(struct i2c_adapter *control)
+ 	}
+ 
+ 	/* Restore clock gating */
+-	smu_v11_0_i2c_set_clock_gating(control, true);
++
++	/*
++	 * TODO Reenabling clock gating seems to break subsequent SMU operation
++	 *      on the I2C bus. My guess is that SMU doesn't disable clock gating like
++	 *      we do here before working with the bus. So for now just don't restore
++	 *      it but later work with SMU to see if they have this issue and can
++	 *      update their code appropriately
++	 */
++	/* smu_v11_0_i2c_set_clock_gating(control, true); */
+ 
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3749-drm-madgpu-Fix-EEPROM-Checksum-calculation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3749-drm-madgpu-Fix-EEPROM-Checksum-calculation.patch
new file mode 100644
index 00000000..c40c5a8c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3749-drm-madgpu-Fix-EEPROM-Checksum-calculation.patch
@@ -0,0 +1,32 @@
+From 597258875216221dc204572186cf6395076a3353 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Wed, 4 Sep 2019 22:45:20 -0400
+Subject: [PATCH 3749/4256] drm/madgpu: Fix EEPROM Checksum calculation.
+
+Fix typo which messed up the calculation.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-and-tested-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+index 8a32b5c93778..43dd4ab9b6d5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+@@ -226,8 +226,8 @@ static void __decode_table_record_from_buff(struct amdgpu_ras_eeprom_control *co
+ 	record->offset = (le64_to_cpu(tmp) & 0xffffffffffff);
+ 	i += 6;
+ 
+-	buff[i++] = record->mem_channel;
+-	buff[i++] = record->mcumc_id;
++	record->mem_channel = buff[i++];
++	record->mcumc_id = buff[i++];
+ 
+ 	memcpy(&tmp, buff + i,  6);
+ 	record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3750-drm-amdgpu-change-ras-bps-type-to-eeprom-table-recor.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3750-drm-amdgpu-change-ras-bps-type-to-eeprom-table-recor.patch
new file mode 100644
index 00000000..6c6f64df
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3750-drm-amdgpu-change-ras-bps-type-to-eeprom-table-recor.patch
@@ -0,0 +1,186 @@
+From 769ca42dc042d1ca918ced73a89f2732b626d328 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Tue, 13 Aug 2019 10:39:05 +0800
+Subject: [PATCH 3750/4256] drm/amdgpu: change ras bps type to eeprom table
+ record structure
+
+change bps type from retired page to eeprom table record, prepare for
+saving umc error records to eeprom
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 59 ++++++++++++++++---------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 11 +++--
+ 2 files changed, 43 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 5c2276bb8325..c6f4c01b98a8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1203,14 +1203,14 @@ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
+ 
+ 	for (; i < data->count; i++) {
+ 		(*bps)[i] = (struct ras_badpage){
+-			.bp = data->bps[i].bp,
++			.bp = data->bps[i].retired_page,
+ 			.size = AMDGPU_GPU_PAGE_SIZE,
+ 			.flags = 0,
+ 		};
+ 
+ 		if (data->last_reserved <= i)
+ 			(*bps)[i].flags = 1;
+-		else if (data->bps[i].bo == NULL)
++		else if (data->bps_bo[i] == NULL)
+ 			(*bps)[i].flags = 2;
+ 	}
+ 
+@@ -1304,30 +1304,40 @@ static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
+ {
+ 	unsigned int old_space = data->count + data->space_left;
+ 	unsigned int new_space = old_space + pages;
+-	unsigned int align_space = ALIGN(new_space, 1024);
+-	void *tmp = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
+-
+-	if (!tmp)
++	unsigned int align_space = ALIGN(new_space, 512);
++	void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
++	struct amdgpu_bo **bps_bo =
++			kmalloc(align_space * sizeof(*data->bps_bo), GFP_KERNEL);
++
++	if (!bps || !bps_bo) {
++		kfree(bps);
++		kfree(bps_bo);
+ 		return -ENOMEM;
++	}
+ 
+ 	if (data->bps) {
+-		memcpy(tmp, data->bps,
++		memcpy(bps, data->bps,
+ 				data->count * sizeof(*data->bps));
+ 		kfree(data->bps);
+ 	}
++	if (data->bps_bo) {
++		memcpy(bps_bo, data->bps_bo,
++				data->count * sizeof(*data->bps_bo));
++		kfree(data->bps_bo);
++	}
+ 
+-	data->bps = tmp;
++	data->bps = bps;
++	data->bps_bo = bps_bo;
+ 	data->space_left += align_space - old_space;
+ 	return 0;
+ }
+ 
+ /* it deal with vram only. */
+ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
+-		unsigned long *bps, int pages)
++		struct eeprom_table_record *bps, int pages)
+ {
+ 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+ 	struct ras_err_handler_data *data;
+-	int i = pages;
+ 	int ret = 0;
+ 
+ 	if (!con || !con->eh_data || !bps || pages <= 0)
+@@ -1344,10 +1354,10 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
+ 			goto out;
+ 		}
+ 
+-	while (i--)
+-		data->bps[data->count++].bp = bps[i];
+-
++	memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps));
++	data->count += pages;
+ 	data->space_left -= pages;
++
+ out:
+ 	mutex_unlock(&con->recovery_lock);
+ 
+@@ -1372,13 +1382,13 @@ int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
+ 		goto out;
+ 	/* reserve vram at driver post stage. */
+ 	for (i = data->last_reserved; i < data->count; i++) {
+-		bp = data->bps[i].bp;
++		bp = data->bps[i].retired_page;
+ 
+ 		if (amdgpu_ras_reserve_vram(adev, bp << PAGE_SHIFT,
+ 					PAGE_SIZE, &bo))
+ 			DRM_ERROR("RAS ERROR: reserve vram %llx fail\n", bp);
+ 
+-		data->bps[i].bo = bo;
++		data->bps_bo[i] = bo;
+ 		data->last_reserved = i + 1;
+ 	}
+ out:
+@@ -1403,11 +1413,11 @@ static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev)
+ 		goto out;
+ 
+ 	for (i = data->last_reserved - 1; i >= 0; i--) {
+-		bo = data->bps[i].bo;
++		bo = data->bps_bo[i];
+ 
+ 		amdgpu_ras_release_vram(adev, &bo);
+ 
+-		data->bps[i].bo = bo;
++		data->bps_bo[i] = bo;
+ 		data->last_reserved = i;
+ 	}
+ out:
+@@ -1423,12 +1433,19 @@ static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
++/*
++ * read error record array in eeprom and reserve enough space for
++ * storing new bad pages
++ */
+ static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
+ {
+-	/* TODO
+-	 * read the array to eeprom when SMU disabled.
+-	 */
+-	return 0;
++	struct eeprom_table_record *bps = NULL;
++	int ret;
++
++	ret = amdgpu_ras_add_bad_pages(adev, bps,
++				adev->umc.max_ras_err_cnt_per_query);
++
++	return ret;
+ }
+ 
+ static int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index f487038ba331..bc1d45971607 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -351,11 +351,10 @@ struct ras_err_data {
+ };
+ 
+ struct ras_err_handler_data {
+-	/* point to bad pages array */
+-	struct {
+-		unsigned long bp;
+-		struct amdgpu_bo *bo;
+-	} *bps;
++	/* point to bad page records array */
++	struct eeprom_table_record *bps;
++	/* point to reserved bo array */
++	struct amdgpu_bo **bps_bo;
+ 	/* the count of entries */
+ 	int count;
+ 	/* the space can place new entries */
+@@ -492,7 +491,7 @@ unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
+ 
+ /* error handling functions */
+ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
+-		unsigned long *bps, int pages);
++		struct eeprom_table_record *bps, int pages);
+ 
+ int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3751-drm-amdgpu-Hook-EEPROM-table-to-RAS.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3751-drm-amdgpu-Hook-EEPROM-table-to-RAS.patch
new file mode 100644
index 00000000..907d2a11
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3751-drm-amdgpu-Hook-EEPROM-table-to-RAS.patch
@@ -0,0 +1,181 @@
+From 22b36201f07bdc613ce880ae7ddd3aebe1eb10a3 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 15 Aug 2019 14:55:55 +0800
+Subject: [PATCH 3751/4256] drm/amdgpu: Hook EEPROM table to RAS
+
+support eeprom records load and save for ras,
+move EEPROM records storing to bad page reserving
+
+v2: remove redundant check for con->eh_data
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 109 ++++++++++++++++++------
+ 1 file changed, 81 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index c6f4c01b98a8..e68f43d1cfea 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1364,6 +1364,69 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
+ 	return ret;
+ }
+ 
++/*
++ * write error record array to eeprom, the function should be
++ * protected by recovery_lock
++ */
++static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
++{
++	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
++	struct ras_err_handler_data *data;
++	struct amdgpu_ras_eeprom_control *control =
++					&adev->psp.ras.ras->eeprom_control;
++	int save_count;
++
++	if (!con || !con->eh_data)
++		return 0;
++
++	data = con->eh_data;
++	save_count = data->count - control->num_recs;
++	/* only new entries are saved */
++	if (save_count > 0)
++		if (amdgpu_ras_eeprom_process_recods(&con->eeprom_control,
++							&data->bps[control->num_recs],
++							true,
++							save_count)) {
++			DRM_ERROR("Failed to save EEPROM table data!");
++			return -EIO;
++		}
++
++	return 0;
++}
++
++/*
++ * read error record array in eeprom and reserve enough space for
++ * storing new bad pages
++ */
++static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
++{
++	struct amdgpu_ras_eeprom_control *control =
++					&adev->psp.ras.ras->eeprom_control;
++	struct eeprom_table_record *bps = NULL;
++	int ret = 0;
++
++	/* no bad page record, skip eeprom access */
++	if (!control->num_recs)
++		return ret;
++
++	bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL);
++	if (!bps)
++		return -ENOMEM;
++
++	if (amdgpu_ras_eeprom_process_recods(control, bps, false,
++		control->num_recs)) {
++		DRM_ERROR("Failed to load EEPROM table records!");
++		ret = -EIO;
++		goto out;
++	}
++
++	ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
++
++out:
++	kfree(bps);
++	return ret;
++}
++
+ /* called in gpu recovery/init */
+ int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
+ {
+@@ -1371,7 +1434,7 @@ int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
+ 	struct ras_err_handler_data *data;
+ 	uint64_t bp;
+ 	struct amdgpu_bo *bo;
+-	int i;
++	int i, ret = 0;
+ 
+ 	if (!con || !con->eh_data)
+ 		return 0;
+@@ -1391,9 +1454,12 @@ int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
+ 		data->bps_bo[i] = bo;
+ 		data->last_reserved = i + 1;
+ 	}
++
++	/* continue to save bad pages to eeprom even reesrve_vram fails */
++	ret = amdgpu_ras_save_bad_pages(adev);
+ out:
+ 	mutex_unlock(&con->recovery_lock);
+-	return 0;
++	return ret;
+ }
+ 
+ /* called when driver unload */
+@@ -1425,33 +1491,11 @@ static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
+-static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
+-{
+-	/* TODO
+-	 * write the array to eeprom when SMU disabled.
+-	 */
+-	return 0;
+-}
+-
+-/*
+- * read error record array in eeprom and reserve enough space for
+- * storing new bad pages
+- */
+-static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
+-{
+-	struct eeprom_table_record *bps = NULL;
+-	int ret;
+-
+-	ret = amdgpu_ras_add_bad_pages(adev, bps,
+-				adev->umc.max_ras_err_cnt_per_query);
+-
+-	return ret;
+-}
+-
+ static int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
+ {
+ 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+ 	struct ras_err_handler_data **data = &con->eh_data;
++	int ret;
+ 
+ 	*data = kmalloc(sizeof(**data),
+ 			GFP_KERNEL|__GFP_ZERO);
+@@ -1463,8 +1507,18 @@ static int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
+ 	atomic_set(&con->in_recovery, 0);
+ 	con->adev = adev;
+ 
+-	amdgpu_ras_load_bad_pages(adev);
+-	amdgpu_ras_reserve_bad_pages(adev);
++	ret = amdgpu_ras_eeprom_init(&adev->psp.ras.ras->eeprom_control);
++	if (ret)
++		return ret;
++
++	if (adev->psp.ras.ras->eeprom_control.num_recs) {
++		ret = amdgpu_ras_load_bad_pages(adev);
++		if (ret)
++			return ret;
++		ret = amdgpu_ras_reserve_bad_pages(adev);
++		if (ret)
++			return ret;
++	}
+ 
+ 	return 0;
+ }
+@@ -1475,7 +1529,6 @@ static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
+ 	struct ras_err_handler_data *data = con->eh_data;
+ 
+ 	cancel_work_sync(&con->recovery_work);
+-	amdgpu_ras_save_bad_pages(adev);
+ 	amdgpu_ras_release_bad_pages(adev);
+ 
+ 	mutex_lock(&con->recovery_lock);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3752-drm-amdgpu-save-umc-error-records.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3752-drm-amdgpu-save-umc-error-records.patch
new file mode 100644
index 00000000..eb253044
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3752-drm-amdgpu-save-umc-error-records.patch
@@ -0,0 +1,163 @@
+From c251a1c24acb293667147ac950d5800e07abb490 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 15 Aug 2019 16:15:08 +0800
+Subject: [PATCH 3752/4256] drm/amdgpu: save umc error records
+
+save umc error records to ras bad page array
+
+v2: add bad pages before gpu reset
+v3: add NULL check for adev->umc.funcs
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h |  2 +-
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 40 +++++++++++++++++++------
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.c   | 39 +++++++++++++++++++-----
+ 3 files changed, 64 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index bc1d45971607..96210e18191e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -347,7 +347,7 @@ struct ras_err_data {
+ 	unsigned long ue_count;
+ 	unsigned long ce_count;
+ 	unsigned long err_addr_cnt;
+-	uint64_t *err_addr;
++	struct eeprom_table_record *err_addr;
+ };
+ 
+ struct ras_err_handler_data {
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index d5c18deb407a..7a7068da02dd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -243,21 +243,43 @@ static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+ 		struct ras_err_data *err_data,
+ 		struct amdgpu_iv_entry *entry)
+ {
+-	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
+-		kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
+-		if (adev->umc.funcs->query_ras_error_count)
+-			adev->umc.funcs->query_ras_error_count(adev, err_data);
++	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
++		return AMDGPU_RAS_SUCCESS;
++
++	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
++	if (adev->umc.funcs &&
++	    adev->umc.funcs->query_ras_error_count)
++	    adev->umc.funcs->query_ras_error_count(adev, err_data);
++
++	if (adev->umc.funcs &&
++	    adev->umc.funcs->query_ras_error_address &&
++	    adev->umc.max_ras_err_cnt_per_query) {
++		err_data->err_addr =
++			kcalloc(adev->umc.max_ras_err_cnt_per_query,
++				sizeof(struct eeprom_table_record), GFP_KERNEL);
++		/* still call query_ras_error_address to clear error status
++		 * even NOMEM error is encountered
++		 */
++		if(!err_data->err_addr)
++			DRM_WARN("Failed to alloc memory for umc error address record!\n");
++
+ 		/* umc query_ras_error_address is also responsible for clearing
+ 		 * error status
+ 		 */
+-		if (adev->umc.funcs->query_ras_error_address)
+-			adev->umc.funcs->query_ras_error_address(adev, err_data);
++		adev->umc.funcs->query_ras_error_address(adev, err_data);
++	}
++
++	/* only uncorrectable error needs gpu reset */
++	if (err_data->ue_count) {
++		if (err_data->err_addr_cnt &&
++		    amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
++						err_data->err_addr_cnt))
++			DRM_WARN("Failed to add ras bad page!\n");
+ 
+-		/* only uncorrectable error needs gpu reset */
+-		if (err_data->ue_count)
+-			amdgpu_ras_reset_gpu(adev, 0);
++		amdgpu_ras_reset_gpu(adev, 0);
+ 	}
+ 
++	kfree(err_data->err_addr);
+ 	return AMDGPU_RAS_SUCCESS;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+index 8502e736f721..09e316a22f1a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+@@ -75,6 +75,17 @@ static void umc_v6_1_disable_umc_index_mode(struct amdgpu_device *adev)
+ 			RSMU_UMC_INDEX_MODE_EN, 0);
+ }
+ 
++static uint32_t umc_v6_1_get_umc_inst(struct amdgpu_device *adev)
++{
++	uint32_t rsmu_umc_index;
++
++	rsmu_umc_index = RREG32_SOC15(RSMU, 0,
++				mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU);
++	return REG_GET_FIELD(rsmu_umc_index,
++				RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
++				RSMU_UMC_INDEX_INSTANCE);
++}
++
+ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
+ 						   uint32_t umc_reg_offset,
+ 						   unsigned long *error_count)
+@@ -165,7 +176,8 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
+ 					 uint32_t umc_reg_offset, uint32_t channel_index)
+ {
+ 	uint32_t lsb, mc_umc_status_addr;
+-	uint64_t mc_umc_status, err_addr;
++	uint64_t mc_umc_status, err_addr, retired_page;
++	struct eeprom_table_record *err_rec;
+ 
+ 	mc_umc_status_addr =
+ 		SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
+@@ -177,6 +189,7 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
+ 		return;
+ 	}
+ 
++	err_rec = &err_data->err_addr[err_data->err_addr_cnt];
+ 	mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
+ 
+ 	/* calculate error address if ue/ce error is detected */
+@@ -191,12 +204,24 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
+ 		err_addr &= ~((0x1ULL << lsb) - 1);
+ 
+ 		/* translate umc channel address to soc pa, 3 parts are included */
+-		err_data->err_addr[err_data->err_addr_cnt] =
+-						ADDR_OF_8KB_BLOCK(err_addr) |
+-						ADDR_OF_256B_BLOCK(channel_index) |
+-						OFFSET_IN_256B_BLOCK(err_addr);
+-
+-		err_data->err_addr_cnt++;
++		retired_page = ADDR_OF_8KB_BLOCK(err_addr) |
++				ADDR_OF_256B_BLOCK(channel_index) |
++				OFFSET_IN_256B_BLOCK(err_addr);
++
++		/* we only save ue error information currently, ce is skipped */
++		if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)
++				== 1) {
++			err_rec->address = err_addr;
++			/* page frame address is saved */
++			err_rec->retired_page = retired_page >> PAGE_SHIFT;
++			err_rec->ts = (uint64_t)ktime_get_real_seconds();
++			err_rec->err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
++			err_rec->cu = 0;
++			err_rec->mem_channel = channel_index;
++			err_rec->mcumc_id = umc_v6_1_get_umc_inst(adev);
++
++			err_data->err_addr_cnt++;
++		}
+ 	}
+ 
+ 	/* clear umc status */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3753-drm-amdgpu-move-the-call-of-ras-recovery_init-and-ba.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3753-drm-amdgpu-move-the-call-of-ras-recovery_init-and-ba.patch
new file mode 100644
index 00000000..52387a9f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3753-drm-amdgpu-move-the-call-of-ras-recovery_init-and-ba.patch
@@ -0,0 +1,193 @@
+From 78f24d941619c851ff2d6fdbe68a390484b58573 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Fri, 30 Aug 2019 19:50:39 +0800
+Subject: [PATCH 3753/4256] drm/amdgpu: move the call of ras recovery_init and
+ bad page reserve to proper place
+
+ras recovery_init should be called after ttm init,
+bad page reserve should be put in front of gpu reset since i2c
+may be unstable during gpu reset.
+add cleanup for recovery_init and recovery_fini
+
+v2: add more comment and print.
+    remove cancel_work_sync in recovery_init.
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  5 ---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c    | 39 ++++++++++++++--------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h    |  5 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    | 12 +++++++
+ 4 files changed, 43 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index b29b26098b8f..92e01084911c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3619,11 +3619,6 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
+ 						break;
+ 				}
+ 			}
+-
+-			list_for_each_entry(tmp_adev, device_list_handle,
+-					gmc.xgmi.head) {
+-				amdgpu_ras_reserve_bad_pages(tmp_adev);
+-			}
+ 		}
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index e68f43d1cfea..d2437e13a085 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1491,16 +1491,17 @@ static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
+-static int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
++int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
+ {
+ 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+ 	struct ras_err_handler_data **data = &con->eh_data;
+ 	int ret;
+ 
+-	*data = kmalloc(sizeof(**data),
+-			GFP_KERNEL|__GFP_ZERO);
+-	if (!*data)
+-		return -ENOMEM;
++	*data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
++	if (!*data) {
++		ret = -ENOMEM;
++		goto out;
++	}
+ 
+ 	mutex_init(&con->recovery_lock);
+ 	INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
+@@ -1509,18 +1510,30 @@ static int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
+ 
+ 	ret = amdgpu_ras_eeprom_init(&adev->psp.ras.ras->eeprom_control);
+ 	if (ret)
+-		return ret;
++		goto free;
+ 
+ 	if (adev->psp.ras.ras->eeprom_control.num_recs) {
+ 		ret = amdgpu_ras_load_bad_pages(adev);
+ 		if (ret)
+-			return ret;
++			goto free;
+ 		ret = amdgpu_ras_reserve_bad_pages(adev);
+ 		if (ret)
+-			return ret;
++			goto release;
+ 	}
+ 
+ 	return 0;
++
++release:
++	amdgpu_ras_release_bad_pages(adev);
++free:
++	con->eh_data = NULL;
++	kfree((*data)->bps);
++	kfree((*data)->bps_bo);
++	kfree(*data);
++out:
++	DRM_WARN("Failed to initialize ras recovery!\n");
++
++	return ret;
+ }
+ 
+ static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
+@@ -1528,12 +1541,17 @@ static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
+ 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+ 	struct ras_err_handler_data *data = con->eh_data;
+ 
++	/* recovery_init failed to init it, fini is useless */
++	if (!data)
++		return 0;
++
+ 	cancel_work_sync(&con->recovery_work);
+ 	amdgpu_ras_release_bad_pages(adev);
+ 
+ 	mutex_lock(&con->recovery_lock);
+ 	con->eh_data = NULL;
+ 	kfree(data->bps);
++	kfree(data->bps_bo);
+ 	kfree(data);
+ 	mutex_unlock(&con->recovery_lock);
+ 
+@@ -1625,9 +1643,6 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
+ 			return r;
+ 	}
+ 
+-	if (amdgpu_ras_recovery_init(adev))
+-		goto recovery_out;
+-
+ 	amdgpu_ras_mask &= AMDGPU_RAS_BLOCK_MASK;
+ 
+ 	if (amdgpu_ras_fs_init(adev))
+@@ -1642,8 +1657,6 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
+ 			con->hw_supported, con->supported);
+ 	return 0;
+ fs_out:
+-	amdgpu_ras_recovery_fini(adev);
+-recovery_out:
+ 	amdgpu_ras_set_context(adev, NULL);
+ 	kfree(con);
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index 96210e18191e..012034d2ae06 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -480,6 +480,7 @@ static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev,
+ 	return ras && (ras->supported & (1 << block));
+ }
+ 
++int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
+ int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
+ 		unsigned int block);
+ 
+@@ -500,6 +501,10 @@ static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev,
+ {
+ 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+ 
++	/* save bad page to eeprom before gpu reset,
++	 * i2c may be unstable in gpu reset
++	 */
++	amdgpu_ras_reserve_bad_pages(adev);
+ 	if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
+ 		schedule_work(&ras->recovery_work);
+ 	return 0;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 7377bff42335..7c3025abd387 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -49,6 +49,7 @@
+ #include "amdgpu_trace.h"
+ #include "amdgpu_amdkfd.h"
+ #include "amdgpu_sdma.h"
++#include "amdgpu_ras.h"
+ #include "bif/bif_4_1_d.h"
+ #include "amdgpu_amdkfd.h"
+ 
+@@ -2090,6 +2091,17 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
+ 						adev->gmc.visible_vram_size);
+ #endif
+ 
++	/*
++	 * retired pages will be loaded from eeprom and reserved here,
++	 * it should be called after ttm init since new bo may be created,
++	 * recovery_init may fail, but it can free all resources allocated by
++	 * itself and its failure should not stop amdgpu init process.
++	 *
++	 * Note: theoretically, this should be called before all vram allocations
++	 * to protect retired page from abusing
++	 */
++	amdgpu_ras_recovery_init(adev);
++
+ 	/*
+ 	 *The reserved vram for firmware must be pinned to the specified
+ 	 *place on the VRAM, so reserve it early.
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3754-drm-amdgpu-enable-TA-load-support-in-Arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3754-drm-amdgpu-enable-TA-load-support-in-Arcturus.patch
new file mode 100644
index 00000000..2d636e0d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3754-drm-amdgpu-enable-TA-load-support-in-Arcturus.patch
@@ -0,0 +1,45 @@
+From 6f8bae668dfb7431a6f61c38dabb8e29f56cc97d Mon Sep 17 00:00:00 2001
+From: John Clements <john.clements@amd.com>
+Date: Wed, 4 Sep 2019 16:23:08 +0800
+Subject: [PATCH 3754/4256] drm/amdgpu: enable TA load support in Arcturus
+
+Add support for loading XGMI/RAS FW
+
+Change-Id: I391f58fd461fd3f00edd074ba99f47bd5f8afe1a
+Signed-off-by: John Clements <john.clements@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index 247a7aebb273..9d5d44cfe813 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -48,6 +48,7 @@ MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
+ MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
+ MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
+ MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
++MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
+ 
+ /* address block */
+ #define smnMP1_FIRMWARE_FLAGS		0x3010024
+@@ -163,6 +164,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_VEGA20:
++	case CHIP_ARCTURUS:
+ 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
+ 		err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
+ 		if (err) {
+@@ -190,7 +192,6 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+ 	case CHIP_NAVI12:
+-	case CHIP_ARCTURUS:
+ 		break;
+ 	default:
+ 		BUG();
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3755-drm-amd-powerplay-Add-the-interface-for-geting-dpm-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3755-drm-amd-powerplay-Add-the-interface-for-geting-dpm-c.patch
new file mode 100644
index 00000000..6c3b21b0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3755-drm-amd-powerplay-Add-the-interface-for-geting-dpm-c.patch
@@ -0,0 +1,69 @@
+From e07946a6c24cbffb845fed15ba3f75b4edeae673 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Fri, 6 Sep 2019 15:13:03 +0800
+Subject: [PATCH 3755/4256] drm/amd/powerplay: Add the interface for geting dpm
+ current power state
+
+implement the sysfs power_dpm_state
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 34 ++++++++++++++++++++++
+ 1 file changed, 34 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index a5cf846b50d4..2c22ba49c453 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -246,6 +246,38 @@ static int renoir_print_clk_levels(struct smu_context *smu,
+ 	return size;
+ }
+ 
++static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu)
++{
++	enum amd_pm_state_type pm_type;
++	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
++
++	if (!smu_dpm_ctx->dpm_context ||
++	    !smu_dpm_ctx->dpm_current_power_state)
++		return -EINVAL;
++
++	mutex_lock(&(smu->mutex));
++	switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
++	case SMU_STATE_UI_LABEL_BATTERY:
++		pm_type = POWER_STATE_TYPE_BATTERY;
++		break;
++	case SMU_STATE_UI_LABEL_BALLANCED:
++		pm_type = POWER_STATE_TYPE_BALANCED;
++		break;
++	case SMU_STATE_UI_LABEL_PERFORMANCE:
++		pm_type = POWER_STATE_TYPE_PERFORMANCE;
++		break;
++	default:
++		if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
++			pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
++		else
++			pm_type = POWER_STATE_TYPE_DEFAULT;
++		break;
++	}
++	mutex_unlock(&(smu->mutex));
++
++	return pm_type;
++}
++
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_smu_msg_index = renoir_get_smu_msg_index,
+ 	.get_smu_table_index = renoir_get_smu_table_index,
+@@ -253,6 +285,8 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.set_power_state = NULL,
+ 	.get_dpm_uclk_limited = renoir_get_dpm_uclk_limited,
+ 	.print_clk_levels = renoir_print_clk_levels,
++	.get_current_power_state = renoir_get_current_power_state,
++
+ };
+ 
+ void renoir_set_ppt_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3756-drm-amd-powerplay-issue-DC-BTC-for-arcturus-on-SMU-i.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3756-drm-amd-powerplay-issue-DC-BTC-for-arcturus-on-SMU-i.patch
new file mode 100644
index 00000000..6990a57e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3756-drm-amd-powerplay-issue-DC-BTC-for-arcturus-on-SMU-i.patch
@@ -0,0 +1,144 @@
+From 725eea9c1cf61a57b9d0fa26b713415681df6c73 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 5 Sep 2019 12:22:42 +0800
+Subject: [PATCH 3756/4256] drm/amd/powerplay: issue DC-BTC for arcturus on SMU
+ init
+
+Need to perform DC-BTC for arcturus on bootup.
+
+Change-Id: I7f048ba17cafe8909c5ee1e00830e4f8527d1a05
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c      |  4 ++--
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c    | 17 ++++++++++++-----
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h  |  6 +++---
+ .../gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h  |  3 +--
+ drivers/gpu/drm/amd/powerplay/inc/smu_types.h   |  1 +
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c      |  2 +-
+ 6 files changed, 20 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index e53ea7b9e8f9..e18bfce25dfa 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1079,8 +1079,8 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ 	if (ret)
+ 		return ret;
+ 
+-	/* issue RunAfllBtc msg */
+-	ret = smu_run_afll_btc(smu);
++	/* issue Run*Btc msg */
++	ret = smu_run_btc(smu);
+ 	if (ret)
+ 		return ret;
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index f2be65928237..1433bd3129a4 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -112,8 +112,7 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT]
+ 	MSG_MAP(PrepareMp1ForShutdown,		     PPSMC_MSG_PrepareMp1ForShutdown),
+ 	MSG_MAP(SoftReset,			     PPSMC_MSG_SoftReset),
+ 	MSG_MAP(RunAfllBtc,			     PPSMC_MSG_RunAfllBtc),
+-	MSG_MAP(RunGfxDcBtc,			     PPSMC_MSG_RunGfxDcBtc),
+-	MSG_MAP(RunSocDcBtc,			     PPSMC_MSG_RunSocDcBtc),
++	MSG_MAP(RunDcBtc,			     PPSMC_MSG_RunDcBtc),
+ 	MSG_MAP(DramLogSetDramAddrHigh,		     PPSMC_MSG_DramLogSetDramAddrHigh),
+ 	MSG_MAP(DramLogSetDramAddrLow,		     PPSMC_MSG_DramLogSetDramAddrLow),
+ 	MSG_MAP(DramLogSetDramSize,		     PPSMC_MSG_DramLogSetDramSize),
+@@ -528,9 +527,17 @@ static int arcturus_append_powerplay_table(struct smu_context *smu)
+ 	return 0;
+ }
+ 
+-static int arcturus_run_btc_afll(struct smu_context *smu)
++static int arcturus_run_btc(struct smu_context *smu)
+ {
+-	return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
++	int ret = 0;
++
++	ret = smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
++	if (ret) {
++		pr_err("RunAfllBtc failed!\n");
++		return ret;
++	}
++
++	return smu_send_smc_msg(smu, SMU_MSG_RunDcBtc);
+ }
+ 
+ static int arcturus_populate_umd_state_clk(struct smu_context *smu)
+@@ -1907,7 +1914,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 	/* init dpm */
+ 	.get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
+ 	/* btc */
+-	.run_afll_btc = arcturus_run_btc_afll,
++	.run_btc = arcturus_run_btc,
+ 	/* dpm/clk tables */
+ 	.set_default_dpm_table = arcturus_set_default_dpm_table,
+ 	.populate_umd_state_clk = arcturus_populate_umd_state_clk,
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index e1237ea8844c..88f1ee9a2f1d 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -396,7 +396,7 @@ struct pptable_funcs {
+ 	int (*get_smu_table_index)(struct smu_context *smu, uint32_t index);
+ 	int (*get_smu_power_index)(struct smu_context *smu, uint32_t index);
+ 	int (*get_workload_type)(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile);
+-	int (*run_afll_btc)(struct smu_context *smu);
++	int (*run_btc)(struct smu_context *smu);
+ 	int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
+ 	enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
+ 	int (*set_default_dpm_table)(struct smu_context *smu);
+@@ -696,8 +696,8 @@ struct smu_funcs
+ 	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_power_index? (smu)->ppt_funcs->get_smu_power_index((smu), (src)) : -EINVAL) : -EINVAL)
+ #define smu_workload_get_type(smu, profile) \
+ 	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_workload_type? (smu)->ppt_funcs->get_workload_type((smu), (profile)) : -EINVAL) : -EINVAL)
+-#define smu_run_afll_btc(smu) \
+-	((smu)->ppt_funcs? ((smu)->ppt_funcs->run_afll_btc? (smu)->ppt_funcs->run_afll_btc((smu)) : 0) : 0)
++#define smu_run_btc(smu) \
++	((smu)->ppt_funcs? ((smu)->ppt_funcs->run_btc? (smu)->ppt_funcs->run_btc((smu)) : 0) : 0)
+ #define smu_get_allowed_feature_mask(smu, feature_mask, num) \
+ 	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
+ #define smu_set_deep_sleep_dcefclk(smu, clk) \
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h
+index 78e5927b7711..e3291259b249 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h
+@@ -95,8 +95,7 @@
+ 
+ //BTC
+ #define PPSMC_MSG_RunAfllBtc                     0x30
+-#define PPSMC_MSG_RunGfxDcBtc                    0x31
+-#define PPSMC_MSG_RunSocDcBtc                    0x32
++#define PPSMC_MSG_RunDcBtc                       0x31
+ 
+ //Debug
+ #define PPSMC_MSG_DramLogSetDramAddrHigh         0x33
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+index b0dd05d431dd..ab8c92a60fc4 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+@@ -114,6 +114,7 @@
+        __SMU_DUMMY_MAP(PowerDownJpeg),                \
+        __SMU_DUMMY_MAP(BacoAudioD3PME),               \
+        __SMU_DUMMY_MAP(ArmD3),                        \
++       __SMU_DUMMY_MAP(RunDcBtc),                     \
+        __SMU_DUMMY_MAP(RunGfxDcBtc),                  \
+        __SMU_DUMMY_MAP(RunSocDcBtc),                  \
+        __SMU_DUMMY_MAP(SetMemoryChannelEnable),       \
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 929f61891dfa..e9ecc3f7aab1 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -3145,7 +3145,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
+ 	.get_smu_table_index = vega20_get_smu_table_index,
+ 	.get_smu_power_index = vega20_get_pwr_src_index,
+ 	.get_workload_type = vega20_get_workload_type,
+-	.run_afll_btc = vega20_run_btc_afll,
++	.run_btc = vega20_run_btc_afll,
+ 	.get_allowed_feature_mask = vega20_get_allowed_feature_mask,
+ 	.get_current_power_state = vega20_get_current_power_state,
+ 	.set_default_dpm_table = vega20_set_default_dpm_table,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3757-drm-amdgpu-add-firmware-header-printing-for-psp-fw-l.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3757-drm-amdgpu-add-firmware-header-printing-for-psp-fw-l.patch
new file mode 100644
index 00000000..6cbd6cb5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3757-drm-amdgpu-add-firmware-header-printing-for-psp-fw-l.patch
@@ -0,0 +1,90 @@
+From fbd68c2a230e881accece28476734e597a534693 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 15 Aug 2019 17:44:22 +0800
+Subject: [PATCH 3757/4256] drm/amdgpu: add firmware header printing for psp fw
+ loading
+
+firmware header information is printed for direct fw loading but not
+added for psp fw loading yet
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 54 +++++++++++++++++++++++++
+ 1 file changed, 54 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 52b02ce626e1..e50dd3c320c5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -942,6 +942,58 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
+ 	return 0;
+ }
+ 
++static void psp_print_fw_hdr(struct psp_context *psp,
++			     struct amdgpu_firmware_info *ucode)
++{
++	struct amdgpu_device *adev = psp->adev;
++	const struct sdma_firmware_header_v1_0 *sdma_hdr =
++		(const struct sdma_firmware_header_v1_0 *)
++		adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
++	const struct gfx_firmware_header_v1_0 *ce_hdr =
++		(const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
++	const struct gfx_firmware_header_v1_0 *pfp_hdr =
++		(const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
++	const struct gfx_firmware_header_v1_0 *me_hdr =
++		(const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
++	const struct gfx_firmware_header_v1_0 *mec_hdr =
++		(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
++	const struct rlc_firmware_header_v2_0 *rlc_hdr =
++		(const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
++	const struct smc_firmware_header_v1_0 *smc_hdr =
++		(const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
++
++	switch (ucode->ucode_id) {
++	case AMDGPU_UCODE_ID_SDMA0:
++	case AMDGPU_UCODE_ID_SDMA1:
++	case AMDGPU_UCODE_ID_SDMA2:
++	case AMDGPU_UCODE_ID_SDMA3:
++	case AMDGPU_UCODE_ID_SDMA4:
++	case AMDGPU_UCODE_ID_SDMA5:
++	case AMDGPU_UCODE_ID_SDMA6:
++	case AMDGPU_UCODE_ID_SDMA7:
++		amdgpu_ucode_print_sdma_hdr(&sdma_hdr->header);
++		break;
++	case AMDGPU_UCODE_ID_CP_CE:
++		amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
++		break;
++	case AMDGPU_UCODE_ID_CP_PFP:
++		amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
++		break;
++	case AMDGPU_UCODE_ID_CP_ME:
++		amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
++		break;
++	case AMDGPU_UCODE_ID_CP_MEC1:
++		amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
++		break;
++	case AMDGPU_UCODE_ID_RLC_G:
++		amdgpu_ucode_print_rlc_hdr(&rlc_hdr->header);
++		break;
++	case AMDGPU_UCODE_ID_SMC:
++		amdgpu_ucode_print_smc_hdr(&smc_hdr->header);
++		break;
++	}
++}
++
+ static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
+ 				       struct psp_gfx_cmd_resp *cmd)
+ {
+@@ -1026,6 +1078,8 @@ static int psp_np_fw_load(struct psp_context *psp)
+ 		    ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)
+ 			continue;
+ 
++		psp_print_fw_hdr(psp, ucode);
++
+ 		ret = psp_execute_np_fw_load(psp, ucode);
+ 		if (ret)
+ 			return ret;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3758-drm-amdgpu-fix-null-pointer-deref-in-firmware-header.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3758-drm-amdgpu-fix-null-pointer-deref-in-firmware-header.patch
new file mode 100644
index 00000000..b1cf14a2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3758-drm-amdgpu-fix-null-pointer-deref-in-firmware-header.patch
@@ -0,0 +1,145 @@
+From dea56671177e59f4c9445e2c5b1534e215d8a395 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 5 Sep 2019 16:50:22 +0800
+Subject: [PATCH 3758/4256] drm/amdgpu: fix null pointer deref in firmware
+ header printing
+
+v2: declare as (struct common_firmware_header *) type because
+    struct xxx_firmware_header inherits from it
+
+When CE's ucode_id(8) is used to get sdma_hdr, we will be accessing an
+unallocated amdgpu_firmware_info instance.
+
+This issue appears on rhel7.7 with gcc 4.8.5. Newer compilers might have
+optimized out such 'defined but not referenced' variable.
+
+[ 1120.798564] BUG: unable to handle kernel NULL pointer dereference at 000000000000000a
+[ 1120.806703] IP: [<ffffffffc0e3c9b3>] psp_np_fw_load+0x1e3/0x390 [amdgpu]
+[ 1120.813693] PGD 80000002603ff067 PUD 271b8d067 PMD 0
+[ 1120.818931] Oops: 0000 [#1] SMP
+[ 1120.822245] Modules linked in: amdgpu(OE+) amdkcl(OE) amd_iommu_v2 amdttm(OE) amd_sched(OE) xt_CHECKSUM ipt_MASQUERADE nf_nat_masquerade_ipv4 tun bridge stp llc devlink ip6t_rpfilter ip6t_REJECT nf_reject_ipv6 ipt_REJECT nf_reject_ipv4 xt_conntrack ebtable_nat ip6table_nat nf_conntrack_ipv6 nf_defrag_ipv6 nf_nat_ipv6 ip6table_mangle ip6table_security ip6table_raw iptable_nat nf_conntrack_ipv4 nf_defrag_ipv4 nf_nat_ipv4 nf_nat iptable_mangle iptable_security iptable_raw nf_conntrack libcrc32c ip_set nfnetlink ebtable_filter ebtables ip6table_filter ip6_tables iptable_filter sunrpc dm_mirror dm_region_hash dm_log dm_mod intel_pmc_core intel_powerclamp coretemp intel_rapl joydev kvm_intel eeepc_wmi asus_wmi kvm sparse_keymap iTCO_wdt irqbypass rfkill crc32_pclmul snd_hda_codec_realtek mxm_wmi ghash_clmulni_intel intel_wmi_thunderbolt iTCO_vendor_support snd_hda_codec_generic snd_hda_codec_hdmi aesni_intel lrw gf128mul glue_helper ablk_helper sg cryptd pcspkr snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_seq snd_seq_device snd_pcm snd_timer snd pinctrl_sunrisepoint pinctrl_intel soundcore acpi_pad mei_me wmi mei i2c_i801 pcc_cpufreq ip_tables ext4 mbcache jbd2 sd_mod crc_t10dif crct10dif_generic i915 i2c_algo_bit iosf_mbi drm_kms_helper e1000e syscopyarea sysfillrect sysimgblt fb_sys_fops ahci libahci drm ptp libata crct10dif_pclmul crct10dif_common crc32c_intel serio_raw pps_core drm_panel_orientation_quirks video i2c_hid
+[ 1120.954136] CPU: 4 PID: 2426 Comm: modprobe Tainted: G           OE  ------------   3.10.0-1062.el7.x86_64 #1
+[ 1120.964390] Hardware name: System manufacturer System Product Name/Z170-A, BIOS 1302 11/09/2015
+[ 1120.973321] task: ffff991ef1e3c1c0 ti: ffff991ee625c000 task.ti: ffff991ee625c000
+[ 1120.981020] RIP: 0010:[<ffffffffc0e3c9b3>]  [<ffffffffc0e3c9b3>] psp_np_fw_load+0x1e3/0x390 [amdgpu]
+[ 1120.990483] RSP: 0018:ffff991ee625f950  EFLAGS: 00010202
+[ 1120.995935] RAX: 0000000000000002 RBX: ffff991edf6b2d38 RCX: ffff991edf6a0000
+[ 1121.003391] RDX: 0000000000000000 RSI: ffff991f01d13898 RDI: ffffffffc110afb3
+[ 1121.010706] RBP: ffff991ee625f9b0 R08: 0000000000000000 R09: 0000000000000000
+[ 1121.018029] R10: 00000000000004c4 R11: ffff991ee625f64e R12: ffff991edf6b3220
+[ 1121.025353] R13: ffff991edf6a0000 R14: 0000000000000008 R15: ffff991edf6b2d30
+[ 1121.032666] FS:  00007f97b0c0b740(0000) GS:ffff991f01d00000(0000) knlGS:0000000000000000
+[ 1121.041000] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+[ 1121.046880] CR2: 000000000000000a CR3: 000000025e604000 CR4: 00000000003607e0
+[ 1121.054239] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
+[ 1121.061631] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
+[ 1121.068938] Call Trace:
+[ 1121.071494]  [<ffffffffc0e3dba8>] psp_hw_init+0x218/0x270 [amdgpu]
+[ 1121.077886]  [<ffffffffc0da3188>] amdgpu_device_fw_loading+0xe8/0x160 [amdgpu]
+[ 1121.085296]  [<ffffffffc0e3b34c>] ? vega10_ih_irq_init+0x4bc/0x730 [amdgpu]
+[ 1121.092534]  [<ffffffffc0da5c75>] amdgpu_device_init+0x1495/0x1c90 [amdgpu]
+[ 1121.099675]  [<ffffffffc0da9cab>] amdgpu_driver_load_kms+0x8b/0x2f0 [amdgpu]
+[ 1121.106888]  [<ffffffffc01b25cf>] drm_dev_register+0x12f/0x1d0 [drm]
+[ 1121.113419]  [<ffffffffa4dcdfd8>] ? pci_enable_device_flags+0xe8/0x140
+[ 1121.120183]  [<ffffffffc0da260a>] amdgpu_pci_probe+0xca/0x170 [amdgpu]
+[ 1121.126919]  [<ffffffffa4dcf97a>] local_pci_probe+0x4a/0xb0
+[ 1121.132622]  [<ffffffffa4dd10c9>] pci_device_probe+0x109/0x160
+[ 1121.138607]  [<ffffffffa4eb4205>] driver_probe_device+0xc5/0x3e0
+[ 1121.144766]  [<ffffffffa4eb4603>] __driver_attach+0x93/0xa0
+[ 1121.150507]  [<ffffffffa4eb4570>] ? __device_attach+0x50/0x50
+[ 1121.156422]  [<ffffffffa4eb1da5>] bus_for_each_dev+0x75/0xc0
+[ 1121.162213]  [<ffffffffa4eb3b7e>] driver_attach+0x1e/0x20
+[ 1121.167771]  [<ffffffffa4eb3620>] bus_add_driver+0x200/0x2d0
+[ 1121.173590]  [<ffffffffa4eb4c94>] driver_register+0x64/0xf0
+[ 1121.179345]  [<ffffffffa4dd0905>] __pci_register_driver+0xa5/0xc0
+[ 1121.185593]  [<ffffffffc099f000>] ? 0xffffffffc099efff
+[ 1121.190914]  [<ffffffffc099f0a4>] amdgpu_init+0xa4/0xb0 [amdgpu]
+[ 1121.197101]  [<ffffffffa4a0210a>] do_one_initcall+0xba/0x240
+[ 1121.202901]  [<ffffffffa4b1c90a>] load_module+0x271a/0x2bb0
+[ 1121.208598]  [<ffffffffa4dad740>] ? ddebug_proc_write+0x100/0x100
+[ 1121.214894]  [<ffffffffa4b1ce8f>] SyS_init_module+0xef/0x140
+[ 1121.220698]  [<ffffffffa518bede>] system_call_fastpath+0x25/0x2a
+[ 1121.226870] Code: b4 01 60 a2 00 00 31 c0 e8 83 60 33 e4 41 8b 47 08 48 8b 4d d0 48 c7 c7 b3 af 10 c1 48 69 c0 68 07 00 00 48 8b 84 01 60 a2 00 00 <48> 8b 70 08 31 c0 48 89 75 c8 e8 56 60 33 e4 48 8b 4d d0 48 c7
+[ 1121.247422] RIP  [<ffffffffc0e3c9b3>] psp_np_fw_load+0x1e3/0x390 [amdgpu]
+[ 1121.254432]  RSP <ffff991ee625f950>
+[ 1121.258017] CR2: 000000000000000a
+[ 1121.261427] ---[ end trace e98b35387ede75bd ]---
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Fixes: 5206b0e79cfe ("drm/amdgpu: add firmware header printing for psp fw loading")
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 38 +++++++++++--------------
+ 1 file changed, 16 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index e50dd3c320c5..b45216c37aeb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -946,21 +946,7 @@ static void psp_print_fw_hdr(struct psp_context *psp,
+ 			     struct amdgpu_firmware_info *ucode)
+ {
+ 	struct amdgpu_device *adev = psp->adev;
+-	const struct sdma_firmware_header_v1_0 *sdma_hdr =
+-		(const struct sdma_firmware_header_v1_0 *)
+-		adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
+-	const struct gfx_firmware_header_v1_0 *ce_hdr =
+-		(const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
+-	const struct gfx_firmware_header_v1_0 *pfp_hdr =
+-		(const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
+-	const struct gfx_firmware_header_v1_0 *me_hdr =
+-		(const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
+-	const struct gfx_firmware_header_v1_0 *mec_hdr =
+-		(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
+-	const struct rlc_firmware_header_v2_0 *rlc_hdr =
+-		(const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
+-	const struct smc_firmware_header_v1_0 *smc_hdr =
+-		(const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
++	struct common_firmware_header *hdr;
+ 
+ 	switch (ucode->ucode_id) {
+ 	case AMDGPU_UCODE_ID_SDMA0:
+@@ -971,25 +957,33 @@ static void psp_print_fw_hdr(struct psp_context *psp,
+ 	case AMDGPU_UCODE_ID_SDMA5:
+ 	case AMDGPU_UCODE_ID_SDMA6:
+ 	case AMDGPU_UCODE_ID_SDMA7:
+-		amdgpu_ucode_print_sdma_hdr(&sdma_hdr->header);
++		hdr = (struct common_firmware_header *)
++			adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
++		amdgpu_ucode_print_sdma_hdr(hdr);
+ 		break;
+ 	case AMDGPU_UCODE_ID_CP_CE:
+-		amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
++		hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
++		amdgpu_ucode_print_gfx_hdr(hdr);
+ 		break;
+ 	case AMDGPU_UCODE_ID_CP_PFP:
+-		amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
++		hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
++		amdgpu_ucode_print_gfx_hdr(hdr);
+ 		break;
+ 	case AMDGPU_UCODE_ID_CP_ME:
+-		amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
++		hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
++		amdgpu_ucode_print_gfx_hdr(hdr);
+ 		break;
+ 	case AMDGPU_UCODE_ID_CP_MEC1:
+-		amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
++		hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
++		amdgpu_ucode_print_gfx_hdr(hdr);
+ 		break;
+ 	case AMDGPU_UCODE_ID_RLC_G:
+-		amdgpu_ucode_print_rlc_hdr(&rlc_hdr->header);
++		hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
++		amdgpu_ucode_print_rlc_hdr(hdr);
+ 		break;
+ 	case AMDGPU_UCODE_ID_SMC:
+-		amdgpu_ucode_print_smc_hdr(&smc_hdr->header);
++		hdr = (struct common_firmware_header *)adev->pm.fw->data;
++		amdgpu_ucode_print_smc_hdr(hdr);
+ 		break;
+ 	}
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3759-drm-amdgpu-add-navi14-PCI-ID-for-work-station-SKU.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3759-drm-amdgpu-add-navi14-PCI-ID-for-work-station-SKU.patch
new file mode 100644
index 00000000..acbf8c07
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3759-drm-amdgpu-add-navi14-PCI-ID-for-work-station-SKU.patch
@@ -0,0 +1,30 @@
+From a7796882b3188342a554049b96e555d0d3d3e3f4 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Thu, 5 Sep 2019 15:28:57 +0800
+Subject: [PATCH 3759/4256] drm/amdgpu: add navi14 PCI ID for work station SKU
+
+Add the navi14 PCI device id.
+
+Change-Id: I96a8c892becaa8dcc7ad59dc80d047d3f755775f
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 511fd4649796..27828e432601 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1061,6 +1061,8 @@ static const struct pci_device_id pciidlist[] = {
+ 	{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
+ 	/* Navi14 */
+ 	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
++	{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
++	{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
+ 
+ 	/* Renoir */
+ 	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3760-drm-amdgpu-Avoid-RAS-recovery-init-when-no-RAS-suppo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3760-drm-amdgpu-Avoid-RAS-recovery-init-when-no-RAS-suppo.patch
new file mode 100644
index 00000000..b03837e2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3760-drm-amdgpu-Avoid-RAS-recovery-init-when-no-RAS-suppo.patch
@@ -0,0 +1,37 @@
+From 74fad849d83a60abc1692d5d278668d2f0e15bf4 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Fri, 6 Sep 2019 17:23:44 -0400
+Subject: [PATCH 3760/4256] drm/amdgpu: Avoid RAS recovery init when no RAS
+ support.
+
+Fixes driver load regression on APUs.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index d2437e13a085..119bedc9802a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1494,9 +1494,14 @@ static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev)
+ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
+ {
+ 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+-	struct ras_err_handler_data **data = &con->eh_data;
++	struct ras_err_handler_data **data;
+ 	int ret;
+ 
++	if (con)
++		data = &con->eh_data;
++	else
++		return 0;
++
+ 	*data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
+ 	if (!*data) {
+ 		ret = -ENOMEM;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3761-drm-amdgpu-psp-fix-warning-in-switch-statement.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3761-drm-amdgpu-psp-fix-warning-in-switch-statement.patch
new file mode 100644
index 00000000..015e1d81
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3761-drm-amdgpu-psp-fix-warning-in-switch-statement.patch
@@ -0,0 +1,28 @@
+From 5a183f691f07e7bfa577d3860f066c9903bb1abd Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 19 Aug 2019 08:30:38 -0500
+Subject: [PATCH 3761/4256] drm/amdgpu/psp: fix warning in switch statement
+
+Trivial.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index b45216c37aeb..a49b4ccd611e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -985,6 +985,8 @@ static void psp_print_fw_hdr(struct psp_context *psp,
+ 		hdr = (struct common_firmware_header *)adev->pm.fw->data;
+ 		amdgpu_ucode_print_smc_hdr(hdr);
+ 		break;
++	default:
++		break;
+ 	}
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3762-drm-amdgpu-fix-build-error-without-CONFIG_HSA_AMD.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3762-drm-amdgpu-fix-build-error-without-CONFIG_HSA_AMD.patch
new file mode 100644
index 00000000..7a0a8816
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3762-drm-amdgpu-fix-build-error-without-CONFIG_HSA_AMD.patch
@@ -0,0 +1,55 @@
+From 977264aed4e0866a522df9906846284b9059976b Mon Sep 17 00:00:00 2001
+From: Shirish S <shirish.s@amd.com>
+Date: Tue, 10 Sep 2019 12:45:01 +0530
+Subject: [PATCH 3762/4256] drm/amdgpu: fix build error without CONFIG_HSA_AMD
+
+If CONFIG_HSA_AMD is not set, build fails:
+
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.o: In function `amdgpu_device_ip_early_init':
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626: undefined reference to `sched_policy'
+
+Use CONFIG_HSA_AMD to guard this.
+
+Fixes: 1abb680ad371 ("drm/amdgpu: disable gfxoff while use no H/W scheduling policy")
+
+Signed-off-by: Shirish S <shirish.s@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 2 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++++-
+ 2 files changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 55e3d3e2e69c..2f6d165a1ac0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -173,7 +173,9 @@ extern int amdgpu_discovery;
+ extern int amdgpu_mes;
+ extern int amdgpu_noretry;
+ extern int amdgpu_force_asic_type;
++#ifdef CONFIG_HSA_AMD
+ extern int sched_policy;
++#endif
+ 
+ #ifdef CONFIG_DRM_AMDGPU_SI
+ extern int amdgpu_si_support;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 92e01084911c..8d113a29b0df 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1624,7 +1624,11 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
+ 	}
+ 
+ 	adev->pm.pp_feature = amdgpu_pp_feature_mask;
+-	if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
++	if (amdgpu_sriov_vf(adev)
++	    #ifdef CONFIG_HSA_AMD
++	    || sched_policy == KFD_SCHED_POLICY_NO_HWS
++	    #endif
++	    )
+ 		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ 
+ 	for (i = 0; i < adev->num_ip_blocks; i++) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3763-drm-amdgpu-remove-duplicated-header-file-include.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3763-drm-amdgpu-remove-duplicated-header-file-include.patch
new file mode 100644
index 00000000..31cca761
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3763-drm-amdgpu-remove-duplicated-header-file-include.patch
@@ -0,0 +1,31 @@
+From f99fc233a2b180ce4cc1be8b9f2bdec1a7066bfa Mon Sep 17 00:00:00 2001
+From: Guchun Chen <guchun.chen@amd.com>
+Date: Tue, 10 Sep 2019 16:23:53 +0800
+Subject: [PATCH 3763/4256] drm/amdgpu: remove duplicated header file include
+
+amdgpu_ras.h is already included.
+
+Fixes: b1718da (dmr/amdgpu: Avoid HW GPU reset for RAS.)
+
+Change-Id: I4cf1eb5393d80c42b426dc1ddfc696e486a02c6f
+Signed-off-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index bfa919190fb4..2d171bf07ad5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -30,7 +30,6 @@
+ #include "nbio/nbio_7_4_0_smn.h"
+ #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
+ #include <uapi/linux/kfd_ioctl.h>
+-#include "amdgpu_ras.h"
+ 
+ #define smnNBIF_MGCG_CTRL_LCLK	0x1013a21c
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3764-drm-amdgpu-move-umc-late-init-from-gmc-to-umc-block.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3764-drm-amdgpu-move-umc-late-init-from-gmc-to-umc-block.patch
new file mode 100644
index 00000000..ea979341
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3764-drm-amdgpu-move-umc-late-init-from-gmc-to-umc-block.patch
@@ -0,0 +1,234 @@
+From ac4cd7c18c4e824da06d3a45b5ece553ea18d064 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 5 Sep 2019 19:16:19 +0800
+Subject: [PATCH 3764/4256] drm/amdgpu: move umc late init from gmc to umc
+ block
+
+umc late init is umc specific, it's more suitable to be put in umc block
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile     |  3 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 48 ----------------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  2 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 73 +++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h |  2 +
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |  8 ++-
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.c   |  1 +
+ 7 files changed, 83 insertions(+), 54 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index 655e5f0cf7b2..d3c2ccd8f98a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -55,7 +55,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
+ 	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
+ 	amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_sem.o \
+ 	amdgpu_ras.o amdgpu_vm_cpu.o amdgpu_vm_sdma.o amdgpu_pmu.o \
+-	amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o smu_v11_0_i2c.o
++	amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o amdgpu_umc.o \
++	smu_v11_0_i2c.o
+ 
+ amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+index 51890b1d8522..dc044eec188e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+@@ -304,51 +304,3 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
+ 	gmc->fault_hash[hash].idx = gmc->last_fault++;
+ 	return false;
+ }
+-
+-int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev,
+-			     void *ras_ih_info)
+-{
+-	int r;
+-	struct ras_ih_if *ih_info = (struct ras_ih_if *)ras_ih_info;
+-	struct ras_fs_if fs_info = {
+-		.sysfs_name = "umc_err_count",
+-		.debugfs_name = "umc_err_inject",
+-	};
+-
+-	if (!ih_info)
+-		return -EINVAL;
+-
+-	if (!adev->gmc.umc_ras_if) {
+-		adev->gmc.umc_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
+-		if (!adev->gmc.umc_ras_if)
+-			return -ENOMEM;
+-		adev->gmc.umc_ras_if->block = AMDGPU_RAS_BLOCK__UMC;
+-		adev->gmc.umc_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
+-		adev->gmc.umc_ras_if->sub_block_index = 0;
+-		strcpy(adev->gmc.umc_ras_if->name, "umc");
+-	}
+-	ih_info->head = fs_info.head = *adev->gmc.umc_ras_if;
+-
+-	r = amdgpu_ras_late_init(adev, adev->gmc.umc_ras_if,
+-				 &fs_info, ih_info);
+-	if (r)
+-		goto free;
+-
+-	if (amdgpu_ras_is_supported(adev, adev->gmc.umc_ras_if->block)) {
+-		r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
+-		if (r)
+-			goto late_fini;
+-	} else {
+-		r = 0;
+-		goto free;
+-	}
+-
+-	return 0;
+-
+-late_fini:
+-	amdgpu_ras_late_fini(adev, adev->gmc.umc_ras_if, ih_info);
+-free:
+-	kfree(adev->gmc.umc_ras_if);
+-	adev->gmc.umc_ras_if = NULL;
+-	return r;
+-}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+index 03687fa01817..e03351f0ba5a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+@@ -230,7 +230,5 @@ void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
+ 			     struct amdgpu_gmc *mc);
+ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
+ 			      uint16_t pasid, uint64_t timestamp);
+-int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev,
+-			     void *ih_info);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+new file mode 100644
+index 000000000000..c8de127097ab
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+@@ -0,0 +1,73 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include "amdgpu.h"
++#include "amdgpu_ras.h"
++
++int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_ih_info)
++{
++	int r;
++	struct ras_ih_if *ih_info = (struct ras_ih_if *)ras_ih_info;
++	struct ras_fs_if fs_info = {
++		.sysfs_name = "umc_err_count",
++		.debugfs_name = "umc_err_inject",
++	};
++
++	if (!ih_info)
++		return -EINVAL;
++
++	if (!adev->gmc.umc_ras_if) {
++		adev->gmc.umc_ras_if =
++			kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++		if (!adev->gmc.umc_ras_if)
++			return -ENOMEM;
++		adev->gmc.umc_ras_if->block = AMDGPU_RAS_BLOCK__UMC;
++		adev->gmc.umc_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++		adev->gmc.umc_ras_if->sub_block_index = 0;
++		strcpy(adev->gmc.umc_ras_if->name, "umc");
++	}
++	ih_info->head = fs_info.head = *adev->gmc.umc_ras_if;
++
++	r = amdgpu_ras_late_init(adev, adev->gmc.umc_ras_if,
++				 &fs_info, ih_info);
++	if (r)
++		goto free;
++
++	if (amdgpu_ras_is_supported(adev, adev->gmc.umc_ras_if->block)) {
++		r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
++		if (r)
++			goto late_fini;
++	} else {
++		r = 0;
++		goto free;
++	}
++
++	return 0;
++
++late_fini:
++	amdgpu_ras_late_fini(adev, adev->gmc.umc_ras_if, ih_info);
++free:
++	kfree(adev->gmc.umc_ras_if);
++	adev->gmc.umc_ras_if = NULL;
++	return r;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+index 975afa04df09..6f22c9704555 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+@@ -55,6 +55,7 @@
+ 
+ struct amdgpu_umc_funcs {
+ 	void (*ras_init)(struct amdgpu_device *adev);
++	int (*ras_late_init)(struct amdgpu_device *adev, void *ras_ih_info);
+ 	void (*query_ras_error_count)(struct amdgpu_device *adev,
+ 					void *ras_error_status);
+ 	void (*query_ras_error_address)(struct amdgpu_device *adev,
+@@ -79,4 +80,5 @@ struct amdgpu_umc {
+ 	const struct amdgpu_umc_funcs *funcs;
+ };
+ 
++int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_ih_info);
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 7a7068da02dd..64cc3068873a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -793,9 +793,11 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ 		.cb = gmc_v9_0_process_ras_data_cb,
+ 	};
+ 
+-	r = amdgpu_gmc_ras_late_init(adev, &umc_ih_info);
+-	if (r)
+-		return r;
++	if (adev->umc.funcs && adev->umc.funcs->ras_late_init) {
++		r = adev->umc.funcs->ras_late_init(adev, &umc_ih_info);
++		if (r)
++			return r;
++	}
+ 
+ 	if (adev->mmhub_funcs && adev->mmhub_funcs->ras_late_init) {
+ 		r = adev->mmhub_funcs->ras_late_init(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+index 09e316a22f1a..4cdb5c04cd17 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+@@ -273,6 +273,7 @@ static void umc_v6_1_ras_init(struct amdgpu_device *adev)
+ 
+ const struct amdgpu_umc_funcs umc_v6_1_funcs = {
+ 	.ras_init = umc_v6_1_ras_init,
++	.ras_late_init = amdgpu_umc_ras_late_init,
+ 	.query_ras_error_count = umc_v6_1_query_ras_error_count,
+ 	.query_ras_error_address = umc_v6_1_query_ras_error_address,
+ 	.enable_umc_index_mode = umc_v6_1_enable_umc_index_mode,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3765-drm-amdgpu-move-umc-ras-init-to-umc-block.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3765-drm-amdgpu-move-umc-ras-init-to-umc-block.patch
new file mode 100644
index 00000000..40d556eb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3765-drm-amdgpu-move-umc-ras-init-to-umc-block.patch
@@ -0,0 +1,48 @@
+From 4a9b9fbbcc161b275bbe42fbb5e681a296e501bb Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 5 Sep 2019 19:25:18 +0800
+Subject: [PATCH 3765/4256] drm/amdgpu: move umc ras init to umc block
+
+move umc ras init from ras module to umc block, generic ras module
+should pay less attention to specific ras block.
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 4 ++++
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 119bedc9802a..a9aba06c9452 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1653,10 +1653,6 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
+ 	if (amdgpu_ras_fs_init(adev))
+ 		goto fs_out;
+ 
+-	/* ras init for each ras block */
+-	if (adev->umc.funcs->ras_init)
+-		adev->umc.funcs->ras_init(adev);
+-
+ 	DRM_INFO("RAS INFO: ras initialized successfully, "
+ 			"hardware ability[%x] ras_mask[%x]\n",
+ 			con->hw_supported, con->supported);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+index c8de127097ab..5683c51710aa 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+@@ -62,6 +62,10 @@ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_ih_info)
+ 		goto free;
+ 	}
+ 
++	/* ras init of specific umc version */
++	if (adev->umc.funcs && adev->umc.funcs->ras_init)
++		adev->umc.funcs->ras_init(adev);
++
+ 	return 0;
+ 
+ late_fini:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3766-drm-amdgpu-rename-umc-ras_init-to-err_cnt_init.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3766-drm-amdgpu-rename-umc-ras_init-to-err_cnt_init.patch
new file mode 100644
index 00000000..387a8363
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3766-drm-amdgpu-rename-umc-ras_init-to-err_cnt_init.patch
@@ -0,0 +1,79 @@
+From 6cc768df49a4153e6cc3563467163a0ad17f255e Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Fri, 6 Sep 2019 14:32:14 +0800
+Subject: [PATCH 3766/4256] drm/amdgpu: rename umc ras_init to err_cnt_init
+
+this interface is related to specific version of umc, distinguish it
+from ras_late_init
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 2 +-
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.c   | 8 ++++----
+ 3 files changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+index 5683c51710aa..c5d8b08af731 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+@@ -63,8 +63,8 @@ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_ih_info)
+ 	}
+ 
+ 	/* ras init of specific umc version */
+-	if (adev->umc.funcs && adev->umc.funcs->ras_init)
+-		adev->umc.funcs->ras_init(adev);
++	if (adev->umc.funcs && adev->umc.funcs->err_cnt_init)
++		adev->umc.funcs->err_cnt_init(adev);
+ 
+ 	return 0;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+index 6f22c9704555..3ec36d9e012a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+@@ -54,7 +54,7 @@
+ 	adev->umc.funcs->disable_umc_index_mode(adev);
+ 
+ struct amdgpu_umc_funcs {
+-	void (*ras_init)(struct amdgpu_device *adev);
++	void (*err_cnt_init)(struct amdgpu_device *adev);
+ 	int (*ras_late_init)(struct amdgpu_device *adev, void *ras_ih_info);
+ 	void (*query_ras_error_count)(struct amdgpu_device *adev,
+ 					void *ras_error_status);
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+index 4cdb5c04cd17..1c0da32c1561 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+@@ -234,7 +234,7 @@ static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
+ 	amdgpu_umc_for_each_channel(umc_v6_1_query_error_address);
+ }
+ 
+-static void umc_v6_1_ras_init_per_channel(struct amdgpu_device *adev,
++static void umc_v6_1_err_cnt_init_per_channel(struct amdgpu_device *adev,
+ 					 struct ras_err_data *err_data,
+ 					 uint32_t umc_reg_offset, uint32_t channel_index)
+ {
+@@ -264,15 +264,15 @@ static void umc_v6_1_ras_init_per_channel(struct amdgpu_device *adev,
+ 	WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
+ }
+ 
+-static void umc_v6_1_ras_init(struct amdgpu_device *adev)
++static void umc_v6_1_err_cnt_init(struct amdgpu_device *adev)
+ {
+ 	void *ras_error_status = NULL;
+ 
+-	amdgpu_umc_for_each_channel(umc_v6_1_ras_init_per_channel);
++	amdgpu_umc_for_each_channel(umc_v6_1_err_cnt_init_per_channel);
+ }
+ 
+ const struct amdgpu_umc_funcs umc_v6_1_funcs = {
+-	.ras_init = umc_v6_1_ras_init,
++	.err_cnt_init = umc_v6_1_err_cnt_init,
+ 	.ras_late_init = amdgpu_umc_ras_late_init,
+ 	.query_ras_error_count = umc_v6_1_query_ras_error_count,
+ 	.query_ras_error_address = umc_v6_1_query_ras_error_address,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3767-drm-amdgpu-Add-amdgpu_ras_eeprom_reset_table.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3767-drm-amdgpu-Add-amdgpu_ras_eeprom_reset_table.patch
new file mode 100644
index 00000000..ea6e1cd0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3767-drm-amdgpu-Add-amdgpu_ras_eeprom_reset_table.patch
@@ -0,0 +1,73 @@
+From 00f45d13fe2c5551d7e1cc74eaada5146e62ee37 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Mon, 9 Sep 2019 15:59:45 -0400
+Subject: [PATCH 3767/4256] drm/amdgpu: Add amdgpu_ras_eeprom_reset_table
+
+This will allow to reset the table on the fly.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c    | 25 +++++++++++++------
+ .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h    |  1 +
+ 2 files changed, 18 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+index 43dd4ab9b6d5..11a8445cf734 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+@@ -102,6 +102,22 @@ static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
+ 
+ static uint32_t  __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control);
+ 
++int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
++{
++	unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
++
++	hdr->header = EEPROM_TABLE_HDR_VAL;
++	hdr->version = EEPROM_TABLE_VER;
++	hdr->first_rec_offset = EEPROM_RECORD_START;
++	hdr->tbl_size = EEPROM_TABLE_HEADER_SIZE;
++
++	adev->psp.ras.ras->eeprom_control.tbl_byte_sum =
++			__calc_hdr_byte_sum(&adev->psp.ras.ras->eeprom_control);
++	return __update_table_header(control, buff);
++}
++
+ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
+ {
+ 	int ret = 0;
+@@ -149,14 +165,7 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
+ 	} else {
+ 		DRM_INFO("Creating new EEPROM table");
+ 
+-		hdr->header = EEPROM_TABLE_HDR_VAL;
+-		hdr->version = EEPROM_TABLE_VER;
+-		hdr->first_rec_offset = EEPROM_RECORD_START;
+-		hdr->tbl_size = EEPROM_TABLE_HEADER_SIZE;
+-
+-		adev->psp.ras.ras->eeprom_control.tbl_byte_sum =
+-				__calc_hdr_byte_sum(&adev->psp.ras.ras->eeprom_control);
+-		ret = __update_table_header(control, buff);
++		ret = amdgpu_ras_eeprom_reset_table(control);
+ 	}
+ 
+ 	/* Start inserting records from here */
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
+index 41f3fcb9a29b..622269957c1b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
+@@ -79,6 +79,7 @@ struct eeprom_table_record {
+ 
+ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control);
+ void amdgpu_ras_eeprom_fini(struct amdgpu_ras_eeprom_control *control);
++int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control);
+ 
+ int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
+ 					    struct eeprom_table_record *records,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3768-drm-amdgpu-Allow-to-reset-to-EERPOM-table.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3768-drm-amdgpu-Allow-to-reset-to-EERPOM-table.patch
new file mode 100644
index 00000000..6ce6f73a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3768-drm-amdgpu-Allow-to-reset-to-EERPOM-table.patch
@@ -0,0 +1,71 @@
+From 2f862e4caa1c7df5ed6a3254a7c925f0dcbf357f Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Mon, 9 Sep 2019 16:00:56 -0400
+Subject: [PATCH 3768/4256] drm/amdgpu: Allow to reset to EERPOM table.
+
+The table grows quickly during debug/development effort when
+multiple RAS errors are injected. Allow to avoid this by setting
+table header back to empty if needed.
+
+v2: Switch to debugfs entry instead of load time parameter.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 25 +++++++++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index a9aba06c9452..656e364a473d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -303,6 +303,22 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *
+ 	return size;
+ }
+ 
++/**
++ * DOC: AMDGPU RAS debugfs EEPROM table reset interface
++ *
++ * Usage: echo 1 > ../ras/ras_eeprom_reset will reset EEPROM table to 0 entries.
++ */
++static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf,
++		size_t size, loff_t *pos)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
++	int ret;
++
++	ret = amdgpu_ras_eeprom_reset_table(&adev->psp.ras.ras->eeprom_control);
++
++	return ret == 1 ? size : -EIO;
++}
++
+ static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
+ 	.owner = THIS_MODULE,
+ 	.read = NULL,
+@@ -310,6 +326,13 @@ static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
+ 	.llseek = default_llseek
+ };
+ 
++static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
++	.owner = THIS_MODULE,
++	.read = NULL,
++	.write = amdgpu_ras_debugfs_eeprom_write,
++	.llseek = default_llseek
++};
++
+ static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
+ 		struct device_attribute *attr, char *buf)
+ {
+@@ -951,6 +974,8 @@ static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
+ 	con->dir = debugfs_create_dir("ras", minor->debugfs_root);
+ 	con->ent = debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, con->dir,
+ 				       adev, &amdgpu_ras_debugfs_ctrl_ops);
++	con->ent = debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, con->dir,
++					       adev, &amdgpu_ras_debugfs_eeprom_ops);
+ }
+ 
+ void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3769-drm-amdgpu-adding-xgmi-error-monitoring.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3769-drm-amdgpu-adding-xgmi-error-monitoring.patch
new file mode 100644
index 00000000..c6781e07
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3769-drm-amdgpu-adding-xgmi-error-monitoring.patch
@@ -0,0 +1,82 @@
+From 26b13c50de6243cf9dfd22fbd21ed6f2216f753b Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Thu, 11 Jul 2019 13:14:02 -0400
+Subject: [PATCH 3769/4256] drm/amdgpu: adding xgmi error monitoring
+
+monitor xgmi errors via mc pie status through fica registers.
+
+Change-Id: Id80b6c2f635a294afe343cf55a03902e9a1787a5
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+Reviewed-by: Kent Russell <Kent.Russell@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 38 ++++++++++++++++++++++--
+ 1 file changed, 36 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+index 28273d961a1b..83be108f57bd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+@@ -25,7 +25,7 @@
+ #include "amdgpu.h"
+ #include "amdgpu_xgmi.h"
+ #include "amdgpu_smu.h"
+-
++#include "df/df_3_6_offset.h"
+ 
+ static DEFINE_MUTEX(xgmi_mutex);
+ 
+@@ -131,9 +131,37 @@ static ssize_t amdgpu_xgmi_show_device_id(struct device *dev,
+ 
+ }
+ 
++#define AMDGPU_XGMI_SET_FICAA(o)	((o) | 0x456801)
++static ssize_t amdgpu_xgmi_show_error(struct device *dev,
++				      struct device_attribute *attr,
++				      char *buf)
++{
++	struct drm_device *ddev = dev_get_drvdata(dev);
++	struct amdgpu_device *adev = ddev->dev_private;
++	uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in;
++	uint64_t fica_out;
++	unsigned int error_count = 0;
++
++	ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200);
++	ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208);
+ 
+-static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
++	fica_out = adev->df_funcs->get_fica(adev, ficaa_pie_ctl_in);
++	if (fica_out != 0x1f)
++		pr_err("xGMI error counters not enabled!\n");
++
++	fica_out = adev->df_funcs->get_fica(adev, ficaa_pie_status_in);
++
++	if ((fica_out & 0xffff) == 2)
++		error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63);
+ 
++	adev->df_funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);
++
++	return snprintf(buf, PAGE_SIZE, "%d\n", error_count);
++}
++
++
++static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
++static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL);
+ 
+ static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
+ 					 struct amdgpu_hive_info *hive)
+@@ -148,6 +176,12 @@ static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
+ 		return ret;
+ 	}
+ 
++	/* Create xgmi error file */
++	ret = device_create_file(adev->dev, &dev_attr_xgmi_error);
++	if (ret)
++		pr_err("failed to create xgmi_error\n");
++
++
+ 	/* Create sysfs link to hive info folder on the first device */
+ 	if (adev != hive->adev) {
+ 		ret = sysfs_create_link(&adev->dev->kobj, hive->kobj,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3770-drm-amdgpu-initialize-ras-structures-for-xgmi-block-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3770-drm-amdgpu-initialize-ras-structures-for-xgmi-block-.patch
new file mode 100644
index 00000000..81cd4625
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3770-drm-amdgpu-initialize-ras-structures-for-xgmi-block-.patch
@@ -0,0 +1,120 @@
+From e3a7a6666e4bc09e679b68a0dd43113e595c03c6 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Tue, 10 Sep 2019 11:13:39 +0800
+Subject: [PATCH 3770/4256] drm/amdgpu: initialize ras structures for xgmi
+ block (v2)
+
+init ras common interface and fs node for xgmi block
+
+v2: remove unnecessary physical node number check before
+invoking amdgpu_xgmi_ras_late_init
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h  |  1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 36 ++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h |  1 +
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c    |  4 ++-
+ 4 files changed, 41 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+index e03351f0ba5a..df012766d907 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+@@ -120,6 +120,7 @@ struct amdgpu_xgmi {
+ 	/* gpu list in the same hive */
+ 	struct list_head head;
+ 	bool supported;
++	struct ras_common_if *ras_if;
+ };
+ 
+ struct amdgpu_gmc {
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+index 83be108f57bd..0fa1d2416b57 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+@@ -25,6 +25,7 @@
+ #include "amdgpu.h"
+ #include "amdgpu_xgmi.h"
+ #include "amdgpu_smu.h"
++#include "amdgpu_ras.h"
+ #include "df/df_3_6_offset.h"
+ 
+ static DEFINE_MUTEX(xgmi_mutex);
+@@ -436,3 +437,38 @@ void amdgpu_xgmi_remove_device(struct amdgpu_device *adev)
+ 		mutex_unlock(&hive->hive_lock);
+ 	}
+ }
++
++int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev)
++{
++	int r;
++	struct ras_ih_if ih_info = {
++		.cb = NULL,
++	};
++	struct ras_fs_if fs_info = {
++		.sysfs_name = "xgmi_wafl_err_count",
++		.debugfs_name = "xgmi_wafl_err_inject",
++	};
++
++	if (!adev->gmc.xgmi.supported ||
++	    adev->gmc.xgmi.num_physical_nodes == 0)
++		return 0;
++
++	if (!adev->gmc.xgmi.ras_if) {
++		adev->gmc.xgmi.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++		if (!adev->gmc.xgmi.ras_if)
++			return -ENOMEM;
++		adev->gmc.xgmi.ras_if->block = AMDGPU_RAS_BLOCK__XGMI_WAFL;
++		adev->gmc.xgmi.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++		adev->gmc.xgmi.ras_if->sub_block_index = 0;
++		strcpy(adev->gmc.xgmi.ras_if->name, "xgmi_wafl");
++	}
++	ih_info.head = fs_info.head = *adev->gmc.xgmi.ras_if;
++	r = amdgpu_ras_late_init(adev, adev->gmc.xgmi.ras_if,
++				 &fs_info, &ih_info);
++	if (r || !amdgpu_ras_is_supported(adev, adev->gmc.xgmi.ras_if->block)) {
++		kfree(adev->gmc.xgmi.ras_if);
++		adev->gmc.xgmi.ras_if = NULL;
++	}
++
++	return r;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
+index fbcee31788c4..9023789397c0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
+@@ -42,6 +42,7 @@ void amdgpu_xgmi_remove_device(struct amdgpu_device *adev);
+ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate);
+ int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
+ 		struct amdgpu_device *peer_adev);
++int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev);
+ 
+ static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,
+ 		struct amdgpu_device *bo_adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 64cc3068873a..3dde208fa0c6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -51,6 +51,7 @@
+ #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
+ 
+ #include "amdgpu_ras.h"
++#include "amdgpu_xgmi.h"
+ 
+ /* add these here since we already include dce12 headers and these are for DCN */
+ #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x055d
+@@ -804,7 +805,8 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ 		if (r)
+ 			return r;
+ 	}
+-	return 0;
++
++	return amdgpu_xgmi_ras_late_init(adev);
+ }
+ 
+ static int gmc_v9_0_late_init(void *handle)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3771-drm-amdgpu-enable-error-injection-to-XGMI-block-via-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3771-drm-amdgpu-enable-error-injection-to-XGMI-block-via-.patch
new file mode 100644
index 00000000..2a1ebc12
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3771-drm-amdgpu-enable-error-injection-to-XGMI-block-via-.patch
@@ -0,0 +1,29 @@
+From c786548efbb5f1d4f96fae2ed45b61aa5467c34f Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Sun, 8 Sep 2019 09:09:15 +0800
+Subject: [PATCH 3771/4256] drm/amdgpu: enable error injection to XGMI block
+ via debugfs
+
+allow inject error to XGMI block via debugfs node ras_ctrl
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 656e364a473d..84ca13b9d42e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -702,6 +702,7 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev,
+ 		break;
+ 	case AMDGPU_RAS_BLOCK__UMC:
+ 	case AMDGPU_RAS_BLOCK__MMHUB:
++	case AMDGPU_RAS_BLOCK__XGMI_WAFL:
+ 		ret = psp_ras_trigger_error(&adev->psp, &block_info);
+ 		break;
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3772-drm-amdgpu-fix-CPDMA-hang-in-PRT-mode-for-VEGA10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3772-drm-amdgpu-fix-CPDMA-hang-in-PRT-mode-for-VEGA10.patch
new file mode 100644
index 00000000..153b0c05
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3772-drm-amdgpu-fix-CPDMA-hang-in-PRT-mode-for-VEGA10.patch
@@ -0,0 +1,60 @@
+From 16605451a64eca00af5dd8e4da3d8cfe55f107f1 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Tue, 10 Sep 2019 16:54:14 +0800
+Subject: [PATCH 3772/4256] drm/amdgpu: fix CPDMA hang in PRT mode for VEGA10
+
+add and_mask since the programming logic of golden setting changed
+
+Change-Id: If3744beb779c56255c7e797eb115bd6e462237c5
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 3ad97ca9efc5..81ff4e86b65e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -513,9 +513,9 @@ static const struct soc15_reg_golden golden_settings_gc_9_0[] =
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
+-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
+-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
+-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000)
+ };
+ 
+ static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
+@@ -578,9 +578,9 @@ static const struct soc15_reg_golden golden_settings_gc_9_1[] =
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080),
+-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
+-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
+-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000)
+ };
+ 
+ static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
+@@ -672,9 +672,9 @@ static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] =
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
+-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
+-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
+-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000)
+ };
+ 
+ static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] =
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3773-drm-amdkfd-fix-the-missed-asic-name-while-inited-ren.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3773-drm-amdkfd-fix-the-missed-asic-name-while-inited-ren.patch
new file mode 100644
index 00000000..e29f39ca
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3773-drm-amdkfd-fix-the-missed-asic-name-while-inited-ren.patch
@@ -0,0 +1,57 @@
+From 13045486354b5fe7cdc8b93c6d949a184b1f3ee0 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Tue, 10 Sep 2019 19:10:42 +0800
+Subject: [PATCH 3773/4256] drm/amdkfd: fix the missed asic name while inited
+ renoir_device_info
+
+This patch fixes null pointer issue below, I missed to init the asic renior name
+while I rebase the patches.
+
+[  106.004250] BUG: kernel NULL pointer dereference, address: 0000000000000000
+[  106.004254] #PF: supervisor read access in kernel mode
+[  106.004256] #PF: error_code(0x0000) - not-present page
+[  106.004257] PGD 0 P4D 0
+[  106.004261] Oops: 0000 [#1] SMP NOPTI
+[  106.004264] CPU: 3 PID: 1422 Comm: modprobe Not tainted 5.2.0-rc1-custom #1
+[  106.004266] Hardware name: AMD Celadon-RN/Celadon-RN, BIOS
+WCD9814N_Weekly_19_08_1 08/14/2019
+[  106.004272] RIP: 0010:strncpy+0x12/0x30
+[  106.004274] Code: c1 c0 11 48 c1 c6 15 48 31 d0 48 c1 c2 20 31 c2 89 d0 31 f0
+41 5c 5d c3 55 48 85 d2 48 89 f8 48 89 e5 74 1e 48 01 fa 48 89 f9 <44> 0f b6 06
+41 80 f8 01 44 88 01 48 83 de ff 48 83 c1 01 48 39 d1
+[  106.004278] RSP: 0018:ffffc092c1fd37a8 EFLAGS: 00010286
+[  106.004281] RAX: ffff9e943466a28c RBX: 00000000000036ed RCX: ffff9e943466a28c
+[  106.004283] RDX: ffff9e943466a2ac RSI: 0000000000000000 RDI: ffff9e943466a28c
+[  106.004285] RBP: ffffc092c1fd37a8 R08: ffff9e943d100000 R09: 0000000000000228
+[  106.004287] R10: ffff9e94418dc5a8 R11: ffff9e944746c0d0 R12: 0000000000000000
+[  106.004289] R13: ffff9e943fa1ec00 R14: ffff9e943466a200 R15: ffff9e943466a200
+[  106.004291] FS:  00007f7a022c5540(0000) GS:ffff9e9447ac0000(0000)
+knlGS:0000000000000000
+[  106.004294] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+[  106.004296] CR2: 0000000000000000 CR3: 00000001ff0b0000 CR4: 0000000000340ee0
+[  106.004298] Call Trace:
+[  106.004382]  kfd_topology_add_device+0x150/0x610 [amdgpu]
+[  106.004445]  kgd2kfd_device_init+0x2e0/0x4f0 [amdgpu]
+[  106.004509]  amdgpu_amdkfd_device_init+0x14c/0x1b0 [amdgpu]
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-and-Tested-by: Aaron Liu <aaron.liu@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index 3e3fb994bc86..a4ea2fdb1646 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -353,6 +353,7 @@ static const struct kfd_device_info arcturus_device_info = {
+ 
+ static const struct kfd_device_info renoir_device_info = {
+ 	.asic_family = CHIP_RENOIR,
++	.asic_name = "renoir",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+ 	.doorbell_size  = 8,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3774-drm-amdgpu-add-ras-error-query-count-interface-for-n.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3774-drm-amdgpu-add-ras-error-query-count-interface-for-n.patch
new file mode 100644
index 00000000..eed87205
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3774-drm-amdgpu-add-ras-error-query-count-interface-for-n.patch
@@ -0,0 +1,56 @@
+From 2ba58b8d891b5f9eef941d7b3eee85b76bc49bbd Mon Sep 17 00:00:00 2001
+From: Guchun Chen <guchun.chen@amd.com>
+Date: Wed, 4 Sep 2019 14:58:54 +0800
+Subject: [PATCH 3774/4256] drm/amdgpu: add ras error query count interface for
+ nbio
+
+Add the interface query_ras_error_count for nbio.
+
+Change-Id: I32a9d8102068bd8eb53961d290eac1d1a7137a99
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Signed-off-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 ++
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c   | 6 ++++++
+ 2 files changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+index c5255a7fd65a..9e26b81ba6ad 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+@@ -81,6 +81,8 @@ struct amdgpu_nbio_funcs {
+ 	void (*handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device *adev);
+ 	int (*init_ras_controller_interrupt)(struct amdgpu_device *adev);
+ 	int (*init_ras_err_event_athub_interrupt)(struct amdgpu_device *adev);
++	void (*query_ras_error_count)(struct amdgpu_device *adev,
++					void *ras_error_status);
+ 	int (*ras_late_init)(struct amdgpu_device *adev);
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index 2d171bf07ad5..fa6a8918dc8c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -473,6 +473,11 @@ static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *a
+ 	return 0;
+ }
+ 
++static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
++					void *ras_error_status)
++{
++}
++
+ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ 	.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
+ 	.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
+@@ -498,5 +503,6 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ 	.handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
+ 	.init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,
+ 	.init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,
++	.query_ras_error_count = nbio_v7_4_query_ras_error_count,
+ 	.ras_late_init = amdgpu_nbio_ras_late_init,
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3775-drm-amdgpu-support-pcie-bif-ras-query-and-inject.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3775-drm-amdgpu-support-pcie-bif-ras-query-and-inject.patch
new file mode 100644
index 00000000..8b5b928a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3775-drm-amdgpu-support-pcie-bif-ras-query-and-inject.patch
@@ -0,0 +1,41 @@
+From 78d03b0335b485cff0ebbf57126442a1d9122ba7 Mon Sep 17 00:00:00 2001
+From: Guchun Chen <guchun.chen@amd.com>
+Date: Wed, 11 Sep 2019 11:07:15 +0800
+Subject: [PATCH 3775/4256] drm/amdgpu: support pcie bif ras query and inject
+
+Call pcie bif ras query/inject in amdgpu ras.
+
+Change-Id: Idf5021edf21e704314338aa2e8b0671e4d622d1d
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Signed-off-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 84ca13b9d42e..5f06f1e645c7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -654,6 +654,10 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev,
+ 		if (adev->mmhub_funcs->query_ras_error_count)
+ 			adev->mmhub_funcs->query_ras_error_count(adev, &err_data);
+ 		break;
++	case AMDGPU_RAS_BLOCK__PCIE_BIF:
++		if (adev->nbio.funcs->query_ras_error_count)
++			adev->nbio.funcs->query_ras_error_count(adev, &err_data);
++		break;
+ 	default:
+ 		break;
+ 	}
+@@ -703,6 +707,7 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev,
+ 	case AMDGPU_RAS_BLOCK__UMC:
+ 	case AMDGPU_RAS_BLOCK__MMHUB:
+ 	case AMDGPU_RAS_BLOCK__XGMI_WAFL:
++	case AMDGPU_RAS_BLOCK__PCIE_BIF:
+ 		ret = psp_ras_trigger_error(&adev->psp, &block_info);
+ 		break;
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3776-drm-amdgpu-add-pcie-bif-ras-related-registers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3776-drm-amdgpu-add-pcie-bif-ras-related-registers.patch
new file mode 100644
index 00000000..8f37cc1e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3776-drm-amdgpu-add-pcie-bif-ras-related-registers.patch
@@ -0,0 +1,99 @@
+From 1b7282c7d20b1437344b29cfe60b7a5cfb504876 Mon Sep 17 00:00:00 2001
+From: Guchun Chen <guchun.chen@amd.com>
+Date: Wed, 11 Sep 2019 11:10:02 +0800
+Subject: [PATCH 3776/4256] drm/amdgpu: add pcie bif ras related registers
+
+These registers will be accessed for querying ras errors.
+
+Change-Id: If263879c43b2a5a6136a2fb04990daddd860567d
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Signed-off-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ .../include/asic_reg/nbio/nbio_7_4_0_smn.h    | 12 ++++++
+ .../include/asic_reg/nbio/nbio_7_4_sh_mask.h  | 43 +++++++++++++++++++
+ 2 files changed, 55 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h
+index 4bcacf529852..991128bb9476 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h
+@@ -22,6 +22,9 @@
+ #ifndef _nbio_7_4_0_SMN_HEADER
+ #define _nbio_7_4_0_SMN_HEADER
+ 
++// addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk
++// base address: 0x10100000
++#define smnBIFL_RAS_CENTRAL_STATUS			0x10139040
+ 
+ #define smnNBIF_MGCG_CTRL_LCLK				0x1013a21c
+ #define smnCPM_CONTROL					0x11180460
+@@ -53,4 +56,13 @@
+ #define smnPCIE_RX_NUM_NAK				0x11180038
+ #define smnPCIE_RX_NUM_NAK_GENERATED			0x1118003c
+ 
++// addressBlock: nbio_iohub_nb_misc_misc_cfgdec
++// base address: 0x13a10000
++#define smnIOHC_INTERRUPT_EOI				0x13a10120
++
++// addressBlock: nbio_iohub_nb_rascfg_ras_cfgdec
++// base address: 0x13a20000
++#define smnRAS_GLOBAL_STATUS_LO				0x13a20020
++#define smnRAS_GLOBAL_STATUS_HI				0x13a20024
++
+ #endif	// _nbio_7_4_0_SMN_HEADER
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h
+index f9829f577364..07f04b2b5bdd 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h
+@@ -48436,4 +48436,47 @@
+ #define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK                                              0x00000002L
+ #define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK                                              0x00000004L
+ 
++//IOHC_INTERRUPT_EOI
++#define IOHC_INTERRUPT_EOI__SMI_EOI__SHIFT                                                                    0x0
++#define IOHC_INTERRUPT_EOI__SCI_EOI__SHIFT                                                                    0x1
++#define IOHC_INTERRUPT_EOI__NMI_EOI__SHIFT                                                                    0x2
++#define IOHC_INTERRUPT_EOI__SMI_EOI_MASK                                                                      0x00000001L
++#define IOHC_INTERRUPT_EOI__SCI_EOI_MASK                                                                      0x00000002L
++#define IOHC_INTERRUPT_EOI__NMI_EOI_MASK                                                                      0x00000004L
++
++//RAS_GLOBAL_STATUS_LO
++#define RAS_GLOBAL_STATUS_LO__ParityErrCorr__SHIFT                                                            0x0
++#define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal__SHIFT                                                        0x1
++#define RAS_GLOBAL_STATUS_LO__ParityErrFatal__SHIFT                                                           0x2
++#define RAS_GLOBAL_STATUS_LO__ParityErrSerr__SHIFT                                                            0x3
++#define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI__SHIFT                                                               0x6
++#define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI__SHIFT                                                               0x7
++#define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI__SHIFT                                                               0x8
++#define RAS_GLOBAL_STATUS_LO__SW_SMI__SHIFT                                                                   0x9
++#define RAS_GLOBAL_STATUS_LO__SW_SCI__SHIFT                                                                   0xa
++#define RAS_GLOBAL_STATUS_LO__SW_NMI__SHIFT                                                                   0xb
++#define RAS_GLOBAL_STATUS_LO__APML_NMI__SHIFT                                                                 0xc
++#define RAS_GLOBAL_STATUS_LO__APML_SyncFld__SHIFT                                                             0xd
++#define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI__SHIFT                                                          0xe
++#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private__SHIFT                                                     0xf
++#define RAS_GLOBAL_STATUS_LO__ParityErrCorr_MASK                                                              0x00000001L
++#define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal_MASK                                                          0x00000002L
++#define RAS_GLOBAL_STATUS_LO__ParityErrFatal_MASK                                                             0x00000004L
++#define RAS_GLOBAL_STATUS_LO__ParityErrSerr_MASK                                                              0x00000008L
++#define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI_MASK                                                                 0x00000040L
++#define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI_MASK                                                                 0x00000080L
++#define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI_MASK                                                                 0x00000100L
++#define RAS_GLOBAL_STATUS_LO__SW_SMI_MASK                                                                     0x00000200L
++#define RAS_GLOBAL_STATUS_LO__SW_SCI_MASK                                                                     0x00000400L
++#define RAS_GLOBAL_STATUS_LO__SW_NMI_MASK                                                                     0x00000800L
++#define RAS_GLOBAL_STATUS_LO__APML_NMI_MASK                                                                   0x00001000L
++#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_MASK                                                               0x00002000L
++#define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI_MASK                                                            0x00004000L
++#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private_MASK                                                       0x00008000L
++//RAS_GLOBAL_STATUS_HI
++#define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr__SHIFT                                                            0x0
++#define RAS_GLOBAL_STATUS_HI__NBIF0PortAErr__SHIFT                                                            0x1
++#define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr_MASK                                                              0x00000001L
++#define RAS_GLOBAL_STATUS_HI__NBIF0PortAErr_MASK                                                              0x00000002L
++
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3777-drm-amdgpu-implement-ras-query-function-for-pcie-bif.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3777-drm-amdgpu-implement-ras-query-function-for-pcie-bif.patch
new file mode 100644
index 00000000..5d386e7e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3777-drm-amdgpu-implement-ras-query-function-for-pcie-bif.patch
@@ -0,0 +1,60 @@
+From 250281209ac40233db6c61c2a96acb30081dd668 Mon Sep 17 00:00:00 2001
+From: Guchun Chen <guchun.chen@amd.com>
+Date: Wed, 11 Sep 2019 11:12:17 +0800
+Subject: [PATCH 3777/4256] drm/amdgpu: implement ras query function for pcie
+ bif
+
+ras error query funtionality implementation
+
+Change-Id: Id7d8c35621960685a2a7507e4e95939f5a05bdc6
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Signed-off-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 30 ++++++++++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index fa6a8918dc8c..b776332d979f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -476,6 +476,36 @@ static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *a
+ static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
+ 					void *ras_error_status)
+ {
++	uint32_t global_sts, central_sts, int_eoi;
++	uint32_t corr, fatal, non_fatal;
++	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
++
++	global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO);
++	corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr);
++	fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal);
++	non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO,
++				ParityErrNonFatal);
++
++	if (corr)
++		err_data->ce_count++;
++	if (fatal)
++		err_data->ue_count++;
++
++	if (corr || fatal || non_fatal) {
++		central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS);
++		/* clear error status register */
++		WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts);
++
++		if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS,
++				BIFL_RasContller_Intr_Recv)) {
++			/* clear interrupt status register */
++			WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts);
++			int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI);
++			int_eoi = REG_SET_FIELD(int_eoi,
++					IOHC_INTERRUPT_EOI, SMI_EOI, 1);
++			WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi);
++		}
++	}
+ }
+ 
+ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3778-drm-amd-display-add-Asic-ID-for-Dali.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3778-drm-amd-display-add-Asic-ID-for-Dali.patch
new file mode 100644
index 00000000..6a40d36b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3778-drm-amd-display-add-Asic-ID-for-Dali.patch
@@ -0,0 +1,38 @@
+From 22cf5278c460d2cfa3d5a80239078a28a4e3e146 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 6 Sep 2019 16:31:21 -0400
+Subject: [PATCH 3778/4256] drm/amd/display: add Asic ID for Dali
+
+Dali is a new asic revision based on raven2
+
+Add the ID and ASICREV_IS_DALI define
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/include/dal_asic_id.h | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+index 47c156800e1e..68e8f6378d40 100644
+--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
++++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+@@ -137,9 +137,13 @@
+ #define RAVEN1_F0 0xF0
+ #define RAVEN_UNKNOWN 0xFF
+ 
++#define PICASSO_15D8_REV_E3 0xE3
++#define PICASSO_15D8_REV_E4 0xE4
++
+ #define ASICREV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
+ #define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0))
+-#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < 0xF0))
++#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < PICASSO_15D8_REV_E3))
++#define ASICREV_IS_DALI(eChipRev) ((eChipRev >= PICASSO_15D8_REV_E3) && (eChipRev < RAVEN1_F0))
+ 
+ #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3779-drm-amd-display-Implement-voltage-limitation-for-dal.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3779-drm-amd-display-Implement-voltage-limitation-for-dal.patch
new file mode 100644
index 00000000..d0e7c0f0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3779-drm-amd-display-Implement-voltage-limitation-for-dal.patch
@@ -0,0 +1,38 @@
+From 1285c81e64de35f423e974ddf24b8d267a07f237 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 6 Sep 2019 16:32:44 -0400
+Subject: [PATCH 3779/4256] drm/amd/display: Implement voltage limitation for
+ dali
+
+[Why]
+we only want the lowest voltage to be available for dali.
+
+[How]
+Use the get_highest_allowed_voltage_level function
+to return 0 for dali
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+index 383f4f8db8f4..9b2cb57bf2ba 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+@@ -708,6 +708,10 @@ static void hack_bounding_box(struct dcn_bw_internal_vars *v,
+ 
+ unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev)
+ {
++	/* for dali, the highest voltage level we want is 0 */
++	if (ASICREV_IS_DALI(hw_internal_rev))
++		return 0;
++
+ 	/* we are ok with all levels */
+ 	return 4;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3780-drm-amdkfd-add-queue-snapshot.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3780-drm-amdkfd-add-queue-snapshot.patch
new file mode 100644
index 00000000..e0e75e7d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3780-drm-amdkfd-add-queue-snapshot.patch
@@ -0,0 +1,311 @@
+From ffcec3477d42f38d9f4b1ed0da69bf9880931070 Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Tue, 27 Aug 2019 15:14:51 -0400
+Subject: [PATCH 3780/4256] drm/amdkfd: add queue snapshot
+
+update ioctl call to get queue snapshot per process
+
+Change-Id: I827e8dd4e570e31e01c775b24949b0d2aeb6d9b4
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c      | 12 ++++-
+ drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c | 45 ++++++++++---------
+ drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h |  2 +
+ .../drm/amd/amdkfd/kfd_device_queue_manager.c | 38 ++++++++++++++++
+ .../drm/amd/amdkfd/kfd_device_queue_manager.h |  5 +++
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h         |  5 +++
+ .../amd/amdkfd/kfd_process_queue_manager.c    | 36 +++++++++++++++
+ include/uapi/linux/kfd_ioctl.h                | 21 +++++++++
+ 8 files changed, 142 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index 44a9803f26f3..547e7f511775 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -2628,7 +2628,6 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 		debug_trap_action == KFD_IOC_DBG_TRAP_NODE_SUSPEND ||
+ 		debug_trap_action == KFD_IOC_DBG_TRAP_NODE_RESUME;
+ 
+-
+ 	pid = find_get_pid(args->pid);
+ 	if (!pid) {
+ 		pr_err("Cannot find pid info for %i\n",
+@@ -2801,6 +2800,17 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 						 args->data2,
+ 						 &args->data3);
+ 		break;
++	case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT:
++		r = pqm_get_queue_snapshot(&p->pqm, args->data1,
++					   (void __user *)args->ptr,
++					   args->data2);
++
++		if (r > 0) {
++			args->data2 = r;
++			r = 0;
++		}
++
++		break;
+ 	default:
+ 		pr_err("Invalid option: %i\n", debug_trap_action);
+ 		r = -EINVAL;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
+index 1681107a2aa6..5433b6527bae 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
+@@ -101,6 +101,25 @@ static int kfd_dbg_ev_release(struct inode *inode, struct file *filep)
+ 	((x) = (n) ? (x) | KFD_DBG_EV_STATUS_NEW_QUEUE :	\
+ 		(x) & ~KFD_DBG_EV_STATUS_NEW_QUEUE)
+ 
++uint32_t kfd_dbg_get_queue_status_word(struct queue *q, int flags)
++{
++	uint32_t queue_status_word = 0;
++
++	KFD_DBG_EV_SET_EVENT_TYPE(queue_status_word,
++				  q->properties.debug_event_type);
++	KFD_DBG_EV_SET_SUSPEND_STATE(queue_status_word,
++				  q->properties.is_suspended);
++	KFD_DBG_EV_SET_NEW_QUEUE_STATE(queue_status_word,
++				  q->properties.is_new);
++
++	if (flags & KFD_DBG_EV_FLAG_CLEAR_STATUS) {
++		q->properties.is_new = false;
++		q->properties.debug_event_type = 0;
++	}
++
++	return queue_status_word;
++}
++
+ int kfd_dbg_ev_query_debug_event(struct kfd_process_device *pdd,
+ 		      unsigned int *queue_id,
+ 		      unsigned int flags,
+@@ -126,16 +145,8 @@ int kfd_dbg_ev_query_debug_event(struct kfd_process_device *pdd,
+ 			goto out;
+ 		}
+ 
+-		KFD_DBG_EV_SET_EVENT_TYPE(*event_status,
+-					  q->properties.debug_event_type);
+-		KFD_DBG_EV_SET_SUSPEND_STATE(*event_status,
+-					  q->properties.is_suspended);
+-		KFD_DBG_EV_SET_NEW_QUEUE_STATE(*event_status,
+-					  q->properties.is_new);
+-		if (flags & KFD_DBG_EV_FLAG_CLEAR_STATUS) {
+-			q->properties.is_new = false;
+-			q->properties.debug_event_type = 0;
+-		}
++		*event_status = kfd_dbg_get_queue_status_word(q, flags);
++
+ 		goto out;
+ 
+ 	} else {
+@@ -146,17 +157,9 @@ int kfd_dbg_ev_query_debug_event(struct kfd_process_device *pdd,
+ 				|| pqn->q->properties.debug_event_type
+ 					== KFD_DBG_EV_STATUS_VMFAULT)) {
+ 				*queue_id = pqn->q->properties.queue_id;
+-				KFD_DBG_EV_SET_EVENT_TYPE(*event_status,
+-					pqn->q->properties.debug_event_type);
+-				KFD_DBG_EV_SET_SUSPEND_STATE(*event_status,
+-					pqn->q->properties.is_suspended);
+-				KFD_DBG_EV_SET_NEW_QUEUE_STATE(*event_status,
+-					pqn->q->properties.is_new);
+-				if (flags & KFD_DBG_EV_FLAG_CLEAR_STATUS) {
+-					pqn->q->properties.is_new = false;
+-					pqn->q->properties.debug_event_type
+-									= 0;
+-				}
++				*event_status =
++					kfd_dbg_get_queue_status_word(pqn->q,
++								      flags);
+ 				goto out;
+ 			}
+ 		}
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h
+index 5b035a4321c6..49ccf8b2b66c 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.h
+@@ -25,6 +25,8 @@
+ 
+ #include "kfd_priv.h"
+ 
++uint32_t kfd_dbg_get_queue_status_word(struct queue *q, int flags);
++
+ int kfd_dbg_ev_query_debug_event(struct kfd_process_device *pdd,
+ 		      unsigned int *queue_id,
+ 		      unsigned int flags,
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 83cddab4d482..dbcbacb5abd4 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -35,6 +35,7 @@
+ #include "cik_regs.h"
+ #include "kfd_kernel_queue.h"
+ #include "amdgpu_amdkfd.h"
++#include "kfd_debug_events.h"
+ 
+ /* Size of the per-pipe EOP queue */
+ #define CIK_HPD_EOP_BYTES_LOG2 11
+@@ -2234,6 +2235,43 @@ int resume_queues(struct kfd_process *p,
+ 	return r;
+ }
+ 
++static uint32_t set_queue_type_for_user(struct queue_properties *q_props)
++{
++	switch (q_props->type) {
++	case KFD_QUEUE_TYPE_COMPUTE:
++		return q_props->format == KFD_QUEUE_FORMAT_PM4
++					? KFD_IOC_QUEUE_TYPE_COMPUTE
++					: KFD_IOC_QUEUE_TYPE_COMPUTE_AQL;
++	case KFD_QUEUE_TYPE_SDMA:
++		return KFD_IOC_QUEUE_TYPE_SDMA;
++	case KFD_QUEUE_TYPE_SDMA_XGMI:
++		return KFD_IOC_QUEUE_TYPE_SDMA_XGMI;
++	default:
++		WARN_ONCE(true, "queue type not recognized!");
++		return 0xffffffff;
++	};
++}
++
++void set_queue_snapshot_entry(struct device_queue_manager *dqm,
++			      struct queue *q,
++			      int flags,
++			      struct kfd_queue_snapshot_entry *qss_entry)
++{
++	dqm_lock(dqm);
++
++	qss_entry->ring_base_address = q->properties.queue_address,
++	qss_entry->write_pointer_address = (uint64_t)q->properties.write_ptr;
++	qss_entry->read_pointer_address = (uint64_t)q->properties.read_ptr,
++	qss_entry->ctx_save_restore_address =
++				q->properties.ctx_save_restore_area_address;
++	qss_entry->queue_id = q->properties.queue_id;
++	qss_entry->gpu_id = q->device->id;
++	qss_entry->ring_size = (uint32_t)q->properties.queue_size;
++	qss_entry->queue_type = set_queue_type_for_user(&q->properties);
++	qss_entry->queue_status = kfd_dbg_get_queue_status_word(q, flags);
++
++	dqm_unlock(dqm);
++}
+ 
+ #if defined(CONFIG_DEBUG_FS)
+ 
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+index fcab7ad80512..54f4fad61359 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+@@ -237,6 +237,11 @@ int resume_queues(struct kfd_process *p,
+ 		uint32_t flags,
+ 		uint32_t *queue_ids);
+ 
++void set_queue_snapshot_entry(struct device_queue_manager *dqm,
++			      struct queue *q,
++			      int flags,
++			      struct kfd_queue_snapshot_entry *qss_entry);
++
+ static inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd)
+ {
+ 	return (pdd->lds_base >> 16) & 0xFF;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index 5d3cffc9d0ec..b0965eaa327e 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -1055,6 +1055,11 @@ int pqm_get_wave_state(struct process_queue_manager *pqm,
+ 		       u32 *ctl_stack_used_size,
+ 		       u32 *save_area_used_size);
+ 
++int pqm_get_queue_snapshot(struct process_queue_manager *pqm,
++			   int flags,
++			   struct kfd_queue_snapshot_entry __user *buf,
++			   int num_qss_entries);
++
+ int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
+ 				unsigned int fence_value,
+ 				unsigned int timeout_ms);
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+index d47ab53d613b..a594945097a3 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+@@ -505,6 +505,42 @@ int pqm_get_wave_state(struct process_queue_manager *pqm,
+ 						       save_area_used_size);
+ }
+ 
++int pqm_get_queue_snapshot(struct process_queue_manager *pqm,
++			   int flags,
++			   struct kfd_queue_snapshot_entry __user *buf,
++			   int num_qss_entries)
++{
++	struct process_queue_node *pqn;
++	int r, qss_entry_count = 0;
++
++	mutex_lock(&pqm->process->event_mutex);
++
++	list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
++		if (!pqn->q)
++			continue;
++
++		if (qss_entry_count < num_qss_entries) {
++
++			struct kfd_queue_snapshot_entry src = {0};
++
++			set_queue_snapshot_entry(pqn->q->device->dqm,
++						 pqn->q, flags, &src);
++
++			r = copy_to_user(buf++, &src, sizeof(src));
++
++			if (r) {
++				qss_entry_count = -EFAULT;
++				goto unlock;
++			}
++		}
++
++		qss_entry_count++;
++	}
++unlock:
++	mutex_unlock(&pqm->process->event_mutex);
++	return qss_entry_count;
++}
++
+ #if defined(CONFIG_DEBUG_FS)
+ 
+ int pqm_debugfs_mqds(struct seq_file *m, void *data)
+diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
+index 86805463e1d3..be91603f2c0f 100644
+--- a/include/uapi/linux/kfd_ioctl.h
++++ b/include/uapi/linux/kfd_ioctl.h
+@@ -91,6 +91,19 @@ struct kfd_ioctl_get_queue_wave_state_args {
+ 	__u32 pad;
+ };
+ 
++struct kfd_queue_snapshot_entry {
++	__u64 ring_base_address;
++	__u64 write_pointer_address;
++	__u64 read_pointer_address;
++	__u64 ctx_save_restore_address;
++	__u32 queue_id;
++	__u32 gpu_id;
++	__u32 ring_size;
++	__u32 queue_type;
++	__u32 queue_status;
++	__u32 reserved[19];
++};
++
+ /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
+ #define KFD_IOC_CACHE_POLICY_COHERENT 0
+ #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
+@@ -252,6 +265,14 @@ struct kfd_ioctl_dbg_wave_control_args {
+  */
+ #define KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT 6
+ 
++/* KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT:
++ * ptr: user buffer (IN)
++ * data1: flags (IN)
++ * data2: number of queue snapshots (IN/OUT) - 0 for IN ignores buffer writes
++ * data3: unused
++ */
++#define KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT 7
++
+ struct kfd_ioctl_dbg_trap_args {
+ 	__u64 ptr;     /* to KFD -- used for pointer arguments: queue arrays */
+ 	__u32 pid;     /* to KFD */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3781-drm-amdgpu-Add-SRIOV-mailbox-backend-for-Navi1x.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3781-drm-amdgpu-Add-SRIOV-mailbox-backend-for-Navi1x.patch
new file mode 100644
index 00000000..4e05466a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3781-drm-amdgpu-Add-SRIOV-mailbox-backend-for-Navi1x.patch
@@ -0,0 +1,466 @@
+From 53ca151c207b31324de02b0414db9a6f4e20be80 Mon Sep 17 00:00:00 2001
+From: Jiange Zhao <Jiange.Zhao@amd.com>
+Date: Wed, 4 Sep 2019 14:42:01 +0800
+Subject: [PATCH 3781/4256] drm/amdgpu: Add SRIOV mailbox backend for Navi1x
+
+Mimic the ones for Vega10, add mailbox backend for Navi1x
+
+Reviewed-by: Emily Deng <Emily.Deng@amd.com>
+Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
+ drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 380 ++++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h |  41 +++
+ 3 files changed, 422 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index d3c2ccd8f98a..1589a2489944 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -69,7 +69,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce
+ amdgpu-y += \
+ 	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
+ 	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
+-	arct_reg_init.o navi12_reg_init.o
++	arct_reg_init.o navi12_reg_init.o mxgpu_nv.o
+ 
+ # add DF block
+ amdgpu-y += \
+diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
+new file mode 100644
+index 000000000000..0d8767eb7a70
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
+@@ -0,0 +1,380 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include "amdgpu.h"
++#include "nbio/nbio_2_3_offset.h"
++#include "nbio/nbio_2_3_sh_mask.h"
++#include "gc/gc_10_1_0_offset.h"
++#include "gc/gc_10_1_0_sh_mask.h"
++#include "soc15.h"
++#include "navi10_ih.h"
++#include "soc15_common.h"
++#include "mxgpu_nv.h"
++#include "mxgpu_ai.h"
++
++static void xgpu_nv_mailbox_send_ack(struct amdgpu_device *adev)
++{
++	WREG8(NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2);
++}
++
++static void xgpu_nv_mailbox_set_valid(struct amdgpu_device *adev, bool val)
++{
++	WREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0);
++}
++
++/*
++ * this peek_msg could *only* be called in IRQ routine becuase in IRQ routine
++ * RCV_MSG_VALID filed of BIF_BX_PF_MAILBOX_CONTROL must already be set to 1
++ * by host.
++ *
++ * if called no in IRQ routine, this peek_msg cannot guaranteed to return the
++ * correct value since it doesn't return the RCV_DW0 under the case that
++ * RCV_MSG_VALID is set by host.
++ */
++static enum idh_event xgpu_nv_mailbox_peek_msg(struct amdgpu_device *adev)
++{
++	return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
++				mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0));
++}
++
++
++static int xgpu_nv_mailbox_rcv_msg(struct amdgpu_device *adev,
++				   enum idh_event event)
++{
++	u32 reg;
++
++	reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
++					     mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0));
++	if (reg != event)
++		return -ENOENT;
++
++	xgpu_nv_mailbox_send_ack(adev);
++
++	return 0;
++}
++
++static uint8_t xgpu_nv_peek_ack(struct amdgpu_device *adev)
++{
++	return RREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE) & 2;
++}
++
++static int xgpu_nv_poll_ack(struct amdgpu_device *adev)
++{
++	int timeout  = NV_MAILBOX_POLL_ACK_TIMEDOUT;
++	u8 reg;
++
++	do {
++		reg = RREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE);
++		if (reg & 2)
++			return 0;
++
++		mdelay(5);
++		timeout -= 5;
++	} while (timeout > 1);
++
++	pr_err("Doesn't get TRN_MSG_ACK from pf in %d msec\n", NV_MAILBOX_POLL_ACK_TIMEDOUT);
++
++	return -ETIME;
++}
++
++static int xgpu_nv_poll_msg(struct amdgpu_device *adev, enum idh_event event)
++{
++	int r, timeout = NV_MAILBOX_POLL_MSG_TIMEDOUT;
++
++	do {
++		r = xgpu_nv_mailbox_rcv_msg(adev, event);
++		if (!r)
++			return 0;
++
++		msleep(10);
++		timeout -= 10;
++	} while (timeout > 1);
++
++	pr_err("Doesn't get msg:%d from pf, error=%d\n", event, r);
++
++	return -ETIME;
++}
++
++static void xgpu_nv_mailbox_trans_msg (struct amdgpu_device *adev,
++	      enum idh_request req, u32 data1, u32 data2, u32 data3)
++{
++	u32 reg;
++	int r;
++	uint8_t trn;
++
++	/* IMPORTANT:
++	 * clear TRN_MSG_VALID valid to clear host's RCV_MSG_ACK
++	 * and with host's RCV_MSG_ACK cleared hw automatically clear host's RCV_MSG_ACK
++	 * which lead to VF's TRN_MSG_ACK cleared, otherwise below xgpu_nv_poll_ack()
++	 * will return immediatly
++	 */
++	do {
++		xgpu_nv_mailbox_set_valid(adev, false);
++		trn = xgpu_nv_peek_ack(adev);
++		if (trn) {
++			pr_err("trn=%x ACK should not assert! wait again !\n", trn);
++			msleep(1);
++		}
++	} while (trn);
++
++	reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
++					     mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0));
++	reg = REG_SET_FIELD(reg, BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0,
++			    MSGBUF_DATA, req);
++	WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0),
++		      reg);
++	WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1),
++				data1);
++	WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2),
++				data2);
++	WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3),
++				data3);
++
++	xgpu_nv_mailbox_set_valid(adev, true);
++
++	/* start to poll ack */
++	r = xgpu_nv_poll_ack(adev);
++	if (r)
++		pr_err("Doesn't get ack from pf, continue\n");
++
++	xgpu_nv_mailbox_set_valid(adev, false);
++}
++
++static int xgpu_nv_send_access_requests(struct amdgpu_device *adev,
++					enum idh_request req)
++{
++	int r;
++
++	xgpu_nv_mailbox_trans_msg(adev, req, 0, 0, 0);
++
++	/* start to check msg if request is idh_req_gpu_init_access */
++	if (req == IDH_REQ_GPU_INIT_ACCESS ||
++		req == IDH_REQ_GPU_FINI_ACCESS ||
++		req == IDH_REQ_GPU_RESET_ACCESS) {
++		r = xgpu_nv_poll_msg(adev, IDH_READY_TO_ACCESS_GPU);
++		if (r) {
++			pr_err("Doesn't get READY_TO_ACCESS_GPU from pf, give up\n");
++			return r;
++		}
++		/* Retrieve checksum from mailbox2 */
++		if (req == IDH_REQ_GPU_INIT_ACCESS || req == IDH_REQ_GPU_RESET_ACCESS) {
++			adev->virt.fw_reserve.checksum_key =
++				RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
++					mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2));
++		}
++	}
++
++	return 0;
++}
++
++static int xgpu_nv_request_reset(struct amdgpu_device *adev)
++{
++	return xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);
++}
++
++static int xgpu_nv_request_full_gpu_access(struct amdgpu_device *adev,
++					   bool init)
++{
++	enum idh_request req;
++
++	req = init ? IDH_REQ_GPU_INIT_ACCESS : IDH_REQ_GPU_FINI_ACCESS;
++	return xgpu_nv_send_access_requests(adev, req);
++}
++
++static int xgpu_nv_release_full_gpu_access(struct amdgpu_device *adev,
++					   bool init)
++{
++	enum idh_request req;
++	int r = 0;
++
++	req = init ? IDH_REL_GPU_INIT_ACCESS : IDH_REL_GPU_FINI_ACCESS;
++	r = xgpu_nv_send_access_requests(adev, req);
++
++	return r;
++}
++
++static int xgpu_nv_mailbox_ack_irq(struct amdgpu_device *adev,
++					struct amdgpu_irq_src *source,
++					struct amdgpu_iv_entry *entry)
++{
++	DRM_DEBUG("get ack intr and do nothing.\n");
++	return 0;
++}
++
++static int xgpu_nv_set_mailbox_ack_irq(struct amdgpu_device *adev,
++					struct amdgpu_irq_src *source,
++					unsigned type,
++					enum amdgpu_interrupt_state state)
++{
++	u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_INT_CNTL));
++
++	tmp = REG_SET_FIELD(tmp, BIF_BX_PF_MAILBOX_INT_CNTL, ACK_INT_EN,
++				(state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);
++	WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_INT_CNTL), tmp);
++
++	return 0;
++}
++
++static void xgpu_nv_mailbox_flr_work(struct work_struct *work)
++{
++	struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work);
++	struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);
++	int timeout = NV_MAILBOX_POLL_FLR_TIMEDOUT;
++	int locked;
++
++	/* block amdgpu_gpu_recover till msg FLR COMPLETE received,
++	 * otherwise the mailbox msg will be ruined/reseted by
++	 * the VF FLR.
++	 *
++	 * we can unlock the lock_reset to allow "amdgpu_job_timedout"
++	 * to run gpu_recover() after FLR_NOTIFICATION_CMPL received
++	 * which means host side had finished this VF's FLR.
++	 */
++	locked = mutex_trylock(&adev->lock_reset);
++	if (locked)
++		adev->in_gpu_reset = 1;
++
++	do {
++		if (xgpu_nv_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL)
++			goto flr_done;
++
++		msleep(10);
++		timeout -= 10;
++	} while (timeout > 1);
++
++flr_done:
++	if (locked) {
++		adev->in_gpu_reset = 0;
++		mutex_unlock(&adev->lock_reset);
++	}
++
++	/* Trigger recovery for world switch failure if no TDR */
++	if (amdgpu_device_should_recover_gpu(adev))
++		amdgpu_device_gpu_recover(adev, NULL);
++}
++
++static int xgpu_nv_set_mailbox_rcv_irq(struct amdgpu_device *adev,
++				       struct amdgpu_irq_src *src,
++				       unsigned type,
++				       enum amdgpu_interrupt_state state)
++{
++	u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_INT_CNTL));
++
++	tmp = REG_SET_FIELD(tmp, BIF_BX_PF_MAILBOX_INT_CNTL, VALID_INT_EN,
++			    (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);
++	WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_INT_CNTL), tmp);
++
++	return 0;
++}
++
++static int xgpu_nv_mailbox_rcv_irq(struct amdgpu_device *adev,
++				   struct amdgpu_irq_src *source,
++				   struct amdgpu_iv_entry *entry)
++{
++	enum idh_event event = xgpu_nv_mailbox_peek_msg(adev);
++
++	switch (event) {
++	case IDH_FLR_NOTIFICATION:
++		if (amdgpu_sriov_runtime(adev))
++			schedule_work(&adev->virt.flr_work);
++		break;
++		/* READY_TO_ACCESS_GPU is fetched by kernel polling, IRQ can ignore
++		 * it byfar since that polling thread will handle it,
++		 * other msg like flr complete is not handled here.
++		 */
++	case IDH_CLR_MSG_BUF:
++	case IDH_FLR_NOTIFICATION_CMPL:
++	case IDH_READY_TO_ACCESS_GPU:
++	default:
++		break;
++	}
++
++	return 0;
++}
++
++static const struct amdgpu_irq_src_funcs xgpu_nv_mailbox_ack_irq_funcs = {
++	.set = xgpu_nv_set_mailbox_ack_irq,
++	.process = xgpu_nv_mailbox_ack_irq,
++};
++
++static const struct amdgpu_irq_src_funcs xgpu_nv_mailbox_rcv_irq_funcs = {
++	.set = xgpu_nv_set_mailbox_rcv_irq,
++	.process = xgpu_nv_mailbox_rcv_irq,
++};
++
++void xgpu_nv_mailbox_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->virt.ack_irq.num_types = 1;
++	adev->virt.ack_irq.funcs = &xgpu_nv_mailbox_ack_irq_funcs;
++	adev->virt.rcv_irq.num_types = 1;
++	adev->virt.rcv_irq.funcs = &xgpu_nv_mailbox_rcv_irq_funcs;
++}
++
++int xgpu_nv_mailbox_add_irq_id(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq);
++	if (r)
++		return r;
++
++	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);
++	if (r) {
++		amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
++		return r;
++	}
++
++	return 0;
++}
++
++int xgpu_nv_mailbox_get_irq(struct amdgpu_device *adev)
++{
++	int r;
++
++	r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0);
++	if (r)
++		return r;
++	r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0);
++	if (r) {
++		amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
++		return r;
++	}
++
++	INIT_WORK(&adev->virt.flr_work, xgpu_nv_mailbox_flr_work);
++
++	return 0;
++}
++
++void xgpu_nv_mailbox_put_irq(struct amdgpu_device *adev)
++{
++	amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);
++	amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
++}
++
++const struct amdgpu_virt_ops xgpu_nv_virt_ops = {
++	.req_full_gpu	= xgpu_nv_request_full_gpu_access,
++	.rel_full_gpu	= xgpu_nv_release_full_gpu_access,
++	.reset_gpu = xgpu_nv_request_reset,
++	.wait_reset = NULL,
++	.trans_msg = xgpu_nv_mailbox_trans_msg,
++};
+diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
+new file mode 100644
+index 000000000000..99b15f6865cb
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
+@@ -0,0 +1,41 @@
++/*
++ * Copyright 2014 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __MXGPU_NV_H__
++#define __MXGPU_NV_H__
++
++#define NV_MAILBOX_POLL_ACK_TIMEDOUT	500
++#define NV_MAILBOX_POLL_MSG_TIMEDOUT	12000
++#define NV_MAILBOX_POLL_FLR_TIMEDOUT	500
++
++extern const struct amdgpu_virt_ops xgpu_nv_virt_ops;
++
++void xgpu_nv_mailbox_set_irq_funcs(struct amdgpu_device *adev);
++int xgpu_nv_mailbox_add_irq_id(struct amdgpu_device *adev);
++int xgpu_nv_mailbox_get_irq(struct amdgpu_device *adev);
++void xgpu_nv_mailbox_put_irq(struct amdgpu_device *adev);
++
++#define NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE (SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_CONTROL) * 4)
++#define NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE (SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_CONTROL) * 4 + 1)
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3782-drm-amdgpu-Fix-mutex-lock-from-atomic-context.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3782-drm-amdgpu-Fix-mutex-lock-from-atomic-context.patch
new file mode 100644
index 00000000..5076903d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3782-drm-amdgpu-Fix-mutex-lock-from-atomic-context.patch
@@ -0,0 +1,41 @@
+From 37ee7543723ef762a479ac6d6bb5c53555950f58 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Tue, 10 Sep 2019 15:34:16 -0400
+Subject: [PATCH 3782/4256] drm/amdgpu: Fix mutex lock from atomic context.
+
+Problem:
+amdgpu_ras_reserve_bad_pages was moved to amdgpu_ras_reset_gpu
+because writing to EEPROM during ASIC reset was unstable.
+But for ERREVENT_ATHUB_INTERRUPT amdgpu_ras_reset_gpu is called
+directly from ISR context and so locking is not allowed. Also it's
+irrelevant for this partilcular interrupt as this is generic RAS
+interrupt and not memory errors specific.
+
+Fix:
+Avoid calling amdgpu_ras_reserve_bad_pages if not in task context.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index 012034d2ae06..dd5da3c6327e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -504,7 +504,9 @@ static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev,
+ 	/* save bad page to eeprom before gpu reset,
+ 	 * i2c may be unstable in gpu reset
+ 	 */
+-	amdgpu_ras_reserve_bad_pages(adev);
++	if (in_task())
++		amdgpu_ras_reserve_bad_pages(adev);
++
+ 	if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
+ 		schedule_work(&ras->recovery_work);
+ 	return 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3783-drm-amdgpu-Fix-KFD-related-kernel-oops-on-Hawaii.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3783-drm-amdgpu-Fix-KFD-related-kernel-oops-on-Hawaii.patch
new file mode 100644
index 00000000..a5b17cec
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3783-drm-amdgpu-Fix-KFD-related-kernel-oops-on-Hawaii.patch
@@ -0,0 +1,35 @@
+From e0b28c9f844741146773f7b920cf7efbbe078e28 Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Thu, 5 Sep 2019 19:22:02 -0400
+Subject: [PATCH 3783/4256] drm/amdgpu: Fix KFD-related kernel oops on Hawaii
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Hawaii needs to flush caches explicitly, submitting an IB in a user
+VMID from kernel mode. There is no s_fence in this case.
+
+Fixes: eb3961a57424 ("drm/amdgpu: remove fence context from the job")
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+index 210a6fd5676a..0515f7a98a11 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+@@ -142,7 +142,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
+ 	/* ring tests don't use a job */
+ 	if (job) {
+ 		vm = job->vm;
+-		fence_ctx = job->base.s_fence->scheduled.context;
++		fence_ctx = job->base.s_fence ?
++			job->base.s_fence->scheduled.context : 0;
+ 	} else {
+ 		vm = NULL;
+ 		fence_ctx = 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3784-drm-amd-powerplay-properly-set-mp1-state-for-SW-SMU-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3784-drm-amd-powerplay-properly-set-mp1-state-for-SW-SMU-.patch
new file mode 100644
index 00000000..869e0f0a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3784-drm-amd-powerplay-properly-set-mp1-state-for-SW-SMU-.patch
@@ -0,0 +1,110 @@
+From 9cf8bd1e00f9533c2af5c980d9a157d1dae5f853 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Wed, 11 Sep 2019 19:35:45 +0800
+Subject: [PATCH 3784/4256] drm/amd/powerplay: properly set mp1 state for SW
+ SMU suspend/reset routine
+
+Set mp1 state properly for SW SMU suspend/reset routine.
+
+Change-Id: I458d09e79bba2613bb85099938648782ff91b97a
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    | 11 ++---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 40 +++++++++++++++++++
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  2 +
+ 3 files changed, 48 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 8d113a29b0df..078df285b86a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2221,16 +2221,17 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
+ 		/* handle putting the SMC in the appropriate state */
+ 		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
+ 			if (is_support_sw_smu(adev)) {
+-				/* todo */
++				r = smu_set_mp1_state(&adev->smu, adev->mp1_state);
+ 			} else if (adev->powerplay.pp_funcs &&
+ 				   adev->powerplay.pp_funcs->set_mp1_state) {
+ 				r = adev->powerplay.pp_funcs->set_mp1_state(
+ 					adev->powerplay.pp_handle,
+ 					adev->mp1_state);
+-				if (r) {
+-					DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
+-						  adev->mp1_state, r);
+-				}
++			}
++			if (r) {
++				DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
++					  adev->mp1_state, r);
++				return r;
+ 			}
+ 		}
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index e18bfce25dfa..a10387f51e21 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1788,6 +1788,46 @@ int smu_force_clk_levels(struct smu_context *smu,
+ 	return ret;
+ }
+ 
++int smu_set_mp1_state(struct smu_context *smu,
++		      enum pp_mp1_state mp1_state)
++{
++	uint16_t msg;
++	int ret;
++
++	/*
++	 * The SMC is not fully ready. That may be
++	 * expected as the IP may be masked.
++	 * So, just return without error.
++	 */
++	if (!smu->pm_enabled)
++		return 0;
++
++	switch (mp1_state) {
++	case PP_MP1_STATE_SHUTDOWN:
++		msg = SMU_MSG_PrepareMp1ForShutdown;
++		break;
++	case PP_MP1_STATE_UNLOAD:
++		msg = SMU_MSG_PrepareMp1ForUnload;
++		break;
++	case PP_MP1_STATE_RESET:
++		msg = SMU_MSG_PrepareMp1ForReset;
++		break;
++	case PP_MP1_STATE_NONE:
++	default:
++		return 0;
++	}
++
++	/* some asics may not support those messages */
++	if (smu_msg_get_index(smu, msg) < 0)
++		return 0;
++
++	ret = smu_send_smc_msg(smu, msg);
++	if (ret)
++		pr_err("[PrepareMp1] Failed!\n");
++
++	return ret;
++}
++
+ const struct amd_ip_funcs smu_ip_funcs = {
+ 	.name = "smu",
+ 	.early_init = smu_early_init,
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 88f1ee9a2f1d..45da21dc2356 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -836,5 +836,7 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
+ int smu_force_clk_levels(struct smu_context *smu,
+ 			 enum smu_clk_type clk_type,
+ 			 uint32_t mask);
++int smu_set_mp1_state(struct smu_context *smu,
++		      enum pp_mp1_state mp1_state);
+ 
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3785-drm-amd-powerplay-check-SMU-engine-readiness-before-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3785-drm-amd-powerplay-check-SMU-engine-readiness-before-.patch
new file mode 100644
index 00000000..9994a02b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3785-drm-amd-powerplay-check-SMU-engine-readiness-before-.patch
@@ -0,0 +1,73 @@
+From db836f5b5a9251b68576c54fb11b9682235ea734 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Wed, 11 Sep 2019 19:39:34 +0800
+Subject: [PATCH 3785/4256] drm/amd/powerplay: check SMU engine readiness
+ before proceeding on S3 resume
+
+This is especially needed for non-psp loading way.
+
+Change-Id: I1e523168ed4892c34c8cbb66077c3f9288dd8006
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 28 ++++++++++++++++++----
+ 1 file changed, 23 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index a10387f51e21..bc11dff37a02 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1213,11 +1213,10 @@ static int smu_free_memory_pool(struct smu_context *smu)
+ 	return ret;
+ }
+ 
+-static int smu_hw_init(void *handle)
++static int smu_start_smc_engine(struct smu_context *smu)
+ {
+-	int ret;
+-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	struct smu_context *smu = &adev->smu;
++	struct amdgpu_device *adev = smu->adev;
++	int ret = 0;
+ 
+ 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+ 		if (adev->asic_type < CHIP_NAVI10) {
+@@ -1228,8 +1227,21 @@ static int smu_hw_init(void *handle)
+ 	}
+ 
+ 	ret = smu_check_fw_status(smu);
++	if (ret)
++		pr_err("SMC is not ready\n");
++
++	return ret;
++}
++
++static int smu_hw_init(void *handle)
++{
++	int ret;
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	struct smu_context *smu = &adev->smu;
++
++	ret = smu_start_smc_engine(smu);
+ 	if (ret) {
+-		pr_err("SMC firmware status is not correct\n");
++		pr_err("SMU is not ready yet!\n");
+ 		return ret;
+ 	}
+ 
+@@ -1381,6 +1393,12 @@ static int smu_resume(void *handle)
+ 
+ 	mutex_lock(&smu->mutex);
+ 
++	ret = smu_start_smc_engine(smu);
++	if (ret) {
++		pr_err("SMU is not ready yet!\n");
++		return ret;
++	}
++
+ 	ret = smu_smc_table_hw_init(smu, false);
+ 	if (ret)
+ 		goto failed;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3786-drm-amd-powerplay-update-smu11_driver_if_arcturus.h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3786-drm-amd-powerplay-update-smu11_driver_if_arcturus.h.patch
new file mode 100644
index 00000000..c084e7b8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3786-drm-amd-powerplay-update-smu11_driver_if_arcturus.h.patch
@@ -0,0 +1,49 @@
+From dd4b4d1b90bd45c9fc273fcfd17a0800a7ecd307 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 6 Sep 2019 10:08:32 +0800
+Subject: [PATCH 3786/4256] drm/amd/powerplay: update
+ smu11_driver_if_arcturus.h
+
+Also bump the SMU11_DRIVER_IF_VERSION_ARCT.
+
+Change-Id: I786047d93bf4e1f0905069e2c742479740778fe6
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ .../gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h    | 6 +++++-
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h               | 2 +-
+ 2 files changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+index e02950b505fa..40a51a141336 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+@@ -696,7 +696,11 @@ typedef struct {
+   uint8_t      GpioI2cSda;          // Serial Data
+   uint16_t     GpioPadding;
+ 
+-  uint32_t     BoardReserved[9];
++  // Platform input telemetry voltage coefficient
++  uint32_t     BoardVoltageCoeffA;    // decode by /1000
++  uint32_t     BoardVoltageCoeffB;    // decode by /1000
++
++  uint32_t     BoardReserved[7];
+ 
+   // Padding for MMHUB - do not modify this
+   uint32_t     MmHubPadding[8]; // SMU internal use
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 196a97832f6d..af1add570153 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -27,7 +27,7 @@
+ 
+ #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
+ #define SMU11_DRIVER_IF_VERSION_VG20 0x13
+-#define SMU11_DRIVER_IF_VERSION_ARCT 0x09
++#define SMU11_DRIVER_IF_VERSION_ARCT 0x0A
+ #define SMU11_DRIVER_IF_VERSION_NV10 0x33
+ #define SMU11_DRIVER_IF_VERSION_NV12 0x33
+ #define SMU11_DRIVER_IF_VERSION_NV14 0x34
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3787-drm-amdgpu-sriov-add-ring_stop-before-ring_create-in.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3787-drm-amdgpu-sriov-add-ring_stop-before-ring_create-in.patch
new file mode 100644
index 00000000..e5d7b5db
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3787-drm-amdgpu-sriov-add-ring_stop-before-ring_create-in.patch
@@ -0,0 +1,108 @@
+From d9d44114bec4855d582d50108a2a13f1c833148c Mon Sep 17 00:00:00 2001
+From: Jack Zhang <Jack.Zhang1@amd.com>
+Date: Tue, 10 Sep 2019 12:29:14 +0800
+Subject: [PATCH 3787/4256] drm/amdgpu/sriov: add ring_stop before ring_create
+ in psp v11 code
+
+psp  v11 code missed ring stop in ring create function(VMR)
+while psp v3.1 code had the code. This will cause VM destroy1
+fail and psp ring create fail.
+
+For SIOV-VF, ring_stop should not be deleted in ring_create
+function.
+
+Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 61 ++++++++++++++------------
+ 1 file changed, 34 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index 9d5d44cfe813..54de388ae114 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -407,6 +407,34 @@ static bool psp_v11_0_support_vmr_ring(struct psp_context *psp)
+ 	return false;
+ }
+ 
++static int psp_v11_0_ring_stop(struct psp_context *psp,
++			      enum psp_ring_type ring_type)
++{
++	int ret = 0;
++	struct amdgpu_device *adev = psp->adev;
++
++	/* Write the ring destroy command*/
++	if (psp_v11_0_support_vmr_ring(psp))
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
++				     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
++	else
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
++				     GFX_CTRL_CMD_ID_DESTROY_RINGS);
++
++	/* there might be handshake issue with hardware which needs delay */
++	mdelay(20);
++
++	/* Wait for response flag (bit 31) */
++	if (psp_v11_0_support_vmr_ring(psp))
++		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
++				   0x80000000, 0x80000000, false);
++	else
++		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
++				   0x80000000, 0x80000000, false);
++
++	return ret;
++}
++
+ static int psp_v11_0_ring_create(struct psp_context *psp,
+ 				enum psp_ring_type ring_type)
+ {
+@@ -416,6 +444,12 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
+ 	struct amdgpu_device *adev = psp->adev;
+ 
+ 	if (psp_v11_0_support_vmr_ring(psp)) {
++		ret = psp_v11_0_ring_stop(psp, ring_type);
++		if (ret) {
++			DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");
++			return ret;
++		}
++
+ 		/* Write low address of the ring to C2PMSG_102 */
+ 		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
+ 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
+@@ -460,33 +494,6 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
+ 	return ret;
+ }
+ 
+-static int psp_v11_0_ring_stop(struct psp_context *psp,
+-			      enum psp_ring_type ring_type)
+-{
+-	int ret = 0;
+-	struct amdgpu_device *adev = psp->adev;
+-
+-	/* Write the ring destroy command*/
+-	if (psp_v11_0_support_vmr_ring(psp))
+-		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
+-				     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
+-	else
+-		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
+-				     GFX_CTRL_CMD_ID_DESTROY_RINGS);
+-
+-	/* there might be handshake issue with hardware which needs delay */
+-	mdelay(20);
+-
+-	/* Wait for response flag (bit 31) */
+-	if (psp_v11_0_support_vmr_ring(psp))
+-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
+-				   0x80000000, 0x80000000, false);
+-	else
+-		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+-				   0x80000000, 0x80000000, false);
+-
+-	return ret;
+-}
+ 
+ static int psp_v11_0_ring_destroy(struct psp_context *psp,
+ 				 enum psp_ring_type ring_type)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3788-drm-amdgpu-For-Navi12-SRIOV-VF-register-mailbox-func.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3788-drm-amdgpu-For-Navi12-SRIOV-VF-register-mailbox-func.patch
new file mode 100644
index 00000000..1b641d1f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3788-drm-amdgpu-For-Navi12-SRIOV-VF-register-mailbox-func.patch
@@ -0,0 +1,73 @@
+From db8ca3585d94b3285d6c8df7fcbb9f26186f722c Mon Sep 17 00:00:00 2001
+From: Jiange Zhao <Jiange.Zhao@amd.com>
+Date: Wed, 11 Sep 2019 17:29:07 +0800
+Subject: [PATCH 3788/4256] drm/amdgpu: For Navi12 SRIOV VF, register mailbox
+ functions
+
+Mailbox functions and interrupts are only for Navi12 VF.
+
+Register functions and irqs during initialization.
+
+Reviewed-by: Emily Deng <Emily.Deng@amd.com>
+Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index a61f43c0c9df..4c24672be12a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -53,6 +53,7 @@
+ #include "vcn_v2_0.h"
+ #include "dce_virtual.h"
+ #include "mes_v10_1.h"
++#include "mxgpu_nv.h"
+ 
+ static const struct amd_ip_funcs nv_common_ip_funcs;
+ 
+@@ -426,6 +427,9 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ 
+ 	adev->nbio.funcs->detect_hw_virt(adev);
+ 
++	if (amdgpu_sriov_vf(adev))
++		adev->virt.ops = &xgpu_nv_virt_ops;
++
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+@@ -666,16 +670,31 @@ static int nv_common_early_init(void *handle)
+ 		return -EINVAL;
+ 	}
+ 
++	if (amdgpu_sriov_vf(adev)) {
++		amdgpu_virt_init_setting(adev);
++		xgpu_nv_mailbox_set_irq_funcs(adev);
++	}
++
+ 	return 0;
+ }
+ 
+ static int nv_common_late_init(void *handle)
+ {
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++	if (amdgpu_sriov_vf(adev))
++		xgpu_nv_mailbox_get_irq(adev);
++
+ 	return 0;
+ }
+ 
+ static int nv_common_sw_init(void *handle)
+ {
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++	if (amdgpu_sriov_vf(adev))
++		xgpu_nv_mailbox_add_irq_id(adev);
++
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3789-drm-amd-amdgpu-power-up-sdma-engine-when-S3-resume-b.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3789-drm-amd-amdgpu-power-up-sdma-engine-when-S3-resume-b.patch
new file mode 100644
index 00000000..72b655ed
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3789-drm-amd-amdgpu-power-up-sdma-engine-when-S3-resume-b.patch
@@ -0,0 +1,82 @@
+From 0b4d4b4075020fc18b38964b00456a7ce139b49f Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Wed, 11 Sep 2019 13:15:17 +0800
+Subject: [PATCH 3789/4256] drm/amd/amdgpu: power up sdma engine when S3 resume
+ back
+
+The sdma_v4 should be ungated when the IP resume back,
+otherwise it will hang up and resume time out error.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c    |  2 +-
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c     | 10 ++++++----
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c |  3 +++
+ 3 files changed, 10 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+index 357e45fa5711..263265245e19 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+@@ -951,6 +951,7 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
+ 	case AMD_IP_BLOCK_TYPE_UVD:
+ 	case AMD_IP_BLOCK_TYPE_VCN:
+ 	case AMD_IP_BLOCK_TYPE_VCE:
++	case AMD_IP_BLOCK_TYPE_SDMA:
+ 		if (swsmu)
+ 			ret = smu_dpm_set_power_gate(&adev->smu, block_type, gate);
+ 		else
+@@ -959,7 +960,6 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
+ 		break;
+ 	case AMD_IP_BLOCK_TYPE_GMC:
+ 	case AMD_IP_BLOCK_TYPE_ACP:
+-	case AMD_IP_BLOCK_TYPE_SDMA:
+ 		ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu(
+ 				(adev)->powerplay.pp_handle, block_type, gate));
+ 		break;
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 9cf417a76697..06f769acac62 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1803,8 +1803,9 @@ static int sdma_v4_0_hw_init(void *handle)
+ 	int r;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
+-	if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs &&
+-			adev->powerplay.pp_funcs->set_powergating_by_smu)
++	if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs &&
++			adev->powerplay.pp_funcs->set_powergating_by_smu) ||
++			adev->asic_type == CHIP_RENOIR)
+ 		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
+ 
+ 	if (!amdgpu_sriov_vf(adev))
+@@ -1831,8 +1832,9 @@ static int sdma_v4_0_hw_fini(void *handle)
+ 	sdma_v4_0_ctx_switch_enable(adev, false);
+ 	sdma_v4_0_enable(adev, false);
+ 
+-	if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs
+-			&& adev->powerplay.pp_funcs->set_powergating_by_smu)
++	if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs
++			&& adev->powerplay.pp_funcs->set_powergating_by_smu) ||
++			adev->asic_type == CHIP_RENOIR)
+ 		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
+ 
+ 	return 0;
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index bc11dff37a02..b3025bd0ea88 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -400,6 +400,9 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
+ 	case AMD_IP_BLOCK_TYPE_GFX:
+ 		ret = smu_gfx_off_control(smu, gate);
+ 		break;
++	case AMD_IP_BLOCK_TYPE_SDMA:
++		ret = smu_powergate_sdma(smu, gate);
++		break;
+ 	default:
+ 		break;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3790-drm-amdgpu-SRIOV-Navi10-12-VF-doesn-t-support-SMU.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3790-drm-amdgpu-SRIOV-Navi10-12-VF-doesn-t-support-SMU.patch
new file mode 100644
index 00000000..540feb82
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3790-drm-amdgpu-SRIOV-Navi10-12-VF-doesn-t-support-SMU.patch
@@ -0,0 +1,58 @@
+From b650d992404e2902153567219c3344f587fb368c Mon Sep 17 00:00:00 2001
+From: Jiange Zhao <Jiange.Zhao@amd.com>
+Date: Thu, 12 Sep 2019 13:15:35 +0800
+Subject: [PATCH 3790/4256] drm/amdgpu/SRIOV: Navi10/12 VF doesn't support SMU
+
+In SRIOV case, SMU and powerplay are handled in HV.
+
+VF shouldn't have control over SMU and powerplay.
+
+Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
+Reviewed-by: Emily Deng <Emily.Deng@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 4c24672be12a..fb097aa089da 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -438,7 +438,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ 		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+ 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
+-		    is_support_sw_smu(adev))
++		    is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
+ 			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+ 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+@@ -449,7 +449,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ 		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
+ 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
+-		    is_support_sw_smu(adev))
++		    is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
+ 			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
+ 		if (adev->enable_mes)
+@@ -461,7 +461,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ 		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+ 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
+-		    is_support_sw_smu(adev))
++		    is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
+ 			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+ 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+@@ -472,7 +472,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ 		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
+ 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
+-		    is_support_sw_smu(adev))
++		    is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
+ 			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3791-drm-amdgpu-SRIOV-Navi12-SRIOV-VF-doesn-t-load-TOC.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3791-drm-amdgpu-SRIOV-Navi12-SRIOV-VF-doesn-t-load-TOC.patch
new file mode 100644
index 00000000..f5c6e568
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3791-drm-amdgpu-SRIOV-Navi12-SRIOV-VF-doesn-t-load-TOC.patch
@@ -0,0 +1,42 @@
+From 759031f97bebc5a09fb385900937c736ebca3e4c Mon Sep 17 00:00:00 2001
+From: Jiange Zhao <Jiange.Zhao@amd.com>
+Date: Thu, 12 Sep 2019 13:18:41 +0800
+Subject: [PATCH 3791/4256] drm/amdgpu/SRIOV: Navi12 SRIOV VF doesn't load TOC
+
+In SRIOV case, the autoload sequence is the same
+
+as bare metal, except VF won't load TOC.
+
+Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
+Reviewed-by: Emily Deng <Emily.Deng@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index a49b4ccd611e..b954b48f3ddf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -255,7 +255,8 @@ static int psp_tmr_init(struct psp_context *psp)
+ 
+ 	/* For ASICs support RLC autoload, psp will parse the toc
+ 	 * and calculate the total size of TMR needed */
+-	if (psp->toc_start_addr &&
++	if (!amdgpu_sriov_vf(psp->adev) &&
++	    psp->toc_start_addr &&
+ 	    psp->toc_bin_size &&
+ 	    psp->fw_pri_buf) {
+ 		ret = psp_load_toc(psp, &tmr_size);
+@@ -1307,9 +1308,6 @@ int psp_rlc_autoload_start(struct psp_context *psp)
+ 	int ret;
+ 	struct psp_gfx_cmd_resp *cmd;
+ 
+-	if (amdgpu_sriov_vf(psp->adev))
+-		return 0;
+-
+ 	cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
+ 	if (!cmd)
+ 		return -ENOMEM;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3792-drm-amdgpu-grab-the-id-mgr-lock-while-accessing-pass.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3792-drm-amdgpu-grab-the-id-mgr-lock-while-accessing-pass.patch
new file mode 100644
index 00000000..20a375a9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3792-drm-amdgpu-grab-the-id-mgr-lock-while-accessing-pass.patch
@@ -0,0 +1,62 @@
+From 87ba454d8392ee80af5928491857f298f2588638 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Mon, 9 Sep 2019 13:57:32 +0200
+Subject: [PATCH 3792/4256] drm/amdgpu: grab the id mgr lock while accessing
+ passid_mapping
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Need to make sure that we actually dropping the right fence.
+Could be done with RCU as well, but to complicated for a fix.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 12 +++++++++---
+ 1 file changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 31b25d27e50e..6865baac7823 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -1009,10 +1009,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_
+ 		id->oa_base != job->oa_base ||
+ 		id->oa_size != job->oa_size);
+ 	bool vm_flush_needed = job->vm_needs_flush;
+-	bool pasid_mapping_needed = id->pasid != job->pasid ||
+-		!id->pasid_mapping ||
+-		!dma_fence_is_signaled(id->pasid_mapping);
+ 	struct dma_fence *fence = NULL;
++	bool pasid_mapping_needed;
+ 	unsigned patch_offset = 0;
+ 	int r;
+ 
+@@ -1022,6 +1020,12 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_
+ 		pasid_mapping_needed = true;
+ 	}
+ 
++	mutex_lock(&id_mgr->lock);
++	if (id->pasid != job->pasid || !id->pasid_mapping ||
++	    !dma_fence_is_signaled(id->pasid_mapping))
++		pasid_mapping_needed = true;
++	mutex_unlock(&id_mgr->lock);
++
+ 	gds_switch_needed &= !!ring->funcs->emit_gds_switch;
+ 	vm_flush_needed &= !!ring->funcs->emit_vm_flush  &&
+ 			job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
+@@ -1061,9 +1065,11 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_
+ 	}
+ 
+ 	if (pasid_mapping_needed) {
++		mutex_lock(&id_mgr->lock);
+ 		id->pasid = job->pasid;
+ 		dma_fence_put(id->pasid_mapping);
+ 		id->pasid_mapping = dma_fence_get(fence);
++		mutex_unlock(&id_mgr->lock);
+ 	}
+ 	dma_fence_put(fence);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3793-drm-amdgpu-split-the-VM-entity-into-direct-and-delay.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3793-drm-amdgpu-split-the-VM-entity-into-direct-and-delay.patch
new file mode 100644
index 00000000..d8fa04aa
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3793-drm-amdgpu-split-the-VM-entity-into-direct-and-delay.patch
@@ -0,0 +1,148 @@
+From ef5c04c3d93475e3e5ab856779f8963adf380f73 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Fri, 19 Jul 2019 14:41:12 +0200
+Subject: [PATCH 3793/4256] drm/amdgpu: split the VM entity into direct and
+ delayed
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+For page fault handling we need to use a direct update which can't be
+blocked by ongoing user CS.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c     |  6 +++---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c      | 21 +++++++++++++++------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h      |  5 +++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c |  5 +++--
+ 4 files changed, 24 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+index cd15540c5622..dfe155566571 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+@@ -282,7 +282,7 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,
+ 	    !dma_fence_is_later(updates, (*id)->flushed_updates))
+ 	    updates = NULL;
+ 
+-	if ((*id)->owner != vm->entity.fence_context ||
++	if ((*id)->owner != vm->direct.fence_context ||
+ 	    job->vm_pd_addr != (*id)->pd_gpu_addr ||
+ 	    updates || !(*id)->last_flush ||
+ 	    ((*id)->last_flush->context != fence_context &&
+@@ -349,7 +349,7 @@ static int amdgpu_vmid_grab_used(struct amdgpu_vm *vm,
+ 		struct dma_fence *flushed;
+ 
+ 		/* Check all the prerequisites to using this VMID */
+-		if ((*id)->owner != vm->entity.fence_context)
++		if ((*id)->owner != vm->direct.fence_context)
+ 			continue;
+ 
+ 		if ((*id)->pd_gpu_addr != job->vm_pd_addr)
+@@ -449,7 +449,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
+ 	}
+ 
+ 	id->pd_gpu_addr = job->vm_pd_addr;
+-	id->owner = vm->entity.fence_context;
++	id->owner = vm->direct.fence_context;
+ 
+ 	if (job->vm_needs_flush) {
+ 		dma_fence_put(id->last_flush);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 6865baac7823..031d5bd3cf27 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -2654,12 +2654,17 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ 	spin_lock_init(&vm->invalidated_lock);
+ 	INIT_LIST_HEAD(&vm->freed);
+ 
+-	/* create scheduler entity for page table updates */
+-	r = drm_sched_entity_init(&vm->entity, adev->vm_manager.vm_pte_rqs,
++	/* create scheduler entities for page table updates */
++	r = drm_sched_entity_init(&vm->direct, adev->vm_manager.vm_pte_rqs,
+ 				  adev->vm_manager.vm_pte_num_rqs, NULL);
+ 	if (r)
+ 		return r;
+ 
++	r = drm_sched_entity_init(&vm->delayed, adev->vm_manager.vm_pte_rqs,
++				  adev->vm_manager.vm_pte_num_rqs, NULL);
++	if (r)
++		goto error_free_direct;
++
+ 	vm->pte_support_ats = false;
+ 
+ 	if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
+@@ -2688,7 +2693,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ 		bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW;
+ 	r = amdgpu_bo_create(adev, &bp, &root);
+ 	if (r)
+-		goto error_free_sched_entity;
++		goto error_free_delayed;
+ 
+ 	r = amdgpu_bo_reserve(root, true);
+ 	if (r)
+@@ -2731,8 +2736,11 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ 	amdgpu_bo_unref(&vm->root.base.bo);
+ 	vm->root.base.bo = NULL;
+ 
+-error_free_sched_entity:
+-	drm_sched_entity_destroy(&vm->entity);
++error_free_delayed:
++	drm_sched_entity_destroy(&vm->delayed);
++
++error_free_direct:
++	drm_sched_entity_destroy(&vm->direct);
+ 
+ 	return r;
+ }
+@@ -2891,7 +2899,8 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+ 		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
+ 	}
+ 
+-	drm_sched_entity_destroy(&vm->entity);
++	drm_sched_entity_destroy(&vm->direct);
++	drm_sched_entity_destroy(&vm->delayed);
+ 
+ 	if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
+ 		dev_err(adev->dev, "still active bo inside vm\n");
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+index 269e55082737..8bb6d0a5c55d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+@@ -257,8 +257,9 @@ struct amdgpu_vm {
+ 	struct amdgpu_vm_pt     root;
+ 	struct dma_fence	*last_update;
+ 
+-	/* Scheduler entity for page table updates */
+-	struct drm_sched_entity	entity;
++	/* Scheduler entities for page table updates */
++	struct drm_sched_entity	direct;
++	struct drm_sched_entity	delayed;
+ 
+ 	unsigned int		pasid;
+ 	/* dedicated to vm */
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+index ddd181f5ed37..d087d6650d79 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+@@ -99,12 +99,13 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p,
+ 	struct dma_fence *f;
+ 	int r;
+ 
+-	ring = container_of(p->vm->entity.rq->sched, struct amdgpu_ring, sched);
++	ring = container_of(p->vm->delayed.rq->sched, struct amdgpu_ring,
++			    sched);
+ 
+ 	WARN_ON(ib->length_dw == 0);
+ 	amdgpu_ring_pad_ib(ring, ib);
+ 	WARN_ON(ib->length_dw > p->num_dw_left);
+-	r = amdgpu_job_submit(p->job, &p->vm->entity,
++	r = amdgpu_job_submit(p->job, &p->vm->delayed,
+ 			      AMDGPU_FENCE_OWNER_VM, &f);
+ 	if (r)
+ 		goto error;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3794-drm-amdgpu-allow-direct-submission-in-the-VM-backend.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3794-drm-amdgpu-allow-direct-submission-in-the-VM-backend.patch
new file mode 100644
index 00000000..58d83a26
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3794-drm-amdgpu-allow-direct-submission-in-the-VM-backend.patch
@@ -0,0 +1,141 @@
+From ea045338c36f33e51a493279523a73951faeebaa Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Wed, 27 Mar 2019 13:16:18 +0100
+Subject: [PATCH 3794/4256] drm/amdgpu: allow direct submission in the VM
+ backends v2
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This allows us to update page tables directly while in a page fault.
+
+v2: use direct/delayed entities and still wait for moves
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h      |  5 +++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c  | 16 ++++++-------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 25 +++++++++++----------
+ 3 files changed, 26 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+index 8bb6d0a5c55d..7aa15714d600 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+@@ -201,6 +201,11 @@ struct amdgpu_vm_update_params {
+ 	 */
+ 	struct amdgpu_vm *vm;
+ 
++	/**
++	 * @direct: if changes should be made directly
++	 */
++	bool direct;
++
+ 	/**
+ 	 * @pages_addr:
+ 	 *
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
+index 5222d165abfc..a2daeadd770f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
+@@ -49,13 +49,6 @@ static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p, void *owner,
+ {
+ 	int r;
+ 
+-	/* Wait for PT BOs to be idle. PTs share the same resv. object
+-	 * as the root PD BO
+-	 */
+-	r = amdgpu_bo_sync_wait(p->vm->root.base.bo, owner, true);
+-	if (unlikely(r))
+-		return r;
+-
+ 	/* Wait for any BO move to be completed */
+ 	if (exclusive) {
+ 		r = dma_fence_wait(exclusive, true);
+@@ -63,7 +56,14 @@ static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p, void *owner,
+ 			return r;
+ 	}
+ 
+-	return 0;
++	/* Don't wait for submissions during page fault */
++	if (p->direct)
++		return 0;
++
++	/* Wait for PT BOs to be idle. PTs share the same resv. object
++	 * as the root PD BO
++	 */
++	return amdgpu_bo_sync_wait(p->vm->root.base.bo, owner, true);
+ }
+ 
+ /**
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+index d087d6650d79..38c966cedc26 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+@@ -68,17 +68,19 @@ static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p,
+ 	if (r)
+ 		return r;
+ 
++	p->num_dw_left = ndw;
++
++	/* Wait for moves to be completed */
+ 	r = amdgpu_sync_fence(p->adev, &p->job->sync, exclusive, false);
+ 	if (r)
+ 		return r;
+ 
+-	r = amdgpu_sync_resv(p->adev, &p->job->sync, root->tbo.resv,
+-			     owner, false);
+-	if (r)
+-		return r;
++	/* Don't wait for any submissions during page fault handling */
++	if (p->direct)
++		return 0;
+ 
+-	p->num_dw_left = ndw;
+-	return 0;
++	return amdgpu_sync_resv(p->adev, &p->job->sync, root->tbo.resv,
++				owner, false);
+ }
+ 
+ /**
+@@ -95,23 +97,23 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p,
+ {
+ 	struct amdgpu_bo *root = p->vm->root.base.bo;
+ 	struct amdgpu_ib *ib = p->job->ibs;
++	struct drm_sched_entity *entity;
+ 	struct amdgpu_ring *ring;
+ 	struct dma_fence *f;
+ 	int r;
+ 
+-	ring = container_of(p->vm->delayed.rq->sched, struct amdgpu_ring,
+-			    sched);
++	entity = p->direct ? &p->vm->direct : &p->vm->delayed;
++	ring = container_of(entity->rq->sched, struct amdgpu_ring, sched);
+ 
+ 	WARN_ON(ib->length_dw == 0);
+ 	amdgpu_ring_pad_ib(ring, ib);
+ 	WARN_ON(ib->length_dw > p->num_dw_left);
+-	r = amdgpu_job_submit(p->job, &p->vm->delayed,
+-			      AMDGPU_FENCE_OWNER_VM, &f);
++	r = amdgpu_job_submit(p->job, entity, AMDGPU_FENCE_OWNER_VM, &f);
+ 	if (r)
+ 		goto error;
+ 
+ 	amdgpu_bo_fence(root, f, true);
+-	if (fence)
++	if (fence && !p->direct)
+ 		swap(*fence, f);
+ 	dma_fence_put(f);
+ 	return 0;
+@@ -121,7 +123,6 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p,
+ 	return r;
+ }
+ 
+-
+ /**
+  * amdgpu_vm_sdma_copy_ptes - copy the PTEs from mapping
+  *
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3795-drm-amdgpu-allow-direct-submission-of-PDE-updates-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3795-drm-amdgpu-allow-direct-submission-of-PDE-updates-v2.patch
new file mode 100644
index 00000000..6b8a4263
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3795-drm-amdgpu-allow-direct-submission-of-PDE-updates-v2.patch
@@ -0,0 +1,115 @@
+From 1f2c49ee82ebb7671f67d82bf6328c096de47423 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Thu, 14 Mar 2019 09:10:01 +0100
+Subject: [PATCH 3795/4256] drm/amdgpu: allow direct submission of PDE updates
+ v2
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+For handling PDE updates directly in the fault handler.
+
+v2: fix typo in comment
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c           | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c          | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c           | 8 +++++---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h           | 4 ++--
+ 5 files changed, 10 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index 7d540d5f4f9a..8288cd965f8e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -375,7 +375,7 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
+ 	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
+ 	int ret;
+ 
+-	ret = amdgpu_vm_update_directories(adev, vm);
++	ret = amdgpu_vm_update_pdes(adev, vm, false);
+ 	if (ret)
+ 		return ret;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+index 901ce33cc481..34b793b980a1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+@@ -838,7 +838,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
+ 	if (r)
+ 		return r;
+ 
+-	r = amdgpu_vm_update_directories(adev, vm);
++	r = amdgpu_vm_update_pdes(adev, vm, false);
+ 	if (r)
+ 		return r;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+index 3642abd765b6..cbd09e9b1092 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+@@ -610,7 +610,7 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
+ 			goto error;
+ 	}
+ 
+-	r = amdgpu_vm_update_directories(adev, vm);
++	r = amdgpu_vm_update_pdes(adev, vm, false);
+ 
+ error:
+ 	if (r && r != -ERESTARTSYS)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 031d5bd3cf27..c787f71ef6a0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -1200,18 +1200,19 @@ static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
+ }
+ 
+ /*
+- * amdgpu_vm_update_directories - make sure that all directories are valid
++ * amdgpu_vm_update_pdes - make sure that all directories are valid
+  *
+  * @adev: amdgpu_device pointer
+  * @vm: requested vm
++ * @direct: submit directly to the paging queue
+  *
+  * Makes sure all directories are up to date.
+  *
+  * Returns:
+  * 0 for success, error for failure.
+  */
+-int amdgpu_vm_update_directories(struct amdgpu_device *adev,
+-				 struct amdgpu_vm *vm)
++int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
++			  struct amdgpu_vm *vm, bool direct)
+ {
+ 	struct amdgpu_vm_update_params params;
+ 	int r;
+@@ -1222,6 +1223,7 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev,
+ 	memset(&params, 0, sizeof(params));
+ 	params.adev = adev;
+ 	params.vm = vm;
++	params.direct = direct;
+ 
+ 	r = vm->update_funcs->prepare(&params, AMDGPU_FENCE_OWNER_VM, NULL);
+ 	if (r)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+index 7aa15714d600..3f1335295c00 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+@@ -366,8 +366,8 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ 			      int (*callback)(void *p, struct amdgpu_bo *bo),
+ 			      void *param);
+ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
+-int amdgpu_vm_update_directories(struct amdgpu_device *adev,
+-				 struct amdgpu_vm *vm);
++int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
++			  struct amdgpu_vm *vm, bool direct);
+ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
+ 			  struct amdgpu_vm *vm,
+ 			  struct dma_fence **fence);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3796-drm-amdgpu-allow-direct-submission-of-PTE-updates.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3796-drm-amdgpu-allow-direct-submission-of-PTE-updates.patch
new file mode 100644
index 00000000..a788b732
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3796-drm-amdgpu-allow-direct-submission-of-PTE-updates.patch
@@ -0,0 +1,86 @@
+From 9ba9bc43fa7d25e1127aa7be0afb3b404b4025c1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Wed, 27 Mar 2019 13:59:23 +0100
+Subject: [PATCH 3796/4256] drm/amdgpu: allow direct submission of PTE updates
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+For handling PTE updates directly in the fault handler.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 18 ++++++++++--------
+ 1 file changed, 10 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index c787f71ef6a0..364a17683506 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -1457,13 +1457,14 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
+  * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
+  *
+  * @adev: amdgpu_device pointer
+- * @exclusive: fence we need to sync to
+- * @pages_addr: DMA addresses to use for mapping
+  * @vm: requested vm
++ * @direct: direct submission in a page fault
++ * @exclusive: fence we need to sync to
+  * @start: start of mapped range
+  * @last: last mapped entry
+  * @flags: flags for the entries
+  * @addr: addr to set the area to
++ * @pages_addr: DMA addresses to use for mapping
+  * @fence: optional resulting fence
+  *
+  * Fill in the page table entries between @start and @last.
+@@ -1472,11 +1473,11 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
+  * 0 for success, -EINVAL for failure.
+  */
+ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
++				       struct amdgpu_vm *vm, bool direct,
+ 				       struct dma_fence *exclusive,
+-				       dma_addr_t *pages_addr,
+-				       struct amdgpu_vm *vm,
+ 				       uint64_t start, uint64_t last,
+ 				       uint64_t flags, uint64_t addr,
++				       dma_addr_t *pages_addr,
+ 				       struct dma_fence **fence)
+ {
+ 	struct amdgpu_vm_update_params params;
+@@ -1486,6 +1487,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
+ 	memset(&params, 0, sizeof(params));
+ 	params.adev = adev;
+ 	params.vm = vm;
++	params.direct = direct;
+ 	params.pages_addr = pages_addr;
+ 
+ 	/* sync to everything on unmapping */
+@@ -1617,9 +1619,9 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
+ 		}
+ 
+ 		last = min((uint64_t)mapping->last, start + max_entries - 1);
+-		r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm,
++		r = amdgpu_vm_bo_update_mapping(adev, vm, false, exclusive,
+ 						start, last, flags, addr,
+-						fence);
++						dma_addr, fence);
+ 		if (r)
+ 			return r;
+ 
+@@ -1913,9 +1915,9 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
+ 		    mapping->start < AMDGPU_GMC_HOLE_START)
+ 			init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
+ 
+-		r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,
++		r = amdgpu_vm_bo_update_mapping(adev, vm, false, NULL,
+ 						mapping->start, mapping->last,
+-						init_pte_value, 0, &f);
++						init_pte_value, 0, NULL, &f);
+ 		amdgpu_vm_free_mapping(adev, vm, mapping, f);
+ 		if (r) {
+ 			dma_fence_put(f);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3797-drm-amdgpu-allow-direct-submission-of-clears.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3797-drm-amdgpu-allow-direct-submission-of-clears.patch
new file mode 100644
index 00000000..922210e9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3797-drm-amdgpu-allow-direct-submission-of-clears.patch
@@ -0,0 +1,96 @@
+From 0a4b5606d82154cb9e4f1ca2adcea9ffbcc5a1ca Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Thu, 28 Mar 2019 10:53:33 +0100
+Subject: [PATCH 3797/4256] drm/amdgpu: allow direct submission of clears
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+For handling PD/PT clears directly in the fault handler.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 +++++++++++------
+ 1 file changed, 11 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 364a17683506..b42436fafe4b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -670,6 +670,7 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm)
+  * @adev: amdgpu_device pointer
+  * @vm: VM to clear BO from
+  * @bo: BO to clear
++ * @direct: use a direct update
+  *
+  * Root PD needs to be reserved when calling this.
+  *
+@@ -678,7 +679,8 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm)
+  */
+ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
+ 			      struct amdgpu_vm *vm,
+-			      struct amdgpu_bo *bo)
++			      struct amdgpu_bo *bo,
++			      bool direct)
+ {
+ 	struct ttm_operation_ctx ctx = { true, false };
+ 	unsigned level = adev->vm_manager.root_level;
+@@ -736,6 +738,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
+         memset(&params, 0, sizeof(params));
+         params.adev = adev;
+         params.vm = vm;
++	params.direct = direct;
+ 
+         r = vm->update_funcs->prepare(&params, AMDGPU_FENCE_OWNER_KFD, NULL);
+ 
+@@ -825,7 +828,8 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+  */
+ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
+ 			       struct amdgpu_vm *vm,
+-			       struct amdgpu_vm_pt_cursor *cursor)
++			       struct amdgpu_vm_pt_cursor *cursor,
++			       bool direct)
+ {
+ 	struct amdgpu_vm_pt *entry = cursor->entry;
+ 	struct amdgpu_bo_param bp;
+@@ -858,7 +862,7 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
+ 	pt->parent = amdgpu_bo_ref(cursor->parent->base.bo);
+ 	amdgpu_vm_bo_base_init(&entry->base, vm, pt);
+ 
+-	r = amdgpu_vm_clear_bo(adev, vm, pt);
++	r = amdgpu_vm_clear_bo(adev, vm, pt, direct);
+ 	if (r)
+ 		goto error_free_pt;
+ 
+@@ -1366,7 +1370,8 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
+ 		uint64_t incr, entry_end, pe_start;
+ 		struct amdgpu_bo *pt;
+ 
+-		r = amdgpu_vm_alloc_pts(params->adev, params->vm, &cursor);
++		r = amdgpu_vm_alloc_pts(params->adev, params->vm, &cursor,
++					params->direct);
+ 		if (r)
+ 			return r;
+ 
+@@ -2709,7 +2714,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ 
+ 	amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
+ 
+-	r = amdgpu_vm_clear_bo(adev, vm, root);
++	r = amdgpu_vm_clear_bo(adev, vm, root, false);
+ 	if (r)
+ 		goto error_unreserve;
+ 
+@@ -2820,7 +2825,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+ 	 */
+ 	if (pte_support_ats != vm->pte_support_ats) {
+ 		vm->pte_support_ats = pte_support_ats;
+-		r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo);
++		r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo, false);
+ 		if (r)
+ 			goto error;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3798-drm-amdgpu-allocate-PDs-PTs-with-no_gpu_wait-in-a-pa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3798-drm-amdgpu-allocate-PDs-PTs-with-no_gpu_wait-in-a-pa.patch
new file mode 100644
index 00000000..2d50572e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3798-drm-amdgpu-allocate-PDs-PTs-with-no_gpu_wait-in-a-pa.patch
@@ -0,0 +1,88 @@
+From c70e9556a9c404989fd017291faefa9cadd30cd1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Wed, 17 Jul 2019 14:58:02 +0200
+Subject: [PATCH 3798/4256] drm/amdgpu: allocate PDs/PTs with no_gpu_wait in a
+ page fault
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+While handling a page fault we can't wait for other ongoing GPU
+operations or we can potentially run into deadlocks.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     | 8 +++++---
+ 3 files changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+index 83df25888e02..c82d35faf91c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+@@ -472,7 +472,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
+ {
+ 	struct ttm_operation_ctx ctx = {
+ 		.interruptible = (bp->type != ttm_bo_type_kernel),
+-		.no_wait_gpu = false,
++		.no_wait_gpu = bp->no_wait_gpu,
+ 		.resv = bp->resv,
+ 		.flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
+ 	};
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+index aed30cc3f4ca..c3047d2d1833 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+@@ -41,6 +41,7 @@ struct amdgpu_bo_param {
+ 	u32				preferred_domain;
+ 	u64				flags;
+ 	enum ttm_bo_type		type;
++	bool				no_wait_gpu;
+ 	struct reservation_object	*resv;
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index b42436fafe4b..9bfa2c295c32 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -794,7 +794,8 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
+  * @bp: resulting BO allocation parameters
+  */
+ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+-			       int level, struct amdgpu_bo_param *bp)
++			       int level, bool direct,
++			       struct amdgpu_bo_param *bp)
+ {
+ 	memset(bp, 0, sizeof(*bp));
+ 
+@@ -809,6 +810,7 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ 	else if (!vm->root.base.bo || vm->root.base.bo->shadow)
+ 		bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
+ 	bp->type = ttm_bo_type_kernel;
++	bp->no_wait_gpu = direct;
+ 	if (vm->root.base.bo)
+ 		bp->resv = vm->root.base.bo->tbo.resv;
+ }
+@@ -850,7 +852,7 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
+ 	if (entry->base.bo)
+ 		return 0;
+ 
+-	amdgpu_vm_bo_param(adev, vm, cursor->level, &bp);
++	amdgpu_vm_bo_param(adev, vm, cursor->level, direct, &bp);
+ 
+ 	r = amdgpu_bo_create(adev, &bp, &pt);
+ 	if (r)
+@@ -2697,7 +2699,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ 		vm->update_funcs = &amdgpu_vm_sdma_funcs;
+ 	vm->last_update = NULL;
+ 
+-	amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp);
++	amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, false, &bp);
+ 	if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)
+ 		bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW;
+ 	r = amdgpu_bo_create(adev, &bp, &root);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3799-drm-amdgpu-reserve-the-root-PD-while-freeing-PASIDs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3799-drm-amdgpu-reserve-the-root-PD-while-freeing-PASIDs.patch
new file mode 100644
index 00000000..12fd01c9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3799-drm-amdgpu-reserve-the-root-PD-while-freeing-PASIDs.patch
@@ -0,0 +1,70 @@
+From edbc0814ec2a30318abe12a172d0f83162b735d9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Wed, 17 Jul 2019 09:58:47 +0200
+Subject: [PATCH 3799/4256] drm/amdgpu: reserve the root PD while freeing
+ PASIDs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Free the pasid only while the root PD is reserved. This prevents use after
+free in the page fault handling.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 20 +++++++++-----------
+ 1 file changed, 9 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 9bfa2c295c32..144cb2e0e9aa 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -2898,18 +2898,26 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+ 	struct amdgpu_bo_va_mapping *mapping, *tmp;
+ 	bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
+ 	struct amdgpu_bo *root;
+-	int i, r;
++	int i;
+ 
+ 	amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
+ 
++	root = amdgpu_bo_ref(vm->root.base.bo);
++	amdgpu_bo_reserve(root, true);
+ 	if (vm->pasid) {
+ 		unsigned long flags;
+ 
+ 		spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
+ 		idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
+ 		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
++		vm->pasid = 0;
+ 	}
+ 
++	amdgpu_vm_free_pts(adev, vm, NULL);
++	amdgpu_bo_unreserve(root);
++	amdgpu_bo_unref(&root);
++	WARN_ON(vm->root.base.bo);
++
+ 	drm_sched_entity_destroy(&vm->direct);
+ 	drm_sched_entity_destroy(&vm->delayed);
+ 
+@@ -2934,16 +2942,6 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+ 		amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
+ 	}
+ 
+-	root = amdgpu_bo_ref(vm->root.base.bo);
+-	r = amdgpu_bo_reserve(root, true);
+-	if (r) {
+-		dev_err(adev->dev, "Leaking page tables because BO reservation failed\n");
+-	} else {
+-		amdgpu_vm_free_pts(adev, vm, NULL);
+-		amdgpu_bo_unreserve(root);
+-	}
+-	amdgpu_bo_unref(&root);
+-	WARN_ON(vm->root.base.bo);
+ 	dma_fence_put(vm->last_update);
+ 	for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
+ 		amdgpu_vmid_free_reserved(adev, vm, i);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3800-drm-amdgpu-add-graceful-VM-fault-handling-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3800-drm-amdgpu-add-graceful-VM-fault-handling-v3.patch
new file mode 100644
index 00000000..88f5ae2f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3800-drm-amdgpu-add-graceful-VM-fault-handling-v3.patch
@@ -0,0 +1,134 @@
+From 7741229a1c0e20ffe2824b5122694c2822d86b1d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Fri, 7 Dec 2018 15:18:43 +0100
+Subject: [PATCH 3800/4256] drm/amdgpu: add graceful VM fault handling v3
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Next step towards HMM support. For now just silence the retry fault and
+optionally redirect the request to the dummy page.
+
+v2: make sure the VM is not destroyed while we handle the fault.
+v3: fix VM destroy check, cleanup comments
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 73 ++++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  2 +
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |  4 ++
+ 3 files changed, 79 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 144cb2e0e9aa..f0daa5e20f3d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -3079,3 +3079,76 @@ void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
+ 		}
+ 	}
+ }
++
++/**
++ * amdgpu_vm_handle_fault - graceful handling of VM faults.
++ * @adev: amdgpu device pointer
++ * @pasid: PASID of the VM
++ * @addr: Address of the fault
++ *
++ * Try to gracefully handle a VM fault. Return true if the fault was handled and
++ * shouldn't be reported any more.
++ */
++bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, unsigned int pasid,
++			    uint64_t addr)
++{
++	struct amdgpu_bo *root;
++	uint64_t value, flags;
++	struct amdgpu_vm *vm;
++	long r;
++
++	spin_lock(&adev->vm_manager.pasid_lock);
++	vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
++	if (vm)
++		root = amdgpu_bo_ref(vm->root.base.bo);
++	else
++		root = NULL;
++	spin_unlock(&adev->vm_manager.pasid_lock);
++
++	if (!root)
++		return false;
++
++	r = amdgpu_bo_reserve(root, true);
++	if (r)
++		goto error_unref;
++
++	/* Double check that the VM still exists */
++	spin_lock(&adev->vm_manager.pasid_lock);
++	vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
++	if (vm && vm->root.base.bo != root)
++		vm = NULL;
++	spin_unlock(&adev->vm_manager.pasid_lock);
++	if (!vm)
++		goto error_unlock;
++
++	addr /= AMDGPU_GPU_PAGE_SIZE;
++	flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
++		AMDGPU_PTE_SYSTEM;
++
++	if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
++		/* Redirect the access to the dummy page */
++		value = adev->dummy_page_addr;
++		flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
++			AMDGPU_PTE_WRITEABLE;
++	} else {
++		/* Let the hw retry silently on the PTE */
++		value = 0;
++	}
++
++	r = amdgpu_vm_bo_update_mapping(adev, vm, true, NULL, addr, addr + 1,
++					flags, value, NULL, NULL);
++	if (r)
++		goto error_unlock;
++
++	r = amdgpu_vm_update_pdes(adev, vm, true);
++
++error_unlock:
++	amdgpu_bo_unreserve(root);
++	if (r < 0)
++		DRM_ERROR("Can't handle page fault (%ld)\n", r);
++
++error_unref:
++	amdgpu_bo_unref(&root);
++
++	return false;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+index 3f1335295c00..5fbb26a0e1d8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+@@ -413,6 +413,8 @@ void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
+ 
+ void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
+ 			     struct amdgpu_task_info *task_info);
++bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, unsigned int pasid,
++			    uint64_t addr);
+ 
+ void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 3dde208fa0c6..fe63f64c4db3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -376,6 +376,10 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
+ 	}
+ 
+ 	/* If it's the first fault for this address, process it normally */
++	if (retry_fault && !in_interrupt() &&
++	    amdgpu_vm_handle_fault(adev, entry->pasid, addr))
++		return 1; /* This also prevents sending it to KFD */
++
+ 	if (!amdgpu_sriov_vf(adev)) {
+ 		/*
+ 		 * Issue a dummy read to wait for the status register to
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3801-drm-amdgpu-remove-needless-usage-of-ifdef.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3801-drm-amdgpu-remove-needless-usage-of-ifdef.patch
new file mode 100644
index 00000000..eabfcfba
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3801-drm-amdgpu-remove-needless-usage-of-ifdef.patch
@@ -0,0 +1,50 @@
+From 96c669b5cf7448b05ef1dae4763e5a66988fe289 Mon Sep 17 00:00:00 2001
+From: Shirish S <shirish.s@amd.com>
+Date: Thu, 12 Sep 2019 12:03:55 +0530
+Subject: [PATCH 3801/4256] drm/amdgpu: remove needless usage of #ifdef
+
+define sched_policy in case CONFIG_HSA_AMD is not
+enabled, with this there is no need to check for CONFIG_HSA_AMD
+else where in driver code.
+
+Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Shirish S <shirish.s@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 2 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +-----
+ 2 files changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 2f6d165a1ac0..8c2c52fe43a9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -175,6 +175,8 @@ extern int amdgpu_noretry;
+ extern int amdgpu_force_asic_type;
+ #ifdef CONFIG_HSA_AMD
+ extern int sched_policy;
++#else
++static const int sched_policy = KFD_SCHED_POLICY_HWS;
+ #endif
+ 
+ #ifdef CONFIG_DRM_AMDGPU_SI
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 078df285b86a..d3152aa16396 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1624,11 +1624,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
+ 	}
+ 
+ 	adev->pm.pp_feature = amdgpu_pp_feature_mask;
+-	if (amdgpu_sriov_vf(adev)
+-	    #ifdef CONFIG_HSA_AMD
+-	    || sched_policy == KFD_SCHED_POLICY_NO_HWS
+-	    #endif
+-	    )
++	if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
+ 		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ 
+ 	for (i = 0; i < adev->num_ip_blocks; i++) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3802-Revert-drm-amdgpu-nbio7.4-add-hw-bug-workaround-for-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3802-Revert-drm-amdgpu-nbio7.4-add-hw-bug-workaround-for-.patch
new file mode 100644
index 00000000..f87d7f45
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3802-Revert-drm-amdgpu-nbio7.4-add-hw-bug-workaround-for-.patch
@@ -0,0 +1,41 @@
+From 3b043c7fe5efc7c7ff437957f45a1356dc40e484 Mon Sep 17 00:00:00 2001
+From: Kent Russell <kent.russell@amd.com>
+Date: Tue, 10 Sep 2019 15:48:55 -0400
+Subject: [PATCH 3802/4256] Revert "drm/amdgpu/nbio7.4: add hw bug workaround
+ for vega20"
+
+This reverts commit e01f2d41895102d824c6b8f5e011dd5e286d5e8b.
+
+VG20 did not require this workaround, as the fix is in the VBIOS.
+Leave VG10/12 workaround as some older shipped cards do not have the
+VBIOS fix in place, and the kernel workaround is required in those
+situations
+
+Change-Id: I2d7c394ce9d205d97be6acfa5edc4635951fdadf
+Signed-off-by: Kent Russell <kent.russell@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index b776332d979f..238c2483496a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -308,13 +308,7 @@ static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev)
+ 
+ static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
+ {
+-	uint32_t def, data;
+-
+-	def = data = RREG32_PCIE(smnPCIE_CI_CNTL);
+-	data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);
+ 
+-	if (def != data)
+-		WREG32_PCIE(smnPCIE_CI_CNTL, data);
+ }
+ 
+ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3803-drm-amd-display-rename-variable-eanble-enable.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3803-drm-amd-display-rename-variable-eanble-enable.patch
new file mode 100644
index 00000000..526c8e30
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3803-drm-amd-display-rename-variable-eanble-enable.patch
@@ -0,0 +1,50 @@
+From b36b98101da1599c5fa130fdb0d09851a2003335 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Fri, 13 Sep 2019 09:02:48 +0100
+Subject: [PATCH 3803/4256] drm/amd/display: rename variable eanble -> enable
+
+There is a spelling mistake in the variable name eanble,
+rename it to enable.
+
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+index 31b698bf9cfc..8aa937f496c4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+@@ -606,11 +606,11 @@ static void dce_mi_allocate_dmif(
+ 	}
+ 
+ 	if (dce_mi->wa.single_head_rdreq_dmif_limit) {
+-		uint32_t eanble =  (total_stream_num > 1) ? 0 :
++		uint32_t enable =  (total_stream_num > 1) ? 0 :
+ 				dce_mi->wa.single_head_rdreq_dmif_limit;
+ 
+ 		REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT,
+-				ENABLE, eanble);
++				ENABLE, enable);
+ 	}
+ }
+ 
+@@ -636,11 +636,11 @@ static void dce_mi_free_dmif(
+ 			10, 3500);
+ 
+ 	if (dce_mi->wa.single_head_rdreq_dmif_limit) {
+-		uint32_t eanble =  (total_stream_num > 1) ? 0 :
++		uint32_t enable =  (total_stream_num > 1) ? 0 :
+ 				dce_mi->wa.single_head_rdreq_dmif_limit;
+ 
+ 		REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT,
+-				ENABLE, eanble);
++				ENABLE, enable);
+ 	}
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3804-drm-amdgpu-Check-for-valid-number-of-registers-to-re.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3804-drm-amdgpu-Check-for-valid-number-of-registers-to-re.patch
new file mode 100644
index 00000000..7160056a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3804-drm-amdgpu-Check-for-valid-number-of-registers-to-re.patch
@@ -0,0 +1,36 @@
+From 7a7cd1730ad34efcf3b041fa12b8f1c4e96b06cc Mon Sep 17 00:00:00 2001
+From: Trek <trek00@inbox.ru>
+Date: Sat, 31 Aug 2019 21:25:36 +0200
+Subject: [PATCH 3804/4256] drm/amdgpu: Check for valid number of registers to
+ read
+
+Do not try to allocate any amount of memory requested by the user.
+Instead limit it to 128 registers. Actually the longest series of
+consecutive allowed registers are 48, mmGB_TILE_MODE0-31 and
+mmGB_MACROTILE_MODE0-15 (0x2644-0x2673).
+
+Bug: https://bugs.freedesktop.org/show_bug.cgi?id=111273
+Signed-off-by: Trek <trek00@inbox.ru>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 9d4e71ee8791..9be4c182242f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -694,6 +694,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
+ 		if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
+ 			sh_num = 0xffffffff;
+ 
++		if (info->read_mmr_reg.count > 128)
++			return -EINVAL;
++
+ 		regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
+ 		if (!regs)
+ 			return -ENOMEM;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3805-drm-amd-be-quiet-when-no-SAD-block-is-found.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3805-drm-amd-be-quiet-when-no-SAD-block-is-found.patch
new file mode 100644
index 00000000..3bdf4ffa
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3805-drm-amd-be-quiet-when-no-SAD-block-is-found.patch
@@ -0,0 +1,123 @@
+From c8fe40264bfdb0cae6838f8fdbe88100c409fb2d Mon Sep 17 00:00:00 2001
+From: Jean Delvare <jdelvare@suse.de>
+Date: Wed, 4 Sep 2019 11:12:48 +0200
+Subject: [PATCH 3805/4256] drm/amd: be quiet when no SAD block is found
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It is fine for displays without audio functionality to not provide
+any SAD block in their EDID. Do not log an error in that case,
+just return quietly.
+
+This fixes half of bug fdo#107825:
+https://bugs.freedesktop.org/show_bug.cgi?id=107825
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Jean Delvare <jdelvare@suse.de>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: "Christian König" <christian.koenig@amd.com>
+Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com>
+Cc: David Airlie <airlied@linux.ie>
+Cc: Daniel Vetter <daniel@ffwll.ch>
+Cc: Harry Wentland <harry.wentland@amd.com>
+Cc: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c                    | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c                    | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c                     | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c                     | 4 ++--
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 7 +++----
+ 5 files changed, 11 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+index 6cc3498fce9e..c35181e2bfe7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+@@ -1349,10 +1349,10 @@ static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
+ 	}
+ 
+ 	sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
+-	if (sad_count <= 0) {
++	if (sad_count < 0)
+ 		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
++	if (sad_count <= 0)
+ 		return;
+-	}
+ 	BUG_ON(!sads);
+ 
+ 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+index 73b91e1f1cd9..f459fc70074c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+@@ -1375,10 +1375,10 @@ static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
+ 	}
+ 
+ 	sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
+-	if (sad_count <= 0) {
++	if (sad_count < 0)
+ 		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
++	if (sad_count <= 0)
+ 		return;
+-	}
+ 	BUG_ON(!sads);
+ 
+ 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+index 04c81df035c3..bcea8a1a6ba6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+@@ -1252,10 +1252,10 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)
+ 	}
+ 
+ 	sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
+-	if (sad_count <= 0) {
++	if (sad_count < 0)
+ 		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
++	if (sad_count <= 0)
+ 		return;
+-	}
+ 
+ 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
+ 		u32 tmp = 0;
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+index b239b04bd6c0..37fd742ab62d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+@@ -1302,10 +1302,10 @@ static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
+ 	}
+ 
+ 	sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
+-	if (sad_count <= 0) {
++	if (sad_count < 0)
+ 		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
++	if (sad_count <= 0)
+ 		return;
+-	}
+ 	BUG_ON(!sads);
+ 
+ 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+index 1f0c8821af53..d14284602ced 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+@@ -98,11 +98,10 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
+ 			(struct edid *) edid->raw_edid);
+ 
+ 	sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
+-	if (sad_count <= 0) {
+-		DRM_INFO("SADs count is: %d, don't need to read it\n",
+-				sad_count);
++	if (sad_count < 0)
++		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
++	if (sad_count <= 0)
+ 		return result;
+-	}
+ 
+ 	edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT;
+ 	for (i = 0; i < edid_caps->audio_mode_count; ++i) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3806-drm-amdgpu-remove-the-redundant-null-checks.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3806-drm-amdgpu-remove-the-redundant-null-checks.patch
new file mode 100644
index 00000000..5c60bfb9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3806-drm-amdgpu-remove-the-redundant-null-checks.patch
@@ -0,0 +1,45 @@
+From 5dfdec6f30b28e528178934f26c268aa15fe85be Mon Sep 17 00:00:00 2001
+From: zhong jiang <zhongjiang@huawei.com>
+Date: Tue, 3 Sep 2019 14:15:05 +0800
+Subject: [PATCH 3806/4256] drm/amdgpu: remove the redundant null checks
+
+debugfs_remove and kfree has taken the null check in account.
+hence it is unnecessary to check it. Just remove the condition.
+No functional change.
+
+This issue was detected by using the Coccinelle software.
+
+Signed-off-by: zhong jiang <zhongjiang@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+index 79c8cf61c577..f68438e8f092 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+@@ -1074,8 +1074,7 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
+ 
+ 	ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
+ 
+-	if (fences)
+-		kfree(fences);
++	kfree(fences);
+ 
+ 	return 0;
+ }
+@@ -1100,8 +1099,7 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
+ 
+ void amdgpu_debugfs_preempt_cleanup(struct amdgpu_device *adev)
+ {
+-	if (adev->debugfs_preempt)
+-		debugfs_remove(adev->debugfs_preempt);
++	debugfs_remove(adev->debugfs_preempt);
+ }
+ 
+ #else
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3807-drm-amdkfd-Swap-trap-temporary-registers-in-gfx10-tr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3807-drm-amdkfd-Swap-trap-temporary-registers-in-gfx10-tr.patch
new file mode 100644
index 00000000..3469dcb5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3807-drm-amdkfd-Swap-trap-temporary-registers-in-gfx10-tr.patch
@@ -0,0 +1,59 @@
+From 07dcdb04449c5d22090041f20ce4df66f9b9c1c1 Mon Sep 17 00:00:00 2001
+From: Jay Cornwall <jay.cornwall@amd.com>
+Date: Thu, 12 Sep 2019 14:03:41 -0500
+Subject: [PATCH 3807/4256] drm/amdkfd: Swap trap temporary registers in gfx10
+ trap handler
+
+ttmp[4:5] hold information useful to the debugger. Use ttmp[14:15]
+instead, aligning implementation with gfx9 trap handler.
+
+Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
+Reviewed-by: shaoyun liu <Shaoyun.liu@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h         |  6 +++---
+ drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm | 10 +++++-----
+ 2 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+index a8cf82d46109..901fe3590165 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+@@ -694,10 +694,10 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
+ 	0x003f8000, 0x8f6f896f,
+ 	0x88776f77, 0x8a6eff6e,
+ 	0x023f8000, 0xb9eef807,
+-	0xb970f812, 0xb971f813,
+-	0x8ff08870, 0xf4051bb8,
++	0xb97af812, 0xb97bf813,
++	0x8ffa887a, 0xf4051bbd,
+ 	0xfa000000, 0xbf8cc07f,
+-	0xf4051c38, 0xfa000008,
++	0xf4051ebd, 0xfa000008,
+ 	0xbf8cc07f, 0x87ee6e6e,
+ 	0xbf840001, 0xbe80206e,
+ 	0xb971f803, 0x8771ff71,
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
+index 35986219ce5f..cdaa523ce6be 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
+@@ -187,12 +187,12 @@ L_FETCH_2ND_TRAP:
+ 	// Read second-level TBA/TMA from first-level TMA and jump if available.
+ 	// ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data)
+ 	// ttmp12 holds SQ_WAVE_STATUS
+-	s_getreg_b32	ttmp4, hwreg(HW_REG_SHADER_TMA_LO)
+-	s_getreg_b32	ttmp5, hwreg(HW_REG_SHADER_TMA_HI)
+-	s_lshl_b64	[ttmp4, ttmp5], [ttmp4, ttmp5], 0x8
+-	s_load_dwordx2	[ttmp2, ttmp3], [ttmp4, ttmp5], 0x0 glc:1		// second-level TBA
++	s_getreg_b32	ttmp14, hwreg(HW_REG_SHADER_TMA_LO)
++	s_getreg_b32	ttmp15, hwreg(HW_REG_SHADER_TMA_HI)
++	s_lshl_b64	[ttmp14, ttmp15], [ttmp14, ttmp15], 0x8
++	s_load_dwordx2	[ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1		// second-level TBA
+ 	s_waitcnt	lgkmcnt(0)
+-	s_load_dwordx2	[ttmp4, ttmp5], [ttmp4, ttmp5], 0x8 glc:1		// second-level TMA
++	s_load_dwordx2	[ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1		// second-level TMA
+ 	s_waitcnt	lgkmcnt(0)
+ 	s_and_b64	[ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3]
+ 	s_cbranch_scc0	L_NO_NEXT_TRAP						// second-level trap handler not been set
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3808-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3808-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch
new file mode 100644
index 00000000..2db39b10
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3808-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch
@@ -0,0 +1,189 @@
+From 34a2a6a4fee196cb732c921ffc86e560c3183408 Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Wed, 31 Jul 2019 16:47:56 +0800
+Subject: [PATCH 3808/4256] drm/amdgpu: fix double ucode load by PSP(v3)
+
+previously the ucode loading of PSP was repreated, one executed in
+phase_1 init/re-init/resume and the other in fw_loading routine
+
+Avoid this double loading by clearing ip_blocks.status.hw in suspend or reset
+prior to the FW loading and any block's hw_init/resume
+
+v2:
+still do the smu fw loading since it is needed by bare-metal
+
+v3:
+drop the change in reinit_early_sriov, just clear all block's status.hw
+in the head place and set the status.hw after hw_init done is enough
+
+Change-Id: I3b871124da60ff356a78ea974ed6cd2b7e750376
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+Reviewed-by: Emily Deng <Emily.Deng@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 68 +++++++++++++---------
+ 1 file changed, 42 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index d3152aa16396..74c7723ad5e2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1723,28 +1723,34 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
+ 
+ 	if (adev->asic_type >= CHIP_VEGA10) {
+ 		for (i = 0; i < adev->num_ip_blocks; i++) {
+-			if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
+-				if (adev->in_gpu_reset || adev->in_suspend) {
+-					if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset)
+-						break; /* sriov gpu reset, psp need to do hw_init before IH because of hw limit */
+-					r = adev->ip_blocks[i].version->funcs->resume(adev);
+-					if (r) {
+-						DRM_ERROR("resume of IP block <%s> failed %d\n",
++			if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
++				continue;
++
++			/* no need to do the fw loading again if already done*/
++			if (adev->ip_blocks[i].status.hw == true)
++				break;
++
++			if (adev->in_gpu_reset || adev->in_suspend) {
++				r = adev->ip_blocks[i].version->funcs->resume(adev);
++				if (r) {
++					DRM_ERROR("resume of IP block <%s> failed %d\n",
+ 							  adev->ip_blocks[i].version->funcs->name, r);
+-						return r;
+-					}
+-				} else {
+-					r = adev->ip_blocks[i].version->funcs->hw_init(adev);
+-					if (r) {
+-						DRM_ERROR("hw_init of IP block <%s> failed %d\n",
+-						  adev->ip_blocks[i].version->funcs->name, r);
+-						return r;
+-					}
++					return r;
++				}
++			} else {
++				r = adev->ip_blocks[i].version->funcs->hw_init(adev);
++				if (r) {
++					DRM_ERROR("hw_init of IP block <%s> failed %d\n",
++							  adev->ip_blocks[i].version->funcs->name, r);
++					return r;
+ 				}
+-				adev->ip_blocks[i].status.hw = true;
+ 			}
++
++			adev->ip_blocks[i].status.hw = true;
++			break;
+ 		}
+ 	}
++
+ 	r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
+ 
+ 	return r;
+@@ -2178,7 +2184,9 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
+ 			if (r) {
+ 				DRM_ERROR("suspend of IP block <%s> failed %d\n",
+ 					  adev->ip_blocks[i].version->funcs->name, r);
++				return r;
+ 			}
++			adev->ip_blocks[i].status.hw = false;
+ 		}
+ 	}
+ 
+@@ -2219,15 +2227,16 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
+ 			if (is_support_sw_smu(adev)) {
+ 				r = smu_set_mp1_state(&adev->smu, adev->mp1_state);
+ 			} else if (adev->powerplay.pp_funcs &&
+-				   adev->powerplay.pp_funcs->set_mp1_state) {
++					   adev->powerplay.pp_funcs->set_mp1_state) {
+ 				r = adev->powerplay.pp_funcs->set_mp1_state(
+ 					adev->powerplay.pp_handle,
+ 					adev->mp1_state);
+-			}
+-			if (r) {
+-				DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
+-					  adev->mp1_state, r);
+-				return r;
++				if (r) {
++					DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
++						  adev->mp1_state, r);
++					return r;
++				}
++				adev->ip_blocks[i].status.hw = false;
+ 			}
+ 		}
+ 
+@@ -2284,6 +2293,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
+ 		for (j = 0; j < adev->num_ip_blocks; j++) {
+ 			block = &adev->ip_blocks[j];
+ 
++			block->status.hw = false;
+ 			if (block->version->type != ip_order[i] ||
+ 				!block->status.valid)
+ 				continue;
+@@ -2292,6 +2302,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
+ 			DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
+ 			if (r)
+ 				return r;
++			block->status.hw = true;
+ 		}
+ 	}
+ 
+@@ -2319,13 +2330,15 @@ static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
+ 			block = &adev->ip_blocks[j];
+ 
+ 			if (block->version->type != ip_order[i] ||
+-				!block->status.valid)
++				!block->status.valid ||
++				block->status.hw)
+ 				continue;
+ 
+ 			r = block->version->funcs->hw_init(adev);
+ 			DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
+ 			if (r)
+ 				return r;
++			block->status.hw = true;
+ 		}
+ 	}
+ 
+@@ -2349,17 +2362,19 @@ static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
+ 	int i, r;
+ 
+ 	for (i = 0; i < adev->num_ip_blocks; i++) {
+-		if (!adev->ip_blocks[i].status.valid)
++		if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
+ 			continue;
+ 		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
+ 		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
+ 		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
++
+ 			r = adev->ip_blocks[i].version->funcs->resume(adev);
+ 			if (r) {
+ 				DRM_ERROR("resume of IP block <%s> failed %d\n",
+ 					  adev->ip_blocks[i].version->funcs->name, r);
+ 				return r;
+ 			}
++			adev->ip_blocks[i].status.hw = true;
+ 		}
+ 	}
+ 
+@@ -2384,7 +2399,7 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
+ 	int i, r;
+ 
+ 	for (i = 0; i < adev->num_ip_blocks; i++) {
+-		if (!adev->ip_blocks[i].status.valid)
++		if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
+ 			continue;
+ 		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
+ 		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
+@@ -2397,6 +2412,7 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
+ 				  adev->ip_blocks[i].version->funcs->name, r);
+ 			return r;
+ 		}
++		adev->ip_blocks[i].status.hw = true;
+ 	}
+ 
+ 	return 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3809-drm-amdgpu-add-navi12-pci-id.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3809-drm-amdgpu-add-navi12-pci-id.patch
new file mode 100644
index 00000000..f6aca523
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3809-drm-amdgpu-add-navi12-pci-id.patch
@@ -0,0 +1,31 @@
+From a9ff07de9f531bbb5ed56c8ba9a23d53d86cfb5b Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Tue, 17 Sep 2019 10:35:34 +0800
+Subject: [PATCH 3809/4256] drm/amdgpu: add navi12 pci id
+
+Add Navi12 PCI id support.
+
+Change-Id: Ic4e63f46f6ddf856910018dc3ddc2093d87873d0
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 27828e432601..f1def7d9af2b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1067,6 +1067,9 @@ static const struct pci_device_id pciidlist[] = {
+ 	/* Renoir */
+ 	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
+ 
++	/* Navi12 */
++	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
++
+ 	{0, 0, 0}
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3810-drm-amd-powerplay-implement-VCN-power-gating-control.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3810-drm-amd-powerplay-implement-VCN-power-gating-control.patch
new file mode 100644
index 00000000..f7ebf80e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3810-drm-amd-powerplay-implement-VCN-power-gating-control.patch
@@ -0,0 +1,64 @@
+From db28c9ad99c880579d979cee2eebba2f9f0f4da7 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Mon, 16 Sep 2019 15:56:52 +0800
+Subject: [PATCH 3810/4256] drm/amd/powerplay: implement VCN power gating
+ control interface
+
+VCN Gat/Ungat by processing the SMU power up/down message, otherwise
+S3 will resume failed as JPEG always power off during start VCN stage.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 28 +++++++++++++++++++++-
+ 1 file changed, 27 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 2c22ba49c453..9311b6acc34d 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -278,6 +278,32 @@ static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context
+ 	return pm_type;
+ }
+ 
++static int renoir_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
++{
++	struct smu_power_context *smu_power = &smu->smu_power;
++	struct smu_power_gate *power_gate = &smu_power->power_gate;
++	int ret = 0;
++
++	if (enable) {
++		/* vcn dpm on is a prerequisite for vcn power gate messages */
++		if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
++			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
++			if (ret)
++				return ret;
++		}
++		power_gate->vcn_gated = false;
++	} else {
++		if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
++			ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
++			if (ret)
++				return ret;
++		}
++		power_gate->vcn_gated = true;
++	}
++
++	return ret;
++}
++
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_smu_msg_index = renoir_get_smu_msg_index,
+ 	.get_smu_table_index = renoir_get_smu_table_index,
+@@ -286,7 +312,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_dpm_uclk_limited = renoir_get_dpm_uclk_limited,
+ 	.print_clk_levels = renoir_print_clk_levels,
+ 	.get_current_power_state = renoir_get_current_power_state,
+-
++	.dpm_set_uvd_enable = renoir_dpm_set_uvd_enable,
+ };
+ 
+ void renoir_set_ppt_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3811-drm-amdgpu-remove-program-of-lbpw-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3811-drm-amdgpu-remove-program-of-lbpw-for-renoir.patch
new file mode 100644
index 00000000..ba32e962
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3811-drm-amdgpu-remove-program-of-lbpw-for-renoir.patch
@@ -0,0 +1,36 @@
+From e958e4469b5facfa10c7029d2618fc7224ef4d3e Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Mon, 16 Sep 2019 09:26:28 +0800
+Subject: [PATCH 3811/4256] drm/amdgpu: remove program of lbpw for renoir
+
+These is no LBPW on Renoir. So removing program of lbpw for renoir.
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 81ff4e86b65e..08f5ca346d71 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -1646,7 +1646,6 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_RAVEN:
+-	case CHIP_RENOIR:
+ 		gfx_v9_0_init_lbpw(adev);
+ 		break;
+ 	case CHIP_VEGA20:
+@@ -3024,7 +3023,6 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_RAVEN:
+-	case CHIP_RENOIR:
+ 		if (amdgpu_lbpw == 0)
+ 			gfx_v9_0_enable_lbpw(adev, false);
+ 		else
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3812-drm-amdgpu-SRIOV-Navi12-SRIOV-VF-gets-GTT-base.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3812-drm-amdgpu-SRIOV-Navi12-SRIOV-VF-gets-GTT-base.patch
new file mode 100644
index 00000000..43d221d4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3812-drm-amdgpu-SRIOV-Navi12-SRIOV-VF-gets-GTT-base.patch
@@ -0,0 +1,34 @@
+From 56c6c2fa270161780cab3275ed4b52bc2f3f80ab Mon Sep 17 00:00:00 2001
+From: Jiange Zhao <Jiange.Zhao@amd.com>
+Date: Mon, 16 Sep 2019 14:56:06 +0800
+Subject: [PATCH 3812/4256] drm/amdgpu/SRIOV: Navi12 SRIOV VF gets GTT base
+
+With changes in PSP and HV, SRIOV VF will handle
+
+vram gtt location just like bare metal. There is
+
+no need to differentiate it anymore.
+
+Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
+Reviewed-by: Emily Deng <Emily.Deng@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index 46efd4d17a34..2f9f881b810d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -519,8 +519,7 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
+ {
+ 	u64 base = 0;
+ 
+-	if (!amdgpu_sriov_vf(adev))
+-		base = gfxhub_v2_0_get_fb_location(adev);
++	base = gfxhub_v2_0_get_fb_location(adev);
+ 
+ 	amdgpu_gmc_vram_location(adev, &adev->gmc, base);
+ 	amdgpu_gmc_gart_location(adev, mc);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3813-drm-amdgpu-set-bulk_moveable-to-false-when-lru-chang.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3813-drm-amdgpu-set-bulk_moveable-to-false-when-lru-chang.patch
new file mode 100644
index 00000000..763d4e5d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3813-drm-amdgpu-set-bulk_moveable-to-false-when-lru-chang.patch
@@ -0,0 +1,83 @@
+From 1f7cdec9e120965a5004e502b6e3f197ac620d26 Mon Sep 17 00:00:00 2001
+From: Chunming Zhou <david1.zhou@amd.com>
+Date: Thu, 10 Jan 2019 15:49:54 +0800
+Subject: [PATCH 3813/4256] drm/amdgpu: set bulk_moveable to false when lru
+ changed v2
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+if lru is changed, we cannot do bulk moving.
+v2:
+root bo isn't in bulk moving, skip its change.
+
+Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  3 ++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 22 ++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  2 ++
+ 3 files changed, 26 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 7c3025abd387..341150b70e36 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -1763,7 +1763,8 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
+ 	.io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
+ 	.io_mem_free = &amdgpu_ttm_io_mem_free,
+ 	.io_mem_pfn = amdgpu_ttm_io_mem_pfn,
+-	.access_memory = &amdgpu_ttm_access_memory
++	.access_memory = &amdgpu_ttm_access_memory,
++	.del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
+ };
+ 
+ /*
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index f0daa5e20f3d..26ca609c1c20 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -565,6 +565,28 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
+ 	list_add(&entry->tv.head, validated);
+ }
+ 
++void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
++{
++	struct amdgpu_bo *abo;
++	struct amdgpu_vm_bo_base *bo_base;
++
++	if (!amdgpu_bo_is_amdgpu_bo(bo))
++		return;
++
++	if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT)
++		return;
++
++	abo = ttm_to_amdgpu_bo(bo);
++	if (!abo->parent)
++		return;
++	for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
++		struct amdgpu_vm *vm = bo_base->vm;
++
++		if (abo->tbo.resv == vm->root.base.bo->tbo.resv)
++			vm->bulk_moveable = false;
++	}
++
++}
+ /**
+  * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
+  *
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+index 5fbb26a0e1d8..0593978812ce 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+@@ -420,4 +420,6 @@ void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
+ 
+ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
+ 				struct amdgpu_vm *vm);
++void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo);
++
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3814-drm-amdgpu-Set-pasid-for-compute-vm-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3814-drm-amdgpu-Set-pasid-for-compute-vm-v2.patch
new file mode 100644
index 00000000..67e9c42e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3814-drm-amdgpu-Set-pasid-for-compute-vm-v2.patch
@@ -0,0 +1,127 @@
+From 3534633c662a355455085b75a7117c9cbcefc7a6 Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Wed, 29 Aug 2018 12:33:52 -0500
+Subject: [PATCH 3814/4256] drm/amdgpu: Set pasid for compute vm (v2)
+
+To make a amdgpu vm to a compute vm, the old pasid will be freed and
+replaced with a pasid managed by kfd. Kfd can't reuse original pasid
+allocated by amdgpu because kfd uses different pasid policy with amdgpu.
+For example, all graphic devices share one same pasid in a process.
+
+v2: rebase (Alex)
+
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |  2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c        | 40 +++++++++++++++++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h        |  2 +-
+ 3 files changed, 38 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index 8288cd965f8e..92af06fa011a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -1059,7 +1059,7 @@ int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
+ 		return -EINVAL;
+ 
+ 	/* Convert VM into a compute VM */
+-	ret = amdgpu_vm_make_compute(adev, avm);
++	ret = amdgpu_vm_make_compute(adev, avm, pasid);
+ 	if (ret)
+ 		return ret;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 26ca609c1c20..05c6ef31bb06 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -2830,7 +2830,7 @@ static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
+  * Returns:
+  * 0 for success, -errno for errors.
+  */
+-int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
++int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid)
+ {
+ 	bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
+ 	int r;
+@@ -2842,7 +2842,21 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+ 	/* Sanity checks */
+ 	r = amdgpu_vm_check_clean_reserved(adev, vm);
+ 	if (r)
+-		goto error;
++		goto unreserve_bo;
++
++	if (pasid) {
++                unsigned long flags;
++
++                spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
++                r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
++                              GFP_ATOMIC);
++                spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
++
++                if (r == -ENOSPC)
++                        goto unreserve_bo;
++                r = 0;
++        }
++
+ 
+ 	/* Check if PD needs to be reinitialized and do it before
+ 	 * changing any other state, in case it fails.
+@@ -2851,7 +2865,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+ 		vm->pte_support_ats = pte_support_ats;
+ 		r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo, false);
+ 		if (r)
+-			goto error;
++			goto free_idr;
+ 	}
+ 
+ 	/* Update VM state */
+@@ -2876,12 +2890,30 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+ 		idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
+ 		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
+ 
++		/* Free the original amdgpu allocated pasid
++                 * Will be replaced with kfd allocated pasid
++                 */
++                amdgpu_pasid_free(vm->pasid);
+ 		vm->pasid = 0;
+ 	}
+ 
+ 	/* Free the shadow bo for compute VM */
+ 	amdgpu_bo_unref(&vm->root.base.bo->shadow);
+-error:
++
++	 if (pasid)
++                vm->pasid = pasid;
++
++        goto unreserve_bo;
++
++free_idr:
++        if (pasid) {
++                unsigned long flags;
++
++                spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
++                idr_remove(&adev->vm_manager.pasid_idr, pasid);
++                spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
++        }
++unreserve_bo:
+ 	amdgpu_bo_unreserve(vm->root.base.bo);
+ 	return r;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+index 0593978812ce..4dbbe1b6b413 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+@@ -355,7 +355,7 @@ void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
+ long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);
+ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ 		   int vm_context, unsigned int pasid);
+-int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
++int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid);
+ void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
+ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
+ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3815-drm-amdgpu-cleanup-coding-style-in-the-VM-code-a-bit.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3815-drm-amdgpu-cleanup-coding-style-in-the-VM-code-a-bit.patch
new file mode 100644
index 00000000..8472ff83
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3815-drm-amdgpu-cleanup-coding-style-in-the-VM-code-a-bit.patch
@@ -0,0 +1,147 @@
+From de52b6116c3311ad8e8fb3e15b48869fde127a5f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Fri, 13 Sep 2019 12:12:40 +0200
+Subject: [PATCH 3815/4256] drm/amdgpu: cleanup coding style in the VM code a
+ bit
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+No functional change.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 52 +++++++++++++++++---------
+ 1 file changed, 34 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 05c6ef31bb06..6cda76591973 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -130,7 +130,8 @@ static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
+ 
+ 	if (level == adev->vm_manager.root_level)
+ 		/* For the root directory */
+-		return round_up(adev->vm_manager.max_pfn, 1ULL << shift) >> shift;
++		return round_up(adev->vm_manager.max_pfn, 1ULL << shift)
++			>> shift;
+ 	else if (level != AMDGPU_VM_PTB)
+ 		/* Everything in between */
+ 		return 512;
+@@ -565,6 +566,14 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
+ 	list_add(&entry->tv.head, validated);
+ }
+ 
++/**
++ * amdgpu_vm_del_from_lru_notify - update bulk_moveable flag
++ *
++ * @bo: BO which was removed from the LRU
++ *
++ * Make sure the bulk_moveable flag is updated when a BO is removed from the
++ * LRU.
++ */
+ void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
+ {
+ 	struct amdgpu_bo *abo;
+@@ -1023,7 +1032,8 @@ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
+  * Returns:
+  * 0 on success, errno otherwise.
+  */
+-int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync)
++int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
++		    bool need_pipe_sync)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 	unsigned vmhub = ring->funcs->vmhub;
+@@ -1678,8 +1688,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
+  * Returns:
+  * 0 for success, -EINVAL for failure.
+  */
+-int amdgpu_vm_bo_update(struct amdgpu_device *adev,
+-			struct amdgpu_bo_va *bo_va,
++int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
+ 			bool clear)
+ {
+ 	struct amdgpu_bo *bo = bo_va->base.bo;
+@@ -1750,7 +1759,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
+ 	if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
+ 		uint32_t mem_type = bo->tbo.mem.mem_type;
+ 
+-		if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type)))
++		if (!(bo->preferred_domains &
++		      amdgpu_mem_type_to_domain(mem_type)))
+ 			amdgpu_vm_bo_evicted(&bo_va->base);
+ 		else
+ 			amdgpu_vm_bo_idle(&bo_va->base);
+@@ -2712,7 +2722,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ 	}
+ 	DRM_DEBUG_DRIVER("VM update mode is %s\n",
+ 			 vm->use_cpu_for_update ? "CPU" : "SDMA");
+-	WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)),
++	WARN_ONCE((vm->use_cpu_for_update &&
++		   !amdgpu_gmc_vram_full_visible(&adev->gmc)),
+ 		  "CPU update of VM recommended only for large BAR system\n");
+ 
+ 	if (vm->use_cpu_for_update)
+@@ -2830,7 +2841,8 @@ static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
+  * Returns:
+  * 0 for success, -errno for errors.
+  */
+-int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid)
++int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
++			   unsigned int pasid)
+ {
+ 	bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
+ 	int r;
+@@ -2873,7 +2885,8 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, uns
+ 				    AMDGPU_VM_USE_CPU_FOR_COMPUTE);
+ 	DRM_DEBUG_DRIVER("VM update mode is %s\n",
+ 			 vm->use_cpu_for_update ? "CPU" : "SDMA");
+-	WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)),
++	WARN_ONCE((vm->use_cpu_for_update &&
++		   !amdgpu_gmc_vram_full_visible(&adev->gmc)),
+ 		  "CPU update of VM recommended only for large BAR system\n");
+ 
+ 	if (vm->use_cpu_for_update)
+@@ -3079,8 +3092,9 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
+ 
+ 	switch (args->in.op) {
+ 	case AMDGPU_VM_OP_RESERVE_VMID:
+-		/* current, we only have requirement to reserve vmid from gfxhub */
+-		r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
++		/* We only have requirement to reserve vmid from gfxhub */
++		r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm,
++					       AMDGPU_GFXHUB_0);
+ 		if (r)
+ 			return r;
+ 		break;
+@@ -3123,15 +3137,17 @@ void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
+  */
+ void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
+ {
+-	if (!vm->task_info.pid) {
+-		vm->task_info.pid = current->pid;
+-		get_task_comm(vm->task_info.task_name, current);
++	if (vm->task_info.pid)
++		return;
+ 
+-		if (current->group_leader->mm == current->mm) {
+-			vm->task_info.tgid = current->group_leader->pid;
+-			get_task_comm(vm->task_info.process_name, current->group_leader);
+-		}
+-	}
++	vm->task_info.pid = current->pid;
++	get_task_comm(vm->task_info.task_name, current);
++
++	if (current->group_leader->mm != current->mm)
++		return;
++
++	vm->task_info.tgid = current->group_leader->pid;
++	get_task_comm(vm->task_info.process_name, current->group_leader);
+ }
+ 
+ /**
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3816-drm-amdgpu-drop-double-HDP-flush-in-the-VM-code.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3816-drm-amdgpu-drop-double-HDP-flush-in-the-VM-code.patch
new file mode 100644
index 00000000..1f9053ac
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3816-drm-amdgpu-drop-double-HDP-flush-in-the-VM-code.patch
@@ -0,0 +1,36 @@
+From 86618a1575348c674992b1180960e4316988c3bd Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Wed, 3 Apr 2019 14:11:53 +0200
+Subject: [PATCH 3816/4256] drm/amdgpu: drop double HDP flush in the VM code
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Already done in the CPU based backend code.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 6cda76591973..db1fe417fc95 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -1746,12 +1746,6 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
+ 			return r;
+ 	}
+ 
+-	if (vm->use_cpu_for_update) {
+-		/* Flush HDP */
+-		mb();
+-		amdgpu_asic_flush_hdp(adev, NULL);
+-	}
+-
+ 	/* If the BO is not in its preferred location add it back to
+ 	 * the evicted list so that it gets validated again on the
+ 	 * next command submission.
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3817-drm-amdgpu-trace-if-a-PD-PT-update-is-done-directly.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3817-drm-amdgpu-trace-if-a-PD-PT-update-is-done-directly.patch
new file mode 100644
index 00000000..f8021583
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3817-drm-amdgpu-trace-if-a-PD-PT-update-is-done-directly.patch
@@ -0,0 +1,119 @@
+From b6d89e4c69a249866f9b068a7289cbfd50757616 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Wed, 3 Apr 2019 13:30:56 +0200
+Subject: [PATCH 3817/4256] drm/amdgpu: trace if a PD/PT update is done
+ directly
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This is usfull for debugging.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h   | 23 +++++++++++++--------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c  |  2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c |  4 ++--
+ 3 files changed, 17 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+index d3ca2424b5fe..e9feb5a8fb9d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+@@ -325,14 +325,15 @@ DEFINE_EVENT(amdgpu_vm_mapping, amdgpu_vm_bo_cs,
+ 
+ TRACE_EVENT(amdgpu_vm_set_ptes,
+ 	    TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,
+-		     uint32_t incr, uint64_t flags),
+-	    TP_ARGS(pe, addr, count, incr, flags),
++		     uint32_t incr, uint64_t flags, bool direct),
++	    TP_ARGS(pe, addr, count, incr, flags, direct),
+ 	    TP_STRUCT__entry(
+ 			     __field(u64, pe)
+ 			     __field(u64, addr)
+ 			     __field(u32, count)
+ 			     __field(u32, incr)
+ 			     __field(u64, flags)
++			     __field(bool, direct)
+ 			     ),
+ 
+ 	    TP_fast_assign(
+@@ -341,28 +342,32 @@ TRACE_EVENT(amdgpu_vm_set_ptes,
+ 			   __entry->count = count;
+ 			   __entry->incr = incr;
+ 			   __entry->flags = flags;
++			   __entry->direct = direct;
+ 			   ),
+-	    TP_printk("pe=%010Lx, addr=%010Lx, incr=%u, flags=%llx, count=%u",
+-		      __entry->pe, __entry->addr, __entry->incr,
+-		      __entry->flags, __entry->count)
++	    TP_printk("pe=%010Lx, addr=%010Lx, incr=%u, flags=%llx, count=%u, "
++		      "direct=%d", __entry->pe, __entry->addr, __entry->incr,
++		      __entry->flags, __entry->count, __entry->direct)
+ );
+ 
+ TRACE_EVENT(amdgpu_vm_copy_ptes,
+-	    TP_PROTO(uint64_t pe, uint64_t src, unsigned count),
+-	    TP_ARGS(pe, src, count),
++	    TP_PROTO(uint64_t pe, uint64_t src, unsigned count, bool direct),
++	    TP_ARGS(pe, src, count, direct),
+ 	    TP_STRUCT__entry(
+ 			     __field(u64, pe)
+ 			     __field(u64, src)
+ 			     __field(u32, count)
++			     __field(bool, direct)
+ 			     ),
+ 
+ 	    TP_fast_assign(
+ 			   __entry->pe = pe;
+ 			   __entry->src = src;
+ 			   __entry->count = count;
++			   __entry->direct = direct;
+ 			   ),
+-	    TP_printk("pe=%010Lx, src=%010Lx, count=%u",
+-		      __entry->pe, __entry->src, __entry->count)
++	    TP_printk("pe=%010Lx, src=%010Lx, count=%u, direct=%d",
++		      __entry->pe, __entry->src, __entry->count,
++		      __entry->direct)
+ );
+ 
+ TRACE_EVENT(amdgpu_vm_flush,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
+index a2daeadd770f..73fec7a0ced5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
+@@ -89,7 +89,7 @@ static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p,
+ 
+ 	pe += (unsigned long)amdgpu_bo_kptr(bo);
+ 
+-	trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
++	trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->direct);
+ 
+ 	for (i = 0; i < count; i++) {
+ 		value = p->pages_addr ?
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+index 38c966cedc26..e8db1467a71d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+@@ -143,7 +143,7 @@ static void amdgpu_vm_sdma_copy_ptes(struct amdgpu_vm_update_params *p,
+ 	src += p->num_dw_left * 4;
+ 
+ 	pe += amdgpu_bo_gpu_offset(bo);
+-	trace_amdgpu_vm_copy_ptes(pe, src, count);
++	trace_amdgpu_vm_copy_ptes(pe, src, count, p->direct);
+ 
+ 	amdgpu_vm_copy_pte(p->adev, ib, pe, src, count);
+ }
+@@ -170,7 +170,7 @@ static void amdgpu_vm_sdma_set_ptes(struct amdgpu_vm_update_params *p,
+ 	struct amdgpu_ib *ib = p->job->ibs;
+ 
+ 	pe += amdgpu_bo_gpu_offset(bo);
+-	trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
++	trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->direct);
+ 	if (count < 3) {
+ 		amdgpu_vm_write_pte(p->adev, ib, pe, addr | flags,
+ 				    count, incr);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3818-drm-amdgpu-fix-ras-ctrl-debugfs-node-leak.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3818-drm-amdgpu-fix-ras-ctrl-debugfs-node-leak.patch
new file mode 100644
index 00000000..7becda10
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3818-drm-amdgpu-fix-ras-ctrl-debugfs-node-leak.patch
@@ -0,0 +1,66 @@
+From 8fcc9ada7b2402c36260efa8a5525f94edce3029 Mon Sep 17 00:00:00 2001
+From: Guchun Chen <guchun.chen@amd.com>
+Date: Mon, 16 Sep 2019 13:42:46 +0800
+Subject: [PATCH 3818/4256] drm/amdgpu: fix ras ctrl debugfs node leak
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use debugfs_remove_recursive to remove the whole debugfs
+directory instead of removing the node one by one.
+
+Change-Id: I27e9edab20d568b16d0163f8c7c3d81fb6832acd
+Signed-off-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 12 +++++-------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h |  2 --
+ 2 files changed, 5 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 5f06f1e645c7..0a90e5cb3ca4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -978,10 +978,10 @@ static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
+ 	struct drm_minor *minor = adev->ddev->primary;
+ 
+ 	con->dir = debugfs_create_dir("ras", minor->debugfs_root);
+-	con->ent = debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, con->dir,
+-				       adev, &amdgpu_ras_debugfs_ctrl_ops);
+-	con->ent = debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, con->dir,
+-					       adev, &amdgpu_ras_debugfs_eeprom_ops);
++	debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, con->dir,
++				adev, &amdgpu_ras_debugfs_ctrl_ops);
++	debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, con->dir,
++				adev, &amdgpu_ras_debugfs_eeprom_ops);
+ }
+ 
+ void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
+@@ -1026,10 +1026,8 @@ static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev)
+ 		amdgpu_ras_debugfs_remove(adev, &obj->head);
+ 	}
+ 
+-	debugfs_remove(con->ent);
+-	debugfs_remove(con->dir);
++	debugfs_remove_recursive(con->dir);
+ 	con->dir = NULL;
+-	con->ent = NULL;
+ }
+ /* debugfs end */
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index dd5da3c6327e..ae386c466c0e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -317,8 +317,6 @@ struct amdgpu_ras {
+ 	struct list_head head;
+ 	/* debugfs */
+ 	struct dentry *dir;
+-	/* debugfs ctrl */
+-	struct dentry *ent;
+ 	/* sysfs */
+ 	struct device_attribute features_attr;
+ 	struct bin_attribute badpages_attr;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3819-drm-amdgpu-Fix-EEPROM-checksum-calculation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3819-drm-amdgpu-Fix-EEPROM-checksum-calculation.patch
new file mode 100644
index 00000000..f3243917
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3819-drm-amdgpu-Fix-EEPROM-checksum-calculation.patch
@@ -0,0 +1,225 @@
+From b4798087078ac666f89859028629d3d06efd736b Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Thu, 12 Sep 2019 17:16:32 -0400
+Subject: [PATCH 3819/4256] drm/amdgpu:Fix EEPROM checksum calculation.
+
+Fix checksum calculation after manually resetting the table.
+Unify reset and empty EEPROM init flow.
+Protect the table reset with lock.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c    | 164 +++++++++---------
+ 1 file changed, 86 insertions(+), 78 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+index 11a8445cf734..d0e020ef73e3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+@@ -100,22 +100,100 @@ static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
+ 	return ret;
+ }
+ 
+-static uint32_t  __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control);
++
++
++static uint32_t  __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control)
++{
++	int i;
++	uint32_t tbl_sum = 0;
++
++	/* Header checksum, skip checksum field in the calculation */
++	for (i = 0; i < sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); i++)
++		tbl_sum += *(((unsigned char *)&control->tbl_hdr) + i);
++
++	return tbl_sum;
++}
++
++static uint32_t  __calc_recs_byte_sum(struct eeprom_table_record *records,
++				      int num)
++{
++	int i, j;
++	uint32_t tbl_sum = 0;
++
++	/* Records checksum */
++	for (i = 0; i < num; i++) {
++		struct eeprom_table_record *record = &records[i];
++
++		for (j = 0; j < sizeof(*record); j++) {
++			tbl_sum += *(((unsigned char *)record) + j);
++		}
++	}
++
++	return tbl_sum;
++}
++
++static inline uint32_t  __calc_tbl_byte_sum(struct amdgpu_ras_eeprom_control *control,
++				  struct eeprom_table_record *records, int num)
++{
++	return __calc_hdr_byte_sum(control) + __calc_recs_byte_sum(records, num);
++}
++
++/* Checksum = 256 -((sum of all table entries) mod 256) */
++static void __update_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
++				  struct eeprom_table_record *records, int num,
++				  uint32_t old_hdr_byte_sum)
++{
++	/*
++	 * This will update the table sum with new records.
++	 *
++	 * TODO: What happens when the EEPROM table is to be wrapped around
++	 * and old records from start will get overridden.
++	 */
++
++	/* need to recalculate updated header byte sum */
++	control->tbl_byte_sum -= old_hdr_byte_sum;
++	control->tbl_byte_sum += __calc_tbl_byte_sum(control, records, num);
++
++	control->tbl_hdr.checksum = 256 - (control->tbl_byte_sum % 256);
++}
++
++/* table sum mod 256 + checksum must equals 256 */
++static bool __validate_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
++			    struct eeprom_table_record *records, int num)
++{
++	control->tbl_byte_sum = __calc_tbl_byte_sum(control, records, num);
++
++	if (control->tbl_hdr.checksum + (control->tbl_byte_sum % 256) != 256) {
++		DRM_WARN("Checksum mismatch, checksum: %u ", control->tbl_hdr.checksum);
++		return false;
++	}
++
++	return true;
++}
+ 
+ int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
+ {
+ 	unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };
+-	struct amdgpu_device *adev = to_amdgpu_device(control);
+ 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
++	int ret = 0;
++
++	mutex_lock(&control->tbl_mutex);
+ 
+ 	hdr->header = EEPROM_TABLE_HDR_VAL;
+ 	hdr->version = EEPROM_TABLE_VER;
+ 	hdr->first_rec_offset = EEPROM_RECORD_START;
+ 	hdr->tbl_size = EEPROM_TABLE_HEADER_SIZE;
+ 
+-	adev->psp.ras.ras->eeprom_control.tbl_byte_sum =
+-			__calc_hdr_byte_sum(&adev->psp.ras.ras->eeprom_control);
+-	return __update_table_header(control, buff);
++	control->tbl_byte_sum = 0;
++	__update_tbl_checksum(control, NULL, 0, 0);
++	control->next_addr = EEPROM_RECORD_START;
++
++	ret = __update_table_header(control, buff);
++
++	mutex_unlock(&control->tbl_mutex);
++
++	return ret;
++
+ }
+ 
+ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
+@@ -159,6 +237,9 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
+ 	if (hdr->header == EEPROM_TABLE_HDR_VAL) {
+ 		control->num_recs = (hdr->tbl_size - EEPROM_TABLE_HEADER_SIZE) /
+ 				    EEPROM_TABLE_RECORD_SIZE;
++		control->tbl_byte_sum = __calc_hdr_byte_sum(control);
++		control->next_addr = EEPROM_RECORD_START;
++
+ 		DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records",
+ 				 control->num_recs);
+ 
+@@ -168,9 +249,6 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
+ 		ret = amdgpu_ras_eeprom_reset_table(control);
+ 	}
+ 
+-	/* Start inserting records from here */
+-	adev->psp.ras.ras->eeprom_control.next_addr = EEPROM_RECORD_START;
+-
+ 	return ret == 1 ? 0 : -EIO;
+ }
+ 
+@@ -275,76 +353,6 @@ static uint32_t __correct_eeprom_dest_address(uint32_t curr_address)
+ 	return curr_address;
+ }
+ 
+-
+-static uint32_t  __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control)
+-{
+-	int i;
+-	uint32_t tbl_sum = 0;
+-
+-	/* Header checksum, skip checksum field in the calculation */
+-	for (i = 0; i < sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); i++)
+-		tbl_sum += *(((unsigned char *)&control->tbl_hdr) + i);
+-
+-	return tbl_sum;
+-}
+-
+-static uint32_t  __calc_recs_byte_sum(struct eeprom_table_record *records,
+-				      int num)
+-{
+-	int i, j;
+-	uint32_t tbl_sum = 0;
+-
+-	/* Records checksum */
+-	for (i = 0; i < num; i++) {
+-		struct eeprom_table_record *record = &records[i];
+-
+-		for (j = 0; j < sizeof(*record); j++) {
+-			tbl_sum += *(((unsigned char *)record) + j);
+-		}
+-	}
+-
+-	return tbl_sum;
+-}
+-
+-static inline uint32_t  __calc_tbl_byte_sum(struct amdgpu_ras_eeprom_control *control,
+-				  struct eeprom_table_record *records, int num)
+-{
+-	return __calc_hdr_byte_sum(control) + __calc_recs_byte_sum(records, num);
+-}
+-
+-/* Checksum = 256 -((sum of all table entries) mod 256) */
+-static void __update_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
+-				  struct eeprom_table_record *records, int num,
+-				  uint32_t old_hdr_byte_sum)
+-{
+-	/*
+-	 * This will update the table sum with new records.
+-	 *
+-	 * TODO: What happens when the EEPROM table is to be wrapped around
+-	 * and old records from start will get overridden.
+-	 */
+-
+-	/* need to recalculate updated header byte sum */
+-	control->tbl_byte_sum -= old_hdr_byte_sum;
+-	control->tbl_byte_sum += __calc_tbl_byte_sum(control, records, num);
+-
+-	control->tbl_hdr.checksum = 256 - (control->tbl_byte_sum % 256);
+-}
+-
+-/* table sum mod 256 + checksum must equals 256 */
+-static bool __validate_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
+-			    struct eeprom_table_record *records, int num)
+-{
+-	control->tbl_byte_sum = __calc_tbl_byte_sum(control, records, num);
+-
+-	if (control->tbl_hdr.checksum + (control->tbl_byte_sum % 256) != 256) {
+-		DRM_WARN("Checksum mismatch, checksum: %u ", control->tbl_hdr.checksum);
+-		return false;
+-	}
+-
+-	return true;
+-}
+-
+ int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
+ 					    struct eeprom_table_record *records,
+ 					    bool write,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3820-drm-amdgpu-cleanup-mtype-mapping.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3820-drm-amdgpu-cleanup-mtype-mapping.patch
new file mode 100644
index 00000000..112faf00
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3820-drm-amdgpu-cleanup-mtype-mapping.patch
@@ -0,0 +1,395 @@
+From d178e867b2fc43900e5abd09c7c53ac9e3566367 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Mon, 2 Sep 2019 14:52:30 +0200
+Subject: [PATCH 3820/4256] drm/amdgpu: cleanup mtype mapping
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Unify how we map the UAPI flags to the PTE hardware flags for a mapping.
+
+Only the MTYPE is actually ASIC dependent, all other flags should be
+copied over 1 to 1 and ASIC differences are handled later on.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+---
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |  2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c       | 32 +++++++++++++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h       |  1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h       |  7 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c        |  6 ++-
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c        | 40 +++++-------------
+ drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c         | 16 -------
+ drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c         | 16 -------
+ drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c         | 18 --------
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c         | 42 +++++--------------
+ 10 files changed, 59 insertions(+), 121 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index 92af06fa011a..9ffe63377c99 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -412,7 +412,7 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
+ 			AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
+ 	}
+ 
+-	return amdgpu_gmc_get_pte_flags(adev, mapping_flags);
++	return amdgpu_gem_va_map_flags(adev, mapping_flags);
+ }
+ 
+ /* add_bo_to_vm - Add a BO to a VM
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+index cbd09e9b1092..59a1e73f4056 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+@@ -617,6 +617,34 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
+ 		DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
+ }
+ 
++/**
++ * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags
++ *
++ * @adev: amdgpu_device pointer
++ * @flags: GEM UAPI flags
++ *
++ * Returns the GEM UAPI flags mapped into hardware for the ASIC.
++ */
++uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags)
++{
++	uint64_t pte_flag = 0;
++
++	if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
++		pte_flag |= AMDGPU_PTE_EXECUTABLE;
++	if (flags & AMDGPU_VM_PAGE_READABLE)
++		pte_flag |= AMDGPU_PTE_READABLE;
++	if (flags & AMDGPU_VM_PAGE_WRITEABLE)
++		pte_flag |= AMDGPU_PTE_WRITEABLE;
++	if (flags & AMDGPU_VM_PAGE_PRT)
++		pte_flag |= AMDGPU_PTE_PRT;
++
++	if (adev->gmc.gmc_funcs->map_mtype)
++		pte_flag |= amdgpu_gmc_map_mtype(adev,
++						 flags & AMDGPU_VM_MTYPE_MASK);
++
++	return pte_flag;
++}
++
+ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
+ 			  struct drm_file *filp)
+ {
+@@ -711,7 +739,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
+ 
+ 	switch (args->operation) {
+ 	case AMDGPU_VA_OP_MAP:
+-		va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags);
++		va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
+ 		r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
+ 				     args->offset_in_bo, args->map_size,
+ 				     va_flags);
+@@ -726,7 +754,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
+ 						args->map_size);
+ 		break;
+ 	case AMDGPU_VA_OP_REPLACE:
+-		va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags);
++		va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
+ 		r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
+ 					     args->offset_in_bo, args->map_size,
+ 					     va_flags);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
+index 206c5fa2c18f..ff7f8de62655 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
+@@ -69,6 +69,7 @@ int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
+ 			  struct drm_file *filp);
+ int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
+ 			      struct drm_file *filp);
++uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags);
+ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
+ 			  struct drm_file *filp);
+ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+index df012766d907..a669c5826415 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+@@ -99,9 +99,8 @@ struct amdgpu_gmc_funcs {
+ 				   unsigned pasid);
+ 	/* enable/disable PRT support */
+ 	void (*set_prt)(struct amdgpu_device *adev, bool enable);
+-	/* set pte flags based per asic */
+-	uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
+-				     uint32_t flags);
++	/* map mtype to hardware flags */
++	uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags);
+ 	/* get the pde for a given mc addr */
+ 	void (*get_vm_pde)(struct amdgpu_device *adev, int level,
+ 			   u64 *dst, u64 *flags);
+@@ -185,8 +184,8 @@ struct amdgpu_gmc {
+ #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
+ #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
+ #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
++#define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
+ #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
+-#define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
+ 
+ /**
+  * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index db1fe417fc95..d85753632840 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -1585,8 +1585,10 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
+ 	if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
+ 		flags &= ~AMDGPU_PTE_WRITEABLE;
+ 
+-	flags &= ~AMDGPU_PTE_EXECUTABLE;
+-	flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
++	if (adev->asic_type >= CHIP_TONGA) {
++		flags &= ~AMDGPU_PTE_EXECUTABLE;
++		flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
++	}
+ 
+ 	if (adev->asic_type >= CHIP_NAVI10) {
+ 		flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index 2f9f881b810d..ebc2abbbf039 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -397,43 +397,23 @@ static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid
+  * 1 system
+  * 0 valid
+  */
+-static uint64_t gmc_v10_0_get_vm_pte_flags(struct amdgpu_device *adev,
+-					   uint32_t flags)
+-{
+-	uint64_t pte_flag = 0;
+-
+-	if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
+-		pte_flag |= AMDGPU_PTE_EXECUTABLE;
+-	if (flags & AMDGPU_VM_PAGE_READABLE)
+-		pte_flag |= AMDGPU_PTE_READABLE;
+-	if (flags & AMDGPU_VM_PAGE_WRITEABLE)
+-		pte_flag |= AMDGPU_PTE_WRITEABLE;
+ 
+-	switch (flags & AMDGPU_VM_MTYPE_MASK) {
++static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
++{
++	switch (flags) {
+ 	case AMDGPU_VM_MTYPE_DEFAULT:
+-		pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
+-		break;
++		return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
+ 	case AMDGPU_VM_MTYPE_NC:
+-		pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
+-		break;
++		return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
+ 	case AMDGPU_VM_MTYPE_WC:
+-		pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
+-		break;
++		return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
+ 	case AMDGPU_VM_MTYPE_CC:
+-		pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
+-		break;
++		return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
+ 	case AMDGPU_VM_MTYPE_UC:
+-		pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
+-		break;
++		return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
+ 	default:
+-		pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
+-		break;
++		return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
+ 	}
+-
+-	if (flags & AMDGPU_VM_PAGE_PRT)
+-		pte_flag |= AMDGPU_PTE_PRT;
+-
+-	return pte_flag;
+ }
+ 
+ static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
+@@ -464,7 +444,7 @@ static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
+ 	.flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
+ 	.emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
+ 	.emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
+-	.get_vm_pte_flags = gmc_v10_0_get_vm_pte_flags,
++	.map_mtype = gmc_v10_0_map_mtype,
+ 	.get_vm_pde = gmc_v10_0_get_vm_pde
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+index e60b6a5f170a..2b6a0d27f085 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+@@ -383,21 +383,6 @@ static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+ 	return pd_addr;
+ }
+ 
+-static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev,
+-					  uint32_t flags)
+-{
+-	uint64_t pte_flag = 0;
+-
+-	if (flags & AMDGPU_VM_PAGE_READABLE)
+-		pte_flag |= AMDGPU_PTE_READABLE;
+-	if (flags & AMDGPU_VM_PAGE_WRITEABLE)
+-		pte_flag |= AMDGPU_PTE_WRITEABLE;
+-	if (flags & AMDGPU_VM_PAGE_PRT)
+-		pte_flag |= AMDGPU_PTE_PRT;
+-
+-	return pte_flag;
+-}
+-
+ static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level,
+ 				uint64_t *addr, uint64_t *flags)
+ {
+@@ -1159,7 +1144,6 @@ static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
+ 	.emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb,
+ 	.set_prt = gmc_v6_0_set_prt,
+ 	.get_vm_pde = gmc_v6_0_get_vm_pde,
+-	.get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags
+ };
+ 
+ static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+index ef628f7b2a0e..5a47f5c4a118 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+@@ -460,21 +460,6 @@ static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
+ 	amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
+ }
+ 
+-static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev,
+-					  uint32_t flags)
+-{
+-	uint64_t pte_flag = 0;
+-
+-	if (flags & AMDGPU_VM_PAGE_READABLE)
+-		pte_flag |= AMDGPU_PTE_READABLE;
+-	if (flags & AMDGPU_VM_PAGE_WRITEABLE)
+-		pte_flag |= AMDGPU_PTE_WRITEABLE;
+-	if (flags & AMDGPU_VM_PAGE_PRT)
+-		pte_flag |= AMDGPU_PTE_PRT;
+-
+-	return pte_flag;
+-}
+-
+ static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level,
+ 				uint64_t *addr, uint64_t *flags)
+ {
+@@ -1355,7 +1340,6 @@ static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
+ 	.emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
+ 	.emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,
+ 	.set_prt = gmc_v7_0_set_prt,
+-	.get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags,
+ 	.get_vm_pde = gmc_v7_0_get_vm_pde
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+index d42610450807..8519d1346a37 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+@@ -688,23 +688,6 @@ static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
+  * 0 valid
+  */
+ 
+-static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev,
+-					  uint32_t flags)
+-{
+-	uint64_t pte_flag = 0;
+-
+-	if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
+-		pte_flag |= AMDGPU_PTE_EXECUTABLE;
+-	if (flags & AMDGPU_VM_PAGE_READABLE)
+-		pte_flag |= AMDGPU_PTE_READABLE;
+-	if (flags & AMDGPU_VM_PAGE_WRITEABLE)
+-		pte_flag |= AMDGPU_PTE_WRITEABLE;
+-	if (flags & AMDGPU_VM_PAGE_PRT)
+-		pte_flag |= AMDGPU_PTE_PRT;
+-
+-	return pte_flag;
+-}
+-
+ static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
+ 				uint64_t *addr, uint64_t *flags)
+ {
+@@ -1728,7 +1711,6 @@ static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
+ 	.emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
+ 	.emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
+ 	.set_prt = gmc_v8_0_set_prt,
+-	.get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags,
+ 	.get_vm_pde = gmc_v8_0_get_vm_pde
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index fe63f64c4db3..c95e62023e5e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -609,47 +609,25 @@ static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
+  * 0 valid
+  */
+ 
+-static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
+-						uint32_t flags)
++static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
+ 
+ {
+-	uint64_t pte_flag = 0;
+-
+-	if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
+-		pte_flag |= AMDGPU_PTE_EXECUTABLE;
+-	if (flags & AMDGPU_VM_PAGE_READABLE)
+-		pte_flag |= AMDGPU_PTE_READABLE;
+-	if (flags & AMDGPU_VM_PAGE_WRITEABLE)
+-		pte_flag |= AMDGPU_PTE_WRITEABLE;
+-
+-	switch (flags & AMDGPU_VM_MTYPE_MASK) {
++	switch (flags) {
+ 	case AMDGPU_VM_MTYPE_DEFAULT:
+-		pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
+-		break;
++		return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
+ 	case AMDGPU_VM_MTYPE_NC:
+-		pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
+-		break;
++		return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
+ 	case AMDGPU_VM_MTYPE_WC:
+-		pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
+-		break;
++		return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
+ 	case AMDGPU_VM_MTYPE_RW:
+-		pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
+-		break;
++		return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
+ 	case AMDGPU_VM_MTYPE_CC:
+-		pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
+-		break;
++		return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
+ 	case AMDGPU_VM_MTYPE_UC:
+-		pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
+-		break;
++		return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
+ 	default:
+-		pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
+-		break;
++		return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
+ 	}
+-
+-	if (flags & AMDGPU_VM_PAGE_PRT)
+-		pte_flag |= AMDGPU_PTE_PRT;
+-
+-	return pte_flag;
+ }
+ 
+ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
+@@ -680,7 +658,7 @@ static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
+ 	.flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
+ 	.emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
+ 	.emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
+-	.get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
++	.map_mtype = gmc_v9_0_map_mtype,
+ 	.get_vm_pde = gmc_v9_0_get_vm_pde
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3821-drm-amdgpu-check-large-bar-when-map-peer-device.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3821-drm-amdgpu-check-large-bar-when-map-peer-device.patch
new file mode 100644
index 00000000..b9f3b803
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3821-drm-amdgpu-check-large-bar-when-map-peer-device.patch
@@ -0,0 +1,48 @@
+From fb5b1de5f22ffa0a1ab04d46a88f65c11f4fdf2e Mon Sep 17 00:00:00 2001
+From: shaoyunl <shaoyun.liu@amd.com>
+Date: Wed, 14 Nov 2018 15:16:19 -0500
+Subject: [PATCH 3821/4256] drm/amdgpu: check large bar when map peer device
+
+CPU_ACCESS flag may be cleared on VRAM migration
+
+Change-Id: Ic2edf02cd23cb3d3d2b5a726dffeb5c55a50e274
+Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 23 ++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 74c7723ad5e2..63ec56c38bd8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -4113,3 +4113,26 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
+ 	}
+ }
+ 
++/**
++ * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR
++ *
++ * @adev: amdgpu_device pointer
++ * @peer_adev: amdgpu_device pointer for peer device trying to access @adev
++ *
++ * Return true if @peer_adev can access (DMA) @adev through the PCIe
++ * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of
++ * @peer_adev.
++ */
++bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
++				      struct amdgpu_device *peer_adev)
++{
++	uint64_t address_mask = peer_adev->dev->dma_mask ?
++		~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
++	resource_size_t aper_limit =
++		adev->gmc.aper_base + adev->gmc.aper_size - 1;
++
++	return adev->gmc.visible_vram_size &&
++		adev->gmc.real_vram_size == adev->gmc.visible_vram_size &&
++		!(adev->gmc.aper_base & address_mask ||
++		  aper_limit & address_mask);
++}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3822-drm-amdgpu-cleanup-PTE-flag-generation-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3822-drm-amdgpu-cleanup-PTE-flag-generation-v3.patch
new file mode 100644
index 00000000..46d877e0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3822-drm-amdgpu-cleanup-PTE-flag-generation-v3.patch
@@ -0,0 +1,272 @@
+From 7a77c6fa413d54dd9de3cff51b1083fb4e57df24 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Mon, 2 Sep 2019 16:39:40 +0200
+Subject: [PATCH 3822/4256] drm/amdgpu: cleanup PTE flag generation v3
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Move the ASIC specific code into a new callback function.
+
+v2: mask the flags for SI and CIK instead of a BUG_ON().
+v3: remove last missed BUG_ON().
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  5 ++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 38 ++++++++++---------------
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c  | 22 +++++++++++++-
+ drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c   |  9 ++++++
+ drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c   | 11 ++++++-
+ drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c   | 12 +++++++-
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 24 +++++++++++++++-
+ 7 files changed, 94 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+index a669c5826415..88894fd2784d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+@@ -104,6 +104,10 @@ struct amdgpu_gmc_funcs {
+ 	/* get the pde for a given mc addr */
+ 	void (*get_vm_pde)(struct amdgpu_device *adev, int level,
+ 			   u64 *dst, u64 *flags);
++	/* get the pte flags to use for a BO VA mapping */
++	void (*get_vm_pte)(struct amdgpu_device *adev,
++			   struct amdgpu_bo_va_mapping *mapping,
++			   uint64_t *flags);
+ };
+ 
+ struct amdgpu_xgmi {
+@@ -186,6 +190,7 @@ struct amdgpu_gmc {
+ #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
+ #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
+ #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
++#define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags))
+ 
+ /**
+  * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index d85753632840..604689385713 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -1573,6 +1573,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
+ 				      struct drm_mm_node *nodes,
+ 				      struct dma_fence **fence)
+ {
++	uint64_t vram_base_offset = bo_adev->vm_manager.vram_base_offset;
+ 	unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size;
+ 	uint64_t pfn, start = mapping->start;
+ 	int r;
+@@ -1585,29 +1586,20 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
+ 	if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
+ 		flags &= ~AMDGPU_PTE_WRITEABLE;
+ 
+-	if (adev->asic_type >= CHIP_TONGA) {
+-		flags &= ~AMDGPU_PTE_EXECUTABLE;
+-		flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
+-	}
+-
+-	if (adev->asic_type >= CHIP_NAVI10) {
+-		flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
+-		flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
+-	} else {
+-		flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
+-		flags |= (mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK);
+-	}
+-
+-	if ((mapping->flags & AMDGPU_PTE_PRT) &&
+-	    (adev->asic_type >= CHIP_VEGA10)) {
+-		flags |= AMDGPU_PTE_PRT;
+-		if (adev->asic_type >= CHIP_NAVI10) {
+-			flags |= AMDGPU_PTE_SNOOPED;
+-			flags |= AMDGPU_PTE_LOG;
+-			flags |= AMDGPU_PTE_SYSTEM;
+-		}
+-		flags &= ~AMDGPU_PTE_VALID;
+-	}
++	/* Apply ASIC specific mapping flags */
++        amdgpu_gmc_get_vm_pte(adev, mapping, &flags);
++
++	if (adev != bo_adev &&
++            !(flags & AMDGPU_PTE_SYSTEM) &&
++            !mapping->bo_va->is_xgmi) {
++                if (amdgpu_device_is_peer_accessible(bo_adev, adev)) {
++                        flags |= AMDGPU_PTE_SYSTEM;
++                        vram_base_offset = bo_adev->gmc.aper_base;
++                } else {
++                        DRM_DEBUG_DRIVER("Failed to map the VRAM for peer device access.\n");
++                        return -EINVAL;
++                }
++        }
+ 
+ 	trace_amdgpu_vm_bo_update(mapping);
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index ebc2abbbf039..ed1c3b883f6a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -440,12 +440,32 @@ static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
+ 	}
+ }
+ 
++static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
++				 struct amdgpu_bo_va_mapping *mapping,
++				 uint64_t *flags)
++{
++	*flags &= ~AMDGPU_PTE_EXECUTABLE;
++	*flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
++
++	*flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
++	*flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
++
++	if (mapping->flags & AMDGPU_PTE_PRT) {
++		*flags |= AMDGPU_PTE_PRT;
++		*flags |= AMDGPU_PTE_SNOOPED;
++		*flags |= AMDGPU_PTE_LOG;
++		*flags |= AMDGPU_PTE_SYSTEM;
++		*flags &= ~AMDGPU_PTE_VALID;
++	}
++}
++
+ static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
+ 	.flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
+ 	.emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
+ 	.emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
+ 	.map_mtype = gmc_v10_0_map_mtype,
+-	.get_vm_pde = gmc_v10_0_get_vm_pde
++	.get_vm_pde = gmc_v10_0_get_vm_pde,
++	.get_vm_pte = gmc_v10_0_get_vm_pte
+ };
+ 
+ static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+index 2b6a0d27f085..5ed0d3993cb7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+@@ -389,6 +389,14 @@ static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level,
+ 	BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
+ }
+ 
++static void gmc_v6_0_get_vm_pte(struct amdgpu_device *adev,
++				struct amdgpu_bo_va_mapping *mapping,
++				uint64_t *flags)
++{
++	*flags &= ~AMDGPU_PTE_EXECUTABLE;
++	*flags &= ~AMDGPU_PTE_PRT;
++}
++
+ static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
+ 					      bool value)
+ {
+@@ -1144,6 +1152,7 @@ static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
+ 	.emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb,
+ 	.set_prt = gmc_v6_0_set_prt,
+ 	.get_vm_pde = gmc_v6_0_get_vm_pde,
++	.get_vm_pte = gmc_v6_0_get_vm_pte,
+ };
+ 
+ static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+index 5a47f5c4a118..3fa973e6ec19 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+@@ -466,6 +466,14 @@ static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level,
+ 	BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
+ }
+ 
++static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev,
++				struct amdgpu_bo_va_mapping *mapping,
++				uint64_t *flags)
++{
++	*flags &= ~AMDGPU_PTE_EXECUTABLE;
++	*flags &= ~AMDGPU_PTE_PRT;
++}
++
+ /**
+  * gmc_v8_0_set_fault_enable_default - update VM fault handling
+  *
+@@ -1340,7 +1348,8 @@ static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
+ 	.emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
+ 	.emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,
+ 	.set_prt = gmc_v7_0_set_prt,
+-	.get_vm_pde = gmc_v7_0_get_vm_pde
++	.get_vm_pde = gmc_v7_0_get_vm_pde,
++	.get_vm_pte = gmc_v7_0_get_vm_pte
+ };
+ 
+ static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+index 8519d1346a37..238e20a8e4f0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+@@ -694,6 +694,15 @@ static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
+ 	BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
+ }
+ 
++static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev,
++				struct amdgpu_bo_va_mapping *mapping,
++				uint64_t *flags)
++{
++	*flags &= ~AMDGPU_PTE_EXECUTABLE;
++	*flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
++	*flags &= ~AMDGPU_PTE_PRT;
++}
++
+ /**
+  * gmc_v8_0_set_fault_enable_default - update VM fault handling
+  *
+@@ -1711,7 +1720,8 @@ static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
+ 	.emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
+ 	.emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
+ 	.set_prt = gmc_v8_0_set_prt,
+-	.get_vm_pde = gmc_v8_0_get_vm_pde
++	.get_vm_pde = gmc_v8_0_get_vm_pde,
++	.get_vm_pte = gmc_v8_0_get_vm_pte
+ };
+ 
+ static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index c95e62023e5e..561cc6bef280 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -654,12 +654,34 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
+ 	}
+ }
+ 
++static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
++				struct amdgpu_bo_va_mapping *mapping,
++				uint64_t *flags)
++{
++	*flags &= ~AMDGPU_PTE_EXECUTABLE;
++	*flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
++
++	*flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
++	*flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
++
++	if (mapping->flags & AMDGPU_PTE_PRT) {
++		*flags |= AMDGPU_PTE_PRT;
++		*flags &= ~AMDGPU_PTE_VALID;
++	}
++
++	if (adev->asic_type == CHIP_ARCTURUS &&
++	    !(*flags & AMDGPU_PTE_SYSTEM) &&
++	    mapping->bo_va->is_xgmi)
++		*flags |= AMDGPU_PTE_SNOOPED;
++}
++
+ static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
+ 	.flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
+ 	.emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
+ 	.emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
+ 	.map_mtype = gmc_v9_0_map_mtype,
+-	.get_vm_pde = gmc_v9_0_get_vm_pde
++	.get_vm_pde = gmc_v9_0_get_vm_pde,
++	.get_vm_pte = gmc_v9_0_get_vm_pte
+ };
+ 
+ static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3823-drm-amdkfd-fix-queue-snapshot-input-handling-and-ret.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3823-drm-amdkfd-fix-queue-snapshot-input-handling-and-ret.patch
new file mode 100644
index 00000000..9c904339
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3823-drm-amdkfd-fix-queue-snapshot-input-handling-and-ret.patch
@@ -0,0 +1,99 @@
+From d3247f280efdb81b94cc45cf6aea5e2c32321be8 Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Wed, 11 Sep 2019 09:30:07 -0400
+Subject: [PATCH 3823/4256] drm/amdkfd: fix queue snapshot input handling and
+ return
+
+queue snapshot doesn't need to set gpu id.  should get queues
+from target process, not calling process.  set queues copied
+to 0 if there are 0 queues or on errno.
+
+New queue should clear unconditionally on any queue status word update.
+
+Change-Id: If8bcf35ce27da2a8e07061a67298b5a29d5f7b99
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c      | 15 +++++++++------
+ drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c |  6 +++---
+ 2 files changed, 12 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index 547e7f511775..fa1385d60235 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -2611,6 +2611,7 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 	uint32_t data2;
+ 	uint32_t data3;
+ 	bool is_suspend_or_resume;
++	bool is_q_snapshot;
+ 
+ 	debug_trap_action = args->op;
+ 	gpu_id = args->gpu_id;
+@@ -2628,6 +2629,9 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 		debug_trap_action == KFD_IOC_DBG_TRAP_NODE_SUSPEND ||
+ 		debug_trap_action == KFD_IOC_DBG_TRAP_NODE_RESUME;
+ 
++	is_q_snapshot =
++		debug_trap_action == KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT;
++
+ 	pid = find_get_pid(args->pid);
+ 	if (!pid) {
+ 		pr_err("Cannot find pid info for %i\n",
+@@ -2661,7 +2665,7 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 
+ 	mutex_lock(&target->mutex);
+ 
+-	if (!is_suspend_or_resume) {
++	if (!(is_suspend_or_resume || is_q_snapshot)) {
+ 
+ 		dev = kfd_device_by_id(args->gpu_id);
+ 		if (!dev) {
+@@ -2705,7 +2709,7 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 			r = -EINVAL;
+ 			goto unlock_out;
+ 		}
+-	} else {
++	} else if (!is_q_snapshot) {
+ 		/* data 2 has the number of queue IDs */
+ 		size_t queue_id_array_size = sizeof(uint32_t) * data2;
+ 
+@@ -2801,14 +2805,13 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 						 &args->data3);
+ 		break;
+ 	case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT:
+-		r = pqm_get_queue_snapshot(&p->pqm, args->data1,
++		r = pqm_get_queue_snapshot(&target->pqm, args->data1,
+ 					   (void __user *)args->ptr,
+ 					   args->data2);
+ 
+-		if (r > 0) {
+-			args->data2 = r;
++		args->data2 = r < 0 ? 0 : r;
++		if (r > 0)
+ 			r = 0;
+-		}
+ 
+ 		break;
+ 	default:
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
+index 5433b6527bae..cabf26f03077 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
+@@ -112,10 +112,10 @@ uint32_t kfd_dbg_get_queue_status_word(struct queue *q, int flags)
+ 	KFD_DBG_EV_SET_NEW_QUEUE_STATE(queue_status_word,
+ 				  q->properties.is_new);
+ 
+-	if (flags & KFD_DBG_EV_FLAG_CLEAR_STATUS) {
+-		q->properties.is_new = false;
++	if (flags & KFD_DBG_EV_FLAG_CLEAR_STATUS)
+ 		q->properties.debug_event_type = 0;
+-	}
++
++	q->properties.is_new = false;
+ 
+ 	return queue_status_word;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3824-drm-amdgpu-gfx10-add-support-for-wks-firmware-loadin.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3824-drm-amdgpu-gfx10-add-support-for-wks-firmware-loadin.patch
new file mode 100644
index 00000000..25efb32e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3824-drm-amdgpu-gfx10-add-support-for-wks-firmware-loadin.patch
@@ -0,0 +1,106 @@
+From 59a1b672b32b60a65f2e103909fe8bf51fc77672 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Thu, 12 Sep 2019 17:40:22 +0800
+Subject: [PATCH 3824/4256] drm/amdgpu/gfx10: add support for wks firmware
+ loading
+
+load different cp firmware according to the DID and RID
+
+Change-Id: I6bb4cee12c8c47be6d3ef1150df93d7e1fbbecc7
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 22 ++++++++++++++++------
+ 1 file changed, 16 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 082a0b3298a9..65caf404e7d1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -66,6 +66,11 @@ MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
+ MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
+ MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
+ 
++MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
++MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
++MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
++MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
++MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
+ MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
+ MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
+ MODULE_FIRMWARE("amdgpu/navi14_me.bin");
+@@ -591,7 +596,8 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
+ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
+ {
+ 	const char *chip_name;
+-	char fw_name[30];
++	char fw_name[40];
++	char wks[10];
+ 	int err;
+ 	struct amdgpu_firmware_info *info = NULL;
+ 	const struct common_firmware_header *header = NULL;
+@@ -604,12 +610,16 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
+ 
+ 	DRM_DEBUG("\n");
+ 
++	memset(wks, 0, sizeof(wks));
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+ 		chip_name = "navi10";
+ 		break;
+ 	case CHIP_NAVI14:
+ 		chip_name = "navi14";
++		if (!(adev->pdev->device == 0x7340 &&
++		      adev->pdev->revision != 0x00))
++			snprintf(wks, sizeof(wks), "_wks");
+ 		break;
+ 	case CHIP_NAVI12:
+ 		chip_name = "navi12";
+@@ -618,7 +628,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
+ 		BUG();
+ 	}
+ 
+-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
++	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
+ 	err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
+ 	if (err)
+ 		goto out;
+@@ -629,7 +639,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
+ 	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+ 	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
+ 
+-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
++	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
+ 	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
+ 	if (err)
+ 		goto out;
+@@ -640,7 +650,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
+ 	adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+ 	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
+ 
+-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
++	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
+ 	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
+ 	if (err)
+ 		goto out;
+@@ -705,7 +715,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
+ 	if (adev->gfx.rlc.is_rlc_v2_1)
+ 		gfx_v10_0_init_rlc_ext_microcode(adev);
+ 
+-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
++	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
+ 	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
+ 	if (err)
+ 		goto out;
+@@ -716,7 +726,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
+ 	adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+ 	adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
+ 
+-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
++	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
+ 	err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
+ 	if (!err) {
+ 		err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3825-drm-amd-display-Fix-HUBP-secondary-viewport-programm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3825-drm-amd-display-Fix-HUBP-secondary-viewport-programm.patch
new file mode 100644
index 00000000..1e24fdda
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3825-drm-amd-display-Fix-HUBP-secondary-viewport-programm.patch
@@ -0,0 +1,87 @@
+From d4dd0d33bd686297e59fc95e95fdc9b6f423b9ec Mon Sep 17 00:00:00 2001
+From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Date: Fri, 23 Aug 2019 12:45:34 -0400
+Subject: [PATCH 3825/4256] drm/amd/display: Fix HUBP secondary viewport
+ programming
+
+[Why]
+Secondary viewport dimension/position registers are not programmed,
+which can cause issues in some stereo configurations.
+
+[How]
+Add register definitions and register programming.
+
+Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |  8 ++++++++
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 12 ++++++++++++
+ 2 files changed, 20 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+index 001db49e4bb2..14d1be6c66e6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+@@ -841,6 +841,14 @@ void min_set_viewport(
+ 	REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
+ 		  PRI_VIEWPORT_X_START_C, viewport_c->x,
+ 		  PRI_VIEWPORT_Y_START_C, viewport_c->y);
++
++	REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,
++		  SEC_VIEWPORT_WIDTH_C, viewport_c->width,
++		  SEC_VIEWPORT_HEIGHT_C, viewport_c->height);
++
++	REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,
++		  SEC_VIEWPORT_X_START_C, viewport_c->x,
++		  SEC_VIEWPORT_Y_START_C, viewport_c->y);
+ }
+ 
+ void hubp1_read_state_common(struct hubp *hubp)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+index f8e82ef24c09..ae70d9c0aa1d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+@@ -47,6 +47,8 @@
+ 	SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
+ 	SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
+ 	SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
++	SRI(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id), \
++	SRI(DCSURF_SEC_VIEWPORT_START_C, HUBP, id), \
+ 	SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
+ 	SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\
+ 	SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
+@@ -154,6 +156,8 @@
+ 	uint32_t DCSURF_SEC_VIEWPORT_START; \
+ 	uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C; \
+ 	uint32_t DCSURF_PRI_VIEWPORT_START_C; \
++	uint32_t DCSURF_SEC_VIEWPORT_DIMENSION_C; \
++	uint32_t DCSURF_SEC_VIEWPORT_START_C; \
+ 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; \
+ 	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; \
+ 	uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; \
+@@ -287,6 +291,10 @@
+ 	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
+ 	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
+ 	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
++	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_WIDTH_C, mask_sh),\
++	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_HEIGHT_C, mask_sh),\
++	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_X_START_C, mask_sh),\
++	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_Y_START_C, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
+ 	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
+@@ -481,6 +489,10 @@
+ 	type PRI_VIEWPORT_HEIGHT_C; \
+ 	type PRI_VIEWPORT_X_START_C; \
+ 	type PRI_VIEWPORT_Y_START_C; \
++	type SEC_VIEWPORT_WIDTH_C; \
++	type SEC_VIEWPORT_HEIGHT_C; \
++	type SEC_VIEWPORT_X_START_C; \
++	type SEC_VIEWPORT_Y_START_C; \
+ 	type PRIMARY_SURFACE_ADDRESS_HIGH;\
+ 	type PRIMARY_SURFACE_ADDRESS;\
+ 	type SECONDARY_SURFACE_ADDRESS_HIGH;\
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3826-drm-amd-display-define-parameters-for-abm-2.3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3826-drm-amd-display-define-parameters-for-abm-2.3.patch
new file mode 100644
index 00000000..cff15a46
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3826-drm-amd-display-define-parameters-for-abm-2.3.patch
@@ -0,0 +1,54 @@
+From 88bab55da9ecb7c77f35110a623f2c1dcd80b774 Mon Sep 17 00:00:00 2001
+From: Josip Pavic <Josip.Pavic@amd.com>
+Date: Fri, 23 Aug 2019 20:54:12 -0400
+Subject: [PATCH 3826/4256] drm/amd/display: define parameters for abm 2.3
+
+[Why]
+Current configuration 0 is just a placeholder, and final parameters needed.
+Also, configuration 1 is expected to emulate ABM 2.1 but is too aggressive.
+
+[How]
+Redefine configuration 0 with the finalized parameters, and increase the
+contrast gain of configuration 1 so that it properly emulates ABM 2.1.
+
+Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/modules/power/power_helpers.c    | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+index 05e2be856037..cc6b794821d9 100644
+--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
++++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+@@ -80,18 +80,18 @@ struct abm_parameters {
+ 
+ static const struct abm_parameters abm_settings_config0[abm_defines_max_level] = {
+ //  min_red  max_red  bright_pos  dark_pos  brightness_gain  contrast  deviation  min_knee  max_knee
+-	{0xff,   0xbf,    0x20,       0x00,     0xff,            0x99,     0xb3,      0x40,     0xE0},
+-	{0xff,   0x85,    0x20,       0x00,     0xff,            0x90,     0xa8,      0x40,     0xE0},
+-	{0xff,   0x40,    0x20,       0x00,     0xff,            0x90,     0x68,      0x40,     0xE0},
+-	{0x82,   0x4d,    0x20,       0x00,     0x00,            0x90,     0xb3,      0x70,     0x70},
++	{0xff,   0xbf,    0x20,       0x00,     0xff,            0x99,     0xb3,      0x40,     0xe0},
++	{0xde,   0x85,    0x20,       0x00,     0xff,            0x90,     0xa8,      0x40,     0xdf},
++	{0xb0,   0x50,    0x20,       0x00,     0xc0,            0x88,     0x78,      0x70,     0xa0},
++	{0x82,   0x40,    0x20,       0x00,     0x00,            0xff,     0xb3,      0x70,     0x70},
+ };
+ 
+ static const struct abm_parameters abm_settings_config1[abm_defines_max_level] = {
+ //  min_red  max_red  bright_pos  dark_pos  brightness_gain  contrast  deviation  min_knee  max_knee
+-	{0xf0,   0xd9,    0x20,       0x00,     0x00,            0xa8,     0xb3,      0x70,     0x70},
+-	{0xcd,   0xa5,    0x20,       0x00,     0x00,            0xa8,     0xb3,      0x70,     0x70},
+-	{0x99,   0x65,    0x20,       0x00,     0x00,            0xa8,     0xb3,      0x70,     0x70},
+-	{0x82,   0x4d,    0x20,       0x00,     0x00,            0xa8,     0xb3,      0x70,     0x70},
++	{0xf0,   0xd9,    0x20,       0x00,     0x00,            0xff,     0xb3,      0x70,     0x70},
++	{0xcd,   0xa5,    0x20,       0x00,     0x00,            0xff,     0xb3,      0x70,     0x70},
++	{0x99,   0x65,    0x20,       0x00,     0x00,            0xff,     0xb3,      0x70,     0x70},
++	{0x82,   0x4d,    0x20,       0x00,     0x00,            0xff,     0xb3,      0x70,     0x70},
+ };
+ 
+ static const struct abm_parameters * const abm_settings[] = {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3827-drm-amd-display-3.2.50.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3827-drm-amd-display-3.2.50.patch
new file mode 100644
index 00000000..8ed7707a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3827-drm-amd-display-3.2.50.patch
@@ -0,0 +1,27 @@
+From c00c4478c4635c0acdc6b40a3ea10d2f2c461a88 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Mon, 26 Aug 2019 15:54:27 -0400
+Subject: [PATCH 3827/4256] drm/amd/display: 3.2.50
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 3bb4d41ffdb4..09f0a6d1ac5a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -42,7 +42,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.49"
++#define DC_VER "3.2.50"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3828-drm-amd-display-Rebuild-mapped-resources-after-pipe-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3828-drm-amd-display-Rebuild-mapped-resources-after-pipe-.patch
new file mode 100644
index 00000000..f5d52edc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3828-drm-amd-display-Rebuild-mapped-resources-after-pipe-.patch
@@ -0,0 +1,37 @@
+From 3f14dce371b93c0e539882d9afa11a60e8e26f97 Mon Sep 17 00:00:00 2001
+From: Mikita Lipski <mikita.lipski@amd.com>
+Date: Fri, 23 Aug 2019 13:26:24 -0400
+Subject: [PATCH 3828/4256] drm/amd/display: Rebuild mapped resources after
+ pipe split
+
+[why]
+The issue is specific for linux, as on timings such as 8K@60
+or 4K@144 DSC should be working in combination with ODM Combine
+in order to ensure that we can run those timings. The validation
+for those timings was passing, but when pipe split was happening
+second pipe wasn't being programmed.
+
+[how]
+Rebuild mapped resources if we split stream for ODM.
+
+Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 62e9a9826c97..9aceb159bef5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2466,6 +2466,7 @@ bool dcn20_fast_validate_bw(
+ 							&context->res_ctx, dc->res_pool,
+ 							pipe, hsplit_pipe))
+ 						goto validate_fail;
++					dcn20_build_mapped_resource(dc, context, pipe->stream);
+ 				} else
+ 					dcn20_split_stream_for_mpc(
+ 						&context->res_ctx, dc->res_pool,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3829-drm-amd-display-Replace-for-loop-w-function-call.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3829-drm-amd-display-Replace-for-loop-w-function-call.patch
new file mode 100644
index 00000000..4b1f7e71
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3829-drm-amd-display-Replace-for-loop-w-function-call.patch
@@ -0,0 +1,68 @@
+From 2d808f3432e47fbc8fc75dd42b8fa9b706ea3c6d Mon Sep 17 00:00:00 2001
+From: Wesley Chalmers <Wesley.Chalmers@amd.com>
+Date: Wed, 21 Aug 2019 16:09:27 -0400
+Subject: [PATCH 3829/4256] drm/amd/display: Replace for loop w/ function call
+
+[WHY]
+A function to adjust DPP clocks with DTO already exists; function code
+is identical to the code replaced here
+
+Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  | 25 ++-----------------
+ 1 file changed, 2 insertions(+), 23 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index 3e8ac303bd52..f1df32664414 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -196,7 +196,6 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+ 	bool enter_display_off = false;
+ 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
+ 	bool force_reset = false;
+-	int i;
+ 
+ 	if (dc->work_arounds.skip_clock_update)
+ 		return;
+@@ -278,34 +277,14 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+ 				request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz);
+ 
+ 			// Then raise any dividers that need raising
+-			for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
+-				int dpp_inst, dppclk_khz;
+-
+-				if (!context->res_ctx.pipe_ctx[i].plane_state)
+-					continue;
+-
+-				dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
+-				dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
+-
+-				clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, true);
+-			}
++			dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
+ 		} else {
+ 			// For post-programming, we can lower ref clk if needed, and unconditionally set all the DTOs
+ 
+ 			if (new_clocks->dppclk_khz < clk_mgr_base->clks.dppclk_khz)
+ 				request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz);
++			dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
+ 
+-			for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
+-				int dpp_inst, dppclk_khz;
+-
+-				if (!context->res_ctx.pipe_ctx[i].plane_state)
+-					continue;
+-
+-				dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
+-				dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
+-
+-				clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, false);
+-			}
+ 		}
+ 	}
+ 	if (update_dispclk &&
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3830-drm-amd-display-add-additional-flag-consideration-fo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3830-drm-amd-display-add-additional-flag-consideration-fo.patch
new file mode 100644
index 00000000..56c91e5f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3830-drm-amd-display-add-additional-flag-consideration-fo.patch
@@ -0,0 +1,31 @@
+From 2068230d53fe5f8d75ad20609c25c04f42978edd Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Thu, 22 Aug 2019 14:12:57 -0400
+Subject: [PATCH 3830/4256] drm/amd/display: add additional flag consideration
+ for surface update
+
+Surface dchub/dpp update would not trigger if a stream update was the
+only cause. This change now allows stream flags to trigger this update.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 81740e0c4c4e..faaf8841c61e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1375,7 +1375,7 @@ static void dcn20_program_pipe(
+ 	if (pipe_ctx->update_flags.bits.enable)
+ 		dcn20_enable_plane(dc, pipe_ctx, context);
+ 
+-	if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw)
++	if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
+ 		dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
+ 
+ 	if (pipe_ctx->update_flags.bits.enable
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3831-drm-amd-display-Add-debugfs-entry-to-force-YUV420-ou.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3831-drm-amd-display-Add-debugfs-entry-to-force-YUV420-ou.patch
new file mode 100644
index 00000000..f756f400
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3831-drm-amd-display-Add-debugfs-entry-to-force-YUV420-ou.patch
@@ -0,0 +1,110 @@
+From ef1c0ee906b4da04cbf3684cf26feab70b2b899f Mon Sep 17 00:00:00 2001
+From: Stylon Wang <stylon.wang@amd.com>
+Date: Tue, 20 Aug 2019 14:48:37 -0400
+Subject: [PATCH 3831/4256] drm/amd/display: Add debugfs entry to force YUV420
+ output
+
+[Why]
+Even if YUV420 is available for video mode, YUV444 is still
+automatically selected. This poses a problem for compliance tests.
+
+[How]
+Add a per-connector debugfs entry "force_yuv420_output" to force
+selection of YUV420 mode.
+
+Signed-off-by: Stylon Wang <stylon.wang@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  5 ++-
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  1 +
+ .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 31 +++++++++++++++++++
+ 3 files changed, 36 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index a0ae950d3a60..1b63ce6b9370 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -3380,7 +3380,7 @@ static void fill_stream_properties_from_drm_display_mode(
+ {
+ 	struct dc_crtc_timing *timing_out = &stream->timing;
+ 	const struct drm_display_info *info = &connector->display_info;
+-
++	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
+ 	memset(timing_out, 0, sizeof(struct dc_crtc_timing));
+ 
+ 	timing_out->h_border_left = 0;
+@@ -3391,6 +3391,9 @@ static void fill_stream_properties_from_drm_display_mode(
+ 	if (drm_mode_is_420_only(info, mode_in)
+ 			&& stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
+ 		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
++	else if (drm_mode_is_420_also(info, mode_in)
++			&& aconnector->force_yuv420_output)
++		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
+ 	else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
+ 			&& stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
+ 		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+index 32893635c995..c39ee21c290f 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+@@ -281,6 +281,7 @@ struct amdgpu_dm_connector {
+ 	uint32_t debugfs_dpcd_address;
+ 	uint32_t debugfs_dpcd_size;
+ #endif
++	bool force_yuv420_output;
+ };
+ 
+ #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+index 8fa160378378..1f1ed64dd78d 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+@@ -941,6 +941,33 @@ static const struct {
+ 		{"aux_dpcd_data", &dp_dpcd_data_debugfs_fops}
+ };
+ 
++/*
++ * Force YUV420 output if available from the given mode
++ */
++static int force_yuv420_output_set(void *data, u64 val)
++{
++	struct amdgpu_dm_connector *connector = data;
++
++	connector->force_yuv420_output = (bool)val;
++
++	return 0;
++}
++
++/*
++ * Check if YUV420 is forced when available from the given mode
++ */
++static int force_yuv420_output_get(void *data, u64 *val)
++{
++	struct amdgpu_dm_connector *connector = data;
++
++	*val = connector->force_yuv420_output;
++
++	return 0;
++}
++
++DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
++			 force_yuv420_output_set, "%llu\n");
++
+ void connector_debugfs_init(struct amdgpu_dm_connector *connector)
+ {
+ 	int i;
+@@ -954,6 +981,10 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector)
+ 					    dp_debugfs_entries[i].fops);
+ 		}
+ 	}
++
++	debugfs_create_file_unsafe("force_yuv420_output", 0644, dir, connector,
++				   &force_yuv420_output_fops);
++
+ }
+ 
+ /*
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3832-drm-amd-display-add-vtg-update-after-global-sync-upd.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3832-drm-amd-display-add-vtg-update-after-global-sync-upd.patch
new file mode 100644
index 00000000..5c114bed
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3832-drm-amd-display-add-vtg-update-after-global-sync-upd.patch
@@ -0,0 +1,43 @@
+From 310d024c1aa624538d9fdf7f3c62983792df4e01 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Mon, 26 Aug 2019 15:04:18 -0400
+Subject: [PATCH 3832/4256] drm/amd/display: add vtg update after global sync
+ update
+
+Global sync update was missing vtg update resulting in underflow if
+vstartup decreased a significant amount.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Jaehyun Chung <Jaehyun.Chung@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index faaf8841c61e..4bb5ad19c4cf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1361,7 +1361,7 @@ static void dcn20_program_pipe(
+ 			&& !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
+ 		dc->hwss.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
+ 
+-	if (pipe_ctx->update_flags.bits.global_sync)
++	if (pipe_ctx->update_flags.bits.global_sync) {
+ 		pipe_ctx->stream_res.tg->funcs->program_global_sync(
+ 				pipe_ctx->stream_res.tg,
+ 				pipe_ctx->pipe_dlg_param.vready_offset,
+@@ -1369,6 +1369,10 @@ static void dcn20_program_pipe(
+ 				pipe_ctx->pipe_dlg_param.vupdate_offset,
+ 				pipe_ctx->pipe_dlg_param.vupdate_width);
+ 
++		pipe_ctx->stream_res.tg->funcs->set_vtg_params(
++				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
++	}
++
+ 	if (pipe_ctx->update_flags.bits.odm)
+ 		dc->hwss.update_odm(dc, context, pipe_ctx);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3833-drm-amd-display-fix-global-sync-param-extraction-ind.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3833-drm-amd-display-fix-global-sync-param-extraction-ind.patch
new file mode 100644
index 00000000..85072d4a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3833-drm-amd-display-fix-global-sync-param-extraction-ind.patch
@@ -0,0 +1,34 @@
+From 2714e4e91ba4706ae8646d6409ad3b49968455aa Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Fri, 23 Aug 2019 14:22:40 -0400
+Subject: [PATCH 3833/4256] drm/amd/display: fix global sync param extraction
+ indexing
+
+dcn20_calculate_dlg_params was incorrectly indexing pipe src and
+dst structs when extracting global sync params.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Jaehyun Chung <Jaehyun.Chung@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 9aceb159bef5..49a147661cd4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2638,8 +2638,8 @@ void dcn20_calculate_dlg_params(
+ 			continue;
+ 
+ 		if (!visited[pipe_idx]) {
+-			display_pipe_source_params_st *src = &pipes[pipe_idx_unsplit].pipe.src;
+-			display_pipe_dest_params_st *dst = &pipes[pipe_idx_unsplit].pipe.dest;
++			display_pipe_source_params_st *src = &pipes[pipe_idx].pipe.src;
++			display_pipe_dest_params_st *dst = &pipes[pipe_idx].pipe.dest;
+ 
+ 			dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
+ 			dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3834-drm-amd-display-Handle-virtual-signal-type-in-disabl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3834-drm-amd-display-Handle-virtual-signal-type-in-disabl.patch
new file mode 100644
index 00000000..1b007862
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3834-drm-amd-display-Handle-virtual-signal-type-in-disabl.patch
@@ -0,0 +1,44 @@
+From 0c35e4608756e725b4487a1e203f914024afb97a Mon Sep 17 00:00:00 2001
+From: Martin Tsai <martin.tsai@amd.com>
+Date: Thu, 22 Aug 2019 10:02:13 +0800
+Subject: [PATCH 3834/4256] drm/amd/display: Handle virtual signal type in
+ disable_link()
+
+[Why]
+The new implementation changed the behavior to allow process setMode
+to DAL when DAL returns empty mode query for unplugged display.
+This will trigger additional disable_link().
+When unplug HDMI from MST dock, driver will update stream->signal to
+"Virtual". disable_link() will call disable_output() if the signal type
+is not DP and induce other displays on MST dock show black screen.
+
+[How]
+Don't need to process disable_output() if the signal type is virtual.
+
+Signed-off-by: Martin Tsai <martin.tsai@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index fcc25eea0d8f..a20310feb352 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2166,8 +2166,10 @@ static void disable_link(struct dc_link *link, enum signal_type signal)
+ 			dp_set_fec_ready(link, false);
+ 		}
+ #endif
+-	} else
+-		link->link_enc->funcs->disable_output(link->link_enc, signal);
++	} else {
++		if (signal != SIGNAL_TYPE_VIRTUAL)
++			link->link_enc->funcs->disable_output(link->link_enc, signal);
++	}
+ 
+ 	if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+ 		/* MST disable link only when no stream use the link */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3835-drm-amd-display-fix-i2c-wtire-mot-incorrect-issue.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3835-drm-amd-display-fix-i2c-wtire-mot-incorrect-issue.patch
new file mode 100644
index 00000000..579c8ac3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3835-drm-amd-display-fix-i2c-wtire-mot-incorrect-issue.patch
@@ -0,0 +1,44 @@
+From 5e3ca7c1893246f537cb3aca8d6296ae9a7a23f2 Mon Sep 17 00:00:00 2001
+From: Lewis Huang <Lewis.Huang@amd.com>
+Date: Tue, 27 Aug 2019 17:03:41 +0800
+Subject: [PATCH 3835/4256] drm/amd/display: fix i2c wtire mot incorrect issue
+
+[Why]
+I2C write command always send mot = true will cause sink state incorrect.
+
+[How]
+1. Remove default i2c write mot = true.
+2. Deciding mot flag by is_end_of_payload flag.
+
+Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+index f70137d67c82..588a07b525a0 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+@@ -523,7 +523,7 @@ bool dal_ddc_service_query_ddc_data(
+ 
+ 		if (write_size != 0) {
+ 			payload.write = true;
+-			payload.mot = true;
++			payload.mot = false;
+ 			payload.length = write_size;
+ 			payload.data = write_buf;
+ 
+@@ -592,7 +592,7 @@ bool dal_ddc_submit_aux_command(struct ddc_service *ddc,
+ 		current_payload.i2c_over_aux = payload->i2c_over_aux;
+ 		current_payload.length = is_end_of_payload ?
+ 			payload->length - retrieved : DEFAULT_AUX_MAX_DATA_SIZE;
+-		current_payload.mot = payload->mot ? payload->mot : !is_end_of_payload;
++		current_payload.mot = !is_end_of_payload;
+ 		current_payload.reply = payload->reply;
+ 		current_payload.write = payload->write;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3836-drm-amd-display-Separate-hardware-initialization-fro.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3836-drm-amd-display-Separate-hardware-initialization-fro.patch
new file mode 100644
index 00000000..26ee7990
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3836-drm-amd-display-Separate-hardware-initialization-fro.patch
@@ -0,0 +1,80 @@
+From 059ea4e591abd40d0726d22c38b29f4b5c99cb73 Mon Sep 17 00:00:00 2001
+From: Julian Parkin <julian.parkin@amd.com>
+Date: Mon, 12 Aug 2019 18:47:50 -0400
+Subject: [PATCH 3836/4256] drm/amd/display: Separate hardware initialization
+ from creation
+
+[Why]
+Separating the hardware initialization from the creation of the
+dc structures gives greater flexibility to the dm to override
+options for debugging.
+
+[How]
+Move the hardware initialization call to a new function,
+dc_hardware_init. No functional change is intended.
+
+Signed-off-by: Julian Parkin <julian.parkin@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
+ drivers/gpu/drm/amd/display/dc/core/dc.c          | 8 +++++---
+ drivers/gpu/drm/amd/display/dc/dc.h               | 2 ++
+ 3 files changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 1b63ce6b9370..f3e1193e9ce4 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -711,6 +711,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ 		goto error;
+ 	}
+ 
++	dc_hardware_init(adev->dm.dc);
++
+ 	adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
+ 	if (!adev->dm.freesync_module) {
+ 		DRM_ERROR(
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 1139a365aa8d..ffa6544f1e25 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -794,9 +794,6 @@ struct dc *dc_create(const struct dc_init_data *init_params)
+ 	if (false == construct(dc, init_params))
+ 		goto construct_fail;
+ 
+-	/*TODO: separate HW and SW initialization*/
+-	dc->hwss.init_hw(dc);
+-
+ 	full_pipe_count = dc->res_pool->pipe_count;
+ 	if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
+ 		full_pipe_count--;
+@@ -829,6 +826,11 @@ struct dc *dc_create(const struct dc_init_data *init_params)
+ 	return NULL;
+ }
+ 
++void dc_hardware_init(struct dc *dc)
++{
++	dc->hwss.init_hw(dc);
++}
++
+ void dc_init_callbacks(struct dc *dc,
+ 		const struct dc_callback_init *init_params)
+ {
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 09f0a6d1ac5a..a1697486b352 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -570,6 +570,8 @@ struct dc_callback_init {
+ };
+ 
+ struct dc *dc_create(const struct dc_init_data *init_params);
++void dc_hardware_init(struct dc *dc);
++
+ int dc_get_vmid_use_vector(struct dc *dc);
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3837-drm-amd-display-Do-not-double-buffer-DTO-adjustments.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3837-drm-amd-display-Do-not-double-buffer-DTO-adjustments.patch
new file mode 100644
index 00000000..e9d69135
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3837-drm-amd-display-Do-not-double-buffer-DTO-adjustments.patch
@@ -0,0 +1,58 @@
+From 6f2e055fc0eaeed19b9445543d2bcd7dbda2e7e2 Mon Sep 17 00:00:00 2001
+From: Wesley Chalmers <Wesley.Chalmers@amd.com>
+Date: Fri, 23 Aug 2019 10:56:13 -0400
+Subject: [PATCH 3837/4256] drm/amd/display: Do not double-buffer DTO
+ adjustments
+
+[WHY]
+When changing DPP global ref clock, DTO adjustments must take effect
+immediately, or else underflow may occur.
+It appears the original decision to double-buffer DTO adjustments was made to
+prevent underflows that occur when raising DPP ref clock (which is not
+double-buffered), but that same decision causes similar issues when
+lowering DPP global ref clock. The better solution is to order the
+adjustments according to whether clocks are being raised or lowered.
+
+Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 21 -------------------
+ 1 file changed, 21 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
+index f9b99f8cfc31..313d3793005e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
+@@ -117,27 +117,6 @@ void dccg2_get_dccg_ref_freq(struct dccg *dccg,
+ 
+ void dccg2_init(struct dccg *dccg)
+ {
+-	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+-
+-	// Fallthrough intentional to program all available dpp_dto's
+-	switch (dccg_dcn->base.ctx->dc->res_pool->pipe_count) {
+-	case 6:
+-		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[5], 1);
+-	case 5:
+-		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[4], 1);
+-	case 4:
+-		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[3], 1);
+-	case 3:
+-		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[2], 1);
+-	case 2:
+-		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[1], 1);
+-	case 1:
+-		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[0], 1);
+-		break;
+-	default:
+-		ASSERT(false);
+-		break;
+-	}
+ }
+ 
+ static const struct dccg_funcs dccg2_funcs = {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3838-drm-amd-display-Revert-fixup-DPP-programming-sequenc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3838-drm-amd-display-Revert-fixup-DPP-programming-sequenc.patch
new file mode 100644
index 00000000..5dca0e36
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3838-drm-amd-display-Revert-fixup-DPP-programming-sequenc.patch
@@ -0,0 +1,376 @@
+From f45067cf2a12e9f1e9f401d59ecf7298fb8e72d8 Mon Sep 17 00:00:00 2001
+From: Wesley Chalmers <Wesley.Chalmers@amd.com>
+Date: Mon, 26 Aug 2019 15:02:47 -0400
+Subject: [PATCH 3838/4256] drm/amd/display: Revert fixup DPP programming
+ sequence
+
+[WHY]
+This change was made because DTO programming was double-buffered, which
+is itself an issue. After deactivating the DTO double buffer, this
+change becomes unnecessary.
+
+This reverts commit 79a0feda4306a2e46872fffd1e5507b8e1785244
+
+Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  | 111 ++++++------------
+ drivers/gpu/drm/amd/display/dc/core/dc.c      |   3 -
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   3 +-
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c |  31 +----
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h |   2 +-
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |   3 +-
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c |   2 +-
+ .../gpu/drm/amd/display/dc/inc/core_types.h   |   1 +
+ .../amd/display/dc/inc/hw/clk_mgr_internal.h  |  10 +-
+ drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |   3 +-
+ 10 files changed, 48 insertions(+), 121 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index f1df32664414..559e16983f91 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -104,6 +104,7 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
+ {
+ 	int i;
+ 
++	clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
+ 	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
+ 		int dpp_inst, dppclk_khz;
+ 
+@@ -113,75 +114,28 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
+ 		dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
+ 		dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
+ 		clk_mgr->dccg->funcs->update_dpp_dto(
+-				clk_mgr->dccg, dpp_inst, dppclk_khz, false);
++				clk_mgr->dccg, dpp_inst, dppclk_khz);
+ 	}
+ }
+ 
+-static void update_global_dpp_clk(struct clk_mgr_internal *clk_mgr, unsigned int khz)
++void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr)
+ {
+ 	int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+-			* clk_mgr->dentist_vco_freq_khz / khz;
+-
+-	uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
+-
+-	REG_UPDATE(DENTIST_DISPCLK_CNTL,
+-			DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);
+-	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
+-}
+-
+-static void update_display_clk(struct clk_mgr_internal *clk_mgr, unsigned int khz)
+-{
++			* clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
+ 	int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+-			* clk_mgr->dentist_vco_freq_khz / khz;
++			* clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
+ 
++	uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
+ 	uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
+ 
+ 	REG_UPDATE(DENTIST_DISPCLK_CNTL,
+ 			DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
++//	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100);
++	REG_UPDATE(DENTIST_DISPCLK_CNTL,
++			DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);
++	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
+ }
+ 
+-static void request_voltage_and_program_disp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz)
+-{
+-	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+-	struct dc *dc = clk_mgr_base->ctx->dc;
+-	struct pp_smu_funcs_nv *pp_smu = NULL;
+-	bool going_up = clk_mgr->base.clks.dispclk_khz < khz;
+-
+-	if (dc->res_pool->pp_smu)
+-		pp_smu = &dc->res_pool->pp_smu->nv_funcs;
+-
+-	clk_mgr->base.clks.dispclk_khz = khz;
+-
+-	if (going_up && pp_smu && pp_smu->set_voltage_by_freq)
+-		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
+-
+-	update_display_clk(clk_mgr, khz);
+-
+-	if (!going_up && pp_smu && pp_smu->set_voltage_by_freq)
+-		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
+-}
+-
+-static void request_voltage_and_program_global_dpp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz)
+-{
+-	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+-	struct dc *dc = clk_mgr_base->ctx->dc;
+-	struct pp_smu_funcs_nv *pp_smu = NULL;
+-	bool going_up = clk_mgr->base.clks.dppclk_khz < khz;
+-
+-	if (dc->res_pool->pp_smu)
+-		pp_smu = &dc->res_pool->pp_smu->nv_funcs;
+-
+-	clk_mgr->base.clks.dppclk_khz = khz;
+-	clk_mgr->dccg->ref_dppclk = khz;
+-
+-	if (going_up && pp_smu && pp_smu->set_voltage_by_freq)
+-		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);
+-
+-	update_global_dpp_clk(clk_mgr, khz);
+-
+-	if (!going_up && pp_smu && pp_smu->set_voltage_by_freq)
+-		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);
+-}
+ 
+ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+ 			struct dc_state *context,
+@@ -192,8 +146,10 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+ 	struct dc *dc = clk_mgr_base->ctx->dc;
+ 	struct pp_smu_funcs_nv *pp_smu = NULL;
+ 	int display_count;
++	bool update_dppclk = false;
+ 	bool update_dispclk = false;
+ 	bool enter_display_off = false;
++	bool dpp_clock_lowered = false;
+ 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
+ 	bool force_reset = false;
+ 
+@@ -250,12 +206,10 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+ 
+ 	if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
+ 		clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
+-
+ 		clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support;
+ 		if (pp_smu && pp_smu->set_pstate_handshake_support)
+ 			pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);
+ 	}
+-	clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
+ 
+ 	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
+ 		clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
+@@ -263,28 +217,35 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+ 			pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000);
+ 	}
+ 
+-	if (dc->config.forced_clocks == false) {
+-		// First update display clock
+-		if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz))
+-			request_voltage_and_program_disp_clk(clk_mgr_base, new_clocks->dispclk_khz);
++	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
++		if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
++			dpp_clock_lowered = true;
++		clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
+ 
+-		// Updating DPP clock requires some more logic
+-		if (!safe_to_lower) {
+-			// For pre-programming, we need to make sure any DPP clock that will go up has to go up
++		if (pp_smu && pp_smu->set_voltage_by_freq)
++			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);
+ 
+-			// First raise the global reference if needed
+-			if (new_clocks->dppclk_khz > clk_mgr_base->clks.dppclk_khz)
+-				request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz);
++		update_dppclk = true;
++	}
+ 
+-			// Then raise any dividers that need raising
+-			dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
+-		} else {
+-			// For post-programming, we can lower ref clk if needed, and unconditionally set all the DTOs
++	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
++		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
++		if (pp_smu && pp_smu->set_voltage_by_freq)
++			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
+ 
+-			if (new_clocks->dppclk_khz < clk_mgr_base->clks.dppclk_khz)
+-				request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz);
++		update_dispclk = true;
++	}
++	if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
++		if (dpp_clock_lowered) {
++			// if clock is being lowered, increase DTO before lowering refclk
+ 			dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
+-
++			dcn20_update_clocks_update_dentist(clk_mgr);
++		} else {
++			// if clock is being raised, increase refclk before lowering DTO
++			if (update_dppclk || update_dispclk)
++				dcn20_update_clocks_update_dentist(clk_mgr);
++			if (update_dppclk)
++				dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
+ 		}
+ 	}
+ 	if (update_dispclk &&
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index ffa6544f1e25..3affefd6d427 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1655,9 +1655,6 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
+ 			updates[i].surface->update_flags.raw = 0xFFFFFFFF;
+ 	}
+ 
+-	if (type == UPDATE_TYPE_FAST && memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0)
+-		dc->optimized_required = true;
+-
+ 	return type;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 866705ea45a7..0123aec93285 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2302,8 +2302,7 @@ void update_dchubp_dpp(
+ 			dc->res_pool->dccg->funcs->update_dpp_dto(
+ 					dc->res_pool->dccg,
+ 					dpp->inst,
+-					pipe_ctx->plane_res.bw.dppclk_khz,
+-					false);
++					pipe_ctx->plane_res.bw.dppclk_khz);
+ 		else
+ 			dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
+ 						dc->clk_mgr->clks.dispclk_khz / 2 :
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
+index 313d3793005e..ece8b7452397 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
+@@ -42,16 +42,12 @@
+ #define DC_LOGGER \
+ 	dccg->ctx->logger
+ 
+-void dccg2_update_dpp_dto(struct dccg *dccg,
+-		int dpp_inst,
+-		int req_dppclk,
+-		bool reduce_divider_only)
++void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
+ {
+ 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+ 
+ 	if (dccg->ref_dppclk && req_dppclk) {
+ 		int ref_dppclk = dccg->ref_dppclk;
+-		int current_phase, current_modulo;
+ 
+ 		ASSERT(req_dppclk <= ref_dppclk);
+ 		/* need to clamp to 8 bits */
+@@ -63,28 +59,9 @@ void dccg2_update_dpp_dto(struct dccg *dccg,
+ 			if (req_dppclk > ref_dppclk)
+ 				req_dppclk = ref_dppclk;
+ 		}
+-
+-		REG_GET_2(DPPCLK_DTO_PARAM[dpp_inst],
+-				DPPCLK0_DTO_PHASE, &current_phase,
+-				DPPCLK0_DTO_MODULO, &current_modulo);
+-
+-		if (reduce_divider_only) {
+-			// requested phase/modulo greater than current
+-			if (req_dppclk * current_modulo >= current_phase * ref_dppclk) {
+-				REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
+-						DPPCLK0_DTO_PHASE, req_dppclk,
+-						DPPCLK0_DTO_MODULO, ref_dppclk);
+-			} else {
+-				REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
+-						DPPCLK0_DTO_PHASE, current_phase,
+-						DPPCLK0_DTO_MODULO, current_modulo);
+-			}
+-		} else {
+-			REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
+-					DPPCLK0_DTO_PHASE, req_dppclk,
+-					DPPCLK0_DTO_MODULO, ref_dppclk);
+-		}
+-
++		REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
++				DPPCLK0_DTO_PHASE, req_dppclk,
++				DPPCLK0_DTO_MODULO, ref_dppclk);
+ 		REG_UPDATE(DPPCLK_DTO_CTRL,
+ 				DPPCLK_DTO_ENABLE[dpp_inst], 1);
+ 	} else {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+index 74a074a873cd..2205cb0204e7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+@@ -97,7 +97,7 @@ struct dcn_dccg {
+ 	const struct dccg_mask *dccg_mask;
+ };
+ 
+-void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk, bool raise_divider_only);
++void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
+ 
+ void dccg2_get_dccg_ref_freq(struct dccg *dccg,
+ 		unsigned int xtalin_freq_inKhz,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 4bb5ad19c4cf..84aae9c05781 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1208,8 +1208,7 @@ static void dcn20_update_dchubp_dpp(
+ 		dc->res_pool->dccg->funcs->update_dpp_dto(
+ 				dc->res_pool->dccg,
+ 				dpp->inst,
+-				pipe_ctx->plane_res.bw.dppclk_khz,
+-				false);
++				pipe_ctx->plane_res.bw.dppclk_khz);
+ 	}
+ 
+ 	/* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 49a147661cd4..d1901ab5fb8c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2622,7 +2622,7 @@ void dcn20_calculate_dlg_params(
+ 	context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
+ 	context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
+ 	context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
+-	context->bw_ctx.bw.dcn.clk.fclk_khz = 0;
++	context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
+ 	context->bw_ctx.bw.dcn.clk.p_state_change_support =
+ 		context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
+ 							!= dm_dram_clock_change_unsupported;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index f189307750ab..daf8d5d9c3f1 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -231,6 +231,7 @@ struct resource_pool {
+ 
+ struct dcn_fe_bandwidth {
+ 	int dppclk_khz;
++
+ };
+ 
+ struct stream_resource {
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+index 7dd46eb96d67..213046de1675 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+@@ -281,14 +281,8 @@ static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_cl
+ 
+ static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support)
+ {
+-	if (cur_support != calc_support) {
+-		if (calc_support == true && safe_to_lower)
+-			return true;
+-		else if (calc_support == false && !safe_to_lower)
+-			return true;
+-	}
+-
+-	return false;
++	// Whenever we are transitioning pstate support, we always want to notify prior to committing state
++	return (calc_support != cur_support) ? !safe_to_lower : false;
+ }
+ 
+ int clk_mgr_helper_get_active_display_cnt(
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+index d8e744f366e5..05ee5295d2c1 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+@@ -38,8 +38,7 @@ struct dccg {
+ struct dccg_funcs {
+ 	void (*update_dpp_dto)(struct dccg *dccg,
+ 			int dpp_inst,
+-			int req_dppclk,
+-			bool reduce_divider_only);
++			int req_dppclk);
+ 	void (*get_dccg_ref_freq)(struct dccg *dccg,
+ 			unsigned int xtalin_freq_inKhz,
+ 			unsigned int *dccg_ref_freq_inKhz);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3839-drm-amd-display-set-minimum-abm-backlight-level.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3839-drm-amd-display-set-minimum-abm-backlight-level.patch
new file mode 100644
index 00000000..5c66a82b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3839-drm-amd-display-set-minimum-abm-backlight-level.patch
@@ -0,0 +1,189 @@
+From 55d80ae7e660d3698395daba46a71a91cb6be32d Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Thu, 29 Aug 2019 10:49:12 -0400
+Subject: [PATCH 3839/4256] drm/amd/display: set minimum abm backlight level
+
+[Why]
+A lot of the time, the backlight characteristic curve maps min backlight
+to a non-zero value.
+But there are cases where we want the curve to intersect at 0.
+In this scenario even if OS never asks to set 0% backlight, the ABM
+reduction can result in backlight being lowered close to 0.
+This particularly can cause problems in some LED drivers, and in
+general just looks like backlight is completely off.
+
+[How]
+Add default cap to disallow backlight from dropping below 1%
+even after ABM reduction is applied.
+
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  5 ++
+ .../amd/display/modules/power/power_helpers.c | 77 +++++++++++--------
+ .../amd/display/modules/power/power_helpers.h |  1 +
+ 3 files changed, 49 insertions(+), 34 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index f3e1193e9ce4..bc6389e13b12 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -939,6 +939,11 @@ static int dm_late_init(void *handle)
+ 	params.backlight_lut_array_size = 16;
+ 	params.backlight_lut_array = linear_lut;
+ 
++	/* Min backlight level after ABM reduction,  Don't allow below 1%
++	 * 0xFFFF x 0.01 = 0x28F
++	 */
++	params.min_abm_backlight = 0x28F;
++
+ 	/* todo will enable for navi10 */
+ 	if (adev->asic_type <= CHIP_RAVEN) {
+ 		ret = dmcu_load_iram(dmcu, params);
+diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+index cc6b794821d9..4e2f615c3566 100644
+--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
++++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+@@ -115,7 +115,7 @@ static const struct abm_parameters * const abm_settings[] = {
+ /* NOTE: iRAM is 256B in size */
+ struct iram_table_v_2 {
+ 	/* flags                      */
+-	uint16_t flags;							/* 0x00 U16  */
++	uint16_t min_abm_backlight;					/* 0x00 U16  */
+ 
+ 	/* parameters for ABM2.0 algorithm */
+ 	uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];		/* 0x02 U0.8 */
+@@ -140,10 +140,10 @@ struct iram_table_v_2 {
+ 
+ 	/* For reading PSR State directly from IRAM */
+ 	uint8_t psr_state;						/* 0xf0       */
+-	uint8_t dmcu_mcp_interface_version;							/* 0xf1       */
+-	uint8_t dmcu_abm_feature_version;							/* 0xf2       */
+-	uint8_t dmcu_psr_feature_version;							/* 0xf3       */
+-	uint16_t dmcu_version;										/* 0xf4       */
++	uint8_t dmcu_mcp_interface_version;				/* 0xf1       */
++	uint8_t dmcu_abm_feature_version;				/* 0xf2       */
++	uint8_t dmcu_psr_feature_version;				/* 0xf3       */
++	uint16_t dmcu_version;						/* 0xf4       */
+ 	uint8_t dmcu_state;						/* 0xf6       */
+ 
+ 	uint16_t blRampReduction;					/* 0xf7       */
+@@ -164,42 +164,43 @@ struct iram_table_v_2_2 {
+ 	uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];		/* 0x16 U0.8 */
+ 	uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];	/* 0x2a U2.6 */
+ 	uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];		/* 0x3e U2.6 */
+-	uint8_t hybrid_factor[NUM_AGGR_LEVEL];						/* 0x52 U0.8 */
+-	uint8_t contrast_factor[NUM_AGGR_LEVEL];					/* 0x56 U0.8 */
+-	uint8_t deviation_gain[NUM_AGGR_LEVEL];						/* 0x5a U0.8 */
+-	uint8_t iir_curve[NUM_AMBI_LEVEL];							/* 0x5e U0.8 */
+-	uint8_t min_knee[NUM_AGGR_LEVEL];							/* 0x63 U0.8 */
+-	uint8_t max_knee[NUM_AGGR_LEVEL];							/* 0x67 U0.8 */
+-	uint8_t pad[21];											/* 0x6b U0.8 */
++	uint8_t hybrid_factor[NUM_AGGR_LEVEL];				/* 0x52 U0.8 */
++	uint8_t contrast_factor[NUM_AGGR_LEVEL];			/* 0x56 U0.8 */
++	uint8_t deviation_gain[NUM_AGGR_LEVEL];				/* 0x5a U0.8 */
++	uint8_t iir_curve[NUM_AMBI_LEVEL];				/* 0x5e U0.8 */
++	uint8_t min_knee[NUM_AGGR_LEVEL];				/* 0x63 U0.8 */
++	uint8_t max_knee[NUM_AGGR_LEVEL];				/* 0x67 U0.8 */
++	uint16_t min_abm_backlight;					/* 0x6b U16  */
++	uint8_t pad[19];						/* 0x6d U0.8 */
+ 
+ 	/* parameters for crgb conversion */
+-	uint16_t crgb_thresh[NUM_POWER_FN_SEGS];					/* 0x80 U3.13 */
+-	uint16_t crgb_offset[NUM_POWER_FN_SEGS];					/* 0x90 U1.15 */
+-	uint16_t crgb_slope[NUM_POWER_FN_SEGS];						/* 0xa0 U4.12 */
++	uint16_t crgb_thresh[NUM_POWER_FN_SEGS];			/* 0x80 U3.13 */
++	uint16_t crgb_offset[NUM_POWER_FN_SEGS];			/* 0x90 U1.15 */
++	uint16_t crgb_slope[NUM_POWER_FN_SEGS];				/* 0xa0 U4.12 */
+ 
+ 	/* parameters for custom curve */
+ 	/* thresholds for brightness --> backlight */
+-	uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS];			/* 0xb0 U16.0 */
++	uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS];		/* 0xb0 U16.0 */
+ 	/* offsets for brightness --> backlight */
+-	uint16_t backlight_offsets[NUM_BL_CURVE_SEGS];				/* 0xd0 U16.0 */
++	uint16_t backlight_offsets[NUM_BL_CURVE_SEGS];			/* 0xd0 U16.0 */
+ 
+ 	/* For reading PSR State directly from IRAM */
+-	uint8_t psr_state;											/* 0xf0       */
+-	uint8_t dmcu_mcp_interface_version;							/* 0xf1       */
+-	uint8_t dmcu_abm_feature_version;							/* 0xf2       */
+-	uint8_t dmcu_psr_feature_version;							/* 0xf3       */
+-	uint16_t dmcu_version;										/* 0xf4       */
+-	uint8_t dmcu_state;											/* 0xf6       */
+-
+-	uint8_t dummy1;												/* 0xf7       */
+-	uint8_t dummy2;												/* 0xf8       */
+-	uint8_t dummy3;												/* 0xf9       */
+-	uint8_t dummy4;												/* 0xfa       */
+-	uint8_t dummy5;												/* 0xfb       */
+-	uint8_t dummy6;												/* 0xfc       */
+-	uint8_t dummy7;												/* 0xfd       */
+-	uint8_t dummy8;												/* 0xfe       */
+-	uint8_t dummy9;												/* 0xff       */
++	uint8_t psr_state;						/* 0xf0       */
++	uint8_t dmcu_mcp_interface_version;				/* 0xf1       */
++	uint8_t dmcu_abm_feature_version;				/* 0xf2       */
++	uint8_t dmcu_psr_feature_version;				/* 0xf3       */
++	uint16_t dmcu_version;						/* 0xf4       */
++	uint8_t dmcu_state;						/* 0xf6       */
++
++	uint8_t dummy1;							/* 0xf7       */
++	uint8_t dummy2;							/* 0xf8       */
++	uint8_t dummy3;							/* 0xf9       */
++	uint8_t dummy4;							/* 0xfa       */
++	uint8_t dummy5;							/* 0xfb       */
++	uint8_t dummy6;							/* 0xfc       */
++	uint8_t dummy7;							/* 0xfd       */
++	uint8_t dummy8;							/* 0xfe       */
++	uint8_t dummy9;							/* 0xff       */
+ };
+ #pragma pack(pop)
+ 
+@@ -271,7 +272,8 @@ void fill_iram_v_2(struct iram_table_v_2 *ram_table, struct dmcu_iram_parameters
+ {
+ 	unsigned int set = params.set;
+ 
+-	ram_table->flags = 0x0;
++	ram_table->min_abm_backlight =
++			cpu_to_be16(params.min_abm_backlight);
+ 	ram_table->deviation_gain = 0xb3;
+ 
+ 	ram_table->blRampReduction =
+@@ -445,6 +447,9 @@ void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parame
+ 
+ 	ram_table->flags = 0x0;
+ 
++	ram_table->min_abm_backlight =
++			cpu_to_be16(params.min_abm_backlight);
++
+ 	ram_table->deviation_gain[0] = 0xb3;
+ 	ram_table->deviation_gain[1] = 0xa8;
+ 	ram_table->deviation_gain[2] = 0x98;
+@@ -588,6 +593,10 @@ void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parame
+ 	unsigned int set = params.set;
+ 
+ 	ram_table->flags = 0x0;
++
++	ram_table->min_abm_backlight =
++			cpu_to_be16(params.min_abm_backlight);
++
+ 	for (i = 0; i < NUM_AGGR_LEVEL; i++) {
+ 		ram_table->hybrid_factor[i] = abm_settings[set][i].brightness_gain;
+ 		ram_table->contrast_factor[i] = abm_settings[set][i].contrast_factor;
+diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
+index da5df00fedce..e54157026330 100644
+--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
++++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h
+@@ -38,6 +38,7 @@ struct dmcu_iram_parameters {
+ 	unsigned int backlight_lut_array_size;
+ 	unsigned int backlight_ramping_reduction;
+ 	unsigned int backlight_ramping_start;
++	unsigned int min_abm_backlight;
+ 	unsigned int set;
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3840-drm-amd-display-Set-number-of-pipes-to-1-if-the-seco.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3840-drm-amd-display-Set-number-of-pipes-to-1-if-the-seco.patch
new file mode 100644
index 00000000..d6a235c8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3840-drm-amd-display-Set-number-of-pipes-to-1-if-the-seco.patch
@@ -0,0 +1,41 @@
+From 082ff1684f993a8d2ee63ed18dbd9412887c2952 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Wed, 28 Aug 2019 18:30:43 -0400
+Subject: [PATCH 3840/4256] drm/amd/display: Set number of pipes to 1 if the
+ second pipe was disabled
+
+[why]
+Some ODM-related register settings are inconsistently updated by VBIOS, causing
+the state in DC to be invalid, which would then end up crashing in certain
+use-cases (such as disable/enable device).
+
+[how]
+Check the enabled status of the second pipe when determining the number of
+OPTC sources. If the second pipe is disabled, set the number of sources to 1
+regardless of other settings (that may not be updated correctly).
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+index 2137e2be2140..dda90995ba93 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+@@ -287,6 +287,10 @@ void optc2_get_optc_source(struct timing_generator *optc,
+ 		*num_of_src_opp = 2;
+ 	else
+ 		*num_of_src_opp = 1;
++
++	/* Work around VBIOS not updating OPTC_NUM_OF_INPUT_SEGMENT */
++	if (*src_opp_id_1 == 0xf)
++		*num_of_src_opp = 1;
+ }
+ 
+ void optc2_set_dwb_source(struct timing_generator *optc,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3841-drm-amd-display-Optimize-clocks-on-clock-change.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3841-drm-amd-display-Optimize-clocks-on-clock-change.patch
new file mode 100644
index 00000000..55b7abe3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3841-drm-amd-display-Optimize-clocks-on-clock-change.patch
@@ -0,0 +1,67 @@
+From 9f6396ff839b5c8bbd295039e70e08c39dc8066c Mon Sep 17 00:00:00 2001
+From: Wesley Chalmers <Wesley.Chalmers@amd.com>
+Date: Fri, 30 Aug 2019 14:59:00 -0400
+Subject: [PATCH 3841/4256] drm/amd/display: Optimize clocks on clock change
+
+[WHY]
+Presently, there is no way for clocks to be lowered, only raised.
+
+[HOW]
+Compare clock status against previous known clock status, and optimize
+if different.
+This requires re-ordering the layout of the dc_clocks structure, as the
+current ordering allows identical clock states to appear different.
+
+Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++
+ drivers/gpu/drm/amd/display/dc/dc.h      | 8 ++++----
+ 2 files changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 3affefd6d427..ffa6544f1e25 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1655,6 +1655,9 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
+ 			updates[i].surface->update_flags.raw = 0xFFFFFFFF;
+ 	}
+ 
++	if (type == UPDATE_TYPE_FAST && memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0)
++		dc->optimized_required = true;
++
+ 	return type;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index a1697486b352..afbcf052f478 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -255,11 +255,7 @@ enum wm_report_mode {
+  */
+ struct dc_clocks {
+ 	int dispclk_khz;
+-	int max_supported_dppclk_khz;
+-	int max_supported_dispclk_khz;
+ 	int dppclk_khz;
+-	int bw_dppclk_khz; /*a copy of dppclk_khz*/
+-	int bw_dispclk_khz;
+ 	int dcfclk_khz;
+ 	int socclk_khz;
+ 	int dcfclk_deep_sleep_khz;
+@@ -273,6 +269,10 @@ struct dc_clocks {
+ 	 * optimization required
+ 	 */
+ 	bool prev_p_state_change_support;
++	int max_supported_dppclk_khz;
++	int max_supported_dispclk_khz;
++	int bw_dppclk_khz; /*a copy of dppclk_khz*/
++	int bw_dispclk_khz;
+ };
+ 
+ struct dc_bw_validation_profile {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3842-drm-amd-display-update-odm-mode-validation-to-be-in-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3842-drm-amd-display-update-odm-mode-validation-to-be-in-.patch
new file mode 100644
index 00000000..6e03c996
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3842-drm-amd-display-update-odm-mode-validation-to-be-in-.patch
@@ -0,0 +1,113 @@
+From 3ce73c2b6ec251fba6b91c0e65b7bb6938f5b9e4 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Fri, 30 Aug 2019 16:32:13 -0400
+Subject: [PATCH 3842/4256] drm/amd/display: update odm mode validation to be
+ in line with policy
+
+Previously 8k30 worked with dsc and odm combine due to a workaround that ran
+the formula a second time with dsc support enable should dsc validation fail.
+This worked when clocks were low enough for formula to enable odm to lower
+voltage, however now broke due to increased clocks.
+
+This change updates the ODM combine policy within the formula to properly
+reflect our current policy within DC, only enabling ODM when we have to, as
+well as adding a check for viewport width when dsc is enabled.
+
+As a side effect the redundant call to dml when odm is required is now
+unnecessary.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 22 +------------------
+ .../dc/dml/dcn20/display_mode_vba_20v2.c      |  9 +++++++-
+ 2 files changed, 9 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index d1901ab5fb8c..8d81c65157d4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2246,11 +2246,7 @@ bool dcn20_fast_validate_bw(
+ 	bool out = false;
+ 
+ 	int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
+-	bool odm_capable = context->bw_ctx.dml.ip.odm_capable;
+ 	bool force_split = false;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-	bool failed_non_odm_dsc = false;
+-#endif
+ 	int split_threshold = dc->res_pool->pipe_count / 2;
+ 	bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
+ 
+@@ -2327,24 +2323,8 @@ bool dcn20_fast_validate_bw(
+ 		goto validate_out;
+ 	}
+ 
+-	context->bw_ctx.dml.ip.odm_capable = 0;
+-
+ 	vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
+ 
+-	context->bw_ctx.dml.ip.odm_capable = odm_capable;
+-
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-	/* 1 dsc per stream dsc validation */
+-	if (vlevel <= context->bw_ctx.dml.soc.num_states)
+-		if (!dcn20_validate_dsc(dc, context)) {
+-			failed_non_odm_dsc = true;
+-			vlevel = context->bw_ctx.dml.soc.num_states + 1;
+-		}
+-#endif
+-
+-	if (vlevel > context->bw_ctx.dml.soc.num_states && odm_capable)
+-		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
+-
+ 	if (vlevel > context->bw_ctx.dml.soc.num_states)
+ 		goto validate_fail;
+ 
+@@ -2480,7 +2460,7 @@ bool dcn20_fast_validate_bw(
+ 	}
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	/* Actual dsc count per stream dsc validation*/
+-	if (failed_non_odm_dsc && !dcn20_validate_dsc(dc, context)) {
++	if (!dcn20_validate_dsc(dc, context)) {
+ 		context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
+ 				DML_FAIL_DSC_VALIDATION_FAILURE;
+ 		goto validate_fail;
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+index 0fafd693ffb4..841ed6c23f93 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+@@ -38,6 +38,7 @@
+ 
+ #define BPP_INVALID 0
+ #define BPP_BLENDED_PIPE 0xffffffff
++#define DCN20_MAX_DSC_IMAGE_WIDTH 5184
+ 
+ static double adjust_ReturnBW(
+ 		struct display_mode_lib *mode_lib,
+@@ -3901,6 +3902,10 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode
+ 				mode_lib->vba.MaximumSwathWidthInLineBuffer);
+ 	}
+ 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		double MaxMaxDispclkRoundedDown = RoundToDFSGranularityDown(
++			mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states],
++			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
++
+ 		for (j = 0; j < 2; j++) {
+ 			mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(
+ 				mode_lib->vba.MaxDispclk[i],
+@@ -3925,7 +3930,9 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode
+ 						&& i == mode_lib->vba.soc.num_states)
+ 					mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
+ 							* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
+-				if (mode_lib->vba.ODMCapability == false || mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine <= mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
++				if (mode_lib->vba.ODMCapability == false ||
++						(locals->PlaneRequiredDISPCLKWithoutODMCombine <= MaxMaxDispclkRoundedDown
++							&& (!locals->DSCEnabled[k] || locals->HActive[k] <= DCN20_MAX_DSC_IMAGE_WIDTH))) {
+ 					locals->ODMCombineEnablePerState[i][k] = false;
+ 					mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
+ 				} else {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3843-drm-amd-display-enable-single-dp-seamless-boot.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3843-drm-amd-display-enable-single-dp-seamless-boot.patch
new file mode 100644
index 00000000..1105730a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3843-drm-amd-display-enable-single-dp-seamless-boot.patch
@@ -0,0 +1,255 @@
+From 3fd571fd36708e2dd7c6873038e113251468d836 Mon Sep 17 00:00:00 2001
+From: Martin Leung <martin.leung@amd.com>
+Date: Fri, 16 Aug 2019 17:26:23 -0400
+Subject: [PATCH 3843/4256] drm/amd/display: enable single dp seamless boot
+
+[why]
+seamless boot didn't work for non edp's before
+
+[how]
+removed edp-specific code, made dp read uefi-set link settings. Also fixed
+a hubbub code line to be consistent with usage of function.
+
+Signed-off-by: Martin Leung <martin.leung@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c      | 30 +++++-----
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 57 ++++++++++++-------
+ .../gpu/drm/amd/display/dc/core/dc_resource.c | 26 ++++-----
+ .../drm/amd/display/dc/dcn20/dcn20_hubbub.c   |  5 +-
+ 4 files changed, 71 insertions(+), 47 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index ffa6544f1e25..e5fd65f634ac 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -983,29 +983,33 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
+ {
+ 	struct timing_generator *tg;
+ 	struct dc_link *link = sink->link;
+-	unsigned int enc_inst, tg_inst;
++	unsigned int enc_inst, tg_inst, i;
++
++	// Seamless port only support single DP and EDP so far
++	if (sink->sink_signal != SIGNAL_TYPE_DISPLAY_PORT &&
++		sink->sink_signal != SIGNAL_TYPE_EDP)
++		return false;
+ 
+ 	/* Check for enabled DIG to identify enabled display */
+ 	if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
+ 		return false;
+ 
+-	/* Check for which front end is used by this encoder.
+-	 * Note the inst is 1 indexed, where 0 is undefined.
+-	 * Note that DIG_FE can source from different OTG but our
+-	 * current implementation always map 1-to-1, so this code makes
+-	 * the same assumption and doesn't check OTG source.
+-	 */
+ 	enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
+ 
+-	/* Instance should be within the range of the pool */
+-	if (enc_inst >= dc->res_pool->pipe_count)
++	if (enc_inst == ENGINE_ID_UNKNOWN)
+ 		return false;
+ 
+-	if (enc_inst >= dc->res_pool->stream_enc_count)
+-		return false;
++	for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
++		if (dc->res_pool->stream_enc[i]->id == enc_inst) {
++			tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
++				dc->res_pool->stream_enc[i]);
++			break;
++		}
++	}
+ 
+-	tg_inst = dc->res_pool->stream_enc[enc_inst]->funcs->dig_source_otg(
+-		dc->res_pool->stream_enc[enc_inst]);
++	// tg_inst not found
++	if (i == dc->res_pool->stream_enc_count)
++		return false;
+ 
+ 	if (tg_inst >= dc->res_pool->timing_generator_count)
+ 		return false;
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index a20310feb352..66758033757d 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -517,7 +517,7 @@ static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *lin
+ }
+ 
+ 
+-static void read_edp_current_link_settings_on_detect(struct dc_link *link)
++static void read_current_link_settings_on_detect(struct dc_link *link)
+ {
+ 	union lane_count_set lane_count_set = { {0} };
+ 	uint8_t link_bw_set;
+@@ -552,17 +552,23 @@ static void read_edp_current_link_settings_on_detect(struct dc_link *link)
+ 			&link_bw_set, sizeof(link_bw_set));
+ 
+ 	if (link_bw_set == 0) {
+-		/* If standard link rates are not being used,
+-		 * Read DPCD 00115h to find the link rate set used
+-		 */
+-		core_link_read_dpcd(link, DP_LINK_RATE_SET,
+-				&link_rate_set, sizeof(link_rate_set));
+-
+-		if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
+-			link->cur_link_settings.link_rate =
+-				link->dpcd_caps.edp_supported_link_rates[link_rate_set];
+-			link->cur_link_settings.link_rate_set = link_rate_set;
+-			link->cur_link_settings.use_link_rate_set = true;
++		if (link->connector_signal == SIGNAL_TYPE_EDP) {
++			/* If standard link rates are not being used,
++			 * Read DPCD 00115h to find the edp link rate set used
++			 */
++			core_link_read_dpcd(link, DP_LINK_RATE_SET,
++					&link_rate_set, sizeof(link_rate_set));
++
++			// edp_supported_link_rates_count = 0 for DP
++			if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
++				link->cur_link_settings.link_rate =
++						link->dpcd_caps.edp_supported_link_rates[link_rate_set];
++				link->cur_link_settings.link_rate_set = link_rate_set;
++				link->cur_link_settings.use_link_rate_set = true;
++			}
++		} else {
++			// Link Rate not found. Seamless boot may not work.
++			ASSERT(false);
+ 		}
+ 	} else {
+ 		link->cur_link_settings.link_rate = link_bw_set;
+@@ -750,6 +756,7 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
+ 	struct dpcd_caps prev_dpcd_caps;
+ 	bool same_dpcd = true;
+ 	enum dc_connection_type new_connection_type = dc_connection_none;
++	bool perform_dp_seamless_boot = false;
+ 	DC_LOGGER_INIT(link->ctx->logger);
+ 
+ 	if (dc_is_virtual_signal(link->connector_signal))
+@@ -806,15 +813,15 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
+ 		}
+ 
+ 		case SIGNAL_TYPE_EDP: {
+-			read_edp_current_link_settings_on_detect(link);
++			read_current_link_settings_on_detect(link);
+ 			detect_edp_sink_caps(link);
+-			sink_caps.transaction_type =
+-				DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
++			sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
+ 			sink_caps.signal = SIGNAL_TYPE_EDP;
+ 			break;
+ 		}
+ 
+ 		case SIGNAL_TYPE_DISPLAY_PORT: {
++
+ 			/* wa HPD high coming too early*/
+ 			if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
+ 
+@@ -868,6 +875,17 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
+ 				return false;
+ 			}
+ 
++			// For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
++			if (reason == DETECT_REASON_BOOT &&
++					dc_ctx->dc->config.power_down_display_on_boot == false &&
++					link->link_status.link_active == true)
++				perform_dp_seamless_boot = true;
++
++			if (perform_dp_seamless_boot) {
++				read_current_link_settings_on_detect(link);
++				link->verified_link_cap = link->reported_link_cap;
++			}
++
+ 			break;
+ 		}
+ 
+@@ -952,10 +970,11 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
+ 			 *  two link trainings
+ 			 */
+ 
+-			/* deal with non-mst cases */
+-			dp_verify_link_cap_with_retries(link,
+-					&link->reported_link_cap,
+-					LINK_TRAINING_MAX_VERIFY_RETRY);
++			// verify link cap for SST non-seamless boot
++			if (!perform_dp_seamless_boot)
++				dp_verify_link_cap_with_retries(link,
++						&link->reported_link_cap,
++						LINK_TRAINING_MAX_VERIFY_RETRY);
+ 		} else {
+ 			// If edid is the same, then discard new sink and revert back to original sink
+ 			if (same_edid) {
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 2ae883a248da..af85d6cf4427 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -1845,28 +1845,28 @@ static int acquire_resource_from_hw_enabled_state(
+ 		struct dc_stream_state *stream)
+ {
+ 	struct dc_link *link = stream->link;
+-	unsigned int inst, tg_inst;
++	unsigned int inst, tg_inst, i;
+ 
+ 	/* Check for enabled DIG to identify enabled display */
+ 	if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
+ 		return -1;
+ 
+-	/* Check for which front end is used by this encoder.
+-	 * Note the inst is 1 indexed, where 0 is undefined.
+-	 * Note that DIG_FE can source from different OTG but our
+-	 * current implementation always map 1-to-1, so this code makes
+-	 * the same assumption and doesn't check OTG source.
+-	 */
+ 	inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
+ 
+-	/* Instance should be within the range of the pool */
+-	if (inst >= pool->pipe_count)
+-		return -1;
++	if (inst == ENGINE_ID_UNKNOWN)
++		return false;
+ 
+-	if (inst >= pool->stream_enc_count)
+-		return -1;
++	for (i = 0; i < pool->stream_enc_count; i++) {
++		if (pool->stream_enc[i]->id == inst) {
++			tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
++				pool->stream_enc[i]);
++			break;
++		}
++	}
+ 
+-	tg_inst = pool->stream_enc[inst]->funcs->dig_source_otg(pool->stream_enc[inst]);
++	// tg_inst not found
++	if (i == pool->stream_enc_count)
++		return false;
+ 
+ 	if (tg_inst >= pool->timing_generator_count)
+ 		return false;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+index b83c022e2c6f..e0a6e30ac3e1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+@@ -588,7 +588,7 @@ static void hubbub2_program_watermarks(
+ 			DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
+ 	REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 180);
+ 
+-	hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
++	hubbub->funcs->allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
+ }
+ 
+ static const struct hubbub_funcs hubbub2_funcs = {
+@@ -600,7 +600,8 @@ static const struct hubbub_funcs hubbub2_funcs = {
+ 	.get_dcc_compression_cap = hubbub2_get_dcc_compression_cap,
+ 	.wm_read_state = hubbub2_wm_read_state,
+ 	.get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
+-	.program_watermarks = hubbub2_program_watermarks
++	.program_watermarks = hubbub2_program_watermarks,
++	.allow_self_refresh_control = hubbub1_allow_self_refresh_control
+ };
+ 
+ void hubbub2_construct(struct dcn20_hubbub *hubbub,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3844-drm-amd-display-3.2.51.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3844-drm-amd-display-3.2.51.patch
new file mode 100644
index 00000000..3c8beb7f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3844-drm-amd-display-3.2.51.patch
@@ -0,0 +1,27 @@
+From 92dce0151e9356e3b29131bb2c08f09fffea3ef6 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Tue, 3 Sep 2019 10:39:16 -0400
+Subject: [PATCH 3844/4256] drm/amd/display: 3.2.51
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index afbcf052f478..b4954028a8dc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -42,7 +42,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.50"
++#define DC_VER "3.2.51"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3845-drm-amd-display-Add-missing-HBM-support-and-raise-Ve.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3845-drm-amd-display-Add-missing-HBM-support-and-raise-Ve.patch
new file mode 100644
index 00000000..3ee341d6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3845-drm-amd-display-Add-missing-HBM-support-and-raise-Ve.patch
@@ -0,0 +1,67 @@
+From b12144aa5fc618321cb7c664a2d154486897204e Mon Sep 17 00:00:00 2001
+From: Zhan Liu <zhan.liu@amd.com>
+Date: Thu, 22 Aug 2019 14:54:18 -0400
+Subject: [PATCH 3845/4256] drm/amd/display: Add missing HBM support and raise
+ Vega20's uclk.
+
+[Why]
+When more than 2 displays are connected to the graphics card,
+only the minimum memory clock is needed. However, when more
+displays are connected, the minimum memory clock is not
+sufficient enough to support the overwhelming bandwidth.
+System will hang under this circumstance.
+
+Also, the old code didn't address HBM cards, which has 2
+pseudo channels. We need to add the HBM part here.
+
+[How]
+When graphics card connects to 2 or more displays,
+switch to high memory clock. Also, choose memory
+multiplier based on whether its regular DRAM or HBM.
+
+Signed-off-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 18 ++++++++++++++++--
+ 1 file changed, 16 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+index ee32d2c19305..36277bca0326 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+@@ -174,6 +174,10 @@ void dce11_pplib_apply_display_requirements(
+ 	struct dc_state *context)
+ {
+ 	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
++	int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
++
++	if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm)
++		memory_type_multiplier = MEMORY_TYPE_HBM;
+ 
+ 	pp_display_cfg->all_displays_in_sync =
+ 		context->bw_ctx.bw.dce.all_displays_in_sync;
+@@ -186,8 +190,18 @@ void dce11_pplib_apply_display_requirements(
+ 	pp_display_cfg->cpu_pstate_separation_time =
+ 			context->bw_ctx.bw.dce.blackout_recovery_time_us;
+ 
+-	pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz
+-		/ MEMORY_TYPE_MULTIPLIER_CZ;
++	/*
++	 * TODO: determine whether the bandwidth has reached memory's limitation
++	 * , then change minimum memory clock based on real-time bandwidth
++	 * limitation.
++	 */
++	if (ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) {
++		pp_display_cfg->min_memory_clock_khz = max(pp_display_cfg->min_memory_clock_khz,
++			(uint32_t) (dc->bw_vbios->high_yclk.value / memory_type_multiplier / 10000));
++	} else {
++		pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz
++			/ memory_type_multiplier;
++	}
+ 
+ 	pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
+ 			dc,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3846-drm-amd-display-3.2.51.1.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3846-drm-amd-display-3.2.51.1.patch
new file mode 100644
index 00000000..0a34a4f3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3846-drm-amd-display-3.2.51.1.patch
@@ -0,0 +1,27 @@
+From 705734e682373b90c182a7d98a88bafc7f4388df Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Tue, 3 Sep 2019 15:54:43 -0400
+Subject: [PATCH 3846/4256] drm/amd/display: 3.2.51.1
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index b4954028a8dc..ed596ffd7468 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -42,7 +42,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.51"
++#define DC_VER "3.2.51.1"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3847-drm-amd-display-fix-use-of-uninitialized-variable.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3847-drm-amd-display-fix-use-of-uninitialized-variable.patch
new file mode 100644
index 00000000..e7d8686c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3847-drm-amd-display-fix-use-of-uninitialized-variable.patch
@@ -0,0 +1,44 @@
+From e00ae6bee032671f36bcb5c2661fb6912181b9b5 Mon Sep 17 00:00:00 2001
+From: Martin Leung <martin.leung@amd.com>
+Date: Tue, 3 Sep 2019 15:22:30 -0400
+Subject: [PATCH 3847/4256] drm/amd/display: fix use of uninitialized variable
+
+tg_inst may be used uninitialized, so initialize it to 0.
+
+Signed-off-by: Martin Leung <martin.leung@amd.com>
+Reviewed-by: Jaehyun Chung <Jaehyun.Chung@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c          | 2 +-
+ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index e5fd65f634ac..8a1947e6741a 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -983,7 +983,7 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
+ {
+ 	struct timing_generator *tg;
+ 	struct dc_link *link = sink->link;
+-	unsigned int enc_inst, tg_inst, i;
++	unsigned int i, enc_inst, tg_inst = 0;
+ 
+ 	// Seamless port only support single DP and EDP so far
+ 	if (sink->sink_signal != SIGNAL_TYPE_DISPLAY_PORT &&
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index af85d6cf4427..23313c8808b3 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -1845,7 +1845,7 @@ static int acquire_resource_from_hw_enabled_state(
+ 		struct dc_stream_state *stream)
+ {
+ 	struct dc_link *link = stream->link;
+-	unsigned int inst, tg_inst, i;
++	unsigned int i, inst, tg_inst = 0;
+ 
+ 	/* Check for enabled DIG to identify enabled display */
+ 	if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3848-drm-amd-display-Add-detile-buffer-size-for-DCN20.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3848-drm-amd-display-Add-detile-buffer-size-for-DCN20.patch
new file mode 100644
index 00000000..87d0dbcd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3848-drm-amd-display-Add-detile-buffer-size-for-DCN20.patch
@@ -0,0 +1,67 @@
+From 0a5253fef99c1f70b26f82a8a9c96d5a667f1459 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Tue, 3 Sep 2019 14:10:28 -0400
+Subject: [PATCH 3848/4256] drm/amd/display: Add detile buffer size for DCN20
+
+Detile buffer size affects dcc caps and therefore needs to be
+corrected for each ip.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Chris Park <Chris.Park@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 7 ++++---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h | 1 +
+ 2 files changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+index e0a6e30ac3e1..8b8438566101 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+@@ -186,14 +186,13 @@ static void hubbub2_get_blk256_size(unsigned int *blk256_width, unsigned int *bl
+ }
+ 
+ static void hubbub2_det_request_size(
++		unsigned int detile_buf_size,
+ 		unsigned int height,
+ 		unsigned int width,
+ 		unsigned int bpe,
+ 		bool *req128_horz_wc,
+ 		bool *req128_vert_wc)
+ {
+-	unsigned int detile_buf_size = 164 * 1024;  /* 164KB for DCN1.0 */
+-
+ 	unsigned int blk256_height = 0;
+ 	unsigned int blk256_width = 0;
+ 	unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
+@@ -236,7 +235,8 @@ bool hubbub2_get_dcc_compression_cap(struct hubbub *hubbub,
+ 			&segment_order_horz, &segment_order_vert))
+ 		return false;
+ 
+-	hubbub2_det_request_size(input->surface_size.height,  input->surface_size.width,
++	hubbub2_det_request_size(TO_DCN20_HUBBUB(hubbub)->detile_buf_size,
++			input->surface_size.height,  input->surface_size.width,
+ 			bpe, &req128_horz_wc, &req128_vert_wc);
+ 
+ 	if (!req128_horz_wc && !req128_vert_wc) {
+@@ -619,4 +619,5 @@ void hubbub2_construct(struct dcn20_hubbub *hubbub,
+ 	hubbub->masks = hubbub_mask;
+ 
+ 	hubbub->debug_test_index_pstate = 0xB;
++	hubbub->detile_buf_size = 164 * 1024; /* 164KB for DCN2.0 */
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
+index 626117d3b4e9..501532dd523a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
+@@ -81,6 +81,7 @@ struct dcn20_hubbub {
+ 	unsigned int debug_test_index_pstate;
+ 	struct dcn_watermark_set watermarks;
+ 	struct dcn20_vmid vmid[16];
++	unsigned int detile_buf_size;
+ };
+ 
+ void hubbub2_construct(struct dcn20_hubbub *hubbub,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3849-drm-amd-display-Improve-LFC-behaviour.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3849-drm-amd-display-Improve-LFC-behaviour.patch
new file mode 100644
index 00000000..53bda9f3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3849-drm-amd-display-Improve-LFC-behaviour.patch
@@ -0,0 +1,124 @@
+From f689d334f54b3ed43320221ae014f13b6023f627 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Tue, 3 Sep 2019 18:18:08 -0400
+Subject: [PATCH 3849/4256] drm/amd/display: Improve LFC behaviour
+
+[Why]
+There can be some unsynchronized frames when entering/exiting
+LFC.  This may cause tearing or stuttering at such transitions.
+
+[How]
+Add a enter/exit margin to algorithm to smoothly transition into
+and out of LFC without desynchronizing frames.
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Reza Amini <Reza.Amini@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Acked-by: Sivapiriyan Kumarasamy <Sivapiriyan.Kumarasamy@amd.com>
+---
+ .../amd/display/modules/freesync/freesync.c   | 32 +++++++++++--------
+ .../amd/display/modules/inc/mod_freesync.h    |  1 +
+ 2 files changed, 20 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+index 107d81ea689b..5e5ce9e5eab7 100644
+--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
++++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+@@ -35,8 +35,8 @@
+ #define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65)
+ /* Number of elements in the render times cache array */
+ #define RENDER_TIMES_MAX_COUNT 10
+-/* Threshold to exit BTR (to avoid frequent enter-exits at the lower limit) */
+-#define BTR_EXIT_MARGIN 2000
++/* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */
++#define BTR_MAX_MARGIN 2500
+ /* Threshold to change BTR multiplier (to avoid frequent changes) */
+ #define BTR_DRIFT_MARGIN 2000
+ /*Threshold to exit fixed refresh rate*/
+@@ -248,24 +248,22 @@ static void apply_below_the_range(struct core_freesync *core_freesync,
+ 	unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF;
+ 	unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF;
+ 	unsigned int frames_to_insert = 0;
+-	unsigned int min_frame_duration_in_ns = 0;
+-	unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us;
+ 	unsigned int delta_from_mid_point_delta_in_us;
+-
+-	min_frame_duration_in_ns = ((unsigned int) (div64_u64(
+-		(1000000000ULL * 1000000),
+-		in_out_vrr->max_refresh_in_uhz)));
++	unsigned int max_render_time_in_us =
++			in_out_vrr->max_duration_in_us - in_out_vrr->btr.margin_in_us;
+ 
+ 	/* Program BTR */
+-	if (last_render_time_in_us + BTR_EXIT_MARGIN < max_render_time_in_us) {
++	if ((last_render_time_in_us + in_out_vrr->btr.margin_in_us / 2) < max_render_time_in_us) {
+ 		/* Exit Below the Range */
+ 		if (in_out_vrr->btr.btr_active) {
+ 			in_out_vrr->btr.frame_counter = 0;
+ 			in_out_vrr->btr.btr_active = false;
+ 		}
+-	} else if (last_render_time_in_us > max_render_time_in_us) {
++	} else if (last_render_time_in_us > (max_render_time_in_us + in_out_vrr->btr.margin_in_us / 2)) {
+ 		/* Enter Below the Range */
+-		in_out_vrr->btr.btr_active = true;
++		if (!in_out_vrr->btr.btr_active) {
++			in_out_vrr->btr.btr_active = true;
++		}
+ 	}
+ 
+ 	/* BTR set to "not active" so disengage */
+@@ -321,7 +319,9 @@ static void apply_below_the_range(struct core_freesync *core_freesync,
+ 		/* Choose number of frames to insert based on how close it
+ 		 * can get to the mid point of the variable range.
+ 		 */
+-		if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
++		if ((frame_time_in_us / mid_point_frames_ceil) > in_out_vrr->min_duration_in_us &&
++				(delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2 ||
++						mid_point_frames_floor < 2)) {
+ 			frames_to_insert = mid_point_frames_ceil;
+ 			delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_2 -
+ 					delta_from_mid_point_in_us_1;
+@@ -337,7 +337,7 @@ static void apply_below_the_range(struct core_freesync *core_freesync,
+ 		if (in_out_vrr->btr.frames_to_insert != 0 &&
+ 				delta_from_mid_point_delta_in_us < BTR_DRIFT_MARGIN) {
+ 			if (((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) <
+-					in_out_vrr->max_duration_in_us) &&
++					max_render_time_in_us) &&
+ 				((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) >
+ 					in_out_vrr->min_duration_in_us))
+ 				frames_to_insert = in_out_vrr->btr.frames_to_insert;
+@@ -786,6 +786,11 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
+ 		refresh_range = in_out_vrr->max_refresh_in_uhz -
+ 				in_out_vrr->min_refresh_in_uhz;
+ 
++		in_out_vrr->btr.margin_in_us = in_out_vrr->max_duration_in_us -
++				2 * in_out_vrr->min_duration_in_us;
++		if (in_out_vrr->btr.margin_in_us > BTR_MAX_MARGIN)
++			in_out_vrr->btr.margin_in_us = BTR_MAX_MARGIN;
++
+ 		in_out_vrr->supported = true;
+ 	}
+ 
+@@ -801,6 +806,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
+ 	in_out_vrr->btr.inserted_duration_in_us = 0;
+ 	in_out_vrr->btr.frames_to_insert = 0;
+ 	in_out_vrr->btr.frame_counter = 0;
++
+ 	in_out_vrr->btr.mid_point_in_us =
+ 				(in_out_vrr->min_duration_in_us +
+ 				 in_out_vrr->max_duration_in_us) / 2;
+diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+index dc187844d10b..dbe7835aabcf 100644
+--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+@@ -92,6 +92,7 @@ struct mod_vrr_params_btr {
+ 	uint32_t inserted_duration_in_us;
+ 	uint32_t frames_to_insert;
+ 	uint32_t frame_counter;
++	uint32_t margin_in_us;
+ };
+ 
+ struct mod_vrr_params_fixed_refresh {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3850-drm-amdgpu-gmc10-apply-the-invalidation-from-sdma-wo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3850-drm-amdgpu-gmc10-apply-the-invalidation-from-sdma-wo.patch
new file mode 100644
index 00000000..a809ae47
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3850-drm-amdgpu-gmc10-apply-the-invalidation-from-sdma-wo.patch
@@ -0,0 +1,31 @@
+From b13b863dd7ad65ba729b5f1d3ed0c3cd4eae2bef Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Mon, 23 Sep 2019 21:32:05 +0800
+Subject: [PATCH 3850/4256] drm/amdgpu/gmc10: apply the 'invalidation from
+ sdma' workaround for navi12
+
+when gfxoff is enabled, sdma hangs while entering desktop without this
+workaround
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index ed1c3b883f6a..2ea9278a8368 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -291,7 +291,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
+ 
+ 	if (!adev->mman.buffer_funcs_enabled ||
+ 	    !adev->ib_pool_ready ||
+-	    adev->asic_type > CHIP_NAVI14 ||
++	    !(adev->asic_type >= CHIP_NAVI10 && adev->asic_type <= CHIP_NAVI12) ||
+ 	    adev->in_gpu_reset) {
+ 		gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
+ 		mutex_unlock(&adev->mman.gtt_window_lock);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3851-drm-amdgpu-gfx10-enable-gfxoff-for-navi12.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3851-drm-amdgpu-gfx10-enable-gfxoff-for-navi12.patch
new file mode 100644
index 00000000..ee35fd9c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3851-drm-amdgpu-gfx10-enable-gfxoff-for-navi12.patch
@@ -0,0 +1,33 @@
+From 0556da67e2e51c68e26fe49e8cd258c908de7c92 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Tue, 17 Sep 2019 18:57:37 +0800
+Subject: [PATCH 3851/4256] drm/amdgpu/gfx10: enable gfxoff for navi12
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 65caf404e7d1..ecfda0602456 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -585,7 +585,6 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
+ {
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+-	case CHIP_NAVI12:
+ 		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ 		break;
+ 	default:
+@@ -4194,6 +4193,7 @@ static int gfx_v10_0_set_powergating_state(void *handle,
+ 	bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
++	case CHIP_NAVI12:
+ 	case CHIP_NAVI14:
+ 		if (!enable) {
+ 			amdgpu_gfx_off_ctrl(adev, false);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3852-drm-amdgpu-add-psp-ip-block-for-arct.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3852-drm-amdgpu-add-psp-ip-block-for-arct.patch
new file mode 100644
index 00000000..b9f44fba
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3852-drm-amdgpu-add-psp-ip-block-for-arct.patch
@@ -0,0 +1,31 @@
+From f23f35456937fe03b3cf2c1845050ca8a4431a19 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 18 Sep 2019 04:05:34 +0800
+Subject: [PATCH 3852/4256] drm/amdgpu: add psp ip block for arct
+
+enable psp block for firmware loading and other security
+feature setup.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 7c7e9f550c02..769c568d3552 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -755,6 +755,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ 		amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
++		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
++			amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+ 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+ 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3853-drm-amdgpu-disable-vcn-ip-block-for-front-door-loadi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3853-drm-amdgpu-disable-vcn-ip-block-for-front-door-loadi.patch
new file mode 100644
index 00000000..d84c7273
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3853-drm-amdgpu-disable-vcn-ip-block-for-front-door-loadi.patch
@@ -0,0 +1,30 @@
+From c0a17ca07b319de6f162f2f0c3d65fee48c473b2 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Mon, 23 Sep 2019 12:25:03 +0800
+Subject: [PATCH 3853/4256] drm/amdgpu: disable vcn ip block for front door
+ loading on Arcturus
+
+Change-Id: Ibf137cd57659e70516bcbbe456a00ad77e60647c
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 769c568d3552..dbd790eb5040 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -762,7 +762,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ 		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+-		amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
++		if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT))
++			amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
+ 		break;
+ 	case CHIP_RENOIR:
+ 		amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3854-drm-amdgpu-enable-psp-front-door-loading-by-default-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3854-drm-amdgpu-enable-psp-front-door-loading-by-default-.patch
new file mode 100644
index 00000000..63c1077f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3854-drm-amdgpu-enable-psp-front-door-loading-by-default-.patch
@@ -0,0 +1,37 @@
+From f10fe7c3d94c7c368dc2072549eaffe09407c36e Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Mon, 23 Sep 2019 14:10:55 +0800
+Subject: [PATCH 3854/4256] drm/amdgpu: enable psp front door loading by
+ default on Arcturus
+
+Change-Id: I13a5f590d5a49655965a13eb7ce773d1efffcbd0
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+index 82f6b413718b..fce1f71c1cff 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+@@ -360,6 +360,7 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
+ 	case CHIP_RAVEN:
+ 	case CHIP_VEGA12:
+ 	case CHIP_VEGA20:
++	case CHIP_ARCTURUS:
+ 	case CHIP_RENOIR:
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+@@ -368,8 +369,6 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
+ 			return AMDGPU_FW_LOAD_DIRECT;
+ 		else
+ 			return AMDGPU_FW_LOAD_PSP;
+-	case CHIP_ARCTURUS:
+-		return AMDGPU_FW_LOAD_DIRECT;
+ 
+ 	default:
+ 		DRM_ERROR("Unknown firmware load type\n");
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3855-drm-amdgpu-add-command-id-in-psp-response-failure-me.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3855-drm-amdgpu-add-command-id-in-psp-response-failure-me.patch
new file mode 100644
index 00000000..385587d5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3855-drm-amdgpu-add-command-id-in-psp-response-failure-me.patch
@@ -0,0 +1,32 @@
+From b12457a9f7d193c0e08621f0b90e6c523c654c47 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 23 Sep 2019 20:41:04 +0800
+Subject: [PATCH 3855/4256] drm/amdgpu: add command id in psp response failure
+ message
+
+For better clarification of issue.
+
+Change-Id: I88649fc5dbc7376f3c90ec2114236294ca9189de
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index b954b48f3ddf..7146c29c35f1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -170,7 +170,8 @@ psp_cmd_submit_buf(struct psp_context *psp,
+                 if (ucode)
+                         DRM_WARN("failed to load ucode id (%d) ",
+                                   ucode->ucode_id);
+-		DRM_WARN("psp command failed and response status is (0x%X)\n",
++		DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n",
++				psp->cmd_buf_mem->cmd_id,
+ 				psp->cmd_buf_mem->resp.status & GFX_CMD_STATUS_MASK);
+ 		if (!timeout) {
+ 			mutex_unlock(&psp->mutex);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3856-drm-amdgpu-correct-condition-check-for-psp-rlc-autol.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3856-drm-amdgpu-correct-condition-check-for-psp-rlc-autol.patch
new file mode 100644
index 00000000..7356e717
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3856-drm-amdgpu-correct-condition-check-for-psp-rlc-autol.patch
@@ -0,0 +1,32 @@
+From 468edb0fcd40b82c79cc81116547996eebee3c2b Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Mon, 23 Sep 2019 21:09:38 +0800
+Subject: [PATCH 3856/4256] drm/amdgpu: correct condition check for psp rlc
+ autoload
+
+Otherwise non-autoload case will go into the wrong routine and fail.
+
+Change-Id: Ia91d0fb7179f6944214e892f370d7ef3d6b7d30e
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 7146c29c35f1..a0c5aae2daef 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1083,7 +1083,8 @@ static int psp_np_fw_load(struct psp_context *psp)
+ 			return ret;
+ 
+ 		/* Start rlc autoload after psp recieved all the gfx firmware */
+-		if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
++		if (psp->autoload_supported && ucode->ucode_id ==
++			AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
+ 			ret = psp_rlc_autoload(psp);
+ 			if (ret) {
+ 				DRM_ERROR("Failed to start rlc autoload\n");
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3857-Revert-drm-amd-display-Add-dmub-offload-functions.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3857-Revert-drm-amd-display-Add-dmub-offload-functions.patch
new file mode 100644
index 00000000..d5b11f44
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3857-Revert-drm-amd-display-Add-dmub-offload-functions.patch
@@ -0,0 +1,532 @@
+From bb55adf710ed52497c932dd368965bb3064760f4 Mon Sep 17 00:00:00 2001
+From: Rui Teng <rui.teng@amd.com>
+Date: Wed, 25 Sep 2019 08:38:52 +0800
+Subject: [PATCH 3857/4256] Revert "drm/amd/display: Add dmub offload
+ functions."
+
+This reverts commit 32add621ba8f6021e3a52cabafe88f660d46a0a4.
+
+This patch does not exist on amd-staging-drm-next-20190920, and it conflict
+with new patches.
+
+Signed-off-by: Rui Teng <rui.teng@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c      |  15 +--
+ drivers/gpu/drm/amd/display/dc/dc.h           |  14 ---
+ drivers/gpu/drm/amd/display/dc/dc_helper.c    |  79 ------------
+ drivers/gpu/drm/amd/display/dc/dc_types.h     |   9 --
+ drivers/gpu/drm/amd/display/dc/dmub_cmd.h     | 115 ------------------
+ drivers/gpu/drm/amd/display/dc/dmub_dc.h      |  53 --------
+ .../gpu/drm/amd/display/dc/inc/reg_helper.h   |  27 ----
+ .../display/dmub_fw/src/common/dmub_common.h  |  58 ---------
+ 8 files changed, 2 insertions(+), 368 deletions(-)
+ delete mode 100644 drivers/gpu/drm/amd/display/dc/dmub_cmd.h
+ delete mode 100644 drivers/gpu/drm/amd/display/dc/dmub_dc.h
+ delete mode 100644 drivers/gpu/drm/amd/display/dmub_fw/src/common/dmub_common.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 8a1947e6741a..1ab1df443202 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -31,8 +31,6 @@
+ #include "hw_sequencer.h"
+ #include "dce/dce_hwseq.h"
+ 
+-#include "reg_helper.h"
+-
+ #include "resource.h"
+ 
+ #include "clk_mgr.h"
+@@ -68,12 +66,8 @@
+ 
+ #include "dce/dce_i2c.h"
+ 
+-#define CTX \
+-	dc->ctx
+-
+ #define DC_LOGGER \
+-	CTX->logger
+-
++	dc->ctx->logger
+ 
+ const static char DC_BUILD_ID[] = "production-build";
+ 
+@@ -635,7 +629,6 @@ static bool construct(struct dc *dc,
+ 	dc_ctx->asic_id = init_params->asic_id;
+ 	dc_ctx->dc_sink_id_count = 0;
+ 	dc_ctx->dc_stream_id_count = 0;
+-
+ 	dc->ctx = dc_ctx;
+ 
+ 	/* Create logger */
+@@ -834,11 +827,6 @@ void dc_hardware_init(struct dc *dc)
+ void dc_init_callbacks(struct dc *dc,
+ 		const struct dc_callback_init *init_params)
+ {
+-
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+-	dc->ctx->dmub_if = init_params->dmub_if;
+-	dc->ctx->reg_helper_offload = init_params->dmub_offload;
+-#endif
+ }
+ 
+ void dc_destroy(struct dc **dc)
+@@ -2170,6 +2158,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ 					dc->hwss.update_plane_addr(dc, pipe_ctx);
+ 			}
+ 		}
++
+ 		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index ed596ffd7468..3ecc42987b05 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -29,9 +29,6 @@
+ #include "dc_types.h"
+ #include "grph_object_defs.h"
+ #include "logger_types.h"
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+-#include "dmub_dc.h"
+-#endif
+ #include "gpio_types.h"
+ #include "link_service_types.h"
+ #include "grph_object_ctrl_defs.h"
+@@ -543,10 +540,6 @@ struct dc_init_data {
+ 	struct dc_bios *vbios_override;
+ 	enum dce_environment dce_environment;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+-	struct dmub_offload_funcs *dmub_if;
+-	struct dc_reg_helper_state *dmub_offload;
+-#endif
+ 	struct dc_config flags;
+ 	uint32_t log_mask;
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+@@ -559,14 +552,7 @@ struct dc_init_data {
+ };
+ 
+ struct dc_callback_init {
+-
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+-	struct dmub_offload_funcs *dmub_if;
+-	struct dc_reg_helper_state *dmub_offload;
+-#endif
+-
+ 	uint8_t reserved;
+-
+ };
+ 
+ struct dc *dc_create(const struct dc_init_data *init_params);
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
+index e45278a246d8..2d0acf109360 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
++++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
+@@ -29,25 +29,6 @@
+ #include "dm_services.h"
+ #include <stdarg.h>
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+-#include "dmub_dc.h"
+-
+-static inline void submit_dmub_read_modify_write(
+-	struct dc_reg_helper_state *offload,
+-	const struct dc_context *ctx)
+-{
+-	struct dmub_rb_cmd_read_modify_write *cmd_buf = &offload->cmd_data.read_modify_write;
+-	struct dmub_offload_funcs *dmub_if = ctx->dmub_if;
+-
+-	cmd_buf->header.type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE;
+-	cmd_buf->header.payload_bytes = sizeof(struct read_modify_write_sequence) * offload->reg_seq_count;
+-
+-	dmub_if->queue_dmub_cmd(&dmub_if->dmub_cmd, &cmd_buf->header);
+-
+-	offload->reg_seq_count = 0;
+-}
+-#endif
+-
+ struct dc_reg_value_masks {
+ 	uint32_t value;
+ 	uint32_t mask;
+@@ -131,28 +112,6 @@ uint32_t generic_reg_set_ex(const struct dc_context *ctx,
+ 
+ 	va_end(ap);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+-	if (ctx->reg_helper_offload && ctx->reg_helper_offload->gather_in_progress) {
+-
+-		struct dc_reg_helper_state *offload = ctx->reg_helper_offload;
+-		struct dmub_rb_cmd_read_modify_write *cmd_buf = &offload->cmd_data.read_modify_write;
+-		struct read_modify_write_sequence *seq;
+-
+-		/* flush command if buffer is full */
+-		if (offload->reg_seq_count == DMUB_READ_MODIFY_WRITE_SEQ__MAX)
+-			submit_dmub_read_modify_write(offload, ctx);
+-
+-		/* pack commands */
+-		seq = &cmd_buf->seq[offload->reg_seq_count];
+-
+-		seq->addr = addr;
+-		seq->modify_mask = field_value_mask.mask;
+-		seq->modify_value = field_value_mask.value;
+-		offload->reg_seq_count++;
+-
+-		return reg_val;  /* todo: return void so we can decouple code running in driver from register states */
+-	}
+-#endif
+ 
+ 	/* mmio write directly */
+ 	reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
+@@ -420,41 +379,3 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
+ 
+ 	return reg_val;
+ }
+-
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+-void reg_sequence_start_gather(const struct dc_context *ctx)
+-{
+-	/* if reg sequence is supported and enabled, set flag to
+-	 * indicate we want to have REG_SET, REG_UPDATE macro build
+-	 * reg sequence command buffer rather than MMIO directly.
+-	 */
+-
+-	if (ctx->reg_helper_offload) {
+-		struct dc_reg_helper_state *offload = ctx->reg_helper_offload;
+-
+-		/* caller sequence mismatch.  need to debug caller.  offload will not work!!! */
+-		ASSERT(!offload->gather_in_progress);
+-
+-		offload->gather_in_progress = true;
+-	}
+-}
+-
+-void reg_sequence_start_execute(const struct dc_context *ctx)
+-{
+-	struct dc_reg_helper_state *offload = ctx->reg_helper_offload;
+-
+-	if (offload && offload->gather_in_progress) {
+-
+-		submit_dmub_read_modify_write(offload, ctx);
+-
+-		offload->gather_in_progress = false;
+-
+-		ctx->dmub_if->execute_dmub_queue(&ctx->dmub_if->dmub_cmd);
+-	}
+-}
+-
+-void reg_sequence_wait_done(const struct dc_context *ctx)
+-{
+-	/* callback to DM to poll for last submission done*/
+-}
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
+index ed60bf011af2..e6ae66791943 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
+@@ -38,10 +38,6 @@
+ #include "dal_types.h"
+ #include "grph_object_defs.h"
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+-#include "dmub_dc.h"
+-#endif
+-
+ /* forward declarations */
+ struct dc_plane_state;
+ struct dc_stream_state;
+@@ -109,11 +105,6 @@ struct dc_context {
+ 	uint32_t dc_sink_id_count;
+ 	uint32_t dc_stream_id_count;
+ 	uint64_t fbc_gpu_addr;
+-
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+-	struct dc_reg_helper_state *reg_helper_offload;
+-	struct dmub_offload_funcs *dmub_if;
+-#endif
+ };
+ 
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dc/dmub_cmd.h
+deleted file mode 100644
+index eb9c68657d1d..000000000000
+--- a/drivers/gpu/drm/amd/display/dc/dmub_cmd.h
++++ /dev/null
+@@ -1,115 +0,0 @@
+-/*
+- * Copyright 2018 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included in
+- * all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+- *
+- * Authors: AMD
+- *
+- */
+-
+-#ifndef DMUB_CMD__H
+-#define DMUB_CMD__H
+-
+-
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+-#include "os_types.h"
+-#else
+-#include "dmub_types.h"
+-#endif
+-/*
+- * DMUB command definition
+- */
+-
+-
+-#define DMUB_RB_MAX_ENTRY	16
+-#define DMUB_RB_CMD_SIZE	64
+-#define DMUB_RB_SIZE	(DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
+-
+-#ifdef DMUB_EMULATION
+-
+-#else
+-
+-#endif
+-
+-
+-enum dmub_cmd_type {
+-	DMUB_CMD__NULL,
+-	DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE,
+-	DMUB_CMD__REG_SEQ_BURST_WRITE,
+-};
+-
+-
+-struct dmub_cmd_header {
+-	enum dmub_cmd_type type : 11;
+-	unsigned int payload_bytes : 5;  /* up to 60 bytes */
+-	unsigned int reserved : 16;
+-};
+-
+-struct read_modify_write_sequence {
+-	uint32_t addr;
+-	uint32_t modify_mask;
+-	uint32_t modify_value;
+-};
+-
+-
+-/* read modify write
+- *
+- * 60 payload bytes can hold up to 5 sets of read modify writes,
+- * each take 3 dwords.
+- *
+- * number of sequences = header.payload_bytes / sizeof(struct read_modify_write_sequence)
+- *
+- * modify_mask = 0xffff'ffff means all fields are going to be updated.  in this case
+- * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
+- */
+-#define DMUB_READ_MODIFY_WRITE_SEQ__MAX		5
+-struct dmub_rb_cmd_read_modify_write {
+-	struct dmub_cmd_header header;  // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE
+-	struct read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
+-};
+-
+-
+-/* burst write
+- *
+- * support use case such as writing out LUTs.
+- *
+- * 60 payload bytes can hold up to 14 values to write to given address
+- *
+- * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
+- */
+-struct dmub_rb_cmd_burst_write {
+-	struct dmub_cmd_header header;  // type = DMUB_CMD__REG_SEQ_BURST_WRITE
+-	uint32_t addr;
+-	uint32_t write_values[14];
+-};
+-
+-#define HEAD_BYTES sizeof(struct dmub_cmd_header) / 8
+-
+-struct dmub_rb_cmd_common {
+-	struct dmub_cmd_header header;
+-	uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - HEAD_BYTES];
+-};
+-
+-union dmub_rb_cmd {
+-	struct dmub_rb_cmd_read_modify_write read_modify_write;
+-	struct dmub_rb_cmd_burst_write burst_write;
+-	struct dmub_rb_cmd_common cmd_common;
+-};
+-
+-#endif /* DMUB_CMD__H */
+diff --git a/drivers/gpu/drm/amd/display/dc/dmub_dc.h b/drivers/gpu/drm/amd/display/dc/dmub_dc.h
+deleted file mode 100644
+index a7b8c278ef33..000000000000
+--- a/drivers/gpu/drm/amd/display/dc/dmub_dc.h
++++ /dev/null
+@@ -1,53 +0,0 @@
+-/*
+- * Copyright 2018 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included in
+- * all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+- *
+- * Authors: AMD
+- *
+- */
+-
+-#ifndef DMUB_DC__H
+-#define DMUB_DC__H
+-
+-#include "dmub_cmd.h"
+-
+-
+-struct dmub_dc_cmd {
+-	const void *dm;
+-};
+-
+-
+-struct dmub_offload_funcs {
+-	struct dmub_dc_cmd dmub_cmd;
+-
+-	void (*queue_dmub_cmd)(struct dmub_dc_cmd *dmub_cmd, struct dmub_cmd_header *cmd);
+-	void (*execute_dmub_queue)(struct dmub_dc_cmd *dmub_cmd);
+-	void (*wait_queue_idle)(struct dmub_dc_cmd *dmub_cmd);
+-};
+-
+-struct dc_reg_helper_state {
+-	bool gather_in_progress;
+-
+-	union dmub_rb_cmd cmd_data;
+-	unsigned int reg_seq_count;
+-};
+-
+-
+-#endif /* DMUB_DC__H */
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+index 3ad739568e3b..8503d9cc4763 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+@@ -485,31 +485,4 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
+ 		uint8_t shift1, uint32_t mask1, uint32_t field_value1,
+ 		...);
+ 
+-
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+-/* register offload macros
+- *
+- * instead of MMIO to register directly, in some cases we want
+- * to gather register sequence and execute the register sequence
+- * from another thread so we optimize time required for lengthy ops
+- */
+-
+-/* start gathering register sequence */
+-#define REG_SEQ_START() \
+-	reg_sequence_start_gather(CTX)
+-
+-/* start execution of register sequence gathered since REG_SEQ_START */
+-#define REG_SEQ_SUBMIT() \
+-	reg_sequence_start_execute(CTX)
+-
+-/* wait for the last REG_SEQ_SUBMIT to finish */
+-#define REG_SEQ_WAIT_DONE() \
+-	reg_sequence_wait_done(CTX)
+-
+-void reg_sequence_start_gather(const struct dc_context *ctx);
+-void reg_sequence_start_execute(const struct dc_context *ctx);
+-void reg_sequence_wait_done(const struct dc_context *ctx);
+-
+-#endif
+-
+ #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub_fw/src/common/dmub_common.h b/drivers/gpu/drm/amd/display/dmub_fw/src/common/dmub_common.h
+deleted file mode 100644
+index edecbba394c7..000000000000
+--- a/drivers/gpu/drm/amd/display/dmub_fw/src/common/dmub_common.h
++++ /dev/null
+@@ -1,58 +0,0 @@
+-/*
+- * Copyright 2018 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included in
+- * all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+- *
+- * Authors: AMD
+- *
+- */
+-#ifndef DMUB_COMMON_H_
+-#define DMUB_COMMON_H_
+-
+-#ifdef __cplusplus
+-extern "C" {
+-#endif
+-
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+-#include "os_types.h"
+-struct dmub_dc_cmd;
+-
+-struct dmub {
+-	void *ctx;
+-	void (*reg_write)(struct dmub *dmub, uint32_t offset, uint32_t value);
+-	uint32_t (*reg_read)(struct dmub *dmub, uint32_t offset);
+-	void (*dequeque)();
+-};
+-
+-#define mmRegWrite(offset, value)
+-#define mmRegRead(offset)
+-#endif
+-
+-void process_ring_buffer_command(
+-		struct dmub *dmub,
+-		struct dmub_dc_cmd *dc_cmd);
+-void ring_buffer_command_dequeue(
+-		struct dmub_dc_cmd *dmub_cmd,
+-		union dmub_rb_cmd *cmd);
+-
+-#ifdef __cplusplus
+-}
+-#endif
+-
+-#endif /* DMUB_COMMON_H_ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3858-drm-amdgpu-psp-HDCP-init.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3858-drm-amdgpu-psp-HDCP-init.patch
new file mode 100644
index 00000000..d85d9133
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3858-drm-amdgpu-psp-HDCP-init.patch
@@ -0,0 +1,363 @@
+From 6be93ad7952cf7f0da502252c3937ef9396a8bec Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 19 Jun 2019 14:37:29 -0400
+Subject: [PATCH 3858/4256] drm/amdgpu: psp HDCP init
+
+This patch adds
+-Loading the firmware
+-The functions and definitions for communication with the firmware
+
+v2: Fix formatting
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c   | 189 +++++++++++++++++++++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h   |  17 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h |   3 +
+ drivers/gpu/drm/amd/amdgpu/psp_v10_0.c    |  33 +++-
+ 4 files changed, 240 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index a0c5aae2daef..3301c390b151 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -770,6 +770,181 @@ static int psp_ras_initialize(struct psp_context *psp)
+ }
+ // ras end
+ 
++// HDCP start
++static void psp_prep_hdcp_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
++					  uint64_t hdcp_ta_mc,
++					  uint64_t hdcp_mc_shared,
++					  uint32_t hdcp_ta_size,
++					  uint32_t shared_size)
++{
++	cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
++	cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(hdcp_ta_mc);
++	cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(hdcp_ta_mc);
++	cmd->cmd.cmd_load_ta.app_len = hdcp_ta_size;
++
++	cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
++		lower_32_bits(hdcp_mc_shared);
++	cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
++		upper_32_bits(hdcp_mc_shared);
++	cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
++}
++
++static int psp_hdcp_init_shared_buf(struct psp_context *psp)
++{
++	int ret;
++
++	/*
++	 * Allocate 16k memory aligned to 4k from Frame Buffer (local
++	 * physical) for hdcp ta <-> Driver
++	 */
++	ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE,
++				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
++				      &psp->hdcp_context.hdcp_shared_bo,
++				      &psp->hdcp_context.hdcp_shared_mc_addr,
++				      &psp->hdcp_context.hdcp_shared_buf);
++
++	return ret;
++}
++
++static int psp_hdcp_load(struct psp_context *psp)
++{
++	int ret;
++	struct psp_gfx_cmd_resp *cmd;
++
++	/*
++	 * TODO: bypass the loading in sriov for now
++	 */
++	if (amdgpu_sriov_vf(psp->adev))
++		return 0;
++
++	cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
++	if (!cmd)
++		return -ENOMEM;
++
++	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
++	memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr,
++	       psp->ta_hdcp_ucode_size);
++
++	psp_prep_hdcp_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
++				      psp->hdcp_context.hdcp_shared_mc_addr,
++				      psp->ta_hdcp_ucode_size,
++				      PSP_HDCP_SHARED_MEM_SIZE);
++
++	ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
++
++	if (!ret) {
++		psp->hdcp_context.hdcp_initialized = 1;
++		psp->hdcp_context.session_id = cmd->resp.session_id;
++	}
++
++	kfree(cmd);
++
++	return ret;
++}
++static int psp_hdcp_initialize(struct psp_context *psp)
++{
++	int ret;
++
++	if (!psp->hdcp_context.hdcp_initialized) {
++		ret = psp_hdcp_init_shared_buf(psp);
++		if (ret)
++			return ret;
++	}
++
++	ret = psp_hdcp_load(psp);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++static void psp_prep_hdcp_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
++					    uint32_t hdcp_session_id)
++{
++	cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
++	cmd->cmd.cmd_unload_ta.session_id = hdcp_session_id;
++}
++
++static int psp_hdcp_unload(struct psp_context *psp)
++{
++	int ret;
++	struct psp_gfx_cmd_resp *cmd;
++
++	/*
++	 * TODO: bypass the unloading in sriov for now
++	 */
++	if (amdgpu_sriov_vf(psp->adev))
++		return 0;
++
++	cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
++	if (!cmd)
++		return -ENOMEM;
++
++	psp_prep_hdcp_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id);
++
++	ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
++
++	kfree(cmd);
++
++	return ret;
++}
++
++static void psp_prep_hdcp_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
++					    uint32_t ta_cmd_id,
++					    uint32_t hdcp_session_id)
++{
++	cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
++	cmd->cmd.cmd_invoke_cmd.session_id = hdcp_session_id;
++	cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
++	/* Note: cmd_invoke_cmd.buf is not used for now */
++}
++
++int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
++{
++	int ret;
++	struct psp_gfx_cmd_resp *cmd;
++
++	/*
++	 * TODO: bypass the loading in sriov for now
++	 */
++	if (amdgpu_sriov_vf(psp->adev))
++		return 0;
++
++	cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
++	if (!cmd)
++		return -ENOMEM;
++
++	psp_prep_hdcp_ta_invoke_cmd_buf(cmd, ta_cmd_id,
++					psp->hdcp_context.session_id);
++
++	ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
++
++	kfree(cmd);
++
++	return ret;
++}
++
++static int psp_hdcp_terminate(struct psp_context *psp)
++{
++	int ret;
++
++	if (!psp->hdcp_context.hdcp_initialized)
++		return 0;
++
++	ret = psp_hdcp_unload(psp);
++	if (ret)
++		return ret;
++
++	psp->hdcp_context.hdcp_initialized = 0;
++
++	/* free hdcp shared memory */
++	amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo,
++			      &psp->hdcp_context.hdcp_shared_mc_addr,
++			      &psp->hdcp_context.hdcp_shared_buf);
++
++	return 0;
++}
++// HDCP end
++
+ static int psp_hw_start(struct psp_context *psp)
+ {
+ 	struct amdgpu_device *adev = psp->adev;
+@@ -843,6 +1018,11 @@ static int psp_hw_start(struct psp_context *psp)
+ 		if (ret)
+ 			dev_err(psp->adev->dev,
+ 					"RAS: Failed to initialize RAS\n");
++
++		ret = psp_hdcp_initialize(psp);
++		if (ret)
++			dev_err(psp->adev->dev,
++				"HDCP: Failed to initialize HDCP\n");
+ 	}
+ 
+ 	return 0;
+@@ -1209,8 +1389,10 @@ static int psp_hw_fini(void *handle)
+ 	    psp->xgmi_context.initialized == 1)
+                 psp_xgmi_terminate(psp);
+ 
+-	if (psp->adev->psp.ta_fw)
++	if (psp->adev->psp.ta_fw) {
+ 		psp_ras_terminate(psp);
++		psp_hdcp_terminate(psp);
++	}
+ 
+ 	psp_ring_destroy(psp, PSP_RING_TYPE__KM);
+ 
+@@ -1252,6 +1434,11 @@ static int psp_suspend(void *handle)
+ 			DRM_ERROR("Failed to terminate ras ta\n");
+ 			return ret;
+ 		}
++		ret = psp_hdcp_terminate(psp);
++		if (ret) {
++			DRM_ERROR("Failed to terminate hdcp ta\n");
++			return ret;
++		}
+ 	}
+ 
+ 	ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+index bc0947f6bc8a..6788e1601945 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+@@ -37,6 +37,8 @@
+ #define PSP_RAS_SHARED_MEM_SIZE 0x4000
+ #define PSP_1_MEG		0x100000
+ #define PSP_TMR_SIZE	0x400000
++#define PSP_HDCP_SHARED_MEM_SIZE	0x4000
++#define PSP_SHARED_MEM_SIZE		0x4000
+ 
+ struct psp_context;
+ struct psp_xgmi_node_info;
+@@ -142,6 +144,14 @@ struct psp_ras_context {
+ 	struct amdgpu_ras	*ras;
+ };
+ 
++struct psp_hdcp_context {
++	bool			hdcp_initialized;
++	uint32_t		session_id;
++	struct amdgpu_bo	*hdcp_shared_bo;
++	uint64_t		hdcp_shared_mc_addr;
++	void			*hdcp_shared_buf;
++};
++
+ struct psp_context
+ {
+ 	struct amdgpu_device            *adev;
+@@ -206,8 +216,14 @@ struct psp_context
+ 	uint32_t			ta_ras_ucode_version;
+ 	uint32_t			ta_ras_ucode_size;
+ 	uint8_t				*ta_ras_start_addr;
++
++	uint32_t			ta_hdcp_ucode_version;
++	uint32_t			ta_hdcp_ucode_size;
++	uint8_t				*ta_hdcp_start_addr;
++
+ 	struct psp_xgmi_context		xgmi_context;
+ 	struct psp_ras_context		ras;
++	struct psp_hdcp_context 	hdcp_context;
+ 	struct mutex			mutex;
+ };
+ 
+@@ -279,6 +295,7 @@ int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
+ int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
+ int psp_ras_enable_features(struct psp_context *psp,
+ 		union ta_ras_cmd_input *info, bool enable);
++int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
+ 
+ int psp_rlc_autoload_start(struct psp_context *psp);
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+index b34f00d42049..c2b593ab7495 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+@@ -108,6 +108,9 @@ struct ta_firmware_header_v1_0 {
+ 	uint32_t ta_ras_ucode_version;
+ 	uint32_t ta_ras_offset_bytes;
+ 	uint32_t ta_ras_size_bytes;
++	uint32_t ta_hdcp_ucode_version;
++	uint32_t ta_hdcp_offset_bytes;
++	uint32_t ta_hdcp_size_bytes;
+ };
+ 
+ /* version_major=1, version_minor=0 */
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+index e5fff6b30137..a43d7bafe954 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+@@ -45,7 +45,7 @@ static int psp_v10_0_init_microcode(struct psp_context *psp)
+ 	char fw_name[30];
+ 	int err = 0;
+ 	const struct psp_firmware_header_v1_0 *hdr;
+-
++	const struct ta_firmware_header_v1_0 *ta_hdr;
+ 	DRM_DEBUG("\n");
+ 
+ 	switch (adev->asic_type) {
+@@ -76,7 +76,38 @@ static int psp_v10_0_init_microcode(struct psp_context *psp)
+ 	adev->psp.asd_start_addr = (uint8_t *)hdr +
+ 				le32_to_cpu(hdr->header.ucode_array_offset_bytes);
+ 
++	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
++	err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
++	if (err) {
++		release_firmware(adev->psp.ta_fw);
++		adev->psp.ta_fw = NULL;
++		dev_info(adev->dev,
++			 "psp v10.0: Failed to load firmware \"%s\"\n",
++			 fw_name);
++	} else {
++		err = amdgpu_ucode_validate(adev->psp.ta_fw);
++		if (err)
++			goto out2;
++
++		ta_hdr = (const struct ta_firmware_header_v1_0 *)
++				 adev->psp.ta_fw->data;
++		adev->psp.ta_hdcp_ucode_version =
++			le32_to_cpu(ta_hdr->ta_hdcp_ucode_version);
++		adev->psp.ta_hdcp_ucode_size =
++			le32_to_cpu(ta_hdr->ta_hdcp_size_bytes);
++		adev->psp.ta_hdcp_start_addr =
++			(uint8_t *)ta_hdr +
++			le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
++
++		adev->psp.ta_fw_version =
++			le32_to_cpu(ta_hdr->header.ucode_version);
++	}
++
+ 	return 0;
++
++out2:
++	release_firmware(adev->psp.ta_fw);
++	adev->psp.ta_fw = NULL;
+ out:
+ 	if (err) {
+ 		dev_err(adev->dev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3859-drm-amdgpu-psp-DTM-init.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3859-drm-amdgpu-psp-DTM-init.patch
new file mode 100644
index 00000000..4d77225c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3859-drm-amdgpu-psp-DTM-init.patch
@@ -0,0 +1,299 @@
+From b2a8db021349346e68551a0e08ff0ac3ddfddd61 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 19 Jun 2019 14:40:58 -0400
+Subject: [PATCH 3859/4256] drm/amdgpu: psp DTM init
+
+DTM is the display topology manager. This is needed to communicate with
+psp about the display configurations.
+
+This patch adds
+    -Loading the firmware
+    -The functions and definitions for communication with the firmware
+
+v2: Fix formatting
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c   | 154 ++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h   |  15 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h |   3 +
+ drivers/gpu/drm/amd/amdgpu/psp_v10_0.c    |  11 +-
+ 4 files changed, 181 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 3301c390b151..f09d8cc6e557 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -945,6 +945,149 @@ static int psp_hdcp_terminate(struct psp_context *psp)
+ }
+ // HDCP end
+ 
++// DTM start
++static void psp_prep_dtm_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
++					 uint64_t dtm_ta_mc,
++					 uint64_t dtm_mc_shared,
++					 uint32_t dtm_ta_size,
++					 uint32_t shared_size)
++{
++	cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
++	cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(dtm_ta_mc);
++	cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(dtm_ta_mc);
++	cmd->cmd.cmd_load_ta.app_len = dtm_ta_size;
++
++	cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(dtm_mc_shared);
++	cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(dtm_mc_shared);
++	cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
++}
++
++static int psp_dtm_init_shared_buf(struct psp_context *psp)
++{
++	int ret;
++
++	/*
++	 * Allocate 16k memory aligned to 4k from Frame Buffer (local
++	 * physical) for dtm ta <-> Driver
++	 */
++	ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE,
++				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
++				      &psp->dtm_context.dtm_shared_bo,
++				      &psp->dtm_context.dtm_shared_mc_addr,
++				      &psp->dtm_context.dtm_shared_buf);
++
++	return ret;
++}
++
++static int psp_dtm_load(struct psp_context *psp)
++{
++	int ret;
++	struct psp_gfx_cmd_resp *cmd;
++
++	/*
++	 * TODO: bypass the loading in sriov for now
++	 */
++	if (amdgpu_sriov_vf(psp->adev))
++		return 0;
++
++	cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
++	if (!cmd)
++		return -ENOMEM;
++
++	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
++	memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size);
++
++	psp_prep_dtm_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
++				     psp->dtm_context.dtm_shared_mc_addr,
++				     psp->ta_dtm_ucode_size,
++				     PSP_DTM_SHARED_MEM_SIZE);
++
++	ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
++
++	if (!ret) {
++		psp->dtm_context.dtm_initialized = 1;
++		psp->dtm_context.session_id = cmd->resp.session_id;
++	}
++
++	kfree(cmd);
++
++	return ret;
++}
++
++static int psp_dtm_initialize(struct psp_context *psp)
++{
++	int ret;
++
++	if (!psp->dtm_context.dtm_initialized) {
++		ret = psp_dtm_init_shared_buf(psp);
++		if (ret)
++			return ret;
++	}
++
++	ret = psp_dtm_load(psp);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static void psp_prep_dtm_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
++					   uint32_t ta_cmd_id,
++					   uint32_t dtm_session_id)
++{
++	cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
++	cmd->cmd.cmd_invoke_cmd.session_id = dtm_session_id;
++	cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
++	/* Note: cmd_invoke_cmd.buf is not used for now */
++}
++
++int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
++{
++	int ret;
++	struct psp_gfx_cmd_resp *cmd;
++
++	/*
++	 * TODO: bypass the loading in sriov for now
++	 */
++	if (amdgpu_sriov_vf(psp->adev))
++		return 0;
++
++	cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
++	if (!cmd)
++		return -ENOMEM;
++
++	psp_prep_dtm_ta_invoke_cmd_buf(cmd, ta_cmd_id,
++				       psp->dtm_context.session_id);
++
++	ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
++
++	kfree(cmd);
++
++	return ret;
++}
++
++static int psp_dtm_terminate(struct psp_context *psp)
++{
++	int ret;
++
++	if (!psp->dtm_context.dtm_initialized)
++		return 0;
++
++	ret = psp_hdcp_unload(psp);
++	if (ret)
++		return ret;
++
++	psp->dtm_context.dtm_initialized = 0;
++
++	/* free hdcp shared memory */
++	amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo,
++			      &psp->dtm_context.dtm_shared_mc_addr,
++			      &psp->dtm_context.dtm_shared_buf);
++
++	return 0;
++}
++// DTM end
++
+ static int psp_hw_start(struct psp_context *psp)
+ {
+ 	struct amdgpu_device *adev = psp->adev;
+@@ -1023,6 +1166,11 @@ static int psp_hw_start(struct psp_context *psp)
+ 		if (ret)
+ 			dev_err(psp->adev->dev,
+ 				"HDCP: Failed to initialize HDCP\n");
++
++		ret = psp_dtm_initialize(psp);
++		if (ret)
++			dev_err(psp->adev->dev,
++				"DTM: Failed to initialize DTM\n");
+ 	}
+ 
+ 	return 0;
+@@ -1391,6 +1539,7 @@ static int psp_hw_fini(void *handle)
+ 
+ 	if (psp->adev->psp.ta_fw) {
+ 		psp_ras_terminate(psp);
++		psp_dtm_terminate(psp);
+ 		psp_hdcp_terminate(psp);
+ 	}
+ 
+@@ -1439,6 +1588,11 @@ static int psp_suspend(void *handle)
+ 			DRM_ERROR("Failed to terminate hdcp ta\n");
+ 			return ret;
+ 		}
++		ret = psp_dtm_terminate(psp);
++		if (ret) {
++			DRM_ERROR("Failed to terminate dtm ta\n");
++			return ret;
++		}
+ 	}
+ 
+ 	ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+index 6788e1601945..7dd9ae7dbbe4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+@@ -38,6 +38,7 @@
+ #define PSP_1_MEG		0x100000
+ #define PSP_TMR_SIZE	0x400000
+ #define PSP_HDCP_SHARED_MEM_SIZE	0x4000
++#define PSP_DTM_SHARED_MEM_SIZE	0x4000
+ #define PSP_SHARED_MEM_SIZE		0x4000
+ 
+ struct psp_context;
+@@ -152,6 +153,14 @@ struct psp_hdcp_context {
+ 	void			*hdcp_shared_buf;
+ };
+ 
++struct psp_dtm_context {
++	bool			dtm_initialized;
++	uint32_t		session_id;
++	struct amdgpu_bo	*dtm_shared_bo;
++	uint64_t		dtm_shared_mc_addr;
++	void			*dtm_shared_buf;
++};
++
+ struct psp_context
+ {
+ 	struct amdgpu_device            *adev;
+@@ -221,9 +230,14 @@ struct psp_context
+ 	uint32_t			ta_hdcp_ucode_size;
+ 	uint8_t				*ta_hdcp_start_addr;
+ 
++	uint32_t			ta_dtm_ucode_version;
++	uint32_t			ta_dtm_ucode_size;
++	uint8_t				*ta_dtm_start_addr;
++
+ 	struct psp_xgmi_context		xgmi_context;
+ 	struct psp_ras_context		ras;
+ 	struct psp_hdcp_context 	hdcp_context;
++	struct psp_dtm_context		dtm_context;
+ 	struct mutex			mutex;
+ };
+ 
+@@ -296,6 +310,7 @@ int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
+ int psp_ras_enable_features(struct psp_context *psp,
+ 		union ta_ras_cmd_input *info, bool enable);
+ int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
++int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
+ 
+ int psp_rlc_autoload_start(struct psp_context *psp);
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+index c2b593ab7495..410587b950f3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+@@ -111,6 +111,9 @@ struct ta_firmware_header_v1_0 {
+ 	uint32_t ta_hdcp_ucode_version;
+ 	uint32_t ta_hdcp_offset_bytes;
+ 	uint32_t ta_hdcp_size_bytes;
++	uint32_t ta_dtm_ucode_version;
++	uint32_t ta_dtm_offset_bytes;
++	uint32_t ta_dtm_size_bytes;
+ };
+ 
+ /* version_major=1, version_minor=0 */
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+index a43d7bafe954..6dec5fbc2678 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+@@ -99,8 +99,15 @@ static int psp_v10_0_init_microcode(struct psp_context *psp)
+ 			(uint8_t *)ta_hdr +
+ 			le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
+ 
+-		adev->psp.ta_fw_version =
+-			le32_to_cpu(ta_hdr->header.ucode_version);
++		adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
++
++		adev->psp.ta_dtm_ucode_version =
++			le32_to_cpu(ta_hdr->ta_dtm_ucode_version);
++		adev->psp.ta_dtm_ucode_size =
++			le32_to_cpu(ta_hdr->ta_dtm_size_bytes);
++		adev->psp.ta_dtm_start_addr =
++			(uint8_t *)adev->psp.ta_hdcp_start_addr +
++			le32_to_cpu(ta_hdr->ta_dtm_offset_bytes);
+ 	}
+ 
+ 	return 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3860-drm-amd-display-Add-HDCP-module.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3860-drm-amd-display-Add-HDCP-module.patch
new file mode 100644
index 00000000..64b7c305
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3860-drm-amd-display-Add-HDCP-module.patch
@@ -0,0 +1,3268 @@
+From 534836296531de1667b952c884571e7939299587 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Tue, 6 Aug 2019 17:52:01 -0400
+Subject: [PATCH 3860/4256] drm/amd/display: Add HDCP module
+
+This module manages HDCP for amdgpu driver. The module behaves as a
+state machine which handles the different authentication states of HDCP
+
+The module is divided into 3 major components
++--------+
+| Hdcp.c |
++--------+
+Manages the state machine, sends the events to be executed and communicates
+with the dm
+
++-----------+
+|Execution.c|
++-----------+
+This executes events based on the current state. Also generates
+execution results as transition inputs
+
++------------+
+|Transition.c|
++------------+
+Decides the next state based on the input and makes requests to
+hdcp.c to handle.
+                                +-------------+
+                        ------> | Execution.c | ------
+                        |       +-------------+       |
+                        |                             V
++----+              +--------+                 +--------------+
+| DM |    ----->    | Hdcp.c |  <------------  | Transition.c |
++----+    <-----    +--------+                 +--------------+
+
+v2: Drop unused function definitions
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/Makefile          |   7 +
+ drivers/gpu/drm/amd/display/dc/Makefile       |   4 +
+ drivers/gpu/drm/amd/display/dc/hdcp/Makefile  |  28 +
+ .../gpu/drm/amd/display/dc/hdcp/hdcp_msg.c    | 326 +++++++++++
+ .../gpu/drm/amd/display/include/hdcp_types.h  |  96 ++++
+ .../gpu/drm/amd/display/modules/hdcp/Makefile |  32 ++
+ .../gpu/drm/amd/display/modules/hdcp/hdcp.c   | 426 ++++++++++++++
+ .../gpu/drm/amd/display/modules/hdcp/hdcp.h   | 442 +++++++++++++++
+ .../display/modules/hdcp/hdcp1_execution.c    | 531 ++++++++++++++++++
+ .../display/modules/hdcp/hdcp1_transition.c   | 307 ++++++++++
+ .../drm/amd/display/modules/hdcp/hdcp_ddc.c   | 305 ++++++++++
+ .../drm/amd/display/modules/hdcp/hdcp_log.c   | 163 ++++++
+ .../drm/amd/display/modules/hdcp/hdcp_log.h   | 139 +++++
+ .../drm/amd/display/modules/inc/mod_hdcp.h    | 289 ++++++++++
+ 14 files changed, 3095 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/hdcp/Makefile
+ create mode 100644 drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
+ create mode 100644 drivers/gpu/drm/amd/display/include/hdcp_types.h
+ create mode 100644 drivers/gpu/drm/amd/display/modules/hdcp/Makefile
+ create mode 100644 drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+ create mode 100644 drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+ create mode 100644 drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+ create mode 100644 drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
+ create mode 100644 drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
+ create mode 100644 drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
+ create mode 100644 drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
+ create mode 100644 drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+
+diff --git a/drivers/gpu/drm/amd/display/Makefile b/drivers/gpu/drm/amd/display/Makefile
+index 496cee000f10..36b3d6a5d04d 100644
+--- a/drivers/gpu/drm/amd/display/Makefile
++++ b/drivers/gpu/drm/amd/display/Makefile
+@@ -34,12 +34,19 @@ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/freesync
+ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/color
+ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/info_packet
+ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/power
++ifdef CONFIG_DRM_AMD_DC_HDCP
++subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/hdcp
++endif
+ 
+ #TODO: remove when Timing Sync feature is complete
+ subdir-ccflags-y += -DBUILD_FEATURE_TIMING_SYNC=0
+ 
+ DAL_LIBS = amdgpu_dm dc	modules/freesync modules/color modules/info_packet modules/power
+ 
++ifdef CONFIG_DRM_AMD_DC_HDCP
++DAL_LIBS += modules/hdcp
++endif
++
+ AMD_DAL = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/,$(DAL_LIBS)))
+ 
+ include $(AMD_DAL)
+diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
+index 627982cb15d2..a160512a2f04 100644
+--- a/drivers/gpu/drm/amd/display/dc/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/Makefile
+@@ -48,6 +48,10 @@ DC_LIBS += dce110
+ DC_LIBS += dce100
+ DC_LIBS += dce80
+ 
++ifdef CONFIG_DRM_AMD_DC_HDCP
++DC_LIBS += hdcp
++endif
++
+ AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LIBS)))
+ 
+ include $(AMD_DC)
+diff --git a/drivers/gpu/drm/amd/display/dc/hdcp/Makefile b/drivers/gpu/drm/amd/display/dc/hdcp/Makefile
+new file mode 100644
+index 000000000000..4170b6eb9ec0
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/hdcp/Makefile
+@@ -0,0 +1,28 @@
++# Copyright 2019 Advanced Micro Devices, Inc.
++#
++# Permission is hereby granted, free of charge, to any person obtaining a
++# copy of this software and associated documentation files (the "Software"),
++# to deal in the Software without restriction, including without limitation
++# the rights to use, copy, modify, merge, publish, distribute, sublicense,
++# and/or sell copies of the Software, and to permit persons to whom the
++# Software is furnished to do so, subject to the following conditions:
++#
++# The above copyright notice and this permission notice shall be included in
++# all copies or substantial portions of the Software.
++#
++# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++# OTHER DEALINGS IN THE SOFTWARE.
++#
++# Makefile for the 'hdcp' sub-component of DAL.
++#
++
++HDCP_MSG = hdcp_msg.o
++
++AMD_DAL_HDCP_MSG = $(addprefix $(AMDDALPATH)/dc/hdcp/,$(HDCP_MSG))
++
++AMD_DISPLAY_FILES += $(AMD_DAL_HDCP_MSG)
+diff --git a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
+new file mode 100644
+index 000000000000..cf6ef387e5d2
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
+@@ -0,0 +1,326 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include <linux/slab.h>
++
++#include "dm_services.h"
++#include "dm_helpers.h"
++#include "include/hdcp_types.h"
++#include "include/i2caux_interface.h"
++#include "include/signal_types.h"
++#include "core_types.h"
++#include "dc_link_ddc.h"
++#include "link_hwss.h"
++
++#define DC_LOGGER \
++	link->ctx->logger
++#define HDCP14_KSV_SIZE 5
++#define HDCP14_MAX_KSV_FIFO_SIZE 127*HDCP14_KSV_SIZE
++
++static const bool hdcp_cmd_is_read[] = {
++	[HDCP_MESSAGE_ID_READ_BKSV] = true,
++	[HDCP_MESSAGE_ID_READ_RI_R0] = true,
++	[HDCP_MESSAGE_ID_READ_PJ] = true,
++	[HDCP_MESSAGE_ID_WRITE_AKSV] = false,
++	[HDCP_MESSAGE_ID_WRITE_AINFO] = false,
++	[HDCP_MESSAGE_ID_WRITE_AN] = false,
++	[HDCP_MESSAGE_ID_READ_VH_X] = true,
++	[HDCP_MESSAGE_ID_READ_VH_0] = true,
++	[HDCP_MESSAGE_ID_READ_VH_1] = true,
++	[HDCP_MESSAGE_ID_READ_VH_2] = true,
++	[HDCP_MESSAGE_ID_READ_VH_3] = true,
++	[HDCP_MESSAGE_ID_READ_VH_4] = true,
++	[HDCP_MESSAGE_ID_READ_BCAPS] = true,
++	[HDCP_MESSAGE_ID_READ_BSTATUS] = true,
++	[HDCP_MESSAGE_ID_READ_KSV_FIFO] = true,
++	[HDCP_MESSAGE_ID_READ_BINFO] = true,
++	[HDCP_MESSAGE_ID_HDCP2VERSION] = true,
++	[HDCP_MESSAGE_ID_RX_CAPS] = true,
++	[HDCP_MESSAGE_ID_WRITE_AKE_INIT] = false,
++	[HDCP_MESSAGE_ID_READ_AKE_SEND_CERT] = true,
++	[HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM] = false,
++	[HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM] = false,
++	[HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME] = true,
++	[HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO] = true,
++	[HDCP_MESSAGE_ID_WRITE_LC_INIT] = false,
++	[HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME] = true,
++	[HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS] = false,
++	[HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST] = true,
++	[HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK] = false,
++	[HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE] = false,
++	[HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY] = true,
++	[HDCP_MESSAGE_ID_READ_RXSTATUS] = true,
++	[HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE] = false
++};
++
++static const uint8_t hdcp_i2c_offsets[] = {
++	[HDCP_MESSAGE_ID_READ_BKSV] = 0x0,
++	[HDCP_MESSAGE_ID_READ_RI_R0] = 0x8,
++	[HDCP_MESSAGE_ID_READ_PJ] = 0xA,
++	[HDCP_MESSAGE_ID_WRITE_AKSV] = 0x10,
++	[HDCP_MESSAGE_ID_WRITE_AINFO] = 0x15,
++	[HDCP_MESSAGE_ID_WRITE_AN] = 0x18,
++	[HDCP_MESSAGE_ID_READ_VH_X] = 0x20,
++	[HDCP_MESSAGE_ID_READ_VH_0] = 0x20,
++	[HDCP_MESSAGE_ID_READ_VH_1] = 0x24,
++	[HDCP_MESSAGE_ID_READ_VH_2] = 0x28,
++	[HDCP_MESSAGE_ID_READ_VH_3] = 0x2C,
++	[HDCP_MESSAGE_ID_READ_VH_4] = 0x30,
++	[HDCP_MESSAGE_ID_READ_BCAPS] = 0x40,
++	[HDCP_MESSAGE_ID_READ_BSTATUS] = 0x41,
++	[HDCP_MESSAGE_ID_READ_KSV_FIFO] = 0x43,
++	[HDCP_MESSAGE_ID_READ_BINFO] = 0xFF,
++	[HDCP_MESSAGE_ID_HDCP2VERSION] = 0x50,
++	[HDCP_MESSAGE_ID_WRITE_AKE_INIT] = 0x60,
++	[HDCP_MESSAGE_ID_READ_AKE_SEND_CERT] = 0x80,
++	[HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM] = 0x60,
++	[HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM] = 0x60,
++	[HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME] = 0x80,
++	[HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO] = 0x80,
++	[HDCP_MESSAGE_ID_WRITE_LC_INIT] = 0x60,
++	[HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME] = 0x80,
++	[HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS] = 0x60,
++	[HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST] = 0x80,
++	[HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK] = 0x60,
++	[HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE] = 0x60,
++	[HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY] = 0x80,
++	[HDCP_MESSAGE_ID_READ_RXSTATUS] = 0x70
++};
++
++struct protection_properties {
++	bool supported;
++	bool (*process_transaction)(
++		struct dc_link *link,
++		struct hdcp_protection_message *message_info);
++};
++
++static const struct protection_properties non_supported_protection = {
++	.supported = false
++};
++
++static bool hdmi_14_process_transaction(
++	struct dc_link *link,
++	struct hdcp_protection_message *message_info)
++{
++	uint8_t *buff = NULL;
++	bool result;
++	const uint8_t hdcp_i2c_addr_link_primary = 0x3a; /* 0x74 >> 1*/
++	const uint8_t hdcp_i2c_addr_link_secondary = 0x3b; /* 0x76 >> 1*/
++	struct i2c_command i2c_command;
++	uint8_t offset = hdcp_i2c_offsets[message_info->msg_id];
++	struct i2c_payload i2c_payloads[] = {
++		{ true, 0, 1, &offset },
++		/* actual hdcp payload, will be filled later, zeroed for now*/
++		{ 0 }
++	};
++
++	switch (message_info->link) {
++	case HDCP_LINK_SECONDARY:
++		i2c_payloads[0].address = hdcp_i2c_addr_link_secondary;
++		i2c_payloads[1].address = hdcp_i2c_addr_link_secondary;
++		break;
++	case HDCP_LINK_PRIMARY:
++	default:
++		i2c_payloads[0].address = hdcp_i2c_addr_link_primary;
++		i2c_payloads[1].address = hdcp_i2c_addr_link_primary;
++		break;
++	}
++
++	if (hdcp_cmd_is_read[message_info->msg_id]) {
++		i2c_payloads[1].write = false;
++		i2c_command.number_of_payloads = ARRAY_SIZE(i2c_payloads);
++		i2c_payloads[1].length = message_info->length;
++		i2c_payloads[1].data = message_info->data;
++	} else {
++		i2c_command.number_of_payloads = 1;
++		buff = kzalloc(message_info->length + 1, GFP_KERNEL);
++
++		if (!buff)
++			return false;
++
++		buff[0] = offset;
++		memmove(&buff[1], message_info->data, message_info->length);
++		i2c_payloads[0].length = message_info->length + 1;
++		i2c_payloads[0].data = buff;
++	}
++
++	i2c_command.payloads = i2c_payloads;
++	i2c_command.engine = I2C_COMMAND_ENGINE_HW;//only HW
++	i2c_command.speed = link->ddc->ctx->dc->caps.i2c_speed_in_khz;
++
++	result = dm_helpers_submit_i2c(
++			link->ctx,
++			link,
++			&i2c_command);
++
++	if (buff)
++		kfree(buff);
++
++	return result;
++}
++
++static const struct protection_properties hdmi_14_protection = {
++	.supported = true,
++	.process_transaction = hdmi_14_process_transaction
++};
++
++static const uint32_t hdcp_dpcd_addrs[] = {
++	[HDCP_MESSAGE_ID_READ_BKSV] = 0x68000,
++	[HDCP_MESSAGE_ID_READ_RI_R0] = 0x68005,
++	[HDCP_MESSAGE_ID_READ_PJ] = 0xFFFFFFFF,
++	[HDCP_MESSAGE_ID_WRITE_AKSV] = 0x68007,
++	[HDCP_MESSAGE_ID_WRITE_AINFO] = 0x6803B,
++	[HDCP_MESSAGE_ID_WRITE_AN] = 0x6800c,
++	[HDCP_MESSAGE_ID_READ_VH_X] = 0x68014,
++	[HDCP_MESSAGE_ID_READ_VH_0] = 0x68014,
++	[HDCP_MESSAGE_ID_READ_VH_1] = 0x68018,
++	[HDCP_MESSAGE_ID_READ_VH_2] = 0x6801c,
++	[HDCP_MESSAGE_ID_READ_VH_3] = 0x68020,
++	[HDCP_MESSAGE_ID_READ_VH_4] = 0x68024,
++	[HDCP_MESSAGE_ID_READ_BCAPS] = 0x68028,
++	[HDCP_MESSAGE_ID_READ_BSTATUS] = 0x68029,
++	[HDCP_MESSAGE_ID_READ_KSV_FIFO] = 0x6802c,
++	[HDCP_MESSAGE_ID_READ_BINFO] = 0x6802a,
++	[HDCP_MESSAGE_ID_RX_CAPS] = 0x6921d,
++	[HDCP_MESSAGE_ID_WRITE_AKE_INIT] = 0x69000,
++	[HDCP_MESSAGE_ID_READ_AKE_SEND_CERT] = 0x6900b,
++	[HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM] = 0x69220,
++	[HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM] = 0x692a0,
++	[HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME] = 0x692c0,
++	[HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO] = 0x692e0,
++	[HDCP_MESSAGE_ID_WRITE_LC_INIT] = 0x692f0,
++	[HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME] = 0x692f8,
++	[HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS] = 0x69318,
++	[HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST] = 0x69330,
++	[HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK] = 0x693e0,
++	[HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE] = 0x693f0,
++	[HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY] = 0x69473,
++	[HDCP_MESSAGE_ID_READ_RXSTATUS] = 0x69493,
++	[HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE] = 0x69494
++};
++
++static bool dpcd_access_helper(
++	struct dc_link *link,
++	uint32_t length,
++	uint8_t *data,
++	uint32_t dpcd_addr,
++	bool is_read)
++{
++	enum dc_status status;
++	uint32_t cur_length = 0;
++	uint32_t offset = 0;
++	uint32_t ksv_read_size = 0x6803b - 0x6802c;
++
++	/* Read KSV, need repeatedly handle */
++	if (dpcd_addr == 0x6802c) {
++		if (length % HDCP14_KSV_SIZE) {
++			DC_LOG_ERROR("%s: KsvFifo Size(%d) is not a multiple of HDCP14_KSV_SIZE(%d)\n",
++				__func__,
++				length,
++				HDCP14_KSV_SIZE);
++		}
++		if (length > HDCP14_MAX_KSV_FIFO_SIZE) {
++			DC_LOG_ERROR("%s: KsvFifo Size(%d) is greater than HDCP14_MAX_KSV_FIFO_SIZE(%d)\n",
++				__func__,
++				length,
++				HDCP14_MAX_KSV_FIFO_SIZE);
++		}
++
++		DC_LOG_ERROR("%s: Reading %d Ksv(s) from KsvFifo\n",
++			__func__,
++			length / HDCP14_KSV_SIZE);
++
++		while (length > 0) {
++			if (length > ksv_read_size) {
++				status = core_link_read_dpcd(
++					link,
++					dpcd_addr + offset,
++					data + offset,
++					ksv_read_size);
++
++				data += ksv_read_size;
++				length -= ksv_read_size;
++			} else {
++				status = core_link_read_dpcd(
++					link,
++					dpcd_addr + offset,
++					data + offset,
++					length);
++
++				data += length;
++				length = 0;
++			}
++
++			if (status != DC_OK)
++				return false;
++		}
++	} else {
++		while (length > 0) {
++			if (length > DEFAULT_AUX_MAX_DATA_SIZE)
++				cur_length = DEFAULT_AUX_MAX_DATA_SIZE;
++			else
++				cur_length = length;
++
++			if (is_read) {
++				status = core_link_read_dpcd(
++					link,
++					dpcd_addr + offset,
++					data + offset,
++					cur_length);
++			} else {
++				status = core_link_write_dpcd(
++					link,
++					dpcd_addr + offset,
++					data + offset,
++					cur_length);
++			}
++
++			if (status != DC_OK)
++				return false;
++
++			length -= cur_length;
++			offset += cur_length;
++		}
++	}
++	return true;
++}
++
++static bool dp_11_process_transaction(
++	struct dc_link *link,
++	struct hdcp_protection_message *message_info)
++{
++	return dpcd_access_helper(
++		link,
++		message_info->length,
++		message_info->data,
++		hdcp_dpcd_addrs[message_info->msg_id],
++		hdcp_cmd_is_read[message_info->msg_id]);
++}
++
++static const struct protection_properties dp_11_protection = {
++	.supported = true,
++	.process_transaction = dp_11_process_transaction
++};
++
+diff --git a/drivers/gpu/drm/amd/display/include/hdcp_types.h b/drivers/gpu/drm/amd/display/include/hdcp_types.h
+new file mode 100644
+index 000000000000..f31e6befc8d6
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/include/hdcp_types.h
+@@ -0,0 +1,96 @@
++/*
++* Copyright 2019 Advanced Micro Devices, Inc.
++*
++* Permission is hereby granted, free of charge, to any person obtaining a
++* copy of this software and associated documentation files (the "Software"),
++* to deal in the Software without restriction, including without limitation
++* the rights to use, copy, modify, merge, publish, distribute, sublicense,
++* and/or sell copies of the Software, and to permit persons to whom the
++* Software is furnished to do so, subject to the following conditions:
++*
++* The above copyright notice and this permission notice shall be included in
++* all copies or substantial portions of the Software.
++*
++* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++* OTHER DEALINGS IN THE SOFTWARE.
++*
++* Authors: AMD
++*
++*/
++
++#ifndef __DC_HDCP_TYPES_H__
++#define __DC_HDCP_TYPES_H__
++
++enum hdcp_message_id {
++	HDCP_MESSAGE_ID_INVALID = -1,
++
++	/* HDCP 1.4 */
++
++	HDCP_MESSAGE_ID_READ_BKSV = 0,
++	/* HDMI is called Ri', DP is called R0' */
++	HDCP_MESSAGE_ID_READ_RI_R0,
++	HDCP_MESSAGE_ID_READ_PJ,
++	HDCP_MESSAGE_ID_WRITE_AKSV,
++	HDCP_MESSAGE_ID_WRITE_AINFO,
++	HDCP_MESSAGE_ID_WRITE_AN,
++	HDCP_MESSAGE_ID_READ_VH_X,
++	HDCP_MESSAGE_ID_READ_VH_0,
++	HDCP_MESSAGE_ID_READ_VH_1,
++	HDCP_MESSAGE_ID_READ_VH_2,
++	HDCP_MESSAGE_ID_READ_VH_3,
++	HDCP_MESSAGE_ID_READ_VH_4,
++	HDCP_MESSAGE_ID_READ_BCAPS,
++	HDCP_MESSAGE_ID_READ_BSTATUS,
++	HDCP_MESSAGE_ID_READ_KSV_FIFO,
++	HDCP_MESSAGE_ID_READ_BINFO,
++
++	/* HDCP 2.2 */
++
++	HDCP_MESSAGE_ID_HDCP2VERSION,
++	HDCP_MESSAGE_ID_RX_CAPS,
++	HDCP_MESSAGE_ID_WRITE_AKE_INIT,
++	HDCP_MESSAGE_ID_READ_AKE_SEND_CERT,
++	HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM,
++	HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM,
++	HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME,
++	HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO,
++	HDCP_MESSAGE_ID_WRITE_LC_INIT,
++	HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME,
++	HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS,
++	HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST,
++	HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK,
++	HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE,
++	HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY,
++	HDCP_MESSAGE_ID_READ_RXSTATUS,
++	HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE,
++
++	HDCP_MESSAGE_ID_MAX
++};
++
++enum hdcp_version {
++	HDCP_Unknown = 0,
++	HDCP_VERSION_14,
++	HDCP_VERSION_22,
++};
++
++enum hdcp_link {
++	HDCP_LINK_PRIMARY,
++	HDCP_LINK_SECONDARY
++};
++
++struct hdcp_protection_message {
++	enum hdcp_version version;
++	/* relevant only for DVI */
++	enum hdcp_link link;
++	enum hdcp_message_id msg_id;
++	uint32_t length;
++	uint8_t max_retries;
++	uint8_t *data;
++};
++
++#endif
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/Makefile b/drivers/gpu/drm/amd/display/modules/hdcp/Makefile
+new file mode 100644
+index 000000000000..1c3c6d47973a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/Makefile
+@@ -0,0 +1,32 @@
++#
++# Copyright 2019 Advanced Micro Devices, Inc.
++#
++# Permission is hereby granted, free of charge, to any person obtaining a
++# copy of this software and associated documentation files (the "Software"),
++# to deal in the Software without restriction, including without limitation
++# the rights to use, copy, modify, merge, publish, distribute, sublicense,
++# and/or sell copies of the Software, and to permit persons to whom the
++# Software is furnished to do so, subject to the following conditions:
++#
++# The above copyright notice and this permission notice shall be included in
++# all copies or substantial portions of the Software.
++#
++# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++# OTHER DEALINGS IN THE SOFTWARE.
++#
++#
++# Makefile for the 'hdcp' sub-module of DAL.
++#
++
++HDCP = hdcp_ddc.o hdcp_log.o hdcp_psp.o hdcp.o \
++		hdcp1_execution.o hdcp1_transition.o
++
++AMD_DAL_HDCP = $(addprefix $(AMDDALPATH)/modules/hdcp/,$(HDCP))
++#$(info ************  DAL-HDCP_MAKEFILE ************)
++
++AMD_DISPLAY_FILES += $(AMD_DAL_HDCP)
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+new file mode 100644
+index 000000000000..d7ac445dec6f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+@@ -0,0 +1,426 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "hdcp.h"
++
++static void push_error_status(struct mod_hdcp *hdcp,
++		enum mod_hdcp_status status)
++{
++	struct mod_hdcp_trace *trace = &hdcp->connection.trace;
++
++	if (trace->error_count < MAX_NUM_OF_ERROR_TRACE) {
++		trace->errors[trace->error_count].status = status;
++		trace->errors[trace->error_count].state_id = hdcp->state.id;
++		trace->error_count++;
++		HDCP_ERROR_TRACE(hdcp, status);
++	}
++
++	hdcp->connection.hdcp1_retry_count++;
++}
++
++static uint8_t is_cp_desired_hdcp1(struct mod_hdcp *hdcp)
++{
++	int i, display_enabled = 0;
++
++	/* if all displays on the link are disabled, hdcp is not desired */
++	for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++) {
++		if (hdcp->connection.displays[i].state != MOD_HDCP_DISPLAY_INACTIVE &&
++				!hdcp->connection.displays[i].adjust.disable) {
++			display_enabled = 1;
++			break;
++		}
++	}
++
++	return (hdcp->connection.hdcp1_retry_count < MAX_NUM_OF_ATTEMPTS) &&
++			display_enabled && !hdcp->connection.link.adjust.hdcp1.disable;
++}
++
++static enum mod_hdcp_status execution(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		union mod_hdcp_transition_input *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (is_in_initialized_state(hdcp)) {
++		if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++			event_ctx->unexpected_event = 1;
++			goto out;
++		}
++		/* initialize transition input */
++		memset(input, 0, sizeof(union mod_hdcp_transition_input));
++	} else if (is_in_cp_not_desired_state(hdcp)) {
++		if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++			event_ctx->unexpected_event = 1;
++			goto out;
++		}
++		/* update topology event if hdcp is not desired */
++		status = mod_hdcp_add_display_topology(hdcp);
++	} else if (is_in_hdcp1_states(hdcp)) {
++		status = mod_hdcp_hdcp1_execution(hdcp, event_ctx, &input->hdcp1);
++	} else if (is_in_hdcp1_dp_states(hdcp)) {
++		status = mod_hdcp_hdcp1_dp_execution(hdcp,
++				event_ctx, &input->hdcp1);
++	}
++out:
++	return status;
++}
++
++static enum mod_hdcp_status transition(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		union mod_hdcp_transition_input *input,
++		struct mod_hdcp_output *output)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->unexpected_event)
++		goto out;
++
++	if (is_in_initialized_state(hdcp)) {
++		if (is_dp_hdcp(hdcp))
++			if (is_cp_desired_hdcp1(hdcp)) {
++				callback_in_ms(0, output);
++				set_state_id(hdcp, output, D1_A0_DETERMINE_RX_HDCP_CAPABLE);
++			} else {
++				callback_in_ms(0, output);
++				set_state_id(hdcp, output, HDCP_CP_NOT_DESIRED);
++			}
++		else if (is_hdmi_dvi_sl_hdcp(hdcp))
++			if (is_cp_desired_hdcp1(hdcp)) {
++				callback_in_ms(0, output);
++				set_state_id(hdcp, output, H1_A0_WAIT_FOR_ACTIVE_RX);
++			} else {
++				callback_in_ms(0, output);
++				set_state_id(hdcp, output, HDCP_CP_NOT_DESIRED);
++			}
++		else {
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, HDCP_CP_NOT_DESIRED);
++		}
++	} else if (is_in_cp_not_desired_state(hdcp)) {
++		increment_stay_counter(hdcp);
++	} else if (is_in_hdcp1_states(hdcp)) {
++		status = mod_hdcp_hdcp1_transition(hdcp,
++				event_ctx, &input->hdcp1, output);
++	} else if (is_in_hdcp1_dp_states(hdcp)) {
++		status = mod_hdcp_hdcp1_dp_transition(hdcp,
++				event_ctx, &input->hdcp1, output);
++	} else {
++		status = MOD_HDCP_STATUS_INVALID_STATE;
++	}
++out:
++	return status;
++}
++
++static enum mod_hdcp_status reset_authentication(struct mod_hdcp *hdcp,
++		struct mod_hdcp_output *output)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (is_hdcp1(hdcp)) {
++		if (hdcp->auth.trans_input.hdcp1.create_session != UNKNOWN)
++			mod_hdcp_hdcp1_destroy_session(hdcp);
++
++		if (hdcp->auth.trans_input.hdcp1.add_topology == PASS) {
++			status = mod_hdcp_remove_display_topology(hdcp);
++			if (status != MOD_HDCP_STATUS_SUCCESS) {
++				output->callback_needed = 0;
++				output->watchdog_timer_needed = 0;
++				goto out;
++			}
++		}
++		HDCP_TOP_RESET_AUTH_TRACE(hdcp);
++		memset(&hdcp->auth, 0, sizeof(struct mod_hdcp_authentication));
++		memset(&hdcp->state, 0, sizeof(struct mod_hdcp_state));
++		set_state_id(hdcp, output, HDCP_INITIALIZED);
++	} else if (is_in_cp_not_desired_state(hdcp)) {
++		status = mod_hdcp_remove_display_topology(hdcp);
++		if (status != MOD_HDCP_STATUS_SUCCESS) {
++			output->callback_needed = 0;
++			output->watchdog_timer_needed = 0;
++			goto out;
++		}
++		HDCP_TOP_RESET_AUTH_TRACE(hdcp);
++		memset(&hdcp->auth, 0, sizeof(struct mod_hdcp_authentication));
++		memset(&hdcp->state, 0, sizeof(struct mod_hdcp_state));
++		set_state_id(hdcp, output, HDCP_INITIALIZED);
++	}
++
++out:
++	/* stop callback and watchdog requests from previous authentication*/
++	output->watchdog_timer_stop = 1;
++	output->callback_stop = 1;
++	return status;
++}
++
++static enum mod_hdcp_status reset_connection(struct mod_hdcp *hdcp,
++		struct mod_hdcp_output *output)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	memset(output, 0, sizeof(struct mod_hdcp_output));
++
++	status = reset_authentication(hdcp, output);
++	if (status != MOD_HDCP_STATUS_SUCCESS)
++		goto out;
++
++	if (current_state(hdcp) != HDCP_UNINITIALIZED) {
++		HDCP_TOP_RESET_CONN_TRACE(hdcp);
++		set_state_id(hdcp, output, HDCP_UNINITIALIZED);
++	}
++	memset(&hdcp->connection, 0, sizeof(hdcp->connection));
++out:
++	return status;
++}
++
++/*
++ * Implementation of functions in mod_hdcp.h
++ */
++size_t mod_hdcp_get_memory_size(void)
++{
++	return sizeof(struct mod_hdcp);
++}
++
++enum mod_hdcp_status mod_hdcp_setup(struct mod_hdcp *hdcp,
++		struct mod_hdcp_config *config)
++{
++	struct mod_hdcp_output output;
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	memset(hdcp, 0, sizeof(struct mod_hdcp));
++	memset(&output, 0, sizeof(output));
++	hdcp->config = *config;
++	HDCP_TOP_INTERFACE_TRACE(hdcp);
++	status = reset_connection(hdcp, &output);
++	if (status != MOD_HDCP_STATUS_SUCCESS)
++		push_error_status(hdcp, status);
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_teardown(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++	struct mod_hdcp_output output;
++
++	HDCP_TOP_INTERFACE_TRACE(hdcp);
++	memset(&output, 0,  sizeof(output));
++	status = reset_connection(hdcp, &output);
++	if (status == MOD_HDCP_STATUS_SUCCESS)
++		memset(hdcp, 0, sizeof(struct mod_hdcp));
++	else
++		push_error_status(hdcp, status);
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_add_display(struct mod_hdcp *hdcp,
++		struct mod_hdcp_link *link, struct mod_hdcp_display *display,
++		struct mod_hdcp_output *output)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++	struct mod_hdcp_display *display_container = NULL;
++
++	HDCP_TOP_INTERFACE_TRACE_WITH_INDEX(hdcp, display->index);
++	memset(output, 0, sizeof(struct mod_hdcp_output));
++
++	/* skip inactive display */
++	if (display->state != MOD_HDCP_DISPLAY_ACTIVE) {
++		status = MOD_HDCP_STATUS_SUCCESS;
++		goto out;
++	}
++
++	/* check existing display container */
++	if (get_active_display_at_index(hdcp, display->index)) {
++		status = MOD_HDCP_STATUS_SUCCESS;
++		goto out;
++	}
++
++	/* find an empty display container */
++	display_container = get_empty_display_container(hdcp);
++	if (!display_container) {
++		status = MOD_HDCP_STATUS_DISPLAY_OUT_OF_BOUND;
++		goto out;
++	}
++
++	/* reset existing authentication status */
++	status = reset_authentication(hdcp, output);
++	if (status != MOD_HDCP_STATUS_SUCCESS)
++		goto out;
++
++	/* add display to connection */
++	hdcp->connection.link = *link;
++	*display_container = *display;
++
++	/* reset retry counters */
++	reset_retry_counts(hdcp);
++
++	/* reset error trace */
++	memset(&hdcp->connection.trace, 0, sizeof(hdcp->connection.trace));
++
++	/* request authentication */
++	if (current_state(hdcp) != HDCP_INITIALIZED)
++		set_state_id(hdcp, output, HDCP_INITIALIZED);
++	callback_in_ms(hdcp->connection.link.adjust.auth_delay * 1000, output);
++out:
++	if (status != MOD_HDCP_STATUS_SUCCESS)
++		push_error_status(hdcp, status);
++
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_remove_display(struct mod_hdcp *hdcp,
++		uint8_t index, struct mod_hdcp_output *output)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++	struct mod_hdcp_display *display = NULL;
++
++	HDCP_TOP_INTERFACE_TRACE_WITH_INDEX(hdcp, index);
++	memset(output, 0, sizeof(struct mod_hdcp_output));
++
++	/* find display in connection */
++	display = get_active_display_at_index(hdcp, index);
++	if (!display) {
++		status = MOD_HDCP_STATUS_SUCCESS;
++		goto out;
++	}
++
++	/* stop current authentication */
++	status = reset_authentication(hdcp, output);
++	if (status != MOD_HDCP_STATUS_SUCCESS)
++		goto out;
++
++	/* remove display */
++	display->state = MOD_HDCP_DISPLAY_INACTIVE;
++
++	/* clear retry counters */
++	reset_retry_counts(hdcp);
++
++	/* reset error trace */
++	memset(&hdcp->connection.trace, 0, sizeof(hdcp->connection.trace));
++
++	/* request authentication for remaining displays*/
++	if (get_active_display_count(hdcp) > 0)
++		callback_in_ms(hdcp->connection.link.adjust.auth_delay * 1000,
++				output);
++out:
++	if (status != MOD_HDCP_STATUS_SUCCESS)
++		push_error_status(hdcp, status);
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_query_display(struct mod_hdcp *hdcp,
++		uint8_t index, struct mod_hdcp_display_query *query)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++	struct mod_hdcp_display *display = NULL;
++
++	/* find display in connection */
++	display = get_active_display_at_index(hdcp, index);
++	if (!display) {
++		status = MOD_HDCP_STATUS_DISPLAY_NOT_FOUND;
++		goto out;
++	}
++
++	/* populate query */
++	query->link = &hdcp->connection.link;
++	query->display = display;
++	query->trace = &hdcp->connection.trace;
++	query->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
++
++	mod_hdcp_hdcp1_get_link_encryption_status(hdcp, &query->encryption_status);
++
++out:
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_reset_connection(struct mod_hdcp *hdcp,
++		struct mod_hdcp_output *output)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	HDCP_TOP_INTERFACE_TRACE(hdcp);
++	status = reset_connection(hdcp, output);
++	if (status != MOD_HDCP_STATUS_SUCCESS)
++		push_error_status(hdcp, status);
++
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_process_event(struct mod_hdcp *hdcp,
++		enum mod_hdcp_event event, struct mod_hdcp_output *output)
++{
++	enum mod_hdcp_status exec_status, trans_status, reset_status, status;
++	struct mod_hdcp_event_context event_ctx;
++
++	HDCP_EVENT_TRACE(hdcp, event);
++	memset(output, 0, sizeof(struct mod_hdcp_output));
++	memset(&event_ctx, 0, sizeof(struct mod_hdcp_event_context));
++	event_ctx.event = event;
++
++	/* execute and transition */
++	exec_status = execution(hdcp, &event_ctx, &hdcp->auth.trans_input);
++	trans_status = transition(
++			hdcp, &event_ctx, &hdcp->auth.trans_input, output);
++	if (trans_status == MOD_HDCP_STATUS_SUCCESS) {
++		status = MOD_HDCP_STATUS_SUCCESS;
++	} else if (exec_status == MOD_HDCP_STATUS_SUCCESS) {
++		status = MOD_HDCP_STATUS_INTERNAL_POLICY_FAILURE;
++		push_error_status(hdcp, status);
++	} else {
++		status = exec_status;
++		push_error_status(hdcp, status);
++	}
++
++	/* reset authentication if needed */
++	if (trans_status == MOD_HDCP_STATUS_RESET_NEEDED) {
++		HDCP_FULL_DDC_TRACE(hdcp);
++		reset_status = reset_authentication(hdcp, output);
++		if (reset_status != MOD_HDCP_STATUS_SUCCESS)
++			push_error_status(hdcp, reset_status);
++	}
++	return status;
++}
++
++enum mod_hdcp_operation_mode mod_hdcp_signal_type_to_operation_mode(
++		enum signal_type signal)
++{
++	enum mod_hdcp_operation_mode mode = MOD_HDCP_MODE_OFF;
++
++	switch (signal) {
++	case SIGNAL_TYPE_DVI_SINGLE_LINK:
++	case SIGNAL_TYPE_HDMI_TYPE_A:
++		mode = MOD_HDCP_MODE_DEFAULT;
++		break;
++	case SIGNAL_TYPE_EDP:
++	case SIGNAL_TYPE_DISPLAY_PORT:
++		mode = MOD_HDCP_MODE_DP;
++		break;
++	case SIGNAL_TYPE_DISPLAY_PORT_MST:
++		mode = MOD_HDCP_MODE_DP_MST;
++		break;
++	default:
++		break;
++	};
++
++	return mode;
++}
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+new file mode 100644
+index 000000000000..402bb7999093
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+@@ -0,0 +1,442 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef HDCP_H_
++#define HDCP_H_
++
++#include "mod_hdcp.h"
++#include "hdcp_log.h"
++
++#define BCAPS_READY_MASK				0x20
++#define BCAPS_REPEATER_MASK				0x40
++#define BSTATUS_DEVICE_COUNT_MASK			0X007F
++#define BSTATUS_MAX_DEVS_EXCEEDED_MASK			0x0080
++#define BSTATUS_MAX_CASCADE_EXCEEDED_MASK		0x0800
++#define BCAPS_HDCP_CAPABLE_MASK_DP			0x01
++#define BCAPS_REPEATER_MASK_DP				0x02
++#define BSTATUS_READY_MASK_DP				0x01
++#define BSTATUS_R0_P_AVAILABLE_MASK_DP			0x02
++#define BSTATUS_LINK_INTEGRITY_FAILURE_MASK_DP		0x04
++#define BSTATUS_REAUTH_REQUEST_MASK_DP			0x08
++#define BINFO_DEVICE_COUNT_MASK_DP			0X007F
++#define BINFO_MAX_DEVS_EXCEEDED_MASK_DP			0x0080
++#define BINFO_MAX_CASCADE_EXCEEDED_MASK_DP		0x0800
++
++#define RXSTATUS_MSG_SIZE_MASK				0x03FF
++#define RXSTATUS_READY_MASK				0x0400
++#define RXSTATUS_REAUTH_REQUEST_MASK			0x0800
++#define RXIDLIST_DEVICE_COUNT_LOWER_MASK		0xf0
++#define RXIDLIST_DEVICE_COUNT_UPPER_MASK		0x01
++#define RXCAPS_BYTE0_HDCP_CAPABLE_MASK_DP		0x02
++#define RXSTATUS_READY_MASK_DP				0x0001
++#define RXSTATUS_H_P_AVAILABLE_MASK_DP			0x0002
++#define RXSTATUS_PAIRING_AVAILABLE_MASK_DP		0x0004
++#define RXSTATUS_REAUTH_REQUEST_MASK_DP			0x0008
++#define RXSTATUS_LINK_INTEGRITY_FAILURE_MASK_DP		0x0010
++
++enum mod_hdcp_trans_input_result {
++	UNKNOWN = 0,
++	PASS,
++	FAIL
++};
++
++struct mod_hdcp_transition_input_hdcp1 {
++	uint8_t bksv_read;
++	uint8_t bksv_validation;
++	uint8_t add_topology;
++	uint8_t create_session;
++	uint8_t an_write;
++	uint8_t aksv_write;
++	uint8_t ainfo_write;
++	uint8_t bcaps_read;
++	uint8_t r0p_read;
++	uint8_t rx_validation;
++	uint8_t encryption;
++	uint8_t link_maintenance;
++	uint8_t ready_check;
++	uint8_t bstatus_read;
++	uint8_t max_cascade_check;
++	uint8_t max_devs_check;
++	uint8_t device_count_check;
++	uint8_t ksvlist_read;
++	uint8_t vp_read;
++	uint8_t ksvlist_vp_validation;
++
++	uint8_t hdcp_capable_dp;
++	uint8_t binfo_read_dp;
++	uint8_t r0p_available_dp;
++	uint8_t link_integiry_check;
++	uint8_t reauth_request_check;
++	uint8_t stream_encryption_dp;
++};
++
++union mod_hdcp_transition_input {
++	struct mod_hdcp_transition_input_hdcp1 hdcp1;
++};
++
++struct mod_hdcp_message_hdcp1 {
++	uint8_t		an[8];
++	uint8_t		aksv[5];
++	uint8_t		ainfo;
++	uint8_t		bksv[5];
++	uint16_t	r0p;
++	uint8_t		bcaps;
++	uint16_t	bstatus;
++	uint8_t		ksvlist[635];
++	uint16_t	ksvlist_size;
++	uint8_t		vp[20];
++
++	uint16_t	binfo_dp;
++};
++
++union mod_hdcp_message {
++	struct mod_hdcp_message_hdcp1 hdcp1;
++};
++
++struct mod_hdcp_auth_counters {
++	uint8_t stream_management_retry_count;
++};
++
++/* contains values per connection */
++struct mod_hdcp_connection {
++	struct mod_hdcp_link link;
++	struct mod_hdcp_display displays[MAX_NUM_OF_DISPLAYS];
++	uint8_t is_repeater;
++	uint8_t is_km_stored;
++	struct mod_hdcp_trace trace;
++	uint8_t hdcp1_retry_count;
++};
++
++/* contains values per authentication cycle */
++struct mod_hdcp_authentication {
++	uint32_t id;
++	union mod_hdcp_message msg;
++	union mod_hdcp_transition_input trans_input;
++	struct mod_hdcp_auth_counters count;
++};
++
++/* contains values per state change */
++struct mod_hdcp_state {
++	uint8_t id;
++	uint32_t stay_count;
++};
++
++/* per event in a state */
++struct mod_hdcp_event_context {
++	enum mod_hdcp_event event;
++	uint8_t rx_id_list_ready;
++	uint8_t unexpected_event;
++};
++
++struct mod_hdcp {
++	/* per link */
++	struct mod_hdcp_config config;
++	/* per connection */
++	struct mod_hdcp_connection connection;
++	/* per authentication attempt */
++	struct mod_hdcp_authentication auth;
++	/* per state in an authentication */
++	struct mod_hdcp_state state;
++	/* reserved memory buffer */
++	uint8_t buf[2025];
++};
++
++enum mod_hdcp_initial_state_id {
++	HDCP_UNINITIALIZED = 0x0,
++	HDCP_INITIAL_STATE_START = HDCP_UNINITIALIZED,
++	HDCP_INITIALIZED,
++	HDCP_CP_NOT_DESIRED,
++	HDCP_INITIAL_STATE_END = HDCP_CP_NOT_DESIRED
++};
++
++enum mod_hdcp_hdcp1_state_id {
++	HDCP1_STATE_START = HDCP_INITIAL_STATE_END,
++	H1_A0_WAIT_FOR_ACTIVE_RX,
++	H1_A1_EXCHANGE_KSVS,
++	H1_A2_COMPUTATIONS_A3_VALIDATE_RX_A6_TEST_FOR_REPEATER,
++	H1_A45_AUTHENICATED,
++	H1_A8_WAIT_FOR_READY,
++	H1_A9_READ_KSV_LIST,
++	HDCP1_STATE_END = H1_A9_READ_KSV_LIST
++};
++
++enum mod_hdcp_hdcp1_dp_state_id {
++	HDCP1_DP_STATE_START = HDCP1_STATE_END,
++	D1_A0_DETERMINE_RX_HDCP_CAPABLE,
++	D1_A1_EXCHANGE_KSVS,
++	D1_A23_WAIT_FOR_R0_PRIME,
++	D1_A2_COMPUTATIONS_A3_VALIDATE_RX_A5_TEST_FOR_REPEATER,
++	D1_A4_AUTHENICATED,
++	D1_A6_WAIT_FOR_READY,
++	D1_A7_READ_KSV_LIST,
++	HDCP1_DP_STATE_END = D1_A7_READ_KSV_LIST,
++};
++
++/* hdcp1 executions and transitions */
++typedef enum mod_hdcp_status (*mod_hdcp_action)(struct mod_hdcp *hdcp);
++uint8_t mod_hdcp_execute_and_set(
++		mod_hdcp_action func, uint8_t *flag,
++		enum mod_hdcp_status *status, struct mod_hdcp *hdcp, char *str);
++enum mod_hdcp_status mod_hdcp_hdcp1_execution(struct mod_hdcp *hdcp,
++	struct mod_hdcp_event_context *event_ctx,
++	struct mod_hdcp_transition_input_hdcp1 *input);
++enum mod_hdcp_status mod_hdcp_hdcp1_dp_execution(struct mod_hdcp *hdcp,
++	struct mod_hdcp_event_context *event_ctx,
++	struct mod_hdcp_transition_input_hdcp1 *input);
++enum mod_hdcp_status mod_hdcp_hdcp1_transition(struct mod_hdcp *hdcp,
++	struct mod_hdcp_event_context *event_ctx,
++	struct mod_hdcp_transition_input_hdcp1 *input,
++	struct mod_hdcp_output *output);
++enum mod_hdcp_status mod_hdcp_hdcp1_dp_transition(struct mod_hdcp *hdcp,
++	struct mod_hdcp_event_context *event_ctx,
++	struct mod_hdcp_transition_input_hdcp1 *input,
++	struct mod_hdcp_output *output);
++
++/* log functions */
++void mod_hdcp_dump_binary_message(uint8_t *msg, uint32_t msg_size,
++		uint8_t *buf, uint32_t buf_size);
++/* TODO: add adjustment log */
++
++/* psp functions */
++enum mod_hdcp_status mod_hdcp_add_display_topology(
++		struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_remove_display_topology(
++		struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp1_create_session(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp1_destroy_session(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp1_validate_rx(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp1_enable_encryption(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp1_validate_ksvlist_vp(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp1_enable_dp_stream_encryption(
++	struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp1_link_maintenance(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp1_get_link_encryption_status(struct mod_hdcp *hdcp,
++							       enum mod_hdcp_encryption_status *encryption_status);
++/* ddc functions */
++enum mod_hdcp_status mod_hdcp_read_bksv(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_read_bcaps(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_read_bstatus(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_read_r0p(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_read_ksvlist(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_read_vp(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_read_binfo(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_write_aksv(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_write_ainfo(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_write_an(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_read_rxcaps(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_read_rxstatus(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_read_ake_cert(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_read_h_prime(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_read_pairing_info(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_read_l_prime(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_read_rx_id_list(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_read_stream_ready(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_write_ake_init(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_write_no_stored_km(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_write_stored_km(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_write_lc_init(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_write_eks(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_write_repeater_auth_ack(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_write_stream_manage(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_write_content_type(struct mod_hdcp *hdcp);
++
++/* hdcp version helpers */
++static inline uint8_t is_dp_hdcp(struct mod_hdcp *hdcp)
++{
++	return (hdcp->connection.link.mode == MOD_HDCP_MODE_DP ||
++			hdcp->connection.link.mode == MOD_HDCP_MODE_DP_MST);
++}
++
++static inline uint8_t is_dp_mst_hdcp(struct mod_hdcp *hdcp)
++{
++	return (hdcp->connection.link.mode == MOD_HDCP_MODE_DP_MST);
++}
++
++static inline uint8_t is_hdmi_dvi_sl_hdcp(struct mod_hdcp *hdcp)
++{
++	return (hdcp->connection.link.mode == MOD_HDCP_MODE_DEFAULT);
++}
++
++/* hdcp state helpers */
++static inline uint8_t current_state(struct mod_hdcp *hdcp)
++{
++	return hdcp->state.id;
++}
++
++static inline void set_state_id(struct mod_hdcp *hdcp,
++		struct mod_hdcp_output *output, uint8_t id)
++{
++	memset(&hdcp->state, 0, sizeof(hdcp->state));
++	hdcp->state.id = id;
++	/* callback timer should be reset per state */
++	output->callback_stop = 1;
++	output->watchdog_timer_stop = 1;
++	HDCP_NEXT_STATE_TRACE(hdcp, id, output);
++}
++
++static inline uint8_t is_in_hdcp1_states(struct mod_hdcp *hdcp)
++{
++	return (current_state(hdcp) > HDCP1_STATE_START &&
++			current_state(hdcp) <= HDCP1_STATE_END);
++}
++
++static inline uint8_t is_in_hdcp1_dp_states(struct mod_hdcp *hdcp)
++{
++	return (current_state(hdcp) > HDCP1_DP_STATE_START &&
++			current_state(hdcp) <= HDCP1_DP_STATE_END);
++}
++
++static inline uint8_t is_hdcp1(struct mod_hdcp *hdcp)
++{
++	return (is_in_hdcp1_states(hdcp) || is_in_hdcp1_dp_states(hdcp));
++}
++
++static inline uint8_t is_in_cp_not_desired_state(struct mod_hdcp *hdcp)
++{
++	return current_state(hdcp) == HDCP_CP_NOT_DESIRED;
++}
++
++static inline uint8_t is_in_initialized_state(struct mod_hdcp *hdcp)
++{
++	return current_state(hdcp) == HDCP_INITIALIZED;
++}
++
++/* transition operation helpers */
++static inline void increment_stay_counter(struct mod_hdcp *hdcp)
++{
++	hdcp->state.stay_count++;
++}
++
++static inline void fail_and_restart_in_ms(uint16_t time,
++		enum mod_hdcp_status *status,
++		struct mod_hdcp_output *output)
++{
++	output->callback_needed = 1;
++	output->callback_delay = time;
++	output->watchdog_timer_needed = 0;
++	output->watchdog_timer_delay = 0;
++	*status = MOD_HDCP_STATUS_RESET_NEEDED;
++}
++
++static inline void callback_in_ms(uint16_t time, struct mod_hdcp_output *output)
++{
++	output->callback_needed = 1;
++	output->callback_delay = time;
++}
++
++static inline void set_watchdog_in_ms(struct mod_hdcp *hdcp, uint16_t time,
++		struct mod_hdcp_output *output)
++{
++	output->watchdog_timer_needed = 1;
++	output->watchdog_timer_delay = time;
++}
++
++/* connection topology helpers */
++static inline uint8_t is_display_active(struct mod_hdcp_display *display)
++{
++	return display->state >= MOD_HDCP_DISPLAY_ACTIVE;
++}
++
++static inline uint8_t is_display_added(struct mod_hdcp_display *display)
++{
++	return display->state >= MOD_HDCP_DISPLAY_ACTIVE_AND_ADDED;
++}
++
++static inline uint8_t is_display_encryption_enabled(struct mod_hdcp_display *display)
++{
++	return display->state >= MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;
++}
++
++static inline uint8_t get_active_display_count(struct mod_hdcp *hdcp)
++{
++	uint8_t added_count = 0;
++	uint8_t i;
++
++	for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++)
++		if (is_display_active(&hdcp->connection.displays[i]))
++			added_count++;
++	return added_count;
++}
++
++static inline uint8_t get_added_display_count(struct mod_hdcp *hdcp)
++{
++	uint8_t added_count = 0;
++	uint8_t i;
++
++	for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++)
++		if (is_display_added(&hdcp->connection.displays[i]))
++			added_count++;
++	return added_count;
++}
++
++static inline struct mod_hdcp_display *get_first_added_display(
++		struct mod_hdcp *hdcp)
++{
++	uint8_t i;
++	struct mod_hdcp_display *display = NULL;
++
++	for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++)
++		if (is_display_added(&hdcp->connection.displays[i])) {
++			display = &hdcp->connection.displays[i];
++			break;
++		}
++	return display;
++}
++
++static inline struct mod_hdcp_display *get_active_display_at_index(
++		struct mod_hdcp *hdcp, uint8_t index)
++{
++	uint8_t i;
++	struct mod_hdcp_display *display = NULL;
++
++	for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++)
++		if (hdcp->connection.displays[i].index == index &&
++				is_display_active(&hdcp->connection.displays[i])) {
++			display = &hdcp->connection.displays[i];
++			break;
++		}
++	return display;
++}
++
++static inline struct mod_hdcp_display *get_empty_display_container(
++		struct mod_hdcp *hdcp)
++{
++	uint8_t i;
++	struct mod_hdcp_display *display = NULL;
++
++	for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++)
++		if (!is_display_active(&hdcp->connection.displays[i])) {
++			display = &hdcp->connection.displays[i];
++			break;
++		}
++	return display;
++}
++
++static inline void reset_retry_counts(struct mod_hdcp *hdcp)
++{
++	hdcp->connection.hdcp1_retry_count = 0;
++}
++
++#endif /* HDCP_H_ */
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+new file mode 100644
+index 000000000000..9e7302eac299
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+@@ -0,0 +1,531 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "hdcp.h"
++
++static inline enum mod_hdcp_status validate_bksv(struct mod_hdcp *hdcp)
++{
++	uint64_t n = *(uint64_t *)hdcp->auth.msg.hdcp1.bksv;
++	uint8_t count = 0;
++
++	while (n) {
++		count++;
++		n &= (n - 1);
++	}
++	return (count == 20) ? MOD_HDCP_STATUS_SUCCESS :
++			MOD_HDCP_STATUS_HDCP1_INVALID_BKSV;
++}
++
++static inline enum mod_hdcp_status check_ksv_ready(struct mod_hdcp *hdcp)
++{
++	if (is_dp_hdcp(hdcp))
++		return (hdcp->auth.msg.hdcp1.bstatus & BSTATUS_READY_MASK_DP) ?
++				MOD_HDCP_STATUS_SUCCESS :
++				MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY;
++	return (hdcp->auth.msg.hdcp1.bcaps & BCAPS_READY_MASK) ?
++			MOD_HDCP_STATUS_SUCCESS :
++			MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY;
++}
++
++static inline enum mod_hdcp_status check_hdcp_capable_dp(struct mod_hdcp *hdcp)
++{
++	return (hdcp->auth.msg.hdcp1.bcaps & BCAPS_HDCP_CAPABLE_MASK_DP) ?
++			MOD_HDCP_STATUS_SUCCESS :
++			MOD_HDCP_STATUS_HDCP1_NOT_CAPABLE;
++}
++
++static inline enum mod_hdcp_status check_r0p_available_dp(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++	if (is_dp_hdcp(hdcp)) {
++		status = (hdcp->auth.msg.hdcp1.bstatus &
++				BSTATUS_R0_P_AVAILABLE_MASK_DP) ?
++			MOD_HDCP_STATUS_SUCCESS :
++			MOD_HDCP_STATUS_HDCP1_R0_PRIME_PENDING;
++	} else {
++		status = MOD_HDCP_STATUS_INVALID_OPERATION;
++	}
++	return status;
++}
++
++static inline enum mod_hdcp_status check_link_integrity_dp(
++		struct mod_hdcp *hdcp)
++{
++	return (hdcp->auth.msg.hdcp1.bstatus &
++			BSTATUS_LINK_INTEGRITY_FAILURE_MASK_DP) ?
++			MOD_HDCP_STATUS_HDCP1_LINK_INTEGRITY_FAILURE :
++			MOD_HDCP_STATUS_SUCCESS;
++}
++
++static inline enum mod_hdcp_status check_no_reauthentication_request_dp(
++		struct mod_hdcp *hdcp)
++{
++	return (hdcp->auth.msg.hdcp1.bstatus & BSTATUS_REAUTH_REQUEST_MASK_DP) ?
++			MOD_HDCP_STATUS_HDCP1_REAUTH_REQUEST_ISSUED :
++			MOD_HDCP_STATUS_SUCCESS;
++}
++
++static inline enum mod_hdcp_status check_no_max_cascade(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp))
++		status = (hdcp->auth.msg.hdcp1.binfo_dp &
++				BINFO_MAX_CASCADE_EXCEEDED_MASK_DP) ?
++			MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE :
++			MOD_HDCP_STATUS_SUCCESS;
++	else
++		status = (hdcp->auth.msg.hdcp1.bstatus &
++				BSTATUS_MAX_CASCADE_EXCEEDED_MASK) ?
++				MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE :
++				MOD_HDCP_STATUS_SUCCESS;
++	return status;
++}
++
++static inline enum mod_hdcp_status check_no_max_devs(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp))
++		status = (hdcp->auth.msg.hdcp1.binfo_dp &
++				BINFO_MAX_DEVS_EXCEEDED_MASK_DP) ?
++				MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE :
++				MOD_HDCP_STATUS_SUCCESS;
++	else
++		status = (hdcp->auth.msg.hdcp1.bstatus &
++				BSTATUS_MAX_DEVS_EXCEEDED_MASK) ?
++				MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE :
++				MOD_HDCP_STATUS_SUCCESS;
++	return status;
++}
++
++static inline uint8_t get_device_count(struct mod_hdcp *hdcp)
++{
++	return is_dp_hdcp(hdcp) ?
++			(hdcp->auth.msg.hdcp1.binfo_dp & BINFO_DEVICE_COUNT_MASK_DP) :
++			(hdcp->auth.msg.hdcp1.bstatus & BSTATUS_DEVICE_COUNT_MASK);
++}
++
++static inline enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp)
++{
++	/* device count must be greater than or equal to tracked hdcp displays */
++	return (get_device_count(hdcp) < get_added_display_count(hdcp)) ?
++			MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE :
++			MOD_HDCP_STATUS_SUCCESS;
++}
++
++static enum mod_hdcp_status wait_for_active_rx(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp1 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_bksv,
++			&input->bksv_read, &status,
++			hdcp, "bksv_read"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_bcaps,
++			&input->bcaps_read, &status,
++			hdcp, "bcaps_read"))
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status exchange_ksvs(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp1 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (!mod_hdcp_execute_and_set(mod_hdcp_add_display_topology,
++			&input->add_topology, &status,
++			hdcp, "add_topology"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp1_create_session,
++			&input->create_session, &status,
++			hdcp, "create_session"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_write_an,
++			&input->an_write, &status,
++			hdcp, "an_write"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_write_aksv,
++			&input->aksv_write, &status,
++			hdcp, "aksv_write"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_bksv,
++			&input->bksv_read, &status,
++			hdcp, "bksv_read"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(validate_bksv,
++			&input->bksv_validation, &status,
++			hdcp, "bksv_validation"))
++		goto out;
++	if (hdcp->auth.msg.hdcp1.ainfo) {
++		if (!mod_hdcp_execute_and_set(mod_hdcp_write_ainfo,
++				&input->ainfo_write, &status,
++				hdcp, "ainfo_write"))
++			goto out;
++	}
++out:
++	return status;
++}
++
++static enum mod_hdcp_status computations_validate_rx_test_for_repeater(
++		struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp1 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_r0p,
++			&input->r0p_read, &status,
++			hdcp, "r0p_read"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp1_validate_rx,
++			&input->rx_validation, &status,
++			hdcp, "rx_validation"))
++		goto out;
++	if (hdcp->connection.is_repeater) {
++		if (!hdcp->connection.link.adjust.hdcp1.postpone_encryption)
++			if (!mod_hdcp_execute_and_set(
++					mod_hdcp_hdcp1_enable_encryption,
++					&input->encryption, &status,
++					hdcp, "encryption"))
++				goto out;
++	} else {
++		if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp1_enable_encryption,
++				&input->encryption, &status,
++				hdcp, "encryption"))
++			goto out;
++		if (is_dp_mst_hdcp(hdcp))
++			if (!mod_hdcp_execute_and_set(
++					mod_hdcp_hdcp1_enable_dp_stream_encryption,
++					&input->stream_encryption_dp, &status,
++					hdcp, "stream_encryption_dp"))
++				goto out;
++	}
++out:
++	return status;
++}
++
++static enum mod_hdcp_status authenticated(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp1 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp1_link_maintenance,
++			&input->link_maintenance, &status,
++			hdcp, "link_maintenance"))
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status wait_for_ready(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp1 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++			event_ctx->event != MOD_HDCP_EVENT_CPIRQ &&
++			event_ctx->event != MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (is_dp_hdcp(hdcp)) {
++		if (!mod_hdcp_execute_and_set(mod_hdcp_read_bstatus,
++				&input->bstatus_read, &status,
++				hdcp, "bstatus_read"))
++			goto out;
++		if (!mod_hdcp_execute_and_set(check_link_integrity_dp,
++				&input->link_integiry_check, &status,
++				hdcp, "link_integiry_check"))
++			goto out;
++		if (!mod_hdcp_execute_and_set(check_no_reauthentication_request_dp,
++				&input->reauth_request_check, &status,
++				hdcp, "reauth_request_check"))
++			goto out;
++	} else {
++		if (!mod_hdcp_execute_and_set(mod_hdcp_read_bcaps,
++				&input->bcaps_read, &status,
++				hdcp, "bcaps_read"))
++			goto out;
++	}
++	if (!mod_hdcp_execute_and_set(check_ksv_ready,
++			&input->ready_check, &status,
++			hdcp, "ready_check"))
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status read_ksv_list(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp1 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++	uint8_t device_count;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (is_dp_hdcp(hdcp)) {
++		if (!mod_hdcp_execute_and_set(mod_hdcp_read_binfo,
++				&input->binfo_read_dp, &status,
++				hdcp, "binfo_read_dp"))
++			goto out;
++	} else {
++		if (!mod_hdcp_execute_and_set(mod_hdcp_read_bstatus,
++				&input->bstatus_read, &status,
++				hdcp, "bstatus_read"))
++			goto out;
++	}
++	if (!mod_hdcp_execute_and_set(check_no_max_cascade,
++			&input->max_cascade_check, &status,
++			hdcp, "max_cascade_check"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(check_no_max_devs,
++			&input->max_devs_check, &status,
++			hdcp, "max_devs_check"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(check_device_count,
++			&input->device_count_check, &status,
++			hdcp, "device_count_check"))
++		goto out;
++	device_count = get_device_count(hdcp);
++	hdcp->auth.msg.hdcp1.ksvlist_size = device_count*5;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_ksvlist,
++			&input->ksvlist_read, &status,
++			hdcp, "ksvlist_read"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_vp,
++			&input->vp_read, &status,
++			hdcp, "vp_read"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp1_validate_ksvlist_vp,
++			&input->ksvlist_vp_validation, &status,
++			hdcp, "ksvlist_vp_validation"))
++		goto out;
++	if (input->encryption != PASS)
++		if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp1_enable_encryption,
++				&input->encryption, &status,
++				hdcp, "encryption"))
++			goto out;
++	if (is_dp_mst_hdcp(hdcp))
++		if (!mod_hdcp_execute_and_set(
++				mod_hdcp_hdcp1_enable_dp_stream_encryption,
++				&input->stream_encryption_dp, &status,
++				hdcp, "stream_encryption_dp"))
++			goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status determine_rx_hdcp_capable_dp(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp1 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_bcaps,
++			&input->bcaps_read, &status,
++			hdcp, "bcaps_read"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(check_hdcp_capable_dp,
++			&input->hdcp_capable_dp, &status,
++			hdcp, "hdcp_capable_dp"))
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status wait_for_r0_prime_dp(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp1 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CPIRQ &&
++			event_ctx->event != MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_bstatus,
++			&input->bstatus_read, &status,
++			hdcp, "bstatus_read"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(check_r0p_available_dp,
++			&input->r0p_available_dp, &status,
++			hdcp, "r0p_available_dp"))
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status authenticated_dp(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp1 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CPIRQ) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_bstatus,
++			&input->bstatus_read, &status,
++			hdcp, "bstatus_read"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(check_link_integrity_dp,
++			&input->link_integiry_check, &status,
++			hdcp, "link_integiry_check"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(check_no_reauthentication_request_dp,
++			&input->reauth_request_check, &status,
++			hdcp, "reauth_request_check"))
++		goto out;
++out:
++	return status;
++}
++
++uint8_t mod_hdcp_execute_and_set(
++		mod_hdcp_action func, uint8_t *flag,
++		enum mod_hdcp_status *status, struct mod_hdcp *hdcp, char *str)
++{
++	*status = func(hdcp);
++	if (*status == MOD_HDCP_STATUS_SUCCESS && *flag != PASS) {
++		HDCP_INPUT_PASS_TRACE(hdcp, str);
++		*flag = PASS;
++	} else if (*status != MOD_HDCP_STATUS_SUCCESS && *flag != FAIL) {
++		HDCP_INPUT_FAIL_TRACE(hdcp, str);
++		*flag = FAIL;
++	}
++	return (*status == MOD_HDCP_STATUS_SUCCESS);
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp1_execution(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp1 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	switch (current_state(hdcp)) {
++	case H1_A0_WAIT_FOR_ACTIVE_RX:
++		status = wait_for_active_rx(hdcp, event_ctx, input);
++		break;
++	case H1_A1_EXCHANGE_KSVS:
++		status = exchange_ksvs(hdcp, event_ctx, input);
++		break;
++	case H1_A2_COMPUTATIONS_A3_VALIDATE_RX_A6_TEST_FOR_REPEATER:
++		status = computations_validate_rx_test_for_repeater(hdcp,
++				event_ctx, input);
++		break;
++	case H1_A45_AUTHENICATED:
++		status = authenticated(hdcp, event_ctx, input);
++		break;
++	case H1_A8_WAIT_FOR_READY:
++		status = wait_for_ready(hdcp, event_ctx, input);
++		break;
++	case H1_A9_READ_KSV_LIST:
++		status = read_ksv_list(hdcp, event_ctx, input);
++		break;
++	default:
++		status = MOD_HDCP_STATUS_INVALID_STATE;
++		break;
++	}
++
++	return status;
++}
++
++extern enum mod_hdcp_status mod_hdcp_hdcp1_dp_execution(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp1 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	switch (current_state(hdcp)) {
++	case D1_A0_DETERMINE_RX_HDCP_CAPABLE:
++		status = determine_rx_hdcp_capable_dp(hdcp, event_ctx, input);
++		break;
++	case D1_A1_EXCHANGE_KSVS:
++		status = exchange_ksvs(hdcp, event_ctx, input);
++		break;
++	case D1_A23_WAIT_FOR_R0_PRIME:
++		status = wait_for_r0_prime_dp(hdcp, event_ctx, input);
++		break;
++	case D1_A2_COMPUTATIONS_A3_VALIDATE_RX_A5_TEST_FOR_REPEATER:
++		status = computations_validate_rx_test_for_repeater(
++				hdcp, event_ctx, input);
++		break;
++	case D1_A4_AUTHENICATED:
++		status = authenticated_dp(hdcp, event_ctx, input);
++		break;
++	case D1_A6_WAIT_FOR_READY:
++		status = wait_for_ready(hdcp, event_ctx, input);
++		break;
++	case D1_A7_READ_KSV_LIST:
++		status = read_ksv_list(hdcp, event_ctx, input);
++		break;
++	default:
++		status = MOD_HDCP_STATUS_INVALID_STATE;
++		break;
++	}
++
++	return status;
++}
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
+new file mode 100644
+index 000000000000..1d187809b709
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
+@@ -0,0 +1,307 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "hdcp.h"
++
++enum mod_hdcp_status mod_hdcp_hdcp1_transition(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp1 *input,
++		struct mod_hdcp_output *output)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++	struct mod_hdcp_connection *conn = &hdcp->connection;
++	struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust;
++
++	switch (current_state(hdcp)) {
++	case H1_A0_WAIT_FOR_ACTIVE_RX:
++		if (input->bksv_read != PASS || input->bcaps_read != PASS) {
++			/* 1A-04: repeatedly attempts on port access failure */
++			callback_in_ms(500, output);
++			increment_stay_counter(hdcp);
++			break;
++		}
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, H1_A1_EXCHANGE_KSVS);
++		break;
++	case H1_A1_EXCHANGE_KSVS:
++		if (input->add_topology != PASS ||
++				input->create_session != PASS) {
++			/* out of sync with psp state */
++			adjust->hdcp1.disable = 1;
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (input->an_write != PASS ||
++				input->aksv_write != PASS ||
++				input->bksv_read != PASS ||
++				input->bksv_validation != PASS ||
++				input->ainfo_write == FAIL) {
++			/* 1A-05: consider invalid bksv a failure */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		callback_in_ms(300, output);
++		set_state_id(hdcp, output,
++			H1_A2_COMPUTATIONS_A3_VALIDATE_RX_A6_TEST_FOR_REPEATER);
++		break;
++	case H1_A2_COMPUTATIONS_A3_VALIDATE_RX_A6_TEST_FOR_REPEATER:
++		if (input->bcaps_read != PASS ||
++				input->r0p_read != PASS ||
++				input->rx_validation != PASS ||
++				(!conn->is_repeater && input->encryption != PASS)) {
++			/* 1A-06: consider invalid r0' a failure */
++			/* 1A-08: consider bksv listed in SRM a failure */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		if (conn->is_repeater) {
++			callback_in_ms(0, output);
++			set_watchdog_in_ms(hdcp, 5000, output);
++			set_state_id(hdcp, output, H1_A8_WAIT_FOR_READY);
++		} else {
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, H1_A45_AUTHENICATED);
++			HDCP_FULL_DDC_TRACE(hdcp);
++		}
++		break;
++	case H1_A45_AUTHENICATED:
++		if (input->link_maintenance != PASS) {
++			/* 1A-07: consider invalid ri' a failure */
++			/* 1A-07a: consider read ri' not returned a failure */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		callback_in_ms(500, output);
++		increment_stay_counter(hdcp);
++		break;
++	case H1_A8_WAIT_FOR_READY:
++		if (input->ready_check != PASS) {
++			if (event_ctx->event ==
++					MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++				/* 1B-03: fail hdcp on ksv list READY timeout */
++				/* prevent black screen in next attempt */
++				adjust->hdcp1.postpone_encryption = 1;
++				fail_and_restart_in_ms(0, &status, output);
++			} else {
++				/* continue ksv list READY polling*/
++				callback_in_ms(500, output);
++				increment_stay_counter(hdcp);
++			}
++			break;
++		}
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, H1_A9_READ_KSV_LIST);
++		break;
++	case H1_A9_READ_KSV_LIST:
++		if (input->bstatus_read != PASS ||
++				input->max_cascade_check != PASS ||
++				input->max_devs_check != PASS ||
++				input->device_count_check != PASS ||
++				input->ksvlist_read != PASS ||
++				input->vp_read != PASS ||
++				input->ksvlist_vp_validation != PASS ||
++				input->encryption != PASS) {
++			/* 1B-06: consider MAX_CASCADE_EXCEEDED a failure */
++			/* 1B-05: consider MAX_DEVS_EXCEEDED a failure */
++			/* 1B-04: consider invalid v' a failure */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, H1_A45_AUTHENICATED);
++		HDCP_FULL_DDC_TRACE(hdcp);
++		break;
++	default:
++		status = MOD_HDCP_STATUS_INVALID_STATE;
++		fail_and_restart_in_ms(0, &status, output);
++		break;
++	}
++
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp1_dp_transition(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp1 *input,
++		struct mod_hdcp_output *output)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++	struct mod_hdcp_connection *conn = &hdcp->connection;
++	struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust;
++
++	switch (current_state(hdcp)) {
++	case D1_A0_DETERMINE_RX_HDCP_CAPABLE:
++		if (input->bcaps_read != PASS) {
++			/* 1A-04: no authentication on bcaps read failure */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (input->hdcp_capable_dp != PASS) {
++			adjust->hdcp1.disable = 1;
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, D1_A1_EXCHANGE_KSVS);
++		break;
++	case D1_A1_EXCHANGE_KSVS:
++		if (input->add_topology != PASS ||
++				input->create_session != PASS) {
++			/* out of sync with psp state */
++			adjust->hdcp1.disable = 1;
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (input->an_write != PASS ||
++				input->aksv_write != PASS ||
++				input->bksv_read != PASS ||
++				input->bksv_validation != PASS ||
++				input->ainfo_write == FAIL) {
++			/* 1A-05: consider invalid bksv a failure */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		set_watchdog_in_ms(hdcp, 100, output);
++		set_state_id(hdcp, output, D1_A23_WAIT_FOR_R0_PRIME);
++		break;
++	case D1_A23_WAIT_FOR_R0_PRIME:
++		if (input->bstatus_read != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (input->r0p_available_dp != PASS) {
++			if (event_ctx->event == MOD_HDCP_EVENT_WATCHDOG_TIMEOUT)
++				fail_and_restart_in_ms(0, &status, output);
++			else
++				increment_stay_counter(hdcp);
++			break;
++		}
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, D1_A2_COMPUTATIONS_A3_VALIDATE_RX_A5_TEST_FOR_REPEATER);
++		break;
++	case D1_A2_COMPUTATIONS_A3_VALIDATE_RX_A5_TEST_FOR_REPEATER:
++		if (input->r0p_read != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (input->rx_validation != PASS) {
++			if (hdcp->state.stay_count < 2) {
++				/* allow 2 additional retries */
++				callback_in_ms(0, output);
++				increment_stay_counter(hdcp);
++			} else {
++				/*
++				 * 1A-06: consider invalid r0' a failure
++				 * after 3 attempts.
++				 * 1A-08: consider bksv listed in SRM a failure
++				 */
++				fail_and_restart_in_ms(0, &status, output);
++			}
++			break;
++		} else if ((!conn->is_repeater && input->encryption != PASS) ||
++				(!conn->is_repeater && is_dp_mst_hdcp(hdcp) && input->stream_encryption_dp != PASS)) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		if (conn->is_repeater) {
++			set_watchdog_in_ms(hdcp, 5000, output);
++			set_state_id(hdcp, output, D1_A6_WAIT_FOR_READY);
++		} else {
++			set_state_id(hdcp, output, D1_A4_AUTHENICATED);
++			HDCP_FULL_DDC_TRACE(hdcp);
++		}
++		break;
++	case D1_A4_AUTHENICATED:
++		if (input->link_integiry_check != PASS ||
++				input->reauth_request_check != PASS) {
++			/* 1A-07: restart hdcp on a link integrity failure */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		break;
++	case D1_A6_WAIT_FOR_READY:
++		if (input->link_integiry_check == FAIL ||
++				input->reauth_request_check == FAIL) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (input->ready_check != PASS) {
++			if (event_ctx->event ==
++					MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++				/* 1B-04: fail hdcp on ksv list READY timeout */
++				/* prevent black screen in next attempt */
++				adjust->hdcp1.postpone_encryption = 1;
++				fail_and_restart_in_ms(0, &status, output);
++			} else {
++				increment_stay_counter(hdcp);
++			}
++			break;
++		}
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, D1_A7_READ_KSV_LIST);
++		break;
++	case D1_A7_READ_KSV_LIST:
++		if (input->binfo_read_dp != PASS ||
++				input->max_cascade_check != PASS ||
++				input->max_devs_check != PASS) {
++			/* 1B-06: consider MAX_DEVS_EXCEEDED a failure */
++			/* 1B-07: consider MAX_CASCADE_EXCEEDED a failure */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (input->device_count_check != PASS) {
++			/*
++			 * some slow dongle doesn't update
++			 * device count as soon as downstream is connected.
++			 * give it more time to react.
++			 */
++			adjust->hdcp1.postpone_encryption = 1;
++			fail_and_restart_in_ms(1000, &status, output);
++			break;
++		} else if (input->ksvlist_read != PASS ||
++				input->vp_read != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (input->ksvlist_vp_validation != PASS) {
++			if (hdcp->state.stay_count < 2) {
++				/* allow 2 additional retries */
++				callback_in_ms(0, output);
++				increment_stay_counter(hdcp);
++			} else {
++				/*
++				 * 1B-05: consider invalid v' a failure
++				 * after 3 attempts.
++				 */
++				fail_and_restart_in_ms(0, &status, output);
++			}
++			break;
++		} else if (input->encryption != PASS ||
++				(is_dp_mst_hdcp(hdcp) && input->stream_encryption_dp != PASS)) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		set_state_id(hdcp, output, D1_A4_AUTHENICATED);
++		HDCP_FULL_DDC_TRACE(hdcp);
++		break;
++	default:
++		fail_and_restart_in_ms(0, &status, output);
++		break;
++	}
++
++	return status;
++}
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
+new file mode 100644
+index 000000000000..e7baae059b85
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
+@@ -0,0 +1,305 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "hdcp.h"
++
++#define MIN(a, b) ((a) < (b) ? (a) : (b))
++#define HDCP_I2C_ADDR 0x3a	/* 0x74 >> 1*/
++#define KSV_READ_SIZE 0xf	/* 0x6803b - 0x6802c */
++#define HDCP_MAX_AUX_TRANSACTION_SIZE 16
++
++enum mod_hdcp_ddc_message_id {
++	MOD_HDCP_MESSAGE_ID_INVALID = -1,
++
++	/* HDCP 1.4 */
++
++	MOD_HDCP_MESSAGE_ID_READ_BKSV = 0,
++	MOD_HDCP_MESSAGE_ID_READ_RI_R0,
++	MOD_HDCP_MESSAGE_ID_WRITE_AKSV,
++	MOD_HDCP_MESSAGE_ID_WRITE_AINFO,
++	MOD_HDCP_MESSAGE_ID_WRITE_AN,
++	MOD_HDCP_MESSAGE_ID_READ_VH_X,
++	MOD_HDCP_MESSAGE_ID_READ_VH_0,
++	MOD_HDCP_MESSAGE_ID_READ_VH_1,
++	MOD_HDCP_MESSAGE_ID_READ_VH_2,
++	MOD_HDCP_MESSAGE_ID_READ_VH_3,
++	MOD_HDCP_MESSAGE_ID_READ_VH_4,
++	MOD_HDCP_MESSAGE_ID_READ_BCAPS,
++	MOD_HDCP_MESSAGE_ID_READ_BSTATUS,
++	MOD_HDCP_MESSAGE_ID_READ_KSV_FIFO,
++	MOD_HDCP_MESSAGE_ID_READ_BINFO,
++
++	MOD_HDCP_MESSAGE_ID_MAX
++};
++
++static const uint8_t hdcp_i2c_offsets[] = {
++	[MOD_HDCP_MESSAGE_ID_READ_BKSV] = 0x0,
++	[MOD_HDCP_MESSAGE_ID_READ_RI_R0] = 0x8,
++	[MOD_HDCP_MESSAGE_ID_WRITE_AKSV] = 0x10,
++	[MOD_HDCP_MESSAGE_ID_WRITE_AINFO] = 0x15,
++	[MOD_HDCP_MESSAGE_ID_WRITE_AN] = 0x18,
++	[MOD_HDCP_MESSAGE_ID_READ_VH_X] = 0x20,
++	[MOD_HDCP_MESSAGE_ID_READ_VH_0] = 0x20,
++	[MOD_HDCP_MESSAGE_ID_READ_VH_1] = 0x24,
++	[MOD_HDCP_MESSAGE_ID_READ_VH_2] = 0x28,
++	[MOD_HDCP_MESSAGE_ID_READ_VH_3] = 0x2C,
++	[MOD_HDCP_MESSAGE_ID_READ_VH_4] = 0x30,
++	[MOD_HDCP_MESSAGE_ID_READ_BCAPS] = 0x40,
++	[MOD_HDCP_MESSAGE_ID_READ_BSTATUS] = 0x41,
++	[MOD_HDCP_MESSAGE_ID_READ_KSV_FIFO] = 0x43,
++	[MOD_HDCP_MESSAGE_ID_READ_BINFO] = 0xFF,
++};
++
++static const uint32_t hdcp_dpcd_addrs[] = {
++	[MOD_HDCP_MESSAGE_ID_READ_BKSV] = 0x68000,
++	[MOD_HDCP_MESSAGE_ID_READ_RI_R0] = 0x68005,
++	[MOD_HDCP_MESSAGE_ID_WRITE_AKSV] = 0x68007,
++	[MOD_HDCP_MESSAGE_ID_WRITE_AINFO] = 0x6803B,
++	[MOD_HDCP_MESSAGE_ID_WRITE_AN] = 0x6800c,
++	[MOD_HDCP_MESSAGE_ID_READ_VH_X] = 0x68014,
++	[MOD_HDCP_MESSAGE_ID_READ_VH_0] = 0x68014,
++	[MOD_HDCP_MESSAGE_ID_READ_VH_1] = 0x68018,
++	[MOD_HDCP_MESSAGE_ID_READ_VH_2] = 0x6801c,
++	[MOD_HDCP_MESSAGE_ID_READ_VH_3] = 0x68020,
++	[MOD_HDCP_MESSAGE_ID_READ_VH_4] = 0x68024,
++	[MOD_HDCP_MESSAGE_ID_READ_BCAPS] = 0x68028,
++	[MOD_HDCP_MESSAGE_ID_READ_BSTATUS] = 0x68029,
++	[MOD_HDCP_MESSAGE_ID_READ_KSV_FIFO] = 0x6802c,
++	[MOD_HDCP_MESSAGE_ID_READ_BINFO] = 0x6802a,
++};
++
++static enum mod_hdcp_status read(struct mod_hdcp *hdcp,
++		enum mod_hdcp_ddc_message_id msg_id,
++		uint8_t *buf,
++		uint32_t buf_len)
++{
++	bool success = true;
++	uint32_t cur_size = 0;
++	uint32_t data_offset = 0;
++
++	if (is_dp_hdcp(hdcp)) {
++		while (buf_len > 0) {
++			cur_size = MIN(buf_len, HDCP_MAX_AUX_TRANSACTION_SIZE);
++			success = hdcp->config.ddc.funcs.read_dpcd(hdcp->config.ddc.handle,
++					hdcp_dpcd_addrs[msg_id] + data_offset,
++					buf + data_offset,
++					cur_size);
++
++			if (!success)
++				break;
++
++			buf_len -= cur_size;
++			data_offset += cur_size;
++		}
++	} else {
++		success = hdcp->config.ddc.funcs.read_i2c(
++				hdcp->config.ddc.handle,
++				HDCP_I2C_ADDR,
++				hdcp_i2c_offsets[msg_id],
++				buf,
++				(uint32_t)buf_len);
++	}
++
++	return success ? MOD_HDCP_STATUS_SUCCESS : MOD_HDCP_STATUS_DDC_FAILURE;
++}
++
++static enum mod_hdcp_status read_repeatedly(struct mod_hdcp *hdcp,
++		enum mod_hdcp_ddc_message_id msg_id,
++		uint8_t *buf,
++		uint32_t buf_len,
++		uint8_t read_size)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_DDC_FAILURE;
++	uint32_t cur_size = 0;
++	uint32_t data_offset = 0;
++
++	while (buf_len > 0) {
++		cur_size = MIN(buf_len, read_size);
++		status = read(hdcp, msg_id, buf + data_offset, cur_size);
++
++		if (status != MOD_HDCP_STATUS_SUCCESS)
++			break;
++
++		buf_len -= cur_size;
++		data_offset += cur_size;
++	}
++
++	return status;
++}
++
++static enum mod_hdcp_status write(struct mod_hdcp *hdcp,
++		enum mod_hdcp_ddc_message_id msg_id,
++		uint8_t *buf,
++		uint32_t buf_len)
++{
++	bool success = true;
++	uint32_t cur_size = 0;
++	uint32_t data_offset = 0;
++
++	if (is_dp_hdcp(hdcp)) {
++		while (buf_len > 0) {
++			cur_size = MIN(buf_len, HDCP_MAX_AUX_TRANSACTION_SIZE);
++			success = hdcp->config.ddc.funcs.write_dpcd(
++					hdcp->config.ddc.handle,
++					hdcp_dpcd_addrs[msg_id] + data_offset,
++					buf + data_offset,
++					cur_size);
++
++			if (!success)
++				break;
++
++			buf_len -= cur_size;
++			data_offset += cur_size;
++		}
++	} else {
++		hdcp->buf[0] = hdcp_i2c_offsets[msg_id];
++		memmove(&hdcp->buf[1], buf, buf_len);
++		success = hdcp->config.ddc.funcs.write_i2c(
++				hdcp->config.ddc.handle,
++				HDCP_I2C_ADDR,
++				hdcp->buf,
++				(uint32_t)(buf_len+1));
++	}
++
++	return success ? MOD_HDCP_STATUS_SUCCESS : MOD_HDCP_STATUS_DDC_FAILURE;
++}
++
++enum mod_hdcp_status mod_hdcp_read_bksv(struct mod_hdcp *hdcp)
++{
++	return read(hdcp, MOD_HDCP_MESSAGE_ID_READ_BKSV,
++			hdcp->auth.msg.hdcp1.bksv,
++			sizeof(hdcp->auth.msg.hdcp1.bksv));
++}
++
++enum mod_hdcp_status mod_hdcp_read_bcaps(struct mod_hdcp *hdcp)
++{
++	return read(hdcp, MOD_HDCP_MESSAGE_ID_READ_BCAPS,
++			&hdcp->auth.msg.hdcp1.bcaps,
++			sizeof(hdcp->auth.msg.hdcp1.bcaps));
++}
++
++enum mod_hdcp_status mod_hdcp_read_bstatus(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp))
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_BSTATUS,
++					(uint8_t *)&hdcp->auth.msg.hdcp1.bstatus,
++					1);
++	else
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_BSTATUS,
++				(uint8_t *)&hdcp->auth.msg.hdcp1.bstatus,
++				sizeof(hdcp->auth.msg.hdcp1.bstatus));
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_r0p(struct mod_hdcp *hdcp)
++{
++	return read(hdcp, MOD_HDCP_MESSAGE_ID_READ_RI_R0,
++			(uint8_t *)&hdcp->auth.msg.hdcp1.r0p,
++			sizeof(hdcp->auth.msg.hdcp1.r0p));
++}
++
++/* special case, reading repeatedly at the same address, don't use read() */
++enum mod_hdcp_status mod_hdcp_read_ksvlist(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp))
++		status = read_repeatedly(hdcp, MOD_HDCP_MESSAGE_ID_READ_KSV_FIFO,
++				hdcp->auth.msg.hdcp1.ksvlist,
++				hdcp->auth.msg.hdcp1.ksvlist_size,
++				KSV_READ_SIZE);
++	else
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_KSV_FIFO,
++				(uint8_t *)&hdcp->auth.msg.hdcp1.ksvlist,
++				hdcp->auth.msg.hdcp1.ksvlist_size);
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_vp(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_VH_0,
++			&hdcp->auth.msg.hdcp1.vp[0], 4);
++	if (status != MOD_HDCP_STATUS_SUCCESS)
++		goto out;
++
++	status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_VH_1,
++			&hdcp->auth.msg.hdcp1.vp[4], 4);
++	if (status != MOD_HDCP_STATUS_SUCCESS)
++		goto out;
++
++	status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_VH_2,
++			&hdcp->auth.msg.hdcp1.vp[8], 4);
++	if (status != MOD_HDCP_STATUS_SUCCESS)
++		goto out;
++
++	status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_VH_3,
++			&hdcp->auth.msg.hdcp1.vp[12], 4);
++	if (status != MOD_HDCP_STATUS_SUCCESS)
++		goto out;
++
++	status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_VH_4,
++			&hdcp->auth.msg.hdcp1.vp[16], 4);
++out:
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_binfo(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp))
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_BINFO,
++				(uint8_t *)&hdcp->auth.msg.hdcp1.binfo_dp,
++				sizeof(hdcp->auth.msg.hdcp1.binfo_dp));
++	else
++		status = MOD_HDCP_STATUS_INVALID_OPERATION;
++
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_write_aksv(struct mod_hdcp *hdcp)
++{
++	return write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_AKSV,
++			hdcp->auth.msg.hdcp1.aksv,
++			sizeof(hdcp->auth.msg.hdcp1.aksv));
++}
++
++enum mod_hdcp_status mod_hdcp_write_ainfo(struct mod_hdcp *hdcp)
++{
++	return write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_AINFO,
++			&hdcp->auth.msg.hdcp1.ainfo,
++			sizeof(hdcp->auth.msg.hdcp1.ainfo));
++}
++
++enum mod_hdcp_status mod_hdcp_write_an(struct mod_hdcp *hdcp)
++{
++	return write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_AN,
++			hdcp->auth.msg.hdcp1.an,
++			sizeof(hdcp->auth.msg.hdcp1.an));
++}
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
+new file mode 100644
+index 000000000000..d868f556d180
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
+@@ -0,0 +1,163 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++
++#include "hdcp.h"
++
++void mod_hdcp_dump_binary_message(uint8_t *msg, uint32_t msg_size,
++		uint8_t *buf, uint32_t buf_size)
++{
++	const uint8_t bytes_per_line = 16,
++			byte_size = 3,
++			newline_size = 1,
++			terminator_size = 1;
++	uint32_t line_count = msg_size / bytes_per_line,
++			trailing_bytes = msg_size % bytes_per_line;
++	uint32_t target_size = (byte_size * bytes_per_line + newline_size) * line_count +
++			byte_size * trailing_bytes + newline_size + terminator_size;
++	uint32_t buf_pos = 0;
++	uint32_t i = 0;
++
++	if (buf_size >= target_size) {
++		for (i = 0; i < msg_size; i++) {
++			if (i % bytes_per_line == 0)
++				buf[buf_pos++] = '\n';
++			sprintf(&buf[buf_pos], "%02X ", msg[i]);
++			buf_pos += byte_size;
++		}
++		buf[buf_pos++] = '\0';
++	}
++}
++
++char *mod_hdcp_status_to_str(int32_t status)
++{
++	switch (status) {
++	case MOD_HDCP_STATUS_SUCCESS:
++		return "MOD_HDCP_STATUS_SUCCESS";
++	case MOD_HDCP_STATUS_FAILURE:
++		return "MOD_HDCP_STATUS_FAILURE";
++	case MOD_HDCP_STATUS_RESET_NEEDED:
++		return "MOD_HDCP_STATUS_RESET_NEEDED";
++	case MOD_HDCP_STATUS_DISPLAY_OUT_OF_BOUND:
++		return "MOD_HDCP_STATUS_DISPLAY_OUT_OF_BOUND";
++	case MOD_HDCP_STATUS_DISPLAY_NOT_FOUND:
++		return "MOD_HDCP_STATUS_DISPLAY_NOT_FOUND";
++	case MOD_HDCP_STATUS_INVALID_STATE:
++		return "MOD_HDCP_STATUS_INVALID_STATE";
++	case MOD_HDCP_STATUS_NOT_IMPLEMENTED:
++		return "MOD_HDCP_STATUS_NOT_IMPLEMENTED";
++	case MOD_HDCP_STATUS_INTERNAL_POLICY_FAILURE:
++		return "MOD_HDCP_STATUS_INTERNAL_POLICY_FAILURE";
++	case MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE:
++		return "MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE";
++	case MOD_HDCP_STATUS_CREATE_PSP_SERVICE_FAILURE:
++		return "MOD_HDCP_STATUS_CREATE_PSP_SERVICE_FAILURE";
++	case MOD_HDCP_STATUS_DESTROY_PSP_SERVICE_FAILURE:
++		return "MOD_HDCP_STATUS_DESTROY_PSP_SERVICE_FAILURE";
++	case MOD_HDCP_STATUS_HDCP1_CREATE_SESSION_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP1_CREATE_SESSION_FAILURE";
++	case MOD_HDCP_STATUS_HDCP1_DESTROY_SESSION_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP1_DESTROY_SESSION_FAILURE";
++	case MOD_HDCP_STATUS_HDCP1_VALIDATE_ENCRYPTION_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP1_VALIDATE_ENCRYPTION_FAILURE";
++	case MOD_HDCP_STATUS_HDCP1_NOT_HDCP_REPEATER:
++		return "MOD_HDCP_STATUS_HDCP1_NOT_HDCP_REPEATER";
++	case MOD_HDCP_STATUS_HDCP1_NOT_CAPABLE:
++		return "MOD_HDCP_STATUS_HDCP1_NOT_CAPABLE";
++	case MOD_HDCP_STATUS_HDCP1_R0_PRIME_PENDING:
++		return "MOD_HDCP_STATUS_HDCP1_R0_PRIME_PENDING";
++	case MOD_HDCP_STATUS_HDCP1_VALIDATE_RX_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP1_VALIDATE_RX_FAILURE";
++	case MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY:
++		return "MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY";
++	case MOD_HDCP_STATUS_HDCP1_VALIDATE_KSV_LIST_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP1_VALIDATE_KSV_LIST_FAILURE";
++	case MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION:
++		return "MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION";
++	case MOD_HDCP_STATUS_HDCP1_ENABLE_STREAM_ENCRYPTION_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP1_ENABLE_STREAM_ENCRYPTION_FAILURE";
++	case MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE";
++	case MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE";
++	case MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE";
++	case MOD_HDCP_STATUS_HDCP1_LINK_INTEGRITY_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP1_LINK_INTEGRITY_FAILURE";
++	case MOD_HDCP_STATUS_HDCP1_REAUTH_REQUEST_ISSUED:
++		return "MOD_HDCP_STATUS_HDCP1_REAUTH_REQUEST_ISSUED";
++	case MOD_HDCP_STATUS_HDCP1_LINK_MAINTENANCE_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP1_LINK_MAINTENANCE_FAILURE";
++	case MOD_HDCP_STATUS_HDCP1_INVALID_BKSV:
++		return "MOD_HDCP_STATUS_HDCP1_INVALID_BKSV";
++	case MOD_HDCP_STATUS_DDC_FAILURE:
++		return "MOD_HDCP_STATUS_DDC_FAILURE";
++	case MOD_HDCP_STATUS_INVALID_OPERATION:
++		return "MOD_HDCP_STATUS_INVALID_OPERATION";
++	default:
++		return "MOD_HDCP_STATUS_UNKNOWN";
++	}
++}
++
++char *mod_hdcp_state_id_to_str(int32_t id)
++{
++	switch (id) {
++	case HDCP_UNINITIALIZED:
++		return "HDCP_UNINITIALIZED";
++	case HDCP_INITIALIZED:
++		return "HDCP_INITIALIZED";
++	case HDCP_CP_NOT_DESIRED:
++		return "HDCP_CP_NOT_DESIRED";
++	case H1_A0_WAIT_FOR_ACTIVE_RX:
++		return "H1_A0_WAIT_FOR_ACTIVE_RX";
++	case H1_A1_EXCHANGE_KSVS:
++		return "H1_A1_EXCHANGE_KSVS";
++	case H1_A2_COMPUTATIONS_A3_VALIDATE_RX_A6_TEST_FOR_REPEATER:
++		return "H1_A2_COMPUTATIONS_A3_VALIDATE_RX_A6_TEST_FOR_REPEATER";
++	case H1_A45_AUTHENICATED:
++		return "H1_A45_AUTHENICATED";
++	case H1_A8_WAIT_FOR_READY:
++		return "H1_A8_WAIT_FOR_READY";
++	case H1_A9_READ_KSV_LIST:
++		return "H1_A9_READ_KSV_LIST";
++	case D1_A0_DETERMINE_RX_HDCP_CAPABLE:
++		return "D1_A0_DETERMINE_RX_HDCP_CAPABLE";
++	case D1_A1_EXCHANGE_KSVS:
++		return "D1_A1_EXCHANGE_KSVS";
++	case D1_A23_WAIT_FOR_R0_PRIME:
++		return "D1_A23_WAIT_FOR_R0_PRIME";
++	case D1_A2_COMPUTATIONS_A3_VALIDATE_RX_A5_TEST_FOR_REPEATER:
++		return "D1_A2_COMPUTATIONS_A3_VALIDATE_RX_A5_TEST_FOR_REPEATER";
++	case D1_A4_AUTHENICATED:
++		return "D1_A4_AUTHENICATED";
++	case D1_A6_WAIT_FOR_READY:
++		return "D1_A6_WAIT_FOR_READY";
++	case D1_A7_READ_KSV_LIST:
++		return "D1_A7_READ_KSV_LIST";
++	default:
++		return "UNKNOWN_STATE_ID";
++	};
++}
++
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
+new file mode 100644
+index 000000000000..2fd0e0a893ef
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
+@@ -0,0 +1,139 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef MOD_HDCP_LOG_H_
++#define MOD_HDCP_LOG_H_
++
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++#define HDCP_LOG_ERR(hdcp, ...) DRM_ERROR(__VA_ARGS__)
++#define HDCP_LOG_VER(hdcp, ...) DRM_DEBUG_KMS(__VA_ARGS__)
++#define HDCP_LOG_FSM(hdcp, ...) DRM_DEBUG_KMS(__VA_ARGS__)
++#define HDCP_LOG_TOP(hdcp, ...) pr_debug("[HDCP_TOP]:"__VA_ARGS__)
++#define HDCP_LOG_DDC(hdcp, ...) pr_debug("[HDCP_DDC]:"__VA_ARGS__)
++#endif
++
++/* default logs */
++#define HDCP_ERROR_TRACE(hdcp, status) \
++		HDCP_LOG_ERR(hdcp, \
++			"[Link %d] ERROR %s IN STATE %s", \
++			hdcp->config.index, \
++			mod_hdcp_status_to_str(status), \
++			mod_hdcp_state_id_to_str(hdcp->state.id))
++#define HDCP_HDCP1_ENABLED_TRACE(hdcp, displayIndex) \
++		HDCP_LOG_VER(hdcp, \
++			"[Link %d] HDCP 1.4 enabled on display %d", \
++			hdcp->config.index, displayIndex)
++/* state machine logs */
++#define HDCP_REMOVE_DISPLAY_TRACE(hdcp, displayIndex) \
++		HDCP_LOG_FSM(hdcp, \
++			"[Link %d] HDCP_REMOVE_DISPLAY index %d", \
++			hdcp->config.index, displayIndex)
++#define HDCP_INPUT_PASS_TRACE(hdcp, str) \
++		HDCP_LOG_FSM(hdcp, \
++			"[Link %d]\tPASS %s", \
++			hdcp->config.index, str)
++#define HDCP_INPUT_FAIL_TRACE(hdcp, str) \
++		HDCP_LOG_FSM(hdcp, \
++			"[Link %d]\tFAIL %s", \
++			hdcp->config.index, str)
++#define HDCP_NEXT_STATE_TRACE(hdcp, id, output) do { \
++		if (output->watchdog_timer_needed) \
++			HDCP_LOG_FSM(hdcp, \
++				"[Link %d] > %s with %d ms watchdog", \
++				hdcp->config.index, \
++				mod_hdcp_state_id_to_str(id), output->watchdog_timer_delay); \
++		else \
++			HDCP_LOG_FSM(hdcp, \
++				"[Link %d] > %s", hdcp->config.index, \
++				mod_hdcp_state_id_to_str(id)); \
++} while (0)
++#define HDCP_TIMEOUT_TRACE(hdcp) \
++		HDCP_LOG_FSM(hdcp, "[Link %d] --> TIMEOUT", hdcp->config.index)
++#define HDCP_CPIRQ_TRACE(hdcp) \
++		HDCP_LOG_FSM(hdcp, "[Link %d] --> CPIRQ", hdcp->config.index)
++#define HDCP_EVENT_TRACE(hdcp, event) \
++		if (event == MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) \
++			HDCP_TIMEOUT_TRACE(hdcp); \
++		else if (event == MOD_HDCP_EVENT_CPIRQ) \
++			HDCP_CPIRQ_TRACE(hdcp)
++/* TODO: find some way to tell if logging is off to save time */
++#define HDCP_DDC_READ_TRACE(hdcp, msg_name, msg, msg_size) do { \
++		mod_hdcp_dump_binary_message(msg, msg_size, hdcp->buf, \
++				sizeof(hdcp->buf)); \
++		HDCP_LOG_DDC(hdcp, "[Link %d] Read %s%s", hdcp->config.index, \
++				msg_name, hdcp->buf); \
++} while (0)
++#define HDCP_DDC_WRITE_TRACE(hdcp, msg_name, msg, msg_size) do { \
++		mod_hdcp_dump_binary_message(msg, msg_size, hdcp->buf, \
++				sizeof(hdcp->buf)); \
++		HDCP_LOG_DDC(hdcp, "[Link %d] Write %s%s", \
++				hdcp->config.index, msg_name,\
++				hdcp->buf); \
++} while (0)
++#define HDCP_FULL_DDC_TRACE(hdcp) do { \
++	HDCP_DDC_READ_TRACE(hdcp, "BKSV", hdcp->auth.msg.hdcp1.bksv, \
++			sizeof(hdcp->auth.msg.hdcp1.bksv)); \
++	HDCP_DDC_READ_TRACE(hdcp, "BCAPS", &hdcp->auth.msg.hdcp1.bcaps, \
++			sizeof(hdcp->auth.msg.hdcp1.bcaps)); \
++	HDCP_DDC_WRITE_TRACE(hdcp, "AN", hdcp->auth.msg.hdcp1.an, \
++			sizeof(hdcp->auth.msg.hdcp1.an)); \
++	HDCP_DDC_WRITE_TRACE(hdcp, "AKSV", hdcp->auth.msg.hdcp1.aksv, \
++			sizeof(hdcp->auth.msg.hdcp1.aksv)); \
++	HDCP_DDC_WRITE_TRACE(hdcp, "AINFO", &hdcp->auth.msg.hdcp1.ainfo, \
++			sizeof(hdcp->auth.msg.hdcp1.ainfo)); \
++	HDCP_DDC_READ_TRACE(hdcp, "RI' / R0'", \
++			(uint8_t *)&hdcp->auth.msg.hdcp1.r0p, \
++			sizeof(hdcp->auth.msg.hdcp1.r0p)); \
++	HDCP_DDC_READ_TRACE(hdcp, "BINFO", \
++			(uint8_t *)&hdcp->auth.msg.hdcp1.binfo_dp, \
++			sizeof(hdcp->auth.msg.hdcp1.binfo_dp)); \
++	HDCP_DDC_READ_TRACE(hdcp, "KSVLIST", hdcp->auth.msg.hdcp1.ksvlist, \
++			hdcp->auth.msg.hdcp1.ksvlist_size); \
++	HDCP_DDC_READ_TRACE(hdcp, "V'", hdcp->auth.msg.hdcp1.vp, \
++			sizeof(hdcp->auth.msg.hdcp1.vp)); \
++} while (0)
++#define HDCP_TOP_ADD_DISPLAY_TRACE(hdcp, i) \
++		HDCP_LOG_TOP(hdcp, "[Link %d]\tadd display %d", \
++				hdcp->config.index, i)
++#define HDCP_TOP_REMOVE_DISPLAY_TRACE(hdcp, i) \
++		HDCP_LOG_TOP(hdcp, "[Link %d]\tremove display %d", \
++				hdcp->config.index, i)
++#define HDCP_TOP_HDCP1_DESTROY_SESSION_TRACE(hdcp) \
++		HDCP_LOG_TOP(hdcp, "[Link %d]\tdestroy hdcp1 session", \
++				hdcp->config.index)
++#define HDCP_TOP_RESET_AUTH_TRACE(hdcp) \
++		HDCP_LOG_TOP(hdcp, "[Link %d]\treset authentication", hdcp->config.index)
++#define HDCP_TOP_RESET_CONN_TRACE(hdcp) \
++		HDCP_LOG_TOP(hdcp, "[Link %d]\treset connection", hdcp->config.index)
++#define HDCP_TOP_INTERFACE_TRACE(hdcp) do { \
++		HDCP_LOG_TOP(hdcp, "\n"); \
++		HDCP_LOG_TOP(hdcp, "[Link %d] %s", hdcp->config.index, __func__); \
++} while (0)
++#define HDCP_TOP_INTERFACE_TRACE_WITH_INDEX(hdcp, i) do { \
++		HDCP_LOG_TOP(hdcp, "\n"); \
++		HDCP_LOG_TOP(hdcp, "[Link %d] %s display %d", hdcp->config.index, __func__, i); \
++} while (0)
++
++#endif // MOD_HDCP_LOG_H_
+diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+new file mode 100644
+index 000000000000..dea21702edff
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+@@ -0,0 +1,289 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef MOD_HDCP_H_
++#define MOD_HDCP_H_
++
++#include "os_types.h"
++#include "signal_types.h"
++
++/* Forward Declarations */
++struct mod_hdcp;
++
++#define MAX_NUM_OF_DISPLAYS 6
++#define MAX_NUM_OF_ATTEMPTS 4
++#define MAX_NUM_OF_ERROR_TRACE 10
++
++/* detailed return status */
++enum mod_hdcp_status {
++	MOD_HDCP_STATUS_SUCCESS = 0,
++	MOD_HDCP_STATUS_FAILURE,
++	MOD_HDCP_STATUS_RESET_NEEDED,
++	MOD_HDCP_STATUS_DISPLAY_OUT_OF_BOUND,
++	MOD_HDCP_STATUS_DISPLAY_NOT_FOUND,
++	MOD_HDCP_STATUS_INVALID_STATE,
++	MOD_HDCP_STATUS_NOT_IMPLEMENTED,
++	MOD_HDCP_STATUS_INTERNAL_POLICY_FAILURE,
++	MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE,
++	MOD_HDCP_STATUS_CREATE_PSP_SERVICE_FAILURE,
++	MOD_HDCP_STATUS_DESTROY_PSP_SERVICE_FAILURE,
++	MOD_HDCP_STATUS_HDCP1_CREATE_SESSION_FAILURE,
++	MOD_HDCP_STATUS_HDCP1_DESTROY_SESSION_FAILURE,
++	MOD_HDCP_STATUS_HDCP1_VALIDATE_ENCRYPTION_FAILURE,
++	MOD_HDCP_STATUS_HDCP1_NOT_HDCP_REPEATER,
++	MOD_HDCP_STATUS_HDCP1_NOT_CAPABLE,
++	MOD_HDCP_STATUS_HDCP1_R0_PRIME_PENDING,
++	MOD_HDCP_STATUS_HDCP1_VALIDATE_RX_FAILURE,
++	MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY,
++	MOD_HDCP_STATUS_HDCP1_VALIDATE_KSV_LIST_FAILURE,
++	MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION,
++	MOD_HDCP_STATUS_HDCP1_ENABLE_STREAM_ENCRYPTION_FAILURE,
++	MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE,
++	MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE,
++	MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE,
++	MOD_HDCP_STATUS_HDCP1_LINK_INTEGRITY_FAILURE,
++	MOD_HDCP_STATUS_HDCP1_REAUTH_REQUEST_ISSUED,
++	MOD_HDCP_STATUS_HDCP1_LINK_MAINTENANCE_FAILURE,
++	MOD_HDCP_STATUS_HDCP1_INVALID_BKSV,
++	MOD_HDCP_STATUS_DDC_FAILURE, /* TODO: specific errors */
++	MOD_HDCP_STATUS_INVALID_OPERATION,
++	MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE,
++	MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE,
++	MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE,
++	MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE,
++	MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING,
++	MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING,
++	MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING,
++	MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE,
++	MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE,
++	MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE,
++	MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE,
++	MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING,
++	MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE,
++	MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE,
++	MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE,
++	MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY,
++	MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE,
++	MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION,
++	MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING,
++	MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE,
++	MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE,
++	MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST,
++	MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE,
++	MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE,
++};
++
++struct mod_hdcp_displayport {
++	uint8_t rev;
++	uint8_t assr_supported;
++};
++
++struct mod_hdcp_hdmi {
++	uint8_t reserved;
++};
++enum mod_hdcp_operation_mode {
++	MOD_HDCP_MODE_OFF,
++	MOD_HDCP_MODE_DEFAULT,
++	MOD_HDCP_MODE_DP,
++	MOD_HDCP_MODE_DP_MST
++};
++
++enum mod_hdcp_display_state {
++	MOD_HDCP_DISPLAY_INACTIVE = 0,
++	MOD_HDCP_DISPLAY_ACTIVE,
++	MOD_HDCP_DISPLAY_ACTIVE_AND_ADDED,
++	MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED
++};
++
++struct mod_hdcp_ddc {
++	void *handle;
++	struct {
++		bool (*read_i2c)(void *handle,
++				uint32_t address,
++				uint8_t offset,
++				uint8_t *data,
++				uint32_t size);
++		bool (*write_i2c)(void *handle,
++				uint32_t address,
++				const uint8_t *data,
++				uint32_t size);
++		bool (*read_dpcd)(void *handle,
++				uint32_t address,
++				uint8_t *data,
++				uint32_t size);
++		bool (*write_dpcd)(void *handle,
++				uint32_t address,
++				const uint8_t *data,
++				uint32_t size);
++	} funcs;
++};
++
++struct mod_hdcp_psp {
++	void *handle;
++	void *funcs;
++};
++
++struct mod_hdcp_display_adjustment {
++	uint8_t disable			: 1;
++	uint8_t reserved		: 7;
++};
++
++struct mod_hdcp_link_adjustment_hdcp1 {
++	uint8_t disable			: 1;
++	uint8_t postpone_encryption	: 1;
++	uint8_t reserved		: 6;
++};
++
++struct mod_hdcp_link_adjustment_hdcp2 {
++	uint8_t disable			: 1;
++	uint8_t disable_type1		: 1;
++	uint8_t force_no_stored_km	: 1;
++	uint8_t increase_h_prime_timeout: 1;
++	uint8_t reserved		: 4;
++};
++
++struct mod_hdcp_link_adjustment {
++	uint8_t auth_delay;
++	struct mod_hdcp_link_adjustment_hdcp1 hdcp1;
++	struct mod_hdcp_link_adjustment_hdcp2 hdcp2;
++};
++
++struct mod_hdcp_error {
++	enum mod_hdcp_status status;
++	uint8_t state_id;
++};
++
++struct mod_hdcp_trace {
++	struct mod_hdcp_error errors[MAX_NUM_OF_ERROR_TRACE];
++	uint8_t error_count;
++};
++
++enum mod_hdcp_encryption_status {
++	MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF = 0,
++	MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON,
++	MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON,
++	MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON
++};
++
++/* per link events dm has to notify to hdcp module */
++enum mod_hdcp_event {
++	MOD_HDCP_EVENT_CALLBACK = 0,
++	MOD_HDCP_EVENT_WATCHDOG_TIMEOUT,
++	MOD_HDCP_EVENT_CPIRQ
++};
++
++/* output flags from module requesting timer operations */
++struct mod_hdcp_output {
++	uint8_t callback_needed;
++	uint8_t callback_stop;
++	uint8_t watchdog_timer_needed;
++	uint8_t watchdog_timer_stop;
++	uint16_t callback_delay;
++	uint16_t watchdog_timer_delay;
++};
++
++/* used to represent per display info */
++struct mod_hdcp_display {
++	enum mod_hdcp_display_state state;
++	uint8_t index;
++	uint8_t controller;
++	uint8_t dig_fe;
++	union {
++		uint8_t vc_id;
++	};
++	struct mod_hdcp_display_adjustment adjust;
++};
++
++/* used to represent per link info */
++/* in case a link has multiple displays, they share the same link info */
++struct mod_hdcp_link {
++	enum mod_hdcp_operation_mode mode;
++	uint8_t dig_be;
++	uint8_t ddc_line;
++	union {
++		struct mod_hdcp_displayport dp;
++		struct mod_hdcp_hdmi hdmi;
++	};
++	struct mod_hdcp_link_adjustment adjust;
++};
++
++/* a query structure for a display's hdcp information */
++struct mod_hdcp_display_query {
++	const struct mod_hdcp_display *display;
++	const struct mod_hdcp_link *link;
++	const struct mod_hdcp_trace *trace;
++	enum mod_hdcp_encryption_status encryption_status;
++};
++
++/* contains values per on external display configuration change */
++struct mod_hdcp_config {
++	struct mod_hdcp_psp psp;
++	struct mod_hdcp_ddc ddc;
++	uint8_t index;
++};
++
++struct mod_hdcp;
++
++/* dm allocates memory of mod_hdcp per dc_link on dm init based on memory size*/
++size_t mod_hdcp_get_memory_size(void);
++
++/* called per link on link creation */
++enum mod_hdcp_status mod_hdcp_setup(struct mod_hdcp *hdcp,
++		struct mod_hdcp_config *config);
++
++/* called per link on link destroy */
++enum mod_hdcp_status mod_hdcp_teardown(struct mod_hdcp *hdcp);
++
++/* called per display on cp_desired set to true */
++enum mod_hdcp_status mod_hdcp_add_display(struct mod_hdcp *hdcp,
++		struct mod_hdcp_link *link, struct mod_hdcp_display *display,
++		struct mod_hdcp_output *output);
++
++/* called per display on cp_desired set to false */
++enum mod_hdcp_status mod_hdcp_remove_display(struct mod_hdcp *hdcp,
++		uint8_t index, struct mod_hdcp_output *output);
++
++/* called to query hdcp information on a specific index */
++enum mod_hdcp_status mod_hdcp_query_display(struct mod_hdcp *hdcp,
++		uint8_t index, struct mod_hdcp_display_query *query);
++
++/* called per link on connectivity change */
++enum mod_hdcp_status mod_hdcp_reset_connection(struct mod_hdcp *hdcp,
++		struct mod_hdcp_output *output);
++
++/* called per link on events (i.e. callback, watchdog, CP_IRQ) */
++enum mod_hdcp_status mod_hdcp_process_event(struct mod_hdcp *hdcp,
++		enum mod_hdcp_event event, struct mod_hdcp_output *output);
++
++/* called to convert enum mod_hdcp_status to c string */
++char *mod_hdcp_status_to_str(int32_t status);
++
++/* called to convert state id to c string */
++char *mod_hdcp_state_id_to_str(int32_t id);
++
++/* called to convert signal type to operation mode */
++enum mod_hdcp_operation_mode mod_hdcp_signal_type_to_operation_mode(
++		enum signal_type signal);
++#endif /* MOD_HDCP_H_ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3861-drm-amd-display-add-PSP-block-to-verify-hdcp-steps.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3861-drm-amd-display-add-PSP-block-to-verify-hdcp-steps.patch
new file mode 100644
index 00000000..46318d55
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3861-drm-amd-display-add-PSP-block-to-verify-hdcp-steps.patch
@@ -0,0 +1,637 @@
+From 0008c5471d74cc19c910a6341f3386fb25ca7a52 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Tue, 6 Aug 2019 18:04:44 -0400
+Subject: [PATCH 3861/4256] drm/amd/display: add PSP block to verify hdcp steps
+
+[Why]
+All the HDCP transactions should be verified using PSP.
+
+[How]
+This patch calls psp with the correct inputs to verify the steps
+of authentication.
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/display/modules/hdcp/hdcp_psp.c   | 328 ++++++++++++++++++
+ .../drm/amd/display/modules/hdcp/hdcp_psp.h   | 272 +++++++++++++++
+ 2 files changed, 600 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+ create mode 100644 drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+new file mode 100644
+index 000000000000..646d909bbc37
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+@@ -0,0 +1,328 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#define MAX_NUM_DISPLAYS 24
++
++
++#include "hdcp.h"
++
++#include "amdgpu.h"
++#include "hdcp_psp.h"
++
++enum mod_hdcp_status mod_hdcp_remove_display_topology(struct mod_hdcp *hdcp)
++{
++
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_dtm_shared_memory *dtm_cmd;
++	struct mod_hdcp_display *display = NULL;
++	uint8_t i;
++
++	dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.dtm_shared_buf;
++
++	for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++) {
++		if (hdcp->connection.displays[i].state == MOD_HDCP_DISPLAY_ACTIVE_AND_ADDED) {
++
++			memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory));
++
++			display = &hdcp->connection.displays[i];
++
++			dtm_cmd->cmd_id = TA_DTM_COMMAND__TOPOLOGY_UPDATE_V2;
++			dtm_cmd->dtm_in_message.topology_update_v2.display_handle = display->index;
++			dtm_cmd->dtm_in_message.topology_update_v2.is_active = 0;
++			dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE;
++
++			psp_dtm_invoke(psp, dtm_cmd->cmd_id);
++
++			if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS)
++				return MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE;
++
++			display->state = MOD_HDCP_DISPLAY_ACTIVE;
++			HDCP_TOP_REMOVE_DISPLAY_TRACE(hdcp, display->index);
++		}
++	}
++
++	return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_add_display_topology(struct mod_hdcp *hdcp)
++{
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_dtm_shared_memory *dtm_cmd;
++	struct mod_hdcp_display *display = NULL;
++	struct mod_hdcp_link *link = &hdcp->connection.link;
++	uint8_t i;
++
++	if (!psp->dtm_context.dtm_initialized) {
++		DRM_ERROR("Failed to add display topology, DTM TA is not initialized.");
++		return MOD_HDCP_STATUS_FAILURE;
++	}
++
++	dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.dtm_shared_buf;
++
++	for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++) {
++		if (hdcp->connection.displays[i].state == MOD_HDCP_DISPLAY_ACTIVE) {
++			display = &hdcp->connection.displays[i];
++
++			memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory));
++
++			dtm_cmd->cmd_id = TA_DTM_COMMAND__TOPOLOGY_UPDATE_V2;
++			dtm_cmd->dtm_in_message.topology_update_v2.display_handle = display->index;
++			dtm_cmd->dtm_in_message.topology_update_v2.is_active = 1;
++			dtm_cmd->dtm_in_message.topology_update_v2.controller = display->controller;
++			dtm_cmd->dtm_in_message.topology_update_v2.ddc_line = link->ddc_line;
++			dtm_cmd->dtm_in_message.topology_update_v2.dig_be = link->dig_be;
++			dtm_cmd->dtm_in_message.topology_update_v2.dig_fe = display->dig_fe;
++			dtm_cmd->dtm_in_message.topology_update_v2.dp_mst_vcid = display->vc_id;
++			dtm_cmd->dtm_in_message.topology_update_v2.max_hdcp_supported_version =
++				TA_DTM_HDCP_VERSION_MAX_SUPPORTED__1_x;
++			dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE;
++
++			psp_dtm_invoke(psp, dtm_cmd->cmd_id);
++
++			if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS)
++				return MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE;
++
++			display->state = MOD_HDCP_DISPLAY_ACTIVE_AND_ADDED;
++			HDCP_TOP_ADD_DISPLAY_TRACE(hdcp, display->index);
++		}
++	}
++
++	return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp1_create_session(struct mod_hdcp *hdcp)
++{
++
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct mod_hdcp_display *display = get_first_added_display(hdcp);
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++
++	if (!psp->hdcp_context.hdcp_initialized) {
++		DRM_ERROR("Failed to create hdcp session. HDCP TA is not initialized.");
++		return MOD_HDCP_STATUS_FAILURE;
++	}
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	hdcp_cmd->in_msg.hdcp1_create_session.display_handle = display->index;
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP1_CREATE_SESSION;
++
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP1_CREATE_SESSION_FAILURE;
++
++	hdcp->auth.id = hdcp_cmd->out_msg.hdcp1_create_session.session_handle;
++	hdcp->auth.msg.hdcp1.ainfo = hdcp_cmd->out_msg.hdcp1_create_session.ainfo_primary;
++	memcpy(hdcp->auth.msg.hdcp1.aksv, hdcp_cmd->out_msg.hdcp1_create_session.aksv_primary,
++		sizeof(hdcp->auth.msg.hdcp1.aksv));
++	memcpy(hdcp->auth.msg.hdcp1.an, hdcp_cmd->out_msg.hdcp1_create_session.an_primary,
++		sizeof(hdcp->auth.msg.hdcp1.an));
++
++	return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp1_destroy_session(struct mod_hdcp *hdcp)
++{
++
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	hdcp_cmd->in_msg.hdcp1_destroy_session.session_handle = hdcp->auth.id;
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP1_DESTROY_SESSION;
++
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP1_DESTROY_SESSION_FAILURE;
++
++	HDCP_TOP_HDCP1_DESTROY_SESSION_TRACE(hdcp);
++
++	return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp1_validate_rx(struct mod_hdcp *hdcp)
++{
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	hdcp_cmd->in_msg.hdcp1_first_part_authentication.session_handle = hdcp->auth.id;
++
++	memcpy(hdcp_cmd->in_msg.hdcp1_first_part_authentication.bksv_primary, hdcp->auth.msg.hdcp1.bksv,
++		TA_HDCP__HDCP1_KSV_SIZE);
++
++	hdcp_cmd->in_msg.hdcp1_first_part_authentication.r0_prime_primary = hdcp->auth.msg.hdcp1.r0p;
++	hdcp_cmd->in_msg.hdcp1_first_part_authentication.bcaps = hdcp->auth.msg.hdcp1.bcaps;
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP1_FIRST_PART_AUTHENTICATION;
++
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP1_VALIDATE_RX_FAILURE;
++
++	if (hdcp_cmd->out_msg.hdcp1_first_part_authentication.authentication_status ==
++	    TA_HDCP_AUTHENTICATION_STATUS__HDCP1_FIRST_PART_COMPLETE) {
++		/* needs second part of authentication */
++		hdcp->connection.is_repeater = 1;
++	} else if (hdcp_cmd->out_msg.hdcp1_first_part_authentication.authentication_status ==
++		   TA_HDCP_AUTHENTICATION_STATUS__HDCP1_AUTHENTICATED) {
++		hdcp->connection.is_repeater = 0;
++	} else
++		return MOD_HDCP_STATUS_HDCP1_VALIDATE_RX_FAILURE;
++
++
++	return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp1_enable_encryption(struct mod_hdcp *hdcp)
++{
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++	struct mod_hdcp_display *display = get_first_added_display(hdcp);
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	hdcp_cmd->in_msg.hdcp1_enable_encryption.session_handle = hdcp->auth.id;
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP1_ENABLE_ENCRYPTION;
++
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION;
++
++	if (!is_dp_mst_hdcp(hdcp)) {
++		display->state = MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;
++		HDCP_HDCP1_ENABLED_TRACE(hdcp, display->index);
++	}
++	return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp1_validate_ksvlist_vp(struct mod_hdcp *hdcp)
++{
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	hdcp_cmd->in_msg.hdcp1_second_part_authentication.session_handle = hdcp->auth.id;
++
++	hdcp_cmd->in_msg.hdcp1_second_part_authentication.ksv_list_size = hdcp->auth.msg.hdcp1.ksvlist_size;
++	memcpy(hdcp_cmd->in_msg.hdcp1_second_part_authentication.ksv_list, hdcp->auth.msg.hdcp1.ksvlist,
++	       hdcp->auth.msg.hdcp1.ksvlist_size);
++
++	memcpy(hdcp_cmd->in_msg.hdcp1_second_part_authentication.v_prime, hdcp->auth.msg.hdcp1.vp,
++	       sizeof(hdcp->auth.msg.hdcp1.vp));
++
++	hdcp_cmd->in_msg.hdcp1_second_part_authentication.bstatus_binfo =
++		is_dp_hdcp(hdcp) ? hdcp->auth.msg.hdcp1.binfo_dp : hdcp->auth.msg.hdcp1.bstatus;
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP1_SECOND_PART_AUTHENTICATION;
++
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP1_VALIDATE_KSV_LIST_FAILURE;
++
++	return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp1_enable_dp_stream_encryption(struct mod_hdcp *hdcp)
++{
++
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++	int i = 0;
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++
++	for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++) {
++
++		if (hdcp->connection.displays[i].state != MOD_HDCP_DISPLAY_ACTIVE_AND_ADDED ||
++		    hdcp->connection.displays[i].adjust.disable)
++			continue;
++
++		memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++		hdcp_cmd->in_msg.hdcp1_enable_dp_stream_encryption.session_handle = hdcp->auth.id;
++		hdcp_cmd->in_msg.hdcp1_enable_dp_stream_encryption.display_handle = hdcp->connection.displays[i].index;
++		hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP1_ENABLE_DP_STREAM_ENCRYPTION;
++
++		psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++		if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++			return MOD_HDCP_STATUS_HDCP1_ENABLE_STREAM_ENCRYPTION_FAILURE;
++
++		hdcp->connection.displays[i].state = MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;
++		HDCP_HDCP1_ENABLED_TRACE(hdcp, hdcp->connection.displays[i].index);
++	}
++
++	return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp1_link_maintenance(struct mod_hdcp *hdcp)
++{
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	hdcp_cmd->in_msg.hdcp1_get_encryption_status.session_handle = hdcp->auth.id;
++
++	hdcp_cmd->out_msg.hdcp1_get_encryption_status.protection_level = 0;
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP1_GET_ENCRYPTION_STATUS;
++
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP1_LINK_MAINTENANCE_FAILURE;
++
++	return (hdcp_cmd->out_msg.hdcp1_get_encryption_status.protection_level == 1)
++		       ? MOD_HDCP_STATUS_SUCCESS
++		       : MOD_HDCP_STATUS_HDCP1_LINK_MAINTENANCE_FAILURE;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp1_get_link_encryption_status(struct mod_hdcp *hdcp,
++							       enum mod_hdcp_encryption_status *encryption_status)
++{
++	*encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
++
++	if (mod_hdcp_hdcp1_link_maintenance(hdcp) != MOD_HDCP_STATUS_SUCCESS)
++		return MOD_HDCP_STATUS_FAILURE;
++
++	*encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON;
++
++	return MOD_HDCP_STATUS_SUCCESS;
++}
++
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
+new file mode 100644
+index 000000000000..986fc07ea9ea
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
+@@ -0,0 +1,272 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef MODULES_HDCP_HDCP_PSP_H_
++#define MODULES_HDCP_HDCP_PSP_H_
++
++/*
++ * NOTE: These parameters are a one-to-one copy of the
++ * parameters required by PSP
++ */
++enum bgd_security_hdcp_encryption_level {
++	HDCP_ENCRYPTION_LEVEL__INVALID = 0,
++	HDCP_ENCRYPTION_LEVEL__OFF,
++	HDCP_ENCRYPTION_LEVEL__ON
++};
++
++enum ta_dtm_command {
++	TA_DTM_COMMAND__UNUSED_1 = 1,
++	TA_DTM_COMMAND__TOPOLOGY_UPDATE_V2,
++	TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE
++};
++
++/* DTM related enumerations */
++/**********************************************************/
++
++enum ta_dtm_status {
++	TA_DTM_STATUS__SUCCESS = 0x00,
++	TA_DTM_STATUS__GENERIC_FAILURE = 0x01,
++	TA_DTM_STATUS__INVALID_PARAMETER = 0x02,
++	TA_DTM_STATUS__NULL_POINTER = 0x3
++};
++
++/* input/output structures for DTM commands */
++/**********************************************************/
++/**
++ * Input structures
++ */
++enum ta_dtm_hdcp_version_max_supported {
++	TA_DTM_HDCP_VERSION_MAX_SUPPORTED__NONE = 0,
++	TA_DTM_HDCP_VERSION_MAX_SUPPORTED__1_x = 10,
++	TA_DTM_HDCP_VERSION_MAX_SUPPORTED__2_0 = 20,
++	TA_DTM_HDCP_VERSION_MAX_SUPPORTED__2_1 = 21,
++	TA_DTM_HDCP_VERSION_MAX_SUPPORTED__2_2 = 22,
++	TA_DTM_HDCP_VERSION_MAX_SUPPORTED__2_3 = 23
++};
++
++struct ta_dtm_topology_update_input_v2 {
++	/* display handle is unique across the driver and is used to identify a display */
++	/* for all security interfaces which reference displays such as HDCP */
++	uint32_t display_handle;
++	uint32_t is_active;
++	uint32_t is_miracast;
++	uint32_t controller;
++	uint32_t ddc_line;
++	uint32_t dig_be;
++	uint32_t dig_fe;
++	uint32_t dp_mst_vcid;
++	uint32_t is_assr;
++	uint32_t max_hdcp_supported_version;
++};
++
++struct ta_dtm_topology_assr_enable {
++	uint32_t display_topology_dig_be_index;
++};
++
++/**
++ * Output structures
++ */
++
++/* No output structures yet */
++
++union ta_dtm_cmd_input {
++	struct ta_dtm_topology_update_input_v2 topology_update_v2;
++	struct ta_dtm_topology_assr_enable topology_assr_enable;
++};
++
++union ta_dtm_cmd_output {
++	uint32_t reserved;
++};
++
++struct ta_dtm_shared_memory {
++	uint32_t cmd_id;
++	uint32_t resp_id;
++	enum ta_dtm_status dtm_status;
++	uint32_t reserved;
++	union ta_dtm_cmd_input dtm_in_message;
++	union ta_dtm_cmd_output dtm_out_message;
++};
++
++int psp_cmd_submit_buf(struct psp_context *psp, struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd,
++		uint64_t fence_mc_addr);
++
++enum ta_hdcp_command {
++	TA_HDCP_COMMAND__INITIALIZE,
++	TA_HDCP_COMMAND__HDCP1_CREATE_SESSION,
++	TA_HDCP_COMMAND__HDCP1_DESTROY_SESSION,
++	TA_HDCP_COMMAND__HDCP1_FIRST_PART_AUTHENTICATION,
++	TA_HDCP_COMMAND__HDCP1_SECOND_PART_AUTHENTICATION,
++	TA_HDCP_COMMAND__HDCP1_ENABLE_ENCRYPTION,
++	TA_HDCP_COMMAND__HDCP1_ENABLE_DP_STREAM_ENCRYPTION,
++	TA_HDCP_COMMAND__HDCP1_GET_ENCRYPTION_STATUS,
++};
++
++
++/* HDCP related enumerations */
++/**********************************************************/
++#define TA_HDCP__INVALID_SESSION 0xFFFF
++#define TA_HDCP__HDCP1_AN_SIZE 8
++#define TA_HDCP__HDCP1_KSV_SIZE 5
++#define TA_HDCP__HDCP1_KSV_LIST_MAX_ENTRIES 127
++#define TA_HDCP__HDCP1_V_PRIME_SIZE 20
++
++enum ta_hdcp_status {
++	TA_HDCP_STATUS__SUCCESS = 0x00,
++	TA_HDCP_STATUS__GENERIC_FAILURE = 0x01,
++	TA_HDCP_STATUS__NULL_POINTER = 0x02,
++	TA_HDCP_STATUS__FAILED_ALLOCATING_SESSION = 0x03,
++	TA_HDCP_STATUS__FAILED_SETUP_TX = 0x04,
++	TA_HDCP_STATUS__INVALID_PARAMETER = 0x05,
++	TA_HDCP_STATUS__VHX_ERROR = 0x06,
++	TA_HDCP_STATUS__SESSION_NOT_CLOSED_PROPERLY = 0x07,
++	TA_HDCP_STATUS__SRM_FAILURE = 0x08,
++	TA_HDCP_STATUS__MST_AUTHENTICATED_ALREADY_STARTED = 0x09,
++	TA_HDCP_STATUS__AKE_SEND_CERT_FAILURE = 0x0A,
++	TA_HDCP_STATUS__AKE_NO_STORED_KM_FAILURE = 0x0B,
++	TA_HDCP_STATUS__AKE_SEND_HPRIME_FAILURE = 0x0C,
++	TA_HDCP_STATUS__LC_SEND_LPRIME_FAILURE = 0x0D,
++	TA_HDCP_STATUS__SKE_SEND_EKS_FAILURE = 0x0E,
++	TA_HDCP_STATUS__REPAUTH_SEND_RXIDLIST_FAILURE = 0x0F,
++	TA_HDCP_STATUS__REPAUTH_STREAM_READY_FAILURE = 0x10,
++	TA_HDCP_STATUS__ASD_GENERIC_FAILURE = 0x11,
++	TA_HDCP_STATUS__UNWRAP_SECRET_FAILURE = 0x12,
++	TA_HDCP_STATUS__ENABLE_ENCR_FAILURE = 0x13,
++	TA_HDCP_STATUS__DISABLE_ENCR_FAILURE = 0x14,
++	TA_HDCP_STATUS__NOT_ENOUGH_MEMORY_FAILURE = 0x15,
++	TA_HDCP_STATUS__UNKNOWN_MESSAGE = 0x16,
++	TA_HDCP_STATUS__TOO_MANY_STREAM = 0x17
++};
++
++enum ta_hdcp_authentication_status {
++	TA_HDCP_AUTHENTICATION_STATUS__NOT_STARTED = 0x00,
++	TA_HDCP_AUTHENTICATION_STATUS__HDCP1_FIRST_PART_FAILED = 0x01,
++	TA_HDCP_AUTHENTICATION_STATUS__HDCP1_FIRST_PART_COMPLETE = 0x02,
++	TA_HDCP_AUTHENTICATION_STATUS__HDCP1_SECOND_PART_FAILED = 0x03,
++	TA_HDCP_AUTHENTICATION_STATUS__HDCP1_AUTHENTICATED = 0x04,
++	TA_HDCP_AUTHENTICATION_STATUS__HDCP1_KSV_VALIDATION_FAILED = 0x09
++};
++
++
++/* input/output structures for HDCP commands */
++/**********************************************************/
++struct ta_hdcp_cmd_hdcp1_create_session_input {
++	uint8_t display_handle;
++};
++
++struct ta_hdcp_cmd_hdcp1_create_session_output {
++	uint32_t session_handle;
++	uint8_t an_primary[TA_HDCP__HDCP1_AN_SIZE];
++	uint8_t aksv_primary[TA_HDCP__HDCP1_KSV_SIZE];
++	uint8_t ainfo_primary;
++	uint8_t an_secondary[TA_HDCP__HDCP1_AN_SIZE];
++	uint8_t aksv_secondary[TA_HDCP__HDCP1_KSV_SIZE];
++	uint8_t ainfo_secondary;
++};
++
++struct ta_hdcp_cmd_hdcp1_destroy_session_input {
++	uint32_t session_handle;
++};
++
++struct ta_hdcp_cmd_hdcp1_first_part_authentication_input {
++	uint32_t session_handle;
++	uint8_t bksv_primary[TA_HDCP__HDCP1_KSV_SIZE];
++	uint8_t bksv_secondary[TA_HDCP__HDCP1_KSV_SIZE];
++	uint8_t bcaps;
++	uint16_t r0_prime_primary;
++	uint16_t r0_prime_secondary;
++};
++
++struct ta_hdcp_cmd_hdcp1_first_part_authentication_output {
++	enum ta_hdcp_authentication_status authentication_status;
++};
++
++struct ta_hdcp_cmd_hdcp1_second_part_authentication_input {
++	uint32_t session_handle;
++	uint16_t bstatus_binfo;
++	uint8_t ksv_list[TA_HDCP__HDCP1_KSV_LIST_MAX_ENTRIES][TA_HDCP__HDCP1_KSV_SIZE];
++	uint32_t ksv_list_size;
++	uint8_t pj_prime;
++	uint8_t v_prime[TA_HDCP__HDCP1_V_PRIME_SIZE];
++};
++
++struct ta_hdcp_cmd_hdcp1_second_part_authentication_output {
++	enum ta_hdcp_authentication_status authentication_status;
++};
++
++struct ta_hdcp_cmd_hdcp1_enable_encryption_input {
++	uint32_t session_handle;
++};
++
++struct ta_hdcp_cmd_hdcp1_enable_dp_stream_encryption_input {
++	uint32_t session_handle;
++	uint32_t display_handle;
++};
++
++struct ta_hdcp_cmd_hdcp1_get_encryption_status_input {
++	uint32_t session_handle;
++};
++
++struct ta_hdcp_cmd_hdcp1_get_encryption_status_output {
++	uint32_t protection_level;
++};
++
++/**********************************************************/
++/* Common input structure for HDCP callbacks */
++union ta_hdcp_cmd_input {
++	struct ta_hdcp_cmd_hdcp1_create_session_input hdcp1_create_session;
++	struct ta_hdcp_cmd_hdcp1_destroy_session_input hdcp1_destroy_session;
++	struct ta_hdcp_cmd_hdcp1_first_part_authentication_input hdcp1_first_part_authentication;
++	struct ta_hdcp_cmd_hdcp1_second_part_authentication_input hdcp1_second_part_authentication;
++	struct ta_hdcp_cmd_hdcp1_enable_encryption_input hdcp1_enable_encryption;
++	struct ta_hdcp_cmd_hdcp1_enable_dp_stream_encryption_input hdcp1_enable_dp_stream_encryption;
++	struct ta_hdcp_cmd_hdcp1_get_encryption_status_input hdcp1_get_encryption_status;
++};
++
++/* Common output structure for HDCP callbacks */
++union ta_hdcp_cmd_output {
++	struct ta_hdcp_cmd_hdcp1_create_session_output hdcp1_create_session;
++	struct ta_hdcp_cmd_hdcp1_first_part_authentication_output hdcp1_first_part_authentication;
++	struct ta_hdcp_cmd_hdcp1_second_part_authentication_output hdcp1_second_part_authentication;
++	struct ta_hdcp_cmd_hdcp1_get_encryption_status_output hdcp1_get_encryption_status;
++};
++/**********************************************************/
++
++struct ta_hdcp_shared_memory {
++	uint32_t cmd_id;
++	enum ta_hdcp_status hdcp_status;
++	uint32_t reserved;
++	union ta_hdcp_cmd_input in_msg;
++	union ta_hdcp_cmd_output out_msg;
++};
++
++enum psp_status {
++	PSP_STATUS__SUCCESS = 0,
++	PSP_STATUS__ERROR_INVALID_PARAMS,
++	PSP_STATUS__ERROR_GENERIC,
++	PSP_STATUS__ERROR_OUT_OF_MEMORY,
++	PSP_STATUS__ERROR_UNSUPPORTED_FEATURE
++};
++
++#endif /* MODULES_HDCP_HDCP_PSP_H_ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3862-drm-amd-display-Update-hdcp-display-config.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3862-drm-amd-display-Update-hdcp-display-config.patch
new file mode 100644
index 00000000..946f0d5b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3862-drm-amd-display-Update-hdcp-display-config.patch
@@ -0,0 +1,240 @@
+From 9ff67f68857534e2d360e281e16c913c7392e6bc Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Tue, 6 Aug 2019 17:43:53 -0400
+Subject: [PATCH 3862/4256] drm/amd/display: Update hdcp display config
+
+[Why]
+We need to update the hdcp display parameter whenever the link is
+updated, so the next time there is an update to hdcp we have the
+latest display info
+
+[How]
+Create a callback, and use this anytime there is a change in the link. This will
+be used later by the dm.
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c      | 10 ++++
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 31 ++++++++++++
+ drivers/gpu/drm/amd/display/dc/dc.h           |  5 ++
+ drivers/gpu/drm/amd/display/dc/dc_types.h     |  7 +++
+ drivers/gpu/drm/amd/display/dc/dm_cp_psp.h    | 49 +++++++++++++++++++
+ .../gpu/drm/amd/display/dc/inc/core_types.h   |  4 +-
+ 6 files changed, 105 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 1ab1df443202..56861f796406 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -827,6 +827,16 @@ void dc_hardware_init(struct dc *dc)
+ void dc_init_callbacks(struct dc *dc,
+ 		const struct dc_callback_init *init_params)
+ {
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++	dc->ctx->cp_psp = init_params->cp_psp;
++#endif
++}
++
++void dc_deinit_callbacks(struct dc *dc)
++{
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++	memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
++#endif
+ }
+ 
+ void dc_destroy(struct dc **dc)
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 66758033757d..2da239765690 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2688,6 +2688,24 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
+ 
+ 	return DC_OK;
+ }
++#if defined(CONFIG_DRM_AMD_DC_HDCP)
++static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
++{
++	struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
++	if (cp_psp && cp_psp->funcs.update_stream_config) {
++		struct cp_psp_stream_config config;
++
++		memset(&config, 0, sizeof(config));
++
++		config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
++		config.stream_enc_inst = (uint8_t) pipe_ctx->stream_res.stream_enc->id;
++		config.link_enc_inst = pipe_ctx->stream->link->link_enc_hw_inst;
++		config.dpms_off = dpms_off;
++		config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
++		cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
++	}
++}
++#endif
+ 
+ void core_link_enable_stream(
+ 		struct dc_state *state,
+@@ -2748,6 +2766,9 @@ void core_link_enable_stream(
+ 		/* Do not touch link on seamless boot optimization. */
+ 		if (pipe_ctx->stream->apply_seamless_boot_optimization) {
+ 			pipe_ctx->stream->dpms_off = false;
++#if defined(CONFIG_DRM_AMD_DC_HDCP)
++			update_psp_stream_config(pipe_ctx, false);
++#endif
+ 			return;
+ 		}
+ 
+@@ -2755,6 +2776,9 @@ void core_link_enable_stream(
+ 		if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
+ 					apply_edp_fast_boot_optimization) {
+ 			pipe_ctx->stream->dpms_off = false;
++#if defined(CONFIG_DRM_AMD_DC_HDCP)
++			update_psp_stream_config(pipe_ctx, false);
++#endif
+ 			return;
+ 		}
+ 
+@@ -2814,6 +2838,9 @@ void core_link_enable_stream(
+ 
+ 		if (dc_is_dp_signal(pipe_ctx->stream->signal))
+ 			enable_stream_features(pipe_ctx);
++#if defined(CONFIG_DRM_AMD_DC_HDCP)
++		update_psp_stream_config(pipe_ctx, false);
++#endif
+ 	}
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	else { // if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
+@@ -2831,6 +2858,10 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	struct dc_link *link = stream->sink->link;
+ 
++#if defined(CONFIG_DRM_AMD_DC_HDCP)
++	update_psp_stream_config(pipe_ctx, true);
++#endif
++
+ 	core_dc->hwss.blank_stream(pipe_ctx);
+ 
+ 	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 3ecc42987b05..9185297d93c4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -552,7 +552,11 @@ struct dc_init_data {
+ };
+ 
+ struct dc_callback_init {
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++	struct cp_psp cp_psp;
++#else
+ 	uint8_t reserved;
++#endif
+ };
+ 
+ struct dc *dc_create(const struct dc_init_data *init_params);
+@@ -566,6 +570,7 @@ int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_c
+ #endif
+ void dc_init_callbacks(struct dc *dc,
+ 		const struct dc_callback_init *init_params);
++void dc_deinit_callbacks(struct dc *dc);
+ void dc_destroy(struct dc **dc);
+ 
+ /*******************************************************************************
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
+index e6ae66791943..d9be8fc3889f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
+@@ -38,6 +38,10 @@
+ #include "dal_types.h"
+ #include "grph_object_defs.h"
+ 
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++#include "dm_cp_psp.h"
++#endif
++
+ /* forward declarations */
+ struct dc_plane_state;
+ struct dc_stream_state;
+@@ -105,6 +109,9 @@ struct dc_context {
+ 	uint32_t dc_sink_id_count;
+ 	uint32_t dc_stream_id_count;
+ 	uint64_t fbc_gpu_addr;
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++	struct cp_psp cp_psp;
++#endif
+ };
+ 
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h b/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
+new file mode 100644
+index 000000000000..626d22d437f4
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
+@@ -0,0 +1,49 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef DM_CP_PSP_IF__H
++#define DM_CP_PSP_IF__H
++
++struct dc_link;
++
++struct cp_psp_stream_config {
++	uint8_t otg_inst;
++	uint8_t link_enc_inst;
++	uint8_t stream_enc_inst;
++	void *dm_stream_ctx;
++	bool dpms_off;
++};
++
++struct cp_psp_funcs {
++	void (*update_stream_config)(void *handle, struct cp_psp_stream_config *config);
++};
++
++struct cp_psp {
++	void *handle;
++	struct cp_psp_funcs funcs;
++};
++
++
++#endif /* DM_CP_PSP_IF__H */
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index daf8d5d9c3f1..eee78a73d88c 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -52,7 +52,9 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
+ #include "clock_source.h"
+ #include "audio.h"
+ #include "dm_pp_smu.h"
+-
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++#include "dm_cp_psp.h"
++#endif
+ 
+ /************ link *****************/
+ struct link_init_data {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3863-drm-amd-display-Create-amdgpu_dm_hdcp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3863-drm-amd-display-Create-amdgpu_dm_hdcp.patch
new file mode 100644
index 00000000..94079b51
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3863-drm-amd-display-Create-amdgpu_dm_hdcp.patch
@@ -0,0 +1,359 @@
+From cfa8cb5aa5404c3bdc360563d245d755c6fac9f8 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Tue, 14 May 2019 13:20:19 -0400
+Subject: [PATCH 3863/4256] drm/amd/display: Create amdgpu_dm_hdcp
+
+[Why]
+We need to interact with the hdcp module from the DM, the module
+has to be interacted with in terms of events
+
+[How]
+Create the files needed for linux hdcp. These files manage the events
+needed for the dm to interact with the hdcp module.
+
+We use the kernel work queue to process the events needed for
+the module
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/Makefile    |   4 +
+ .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c    | 241 ++++++++++++++++++
+ .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.h    |  61 +++++
+ 3 files changed, 306 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+ create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile
+index 94911871eb9b..9a3b7bf8ab0b 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile
+@@ -31,6 +31,10 @@ ifneq ($(CONFIG_DRM_AMD_DC),)
+ AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o amdgpu_dm_pp_smu.o
+ endif
+ 
++ifdef CONFIG_DRM_AMD_DC_HDCP
++AMDGPUDM += amdgpu_dm_hdcp.o
++endif
++
+ ifneq ($(CONFIG_DEBUG_FS),)
+ AMDGPUDM += amdgpu_dm_crc.o amdgpu_dm_debugfs.o
+ endif
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+new file mode 100644
+index 000000000000..004b6e8e9ed5
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+@@ -0,0 +1,241 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "amdgpu_dm_hdcp.h"
++#include "amdgpu.h"
++#include "amdgpu_dm.h"
++
++static void process_output(struct hdcp_workqueue *hdcp_work)
++{
++	struct mod_hdcp_output output = hdcp_work->output;
++
++	if (output.callback_stop)
++		cancel_delayed_work(&hdcp_work->callback_dwork);
++
++	if (output.callback_needed)
++		schedule_delayed_work(&hdcp_work->callback_dwork,
++				      msecs_to_jiffies(output.callback_delay));
++
++	if (output.watchdog_timer_stop)
++		cancel_delayed_work(&hdcp_work->watchdog_timer_dwork);
++
++	if (output.watchdog_timer_needed)
++		schedule_delayed_work(&hdcp_work->watchdog_timer_dwork,
++				      msecs_to_jiffies(output.watchdog_timer_delay));
++
++}
++
++void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index)
++{
++	struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
++	struct mod_hdcp_display *display = &hdcp_work[link_index].display;
++	struct mod_hdcp_link *link = &hdcp_work[link_index].link;
++
++	mutex_lock(&hdcp_w->mutex);
++
++	mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output);
++
++	process_output(hdcp_w);
++
++	mutex_unlock(&hdcp_w->mutex);
++
++}
++
++void hdcp_remove_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index,  unsigned int display_index)
++{
++	struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
++
++	mutex_lock(&hdcp_w->mutex);
++
++	mod_hdcp_remove_display(&hdcp_w->hdcp, display_index, &hdcp_w->output);
++
++	process_output(hdcp_w);
++
++	mutex_unlock(&hdcp_w->mutex);
++
++}
++
++void hdcp_reset_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index)
++{
++	struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
++
++	mutex_lock(&hdcp_w->mutex);
++
++	mod_hdcp_reset_connection(&hdcp_w->hdcp,  &hdcp_w->output);
++
++	process_output(hdcp_w);
++
++	mutex_unlock(&hdcp_w->mutex);
++}
++
++void hdcp_handle_cpirq(struct hdcp_workqueue *hdcp_work, unsigned int link_index)
++{
++	struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
++
++	schedule_work(&hdcp_w->cpirq_work);
++}
++
++
++
++
++static void event_callback(struct work_struct *work)
++{
++	struct hdcp_workqueue *hdcp_work;
++
++	hdcp_work = container_of(to_delayed_work(work), struct hdcp_workqueue,
++				      callback_dwork);
++
++	mutex_lock(&hdcp_work->mutex);
++
++	cancel_delayed_work(&hdcp_work->watchdog_timer_dwork);
++
++	mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CALLBACK,
++			       &hdcp_work->output);
++
++	process_output(hdcp_work);
++
++	mutex_unlock(&hdcp_work->mutex);
++
++
++}
++
++
++static void event_watchdog_timer(struct work_struct *work)
++{
++	struct hdcp_workqueue *hdcp_work;
++
++	hdcp_work = container_of(to_delayed_work(work),
++				      struct hdcp_workqueue,
++				      watchdog_timer_dwork);
++
++	mutex_lock(&hdcp_work->mutex);
++
++	mod_hdcp_process_event(&hdcp_work->hdcp,
++			       MOD_HDCP_EVENT_WATCHDOG_TIMEOUT,
++			       &hdcp_work->output);
++
++	process_output(hdcp_work);
++
++	mutex_unlock(&hdcp_work->mutex);
++
++}
++
++static void event_cpirq(struct work_struct *work)
++{
++	struct hdcp_workqueue *hdcp_work;
++
++	hdcp_work = container_of(work, struct hdcp_workqueue, cpirq_work);
++
++	mutex_lock(&hdcp_work->mutex);
++
++	mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CPIRQ, &hdcp_work->output);
++
++	process_output(hdcp_work);
++
++	mutex_unlock(&hdcp_work->mutex);
++
++}
++
++
++void hdcp_destroy(struct hdcp_workqueue *hdcp_work)
++{
++	int i = 0;
++
++	for (i = 0; i < hdcp_work->max_link; i++) {
++		cancel_delayed_work_sync(&hdcp_work[i].callback_dwork);
++		cancel_delayed_work_sync(&hdcp_work[i].watchdog_timer_dwork);
++	}
++
++	kfree(hdcp_work);
++
++}
++
++static void update_config(void *handle, struct cp_psp_stream_config *config)
++{
++	struct hdcp_workqueue *hdcp_work = handle;
++	struct amdgpu_dm_connector *aconnector = config->dm_stream_ctx;
++	int link_index = aconnector->dc_link->link_index;
++	struct mod_hdcp_display *display = &hdcp_work[link_index].display;
++	struct mod_hdcp_link *link = &hdcp_work[link_index].link;
++
++	memset(display, 0, sizeof(*display));
++	memset(link, 0, sizeof(*link));
++
++	display->index = aconnector->base.index;
++	display->state = MOD_HDCP_DISPLAY_ACTIVE;
++
++	if (aconnector->dc_sink != NULL)
++		link->mode = mod_hdcp_signal_type_to_operation_mode(aconnector->dc_sink->sink_signal);
++
++	display->controller = CONTROLLER_ID_D0 + config->otg_inst;
++	display->dig_fe = config->stream_enc_inst;
++	link->dig_be = config->link_enc_inst;
++	link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1;
++	link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
++	link->adjust.hdcp2.disable = 1;
++
++}
++
++struct hdcp_workqueue *hdcp_create_workqueue(void *psp_context, struct cp_psp *cp_psp, struct dc *dc)
++{
++
++	int max_caps = dc->caps.max_links;
++	struct hdcp_workqueue *hdcp_work = kzalloc(max_caps*sizeof(*hdcp_work), GFP_KERNEL);
++	int i = 0;
++
++	if (hdcp_work == NULL)
++		goto fail_alloc_context;
++
++	hdcp_work->max_link = max_caps;
++
++	for (i = 0; i < max_caps; i++) {
++
++		mutex_init(&hdcp_work[i].mutex);
++
++		INIT_WORK(&hdcp_work[i].cpirq_work, event_cpirq);
++		INIT_DELAYED_WORK(&hdcp_work[i].callback_dwork, event_callback);
++		INIT_DELAYED_WORK(&hdcp_work[i].watchdog_timer_dwork, event_watchdog_timer);
++
++		hdcp_work[i].hdcp.config.psp.handle =  psp_context;
++		hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i);
++
++	}
++
++	cp_psp->funcs.update_stream_config = update_config;
++	cp_psp->handle = hdcp_work;
++
++	return hdcp_work;
++
++fail_alloc_context:
++	kfree(hdcp_work);
++
++	return NULL;
++
++
++
++}
++
++
++
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+new file mode 100644
+index 000000000000..cb6c6fbd74f6
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+@@ -0,0 +1,61 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef AMDGPU_DM_AMDGPU_DM_HDCP_H_
++#define AMDGPU_DM_AMDGPU_DM_HDCP_H_
++
++#include "mod_hdcp.h"
++#include "hdcp.h"
++#include "dc.h"
++#include "dm_cp_psp.h"
++
++struct mod_hdcp;
++struct mod_hdcp_link;
++struct mod_hdcp_display;
++struct cp_psp;
++
++struct hdcp_workqueue {
++	struct work_struct cpirq_work;
++	struct delayed_work callback_dwork;
++	struct delayed_work watchdog_timer_dwork;
++	struct mutex mutex;
++
++	struct mod_hdcp hdcp;
++	struct mod_hdcp_output output;
++	struct mod_hdcp_display display;
++	struct mod_hdcp_link link;
++
++	uint8_t max_link;
++};
++
++void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index);
++void hdcp_remove_display(struct hdcp_workqueue *work, unsigned int link_index, unsigned int display_index);
++void hdcp_reset_display(struct hdcp_workqueue *work, unsigned int link_index);
++void hdcp_handle_cpirq(struct hdcp_workqueue *work, unsigned int link_index);
++void hdcp_destroy(struct hdcp_workqueue *work);
++
++struct hdcp_workqueue *hdcp_create_workqueue(void *psp_context, struct cp_psp *cp_psp, struct dc *dc);
++
++#endif /* AMDGPU_DM_AMDGPU_DM_HDCP_H_ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3864-drm-amd-display-Create-dpcd-and-i2c-packing-function.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3864-drm-amd-display-Create-dpcd-and-i2c-packing-function.patch
new file mode 100644
index 00000000..3299f973
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3864-drm-amd-display-Create-dpcd-and-i2c-packing-function.patch
@@ -0,0 +1,80 @@
+From 215e72a5c23f7d3a9dd5400fa0b05ed423828ab6 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 16 May 2019 11:57:52 -0400
+Subject: [PATCH 3864/4256] drm/amd/display: Create dpcd and i2c packing
+ functions
+
+[Why]
+We need to read and write specific i2c and dpcd messages.
+
+[How]
+Created static functions for packing the dpcd and i2c messages for hdcp.
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c    | 40 ++++++++++++++++++-
+ 1 file changed, 39 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+index 004b6e8e9ed5..9d11d7695508 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+@@ -26,6 +26,41 @@
+ #include "amdgpu_dm_hdcp.h"
+ #include "amdgpu.h"
+ #include "amdgpu_dm.h"
++#include "dm_helpers.h"
++
++bool lp_write_i2c(void *handle, uint32_t address, const uint8_t *data, uint32_t size)
++{
++
++	struct dc_link *link = handle;
++	struct i2c_payload i2c_payloads[] = {{true, address, size, (void *)data} };
++	struct i2c_command cmd = {i2c_payloads, 1, I2C_COMMAND_ENGINE_HW, link->dc->caps.i2c_speed_in_khz};
++
++	return dm_helpers_submit_i2c(link->ctx, link, &cmd);
++}
++
++bool lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t *data, uint32_t size)
++{
++	struct dc_link *link = handle;
++
++	struct i2c_payload i2c_payloads[] = {{true, address, 1, &offset}, {false, address, size, data} };
++	struct i2c_command cmd = {i2c_payloads, 2, I2C_COMMAND_ENGINE_HW, link->dc->caps.i2c_speed_in_khz};
++
++	return dm_helpers_submit_i2c(link->ctx, link, &cmd);
++}
++
++bool lp_write_dpcd(void *handle, uint32_t address, const uint8_t *data, uint32_t size)
++{
++	struct dc_link *link = handle;
++
++	return dm_helpers_dp_write_dpcd(link->ctx, link, address, data, size);
++}
++
++bool lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t size)
++{
++	struct dc_link *link = handle;
++
++	return dm_helpers_dp_read_dpcd(link->ctx, link, address, data, size);
++}
+ 
+ static void process_output(struct hdcp_workqueue *hdcp_work)
+ {
+@@ -220,7 +255,10 @@ struct hdcp_workqueue *hdcp_create_workqueue(void *psp_context, struct cp_psp *c
+ 
+ 		hdcp_work[i].hdcp.config.psp.handle =  psp_context;
+ 		hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i);
+-
++		hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c;
++		hdcp_work[i].hdcp.config.ddc.funcs.read_i2c = lp_read_i2c;
++		hdcp_work[i].hdcp.config.ddc.funcs.write_dpcd = lp_write_dpcd;
++		hdcp_work[i].hdcp.config.ddc.funcs.read_dpcd = lp_read_dpcd;
+ 	}
+ 
+ 	cp_psp->funcs.update_stream_config = update_config;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3865-drm-amd-display-Initialize-HDCP-work-queue.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3865-drm-amd-display-Initialize-HDCP-work-queue.patch
new file mode 100644
index 00000000..8d82b2b8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3865-drm-amd-display-Initialize-HDCP-work-queue.patch
@@ -0,0 +1,104 @@
+From 7449b7794f2bfbf63c8347d2e82175447b17dd87 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 24 May 2019 15:44:20 -0400
+Subject: [PATCH 3865/4256] drm/amd/display: Initialize HDCP work queue
+
+[Why]
+We need this to enable HDCP on linux, as we need events to interact
+with the hdcp module
+
+[How]
+Add work queue to display manager and handle the creation and destruction
+of the queue
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 29 ++++++++++++++++++-
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  3 ++
+ 2 files changed, 31 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index bc6389e13b12..f04b5798ce2c 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -37,6 +37,9 @@
+ #include "amdgpu_ucode.h"
+ #include "atom.h"
+ #include "amdgpu_dm.h"
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++#include "amdgpu_dm_hdcp.h"
++#endif
+ #include "amdgpu_pm.h"
+ 
+ #include "amd_shared.h"
+@@ -644,11 +647,17 @@ void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
+ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ {
+ 	struct dc_init_data init_data;
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++	struct dc_callback_init init_params;
++#endif
+ 	adev->dm.ddev = adev->ddev;
+ 	adev->dm.adev = adev;
+ 
+ 	/* Zero all the fields */
+ 	memset(&init_data, 0, sizeof(init_data));
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++        memset(&init_params, 0, sizeof(init_params));
++#endif
+ 
+ 	mutex_init(&adev->dm.dc_lock);
+ 	mutex_init(&adev->dm.audio_lock);
+@@ -763,7 +772,15 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
+ 	amdgpu_dm_audio_fini(adev);
+ 
+ 	amdgpu_dm_destroy_drm_device(&adev->dm);
+-
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++        if (adev->dm.hdcp_workqueue) {
++                hdcp_destroy(adev->dm.hdcp_workqueue);
++                adev->dm.hdcp_workqueue = NULL;
++       }
++
++        if (adev->dm.dc)
++                dc_deinit_callbacks(adev->dm.dc);
++#endif
+ 	/* DC Destroy TODO: Replace destroy DAL */
+ 	if (adev->dm.dc)
+ 		dc_destroy(&adev->dm.dc);
+@@ -2147,6 +2164,16 @@ amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
+ 		DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
+ }
+ 
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++	adev->dm.hdcp_workqueue = hdcp_create_workqueue(&adev->psp, &init_params.cp_psp, adev->dm.dc);
++
++	if (!adev->dm.hdcp_workqueue)
++		DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
++	else
++		DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
++
++	dc_init_callbacks(adev->dm.dc, &init_params);
++#endif
+ #endif
+ 
+ static int initialize_plane(struct amdgpu_display_manager *dm,
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+index c39ee21c290f..94ab7109447a 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+@@ -219,6 +219,9 @@ struct amdgpu_display_manager {
+ 	struct amdgpu_dm_backlight_caps backlight_caps;
+ 
+ 	struct mod_freesync *freesync_module;
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++	struct hdcp_workqueue *hdcp_workqueue;
++#endif
+ 
+ 	struct drm_atomic_state *cached_state;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3866-drm-amd-display-Handle-Content-protection-property-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3866-drm-amd-display-Handle-Content-protection-property-c.patch
new file mode 100644
index 00000000..213393fc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3866-drm-amd-display-Handle-Content-protection-property-c.patch
@@ -0,0 +1,185 @@
+From b0606e6d078d670cfca992383f5b886cf64d69a2 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Mon, 16 Sep 2019 15:52:58 -0500
+Subject: [PATCH 3866/4256] drm/amd/display: Handle Content protection property
+ changes
+
+[Why]
+We need to manage the content protection property changes for
+different usecase, once cp is DESIRED we need to maintain the
+ENABLED/DESIRED status for different cases.
+
+[How]
+1. Attach the content_protection property
+
+2. HDCP enable (UNDESIRED -> DESIRED)
+	call into the module with the correct parameters to start
+	hdcp. Set cp to ENABLED
+
+3. HDCP disable (ENABLED -> UNDESIRED)
+	Call the module to disable hdcp.
+
+3. Handle Special cases	(Hotplug, S3, headless S3, DPMS)
+	If already ENABLED: set to DESIRED on unplug/suspend/dpms,
+	and disable hdcp
+
+	Then on plugin/resume/dpms: enable HDCP
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 96 +++++++++++++++++++
+ 1 file changed, 96 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index f04b5798ce2c..af7f326c56bd 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -78,6 +78,7 @@
+ 
+ #include "soc15_common.h"
+ #endif
++#include <drm/drm_hdcp.h>
+ 
+ #include "modules/inc/mod_freesync.h"
+ #include "modules/power/power_helpers.h"
+@@ -1459,6 +1460,11 @@ amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
+ 		dc_sink_release(aconnector->dc_sink);
+ 		aconnector->dc_sink = NULL;
+ 		aconnector->edid = NULL;
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++		/* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
++		if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
++			connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
++#endif
+ 	}
+ 
+ 	mutex_unlock(&dev->mode_config.mutex);
+@@ -1473,12 +1479,18 @@ static void handle_hpd_irq(void *param)
+ 	struct drm_connector *connector = &aconnector->base;
+ 	struct drm_device *dev = connector->dev;
+ 	enum dc_connection_type new_connection_type = dc_connection_none;
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++	struct amdgpu_device *adev = dev->dev_private;
++#endif
+ 
+ 	/* In case of failure or MST no need to update connector status or notify the OS
+ 	 * since (for MST case) MST does this in it's own context.
+ 	 */
+ 	mutex_lock(&aconnector->hpd_lock);
+ 
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++	hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
++#endif
+ 	if (aconnector->fake_enable)
+ 		aconnector->fake_enable = false;
+ 
+@@ -5086,6 +5098,9 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
+ 				adev->mode_info.freesync_property, 0);
+ 		drm_object_attach_property(&aconnector->base.base,
+ 				adev->mode_info.freesync_capable_property, 0);
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++		drm_connector_attach_content_protection_property(&aconnector->base, false);
++#endif
+ 	}
+ }
+ 
+@@ -5328,6 +5343,63 @@ is_scaling_state_different(const struct dm_connector_state *dm_state,
+ 	return false;
+ }
+ 
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++static bool is_content_protection_different(struct drm_connector_state *state,
++					    const struct drm_connector_state *old_state,
++					    const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
++{
++	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
++
++	/* CP is being re enabled, ignore this */
++	if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
++	    state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
++		state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
++		return false;
++	}
++
++	/* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED */
++	if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
++	    state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
++		state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
++
++	/* Check if something is connected/enabled, otherwise we start hdcp but nothing is connected/enabled
++	 * hot-plug, headless s3, dpms
++	 */
++	if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && connector->dpms == DRM_MODE_DPMS_ON &&
++	    aconnector->dc_sink != NULL)
++		return true;
++
++	if (old_state->content_protection == state->content_protection)
++		return false;
++
++	if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
++		return true;
++
++	return false;
++}
++
++static void update_content_protection(struct drm_connector_state *state, const struct drm_connector *connector,
++				      struct hdcp_workqueue *hdcp_w)
++{
++	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
++
++	if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
++		hdcp_add_display(hdcp_w, aconnector->dc_link->link_index);
++
++		/*
++		 * TODO: ENABLED should be verified using psp, it is planned later.
++		 * Just set this to ENABLED for now
++		 */
++		state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
++
++		return;
++	}
++
++	if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
++		hdcp_remove_display(hdcp_w, aconnector->dc_link->link_index, aconnector->base.index);
++
++}
++#endif
+ static void remove_stream(struct amdgpu_device *adev,
+ 			  struct amdgpu_crtc *acrtc,
+ 			  struct dc_stream_state *stream)
+@@ -6247,6 +6319,30 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
+ 				acrtc->otg_inst = status->primary_otg_inst;
+ 		}
+ 	}
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
++		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
++		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
++		struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
++
++		new_crtc_state = NULL;
++
++		if (acrtc)
++			new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
++
++		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
++
++		if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
++		    connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
++			hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
++			new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
++			continue;
++		}
++
++		if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
++			update_content_protection(new_con_state, connector, adev->dm.hdcp_workqueue);
++	}
++#endif
+ 
+ 	/* Handle connector state changes */
+ 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3867-drm-amd-display-handle-DP-cpirq.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3867-drm-amd-display-handle-DP-cpirq.patch
new file mode 100644
index 00000000..84808fd9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3867-drm-amd-display-handle-DP-cpirq.patch
@@ -0,0 +1,63 @@
+From 415a500318d3e36fdaf4b8dceba41de1558494b6 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Mon, 10 Jun 2019 16:18:38 -0400
+Subject: [PATCH 3867/4256] drm/amd/display: handle DP cpirq
+
+[Why]
+This is needed for DP as DP can send us info using irq.
+
+[How]
+Check if irq bit is set on short pulse and call the
+function that handles cpirq in amdgpu_dm_hdcp
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index af7f326c56bd..0d017de12f12 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -1609,6 +1609,12 @@ static void handle_hpd_rx_irq(void *param)
+ 	struct dc_link *dc_link = aconnector->dc_link;
+ 	bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
+ 	enum dc_connection_type new_connection_type = dc_connection_none;
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++	union hpd_irq_data hpd_irq_data;
++	struct amdgpu_device *adev = dev->dev_private;
++
++	memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
++#endif
+ 
+ 	/* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
+ 	 * conflict, after implement i2c helper, this mutex should be
+@@ -1617,7 +1623,12 @@ static void handle_hpd_rx_irq(void *param)
+ 	if (dc_link->type != dc_connection_mst_branch)
+ 		mutex_lock(&aconnector->hpd_lock);
+ 
++
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++	if (dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL) &&
++#else
+ 	if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
++#endif
+ 			!is_mst_root_connector) {
+ 		/* Downstream Port status changed. */
+ 		if (!dc_link_detect_sink(dc_link, &new_connection_type))
+@@ -1652,6 +1663,10 @@ static void handle_hpd_rx_irq(void *param)
+ 			drm_kms_helper_hotplug_event(dev);
+ 		}
+ 	}
++#ifdef CONFIG_DRM_AMD_DC_HDCP
++	if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ)
++		hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
++#endif
+ 	if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
+ 	    (dc_link->type == dc_connection_mst_branch))
+ 		dm_handle_hpd_rx_irq(aconnector);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3868-drm-amd-display-Update-CP-property-based-on-HW-query.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3868-drm-amd-display-Update-CP-property-based-on-HW-query.patch
new file mode 100644
index 00000000..a6fc99a3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3868-drm-amd-display-Update-CP-property-based-on-HW-query.patch
@@ -0,0 +1,206 @@
+From e5313f84346649b9c45031f299ae4116d1821570 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Mon, 10 Jun 2019 16:06:05 -0400
+Subject: [PATCH 3868/4256] drm/amd/display: Update CP property based on HW
+ query
+
+[Why]
+We need to use HW state to set content protection to ENABLED.
+This way we know that the link is encrypted from the HW side
+
+[How]
+Create a workqueue that queries the HW every ~2seconds, and sets it to
+ENABLED or DESIRED based on the result from the hardware
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 16 +----
+ .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c    | 65 ++++++++++++++++++-
+ .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.h    |  7 +-
+ 3 files changed, 73 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 0d017de12f12..a6c04f490c48 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -5398,19 +5398,9 @@ static void update_content_protection(struct drm_connector_state *state, const s
+ {
+ 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
+ 
+-	if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
+-		hdcp_add_display(hdcp_w, aconnector->dc_link->link_index);
+-
+-		/*
+-		 * TODO: ENABLED should be verified using psp, it is planned later.
+-		 * Just set this to ENABLED for now
+-		 */
+-		state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
+-
+-		return;
+-	}
+-
+-	if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
++	if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
++		hdcp_add_display(hdcp_w, aconnector->dc_link->link_index, aconnector);
++	else if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
+ 		hdcp_remove_display(hdcp_w, aconnector->dc_link->link_index, aconnector->base.index);
+ 
+ }
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+index 9d11d7695508..2443c238c188 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+@@ -27,6 +27,7 @@
+ #include "amdgpu.h"
+ #include "amdgpu_dm.h"
+ #include "dm_helpers.h"
++#include <drm/drm_hdcp.h>
+ 
+ bool lp_write_i2c(void *handle, uint32_t address, const uint8_t *data, uint32_t size)
+ {
+@@ -82,16 +83,19 @@ static void process_output(struct hdcp_workqueue *hdcp_work)
+ 
+ }
+ 
+-void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index)
++void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index, struct amdgpu_dm_connector *aconnector)
+ {
+ 	struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
+ 	struct mod_hdcp_display *display = &hdcp_work[link_index].display;
+ 	struct mod_hdcp_link *link = &hdcp_work[link_index].link;
+ 
+ 	mutex_lock(&hdcp_w->mutex);
++	hdcp_w->aconnector = aconnector;
+ 
+ 	mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output);
+ 
++	schedule_delayed_work(&hdcp_w->property_validate_dwork, msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
++
+ 	process_output(hdcp_w);
+ 
+ 	mutex_unlock(&hdcp_w->mutex);
+@@ -106,6 +110,9 @@ void hdcp_remove_display(struct hdcp_workqueue *hdcp_work, unsigned int link_ind
+ 
+ 	mod_hdcp_remove_display(&hdcp_w->hdcp, display_index, &hdcp_w->output);
+ 
++	cancel_delayed_work(&hdcp_w->property_validate_dwork);
++	hdcp_w->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
++
+ 	process_output(hdcp_w);
+ 
+ 	mutex_unlock(&hdcp_w->mutex);
+@@ -120,6 +127,9 @@ void hdcp_reset_display(struct hdcp_workqueue *hdcp_work, unsigned int link_inde
+ 
+ 	mod_hdcp_reset_connection(&hdcp_w->hdcp,  &hdcp_w->output);
+ 
++	cancel_delayed_work(&hdcp_w->property_validate_dwork);
++	hdcp_w->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
++
+ 	process_output(hdcp_w);
+ 
+ 	mutex_unlock(&hdcp_w->mutex);
+@@ -155,7 +165,58 @@ static void event_callback(struct work_struct *work)
+ 
+ 
+ }
++static void event_property_update(struct work_struct *work)
++{
++
++	struct hdcp_workqueue *hdcp_work = container_of(work, struct hdcp_workqueue, property_update_work);
++	struct amdgpu_dm_connector *aconnector = hdcp_work->aconnector;
++	struct drm_device *dev = hdcp_work->aconnector->base.dev;
++	long ret;
++
++	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
++	mutex_lock(&hdcp_work->mutex);
++
++
++	if (aconnector->base.state->commit) {
++		ret = wait_for_completion_interruptible_timeout(&aconnector->base.state->commit->hw_done, 10 * HZ);
++
++		if (ret == 0) {
++			DRM_ERROR("HDCP state unknown! Setting it to DESIRED");
++			hdcp_work->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
++		}
++	}
++
++	if (hdcp_work->encryption_status == MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON)
++		drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_ENABLED);
++	else
++		drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_DESIRED);
++
++
++	mutex_unlock(&hdcp_work->mutex);
++	drm_modeset_unlock(&dev->mode_config.connection_mutex);
++}
++
++static void event_property_validate(struct work_struct *work)
++{
++	struct hdcp_workqueue *hdcp_work =
++		container_of(to_delayed_work(work), struct hdcp_workqueue, property_validate_dwork);
++	struct mod_hdcp_display_query query;
++	struct amdgpu_dm_connector *aconnector = hdcp_work->aconnector;
++
++	mutex_lock(&hdcp_work->mutex);
+ 
++	query.encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
++	mod_hdcp_query_display(&hdcp_work->hdcp, aconnector->base.index, &query);
++
++	if (query.encryption_status != hdcp_work->encryption_status) {
++		hdcp_work->encryption_status = query.encryption_status;
++		schedule_work(&hdcp_work->property_update_work);
++	}
++
++	schedule_delayed_work(&hdcp_work->property_validate_dwork, msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
++
++	mutex_unlock(&hdcp_work->mutex);
++}
+ 
+ static void event_watchdog_timer(struct work_struct *work)
+ {
+@@ -250,8 +311,10 @@ struct hdcp_workqueue *hdcp_create_workqueue(void *psp_context, struct cp_psp *c
+ 		mutex_init(&hdcp_work[i].mutex);
+ 
+ 		INIT_WORK(&hdcp_work[i].cpirq_work, event_cpirq);
++		INIT_WORK(&hdcp_work[i].property_update_work, event_property_update);
+ 		INIT_DELAYED_WORK(&hdcp_work[i].callback_dwork, event_callback);
+ 		INIT_DELAYED_WORK(&hdcp_work[i].watchdog_timer_dwork, event_watchdog_timer);
++		INIT_DELAYED_WORK(&hdcp_work[i].property_validate_dwork, event_property_validate);
+ 
+ 		hdcp_work[i].hdcp.config.psp.handle =  psp_context;
+ 		hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i);
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+index cb6c6fbd74f6..d3ba505d0696 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+@@ -38,8 +38,11 @@ struct cp_psp;
+ 
+ struct hdcp_workqueue {
+ 	struct work_struct cpirq_work;
++	struct work_struct property_update_work;
+ 	struct delayed_work callback_dwork;
+ 	struct delayed_work watchdog_timer_dwork;
++	struct delayed_work property_validate_dwork;
++	struct amdgpu_dm_connector *aconnector;
+ 	struct mutex mutex;
+ 
+ 	struct mod_hdcp hdcp;
+@@ -47,10 +50,12 @@ struct hdcp_workqueue {
+ 	struct mod_hdcp_display display;
+ 	struct mod_hdcp_link link;
+ 
++	enum mod_hdcp_encryption_status encryption_status;
+ 	uint8_t max_link;
+ };
+ 
+-void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index);
++void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index,
++		      struct amdgpu_dm_connector *aconnector);
+ void hdcp_remove_display(struct hdcp_workqueue *work, unsigned int link_index, unsigned int display_index);
+ void hdcp_reset_display(struct hdcp_workqueue *work, unsigned int link_index);
+ void hdcp_handle_cpirq(struct hdcp_workqueue *work, unsigned int link_index);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3869-drm-amd-display-only-enable-HDCP-for-DCN.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3869-drm-amd-display-only-enable-HDCP-for-DCN.patch
new file mode 100644
index 00000000..d11b6447
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3869-drm-amd-display-only-enable-HDCP-for-DCN.patch
@@ -0,0 +1,65 @@
+From 6dbbd6d36510f31626a1cb59db68bbdcf8c92535 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Mon, 24 Jun 2019 14:54:13 -0400
+Subject: [PATCH 3869/4256] drm/amd/display: only enable HDCP for DCN+
+
+[Why]
+We don't support HDCP for pre RAVEN asics
+
+[How]
+Check if we are RAVEN+. Use this to attach the content_protection
+property, this way usermode can't try to enable HDCP on pre DCN asics.
+
+Also we need to update the module on hpd so guard it aswell
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c    | 16 ++++------------
+ 1 file changed, 4 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index a6c04f490c48..05eb21d76cc6 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -1489,7 +1489,8 @@ static void handle_hpd_irq(void *param)
+ 	mutex_lock(&aconnector->hpd_lock);
+ 
+ #ifdef CONFIG_DRM_AMD_DC_HDCP
+-	hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
++	if (adev->asic_type >= CHIP_RAVEN)
++		hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
+ #endif
+ 	if (aconnector->fake_enable)
+ 		aconnector->fake_enable = false;
+@@ -2191,16 +2192,6 @@ amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
+ 		DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
+ }
+ 
+-#ifdef CONFIG_DRM_AMD_DC_HDCP
+-	adev->dm.hdcp_workqueue = hdcp_create_workqueue(&adev->psp, &init_params.cp_psp, adev->dm.dc);
+-
+-	if (!adev->dm.hdcp_workqueue)
+-		DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
+-	else
+-		DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
+-
+-	dc_init_callbacks(adev->dm.dc, &init_params);
+-#endif
+ #endif
+ 
+ static int initialize_plane(struct amdgpu_display_manager *dm,
+@@ -5114,7 +5105,8 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
+ 		drm_object_attach_property(&aconnector->base.base,
+ 				adev->mode_info.freesync_capable_property, 0);
+ #ifdef CONFIG_DRM_AMD_DC_HDCP
+-		drm_connector_attach_content_protection_property(&aconnector->base, false);
++		if (adev->asic_type >= CHIP_RAVEN)
++			drm_connector_attach_content_protection_property(&aconnector->base, false);
+ #endif
+ 	}
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3870-drm-amd-display-Add-hdcp-to-Kconfig.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3870-drm-amd-display-Add-hdcp-to-Kconfig.patch
new file mode 100644
index 00000000..d5d1a8ae
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3870-drm-amd-display-Add-hdcp-to-Kconfig.patch
@@ -0,0 +1,41 @@
+From 637475ed62eba7486f2a3781d22c2bf0bd1179ba Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 7 Aug 2019 11:23:30 -0400
+Subject: [PATCH 3870/4256] drm/amd/display: Add hdcp to Kconfig
+
+[Why]
+HDCP is not fully finished, so we need to be able to
+build and run the driver without it.
+
+[How]
+Add a Kconfig to toggle it
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/Kconfig | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
+index 8154fd637afb..b4504257873a 100644
+--- a/drivers/gpu/drm/amd/display/Kconfig
++++ b/drivers/gpu/drm/amd/display/Kconfig
+@@ -43,6 +43,14 @@ config DRM_AMD_DC_DSC_SUPPORT
+ 	    Choose this option if you want to have
+ 	    Dynamic Stream Compression support
+ 
++config DRM_AMD_DC_HDCP
++        bool "Enable HDCP support in DC"
++        depends on DRM_AMD_DC
++        help
++         Choose this option
++         if you want to support
++         HDCP authentication
++
+ config DEBUG_KERNEL_DC
+ 	bool "Enable kgdb break in DC"
+ 	depends on DRM_AMD_DC
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3871-drm-amdkfd-Delete-unused-KFD_IS_-macro.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3871-drm-amdkfd-Delete-unused-KFD_IS_-macro.patch
new file mode 100644
index 00000000..47a16a04
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3871-drm-amdkfd-Delete-unused-KFD_IS_-macro.patch
@@ -0,0 +1,33 @@
+From 4a27cb55c08daadc17ec3b7c23247770566f3562 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Mon, 16 Sep 2019 12:24:38 -0400
+Subject: [PATCH 3871/4256] drm/amdkfd: Delete unused KFD_IS_* macro
+
+These were deleted before, but somehow showed up again. Delete them again.
+
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index b0965eaa327e..6bf5be992303 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -195,10 +195,6 @@ enum cache_policy {
+ 	cache_policy_noncoherent
+ };
+ 
+-#define KFD_IS_VI(chip) ((chip) >= CHIP_CARRIZO && (chip) <= CHIP_POLARIS11)
+-#define KFD_IS_DGPU(chip) (((chip) >= CHIP_TONGA && \
+-			   (chip) <= CHIP_NAVI10) || \
+-			   (chip) == CHIP_HAWAII)
+ #define KFD_IS_SOC15(chip) ((chip) >= CHIP_VEGA10)
+ 
+ struct kfd_event_interrupt_class {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3872-drm-amdgpu-vm-fix-documentation-for-amdgpu_vm_bo_par.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3872-drm-amdgpu-vm-fix-documentation-for-amdgpu_vm_bo_par.patch
new file mode 100644
index 00000000..eb028014
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3872-drm-amdgpu-vm-fix-documentation-for-amdgpu_vm_bo_par.patch
@@ -0,0 +1,34 @@
+From 036bd39a269d2429eddb832122145e0dae1a12e3 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 16 Sep 2019 13:21:32 -0500
+Subject: [PATCH 3872/4256] drm/amdgpu/vm: fix documentation for
+ amdgpu_vm_bo_param
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add new parameters.
+
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 604689385713..91b11c765921 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -822,6 +822,8 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
+  *
+  * @adev: amdgpu_device pointer
+  * @vm: requesting vm
++ * @level: the page table level
++ * @direct: use a direct update
+  * @bp: resulting BO allocation parameters
+  */
+ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3873-docs-drm-amdgpu-Resolve-build-warnings.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3873-docs-drm-amdgpu-Resolve-build-warnings.patch
new file mode 100644
index 00000000..047cc51f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3873-docs-drm-amdgpu-Resolve-build-warnings.patch
@@ -0,0 +1,130 @@
+From 38f1540d3f4c2cfccab7906361a6a9cd09c5e749 Mon Sep 17 00:00:00 2001
+From: Adam Zerella <adam.zerella@gmail.com>
+Date: Sat, 14 Sep 2019 22:56:16 +1000
+Subject: [PATCH 3873/4256] docs: drm/amdgpu: Resolve build warnings
+
+Some of the documentation formatting could be improved
+which will resolve some Sphinx amdgpu build warnings e.g
+
+WARNING: Unexpected indentation.
+WARNING: Block quote ends without a blank line; unexpected unindent.
+WARNING: Inline emphasis start-string without end-string.
+
+Signed-off-by: Adam Zerella <adam.zerella@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 11 ++++---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c  |  4 +--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 44 +++++++++++++++----------
+ 3 files changed, 35 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index f1def7d9af2b..56ecebdcddc2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -248,10 +248,13 @@ module_param_named(msi, amdgpu_msi, int, 0444);
+  *
+  * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
+  * multiple values specified. 0 and negative values are invalidated. They will be adjusted
+- * to default timeout.
+- *  - With one value specified, the setting will apply to all non-compute jobs.
+- *  - With multiple values specified, the first one will be for GFX. The second one is for Compute.
+- *    And the third and fourth ones are for SDMA and Video.
++ * to the default timeout.
++ *
++ * - With one value specified, the setting will apply to all non-compute jobs.
++ * - With multiple values specified, the first one will be for GFX.
++ *   The second one is for Compute. The third and fourth ones are
++ *   for SDMA and Video.
++ *
+  * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
+  * jobs is 10000. And there is no timeout enforced on compute jobs.
+  */
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index 7842beea7d91..5cf8d72e3859 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -2193,9 +2193,9 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
+  *
+  * - fan1_input: fan speed in RPM
+  *
+- * - fan[1-*]_target: Desired fan speed Unit: revolution/min (RPM)
++ * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
+  *
+- * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
++ * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
+  *
+  * hwmon interfaces for GPU clocks:
+  *
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 0a90e5cb3ca4..01356a449160 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -220,29 +220,36 @@ static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
+  *
+  * Second member: struct ras_debug_if::op.
+  * It has three kinds of operations.
+- *  0: disable RAS on the block. Take ::head as its data.
+- *  1: enable RAS on the block. Take ::head as its data.
+- *  2: inject errors on the block. Take ::inject as its data.
++ *
++ * - 0: disable RAS on the block. Take ::head as its data.
++ * - 1: enable RAS on the block. Take ::head as its data.
++ * - 2: inject errors on the block. Take ::inject as its data.
+  *
+  * How to use the interface?
+  * programs:
+  * copy the struct ras_debug_if in your codes and initialize it.
+  * write the struct to the control node.
+  *
+- * bash:
+- * echo op block [error [sub_blcok address value]] > .../ras/ras_ctrl
+- *	op: disable, enable, inject
+- *		disable: only block is needed
+- *		enable: block and error are needed
+- *		inject: error, address, value are needed
+- *	block: umc, smda, gfx, .........
+- *		see ras_block_string[] for details
+- *	error: ue, ce
+- *		ue: multi_uncorrectable
+- *		ce: single_correctable
+- *	sub_block: sub block index, pass 0 if there is no sub block
++ * .. code-block:: bash
++ *
++ *	echo op block [error [sub_blcok address value]] > .../ras/ras_ctrl
++ *
++ * op: disable, enable, inject
++ *	disable: only block is needed
++ *	enable: block and error are needed
++ *	inject: error, address, value are needed
++ * block: umc, smda, gfx, .........
++ *	see ras_block_string[] for details
++ * error: ue, ce
++ *	ue: multi_uncorrectable
++ *	ce: single_correctable
++ * sub_block:
++ *	sub block index, pass 0 if there is no sub block
++ *
++ * here are some examples for bash commands:
++ *
++ * .. code-block:: bash
+  *
+- * here are some examples for bash commands,
+  *	echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
+  *	echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
+  *	echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
+@@ -255,8 +262,9 @@ static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
+  * For inject, please check corresponding err count at
+  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
+  *
+- * NOTE: operation is only allowed on blocks which are supported.
+- * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask
++ * .. note::
++ *	Operation is only allowed on blocks which are supported.
++ *	Please check ras mask at /sys/module/amdgpu/parameters/ras_mask
+  */
+ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
+ 		size_t size, loff_t *pos)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3874-drm-amdgpu-add-navi12-pci-id.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3874-drm-amdgpu-add-navi12-pci-id.patch
new file mode 100644
index 00000000..98736830
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3874-drm-amdgpu-add-navi12-pci-id.patch
@@ -0,0 +1,31 @@
+From 5ba66c3e55eef6acdc20ca3af3cb414551c3dcbd Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Tue, 17 Sep 2019 10:35:34 +0800
+Subject: [PATCH 3874/4256] drm/amdgpu: add navi12 pci id
+
+Add Navi12 PCI id support.
+
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 56ecebdcddc2..23ef849ee51c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1073,6 +1073,9 @@ static const struct pci_device_id pciidlist[] = {
+ 	/* Navi12 */
+ 	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
+ 
++	/* Navi12 */
++	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
++
+ 	{0, 0, 0}
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3875-drm-amdgpu-use-GPU-PAGE-SHIFT-for-umc-retired-page.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3875-drm-amdgpu-use-GPU-PAGE-SHIFT-for-umc-retired-page.patch
new file mode 100644
index 00000000..fc076424
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3875-drm-amdgpu-use-GPU-PAGE-SHIFT-for-umc-retired-page.patch
@@ -0,0 +1,31 @@
+From c1389b6b1bd53ddd37ef57ac0d356f29fabad78d Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Tue, 17 Sep 2019 11:36:05 +0800
+Subject: [PATCH 3875/4256] drm/amdgpu: use GPU PAGE SHIFT for umc retired page
+
+umc retired page belongs to vram and it should be aligned to gpu page
+size
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+index 1c0da32c1561..47c4b96b14d1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+@@ -213,7 +213,7 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
+ 				== 1) {
+ 			err_rec->address = err_addr;
+ 			/* page frame address is saved */
+-			err_rec->retired_page = retired_page >> PAGE_SHIFT;
++			err_rec->retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT;
+ 			err_rec->ts = (uint64_t)ktime_get_real_seconds();
+ 			err_rec->err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
+ 			err_rec->cu = 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3876-drm-amdgpu-discovery-get-gpu-info-from-ip-discovery-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3876-drm-amdgpu-discovery-get-gpu-info-from-ip-discovery-.patch
new file mode 100644
index 00000000..baeb5441
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3876-drm-amdgpu-discovery-get-gpu-info-from-ip-discovery-.patch
@@ -0,0 +1,56 @@
+From 8a12889f0ce2da6b07c27f117b89a16eb0622dac Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 11 Sep 2019 11:41:05 +0800
+Subject: [PATCH 3876/4256] drm/amdgpu/discovery: get gpu info from ip
+ discovery table
+
+except soc_bounding_box which is not integrated in discovery table yet
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 63ec56c38bd8..6df43bc6dc5e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1471,6 +1471,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
+ 			(const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
+ 								le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+ 
++		if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
++			goto parse_soc_bounding_box;
++
+ 		adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
+ 		adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
+ 		adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
+@@ -1498,7 +1501,13 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
+ 			adev->gfx.config.num_packer_per_sc =
+ 				le32_to_cpu(gpu_info_fw->num_packer_per_sc);
+ 		}
++
++parse_soc_bounding_box:
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
++		/*
++		 * soc bounding box info is not integrated in disocovery table,
++		 * we always need to parse it from gpu info firmware.
++		 */
+ 		if (hdr->version_minor == 2) {
+ 			const struct gpu_info_firmware_v1_2 *gpu_info_fw =
+ 				(const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
+@@ -1615,6 +1624,9 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
+ 	if (r)
+ 		return r;
+ 
++	if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
++		amdgpu_discovery_get_gfx_info(adev);
++
+ 	amdgpu_amdkfd_device_probe(adev);
+ 
+ 	if (amdgpu_sriov_vf(adev)) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3877-drm-amdgpu-do-not-init-mec2-jt-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3877-drm-amdgpu-do-not-init-mec2-jt-for-renoir.patch
new file mode 100644
index 00000000..adf65e5d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3877-drm-amdgpu-do-not-init-mec2-jt-for-renoir.patch
@@ -0,0 +1,53 @@
+From a0c73b31b3802cae76bb4c0ac73b97359ba75909 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 18 Sep 2019 06:46:54 +0800
+Subject: [PATCH 3877/4256] drm/amdgpu: do not init mec2 jt for renoir
+
+For ASICs like renoir/arct, driver doesn't need to load mec2 jt.
+when mec1 jt is loaded, mec2 jt will be loaded automatically
+since the write is actaully broadcasted to both.
+
+We need to more time to test other gfx9 asic. but for now we should
+be able to draw conclusion that mec2 jt is not needed for renoir and
+arct.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ----
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 3 ++-
+ 2 files changed, 2 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index f09d8cc6e557..1963e11a37c0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1399,10 +1399,6 @@ static int psp_np_fw_load(struct psp_context *psp)
+ 		     ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
+ 			/* skip mec JT when autoload is enabled */
+ 			continue;
+-		/* Renoir only needs to load mec jump table one time */
+-		if (adev->asic_type == CHIP_RENOIR &&
+-		    ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)
+-			continue;
+ 
+ 		psp_print_fw_hdr(psp, ucode);
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 08f5ca346d71..946e21869a8e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -1320,7 +1320,8 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev,
+ 
+ 			/* TODO: Determine if MEC2 JT FW loading can be removed
+ 				 for all GFX V9 asic and above */
+-			if (adev->asic_type != CHIP_ARCTURUS) {
++			if (adev->asic_type != CHIP_ARCTURUS &&
++			    adev->asic_type != CHIP_RENOIR) {
+ 				info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
+ 				info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
+ 				info->fw = adev->gfx.mec2_fw;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3878-drm-amdgpu-powerplay-add-new-mapping-for-APCC_DFLL-f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3878-drm-amdgpu-powerplay-add-new-mapping-for-APCC_DFLL-f.patch
new file mode 100644
index 00000000..daf4824c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3878-drm-amdgpu-powerplay-add-new-mapping-for-APCC_DFLL-f.patch
@@ -0,0 +1,42 @@
+From c66330ecd7624e7744d67b2d139345204fadbb35 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 11 Sep 2019 19:09:27 +0800
+Subject: [PATCH 3878/4256] drm/amdgpu/powerplay: add new mapping for APCC_DFLL
+ feature
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 1 +
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+index ab8c92a60fc4..12a1de55ce3c 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+@@ -252,6 +252,7 @@ enum smu_clk_type {
+        __SMU_DUMMY_MAP(TEMP_DEPENDENT_VMIN),           	\
+        __SMU_DUMMY_MAP(MMHUB_PG),                      	\
+        __SMU_DUMMY_MAP(ATHUB_PG),                      	\
++       __SMU_DUMMY_MAP(APCC_DFLL),                     	\
+        __SMU_DUMMY_MAP(WAFL_CG),
+ 
+ #undef __SMU_DUMMY_MAP
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 16634e657589..5a34d01f7f7c 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -176,6 +176,7 @@ static struct smu_11_0_cmn2aisc_mapping navi10_feature_mask_map[SMU_FEATURE_COUN
+ 	FEA_MAP(TEMP_DEPENDENT_VMIN),
+ 	FEA_MAP(MMHUB_PG),
+ 	FEA_MAP(ATHUB_PG),
++	FEA_MAP(APCC_DFLL),
+ };
+ 
+ static struct smu_11_0_cmn2aisc_mapping navi10_table_map[SMU_TABLE_COUNT] = {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3879-drm-amdgpu-avoid-null-pointer-dereference.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3879-drm-amdgpu-avoid-null-pointer-dereference.patch
new file mode 100644
index 00000000..e73baf74
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3879-drm-amdgpu-avoid-null-pointer-dereference.patch
@@ -0,0 +1,37 @@
+From 6c627cce3729c676e557d56d14ab17386c916f87 Mon Sep 17 00:00:00 2001
+From: Guchun Chen <guchun.chen@amd.com>
+Date: Tue, 17 Sep 2019 17:49:29 +0800
+Subject: [PATCH 3879/4256] drm/amdgpu: avoid null pointer dereference
+
+null ptr should be checked first to avoid null ptr access
+
+Signed-off-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 01356a449160..f5aea49f2ab3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1409,13 +1409,13 @@ static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
+ {
+ 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+ 	struct ras_err_handler_data *data;
+-	struct amdgpu_ras_eeprom_control *control =
+-					&adev->psp.ras.ras->eeprom_control;
++	struct amdgpu_ras_eeprom_control *control;
+ 	int save_count;
+ 
+ 	if (!con || !con->eh_data)
+ 		return 0;
+ 
++	control = &con->eeprom_control;
+ 	data = con->eh_data;
+ 	save_count = data->count - control->num_recs;
+ 	/* only new entries are saved */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3880-drm-amdgpu-remove-redundant-variable-definition.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3880-drm-amdgpu-remove-redundant-variable-definition.patch
new file mode 100644
index 00000000..43e30bf2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3880-drm-amdgpu-remove-redundant-variable-definition.patch
@@ -0,0 +1,57 @@
+From 620f5965dce235f739ef381f6a45ef683e35294b Mon Sep 17 00:00:00 2001
+From: Guchun Chen <guchun.chen@amd.com>
+Date: Wed, 18 Sep 2019 11:33:19 +0800
+Subject: [PATCH 3880/4256] drm/amdgpu: remove redundant variable definition
+
+No need to define the same variables in each loop of the function.
+
+Signed-off-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 15 ++++++++-------
+ 1 file changed, 8 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+index d0e020ef73e3..20af0a17d00b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+@@ -359,8 +359,9 @@ int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
+ 					    int num)
+ {
+ 	int i, ret = 0;
+-	struct i2c_msg *msgs;
+-	unsigned char *buffs;
++	struct i2c_msg *msgs, *msg;
++	unsigned char *buffs, *buff;
++	struct eeprom_table_record *record;
+ 	struct amdgpu_device *adev = to_amdgpu_device(control);
+ 
+ 	if (adev->asic_type != CHIP_VEGA20)
+@@ -390,9 +391,9 @@ int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
+ 	 * 256b
+ 	 */
+ 	for (i = 0; i < num; i++) {
+-		unsigned char *buff = &buffs[i * (EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
+-		struct eeprom_table_record *record = &records[i];
+-		struct i2c_msg *msg = &msgs[i];
++		buff = &buffs[i * (EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
++		record = &records[i];
++		msg = &msgs[i];
+ 
+ 		control->next_addr = __correct_eeprom_dest_address(control->next_addr);
+ 
+@@ -432,8 +433,8 @@ int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
+ 
+ 	if (!write) {
+ 		for (i = 0; i < num; i++) {
+-			unsigned char *buff = &buffs[i*(EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
+-			struct eeprom_table_record *record = &records[i];
++			buff = &buffs[i*(EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
++			record = &records[i];
+ 
+ 			__decode_table_record_from_buff(control, record, buff + EEPROM_ADDRESS_SIZE);
+ 		}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3881-drm-amdgpu-psp-flush-HDP-write-fifo-after-submitting.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3881-drm-amdgpu-psp-flush-HDP-write-fifo-after-submitting.patch
new file mode 100644
index 00000000..2b02af2f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3881-drm-amdgpu-psp-flush-HDP-write-fifo-after-submitting.patch
@@ -0,0 +1,69 @@
+From bb2dccc1156971611b25b5d7e9a877cca31118fc Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 17 Sep 2019 15:12:18 -0500
+Subject: [PATCH 3881/4256] drm/amdgpu/psp: flush HDP write fifo after
+ submitting cmds to the psp
+
+We need to make sure the fifo is flushed before we ask the psp to
+process the commands.
+
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 1 +
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 1 +
+ drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 1 +
+ drivers/gpu/drm/amd/amdgpu/psp_v3_1.c  | 1 +
+ 4 files changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+index 6dec5fbc2678..f24760dab4e0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+@@ -263,6 +263,7 @@ static int psp_v10_0_cmd_submit(struct psp_context *psp,
+ 	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
+ 	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
+ 	write_frame->fence_value = index;
++	amdgpu_asic_flush_hdp(adev, NULL);
+ 
+ 	/* Update the write Pointer in DWORDs */
+ 	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index 54de388ae114..f5bc9c176e7b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -557,6 +557,7 @@ static int psp_v11_0_cmd_submit(struct psp_context *psp,
+ 	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
+ 	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
+ 	write_frame->fence_value = index;
++	amdgpu_asic_flush_hdp(adev, NULL);
+ 
+ 	/* Update the write Pointer in DWORDs */
+ 	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+index c72e43f8e0be..8f553f6f92d6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+@@ -378,6 +378,7 @@ static int psp_v12_0_cmd_submit(struct psp_context *psp,
+ 	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
+ 	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
+ 	write_frame->fence_value = index;
++	amdgpu_asic_flush_hdp(adev, NULL);
+ 
+ 	/* Update the write Pointer in DWORDs */
+ 	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+index 4a02058682f5..f652241aa71a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+@@ -452,6 +452,7 @@ static int psp_v3_1_cmd_submit(struct psp_context *psp,
+ 	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
+ 	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
+ 	write_frame->fence_value = index;
++	amdgpu_asic_flush_hdp(adev, NULL);
+ 
+ 	/* Update the write Pointer in DWORDs */
+ 	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3882-drm-amdgpu-psp-invalidate-the-hdp-read-cache-before-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3882-drm-amdgpu-psp-invalidate-the-hdp-read-cache-before-.patch
new file mode 100644
index 00000000..32557234
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3882-drm-amdgpu-psp-invalidate-the-hdp-read-cache-before-.patch
@@ -0,0 +1,34 @@
+From b03a12685ba130cb9b05666da51fcdbe709c7fa6 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 17 Sep 2019 15:17:41 -0500
+Subject: [PATCH 3882/4256] drm/amdgpu/psp: invalidate the hdp read cache
+ before reading the psp response
+
+Otherwise we may get stale data.
+
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 1963e11a37c0..d3444f24647e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -151,10 +151,12 @@ psp_cmd_submit_buf(struct psp_context *psp,
+                 return ret;
+         }
+ 
++	amdgpu_asic_invalidate_hdp(psp->adev, NULL);
+ 	while (*((unsigned int *)psp->fence_buf) != index) {
+                 if (--timeout == 0)
+ 			break;
+ 		msleep(1);
++		amdgpu_asic_invalidate_hdp(psp->adev, NULL);
+ 	}
+ 	
+ 	/* In some cases, psp response status is not 0 even there is no
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3883-drm-amdgpu-flag-navi12-and-14-as-experimental-for-5..patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3883-drm-amdgpu-flag-navi12-and-14-as-experimental-for-5..patch
new file mode 100644
index 00000000..150fb492
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3883-drm-amdgpu-flag-navi12-and-14-as-experimental-for-5..patch
@@ -0,0 +1,43 @@
+From 53fab8774cf1864ba54a7d0629a606ec98a10283 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 17 Sep 2019 14:49:53 -0500
+Subject: [PATCH 3883/4256] drm/amdgpu: flag navi12 and 14 as experimental for
+ 5.4
+
+We can remove this later as things get closer to launch.
+
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 23ef849ee51c..8471c11fa5e1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1063,9 +1063,9 @@ static const struct pci_device_id pciidlist[] = {
+ 	{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
+ 	{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
+ 	/* Navi14 */
+-	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
+-	{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
+-	{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
++	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
++	{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
++	{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
+ 
+ 	/* Renoir */
+ 	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
+@@ -1074,7 +1074,7 @@ static const struct pci_device_id pciidlist[] = {
+ 	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
+ 
+ 	/* Navi12 */
+-	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
++	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT},
+ 
+ 	{0, 0, 0}
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3884-drm-amdgpu-gfx10-update-gfx-golden-settings.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3884-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
new file mode 100644
index 00000000..6c8e10ef
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3884-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
@@ -0,0 +1,31 @@
+From f752bbc3da9d8933f38ad645cf5e4057b37d7f9a Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Thu, 22 Aug 2019 15:00:08 +0800
+Subject: [PATCH 3884/4256] drm/amdgpu/gfx10: update gfx golden settings
+
+update registers: mmUTCL1_CTRL
+
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index ecfda0602456..c427b6f5f00a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -123,7 +123,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1[] =
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
+-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
+ };
+ 
+ static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3885-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3885-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
new file mode 100644
index 00000000..549ae32b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3885-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
@@ -0,0 +1,32 @@
+From 5f585b743b2a15aea8447c4dcfa07bc806eb284a Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Thu, 22 Aug 2019 15:09:29 +0800
+Subject: [PATCH 3885/4256] drm/amdgpu/gfx10: update gfx golden settings for
+ navi14
+
+update registers: mmUTCL1_CTRL
+
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index c427b6f5f00a..afe94b027112 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -167,7 +167,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
+-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
+ };
+ 
+ static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3886-drm-amdgpu-SRIOV-add-navi12-pci-id-for-SRIOV-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3886-drm-amdgpu-SRIOV-add-navi12-pci-id-for-SRIOV-v2.patch
new file mode 100644
index 00000000..321aed81
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3886-drm-amdgpu-SRIOV-add-navi12-pci-id-for-SRIOV-v2.patch
@@ -0,0 +1,31 @@
+From 4c38443b06be87316949ef1f5e26bdf81219dcaf Mon Sep 17 00:00:00 2001
+From: Jiange Zhao <Jiange.Zhao@amd.com>
+Date: Thu, 19 Sep 2019 13:22:59 -0500
+Subject: [PATCH 3886/4256] drm/amdgpu/SRIOV: add navi12 pci id for SRIOV (v2)
+
+Add Navi12 PCI id support.
+
+v2: flag as experimental for now (Alex)
+
+Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 8471c11fa5e1..952ed019fb22 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1075,6 +1075,7 @@ static const struct pci_device_id pciidlist[] = {
+ 
+ 	/* Navi12 */
+ 	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT},
++	{0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT},
+ 
+ 	{0, 0, 0}
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3887-drm-amdgpu-enable-full-ras-by-default.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3887-drm-amdgpu-enable-full-ras-by-default.patch
new file mode 100644
index 00000000..6b20c89f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3887-drm-amdgpu-enable-full-ras-by-default.patch
@@ -0,0 +1,31 @@
+From 6256d95ecda85f154de54ac0bf61da76a17446f7 Mon Sep 17 00:00:00 2001
+From: Guchun Chen <guchun.chen@amd.com>
+Date: Thu, 19 Sep 2019 11:08:58 +0800
+Subject: [PATCH 3887/4256] drm/amdgpu: enable full ras by default
+
+Enable full ras by default, user does not need to enable it by
+boot parameter.
+
+Signed-off-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 952ed019fb22..355aa4221a88 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -155,7 +155,7 @@ struct amdgpu_mgpu_info mgpu_info = {
+ 	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
+ };
+ int amdgpu_ras_enable = -1;
+-uint amdgpu_ras_mask = 0xfffffffb;
++uint amdgpu_ras_mask = 0xffffffff;
+ 
+ /**
+  * DOC: vramlimit (int)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3888-drm-amdgpu-remove-excess-function-parameter-descript.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3888-drm-amdgpu-remove-excess-function-parameter-descript.patch
new file mode 100644
index 00000000..3df04e68
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3888-drm-amdgpu-remove-excess-function-parameter-descript.patch
@@ -0,0 +1,43 @@
+From 698b83a1f206e311edb5f675c8a4fb2fcad704ab Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Thu, 19 Sep 2019 22:09:09 +0800
+Subject: [PATCH 3888/4256] drm/amdgpu: remove excess function parameter
+ description
+
+Fixes gcc warning:
+
+drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:431: warning: Excess function
+parameter 'sw' description in 'vcn_v2_5_disable_clock_gating'
+drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:550: warning: Excess function
+parameter 'sw' description in 'vcn_v2_5_enable_clock_gating'
+
+Fixes: cbead2bdfcf1 ("drm/amdgpu: add VCN2.5 VCPU start and stop")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index 247cf7e71e1b..22e4644521dc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -423,7 +423,6 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
+  * vcn_v2_5_disable_clock_gating - disable VCN clock gating
+  *
+  * @adev: amdgpu_device pointer
+- * @sw: enable SW clock gating
+  *
+  * Disable clock gating for VCN block
+  */
+@@ -542,7 +541,6 @@ static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
+  * vcn_v2_5_enable_clock_gating - enable VCN clock gating
+  *
+  * @adev: amdgpu_device pointer
+- * @sw: enable SW clock gating
+  *
+  * Enable clock gating for VCN block
+  */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3889-Revert-drm-amdgpu-enable-full-ras-by-default.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3889-Revert-drm-amdgpu-enable-full-ras-by-default.patch
new file mode 100644
index 00000000..a73bb6f5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3889-Revert-drm-amdgpu-enable-full-ras-by-default.patch
@@ -0,0 +1,31 @@
+From 8b4749062c4ff4a998c1004cf52b862daf6ecc77 Mon Sep 17 00:00:00 2001
+From: Rui Teng <rui.teng@amd.com>
+Date: Thu, 26 Sep 2019 17:13:38 +0800
+Subject: [PATCH 3889/4256] Revert "drm/amdgpu: enable full ras by default"
+
+This reverts commit 5e6ebea39014345b35e1751fa1ca687e3315a2aa.
+
+The original patch will cause kfdtest failed on mi50 and mi60.
+
+Change-Id: Idef24a8dc6318a30b2c212f0c615c5ec8239d1a4
+Signed-off-by: Rui Teng <rui.teng@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 355aa4221a88..952ed019fb22 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -155,7 +155,7 @@ struct amdgpu_mgpu_info mgpu_info = {
+ 	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
+ };
+ int amdgpu_ras_enable = -1;
+-uint amdgpu_ras_mask = 0xffffffff;
++uint amdgpu_ras_mask = 0xfffffffb;
+ 
+ /**
+  * DOC: vramlimit (int)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3890-drm-amd-display-Restore-backlight-brightness-after-s.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3890-drm-amd-display-Restore-backlight-brightness-after-s.patch
new file mode 100644
index 00000000..23523b6b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3890-drm-amd-display-Restore-backlight-brightness-after-s.patch
@@ -0,0 +1,39 @@
+From e134bf7296d335ed5a1f3ac332eb766057bfd866 Mon Sep 17 00:00:00 2001
+From: Kai-Heng Feng <kai.heng.feng@canonical.com>
+Date: Mon, 2 Sep 2019 16:33:42 +0800
+Subject: [PATCH 3890/4256] drm/amd/display: Restore backlight brightness after
+ system resume
+
+Laptops with AMD APU doesn't restore display backlight brightness after
+system resume.
+
+This issue started when DC was introduced.
+
+Let's use BL_CORE_SUSPENDRESUME so the backlight core calls
+update_status callback after system resume to restore the backlight
+level.
+
+Tested on Dell Inspiron 3180 (Stoney Ridge) and Dell Latitude 5495
+(Raven Ridge).
+
+Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 05eb21d76cc6..3e75028529d1 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -2161,6 +2161,7 @@ static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
+ }
+ 
+ static const struct backlight_ops amdgpu_dm_backlight_ops = {
++	.options = BL_CORE_SUSPENDRESUME,
+ 	.get_brightness = amdgpu_dm_backlight_get_brightness,
+ 	.update_status	= amdgpu_dm_backlight_update_status,
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3891-drm-amd-display-hide-an-unused-variable.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3891-drm-amd-display-hide-an-unused-variable.patch
new file mode 100644
index 00000000..77918102
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3891-drm-amd-display-hide-an-unused-variable.patch
@@ -0,0 +1,37 @@
+From 94d010a7b2d46f79be1b805ece7ecd7d6188cdb3 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Wed, 18 Sep 2019 21:53:58 +0200
+Subject: [PATCH 3891/4256] drm/amd/display: hide an unused variable
+
+Without CONFIG_DEBUG_FS, we get a warning for an unused
+variable:
+
+drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:6020:33: error: unused variable 'source' [-Werror,-Wunused-variable]
+
+Hide the variable in an #ifdef like its only users.
+
+Fixes: 14b2584636c6 ("drm/amd/display: add functionality to grab DPRX CRC entries.")
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 3e75028529d1..3014fbe98c67 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -6890,7 +6890,9 @@ static bool should_reset_plane(struct drm_atomic_state *state,
+ 	struct drm_plane_state *old_other_state, *new_other_state;
+ 	struct drm_crtc_state *new_crtc_state;
+ 	int i;
++#ifdef CONFIG_DEBUG_FS
+ 	enum amdgpu_dm_pipe_crc_source source;
++#endif
+ 
+ 	/*
+ 	 * TODO: Remove this hack once the checks below are sufficient
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3892-drm-amd-display-Fix-kernel-doc-warnings.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3892-drm-amd-display-Fix-kernel-doc-warnings.patch
new file mode 100644
index 00000000..622cf4dd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3892-drm-amd-display-Fix-kernel-doc-warnings.patch
@@ -0,0 +1,88 @@
+From be64b0cd6f17106e8dcd27cd5ab7e3059255fd2e Mon Sep 17 00:00:00 2001
+From: Harry Wentland <harry.wentland@amd.com>
+Date: Wed, 18 Sep 2019 11:42:59 -0400
+Subject: [PATCH 3892/4256] drm/amd/display; Fix kernel doc warnings
+
+We had a couple of missing definitions and formatting errors.
+
+v2: Fix 'notifying' type
+
+Signed-off-by: Harry Wentland <harry.wentland@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 ++++++++++++++
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 10 +++++++++-
+ 2 files changed, 23 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 3014fbe98c67..2f80fb927888 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -266,6 +266,13 @@ static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
+ 	       dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
+ }
+ 
++/**
++ * dm_pflip_high_irq() - Handle pageflip interrupt
++ * @interrupt_params: ignored
++ *
++ * Handles the pageflip interrupt by notifying all interested parties
++ * that the pageflip has been completed.
++ */
+ static void dm_pflip_high_irq(void *interrupt_params)
+ {
+ 	struct amdgpu_crtc *amdgpu_crtc;
+@@ -409,6 +416,13 @@ static void dm_vupdate_high_irq(void *interrupt_params)
+ 	}
+ }
+ 
++/**
++ * dm_crtc_high_irq() - Handles CRTC interrupt
++ * @interrupt_params: ignored
++ *
++ * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
++ * event handler.
++ */
+ static void dm_crtc_high_irq(void *interrupt_params)
+ {
+ 	struct common_irq_params *irq_params = interrupt_params;
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+index 94ab7109447a..1aba070477b9 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+@@ -105,6 +105,12 @@ struct amdgpu_dm_backlight_caps {
+  * @display_indexes_num: Max number of display streams supported
+  * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
+  * @backlight_dev: Backlight control device
++ * @backlight_link: Link on which to control backlight
++ * @backlight_caps: Capabilities of the backlight device
++ * @freesync_module: Module handling freesync calculations
++ * @fw_dmcu: Reference to DMCU firmware
++ * @dmcu_fw_version: Version of the DMCU firmware
++ * @soc_bounding_box: SOC bounding box values provided by gpu_info FW
+  * @cached_state: Caches device atomic state for suspend/resume
+  * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info
+  */
+@@ -123,7 +129,7 @@ struct amdgpu_display_manager {
+ 	u16 display_indexes_num;
+ 
+ 	/**
+-	 * @atomic_obj
++	 * @atomic_obj:
+ 	 *
+ 	 * In combination with &dm_atomic_state it helps manage
+ 	 * global atomic state that doesn't map cleanly into existing
+@@ -231,6 +237,8 @@ struct amdgpu_display_manager {
+ 	uint32_t dmcu_fw_version;
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	/**
++	 * @soc_bounding_box:
++	 *
+ 	 * gpu_info FW provided soc bounding box struct or 0 if not
+ 	 * available in FW
+ 	 */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3893-Fix-the-messed-up-format.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3893-Fix-the-messed-up-format.patch
new file mode 100644
index 00000000..41044763
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3893-Fix-the-messed-up-format.patch
@@ -0,0 +1,2083 @@
+From a57cc62927d04caa52937b894b89353003eddea6 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Thu, 26 Sep 2019 16:49:19 -0400
+Subject: [PATCH 3893/4256] Fix the messed up format
+
+Change-Id: I1fdf5536dca4045c68010b0c78e4a541e916fcaf
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+---
+ .../drm/amd/amdkfd/kfd_device_queue_manager.c | 1706 ++++++++---------
+ 1 file changed, 853 insertions(+), 853 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index dbcbacb5abd4..787b936a026d 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -42,558 +42,558 @@
+ #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2)
+ 
+ static int set_pasid_vmid_mapping(struct device_queue_manager *dqm,
+-								  unsigned int pasid, unsigned int vmid);
++					unsigned int pasid, unsigned int vmid);
+ 
+ static int execute_queues_cpsch(struct device_queue_manager *dqm,
+-								enum kfd_unmap_queues_filter filter,
+-								uint32_t filter_param,
+-								uint32_t grace_period);
++				enum kfd_unmap_queues_filter filter,
++				uint32_t filter_param,
++				uint32_t grace_period);
+ static int unmap_queues_cpsch(struct device_queue_manager *dqm,
+-							  enum kfd_unmap_queues_filter filter,
+-							  uint32_t filter_param,
+-							  uint32_t grace_period);
++				enum kfd_unmap_queues_filter filter,
++				uint32_t filter_param,
++				uint32_t grace_period);
+ 
+ static int map_queues_cpsch(struct device_queue_manager *dqm);
+ 
+ static void deallocate_sdma_queue(struct device_queue_manager *dqm,
+-								  struct queue *q);
++				struct queue *q);
+ 
+ static inline void deallocate_hqd(struct device_queue_manager *dqm,
+-								  struct queue *q);
++				struct queue *q);
+ static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q);
+ static int allocate_sdma_queue(struct device_queue_manager *dqm,
+-							   struct queue *q);
++				struct queue *q);
+ static void kfd_process_hw_exception(struct work_struct *work);
+ 
+-  static inline
++static inline
+ enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
+ {
+-  if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI)
+-	return KFD_MQD_TYPE_SDMA;
+-  return KFD_MQD_TYPE_CP;
++	if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI)
++		return KFD_MQD_TYPE_SDMA;
++	return KFD_MQD_TYPE_CP;
+ }
+ 
+ static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
+ {
+-  int i;
+-  int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec
+-	+ pipe * dqm->dev->shared_resources.num_queue_per_pipe;
++	int i;
++	int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec
++		+ pipe * dqm->dev->shared_resources.num_queue_per_pipe;
+ 
+-  /* queue is available for KFD usage if bit is 1 */
+-  for (i = 0; i <  dqm->dev->shared_resources.num_queue_per_pipe; ++i)
+-	if (test_bit(pipe_offset + i,
+-				 dqm->dev->shared_resources.queue_bitmap))
+-	  return true;
+-  return false;
++	/* queue is available for KFD usage if bit is 1 */
++	for (i = 0; i <  dqm->dev->shared_resources.num_queue_per_pipe; ++i)
++		if (test_bit(pipe_offset + i,
++			      dqm->dev->shared_resources.queue_bitmap))
++			return true;
++	return false;
+ }
+ 
+ unsigned int get_queues_num(struct device_queue_manager *dqm)
+ {
+-  return bitmap_weight(dqm->dev->shared_resources.queue_bitmap,
+-					   KGD_MAX_QUEUES);
++	return bitmap_weight(dqm->dev->shared_resources.queue_bitmap,
++				KGD_MAX_QUEUES);
+ }
+ 
+ unsigned int get_queues_per_pipe(struct device_queue_manager *dqm)
+ {
+-  return dqm->dev->shared_resources.num_queue_per_pipe;
++	return dqm->dev->shared_resources.num_queue_per_pipe;
+ }
+ 
+ unsigned int get_pipes_per_mec(struct device_queue_manager *dqm)
+ {
+-  return dqm->dev->shared_resources.num_pipe_per_mec;
++	return dqm->dev->shared_resources.num_pipe_per_mec;
+ }
+ 
+ static unsigned int get_num_sdma_engines(struct device_queue_manager *dqm)
+ {
+-  return dqm->dev->device_info->num_sdma_engines;
++	return dqm->dev->device_info->num_sdma_engines;
+ }
+ 
+ static unsigned int get_num_xgmi_sdma_engines(struct device_queue_manager *dqm)
+ {
+-  return dqm->dev->device_info->num_xgmi_sdma_engines;
++	return dqm->dev->device_info->num_xgmi_sdma_engines;
+ }
+ 
+ unsigned int get_num_sdma_queues(struct device_queue_manager *dqm)
+ {
+-  return dqm->dev->device_info->num_sdma_engines
+-	* dqm->dev->device_info->num_sdma_queues_per_engine;
++	return dqm->dev->device_info->num_sdma_engines
++			* dqm->dev->device_info->num_sdma_queues_per_engine;
+ }
+ 
+ unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm)
+ {
+-  return dqm->dev->device_info->num_xgmi_sdma_engines
+-	* dqm->dev->device_info->num_sdma_queues_per_engine;
++	return dqm->dev->device_info->num_xgmi_sdma_engines
++			* dqm->dev->device_info->num_sdma_queues_per_engine;
+ }
+ 
+ void program_sh_mem_settings(struct device_queue_manager *dqm,
+-							 struct qcm_process_device *qpd)
++					struct qcm_process_device *qpd)
+ {
+-  return dqm->dev->kfd2kgd->program_sh_mem_settings(
+-													dqm->dev->kgd, qpd->vmid,
+-													qpd->sh_mem_config,
+-													qpd->sh_mem_ape1_base,
+-													qpd->sh_mem_ape1_limit,
+-													qpd->sh_mem_bases);
++	return dqm->dev->kfd2kgd->program_sh_mem_settings(
++						dqm->dev->kgd, qpd->vmid,
++						qpd->sh_mem_config,
++						qpd->sh_mem_ape1_base,
++						qpd->sh_mem_ape1_limit,
++						qpd->sh_mem_bases);
+ }
+ 
+ bool check_if_queues_active(struct device_queue_manager *dqm,
+-							struct qcm_process_device *qpd)
++		struct qcm_process_device *qpd)
+ {
+-  bool busy = false;
+-  struct queue *q;
++	bool busy = false;
++	struct queue *q;
+ 
+-  dqm_lock(dqm);
+-  list_for_each_entry(q, &qpd->queues_list, list) {
+-	struct mqd_manager *mqd_mgr;
+-	enum KFD_MQD_TYPE type;
++	dqm_lock(dqm);
++	list_for_each_entry(q, &qpd->queues_list, list) {
++		struct mqd_manager *mqd_mgr;
++		enum KFD_MQD_TYPE type;
+ 
+-	type = get_mqd_type_from_queue_type(q->properties.type);
+-	mqd_mgr = dqm->mqd_mgrs[type];
+-	if (!mqd_mgr || !mqd_mgr->check_queue_active)
+-	  continue;
++		type = get_mqd_type_from_queue_type(q->properties.type);
++		mqd_mgr = dqm->mqd_mgrs[type];
++		if (!mqd_mgr || !mqd_mgr->check_queue_active)
++			continue;
+ 
+-	busy = mqd_mgr->check_queue_active(q);
+-	if (busy)
+-	  break;
+-  }
+-  dqm_unlock(dqm);
++		busy = mqd_mgr->check_queue_active(q);
++		if (busy)
++			break;
++	}
++	dqm_unlock(dqm);
+ 
+-  return busy;
++	return busy;
+ }
+ 
+ static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q)
+ {
+-  struct kfd_dev *dev = qpd->dqm->dev;
+-
+-  if (!KFD_IS_SOC15(dev->device_info->asic_family)) {
+-	/* On pre-SOC15 chips we need to use the queue ID to
+-	 * preserve the user mode ABI.
+-	 */
+-	q->doorbell_id = q->properties.queue_id;
+-  } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
+-			 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
+-	/* For SDMA queues on SOC15 with 8-byte doorbell, use static
+-	 * doorbell assignments based on the engine and queue id.
+-	 * The doobell index distance between RLC (2*i) and (2*i+1)
+-	 * for a SDMA engine is 512.
+-	 */
+-	uint32_t *idx_offset =
+-	  dev->shared_resources.sdma_doorbell_idx;
++	struct kfd_dev *dev = qpd->dqm->dev;
+ 
+-	q->doorbell_id = idx_offset[q->properties.sdma_engine_id]
+-	  + (q->properties.sdma_queue_id & 1)
+-	  * KFD_QUEUE_DOORBELL_MIRROR_OFFSET
+-	  + (q->properties.sdma_queue_id >> 1);
+-  } else {
+-	/* For CP queues on SOC15 reserve a free doorbell ID */
+-	unsigned int found;
++	if (!KFD_IS_SOC15(dev->device_info->asic_family)) {
++		/* On pre-SOC15 chips we need to use the queue ID to
++		 * preserve the user mode ABI.
++		 */
++		q->doorbell_id = q->properties.queue_id;
++	} else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
++			q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
++		/* For SDMA queues on SOC15 with 8-byte doorbell, use static
++		 * doorbell assignments based on the engine and queue id.
++		 * The doobell index distance between RLC (2*i) and (2*i+1)
++		 * for a SDMA engine is 512.
++		 */
++		uint32_t *idx_offset =
++				dev->shared_resources.sdma_doorbell_idx;
+ 
+-	found = find_first_zero_bit(qpd->doorbell_bitmap,
+-								KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
+-	if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
+-	  pr_debug("No doorbells available");
+-	  return -EBUSY;
++		q->doorbell_id = idx_offset[q->properties.sdma_engine_id]
++			+ (q->properties.sdma_queue_id & 1)
++			* KFD_QUEUE_DOORBELL_MIRROR_OFFSET
++			+ (q->properties.sdma_queue_id >> 1);
++	} else {
++		/* For CP queues on SOC15 reserve a free doorbell ID */
++		unsigned int found;
++
++		found = find_first_zero_bit(qpd->doorbell_bitmap,
++					    KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
++		if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
++			pr_debug("No doorbells available");
++			return -EBUSY;
++		}
++		set_bit(found, qpd->doorbell_bitmap);
++		q->doorbell_id = found;
+ 	}
+-	set_bit(found, qpd->doorbell_bitmap);
+-	q->doorbell_id = found;
+-  }
+ 
+-  q->properties.doorbell_off =
+-	kfd_doorbell_id_to_offset(dev, q->process,
+-							  q->doorbell_id);
++	q->properties.doorbell_off =
++		kfd_doorbell_id_to_offset(dev, q->process,
++					  q->doorbell_id);
+ 
+-  return 0;
++	return 0;
+ }
+ 
+ static void deallocate_doorbell(struct qcm_process_device *qpd,
+-								struct queue *q)
++				struct queue *q)
+ {
+-  unsigned int old;
+-  struct kfd_dev *dev = qpd->dqm->dev;
++	unsigned int old;
++	struct kfd_dev *dev = qpd->dqm->dev;
+ 
+-  if (!KFD_IS_SOC15(dev->device_info->asic_family) ||
+-	  q->properties.type == KFD_QUEUE_TYPE_SDMA ||
+-	  q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
+-	return;
++	if (!KFD_IS_SOC15(dev->device_info->asic_family) ||
++	    q->properties.type == KFD_QUEUE_TYPE_SDMA ||
++	    q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
++		return;
+ 
+-  old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap);
+-  WARN_ON(!old);
++	old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap);
++	WARN_ON(!old);
+ }
+ 
+ static int allocate_vmid(struct device_queue_manager *dqm,
+-						 struct qcm_process_device *qpd,
+-						 struct queue *q)
++			struct qcm_process_device *qpd,
++			struct queue *q)
+ {
+-  int bit, allocated_vmid;
++	int bit, allocated_vmid;
+ 
+-  if (dqm->vmid_bitmap == 0)
+-	return -ENOMEM;
++	if (dqm->vmid_bitmap == 0)
++		return -ENOMEM;
+ 
+-  bit = ffs(dqm->vmid_bitmap) - 1;
+-  dqm->vmid_bitmap &= ~(1 << bit);
++	bit = ffs(dqm->vmid_bitmap) - 1;
++	dqm->vmid_bitmap &= ~(1 << bit);
+ 
+-  allocated_vmid = bit + dqm->dev->vm_info.first_vmid_kfd;
+-  pr_debug("vmid allocation %d\n", allocated_vmid);
+-  qpd->vmid = allocated_vmid;
+-  q->properties.vmid = allocated_vmid;
++	allocated_vmid = bit + dqm->dev->vm_info.first_vmid_kfd;
++	pr_debug("vmid allocation %d\n", allocated_vmid);
++	qpd->vmid = allocated_vmid;
++	q->properties.vmid = allocated_vmid;
+ 
+-  set_pasid_vmid_mapping(dqm, q->process->pasid, q->properties.vmid);
+-  program_sh_mem_settings(dqm, qpd);
++	set_pasid_vmid_mapping(dqm, q->process->pasid, q->properties.vmid);
++	program_sh_mem_settings(dqm, qpd);
+ 
+-  /* qpd->page_table_base is set earlier when register_process()
+-   * is called, i.e. when the first queue is created.
+-   */
+-  dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->kgd,
+-													qpd->vmid,
+-													qpd->page_table_base);
+-  /* invalidate the VM context after pasid and vmid mapping is set up */
+-  kfd_flush_tlb(qpd_to_pdd(qpd));
++	/* qpd->page_table_base is set earlier when register_process()
++	 * is called, i.e. when the first queue is created.
++	 */
++	dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->kgd,
++			qpd->vmid,
++			qpd->page_table_base);
++	/* invalidate the VM context after pasid and vmid mapping is set up */
++	kfd_flush_tlb(qpd_to_pdd(qpd));
+ 
+-  dqm->dev->kfd2kgd->set_scratch_backing_va(
+-											dqm->dev->kgd, qpd->sh_hidden_private_base, qpd->vmid);
++	dqm->dev->kfd2kgd->set_scratch_backing_va(
++		dqm->dev->kgd, qpd->sh_hidden_private_base, qpd->vmid);
+ 
+-  return 0;
++	return 0;
+ }
+ 
+ static int flush_texture_cache_nocpsch(struct kfd_dev *kdev,
+-									   struct qcm_process_device *qpd)
++				struct qcm_process_device *qpd)
+ {
+-  const struct packet_manager_funcs *pmf = qpd->dqm->packets.pmf;
+-  int ret;
++	const struct packet_manager_funcs *pmf = qpd->dqm->packets.pmf;
++	int ret;
+ 
+-  if (!qpd->ib_kaddr)
+-	return -ENOMEM;
++	if (!qpd->ib_kaddr)
++		return -ENOMEM;
+ 
+-  ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr);
+-  if (ret)
+-	return ret;
++	ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr);
++	if (ret)
++		return ret;
+ 
+-  return amdgpu_amdkfd_submit_ib(kdev->kgd, KGD_ENGINE_MEC1, qpd->vmid,
+-								 qpd->ib_base, (uint32_t *)qpd->ib_kaddr,
+-								 pmf->release_mem_size / sizeof(uint32_t));
++	return amdgpu_amdkfd_submit_ib(kdev->kgd, KGD_ENGINE_MEC1, qpd->vmid,
++				qpd->ib_base, (uint32_t *)qpd->ib_kaddr,
++				pmf->release_mem_size / sizeof(uint32_t));
+ }
+ 
+ static void deallocate_vmid(struct device_queue_manager *dqm,
+-							struct qcm_process_device *qpd,
+-							struct queue *q)
++				struct qcm_process_device *qpd,
++				struct queue *q)
+ {
+-  int bit = qpd->vmid - dqm->dev->vm_info.first_vmid_kfd;
++	int bit = qpd->vmid - dqm->dev->vm_info.first_vmid_kfd;
+ 
+-  /* On GFX v7, CP doesn't flush TC at dequeue */
+-  if (q->device->device_info->asic_family == CHIP_HAWAII)
+-	if (flush_texture_cache_nocpsch(q->device, qpd))
+-	  pr_err("Failed to flush TC\n");
++	/* On GFX v7, CP doesn't flush TC at dequeue */
++	if (q->device->device_info->asic_family == CHIP_HAWAII)
++		if (flush_texture_cache_nocpsch(q->device, qpd))
++			pr_err("Failed to flush TC\n");
+ 
+-  kfd_flush_tlb(qpd_to_pdd(qpd));
++	kfd_flush_tlb(qpd_to_pdd(qpd));
+ 
+-  /* Release the vmid mapping */
+-  set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
++	/* Release the vmid mapping */
++	set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
+ 
+-  dqm->vmid_bitmap |= (1 << bit);
+-  qpd->vmid = 0;
+-  q->properties.vmid = 0;
++	dqm->vmid_bitmap |= (1 << bit);
++	qpd->vmid = 0;
++	q->properties.vmid = 0;
+ }
+ 
+ static int create_queue_nocpsch(struct device_queue_manager *dqm,
+-								struct queue *q,
+-								struct qcm_process_device *qpd)
++				struct queue *q,
++				struct qcm_process_device *qpd)
+ {
+-  struct mqd_manager *mqd_mgr;
+-  int retval;
++	struct mqd_manager *mqd_mgr;
++	int retval;
+ 
+-  print_queue(q);
++	print_queue(q);
+ 
+-  dqm_lock(dqm);
++	dqm_lock(dqm);
+ 
+-  if (dqm->total_queue_count >= max_num_of_queues_per_device) {
+-	pr_warn("Can't create new usermode queue because %d queues were already created\n",
+-			dqm->total_queue_count);
+-	retval = -EPERM;
+-	goto out_unlock;
+-  }
++	if (dqm->total_queue_count >= max_num_of_queues_per_device) {
++		pr_warn("Can't create new usermode queue because %d queues were already created\n",
++				dqm->total_queue_count);
++		retval = -EPERM;
++		goto out_unlock;
++	}
+ 
+-  if (list_empty(&qpd->queues_list)) {
+-	retval = allocate_vmid(dqm, qpd, q);
+-	if (retval)
+-	  goto out_unlock;
+-  }
+-  q->properties.vmid = qpd->vmid;
+-  /*
+-   * Eviction state logic: mark all queues as evicted, even ones
+-   * not currently active. Restoring inactive queues later only
+-   * updates the is_evicted flag but is a no-op otherwise.
+-   */
+-  q->properties.is_evicted = !!qpd->evicted;
+-
+-  q->properties.tba_addr = qpd->tba_addr;
+-  q->properties.tma_addr = qpd->tma_addr;
+-
+-  mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
+-													   q->properties.type)];
+-  if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
+-	retval = allocate_hqd(dqm, q);
+-	if (retval)
+-	  goto deallocate_vmid;
+-	pr_debug("Loading mqd to hqd on pipe %d, queue %d\n",
+-			 q->pipe, q->queue);
+-  } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
+-			 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
+-	retval = allocate_sdma_queue(dqm, q);
+-	if (retval)
+-	  goto deallocate_vmid;
+-	dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
+-  }
+-
+-  retval = allocate_doorbell(qpd, q);
+-  if (retval)
+-	goto out_deallocate_hqd;
+-
+-  /* Temporarily release dqm lock to avoid a circular lock dependency */
+-  dqm_unlock(dqm);
+-  q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
+-  dqm_lock(dqm);
+-
+-  if (!q->mqd_mem_obj) {
+-	retval = -ENOMEM;
+-	goto out_deallocate_doorbell;
+-  }
+-  mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
+-					&q->gart_mqd_addr, &q->properties);
+-  if (q->properties.is_active) {
+-
+-	if (WARN(q->process->mm != current->mm,
+-			 "should only run in user thread"))
+-	  retval = -EFAULT;
+-	else
+-	  retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
+-								 q->queue, &q->properties, current->mm);
++	if (list_empty(&qpd->queues_list)) {
++		retval = allocate_vmid(dqm, qpd, q);
++		if (retval)
++			goto out_unlock;
++	}
++	q->properties.vmid = qpd->vmid;
++	/*
++	 * Eviction state logic: mark all queues as evicted, even ones
++	 * not currently active. Restoring inactive queues later only
++	 * updates the is_evicted flag but is a no-op otherwise.
++	 */
++	q->properties.is_evicted = !!qpd->evicted;
++
++	q->properties.tba_addr = qpd->tba_addr;
++	q->properties.tma_addr = qpd->tma_addr;
++
++	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
++			q->properties.type)];
++	if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
++		retval = allocate_hqd(dqm, q);
++		if (retval)
++			goto deallocate_vmid;
++		pr_debug("Loading mqd to hqd on pipe %d, queue %d\n",
++			q->pipe, q->queue);
++	} else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
++		q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
++		retval = allocate_sdma_queue(dqm, q);
++		if (retval)
++			goto deallocate_vmid;
++		dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
++	}
++
++	retval = allocate_doorbell(qpd, q);
+ 	if (retval)
+-	  goto out_free_mqd;
+-  }
++		goto out_deallocate_hqd;
+ 
+-  list_add(&q->list, &qpd->queues_list);
+-  qpd->queue_count++;
+-  if (q->properties.is_active)
+-	dqm->queue_count++;
++	/* Temporarily release dqm lock to avoid a circular lock dependency */
++	dqm_unlock(dqm);
++	q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
++	dqm_lock(dqm);
++
++	if (!q->mqd_mem_obj) {
++		retval = -ENOMEM;
++		goto out_deallocate_doorbell;
++	}
++	mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
++				&q->gart_mqd_addr, &q->properties);
++	if (q->properties.is_active) {
+ 
+-  if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
+-	dqm->sdma_queue_count++;
+-  else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
+-	dqm->xgmi_sdma_queue_count++;
++		if (WARN(q->process->mm != current->mm,
++					"should only run in user thread"))
++			retval = -EFAULT;
++		else
++			retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
++					q->queue, &q->properties, current->mm);
++		if (retval)
++			goto out_free_mqd;
++	}
+ 
+-  /*
+-   * Unconditionally increment this counter, regardless of the queue's
+-   * type or whether the queue is active.
+-   */
+-  dqm->total_queue_count++;
+-  pr_debug("Total of %d queues are accountable so far\n",
+-		   dqm->total_queue_count);
+-  goto out_unlock;
++	list_add(&q->list, &qpd->queues_list);
++	qpd->queue_count++;
++	if (q->properties.is_active)
++		dqm->queue_count++;
++
++	if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
++		dqm->sdma_queue_count++;
++	else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
++		dqm->xgmi_sdma_queue_count++;
++
++	/*
++	 * Unconditionally increment this counter, regardless of the queue's
++	 * type or whether the queue is active.
++	 */
++	dqm->total_queue_count++;
++	pr_debug("Total of %d queues are accountable so far\n",
++			dqm->total_queue_count);
++	goto out_unlock;
+ 
+ out_free_mqd:
+-  mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
++	mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
+ out_deallocate_doorbell:
+-  deallocate_doorbell(qpd, q);
++	deallocate_doorbell(qpd, q);
+ out_deallocate_hqd:
+-  if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
+-	deallocate_hqd(dqm, q);
+-  else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
+-		   q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
+-	deallocate_sdma_queue(dqm, q);
++	if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
++		deallocate_hqd(dqm, q);
++	else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
++		q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
++		deallocate_sdma_queue(dqm, q);
+ deallocate_vmid:
+-  if (list_empty(&qpd->queues_list))
+-	deallocate_vmid(dqm, qpd, q);
++	if (list_empty(&qpd->queues_list))
++		deallocate_vmid(dqm, qpd, q);
+ out_unlock:
+-  dqm_unlock(dqm);
+-  return retval;
++	dqm_unlock(dqm);
++	return retval;
+ }
+ 
+ static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q)
+ {
+-  bool set;
+-  int pipe, bit, i;
++	bool set;
++	int pipe, bit, i;
+ 
+-  set = false;
++	set = false;
+ 
+-  for (pipe = dqm->next_pipe_to_allocate, i = 0;
+-	   i < get_pipes_per_mec(dqm);
+-	   pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) {
++	for (pipe = dqm->next_pipe_to_allocate, i = 0;
++			i < get_pipes_per_mec(dqm);
++			pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) {
+ 
+-	if (!is_pipe_enabled(dqm, 0, pipe))
+-	  continue;
++		if (!is_pipe_enabled(dqm, 0, pipe))
++			continue;
+ 
+-	if (dqm->allocated_queues[pipe] != 0) {
+-	  bit = ffs(dqm->allocated_queues[pipe]) - 1;
+-	  dqm->allocated_queues[pipe] &= ~(1 << bit);
+-	  q->pipe = pipe;
+-	  q->queue = bit;
+-	  set = true;
+-	  break;
++		if (dqm->allocated_queues[pipe] != 0) {
++			bit = ffs(dqm->allocated_queues[pipe]) - 1;
++			dqm->allocated_queues[pipe] &= ~(1 << bit);
++			q->pipe = pipe;
++			q->queue = bit;
++			set = true;
++			break;
++		}
+ 	}
+-  }
+ 
+-  if (!set)
+-	return -EBUSY;
++	if (!set)
++		return -EBUSY;
+ 
+-  pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue);
+-  /* horizontal hqd allocation */
+-  dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm);
++	pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue);
++	/* horizontal hqd allocation */
++	dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm);
+ 
+-  return 0;
++	return 0;
+ }
+ 
+ static inline void deallocate_hqd(struct device_queue_manager *dqm,
+-								  struct queue *q)
++				struct queue *q)
+ {
+-  dqm->allocated_queues[q->pipe] |= (1 << q->queue);
++	dqm->allocated_queues[q->pipe] |= (1 << q->queue);
+ }
+ 
+ /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked
+  * to avoid asynchronized access
+  */
+ static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
+-										struct qcm_process_device *qpd,
+-										struct queue *q)
+-{
+-  int retval;
+-  struct mqd_manager *mqd_mgr;
+-
+-  mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
+-													   q->properties.type)];
+-
+-  if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
+-	deallocate_hqd(dqm, q);
+-  } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
+-	dqm->sdma_queue_count--;
+-	deallocate_sdma_queue(dqm, q);
+-  } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
+-	dqm->xgmi_sdma_queue_count--;
+-	deallocate_sdma_queue(dqm, q);
+-  } else {
+-	pr_debug("q->properties.type %d is invalid\n",
+-			 q->properties.type);
+-	return -EINVAL;
+-  }
+-  dqm->total_queue_count--;
+-
+-  deallocate_doorbell(qpd, q);
+-
+-  retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
+-								KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
+-								KFD_UNMAP_LATENCY_MS,
+-								q->pipe, q->queue);
+-  if (retval == -ETIME)
+-	qpd->reset_wavefronts = true;
+-
+-  mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
+-
+-  list_del(&q->list);
+-  if (list_empty(&qpd->queues_list)) {
+-	if (qpd->reset_wavefronts) {
+-	  pr_warn("Resetting wave fronts (nocpsch) on dev %p\n",
+-			  dqm->dev);
+-	  /* dbgdev_wave_reset_wavefronts has to be called before
+-	   * deallocate_vmid(), i.e. when vmid is still in use.
+-	   */
+-	  dbgdev_wave_reset_wavefronts(dqm->dev,
+-								   qpd->pqm->process);
+-	  qpd->reset_wavefronts = false;
+-	}
+-
+-	deallocate_vmid(dqm, qpd, q);
+-  }
+-  qpd->queue_count--;
+-  if (q->properties.is_active)
+-	dqm->queue_count--;
++				struct qcm_process_device *qpd,
++				struct queue *q)
++{
++	int retval;
++	struct mqd_manager *mqd_mgr;
++
++	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
++			q->properties.type)];
++
++	if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
++		deallocate_hqd(dqm, q);
++	} else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
++		dqm->sdma_queue_count--;
++		deallocate_sdma_queue(dqm, q);
++	} else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
++		dqm->xgmi_sdma_queue_count--;
++		deallocate_sdma_queue(dqm, q);
++	} else {
++		pr_debug("q->properties.type %d is invalid\n",
++				q->properties.type);
++		return -EINVAL;
++	}
++	dqm->total_queue_count--;
++
++	deallocate_doorbell(qpd, q);
+ 
+-  return retval;
++	retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
++				KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
++				KFD_UNMAP_LATENCY_MS,
++				q->pipe, q->queue);
++	if (retval == -ETIME)
++		qpd->reset_wavefronts = true;
++
++	mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
++
++	list_del(&q->list);
++	if (list_empty(&qpd->queues_list)) {
++		if (qpd->reset_wavefronts) {
++			pr_warn("Resetting wave fronts (nocpsch) on dev %p\n",
++					dqm->dev);
++			/* dbgdev_wave_reset_wavefronts has to be called before
++			 * deallocate_vmid(), i.e. when vmid is still in use.
++			 */
++			dbgdev_wave_reset_wavefronts(dqm->dev,
++					qpd->pqm->process);
++			qpd->reset_wavefronts = false;
++		}
++
++		deallocate_vmid(dqm, qpd, q);
++	}
++	qpd->queue_count--;
++	if (q->properties.is_active)
++		dqm->queue_count--;
++
++	return retval;
+ }
+ 
+ static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
+-								 struct qcm_process_device *qpd,
+-								 struct queue *q)
++				struct qcm_process_device *qpd,
++				struct queue *q)
+ {
+-  int retval;
++	int retval;
+ 
+-  dqm_lock(dqm);
+-  retval = destroy_queue_nocpsch_locked(dqm, qpd, q);
+-  dqm_unlock(dqm);
++	dqm_lock(dqm);
++	retval = destroy_queue_nocpsch_locked(dqm, qpd, q);
++	dqm_unlock(dqm);
+ 
+-  return retval;
++	return retval;
+ }
+ 
+ static int update_queue(struct device_queue_manager *dqm, struct queue *q)
+ {
+-  int retval = 0;
+-  struct mqd_manager *mqd_mgr;
+-  struct kfd_process_device *pdd;
+-  bool prev_active = false;
++	int retval = 0;
++	struct mqd_manager *mqd_mgr;
++	struct kfd_process_device *pdd;
++	bool prev_active = false;
+ 
+-  dqm_lock(dqm);
+-  pdd = kfd_get_process_device_data(q->device, q->process);
+-  if (!pdd) {
+-	retval = -ENODEV;
+-	goto out_unlock;
+-  }
+-  mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
+-													   q->properties.type)];
+-
+-  /* Save previous activity state for counters */
+-  prev_active = q->properties.is_active;
+-
+-  /* Make sure the queue is unmapped before updating the MQD */
+-  if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
+-	retval = unmap_queues_cpsch(dqm,
+-								KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
+-								USE_DEFAULT_GRACE_PERIOD);
+-	if (retval) {
+-	  pr_err("unmap queue failed\n");
+-	  goto out_unlock;
++	dqm_lock(dqm);
++	pdd = kfd_get_process_device_data(q->device, q->process);
++	if (!pdd) {
++		retval = -ENODEV;
++		goto out_unlock;
+ 	}
+-  } else if (prev_active &&
+-			 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
+-			  q->properties.type == KFD_QUEUE_TYPE_SDMA ||
+-			  q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
+-	retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
+-								  KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
+-								  KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
+-	if (retval) {
+-	  pr_err("destroy mqd failed\n");
+-	  goto out_unlock;
++	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
++			q->properties.type)];
++
++	/* Save previous activity state for counters */
++	prev_active = q->properties.is_active;
++
++	/* Make sure the queue is unmapped before updating the MQD */
++	if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
++		retval = unmap_queues_cpsch(dqm,
++				KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
++				USE_DEFAULT_GRACE_PERIOD);
++		if (retval) {
++			pr_err("unmap queue failed\n");
++			goto out_unlock;
++		}
++	} else if (prev_active &&
++		   (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
++		    q->properties.type == KFD_QUEUE_TYPE_SDMA ||
++		    q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
++		retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
++				KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
++				KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
++		if (retval) {
++			pr_err("destroy mqd failed\n");
++			goto out_unlock;
++		}
+ 	}
+-  }
+ 
+-  mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties);
++	mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties);
+ 
+-  /*
+-   * check active state vs. the previous state and modify
+-   * counter accordingly. map_queues_cpsch uses the
+-   * dqm->queue_count to determine whether a new runlist must be
+-   * uploaded.
+-   */
+-  if (q->properties.is_active && !prev_active)
+-	dqm->queue_count++;
+-  else if (!q->properties.is_active && prev_active)
+-	dqm->queue_count--;
++	/*
++	 * check active state vs. the previous state and modify
++	 * counter accordingly. map_queues_cpsch uses the
++	 * dqm->queue_count to determine whether a new runlist must be
++	 * uploaded.
++	 */
++	if (q->properties.is_active && !prev_active)
++		dqm->queue_count++;
++	else if (!q->properties.is_active && prev_active)
++		dqm->queue_count--;
+ 
+-  if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS)
+-	retval = map_queues_cpsch(dqm);
+-  else if (q->properties.is_active &&
+-		   (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
+-			q->properties.type == KFD_QUEUE_TYPE_SDMA ||
+-			q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
+-	if (WARN(q->process->mm != current->mm,
++	if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS)
++		retval = map_queues_cpsch(dqm);
++	else if (q->properties.is_active &&
++		 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
++		  q->properties.type == KFD_QUEUE_TYPE_SDMA ||
++		  q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
++		if (WARN(q->process->mm != current->mm,
+ 			 "should only run in user thread"))
+-	  retval = -EFAULT;
+-	else
+-	  retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd,
+-								 q->pipe, q->queue,
+-								 &q->properties, current->mm);
+-  }
++			retval = -EFAULT;
++		else
++			retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd,
++						   q->pipe, q->queue,
++						   &q->properties, current->mm);
++	}
+ 
+ out_unlock:
+-  dqm_unlock(dqm);
+-  return retval;
++	dqm_unlock(dqm);
++	return retval;
+ }
+ 
+ /* suspend_single_queue does not lock the dqm like the
+@@ -605,22 +605,22 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q)
+  * multiple times, we will just keep the dqm locked for all of the calls.
+  */
+ static int suspend_single_queue(struct device_queue_manager *dqm,
+-								struct kfd_process_device *pdd,
+-								struct queue *q)
++				      struct kfd_process_device *pdd,
++				      struct queue *q)
+ {
+-  int retval = 0;
++	int retval = 0;
+ 
+-  pr_debug("Suspending PASID %u queue [%i]\n",
+-		   pdd->process->pasid,
+-		   q->properties.queue_id);
++	pr_debug("Suspending PASID %u queue [%i]\n",
++			pdd->process->pasid,
++			q->properties.queue_id);
+ 
+-  q->properties.is_suspended = true;
+-  if (q->properties.is_active) {
+-	dqm->queue_count--;
+-	q->properties.is_active = false;
+-  }
++	q->properties.is_suspended = true;
++	if (q->properties.is_active) {
++		dqm->queue_count--;
++		q->properties.is_active = false;
++	}
+ 
+-  return retval;
++	return retval;
+ }
+ 
+ /* resume_single_queue does not lock the dqm like the functions
+@@ -632,419 +632,419 @@ static int suspend_single_queue(struct device_queue_manager *dqm,
+  * multiple times, we will just keep the dqm locked for all of the calls.
+  */
+ static int resume_single_queue(struct device_queue_manager *dqm,
+-							   struct qcm_process_device *qpd,
+-							   struct queue *q)
++				      struct qcm_process_device *qpd,
++				      struct queue *q)
+ {
+-  struct kfd_process_device *pdd;
+-  uint64_t pd_base;
+-  int retval = 0;
++	struct kfd_process_device *pdd;
++	uint64_t pd_base;
++	int retval = 0;
+ 
+-  pdd = qpd_to_pdd(qpd);
+-  /* Retrieve PD base */
+-  pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
++	pdd = qpd_to_pdd(qpd);
++	/* Retrieve PD base */
++	pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
+ 
+-  pr_debug("Restoring from suspend PASID %u queue [%i]\n",
+-		   pdd->process->pasid,
+-		   q->properties.queue_id);
++	pr_debug("Restoring from suspend PASID %u queue [%i]\n",
++			    pdd->process->pasid,
++			    q->properties.queue_id);
+ 
+-  q->properties.is_suspended = false;
++	q->properties.is_suspended = false;
+ 
+-  if (QUEUE_IS_ACTIVE(q->properties)) {
+-	q->properties.is_active = true;
+-	dqm->queue_count++;
+-  }
++	if (QUEUE_IS_ACTIVE(q->properties)) {
++		q->properties.is_active = true;
++		dqm->queue_count++;
++	}
+ 
+-  return retval;
++	return retval;
+ }
+ static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
+-										struct qcm_process_device *qpd)
++					struct qcm_process_device *qpd)
+ {
+-  struct queue *q;
+-  struct mqd_manager *mqd_mgr;
+-  struct kfd_process_device *pdd;
+-  int retval, ret = 0;
++	struct queue *q;
++	struct mqd_manager *mqd_mgr;
++	struct kfd_process_device *pdd;
++	int retval, ret = 0;
+ 
+-  dqm_lock(dqm);
+-  if (qpd->evicted++ > 0) /* already evicted, do nothing */
+-	goto out;
++	dqm_lock(dqm);
++	if (qpd->evicted++ > 0) /* already evicted, do nothing */
++		goto out;
+ 
+-  pdd = qpd_to_pdd(qpd);
+-  pr_info_ratelimited("Evicting PASID %u queues\n",
+-					  pdd->process->pasid);
++	pdd = qpd_to_pdd(qpd);
++	pr_info_ratelimited("Evicting PASID %u queues\n",
++			    pdd->process->pasid);
+ 
+-  /* Mark all queues as evicted. Deactivate all active queues on
+-   * the qpd.
+-   */
+-  list_for_each_entry(q, &qpd->queues_list, list) {
+-	q->properties.is_evicted = true;
+-	if (!q->properties.is_active)
+-	  continue;
++	/* Mark all queues as evicted. Deactivate all active queues on
++	 * the qpd.
++	 */
++	list_for_each_entry(q, &qpd->queues_list, list) {
++		q->properties.is_evicted = true;
++		if (!q->properties.is_active)
++			continue;
+ 
+-	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
+-														 q->properties.type)];
+-	q->properties.is_active = false;
+-	retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
+-								  KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
+-								  KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
+-	if (retval && !ret)
+-	  /* Return the first error, but keep going to
+-	   * maintain a consistent eviction state
+-	   */
+-	  ret = retval;
+-	dqm->queue_count--;
+-  }
++		mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
++				q->properties.type)];
++		q->properties.is_active = false;
++		retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
++				KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
++				KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
++		if (retval && !ret)
++			/* Return the first error, but keep going to
++			 * maintain a consistent eviction state
++			 */
++			ret = retval;
++		dqm->queue_count--;
++	}
+ 
+ out:
+-  dqm_unlock(dqm);
+-  return ret;
++	dqm_unlock(dqm);
++	return ret;
+ }
+ 
+ static int evict_process_queues_cpsch(struct device_queue_manager *dqm,
+-									  struct qcm_process_device *qpd)
++				      struct qcm_process_device *qpd)
+ {
+-  struct queue *q;
+-  struct kfd_process_device *pdd;
+-  int retval = 0;
++	struct queue *q;
++	struct kfd_process_device *pdd;
++	int retval = 0;
+ 
+-  dqm_lock(dqm);
+-  if (qpd->evicted++ > 0) /* already evicted, do nothing */
+-	goto out;
++	dqm_lock(dqm);
++	if (qpd->evicted++ > 0) /* already evicted, do nothing */
++		goto out;
+ 
+-  pdd = qpd_to_pdd(qpd);
+-  pr_info_ratelimited("Evicting PASID %u queues\n",
+-					  pdd->process->pasid);
++	pdd = qpd_to_pdd(qpd);
++	pr_info_ratelimited("Evicting PASID %u queues\n",
++			    pdd->process->pasid);
+ 
+-  /* Mark all queues as evicted. Deactivate all active queues on
+-   * the qpd.
+-   */
+-  list_for_each_entry(q, &qpd->queues_list, list) {
+-	q->properties.is_evicted = true;
+-	if (!q->properties.is_active)
+-	  continue;
++	/* Mark all queues as evicted. Deactivate all active queues on
++	 * the qpd.
++	 */
++	list_for_each_entry(q, &qpd->queues_list, list) {
++		q->properties.is_evicted = true;
++		if (!q->properties.is_active)
++			continue;
+ 
+-	q->properties.is_active = false;
+-	dqm->queue_count--;
+-  }
+-  retval = execute_queues_cpsch(dqm,
+-								qpd->is_debug ?
+-								KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES :
+-								KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
+-								USE_DEFAULT_GRACE_PERIOD);
++		q->properties.is_active = false;
++		dqm->queue_count--;
++	}
++	retval = execute_queues_cpsch(dqm,
++				qpd->is_debug ?
++				KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES :
++				KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
++				USE_DEFAULT_GRACE_PERIOD);
+ 
+ out:
+-  dqm_unlock(dqm);
+-  return retval;
++	dqm_unlock(dqm);
++	return retval;
+ }
+ 
+ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
+-										  struct qcm_process_device *qpd)
+-{
+-  struct mm_struct *mm = NULL;
+-  struct queue *q;
+-  struct mqd_manager *mqd_mgr;
+-  struct kfd_process_device *pdd;
+-  uint64_t pd_base;
+-  int retval, ret = 0;
+-
+-  pdd = qpd_to_pdd(qpd);
+-  /* Retrieve PD base */
+-  pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
+-
+-  dqm_lock(dqm);
+-  if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
+-	goto out;
+-  if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
+-	qpd->evicted--;
+-	goto out;
+-  }
+-
+-  pr_info_ratelimited("Restoring PASID %u queues\n",
+-					  pdd->process->pasid);
+-
+-  /* Update PD Base in QPD */
+-  qpd->page_table_base = pd_base;
+-  pr_debug("Updated PD address to 0x%llx\n", pd_base);
+-
+-  if (!list_empty(&qpd->queues_list)) {
+-	dqm->dev->kfd2kgd->set_vm_context_page_table_base(
+-													  dqm->dev->kgd,
+-													  qpd->vmid,
+-													  qpd->page_table_base);
+-	kfd_flush_tlb(pdd);
+-  }
+-
+-  /* Take a safe reference to the mm_struct, which may otherwise
+-   * disappear even while the kfd_process is still referenced.
+-   */
+-  mm = get_task_mm(pdd->process->lead_thread);
+-  if (!mm) {
+-	ret = -EFAULT;
+-	goto out;
+-  }
+-
+-  /* Remove the eviction flags. Activate queues that are not
+-   * inactive for other reasons.
+-   */
+-  list_for_each_entry(q, &qpd->queues_list, list) {
+-	q->properties.is_evicted = false;
+-	if (!QUEUE_IS_ACTIVE(q->properties))
+-	  continue;
++					  struct qcm_process_device *qpd)
++{
++	struct mm_struct *mm = NULL;
++	struct queue *q;
++	struct mqd_manager *mqd_mgr;
++	struct kfd_process_device *pdd;
++	uint64_t pd_base;
++	int retval, ret = 0;
+ 
+-	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
+-														 q->properties.type)];
+-	q->properties.is_active = true;
+-	retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
+-							   q->queue, &q->properties, mm);
+-	if (retval && !ret)
+-	  /* Return the first error, but keep going to
+-	   * maintain a consistent eviction state
+-	   */
+-	  ret = retval;
+-	dqm->queue_count++;
+-  }
+-  qpd->evicted = 0;
++	pdd = qpd_to_pdd(qpd);
++	/* Retrieve PD base */
++	pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
++
++	dqm_lock(dqm);
++	if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
++		goto out;
++	if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
++		qpd->evicted--;
++		goto out;
++	}
++
++	pr_info_ratelimited("Restoring PASID %u queues\n",
++			    pdd->process->pasid);
++
++	/* Update PD Base in QPD */
++	qpd->page_table_base = pd_base;
++	pr_debug("Updated PD address to 0x%llx\n", pd_base);
++
++	if (!list_empty(&qpd->queues_list)) {
++		dqm->dev->kfd2kgd->set_vm_context_page_table_base(
++				dqm->dev->kgd,
++				qpd->vmid,
++				qpd->page_table_base);
++		kfd_flush_tlb(pdd);
++	}
++
++	/* Take a safe reference to the mm_struct, which may otherwise
++	 * disappear even while the kfd_process is still referenced.
++	 */
++	mm = get_task_mm(pdd->process->lead_thread);
++	if (!mm) {
++		ret = -EFAULT;
++		goto out;
++	}
++
++	/* Remove the eviction flags. Activate queues that are not
++	 * inactive for other reasons.
++	 */
++	list_for_each_entry(q, &qpd->queues_list, list) {
++		q->properties.is_evicted = false;
++		if (!QUEUE_IS_ACTIVE(q->properties))
++			continue;
++
++		mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
++				q->properties.type)];
++		q->properties.is_active = true;
++		retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
++				       q->queue, &q->properties, mm);
++		if (retval && !ret)
++			/* Return the first error, but keep going to
++			 * maintain a consistent eviction state
++			 */
++			ret = retval;
++		dqm->queue_count++;
++	}
++	qpd->evicted = 0;
+ out:
+-  if (mm)
+-	mmput(mm);
+-  dqm_unlock(dqm);
+-  return ret;
++	if (mm)
++		mmput(mm);
++	dqm_unlock(dqm);
++	return ret;
+ }
+ 
+ static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
+-										struct qcm_process_device *qpd)
+-{
+-  struct queue *q;
+-  struct kfd_process_device *pdd;
+-  uint64_t pd_base;
+-  int retval = 0;
+-
+-  pdd = qpd_to_pdd(qpd);
+-  /* Retrieve PD base */
+-  pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
+-
+-  dqm_lock(dqm);
+-  if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
+-	goto out;
+-  if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
+-	qpd->evicted--;
+-	goto out;
+-  }
+-
+-  pr_info_ratelimited("Restoring PASID %u queues\n",
+-					  pdd->process->pasid);
+-
+-  /* Update PD Base in QPD */
+-  qpd->page_table_base = pd_base;
+-  pr_debug("Updated PD address to 0x%llx\n", pd_base);
+-
+-  /* activate all active queues on the qpd */
+-  list_for_each_entry(q, &qpd->queues_list, list) {
+-	q->properties.is_evicted = false;
+-	if (!QUEUE_IS_ACTIVE(q->properties))
+-	  continue;
+-
+-	q->properties.is_active = true;
+-	dqm->queue_count++;
+-  }
+-  retval = execute_queues_cpsch(dqm,
+-								KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
+-								USE_DEFAULT_GRACE_PERIOD);
+-  qpd->evicted = 0;
++					struct qcm_process_device *qpd)
++{
++	struct queue *q;
++	struct kfd_process_device *pdd;
++	uint64_t pd_base;
++	int retval = 0;
++
++	pdd = qpd_to_pdd(qpd);
++	/* Retrieve PD base */
++	pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
++
++	dqm_lock(dqm);
++	if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
++		goto out;
++	if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
++		qpd->evicted--;
++		goto out;
++	}
++
++	pr_info_ratelimited("Restoring PASID %u queues\n",
++			    pdd->process->pasid);
++
++	/* Update PD Base in QPD */
++	qpd->page_table_base = pd_base;
++	pr_debug("Updated PD address to 0x%llx\n", pd_base);
++
++	/* activate all active queues on the qpd */
++	list_for_each_entry(q, &qpd->queues_list, list) {
++		q->properties.is_evicted = false;
++		if (!QUEUE_IS_ACTIVE(q->properties))
++			continue;
++
++		q->properties.is_active = true;
++		dqm->queue_count++;
++	}
++	retval = execute_queues_cpsch(dqm,
++				KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
++				USE_DEFAULT_GRACE_PERIOD);
++	qpd->evicted = 0;
+ out:
+-  dqm_unlock(dqm);
+-  return retval;
++	dqm_unlock(dqm);
++	return retval;
+ }
+ 
+ static int register_process(struct device_queue_manager *dqm,
+-							struct qcm_process_device *qpd)
++					struct qcm_process_device *qpd)
+ {
+-  struct device_process_node *n;
+-  struct kfd_process_device *pdd;
+-  uint64_t pd_base;
+-  int retval;
++	struct device_process_node *n;
++	struct kfd_process_device *pdd;
++	uint64_t pd_base;
++	int retval;
+ 
+-  n = kzalloc(sizeof(*n), GFP_KERNEL);
+-  if (!n)
+-	return -ENOMEM;
++	n = kzalloc(sizeof(*n), GFP_KERNEL);
++	if (!n)
++		return -ENOMEM;
+ 
+-  n->qpd = qpd;
++	n->qpd = qpd;
+ 
+-  pdd = qpd_to_pdd(qpd);
+-  /* Retrieve PD base */
+-  pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
++	pdd = qpd_to_pdd(qpd);
++	/* Retrieve PD base */
++	pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->vm);
+ 
+-  dqm_lock(dqm);
+-  list_add(&n->list, &dqm->queues);
++	dqm_lock(dqm);
++	list_add(&n->list, &dqm->queues);
+ 
+-  /* Update PD Base in QPD */
+-  qpd->page_table_base = pd_base;
+-  pr_debug("Updated PD address to 0x%llx\n", pd_base);
++	/* Update PD Base in QPD */
++	qpd->page_table_base = pd_base;
++	pr_debug("Updated PD address to 0x%llx\n", pd_base);
+ 
+-  retval = dqm->asic_ops.update_qpd(dqm, qpd);
++	retval = dqm->asic_ops.update_qpd(dqm, qpd);
+ 
+-  dqm->processes_count++;
+-  kfd_inc_compute_active(dqm->dev);
++	dqm->processes_count++;
++	kfd_inc_compute_active(dqm->dev);
+ 
+-  dqm_unlock(dqm);
++	dqm_unlock(dqm);
+ 
+-  return retval;
++	return retval;
+ }
+ 
+ static int unregister_process(struct device_queue_manager *dqm,
+-							  struct qcm_process_device *qpd)
++					struct qcm_process_device *qpd)
+ {
+-  int retval;
+-  struct device_process_node *cur, *next;
++	int retval;
++	struct device_process_node *cur, *next;
+ 
+-  pr_debug("qpd->queues_list is %s\n",
+-		   list_empty(&qpd->queues_list) ? "empty" : "not empty");
++	pr_debug("qpd->queues_list is %s\n",
++			list_empty(&qpd->queues_list) ? "empty" : "not empty");
+ 
+-  retval = 0;
+-  dqm_lock(dqm);
++	retval = 0;
++	dqm_lock(dqm);
+ 
+-  list_for_each_entry_safe(cur, next, &dqm->queues, list) {
+-	if (qpd == cur->qpd) {
+-	  list_del(&cur->list);
+-	  kfree(cur);
+-	  dqm->processes_count--;
+-	  kfd_dec_compute_active(dqm->dev);
+-	  goto out;
++	list_for_each_entry_safe(cur, next, &dqm->queues, list) {
++		if (qpd == cur->qpd) {
++			list_del(&cur->list);
++			kfree(cur);
++			dqm->processes_count--;
++			kfd_dec_compute_active(dqm->dev);
++			goto out;
++		}
+ 	}
+-  }
+-  /* qpd not found in dqm list */
+-  retval = 1;
++	/* qpd not found in dqm list */
++	retval = 1;
+ out:
+-  dqm_unlock(dqm);
+-  return retval;
++	dqm_unlock(dqm);
++	return retval;
+ }
+ 
+-  static int
++static int
+ set_pasid_vmid_mapping(struct device_queue_manager *dqm, unsigned int pasid,
+-					   unsigned int vmid)
++			unsigned int vmid)
+ {
+-  return dqm->dev->kfd2kgd->set_pasid_vmid_mapping(
+-												   dqm->dev->kgd, pasid, vmid);
++	return dqm->dev->kfd2kgd->set_pasid_vmid_mapping(
++						dqm->dev->kgd, pasid, vmid);
+ }
+ 
+ static void init_interrupts(struct device_queue_manager *dqm)
+ {
+-  unsigned int i;
++	unsigned int i;
+ 
+-  for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++)
+-	if (is_pipe_enabled(dqm, 0, i))
+-	  dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, i);
++	for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++)
++		if (is_pipe_enabled(dqm, 0, i))
++			dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, i);
+ }
+ 
+ static int initialize_nocpsch(struct device_queue_manager *dqm)
+ {
+-  int pipe, queue;
++	int pipe, queue;
+ 
+-  pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
++	pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
+ 
+-  dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm),
+-								  sizeof(unsigned int), GFP_KERNEL);
+-  if (!dqm->allocated_queues)
+-	return -ENOMEM;
++	dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm),
++					sizeof(unsigned int), GFP_KERNEL);
++	if (!dqm->allocated_queues)
++		return -ENOMEM;
+ 
+-  mutex_init(&dqm->lock_hidden);
+-  INIT_LIST_HEAD(&dqm->queues);
+-  dqm->queue_count = dqm->next_pipe_to_allocate = 0;
+-  dqm->sdma_queue_count = 0;
+-  dqm->xgmi_sdma_queue_count = 0;
+-  dqm->trap_debug_vmid = 0;
++	mutex_init(&dqm->lock_hidden);
++	INIT_LIST_HEAD(&dqm->queues);
++	dqm->queue_count = dqm->next_pipe_to_allocate = 0;
++	dqm->sdma_queue_count = 0;
++	dqm->xgmi_sdma_queue_count = 0;
++	dqm->trap_debug_vmid = 0;
+ 
+-  for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
+-	int pipe_offset = pipe * get_queues_per_pipe(dqm);
++	for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
++		int pipe_offset = pipe * get_queues_per_pipe(dqm);
+ 
+-	for (queue = 0; queue < get_queues_per_pipe(dqm); queue++)
+-	  if (test_bit(pipe_offset + queue,
+-				   dqm->dev->shared_resources.queue_bitmap))
+-		dqm->allocated_queues[pipe] |= 1 << queue;
+-  }
++		for (queue = 0; queue < get_queues_per_pipe(dqm); queue++)
++			if (test_bit(pipe_offset + queue,
++				     dqm->dev->shared_resources.queue_bitmap))
++				dqm->allocated_queues[pipe] |= 1 << queue;
++	}
+ 
+-  dqm->vmid_bitmap = (1 << dqm->dev->vm_info.vmid_num_kfd) - 1;
+-  dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
+-  dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
++	dqm->vmid_bitmap = (1 << dqm->dev->vm_info.vmid_num_kfd) - 1;
++	dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
++ 	dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
+ 
+-  return 0;
++	return 0;
+ }
+ 
+ static void uninitialize(struct device_queue_manager *dqm)
+ {
+-  int i;
++	int i;
+ 
+-  WARN_ON(dqm->queue_count > 0 || dqm->processes_count > 0);
++	WARN_ON(dqm->queue_count > 0 || dqm->processes_count > 0);
+ 
+-  kfree(dqm->allocated_queues);
+-  for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++)
+-	kfree(dqm->mqd_mgrs[i]);
+-  mutex_destroy(&dqm->lock_hidden);
+-  kfd_gtt_sa_free(dqm->dev, dqm->pipeline_mem);
++	kfree(dqm->allocated_queues);
++	for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++)
++		kfree(dqm->mqd_mgrs[i]);
++	mutex_destroy(&dqm->lock_hidden);
++	kfd_gtt_sa_free(dqm->dev, dqm->pipeline_mem);
+ }
+ 
+ static int start_nocpsch(struct device_queue_manager *dqm)
+ {
+-  init_interrupts(dqm);
+-  return pm_init(&dqm->packets, dqm);
++	init_interrupts(dqm);
++	return pm_init(&dqm->packets, dqm);
+ }
+ 
+ static int stop_nocpsch(struct device_queue_manager *dqm)
+ {
+-  pm_uninit(&dqm->packets);
+-  return 0;
++	pm_uninit(&dqm->packets);
++	return 0;
+ }
+ 
+ static int allocate_sdma_queue(struct device_queue_manager *dqm,
+-							   struct queue *q)
+-{
+-  int bit;
+-
+-  if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
+-	if (dqm->sdma_bitmap == 0)
+-	  return -ENOMEM;
+-	bit = __ffs64(dqm->sdma_bitmap);
+-	dqm->sdma_bitmap &= ~(1ULL << bit);
+-	q->sdma_id = bit;
+-	q->properties.sdma_engine_id = q->sdma_id %
+-	  get_num_sdma_engines(dqm);
+-	q->properties.sdma_queue_id = q->sdma_id /
+-	  get_num_sdma_engines(dqm);
+-  } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
+-	if (dqm->xgmi_sdma_bitmap == 0)
+-	  return -ENOMEM;
+-	bit = __ffs64(dqm->xgmi_sdma_bitmap);
+-	dqm->xgmi_sdma_bitmap &= ~(1ULL << bit);
+-	q->sdma_id = bit;
+-	/* sdma_engine_id is sdma id including
+-	 * both PCIe-optimized SDMAs and XGMI-
+-	 * optimized SDMAs. The calculation below
+-	 * assumes the first N engines are always
+-	 * PCIe-optimized ones
+-	 */
+-	q->properties.sdma_engine_id = get_num_sdma_engines(dqm) +
+-	  q->sdma_id % get_num_xgmi_sdma_engines(dqm);
+-	q->properties.sdma_queue_id = q->sdma_id /
+-	  get_num_xgmi_sdma_engines(dqm);
+-  }
++				struct queue *q)
++{
++	int bit;
+ 
+-  pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id);
+-  pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id);
++	if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
++		if (dqm->sdma_bitmap == 0)
++			return -ENOMEM;
++		bit = __ffs64(dqm->sdma_bitmap);
++		dqm->sdma_bitmap &= ~(1ULL << bit);
++		q->sdma_id = bit;
++		q->properties.sdma_engine_id = q->sdma_id %
++				get_num_sdma_engines(dqm);
++		q->properties.sdma_queue_id = q->sdma_id /
++				get_num_sdma_engines(dqm);
++	} else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
++		if (dqm->xgmi_sdma_bitmap == 0)
++			return -ENOMEM;
++		bit = __ffs64(dqm->xgmi_sdma_bitmap);
++		dqm->xgmi_sdma_bitmap &= ~(1ULL << bit);
++		q->sdma_id = bit;
++		/* sdma_engine_id is sdma id including
++		 * both PCIe-optimized SDMAs and XGMI-
++		 * optimized SDMAs. The calculation below
++		 * assumes the first N engines are always
++		 * PCIe-optimized ones
++		 */
++		q->properties.sdma_engine_id = get_num_sdma_engines(dqm) +
++				q->sdma_id % get_num_xgmi_sdma_engines(dqm);
++		q->properties.sdma_queue_id = q->sdma_id /
++				get_num_xgmi_sdma_engines(dqm);
++	}
++
++	pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id);
++	pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id);
+ 
+-  return 0;
++	return 0;
+ }
+ 
+ static void deallocate_sdma_queue(struct device_queue_manager *dqm,
+-								  struct queue *q)
++				struct queue *q)
+ {
+-  if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
+-	if (q->sdma_id >= get_num_sdma_queues(dqm))
+-	  return;
+-	dqm->sdma_bitmap |= (1ULL << q->sdma_id);
+-  } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
+-	if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm))
+-	  return;
+-	dqm->xgmi_sdma_bitmap |= (1ULL << q->sdma_id);
+-  }
++	if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
++		if (q->sdma_id >= get_num_sdma_queues(dqm))
++			return;
++		dqm->sdma_bitmap |= (1ULL << q->sdma_id);
++	} else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
++		if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm))
++			return;
++		dqm->xgmi_sdma_bitmap |= (1ULL << q->sdma_id);
++	}
+ }
+ 
+ /*
+@@ -1053,60 +1053,60 @@ static void deallocate_sdma_queue(struct device_queue_manager *dqm,
+ 
+ static int set_sched_resources(struct device_queue_manager *dqm)
+ {
+-  int i, mec;
+-  struct scheduling_resources res;
++	int i, mec;
++	struct scheduling_resources res;
+ 
+-  res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap;
++	res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap;
+ 
+-  res.queue_mask = 0;
+-  for (i = 0; i < KGD_MAX_QUEUES; ++i) {
+-	mec = (i / dqm->dev->shared_resources.num_queue_per_pipe)
+-	  / dqm->dev->shared_resources.num_pipe_per_mec;
++	res.queue_mask = 0;
++	for (i = 0; i < KGD_MAX_QUEUES; ++i) {
++		mec = (i / dqm->dev->shared_resources.num_queue_per_pipe)
++			/ dqm->dev->shared_resources.num_pipe_per_mec;
+ 
+-	if (!test_bit(i, dqm->dev->shared_resources.queue_bitmap))
+-	  continue;
++		if (!test_bit(i, dqm->dev->shared_resources.queue_bitmap))
++			continue;
+ 
+-	/* only acquire queues from the first MEC */
+-	if (mec > 0)
+-	  continue;
++		/* only acquire queues from the first MEC */
++		if (mec > 0)
++			continue;
+ 
+-	/* This situation may be hit in the future if a new HW
+-	 * generation exposes more than 64 queues. If so, the
+-	 * definition of res.queue_mask needs updating
+-	 */
+-	if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) {
+-	  pr_err("Invalid queue enabled by amdgpu: %d\n", i);
+-	  break;
+-	}
++		/* This situation may be hit in the future if a new HW
++		 * generation exposes more than 64 queues. If so, the
++		 * definition of res.queue_mask needs updating
++		 */
++		if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) {
++			pr_err("Invalid queue enabled by amdgpu: %d\n", i);
++			break;
++		}
+ 
+-	res.queue_mask |= (1ull << i);
+-  }
+-  res.gws_mask = ~0ull;
+-  res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0;
++		res.queue_mask |= (1ull << i);
++	}
++	res.gws_mask = ~0ull;
++	res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0;
+ 
+-  pr_debug("Scheduling resources:\n"
+-		   "vmid mask: 0x%8X\n"
+-		   "queue mask: 0x%8llX\n",
+-		   res.vmid_mask, res.queue_mask);
++	pr_debug("Scheduling resources:\n"
++			"vmid mask: 0x%8X\n"
++			"queue mask: 0x%8llX\n",
++			res.vmid_mask, res.queue_mask);
+ 
+-  return pm_send_set_resources(&dqm->packets, &res);
++	return pm_send_set_resources(&dqm->packets, &res);
+ }
+ 
+ static int initialize_cpsch(struct device_queue_manager *dqm)
+ {
+-  pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
++	pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
+ 
+-  mutex_init(&dqm->lock_hidden);
+-  INIT_LIST_HEAD(&dqm->queues);
+-  dqm->queue_count = dqm->processes_count = 0;
+-  dqm->sdma_queue_count = 0;
+-  dqm->xgmi_sdma_queue_count = 0;
+-  dqm->active_runlist = false;
+-  dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
+-  dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
+-  dqm->trap_debug_vmid = 0;
++	mutex_init(&dqm->lock_hidden);
++	INIT_LIST_HEAD(&dqm->queues);
++	dqm->queue_count = dqm->processes_count = 0;
++	dqm->sdma_queue_count = 0;
++	dqm->xgmi_sdma_queue_count = 0;
++	dqm->active_runlist = false;
++	dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
++	dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
++	dqm->trap_debug_vmid = 0;
+ 
+-  INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception);
++	INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception);
+ 
+ 	if (dqm->dev->kfd2kgd->get_iq_wait_times)
+ 		dqm->dev->kfd2kgd->get_iq_wait_times(dqm->dev->kgd,
+@@ -1116,141 +1116,140 @@ static int initialize_cpsch(struct device_queue_manager *dqm)
+ 
+ static int start_cpsch(struct device_queue_manager *dqm)
+ {
+-  int retval;
++	int retval;
+ 
+-  retval = 0;
++	retval = 0;
+ 
+-  retval = pm_init(&dqm->packets, dqm);
+-  if (retval)
+-	goto fail_packet_manager_init;
++	retval = pm_init(&dqm->packets, dqm);
++	if (retval)
++		goto fail_packet_manager_init;
+ 
+-  retval = set_sched_resources(dqm);
+-  if (retval)
+-	goto fail_set_sched_resources;
++	retval = set_sched_resources(dqm);
++	if (retval)
++		goto fail_set_sched_resources;
+ 
+-  pr_debug("Allocating fence memory\n");
++	pr_debug("Allocating fence memory\n");
+ 
+-  /* allocate fence memory on the gart */
+-  retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
+-							   &dqm->fence_mem);
++	/* allocate fence memory on the gart */
++	retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
++					&dqm->fence_mem);
+ 
+-  if (retval)
+-	goto fail_allocate_vidmem;
++	if (retval)
++		goto fail_allocate_vidmem;
+ 
+-  dqm->fence_addr = dqm->fence_mem->cpu_ptr;
+-  dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr;
++	dqm->fence_addr = dqm->fence_mem->cpu_ptr;
++	dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr;
+ 
+-  init_interrupts(dqm);
++	init_interrupts(dqm);
+ 
+-  dqm_lock(dqm);
+-  /* clear hang status when driver try to start the hw scheduler */
+-  dqm->is_hws_hang = false;
+-  execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
+-					   USE_DEFAULT_GRACE_PERIOD);
+-  dqm_unlock(dqm);
++	dqm_lock(dqm);
++	/* clear hang status when driver try to start the hw scheduler */
++	dqm->is_hws_hang = false;
++	execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
++			USE_DEFAULT_GRACE_PERIOD);
++	dqm_unlock(dqm);
+ 
+-  return 0;
++	return 0;
+ fail_allocate_vidmem:
+ fail_set_sched_resources:
+-  pm_uninit(&dqm->packets);
++	pm_uninit(&dqm->packets);
+ fail_packet_manager_init:
+-  return retval;
++	return retval;
+ }
+ 
+ static int stop_cpsch(struct device_queue_manager *dqm)
+ {
+-  dqm_lock(dqm);
+-  unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
++	dqm_lock(dqm);
++	unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
+ 					 USE_DEFAULT_GRACE_PERIOD);
+-  dqm_unlock(dqm);
++	dqm_unlock(dqm);
+ 
+-  kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
+-  pm_uninit(&dqm->packets);
++	kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
++	pm_uninit(&dqm->packets);
+ 
+-  return 0;
++	return 0;
+ }
+ 
+ static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,
+-									 struct kernel_queue *kq,
+-									 struct qcm_process_device *qpd)
++					struct kernel_queue *kq,
++					struct qcm_process_device *qpd)
+ {
+-  dqm_lock(dqm);
+-  if (dqm->total_queue_count >= max_num_of_queues_per_device) {
+-	pr_warn("Can't create new kernel queue because %d queues were already created\n",
+-			dqm->total_queue_count);
+-	dqm_unlock(dqm);
+-	return -EPERM;
+-  }
++	dqm_lock(dqm);
++	if (dqm->total_queue_count >= max_num_of_queues_per_device) {
++		pr_warn("Can't create new kernel queue because %d queues were already created\n",
++				dqm->total_queue_count);
++		dqm_unlock(dqm);
++		return -EPERM;
++	}
+ 
+-  /*
+-   * Unconditionally increment this counter, regardless of the queue's
+-   * type or whether the queue is active.
+-   */
+-  dqm->total_queue_count++;
+-  pr_debug("Total of %d queues are accountable so far\n",
+-		   dqm->total_queue_count);
++	/*
++	 * Unconditionally increment this counter, regardless of the queue's
++	 * type or whether the queue is active.
++	 */
++	dqm->total_queue_count++;
++	pr_debug("Total of %d queues are accountable so far\n",
++			dqm->total_queue_count);
+ 
+-  list_add(&kq->list, &qpd->priv_queue_list);
+-  dqm->queue_count++;
+-  qpd->is_debug = true;
+-  execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
+-					   USE_DEFAULT_GRACE_PERIOD);
+-  dqm_unlock(dqm);
++	list_add(&kq->list, &qpd->priv_queue_list);
++	dqm->queue_count++;
++	qpd->is_debug = true;
++	execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
++				USE_DEFAULT_GRACE_PERIOD);
++	dqm_unlock(dqm);
+ 
+-  return 0;
++	return 0;
+ }
+ 
+ static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm,
+-									   struct kernel_queue *kq,
+-									   struct qcm_process_device *qpd)
+-{
+-  dqm_lock(dqm);
+-  list_del(&kq->list);
+-  dqm->queue_count--;
+-  qpd->is_debug = false;
+-  execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
+-					   USE_DEFAULT_GRACE_PERIOD);
+-  /*
+-   * Unconditionally decrement this counter, regardless of the queue's
+-   * type.
+-   */
+-  dqm->total_queue_count--;
+-  pr_debug("Total of %d queues are accountable so far\n",
+-		   dqm->total_queue_count);
+-  dqm_unlock(dqm);
++					struct kernel_queue *kq,
++					struct qcm_process_device *qpd)
++{
++	dqm_lock(dqm);
++	list_del(&kq->list);
++	dqm->queue_count--;
++	qpd->is_debug = false;
++	execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
++			USE_DEFAULT_GRACE_PERIOD);
++	/*
++	 * Unconditionally decrement this counter, regardless of the queue's
++	 * type.
++	 */
++	dqm->total_queue_count--;
++	pr_debug("Total of %d queues are accountable so far\n",
++			dqm->total_queue_count);
++	dqm_unlock(dqm);
+ }
+ 
+ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
+-							  struct qcm_process_device *qpd)
++			struct qcm_process_device *qpd)
+ {
+-  int retval;
+-  struct mqd_manager *mqd_mgr;
++	int retval;
++	struct mqd_manager *mqd_mgr;
+ 
+-  if (dqm->total_queue_count >= max_num_of_queues_per_device) {
+-	pr_warn("Can't create new usermode queue because %d queues were already created\n",
+-			dqm->total_queue_count);
+-	retval = -EPERM;
+-	goto out;
+-  }
++	if (dqm->total_queue_count >= max_num_of_queues_per_device) {
++		pr_warn("Can't create new usermode queue because %d queues were already created\n",
++				dqm->total_queue_count);
++		retval = -EPERM;
++		goto out;
++	}
+ 
+-  if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
+-	  q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
+-	dqm_lock(dqm);
+-	retval = allocate_sdma_queue(dqm, q);
+-	dqm_unlock(dqm);
+-	if (retval)
+-	  goto out;
+-  }
++	if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
++		q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
++		dqm_lock(dqm);
++		retval = allocate_sdma_queue(dqm, q);
++		dqm_unlock(dqm);
++		if (retval)
++			goto out;
++	}
+ 
+-  retval = allocate_doorbell(qpd, q);
+-  if (retval)
+-	goto out_deallocate_sdma_queue;
++	retval = allocate_doorbell(qpd, q);
++	if (retval)
++		goto out_deallocate_sdma_queue;
+ 
+-  mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
+-													   q->properties.type)];
+-  q->properties.is_suspended = false;
++	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
++			q->properties.type)];
+ 
+-  	if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
++	if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
+ 		q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
+ 		dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
+ 	q->properties.tba_addr = qpd->tba_addr;
+@@ -1268,6 +1267,7 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
+ 	 * updates the is_evicted flag but is a no-op otherwise.
+ 	 */
+ 	q->properties.is_evicted = !!qpd->evicted;
++	q->properties.is_suspended = false;
+ 	mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
+ 				&q->gart_mqd_addr, &q->properties);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3894-drm-amdgpu-drop-experimental-flag-for-amd-staging-dr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3894-drm-amdgpu-drop-experimental-flag-for-amd-staging-dr.patch
new file mode 100644
index 00000000..c1610dc5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3894-drm-amdgpu-drop-experimental-flag-for-amd-staging-dr.patch
@@ -0,0 +1,45 @@
+From 3c28e0b95b1049f70fef4da2a67fcb805562f97e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 19 Sep 2019 13:27:20 -0500
+Subject: [PATCH 3894/4256] drm/amdgpu: drop experimental flag for
+ amd-staging-drm-next
+
+This is the active development branch so the driver is
+expected to load on everything supported.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 11 ++++-------
+ 1 file changed, 4 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 952ed019fb22..0d8d292eb236 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1063,19 +1063,16 @@ static const struct pci_device_id pciidlist[] = {
+ 	{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
+ 	{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
+ 	/* Navi14 */
+-	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
+-	{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
+-	{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
++	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
++	{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
++	{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
+ 
+ 	/* Renoir */
+ 	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
+ 
+ 	/* Navi12 */
+ 	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
+-
+-	/* Navi12 */
+-	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT},
+-	{0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT},
++	{0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
+ 
+ 	{0, 0, 0}
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3895-drm-amdgpu-fix-documentation-for-amdgpu_gem_prime_ex.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3895-drm-amdgpu-fix-documentation-for-amdgpu_gem_prime_ex.patch
new file mode 100644
index 00000000..e5f0d2bc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3895-drm-amdgpu-fix-documentation-for-amdgpu_gem_prime_ex.patch
@@ -0,0 +1,32 @@
+From 89e57081994d82d26bc15f94a594197823d2776d Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 19 Sep 2019 14:18:10 -0500
+Subject: [PATCH 3895/4256] drm/amdgpu: fix documentation for
+ amdgpu_gem_prime_export
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Drop extra function parameter.
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+index 91f023c928dc..be231f91359b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+@@ -337,7 +337,6 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = {
+ 
+ /**
+  * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
+- * @dev: DRM device
+  * @gobj: GEM BO
+  * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
+  *
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3896-drm-amdgpu-mn-fix-documentation-for-amdgpu_mn_read_l.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3896-drm-amdgpu-mn-fix-documentation-for-amdgpu_mn_read_l.patch
new file mode 100644
index 00000000..b1da0140
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3896-drm-amdgpu-mn-fix-documentation-for-amdgpu_mn_read_l.patch
@@ -0,0 +1,33 @@
+From bd7d31534a02c8b4c04fe73d741d69e479bafa32 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 19 Sep 2019 14:24:11 -0500
+Subject: [PATCH 3896/4256] drm/amdgpu/mn: fix documentation for
+ amdgpu_mn_read_lock
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Document the new parameter.
+
+Fixes: 93065ac753e4 ("mm, oom: distinguish blockable mode for mmu notifiers")
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+index e483bf5191cd..b9b5733ff836 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+@@ -173,6 +173,7 @@ void amdgpu_mn_unlock(struct amdgpu_mn *mn)
+  * amdgpu_mn_read_lock - take the read side lock for this notifier
+  *
+  * @amn: our notifier
++ * @blockable: is the notifier blockable
+  */
+ static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable)
+ {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3897-drm-amdgpu-vm-fix-up-documentation-in-amdgpu_vm.c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3897-drm-amdgpu-vm-fix-up-documentation-in-amdgpu_vm.c.patch
new file mode 100644
index 00000000..592abf39
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3897-drm-amdgpu-vm-fix-up-documentation-in-amdgpu_vm.c.patch
@@ -0,0 +1,105 @@
+From 889793dccbdf347f585d85d3e375d85d2b314690 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 19 Sep 2019 14:39:08 -0500
+Subject: [PATCH 3897/4256] drm/amdgpu/vm: fix up documentation in amdgpu_vm.c
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Missing parameters, wrong comment type, etc.
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 ++++++++++-------
+ 1 file changed, 10 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 91b11c765921..8566f6b0729a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -342,7 +342,7 @@ static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt)
+ 	return container_of(parent->vm_bo, struct amdgpu_vm_pt, base);
+ }
+ 
+-/**
++/*
+  * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
+  */
+ struct amdgpu_vm_pt_cursor {
+@@ -483,6 +483,7 @@ static void amdgpu_vm_pt_next(struct amdgpu_device *adev,
+  *
+  * @adev: amdgpu_device structure
+  * @vm: amdgpu_vm structure
++ * @start: optional cursor to start with
+  * @cursor: state to initialize
+  *
+  * Starts a deep first traversal of the PD/PT tree.
+@@ -536,7 +537,7 @@ static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev,
+ 		amdgpu_vm_pt_ancestor(cursor);
+ }
+ 
+-/**
++/*
+  * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs
+  */
+ #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)		\
+@@ -854,6 +855,7 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+  * @adev: amdgpu_device pointer
+  * @vm: VM to allocate page tables for
+  * @cursor: Which page table to allocate
++ * @direct: use a direct update
+  *
+  * Make sure a specific page table or directory is allocated.
+  *
+@@ -1193,10 +1195,10 @@ uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
+ 	return result;
+ }
+ 
+-/*
++/**
+  * amdgpu_vm_update_pde - update a single level in the hierarchy
+  *
+- * @param: parameters for the update
++ * @params: parameters for the update
+  * @vm: requested vm
+  * @entry: entry to update
+  *
+@@ -1220,7 +1222,7 @@ static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params,
+ 	return vm->update_funcs->update(params, bo, pde, pt, 1, 0, flags);
+ }
+ 
+-/*
++/**
+  * amdgpu_vm_invalidate_pds - mark all PDs as invalid
+  *
+  * @adev: amdgpu_device pointer
+@@ -1239,7 +1241,7 @@ static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
+ 			amdgpu_vm_bo_relocated(&entry->base);
+ }
+ 
+-/*
++/**
+  * amdgpu_vm_update_pdes - make sure that all directories are valid
+  *
+  * @adev: amdgpu_device pointer
+@@ -1291,7 +1293,7 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
+ 	return r;
+ }
+ 
+-/**
++/*
+  * amdgpu_vm_update_flags - figure out flags for PTE updates
+  *
+  * Make sure to set the right flags for the PTEs at the desired level.
+@@ -2815,6 +2817,7 @@ static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
+  *
+  * @adev: amdgpu_device pointer
+  * @vm: requested vm
++ * @pasid: pasid to use
+  *
+  * This only works on GFX VMs that don't have any BOs added and no
+  * page tables allocated yet.
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3898-drm-amdgpu-ih-fix-documentation-in-amdgpu_irq_dispat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3898-drm-amdgpu-ih-fix-documentation-in-amdgpu_irq_dispat.patch
new file mode 100644
index 00000000..eecaaf1d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3898-drm-amdgpu-ih-fix-documentation-in-amdgpu_irq_dispat.patch
@@ -0,0 +1,33 @@
+From d27602b7ca55fdbfdcc76febc0a6658d505a10a0 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 19 Sep 2019 14:40:57 -0500
+Subject: [PATCH 3898/4256] drm/amdgpu/ih: fix documentation in
+ amdgpu_irq_dispatch
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fix parameters.
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+index d130a30e9155..d391087844e0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+@@ -380,7 +380,7 @@ int amdgpu_irq_add_id(struct amdgpu_device *adev,
+  * amdgpu_irq_dispatch - dispatch IRQ to IP blocks
+  *
+  * @adev: amdgpu device pointer
+- * @entry: interrupt vector pointer
++ * @ih: interrupt ring instance
+  *
+  * Dispatches IRQ to IP blocks.
+  */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3899-drm-amdgpu-fix-documentation-for-amdgpu_pm.c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3899-drm-amdgpu-fix-documentation-for-amdgpu_pm.c.patch
new file mode 100644
index 00000000..0108068a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3899-drm-amdgpu-fix-documentation-for-amdgpu_pm.c.patch
@@ -0,0 +1,71 @@
+From 9d28186bc88310c6627777e5e7d43e3e5d013095 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 19 Sep 2019 15:03:27 -0500
+Subject: [PATCH 3899/4256] drm/amdgpu: fix documentation for amdgpu_pm.c
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fix DOC link name, clean up formatting in pp_dpm_* section.
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ Documentation/gpu/amdgpu.rst           |  6 +++---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 13 +++++++++----
+ 2 files changed, 12 insertions(+), 7 deletions(-)
+
+diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
+index 5acdd1842ea2..80db5d89cd49 100644
+--- a/Documentation/gpu/amdgpu.rst
++++ b/Documentation/gpu/amdgpu.rst
+@@ -130,11 +130,11 @@ pp_od_clk_voltage
+ .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+    :doc: pp_od_clk_voltage
+ 
+-pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
+-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++pp_dpm_*
++~~~~~~~~
+ 
+ .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+-   :doc: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
++   :doc: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
+ 
+ pp_power_profile_mode
+ ~~~~~~~~~~~~~~~~~~~~~
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index 5cf8d72e3859..571d10de9eca 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -802,8 +802,7 @@ static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
+ }
+ 
+ /**
+- * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk
+- * pp_dpm_pcie
++ * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
+  *
+  * The amdgpu driver provides a sysfs API for adjusting what power levels
+  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
+@@ -819,9 +818,15 @@ static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
+  *
+  * To manually adjust these states, first select manual using
+  * power_dpm_force_performance_level.
+- * Secondly,Enter a new value for each level by inputing a string that
++ * Secondly, enter a new value for each level by inputing a string that
+  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
+- * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
++ * E.g.,
++ *
++ * .. code-block:: bash
++ *
++ *	echo "4 5 6" > pp_dpm_sclk
++ *
++ * will enable sclk levels 4, 5, and 6.
+  *
+  * NOTE: change to the dcefclk max dpm level is not supported now
+  */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3900-drm-amdgpu-ras-fix-and-update-the-documentation-for-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3900-drm-amdgpu-ras-fix-and-update-the-documentation-for-.patch
new file mode 100644
index 00000000..160d09d2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3900-drm-amdgpu-ras-fix-and-update-the-documentation-for-.patch
@@ -0,0 +1,150 @@
+From f3174d9652f9f5a198677a5cc789506612461803 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 19 Sep 2019 15:09:56 -0500
+Subject: [PATCH 3900/4256] drm/amdgpu/ras: fix and update the documentation
+ for RAS
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add new sections to amdgpu.rst, fix up formatting issues,
+add additional documentation to each section.
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ Documentation/gpu/amdgpu.rst            | 24 ++++++++++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 53 +++++++++++++++++++++----
+ 2 files changed, 68 insertions(+), 9 deletions(-)
+
+diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
+index 80db5d89cd49..5b9eaf23558e 100644
+--- a/Documentation/gpu/amdgpu.rst
++++ b/Documentation/gpu/amdgpu.rst
+@@ -79,12 +79,32 @@ AMDGPU XGMI Support
+ .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+    :internal:
+ 
+-AMDGPU RAS debugfs control interface
+-====================================
++AMDGPU RAS Support
++==================
++
++RAS debugfs/sysfs Control and Error Injection Interfaces
++--------------------------------------------------------
+ 
+ .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+    :doc: AMDGPU RAS debugfs control interface
+ 
++RAS Error Count sysfs Interface
++-------------------------------
++
++.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++   :doc: AMDGPU RAS sysfs Error Count Interface
++
++RAS EEPROM debugfs Interface
++----------------------------
++
++.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++   :doc: AMDGPU RAS debugfs EEPROM table reset interface
++
++RAS VRAM Bad Pages sysfs Interface
++----------------------------------
++
++.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++   :doc: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
+ 
+ .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+    :internal:
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index f5aea49f2ab3..48541adb12fb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -314,7 +314,18 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *
+ /**
+  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
+  *
+- * Usage: echo 1 > ../ras/ras_eeprom_reset will reset EEPROM table to 0 entries.
++ * Some boards contain an EEPROM which is used to persistently store a list of
++ * bad pages containing ECC errors detected in vram.  This interface provides
++ * a way to reset the EEPROM, e.g., after testing error injection.
++ *
++ * Usage:
++ *
++ * .. code-block:: bash
++ *
++ *	echo 1 > ../ras/ras_eeprom_reset
++ *
++ * will reset EEPROM table to 0 entries.
++ *
+  */
+ static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf,
+ 		size_t size, loff_t *pos)
+@@ -341,6 +352,27 @@ static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
+ 	.llseek = default_llseek
+ };
+ 
++/**
++ * DOC: AMDGPU RAS sysfs Error Count Interface
++ *
++ * It allows user to read the error count for each IP block on the gpu through
++ * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
++ *
++ * It outputs the multiple lines which report the uncorrected (ue) and corrected
++ * (ce) error counts.
++ *
++ * The format of one line is below,
++ *
++ * [ce|ue]: count
++ *
++ * Example:
++ *
++ * .. code-block:: bash
++ *
++ *	ue: 0
++ *	ce: 1
++ *
++ */
+ static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
+ 		struct device_attribute *attr, char *buf)
+ {
+@@ -785,8 +817,8 @@ static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
+ 	};
+ }
+ 
+-/*
+- * DOC: ras sysfs gpu_vram_bad_pages interface
++/**
++ * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
+  *
+  * It allows user to read the bad pages of vram on the gpu through
+  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
+@@ -798,14 +830,21 @@ static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
+  *
+  * gpu pfn and gpu page size are printed in hex format.
+  * flags can be one of below character,
++ *
+  * R: reserved, this gpu page is reserved and not able to use.
++ *
+  * P: pending for reserve, this gpu page is marked as bad, will be reserved
+- *    in next window of page_reserve.
++ * in next window of page_reserve.
++ *
+  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
+  *
+- * examples:
+- * 0x00000001 : 0x00001000 : R
+- * 0x00000002 : 0x00001000 : P
++ * Examples:
++ *
++ * .. code-block:: bash
++ *
++ *	0x00000001 : 0x00001000 : R
++ *	0x00000002 : 0x00001000 : P
++ *
+  */
+ 
+ static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3901-drm-amdkfd-fix-a-potential-NULL-pointer-dereference-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3901-drm-amdkfd-fix-a-potential-NULL-pointer-dereference-.patch
new file mode 100644
index 00000000..d90ad411
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3901-drm-amdkfd-fix-a-potential-NULL-pointer-dereference-.patch
@@ -0,0 +1,39 @@
+From 23c7d75e5bffdd247602a29350caf80535136af7 Mon Sep 17 00:00:00 2001
+From: Allen Pais <allen.pais@oracle.com>
+Date: Wed, 18 Sep 2019 22:00:31 +0530
+Subject: [PATCH 3901/4256] drm/amdkfd: fix a potential NULL pointer
+ dereference (v2)
+
+alloc_workqueue is not checked for errors and as a result,
+a potential NULL dereference could occur.
+
+v2 (Felix Kuehling):
+* Fix compile error (kfifo_free instead of fifo_free)
+* Return proper error code
+
+Signed-off-by: Allen Pais <allen.pais@oracle.com>
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
+index c56ac47cd318..4b642a288b97 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
+@@ -62,6 +62,11 @@ int kfd_interrupt_init(struct kfd_dev *kfd)
+ 	}
+ 
+ 	kfd->ih_wq = alloc_workqueue("KFD IH", WQ_HIGHPRI, 1);
++	if (unlikely(!kfd->ih_wq)) {
++                kfifo_free(&kfd->ih_fifo);
++                dev_err(kfd_chardev(), "Failed to allocate KFD IH workqueue\n");
++                return -ENOMEM;
++        }
+ 	spin_lock_init(&kfd->interrupt_lock);
+ 
+ 	INIT_WORK(&kfd->interrupt_work, interrupt_wq);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3902-drm-amdkfd-Add-an-error-print-if-SDMA-RLC-is-not-idl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3902-drm-amdkfd-Add-an-error-print-if-SDMA-RLC-is-not-idl.patch
new file mode 100644
index 00000000..8d8d2853
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3902-drm-amdkfd-Add-an-error-print-if-SDMA-RLC-is-not-idl.patch
@@ -0,0 +1,162 @@
+From 36b74818cd50f8e1dc5601cbc8fd7a4eada372ba Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Thu, 19 Sep 2019 12:42:34 -0400
+Subject: [PATCH 3902/4256] drm/amdkfd: Add an error print if SDMA RLC is not
+ idle
+
+The message will be useful when troubleshooting the issues.
+
+Change-Id: Id82bbe80810dccff67c5b1275e9779f6a945dc7a
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 8 ++++++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c  | 8 ++++++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c   | 8 ++++++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c   | 8 ++++++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c   | 8 ++++++--
+ 5 files changed, 30 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+index 7ef62f62abf9..ada4662a0842 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+@@ -153,8 +153,10 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 		data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+-		if (time_after(jiffies, end_jiffies))
++		if (time_after(jiffies, end_jiffies)) {
++			pr_err("SDMA RLC not idle in %s\n", __func__);
+ 			return -ETIME;
++		}
+ 		usleep_range(500, 1000);
+ 	}
+ 	data = RREG32(sdmax_gfx_context_cntl);
+@@ -272,8 +274,10 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ 		temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+-		if (time_after(jiffies, end_jiffies))
++		if (time_after(jiffies, end_jiffies)) {
++			pr_err("SDMA RLC not idle in %s\n", __func__);
+ 			return -ETIME;
++		}
+ 		usleep_range(500, 1000);
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+index 3aff2b5758e0..3b164c071f37 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+@@ -511,8 +511,10 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 		data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+-		if (time_after(jiffies, end_jiffies))
++		if (time_after(jiffies, end_jiffies)) {
++			pr_err("SDMA RLC not idle in %s\n", __func__);
+ 			return -ETIME;
++		}
+ 		usleep_range(500, 1000);
+ 	}
+ 	data = RREG32(sdmax_gfx_context_cntl);
+@@ -763,8 +765,10 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ 		temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+-		if (time_after(jiffies, end_jiffies))
++		if (time_after(jiffies, end_jiffies)) {
++			pr_err("SDMA RLC not idle in %s\n", __func__);
+ 			return -ETIME;
++		}
+ 		usleep_range(500, 1000);
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+index c73aac88d0ab..7eedb5c9fd1d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+@@ -429,8 +429,10 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 		data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+-		if (time_after(jiffies, end_jiffies))
++		if (time_after(jiffies, end_jiffies)) {
++			pr_err("SDMA RLC not idle in %s\n", __func__);
+ 			return -ETIME;
++		}
+ 		usleep_range(500, 1000);
+ 	}
+ 	if (m->sdma_engine_id) {
+@@ -662,8 +664,10 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ 		temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+-		if (time_after(jiffies, end_jiffies))
++		if (time_after(jiffies, end_jiffies)) {
++			pr_err("SDMA RLC not idle in %s\n", __func__);
+ 			return -ETIME;
++		}
+ 		usleep_range(500, 1000);
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+index 930b45b863cd..fafb42175656 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+@@ -421,8 +421,10 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 		data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+-		if (time_after(jiffies, end_jiffies))
++		if (time_after(jiffies, end_jiffies)) {
++			pr_err("SDMA RLC not idle in %s\n", __func__);
+ 			return -ETIME;
++		}
+ 		usleep_range(500, 1000);
+ 	}
+ 	if (m->sdma_engine_id) {
+@@ -666,8 +668,10 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ 		temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+-		if (time_after(jiffies, end_jiffies))
++		if (time_after(jiffies, end_jiffies)) {
++			pr_err("SDMA RLC not idle in %s\n", __func__);
+ 			return -ETIME;
++		}
+ 		usleep_range(500, 1000);
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+index 63c71a010865..e8d6d2dc19e7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+@@ -427,8 +427,10 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 		data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+-		if (time_after(jiffies, end_jiffies))
++		if (time_after(jiffies, end_jiffies)) {
++			pr_err("SDMA RLC not idle in %s\n", __func__);
+ 			return -ETIME;
++		}
+ 		usleep_range(500, 1000);
+ 	}
+ 	data = RREG32(sdmax_gfx_context_cntl);
+@@ -618,8 +620,10 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ 		temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+-		if (time_after(jiffies, end_jiffies))
++		if (time_after(jiffies, end_jiffies)) {
++			pr_err("SDMA RLC not idle in %s\n", __func__);
+ 			return -ETIME;
++		}
+ 		usleep_range(500, 1000);
+ 	}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3903-drm-amdkfd-Remove-excessive-print-when-reserving-doo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3903-drm-amdkfd-Remove-excessive-print-when-reserving-doo.patch
new file mode 100644
index 00000000..d567dc00
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3903-drm-amdkfd-Remove-excessive-print-when-reserving-doo.patch
@@ -0,0 +1,52 @@
+From 204c5a62eb751df26c022f4ec396f416a3e246a5 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Sat, 21 Sep 2019 02:01:50 -0400
+Subject: [PATCH 3903/4256] drm/amdkfd: Remove excessive print when reserving
+ doorbells
+
+The dozens of printing messages are compressed into 2 lines.
+
+Change-Id: I339b3eee06509973f76577091c4c4e9c70ed8248
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+index 9446cc45d80f..c14fdf3bda75 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+@@ -762,6 +762,8 @@ static int init_doorbell_bitmap(struct qcm_process_device *qpd,
+ 			struct kfd_dev *dev)
+ {
+ 	unsigned int i;
++	int range_start = dev->shared_resources.non_cp_doorbells_start;
++	int range_end = dev->shared_resources.non_cp_doorbells_end;
+ 
+ 	if (!KFD_IS_SOC15(dev->device_info->asic_family))
+ 		return 0;
+@@ -773,14 +775,16 @@ static int init_doorbell_bitmap(struct qcm_process_device *qpd,
+ 		return -ENOMEM;
+ 
+ 	/* Mask out doorbells reserved for SDMA, IH, and VCN on SOC15. */
++	pr_debug("reserved doorbell 0x%03x - 0x%03x\n", range_start, range_end);
++	pr_debug("reserved doorbell 0x%03x - 0x%03x\n",
++			range_start + KFD_QUEUE_DOORBELL_MIRROR_OFFSET,
++			range_end + KFD_QUEUE_DOORBELL_MIRROR_OFFSET);
++
+ 	for (i = 0; i < KFD_MAX_NUM_OF_QUEUES_PER_PROCESS / 2; i++) {
+-		if (i >= dev->shared_resources.non_cp_doorbells_start
+-			&& i <= dev->shared_resources.non_cp_doorbells_end) {
++		if (i >= range_start && i <= range_end) {
+ 			set_bit(i, qpd->doorbell_bitmap);
+ 			set_bit(i + KFD_QUEUE_DOORBELL_MIRROR_OFFSET,
+ 				qpd->doorbell_bitmap);
+-			pr_debug("reserved doorbell 0x%03x and 0x%03x\n", i,
+-				i + KFD_QUEUE_DOORBELL_MIRROR_OFFSET);
+ 		}
+ 	}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3904-drm-amdkfd-Remove-unnecessary-pm_init-for-non-HWS-mo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3904-drm-amdkfd-Remove-unnecessary-pm_init-for-non-HWS-mo.patch
new file mode 100644
index 00000000..1dc40ba0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3904-drm-amdkfd-Remove-unnecessary-pm_init-for-non-HWS-mo.patch
@@ -0,0 +1,46 @@
+From 1ca224f36a896a2ae19c584ab2ee769125a0e66f Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Tue, 22 Jan 2019 20:09:17 -0500
+Subject: [PATCH 3904/4256] drm/amdkfd: Remove unnecessary pm_init() for non
+ HWS mode
+
+The packet manager is not needed for non HWS mode except Hawaii, so only
+initialize it for Hawaii under non HWS mode. This will simplify debugging
+under non HWS mode for all new asics, because it eliminates one variable
+out of the equation in non HWS mode
+
+Change-Id: Ie2b61b546299a50366b9ab97900f4bb13de33d5b
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 787b936a026d..62c612cff26b 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -985,12 +985,18 @@ static void uninitialize(struct device_queue_manager *dqm)
+ static int start_nocpsch(struct device_queue_manager *dqm)
+ {
+ 	init_interrupts(dqm);
+-	return pm_init(&dqm->packets, dqm);
++	
++	if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
++		return pm_init(&dqm->packets, dqm);
++	
++	return 0;
+ }
+ 
+ static int stop_nocpsch(struct device_queue_manager *dqm)
+ {
+-	pm_uninit(&dqm->packets);
++	if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
++		pm_uninit(&dqm->packets);
++	
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3905-drm-amdkfd-Fix-NULL-pointer-dereference-for-set_scra.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3905-drm-amdkfd-Fix-NULL-pointer-dereference-for-set_scra.patch
new file mode 100644
index 00000000..79472cf4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3905-drm-amdkfd-Fix-NULL-pointer-dereference-for-set_scra.patch
@@ -0,0 +1,125 @@
+From 4952e695e7c4a3d0f65d17371a01a8744fb0aac9 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 18 Sep 2019 18:17:57 -0400
+Subject: [PATCH 3905/4256] drm/amdkfd: Fix NULL pointer dereference for
+ set_scratch_backing_va()
+
+Currently this function pointer is missing for GFX10. Considering it is
+a void function since GFX9, fix it by checking the function pointer
+before dereferencing it.
+
+Change-Id: I1dc8e5163f259251357bfaa42a91ff991fba6dd5
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c   |  1 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c     | 10 ----------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h     |  2 --
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c              |  2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c |  5 +++--
+ drivers/gpu/drm/amd/include/kgd_kfd_interface.h       |  5 +++++
+ 6 files changed, 9 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+index ada4662a0842..ce0ceb71ef35 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+@@ -313,7 +313,6 @@ static const struct kfd2kgd_calls kfd2kgd = {
+ 			kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid,
+ 	.get_atc_vmid_pasid_mapping_valid =
+ 			kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid,
+-	.set_scratch_backing_va = kgd_gfx_v9_set_scratch_backing_va,
+ 	.get_tile_config = kgd_gfx_v9_get_tile_config,
+ 	.set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
+ 	.invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+index e8d6d2dc19e7..58f82da00e6d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+@@ -992,15 +992,6 @@ void kgd_gfx_v9_get_iq_wait_times(struct kgd_dev *kgd,
+ 	*wait_times = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2));
+ }
+ 
+-void kgd_gfx_v9_set_scratch_backing_va(struct kgd_dev *kgd,
+-					uint64_t va, uint32_t vmid)
+-{
+-	/* No longer needed on GFXv9. The scratch base address is
+-	 * passed to the shader by the CP. It's the user mode driver's
+-	 * responsibility.
+-	 */
+-}
+-
+ void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
+ 		uint64_t page_table_base)
+ {
+@@ -1062,7 +1053,6 @@ static const struct kfd2kgd_calls kfd2kgd = {
+ 			kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid,
+ 	.get_atc_vmid_pasid_mapping_valid =
+ 			kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid,
+-	.set_scratch_backing_va = kgd_gfx_v9_set_scratch_backing_va,
+ 	.get_tile_config = kgd_gfx_v9_get_tile_config,
+ 	.set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
+ 	.invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
+index a1c5789b5c36..a30e36341502 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
+@@ -61,8 +61,6 @@ uint16_t kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
+ 		uint8_t vmid);
+ void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
+ 		uint64_t page_table_base);
+-void kgd_gfx_v9_set_scratch_backing_va(struct kgd_dev *kgd,
+-					uint64_t va, uint32_t vmid);
+ int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
+ int kgd_gfx_v9_invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
+ int kgd_gfx_v9_get_tile_config(struct kgd_dev *kgd,
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index fa1385d60235..3362b4516089 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -1133,7 +1133,7 @@ static int kfd_ioctl_set_scratch_backing_va(struct file *filep,
+ 	mutex_unlock(&p->mutex);
+ 
+ 	if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS &&
+-	    pdd->qpd.vmid != 0)
++	    pdd->qpd.vmid != 0 && dev->kfd2kgd->set_scratch_backing_va)
+ 		dev->kfd2kgd->set_scratch_backing_va(
+ 			dev->kgd, args->va_addr, pdd->qpd.vmid);
+ 
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 62c612cff26b..eb7e1aaf54a4 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -249,8 +249,9 @@ static int allocate_vmid(struct device_queue_manager *dqm,
+ 	/* invalidate the VM context after pasid and vmid mapping is set up */
+ 	kfd_flush_tlb(qpd_to_pdd(qpd));
+ 
+-	dqm->dev->kfd2kgd->set_scratch_backing_va(
+-		dqm->dev->kgd, qpd->sh_hidden_private_base, qpd->vmid);
++	if (dqm->dev->kfd2kgd->set_scratch_backing_va)
++		dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->kgd,
++				qpd->sh_hidden_private_base, qpd->vmid);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+index db3f4b76d40f..57cf9aabedb4 100644
+--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
++++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+@@ -306,8 +306,13 @@ struct kfd2kgd_calls {
+ 					struct kgd_dev *kgd,
+ 					uint8_t vmid);
+ 
++	/* No longer needed from GFXv9 onward. The scratch base address is
++	 * passed to the shader by the CP. It's the user mode driver's
++	 * responsibility.
++	 */
+ 	void (*set_scratch_backing_va)(struct kgd_dev *kgd,
+ 				uint64_t va, uint32_t vmid);
++
+ 	int (*get_tile_config)(struct kgd_dev *kgd, struct tile_config *config);
+ 
+ 	void (*set_vm_context_page_table_base)(struct kgd_dev *kgd,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3906-drm-amdkfd-Sync-gfx10-kfd2kgd_calls-function-pointer.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3906-drm-amdkfd-Sync-gfx10-kfd2kgd_calls-function-pointer.patch
new file mode 100644
index 00000000..226e2585
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3906-drm-amdkfd-Sync-gfx10-kfd2kgd_calls-function-pointer.patch
@@ -0,0 +1,36 @@
+From 1c8d59842dbb28cb95989c6501d926b78f15904d Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Mon, 23 Sep 2019 15:53:13 -0400
+Subject: [PATCH 3906/4256] drm/amdkfd: Sync gfx10 kfd2kgd_calls function
+ pointers
+
+get_hive_id was not set. Also, adjust the function setting sequence.
+
+Change-Id: I51962954cd0707ebe9aa6c85c71110dee98d6200
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+index 3b164c071f37..ae0862b05dd3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+@@ -160,10 +160,11 @@ static const struct kfd2kgd_calls kfd2kgd = {
+ 			get_atc_vmid_pasid_mapping_pasid,
+ 	.get_atc_vmid_pasid_mapping_valid =
+ 			get_atc_vmid_pasid_mapping_valid,
++	.get_tile_config = amdgpu_amdkfd_get_tile_config,
++	.set_vm_context_page_table_base = set_vm_context_page_table_base,
+ 	.invalidate_tlbs = invalidate_tlbs,
+ 	.invalidate_tlbs_vmid = invalidate_tlbs_vmid,
+-	.set_vm_context_page_table_base = set_vm_context_page_table_base,
+-	.get_tile_config = amdgpu_amdkfd_get_tile_config,
++	.get_hive_id = amdgpu_amdkfd_get_hive_id,
+ };
+ 
+ struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions()
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3907-drm-amdgpu-display-fix-64-bit-divide.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3907-drm-amdgpu-display-fix-64-bit-divide.patch
new file mode 100644
index 00000000..75c1c08c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3907-drm-amdgpu-display-fix-64-bit-divide.patch
@@ -0,0 +1,31 @@
+From e6231755f2a46ffa80c9990005de1a5b7fd82279 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 20 Sep 2019 15:13:24 -0500
+Subject: [PATCH 3907/4256] drm/amdgpu/display: fix 64 bit divide
+
+Use proper helper for 32 bit.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c    | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+index 36277bca0326..b1e657e137a9 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+@@ -197,7 +197,9 @@ void dce11_pplib_apply_display_requirements(
+ 	 */
+ 	if (ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) {
+ 		pp_display_cfg->min_memory_clock_khz = max(pp_display_cfg->min_memory_clock_khz,
+-			(uint32_t) (dc->bw_vbios->high_yclk.value / memory_type_multiplier / 10000));
++							   (uint32_t) div64_s64(
++								   div64_s64(dc->bw_vbios->high_yclk.value,
++									     memory_type_multiplier), 10000));
+ 	} else {
+ 		pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz
+ 			/ memory_type_multiplier;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3908-drm-amd-powerplay-Add-mode2-mode-for-GPU-RESET-in-SM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3908-drm-amd-powerplay-Add-mode2-mode-for-GPU-RESET-in-SM.patch
new file mode 100644
index 00000000..66cc5eff
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3908-drm-amd-powerplay-Add-mode2-mode-for-GPU-RESET-in-SM.patch
@@ -0,0 +1,75 @@
+From ff05a3bd676f34783d452dab5af4f1715b93bc38 Mon Sep 17 00:00:00 2001
+From: chen gong <curry.gong@amd.com>
+Date: Mon, 23 Sep 2019 14:56:43 +0800
+Subject: [PATCH 3908/4256] drm/amd/powerplay: Add mode2 mode for GPU RESET in
+ SMU
+
+Renoir need to use mode2 mode to implement GPU RESET
+
+Signed-off-by: chen gong <curry.gong@amd.com>
+Reviewed-by: Aaron Liu <aaron.liu@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 10 ++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c      |  4 ++++
+ 2 files changed, 14 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 45da21dc2356..149de9277f8e 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -321,6 +321,13 @@ struct mclock_latency_table {
+ 	struct mclk_latency_entries  entries[MAX_REGULAR_DPM_NUM];
+ };
+ 
++enum smu_reset_mode
++{
++    SMU_RESET_MODE_0,
++    SMU_RESET_MODE_1,
++    SMU_RESET_MODE_2,
++};
++
+ enum smu_baco_state
+ {
+ 	SMU_BACO_STATE_ENTER = 0,
+@@ -537,6 +544,7 @@ struct smu_funcs
+ 	enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
+ 	int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
+ 	int (*baco_reset)(struct smu_context *smu);
++	int (*mode2_reset)(struct smu_context *smu);
+ 	int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
+ };
+ 
+@@ -760,6 +768,8 @@ struct smu_funcs
+ 	((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0)
+ #define smu_baco_reset(smu) \
+ 	((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
++#define smu_mode2_reset(smu) \
++	((smu)->funcs->mode2_reset? (smu)->funcs->mode2_reset((smu)) : 0)
+ #define smu_asic_set_performance_level(smu, level) \
+ 	((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
+ #define smu_dump_pptable(smu) \
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 24274c9bb87d..d9d947375557 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -380,6 +380,9 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ 	return ret;
+ }
+ 
++static int smu_v12_0_mode2_reset(struct smu_context *smu){
++	return smu_v12_0_send_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2);
++}
+ static const struct smu_funcs smu_v12_0_funcs = {
+ 	.check_fw_status = smu_v12_0_check_fw_status,
+ 	.check_fw_version = smu_v12_0_check_fw_version,
+@@ -394,6 +397,7 @@ static const struct smu_funcs smu_v12_0_funcs = {
+ 	.fini_smc_tables = smu_v12_0_fini_smc_tables,
+ 	.populate_smc_tables = smu_v12_0_populate_smc_tables,
+ 	.get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
++	.mode2_reset = smu_v12_0_mode2_reset,
+ };
+ 
+ void smu_v12_0_set_smu_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3909-drm-amd-powerplay-A-workaround-to-GPU-RESET-on-APU.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3909-drm-amd-powerplay-A-workaround-to-GPU-RESET-on-APU.patch
new file mode 100644
index 00000000..9f3882a2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3909-drm-amd-powerplay-A-workaround-to-GPU-RESET-on-APU.patch
@@ -0,0 +1,38 @@
+From 40a7aa9c083a0259bd1fc9e2217932b89ab94187 Mon Sep 17 00:00:00 2001
+From: chen gong <curry.gong@amd.com>
+Date: Mon, 23 Sep 2019 15:02:56 +0800
+Subject: [PATCH 3909/4256] drm/amd/powerplay: A workaround to GPU RESET on APU
+
+Changes to function "smu_suspend" in amdgpu_smu.c is a workaround.
+
+We should get real information about if baco is enabled or not, while we
+always consider APU SMU feature as enabled in current code.
+
+I know APU do not support baco mode for GPU reset, so I use
+"adev->flags" to skip function "smu_feature_is_enabled".
+
+Signed-off-by: chen gong <curry.gong@amd.com>
+Reviewed-by: Aaron Liu <aaron.liu@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index b3025bd0ea88..0237e4d06aca 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1363,7 +1363,10 @@ static int smu_suspend(void *handle)
+ 	int ret;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 	struct smu_context *smu = &adev->smu;
+-	bool baco_feature_is_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT);
++	bool baco_feature_is_enabled = false;
++
++	if(!(adev->flags & AMD_IS_APU))
++		baco_feature_is_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT);
+ 
+ 	ret = smu_system_features_control(smu, false);
+ 	if (ret)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3910-drm-amdgpu-Use-mode2-mode-to-perform-GPU-RESET-for-R.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3910-drm-amdgpu-Use-mode2-mode-to-perform-GPU-RESET-for-R.patch
new file mode 100644
index 00000000..d0893298
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3910-drm-amdgpu-Use-mode2-mode-to-perform-GPU-RESET-for-R.patch
@@ -0,0 +1,39 @@
+From 1a3867ad2fb39bedf16642463b9af011dded3073 Mon Sep 17 00:00:00 2001
+From: chen gong <curry.gong@amd.com>
+Date: Thu, 19 Sep 2019 15:02:40 +0800
+Subject: [PATCH 3910/4256] drm/amdgpu: Use mode2 mode to perform GPU RESET for
+ Renoir
+
+Renoir need to use mode2 mode to implement GPU RESET
+
+Signed-off-by: chen gong <curry.gong@amd.com>
+Reviewed-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index dbd790eb5040..a66ef0460762 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -513,6 +513,8 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+ 
+ static int soc15_mode2_reset(struct amdgpu_device *adev)
+ {
++	if (is_support_sw_smu(adev))
++		return smu_mode2_reset(&adev->smu);
+ 	if (!adev->powerplay.pp_funcs ||
+ 	    !adev->powerplay.pp_funcs->asic_reset_mode_2)
+ 		return -ENOENT;
+@@ -527,6 +529,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_RAVEN:
++	case CHIP_RENOIR:
+ 		return AMD_RESET_METHOD_MODE2;
+ 	case CHIP_VEGA10:
+ 	case CHIP_VEGA12:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3911-drm-amdgpu-fix-an-UMC-hw-arbitrator-bug.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3911-drm-amdgpu-fix-an-UMC-hw-arbitrator-bug.patch
new file mode 100644
index 00000000..6f467e0c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3911-drm-amdgpu-fix-an-UMC-hw-arbitrator-bug.patch
@@ -0,0 +1,54 @@
+From aa78ca7c874cd5e6d3aa57bebb4427b87fc18801 Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Wed, 21 Aug 2019 18:04:42 +0800
+Subject: [PATCH 3911/4256] drm/amdgpu: fix an UMC hw arbitrator bug
+
+issue:
+the UMC h/w bug is that when MCLK is doing the switch
+in the middle of a page access being preempted by high
+priority client (e.g. DISPLAY) then UMC and the mclk switch
+would stuck there due to deadlock
+
+how:
+fixed by disabling auto PreChg for UMC to avoid high
+priority client preempting other client's access on
+the same page, thus the deadlock could be avoided
+
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+Change-Id: Iaf6eb2a20a4785ec8440e64d5e0cae67aa0603da
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 561cc6bef280..9b823cd9d86e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -1316,6 +1316,24 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
+ 		 (unsigned)(adev->gmc.gart_size >> 20),
+ 		 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
+ 	adev->gart.ready = true;
++
++	/* disable auto Pchg is a w/a for the vega10 UMC hardware bug */
++	WREG32(0x5010c/4, 0x1002);
++	WREG32(0x5210c/4, 0x1002);
++	WREG32(0x5410c/4, 0x1002);
++	WREG32(0x5610c/4, 0x1002);
++	WREG32(0x15010c/4, 0x1002);
++	WREG32(0x15210c/4, 0x1002);
++	WREG32(0x15410c/4, 0x1002);
++	WREG32(0x15610c/4, 0x1002);
++	WREG32(0x25010c/4, 0x1002);
++	WREG32(0x25210c/4, 0x1002);
++	WREG32(0x25410c/4, 0x1002);
++	WREG32(0x25610c/4, 0x1002);
++	WREG32(0x35010c/4, 0x1002);
++	WREG32(0x35210c/4, 0x1002);
++	WREG32(0x35410c/4, 0x1002);
++	WREG32(0x35610c/4, 0x1002);
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3912-Revert-drm-amdgpu-fix-an-UMC-hw-arbitrator-bug.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3912-Revert-drm-amdgpu-fix-an-UMC-hw-arbitrator-bug.patch
new file mode 100644
index 00000000..232988e0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3912-Revert-drm-amdgpu-fix-an-UMC-hw-arbitrator-bug.patch
@@ -0,0 +1,46 @@
+From 6e950690501de1d272c3897c42699238627fe75a Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Tue, 24 Sep 2019 11:39:59 +0800
+Subject: [PATCH 3912/4256] Revert "drm/amdgpu: fix an UMC hw arbitrator bug"
+
+pushed by mistake
+
+This reverts commit e708931930cbf5594c0c5b86246724cd310cd6a1.
+
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 18 ------------------
+ 1 file changed, 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 9b823cd9d86e..561cc6bef280 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -1316,24 +1316,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
+ 		 (unsigned)(adev->gmc.gart_size >> 20),
+ 		 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
+ 	adev->gart.ready = true;
+-
+-	/* disable auto Pchg is a w/a for the vega10 UMC hardware bug */
+-	WREG32(0x5010c/4, 0x1002);
+-	WREG32(0x5210c/4, 0x1002);
+-	WREG32(0x5410c/4, 0x1002);
+-	WREG32(0x5610c/4, 0x1002);
+-	WREG32(0x15010c/4, 0x1002);
+-	WREG32(0x15210c/4, 0x1002);
+-	WREG32(0x15410c/4, 0x1002);
+-	WREG32(0x15610c/4, 0x1002);
+-	WREG32(0x25010c/4, 0x1002);
+-	WREG32(0x25210c/4, 0x1002);
+-	WREG32(0x25410c/4, 0x1002);
+-	WREG32(0x25610c/4, 0x1002);
+-	WREG32(0x35010c/4, 0x1002);
+-	WREG32(0x35210c/4, 0x1002);
+-	WREG32(0x35410c/4, 0x1002);
+-	WREG32(0x35610c/4, 0x1002);
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3913-drm-amd-powerplay-Vega10-Vega10-BKM0.83-AVFS-paramet.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3913-drm-amd-powerplay-Vega10-Vega10-BKM0.83-AVFS-paramet.patch
new file mode 100644
index 00000000..8892aa5a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3913-drm-amd-powerplay-Vega10-Vega10-BKM0.83-AVFS-paramet.patch
@@ -0,0 +1,44 @@
+From c496544a088014f676659cbd67f33d742123f50e Mon Sep 17 00:00:00 2001
+From: zhexzhan <zhexi.zhang@amd.com>
+Date: Wed, 5 Jun 2019 13:19:16 +0800
+Subject: [PATCH 3913/4256] drm/amd/powerplay [Vega10]Vega10 BKM0.83 AVFS
+ parameters patch for Linux Driver
+
+Issue: DROOP coef read by HDT appear to be mismatch with requirement of BKM0.83
+
+Root cause: These values are supposed to be overwritten by PPLIB.
+However, driver missed code of this part.
+
+Solution: Add overwriting process when reading pptable from vBIOS
+Hardcode specific coef with correct values:
+GbVdroopTableCksoffA0 = 0xFFFCD2E7
+GbVdroopTableCksoffA1 = 0x24902
+GbVdroopTableCksoffA2 = 0x249BA
+
+Change-Id: I6cddd7fc22d59c555f784c12596ad3a48b2cffcd
+Signed-off-by: zhexzhan <zhexi.zhang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
+index 615cf2c09e54..b827c2c1f0e2 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
+@@ -293,6 +293,13 @@ int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
+ 	format_revision = ((struct atom_common_table_header *)profile)->format_revision;
+ 	content_revision = ((struct atom_common_table_header *)profile)->content_revision;
+ 
++	if (format_revision == 4)
++	{
++		profile->gb_vdroop_table_cksoff_a0 = 0xfffcd2e7;
++		profile->gb_vdroop_table_cksoff_a1 = 0x24902;
++		profile->gb_vdroop_table_cksoff_a2 = 0x249ba;
++	}
++
+ 	if (format_revision == 4 && content_revision == 1) {
+ 		param->ulMaxVddc = le32_to_cpu(profile->maxvddc);
+ 		param->ulMinVddc = le32_to_cpu(profile->minvddc);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3914-drm-amd-amdgpu-Fix-compute-ring-unable-to-detect-han.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3914-drm-amd-amdgpu-Fix-compute-ring-unable-to-detect-han.patch
new file mode 100644
index 00000000..e421e4eb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3914-drm-amd-amdgpu-Fix-compute-ring-unable-to-detect-han.patch
@@ -0,0 +1,103 @@
+From e7b93cd9b3cbdcb0999eb91a89e81846948899fd Mon Sep 17 00:00:00 2001
+From: Jesse Zhang <zhexi.zhang@amd.com>
+Date: Tue, 30 Jul 2019 19:15:42 +0800
+Subject: [PATCH 3914/4256] drm/amd/amdgpu:Fix compute ring unable to detect
+ hang.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+When compute fence did not signal, compute ring cannot detect hardware hang
+because its timeout value is set to be infinite by default.
+
+In SR-IOV and passthrough mode, if user does not declare custome timeout
+value for compute ring, then use gfx ring timeout value as default. So
+that when there is a ture hardware hang, compute ring can detect it.
+
+Change-Id: I794ec0868c6c0aad407749457260ecfee0617c10
+Signed-off-by: Jesse Zhang <zhexi.zhang@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 ++++++------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c    |  7 ++++++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c  | 13 +------------
+ 3 files changed, 13 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 6df43bc6dc5e..8f7e8911d4f3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1024,12 +1024,6 @@ static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
+ 
+ 	amdgpu_device_check_block_size(adev);
+ 
+-        ret = amdgpu_device_get_job_timeout_settings(adev);
+-        if (ret) {
+-                dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
+-                return ret;
+-	}
+-
+ 	adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
+ 	amdgpu_direct_gma_size = min(amdgpu_direct_gma_size, 96);
+ 
+@@ -2737,6 +2731,12 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ 	r = amdgpu_device_ip_early_init(adev);
+ 	if (r)
+ 		return r;
++	
++	r = amdgpu_device_get_job_timeout_settings(adev);
++	if (r) {
++		dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
++		return r;
++	}
+ 
+ 	/* doorbell bar mapping and doorbell index init*/
+ 	amdgpu_device_doorbell_init(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 0d8d292eb236..50f962a78a61 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1376,10 +1376,15 @@ int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
+ 	/*
+ 	 * By default timeout for non compute jobs is 10000.
+ 	 * And there is no timeout enforced on compute jobs.
++	 * In SR-IOV or passthrough mode, timeout for compute
++	 * jobs are 10000 by default.
+ 	 */
+ 	adev->gfx_timeout = msecs_to_jiffies(10000);
+ 	adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
+-	adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
++	if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
++		adev->compute_timeout = adev->gfx_timeout;
++	else
++		adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
+ 
+ 	if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
+ 		while ((timeout_setting = strsep(&input, ",")) &&
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+index a947fe4e2368..295b3f38a89d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+@@ -460,18 +460,7 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
+ 			timeout = adev->gfx_timeout;
+ 			break;
+ 		case AMDGPU_RING_TYPE_COMPUTE:
+-			/*
+-			 * For non-sriov case, no timeout enforce
+-			 * on compute ring by default. Unless user
+-			 * specifies a timeout for compute ring.
+-			 *
+-			 * For sriov case, always use the timeout
+-			 * as gfx ring
+-			 */
+-			if (!amdgpu_sriov_vf(ring->adev))
+-				timeout = adev->compute_timeout;
+-			else
+-				timeout = adev->gfx_timeout;
++			timeout = adev->compute_timeout;
+ 			break;
+ 		case AMDGPU_RING_TYPE_SDMA:
+ 			timeout = adev->sdma_timeout;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3915-Revert-drm-amd-powerplay-Vega10-Vega10-BKM0.83-AVFS-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3915-Revert-drm-amd-powerplay-Vega10-Vega10-BKM0.83-AVFS-.patch
new file mode 100644
index 00000000..922fb1c9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3915-Revert-drm-amd-powerplay-Vega10-Vega10-BKM0.83-AVFS-.patch
@@ -0,0 +1,35 @@
+From 2da8abe5f1a1aef2fad014ee3b5c7c79ae14badc Mon Sep 17 00:00:00 2001
+From: Jesse Zhang <zhexi.zhang@amd.com>
+Date: Tue, 24 Sep 2019 11:54:37 +0800
+Subject: [PATCH 3915/4256] Revert "drm/amd/powerplay [Vega10]Vega10 BKM0.83
+ AVFS parameters patch for Linux Driver"
+
+This reverts commit 72328b005eee2357024b69620add9c14421c03d4.
+
+Change-Id: I5c9d58196f3f55ac795fe45cb38b292572ca1b8d
+Signed-off-by: Jesse Zhang <zhexi.zhang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 7 -------
+ 1 file changed, 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
+index b827c2c1f0e2..615cf2c09e54 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
+@@ -293,13 +293,6 @@ int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
+ 	format_revision = ((struct atom_common_table_header *)profile)->format_revision;
+ 	content_revision = ((struct atom_common_table_header *)profile)->content_revision;
+ 
+-	if (format_revision == 4)
+-	{
+-		profile->gb_vdroop_table_cksoff_a0 = 0xfffcd2e7;
+-		profile->gb_vdroop_table_cksoff_a1 = 0x24902;
+-		profile->gb_vdroop_table_cksoff_a2 = 0x249ba;
+-	}
+-
+ 	if (format_revision == 4 && content_revision == 1) {
+ 		param->ulMaxVddc = le32_to_cpu(profile->maxvddc);
+ 		param->ulMinVddc = le32_to_cpu(profile->minvddc);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3916-drm-amd-powerplay-remove-duplicate-macro-of-smu_get_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3916-drm-amd-powerplay-remove-duplicate-macro-of-smu_get_.patch
new file mode 100644
index 00000000..a2dd4db7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3916-drm-amd-powerplay-remove-duplicate-macro-of-smu_get_.patch
@@ -0,0 +1,34 @@
+From ed4e49791c6d3b6ed0cc7faafcf65e4d3ad4a0a8 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Mon, 23 Sep 2019 15:36:11 +0800
+Subject: [PATCH 3916/4256] drm/amd/powerplay: remove duplicate macro of
+ smu_get_uclk_dpm_states
+
+remove duplicate macro of smu_get_uclk_dpm_states
+
+fix commit:
+drm/amd/powerplay: add the interface for getting ultimate frequency v3
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Prike Liang <Prike.Liang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 149de9277f8e..5c898444ff97 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -760,8 +760,6 @@ struct smu_funcs
+ 	((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
+ #define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
+ 	((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
+-#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
+-	((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
+ #define smu_baco_is_support(smu) \
+ 	((smu)->funcs->baco_is_support? (smu)->funcs->baco_is_support((smu)) : false)
+ #define smu_baco_get_state(smu, state) \
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3917-drm-amdgpu-psp-silence-response-status-warning.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3917-drm-amdgpu-psp-silence-response-status-warning.patch
new file mode 100644
index 00000000..80360122
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3917-drm-amdgpu-psp-silence-response-status-warning.patch
@@ -0,0 +1,34 @@
+From 09f13513460bdc9a876db5fae9845f782784167e Mon Sep 17 00:00:00 2001
+From: Shirish S <shirish.s@amd.com>
+Date: Tue, 24 Sep 2019 14:45:54 +0530
+Subject: [PATCH 3917/4256] drm/amdgpu/psp: silence response status warning
+
+log the response status related error to the driver's
+debug log since  psp response status is not 0 even though
+there was no problem while the command was submitted.
+
+This warning misleads, hence this change.
+
+Signed-off-by: Shirish S <shirish.s@amd.com>
+Acked-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index d3444f24647e..e4f4ae99280a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -172,7 +172,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
+                 if (ucode)
+                         DRM_WARN("failed to load ucode id (%d) ",
+                                   ucode->ucode_id);
+-		DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n",
++		DRM_DEBUG_DRIVER("psp command (0x%X) failed and response status is (0x%X)\n",
+ 				psp->cmd_buf_mem->cmd_id,
+ 				psp->cmd_buf_mem->resp.status & GFX_CMD_STATUS_MASK);
+ 		if (!timeout) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3918-drm-amdgpu-display-include-slab.h-in-dcn21_resource..patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3918-drm-amdgpu-display-include-slab.h-in-dcn21_resource..patch
new file mode 100644
index 00000000..4177efc8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3918-drm-amdgpu-display-include-slab.h-in-dcn21_resource..patch
@@ -0,0 +1,30 @@
+From 2e91e081298a56a6456963c0c0d23cad8905631b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 23 Sep 2019 15:56:25 -0500
+Subject: [PATCH 3918/4256] drm/amdgpu/display: include slab.h in
+ dcn21_resource.c
+
+It's apparently needed in some configurations.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 3ca5139f1273..de182185fe1f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -23,6 +23,8 @@
+  *
+  */
+ 
++#include <linux/slab.h>
++
+ #include "dm_services.h"
+ #include "dc.h"
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3919-drm-amdgpu-atomfirmware-use-proper-index-for-queryin.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3919-drm-amdgpu-atomfirmware-use-proper-index-for-queryin.patch
new file mode 100644
index 00000000..f3cdca67
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3919-drm-amdgpu-atomfirmware-use-proper-index-for-queryin.patch
@@ -0,0 +1,240 @@
+From 8a506d87d40632dd9d40d4815f0388b28ac6614b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 20 Sep 2019 14:43:44 -0500
+Subject: [PATCH 3919/4256] drm/amdgpu/atomfirmware: use proper index for
+ querying vram type (v3)
+
+The index is stored in scratch register 4 after asic init.  Use
+that index.  No functional change since all asics in a family
+use the same type of vram (G5, G6, HBM) and that is all we use
+at the monent, but if we ever need to query other info, we will
+now have the proper index.
+
+v2: module array is variable sized, handle that.
+v3: fix off by one in array handling
+
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c  | 158 ++++++++++--------
+ 1 file changed, 88 insertions(+), 70 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+index 606ed819f355..e0e67a53fb3c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+@@ -120,65 +120,14 @@ union vram_info {
+ 	struct atom_vram_info_header_v2_3 v23;
+ 	struct atom_vram_info_header_v2_4 v24;
+ };
+-/*
+- * Return vram width from integrated system info table, if available,
+- * or 0 if not.
+- */
+-int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev)
+-{
+-	struct amdgpu_mode_info *mode_info = &adev->mode_info;
+-	int index;
+-	u16 data_offset, size;
+-	union igp_info *igp_info;
+-	union vram_info *vram_info;
+-	u32 mem_channel_number;
+-	u32 mem_channel_width;
+-	u8 frev, crev;
+-
+-	if (adev->flags & AMD_IS_APU)
+-		index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+-						    integratedsysteminfo);
+-	else
+-		index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+-						    vram_info);
+-
+-	/* get any igp specific overrides */
+-	if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
+-				   &frev, &crev, &data_offset)) {
+-		if (adev->flags & AMD_IS_APU) {
+-			igp_info = (union igp_info *)
+-				(mode_info->atom_context->bios + data_offset);
+-			switch (crev) {
+-			case 11:
+-				mem_channel_number = igp_info->v11.umachannelnumber;
+-				/* channel width is 64 */
+-				return mem_channel_number * 64;
+-			default:
+-				return 0;
+-			}
+-		} else {
+-			vram_info = (union vram_info *)
+-				(mode_info->atom_context->bios + data_offset);
+-			switch (crev) {
+-			case 3:
+-				mem_channel_number = vram_info->v23.vram_module[0].channel_num;
+-				mem_channel_width = vram_info->v23.vram_module[0].channel_width;
+-				return mem_channel_number * (1 << mem_channel_width);
+-			case 4:
+-				mem_channel_number = vram_info->v24.vram_module[0].channel_num;
+-				mem_channel_width = vram_info->v24.vram_module[0].channel_width;
+-				return mem_channel_number * (1 << mem_channel_width);
+-			default:
+-				return 0;
+-			}
+-		}
+-	}
+ 
+-	return 0;
+-}
++union vram_module {
++	struct atom_vram_module_v9 v9;
++	struct atom_vram_module_v10 v10;
++};
+ 
+-static int convert_atom_mem_type_to_vram_type (struct amdgpu_device *adev,
+-					       int atom_mem_type)
++static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
++					      int atom_mem_type)
+ {
+ 	int vram_type;
+ 
+@@ -219,19 +168,23 @@ static int convert_atom_mem_type_to_vram_type (struct amdgpu_device *adev,
+ 
+ 	return vram_type;
+ }
+-/*
+- * Return vram type from either integrated system info table
+- * or umc info table, if available, or 0 (TYPE_UNKNOWN) if not
+- */
+-int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
++
++static int
++amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
++				  int *vram_width, int *vram_type)
+ {
+ 	struct amdgpu_mode_info *mode_info = &adev->mode_info;
+-	int index;
++	int index, i = 0;
+ 	u16 data_offset, size;
+ 	union igp_info *igp_info;
+ 	union vram_info *vram_info;
++	union vram_module *vram_module;
+ 	u8 frev, crev;
+ 	u8 mem_type;
++	u32 mem_channel_number;
++	u32 mem_channel_width;
++	u32 module_id;
++
+ 
+ 	if (adev->flags & AMD_IS_APU)
+ 		index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+@@ -239,6 +192,7 @@ int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
+ 	else
+ 		index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+ 						    vram_info);
++
+ 	if (amdgpu_atom_parse_data_header(mode_info->atom_context,
+ 					  index, &size,
+ 					  &frev, &crev, &data_offset)) {
+@@ -247,30 +201,94 @@ int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
+ 				(mode_info->atom_context->bios + data_offset);
+ 			switch (crev) {
+ 			case 11:
++				mem_channel_number = igp_info->v11.umachannelnumber;
++				/* channel width is 64 */
++				if (vram_width)
++					*vram_width = mem_channel_number * 64;
+ 				mem_type = igp_info->v11.memorytype;
+-				return convert_atom_mem_type_to_vram_type(adev, mem_type);
++				if (vram_type)
++					*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
++				break;
+ 			default:
+-				return 0;
++				return -EINVAL;
+ 			}
+ 		} else {
+ 			vram_info = (union vram_info *)
+ 				(mode_info->atom_context->bios + data_offset);
++			module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
+ 			switch (crev) {
+ 			case 3:
+-				mem_type = vram_info->v23.vram_module[0].memory_type;
+-				return convert_atom_mem_type_to_vram_type(adev, mem_type);
++				if (module_id > vram_info->v23.vram_module_num)
++					module_id = 0;
++				vram_module = (union vram_module *)vram_info->v23.vram_module;
++				while (i < module_id) {
++					vram_module = (union vram_module *)
++						((u8 *)vram_module + vram_module->v9.vram_module_size);
++					i++;
++				}
++				mem_type = vram_module->v9.memory_type;
++				if (vram_type)
++					*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
++				mem_channel_number = vram_module->v9.channel_num;
++				mem_channel_width = vram_module->v9.channel_width;
++				if (vram_width)
++					*vram_width = mem_channel_number * (1 << mem_channel_width);
++				break;
+ 			case 4:
+-				mem_type = vram_info->v24.vram_module[0].memory_type;
+-				return convert_atom_mem_type_to_vram_type(adev, mem_type);
++				if (module_id > vram_info->v24.vram_module_num)
++					module_id = 0;
++				vram_module = (union vram_module *)vram_info->v24.vram_module;
++				while (i < module_id) {
++					vram_module = (union vram_module *)
++						((u8 *)vram_module + vram_module->v10.vram_module_size);
++					i++;
++				}
++				mem_type = vram_module->v10.memory_type;
++				if (vram_type)
++					*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
++				mem_channel_number = vram_module->v10.channel_num;
++				mem_channel_width = vram_module->v10.channel_width;
++				if (vram_width)
++					*vram_width = mem_channel_number * (1 << mem_channel_width);
++				break;
+ 			default:
+-				return 0;
++				return -EINVAL;
+ 			}
+ 		}
++
+ 	}
+ 
+ 	return 0;
+ }
+ 
++/*
++ * Return vram width from integrated system info table, if available,
++ * or 0 if not.
++ */
++int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev)
++{
++	int vram_width = 0, vram_type = 0;
++	int r = amdgpu_atomfirmware_get_vram_info(adev, &vram_width, &vram_type);
++	if (r)
++		return 0;
++
++	return vram_width;
++}
++
++/*
++ * Return vram type from either integrated system info table
++ * or umc info table, if available, or 0 (TYPE_UNKNOWN) if not
++ */
++int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
++{
++	int vram_width = 0, vram_type = 0;
++	int r = amdgpu_atomfirmware_get_vram_info(adev, &vram_width, &vram_type);
++	if (r)
++		return 0;
++
++	return vram_type;
++}
++
+ /*
+  * Return true if vbios enabled ecc by default, if umc info table is available
+  * or false if ecc is not enabled or umc info table is not available
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3920-drm-amdgpu-atomfirmware-simplify-the-interface-to-ge.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3920-drm-amdgpu-atomfirmware-simplify-the-interface-to-ge.patch
new file mode 100644
index 00000000..0df7f70e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3920-drm-amdgpu-atomfirmware-simplify-the-interface-to-ge.patch
@@ -0,0 +1,220 @@
+From 515e4c0ae27fdf3e5066b7261527956f2edf8a5b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 23 Sep 2019 15:12:46 -0500
+Subject: [PATCH 3920/4256] drm/amdgpu/atomfirmware: simplify the interface to
+ get vram info
+
+fetch both the vram type and width in one function call.  This
+avoids having to parse the same data table twice to get the two
+pieces of data.
+
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c  | 34 +------------
+ .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h  |  4 +-
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c        | 21 +++-----
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c         | 49 ++++++++++---------
+ 4 files changed, 37 insertions(+), 71 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+index e0e67a53fb3c..fbff37bd2b03 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+@@ -169,9 +169,8 @@ static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
+ 	return vram_type;
+ }
+ 
+-static int
+-amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+-				  int *vram_width, int *vram_type)
++int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
++				      int *vram_width, int *vram_type)
+ {
+ 	struct amdgpu_mode_info *mode_info = &adev->mode_info;
+ 	int index, i = 0;
+@@ -185,7 +184,6 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+ 	u32 mem_channel_width;
+ 	u32 module_id;
+ 
+-
+ 	if (adev->flags & AMD_IS_APU)
+ 		index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+ 						    integratedsysteminfo);
+@@ -261,34 +259,6 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+ 	return 0;
+ }
+ 
+-/*
+- * Return vram width from integrated system info table, if available,
+- * or 0 if not.
+- */
+-int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev)
+-{
+-	int vram_width = 0, vram_type = 0;
+-	int r = amdgpu_atomfirmware_get_vram_info(adev, &vram_width, &vram_type);
+-	if (r)
+-		return 0;
+-
+-	return vram_width;
+-}
+-
+-/*
+- * Return vram type from either integrated system info table
+- * or umc info table, if available, or 0 (TYPE_UNKNOWN) if not
+- */
+-int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
+-{
+-	int vram_width = 0, vram_type = 0;
+-	int r = amdgpu_atomfirmware_get_vram_info(adev, &vram_width, &vram_type);
+-	if (r)
+-		return 0;
+-
+-	return vram_type;
+-}
+-
+ /*
+  * Return true if vbios enabled ecc by default, if umc info table is available
+  * or false if ecc is not enabled or umc info table is not available
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+index 5ec6f92f353c..82819f03e444 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+@@ -29,8 +29,8 @@
+ bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev);
+ void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);
+ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
+-int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev);
+-int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev);
++int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
++				      int *vram_width, int *vram_type);
+ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev);
+ int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev);
+ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index 2ea9278a8368..055a8cbf889b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -539,17 +539,6 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
+  */
+ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
+ {
+-	int chansize, numchan;
+-
+-	if (!amdgpu_emu_mode)
+-		adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
+-	else {
+-		/* hard code vram_width for emulation */
+-		chansize = 128;
+-		numchan = 1;
+-		adev->gmc.vram_width = numchan * chansize;
+-	}
+-
+ 	/* Could aper size report 0 ? */
+ 	adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
+ 	adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
+@@ -635,8 +624,8 @@ static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
+ 
+ static int gmc_v10_0_sw_init(void *handle)
+ {
+-	int r;
+ 	int dma_bits;
++	int r, vram_width = 0, vram_type = 0;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
+ 	gfxhub_v2_0_init(adev);
+@@ -644,7 +633,13 @@ static int gmc_v10_0_sw_init(void *handle)
+ 
+ 	spin_lock_init(&adev->gmc.invalidate_lock);
+ 
+-	adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
++	r = amdgpu_atomfirmware_get_vram_info(adev, &vram_width, &vram_type);
++	if (!amdgpu_emu_mode)
++		adev->gmc.vram_width = vram_width;
++	else
++		adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
++
++	adev->gmc.vram_type = vram_type;
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 561cc6bef280..abd7a5e22c3f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -891,30 +891,8 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
+  */
+ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
+ {
+-	int chansize, numchan;
+ 	int r;
+ 
+-	if (amdgpu_sriov_vf(adev)) {
+-		/* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
+-		 * and DF related registers is not readable, seems hardcord is the
+-		 * only way to set the correct vram_width
+-		 */
+-		adev->gmc.vram_width = 2048;
+-	} else if (amdgpu_emu_mode != 1) {
+-		adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
+-	}
+-
+-	if (!adev->gmc.vram_width) {
+-		/* hbm memory channel size */
+-		if (adev->flags & AMD_IS_APU)
+-			chansize = 64;
+-		else
+-			chansize = 128;
+-
+-		numchan = adev->df_funcs->get_hbm_channel_number(adev);
+-		adev->gmc.vram_width = numchan * chansize;
+-	}
+-
+ 	/* size in MB on si */
+ 	adev->gmc.mc_vram_size =
+ 		adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
+@@ -1029,8 +1007,8 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
+ 
+ static int gmc_v9_0_sw_init(void *handle)
+ {
+-	int r;
+ 	int dma_bits;
++	int r, vram_width = 0, vram_type = 0;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
+ 	gfxhub_v1_0_init(adev);
+@@ -1041,7 +1019,30 @@ static int gmc_v9_0_sw_init(void *handle)
+ 
+ 	spin_lock_init(&adev->gmc.invalidate_lock);
+ 
+-	adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
++	r = amdgpu_atomfirmware_get_vram_info(adev, &vram_width, &vram_type);
++	if (amdgpu_sriov_vf(adev))
++		/* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
++		 * and DF related registers is not readable, seems hardcord is the
++		 * only way to set the correct vram_width
++		 */
++		adev->gmc.vram_width = 2048;
++	else if (amdgpu_emu_mode != 1)
++		adev->gmc.vram_width = vram_width;
++
++	if (!adev->gmc.vram_width) {
++		int chansize, numchan;
++
++		/* hbm memory channel size */
++		if (adev->flags & AMD_IS_APU)
++			chansize = 64;
++		else
++			chansize = 128;
++
++		numchan = adev->df_funcs->get_hbm_channel_number(adev);
++		adev->gmc.vram_width = numchan * chansize;
++	}
++
++	adev->gmc.vram_type = vram_type;
+ 	switch (adev->asic_type) {
+ 	case CHIP_RAVEN:
+ 		adev->num_vmhubs = 2;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3921-Enable-over-subscription-with-1-GWS-queue.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3921-Enable-over-subscription-with-1-GWS-queue.patch
new file mode 100644
index 00000000..2a841667
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3921-Enable-over-subscription-with-1-GWS-queue.patch
@@ -0,0 +1,314 @@
+From bfdaf131a7afc8226419aa8f5176648833329105 Mon Sep 17 00:00:00 2001
+From: Joseph Greathouse <Joseph.Greathouse@amd.com>
+Date: Wed, 18 Sep 2019 14:49:57 -0500
+Subject: [PATCH 3921/4256] Enable over-subscription with >1 GWS queue
+
+The current GWS usage model will only allows a single GWS-enabled
+process to be active on the GPU at once. This ensures that a
+barrier-using kernel gets a known amount of GPU hardware, to
+prevent deadlock due to inability to go beyond the GWS barrier.
+
+The HWS watches how many GWS entries are assigned to each process,
+and goes into over-subscription mode when two processes need more
+than the 64 that are available. The current KFD method for working
+with this is to allocate all 64 GWS entries to each GWS-capable
+process.
+
+When more than one GWS-enabled process is in the runlist, we must
+make sure the runlist is in over-subscription mode, so that the
+HWS gets a chained RUN_LIST packet and continues scheduling
+kernels.
+
+Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c      |  1 +
+ .../drm/amd/amdkfd/kfd_device_queue_manager.c | 58 ++++++++++++++++++-
+ .../drm/amd/amdkfd/kfd_device_queue_manager.h |  1 +
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c |  1 +
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c  |  2 +-
+ .../gpu/drm/amd/amdkfd/kfd_packet_manager.c   |  6 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h         | 13 +++++
+ drivers/gpu/drm/amd/amdkfd/kfd_process.c      |  1 +
+ 8 files changed, 78 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index 3362b4516089..838a8d46ba47 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -219,6 +219,7 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties,
+ 	}
+ 
+ 	q_properties->is_interop = false;
++	q_properties->is_gws = false;
+ 	q_properties->queue_percent = args->queue_percentage;
+ 	q_properties->priority = args->queue_priority;
+ 	q_properties->queue_address = args->ring_base_address;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index eb7e1aaf54a4..3aec5046d26d 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -504,8 +504,13 @@ static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
+ 		deallocate_vmid(dqm, qpd, q);
+ 	}
+ 	qpd->queue_count--;
+-	if (q->properties.is_active)
++	if (q->properties.is_active) {
+ 		dqm->queue_count--;
++		if (q->properties.is_gws) {
++			dqm->gws_queue_count--;
++			qpd->mapped_gws_queue = false;
++		}
++	}
+ 
+ 	return retval;
+ }
+@@ -577,6 +582,20 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q)
+ 	else if (!q->properties.is_active && prev_active)
+ 		dqm->queue_count--;
+ 
++	if (q->gws && !q->properties.is_gws) {
++		if (q->properties.is_active) {
++			dqm->gws_queue_count++;
++			pdd->qpd.mapped_gws_queue = true;
++		}
++		q->properties.is_gws = true;
++	} else if (!q->gws && q->properties.is_gws) {
++		if (q->properties.is_active) {
++			dqm->gws_queue_count--;
++			pdd->qpd.mapped_gws_queue = false;
++		}
++		q->properties.is_gws = false;
++	}
++
+ 	if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS)
+ 		retval = map_queues_cpsch(dqm);
+ 	else if (q->properties.is_active &&
+@@ -619,6 +638,10 @@ static int suspend_single_queue(struct device_queue_manager *dqm,
+ 	if (q->properties.is_active) {
+ 		dqm->queue_count--;
+ 		q->properties.is_active = false;
++		if (q->properties.is_gws) {
++			dqm->gws_queue_count--;
++			pdd->qpd.mapped_gws_queue = false;
++		}
+ 	}
+ 
+ 	return retval;
+@@ -653,6 +676,10 @@ static int resume_single_queue(struct device_queue_manager *dqm,
+ 	if (QUEUE_IS_ACTIVE(q->properties)) {
+ 		q->properties.is_active = true;
+ 		dqm->queue_count++;
++		if (q->properties.is_gws) {
++			dqm->gws_queue_count++;
++			qpd->mapped_gws_queue = true;
++		}
+ 	}
+ 
+ 	return retval;
+@@ -693,6 +720,10 @@ static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
+ 			 */
+ 			ret = retval;
+ 		dqm->queue_count--;
++		if (q->properties.is_gws) {
++			dqm->gws_queue_count--;
++			qpd->mapped_gws_queue = false;
++		}
+ 	}
+ 
+ out:
+@@ -725,6 +756,10 @@ static int evict_process_queues_cpsch(struct device_queue_manager *dqm,
+ 
+ 		q->properties.is_active = false;
+ 		dqm->queue_count--;
++		if (q->properties.is_gws) {
++			dqm->gws_queue_count--;
++			qpd->mapped_gws_queue = false;
++		}
+ 	}
+ 	retval = execute_queues_cpsch(dqm,
+ 				qpd->is_debug ?
+@@ -802,6 +837,10 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
+ 			 */
+ 			ret = retval;
+ 		dqm->queue_count++;
++		if (q->properties.is_gws) {
++			dqm->gws_queue_count++;
++			qpd->mapped_gws_queue = true;
++		}
+ 	}
+ 	qpd->evicted = 0;
+ out:
+@@ -846,6 +885,10 @@ static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
+ 
+ 		q->properties.is_active = true;
+ 		dqm->queue_count++;
++		if (q->properties.is_gws) {
++			dqm->gws_queue_count++;
++			qpd->mapped_gws_queue = true;
++		}
+ 	}
+ 	retval = execute_queues_cpsch(dqm,
+ 				KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
+@@ -952,6 +995,7 @@ static int initialize_nocpsch(struct device_queue_manager *dqm)
+ 	dqm->queue_count = dqm->next_pipe_to_allocate = 0;
+ 	dqm->sdma_queue_count = 0;
+ 	dqm->xgmi_sdma_queue_count = 0;
++	dqm->gws_queue_count = 0;
+ 	dqm->trap_debug_vmid = 0;
+ 
+ 	for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
+@@ -1108,6 +1152,7 @@ static int initialize_cpsch(struct device_queue_manager *dqm)
+ 	dqm->queue_count = dqm->processes_count = 0;
+ 	dqm->sdma_queue_count = 0;
+ 	dqm->xgmi_sdma_queue_count = 0;
++	dqm->gws_queue_count = 0;
+ 	dqm->active_runlist = false;
+ 	dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
+ 	dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
+@@ -1492,6 +1537,10 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm,
+ 				USE_DEFAULT_GRACE_PERIOD);
+ 		if (retval == -ETIME)
+ 			qpd->reset_wavefronts = true;
++		if (q->properties.is_gws) {
++			dqm->gws_queue_count--;
++			qpd->mapped_gws_queue = false;
++		}
+ 	}
+ 
+ 	/*
+@@ -1704,8 +1753,13 @@ static int process_termination_cpsch(struct device_queue_manager *dqm,
+ 			deallocate_sdma_queue(dqm, q);
+ 		}
+ 
+-		if (q->properties.is_active)
++		if (q->properties.is_active) {
+ 			dqm->queue_count--;
++			if (q->properties.is_gws) {
++				dqm->gws_queue_count--;
++				qpd->mapped_gws_queue = false;
++			}
++		}
+ 
+ 		dqm->total_queue_count--;
+ 	}
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+index 54f4fad61359..eed8f950b663 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+@@ -182,6 +182,7 @@ struct device_queue_manager {
+ 	unsigned int		queue_count;
+ 	unsigned int		sdma_queue_count;
+ 	unsigned int		xgmi_sdma_queue_count;
++	unsigned int		gws_queue_count;
+ 	unsigned int		total_queue_count;
+ 	unsigned int		next_pipe_to_allocate;
+ 	unsigned int		*allocated_queues;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+index 9ec62435326e..ac031dc09d66 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+@@ -115,6 +115,7 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev,
+ 
+ 	prop.queue_size = queue_size;
+ 	prop.is_interop = false;
++	prop.is_gws = false;
+ 	prop.priority = 1;
+ 	prop.queue_percent = 100;
+ 	prop.type = type;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+index c3f39ef4de56..f7d9dac26485 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+@@ -84,7 +84,7 @@ static int pm_map_process_v9(struct packet_manager *pm,
+ 	packet->bitfields2.pasid = qpd->pqm->process->pasid;
+ 	packet->bitfields14.gds_size = qpd->gds_size & 0x3F;
+ 	packet->bitfields14.gds_size_hi = (qpd->gds_size >> 6) & 0xF;
+-	packet->bitfields14.num_gws = qpd->num_gws;
++	packet->bitfields14.num_gws = (qpd->mapped_gws_queue) ? qpd->num_gws : 0;
+ 	packet->bitfields14.num_oac = qpd->num_oac;
+ 	packet->bitfields14.sdma_enable = 1;
+ 	packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+index 08d3b38117b5..43e8e0258188 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+@@ -41,7 +41,7 @@ static void pm_calc_rlib_size(struct packet_manager *pm,
+ 				unsigned int *rlib_size,
+ 				bool *over_subscription)
+ {
+-	unsigned int process_count, queue_count, compute_queue_count;
++	unsigned int process_count, queue_count, compute_queue_count, gws_queue_count;
+ 	unsigned int map_queue_size;
+ 	unsigned int max_proc_per_quantum = 1;
+ 	struct kfd_dev *dev = pm->dqm->dev;
+@@ -50,6 +50,7 @@ static void pm_calc_rlib_size(struct packet_manager *pm,
+ 	queue_count = pm->dqm->queue_count;
+ 	compute_queue_count = queue_count - pm->dqm->sdma_queue_count -
+ 				pm->dqm->xgmi_sdma_queue_count;
++	gws_queue_count = pm->dqm->gws_queue_count;
+ 
+ 	/* check if there is over subscription
+ 	 * Note: the arbitration between the number of VMIDs and
+@@ -62,7 +63,8 @@ static void pm_calc_rlib_size(struct packet_manager *pm,
+ 		max_proc_per_quantum = dev->max_proc_per_quantum;
+ 
+ 	if ((process_count > max_proc_per_quantum) ||
+-	    compute_queue_count > get_queues_num(pm->dqm)) {
++	    compute_queue_count > get_queues_num(pm->dqm) ||
++	    gws_queue_count > 1) {
+ 		*over_subscription = true;
+ 		pr_debug("Over subscribed runlist\n");
+ 	}
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index 6bf5be992303..9ac50a4eb294 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -466,6 +466,10 @@ enum KFD_QUEUE_PRIORITY {
+  * @is_active: Defines if the queue is active or not. @is_active and
+  * @is_evicted are protected by the DQM lock.
+  *
++ * @is_gws: Defines if the queue has been updated to be GWS-capable or not.
++ * @is_gws should be protected by the DQM lock, since changing it can yield the
++ * possibility of updating DQM state on number of GWS queues.
++ *
+  * @vmid: If the scheduling mode is no cp scheduling the field defines the vmid
+  * of the queue.
+  *
+@@ -490,6 +494,7 @@ struct queue_properties {
+ 	bool is_suspended;
+ 	bool is_active;
+ 	bool is_new;
++	bool is_gws;
+ 	/* Not relevant for user mode queues in cp scheduling */
+ 	unsigned int vmid;
+ 	/* Relevant only for sdma queues*/
+@@ -628,6 +633,14 @@ struct qcm_process_device {
+ 	 */
+ 	bool reset_wavefronts;
+ 
++	/* This flag tells us if this process has a GWS-capable
++	 * queue that will be mapped into the runlist. It's
++	 * possible to request a GWS BO, but not have the queue
++	 * currently mapped, and this changes how the MAP_PROCESS
++	 * PM4 packet is configured.
++	 */
++	bool mapped_gws_queue;
++
+ 	/*
+ 	 * All the memory management data should be here too
+ 	 */
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+index c14fdf3bda75..d7e057376d8f 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+@@ -824,6 +824,7 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_dev *dev,
+ 	pdd->qpd.dqm = dev->dqm;
+ 	pdd->qpd.pqm = &p->pqm;
+ 	pdd->qpd.evicted = 0;
++	pdd->qpd.mapped_gws_queue = false;
+ 	mutex_init(&pdd->qpd.doorbell_lock);
+ 	pdd->process = p;
+ 	pdd->bound = PDD_UNBOUND;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3922-drm-amdkfd-add-pre-alpha-debugger-versioning.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3922-drm-amdkfd-add-pre-alpha-debugger-versioning.patch
new file mode 100644
index 00000000..38e0fdfc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3922-drm-amdkfd-add-pre-alpha-debugger-versioning.patch
@@ -0,0 +1,120 @@
+From ac678417637b2f032450126406f891471201fabc Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Fri, 20 Sep 2019 15:02:47 -0400
+Subject: [PATCH 3922/4256] drm/amdkfd: add pre-alpha debugger versioning
+
+add temporary ioctl option in dbg trap to get pre-alpha debugger
+feature version
+
+Change-Id: Iffa579056b89088da0cc1863bf6833b9e710a1ee
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 24 +++++++++++++++---------
+ include/uapi/linux/kfd_ioctl.h           | 10 ++++++++++
+ 2 files changed, 25 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index 838a8d46ba47..1713413e5ce5 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -2611,8 +2611,8 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 	uint32_t data1;
+ 	uint32_t data2;
+ 	uint32_t data3;
+-	bool is_suspend_or_resume;
+-	bool is_q_snapshot;
++	bool need_device;
++	bool need_qid_array;
+ 
+ 	debug_trap_action = args->op;
+ 	gpu_id = args->gpu_id;
+@@ -2626,13 +2626,16 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 		goto out;
+ 	}
+ 
+-	is_suspend_or_resume =
++	need_device =
++		debug_trap_action != KFD_IOC_DBG_TRAP_NODE_SUSPEND &&
++		debug_trap_action != KFD_IOC_DBG_TRAP_NODE_RESUME &&
++		debug_trap_action != KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT &&
++		debug_trap_action != KFD_IOC_DBG_TRAP_GET_VERSION;
++
++	need_qid_array =
+ 		debug_trap_action == KFD_IOC_DBG_TRAP_NODE_SUSPEND ||
+ 		debug_trap_action == KFD_IOC_DBG_TRAP_NODE_RESUME;
+ 
+-	is_q_snapshot =
+-		debug_trap_action == KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT;
+-
+ 	pid = find_get_pid(args->pid);
+ 	if (!pid) {
+ 		pr_err("Cannot find pid info for %i\n",
+@@ -2666,7 +2669,7 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 
+ 	mutex_lock(&target->mutex);
+ 
+-	if (!(is_suspend_or_resume || is_q_snapshot)) {
++	if (need_device) {
+ 
+ 		dev = kfd_device_by_id(args->gpu_id);
+ 		if (!dev) {
+@@ -2710,7 +2713,7 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 			r = -EINVAL;
+ 			goto unlock_out;
+ 		}
+-	} else if (!is_q_snapshot) {
++	} else if (need_qid_array) {
+ 		/* data 2 has the number of queue IDs */
+ 		size_t queue_id_array_size = sizeof(uint32_t) * data2;
+ 
+@@ -2728,7 +2731,6 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 		}
+ 	}
+ 
+-
+ 	switch (debug_trap_action) {
+ 	case KFD_IOC_DBG_TRAP_ENABLE:
+ 		switch (data1) {
+@@ -2814,6 +2816,10 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 		if (r > 0)
+ 			r = 0;
+ 
++		break;
++	case KFD_IOC_DBG_TRAP_GET_VERSION:
++		args->data1 = KFD_IOCTL_DBG_MAJOR_VERSION;
++		args->data2 = KFD_IOCTL_DBG_MINOR_VERSION;
+ 		break;
+ 	default:
+ 		pr_err("Invalid option: %i\n", debug_trap_action);
+diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
+index be91603f2c0f..e126cfcb0bbe 100644
+--- a/include/uapi/linux/kfd_ioctl.h
++++ b/include/uapi/linux/kfd_ioctl.h
+@@ -28,6 +28,8 @@
+ 
+ #define KFD_IOCTL_MAJOR_VERSION 1
+ #define KFD_IOCTL_MINOR_VERSION 2
++#define KFD_IOCTL_DBG_MAJOR_VERSION	0
++#define KFD_IOCTL_DBG_MINOR_VERSION	1
+ 
+ struct kfd_ioctl_get_version_args {
+ 	__u32 major_version;	/* from KFD */
+@@ -273,6 +275,14 @@ struct kfd_ioctl_dbg_wave_control_args {
+  */
+ #define KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT 7
+ 
++/* KFD_IOC_DBG_TRAP_GET_VERSION:
++ * prt: unsused
++ * data1: major version (OUT)
++ * data2: minor version (OUT)
++ * data3: unused
++ */
++#define KFD_IOC_DBG_TRAP_GET_VERSION	8
++
+ struct kfd_ioctl_dbg_trap_args {
+ 	__u64 ptr;     /* to KFD -- used for pointer arguments: queue arrays */
+ 	__u32 pid;     /* to KFD */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3923-drm-amdkfd-fix-query-pending-event-with-unspecified-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3923-drm-amdkfd-fix-query-pending-event-with-unspecified-.patch
new file mode 100644
index 00000000..9b49b5d8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3923-drm-amdkfd-fix-query-pending-event-with-unspecified-.patch
@@ -0,0 +1,35 @@
+From 552de4fb9ebea138186d9f9b37c56d6d40b1567d Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Fri, 27 Sep 2019 04:03:42 -0400
+Subject: [PATCH 3923/4256] drm/amdkfd: fix query pending event with
+ unspecified queue id
+
+query pending event failed to return queue with both trap and vmfault pending
+event status when queue id is not specified.
+
+Change-Id: If18b8a34b14965d9dcd7c62ca568a82f2ee47c97
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
+index cabf26f03077..90d7215a4fd3 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug_events.c
+@@ -153,9 +153,8 @@ int kfd_dbg_ev_query_debug_event(struct kfd_process_device *pdd,
+ 		list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
+ 			if (pqn->q &&
+ 				 (pqn->q->properties.debug_event_type
+-					== KFD_DBG_EV_STATUS_TRAP
+-				|| pqn->q->properties.debug_event_type
+-					== KFD_DBG_EV_STATUS_VMFAULT)) {
++					& (KFD_DBG_EV_STATUS_TRAP
++					| KFD_DBG_EV_STATUS_VMFAULT))) {
+ 				*queue_id = pqn->q->properties.queue_id;
+ 				*event_status =
+ 					kfd_dbg_get_queue_status_word(pqn->q,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3924-include-uapi-linux-up-rev-debugger-pr-alpha-minor-re.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3924-include-uapi-linux-up-rev-debugger-pr-alpha-minor-re.patch
new file mode 100644
index 00000000..395c0f4a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3924-include-uapi-linux-up-rev-debugger-pr-alpha-minor-re.patch
@@ -0,0 +1,31 @@
+From c6e7d6cb1d0b67d0544d240e52335ba99b167a1e Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Fri, 27 Sep 2019 15:07:34 -0400
+Subject: [PATCH 3924/4256] include/uapi/linux: up rev debugger pr-alpha minor
+ rev
+
+one time revision bump.  in future all kernel feature add/fixes for
+debugger should include rev bump.
+
+Change-Id: I19f16f7ddbcc13bac266320abd57b7a721c4cc86
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+---
+ include/uapi/linux/kfd_ioctl.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
+index e126cfcb0bbe..8c9a5ab34d9e 100644
+--- a/include/uapi/linux/kfd_ioctl.h
++++ b/include/uapi/linux/kfd_ioctl.h
+@@ -29,7 +29,7 @@
+ #define KFD_IOCTL_MAJOR_VERSION 1
+ #define KFD_IOCTL_MINOR_VERSION 2
+ #define KFD_IOCTL_DBG_MAJOR_VERSION	0
+-#define KFD_IOCTL_DBG_MINOR_VERSION	1
++#define KFD_IOCTL_DBG_MINOR_VERSION	2
+ 
+ struct kfd_ioctl_get_version_args {
+ 	__u32 major_version;	/* from KFD */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3925-drm-amdgpu-remove-gfx9-NGG.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3925-drm-amdgpu-remove-gfx9-NGG.patch
new file mode 100644
index 00000000..76a6f619
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3925-drm-amdgpu-remove-gfx9-NGG.patch
@@ -0,0 +1,390 @@
+From 07f53a0f4b1f1c67c01959654d8a958d601ec01c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Thu, 19 Sep 2019 22:04:43 -0400
+Subject: [PATCH 3925/4256] drm/amdgpu: remove gfx9 NGG
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Never used.
+
+Signed-off-by: Marek Olšák <marek.olsak@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h     |   5 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  41 -----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  25 ---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  11 --
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 195 ------------------------
+ 5 files changed, 277 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 8c2c52fe43a9..24f3b548f368 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -151,11 +151,6 @@ extern char *amdgpu_disable_cu;
+ extern char *amdgpu_virtual_display;
+ extern uint amdgpu_pp_feature_mask;
+ extern int amdgpu_ssg_enabled;
+-extern int amdgpu_ngg;
+-extern int amdgpu_prim_buf_per_se;
+-extern int amdgpu_pos_buf_per_se;
+-extern int amdgpu_cntl_sb_buf_per_se;
+-extern int amdgpu_param_buf_per_se;
+ extern int amdgpu_job_hang_limit;
+ extern int amdgpu_lbpw;
+ extern int amdgpu_compute_multipipe;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 50f962a78a61..9f7118ab1e93 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -131,11 +131,6 @@ char *amdgpu_disable_cu = NULL;
+ char *amdgpu_virtual_display = NULL;
+ /* OverDrive(bit 14) disabled by default*/
+ uint amdgpu_pp_feature_mask = 0xffffbfff;
+-int amdgpu_ngg = 0;
+-int amdgpu_prim_buf_per_se = 0;
+-int amdgpu_pos_buf_per_se = 0;
+-int amdgpu_cntl_sb_buf_per_se = 0;
+-int amdgpu_param_buf_per_se = 0;
+ int amdgpu_job_hang_limit = 0;
+ int amdgpu_lbpw = -1;
+ int amdgpu_compute_multipipe = -1;
+@@ -464,42 +459,6 @@ MODULE_PARM_DESC(virtual_display,
+ 		 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
+ module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
+ 
+-/**
+- * DOC: ngg (int)
+- * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled).
+- */
+-MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
+-module_param_named(ngg, amdgpu_ngg, int, 0444);
+-
+-/**
+- * DOC: prim_buf_per_se (int)
+- * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
+- */
+-MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
+-module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
+-
+-/**
+- * DOC: pos_buf_per_se (int)
+- * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
+- */
+-MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)");
+-module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
+-
+-/**
+- * DOC: cntl_sb_buf_per_se (int)
+- * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx).
+- */
+-MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)");
+-module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
+-
+-/**
+- * DOC: param_buf_per_se (int)
+- * Override the size of Off-Chip Parameter Cache per Shader Engine in Byte.
+- * The default is 0 (depending on gfx).
+- */
+-MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)");
+-module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
+-
+ /**
+  * DOC: job_hang_limit (int)
+  * Set how much time allow a job hang and not drop it. The default is 0.
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+index 6ed0560d7299..59c5464c96be 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+@@ -200,28 +200,6 @@ struct amdgpu_gfx_funcs {
+ 	int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status);
+ };
+ 
+-struct amdgpu_ngg_buf {
+-	struct amdgpu_bo	*bo;
+-	uint64_t		gpu_addr;
+-	uint32_t		size;
+-	uint32_t		bo_size;
+-};
+-
+-enum {
+-	NGG_PRIM = 0,
+-	NGG_POS,
+-	NGG_CNTL,
+-	NGG_PARAM,
+-	NGG_BUF_MAX
+-};
+-
+-struct amdgpu_ngg {
+-	struct amdgpu_ngg_buf	buf[NGG_BUF_MAX];
+-	uint32_t		gds_reserve_addr;
+-	uint32_t		gds_reserve_size;
+-	bool			init;
+-};
+-
+ struct sq_work {
+ 	struct work_struct	work;
+ 	unsigned ih_data;
+@@ -310,9 +288,6 @@ struct amdgpu_gfx {
+ 	uint32_t                        grbm_soft_reset;
+ 	uint32_t                        srbm_soft_reset;
+ 
+-	/* NGG */
+-	struct amdgpu_ngg		ngg;
+-
+ 	/* gfx off */
+ 	bool                            gfx_off_state; /* true: enabled, false: disabled */
+ 	struct mutex                    gfx_off_mutex;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 9be4c182242f..75965119271b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -781,17 +781,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
+ 		dev_info.vce_harvest_config = adev->vce.harvest_config;
+ 		dev_info.gc_double_offchip_lds_buf =
+ 			adev->gfx.config.double_offchip_lds_buf;
+-
+-		if (amdgpu_ngg) {
+-			dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
+-			dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
+-			dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
+-			dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
+-			dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
+-			dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
+-			dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
+-			dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
+-		}
+ 		dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
+ 		dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
+ 		dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 946e21869a8e..c1f5970d59e6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -1953,190 +1953,6 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
+-static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
+-				   struct amdgpu_ngg_buf *ngg_buf,
+-				   int size_se,
+-				   int default_size_se)
+-{
+-	int r;
+-
+-	if (size_se < 0) {
+-		dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
+-		return -EINVAL;
+-	}
+-	size_se = size_se ? size_se : default_size_se;
+-
+-	ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
+-	r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
+-				    PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
+-				    &ngg_buf->bo,
+-				    &ngg_buf->gpu_addr,
+-				    NULL);
+-	if (r) {
+-		dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
+-		return r;
+-	}
+-	ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
+-
+-	return r;
+-}
+-
+-static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
+-{
+-	int i;
+-
+-	for (i = 0; i < NGG_BUF_MAX; i++)
+-		amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
+-				      &adev->gfx.ngg.buf[i].gpu_addr,
+-				      NULL);
+-
+-	memset(&adev->gfx.ngg.buf[0], 0,
+-			sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
+-
+-	adev->gfx.ngg.init = false;
+-
+-	return 0;
+-}
+-
+-static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
+-{
+-	int r;
+-
+-	if (!amdgpu_ngg || adev->gfx.ngg.init == true)
+-		return 0;
+-
+-	/* GDS reserve memory: 64 bytes alignment */
+-	adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
+-	adev->gds.gds_size -= adev->gfx.ngg.gds_reserve_size;
+-	adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
+-	adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
+-
+-	/* Primitive Buffer */
+-	r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
+-				    amdgpu_prim_buf_per_se,
+-				    64 * 1024);
+-	if (r) {
+-		dev_err(adev->dev, "Failed to create Primitive Buffer\n");
+-		goto err;
+-	}
+-
+-	/* Position Buffer */
+-	r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
+-				    amdgpu_pos_buf_per_se,
+-				    256 * 1024);
+-	if (r) {
+-		dev_err(adev->dev, "Failed to create Position Buffer\n");
+-		goto err;
+-	}
+-
+-	/* Control Sideband */
+-	r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
+-				    amdgpu_cntl_sb_buf_per_se,
+-				    256);
+-	if (r) {
+-		dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
+-		goto err;
+-	}
+-
+-	/* Parameter Cache, not created by default */
+-	if (amdgpu_param_buf_per_se <= 0)
+-		goto out;
+-
+-	r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
+-				    amdgpu_param_buf_per_se,
+-				    512 * 1024);
+-	if (r) {
+-		dev_err(adev->dev, "Failed to create Parameter Cache\n");
+-		goto err;
+-	}
+-
+-out:
+-	adev->gfx.ngg.init = true;
+-	return 0;
+-err:
+-	gfx_v9_0_ngg_fini(adev);
+-	return r;
+-}
+-
+-static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
+-{
+-	struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
+-	int r;
+-	u32 data, base;
+-
+-	if (!amdgpu_ngg)
+-		return 0;
+-
+-	/* Program buffer size */
+-	data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
+-			     adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
+-	data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
+-			     adev->gfx.ngg.buf[NGG_POS].size >> 8);
+-	WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
+-
+-	data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
+-			     adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
+-	data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
+-			     adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
+-	WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
+-
+-	/* Program buffer base address */
+-	base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
+-	data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
+-	WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
+-
+-	base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
+-	data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
+-	WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
+-
+-	base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
+-	data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
+-	WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
+-
+-	base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
+-	data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
+-	WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
+-
+-	base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
+-	data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
+-	WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
+-
+-	base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
+-	data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
+-	WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
+-
+-	/* Clear GDS reserved memory */
+-	r = amdgpu_ring_alloc(ring, 17);
+-	if (r) {
+-		DRM_ERROR("amdgpu: NGG failed to lock ring %s (%d).\n",
+-			  ring->name, r);
+-		return r;
+-	}
+-
+-	gfx_v9_0_write_data_to_reg(ring, 0, false,
+-				   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
+-			           (adev->gds.gds_size +
+-				    adev->gfx.ngg.gds_reserve_size));
+-
+-	amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
+-	amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
+-				PACKET3_DMA_DATA_DST_SEL(1) |
+-				PACKET3_DMA_DATA_SRC_SEL(2)));
+-	amdgpu_ring_write(ring, 0);
+-	amdgpu_ring_write(ring, 0);
+-	amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
+-	amdgpu_ring_write(ring, 0);
+-	amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
+-				adev->gfx.ngg.gds_reserve_size);
+-
+-	gfx_v9_0_write_data_to_reg(ring, 0, false,
+-				   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
+-
+-	amdgpu_ring_commit(ring);
+-
+-	return 0;
+-}
+-
+ static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
+ 				      int mec, int pipe, int queue)
+ {
+@@ -2304,10 +2120,6 @@ static int gfx_v9_0_sw_init(void *handle)
+ 	if (r)
+ 		return r;
+ 
+-	r = gfx_v9_0_ngg_init(adev);
+-	if (r)
+-		return r;
+-
+ 	return 0;
+ }
+ 
+@@ -2341,7 +2153,6 @@ static int gfx_v9_0_sw_fini(void *handle)
+ 	amdgpu_gfx_kiq_fini(adev);
+ 
+ 	gfx_v9_0_mec_fini(adev);
+-	gfx_v9_0_ngg_fini(adev);
+ 	amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
+ 	if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) {
+ 		amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
+@@ -3882,12 +3693,6 @@ static int gfx_v9_0_hw_init(void *handle)
+ 	if (r)
+ 		return r;
+ 
+-	if (adev->asic_type != CHIP_ARCTURUS) {
+-		r = gfx_v9_0_ngg_en(adev);
+-		if (r)
+-			return r;
+-	}
+-
+ 	return r;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3926-drm-amdgpu-fix-an-UMC-hw-arbitrator-bug-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3926-drm-amdgpu-fix-an-UMC-hw-arbitrator-bug-v3.patch
new file mode 100644
index 00000000..9e625971
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3926-drm-amdgpu-fix-an-UMC-hw-arbitrator-bug-v3.patch
@@ -0,0 +1,174 @@
+From b883d40dafb4c21f7e4a4d4a1dbb8ab7919a6e3d Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Tue, 24 Sep 2019 16:08:00 +0800
+Subject: [PATCH 3926/4256] drm/amdgpu: fix an UMC hw arbitrator bug(v3)
+
+issue:
+the UMC6 h/w bug is that when MCLK is doing the switch
+in the middle of a page access being preempted by high
+priority client (e.g. DISPLAY) then UMC and the mclk switch
+would stuck there due to deadlock
+
+how:
+fixed by disabling auto PreChg for UMC to avoid high
+priority client preempting other client's access on
+the same page, thus the deadlock could be avoided
+
+v2:
+put the patch in callback of UMC6
+v3:
+rename the callback to "init_registers"
+
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile     |  2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h |  1 +
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |  7 +++++
+ drivers/gpu/drm/amd/amdgpu/umc_v6_0.c   | 37 +++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/umc_v6_0.h   | 31 +++++++++++++++++++++
+ 5 files changed, 77 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/umc_v6_0.c
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/umc_v6_0.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index 1589a2489944..22c4bcbe7001 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -85,7 +85,7 @@ amdgpu-y += \
+ 
+ # add UMC block
+ amdgpu-y += \
+-	umc_v6_1.o
++	umc_v6_1.o umc_v6_0.o
+ 
+ # add IH block
+ amdgpu-y += \
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+index 3ec36d9e012a..c907b14c9be8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+@@ -63,6 +63,7 @@ struct amdgpu_umc_funcs {
+ 	void (*enable_umc_index_mode)(struct amdgpu_device *adev,
+ 					uint32_t umc_instance);
+ 	void (*disable_umc_index_mode)(struct amdgpu_device *adev);
++	void (*init_registers)(struct amdgpu_device *adev);
+ };
+ 
+ struct amdgpu_umc {
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index abd7a5e22c3f..88e09e4e8baf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -47,6 +47,7 @@
+ #include "gfxhub_v1_1.h"
+ #include "mmhub_v9_4.h"
+ #include "umc_v6_1.h"
++#include "umc_v6_0.h"
+ 
+ #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
+ 
+@@ -692,6 +693,9 @@ static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
+ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
+ {
+ 	switch (adev->asic_type) {
++	case CHIP_VEGA10:
++		adev->umc.funcs = &umc_v6_0_funcs;
++		break;
+ 	case CHIP_VEGA20:
+ 		adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
+ 		adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
+@@ -1313,6 +1317,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
+ 	for (i = 0; i < adev->num_vmhubs; ++i)
+ 		gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
+ 
++	if (adev->umc.funcs && adev->umc.funcs->init_registers)
++		adev->umc.funcs->init_registers(adev);
++
+ 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+ 		 (unsigned)(adev->gmc.gart_size >> 20),
+ 		 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_0.c
+new file mode 100644
+index 000000000000..0d6b50528d76
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_0.c
+@@ -0,0 +1,37 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "umc_v6_0.h"
++#include "amdgpu.h"
++
++static void umc_v6_0_init_registers(struct amdgpu_device *adev)
++{
++	unsigned i,j;
++
++	for (i = 0; i < 4; i++)
++		for (j = 0; j < 4; j++)
++			WREG32((i*0x100000 + 0x5010c + j*0x2000)/4, 0x1002);
++}
++
++const struct amdgpu_umc_funcs umc_v6_0_funcs = {
++	.init_registers = umc_v6_0_init_registers,
++};
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_0.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_0.h
+new file mode 100644
+index 000000000000..109f1a57a46e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_0.h
+@@ -0,0 +1,31 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __UMC_V6_0_H__
++#define __UMC_V6_0_H__
++
++#include "soc15_common.h"
++#include "amdgpu.h"
++
++extern const struct amdgpu_umc_funcs umc_v6_0_funcs;
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3927-drm-amdgpu-update-parameter-of-ras_ih_cb.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3927-drm-amdgpu-update-parameter-of-ras_ih_cb.patch
new file mode 100644
index 00000000..9dc2dd9a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3927-drm-amdgpu-update-parameter-of-ras_ih_cb.patch
@@ -0,0 +1,103 @@
+From 1d3a7d96ad1de74707e7050da09505e9d3209a80 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 12 Sep 2019 13:38:44 +0800
+Subject: [PATCH 3927/4256] drm/amdgpu: update parameter of ras_ih_cb
+
+change struct ras_err_data *err_data to void *err_data, align with
+umc code and the callback's declaration in each ras block could
+pay no attention to the structure type
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 2 +-
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 6 ++++--
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c  | 4 ++--
+ 4 files changed, 9 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index ae386c466c0e..f80fd3428c98 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -362,7 +362,7 @@ struct ras_err_handler_data {
+ };
+ 
+ typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
+-		struct ras_err_data *err_data,
++		void *err_data,
+ 		struct amdgpu_iv_entry *entry);
+ 
+ struct ras_ih_data {
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index c1f5970d59e6..edeac8eb8cc6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4202,7 +4202,7 @@ static int gfx_v9_0_early_init(void *handle)
+ }
+ 
+ static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+-		struct ras_err_data *err_data,
++		void *err_data,
+ 		struct amdgpu_iv_entry *entry);
+ 
+ static int gfx_v9_0_ecc_late_init(void *handle)
+@@ -5455,7 +5455,7 @@ static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
+ }
+ 
+ static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+-		struct ras_err_data *err_data,
++		void *err_data,
+ 		struct amdgpu_iv_entry *entry)
+ {
+ 	/* TODO ue will trigger an interrupt. */
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 88e09e4e8baf..534c5761c079 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -242,16 +242,18 @@ static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
+ }
+ 
+ static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+-		struct ras_err_data *err_data,
++		void *ras_error_status,
+ 		struct amdgpu_iv_entry *entry)
+ {
++	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
++
+ 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
+ 		return AMDGPU_RAS_SUCCESS;
+ 
+ 	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
+ 	if (adev->umc.funcs &&
+ 	    adev->umc.funcs->query_ras_error_count)
+-	    adev->umc.funcs->query_ras_error_count(adev, err_data);
++	    adev->umc.funcs->query_ras_error_count(adev, ras_error_status);
+ 
+ 	if (adev->umc.funcs &&
+ 	    adev->umc.funcs->query_ras_error_address &&
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 06f769acac62..4bb17d85a0ce 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1689,7 +1689,7 @@ static int sdma_v4_0_early_init(void *handle)
+ }
+ 
+ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
+-		struct ras_err_data *err_data,
++		void *err_data,
+ 		struct amdgpu_iv_entry *entry);
+ 
+ static int sdma_v4_0_late_init(void *handle)
+@@ -1938,7 +1938,7 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
+ }
+ 
+ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
+-		struct ras_err_data *err_data,
++		void *err_data,
+ 		struct amdgpu_iv_entry *entry)
+ {
+ 	uint32_t err_source;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3928-drm-amdgpu-move-umc-ras-irq-functions-to-umc-block.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3928-drm-amdgpu-move-umc-ras-irq-functions-to-umc-block.patch
new file mode 100644
index 00000000..85e45478
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3928-drm-amdgpu-move-umc-ras-irq-functions-to-umc-block.patch
@@ -0,0 +1,208 @@
+From 022ef19f50a9c183d2b0ad95716e594430ca260c Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 12 Sep 2019 11:11:25 +0800
+Subject: [PATCH 3928/4256] drm/amdgpu: move umc ras irq functions to umc block
+
+move umc ras irq functions from gmc v9 to generic umc block, these
+functions are relevant to umc and they can be shared among all
+generations of umc
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 65 ++++++++++++++++++++++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h |  6 +++
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 68 +------------------------
+ 3 files changed, 72 insertions(+), 67 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+index c5d8b08af731..d11b4d38ca1e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+@@ -21,7 +21,6 @@
+  *
+  */
+ 
+-#include "amdgpu.h"
+ #include "amdgpu_ras.h"
+ 
+ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_ih_info)
+@@ -75,3 +74,67 @@ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_ih_info)
+ 	adev->gmc.umc_ras_if = NULL;
+ 	return r;
+ }
++
++int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
++		void *ras_error_status,
++		struct amdgpu_iv_entry *entry)
++{
++	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
++
++	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
++		return AMDGPU_RAS_SUCCESS;
++
++	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
++	if (adev->umc.funcs &&
++	    adev->umc.funcs->query_ras_error_count)
++	    adev->umc.funcs->query_ras_error_count(adev, ras_error_status);
++
++	if (adev->umc.funcs &&
++	    adev->umc.funcs->query_ras_error_address &&
++	    adev->umc.max_ras_err_cnt_per_query) {
++		err_data->err_addr =
++			kcalloc(adev->umc.max_ras_err_cnt_per_query,
++				sizeof(struct eeprom_table_record), GFP_KERNEL);
++		/* still call query_ras_error_address to clear error status
++		 * even NOMEM error is encountered
++		 */
++		if(!err_data->err_addr)
++			DRM_WARN("Failed to alloc memory for umc error address record!\n");
++
++		/* umc query_ras_error_address is also responsible for clearing
++		 * error status
++		 */
++		adev->umc.funcs->query_ras_error_address(adev, ras_error_status);
++	}
++
++	/* only uncorrectable error needs gpu reset */
++	if (err_data->ue_count) {
++		if (err_data->err_addr_cnt &&
++		    amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
++						err_data->err_addr_cnt))
++			DRM_WARN("Failed to add ras bad page!\n");
++
++		amdgpu_ras_reset_gpu(adev, 0);
++	}
++
++	kfree(err_data->err_addr);
++	return AMDGPU_RAS_SUCCESS;
++}
++
++int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
++		struct amdgpu_irq_src *source,
++		struct amdgpu_iv_entry *entry)
++{
++	struct ras_common_if *ras_if = adev->gmc.umc_ras_if;
++	struct ras_dispatch_if ih_data = {
++		.entry = entry,
++	};
++
++	if (!ras_if)
++		return 0;
++
++	ih_data.head = *ras_if;
++
++	amdgpu_ras_interrupt_dispatch(adev, &ih_data);
++	return 0;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+index c907b14c9be8..9ac1c2f79299 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+@@ -82,4 +82,10 @@ struct amdgpu_umc {
+ };
+ 
+ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_ih_info);
++int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
++		void *ras_error_status,
++		struct amdgpu_iv_entry *entry);
++int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
++		struct amdgpu_irq_src *source,
++		struct amdgpu_iv_entry *entry);
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 534c5761c079..d6a99e2d6343 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -241,70 +241,6 @@ static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
+ 	return 0;
+ }
+ 
+-static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+-		void *ras_error_status,
+-		struct amdgpu_iv_entry *entry)
+-{
+-	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+-
+-	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
+-		return AMDGPU_RAS_SUCCESS;
+-
+-	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
+-	if (adev->umc.funcs &&
+-	    adev->umc.funcs->query_ras_error_count)
+-	    adev->umc.funcs->query_ras_error_count(adev, ras_error_status);
+-
+-	if (adev->umc.funcs &&
+-	    adev->umc.funcs->query_ras_error_address &&
+-	    adev->umc.max_ras_err_cnt_per_query) {
+-		err_data->err_addr =
+-			kcalloc(adev->umc.max_ras_err_cnt_per_query,
+-				sizeof(struct eeprom_table_record), GFP_KERNEL);
+-		/* still call query_ras_error_address to clear error status
+-		 * even NOMEM error is encountered
+-		 */
+-		if(!err_data->err_addr)
+-			DRM_WARN("Failed to alloc memory for umc error address record!\n");
+-
+-		/* umc query_ras_error_address is also responsible for clearing
+-		 * error status
+-		 */
+-		adev->umc.funcs->query_ras_error_address(adev, err_data);
+-	}
+-
+-	/* only uncorrectable error needs gpu reset */
+-	if (err_data->ue_count) {
+-		if (err_data->err_addr_cnt &&
+-		    amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
+-						err_data->err_addr_cnt))
+-			DRM_WARN("Failed to add ras bad page!\n");
+-
+-		amdgpu_ras_reset_gpu(adev, 0);
+-	}
+-
+-	kfree(err_data->err_addr);
+-	return AMDGPU_RAS_SUCCESS;
+-}
+-
+-static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev,
+-		struct amdgpu_irq_src *source,
+-		struct amdgpu_iv_entry *entry)
+-{
+-	struct ras_common_if *ras_if = adev->gmc.umc_ras_if;
+-	struct ras_dispatch_if ih_data = {
+-		.entry = entry,
+-	};
+-
+-	if (!ras_if)
+-		return 0;
+-
+-	ih_data.head = *ras_if;
+-
+-	amdgpu_ras_interrupt_dispatch(adev, &ih_data);
+-	return 0;
+-}
+-
+ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
+ 					struct amdgpu_irq_src *src,
+ 					unsigned type,
+@@ -445,7 +381,7 @@ static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
+ 
+ static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
+ 	.set = gmc_v9_0_ecc_interrupt_state,
+-	.process = gmc_v9_0_process_ecc_irq,
++	.process = amdgpu_umc_process_ecc_irq,
+ };
+ 
+ static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
+@@ -801,7 +737,7 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ 	int r;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 	struct ras_ih_if umc_ih_info = {
+-		.cb = gmc_v9_0_process_ras_data_cb,
++		.cb = amdgpu_umc_process_ras_data_cb,
+ 	};
+ 
+ 	if (adev->umc.funcs && adev->umc.funcs->ras_late_init) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3929-drm-amdgpu-move-gfx-ecc-functions-to-generic-gfx-fil.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3929-drm-amdgpu-move-gfx-ecc-functions-to-generic-gfx-fil.patch
new file mode 100644
index 00000000..f8addef6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3929-drm-amdgpu-move-gfx-ecc-functions-to-generic-gfx-fil.patch
@@ -0,0 +1,152 @@
+From b2b6ce6d6ec7bc017402393544f278f9ee94d090 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 12 Sep 2019 14:06:35 +0800
+Subject: [PATCH 3929/4256] drm/amdgpu: move gfx ecc functions to generic gfx
+ file
+
+gfx ras ecc common functions could be reused among all gfx generations
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 33 ++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  6 ++++
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 41 ++-----------------------
+ 3 files changed, 41 insertions(+), 39 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+index 508d521a0e59..e7d87f717737 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+@@ -618,3 +618,36 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev,
+ 	adev->gfx.ras_if = NULL;
+ 	return r;
+ }
++
++int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
++		void *err_data,
++		struct amdgpu_iv_entry *entry)
++{
++	/* TODO ue will trigger an interrupt. */
++	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
++		kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
++		if (adev->gfx.funcs->query_ras_error_count)
++			adev->gfx.funcs->query_ras_error_count(adev, err_data);
++		amdgpu_ras_reset_gpu(adev, 0);
++	}
++	return AMDGPU_RAS_SUCCESS;
++}
++
++int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
++				  struct amdgpu_irq_src *source,
++				  struct amdgpu_iv_entry *entry)
++{
++	struct ras_common_if *ras_if = adev->gfx.ras_if;
++	struct ras_dispatch_if ih_data = {
++		.entry = entry,
++	};
++
++	if (!ras_if)
++		return 0;
++
++	ih_data.head = *ras_if;
++
++	DRM_ERROR("CP ECC ERROR IRQ\n");
++	amdgpu_ras_interrupt_dispatch(adev, &ih_data);
++	return 0;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+index 59c5464c96be..179dd4e980b7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+@@ -360,4 +360,10 @@ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
+ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
+ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev,
+ 			     void *ras_ih_info);
++int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
++		void *err_data,
++		struct amdgpu_iv_entry *entry);
++int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
++				  struct amdgpu_irq_src *source,
++				  struct amdgpu_iv_entry *entry);
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index edeac8eb8cc6..b238f8b45336 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4201,15 +4201,11 @@ static int gfx_v9_0_early_init(void *handle)
+ 	return 0;
+ }
+ 
+-static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+-		void *err_data,
+-		struct amdgpu_iv_entry *entry);
+-
+ static int gfx_v9_0_ecc_late_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 	struct ras_ih_if ih_info = {
+-		.cb = gfx_v9_0_process_ras_data_cb,
++		.cb = amdgpu_gfx_process_ras_data_cb,
+ 	};
+ 	int r;
+ 
+@@ -5454,20 +5450,6 @@ static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
+ 	return 0;
+ }
+ 
+-static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+-		void *err_data,
+-		struct amdgpu_iv_entry *entry)
+-{
+-	/* TODO ue will trigger an interrupt. */
+-	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
+-		kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
+-		if (adev->gfx.funcs->query_ras_error_count)
+-			adev->gfx.funcs->query_ras_error_count(adev, err_data);
+-		amdgpu_ras_reset_gpu(adev, 0);
+-	}
+-	return AMDGPU_RAS_SUCCESS;
+-}
+-
+ static const struct {
+ 	const char *name;
+ 	uint32_t ip;
+@@ -5876,25 +5858,6 @@ static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
+ 	return 0;
+ }
+ 
+-static int gfx_v9_0_cp_ecc_error_irq(struct amdgpu_device *adev,
+-				  struct amdgpu_irq_src *source,
+-				  struct amdgpu_iv_entry *entry)
+-{
+-	struct ras_common_if *ras_if = adev->gfx.ras_if;
+-	struct ras_dispatch_if ih_data = {
+-		.entry = entry,
+-	};
+-
+-	if (!ras_if)
+-		return 0;
+-
+-	ih_data.head = *ras_if;
+-
+-	DRM_ERROR("CP ECC ERROR IRQ\n");
+-	amdgpu_ras_interrupt_dispatch(adev, &ih_data);
+-	return 0;
+-}
+-
+ static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
+ 	.name = "gfx_v9_0",
+ 	.early_init = gfx_v9_0_early_init,
+@@ -6058,7 +6021,7 @@ static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
+ 
+ static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = {
+ 	.set = gfx_v9_0_set_cp_ecc_error_state,
+-	.process = gfx_v9_0_cp_ecc_error_irq,
++	.process = amdgpu_gfx_cp_ecc_error_irq,
+ };
+ 
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3930-drm-amdgpu-move-sdma-ecc-functions-to-generic-sdma-f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3930-drm-amdgpu-move-sdma-ecc-functions-to-generic-sdma-f.patch
new file mode 100644
index 00000000..cef5ea9c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3930-drm-amdgpu-move-sdma-ecc-functions-to-generic-sdma-f.patch
@@ -0,0 +1,117 @@
+From ad4ef9903771a4416b57fefc427467b2b1cb2bac Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 12 Sep 2019 14:28:18 +0800
+Subject: [PATCH 3930/4256] drm/amdgpu: move sdma ecc functions to generic sdma
+ file
+
+sdma ras ecc functions can be reused among all sdma generations
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 28 ++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h |  6 +++++
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 24 ++------------------
+ 3 files changed, 36 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+index a25301b75ef7..b294157c1deb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+@@ -135,3 +135,31 @@ int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
+ 	adev->sdma.ras_if = NULL;
+ 	return r;
+ }
++
++int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
++		void *err_data,
++		struct amdgpu_iv_entry *entry)
++{
++	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
++	amdgpu_ras_reset_gpu(adev, 0);
++
++	return AMDGPU_RAS_SUCCESS;
++}
++
++int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
++				      struct amdgpu_irq_src *source,
++				      struct amdgpu_iv_entry *entry)
++{
++	struct ras_common_if *ras_if = adev->sdma.ras_if;
++	struct ras_dispatch_if ih_data = {
++		.entry = entry,
++	};
++
++	if (!ras_if)
++		return 0;
++
++	ih_data.head = *ras_if;
++
++	amdgpu_ras_interrupt_dispatch(adev, &ih_data);
++	return 0;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+index 79dcb907d00d..95e01d522537 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+@@ -106,4 +106,10 @@ int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
+ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
+ int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
+ 			      void *ras_ih_info);
++int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
++		void *err_data,
++		struct amdgpu_iv_entry *entry);
++int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
++				      struct amdgpu_irq_src *source,
++				      struct amdgpu_iv_entry *entry);
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 4bb17d85a0ce..ca30cbfad59f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1960,32 +1960,12 @@ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
+ 			return 0;
+ 		}
+ 
+-		kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
+-
+-		amdgpu_ras_reset_gpu(adev, 0);
++		amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
+ 	}
+ 
+ 	return AMDGPU_RAS_SUCCESS;
+ }
+ 
+-static int sdma_v4_0_process_ecc_irq(struct amdgpu_device *adev,
+-				      struct amdgpu_irq_src *source,
+-				      struct amdgpu_iv_entry *entry)
+-{
+-	struct ras_common_if *ras_if = adev->sdma.ras_if;
+-	struct ras_dispatch_if ih_data = {
+-		.entry = entry,
+-	};
+-
+-	if (!ras_if)
+-		return 0;
+-
+-	ih_data.head = *ras_if;
+-
+-	amdgpu_ras_interrupt_dispatch(adev, &ih_data);
+-	return 0;
+-}
+-
+ static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
+ 					      struct amdgpu_irq_src *source,
+ 					      struct amdgpu_iv_entry *entry)
+@@ -2333,7 +2313,7 @@ static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
+ 
+ static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = {
+ 	.set = sdma_v4_0_set_ecc_irq_state,
+-	.process = sdma_v4_0_process_ecc_irq,
++	.process = amdgpu_sdma_process_ecc_irq,
+ };
+ 
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3931-drm-amdgpu-refine-sdma4-ras_data_cb.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3931-drm-amdgpu-refine-sdma4-ras_data_cb.patch
new file mode 100644
index 00000000..69954930
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3931-drm-amdgpu-refine-sdma4-ras_data_cb.patch
@@ -0,0 +1,58 @@
+From 298dcc0e4f171fc5fdcd86328b8321558941156d Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Tue, 17 Sep 2019 19:01:38 +0800
+Subject: [PATCH 3931/4256] drm/amdgpu: refine sdma4 ras_data_cb
+
+simplify code logic and refine return value
+
+v2: remove unused error source code
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 24 +++++++-----------------
+ 1 file changed, 7 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index ca30cbfad59f..2ce0ecce145f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1941,28 +1941,18 @@ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
+ 		void *err_data,
+ 		struct amdgpu_iv_entry *entry)
+ {
+-	uint32_t err_source;
+ 	int instance;
+ 
+-	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
+-		instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
+-		if (instance < 0)
+-			return 0;
++	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
++		goto out;
+ 
+-		switch (entry->src_id) {
+-		case SDMA0_4_0__SRCID__SDMA_SRAM_ECC:
+-			err_source = 0;
+-			break;
+-		case SDMA0_4_0__SRCID__SDMA_ECC:
+-			err_source = 1;
+-			break;
+-		default:
+-			return 0;
+-		}
++	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
++	if (instance < 0)
++		goto out;
+ 
+-		amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
+-	}
++	amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
+ 
++out:
+ 	return AMDGPU_RAS_SUCCESS;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3932-drm-amdgpu-move-umc_ras_if-from-gmc-to-umc-block.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3932-drm-amdgpu-move-umc_ras_if-from-gmc-to-umc-block.patch
new file mode 100644
index 00000000..a871a2e6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3932-drm-amdgpu-move-umc_ras_if-from-gmc-to-umc-block.patch
@@ -0,0 +1,120 @@
+From 5262d5f0d2b7ebc4b732607697b33ea89018278d Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 12 Sep 2019 16:34:08 +0800
+Subject: [PATCH 3932/4256] drm/amdgpu: move umc_ras_if from gmc to umc block
+
+umc_ras_if is relevant to umc
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  1 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 28 ++++++++++++-------------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h |  1 +
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |  4 ++--
+ 4 files changed, 17 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+index 88894fd2784d..7cfb0b72161e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+@@ -181,7 +181,6 @@ struct amdgpu_gmc {
+ 
+ 	struct amdgpu_xgmi xgmi;
+ 	struct amdgpu_irq_src	ecc_irq;
+-	struct ras_common_if    *umc_ras_if;
+ 	struct ras_common_if    *mmhub_ras_if;
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+index d11b4d38ca1e..acc0c428f6fa 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+@@ -35,24 +35,24 @@ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_ih_info)
+ 	if (!ih_info)
+ 		return -EINVAL;
+ 
+-	if (!adev->gmc.umc_ras_if) {
+-		adev->gmc.umc_ras_if =
++	if (!adev->umc.ras_if) {
++		adev->umc.ras_if =
+ 			kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
+-		if (!adev->gmc.umc_ras_if)
++		if (!adev->umc.ras_if)
+ 			return -ENOMEM;
+-		adev->gmc.umc_ras_if->block = AMDGPU_RAS_BLOCK__UMC;
+-		adev->gmc.umc_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
+-		adev->gmc.umc_ras_if->sub_block_index = 0;
+-		strcpy(adev->gmc.umc_ras_if->name, "umc");
++		adev->umc.ras_if->block = AMDGPU_RAS_BLOCK__UMC;
++		adev->umc.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++		adev->umc.ras_if->sub_block_index = 0;
++		strcpy(adev->umc.ras_if->name, "umc");
+ 	}
+-	ih_info->head = fs_info.head = *adev->gmc.umc_ras_if;
++	ih_info->head = fs_info.head = *adev->umc.ras_if;
+ 
+-	r = amdgpu_ras_late_init(adev, adev->gmc.umc_ras_if,
++	r = amdgpu_ras_late_init(adev, adev->umc.ras_if,
+ 				 &fs_info, ih_info);
+ 	if (r)
+ 		goto free;
+ 
+-	if (amdgpu_ras_is_supported(adev, adev->gmc.umc_ras_if->block)) {
++	if (amdgpu_ras_is_supported(adev, adev->umc.ras_if->block)) {
+ 		r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
+ 		if (r)
+ 			goto late_fini;
+@@ -68,10 +68,10 @@ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_ih_info)
+ 	return 0;
+ 
+ late_fini:
+-	amdgpu_ras_late_fini(adev, adev->gmc.umc_ras_if, ih_info);
++	amdgpu_ras_late_fini(adev, adev->umc.ras_if, ih_info);
+ free:
+-	kfree(adev->gmc.umc_ras_if);
+-	adev->gmc.umc_ras_if = NULL;
++	kfree(adev->umc.ras_if);
++	adev->umc.ras_if = NULL;
+ 	return r;
+ }
+ 
+@@ -125,7 +125,7 @@ int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
+ 		struct amdgpu_irq_src *source,
+ 		struct amdgpu_iv_entry *entry)
+ {
+-	struct ras_common_if *ras_if = adev->gmc.umc_ras_if;
++	struct ras_common_if *ras_if = adev->umc.ras_if;
+ 	struct ras_dispatch_if ih_data = {
+ 		.entry = entry,
+ 	};
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+index 9ac1c2f79299..72c378aec724 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+@@ -77,6 +77,7 @@ struct amdgpu_umc {
+ 	uint32_t channel_offs;
+ 	/* channel index table of interleaved memory */
+ 	const uint32_t *channel_idx_tbl;
++	struct ras_common_if *ras_if;
+ 
+ 	const struct amdgpu_umc_funcs *funcs;
+ };
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index d6a99e2d6343..307b153e42c1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -1119,8 +1119,8 @@ static int gmc_v9_0_sw_fini(void *handle)
+ 	void *stolen_vga_buf;
+ 
+ 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
+-			adev->gmc.umc_ras_if) {
+-		struct ras_common_if *ras_if = adev->gmc.umc_ras_if;
++			adev->umc.ras_if) {
++		struct ras_common_if *ras_if = adev->umc.ras_if;
+ 		struct ras_ih_if ih_info = {
+ 			.head = *ras_if,
+ 		};
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3933-drm-amdgpu-add-common-mmhub-member-for-adev.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3933-drm-amdgpu-add-common-mmhub-member-for-adev.patch
new file mode 100644
index 00000000..f0f42ad4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3933-drm-amdgpu-add-common-mmhub-member-for-adev.patch
@@ -0,0 +1,47 @@
+From afc008806da6aad3f5f31e77cdb14040411bc1f6 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 12 Sep 2019 17:03:14 +0800
+Subject: [PATCH 3933/4256] drm/amdgpu: add common mmhub member for adev
+
+put mmhub_funcs and ras_if pointer into mmhub struct
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h       | 3 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h | 5 +++++
+ 2 files changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 24f3b548f368..483e747ff316 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -909,6 +909,9 @@ struct amdgpu_device {
+ 	/* nbio */
+ 	struct amdgpu_nbio		nbio;
+ 
++	/* mmhub */
++	struct amdgpu_mmhub		mmhub;
++
+ 	/* gfx */
+ 	struct amdgpu_gfx		gfx;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
+index 685e54e58700..a733898c7d55 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
+@@ -28,6 +28,11 @@ struct amdgpu_mmhub_funcs {
+ 					void *ras_error_status);
+ };
+ 
++struct amdgpu_mmhub {
++	struct ras_common_if *ras_if;
++	const struct amdgpu_mmhub_funcs *funcs;
++};
++
+ int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev);
+ 
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3934-drm-amdgpu-replace-mmhub_funcs-with-mmhub.funcs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3934-drm-amdgpu-replace-mmhub_funcs-with-mmhub.funcs.patch
new file mode 100644
index 00000000..b6a4755c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3934-drm-amdgpu-replace-mmhub_funcs-with-mmhub.funcs.patch
@@ -0,0 +1,69 @@
+From 30ae76ab833a101e957e324e22865d58f5cfd418 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 12 Sep 2019 17:12:21 +0800
+Subject: [PATCH 3934/4256] drm/amdgpu: replace mmhub_funcs with mmhub.funcs
+
+remove mmhub_funcs in adev
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 1 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 6 +++---
+ 3 files changed, 5 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 483e747ff316..59e465ad4abf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -966,7 +966,6 @@ struct amdgpu_device {
+ 	uint32_t 		*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
+ 
+ 	const struct amdgpu_df_funcs	*df_funcs;
+-	const struct amdgpu_mmhub_funcs	*mmhub_funcs;
+ 
+ 	/* delayed work_func for deferring clockgating during resume */
+ 	struct delayed_work     delayed_init_work;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 48541adb12fb..f0dd1c3c928c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -691,8 +691,8 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev,
+ 			adev->gfx.funcs->query_ras_error_count(adev, &err_data);
+ 		break;
+ 	case AMDGPU_RAS_BLOCK__MMHUB:
+-		if (adev->mmhub_funcs->query_ras_error_count)
+-			adev->mmhub_funcs->query_ras_error_count(adev, &err_data);
++		if (adev->mmhub.funcs->query_ras_error_count)
++			adev->mmhub.funcs->query_ras_error_count(adev, &err_data);
+ 		break;
+ 	case AMDGPU_RAS_BLOCK__PCIE_BIF:
+ 		if (adev->nbio.funcs->query_ras_error_count)
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 307b153e42c1..8f9373d57c48 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -651,7 +651,7 @@ static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
+ {
+ 	switch (adev->asic_type) {
+ 	case CHIP_VEGA20:
+-		adev->mmhub_funcs = &mmhub_v1_0_funcs;
++		adev->mmhub.funcs = &mmhub_v1_0_funcs;
+ 		break;
+ 	default:
+ 		break;
+@@ -746,8 +746,8 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ 			return r;
+ 	}
+ 
+-	if (adev->mmhub_funcs && adev->mmhub_funcs->ras_late_init) {
+-		r = adev->mmhub_funcs->ras_late_init(adev);
++	if (adev->mmhub.funcs && adev->mmhub.funcs->ras_late_init) {
++		r = adev->mmhub.funcs->ras_late_init(adev);
+ 		if (r)
+ 			return r;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3935-drm-amdgpu-move-mmhub_ras_if-from-gmc-to-mmhub-block.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3935-drm-amdgpu-move-mmhub_ras_if-from-gmc-to-mmhub-block.patch
new file mode 100644
index 00000000..d3861f4d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3935-drm-amdgpu-move-mmhub_ras_if-from-gmc-to-mmhub-block.patch
@@ -0,0 +1,84 @@
+From c1e252066c84b0aee58d6d81ba402aeb959c1724 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 12 Sep 2019 17:21:46 +0800
+Subject: [PATCH 3935/4256] drm/amdgpu: move mmhub_ras_if from gmc to mmhub
+ block
+
+mmhub_ras_if is relevant to mmhub
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h   |  1 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c | 24 +++++++++++------------
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c     |  4 ++--
+ 3 files changed, 14 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+index 7cfb0b72161e..a0c04f1fb256 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+@@ -181,7 +181,6 @@ struct amdgpu_gmc {
+ 
+ 	struct amdgpu_xgmi xgmi;
+ 	struct amdgpu_irq_src	ecc_irq;
+-	struct ras_common_if    *mmhub_ras_if;
+ };
+ 
+ #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c
+index 99ef6b1f8526..fe1709ee8f4b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c
+@@ -35,21 +35,21 @@ int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev)
+ 		.debugfs_name = "mmhub_err_inject",
+ 	};
+ 
+-	if (!adev->gmc.mmhub_ras_if) {
+-		adev->gmc.mmhub_ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
+-		if (!adev->gmc.mmhub_ras_if)
++	if (!adev->mmhub.ras_if) {
++		adev->mmhub.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
++		if (!adev->mmhub.ras_if)
+ 			return -ENOMEM;
+-		adev->gmc.mmhub_ras_if->block = AMDGPU_RAS_BLOCK__MMHUB;
+-		adev->gmc.mmhub_ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
+-		adev->gmc.mmhub_ras_if->sub_block_index = 0;
+-		strcpy(adev->gmc.mmhub_ras_if->name, "mmhub");
++		adev->mmhub.ras_if->block = AMDGPU_RAS_BLOCK__MMHUB;
++		adev->mmhub.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
++		adev->mmhub.ras_if->sub_block_index = 0;
++		strcpy(adev->mmhub.ras_if->name, "mmhub");
+ 	}
+-	ih_info.head = fs_info.head = *adev->gmc.mmhub_ras_if;
+-	r = amdgpu_ras_late_init(adev, adev->gmc.mmhub_ras_if,
++	ih_info.head = fs_info.head = *adev->mmhub.ras_if;
++	r = amdgpu_ras_late_init(adev, adev->mmhub.ras_if,
+ 				 &fs_info, &ih_info);
+-	if (r || !amdgpu_ras_is_supported(adev, adev->gmc.mmhub_ras_if->block)) {
+-		kfree(adev->gmc.mmhub_ras_if);
+-		adev->gmc.mmhub_ras_if = NULL;
++	if (r || !amdgpu_ras_is_supported(adev, adev->mmhub.ras_if->block)) {
++		kfree(adev->mmhub.ras_if);
++		adev->mmhub.ras_if = NULL;
+ 	}
+ 
+ 	return r;
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 8f9373d57c48..06f2d073db55 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -1135,8 +1135,8 @@ static int gmc_v9_0_sw_fini(void *handle)
+ 	}
+ 
+ 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) &&
+-			adev->gmc.mmhub_ras_if) {
+-		struct ras_common_if *ras_if = adev->gmc.mmhub_ras_if;
++			adev->mmhub.ras_if) {
++		struct ras_common_if *ras_if = adev->mmhub.ras_if;
+ 
+ 		/* remove fs and disable ras feature */
+ 		amdgpu_ras_debugfs_remove(adev, ras_if);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3936-drm-amdgpu-add-common-gmc_ras_fini-function.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3936-drm-amdgpu-add-common-gmc_ras_fini-function.patch
new file mode 100644
index 00000000..ef49fa79
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3936-drm-amdgpu-add-common-gmc_ras_fini-function.patch
@@ -0,0 +1,102 @@
+From a088ac456990448e69dbb43b00e7aa17e7afe5af Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 12 Sep 2019 17:39:47 +0800
+Subject: [PATCH 3936/4256] drm/amdgpu: add common gmc_ras_fini function
+
+gmc_ras_fini can be shared among all generations of gmc
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 26 +++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  1 +
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 28 +------------------------
+ 3 files changed, 28 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+index dc044eec188e..58a95a67336a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+@@ -304,3 +304,29 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
+ 	gmc->fault_hash[hash].idx = gmc->last_fault++;
+ 	return false;
+ }
++
++void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
++{
++	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
++			adev->umc.ras_if) {
++		struct ras_common_if *ras_if = adev->umc.ras_if;
++		struct ras_ih_if ih_info = {
++			.head = *ras_if,
++			.cb = amdgpu_umc_process_ras_data_cb,
++		};
++
++		amdgpu_ras_late_fini(adev, ras_if, &ih_info);
++		kfree(ras_if);
++	}
++
++	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) &&
++			adev->mmhub.ras_if) {
++		struct ras_common_if *ras_if = adev->mmhub.ras_if;
++		struct ras_ih_if ih_info = {
++			.cb = NULL,
++		};
++
++		amdgpu_ras_late_fini(adev, ras_if, &ih_info);
++		kfree(ras_if);
++	}
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+index a0c04f1fb256..9dd9c47cb47d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+@@ -233,5 +233,6 @@ void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
+ 			     struct amdgpu_gmc *mc);
+ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
+ 			      uint16_t pasid, uint64_t timestamp);
++void amdgpu_gmc_ras_fini(struct amdgpu_device *adev);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 06f2d073db55..6570c3f41bf2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -1118,33 +1118,7 @@ static int gmc_v9_0_sw_fini(void *handle)
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 	void *stolen_vga_buf;
+ 
+-	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
+-			adev->umc.ras_if) {
+-		struct ras_common_if *ras_if = adev->umc.ras_if;
+-		struct ras_ih_if ih_info = {
+-			.head = *ras_if,
+-		};
+-
+-		/* remove fs first */
+-		amdgpu_ras_debugfs_remove(adev, ras_if);
+-		amdgpu_ras_sysfs_remove(adev, ras_if);
+-		/* remove the IH */
+-		amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
+-		amdgpu_ras_feature_enable(adev, ras_if, 0);
+-		kfree(ras_if);
+-	}
+-
+-	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) &&
+-			adev->mmhub.ras_if) {
+-		struct ras_common_if *ras_if = adev->mmhub.ras_if;
+-
+-		/* remove fs and disable ras feature */
+-		amdgpu_ras_debugfs_remove(adev, ras_if);
+-		amdgpu_ras_sysfs_remove(adev, ras_if);
+-		amdgpu_ras_feature_enable(adev, ras_if, 0);
+-		kfree(ras_if);
+-	}
+-
++	amdgpu_gmc_ras_fini(adev);
+ 	amdgpu_gem_force_release(adev);
+ 	amdgpu_vm_manager_fini(adev);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3937-drm-amdgpu-add-common-gfx_ras_fini-function.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3937-drm-amdgpu-add-common-gfx_ras_fini-function.patch
new file mode 100644
index 00000000..b1785a8f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3937-drm-amdgpu-add-common-gfx_ras_fini-function.patch
@@ -0,0 +1,81 @@
+From 533ca3e9df21c2e9534799da23c9e660fb8661d2 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 12 Sep 2019 17:44:49 +0800
+Subject: [PATCH 3937/4256] drm/amdgpu: add common gfx_ras_fini function
+
+gfx_ras_fini can be shared among all generations of gfx
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 15 +++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  1 +
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 14 +-------------
+ 3 files changed, 17 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+index e7d87f717737..c0d297acb19c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+@@ -619,6 +619,21 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev,
+ 	return r;
+ }
+ 
++void amdgpu_gfx_ras_fini(struct amdgpu_device *adev)
++{
++	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX) &&
++			adev->gfx.ras_if) {
++		struct ras_common_if *ras_if = adev->gfx.ras_if;
++		struct ras_ih_if ih_info = {
++			.head = *ras_if,
++			.cb = amdgpu_gfx_process_ras_data_cb,
++		};
++
++		amdgpu_ras_late_fini(adev, ras_if, &ih_info);
++		kfree(ras_if);
++	}
++}
++
+ int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
+ 		void *err_data,
+ 		struct amdgpu_iv_entry *entry)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+index 179dd4e980b7..70a940911724 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+@@ -360,6 +360,7 @@ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
+ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
+ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev,
+ 			     void *ras_ih_info);
++void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
+ int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
+ 		void *err_data,
+ 		struct amdgpu_iv_entry *entry);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index b238f8b45336..225b22841f5c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -2129,19 +2129,7 @@ static int gfx_v9_0_sw_fini(void *handle)
+ 	int i;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
+-	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX) &&
+-			adev->gfx.ras_if) {
+-		struct ras_common_if *ras_if = adev->gfx.ras_if;
+-		struct ras_ih_if ih_info = {
+-			.head = *ras_if,
+-		};
+-
+-		amdgpu_ras_debugfs_remove(adev, ras_if);
+-		amdgpu_ras_sysfs_remove(adev, ras_if);
+-		amdgpu_ras_interrupt_remove_handler(adev,  &ih_info);
+-		amdgpu_ras_feature_enable(adev, ras_if, 0);
+-		kfree(ras_if);
+-	}
++	amdgpu_gfx_ras_fini(adev);
+ 
+ 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
+ 		amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3938-drm-amdgpu-add-common-sdma_ras_fini-function.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3938-drm-amdgpu-add-common-sdma_ras_fini-function.patch
new file mode 100644
index 00000000..e8ca8718
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3938-drm-amdgpu-add-common-sdma_ras_fini-function.patch
@@ -0,0 +1,87 @@
+From 48cb5693e7d60df67c59e78075d644492d72397b Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 12 Sep 2019 18:19:02 +0800
+Subject: [PATCH 3938/4256] drm/amdgpu: add common sdma_ras_fini function
+
+sdma_ras_fini can be shared among all generations of sdma
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 19 +++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h |  1 +
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 16 +---------------
+ 3 files changed, 21 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+index b294157c1deb..6361b2c9ae1a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+@@ -136,6 +136,25 @@ int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
+ 	return r;
+ }
+ 
++void amdgpu_sdma_ras_fini(struct amdgpu_device *adev)
++{
++	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA) &&
++			adev->sdma.ras_if) {
++		struct ras_common_if *ras_if = adev->sdma.ras_if;
++		struct ras_ih_if ih_info = {
++			.head = *ras_if,
++			/* the cb member will not be used by
++			 * amdgpu_ras_interrupt_remove_handler, init it only
++			 * to cheat the check in ras_late_fini
++			 */
++			.cb = amdgpu_sdma_process_ras_data_cb,
++		};
++
++		amdgpu_ras_late_fini(adev, ras_if, &ih_info);
++		kfree(ras_if);
++	}
++}
++
+ int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
+ 		void *err_data,
+ 		struct amdgpu_iv_entry *entry)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+index 95e01d522537..761ff8be6314 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+@@ -106,6 +106,7 @@ int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
+ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
+ int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
+ 			      void *ras_ih_info);
++void amdgpu_sdma_ras_fini(struct amdgpu_device *adev);
+ int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
+ 		void *err_data,
+ 		struct amdgpu_iv_entry *entry);
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 2ce0ecce145f..1dac74c441bb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1771,21 +1771,7 @@ static int sdma_v4_0_sw_fini(void *handle)
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 	int i;
+ 
+-	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA) &&
+-			adev->sdma.ras_if) {
+-		struct ras_common_if *ras_if = adev->sdma.ras_if;
+-		struct ras_ih_if ih_info = {
+-			.head = *ras_if,
+-		};
+-
+-		/*remove fs first*/
+-		amdgpu_ras_debugfs_remove(adev, ras_if);
+-		amdgpu_ras_sysfs_remove(adev, ras_if);
+-		/*remove the IH*/
+-		amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
+-		amdgpu_ras_feature_enable(adev, ras_if, 0);
+-		kfree(ras_if);
+-	}
++	amdgpu_sdma_ras_fini(adev);
+ 
+ 	for (i = 0; i < adev->sdma.num_instances; i++) {
+ 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3939-drm-amdgpu-remove-ih_info-parameter-of-umc_ras_late_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3939-drm-amdgpu-remove-ih_info-parameter-of-umc_ras_late_.patch
new file mode 100644
index 00000000..aebb1919
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3939-drm-amdgpu-remove-ih_info-parameter-of-umc_ras_late_.patch
@@ -0,0 +1,107 @@
+From 0b9558274eee9a0cbaf7978feb4b5cf75c935aa6 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 12 Sep 2019 18:54:33 +0800
+Subject: [PATCH 3939/4256] drm/amdgpu: remove ih_info parameter of
+ umc_ras_late_init
+
+umc_ras_late_init can get the info by itself
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 15 +++++++--------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h |  4 ++--
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |  5 +----
+ 3 files changed, 10 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+index acc0c428f6fa..08037f086d28 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+@@ -23,17 +23,16 @@
+ 
+ #include "amdgpu_ras.h"
+ 
+-int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_ih_info)
++int amdgpu_umc_ras_late_init(struct amdgpu_device *adev)
+ {
+ 	int r;
+-	struct ras_ih_if *ih_info = (struct ras_ih_if *)ras_ih_info;
+ 	struct ras_fs_if fs_info = {
+ 		.sysfs_name = "umc_err_count",
+ 		.debugfs_name = "umc_err_inject",
+ 	};
+-
+-	if (!ih_info)
+-		return -EINVAL;
++	struct ras_ih_if ih_info = {
++		.cb = amdgpu_umc_process_ras_data_cb,
++	};
+ 
+ 	if (!adev->umc.ras_if) {
+ 		adev->umc.ras_if =
+@@ -45,10 +44,10 @@ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_ih_info)
+ 		adev->umc.ras_if->sub_block_index = 0;
+ 		strcpy(adev->umc.ras_if->name, "umc");
+ 	}
+-	ih_info->head = fs_info.head = *adev->umc.ras_if;
++	ih_info.head = fs_info.head = *adev->umc.ras_if;
+ 
+ 	r = amdgpu_ras_late_init(adev, adev->umc.ras_if,
+-				 &fs_info, ih_info);
++				 &fs_info, &ih_info);
+ 	if (r)
+ 		goto free;
+ 
+@@ -68,7 +67,7 @@ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_ih_info)
+ 	return 0;
+ 
+ late_fini:
+-	amdgpu_ras_late_fini(adev, adev->umc.ras_if, ih_info);
++	amdgpu_ras_late_fini(adev, adev->umc.ras_if, &ih_info);
+ free:
+ 	kfree(adev->umc.ras_if);
+ 	adev->umc.ras_if = NULL;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+index 72c378aec724..8cc9852e99e6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+@@ -55,7 +55,7 @@
+ 
+ struct amdgpu_umc_funcs {
+ 	void (*err_cnt_init)(struct amdgpu_device *adev);
+-	int (*ras_late_init)(struct amdgpu_device *adev, void *ras_ih_info);
++	int (*ras_late_init)(struct amdgpu_device *adev);
+ 	void (*query_ras_error_count)(struct amdgpu_device *adev,
+ 					void *ras_error_status);
+ 	void (*query_ras_error_address)(struct amdgpu_device *adev,
+@@ -82,7 +82,7 @@ struct amdgpu_umc {
+ 	const struct amdgpu_umc_funcs *funcs;
+ };
+ 
+-int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_ih_info);
++int amdgpu_umc_ras_late_init(struct amdgpu_device *adev);
+ int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
+ 		void *ras_error_status,
+ 		struct amdgpu_iv_entry *entry);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 6570c3f41bf2..a7ef9f3f5207 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -736,12 +736,9 @@ static int gmc_v9_0_ecc_late_init(void *handle)
+ {
+ 	int r;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	struct ras_ih_if umc_ih_info = {
+-		.cb = amdgpu_umc_process_ras_data_cb,
+-	};
+ 
+ 	if (adev->umc.funcs && adev->umc.funcs->ras_late_init) {
+-		r = adev->umc.funcs->ras_late_init(adev, &umc_ih_info);
++		r = adev->umc.funcs->ras_late_init(adev);
+ 		if (r)
+ 			return r;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3940-drm-amdgpu-remove-ih_info-parameter-of-gfx_ras_late_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3940-drm-amdgpu-remove-ih_info-parameter-of-gfx_ras_late_.patch
new file mode 100644
index 00000000..520bcae6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3940-drm-amdgpu-remove-ih_info-parameter-of-gfx_ras_late_.patch
@@ -0,0 +1,100 @@
+From 5b513fca1696b4936bd333ba29ca3061bd1bbde9 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 19 Sep 2019 11:46:11 +0800
+Subject: [PATCH 3940/4256] drm/amdgpu: remove ih_info parameter of
+ gfx_ras_late_init
+
+gfx_ras_late_init can get the info by itself
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 16 +++++++---------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  3 +--
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   |  5 +----
+ 3 files changed, 9 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+index c0d297acb19c..d1c436df0f3a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+@@ -571,18 +571,16 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
+ 	mutex_unlock(&adev->gfx.gfx_off_mutex);
+ }
+ 
+-int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev,
+-			     void *ras_ih_info)
++int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev)
+ {
+ 	int r;
+-	struct ras_ih_if *ih_info = (struct ras_ih_if *)ras_ih_info;
+ 	struct ras_fs_if fs_info = {
+ 		.sysfs_name = "gfx_err_count",
+ 		.debugfs_name = "gfx_err_inject",
+ 	};
+-
+-	if (!ih_info)
+-		return -EINVAL;
++	struct ras_ih_if ih_info = {
++		.cb = amdgpu_gfx_process_ras_data_cb,
++	};
+ 
+ 	if (!adev->gfx.ras_if) {
+ 		adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
+@@ -593,10 +591,10 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev,
+ 		adev->gfx.ras_if->sub_block_index = 0;
+ 		strcpy(adev->gfx.ras_if->name, "gfx");
+ 	}
+-	fs_info.head = ih_info->head = *adev->gfx.ras_if;
++	fs_info.head = ih_info.head = *adev->gfx.ras_if;
+ 
+ 	r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
+-				 &fs_info, ih_info);
++				 &fs_info, &ih_info);
+ 	if (r)
+ 		goto free;
+ 
+@@ -612,7 +610,7 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev,
+ 
+ 	return 0;
+ late_fini:
+-	amdgpu_ras_late_fini(adev, adev->gfx.ras_if, ih_info);
++	amdgpu_ras_late_fini(adev, adev->gfx.ras_if, &ih_info);
+ free:
+ 	kfree(adev->gfx.ras_if);
+ 	adev->gfx.ras_if = NULL;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+index 70a940911724..c5179a807a04 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+@@ -358,8 +358,7 @@ void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
+ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
+ 				    int pipe, int queue);
+ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
+-int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev,
+-			     void *ras_ih_info);
++int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev);
+ void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
+ int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
+ 		void *err_data,
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 225b22841f5c..5f7956004627 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4192,12 +4192,9 @@ static int gfx_v9_0_early_init(void *handle)
+ static int gfx_v9_0_ecc_late_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-	struct ras_ih_if ih_info = {
+-		.cb = amdgpu_gfx_process_ras_data_cb,
+-	};
+ 	int r;
+ 
+-	r = amdgpu_gfx_ras_late_init(adev, &ih_info);
++	r = amdgpu_gfx_ras_late_init(adev);
+ 	if (r)
+ 		return r;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3941-drm-amdgpu-simplify-the-access-to-eeprom_control-str.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3941-drm-amdgpu-simplify-the-access-to-eeprom_control-str.patch
new file mode 100644
index 00000000..1ce5d34c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3941-drm-amdgpu-simplify-the-access-to-eeprom_control-str.patch
@@ -0,0 +1,44 @@
+From 1893fa5099afd14f5cb34d0fab8586f8611740a7 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Wed, 18 Sep 2019 15:26:23 +0800
+Subject: [PATCH 3941/4256] drm/amdgpu: simplify the access to eeprom_control
+ struct
+
+simplify the code of accessing to eeprom_control struct
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index f0dd1c3c928c..e43ade828c88 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1459,7 +1459,7 @@ static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
+ 	save_count = data->count - control->num_recs;
+ 	/* only new entries are saved */
+ 	if (save_count > 0)
+-		if (amdgpu_ras_eeprom_process_recods(&con->eeprom_control,
++		if (amdgpu_ras_eeprom_process_recods(control,
+ 							&data->bps[control->num_recs],
+ 							true,
+ 							save_count)) {
+@@ -1589,11 +1589,11 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
+ 	atomic_set(&con->in_recovery, 0);
+ 	con->adev = adev;
+ 
+-	ret = amdgpu_ras_eeprom_init(&adev->psp.ras.ras->eeprom_control);
++	ret = amdgpu_ras_eeprom_init(&con->eeprom_control);
+ 	if (ret)
+ 		goto free;
+ 
+-	if (adev->psp.ras.ras->eeprom_control.num_recs) {
++	if (con->eeprom_control.num_recs) {
+ 		ret = amdgpu_ras_load_bad_pages(adev);
+ 		if (ret)
+ 			goto free;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3942-drm-amdgpu-add-ras-fini-for-nbio.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3942-drm-amdgpu-add-ras-fini-for-nbio.patch
new file mode 100644
index 00000000..25d11997
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3942-drm-amdgpu-add-ras-fini-for-nbio.patch
@@ -0,0 +1,63 @@
+From 338a97d4f5bb1371a8d886539d426d34d4eb1e64 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Wed, 18 Sep 2019 17:30:50 +0800
+Subject: [PATCH 3942/4256] drm/amdgpu: add ras fini for nbio
+
+add a common nbio ras fini implementation to cleanup nbio ras framework
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c | 14 ++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h |  2 +-
+ drivers/gpu/drm/amd/amdgpu/soc15.c       |  1 +
+ 3 files changed, 16 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
+index 65373ad03763..7d5c3a9de9ea 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
+@@ -68,3 +68,17 @@ int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev)
+ 	adev->nbio.ras_if = NULL;
+ 	return r;
+ }
++
++void amdgpu_nbio_ras_fini(struct amdgpu_device *adev)
++{
++	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF) &&
++			adev->nbio.ras_if) {
++		struct ras_common_if *ras_if = adev->nbio.ras_if;
++		struct ras_ih_if ih_info = {
++			.cb = NULL,
++		};
++
++		amdgpu_ras_late_fini(adev, ras_if, &ih_info);
++		kfree(ras_if);
++	}
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+index 9e26b81ba6ad..1f26a17e6561 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+@@ -95,5 +95,5 @@ struct amdgpu_nbio {
+ };
+ 
+ int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev);
+-
++void amdgpu_nbio_ras_fini(struct amdgpu_device *adev);
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index a66ef0460762..14c7fc141322 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1247,6 +1247,7 @@ static int soc15_common_sw_fini(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
++	amdgpu_nbio_ras_fini(adev);
+ 	adev->df_funcs->sw_fini(adev);
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3943-drm-amdgpu-add-ras-fini-for-xgmi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3943-drm-amdgpu-add-ras-fini-for-xgmi.patch
new file mode 100644
index 00000000..095c3f8e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3943-drm-amdgpu-add-ras-fini-for-xgmi.patch
@@ -0,0 +1,36 @@
+From a9ea1cc8cca850d803c4a4147c729036ccf70e97 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Wed, 18 Sep 2019 17:40:06 +0800
+Subject: [PATCH 3943/4256] drm/amdgpu: add ras fini for xgmi
+
+add ras fini for xgmi to cleanup xgmi ras framework
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+index 58a95a67336a..4cd206ee3e0b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+@@ -329,4 +329,15 @@ void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
+ 		amdgpu_ras_late_fini(adev, ras_if, &ih_info);
+ 		kfree(ras_if);
+ 	}
++
++	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL) &&
++			adev->gmc.xgmi.ras_if) {
++		struct ras_common_if *ras_if = adev->gmc.xgmi.ras_if;
++		struct ras_ih_if ih_info = {
++			.cb = NULL,
++		};
++
++		amdgpu_ras_late_fini(adev, ras_if, &ih_info);
++		kfree(ras_if);
++	}
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3944-drm-amdgpu-move-umc-ras-fini-to-umc-block.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3944-drm-amdgpu-move-umc-ras-fini-to-umc-block.patch
new file mode 100644
index 00000000..dc0e8f1e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3944-drm-amdgpu-move-umc-ras-fini-to-umc-block.patch
@@ -0,0 +1,79 @@
+From 610b3a7fe70518a412ff5f4d8c5d379f9710d1f4 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Wed, 18 Sep 2019 17:46:42 +0800
+Subject: [PATCH 3944/4256] drm/amdgpu: move umc ras fini to umc block
+
+it's more suitable to put umc ras fini in umc block
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 12 +-----------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 15 +++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h |  1 +
+ 3 files changed, 17 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+index 4cd206ee3e0b..bf8084deb028 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+@@ -307,17 +307,7 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
+ 
+ void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
+ {
+-	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
+-			adev->umc.ras_if) {
+-		struct ras_common_if *ras_if = adev->umc.ras_if;
+-		struct ras_ih_if ih_info = {
+-			.head = *ras_if,
+-			.cb = amdgpu_umc_process_ras_data_cb,
+-		};
+-
+-		amdgpu_ras_late_fini(adev, ras_if, &ih_info);
+-		kfree(ras_if);
+-	}
++	amdgpu_umc_ras_fini(adev);
+ 
+ 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) &&
+ 			adev->mmhub.ras_if) {
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+index 08037f086d28..7744de149949 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+@@ -74,6 +74,21 @@ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev)
+ 	return r;
+ }
+ 
++void amdgpu_umc_ras_fini(struct amdgpu_device *adev)
++{
++	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
++			adev->umc.ras_if) {
++		struct ras_common_if *ras_if = adev->umc.ras_if;
++		struct ras_ih_if ih_info = {
++			.head = *ras_if,
++			.cb = amdgpu_umc_process_ras_data_cb,
++		};
++
++		amdgpu_ras_late_fini(adev, ras_if, &ih_info);
++		kfree(ras_if);
++	}
++}
++
+ int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
+ 		void *ras_error_status,
+ 		struct amdgpu_iv_entry *entry)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+index 8cc9852e99e6..3283032a78e5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+@@ -83,6 +83,7 @@ struct amdgpu_umc {
+ };
+ 
+ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev);
++void amdgpu_umc_ras_fini(struct amdgpu_device *adev);
+ int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
+ 		void *ras_error_status,
+ 		struct amdgpu_iv_entry *entry);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3945-drm-amdgpu-move-mmhub-ras-fini-to-mmhub-block.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3945-drm-amdgpu-move-mmhub-ras-fini-to-mmhub-block.patch
new file mode 100644
index 00000000..3d5af4ce
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3945-drm-amdgpu-move-mmhub-ras-fini-to-mmhub-block.patch
@@ -0,0 +1,75 @@
+From 0d45e36b2b4094885fc5c2d4bdfb138413c2e989 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Wed, 18 Sep 2019 17:51:20 +0800
+Subject: [PATCH 3945/4256] drm/amdgpu: move mmhub ras fini to mmhub block
+
+it's more suitable to put mmhub ras fini in mmhub block
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c   | 12 +-----------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c | 14 ++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h |  2 +-
+ 3 files changed, 16 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+index bf8084deb028..d35669e0dbac 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+@@ -308,17 +308,7 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
+ void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
+ {
+ 	amdgpu_umc_ras_fini(adev);
+-
+-	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) &&
+-			adev->mmhub.ras_if) {
+-		struct ras_common_if *ras_if = adev->mmhub.ras_if;
+-		struct ras_ih_if ih_info = {
+-			.cb = NULL,
+-		};
+-
+-		amdgpu_ras_late_fini(adev, ras_if, &ih_info);
+-		kfree(ras_if);
+-	}
++	amdgpu_mmhub_ras_fini(adev);
+ 
+ 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL) &&
+ 			adev->gmc.xgmi.ras_if) {
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c
+index fe1709ee8f4b..676c48c02d77 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c
+@@ -54,3 +54,17 @@ int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev)
+ 
+ 	return r;
+ }
++
++void amdgpu_mmhub_ras_fini(struct amdgpu_device *adev)
++{
++	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) &&
++			adev->mmhub.ras_if) {
++		struct ras_common_if *ras_if = adev->mmhub.ras_if;
++		struct ras_ih_if ih_info = {
++			.cb = NULL,
++		};
++
++		amdgpu_ras_late_fini(adev, ras_if, &ih_info);
++		kfree(ras_if);
++	}
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
+index a733898c7d55..1cd78940cf82 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
+@@ -34,6 +34,6 @@ struct amdgpu_mmhub {
+ };
+ 
+ int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev);
+-
++void amdgpu_mmhub_ras_fini(struct amdgpu_device *adev);
+ #endif
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3946-drm-amdgpu-move-xgmi-ras-fini-to-xgmi-block.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3946-drm-amdgpu-move-xgmi-ras-fini-to-xgmi-block.patch
new file mode 100644
index 00000000..b6b15805
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3946-drm-amdgpu-move-xgmi-ras-fini-to-xgmi-block.patch
@@ -0,0 +1,81 @@
+From 26ab314c0c94d8656b2b256735b7bbe5e6524f21 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Wed, 18 Sep 2019 17:58:14 +0800
+Subject: [PATCH 3946/4256] drm/amdgpu: move xgmi ras fini to xgmi block
+
+it's more suitable to put xgmi ras fini in xgmi block
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c  | 13 ++-----------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 14 ++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h |  1 +
+ 3 files changed, 17 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+index d35669e0dbac..8dc5251d346f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+@@ -26,6 +26,7 @@
+ 
+ #include "amdgpu.h"
+ #include "amdgpu_ras.h"
++#include "amdgpu_xgmi.h"
+ 
+ /**
+  * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
+@@ -309,15 +310,5 @@ void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
+ {
+ 	amdgpu_umc_ras_fini(adev);
+ 	amdgpu_mmhub_ras_fini(adev);
+-
+-	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL) &&
+-			adev->gmc.xgmi.ras_if) {
+-		struct ras_common_if *ras_if = adev->gmc.xgmi.ras_if;
+-		struct ras_ih_if ih_info = {
+-			.cb = NULL,
+-		};
+-
+-		amdgpu_ras_late_fini(adev, ras_if, &ih_info);
+-		kfree(ras_if);
+-	}
++	amdgpu_xgmi_ras_fini(adev);
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+index 0fa1d2416b57..ba88acdf87ec 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+@@ -472,3 +472,17 @@ int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev)
+ 
+ 	return r;
+ }
++
++void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev)
++{
++	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL) &&
++			adev->gmc.xgmi.ras_if) {
++		struct ras_common_if *ras_if = adev->gmc.xgmi.ras_if;
++		struct ras_ih_if ih_info = {
++			.cb = NULL,
++		};
++
++		amdgpu_ras_late_fini(adev, ras_if, &ih_info);
++		kfree(ras_if);
++	}
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
+index 9023789397c0..bbf504ff7051 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
+@@ -43,6 +43,7 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate);
+ int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
+ 		struct amdgpu_device *peer_adev);
+ int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev);
++void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev);
+ 
+ static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,
+ 		struct amdgpu_device *bo_adev)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3947-drm-amdgpu-implement-common-gmc_ras_late_init.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3947-drm-amdgpu-implement-common-gmc_ras_late_init.patch
new file mode 100644
index 00000000..5a9ae8b0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3947-drm-amdgpu-implement-common-gmc_ras_late_init.patch
@@ -0,0 +1,102 @@
+From 1e29fc6cc7d5d385a8a79ea0591579006c37dc0c Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Wed, 18 Sep 2019 18:31:07 +0800
+Subject: [PATCH 3947/4256] drm/amdgpu: implement common gmc_ras_late_init
+
+common gmc_ecc_late_init can be shared among all generations of gmc
+
+v2: rename gmc_ecc_late_init to gmc_ras_late_init
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 19 +++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  1 +
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 22 +---------------------
+ 3 files changed, 21 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+index 8dc5251d346f..3ffd7fe16679 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+@@ -306,6 +306,25 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
+ 	return false;
+ }
+ 
++int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (adev->umc.funcs && adev->umc.funcs->ras_late_init) {
++		r = adev->umc.funcs->ras_late_init(adev);
++		if (r)
++			return r;
++	}
++
++	if (adev->mmhub.funcs && adev->mmhub.funcs->ras_late_init) {
++		r = adev->mmhub.funcs->ras_late_init(adev);
++		if (r)
++			return r;
++	}
++
++	return amdgpu_xgmi_ras_late_init(adev);
++}
++
+ void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
+ {
+ 	amdgpu_umc_ras_fini(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+index 9dd9c47cb47d..387cf338c958 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+@@ -233,6 +233,7 @@ void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
+ 			     struct amdgpu_gmc *mc);
+ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
+ 			      uint16_t pasid, uint64_t timestamp);
++int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev);
+ void amdgpu_gmc_ras_fini(struct amdgpu_device *adev);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index a7ef9f3f5207..5b6f97f4a875 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -732,26 +732,6 @@ static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
+-static int gmc_v9_0_ecc_late_init(void *handle)
+-{
+-	int r;
+-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-
+-	if (adev->umc.funcs && adev->umc.funcs->ras_late_init) {
+-		r = adev->umc.funcs->ras_late_init(adev);
+-		if (r)
+-			return r;
+-	}
+-
+-	if (adev->mmhub.funcs && adev->mmhub.funcs->ras_late_init) {
+-		r = adev->mmhub.funcs->ras_late_init(adev);
+-		if (r)
+-			return r;
+-	}
+-
+-	return amdgpu_xgmi_ras_late_init(adev);
+-}
+-
+ static int gmc_v9_0_late_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+@@ -789,7 +769,7 @@ static int gmc_v9_0_late_init(void *handle)
+ 		}
+ 	}
+ 
+-	r = gmc_v9_0_ecc_late_init(handle);
++	r = amdgpu_gmc_ras_late_init(adev);
+ 	if (r)
+ 		return r;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3948-drm-amdgpu-add-comments-in-ras-interrupt-callback.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3948-drm-amdgpu-add-comments-in-ras-interrupt-callback.patch
new file mode 100644
index 00000000..c5827ef7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3948-drm-amdgpu-add-comments-in-ras-interrupt-callback.patch
@@ -0,0 +1,66 @@
+From fa95f0afe23433ca448e2b008934dace6697c7bf Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Mon, 23 Sep 2019 19:10:19 +0800
+Subject: [PATCH 3948/4256] drm/amdgpu: add comments in ras interrupt callback
+
+add comments to clarify why checking GFX IP BLOCK for each ras interrupt callback
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 7 ++++++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 4 ++++
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c  | 4 ++++
+ 3 files changed, 14 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+index d1c436df0f3a..fdcb7057093f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+@@ -636,7 +636,12 @@ int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
+ 		void *err_data,
+ 		struct amdgpu_iv_entry *entry)
+ {
+-	/* TODO ue will trigger an interrupt. */
++	/* TODO ue will trigger an interrupt.
++	 *
++	 * When “Full RAS� is enabled, the per-IP interrupt sources should
++	 * be disabled and the driver should only look for the aggregated
++	 * interrupt via sync flood
++	 */
+ 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
+ 		kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
+ 		if (adev->gfx.funcs->query_ras_error_count)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+index 7744de149949..d4fb9cf27e21 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+@@ -95,6 +95,10 @@ int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
+ {
+ 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+ 
++	/* When “Full RAS� is enabled, the per-IP interrupt sources should
++	 * be disabled and the driver should only look for the aggregated
++	 * interrupt via sync flood
++	 */
+ 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
+ 		return AMDGPU_RAS_SUCCESS;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 1dac74c441bb..cf784a4caa24 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1929,6 +1929,10 @@ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
+ {
+ 	int instance;
+ 
++	/* When “Full RAS� is enabled, the per-IP interrupt sources should
++	 * be disabled and the driver should only look for the aggregated
++	 * interrupt via sync flood
++	 */
+ 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
+ 		goto out;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3949-drm-amd-powerplay-update-arcturus-smu-driver-interac.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3949-drm-amd-powerplay-update-arcturus-smu-driver-interac.patch
new file mode 100644
index 00000000..5c701d78
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3949-drm-amd-powerplay-update-arcturus-smu-driver-interac.patch
@@ -0,0 +1,83 @@
+From c655e54c5190bf8fb7296e43d4633b12eaba69d9 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 24 Sep 2019 12:43:51 +0800
+Subject: [PATCH 3949/4256] drm/amd/powerplay: update arcturus smu-driver
+ interaction header
+
+To pair the latest SMU firmware.
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+---
+ .../amd/powerplay/inc/smu11_driver_if_arcturus.h  | 15 ++++++++-------
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h     |  2 +-
+ 2 files changed, 9 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+index 40a51a141336..2248d682c462 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+@@ -137,23 +137,23 @@
+ #define FEATURE_DS_SOCCLK_MASK            (1 << FEATURE_DS_SOCCLK_BIT            )
+ #define FEATURE_DS_LCLK_MASK              (1 << FEATURE_DS_LCLK_BIT              )
+ #define FEATURE_DS_FCLK_MASK              (1 << FEATURE_DS_FCLK_BIT              )
+-#define FEATURE_DS_LCLK_MASK              (1 << FEATURE_DS_LCLK_BIT              )
++#define FEATURE_DS_UCLK_MASK              (1 << FEATURE_DS_UCLK_BIT              )
+ #define FEATURE_GFX_ULV_MASK              (1 << FEATURE_GFX_ULV_BIT              )
+-#define FEATURE_VCN_PG_MASK               (1 << FEATURE_VCN_PG_BIT               )
++#define FEATURE_DPM_VCN_MASK              (1 << FEATURE_DPM_VCN_BIT              )
+ #define FEATURE_RSMU_SMN_CG_MASK          (1 << FEATURE_RSMU_SMN_CG_BIT          )
+ #define FEATURE_WAFL_CG_MASK              (1 << FEATURE_WAFL_CG_BIT              )
+ 
+ #define FEATURE_PPT_MASK                  (1 << FEATURE_PPT_BIT                  )
+ #define FEATURE_TDC_MASK                  (1 << FEATURE_TDC_BIT                  )
+-#define FEATURE_APCC_MASK                 (1 << FEATURE_APCC_BIT                 )
++#define FEATURE_APCC_PLUS_MASK            (1 << FEATURE_APCC_PLUS_BIT            )
+ #define FEATURE_VR0HOT_MASK               (1 << FEATURE_VR0HOT_BIT               )
+ #define FEATURE_VR1HOT_MASK               (1 << FEATURE_VR1HOT_BIT               )
+ #define FEATURE_FW_CTF_MASK               (1 << FEATURE_FW_CTF_BIT               )
+ #define FEATURE_FAN_CONTROL_MASK          (1 << FEATURE_FAN_CONTROL_BIT          )
+ #define FEATURE_THERMAL_MASK              (1 << FEATURE_THERMAL_BIT              )
+ 
+-#define FEATURE_OUT_OF_BAND_MONITOR_MASK  (1 << EATURE_OUT_OF_BAND_MONITOR_BIT   )
+-#define FEATURE_TEMP_DEPENDENT_VMIN_MASK  (1 << FEATURE_TEMP_DEPENDENT_VMIN_MASK )
++#define FEATURE_OUT_OF_BAND_MONITOR_MASK  (1 << FEATURE_OUT_OF_BAND_MONITOR_BIT   )
++#define FEATURE_TEMP_DEPENDENT_VMIN_MASK  (1 << FEATURE_TEMP_DEPENDENT_VMIN_BIT )
+ 
+ 
+ //FIXME need updating
+@@ -806,7 +806,7 @@ typedef struct {
+ 
+   uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units
+ 
+-  uint32_t EnabledAvfsModules[2];
++  uint32_t EnabledAvfsModules[3];
+ 
+   uint32_t MmHubPadding[8]; // SMU internal use
+ } AvfsFuseOverride_t;
+@@ -869,7 +869,8 @@ typedef struct {
+ //#define TABLE_ACTIVITY_MONITOR_COEFF  7
+ #define TABLE_OVERDRIVE               7
+ #define TABLE_WAFL_XGMI_TOPOLOGY      8
+-#define TABLE_COUNT                   9
++#define TABLE_I2C_COMMANDS            9
++#define TABLE_COUNT                   10
+ 
+ // These defines are used with the SMC_MSG_SetUclkFastSwitch message.
+ typedef enum {
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index af1add570153..e71f6fedf3c6 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -27,7 +27,7 @@
+ 
+ #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
+ #define SMU11_DRIVER_IF_VERSION_VG20 0x13
+-#define SMU11_DRIVER_IF_VERSION_ARCT 0x0A
++#define SMU11_DRIVER_IF_VERSION_ARCT 0x0D
+ #define SMU11_DRIVER_IF_VERSION_NV10 0x33
+ #define SMU11_DRIVER_IF_VERSION_NV12 0x33
+ #define SMU11_DRIVER_IF_VERSION_NV14 0x34
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3950-drm-amdgpu-cleanup-creating-BOs-at-fixed-location-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3950-drm-amdgpu-cleanup-creating-BOs-at-fixed-location-v2.patch
new file mode 100644
index 00000000..fb4bc4b5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3950-drm-amdgpu-cleanup-creating-BOs-at-fixed-location-v2.patch
@@ -0,0 +1,339 @@
+From fdd6f2f9931efbf78c89e29fe2e6ea95b22870e9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Fri, 13 Sep 2019 13:43:15 +0200
+Subject: [PATCH 3950/4256] drm/amdgpu: cleanup creating BOs at fixed location
+ (v2)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The placement is something TTM/BO internal and the RAS code should
+avoid touching that directly.
+
+Add a helper to create a BO at a fixed location and use that instead.
+
+v2: squash in fixes (Alex)
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 61 ++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  3 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c    | 85 ++--------------------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    | 79 +++-----------------
+ 4 files changed, 81 insertions(+), 147 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+index c82d35faf91c..b08bbecb63f2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+@@ -363,6 +363,67 @@ int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
+ 	return 0;
+ }
+ 
++/**
++ * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location
++ *
++ * @adev: amdgpu device object
++ * @offset: offset of the BO
++ * @size: size of the BO
++ * @domain: where to place it
++ * @bo_ptr:  used to initialize BOs in structures
++ * @cpu_addr: optional CPU address mapping
++ *
++ * Creates a kernel BO at a specific offset in the address space of the domain.
++ *
++ * Returns:
++ * 0 on success, negative error code otherwise.
++ */
++int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
++			       uint64_t offset, uint64_t size, uint32_t domain,
++			       struct amdgpu_bo **bo_ptr, void **cpu_addr)
++{
++	struct ttm_operation_ctx ctx = { false, false };
++	unsigned int i;
++	int r;
++
++	offset &= PAGE_MASK;
++	size = ALIGN(size, PAGE_SIZE);
++
++	r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr,
++				      NULL, NULL);
++	if (r)
++		return r;
++
++	/*
++	 * Remove the original mem node and create a new one at the request
++	 * position.
++	 */
++	for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) {
++		(*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT;
++		(*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
++	}
++
++	ttm_bo_mem_put(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem);
++	r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement,
++			     &(*bo_ptr)->tbo.mem, &ctx);
++	if (r)
++		goto error;
++
++	if (cpu_addr) {
++		r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
++		if (r)
++			goto error;
++	}
++
++	amdgpu_bo_unreserve(*bo_ptr);
++	return 0;
++
++error:
++	amdgpu_bo_unreserve(*bo_ptr);
++	amdgpu_bo_unref(bo_ptr);
++	return r;
++}
++
+ /**
+  * amdgpu_bo_free_kernel - free BO for kernel use
+  *
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+index c3047d2d1833..57f41bed2898 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+@@ -243,6 +243,9 @@ int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
+ 			    unsigned long size, int align,
+ 			    u32 domain, struct amdgpu_bo **bo_ptr,
+ 			    u64 *gpu_addr, void **cpu_addr);
++int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
++			       uint64_t offset, uint64_t size, uint32_t domain,
++			       struct amdgpu_bo **bo_ptr, void **cpu_addr);
+ void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
+ 			   void **cpu_addr);
+ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index e43ade828c88..2cd94d4b3309 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -69,12 +69,6 @@ const char *ras_block_string[] = {
+ 
+ atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
+ 
+-static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev,
+-		uint64_t offset, uint64_t size,
+-		struct amdgpu_bo **bo_ptr);
+-static int amdgpu_ras_release_vram(struct amdgpu_device *adev,
+-		struct amdgpu_bo **bo_ptr);
+-
+ static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
+ 					size_t size, loff_t *pos)
+ {
+@@ -1305,75 +1299,6 @@ static void amdgpu_ras_do_recovery(struct work_struct *work)
+ 	atomic_set(&ras->in_recovery, 0);
+ }
+ 
+-static int amdgpu_ras_release_vram(struct amdgpu_device *adev,
+-		struct amdgpu_bo **bo_ptr)
+-{
+-	/* no need to free it actually. */
+-	amdgpu_bo_free_kernel(bo_ptr, NULL, NULL);
+-	return 0;
+-}
+-
+-/* reserve vram with size@offset */
+-static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev,
+-		uint64_t offset, uint64_t size,
+-		struct amdgpu_bo **bo_ptr)
+-{
+-	struct ttm_operation_ctx ctx = { false, false };
+-	struct amdgpu_bo_param bp;
+-	int r = 0;
+-	int i;
+-	struct amdgpu_bo *bo;
+-
+-	if (bo_ptr)
+-		*bo_ptr = NULL;
+-	memset(&bp, 0, sizeof(bp));
+-	bp.size = size;
+-	bp.byte_align = PAGE_SIZE;
+-	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
+-	bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+-		AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
+-	bp.type = ttm_bo_type_kernel;
+-	bp.resv = NULL;
+-
+-	r = amdgpu_bo_create(adev, &bp, &bo);
+-	if (r)
+-		return -EINVAL;
+-
+-	r = amdgpu_bo_reserve(bo, false);
+-	if (r)
+-		goto error_reserve;
+-
+-	offset = ALIGN(offset, PAGE_SIZE);
+-	for (i = 0; i < bo->placement.num_placement; ++i) {
+-		bo->placements[i].fpfn = offset >> PAGE_SHIFT;
+-		bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
+-	}
+-
+-	ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
+-	r = ttm_bo_mem_space(&bo->tbo, &bo->placement, &bo->tbo.mem, &ctx);
+-	if (r)
+-		goto error_pin;
+-
+-	r = amdgpu_bo_pin_restricted(bo,
+-			AMDGPU_GEM_DOMAIN_VRAM,
+-			offset,
+-			offset + size);
+-	if (r)
+-		goto error_pin;
+-
+-	if (bo_ptr)
+-		*bo_ptr = bo;
+-
+-	amdgpu_bo_unreserve(bo);
+-	return r;
+-
+-error_pin:
+-	amdgpu_bo_unreserve(bo);
+-error_reserve:
+-	amdgpu_bo_unref(&bo);
+-	return r;
+-}
+-
+ /* alloc/realloc bps array */
+ static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
+ 		struct ras_err_handler_data *data, int pages)
+@@ -1509,7 +1434,7 @@ int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
+ 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+ 	struct ras_err_handler_data *data;
+ 	uint64_t bp;
+-	struct amdgpu_bo *bo;
++	struct amdgpu_bo *bo = NULL;
+ 	int i, ret = 0;
+ 
+ 	if (!con || !con->eh_data)
+@@ -1523,12 +1448,14 @@ int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
+ 	for (i = data->last_reserved; i < data->count; i++) {
+ 		bp = data->bps[i].retired_page;
+ 
+-		if (amdgpu_ras_reserve_vram(adev, bp << PAGE_SHIFT,
+-					PAGE_SIZE, &bo))
++		if (amdgpu_bo_create_kernel_at(adev, bp << PAGE_SHIFT, PAGE_SIZE,
++					       AMDGPU_GEM_DOMAIN_VRAM,
++					       &bo, NULL))
+ 			DRM_ERROR("RAS ERROR: reserve vram %llx fail\n", bp);
+ 
+ 		data->bps_bo[i] = bo;
+ 		data->last_reserved = i + 1;
++		bo = NULL;
+ 	}
+ 
+ 	/* continue to save bad pages to eeprom even reesrve_vram fails */
+@@ -1557,7 +1484,7 @@ static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev)
+ 	for (i = data->last_reserved - 1; i >= 0; i--) {
+ 		bo = data->bps_bo[i];
+ 
+-		amdgpu_ras_release_vram(adev, &bo);
++		amdgpu_bo_free_kernel(&bo, NULL, NULL);
+ 
+ 		data->bps_bo[i] = bo;
+ 		data->last_reserved = i;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 341150b70e36..677275c1b2c3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -1792,79 +1792,22 @@ static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
+  */
+ static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
+ {
+-	struct ttm_operation_ctx ctx = { false, false };
+-	struct amdgpu_bo_param bp;
+-	int r = 0;
+-	int i;
+-	u64 vram_size = adev->gmc.visible_vram_size;
+-	u64 offset = adev->fw_vram_usage.start_offset;
+-	u64 size = adev->fw_vram_usage.size;
+-	struct amdgpu_bo *bo;
++	uint64_t vram_size = adev->gmc.visible_vram_size;
++	int r;
+ 
+-	memset(&bp, 0, sizeof(bp));
+-	bp.size = adev->fw_vram_usage.size;
+-	bp.byte_align = PAGE_SIZE;
+-	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
+-	bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+-		AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+-	bp.type = ttm_bo_type_kernel;
+-	bp.resv = NULL;
+ 	adev->fw_vram_usage.va = NULL;
+ 	adev->fw_vram_usage.reserved_bo = NULL;
+ 
+-	if (adev->fw_vram_usage.size > 0 &&
+-		adev->fw_vram_usage.size <= vram_size) {
+-
+-		r = amdgpu_bo_create(adev, &bp,
+-				     &adev->fw_vram_usage.reserved_bo);
+-		if (r)
+-			goto error_create;
+-
+-		r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
+-		if (r)
+-			goto error_reserve;
+-
+-		/* remove the original mem node and create a new one at the
+-		 * request position
+-		 */
+-		bo = adev->fw_vram_usage.reserved_bo;
+-		offset = ALIGN(offset, PAGE_SIZE);
+-		for (i = 0; i < bo->placement.num_placement; ++i) {
+-			bo->placements[i].fpfn = offset >> PAGE_SHIFT;
+-			bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
+-		}
+-
+-		ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
+-		r = ttm_bo_mem_space(&bo->tbo, &bo->placement,
+-				     &bo->tbo.mem, &ctx);
+-		if (r)
+-			goto error_pin;
+-
+-		r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
+-			AMDGPU_GEM_DOMAIN_VRAM,
+-			adev->fw_vram_usage.start_offset,
+-			(adev->fw_vram_usage.start_offset +
+-			adev->fw_vram_usage.size));
+-		if (r)
+-			goto error_pin;
+-		r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
+-			&adev->fw_vram_usage.va);
+-		if (r)
+-			goto error_kmap;
+-
+-		amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
+-	}
+-	return r;
++	if (adev->fw_vram_usage.size == 0 ||
++	    adev->fw_vram_usage.size > vram_size)
++		return 0;
+ 
+-error_kmap:
+-	amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
+-error_pin:
+-	amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
+-error_reserve:
+-	amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
+-error_create:
+-	adev->fw_vram_usage.va = NULL;
+-	adev->fw_vram_usage.reserved_bo = NULL;
++	return amdgpu_bo_create_kernel_at(adev,
++					  adev->fw_vram_usage.start_offset,
++					  adev->fw_vram_usage.size,
++					  AMDGPU_GEM_DOMAIN_VRAM,
++					  &adev->fw_vram_usage.reserved_bo,
++					  &adev->fw_vram_usage.va);
+ 	return r;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3951-drm-amdgpu-replace-DRM_ERROR-with-DRM_WARN-in-ras_re.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3951-drm-amdgpu-replace-DRM_ERROR-with-DRM_WARN-in-ras_re.patch
new file mode 100644
index 00000000..be68cc8a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3951-drm-amdgpu-replace-DRM_ERROR-with-DRM_WARN-in-ras_re.patch
@@ -0,0 +1,43 @@
+From d11fb986dce4d6c323eecece70c3622f97561a3b Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Thu, 12 Sep 2019 18:57:23 +0800
+Subject: [PATCH 3951/4256] drm/amdgpu: replace DRM_ERROR with DRM_WARN in
+ ras_reserve_bad_pages
+
+There are two cases of reserve error should be ignored:
+1) a ras bad page has been allocated (used by someone);
+2) a ras bad page has been reserved (duplicate error injection for one page);
+
+DRM_ERROR is unnecessary for the failure of bad page reserve
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 2cd94d4b3309..6e46f1afcb03 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1448,10 +1448,15 @@ int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
+ 	for (i = data->last_reserved; i < data->count; i++) {
+ 		bp = data->bps[i].retired_page;
+ 
++		/* There are two cases of reserve error should be ignored:
++		 * 1) a ras bad page has been allocated (used by someone);
++		 * 2) a ras bad page has been reserved (duplicate error injection
++		 *    for one page);
++		 */
+ 		if (amdgpu_bo_create_kernel_at(adev, bp << PAGE_SHIFT, PAGE_SIZE,
+ 					       AMDGPU_GEM_DOMAIN_VRAM,
+ 					       &bo, NULL))
+-			DRM_ERROR("RAS ERROR: reserve vram %llx fail\n", bp);
++			DRM_WARN("RAS WARN: reserve vram for retired page %llx fail\n", bp);
+ 
+ 		data->bps_bo[i] = bo;
+ 		data->last_reserved = i + 1;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3952-drm-amdgpu-ras-use-GPU-PAGE_SIZE-SHIFT-for-reserving.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3952-drm-amdgpu-ras-use-GPU-PAGE_SIZE-SHIFT-for-reserving.patch
new file mode 100644
index 00000000..56b853a8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3952-drm-amdgpu-ras-use-GPU-PAGE_SIZE-SHIFT-for-reserving.patch
@@ -0,0 +1,36 @@
+From 3108291b06ba704330302613b110b40b71538a74 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 17 Sep 2019 08:11:24 -0500
+Subject: [PATCH 3952/4256] drm/amdgpu/ras: use GPU PAGE_SIZE/SHIFT for
+ reserving pages
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We are reserving vram pages so they should be aligned to the
+GPU page size.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 6e46f1afcb03..6fc158391e92 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1453,7 +1453,8 @@ int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
+ 		 * 2) a ras bad page has been reserved (duplicate error injection
+ 		 *    for one page);
+ 		 */
+-		if (amdgpu_bo_create_kernel_at(adev, bp << PAGE_SHIFT, PAGE_SIZE,
++		if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT,
++					       AMDGPU_GPU_PAGE_SIZE,
+ 					       AMDGPU_GEM_DOMAIN_VRAM,
+ 					       &bo, NULL))
+ 			DRM_WARN("RAS WARN: reserve vram for retired page %llx fail\n", bp);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3953-drm-amdgpu-once-more-fix-amdgpu_bo_create_kernel_at.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3953-drm-amdgpu-once-more-fix-amdgpu_bo_create_kernel_at.patch
new file mode 100644
index 00000000..4333c416
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3953-drm-amdgpu-once-more-fix-amdgpu_bo_create_kernel_at.patch
@@ -0,0 +1,52 @@
+From f4e6fbe7b1d5582ca707b4f675f055e75c1185bf Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Tue, 24 Sep 2019 13:29:27 +0200
+Subject: [PATCH 3953/4256] drm/amdgpu: once more fix
+ amdgpu_bo_create_kernel_at
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+When CPU access is needed we should tell that to
+amdgpu_bo_create_reserved() or otherwise the access is denied later on.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Emily Deng <Emily.Deng@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+index b08bbecb63f2..acb0755fe724 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+@@ -390,7 +390,7 @@ int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
+ 	size = ALIGN(size, PAGE_SIZE);
+ 
+ 	r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr,
+-				      NULL, NULL);
++				      NULL, cpu_addr);
+ 	if (r)
+ 		return r;
+ 
+@@ -398,12 +398,15 @@ int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
+ 	 * Remove the original mem node and create a new one at the request
+ 	 * position.
+ 	 */
++	if (cpu_addr)
++		amdgpu_bo_kunmap(*bo_ptr);
++
++	ttm_bo_mem_put(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem);
++
+ 	for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) {
+ 		(*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT;
+ 		(*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
+ 	}
+-
+-	ttm_bo_mem_put(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem);
+ 	r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement,
+ 			     &(*bo_ptr)->tbo.mem, &ctx);
+ 	if (r)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3954-drm-amdgpu-restrict-hotplug-error-message.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3954-drm-amdgpu-restrict-hotplug-error-message.patch
new file mode 100644
index 00000000..b48e2cd9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3954-drm-amdgpu-restrict-hotplug-error-message.patch
@@ -0,0 +1,80 @@
+From ed1735eaaadc754a8b233a98b0af77dbeebeceb0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <ckoenig.leichtzumerken@gmail.com>
+Date: Thu, 19 Sep 2019 15:16:49 +0200
+Subject: [PATCH 3954/4256] drm/amdgpu: restrict hotplug error message
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We should print the error only when we are hotplugged and crash
+basically all userspace applications.
+
+Signed-off-by: Christian König <ckoenig.leichtzumerken@gmail.com>
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Emily Deng <Emily.Deng@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c     |  8 ++++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.rej | 30 ---------------------
+ 2 files changed, 6 insertions(+), 32 deletions(-)
+ delete mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.rej
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 9f7118ab1e93..82b20de92591 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1101,9 +1101,13 @@ static void
+ amdgpu_pci_remove(struct pci_dev *pdev)
+ {
+ 	struct drm_device *dev = pci_get_drvdata(pdev);
+-	
+-	DRM_ERROR("Device removal is currently not supported outside of fbcon\n");
++
++#ifdef MODULE
++        if (THIS_MODULE->state != MODULE_STATE_GOING)
++#endif
++	        DRM_ERROR("Hotplug removal is not supported\n");	
+ 	drm_dev_unplug(dev);
++	drm_dev_put(dev);
+ 	pci_disable_device(pdev);
+ 	pci_set_drvdata(pdev, NULL);
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.rej b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.rej
+deleted file mode 100644
+index 98377b949f17..000000000000
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.rej
++++ /dev/null
+@@ -1,30 +0,0 @@
+---- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+-+++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+-@@ -527,22 +527,21 @@ module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
+- MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
+- module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
+- 
+--/*
+-- * DOC: amdgpu_ras_enable (int)
+-+/**
+-+ * DOC: ras_enable (int)
+-  * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
+-  */
+--MODULE_PARM_DESC(amdgpu_ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
+-+MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
+- module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
+- 
+- /**
+-- * DOC: amdgpu_ras_mask (uint)
+-+ * DOC: ras_mask (uint)
+-  * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
+-  * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+-  */
+--MODULE_PARM_DESC(amdgpu_ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
+-+MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
+- module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
+- 
+--
+- /**
+-  * DOC: si_support (int)
+-  * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3955-drm-amd-display-prevent-memory-leak.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3955-drm-amd-display-prevent-memory-leak.patch
new file mode 100644
index 00000000..e9164b9d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3955-drm-amd-display-prevent-memory-leak.patch
@@ -0,0 +1,82 @@
+From ebdc6329d11990ac3b3a00ebcb643212a1888d2e Mon Sep 17 00:00:00 2001
+From: Navid Emamdoost <navid.emamdoost@gmail.com>
+Date: Tue, 24 Sep 2019 23:23:56 -0500
+Subject: [PATCH 3955/4256] drm/amd/display: prevent memory leak
+
+In dcn*_create_resource_pool the allocated memory should be released if
+construct pool fails.
+
+Signed-off-by: Navid Emamdoost <navid.emamdoost@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 1 +
+ drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 1 +
+ drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 1 +
+ drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 1 +
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c   | 1 +
+ 5 files changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+index 9de2a0bda38a..99c9c5e7476d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+@@ -1088,6 +1088,7 @@ struct resource_pool *dce100_create_resource_pool(
+ 	if (construct(num_virtual_links, dc, pool))
+ 		return &pool->base;
+ 
++	kfree(pool);
+ 	BREAK_TO_DEBUGGER();
+ 	return NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index dc1764f2f8c2..b35caf9fad49 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -1460,6 +1460,7 @@ struct resource_pool *dce110_create_resource_pool(
+ 	if (construct(num_virtual_links, dc, pool, asic_id))
+ 		return &pool->base;
+ 
++	kfree(pool);
+ 	BREAK_TO_DEBUGGER();
+ 	return NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+index 65f17bbdef2a..254a6452b2b3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+@@ -1340,6 +1340,7 @@ struct resource_pool *dce112_create_resource_pool(
+ 	if (construct(num_virtual_links, dc, pool))
+ 		return &pool->base;
+ 
++	kfree(pool);
+ 	BREAK_TO_DEBUGGER();
+ 	return NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index c10392bbcb38..fde60d41f865 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -1206,6 +1206,7 @@ struct resource_pool *dce120_create_resource_pool(
+ 	if (construct(num_virtual_links, dc, pool))
+ 		return &pool->base;
+ 
++	kfree(pool);
+ 	BREAK_TO_DEBUGGER();
+ 	return NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index 2fb56dbefbda..4e633f3a99d4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -1568,6 +1568,7 @@ struct resource_pool *dcn10_create_resource_pool(
+ 	if (construct(init_data->num_virtual_links, dc, pool))
+ 		return &pool->base;
+ 
++	kfree(pool);
+ 	BREAK_TO_DEBUGGER();
+ 	return NULL;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3956-Revert-drm-amd-display-dc-fix-TRANSMITTER_UNIPHY_G-o.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3956-Revert-drm-amd-display-dc-fix-TRANSMITTER_UNIPHY_G-o.patch
new file mode 100644
index 00000000..5cb51521
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3956-Revert-drm-amd-display-dc-fix-TRANSMITTER_UNIPHY_G-o.patch
@@ -0,0 +1,37 @@
+From 3dca4e05ef422e3fdd931a3befd43211b33ef128 Mon Sep 17 00:00:00 2001
+From: Chaudhary Amit Kumar <Chaudharyamit.Kumar@amd.com>
+Date: Mon, 7 Oct 2019 13:49:57 +0530
+Subject: [PATCH 3956/4256] Revert "drm/amd/display/dc: fix
+ TRANSMITTER_UNIPHY_G offset"
+
+This reverts commit 9e71cc6934e138ec33ae79dcbab960ee97600cb6.
+---
+ drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 5 +----
+ 1 file changed, 1 insertion(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+index 8e4effb1f439..86be482b6816 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -226,7 +226,7 @@ static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
+ };
+ 
+ #define link_regs(id)\
+-{\
++[id] = {\
+ 	LE_DCE80_REG_LIST(id)\
+ }
+ 
+@@ -237,9 +237,6 @@ static const struct dce110_link_enc_registers link_enc_regs[] = {
+ 	link_regs(3),
+ 	link_regs(4),
+ 	link_regs(5),
+-	link_regs(0),
+-	link_regs(0),
+-	link_regs(0),
+ 	link_regs(6),
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3957-SWDEV-202843-drm-amd-display-dc-map-TRANSMITTER_UNIP.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3957-SWDEV-202843-drm-amd-display-dc-map-TRANSMITTER_UNIP.patch
new file mode 100644
index 00000000..110f3ac3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3957-SWDEV-202843-drm-amd-display-dc-map-TRANSMITTER_UNIP.patch
@@ -0,0 +1,515 @@
+From f193f8d3319e7276dd520fcfcc21348d5cc680fe Mon Sep 17 00:00:00 2001
+From: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
+Date: Wed, 2 Oct 2019 12:36:33 +0530
+Subject: [PATCH 3957/4256] SWDEV-202843 - drm/amd/display/dc: map
+ TRANSMITTER_UNIPHY_x to LINK_REGS_x
+
+[Why]
+The enum value for TRANSMITTER_UNIPHY_G is 9. In resource dc_xx_resource
+file structure link_enc_regs[], the TRANSMITTER_UNIPHY_G registers are
+initialized at index 6. Due to this mismatch, if monitor is attached to
+port using TRANSMITTER_UNIPHY_G then the monitor blanks out.
+
+[How]
+add function map_transmitter_id_to_phy_instance() and use the function
+to map enum transmitter to link regs.
+
+Change-Id: I1475721eefeed5b802697c7b3e05d9aeaf6e38ca
+Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+---
+ .../amd/display/dc/dce100/dce100_resource.c   | 37 +++++++++++++-
+ .../amd/display/dc/dce110/dce110_resource.c   | 37 +++++++++++++-
+ .../amd/display/dc/dce112/dce112_resource.c   | 37 +++++++++++++-
+ .../amd/display/dc/dce120/dce120_resource.c   | 37 +++++++++++++-
+ .../drm/amd/display/dc/dce80/dce80_resource.c | 37 +++++++++++++-
+ .../drm/amd/display/dc/dcn10/dcn10_resource.c | 28 ++++++++++-
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 33 +++++++++++-
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 50 +++++++++++++++++++
+ 8 files changed, 289 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+index 99c9c5e7476d..e39c9a732f07 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+@@ -396,6 +396,37 @@ static const struct dc_plane_cap plane_cap = {
+ #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
+ #endif
+ 
++static int map_transmitter_id_to_phy_instance(
++	enum transmitter transmitter)
++{
++	switch (transmitter) {
++	case TRANSMITTER_UNIPHY_A:
++		return 0;
++	break;
++	case TRANSMITTER_UNIPHY_B:
++		return 1;
++	break;
++	case TRANSMITTER_UNIPHY_C:
++		return 2;
++	break;
++	case TRANSMITTER_UNIPHY_D:
++		return 3;
++	break;
++	case TRANSMITTER_UNIPHY_E:
++		return 4;
++	break;
++	case TRANSMITTER_UNIPHY_F:
++		return 5;
++	break;
++	case TRANSMITTER_UNIPHY_G:
++		return 6;
++	break;
++	default:
++		ASSERT(0);
++		return 0;
++	}
++}
++
+ static void read_dce_straps(
+ 	struct dc_context *ctx,
+ 	struct resource_straps *straps)
+@@ -568,14 +599,18 @@ struct link_encoder *dce100_link_encoder_create(
+ {
+ 	struct dce110_link_encoder *enc110 =
+ 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
++	int link_regs_id;
+ 
+ 	if (!enc110)
+ 		return NULL;
+ 
++	link_regs_id =
++		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
++
+ 	dce110_link_encoder_construct(enc110,
+ 				      enc_init_data,
+ 				      &link_enc_feature,
+-				      &link_enc_regs[enc_init_data->transmitter],
++				      &link_enc_regs[link_regs_id],
+ 				      &link_enc_aux_regs[enc_init_data->channel - 1],
+ 				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
+ 	return &enc110->base;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index b35caf9fad49..e8e018e2a67b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -438,6 +438,37 @@ static const struct dc_plane_cap underlay_plane_cap = {
+ #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
+ #endif
+ 
++static int map_transmitter_id_to_phy_instance(
++	enum transmitter transmitter)
++{
++	switch (transmitter) {
++	case TRANSMITTER_UNIPHY_A:
++		return 0;
++	break;
++	case TRANSMITTER_UNIPHY_B:
++		return 1;
++	break;
++	case TRANSMITTER_UNIPHY_C:
++		return 2;
++	break;
++	case TRANSMITTER_UNIPHY_D:
++		return 3;
++	break;
++	case TRANSMITTER_UNIPHY_E:
++		return 4;
++	break;
++	case TRANSMITTER_UNIPHY_F:
++		return 5;
++	break;
++	case TRANSMITTER_UNIPHY_G:
++		return 6;
++	break;
++	default:
++		ASSERT(0);
++		return 0;
++	}
++}
++
+ static void read_dce_straps(
+ 	struct dc_context *ctx,
+ 	struct resource_straps *straps)
+@@ -615,14 +646,18 @@ static struct link_encoder *dce110_link_encoder_create(
+ {
+ 	struct dce110_link_encoder *enc110 =
+ 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
++	int link_regs_id;
+ 
+ 	if (!enc110)
+ 		return NULL;
+ 
++	link_regs_id =
++		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
++
+ 	dce110_link_encoder_construct(enc110,
+ 				      enc_init_data,
+ 				      &link_enc_feature,
+-				      &link_enc_regs[enc_init_data->transmitter],
++				      &link_enc_regs[link_regs_id],
+ 				      &link_enc_aux_regs[enc_init_data->channel - 1],
+ 				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
+ 	return &enc110->base;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+index 254a6452b2b3..de0b3785f0d2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+@@ -415,6 +415,37 @@ static const struct dc_plane_cap plane_cap = {
+ #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
+ #endif
+ 
++static int map_transmitter_id_to_phy_instance(
++	enum transmitter transmitter)
++{
++	switch (transmitter) {
++	case TRANSMITTER_UNIPHY_A:
++		return 0;
++	break;
++	case TRANSMITTER_UNIPHY_B:
++		return 1;
++	break;
++	case TRANSMITTER_UNIPHY_C:
++		return 2;
++	break;
++	case TRANSMITTER_UNIPHY_D:
++		return 3;
++	break;
++	case TRANSMITTER_UNIPHY_E:
++		return 4;
++	break;
++	case TRANSMITTER_UNIPHY_F:
++		return 5;
++	break;
++	case TRANSMITTER_UNIPHY_G:
++		return 6;
++	break;
++	default:
++		ASSERT(0);
++		return 0;
++	}
++}
++
+ static void read_dce_straps(
+ 	struct dc_context *ctx,
+ 	struct resource_straps *straps)
+@@ -573,14 +604,18 @@ struct link_encoder *dce112_link_encoder_create(
+ {
+ 	struct dce110_link_encoder *enc110 =
+ 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
++	int link_regs_id;
+ 
+ 	if (!enc110)
+ 		return NULL;
+ 
++	link_regs_id =
++		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
++
+ 	dce110_link_encoder_construct(enc110,
+ 				      enc_init_data,
+ 				      &link_enc_feature,
+-				      &link_enc_regs[enc_init_data->transmitter],
++				      &link_enc_regs[link_regs_id],
+ 				      &link_enc_aux_regs[enc_init_data->channel - 1],
+ 				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
+ 	return &enc110->base;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index fde60d41f865..c47961549f0b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -354,6 +354,37 @@ static const struct dce_audio_mask audio_mask = {
+ 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
+ };
+ 
++static int map_transmitter_id_to_phy_instance(
++	enum transmitter transmitter)
++{
++	switch (transmitter) {
++	case TRANSMITTER_UNIPHY_A:
++		return 0;
++	break;
++	case TRANSMITTER_UNIPHY_B:
++		return 1;
++	break;
++	case TRANSMITTER_UNIPHY_C:
++		return 2;
++	break;
++	case TRANSMITTER_UNIPHY_D:
++		return 3;
++	break;
++	case TRANSMITTER_UNIPHY_E:
++		return 4;
++	break;
++	case TRANSMITTER_UNIPHY_F:
++		return 5;
++	break;
++	case TRANSMITTER_UNIPHY_G:
++		return 6;
++	break;
++	default:
++		ASSERT(0);
++		return 0;
++	}
++}
++
+ #define clk_src_regs(index, id)\
+ [index] = {\
+ 	CS_COMMON_REG_LIST_DCE_112(id),\
+@@ -652,14 +683,18 @@ static struct link_encoder *dce120_link_encoder_create(
+ {
+ 	struct dce110_link_encoder *enc110 =
+ 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
++	int link_regs_id;
+ 
+ 	if (!enc110)
+ 		return NULL;
+ 
++	link_regs_id =
++		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
++
+ 	dce110_link_encoder_construct(enc110,
+ 				      enc_init_data,
+ 				      &link_enc_feature,
+-				      &link_enc_regs[enc_init_data->transmitter],
++				      &link_enc_regs[link_regs_id],
+ 				      &link_enc_aux_regs[enc_init_data->channel - 1],
+ 				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+index 86be482b6816..ff35eff3f34b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -429,6 +429,37 @@ static const struct dce_abm_mask abm_mask = {
+ #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
+ #endif
+ 
++static int map_transmitter_id_to_phy_instance(
++	enum transmitter transmitter)
++{
++	switch (transmitter) {
++	case TRANSMITTER_UNIPHY_A:
++		return 0;
++	break;
++	case TRANSMITTER_UNIPHY_B:
++		return 1;
++	break;
++	case TRANSMITTER_UNIPHY_C:
++		return 2;
++	break;
++	case TRANSMITTER_UNIPHY_D:
++		return 3;
++	break;
++	case TRANSMITTER_UNIPHY_E:
++		return 4;
++	break;
++	case TRANSMITTER_UNIPHY_F:
++		return 5;
++	break;
++	case TRANSMITTER_UNIPHY_G:
++		return 6;
++	break;
++	default:
++		ASSERT(0);
++		return 0;
++	}
++}
++
+ static void read_dce_straps(
+ 	struct dc_context *ctx,
+ 	struct resource_straps *straps)
+@@ -667,14 +698,18 @@ struct link_encoder *dce80_link_encoder_create(
+ {
+ 	struct dce110_link_encoder *enc110 =
+ 		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
++	int link_regs_id;
+ 
+ 	if (!enc110)
+ 		return NULL;
+ 
++	link_regs_id =
++		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
++
+ 	dce110_link_encoder_construct(enc110,
+ 				      enc_init_data,
+ 				      &link_enc_feature,
+-				      &link_enc_regs[enc_init_data->transmitter],
++				      &link_enc_regs[link_regs_id],
+ 				      &link_enc_aux_regs[enc_init_data->channel - 1],
+ 				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
+ 	return &enc110->base;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index 4e633f3a99d4..eb8bc5538626 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -469,6 +469,28 @@ static const struct dcn_hubbub_mask hubbub_mask = {
+ 		HUBBUB_MASK_SH_LIST_DCN10(_MASK)
+ };
+ 
++static int map_transmitter_id_to_phy_instance(
++	enum transmitter transmitter)
++{
++	switch (transmitter) {
++	case TRANSMITTER_UNIPHY_A:
++		return 0;
++	break;
++	case TRANSMITTER_UNIPHY_B:
++		return 1;
++	break;
++	case TRANSMITTER_UNIPHY_C:
++		return 2;
++	break;
++	case TRANSMITTER_UNIPHY_D:
++		return 3;
++	break;
++	default:
++		ASSERT(0);
++		return 0;
++	}
++}
++
+ #define clk_src_regs(index, pllid)\
+ [index] = {\
+ 	CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
+@@ -749,14 +771,18 @@ struct link_encoder *dcn10_link_encoder_create(
+ {
+ 	struct dcn10_link_encoder *enc10 =
+ 		kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL);
++	int link_regs_id;
+ 
+ 	if (!enc10)
+ 		return NULL;
+ 
++	link_regs_id =
++		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
++
+ 	dcn10_link_encoder_construct(enc10,
+ 				      enc_init_data,
+ 				      &link_enc_feature,
+-				      &link_enc_regs[enc_init_data->transmitter],
++				      &link_enc_regs[link_regs_id],
+ 				      &link_enc_aux_regs[enc_init_data->channel - 1],
+ 				      &link_enc_hpd_regs[enc_init_data->hpd_source],
+ 				      &le_shift,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 8d81c65157d4..035ef83be6cf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -891,6 +891,33 @@ struct input_pixel_processor *dcn20_ipp_create(
+ 	return &ipp->base;
+ }
+ 
++static int map_transmitter_id_to_phy_instance(
++	enum transmitter transmitter)
++{
++	switch (transmitter) {
++	case TRANSMITTER_UNIPHY_A:
++		return 0;
++	break;
++	case TRANSMITTER_UNIPHY_B:
++		return 1;
++	break;
++	case TRANSMITTER_UNIPHY_C:
++		return 2;
++	break;
++	case TRANSMITTER_UNIPHY_D:
++		return 3;
++	break;
++	case TRANSMITTER_UNIPHY_E:
++		return 4;
++	break;
++	case TRANSMITTER_UNIPHY_F:
++		return 5;
++	break;
++	default:
++		ASSERT(0);
++		return 0;
++	}
++}
+ 
+ struct output_pixel_processor *dcn20_opp_create(
+ 	struct dc_context *ctx, uint32_t inst)
+@@ -1040,14 +1067,18 @@ struct link_encoder *dcn20_link_encoder_create(
+ {
+ 	struct dcn20_link_encoder *enc20 =
+ 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
++	int link_regs_id;
+ 
+ 	if (!enc20)
+ 		return NULL;
+ 
++	link_regs_id =
++		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
++
+ 	dcn20_link_encoder_construct(enc20,
+ 				      enc_init_data,
+ 				      &link_enc_feature,
+-				      &link_enc_regs[enc_init_data->transmitter],
++				      &link_enc_regs[link_regs_id],
+ 				      &link_enc_aux_regs[enc_init_data->channel - 1],
+ 				      &link_enc_hpd_regs[enc_init_data->hpd_source],
+ 				      &le_shift,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index de182185fe1f..5a6e55b7d536 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1418,6 +1418,56 @@ static const struct resource_create_funcs res_create_maximus_funcs = {
+ 	.create_hwseq = dcn21_hwseq_create,
+ };
+ 
++static int map_transmitter_id_to_phy_instance(
++        enum transmitter transmitter)
++{
++        switch (transmitter) {
++        case TRANSMITTER_UNIPHY_A:
++                return 0;
++        break;
++        case TRANSMITTER_UNIPHY_B:
++                return 1;
++        break;
++        case TRANSMITTER_UNIPHY_C:
++                return 2;
++        break;
++        case TRANSMITTER_UNIPHY_D:
++                return 3;
++        break;
++        case TRANSMITTER_UNIPHY_E:
++                return 4;
++        break;
++        default:
++                ASSERT(0);
++                return 0;
++        }
++}
++
++static struct link_encoder *dcn21_link_encoder_create(
++        const struct encoder_init_data *enc_init_data)
++{
++        struct dcn21_link_encoder *enc21 =
++                kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
++        int link_regs_id;
++
++        if (!enc21)
++                return NULL;
++
++        link_regs_id =
++                map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
++
++        dcn21_link_encoder_construct(enc21,
++                                      enc_init_data,
++                                      &link_enc_feature,
++                                      &link_enc_regs[link_regs_id],
++                                      &link_enc_aux_regs[enc_init_data->channel - 1],
++                                      &link_enc_hpd_regs[enc_init_data->hpd_source],
++                                      &le_shift,
++                                      &le_mask);
++
++        return &enc21->enc10.base;
++}
++
+ static struct resource_funcs dcn21_res_pool_funcs = {
+ 	.destroy = dcn21_destroy_resource_pool,
+ 	.link_enc_create = dcn20_link_encoder_create,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3958-drm-amdgpu-Fix-error-handling-in-amdgpu_ras_recovery.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3958-drm-amdgpu-Fix-error-handling-in-amdgpu_ras_recovery.patch
new file mode 100644
index 00000000..26c8087a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3958-drm-amdgpu-Fix-error-handling-in-amdgpu_ras_recovery.patch
@@ -0,0 +1,36 @@
+From 886b6a3216b6a7704b1370bba6506f565080315c Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Thu, 3 Oct 2019 17:54:57 -0400
+Subject: [PATCH 3958/4256] drm/amdgpu: Fix error handling in
+ amdgpu_ras_recovery_init
+
+Don't set a struct pointer to NULL before freeing its members. It's
+hard to see what's happening due to a local pointer-to-pointer data
+aliasing con->eh_data.
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Tested-by: Philip Cox <Philip.Cox@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 6fc158391e92..0581004e2ed3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1540,10 +1540,10 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
+ release:
+ 	amdgpu_ras_release_bad_pages(adev);
+ free:
+-	con->eh_data = NULL;
+ 	kfree((*data)->bps);
+ 	kfree((*data)->bps_bo);
+ 	kfree(*data);
++	con->eh_data = NULL;
+ out:
+ 	DRM_WARN("Failed to initialize ras recovery!\n");
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3959-drm-ttm-Refactor-ttm_bo_pipeline_move.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3959-drm-ttm-Refactor-ttm_bo_pipeline_move.patch
new file mode 100644
index 00000000..2d2a1ad3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3959-drm-ttm-Refactor-ttm_bo_pipeline_move.patch
@@ -0,0 +1,107 @@
+From eb9b5b91a85f2aa32a5315a86933e9647cf25f78 Mon Sep 17 00:00:00 2001
+From: Brian Welty <brian.welty@intel.com>
+Date: Fri, 16 Aug 2019 14:59:16 -0400
+Subject: [PATCH 3959/4256] drm/ttm: Refactor ttm_bo_pipeline_move
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+ttm_bo_pipeline_move needlessly duplicates code. Refactor this to
+instead call ttm_bo_move_accel_cleanup.
+
+Signed-off-by: Brian Welty <brian.welty@intel.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/ttm/ttm_bo_util.c | 64 +++----------------------------
+ 1 file changed, 5 insertions(+), 59 deletions(-)
+
+diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
+index 046a6dda690a..23fa015be34e 100644
+--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
++++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
+@@ -747,49 +747,10 @@ int ttm_bo_pipeline_move(struct ttm_buffer_object *bo,
+ {
+ 	struct ttm_bo_device *bdev = bo->bdev;
+ 	struct ttm_mem_reg *old_mem = &bo->mem;
+-
+ 	struct ttm_mem_type_manager *from = &bdev->man[old_mem->mem_type];
+-	struct ttm_mem_type_manager *to = &bdev->man[new_mem->mem_type];
+-
+-	int ret;
+-
+-	reservation_object_add_excl_fence(bo->resv, fence);
+-
+-	if (!evict) {
+-		struct ttm_buffer_object *ghost_obj;
+-
+-		/**
+-		 * This should help pipeline ordinary buffer moves.
+-		 *
+-		 * Hang old buffer memory on a new buffer object,
+-		 * and leave it to be released when the GPU
+-		 * operation has completed.
+-		 */
+-
+-		dma_fence_put(bo->moving);
+-		bo->moving = dma_fence_get(fence);
+ 
+-		ret = ttm_buffer_object_transfer(bo, &ghost_obj);
+-		if (ret)
+-			return ret;
+-
+-		reservation_object_add_excl_fence(ghost_obj->resv, fence);
+-
+-		/**
+-		 * If we're not moving to fixed memory, the TTM object
+-		 * needs to stay alive. Otherwhise hang it on the ghost
+-		 * bo to be unbound and destroyed.
+-		 */
+-
+-		if (!(to->flags & TTM_MEMTYPE_FLAG_FIXED))
+-			ghost_obj->ttm = NULL;
+-		else
+-			bo->ttm = NULL;
+-
+-		ttm_bo_unreserve(ghost_obj);
+-		ttm_bo_put(ghost_obj);
+-
+-	} else if (from->flags & TTM_MEMTYPE_FLAG_FIXED) {
++	if (evict && from->flags & TTM_MEMTYPE_FLAG_FIXED) {
++		reservation_object_add_excl_fence(bo->resv, fence);
+ 
+ 		/**
+ 		 * BO doesn't have a TTM we need to bind/unbind. Just remember
+@@ -808,27 +769,12 @@ int ttm_bo_pipeline_move(struct ttm_buffer_object *bo,
+ 		dma_fence_put(bo->moving);
+ 		bo->moving = dma_fence_get(fence);
+ 
++		*old_mem = *new_mem;
++		new_mem->mm_node = NULL;
+ 	} else {
+-		/**
+-		 * Last resort, wait for the move to be completed.
+-		 *
+-		 * Should never happen in pratice.
+-		 */
+-
+-		ret = ttm_bo_wait(bo, false, false);
+-		if (ret)
+-			return ret;
+-
+-		if (to->flags & TTM_MEMTYPE_FLAG_FIXED) {
+-			ttm_tt_destroy(bo->ttm);
+-			bo->ttm = NULL;
+-		}
+-		ttm_bo_free_old_node(bo);
++		return ttm_bo_move_accel_cleanup(bo, fence, evict, new_mem);
+ 	}
+ 
+-	*old_mem = *new_mem;
+-	new_mem->mm_node = NULL;
+-
+ 	return 0;
+ }
+ EXPORT_SYMBOL(ttm_bo_pipeline_move);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3960-drm-ttm-Restore-ttm-prefaulting.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3960-drm-ttm-Restore-ttm-prefaulting.patch
new file mode 100644
index 00000000..f347067a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3960-drm-ttm-Restore-ttm-prefaulting.patch
@@ -0,0 +1,56 @@
+From 45d7aafd61f363dce97c72991ffde801dfa72374 Mon Sep 17 00:00:00 2001
+From: Thomas Hellstrom <thellstrom@vmware.com>
+Date: Thu, 12 Sep 2019 20:38:54 +0200
+Subject: [PATCH 3960/4256] drm/ttm: Restore ttm prefaulting
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Commit 4daa4fba3a38 ("gpu: drm: ttm: Adding new return type vm_fault_t")
+broke TTM prefaulting. Since vmf_insert_mixed() typically always returns
+VM_FAULT_NOPAGE, prefaulting stops after the second PTE.
+
+Restore (almost) the original behaviour. Unfortunately we can no longer
+with the new vm_fault_t return type determine whether a prefaulting
+PTE insertion hit an already populated PTE, and terminate the insertion
+loop. Instead we continue with the pre-determined number of prefaults.
+
+Fixes: 4daa4fba3a38 ("gpu: drm: ttm: Adding new return type vm_fault_t")
+Cc: Souptick Joarder <jrdr.linux@gmail.com>
+Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Cc: stable@vger.kernel.org # v4.19+
+---
+ drivers/gpu/drm/ttm/ttm_bo_vm.c | 16 +++++++---------
+ 1 file changed, 7 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c
+index f1114a6e6b1e..41ae5200ac5c 100644
+--- a/drivers/gpu/drm/ttm/ttm_bo_vm.c
++++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c
+@@ -273,15 +273,13 @@ static vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf)
+ 		else
+ 			ret = vmf_insert_pfn(&cvma, address, pfn);
+ 
+-		/*
+-		 * Somebody beat us to this PTE or prefaulting to
+-		 * an already populated PTE, or prefaulting error.
+-		 */
+-
+-		if (unlikely((ret == VM_FAULT_NOPAGE && i > 0)))
+-			break;
+-		else if (unlikely(ret & VM_FAULT_ERROR))
+-			goto out_io_unlock;
++		/* Never error on prefaulted PTEs */
++		if (unlikely((ret & VM_FAULT_ERROR))) {
++			if (i == 0)
++				goto out_io_unlock;
++			else
++				break;
++		}
+ 
+ 		address += PAGE_SIZE;
+ 		if (unlikely(++page_offset >= page_last))
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3961-drm-ttm-Remove-explicit-typecasts-of-vm_private_data.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3961-drm-ttm-Remove-explicit-typecasts-of-vm_private_data.patch
new file mode 100644
index 00000000..5c2de532
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3961-drm-ttm-Remove-explicit-typecasts-of-vm_private_data.patch
@@ -0,0 +1,54 @@
+From 5d719ac7b063e7ac090b0394bd6b9dbb551b07e1 Mon Sep 17 00:00:00 2001
+From: Thomas Hellstrom <thellstrom@vmware.com>
+Date: Wed, 25 Sep 2019 15:11:22 +0200
+Subject: [PATCH 3961/4256] drm/ttm: Remove explicit typecasts of
+ vm_private_data
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The explicit typcasts are meaningless, so remove them.
+
+Suggested-by: Matthew Wilcox <willy@infradead.org>
+Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/ttm/ttm_bo_vm.c | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c
+index 41ae5200ac5c..26defaaa1f81 100644
+--- a/drivers/gpu/drm/ttm/ttm_bo_vm.c
++++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c
+@@ -109,8 +109,7 @@ static unsigned long ttm_bo_io_mem_pfn(struct ttm_buffer_object *bo,
+ static vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf)
+ {
+ 	struct vm_area_struct *vma = vmf->vma;
+-	struct ttm_buffer_object *bo = (struct ttm_buffer_object *)
+-	    vma->vm_private_data;
++	struct ttm_buffer_object *bo = vma->vm_private_data;
+ 	struct ttm_bo_device *bdev = bo->bdev;
+ 	unsigned long page_offset;
+ 	unsigned long page_last;
+@@ -295,8 +294,7 @@ static vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf)
+ 
+ static void ttm_bo_vm_open(struct vm_area_struct *vma)
+ {
+-	struct ttm_buffer_object *bo =
+-	    (struct ttm_buffer_object *)vma->vm_private_data;
++	struct ttm_buffer_object *bo = vma->vm_private_data;
+ 
+ 	WARN_ON(bo->bdev->dev_mapping != vma->vm_file->f_mapping);
+ 
+@@ -305,7 +303,7 @@ static void ttm_bo_vm_open(struct vm_area_struct *vma)
+ 
+ static void ttm_bo_vm_close(struct vm_area_struct *vma)
+ {
+-	struct ttm_buffer_object *bo = (struct ttm_buffer_object *)vma->vm_private_data;
++	struct ttm_buffer_object *bo = vma->vm_private_data;
+ 
+ 	ttm_bo_put(bo);
+ 	vma->vm_private_data = NULL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3962-drm-amdkfd-Add-NAVI12-support-from-kfd-side.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3962-drm-amdkfd-Add-NAVI12-support-from-kfd-side.patch
new file mode 100644
index 00000000..3551f9fe
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3962-drm-amdkfd-Add-NAVI12-support-from-kfd-side.patch
@@ -0,0 +1,54 @@
+From 378f6920c78752d620c3629d9ea4918c633e3bef Mon Sep 17 00:00:00 2001
+From: shaoyunl <shaoyun.liu@amd.com>
+Date: Tue, 24 Sep 2019 18:11:12 -0400
+Subject: [PATCH 3962/4256] drm/amdkfd: Add NAVI12 support from kfd side
+
+Add device info for both navi12 PF and VF
+
+Change-Id: Ifb4035e65c12d153fc30e593fe109f9c7e0541f4
+Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index a4ea2fdb1646..43c4456b8620 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -387,6 +387,24 @@ static const struct kfd_device_info navi10_device_info = {
+ 	.num_sdma_queues_per_engine = 8,
+ };
+ 
++static const struct kfd_device_info navi12_device_info = {
++	.asic_family = CHIP_NAVI10,
++	.asic_name = "navi12",
++	.max_pasid_bits = 16,
++	.max_no_of_hqd  = 24,
++	.doorbell_size  = 8,
++	.ih_ring_entry_size = 8 * sizeof(uint32_t),
++	.event_interrupt_class = &event_interrupt_class_v9,
++	.num_of_watch_points = 4,
++	.mqd_size_aligned = MQD_SIZE_ALIGNED,
++	.needs_iommu_device = false,
++	.supports_cwsr = true,
++	.needs_pci_atomics = false,
++	.num_sdma_engines = 2,
++	.num_xgmi_sdma_engines = 0,
++	.num_sdma_queues_per_engine = 8,
++};
++
+ static const struct kfd_device_info navi14_device_info = {
+ 	.asic_family = CHIP_NAVI14,
+ 	.asic_name = "navi14",
+@@ -425,6 +443,7 @@ static const struct kfd_device_info *kfd_supported_devices[][2] = {
+ 	[CHIP_RENOIR] = {&renoir_device_info, NULL},
+ 	[CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info},
+ 	[CHIP_NAVI10] = {&navi10_device_info, NULL},
++	[CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info},
+ 	[CHIP_NAVI14] = {&navi14_device_info, NULL},
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3963-drm-kms-Duct-tape-for-mode-object-lifetime-checks.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3963-drm-kms-Duct-tape-for-mode-object-lifetime-checks.patch
new file mode 100644
index 00000000..7bbf914d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3963-drm-kms-Duct-tape-for-mode-object-lifetime-checks.patch
@@ -0,0 +1,82 @@
+From a63c863e6d1fac6e8e93f3a72df649cd5655e6e3 Mon Sep 17 00:00:00 2001
+From: Daniel Vetter <daniel.vetter@ffwll.ch>
+Date: Tue, 17 Sep 2019 14:09:35 +0200
+Subject: [PATCH 3963/4256] drm/kms: Duct-tape for mode object lifetime checks
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+commit 4f5368b5541a902f6596558b05f5c21a9770dd32
+Author: Daniel Vetter <daniel.vetter@ffwll.ch>
+Date:   Fri Jun 14 08:17:23 2019 +0200
+
+    drm/kms: Catch mode_object lifetime errors
+
+uncovered a bit a mess in dp drivers. Most drivers (from a quick look,
+all except i915) register all the dp stuff in their init code, which
+is too early. With CONFIG_DRM_DP_AUX_CHARDEV this will blow up,
+because drm_dp_aux_register tries to add a child to a device in sysfs
+(the connector) which doesn't even exist yet.
+
+No one seems to have cared thus far. But with the above change I also
+moved the setting of dev->registered after the ->load callback, in an
+attempt to keep old drivers from hitting any WARN_ON backtraces. But
+that moved radeon.ko from the "working, by accident" to "now also
+broken" category.
+
+Since this is a huge mess I figured a revert would be simplest. But
+this check has already caught issues in i915:
+
+commit 1b9bd09630d4db4827cc04d358a41a16a6bc2cb0
+Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Date:   Tue Aug 20 19:16:57 2019 +0300
+
+    drm/i915: Do not create a new max_bpc prop for MST connectors
+
+Hence I'd like to retain it. Fix the radeon regression by moving the
+setting of dev->registered back to were it was, and stop the
+backtraces with an explicit check for dev->driver->load.
+
+Everyone else will stay as broken with CONFIG_DRM_DP_AUX_CHARDEV. The
+next patch will improve the kerneldoc and add a todo entry for this.
+
+Fixes: 4f5368b5541a ("drm/kms: Catch mode_object lifetime errors")
+Cc: Sean Paul <sean@poorly.run>
+Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
+Reported-by: Michel Dänzer <michel@daenzer.net>
+Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
+Tested-by: Michel Dänzer <mdaenzer@redhat.com>
+Cc: Michel Dänzer <michel@daenzer.net>
+Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190917120936.7501-1-daniel.vetter@ffwll.ch
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+---
+ drivers/gpu/drm/drm_mode_object.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/drm_mode_object.c b/drivers/gpu/drm/drm_mode_object.c
+index fcb0ab0abb75..126750583415 100644
+--- a/drivers/gpu/drm/drm_mode_object.c
++++ b/drivers/gpu/drm/drm_mode_object.c
+@@ -37,6 +37,8 @@ int __drm_mode_object_add(struct drm_device *dev, struct drm_mode_object *obj,
+ {
+ 	int ret;
+ 
++	WARN_ON(!dev->driver->load && dev->registered && !obj_free_cb);
++
+ 	mutex_lock(&dev->mode_config.idr_mutex);
+ 	ret = idr_alloc(&dev->mode_config.crtc_idr, register_obj ? obj : NULL, 1, 0, GFP_KERNEL);
+ 	if (ret >= 0) {
+@@ -96,6 +98,8 @@ void drm_mode_object_register(struct drm_device *dev,
+ void drm_mode_object_unregister(struct drm_device *dev,
+ 				struct drm_mode_object *object)
+ {
++	WARN_ON(!dev->driver->load && dev->registered && !object->free_cb);
++
+ 	mutex_lock(&dev->mode_config.idr_mutex);
+ 	if (object->id) {
+ 		idr_remove(&dev->mode_config.crtc_idr, object->id);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3964-drm-amdkfd-Delete-useless-SDMA-register-setting-on-n.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3964-drm-amdkfd-Delete-useless-SDMA-register-setting-on-n.patch
new file mode 100644
index 00000000..d878629a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3964-drm-amdkfd-Delete-useless-SDMA-register-setting-on-n.patch
@@ -0,0 +1,199 @@
+From 35cdf912c427cf87744feab42a5e89cc77ccf6f1 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Sat, 21 Sep 2019 20:02:57 -0400
+Subject: [PATCH 3964/4256] drm/amdkfd: Delete useless SDMA register setting on
+ non HWS path
+
+HW folks have confirm that we should not touch RESUME_CTX of
+SDMA*_GFX_CONTEXT_CNTL when manipulating RLC queues.
+
+Change-Id: I2c142d024e94f92194b1cb9feb7f44396b8f3ecc
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c   | 34 +------------------
+ .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c    |  9 +----
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 11 ------
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 11 ------
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c |  9 +----
+ 5 files changed, 3 insertions(+), 71 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+index ce0ceb71ef35..a3382af6a89f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+@@ -102,38 +102,12 @@ static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
+ 	return retval;
+ }
+ 
+-static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
+-		u32 instance, u32 offset)
+-{
+-	switch (instance) {
+-	case 0:
+-		return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
+-	case 1:
+-		return (adev->reg_offset[SDMA1_HWIP][0][1] + offset);
+-	case 2:
+-		return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
+-	case 3:
+-		return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
+-	case 4:
+-		return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
+-	case 5:
+-		return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
+-	case 6:
+-		return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
+-	case 7:
+-		return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
+-	default:
+-		break;
+-	}
+-	return 0;
+-}
+-
+ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 			     uint32_t __user *wptr, struct mm_struct *mm)
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 	struct v9_sdma_mqd *m;
+-	uint32_t sdma_base_addr, sdmax_gfx_context_cntl;
++	uint32_t sdma_base_addr;
+ 	unsigned long end_jiffies;
+ 	uint32_t data;
+ 	uint64_t data64;
+@@ -142,8 +116,6 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 	m = get_sdma_mqd(mqd);
+ 	sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
+ 					    m->sdma_queue_id);
+-	sdmax_gfx_context_cntl = sdma_v4_0_get_reg_offset(adev,
+-			m->sdma_engine_id, mmSDMA0_GFX_CONTEXT_CNTL);
+ 
+ 	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+ 		m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
+@@ -159,10 +131,6 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 		}
+ 		usleep_range(500, 1000);
+ 	}
+-	data = RREG32(sdmax_gfx_context_cntl);
+-	data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
+-			     RESUME_CTX, 0);
+-	WREG32(sdmax_gfx_context_cntl, data);
+ 
+ 	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
+ 	       m->sdmax_rlcx_doorbell_offset);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+index ae0862b05dd3..0ebca783753f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+@@ -490,7 +490,7 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 	struct v10_sdma_mqd *m;
+-	uint32_t sdma_base_addr, sdmax_gfx_context_cntl;
++	uint32_t sdma_base_addr;
+ 	unsigned long end_jiffies;
+ 	uint32_t data;
+ 	uint64_t data64;
+@@ -500,9 +500,6 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 	sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
+ 					    m->sdma_queue_id);
+ 	pr_debug("sdma load base addr %x for engine %d, queue %d\n", sdma_base_addr, m->sdma_engine_id, m->sdma_queue_id);
+-	sdmax_gfx_context_cntl = m->sdma_engine_id ?
+-		SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_CONTEXT_CNTL) :
+-		SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_CONTEXT_CNTL);
+ 
+ 	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+ 		m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
+@@ -518,10 +515,6 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 		}
+ 		usleep_range(500, 1000);
+ 	}
+-	data = RREG32(sdmax_gfx_context_cntl);
+-	data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
+-			     RESUME_CTX, 0);
+-	WREG32(sdmax_gfx_context_cntl, data);
+ 
+ 	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
+ 	       m->sdmax_rlcx_doorbell_offset);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+index 7eedb5c9fd1d..ccbb1adbcb55 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+@@ -435,17 +435,6 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 		}
+ 		usleep_range(500, 1000);
+ 	}
+-	if (m->sdma_engine_id) {
+-		data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
+-		data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
+-				RESUME_CTX, 0);
+-		WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
+-	} else {
+-		data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
+-		data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
+-				RESUME_CTX, 0);
+-		WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
+-	}
+ 
+ 	data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,
+ 			     ENABLE, 1);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+index fafb42175656..dc72a4242e7e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+@@ -427,17 +427,6 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 		}
+ 		usleep_range(500, 1000);
+ 	}
+-	if (m->sdma_engine_id) {
+-		data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
+-		data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
+-				RESUME_CTX, 0);
+-		WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
+-	} else {
+-		data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
+-		data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
+-				RESUME_CTX, 0);
+-		WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
+-	}
+ 
+ 	data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
+ 			     ENABLE, 1);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+index 58f82da00e6d..10d500507501 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+@@ -406,7 +406,7 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 	struct v9_sdma_mqd *m;
+-	uint32_t sdma_base_addr, sdmax_gfx_context_cntl;
++	uint32_t sdma_base_addr;
+ 	unsigned long end_jiffies;
+ 	uint32_t data;
+ 	uint64_t data64;
+@@ -415,9 +415,6 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 	m = get_sdma_mqd(mqd);
+ 	sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
+ 					    m->sdma_queue_id);
+-	sdmax_gfx_context_cntl = m->sdma_engine_id ?
+-		SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_CONTEXT_CNTL) :
+-		SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_CONTEXT_CNTL);
+ 
+ 	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+ 		m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
+@@ -433,10 +430,6 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 		}
+ 		usleep_range(500, 1000);
+ 	}
+-	data = RREG32(sdmax_gfx_context_cntl);
+-	data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
+-			     RESUME_CTX, 0);
+-	WREG32(sdmax_gfx_context_cntl, data);
+ 
+ 	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
+ 	       m->sdmax_rlcx_doorbell_offset);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3965-drm-amdkfd-Use-better-name-for-sdma-queue-non-HWS-pa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3965-drm-amdkfd-Use-better-name-for-sdma-queue-non-HWS-pa.patch
new file mode 100644
index 00000000..786153f9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3965-drm-amdkfd-Use-better-name-for-sdma-queue-non-HWS-pa.patch
@@ -0,0 +1,957 @@
+From 80f585f9389df7f2caaa6857d669d83998a60106 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Sat, 21 Sep 2019 17:46:03 -0400
+Subject: [PATCH 3965/4256] drm/amdkfd: Use better name for sdma queue non HWS
+ path
+
+The old name is prone to confusion. The register offset is for a RLC queue
+rather than a SDMA engine. The value is not a base address, but a
+register offset.
+
+Change-Id: I55fb835f2105392344b1c17323bb55c03f927836
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c   | 88 +++++++++---------
+ .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c    | 92 +++++++++----------
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 59 ++++++------
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 59 ++++++------
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 89 +++++++++---------
+ 5 files changed, 197 insertions(+), 190 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+index a3382af6a89f..75a351739168 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+@@ -70,11 +70,11 @@ static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd)
+ 	return (struct v9_sdma_mqd *)mqd;
+ }
+ 
+-static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
++static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
+ 				unsigned int engine_id,
+ 				unsigned int queue_id)
+ {
+-	uint32_t base[8] = {
++	uint32_t sdma_engine_reg_base[8] = {
+ 		SOC15_REG_OFFSET(SDMA0, 0,
+ 				 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
+ 		SOC15_REG_OFFSET(SDMA1, 0,
+@@ -92,12 +92,12 @@ static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
+ 		SOC15_REG_OFFSET(SDMA7, 0,
+ 				 mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL
+ 	};
+-	uint32_t retval;
+ 
+-	retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL -
+-					       mmSDMA0_RLC0_RB_CNTL);
++	uint32_t retval = sdma_engine_reg_base[engine_id]
++		+ queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
+ 
+-	pr_debug("sdma base address: 0x%x\n", retval);
++	pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
++			queue_id, retval);
+ 
+ 	return retval;
+ }
+@@ -107,22 +107,22 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 	struct v9_sdma_mqd *m;
+-	uint32_t sdma_base_addr;
++	uint32_t sdma_rlc_reg_offset;
+ 	unsigned long end_jiffies;
+ 	uint32_t data;
+ 	uint64_t data64;
+ 	uint64_t __user *wptr64 = (uint64_t __user *)wptr;
+ 
+ 	m = get_sdma_mqd(mqd);
+-	sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
++	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
+ 					    m->sdma_queue_id);
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
+ 		m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
+ 
+ 	end_jiffies = msecs_to_jiffies(2000) + jiffies;
+ 	while (true) {
+-		data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
++		data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+ 		if (time_after(jiffies, end_jiffies)) {
+@@ -132,41 +132,42 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 		usleep_range(500, 1000);
+ 	}
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
+ 	       m->sdmax_rlcx_doorbell_offset);
+ 
+ 	data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
+ 			     ENABLE, 1);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
++				m->sdmax_rlcx_rb_rptr);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
+ 				m->sdmax_rlcx_rb_rptr_hi);
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
+ 	if (read_user_wptr(mm, wptr64, data64)) {
+-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
++		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
+ 		       lower_32_bits(data64));
+-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
++		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
+ 		       upper_32_bits(data64));
+ 	} else {
+-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
++		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
+ 		       m->sdmax_rlcx_rb_rptr);
+-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
++		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
+ 		       m->sdmax_rlcx_rb_rptr_hi);
+ 	}
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
+ 			m->sdmax_rlcx_rb_base_hi);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
+ 			m->sdmax_rlcx_rb_rptr_addr_lo);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
+ 			m->sdmax_rlcx_rb_rptr_addr_hi);
+ 
+ 	data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
+ 			     RB_ENABLE, 1);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
+ 
+ 	return 0;
+ }
+@@ -176,7 +177,8 @@ static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
+ 			     uint32_t (**dump)[2], uint32_t *n_regs)
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+-	uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id);
++	uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
++			engine_id, queue_id);
+ 	uint32_t i = 0, reg;
+ #undef HQD_N_REGS
+ #define HQD_N_REGS (19+6+7+10)
+@@ -186,15 +188,15 @@ static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
+ 		return -ENOMEM;
+ 
+ 	for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
+-		DUMP_REG(sdma_base_addr + reg);
++		DUMP_REG(sdma_rlc_reg_offset + reg);
+ 	for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
+-		DUMP_REG(sdma_base_addr + reg);
++		DUMP_REG(sdma_rlc_reg_offset + reg);
+ 	for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
+ 	     reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
+-		DUMP_REG(sdma_base_addr + reg);
++		DUMP_REG(sdma_rlc_reg_offset + reg);
+ 	for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
+ 	     reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
+-		DUMP_REG(sdma_base_addr + reg);
++		DUMP_REG(sdma_rlc_reg_offset + reg);
+ 
+ 	WARN_ON_ONCE(i != HQD_N_REGS);
+ 	*n_regs = i;
+@@ -206,14 +208,14 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 	struct v9_sdma_mqd *m;
+-	uint32_t sdma_base_addr;
++	uint32_t sdma_rlc_reg_offset;
+ 	uint32_t sdma_rlc_rb_cntl;
+ 
+ 	m = get_sdma_mqd(mqd);
+-	sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
++	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
+ 					    m->sdma_queue_id);
+ 
+-	sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
++	sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
+ 
+ 	if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
+ 		return true;
+@@ -226,20 +228,20 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 	struct v9_sdma_mqd *m;
+-	uint32_t sdma_base_addr;
++	uint32_t sdma_rlc_reg_offset;
+ 	uint32_t temp;
+ 	unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
+ 
+ 	m = get_sdma_mqd(mqd);
+-	sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
++	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
+ 					    m->sdma_queue_id);
+ 
+-	temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
++	temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
+ 	temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
+ 
+ 	while (true) {
+-		temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
++		temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+ 		if (time_after(jiffies, end_jiffies)) {
+@@ -249,14 +251,14 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ 		usleep_range(500, 1000);
+ 	}
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+-		RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
++		RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
+ 		SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
+ 
+-	m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
++	m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
+ 	m->sdmax_rlcx_rb_rptr_hi =
+-		RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI);
++		RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+index 0ebca783753f..3ccaa088cafe 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+@@ -308,11 +308,11 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
+ 	return 0;
+ }
+ 
+-static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
++static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
+ 				unsigned int engine_id,
+ 				unsigned int queue_id)
+ {
+-	uint32_t base[2] = {
++	uint32_t sdma_engine_reg_base[2] = {
+ 		SOC15_REG_OFFSET(SDMA0, 0,
+ 				 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
+ 		/* On gfx10, mmSDMA1_xxx registers are defined NOT based
+@@ -324,12 +324,12 @@ static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
+ 		SOC15_REG_OFFSET(SDMA1, 0,
+ 				 mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL
+ 	};
+-	uint32_t retval;
+ 
+-	retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL -
+-					       mmSDMA0_RLC0_RB_CNTL);
++	uint32_t retval = sdma_engine_reg_base[engine_id]
++		+ queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
+ 
+-	pr_debug("sdma base address: 0x%x\n", retval);
++	pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
++			queue_id, retval);
+ 
+ 	return retval;
+ }
+@@ -490,23 +490,22 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 	struct v10_sdma_mqd *m;
+-	uint32_t sdma_base_addr;
++	uint32_t sdma_rlc_reg_offset;
+ 	unsigned long end_jiffies;
+ 	uint32_t data;
+ 	uint64_t data64;
+ 	uint64_t __user *wptr64 = (uint64_t __user *)wptr;
+ 
+ 	m = get_sdma_mqd(mqd);
+-	sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
++	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
+ 					    m->sdma_queue_id);
+-	pr_debug("sdma load base addr %x for engine %d, queue %d\n", sdma_base_addr, m->sdma_engine_id, m->sdma_queue_id);
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
+ 		m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
+ 
+ 	end_jiffies = msecs_to_jiffies(2000) + jiffies;
+ 	while (true) {
+-		data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
++		data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+ 		if (time_after(jiffies, end_jiffies)) {
+@@ -516,41 +515,42 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 		usleep_range(500, 1000);
+ 	}
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
+ 	       m->sdmax_rlcx_doorbell_offset);
+ 
+ 	data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
+ 			     ENABLE, 1);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
++				m->sdmax_rlcx_rb_rptr);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
+ 				m->sdmax_rlcx_rb_rptr_hi);
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
+ 	if (read_user_wptr(mm, wptr64, data64)) {
+-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
++		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
+ 		       lower_32_bits(data64));
+-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
++		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
+ 		       upper_32_bits(data64));
+ 	} else {
+-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
++		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
+ 		       m->sdmax_rlcx_rb_rptr);
+-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
++		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
+ 		       m->sdmax_rlcx_rb_rptr_hi);
+ 	}
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
+ 			m->sdmax_rlcx_rb_base_hi);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
+ 			m->sdmax_rlcx_rb_rptr_addr_lo);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
+ 			m->sdmax_rlcx_rb_rptr_addr_hi);
+ 
+ 	data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
+ 			     RB_ENABLE, 1);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
+ 
+ 	return 0;
+ }
+@@ -560,28 +560,26 @@ static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
+ 			     uint32_t (**dump)[2], uint32_t *n_regs)
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+-	uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id);
++	uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
++			engine_id, queue_id);
+ 	uint32_t i = 0, reg;
+ #undef HQD_N_REGS
+ #define HQD_N_REGS (19+6+7+10)
+ 
+-	pr_debug("sdma dump engine id %d queue_id %d\n", engine_id, queue_id);
+-	pr_debug("sdma base addr %x\n", sdma_base_addr);
+-
+ 	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
+ 	if (*dump == NULL)
+ 		return -ENOMEM;
+ 
+ 	for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
+-		DUMP_REG(sdma_base_addr + reg);
++		DUMP_REG(sdma_rlc_reg_offset + reg);
+ 	for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
+-		DUMP_REG(sdma_base_addr + reg);
++		DUMP_REG(sdma_rlc_reg_offset + reg);
+ 	for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
+ 	     reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
+-		DUMP_REG(sdma_base_addr + reg);
++		DUMP_REG(sdma_rlc_reg_offset + reg);
+ 	for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
+ 	     reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
+-		DUMP_REG(sdma_base_addr + reg);
++		DUMP_REG(sdma_rlc_reg_offset + reg);
+ 
+ 	WARN_ON_ONCE(i != HQD_N_REGS);
+ 	*n_regs = i;
+@@ -615,14 +613,14 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 	struct v10_sdma_mqd *m;
+-	uint32_t sdma_base_addr;
++	uint32_t sdma_rlc_reg_offset;
+ 	uint32_t sdma_rlc_rb_cntl;
+ 
+ 	m = get_sdma_mqd(mqd);
+-	sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
++	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
+ 					    m->sdma_queue_id);
+ 
+-	sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
++	sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
+ 
+ 	if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
+ 		return true;
+@@ -743,20 +741,20 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 	struct v10_sdma_mqd *m;
+-	uint32_t sdma_base_addr;
++	uint32_t sdma_rlc_reg_offset;
+ 	uint32_t temp;
+ 	unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
+ 
+ 	m = get_sdma_mqd(mqd);
+-	sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
++	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
+ 					    m->sdma_queue_id);
+ 
+-	temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
++	temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
+ 	temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
+ 
+ 	while (true) {
+-		temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
++		temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+ 		if (time_after(jiffies, end_jiffies)) {
+@@ -766,14 +764,14 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ 		usleep_range(500, 1000);
+ 	}
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+-		RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
++		RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
+ 		SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
+ 
+-	m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
++	m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
+ 	m->sdmax_rlcx_rb_rptr_hi =
+-		RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI);
++		RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+index ccbb1adbcb55..dd7548e9932b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+@@ -306,13 +306,15 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
+ 	return 0;
+ }
+ 
+-static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
++static inline uint32_t get_sdma_rlc_reg_offset(struct cik_sdma_rlc_registers *m)
+ {
+ 	uint32_t retval;
+ 
+ 	retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
+ 			m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
+-	pr_debug("sdma base address: 0x%x\n", retval);
++
++	pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n",
++			m->sdma_engine_id, m->sdma_queue_id, retval);
+ 
+ 	return retval;
+ }
+@@ -415,18 +417,18 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 	struct cik_sdma_rlc_registers *m;
+ 	unsigned long end_jiffies;
+-	uint32_t sdma_base_addr;
++	uint32_t sdma_rlc_reg_offset;
+ 	uint32_t data;
+ 
+ 	m = get_sdma_mqd(mqd);
+-	sdma_base_addr = get_sdma_base_addr(m);
++	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
+ 		m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
+ 
+ 	end_jiffies = msecs_to_jiffies(2000) + jiffies;
+ 	while (true) {
+-		data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
++		data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+ 		if (time_after(jiffies, end_jiffies)) {
+@@ -438,28 +440,29 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 
+ 	data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,
+ 			     ENABLE, 1);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdma_rlc_rb_rptr);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
++				m->sdma_rlc_rb_rptr);
+ 
+ 	if (read_user_wptr(mm, wptr, data))
+-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
++		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data);
+ 	else
+-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
++		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
+ 		       m->sdma_rlc_rb_rptr);
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR,
+ 				m->sdma_rlc_virtual_addr);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
+ 			m->sdma_rlc_rb_base_hi);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
+ 			m->sdma_rlc_rb_rptr_addr_lo);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
+ 			m->sdma_rlc_rb_rptr_addr_hi);
+ 
+ 	data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL,
+ 			     RB_ENABLE, 1);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
+ 
+ 	return 0;
+ }
+@@ -517,13 +520,13 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 	struct cik_sdma_rlc_registers *m;
+-	uint32_t sdma_base_addr;
++	uint32_t sdma_rlc_reg_offset;
+ 	uint32_t sdma_rlc_rb_cntl;
+ 
+ 	m = get_sdma_mqd(mqd);
+-	sdma_base_addr = get_sdma_base_addr(m);
++	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
+ 
+-	sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
++	sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
+ 
+ 	if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
+ 		return true;
+@@ -638,19 +641,19 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 	struct cik_sdma_rlc_registers *m;
+-	uint32_t sdma_base_addr;
++	uint32_t sdma_rlc_reg_offset;
+ 	uint32_t temp;
+ 	unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
+ 
+ 	m = get_sdma_mqd(mqd);
+-	sdma_base_addr = get_sdma_base_addr(m);
++	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
+ 
+-	temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
++	temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
+ 	temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
+ 
+ 	while (true) {
+-		temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
++		temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+ 		if (time_after(jiffies, end_jiffies)) {
+@@ -660,12 +663,12 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ 		usleep_range(500, 1000);
+ 	}
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+-		RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
++		RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
+ 		SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
+ 
+-	m->sdma_rlc_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
++	m->sdma_rlc_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+index dc72a4242e7e..f12ac78707b4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+@@ -270,13 +270,15 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
+ 	return 0;
+ }
+ 
+-static inline uint32_t get_sdma_base_addr(struct vi_sdma_mqd *m)
++static inline uint32_t get_sdma_rlc_reg_offset(struct vi_sdma_mqd *m)
+ {
+ 	uint32_t retval;
+ 
+ 	retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
+ 		m->sdma_queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
+-	pr_debug("sdma base address: 0x%x\n", retval);
++
++	pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n",
++			m->sdma_engine_id, m->sdma_queue_id, retval);
+ 
+ 	return retval;
+ }
+@@ -408,17 +410,17 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 	struct vi_sdma_mqd *m;
+ 	unsigned long end_jiffies;
+-	uint32_t sdma_base_addr;
++	uint32_t sdma_rlc_reg_offset;
+ 	uint32_t data;
+ 
+ 	m = get_sdma_mqd(mqd);
+-	sdma_base_addr = get_sdma_base_addr(m);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
++	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
+ 		m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
+ 
+ 	end_jiffies = msecs_to_jiffies(2000) + jiffies;
+ 	while (true) {
+-		data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
++		data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+ 		if (time_after(jiffies, end_jiffies)) {
+@@ -430,28 +432,29 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 
+ 	data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
+ 			     ENABLE, 1);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
++				m->sdmax_rlcx_rb_rptr);
+ 
+ 	if (read_user_wptr(mm, wptr, data))
+-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
++		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data);
+ 	else
+-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
++		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
+ 		       m->sdmax_rlcx_rb_rptr);
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR,
+ 				m->sdmax_rlcx_virtual_addr);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
+ 			m->sdmax_rlcx_rb_base_hi);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
+ 			m->sdmax_rlcx_rb_rptr_addr_lo);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
+ 			m->sdmax_rlcx_rb_rptr_addr_hi);
+ 
+ 	data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
+ 			     RB_ENABLE, 1);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
+ 
+ 	return 0;
+ }
+@@ -518,13 +521,13 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 	struct vi_sdma_mqd *m;
+-	uint32_t sdma_base_addr;
++	uint32_t sdma_rlc_reg_offset;
+ 	uint32_t sdma_rlc_rb_cntl;
+ 
+ 	m = get_sdma_mqd(mqd);
+-	sdma_base_addr = get_sdma_base_addr(m);
++	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
+ 
+-	sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
++	sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
+ 
+ 	if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
+ 		return true;
+@@ -642,19 +645,19 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 	struct vi_sdma_mqd *m;
+-	uint32_t sdma_base_addr;
++	uint32_t sdma_rlc_reg_offset;
+ 	uint32_t temp;
+ 	unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
+ 
+ 	m = get_sdma_mqd(mqd);
+-	sdma_base_addr = get_sdma_base_addr(m);
++	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
+ 
+-	temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
++	temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
+ 	temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
+ 
+ 	while (true) {
+-		temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
++		temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+ 		if (time_after(jiffies, end_jiffies)) {
+@@ -664,12 +667,12 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ 		usleep_range(500, 1000);
+ 	}
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+-		RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
++		RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
+ 		SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
+ 
+-	m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
++	m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+index 10d500507501..f214c94ccb2c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+@@ -234,22 +234,21 @@ int kgd_gfx_v9_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
+ 	return 0;
+ }
+ 
+-static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
++static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
+ 				unsigned int engine_id,
+ 				unsigned int queue_id)
+ {
+-	uint32_t base[2] = {
++	uint32_t sdma_engine_reg_base[2] = {
+ 		SOC15_REG_OFFSET(SDMA0, 0,
+ 				 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
+ 		SOC15_REG_OFFSET(SDMA1, 0,
+ 				 mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL
+ 	};
+-	uint32_t retval;
++	uint32_t retval = sdma_engine_reg_base[engine_id]
++		+ queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
+ 
+-	retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL -
+-					       mmSDMA0_RLC0_RB_CNTL);
+-
+-	pr_debug("sdma base address: 0x%x\n", retval);
++	pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
++			queue_id, retval);
+ 
+ 	return retval;
+ }
+@@ -406,22 +405,22 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 	struct v9_sdma_mqd *m;
+-	uint32_t sdma_base_addr;
++	uint32_t sdma_rlc_reg_offset;
+ 	unsigned long end_jiffies;
+ 	uint32_t data;
+ 	uint64_t data64;
+ 	uint64_t __user *wptr64 = (uint64_t __user *)wptr;
+ 
+ 	m = get_sdma_mqd(mqd);
+-	sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
++	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
+ 					    m->sdma_queue_id);
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
+ 		m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
+ 
+ 	end_jiffies = msecs_to_jiffies(2000) + jiffies;
+ 	while (true) {
+-		data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
++		data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+ 		if (time_after(jiffies, end_jiffies)) {
+@@ -431,41 +430,42 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+ 		usleep_range(500, 1000);
+ 	}
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
+ 	       m->sdmax_rlcx_doorbell_offset);
+ 
+ 	data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
+ 			     ENABLE, 1);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
++				m->sdmax_rlcx_rb_rptr);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
+ 				m->sdmax_rlcx_rb_rptr_hi);
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
+ 	if (read_user_wptr(mm, wptr64, data64)) {
+-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
++		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
+ 		       lower_32_bits(data64));
+-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
++		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
+ 		       upper_32_bits(data64));
+ 	} else {
+-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
++		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
+ 		       m->sdmax_rlcx_rb_rptr);
+-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
++		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
+ 		       m->sdmax_rlcx_rb_rptr_hi);
+ 	}
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
+ 			m->sdmax_rlcx_rb_base_hi);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
+ 			m->sdmax_rlcx_rb_rptr_addr_lo);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
+ 			m->sdmax_rlcx_rb_rptr_addr_hi);
+ 
+ 	data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
+ 			     RB_ENABLE, 1);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
+ 
+ 	return 0;
+ }
+@@ -475,7 +475,8 @@ static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
+ 			     uint32_t (**dump)[2], uint32_t *n_regs)
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+-	uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id);
++	uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
++			engine_id, queue_id);
+ 	uint32_t i = 0, reg;
+ #undef HQD_N_REGS
+ #define HQD_N_REGS (19+6+7+10)
+@@ -485,15 +486,15 @@ static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
+ 		return -ENOMEM;
+ 
+ 	for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
+-		DUMP_REG(sdma_base_addr + reg);
++		DUMP_REG(sdma_rlc_reg_offset + reg);
+ 	for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
+-		DUMP_REG(sdma_base_addr + reg);
++		DUMP_REG(sdma_rlc_reg_offset + reg);
+ 	for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
+ 	     reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
+-		DUMP_REG(sdma_base_addr + reg);
++		DUMP_REG(sdma_rlc_reg_offset + reg);
+ 	for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
+ 	     reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
+-		DUMP_REG(sdma_base_addr + reg);
++		DUMP_REG(sdma_rlc_reg_offset + reg);
+ 
+ 	WARN_ON_ONCE(i != HQD_N_REGS);
+ 	*n_regs = i;
+@@ -527,14 +528,14 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 	struct v9_sdma_mqd *m;
+-	uint32_t sdma_base_addr;
++	uint32_t sdma_rlc_reg_offset;
+ 	uint32_t sdma_rlc_rb_cntl;
+ 
+ 	m = get_sdma_mqd(mqd);
+-	sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
++	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
+ 					    m->sdma_queue_id);
+ 
+-	sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
++	sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
+ 
+ 	if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
+ 		return true;
+@@ -597,20 +598,20 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ 	struct v9_sdma_mqd *m;
+-	uint32_t sdma_base_addr;
++	uint32_t sdma_rlc_reg_offset;
+ 	uint32_t temp;
+ 	unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
+ 
+ 	m = get_sdma_mqd(mqd);
+-	sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
++	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
+ 					    m->sdma_queue_id);
+ 
+-	temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
++	temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
+ 	temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
+ 
+ 	while (true) {
+-		temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
++		temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
+ 		if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+ 			break;
+ 		if (time_after(jiffies, end_jiffies)) {
+@@ -620,14 +621,14 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ 		usleep_range(500, 1000);
+ 	}
+ 
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
+-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+-		RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
++	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
++		RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
+ 		SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
+ 
+-	m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
++	m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
+ 	m->sdmax_rlcx_rb_rptr_hi =
+-		RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI);
++		RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
+ 
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3966-drm-amdgpu-Add-SMUIO-values-for-other-I2C-controller.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3966-drm-amdgpu-Add-SMUIO-values-for-other-I2C-controller.patch
new file mode 100644
index 00000000..b4bb6c1e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3966-drm-amdgpu-Add-SMUIO-values-for-other-I2C-controller.patch
@@ -0,0 +1,312 @@
+From d2b181d1d6781cd3a3762aedca69af89a1f97133 Mon Sep 17 00:00:00 2001
+From: Kent Russell <kent.russell@amd.com>
+Date: Sun, 22 Sep 2019 21:20:14 -0400
+Subject: [PATCH 3966/4256] drm/amdgpu: Add SMUIO values for other I2C
+ controller v2
+
+These are the offsets for CKSVII2C1, and match up with the values
+already added for CKSVII2C
+
+v2: Don't remove some of the CSKVII2C values
+
+Change-Id: I5ed88bb31253ccaf4ed4ae6f4959040c0da2f6d0
+Signed-off-by: Kent Russell <kent.russell@amd.com>
+Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+---
+ .../asic_reg/smuio/smuio_11_0_0_offset.h      |  92 +++++++++
+ .../asic_reg/smuio/smuio_11_0_0_sh_mask.h     | 176 ++++++++++++++++++
+ 2 files changed, 268 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h
+index d3876052562b..687d6843c258 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h
+@@ -121,6 +121,98 @@
+ #define mmCKSVII2C_IC_COMP_VERSION_BASE_IDX                                                            0
+ #define mmCKSVII2C_IC_COMP_TYPE                                                                        0x006d
+ #define mmCKSVII2C_IC_COMP_TYPE_BASE_IDX                                                               0
++#define mmCKSVII2C1_IC_CON                                                                             0x0080
++#define mmCKSVII2C1_IC_CON_BASE_IDX                                                                    0
++#define mmCKSVII2C1_IC_TAR                                                                             0x0081
++#define mmCKSVII2C1_IC_TAR_BASE_IDX                                                                    0
++#define mmCKSVII2C1_IC_SAR                                                                             0x0082
++#define mmCKSVII2C1_IC_SAR_BASE_IDX                                                                    0
++#define mmCKSVII2C1_IC_HS_MADDR                                                                        0x0083
++#define mmCKSVII2C1_IC_HS_MADDR_BASE_IDX                                                               0
++#define mmCKSVII2C1_IC_DATA_CMD                                                                        0x0084
++#define mmCKSVII2C1_IC_DATA_CMD_BASE_IDX                                                               0
++#define mmCKSVII2C1_IC_SS_SCL_HCNT                                                                     0x0085
++#define mmCKSVII2C1_IC_SS_SCL_HCNT_BASE_IDX                                                            0
++#define mmCKSVII2C1_IC_SS_SCL_LCNT                                                                     0x0086
++#define mmCKSVII2C1_IC_SS_SCL_LCNT_BASE_IDX                                                            0
++#define mmCKSVII2C1_IC_FS_SCL_HCNT                                                                     0x0087
++#define mmCKSVII2C1_IC_FS_SCL_HCNT_BASE_IDX                                                            0
++#define mmCKSVII2C1_IC_FS_SCL_LCNT                                                                     0x0088
++#define mmCKSVII2C1_IC_FS_SCL_LCNT_BASE_IDX                                                            0
++#define mmCKSVII2C1_IC_HS_SCL_HCNT                                                                     0x0089
++#define mmCKSVII2C1_IC_HS_SCL_HCNT_BASE_IDX                                                            0
++#define mmCKSVII2C1_IC_HS_SCL_LCNT                                                                     0x008a
++#define mmCKSVII2C1_IC_HS_SCL_LCNT_BASE_IDX                                                            0
++#define mmCKSVII2C1_IC_INTR_STAT                                                                       0x008b
++#define mmCKSVII2C1_IC_INTR_STAT_BASE_IDX                                                              0
++#define mmCKSVII2C1_IC_INTR_MASK                                                                       0x008c
++#define mmCKSVII2C1_IC_INTR_MASK_BASE_IDX                                                              0
++#define mmCKSVII2C1_IC_RAW_INTR_STAT                                                                   0x008d
++#define mmCKSVII2C1_IC_RAW_INTR_STAT_BASE_IDX                                                          0
++#define mmCKSVII2C1_IC_RX_TL                                                                           0x008e
++#define mmCKSVII2C1_IC_RX_TL_BASE_IDX                                                                  0
++#define mmCKSVII2C1_IC_TX_TL                                                                           0x008f
++#define mmCKSVII2C1_IC_TX_TL_BASE_IDX                                                                  0
++#define mmCKSVII2C1_IC_CLR_INTR                                                                        0x0090
++#define mmCKSVII2C1_IC_CLR_INTR_BASE_IDX                                                               0
++#define mmCKSVII2C1_IC_CLR_RX_UNDER                                                                    0x0091
++#define mmCKSVII2C1_IC_CLR_RX_UNDER_BASE_IDX                                                           0
++#define mmCKSVII2C1_IC_CLR_RX_OVER                                                                     0x0092
++#define mmCKSVII2C1_IC_CLR_RX_OVER_BASE_IDX                                                            0
++#define mmCKSVII2C1_IC_CLR_TX_OVER                                                                     0x0093
++#define mmCKSVII2C1_IC_CLR_TX_OVER_BASE_IDX                                                            0
++#define mmCKSVII2C1_IC_CLR_RD_REQ                                                                      0x0094
++#define mmCKSVII2C1_IC_CLR_RD_REQ_BASE_IDX                                                             0
++#define mmCKSVII2C1_IC_CLR_TX_ABRT                                                                     0x0095
++#define mmCKSVII2C1_IC_CLR_TX_ABRT_BASE_IDX                                                            0
++#define mmCKSVII2C1_IC_CLR_RX_DONE                                                                     0x0096
++#define mmCKSVII2C1_IC_CLR_RX_DONE_BASE_IDX                                                            0
++#define mmCKSVII2C1_IC_CLR_ACTIVITY                                                                    0x0097
++#define mmCKSVII2C1_IC_CLR_ACTIVITY_BASE_IDX                                                           0
++#define mmCKSVII2C1_IC_CLR_STOP_DET                                                                    0x0098
++#define mmCKSVII2C1_IC_CLR_STOP_DET_BASE_IDX                                                           0
++#define mmCKSVII2C1_IC_CLR_START_DET                                                                   0x0099
++#define mmCKSVII2C1_IC_CLR_START_DET_BASE_IDX                                                          0
++#define mmCKSVII2C1_IC_CLR_GEN_CALL                                                                    0x009a
++#define mmCKSVII2C1_IC_CLR_GEN_CALL_BASE_IDX                                                           0
++#define mmCKSVII2C1_IC_ENABLE                                                                          0x009b
++#define mmCKSVII2C1_IC_ENABLE_BASE_IDX                                                                 0
++#define mmCKSVII2C1_IC_STATUS                                                                          0x009c
++#define mmCKSVII2C1_IC_STATUS_BASE_IDX                                                                 0
++#define mmCKSVII2C1_IC_TXFLR                                                                           0x009d
++#define mmCKSVII2C1_IC_TXFLR_BASE_IDX                                                                  0
++#define mmCKSVII2C1_IC_RXFLR                                                                           0x009e
++#define mmCKSVII2C1_IC_RXFLR_BASE_IDX                                                                  0
++#define mmCKSVII2C1_IC_SDA_HOLD                                                                        0x009f
++#define mmCKSVII2C1_IC_SDA_HOLD_BASE_IDX                                                               0
++#define mmCKSVII2C1_IC_TX_ABRT_SOURCE                                                                  0x00a0
++#define mmCKSVII2C1_IC_TX_ABRT_SOURCE_BASE_IDX                                                         0
++#define mmCKSVII2C1_IC_SLV_DATA_NACK_ONLY                                                              0x00a1
++#define mmCKSVII2C1_IC_SLV_DATA_NACK_ONLY_BASE_IDX                                                     0
++#define mmCKSVII2C1_IC_DMA_CR                                                                          0x00a2
++#define mmCKSVII2C1_IC_DMA_CR_BASE_IDX                                                                 0
++#define mmCKSVII2C1_IC_DMA_TDLR                                                                        0x00a3
++#define mmCKSVII2C1_IC_DMA_TDLR_BASE_IDX                                                               0
++#define mmCKSVII2C1_IC_DMA_RDLR                                                                        0x00a4
++#define mmCKSVII2C1_IC_DMA_RDLR_BASE_IDX                                                               0
++#define mmCKSVII2C1_IC_SDA_SETUP                                                                       0x00a5
++#define mmCKSVII2C1_IC_SDA_SETUP_BASE_IDX                                                              0
++#define mmCKSVII2C1_IC_ACK_GENERAL_CALL                                                                0x00a6
++#define mmCKSVII2C1_IC_ACK_GENERAL_CALL_BASE_IDX                                                       0
++#define mmCKSVII2C1_IC_ENABLE_STATUS                                                                   0x00a7
++#define mmCKSVII2C1_IC_ENABLE_STATUS_BASE_IDX                                                          0
++#define mmCKSVII2C1_IC_FS_SPKLEN                                                                       0x00a8
++#define mmCKSVII2C1_IC_FS_SPKLEN_BASE_IDX                                                              0
++#define mmCKSVII2C1_IC_HS_SPKLEN                                                                       0x00a9
++#define mmCKSVII2C1_IC_HS_SPKLEN_BASE_IDX                                                              0
++#define mmCKSVII2C1_IC_CLR_RESTART_DET                                                                 0x00aa
++#define mmCKSVII2C1_IC_CLR_RESTART_DET_BASE_IDX                                                        0
++#define mmCKSVII2C1_IC_COMP_PARAM_1                                                                    0x00ab
++#define mmCKSVII2C1_IC_COMP_PARAM_1_BASE_IDX                                                           0
++#define mmCKSVII2C1_IC_COMP_VERSION                                                                    0x00ac
++#define mmCKSVII2C1_IC_COMP_VERSION_BASE_IDX                                                           0
++#define mmCKSVII2C1_IC_COMP_TYPE                                                                       0x00ad
++#define mmCKSVII2C1_IC_COMP_TYPE_BASE_IDX                                                              0
+ #define mmSMUIO_MP_RESET_INTR                                                                          0x00c1
+ #define mmSMUIO_MP_RESET_INTR_BASE_IDX                                                                 0
+ #define mmSMUIO_SOC_HALT                                                                               0x00c2
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h
+index f8afa3518bf2..6905a9618127 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h
+@@ -268,6 +268,182 @@
+ //CKSVII2C_IC_COMP_TYPE
+ #define CKSVII2C_IC_COMP_TYPE__COMP_TYPE__SHIFT                                                               0x0
+ #define CKSVII2C_IC_COMP_TYPE__COMP_TYPE_MASK                                                                 0xFFFFFFFFL
++//CKSVII2C1_IC_CON
++#define CKSVII2C1_IC_CON__IC1_MASTER_MODE__SHIFT                                                              0x0
++#define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE__SHIFT                                                           0x1
++#define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE__SHIFT                                                          0x3
++#define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER__SHIFT                                                         0x4
++#define CKSVII2C1_IC_CON__IC1_RESTART_EN__SHIFT                                                               0x5
++#define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE__SHIFT                                                            0x6
++#define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED__SHIFT                                                        0x7
++#define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL__SHIFT                                                               0x8
++#define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL__SHIFT                                                       0x9
++#define CKSVII2C1_IC_CON__IC1_MASTER_MODE_MASK                                                                0x00000001L
++#define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE_MASK                                                             0x00000006L
++#define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE_MASK                                                            0x00000008L
++#define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER_MASK                                                           0x00000010L
++#define CKSVII2C1_IC_CON__IC1_RESTART_EN_MASK                                                                 0x00000020L
++#define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE_MASK                                                              0x00000040L
++#define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED_MASK                                                          0x00000080L
++#define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL_MASK                                                                 0x00000100L
++#define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL_MASK                                                         0x00000200L
++//CKSVII2C1_IC_TAR
++#define CKSVII2C1_IC_TAR__IC1_TAR__SHIFT                                                                      0x0
++#define CKSVII2C1_IC_TAR__GC1_OR_START__SHIFT                                                                 0xa
++#define CKSVII2C1_IC_TAR__SPECIAL1__SHIFT                                                                     0xb
++#define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER__SHIFT                                                         0xc
++#define CKSVII2C1_IC_TAR__IC1_TAR_MASK                                                                        0x000003FFL
++#define CKSVII2C1_IC_TAR__GC1_OR_START_MASK                                                                   0x00000400L
++#define CKSVII2C1_IC_TAR__SPECIAL1_MASK                                                                       0x00000800L
++#define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER_MASK                                                           0x00001000L
++//CKSVII2C1_IC_SAR
++#define CKSVII2C1_IC_SAR__IC1_SAR__SHIFT                                                                      0x0
++#define CKSVII2C1_IC_SAR__IC1_SAR_MASK                                                                        0x000003FFL
++//CKSVII2C1_IC_HS_MADDR
++#define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR__SHIFT                                                            0x0
++#define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR_MASK                                                              0x00000007L
++//CKSVII2C1_IC_DATA_CMD
++#define CKSVII2C1_IC_DATA_CMD__DAT1__SHIFT                                                                    0x0
++#define CKSVII2C1_IC_DATA_CMD__CMD1__SHIFT                                                                    0x8
++#define CKSVII2C1_IC_DATA_CMD__STOP1__SHIFT                                                                   0x9
++#define CKSVII2C1_IC_DATA_CMD__RESTART1__SHIFT                                                                0xa
++#define CKSVII2C1_IC_DATA_CMD__DAT1_MASK                                                                      0x000000FFL
++#define CKSVII2C1_IC_DATA_CMD__CMD1_MASK                                                                      0x00000100L
++#define CKSVII2C1_IC_DATA_CMD__STOP1_MASK                                                                     0x00000200L
++#define CKSVII2C1_IC_DATA_CMD__RESTART1_MASK                                                                  0x00000400L
++//CKSVII2C1_IC_SS_SCL_HCNT
++#define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT__SHIFT                                                      0x0
++#define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT_MASK                                                        0x0000FFFFL
++//CKSVII2C1_IC_SS_SCL_LCNT
++#define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT__SHIFT                                                      0x0
++#define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT_MASK                                                        0x0000FFFFL
++//CKSVII2C1_IC_FS_SCL_HCNT
++#define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT__SHIFT                                                      0x0
++#define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT_MASK                                                        0x0000FFFFL
++//CKSVII2C1_IC_FS_SCL_LCNT
++#define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT__SHIFT                                                      0x0
++#define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT_MASK                                                        0x0000FFFFL
++//CKSVII2C1_IC_HS_SCL_HCNT
++#define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT__SHIFT                                                      0x0
++#define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT_MASK                                                        0x0000FFFFL
++//CKSVII2C1_IC_HS_SCL_LCNT
++#define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT__SHIFT                                                      0x0
++#define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT_MASK                                                        0x0000FFFFL
++//CKSVII2C1_IC_INTR_STAT
++#define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER__SHIFT                                                            0x0
++#define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER__SHIFT                                                             0x1
++#define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL__SHIFT                                                             0x2
++#define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER__SHIFT                                                             0x3
++#define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY__SHIFT                                                            0x4
++#define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ__SHIFT                                                              0x5
++#define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT__SHIFT                                                             0x6
++#define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE__SHIFT                                                             0x7
++#define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY__SHIFT                                                            0x8
++#define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET__SHIFT                                                            0x9
++#define CKSVII2C1_IC_INTR_STAT__R1_START_DET__SHIFT                                                           0xa
++#define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL__SHIFT                                                            0xb
++#define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET__SHIFT                                                         0xc
++#define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD__SHIFT                                                         0xd
++#define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER_MASK                                                              0x00000001L
++#define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER_MASK                                                               0x00000002L
++#define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL_MASK                                                               0x00000004L
++#define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER_MASK                                                               0x00000008L
++#define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY_MASK                                                              0x00000010L
++#define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ_MASK                                                                0x00000020L
++#define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT_MASK                                                               0x00000040L
++#define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE_MASK                                                               0x00000080L
++#define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY_MASK                                                              0x00000100L
++#define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET_MASK                                                              0x00000200L
++#define CKSVII2C1_IC_INTR_STAT__R1_START_DET_MASK                                                             0x00000400L
++#define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL_MASK                                                              0x00000800L
++#define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET_MASK                                                           0x00001000L
++#define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD_MASK                                                           0x00002000L
++//CKSVII2C1_IC_INTR_MASK
++#define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER__SHIFT                                                            0x0
++#define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER__SHIFT                                                             0x1
++#define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL__SHIFT                                                             0x2
++#define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER__SHIFT                                                             0x3
++#define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY__SHIFT                                                            0x4
++#define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ__SHIFT                                                              0x5
++#define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT__SHIFT                                                             0x6
++#define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE__SHIFT                                                             0x7
++#define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY__SHIFT                                                            0x8
++#define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET__SHIFT                                                            0x9
++#define CKSVII2C1_IC_INTR_MASK__M1_START_DET__SHIFT                                                           0xa
++#define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL__SHIFT                                                            0xb
++#define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET__SHIFT                                                         0xc
++#define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD__SHIFT                                                         0xd
++#define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER_MASK                                                              0x00000001L
++#define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER_MASK                                                               0x00000002L
++#define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL_MASK                                                               0x00000004L
++#define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER_MASK                                                               0x00000008L
++#define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY_MASK                                                              0x00000010L
++#define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ_MASK                                                                0x00000020L
++#define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT_MASK                                                               0x00000040L
++#define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE_MASK                                                               0x00000080L
++#define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY_MASK                                                              0x00000100L
++#define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET_MASK                                                              0x00000200L
++#define CKSVII2C1_IC_INTR_MASK__M1_START_DET_MASK                                                             0x00000400L
++#define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL_MASK                                                              0x00000800L
++#define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET_MASK                                                           0x00001000L
++#define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD_MASK                                                           0x00002000L
++//CKSVII2C1_IC_RAW_INTR_STAT
++//CKSVII2C1_IC_RX_TL
++//CKSVII2C1_IC_TX_TL
++//CKSVII2C1_IC_CLR_INTR
++//CKSVII2C1_IC_CLR_RX_UNDER
++//CKSVII2C1_IC_CLR_RX_OVER
++//CKSVII2C1_IC_CLR_TX_OVER
++//CKSVII2C1_IC_CLR_RD_REQ
++//CKSVII2C1_IC_CLR_TX_ABRT
++//CKSVII2C1_IC_CLR_RX_DONE
++//CKSVII2C1_IC_CLR_ACTIVITY
++//CKSVII2C1_IC_CLR_STOP_DET
++//CKSVII2C1_IC_CLR_START_DET
++//CKSVII2C1_IC_CLR_GEN_CALL
++//CKSVII2C1_IC_ENABLE
++#define CKSVII2C1_IC_ENABLE__ENABLE1__SHIFT                                                                   0x0
++#define CKSVII2C1_IC_ENABLE__ABORT1__SHIFT                                                                    0x1
++#define CKSVII2C1_IC_ENABLE__ENABLE1_MASK                                                                     0x00000001L
++#define CKSVII2C1_IC_ENABLE__ABORT1_MASK                                                                      0x00000002L
++//CKSVII2C1_IC_STATUS
++#define CKSVII2C1_IC_STATUS__ACTIVITY1__SHIFT                                                                 0x0
++#define CKSVII2C1_IC_STATUS__TFNF1__SHIFT                                                                     0x1
++#define CKSVII2C1_IC_STATUS__TFE1__SHIFT                                                                      0x2
++#define CKSVII2C1_IC_STATUS__RFNE1__SHIFT                                                                     0x3
++#define CKSVII2C1_IC_STATUS__RFF1__SHIFT                                                                      0x4
++#define CKSVII2C1_IC_STATUS__MST1_ACTIVITY__SHIFT                                                             0x5
++#define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY__SHIFT                                                             0x6
++#define CKSVII2C1_IC_STATUS__ACTIVITY1_MASK                                                                   0x00000001L
++#define CKSVII2C1_IC_STATUS__TFNF1_MASK                                                                       0x00000002L
++#define CKSVII2C1_IC_STATUS__TFE1_MASK                                                                        0x00000004L
++#define CKSVII2C1_IC_STATUS__RFNE1_MASK                                                                       0x00000008L
++#define CKSVII2C1_IC_STATUS__RFF1_MASK                                                                        0x00000010L
++#define CKSVII2C1_IC_STATUS__MST1_ACTIVITY_MASK                                                               0x00000020L
++#define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY_MASK                                                               0x00000040L
++//CKSVII2C1_IC_TXFLR
++//CKSVII2C1_IC_RXFLR
++//CKSVII2C1_IC_SDA_HOLD
++#define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_HOLD__SHIFT                                                            0x0
++#define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_HOLD_MASK                                                              0x00FFFFFFL
++//CKSVII2C1_IC_TX_ABRT_SOURCE
++//CKSVII2C1_IC_SLV_DATA_NACK_ONLY
++//CKSVII2C1_IC_DMA_CR
++//CKSVII2C1_IC_DMA_TDLR
++//CKSVII2C1_IC_DMA_RDLR
++//CKSVII2C1_IC_SDA_SETUP
++#define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP__SHIFT                                                             0x0
++#define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP_MASK                                                               0x000000FFL
++//CKSVII2C1_IC_ACK_GENERAL_CALL
++#define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GENERAL_CALL__SHIFT                                               0x0
++#define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GENERAL_CALL_MASK                                                 0x00000001L
++//CKSVII2C1_IC_ENABLE_STATUS
++#define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN__SHIFT                                                             0x0
++#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_ABORTED__SHIFT                                                    0x1
++#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_FIFO_FILLED_AND_FLUSHED__SHIFT                                       0x2
++#define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN_MASK                                                               0x00000001L
++#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_ABORTED_MASK                                                      0x00000002L
++#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_FIFO_FILLED_AND_FLUSHED_MASK                                         0x00000004L
+ //SMUIO_MP_RESET_INTR
+ #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT                                                       0x0
+ #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK                                                         0x00000001L
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3967-drm-amdkfd-use-navi12-specific-family-id-for-navi12-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3967-drm-amdkfd-use-navi12-specific-family-id-for-navi12-.patch
new file mode 100644
index 00000000..8b885ea3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3967-drm-amdkfd-use-navi12-specific-family-id-for-navi12-.patch
@@ -0,0 +1,109 @@
+From 4555bf4a65ef3b32ef35e36524f3e7d7564e5f19 Mon Sep 17 00:00:00 2001
+From: shaoyunl <shaoyun.liu@amd.com>
+Date: Wed, 25 Sep 2019 17:07:38 -0400
+Subject: [PATCH 3967/4256] drm/amdkfd: use navi12 specific family id for
+ navi12 code path
+
+Keep the same use of CHIP_IDs for navi12 in kfd
+
+Change-Id: I5e52bbc058be51e79553147732a571a604537b7c
+Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_crat.c                 | 1 +
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c               | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 1 +
+ drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c          | 1 +
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c         | 1 +
+ drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c       | 1 +
+ drivers/gpu/drm/amd/amdkfd/kfd_topology.c             | 1 +
+ 7 files changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+index d9e075d66065..7655c6a2b184 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+@@ -676,6 +676,7 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
+ 		num_of_cache_types = ARRAY_SIZE(renoir_cache_info);
+ 		break;
+ 	case CHIP_NAVI10:
++	case CHIP_NAVI12:
+ 	case CHIP_NAVI14:
+ 		pcache_info = navi10_cache_info;
+ 		num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index 43c4456b8620..d7e687062dd7 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -388,7 +388,7 @@ static const struct kfd_device_info navi10_device_info = {
+ };
+ 
+ static const struct kfd_device_info navi12_device_info = {
+-	.asic_family = CHIP_NAVI10,
++	.asic_family = CHIP_NAVI12,
+ 	.asic_name = "navi12",
+ 	.max_pasid_bits = 16,
+ 	.max_no_of_hqd  = 24,
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 3aec5046d26d..02d2118fa9ba 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -1946,6 +1946,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
+ 		device_queue_manager_init_v9(&dqm->asic_ops);
+ 		break;
+ 	case CHIP_NAVI10:
++	case CHIP_NAVI12:
+ 	case CHIP_NAVI14:
+ 		device_queue_manager_init_v10_navi10(&dqm->asic_ops);
+ 		break;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+index ae950633228c..bb77b8890e77 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+@@ -413,6 +413,7 @@ int kfd_init_apertures(struct kfd_process *process)
+ 			case CHIP_RENOIR:
+ 			case CHIP_ARCTURUS:
+ 			case CHIP_NAVI10:
++			case CHIP_NAVI12:
+ 			case CHIP_NAVI14:
+ 				kfd_init_apertures_v9(pdd, id);
+ 				break;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+index ac031dc09d66..5e2d75ca2b62 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+@@ -370,6 +370,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
+ 		kernel_queue_init_v9(&kq->ops_asic_specific);
+ 		break;
+ 	case CHIP_NAVI10:
++	case CHIP_NAVI12:
+ 	case CHIP_NAVI14:
+ 		kernel_queue_init_v10(&kq->ops_asic_specific);
+ 		break;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+index 43e8e0258188..13bd55a92fd6 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+@@ -246,6 +246,7 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
+ 		pm->pmf = &kfd_v9_pm_funcs;
+ 		break;
+ 	case CHIP_NAVI10:
++	case CHIP_NAVI12:
+ 	case CHIP_NAVI14:
+ 		pm->pmf = &kfd_v10_pm_funcs;
+ 		break;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+index ea6dc5d73c8c..49a1728dadf2 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+@@ -1396,6 +1396,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
+ 	case CHIP_RENOIR:
+ 	case CHIP_ARCTURUS:
+ 	case CHIP_NAVI10:
++	case CHIP_NAVI12:
+ 	case CHIP_NAVI14:
+ 		dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
+ 			HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3968-device_cgroup-Export-devcgroup_check_permission.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3968-device_cgroup-Export-devcgroup_check_permission.patch
new file mode 100644
index 00000000..a9bf6768
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3968-device_cgroup-Export-devcgroup_check_permission.patch
@@ -0,0 +1,93 @@
+From cc0651f68dbb5196c0e8bdd4a154850319455e89 Mon Sep 17 00:00:00 2001
+From: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
+Date: Thu, 16 May 2019 11:37:16 -0400
+Subject: [PATCH 3968/4256] device_cgroup: Export devcgroup_check_permission
+
+For AMD compute (amdkfd) driver.
+
+All AMD compute devices are exported via single device node /dev/kfd. As
+a result devices cannot be controlled individually using device cgroup.
+
+AMD compute devices will rely on its graphics counterpart that exposes
+/dev/dri/renderN node for each device. For each task (based on its
+cgroup), KFD driver will check if /dev/dri/renderN node is accessible
+before exposing it.
+
+Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
+Acked-by: Tejun Heo <tj@kernel.org>
+Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by:: Roman Gushchin <guro@fb.com>
+---
+ include/linux/device_cgroup.h | 19 ++++---------------
+ security/device_cgroup.c      | 16 +++++++++++++---
+ 2 files changed, 17 insertions(+), 18 deletions(-)
+
+diff --git a/include/linux/device_cgroup.h b/include/linux/device_cgroup.h
+index 8557efe096dc..fa35b52e0002 100644
+--- a/include/linux/device_cgroup.h
++++ b/include/linux/device_cgroup.h
+@@ -12,26 +12,15 @@
+ #define DEVCG_DEV_ALL   4  /* this represents all devices */
+ 
+ #ifdef CONFIG_CGROUP_DEVICE
+-extern int __devcgroup_check_permission(short type, u32 major, u32 minor,
+-					short access);
++int devcgroup_check_permission(short type, u32 major, u32 minor,
++			       short access);
+ #else
+-static inline int __devcgroup_check_permission(short type, u32 major, u32 minor,
+-					       short access)
++static inline int devcgroup_check_permission(short type, u32 major, u32 minor,
++					     short access)
+ { return 0; }
+ #endif
+ 
+ #if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF)
+-static inline int devcgroup_check_permission(short type, u32 major, u32 minor,
+-					     short access)
+-{
+-	int rc = BPF_CGROUP_RUN_PROG_DEVICE_CGROUP(type, major, minor, access);
+-
+-	if (rc)
+-		return -EPERM;
+-
+-	return __devcgroup_check_permission(type, major, minor, access);
+-}
+-
+ static inline int devcgroup_inode_permission(struct inode *inode, int mask)
+ {
+ 	short type, access = 0;
+diff --git a/security/device_cgroup.c b/security/device_cgroup.c
+index e3a9ad5db5a0..3c57e05bf73b 100644
+--- a/security/device_cgroup.c
++++ b/security/device_cgroup.c
+@@ -801,8 +801,8 @@ struct cgroup_subsys devices_cgrp_subsys = {
+  *
+  * returns 0 on success, -EPERM case the operation is not permitted
+  */
+-int __devcgroup_check_permission(short type, u32 major, u32 minor,
+-				 short access)
++static int __devcgroup_check_permission(short type, u32 major, u32 minor,
++					short access)
+ {
+ 	struct dev_cgroup *dev_cgroup;
+ 	bool rc;
+@@ -824,4 +824,14 @@ int __devcgroup_check_permission(short type, u32 major, u32 minor,
+ 
+ 	return 0;
+ }
+-EXPORT_SYMBOL(__devcgroup_check_permission);
++
++int devcgroup_check_permission(short type, u32 major, u32 minor, short access)
++{
++	int rc = BPF_CGROUP_RUN_PROG_DEVICE_CGROUP(type, major, minor, access);
++
++	if (rc)
++		return -EPERM;
++
++	return __devcgroup_check_permission(type, major, minor, access);
++}
++EXPORT_SYMBOL(devcgroup_check_permission);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3969-drm-amdkfd-Move-the-control-stack-on-GFX10-to-usersp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3969-drm-amdkfd-Move-the-control-stack-on-GFX10-to-usersp.patch
new file mode 100644
index 00000000..313e093f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3969-drm-amdkfd-Move-the-control-stack-on-GFX10-to-usersp.patch
@@ -0,0 +1,78 @@
+From 95390fb66b10ea4a34b7d88c5a90731565378709 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 25 Sep 2019 14:07:26 -0400
+Subject: [PATCH 3969/4256] drm/amdkfd: Move the control stack on GFX10 to
+ userspace buffer
+
+The GFX10 does not require the control stack to be right after mqd
+buffer any more, so move it back to usersapce allocated CSWR buffer.
+
+Change-Id: I446c9685549a09ac8846a42ee22d86cfb93fd98c
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c  | 37 ++-----------------
+ 1 file changed, 4 insertions(+), 33 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index 29d50d6af9d7..e2fb76247f47 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -69,35 +69,13 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd,
+ static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,
+ 		struct queue_properties *q)
+ {
+-	int retval;
+-	struct kfd_mem_obj *mqd_mem_obj = NULL;
++	struct kfd_mem_obj *mqd_mem_obj;
+ 
+-	/* From V9,  for CWSR, the control stack is located on the next page
+-	 * boundary after the mqd, we will use the gtt allocation function
+-	 * instead of sub-allocation function.
+-	 */
+-	if (kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) {
+-		mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_NOIO);
+-		if (!mqd_mem_obj)
+-			return NULL;
+-		retval = amdgpu_amdkfd_alloc_gtt_mem(kfd->kgd,
+-			ALIGN(q->ctl_stack_size, PAGE_SIZE) +
+-				ALIGN(sizeof(struct v10_compute_mqd), PAGE_SIZE),
+-			&(mqd_mem_obj->gtt_mem),
+-			&(mqd_mem_obj->gpu_addr),
+-			(void *)&(mqd_mem_obj->cpu_ptr), true);
+-	} else {
+-		retval = kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd),
+-				&mqd_mem_obj);
+-	}
+-
+-	if (retval) {
+-		kfree(mqd_mem_obj);
++	if (kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd),
++			&mqd_mem_obj))
+ 		return NULL;
+-	}
+ 
+ 	return mqd_mem_obj;
+-
+ }
+ 
+ static void init_mqd(struct mqd_manager *mm, void **mqd,
+@@ -250,14 +228,7 @@ static int destroy_mqd(struct mqd_manager *mm, void *mqd,
+ static void free_mqd(struct mqd_manager *mm, void *mqd,
+ 			struct kfd_mem_obj *mqd_mem_obj)
+ {
+-	struct kfd_dev *kfd = mm->dev;
+-
+-	if (mqd_mem_obj->gtt_mem) {
+-		amdgpu_amdkfd_free_gtt_mem(kfd->kgd, mqd_mem_obj->gtt_mem);
+-		kfree(mqd_mem_obj);
+-	} else {
+-		kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
+-	}
++	kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
+ }
+ 
+ static bool is_occupied(struct mqd_manager *mm, void *mqd,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3970-drm-amdkfd-Delete-unused-defines.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3970-drm-amdkfd-Delete-unused-defines.patch
new file mode 100644
index 00000000..86884160
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3970-drm-amdkfd-Delete-unused-defines.patch
@@ -0,0 +1,31 @@
+From 5617134a4e5e3c8fe11a420bb6390217cc33c519 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 25 Sep 2019 16:45:18 -0400
+Subject: [PATCH 3970/4256] drm/amdkfd: Delete unused defines
+
+They are not used anywhere.
+
+Change-Id: Ieba4f57760f0c45f24e54629245cae419b8ff157
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+index f214c94ccb2c..c6f27ad29d61 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+@@ -52,9 +52,6 @@
+ #include "gmc_v9_0.h"
+ 
+ 
+-#define V9_PIPE_PER_MEC		(4)
+-#define V9_QUEUES_PER_PIPE_MEC	(8)
+-
+ enum hqd_dequeue_request_type {
+ 	NO_ACTION = 0,
+ 	DRAIN_PIPE,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3971-drm-amdkfd-Use-hex-print-format-for-pasid.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3971-drm-amdkfd-Use-hex-print-format-for-pasid.patch
new file mode 100644
index 00000000..5f52dad9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3971-drm-amdkfd-Use-hex-print-format-for-pasid.patch
@@ -0,0 +1,377 @@
+From 2b79da22d5be104feb44f634543969b67fe5cbb4 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 25 Sep 2019 17:00:59 -0400
+Subject: [PATCH 3971/4256] drm/amdkfd: Use hex print format for pasid
+
+Since KFD pasid starts from 0x8000 (32768 in decimal), it is better
+perceived as a hex number. Meanwhile, change the pasid type from
+unsigned int to uint16_t to be consistent throughout the code.
+
+Change-Id: I565fe39f69e782749a697f18545775354c7a89f8
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c      | 12 +++++------
+ drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c       |  4 ++--
+ drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c       |  8 ++++----
+ .../drm/amd/amdkfd/kfd_device_queue_manager.c |  8 ++++----
+ drivers/gpu/drm/amd/amdkfd/kfd_events.c       | 12 +++++------
+ drivers/gpu/drm/amd/amdkfd/kfd_iommu.c        |  6 +++---
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h         |  2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_process.c      | 20 +++++++++----------
+ .../amd/amdkfd/kfd_process_queue_manager.c    |  6 +++---
+ 9 files changed, 39 insertions(+), 39 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index 1713413e5ce5..9b934f68d726 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -306,7 +306,7 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
+ 		goto err_bind_process;
+ 	}
+ 
+-	pr_debug("Creating queue for PASID %d on gpu 0x%x\n",
++	pr_debug("Creating queue for PASID 0x%x on gpu 0x%x\n",
+ 			p->pasid,
+ 			dev->id);
+ 
+@@ -356,7 +356,7 @@ static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p,
+ 	int retval;
+ 	struct kfd_ioctl_destroy_queue_args *args = data;
+ 
+-	pr_debug("Destroying queue id %d for pasid %d\n",
++	pr_debug("Destroying queue id %d for pasid 0x%x\n",
+ 				args->queue_id,
+ 				p->pasid);
+ 
+@@ -403,7 +403,7 @@ static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p,
+ 	properties.queue_percent = args->queue_percentage;
+ 	properties.priority = args->queue_priority;
+ 
+-	pr_debug("Updating queue id %d for pasid %d\n",
++	pr_debug("Updating queue id %d for pasid 0x%x\n",
+ 			args->queue_id, p->pasid);
+ 
+ 	mutex_lock(&p->mutex);
+@@ -860,7 +860,7 @@ static int kfd_ioctl_get_process_apertures(struct file *filp,
+ 	struct kfd_process_device_apertures *pAperture;
+ 	struct kfd_process_device *pdd;
+ 
+-	dev_dbg(kfd_device, "get apertures for PASID %d", p->pasid);
++	dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid);
+ 
+ 	args->num_of_nodes = 0;
+ 
+@@ -918,7 +918,7 @@ static int kfd_ioctl_get_process_apertures_new(struct file *filp,
+ 	uint32_t nodes = 0;
+ 	int ret;
+ 
+-	dev_dbg(kfd_device, "get apertures for PASID %d", p->pasid);
++	dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid);
+ 
+ 	if (args->num_of_nodes == 0) {
+ 		/* Return number of nodes, so that user space can alloacate
+@@ -3067,7 +3067,7 @@ static int kfd_mmio_mmap(struct kfd_dev *dev, struct kfd_process *process,
+ 
+ 	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+ 
+-	pr_debug("Process %d mapping mmio page\n"
++	pr_debug("pasid 0x%x mapping mmio page\n"
+ 		 "     target user address == 0x%08llX\n"
+ 		 "     physical address    == 0x%08llX\n"
+ 		 "     vm_flags            == 0x%04lX\n"
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
+index 3635e0b4b3b7..492951cad143 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
+@@ -800,7 +800,7 @@ int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p)
+ 				(dev->kgd, vmid)) {
+ 			if (dev->kfd2kgd->get_atc_vmid_pasid_mapping_pasid
+ 					(dev->kgd, vmid) == p->pasid) {
+-				pr_debug("Killing wave fronts of vmid %d and pasid %d\n",
++				pr_debug("Killing wave fronts of vmid %d and pasid 0x%x\n",
+ 						vmid, p->pasid);
+ 				break;
+ 			}
+@@ -808,7 +808,7 @@ int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p)
+ 	}
+ 
+ 	if (vmid > last_vmid_to_scan) {
+-		pr_err("Didn't find vmid for pasid %d\n", p->pasid);
++		pr_err("Didn't find vmid for pasid 0x%x\n", p->pasid);
+ 		return -EFAULT;
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c
+index 9d4af961c5d1..9bfa50633654 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c
+@@ -96,7 +96,7 @@ bool kfd_dbgmgr_create(struct kfd_dbgmgr **ppmgr, struct kfd_dev *pdev)
+ long kfd_dbgmgr_register(struct kfd_dbgmgr *pmgr, struct kfd_process *p)
+ {
+ 	if (pmgr->pasid != 0) {
+-		pr_debug("H/W debugger is already active using pasid %d\n",
++		pr_debug("H/W debugger is already active using pasid 0x%x\n",
+ 				pmgr->pasid);
+ 		return -EBUSY;
+ 	}
+@@ -117,7 +117,7 @@ long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p)
+ {
+ 	/* Is the requests coming from the already registered process? */
+ 	if (pmgr->pasid != p->pasid) {
+-		pr_debug("H/W debugger is not registered by calling pasid %d\n",
++		pr_debug("H/W debugger is not registered by calling pasid 0x%x\n",
+ 				p->pasid);
+ 		return -EINVAL;
+ 	}
+@@ -134,7 +134,7 @@ long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr,
+ {
+ 	/* Is the requests coming from the already registered process? */
+ 	if (pmgr->pasid != wac_info->process->pasid) {
+-		pr_debug("H/W debugger support was not registered for requester pasid %d\n",
++		pr_debug("H/W debugger support was not registered for requester pasid 0x%x\n",
+ 				wac_info->process->pasid);
+ 		return -EINVAL;
+ 	}
+@@ -147,7 +147,7 @@ long kfd_dbgmgr_address_watch(struct kfd_dbgmgr *pmgr,
+ {
+ 	/* Is the requests coming from the already registered process? */
+ 	if (pmgr->pasid != adw_info->process->pasid) {
+-		pr_debug("H/W debugger support was not registered for requester pasid %d\n",
++		pr_debug("H/W debugger support was not registered for requester pasid 0x%x\n",
+ 				adw_info->process->pasid);
+ 		return -EINVAL;
+ 	}
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 02d2118fa9ba..10e49a9cbcfa 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -697,7 +697,7 @@ static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
+ 		goto out;
+ 
+ 	pdd = qpd_to_pdd(qpd);
+-	pr_info_ratelimited("Evicting PASID %u queues\n",
++	pr_info_ratelimited("Evicting PASID 0x%x queues\n",
+ 			    pdd->process->pasid);
+ 
+ 	/* Mark all queues as evicted. Deactivate all active queues on
+@@ -743,7 +743,7 @@ static int evict_process_queues_cpsch(struct device_queue_manager *dqm,
+ 		goto out;
+ 
+ 	pdd = qpd_to_pdd(qpd);
+-	pr_info_ratelimited("Evicting PASID %u queues\n",
++	pr_info_ratelimited("Evicting PASID 0x%x queues\n",
+ 			    pdd->process->pasid);
+ 
+ 	/* Mark all queues as evicted. Deactivate all active queues on
+@@ -794,7 +794,7 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
+ 		goto out;
+ 	}
+ 
+-	pr_info_ratelimited("Restoring PASID %u queues\n",
++	pr_info_ratelimited("Restoring PASID 0x%x queues\n",
+ 			    pdd->process->pasid);
+ 
+ 	/* Update PD Base in QPD */
+@@ -870,7 +870,7 @@ static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
+ 		goto out;
+ 	}
+ 
+-	pr_info_ratelimited("Restoring PASID %u queues\n",
++	pr_info_ratelimited("Restoring PASID 0x%x queues\n",
+ 			    pdd->process->pasid);
+ 
+ 	/* Update PD Base in QPD */
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+index 38a99ba91a88..6baf78c9245f 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+@@ -852,8 +852,8 @@ static void lookup_events_by_type_and_signal(struct kfd_process *p,
+ 
+ 	if (type == KFD_EVENT_TYPE_MEMORY) {
+ 		dev_warn(kfd_device,
+-			"Sending SIGSEGV to HSA Process with PID %d ",
+-				p->lead_thread->pid);
++			"Sending SIGSEGV to process %d (pasid 0x%x)",
++				p->lead_thread->pid, p->pasid);
+ 		send_sig(SIGSEGV, p->lead_thread, 0);
+ 	}
+ 
+@@ -861,13 +861,13 @@ static void lookup_events_by_type_and_signal(struct kfd_process *p,
+ 	if (send_signal) {
+ 		if (send_sigterm) {
+ 			dev_warn(kfd_device,
+-				"Sending SIGTERM to HSA Process with PID %d ",
+-					p->lead_thread->pid);
++				"Sending SIGTERM to process %d (pasid 0x%x)",
++					p->lead_thread->pid, p->pasid);
+ 			send_sig(SIGTERM, p->lead_thread, 0);
+ 		} else {
+ 			dev_err(kfd_device,
+-				"HSA Process (PID %d) got unhandled exception",
+-				p->lead_thread->pid);
++				"Process %d (pasid 0x%x) got unhandled exception",
++				p->lead_thread->pid, p->pasid);
+ 		}
+ 	}
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c b/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
+index 5f35df23fb18..193e2835bd4d 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
+@@ -160,7 +160,7 @@ static void iommu_pasid_shutdown_callback(struct pci_dev *pdev, int pasid)
+ 	if (!p)
+ 		return;
+ 
+-	pr_debug("Unbinding process %d from IOMMU\n", pasid);
++	pr_debug("Unbinding process 0x%x from IOMMU\n", pasid);
+ 
+ 	mutex_lock(kfd_get_dbgmgr_mutex());
+ 
+@@ -194,7 +194,7 @@ static int iommu_invalid_ppr_cb(struct pci_dev *pdev, int pasid,
+ 	struct kfd_dev *dev;
+ 
+ 	dev_warn_ratelimited(kfd_device,
+-			"Invalid PPR device %x:%x.%x pasid %d address 0x%lX flags 0x%X",
++			"Invalid PPR device %x:%x.%x pasid 0x%x address 0x%lX flags 0x%X",
+ 			PCI_BUS_NUM(pdev->devfn),
+ 			PCI_SLOT(pdev->devfn),
+ 			PCI_FUNC(pdev->devfn),
+@@ -235,7 +235,7 @@ static int kfd_bind_processes_to_device(struct kfd_dev *kfd)
+ 		err = amd_iommu_bind_pasid(kfd->pdev, p->pasid,
+ 				p->lead_thread);
+ 		if (err < 0) {
+-			pr_err("Unexpected pasid %d binding failure\n",
++			pr_err("Unexpected pasid 0x%x binding failure\n",
+ 					p->pasid);
+ 			mutex_unlock(&p->mutex);
+ 			break;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index 9ac50a4eb294..f856c14a6ed0 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -813,7 +813,7 @@ struct kfd_process {
+ 	/* Use for delayed freeing of kfd_process structure */
+ 	struct rcu_head	rcu;
+ 
+-	unsigned int pasid;
++	uint16_t pasid;
+ 	unsigned int doorbell_index;
+ 
+ 	/*
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+index d7e057376d8f..3f061264bae9 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+@@ -446,7 +446,7 @@ static void kfd_process_destroy_pdds(struct kfd_process *p)
+ 
+ 	list_for_each_entry_safe(pdd, temp, &p->per_device_data,
+ 				 per_device_list) {
+-		pr_debug("Releasing pdd (topology id %d) for process (pasid %d)\n",
++		pr_debug("Releasing pdd (topology id %d) for process (pasid 0x%x)\n",
+ 				pdd->dev->id, p->pasid);
+ 
+ 		if (pdd->drm_file) {
+@@ -1279,7 +1279,7 @@ static void evict_process_worker(struct work_struct *work)
+ 
+ 	p->last_evict_timestamp = get_jiffies_64();
+ 
+-	pr_info("Started evicting pasid %d\n", p->pasid);
++	pr_debug("Started evicting pasid 0x%x\n", p->pasid);
+ 	ret = kfd_process_evict_queues(p);
+ 	if (!ret) {
+ 		dma_fence_signal(p->ef);
+@@ -1292,9 +1292,9 @@ static void evict_process_worker(struct work_struct *work)
+ 			pr_debug("Process %d queues idle, doorbell unmapped\n",
+ 				p->pasid);
+ 
+-		pr_info("Finished evicting pasid %d\n", p->pasid);
++		pr_debug("Finished evicting pasid 0x%x\n", p->pasid);
+ 	} else
+-		pr_err("Failed to evict queues of pasid %d\n", p->pasid);
++		pr_err("Failed to evict queues of pasid 0x%x\n", p->pasid);
+ 	trace_kfd_evict_process_worker_end(p, ret ? "Failed" : "Success");
+ }
+ 
+@@ -1313,7 +1313,7 @@ static void restore_process_worker(struct work_struct *work)
+ 
+ 	trace_kfd_restore_process_worker_start(p);
+ 
+-	pr_info("Started restoring pasid %d\n", p->pasid);
++	pr_debug("Started restoring pasid 0x%x\n", p->pasid);
+ 
+ 	/* Setting last_restore_timestamp before successful restoration.
+ 	 * Otherwise this would have to be set by KGD (restore_process_bos)
+@@ -1329,7 +1329,7 @@ static void restore_process_worker(struct work_struct *work)
+ 	ret = amdgpu_amdkfd_gpuvm_restore_process_bos(p->kgd_process_info,
+ 						     &p->ef);
+ 	if (ret) {
+-		pr_info("Failed to restore BOs of pasid %d, retry after %d ms\n",
++		pr_debug("Failed to restore BOs of pasid 0x%x, retry after %d ms\n",
+ 			 p->pasid, PROCESS_BACK_OFF_TIME_MS);
+ 
+ 		ret = queue_delayed_work(kfd_restore_wq, &p->restore_work,
+@@ -1344,9 +1344,9 @@ static void restore_process_worker(struct work_struct *work)
+ 	ret = kfd_process_restore_queues(p);
+ 	trace_kfd_restore_process_worker_end(p,	ret ? "Failed" : "Success");
+ 	if (!ret)
+-		pr_info("Finished restoring pasid %d\n", p->pasid);
++		pr_debug("Finished restoring pasid 0x%x\n", p->pasid);
+ 	else
+-		pr_err("Failed to restore queues of pasid %d\n", p->pasid);
++		pr_err("Failed to restore queues of pasid 0x%x\n", p->pasid);
+ }
+ 
+ void kfd_suspend_all_processes(void)
+@@ -1360,7 +1360,7 @@ void kfd_suspend_all_processes(void)
+ 		cancel_delayed_work_sync(&p->restore_work);
+ 
+ 		if (kfd_process_evict_queues(p))
+-			pr_err("Failed to suspend process %d\n", p->pasid);
++			pr_err("Failed to suspend process 0x%x\n", p->pasid);
+ 		dma_fence_signal(p->ef);
+ 		dma_fence_put(p->ef);
+ 		p->ef = NULL;
+@@ -1443,7 +1443,7 @@ int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data)
+ 	int idx = srcu_read_lock(&kfd_processes_srcu);
+ 
+ 	hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {
+-		seq_printf(m, "Process %d PASID %d:\n",
++		seq_printf(m, "Process %d PASID 0x%x:\n",
+ 			   p->lead_thread->tgid, p->pasid);
+ 
+ 		mutex_lock(&p->mutex);
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+index a594945097a3..227fb0ec8115 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+@@ -53,7 +53,7 @@ static int find_available_queue_slot(struct process_queue_manager *pqm,
+ 	pr_debug("The new slot id %lu\n", found);
+ 
+ 	if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
+-		pr_info("Cannot open more queues for process with pasid %d\n",
++		pr_info("Cannot open more queues for process with pasid 0x%x\n",
+ 				pqm->process->pasid);
+ 		return -ENOMEM;
+ 	}
+@@ -298,7 +298,7 @@ int pqm_create_queue(struct process_queue_manager *pqm,
+ 	}
+ 
+ 	if (retval != 0) {
+-		pr_err("Pasid %d DQM create queue %d failed. ret %d\n",
++		pr_err("Pasid 0x%x DQM create queue %d failed. ret %d\n",
+ 			pqm->process->pasid, type, retval);
+ 		goto err_create_queue;
+ 	}
+@@ -378,7 +378,7 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid)
+ 		dqm = pqn->q->device->dqm;
+ 		retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q);
+ 		if (retval) {
+-			pr_err("Pasid %d destroy queue %d failed, ret %d\n",
++			pr_err("Pasid 0x%x destroy queue %d failed, ret %d\n",
+ 				pqm->process->pasid,
+ 				pqn->q->properties.queue_id, retval);
+ 			if (retval != -ETIME)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3972-drm-amdkfd-Record-vmid-pasid-mapping-in-the-driver-f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3972-drm-amdkfd-Record-vmid-pasid-mapping-in-the-driver-f.patch
new file mode 100644
index 00000000..71130291
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3972-drm-amdkfd-Record-vmid-pasid-mapping-in-the-driver-f.patch
@@ -0,0 +1,113 @@
+From 45839c019bcc30a3af67f4df0bf12d090fdc25b2 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 25 Sep 2019 23:49:46 -0400
+Subject: [PATCH 3972/4256] drm/amdkfd: Record vmid pasid mapping in the driver
+ for non HWS mode
+
+This makes possible the vmid pasid mapping query through software.
+
+Change-Id: Ib539aae277a227cc39f6469ae23c46c4d289b87b
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ .../drm/amd/amdkfd/kfd_device_queue_manager.c | 33 ++++++++++++-------
+ .../drm/amd/amdkfd/kfd_device_queue_manager.h |  4 ++-
+ 2 files changed, 24 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 10e49a9cbcfa..437a9d28b5c2 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -224,20 +224,30 @@ static int allocate_vmid(struct device_queue_manager *dqm,
+ 			struct qcm_process_device *qpd,
+ 			struct queue *q)
+ {
+-	int bit, allocated_vmid;
++	int allocated_vmid = -1, i;
+ 
+-	if (dqm->vmid_bitmap == 0)
+-		return -ENOMEM;
++	for (i = dqm->dev->vm_info.first_vmid_kfd;
++			i <= dqm->dev->vm_info.last_vmid_kfd; i++) {
++		if (!dqm->vmid_pasid[i]) {
++			allocated_vmid = i;
++			break;
++		}
++	}
++
++	if (allocated_vmid < 0) {
++		pr_err("no more vmid to allocate\n");
++		return -ENOSPC;
++	}
++
++	pr_debug("vmid allocated: %d\n", allocated_vmid);
++
++	dqm->vmid_pasid[allocated_vmid] = q->process->pasid;
+ 
+-	bit = ffs(dqm->vmid_bitmap) - 1;
+-	dqm->vmid_bitmap &= ~(1 << bit);
++	set_pasid_vmid_mapping(dqm, q->process->pasid, allocated_vmid);
+ 
+-	allocated_vmid = bit + dqm->dev->vm_info.first_vmid_kfd;
+-	pr_debug("vmid allocation %d\n", allocated_vmid);
+ 	qpd->vmid = allocated_vmid;
+ 	q->properties.vmid = allocated_vmid;
+ 
+-	set_pasid_vmid_mapping(dqm, q->process->pasid, q->properties.vmid);
+ 	program_sh_mem_settings(dqm, qpd);
+ 
+ 	/* qpd->page_table_base is set earlier when register_process()
+@@ -278,8 +288,6 @@ static void deallocate_vmid(struct device_queue_manager *dqm,
+ 				struct qcm_process_device *qpd,
+ 				struct queue *q)
+ {
+-	int bit = qpd->vmid - dqm->dev->vm_info.first_vmid_kfd;
+-
+ 	/* On GFX v7, CP doesn't flush TC at dequeue */
+ 	if (q->device->device_info->asic_family == CHIP_HAWAII)
+ 		if (flush_texture_cache_nocpsch(q->device, qpd))
+@@ -289,8 +297,8 @@ static void deallocate_vmid(struct device_queue_manager *dqm,
+ 
+ 	/* Release the vmid mapping */
+ 	set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
++	dqm->vmid_pasid[qpd->vmid] = 0;
+ 
+-	dqm->vmid_bitmap |= (1 << bit);
+ 	qpd->vmid = 0;
+ 	q->properties.vmid = 0;
+ }
+@@ -1007,7 +1015,8 @@ static int initialize_nocpsch(struct device_queue_manager *dqm)
+ 				dqm->allocated_queues[pipe] |= 1 << queue;
+ 	}
+ 
+-	dqm->vmid_bitmap = (1 << dqm->dev->vm_info.vmid_num_kfd) - 1;
++	memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid));
++
+ 	dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
+  	dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
+ 
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+index eed8f950b663..48e3b89e27c3 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+@@ -33,6 +33,7 @@
+ 
+ 
+ #define USE_DEFAULT_GRACE_PERIOD 0xffffffff
++#define VMID_NUM 16
+ 
+ struct device_process_node {
+ 	struct qcm_process_device *qpd;
+@@ -188,7 +189,8 @@ struct device_queue_manager {
+ 	unsigned int		*allocated_queues;
+ 	uint64_t		sdma_bitmap;
+ 	uint64_t		xgmi_sdma_bitmap;
+-	unsigned int		vmid_bitmap;
++	/* the pasid mapping for each kfd vmid */
++	uint16_t		vmid_pasid[VMID_NUM];
+ 	uint64_t		pipelines_addr;
+ 	struct kfd_mem_obj	*pipeline_mem;
+ 	uint64_t		fence_gpu_addr;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3973-drm-amdkfd-Query-vmid-pasid-mapping-through-stored-i.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3973-drm-amdkfd-Query-vmid-pasid-mapping-through-stored-i.patch
new file mode 100644
index 00000000..dd41e462
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3973-drm-amdkfd-Query-vmid-pasid-mapping-through-stored-i.patch
@@ -0,0 +1,36 @@
+From b41ffc6180649d02c93de7bf15c81f44c2a56ee4 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 25 Sep 2019 17:06:12 -0400
+Subject: [PATCH 3973/4256] drm/amdkfd: Query vmid pasid mapping through stored
+ info for non HWS
+
+Because we record the mapping under non HWS mode in the software,
+we can query pasid through vmid using the stored mapping instead of
+reading from ATC registers.
+
+This also prepares for the defeatured ATC block in future ASICs.
+
+Change-Id: I781cb9d30dc0cc93379908ff1cf8da798bb26f13
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
+index ab8a695c4a3c..ee82632cfed4 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
+@@ -58,8 +58,7 @@ static bool event_interrupt_isr_v9(struct kfd_dev *dev,
+ 		memcpy(patched_ihre, ih_ring_entry,
+ 				dev->device_info->ih_ring_entry_size);
+ 
+-		pasid = dev->kfd2kgd->get_atc_vmid_pasid_mapping_pasid(
+-				dev->kgd, vmid);
++		pasid = dev->dqm->vmid_pasid[vmid];
+ 
+ 		/* Patch the pasid field */
+ 		patched_ihre[3] = cpu_to_le32((le32_to_cpu(patched_ihre[3])
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3974-drm-amdkfd-Eliminate-get_atc_vmid_pasid_mapping_vali.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3974-drm-amdkfd-Eliminate-get_atc_vmid_pasid_mapping_vali.patch
new file mode 100644
index 00000000..d95209c7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3974-drm-amdkfd-Eliminate-get_atc_vmid_pasid_mapping_vali.patch
@@ -0,0 +1,442 @@
+From b5b576539fb063762c79c45e9f9863353c8b8125 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 25 Sep 2019 23:57:30 -0400
+Subject: [PATCH 3974/4256] drm/amdkfd: Eliminate
+ get_atc_vmid_pasid_mapping_valid
+
+get_atc_vmid_pasid_mapping_valid() is very similar to
+get_atc_vmid_pasid_mapping_pasid(), so they can be merged into a new
+function get_atc_vmid_pasid_mapping_info() to reduce register access
+times. More importantly, getting the PASID and the valid bit atomically
+with a single read fixes some potential race conditions where the
+mapping changes between the two reads.
+
+Change-Id: I255ebf2629012400b07fe6a69c3d075cfd46612e
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c   |  6 +--
+ .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c    | 49 +++++++------------
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 28 ++++-------
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 32 ++++--------
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 44 +++++++----------
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h |  6 +--
+ .../gpu/drm/amd/amdkfd/cik_event_interrupt.c  |  8 +--
+ drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c       | 16 +++---
+ .../gpu/drm/amd/include/kgd_kfd_interface.h   |  8 ++-
+ 9 files changed, 75 insertions(+), 122 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+index 75a351739168..f0b19f20d1af 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+@@ -279,10 +279,8 @@ static const struct kfd2kgd_calls kfd2kgd = {
+ 	.address_watch_execute = kgd_gfx_v9_address_watch_execute,
+ 	.wave_control_execute = kgd_gfx_v9_wave_control_execute,
+ 	.address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
+-	.get_atc_vmid_pasid_mapping_pasid =
+-			kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid,
+-	.get_atc_vmid_pasid_mapping_valid =
+-			kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid,
++	.get_atc_vmid_pasid_mapping_info =
++			kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
+ 	.get_tile_config = kgd_gfx_v9_get_tile_config,
+ 	.set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
+ 	.invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+index 3ccaa088cafe..9bd81e1c3a46 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+@@ -99,10 +99,8 @@ static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
+ 					unsigned int watch_point_id,
+ 					unsigned int reg_offset);
+ 
+-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
+-		uint8_t vmid);
+-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
+-		uint8_t vmid);
++static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
++					uint8_t vmid, uint16_t *p_pasid);
+ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
+ 		uint64_t page_table_base);
+ static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
+@@ -156,10 +154,8 @@ static const struct kfd2kgd_calls kfd2kgd = {
+ 	.address_watch_execute = kgd_address_watch_execute,
+ 	.wave_control_execute = kgd_wave_control_execute,
+ 	.address_watch_get_offset = kgd_address_watch_get_offset,
+-	.get_atc_vmid_pasid_mapping_pasid =
+-			get_atc_vmid_pasid_mapping_pasid,
+-	.get_atc_vmid_pasid_mapping_valid =
+-			get_atc_vmid_pasid_mapping_valid,
++	.get_atc_vmid_pasid_mapping_info =
++			get_atc_vmid_pasid_mapping_info,
+ 	.get_tile_config = amdgpu_amdkfd_get_tile_config,
+ 	.set_vm_context_page_table_base = set_vm_context_page_table_base,
+ 	.invalidate_tlbs = invalidate_tlbs,
+@@ -776,26 +772,17 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ 	return 0;
+ }
+ 
+-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
+-							uint8_t vmid)
++static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
++					uint8_t vmid, uint16_t *p_pasid)
+ {
+-	uint32_t reg;
++	uint32_t value;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
+ 
+-	reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
++	value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
+ 		     + vmid);
+-	return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
+-}
+-
+-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
+-								uint8_t vmid)
+-{
+-	uint32_t reg;
+-	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
++	*p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
+ 
+-	reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
+-		     + vmid);
+-	return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
++	return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
+ }
+ 
+ static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid)
+@@ -827,6 +814,8 @@ static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
+ 	int vmid;
++	uint16_t queried_pasid;
++	bool ret;
+ 	struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
+ 
+ 	if (amdgpu_emu_mode == 0 && ring->sched.ready)
+@@ -835,13 +824,13 @@ static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
+ 	for (vmid = 0; vmid < 16; vmid++) {
+ 		if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
+ 			continue;
+-		if (get_atc_vmid_pasid_mapping_valid(kgd, vmid)) {
+-			if (get_atc_vmid_pasid_mapping_pasid(kgd, vmid)
+-				== pasid) {
+-				amdgpu_gmc_flush_gpu_tlb(adev, vmid,
+-						AMDGPU_GFXHUB_0, 0);
+-				break;
+-			}
++
++		ret = get_atc_vmid_pasid_mapping_info(kgd, vmid,
++				&queried_pasid);
++		if (ret	&& queried_pasid == pasid) {
++			amdgpu_gmc_flush_gpu_tlb(adev, vmid,
++					AMDGPU_GFXHUB_0, 0);
++			break;
+ 		}
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+index dd7548e9932b..ac811361246d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+@@ -136,9 +136,8 @@ static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
+ 					unsigned int watch_point_id,
+ 					unsigned int reg_offset);
+ 
+-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid);
+-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
+-							uint8_t vmid);
++static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
++					uint8_t vmid, uint16_t *p_pasid);
+ 
+ static void set_scratch_backing_va(struct kgd_dev *kgd,
+ 					uint64_t va, uint32_t vmid);
+@@ -189,8 +188,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
+ 	.address_watch_execute = kgd_address_watch_execute,
+ 	.wave_control_execute = kgd_wave_control_execute,
+ 	.address_watch_get_offset = kgd_address_watch_get_offset,
+-	.get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid,
+-	.get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid,
++	.get_atc_vmid_pasid_mapping_info = get_atc_vmid_pasid_mapping_info,
+ 	.set_scratch_backing_va = set_scratch_backing_va,
+ 	.get_tile_config = get_tile_config,
+ 	.set_vm_context_page_table_base = set_vm_context_page_table_base,
+@@ -756,24 +754,16 @@ static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
+ 	return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
+ }
+ 
+-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
+-							uint8_t vmid)
++static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
++					uint8_t vmid, uint16_t *p_pasid)
+ {
+-	uint32_t reg;
++	uint32_t value;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
+ 
+-	reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
+-	return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
+-}
+-
+-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
+-								uint8_t vmid)
+-{
+-	uint32_t reg;
+-	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
++	value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
++	*p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
+ 
+-	reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
+-	return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
++	return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
+ }
+ 
+ static void set_scratch_backing_va(struct kgd_dev *kgd,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+index f12ac78707b4..b7f0d594ec7b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+@@ -99,10 +99,8 @@ static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
+ 					unsigned int watch_point_id,
+ 					unsigned int reg_offset);
+ 
+-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
+-		uint8_t vmid);
+-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
+-		uint8_t vmid);
++static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
++					uint8_t vmid, uint16_t *p_pasid);
+ static void set_scratch_backing_va(struct kgd_dev *kgd,
+ 					uint64_t va, uint32_t vmid);
+ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
+@@ -151,10 +149,8 @@ static const struct kfd2kgd_calls kfd2kgd = {
+ 	.address_watch_execute = kgd_address_watch_execute,
+ 	.wave_control_execute = kgd_wave_control_execute,
+ 	.address_watch_get_offset = kgd_address_watch_get_offset,
+-	.get_atc_vmid_pasid_mapping_pasid =
+-			get_atc_vmid_pasid_mapping_pasid,
+-	.get_atc_vmid_pasid_mapping_valid =
+-			get_atc_vmid_pasid_mapping_valid,
++	.get_atc_vmid_pasid_mapping_info =
++			get_atc_vmid_pasid_mapping_info,
+ 	.set_scratch_backing_va = set_scratch_backing_va,
+ 	.get_tile_config = get_tile_config,
+ 	.set_vm_context_page_table_base = set_vm_context_page_table_base,
+@@ -677,24 +673,16 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ 	return 0;
+ }
+ 
+-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
+-							uint8_t vmid)
++static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
++					uint8_t vmid, uint16_t *p_pasid)
+ {
+-	uint32_t reg;
++	uint32_t value;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
+ 
+-	reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
+-	return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
+-}
+-
+-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
+-								uint8_t vmid)
+-{
+-	uint32_t reg;
+-	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
++	value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
++	*p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
+ 
+-	reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
+-	return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
++	return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
+ }
+ 
+ static int kgd_address_watch_disable(struct kgd_dev *kgd)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+index c6f27ad29d61..04448869abff 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+@@ -630,26 +630,17 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ 	return 0;
+ }
+ 
+-bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
+-							uint8_t vmid)
++bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
++					uint8_t vmid, uint16_t *p_pasid)
+ {
+-	uint32_t reg;
++	uint32_t value;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
+ 
+-	reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
++	value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
+ 		     + vmid);
+-	return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
+-}
+-
+-uint16_t kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
+-								uint8_t vmid)
+-{
+-	uint32_t reg;
+-	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
++	*p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
+ 
+-	reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
+-		     + vmid);
+-	return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
++	return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
+ }
+ 
+ static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid,
+@@ -684,6 +675,8 @@ int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
+ 	int vmid, i;
++	uint16_t queried_pasid;
++	bool ret;
+ 	struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
+ 	uint32_t flush_type = 0;
+ 
+@@ -699,14 +692,13 @@ int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
+ 	for (vmid = 0; vmid < 16; vmid++) {
+ 		if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
+ 			continue;
+-		if (kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(kgd, vmid)) {
+-			if (kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(kgd, vmid)
+-				== pasid) {
+-				for (i = 0; i < adev->num_vmhubs; i++)
+-					amdgpu_gmc_flush_gpu_tlb(adev, vmid,
+-							i, flush_type);
+-				break;
+-			}
++		ret = kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(kgd, vmid,
++				&queried_pasid);
++		if (ret && queried_pasid == pasid) {
++			for (i = 0; i < adev->num_vmhubs; i++)
++				amdgpu_gmc_flush_gpu_tlb(adev, vmid,
++						i, flush_type);
++			break;
+ 		}
+ 	}
+ 
+@@ -1040,10 +1032,8 @@ static const struct kfd2kgd_calls kfd2kgd = {
+ 	.address_watch_execute = kgd_gfx_v9_address_watch_execute,
+ 	.wave_control_execute = kgd_gfx_v9_wave_control_execute,
+ 	.address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
+-	.get_atc_vmid_pasid_mapping_pasid =
+-			kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid,
+-	.get_atc_vmid_pasid_mapping_valid =
+-			kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid,
++	.get_atc_vmid_pasid_mapping_info =
++			kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
+ 	.get_tile_config = kgd_gfx_v9_get_tile_config,
+ 	.set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
+ 	.invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
+index a30e36341502..7611ba466aa4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
+@@ -55,10 +55,8 @@ uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd,
+ 					unsigned int watch_point_id,
+ 					unsigned int reg_offset);
+ 
+-bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
+-		uint8_t vmid);
+-uint16_t kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
+-		uint8_t vmid);
++bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
++					uint8_t vmid, uint16_t *p_pasid);
+ void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
+ 		uint64_t page_table_base);
+ int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
+diff --git a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
+index 177d1e5329a5..9f59ba93cfe0 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
++++ b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
+@@ -33,7 +33,9 @@ static bool cik_event_interrupt_isr(struct kfd_dev *dev,
+ 	const struct cik_ih_ring_entry *ihre =
+ 			(const struct cik_ih_ring_entry *)ih_ring_entry;
+ 	const struct kfd2kgd_calls *f2g = dev->kfd2kgd;
+-	unsigned int vmid, pasid;
++	unsigned int vmid;
++	uint16_t pasid;
++	bool ret;
+ 
+ 	/* This workaround is due to HW/FW limitation on Hawaii that
+ 	 * VMID and PASID are not written into ih_ring_entry
+@@ -48,13 +50,13 @@ static bool cik_event_interrupt_isr(struct kfd_dev *dev,
+ 		*tmp_ihre = *ihre;
+ 
+ 		vmid = f2g->read_vmid_from_vmfault_reg(dev->kgd);
+-		pasid = f2g->get_atc_vmid_pasid_mapping_pasid(dev->kgd, vmid);
++		ret = f2g->get_atc_vmid_pasid_mapping_info(dev->kgd, vmid, &pasid);
+ 
+ 		tmp_ihre->ring_id &= 0x000000ff;
+ 		tmp_ihre->ring_id |= vmid << 8;
+ 		tmp_ihre->ring_id |= pasid << 16;
+ 
+-		return (pasid != 0) &&
++		return ret && (pasid != 0) &&
+ 			vmid >= dev->vm_info.first_vmid_kfd &&
+ 			vmid <= dev->vm_info.last_vmid_kfd;
+ 	}
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
+index 492951cad143..1eb0c2bedcd9 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
+@@ -775,6 +775,7 @@ int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p)
+ {
+ 	int status = 0;
+ 	unsigned int vmid;
++	uint16_t queried_pasid;
+ 	union SQ_CMD_BITS reg_sq_cmd;
+ 	union GRBM_GFX_INDEX_BITS reg_gfx_index;
+ 	struct kfd_process_device *pdd;
+@@ -796,14 +797,13 @@ int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p)
+ 	 */
+ 
+ 	for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) {
+-		if (dev->kfd2kgd->get_atc_vmid_pasid_mapping_valid
+-				(dev->kgd, vmid)) {
+-			if (dev->kfd2kgd->get_atc_vmid_pasid_mapping_pasid
+-					(dev->kgd, vmid) == p->pasid) {
+-				pr_debug("Killing wave fronts of vmid %d and pasid 0x%x\n",
+-						vmid, p->pasid);
+-				break;
+-			}
++		status = dev->kfd2kgd->get_atc_vmid_pasid_mapping_info
++				(dev->kgd, vmid, &queried_pasid);
++
++		if (status && queried_pasid == p->pasid) {
++			pr_debug("Killing wave fronts of vmid %d and pasid 0x%x\n",
++					vmid, p->pasid);
++			break;
+ 		}
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+index 57cf9aabedb4..db00c2ec9277 100644
+--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
++++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+@@ -299,12 +299,10 @@ struct kfd2kgd_calls {
+ 	uint32_t (*address_watch_get_offset)(struct kgd_dev *kgd,
+ 					unsigned int watch_point_id,
+ 					unsigned int reg_offset);
+-	bool (*get_atc_vmid_pasid_mapping_valid)(
++	bool (*get_atc_vmid_pasid_mapping_info)(
+ 					struct kgd_dev *kgd,
+-					uint8_t vmid);
+-	uint16_t (*get_atc_vmid_pasid_mapping_pasid)(
+-					struct kgd_dev *kgd,
+-					uint8_t vmid);
++					uint8_t vmid,
++					uint16_t *p_pasid);
+ 
+ 	/* No longer needed from GFXv9 onward. The scratch base address is
+ 	 * passed to the shader by the CP. It's the user mode driver's
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3975-drm-amdgpu-Export-setup_vm_pt_regs-logic-for-gfxhub-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3975-drm-amdgpu-Export-setup_vm_pt_regs-logic-for-gfxhub-.patch
new file mode 100644
index 00000000..75d54bb5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3975-drm-amdgpu-Export-setup_vm_pt_regs-logic-for-gfxhub-.patch
@@ -0,0 +1,69 @@
+From d02e0ed0789df185c8069a2fcaf38aed86636e94 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Tue, 24 Sep 2019 17:08:30 -0400
+Subject: [PATCH 3975/4256] drm/amdgpu: Export setup_vm_pt_regs() logic for
+ gfxhub 2.0
+
+The KFD code will call this function later.
+
+Change-Id: I88a53368cdee719b2c75393e5cdbd8290584548e
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 20 ++++++++++++--------
+ drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.h |  2 ++
+ 2 files changed, 14 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+index a9238735d361..b601c6740ef5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+@@ -46,21 +46,25 @@ u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev)
+ 	return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;
+ }
+ 
+-static void gfxhub_v2_0_init_gart_pt_regs(struct amdgpu_device *adev)
++void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
++				uint64_t page_table_base)
+ {
+-	uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
++	/* two registers distance between mmGCVM_CONTEXT0_* to mmGCVM_CONTEXT1_* */
++	int offset = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
++			- mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
+ 
++	WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
++				offset * vmid, lower_32_bits(page_table_base));
+ 
+-	WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+-		     lower_32_bits(value));
+-
+-	WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+-		     upper_32_bits(value));
++	WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
++				offset * vmid, upper_32_bits(page_table_base));
+ }
+ 
+ static void gfxhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
+ {
+-	gfxhub_v2_0_init_gart_pt_regs(adev);
++	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
++
++	gfxhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
+ 
+ 	WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+ 		     (u32)(adev->gmc.gart_start >> 12));
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.h b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.h
+index 06807940748b..392b8cd94fc0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.h
++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.h
+@@ -31,5 +31,7 @@ void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,
+ 					  bool value);
+ void gfxhub_v2_0_init(struct amdgpu_device *adev);
+ u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev);
++void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
++				uint64_t page_table_base);
+ 
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3976-drm-amdkfd-Use-setup_vm_pt_regs-function-from-base-d.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3976-drm-amdkfd-Use-setup_vm_pt_regs-function-from-base-d.patch
new file mode 100644
index 00000000..aa5413b9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3976-drm-amdkfd-Use-setup_vm_pt_regs-function-from-base-d.patch
@@ -0,0 +1,71 @@
+From 2c2d797328d0af2442aa7233e71caa725eb1cf10 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 25 Sep 2019 14:01:24 -0400
+Subject: [PATCH 3976/4256] drm/amdkfd: Use setup_vm_pt_regs function from base
+ driver in KFD
+
+This was done on GFX9 previously, now do it for GFX10.
+
+Change-Id: I4442e60534c59bc9526a673559f018ba8058deac
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c    | 23 +++----------------
+ 1 file changed, 3 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+index 9bd81e1c3a46..57ff698f51bb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+@@ -43,6 +43,7 @@
+ #include "v10_structs.h"
+ #include "nv.h"
+ #include "nvd.h"
++#include "gfxhub_v2_0.h"
+ 
+ enum hqd_dequeue_request_type {
+ 	NO_ACTION = 0,
+@@ -248,11 +249,6 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
+ 			ATC_VMID0_PASID_MAPPING__VALID_MASK;
+ 
+ 	pr_debug("pasid 0x%x vmid %d, reg value %x\n", pasid, vmid, pasid_mapping);
+-	/*
+-	 * need to do this twice, once for gfx and once for mmhub
+-	 * for ATC add 16 to VMID for mmhub, for IH different registers.
+-	 * ATC_VMID0..15 registers are separate from ATC_VMID16..31.
+-	 */
+ 
+ 	pr_debug("ATHUB, reg %x\n",SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid);
+ 	WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
+@@ -900,7 +896,6 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
+ 		uint64_t page_table_base)
+ {
+ 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+-	uint64_t base = page_table_base | AMDGPU_PTE_VALID;
+ 
+ 	if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
+ 		pr_err("trying to set page table base for wrong VMID %u\n",
+@@ -908,18 +903,6 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
+ 		return;
+ 	}
+ 
+-	/* TODO: take advantage of per-process address space size. For
+-	 * now, all processes share the same address space size, like
+-	 * on GFX8 and older.
+-	 */
+-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0);
+-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0);
+-
+-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2),
+-			lower_32_bits(adev->vm_manager.max_pfn - 1));
+-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2),
+-			upper_32_bits(adev->vm_manager.max_pfn - 1));
+-
+-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base));
+-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base));
++	/* SDMA is on gfxhub as well for Navi1* series */
++	gfxhub_v2_0_setup_vm_pt_regs(adev, vmid, page_table_base);
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3977-drm-amdkfd-Fix-race-in-gfx10-context-restore-handler.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3977-drm-amdkfd-Fix-race-in-gfx10-context-restore-handler.patch
new file mode 100644
index 00000000..c32a5c84
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3977-drm-amdkfd-Fix-race-in-gfx10-context-restore-handler.patch
@@ -0,0 +1,205 @@
+From 5406262808b235a2532f6a4a85c34dff3131b24a Mon Sep 17 00:00:00 2001
+From: Jay Cornwall <jay.cornwall@amd.com>
+Date: Wed, 25 Sep 2019 17:05:01 -0500
+Subject: [PATCH 3977/4256] drm/amdkfd: Fix race in gfx10 context restore
+ handler
+
+Missing synchronization with VGPR restore leads to intermittent
+VGPR trashing in the user shader.
+
+Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
+Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
+---
+ .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h    | 139 +++++++++---------
+ .../amd/amdkfd/cwsr_trap_handler_gfx10.asm    |   1 +
+ 2 files changed, 71 insertions(+), 69 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+index 901fe3590165..d3400da6ab64 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+@@ -905,7 +905,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
+ 	0x7a5d0000, 0x807c817c,
+ 	0x807aff7a, 0x00000080,
+ 	0xbf0a717c, 0xbf85fff8,
+-	0xbf820141, 0xbef4037e,
++	0xbf820142, 0xbef4037e,
+ 	0x8775ff7f, 0x0000ffff,
+ 	0x8875ff75, 0x00040000,
+ 	0xbef60380, 0xbef703ff,
+@@ -967,7 +967,7 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
+ 	0x725d0000, 0xe0304080,
+ 	0x725d0100, 0xe0304100,
+ 	0x725d0200, 0xe0304180,
+-	0x725d0300, 0xbf820031,
++	0x725d0300, 0xbf820032,
+ 	0xbef603ff, 0x01000000,
+ 	0xbef20378, 0x8078ff78,
+ 	0x00000400, 0xbefc0384,
+@@ -992,83 +992,84 @@ static const uint32_t cwsr_trap_gfx10_hex[] = {
+ 	0x725d0000, 0xe0304100,
+ 	0x725d0100, 0xe0304200,
+ 	0x725d0200, 0xe0304300,
+-	0x725d0300, 0xb9782a05,
+-	0x80788178, 0x907c9973,
+-	0x877c817c, 0xbf06817c,
+-	0xbf850002, 0x8f788978,
+-	0xbf820001, 0x8f788a78,
+-	0xb9721e06, 0x8f728a72,
+-	0x80787278, 0x8078ff78,
+-	0x00000200, 0x80f8ff78,
+-	0x00000050, 0xbef603ff,
+-	0x01000000, 0xbefc03ff,
+-	0x0000006c, 0x80f89078,
+-	0xf429003a, 0xf0000000,
+-	0xbf8cc07f, 0x80fc847c,
+-	0xbf800000, 0xbe803100,
+-	0xbe823102, 0x80f8a078,
+-	0xf42d003a, 0xf0000000,
+-	0xbf8cc07f, 0x80fc887c,
+-	0xbf800000, 0xbe803100,
+-	0xbe823102, 0xbe843104,
+-	0xbe863106, 0x80f8c078,
+-	0xf431003a, 0xf0000000,
+-	0xbf8cc07f, 0x80fc907c,
+-	0xbf800000, 0xbe803100,
+-	0xbe823102, 0xbe843104,
+-	0xbe863106, 0xbe883108,
+-	0xbe8a310a, 0xbe8c310c,
+-	0xbe8e310e, 0xbf06807c,
+-	0xbf84fff0, 0xb9782a05,
+-	0x80788178, 0x907c9973,
+-	0x877c817c, 0xbf06817c,
+-	0xbf850002, 0x8f788978,
+-	0xbf820001, 0x8f788a78,
+-	0xb9721e06, 0x8f728a72,
+-	0x80787278, 0x8078ff78,
+-	0x00000200, 0xbef603ff,
+-	0x01000000, 0xf4211bfa,
++	0x725d0300, 0xbf8c3f70,
++	0xb9782a05, 0x80788178,
++	0x907c9973, 0x877c817c,
++	0xbf06817c, 0xbf850002,
++	0x8f788978, 0xbf820001,
++	0x8f788a78, 0xb9721e06,
++	0x8f728a72, 0x80787278,
++	0x8078ff78, 0x00000200,
++	0x80f8ff78, 0x00000050,
++	0xbef603ff, 0x01000000,
++	0xbefc03ff, 0x0000006c,
++	0x80f89078, 0xf429003a,
++	0xf0000000, 0xbf8cc07f,
++	0x80fc847c, 0xbf800000,
++	0xbe803100, 0xbe823102,
++	0x80f8a078, 0xf42d003a,
++	0xf0000000, 0xbf8cc07f,
++	0x80fc887c, 0xbf800000,
++	0xbe803100, 0xbe823102,
++	0xbe843104, 0xbe863106,
++	0x80f8c078, 0xf431003a,
++	0xf0000000, 0xbf8cc07f,
++	0x80fc907c, 0xbf800000,
++	0xbe803100, 0xbe823102,
++	0xbe843104, 0xbe863106,
++	0xbe883108, 0xbe8a310a,
++	0xbe8c310c, 0xbe8e310e,
++	0xbf06807c, 0xbf84fff0,
++	0xb9782a05, 0x80788178,
++	0x907c9973, 0x877c817c,
++	0xbf06817c, 0xbf850002,
++	0x8f788978, 0xbf820001,
++	0x8f788a78, 0xb9721e06,
++	0x8f728a72, 0x80787278,
++	0x8078ff78, 0x00000200,
++	0xbef603ff, 0x01000000,
++	0xf4211bfa, 0xf0000000,
++	0x80788478, 0xf4211b3a,
+ 	0xf0000000, 0x80788478,
+-	0xf4211b3a, 0xf0000000,
+-	0x80788478, 0xf4211b7a,
++	0xf4211b7a, 0xf0000000,
++	0x80788478, 0xf4211eba,
+ 	0xf0000000, 0x80788478,
+-	0xf4211eba, 0xf0000000,
+-	0x80788478, 0xf4211efa,
++	0xf4211efa, 0xf0000000,
++	0x80788478, 0xf4211c3a,
+ 	0xf0000000, 0x80788478,
+-	0xf4211c3a, 0xf0000000,
+-	0x80788478, 0xf4211c7a,
++	0xf4211c7a, 0xf0000000,
++	0x80788478, 0xf4211e7a,
+ 	0xf0000000, 0x80788478,
+-	0xf4211e7a, 0xf0000000,
+-	0x80788478, 0xf4211cfa,
++	0xf4211cfa, 0xf0000000,
++	0x80788478, 0xf4211bba,
+ 	0xf0000000, 0x80788478,
++	0xbf8cc07f, 0xb9eef814,
+ 	0xf4211bba, 0xf0000000,
+ 	0x80788478, 0xbf8cc07f,
+-	0xb9eef814, 0xf4211bba,
+-	0xf0000000, 0x80788478,
+-	0xbf8cc07f, 0xb9eef815,
+-	0xbef2036d, 0x876dff72,
+-	0x0000ffff, 0xbefc036f,
+-	0xbefe037a, 0xbeff037b,
+-	0x876f71ff, 0x000003ff,
+-	0xb9ef4803, 0xb9f9f816,
+-	0x876f71ff, 0xfffff800,
+-	0x906f8b6f, 0xb9efa2c3,
+-	0xb9f3f801, 0x876fff72,
+-	0xfc000000, 0x906f9a6f,
+-	0x8f6f906f, 0xbef30380,
++	0xb9eef815, 0xbef2036d,
++	0x876dff72, 0x0000ffff,
++	0xbefc036f, 0xbefe037a,
++	0xbeff037b, 0x876f71ff,
++	0x000003ff, 0xb9ef4803,
++	0xb9f9f816, 0x876f71ff,
++	0xfffff800, 0x906f8b6f,
++	0xb9efa2c3, 0xb9f3f801,
++	0x876fff72, 0xfc000000,
++	0x906f9a6f, 0x8f6f906f,
++	0xbef30380, 0x88736f73,
++	0x876fff72, 0x02000000,
++	0x906f996f, 0x8f6f8f6f,
+ 	0x88736f73, 0x876fff72,
+-	0x02000000, 0x906f996f,
+-	0x8f6f8f6f, 0x88736f73,
+-	0x876fff72, 0x01000000,
+-	0x906f986f, 0x8f6f996f,
+-	0x88736f73, 0x876fff70,
+-	0x00800000, 0x906f976f,
+-	0xb9f3f807, 0x87fe7e7e,
+-	0x87ea6a6a, 0xb9f0f802,
+-	0xbf8a0000, 0xbe80226c,
+-	0xbf810000, 0xbf9f0000,
++	0x01000000, 0x906f986f,
++	0x8f6f996f, 0x88736f73,
++	0x876fff70, 0x00800000,
++	0x906f976f, 0xb9f3f807,
++	0x87fe7e7e, 0x87ea6a6a,
++	0xb9f0f802, 0xbf8a0000,
++	0xbe80226c, 0xbf810000,
+ 	0xbf9f0000, 0xbf9f0000,
+ 	0xbf9f0000, 0xbf9f0000,
++	0xbf9f0000, 0x00000000,
+ };
+ static const uint32_t cwsr_trap_arcturus_hex[] = {
+ 	0xbf820001, 0xbf8202c4,
+diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
+index cdaa523ce6be..4433bda2ce25 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
++++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
+@@ -758,6 +758,7 @@ L_RESTORE_V0:
+ 	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256
+ 	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2
+ 	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3
++	s_waitcnt	vmcnt(0)
+ 
+ 	/* restore SGPRs */
+ 	//will be 2+8+16*6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3978-drm-amdkfd-Fix-MQD-size-calculation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3978-drm-amdkfd-Fix-MQD-size-calculation.patch
new file mode 100644
index 00000000..ed8fa89d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3978-drm-amdkfd-Fix-MQD-size-calculation.patch
@@ -0,0 +1,36 @@
+From 422949a500329692033a8700c9b067bc4ddd3b6d Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Fri, 4 Oct 2019 09:28:21 -0500
+Subject: [PATCH 3978/4256] drm/amdkfd: Fix MQD size calculation
+
+On device initialization, a chunk of GTT memory is pre-allocated for
+HIQ and all SDMA queues mqd. The size of this allocation was wrong.
+The correct sdma engine number should be PCIe-optimized SDMA engine
+number plus xgmi SDMA engine number.
+
+Change-Id: Iecd11ae4f5a314591566772aa2a23e1fe4b94275
+Reported-by: Jonathan Kim <Jonathan.Kim@amd.com>
+Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 437a9d28b5c2..d8b54ebe8359 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -1840,7 +1840,8 @@ static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm)
+ 	struct kfd_dev *dev = dqm->dev;
+ 	struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd;
+ 	uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size *
+-		dev->device_info->num_sdma_engines *
++		(dev->device_info->num_sdma_engines +
++		dev->device_info->num_xgmi_sdma_engines) *
+ 		dev->device_info->num_sdma_queues_per_engine +
+ 		dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3979-drm-amdkfd-Print-more-sdma-engine-hqds-in-debug-fs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3979-drm-amdkfd-Print-more-sdma-engine-hqds-in-debug-fs.patch
new file mode 100644
index 00000000..ffea60da
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3979-drm-amdkfd-Print-more-sdma-engine-hqds-in-debug-fs.patch
@@ -0,0 +1,34 @@
+From 2b975fee915f259d86c08fe46fcf8db9b35643bc Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Fri, 4 Oct 2019 09:34:29 -0500
+Subject: [PATCH 3979/4256] drm/amdkfd: Print more sdma engine hqds in debug fs
+
+Previously only PCIe-optimized SDMA engine hqds were
+exposed in debug fs. Print all SDMA engine hqds.
+
+Change-Id: I03756fc0fa99169d88e265560f505ed186242b02
+Reported-by: Jonathan Kim <Jonathan.Kim@amd.com>
+Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index d8b54ebe8359..0b63740b4c63 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -2408,7 +2408,8 @@ int dqm_debugfs_hqds(struct seq_file *m, void *data)
+ 		}
+ 	}
+ 
+-	for (pipe = 0; pipe < get_num_sdma_engines(dqm); pipe++) {
++	for (pipe = 0; pipe < get_num_sdma_engines(dqm) +
++			get_num_xgmi_sdma_engines(dqm); pipe++) {
+ 		for (queue = 0;
+ 		     queue < dqm->dev->device_info->num_sdma_queues_per_engine;
+ 		     queue++) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3980-drm-amd-powerplay-change-metrics-update-period-from-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3980-drm-amd-powerplay-change-metrics-update-period-from-.patch
new file mode 100644
index 00000000..68722c7c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3980-drm-amd-powerplay-change-metrics-update-period-from-.patch
@@ -0,0 +1,35 @@
+From dbab4ee5d585c821a15989637aaa87722f1e69d7 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Thu, 26 Sep 2019 16:16:41 +0800
+Subject: [PATCH 3980/4256] drm/amd/powerplay: change metrics update period
+ from 1ms to 100ms
+
+v2:
+change period from 10ms to 100ms (typo error)
+
+too high frequence to update mertrics table will cause smu firmware
+error,so change mertrics table update period from 1ms to 100ms
+(navi10, 12, 14)
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 5a34d01f7f7c..f9147655d115 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -547,7 +547,7 @@ static int navi10_get_metrics_table(struct smu_context *smu,
+ 	struct smu_table_context *smu_table= &smu->smu_table;
+ 	int ret = 0;
+ 
+-	if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
++	if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
+ 		ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
+ 				(void *)smu_table->metrics_table, false);
+ 		if (ret) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3981-drm-amd-powerplay-add-sensor-lock-support-for-smu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3981-drm-amd-powerplay-add-sensor-lock-support-for-smu.patch
new file mode 100644
index 00000000..59e032b2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3981-drm-amd-powerplay-add-sensor-lock-support-for-smu.patch
@@ -0,0 +1,118 @@
+From 0fc035a37385c60b7e2df87e29fb517a4f047a88 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Thu, 26 Sep 2019 16:22:13 +0800
+Subject: [PATCH 3981/4256] drm/amd/powerplay: add sensor lock support for smu
+
+when multithreading access sysfs of amdgpu_pm_info at the sametime.
+the swsmu driver cause smu firmware hang.
+
+eg:
+single thread access:
+Message A + Param A ==> right
+Message B + Param B ==> right
+Message C + Param C ==> right
+multithreading access:
+Message A + Param B ==> error
+Message B + Param A ==> error
+Message C + Param C ==> right
+
+the patch will add sensor lock(mutex) to avoid this error.
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     | 2 ++
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c   | 2 ++
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 +
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c     | 2 ++
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c     | 2 ++
+ 5 files changed, 9 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 0237e4d06aca..3d1bfa8ea7c2 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -840,6 +840,8 @@ static int smu_sw_init(void *handle)
+ 	smu->smu_baco.state = SMU_BACO_STATE_EXIT;
+ 	smu->smu_baco.platform_support = false;
+ 
++	mutex_init(&smu->sensor_lock);
++
+ 	smu->watermarks_bitmap = 0;
+ 	smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+ 	smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 1433bd3129a4..37ac01d37ae8 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -1025,6 +1025,7 @@ static int arcturus_read_sensor(struct smu_context *smu,
+ 	if (!data || !size)
+ 		return -EINVAL;
+ 
++	mutex_lock(&smu->sensor_lock);
+ 	switch (sensor) {
+ 	case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
+ 		*(uint32_t *)data = pptable->FanMaximumRpm;
+@@ -1051,6 +1052,7 @@ static int arcturus_read_sensor(struct smu_context *smu,
+ 	default:
+ 		ret = smu_smc_read_sensor(smu, sensor, data, size);
+ 	}
++	mutex_unlock(&smu->sensor_lock);
+ 
+ 	return ret;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 5c898444ff97..bc4b73e0718e 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -350,6 +350,7 @@ struct smu_context
+ 	const struct smu_funcs		*funcs;
+ 	const struct pptable_funcs	*ppt_funcs;
+ 	struct mutex			mutex;
++	struct mutex			sensor_lock;
+ 	uint64_t pool_size;
+ 
+ 	struct smu_table_context	smu_table;
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index f9147655d115..7c0c5bc28fcc 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1386,6 +1386,7 @@ static int navi10_read_sensor(struct smu_context *smu,
+ 	if(!data || !size)
+ 		return -EINVAL;
+ 
++	mutex_lock(&smu->sensor_lock);
+ 	switch (sensor) {
+ 	case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
+ 		*(uint32_t *)data = pptable->FanMaximumRpm;
+@@ -1409,6 +1410,7 @@ static int navi10_read_sensor(struct smu_context *smu,
+ 	default:
+ 		ret = smu_smc_read_sensor(smu, sensor, data, size);
+ 	}
++	mutex_unlock(&smu->sensor_lock);
+ 
+ 	return ret;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index e9ecc3f7aab1..99effde33ac1 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -3017,6 +3017,7 @@ static int vega20_read_sensor(struct smu_context *smu,
+ 	if(!data || !size)
+ 		return -EINVAL;
+ 
++	mutex_lock(&smu->sensor_lock);
+ 	switch (sensor) {
+ 	case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
+ 		*(uint32_t *)data = pptable->FanMaximumRpm;
+@@ -3042,6 +3043,7 @@ static int vega20_read_sensor(struct smu_context *smu,
+ 	default:
+ 		ret = smu_smc_read_sensor(smu, sensor, data, size);
+ 	}
++	mutex_unlock(&smu->sensor_lock);
+ 
+ 	return ret;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3982-drm-amd-amdgpu-add-IH-cg-support-on-soc15-project.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3982-drm-amd-amdgpu-add-IH-cg-support-on-soc15-project.patch
new file mode 100644
index 00000000..b343983b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3982-drm-amd-amdgpu-add-IH-cg-support-on-soc15-project.patch
@@ -0,0 +1,106 @@
+From 861e0f8a4ee3ded149566d22167847a7a21f5e91 Mon Sep 17 00:00:00 2001
+From: Kenneth Feng <kenneth.feng@amd.com>
+Date: Wed, 25 Sep 2019 13:41:35 +0800
+Subject: [PATCH 3982/4256] drm/amd/amdgpu: add IH cg support on soc15 project
+
+enable/disable IH clock gating on soc15 projects.
+
+Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c            |  3 +-
+ drivers/gpu/drm/amd/amdgpu/vega10_ih.c        | 39 +++++++++++++++++++
+ .../include/asic_reg/oss/osssys_4_0_sh_mask.h |  4 ++
+ 3 files changed, 45 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 14c7fc141322..e168d4fa471c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1169,7 +1169,8 @@ static int soc15_common_early_init(void *handle)
+ 			AMD_CG_SUPPORT_SDMA_MGCG |
+ 			AMD_CG_SUPPORT_SDMA_LS |
+ 			AMD_CG_SUPPORT_MC_MGCG |
+-			AMD_CG_SUPPORT_MC_LS;
++			AMD_CG_SUPPORT_MC_LS |
++			AMD_CG_SUPPORT_IH_CG;
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x32;
+ 		break;
+diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+index d7135e5871d4..1aebf7dab4e5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
++++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+@@ -673,10 +673,49 @@ static int vega10_ih_soft_reset(void *handle)
+ 	return 0;
+ }
+ 
++static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev,
++					       bool enable)
++{
++	uint32_t data, def, field_val;
++
++	if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
++		def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
++		field_val = enable ? 0 : 1;
++		/**
++		 * Vega10 does not have IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE
++		 * and IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field.
++		 */
++		if (adev->asic_type > CHIP_VEGA10) {
++			data = REG_SET_FIELD(data, IH_CLK_CTRL,
++				     IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val);
++			data = REG_SET_FIELD(data, IH_CLK_CTRL,
++				     IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val);
++		}
++
++		data = REG_SET_FIELD(data, IH_CLK_CTRL,
++				     DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
++		data = REG_SET_FIELD(data, IH_CLK_CTRL,
++				     OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
++		data = REG_SET_FIELD(data, IH_CLK_CTRL,
++				     LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
++		data = REG_SET_FIELD(data, IH_CLK_CTRL,
++				     DYN_CLK_SOFT_OVERRIDE, field_val);
++		data = REG_SET_FIELD(data, IH_CLK_CTRL,
++				     REG_CLK_SOFT_OVERRIDE, field_val);
++		if (def != data)
++			WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
++	}
++}
++
+ static int vega10_ih_set_clockgating_state(void *handle,
+ 					  enum amd_clockgating_state state)
+ {
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++	vega10_ih_update_clockgating_state(adev,
++				state == AMD_CG_STATE_GATE ? true : false);
+ 	return 0;
++
+ }
+ 
+ static int vega10_ih_set_powergating_state(void *handle,
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h
+index dc9895a684fe..096d878eb1de 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h
+@@ -588,11 +588,15 @@
+ #define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK                                              0x40000000L
+ #define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK                                              0x80000000L
+ //IH_CLK_CTRL
++#define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE__SHIFT                                             0x19
++#define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE__SHIFT                                             		  0x1a
+ #define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT                                                        0x1b
+ #define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT                                                    0x1c
+ #define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT                                                       0x1d
+ #define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT                                                             0x1e
+ #define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT                                                             0x1f
++#define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE_MASK                                              0x02000000L
++#define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE_MASK                                             		  0x04000000L
+ #define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK                                                          0x08000000L
+ #define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK                                                      0x10000000L
+ #define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK                                                         0x20000000L
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3983-drm-amd-powerplay-bypass-dpm_context-null-pointer-ch.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3983-drm-amd-powerplay-bypass-dpm_context-null-pointer-ch.patch
new file mode 100644
index 00000000..a747de58
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3983-drm-amd-powerplay-bypass-dpm_context-null-pointer-ch.patch
@@ -0,0 +1,75 @@
+From f4006b640275b8f5646ff61198594b7ed441b93d Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Wed, 18 Sep 2019 15:11:34 +0800
+Subject: [PATCH 3983/4256] drm/amd/powerplay: bypass dpm_context null pointer
+ check guard for some smu series
+
+For now APU has no smu_dpm_context structure for containing default/current related dpm tables,
+thus will needn't initialize smu_dpm_context to aviod APU null pointer issue.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c     | 7 ++++---
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 +
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c     | 1 +
+ 3 files changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 3d1bfa8ea7c2..a307d4a52e87 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1559,7 +1559,8 @@ static int smu_enable_umd_pstate(void *handle,
+ 
+ 	struct smu_context *smu = (struct smu_context*)(handle);
+ 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+-	if (!smu->pm_enabled || !smu_dpm_ctx->dpm_context)
++
++	if (!smu->is_apu && (!smu->pm_enabled || !smu_dpm_ctx->dpm_context))
+ 		return -EINVAL;
+ 
+ 	if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
+@@ -1757,7 +1758,7 @@ enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
+ 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+ 	enum amd_dpm_forced_level level;
+ 
+-	if (!smu_dpm_ctx->dpm_context)
++	if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
+ 		return -EINVAL;
+ 
+ 	mutex_lock(&(smu->mutex));
+@@ -1772,7 +1773,7 @@ int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_lev
+ 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+ 	int ret = 0;
+ 
+-	if (!smu_dpm_ctx->dpm_context)
++	if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
+ 		return -EINVAL;
+ 
+ 	ret = smu_enable_umd_pstate(smu, &level);
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index bc4b73e0718e..f1b378965551 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -388,6 +388,7 @@ struct smu_context
+ 	uint32_t power_profile_mode;
+ 	uint32_t default_power_profile_mode;
+ 	bool pm_enabled;
++	bool is_apu;
+ 
+ 	uint32_t smc_if_version;
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 9311b6acc34d..0985da2ed922 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -319,4 +319,5 @@ void renoir_set_ppt_funcs(struct smu_context *smu)
+ {
+ 	smu->ppt_funcs = &renoir_ppt_funcs;
+ 	smu->smc_if_version = SMU12_DRIVER_IF_VERSION;
++	smu->is_apu = true;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3984-drm-amd-powerplay-implement-the-interface-for-settin.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3984-drm-amd-powerplay-implement-the-interface-for-settin.patch
new file mode 100644
index 00000000..e92e4f62
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3984-drm-amd-powerplay-implement-the-interface-for-settin.patch
@@ -0,0 +1,207 @@
+From 33ef11ddd78d1e905f2b9566fbc5d90551b8aa56 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Tue, 24 Sep 2019 14:40:09 +0800
+Subject: [PATCH 3984/4256] drm/amd/powerplay: implement the interface for
+ setting soft freq range
+
+The APU soft freq range set by different way from DGPU, thus need implement
+the function respectively base on each common SMU part.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 25 +--------
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  3 +
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 30 ++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c     | 56 +++++++++++++++++++
+ 4 files changed, 91 insertions(+), 23 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index a307d4a52e87..efc14c7e7bc2 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -205,8 +205,7 @@ int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t
+ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ 			    uint32_t min, uint32_t max)
+ {
+-	int ret = 0, clk_id = 0;
+-	uint32_t param;
++	int ret = 0;
+ 
+ 	if (min <= 0 && max <= 0)
+ 		return -EINVAL;
+@@ -214,27 +213,7 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ 	if (!smu_clk_dpm_is_enabled(smu, clk_type))
+ 		return 0;
+ 
+-	clk_id = smu_clk_get_index(smu, clk_type);
+-	if (clk_id < 0)
+-		return clk_id;
+-
+-	if (max > 0) {
+-		param = (uint32_t)((clk_id << 16) | (max & 0xffff));
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
+-						  param);
+-		if (ret)
+-			return ret;
+-	}
+-
+-	if (min > 0) {
+-		param = (uint32_t)((clk_id << 16) | (min & 0xffff));
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
+-						  param);
+-		if (ret)
+-			return ret;
+-	}
+-
+-
++	ret = smu_set_soft_freq_limited_range(smu, clk_type, min, max);
+ 	return ret;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index f1b378965551..504d6487c3d2 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -548,6 +548,7 @@ struct smu_funcs
+ 	int (*baco_reset)(struct smu_context *smu);
+ 	int (*mode2_reset)(struct smu_context *smu);
+ 	int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
++	int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
+ };
+ 
+ #define smu_init_microcode(smu) \
+@@ -777,6 +778,8 @@ struct smu_funcs
+ #define smu_get_dpm_uclk_limited(smu, clock, max) \
+ 		((smu)->ppt_funcs->get_dpm_uclk_limited ? (smu)->ppt_funcs->get_dpm_uclk_limited((smu), (clock), (max)) : -EINVAL)
+ 
++#define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
++		((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
+ 
+ extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
+ 				   uint16_t *size, uint8_t *frev, uint8_t *crev,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 022b5c8672a1..9883f0a4471a 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1762,6 +1762,35 @@ static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ 	return ret;
+ }
+ 
++static int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
++			    uint32_t min, uint32_t max)
++{
++	int ret = 0, clk_id = 0;
++	uint32_t param;
++
++	clk_id = smu_clk_get_index(smu, clk_type);
++	if (clk_id < 0)
++		return clk_id;
++
++	if (max > 0) {
++		param = (uint32_t)((clk_id << 16) | (max & 0xffff));
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
++						  param);
++		if (ret)
++			return ret;
++	}
++
++	if (min > 0) {
++		param = (uint32_t)((clk_id << 16) | (min & 0xffff));
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
++						  param);
++		if (ret)
++			return ret;
++	}
++
++	return ret;
++}
++
+ static const struct smu_funcs smu_v11_0_funcs = {
+ 	.init_microcode = smu_v11_0_init_microcode,
+ 	.load_microcode = smu_v11_0_load_microcode,
+@@ -1813,6 +1842,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
+ 	.baco_set_state = smu_v11_0_baco_set_state,
+ 	.baco_reset = smu_v11_0_baco_reset,
+ 	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
++	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+ };
+ 
+ void smu_v11_0_set_smu_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index d9d947375557..d3563f0c44e9 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -383,6 +383,61 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ static int smu_v12_0_mode2_reset(struct smu_context *smu){
+ 	return smu_v12_0_send_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2);
+ }
++
++static int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
++			    uint32_t min, uint32_t max)
++{
++	int ret = 0;
++
++	if (max < min)
++		return -EINVAL;
++
++	switch (clk_type) {
++	case SMU_GFXCLK:
++	case SMU_SCLK:
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, min);
++		if (ret)
++			return ret;
++
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, max);
++		if (ret)
++			return ret;
++	break;
++	case SMU_FCLK:
++	case SMU_MCLK:
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min);
++		if (ret)
++			return ret;
++
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max);
++		if (ret)
++			return ret;
++	break;
++	case SMU_SOCCLK:
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min);
++		if (ret)
++			return ret;
++
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max);
++		if (ret)
++			return ret;
++	break;
++	case SMU_VCLK:
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn, min);
++		if (ret)
++			return ret;
++
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxVcn, max);
++		if (ret)
++			return ret;
++	break;
++	default:
++		return -EINVAL;
++	}
++
++	return ret;
++}
++
+ static const struct smu_funcs smu_v12_0_funcs = {
+ 	.check_fw_status = smu_v12_0_check_fw_status,
+ 	.check_fw_version = smu_v12_0_check_fw_version,
+@@ -398,6 +453,7 @@ static const struct smu_funcs smu_v12_0_funcs = {
+ 	.populate_smc_tables = smu_v12_0_populate_smc_tables,
+ 	.get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
+ 	.mode2_reset = smu_v12_0_mode2_reset,
++	.set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
+ };
+ 
+ void smu_v12_0_set_smu_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3985-drm-amd-powerplay-add-interface-for-forcing-and-unfo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3985-drm-amd-powerplay-add-interface-for-forcing-and-unfo.patch
new file mode 100644
index 00000000..d2ed8fb5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3985-drm-amd-powerplay-add-interface-for-forcing-and-unfo.patch
@@ -0,0 +1,97 @@
+From 86fd9618e5d5eac1b07e5719dea89ca1f854115b Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Mon, 23 Sep 2019 11:02:40 +0800
+Subject: [PATCH 3985/4256] drm/amd/powerplay: add interface for forcing and
+ unforcing dpm limit value
+
+That's base function for forcing and unforcing dpm limit value.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 62 ++++++++++++++++++++++
+ 1 file changed, 62 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 0985da2ed922..668b07985ea0 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -304,6 +304,66 @@ static int renoir_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
+ 	return ret;
+ }
+ 
++static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
++{
++	int ret = 0, i = 0;
++	uint32_t min_freq, max_freq, force_freq;
++	enum smu_clk_type clk_type;
++
++	enum smu_clk_type clks[] = {
++		SMU_GFXCLK,
++		SMU_MCLK,
++		SMU_SOCCLK,
++	};
++
++	for (i = 0; i < ARRAY_SIZE(clks); i++) {
++		clk_type = clks[i];
++		ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
++		if (ret)
++			return ret;
++
++		force_freq = highest ? max_freq : min_freq;
++		ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
++		if (ret)
++			return ret;
++	}
++
++	return ret;
++}
++
++static int renoir_unforce_dpm_levels(struct smu_context *smu) {
++
++	int ret = 0, i = 0;
++	uint32_t min_freq, max_freq;
++	enum smu_clk_type clk_type;
++
++	struct clk_feature_map {
++		enum smu_clk_type clk_type;
++		uint32_t	feature;
++	} clk_feature_map[] = {
++		{SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
++		{SMU_MCLK,   SMU_FEATURE_DPM_UCLK_BIT},
++		{SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
++	};
++
++	for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
++		if (!smu_feature_is_enabled(smu, clk_feature_map[i].feature))
++		    continue;
++
++		clk_type = clk_feature_map[i].clk_type;
++
++		ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
++		if (ret)
++			return ret;
++
++		ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
++		if (ret)
++			return ret;
++	}
++
++	return ret;
++}
++
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_smu_msg_index = renoir_get_smu_msg_index,
+ 	.get_smu_table_index = renoir_get_smu_table_index,
+@@ -313,6 +373,8 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.print_clk_levels = renoir_print_clk_levels,
+ 	.get_current_power_state = renoir_get_current_power_state,
+ 	.dpm_set_uvd_enable = renoir_dpm_set_uvd_enable,
++	.force_dpm_limit_value = renoir_force_dpm_limit_value,
++	.unforce_dpm_levels = renoir_unforce_dpm_levels,
+ };
+ 
+ void renoir_set_ppt_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3986-drm-amd-powerplay-add-interface-for-getting-workload.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3986-drm-amd-powerplay-add-interface-for-getting-workload.patch
new file mode 100644
index 00000000..fad40f85
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3986-drm-amd-powerplay-add-interface-for-getting-workload.patch
@@ -0,0 +1,64 @@
+From 6caa4d083c60a0437a58a452880f1e4533b3ebb4 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Mon, 23 Sep 2019 14:42:36 +0800
+Subject: [PATCH 3986/4256] drm/amd/powerplay: add interface for getting
+ workload type
+
+The workload type was got from the input of power profile mode.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 29 ++++++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 668b07985ea0..11d57e26b855 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -364,6 +364,34 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
+ 	return ret;
+ }
+ 
++static int renoir_get_workload_type(struct smu_context *smu, uint32_t profile)
++{
++
++	uint32_t  pplib_workload = 0;
++
++	switch (profile) {
++	case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
++		pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
++		break;
++	case PP_SMC_POWER_PROFILE_CUSTOM:
++		pplib_workload = WORKLOAD_PPLIB_COUNT;
++		break;
++	case PP_SMC_POWER_PROFILE_VIDEO:
++		pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
++		break;
++	case PP_SMC_POWER_PROFILE_VR:
++		pplib_workload = WORKLOAD_PPLIB_VR_BIT;
++		break;
++	case PP_SMC_POWER_PROFILE_COMPUTE:
++		pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return pplib_workload;
++}
++
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_smu_msg_index = renoir_get_smu_msg_index,
+ 	.get_smu_table_index = renoir_get_smu_table_index,
+@@ -375,6 +403,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.dpm_set_uvd_enable = renoir_dpm_set_uvd_enable,
+ 	.force_dpm_limit_value = renoir_force_dpm_limit_value,
+ 	.unforce_dpm_levels = renoir_unforce_dpm_levels,
++	.get_workload_type = renoir_get_workload_type,
+ };
+ 
+ void renoir_set_ppt_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3987-drm-amd-powerplay-add-the-interfaces-for-getting-and.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3987-drm-amd-powerplay-add-the-interfaces-for-getting-and.patch
new file mode 100644
index 00000000..42874935
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3987-drm-amd-powerplay-add-the-interfaces-for-getting-and.patch
@@ -0,0 +1,126 @@
+From b2eaa7361d5f5bd665eca32037f7d9a666f3ad00 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Mon, 23 Sep 2019 15:29:07 +0800
+Subject: [PATCH 3987/4256] drm/amd/powerplay: add the interfaces for getting
+ and setting profiling dpm clock level
+
+implement get_profiling_clk_mask and force_clk_levels for forcing dpm clk to limit value.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 91 ++++++++++++++++++++++
+ 1 file changed, 91 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 11d57e26b855..18ebeaba8d30 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -392,6 +392,95 @@ static int renoir_get_workload_type(struct smu_context *smu, uint32_t profile)
+ 	return pplib_workload;
+ }
+ 
++static int renoir_get_profiling_clk_mask(struct smu_context *smu,
++					 enum amd_dpm_forced_level level,
++					 uint32_t *sclk_mask,
++					 uint32_t *mclk_mask,
++					 uint32_t *soc_mask)
++{
++
++	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
++		if (sclk_mask)
++			*sclk_mask = 0;
++	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
++		if (mclk_mask)
++			*mclk_mask = 0;
++	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
++		if(sclk_mask)
++			/* The sclk as gfxclk and has three level about max/min/current */
++			*sclk_mask = 3 - 1;
++
++		if(mclk_mask)
++			*mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
++
++		if(soc_mask)
++			*soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
++	}
++
++	return 0;
++}
++
++static int renoir_force_clk_levels(struct smu_context *smu,
++				   enum smu_clk_type clk_type, uint32_t mask)
++{
++
++	int ret = 0 ;
++	uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
++	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
++
++	soft_min_level = mask ? (ffs(mask) - 1) : 0;
++	soft_max_level = mask ? (fls(mask) - 1) : 0;
++
++	switch (clk_type) {
++	case SMU_GFXCLK:
++	case SMU_SCLK:
++		if (soft_min_level > 2 || soft_max_level > 2) {
++			pr_info("Currently sclk only support 3 levels on APU\n");
++			return -EINVAL;
++		}
++
++		ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min_freq, &max_freq);
++		if (ret)
++			return ret;
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
++					soft_max_level == 0 ? min_freq :
++					soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq);
++		if (ret)
++			return ret;
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
++					soft_min_level == 2 ? max_freq :
++					soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq);
++		if (ret)
++			return ret;
++		break;
++	case SMU_SOCCLK:
++		GET_DPM_CUR_FREQ(clk_table, clk_type, soft_min_level, min_freq);
++		GET_DPM_CUR_FREQ(clk_table, clk_type, soft_max_level, max_freq);
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq);
++		if (ret)
++			return ret;
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq);
++		if (ret)
++			return ret;
++		break;
++	case SMU_MCLK:
++	case SMU_FCLK:
++		GET_DPM_CUR_FREQ(clk_table, clk_type, soft_min_level, min_freq);
++		GET_DPM_CUR_FREQ(clk_table, clk_type, soft_max_level, max_freq);
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq);
++		if (ret)
++			return ret;
++		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq);
++		if (ret)
++			return ret;
++		break;
++	default:
++		break;
++	}
++
++	return ret;
++}
++
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_smu_msg_index = renoir_get_smu_msg_index,
+ 	.get_smu_table_index = renoir_get_smu_table_index,
+@@ -404,6 +493,8 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.force_dpm_limit_value = renoir_force_dpm_limit_value,
+ 	.unforce_dpm_levels = renoir_unforce_dpm_levels,
+ 	.get_workload_type = renoir_get_workload_type,
++	.get_profiling_clk_mask = renoir_get_profiling_clk_mask,
++	.force_clk_levels = renoir_force_clk_levels,
+ };
+ 
+ void renoir_set_ppt_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3988-drm-amd-powerplay-implement-interface-set_power_prof.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3988-drm-amd-powerplay-implement-interface-set_power_prof.patch
new file mode 100644
index 00000000..7db4573a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3988-drm-amd-powerplay-implement-interface-set_power_prof.patch
@@ -0,0 +1,70 @@
+From 11f1b9201791dc93e3655c2e97fe1eb43459149d Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Mon, 23 Sep 2019 15:52:12 +0800
+Subject: [PATCH 3988/4256] drm/amd/powerplay: implement interface
+ set_power_profile_mode() (v2)
+
+v1:
+Add set_power_profile_mode() for none manual dpm level case setting power profile mode.
+
+v2:
+After input power profile update successfully need can update the smu profile mode.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 31 ++++++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 18ebeaba8d30..3785b7fd3d66 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -481,6 +481,36 @@ static int renoir_force_clk_levels(struct smu_context *smu,
+ 	return ret;
+ }
+ 
++static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
++{
++	int workload_type, ret;
++	uint32_t profile_mode = input[size];
++
++	if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
++		pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
++		return -EINVAL;
++	}
++
++	/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
++	workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
++	if (workload_type < 0) {
++		pr_err("Unsupported power profile mode %d on RENOIR\n",smu->power_profile_mode);
++		return -EINVAL;
++	}
++
++	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
++				    1 << workload_type);
++	if (ret) {
++		pr_err("Fail to set workload type %d\n", workload_type);
++		return ret;
++	}
++
++	smu->power_profile_mode = profile_mode;
++
++	return 0;
++}
++
++
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_smu_msg_index = renoir_get_smu_msg_index,
+ 	.get_smu_table_index = renoir_get_smu_table_index,
+@@ -495,6 +525,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_workload_type = renoir_get_workload_type,
+ 	.get_profiling_clk_mask = renoir_get_profiling_clk_mask,
+ 	.force_clk_levels = renoir_force_clk_levels,
++	.set_power_profile_mode = renoir_set_power_profile_mode,
+ };
+ 
+ void renoir_set_ppt_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3989-drm-amd-powerplay-implement-the-interface-for-settin.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3989-drm-amd-powerplay-implement-the-interface-for-settin.patch
new file mode 100644
index 00000000..21fcf9f3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3989-drm-amd-powerplay-implement-the-interface-for-settin.patch
@@ -0,0 +1,75 @@
+From df8b7d22fefdc299202a8fa821f0750baf2b9b03 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Wed, 25 Sep 2019 14:11:41 +0800
+Subject: [PATCH 3989/4256] drm/amd/powerplay: implement the interface for
+ setting sclk/uclk profile_peak level
+
+Add the interface for setting sclk and uclk peak frequency.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 40 ++++++++++++++++++++++
+ 1 file changed, 40 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 3785b7fd3d66..c11f8d74b7f8 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -510,6 +510,45 @@ static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, u
+ 	return 0;
+ }
+ 
++static int renoir_set_peak_clock_by_device(struct smu_context *smu)
++{
++	int ret = 0;
++	uint32_t sclk_freq = 0, uclk_freq = 0;
++
++	ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL, &sclk_freq);
++	if (ret)
++		return ret;
++
++	ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
++	if (ret)
++		return ret;
++
++	ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &uclk_freq);
++	if (ret)
++		return ret;
++
++	ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
++	if (ret)
++		return ret;
++
++	return ret;
++}
++
++static int renoir_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
++{
++	int ret = 0;
++
++	switch (level) {
++	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
++		ret = renoir_set_peak_clock_by_device(smu);
++		break;
++	default:
++		ret = -EINVAL;
++		break;
++	}
++
++	return ret;
++}
+ 
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_smu_msg_index = renoir_get_smu_msg_index,
+@@ -526,6 +565,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_profiling_clk_mask = renoir_get_profiling_clk_mask,
+ 	.force_clk_levels = renoir_force_clk_levels,
+ 	.set_power_profile_mode = renoir_set_power_profile_mode,
++	.set_performance_level = renoir_set_performance_level,
+ };
+ 
+ void renoir_set_ppt_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3990-drm-amd-powerplay-update-the-interface-for-getting-d.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3990-drm-amd-powerplay-update-the-interface-for-getting-d.patch
new file mode 100644
index 00000000..ecaab429
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3990-drm-amd-powerplay-update-the-interface-for-getting-d.patch
@@ -0,0 +1,154 @@
+From 449dd12af5033c7dd89c0f9664baf47273c03827 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Wed, 25 Sep 2019 17:48:56 +0800
+Subject: [PATCH 3990/4256] drm/amd/powerplay: update the interface for getting
+ dpm full scale clock frequency
+
+Update get_dpm_uclk_limited to get more clock type full scale dpm frequency.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  7 +++--
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c    | 16 ++++-------
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c     | 28 ++++++++++++++++---
+ 3 files changed, 34 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 504d6487c3d2..ccf711c327c8 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -466,7 +466,8 @@ struct pptable_funcs {
+ 	int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
+ 	void (*dump_pptable)(struct smu_context *smu);
+ 	int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool asic_default);
+-	int (*get_dpm_uclk_limited)(struct smu_context *smu, uint32_t *clock, bool max);
++	int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type clk_type,
++				   uint32_t dpm_level, uint32_t *freq);
+ };
+ 
+ struct smu_funcs
+@@ -775,8 +776,8 @@ struct smu_funcs
+ 	((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
+ #define smu_dump_pptable(smu) \
+ 	((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0)
+-#define smu_get_dpm_uclk_limited(smu, clock, max) \
+-		((smu)->ppt_funcs->get_dpm_uclk_limited ? (smu)->ppt_funcs->get_dpm_uclk_limited((smu), (clock), (max)) : -EINVAL)
++#define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) \
++		((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EINVAL)
+ 
+ #define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
+ 		((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index c11f8d74b7f8..6aedffd739db 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -160,21 +160,17 @@ static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
+  * This interface just for getting uclk ultimate freq and should't introduce
+  * other likewise function result in overmuch callback.
+  */
+-static int renoir_get_dpm_uclk_limited(struct smu_context *smu, uint32_t *clock, bool max)
++static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
++						uint32_t dpm_level, uint32_t *freq)
+ {
++	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
+ 
+-	DpmClocks_t *table = smu->smu_table.clocks_table;
+-
+-	if (!clock || !table)
++	if (!clk_table || clk_type >= SMU_CLK_COUNT)
+ 		return -EINVAL;
+ 
+-	if (max)
+-		*clock = table->FClocks[NUM_FCLK_DPM_LEVELS-1].Freq;
+-	else
+-		*clock = table->FClocks[0].Freq;
++	GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq);
+ 
+ 	return 0;
+-
+ }
+ 
+ static int renoir_print_clk_levels(struct smu_context *smu,
+@@ -555,7 +551,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_smu_table_index = renoir_get_smu_table_index,
+ 	.tables_init = renoir_tables_init,
+ 	.set_power_state = NULL,
+-	.get_dpm_uclk_limited = renoir_get_dpm_uclk_limited,
++	.get_dpm_clk_limited = renoir_get_dpm_clk_limited,
+ 	.print_clk_levels = renoir_print_clk_levels,
+ 	.get_current_power_state = renoir_get_current_power_state,
+ 	.dpm_set_uvd_enable = renoir_dpm_set_uvd_enable,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index d3563f0c44e9..c9691d0fb523 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -323,10 +323,18 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ 						 uint32_t *min, uint32_t *max)
+ {
+ 	int ret = 0;
++	uint32_t mclk_mask, soc_mask;
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+ 	if (max) {
++		ret = smu_get_profiling_clk_mask(smu, AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
++						 NULL,
++						 &mclk_mask,
++						 &soc_mask);
++		if (ret)
++			goto failed;
++
+ 		switch (clk_type) {
+ 		case SMU_GFXCLK:
+ 		case SMU_SCLK:
+@@ -340,14 +348,20 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ 				goto failed;
+ 			break;
+ 		case SMU_UCLK:
+-			ret = smu_get_dpm_uclk_limited(smu, max, true);
++		case SMU_FCLK:
++		case SMU_MCLK:
++			ret = smu_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
++			if (ret)
++				goto failed;
++			break;
++		case SMU_SOCCLK:
++			ret = smu_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
+ 			if (ret)
+ 				goto failed;
+ 			break;
+ 		default:
+ 			ret = -EINVAL;
+ 			goto failed;
+-
+ 		}
+ 	}
+ 
+@@ -365,7 +379,14 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ 				goto failed;
+ 			break;
+ 		case SMU_UCLK:
+-			ret = smu_get_dpm_uclk_limited(smu, min, false);
++		case SMU_FCLK:
++		case SMU_MCLK:
++			ret = smu_get_dpm_clk_limited(smu, clk_type, 0, min);
++			if (ret)
++				goto failed;
++			break;
++		case SMU_SOCCLK:
++			ret = smu_get_dpm_clk_limited(smu, clk_type, 0, min);
+ 			if (ret)
+ 				goto failed;
+ 			break;
+@@ -373,7 +394,6 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ 			ret = -EINVAL;
+ 			goto failed;
+ 		}
+-
+ 	}
+ failed:
+ 	mutex_unlock(&smu->mutex);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3991-drm-amd-powerplay-initlialize-smu-is_apu-is-false-by.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3991-drm-amd-powerplay-initlialize-smu-is_apu-is-false-by.patch
new file mode 100644
index 00000000..d6a5fb7a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3991-drm-amd-powerplay-initlialize-smu-is_apu-is-false-by.patch
@@ -0,0 +1,36 @@
+From 0db115dbc6fb543d8477e5fbeab2dec3ffe265c0 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Fri, 27 Sep 2019 14:52:10 +0800
+Subject: [PATCH 3991/4256] drm/amd/powerplay: initlialize smu->is_apu is false
+ by default
+
+the member of is_apu in smu_context need to initlialize by default.
+
+set default value is false (dGPU)
+
+for patch:
+	drm/amd/powerplay: bypass dpm_context null pointer check guard
+	for some smu series
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Prike Liang <Prike.Liang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index efc14c7e7bc2..c63b2a9902de 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -712,6 +712,7 @@ static int smu_early_init(void *handle)
+ 
+ 	smu->adev = adev;
+ 	smu->pm_enabled = !!amdgpu_dpm;
++	smu->is_apu = false;
+ 	mutex_init(&smu->mutex);
+ 
+ 	return smu_set_funcs(adev);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3992-drm-amd-powerplay-unlock-on-error-in-smu_resume.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3992-drm-amd-powerplay-unlock-on-error-in-smu_resume.patch
new file mode 100644
index 00000000..93f276ed
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3992-drm-amd-powerplay-unlock-on-error-in-smu_resume.patch
@@ -0,0 +1,31 @@
+From 87a0ac5da5aea95ee0936f90a0c8ee3f43f9a594 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Mon, 7 Oct 2019 12:04:54 +0300
+Subject: [PATCH 3992/4256] drm/amd/powerplay: unlock on error in smu_resume()
+
+This function needs to drop the mutex before returning.
+
+Fixes: f7e3a5776fa6 ("drm/amd/powerplay: check SMU engine readiness before proceeding on S3 resume")
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index c63b2a9902de..88d7376aee71 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1384,7 +1384,7 @@ static int smu_resume(void *handle)
+ 	ret = smu_start_smc_engine(smu);
+ 	if (ret) {
+ 		pr_err("SMU is not ready yet!\n");
+-		return ret;
++		goto failed;
+ 	}
+ 
+ 	ret = smu_smc_table_hw_init(smu, false);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3993-drm-amd-powerplay-Fix-error-handling-in-smu_init_fb_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3993-drm-amd-powerplay-Fix-error-handling-in-smu_init_fb_.patch
new file mode 100644
index 00000000..7cd39f2e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3993-drm-amd-powerplay-Fix-error-handling-in-smu_init_fb_.patch
@@ -0,0 +1,48 @@
+From cf2ec759c2eb91c144c94a1eed145982c01f31e3 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Mon, 7 Oct 2019 12:02:06 +0300
+Subject: [PATCH 3993/4256] drm/amd/powerplay: Fix error handling in
+ smu_init_fb_allocations()
+
+The error handling is off by one.  We should not free the first
+"tables[i].bo" without decrementing "i" because that might result in a
+double free.  The second problem is that when an error occurs, then the
+zeroth element "tables[0].bo" isn't freed.
+
+I had make "i" signed int for the error handling to work, so I just
+updated "ret" as well as a clean up.
+
+Fixes: f96357a991b9 ("drm/amd/powerplay: implement smu_init(fini)_fb_allocations function")
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 88d7376aee71..054376342454 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -896,8 +896,7 @@ static int smu_init_fb_allocations(struct smu_context *smu)
+ 	struct amdgpu_device *adev = smu->adev;
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 	struct smu_table *tables = smu_table->tables;
+-	uint32_t i = 0;
+-	int32_t ret = 0;
++	int ret, i;
+ 
+ 	for (i = 0; i < SMU_TABLE_COUNT; i++) {
+ 		if (tables[i].size == 0)
+@@ -915,7 +914,7 @@ static int smu_init_fb_allocations(struct smu_context *smu)
+ 
+ 	return 0;
+ failed:
+-	for (; i > 0; i--) {
++	while (--i >= 0) {
+ 		if (tables[i].size == 0)
+ 			continue;
+ 		amdgpu_bo_free_kernel(&tables[i].bo,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3994-Revert-drm-amdgpu-disable-stutter-mode-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3994-Revert-drm-amdgpu-disable-stutter-mode-for-renoir.patch
new file mode 100644
index 00000000..b5dad724
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3994-Revert-drm-amdgpu-disable-stutter-mode-for-renoir.patch
@@ -0,0 +1,33 @@
+From a83fac0be401fa93ab5e47ae0af34c1db2182bfd Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Mon, 16 Sep 2019 10:05:09 +0800
+Subject: [PATCH 3994/4256] Revert "drm/amdgpu: disable stutter mode for
+ renoir"
+
+This reverts commit c512e6fdfd2da917b5b6792902e7224f58a77f94.
+
+Since SBIOS WCD9925N, NMI printing disappeared. Hence enable stutter
+mode.
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 2f80fb927888..be9a95b534b8 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -2447,8 +2447,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
+ 
+ 	if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
+ 		dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
+-	if (adev->asic_type == CHIP_RENOIR)
+-		dm->dc->debug.disable_stutter = true;
+ 
+ 	return 0;
+ fail:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3995-drm-amdgpu-dm-Resume-short-HPD-IRQs-before-resuming-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3995-drm-amdgpu-dm-Resume-short-HPD-IRQs-before-resuming-.patch
new file mode 100644
index 00000000..3f8e8a9d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3995-drm-amdgpu-dm-Resume-short-HPD-IRQs-before-resuming-.patch
@@ -0,0 +1,55 @@
+From dd588511b3d9462a8d8cb12bb5de259548dbcea4 Mon Sep 17 00:00:00 2001
+From: Lyude Paul <lyude@redhat.com>
+Date: Wed, 25 Sep 2019 17:52:48 -0400
+Subject: [PATCH 3995/4256] drm/amdgpu/dm: Resume short HPD IRQs before
+ resuming MST topology
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Since we're going to be reprobing the entire topology state on resume
+now using sideband transactions, we need to ensure that we actually have
+short HPD irqs enabled before calling drm_dp_mst_topology_mgr_resume().
+So, do that.
+
+Changes since v4:
+* Fix typo in comments
+
+Cc: Juston Li <juston.li@intel.com>
+Cc: Imre Deak <imre.deak@intel.com>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: Harry Wentland <hwentlan@amd.com>
+Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Lyude Paul <lyude@redhat.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index be9a95b534b8..7ade3cbb5552 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -1221,15 +1221,15 @@ static int dm_resume(void *handle)
+ 	/* program HPD filter */
+ 	dc_resume(dm->dc);
+ 
+-	/* On resume we need to  rewrite the MSTM control bits to enamble MST*/
+-	s3_handle_mst(ddev, false);
+-
+ 	/*
+ 	 * early enable HPD Rx IRQ, should be done before set mode as short
+ 	 * pulse interrupts are used for MST
+ 	 */
+ 	amdgpu_dm_irq_resume_early(adev);
+ 
++	/* On resume we need to  rewrite the MSTM control bits to enable MST*/
++	s3_handle_mst(ddev, false);
++
+ 	/* Do detection*/
+ 	list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
+ 		aconnector = to_amdgpu_dm_connector(connector);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3996-drm-amdgpu-Iterate-through-DRM-connectors-correctly.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3996-drm-amdgpu-Iterate-through-DRM-connectors-correctly.patch
new file mode 100644
index 00000000..8435d75f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3996-drm-amdgpu-Iterate-through-DRM-connectors-correctly.patch
@@ -0,0 +1,998 @@
+From 2ece5e4d1ded4f21bd19abcc9e36b9745ea19354 Mon Sep 17 00:00:00 2001
+From: Lyude Paul <lyude@redhat.com>
+Date: Tue, 3 Sep 2019 16:46:01 -0400
+Subject: [PATCH 3996/4256] drm/amdgpu: Iterate through DRM connectors
+ correctly
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Currently, every single piece of code in amdgpu that loops through
+connectors does it incorrectly and doesn't use the proper list iteration
+helpers, drm_connector_list_iter_begin() and
+drm_connector_list_iter_end(). Yeesh.
+
+So, do that.
+
+Cc: Juston Li <juston.li@intel.com>
+Cc: Imre Deak <imre.deak@intel.com>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: Harry Wentland <hwentlan@amd.com>
+Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Lyude Paul <lyude@redhat.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/amdgpu/amdgpu_connectors.c    | 13 +++++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    | 20 +++++++---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  5 ++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c  | 40 +++++++++++++------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c       |  5 ++-
+ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c        | 34 ++++++++++++----
+ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c        | 34 ++++++++++++----
+ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c         | 40 ++++++++++++++-----
+ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c         | 34 ++++++++++++----
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 33 ++++++++-------
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 10 ++++-
+ 11 files changed, 195 insertions(+), 73 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+index 69ad6ec0a4f3..b1226ac57515 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+@@ -1022,8 +1022,12 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
+ 			 */
+ 			if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
+ 				struct drm_connector *list_connector;
++				struct drm_connector_list_iter iter;
+ 				struct amdgpu_connector *list_amdgpu_connector;
+-				list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
++
++				drm_connector_list_iter_begin(dev, &iter);
++				drm_for_each_connector_iter(list_connector,
++							    &iter) {
+ 					if (connector == list_connector)
+ 						continue;
+ 					list_amdgpu_connector = to_amdgpu_connector(list_connector);
+@@ -1040,6 +1044,7 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
+ 						}
+ 					}
+ 				}
++				drm_connector_list_iter_end(&iter);
+ 			}
+ 		}
+ 	}
+@@ -1501,6 +1506,7 @@ amdgpu_connector_add(struct amdgpu_device *adev,
+ {
+ 	struct drm_device *dev = adev->ddev;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	struct amdgpu_connector *amdgpu_connector;
+ 	struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
+ 	struct drm_encoder *encoder;
+@@ -1514,10 +1520,12 @@ amdgpu_connector_add(struct amdgpu_device *adev,
+ 		return;
+ 
+ 	/* see if we already added it */
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		amdgpu_connector = to_amdgpu_connector(connector);
+ 		if (amdgpu_connector->connector_id == connector_id) {
+ 			amdgpu_connector->devices |= supported_device;
++			drm_connector_list_iter_end(&iter);
+ 			return;
+ 		}
+ 		if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
+@@ -1532,6 +1540,7 @@ amdgpu_connector_add(struct amdgpu_device *adev,
+ 			}
+ 		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ 
+ 	/* check if it's a dp bridge */
+ 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 8f7e8911d4f3..9e9617ce9381 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3027,6 +3027,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
+ 	struct amdgpu_device *adev;
+ 	struct drm_crtc *crtc;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	int r;
+ 
+ 	if (dev == NULL || dev->dev_private == NULL) {
+@@ -3049,9 +3050,11 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
+ 	if (!amdgpu_device_has_dc_support(adev)) {
+ 		/* turn off display hw */
+ 		drm_modeset_lock_all(dev);
+-		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+-			drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
+-		}
++		drm_connector_list_iter_begin(dev, &iter);
++		drm_for_each_connector_iter(connector, &iter)
++			drm_helper_connector_dpms(connector,
++						  DRM_MODE_DPMS_OFF);
++		drm_connector_list_iter_end(&iter);
+ 		drm_modeset_unlock_all(dev);
+ 			/* unpin the front buffers and cursors */
+ 		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+@@ -3130,6 +3133,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
+ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
+ {
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	struct amdgpu_device *adev = dev->dev_private;
+ 	struct drm_crtc *crtc;
+ 	int r = 0;
+@@ -3200,9 +3204,13 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
+ 
+ 			/* turn on display hw */
+ 			drm_modeset_lock_all(dev);
+-			list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+-				drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
+-			}
++
++			drm_connector_list_iter_begin(dev, &iter);
++			drm_for_each_connector_iter(connector, &iter)
++				drm_helper_connector_dpms(connector,
++							  DRM_MODE_DPMS_ON);
++			drm_connector_list_iter_end(&iter);
++
+ 			drm_modeset_unlock_all(dev);
+ 		}
+ 		amdgpu_fbdev_set_suspend(adev, 0);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+index 543f7a8f6c76..aad642e660b2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+@@ -368,11 +368,13 @@ void amdgpu_display_print_display_setup(struct drm_device *dev)
+ 	struct amdgpu_connector *amdgpu_connector;
+ 	struct drm_encoder *encoder;
+ 	struct amdgpu_encoder *amdgpu_encoder;
++	struct drm_connector_list_iter iter;
+ 	uint32_t devices;
+ 	int i = 0;
+ 
++	drm_connector_list_iter_begin(dev, &iter);
+ 	DRM_INFO("AMDGPU Display Connectors\n");
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++	drm_for_each_connector_iter(connector, &iter) {
+ 		amdgpu_connector = to_amdgpu_connector(connector);
+ 		DRM_INFO("Connector %d:\n", i);
+ 		DRM_INFO("  %s\n", connector->name);
+@@ -436,6 +438,7 @@ void amdgpu_display_print_display_setup(struct drm_device *dev)
+ 		}
+ 		i++;
+ 	}
++	drm_connector_list_iter_end(&iter);
+ }
+ 
+ /**
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c
+index ec78e2b2015c..02a42e908b1d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c
+@@ -37,12 +37,14 @@ amdgpu_link_encoder_connector(struct drm_device *dev)
+ {
+ 	struct amdgpu_device *adev = dev->dev_private;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	struct amdgpu_connector *amdgpu_connector;
+ 	struct drm_encoder *encoder;
+ 	struct amdgpu_encoder *amdgpu_encoder;
+ 
++	drm_connector_list_iter_begin(dev, &iter);
+ 	/* walk the list and link encoders to connectors */
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++	drm_for_each_connector_iter(connector, &iter) {
+ 		amdgpu_connector = to_amdgpu_connector(connector);
+ 		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+ 			amdgpu_encoder = to_amdgpu_encoder(encoder);
+@@ -55,6 +57,7 @@ amdgpu_link_encoder_connector(struct drm_device *dev)
+ 			}
+ 		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ }
+ 
+ void amdgpu_encoder_set_active_device(struct drm_encoder *encoder)
+@@ -62,8 +65,10 @@ void amdgpu_encoder_set_active_device(struct drm_encoder *encoder)
+ 	struct drm_device *dev = encoder->dev;
+ 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		if (connector->encoder == encoder) {
+ 			struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
+ 			amdgpu_encoder->active_device = amdgpu_encoder->devices & amdgpu_connector->devices;
+@@ -72,6 +77,7 @@ void amdgpu_encoder_set_active_device(struct drm_encoder *encoder)
+ 				  amdgpu_connector->devices, encoder->encoder_type);
+ 		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ }
+ 
+ struct drm_connector *
+@@ -79,15 +85,20 @@ amdgpu_get_connector_for_encoder(struct drm_encoder *encoder)
+ {
+ 	struct drm_device *dev = encoder->dev;
+ 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+-	struct drm_connector *connector;
++	struct drm_connector *connector, *found = NULL;
++	struct drm_connector_list_iter iter;
+ 	struct amdgpu_connector *amdgpu_connector;
+ 
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		amdgpu_connector = to_amdgpu_connector(connector);
+-		if (amdgpu_encoder->active_device & amdgpu_connector->devices)
+-			return connector;
++		if (amdgpu_encoder->active_device & amdgpu_connector->devices) {
++			found = connector;
++			break;
++		}
+ 	}
+-	return NULL;
++	drm_connector_list_iter_end(&iter);
++	return found;
+ }
+ 
+ struct drm_connector *
+@@ -95,15 +106,20 @@ amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder)
+ {
+ 	struct drm_device *dev = encoder->dev;
+ 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+-	struct drm_connector *connector;
++	struct drm_connector *connector, *found = NULL;
++	struct drm_connector_list_iter iter;
+ 	struct amdgpu_connector *amdgpu_connector;
+ 
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		amdgpu_connector = to_amdgpu_connector(connector);
+-		if (amdgpu_encoder->devices & amdgpu_connector->devices)
+-			return connector;
++		if (amdgpu_encoder->devices & amdgpu_connector->devices) {
++			found = connector;
++			break;
++		}
+ 	}
+-	return NULL;
++	drm_connector_list_iter_end(&iter);
++	return found;
+ }
+ 
+ struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+index d391087844e0..708fee1f2466 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+@@ -84,10 +84,13 @@ static void amdgpu_hotplug_work_func(struct work_struct *work)
+ 	struct drm_device *dev = adev->ddev;
+ 	struct drm_mode_config *mode_config = &dev->mode_config;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 
+ 	mutex_lock(&mode_config->mutex);
+-	list_for_each_entry(connector, &mode_config->connector_list, head)
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter)
+ 		amdgpu_connector_hotplug(connector);
++	drm_connector_list_iter_end(&iter);
+ 	mutex_unlock(&mode_config->mutex);
+ 	/* Just fire off a uevent and let userspace tell us what to do */
+ 	drm_helper_hpd_irq_event(dev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+index c35181e2bfe7..b6338d9d871b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+@@ -327,9 +327,11 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
+ {
+ 	struct drm_device *dev = adev->ddev;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	u32 tmp;
+ 
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
+ 
+ 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
+@@ -365,6 +367,7 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
+ 		amdgpu_irq_get(adev, &adev->hpd_irq,
+ 			       amdgpu_connector->hpd.hpd);
+ 	}
++	drm_connector_list_iter_end(&iter);
+ }
+ 
+ /**
+@@ -379,9 +382,11 @@ static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
+ {
+ 	struct drm_device *dev = adev->ddev;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	u32 tmp;
+ 
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
+ 
+ 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
+@@ -394,6 +399,7 @@ static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
+ 		amdgpu_irq_put(adev, &adev->hpd_irq,
+ 			       amdgpu_connector->hpd.hpd);
+ 	}
++	drm_connector_list_iter_end(&iter);
+ }
+ 
+ static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
+@@ -1216,10 +1222,12 @@ static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
+ static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
+ 						struct drm_display_mode *mode)
+ {
+-	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
+ 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+ 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	struct amdgpu_connector *amdgpu_connector = NULL;
+ 	u32 tmp;
+ 	int interlace = 0;
+@@ -1227,12 +1235,14 @@ static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
+ 	if (!dig || !dig->afmt || !dig->afmt->pin)
+ 		return;
+ 
+-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		if (connector->encoder == encoder) {
+ 			amdgpu_connector = to_amdgpu_connector(connector);
+ 			break;
+ 		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ 
+ 	if (!amdgpu_connector) {
+ 		DRM_ERROR("Couldn't find encoder's connector\n");
+@@ -1258,10 +1268,12 @@ static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
+ 
+ static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
+ {
+-	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
+ 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+ 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	struct amdgpu_connector *amdgpu_connector = NULL;
+ 	u32 tmp;
+ 	u8 *sadb = NULL;
+@@ -1270,12 +1282,14 @@ static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder
+ 	if (!dig || !dig->afmt || !dig->afmt->pin)
+ 		return;
+ 
+-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		if (connector->encoder == encoder) {
+ 			amdgpu_connector = to_amdgpu_connector(connector);
+ 			break;
+ 		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ 
+ 	if (!amdgpu_connector) {
+ 		DRM_ERROR("Couldn't find encoder's connector\n");
+@@ -1310,10 +1324,12 @@ static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder
+ 
+ static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
+ {
+-	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
+ 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+ 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	struct amdgpu_connector *amdgpu_connector = NULL;
+ 	struct cea_sad *sads;
+ 	int i, sad_count;
+@@ -1336,12 +1352,14 @@ static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
+ 	if (!dig || !dig->afmt || !dig->afmt->pin)
+ 		return;
+ 
+-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		if (connector->encoder == encoder) {
+ 			amdgpu_connector = to_amdgpu_connector(connector);
+ 			break;
+ 		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ 
+ 	if (!amdgpu_connector) {
+ 		DRM_ERROR("Couldn't find encoder's connector\n");
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+index f459fc70074c..6a5e13f34e8c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+@@ -345,9 +345,11 @@ static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
+ {
+ 	struct drm_device *dev = adev->ddev;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	u32 tmp;
+ 
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
+ 
+ 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
+@@ -382,6 +384,7 @@ static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
+ 		dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
+ 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
+ 	}
++	drm_connector_list_iter_end(&iter);
+ }
+ 
+ /**
+@@ -396,9 +399,11 @@ static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
+ {
+ 	struct drm_device *dev = adev->ddev;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	u32 tmp;
+ 
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
+ 
+ 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
+@@ -410,6 +415,7 @@ static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
+ 
+ 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
+ 	}
++	drm_connector_list_iter_end(&iter);
+ }
+ 
+ static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
+@@ -1242,10 +1248,12 @@ static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
+ static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
+ 						struct drm_display_mode *mode)
+ {
+-	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
+ 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+ 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	struct amdgpu_connector *amdgpu_connector = NULL;
+ 	u32 tmp;
+ 	int interlace = 0;
+@@ -1253,12 +1261,14 @@ static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
+ 	if (!dig || !dig->afmt || !dig->afmt->pin)
+ 		return;
+ 
+-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		if (connector->encoder == encoder) {
+ 			amdgpu_connector = to_amdgpu_connector(connector);
+ 			break;
+ 		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ 
+ 	if (!amdgpu_connector) {
+ 		DRM_ERROR("Couldn't find encoder's connector\n");
+@@ -1284,10 +1294,12 @@ static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
+ 
+ static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
+ {
+-	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
+ 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+ 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	struct amdgpu_connector *amdgpu_connector = NULL;
+ 	u32 tmp;
+ 	u8 *sadb = NULL;
+@@ -1296,12 +1308,14 @@ static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder
+ 	if (!dig || !dig->afmt || !dig->afmt->pin)
+ 		return;
+ 
+-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		if (connector->encoder == encoder) {
+ 			amdgpu_connector = to_amdgpu_connector(connector);
+ 			break;
+ 		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ 
+ 	if (!amdgpu_connector) {
+ 		DRM_ERROR("Couldn't find encoder's connector\n");
+@@ -1336,10 +1350,12 @@ static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder
+ 
+ static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
+ {
+-	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
+ 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+ 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	struct amdgpu_connector *amdgpu_connector = NULL;
+ 	struct cea_sad *sads;
+ 	int i, sad_count;
+@@ -1362,12 +1378,14 @@ static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
+ 	if (!dig || !dig->afmt || !dig->afmt->pin)
+ 		return;
+ 
+-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		if (connector->encoder == encoder) {
+ 			amdgpu_connector = to_amdgpu_connector(connector);
+ 			break;
+ 		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ 
+ 	if (!amdgpu_connector) {
+ 		DRM_ERROR("Couldn't find encoder's connector\n");
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+index bcea8a1a6ba6..084d5770b32d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+@@ -276,9 +276,11 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
+ {
+ 	struct drm_device *dev = adev->ddev;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	u32 tmp;
+ 
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
+ 
+ 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
+@@ -304,7 +306,7 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
+ 		dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
+ 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
+ 	}
+-
++	drm_connector_list_iter_end(&iter);
+ }
+ 
+ /**
+@@ -319,9 +321,11 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
+ {
+ 	struct drm_device *dev = adev->ddev;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	u32 tmp;
+ 
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
+ 
+ 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
+@@ -333,6 +337,7 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
+ 
+ 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
+ 	}
++	drm_connector_list_iter_end(&iter);
+ }
+ 
+ static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
+@@ -1119,20 +1124,24 @@ static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder)
+ static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder,
+ 						struct drm_display_mode *mode)
+ {
+-	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
+ 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+ 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	struct amdgpu_connector *amdgpu_connector = NULL;
+ 	int interlace = 0;
+ 	u32 tmp;
+ 
+-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		if (connector->encoder == encoder) {
+ 			amdgpu_connector = to_amdgpu_connector(connector);
+ 			break;
+ 		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ 
+ 	if (!amdgpu_connector) {
+ 		DRM_ERROR("Couldn't find encoder's connector\n");
+@@ -1159,21 +1168,25 @@ static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder,
+ 
+ static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
+ {
+-	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
+ 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+ 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	struct amdgpu_connector *amdgpu_connector = NULL;
+ 	u8 *sadb = NULL;
+ 	int sad_count;
+ 	u32 tmp;
+ 
+-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		if (connector->encoder == encoder) {
+ 			amdgpu_connector = to_amdgpu_connector(connector);
+ 			break;
+ 		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ 
+ 	if (!amdgpu_connector) {
+ 		DRM_ERROR("Couldn't find encoder's connector\n");
+@@ -1216,10 +1229,12 @@ static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
+ 
+ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)
+ {
+-	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
+ 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+ 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	struct amdgpu_connector *amdgpu_connector = NULL;
+ 	struct cea_sad *sads;
+ 	int i, sad_count;
+@@ -1239,12 +1254,14 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)
+ 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
+ 	};
+ 
+-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		if (connector->encoder == encoder) {
+ 			amdgpu_connector = to_amdgpu_connector(connector);
+ 			break;
+ 		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ 
+ 	if (!amdgpu_connector) {
+ 		DRM_ERROR("Couldn't find encoder's connector\n");
+@@ -1626,6 +1643,7 @@ static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder,
+ 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+ 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	struct amdgpu_connector *amdgpu_connector = NULL;
+ 	int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
+ 	int bpc = 8;
+@@ -1633,12 +1651,14 @@ static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder,
+ 	if (!dig || !dig->afmt)
+ 		return;
+ 
+-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		if (connector->encoder == encoder) {
+ 			amdgpu_connector = to_amdgpu_connector(connector);
+ 			break;
+ 		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ 
+ 	if (!amdgpu_connector) {
+ 		DRM_ERROR("Couldn't find encoder's connector\n");
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+index 37fd742ab62d..183fc065963a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+@@ -272,9 +272,11 @@ static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
+ {
+ 	struct drm_device *dev = adev->ddev;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	u32 tmp;
+ 
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
+ 
+ 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
+@@ -300,6 +302,7 @@ static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
+ 		dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
+ 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
+ 	}
++	drm_connector_list_iter_end(&iter);
+ }
+ 
+ /**
+@@ -314,9 +317,11 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
+ {
+ 	struct drm_device *dev = adev->ddev;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	u32 tmp;
+ 
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
+ 
+ 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
+@@ -328,6 +333,7 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
+ 
+ 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
+ 	}
++	drm_connector_list_iter_end(&iter);
+ }
+ 
+ static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
+@@ -1154,10 +1160,12 @@ static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
+ static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
+ 						struct drm_display_mode *mode)
+ {
+-	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
+ 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+ 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	struct amdgpu_connector *amdgpu_connector = NULL;
+ 	u32 tmp = 0, offset;
+ 
+@@ -1166,12 +1174,14 @@ static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
+ 
+ 	offset = dig->afmt->pin->offset;
+ 
+-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		if (connector->encoder == encoder) {
+ 			amdgpu_connector = to_amdgpu_connector(connector);
+ 			break;
+ 		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ 
+ 	if (!amdgpu_connector) {
+ 		DRM_ERROR("Couldn't find encoder's connector\n");
+@@ -1211,10 +1221,12 @@ static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
+ 
+ static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
+ {
+-	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
+ 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+ 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	struct amdgpu_connector *amdgpu_connector = NULL;
+ 	u32 offset, tmp;
+ 	u8 *sadb = NULL;
+@@ -1225,12 +1237,14 @@ static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
+ 
+ 	offset = dig->afmt->pin->offset;
+ 
+-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		if (connector->encoder == encoder) {
+ 			amdgpu_connector = to_amdgpu_connector(connector);
+ 			break;
+ 		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ 
+ 	if (!amdgpu_connector) {
+ 		DRM_ERROR("Couldn't find encoder's connector\n");
+@@ -1260,11 +1274,13 @@ static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
+ 
+ static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
+ {
+-	struct amdgpu_device *adev = encoder->dev->dev_private;
++	struct drm_device *dev = encoder->dev;
++	struct amdgpu_device *adev = dev->dev_private;
+ 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+ 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+ 	u32 offset;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	struct amdgpu_connector *amdgpu_connector = NULL;
+ 	struct cea_sad *sads;
+ 	int i, sad_count;
+@@ -1289,12 +1305,14 @@ static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
+ 
+ 	offset = dig->afmt->pin->offset;
+ 
+-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		if (connector->encoder == encoder) {
+ 			amdgpu_connector = to_amdgpu_connector(connector);
+ 			break;
+ 		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ 
+ 	if (!amdgpu_connector) {
+ 		DRM_ERROR("Couldn't find encoder's connector\n");
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 7ade3cbb5552..c654ec649ae5 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -928,27 +928,29 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev)
+ {
+ 	struct amdgpu_dm_connector *aconnector;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	int ret = 0;
+ 
+-	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
+-
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		aconnector = to_amdgpu_dm_connector(connector);
+ 		if (aconnector->dc_link->type == dc_connection_mst_branch &&
+ 		    aconnector->mst_mgr.aux) {
+ 			DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
+-					aconnector, aconnector->base.base.id);
++					 aconnector,
++					 aconnector->base.base.id);
+ 
+ 			ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
+ 			if (ret < 0) {
+ 				DRM_ERROR("DM_MST: Failed to start MST\n");
+-				((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
+-				return ret;
+-				}
++				aconnector->dc_link->type =
++					dc_connection_single;
++				break;
+ 			}
++		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ 
+-	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+ 	return ret;
+ }
+ 
+@@ -991,14 +993,13 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend)
+ {
+ 	struct amdgpu_dm_connector *aconnector;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	struct drm_dp_mst_topology_mgr *mgr;
+ 	int ret;
+ 	bool need_hotplug = false;
+ 
+-	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
+-
+-	list_for_each_entry(connector, &dev->mode_config.connector_list,
+-			    head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		aconnector = to_amdgpu_dm_connector(connector);
+ 		if (aconnector->dc_link->type != dc_connection_mst_branch ||
+ 		    aconnector->mst_port)
+@@ -1016,8 +1017,7 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend)
+ 			}
+ 		}
+ 	}
+-
+-	drm_modeset_unlock(&dev->mode_config.connection_mutex);
++	drm_connector_list_iter_end(&iter);
+ 
+ 	if (need_hotplug)
+ 		drm_kms_helper_hotplug_event(dev);
+@@ -1199,6 +1199,7 @@ static int dm_resume(void *handle)
+ 	struct amdgpu_display_manager *dm = &adev->dm;
+ 	struct amdgpu_dm_connector *aconnector;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 	struct drm_crtc *crtc;
+ 	struct drm_crtc_state *new_crtc_state;
+ 	struct dm_crtc_state *dm_new_crtc_state;
+@@ -1231,7 +1232,8 @@ static int dm_resume(void *handle)
+ 	s3_handle_mst(ddev, false);
+ 
+ 	/* Do detection*/
+-	list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(ddev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		aconnector = to_amdgpu_dm_connector(connector);
+ 
+ 		/*
+@@ -1259,6 +1261,7 @@ static int dm_resume(void *handle)
+ 		amdgpu_dm_update_connector_after_detect(aconnector);
+ 		mutex_unlock(&aconnector->hpd_lock);
+ 	}
++	drm_connector_list_iter_end(&iter);
+ 
+ 	/* Force mode set in atomic comit */
+ 	for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+index 4e6da61d1a93..c68ab269523e 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+@@ -734,8 +734,10 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev)
+ {
+ 	struct drm_device *dev = adev->ddev;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		struct amdgpu_dm_connector *amdgpu_dm_connector =
+ 				to_amdgpu_dm_connector(connector);
+ 
+@@ -753,6 +755,7 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev)
+ 					true);
+ 		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ }
+ 
+ /**
+@@ -767,8 +770,10 @@ void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)
+ {
+ 	struct drm_device *dev = adev->ddev;
+ 	struct drm_connector *connector;
++	struct drm_connector_list_iter iter;
+ 
+-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
++	drm_connector_list_iter_begin(dev, &iter);
++	drm_for_each_connector_iter(connector, &iter) {
+ 		struct amdgpu_dm_connector *amdgpu_dm_connector =
+ 				to_amdgpu_dm_connector(connector);
+ 		const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
+@@ -781,4 +786,5 @@ void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)
+ 					false);
+ 		}
+ 	}
++	drm_connector_list_iter_end(&iter);
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3997-drm-amdgpu-dm-mst-Remove-unnecessary-NULL-check.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3997-drm-amdgpu-dm-mst-Remove-unnecessary-NULL-check.patch
new file mode 100644
index 00000000..20ea3720
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3997-drm-amdgpu-dm-mst-Remove-unnecessary-NULL-check.patch
@@ -0,0 +1,34 @@
+From 20173bc1e4da5377836e08900bbc8fa83aebe7ad Mon Sep 17 00:00:00 2001
+From: Lyude Paul <lyude@redhat.com>
+Date: Thu, 26 Sep 2019 18:51:04 -0400
+Subject: [PATCH 3997/4256] drm/amdgpu/dm/mst: Remove unnecessary NULL check
+
+kfree() checks this automatically.
+
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Lyude Paul <lyude@redhat.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+index 98916da6d25f..cfca1924328e 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+@@ -144,10 +144,8 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector)
+ 	struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
+ 	struct amdgpu_encoder *amdgpu_encoder = amdgpu_dm_connector->mst_encoder;
+ 
+-	if (amdgpu_dm_connector->edid) {
+-		kfree(amdgpu_dm_connector->edid);
+-		amdgpu_dm_connector->edid = NULL;
+-	}
++	kfree(amdgpu_dm_connector->edid);
++	amdgpu_dm_connector->edid = NULL;
+ 
+ 	drm_encoder_cleanup(&amdgpu_encoder->base);
+ 	kfree(amdgpu_encoder);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3998-drm-amdgpu-dm-mst-Don-t-create-MST-topology-managers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3998-drm-amdgpu-dm-mst-Don-t-create-MST-topology-managers.patch
new file mode 100644
index 00000000..f0b5c81e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3998-drm-amdgpu-dm-mst-Don-t-create-MST-topology-managers.patch
@@ -0,0 +1,31 @@
+From 65cb3afc5505559c4ed4b652f50efa04fc0bd82b Mon Sep 17 00:00:00 2001
+From: Lyude Paul <lyude@redhat.com>
+Date: Thu, 26 Sep 2019 18:51:03 -0400
+Subject: [PATCH 3998/4256] drm/amdgpu/dm/mst: Don't create MST topology
+ managers for eDP ports
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Lyude Paul <lyude@redhat.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+index cfca1924328e..6406b92a1c05 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+@@ -412,6 +412,10 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
+ 	drm_dp_aux_register(&aconnector->dm_dp_aux.aux);
+ 	drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
+ 				      aconnector->base.name, dm->adev->dev);
++
++	if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
++		return;
++
+ 	aconnector->mst_mgr.cbs = &dm_mst_cbs;
+ 	drm_dp_mst_topology_mgr_init(
+ 		&aconnector->mst_mgr,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3999-drm-amdgpu-dm-mst-Use-atomic_best_encoder.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3999-drm-amdgpu-dm-mst-Use-atomic_best_encoder.patch
new file mode 100644
index 00000000..74091b7a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/3999-drm-amdgpu-dm-mst-Use-atomic_best_encoder.patch
@@ -0,0 +1,46 @@
+From bc5e7ba186d29b8f51d92974a1c5b09a33aaee22 Mon Sep 17 00:00:00 2001
+From: Lyude Paul <lyude@redhat.com>
+Date: Thu, 26 Sep 2019 18:51:05 -0400
+Subject: [PATCH 3999/4256] drm/amdgpu/dm/mst: Use ->atomic_best_encoder
+
+We are supposed to be atomic after all. We'll need this in a moment for
+the next commit.
+
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Lyude Paul <lyude@redhat.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c    | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+index 6406b92a1c05..430155730c29 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+@@ -242,17 +242,17 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
+ 	return ret;
+ }
+ 
+-static struct drm_encoder *dm_mst_best_encoder(struct drm_connector *connector)
++static struct drm_encoder *
++dm_mst_atomic_best_encoder(struct drm_connector *connector,
++			   struct drm_connector_state *connector_state)
+ {
+-	struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
+-
+-	return &amdgpu_dm_connector->mst_encoder->base;
++	return &to_amdgpu_dm_connector(connector)->mst_encoder->base;
+ }
+ 
+ static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
+ 	.get_modes = dm_dp_mst_get_modes,
+ 	.mode_valid = amdgpu_dm_connector_mode_valid,
+-	.best_encoder = dm_mst_best_encoder,
++	.atomic_best_encoder = dm_mst_atomic_best_encoder,
+ };
+ 
+ static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4000-drm-amdgpu-return-tcc_disabled_mask-to-userspace.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4000-drm-amdgpu-return-tcc_disabled_mask-to-userspace.patch
new file mode 100644
index 00000000..df96d0e1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4000-drm-amdgpu-return-tcc_disabled_mask-to-userspace.patch
@@ -0,0 +1,107 @@
+From 4cef9a6b14781fc9979f96e63bbcfa3a7ea2f30f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Tue, 24 Sep 2019 17:53:25 -0400
+Subject: [PATCH 4000/4256] drm/amdgpu: return tcc_disabled_mask to userspace
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+UMDs need this for correct programming of harvested chips.
+
+Signed-off-by: Marek Olšák <marek.olsak@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  3 ++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  2 ++
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 12 ++++++++++++
+ include/uapi/drm/amdgpu_drm.h           |  2 ++
+ 5 files changed, 19 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 82b20de92591..6d1ddde08de7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -80,9 +80,10 @@
+  * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
+  * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
+  * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
++ * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
+  */
+ #define KMS_DRIVER_MAJOR	3
+-#define KMS_DRIVER_MINOR	34
++#define KMS_DRIVER_MINOR	35
+ #define KMS_DRIVER_PATCHLEVEL	0
+ 
+ #define AMDGPU_VERSION          "19.10.9.418"
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+index c5179a807a04..35eff9e6ce16 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+@@ -165,6 +165,7 @@ struct amdgpu_gfx_config {
+ 	uint32_t num_sc_per_sh;
+ 	uint32_t num_packer_per_sc;
+ 	uint32_t pa_sc_tile_steering_override;
++	uint64_t tcc_disabled_mask;
+ };
+ 
+ struct amdgpu_cu_info {
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 75965119271b..20b11c024b87 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -793,6 +793,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
+ 			dev_info.pa_sc_tile_steering_override =
+ 				adev->gfx.config.pa_sc_tile_steering_override;
+ 
++		dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
++
+ 		return copy_to_user(out, &dev_info,
+ 				    min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
+ 	}
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index afe94b027112..9daf28e83236 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1678,6 +1678,17 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
+ 	}
+ }
+ 
++static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
++{
++	/* TCCs are global (not instanced). */
++	uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
++			       RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
++
++	adev->gfx.config.tcc_disabled_mask =
++		REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
++		(REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
++}
++
+ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
+ {
+ 	u32 tmp;
+@@ -1689,6 +1700,7 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
+ 
+ 	gfx_v10_0_setup_rb(adev);
+ 	gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
++	gfx_v10_0_get_tcc_info(adev);
+ 	adev->gfx.config.pa_sc_tile_steering_override =
+ 		gfx_v10_0_init_pa_sc_tile_steering_override(adev);
+ 
+diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
+index 65d49a894cbe..43a87fc23865 100644
+--- a/include/uapi/drm/amdgpu_drm.h
++++ b/include/uapi/drm/amdgpu_drm.h
+@@ -1085,6 +1085,8 @@ struct drm_amdgpu_info_device {
+ 	__u64 high_va_max;
+ 	/* gfx10 pa_sc_tile_steering_override */
+ 	__u32 pa_sc_tile_steering_override;
++	/* disabled TCCs */
++	__u64 tcc_disabled_mask;
+ };
+ 
+ struct drm_amdgpu_info_hw_ip {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4001-drm-amd-amdgpu-sriov-ip-block-setting-of-Arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4001-drm-amd-amdgpu-sriov-ip-block-setting-of-Arcturus.patch
new file mode 100644
index 00000000..6cd05670
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4001-drm-amd-amdgpu-sriov-ip-block-setting-of-Arcturus.patch
@@ -0,0 +1,77 @@
+From 1f2686376d9ec1ae178068f29b5b21c3080a447e Mon Sep 17 00:00:00 2001
+From: Jack Zhang <Jack.Zhang1@amd.com>
+Date: Thu, 26 Sep 2019 15:24:55 +0800
+Subject: [PATCH 4001/4256] drm/amd/amdgpu/sriov ip block setting of Arcturus
+
+Add ip block setting for Arcturus SRIOV
+
+1.PSP need to be initialized before IH.
+2.SMU doesn't need to be initialized at kmd driver.
+3.Arcturus doesn't support DCE hardware,it needs to skip
+  register access to DCE.
+
+Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10 ++++++----
+ drivers/gpu/drm/amd/amdgpu/soc15.c    | 18 ++++++++++++++----
+ 2 files changed, 20 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 5b6f97f4a875..2fa441d9c5a0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -1225,11 +1225,13 @@ static int gmc_v9_0_hw_init(void *handle)
+ 	gmc_v9_0_init_golden_registers(adev);
+ 
+ 	if (adev->mode_info.num_crtc) {
+-		/* Lockout access through VGA aperture*/
+-		WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
++		if (adev->asic_type != CHIP_ARCTURUS) {
++			/* Lockout access through VGA aperture*/
++			WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
+ 
+-		/* disable VGA render */
+-		WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
++			/* disable VGA render */
++			WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
++		}
+ 	}
+ 
+ 	r = gmc_v9_0_gart_enable(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index e168d4fa471c..eb87d04cb425 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -757,14 +757,24 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ 	case CHIP_ARCTURUS:
+ 		amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
+-		amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
+-		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+-			amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
++
++		if (amdgpu_sriov_vf(adev)) {
++			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
++				amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
++			amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
++		} else {
++			amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
++			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
++				amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
++		}
++
+ 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+ 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
+-		amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
++		if (!amdgpu_sriov_vf(adev))
++			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
++
+ 		if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT))
+ 			amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4002-drm-amd-display-memory-leak.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4002-drm-amd-display-memory-leak.patch
new file mode 100644
index 00000000..414ef5cd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4002-drm-amd-display-memory-leak.patch
@@ -0,0 +1,107 @@
+From d89f5e3fbf6812fa0caa7ea3e8fd8ed691f8dc87 Mon Sep 17 00:00:00 2001
+From: Navid Emamdoost <navid.emamdoost@gmail.com>
+Date: Mon, 16 Sep 2019 22:20:44 -0500
+Subject: [PATCH 4002/4256] drm/amd/display: memory leak
+
+In dcn*_clock_source_create when dcn20_clk_src_construct fails allocated
+clk_src needs release.
+
+Signed-off-by: Navid Emamdoost <navid.emamdoost@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 1 +
+ drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 1 +
+ drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 1 +
+ drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 1 +
+ drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c   | 1 +
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c   | 1 +
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c   | 1 +
+ 7 files changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+index e39c9a732f07..3614e516489f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+@@ -700,6 +700,7 @@ struct clock_source *dce100_clock_source_create(
+ 		return &clk_src->base;
+ 	}
+ 
++	kfree(clk_src);
+ 	BREAK_TO_DEBUGGER();
+ 	return NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index e8e018e2a67b..a487b75d23b6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -747,6 +747,7 @@ struct clock_source *dce110_clock_source_create(
+ 		return &clk_src->base;
+ 	}
+ 
++	kfree(clk_src);
+ 	BREAK_TO_DEBUGGER();
+ 	return NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+index de0b3785f0d2..ec67db9c86e8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+@@ -720,6 +720,7 @@ struct clock_source *dce112_clock_source_create(
+ 		return &clk_src->base;
+ 	}
+ 
++	kfree(clk_src);
+ 	BREAK_TO_DEBUGGER();
+ 	return NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index c47961549f0b..b5b9a74086a0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -529,6 +529,7 @@ static struct clock_source *dce120_clock_source_create(
+ 		return &clk_src->base;
+ 	}
+ 
++	kfree(clk_src);
+ 	BREAK_TO_DEBUGGER();
+ 	return NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+index ff35eff3f34b..8e2aa0abf87c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -734,6 +734,7 @@ struct clock_source *dce80_clock_source_create(
+ 		return &clk_src->base;
+ 	}
+ 
++	kfree(clk_src);
+ 	BREAK_TO_DEBUGGER();
+ 	return NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index eb8bc5538626..4522097e8a26 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -810,6 +810,7 @@ struct clock_source *dcn10_clock_source_create(
+ 		return &clk_src->base;
+ 	}
+ 
++	kfree(clk_src);
+ 	BREAK_TO_DEBUGGER();
+ 	return NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 035ef83be6cf..6072b919db5f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1106,6 +1106,7 @@ struct clock_source *dcn20_clock_source_create(
+ 		return &clk_src->base;
+ 	}
+ 
++	kfree(clk_src);
+ 	BREAK_TO_DEBUGGER();
+ 	return NULL;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4003-drm-amdgpu-display_mode_vba_21-remove-uint-typedef.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4003-drm-amdgpu-display_mode_vba_21-remove-uint-typedef.patch
new file mode 100644
index 00000000..e79fc6f7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4003-drm-amdgpu-display_mode_vba_21-remove-uint-typedef.patch
@@ -0,0 +1,84 @@
+From a25ee9d8fb628a8e77eddff96a2523e617ba4878 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Wed, 2 Oct 2019 14:01:24 +0200
+Subject: [PATCH 4003/4256] drm/amdgpu: display_mode_vba_21: remove uint
+ typedef
+
+The type definition for 'uint' clashes with the generic kernel
+headers:
+
+drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.c:43:22: error: redefinition of typedef 'uint' is a C11 feature [-Werror,-Wtypedef-redefinition]
+include/linux/types.h:92:23: note: previous definition is here
+
+Just remove this type and use plain 'unsigned int' consistently,
+as it is already use almost everywhere in this file.
+
+Fixes: b04641a3f4c5 ("drm/amd/display: Add Renoir DML")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../amd/display/dc/dml/dcn21/display_mode_vba_21.c  | 13 +++++--------
+ 1 file changed, 5 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+index 456cd0e3289c..3b6ed60dcd35 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+@@ -39,9 +39,6 @@
+  * ways. Unless there is something clearly wrong with it the code should
+  * remain as-is as it provides us with a guarantee from HW that it is correct.
+  */
+-
+-typedef unsigned int uint;
+-
+ typedef struct {
+ 	double DPPCLK;
+ 	double DISPCLK;
+@@ -4774,7 +4771,7 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
+ 				mode_lib->vba.MaximumReadBandwidthWithoutPrefetch = 0.0;
+ 				mode_lib->vba.MaximumReadBandwidthWithPrefetch = 0.0;
+ 				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
+-					uint m;
++					unsigned int m;
+ 
+ 					locals->cursor_bw[k] = 0;
+ 					locals->cursor_bw_pre[k] = 0;
+@@ -5285,7 +5282,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
+ 	double SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank;
+ 	double FullDETBufferingTimeYStutterCriticalPlane = 0;
+ 	double TimeToFinishSwathTransferStutterCriticalPlane = 0;
+-	uint k, j;
++	unsigned int k, j;
+ 
+ 	mode_lib->vba.TotalActiveDPP = 0;
+ 	mode_lib->vba.TotalDCCActiveDPP = 0;
+@@ -5507,7 +5504,7 @@ static void CalculateDCFCLKDeepSleep(
+ 		double DPPCLK[],
+ 		double *DCFCLKDeepSleep)
+ {
+-	uint k;
++	unsigned int k;
+ 	double DisplayPipeLineDeliveryTimeLuma;
+ 	double DisplayPipeLineDeliveryTimeChroma;
+ 	//double   DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
+@@ -5727,7 +5724,7 @@ static void CalculatePixelDeliveryTimes(
+ 		double DisplayPipeRequestDeliveryTimeChromaPrefetch[])
+ {
+ 	double req_per_swath_ub;
+-	uint k;
++	unsigned int k;
+ 
+ 	for (k = 0; k < NumberOfActivePlanes; ++k) {
+ 		if (VRatio[k] <= 1) {
+@@ -5869,7 +5866,7 @@ static void CalculateMetaAndPTETimes(
+ 	unsigned int dpte_groups_per_row_chroma_ub;
+ 	unsigned int num_group_per_lower_vm_stage;
+ 	unsigned int num_req_per_lower_vm_stage;
+-	uint k;
++	unsigned int k;
+ 
+ 	for (k = 0; k < NumberOfActivePlanes; ++k) {
+ 		if (GPUVMEnable == true) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4004-drm-amd-display-fix-spelling-mistake-AUTHENICATED-AU.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4004-drm-amd-display-fix-spelling-mistake-AUTHENICATED-AU.patch
new file mode 100644
index 00000000..0c022b3b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4004-drm-amd-display-fix-spelling-mistake-AUTHENICATED-AU.patch
@@ -0,0 +1,142 @@
+From 5228fb354120b3c2c2d5707bcfbffe284b81867d Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Thu, 3 Oct 2019 09:22:32 +0100
+Subject: [PATCH 4004/4256] drm/amd/display: fix spelling mistake AUTHENICATED
+ -> AUTHENTICATED
+
+There is a spelling mistake in the macros H1_A45_AUTHENICATED and
+D1_A4_AUTHENICATED, fix these by adding the missing T.
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h      |  4 ++--
+ .../drm/amd/display/modules/hdcp/hdcp1_execution.c   |  4 ++--
+ .../drm/amd/display/modules/hdcp/hdcp1_transition.c  | 12 ++++++------
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c  |  8 ++++----
+ 4 files changed, 14 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+index 402bb7999093..5664bc0b5bd0 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+@@ -176,7 +176,7 @@ enum mod_hdcp_hdcp1_state_id {
+ 	H1_A0_WAIT_FOR_ACTIVE_RX,
+ 	H1_A1_EXCHANGE_KSVS,
+ 	H1_A2_COMPUTATIONS_A3_VALIDATE_RX_A6_TEST_FOR_REPEATER,
+-	H1_A45_AUTHENICATED,
++	H1_A45_AUTHENTICATED,
+ 	H1_A8_WAIT_FOR_READY,
+ 	H1_A9_READ_KSV_LIST,
+ 	HDCP1_STATE_END = H1_A9_READ_KSV_LIST
+@@ -188,7 +188,7 @@ enum mod_hdcp_hdcp1_dp_state_id {
+ 	D1_A1_EXCHANGE_KSVS,
+ 	D1_A23_WAIT_FOR_R0_PRIME,
+ 	D1_A2_COMPUTATIONS_A3_VALIDATE_RX_A5_TEST_FOR_REPEATER,
+-	D1_A4_AUTHENICATED,
++	D1_A4_AUTHENTICATED,
+ 	D1_A6_WAIT_FOR_READY,
+ 	D1_A7_READ_KSV_LIST,
+ 	HDCP1_DP_STATE_END = D1_A7_READ_KSV_LIST,
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+index 9e7302eac299..3db4a7da414f 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+@@ -476,7 +476,7 @@ enum mod_hdcp_status mod_hdcp_hdcp1_execution(struct mod_hdcp *hdcp,
+ 		status = computations_validate_rx_test_for_repeater(hdcp,
+ 				event_ctx, input);
+ 		break;
+-	case H1_A45_AUTHENICATED:
++	case H1_A45_AUTHENTICATED:
+ 		status = authenticated(hdcp, event_ctx, input);
+ 		break;
+ 	case H1_A8_WAIT_FOR_READY:
+@@ -513,7 +513,7 @@ extern enum mod_hdcp_status mod_hdcp_hdcp1_dp_execution(struct mod_hdcp *hdcp,
+ 		status = computations_validate_rx_test_for_repeater(
+ 				hdcp, event_ctx, input);
+ 		break;
+-	case D1_A4_AUTHENICATED:
++	case D1_A4_AUTHENTICATED:
+ 		status = authenticated_dp(hdcp, event_ctx, input);
+ 		break;
+ 	case D1_A6_WAIT_FOR_READY:
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
+index 1d187809b709..136b8011ff3f 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
+@@ -81,11 +81,11 @@ enum mod_hdcp_status mod_hdcp_hdcp1_transition(struct mod_hdcp *hdcp,
+ 			set_state_id(hdcp, output, H1_A8_WAIT_FOR_READY);
+ 		} else {
+ 			callback_in_ms(0, output);
+-			set_state_id(hdcp, output, H1_A45_AUTHENICATED);
++			set_state_id(hdcp, output, H1_A45_AUTHENTICATED);
+ 			HDCP_FULL_DDC_TRACE(hdcp);
+ 		}
+ 		break;
+-	case H1_A45_AUTHENICATED:
++	case H1_A45_AUTHENTICATED:
+ 		if (input->link_maintenance != PASS) {
+ 			/* 1A-07: consider invalid ri' a failure */
+ 			/* 1A-07a: consider read ri' not returned a failure */
+@@ -129,7 +129,7 @@ enum mod_hdcp_status mod_hdcp_hdcp1_transition(struct mod_hdcp *hdcp,
+ 			break;
+ 		}
+ 		callback_in_ms(0, output);
+-		set_state_id(hdcp, output, H1_A45_AUTHENICATED);
++		set_state_id(hdcp, output, H1_A45_AUTHENTICATED);
+ 		HDCP_FULL_DDC_TRACE(hdcp);
+ 		break;
+ 	default:
+@@ -224,11 +224,11 @@ enum mod_hdcp_status mod_hdcp_hdcp1_dp_transition(struct mod_hdcp *hdcp,
+ 			set_watchdog_in_ms(hdcp, 5000, output);
+ 			set_state_id(hdcp, output, D1_A6_WAIT_FOR_READY);
+ 		} else {
+-			set_state_id(hdcp, output, D1_A4_AUTHENICATED);
++			set_state_id(hdcp, output, D1_A4_AUTHENTICATED);
+ 			HDCP_FULL_DDC_TRACE(hdcp);
+ 		}
+ 		break;
+-	case D1_A4_AUTHENICATED:
++	case D1_A4_AUTHENTICATED:
+ 		if (input->link_integiry_check != PASS ||
+ 				input->reauth_request_check != PASS) {
+ 			/* 1A-07: restart hdcp on a link integrity failure */
+@@ -295,7 +295,7 @@ enum mod_hdcp_status mod_hdcp_hdcp1_dp_transition(struct mod_hdcp *hdcp,
+ 			fail_and_restart_in_ms(0, &status, output);
+ 			break;
+ 		}
+-		set_state_id(hdcp, output, D1_A4_AUTHENICATED);
++		set_state_id(hdcp, output, D1_A4_AUTHENTICATED);
+ 		HDCP_FULL_DDC_TRACE(hdcp);
+ 		break;
+ 	default:
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
+index d868f556d180..3982ced5f969 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
+@@ -136,8 +136,8 @@ char *mod_hdcp_state_id_to_str(int32_t id)
+ 		return "H1_A1_EXCHANGE_KSVS";
+ 	case H1_A2_COMPUTATIONS_A3_VALIDATE_RX_A6_TEST_FOR_REPEATER:
+ 		return "H1_A2_COMPUTATIONS_A3_VALIDATE_RX_A6_TEST_FOR_REPEATER";
+-	case H1_A45_AUTHENICATED:
+-		return "H1_A45_AUTHENICATED";
++	case H1_A45_AUTHENTICATED:
++		return "H1_A45_AUTHENTICATED";
+ 	case H1_A8_WAIT_FOR_READY:
+ 		return "H1_A8_WAIT_FOR_READY";
+ 	case H1_A9_READ_KSV_LIST:
+@@ -150,8 +150,8 @@ char *mod_hdcp_state_id_to_str(int32_t id)
+ 		return "D1_A23_WAIT_FOR_R0_PRIME";
+ 	case D1_A2_COMPUTATIONS_A3_VALIDATE_RX_A5_TEST_FOR_REPEATER:
+ 		return "D1_A2_COMPUTATIONS_A3_VALIDATE_RX_A5_TEST_FOR_REPEATER";
+-	case D1_A4_AUTHENICATED:
+-		return "D1_A4_AUTHENICATED";
++	case D1_A4_AUTHENTICATED:
++		return "D1_A4_AUTHENTICATED";
+ 	case D1_A6_WAIT_FOR_READY:
+ 		return "D1_A6_WAIT_FOR_READY";
+ 	case D1_A7_READ_KSV_LIST:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4005-drm-amd-display-fix-struct-init-in-update_bounding_b.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4005-drm-amd-display-fix-struct-init-in-update_bounding_b.patch
new file mode 100644
index 00000000..ae01a78d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4005-drm-amd-display-fix-struct-init-in-update_bounding_b.patch
@@ -0,0 +1,43 @@
+From 7c345a2c6398fc016d112b75198e67a34a3d0d58 Mon Sep 17 00:00:00 2001
+From: Raul E Rangel <rrangel@chromium.org>
+Date: Thu, 3 Oct 2019 14:24:44 -0600
+Subject: [PATCH 4005/4256] drm/amd/display: fix struct init in
+ update_bounding_box
+
+dcn20_resource.c:2636:9: error: missing braces around initializer [-Werror=missing-braces]
+  struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES] = {0};
+         ^
+
+Fixes: 7ed4e6352c16f ("drm/amd/display: Add DCN2 HW Sequencer and Resource")
+
+Signed-off-by: Raul E Rangel <rrangel@chromium.org>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 6072b919db5f..502498675226 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -3044,7 +3044,7 @@ static void cap_soc_clocks(
+ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
+ 		struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
+ {
+-	struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES] = {0};
++	struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES];
+ 	int i;
+ 	int num_calculated_states = 0;
+ 	int min_dcfclk = 0;
+@@ -3052,6 +3052,8 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_
+ 	if (num_states == 0)
+ 		return;
+ 
++	memset(calculated_states, 0, sizeof(calculated_states));
++
+ 	if (dc->bb_overrides.min_dcfclk_mhz > 0)
+ 		min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
+ 	else
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4006-drm-amd-display-Make-some-functions-static.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4006-drm-amd-display-Make-some-functions-static.patch
new file mode 100644
index 00000000..ad8c3939
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4006-drm-amd-display-Make-some-functions-static.patch
@@ -0,0 +1,65 @@
+From 90e6f5802cde32f75987092b0f3caa1ce920650a Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Fri, 4 Oct 2019 17:37:40 +0800
+Subject: [PATCH 4006/4256] drm/amd/display: Make some functions static
+
+Fix sparse warnings:
+
+drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.c:32:6: warning: symbol 'lp_write_i2c' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.c:42:6: warning: symbol 'lp_read_i2c' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.c:52:6: warning: symbol 'lp_write_dpcd' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.c:59:6: warning: symbol 'lp_read_dpcd' was not declared. Should it be static?
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c   | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+index 2443c238c188..77181ddf6c8e 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+@@ -29,7 +29,8 @@
+ #include "dm_helpers.h"
+ #include <drm/drm_hdcp.h>
+ 
+-bool lp_write_i2c(void *handle, uint32_t address, const uint8_t *data, uint32_t size)
++static bool
++lp_write_i2c(void *handle, uint32_t address, const uint8_t *data, uint32_t size)
+ {
+ 
+ 	struct dc_link *link = handle;
+@@ -39,7 +40,8 @@ bool lp_write_i2c(void *handle, uint32_t address, const uint8_t *data, uint32_t
+ 	return dm_helpers_submit_i2c(link->ctx, link, &cmd);
+ }
+ 
+-bool lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t *data, uint32_t size)
++static bool
++lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t *data, uint32_t size)
+ {
+ 	struct dc_link *link = handle;
+ 
+@@ -49,14 +51,16 @@ bool lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t *data,
+ 	return dm_helpers_submit_i2c(link->ctx, link, &cmd);
+ }
+ 
+-bool lp_write_dpcd(void *handle, uint32_t address, const uint8_t *data, uint32_t size)
++static bool
++lp_write_dpcd(void *handle, uint32_t address, const uint8_t *data, uint32_t size)
+ {
+ 	struct dc_link *link = handle;
+ 
+ 	return dm_helpers_dp_write_dpcd(link->ctx, link, address, data, size);
+ }
+ 
+-bool lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t size)
++static bool
++lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t size)
+ {
+ 	struct dc_link *link = handle;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4007-drm-amd-display-Fix-typo-in-some-comments.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4007-drm-amd-display-Fix-typo-in-some-comments.patch
new file mode 100644
index 00000000..52f88c36
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4007-drm-amd-display-Fix-typo-in-some-comments.patch
@@ -0,0 +1,39 @@
+From 57e07b85b91be936f4724f78be592abe88529e71 Mon Sep 17 00:00:00 2001
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Date: Sat, 5 Oct 2019 13:32:05 +0200
+Subject: [PATCH 4007/4256] drm/amd/display: Fix typo in some comments
+
+p and g are switched in 'amdpgu_dm'
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index c654ec649ae5..8976321d1bcd 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -1025,7 +1025,7 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend)
+ 
+ /**
+  * dm_hw_init() - Initialize DC device
+- * @handle: The base driver device containing the amdpgu_dm device.
++ * @handle: The base driver device containing the amdgpu_dm device.
+  *
+  * Initialize the &struct amdgpu_display_manager device. This involves calling
+  * the initializers of each DM component, then populating the struct with them.
+@@ -1055,7 +1055,7 @@ static int dm_hw_init(void *handle)
+ 
+ /**
+  * dm_hw_fini() - Teardown DC device
+- * @handle: The base driver device containing the amdpgu_dm device.
++ * @handle: The base driver device containing the amdgpu_dm device.
+  *
+  * Teardown components within &struct amdgpu_display_manager that require
+  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4008-drm-amd-display-remove-set-but-not-used-variable-cor.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4008-drm-amd-display-remove-set-but-not-used-variable-cor.patch
new file mode 100644
index 00000000..ec9a978c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4008-drm-amd-display-remove-set-but-not-used-variable-cor.patch
@@ -0,0 +1,44 @@
+From 6d8803f44122c3a53036b82af028ea3d71bed8de Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Sun, 6 Oct 2019 18:57:35 +0800
+Subject: [PATCH 4008/4256] drm/amd/display: remove set but not used variable
+ 'core_freesync'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+rivers/gpu/drm/amd/amdgpu/../display/modules/freesync/freesync.c:
+ In function mod_freesync_get_settings:
+drivers/gpu/drm/amd/amdgpu/../display/modules/freesync/freesync.c:984:24:
+ warning: variable core_freesync set but not used [-Wunused-but-set-variable]
+
+It is not used since commit 98e6436d3af5 ("drm/amd/display: Refactor FreeSync module")
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+index 5e5ce9e5eab7..a978afac8b79 100644
+--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
++++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+@@ -979,13 +979,9 @@ void mod_freesync_get_settings(struct mod_freesync *mod_freesync,
+ 		unsigned int *inserted_frames,
+ 		unsigned int *inserted_duration_in_us)
+ {
+-	struct core_freesync *core_freesync = NULL;
+-
+ 	if (mod_freesync == NULL)
+ 		return;
+ 
+-	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
+-
+ 	if (vrr->supported) {
+ 		*v_total_min = vrr->adjust.v_total_min;
+ 		*v_total_max = vrr->adjust.v_total_max;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4009-drm-amd-display-Make-function-wait_for_alt_mode-stat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4009-drm-amd-display-Make-function-wait_for_alt_mode-stat.patch
new file mode 100644
index 00000000..31442d7c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4009-drm-amd-display-Make-function-wait_for_alt_mode-stat.patch
@@ -0,0 +1,34 @@
+From 0a6668178735fb59fa2ac0f59f6e0bf0bfcc8a8c Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Sat, 5 Oct 2019 10:44:32 +0800
+Subject: [PATCH 4009/4256] drm/amd/display: Make function wait_for_alt_mode
+ static
+
+Fix sparse warnings:
+
+drivers/gpu/drm/amd/display/dc/core/dc_link.c:687:6: warning: symbol 'wait_for_alt_mode' was not declared. Should it be static?
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 2da239765690..ec2a249c13f0 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -683,7 +683,7 @@ static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
+ 	return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
+ }
+ 
+-bool wait_for_alt_mode(struct dc_link *link)
++static bool wait_for_alt_mode(struct dc_link *link)
+ {
+ 
+ 	/**
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4010-drm-amd-display-Remove-set-but-not-used-variable-sou.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4010-drm-amd-display-Remove-set-but-not-used-variable-sou.patch
new file mode 100644
index 00000000..7feca09d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4010-drm-amd-display-Remove-set-but-not-used-variable-sou.patch
@@ -0,0 +1,46 @@
+From 2b7c94cd4151a4711c3184b74e82e199f548474f Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Sat, 5 Oct 2019 10:44:33 +0800
+Subject: [PATCH 4010/4256] drm/amd/display: Remove set but not used variable
+ 'source_bpp'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c: In function calc_rc_params:
+drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c:180:6: warning: variable source_bpp set but not used [-Wunused-but-set-variable]
+
+It is not used since commit 97bda0322b8a ("drm/amd/display:
+Add DSC support for Navi (v2)")
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
+index ca51e83f8764..76c4b12d6824 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
++++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
+@@ -177,7 +177,6 @@ void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_com
+ {
+ 	float bpp_group;
+ 	float initial_xmit_delay_factor;
+-	int source_bpp;
+ 	int padding_pixels;
+ 	int i;
+ 
+@@ -217,8 +216,6 @@ void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_com
+ 			rc->initial_xmit_delay++;
+ 	}
+ 
+-	source_bpp = MODE_SELECT(bpc * 3, bpc * 2, bpc * 1.5);
+-
+ 	rc->flatness_min_qp     = ((bpc == BPC_8) ?  (3) : ((bpc == BPC_10) ? (7)  : (11))) - ((minor_version == 1 && cm == CM_444) ? 1 : 0);
+ 	rc->flatness_max_qp     = ((bpc == BPC_8) ? (12) : ((bpc == BPC_10) ? (16) : (20))) - ((minor_version == 1 && cm == CM_444) ? 1 : 0);
+ 	rc->flatness_det_thresh = 2 << (bpc - 8);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4011-drm-amd-display-Remove-set-but-not-used-variables-h_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4011-drm-amd-display-Remove-set-but-not-used-variables-h_.patch
new file mode 100644
index 00000000..e71f28d1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4011-drm-amd-display-Remove-set-but-not-used-variables-h_.patch
@@ -0,0 +1,63 @@
+From 40874ac796a6fc1a59f740f151cc192861c96b9a Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Sat, 5 Oct 2019 10:44:34 +0800
+Subject: [PATCH 4011/4256] drm/amd/display: Remove set but not used variables
+ 'h_ratio_chroma', 'v_ratio_chroma'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c: In function dwb_program_horz_scalar:
+drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c:725:11: warning: variable h_ratio_chroma set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c: In function dwb_program_vert_scalar:
+drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c:806:11: warning: variable v_ratio_chroma set but not used [-Wunused-but-set-variable]
+
+They are not used since commit 345429a67c48 ("drm/amd/display:
+Add DCN2 DWB")
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
+index cd8bc92ce3ba..880954ac0b02 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
+@@ -722,7 +722,6 @@ bool dwb_program_horz_scalar(struct dcn20_dwbc *dwbc20,
+ 		struct scaling_taps num_taps)
+ {
+ 	uint32_t h_ratio_luma = 1;
+-	uint32_t h_ratio_chroma = 1;
+ 	uint32_t h_taps_luma = num_taps.h_taps;
+ 	uint32_t h_taps_chroma = num_taps.h_taps_c;
+ 	int32_t h_init_phase_luma = 0;
+@@ -747,7 +746,6 @@ bool dwb_program_horz_scalar(struct dcn20_dwbc *dwbc20,
+ 		h_ratio_luma = -1;
+ 	else
+ 		h_ratio_luma = dc_fixpt_u3d19(tmp_h_ratio_luma) << 5;
+-	h_ratio_chroma = h_ratio_luma * 2;
+ 
+ 	/*Program ratio*/
+ 	REG_UPDATE(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, h_ratio_luma);
+@@ -803,7 +801,6 @@ bool dwb_program_vert_scalar(struct dcn20_dwbc *dwbc20,
+ 		enum dwb_subsample_position subsample_position)
+ {
+ 	uint32_t v_ratio_luma = 1;
+-	uint32_t v_ratio_chroma = 1;
+ 	uint32_t v_taps_luma = num_taps.v_taps;
+ 	uint32_t v_taps_chroma = num_taps.v_taps_c;
+ 	int32_t v_init_phase_luma = 0;
+@@ -827,7 +824,6 @@ bool dwb_program_vert_scalar(struct dcn20_dwbc *dwbc20,
+ 		v_ratio_luma = -1;
+ 	else
+ 		v_ratio_luma = dc_fixpt_u3d19(tmp_v_ratio_luma) << 5;
+-	v_ratio_chroma = v_ratio_luma * 2;
+ 
+ 	/*Program ratio*/
+ 	REG_UPDATE(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, v_ratio_luma);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4012-drm-amd-display-Remove-set-but-not-used-variable-pix.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4012-drm-amd-display-Remove-set-but-not-used-variable-pix.patch
new file mode 100644
index 00000000..89e7efb9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4012-drm-amd-display-Remove-set-but-not-used-variable-pix.patch
@@ -0,0 +1,43 @@
+From dc9f973530f53aee83bb5b617f39d6008789a7a7 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Sat, 5 Oct 2019 10:44:35 +0800
+Subject: [PATCH 4012/4256] drm/amd/display: Remove set but not used variable
+ 'pixel_width'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c: In function dpp2_get_optimal_number_of_taps:
+drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c:359:11: warning: variable pixel_width set but not used [-Wunused-but-set-variable]
+
+It is not used since commit f7de96ee8b5f ("drm/amd/display:
+Add DCN2 DPP")
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 7 -------
+ 1 file changed, 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+index 2f5aade1e882..ae8534308229 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+@@ -376,13 +376,6 @@ bool dpp2_get_optimal_number_of_taps(
+ 		struct scaler_data *scl_data,
+ 		const struct scaling_taps *in_taps)
+ {
+-	uint32_t pixel_width;
+-
+-	if (scl_data->viewport.width > scl_data->recout.width)
+-		pixel_width = scl_data->recout.width;
+-	else
+-		pixel_width = scl_data->viewport.width;
+-
+ 	/* Some ASICs does not support  FP16 scaling, so we reject modes require this*/
+ 	if (scl_data->viewport.width  != scl_data->h_active &&
+ 		scl_data->viewport.height != scl_data->v_active &&
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4013-drm-amd-display-Remove-set-but-not-used-variables-pp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4013-drm-amd-display-Remove-set-but-not-used-variables-pp.patch
new file mode 100644
index 00000000..1c658472
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4013-drm-amd-display-Remove-set-but-not-used-variables-pp.patch
@@ -0,0 +1,90 @@
+From 2ad9e7aee166febfa02889c1501714a1b9ffc0b9 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Sat, 5 Oct 2019 10:44:36 +0800
+Subject: [PATCH 4013/4256] drm/amd/display: Remove set but not used variables
+ 'pp_smu', 'old_pipe'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c: In function dce110_enable_audio_stream:
+drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c:949:23: warning: variable pp_smu set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c: In function dce110_disable_audio_stream:
+drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c:983:23: warning: variable pp_smu set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c: In function dce110_program_front_end_for_pipe:
+drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c:2429:19: warning: variable old_pipe set but not used [-Wunused-but-set-variable]
+
+'pp_smu' is not used since commit 170a2398d2d8 ("drm/amd/display:
+make clk_mgr call enable_pme_wa")
+
+'old_pipe' is not used since commit 65d38262b3e8 ("drm/amd/display:
+fbc state could not reach while enable fbc")
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c  | 12 ------------
+ 1 file changed, 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index c273490ddcab..e11509506376 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -941,7 +941,6 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
+ {
+ 	/* notify audio driver for audio modes of monitor */
+ 	struct dc *core_dc;
+-	struct pp_smu_funcs *pp_smu = NULL;
+ 	struct clk_mgr *clk_mgr;
+ 	unsigned int i, num_audio = 1;
+ 
+@@ -954,9 +953,6 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
+ 	if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
+ 		return;
+ 
+-	if (core_dc->res_pool->pp_smu)
+-		pp_smu = core_dc->res_pool->pp_smu;
+-
+ 	if (pipe_ctx->stream_res.audio) {
+ 		for (i = 0; i < MAX_PIPES; i++) {
+ 			/*current_state not updated yet*/
+@@ -981,7 +977,6 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
+ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
+ {
+ 	struct dc *dc;
+-	struct pp_smu_funcs *pp_smu = NULL;
+ 	struct clk_mgr *clk_mgr;
+ 
+ 	if (!pipe_ctx || !pipe_ctx->stream)
+@@ -998,9 +993,6 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
+ 	if (pipe_ctx->stream_res.audio) {
+ 		pipe_ctx->stream_res.audio->enabled = false;
+ 
+-		if (dc->res_pool->pp_smu)
+-			pp_smu = dc->res_pool->pp_smu;
+-
+ 		if (dc_is_dp_signal(pipe_ctx->stream->signal))
+ 			pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
+ 					pipe_ctx->stream_res.stream_enc);
+@@ -2461,7 +2453,6 @@ static void dce110_program_front_end_for_pipe(
+ 		struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	struct mem_input *mi = pipe_ctx->plane_res.mi;
+-	struct pipe_ctx *old_pipe = NULL;
+ 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+ 	struct xfm_grph_csc_adjustment adjust;
+ 	struct out_csc_color_matrix tbl_entry;
+@@ -2469,9 +2460,6 @@ static void dce110_program_front_end_for_pipe(
+ 	DC_LOGGER_INIT();
+ 	memset(&tbl_entry, 0, sizeof(tbl_entry));
+ 
+-	if (dc->current_state)
+-		old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
+-
+ 	memset(&adjust, 0, sizeof(adjust));
+ 	adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4014-drm-amd-powerplay-add-more-feature-bits.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4014-drm-amd-powerplay-add-more-feature-bits.patch
new file mode 100644
index 00000000..79741ae7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4014-drm-amd-powerplay-add-more-feature-bits.patch
@@ -0,0 +1,43 @@
+From eb4a5dc05e1ac45e349f1e41251b6d63b740a499 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 9 Oct 2019 16:40:59 +0800
+Subject: [PATCH 4014/4256] drm/amd/powerplay: add more feature bits
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 7c0c5bc28fcc..e6490d2eb4f2 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -337,19 +337,22 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
+ 				| FEATURE_MASK(FEATURE_PPT_BIT)
+ 				| FEATURE_MASK(FEATURE_TDC_BIT)
+ 				| FEATURE_MASK(FEATURE_GFX_EDC_BIT)
++				| FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
+ 				| FEATURE_MASK(FEATURE_VR0HOT_BIT)
+ 				| FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
+ 				| FEATURE_MASK(FEATURE_THERMAL_BIT)
+ 				| FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
+ 				| FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
+ 				| FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)
++				| FEATURE_MASK(FEATURE_DS_LCLK_BIT)
+ 				| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
+ 				| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
+ 				| FEATURE_MASK(FEATURE_BACO_BIT)
+ 				| FEATURE_MASK(FEATURE_ACDC_BIT)
+ 				| FEATURE_MASK(FEATURE_GFX_SS_BIT)
+ 				| FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
+-				| FEATURE_MASK(FEATURE_FW_CTF_BIT);
++				| FEATURE_MASK(FEATURE_FW_CTF_BIT)
++				| FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
+ 
+ 	if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
+ 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4015-drm-amdgpu-add-lock-for-i2c-bus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4015-drm-amdgpu-add-lock-for-i2c-bus.patch
new file mode 100644
index 00000000..61a25548
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4015-drm-amdgpu-add-lock-for-i2c-bus.patch
@@ -0,0 +1,42 @@
+From 35f31816a1fcb441728ee33103c023cb918fb78d Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Thu, 10 Oct 2019 16:41:54 +0800
+Subject: [PATCH 4015/4256] drm/amdgpu: add lock for i2c bus
+
+I2C bus must be locked at all time we access the I2C bus.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Rui Teng <rui.teng@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
+index aad83932dd05..15674337144f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
++++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
+@@ -630,6 +630,10 @@ static int smu_v11_0_i2c_eeprom_i2c_xfer(struct i2c_adapter *i2c_adap,
+ 	int i, ret;
+ 	struct amdgpu_ras_eeprom_control *control = to_eeprom_control(i2c_adap);
+ 
++#if !defined(HAVE_I2C_LOCK_OPERATIONS_STRUCT)
++	lock_bus(i2c_adap, 0);
++#endif
++
+ 	if (!control->bus_locked) {
+ 		DRM_ERROR("I2C bus unlocked, stopping transaction!");
+ 		return -EIO;
+@@ -654,6 +658,10 @@ static int smu_v11_0_i2c_eeprom_i2c_xfer(struct i2c_adapter *i2c_adap,
+ 	}
+ 
+ 	smu_v11_0_i2c_fini(i2c_adap);
++
++#if !defined(HAVE_I2C_LOCK_OPERATIONS_STRUCT)
++	unlock_bus(i2c_adap, 0);
++#endif
+ 	return num;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4016-drm-amdgpu-Delete-useless-header-file-reference.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4016-drm-amdgpu-Delete-useless-header-file-reference.patch
new file mode 100644
index 00000000..a97bc583
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4016-drm-amdgpu-Delete-useless-header-file-reference.patch
@@ -0,0 +1,166 @@
+From 5dccfcdb4ec8c8dcbbe2fe78f6afacf8f1083226 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Sat, 21 Sep 2019 15:51:19 -0400
+Subject: [PATCH 4016/4256] drm/amdgpu: Delete useless header file reference
+
+Those header file includes are not needed.
+
+Change-Id: I44aa7e4d0391f9b2c2be757765c1437b603688ae
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c | 6 ------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c  | 2 --
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c  | 3 ---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c  | 4 ----
+ drivers/gpu/drm/amd/amdgpu/arct_reg_init.c         | 1 -
+ drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c       | 1 -
+ drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c       | 1 -
+ drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c       | 1 -
+ drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c       | 1 -
+ drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c       | 1 -
+ 10 files changed, 21 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+index 57ff698f51bb..684087839c7a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+@@ -22,16 +22,10 @@
+ #undef pr_fmt
+ #define pr_fmt(fmt) "kfd2kgd: " fmt
+ 
+-#include <linux/module.h>
+-#include <linux/fdtable.h>
+-#include <linux/uaccess.h>
+-#include <linux/firmware.h>
+ #include <linux/mmu_context.h>
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
+ #include "amdgpu_amdkfd.h"
+-#include "amdgpu_ucode.h"
+-#include "soc15_hw_ip.h"
+ #include "gc/gc_10_1_0_offset.h"
+ #include "gc/gc_10_1_0_sh_mask.h"
+ #include "navi10_enum.h"
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+index ac811361246d..c5078223fac3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+@@ -23,8 +23,6 @@
+ #undef pr_fmt
+ #define pr_fmt(fmt) "kfd2kgd: " fmt
+ 
+-#include <linux/fdtable.h>
+-#include <linux/uaccess.h>
+ #include <linux/mmu_context.h>
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+index b7f0d594ec7b..fabf0dbb3e69 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+@@ -23,9 +23,6 @@
+ #undef pr_fmt
+ #define pr_fmt(fmt) "kfd2kgd: " fmt
+ 
+-#include <linux/module.h>
+-#include <linux/fdtable.h>
+-#include <linux/uaccess.h>
+ #include <linux/mmu_context.h>
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+index 04448869abff..9c4992d8f4b7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+@@ -23,15 +23,11 @@
+ #undef pr_fmt
+ #define pr_fmt(fmt) "kfd2kgd: " fmt
+ 
+-#include <linux/module.h>
+-#include <linux/fdtable.h>
+-#include <linux/uaccess.h>
+ #include <linux/mmu_context.h>
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
+ #include "amdgpu_amdkfd.h"
+ #include "amdgpu_amdkfd_gfx_v8.h"
+-#include "soc15_hw_ip.h"
+ #include "gc/gc_9_0_offset.h"
+ #include "gc/gc_9_0_sh_mask.h"
+ #include "vega10_enum.h"
+diff --git a/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c b/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c
+index e62609d5126b..fda99c958c3b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c
++++ b/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c
+@@ -24,7 +24,6 @@
+ #include "soc15.h"
+ 
+ #include "soc15_common.h"
+-#include "soc15_hw_ip.h"
+ #include "arct_ip_offset.h"
+ 
+ int arct_reg_base_init(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
+index a56c93620e78..88efaecf9f70 100644
+--- a/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
++++ b/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
+@@ -24,7 +24,6 @@
+ #include "nv.h"
+ 
+ #include "soc15_common.h"
+-#include "soc15_hw_ip.h"
+ #include "navi10_ip_offset.h"
+ 
+ int navi10_reg_base_init(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c b/drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c
+index cadc7603ca41..a786d159e5e9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c
++++ b/drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c
+@@ -24,7 +24,6 @@
+ #include "nv.h"
+ 
+ #include "soc15_common.h"
+-#include "soc15_hw_ip.h"
+ #include "navi12_ip_offset.h"
+ 
+ int navi12_reg_base_init(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c b/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c
+index 3b5f0f65e096..4ea1e8fbb601 100644
+--- a/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c
++++ b/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c
+@@ -24,7 +24,6 @@
+ #include "nv.h"
+ 
+ #include "soc15_common.h"
+-#include "soc15_hw_ip.h"
+ #include "navi14_ip_offset.h"
+ 
+ int navi14_reg_base_init(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+index bd0580334f83..6b52a539d51b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
++++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+@@ -24,7 +24,6 @@
+ #include "soc15.h"
+ 
+ #include "soc15_common.h"
+-#include "soc15_hw_ip.h"
+ #include "vega10_ip_offset.h"
+ 
+ int vega10_reg_base_init(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+index 587e33f5dcce..556f854e3551 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
++++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+@@ -24,7 +24,6 @@
+ #include "soc15.h"
+ 
+ #include "soc15_common.h"
+-#include "soc15_hw_ip.h"
+ #include "vega20_ip_offset.h"
+ 
+ int vega20_reg_base_init(struct amdgpu_device *adev)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4017-drm-amdkfd-Delete-unnecessary-function-declarations.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4017-drm-amdkfd-Delete-unnecessary-function-declarations.patch
new file mode 100644
index 00000000..fb711405
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4017-drm-amdkfd-Delete-unnecessary-function-declarations.patch
@@ -0,0 +1,434 @@
+From 958dec157774c9331eab09ba3a2fdc969d270911 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 27 Sep 2019 21:22:07 -0400
+Subject: [PATCH 4017/4256] drm/amdkfd: Delete unnecessary function
+ declarations
+
+Ajust the function sequences so that those function delcarations are not
+needed any more.
+
+Change-Id: I3a270ade7ac380cd083e90611177d7a45249823f
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c    | 115 +++++------------
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 118 +++++-------------
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 114 +++++------------
+ 3 files changed, 90 insertions(+), 257 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+index 684087839c7a..c1f194f9c515 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+@@ -46,61 +46,6 @@ enum hqd_dequeue_request_type {
+ 	SAVE_WAVES
+ };
+ 
+-/*
+- * Register access functions
+- */
+-
+-static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
+-		uint32_t sh_mem_config,
+-		uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
+-		uint32_t sh_mem_bases);
+-static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
+-		unsigned int vmid);
+-static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
+-static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
+-			uint32_t queue_id, uint32_t __user *wptr,
+-			uint32_t wptr_shift, uint32_t wptr_mask,
+-			struct mm_struct *mm);
+-static int kgd_hqd_dump(struct kgd_dev *kgd,
+-			uint32_t pipe_id, uint32_t queue_id,
+-			uint32_t (**dump)[2], uint32_t *n_regs);
+-static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+-			     uint32_t __user *wptr, struct mm_struct *mm);
+-static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
+-			     uint32_t engine_id, uint32_t queue_id,
+-			     uint32_t (**dump)[2], uint32_t *n_regs);
+-static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
+-		uint32_t pipe_id, uint32_t queue_id);
+-static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
+-static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
+-				enum kfd_preempt_type reset_type,
+-				unsigned int utimeout, uint32_t pipe_id,
+-				uint32_t queue_id);
+-static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+-				unsigned int utimeout);
+-#if 0
+-static uint32_t get_watch_base_addr(struct amdgpu_device *adev);
+-#endif
+-static int kgd_address_watch_disable(struct kgd_dev *kgd);
+-static int kgd_address_watch_execute(struct kgd_dev *kgd,
+-					unsigned int watch_point_id,
+-					uint32_t cntl_val,
+-					uint32_t addr_hi,
+-					uint32_t addr_lo);
+-static int kgd_wave_control_execute(struct kgd_dev *kgd,
+-					uint32_t gfx_index_val,
+-					uint32_t sq_cmd);
+-static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
+-					unsigned int watch_point_id,
+-					unsigned int reg_offset);
+-
+-static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
+-					uint8_t vmid, uint16_t *p_pasid);
+-static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
+-		uint64_t page_table_base);
+-static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
+-static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
+-
+ /* Because of REG_GET_FIELD() being used, we put this function in the
+  * asic specific file.
+  */
+@@ -133,36 +78,6 @@ static int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
+ 	return 0;
+ }
+ 
+-static const struct kfd2kgd_calls kfd2kgd = {
+-	.program_sh_mem_settings = kgd_program_sh_mem_settings,
+-	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
+-	.init_interrupts = kgd_init_interrupts,
+-	.hqd_load = kgd_hqd_load,
+-	.hqd_sdma_load = kgd_hqd_sdma_load,
+-	.hqd_dump = kgd_hqd_dump,
+-	.hqd_sdma_dump = kgd_hqd_sdma_dump,
+-	.hqd_is_occupied = kgd_hqd_is_occupied,
+-	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
+-	.hqd_destroy = kgd_hqd_destroy,
+-	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
+-	.address_watch_disable = kgd_address_watch_disable,
+-	.address_watch_execute = kgd_address_watch_execute,
+-	.wave_control_execute = kgd_wave_control_execute,
+-	.address_watch_get_offset = kgd_address_watch_get_offset,
+-	.get_atc_vmid_pasid_mapping_info =
+-			get_atc_vmid_pasid_mapping_info,
+-	.get_tile_config = amdgpu_amdkfd_get_tile_config,
+-	.set_vm_context_page_table_base = set_vm_context_page_table_base,
+-	.invalidate_tlbs = invalidate_tlbs,
+-	.invalidate_tlbs_vmid = invalidate_tlbs_vmid,
+-	.get_hive_id = amdgpu_amdkfd_get_hive_id,
+-};
+-
+-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions()
+-{
+-	return (struct kfd2kgd_calls *)&kfd2kgd;
+-}
+-
+ static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
+ {
+ 	return (struct amdgpu_device *)kgd;
+@@ -900,3 +815,33 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
+ 	/* SDMA is on gfxhub as well for Navi1* series */
+ 	gfxhub_v2_0_setup_vm_pt_regs(adev, vmid, page_table_base);
+ }
++
++static const struct kfd2kgd_calls kfd2kgd = {
++	.program_sh_mem_settings = kgd_program_sh_mem_settings,
++	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
++	.init_interrupts = kgd_init_interrupts,
++	.hqd_load = kgd_hqd_load,
++	.hqd_sdma_load = kgd_hqd_sdma_load,
++	.hqd_dump = kgd_hqd_dump,
++	.hqd_sdma_dump = kgd_hqd_sdma_dump,
++	.hqd_is_occupied = kgd_hqd_is_occupied,
++	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
++	.hqd_destroy = kgd_hqd_destroy,
++	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
++	.address_watch_disable = kgd_address_watch_disable,
++	.address_watch_execute = kgd_address_watch_execute,
++	.wave_control_execute = kgd_wave_control_execute,
++	.address_watch_get_offset = kgd_address_watch_get_offset,
++	.get_atc_vmid_pasid_mapping_info =
++			get_atc_vmid_pasid_mapping_info,
++	.get_tile_config = amdgpu_amdkfd_get_tile_config,
++	.set_vm_context_page_table_base = set_vm_context_page_table_base,
++	.invalidate_tlbs = invalidate_tlbs,
++	.invalidate_tlbs_vmid = invalidate_tlbs_vmid,
++	.get_hive_id = amdgpu_amdkfd_get_hive_id,
++};
++
++struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions()
++{
++	return (struct kfd2kgd_calls *)&kfd2kgd;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+index c5078223fac3..f0ef2e64f592 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+@@ -87,64 +87,6 @@ union TCP_WATCH_CNTL_BITS {
+ 	float f32All;
+ };
+ 
+-/*
+- * Register access functions
+- */
+-
+-static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
+-		uint32_t sh_mem_config,	uint32_t sh_mem_ape1_base,
+-		uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
+-
+-static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
+-					unsigned int vmid);
+-
+-static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
+-static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
+-			uint32_t queue_id, uint32_t __user *wptr,
+-			uint32_t wptr_shift, uint32_t wptr_mask,
+-			struct mm_struct *mm);
+-static int kgd_hqd_dump(struct kgd_dev *kgd,
+-			uint32_t pipe_id, uint32_t queue_id,
+-			uint32_t (**dump)[2], uint32_t *n_regs);
+-static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+-			     uint32_t __user *wptr, struct mm_struct *mm);
+-static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
+-			     uint32_t engine_id, uint32_t queue_id,
+-			     uint32_t (**dump)[2], uint32_t *n_regs);
+-static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
+-				uint32_t pipe_id, uint32_t queue_id);
+-
+-static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
+-				enum kfd_preempt_type reset_type,
+-				unsigned int utimeout, uint32_t pipe_id,
+-				uint32_t queue_id);
+-static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
+-static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+-				unsigned int utimeout);
+-static int kgd_address_watch_disable(struct kgd_dev *kgd);
+-static int kgd_address_watch_execute(struct kgd_dev *kgd,
+-					unsigned int watch_point_id,
+-					uint32_t cntl_val,
+-					uint32_t addr_hi,
+-					uint32_t addr_lo);
+-static int kgd_wave_control_execute(struct kgd_dev *kgd,
+-					uint32_t gfx_index_val,
+-					uint32_t sq_cmd);
+-static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
+-					unsigned int watch_point_id,
+-					unsigned int reg_offset);
+-
+-static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
+-					uint8_t vmid, uint16_t *p_pasid);
+-
+-static void set_scratch_backing_va(struct kgd_dev *kgd,
+-					uint64_t va, uint32_t vmid);
+-static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
+-		uint64_t page_table_base);
+-static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
+-static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
+-static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd);
+-
+ /* Because of REG_GET_FIELD() being used, we put this function in the
+  * asic specific file.
+  */
+@@ -170,36 +112,6 @@ static int get_tile_config(struct kgd_dev *kgd,
+ 	return 0;
+ }
+ 
+-static const struct kfd2kgd_calls kfd2kgd = {
+-	.program_sh_mem_settings = kgd_program_sh_mem_settings,
+-	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
+-	.init_interrupts = kgd_init_interrupts,
+-	.hqd_load = kgd_hqd_load,
+-	.hqd_sdma_load = kgd_hqd_sdma_load,
+-	.hqd_dump = kgd_hqd_dump,
+-	.hqd_sdma_dump = kgd_hqd_sdma_dump,
+-	.hqd_is_occupied = kgd_hqd_is_occupied,
+-	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
+-	.hqd_destroy = kgd_hqd_destroy,
+-	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
+-	.address_watch_disable = kgd_address_watch_disable,
+-	.address_watch_execute = kgd_address_watch_execute,
+-	.wave_control_execute = kgd_wave_control_execute,
+-	.address_watch_get_offset = kgd_address_watch_get_offset,
+-	.get_atc_vmid_pasid_mapping_info = get_atc_vmid_pasid_mapping_info,
+-	.set_scratch_backing_va = set_scratch_backing_va,
+-	.get_tile_config = get_tile_config,
+-	.set_vm_context_page_table_base = set_vm_context_page_table_base,
+-	.invalidate_tlbs = invalidate_tlbs,
+-	.invalidate_tlbs_vmid = invalidate_tlbs_vmid,
+-	.read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg,
+-};
+-
+-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
+-{
+-	return (struct kfd2kgd_calls *)&kfd2kgd;
+-}
+-
+ static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
+ {
+ 	return (struct amdgpu_device *)kgd;
+@@ -841,3 +753,33 @@ static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd)
+ 
+ 	return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
+ }
++
++static const struct kfd2kgd_calls kfd2kgd = {
++	.program_sh_mem_settings = kgd_program_sh_mem_settings,
++	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
++	.init_interrupts = kgd_init_interrupts,
++	.hqd_load = kgd_hqd_load,
++	.hqd_sdma_load = kgd_hqd_sdma_load,
++	.hqd_dump = kgd_hqd_dump,
++	.hqd_sdma_dump = kgd_hqd_sdma_dump,
++	.hqd_is_occupied = kgd_hqd_is_occupied,
++	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
++	.hqd_destroy = kgd_hqd_destroy,
++	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
++	.address_watch_disable = kgd_address_watch_disable,
++	.address_watch_execute = kgd_address_watch_execute,
++	.wave_control_execute = kgd_wave_control_execute,
++	.address_watch_get_offset = kgd_address_watch_get_offset,
++	.get_atc_vmid_pasid_mapping_info = get_atc_vmid_pasid_mapping_info,
++	.set_scratch_backing_va = set_scratch_backing_va,
++	.get_tile_config = get_tile_config,
++	.set_vm_context_page_table_base = set_vm_context_page_table_base,
++	.invalidate_tlbs = invalidate_tlbs,
++	.invalidate_tlbs_vmid = invalidate_tlbs_vmid,
++	.read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg,
++};
++
++struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
++{
++	return (struct kfd2kgd_calls *)&kfd2kgd;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+index fabf0dbb3e69..17a31c1b1272 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+@@ -51,60 +51,6 @@ static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = {
+ 	mmTCP_WATCH3_ADDR_H, mmTCP_WATCH3_ADDR_L, mmTCP_WATCH3_CNTL
+ };
+ 
+-/*
+- * Register access functions
+- */
+-
+-static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
+-		uint32_t sh_mem_config,
+-		uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
+-		uint32_t sh_mem_bases);
+-static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
+-		unsigned int vmid);
+-static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
+-static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
+-			uint32_t queue_id, uint32_t __user *wptr,
+-			uint32_t wptr_shift, uint32_t wptr_mask,
+-			struct mm_struct *mm);
+-static int kgd_hqd_dump(struct kgd_dev *kgd,
+-			uint32_t pipe_id, uint32_t queue_id,
+-			uint32_t (**dump)[2], uint32_t *n_regs);
+-static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+-			     uint32_t __user *wptr, struct mm_struct *mm);
+-static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
+-			     uint32_t engine_id, uint32_t queue_id,
+-			     uint32_t (**dump)[2], uint32_t *n_regs);
+-static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
+-		uint32_t pipe_id, uint32_t queue_id);
+-static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
+-static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
+-				enum kfd_preempt_type reset_type,
+-				unsigned int utimeout, uint32_t pipe_id,
+-				uint32_t queue_id);
+-static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+-				unsigned int utimeout);
+-static int kgd_address_watch_disable(struct kgd_dev *kgd);
+-static int kgd_address_watch_execute(struct kgd_dev *kgd,
+-					unsigned int watch_point_id,
+-					uint32_t cntl_val,
+-					uint32_t addr_hi,
+-					uint32_t addr_lo);
+-static int kgd_wave_control_execute(struct kgd_dev *kgd,
+-					uint32_t gfx_index_val,
+-					uint32_t sq_cmd);
+-static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
+-					unsigned int watch_point_id,
+-					unsigned int reg_offset);
+-
+-static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
+-					uint8_t vmid, uint16_t *p_pasid);
+-static void set_scratch_backing_va(struct kgd_dev *kgd,
+-					uint64_t va, uint32_t vmid);
+-static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
+-		uint64_t page_table_base);
+-static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
+-static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
+-
+ /* Because of REG_GET_FIELD() being used, we put this function in the
+  * asic specific file.
+  */
+@@ -130,36 +76,6 @@ static int get_tile_config(struct kgd_dev *kgd,
+ 	return 0;
+ }
+ 
+-static const struct kfd2kgd_calls kfd2kgd = {
+-	.program_sh_mem_settings = kgd_program_sh_mem_settings,
+-	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
+-	.init_interrupts = kgd_init_interrupts,
+-	.hqd_load = kgd_hqd_load,
+-	.hqd_sdma_load = kgd_hqd_sdma_load,
+-	.hqd_dump = kgd_hqd_dump,
+-	.hqd_sdma_dump = kgd_hqd_sdma_dump,
+-	.hqd_is_occupied = kgd_hqd_is_occupied,
+-	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
+-	.hqd_destroy = kgd_hqd_destroy,
+-	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
+-	.address_watch_disable = kgd_address_watch_disable,
+-	.address_watch_execute = kgd_address_watch_execute,
+-	.wave_control_execute = kgd_wave_control_execute,
+-	.address_watch_get_offset = kgd_address_watch_get_offset,
+-	.get_atc_vmid_pasid_mapping_info =
+-			get_atc_vmid_pasid_mapping_info,
+-	.set_scratch_backing_va = set_scratch_backing_va,
+-	.get_tile_config = get_tile_config,
+-	.set_vm_context_page_table_base = set_vm_context_page_table_base,
+-	.invalidate_tlbs = invalidate_tlbs,
+-	.invalidate_tlbs_vmid = invalidate_tlbs_vmid,
+-};
+-
+-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
+-{
+-	return (struct kfd2kgd_calls *)&kfd2kgd;
+-}
+-
+ static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
+ {
+ 	return (struct amdgpu_device *)kgd;
+@@ -870,3 +786,33 @@ static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
+ 	RREG32(mmVM_INVALIDATE_RESPONSE);
+ 	return 0;
+ }
++
++static const struct kfd2kgd_calls kfd2kgd = {
++	.program_sh_mem_settings = kgd_program_sh_mem_settings,
++	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
++	.init_interrupts = kgd_init_interrupts,
++	.hqd_load = kgd_hqd_load,
++	.hqd_sdma_load = kgd_hqd_sdma_load,
++	.hqd_dump = kgd_hqd_dump,
++	.hqd_sdma_dump = kgd_hqd_sdma_dump,
++	.hqd_is_occupied = kgd_hqd_is_occupied,
++	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
++	.hqd_destroy = kgd_hqd_destroy,
++	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
++	.address_watch_disable = kgd_address_watch_disable,
++	.address_watch_execute = kgd_address_watch_execute,
++	.wave_control_execute = kgd_wave_control_execute,
++	.address_watch_get_offset = kgd_address_watch_get_offset,
++	.get_atc_vmid_pasid_mapping_info =
++			get_atc_vmid_pasid_mapping_info,
++	.set_scratch_backing_va = set_scratch_backing_va,
++	.get_tile_config = get_tile_config,
++	.set_vm_context_page_table_base = set_vm_context_page_table_base,
++	.invalidate_tlbs = invalidate_tlbs,
++	.invalidate_tlbs_vmid = invalidate_tlbs_vmid,
++};
++
++struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
++{
++	return (struct kfd2kgd_calls *)&kfd2kgd;
++}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4018-drm-amdkfd-Use-array-to-probe-kfd2kgd_calls.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4018-drm-amdkfd-Use-array-to-probe-kfd2kgd_calls.patch
new file mode 100644
index 00000000..471575be
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4018-drm-amdkfd-Use-array-to-probe-kfd2kgd_calls.patch
@@ -0,0 +1,322 @@
+From 8163b2a036a633ae41a6793b2f620f7c0a048f7e Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 27 Sep 2019 22:03:42 -0400
+Subject: [PATCH 4018/4256] drm/amdkfd: Use array to probe kfd2kgd_calls
+
+This is the same idea as the kfd device info probe and move all the
+probe control together for easy maintenance and fix the build when CIK support is
+disabled.
+
+Change-Id: I85c98bb08eb2a4a1a80c3b913c32691cc74602d1
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c    | 65 +------------------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h    |  6 --
+ .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c   |  8 +--
+ .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c    |  7 +-
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c |  7 +-
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c |  7 +-
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c |  7 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c       | 45 +++++++++++--
+ 8 files changed, 47 insertions(+), 105 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+index 9a3ab7fde205..1783883e40b6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+@@ -69,48 +69,11 @@ void amdgpu_amdkfd_fini(void)
+ 
+ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
+ {
+-	const struct kfd2kgd_calls *kfd2kgd;
+ 	bool vf = amdgpu_sriov_vf(adev);
+ 
+ 
+-	switch (adev->asic_type) {
+-#ifdef CONFIG_DRM_AMDGPU_CIK
+-	case CHIP_KAVERI:
+-	case CHIP_HAWAII:
+-		kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
+-		break;
+-#endif
+-	case CHIP_CARRIZO:
+-	case CHIP_TONGA:
+-	case CHIP_FIJI:
+-	case CHIP_POLARIS10:
+-	case CHIP_POLARIS11:
+-	case CHIP_POLARIS12:
+-	case CHIP_VEGAM:
+-		kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
+-		break;
+-	case CHIP_VEGA10:
+-	case CHIP_VEGA12:
+-	case CHIP_VEGA20:
+-	case CHIP_RAVEN:
+-	case CHIP_RENOIR:
+-		kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
+-		break;
+-	case CHIP_ARCTURUS:
+-		kfd2kgd = amdgpu_amdkfd_arcturus_get_functions();
+-		break;
+-	case CHIP_NAVI10:
+-	case CHIP_NAVI14:
+-	case CHIP_NAVI12:
+-		kfd2kgd = amdgpu_amdkfd_gfx_10_0_get_functions();
+-		break;
+-	default:
+-		dev_info(adev->dev, "kfd not supported on this ASIC\n");
+-		return;
+-	}
+-
+ 	adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
+-				      adev->pdev, kfd2kgd, adev->asic_type, vf);
++				      adev->pdev, adev->asic_type, vf);
+ 
+ 	if (adev->kfd.dev)
+ 		amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
+@@ -733,33 +696,7 @@ int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
+ 	return 0;
+ }
+ 
+-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
+-{
+-	return NULL;
+-}
+-
+-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
+-{
+-	return NULL;
+-}
+-
+-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
+-{
+-	return NULL;
+-}
+-
+-struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void)
+-{
+-	return NULL;
+-}
+-
+-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions(void)
+-{
+-	return NULL;
+-}
+-
+ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
+-			      const struct kfd2kgd_calls *f2g,
+ 			      unsigned int asic_type, bool vf)
+ {
+ 	return NULL;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+index a41fe657ba2a..65120f05fd58 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+@@ -138,11 +138,6 @@ int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
+ void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle);
+ bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd);
+ 
+-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void);
+-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void);
+-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void);
+-struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void);
+-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions(void);
+ int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem,
+ 		uint64_t src_offset, struct kgd_mem *dst_mem,
+ 		uint64_t dest_offset, uint64_t size, struct dma_fence **f,
+@@ -262,7 +257,6 @@ void amdgpu_amdkfd_debug_mem_fence(struct kgd_dev *kgd);
+ int kgd2kfd_init(void);
+ void kgd2kfd_exit(void);
+ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
+-			      const struct kfd2kgd_calls *f2g,
+ 			      unsigned int asic_type, bool vf);
+ bool kgd2kfd_device_init(struct kfd_dev *kfd,
+ 			 struct drm_device *ddev,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+index f0b19f20d1af..db39c6653cce 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+@@ -263,7 +263,7 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+ 	return 0;
+ }
+ 
+-static const struct kfd2kgd_calls kfd2kgd = {
++const struct kfd2kgd_calls arcturus_kfd2kgd = {
+ 	.program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,
+ 	.set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,
+ 	.init_interrupts = kgd_gfx_v9_init_interrupts,
+@@ -294,9 +294,3 @@ static const struct kfd2kgd_calls kfd2kgd = {
+ 	.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,
+ 	.build_grace_period_packet_info = kgd_gfx_v9_build_grace_period_packet_info,
+ };
+-
+-struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void)
+-{
+-	return (struct kfd2kgd_calls *)&kfd2kgd;
+-}
+-
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+index c1f194f9c515..b5091e31c83f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+@@ -816,7 +816,7 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
+ 	gfxhub_v2_0_setup_vm_pt_regs(adev, vmid, page_table_base);
+ }
+ 
+-static const struct kfd2kgd_calls kfd2kgd = {
++const struct kfd2kgd_calls gfx_v10_kfd2kgd = {
+ 	.program_sh_mem_settings = kgd_program_sh_mem_settings,
+ 	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
+ 	.init_interrupts = kgd_init_interrupts,
+@@ -840,8 +840,3 @@ static const struct kfd2kgd_calls kfd2kgd = {
+ 	.invalidate_tlbs_vmid = invalidate_tlbs_vmid,
+ 	.get_hive_id = amdgpu_amdkfd_get_hive_id,
+ };
+-
+-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions()
+-{
+-	return (struct kfd2kgd_calls *)&kfd2kgd;
+-}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+index f0ef2e64f592..495b15ed28cd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+@@ -754,7 +754,7 @@ static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd)
+ 	return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
+ }
+ 
+-static const struct kfd2kgd_calls kfd2kgd = {
++const struct kfd2kgd_calls gfx_v7_kfd2kgd = {
+ 	.program_sh_mem_settings = kgd_program_sh_mem_settings,
+ 	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
+ 	.init_interrupts = kgd_init_interrupts,
+@@ -778,8 +778,3 @@ static const struct kfd2kgd_calls kfd2kgd = {
+ 	.invalidate_tlbs_vmid = invalidate_tlbs_vmid,
+ 	.read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg,
+ };
+-
+-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
+-{
+-	return (struct kfd2kgd_calls *)&kfd2kgd;
+-}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+index 17a31c1b1272..0118e6f18355 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+@@ -787,7 +787,7 @@ static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
+ 	return 0;
+ }
+ 
+-static const struct kfd2kgd_calls kfd2kgd = {
++const struct kfd2kgd_calls gfx_v8_kfd2kgd = {
+ 	.program_sh_mem_settings = kgd_program_sh_mem_settings,
+ 	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
+ 	.init_interrupts = kgd_init_interrupts,
+@@ -811,8 +811,3 @@ static const struct kfd2kgd_calls kfd2kgd = {
+ 	.invalidate_tlbs = invalidate_tlbs,
+ 	.invalidate_tlbs_vmid = invalidate_tlbs_vmid,
+ };
+-
+-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
+-{
+-	return (struct kfd2kgd_calls *)&kfd2kgd;
+-}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+index 9c4992d8f4b7..530b8ada1f8f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+@@ -1012,7 +1012,7 @@ void kgd_gfx_v9_build_grace_period_packet_info(struct kgd_dev *kgd,
+ 	*reg_offset = mmCP_IQ_WAIT_TIME2;
+ }
+ 
+-static const struct kfd2kgd_calls kfd2kgd = {
++const struct kfd2kgd_calls gfx_v9_kfd2kgd = {
+ 	.program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,
+ 	.set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,
+ 	.init_interrupts = kgd_gfx_v9_init_interrupts,
+@@ -1043,8 +1043,3 @@ static const struct kfd2kgd_calls kfd2kgd = {
+ 	.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,
+ 	.build_grace_period_packet_info = kgd_gfx_v9_build_grace_period_packet_info,
+ };
+-
+-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
+-{
+-	return (struct kfd2kgd_calls *)&kfd2kgd;
+-}
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index d7e687062dd7..bdf890912ff8 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -39,6 +39,41 @@
+  */
+ static atomic_t kfd_locked = ATOMIC_INIT(0);
+ 
++#ifdef CONFIG_DRM_AMDGPU_CIK
++extern const struct kfd2kgd_calls gfx_v7_kfd2kgd;
++#endif
++extern const struct kfd2kgd_calls gfx_v8_kfd2kgd;
++extern const struct kfd2kgd_calls gfx_v9_kfd2kgd;
++extern const struct kfd2kgd_calls arcturus_kfd2kgd;
++extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
++
++static const struct kfd2kgd_calls *kfd2kgd_funcs[] = {
++#ifdef KFD_SUPPORT_IOMMU_V2
++#ifdef CONFIG_DRM_AMDGPU_CIK
++	[CHIP_KAVERI] = &gfx_v7_kfd2kgd,
++#endif
++	[CHIP_CARRIZO] = &gfx_v8_kfd2kgd,
++	[CHIP_RAVEN] = &gfx_v9_kfd2kgd,
++#endif
++#ifdef CONFIG_DRM_AMDGPU_CIK
++	[CHIP_HAWAII] = &gfx_v7_kfd2kgd,
++#endif
++	[CHIP_TONGA] = &gfx_v8_kfd2kgd,
++	[CHIP_FIJI] = &gfx_v8_kfd2kgd,
++	[CHIP_POLARIS10] = &gfx_v8_kfd2kgd,
++	[CHIP_POLARIS11] = &gfx_v8_kfd2kgd,
++	[CHIP_POLARIS12] = &gfx_v8_kfd2kgd,
++	[CHIP_VEGAM] = &gfx_v8_kfd2kgd,
++	[CHIP_VEGA10] = &gfx_v9_kfd2kgd,
++	[CHIP_VEGA12] = &gfx_v9_kfd2kgd,
++	[CHIP_VEGA20] = &gfx_v9_kfd2kgd,
++	[CHIP_RENOIR] = &gfx_v9_kfd2kgd,
++	[CHIP_ARCTURUS] = &arcturus_kfd2kgd,
++	[CHIP_NAVI10] = &gfx_v10_kfd2kgd,
++	[CHIP_NAVI12] = &gfx_v10_kfd2kgd,
++	[CHIP_NAVI14] = &gfx_v10_kfd2kgd,
++};
++
+ #ifdef KFD_SUPPORT_IOMMU_V2
+ static const struct kfd_device_info kaveri_device_info = {
+ 	.asic_family = CHIP_KAVERI,
+@@ -454,20 +489,22 @@ static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
+ static int kfd_resume(struct kfd_dev *kfd);
+ 
+ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
+-	struct pci_dev *pdev, const struct kfd2kgd_calls *f2g,
+-	unsigned int asic_type, bool vf)
++	struct pci_dev *pdev, unsigned int asic_type, bool vf)
+ {
+ 	struct kfd_dev *kfd;
+ 	const struct kfd_device_info *device_info;
++	const struct kfd2kgd_calls *f2g;
+ 
+-	if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2)) {
++	if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2)
++		|| asic_type >= sizeof(kfd2kgd_funcs) / sizeof(void *)) {
+ 		dev_err(kfd_device, "asic_type %d out of range\n", asic_type);
+ 		return NULL; /* asic_type out of range */
+ 	}
+ 
+ 	device_info = kfd_supported_devices[asic_type][vf];
++	f2g = kfd2kgd_funcs[asic_type];
+ 
+-	if (!device_info) {
++	if (!device_info && !f2g) {
+ 		dev_err(kfd_device, "%s %s not supported in kfd\n",
+ 			amdgpu_asic_name[asic_type], vf ? "VF" : "");
+ 		return NULL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4019-drm-amdgpu-Add-the-HDP-flush-support-for-Navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4019-drm-amdgpu-Add-the-HDP-flush-support-for-Navi.patch
new file mode 100644
index 00000000..1a090d73
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4019-drm-amdgpu-Add-the-HDP-flush-support-for-Navi.patch
@@ -0,0 +1,92 @@
+From e3d39c2c179e85298a7f9d75e047b45fceacca77 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 27 Sep 2019 23:30:05 -0400
+Subject: [PATCH 4019/4256] drm/amdgpu: Add the HDP flush support for Navi
+
+The HDP flush support code was missing in the nbio and nv files.
+
+Change-Id: I046ff52567676b56bf16dc1728b02481233acb61
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 16 +++++++++++++---
+ drivers/gpu/drm/amd/amdgpu/nv.c        |  9 +++++++++
+ 2 files changed, 22 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+index a5fa741e4aff..f3a5276ce803 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+@@ -27,11 +27,21 @@
+ #include "nbio/nbio_2_3_default.h"
+ #include "nbio/nbio_2_3_offset.h"
+ #include "nbio/nbio_2_3_sh_mask.h"
++#include <uapi/linux/kfd_ioctl.h>
+ 
+ #define smnPCIE_CONFIG_CNTL	0x11180044
+ #define smnCPM_CONTROL		0x11180460
+ #define smnPCIE_CNTL2		0x11180070
+ 
++
++static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev)
++{
++	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
++		adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
++	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
++		adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
++}
++
+ static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)
+ {
+ 	u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+@@ -56,10 +66,9 @@ static void nbio_v2_3_hdp_flush(struct amdgpu_device *adev,
+ 				struct amdgpu_ring *ring)
+ {
+ 	if (!ring || !ring->funcs->emit_wreg)
+-		WREG32_SOC15_NO_KIQ(NBIO, 0, mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
++		WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+ 	else
+-		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
+-			NBIO, 0, mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL), 0);
++		amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+ }
+ 
+ static u32 nbio_v2_3_get_memsize(struct amdgpu_device *adev)
+@@ -330,4 +339,5 @@ const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
+ 	.ih_control = nbio_v2_3_ih_control,
+ 	.init_registers = nbio_v2_3_init_registers,
+ 	.detect_hw_virt = nbio_v2_3_detect_hw_virt,
++	.remap_hdp_registers = nbio_v2_3_remap_hdp_registers,
+ };
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index fb097aa089da..994198ef853a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -586,8 +586,11 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
+ 
+ static int nv_common_early_init(void *handle)
+ {
++#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
++	adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
++	adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+ 	adev->smc_rreg = NULL;
+ 	adev->smc_wreg = NULL;
+ 	adev->pcie_rreg = &nv_pcie_rreg;
+@@ -713,6 +716,12 @@ static int nv_common_hw_init(void *handle)
+ 	nv_program_aspm(adev);
+ 	/* setup nbio registers */
+ 	adev->nbio.funcs->init_registers(adev);
++	/* remap HDP registers to a hole in mmio space,
++	 * for the purpose of expose those registers
++	 * to process space
++	 */
++	if (adev->nbio.funcs->remap_hdp_registers)
++		adev->nbio.funcs->remap_hdp_registers(adev);
+ 	/* enable the doorbell aperture */
+ 	nv_enable_doorbell_aperture(adev, true);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4020-drm-amdgpu-Export-setup_vm_pt_regs-logic-for-mmhub-2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4020-drm-amdgpu-Export-setup_vm_pt_regs-logic-for-mmhub-2.patch
new file mode 100644
index 00000000..f27231d0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4020-drm-amdgpu-Export-setup_vm_pt_regs-logic-for-mmhub-2.patch
@@ -0,0 +1,68 @@
+From 74875a8bb5b92463c8d15e51e90cfe67d847d8a5 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Tue, 24 Sep 2019 17:23:12 -0400
+Subject: [PATCH 4020/4256] drm/amdgpu: Export setup_vm_pt_regs() logic for
+ mmhub 2.0
+
+The KFD code will call this function later.
+
+Change-Id: I5993323603799963e9eb473852b6c72de2172ed6
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 19 ++++++++++++-------
+ drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h |  2 ++
+ 2 files changed, 14 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+index 86ed8cb915a8..2eea702de8ee 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+@@ -31,20 +31,25 @@
+ 
+ #include "soc15_common.h"
+ 
+-static void mmhub_v2_0_init_gart_pt_regs(struct amdgpu_device *adev)
++void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
++				uint64_t page_table_base)
+ {
+-	uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
++	/* two registers distance between mmMMVM_CONTEXT0_* to mmMMVM_CONTEXT1_* */
++	int offset = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
++			- mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
+ 
+-	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+-		     lower_32_bits(value));
++	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
++			offset * vmid, lower_32_bits(page_table_base));
+ 
+-	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+-		     upper_32_bits(value));
++	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
++			offset * vmid, upper_32_bits(page_table_base));
+ }
+ 
+ static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
+ {
+-	mmhub_v2_0_init_gart_pt_regs(adev);
++	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
++
++	mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
+ 
+ 	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+ 		     (u32)(adev->gmc.gart_start >> 12));
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h
+index db16f3ece218..3ea4344f0315 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.h
+@@ -31,5 +31,7 @@ void mmhub_v2_0_init(struct amdgpu_device *adev);
+ int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
+ 			       enum amd_clockgating_state state);
+ void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags);
++void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
++				uint64_t page_table_base);
+ 
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4021-drm-amdkfd-Improve-KFD-IOCTL-printing.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4021-drm-amdkfd-Improve-KFD-IOCTL-printing.patch
new file mode 100644
index 00000000..695479e3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4021-drm-amdkfd-Improve-KFD-IOCTL-printing.patch
@@ -0,0 +1,40 @@
+From 998584da07efe61d6d5dc21bc6809b122252a8d3 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 20 Sep 2019 22:06:57 -0400
+Subject: [PATCH 4021/4256] drm/amdkfd: Improve KFD IOCTL printing
+
+The code use hex define, so should the printing.
+
+Change-Id: Ia7cc7690553bb043915b3d8c0157216c64421a60
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index 9b934f68d726..c60c4480d124 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -2991,7 +2991,7 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
+ 	} else
+ 		goto err_i1;
+ 
+-	dev_dbg(kfd_device, "ioctl cmd 0x%x (#%d), arg 0x%lx\n", cmd, nr, arg);
++	dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg);
+ 
+ 	process = kfd_get_process(current);
+ 	if (IS_ERR(process)) {
+@@ -3046,7 +3046,8 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
+ 		kfree(kdata);
+ 
+ 	if (retcode)
+-		dev_dbg(kfd_device, "ret = %d\n", retcode);
++		dev_dbg(kfd_device, "ioctl cmd (#0x%x), arg 0x%lx, ret = %d\n",
++				nr, arg, retcode);
+ 
+ 	return retcode;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4022-drm-amdgpu-enable-msix-for-amdgpu-driver.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4022-drm-amdgpu-enable-msix-for-amdgpu-driver.patch
new file mode 100644
index 00000000..309b3e7f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4022-drm-amdgpu-enable-msix-for-amdgpu-driver.patch
@@ -0,0 +1,35 @@
+From 3004045dada429a115f347dd8a5660de6977b293 Mon Sep 17 00:00:00 2001
+From: shaoyunl <shaoyun.liu@amd.com>
+Date: Tue, 1 Oct 2019 15:52:31 -0400
+Subject: [PATCH 4022/4256] drm/amdgpu : enable msix for amdgpu driver
+
+We might used out of the msi resources in some cloud project
+which have a lot gpu devices(including PF and VF), msix can
+provide enough resources from system level view
+
+Change-Id: I9f03762074ac416c07f27b8f00c052ca93c7d6cb
+Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+index 708fee1f2466..6feaf3db649a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+@@ -242,8 +242,9 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
+ 	adev->irq.msi_enabled = false;
+ 
+ 	if (amdgpu_msi_ok(adev)) {
+-		int ret = pci_enable_msi(adev->pdev);
+-		if (!ret) {
++		int nvec = pci_alloc_irq_vectors(adev->pdev, 1, pci_msix_vec_count(adev->pdev),
++					PCI_IRQ_MSI | PCI_IRQ_MSIX);
++		if (nvec > 0) {
+ 			adev->irq.msi_enabled = true;
+ 			dev_dbg(adev->dev, "amdgpu: using MSI.\n");
+ 		}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4023-drm-amdgpu-don-t-increment-vram-lost-if-we-are-in-hi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4023-drm-amdgpu-don-t-increment-vram-lost-if-we-are-in-hi.patch
new file mode 100644
index 00000000..da2f6d7e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4023-drm-amdgpu-don-t-increment-vram-lost-if-we-are-in-hi.patch
@@ -0,0 +1,63 @@
+From 717d6e84270cf1c0e98901b4be5962339ca911c7 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 1 Oct 2019 16:45:27 -0500
+Subject: [PATCH 4023/4256] drm/amdgpu: don't increment vram lost if we are in
+ hibernation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We reset the GPU as part of our hibernation sequence so we need
+to make sure we don't mark vram as lost in that case.
+
+Bug: https://bugs.freedesktop.org/show_bug.cgi?id=111879
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c    | 6 ++++--
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 6 ++++--
+ 2 files changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 994198ef853a..55a6ed09a953 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -318,10 +318,12 @@ static int nv_asic_reset(struct amdgpu_device *adev)
+ 	struct smu_context *smu = &adev->smu;
+ 
+ 	if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
+-		amdgpu_inc_vram_lost(adev);
++		if (!adev->in_suspend)
++			amdgpu_inc_vram_lost(adev);
+ 		ret = smu_baco_reset(smu);
+ 	} else {
+-		amdgpu_inc_vram_lost(adev);
++		if (!adev->in_suspend)
++			amdgpu_inc_vram_lost(adev);
+ 		ret = nv_asic_mode1_reset(adev);
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index eb87d04cb425..3f89a57e823e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -563,12 +563,14 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
+ {
+ 	switch (soc15_asic_reset_method(adev)) {
+ 		case AMD_RESET_METHOD_BACO:
+-			amdgpu_inc_vram_lost(adev);
++			if (!adev->in_suspend)
++				amdgpu_inc_vram_lost(adev);
+ 			return soc15_asic_baco_reset(adev);
+ 		case AMD_RESET_METHOD_MODE2:
+ 			return soc15_mode2_reset(adev);
+ 		default:
+-			amdgpu_inc_vram_lost(adev);
++			if (!adev->in_suspend)
++				amdgpu_inc_vram_lost(adev);
+ 			return soc15_asic_mode1_reset(adev);
+ 	}
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4024-drm-amdgpu-fix-multiple-memory-leaks-in-acp_hw_init.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4024-drm-amdgpu-fix-multiple-memory-leaks-in-acp_hw_init.patch
new file mode 100644
index 00000000..f157c8c9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4024-drm-amdgpu-fix-multiple-memory-leaks-in-acp_hw_init.patch
@@ -0,0 +1,121 @@
+From deee3b06cc1912e53df6410594d1d17688c03278 Mon Sep 17 00:00:00 2001
+From: Navid Emamdoost <navid.emamdoost@gmail.com>
+Date: Tue, 1 Oct 2019 22:46:07 -0500
+Subject: [PATCH 4024/4256] drm/amdgpu: fix multiple memory leaks in
+ acp_hw_init
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+In acp_hw_init there are some allocations that needs to be released in
+case of failure:
+
+1- adev->acp.acp_genpd should be released if any allocation attemp for
+adev->acp.acp_cell, adev->acp.acp_res or i2s_pdata fails.
+2- all of those allocations should be released if
+mfd_add_hotplug_devices or pm_genpd_add_device fail.
+3- Release is needed in case of time out values expire.
+
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Navid Emamdoost <navid.emamdoost@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 34 ++++++++++++++++---------
+ 1 file changed, 22 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+index 0a4fba196b84..7f3538710d1f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+@@ -188,7 +188,7 @@ static int acp_hw_init(void *handle)
+ 	u32 val = 0;
+ 	u32 count = 0;
+ 	struct device *dev;
+-	struct i2s_platform_data *i2s_pdata;
++	struct i2s_platform_data *i2s_pdata = NULL;
+ 
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
+@@ -230,20 +230,21 @@ static int acp_hw_init(void *handle)
+ 	adev->acp.acp_cell = kcalloc(ACP_DEVS, sizeof(struct mfd_cell),
+ 							GFP_KERNEL);
+ 
+-	if (adev->acp.acp_cell == NULL)
+-		return -ENOMEM;
++	if (adev->acp.acp_cell == NULL) {
++		r = -ENOMEM;
++		goto failure;
++	}
+ 
+ 	adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL);
+ 	if (adev->acp.acp_res == NULL) {
+-		kfree(adev->acp.acp_cell);
+-		return -ENOMEM;
++		r = -ENOMEM;
++		goto failure;
+ 	}
+ 
+ 	i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL);
+ 	if (i2s_pdata == NULL) {
+-		kfree(adev->acp.acp_res);
+-		kfree(adev->acp.acp_cell);
+-		return -ENOMEM;
++		r = -ENOMEM;
++		goto failure;
+ 	}
+ 
+ 	switch (adev->asic_type) {
+@@ -340,14 +341,14 @@ static int acp_hw_init(void *handle)
+ 	r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell,
+ 								ACP_DEVS);
+ 	if (r)
+-		return r;
++		goto failure;
+ 
+ 	for (i = 0; i < ACP_DEVS ; i++) {
+ 		dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
+ 		r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev);
+ 		if (r) {
+ 			dev_err(dev, "Failed to add dev to genpd\n");
+-			return r;
++			goto failure;
+ 		}
+ 	}
+ 
+@@ -366,7 +367,8 @@ static int acp_hw_init(void *handle)
+ 			break;
+ 		if (--count == 0) {
+ 			dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
+-			return -ETIMEDOUT;
++			r = -ETIMEDOUT;
++			goto failure;
+ 		}
+ 		udelay(100);
+ 	}
+@@ -383,7 +385,8 @@ static int acp_hw_init(void *handle)
+ 			break;
+ 		if (--count == 0) {
+ 			dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
+-			return -ETIMEDOUT;
++			r = -ETIMEDOUT;
++			goto failure;
+ 		}
+ 		udelay(100);
+ 	}
+@@ -392,6 +395,13 @@ static int acp_hw_init(void *handle)
+ 	val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
+ 	cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
+ 	return 0;
++
++failure:
++	kfree(i2s_pdata);
++	kfree(adev->acp.acp_res);
++	kfree(adev->acp.acp_cell);
++	kfree(adev->acp.acp_genpd);
++	return r;
+ }
+ 
+ /**
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4025-drm-amdgpu-Drop-unused-variable-and-statement.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4025-drm-amdgpu-Drop-unused-variable-and-statement.patch
new file mode 100644
index 00000000..1e6d02a4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4025-drm-amdgpu-Drop-unused-variable-and-statement.patch
@@ -0,0 +1,47 @@
+From b0b1c1ca29b188e2c970aea77e7afb0a237c4b32 Mon Sep 17 00:00:00 2001
+From: Austin Kim <austindh.kim@gmail.com>
+Date: Wed, 2 Oct 2019 14:17:59 +0900
+Subject: [PATCH 4025/4256] drm/amdgpu: Drop unused variable and statement
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Even though 'smu8_smu' is declared, it is not used after below statement.
+
+   smu8_smu = hwmgr->smu_backend;
+
+So 'unused variable' could be safely removed
+to stop warning message as below:
+
+   drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/smu8_smumgr.c:180:22:
+   warning: variable ‘smu8_smu’ set but not used
+   [-Wunused-but-set-variable]
+
+   struct smu8_smumgr *smu8_smu;
+             ^
+Signed-off-by: Austin Kim <austindh.kim@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
+index 4728aa23a818..7dca04a89217 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
+@@ -177,12 +177,10 @@ static int smu8_load_mec_firmware(struct pp_hwmgr *hwmgr)
+ 	uint32_t tmp;
+ 	int ret = 0;
+ 	struct cgs_firmware_info info = {0};
+-	struct smu8_smumgr *smu8_smu;
+ 
+ 	if (hwmgr == NULL || hwmgr->device == NULL)
+ 		return -EINVAL;
+ 
+-	smu8_smu = hwmgr->smu_backend;
+ 	ret = cgs_get_firmware_info(hwmgr->device,
+ 						CGS_UCODE_ID_CP_MEC, &info);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4026-drm-amdgpu-remove-set-but-not-used-variable-pipe.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4026-drm-amdgpu-remove-set-but-not-used-variable-pipe.patch
new file mode 100644
index 00000000..5ee385e2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4026-drm-amdgpu-remove-set-but-not-used-variable-pipe.patch
@@ -0,0 +1,45 @@
+From 70530be7e885e03778131e73e152127728804b32 Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Sun, 29 Sep 2019 20:38:43 +0800
+Subject: [PATCH 4026/4256] drm/amdgpu: remove set but not used variable 'pipe'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+rivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function
+‘amdgpu_gfx_graphics_queue_acquire’:
+drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:234:16: warning:
+variable ‘pipe’ set but not used [-Wunused-but-set-variable]
+
+It is never used, so can be removed.
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+index fdcb7057093f..56b31668d551 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+@@ -232,12 +232,10 @@ void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
+ 
+ void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
+ {
+-	int i, queue, pipe, me;
++	int i, queue, me;
+ 
+ 	for (i = 0; i < AMDGPU_MAX_GFX_QUEUES; ++i) {
+ 		queue = i % adev->gfx.me.num_queue_per_pipe;
+-		pipe = (i / adev->gfx.me.num_queue_per_pipe)
+-			% adev->gfx.me.num_pipe_per_me;
+ 		me = (i / adev->gfx.me.num_queue_per_pipe)
+ 		      / adev->gfx.me.num_pipe_per_me;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4027-drm-amdgpu-make-pmu-support-optional-again.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4027-drm-amdgpu-make-pmu-support-optional-again.patch
new file mode 100644
index 00000000..c2260940
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4027-drm-amdgpu-make-pmu-support-optional-again.patch
@@ -0,0 +1,43 @@
+From d6b2843bd2523abf10cdb00df252d28044c89b3e Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Wed, 2 Oct 2019 14:01:22 +0200
+Subject: [PATCH 4027/4256] drm/amdgpu: make pmu support optional, again
+
+When CONFIG_PERF_EVENTS is disabled, we cannot compile the pmu
+portion of the amdgpu driver:
+
+drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:48:38: error: no member named 'hw' in 'struct perf_event'
+        struct hw_perf_event *hwc = &event->hw;
+                                     ~~~~~  ^
+drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:51:13: error: no member named 'attr' in 'struct perf_event'
+        if (event->attr.type != event->pmu->type)
+            ~~~~~  ^
+...
+
+The same bug was already fixed by commit d155bef0636e ("amdgpu: make pmu
+support optional") but broken again by what looks like an incorrectly
+rebased patch.
+
+Fixes: 64f55e629237 ("drm/amdgpu: Add RAS EEPROM table.")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index 22c4bcbe7001..fa5703505748 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -54,7 +54,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
+ 	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
+ 	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
+ 	amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_sem.o \
+-	amdgpu_ras.o amdgpu_vm_cpu.o amdgpu_vm_sdma.o amdgpu_pmu.o \
++	amdgpu_ras.o amdgpu_vm_cpu.o amdgpu_vm_sdma.o \
+ 	amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o amdgpu_umc.o \
+ 	smu_v11_0_i2c.o
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4028-drm-amdgpu-hide-another-warning.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4028-drm-amdgpu-hide-another-warning.patch
new file mode 100644
index 00000000..133493fa
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4028-drm-amdgpu-hide-another-warning.patch
@@ -0,0 +1,35 @@
+From 3532d7ac060ae4a5bc848cdf83e8ebcf46d3dadf Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Wed, 2 Oct 2019 14:01:23 +0200
+Subject: [PATCH 4028/4256] drm/amdgpu: hide another #warning
+
+An earlier patch of mine disabled some #warning statements
+that get in the way of build testing, but then another
+instance was added around the same time.
+
+Remove that as well.
+
+Fixes: b5203d16aef4 ("drm/amd/amdgpu: hide #warning for missing DC config")
+Fixes: e1c14c43395c ("drm/amdgpu: Enable DC on Renoir")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 3f89a57e823e..a77f9b708f7f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -795,8 +795,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ #if defined(CONFIG_DRM_AMD_DC)
+                 else if (amdgpu_device_has_dc_support(adev))
+                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
+-#else
+-#       warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
+ #endif
+ 		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4029-drm-amdgpu-work-around-llvm-bug-42576.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4029-drm-amdgpu-work-around-llvm-bug-42576.patch
new file mode 100644
index 00000000..f4772ba3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4029-drm-amdgpu-work-around-llvm-bug-42576.patch
@@ -0,0 +1,36 @@
+From 44d1b0c79da2839e225acd43f07e57a07e73f224 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Wed, 2 Oct 2019 14:01:27 +0200
+Subject: [PATCH 4029/4256] drm/amdgpu: work around llvm bug #42576
+
+Code in the amdgpu driver triggers a bug when using clang to build
+an arm64 kernel:
+
+/tmp/sdma_v4_0-f95fd3.s: Assembler messages:
+/tmp/sdma_v4_0-f95fd3.s:44: Error: selected processor does not support `bfc w0,#1,#5'
+
+I expect this to be fixed in llvm soon, but we can also work around
+it by inserting a barrier() that prevents the optimization.
+
+Link: https://bugs.llvm.org/show_bug.cgi?id=42576
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index cf784a4caa24..26f13de35b2c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -958,6 +958,7 @@ static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
+ 	/* Set ring buffer size in dwords */
+ 	uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
+ 
++	barrier(); /* work around https://bugs.llvm.org/show_bug.cgi?id=42576 */
+ 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
+ #ifdef __BIG_ENDIAN
+ 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4030-drm-amdgpu-improve-MSI-X-handling-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4030-drm-amdgpu-improve-MSI-X-handling-v3.patch
new file mode 100644
index 00000000..b3c26754
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4030-drm-amdgpu-improve-MSI-X-handling-v3.patch
@@ -0,0 +1,60 @@
+From d5394a0c34d2b341f66d0249344c77eb2ff0bb7b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 3 Oct 2019 10:34:30 -0500
+Subject: [PATCH 4030/4256] drm/amdgpu: improve MSI-X handling (v3)
+
+Check the number of supported vectors and fall back to MSI if
+we return or error or 0 MSI-X vectors.
+
+v2: only allocate one vector.  We can't currently use more than
+one anyway.
+
+v3: install the irq on vector 0.
+
+Tested-by: Tom St Denis <tom.stdenis@amd.com>
+Reviewed-by: Shaoyun liu  <shaoyun.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 17 +++++++++++++----
+ 1 file changed, 13 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+index 6feaf3db649a..22edda8ad261 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+@@ -242,11 +242,19 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
+ 	adev->irq.msi_enabled = false;
+ 
+ 	if (amdgpu_msi_ok(adev)) {
+-		int nvec = pci_alloc_irq_vectors(adev->pdev, 1, pci_msix_vec_count(adev->pdev),
+-					PCI_IRQ_MSI | PCI_IRQ_MSIX);
++		int nvec = pci_msix_vec_count(adev->pdev);
++		unsigned int flags;
++
++		if (nvec <= 0) {
++			flags = PCI_IRQ_MSI;
++		} else {
++			flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
++		}
++		/* we only need one vector */
++		nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
+ 		if (nvec > 0) {
+ 			adev->irq.msi_enabled = true;
+-			dev_dbg(adev->dev, "amdgpu: using MSI.\n");
++			dev_dbg(adev->dev, "amdgpu: using MSI/MSI-X.\n");
+ 		}
+ 	}
+ 
+@@ -269,7 +277,8 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
+ 	INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
+ 
+ 	adev->irq.installed = true;
+-	r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
++	/* Use vector 0 for MSI-X */
++	r = drm_irq_install(adev->ddev, pci_irq_vector(adev->pdev, 0));
+ 	if (r) {
+ 		adev->irq.installed = false;
+ 		if (!amdgpu_device_has_dc_support(adev))
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4031-drm-amdgpu-vcn-use-amdgpu_ring_test_helper.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4031-drm-amdgpu-vcn-use-amdgpu_ring_test_helper.patch
new file mode 100644
index 00000000..00e71c2f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4031-drm-amdgpu-vcn-use-amdgpu_ring_test_helper.patch
@@ -0,0 +1,118 @@
+From 68d106a155cabeec5acc1ea112e172fb5868a4ee Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Tue, 1 Oct 2019 18:08:46 -0400
+Subject: [PATCH 4031/4256] drm/amdgpu/vcn: use amdgpu_ring_test_helper
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Instead of amdgpu_ring_test_ring, so the helper function determines
+whether the ring is ready
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: James Zhu <James.Zhu@amd.com>
+Acked-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
+Cc: Gustavo A. R. Silva <gustavo@embeddedor.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c |  1 -
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 21 ++++++---------------
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 18 ++++++------------
+ 3 files changed, 12 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+index 07a2f36ea7ce..b23362102e51 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+@@ -202,7 +202,6 @@ static int vcn_v1_0_hw_init(void *handle)
+ 
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ 		ring = &adev->vcn.inst->ring_enc[i];
+-		ring->sched.ready = true;
+ 		r = amdgpu_ring_test_helper(ring);
+ 		if (r)
+ 			goto done;
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+index 5a590064bfff..16f192f6c967 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+@@ -247,30 +247,21 @@ static int vcn_v2_0_hw_init(void *handle)
+ 	adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+ 					     ring->doorbell_index, 0);
+ 
+-	ring->sched.ready = true;
+-	r = amdgpu_ring_test_ring(ring);
+-	if (r) {
+-		ring->sched.ready = false;
++	r = amdgpu_ring_test_helper(ring);
++	if (r)
+ 		goto done;
+-	}
+ 
+ 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ 		ring = &adev->vcn.inst->ring_enc[i];
+-		ring->sched.ready = true;
+-		r = amdgpu_ring_test_ring(ring);
+-		if (r) {
+-			ring->sched.ready = false;
++		r = amdgpu_ring_test_helper(ring);
++		if (r)
+ 			goto done;
+-		}
+ 	}
+ 
+ 	ring = &adev->vcn.inst->ring_jpeg;
+-	ring->sched.ready = true;
+-	r = amdgpu_ring_test_ring(ring);
+-	if (r) {
+-		ring->sched.ready = false;
++	r = amdgpu_ring_test_helper(ring);
++	if (r)
+ 		goto done;
+-	}
+ 
+ done:
+ 	if (!r)
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index 22e4644521dc..4840f110bbed 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -258,29 +258,23 @@ static int vcn_v2_5_hw_init(void *handle)
+ 		adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+ 						     ring->doorbell_index, j);
+ 
+-		r = amdgpu_ring_test_ring(ring);
+-		if (r) {
+-			ring->sched.ready = false;
++		r = amdgpu_ring_test_helper(ring);
++		if (r)
+ 			goto done;
+-		}
+ 
+ 		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ 			ring = &adev->vcn.inst[j].ring_enc[i];
+ 			ring->sched.ready = false;
+ 			continue;
+-			r = amdgpu_ring_test_ring(ring);
+-			if (r) {
+-				ring->sched.ready = false;
++			r = amdgpu_ring_test_helper(ring);
++			if (r)
+ 				goto done;
+-			}
+ 		}
+ 
+ 		ring = &adev->vcn.inst[j].ring_jpeg;
+-		r = amdgpu_ring_test_ring(ring);
+-		if (r) {
+-			ring->sched.ready = false;
++		r = amdgpu_ring_test_helper(ring);
++		if (r)
+ 			goto done;
+-		}
+ 	}
+ done:
+ 	if (!r)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4032-drm-amdgpu-add-code-comment-in-vcn_v2_5_hw_init.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4032-drm-amdgpu-add-code-comment-in-vcn_v2_5_hw_init.patch
new file mode 100644
index 00000000..a63e28b3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4032-drm-amdgpu-add-code-comment-in-vcn_v2_5_hw_init.patch
@@ -0,0 +1,41 @@
+From 44a2bc94799113df09b6654f8993700c6ebdd5ec Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Tue, 1 Oct 2019 18:12:45 -0400
+Subject: [PATCH 4032/4256] drm/amdgpu: add code comment in vcn_v2_5_hw_init
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add a comment to VCN 2.5 encode ring
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: James Zhu <James.Zhu@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: Christian König <christian.koenig@amd.com>
+Cc: David (ChunMing) Zhou <David1.Zhou@amd.com>
+Cc: David Airlie <airlied@linux.ie>
+Cc: Daniel Vetter <daniel@ffwll.ch>
+Cc: amd-gfx@lists.freedesktop.org
+Cc: dri-devel@lists.freedesktop.org
+Cc: linux-kernel@vger.kernel.org
+Cc: Gustavo A. R. Silva <gustavo@embeddedor.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index 4840f110bbed..2608c932a775 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -264,6 +264,7 @@ static int vcn_v2_5_hw_init(void *handle)
+ 
+ 		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ 			ring = &adev->vcn.inst[j].ring_enc[i];
++			/* disable encode rings till the robustness of the FW */
+ 			ring->sched.ready = false;
+ 			continue;
+ 			r = amdgpu_ring_test_helper(ring);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4033-drm-amdgpu-fix-uninitialized-variable-pasid_mapping_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4033-drm-amdgpu-fix-uninitialized-variable-pasid_mapping_.patch
new file mode 100644
index 00000000..85dd7470
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4033-drm-amdgpu-fix-uninitialized-variable-pasid_mapping_.patch
@@ -0,0 +1,39 @@
+From 5a11480c4166d4c53ad10021c1c23c901ded7805 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Thu, 3 Oct 2019 22:52:27 +0100
+Subject: [PATCH 4033/4256] drm/amdgpu: fix uninitialized variable
+ pasid_mapping_needed
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The boolean variable pasid_mapping_needed is not initialized and
+there are code paths that do not assign it any value before it is
+is read later.  Fix this by initializing pasid_mapping_needed to
+false.
+
+Addresses-Coverity: ("Uninitialized scalar variable")
+Fixes: 6817bf283b2b ("drm/amdgpu: grab the id mgr lock while accessing passid_mapping")
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 8566f6b0729a..af4fda196c7d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -1052,7 +1052,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
+ 		id->oa_size != job->oa_size);
+ 	bool vm_flush_needed = job->vm_needs_flush;
+ 	struct dma_fence *fence = NULL;
+-	bool pasid_mapping_needed;
++	bool pasid_mapping_needed = false;
+ 	unsigned patch_offset = 0;
+ 	int r;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4034-drm-amdgpu-remove-redundant-variable-r-and-redundant.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4034-drm-amdgpu-remove-redundant-variable-r-and-redundant.patch
new file mode 100644
index 00000000..b14ee1ea
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4034-drm-amdgpu-remove-redundant-variable-r-and-redundant.patch
@@ -0,0 +1,44 @@
+From 4fe886989f7416fdbce7c6a50cacaee0aaf85562 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Thu, 3 Oct 2019 22:40:49 +0100
+Subject: [PATCH 4034/4256] drm/amdgpu: remove redundant variable r and
+ redundant return statement
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There is a return statement that is not reachable and a variable that
+is not used.  Remove them.
+
+Addresses-Coverity: ("Structurally dead code")
+Fixes: de7b45babd9b ("drm/amdgpu: cleanup creating BOs at fixed location (v2)")
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 677275c1b2c3..2e0e7fe98b3c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -1793,7 +1793,6 @@ static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
+ static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
+ {
+ 	uint64_t vram_size = adev->gmc.visible_vram_size;
+-	int r;
+ 
+ 	adev->fw_vram_usage.va = NULL;
+ 	adev->fw_vram_usage.reserved_bo = NULL;
+@@ -1808,7 +1807,6 @@ static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
+ 					  AMDGPU_GEM_DOMAIN_VRAM,
+ 					  &adev->fw_vram_usage.reserved_bo,
+ 					  &adev->fw_vram_usage.va);
+-	return r;
+ }
+ 
+ static int amdgpu_direct_gma_init(struct amdgpu_device *adev)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4035-drm-amdgpu-move-amdgpu_device_get_job_timeout_settin.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4035-drm-amdgpu-move-amdgpu_device_get_job_timeout_settin.patch
new file mode 100644
index 00000000..1b2bcf09
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4035-drm-amdgpu-move-amdgpu_device_get_job_timeout_settin.patch
@@ -0,0 +1,209 @@
+From 9f9380552adfd2adcd566447f2ee6a9c2febe760 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 13:36:09 -0500
+Subject: [PATCH 4035/4256] drm/amdgpu: move
+ amdgpu_device_get_job_timeout_settings
+
+It's only used in amdgpu_device.c and the naming also
+reflects that.  Move it there.
+
+Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  4 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 64 +++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c    | 67 ----------------------
+ 3 files changed, 67 insertions(+), 68 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 59e465ad4abf..0f36549b5580 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -108,6 +108,8 @@ struct amdgpu_mgpu_info
+ 	uint32_t			num_apu;
+ };
+ 
++#define AMDGPU_MAX_TIMEOUT_PARAM_LENTH	256
++
+ /*
+  * Modules parameters.
+  */
+@@ -124,6 +126,7 @@ extern int amdgpu_disp_priority;
+ extern int amdgpu_hw_i2c;
+ extern int amdgpu_pcie_gen2;
+ extern int amdgpu_msi;
++extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH];
+ extern int amdgpu_dpm;
+ extern int amdgpu_fw_load_type;
+ extern int amdgpu_aspm;
+@@ -432,7 +435,6 @@ struct amdgpu_fpriv {
+ };
+ 
+ int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
+-int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev);
+ 
+ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ 		  unsigned size, struct amdgpu_ib *ib);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 9e9617ce9381..4f7b0f0447bf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2557,6 +2557,70 @@ static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
+ 			 adev->asic_reset_res, adev->ddev->unique);
+ }
+ 
++static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
++{
++	char *input = amdgpu_lockup_timeout;
++	char *timeout_setting = NULL;
++	int index = 0;
++	long timeout;
++	int ret = 0;
++
++	/*
++	 * By default timeout for non compute jobs is 10000.
++	 * And there is no timeout enforced on compute jobs.
++	 * In SR-IOV or passthrough mode, timeout for compute
++	 * jobs are 10000 by default.
++	 */
++	adev->gfx_timeout = msecs_to_jiffies(10000);
++	adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
++	if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
++		adev->compute_timeout = adev->gfx_timeout;
++	else
++		adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
++
++	if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
++		while ((timeout_setting = strsep(&input, ",")) &&
++				strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
++			ret = kstrtol(timeout_setting, 0, &timeout);
++			if (ret)
++				return ret;
++
++			if (timeout == 0) {
++				index++;
++				continue;
++			} else if (timeout < 0) {
++				timeout = MAX_SCHEDULE_TIMEOUT;
++			} else {
++				timeout = msecs_to_jiffies(timeout);
++			}
++
++			switch (index++) {
++			case 0:
++				adev->gfx_timeout = timeout;
++				break;
++			case 1:
++				adev->compute_timeout = timeout;
++				break;
++			case 2:
++				adev->sdma_timeout = timeout;
++				break;
++			case 3:
++				adev->video_timeout = timeout;
++				break;
++			default:
++				break;
++			}
++		}
++		/*
++		 * There is only one value specified and
++		 * it should apply to all non-compute jobs.
++		 */
++		if (index == 1)
++			adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
++	}
++
++	return ret;
++}
+ 
+ /**
+  * amdgpu_device_init - initialize the driver
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 6d1ddde08de7..08c4405ad1d6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -88,8 +88,6 @@
+ 
+ #define AMDGPU_VERSION          "19.10.9.418"
+ 
+-#define AMDGPU_MAX_TIMEOUT_PARAM_LENTH	256
+-
+ int amdgpu_vram_limit = 0;
+ int amdgpu_vis_vram_limit = 0;
+ int amdgpu_gart_size = -1; /* auto */
+@@ -1329,71 +1327,6 @@ int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
+ 	return 0;
+ }
+ 
+-int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
+-{
+-	char *input = amdgpu_lockup_timeout;
+-	char *timeout_setting = NULL;
+-	int index = 0;
+-	long timeout;
+-	int ret = 0;
+-
+-	/*
+-	 * By default timeout for non compute jobs is 10000.
+-	 * And there is no timeout enforced on compute jobs.
+-	 * In SR-IOV or passthrough mode, timeout for compute
+-	 * jobs are 10000 by default.
+-	 */
+-	adev->gfx_timeout = msecs_to_jiffies(10000);
+-	adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
+-	if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
+-		adev->compute_timeout = adev->gfx_timeout;
+-	else
+-		adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
+-
+-	if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
+-		while ((timeout_setting = strsep(&input, ",")) &&
+-				strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
+-			ret = kstrtol(timeout_setting, 0, &timeout);
+-			if (ret)
+-				return ret;
+-
+-			if (timeout == 0) {
+-				index++;
+-				continue;
+-			} else if (timeout < 0) {
+-				timeout = MAX_SCHEDULE_TIMEOUT;
+-			} else {
+-				timeout = msecs_to_jiffies(timeout);
+-			}
+-
+-			switch (index++) {
+-			case 0:
+-				adev->gfx_timeout = timeout;
+-				break;
+-			case 1:
+-				adev->compute_timeout = timeout;
+-				break;
+-			case 2:
+-				adev->sdma_timeout = timeout;
+-				break;
+-			case 3:
+-				adev->video_timeout = timeout;
+-				break;
+-			default:
+-				break;
+-			}
+-		}
+-		/*
+-		 * There is only one value specified and
+-		 * it should apply to all non-compute jobs.
+-		 */
+-		if (index == 1)
+-			adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
+-	}
+-
+-	return ret;
+-}
+-
+ static bool
+ amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
+ 				 bool in_vblank_irq, int *vpos, int *hpos,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4036-drm-amdkfd-add-missing-void-argument-to-function-kgd.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4036-drm-amdkfd-add-missing-void-argument-to-function-kgd.patch
new file mode 100644
index 00000000..8cd9d271
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4036-drm-amdkfd-add-missing-void-argument-to-function-kgd.patch
@@ -0,0 +1,32 @@
+From ff567a7d75891bb772ec2ab57149f959b8c5c279 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Sat, 5 Oct 2019 18:58:08 +0100
+Subject: [PATCH 4036/4256] drm/amdkfd: add missing void argument to function
+ kgd2kfd_init
+
+Function kgd2kfd_init is missing a void argument, add it
+to clean up the non-ANSI function declaration.
+
+Acked-by: Randy Dunlap <rdunlap@infradead.org>
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_module.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
+index d0a05024d38c..c7b857b542e8 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
+@@ -90,7 +90,7 @@ static void kfd_exit(void)
+ 	kfd_chardev_exit();
+ }
+ 
+-int kgd2kfd_init()
++int kgd2kfd_init(void)
+ {
+ 	return kfd_init();
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4037-drm-amdkfd-Fix-a-vs-typo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4037-drm-amdkfd-Fix-a-vs-typo.patch
new file mode 100644
index 00000000..d7b6bcb9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4037-drm-amdkfd-Fix-a-vs-typo.patch
@@ -0,0 +1,31 @@
+From 61818f65cd061d7dc151b07a6890f89959a73b15 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Mon, 7 Oct 2019 11:52:10 +0300
+Subject: [PATCH 4037/4256] drm/amdkfd: Fix a && vs || typo
+
+In the current code if "device_info" is ever NULL then the kernel will
+Oops so probably || was intended instead of &&.
+
+Fixes: e392c887df97 ("drm/amdkfd: Use array to probe kfd2kgd_calls")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index bdf890912ff8..24728e70e871 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -504,7 +504,7 @@ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
+ 	device_info = kfd_supported_devices[asic_type][vf];
+ 	f2g = kfd2kgd_funcs[asic_type];
+ 
+-	if (!device_info && !f2g) {
++	if (!device_info || !f2g) {
+ 		dev_err(kfd_device, "%s %s not supported in kfd\n",
+ 			amdgpu_asic_name[asic_type], vf ? "VF" : "");
+ 		return NULL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4038-drm-amdgpu-Report-vram-vendor-with-sysfs-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4038-drm-amdgpu-Report-vram-vendor-with-sysfs-v3.patch
new file mode 100644
index 00000000..3e64a1fa
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4038-drm-amdgpu-Report-vram-vendor-with-sysfs-v3.patch
@@ -0,0 +1,241 @@
+From b2b22a3430c16d8d38c4a81776359955a3e1737e Mon Sep 17 00:00:00 2001
+From: Ori Messinger <Ori.Messinger@amd.com>
+Date: Wed, 2 Oct 2019 10:02:07 -0400
+Subject: [PATCH 4038/4256] drm/amdgpu: Report vram vendor with sysfs (v3)
+
+The vram vendor can be found as a separate sysfs file at:
+/sys/class/drm/card[X]/device/mem_info_vram_vendor
+The vram vendor is displayed as a string value.
+
+v2: Use correct bit masking, and cache vram_vendor in gmc
+v3: Drop unused functions for vram width, type, and vendor
+
+Change-Id: Iaa3ccf3f483ee6536281fe777772ba241a6e0d43
+Signed-off-by: Ori Messinger <Ori.Messinger@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c  | 14 +++++-
+ .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h  |  2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h       |  1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c  | 43 +++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c        |  6 ++-
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c         |  6 ++-
+ 6 files changed, 65 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+index fbff37bd2b03..a253a554f41f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+@@ -169,8 +169,11 @@ static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
+ 	return vram_type;
+ }
+ 
+-int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+-				      int *vram_width, int *vram_type)
++
++int
++amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
++				  int *vram_width, int *vram_type,
++				  int *vram_vendor)
+ {
+ 	struct amdgpu_mode_info *mode_info = &adev->mode_info;
+ 	int index, i = 0;
+@@ -180,6 +183,7 @@ int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+ 	union vram_module *vram_module;
+ 	u8 frev, crev;
+ 	u8 mem_type;
++	u8 mem_vendor;
+ 	u32 mem_channel_number;
+ 	u32 mem_channel_width;
+ 	u32 module_id;
+@@ -231,6 +235,9 @@ int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+ 				mem_channel_width = vram_module->v9.channel_width;
+ 				if (vram_width)
+ 					*vram_width = mem_channel_number * (1 << mem_channel_width);
++				mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
++				if (vram_vendor)
++					*vram_vendor = mem_vendor;
+ 				break;
+ 			case 4:
+ 				if (module_id > vram_info->v24.vram_module_num)
+@@ -248,6 +255,9 @@ int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+ 				mem_channel_width = vram_module->v10.channel_width;
+ 				if (vram_width)
+ 					*vram_width = mem_channel_number * (1 << mem_channel_width);
++				mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
++				if (vram_vendor)
++					*vram_vendor = mem_vendor;
+ 				break;
+ 			default:
+ 				return -EINVAL;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+index 82819f03e444..53449fc7baf4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+@@ -30,7 +30,7 @@ bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
+ void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);
+ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
+ int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+-				      int *vram_width, int *vram_type);
++	int *vram_width, int *vram_type, int *vram_vendor);
+ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev);
+ int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev);
+ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+index 387cf338c958..f9d62e80a64e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+@@ -157,6 +157,7 @@ struct amdgpu_gmc {
+ 	uint32_t                fw_version;
+ 	struct amdgpu_irq_src	vm_fault;
+ 	uint32_t		vram_type;
++	uint8_t			vram_vendor;
+ 	uint32_t                srbm_soft_reset;
+ 	bool			prt_warning;
+ 	uint64_t		stolen_size;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+index 59440f71d304..cd750c3f4c18 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+@@ -25,6 +25,8 @@
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
+ #include "amdgpu_vm.h"
++#include "amdgpu_atomfirmware.h"
++#include "atom.h"
+ 
+ struct amdgpu_vram_mgr {
+ 	struct drm_mm mm;
+@@ -103,6 +105,39 @@ static ssize_t amdgpu_mem_info_vis_vram_used_show(struct device *dev,
+ 		amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]));
+ }
+ 
++static ssize_t amdgpu_mem_info_vram_vendor(struct device *dev,
++						 struct device_attribute *attr,
++						 char *buf)
++{
++	struct drm_device *ddev = dev_get_drvdata(dev);
++	struct amdgpu_device *adev = ddev->dev_private;
++
++	switch (adev->gmc.vram_vendor) {
++	case SAMSUNG:
++		return snprintf(buf, PAGE_SIZE, "samsung\n");
++	case INFINEON:
++		return snprintf(buf, PAGE_SIZE, "infineon\n");
++	case ELPIDA:
++		return snprintf(buf, PAGE_SIZE, "elpida\n");
++	case ETRON:
++		return snprintf(buf, PAGE_SIZE, "etron\n");
++	case NANYA:
++		return snprintf(buf, PAGE_SIZE, "nanya\n");
++	case HYNIX:
++		return snprintf(buf, PAGE_SIZE, "hynix\n");
++	case MOSEL:
++		return snprintf(buf, PAGE_SIZE, "mosel\n");
++	case WINBOND:
++		return snprintf(buf, PAGE_SIZE, "winbond\n");
++	case ESMT:
++		return snprintf(buf, PAGE_SIZE, "esmt\n");
++	case MICRON:
++		return snprintf(buf, PAGE_SIZE, "micron\n");
++	default:
++		return snprintf(buf, PAGE_SIZE, "unknown\n");
++	}
++}
++
+ static DEVICE_ATTR(mem_info_vram_total, S_IRUGO,
+ 		   amdgpu_mem_info_vram_total_show, NULL);
+ static DEVICE_ATTR(mem_info_vis_vram_total, S_IRUGO,
+@@ -111,6 +146,8 @@ static DEVICE_ATTR(mem_info_vram_used, S_IRUGO,
+ 		   amdgpu_mem_info_vram_used_show, NULL);
+ static DEVICE_ATTR(mem_info_vis_vram_used, S_IRUGO,
+ 		   amdgpu_mem_info_vis_vram_used_show, NULL);
++static DEVICE_ATTR(mem_info_vram_vendor, S_IRUGO,
++		   amdgpu_mem_info_vram_vendor, NULL);
+ 
+ /**
+  * amdgpu_vram_mgr_init - init VRAM manager and DRM MM
+@@ -156,6 +193,11 @@ static int amdgpu_vram_mgr_init(struct ttm_mem_type_manager *man,
+ 		DRM_ERROR("Failed to create device file mem_info_vis_vram_used\n");
+ 		return ret;
+ 	}
++	ret = device_create_file(adev->dev, &dev_attr_mem_info_vram_vendor);
++	if (ret) {
++		DRM_ERROR("Failed to create device file mem_info_vram_vendor\n");
++		return ret;
++	}
+ 
+ 	return 0;
+ }
+@@ -182,6 +224,7 @@ static int amdgpu_vram_mgr_fini(struct ttm_mem_type_manager *man)
+ 	device_remove_file(adev->dev, &dev_attr_mem_info_vis_vram_total);
+ 	device_remove_file(adev->dev, &dev_attr_mem_info_vram_used);
+ 	device_remove_file(adev->dev, &dev_attr_mem_info_vis_vram_used);
++	device_remove_file(adev->dev, &dev_attr_mem_info_vram_vendor);
+ 	return 0;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index 055a8cbf889b..6a73e8d95f0a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -625,7 +625,7 @@ static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
+ static int gmc_v10_0_sw_init(void *handle)
+ {
+ 	int dma_bits;
+-	int r, vram_width = 0, vram_type = 0;
++	int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
+ 	gfxhub_v2_0_init(adev);
+@@ -633,13 +633,15 @@ static int gmc_v10_0_sw_init(void *handle)
+ 
+ 	spin_lock_init(&adev->gmc.invalidate_lock);
+ 
+-	r = amdgpu_atomfirmware_get_vram_info(adev, &vram_width, &vram_type);
++	r = amdgpu_atomfirmware_get_vram_info(adev,
++		&vram_width, &vram_type, &vram_vendor);
+ 	if (!amdgpu_emu_mode)
+ 		adev->gmc.vram_width = vram_width;
+ 	else
+ 		adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
+ 
+ 	adev->gmc.vram_type = vram_type;
++	adev->gmc.vram_vendor = vram_vendor;
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 2fa441d9c5a0..b5ecc12cfea2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -927,7 +927,7 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
+ static int gmc_v9_0_sw_init(void *handle)
+ {
+ 	int dma_bits;
+-	int r, vram_width = 0, vram_type = 0;
++	int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
+ 	gfxhub_v1_0_init(adev);
+@@ -938,7 +938,8 @@ static int gmc_v9_0_sw_init(void *handle)
+ 
+ 	spin_lock_init(&adev->gmc.invalidate_lock);
+ 
+-	r = amdgpu_atomfirmware_get_vram_info(adev, &vram_width, &vram_type);
++	r = amdgpu_atomfirmware_get_vram_info(adev,
++		&vram_width, &vram_type, &vram_vendor);
+ 	if (amdgpu_sriov_vf(adev))
+ 		/* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
+ 		 * and DF related registers is not readable, seems hardcord is the
+@@ -962,6 +963,7 @@ static int gmc_v9_0_sw_init(void *handle)
+ 	}
+ 
+ 	adev->gmc.vram_type = vram_type;
++	adev->gmc.vram_vendor = vram_vendor;
+ 	switch (adev->asic_type) {
+ 	case CHIP_RAVEN:
+ 		adev->num_vmhubs = 2;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4039-drm-amd-Fix-Kconfig-indentation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4039-drm-amd-Fix-Kconfig-indentation.patch
new file mode 100644
index 00000000..6637802b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4039-drm-amd-Fix-Kconfig-indentation.patch
@@ -0,0 +1,89 @@
+From e2c218f598bbe18eea17634546e95b5a3b01a3cb Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzk@kernel.org>
+Date: Mon, 7 Oct 2019 19:33:22 +0200
+Subject: [PATCH 4039/4256] drm/amd: Fix Kconfig indentation
+
+Adjust indentation from spaces to tab (+optional two spaces) as in
+coding style with command like:
+    $ sed -e 's/^        /\t/' -i */Kconfig
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
+---
+ drivers/gpu/drm/Kconfig             |  4 ++--
+ drivers/gpu/drm/amd/display/Kconfig | 32 ++++++++++++++---------------
+ 2 files changed, 18 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
+index 27e497e149c8..70d233948792 100644
+--- a/drivers/gpu/drm/Kconfig
++++ b/drivers/gpu/drm/Kconfig
+@@ -193,9 +193,9 @@ config DRM_AMDGPU
+ 	tristate "AMD GPU"
+ 	depends on DRM && PCI && MMU
+ 	select FW_LOADER
+-        select DRM_KMS_HELPER
++	select DRM_KMS_HELPER
+ 	select DRM_SCHED
+-        select DRM_TTM
++	select DRM_TTM
+ 	select POWER_SUPPLY
+ 	select HWMON
+ 	select BACKLIGHT_CLASS_DEVICE
+diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
+index b4504257873a..9eae7c67ceb5 100644
+--- a/drivers/gpu/drm/amd/display/Kconfig
++++ b/drivers/gpu/drm/amd/display/Kconfig
+@@ -22,16 +22,16 @@ config DRM_AMD_DC_DCN2_0
+ 	depends on DRM_AMD_DC && X86
+ 	depends on DRM_AMD_DC_DCN1_0
+ 	help
+-	    Choose this option if you want to have
+-	    Navi support for display engine
++	  Choose this option if you want to have
++	  Navi support for display engine
+ 
+ config DRM_AMD_DC_DCN2_1
+-        bool "DCN 2.1 family"
+-        depends on DRM_AMD_DC && X86
+-        depends on DRM_AMD_DC_DCN2_0
+-        help
+-            Choose this option if you want to have
+-            Renoir support for display engine
++	bool "DCN 2.1 family"
++	depends on DRM_AMD_DC && X86
++	depends on DRM_AMD_DC_DCN2_0
++	help
++	  Choose this option if you want to have
++	  Renoir support for display engine
+ 
+ config DRM_AMD_DC_DSC_SUPPORT
+ 	bool "DSC support"
+@@ -40,16 +40,16 @@ config DRM_AMD_DC_DSC_SUPPORT
+ 	depends on DRM_AMD_DC_DCN1_0
+ 	depends on DRM_AMD_DC_DCN2_0
+ 	help
+-	    Choose this option if you want to have
+-	    Dynamic Stream Compression support
++	  Choose this option if you want to have
++	  Dynamic Stream Compression support
+ 
+ config DRM_AMD_DC_HDCP
+-        bool "Enable HDCP support in DC"
+-        depends on DRM_AMD_DC
+-        help
+-         Choose this option
+-         if you want to support
+-         HDCP authentication
++	bool "Enable HDCP support in DC"
++	depends on DRM_AMD_DC
++	help
++	 Choose this option
++	 if you want to support
++	 HDCP authentication
+ 
+ config DEBUG_KERNEL_DC
+ 	bool "Enable kgdb break in DC"
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4040-drm-amdgpu-simplify-gds_compute_max_wave_id-computat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4040-drm-amdgpu-simplify-gds_compute_max_wave_id-computat.patch
new file mode 100644
index 00000000..74344eb2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4040-drm-amdgpu-simplify-gds_compute_max_wave_id-computat.patch
@@ -0,0 +1,43 @@
+From 7e43df13b1fcc8262cc247a0acf17d093aae4fe9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Wed, 25 Sep 2019 15:50:17 -0400
+Subject: [PATCH 4040/4256] drm/amdgpu: simplify gds_compute_max_wave_id
+ computation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Marek Olšák <marek.olsak@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 +++++--------
+ 1 file changed, 5 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 9daf28e83236..1df3a835e62f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -5275,15 +5275,12 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
+ 
+ static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
+ {
+-	/* init asic gds info */
+-	switch (adev->asic_type) {
+-	case CHIP_NAVI10:
+-	default:
+-		adev->gds.gds_size = 0x10000;
+-		adev->gds.gds_compute_max_wave_id = 0x4ff;
+-		break;
+-	}
++	unsigned total_cu = adev->gfx.config.max_cu_per_sh *
++			    adev->gfx.config.max_sh_per_se *
++			    adev->gfx.config.max_shader_engines;
+ 
++	adev->gds.gds_size = 0x10000;
++	adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
+ 	adev->gds.gws_size = 64;
+ 	adev->gds.oa_size = 16;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4041-drm-amdgpu-Clean-up-gmc_v9_0_gart_enable.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4041-drm-amdgpu-Clean-up-gmc_v9_0_gart_enable.patch
new file mode 100644
index 00000000..ed00bfa5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4041-drm-amdgpu-Clean-up-gmc_v9_0_gart_enable.patch
@@ -0,0 +1,133 @@
+From c6e54732f0548998dea2e134966781de6a275ca8 Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Mon, 7 Oct 2019 15:21:03 -0500
+Subject: [PATCH 4041/4256] drm/amdgpu: Clean up gmc_v9_0_gart_enable
+
+Many logic in this function are HDP set up,
+not gart set up. Moved those logic to gmc_v9_0_hw_init.
+No functional change.
+
+Change-Id: Ib00cc1ffd1e486e77571796dce53aa7506c0c55f
+Acked-by: Christian konig <christian.koenig@amd.com>
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 82 +++++++++++++--------------
+ 1 file changed, 41 insertions(+), 41 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index b5ecc12cfea2..cfe135544d24 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -1147,13 +1147,7 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
+  */
+ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
+ {
+-	int r, i;
+-	bool value;
+-	u32 tmp;
+-
+-	amdgpu_device_program_register_sequence(adev,
+-						golden_settings_vega10_hdp,
+-						ARRAY_SIZE(golden_settings_vega10_hdp));
++	int r;
+ 
+ 	if (adev->gart.bo == NULL) {
+ 		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
+@@ -1163,15 +1157,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
+ 	if (r)
+ 		return r;
+ 
+-	switch (adev->asic_type) {
+-	case CHIP_RAVEN:
+-		/* TODO for renoir */
+-		mmhub_v1_0_update_power_gating(adev, true);
+-		break;
+-	default:
+-		break;
+-	}
+-
+ 	r = gfxhub_v1_0_gart_enable(adev);
+ 	if (r)
+ 		return r;
+@@ -1183,6 +1168,46 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
+ 	if (r)
+ 		return r;
+ 
++	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
++		 (unsigned)(adev->gmc.gart_size >> 20),
++		 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
++	adev->gart.ready = true;
++	return 0;
++}
++
++static int gmc_v9_0_hw_init(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	bool value;
++	int r, i;
++	u32 tmp;
++
++	/* The sequence of these two function calls matters.*/
++	gmc_v9_0_init_golden_registers(adev);
++
++	if (adev->mode_info.num_crtc) {
++		if (adev->asic_type != CHIP_ARCTURUS) {
++			/* Lockout access through VGA aperture*/
++			WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
++
++			/* disable VGA render */
++			WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
++		}
++	}
++
++	amdgpu_device_program_register_sequence(adev,
++						golden_settings_vega10_hdp,
++						ARRAY_SIZE(golden_settings_vega10_hdp));
++
++	switch (adev->asic_type) {
++	case CHIP_RAVEN:
++		/* TODO for renoir */
++		mmhub_v1_0_update_power_gating(adev, true);
++		break;
++	default:
++		break;
++	}
++
+ 	WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
+ 
+ 	tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
+@@ -1211,31 +1236,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
+ 	if (adev->umc.funcs && adev->umc.funcs->init_registers)
+ 		adev->umc.funcs->init_registers(adev);
+ 
+-	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+-		 (unsigned)(adev->gmc.gart_size >> 20),
+-		 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
+-	adev->gart.ready = true;
+-	return 0;
+-}
+-
+-static int gmc_v9_0_hw_init(void *handle)
+-{
+-	int r;
+-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-
+-	/* The sequence of these two function calls matters.*/
+-	gmc_v9_0_init_golden_registers(adev);
+-
+-	if (adev->mode_info.num_crtc) {
+-		if (adev->asic_type != CHIP_ARCTURUS) {
+-			/* Lockout access through VGA aperture*/
+-			WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
+-
+-			/* disable VGA render */
+-			WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
+-		}
+-	}
+-
+ 	r = gmc_v9_0_gart_enable(adev);
+ 
+ 	return r;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4042-drm-amdgpu-Enable-gfx-cache-probing-on-HDP-write-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4042-drm-amdgpu-Enable-gfx-cache-probing-on-HDP-write-for.patch
new file mode 100644
index 00000000..5162db11
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4042-drm-amdgpu-Enable-gfx-cache-probing-on-HDP-write-for.patch
@@ -0,0 +1,35 @@
+From c0c1fc42ed27a2e44bb10e65769297d3d9147800 Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Mon, 7 Oct 2019 15:32:23 -0500
+Subject: [PATCH 4042/4256] drm/amdgpu: Enable gfx cache probing on HDP write
+ for arcturus
+
+This allows gfx cache to be probed and invalidated (for none-dirty cache lines)
+on a HDP write (from either another GPU or CPU). This should work only for the
+memory mapped as RW memory type newly added for arcturus, to achieve some cache
+coherence b/t multiple memory clients.
+
+Change-Id: I5c9a6a25d88cd75c71c88822123e0d4c067aa3f8
+Acked-by: Christian Konig <christian.koenig@amd.com>
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index cfe135544d24..6ddb8bdf77cc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -1204,6 +1204,9 @@ static int gmc_v9_0_hw_init(void *handle)
+ 		/* TODO for renoir */
+ 		mmhub_v1_0_update_power_gating(adev, true);
+ 		break;
++	case CHIP_ARCTURUS:
++		WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
++		break;
+ 	default:
+ 		break;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4043-drm-amdgpu-swSMU-custom-UMD-pstate-peak-clock-for-na.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4043-drm-amdgpu-swSMU-custom-UMD-pstate-peak-clock-for-na.patch
new file mode 100644
index 00000000..b846ca25
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4043-drm-amdgpu-swSMU-custom-UMD-pstate-peak-clock-for-na.patch
@@ -0,0 +1,114 @@
+From a76bded1ce531716cf755b9e42171e638dd08356 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Fri, 11 Oct 2019 08:45:41 +0800
+Subject: [PATCH 4043/4256] drm/amdgpu/swSMU: custom UMD pstate peak clock for
+ navi14
+
+add navi14 umd pstate peak clock support.
+
+NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK   1670 MHz
+NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK  1448 MHz
+NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK  1181 MHz
+NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK  1717 MHz
+NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK   1448 MHz
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 53 ++++++++++++++++------
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.h |  6 +++
+ 2 files changed, 45 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index e6490d2eb4f2..68cbcc792ec1 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1454,18 +1454,47 @@ static int navi10_set_peak_clock_by_device(struct smu_context *smu)
+ 	uint32_t sclk_freq = 0, uclk_freq = 0;
+ 	uint32_t uclk_level = 0;
+ 
+-	switch (adev->pdev->revision) {
+-	case 0xf0: /* XTX */
+-	case 0xc0:
+-		sclk_freq = NAVI10_PEAK_SCLK_XTX;
+-		break;
+-	case 0xf1: /* XT */
+-	case 0xc1:
+-		sclk_freq = NAVI10_PEAK_SCLK_XT;
++	switch (adev->asic_type) {
++	case CHIP_NAVI10:
++		switch (adev->pdev->revision) {
++		case 0xf0: /* XTX */
++		case 0xc0:
++			sclk_freq = NAVI10_PEAK_SCLK_XTX;
++			break;
++		case 0xf1: /* XT */
++		case 0xc1:
++			sclk_freq = NAVI10_PEAK_SCLK_XT;
++			break;
++		default: /* XL */
++			sclk_freq = NAVI10_PEAK_SCLK_XL;
++			break;
++		}
+ 		break;
+-	default: /* XL */
+-		sclk_freq = NAVI10_PEAK_SCLK_XL;
++	case CHIP_NAVI14:
++		switch (adev->pdev->revision) {
++		case 0xc7: /* XT */
++		case 0xf4:
++			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
++			break;
++		case 0xc1: /* XTM */
++		case 0xf2:
++			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
++			break;
++		case 0xc3: /* XLM */
++		case 0xf3:
++			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
++			break;
++		case 0xc5: /* XTX */
++		case 0xf6:
++			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
++			break;
++		default: /* XL */
++			sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
++			break;
++		}
+ 		break;
++	default:
++		return -EINVAL;
+ 	}
+ 
+ 	ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level);
+@@ -1488,10 +1517,6 @@ static int navi10_set_peak_clock_by_device(struct smu_context *smu)
+ static int navi10_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
+ {
+ 	int ret = 0;
+-	struct amdgpu_device *adev = smu->adev;
+-
+-	if (adev->asic_type != CHIP_NAVI10)
+-		return -EINVAL;
+ 
+ 	switch (level) {
+ 	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+index 620ff17c2fef..a37e37c5f105 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+@@ -27,6 +27,12 @@
+ #define NAVI10_PEAK_SCLK_XT  		(1755)
+ #define NAVI10_PEAK_SCLK_XL  		(1625)
+ 
++#define NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK      (1670)
++#define NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK     (1448)
++#define NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK     (1181)
++#define NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK     (1717)
++#define NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK      (1448)
++
+ extern void navi10_set_ppt_funcs(struct smu_context *smu);
+ 
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4044-drm-amd-display-Added-pixel-dynamic-expansion-contro.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4044-drm-amd-display-Added-pixel-dynamic-expansion-contro.patch
new file mode 100644
index 00000000..36df2639
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4044-drm-amd-display-Added-pixel-dynamic-expansion-contro.patch
@@ -0,0 +1,144 @@
+From baae5de0423aab2578facf11caad89f4770539f5 Mon Sep 17 00:00:00 2001
+From: Robin Singh <robin.singh@amd.com>
+Date: Thu, 22 Aug 2019 14:42:49 -0400
+Subject: [PATCH 4044/4256] drm/amd/display: Added pixel dynamic expansion
+ control.
+
+[Why]
+To compare the crc of the framebuffer data at input of
+display pipeline with the crc of the otg, we need to
+disable pixel formatter's dynamic expansion feature during
+crc capture and keep it enable in the normal operation.
+
+[HOW]
+Expose a new interface in DM and dc for pixel formatter
+(fmt dynamic bitdepth expansion control). Interface control
+the FMT_DYNAMIC_EXP_EN  bit, during crc capture keep
+it disabled.
+
+Signed-off-by: Robin Singh <robin.singh@amd.com>
+Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c |  9 ++++++--
+ drivers/gpu/drm/amd/display/dc/core/dc.c      | 21 +++++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/dc_hw_types.h  |  5 +++++
+ drivers/gpu/drm/amd/display/dc/dc_stream.h    |  3 +++
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c  |  3 +++
+ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h   |  1 +
+ 6 files changed, 40 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+index fa8e2c3ddf9d..f68f9f6d953e 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+@@ -122,11 +122,16 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
+         }
+ 
+         /* Configure dithering */
+-        if (!dm_need_crc_dither(source))
++        if (!dm_need_crc_dither(source)) {
+                 dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8);
+-        else
++		dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state,
++						DYN_EXPANSION_DISABLE);
++	} else {
+                 dc_stream_set_dither_option(stream_state,
+                                             DITHER_OPTION_DEFAULT);
++		dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state,
++						DYN_EXPANSION_AUTO);
++	}
+ 
+ unlock:
+         mutex_unlock(&adev->dm.dc_lock);
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 56861f796406..6c1de21380ce 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -408,6 +408,27 @@ bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
+ 	return false;
+ }
+ 
++void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
++		enum dc_dynamic_expansion option)
++{
++	/* OPP FMT dyn expansion updates*/
++	int i = 0;
++	struct pipe_ctx *pipe_ctx;
++
++	for (i = 0; i < MAX_PIPES; i++) {
++		if (dc->current_state->res_ctx.pipe_ctx[i].stream
++				== stream) {
++			pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
++			pipe_ctx->stream_res.opp->dyn_expansion = option;
++			pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
++					pipe_ctx->stream_res.opp,
++					COLOR_SPACE_YCBCR601,
++					stream->timing.display_color_depth,
++					stream->signal);
++		}
++	}
++}
++
+ void dc_stream_set_dither_option(struct dc_stream_state *stream,
+ 		enum dc_dither_option option)
+ {
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+index 2869b26d966a..e0856bb8511f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+@@ -578,6 +578,11 @@ enum dc_quantization_range {
+ 	QUANTIZATION_RANGE_LIMITED
+ };
+ 
++enum dc_dynamic_expansion {
++	DYN_EXPANSION_AUTO,
++	DYN_EXPANSION_DISABLE
++};
++
+ /* XFM */
+ 
+ /* used in  struct dc_plane_state */
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+index 3c061d4f214f..fdb6adc37857 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+@@ -451,6 +451,9 @@ void dc_stream_set_static_screen_events(struct dc *dc,
+ 					int num_streams,
+ 					const struct dc_static_screen_events *events);
+ 
++void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
++		enum dc_dynamic_expansion option);
++
+ void dc_stream_set_dither_option(struct dc_stream_state *stream,
+ 				 enum dc_dither_option option);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+index 7045c00edab9..5be042acf9fa 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+@@ -238,6 +238,9 @@ void opp1_set_dyn_expansion(
+ 			FMT_DYNAMIC_EXP_EN, 0,
+ 			FMT_DYNAMIC_EXP_MODE, 0);
+ 
++	if (opp->dyn_expansion == DYN_EXPANSION_DISABLE)
++		return;
++
+ 	/*00 - 10-bit -> 12-bit dynamic expansion*/
+ 	/*01 - 8-bit  -> 12-bit dynamic expansion*/
+ 	if (signal == SIGNAL_TYPE_HDMI_TYPE_A ||
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+index 957e9047381a..18def2b6fafe 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+@@ -208,6 +208,7 @@ struct output_pixel_processor {
+ 	struct mpc_tree mpc_tree_params;
+ 	bool mpcc_disconnect_pending[MAX_PIPES];
+ 	const struct opp_funcs *funcs;
++	uint32_t dyn_expansion;
+ };
+ 
+ enum fmt_stereo_action {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4045-drm-amd-display-Correct-values-in-AVI-infoframe.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4045-drm-amd-display-Correct-values-in-AVI-infoframe.patch
new file mode 100644
index 00000000..0ea95d82
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4045-drm-amd-display-Correct-values-in-AVI-infoframe.patch
@@ -0,0 +1,53 @@
+From cf4a4331984c2a3aa543d5c7f6cb24b6c5c0471e Mon Sep 17 00:00:00 2001
+From: Wayne Lin <Wayne.Lin@amd.com>
+Date: Wed, 4 Sep 2019 06:12:22 +0800
+Subject: [PATCH 4045/4256] drm/amd/display: Correct values in AVI infoframe
+
+[Why]
+While displaying 4k modes defined in HDMI1.4b, should set VIC to 0
+and use VSP HDMI_VIC to indicate the mode.
+
+[How]
+Use functions defined in drm to set up the VIC correspondingly.
+
+Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 8976321d1bcd..3be135654d00 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -3449,6 +3449,8 @@ static void fill_stream_properties_from_drm_display_mode(
+ 	struct dc_crtc_timing *timing_out = &stream->timing;
+ 	const struct drm_display_info *info = &connector->display_info;
+ 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
++	struct hdmi_vendor_infoframe hv_frame;
++	struct hdmi_avi_infoframe avi_frame;
+ 	memset(timing_out, 0, sizeof(struct dc_crtc_timing));
+ 
+ 	timing_out->h_border_left = 0;
+@@ -3486,6 +3488,17 @@ static void fill_stream_properties_from_drm_display_mode(
+ 			timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
+ 	}
+ 
++	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
++#if defined(HAVE_2ARGS_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE)
++		drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, mode_in);
++#else
++		drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, mode_in, false);
++#endif
++		timing_out->vic = avi_frame.video_code;
++		drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
++		timing_out->hdmi_vic = hv_frame.vic;
++	}
++
+ 	timing_out->h_addressable = mode_in->crtc_hdisplay;
+ 	timing_out->h_total = mode_in->crtc_htotal;
+ 	timing_out->h_sync_width =
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4046-drm-amd-display-skip-enable-stream-on-disconnected-d.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4046-drm-amd-display-skip-enable-stream-on-disconnected-d.patch
new file mode 100644
index 00000000..551a7e35
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4046-drm-amd-display-skip-enable-stream-on-disconnected-d.patch
@@ -0,0 +1,50 @@
+From c3fbc13c0bf2901059b8001f19d640449ddf3b57 Mon Sep 17 00:00:00 2001
+From: Wenjing Liu <Wenjing.Liu@amd.com>
+Date: Tue, 3 Sep 2019 17:15:48 -0400
+Subject: [PATCH 4046/4256] drm/amd/display: skip enable stream on disconnected
+ display
+
+[why]
+Virtual signal means there is no display attached.
+In this case we will assign a virtual signal type to the stream.
+We should only enable the front end of the stream but not the back end.
+
+[how]
+When stream is enabling with virtual signal type, skip backend programming.
+
+Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index ec2a249c13f0..ca4a57510e8c 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2716,6 +2716,10 @@ void core_link_enable_stream(
+ 	enum dc_status status;
+ 	DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
+ 
++	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) &&
++			dc_is_virtual_signal(pipe_ctx->stream->signal))
++		return;
++
+ 	if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
+ 		stream->link->link_enc->funcs->setup(
+ 			stream->link->link_enc,
+@@ -2858,6 +2862,10 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	struct dc_link *link = stream->sink->link;
+ 
++	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) &&
++			dc_is_virtual_signal(pipe_ctx->stream->signal))
++		return;
++
+ #if defined(CONFIG_DRM_AMD_DC_HDCP)
+ 	update_psp_stream_config(pipe_ctx, true);
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4047-drm-amd-display-Add-Logging-for-Gamma-Related-inform.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4047-drm-amd-display-Add-Logging-for-Gamma-Related-inform.patch
new file mode 100644
index 00000000..89430462
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4047-drm-amd-display-Add-Logging-for-Gamma-Related-inform.patch
@@ -0,0 +1,50 @@
+From 4ce116b1d5129918c2a56100605be3c8d88d053c Mon Sep 17 00:00:00 2001
+From: Wyatt Wood <wyatt.wood@amd.com>
+Date: Tue, 3 Sep 2019 10:29:00 -0400
+Subject: [PATCH 4047/4256] drm/amd/display: Add Logging for Gamma Related
+ information
+
+[Why]
+A recent bug showed that logging would be useful in debugging
+various gamma issues.
+
+[How]
+Fix formatting for easier graphing.
+Prevent performance hit when doing diag.
+
+Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c    | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 0123aec93285..78dbd17d3573 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1450,15 +1450,15 @@ static void log_tf(struct dc_context *ctx,
+ 	DC_LOG_ALL_TF_CHANNELS("Logging all channels...");
+ 
+ 	for (i = 0; i < hw_points_num; i++) {
+-		DC_LOG_GAMMA("R\t%d\t%llu\n", i, tf->tf_pts.red[i].value);
+-		DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu\n", i, tf->tf_pts.green[i].value);
+-		DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu\n", i, tf->tf_pts.blue[i].value);
++		DC_LOG_GAMMA("R\t%d\t%llu", i, tf->tf_pts.red[i].value);
++		DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu", i, tf->tf_pts.green[i].value);
++		DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu", i, tf->tf_pts.blue[i].value);
+ 	}
+ 
+ 	for (i = hw_points_num; i < MAX_NUM_HW_POINTS; i++) {
+-		DC_LOG_ALL_GAMMA("R\t%d\t%llu\n", i, tf->tf_pts.red[i].value);
+-		DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu\n", i, tf->tf_pts.green[i].value);
+-		DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu\n", i, tf->tf_pts.blue[i].value);
++		DC_LOG_ALL_GAMMA("R\t%d\t%llu", i, tf->tf_pts.red[i].value);
++		DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu", i, tf->tf_pts.green[i].value);
++		DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu", i, tf->tf_pts.blue[i].value);
+ 	}
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4048-drm-amd-display-Update-V_UPDATE-whenever-VSTARTUP-ch.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4048-drm-amd-display-Update-V_UPDATE-whenever-VSTARTUP-ch.patch
new file mode 100644
index 00000000..2a9f6b39
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4048-drm-amd-display-Update-V_UPDATE-whenever-VSTARTUP-ch.patch
@@ -0,0 +1,68 @@
+From 6c748dfa834d882b61f5aaedddb7b9456f63efb0 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Fri, 6 Sep 2019 16:24:54 -0400
+Subject: [PATCH 4048/4256] drm/amd/display: Update V_UPDATE whenever VSTARTUP
+ changes
+
+[Why]
+If VSTARTUP changes due to bandwidth requirements, we must
+recalculate and update VLINE2 as well for proper flip reporting.
+
+[How]
+After all calls to program_global_sync which reconfigures
+VSTARTUP, also make sure to update V_UPDATE (i.e. VLINE2 on DCNx).
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Sivapiriyan Kumarasamy <Sivapiriyan.Kumarasamy@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +++-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c        | 7 +++++++
+ 2 files changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 78dbd17d3573..3b55716bf63b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2509,8 +2509,10 @@ static void program_all_pipe_in_tree(
+ 		pipe_ctx->stream_res.tg->funcs->set_vtg_params(
+ 				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+ 
+-		dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
++		if (dc->hwss.setup_vupdate_interrupt)
++			dc->hwss.setup_vupdate_interrupt(pipe_ctx);
+ 
++		dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
+ 	}
+ 
+ 	if (pipe_ctx->plane_state != NULL)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 84aae9c05781..1b4aac185f3f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1370,6 +1370,9 @@ static void dcn20_program_pipe(
+ 
+ 		pipe_ctx->stream_res.tg->funcs->set_vtg_params(
+ 				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
++
++		if (dc->hwss.setup_vupdate_interrupt)
++			dc->hwss.setup_vupdate_interrupt(pipe_ctx);
+ 	}
+ 
+ 	if (pipe_ctx->update_flags.bits.odm)
+@@ -1581,8 +1584,12 @@ bool dcn20_update_bandwidth(
+ 
+ 			pipe_ctx->stream_res.tg->funcs->set_vtg_params(
+ 					pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
++
+ 			if (pipe_ctx->prev_odm_pipe == NULL)
+ 				dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
++
++			if (dc->hwss.setup_vupdate_interrupt)
++				dc->hwss.setup_vupdate_interrupt(pipe_ctx);
+ 		}
+ 
+ 		pipe_ctx->plane_res.hubp->funcs->hubp_setup(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4049-drm-amd-display-Reprogram-FMT-on-pipe-change.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4049-drm-amd-display-Reprogram-FMT-on-pipe-change.patch
new file mode 100644
index 00000000..4229fa99
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4049-drm-amd-display-Reprogram-FMT-on-pipe-change.patch
@@ -0,0 +1,58 @@
+From 71aae1ea6a0d0a6edb244e045d1fa012f96a1c29 Mon Sep 17 00:00:00 2001
+From: Julian Parkin <julian.parkin@amd.com>
+Date: Thu, 22 Aug 2019 16:32:05 -0400
+Subject: [PATCH 4049/4256] drm/amd/display: Reprogram FMT on pipe change
+
+[Why]
+When planes are added or removed from a stream, the change
+in pipe usage from dynamic MPC combine can cause a second
+stream using ODM combine to pick a different pipe to combine with.
+
+In this scenario, a different OPP is connected to the ODM without
+programming its FMT.
+
+[How]
+Reprogram the FMT in dcn20_program_pipe whenever a pipe is
+newly enabled, or when its opp changes.
+
+Signed-off-by: Julian Parkin <julian.parkin@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 20 +++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 1b4aac185f3f..4a0038293569 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1399,6 +1399,26 @@ static void dcn20_program_pipe(
+ 	 */
+ 	if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf)
+ 		dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
++
++	/* If the pipe has been enabled or has a different opp, we
++	 * should reprogram the fmt. This deals with cases where
++	 * interation between mpc and odm combine on different streams
++	 * causes a different pipe to be chosen to odm combine with.
++	 */
++	if (pipe_ctx->update_flags.bits.enable
++	    || pipe_ctx->update_flags.bits.opp_changed) {
++
++		pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
++			pipe_ctx->stream_res.opp,
++			COLOR_SPACE_YCBCR601,
++			pipe_ctx->stream->timing.display_color_depth,
++			pipe_ctx->stream->signal);
++
++		pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
++			pipe_ctx->stream_res.opp,
++			&pipe_ctx->stream->bit_depth_params,
++			&pipe_ctx->stream->clamping);
++	}
+ }
+ 
+ static bool does_pipe_need_lock(struct pipe_ctx *pipe)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4050-drm-amd-display-fix-pipe-re-assignment-when-odm-pres.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4050-drm-amd-display-fix-pipe-re-assignment-when-odm-pres.patch
new file mode 100644
index 00000000..93244493
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4050-drm-amd-display-fix-pipe-re-assignment-when-odm-pres.patch
@@ -0,0 +1,33 @@
+From 4cea2bf1c0d33919ff218aa8a46152d6ce3aa7ad Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Fri, 6 Sep 2019 11:12:14 -0400
+Subject: [PATCH 4050/4256] drm/amd/display: fix pipe re-assignment when odm
+ present
+
+Currently pipe split may steal an existing ODM pipe depending on stream
+sequence. This change prevents that from happening as easily.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Gary Kattan <Gary.Kattan@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 502498675226..5af85cd67dbb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2231,7 +2231,8 @@ static struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
+ 		 */
+ 		if (secondary_pipe == NULL) {
+ 			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
+-				if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL) {
++				if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL
++						&& dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {
+ 					preferred_pipe_idx = j;
+ 
+ 					if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4051-drm-amd-display-fix-hotplug-during-display-off.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4051-drm-amd-display-fix-hotplug-during-display-off.patch
new file mode 100644
index 00000000..72854024
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4051-drm-amd-display-fix-hotplug-during-display-off.patch
@@ -0,0 +1,286 @@
+From 5bf22bc8d5732211aa6f4ebd81c91acd1ae3a3eb Mon Sep 17 00:00:00 2001
+From: Joseph Gravenor <joseph.gravenor@amd.com>
+Date: Wed, 4 Sep 2019 12:43:05 -0400
+Subject: [PATCH 4051/4256] drm/amd/display: fix hotplug during display off
+
+[why]
+HPD is not suppressed when we lower
+clocks on renoir. B/c of this we do link
+training when the 48mhz refclk is off, which
+will cause ASIC hang.
+
+[how]
+Exit optimized power state for detection purpose.
+
+Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 82 +++++++++++++++++--
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h |  1 -
+ .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c   | 15 +++-
+ .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h   |  2 +-
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 21 ++++-
+ drivers/gpu/drm/amd/display/dc/dc.h           |  7 +-
+ .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  7 ++
+ 7 files changed, 119 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 787f94d815f4..c0e58434be39 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -52,6 +52,44 @@
+ #define REG(reg_name) \
+ 	(CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
+ 
++
++/* TODO: evaluate how to lower or disable all dcn clocks in screen off case */
++int rn_get_active_display_cnt_wa(
++		struct dc *dc,
++		struct dc_state *context)
++{
++	int i, display_count;
++	bool hdmi_present = false;
++
++	display_count = 0;
++	for (i = 0; i < context->stream_count; i++) {
++		const struct dc_stream_state *stream = context->streams[i];
++
++		if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
++			hdmi_present = true;
++	}
++
++	for (i = 0; i < dc->link_count; i++) {
++		const struct dc_link *link = dc->links[i];
++
++		/*
++		 * Only notify active stream or virtual stream.
++		 * Need to notify virtual stream to work around
++		 * headless case. HPD does not fire when system is in
++		 * S0i2.
++		 */
++		/* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
++		if (link->link_enc->funcs->is_dig_enabled(link->link_enc))
++			display_count++;
++	}
++
++	/* WA for hang on HDMI after display off back back on*/
++	if (display_count == 0 && hdmi_present)
++		display_count = 1;
++
++	return display_count;
++}
++
+ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
+ 			struct dc_state *context,
+ 			bool safe_to_lower)
+@@ -62,17 +100,36 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
+ 	int display_count;
+ 	bool update_dppclk = false;
+ 	bool update_dispclk = false;
+-	bool enter_display_off = false;
+ 	bool dpp_clock_lowered = false;
+-	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
+ 
+-	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
++	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
+ 
+-	if (display_count == 0)
+-		enter_display_off = true;
++	if (dc->work_arounds.skip_clock_update)
++		return;
+ 
+-	if (enter_display_off == safe_to_lower) {
+-		rn_vbios_smu_set_display_count(clk_mgr, display_count);
++	/*
++	 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
++	 * also if safe to lower is false, we just go in the higher state
++	 */
++	if (safe_to_lower) {
++		/* check that we're not already in lower */
++		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_OPTIMIZED) {
++
++			display_count = rn_get_active_display_cnt_wa(dc, context);
++			/* if we can go lower, go lower */
++			if (display_count == 0) {
++				rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_OPTIMIZED);
++				/* update power state */
++				clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_OPTIMIZED;
++			}
++		}
++	} else {
++		/* check that we're not already in the normal state */
++		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_NORMAL) {
++			rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_NORMAL);
++			/* update power state */
++			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_NORMAL;
++		}
+ 	}
+ 
+ 	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
+@@ -329,10 +386,19 @@ void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
+ 	rn_vbios_smu_enable_pme_wa(clk_mgr);
+ }
+ 
++void rn_init_clocks(struct clk_mgr *clk_mgr)
++{
++	memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
++	// Assumption is that boot state always supports pstate
++	clk_mgr->clks.p_state_change_support = true;
++	clk_mgr->clks.prev_p_state_change_support = true;
++	clk_mgr->clks.pwr_state = DCN_PWR_STATE_NORMAL;
++}
++
+ static struct clk_mgr_funcs dcn21_funcs = {
+ 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
+ 	.update_clocks = rn_update_clocks,
+-	.init_clocks = dcn2_init_clocks,
++	.init_clocks = rn_init_clocks,
+ 	.enable_pme_wa = rn_enable_pme_wa,
+ 	/* .dump_clk_registers = rn_dump_clk_registers */
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
+index aadec06fde10..958939049add 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
+@@ -30,7 +30,6 @@ struct rn_clk_registers {
+ 	uint32_t CLK1_CLK0_CURRENT_CNT; /* DPREFCLK */
+ };
+ 
+-
+ void rn_clk_mgr_construct(struct dc_context *ctx,
+ 		struct clk_mgr_internal *clk_mgr,
+ 		struct pp_smu_funcs *pp_smu,
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+index 50984c1811bb..fd919b82e902 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+@@ -175,12 +175,19 @@ int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_
+ 	return actual_dppclk_set_mhz * 1000;
+ }
+ 
+-void rn_vbios_smu_set_display_count(struct clk_mgr_internal *clk_mgr, int display_count)
++void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum dcn_pwr_state state)
+ {
++	int disp_count;
++
++	if (state == DCN_PWR_STATE_OPTIMIZED)
++		disp_count = 0;
++	else
++		disp_count = 1;
++
+ 	rn_vbios_smu_send_msg_with_param(
+-			clk_mgr,
+-			VBIOSSMC_MSG_SetDisplayCount,
+-			display_count);
++		clk_mgr,
++		VBIOSSMC_MSG_SetDisplayCount,
++		disp_count);
+ }
+ 
+ void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr)
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h
+index da3a49487c6d..fe2986a2c7a2 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h
+@@ -33,7 +33,7 @@ int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int reque
+ int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
+ void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
+ int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
+-void rn_vbios_smu_set_display_count(struct clk_mgr_internal *clk_mgr, int display_count);
++void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, int display_count);
+ void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr);
+ void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index ca4a57510e8c..80ddde0f0262 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -741,7 +741,7 @@ static bool wait_for_alt_mode(struct dc_link *link)
+  * This does not create remote sinks but will trigger DM
+  * to start MST detection if a branch is detected.
+  */
+-bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
++bool dc_link_detect_helper(struct dc_link *link, enum dc_detect_reason reason)
+ {
+ 	struct dc_sink_init_data sink_init_data = { 0 };
+ 	struct display_sink_capability sink_caps = { 0 };
+@@ -757,6 +757,7 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
+ 	bool same_dpcd = true;
+ 	enum dc_connection_type new_connection_type = dc_connection_none;
+ 	bool perform_dp_seamless_boot = false;
++
+ 	DC_LOGGER_INIT(link->ctx->logger);
+ 
+ 	if (dc_is_virtual_signal(link->connector_signal))
+@@ -1063,6 +1064,24 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
+ 		dc_sink_release(prev_sink);
+ 
+ 	return true;
++
++}
++
++bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
++{
++	const struct dc *dc = link->dc;
++	bool ret;
++	/* get out of low power state */
++
++	if (dc->hwss.exit_optimized_pwr_state)
++		dc->hwss.exit_optimized_pwr_state(dc, dc->current_state);
++
++	ret = dc_link_detect_helper(link, reason);
++
++	if (dc->hwss.optimize_pwr_state)
++		dc->hwss.optimize_pwr_state(dc, dc->current_state);
++
++	return ret;
+ }
+ 
+ bool dc_link_get_hpd_state(struct dc_link *dc_link)
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 9185297d93c4..0921f9101025 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -246,6 +246,11 @@ enum wm_report_mode {
+ 	WM_REPORT_OVERRIDE = 1,
+ };
+ 
++enum dcn_pwr_state {
++	DCN_PWR_STATE_OPTIMIZED = 0,
++	DCN_PWR_STATE_NORMAL = 1
++};
++
+ /*
+  * For any clocks that may differ per pipe
+  * only the max is stored in this structure
+@@ -260,7 +265,7 @@ struct dc_clocks {
+ 	int phyclk_khz;
+ 	int dramclk_khz;
+ 	bool p_state_change_support;
+-
++	enum dcn_pwr_state pwr_state;
+ 	/*
+ 	 * Elements below are not compared for the purposes of
+ 	 * optimization required
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index cbac3b61da94..de9d0a312180 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -232,6 +232,13 @@ struct hw_sequencer_funcs {
+ 			struct dc *dc,
+ 			struct dc_state *context);
+ 
++	void (*exit_optimized_pwr_state)(
++			const struct dc *dc,
++			struct dc_state *context);
++	void (*optimize_pwr_state)(
++			const struct dc *dc,
++			struct dc_state *context);
++
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	bool (*update_bandwidth)(
+ 			struct dc *dc,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4052-drm-amd-display-add-support-for-VSIP-info-packet.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4052-drm-amd-display-add-support-for-VSIP-info-packet.patch
new file mode 100644
index 00000000..e8fad51d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4052-drm-amd-display-add-support-for-VSIP-info-packet.patch
@@ -0,0 +1,150 @@
+From 895fe14ebb2fac216ae82ea4d18f04cbf4f3691c Mon Sep 17 00:00:00 2001
+From: Wayne Lin <Wayne.Lin@amd.com>
+Date: Wed, 4 Sep 2019 05:18:31 +0800
+Subject: [PATCH 4052/4256] drm/amd/display: add support for VSIP info packet
+
+[Why]
+The vendor specific infoframe is needed for HDMI while displaying
+specific modes.
+DC supports sending it, but we aren't currently building it
+
+[How]
+Add mod_build_hf_vsif_infopacket() to build the vendor specific
+info packet.
+
+Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../amd/display/modules/inc/mod_info_packet.h |  3 +
+ .../display/modules/info_packet/info_packet.c | 98 +++++++++++++++++++
+ 2 files changed, 101 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
+index d930bdecb117..ca8ce3c55337 100644
+--- a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
+@@ -35,4 +35,7 @@ struct mod_vrr_params;
+ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
+ 		struct dc_info_packet *info_packet);
+ 
++void mod_build_hf_vsif_infopacket(const struct dc_stream_state *stream,
++		struct dc_info_packet *info_packet, int ALLMEnabled, int ALLMValue);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
+index d885d642ed7f..db6b08f6d093 100644
+--- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
++++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
+@@ -31,6 +31,7 @@
+ #include "dc.h"
+ 
+ #define HDMI_INFOFRAME_TYPE_VENDOR 0x81
++#define HF_VSIF_VERSION 1
+ 
+ // VTEM Byte Offset
+ #define VTEM_PB0		0
+@@ -395,3 +396,100 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
+ 
+ }
+ 
++/**
++ *****************************************************************************
++ *  Function: mod_build_hf_vsif_infopacket
++ *
++ *  @brief
++ *     Prepare HDMI Vendor Specific info frame.
++ *     Follows HDMI Spec to build up Vendor Specific info frame
++ *
++ *  @param [in] stream: contains data we may need to construct VSIF (i.e. timing_3d_format, etc.)
++ *  @param [out] info_packet:   output structure where to store VSIF
++ *****************************************************************************
++ */
++void mod_build_hf_vsif_infopacket(const struct dc_stream_state *stream,
++		struct dc_info_packet *info_packet, int ALLMEnabled, int ALLMValue)
++{
++		unsigned int length = 5;
++		bool hdmi_vic_mode = false;
++		uint8_t checksum = 0;
++		uint32_t i = 0;
++		enum dc_timing_3d_format format;
++		bool bALLM = (bool)ALLMEnabled;
++		bool bALLMVal = (bool)ALLMValue;
++
++		info_packet->valid = false;
++		format = stream->timing.timing_3d_format;
++		if (stream->view_format == VIEW_3D_FORMAT_NONE)
++			format = TIMING_3D_FORMAT_NONE;
++
++		if (stream->timing.hdmi_vic != 0
++				&& stream->timing.h_total >= 3840
++				&& stream->timing.v_total >= 2160
++				&& format == TIMING_3D_FORMAT_NONE)
++			hdmi_vic_mode = true;
++
++		if ((format == TIMING_3D_FORMAT_NONE) && !hdmi_vic_mode && !bALLM)
++			return;
++
++		info_packet->sb[1] = 0x03;
++		info_packet->sb[2] = 0x0C;
++		info_packet->sb[3] = 0x00;
++
++		if (bALLM) {
++			info_packet->sb[1] = 0xD8;
++			info_packet->sb[2] = 0x5D;
++			info_packet->sb[3] = 0xC4;
++			info_packet->sb[4] = HF_VSIF_VERSION;
++		}
++
++		if (format != TIMING_3D_FORMAT_NONE)
++			info_packet->sb[4] = (2 << 5);
++
++		else if (hdmi_vic_mode)
++			info_packet->sb[4] = (1 << 5);
++
++		switch (format) {
++		case TIMING_3D_FORMAT_HW_FRAME_PACKING:
++		case TIMING_3D_FORMAT_SW_FRAME_PACKING:
++			info_packet->sb[5] = (0x0 << 4);
++			break;
++
++		case TIMING_3D_FORMAT_SIDE_BY_SIDE:
++		case TIMING_3D_FORMAT_SBS_SW_PACKED:
++			info_packet->sb[5] = (0x8 << 4);
++			length = 6;
++			break;
++
++		case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
++		case TIMING_3D_FORMAT_TB_SW_PACKED:
++			info_packet->sb[5] = (0x6 << 4);
++			break;
++
++		default:
++			break;
++		}
++
++		if (hdmi_vic_mode)
++			info_packet->sb[5] = stream->timing.hdmi_vic;
++
++		info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR;
++		info_packet->hb1 = 0x01;
++		info_packet->hb2 = (uint8_t) (length);
++
++		if (bALLM)
++			info_packet->sb[5] = (info_packet->sb[5] & ~0x02) | (bALLMVal << 1);
++
++		checksum += info_packet->hb0;
++		checksum += info_packet->hb1;
++		checksum += info_packet->hb2;
++
++		for (i = 1; i <= length; i++)
++			checksum += info_packet->sb[i];
++
++		info_packet->sb[0] = (uint8_t) (0x100 - checksum);
++
++		info_packet->valid = true;
++}
++
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4053-drm-amd-display-add-explicit-comparator-as-default-o.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4053-drm-amd-display-add-explicit-comparator-as-default-o.patch
new file mode 100644
index 00000000..c5a6468f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4053-drm-amd-display-add-explicit-comparator-as-default-o.patch
@@ -0,0 +1,104 @@
+From c28f5502e5203347bb2ef3cbdd816b2e2ad7611e Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Mon, 9 Sep 2019 11:05:33 -0400
+Subject: [PATCH 4053/4256] drm/amd/display: add explicit comparator as default
+ optimization check
+
+[why]
+memcmp is vulnerable to regression due to dc_clocks structures not being
+organized properly (not "current" clock related structures being at the beginning
+of the structure) and causes unnecessary setting of the optimize bit
+
+[how]
+add a dcn sepcific comparator, implement for dcn2
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c  | 24 +++++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/core/dc.c      | 12 ++++++++--
+ .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   |  3 +++
+ 3 files changed, 37 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index 559e16983f91..ecd2cb4840e3 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -349,12 +349,36 @@ void dcn2_get_clock(struct clk_mgr *clk_mgr,
+ 	}
+ }
+ 
++static bool dcn2_are_clock_states_equal(struct dc_clocks *a,
++		struct dc_clocks *b)
++{
++	if (a->dispclk_khz != b->dispclk_khz)
++		return false;
++	else if (a->dppclk_khz != b->dppclk_khz)
++		return false;
++	else if (a->dcfclk_khz != b->dcfclk_khz)
++		return false;
++	else if (a->socclk_khz != b->socclk_khz)
++		return false;
++	else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
++		return false;
++	else if (a->phyclk_khz != b->phyclk_khz)
++		return false;
++	else if (a->dramclk_khz != b->dramclk_khz)
++		return false;
++	else if (a->p_state_change_support != b->p_state_change_support)
++		return false;
++
++	return true;
++}
++
+ static struct clk_mgr_funcs dcn2_funcs = {
+ 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
+ 	.update_clocks = dcn2_update_clocks,
+ 	.init_clocks = dcn2_init_clocks,
+ 	.enable_pme_wa = dcn2_enable_pme_wa,
+ 	.get_clock = dcn2_get_clock,
++	.are_clock_states_equal = dcn2_are_clock_states_equal,
+ };
+ 
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 6c1de21380ce..85be4db9dcbf 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1678,8 +1678,16 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
+ 			updates[i].surface->update_flags.raw = 0xFFFFFFFF;
+ 	}
+ 
+-	if (type == UPDATE_TYPE_FAST && memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0)
+-		dc->optimized_required = true;
++	if (type == UPDATE_TYPE_FAST) {
++		// If there's an available clock comparator, we use that.
++		if (dc->clk_mgr->funcs->are_clock_states_equal) {
++			if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
++				dc->optimized_required = true;
++		// Else we fallback to mem compare.
++		} else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
++			dc->optimized_required = true;
++		}
++	}
+ 
+ 	return type;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+index 76f9ad1b23df..2fdd0ba93beb 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+@@ -180,6 +180,9 @@ struct clk_mgr_funcs {
+ 			struct dc_state *context,
+ 			enum dc_clock_type clock_type,
+ 			struct dc_clock_config *clock_cfg);
++
++	bool (*are_clock_states_equal) (struct dc_clocks *a,
++			struct dc_clocks *b);
+ };
+ 
+ struct clk_mgr {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4054-drm-amd-display-Add-missing-shifts-and-masks-for-dpp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4054-drm-amd-display-Add-missing-shifts-and-masks-for-dpp.patch
new file mode 100644
index 00000000..2e997ceb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4054-drm-amd-display-Add-missing-shifts-and-masks-for-dpp.patch
@@ -0,0 +1,42 @@
+From 8d9971b9e977ee47a56eff65fb251ecd52baef25 Mon Sep 17 00:00:00 2001
+From: Joshua Aberback <joshua.aberback@amd.com>
+Date: Fri, 6 Sep 2019 17:34:19 -0400
+Subject: [PATCH 4054/4256] drm/amd/display: Add missing shifts and masks for
+ dpp registers on dcn2
+
+[Why]
+The register CM_TEST_DEBUG_DATA is used in dpp1_program_input_csc, which is
+called from dpp2_cnv_setup, but the shifts and masks for the fields of that
+register are not initialized for dcn2. This causes all reads of that register
+to return 0.
+
+Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
+Reviewed-by: Jaehyun Chung <Jaehyun.Chung@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 5af85cd67dbb..2f1dc0277e48 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -579,11 +579,13 @@ static const struct dcn2_dpp_registers tf_regs[] = {
+ };
+ 
+ static const struct dcn2_dpp_shift tf_shift = {
+-		TF_REG_LIST_SH_MASK_DCN20(__SHIFT)
++		TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
++		TF_DEBUG_REG_LIST_SH_DCN10
+ };
+ 
+ static const struct dcn2_dpp_mask tf_mask = {
+-		TF_REG_LIST_SH_MASK_DCN20(_MASK)
++		TF_REG_LIST_SH_MASK_DCN20(_MASK),
++		TF_DEBUG_REG_LIST_MASK_DCN10
+ };
+ 
+ #define dwbc_regs_dcn2(id)\
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4055-drm-amd-display-3.2.52.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4055-drm-amd-display-3.2.52.patch
new file mode 100644
index 00000000..0fe24618
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4055-drm-amd-display-3.2.52.patch
@@ -0,0 +1,28 @@
+From b156df7945ea57c1e27c52e36fcfa9f3c6acf72a Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Mon, 9 Sep 2019 10:27:31 -0400
+Subject: [PATCH 4055/4256] drm/amd/display: 3.2.52
+
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 0921f9101025..3dfc5704bb59 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.51.1"
++#define DC_VER "3.2.52"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4056-drm-amd-display-build-up-VSIF-infopacket.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4056-drm-amd-display-build-up-VSIF-infopacket.patch
new file mode 100644
index 00000000..9c1a4af7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4056-drm-amd-display-build-up-VSIF-infopacket.patch
@@ -0,0 +1,37 @@
+From d1167cf1045fbef72cb0604225a0d929bef790d8 Mon Sep 17 00:00:00 2001
+From: Wayne Lin <Wayne.Lin@amd.com>
+Date: Wed, 4 Sep 2019 05:31:16 +0800
+Subject: [PATCH 4056/4256] drm/amd/display: build up VSIF infopacket
+
+[Why]
+Didn't send VSIF infopacket when it's 4k mode defined in HDMI 1.4b.
+For HDMI 1.4b, While displaying 4k modes, it should send VSP.
+
+[How]
+Call mod_build_hf_vsif_infopacket() function to build info frame
+and send it.
+
+Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 3be135654d00..be90836269b4 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -3792,6 +3792,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ 
+ 	update_stream_signal(stream, sink);
+ 
++	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
++		mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket, false, false);
++
+ finish:
+ 	dc_sink_release(sink);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4057-drm-amd-display-check-phy-dpalt-lane-count-config.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4057-drm-amd-display-check-phy-dpalt-lane-count-config.patch
new file mode 100644
index 00000000..4b5fdc85
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4057-drm-amd-display-check-phy-dpalt-lane-count-config.patch
@@ -0,0 +1,120 @@
+From 0c542eaba5d96996e04bf61828430f1a9ab6fa87 Mon Sep 17 00:00:00 2001
+From: Lewis Huang <Lewis.Huang@amd.com>
+Date: Thu, 5 Sep 2019 15:33:58 +0800
+Subject: [PATCH 4057/4256] drm/amd/display: check phy dpalt lane count config
+
+[Why]
+Type-c PHY config is not align with dpcd lane count.
+When those values didn't match, it cause driver do
+link training with 4 lane but phy only can output 2 lane.
+The link trainig always fail.
+
+[How]
+1. Modify get_max_link_cap function. According DPALT_DP4
+to update max lane count.
+2. Add dp_mst_verify_link_cap to handle MST case because
+we didn't call dp_mst_verify_link_cap for MST case.
+
+Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c    |  3 ++-
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 16 ++++++++++++++++
+ .../amd/display/dc/dcn10/dcn10_link_encoder.h    |  1 +
+ drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h  |  3 +++
+ .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h |  4 ++++
+ 5 files changed, 26 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 80ddde0f0262..f352f6028293 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -870,7 +870,8 @@ bool dc_link_detect_helper(struct dc_link *link, enum dc_detect_reason reason)
+ 				 * empty which leads to allocate_mst_payload() has "0"
+ 				 * pbn_per_slot value leading to exception on dc_fixpt_div()
+ 				 */
+-				link->verified_link_cap = link->reported_link_cap;
++				dp_verify_mst_link_cap(link);
++
+ 				if (prev_sink != NULL)
+ 					dc_sink_release(prev_sink);
+ 				return false;
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 7c78caf7a602..701b73926616 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -1409,6 +1409,9 @@ static struct dc_link_settings get_max_link_cap(struct dc_link *link)
+ 	if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
+ 		max_link_cap.link_rate = LINK_RATE_HIGH3;
+ 
++	if (link->link_enc->funcs->get_max_link_cap)
++		link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
++
+ 	/* Lower link settings based on sink's link cap */
+ 	if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
+ 		max_link_cap.lane_count =
+@@ -1670,6 +1673,19 @@ bool dp_verify_link_cap_with_retries(
+ 	return success;
+ }
+ 
++bool dp_verify_mst_link_cap(
++	struct dc_link *link)
++{
++	struct dc_link_settings max_link_cap = {0};
++
++	max_link_cap = get_max_link_cap(link);
++	link->verified_link_cap = get_common_supported_link_settings(
++		link->reported_link_cap,
++		max_link_cap);
++
++	return true;
++}
++
+ static struct dc_link_settings get_common_supported_link_settings(
+ 		struct dc_link_settings link_setting_a,
+ 		struct dc_link_settings link_setting_b)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+index 8bf5f0f2301d..0c12395cfa36 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+@@ -337,6 +337,7 @@ struct dcn10_link_enc_registers {
+ 		type RDPCS_TX_FIFO_ERROR_MASK;\
+ 		type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\
+ 		type RDPCS_DPALT_4LANE_TOGGLE_MASK;\
++		type RDPCS_PHY_DPALT_DP4;\
+ 		type RDPCS_PHY_DPALT_DISABLE;\
+ 		type RDPCS_PHY_DPALT_DISABLE_ACK;\
+ 		type RDPCS_PHY_DP_MPLLB_V2I;\
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+index 08a4df2c61a8..967706e7898e 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+@@ -43,6 +43,9 @@ bool dp_verify_link_cap_with_retries(
+ 	struct dc_link_settings *known_limit_link_setting,
+ 	int attempts);
+ 
++bool dp_verify_mst_link_cap(
++	struct dc_link *link);
++
+ bool dp_validate_mode_timing(
+ 	struct dc_link *link,
+ 	const struct dc_crtc_timing *timing);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+index abb4e4237fb6..b21909216fb6 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+@@ -184,6 +184,10 @@ struct link_encoder_funcs {
+ 	bool (*fec_is_active)(struct link_encoder *enc);
+ #endif
+ 	bool (*is_in_alt_mode) (struct link_encoder *enc);
++
++	void (*get_max_link_cap)(struct link_encoder *enc,
++		struct dc_link_settings *link_settings);
++
+ 	enum signal_type (*get_dig_mode)(
+ 		struct link_encoder *enc);
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4058-drm-amd-display-Restore-should_update_pstate_support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4058-drm-amd-display-Restore-should_update_pstate_support.patch
new file mode 100644
index 00000000..a27a9f8e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4058-drm-amd-display-Restore-should_update_pstate_support.patch
@@ -0,0 +1,43 @@
+From 90651efcf8165390f653b4e74552d2dc705a26b0 Mon Sep 17 00:00:00 2001
+From: Joshua Aberback <joshua.aberback@amd.com>
+Date: Thu, 12 Sep 2019 13:14:52 -0400
+Subject: [PATCH 4058/4256] drm/amd/display: Restore
+ should_update_pstate_support after bad revert
+
+[Why]
+This function was mistakenly reverted as part of a legitimate revert. The
+old version that was reverted to has bad logic, and is causing situations
+where p-state change support is being toggled when it shouldn't be,
+resulting in hangs.
+
+Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h   | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+index 213046de1675..7dd46eb96d67 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+@@ -281,8 +281,14 @@ static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_cl
+ 
+ static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support)
+ {
+-	// Whenever we are transitioning pstate support, we always want to notify prior to committing state
+-	return (calc_support != cur_support) ? !safe_to_lower : false;
++	if (cur_support != calc_support) {
++		if (calc_support == true && safe_to_lower)
++			return true;
++		else if (calc_support == false && !safe_to_lower)
++			return true;
++	}
++
++	return false;
+ }
+ 
+ int clk_mgr_helper_get_active_display_cnt(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4059-drm-amd-display-Properly-round-nominal-frequency-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4059-drm-amd-display-Properly-round-nominal-frequency-for.patch
new file mode 100644
index 00000000..c97411d2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4059-drm-amd-display-Properly-round-nominal-frequency-for.patch
@@ -0,0 +1,58 @@
+From 68d784353e0efa0f218da7226fc82d59b721b20d Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Wed, 11 Sep 2019 16:17:08 -0400
+Subject: [PATCH 4059/4256] drm/amd/display: Properly round nominal frequency
+ for SPD
+
+[Why]
+Some displays rely on the SPD verticle frequency maximum value.
+Must round the calculated refresh rate to the nearest integer.
+
+[How]
+Round the nominal calculated refresh rate to the nearest whole
+integer.
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/modules/freesync/freesync.c | 13 ++++++++-----
+ 1 file changed, 8 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+index a978afac8b79..65faaf6802e0 100644
+--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
++++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+@@ -741,6 +741,10 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
+ 	nominal_field_rate_in_uhz =
+ 			mod_freesync_calc_nominal_field_rate(stream);
+ 
++	/* Rounded to the nearest Hz */
++	nominal_field_rate_in_uhz = 1000000ULL *
++			div_u64(nominal_field_rate_in_uhz + 500000, 1000000);
++
+ 	min_refresh_in_uhz = in_config->min_refresh_in_uhz;
+ 	max_refresh_in_uhz = in_config->max_refresh_in_uhz;
+ 
+@@ -996,14 +1000,13 @@ unsigned long long mod_freesync_calc_nominal_field_rate(
+ 			const struct dc_stream_state *stream)
+ {
+ 	unsigned long long nominal_field_rate_in_uhz = 0;
++	unsigned int total = stream->timing.h_total * stream->timing.v_total;
+ 
+-	/* Calculate nominal field rate for stream */
++	/* Calculate nominal field rate for stream, rounded up to nearest integer */
+ 	nominal_field_rate_in_uhz = stream->timing.pix_clk_100hz / 10;
+ 	nominal_field_rate_in_uhz *= 1000ULL * 1000ULL * 1000ULL;
+-	nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz,
+-						stream->timing.h_total);
+-	nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz,
+-						stream->timing.v_total);
++
++	nominal_field_rate_in_uhz =	div_u64(nominal_field_rate_in_uhz, total);
+ 
+ 	return nominal_field_rate_in_uhz;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4060-drm-amd-display-Add-output-bitrate-to-DML-calculatio.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4060-drm-amd-display-Add-output-bitrate-to-DML-calculatio.patch
new file mode 100644
index 00000000..9853e1b2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4060-drm-amd-display-Add-output-bitrate-to-DML-calculatio.patch
@@ -0,0 +1,71 @@
+From 926638ed62a64e7537cc42787796af8861cd4708 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Thu, 12 Sep 2019 17:15:16 -0400
+Subject: [PATCH 4060/4256] drm/amd/display: Add output bitrate to DML
+ calculations
+
+[why]
+Output bitrate was mistakenly left out, causing corruption on some
+DSC low resolution (such as 800x600) modes.
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c     | 5 ++++-
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 2 +-
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c     | 2 ++
+ 3 files changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 2f1dc0277e48..5deb8deece0c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1923,7 +1923,7 @@ int dcn20_populate_dml_pipes_from_context(
+ 			break;
+ 		case PIXEL_ENCODING_YCBCR420:
+ 			pipes[pipe_cnt].dout.output_format = dm_420;
+-			pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3) / 2;
++			pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
+ 			break;
+ 		case PIXEL_ENCODING_YCBCR422:
+ 			if (true) /* todo */
+@@ -1937,6 +1937,9 @@ int dcn20_populate_dml_pipes_from_context(
+ 			pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
+ 		}
+ 
++		if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
++			pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
++
+ 		/* todo: default max for now, until there is logic reflecting this in dc*/
+ 		pipes[pipe_cnt].dout.output_bpc = 12;
+ 		/*
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+index f4c1ef9046bf..83f84cdd4055 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+@@ -269,7 +269,7 @@ struct writeback_st {
+ 
+ struct _vcs_dpi_display_output_params_st {
+ 	int dp_lanes;
+-	int output_bpp;
++	double output_bpp;
+ 	int dsc_enable;
+ 	int wb_enable;
+ 	int num_active_wb;
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+index 65cf4edddaff..362dc6ea98ae 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+@@ -434,6 +434,8 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
+ 				dst->odm_combine;
+ 		mode_lib->vba.OutputFormat[mode_lib->vba.NumberOfActivePlanes] =
+ 				(enum output_format_class) (dout->output_format);
++		mode_lib->vba.OutputBpp[mode_lib->vba.NumberOfActivePlanes] =
++				dout->output_bpp;
+ 		mode_lib->vba.Output[mode_lib->vba.NumberOfActivePlanes] =
+ 				(enum output_encoder_class) (dout->output_type);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4061-drm-amd-display-add-config-check-for-DSC-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4061-drm-amd-display-add-config-check-for-DSC-support.patch
new file mode 100644
index 00000000..c4f89b24
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4061-drm-amd-display-add-config-check-for-DSC-support.patch
@@ -0,0 +1,36 @@
+From a3099488f793f73d655b43554298f185b269d960 Mon Sep 17 00:00:00 2001
+From: Rui Teng <rui.teng@amd.com>
+Date: Fri, 11 Oct 2019 17:53:16 +0800
+Subject: [PATCH 4061/4256] drm/amd/display: add config check for DSC support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fix dkms install issue:
+‘struct dc_crtc_timing_flags’ has no member named ‘DSC’
+‘struct dc_crtc_timing’ has no member named ‘dsc_cfg’
+
+Signed-off-by: Rui Teng <rui.teng@amd.com>
+Reviewed-by: changzhu <Changfeng.Zhu@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 5deb8deece0c..4ca819c223bd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1937,8 +1937,10 @@ int dcn20_populate_dml_pipes_from_context(
+ 			pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
+ 		}
+ 
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 		if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
+ 			pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
++#endif
+ 
+ 		/* todo: default max for now, until there is logic reflecting this in dc*/
+ 		pipes[pipe_cnt].dout.output_bpc = 12;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4062-drm-amd-display-wait-for-set-pipe-mcp-command-comple.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4062-drm-amd-display-wait-for-set-pipe-mcp-command-comple.patch
new file mode 100644
index 00000000..e1e7a24d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4062-drm-amd-display-wait-for-set-pipe-mcp-command-comple.patch
@@ -0,0 +1,40 @@
+From 707206a946b412b24b42c67588a02a76e25cd6a1 Mon Sep 17 00:00:00 2001
+From: Josip Pavic <Josip.Pavic@amd.com>
+Date: Thu, 12 Sep 2019 15:40:08 -0400
+Subject: [PATCH 4062/4256] drm/amd/display: wait for set pipe mcp command
+ completion
+
+[Why]
+When the driver sends a pipe set command to the DMCU FW, it does not wait
+for the command to complete. This can lead to unpredictable behavior if,
+for example, the driver were to request a pipe disable to the FW via MCP,
+then power down some hardware before the firmware has completed processing
+the command.
+
+[How]
+Wait for the DMCU FW to finish processing set pipe commands
+
+Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+index b5c97b313c54..4a22b50bd38a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+@@ -75,6 +75,9 @@ static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id)
+ 	/* notifyDMCUMsg */
+ 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
+ 
++	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
++			1, 80000);
++
+ 	return true;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4063-drm-amd-display-fix-bug-with-check-for-HPD-Low-in-ve.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4063-drm-amd-display-fix-bug-with-check-for-HPD-Low-in-ve.patch
new file mode 100644
index 00000000..fff28cb7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4063-drm-amd-display-fix-bug-with-check-for-HPD-Low-in-ve.patch
@@ -0,0 +1,46 @@
+From fc1656e0f154dced4cb23749c4b2cb0e17a061b9 Mon Sep 17 00:00:00 2001
+From: Sivapiriyan Kumarasamy <sivapiriyan.kumarasamy@amd.com>
+Date: Thu, 12 Sep 2019 15:55:44 -0400
+Subject: [PATCH 4063/4256] drm/amd/display: fix bug with check for HPD Low in
+ verify link cap
+
+[Why]
+There is a bug when determining if link training should be retried when
+HPD is low in dp_verify_link_cap_with_retries.
+
+[How]
+Correctly, fail dp_verify_link_cap_with_retries without retry when
+HPD is low.
+
+Signed-off-by: Sivapiriyan Kumarasamy <sivapiriyan.kumarasamy@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 701b73926616..5a0c3384c16b 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -1656,11 +1656,14 @@ bool dp_verify_link_cap_with_retries(
+ 
+ 	for (i = 0; i < attempts; i++) {
+ 		int fail_count = 0;
+-		enum dc_connection_type type;
++		enum dc_connection_type type = dc_connection_none;
+ 
+ 		memset(&link->verified_link_cap, 0,
+ 				sizeof(struct dc_link_settings));
+-		if (!dc_link_detect_sink(link, &type)) {
++		if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
++			link->verified_link_cap.lane_count = LANE_COUNT_ONE;
++			link->verified_link_cap.link_rate = LINK_RATE_LOW;
++			link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
+ 			break;
+ 		} else if (dp_verify_link_cap(link,
+ 				&link->reported_link_cap,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4064-drm-amd-display-Use-dcn1-Optimal-Taps-Get.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4064-drm-amd-display-Use-dcn1-Optimal-Taps-Get.patch
new file mode 100644
index 00000000..53cf9e01
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4064-drm-amd-display-Use-dcn1-Optimal-Taps-Get.patch
@@ -0,0 +1,89 @@
+From 14e1a4613443a646b1bce8e87879b328e487039d Mon Sep 17 00:00:00 2001
+From: Wesley Chalmers <Wesley.Chalmers@amd.com>
+Date: Fri, 13 Sep 2019 13:43:36 -0400
+Subject: [PATCH 4064/4256] drm/amd/display: Use dcn1 Optimal Taps Get
+
+[WHY]
+dpp2_get_optimal_number_of_taps is incorrect, and dcn2 should be using
+dpp1_get_optimal_number_of_taps instead
+
+Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 4 ++--
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 5 +++++
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h | 5 -----
+ 4 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+index d8b2da18db39..997e9582edc7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+@@ -129,7 +129,7 @@ void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
+ 
+ #define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19))
+ 
+-static bool dpp_get_optimal_number_of_taps(
++bool dpp1_get_optimal_number_of_taps(
+ 		struct dpp *dpp,
+ 		struct scaler_data *scl_data,
+ 		const struct scaling_taps *in_taps)
+@@ -521,7 +521,7 @@ static const struct dpp_funcs dcn10_dpp_funcs = {
+ 		.dpp_read_state = dpp_read_state,
+ 		.dpp_reset = dpp_reset,
+ 		.dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
+-		.dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps,
++		.dpp_get_optimal_number_of_taps = dpp1_get_optimal_number_of_taps,
+ 		.dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,
+ 		.dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,
+ 		.dpp_set_csc_default = dpp1_cm_set_output_csc_default,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+index e2c613611ac9..1d4a7d640334 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+@@ -1504,6 +1504,11 @@ void dpp1_set_hdr_multiplier(
+ 		struct dpp *dpp_base,
+ 		uint32_t multiplier);
+ 
++bool dpp1_get_optimal_number_of_taps(
++		struct dpp *dpp,
++		struct scaler_data *scl_data,
++		const struct scaling_taps *in_taps);
++
+ void dpp1_construct(struct dcn10_dpp *dpp1,
+ 	struct dc_context *ctx,
+ 	uint32_t inst,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+index ae8534308229..4d7e45892f08 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+@@ -457,7 +457,7 @@ static struct dpp_funcs dcn20_dpp_funcs = {
+ 	.dpp_read_state = dpp20_read_state,
+ 	.dpp_reset = dpp_reset,
+ 	.dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
+-	.dpp_get_optimal_number_of_taps = dpp2_get_optimal_number_of_taps,
++	.dpp_get_optimal_number_of_taps = dpp1_get_optimal_number_of_taps,
+ 	.dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,
+ 	.dpp_set_csc_adjustment = NULL,
+ 	.dpp_set_csc_default = NULL,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
+index f8db8ad593f8..5b03b737b1d6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
+@@ -705,11 +705,6 @@ void dpp2_set_hdr_multiplier(
+ 		struct dpp *dpp_base,
+ 		uint32_t multiplier);
+ 
+-bool dpp2_get_optimal_number_of_taps(
+-		struct dpp *dpp,
+-		struct scaler_data *scl_data,
+-		const struct scaling_taps *in_taps);
+-
+ bool dpp2_construct(struct dcn20_dpp *dpp2,
+ 	struct dc_context *ctx,
+ 	uint32_t inst,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4065-drm-amd-display-3.2.53.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4065-drm-amd-display-3.2.53.patch
new file mode 100644
index 00000000..894ac62c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4065-drm-amd-display-3.2.53.patch
@@ -0,0 +1,28 @@
+From 2100aec0b929563f150474473b8ef10666a899c4 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Sat, 14 Sep 2019 11:19:18 -0400
+Subject: [PATCH 4065/4256] drm/amd/display: 3.2.53
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 3dfc5704bb59..6c50d5c24658 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.52"
++#define DC_VER "3.2.53"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4066-drm-amd-display-Program-DWB-watermarks-from-correct-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4066-drm-amd-display-Program-DWB-watermarks-from-correct-.patch
new file mode 100644
index 00000000..9df5aee1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4066-drm-amd-display-Program-DWB-watermarks-from-correct-.patch
@@ -0,0 +1,88 @@
+From 8c06029a1c75c844a6365be605a5979bc794b9a4 Mon Sep 17 00:00:00 2001
+From: Julian Parkin <julian.parkin@amd.com>
+Date: Thu, 29 Aug 2019 17:06:05 -0400
+Subject: [PATCH 4066/4256] drm/amd/display: Program DWB watermarks from
+ correct state
+
+[Why]
+When diags adds a DWB via a stream update, we calculate MMHUBBUB
+paramaters, but dc->current_state has not yet been updated
+when the DWB programming happens. This leads to overflow on
+high bandwidth tests since the incorrect MMHUBBUB arbitration
+parameters are programmed.
+
+[How]
+Pass the updated context down to the (enable|update)_writeback functions
+so that they can use the correct watermarks when programming MMHUBBUB.
+
+Signed-off-by: Julian Parkin <julian.parkin@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_stream.c    | 4 ++--
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 5 +++--
+ drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  | 6 ++++--
+ 3 files changed, 9 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+index 41032c4c5bdf..4431cc6000a1 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+@@ -420,10 +420,10 @@ bool dc_stream_add_writeback(struct dc *dc,
+ 
+ 		if (dwb->funcs->is_enabled(dwb)) {
+ 			/* writeback pipe already enabled, only need to update */
+-			dc->hwss.update_writeback(dc, stream_status, wb_info);
++			dc->hwss.update_writeback(dc, stream_status, wb_info, dc->current_state);
+ 		} else {
+ 			/* Enable writeback pipe from scratch*/
+-			dc->hwss.enable_writeback(dc, stream_status, wb_info);
++			dc->hwss.enable_writeback(dc, stream_status, wb_info, dc->current_state);
+ 		}
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 4a0038293569..2dce3e4b5e51 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1626,7 +1626,8 @@ bool dcn20_update_bandwidth(
+ static void dcn20_enable_writeback(
+ 		struct dc *dc,
+ 		const struct dc_stream_status *stream_status,
+-		struct dc_writeback_info *wb_info)
++		struct dc_writeback_info *wb_info,
++		struct dc_state *context)
+ {
+ 	struct dwbc *dwb;
+ 	struct mcif_wb *mcif_wb;
+@@ -1643,7 +1644,7 @@ static void dcn20_enable_writeback(
+ 	optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
+ 	/* set MCIF_WB buffer and arbitration configuration */
+ 	mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
+-	mcif_wb->funcs->config_mcif_arb(mcif_wb, &dc->current_state->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
++	mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
+ 	/* Enable MCIF_WB */
+ 	mcif_wb->funcs->enable_mcif(mcif_wb);
+ 	/* Enable DWB */
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index de9d0a312180..e775d7aa062f 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -331,10 +331,12 @@ struct hw_sequencer_funcs {
+ 			struct dc_state *context);
+ 	void (*update_writeback)(struct dc *dc,
+ 			const struct dc_stream_status *stream_status,
+-			struct dc_writeback_info *wb_info);
++			struct dc_writeback_info *wb_info,
++			struct dc_state *context);
+ 	void (*enable_writeback)(struct dc *dc,
+ 			const struct dc_stream_status *stream_status,
+-			struct dc_writeback_info *wb_info);
++			struct dc_writeback_info *wb_info,
++			struct dc_state *context);
+ 	void (*disable_writeback)(struct dc *dc,
+ 			unsigned int dwb_pipe_inst);
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4067-drm-amd-display-exit-PSR-during-detection.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4067-drm-amd-display-exit-PSR-during-detection.patch
new file mode 100644
index 00000000..0b324df7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4067-drm-amd-display-exit-PSR-during-detection.patch
@@ -0,0 +1,241 @@
+From ecd1557780d79f8262341d69e36cdc819fa5904f Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Fri, 6 Sep 2019 18:26:23 -0400
+Subject: [PATCH 4067/4256] drm/amd/display: exit PSR during detection
+
+[Why]
+If 48mhz refclk is turned off during PSR, we will have issue doing
+link training during detection.
+
+[How]
+Get out of PSR before detection
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  | 25 +++++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 19 ++++++++------
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  8 +++---
+ drivers/gpu/drm/amd/display/dc/dc_link.h      | 17 +++++++++++--
+ .../display/dc/dce110/dce110_hw_sequencer.c   | 16 ++----------
+ .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   |  5 ++++
+ 6 files changed, 62 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+index 8da1256bc144..8af8fab14bcb 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+@@ -63,6 +63,31 @@ int clk_mgr_helper_get_active_display_cnt(
+ 	return display_count;
+ }
+ 
++void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
++{
++	struct dc_link *edp_link = get_edp_link(dc);
++
++	if (dc->hwss.exit_optimized_pwr_state)
++		dc->hwss.exit_optimized_pwr_state(dc, dc->current_state);
++
++	if (edp_link) {
++		clk_mgr->psr_allow_active_cache = edp_link->psr_allow_active;
++		dc_link_set_psr_allow_active(edp_link, false, false);
++	}
++
++}
++
++void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
++{
++	struct dc_link *edp_link = get_edp_link(dc);
++
++	if (edp_link)
++		dc_link_set_psr_allow_active(edp_link, clk_mgr->psr_allow_active_cache, false);
++
++	if (dc->hwss.optimize_pwr_state)
++		dc->hwss.optimize_pwr_state(dc, dc->current_state);
++
++}
+ 
+ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)
+ {
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index f352f6028293..6fdb78a152e0 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -1072,15 +1072,14 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
+ {
+ 	const struct dc *dc = link->dc;
+ 	bool ret;
+-	/* get out of low power state */
+ 
+-	if (dc->hwss.exit_optimized_pwr_state)
+-		dc->hwss.exit_optimized_pwr_state(dc, dc->current_state);
++	/* get out of low power state */
++	clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
+ 
+ 	ret = dc_link_detect_helper(link, reason);
+ 
+-	if (dc->hwss.optimize_pwr_state)
+-		dc->hwss.optimize_pwr_state(dc, dc->current_state);
++	/* Go back to power optimized state */
++	clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
+ 
+ 	return ret;
+ }
+@@ -2419,13 +2418,17 @@ bool dc_link_set_abm_disable(const struct dc_link *link)
+ 	return true;
+ }
+ 
+-bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)
++bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool wait)
+ {
+ 	struct dc  *core_dc = link->ctx->dc;
+ 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
+ 
+-	if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_enabled)
+-		dmcu->funcs->set_psr_enable(dmcu, enable, wait);
++
++
++	if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_feature_enabled)
++		dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
++
++	link->psr_allow_active = allow_active;
+ 
+ 	return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 5a0c3384c16b..649ed31ccfe5 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2076,11 +2076,11 @@ static bool allow_hpd_rx_irq(const struct dc_link *link)
+ 	return false;
+ }
+ 
+-static bool handle_hpd_irq_psr_sink(const struct dc_link *link)
++static bool handle_hpd_irq_psr_sink(struct dc_link *link)
+ {
+ 	union dpcd_psr_configuration psr_configuration;
+ 
+-	if (!link->psr_enabled)
++	if (!link->psr_feature_enabled)
+ 		return false;
+ 
+ 	dm_helpers_dp_read_dpcd(
+@@ -2119,8 +2119,8 @@ static bool handle_hpd_irq_psr_sink(const struct dc_link *link)
+ 				sizeof(psr_error_status.raw));
+ 
+ 			/* PSR error, disable and re-enable PSR */
+-			dc_link_set_psr_enable(link, false, true);
+-			dc_link_set_psr_enable(link, true, true);
++			dc_link_set_psr_allow_active(link, false, true);
++			dc_link_set_psr_allow_active(link, true, true);
+ 
+ 			return true;
+ 		} else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
+index 45e6195c5395..f24fd19ed93d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
+@@ -126,7 +126,8 @@ struct dc_link {
+ 	unsigned short chip_caps;
+ 	unsigned int dpcd_sink_count;
+ 	enum edp_revision edp_revision;
+-	bool psr_enabled;
++	bool psr_feature_enabled;
++	bool psr_allow_active;
+ 
+ 	/* MST record stream using this link */
+ 	struct link_flags {
+@@ -158,6 +159,18 @@ static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_
+ 	return dc->links[link_index];
+ }
+ 
++static inline struct dc_link *get_edp_link(const struct dc *dc)
++{
++	int i;
++
++	// report any eDP links, even unconnected DDI's
++	for (i = 0; i < dc->link_count; i++) {
++		if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP)
++			return dc->links[i];
++	}
++	return NULL;
++}
++
+ /* Set backlight level of an embedded panel (eDP, LVDS).
+  * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer
+  * and 16 bit fractional, where 1.0 is max backlight value.
+@@ -170,7 +183,7 @@ int dc_link_get_backlight_level(const struct dc_link *dc_link);
+ 
+ bool dc_link_set_abm_disable(const struct dc_link *dc_link);
+ 
+-bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable, bool wait);
++bool dc_link_set_psr_allow_active(struct dc_link *dc_link, bool enable, bool wait);
+ 
+ bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index e11509506376..27542c22fa55 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -1407,7 +1407,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ 
+ 	pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
+ 
+-	pipe_ctx->stream->link->psr_enabled = false;
++	pipe_ctx->stream->link->psr_feature_enabled = false;
+ 
+ 	return DC_OK;
+ }
+@@ -1518,18 +1518,6 @@ static struct dc_stream_state *get_edp_stream(struct dc_state *context)
+ 	return NULL;
+ }
+ 
+-static struct dc_link *get_edp_link(struct dc *dc)
+-{
+-	int i;
+-
+-	// report any eDP links, even unconnected DDI's
+-	for (i = 0; i < dc->link_count; i++) {
+-		if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP)
+-			return dc->links[i];
+-	}
+-	return NULL;
+-}
+-
+ static struct dc_link *get_edp_link_with_sink(
+ 		struct dc *dc,
+ 		struct dc_state *context)
+@@ -1823,7 +1811,7 @@ static bool should_enable_fbc(struct dc *dc,
+ 		return false;
+ 
+ 	/* PSR should not be enabled */
+-	if (pipe_ctx->stream->link->psr_enabled)
++	if (pipe_ctx->stream->link->psr_feature_enabled)
+ 		return false;
+ 
+ 	/* Nothing to compress */
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+index 2fdd0ba93beb..f0f3d42a0b6f 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+@@ -189,6 +189,7 @@ struct clk_mgr {
+ 	struct dc_context *ctx;
+ 	struct clk_mgr_funcs *funcs;
+ 	struct dc_clocks clks;
++	bool psr_allow_active_cache;
+ 	int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_1
+ 	struct clk_bw_params *bw_params;
+@@ -202,4 +203,8 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
+ 
+ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr);
+ 
++void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);
++
++void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);
++
+ #endif /* __DAL_CLK_MGR_H__ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4068-drm-amd-display-fix-code-to-control-48mhz-refclk.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4068-drm-amd-display-fix-code-to-control-48mhz-refclk.patch
new file mode 100644
index 00000000..27a53f0f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4068-drm-amd-display-fix-code-to-control-48mhz-refclk.patch
@@ -0,0 +1,87 @@
+From 70252b3921032d75c238d0c0344c847daaca5dfa Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Thu, 18 Jul 2019 13:56:59 -0400
+Subject: [PATCH 4068/4256] drm/amd/display: fix code to control 48mhz refclk
+
+[Why]
+The SMU message to enable this feature looks at argument. Previous code
+didn't send right argument. This change will allow the feature to be
+be enabled.
+
+[How]
+Fixed one issue where SMU message to enable the feature was sent without
+setting the parameter.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c  | 7 ++++---
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c    | 4 ++--
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h    | 2 +-
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c      | 2 +-
+ 4 files changed, 8 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index c0e58434be39..a2a4c7ddc856 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -649,8 +649,9 @@ void rn_clk_mgr_construct(
+ 			pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges);
+ 	}
+ 
+-	/* enable powerfeatures when displaycount goes to 0 */
+-	if (!debug->disable_48mhz_pwrdwn)
+-		rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr);
++	if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
++		/* enable powerfeatures when displaycount goes to 0 */
++		rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
++	}
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+index fd919b82e902..8e860f567d5c 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+@@ -190,12 +190,12 @@ void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum
+ 		disp_count);
+ }
+ 
+-void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr)
++void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
+ {
+ 	rn_vbios_smu_send_msg_with_param(
+ 			clk_mgr,
+ 			VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown,
+-			0);
++			enable);
+ }
+ 
+ void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h
+index fe2986a2c7a2..ccc01879c9d4 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h
+@@ -34,7 +34,7 @@ int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int
+ void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
+ int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
+ void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, int display_count);
+-void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr);
++void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
+ void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
+ 
+ #endif /* DAL_DC_DCN10_RV1_CLK_MGR_VBIOS_SMU_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 5a6e55b7d536..15914bf70008 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -804,7 +804,7 @@ static const struct dc_debug_options debug_defaults_drv = {
+ 		.disable_pplib_wm_range = false,
+ 		.scl_reset_length10 = true,
+ 		.sanity_checks = true,
+-		.disable_48mhz_pwrdwn = true,
++		.disable_48mhz_pwrdwn = false,
+ };
+ 
+ static const struct dc_debug_options debug_defaults_diags = {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4069-drm-amd-display-add-guard-for-SMU-ver-for-48mhz-clk.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4069-drm-amd-display-add-guard-for-SMU-ver-for-48mhz-clk.patch
new file mode 100644
index 00000000..c1db7add
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4069-drm-amd-display-add-guard-for-SMU-ver-for-48mhz-clk.patch
@@ -0,0 +1,35 @@
+From 0bfcf6a853a83e4b3fb53a14dae62d7a73f83cf8 Mon Sep 17 00:00:00 2001
+From: Joseph Gravenor <joseph.gravenor@amd.com>
+Date: Mon, 16 Sep 2019 15:13:33 -0400
+Subject: [PATCH 4069/4256] drm/amd/display: add guard for SMU ver, for 48mhz
+ clk
+
+[why]
+dp_48m_refclk_driver_pwdn is persistent through S3 and S5.
+This was worked arround in SMU FW 55.21.0. Earlier FW don't have this fix
+so we will hang on reboot
+
+[how]
+add a guard for smu versions before SMU FW 55.21.0
+
+Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index a2a4c7ddc856..68d38239304c 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -649,7 +649,7 @@ void rn_clk_mgr_construct(
+ 			pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges);
+ 	}
+ 
+-	if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
++	if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) {
+ 		/* enable powerfeatures when displaycount goes to 0 */
+ 		rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4070-drm-amd-display-Update-number-of-dcn21-audio-endpoin.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4070-drm-amd-display-Update-number-of-dcn21-audio-endpoin.patch
new file mode 100644
index 00000000..759f7fda
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4070-drm-amd-display-Update-number-of-dcn21-audio-endpoin.patch
@@ -0,0 +1,35 @@
+From 6d6d2badc25d3e44f0cf3fa214a961f2baea0389 Mon Sep 17 00:00:00 2001
+From: Michael Strauss <michael.strauss@amd.com>
+Date: Tue, 17 Sep 2019 09:02:01 -0400
+Subject: [PATCH 4070/4256] drm/amd/display: Update number of dcn21 audio
+ endpoints
+
+[WHY]
+Number of audio endpoints wasn't updated from dcn20's 6 when created
+
+[HOW]
+Changed num_audio to 4 to match the correct sbios value
+
+Signed-off-by: Michael Strauss <michael.strauss@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 15914bf70008..0aa8e8e025e6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -726,7 +726,7 @@ static const struct resource_caps res_cap_rn = {
+ 		.num_timing_generator = 4,
+ 		.num_opp = 4,
+ 		.num_video_plane = 4,
+-		.num_audio = 6, // 6 audio endpoints.  4 audio streams
++		.num_audio = 4, // 4 audio endpoints.  4 audio streams
+ 		.num_stream_encoder = 5,
+ 		.num_pll = 5,  // maybe 3 because the last two used for USB-c
+ 		.num_dwb = 1,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4071-drm-amd-display-add-new-active-dongle-to-existent-w-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4071-drm-amd-display-add-new-active-dongle-to-existent-w-.patch
new file mode 100644
index 00000000..e057b890
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4071-drm-amd-display-add-new-active-dongle-to-existent-w-.patch
@@ -0,0 +1,49 @@
+From 32b9217a255f210acae66b763e88c6436336c588 Mon Sep 17 00:00:00 2001
+From: Vitaly Prosyak <vitaly.prosyak@amd.com>
+Date: Mon, 16 Sep 2019 17:04:33 -0500
+Subject: [PATCH 4071/4256] drm/amd/display: add new active dongle to existent
+ w/a
+
+[Why & How]
+Dongle 0x00E04C power down all internal circuits including
+AUX communication preventing reading DPCD table.
+Encoder will skip DP RX power down on disable output
+to keep receiver powered all the time.
+
+Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Acked-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c        | 1 +
+ drivers/gpu/drm/amd/display/include/ddc_service_types.h | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 649ed31ccfe5..aae204141c60 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2721,6 +2721,7 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
+ 		 * keep receiver powered all the time.*/
+ 		case DP_BRANCH_DEVICE_ID_0010FA:
+ 		case DP_BRANCH_DEVICE_ID_0080E1:
++		case DP_BRANCH_DEVICE_ID_00E04C:
+ 			link->wa_flags.dp_keep_receiver_powered = true;
+ 			break;
+ 
+diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+index 18961707db23..9ad49da50a17 100644
+--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
++++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+@@ -31,6 +31,8 @@
+ #define DP_BRANCH_DEVICE_ID_0022B9 0x0022B9
+ #define DP_BRANCH_DEVICE_ID_00001A 0x00001A
+ #define DP_BRANCH_DEVICE_ID_0080E1 0x0080e1
++#define DP_BRANCH_DEVICE_ID_90CC24 0x90CC24
++#define DP_BRANCH_DEVICE_ID_00E04C 0x00E04C
+ 
+ enum ddc_result {
+ 	DDC_RESULT_UNKNOWN = 0,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4072-drm-amd-display-add-more-checks-to-validate-seamless.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4072-drm-amd-display-add-more-checks-to-validate-seamless.patch
new file mode 100644
index 00000000..07321739
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4072-drm-amd-display-add-more-checks-to-validate-seamless.patch
@@ -0,0 +1,387 @@
+From a3434a791c3fc3a0935356e45f4b38f880d36f12 Mon Sep 17 00:00:00 2001
+From: Martin Leung <martin.leung@amd.com>
+Date: Tue, 17 Sep 2019 14:50:22 -0400
+Subject: [PATCH 4072/4256] drm/amd/display: add more checks to validate
+ seamless boot timing
+
+[why]
+we found using an active DP to HDMI panel that we weren't validating
+dp_pixel_format and hardware timing v_front_porch, causing screen to
+blank and/or corrupt while attempting a seamless boot.
+
+[how]
+added checks during dc_validate_seamless_boot_timing for these values
+
+Signed-off-by: Martin Leung <martin.leung@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c      | 61 +++++++++++++++++-
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 60 ++++--------------
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |  5 +-
+ .../display/dc/dcn10/dcn10_stream_encoder.c   | 62 +++++++++++++++++++
+ .../display/dc/dcn10/dcn10_stream_encoder.h   |  5 ++
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c |  2 +-
+ .../display/dc/dcn20/dcn20_stream_encoder.c   |  4 ++
+ .../amd/display/dc/inc/hw/stream_encoder.h    |  5 ++
+ .../amd/display/dc/inc/hw/timing_generator.h  |  2 +
+ 9 files changed, 153 insertions(+), 53 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 85be4db9dcbf..f89766a5cc72 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1001,6 +1001,10 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
+ 				struct dc_crtc_timing *crtc_timing)
+ {
+ 	struct timing_generator *tg;
++	struct stream_encoder *se;
++
++	struct dc_crtc_timing hw_crtc_timing = {0};
++
+ 	struct dc_link *link = sink->link;
+ 	unsigned int i, enc_inst, tg_inst = 0;
+ 
+@@ -1020,6 +1024,9 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
+ 
+ 	for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
+ 		if (dc->res_pool->stream_enc[i]->id == enc_inst) {
++
++			se = dc->res_pool->stream_enc[i];
++
+ 			tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
+ 				dc->res_pool->stream_enc[i]);
+ 			break;
+@@ -1035,10 +1042,46 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
+ 
+ 	tg = dc->res_pool->timing_generators[tg_inst];
+ 
+-	if (!tg->funcs->is_matching_timing)
++	if (!tg->funcs->get_hw_timing)
++		return false;
++
++	if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
++		return false;
++
++	if (crtc_timing->h_total != hw_crtc_timing.h_total)
++		return false;
++
++	if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
++		return false;
++
++	if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
++		return false;
++
++	if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
++		return false;
++
++	if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
++		return false;
++
++	if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
+ 		return false;
+ 
+-	if (!tg->funcs->is_matching_timing(tg, crtc_timing))
++	if (crtc_timing->v_total != hw_crtc_timing.v_total)
++		return false;
++
++	if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
++		return false;
++
++	if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
++		return false;
++
++	if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
++		return false;
++
++	if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
++		return false;
++
++	if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
+ 		return false;
+ 
+ 	if (dc_is_dp_signal(link->connector_signal)) {
+@@ -1051,6 +1094,20 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
+ 		if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
+ 			return false;
+ 
++		if (!se->funcs->dp_get_pixel_format)
++			return false;
++
++		if (!se->funcs->dp_get_pixel_format(
++			se,
++			&hw_crtc_timing.pixel_encoding,
++			&hw_crtc_timing.display_color_depth))
++			return false;
++
++		if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
++			return false;
++
++		if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
++			return false;
+ 	}
+ 
+ 	return true;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+index f3cade20e45c..8710f3ac2abf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+@@ -1238,59 +1238,25 @@ bool optc1_is_stereo_left_eye(struct timing_generator *optc)
+ 	return ret;
+ }
+ 
+-bool optc1_is_matching_timing(struct timing_generator *tg,
+-		const struct dc_crtc_timing *otg_timing)
++bool optc1_get_hw_timing(struct timing_generator *tg,
++		struct dc_crtc_timing *hw_crtc_timing)
+ {
+-	struct dc_crtc_timing hw_crtc_timing = {0};
+ 	struct dcn_otg_state s = {0};
+ 
+-	if (tg == NULL || otg_timing == NULL)
++	if (tg == NULL || hw_crtc_timing == NULL)
+ 		return false;
+ 
+ 	optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
+ 
+-	hw_crtc_timing.h_total = s.h_total + 1;
+-	hw_crtc_timing.h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end);
+-	hw_crtc_timing.h_front_porch = s.h_total + 1 - s.h_blank_start;
+-	hw_crtc_timing.h_sync_width = s.h_sync_a_end - s.h_sync_a_start;
++	hw_crtc_timing->h_total = s.h_total + 1;
++	hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end);
++	hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start;
++	hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start;
+ 
+-	hw_crtc_timing.v_total = s.v_total + 1;
+-	hw_crtc_timing.v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end);
+-	hw_crtc_timing.v_front_porch = s.v_total + 1 - s.v_blank_start;
+-	hw_crtc_timing.v_sync_width = s.v_sync_a_end - s.v_sync_a_start;
+-
+-	if (otg_timing->h_total != hw_crtc_timing.h_total)
+-		return false;
+-
+-	if (otg_timing->h_border_left != hw_crtc_timing.h_border_left)
+-		return false;
+-
+-	if (otg_timing->h_addressable != hw_crtc_timing.h_addressable)
+-		return false;
+-
+-	if (otg_timing->h_border_right != hw_crtc_timing.h_border_right)
+-		return false;
+-
+-	if (otg_timing->h_front_porch != hw_crtc_timing.h_front_porch)
+-		return false;
+-
+-	if (otg_timing->h_sync_width != hw_crtc_timing.h_sync_width)
+-		return false;
+-
+-	if (otg_timing->v_total != hw_crtc_timing.v_total)
+-		return false;
+-
+-	if (otg_timing->v_border_top != hw_crtc_timing.v_border_top)
+-		return false;
+-
+-	if (otg_timing->v_addressable != hw_crtc_timing.v_addressable)
+-		return false;
+-
+-	if (otg_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
+-		return false;
+-
+-	if (otg_timing->v_sync_width != hw_crtc_timing.v_sync_width)
+-		return false;
++	hw_crtc_timing->v_total = s.v_total + 1;
++	hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end);
++	hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start;
++	hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start;
+ 
+ 	return true;
+ }
+@@ -1494,7 +1460,6 @@ static const struct timing_generator_funcs dcn10_tg_funcs = {
+ 		.get_frame_count = optc1_get_vblank_counter,
+ 		.get_scanoutpos = optc1_get_crtc_scanoutpos,
+ 		.get_otg_active_size = optc1_get_otg_active_size,
+-		.is_matching_timing = optc1_is_matching_timing,
+ 		.set_early_control = optc1_set_early_control,
+ 		/* used by enable_timing_synchronization. Not need for FPGA */
+ 		.wait_for_state = optc1_wait_for_state,
+@@ -1522,7 +1487,8 @@ static const struct timing_generator_funcs dcn10_tg_funcs = {
+ 		.configure_crc = optc1_configure_crc,
+ 		.set_vtg_params = optc1_set_vtg_params,
+ 		.program_manual_trigger = optc1_program_manual_trigger,
+-		.setup_manual_trigger = optc1_setup_manual_trigger
++		.setup_manual_trigger = optc1_setup_manual_trigger,
++		.get_hw_timing = optc1_get_hw_timing,
+ };
+ 
+ void dcn10_timing_generator_init(struct optc *optc1)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+index 83575599672e..c8d795b335ba 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+@@ -547,9 +547,8 @@ struct dcn_otg_state {
+ void optc1_read_otg_state(struct optc *optc1,
+ 		struct dcn_otg_state *s);
+ 
+-bool optc1_is_matching_timing(
+-	struct timing_generator *tg,
+-	const struct dc_crtc_timing *otg_timing);
++bool optc1_get_hw_timing(struct timing_generator *tg,
++		struct dc_crtc_timing *hw_crtc_timing);
+ 
+ bool optc1_validate_timing(
+ 	struct timing_generator *optc,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+index 6800b906a86e..f10c1554ec01 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+@@ -1552,6 +1552,66 @@ unsigned int enc1_dig_source_otg(
+ 	return tg_inst;
+ }
+ 
++bool enc1_stream_encoder_dp_get_pixel_format(
++	struct stream_encoder *enc,
++	enum dc_pixel_encoding *encoding,
++	enum dc_color_depth *depth)
++{
++	uint32_t hw_encoding = 0;
++	uint32_t hw_depth = 0;
++	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
++
++	if (enc == NULL ||
++		encoding == NULL ||
++		depth == NULL)
++		return false;
++
++	REG_GET_2(DP_PIXEL_FORMAT,
++		DP_PIXEL_ENCODING, &hw_encoding,
++		DP_COMPONENT_DEPTH, &hw_depth);
++
++	switch (hw_depth) {
++	case DP_COMPONENT_PIXEL_DEPTH_6BPC:
++		*depth = COLOR_DEPTH_666;
++		break;
++	case DP_COMPONENT_PIXEL_DEPTH_8BPC:
++		*depth = COLOR_DEPTH_888;
++		break;
++	case DP_COMPONENT_PIXEL_DEPTH_10BPC:
++		*depth = COLOR_DEPTH_101010;
++		break;
++	case DP_COMPONENT_PIXEL_DEPTH_12BPC:
++		*depth = COLOR_DEPTH_121212;
++		break;
++	case DP_COMPONENT_PIXEL_DEPTH_16BPC:
++		*depth = COLOR_DEPTH_161616;
++		break;
++	default:
++		*depth = COLOR_DEPTH_UNDEFINED;
++		break;
++	}
++
++	switch (hw_encoding) {
++	case DP_PIXEL_ENCODING_TYPE_RGB444:
++		*encoding = PIXEL_ENCODING_RGB;
++		break;
++	case DP_PIXEL_ENCODING_TYPE_YCBCR422:
++		*encoding = PIXEL_ENCODING_YCBCR422;
++		break;
++	case DP_PIXEL_ENCODING_TYPE_YCBCR444:
++	case DP_PIXEL_ENCODING_TYPE_Y_ONLY:
++		*encoding = PIXEL_ENCODING_YCBCR444;
++		break;
++	case DP_PIXEL_ENCODING_TYPE_YCBCR420:
++		*encoding = PIXEL_ENCODING_YCBCR420;
++		break;
++	default:
++		*encoding = PIXEL_ENCODING_UNDEFINED;
++		break;
++	}
++	return true;
++}
++
+ static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
+ 	.dp_set_stream_attribute =
+ 		enc1_stream_encoder_dp_set_stream_attribute,
+@@ -1588,6 +1648,8 @@ static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
+ 	.dig_connect_to_otg  = enc1_dig_connect_to_otg,
+ 	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
+ 	.dig_source_otg = enc1_dig_source_otg,
++
++	.dp_get_pixel_format  = enc1_stream_encoder_dp_get_pixel_format,
+ };
+ 
+ void dcn10_stream_encoder_construct(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+index a512cbea00d1..c9cbc21d121e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+@@ -621,4 +621,9 @@ void get_audio_clock_info(
+ void enc1_reset_hdmi_stream_attribute(
+ 	struct stream_encoder *enc);
+ 
++bool enc1_stream_encoder_dp_get_pixel_format(
++	struct stream_encoder *enc,
++	enum dc_pixel_encoding *encoding,
++	enum dc_color_depth *depth);
++
+ #endif /* __DC_STREAM_ENCODER_DCN10_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+index dda90995ba93..3b613fb93ef8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+@@ -460,7 +460,7 @@ static struct timing_generator_funcs dcn20_tg_funcs = {
+ 		.set_vtg_params = optc1_set_vtg_params,
+ 		.program_manual_trigger = optc2_program_manual_trigger,
+ 		.setup_manual_trigger = optc2_setup_manual_trigger,
+-		.is_matching_timing = optc1_is_matching_timing
++		.get_hw_timing = optc1_get_hw_timing,
+ };
+ 
+ void dcn20_timing_generator_init(struct optc *optc1)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+index b7d977b4b0d5..412d3032e4ef 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+@@ -576,6 +576,10 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = {
+ 	.set_avmute = enc1_stream_encoder_set_avmute,
+ 	.dig_connect_to_otg  = enc1_dig_connect_to_otg,
+ 	.dig_source_otg = enc1_dig_source_otg,
++
++	.dp_get_pixel_format =
++		enc1_stream_encoder_dp_get_pixel_format,
++
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	.enc_read_state = enc2_read_state,
+ 	.dp_set_dsc_config = enc2_dp_set_dsc_config,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+index fe9b7a10a1c3..6305e388612a 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+@@ -214,6 +214,11 @@ struct stream_encoder_funcs {
+ 	unsigned int (*dig_source_otg)(
+ 		struct stream_encoder *enc);
+ 
++	bool (*dp_get_pixel_format)(
++		struct stream_encoder *enc,
++		enum dc_pixel_encoding *encoding,
++		enum dc_color_depth *depth);
++
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	void (*enc_read_state)(struct stream_encoder *enc, struct enc_state *s);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+index 6196cc32356e..27c73caf74ee 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+@@ -261,6 +261,8 @@ struct timing_generator_funcs {
+ 
+ 	void (*program_manual_trigger)(struct timing_generator *optc);
+ 	void (*setup_manual_trigger)(struct timing_generator *optc);
++	bool (*get_hw_timing)(struct timing_generator *optc,
++			struct dc_crtc_timing *hw_crtc_timing);
+ 
+ 	void (*set_vtg_params)(struct timing_generator *optc,
+ 			const struct dc_crtc_timing *dc_crtc_timing);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4073-drm-amd-display-Fix-maybe-uninitialized-warning.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4073-drm-amd-display-Fix-maybe-uninitialized-warning.patch
new file mode 100644
index 00000000..3255d0c6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4073-drm-amd-display-Fix-maybe-uninitialized-warning.patch
@@ -0,0 +1,47 @@
+From 73d960dc23e2175b54a1a34f30c46605b4b87c80 Mon Sep 17 00:00:00 2001
+From: Leo Li <sunpeng.li@amd.com>
+Date: Fri, 20 Sep 2019 09:43:36 -0400
+Subject: [PATCH 4073/4256] drm/amd/display: Fix maybe-uninitialized warning
+
+[Why]
+
+Compiling with GCC 9.1.0 gives the following warning (I have
+warnings-as-errors enabled):
+
+drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/core/dc.c: In function 'dc_validate_seamless_boot_timing':
+drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/core/dc.c:1180:8: error: 'se' may be used uninitialized in this function [-Werror=maybe-uninitialized]
+ 1180 |   if (!se->funcs->dp_get_pixel_format(
+      |        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ 1181 |    se,
+      |    ~~~
+ 1182 |    &hw_crtc_timing.pixel_encoding,
+      |    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ 1183 |    &hw_crtc_timing.display_color_depth))
+
+[How]
+
+Initialize se to NULL.
+
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index f89766a5cc72..7142c014502a 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1001,7 +1001,7 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
+ 				struct dc_crtc_timing *crtc_timing)
+ {
+ 	struct timing_generator *tg;
+-	struct stream_encoder *se;
++	struct stream_encoder *se = NULL;
+ 
+ 	struct dc_crtc_timing hw_crtc_timing = {0};
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4074-drm-amd-display-use-vbios-message-to-call-smu-for-dp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4074-drm-amd-display-use-vbios-message-to-call-smu-for-dp.patch
new file mode 100644
index 00000000..7cbf5340
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4074-drm-amd-display-use-vbios-message-to-call-smu-for-dp.patch
@@ -0,0 +1,102 @@
+From d00b78c7269671f69ede1af2b9bf32ad3a82e932 Mon Sep 17 00:00:00 2001
+From: Charlene Liu <charlene.liu@amd.com>
+Date: Tue, 17 Sep 2019 20:28:40 -0400
+Subject: [PATCH 4074/4256] drm/amd/display: use vbios message to call smu for
+ dpm level
+
+[Description]
+use vbios message to call smu for dpm level
+also only program dmdata in vsyncflip as HW requirement.
+
+Signed-off-by: Charlene Liu <charlene.liu@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h  |  1 +
+ drivers/gpu/drm/amd/display/dc/dc.h               |  8 ++++++++
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  6 ++++--
+ .../drm/amd/display/dc/inc/hw/clk_mgr_internal.h  | 15 +++++++++++++++
+ 4 files changed, 28 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
+index ac31a9787305..c9fd824f3c23 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
+@@ -50,4 +50,5 @@ void dcn2_get_clock(struct clk_mgr *clk_mgr,
+ 			enum dc_clock_type clock_type,
+ 			struct dc_clock_config *clock_cfg);
+ 
++void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr);
+ #endif //__DCN20_CLK_MGR_H__
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 6c50d5c24658..c04a1f40e0be 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -245,6 +245,13 @@ enum wm_report_mode {
+ 	WM_REPORT_DEFAULT = 0,
+ 	WM_REPORT_OVERRIDE = 1,
+ };
++enum dtm_pstate{
++	dtm_level_p0 = 0,/*highest voltage*/
++	dtm_level_p1,
++	dtm_level_p2,
++	dtm_level_p3,
++	dtm_level_p4,/*when active_display_count = 0*/
++};
+ 
+ enum dcn_pwr_state {
+ 	DCN_PWR_STATE_OPTIMIZED = 0,
+@@ -271,6 +278,7 @@ struct dc_clocks {
+ 	 * optimization required
+ 	 */
+ 	bool prev_p_state_change_support;
++	enum dtm_pstate dtm_level;
+ 	int max_supported_dppclk_khz;
+ 	int max_supported_dispclk_khz;
+ 	int bw_dppclk_khz; /*a copy of dppclk_khz*/
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 2dce3e4b5e51..ce2530509e12 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -2209,8 +2209,10 @@ static void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
+ 	link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
+ 						    pipe_ctx->stream_res.stream_enc->id, true);
+ 
+-	if (link->dc->hwss.program_dmdata_engine)
+-		link->dc->hwss.program_dmdata_engine(pipe_ctx);
++	if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {
++		if (link->dc->hwss.program_dmdata_engine)
++			link->dc->hwss.program_dmdata_engine(pipe_ctx);
++	}
+ 
+ 	link->dc->hwss.update_info_frame(pipe_ctx);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+index 7dd46eb96d67..2e8cd7956a17 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+@@ -184,6 +184,21 @@ struct clk_mgr_registers {
+ 	uint32_t MP1_SMN_C2PMSG_91;
+ };
+ 
++enum clock_type {
++	clock_type_dispclk = 1,
++	clock_type_dcfclk,
++	clock_type_socclk,
++	clock_type_pixelclk,
++	clock_type_phyclk,
++	clock_type_dppclk,
++	clock_type_fclk,
++	clock_type_dcfdsclk,
++	clock_type_dscclk,
++	clock_type_uclk,
++	clock_type_dramclk,
++};
++
++
+ struct state_dependent_clocks {
+ 	int display_clk_khz;
+ 	int pixel_clk_khz;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4075-drm-amd-display-make-aux-defer-delay-and-aux-sw-star.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4075-drm-amd-display-make-aux-defer-delay-and-aux-sw-star.patch
new file mode 100644
index 00000000..de6a616c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4075-drm-amd-display-make-aux-defer-delay-and-aux-sw-star.patch
@@ -0,0 +1,55 @@
+From df707b2fb3fdcd2808df16760862d223881fa562 Mon Sep 17 00:00:00 2001
+From: Xiaodong Yan <Xiaodong.Yan@amd.com>
+Date: Fri, 30 Aug 2019 17:07:01 +0800
+Subject: [PATCH 4075/4256] drm/amd/display: make aux defer delay and aux sw
+ start delay seperate
+
+[why]
+1. defer delay and sw start delay has been mixed up, defer delay was
+programmed to AUX_SW_CONTROL:AUX_SW_START_DELAY.
+2. There's no delay for defer
+
+[how]
+1. Set  aux sw start to 0
+2. Add delay for defer scenario
+
+Signed-off-by: Xiaodong Yan <Xiaodong.Yan@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+index 79a16942ce98..16960ef29132 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+@@ -472,7 +472,7 @@ int dce_aux_transfer_raw(struct ddc_service *ddc,
+ 	aux_req.action = i2caux_action_from_payload(payload);
+ 
+ 	aux_req.address = payload->address;
+-	aux_req.delay = payload->defer_delay * 10;
++	aux_req.delay = 0;
+ 	aux_req.length = payload->length;
+ 	aux_req.data = payload->data;
+ 
+@@ -541,8 +541,15 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
+ 			case AUX_TRANSACTION_REPLY_AUX_DEFER:
+ 			case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
+ 			case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
+-				if (++aux_defer_retries >= AUX_MAX_DEFER_RETRIES)
++				if (++aux_defer_retries >= AUX_MAX_DEFER_RETRIES) {
+ 					goto fail;
++				} else {
++					if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) ||
++						(*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
++						if (payload->defer_delay > 0)
++							msleep(payload->defer_delay);
++					}
++				}
+ 				break;
+ 
+ 			case AUX_TRANSACTION_REPLY_I2C_DEFER:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4076-drm-amd-display-3.2.54.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4076-drm-amd-display-3.2.54.patch
new file mode 100644
index 00000000..4854712a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4076-drm-amd-display-3.2.54.patch
@@ -0,0 +1,28 @@
+From bd518914e9ea42034acc656faf19f8c59f4cb597 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Mon, 23 Sep 2019 08:16:36 -0400
+Subject: [PATCH 4076/4256] drm/amd/display: 3.2.54
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index c04a1f40e0be..41e366f59f10 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.53"
++#define DC_VER "3.2.54"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4077-drm-amd-display-Add-capability-check-for-static-ramp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4077-drm-amd-display-Add-capability-check-for-static-ramp.patch
new file mode 100644
index 00000000..6c178fb4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4077-drm-amd-display-Add-capability-check-for-static-ramp.patch
@@ -0,0 +1,40 @@
+From a3341c8396d18832ea305384a18e0cc3095f38fa Mon Sep 17 00:00:00 2001
+From: Jaehyun Chung <jaehyun.chung@amd.com>
+Date: Mon, 23 Sep 2019 10:00:57 -0400
+Subject: [PATCH 4077/4256] drm/amd/display: Add capability check for static
+ ramp calc
+
+[Why]
+Static ramp to max refresh rate does not have capability check on
+calculated v_total. Programming a lower v_total_min and max than the
+total causes continuous spurious HPDs.
+
+[How]
+Add a capability check after v_total calculation similar to calculate
+v_total helper functions.
+
+Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+index 65faaf6802e0..9d68cfecd472 100644
+--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
++++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+@@ -232,6 +232,10 @@ static void update_v_total_for_static_ramp(
+ 			current_duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
+ 				stream->timing.h_total), 1000);
+ 
++	/* v_total cannot be less than nominal */
++	if (v_total < stream->timing.v_total)
++		v_total = stream->timing.v_total;
++
+ 	in_out_vrr->adjust.v_total_min = v_total;
+ 	in_out_vrr->adjust.v_total_max = v_total;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4078-drm-amd-display-Fix-dongle_caps-containing-stale-inf.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4078-drm-amd-display-Fix-dongle_caps-containing-stale-inf.patch
new file mode 100644
index 00000000..897be11d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4078-drm-amd-display-Fix-dongle_caps-containing-stale-inf.patch
@@ -0,0 +1,60 @@
+From 7aa6ab215240392757a08b1ccbddfb2af54442d4 Mon Sep 17 00:00:00 2001
+From: David Galiffi <david.galiffi@amd.com>
+Date: Fri, 20 Sep 2019 20:20:23 -0400
+Subject: [PATCH 4078/4256] drm/amd/display: Fix dongle_caps containing stale
+ information.
+
+[WHY]
+
+During detection:
+function: get_active_converter_info populates link->dpcd_caps.dongle_caps
+only when dpcd_rev >= DPCD_REV_11 and DWN_STRM_PORTX_TYPE is
+DOWN_STREAM_DETAILED_HDMI or DOWN_STREAM_DETAILED_DP_PLUS_PLUS.
+Otherwise, it is not cleared, and stale information remains.
+
+During mode validation:
+function: dp_active_dongle_validate_timing reads
+link->dpcd_caps.dongle_caps->dongle_type to determine the maximum
+pixel clock to support. This information is now stale and no longer
+valid.
+
+[HOW]
+dp_active_dongle_validate_timing should be using
+link->dpcd_caps->dongle_type instead.
+
+Signed-off-by: David Galiffi <david.galiffi@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c    | 2 +-
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 6fdb78a152e0..2a7fb79ad9f3 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2254,7 +2254,7 @@ static bool dp_active_dongle_validate_timing(
+ 		break;
+ 	}
+ 
+-	if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
++	if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
+ 		dongle_caps->extendedCapValid == false)
+ 		return true;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index aae204141c60..0f59b68aa4c2 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2575,6 +2575,7 @@ static void get_active_converter_info(
+ 	uint8_t data, struct dc_link *link)
+ {
+ 	union dp_downstream_port_present ds_port = { .byte = data };
++	memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
+ 
+ 	/* decode converter info*/
+ 	if (!ds_port.fields.PORT_PRESENT) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4079-drm-amd-display-correct-stream-LTE_340MCSC_SCRAMBLE-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4079-drm-amd-display-correct-stream-LTE_340MCSC_SCRAMBLE-.patch
new file mode 100644
index 00000000..938f45d5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4079-drm-amd-display-correct-stream-LTE_340MCSC_SCRAMBLE-.patch
@@ -0,0 +1,53 @@
+From bac1d20351b9cf82ea0545d60cdc97b93f56a96a Mon Sep 17 00:00:00 2001
+From: Wayne Lin <Wayne.Lin@amd.com>
+Date: Thu, 19 Sep 2019 17:41:02 +0800
+Subject: [PATCH 4079/4256] drm/amd/display: correct stream
+ LTE_340MCSC_SCRAMBLE value
+
+[Why]
+HDMI 2.0 requires scrambling under specific conditions. We refer to
+stream property LTE_340MCSC_SCRAMBLE to determine whether en/dis
+scrambling.
+While creating stream for sink, we setup LTE_340MCSC_SCRAMBLE by
+referring to edid_caps. However, dm_helpers_parse_edid_caps()
+doesn't construct HDMI Forum block data for edid_caps.
+Moreover, fill_stream_properties_from_drm_display_mode() aslo
+unconsciously clear the LTE_340MCSC_SCRAMBLE flag.
+
+[How]
+Drm already provides drm_display_info to refer HDMI Forum vsdb info.
+Set stream LTE_340MCSC_SCRAMBLE by drm_display_info and remove
+memset in fill_stream_properties_from_drm_display_mode()
+
+Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index be90836269b4..25d20fd466c0 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -3451,7 +3451,6 @@ static void fill_stream_properties_from_drm_display_mode(
+ 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
+ 	struct hdmi_vendor_infoframe hv_frame;
+ 	struct hdmi_avi_infoframe avi_frame;
+-	memset(timing_out, 0, sizeof(struct dc_crtc_timing));
+ 
+ 	timing_out->h_border_left = 0;
+ 	timing_out->h_border_right = 0;
+@@ -3719,6 +3718,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ 
+ 	stream->dm_stream_context = aconnector;
+ 
++	stream->timing.flags.LTE_340MCSC_SCRAMBLE =
++		drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
++
+ 	list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
+ 		/* Search for preferred mode */
+ 		if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4080-drm-amd-display-Skip-DIG-Check-if-Link-is-Virtual-fo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4080-drm-amd-display-Skip-DIG-Check-if-Link-is-Virtual-fo.patch
new file mode 100644
index 00000000..83a1f49b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4080-drm-amd-display-Skip-DIG-Check-if-Link-is-Virtual-fo.patch
@@ -0,0 +1,39 @@
+From 0e8b18200cfac4a40f7e7636fb1a5892f7d04667 Mon Sep 17 00:00:00 2001
+From: Sung Lee <sung.lee@amd.com>
+Date: Tue, 24 Sep 2019 13:20:33 -0400
+Subject: [PATCH 4080/4256] drm/amd/display: Skip DIG Check if Link is Virtual
+ for Display Count
+
+[WHY]
+Without a check for virtual links, every link's DIG was getting
+checked for enabled or disabled. If link was virtual, since it
+did not have a DIG, this would cause issues.
+
+[HOW]
+Skip DIG Enable check if link is virtual and add virtual link to
+to display count.
+
+Signed-off-by: Sung Lee <sung.lee@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 68d38239304c..cae6a6f5405d 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -79,7 +79,8 @@ int rn_get_active_display_cnt_wa(
+ 		 * S0i2.
+ 		 */
+ 		/* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
+-		if (link->link_enc->funcs->is_dig_enabled(link->link_enc))
++		if (link->connector_signal == SIGNAL_TYPE_VIRTUAL ||
++				link->link_enc->funcs->is_dig_enabled(link->link_enc))
+ 			display_count++;
+ 	}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4081-drm-amd-display-hook-up-notify-watermark-ranges-and-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4081-drm-amd-display-hook-up-notify-watermark-ranges-and-.patch
new file mode 100644
index 00000000..e04489cd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4081-drm-amd-display-hook-up-notify-watermark-ranges-and-.patch
@@ -0,0 +1,118 @@
+From 8d5223711556b6922e79bdd47ad24fbc7beea733 Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Thu, 22 Aug 2019 11:54:41 -0400
+Subject: [PATCH 4081/4256] drm/amd/display: hook up notify watermark ranges
+ and get clock table
+
+[Why]
+Previously SMU was giving us 0s for the clock table. Now they have valid
+clock table. We should use theirs. Also, need to send SMU watermark
+ranges for selecting optimal watermarks.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 44 +++++++++++++++----
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 16 +++++--
+ 2 files changed, 48 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index cae6a6f5405d..ba959f04863c 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -529,22 +529,48 @@ void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_ra
+ 
+ }
+ 
+-void clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
++unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
+ {
+ 	int i;
+ 
++	for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) {
++		if (clock_table->DcfClocks[i].Vol == voltage)
++			return clock_table->DcfClocks[i].Freq;
++	}
++
++	ASSERT(0);
++	return 0;
++}
++
++void clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
++{
++	int i, j = 0;
++
+ 	ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
+ 
+-	for (i = 0; i < PP_SMU_NUM_FCLK_DPM_LEVELS; i++) {
+-		if (clock_table->FClocks[i].Freq == 0)
++	/* Find lowest DPM, FCLK is filled in reverse order*/
++
++	for (i = PP_SMU_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) {
++		if (clock_table->FClocks[i].Freq != 0) {
++			j = i;
+ 			break;
++		}
++	}
+ 
+-		bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i].Freq;
+-		bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[i].Freq;
+-		bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[i].Freq;
+-		bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i].Freq;
+-		bw_params->clk_table.entries[i].voltage = clock_table->FClocks[i].Vol;
++	for (i = 0; i < PP_SMU_NUM_FCLK_DPM_LEVELS; i++) {
++		if (j < 0) {
++			/* Invalid entries */
++			bw_params->clk_table.entries[i].fclk_mhz = 0;
++			continue;
++		}
++		bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq;
++		bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq;
++		bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol;
++		bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
++		j--;
+ 	}
++
++
+ 	bw_params->clk_table.num_entries = i;
+ 
+ 	bw_params->vram_type = asic_id->vram_type;
+@@ -553,7 +579,7 @@ void clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct d
+ 	for (i = 0; i < WM_SET_COUNT; i++) {
+ 		bw_params->wm_table.entries[i].wm_inst = i;
+ 
+-		if (clock_table->FClocks[i].Freq == 0) {
++		if (i >= bw_params->clk_table.num_entries) {
+ 			bw_params->wm_table.entries[i].valid = false;
+ 			continue;
+ 		}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 0aa8e8e025e6..06a3d0bcc660 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1334,10 +1334,20 @@ struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
+ {
+ 	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
+ 
+-	pp_smu->ctx.ver = PP_SMU_VER_RN;
++	if (!pp_smu)
++		return pp_smu;
+ 
+-	pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
+-	pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
++	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
++		pp_smu->ctx.ver = PP_SMU_VER_RN;
++		pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
++		pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
++	} else {
++
++		dm_pp_get_funcs(ctx, pp_smu);
++
++		if (pp_smu->ctx.ver != PP_SMU_VER_RN)
++			pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
++	}
+ 
+ 	return pp_smu;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4082-drm-amd-display-add-renoir-specific-watermark-range-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4082-drm-amd-display-add-renoir-specific-watermark-range-.patch
new file mode 100644
index 00000000..a12845eb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4082-drm-amd-display-add-renoir-specific-watermark-range-.patch
@@ -0,0 +1,197 @@
+From 474da02b714a2fbdb114f50a82a78919fbd377ea Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Fri, 13 Sep 2019 11:33:27 -0400
+Subject: [PATCH 4082/4256] drm/amd/display: add renoir specific watermark
+ range and clk helper
+
+Doing this allows us to split it for diffrent asics. This design will
+be helpful for future Asciis.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 23 +++++++------------
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h | 10 ++++++++
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 12 +++++-----
+ .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   |  3 ++-
+ 4 files changed, 26 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index ba959f04863c..93e46e376bb1 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -472,7 +472,7 @@ struct clk_bw_params rn_bw_params = {
+ 	}
+ };
+ 
+-void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
++void rn_build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
+ {
+ 	int i, num_valid_sets;
+ 
+@@ -529,7 +529,7 @@ void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_ra
+ 
+ }
+ 
+-unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
++static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
+ {
+ 	int i;
+ 
+@@ -542,7 +542,7 @@ unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned in
+ 	return 0;
+ }
+ 
+-void clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
++void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
+ {
+ 	int i, j = 0;
+ 
+@@ -557,22 +557,15 @@ void clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct d
+ 		}
+ 	}
+ 
+-	for (i = 0; i < PP_SMU_NUM_FCLK_DPM_LEVELS; i++) {
+-		if (j < 0) {
+-			/* Invalid entries */
+-			bw_params->clk_table.entries[i].fclk_mhz = 0;
+-			continue;
+-		}
++	bw_params->clk_table.num_entries = j + 1;
++
++	for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
+ 		bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq;
+ 		bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq;
+ 		bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol;
+ 		bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
+-		j--;
+ 	}
+ 
+-
+-	bw_params->clk_table.num_entries = i;
+-
+ 	bw_params->vram_type = asic_id->vram_type;
+ 	bw_params->num_channels = asic_id->vram_width / DDR4_DRAM_WIDTH;
+ 
+@@ -658,7 +651,7 @@ void rn_clk_mgr_construct(
+ 
+ 	if (pp_smu) {
+ 		pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table);
+-		clk_mgr_helper_populate_bw_params(clk_mgr->base.bw_params, &clock_table, &ctx->asic_id);
++		rn_clk_mgr_helper_populate_bw_params(clk_mgr->base.bw_params, &clock_table, &ctx->asic_id);
+ 	}
+ 
+ 	/*
+@@ -669,7 +662,7 @@ void rn_clk_mgr_construct(
+ 	if (!debug->disable_pplib_wm_range) {
+ 		struct pp_smu_wm_range_sets ranges = {0};
+ 
+-		build_watermark_ranges(clk_mgr->base.bw_params, &ranges);
++		rn_build_watermark_ranges(clk_mgr->base.bw_params, &ranges);
+ 
+ 		/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
+ 		if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
+index 958939049add..761bfda970a5 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
+@@ -26,10 +26,20 @@
+ #ifndef __RN_CLK_MGR_H__
+ #define __RN_CLK_MGR_H__
+ 
++#include "clk_mgr.h"
++#include "dm_pp_smu.h"
++
+ struct rn_clk_registers {
+ 	uint32_t CLK1_CLK0_CURRENT_CNT; /* DPREFCLK */
+ };
+ 
++void rn_build_watermark_ranges(
++		struct clk_bw_params *bw_params,
++		struct pp_smu_wm_range_sets *ranges);
++void rn_clk_mgr_helper_populate_bw_params(
++		struct clk_bw_params *bw_params,
++		struct dpm_clocks *clock_table,
++		struct hw_asic_id *asic_id);
+ void rn_clk_mgr_construct(struct dc_context *ctx,
+ 		struct clk_mgr_internal *clk_mgr,
+ 		struct pp_smu_funcs *pp_smu,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 06a3d0bcc660..9fdfa213b47c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1278,7 +1278,6 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
+ 	dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
+ 	dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
+ 	dcn2_1_soc.num_chans = bw_params->num_channels;
+-	dcn2_1_soc.num_states = 0;
+ 
+ 	for (i = 0; i < clk_table->num_entries; i++) {
+ 
+@@ -1288,8 +1287,9 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
+ 		dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
+ 		/* This is probably wrong, TODO: find correct calculation */
+ 		dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 16 / 1000;
+-		dcn2_1_soc.num_states++;
+ 	}
++	dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - i];
++	dcn2_1_soc.num_states = i;
+ }
+ 
+ /* Temporary Place holder until we can get them from fuse */
+@@ -1317,20 +1317,20 @@ static struct dpm_clocks dummy_clocks = {
+ 
+ };
+ 
+-enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
++static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
+ 		struct pp_smu_wm_range_sets *ranges)
+ {
+ 	return PP_SMU_RESULT_OK;
+ }
+ 
+-enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
++static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
+ 		struct dpm_clocks *clock_table)
+ {
+ 	*clock_table = dummy_clocks;
+ 	return PP_SMU_RESULT_OK;
+ }
+ 
+-struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
++static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
+ {
+ 	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
+ 
+@@ -1352,7 +1352,7 @@ struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
+ 	return pp_smu;
+ }
+ 
+-void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
++static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
+ {
+ 	if (pp_smu && *pp_smu) {
+ 		kfree(*pp_smu);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+index f0f3d42a0b6f..f2e21cb9fbd5 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+@@ -47,7 +47,7 @@
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_1
+ /* Will these bw structures be ASIC specific? */
+ 
+-#define MAX_NUM_DPM_LVL		4
++#define MAX_NUM_DPM_LVL		8
+ #define WM_SET_COUNT 		4
+ 
+ 
+@@ -149,6 +149,7 @@ struct wm_table {
+ struct clk_bw_params {
+ 	unsigned int vram_type;
+ 	unsigned int num_channels;
++	unsigned int dispclk_vco_khz;
+ 	struct clk_limit_table clk_table;
+ 	struct wm_table wm_table;
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4083-drm-ttm-fix-handling-in-ttm_bo_add_mem_to_lru.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4083-drm-ttm-fix-handling-in-ttm_bo_add_mem_to_lru.patch
new file mode 100644
index 00000000..47123e55
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4083-drm-ttm-fix-handling-in-ttm_bo_add_mem_to_lru.patch
@@ -0,0 +1,36 @@
+From dd0f56cd0cf6b9c33494e58fc2b8a7cd8d733f16 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Thu, 10 Oct 2019 13:24:17 +0200
+Subject: [PATCH 4083/4256] drm/ttm: fix handling in ttm_bo_add_mem_to_lru
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We should not add the BO to the swap LRU when the new mem is fixed and
+the TTM object about to be destroyed.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/ttm/ttm_bo.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
+index 19fe14514e4c..8d6d13b7439a 100644
+--- a/drivers/gpu/drm/ttm/ttm_bo.c
++++ b/drivers/gpu/drm/ttm/ttm_bo.c
+@@ -172,8 +172,9 @@ void ttm_bo_add_to_lru(struct ttm_buffer_object *bo)
+ 		list_add_tail(&bo->lru, &man->lru[bo->priority]);
+ 		kref_get(&bo->list_kref);
+ 
+-		if (bo->ttm && !(bo->ttm->page_flags &
+-				 (TTM_PAGE_FLAG_SG | TTM_PAGE_FLAG_SWAPPED))) {
++		if (!(man->flags & TTM_MEMTYPE_FLAG_FIXED) && bo->ttm &&
++		    !(bo->ttm->page_flags & (TTM_PAGE_FLAG_SG |
++					     TTM_PAGE_FLAG_SWAPPED))) {
+ 			list_add_tail(&bo->swap,
+ 				      &bdev->glob->swap_lru[bo->priority]);
+ 			kref_get(&bo->list_kref);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4084-drm-amdgpu-remove-duplicated-include-from-mmhub_v1_0.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4084-drm-amdgpu-remove-duplicated-include-from-mmhub_v1_0.patch
new file mode 100644
index 00000000..361c17d8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4084-drm-amdgpu-remove-duplicated-include-from-mmhub_v1_0.patch
@@ -0,0 +1,29 @@
+From 79d4d3e16bdf4b9c69d7fcbc600e0c2f82f38e8d Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Sun, 6 Oct 2019 07:44:04 +0000
+Subject: [PATCH 4084/4256] drm/amdgpu: remove duplicated include from
+ mmhub_v1_0.c
+
+Remove duplicated include.
+
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index 85fdd47e015f..41c340bfc953 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -31,7 +31,6 @@
+ #include "vega10_enum.h"
+ 
+ #include "soc15_common.h"
+-#include "amdgpu_ras.h"
+ 
+ #define mmDAGB0_CNTL_MISC2_RV 0x008f
+ #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4085-drm-amdgpu-ras-fix-typos-in-documentation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4085-drm-amdgpu-ras-fix-typos-in-documentation.patch
new file mode 100644
index 00000000..be2b8653
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4085-drm-amdgpu-ras-fix-typos-in-documentation.patch
@@ -0,0 +1,36 @@
+From 91803831f1c899b5641604552d6113be595f702f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 8 Oct 2019 13:04:33 -0500
+Subject: [PATCH 4085/4256] drm/amdgpu/ras: fix typos in documentation
+
+Fix a couple of spelling typos.
+
+Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 0581004e2ed3..f57b29712d26 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -226,13 +226,13 @@ static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
+  *
+  * .. code-block:: bash
+  *
+- *	echo op block [error [sub_blcok address value]] > .../ras/ras_ctrl
++ *	echo op block [error [sub_block address value]] > .../ras/ras_ctrl
+  *
+  * op: disable, enable, inject
+  *	disable: only block is needed
+  *	enable: block and error are needed
+  *	inject: error, address, value are needed
+- * block: umc, smda, gfx, .........
++ * block: umc, sdma, gfx, .........
+  *	see ras_block_string[] for details
+  * error: ue, ce
+  *	ue: multi_uncorrectable
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4086-drm-amdgpu-ras-document-the-reboot-ras-option.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4086-drm-amdgpu-ras-document-the-reboot-ras-option.patch
new file mode 100644
index 00000000..48b2cfea
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4086-drm-amdgpu-ras-document-the-reboot-ras-option.patch
@@ -0,0 +1,34 @@
+From 050cc6273640517bb761cc168ac302e51f94fdff Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 8 Oct 2019 13:08:30 -0500
+Subject: [PATCH 4086/4256] drm/amdgpu/ras: document the reboot ras option
+
+We recently added it, but never documented it.
+
+Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index f57b29712d26..18af80f1cffd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -213,11 +213,12 @@ static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
+  * value to the address.
+  *
+  * Second member: struct ras_debug_if::op.
+- * It has three kinds of operations.
++ * It has four kinds of operations.
+  *
+  * - 0: disable RAS on the block. Take ::head as its data.
+  * - 1: enable RAS on the block. Take ::head as its data.
+  * - 2: inject errors on the block. Take ::inject as its data.
++ * - 3: reboot on unrecoverable error
+  *
+  * How to use the interface?
+  * programs:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4087-drm-amdgpu-Use-the-ALIGN-macro.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4087-drm-amdgpu-Use-the-ALIGN-macro.patch
new file mode 100644
index 00000000..d2b86243
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4087-drm-amdgpu-Use-the-ALIGN-macro.patch
@@ -0,0 +1,49 @@
+From 0159f5808d07299060963be691b386b227319859 Mon Sep 17 00:00:00 2001
+From: Luben Tuikov <luben.tuikov@amd.com>
+Date: Wed, 2 Oct 2019 00:02:18 -0400
+Subject: [PATCH 4087/4256] drm/amdgpu: Use the ALIGN() macro
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use the ALIGN() macro to set "num_dw" to a
+multiple of 8, i.e. lower 3 bits cleared.
+
+Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 11 ++---------
+ 1 file changed, 2 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 2e0e7fe98b3c..87284e8c8ece 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -2242,10 +2242,7 @@ static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
+ 	*addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
+ 		AMDGPU_GPU_PAGE_SIZE;
+ 
+-	num_dw = adev->mman.buffer_funcs->copy_num_dw;
+-	while (num_dw & 0x7)
+-		num_dw++;
+-
++	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
+ 	num_bytes = num_pages * 8;
+ 
+ 	r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
+@@ -2305,11 +2302,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
+ 
+ 	max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
+ 	num_loops = DIV_ROUND_UP(byte_count, max_bytes);
+-	num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
+-
+-	/* for IB padding */
+-	while (num_dw & 0x7)
+-		num_dw++;
++	num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
+ 
+ 	r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
+ 	if (r)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4088-drm-amdgpu-add-amdgpu_tmz-data-structure.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4088-drm-amdgpu-add-amdgpu_tmz-data-structure.patch
new file mode 100644
index 00000000..b0714113
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4088-drm-amdgpu-add-amdgpu_tmz-data-structure.patch
@@ -0,0 +1,91 @@
+From 7f91646912eddb7d646de3da9ec24fea999be58d Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Thu, 22 Aug 2019 16:21:46 +0800
+Subject: [PATCH 4088/4256] drm/amdgpu: add amdgpu_tmz data structure
+
+This patch to add amdgpu_tmz structure which stores all tmz related fields.
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  6 ++++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h | 36 +++++++++++++++++++++++++
+ 2 files changed, 41 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 0f36549b5580..3149eb06e774 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -90,6 +90,7 @@
+ #include "amdgpu_mes.h"
+ #include "amdgpu_umc.h"
+ #include "amdgpu_mmhub.h"
++#include "amdgpu_tmz.h"
+ 
+ #define MAX_GPU_INSTANCE		16
+ 
+@@ -954,6 +955,9 @@ struct amdgpu_device {
+ 	bool                            enable_mes;
+ 	struct amdgpu_mes               mes;
+ 
++	/* tmz */
++	struct amdgpu_tmz		tmz;
++
+ 	struct amdgpu_ip_block          ip_blocks[AMDGPU_MAX_IP_NUM];
+ 	int				num_ip_blocks;
+ 	struct mutex	mn_lock;
+@@ -965,7 +969,7 @@ struct amdgpu_device {
+ 	atomic64_t gart_pin_size;
+ 
+ 	/* soc15 register offset based on ip, instance and  segment */
+-	uint32_t 		*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
++	uint32_t		*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
+ 
+ 	const struct amdgpu_df_funcs	*df_funcs;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
+new file mode 100644
+index 000000000000..24bbbc21702a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
+@@ -0,0 +1,36 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __AMDGPU_TMZ_H__
++#define __AMDGPU_TMZ_H__
++
++#include "amdgpu.h"
++
++/*
++ * Trust memory zone stuff
++ */
++struct amdgpu_tmz {
++	bool	enabled;
++};
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4089-drm-amdgpu-add-tmz-feature-parameter-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4089-drm-amdgpu-add-tmz-feature-parameter-v2.patch
new file mode 100644
index 00000000..1286d3dd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4089-drm-amdgpu-add-tmz-feature-parameter-v2.patch
@@ -0,0 +1,71 @@
+From 499be98ea6291638c72dd9b1e00f0e63ce6ccd2d Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Sun, 4 Aug 2019 16:33:16 +0800
+Subject: [PATCH 4089/4256] drm/amdgpu: add tmz feature parameter (v2)
+
+This patch adds tmz parameter to enable/disable
+the feature in the amdgpu kernel module. Nomally,
+by default, it should be auto (rely on the
+hardware capability).
+
+But right now, it need to set "off" to avoid
+breaking other developers' work because it's not
+totally completed.
+
+Will set "auto" till the feature is stable and
+completely verified.
+
+v2: add "auto" option for future use.
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  2 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 11 +++++++++++
+ 2 files changed, 13 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 3149eb06e774..3e9b286d3f9e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -178,6 +178,8 @@ extern int sched_policy;
+ static const int sched_policy = KFD_SCHED_POLICY_HWS;
+ #endif
+ 
++extern int amdgpu_tmz;
++
+ #ifdef CONFIG_DRM_AMDGPU_SI
+ extern int amdgpu_si_support;
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 08c4405ad1d6..02f6fae0bbee 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -144,6 +144,7 @@ int amdgpu_discovery = -1;
+ int amdgpu_mes = 0;
+ int amdgpu_noretry = 1;
+ int amdgpu_force_asic_type = -1;
++int amdgpu_tmz = 0;
+ 
+ struct amdgpu_mgpu_info mgpu_info = {
+ 	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
+@@ -751,6 +752,16 @@ uint amdgpu_dm_abm_level = 0;
+ MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
+ module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
+ 
++/**
++ * DOC: tmz (int)
++ * Trusted Memory Zone (TMZ) is a method to protect data being written
++ * to or read from memory.
++ *
++ * The default value: 0 (off).  TODO: change to auto till it is completed.
++ */
++MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto, 0 = off (default), 1 = on)");
++module_param_named(tmz, amdgpu_tmz, int, 0444);
++
+ static const struct pci_device_id pciidlist[] = {
+ #ifdef  CONFIG_DRM_AMDGPU_SI
+ 	{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4090-drm-amdgpu-add-function-to-check-tmz-capability-v4.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4090-drm-amdgpu-add-function-to-check-tmz-capability-v4.patch
new file mode 100644
index 00000000..b402915b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4090-drm-amdgpu-add-function-to-check-tmz-capability-v4.patch
@@ -0,0 +1,126 @@
+From 712ecf0704ca3b2a465027441b729cafb4949e4e Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Mon, 12 Aug 2019 21:06:22 +0800
+Subject: [PATCH 4090/4256] drm/amdgpu: add function to check tmz capability
+ (v4)
+
+Add a function to check tmz capability with kernel parameter and ASIC type.
+
+v2: use a per device tmz variable instead of global amdgpu_tmz.
+v3: refine the comments for the function. (Luben)
+v4: add amdgpu_tmz.c/h for future use.
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile        |  2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  3 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c    | 49 ++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h    |  3 ++
+ 4 files changed, 56 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index fa5703505748..d2fa7313c876 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -56,7 +56,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
+ 	amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_sem.o \
+ 	amdgpu_ras.o amdgpu_vm_cpu.o amdgpu_vm_sdma.o \
+ 	amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o amdgpu_umc.o \
+-	smu_v11_0_i2c.o
++	smu_v11_0_i2c.o amdgpu_tmz.o
+ 
+ amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 4f7b0f0447bf..39ccf6855efb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -63,6 +63,7 @@
+ #include "amdgpu_xgmi.h"
+ #include "amdgpu_ras.h"
+ #include "amdgpu_pmu.h"
++#include "amdgpu_tmz.h"
+ 
+ #include <linux/suspend.h>
+ 
+@@ -1027,6 +1028,8 @@ static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
+ 	adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
+ 	amdgpu_direct_gma_size = min(amdgpu_direct_gma_size, 96);
+ 
++	adev->tmz.enabled = amdgpu_is_tmz(adev);
++
+ 	return ret;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
+new file mode 100644
+index 000000000000..14a55003dd81
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
+@@ -0,0 +1,49 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include <drm/drmP.h>
++#include "amdgpu.h"
++#include "amdgpu_tmz.h"
++
++
++/**
++ * amdgpu_is_tmz - validate trust memory zone
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Return true if @dev supports trusted memory zones (TMZ), and return false if
++ * @dev does not support TMZ.
++ */
++bool amdgpu_is_tmz(struct amdgpu_device *adev)
++{
++	if (!amdgpu_tmz)
++		return false;
++
++	if (adev->asic_type < CHIP_RAVEN || adev->asic_type == CHIP_ARCTURUS) {
++		dev_warn(adev->dev, "doesn't support trusted memory zones (TMZ)\n");
++		return false;
++	}
++
++	dev_info(adev->dev, "TMZ feature is enabled\n");
++
++	return true;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
+index 24bbbc21702a..28e05177fb89 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h
+@@ -33,4 +33,7 @@ struct amdgpu_tmz {
+ 	bool	enabled;
+ };
+ 
++
++extern bool amdgpu_is_tmz(struct amdgpu_device *adev);
++
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4091-drm-amdgpu-add-tmz-bit-in-frame-control-packet.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4091-drm-amdgpu-add-tmz-bit-in-frame-control-packet.patch
new file mode 100644
index 00000000..0b236756
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4091-drm-amdgpu-add-tmz-bit-in-frame-control-packet.patch
@@ -0,0 +1,45 @@
+From bd8867e3b1d805122e517aa1bfa783408a8f7a06 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Thu, 8 Aug 2019 17:00:16 +0800
+Subject: [PATCH 4091/4256] drm/amdgpu: add tmz bit in frame control packet
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This patch adds tmz bit in frame control pm4 packet, and it will used in future.
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nvd.h    | 1 +
+ drivers/gpu/drm/amd/amdgpu/soc15d.h | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nvd.h b/drivers/gpu/drm/amd/amdgpu/nvd.h
+index 1de984647dbb..f3d8771ebed4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nvd.h
++++ b/drivers/gpu/drm/amd/amdgpu/nvd.h
+@@ -306,6 +306,7 @@
+ #define	PACKET3_GET_LOD_STATS				0x8E
+ #define	PACKET3_DRAW_MULTI_PREAMBLE			0x8F
+ #define	PACKET3_FRAME_CONTROL				0x90
++#			define FRAME_TMZ	(1 << 0)
+ #			define FRAME_CMD(x) ((x) << 28)
+ 			/*
+ 			 * x=0: tmz_begin
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h b/drivers/gpu/drm/amd/amdgpu/soc15d.h
+index edfe50821cd9..295d68c5811d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15d.h
++++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h
+@@ -286,6 +286,7 @@
+ #define	PACKET3_WAIT_ON_DE_COUNTER_DIFF			0x88
+ #define	PACKET3_SWITCH_BUFFER				0x8B
+ #define PACKET3_FRAME_CONTROL				0x90
++#			define FRAME_TMZ	(1 << 0)
+ #			define FRAME_CMD(x) ((x) << 28)
+ 			/*
+ 			 * x=0: tmz_begin
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4092-drm-amdgpu-expand-the-emit-tmz-interface-with-truste.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4092-drm-amdgpu-expand-the-emit-tmz-interface-with-truste.patch
new file mode 100644
index 00000000..4ef6f052
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4092-drm-amdgpu-expand-the-emit-tmz-interface-with-truste.patch
@@ -0,0 +1,136 @@
+From 989ed3ab67eeac447326db39a90c1b5e0fadc0c6 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Thu, 8 Aug 2019 19:07:19 +0800
+Subject: [PATCH 4092/4256] drm/amdgpu: expand the emit tmz interface with
+ trusted flag
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This patch expands the emit_tmz function to support trusted flag while we want
+to set command buffer in trusted mode.
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c   |  2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  4 ++--
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 16 ++++++++++++----
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c    | 13 ++++++++++---
+ 4 files changed, 25 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+index 0515f7a98a11..19e638af4d9c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+@@ -238,7 +238,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
+ 	}
+ 
+ 	if (ring->funcs->emit_tmz)
+-		amdgpu_ring_emit_tmz(ring, false);
++		amdgpu_ring_emit_tmz(ring, false, false);
+ 
+ #ifdef CONFIG_X86_64
+ 	if (!(adev->flags & AMD_IS_APU))
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+index 930316e60155..34aa63ad5799 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+@@ -166,7 +166,7 @@ struct amdgpu_ring_funcs {
+ 	void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
+ 					uint32_t reg0, uint32_t reg1,
+ 					uint32_t ref, uint32_t mask);
+-	void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
++	void (*emit_tmz)(struct amdgpu_ring *ring, bool start, bool trusted);
+ 	/* priority functions */
+ 	void (*set_priority) (struct amdgpu_ring *ring,
+ 			      enum drm_sched_priority priority);
+@@ -247,7 +247,7 @@ struct amdgpu_ring {
+ #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
+ #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
+ #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
+-#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
++#define amdgpu_ring_emit_tmz(r, b, s) (r)->funcs->emit_tmz((r), (b), (s))
+ #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
+ #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
+ #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 1df3a835e62f..5a153d3893d8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -248,7 +248,8 @@ static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
+ static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
+ static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
+ static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
+-static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start);
++static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start,
++				    bool trusted);
+ 
+ static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
+ {
+@@ -4548,7 +4549,7 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flag
+ 		gfx_v10_0_ring_emit_ce_meta(ring,
+ 				    flags & AMDGPU_IB_PREEMPTED ? true : false);
+ 
+-	gfx_v10_0_ring_emit_tmz(ring, true);
++	gfx_v10_0_ring_emit_tmz(ring, true, false);
+ 
+ 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
+ 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
+@@ -4706,10 +4707,17 @@ static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
+ 					   sizeof(de_payload) >> 2);
+ }
+ 
+-static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
++static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start,
++				    bool trusted)
+ {
+ 	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
+-	amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
++	/*
++	 * cmd = 0: frame begin
++	 * cmd = 1: frame end
++	 */
++	amdgpu_ring_write(ring,
++			  ((ring->adev->tmz.enabled && trusted) ? FRAME_TMZ : 0)
++			  | FRAME_CMD(start ? 0 : 1));
+ }
+ 
+ static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 5f7956004627..b1ff036e9fb5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -5036,10 +5036,17 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
+ 	amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
+ }
+ 
+-static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
++static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start,
++				   bool trusted)
+ {
+ 	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
+-	amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
++	/*
++	 * cmd = 0: frame begin
++	 * cmd = 1: frame end
++	 */
++	amdgpu_ring_write(ring,
++			  ((ring->adev->tmz.enabled && trusted) ? FRAME_TMZ : 0)
++			  | FRAME_CMD(start ? 0 : 1));
+ }
+ 
+ static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
+@@ -5049,7 +5056,7 @@ static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
+ 	if (amdgpu_sriov_vf(ring->adev))
+ 		gfx_v9_0_ring_emit_ce_meta(ring);
+ 
+-	gfx_v9_0_ring_emit_tmz(ring, true);
++	gfx_v9_0_ring_emit_tmz(ring, true, false);
+ 
+ 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
+ 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4093-drm-amdgpu-expand-the-context-control-interface-with.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4093-drm-amdgpu-expand-the-context-control-interface-with.patch
new file mode 100644
index 00000000..31de8444
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4093-drm-amdgpu-expand-the-context-control-interface-with.patch
@@ -0,0 +1,143 @@
+From 7afa328a1d4e78c59c5e74be206878e5b64350a3 Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Thu, 8 Aug 2019 20:18:42 +0800
+Subject: [PATCH 4093/4256] drm/amdgpu: expand the context control interface
+ with trust flag
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This patch expands the context control function to support trusted flag while we
+want to set command buffer in trusted mode.
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c   | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +++--
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 4 +++-
+ drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c    | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c    | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c    | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c    | 5 +++--
+ 7 files changed, 16 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+index 19e638af4d9c..d75dc14be086 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+@@ -219,7 +219,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
+ 	if (job && ring->funcs->emit_cntxcntl) {
+ 		status |= job->preamble_status;
+ 		status |= job->preemption_status;
+-		amdgpu_ring_emit_cntxcntl(ring, status);
++		amdgpu_ring_emit_cntxcntl(ring, status, false);
+ 	}
+ 
+ 	for (i = 0; i < num_ibs; ++i) {
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+index 34aa63ad5799..5134d0dd6dc2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+@@ -158,7 +158,8 @@ struct amdgpu_ring_funcs {
+ 	void (*begin_use)(struct amdgpu_ring *ring);
+ 	void (*end_use)(struct amdgpu_ring *ring);
+ 	void (*emit_switch_buffer) (struct amdgpu_ring *ring);
+-	void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
++	void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags,
++			       bool trusted);
+ 	void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
+ 	void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
+ 	void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
+@@ -242,7 +243,7 @@ struct amdgpu_ring {
+ #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
+ #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
+ #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
+-#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
++#define amdgpu_ring_emit_cntxcntl(r, d, s) (r)->funcs->emit_cntxcntl((r), (d), (s))
+ #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
+ #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
+ #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 5a153d3893d8..f93ac8f44a58 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -4541,7 +4541,9 @@ static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
+ 	amdgpu_ring_write(ring, 0);
+ }
+ 
+-static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
++static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
++					 uint32_t flags,
++					 bool trusted)
+ {
+ 	uint32_t dw2 = 0;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+index 8c27c305e692..b4af1b55f852 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+@@ -2972,7 +2972,8 @@ static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
+ 	return clock;
+ }
+ 
+-static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
++static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags,
++				      bool trusted)
+ {
+ 	if (flags & AMDGPU_HAVE_CTX_SWITCH)
+ 		gfx_v6_0_ring_emit_vgt_flush(ring);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+index 48796b6824cf..c08f5c53dcb4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+@@ -2309,7 +2309,8 @@ static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
+ 	amdgpu_ring_write(ring, control);
+ }
+ 
+-static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
++static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags,
++				      bool trusted)
+ {
+ 	uint32_t dw2 = 0;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index bd19af733fa8..614b8226b9eb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -6392,7 +6392,8 @@ static void gfx_v8_ring_emit_sb(struct amdgpu_ring *ring)
+ 	amdgpu_ring_write(ring, 0);
+ }
+ 
+-static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
++static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags,
++				      bool trusted)
+ {
+ 	uint32_t dw2 = 0;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index b1ff036e9fb5..2e316e9da4cf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -5049,14 +5049,15 @@ static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start,
+ 			  | FRAME_CMD(start ? 0 : 1));
+ }
+ 
+-static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
++static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags,
++				      bool trusted)
+ {
+ 	uint32_t dw2 = 0;
+ 
+ 	if (amdgpu_sriov_vf(ring->adev))
+ 		gfx_v9_0_ring_emit_ce_meta(ring);
+ 
+-	gfx_v9_0_ring_emit_tmz(ring, true, false);
++	gfx_v9_0_ring_emit_tmz(ring, true, trusted);
+ 
+ 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
+ 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4094-drm-amdgpu-add-UAPI-to-create-secure-commands-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4094-drm-amdgpu-add-UAPI-to-create-secure-commands-v3.patch
new file mode 100644
index 00000000..5a5eb56a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4094-drm-amdgpu-add-UAPI-to-create-secure-commands-v3.patch
@@ -0,0 +1,48 @@
+From 20c539209cd600898d75e8016b1360bbf1091fb1 Mon Sep 17 00:00:00 2001
+From: Luben Tuikov <luben.tuikov@amd.com>
+Date: Mon, 23 Sep 2019 19:02:41 -0400
+Subject: [PATCH 4094/4256] drm/amdgpu: add UAPI to create secure commands (v3)
+
+Add a flag to the command submission IOCTL
+structure which when present indicates that this
+command submission should be treated as
+secure. The kernel driver uses this flag to
+determine whether the engine should be
+transitioned to secure or unsecure, or the work
+can be submitted to a secure queue depending on
+the IP.
+
+v3: the flag is now at command submission IOCTL
+
+Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ include/uapi/drm/amdgpu_drm.h | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
+index 43a87fc23865..8b3694310e44 100644
+--- a/include/uapi/drm/amdgpu_drm.h
++++ b/include/uapi/drm/amdgpu_drm.h
+@@ -219,6 +219,9 @@ union drm_amdgpu_bo_list {
+ #define AMDGPU_CTX_OP_QUERY_STATE	3
+ #define AMDGPU_CTX_OP_QUERY_STATE2	4
+ 
++/* Flag the command submission as secure */
++#define AMDGPU_CS_FLAGS_SECURE          (1 << 0)
++
+ /* GPU reset status */
+ #define AMDGPU_CTX_NO_RESET		0
+ /* this the context caused it */
+@@ -613,7 +616,7 @@ struct drm_amdgpu_cs_in {
+ 	/**  Handle of resource list associated with CS */
+ 	__u32		bo_list_handle;
+ 	__u32		num_chunks;
+-	__u32		_pad;
++	__u32		flags;
+ 	/** this points to __u64 * which point to cs chunks */
+ 	__u64		chunks;
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4095-drm-amdgpu-job-is-secure-iff-CS-is-secure-v5.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4095-drm-amdgpu-job-is-secure-iff-CS-is-secure-v5.patch
new file mode 100644
index 00000000..18f4afe9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4095-drm-amdgpu-job-is-secure-iff-CS-is-secure-v5.patch
@@ -0,0 +1,78 @@
+From b6f6113276322a90cd327af91f0afe784fd93f3a Mon Sep 17 00:00:00 2001
+From: Huang Rui <ray.huang@amd.com>
+Date: Thu, 8 Aug 2019 20:05:15 +0800
+Subject: [PATCH 4095/4256] drm/amdgpu: job is secure iff CS is secure (v5)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Mark a job as secure, if and only if the command
+submission flag has the secure flag set.
+
+v2: fix the null job pointer while in vmid 0
+submission.
+v3: Context --> Command submission.
+v4: filling cs parser with cs->in.flags
+v5: move the job secure flag setting out of amdgpu_cs_submit()
+
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 2 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 2 ++
+ 3 files changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+index 34b793b980a1..ba43f3f6467b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+@@ -230,6 +230,8 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs
+ 	if (ret)
+ 		goto free_all_kdata;
+ 
++	p->job->secure = cs->in.flags & AMDGPU_CS_FLAGS_SECURE;
++
+ 	if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
+ 		ret = -ECANCELED;
+ 		goto free_all_kdata;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+index d75dc14be086..d121bbdf0ca7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+@@ -219,7 +219,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
+ 	if (job && ring->funcs->emit_cntxcntl) {
+ 		status |= job->preamble_status;
+ 		status |= job->preemption_status;
+-		amdgpu_ring_emit_cntxcntl(ring, status, false);
++		amdgpu_ring_emit_cntxcntl(ring, status, job->secure);
+ 	}
+ 
+ 	for (i = 0; i < num_ibs; ++i) {
+@@ -238,7 +238,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
+ 	}
+ 
+ 	if (ring->funcs->emit_tmz)
+-		amdgpu_ring_emit_tmz(ring, false, false);
++		amdgpu_ring_emit_tmz(ring, false, job ? job->secure : false);
+ 
+ #ifdef CONFIG_X86_64
+ 	if (!(adev->flags & AMD_IS_APU))
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+index dc7ee9358dcd..aa0e375062f2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+@@ -63,6 +63,8 @@ struct amdgpu_job {
+ 	uint64_t		uf_addr;
+ 	uint64_t		uf_sequence;
+ 
++	/* the job is due to a secure command submission */
++	bool			secure;
+ };
+ 
+ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4096-drm-amdgpu-add-UAPI-for-creating-encrypted-buffers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4096-drm-amdgpu-add-UAPI-for-creating-encrypted-buffers.patch
new file mode 100644
index 00000000..f03d972c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4096-drm-amdgpu-add-UAPI-for-creating-encrypted-buffers.patch
@@ -0,0 +1,39 @@
+From b665ac5a941f0d47b1cf6c1cc3777ff4f7cffac8 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 7 Aug 2019 21:43:24 -0500
+Subject: [PATCH 4096/4256] drm/amdgpu: add UAPI for creating encrypted buffers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add a flag to the GEM_CREATE ioctl to create encrypted buffers.
+Buffers with this flag set will be created with the TMZ bit set
+in the PTEs or engines accessing them.  This is required in order
+to properly access the data from the engines.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ include/uapi/drm/amdgpu_drm.h | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
+index 8b3694310e44..2de868bf8266 100644
+--- a/include/uapi/drm/amdgpu_drm.h
++++ b/include/uapi/drm/amdgpu_drm.h
+@@ -146,6 +146,11 @@ extern "C" {
+  * releasing the memory
+  */
+ #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE	(1 << 9)
++/* Flag that BO will be encrypted and that the TMZ bit should be
++ * set in the PTEs when mapping this buffer via GPUVM or
++ * accessing it with various hw blocks
++ */
++#define AMDGPU_GEM_CREATE_ENCRYPTED		(1 << 10)
+ 
+ /* hybrid specific */
+ /* Flag that the memory allocation should be from top of domain */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4097-drm-amdgpu-define-the-TMZ-bit-for-the-PTE.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4097-drm-amdgpu-define-the-TMZ-bit-for-the-PTE.patch
new file mode 100644
index 00000000..12caedf7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4097-drm-amdgpu-define-the-TMZ-bit-for-the-PTE.patch
@@ -0,0 +1,31 @@
+From 5d4989e33978d2d81d25fe69f4e23efe49cefc8e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 7 Aug 2019 22:31:50 -0500
+Subject: [PATCH 4097/4256] drm/amdgpu: define the TMZ bit for the PTE
+
+Define the TMZ (encryption) bit in the page table entry (PTE) for
+Raven and newer asics.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+index 4dbbe1b6b413..5cb25c1c54e0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+@@ -53,6 +53,9 @@ struct amdgpu_bo_list_entry;
+ #define AMDGPU_PTE_SYSTEM	(1ULL << 1)
+ #define AMDGPU_PTE_SNOOPED	(1ULL << 2)
+ 
++/* RV+ */
++#define AMDGPU_PTE_TMZ		(1ULL << 3)
++
+ /* VI only */
+ #define AMDGPU_PTE_EXECUTABLE	(1ULL << 4)
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4098-drm-amdgpu-set-TMZ-bits-in-PTEs-for-secure-BO-v4.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4098-drm-amdgpu-set-TMZ-bits-in-PTEs-for-secure-BO-v4.patch
new file mode 100644
index 00000000..b4fba00f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4098-drm-amdgpu-set-TMZ-bits-in-PTEs-for-secure-BO-v4.patch
@@ -0,0 +1,105 @@
+From 64083676a7dd30fec3db9f77cd30b08182aebacf Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 7 Aug 2019 22:32:46 -0500
+Subject: [PATCH 4098/4256] drm/amdgpu: set TMZ bits in PTEs for secure BO (v4)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+If a buffer object is secure, i.e. created with
+AMDGPU_GEM_CREATE_ENCRYPTED, then the TMZ bit of
+the PTEs that belong the buffer object should be
+set.
+
+v1: design and draft the skeletion of TMZ bits setting on PTEs (Alex)
+v2: return failure once create secure BO on non-TMZ platform  (Ray)
+v3: amdgpu_bo_encrypted() only checks the BO (Luben)
+v4: move TMZ flag setting into amdgpu_vm_bo_update  (Christian)
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c    | 10 ++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 11 +++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     |  4 ++++
+ 3 files changed, 25 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+index 59a1e73f4056..021a5c7d6d38 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+@@ -253,6 +253,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
+ 		      AMDGPU_GEM_CREATE_VRAM_CLEARED |
+ 		      AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
+ 		      AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
++		      AMDGPU_GEM_CREATE_ENCRYPTED |
+ 		      AMDGPU_GEM_CREATE_NO_EVICT))
+ 
+ 		return -EINVAL;
+@@ -261,6 +262,11 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
+ 	if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
+ 		return -EINVAL;
+ 
++	if (!adev->tmz.enabled && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
++		DRM_ERROR("Cannot allocate secure buffer while tmz is disabled\n");
++		return -EINVAL;
++	}
++
+ 	/* create a gem object to contain this object in */
+ 	if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
+ 	    AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
+@@ -282,6 +288,10 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
+ 		resv = vm->root.base.bo->tbo.resv;
+ 	}
+ 
++	if (flags & AMDGPU_GEM_CREATE_ENCRYPTED) {
++		/* XXX: pad out alignment to meet TMZ requirements */
++	}
++
+ 	r = amdgpu_gem_object_create(adev, size, args->in.alignment,
+ 				     (u32)(0xffffffff & args->in.domains),
+ 				     flags, ttm_bo_type_device, resv, &gobj);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+index 57f41bed2898..38a6ba7ad9be 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+@@ -229,6 +229,17 @@ static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
+ 	return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
+ }
+ 
++/**
++ * amdgpu_bo_encrypted - test if the BO is encrypted
++ * @bo: pointer to a buffer object
++ *
++ * Return true if the buffer object is encrypted, false otherwise.
++ */
++static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
++{
++	return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED;
++}
++
+ bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
+ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index af4fda196c7d..c970824b041d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -1718,6 +1718,10 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
+ 
+ 	if (bo) {
+ 		flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
++
++		if (amdgpu_bo_encrypted(bo))
++			flags |= AMDGPU_PTE_TMZ;
++
+ 		bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
+ 	} else {
+ 		flags = 0x0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4099-Removing-the-AMDGPU-VERSION-print.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4099-Removing-the-AMDGPU-VERSION-print.patch
new file mode 100644
index 00000000..d78039fd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4099-Removing-the-AMDGPU-VERSION-print.patch
@@ -0,0 +1,41 @@
+From ead762259f79d4c4bfb466f0ef238a3c37909e99 Mon Sep 17 00:00:00 2001
+From: Pavan Kumar Ramayanam <pavan.ramayanam@amd.com>
+Date: Mon, 4 Nov 2019 10:39:20 +0530
+Subject: [PATCH 4099/4103] Removing the AMDGPU VERSION print
+
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 -------
+ 1 file changed, 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 02f6fae0bbee..29cf16edbb10 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -86,8 +86,6 @@
+ #define KMS_DRIVER_MINOR	35
+ #define KMS_DRIVER_PATCHLEVEL	0
+ 
+-#define AMDGPU_VERSION          "19.10.9.418"
+-
+ int amdgpu_vram_limit = 0;
+ int amdgpu_vis_vram_limit = 0;
+ int amdgpu_gart_size = -1; /* auto */
+@@ -1420,10 +1418,6 @@ static int __init amdgpu_init(void)
+ 		goto error_fence;
+ 
+ 	DRM_INFO("amdgpu kernel modesetting enabled.\n");
+-	DRM_INFO("amdgpu version: %s\n", AMDGPU_VERSION);
+-#if defined(DRM_VER) && defined(DRM_PATCH) && defined(DRM_SUB)
+-	DRM_INFO("OS DRM version: %d.%d.%d\n", DRM_VER, DRM_PATCH, DRM_SUB);
+-#endif
+ 	kms_driver.num_ioctls = amdgpu_max_kms_ioctl;
+ 	amdgpu_register_atpx_handler();
+ 
+@@ -1454,4 +1448,3 @@ module_exit(amdgpu_exit);
+ MODULE_AUTHOR(DRIVER_AUTHOR);
+ MODULE_DESCRIPTION(DRIVER_DESC);
+ MODULE_LICENSE("GPL and additional rights");
+-MODULE_VERSION(AMDGPU_VERSION);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4100-drm-amdgpu-enable-VCN-DPG-on-Raven-and-Raven2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4100-drm-amdgpu-enable-VCN-DPG-on-Raven-and-Raven2.patch
new file mode 100644
index 00000000..0d8fdd23
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4100-drm-amdgpu-enable-VCN-DPG-on-Raven-and-Raven2.patch
@@ -0,0 +1,43 @@
+From 9c3d1f83e057cf2f27ed772ecc793e79a808b198 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 31 Oct 2019 10:37:02 -0400
+Subject: [PATCH 4100/4103] drm/amdgpu: enable VCN DPG on Raven and Raven2
+
+It's safe to enable dynamic VCN powergating on raven and
+raven2 for increased power savings.
+
+Reviewed-by: James Zhu <James.Zhu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index a77f9b708f7f..3acfdc1e2bfd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1121,7 +1121,9 @@ static int soc15_common_early_init(void *handle)
+ 				AMD_CG_SUPPORT_SDMA_LS |
+ 				AMD_CG_SUPPORT_VCN_MGCG;
+ 
+-			adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
++			adev->pg_flags = AMD_PG_SUPPORT_SDMA |
++				AMD_PG_SUPPORT_VCN |
++				AMD_PG_SUPPORT_VCN_DPG;
+ 		} else if (adev->pdev->device == 0x15d8) {
+ 			adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+ 				AMD_CG_SUPPORT_GFX_MGLS |
+@@ -1164,7 +1166,9 @@ static int soc15_common_early_init(void *handle)
+ 				AMD_CG_SUPPORT_SDMA_LS |
+ 				AMD_CG_SUPPORT_VCN_MGCG;
+ 
+-			adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
++			adev->pg_flags = AMD_PG_SUPPORT_SDMA |
++				AMD_PG_SUPPORT_VCN |
++				AMD_PG_SUPPORT_VCN_DPG;
+ 		}
+ 		break;
+ 	case CHIP_ARCTURUS:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4101-drm-amd-amdkfd-This-patch-does-not-initialize-kfd-fo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4101-drm-amd-amdkfd-This-patch-does-not-initialize-kfd-fo.patch
new file mode 100644
index 00000000..c4a6cdf7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4101-drm-amd-amdkfd-This-patch-does-not-initialize-kfd-fo.patch
@@ -0,0 +1,266 @@
+From 924825f097f4bfa2cae17a6a14a53117a9de3e9b Mon Sep 17 00:00:00 2001
+From: kalyan alle <Kalyan.Alle@amd.com>
+Date: Sat, 2 Nov 2019 16:30:31 +0530
+Subject: [PATCH 4101/4103] drm/amd/amdkfd:This patch does not initialize kfd
+ for
+
+only for raven2.
+
+Initializing kfd (rocm) for raven2(Bilby R1000) is causing S3 to fail after very few
+iterations(less than 10). With kfd disabled, we could see the S3 getting
+passed. This patch disables kfd based on the device id. If the device id
+ is 15d8(raven2), kfd does not get initialized. This patch does not have
+any impact on the rocm functionality on Bilby V1000.Also it makes sense
+to disable kfd/rocm on Bilby R1000 as Rocm is not supported on it.
+
+Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h           |  1 +
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c  |  7 +++++
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  | 10 +++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |  4 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c       |  1 +
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c       | 28 +++++++++++++++++++
+ drivers/gpu/drm/amd/amdkfd/kfd_module.c       |  4 +++
+ 7 files changed, 55 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 3e9b286d3f9e..3bb4b7c6a42d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -114,6 +114,7 @@ struct amdgpu_mgpu_info
+ /*
+  * Modules parameters.
+  */
++extern int kfd_flag_for_rv2;
+ extern int amdgpu_modeset;
+ extern int amdgpu_vram_limit;
+ extern int amdgpu_vis_vram_limit;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
+index 24d2a623d9f0..4abc39ed8f75 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
+@@ -28,6 +28,7 @@
+ #include <linux/slab.h>
+ #include <linux/sched/mm.h>
+ #include "amdgpu_amdkfd.h"
++#include "amdgpu.h"
+ 
+ static const struct dma_fence_ops amdkfd_fence_ops;
+ static atomic_t fence_seq = ATOMIC_INIT(0);
+@@ -83,6 +84,9 @@ struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
+ #ifdef CONFIG_HSA_AMD
+ struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
+ {
++	if (kfd_flag_for_rv2)
++		return NULL;
++
+ 	struct amdgpu_amdkfd_fence *fence;
+ 
+ 	if (!f)
+@@ -161,6 +165,9 @@ static void amdkfd_fence_release(struct dma_fence *f)
+  */
+ bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
+ {
++	if (kfd_flag_for_rv2)
++		return false;
++
+ 	struct amdgpu_amdkfd_fence *fence = to_amdgpu_amdkfd_fence(f);
+ 
+ 	if (!fence)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index 9ffe63377c99..3e13f3e9097a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -32,6 +32,7 @@
+ #include "amdgpu_vm.h"
+ #include "amdgpu_amdkfd.h"
+ #include "amdgpu_dma_buf.h"
++#include "amdgpu.h"
+ 
+ /* BO flag to indicate a KFD userptr BO */
+ #define AMDGPU_AMDKFD_USERPTR_BO (1ULL << 63)
+@@ -188,6 +189,9 @@ static void unreserve_mem_limit(struct amdgpu_device *adev,
+ 
+ void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo)
+ {
++	if (kfd_flag_for_rv2)
++		return;
++
+ 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+ 	u32 domain = bo->preferred_domains;
+ 	bool sg = (bo->preferred_domains == AMDGPU_GEM_DOMAIN_CPU);
+@@ -1077,6 +1081,9 @@ int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
+ void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
+ 				    struct amdgpu_vm *vm)
+ {
++	if (kfd_flag_for_rv2)
++		return;
++
+ 	struct amdkfd_process_info *process_info = vm->process_info;
+ 	struct amdgpu_bo *pd = vm->root.base.bo;
+ 
+@@ -1919,6 +1926,9 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_dev *kgd, void *vm,
+ int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem,
+ 				struct mm_struct *mm)
+ {
++	if (kfd_flag_for_rv2)
++		return 0;
++
+ 	struct amdkfd_process_info *process_info = mem->process_info;
+ 	int invalid, evicted_bos;
+ 	int r = 0;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 39ccf6855efb..1b972f531740 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1624,6 +1624,10 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
+ 	if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
+ 		amdgpu_discovery_get_gfx_info(adev);
+ 
++	if ((adev->asic_type == CHIP_RAVEN) &&
++            (adev->pdev->device == 0x15d8))
++		kfd_flag_for_rv2 = 1;
++
+ 	amdgpu_amdkfd_device_probe(adev);
+ 
+ 	if (amdgpu_sriov_vf(adev)) {
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 29cf16edbb10..50927cd86cc9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -119,6 +119,7 @@ int amdgpu_sched_hw_submission = 2;
+ int amdgpu_no_evict = 0;
+ int amdgpu_direct_gma_size = 0;
+ int amdgpu_ssg_enabled = 0;
++int kfd_flag_for_rv2 = 0;
+ uint amdgpu_pcie_gen_cap = 0;
+ uint amdgpu_pcie_lane_cap = 0;
+ uint amdgpu_cg_mask = 0xffffffff;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index 24728e70e871..ee9b9a6968bd 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -29,6 +29,7 @@
+ #include "cwsr_trap_handler.h"
+ #include "kfd_iommu.h"
+ #include "amdgpu_amdkfd.h"
++#include "amdgpu.h"
+ 
+ #define MQD_SIZE_ALIGNED 768
+ 
+@@ -491,6 +492,9 @@ static int kfd_resume(struct kfd_dev *kfd);
+ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
+ 	struct pci_dev *pdev, unsigned int asic_type, bool vf)
+ {
++	if (kfd_flag_for_rv2)
++		return NULL;
++
+ 	struct kfd_dev *kfd;
+ 	const struct kfd_device_info *device_info;
+ 	const struct kfd2kgd_calls *f2g;
+@@ -574,6 +578,9 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
+ 			 struct drm_device *ddev,
+ 			 const struct kgd2kfd_shared_resources *gpu_resources)
+ {
++	if (kfd_flag_for_rv2)
++		return false;
++
+ 	unsigned int size;
+ 
+ 	kfd->ddev = ddev;
+@@ -710,6 +717,9 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
+ 
+ void kgd2kfd_device_exit(struct kfd_dev *kfd)
+ {
++	if (kfd_flag_for_rv2)
++		return;
++
+ 	if (kfd->init_complete) {
+ 		kgd2kfd_suspend(kfd);
+ 		device_queue_manager_uninit(kfd->dqm);
+@@ -727,6 +737,9 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd)
+ 
+ int kgd2kfd_pre_reset(struct kfd_dev *kfd)
+ {
++	if (kfd_flag_for_rv2)
++		return 0;
++
+ 	if (!kfd->init_complete)
+ 		return 0;
+ 	kgd2kfd_suspend(kfd);
+@@ -746,6 +759,9 @@ int kgd2kfd_pre_reset(struct kfd_dev *kfd)
+ 
+ int kgd2kfd_post_reset(struct kfd_dev *kfd)
+ {
++	if (kfd_flag_for_rv2)
++		return 0;
++
+ 	int ret, count;
+ 
+ 	if (!kfd->init_complete)
+@@ -772,6 +788,9 @@ bool kfd_is_locked(void)
+ #ifdef CONFIG_HSA_AMD
+ void kgd2kfd_suspend(struct kfd_dev *kfd)
+ {
++	if (kfd_flag_for_rv2)
++		return;
++
+ 	if (!kfd->init_complete)
+ 		return;
+ 
+@@ -786,6 +805,9 @@ void kgd2kfd_suspend(struct kfd_dev *kfd)
+ 
+ int kgd2kfd_resume(struct kfd_dev *kfd)
+ {
++	if (kfd_flag_for_rv2)
++		return 0;
++
+ 	int ret, count;
+ 
+ 	if (!kfd->init_complete)
+@@ -835,6 +857,9 @@ static int kfd_resume(struct kfd_dev *kfd)
+ /* This is called directly from KGD at ISR. */
+ void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
+ {
++	if (kfd_flag_for_rv2)
++		return;
++
+ 	uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE];
+ 	bool is_patched = false;
+ 	unsigned long flags;
+@@ -1130,6 +1155,9 @@ int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj)
+ 
+ void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
+ {
++	if (kfd_flag_for_rv2)
++		return NULL;
++
+ 	if (kfd)
+ 		atomic_inc(&kfd->sram_ecc_flag);
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
+index c7b857b542e8..3b6896effdc9 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
+@@ -24,6 +24,7 @@
+ #include <linux/device.h>
+ #include "kfd_priv.h"
+ #include "amdgpu_amdkfd.h"
++#include "amdgpu.h"
+ 
+ static int kfd_init(void)
+ {
+@@ -98,6 +99,9 @@ int kgd2kfd_init(void)
+ #ifdef CONFIG_HSA_AMD
+ void kgd2kfd_exit(void)
+ {
++	if (kfd_flag_for_rv2)
++		return NULL;
++
+ 	kfd_exit();
+ }
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4102-drm-amd-display-Fixes-the-unigine-heaven-hang-when.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4102-drm-amd-display-Fixes-the-unigine-heaven-hang-when.patch
new file mode 100644
index 00000000..99857663
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4102-drm-amd-display-Fixes-the-unigine-heaven-hang-when.patch
@@ -0,0 +1,75 @@
+From 239474d5beff1d866ec464851c741368bbfc44e4 Mon Sep 17 00:00:00 2001
+From: kalyan alle <Kalyan.Alle@amd.com>
+Date: Fri, 25 Oct 2019 20:18:11 +0530
+Subject: [PATCH 4102/4103] drm/amd/display: Fixes the unigine heaven hang when
+
+user choses to quit/exit the application on 4.19 kernel
+
+This patch fixes the unigine heaven application hang when user chooses
+to quit the application.
+
+Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c   | 17 +++++++++++++----
+ 1 file changed, 13 insertions(+), 4 deletions(-)
+ mode change 100644 => 100755 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+old mode 100644
+new mode 100755
+index 25d20fd466c0..70ca73d2a80b
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -3251,7 +3251,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
+ 	if (ret)
+ 		return ret;
+ 
+-	return ret;
++	return 0;
+ }
+ 
+ static void update_stream_scaling_settings(const struct drm_display_mode *mode,
+@@ -3939,7 +3939,6 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
+ 	.atomic_destroy_state = dm_crtc_destroy_state,
+ 	.set_crc_source = amdgpu_dm_crtc_set_crc_source,
+ 	.verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
+-	.get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
+ 	.enable_vblank = dm_enable_vblank,
+ 	.disable_vblank = dm_disable_vblank,
+ };
+@@ -4034,7 +4033,7 @@ int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
+ 		ret = 0;
+ 	}
+ 
+-	return 0;
++	return ret;
+ }
+ 
+ int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
+@@ -4648,12 +4647,22 @@ static int dm_plane_atomic_check(struct drm_plane *plane,
+ }
+ 
+ static int dm_plane_atomic_async_check(struct drm_plane *plane,
+-				       struct drm_plane_state *new_plane_state)
++					struct drm_plane_state *new_plane_state)
+ {
++	struct drm_plane_state *old_plane_state =
++		drm_atomic_get_old_plane_state(new_plane_state->state, plane);
++
+ 	/* Only support async updates on cursor planes. */
+ 	if (plane->type != DRM_PLANE_TYPE_CURSOR)
+ 		return -EINVAL;
+ 
++	/*
++	* DRM calls prepare_fb and cleanup_fb on new_plane_state for
++	* async commits so don't allow fb changes.
++	*/
++	if (old_plane_state->fb != new_plane_state->fb)
++		return -EINVAL;
++
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4103-modifying-link-and-led-state-with-respect-to-cable-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4103-modifying-link-and-led-state-with-respect-to-cable-c.patch
new file mode 100644
index 00000000..447629ee
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4103-modifying-link-and-led-state-with-respect-to-cable-c.patch
@@ -0,0 +1,210 @@
+From 89a9f6eee64e54ce282584cfc7bedcdd944f7c4b Mon Sep 17 00:00:00 2001
+From: Pavan Kumar Ramayanam <pavan.ramayanam@amd.com>
+Date: Tue, 12 Nov 2019 18:15:16 +0530
+Subject: [PATCH 4103/4736] modifying link and led state with respect to cable
+ connection
+
+ Enable Marvell PHY 10G linkup on Bilby. The current
+ 10G linkup happens only in backplane mode, meaning there will be no sideband
+ to talk to the external PHY connected onboard. So, when the driver reads the
+ port property as BACKPLANE, technically we are not supposed to go and read
+ what is the external PHY connected through MDIO. This changes are only a
+ workaround to read the external phy through MDIO in backplane mode.
+---
+ drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c | 30 ++++++--
+ drivers/net/phy/marvell10g.c                | 80 ++++++++++++++++++++-
+ 2 files changed, 105 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
+index 9cddcc8433e1..a6fb6754984f 100755
+--- a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
++++ b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
+@@ -156,6 +156,11 @@
+ /* RRC frequency during link status check */
+ #define XGBE_RRC_FREQUENCY		10
+ 
++/* Enable Marvell PHY writes by forcing the MDIO connections */
++static int force_mdio_mv_bp_con = 1;
++module_param(force_mdio_mv_bp_con, uint, 0644);
++MODULE_PARM_DESC(force_mdio_mv_bp_con,
++                 " Enable Marvell PHY writes by forcing the MDIO connections");
+ enum xgbe_port_mode {
+ 	XGBE_PORT_MODE_RSVD = 0,
+ 	XGBE_PORT_MODE_BACKPLANE,
+@@ -985,8 +990,15 @@ static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
+ 	pdata->an_again = 0;
+ 
+ 	/* Check for the use of an external PHY */
+-	if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
+-		return 0;
++	if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) {
++		if(force_mdio_mv_bp_con) {
++			phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
++			phy_data->conn_type = XGBE_CONN_TYPE_MDIO;
++			netif_dbg(pdata, drv, pdata->netdev, "*** DEBUG: %s - bypass phydev_mode check\n", __func__);
++		} else {
++			return 0;
++		}
++	}
+ 
+ 	/* For SFP, only use an external PHY if available */
+ 	if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
+@@ -1011,7 +1023,7 @@ static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
+ 		return -ENODEV;
+ 	}
+ 	netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
+-		  phydev->phy_id);
++		 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45) ? phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] : phydev->phy_id);
+ 
+ 	/*TODO: If c45, add request_module based on one of the MMD ids? */
+ 
+@@ -1034,6 +1046,14 @@ static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
+ 
+ 	xgbe_phy_external_phy_quirks(pdata);
+ 
++	if(force_mdio_mv_bp_con) {
++		phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
++		phy_data->conn_type = XGBE_CONN_TYPE_BACKPLANE;
++		netif_dbg(pdata, drv, pdata->netdev, "phy_dev removed!\n");
++		xgbe_phy_free_phy_device(pdata);
++		return 0;
++	}
++
+ 	ethtool_convert_link_mode_to_legacy_u32(&advertising,
+ 						lks->link_modes.advertising);
+ 	phydev->advertising &= advertising;
+@@ -2551,8 +2571,10 @@ static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
+ 			return 0;
+ 
+ 		if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
+-		    !phy_aneg_done(phy_data->phydev))
++		    !phy_aneg_done(phy_data->phydev)) {
++			netif_dbg(pdata, drv, pdata->netdev,"%s Ext phy AN not complete!\n", __func__);
+ 			return 0;
++               }
+ 
+ 		if (!phy_data->phydev->link)
+ 			return 0;
+diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
+index f77a2d9e7f9d..080272a3d2b6 100644
+--- a/drivers/net/phy/marvell10g.c
++++ b/drivers/net/phy/marvell10g.c
+@@ -25,6 +25,7 @@
+ #include <linux/hwmon.h>
+ #include <linux/marvell_phy.h>
+ #include <linux/phy.h>
++#include <linux/delay.h>
+ 
+ enum {
+ 	MV_PCS_BASE_T		= 0x0000,
+@@ -48,7 +49,12 @@ enum {
+ 	MV_V2_TEMP_CTRL_MASK	= 0xc000,
+ 	MV_V2_TEMP_CTRL_SAMPLE	= 0x0000,
+ 	MV_V2_TEMP_CTRL_DISABLE	= 0xc000,
++	MV_V2_MODE_CFG		= 0xf000,
++	MV_V2_PORT_CTRL		= 0xf001,
++	MV_V2_LED0_CTRL		= 0xf020,
+ 	MV_V2_TEMP		= 0xf08c,
++	MV_V2_HOST_KR_ENABLE    = 0xf084,
++	MV_V2_HOST_KR_TUNE      = 0xf07c,
+ 	MV_V2_TEMP_UNKNOWN	= 0x9600, /* unknown function */
+ };
+ 
+@@ -75,7 +81,7 @@ static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,
+ 	return ret < 0 ? ret : 1;
+ }
+ 
+-#ifdef CONFIG_HWMON
++#ifdef CONFIG_HWMON_MV
+ static umode_t mv3310_hwmon_is_visible(const void *data,
+ 				       enum hwmon_sensor_types type,
+ 				       u32 attr, int channel)
+@@ -249,6 +255,77 @@ static int mv3310_resume(struct phy_device *phydev)
+ 	return mv3310_hwmon_config(phydev, true);
+ }
+ 
++
++/* Some PHYs within the Alaska family like 88x3310 has problems with the
++ * KR Auto-negotiation. marvell datasheet for 88x3310 section 6.2.11 says that
++ * KR auto-negotitaion can be enabled to adapt to the incoming SERDES by writing
++ * to autoneg registers and the PMA/PMD registers
++ */
++static int mv3310_amd_quirk(struct phy_device *phydev)
++{
++	int reg=0, count=0;
++	int version, subversion;
++
++	version = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 0xC011);
++	subversion = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 0xC012);
++	dev_dbg(&phydev->mdio.dev,"%s: Marvell FW Version: %x.%x \n", __func__, version, subversion);
++
++	if(subversion != 0x400)
++		return 0;
++
++	reg = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MV_V2_HOST_KR_ENABLE);
++	reg |= 0x8000;
++	phy_write_mmd(phydev, MDIO_MMD_PHYXS, MV_V2_HOST_KR_ENABLE, reg);
++
++	reg = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MV_V2_HOST_KR_TUNE);
++	reg = (reg & ~0x8000) | 0x4000;
++	phy_write_mmd(phydev, MDIO_MMD_PHYXS, MV_V2_HOST_KR_TUNE, reg);
++
++	if((reg & BIT(8)) && (reg & BIT(11))) {
++		reg = phy_read_mmd(phydev, MDIO_MMD_AN, MV_PCS_BASE_R);
++		/* disable BASE-R */
++		phy_write_mmd(phydev, MDIO_MMD_AN, MV_PCS_BASE_R, reg);
++	} else {
++		reg = phy_read_mmd(phydev, MDIO_MMD_AN, MV_PCS_BASE_R);
++		/* enable BASE-R for KR initiation */
++		reg |= 0x1000;
++		phy_write_mmd(phydev, MDIO_MMD_AN, MV_PCS_BASE_R, reg);
++	}
++
++	/* down the port if no link */
++	reg = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_MODE_CFG);
++	reg &= 0xFFF7;
++	phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_MODE_CFG, reg);
++
++	/* reset port to effect above change */
++	reg = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
++	reg |= 0x8000;
++	phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, reg);
++
++	/* wait till reset complete */
++	count = 50;
++	do {
++		msleep(10);
++		reg = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
++	} while ((reg & 0x8000) && --count);
++
++	if(reg & 0x8000){
++		dev_warn(&phydev->mdio.dev,"%s: Port Reset taking long time\n", __func__);
++		return -ETIMEDOUT;
++	}
++
++	/* LED0 Amber light On-Off settings [1:0]=01 */
++	reg = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_LED0_CTRL);
++	if((reg & 0x3) != 0x1) {
++		reg &= 0xFFFC;
++		reg |= 0x1;
++		phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_LED0_CTRL, reg);
++	}
++
++	dev_dbg(&phydev->mdio.dev,"%s: quirk applied\n", __func__);
++	return 0;
++}
++
+ static int mv3310_config_init(struct phy_device *phydev)
+ {
+ 	__ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
+@@ -274,6 +351,7 @@ static int mv3310_config_init(struct phy_device *phydev)
+ 			__set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported);
+ 	}
+ 
++	mv3310_amd_quirk(phydev);
+ 	val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
+ 	if (val < 0)
+ 		return val;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4104-Fix-hot-plug-failure-with-SFP-RJ45-module.-Do-force-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4104-Fix-hot-plug-failure-with-SFP-RJ45-module.-Do-force-.patch
new file mode 100644
index 00000000..9bbb1ee4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4104-Fix-hot-plug-failure-with-SFP-RJ45-module.-Do-force-.patch
@@ -0,0 +1,42 @@
+From e33b0e04ddd97a9ed4a04f001255fb23263cfa13 Mon Sep 17 00:00:00 2001
+From: Sudheer Anumolu <sudheer.anumolu@amd.com>
+Date: Tue, 26 Nov 2019 18:37:56 +0530
+Subject: [PATCH 4104/4736] Fix hot plug failure with SFP+RJ45 module. Do force
+ MDIO only if an external phy is available.
+
+---
+ drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
+index a6fb6754984f..3fcfd7cb04d6 100755
+--- a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
++++ b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
+@@ -989,6 +989,13 @@ static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
+ 	/* Clear the extra AN flag */
+ 	pdata->an_again = 0;
+ 
++	/* For SFP, only use an external PHY if available */
++	if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
++		force_mdio_mv_bp_con = 0;
++	    	if(!phy_data->sfp_phy_avail)
++			return 0;
++	}
++
+ 	/* Check for the use of an external PHY */
+ 	if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) {
+ 		if(force_mdio_mv_bp_con) {
+@@ -1000,10 +1007,6 @@ static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
+ 		}
+ 	}
+ 
+-	/* For SFP, only use an external PHY if available */
+-	if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
+-	    !phy_data->sfp_phy_avail)
+-		return 0;
+ 
+ 	/* Set the proper MDIO mode for the PHY */
+ 	ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4105-Reverting-enable-VCN-DPG-on-Raven-and-Raven2-due-to-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4105-Reverting-enable-VCN-DPG-on-Raven-and-Raven2-due-to-.patch
new file mode 100644
index 00000000..27db294f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4105-Reverting-enable-VCN-DPG-on-Raven-and-Raven2-due-to-.patch
@@ -0,0 +1,39 @@
+From d5b814c2e71b2bb51b3f24ef7fb0b5ea6e5f418c Mon Sep 17 00:00:00 2001
+From: Pavan Kumar Ramayanam <pavan.ramayanam@amd.com>
+Date: Fri, 29 Nov 2019 09:44:24 +0530
+Subject: [PATCH 4105/4736] Reverting enable VCN DPG on Raven and Raven2 due to
+ power efficiency degradation and hang issues
+
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 8 ++------
+ 1 file changed, 2 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 3acfdc1e2bfd..a77f9b708f7f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1121,9 +1121,7 @@ static int soc15_common_early_init(void *handle)
+ 				AMD_CG_SUPPORT_SDMA_LS |
+ 				AMD_CG_SUPPORT_VCN_MGCG;
+ 
+-			adev->pg_flags = AMD_PG_SUPPORT_SDMA |
+-				AMD_PG_SUPPORT_VCN |
+-				AMD_PG_SUPPORT_VCN_DPG;
++			adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
+ 		} else if (adev->pdev->device == 0x15d8) {
+ 			adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+ 				AMD_CG_SUPPORT_GFX_MGLS |
+@@ -1166,9 +1164,7 @@ static int soc15_common_early_init(void *handle)
+ 				AMD_CG_SUPPORT_SDMA_LS |
+ 				AMD_CG_SUPPORT_VCN_MGCG;
+ 
+-			adev->pg_flags = AMD_PG_SUPPORT_SDMA |
+-				AMD_PG_SUPPORT_VCN |
+-				AMD_PG_SUPPORT_VCN_DPG;
++			adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
+ 		}
+ 		break;
+ 	case CHIP_ARCTURUS:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4106-drm-amdgpu-sdma5-fix-mask-value-of-POLL_REGMEM-packe.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4106-drm-amdgpu-sdma5-fix-mask-value-of-POLL_REGMEM-packe.patch
new file mode 100644
index 00000000..9ea16d73
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4106-drm-amdgpu-sdma5-fix-mask-value-of-POLL_REGMEM-packe.patch
@@ -0,0 +1,30 @@
+From 55c838d55e504ca7834858d16a72f644adbb59d3 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 10 Oct 2019 01:01:23 +0800
+Subject: [PATCH 4106/4736] drm/amdgpu/sdma5: fix mask value of POLL_REGMEM
+ packet for pipe sync
+
+sdma will hang once sequence number to be polled reaches 0x1000_0000
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+index ad5c3566337c..3460c00f3eaa 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+@@ -1126,7 +1126,7 @@ static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
+ 	amdgpu_ring_write(ring, addr & 0xfffffffc);
+ 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
+ 	amdgpu_ring_write(ring, seq); /* reference */
+-	amdgpu_ring_write(ring, 0xfffffff); /* mask */
++	amdgpu_ring_write(ring, 0xffffffff); /* mask */
+ 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
+ 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4107-drm-amdgpu-powerplay-fix-typo-in-mvdd-table-setup.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4107-drm-amdgpu-powerplay-fix-typo-in-mvdd-table-setup.patch
new file mode 100644
index 00000000..6d8301bd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4107-drm-amdgpu-powerplay-fix-typo-in-mvdd-table-setup.patch
@@ -0,0 +1,50 @@
+From 6a850ace36127bc4ed674ce691f282c0aeeb930b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 2 Oct 2019 16:10:24 -0500
+Subject: [PATCH 4107/4736] drm/amdgpu/powerplay: fix typo in mvdd table setup
+
+Polaris and vegam use count for the value rather than
+level.  This looks like a copy paste typo from when
+the code was adapted from previous asics.
+
+I'm not sure that the SMU actually uses this value, so
+I don't know that it actually is a bug per se.
+
+Bug: https://bugs.freedesktop.org/show_bug.cgi?id=108609
+Reported-by: Robert Strube <rstrube@gmail.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 2 +-
+ drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c     | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+index a1a9f6196009..2ab589e33b7b 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+@@ -653,7 +653,7 @@ static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
+ 			count = SMU_MAX_SMIO_LEVELS;
+ 		for (level = 0; level < count; level++) {
+ 			table->SmioTable2.Pattern[level].Voltage =
+-				PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
++				PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE);
+ 			/* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
+ 			table->SmioTable2.Pattern[level].Smio =
+ 				(uint8_t) level;
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+index 7c960b07746f..ae18fbcb26fb 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+@@ -456,7 +456,7 @@ static int vegam_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
+ 			count = SMU_MAX_SMIO_LEVELS;
+ 		for (level = 0; level < count; level++) {
+ 			table->SmioTable2.Pattern[level].Voltage = PP_HOST_TO_SMC_US(
+-					data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
++					data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE);
+ 			/* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
+ 			table->SmioTable2.Pattern[level].Smio =
+ 				(uint8_t) level;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4108-drm-amdgpu-powerplay-Use-swap-where-appropriate.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4108-drm-amdgpu-powerplay-Use-swap-where-appropriate.patch
new file mode 100644
index 00000000..2c20817a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4108-drm-amdgpu-powerplay-Use-swap-where-appropriate.patch
@@ -0,0 +1,93 @@
+From 2fb67226c024d6c53c787651d548933ca91b9309 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Thu, 10 Oct 2019 16:11:58 +0300
+Subject: [PATCH 4108/4736] drm/amdgpu/powerplay: Use swap() where appropriate
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+@swap@
+identifier TEMP;
+expression A,B;
+@@
+- TEMP = A;
+- A = B;
+- B = TEMP;
++ swap(A, B);
+
+@@
+type T;
+identifier swap.TEMP;
+@@
+(
+- T TEMP;
+|
+- T TEMP = {...};
+)
+... when != TEMP
+
+Cc: Rex Zhu <rex.zhu@amd.com>
+Cc: Evan Quan <evan.quan@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: "Christian König" <christian.koenig@amd.com>
+Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com>
+Cc: amd-gfx@lists.freedesktop.org
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 6 ++----
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 6 ++----
+ 2 files changed, 4 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+index 25e68f245dba..897fd494fe33 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -1993,7 +1993,6 @@ static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr,
+ 		struct phm_ppt_v1_voltage_lookup_table *lookup_table)
+ {
+ 	uint32_t table_size, i, j;
+-	struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
+ 	table_size = lookup_table->count;
+ 
+ 	PP_ASSERT_WITH_CODE(0 != lookup_table->count,
+@@ -2004,9 +2003,8 @@ static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr,
+ 		for (j = i + 1; j > 0; j--) {
+ 			if (lookup_table->entries[j].us_vdd <
+ 					lookup_table->entries[j - 1].us_vdd) {
+-				tmp_voltage_lookup_record = lookup_table->entries[j - 1];
+-				lookup_table->entries[j - 1] = lookup_table->entries[j];
+-				lookup_table->entries[j] = tmp_voltage_lookup_record;
++				swap(lookup_table->entries[j - 1],
++				     lookup_table->entries[j]);
+ 			}
+ 		}
+ 	}
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+index ccceaba5914a..c31ef4262c9e 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+@@ -711,7 +711,6 @@ static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr,
+ 		struct phm_ppt_v1_voltage_lookup_table *lookup_table)
+ {
+ 	uint32_t table_size, i, j;
+-	struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
+ 
+ 	PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count,
+ 		"Lookup table is empty", return -EINVAL);
+@@ -723,9 +722,8 @@ static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr,
+ 		for (j = i + 1; j > 0; j--) {
+ 			if (lookup_table->entries[j].us_vdd <
+ 					lookup_table->entries[j - 1].us_vdd) {
+-				tmp_voltage_lookup_record = lookup_table->entries[j - 1];
+-				lookup_table->entries[j - 1] = lookup_table->entries[j];
+-				lookup_table->entries[j] = tmp_voltage_lookup_record;
++				swap(lookup_table->entries[j - 1],
++				     lookup_table->entries[j]);
+ 			}
+ 		}
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4109-drm-amdgpu-swSMU-navi-add-feature-toggles-for-more-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4109-drm-amdgpu-swSMU-navi-add-feature-toggles-for-more-t.patch
new file mode 100644
index 00000000..a68d1424
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4109-drm-amdgpu-swSMU-navi-add-feature-toggles-for-more-t.patch
@@ -0,0 +1,73 @@
+From 685533c7ed2d5c4ad8d10df1f5d8a4868f440309 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 9 Oct 2019 08:14:03 -0500
+Subject: [PATCH 4109/4736] drm/amdgpu/swSMU/navi: add feature toggles for more
+ things
+
+Add toggles for more power features.  Helpful in debugging.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 24 ++++++++++++++++------
+ 1 file changed, 18 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 68cbcc792ec1..52a2feef7893 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -327,11 +327,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
+ 	memset(feature_mask, 0, sizeof(uint32_t) * num);
+ 
+ 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
+-				| FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
+-				| FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
+ 				| FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
+-				| FEATURE_MASK(FEATURE_DPM_LINK_BIT)
+-				| FEATURE_MASK(FEATURE_GFX_ULV_BIT)
+ 				| FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
+ 				| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
+ 				| FEATURE_MASK(FEATURE_PPT_BIT)
+@@ -342,8 +338,6 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
+ 				| FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
+ 				| FEATURE_MASK(FEATURE_THERMAL_BIT)
+ 				| FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
+-				| FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
+-				| FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)
+ 				| FEATURE_MASK(FEATURE_DS_LCLK_BIT)
+ 				| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
+ 				| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
+@@ -354,11 +348,29 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
+ 				| FEATURE_MASK(FEATURE_FW_CTF_BIT)
+ 				| FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
+ 
++	if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
++		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
++
++	if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
++		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
++
++	if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
++		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
++
++	if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
++		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
++
+ 	if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
+ 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
+ 				| FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
+ 				| FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
+ 
++	if (adev->pm.pp_feature & PP_ULV_MASK)
++		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
++
++	if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
++		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
++
+ 	if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
+ 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
+ 		/* TODO: remove it once fw fix the bug */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4110-drm-amd-powerplay-enable-df-cstate-control-on-powerp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4110-drm-amd-powerplay-enable-df-cstate-control-on-powerp.patch
new file mode 100644
index 00000000..8804632e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4110-drm-amd-powerplay-enable-df-cstate-control-on-powerp.patch
@@ -0,0 +1,144 @@
+From 38ff634117407a29df3b641470f954694492b934 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 10 Oct 2019 11:34:51 +0800
+Subject: [PATCH 4110/4736] drm/amd/powerplay: enable df cstate control on
+ powerplay routine
+
+Currently this is only supported on Vega20 with 40.50 and later
+SMC firmware.
+
+Change-Id: I4f2f7936a3bc6e1a32d590bc76ebfc9a5a53f9cb
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ .../gpu/drm/amd/include/kgd_pp_interface.h    |  6 ++++++
+ drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 18 ++++++++++++++++++
+ .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c    | 19 +++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/inc/hwmgr.h     |  1 +
+ .../gpu/drm/amd/powerplay/inc/vega20_ppsmc.h  |  3 ++-
+ 5 files changed, 46 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+index 27cf0afaa0b4..5902f80d1fce 100644
+--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
++++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+@@ -179,6 +179,11 @@ enum pp_mp1_state {
+ 	PP_MP1_STATE_RESET,
+ };
+ 
++enum pp_df_cstate {
++	DF_CSTATE_DISALLOW = 0,
++	DF_CSTATE_ALLOW,
++};
++
+ #define PP_GROUP_MASK        0xF0000000
+ #define PP_GROUP_SHIFT       28
+ 
+@@ -312,6 +317,7 @@ struct amd_pm_funcs {
+ 	int (*get_ppfeature_status)(void *handle, char *buf);
+ 	int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
+ 	int (*asic_reset_mode_2)(void *handle);
++	int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
+ };
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+index fa8ad7db2b3a..83196b79edd5 100644
+--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+@@ -1548,6 +1548,23 @@ static int pp_smu_i2c_bus_access(void *handle, bool acquire)
+ 	return ret;
+ }
+ 
++static int pp_set_df_cstate(void *handle, enum pp_df_cstate state)
++{
++	struct pp_hwmgr *hwmgr = handle;
++
++	if (!hwmgr)
++		return -EINVAL;
++
++	if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_df_cstate)
++		return 0;
++
++	mutex_lock(&hwmgr->smu_lock);
++	hwmgr->hwmgr_func->set_df_cstate(hwmgr, state);
++	mutex_unlock(&hwmgr->smu_lock);
++
++	return 0;
++}
++
+ static const struct amd_pm_funcs pp_dpm_funcs = {
+ 	.load_firmware = pp_dpm_load_fw,
+ 	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
+@@ -1606,4 +1623,5 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
+ 	.set_ppfeature_status = pp_set_ppfeature_status,
+ 	.asic_reset_mode_2 = pp_asic_reset_mode_2,
+ 	.smu_i2c_bus_access = pp_smu_i2c_bus_access,
++	.set_df_cstate = pp_set_df_cstate,
+ };
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+index f5915308e643..6629c475fe5d 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+@@ -4155,6 +4155,24 @@ static int vega20_smu_i2c_bus_access(struct pp_hwmgr *hwmgr, bool acquire)
+ 	return res;
+ }
+ 
++static int vega20_set_df_cstate(struct pp_hwmgr *hwmgr,
++				enum pp_df_cstate state)
++{
++	int ret;
++
++	/* PPSMC_MSG_DFCstateControl is supported with 40.50 and later fws */
++	if (hwmgr->smu_version < 0x283200) {
++		pr_err("Df cstate control is supported with 40.50 and later SMC fw!\n");
++		return -EINVAL;
++	}
++
++	ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DFCstateControl, state);
++	if (ret)
++		pr_err("SetDfCstate failed!\n");
++
++	return ret;
++}
++
+ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
+ 	/* init/fini related */
+ 	.backend_init = vega20_hwmgr_backend_init,
+@@ -4223,6 +4241,7 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
+ 	.set_asic_baco_state = vega20_baco_set_state,
+ 	.set_mp1_state = vega20_set_mp1_state,
+ 	.smu_i2c_bus_access = vega20_smu_i2c_bus_access,
++	.set_df_cstate = vega20_set_df_cstate,
+ };
+ 
+ int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+index 7bf9a14bfa0b..bd8c922dfd3e 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+@@ -355,6 +355,7 @@ struct pp_hwmgr_func {
+ 	int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
+ 	int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
+ 	int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire);
++	int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state);
+ };
+ 
+ struct pp_table_func {
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
+index a0883038f3c3..0c66f0fe1aaf 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
+@@ -120,7 +120,8 @@
+ #define PPSMC_MSG_SetMGpuFanBoostLimitRpm        0x5D
+ #define PPSMC_MSG_GetAVFSVoltageByDpm            0x5F
+ #define PPSMC_MSG_BacoWorkAroundFlushVDCI        0x60
+-#define PPSMC_Message_Count                      0x61
++#define PPSMC_MSG_DFCstateControl                0x63
++#define PPSMC_Message_Count                      0x64
+ 
+ typedef uint32_t PPSMC_Result;
+ typedef uint32_t PPSMC_Msg;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4111-drm-amd-powerplay-enable-df-cstate-control-on-swSMU-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4111-drm-amd-powerplay-enable-df-cstate-control-on-swSMU-.patch
new file mode 100644
index 00000000..d777f677
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4111-drm-amd-powerplay-enable-df-cstate-control-on-swSMU-.patch
@@ -0,0 +1,138 @@
+From b3603c96916c7799c3efaf21bf9038ceca4fb521 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 10 Oct 2019 11:40:37 +0800
+Subject: [PATCH 4111/4736] drm/amd/powerplay: enable df cstate control on
+ swSMU routine
+
+Currently this is only supported on Vega20 with 40.50 and later
+SMC firmware.
+
+Change-Id: I8397f9ccc5dec32dc86ef7635c5ed227c77e61a3
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 23 +++++++++++++++++
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  3 +++
+ drivers/gpu/drm/amd/powerplay/inc/smu_types.h |  1 +
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 25 ++++++++++++++++++-
+ 4 files changed, 51 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 054376342454..a37a1b1d8abd 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1834,6 +1834,29 @@ int smu_set_mp1_state(struct smu_context *smu,
+ 	return ret;
+ }
+ 
++int smu_set_df_cstate(struct smu_context *smu,
++		      enum pp_df_cstate state)
++{
++	int ret = 0;
++
++	/*
++	 * The SMC is not fully ready. That may be
++	 * expected as the IP may be masked.
++	 * So, just return without error.
++	 */
++	if (!smu->pm_enabled)
++		return 0;
++
++	if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
++		return 0;
++
++	ret = smu->ppt_funcs->set_df_cstate(smu, state);
++	if (ret)
++		pr_err("[SetDfCstate] failed!\n");
++
++	return ret;
++}
++
+ const struct amd_ip_funcs smu_ip_funcs = {
+ 	.name = "smu",
+ 	.early_init = smu_early_init,
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index ccf711c327c8..401affdee49d 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -468,6 +468,7 @@ struct pptable_funcs {
+ 	int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool asic_default);
+ 	int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type clk_type,
+ 				   uint32_t dpm_level, uint32_t *freq);
++	int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
+ };
+ 
+ struct smu_funcs
+@@ -852,5 +853,7 @@ int smu_force_clk_levels(struct smu_context *smu,
+ 			 uint32_t mask);
+ int smu_set_mp1_state(struct smu_context *smu,
+ 		      enum pp_mp1_state mp1_state);
++int smu_set_df_cstate(struct smu_context *smu,
++		      enum pp_df_cstate state);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+index 12a1de55ce3c..d8c9b7f91fcc 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+@@ -169,6 +169,7 @@
+ 	__SMU_DUMMY_MAP(PowerGateAtHub),              \
+ 	__SMU_DUMMY_MAP(SetSoftMinJpeg),              \
+ 	__SMU_DUMMY_MAP(SetHardMinFclkByFreq),        \
++	__SMU_DUMMY_MAP(DFCstateControl), \
+ 
+ #undef __SMU_DUMMY_MAP
+ #define __SMU_DUMMY_MAP(type)	SMU_MSG_##type
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 99effde33ac1..1050566cb69a 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -143,6 +143,7 @@ static struct smu_11_0_cmn2aisc_mapping vega20_message_map[SMU_MSG_MAX_COUNT] =
+ 	MSG_MAP(PrepareMp1ForShutdown),
+ 	MSG_MAP(SetMGpuFanBoostLimitRpm),
+ 	MSG_MAP(GetAVFSVoltageByDpm),
++	MSG_MAP(DFCstateControl),
+ };
+ 
+ static struct smu_11_0_cmn2aisc_mapping vega20_clk_map[SMU_CLK_COUNT] = {
+@@ -3135,6 +3136,27 @@ static int vega20_get_thermal_temperature_range(struct smu_context *smu,
+ 	return 0;
+ }
+ 
++static int vega20_set_df_cstate(struct smu_context *smu,
++				enum pp_df_cstate state)
++{
++	uint32_t smu_version;
++	int ret;
++
++	ret = smu_get_smc_version(smu, NULL, &smu_version);
++	if (ret) {
++		pr_err("Failed to get smu version!\n");
++		return ret;
++	}
++
++	/* PPSMC_MSG_DFCstateControl is supported with 40.50 and later fws */
++	if (smu_version < 0x283200) {
++		pr_err("Df cstate control is supported with 40.50 and later SMC fw!\n");
++		return -EINVAL;
++	}
++
++	return smu_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state);
++}
++
+ static const struct pptable_funcs vega20_ppt_funcs = {
+ 	.tables_init = vega20_tables_init,
+ 	.alloc_dpm_context = vega20_allocate_dpm_context,
+@@ -3177,7 +3199,8 @@ static const struct pptable_funcs vega20_ppt_funcs = {
+ 	.get_fan_speed_percent = vega20_get_fan_speed_percent,
+ 	.get_fan_speed_rpm = vega20_get_fan_speed_rpm,
+ 	.set_watermarks_table = vega20_set_watermarks_table,
+-	.get_thermal_temperature_range = vega20_get_thermal_temperature_range
++	.get_thermal_temperature_range = vega20_get_thermal_temperature_range,
++	.set_df_cstate = vega20_set_df_cstate,
+ };
+ 
+ void vega20_set_ppt_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4112-drm-amdgpu-avoid-ras-error-injection-for-retired-pag.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4112-drm-amdgpu-avoid-ras-error-injection-for-retired-pag.patch
new file mode 100644
index 00000000..604ab73f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4112-drm-amdgpu-avoid-ras-error-injection-for-retired-pag.patch
@@ -0,0 +1,87 @@
+From 881a616e2e79841ce68a3cd7426a40f41c495a74 Mon Sep 17 00:00:00 2001
+From: Tao Zhou <tao.zhou1@amd.com>
+Date: Mon, 30 Sep 2019 14:48:19 +0800
+Subject: [PATCH 4112/4736] drm/amdgpu: avoid ras error injection for retired
+ page
+
+check whether a page is bad page before umc error injection, bad page
+should not be accessed again
+
+Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 44 +++++++++++++++++++++++++
+ 1 file changed, 44 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 18af80f1cffd..f3f3a98f93b3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -69,6 +69,9 @@ const char *ras_block_string[] = {
+ 
+ atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
+ 
++static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
++				uint64_t addr);
++
+ static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
+ 					size_t size, loff_t *pos)
+ {
+@@ -289,6 +292,14 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *
+ 			break;
+ 		}
+ 
++		/* umc ce/ue error injection for a bad page is not allowed */
++		if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
++		    amdgpu_ras_check_bad_page(adev, data.inject.address)) {
++			DRM_WARN("RAS WARN: 0x%llx has been marked as bad before error injection!\n",
++					data.inject.address);
++			break;
++		}
++
+ 		/* data.inject.address is offset instead of absolute gpu address */
+ 		ret = amdgpu_ras_error_inject(adev, &data.inject);
+ 		break;
+@@ -1429,6 +1440,39 @@ static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
+ 	return ret;
+ }
+ 
++/*
++ * check if an address belongs to bad page
++ *
++ * Note: this check is only for umc block
++ */
++static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
++				uint64_t addr)
++{
++	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
++	struct ras_err_handler_data *data;
++	int i;
++	bool ret = false;
++
++	if (!con || !con->eh_data)
++		return ret;
++
++	mutex_lock(&con->recovery_lock);
++	data = con->eh_data;
++	if (!data)
++		goto out;
++
++	addr >>= AMDGPU_GPU_PAGE_SHIFT;
++	for (i = 0; i < data->count; i++)
++		if (addr == data->bps[i].retired_page) {
++			ret = true;
++			goto out;
++		}
++
++out:
++	mutex_unlock(&con->recovery_lock);
++	return ret;
++}
++
+ /* called in gpu recovery/init */
+ int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
+ {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4113-drm-amdgpu-fix-memory-leak.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4113-drm-amdgpu-fix-memory-leak.patch
new file mode 100644
index 00000000..e8a01f08
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4113-drm-amdgpu-fix-memory-leak.patch
@@ -0,0 +1,68 @@
+From 6ab8eec947ae191bede5fc2d9b9208a82a55196c Mon Sep 17 00:00:00 2001
+From: Nirmoy Das <nirmoy.das@amd.com>
+Date: Fri, 4 Oct 2019 11:53:37 +0200
+Subject: [PATCH 4113/4736] drm/amdgpu: fix memory leak
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+cleanup error handling code and make sure temporary info array
+with the handles are freed by amdgpu_bo_list_put() on
+idr_replace()'s failure.
+
+Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+index ea05784624ed..e143d9e110bd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+@@ -270,7 +270,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
+ 
+ 	r = amdgpu_bo_create_list_entry_array(&args->in, &info);
+ 	if (r)
+-		goto error_free;
++		return r;
+ 
+ 	switch (args->in.operation) {
+ 	case AMDGPU_BO_LIST_OP_CREATE:
+@@ -283,8 +283,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
+ 		r = idr_alloc(&fpriv->bo_list_handles, list, 1, 0, GFP_KERNEL);
+ 		mutex_unlock(&fpriv->bo_list_lock);
+ 		if (r < 0) {
+-			amdgpu_bo_list_put(list);
+-			return r;
++			goto error_put_list;
+ 		}
+ 
+ 		handle = r;
+@@ -306,9 +305,8 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
+ 		mutex_unlock(&fpriv->bo_list_lock);
+ 
+ 		if (IS_ERR(old)) {
+-			amdgpu_bo_list_put(list);
+ 			r = PTR_ERR(old);
+-			goto error_free;
++			goto error_put_list;
+ 		}
+ 
+ 		amdgpu_bo_list_put(old);
+@@ -325,8 +323,10 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
+ 
+ 	return 0;
+ 
++error_put_list:
++	amdgpu_bo_list_put(list);
++
+ error_free:
+-	if (info)
+-		kvfree(info);
++	kvfree(info);
+ 	return r;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4114-drm-HDMI-and-DP-specific-HDCP2.2-defines.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4114-drm-HDMI-and-DP-specific-HDCP2.2-defines.patch
new file mode 100644
index 00000000..ec27a9f0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4114-drm-HDMI-and-DP-specific-HDCP2.2-defines.patch
@@ -0,0 +1,138 @@
+From e2eaca86311ae7819b9b62f77287bd1165d0a6f9 Mon Sep 17 00:00:00 2001
+From: Ramalingam C <ramalingam.c@intel.com>
+Date: Mon, 29 Oct 2018 15:15:50 +0530
+Subject: [PATCH 4114/4736] drm: HDMI and DP specific HDCP2.2 defines
+
+This patch adds HDCP register definitions for HDMI and DP HDCP
+adaptations.
+
+HDMI specific HDCP2.2 register definitions are added into drm_hdcp.h,
+where as HDCP2.2 register offsets in DPCD offsets are defined at
+drm_dp_helper.h.
+
+v2:
+  bit_field definitions are replaced by macros. [Tomas and Jani]
+v3:
+  No Changes.
+v4:
+  Comments style and typos are fixed [Uma]
+v5:
+  Fix for macros.
+v6:
+  Adds _MS to the timeouts to represent units [Sean Paul]
+v7:
+  Macro DP_HDCP_2_2_REG_EKH_KM_OFFSET renamed [Uma]
+  Redundant macro is removed [Uma]
+
+Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
+Reviewed-by: Sean Paul <seanpaul@chromium.org>
+Acked-by: Sean Paul <seanpaul@chromium.org> (for merging through drm-intel)
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Link: https://patchwork.freedesktop.org/patch/msgid/1540806351-7137-6-git-send-email-ramalingam.c@intel.com
+---
+ include/drm/drm_dp_helper.h | 51 +++++++++++++++++++++++++++++++++++++
+ include/drm/drm_hdcp.h      | 28 ++++++++++++++++++++
+ 2 files changed, 79 insertions(+)
+
+diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
+index b81ec228ab8e..432e93ac3b3c 100644
+--- a/include/drm/drm_dp_helper.h
++++ b/include/drm/drm_dp_helper.h
+@@ -913,6 +913,57 @@
+ #define DP_AUX_HDCP_KSV_FIFO		0x6802C
+ #define DP_AUX_HDCP_AINFO		0x6803B
+ 
++/* DP HDCP2.2 parameter offsets in DPCD address space */
++#define DP_HDCP_2_2_REG_RTX_OFFSET		0x69000
++#define DP_HDCP_2_2_REG_TXCAPS_OFFSET		0x69008
++#define DP_HDCP_2_2_REG_CERT_RX_OFFSET		0x6900B
++#define DP_HDCP_2_2_REG_RRX_OFFSET		0x69215
++#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET		0x6921D
++#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET		0x69220
++#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET	0x692A0
++#define DP_HDCP_2_2_REG_M_OFFSET		0x692B0
++#define DP_HDCP_2_2_REG_HPRIME_OFFSET		0x692C0
++#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET	0x692E0
++#define DP_HDCP_2_2_REG_RN_OFFSET		0x692F0
++#define DP_HDCP_2_2_REG_LPRIME_OFFSET		0x692F8
++#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET		0x69318
++#define	DP_HDCP_2_2_REG_RIV_OFFSET		0x69328
++#define DP_HDCP_2_2_REG_RXINFO_OFFSET		0x69330
++#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET	0x69332
++#define DP_HDCP_2_2_REG_VPRIME_OFFSET		0x69335
++#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET	0x69345
++#define DP_HDCP_2_2_REG_V_OFFSET		0x693E0
++#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET	0x693F0
++#define DP_HDCP_2_2_REG_K_OFFSET		0x693F3
++#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET	0x693F5
++#define DP_HDCP_2_2_REG_MPRIME_OFFSET		0x69473
++#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET		0x69493
++#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET	0x69494
++#define DP_HDCP_2_2_REG_DBG_OFFSET		0x69518
++
++/* DP HDCP message start offsets in DPCD address space */
++#define DP_HDCP_2_2_AKE_INIT_OFFSET		DP_HDCP_2_2_REG_RTX_OFFSET
++#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET	DP_HDCP_2_2_REG_CERT_RX_OFFSET
++#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET	DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
++#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET	DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
++#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET	DP_HDCP_2_2_REG_HPRIME_OFFSET
++#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
++						DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
++#define DP_HDCP_2_2_LC_INIT_OFFSET		DP_HDCP_2_2_REG_RN_OFFSET
++#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET	DP_HDCP_2_2_REG_LPRIME_OFFSET
++#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET		DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
++#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET	DP_HDCP_2_2_REG_RXINFO_OFFSET
++#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET		DP_HDCP_2_2_REG_V_OFFSET
++#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET	DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
++#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET	DP_HDCP_2_2_REG_MPRIME_OFFSET
++
++#define HDCP_2_2_DP_RXSTATUS_LEN		1
++#define HDCP_2_2_DP_RXSTATUS_READY(x)		((x) & BIT(0))
++#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x)		((x) & BIT(1))
++#define HDCP_2_2_DP_RXSTATUS_PAIRING(x)		((x) & BIT(2))
++#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x)	((x) & BIT(3))
++#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x)	((x) & BIT(4))
++
+ /* DP 1.2 Sideband message defines */
+ /* peer device type - DP 1.2a Table 2-92 */
+ #define DP_PEER_DEVICE_NONE		0x0
+diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
+index 98e63d870139..5e93faaa7015 100644
+--- a/include/drm/drm_hdcp.h
++++ b/include/drm/drm_hdcp.h
+@@ -38,4 +38,32 @@
+ #define DRM_HDCP_DDC_BSTATUS			0x41
+ #define DRM_HDCP_DDC_KSV_FIFO			0x43
+ 
++/* HDCP2.2 TIMEOUTs in mSec */
++#define HDCP_2_2_CERT_TIMEOUT_MS		100
++#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS	1000
++#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS	200
++#define HDCP_2_2_PAIRING_TIMEOUT_MS		200
++#define	HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS		20
++#define HDCP_2_2_DP_LPRIME_TIMEOUT_MS		7
++#define HDCP_2_2_RECVID_LIST_TIMEOUT_MS		3000
++#define HDCP_2_2_STREAM_READY_TIMEOUT_MS	100
++
++/* HDMI HDCP2.2 Register Offsets */
++#define HDCP_2_2_HDMI_REG_VER_OFFSET		0x50
++#define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET		0x60
++#define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET	0x70
++#define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET		0x80
++#define HDCP_2_2_HDMI_REG_DBG_OFFSET		0xC0
++
++#define HDCP_2_2_HDMI_SUPPORT_MASK		BIT(2)
++#define HDCP_2_2_RX_CAPS_VERSION_VAL		0x02
++#define HDCP_2_2_SEQ_NUM_MAX			0xFFFFFF
++#define	HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN	200
++
++/* Below macros take a byte at a time and mask the bit(s) */
++#define HDCP_2_2_HDMI_RXSTATUS_LEN		2
++#define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x)	((x) & 0x3)
++#define HDCP_2_2_HDMI_RXSTATUS_READY(x)		((x) & BIT(2))
++#define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x)	((x) & BIT(3))
++
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4115-drm-Add-link-training-repeaters-addresses.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4115-drm-Add-link-training-repeaters-addresses.patch
new file mode 100644
index 00000000..3c5430bb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4115-drm-Add-link-training-repeaters-addresses.patch
@@ -0,0 +1,86 @@
+From 274e6cebf8d87f79c433c4d13ce82eb1d549aad3 Mon Sep 17 00:00:00 2001
+From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Date: Mon, 9 Sep 2019 21:21:47 +0000
+Subject: [PATCH 4115/4736] drm: Add link training repeaters addresses
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+DP 1.3 specification introduces the Link Training-tunable PHY Repeater,
+and DP 1.4* supplemented it with new features. In the 1.4a spec, it was
+introduced some innovations to make handy to add support for systems
+with Thunderbolt or other repeater devices.
+
+It is important to highlight that DP specification had some updates from
+1.3 through 1.4a. In particular, DP 1.4 defines Repeater_FEC_CAPABILITY
+at the address 0xf0004, and DP 1.4a redefined the address 0xf0004 to
+DP_MAX_LANE_COUNT_PHY_REPEATER.
+
+Changes since V4:
+- Update commit message
+- Fix misleading comments related to the spec version
+Changes since V3:
+- Replace spaces by tabs
+Changes since V2:
+- Drop the kernel-doc comment
+- Reorder LTTPR according to register offset
+Changes since V1:
+- Adjusts registers names to be aligned with spec and the rest of the
+  file
+- Update spec comment from 1.4 to 1.4a
+
+Cc: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com>
+Cc: Harry Wentland <harry.wentland@amd.com>
+Cc: Leo Li <sunpeng.li@amd.com>
+Cc: Jani Nikula <jani.nikula@linux.intel.com>
+Cc: Manasi Navare <manasi.d.navare@intel.com>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Signed-off-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com>
+Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
+Signed-off-by: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190909212144.deeomlsqihwg4l3y@outlook.office365.com
+---
+ include/drm/drm_dp_helper.h | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
+index 432e93ac3b3c..b2a2c92ac67c 100644
+--- a/include/drm/drm_dp_helper.h
++++ b/include/drm/drm_dp_helper.h
+@@ -941,6 +941,32 @@
+ #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET	0x69494
+ #define DP_HDCP_2_2_REG_DBG_OFFSET		0x69518
+ 
++/* Link Training (LT)-tunable PHY Repeaters */
++#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
++#define DP_MAX_LINK_RATE_PHY_REPEATER			    0xf0001 /* 1.4a */
++#define DP_PHY_REPEATER_CNT				    0xf0002 /* 1.3 */
++#define DP_PHY_REPEATER_MODE				    0xf0003 /* 1.3 */
++#define DP_MAX_LANE_COUNT_PHY_REPEATER			    0xf0004 /* 1.4a */
++#define DP_Repeater_FEC_CAPABILITY			    0xf0004 /* 1.4 */
++#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT		    0xf0005 /* 1.4a */
++#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1		    0xf0010 /* 1.3 */
++#define DP_TRAINING_LANE0_SET_PHY_REPEATER1		    0xf0011 /* 1.3 */
++#define DP_TRAINING_LANE1_SET_PHY_REPEATER1		    0xf0012 /* 1.3 */
++#define DP_TRAINING_LANE2_SET_PHY_REPEATER1		    0xf0013 /* 1.3 */
++#define DP_TRAINING_LANE3_SET_PHY_REPEATER1		    0xf0014 /* 1.3 */
++#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1	    0xf0020 /* 1.4a */
++#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1		    0xf0021 /* 1.4a */
++#define DP_LANE0_1_STATUS_PHY_REPEATER1			    0xf0030 /* 1.3 */
++#define DP_LANE2_3_STATUS_PHY_REPEATER1			    0xf0031 /* 1.3 */
++#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1	    0xf0032 /* 1.3 */
++#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1		    0xf0033 /* 1.3 */
++#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1		    0xf0034 /* 1.3 */
++#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1	    0xf0035 /* 1.3 */
++#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1	    0xf0037 /* 1.3 */
++#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1	    0xf0039 /* 1.3 */
++#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1	    0xf003b /* 1.3 */
++#define DP_FEC_STATUS_PHY_REPEATER1			    0xf0290 /* 1.4 */
++
+ /* DP HDCP message start offsets in DPCD address space */
+ #define DP_HDCP_2_2_AKE_INIT_OFFSET		DP_HDCP_2_2_REG_RTX_OFFSET
+ #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET	DP_HDCP_2_2_REG_CERT_RX_OFFSET
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4116-drm-amdkfd-update-for-drmP.h-removal.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4116-drm-amdkfd-update-for-drmP.h-removal.patch
new file mode 100644
index 00000000..b590044a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4116-drm-amdkfd-update-for-drmP.h-removal.patch
@@ -0,0 +1,37 @@
+From c9926ea4a27022847c208c12d17c6b90206d71f1 Mon Sep 17 00:00:00 2001
+From: Stephen Rothwell <sfr@canb.auug.org.au>
+Date: Wed, 9 Oct 2019 11:35:57 +1100
+Subject: [PATCH 4116/4736] drm/amdkfd: update for drmP.h removal
+
+Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index f856c14a6ed0..e7913212c1f6 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -40,6 +40,9 @@
+ #include <linux/interval_tree.h>
+ #include <linux/device_cgroup.h>
+ #include <drm/drmP.h>
++#include <drm/drm_file.h>
++#include <drm/drm_drv.h>
++#include <drm/drm_device.h>
+ #include <kgd_kfd_interface.h>
+ 
+ #include "amd_shared.h"
+@@ -51,8 +54,6 @@
+ /* GPU ID hash width in bits */
+ #define KFD_GPU_ID_HASH_WIDTH 16
+ 
+-struct drm_device;
+-
+ /* Use upper bits of mmap offset to store KFD driver specific information.
+  * BITS[63:62] - Encode MMAP type
+  * BITS[61:46] - Encode gpu_id. To identify to which GPU the offset belongs to
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4117-drm-amdgpu-Do-not-implement-power-on-for-SDMA-after-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4117-drm-amdgpu-Do-not-implement-power-on-for-SDMA-after-.patch
new file mode 100644
index 00000000..3bdc66a4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4117-drm-amdgpu-Do-not-implement-power-on-for-SDMA-after-.patch
@@ -0,0 +1,35 @@
+From a6ee800e9b828b18b24f685e85de0aa79ee36fcb Mon Sep 17 00:00:00 2001
+From: chen gong <curry.gong@amd.com>
+Date: Sun, 29 Sep 2019 10:58:43 +0800
+Subject: [PATCH 4117/4736] drm/amdgpu: Do not implement power-on for SDMA
+ after do mode2 reset on Renoir
+
+Find that ring sdma0 test failed if turn on SDMA powergating after do
+mode2 reset.
+
+Perhaps the mode2 reset does not reset the SDMA PG state, SDMA is
+already powered up so there is no need to ask the SMU to power it up
+again. So I skip this function for a moment.
+
+Signed-off-by: chen gong <curry.gong@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 26f13de35b2c..78e21c12c17a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1792,7 +1792,7 @@ static int sdma_v4_0_hw_init(void *handle)
+ 
+ 	if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs &&
+ 			adev->powerplay.pp_funcs->set_powergating_by_smu) ||
+-			adev->asic_type == CHIP_RENOIR)
++			(adev->asic_type == CHIP_RENOIR && !adev->in_gpu_reset))
+ 		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
+ 
+ 	if (!amdgpu_sriov_vf(adev))
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4118-drm-amdgpu-discovery-reserve-discovery-data-at-the-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4118-drm-amdgpu-discovery-reserve-discovery-data-at-the-t.patch
new file mode 100644
index 00000000..9b42282e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4118-drm-amdgpu-discovery-reserve-discovery-data-at-the-t.patch
@@ -0,0 +1,122 @@
+From 34c14c75f78c119fe8a7e2c666131a225710fd72 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 10 Oct 2019 20:44:20 +0800
+Subject: [PATCH 4118/4736] drm/amdgpu/discovery: reserve discovery data at the
+ top of VRAM
+
+IP Discovery data is TMR fenced by the latest PSP BL,
+so we need to reserve this region.
+
+Tested on navi10/12/14 with VBIOS integrated with latest PSP BL.
+
+v2: use DISCOVERY_TMR_SIZE macro as bo size
+    use amdgpu_bo_create_kernel_at() to allocate bo
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h           |  1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c |  4 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h |  2 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c       | 17 +++++++++++++++++
+ drivers/gpu/drm/amd/include/discovery.h       |  1 -
+ 5 files changed, 22 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 3bb4b7c6a42d..a994117c4edc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -799,6 +799,7 @@ struct amdgpu_device {
+ 	uint8_t				*bios;
+ 	uint32_t			bios_size;
+ 	struct amdgpu_bo		*stolen_vga_memory;
++	struct amdgpu_bo		*discovery_memory;
+ 	uint32_t			bios_scratch_reg_offset;
+ 	uint32_t			bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+index 1481899f86c1..71198c5318e1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+@@ -136,7 +136,7 @@ static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *bin
+ {
+ 	uint32_t *p = (uint32_t *)binary;
+ 	uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
+-	uint64_t pos = vram_size - BINARY_MAX_SIZE;
++	uint64_t pos = vram_size - DISCOVERY_TMR_SIZE;
+ 	unsigned long flags;
+ 
+ 	while (pos < vram_size) {
+@@ -179,7 +179,7 @@ int amdgpu_discovery_init(struct amdgpu_device *adev)
+ 	uint16_t checksum;
+ 	int r;
+ 
+-	adev->discovery = kzalloc(BINARY_MAX_SIZE, GFP_KERNEL);
++	adev->discovery = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL);
+ 	if (!adev->discovery)
+ 		return -ENOMEM;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
+index 85b8c4d4d576..5a6693d7d269 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
+@@ -24,6 +24,8 @@
+ #ifndef __AMDGPU_DISCOVERY__
+ #define __AMDGPU_DISCOVERY__
+ 
++#define DISCOVERY_TMR_SIZE  (64 << 10)
++
+ int amdgpu_discovery_init(struct amdgpu_device *adev);
+ void amdgpu_discovery_fini(struct amdgpu_device *adev);
+ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 87284e8c8ece..0c1af24f8bc0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -2063,6 +2063,20 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
+ 				    NULL, &stolen_vga_buf);
+ 	if (r)
+ 		return r;
++
++	/*
++	 * reserve one TMR (64K) memory at the top of VRAM which holds
++	 * IP Discovery data and is protected by PSP.
++	 */
++	r = amdgpu_bo_create_kernel_at(adev,
++				       adev->gmc.real_vram_size - DISCOVERY_TMR_SIZE,
++				       DISCOVERY_TMR_SIZE,
++				       AMDGPU_GEM_DOMAIN_VRAM,
++				       &adev->discovery_memory,
++				       NULL);
++	if (r)
++		return r;
++
+ 	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
+ 		 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
+ 
+@@ -2132,6 +2146,9 @@ void amdgpu_ttm_late_init(struct amdgpu_device *adev)
+ 	void *stolen_vga_buf;
+ 	/* return the VGA stolen memory (if any) back to VRAM */
+ 	amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
++
++	/* return the IP Discovery TMR memory back to VRAM */
++	amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
+ }
+ 
+ /**
+diff --git a/drivers/gpu/drm/amd/include/discovery.h b/drivers/gpu/drm/amd/include/discovery.h
+index 5dcb776548d8..7ec4331e67f2 100644
+--- a/drivers/gpu/drm/amd/include/discovery.h
++++ b/drivers/gpu/drm/amd/include/discovery.h
+@@ -25,7 +25,6 @@
+ #define _DISCOVERY_H_
+ 
+ #define PSP_HEADER_SIZE                 256
+-#define BINARY_MAX_SIZE                 (64 << 10)
+ #define BINARY_SIGNATURE                0x28211407
+ #define DISCOVERY_TABLE_SIGNATURE       0x53445049
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4119-drm-amd-display-Use-swap-where-appropriate.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4119-drm-amd-display-Use-swap-where-appropriate.patch
new file mode 100644
index 00000000..c3713e34
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4119-drm-amd-display-Use-swap-where-appropriate.patch
@@ -0,0 +1,122 @@
+From 5c9a30d8d57a134edb1e491aefc4b53f73335305 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Thu, 10 Oct 2019 16:11:57 +0300
+Subject: [PATCH 4119/4736] drm/amd/display: Use swap() where appropriate
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Mostly a cocci-job, but it flat out refused to remove the
+declaration in drivers/gpu/drm/amd/display/dc/core/dc.c so
+had to do that part manually.
+
+@swap@
+identifier TEMP;
+expression A,B;
+@@
+- TEMP = A;
+- A = B;
+- B = TEMP;
++ swap(A, B);
+
+@@
+type T;
+identifier swap.TEMP;
+@@
+(
+- T TEMP;
+|
+- T TEMP = {...};
+)
+... when != TEMP
+
+Cc: Harry Wentland <harry.wentland@amd.com>
+Cc: Leo Li <sunpeng.li@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: "Christian König" <christian.koenig@amd.com>
+Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com>
+Cc: amd-gfx@lists.freedesktop.org
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser.c  | 7 ++-----
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 8 ++------
+ drivers/gpu/drm/amd/display/dc/core/dc.c           | 6 +-----
+ 3 files changed, 5 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+index 207f6084525c..7466e6332299 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+@@ -2541,7 +2541,6 @@ static enum bp_result construct_integrated_info(
+ 
+ 	/* Sort voltage table from low to high*/
+ 	if (result == BP_RESULT_OK) {
+-		struct clock_voltage_caps temp = {0, 0};
+ 		uint32_t i;
+ 		uint32_t j;
+ 
+@@ -2551,10 +2550,8 @@ static enum bp_result construct_integrated_info(
+ 						info->disp_clk_voltage[j].max_supported_clk <
+ 						info->disp_clk_voltage[j-1].max_supported_clk) {
+ 					/* swap j and j - 1*/
+-					temp = info->disp_clk_voltage[j-1];
+-					info->disp_clk_voltage[j-1] =
+-							info->disp_clk_voltage[j];
+-					info->disp_clk_voltage[j] = temp;
++					swap(info->disp_clk_voltage[j - 1],
++					     info->disp_clk_voltage[j]);
+ 				}
+ 			}
+ 		}
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index c9f65c4df530..b4bbfb7bde12 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -1611,8 +1611,6 @@ static enum bp_result construct_integrated_info(
+ 
+ 	struct atom_common_table_header *header;
+ 	struct atom_data_revision revision;
+-
+-	struct clock_voltage_caps temp = {0, 0};
+ 	uint32_t i;
+ 	uint32_t j;
+ 
+@@ -1642,10 +1640,8 @@ static enum bp_result construct_integrated_info(
+ 				info->disp_clk_voltage[j-1].max_supported_clk
+ 				) {
+ 				/* swap j and j - 1*/
+-				temp = info->disp_clk_voltage[j-1];
+-				info->disp_clk_voltage[j-1] =
+-					info->disp_clk_voltage[j];
+-				info->disp_clk_voltage[j] = temp;
++				swap(info->disp_clk_voltage[j - 1],
++				     info->disp_clk_voltage[j]);
+ 			}
+ 		}
+ 	}
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 7142c014502a..699a215ca8ce 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -936,15 +936,11 @@ static void program_timing_sync(
+ 
+ 		/* set first pipe with plane as master */
+ 		for (j = 0; j < group_size; j++) {
+-			struct pipe_ctx *temp;
+-
+ 			if (pipe_set[j]->plane_state) {
+ 				if (j == 0)
+ 					break;
+ 
+-				temp = pipe_set[0];
+-				pipe_set[0] = pipe_set[j];
+-				pipe_set[j] = temp;
++				swap(pipe_set[0], pipe_set[j]);
+ 				break;
+ 			}
+ 		}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4120-drm-amdgpu-display-clean-up-dcn2-_pp_smu-functions.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4120-drm-amdgpu-display-clean-up-dcn2-_pp_smu-functions.patch
new file mode 100644
index 00000000..1b2718c3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4120-drm-amdgpu-display-clean-up-dcn2-_pp_smu-functions.patch
@@ -0,0 +1,88 @@
+From 363163a7abaed056e01ce4019c9b449a80fb588d Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 10 Oct 2019 10:07:40 -0500
+Subject: [PATCH 4120/4736] drm/amdgpu/display: clean up dcn2*_pp_smu functions
+
+Use the dcn21 functions in dcn21_resource.c and make the
+dcn20 functions static since they are only used in
+dcn20_resource now.
+
+Cc: bhawanpreet.lakha@amd.com
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 6 ++++--
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h | 3 ---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 4 +++-
+ 3 files changed, 7 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 4ca819c223bd..968dc5fe4f1b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1185,6 +1185,8 @@ static const struct resource_create_funcs res_create_maximus_funcs = {
+ 	.create_hwseq = dcn20_hwseq_create,
+ };
+ 
++static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
++
+ void dcn20_clock_source_destroy(struct clock_source **clk_src)
+ {
+ 	kfree(TO_DCE110_CLK_SRC(*clk_src));
+@@ -2959,7 +2961,7 @@ bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
+ 	return true;
+ }
+ 
+-struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
++static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
+ {
+ 	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
+ 
+@@ -2974,7 +2976,7 @@ struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
+ 	return pp_smu;
+ }
+ 
+-void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
++static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
+ {
+ 	if (pp_smu && *pp_smu) {
+ 		kfree(*pp_smu);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+index 44f95aa0d61e..55006462f481 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+@@ -95,9 +95,6 @@ struct display_stream_compressor *dcn20_dsc_create(
+ 	struct dc_context *ctx, uint32_t inst);
+ void dcn20_dsc_destroy(struct display_stream_compressor **dsc);
+ 
+-struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx);
+-void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
+-
+ struct hubp *dcn20_hubp_create(
+ 	struct dc_context *ctx,
+ 	uint32_t inst);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 9fdfa213b47c..2cc93e2e6ec0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -636,6 +636,8 @@ static const struct dcn10_stream_encoder_mask se_mask = {
+ 		SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
+ };
+ 
++static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
++
+ static struct input_pixel_processor *dcn21_ipp_create(
+ 	struct dc_context *ctx, uint32_t inst)
+ {
+@@ -939,7 +941,7 @@ static void destruct(struct dcn21_resource_pool *pool)
+ 		dcn_dccg_destroy(&pool->base.dccg);
+ 
+ 	if (pool->base.pp_smu != NULL)
+-		dcn20_pp_smu_destroy(&pool->base.pp_smu);
++		dcn21_pp_smu_destroy(&pool->base.pp_smu);
+ }
+ 
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4121-drm-amd-powerplay-re-enable-FW_DSTATE-feature-bit.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4121-drm-amd-powerplay-re-enable-FW_DSTATE-feature-bit.patch
new file mode 100644
index 00000000..b8cb80d7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4121-drm-amd-powerplay-re-enable-FW_DSTATE-feature-bit.patch
@@ -0,0 +1,34 @@
+From 7380d973669042490c0d393daa5e972b5dc0ed09 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 9 Oct 2019 18:52:51 +0800
+Subject: [PATCH 4121/4736] drm/amd/powerplay: re-enable FW_DSTATE feature bit
+
+SMU firmware has fix the bug, so remove this workaround.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 +----
+ 1 file changed, 1 insertion(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 52a2feef7893..e8e5c889cc95 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -371,11 +371,8 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
+ 	if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
+ 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
+ 
+-	if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
++	if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+ 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
+-		/* TODO: remove it once fw fix the bug */
+-		*(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
+-	}
+ 
+ 	if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
+ 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4122-drm-amdgpu-soc15-disable-doorbell-interrupt-as-part-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4122-drm-amdgpu-soc15-disable-doorbell-interrupt-as-part-.patch
new file mode 100644
index 00000000..451dd4bb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4122-drm-amdgpu-soc15-disable-doorbell-interrupt-as-part-.patch
@@ -0,0 +1,91 @@
+From 7bf9158b5981fbca65e8819df93fb2fc721c95bd Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 11 Oct 2019 18:21:16 +0800
+Subject: [PATCH 4122/4736] drm/amdgpu/soc15: disable doorbell interrupt as
+ part of BACO entry sequence
+
+Workaround to make RAS recovery work in BACO reset.
+
+Change-Id: I4e4a81f719dcc88dfd49f583c4be3a373b5eab2c
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 ++
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c   | 8 ++++++++
+ drivers/gpu/drm/amd/amdgpu/soc15.c       | 9 +++++++++
+ 3 files changed, 19 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+index 1f26a17e6561..919bd566ba3c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+@@ -67,6 +67,8 @@ struct amdgpu_nbio_funcs {
+ 						  bool enable);
+ 	void (*ih_doorbell_range)(struct amdgpu_device *adev,
+ 				  bool use_doorbell, int doorbell_index);
++	void (*enable_doorbell_interrupt)(struct amdgpu_device *adev,
++					  bool enable);
+ 	void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
+ 						 bool enable);
+ 	void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index 238c2483496a..0db458f9fafc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -502,6 +502,13 @@ static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
+ 	}
+ }
+ 
++static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev,
++						bool enable)
++{
++	WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL,
++		       DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
++}
++
+ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ 	.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
+ 	.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
+@@ -516,6 +523,7 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
+ 	.enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
+ 	.enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture,
+ 	.ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
++	.enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt,
+ 	.update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating,
+ 	.update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep,
+ 	.get_clockgating_state = nbio_v7_4_get_clockgating_state,
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index a77f9b708f7f..82b5bc4ddf9b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -492,10 +492,15 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+ {
+ 	void *pp_handle = adev->powerplay.pp_handle;
+ 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
++	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+ 
+ 	if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
+ 		return -ENOENT;
+ 
++	/* avoid NBIF got stuck when do RAS recovery in BACO reset */
++	if (ras && ras->supported)
++		adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
++
+ 	/* enter BACO state */
+ 	if (pp_funcs->set_asic_baco_state(pp_handle, 1))
+ 		return -EIO;
+@@ -504,6 +509,10 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+ 	if (pp_funcs->set_asic_baco_state(pp_handle, 0))
+ 		return -EIO;
+ 
++	/* re-enable doorbell interrupt after BACO exit */
++	if (ras && ras->supported)
++		adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
++
+ 	dev_info(adev->dev, "GPU BACO reset\n");
+ 
+ 	adev->in_baco_reset = 1;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4123-drm-amd-powerplay-avoid-disabling-ECC-if-RAS-is-enab.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4123-drm-amd-powerplay-avoid-disabling-ECC-if-RAS-is-enab.patch
new file mode 100644
index 00000000..b7fb76fd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4123-drm-amd-powerplay-avoid-disabling-ECC-if-RAS-is-enab.patch
@@ -0,0 +1,58 @@
+From d222b18bf2136356f9fae2b6df597e372ebf9da7 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 11 Oct 2019 18:37:49 +0800
+Subject: [PATCH 4123/4736] drm/amd/powerplay: avoid disabling ECC if RAS is
+ enabled for VEGA20
+
+Program THM_BACO_CNTL.SOC_DOMAIN_IDLE=1 will tell VBIOS to disable ECC when
+BACO exit. This can save BACO exit time by PSP on none-ECC SKU. Drop the setting
+for ECC supported SKU.
+
+Change-Id: I2a82c128fa5e9731b886dd61f1273dc48ea1923c
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c | 12 +++++++-----
+ 1 file changed, 7 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
+index df6ff9252401..b068d1c7b44d 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
+@@ -29,7 +29,7 @@
+ #include "vega20_baco.h"
+ #include "vega20_smumgr.h"
+ 
+-
++#include "amdgpu_ras.h"
+ 
+ static const struct soc15_baco_cmd_entry clean_baco_tbl[] =
+ {
+@@ -74,6 +74,7 @@ int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
+ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+ 	enum BACO_STATE cur_state;
+ 	uint32_t data;
+ 
+@@ -84,10 +85,11 @@ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ 		return 0;
+ 
+ 	if (state == BACO_STATE_IN) {
+-		data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
+-		data |= 0x80000000;
+-		WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
+-
++		if (!ras || !ras->supported) {
++			data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
++			data |= 0x80000000;
++			WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
++		}
+ 
+ 		if(smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_EnterBaco, 0))
+ 			return -EINVAL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4124-drm-amd-powerplay-send-EnterBaco-msg-with-argument-a.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4124-drm-amd-powerplay-send-EnterBaco-msg-with-argument-a.patch
new file mode 100644
index 00000000..7d00c82b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4124-drm-amd-powerplay-send-EnterBaco-msg-with-argument-a.patch
@@ -0,0 +1,42 @@
+From f8e3ee206137a22a4172be249df166ebc49325ad Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 11 Oct 2019 18:50:44 +0800
+Subject: [PATCH 4124/4736] drm/amd/powerplay: send EnterBaco msg with argument
+ as RAS recovery flag
+
+1 indicates RAS recovery flag in SMU FW.
+
+Change-Id: Icb8c14586fca1b8ae443bbde764570a9e41850fa
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c | 11 ++++++++---
+ 1 file changed, 8 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
+index b068d1c7b44d..9b5e72bdceca 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
+@@ -89,10 +89,15 @@ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ 			data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
+ 			data |= 0x80000000;
+ 			WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
+-		}
+ 
+-		if(smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_EnterBaco, 0))
+-			return -EINVAL;
++			if(smum_send_msg_to_smc_with_parameter(hwmgr,
++					PPSMC_MSG_EnterBaco, 0))
++				return -EINVAL;
++		} else {
++			if(smum_send_msg_to_smc_with_parameter(hwmgr,
++					PPSMC_MSG_EnterBaco, 1))
++				return -EINVAL;
++		}
+ 
+ 	} else if (state == BACO_STATE_OUT) {
+ 		if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ExitBaco))
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4125-drm-amd-powerplay-add-BACO-platformCaps-for-VEGA20.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4125-drm-amd-powerplay-add-BACO-platformCaps-for-VEGA20.patch
new file mode 100644
index 00000000..32d03754
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4125-drm-amd-powerplay-add-BACO-platformCaps-for-VEGA20.patch
@@ -0,0 +1,32 @@
+From 2aa549a55977d90e59688b551961ced291631f8f Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 11 Oct 2019 19:00:00 +0800
+Subject: [PATCH 4125/4736] drm/amd/powerplay: add BACO platformCaps for VEGA20
+
+BACO reset is needed for RAS recovery.
+
+Change-Id: I8207fc314744468c89ba4a030cb2bb15b082aac7
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+index 6629c475fe5d..3d3c647a63ff 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+@@ -182,6 +182,9 @@ static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
+ 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ 			PHM_PlatformCaps_TablelessHardwareInterface);
+ 
++	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
++			PHM_PlatformCaps_BACO);
++
+ 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ 			PHM_PlatformCaps_EnableSMU7ThermalManagement);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4126-drm-amdgpu-Bail-earlier-when-amdgpu.cik_-si_support-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4126-drm-amdgpu-Bail-earlier-when-amdgpu.cik_-si_support-.patch
new file mode 100644
index 00000000..c84b68c4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4126-drm-amdgpu-Bail-earlier-when-amdgpu.cik_-si_support-.patch
@@ -0,0 +1,121 @@
+From a2d92bf0a020c9db4eb2c9e4c53fd274813f8ad4 Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Thu, 10 Oct 2019 18:28:17 +0200
+Subject: [PATCH 4126/4736] drm/amdgpu: Bail earlier when
+ amdgpu.cik_/si_support is not set to 1
+
+Bail from the pci_driver probe function instead of from the drm_driver
+load function.
+
+This avoid /dev/dri/card0 temporarily getting registered and then
+unregistered again, sending unwanted add / remove udev events to
+userspace.
+
+Specifically this avoids triggering the (userspace) bug fixed by this
+plymouth merge-request:
+https://gitlab.freedesktop.org/plymouth/plymouth/merge_requests/59
+
+Note that despite that being a userspace bug, not sending unnecessary
+udev events is a good idea in general.
+
+BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1490490
+Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 35 +++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 32 ----------------------
+ 2 files changed, 35 insertions(+), 32 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 50927cd86cc9..9ca74f242fd1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1067,6 +1067,41 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
+ 		return -ENODEV;
+ 	}
+ 
++#ifdef CONFIG_DRM_AMDGPU_SI
++	if (!amdgpu_si_support) {
++		switch (flags & AMD_ASIC_MASK) {
++		case CHIP_TAHITI:
++		case CHIP_PITCAIRN:
++		case CHIP_VERDE:
++		case CHIP_OLAND:
++		case CHIP_HAINAN:
++			dev_info(&pdev->dev,
++				 "SI support provided by radeon.\n");
++			dev_info(&pdev->dev,
++				 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
++				);
++			return -ENODEV;
++		}
++	}
++#endif
++#ifdef CONFIG_DRM_AMDGPU_CIK
++	if (!amdgpu_cik_support) {
++		switch (flags & AMD_ASIC_MASK) {
++		case CHIP_KAVERI:
++		case CHIP_BONAIRE:
++		case CHIP_HAWAII:
++		case CHIP_KABINI:
++		case CHIP_MULLINS:
++			dev_info(&pdev->dev,
++				 "CIK support provided by radeon.\n");
++			dev_info(&pdev->dev,
++				 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
++				);
++			return -ENODEV;
++		}
++	}
++#endif
++
+ 	/* Get rid of things like offb */
+ 	ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb");
+ 	if (ret)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 20b11c024b87..ff47dd26e35a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -141,38 +141,6 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
+ 	struct amdgpu_device *adev;
+ 	int r, acpi_status;
+ 
+-#ifdef CONFIG_DRM_AMDGPU_SI
+-	if (!amdgpu_si_support) {
+-		switch (flags & AMD_ASIC_MASK) {
+-		case CHIP_TAHITI:
+-		case CHIP_PITCAIRN:
+-		case CHIP_VERDE:
+-		case CHIP_OLAND:
+-		case CHIP_HAINAN:
+-			dev_info(dev->dev,
+-				 "SI support provided by radeon.\n");
+-			dev_info(dev->dev,
+-		"Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
+-				);
+-			return -ENODEV;
+-		}
+-	}
+-#endif
+-#ifdef CONFIG_DRM_AMDGPU_CIK
+-	if (!amdgpu_cik_support) {
+-		switch (flags & AMD_ASIC_MASK) {
+-		case CHIP_KAVERI:
+-		case CHIP_BONAIRE:
+-		case CHIP_HAWAII:
+-		case CHIP_KABINI:
+-		case CHIP_MULLINS:
+-			dev_info(dev->dev,
+-				 "CIK support disabled by module param\n");
+-			return -ENODEV;
+-		}
+-	}
+-#endif
+-
+ 	adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
+ 	if (adev == NULL) {
+ 		return -ENOMEM;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4127-drm-amdgpu-change-to-query-the-actual-EDC-counter.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4127-drm-amdgpu-change-to-query-the-actual-EDC-counter.patch
new file mode 100644
index 00000000..3d1ddf2c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4127-drm-amdgpu-change-to-query-the-actual-EDC-counter.patch
@@ -0,0 +1,914 @@
+From ffae45c6e296a3acaedd96fab920fb43672b2f50 Mon Sep 17 00:00:00 2001
+From: Dennis Li <Dennis.Li@amd.com>
+Date: Sat, 12 Oct 2019 13:00:22 +0800
+Subject: [PATCH 4127/4736] drm/amdgpu: change to query the actual EDC counter
+
+For the potential request in the future, change to
+query the actual EDC counter.
+
+Change-Id: I783ccd76f4c65f9829f7a8967a539a23ae5484b5
+Signed-off-by: Dennis Li <Dennis.Li@amd.com>
+Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 821 ++++++++++++++++----------
+ drivers/gpu/drm/amd/amdgpu/soc15.h    |   2 +
+ 2 files changed, 498 insertions(+), 325 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 2e316e9da4cf..2d7140e57113 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -127,6 +127,18 @@ MODULE_FIRMWARE("amdgpu/renoir_rlc.bin");
+ #define mmTCP_CHAN_STEER_5_ARCT								0x0b0c
+ #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX							0
+ 
++struct ras_gfx_subblock_reg {
++	const char *name;
++	uint32_t hwip;
++	uint32_t inst;
++	uint32_t seg;
++	uint32_t reg_offset;
++	uint32_t sec_count_mask;
++	uint32_t sec_count_shift;
++	uint32_t ded_count_mask;
++	uint32_t ded_count_shift;
++};
++
+ enum ta_ras_gfx_subblock {
+ 	/*CPC*/
+ 	TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
+@@ -3976,6 +3988,7 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
+    { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16},
+    { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16},
+    { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16},
++   { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16},
+    { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16},
+    { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6},
+    { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16},
+@@ -5443,301 +5456,446 @@ static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
+ 	return 0;
+ }
+ 
+-static const struct {
+-	const char *name;
+-	uint32_t ip;
+-	uint32_t inst;
+-	uint32_t seg;
+-	uint32_t reg_offset;
+-	uint32_t per_se_instance;
+-	int32_t num_instance;
+-	uint32_t sec_count_mask;
+-	uint32_t ded_count_mask;
+-} gfx_ras_edc_regs[] = {
+-	{ "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1,
+-	  REG_FIELD_MASK(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
+-	  REG_FIELD_MASK(CPC_EDC_SCRATCH_CNT, DED_COUNT) },
+-	{ "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1,
+-	  REG_FIELD_MASK(CPC_EDC_UCODE_CNT, SEC_COUNT),
+-	  REG_FIELD_MASK(CPC_EDC_UCODE_CNT, DED_COUNT) },
+-	{ "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1,
+-	  REG_FIELD_MASK(CPF_EDC_ROQ_CNT, COUNT_ME1), 0 },
+-	{ "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1,
+-	  REG_FIELD_MASK(CPF_EDC_ROQ_CNT, COUNT_ME2), 0 },
+-	{ "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1,
+-	  REG_FIELD_MASK(CPF_EDC_TAG_CNT, SEC_COUNT),
+-	  REG_FIELD_MASK(CPF_EDC_TAG_CNT, DED_COUNT) },
+-	{ "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1,
+-	  REG_FIELD_MASK(CPG_EDC_DMA_CNT, ROQ_COUNT), 0 },
+-	{ "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1,
+-	  REG_FIELD_MASK(CPG_EDC_DMA_CNT, TAG_SEC_COUNT),
+-	  REG_FIELD_MASK(CPG_EDC_DMA_CNT, TAG_DED_COUNT) },
+-	{ "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1,
+-	  REG_FIELD_MASK(CPG_EDC_TAG_CNT, SEC_COUNT),
+-	  REG_FIELD_MASK(CPG_EDC_TAG_CNT, DED_COUNT) },
+-	{ "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1,
+-	  REG_FIELD_MASK(DC_EDC_CSINVOC_CNT, COUNT_ME1), 0 },
+-	{ "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1,
+-	  REG_FIELD_MASK(DC_EDC_RESTORE_CNT, COUNT_ME1), 0 },
+-	{ "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1,
+-	  REG_FIELD_MASK(DC_EDC_STATE_CNT, COUNT_ME1), 0 },
+-	{ "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1,
+-	  REG_FIELD_MASK(GDS_EDC_CNT, GDS_MEM_SEC),
+-	  REG_FIELD_MASK(GDS_EDC_CNT, GDS_MEM_DED) },
+-	{ "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1,
+-	  REG_FIELD_MASK(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), 0 },
++
++static const struct ras_gfx_subblock_reg ras_subblock_regs[] = {
++	{ "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT),
++	  SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
++	  SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT)
++	},
++	{ "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT),
++	  SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT),
++	  SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT)
++	},
++	{ "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
++	  SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME1),
++	  0, 0
++	},
++	{ "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
++	  SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME2),
++	  0, 0
++	},
++	{ "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT),
++	  SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT),
++	  SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT)
++	},
++	{ "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT),
++	  SOC15_REG_FIELD(CPG_EDC_DMA_CNT, ROQ_COUNT),
++	  0, 0
++	},
++	{ "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT),
++	  SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_SEC_COUNT),
++	  SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_DED_COUNT)
++	},
++	{ "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT),
++	  SOC15_REG_FIELD(CPG_EDC_TAG_CNT, SEC_COUNT),
++	  SOC15_REG_FIELD(CPG_EDC_TAG_CNT, DED_COUNT)
++	},
++	{ "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
++	  SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, COUNT_ME1),
++	  0, 0
++	},
++	{ "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
++	  SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, COUNT_ME1),
++	  0, 0
++	},
++	{ "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT),
++	  SOC15_REG_FIELD(DC_EDC_STATE_CNT, COUNT_ME1),
++	  0, 0
++	},
++	{ "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
++	  SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC),
++	  SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED)
++	},
++	{ "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
++	  SOC15_REG_FIELD(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED),
++	  0, 0
++	},
+ 	{ "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
+-	  0, 1, REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC),
+-	  REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) },
++	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC),
++	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED)
++	},
+ 	{ "GDS_OA_PHY_PHY_CMD_RAM_MEM",
+-	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1,
+-	  REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC),
+-	  REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) },
++	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
++	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC),
++	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED)
++	},
+ 	{ "GDS_OA_PHY_PHY_DATA_RAM_MEM",
+-	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1,
+-	  REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), 0 },
++	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
++	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED),
++	  0, 0
++	},
+ 	{ "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM",
+-	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
+-	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC),
+-	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) },
++	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
++	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC),
++	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED)
++	},
+ 	{ "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM",
+-	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
+-	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC),
+-	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) },
++	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
++	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC),
++	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED)
++	},
+ 	{ "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM",
+-	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
+-	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC),
+-	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) },
++	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
++	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC),
++	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED)
++	},
+ 	{ "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM",
+-	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
+-	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC),
+-	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) },
+-	{ "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 1, 1,
+-	  REG_FIELD_MASK(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), 0 },
+-	{ "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
+-	  REG_FIELD_MASK(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT),
+-	  REG_FIELD_MASK(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) },
+-	{ "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
+-	  REG_FIELD_MASK(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), 0 },
+-	{ "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
+-	  REG_FIELD_MASK(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), 0 },
+-	{ "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
+-	  REG_FIELD_MASK(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), 0 },
+-	{ "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
+-	  REG_FIELD_MASK(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), 0 },
+-	{ "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 2,
+-	  REG_FIELD_MASK(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), 0 },
+-	{ "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 2,
+-	  REG_FIELD_MASK(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), 0 },
+-	{ "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+-	  REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT),
+-	  REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) },
+-	{ "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+-	  REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT),
+-	  REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) },
+-	{ "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+-	  REG_FIELD_MASK(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT),
+-	  REG_FIELD_MASK(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) },
+-	{ "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+-	  REG_FIELD_MASK(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT),
+-	  REG_FIELD_MASK(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) },
+-	{ "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+-	  REG_FIELD_MASK(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT),
+-	  REG_FIELD_MASK(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) },
+-	{ "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+-	  REG_FIELD_MASK(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), 0 },
+-	{ "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+-	  REG_FIELD_MASK(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), 0 },
+-	{ "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+-	  REG_FIELD_MASK(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), 0 },
+-	{ "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+-	  REG_FIELD_MASK(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), 0 },
+-	{ "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+-	  REG_FIELD_MASK(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), 0 },
+-	{ "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
+-	  REG_FIELD_MASK(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), 0 },
+-	{ "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 16,
+-	  REG_FIELD_MASK(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), 0 },
+-	{ "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 16,
+-	  REG_FIELD_MASK(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), 0 },
+-	{ "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0,
+-	  16, REG_FIELD_MASK(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), 0 },
++	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
++	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC),
++	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED)
++	},
++	{ "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
++	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT),
++	  0, 0
++	},
++	{ "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
++	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT),
++	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT)
++	},
++	{ "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
++	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT),
++	  0, 0
++	},
++	{ "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
++	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT),
++	  0, 0
++	},
++	{ "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
++	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT),
++	  0, 0
++	},
++	{ "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
++	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT),
++	  0, 0
++	},
++	{ "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
++	  SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT),
++	  0, 0
++	},
++	{ "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
++	  SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SED_COUNT),
++	  0, 0
++	},
++	{ "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++	  SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT),
++	  SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT)
++	},
++	{ "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++	  SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT),
++	  SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT)
++	},
++	{ "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++	  SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT),
++	  SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT)
++	},
++	{ "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++	  SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT),
++	  SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT)
++	},
++	{ "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++	  SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT),
++	  SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT)
++	},
++	{ "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++	  SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT),
++	  0, 0
++	},
++	{ "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++	  SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT),
++	  0, 0
++	},
++	{ "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++	  SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT),
++	  0, 0
++	},
++	{ "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++	  SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_DATA_SED_COUNT),
++	  0, 0
++	},
++	{ "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++	  SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT),
++	  0, 0
++	},
++	{ "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
++	  SOC15_REG_FIELD(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT),
++	  0, 0
++	},
++	{ "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
++	  SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT),
++	  0, 0
++	},
++	{ "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
++	  SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT),
++	  0, 0
++	},
++	{ "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
++	  SOC15_REG_FIELD(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT),
++	  0, 0
++	},
+ 	{ "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
+-	  0, 16, REG_FIELD_MASK(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT),
+-	  0 },
+-	{ "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0,
+-	  16, REG_FIELD_MASK(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), 0 },
++	  SOC15_REG_FIELD(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT),
++	  0, 0
++	},
++	{ "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
++	  SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT),
++	  0, 0
++	},
+ 	{ "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
+-	  0, 16, REG_FIELD_MASK(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT),
+-	  0 },
+-	{ "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0,
+-	  16, REG_FIELD_MASK(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), 0 },
+-	{ "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 72,
+-	  REG_FIELD_MASK(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), 0 },
+-	{ "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
+-	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT),
+-	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) },
+-	{ "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
+-	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT),
+-	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) },
+-	{ "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
+-	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), 0 },
+-	{ "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
+-	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), 0 },
+-	{ "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
+-	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 0 },
+-	{ "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
+-	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT),
+-	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) },
+-	{ "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
+-	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT),
+-	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) },
+-	{ "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16,
+-	  REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT),
+-	  REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) },
+-	{ "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16,
+-	  REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT),
+-	  REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) },
+-	{ "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16,
+-	  REG_FIELD_MASK(TD_EDC_CNT, CS_FIFO_SED_COUNT), 0 },
+-	{ "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
+-	  REG_FIELD_MASK(SQ_EDC_CNT, LDS_D_SEC_COUNT),
+-	  REG_FIELD_MASK(SQ_EDC_CNT, LDS_D_DED_COUNT) },
+-	{ "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
+-	  REG_FIELD_MASK(SQ_EDC_CNT, LDS_I_SEC_COUNT),
+-	  REG_FIELD_MASK(SQ_EDC_CNT, LDS_I_DED_COUNT) },
+-	{ "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
+-	  REG_FIELD_MASK(SQ_EDC_CNT, SGPR_SEC_COUNT),
+-	  REG_FIELD_MASK(SQ_EDC_CNT, SGPR_DED_COUNT) },
+-	{ "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
+-	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR0_SEC_COUNT),
+-	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR0_DED_COUNT) },
+-	{ "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
+-	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR1_SEC_COUNT),
+-	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR1_DED_COUNT) },
+-	{ "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
+-	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR2_SEC_COUNT),
+-	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR2_DED_COUNT) },
+-	{ "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
+-	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR3_SEC_COUNT),
+-	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR3_DED_COUNT) },
++	  SOC15_REG_FIELD(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT),
++	  0, 0
++	},
++	{ "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
++	  SOC15_REG_FIELD(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT),
++	  0, 0
++	},
++	{ "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT),
++	  SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SED_COUNT),
++	  0, 0
++	},
++	{ "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
++	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT),
++	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT)
++	},
++	{ "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
++	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT),
++	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT)
++	},
++	{ "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
++	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT),
++	  0, 0
++	},
++	{ "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
++	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT),
++	  0, 0
++	},
++	{ "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
++	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT),
++	  0, 0
++	},
++	{ "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
++	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT),
++	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT)
++	},
++	{ "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
++	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT),
++	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT)
++	},
++	{ "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
++	  SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT),
++	  SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT)
++	},
++	{ "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
++	  SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT),
++	  SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT)
++	},
++	{ "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
++	  SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SED_COUNT),
++	  0, 0
++	},
++	{ "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
++	  SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT),
++	  SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT)
++	},
++	{ "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
++	  SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT),
++	  SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT)
++	},
++	{ "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
++	  SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT),
++	  SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT)
++	},
++	{ "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
++	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT),
++	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT)
++	},
++	{ "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
++	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT),
++	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT)
++	},
++	{ "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
++	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT),
++	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT)
++	},
++	{ "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
++	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT),
++	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT)
++	},
+ 	{ "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
+-	  1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT),
+-	  REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) },
+-	{ "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1,
+-	  6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT),
+-	  REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) },
++	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT),
++	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT)
++	},
++	{ "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
++	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT),
++	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT)
++	},
+ 	{ "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
+-	  1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT),
+-	  REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) },
+-	{ "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1,
+-	  6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT),
+-	  REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) },
++	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT),
++	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT)
++	},
++	{ "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
++	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT),
++	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT)
++	},
+ 	{ "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
+-	  1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT),
+-	  REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) },
+-	{ "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1,
+-	  6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT),
+-	  REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) },
+-	{ "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
+-	  6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT),
+-	  REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) },
+-	{ "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
+-	  6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT),
+-	  REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) },
+-	{ "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
+-	  6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT),
+-	  REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) },
+-	{ "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
+-	  6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT),
+-	  REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) },
+-	{ "SQC_INST_BANKA_UTCL1_MISS_FIFO",
+-	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6,
+-	  REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT),
+-	  0 },
+-	{ "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
+-	  6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), 0 },
+-	{ "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
+-	  6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), 0 },
+-	{ "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
+-	  6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), 0 },
+-	{ "SQC_DATA_BANKA_DIRTY_BIT_RAM",
+-	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6,
+-	  REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), 0 },
+-	{ "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6,
+-	  REG_FIELD_MASK(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT),
+-	  REG_FIELD_MASK(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) },
+-	{ "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
+-	  6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT),
+-	  REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) },
+-	{ "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
+-	  6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT),
+-	  REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) },
+-	{ "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
+-	  6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT),
+-	  REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) },
+-	{ "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
+-	  6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT),
+-	  REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) },
+-	{ "SQC_INST_BANKB_UTCL1_MISS_FIFO",
+-	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, 6,
+-	  REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT),
+-	  0 },
+-	{ "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
+-	  6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), 0 },
+-	{ "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
+-	  6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), 0 },
+-	{ "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
+-	  6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), 0 },
+-	{ "SQC_DATA_BANKB_DIRTY_BIT_RAM",
+-	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, 6,
+-	  REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), 0 },
+-	{ "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
+-	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) },
+-	{ "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
+-	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) },
+-	{ "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
+-	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) },
+-	{ "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
+-	  REG_FIELD_MASK(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) },
+-	{ "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
+-	  REG_FIELD_MASK(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) },
+-	{ "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 0 },
+-	{ "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 0 },
+-	{ "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 0 },
+-	{ "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 0 },
+-	{ "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 0 },
+-	{ "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
+-	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) },
+-	{ "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
+-	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) },
+-	{ "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
+-	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) },
+-	{ "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 0 },
+-	{ "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 0 },
+-	{ "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), 0 },
+-	{ "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), 0 },
+-	{ "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), 0 },
+-	{ "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
+-	  REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), 0 },
++	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT),
++	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT)
++	},
++	{ "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
++	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT),
++	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT)
++	},
++	{ "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT),
++	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT)
++	},
++	{ "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT),
++	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT)
++	},
++	{ "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT),
++	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT)
++	},
++	{ "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT),
++	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT)
++	},
++	{ "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT),
++	  0, 0
++	},
++	{ "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT),
++	  0, 0
++	},
++	{ "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT),
++	  0, 0
++	},
++	{ "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT),
++	  0, 0
++	},
++	{ "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT),
++	  0, 0
++	},
++	{ "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
++	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT),
++	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT)
++	},
++	{ "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
++	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT),
++	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT)
++	},
++	{ "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
++	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT),
++	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT)
++	},
++	{ "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
++	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT),
++	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT)
++	},
++	{ "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
++	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT),
++	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT)
++	},
++	{ "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
++	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT),
++	  0, 0
++	},
++	{ "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
++	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT),
++	  0, 0
++	},
++	{ "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
++	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT),
++	  0, 0
++	},
++	{ "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
++	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT),
++	  0, 0
++	},
++	{ "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
++	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT),
++	  0, 0
++	},
++	{ "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT)
++	},
++	{ "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT)
++	},
++	{ "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT)
++	},
++	{ "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT)
++	},
++	{ "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT)
++	},
++	{ "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
++	  0, 0
++	},
++	{ "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
++	  0, 0
++	},
++	{ "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT),
++	  0, 0
++	},
++	{ "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
++	  0, 0
++	},
++	{ "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
++	  0, 0
++	},
++	{ "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT)
++	},
++	{ "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT)
++	},
++	{ "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT)
++	},
++	{ "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
++	  0, 0
++	},
++	{ "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
++	  0, 0
++	},
++	{ "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT),
++	  0, 0
++	},
++	{ "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT),
++	  0, 0
++	},
++	{ "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT),
++	  0, 0
++	},
++	{ "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
++	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT),
++	  0, 0
++	}
+ };
+ 
+ static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
+@@ -5786,14 +5944,52 @@ static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
+ 	return ret;
+ }
+ 
++static int __get_ras_error_count(const struct soc15_reg_entry *reg,
++	uint32_t se_id, uint32_t inst_id, uint32_t value,
++	uint32_t *sec_count, uint32_t *ded_count)
++{
++	uint32_t i;
++	uint32_t sec_cnt, ded_cnt;
++
++	for (i = 0; i < ARRAY_SIZE(ras_subblock_regs); i++) {
++		if(ras_subblock_regs[i].reg_offset != reg->reg_offset ||
++			ras_subblock_regs[i].seg != reg->seg ||
++			ras_subblock_regs[i].inst != reg->inst)
++			continue;
++
++		sec_cnt = (value &
++				ras_subblock_regs[i].sec_count_mask) >>
++				ras_subblock_regs[i].sec_count_shift;
++		if (sec_cnt) {
++			DRM_INFO("GFX SubBlock %s, Instance[%d][%d], SEC %d\n",
++				ras_subblock_regs[i].name,
++				se_id, inst_id,
++				sec_cnt);
++			*sec_count += sec_cnt;
++		}
++
++		ded_cnt = (value &
++				ras_subblock_regs[i].ded_count_mask) >>
++				ras_subblock_regs[i].ded_count_shift;
++		if (ded_cnt) {
++			DRM_INFO("GFX SubBlock %s, Instance[%d][%d], DED %d\n",
++				ras_subblock_regs[i].name,
++				se_id, inst_id,
++				ded_cnt);
++			*ded_count += ded_cnt;
++		}
++	}
++
++	return 0;
++}
++
+ static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
+ 					  void *ras_error_status)
+ {
+ 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+-	uint32_t sec_count, ded_count;
+-	uint32_t i;
++	uint32_t sec_count = 0, ded_count = 0;
++	uint32_t i, j, k;
+ 	uint32_t reg_value;
+-	uint32_t se_id, instance_id;
+ 
+ 	if (adev->asic_type != CHIP_VEGA20)
+ 		return -EINVAL;
+@@ -5802,49 +5998,24 @@ static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
+ 	err_data->ce_count = 0;
+ 
+ 	mutex_lock(&adev->grbm_idx_mutex);
+-	for (se_id = 0; se_id < adev->gfx.config.max_shader_engines; se_id++) {
+-		for (instance_id = 0; instance_id < 256; instance_id++) {
+-			for (i = 0;
+-			     i < sizeof(gfx_ras_edc_regs) / sizeof(gfx_ras_edc_regs[0]);
+-			     i++) {
+-				if (se_id != 0 &&
+-				    !gfx_ras_edc_regs[i].per_se_instance)
+-					continue;
+-				if (instance_id >= gfx_ras_edc_regs[i].num_instance)
+-					continue;
+ 
+-				gfx_v9_0_select_se_sh(adev, se_id, 0,
+-						      instance_id);
+-
+-				reg_value = RREG32(
+-					adev->reg_offset[gfx_ras_edc_regs[i].ip]
+-							[gfx_ras_edc_regs[i].inst]
+-							[gfx_ras_edc_regs[i].seg] +
+-					gfx_ras_edc_regs[i].reg_offset);
+-				sec_count = reg_value &
+-					    gfx_ras_edc_regs[i].sec_count_mask;
+-				ded_count = reg_value &
+-					    gfx_ras_edc_regs[i].ded_count_mask;
+-				if (sec_count) {
+-					DRM_INFO(
+-						"Instance[%d][%d]: SubBlock %s, SEC %d\n",
+-						se_id, instance_id,
+-						gfx_ras_edc_regs[i].name,
+-						sec_count);
+-					err_data->ce_count++;
+-				}
+-
+-				if (ded_count) {
+-					DRM_INFO(
+-						"Instance[%d][%d]: SubBlock %s, DED %d\n",
+-						se_id, instance_id,
+-						gfx_ras_edc_regs[i].name,
+-						ded_count);
+-					err_data->ue_count++;
+-				}
++	for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) {
++		for (j = 0; j < sec_ded_counter_registers[i].se_num; j++) {
++			for (k = 0; k < sec_ded_counter_registers[i].instance; k++) {
++				gfx_v9_0_select_se_sh(adev, j, 0, k);
++				reg_value =
++					RREG32(SOC15_REG_ENTRY_OFFSET(sec_ded_counter_registers[i]));
++				if (reg_value)
++					__get_ras_error_count(&sec_ded_counter_registers[i],
++							j, k, reg_value,
++							&sec_count, &ded_count);
+ 			}
+ 		}
+ 	}
++
++	err_data->ce_count += sec_count;
++	err_data->ue_count += ded_count;
++
+ 	gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+ 	mutex_unlock(&adev->grbm_idx_mutex);
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
+index a3dde0c31f57..9af6c6ffbfa2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
+@@ -67,6 +67,8 @@ struct soc15_allowed_register_entry {
+ #define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
+ 	{ ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
+ 
++#define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT
++
+ void soc15_grbm_select(struct amdgpu_device *adev,
+ 		    u32 me, u32 pipe, u32 queue, u32 vmid);
+ int soc15_set_ip_blocks(struct amdgpu_device *adev);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4128-drm-amd-include-add-register-define-for-VML2-and-ATC.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4128-drm-amd-include-add-register-define-for-VML2-and-ATC.patch
new file mode 100644
index 00000000..3a3cdbe6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4128-drm-amd-include-add-register-define-for-VML2-and-ATC.patch
@@ -0,0 +1,92 @@
+From b4d660a216d1ef77aca09688ec730030d34befb9 Mon Sep 17 00:00:00 2001
+From: Dennis Li <Dennis.Li@amd.com>
+Date: Fri, 9 Aug 2019 14:30:29 +0800
+Subject: [PATCH 4128/4736] drm/amd/include: add register define for VML2 and
+ ATCL2
+
+Add VML2 and ATCL2 ECC registers to support VEGA20 RAS
+
+Change-Id: I8860f2e37fa7afd8d6123290fb7b9dcee56edd6e
+Signed-off-by: Dennis Li <Dennis.Li@amd.com>
+Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../amd/include/asic_reg/gc/gc_9_0_offset.h    | 18 ++++++++++++++++--
+ .../amd/include/asic_reg/gc/gc_9_0_sh_mask.h   | 18 ++++++++++++++++--
+ 2 files changed, 32 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
+index ca16d9125fbc..2bfaaa8157d0 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
+@@ -1146,7 +1146,14 @@
+ #define mmATC_L2_MEM_POWER_LS_BASE_IDX                                                                 0
+ #define mmATC_L2_CGTT_CLK_CTRL                                                                         0x080c
+ #define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX                                                                0
+-
++#define mmATC_L2_CACHE_4K_EDC_INDEX                                                                    0x080e
++#define mmATC_L2_CACHE_4K_EDC_INDEX_BASE_IDX                                                           0
++#define mmATC_L2_CACHE_2M_EDC_INDEX                                                                    0x080f
++#define mmATC_L2_CACHE_2M_EDC_INDEX_BASE_IDX                                                           0
++#define mmATC_L2_CACHE_4K_EDC_CNT                                                                      0x0810
++#define mmATC_L2_CACHE_4K_EDC_CNT_BASE_IDX                                                             0
++#define mmATC_L2_CACHE_2M_EDC_CNT                                                                      0x0811
++#define mmATC_L2_CACHE_2M_EDC_CNT_BASE_IDX                                                             0
+ 
+ // addressBlock: gc_utcl2_vml2pfdec
+ // base address: 0xa100
+@@ -1206,7 +1213,14 @@
+ #define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX                                                             0
+ #define mmVM_L2_CGTT_CLK_CTRL                                                                          0x085e
+ #define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX                                                                 0
+-
++#define mmVM_L2_MEM_ECC_INDEX                                                                          0x0860
++#define mmVM_L2_MEM_ECC_INDEX_BASE_IDX                                                                 0
++#define mmVM_L2_WALKER_MEM_ECC_INDEX                                                                   0x0861
++#define mmVM_L2_WALKER_MEM_ECC_INDEX_BASE_IDX                                                          0
++#define mmVM_L2_MEM_ECC_CNT                                                                            0x0862
++#define mmVM_L2_MEM_ECC_CNT_BASE_IDX                                                                   0
++#define mmVM_L2_WALKER_MEM_ECC_CNT                                                                     0x0863
++#define mmVM_L2_WALKER_MEM_ECC_CNT_BASE_IDX                                                            0
+ 
+ // addressBlock: gc_utcl2_vml2vcdec
+ // base address: 0xa200
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
+index 064c4bb1dc62..d4c613a85352 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
+@@ -6661,7 +6661,6 @@
+ #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                        0x00FF0000L
+ #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                              0xFF000000L
+ 
+-
+ // addressBlock: gc_utcl2_vml2pfdec
+ //VM_L2_CNTL
+ #define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT                                                                    0x0
+@@ -6991,7 +6990,22 @@
+ #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                               0x00008000L
+ #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                         0x00FF0000L
+ #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                               0xFF000000L
+-
++//VM_L2_MEM_ECC_INDEX
++#define VM_L2_MEM_ECC_INDEX__INDEX__SHIFT                                                                     0x0
++#define VM_L2_MEM_ECC_INDEX__INDEX_MASK                                                                       0x000000FFL
++//VM_L2_WALKER_MEM_ECC_INDEX
++#define VM_L2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT                                                              0x0
++#define VM_L2_WALKER_MEM_ECC_INDEX__INDEX_MASK                                                                0x000000FFL
++//VM_L2_MEM_ECC_CNT
++#define VM_L2_MEM_ECC_CNT__SEC_COUNT__SHIFT                                                                   0xc
++#define VM_L2_MEM_ECC_CNT__DED_COUNT__SHIFT                                                                   0xe
++#define VM_L2_MEM_ECC_CNT__SEC_COUNT_MASK                                                                     0x00003000L
++#define VM_L2_MEM_ECC_CNT__DED_COUNT_MASK                                                                     0x0000C000L
++//VM_L2_WALKER_MEM_ECC_CNT
++#define VM_L2_WALKER_MEM_ECC_CNT__SEC_COUNT__SHIFT                                                            0xc
++#define VM_L2_WALKER_MEM_ECC_CNT__DED_COUNT__SHIFT                                                            0xe
++#define VM_L2_WALKER_MEM_ECC_CNT__SEC_COUNT_MASK                                                              0x00003000L
++#define VM_L2_WALKER_MEM_ECC_CNT__DED_COUNT_MASK                                                              0x0000C000L
+ 
+ // addressBlock: gc_utcl2_vml2vcdec
+ //VM_CONTEXT0_CNTL
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4129-drm-amdgpu-add-RAS-support-for-VML2-and-ATCL2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4129-drm-amdgpu-add-RAS-support-for-VML2-and-ATCL2.patch
new file mode 100644
index 00000000..ca6b0fa0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4129-drm-amdgpu-add-RAS-support-for-VML2-and-ATCL2.patch
@@ -0,0 +1,205 @@
+From 3524f56effff32b75337729b56e3209600be45a0 Mon Sep 17 00:00:00 2001
+From: Dennis Li <Dennis.Li@amd.com>
+Date: Sun, 29 Sep 2019 16:04:10 +0800
+Subject: [PATCH 4129/4736] drm/amdgpu: add RAS support for VML2 and ATCL2
+
+v1: Add codes to query the EDC count of VML2 & ATCL2
+v2: Rename VML2/ATCL2 registers and drop their mask define
+v3: Add back the ECC mask for VML2 registers
+
+Change-Id: If2c251481ba0a1a34ce3405a85f86d65eecee461
+Signed-off-by: Dennis Li <Dennis.Li@amd.com>
+Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 167 ++++++++++++++++++++++++++
+ 1 file changed, 167 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 2d7140e57113..24802e4d25e5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -5944,6 +5944,171 @@ static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
+ 	return ret;
+ }
+ 
++static const char *vml2_mems[] = {
++	"UTC_VML2_BANK_CACHE_0_BIGK_MEM0",
++	"UTC_VML2_BANK_CACHE_0_BIGK_MEM1",
++	"UTC_VML2_BANK_CACHE_0_4K_MEM0",
++	"UTC_VML2_BANK_CACHE_0_4K_MEM1",
++	"UTC_VML2_BANK_CACHE_1_BIGK_MEM0",
++	"UTC_VML2_BANK_CACHE_1_BIGK_MEM1",
++	"UTC_VML2_BANK_CACHE_1_4K_MEM0",
++	"UTC_VML2_BANK_CACHE_1_4K_MEM1",
++	"UTC_VML2_BANK_CACHE_2_BIGK_MEM0",
++	"UTC_VML2_BANK_CACHE_2_BIGK_MEM1",
++	"UTC_VML2_BANK_CACHE_2_4K_MEM0",
++	"UTC_VML2_BANK_CACHE_2_4K_MEM1",
++	"UTC_VML2_BANK_CACHE_3_BIGK_MEM0",
++	"UTC_VML2_BANK_CACHE_3_BIGK_MEM1",
++	"UTC_VML2_BANK_CACHE_3_4K_MEM0",
++	"UTC_VML2_BANK_CACHE_3_4K_MEM1",
++};
++
++static const char *vml2_walker_mems[] = {
++	"UTC_VML2_CACHE_PDE0_MEM0",
++	"UTC_VML2_CACHE_PDE0_MEM1",
++	"UTC_VML2_CACHE_PDE1_MEM0",
++	"UTC_VML2_CACHE_PDE1_MEM1",
++	"UTC_VML2_CACHE_PDE2_MEM0",
++	"UTC_VML2_CACHE_PDE2_MEM1",
++	"UTC_VML2_RDIF_LOG_FIFO",
++};
++
++static const char *atc_l2_cache_2m_mems[] = {
++	"UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM",
++	"UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM",
++	"UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM",
++	"UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM",
++};
++
++static const char *atc_l2_cache_4k_mems[] = {
++	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0",
++	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1",
++	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2",
++	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3",
++	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4",
++	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5",
++	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6",
++	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7",
++	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0",
++	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1",
++	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2",
++	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3",
++	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4",
++	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5",
++	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6",
++	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7",
++	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0",
++	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1",
++	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2",
++	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3",
++	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4",
++	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5",
++	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6",
++	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7",
++	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0",
++	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1",
++	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2",
++	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3",
++	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4",
++	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5",
++	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6",
++	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7",
++};
++
++static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev,
++					 struct ras_err_data *err_data)
++{
++	uint32_t i, data;
++	uint32_t sec_count, ded_count;
++
++	WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255);
++	WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0);
++	WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255);
++	WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0);
++	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255);
++	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0);
++	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255);
++	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0);
++
++	for (i = 0; i < 16; i++) {
++		WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i);
++		data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT);
++
++		sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT);
++		if (sec_count) {
++			DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
++				 vml2_mems[i], sec_count);
++			err_data->ce_count += sec_count;
++		}
++
++		ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT);
++		if (ded_count) {
++			DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
++				 vml2_mems[i], ded_count);
++			err_data->ue_count += ded_count;
++		}
++	}
++
++	for (i = 0; i < 7; i++) {
++		WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i);
++		data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT);
++
++		sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT,
++						SEC_COUNT);
++		if (sec_count) {
++			DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
++				 vml2_walker_mems[i], sec_count);
++			err_data->ce_count += sec_count;
++		}
++
++		ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT,
++						DED_COUNT);
++		if (ded_count) {
++			DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
++				 vml2_walker_mems[i], ded_count);
++			err_data->ue_count += ded_count;
++		}
++	}
++
++	for (i = 0; i < 4; i++) {
++		WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i);
++		data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT);
++
++		sec_count = (data & 0x00006000L) >> 0xd;
++		if (sec_count) {
++			DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
++				 atc_l2_cache_2m_mems[i], sec_count);
++			err_data->ce_count += sec_count;
++		}
++	}
++
++	for (i = 0; i < 32; i++) {
++		WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i);
++		data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT);
++
++		sec_count = (data & 0x00006000L) >> 0xd;
++		if (sec_count) {
++			DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
++				 atc_l2_cache_4k_mems[i], sec_count);
++			err_data->ce_count += sec_count;
++		}
++
++		ded_count = (data & 0x00018000L) >> 0xf;
++		if (ded_count) {
++			DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i,
++				 atc_l2_cache_4k_mems[i], ded_count);
++			err_data->ue_count += ded_count;
++		}
++	}
++
++	WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255);
++	WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255);
++	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255);
++	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255);
++
++	return 0;
++}
++
+ static int __get_ras_error_count(const struct soc15_reg_entry *reg,
+ 	uint32_t se_id, uint32_t inst_id, uint32_t value,
+ 	uint32_t *sec_count, uint32_t *ded_count)
+@@ -6019,6 +6184,8 @@ static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
+ 	gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+ 	mutex_unlock(&adev->grbm_idx_mutex);
+ 
++	gfx_v9_0_query_utc_edc_status(adev, err_data);
++
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4130-drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_crea.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4130-drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_crea.patch
new file mode 100644
index 00000000..bfa13d6e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4130-drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_crea.patch
@@ -0,0 +1,38 @@
+From 883eb361081a64867284c669a6263995512bcb59 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Wed, 18 Sep 2019 19:42:14 +0200
+Subject: [PATCH 4130/4736] drm/amdgpu: fix error handling in
+ amdgpu_bo_list_create
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We need to drop normal and userptr BOs separately.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Acked-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+index e143d9e110bd..92df38fd794d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+@@ -140,7 +140,12 @@ int amdgpu_bo_list_create(struct amdgpu_device *adev, struct drm_file *filp,
+ 	return 0;
+ 
+ error_free:
+-	while (i--) {
++	for (i = 0; i < last_entry; ++i) {
++		struct amdgpu_bo *bo = ttm_to_amdgpu_bo(array[i].tv.bo);
++
++		amdgpu_bo_unref(&bo);
++	}
++	for (i = first_userptr; i < num_entries; ++i) {
+ 		struct amdgpu_bo *bo = ttm_to_amdgpu_bo(array[i].tv.bo);
+ 
+ 		amdgpu_bo_unref(&bo);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4131-drm-amdgpu-fix-potential-VM-faults.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4131-drm-amdgpu-fix-potential-VM-faults.patch
new file mode 100644
index 00000000..80b32dc1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4131-drm-amdgpu-fix-potential-VM-faults.patch
@@ -0,0 +1,34 @@
+From 34b82c5346e844f2f9ffb12745b79fce980f4542 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Thu, 19 Sep 2019 10:38:57 +0200
+Subject: [PATCH 4131/4736] drm/amdgpu: fix potential VM faults
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+When we allocate new page tables under memory
+pressure we should not evict old ones.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+index acb0755fe724..1350666355e0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+@@ -538,7 +538,8 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
+ 		.interruptible = (bp->type != ttm_bo_type_kernel),
+ 		.no_wait_gpu = bp->no_wait_gpu,
+ 		.resv = bp->resv,
+-		.flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
++		.flags = bp->type != ttm_bo_type_kernel ?
++			TTM_OPT_FLAG_ALLOW_RES_EVICT : 0
+ 	};
+ 	struct amdgpu_bo *bo;
+ 	unsigned long page_align, size = bp->size;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4132-drm-amdgpu-Fix-tdr3-could-hang-with-slow-compute-iss.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4132-drm-amdgpu-Fix-tdr3-could-hang-with-slow-compute-iss.patch
new file mode 100644
index 00000000..6813b358
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4132-drm-amdgpu-Fix-tdr3-could-hang-with-slow-compute-iss.patch
@@ -0,0 +1,53 @@
+From bacf25c006ff8772febc7f022976b07bd2b31882 Mon Sep 17 00:00:00 2001
+From: Emily Deng <Emily.Deng@amd.com>
+Date: Tue, 15 Oct 2019 10:08:22 +0800
+Subject: [PATCH 4132/4736] drm/amdgpu: Fix tdr3 could hang with slow compute
+ issue
+
+When index is 1, need to set compute ring timeout for sriov and passthrough.
+
+Signed-off-by: Emily Deng <Emily.Deng@amd.com>
+Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 ++++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c    | 6 ++++--
+ 2 files changed, 8 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 1b972f531740..521af22ad916 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2622,8 +2622,11 @@ static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
+ 		 * There is only one value specified and
+ 		 * it should apply to all non-compute jobs.
+ 		 */
+-		if (index == 1)
++		if (index == 1) {
+ 			adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
++			if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
++				adev->compute_timeout = adev->gfx_timeout;
++		}
+ 	}
+ 
+ 	return ret;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 9ca74f242fd1..658fa3fd5fad 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -252,9 +252,11 @@ module_param_named(msi, amdgpu_msi, int, 0444);
+  * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
+  * jobs is 10000. And there is no timeout enforced on compute jobs.
+  */
+-MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: 10000 for non-compute jobs and infinity timeout for compute jobs."
++MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; "
++		"for passthrough or sriov, 10000 for all jobs."
+ 		" 0: keep default value. negative: infinity timeout), "
+-		"format is [Non-Compute] or [GFX,Compute,SDMA,Video]");
++		"format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
++		"for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
+ module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
+ 
+ /**
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4133-drm-amd-powerplay-bug-fix-for-pcie-parameters-overri.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4133-drm-amd-powerplay-bug-fix-for-pcie-parameters-overri.patch
new file mode 100644
index 00000000..1907ed9b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4133-drm-amd-powerplay-bug-fix-for-pcie-parameters-overri.patch
@@ -0,0 +1,273 @@
+From 0d3a43711fc55bba4355010ec4c165bafad46c69 Mon Sep 17 00:00:00 2001
+From: Kenneth Feng <kenneth.feng@amd.com>
+Date: Fri, 11 Oct 2019 17:51:34 +0800
+Subject: [PATCH 4133/4736] drm/amd/powerplay: bug fix for pcie parameters
+ override
+
+Bug fix for pcie paramerers override on swsmu.
+Below is a scenario to have this problem.
+pptable definition on pcie dpm:
+0 -> pcie gen speed:1, pcie lanes: *16
+1 -> pcie gen speed:4, pcie lanes: *16
+Then if we have a system only have the capbility:
+pcie gen speed: 3, pcie lanes: *8,
+we will override dpm 1 to pcie gen speed 3, pcie lanes *8.
+But the code skips the dpm 0 configuration.
+So the real pcie dpm parameters are:
+0 -> pcie gen speed:1, pcie lanes: *16
+1 -> pcie gen speed:3, pcie lanes: *8
+Then the wrong pcie lanes will be toggled.
+
+Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 44 -------------------
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  8 ++++
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 23 ++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 44 +++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 23 ++++++++++
+ 5 files changed, 98 insertions(+), 44 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index a37a1b1d8abd..26cacc899dfe 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -945,50 +945,6 @@ static int smu_fini_fb_allocations(struct smu_context *smu)
+ 	return 0;
+ }
+ 
+-static int smu_override_pcie_parameters(struct smu_context *smu)
+-{
+-	struct amdgpu_device *adev = smu->adev;
+-	uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
+-	int ret;
+-
+-	if (adev->flags & AMD_IS_APU)
+-		return 0;
+-
+-	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
+-		pcie_gen = 3;
+-	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
+-		pcie_gen = 2;
+-	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
+-		pcie_gen = 1;
+-	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
+-		pcie_gen = 0;
+-
+-	/* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
+-	 * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
+-	 * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
+-	 */
+-	if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
+-		pcie_width = 6;
+-	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
+-		pcie_width = 5;
+-	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
+-		pcie_width = 4;
+-	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
+-		pcie_width = 3;
+-	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
+-		pcie_width = 2;
+-	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
+-		pcie_width = 1;
+-
+-	smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
+-	ret = smu_send_smc_msg_with_param(smu,
+-					  SMU_MSG_OverridePcieParameters,
+-					  smu_pcie_arg);
+-	if (ret)
+-		pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
+-	return ret;
+-}
+-
+ static int smu_smc_table_hw_init(struct smu_context *smu,
+ 				 bool initialize)
+ {
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 401affdee49d..cdb845f5f23e 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -469,6 +469,7 @@ struct pptable_funcs {
+ 	int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type clk_type,
+ 				   uint32_t dpm_level, uint32_t *freq);
+ 	int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
++	int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
+ };
+ 
+ struct smu_funcs
+@@ -551,6 +552,7 @@ struct smu_funcs
+ 	int (*mode2_reset)(struct smu_context *smu);
+ 	int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
+ 	int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
++	int (*override_pcie_parameters)(struct smu_context *smu);
+ };
+ 
+ #define smu_init_microcode(smu) \
+@@ -783,6 +785,12 @@ struct smu_funcs
+ #define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
+ 		((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
+ 
++#define smu_override_pcie_parameters(smu) \
++		((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0)
++
++#define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) \
++		((smu)->ppt_funcs->update_pcie_parameters ? (smu)->ppt_funcs->update_pcie_parameters((smu), (pcie_gen_cap), (pcie_width_cap)) : 0)
++
+ extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
+ 				   uint16_t *size, uint8_t *frev, uint8_t *crev,
+ 				   uint8_t **addr);
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index e8e5c889cc95..b88aae9bb242 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1628,6 +1628,28 @@ static int navi10_get_power_limit(struct smu_context *smu,
+ 	return 0;
+ }
+ 
++static int navi10_update_pcie_parameters(struct smu_context *smu,
++				     uint32_t pcie_gen_cap,
++				     uint32_t pcie_width_cap)
++{
++	PPTable_t *pptable = smu->smu_table.driver_pptable;
++	int ret, i;
++	uint32_t smu_pcie_arg;
++
++	for (i = 0; i < NUM_LINK_LEVELS; i++) {
++		smu_pcie_arg = (i << 16) |
++			((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
++				(pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
++					pptable->PcieLaneCount[i] : pcie_width_cap);
++		ret = smu_send_smc_msg_with_param(smu,
++					  SMU_MSG_OverridePcieParameters,
++					  smu_pcie_arg);
++	}
++
++	return ret;
++}
++
++
+ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.tables_init = navi10_tables_init,
+ 	.alloc_dpm_context = navi10_allocate_dpm_context,
+@@ -1666,6 +1688,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.get_thermal_temperature_range = navi10_get_thermal_temperature_range,
+ 	.display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
+ 	.get_power_limit = navi10_get_power_limit,
++	.update_pcie_parameters = navi10_update_pcie_parameters,
+ };
+ 
+ void navi10_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 9883f0a4471a..df1f2b99fed7 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -32,6 +32,7 @@
+ #include "vega20_ppt.h"
+ #include "arcturus_ppt.h"
+ #include "navi10_ppt.h"
++#include "amd_pcie.h"
+ 
+ #include "asic_reg/thm/thm_11_0_2_offset.h"
+ #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
+@@ -1791,6 +1792,48 @@ static int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum s
+ 	return ret;
+ }
+ 
++static int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
++{
++	struct amdgpu_device *adev = smu->adev;
++	uint32_t pcie_gen = 0, pcie_width = 0;
++	int ret;
++
++	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
++		pcie_gen = 3;
++	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
++		pcie_gen = 2;
++	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
++		pcie_gen = 1;
++	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
++		pcie_gen = 0;
++
++	/* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
++	 * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
++	 * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
++	 */
++	if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
++		pcie_width = 6;
++	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
++		pcie_width = 5;
++	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
++		pcie_width = 4;
++	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
++		pcie_width = 3;
++	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
++		pcie_width = 2;
++	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
++		pcie_width = 1;
++
++	ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
++
++	if (ret)
++		pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
++
++	return ret;
++
++}
++
++
+ static const struct smu_funcs smu_v11_0_funcs = {
+ 	.init_microcode = smu_v11_0_init_microcode,
+ 	.load_microcode = smu_v11_0_load_microcode,
+@@ -1843,6 +1886,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
+ 	.baco_reset = smu_v11_0_baco_reset,
+ 	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+ 	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
++	.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+ };
+ 
+ void smu_v11_0_set_smu_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 1050566cb69a..a76ffd58404e 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -3157,6 +3157,28 @@ static int vega20_set_df_cstate(struct smu_context *smu,
+ 	return smu_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state);
+ }
+ 
++static int vega20_update_pcie_parameters(struct smu_context *smu,
++				     uint32_t pcie_gen_cap,
++				     uint32_t pcie_width_cap)
++{
++	PPTable_t *pptable = smu->smu_table.driver_pptable;
++	int ret, i;
++	uint32_t smu_pcie_arg;
++
++	for (i = 0; i < NUM_LINK_LEVELS; i++) {
++		smu_pcie_arg = (i << 16) |
++			((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
++				(pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
++					pptable->PcieLaneCount[i] : pcie_width_cap);
++		ret = smu_send_smc_msg_with_param(smu,
++					  SMU_MSG_OverridePcieParameters,
++					  smu_pcie_arg);
++	}
++
++	return ret;
++}
++
++
+ static const struct pptable_funcs vega20_ppt_funcs = {
+ 	.tables_init = vega20_tables_init,
+ 	.alloc_dpm_context = vega20_allocate_dpm_context,
+@@ -3201,6 +3223,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
+ 	.set_watermarks_table = vega20_set_watermarks_table,
+ 	.get_thermal_temperature_range = vega20_get_thermal_temperature_range,
+ 	.set_df_cstate = vega20_set_df_cstate,
++	.update_pcie_parameters = vega20_update_pcie_parameters
+ };
+ 
+ void vega20_set_ppt_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4134-drm-amd-powerplay-enable-Arcturus-runtime-VCN-dpm-on.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4134-drm-amd-powerplay-enable-Arcturus-runtime-VCN-dpm-on.patch
new file mode 100644
index 00000000..86f15b3d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4134-drm-amd-powerplay-enable-Arcturus-runtime-VCN-dpm-on.patch
@@ -0,0 +1,99 @@
+From 7af8f2b4309f81b47562e1a04053d6073c7e47f0 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 10 Oct 2019 16:42:31 +0800
+Subject: [PATCH 4134/4736] drm/amd/powerplay: enable Arcturus runtime VCN dpm
+ on/off
+
+Enable runtime VCN DPM on/off on Arcturus.
+
+Change-Id: Ie7d94d67cb4c622c96acced1b5ef0f4e63db5aad
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c        |  7 +++++
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 30 ++++++++++++++++++++
+ 2 files changed, 37 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index 2608c932a775..d270df892223 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -25,6 +25,7 @@
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
+ #include "amdgpu_vcn.h"
++#include "amdgpu_pm.h"
+ #include "soc15.h"
+ #include "soc15d.h"
+ #include "vcn_v2_0.h"
+@@ -709,6 +710,9 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
+ 	uint32_t rb_bufsz, tmp;
+ 	int i, j, k, r;
+ 
++	if (adev->pm.dpm_enabled)
++		amdgpu_dpm_enable_uvd(adev, true);
++
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ 		if (adev->vcn.harvest_config & (1 << i))
+ 			continue;
+@@ -939,6 +943,9 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev)
+ 			~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
+ 	}
+ 
++	if (adev->pm.dpm_enabled)
++		amdgpu_dpm_enable_uvd(adev, false);
++
+ 	return 0;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 37ac01d37ae8..b33e451c7133 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -1898,6 +1898,35 @@ static bool arcturus_is_dpm_running(struct smu_context *smu)
+ 	return !!(feature_enabled & SMC_DPM_FEATURE);
+ }
+ 
++static int arcturus_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
++{
++	struct smu_power_context *smu_power = &smu->smu_power;
++	struct smu_power_gate *power_gate = &smu_power->power_gate;
++	int ret = 0;
++
++	if (enable) {
++		if (!smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
++			ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
++			if (ret) {
++				pr_err("[EnableVCNDPM] failed!\n");
++				return ret;
++			}
++		}
++		power_gate->vcn_gated = false;
++	} else {
++		if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
++			ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
++			if (ret) {
++				pr_err("[DisableVCNDPM] failed!\n");
++				return ret;
++			}
++		}
++		power_gate->vcn_gated = true;
++	}
++
++	return ret;
++}
++
+ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 	/* translate smu index into arcturus specific index */
+ 	.get_smu_msg_index = arcturus_get_smu_msg_index,
+@@ -1936,6 +1965,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 	.dump_pptable = arcturus_dump_pptable,
+ 	.get_power_limit = arcturus_get_power_limit,
+ 	.is_dpm_running = arcturus_is_dpm_running,
++	.dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
+ };
+ 
+ void arcturus_set_ppt_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4135-drm-amdgpu-display-hook-renoir-dc-to-pplib-funcs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4135-drm-amdgpu-display-hook-renoir-dc-to-pplib-funcs.patch
new file mode 100644
index 00000000..f8616d1f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4135-drm-amdgpu-display-hook-renoir-dc-to-pplib-funcs.patch
@@ -0,0 +1,142 @@
+From 61eca185219bdd4755932490ad86d255017c75ba Mon Sep 17 00:00:00 2001
+From: Hersen Wu <hersenxs.wu@amd.com>
+Date: Tue, 15 Oct 2019 10:34:54 -0400
+Subject: [PATCH 4135/4736] drm/amdgpu/display: hook renoir dc to pplib funcs
+
+enable dc get dmp clock table and set dcn watermarks
+via pplib.
+
+Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
+Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c  | 93 +++++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/dm_pp_smu.h    |  2 +-
+ 2 files changed, 94 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+index 9b2ce0264df6..33564c707051 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+@@ -902,6 +902,90 @@ enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp,
+ 	return PP_SMU_RESULT_FAIL;
+ }
+ 
++#ifdef CONFIG_DRM_AMD_DC_DCN2_1
++enum pp_smu_status pp_rn_get_dpm_clock_table(
++		struct pp_smu *pp, struct dpm_clocks *clock_table)
++{
++	const struct dc_context *ctx = pp->dm;
++	struct amdgpu_device *adev = ctx->driver_context;
++	struct smu_context *smu = &adev->smu;
++
++	if (!smu->ppt_funcs)
++		return PP_SMU_RESULT_UNSUPPORTED;
++
++	if (!smu->ppt_funcs->get_dpm_clock_table)
++		return PP_SMU_RESULT_UNSUPPORTED;
++
++	if (!smu->ppt_funcs->get_dpm_clock_table(smu, clock_table))
++		return PP_SMU_RESULT_OK;
++
++	return PP_SMU_RESULT_FAIL;
++}
++
++enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp,
++		struct pp_smu_wm_range_sets *ranges)
++{
++	const struct dc_context *ctx = pp->dm;
++	struct amdgpu_device *adev = ctx->driver_context;
++	struct smu_context *smu = &adev->smu;
++	struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
++	struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =
++			wm_with_clock_ranges.wm_dmif_clocks_ranges;
++	struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks =
++			wm_with_clock_ranges.wm_mcif_clocks_ranges;
++	int32_t i;
++
++	if (!smu->funcs)
++		return PP_SMU_RESULT_UNSUPPORTED;
++
++	wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
++	wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
++
++	for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
++		if (ranges->reader_wm_sets[i].wm_inst > 3)
++			wm_dce_clocks[i].wm_set_id = WM_SET_A;
++		else
++			wm_dce_clocks[i].wm_set_id =
++					ranges->reader_wm_sets[i].wm_inst;
++
++		wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz =
++			ranges->reader_wm_sets[i].min_drain_clk_mhz;
++
++		wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz =
++			ranges->reader_wm_sets[i].max_drain_clk_mhz;
++
++		wm_dce_clocks[i].wm_min_mem_clk_in_khz =
++			ranges->reader_wm_sets[i].min_fill_clk_mhz;
++
++		wm_dce_clocks[i].wm_max_mem_clk_in_khz =
++			ranges->reader_wm_sets[i].max_fill_clk_mhz;
++	}
++
++	for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {
++		if (ranges->writer_wm_sets[i].wm_inst > 3)
++			wm_soc_clocks[i].wm_set_id = WM_SET_A;
++		else
++			wm_soc_clocks[i].wm_set_id =
++					ranges->writer_wm_sets[i].wm_inst;
++		wm_soc_clocks[i].wm_min_socclk_clk_in_khz =
++				ranges->writer_wm_sets[i].min_fill_clk_mhz;
++
++		wm_soc_clocks[i].wm_max_socclk_clk_in_khz =
++			ranges->writer_wm_sets[i].max_fill_clk_mhz;
++
++		wm_soc_clocks[i].wm_min_mem_clk_in_khz =
++			ranges->writer_wm_sets[i].min_drain_clk_mhz;
++
++		wm_soc_clocks[i].wm_max_mem_clk_in_khz =
++			ranges->writer_wm_sets[i].max_drain_clk_mhz;
++	}
++
++	smu_set_watermarks_for_clock_ranges(&adev->smu, &wm_with_clock_ranges);
++
++	return PP_SMU_RESULT_OK;
++}
++#endif
++
+ void dm_pp_get_funcs(
+ 		struct dc_context *ctx,
+ 		struct pp_smu_funcs *funcs)
+@@ -946,6 +1030,15 @@ void dm_pp_get_funcs(
+ 		funcs->nv_funcs.set_pstate_handshake_support = pp_nv_set_pstate_handshake_support;
+ 		break;
+ #endif
++
++#ifdef CONFIG_DRM_AMD_DC_DCN2_1
++	case DCN_VERSION_2_1:
++		funcs->ctx.ver = PP_SMU_VER_RN;
++		funcs->rn_funcs.pp_smu.dm = ctx;
++		funcs->rn_funcs.set_wm_ranges = pp_rn_set_wm_ranges;
++		funcs->rn_funcs.get_dpm_clock_table = pp_rn_get_dpm_clock_table;
++		break;
++#endif
+ 	default:
+ 		DRM_ERROR("smu version is not supported !\n");
+ 		break;
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+index 6aa1686f59ab..ad082181a448 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+@@ -246,7 +246,7 @@ struct pp_smu_funcs_nv {
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ 
+ #define PP_SMU_NUM_SOCCLK_DPM_LEVELS  8
+-#define PP_SMU_NUM_DCFCLK_DPM_LEVELS  4
++#define PP_SMU_NUM_DCFCLK_DPM_LEVELS  8
+ #define PP_SMU_NUM_FCLK_DPM_LEVELS    4
+ #define PP_SMU_NUM_MEMCLK_DPM_LEVELS  4
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4136-drm-amdgpu-display-fix-build-error-casused-by-CONFIG.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4136-drm-amdgpu-display-fix-build-error-casused-by-CONFIG.patch
new file mode 100644
index 00000000..c941254c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4136-drm-amdgpu-display-fix-build-error-casused-by-CONFIG.patch
@@ -0,0 +1,40 @@
+From 1250d2c1f6d25613622af93f47b3bc9f24197a10 Mon Sep 17 00:00:00 2001
+From: Hersen Wu <hersenxs.wu@amd.com>
+Date: Tue, 15 Oct 2019 12:47:31 -0400
+Subject: [PATCH 4136/4736] drm/amdgpu/display: fix build error casused by
+ CONFIG_DRM_AMD_DC_DCN2_1
+
+when CONFIG_DRM_AMD_DC_DCN2_1 is not enable in .config,
+there is build error. struct dpm_clocks shoud not be
+guarded.
+
+Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
+Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+index ad082181a448..95f3193da951 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+@@ -243,8 +243,6 @@ struct pp_smu_funcs_nv {
+ };
+ #endif
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+-
+ #define PP_SMU_NUM_SOCCLK_DPM_LEVELS  8
+ #define PP_SMU_NUM_DCFCLK_DPM_LEVELS  8
+ #define PP_SMU_NUM_FCLK_DPM_LEVELS    4
+@@ -282,7 +280,6 @@ struct pp_smu_funcs_rn {
+ 	enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
+ 			struct dpm_clocks *clock_table);
+ };
+-#endif
+ 
+ struct pp_smu_funcs {
+ 	struct pp_smu ctx;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4137-drm-amd-display-change-PP_SM-defs-to-8.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4137-drm-amd-display-change-PP_SM-defs-to-8.patch
new file mode 100644
index 00000000..35a27b2b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4137-drm-amd-display-change-PP_SM-defs-to-8.patch
@@ -0,0 +1,31 @@
+From 6296a192954b9f8740eacd7c13acd58e8b4d8cbe Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 3 Oct 2019 13:49:30 -0400
+Subject: [PATCH 4137/4736] drm/amd/display: change PP_SM defs to 8
+
+DPM level is 8 these were incorrect before. Fix them
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+index 95f3193da951..60d6620530a8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+@@ -245,8 +245,8 @@ struct pp_smu_funcs_nv {
+ 
+ #define PP_SMU_NUM_SOCCLK_DPM_LEVELS  8
+ #define PP_SMU_NUM_DCFCLK_DPM_LEVELS  8
+-#define PP_SMU_NUM_FCLK_DPM_LEVELS    4
+-#define PP_SMU_NUM_MEMCLK_DPM_LEVELS  4
++#define PP_SMU_NUM_FCLK_DPM_LEVELS    8
++#define PP_SMU_NUM_MEMCLK_DPM_LEVELS  8
+ 
+ struct dpm_clock {
+   uint32_t  Freq;    // In MHz
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4138-drm-amdgpu-powerplay-add-renoir-funcs-to-support-dc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4138-drm-amdgpu-powerplay-add-renoir-funcs-to-support-dc.patch
new file mode 100644
index 00000000..034871d6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4138-drm-amdgpu-powerplay-add-renoir-funcs-to-support-dc.patch
@@ -0,0 +1,376 @@
+From c96339fb3bc2f93450f7df258c119580584619f1 Mon Sep 17 00:00:00 2001
+From: Hersen Wu <hersenxs.wu@amd.com>
+Date: Wed, 18 Sep 2019 09:53:30 -0400
+Subject: [PATCH 4138/4736] drm/amdgpu/powerplay: add renoir funcs to support
+ dc
+
+there are two paths for renoir dc access smu.
+one dc access smu directly using bios smc
+interface: set disply, dprefclk, etc.
+another goes through pplib for get dpm clock
+table and set watermmark.
+
+Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c  | 16 +---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 35 +++++++
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    | 16 ++--
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c    | 96 +++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 39 --------
+ 5 files changed, 141 insertions(+), 61 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+index 33564c707051..8a5eedb6a37a 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+@@ -590,10 +590,9 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp,
+ 	if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges)
+ 		pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
+ 							   &wm_with_clock_ranges);
+-	else if (adev->smu.funcs &&
+-		 adev->smu.funcs->set_watermarks_for_clock_ranges)
++	else
+ 		smu_set_watermarks_for_clock_ranges(&adev->smu,
+-						    &wm_with_clock_ranges);
++				&wm_with_clock_ranges);
+ }
+ 
+ void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
+@@ -666,7 +665,6 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
+ {
+ 	const struct dc_context *ctx = pp->dm;
+ 	struct amdgpu_device *adev = ctx->driver_context;
+-	struct smu_context *smu = &adev->smu;
+ 	struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
+ 	struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =
+ 			wm_with_clock_ranges.wm_dmif_clocks_ranges;
+@@ -709,15 +707,7 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
+ 			ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;
+ 	}
+ 
+-	if (!smu->funcs)
+-		return PP_SMU_RESULT_UNSUPPORTED;
+-
+-	/* 0: successful or smu.funcs->set_watermarks_for_clock_ranges = NULL;
+-	 * 1: fail
+-	 */
+-	if (smu_set_watermarks_for_clock_ranges(&adev->smu,
+-			&wm_with_clock_ranges))
+-		return PP_SMU_RESULT_UNSUPPORTED;
++	smu_set_watermarks_for_clock_ranges(&adev->smu,	&wm_with_clock_ranges);
+ 
+ 	return PP_SMU_RESULT_OK;
+ }
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 26cacc899dfe..a5255116785b 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1813,6 +1813,41 @@ int smu_set_df_cstate(struct smu_context *smu,
+ 	return ret;
+ }
+ 
++int smu_write_watermarks_table(struct smu_context *smu)
++{
++	int ret = 0;
++	struct smu_table_context *smu_table = &smu->smu_table;
++	struct smu_table *table = NULL;
++
++	table = &smu_table->tables[SMU_TABLE_WATERMARKS];
++
++	if (!table->cpu_addr)
++		return -EINVAL;
++
++	ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
++				true);
++
++	return ret;
++}
++
++int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
++		struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
++{
++	int ret = 0;
++	struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
++	void *table = watermarks->cpu_addr;
++
++	if (!smu->disable_watermark &&
++			smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
++			smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
++		smu_set_watermarks_table(smu, table, clock_ranges);
++		smu->watermarks_bitmap |= WATERMARKS_EXIST;
++		smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
++	}
++
++	return ret;
++}
++
+ const struct amd_ip_funcs smu_ip_funcs = {
+ 	.name = "smu",
+ 	.early_init = smu_early_init,
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index cdb845f5f23e..bf13bf33ba0c 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -470,6 +470,7 @@ struct pptable_funcs {
+ 				   uint32_t dpm_level, uint32_t *freq);
+ 	int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
+ 	int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
++	int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
+ };
+ 
+ struct smu_funcs
+@@ -495,7 +496,6 @@ struct smu_funcs
+ 	int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
+ 	int (*set_tool_table_location)(struct smu_context *smu);
+ 	int (*notify_memory_pool_location)(struct smu_context *smu);
+-	int (*write_watermarks_table)(struct smu_context *smu);
+ 	int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
+ 	int (*system_features_control)(struct smu_context *smu, bool en);
+ 	int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
+@@ -533,8 +533,6 @@ struct smu_funcs
+ 	int (*get_current_shallow_sleep_clocks)(struct smu_context *smu,
+ 						struct smu_clock_info *clocks);
+ 	int (*notify_smu_enable_pwe)(struct smu_context *smu);
+-	int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
+-					       struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
+ 	int (*conv_power_profile_to_pplib_workload)(int power_profile);
+ 	uint32_t (*get_fan_control_mode)(struct smu_context *smu);
+ 	int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
+@@ -599,9 +597,6 @@ struct smu_funcs
+ 	((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
+ #define smu_gfx_off_control(smu, enable) \
+ 	((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
+-
+-#define smu_write_watermarks_table(smu) \
+-	((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0)
+ #define smu_set_last_dcef_min_deep_sleep_clk(smu) \
+ 	((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
+ #define smu_system_features_control(smu, en) \
+@@ -741,8 +736,6 @@ struct smu_funcs
+ 	((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
+ #define smu_notify_smu_enable_pwe(smu) \
+ 	((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
+-#define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
+-	((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
+ #define smu_dpm_set_uvd_enable(smu, enable) \
+ 	((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
+ #define smu_dpm_set_vce_enable(smu, enable) \
+@@ -781,9 +774,10 @@ struct smu_funcs
+ 	((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0)
+ #define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) \
+ 		((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EINVAL)
+-
+ #define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
+ 		((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
++#define smu_get_dpm_clock_table(smu, clock_table) \
++		((smu)->ppt_funcs->get_dpm_clock_table ? (smu)->ppt_funcs->get_dpm_clock_table((smu), (clock_table)) : -EINVAL)
+ 
+ #define smu_override_pcie_parameters(smu) \
+ 		((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0)
+@@ -823,6 +817,10 @@ int smu_sys_get_pp_table(struct smu_context *smu, void **table);
+ int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size);
+ int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
+ enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
++int smu_write_watermarks_table(struct smu_context *smu);
++int smu_set_watermarks_for_clock_ranges(
++		struct smu_context *smu,
++		struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
+ 
+ /* smu to display interface */
+ extern int smu_display_configuration_change(struct smu_context *smu, const
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 6aedffd739db..fa314c275a82 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -416,6 +416,40 @@ static int renoir_get_profiling_clk_mask(struct smu_context *smu,
+ 	return 0;
+ }
+ 
++/**
++ * This interface get dpm clock table for dc
++ */
++static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
++{
++	DpmClocks_t *table = smu->smu_table.clocks_table;
++	int i;
++
++	if (!clock_table || !table)
++		return -EINVAL;
++
++	for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) {
++		clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq;
++		clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol;
++	}
++
++	for (i = 0; i < PP_SMU_NUM_SOCCLK_DPM_LEVELS; i++) {
++		clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq;
++		clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol;
++	}
++
++	for (i = 0; i < PP_SMU_NUM_FCLK_DPM_LEVELS; i++) {
++		clock_table->FClocks[i].Freq = table->FClocks[i].Freq;
++		clock_table->FClocks[i].Vol = table->FClocks[i].Vol;
++	}
++
++	for (i = 0; i<  PP_SMU_NUM_MEMCLK_DPM_LEVELS; i++) {
++		clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq;
++		clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol;
++	}
++
++	return 0;
++}
++
+ static int renoir_force_clk_levels(struct smu_context *smu,
+ 				   enum smu_clk_type clk_type, uint32_t mask)
+ {
+@@ -546,6 +580,66 @@ static int renoir_set_performance_level(struct smu_context *smu, enum amd_dpm_fo
+ 	return ret;
+ }
+ 
++/* save watermark settings into pplib smu structure,
++ * also pass data to smu controller
++ */
++static int renoir_set_watermarks_table(
++		struct smu_context *smu,
++		void *watermarks,
++		struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
++{
++	int i;
++	int ret = 0;
++	Watermarks_t *table = watermarks;
++
++	if (!table || !clock_ranges)
++		return -EINVAL;
++
++	if (clock_ranges->num_wm_dmif_sets > 4 ||
++			clock_ranges->num_wm_mcif_sets > 4)
++		return -EINVAL;
++
++	/* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
++	for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
++		table->WatermarkRow[WM_DCFCLK][i].MinClock =
++			cpu_to_le16((uint16_t)
++			(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz));
++		table->WatermarkRow[WM_DCFCLK][i].MaxClock =
++			cpu_to_le16((uint16_t)
++			(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz));
++		table->WatermarkRow[WM_DCFCLK][i].MinMclk =
++			cpu_to_le16((uint16_t)
++			(clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz));
++		table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
++			cpu_to_le16((uint16_t)
++			(clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz));
++		table->WatermarkRow[WM_DCFCLK][i].WmSetting = (uint8_t)
++				clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
++	}
++
++	for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
++		table->WatermarkRow[WM_SOCCLK][i].MinClock =
++			cpu_to_le16((uint16_t)
++			(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz));
++		table->WatermarkRow[WM_SOCCLK][i].MaxClock =
++			cpu_to_le16((uint16_t)
++			(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz));
++		table->WatermarkRow[WM_SOCCLK][i].MinMclk =
++			cpu_to_le16((uint16_t)
++			(clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz));
++		table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
++			cpu_to_le16((uint16_t)
++			(clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz));
++		table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t)
++				clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
++	}
++
++	/* pass data to smu controller */
++	ret = smu_write_watermarks_table(smu);
++
++	return ret;
++}
++
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_smu_msg_index = renoir_get_smu_msg_index,
+ 	.get_smu_table_index = renoir_get_smu_table_index,
+@@ -562,6 +656,8 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.force_clk_levels = renoir_force_clk_levels,
+ 	.set_power_profile_mode = renoir_set_power_profile_mode,
+ 	.set_performance_level = renoir_set_performance_level,
++	.get_dpm_clock_table = renoir_get_dpm_clock_table,
++	.set_watermarks_table = renoir_set_watermarks_table,
+ };
+ 
+ void renoir_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index df1f2b99fed7..ac02bcd24da0 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -771,23 +771,6 @@ static int smu_v11_0_write_pptable(struct smu_context *smu)
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
+-{
+-	int ret = 0;
+-	struct smu_table_context *smu_table = &smu->smu_table;
+-	struct smu_table *table = NULL;
+-
+-	table = &smu_table->tables[SMU_TABLE_WATERMARKS];
+-
+-	if (!table->cpu_addr)
+-		return -EINVAL;
+-
+-	ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
+-				true);
+-
+-	return ret;
+-}
+-
+ static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
+ {
+ 	int ret;
+@@ -1337,26 +1320,6 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
+ 	return ret;
+ }
+ 
+-static int
+-smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
+-					  dm_pp_wm_sets_with_clock_ranges_soc15
+-					  *clock_ranges)
+-{
+-	int ret = 0;
+-	struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
+-	void *table = watermarks->cpu_addr;
+-
+-	if (!smu->disable_watermark &&
+-	    smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
+-	    smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+-		smu_set_watermarks_table(smu, table, clock_ranges);
+-		smu->watermarks_bitmap |= WATERMARKS_EXIST;
+-		smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
+-	}
+-
+-	return ret;
+-}
+-
+ static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
+ {
+ 	int ret = 0;
+@@ -1854,7 +1817,6 @@ static const struct smu_funcs smu_v11_0_funcs = {
+ 	.parse_pptable = smu_v11_0_parse_pptable,
+ 	.populate_smc_tables = smu_v11_0_populate_smc_pptable,
+ 	.write_pptable = smu_v11_0_write_pptable,
+-	.write_watermarks_table = smu_v11_0_write_watermarks_table,
+ 	.set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
+ 	.set_tool_table_location = smu_v11_0_set_tool_table_location,
+ 	.init_display_count = smu_v11_0_init_display_count,
+@@ -1870,7 +1832,6 @@ static const struct smu_funcs smu_v11_0_funcs = {
+ 	.read_sensor = smu_v11_0_read_sensor,
+ 	.set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
+ 	.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
+-	.set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
+ 	.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
+ 	.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
+ 	.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4139-drm-amdgpu-add-GFX_PIPELINE-capacity-check-for-updat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4139-drm-amdgpu-add-GFX_PIPELINE-capacity-check-for-updat.patch
new file mode 100644
index 00000000..702b5411
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4139-drm-amdgpu-add-GFX_PIPELINE-capacity-check-for-updat.patch
@@ -0,0 +1,31 @@
+From 8f499afce3448349e730f7865d953f1ef96085f9 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Tue, 15 Oct 2019 17:24:25 +0800
+Subject: [PATCH 4139/4736] drm/amdgpu: add GFX_PIPELINE capacity check for
+ updating gfx cgpg
+
+Before disable gfx pipeline power gating need check the flag AMD_PG_SUPPORT_GFX_PIPELINE.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 24802e4d25e5..f5322313f93c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4294,7 +4294,8 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
+ 			gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
+ 	} else {
+ 		gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
+-		gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
++		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
++			gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
+ 	}
+ 
+ 	amdgpu_gfx_rlc_exit_safe_mode(adev);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4140-drm-amdgpu-fix-S3-failed-as-RLC-safe-mode-entry-stuc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4140-drm-amdgpu-fix-S3-failed-as-RLC-safe-mode-entry-stuc.patch
new file mode 100644
index 00000000..6cd21b6e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4140-drm-amdgpu-fix-S3-failed-as-RLC-safe-mode-entry-stuc.patch
@@ -0,0 +1,64 @@
+From 3056eac53726a1cb97a3d989fb62d0cd57cf27e4 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Tue, 15 Oct 2019 17:11:49 +0800
+Subject: [PATCH 4140/4736] drm/amdgpu: fix S3 failed as RLC safe mode entry
+ stucked in polloing gfx acq
+
+Fix gfx cgpg setting sequence for RLC deadlock at safe mode entry in polling gfx response.
+The patch can fix VCN IB test failed and DAL get dispaly count failed issue.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c      | 5 -----
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++++
+ 2 files changed, 4 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index f5322313f93c..16043b824f97 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4285,9 +4285,6 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
+ {
+ 	amdgpu_gfx_rlc_enter_safe_mode(adev);
+ 
+-	if (is_support_sw_smu(adev) && !enable)
+-		smu_set_gfx_cgpg(&adev->smu, enable);
+-
+ 	if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
+ 		gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
+ 		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
+@@ -4564,8 +4561,6 @@ static int gfx_v9_0_set_powergating_state(void *handle,
+ 			gfx_v9_0_enable_cp_power_gating(adev, false);
+ 
+ 		/* update gfx cgpg state */
+-		if (is_support_sw_smu(adev) && enable)
+-			smu_set_gfx_cgpg(&adev->smu, enable);
+ 		gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
+ 
+ 		/* update mgcg state */
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index a5255116785b..d0a25dd8fcfc 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1188,6 +1188,7 @@ static int smu_hw_init(void *handle)
+ 	if (adev->flags & AMD_IS_APU) {
+ 		smu_powergate_sdma(&adev->smu, false);
+ 		smu_powergate_vcn(&adev->smu, false);
++		smu_set_gfx_cgpg(&adev->smu, true);
+ 	}
+ 
+ 	if (!smu->pm_enabled)
+@@ -1350,6 +1351,9 @@ static int smu_resume(void *handle)
+ 	if (ret)
+ 		goto failed;
+ 
++	if (smu->is_apu)
++		smu_set_gfx_cgpg(&adev->smu, true);
++
+ 	mutex_unlock(&smu->mutex);
+ 
+ 	pr_info("SMU is resumed successfully!\n");
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4141-drm-amdgpu-set-debug-register-values-at-init-time.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4141-drm-amdgpu-set-debug-register-values-at-init-time.patch
new file mode 100644
index 00000000..17141737
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4141-drm-amdgpu-set-debug-register-values-at-init-time.patch
@@ -0,0 +1,34 @@
+From 4bde2a3a41934d91fdbf726420c657fa1ce6e143 Mon Sep 17 00:00:00 2001
+From: Philip Cox <Philip.Cox@amd.com>
+Date: Wed, 14 Aug 2019 09:09:19 -0400
+Subject: [PATCH 4141/4736] drm/amdgpu: set debug register values at init time
+
+We need to initialize the SPI_GDBG_TRAP_MASK EXCP_EN and REPLACE
+to 0, along with SPI_GDBG_TRAP_DATA0, and SPI_GDBG_TRAP_DATA1 when
+we initialize the debug vmid.
+
+Change-Id: Ib3887397578d63c110a4247d6b61bf62111bc1c5
+Signed-off-by: Philip Cox <Philip.Cox@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 16043b824f97..5e7a01c322ea 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -2273,6 +2273,11 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
+ 	data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
+ 			TRAP_EN, 1);
+ 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
++
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
++
+ }
+ 
+ static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4142-drm-amdkfd-No-longer-support-debug-reg-data-vars.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4142-drm-amdkfd-No-longer-support-debug-reg-data-vars.patch
new file mode 100644
index 00000000..deb670f1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4142-drm-amdkfd-No-longer-support-debug-reg-data-vars.patch
@@ -0,0 +1,225 @@
+From 6d39c416f207a26d59b46ecff9aeb6023b29043d Mon Sep 17 00:00:00 2001
+From: Philip Cox <Philip.Cox@amd.com>
+Date: Wed, 14 Aug 2019 09:05:52 -0400
+Subject: [PATCH 4142/4736] drm/amdkfd: No longer support debug reg data vars
+
+The KFD debugger uses data0/data1 for the debug trap handler, we
+we need to prevent the them being updated from userspace.
+
+Change-Id: I91086062c744a70a2706050aa35f61014551c5ef
+Signed-off-by: Philip Cox <Philip.Cox@amd.com>
+---
+ .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c   |  1 -
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 22 ----------------
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h |  3 ---
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c      |  6 -----
+ .../gpu/drm/amd/include/kgd_kfd_interface.h   |  3 ---
+ include/uapi/linux/kfd_ioctl.h                | 26 +++++++------------
+ 6 files changed, 9 insertions(+), 52 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+index db39c6653cce..7288810e0df5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+@@ -288,7 +288,6 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = {
+ 	.get_hive_id = amdgpu_amdkfd_get_hive_id,
+ 	.enable_debug_trap = kgd_gfx_v9_enable_debug_trap,
+ 	.disable_debug_trap = kgd_gfx_v9_disable_debug_trap,
+-	.set_debug_trap_data = kgd_gfx_v9_set_debug_trap_data,
+ 	.set_wave_launch_trap_override = kgd_gfx_v9_set_wave_launch_trap_override,
+ 	.set_wave_launch_mode = kgd_gfx_v9_set_wave_launch_mode,
+ 	.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+index 530b8ada1f8f..dae572c776cc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+@@ -845,9 +845,6 @@ uint32_t kgd_gfx_v9_enable_debug_trap(struct kgd_dev *kgd,
+ 	data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_RA, 1);
+ 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
+ 
+-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
+-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
+-
+ 	data = 0;
+ 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data);
+ 
+@@ -864,9 +861,6 @@ uint32_t kgd_gfx_v9_disable_debug_trap(struct kgd_dev *kgd)
+ 
+ 	mutex_lock(&adev->grbm_idx_mutex);
+ 
+-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
+-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
+-
+ 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
+ 
+ 	mutex_unlock(&adev->grbm_idx_mutex);
+@@ -874,21 +868,6 @@ uint32_t kgd_gfx_v9_disable_debug_trap(struct kgd_dev *kgd)
+ 	return 0;
+ }
+ 
+-uint32_t kgd_gfx_v9_set_debug_trap_data(struct kgd_dev *kgd,
+-					int trap_data0,
+-					int trap_data1)
+-{
+-	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+-
+-	mutex_lock(&adev->grbm_idx_mutex);
+-
+-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), trap_data0);
+-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), trap_data1);
+-
+-	mutex_unlock(&adev->grbm_idx_mutex);
+-	return 0;
+-}
+-
+ uint32_t kgd_gfx_v9_set_wave_launch_trap_override(struct kgd_dev *kgd,
+ 						uint32_t trap_override,
+ 						uint32_t trap_mask)
+@@ -1037,7 +1016,6 @@ const struct kfd2kgd_calls gfx_v9_kfd2kgd = {
+ 	.get_hive_id = amdgpu_amdkfd_get_hive_id,
+ 	.enable_debug_trap = kgd_gfx_v9_enable_debug_trap,
+ 	.disable_debug_trap = kgd_gfx_v9_disable_debug_trap,
+-	.set_debug_trap_data = kgd_gfx_v9_set_debug_trap_data,
+ 	.set_wave_launch_trap_override = kgd_gfx_v9_set_wave_launch_trap_override,
+ 	.set_wave_launch_mode = kgd_gfx_v9_set_wave_launch_mode,
+ 	.get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
+index 7611ba466aa4..2b41d810c68e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
+@@ -67,9 +67,6 @@ uint32_t kgd_gfx_v9_enable_debug_trap(struct kgd_dev *kgd,
+ 									  uint32_t trap_debug_wave_launch_mode,
+ 									  uint32_t vmid);
+ uint32_t kgd_gfx_v9_disable_debug_trap(struct kgd_dev *kgd);
+-uint32_t kgd_gfx_v9_set_debug_trap_data(struct kgd_dev *kgd,
+-										int trap_data0,
+-										int trap_data1);
+ uint32_t kgd_gfx_v9_set_wave_launch_trap_override(struct kgd_dev *kgd,
+ 												  uint32_t trap_override,
+ 												  uint32_t trap_mask);
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index c60c4480d124..52acb0064939 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -2763,12 +2763,6 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 		}
+ 		break;
+ 
+-	case KFD_IOC_DBG_TRAP_SET_TRAP_DATA:
+-		r = dev->kfd2kgd->set_debug_trap_data(dev->kgd,
+-				data1,
+-				data2);
+-		break;
+-
+ 	case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE:
+ 		r = dev->kfd2kgd->set_wave_launch_trap_override(
+ 				dev->kgd,
+diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+index db00c2ec9277..975961a298d9 100644
+--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
++++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+@@ -327,9 +327,6 @@ struct kfd2kgd_calls {
+ 					uint32_t trap_debug_wave_launch_mode,
+ 					uint32_t vmid);
+ 	uint32_t (*disable_debug_trap)(struct kgd_dev *kgd);
+-	uint32_t (*set_debug_trap_data)(struct kgd_dev *kgd,
+-					int trap_data0,
+-					int trap_data1);
+ 	uint32_t (*set_wave_launch_trap_override)(struct kgd_dev *kgd,
+ 						uint32_t trap_override,
+ 						uint32_t trap_mask);
+diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
+index 8c9a5ab34d9e..760b3d6159fa 100644
+--- a/include/uapi/linux/kfd_ioctl.h
++++ b/include/uapi/linux/kfd_ioctl.h
+@@ -28,8 +28,8 @@
+ 
+ #define KFD_IOCTL_MAJOR_VERSION 1
+ #define KFD_IOCTL_MINOR_VERSION 2
+-#define KFD_IOCTL_DBG_MAJOR_VERSION	0
+-#define KFD_IOCTL_DBG_MINOR_VERSION	2
++#define KFD_IOCTL_DBG_MAJOR_VERSION	1
++#define KFD_IOCTL_DBG_MINOR_VERSION	0
+ 
+ struct kfd_ioctl_get_version_args {
+ 	__u32 major_version;	/* from KFD */
+@@ -219,21 +219,13 @@ struct kfd_ioctl_dbg_wave_control_args {
+  */
+ #define KFD_IOC_DBG_TRAP_ENABLE 0
+ 
+-/* KFD_IOC_DBG_TRAP_SET_TRAP_DATA:
+- * ptr:   unused
+- * data1: SPI_GDBG_TRAP_DATA0
+- * data2: SPI_GDBG_TRAP_DATA1
+- * data3: unused
+- */
+-#define KFD_IOC_DBG_TRAP_SET_TRAP_DATA 1
+-
+ /* KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE:
+  * ptr:   unused
+  * data1: override mode: 0=OR, 1=REPLACE
+  * data2: mask
+  * data3: unused
+  */
+-#define KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE 2
++#define KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE 1
+ 
+ /* KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE:
+  * ptr:   unused
+@@ -241,7 +233,7 @@ struct kfd_ioctl_dbg_wave_control_args {
+  * data2: unused
+  * data3: unused
+  */
+-#define KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE 3
++#define KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE 2
+ 
+ /* KFD_IOC_DBG_TRAP_NODE_SUSPEND:
+  * ptr:   pointer to an array of Queues IDs
+@@ -249,7 +241,7 @@ struct kfd_ioctl_dbg_wave_control_args {
+  * data2: number of queues
+  * data3: grace period
+  */
+-#define KFD_IOC_DBG_TRAP_NODE_SUSPEND 4
++#define KFD_IOC_DBG_TRAP_NODE_SUSPEND 3
+ 
+ /* KFD_IOC_DBG_TRAP_NODE_RESUME:
+  * ptr:   pointer to an array of Queues IDs
+@@ -257,7 +249,7 @@ struct kfd_ioctl_dbg_wave_control_args {
+  * data2: number of queues
+  * data3: unused
+  */
+-#define KFD_IOC_DBG_TRAP_NODE_RESUME 5
++#define KFD_IOC_DBG_TRAP_NODE_RESUME 4
+ 
+ /* KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT:
+  * ptr: unused
+@@ -265,7 +257,7 @@ struct kfd_ioctl_dbg_wave_control_args {
+  * data2: flags (IN)
+  * data3: suspend[2:2], event type [1:0] (OUT)
+  */
+-#define KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT 6
++#define KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT 5
+ 
+ /* KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT:
+  * ptr: user buffer (IN)
+@@ -273,7 +265,7 @@ struct kfd_ioctl_dbg_wave_control_args {
+  * data2: number of queue snapshots (IN/OUT) - 0 for IN ignores buffer writes
+  * data3: unused
+  */
+-#define KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT 7
++#define KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT 6
+ 
+ /* KFD_IOC_DBG_TRAP_GET_VERSION:
+  * prt: unsused
+@@ -281,7 +273,7 @@ struct kfd_ioctl_dbg_wave_control_args {
+  * data2: minor version (OUT)
+  * data3: unused
+  */
+-#define KFD_IOC_DBG_TRAP_GET_VERSION	8
++#define KFD_IOC_DBG_TRAP_GET_VERSION	7
+ 
+ struct kfd_ioctl_dbg_trap_args {
+ 	__u64 ptr;     /* to KFD -- used for pointer arguments: queue arrays */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4143-drm-amdkfd-Debugger-block-non-default-trap-masks.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4143-drm-amdkfd-Debugger-block-non-default-trap-masks.patch
new file mode 100644
index 00000000..2ab9fda2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4143-drm-amdkfd-Debugger-block-non-default-trap-masks.patch
@@ -0,0 +1,40 @@
+From 572c9105eb8273143b2327887ef08c9c06362ed0 Mon Sep 17 00:00:00 2001
+From: Philip Cox <Philip.Cox@amd.com>
+Date: Wed, 14 Aug 2019 09:32:55 -0400
+Subject: [PATCH 4143/4736] drm/amdkfd: Debugger: block non default trap masks
+
+On the current hardware, we only support the default trap mask,
+so we need to block non default values until supported in by
+future hardware.
+
+Change-Id: Iad94057bb33564b972cc3e7e0f401340f215c8ba
+Signed-off-by: Philip Cox <Philip.Cox@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index 52acb0064939..22f7aa576c7e 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -2764,6 +2764,17 @@ static int kfd_ioctl_dbg_set_debug_trap(struct file *filep,
+ 		break;
+ 
+ 	case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE:
++		if (data2 != 0) {
++			/* On current hardware, we only support a trap
++			 * mask value of 0.  This is because the debug
++			 * trap mask is global and shared by all processes
++			 * on current hardware.
++			 */
++			pr_err("Invalid trap override option: %i\n",
++					data2);
++			r = -EINVAL;
++			goto unlock_out;
++		}
+ 		r = dev->kfd2kgd->set_wave_launch_trap_override(
+ 				dev->kgd,
+ 				data1,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4144-drm-amdgpu-user-pages-array-memory-leak-fix.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4144-drm-amdgpu-user-pages-array-memory-leak-fix.patch
new file mode 100644
index 00000000..482f0848
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4144-drm-amdgpu-user-pages-array-memory-leak-fix.patch
@@ -0,0 +1,62 @@
+From b375022c24b01407c736e4a959632368abab0ec1 Mon Sep 17 00:00:00 2001
+From: Philip Yang <Philip.Yang@amd.com>
+Date: Thu, 3 Oct 2019 14:18:25 -0400
+Subject: [PATCH 4144/4736] drm/amdgpu: user pages array memory leak fix
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+user_pages array should always be freed after validation regardless if
+user pages are changed after bo is created because with HMM change parse
+bo always allocate user pages array to get user pages for userptr bo.
+
+v2: remove unused local variable and amend commit
+
+v3: add back get user pages in gem_userptr_ioctl, to detect application
+bug where an userptr VMA is not ananymous memory and reject it.
+
+Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1844962
+
+Signed-off-by: Philip Yang <Philip.Yang@amd.com>
+Tested-by: Joe Barnett <thejoe@gmail.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 8 ++------
+ 1 file changed, 2 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+index ba43f3f6467b..e8dfbcfad034 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+@@ -475,7 +475,6 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
+ 
+ 	list_for_each_entry(lobj, validated, tv.head) {
+ 		struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
+-		bool binding_userptr = false;
+ 		struct mm_struct *usermm;
+ 
+ 		usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
+@@ -492,17 +491,14 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
+ 
+ 			amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
+ 						     lobj->user_pages);
+-			binding_userptr = true;
+ 		}
+ 
+ 		r = amdgpu_cs_validate(p, bo);
+ 		if (r)
+ 			return r;
+ 
+-		if (binding_userptr) {
+-			kvfree(lobj->user_pages);
+-			lobj->user_pages = NULL;
+-		}
++		kvfree(lobj->user_pages);
++		lobj->user_pages = NULL;
+ 	}
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4145-dmr-amdgpu-Fix-crash-on-SRIOV-for-ERREVENT_ATHUB_INT.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4145-dmr-amdgpu-Fix-crash-on-SRIOV-for-ERREVENT_ATHUB_INT.patch
new file mode 100644
index 00000000..b52437d4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4145-dmr-amdgpu-Fix-crash-on-SRIOV-for-ERREVENT_ATHUB_INT.patch
@@ -0,0 +1,35 @@
+From a8345914d289569a43abf805e2492c036e8d1cae Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Fri, 11 Oct 2019 10:32:59 -0400
+Subject: [PATCH 4145/4736] dmr/amdgpu: Fix crash on SRIOV for
+ ERREVENT_ATHUB_INTERRUPT interrupt.
+
+Ignre the ERREVENT_ATHUB_INTERRUPT for systems without RAS.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-and-tested-by: Jack Zhang <Jack.Zhang1@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index f3f3a98f93b3..1ca613014126 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1886,6 +1886,12 @@ int amdgpu_ras_fini(struct amdgpu_device *adev)
+ 
+ void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
+ {
++	uint32_t hw_supported, supported;
++
++	amdgpu_ras_check_supported(adev, &hw_supported, &supported);
++	if (!hw_supported)
++		return;
++
+ 	if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
+ 		DRM_WARN("RAS event of type ERREVENT_ATHUB_INTERRUPT detected!\n");
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4146-drm-amdgpu-move-pci_save_state-into-suspend-path.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4146-drm-amdgpu-move-pci_save_state-into-suspend-path.patch
new file mode 100644
index 00000000..d96baf07
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4146-drm-amdgpu-move-pci_save_state-into-suspend-path.patch
@@ -0,0 +1,31 @@
+From a2d71268b375d0bb2a5a0f2ad251ada05b44be49 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 14:33:39 -0500
+Subject: [PATCH 4146/4736] drm/amdgpu: move pci_save_state into suspend path
+
+for amdgpu_device_suspend.  This follows the logic
+in the resume path.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 521af22ad916..cb4192e6062a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3179,8 +3179,8 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
+ 	 */
+ 	amdgpu_bo_evict_vram(adev);
+ 
+-	pci_save_state(dev->pdev);
+ 	if (suspend) {
++		pci_save_state(dev->pdev);
+ 		/* Shut down the device */
+ 		pci_disable_device(dev->pdev);
+ 		pci_set_power_state(dev->pdev, PCI_D3hot);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4147-drm-amdgpu-move-gpu-reset-out-of-amdgpu_device_suspe.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4147-drm-amdgpu-move-gpu-reset-out-of-amdgpu_device_suspe.patch
new file mode 100644
index 00000000..e4be600c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4147-drm-amdgpu-move-gpu-reset-out-of-amdgpu_device_suspe.patch
@@ -0,0 +1,54 @@
+From d36140c553925eecd978e388bc78d10af37eb90f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 14:57:21 -0500
+Subject: [PATCH 4147/4736] drm/amdgpu: move gpu reset out of
+ amdgpu_device_suspend
+
+Move it into the caller.  There are cases were we don't
+want it.  We need it for hibernation, but we don't need
+it for runtime pm, so drop it for runtime pm.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c    | 7 ++++++-
+ 2 files changed, 6 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index cb4192e6062a..46723a10d98a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3184,10 +3184,6 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
+ 		/* Shut down the device */
+ 		pci_disable_device(dev->pdev);
+ 		pci_set_power_state(dev->pdev, PCI_D3hot);
+-	} else {
+-		r = amdgpu_asic_reset(adev);
+-		if (r)
+-			DRM_ERROR("amdgpu asic reset failed\n");
+ 	}
+ 
+ 	return 0;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 658fa3fd5fad..5ab426726849 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1201,8 +1201,13 @@ static int amdgpu_pmops_resume(struct device *dev)
+ static int amdgpu_pmops_freeze(struct device *dev)
+ {
+ 	struct drm_device *drm_dev = dev_get_drvdata(dev);
++	struct amdgpu_device *adev = drm_dev->dev_private;
++	int r;
+ 
+-	return amdgpu_device_suspend(drm_dev, false, true);
++	r = amdgpu_device_suspend(drm_dev, false, true);
++	if (r)
++		return r;
++	return amdgpu_asic_reset(adev);
+ }
+ 
+ static int amdgpu_pmops_thaw(struct device *dev)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4148-drm-amdgpu-remove-in_baco_reset-hack.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4148-drm-amdgpu-remove-in_baco_reset-hack.patch
new file mode 100644
index 00000000..247673fd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4148-drm-amdgpu-remove-in_baco_reset-hack.patch
@@ -0,0 +1,60 @@
+From a3b613233260dda95131f1651b3eb869ad0c9bbe Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 11:01:11 -0500
+Subject: [PATCH 4148/4736] drm/amdgpu: remove in_baco_reset hack
+
+It was a vega20 specific hack.  Check if we are in reset
+and what reset method we are using.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h                | 2 --
+ drivers/gpu/drm/amd/amdgpu/soc15.c                 | 2 --
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 4 ++--
+ 3 files changed, 2 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index a994117c4edc..e4172f9bece6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1008,8 +1008,6 @@ struct amdgpu_device {
+ 	int asic_reset_res;
+ 	struct work_struct		xgmi_reset_work;
+ 
+-	bool                            in_baco_reset;
+-
+ 	long				gfx_timeout;
+ 	long				sdma_timeout;
+ 	long				video_timeout;
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 82b5bc4ddf9b..5fadb237d103 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -515,8 +515,6 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+ 
+ 	dev_info(adev->dev, "GPU BACO reset\n");
+ 
+-	adev->in_baco_reset = 1;
+-
+ 	return 0;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+index 3d3c647a63ff..9295bd90b792 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+@@ -493,8 +493,8 @@ static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
+ 			"Failed to init sclk threshold!",
+ 			return ret);
+ 
+-	if (adev->in_baco_reset) {
+-		adev->in_baco_reset = 0;
++	if (adev->in_gpu_reset &&
++	    (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) {
+ 
+ 		ret = vega20_baco_apply_vdci_flush_workaround(hwmgr);
+ 		if (ret)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4149-drm-amdgpu-soc15-add-support-for-baco-reset-with-swS.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4149-drm-amdgpu-soc15-add-support-for-baco-reset-with-swS.patch
new file mode 100644
index 00000000..f3fe7ccb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4149-drm-amdgpu-soc15-add-support-for-baco-reset-with-swS.patch
@@ -0,0 +1,100 @@
+From 34656170efd682732e9b3e565cb013055295dbbe Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 15 Oct 2019 14:27:01 -0400
+Subject: [PATCH 4149/4736] drm/amdgpu/soc15: add support for baco reset with
+ swSMU
+
+Add support for vega20 when the swSMU path is used.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 53 ++++++++++++++++++++----------
+ 1 file changed, 35 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 5fadb237d103..438722c0b76a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -477,15 +477,22 @@ static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
+ 
+ static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
+ {
+-	void *pp_handle = adev->powerplay.pp_handle;
+-	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
++	if (is_support_sw_smu(adev)) {
++		struct smu_context *smu = &adev->smu;
+ 
+-	if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
+-		*cap = false;
+-		return -ENOENT;
+-	}
++		*cap = smu_baco_is_support(smu);
++		return 0;
++	} else {
++		void *pp_handle = adev->powerplay.pp_handle;
++		const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
++
++		if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
++			*cap = false;
++			return -ENOENT;
++		}
+ 
+-	return pp_funcs->get_asic_baco_capability(pp_handle, cap);
++		return pp_funcs->get_asic_baco_capability(pp_handle, cap);
++	}
+ }
+ 
+ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+@@ -494,27 +501,37 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+ 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+ 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+ 
+-	if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
+-		return -ENOENT;
+-
+ 	/* avoid NBIF got stuck when do RAS recovery in BACO reset */
+ 	if (ras && ras->supported)
+ 		adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
+ 
+-	/* enter BACO state */
+-	if (pp_funcs->set_asic_baco_state(pp_handle, 1))
+-		return -EIO;
++	dev_info(adev->dev, "GPU BACO reset\n");
++
++	if (is_support_sw_smu(adev)) {
++		struct smu_context *smu = &adev->smu;
++
++		if (smu_baco_reset(smu))
++			return -EIO;
++	} else {
++		void *pp_handle = adev->powerplay.pp_handle;
++		const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
++
++		if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
++			return -ENOENT;
++
++		/* enter BACO state */
++		if (pp_funcs->set_asic_baco_state(pp_handle, 1))
++			return -EIO;
+ 
+-	/* exit BACO state */
+-	if (pp_funcs->set_asic_baco_state(pp_handle, 0))
+-		return -EIO;
++		/* exit BACO state */
++		if (pp_funcs->set_asic_baco_state(pp_handle, 0))
++			return -EIO;
++	}
+ 
+ 	/* re-enable doorbell interrupt after BACO exit */
+ 	if (ras && ras->supported)
+ 		adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
+ 
+-	dev_info(adev->dev, "GPU BACO reset\n");
+-
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4150-drm-amdgpu-add-new-BIF-4.1-register-for-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4150-drm-amdgpu-add-new-BIF-4.1-register-for-BACO.patch
new file mode 100644
index 00000000..4819597a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4150-drm-amdgpu-add-new-BIF-4.1-register-for-BACO.patch
@@ -0,0 +1,44 @@
+From c6859827ffe21a626ef9a31179f937859d553c1d Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Feb 2019 14:40:26 -0500
+Subject: [PATCH 4150/4736] drm/amdgpu: add new BIF 4.1 register for BACO
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h       | 1 +
+ drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h
+index a761ba07f937..fce965984e76 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h
+@@ -27,6 +27,7 @@
+ #define mmMM_INDEX                                                              0x0
+ #define mmMM_INDEX_HI                                                           0x6
+ #define mmMM_DATA                                                               0x1
++#define mmCC_BIF_BX_FUSESTRAP0							0x14D7
+ #define mmBUS_CNTL                                                              0x1508
+ #define mmCONFIG_CNTL                                                           0x1509
+ #define mmCONFIG_MEMSIZE                                                        0x150a
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h
+index 8fbfd0261d27..39cc4880beb4 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h
+@@ -32,6 +32,8 @@
+ #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+ #define MM_DATA__MM_DATA_MASK 0xffffffff
+ #define MM_DATA__MM_DATA__SHIFT 0x0
++#define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK    0x2
++#define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT  0x1
+ #define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1
+ #define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0
+ #define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4151-drm-amdgpu-add-new-BIF-5.0-register-for-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4151-drm-amdgpu-add-new-BIF-5.0-register-for-BACO.patch
new file mode 100644
index 00000000..bae6f731
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4151-drm-amdgpu-add-new-BIF-5.0-register-for-BACO.patch
@@ -0,0 +1,44 @@
+From 58c05ba33e4ff776d63e782cf1d41af513c4732e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 11 Feb 2019 12:28:45 -0500
+Subject: [PATCH 4151/4736] drm/amdgpu: add new BIF 5.0 register for BACO
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h       | 1 +
+ drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h
+index 809759f7bb81..8d05d6ca1c8d 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h
+@@ -27,6 +27,7 @@
+ #define mmMM_INDEX                                                              0x0
+ #define mmMM_INDEX_HI                                                           0x6
+ #define mmMM_DATA                                                               0x1
++#define mmCC_BIF_BX_FUSESTRAP0							0x14D7
+ #define mmCC_BIF_BX_STRAP2							0x152A
+ #define mmBIF_MM_INDACCESS_CNTL                                                 0x1500
+ #define mmBIF_DOORBELL_APER_EN                                                  0x1501
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h
+index adc71b01f793..73435687d049 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h
+@@ -32,6 +32,8 @@
+ #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+ #define MM_DATA__MM_DATA_MASK 0xffffffff
+ #define MM_DATA__MM_DATA__SHIFT 0x0
++#define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK    0x2
++#define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT  0x1
+ #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
+ #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
+ #define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x1
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4152-drm-amdgpu-add-new-SMU-7.0.1-registers-for-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4152-drm-amdgpu-add-new-SMU-7.0.1-registers-for-BACO.patch
new file mode 100644
index 00000000..3640ee54
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4152-drm-amdgpu-add-new-SMU-7.0.1-registers-for-BACO.patch
@@ -0,0 +1,44 @@
+From ebcfe185bdd35b9616c29db859721ca3123c7933 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 15:14:18 -0500
+Subject: [PATCH 4152/4736] drm/amdgpu: add new SMU 7.0.1 registers for BACO
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h       | 1 +
+ drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h
+index dbc2e723f659..71169daa701a 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h
+@@ -49,6 +49,7 @@
+ #define ixCG_SPLL_FUNC_CNTL_5                                                   0xc0500150
+ #define ixCG_SPLL_FUNC_CNTL_6                                                   0xc0500154
+ #define ixCG_SPLL_FUNC_CNTL_7                                                   0xc0500158
++#define ixCG_SPLL_STATUS                                                        0xC050015C
+ #define ixSPLL_CNTL_MODE                                                        0xc0500160
+ #define ixCG_SPLL_SPREAD_SPECTRUM                                               0xc0500164
+ #define ixCG_SPLL_SPREAD_SPECTRUM_2                                             0xc0500168
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
+index 6af9f0217b34..61a9a84e0c3a 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
+@@ -194,6 +194,8 @@
+ #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
+ #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
+ #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
++#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2
++#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x1
+ #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
+ #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
+ #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4153-drm-amdgpu-add-new-SMU-7.1.2-registers-for-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4153-drm-amdgpu-add-new-SMU-7.1.2-registers-for-BACO.patch
new file mode 100644
index 00000000..e4183cdc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4153-drm-amdgpu-add-new-SMU-7.1.2-registers-for-BACO.patch
@@ -0,0 +1,44 @@
+From 4e9bf31212fdf138cab1d6bc69156609822a381b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 15:16:43 -0500
+Subject: [PATCH 4153/4736] drm/amdgpu: add new SMU 7.1.2 registers for BACO
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h       | 1 +
+ drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h
+index bd3685166779..351446754c72 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h
+@@ -49,6 +49,7 @@
+ #define ixCG_SPLL_FUNC_CNTL_5                                                   0xc0500150
+ #define ixCG_SPLL_FUNC_CNTL_6                                                   0xc0500154
+ #define ixCG_SPLL_FUNC_CNTL_7                                                   0xc0500158
++#define ixCG_SPLL_STATUS                                                        0xC050015C
+ #define ixSPLL_CNTL_MODE                                                        0xc0500160
+ #define ixCG_SPLL_SPREAD_SPECTRUM                                               0xc0500164
+ #define ixCG_SPLL_SPREAD_SPECTRUM_2                                             0xc0500168
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h
+index 627906674fe8..4bfd5f8ba66c 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h
+@@ -194,6 +194,8 @@
+ #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
+ #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
+ #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
++#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2
++#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x1
+ #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
+ #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
+ #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4154-drm-amdgpu-add-new-SMU-7.1.3-registers-for-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4154-drm-amdgpu-add-new-SMU-7.1.3-registers-for-BACO.patch
new file mode 100644
index 00000000..bcb1a5c9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4154-drm-amdgpu-add-new-SMU-7.1.3-registers-for-BACO.patch
@@ -0,0 +1,44 @@
+From a991be32477d0862ec2ca93fc8c63f304570b897 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 15:18:52 -0500
+Subject: [PATCH 4154/4736] drm/amdgpu: add new SMU 7.1.3 registers for BACO
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h       | 1 +
+ drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
+index f35aba72e640..21da61c398f5 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
+@@ -52,6 +52,7 @@
+ #define ixCG_SPLL_FUNC_CNTL_5                                                   0xc0500150
+ #define ixCG_SPLL_FUNC_CNTL_6                                                   0xc0500154
+ #define ixCG_SPLL_FUNC_CNTL_7                                                   0xc0500158
++#define ixCG_SPLL_STATUS                                                        0xC050015C
+ #define ixSPLL_CNTL_MODE                                                        0xc0500160
+ #define ixCG_SPLL_SPREAD_SPECTRUM                                               0xc0500164
+ #define ixCG_SPLL_SPREAD_SPECTRUM_2                                             0xc0500168
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
+index 481ee6560aa9..f64fe0fbcb32 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
+@@ -220,6 +220,8 @@
+ #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
+ #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
+ #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
++#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2
++#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x1
+ #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
+ #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
+ #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4155-drm-amdgpu-powerplay-add-core-support-for-pre-SOC15-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4155-drm-amdgpu-powerplay-add-core-support-for-pre-SOC15-.patch
new file mode 100644
index 00000000..47666b97
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4155-drm-amdgpu-powerplay-add-core-support-for-pre-SOC15-.patch
@@ -0,0 +1,83 @@
+From 57a7d38e14d4b5eda2b000265b9714fc137b83df Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Sun, 10 Feb 2019 21:57:55 -0500
+Subject: [PATCH 4155/4736] drm/amdgpu/powerplay: add core support for
+ pre-SOC15 baco
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds core support for BACO on pre-vega asics.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/powerplay/hwmgr/common_baco.c | 19 +++++++++++++++++++
+ .../gpu/drm/amd/powerplay/hwmgr/common_baco.h | 13 +++++++++++++
+ 2 files changed, 32 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c
+index 9c57c1f67749..1c73776bd606 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c
+@@ -79,6 +79,25 @@ static bool baco_cmd_handler(struct pp_hwmgr *hwmgr, u32 command, u32 reg, u32 m
+ 	return ret;
+ }
+ 
++bool baco_program_registers(struct pp_hwmgr *hwmgr,
++			    const struct baco_cmd_entry *entry,
++			    const u32 array_size)
++{
++	u32 i, reg = 0;
++
++	for (i = 0; i < array_size; i++) {
++		if ((entry[i].cmd == CMD_WRITE) ||
++		    (entry[i].cmd == CMD_READMODIFYWRITE) ||
++		    (entry[i].cmd == CMD_WAITFOR))
++			reg = entry[i].reg_offset;
++		if (!baco_cmd_handler(hwmgr, entry[i].cmd, reg, entry[i].mask,
++				     entry[i].shift, entry[i].val, entry[i].timeout))
++			return false;
++	}
++
++	return true;
++}
++
+ bool soc15_baco_program_registers(struct pp_hwmgr *hwmgr,
+ 				 const struct soc15_baco_cmd_entry *entry,
+ 				 const u32 array_size)
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h
+index 95296c916f4e..8393eb62706d 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h
+@@ -33,6 +33,15 @@ enum baco_cmd_type {
+ 	CMD_DELAY_US,
+ };
+ 
++struct baco_cmd_entry {
++	enum baco_cmd_type cmd;
++	uint32_t 	reg_offset;
++	uint32_t     	mask;
++	uint32_t     	shift;
++	uint32_t     	timeout;
++	uint32_t     	val;
++};
++
+ struct soc15_baco_cmd_entry {
+ 	enum baco_cmd_type cmd;
+ 	uint32_t 	hwip;
+@@ -44,6 +53,10 @@ struct soc15_baco_cmd_entry {
+ 	uint32_t     	timeout;
+ 	uint32_t     	val;
+ };
++
++extern bool baco_program_registers(struct pp_hwmgr *hwmgr,
++				   const struct baco_cmd_entry *entry,
++				   const u32 array_size);
+ extern bool soc15_baco_program_registers(struct pp_hwmgr *hwmgr,
+ 					const struct soc15_baco_cmd_entry *entry,
+ 					const u32 array_size);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4156-drm-amdgpu-powerplay-add-support-for-BACO-on-tonga.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4156-drm-amdgpu-powerplay-add-support-for-BACO-on-tonga.patch
new file mode 100644
index 00000000..3e029169
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4156-drm-amdgpu-powerplay-add-support-for-BACO-on-tonga.patch
@@ -0,0 +1,302 @@
+From 718f101490fedd049c6a6a156d9af5701769cdb5 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Feb 2019 17:35:50 -0500
+Subject: [PATCH 4156/4736] drm/amdgpu/powerplay: add support for BACO on tonga
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds BACO support for Tonga.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/Makefile  |   2 +-
+ .../gpu/drm/amd/powerplay/hwmgr/tonga_baco.c  | 221 ++++++++++++++++++
+ .../gpu/drm/amd/powerplay/hwmgr/tonga_baco.h  |  32 +++
+ 3 files changed, 254 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+index cc63705920dc..d66cfe5f80f9 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+@@ -36,7 +36,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
+ 		pp_overdriver.o smu_helper.o \
+ 		vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
+ 		vega20_thermal.o common_baco.o vega10_baco.o  vega20_baco.o \
+-		vega12_baco.o smu9_baco.o
++		vega12_baco.o smu9_baco.o tonga_baco.o
+ 
+ AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
+new file mode 100644
+index 000000000000..37a41b83c913
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
+@@ -0,0 +1,221 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "amdgpu.h"
++#include "tonga_baco.h"
++
++#include "gmc/gmc_8_1_d.h"
++#include "gmc/gmc_8_1_sh_mask.h"
++
++#include "bif/bif_5_0_d.h"
++#include "bif/bif_5_0_sh_mask.h"
++
++#include "dce/dce_10_0_d.h"
++#include "dce/dce_10_0_sh_mask.h"
++
++#include "smu/smu_7_1_2_d.h"
++#include "smu/smu_7_1_2_sh_mask.h"
++
++
++static const struct baco_cmd_entry gpio_tbl[] =
++{
++	{ CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff },
++	{ CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff },
++	{ CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 },
++	{ CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 }
++};
++
++static const struct baco_cmd_entry enable_fb_req_rej_tbl[] =
++{
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0300024 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 },
++	{ CMD_WRITE, mmBIF_FB_EN, 0, 0, 0, 0x0 }
++};
++
++static const struct baco_cmd_entry use_bclk_tbl[] =
++{
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS },
++	{ CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS },
++	{ CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 },
++	{ CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT, 0, 0x1 },
++	{ CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK, MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT, 0, 0x0 }
++};
++
++static const struct baco_cmd_entry turn_off_plls_tbl[] =
++{
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK, CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT, 0, 0x1 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK, CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT, 0, 0x0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x2000000, 0x19, 0, 0x1 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x8000000, 0x1b, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK, MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmMPLL_CONTROL, 0, 0, 0, 0x00000006 },
++	{ CMD_WRITE, mmMC_IO_RXCNTL_DPHY0_D0, 0, 0, 0, 0x00007740 },
++	{ CMD_WRITE, mmMC_IO_RXCNTL_DPHY0_D1, 0, 0, 0, 0x00007740 },
++	{ CMD_WRITE, mmMC_IO_RXCNTL_DPHY1_D0, 0, 0, 0, 0x00007740 },
++	{ CMD_WRITE, mmMC_IO_RXCNTL_DPHY1_D1, 0, 0, 0, 0x00007740 },
++	{ CMD_READMODIFYWRITE, mmMCLK_PWRMGT_CNTL, MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK, MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmMCLK_PWRMGT_CNTL, MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK, MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmMC_SEQ_CNTL_2, MC_SEQ_CNTL_2__DRST_PU_MASK, MC_SEQ_CNTL_2__DRST_PU__SHIFT, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmMC_SEQ_CNTL_2, MC_SEQ_CNTL_2__DRST_PD_MASK, MC_SEQ_CNTL_2__DRST_PD__SHIFT, 0, 0x0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT, 0, 0x0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMISC_CLK_CTRL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT, 0, 0x1 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK, CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT, 0, 0x0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixTHM_CLK_CNTL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK,  THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK,  THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x1 }
++};
++
++static const struct baco_cmd_entry enter_baco_tbl[] =
++{
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x01 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x01 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, 0, 5, 0x40000 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x01 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, 0, 5, 0x02 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, 0, 5, 0x00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, 0, 5, 0x00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x01 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, 0, 5, 0x08 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x40 }
++};
++
++#define BACO_CNTL__PWRGOOD_MASK  BACO_CNTL__PWRGOOD_GPIO_MASK+BACO_CNTL__PWRGOOD_MEM_MASK+BACO_CNTL__PWRGOOD_DVO_MASK
++
++static const struct baco_cmd_entry exit_baco_tbl[] =
++{
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 }
++};
++
++static const struct baco_cmd_entry clean_baco_tbl[] =
++{
++	{ CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
++	{ CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 }
++};
++
++int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++	uint32_t reg;
++
++	*cap = false;
++	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
++		return 0;
++
++	reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
++
++	if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
++		*cap = true;
++
++	return 0;
++}
++
++int tonga_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++	uint32_t reg;
++
++	reg = RREG32(mmBACO_CNTL);
++
++	if (reg & BACO_CNTL__BACO_MODE_MASK)
++		/* gfx has already entered BACO state */
++		*state = BACO_STATE_IN;
++	else
++		*state = BACO_STATE_OUT;
++	return 0;
++}
++
++int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
++{
++	enum BACO_STATE cur_state;
++
++	tonga_baco_get_state(hwmgr, &cur_state);
++
++	if (cur_state == state)
++		/* aisc already in the target state */
++		return 0;
++
++	if (state == BACO_STATE_IN) {
++		baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl));
++		baco_program_registers(hwmgr, enable_fb_req_rej_tbl,
++				       ARRAY_SIZE(enable_fb_req_rej_tbl));
++		baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl));
++		baco_program_registers(hwmgr, turn_off_plls_tbl,
++				       ARRAY_SIZE(turn_off_plls_tbl));
++		if (baco_program_registers(hwmgr, enter_baco_tbl,
++					   ARRAY_SIZE(enter_baco_tbl)))
++			return 0;
++
++	} else if (state == BACO_STATE_OUT) {
++		/* HW requires at least 20ms between regulator off and on */
++		msleep(20);
++		/* Execute Hardware BACO exit sequence */
++		if (baco_program_registers(hwmgr, exit_baco_tbl,
++					   ARRAY_SIZE(exit_baco_tbl))) {
++			if (baco_program_registers(hwmgr, clean_baco_tbl,
++						   ARRAY_SIZE(clean_baco_tbl)))
++				return 0;
++		}
++	}
++
++	return -EINVAL;
++}
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h
+new file mode 100644
+index 000000000000..21301b043255
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h
+@@ -0,0 +1,32 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __TONGA_BACO_H__
++#define __TONGA_BACO_H__
++#include "hwmgr.h"
++#include "common_baco.h"
++
++extern int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
++extern int tonga_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
++extern int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4157-drm-amdgpu-powerplay-add-support-for-BACO-on-Iceland.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4157-drm-amdgpu-powerplay-add-support-for-BACO-on-Iceland.patch
new file mode 100644
index 00000000..823fb413
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4157-drm-amdgpu-powerplay-add-support-for-BACO-on-Iceland.patch
@@ -0,0 +1,100 @@
+From c33a4cf13aff4cdcef3fdc3426ed18f5a3d4c9ef Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Feb 2019 11:56:56 -0500
+Subject: [PATCH 4157/4736] drm/amdgpu/powerplay: add support for BACO on
+ Iceland
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds BACO support for Iceland asics.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/powerplay/hwmgr/tonga_baco.c  | 54 ++++++++++++++++---
+ 1 file changed, 48 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
+index 37a41b83c913..84b7217b7bda 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
+@@ -152,6 +152,36 @@ static const struct baco_cmd_entry clean_baco_tbl[] =
+ 	{ CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 }
+ };
+ 
++static const struct baco_cmd_entry gpio_tbl_iceland[] =
++{
++	{ CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff }
++};
++
++static const struct baco_cmd_entry exit_baco_tbl_iceland[] =
++{
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 },
++	{ CMD_DELAY_MS, 0, 0, 0, 20, 0 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 }
++};
++
++static const struct baco_cmd_entry clean_baco_tbl_iceland[] =
++{
++	{ CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 }
++};
++
+ int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+@@ -195,7 +225,10 @@ int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ 		return 0;
+ 
+ 	if (state == BACO_STATE_IN) {
+-		baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl));
++		if (hwmgr->chip_id == CHIP_TOPAZ)
++			baco_program_registers(hwmgr, gpio_tbl_iceland, ARRAY_SIZE(gpio_tbl_iceland));
++		else
++			baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl));
+ 		baco_program_registers(hwmgr, enable_fb_req_rej_tbl,
+ 				       ARRAY_SIZE(enable_fb_req_rej_tbl));
+ 		baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl));
+@@ -209,11 +242,20 @@ int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ 		/* HW requires at least 20ms between regulator off and on */
+ 		msleep(20);
+ 		/* Execute Hardware BACO exit sequence */
+-		if (baco_program_registers(hwmgr, exit_baco_tbl,
+-					   ARRAY_SIZE(exit_baco_tbl))) {
+-			if (baco_program_registers(hwmgr, clean_baco_tbl,
+-						   ARRAY_SIZE(clean_baco_tbl)))
+-				return 0;
++		if (hwmgr->chip_id == CHIP_TOPAZ) {
++			if (baco_program_registers(hwmgr, exit_baco_tbl_iceland,
++						   ARRAY_SIZE(exit_baco_tbl_iceland))) {
++				if (baco_program_registers(hwmgr, clean_baco_tbl_iceland,
++							   ARRAY_SIZE(clean_baco_tbl_iceland)))
++					return 0;
++			}
++		} else {
++			if (baco_program_registers(hwmgr, exit_baco_tbl,
++						   ARRAY_SIZE(exit_baco_tbl))) {
++				if (baco_program_registers(hwmgr, clean_baco_tbl,
++							   ARRAY_SIZE(clean_baco_tbl)))
++					return 0;
++			}
+ 		}
+ 	}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4158-drm-amdgpu-powerplay-add-support-for-BACO-on-polaris.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4158-drm-amdgpu-powerplay-add-support-for-BACO-on-polaris.patch
new file mode 100644
index 00000000..6bbe9db2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4158-drm-amdgpu-powerplay-add-support-for-BACO-on-polaris.patch
@@ -0,0 +1,300 @@
+From 0f5e17c868a5dd7e9b76cee03469690ba93de246 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Feb 2019 17:36:40 -0500
+Subject: [PATCH 4158/4736] drm/amdgpu/powerplay: add support for BACO on
+ polaris
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds BACO support for Polaris asics.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/Makefile  |   2 +-
+ .../drm/amd/powerplay/hwmgr/polaris_baco.c    | 218 ++++++++++++++++++
+ .../drm/amd/powerplay/hwmgr/polaris_baco.h    |  32 +++
+ 3 files changed, 251 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+index d66cfe5f80f9..a1535e1430d5 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+@@ -36,7 +36,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
+ 		pp_overdriver.o smu_helper.o \
+ 		vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
+ 		vega20_thermal.o common_baco.o vega10_baco.o  vega20_baco.o \
+-		vega12_baco.o smu9_baco.o tonga_baco.o
++		vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o
+ 
+ AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
+new file mode 100644
+index 000000000000..d0c9de88f474
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
+@@ -0,0 +1,218 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "amdgpu.h"
++#include "polaris_baco.h"
++
++#include "gmc/gmc_8_1_d.h"
++#include "gmc/gmc_8_1_sh_mask.h"
++
++#include "bif/bif_5_0_d.h"
++#include "bif/bif_5_0_sh_mask.h"
++
++#include "dce/dce_11_0_d.h"
++#include "dce/dce_11_0_sh_mask.h"
++
++#include "smu/smu_7_1_3_d.h"
++#include "smu/smu_7_1_3_sh_mask.h"
++
++static const struct baco_cmd_entry gpio_tbl[] =
++{
++	{ CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff },
++	{ CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff },
++	{ CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 },
++	{ CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 }
++};
++
++static const struct baco_cmd_entry enable_fb_req_rej_tbl[] =
++{
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0300024 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 },
++	{ CMD_WRITE, mmBIF_FB_EN, 0, 0, 0, 0x0 }
++};
++
++static const struct baco_cmd_entry use_bclk_tbl[] =
++{
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixGCK_DFS_BYPASS_CNTL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK, GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 },
++	{ CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT, 0, 0x1 },
++	{ CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK, MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT, 0, 0x0 }
++};
++
++static const struct baco_cmd_entry turn_off_plls_tbl[] =
++{
++	{ CMD_READMODIFYWRITE, mmDC_GPIO_PAD_STRENGTH_1, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT, 0, 0x1 },
++	{ CMD_DELAY_US, 0, 0, 0, 1, 0x0 },
++	{ CMD_READMODIFYWRITE, mmMC_SEQ_DRAM, MC_SEQ_DRAM__RST_CTL_MASK, MC_SEQ_DRAM__RST_CTL__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC05002B0 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 },
++	{ CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC050032C },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 },
++	{ CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500080 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 },
++	{ CMD_READMODIFYWRITE, 0xda2, 0x40, 0x6, 0, 0x0 },
++	{ CMD_DELAY_US, 0, 0, 0, 3, 0x0 },
++	{ CMD_READMODIFYWRITE, 0xda2, 0x8, 0x3, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, 0xda2, 0x3fff00, 0x8, 0, 0x32 },
++	{ CMD_DELAY_US, 0, 0, 0, 3, 0x0 },
++	{ CMD_READMODIFYWRITE, mmMPLL_FUNC_CNTL_2, MPLL_FUNC_CNTL_2__ISO_DIS_P_MASK, MPLL_FUNC_CNTL_2__ISO_DIS_P__SHIFT, 0, 0x0 },
++	{ CMD_DELAY_US, 0, 0, 0, 5, 0x0 }
++};
++
++static const struct baco_cmd_entry clk_req_b_tbl[] =
++{
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixTHM_CLK_CNTL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMISC_CLK_CTRL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT, 0, 0x1 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK, CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT, 0, 0x0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT, 0, 0x0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0,     0x4 }
++};
++
++static const struct baco_cmd_entry enter_baco_tbl[] =
++{
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x01 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x01 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, 0, 5, 0x40000 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x01 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, 0, 5, 0x02 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, 0, 5, 0x00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, 0, 5, 0x00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x01 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, 0, 5, 0x08 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x40 }
++};
++
++#define BACO_CNTL__PWRGOOD_MASK  BACO_CNTL__PWRGOOD_GPIO_MASK+BACO_CNTL__PWRGOOD_MEM_MASK+BACO_CNTL__PWRGOOD_DVO_MASK
++
++static const struct baco_cmd_entry exit_baco_tbl[] =
++{
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 }
++};
++
++static const struct baco_cmd_entry clean_baco_tbl[] =
++{
++	{ CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
++	{ CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 }
++};
++
++int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++	uint32_t reg;
++
++	*cap = false;
++	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
++		return 0;
++
++	reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
++
++	if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
++		*cap = true;
++
++	return 0;
++}
++
++int polaris_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++	uint32_t reg;
++
++	reg = RREG32(mmBACO_CNTL);
++
++	if (reg & BACO_CNTL__BACO_MODE_MASK)
++		/* gfx has already entered BACO state */
++		*state = BACO_STATE_IN;
++	else
++		*state = BACO_STATE_OUT;
++	return 0;
++}
++
++int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
++{
++	enum BACO_STATE cur_state;
++
++	polaris_baco_get_state(hwmgr, &cur_state);
++
++	if (cur_state == state)
++		/* aisc already in the target state */
++		return 0;
++
++	if (state == BACO_STATE_IN) {
++		baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl));
++		baco_program_registers(hwmgr, enable_fb_req_rej_tbl,
++				       ARRAY_SIZE(enable_fb_req_rej_tbl));
++		baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl));
++		baco_program_registers(hwmgr, turn_off_plls_tbl,
++				       ARRAY_SIZE(turn_off_plls_tbl));
++		baco_program_registers(hwmgr, clk_req_b_tbl, ARRAY_SIZE(clk_req_b_tbl));
++		if (baco_program_registers(hwmgr, enter_baco_tbl,
++					   ARRAY_SIZE(enter_baco_tbl)))
++			return 0;
++
++	} else if (state == BACO_STATE_OUT) {
++		/* HW requires at least 20ms between regulator off and on */
++		msleep(20);
++		/* Execute Hardware BACO exit sequence */
++		if (baco_program_registers(hwmgr, exit_baco_tbl,
++					   ARRAY_SIZE(exit_baco_tbl))) {
++			if (baco_program_registers(hwmgr, clean_baco_tbl,
++						   ARRAY_SIZE(clean_baco_tbl)))
++				return 0;
++		}
++	}
++
++	return -EINVAL;
++}
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h
+new file mode 100644
+index 000000000000..e48bfb1c5c6a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h
+@@ -0,0 +1,32 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __POLARIS_BACO_H__
++#define __POLARIS_BACO_H__
++#include "hwmgr.h"
++#include "common_baco.h"
++
++extern int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
++extern int polaris_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
++extern int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4159-drm-amdgpu-powerplay-add-support-for-BACO-on-VegaM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4159-drm-amdgpu-powerplay-add-support-for-BACO-on-VegaM.patch
new file mode 100644
index 00000000..0b557a14
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4159-drm-amdgpu-powerplay-add-support-for-BACO-on-VegaM.patch
@@ -0,0 +1,80 @@
+From eadd75308b9e8442de6849d88575fa6788c3228b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 14 Feb 2019 16:53:42 -0500
+Subject: [PATCH 4159/4736] drm/amdgpu/powerplay: add support for BACO on VegaM
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds BACO support for VegaM asics.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/powerplay/hwmgr/polaris_baco.c    | 42 +++++++++++++++++--
+ 1 file changed, 39 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
+index d0c9de88f474..a9abe53df475 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
+@@ -148,6 +148,36 @@ static const struct baco_cmd_entry clean_baco_tbl[] =
+ 	{ CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 }
+ };
+ 
++static const struct baco_cmd_entry use_bclk_tbl_vg[] =
++{
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixGCK_DFS_BYPASS_CNTL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK, GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 }
++};
++
++static const struct baco_cmd_entry turn_off_plls_tbl_vg[] =
++{
++	{ CMD_READMODIFYWRITE, mmDC_GPIO_PAD_STRENGTH_1, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK, DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT, 0, 0x1 },
++	{ CMD_DELAY_US, 0, 0, 0, 1, 0x0 },
++	{ CMD_READMODIFYWRITE, mmMC_SEQ_DRAM, MC_SEQ_DRAM__RST_CTL_MASK, MC_SEQ_DRAM__RST_CTL__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC05002B0 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 },
++	{ CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC050032C },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 },
++	{ CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500080 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 },
++	{ CMD_DELAY_US, 0, 0, 0, 3, 0x0 },
++	{ CMD_DELAY_US, 0, 0, 0, 3, 0x0 },
++	{ CMD_DELAY_US, 0, 0, 0, 5, 0x0 }
++};
++
+ int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+@@ -194,9 +224,15 @@ int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ 		baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl));
+ 		baco_program_registers(hwmgr, enable_fb_req_rej_tbl,
+ 				       ARRAY_SIZE(enable_fb_req_rej_tbl));
+-		baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl));
+-		baco_program_registers(hwmgr, turn_off_plls_tbl,
+-				       ARRAY_SIZE(turn_off_plls_tbl));
++		if (hwmgr->chip_id == CHIP_VEGAM) {
++			baco_program_registers(hwmgr, use_bclk_tbl_vg, ARRAY_SIZE(use_bclk_tbl_vg));
++			baco_program_registers(hwmgr, turn_off_plls_tbl_vg,
++					       ARRAY_SIZE(turn_off_plls_tbl_vg));
++		} else {
++			baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl));
++			baco_program_registers(hwmgr, turn_off_plls_tbl,
++					       ARRAY_SIZE(turn_off_plls_tbl));
++		}
+ 		baco_program_registers(hwmgr, clk_req_b_tbl, ARRAY_SIZE(clk_req_b_tbl));
+ 		if (baco_program_registers(hwmgr, enter_baco_tbl,
+ 					   ARRAY_SIZE(enter_baco_tbl)))
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4160-drm-amdgpu-powerplay-add-support-for-BACO-on-Fiji.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4160-drm-amdgpu-powerplay-add-support-for-BACO-on-Fiji.patch
new file mode 100644
index 00000000..349ebad6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4160-drm-amdgpu-powerplay-add-support-for-BACO-on-Fiji.patch
@@ -0,0 +1,309 @@
+From 7e1936b6ba966edb01b6826ce684c565411ee6bf Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Feb 2019 17:37:46 -0500
+Subject: [PATCH 4160/4736] drm/amdgpu/powerplay: add support for BACO on Fiji
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds BACO support for Fiji asics.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/Makefile  |   2 +-
+ .../gpu/drm/amd/powerplay/hwmgr/fiji_baco.c   | 228 ++++++++++++++++++
+ .../gpu/drm/amd/powerplay/hwmgr/fiji_baco.h   |  32 +++
+ 3 files changed, 261 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+index a1535e1430d5..bfd22d8b0aea 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+@@ -36,7 +36,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
+ 		pp_overdriver.o smu_helper.o \
+ 		vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
+ 		vega20_thermal.o common_baco.o vega10_baco.o  vega20_baco.o \
+-		vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o
++		vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o fiji_baco.o
+ 
+ AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c
+new file mode 100644
+index 000000000000..ad01919ccb27
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c
+@@ -0,0 +1,228 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "amdgpu.h"
++#include "fiji_baco.h"
++
++#include "gmc/gmc_8_1_d.h"
++#include "gmc/gmc_8_1_sh_mask.h"
++
++#include "bif/bif_5_0_d.h"
++#include "bif/bif_5_0_sh_mask.h"
++
++#include "dce/dce_10_0_d.h"
++#include "dce/dce_10_0_sh_mask.h"
++
++#include "smu/smu_7_1_3_d.h"
++#include "smu/smu_7_1_3_sh_mask.h"
++
++
++static const struct baco_cmd_entry gpio_tbl[] =
++{
++	{ CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff },
++	{ CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff },
++	{ CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 },
++	{ CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 }
++};
++
++static const struct baco_cmd_entry enable_fb_req_rej_tbl[] =
++{
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0300024 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 },
++	{ CMD_WRITE, mmBIF_FB_EN, 0, 0, 0, 0x0 }
++};
++
++static const struct baco_cmd_entry use_bclk_tbl[] =
++{
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS },
++	{ CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0,  0x0 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0,  0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS },
++	{ CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 }
++};
++
++static const struct baco_cmd_entry turn_off_plls_tbl[] =
++{
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK, CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT, 0,     0x1 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK, CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT, 0,     0x0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x2000000, 0x19, 0, 0x1 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x8000000, 0x1b, 0, 0x0 }
++};
++
++static const struct baco_cmd_entry clk_req_b_tbl[] =
++{
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT, 0, 0x0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMISC_CLK_CTRL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT, 0, 0x1 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK, CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT, 0, 0x0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixTHM_CLK_CNTL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x1 }
++};
++
++static const struct baco_cmd_entry enter_baco_tbl[] =
++{
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x01 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x01 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, 0, 5, 0x40000 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x01 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, 0, 5, 0x02 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, 0, 5, 0x00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, 0, 5, 0x00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x01 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, 0, 5, 0x08 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x40 }
++};
++
++#define BACO_CNTL__PWRGOOD_MASK  BACO_CNTL__PWRGOOD_GPIO_MASK+BACO_CNTL__PWRGOOD_MEM_MASK+BACO_CNTL__PWRGOOD_DVO_MASK
++
++static const struct baco_cmd_entry exit_baco_tbl[] =
++{
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT, 0, 0x00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 }
++};
++
++static const struct baco_cmd_entry clean_baco_tbl[] =
++{
++	{ CMD_WRITE, mmBIOS_SCRATCH_0, 0, 0, 0, 0 },
++	{ CMD_WRITE, mmBIOS_SCRATCH_1, 0, 0, 0, 0 },
++	{ CMD_WRITE, mmBIOS_SCRATCH_2, 0, 0, 0, 0 },
++	{ CMD_WRITE, mmBIOS_SCRATCH_3, 0, 0, 0, 0 },
++	{ CMD_WRITE, mmBIOS_SCRATCH_4, 0, 0, 0, 0 },
++	{ CMD_WRITE, mmBIOS_SCRATCH_5, 0, 0, 0, 0 },
++	{ CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
++	{ CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 },
++	{ CMD_WRITE, mmBIOS_SCRATCH_8, 0, 0, 0, 0 },
++	{ CMD_WRITE, mmBIOS_SCRATCH_9, 0, 0, 0, 0 },
++	{ CMD_WRITE, mmBIOS_SCRATCH_10, 0, 0, 0, 0 },
++	{ CMD_WRITE, mmBIOS_SCRATCH_11, 0, 0, 0, 0 },
++	{ CMD_WRITE, mmBIOS_SCRATCH_12, 0, 0, 0, 0 },
++	{ CMD_WRITE, mmBIOS_SCRATCH_13, 0, 0, 0, 0 },
++	{ CMD_WRITE, mmBIOS_SCRATCH_14, 0, 0, 0, 0 },
++	{ CMD_WRITE, mmBIOS_SCRATCH_15, 0, 0, 0, 0 }
++};
++
++int fiji_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++	uint32_t reg;
++
++	*cap = false;
++	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
++		return 0;
++
++	reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
++
++	if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
++		*cap = true;
++
++	return 0;
++}
++
++int fiji_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++	uint32_t reg;
++
++	reg = RREG32(mmBACO_CNTL);
++
++	if (reg & BACO_CNTL__BACO_MODE_MASK)
++		/* gfx has already entered BACO state */
++		*state = BACO_STATE_IN;
++	else
++		*state = BACO_STATE_OUT;
++	return 0;
++}
++
++int fiji_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
++{
++	enum BACO_STATE cur_state;
++
++	fiji_baco_get_state(hwmgr, &cur_state);
++
++	if (cur_state == state)
++		/* aisc already in the target state */
++		return 0;
++
++	if (state == BACO_STATE_IN) {
++		baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl));
++		baco_program_registers(hwmgr, enable_fb_req_rej_tbl,
++				       ARRAY_SIZE(enable_fb_req_rej_tbl));
++		baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl));
++		baco_program_registers(hwmgr, turn_off_plls_tbl,
++				       ARRAY_SIZE(turn_off_plls_tbl));
++		baco_program_registers(hwmgr, clk_req_b_tbl, ARRAY_SIZE(clk_req_b_tbl));
++		if (baco_program_registers(hwmgr, enter_baco_tbl,
++					   ARRAY_SIZE(enter_baco_tbl)))
++			return 0;
++
++	} else if (state == BACO_STATE_OUT) {
++		/* HW requires at least 20ms between regulator off and on */
++		msleep(20);
++		/* Execute Hardware BACO exit sequence */
++		if (baco_program_registers(hwmgr, exit_baco_tbl,
++					   ARRAY_SIZE(exit_baco_tbl))) {
++			if (baco_program_registers(hwmgr, clean_baco_tbl,
++						   ARRAY_SIZE(clean_baco_tbl)))
++				return 0;
++		}
++	}
++
++	return -EINVAL;
++}
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h
+new file mode 100644
+index 000000000000..2f7c8388667e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h
+@@ -0,0 +1,32 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __FIJI_BACO_H__
++#define __FIJI_BACO_H__
++#include "hwmgr.h"
++#include "common_baco.h"
++
++extern int fiji_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
++extern int fiji_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
++extern int fiji_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4161-drm-amdgpu-powerplay-add-support-for-BACO-on-CI.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4161-drm-amdgpu-powerplay-add-support-for-BACO-on-CI.patch
new file mode 100644
index 00000000..362a646d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4161-drm-amdgpu-powerplay-add-support-for-BACO-on-CI.patch
@@ -0,0 +1,309 @@
+From a835596fe3e90f66093459a5708c26b690d59e8d Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Feb 2019 17:38:44 -0500
+Subject: [PATCH 4161/4736] drm/amdgpu/powerplay: add support for BACO on CI
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds BACO support for CI asics.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/Makefile  |   3 +-
+ drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c | 227 ++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h |  32 +++
+ 3 files changed, 261 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+index bfd22d8b0aea..5ad5893bdae1 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+@@ -36,7 +36,8 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
+ 		pp_overdriver.o smu_helper.o \
+ 		vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
+ 		vega20_thermal.o common_baco.o vega10_baco.o  vega20_baco.o \
+-		vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o fiji_baco.o
++		vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o fiji_baco.o \
++		ci_baco.o
+ 
+ AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c
+new file mode 100644
+index 000000000000..f1a8c9cc0d1f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c
+@@ -0,0 +1,227 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "amdgpu.h"
++#include "ci_baco.h"
++
++#include "gmc/gmc_7_1_d.h"
++#include "gmc/gmc_7_1_sh_mask.h"
++
++#include "bif/bif_4_1_d.h"
++#include "bif/bif_4_1_sh_mask.h"
++
++#include "dce/dce_8_0_d.h"
++#include "dce/dce_8_0_sh_mask.h"
++
++#include "smu/smu_7_0_1_d.h"
++#include "smu/smu_7_0_1_sh_mask.h"
++
++#include "gca/gfx_7_2_d.h"
++#include "gca/gfx_7_2_sh_mask.h"
++
++static const struct baco_cmd_entry gpio_tbl[] =
++{
++	{ CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff },
++	{ CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 },
++	{ CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff },
++	{ CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 },
++	{ CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 }
++};
++
++static const struct baco_cmd_entry enable_fb_req_rej_tbl[] =
++{
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0300024 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x1, 0x0, 0, 0x1 },
++	{ CMD_WRITE, mmBIF_FB_EN, 0, 0, 0, 0x0 }
++};
++
++static const struct baco_cmd_entry use_bclk_tbl[] =
++{
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK, CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS },
++	{ CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_STATUS },
++	{ CMD_WAITFOR, mmGCK_SMC_IND_DATA, CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK, 0, 0xffffffff, 0x2 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK, CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT, 0, 0x0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x4000000, 0x1a, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x2 },
++	{ CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK, MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT, 0, 0x1 },
++	{ CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK, MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT, 0, 0x0 }
++};
++
++static const struct baco_cmd_entry turn_off_plls_tbl[] =
++{
++	{ CMD_READMODIFYWRITE, mmDISPPLL_BG_CNTL, DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK, DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_DC },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_DC__OSC_EN_MASK, CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK, CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmPLL_CNTL, PLL_CNTL__PLL_RESET_MASK, PLL_CNTL__PLL_RESET__SHIFT, 0, 0x1 },
++	{ CMD_READMODIFYWRITE, mmPLL_CNTL, PLL_CNTL__PLL_POWER_DOWN_MASK, PLL_CNTL__PLL_POWER_DOWN__SHIFT, 0, 0x1 },
++	{ CMD_READMODIFYWRITE, mmPLL_CNTL, PLL_CNTL__PLL_BYPASS_CAL_MASK, PLL_CNTL__PLL_BYPASS_CAL__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK, CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT, 0, 0x1 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK, CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT, 0, 0x0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, 0xC0500170 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x2000000, 0x19, 0, 0x1 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x8000000, 0x1b, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmMPLL_CNTL_MODE, MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK, MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT, 0, 0x1 },
++	{ CMD_WRITE, mmMPLL_CONTROL, 0, 0, 0, 0x00000006 },
++	{ CMD_WRITE, mmMC_IO_RXCNTL_DPHY0_D0, 0, 0, 0, 0x00007740 },
++	{ CMD_WRITE, mmMC_IO_RXCNTL_DPHY0_D1, 0, 0, 0, 0x00007740 },
++	{ CMD_WRITE, mmMC_IO_RXCNTL_DPHY1_D0, 0, 0, 0, 0x00007740 },
++	{ CMD_WRITE, mmMC_IO_RXCNTL_DPHY1_D1, 0, 0, 0, 0x00007740 },
++	{ CMD_READMODIFYWRITE, mmMCLK_PWRMGT_CNTL, MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK, MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmMCLK_PWRMGT_CNTL, MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK, MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmMC_SEQ_CNTL_2, MC_SEQ_CNTL_2__DRST_PU_MASK, MC_SEQ_CNTL_2__DRST_PU__SHIFT, 0, 0x0 },
++	{ CMD_READMODIFYWRITE, mmMC_SEQ_CNTL_2, MC_SEQ_CNTL_2__DRST_PD_MASK, MC_SEQ_CNTL_2__DRST_PD__SHIFT, 0, 0x0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL_2 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK, CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT, 0, 0x0 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMPLL_BYPASSCLK_SEL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK, MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT, 0, 0x4 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixMISC_CLK_CTRL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK, MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT, 0, 0x2 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x2 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK, MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT, 0, 0x2 },
++	{ CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixTHM_CLK_CNTL },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x2 },
++	{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, 0x2 }
++};
++
++static const struct baco_cmd_entry enter_baco_tbl[] =
++{
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x01 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x01 },
++	{ CMD_WAITFOR,         mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK, 0, 5, 0x02 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR,         mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, 0, 5,  0x00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR,         mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, 0, 5, 0x00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x01 },
++	{ CMD_WAITFOR,         mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK, 0, 5, 0x08 },
++	{ CMD_WAITFOR,         mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x40 }
++};
++
++#define BACO_CNTL__PWRGOOD_MASK  BACO_CNTL__PWRGOOD_GPIO_MASK+BACO_CNTL__PWRGOOD_MEM_MASK+BACO_CNTL__PWRGOOD_DVO_MASK
++
++static const struct baco_cmd_entry exit_baco_tbl[] =
++{
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x01 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK,           BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK,          BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 },
++	{ CMD_DELAY_MS, 0, 0, 0, 20, 0 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x20 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x10 },
++	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
++	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 }
++};
++
++static const struct baco_cmd_entry clean_baco_tbl[] =
++{
++	{ CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
++	{ CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 }
++};
++
++int ci_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++	uint32_t reg;
++
++	*cap = false;
++	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
++		return 0;
++
++	reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
++
++	if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
++		*cap = true;
++
++	return 0;
++}
++
++int ci_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++	uint32_t reg;
++
++	reg = RREG32(mmBACO_CNTL);
++
++	if (reg & BACO_CNTL__BACO_MODE_MASK)
++		/* gfx has already entered BACO state */
++		*state = BACO_STATE_IN;
++	else
++		*state = BACO_STATE_OUT;
++	return 0;
++}
++
++int ci_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
++{
++	enum BACO_STATE cur_state;
++
++	ci_baco_get_state(hwmgr, &cur_state);
++
++	if (cur_state == state)
++		/* aisc already in the target state */
++		return 0;
++
++	if (state == BACO_STATE_IN) {
++		baco_program_registers(hwmgr, gpio_tbl, ARRAY_SIZE(gpio_tbl));
++		baco_program_registers(hwmgr, enable_fb_req_rej_tbl,
++				       ARRAY_SIZE(enable_fb_req_rej_tbl));
++		baco_program_registers(hwmgr, use_bclk_tbl, ARRAY_SIZE(use_bclk_tbl));
++		baco_program_registers(hwmgr, turn_off_plls_tbl,
++				       ARRAY_SIZE(turn_off_plls_tbl));
++		if (baco_program_registers(hwmgr, enter_baco_tbl,
++					   ARRAY_SIZE(enter_baco_tbl)))
++			return 0;
++
++	} else if (state == BACO_STATE_OUT) {
++		/* HW requires at least 20ms between regulator off and on */
++		msleep(20);
++		/* Execute Hardware BACO exit sequence */
++		if (baco_program_registers(hwmgr, exit_baco_tbl,
++					   ARRAY_SIZE(exit_baco_tbl))) {
++			if (baco_program_registers(hwmgr, clean_baco_tbl,
++						   ARRAY_SIZE(clean_baco_tbl)))
++				return 0;
++		}
++	}
++
++	return -EINVAL;
++}
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h
+new file mode 100644
+index 000000000000..c9bedb51cb25
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h
+@@ -0,0 +1,32 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __CI_BACO_H__
++#define __CI_BACO_H__
++#include "hwmgr.h"
++#include "common_baco.h"
++
++extern int ci_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
++extern int ci_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
++extern int ci_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
++
++#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4162-drm-amdgpu-powerplay-split-out-common-smu7-BACO-code.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4162-drm-amdgpu-powerplay-split-out-common-smu7-BACO-code.patch
new file mode 100644
index 00000000..286aaa53
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4162-drm-amdgpu-powerplay-split-out-common-smu7-BACO-code.patch
@@ -0,0 +1,446 @@
+From 398407598af75bd60cc2a23431c992283eeff37e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Feb 2019 17:39:33 -0500
+Subject: [PATCH 4162/4736] drm/amdgpu/powerplay: split out common smu7 BACO
+ code
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Several of the BACO functions are common across smu7-based
+asics.  Split the common code out.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/Makefile  |  2 +-
+ drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c | 34 +------
+ drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h |  5 +-
+ .../gpu/drm/amd/powerplay/hwmgr/fiji_baco.c   | 34 +------
+ .../gpu/drm/amd/powerplay/hwmgr/fiji_baco.h   |  5 +-
+ .../drm/amd/powerplay/hwmgr/polaris_baco.c    | 34 +------
+ .../drm/amd/powerplay/hwmgr/polaris_baco.h    |  5 +-
+ .../gpu/drm/amd/powerplay/hwmgr/smu7_baco.c   | 91 +++++++++++++++++++
+ .../gpu/drm/amd/powerplay/hwmgr/smu7_baco.h   | 32 +++++++
+ .../gpu/drm/amd/powerplay/hwmgr/tonga_baco.c  | 34 +------
+ .../gpu/drm/amd/powerplay/hwmgr/tonga_baco.h  |  5 +-
+ 11 files changed, 132 insertions(+), 149 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c
+ create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+index 5ad5893bdae1..2773966ae434 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+@@ -37,7 +37,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
+ 		vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
+ 		vega20_thermal.o common_baco.o vega10_baco.o  vega20_baco.o \
+ 		vega12_baco.o smu9_baco.o tonga_baco.o polaris_baco.o fiji_baco.o \
+-		ci_baco.o
++		ci_baco.o smu7_baco.o
+ 
+ AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c
+index f1a8c9cc0d1f..3be40114e63d 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c
+@@ -158,43 +158,11 @@ static const struct baco_cmd_entry clean_baco_tbl[] =
+ 	{ CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 }
+ };
+ 
+-int ci_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
+-{
+-	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+-	uint32_t reg;
+-
+-	*cap = false;
+-	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
+-		return 0;
+-
+-	reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
+-
+-	if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
+-		*cap = true;
+-
+-	return 0;
+-}
+-
+-int ci_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
+-{
+-	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+-	uint32_t reg;
+-
+-	reg = RREG32(mmBACO_CNTL);
+-
+-	if (reg & BACO_CNTL__BACO_MODE_MASK)
+-		/* gfx has already entered BACO state */
+-		*state = BACO_STATE_IN;
+-	else
+-		*state = BACO_STATE_OUT;
+-	return 0;
+-}
+-
+ int ci_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ {
+ 	enum BACO_STATE cur_state;
+ 
+-	ci_baco_get_state(hwmgr, &cur_state);
++	smu7_baco_get_state(hwmgr, &cur_state);
+ 
+ 	if (cur_state == state)
+ 		/* aisc already in the target state */
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h
+index c9bedb51cb25..17041f187020 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h
+@@ -22,11 +22,8 @@
+  */
+ #ifndef __CI_BACO_H__
+ #define __CI_BACO_H__
+-#include "hwmgr.h"
+-#include "common_baco.h"
++#include "smu7_baco.h"
+ 
+-extern int ci_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
+-extern int ci_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
+ extern int ci_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c
+index ad01919ccb27..c0368f2dfb21 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c
+@@ -158,43 +158,11 @@ static const struct baco_cmd_entry clean_baco_tbl[] =
+ 	{ CMD_WRITE, mmBIOS_SCRATCH_15, 0, 0, 0, 0 }
+ };
+ 
+-int fiji_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
+-{
+-	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+-	uint32_t reg;
+-
+-	*cap = false;
+-	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
+-		return 0;
+-
+-	reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
+-
+-	if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
+-		*cap = true;
+-
+-	return 0;
+-}
+-
+-int fiji_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
+-{
+-	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+-	uint32_t reg;
+-
+-	reg = RREG32(mmBACO_CNTL);
+-
+-	if (reg & BACO_CNTL__BACO_MODE_MASK)
+-		/* gfx has already entered BACO state */
+-		*state = BACO_STATE_IN;
+-	else
+-		*state = BACO_STATE_OUT;
+-	return 0;
+-}
+-
+ int fiji_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ {
+ 	enum BACO_STATE cur_state;
+ 
+-	fiji_baco_get_state(hwmgr, &cur_state);
++	smu7_baco_get_state(hwmgr, &cur_state);
+ 
+ 	if (cur_state == state)
+ 		/* aisc already in the target state */
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h
+index 2f7c8388667e..47f402900bdb 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h
+@@ -22,11 +22,8 @@
+  */
+ #ifndef __FIJI_BACO_H__
+ #define __FIJI_BACO_H__
+-#include "hwmgr.h"
+-#include "common_baco.h"
++#include "smu7_baco.h"
+ 
+-extern int fiji_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
+-extern int fiji_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
+ extern int fiji_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
+index a9abe53df475..8f8e296f2fe9 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
+@@ -178,43 +178,11 @@ static const struct baco_cmd_entry turn_off_plls_tbl_vg[] =
+ 	{ CMD_DELAY_US, 0, 0, 0, 5, 0x0 }
+ };
+ 
+-int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
+-{
+-	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+-	uint32_t reg;
+-
+-	*cap = false;
+-	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
+-		return 0;
+-
+-	reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
+-
+-	if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
+-		*cap = true;
+-
+-	return 0;
+-}
+-
+-int polaris_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
+-{
+-	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+-	uint32_t reg;
+-
+-	reg = RREG32(mmBACO_CNTL);
+-
+-	if (reg & BACO_CNTL__BACO_MODE_MASK)
+-		/* gfx has already entered BACO state */
+-		*state = BACO_STATE_IN;
+-	else
+-		*state = BACO_STATE_OUT;
+-	return 0;
+-}
+-
+ int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ {
+ 	enum BACO_STATE cur_state;
+ 
+-	polaris_baco_get_state(hwmgr, &cur_state);
++	smu7_baco_get_state(hwmgr, &cur_state);
+ 
+ 	if (cur_state == state)
+ 		/* aisc already in the target state */
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h
+index e48bfb1c5c6a..87a5fa0a157a 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h
+@@ -22,11 +22,8 @@
+  */
+ #ifndef __POLARIS_BACO_H__
+ #define __POLARIS_BACO_H__
+-#include "hwmgr.h"
+-#include "common_baco.h"
++#include "smu7_baco.h"
+ 
+-extern int polaris_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
+-extern int polaris_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
+ extern int polaris_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c
+new file mode 100644
+index 000000000000..044cda005aed
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c
+@@ -0,0 +1,91 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "amdgpu.h"
++#include "smu7_baco.h"
++#include "tonga_baco.h"
++#include "fiji_baco.h"
++#include "polaris_baco.h"
++#include "ci_baco.h"
++
++#include "bif/bif_5_0_d.h"
++#include "bif/bif_5_0_sh_mask.h"
++
++#include "smu/smu_7_1_2_d.h"
++#include "smu/smu_7_1_2_sh_mask.h"
++
++int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++	uint32_t reg;
++
++	*cap = false;
++	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
++		return 0;
++
++	reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
++
++	if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
++		*cap = true;
++
++	return 0;
++}
++
++int smu7_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++	uint32_t reg;
++
++	reg = RREG32(mmBACO_CNTL);
++
++	if (reg & BACO_CNTL__BACO_MODE_MASK)
++		/* gfx has already entered BACO state */
++		*state = BACO_STATE_IN;
++	else
++		*state = BACO_STATE_OUT;
++	return 0;
++}
++
++int smu7_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
++
++	switch (adev->asic_type) {
++	case CHIP_TOPAZ:
++	case CHIP_TONGA:
++		return tonga_baco_set_state(hwmgr, state);
++	case CHIP_FIJI:
++		return fiji_baco_set_state(hwmgr, state);
++	case CHIP_POLARIS10:
++	case CHIP_POLARIS11:
++	case CHIP_POLARIS12:
++	case CHIP_VEGAM:
++		return polaris_baco_set_state(hwmgr, state);
++#ifdef CONFIG_DRM_AMDGPU_CIK
++	case CHIP_BONAIRE:
++	case CHIP_HAWAII:
++		return ci_baco_set_state(hwmgr, state);
++#endif
++	default:
++		return -EINVAL;
++	}
++}
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h
+new file mode 100644
+index 000000000000..be0d98abb536
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h
+@@ -0,0 +1,32 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#ifndef __SMU7_BACO_H__
++#define __SMU7_BACO_H__
++#include "hwmgr.h"
++#include "common_baco.h"
++
++extern int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
++extern int smu7_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
++extern int smu7_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
+index 84b7217b7bda..ea743bea8e29 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
+@@ -182,43 +182,11 @@ static const struct baco_cmd_entry clean_baco_tbl_iceland[] =
+ 	{ CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 }
+ };
+ 
+-int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
+-{
+-	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+-	uint32_t reg;
+-
+-	*cap = false;
+-	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
+-		return 0;
+-
+-	reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
+-
+-	if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
+-		*cap = true;
+-
+-	return 0;
+-}
+-
+-int tonga_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
+-{
+-	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+-	uint32_t reg;
+-
+-	reg = RREG32(mmBACO_CNTL);
+-
+-	if (reg & BACO_CNTL__BACO_MODE_MASK)
+-		/* gfx has already entered BACO state */
+-		*state = BACO_STATE_IN;
+-	else
+-		*state = BACO_STATE_OUT;
+-	return 0;
+-}
+-
+ int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+ {
+ 	enum BACO_STATE cur_state;
+ 
+-	tonga_baco_get_state(hwmgr, &cur_state);
++	smu7_baco_get_state(hwmgr, &cur_state);
+ 
+ 	if (cur_state == state)
+ 		/* aisc already in the target state */
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h
+index 21301b043255..5dc16cc8a295 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h
+@@ -22,11 +22,8 @@
+  */
+ #ifndef __TONGA_BACO_H__
+ #define __TONGA_BACO_H__
+-#include "hwmgr.h"
+-#include "common_baco.h"
++#include "smu7_baco.h"
+ 
+-extern int tonga_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
+-extern int tonga_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
+ extern int tonga_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
+ 
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4163-drm-amdgpu-powerplay-wire-up-BACO-to-powerplay-API-f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4163-drm-amdgpu-powerplay-wire-up-BACO-to-powerplay-API-f.patch
new file mode 100644
index 00000000..8bcd8982
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4163-drm-amdgpu-powerplay-wire-up-BACO-to-powerplay-API-f.patch
@@ -0,0 +1,43 @@
+From 822464648a32206c3ec2e1992a6d190a14234c85 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Feb 2019 18:17:24 -0500
+Subject: [PATCH 4163/4736] drm/amdgpu/powerplay: wire up BACO to powerplay API
+ for smu7
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Wire up the powerplay callbacks for for BACO for smu7 devices.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+index 897fd494fe33..80bfdf178892 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -47,6 +47,7 @@
+ #include "smu7_clockpowergating.h"
+ #include "processpptables.h"
+ #include "pp_thermal.h"
++#include "smu7_baco.h"
+ 
+ #include "ivsrcid/ivsrcid_vislands30.h"
+ 
+@@ -5142,6 +5143,9 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
+ 	.get_power_profile_mode = smu7_get_power_profile_mode,
+ 	.set_power_profile_mode = smu7_set_power_profile_mode,
+ 	.get_performance_level = smu7_get_performance_level,
++	.get_asic_baco_capability = smu7_baco_get_capability,
++	.get_asic_baco_state = smu7_baco_get_state,
++	.set_asic_baco_state = smu7_baco_set_state,
+ 	.power_off_asic = smu7_power_off_asic,
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4164-drm-amdgpu-enable-BACO-reset-for-SMU7-based-dGPUs-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4164-drm-amdgpu-enable-BACO-reset-for-SMU7-based-dGPUs-v2.patch
new file mode 100644
index 00000000..15c281cd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4164-drm-amdgpu-enable-BACO-reset-for-SMU7-based-dGPUs-v2.patch
@@ -0,0 +1,230 @@
+From 97b0504af3ca00ce13f45fbdfb17767ee4abc4c9 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 11 Mar 2019 18:05:12 -0500
+Subject: [PATCH 4164/4736] drm/amdgpu: enable BACO reset for SMU7 based dGPUs
+ (v2)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use BACO to reset the GPU if supported on SMU7 based
+dGPUs.
+
+v2: don't use baco on CI parts
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/cik.c | 48 ++++++++++++++++--
+ drivers/gpu/drm/amd/amdgpu/cik.h |  3 ++
+ drivers/gpu/drm/amd/amdgpu/vi.c  | 84 ++++++++++++++++++++++++++++++--
+ drivers/gpu/drm/amd/amdgpu/vi.h  |  3 ++
+ 4 files changed, 128 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
+index 7b63d7a8298a..e3c524c8926a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik.c
+@@ -1269,15 +1269,15 @@ static int cik_gpu_pci_config_reset(struct amdgpu_device *adev)
+ }
+ 
+ /**
+- * cik_asic_reset - soft reset GPU
++ * cik_asic_pci_config_reset - soft reset GPU
+  *
+  * @adev: amdgpu_device pointer
+  *
+- * Look up which blocks are hung and attempt
+- * to reset them.
++ * Use PCI Config method to reset the GPU.
++ *
+  * Returns 0 for success.
+  */
+-static int cik_asic_reset(struct amdgpu_device *adev)
++static int cik_asic_pci_config_reset(struct amdgpu_device *adev)
+ {
+ 	int r;
+ 
+@@ -1293,7 +1293,45 @@ static int cik_asic_reset(struct amdgpu_device *adev)
+ static enum amd_reset_method
+ cik_asic_reset_method(struct amdgpu_device *adev)
+ {
+-	return AMD_RESET_METHOD_LEGACY;
++	bool baco_reset;
++
++	switch (adev->asic_type) {
++	case CHIP_BONAIRE:
++	case CHIP_HAWAII:
++		/* disable baco reset until it works */
++		/* smu7_asic_get_baco_capability(adev, &baco_reset); */
++		baco_reset = false;
++		break;
++	default:
++		baco_reset = false;
++		break;
++	}
++
++	if (baco_reset)
++		return AMD_RESET_METHOD_BACO;
++	else
++		return AMD_RESET_METHOD_LEGACY;
++}
++
++/**
++ * cik_asic_reset - soft reset GPU
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Look up which blocks are hung and attempt
++ * to reset them.
++ * Returns 0 for success.
++ */
++static int cik_asic_reset(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (cik_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
++		r = smu7_asic_baco_reset(adev);
++	else
++		r = cik_asic_pci_config_reset(adev);
++
++	return r;
+ }
+ 
+ static u32 cik_get_config_memsize(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik.h b/drivers/gpu/drm/amd/amdgpu/cik.h
+index 54c625a2e570..9870bf27870e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik.h
++++ b/drivers/gpu/drm/amd/amdgpu/cik.h
+@@ -31,4 +31,7 @@ void cik_srbm_select(struct amdgpu_device *adev,
+ int cik_set_ip_blocks(struct amdgpu_device *adev);
+ 
+ void legacy_doorbell_index_init(struct amdgpu_device *adev);
++int smu7_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap);
++int smu7_asic_baco_reset(struct amdgpu_device *adev);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
+index 56c882b3ea3c..34a466e785cb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vi.c
++++ b/drivers/gpu/drm/amd/amdgpu/vi.c
+@@ -687,16 +687,50 @@ static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
+ 	return -EINVAL;
+ }
+ 
++int smu7_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
++{
++	void *pp_handle = adev->powerplay.pp_handle;
++	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
++
++	if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
++		*cap = false;
++		return -ENOENT;
++	}
++
++	return pp_funcs->get_asic_baco_capability(pp_handle, cap);
++}
++
++int smu7_asic_baco_reset(struct amdgpu_device *adev)
++{
++	void *pp_handle = adev->powerplay.pp_handle;
++	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
++
++	if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
++		return -ENOENT;
++
++	/* enter BACO state */
++	if (pp_funcs->set_asic_baco_state(pp_handle, 1))
++		return -EIO;
++
++	/* exit BACO state */
++	if (pp_funcs->set_asic_baco_state(pp_handle, 0))
++		return -EIO;
++
++	dev_info(adev->dev, "GPU BACO reset\n");
++
++	return 0;
++}
++
+ /**
+- * vi_asic_reset - soft reset GPU
++ * vi_asic_pci_config_reset - soft reset GPU
+  *
+  * @adev: amdgpu_device pointer
+  *
+- * Look up which blocks are hung and attempt
+- * to reset them.
++ * Use PCI Config method to reset the GPU.
++ *
+  * Returns 0 for success.
+  */
+-static int vi_asic_reset(struct amdgpu_device *adev)
++static int vi_asic_pci_config_reset(struct amdgpu_device *adev)
+ {
+ 	int r;
+ 
+@@ -712,7 +746,47 @@ static int vi_asic_reset(struct amdgpu_device *adev)
+ static enum amd_reset_method
+ vi_asic_reset_method(struct amdgpu_device *adev)
+ {
+-	return AMD_RESET_METHOD_LEGACY;
++	bool baco_reset;
++
++	switch (adev->asic_type) {
++	case CHIP_FIJI:
++	case CHIP_TONGA:
++	case CHIP_POLARIS10:
++	case CHIP_POLARIS11:
++	case CHIP_POLARIS12:
++	case CHIP_TOPAZ:
++		smu7_asic_get_baco_capability(adev, &baco_reset);
++		break;
++	default:
++		baco_reset = false;
++		break;
++	}
++
++	if (baco_reset)
++		return AMD_RESET_METHOD_BACO;
++	else
++		return AMD_RESET_METHOD_LEGACY;
++}
++
++/**
++ * vi_asic_reset - soft reset GPU
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Look up which blocks are hung and attempt
++ * to reset them.
++ * Returns 0 for success.
++ */
++static int vi_asic_reset(struct amdgpu_device *adev)
++{
++	int r;
++
++	if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
++		r = smu7_asic_baco_reset(adev);
++	else
++		r = vi_asic_pci_config_reset(adev);
++
++	return r;
+ }
+ 
+ static u32 vi_get_config_memsize(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h
+index 8de0772f986c..40d4174913a4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vi.h
++++ b/drivers/gpu/drm/amd/amdgpu/vi.h
+@@ -31,4 +31,7 @@ void vi_srbm_select(struct amdgpu_device *adev,
+ int vi_set_ip_blocks(struct amdgpu_device *adev);
+ 
+ void legacy_doorbell_index_init(struct amdgpu_device *adev);
++int smu7_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap);
++int smu7_asic_baco_reset(struct amdgpu_device *adev);
++
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4165-drm-amdgpu-simplify-ATPX-detection.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4165-drm-amdgpu-simplify-ATPX-detection.patch
new file mode 100644
index 00000000..c292e9ab
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4165-drm-amdgpu-simplify-ATPX-detection.patch
@@ -0,0 +1,41 @@
+From e1ba8d889f2a06ace9596ac989cd48618484bf9b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 9 Oct 2019 14:39:37 -0500
+Subject: [PATCH 4165/4736] drm/amdgpu: simplify ATPX detection
+
+Use the base class rather than the specific class and drop
+the second loop.
+
+Change-Id: Ic4d4dba633a655531c5bd6ec99f903a0805e7455
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 12 +-----------
+ 1 file changed, 1 insertion(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+index 354c8b6106dc..7bebe128dd7b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+@@ -614,17 +614,7 @@ static bool amdgpu_atpx_detect(void)
+ 	bool d3_supported = false;
+ 	struct pci_dev *parent_pdev;
+ 
+-	while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
+-		vga_count++;
+-
+-		has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
+-
+-		parent_pdev = pci_upstream_bridge(pdev);
+-		d3_supported |= parent_pdev && parent_pdev->bridge_d3;
+-		amdgpu_atpx_get_quirks(pdev);
+-	}
+-
+-	while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
++	while ((pdev = pci_get_class(PCI_BASE_CLASS_DISPLAY << 16, pdev)) != NULL) {
+ 		vga_count++;
+ 
+ 		has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4166-drm-amd-powerplay-bug-fix-for-memory-clock-request-f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4166-drm-amd-powerplay-bug-fix-for-memory-clock-request-f.patch
new file mode 100644
index 00000000..fe9f0230
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4166-drm-amd-powerplay-bug-fix-for-memory-clock-request-f.patch
@@ -0,0 +1,34 @@
+From fea8cac04d037e0669ac0ac5fa54c1222cff8769 Mon Sep 17 00:00:00 2001
+From: Kenneth Feng <kenneth.feng@amd.com>
+Date: Wed, 16 Oct 2019 16:20:38 +0800
+Subject: [PATCH 4166/4736] drm/amd/powerplay: bug fix for memory clock request
+ from display
+
+In some cases, display fixes memory clock frequency to a high value
+rather than the natural memory clock switching.
+When we comes back from s3 resume, the request from display is not reset,
+this causes the bug which makes the memory clock goes into a low value.
+Then due to the insuffcient memory clock, the screen flicks.
+
+Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index d0a25dd8fcfc..fb5a55091292 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1354,6 +1354,8 @@ static int smu_resume(void *handle)
+ 	if (smu->is_apu)
+ 		smu_set_gfx_cgpg(&adev->smu, true);
+ 
++	smu->disable_uclk_switch = 0;
++
+ 	mutex_unlock(&smu->mutex);
+ 
+ 	pr_info("SMU is resumed successfully!\n");
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4167-drm-amdgpu-No-need-to-check-gfxoff-status-after-enab.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4167-drm-amdgpu-No-need-to-check-gfxoff-status-after-enab.patch
new file mode 100644
index 00000000..57d925e9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4167-drm-amdgpu-No-need-to-check-gfxoff-status-after-enab.patch
@@ -0,0 +1,43 @@
+From d37f0200c8aa88982cb2358aac4684195d407585 Mon Sep 17 00:00:00 2001
+From: chen gong <curry.gong@amd.com>
+Date: Wed, 16 Oct 2019 18:04:02 +0800
+Subject: [PATCH 4167/4736] drm/amdgpu: No need to check gfxoff status after
+ enable gfxoff feature
+
+smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff) Just turn on a switch.
+
+As to when GPU get into "GFXoff" will be up to drawing load.
+
+So we can not sure which state GPU should be in after enable gfxoff
+feature.
+
+Signed-off-by: chen gong <curry.gong@amd.com>
+Acked-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 9 ---------
+ 1 file changed, 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index c9691d0fb523..cac4269cf1d1 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -244,15 +244,6 @@ static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
+ 	if (enable) {
+ 		ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
+ 
+-		/* confirm gfx is back to "off" state, timeout is 5 seconds */
+-		while (!(smu_v12_0_get_gfxoff_status(smu) == 0)) {
+-			msleep(10);
+-			timeout--;
+-			if (timeout == 0) {
+-				DRM_ERROR("enable gfxoff timeout and failed!\n");
+-				break;
+-			}
+-		}
+ 	} else {
+ 		ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4168-drm-amd-display-update-register-field-access-mechani.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4168-drm-amd-display-update-register-field-access-mechani.patch
new file mode 100644
index 00000000..f41a5fc7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4168-drm-amd-display-update-register-field-access-mechani.patch
@@ -0,0 +1,546 @@
+From 40d01f785cf532f60d467345b0f371059017537b Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Tue, 13 Aug 2019 09:24:10 -0400
+Subject: [PATCH 4168/4736] drm/amd/display: update register field access
+ mechanism
+
+1-add timeout length and multiplier fields to aux_control1 register
+2-update access mechanism from macro constructed name to uint32_t
+defined addresses.
+3-define registers and field per asic family
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c  |  11 +-
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.h  | 175 +++++++++++++++++-
+ .../amd/display/dc/dce100/dce100_resource.c   |  12 +-
+ .../amd/display/dc/dce110/dce110_resource.c   |  12 +-
+ .../amd/display/dc/dce112/dce112_resource.c   |  12 +-
+ .../amd/display/dc/dce120/dce120_resource.c   |  12 +-
+ .../drm/amd/display/dc/dce80/dce80_resource.c |  12 +-
+ .../drm/amd/display/dc/dcn10/dcn10_resource.c |  12 +-
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c |  13 +-
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c |  12 +-
+ 10 files changed, 271 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+index 16960ef29132..574447185f4a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+@@ -39,6 +39,10 @@
+ 
+ #include "reg_helper.h"
+ 
++#undef FN
++#define FN(reg_name, field_name) \
++	aux110->shift->field_name, aux110->mask->field_name
++
+ #define FROM_AUX_ENGINE(ptr) \
+ 	container_of((ptr), struct aux_engine_dce110, base)
+ 
+@@ -411,11 +415,14 @@ void dce110_engine_destroy(struct dce_aux **engine)
+ 	*engine = NULL;
+ 
+ }
++
+ struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110,
+ 		struct dc_context *ctx,
+ 		uint32_t inst,
+ 		uint32_t timeout_period,
+-		const struct dce110_aux_registers *regs)
++		const struct dce110_aux_registers *regs,
++		const struct dce110_aux_registers_mask *mask,
++		const struct dce110_aux_registers_shift *shift)
+ {
+ 	aux_engine110->base.ddc = NULL;
+ 	aux_engine110->base.ctx = ctx;
+@@ -425,6 +432,8 @@ struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine
+ 	aux_engine110->timeout_period = timeout_period;
+ 	aux_engine110->regs = regs;
+ 
++	aux_engine110->mask = mask;
++	aux_engine110->shift = shift;
+ 	return &aux_engine110->base;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+index ed7fec8fe253..717378502e9d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+@@ -29,6 +29,7 @@
+ #include "i2caux_interface.h"
+ #include "inc/hw/aux_engine.h"
+ 
++
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ #define AUX_COMMON_REG_LIST0(id)\
+ 	SRI(AUX_CONTROL, DP_AUX, id), \
+@@ -36,6 +37,7 @@
+ 	SRI(AUX_SW_DATA, DP_AUX, id), \
+ 	SRI(AUX_SW_CONTROL, DP_AUX, id), \
+ 	SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
++	SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id), \
+ 	SRI(AUX_SW_STATUS, DP_AUX, id)
+ #endif
+ 
+@@ -55,6 +57,7 @@ struct dce110_aux_registers {
+ 	uint32_t AUX_SW_DATA;
+ 	uint32_t AUX_SW_CONTROL;
+ 	uint32_t AUX_INTERRUPT_CONTROL;
++	uint32_t AUX_DPHY_RX_CONTROL1;
+ 	uint32_t AUX_SW_STATUS;
+ 	uint32_t AUXN_IMPCAL;
+ 	uint32_t AUXP_IMPCAL;
+@@ -62,6 +65,156 @@ struct dce110_aux_registers {
+ 	uint32_t AUX_RESET_MASK;
+ };
+ 
++#define DCE_AUX_REG_FIELD_LIST(type)\
++	type AUX_EN;\
++	type AUX_RESET;\
++	type AUX_RESET_DONE;\
++	type AUX_REG_RW_CNTL_STATUS;\
++	type AUX_SW_USE_AUX_REG_REQ;\
++	type AUX_SW_DONE_USING_AUX_REG;\
++	type AUX_SW_AUTOINCREMENT_DISABLE;\
++	type AUX_SW_DATA_RW;\
++	type AUX_SW_INDEX;\
++	type AUX_SW_GO;\
++	type AUX_SW_DATA;\
++	type AUX_SW_REPLY_BYTE_COUNT;\
++	type AUX_SW_DONE;\
++	type AUX_SW_DONE_ACK;\
++	type AUXN_IMPCAL_ENABLE;\
++	type AUXP_IMPCAL_ENABLE;\
++	type AUXN_IMPCAL_OVERRIDE_ENABLE;\
++	type AUXP_IMPCAL_OVERRIDE_ENABLE;\
++	type AUX_RX_TIMEOUT_LEN;\
++	type AUX_RX_TIMEOUT_LEN_MUL;\
++	type AUXN_CALOUT_ERROR_AK;\
++	type AUXP_CALOUT_ERROR_AK;\
++	type AUX_SW_START_DELAY;\
++	type AUX_SW_WR_BYTES
++
++#define DCE10_AUX_MASK_SH_LIST(mask_sh)\
++	AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
++	AUX_SF(AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
++	AUX_SF(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
++	AUX_SF(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
++	AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
++	AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
++	AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
++	AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++	AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
++	AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++	AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
++	AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
++	AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
++	AUX_SF(AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
++	AUX_SF(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
++	AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
++	AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
++	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
++	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
++	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
++	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
++
++#define DCE_AUX_MASK_SH_LIST(mask_sh)\
++	AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
++	AUX_SF(AUX_CONTROL, AUX_RESET, mask_sh),\
++	AUX_SF(AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
++	AUX_SF(AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
++	AUX_SF(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
++	AUX_SF(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
++	AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
++	AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
++	AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
++	AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++	AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
++	AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++	AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
++	AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
++	AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
++	AUX_SF(AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
++	AUX_SF(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
++	AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
++	AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
++	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
++	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
++	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
++	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
++
++#define DCE12_AUX_MASK_SH_LIST(mask_sh)\
++	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
++	AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
++	AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
++	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
++	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
++	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
++	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
++
++/* DCN10 MASK */
++#define DCN10_AUX_MASK_SH_LIST(mask_sh)\
++	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
++	AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
++	AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
++	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
++	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
++	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
++	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
++
++/* for all other DCN */
++#define DCN_AUX_MASK_SH_LIST(mask_sh)\
++	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\
++	AUX_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh)
++
++#define AUX_SF(reg_name, field_name, post_fix)\
++	.field_name = reg_name ## __ ## field_name ## post_fix
++
+ enum {	/* This is the timeout as defined in DP 1.2a,
+ 	 * 2.3.4 "Detailed uPacket TX AUX CH State Description".
+ 	 */
+@@ -97,17 +250,31 @@ struct dce_aux {
+ 	uint32_t max_defer_write_retry;
+ 
+ 	bool acquire_reset;
++	const struct dce_aux_funcs *funcs;
++};
++
++struct dce110_aux_registers_mask {
++	DCE_AUX_REG_FIELD_LIST(uint32_t);
+ };
+ 
++struct dce110_aux_registers_shift {
++	DCE_AUX_REG_FIELD_LIST(uint8_t);
++};
++
++
+ struct aux_engine_dce110 {
+ 	struct dce_aux base;
+ 	const struct dce110_aux_registers *regs;
++	const struct dce110_aux_registers_mask *mask;
++	const struct dce110_aux_registers_shift *shift;
+ 	struct {
+ 		uint32_t aux_control;
+ 		uint32_t aux_arb_control;
+ 		uint32_t aux_sw_data;
+ 		uint32_t aux_sw_control;
+ 		uint32_t aux_interrupt_control;
++		uint32_t aux_dphy_rx_control1;
++		uint32_t aux_dphy_rx_control0;
+ 		uint32_t aux_sw_status;
+ 	} addr;
+ 	uint32_t timeout_period;
+@@ -120,12 +287,14 @@ struct aux_engine_dce110_init_data {
+ 	const struct dce110_aux_registers *regs;
+ };
+ 
+-struct dce_aux *dce110_aux_engine_construct(
+-		struct aux_engine_dce110 *aux_engine110,
++struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110,
+ 		struct dc_context *ctx,
+ 		uint32_t inst,
+ 		uint32_t timeout_period,
+-		const struct dce110_aux_registers *regs);
++		const struct dce110_aux_registers *regs,
++
++		const struct dce110_aux_registers_mask *mask,
++		const struct dce110_aux_registers_shift *shift);
+ 
+ void dce110_engine_destroy(struct dce_aux **engine);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+index 3614e516489f..fe1538ab76ba 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+@@ -534,6 +534,14 @@ static const struct dce_mem_input_mask mi_masks = {
+ 		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
+ };
+ 
++static const struct dce110_aux_registers_shift aux_shift = {
++	DCE10_AUX_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dce110_aux_registers_mask aux_mask = {
++	DCE10_AUX_MASK_SH_LIST(_MASK)
++};
++
+ static struct mem_input *dce100_mem_input_create(
+ 	struct dc_context *ctx,
+ 	uint32_t inst)
+@@ -643,7 +651,9 @@ struct dce_aux *dce100_aux_engine_create(
+ 
+ 	dce110_aux_engine_construct(aux_engine, ctx, inst,
+ 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+-				    &aux_engine_regs[inst]);
++				    &aux_engine_regs[inst],
++					&aux_mask,
++					&aux_shift);
+ 
+ 	return &aux_engine->base;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index a487b75d23b6..06ecdf044ddc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -273,6 +273,14 @@ static const struct dce_stream_encoder_mask se_mask = {
+ 		SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
+ };
+ 
++static const struct dce110_aux_registers_shift aux_shift = {
++	DCE_AUX_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dce110_aux_registers_mask aux_mask = {
++	DCE_AUX_MASK_SH_LIST(_MASK)
++};
++
+ #define opp_regs(id)\
+ [id] = {\
+ 	OPP_DCE_110_REG_LIST(id),\
+@@ -690,7 +698,9 @@ struct dce_aux *dce110_aux_engine_create(
+ 
+ 	dce110_aux_engine_construct(aux_engine, ctx, inst,
+ 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+-				    &aux_engine_regs[inst]);
++				    &aux_engine_regs[inst],
++					&aux_mask,
++					&aux_shift);
+ 
+ 	return &aux_engine->base;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+index ec67db9c86e8..8dc75f71240d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+@@ -170,6 +170,14 @@ static const struct dce_abm_mask abm_mask = {
+ 		ABM_MASK_SH_LIST_DCE110(_MASK)
+ };
+ 
++static const struct dce110_aux_registers_shift aux_shift = {
++	DCE_AUX_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dce110_aux_registers_mask aux_mask = {
++	DCE_AUX_MASK_SH_LIST(_MASK)
++};
++
+ #define ipp_regs(id)\
+ [id] = {\
+ 		IPP_DCE110_REG_LIST_DCE_BASE(id)\
+@@ -663,7 +671,9 @@ struct dce_aux *dce112_aux_engine_create(
+ 
+ 	dce110_aux_engine_construct(aux_engine, ctx, inst,
+ 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+-				    &aux_engine_regs[inst]);
++				    &aux_engine_regs[inst],
++					&aux_mask,
++					&aux_shift);
+ 
+ 	return &aux_engine->base;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index b5b9a74086a0..3aac593f9b2e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -291,6 +291,14 @@ static const struct dce_stream_encoder_mask se_mask = {
+ 		SE_COMMON_MASK_SH_LIST_DCE120(_MASK)
+ };
+ 
++static const struct dce110_aux_registers_shift aux_shift = {
++	DCE12_AUX_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dce110_aux_registers_mask aux_mask = {
++	DCE12_AUX_MASK_SH_LIST(_MASK)
++};
++
+ #define opp_regs(id)\
+ [id] = {\
+ 	OPP_DCE_120_REG_LIST(id),\
+@@ -433,7 +441,9 @@ struct dce_aux *dce120_aux_engine_create(
+ 
+ 	dce110_aux_engine_construct(aux_engine, ctx, inst,
+ 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+-				    &aux_engine_regs[inst]);
++				    &aux_engine_regs[inst],
++					&aux_mask,
++					&aux_shift);
+ 
+ 	return &aux_engine->base;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+index 8e2aa0abf87c..934d8deb95fc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -286,6 +286,14 @@ static const struct dce_opp_mask opp_mask = {
+ 	OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
+ };
+ 
++static const struct dce110_aux_registers_shift aux_shift = {
++	DCE10_AUX_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dce110_aux_registers_mask aux_mask = {
++	DCE10_AUX_MASK_SH_LIST(_MASK)
++};
++
+ #define aux_engine_regs(id)\
+ [id] = {\
+ 	AUX_COMMON_REG_LIST(id), \
+@@ -520,7 +528,9 @@ struct dce_aux *dce80_aux_engine_create(
+ 
+ 	dce110_aux_engine_construct(aux_engine, ctx, inst,
+ 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+-				    &aux_engine_regs[inst]);
++				    &aux_engine_regs[inst],
++					&aux_mask,
++					&aux_shift);
+ 
+ 	return &aux_engine->base;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index 4522097e8a26..82dbc00afe54 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -317,6 +317,14 @@ static const struct dcn10_link_enc_mask le_mask = {
+ 		LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
+ };
+ 
++static const struct dce110_aux_registers_shift aux_shift = {
++	DCN10_AUX_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dce110_aux_registers_mask aux_mask = {
++	DCN10_AUX_MASK_SH_LIST(_MASK)
++};
++
+ #define ipp_regs(id)\
+ [id] = {\
+ 	IPP_REG_LIST_DCN10(id),\
+@@ -662,7 +670,9 @@ struct dce_aux *dcn10_aux_engine_create(
+ 
+ 	dce110_aux_engine_construct(aux_engine, ctx, inst,
+ 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+-				    &aux_engine_regs[inst]);
++				    &aux_engine_regs[inst],
++					&aux_mask,
++					&aux_shift);
+ 
+ 	return &aux_engine->base;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 968dc5fe4f1b..f2db1fa2eba9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -732,6 +732,15 @@ static const struct dcn20_vmid_mask vmid_masks = {
+ 		DCN20_VMID_MASK_SH_LIST(_MASK)
+ };
+ 
++static const struct dce110_aux_registers_shift aux_shift = {
++		DCN_AUX_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dce110_aux_registers_mask aux_mask = {
++		DCN_AUX_MASK_SH_LIST(_MASK)
++};
++
++
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #define dsc_regsDCN20(id)\
+ [id] = {\
+@@ -949,7 +958,9 @@ struct dce_aux *dcn20_aux_engine_create(
+ 
+ 	dce110_aux_engine_construct(aux_engine, ctx, inst,
+ 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+-				    &aux_engine_regs[inst]);
++				    &aux_engine_regs[inst],
++					&aux_mask,
++					&aux_shift);
+ 
+ 	return &aux_engine->base;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 2cc93e2e6ec0..dc5d28d002df 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -628,6 +628,14 @@ static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
+ 	stream_enc_regs(4),
+ };
+ 
++static const struct dce110_aux_registers_shift aux_shift = {
++	DCN_AUX_MASK_SH_LIST(__SHIFT)
++};
++
++static const struct dce110_aux_registers_mask aux_mask = {
++	DCN_AUX_MASK_SH_LIST(_MASK)
++};
++
+ static const struct dcn10_stream_encoder_shift se_shift = {
+ 		SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
+ };
+@@ -685,7 +693,9 @@ static struct dce_aux *dcn21_aux_engine_create(
+ 
+ 	dce110_aux_engine_construct(aux_engine, ctx, inst,
+ 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+-				    &aux_engine_regs[inst]);
++				    &aux_engine_regs[inst],
++					&aux_mask,
++					&aux_shift);
+ 
+ 	return &aux_engine->base;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4169-drm-amd-display-configurable-aux-timeout-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4169-drm-amd-display-configurable-aux-timeout-support.patch
new file mode 100644
index 00000000..9f39709d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4169-drm-amd-display-configurable-aux-timeout-support.patch
@@ -0,0 +1,467 @@
+From 7a69015f1ac7aad129d6750e20eb30493409e6ec Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Thu, 18 Jul 2019 15:58:25 -0400
+Subject: [PATCH 4169/4736] drm/amd/display: configurable aux timeout support
+
+[Description]
+1-add configurable timeout support to aux engine.
+2-add timeout support field to dc_caps
+3-add reg_key to override extended timeout support
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 14 ++++
+ drivers/gpu/drm/amd/display/dc/dc.h           |  2 +
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c  | 73 ++++++++++++++++++-
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.h  | 16 +++-
+ .../amd/display/dc/dce100/dce100_resource.c   |  5 +-
+ .../amd/display/dc/dce110/dce110_resource.c   |  4 +-
+ .../amd/display/dc/dce112/dce112_resource.c   |  5 +-
+ .../amd/display/dc/dce120/dce120_resource.c   |  5 +-
+ .../drm/amd/display/dc/dce80/dce80_resource.c |  4 +-
+ .../drm/amd/display/dc/dcn10/dcn10_resource.c |  5 +-
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c |  4 +-
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c |  4 +-
+ .../gpu/drm/amd/display/dc/inc/dc_link_ddc.h  |  3 +
+ .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |  2 +
+ .../drm/amd/display/dc/inc/hw/aux_engine.h    |  3 +
+ 15 files changed, 132 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+index 588a07b525a0..580594be1de5 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+@@ -632,6 +632,20 @@ bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc,
+ 	return dce_aux_transfer_with_retries(ddc, payload);
+ }
+ 
++
++enum dc_status dc_link_aux_configure_timeout(struct ddc_service *ddc,
++		uint32_t timeout)
++{
++	enum dc_status status = DC_OK;
++	struct ddc *ddc_pin = ddc->ddc_pin;
++
++	if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout == NULL)
++		return DC_ERROR_UNEXPECTED;
++	if (!ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout))
++		status = DC_ERROR_UNEXPECTED;
++	return status;
++}
++
+ /*test only function*/
+ void dal_ddc_service_set_ddc_pin(
+ 	struct ddc_service *ddc_service,
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 41e366f59f10..5967106826ca 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -111,6 +111,7 @@ struct dc_caps {
+ 	bool force_dp_tps4_for_cp2520;
+ 	bool disable_dp_clk_share;
+ 	bool psp_setup_panel_mode;
++	bool extended_aux_timeout_support;
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	bool hw_3d_lut;
+ #endif
+@@ -220,6 +221,7 @@ struct dc_config {
+ 	bool power_down_display_on_boot;
+ 	bool edp_not_connected;
+ 	bool forced_clocks;
++	bool disable_extended_timeout_support; // Used to disable extended timeout and lttpr feature as well
+ 	bool multi_mon_pp_mclk_switch;
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+index 574447185f4a..a68edd0c2172 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+@@ -56,6 +56,14 @@ enum {
+ 	AUX_TIMED_OUT_RETRY_COUNTER = 2,
+ 	AUX_DEFER_RETRY_COUNTER = 6
+ };
++
++#define TIME_OUT_INCREMENT      1016
++#define TIME_OUT_MULTIPLIER_8 	8
++#define TIME_OUT_MULTIPLIER_16  16
++#define TIME_OUT_MULTIPLIER_32  32
++#define TIME_OUT_MULTIPLIER_64  64
++#define MAX_TIMEOUT_LENGTH      127
++
+ static void release_engine(
+ 	struct dce_aux *engine)
+ {
+@@ -199,7 +207,7 @@ static void submit_channel_request(
+ 	REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);
+ 
+ 	REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,
+-				10, aux110->timeout_period/10);
++				10, aux110->polling_timeout_period/10);
+ 
+ 	/* set the delay and the number of bytes to write */
+ 
+@@ -328,7 +336,7 @@ static enum aux_channel_operation_result get_channel_status(
+ 
+ 	/* poll to make sure that SW_DONE is asserted */
+ 	REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1,
+-				10, aux110->timeout_period/10);
++				10, aux110->polling_timeout_period/10);
+ 
+ 	value = REG_READ(AUX_SW_STATUS);
+ 	/* in case HPD is LOW, exit AUX transaction */
+@@ -416,24 +424,81 @@ void dce110_engine_destroy(struct dce_aux **engine)
+ 
+ }
+ 
++static bool dce_aux_configure_timeout(struct ddc_service *ddc,
++		uint32_t timeout_in_us)
++{
++	uint32_t multiplier = 0;
++	uint32_t length = 0;
++	uint32_t timeout = 0;
++	struct ddc *ddc_pin = ddc->ddc_pin;
++	struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
++	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine);
++
++	/* 1-Update polling timeout period */
++	aux110->polling_timeout_period = timeout_in_us * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER;
++
++	/* 2-Update aux timeout period length and multiplier */
++	if (timeout_in_us <= TIME_OUT_INCREMENT) {
++		multiplier = 0;
++		length = timeout_in_us/TIME_OUT_MULTIPLIER_8;
++		if (timeout_in_us % TIME_OUT_MULTIPLIER_8 != 0)
++			length++;
++		timeout = length * TIME_OUT_MULTIPLIER_8;
++	} else if (timeout_in_us <= 2 * TIME_OUT_INCREMENT) {
++		multiplier = 1;
++		length = timeout_in_us/TIME_OUT_MULTIPLIER_16;
++		if (timeout_in_us % TIME_OUT_MULTIPLIER_16 != 0)
++			length++;
++		timeout = length * TIME_OUT_MULTIPLIER_16;
++	} else if (timeout_in_us <= 4 * TIME_OUT_INCREMENT) {
++		multiplier = 2;
++		length = timeout_in_us/TIME_OUT_MULTIPLIER_32;
++		if (timeout_in_us % TIME_OUT_MULTIPLIER_32 != 0)
++			length++;
++		timeout = length * TIME_OUT_MULTIPLIER_32;
++	} else if (timeout_in_us > 4 * TIME_OUT_INCREMENT) {
++		multiplier = 3;
++		length = timeout_in_us/TIME_OUT_MULTIPLIER_64;
++		if (timeout_in_us % TIME_OUT_MULTIPLIER_64 != 0)
++			length++;
++		timeout = length * TIME_OUT_MULTIPLIER_64;
++	}
++
++	length = (length < MAX_TIMEOUT_LENGTH) ? length : MAX_TIMEOUT_LENGTH;
++
++	REG_UPDATE_SEQ_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, length, AUX_RX_TIMEOUT_LEN_MUL, multiplier);
++
++	return true;
++}
++
++static struct dce_aux_funcs aux_functions = {
++	.configure_timeout = NULL,
++	.destroy = NULL,
++};
++
+ struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110,
+ 		struct dc_context *ctx,
+ 		uint32_t inst,
+ 		uint32_t timeout_period,
+ 		const struct dce110_aux_registers *regs,
+ 		const struct dce110_aux_registers_mask *mask,
+-		const struct dce110_aux_registers_shift *shift)
++		const struct dce110_aux_registers_shift *shift,
++		bool is_ext_aux_timeout_configurable)
+ {
+ 	aux_engine110->base.ddc = NULL;
+ 	aux_engine110->base.ctx = ctx;
+ 	aux_engine110->base.delay = 0;
+ 	aux_engine110->base.max_defer_write_retry = 0;
+ 	aux_engine110->base.inst = inst;
+-	aux_engine110->timeout_period = timeout_period;
++	aux_engine110->polling_timeout_period = timeout_period;
+ 	aux_engine110->regs = regs;
+ 
+ 	aux_engine110->mask = mask;
+ 	aux_engine110->shift = shift;
++	aux_engine110->base.funcs = &aux_functions;
++	if (is_ext_aux_timeout_configurable)
++		aux_engine110->base.funcs->configure_timeout = &dce_aux_configure_timeout;
++
+ 	return &aux_engine110->base;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+index 717378502e9d..b4b2c79a8073 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+@@ -250,7 +250,7 @@ struct dce_aux {
+ 	uint32_t max_defer_write_retry;
+ 
+ 	bool acquire_reset;
+-	const struct dce_aux_funcs *funcs;
++	struct dce_aux_funcs *funcs;
+ };
+ 
+ struct dce110_aux_registers_mask {
+@@ -277,7 +277,7 @@ struct aux_engine_dce110 {
+ 		uint32_t aux_dphy_rx_control0;
+ 		uint32_t aux_sw_status;
+ 	} addr;
+-	uint32_t timeout_period;
++	uint32_t polling_timeout_period;
+ };
+ 
+ struct aux_engine_dce110_init_data {
+@@ -294,7 +294,8 @@ struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine
+ 		const struct dce110_aux_registers *regs,
+ 
+ 		const struct dce110_aux_registers_mask *mask,
+-		const struct dce110_aux_registers_shift *shift);
++		const struct dce110_aux_registers_shift *shift,
++		bool is_ext_aux_timeout_configurable);
+ 
+ void dce110_engine_destroy(struct dce_aux **engine);
+ 
+@@ -308,4 +309,13 @@ int dce_aux_transfer_raw(struct ddc_service *ddc,
+ 
+ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
+ 		struct aux_payload *cmd);
++
++struct dce_aux_funcs {
++	bool (*configure_timeout)
++		(struct ddc_service *ddc,
++		 uint32_t timeout);
++	void (*destroy)
++		(struct aux_engine **ptr);
++};
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+index fe1538ab76ba..8ec9b4639fe7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+@@ -653,7 +653,8 @@ struct dce_aux *dce100_aux_engine_create(
+ 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+ 				    &aux_engine_regs[inst],
+ 					&aux_mask,
+-					&aux_shift);
++					&aux_shift,
++					ctx->dc->caps.extended_aux_timeout_support);
+ 
+ 	return &aux_engine->base;
+ }
+@@ -1039,6 +1040,8 @@ static bool construct(
+ 	dc->caps.max_cursor_size = 128;
+ 	dc->caps.dual_link_dvi = true;
+ 	dc->caps.disable_dp_clk_share = true;
++	dc->caps.extended_aux_timeout_support = false;
++
+ 	for (i = 0; i < pool->base.pipe_count; i++) {
+ 		pool->base.timing_generators[i] =
+ 			dce100_timing_generator_create(
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index 06ecdf044ddc..377fa9193ce1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -700,7 +700,8 @@ struct dce_aux *dce110_aux_engine_create(
+ 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+ 				    &aux_engine_regs[inst],
+ 					&aux_mask,
+-					&aux_shift);
++					&aux_shift,
++					ctx->dc->caps.extended_aux_timeout_support);
+ 
+ 	return &aux_engine->base;
+ }
+@@ -1336,6 +1337,7 @@ static bool construct(
+ 	dc->caps.i2c_speed_in_khz = 100;
+ 	dc->caps.max_cursor_size = 128;
+ 	dc->caps.is_apu = true;
++	dc->caps.extended_aux_timeout_support = false;
+ 
+ 	/*************************************************
+ 	 *  Create resources                             *
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+index 8dc75f71240d..5bde6ac2fa7e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+@@ -673,7 +673,8 @@ struct dce_aux *dce112_aux_engine_create(
+ 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+ 				    &aux_engine_regs[inst],
+ 					&aux_mask,
+-					&aux_shift);
++					&aux_shift,
++					ctx->dc->caps.extended_aux_timeout_support);
+ 
+ 	return &aux_engine->base;
+ }
+@@ -1206,7 +1207,7 @@ static bool construct(
+ 	dc->caps.i2c_speed_in_khz = 100;
+ 	dc->caps.max_cursor_size = 128;
+ 	dc->caps.dual_link_dvi = true;
+-
++	dc->caps.extended_aux_timeout_support = false;
+ 
+ 	/*************************************************
+ 	 *  Create resources                             *
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index 3aac593f9b2e..2dcc647ad27d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -443,7 +443,8 @@ struct dce_aux *dce120_aux_engine_create(
+ 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+ 				    &aux_engine_regs[inst],
+ 					&aux_mask,
+-					&aux_shift);
++					&aux_shift,
++					ctx->dc->caps.extended_aux_timeout_support);
+ 
+ 	return &aux_engine->base;
+ }
+@@ -1049,7 +1050,7 @@ static bool construct(
+ 	dc->caps.max_cursor_size = 128;
+ 	dc->caps.dual_link_dvi = true;
+ 	dc->caps.psp_setup_panel_mode = true;
+-
++	dc->caps.extended_aux_timeout_support = true;
+ 	dc->debug = debug_defaults;
+ 
+ 	/*************************************************
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+index 934d8deb95fc..6a9efa3bb93e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -530,7 +530,8 @@ struct dce_aux *dce80_aux_engine_create(
+ 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+ 				    &aux_engine_regs[inst],
+ 					&aux_mask,
+-					&aux_shift);
++					&aux_shift,
++					ctx->dc->caps.extended_aux_timeout_support);
+ 
+ 	return &aux_engine->base;
+ }
+@@ -938,6 +939,7 @@ static bool dce80_construct(
+ 	dc->caps.i2c_speed_in_khz = 40;
+ 	dc->caps.max_cursor_size = 128;
+ 	dc->caps.dual_link_dvi = true;
++	dc->caps.extended_aux_timeout_support = false;
+ 
+ 	/*************************************************
+ 	 *  Create resources                             *
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index 82dbc00afe54..a38c83c6aa5c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -672,7 +672,8 @@ struct dce_aux *dcn10_aux_engine_create(
+ 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+ 				    &aux_engine_regs[inst],
+ 					&aux_mask,
+-					&aux_shift);
++					&aux_shift,
++					ctx->dc->caps.extended_aux_timeout_support);
+ 
+ 	return &aux_engine->base;
+ }
+@@ -1342,6 +1343,8 @@ static bool construct(
+ 	dc->caps.max_slave_planes = 1;
+ 	dc->caps.is_apu = true;
+ 	dc->caps.post_blend_color_processing = false;
++	dc->caps.extended_aux_timeout_support = false;
++
+ 	/* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */
+ 	dc->caps.force_dp_tps4_for_cp2520 = true;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index f2db1fa2eba9..2796c84db740 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -960,7 +960,8 @@ struct dce_aux *dcn20_aux_engine_create(
+ 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+ 				    &aux_engine_regs[inst],
+ 					&aux_mask,
+-					&aux_shift);
++					&aux_shift,
++					ctx->dc->caps.extended_aux_timeout_support);
+ 
+ 	return &aux_engine->base;
+ }
+@@ -3372,6 +3373,7 @@ static bool construct(
+ 	dc->caps.post_blend_color_processing = true;
+ 	dc->caps.force_dp_tps4_for_cp2520 = true;
+ 	dc->caps.hw_3d_lut = true;
++	dc->caps.extended_aux_timeout_support = true;
+ 
+ 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
+ 		dc->debug = debug_defaults_drv;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index dc5d28d002df..86005cb05c2a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -695,7 +695,8 @@ static struct dce_aux *dcn21_aux_engine_create(
+ 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+ 				    &aux_engine_regs[inst],
+ 					&aux_mask,
+-					&aux_shift);
++					&aux_shift,
++					ctx->dc->caps.extended_aux_timeout_support);
+ 
+ 	return &aux_engine->base;
+ }
+@@ -1539,6 +1540,7 @@ static bool construct(
+ 	dc->caps.max_slave_planes = 1;
+ 	dc->caps.post_blend_color_processing = true;
+ 	dc->caps.force_dp_tps4_for_cp2520 = true;
++	dc->caps.extended_aux_timeout_support = true;
+ 
+ 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
+ 		dc->debug = debug_defaults_drv;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+index 7d35d03a2d43..14716ba35662 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+@@ -105,6 +105,9 @@ int dc_link_aux_transfer_raw(struct ddc_service *ddc,
+ bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc,
+ 		struct aux_payload *payload);
+ 
++enum dc_status dc_link_aux_configure_timeout(struct ddc_service *ddc,
++		uint32_t timeout);
++
+ void dal_ddc_service_write_scdc_data(
+ 		struct ddc_service *ddc_service,
+ 		uint32_t pix_clk,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+index 967706e7898e..045138dbdccb 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+@@ -28,6 +28,8 @@
+ 
+ #define LINK_TRAINING_ATTEMPTS 4
+ #define LINK_TRAINING_RETRY_DELAY 50 /* ms */
++#define LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD 32000 /*us*/
++#define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 400 /*us*/
+ 
+ struct dc_link;
+ struct dc_stream_state;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h b/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h
+index e79cd4e92919..e77b3a76766d 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h
+@@ -140,6 +140,9 @@ struct write_command_context {
+ 
+ 
+ struct aux_engine_funcs {
++	bool (*configure_timeout)(
++		struct ddc_service *ddc,
++		uint32_t timeout);
+ 	void (*destroy)(
+ 		struct aux_engine **ptr);
+ 	bool (*acquire_engine)(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4170-drm-amd-display-disable-ext-aux-support-for-vega.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4170-drm-amd-display-disable-ext-aux-support-for-vega.patch
new file mode 100644
index 00000000..51c374a0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4170-drm-amd-display-disable-ext-aux-support-for-vega.patch
@@ -0,0 +1,37 @@
+From 380cc83606e4cd2ca0b3b206955d7047d54ace0c Mon Sep 17 00:00:00 2001
+From: Roman Li <Roman.Li@amd.com>
+Date: Tue, 8 Oct 2019 17:35:48 -0400
+Subject: [PATCH 4170/4736] drm/amd/display: disable ext aux support for vega
+
+[Why]
+Earlier changes to support configurable aux timeout
+caused dc init failure on vega due to missing reg defs.
+Needs to be disabled until implemented for vega.
+
+[How]
+Set extended aux timeout cap for vega to false.
+
+fixes: drm/amd/display: configurable aux timeout support
+
+Signed-off-by: Roman Li <Roman.Li@amd.com>
+Reviewed-By: abdoulaye berthe <abdoulaye.berthe@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index 2dcc647ad27d..c982fd336cae 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -1050,7 +1050,7 @@ static bool construct(
+ 	dc->caps.max_cursor_size = 128;
+ 	dc->caps.dual_link_dvi = true;
+ 	dc->caps.psp_setup_panel_mode = true;
+-	dc->caps.extended_aux_timeout_support = true;
++	dc->caps.extended_aux_timeout_support = false;
+ 	dc->debug = debug_defaults;
+ 
+ 	/*************************************************
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4171-drm-amd-display-Add-DP_DPHY_INTERNAL_CTR-regs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4171-drm-amd-display-Add-DP_DPHY_INTERNAL_CTR-regs.patch
new file mode 100644
index 00000000..4b56b5b0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4171-drm-amd-display-Add-DP_DPHY_INTERNAL_CTR-regs.patch
@@ -0,0 +1,63 @@
+From 77b8a13374bac1feff732bbbce9233abd5f65aef Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 2 Oct 2019 11:50:15 -0400
+Subject: [PATCH 4171/4736] drm/amd/display: Add DP_DPHY_INTERNAL_CTR regs
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h    | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
+index be4249adb356..eddf83ec1c39 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
+@@ -9859,6 +9859,8 @@
+ #define mmDP0_DP_STEER_FIFO_BASE_IDX                                                                   2
+ #define mmDP0_DP_MSA_MISC                                                                              0x210e
+ #define mmDP0_DP_MSA_MISC_BASE_IDX                                                                     2
++#define mmDP0_DP_DPHY_INTERNAL_CTRL                                                                    0x210f
++#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+ #define mmDP0_DP_VID_TIMING                                                                            0x2110
+ #define mmDP0_DP_VID_TIMING_BASE_IDX                                                                   2
+ #define mmDP0_DP_VID_N                                                                                 0x2111
+@@ -10187,6 +10189,8 @@
+ #define mmDP1_DP_STEER_FIFO_BASE_IDX                                                                   2
+ #define mmDP1_DP_MSA_MISC                                                                              0x220e
+ #define mmDP1_DP_MSA_MISC_BASE_IDX                                                                     2
++#define mmDP1_DP_DPHY_INTERNAL_CTRL                                                                    0x220f
++#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+ #define mmDP1_DP_VID_TIMING                                                                            0x2210
+ #define mmDP1_DP_VID_TIMING_BASE_IDX                                                                   2
+ #define mmDP1_DP_VID_N                                                                                 0x2211
+@@ -10515,6 +10519,8 @@
+ #define mmDP2_DP_STEER_FIFO_BASE_IDX                                                                   2
+ #define mmDP2_DP_MSA_MISC                                                                              0x230e
+ #define mmDP2_DP_MSA_MISC_BASE_IDX                                                                     2
++#define mmDP2_DP_DPHY_INTERNAL_CTRL                                                                    0x230f
++#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+ #define mmDP2_DP_VID_TIMING                                                                            0x2310
+ #define mmDP2_DP_VID_TIMING_BASE_IDX                                                                   2
+ #define mmDP2_DP_VID_N                                                                                 0x2311
+@@ -10843,6 +10849,8 @@
+ #define mmDP3_DP_STEER_FIFO_BASE_IDX                                                                   2
+ #define mmDP3_DP_MSA_MISC                                                                              0x240e
+ #define mmDP3_DP_MSA_MISC_BASE_IDX                                                                     2
++#define mmDP3_DP_DPHY_INTERNAL_CTRL                                                                    0x240f
++#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+ #define mmDP3_DP_VID_TIMING                                                                            0x2410
+ #define mmDP3_DP_VID_TIMING_BASE_IDX                                                                   2
+ #define mmDP3_DP_VID_N                                                                                 0x2411
+@@ -11171,6 +11179,8 @@
+ #define mmDP4_DP_STEER_FIFO_BASE_IDX                                                                   2
+ #define mmDP4_DP_MSA_MISC                                                                              0x250e
+ #define mmDP4_DP_MSA_MISC_BASE_IDX                                                                     2
++#define mmDP4_DP_DPHY_INTERNAL_CTRL                                                                    0x250f
++#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+ #define mmDP4_DP_VID_TIMING                                                                            0x2510
+ #define mmDP4_DP_VID_TIMING_BASE_IDX                                                                   2
+ #define mmDP4_DP_VID_N                                                                                 0x2511
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4172-drm-amd-display-Add-DCN_BASE-regs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4172-drm-amd-display-Add-DCN_BASE-regs.patch
new file mode 100644
index 00000000..8374bd65
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4172-drm-amd-display-Add-DCN_BASE-regs.patch
@@ -0,0 +1,64 @@
+From 0fcb1884fb7b2db1e44bbdca280bce9284e3b902 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 2 Oct 2019 11:51:20 -0400
+Subject: [PATCH 4172/4736] drm/amd/display: Add DCN_BASE regs
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../gpu/drm/amd/include/renoir_ip_offset.h    | 34 +++++++++++++++++++
+ 1 file changed, 34 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/renoir_ip_offset.h b/drivers/gpu/drm/amd/include/renoir_ip_offset.h
+index 094648cac392..07633e22e99a 100644
+--- a/drivers/gpu/drm/amd/include/renoir_ip_offset.h
++++ b/drivers/gpu/drm/amd/include/renoir_ip_offset.h
+@@ -169,6 +169,11 @@ static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D
+                                         { { 0, 0, 0, 0, 0 } },
+                                         { { 0, 0, 0, 0, 0 } },
+                                         { { 0, 0, 0, 0, 0 } } } };
++static const struct IP_BASE DCN_BASE   ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } },
++                                        { { 0, 0, 0, 0, 0 } } } };
+ static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
+                                         { { 0, 0, 0, 0, 0 } },
+                                         { { 0, 0, 0, 0, 0 } },
+@@ -1361,4 +1366,33 @@ static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x0240300
+ #define UVD0_BASE__INST6_SEG3                      0
+ #define UVD0_BASE__INST6_SEG4                      0
+ 
++#define DCN_BASE__INST0_SEG0                      0x00000012
++#define DCN_BASE__INST0_SEG1                      0x000000C0
++#define DCN_BASE__INST0_SEG2                      0x000034C0
++#define DCN_BASE__INST0_SEG3                      0
++#define DCN_BASE__INST0_SEG4                      0
++
++#define DCN_BASE__INST1_SEG0                      0
++#define DCN_BASE__INST1_SEG1                      0
++#define DCN_BASE__INST1_SEG2                      0
++#define DCN_BASE__INST1_SEG3                      0
++#define DCN_BASE__INST1_SEG4                      0
++
++#define DCN_BASE__INST2_SEG0                      0
++#define DCN_BASE__INST2_SEG1                      0
++#define DCN_BASE__INST2_SEG2                      0
++#define DCN_BASE__INST2_SEG3                      0
++#define DCN_BASE__INST2_SEG4                      0
++
++#define DCN_BASE__INST3_SEG0                      0
++#define DCN_BASE__INST3_SEG1                      0
++#define DCN_BASE__INST3_SEG2                      0
++#define DCN_BASE__INST3_SEG3                      0
++#define DCN_BASE__INST3_SEG4                      0
++
++#define DCN_BASE__INST4_SEG0                      0
++#define DCN_BASE__INST4_SEG1                      0
++#define DCN_BASE__INST4_SEG2                      0
++#define DCN_BASE__INST4_SEG3                      0
++#define DCN_BASE__INST4_SEG4                      0
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4173-drm-amd-display-Add-renoir-hw_seq.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4173-drm-amd-display-Add-renoir-hw_seq.patch
new file mode 100644
index 00000000..8f133525
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4173-drm-amd-display-Add-renoir-hw_seq.patch
@@ -0,0 +1,449 @@
+From 8e48ee9e07fb0aa2b88f1e157660f182afafd7cc Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 2 Oct 2019 11:54:56 -0400
+Subject: [PATCH 4173/4736] drm/amd/display: Add renoir hw_seq
+
+This change adds renoir hw_seq, needed to do renoir
+specific hw programing
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dce/dce_hwseq.h    |   1 +
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   4 +
+ drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   2 +-
+ .../drm/amd/display/dc/dcn21/dcn21_hwseq.c    | 122 ++++++++++++++++++
+ .../drm/amd/display/dc/dcn21/dcn21_hwseq.h    |  33 +++++
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 118 +++++++++++++----
+ .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   3 +
+ 7 files changed, 255 insertions(+), 28 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+index ac04d77058f0..32d145a0d6fc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+@@ -679,6 +679,7 @@ struct dce_hwseq_registers {
+ 	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
+ 	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
+ 	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
++	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh), \
+ 	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
+ 	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 3b55716bf63b..7c02f646feed 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -669,6 +669,10 @@ static void dcn10_bios_golden_init(struct dc *dc)
+ 	int i;
+ 	bool allow_self_fresh_force_enable = true;
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	if (dc->hwss.s0i3_golden_init_wa && dc->hwss.s0i3_golden_init_wa(dc))
++		return;
++#endif
+ 	if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)
+ 		allow_self_fresh_force_enable =
+ 				dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+index b2b39090fb57..5b8f42ae2334 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+@@ -1,7 +1,7 @@
+ #
+ # Makefile for DCN21.
+ 
+-DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o
++DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o
+ 
+ CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+new file mode 100644
+index 000000000000..b25215cadf85
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+@@ -0,0 +1,122 @@
++/*
++ * Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "dm_services.h"
++#include "dm_helpers.h"
++#include "core_types.h"
++#include "resource.h"
++#include "dce/dce_hwseq.h"
++#include "dcn20/dcn20_hwseq.h"
++#include "vmid.h"
++#include "reg_helper.h"
++#include "hw/clk_mgr.h"
++
++
++#define DC_LOGGER_INIT(logger)
++
++#define CTX \
++	hws->ctx
++#define REG(reg)\
++	hws->regs->reg
++
++#undef FN
++#define FN(reg_name, field_name) \
++	hws->shifts->field_name, hws->masks->field_name
++
++/* Temporary read settings, future will get values from kmd directly */
++static void mmhub_update_page_table_config(struct dcn_hubbub_phys_addr_config *config,
++		struct dce_hwseq *hws)
++{
++	uint32_t page_table_base_hi;
++	uint32_t page_table_base_lo;
++
++	REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
++			PAGE_DIRECTORY_ENTRY_HI32, &page_table_base_hi);
++	REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
++			PAGE_DIRECTORY_ENTRY_LO32, &page_table_base_lo);
++
++	config->gart_config.page_table_base_addr = ((uint64_t)page_table_base_hi << 32) | page_table_base_lo;
++
++}
++
++static int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
++{
++	struct dcn_hubbub_phys_addr_config config;
++
++	config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
++	config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
++	config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
++	config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
++	config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
++	config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
++	config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
++	config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
++	config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
++
++	mmhub_update_page_table_config(&config, hws);
++
++	return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
++}
++
++// work around for Renoir s0i3, if register is programmed, bypass golden init.
++
++static bool dcn21_s0i3_golden_init_wa(struct dc *dc)
++{
++	struct dce_hwseq *hws = dc->hwseq;
++	uint32_t value = 0;
++
++	value = REG_READ(MICROSECOND_TIME_BASE_DIV);
++
++	return value != 0x00120464;
++}
++
++void dcn21_exit_optimized_pwr_state(
++		const struct dc *dc,
++		struct dc_state *context)
++{
++	dc->clk_mgr->funcs->update_clocks(
++			dc->clk_mgr,
++			context,
++			false);
++}
++
++void dcn21_optimize_pwr_state(
++		const struct dc *dc,
++		struct dc_state *context)
++{
++	dc->clk_mgr->funcs->update_clocks(
++			dc->clk_mgr,
++			context,
++			true);
++}
++
++void dcn21_hw_sequencer_construct(struct dc *dc)
++{
++	dcn20_hw_sequencer_construct(dc);
++	dc->hwss.init_sys_ctx = dcn21_init_sys_ctx;
++	dc->hwss.s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa;
++	dc->hwss.optimize_pwr_state = dcn21_optimize_pwr_state;
++	dc->hwss.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state;
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
+new file mode 100644
+index 000000000000..be67b62e6fb1
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
+@@ -0,0 +1,33 @@
++/*
++* Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DC_HWSS_DCN21_H__
++#define __DC_HWSS_DCN21_H__
++
++struct dc;
++
++void dcn21_hw_sequencer_construct(struct dc *dc);
++
++#endif /* __DC_HWSS_DCN21_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 86005cb05c2a..1bac7eca5963 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -23,8 +23,6 @@
+  *
+  */
+ 
+-#include <linux/slab.h>
+-
+ #include "dm_services.h"
+ #include "dc.h"
+ 
+@@ -42,7 +40,7 @@
+ #include "irq/dcn21/irq_service_dcn21.h"
+ #include "dcn20/dcn20_dpp.h"
+ #include "dcn20/dcn20_optc.h"
+-#include "dcn20/dcn20_hwseq.h"
++#include "dcn21/dcn21_hwseq.h"
+ #include "dce110/dce110_hw_sequencer.h"
+ #include "dcn20/dcn20_opp.h"
+ #include "dcn20/dcn20_dsc.h"
+@@ -350,6 +348,30 @@ static const struct bios_registers bios_regs = {
+ 		NBIO_SR(BIOS_SCRATCH_6)
+ };
+ 
++static const struct dce_dmcu_registers dmcu_regs = {
++		DMCU_DCN10_REG_LIST()
++};
++
++static const struct dce_dmcu_shift dmcu_shift = {
++		DMCU_MASK_SH_LIST_DCN10(__SHIFT)
++};
++
++static const struct dce_dmcu_mask dmcu_mask = {
++		DMCU_MASK_SH_LIST_DCN10(_MASK)
++};
++
++static const struct dce_abm_registers abm_regs = {
++		ABM_DCN20_REG_LIST()
++};
++
++static const struct dce_abm_shift abm_shift = {
++		ABM_MASK_SH_LIST_DCN20(__SHIFT)
++};
++
++static const struct dce_abm_mask abm_mask = {
++		ABM_MASK_SH_LIST_DCN20(_MASK)
++};
++
+ #ifdef CONFIG_DRM_AMD_DC_DMUB
+ static const struct dcn21_dmcub_registers dmcub_regs = {
+ 		DMCUB_REG_LIST_DCN()
+@@ -1491,6 +1513,19 @@ static struct link_encoder *dcn21_link_encoder_create(
+         return &enc21->enc10.base;
+ }
+ 
++#define CTX ctx
++
++#define REG(reg_name) \
++	(DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
++
++static uint32_t read_pipe_fuses(struct dc_context *ctx)
++{
++	uint32_t value = REG_READ(CC_DC_PIPE_DIS);
++	/* RV1 support max 4 pipes */
++	value = value & 0xf;
++	return value;
++}
++
+ static struct resource_funcs dcn21_res_pool_funcs = {
+ 	.destroy = dcn21_destroy_resource_pool,
+ 	.link_enc_create = dcn20_link_encoder_create,
+@@ -1510,9 +1545,10 @@ static bool construct(
+ 	struct dc *dc,
+ 	struct dcn21_resource_pool *pool)
+ {
+-	int i;
++	int i, j;
+ 	struct dc_context *ctx = dc->ctx;
+ 	struct irq_service_init_data init_data;
++	uint32_t pipe_fuses = read_pipe_fuses(ctx);
+ 
+ 	ctx->dc_bios->regs = &bios_regs;
+ 
+@@ -1530,7 +1566,9 @@ static bool construct(
+ 	 *************************************************/
+ 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+ 
+-	pool->base.pipe_count = 4;
++	/* max pipe num for ASIC before check pipe fuses */
++	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
++
+ 	dc->caps.max_downscale_ratio = 200;
+ 	dc->caps.i2c_speed_in_khz = 100;
+ 	dc->caps.max_cursor_size = 256;
+@@ -1590,6 +1628,26 @@ static bool construct(
+ 		goto create_fail;
+ 	}
+ 
++	pool->base.dmcu = dcn20_dmcu_create(ctx,
++			&dmcu_regs,
++			&dmcu_shift,
++			&dmcu_mask);
++	if (pool->base.dmcu == NULL) {
++		dm_error("DC: failed to create dmcu!\n");
++		BREAK_TO_DEBUGGER();
++		goto create_fail;
++	}
++
++	pool->base.abm = dce_abm_create(ctx,
++			&abm_regs,
++			&abm_shift,
++			&abm_mask);
++	if (pool->base.abm == NULL) {
++		dm_error("DC: failed to create abm!\n");
++		BREAK_TO_DEBUGGER();
++		goto create_fail;
++	}
++
+ #ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	pool->base.dmcub = dcn21_dmcub_create(ctx,
+ 			&dmcub_regs,
+@@ -1611,8 +1669,15 @@ static bool construct(
+ 	if (!pool->base.irqs)
+ 		goto create_fail;
+ 
++	j = 0;
+ 	/* mem input -> ipp -> dpp -> opp -> TG */
+ 	for (i = 0; i < pool->base.pipe_count; i++) {
++		/* if pipe is disabled, skip instance of HW pipe,
++		 * i.e, skip ASIC register instance
++		 */
++		if ((pipe_fuses & (1 << i)) != 0)
++			continue;
++
+ 		pool->base.hubps[i] = dcn21_hubp_create(ctx, i);
+ 		if (pool->base.hubps[i] == NULL) {
+ 			BREAK_TO_DEBUGGER();
+@@ -1636,6 +1701,23 @@ static bool construct(
+ 				"DC: failed to create dpps!\n");
+ 			goto create_fail;
+ 		}
++
++		pool->base.opps[i] = dcn21_opp_create(ctx, i);
++		if (pool->base.opps[i] == NULL) {
++			BREAK_TO_DEBUGGER();
++			dm_error(
++				"DC: failed to create output pixel processor!\n");
++			goto create_fail;
++		}
++
++		pool->base.timing_generators[i] = dcn21_timing_generator_create(
++				ctx, i);
++		if (pool->base.timing_generators[i] == NULL) {
++			BREAK_TO_DEBUGGER();
++			dm_error("DC: failed to create tg!\n");
++			goto create_fail;
++		}
++		j++;
+ 	}
+ 
+ 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+@@ -1656,27 +1738,9 @@ static bool construct(
+ 		pool->base.sw_i2cs[i] = NULL;
+ 	}
+ 
+-	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+-		pool->base.opps[i] = dcn21_opp_create(ctx, i);
+-		if (pool->base.opps[i] == NULL) {
+-			BREAK_TO_DEBUGGER();
+-			dm_error(
+-				"DC: failed to create output pixel processor!\n");
+-			goto create_fail;
+-		}
+-	}
+-
+-	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+-		pool->base.timing_generators[i] = dcn21_timing_generator_create(
+-				ctx, i);
+-		if (pool->base.timing_generators[i] == NULL) {
+-			BREAK_TO_DEBUGGER();
+-			dm_error("DC: failed to create tg!\n");
+-			goto create_fail;
+-		}
+-	}
+-
+-	pool->base.timing_generator_count = i;
++	pool->base.timing_generator_count = j;
++	pool->base.pipe_count = j;
++	pool->base.mpcc_count = j;
+ 
+ 	pool->base.mpc = dcn21_mpc_create(ctx);
+ 	if (pool->base.mpc == NULL) {
+@@ -1719,7 +1783,7 @@ static bool construct(
+ 			&res_create_funcs : &res_create_maximus_funcs)))
+ 			goto create_fail;
+ 
+-	dcn20_hw_sequencer_construct(dc);
++	dcn21_hw_sequencer_construct(dc);
+ 
+ 	dc->caps.max_planes =  pool->base.pipe_count;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index e775d7aa062f..d39c1e11def5 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -349,6 +349,9 @@ struct hw_sequencer_funcs {
+ 			enum dc_clock_type clock_type,
+ 			struct dc_clock_config *clock_cfg);
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	bool (*s0i3_golden_init_wa)(struct dc *dc);
++#endif
+ };
+ 
+ void color_space_to_black_color(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4174-drm-amd-display-create-dcn21_link_encoder-files.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4174-drm-amd-display-create-dcn21_link_encoder-files.patch
new file mode 100644
index 00000000..69b71fce
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4174-drm-amd-display-create-dcn21_link_encoder-files.patch
@@ -0,0 +1,668 @@
+From eedab588549241d11646033a4667dd8851e5a97f Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 2 Oct 2019 11:55:12 -0400
+Subject: [PATCH 4174/4736] drm/amd/display: create dcn21_link_encoder files
+
+[Why]
+DCN20 and DCN21 have different phy programming sequences.
+
+[How]
+Create a separate dcn21_link_encoder for Renoir
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../amd/display/dc/dcn10/dcn10_link_encoder.h |  35 +-
+ .../amd/display/dc/dcn20/dcn20_link_encoder.h |   7 +
+ drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   2 +-
+ .../amd/display/dc/dcn21/dcn21_link_encoder.c | 379 ++++++++++++++++++
+ .../amd/display/dc/dcn21/dcn21_link_encoder.h |  51 +++
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c |  85 +++-
+ 6 files changed, 555 insertions(+), 4 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+index 0c12395cfa36..239a6c90ffb9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+@@ -250,6 +250,10 @@ struct dcn10_link_enc_registers {
+ 		type RDPCS_EXT_REFCLK_EN;\
+ 		type RDPCS_TX_FIFO_EN;\
+ 		type UNIPHY_LINK_ENABLE;\
++		type UNIPHY_CHANNEL0_XBAR_SOURCE;\
++		type UNIPHY_CHANNEL1_XBAR_SOURCE;\
++		type UNIPHY_CHANNEL2_XBAR_SOURCE;\
++		type UNIPHY_CHANNEL3_XBAR_SOURCE;\
+ 		type UNIPHY_CHANNEL0_INVERT;\
+ 		type UNIPHY_CHANNEL1_INVERT;\
+ 		type UNIPHY_CHANNEL2_INVERT;\
+@@ -342,12 +346,41 @@ struct dcn10_link_enc_registers {
+ 		type RDPCS_PHY_DPALT_DISABLE_ACK;\
+ 		type RDPCS_PHY_DP_MPLLB_V2I;\
+ 		type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\
++		type RDPCS_PHY_DP_MPLLB_CP_INT_GS;\
++		type RDPCS_PHY_RX_VREF_CTRL;\
+ 		type RDPCS_PHY_DP_MPLLB_CP_INT;\
+ 		type RDPCS_PHY_DP_MPLLB_CP_PROP;\
+ 		type RDPCS_PHY_RX_REF_LD_VAL;\
+ 		type RDPCS_PHY_RX_VCO_LD_VAL;\
+ 		type DPCSTX_DEBUG_CONFIG; \
+-		type RDPCSTX_DEBUG_CONFIG
++		type RDPCSTX_DEBUG_CONFIG; \
++		type RDPCS_PHY_DP_TX0_EQ_MAIN;\
++		type RDPCS_PHY_DP_TX0_EQ_PRE;\
++		type RDPCS_PHY_DP_TX0_EQ_POST;\
++		type RDPCS_PHY_DP_TX1_EQ_MAIN;\
++		type RDPCS_PHY_DP_TX1_EQ_PRE;\
++		type RDPCS_PHY_DP_TX1_EQ_POST;\
++		type RDPCS_PHY_DP_TX2_EQ_MAIN;\
++		type RDPCS_PHY_DP_MPLLB_CP_PROP_GS;\
++		type RDPCS_PHY_DP_TX2_EQ_PRE;\
++		type RDPCS_PHY_DP_TX2_EQ_POST;\
++		type RDPCS_PHY_DP_TX3_EQ_MAIN;\
++		type RDPCS_PHY_DCO_RANGE;\
++		type RDPCS_PHY_DCO_FINETUNE;\
++		type RDPCS_PHY_DP_TX3_EQ_PRE;\
++		type RDPCS_PHY_DP_TX3_EQ_POST;\
++		type RDPCS_PHY_SUP_PRE_HP;\
++		type RDPCS_PHY_DP_TX0_VREGDRV_BYP;\
++		type RDPCS_PHY_DP_TX1_VREGDRV_BYP;\
++		type RDPCS_PHY_DP_TX2_VREGDRV_BYP;\
++		type RDPCS_PHY_DP_TX3_VREGDRV_BYP;\
++		type RDPCS_DMCU_DPALT_DIS_BLOCK_REG;\
++		type UNIPHYA_SOFT_RESET;\
++		type UNIPHYB_SOFT_RESET;\
++		type UNIPHYC_SOFT_RESET;\
++		type UNIPHYD_SOFT_RESET;\
++		type UNIPHYE_SOFT_RESET;\
++		type UNIPHYF_SOFT_RESET
+ 
+ #define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \
+ 	type DIG_LANE0EN;\
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
+index 3736b5548a25..0c98a0bbbd14 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
+@@ -91,6 +91,13 @@ struct mpll_cfg {
+ 	uint32_t ref_range;
+ 	uint32_t ref_clk;
+ 	bool hdmimode_enable;
++	bool sup_pre_hp;
++	bool dp_tx0_vergdrv_byp;
++	bool dp_tx1_vergdrv_byp;
++	bool dp_tx2_vergdrv_byp;
++	bool dp_tx3_vergdrv_byp;
++
++
+ };
+ 
+ struct dpcssys_phy_seq_cfg {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+index 5b8f42ae2334..b7a9285348fb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+@@ -1,7 +1,7 @@
+ #
+ # Makefile for DCN21.
+ 
+-DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o
++DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o dcn21_link_encoder.o
+ 
+ CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+new file mode 100644
+index 000000000000..526865c43b48
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+@@ -0,0 +1,379 @@
++/*
++ * Copyright 2012-15 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "reg_helper.h"
++
++#include <linux/delay.h>
++#include "core_types.h"
++#include "link_encoder.h"
++#include "dcn21_link_encoder.h"
++#include "stream_encoder.h"
++
++#include "i2caux_interface.h"
++#include "dc_bios_types.h"
++
++#include "gpio_service_interface.h"
++
++#define CTX \
++	enc10->base.ctx
++#define DC_LOGGER \
++	enc10->base.ctx->logger
++
++#define REG(reg)\
++	(enc10->link_regs->reg)
++
++#undef FN
++#define FN(reg_name, field_name) \
++	enc10->link_shift->field_name, enc10->link_mask->field_name
++
++#define IND_REG(index) \
++	(enc10->link_regs->index)
++
++static struct mpll_cfg dcn21_mpll_cfg_ref[] = {
++	// RBR
++	{
++		.hdmimode_enable = 0,
++		.ref_range = 1,
++		.ref_clk_mpllb_div = 1,
++		.mpllb_ssc_en = 1,
++		.mpllb_div5_clk_en = 1,
++		.mpllb_multiplier = 238,
++		.mpllb_fracn_en = 0,
++		.mpllb_fracn_quot = 0,
++		.mpllb_fracn_rem = 0,
++		.mpllb_fracn_den = 1,
++		.mpllb_ssc_up_spread = 0,
++		.mpllb_ssc_peak = 44237,
++		.mpllb_ssc_stepsize = 59454,
++		.mpllb_div_clk_en = 0,
++		.mpllb_div_multiplier = 0,
++		.mpllb_hdmi_div = 0,
++		.mpllb_tx_clk_div = 2,
++		.tx_vboost_lvl = 5,
++		.mpllb_pmix_en = 1,
++		.mpllb_word_div2_en = 0,
++		.mpllb_ana_v2i = 2,
++		.mpllb_ana_freq_vco = 2,
++		.mpllb_ana_cp_int = 9,
++		.mpllb_ana_cp_prop = 15,
++		.hdmi_pixel_clk_div = 0,
++	},
++	// HBR
++	{
++		.hdmimode_enable = 0,
++		.ref_range = 1,
++		.ref_clk_mpllb_div = 1,
++		.mpllb_ssc_en = 1,
++		.mpllb_div5_clk_en = 1,
++		.mpllb_multiplier = 192,
++		.mpllb_fracn_en = 1,
++		.mpllb_fracn_quot = 32768,
++		.mpllb_fracn_rem = 0,
++		.mpllb_fracn_den = 1,
++		.mpllb_ssc_up_spread = 0,
++		.mpllb_ssc_peak = 36864,
++		.mpllb_ssc_stepsize = 49545,
++		.mpllb_div_clk_en = 0,
++		.mpllb_div_multiplier = 0,
++		.mpllb_hdmi_div = 0,
++		.mpllb_tx_clk_div = 1,
++		.tx_vboost_lvl = 5,
++		.mpllb_pmix_en = 1,
++		.mpllb_word_div2_en = 0,
++		.mpllb_ana_v2i = 2,
++		.mpllb_ana_freq_vco = 3,
++		.mpllb_ana_cp_int = 9,
++		.mpllb_ana_cp_prop = 15,
++		.hdmi_pixel_clk_div = 0,
++	},
++	//HBR2
++	{
++		.hdmimode_enable = 0,
++		.ref_range = 1,
++		.ref_clk_mpllb_div = 1,
++		.mpllb_ssc_en = 1,
++		.mpllb_div5_clk_en = 1,
++		.mpllb_multiplier = 192,
++		.mpllb_fracn_en = 1,
++		.mpllb_fracn_quot = 32768,
++		.mpllb_fracn_rem = 0,
++		.mpllb_fracn_den = 1,
++		.mpllb_ssc_up_spread = 0,
++		.mpllb_ssc_peak = 36864,
++		.mpllb_ssc_stepsize = 49545,
++		.mpllb_div_clk_en = 0,
++		.mpllb_div_multiplier = 0,
++		.mpllb_hdmi_div = 0,
++		.mpllb_tx_clk_div = 0,
++		.tx_vboost_lvl = 5,
++		.mpllb_pmix_en = 1,
++		.mpllb_word_div2_en = 0,
++		.mpllb_ana_v2i = 2,
++		.mpllb_ana_freq_vco = 3,
++		.mpllb_ana_cp_int = 9,
++		.mpllb_ana_cp_prop = 15,
++		.hdmi_pixel_clk_div = 0,
++	},
++	//HBR3
++	{
++		.hdmimode_enable = 0,
++		.ref_range = 1,
++		.ref_clk_mpllb_div = 1,
++		.mpllb_ssc_en = 1,
++		.mpllb_div5_clk_en = 1,
++		.mpllb_multiplier = 304,
++		.mpllb_fracn_en = 1,
++		.mpllb_fracn_quot = 49152,
++		.mpllb_fracn_rem = 0,
++		.mpllb_fracn_den = 1,
++		.mpllb_ssc_up_spread = 0,
++		.mpllb_ssc_peak = 55296,
++		.mpllb_ssc_stepsize = 74318,
++		.mpllb_div_clk_en = 0,
++		.mpllb_div_multiplier = 0,
++		.mpllb_hdmi_div = 0,
++		.mpllb_tx_clk_div = 0,
++		.tx_vboost_lvl = 5,
++		.mpllb_pmix_en = 1,
++		.mpllb_word_div2_en = 0,
++		.mpllb_ana_v2i = 2,
++		.mpllb_ana_freq_vco = 1,
++		.mpllb_ana_cp_int = 7,
++		.mpllb_ana_cp_prop = 16,
++		.hdmi_pixel_clk_div = 0,
++	},
++};
++
++
++static bool update_cfg_data(
++		struct dcn10_link_encoder *enc10,
++		const struct dc_link_settings *link_settings,
++		struct dpcssys_phy_seq_cfg *cfg)
++{
++	int i;
++
++	cfg->load_sram_fw = false;
++	cfg->use_calibration_setting = true;
++
++	//TODO: need to implement a proper lane mapping for Renoir.
++	for (i = 0; i < 4; i++)
++		cfg->lane_en[i] = true;
++
++	switch (link_settings->link_rate) {
++	case LINK_RATE_LOW:
++		cfg->mpll_cfg = dcn21_mpll_cfg_ref[0];
++		break;
++	case LINK_RATE_HIGH:
++		cfg->mpll_cfg = dcn21_mpll_cfg_ref[1];
++		break;
++	case LINK_RATE_HIGH2:
++		cfg->mpll_cfg = dcn21_mpll_cfg_ref[2];
++		break;
++	case LINK_RATE_HIGH3:
++		cfg->mpll_cfg = dcn21_mpll_cfg_ref[3];
++		break;
++	default:
++		DC_LOG_ERROR("%s: No supported link rate found %X!\n",
++				__func__, link_settings->link_rate);
++		return false;
++	}
++
++	return true;
++}
++
++void dcn21_link_encoder_enable_dp_output(
++	struct link_encoder *enc,
++	const struct dc_link_settings *link_settings,
++	enum clock_source_id clock_source)
++{
++	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
++	struct dcn21_link_encoder *enc21 = (struct dcn21_link_encoder *) enc10;
++	struct dpcssys_phy_seq_cfg *cfg = &enc21->phy_seq_cfg;
++
++	if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
++		dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source);
++		return;
++	}
++
++	if (!update_cfg_data(enc10, link_settings, cfg))
++		return;
++
++	enc1_configure_encoder(enc10, link_settings);
++
++	dcn10_link_encoder_setup(enc, SIGNAL_TYPE_DISPLAY_PORT);
++
++}
++
++void dcn21_link_encoder_disable_output(
++	struct link_encoder *enc,
++	enum signal_type signal)
++{
++	dcn10_link_encoder_disable_output(enc, signal);
++
++}
++static const struct link_encoder_funcs dcn21_link_enc_funcs = {
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	.read_state = link_enc2_read_state,
++#endif
++	.validate_output_with_stream =
++		dcn10_link_encoder_validate_output_with_stream,
++	.hw_init = enc2_hw_init,
++	.setup = dcn10_link_encoder_setup,
++	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
++	.enable_dp_output = dcn21_link_encoder_enable_dp_output,
++	.enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
++	.disable_output = dcn21_link_encoder_disable_output,
++	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
++	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
++	.update_mst_stream_allocation_table =
++		dcn10_link_encoder_update_mst_stream_allocation_table,
++	.psr_program_dp_dphy_fast_training =
++			dcn10_psr_program_dp_dphy_fast_training,
++	.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
++	.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
++	.enable_hpd = dcn10_link_encoder_enable_hpd,
++	.disable_hpd = dcn10_link_encoder_disable_hpd,
++	.is_dig_enabled = dcn10_is_dig_enabled,
++	.destroy = dcn10_link_encoder_destroy,
++	.fec_set_enable = enc2_fec_set_enable,
++	.fec_set_ready = enc2_fec_set_ready,
++	.fec_is_active = enc2_fec_is_active,
++	.get_dig_frontend = dcn10_get_dig_frontend,
++};
++
++void dcn21_link_encoder_construct(
++	struct dcn21_link_encoder *enc21,
++	const struct encoder_init_data *init_data,
++	const struct encoder_feature_support *enc_features,
++	const struct dcn10_link_enc_registers *link_regs,
++	const struct dcn10_link_enc_aux_registers *aux_regs,
++	const struct dcn10_link_enc_hpd_registers *hpd_regs,
++	const struct dcn10_link_enc_shift *link_shift,
++	const struct dcn10_link_enc_mask *link_mask)
++{
++	struct bp_encoder_cap_info bp_cap_info = {0};
++	const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
++	enum bp_result result = BP_RESULT_OK;
++	struct dcn10_link_encoder *enc10 = &enc21->enc10;
++
++	enc10->base.funcs = &dcn21_link_enc_funcs;
++	enc10->base.ctx = init_data->ctx;
++	enc10->base.id = init_data->encoder;
++
++	enc10->base.hpd_source = init_data->hpd_source;
++	enc10->base.connector = init_data->connector;
++
++	enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
++
++	enc10->base.features = *enc_features;
++
++	enc10->base.transmitter = init_data->transmitter;
++
++	/* set the flag to indicate whether driver poll the I2C data pin
++	 * while doing the DP sink detect
++	 */
++
++/*	if (dal_adapter_service_is_feature_supported(as,
++		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
++		enc10->base.features.flags.bits.
++			DP_SINK_DETECT_POLL_DATA_PIN = true;*/
++
++	enc10->base.output_signals =
++		SIGNAL_TYPE_DVI_SINGLE_LINK |
++		SIGNAL_TYPE_DVI_DUAL_LINK |
++		SIGNAL_TYPE_LVDS |
++		SIGNAL_TYPE_DISPLAY_PORT |
++		SIGNAL_TYPE_DISPLAY_PORT_MST |
++		SIGNAL_TYPE_EDP |
++		SIGNAL_TYPE_HDMI_TYPE_A;
++
++	/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
++	 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
++	 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
++	 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
++	 * Prefer DIG assignment is decided by board design.
++	 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
++	 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
++	 * By this, adding DIGG should not hurt DCE 8.0.
++	 * This will let DCE 8.1 share DCE 8.0 as much as possible
++	 */
++
++	enc10->link_regs = link_regs;
++	enc10->aux_regs = aux_regs;
++	enc10->hpd_regs = hpd_regs;
++	enc10->link_shift = link_shift;
++	enc10->link_mask = link_mask;
++
++	switch (enc10->base.transmitter) {
++	case TRANSMITTER_UNIPHY_A:
++		enc10->base.preferred_engine = ENGINE_ID_DIGA;
++	break;
++	case TRANSMITTER_UNIPHY_B:
++		enc10->base.preferred_engine = ENGINE_ID_DIGB;
++	break;
++	case TRANSMITTER_UNIPHY_C:
++		enc10->base.preferred_engine = ENGINE_ID_DIGC;
++	break;
++	case TRANSMITTER_UNIPHY_D:
++		enc10->base.preferred_engine = ENGINE_ID_DIGD;
++	break;
++	case TRANSMITTER_UNIPHY_E:
++		enc10->base.preferred_engine = ENGINE_ID_DIGE;
++	break;
++	case TRANSMITTER_UNIPHY_F:
++		enc10->base.preferred_engine = ENGINE_ID_DIGF;
++	break;
++	case TRANSMITTER_UNIPHY_G:
++		enc10->base.preferred_engine = ENGINE_ID_DIGG;
++	break;
++	default:
++		ASSERT_CRITICAL(false);
++		enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
++	}
++
++	/* default to one to mirror Windows behavior */
++	enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
++
++	result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
++						enc10->base.id, &bp_cap_info);
++
++	/* Override features with DCE-specific values */
++	if (result == BP_RESULT_OK) {
++		enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
++				bp_cap_info.DP_HBR2_EN;
++		enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
++				bp_cap_info.DP_HBR3_EN;
++		enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
++		enc10->base.features.flags.bits.DP_IS_USB_C =
++				bp_cap_info.DP_IS_USB_C;
++	} else {
++		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
++				__func__,
++				result);
++	}
++	if (enc10->base.ctx->dc->debug.hdmi20_disable) {
++		enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
++	}
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
+new file mode 100644
+index 000000000000..438321e547db
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
+@@ -0,0 +1,51 @@
++/*
++ * Copyright 2012-15 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ *  and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DC_LINK_ENCODER__DCN21_H__
++#define __DC_LINK_ENCODER__DCN21_H__
++
++#include "dcn20/dcn20_link_encoder.h"
++
++struct dcn21_link_encoder {
++	struct dcn10_link_encoder enc10;
++	struct dpcssys_phy_seq_cfg phy_seq_cfg;
++};
++
++void dcn21_link_encoder_enable_dp_output(
++	struct link_encoder *enc,
++	const struct dc_link_settings *link_settings,
++	enum clock_source_id clock_source);
++
++void dcn21_link_encoder_construct(
++	struct dcn21_link_encoder *enc21,
++	const struct encoder_init_data *init_data,
++	const struct encoder_feature_support *enc_features,
++	const struct dcn10_link_enc_registers *link_regs,
++	const struct dcn10_link_enc_aux_registers *aux_regs,
++	const struct dcn10_link_enc_hpd_registers *hpd_regs,
++	const struct dcn10_link_enc_shift *link_shift,
++	const struct dcn10_link_enc_mask *link_mask);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 1bac7eca5963..085e6d38c45e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -44,7 +44,7 @@
+ #include "dce110/dce110_hw_sequencer.h"
+ #include "dcn20/dcn20_opp.h"
+ #include "dcn20/dcn20_dsc.h"
+-#include "dcn20/dcn20_link_encoder.h"
++#include "dcn21/dcn21_link_encoder.h"
+ #include "dcn20/dcn20_stream_encoder.h"
+ #include "dce/dce_clock_source.h"
+ #include "dce/dce_audio.h"
+@@ -1513,6 +1513,87 @@ static struct link_encoder *dcn21_link_encoder_create(
+         return &enc21->enc10.base;
+ }
+ 
++static const struct encoder_feature_support link_enc_feature = {
++		.max_hdmi_deep_color = COLOR_DEPTH_121212,
++		.max_hdmi_pixel_clock = 600000,
++		.hdmi_ycbcr420_supported = true,
++		.dp_ycbcr420_supported = true,
++		.flags.bits.IS_HBR2_CAPABLE = true,
++		.flags.bits.IS_HBR3_CAPABLE = true,
++		.flags.bits.IS_TPS3_CAPABLE = true,
++		.flags.bits.IS_TPS4_CAPABLE = true
++};
++
++
++#define link_regs(id, phyid)\
++[id] = {\
++	LE_DCN10_REG_LIST(id), \
++	UNIPHY_DCN2_REG_LIST(phyid), \
++	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
++}
++
++static const struct dcn10_link_enc_registers link_enc_regs[] = {
++	link_regs(0, A),
++	link_regs(1, B),
++	link_regs(2, C),
++	link_regs(3, D),
++	link_regs(4, E),
++};
++
++#define aux_regs(id)\
++[id] = {\
++	DCN2_AUX_REG_LIST(id)\
++}
++
++static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
++		aux_regs(0),
++		aux_regs(1),
++		aux_regs(2),
++		aux_regs(3),
++		aux_regs(4)
++};
++
++#define hpd_regs(id)\
++[id] = {\
++	HPD_REG_LIST(id)\
++}
++
++static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
++		hpd_regs(0),
++		hpd_regs(1),
++		hpd_regs(2),
++		hpd_regs(3),
++		hpd_regs(4)
++};
++
++static const struct dcn10_link_enc_shift le_shift = {
++	LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT)
++};
++
++static const struct dcn10_link_enc_mask le_mask = {
++	LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK)
++};
++
++static struct link_encoder *dcn21_link_encoder_create(
++	const struct encoder_init_data *enc_init_data)
++{
++	struct dcn21_link_encoder *enc21 =
++		kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
++
++	if (!enc21)
++		return NULL;
++
++	dcn21_link_encoder_construct(enc21,
++				      enc_init_data,
++				      &link_enc_feature,
++				      &link_enc_regs[enc_init_data->transmitter],
++				      &link_enc_aux_regs[enc_init_data->channel - 1],
++				      &link_enc_hpd_regs[enc_init_data->hpd_source],
++				      &le_shift,
++				      &le_mask);
++
++	return &enc21->enc10.base;
++}
+ #define CTX ctx
+ 
+ #define REG(reg_name) \
+@@ -1528,7 +1609,7 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx)
+ 
+ static struct resource_funcs dcn21_res_pool_funcs = {
+ 	.destroy = dcn21_destroy_resource_pool,
+-	.link_enc_create = dcn20_link_encoder_create,
++	.link_enc_create = dcn21_link_encoder_create,
+ 	.validate_bandwidth = dcn21_validate_bandwidth,
+ 	.add_stream_to_ctx = dcn20_add_stream_to_ctx,
+ 	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4175-drm-amd-display-add-REFCYC_PER_TRIP_TO_MEMORY-progra.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4175-drm-amd-display-add-REFCYC_PER_TRIP_TO_MEMORY-progra.patch
new file mode 100644
index 00000000..43cf27f7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4175-drm-amd-display-add-REFCYC_PER_TRIP_TO_MEMORY-progra.patch
@@ -0,0 +1,207 @@
+From fbcf6e7ad774bd6a1f3895a9eae0c4e6150f28a2 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 2 Oct 2019 14:04:54 -0400
+Subject: [PATCH 4175/4736] drm/amd/display: add REFCYC_PER_TRIP_TO_MEMORY
+ programming
+
+it allows us to do urgent latency programming
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 16 ++++++++
+ .../drm/amd/display/dc/dcn21/dcn21_hubbub.c   | 39 +++++++++++++++++--
+ .../drm/amd/display/dc/dcn21/dcn21_hubbub.h   | 17 ++++++++
+ .../gpu/drm/amd/display/dc/inc/hw/mem_input.h |  1 +
+ 4 files changed, 69 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 2796c84db740..58678b679661 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2606,6 +2606,10 @@ void dcn20_calculate_wm(
+ 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ 	context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++#endif
+ 
+ 	if (vlevel < 2) {
+ 		pipes[0].clks_cfg.voltage = 2;
+@@ -2617,6 +2621,10 @@ void dcn20_calculate_wm(
+ 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ 	context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++#endif
+ 
+ 	if (vlevel < 3) {
+ 		pipes[0].clks_cfg.voltage = 3;
+@@ -2628,6 +2636,10 @@ void dcn20_calculate_wm(
+ 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ 	context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++#endif
+ 
+ 	pipes[0].clks_cfg.voltage = vlevel;
+ 	pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
+@@ -2637,6 +2649,10 @@ void dcn20_calculate_wm(
+ 	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ 	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ 	context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++	context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++#endif
+ }
+ 
+ void dcn20_calculate_dlg_params(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+index d1266741763b..8e7e79f44272 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+@@ -97,7 +97,7 @@ void dcn21_dchvm_init(struct hubbub *hubbub)
+ 	REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);
+ }
+ 
+-static int hubbub21_init_dchub(struct hubbub *hubbub,
++int hubbub21_init_dchub(struct hubbub *hubbub,
+ 		struct dcn_hubbub_phys_addr_config *pa_config)
+ {
+ 	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
+@@ -120,7 +120,7 @@ static int hubbub21_init_dchub(struct hubbub *hubbub,
+ 	return NUM_VMID;
+ }
+ 
+-static void hubbub21_program_urgent_watermarks(
++void hubbub21_program_urgent_watermarks(
+ 		struct hubbub *hubbub,
+ 		struct dcn_watermark_set *watermarks,
+ 		unsigned int refclk_mhz,
+@@ -160,6 +160,13 @@ static void hubbub21_program_urgent_watermarks(
+ 		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,
+ 				DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, watermarks->a.frac_urg_bw_nom);
+ 	}
++	if (safe_to_lower || watermarks->a.urgent_latency_ns > hubbub1->watermarks.a.urgent_latency_ns) {
++		hubbub1->watermarks.a.urgent_latency_ns = watermarks->a.urgent_latency_ns;
++		prog_wm_value = convert_and_clamp(watermarks->a.urgent_latency_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0,
++				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, prog_wm_value);
++	}
+ 
+ 	/* clock state B */
+ 	if (safe_to_lower || watermarks->b.urgent_ns > hubbub1->watermarks.b.urgent_ns) {
+@@ -192,6 +199,14 @@ static void hubbub21_program_urgent_watermarks(
+ 				DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, watermarks->a.frac_urg_bw_nom);
+ 	}
+ 
++	if (safe_to_lower || watermarks->b.urgent_latency_ns > hubbub1->watermarks.b.urgent_latency_ns) {
++		hubbub1->watermarks.b.urgent_latency_ns = watermarks->b.urgent_latency_ns;
++		prog_wm_value = convert_and_clamp(watermarks->b.urgent_latency_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0,
++				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, prog_wm_value);
++	}
++
+ 	/* clock state C */
+ 	if (safe_to_lower || watermarks->c.urgent_ns > hubbub1->watermarks.c.urgent_ns) {
+ 		hubbub1->watermarks.c.urgent_ns = watermarks->c.urgent_ns;
+@@ -223,6 +238,14 @@ static void hubbub21_program_urgent_watermarks(
+ 				DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, watermarks->a.frac_urg_bw_nom);
+ 	}
+ 
++	if (safe_to_lower || watermarks->c.urgent_latency_ns > hubbub1->watermarks.c.urgent_latency_ns) {
++		hubbub1->watermarks.c.urgent_latency_ns = watermarks->c.urgent_latency_ns;
++		prog_wm_value = convert_and_clamp(watermarks->c.urgent_latency_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, 0,
++				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, prog_wm_value);
++	}
++
+ 	/* clock state D */
+ 	if (safe_to_lower || watermarks->d.urgent_ns > hubbub1->watermarks.d.urgent_ns) {
+ 		hubbub1->watermarks.d.urgent_ns = watermarks->d.urgent_ns;
+@@ -253,9 +276,17 @@ static void hubbub21_program_urgent_watermarks(
+ 		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0,
+ 				DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, watermarks->a.frac_urg_bw_nom);
+ 	}
++
++	if (safe_to_lower || watermarks->d.urgent_latency_ns > hubbub1->watermarks.d.urgent_latency_ns) {
++		hubbub1->watermarks.d.urgent_latency_ns = watermarks->d.urgent_latency_ns;
++		prog_wm_value = convert_and_clamp(watermarks->d.urgent_latency_ns,
++				refclk_mhz, 0x1fffff);
++		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, 0,
++				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, prog_wm_value);
++	}
+ }
+ 
+-static void hubbub21_program_stutter_watermarks(
++void hubbub21_program_stutter_watermarks(
+ 		struct hubbub *hubbub,
+ 		struct dcn_watermark_set *watermarks,
+ 		unsigned int refclk_mhz,
+@@ -389,7 +420,7 @@ static void hubbub21_program_stutter_watermarks(
+ 	}
+ }
+ 
+-static void hubbub21_program_pstate_watermarks(
++void hubbub21_program_pstate_watermarks(
+ 		struct hubbub *hubbub,
+ 		struct dcn_watermark_set *watermarks,
+ 		unsigned int refclk_mhz,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
+index 6ff3cdb89178..698c470cc0f6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
+@@ -114,11 +114,28 @@
+ 	HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh)
+ 
+ void dcn21_dchvm_init(struct hubbub *hubbub);
++int hubbub21_init_dchub(struct hubbub *hubbub,
++		struct dcn_hubbub_phys_addr_config *pa_config);
+ void hubbub21_program_watermarks(
+ 		struct hubbub *hubbub,
+ 		struct dcn_watermark_set *watermarks,
+ 		unsigned int refclk_mhz,
+ 		bool safe_to_lower);
++void hubbub21_program_urgent_watermarks(
++		struct hubbub *hubbub,
++		struct dcn_watermark_set *watermarks,
++		unsigned int refclk_mhz,
++		bool safe_to_lower);
++void hubbub21_program_stutter_watermarks(
++		struct hubbub *hubbub,
++		struct dcn_watermark_set *watermarks,
++		unsigned int refclk_mhz,
++		bool safe_to_lower);
++void hubbub21_program_pstate_watermarks(
++		struct hubbub *hubbub,
++		struct dcn_watermark_set *watermarks,
++		unsigned int refclk_mhz,
++		bool safe_to_lower);
+ 
+ void hubbub21_wm_read_state(struct hubbub *hubbub,
+ 		struct dcn_hubbub_wm *wm);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+index e8668388581b..67b610d6d91f 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+@@ -43,6 +43,7 @@ struct dcn_watermarks {
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ 	uint32_t frac_urg_bw_nom;
+ 	uint32_t frac_urg_bw_flip;
++	int32_t urgent_latency_ns;
+ #endif
+ 	struct cstate_pstate_watermarks_st cstate_pstate;
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4176-drm-amd-display-move-the-bounding-box-patch-before-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4176-drm-amd-display-move-the-bounding-box-patch-before-c.patch
new file mode 100644
index 00000000..d83d3ade
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4176-drm-amd-display-move-the-bounding-box-patch-before-c.patch
@@ -0,0 +1,66 @@
+From db7b94316b5d854d1eaf74fd7d9f97f331252ac7 Mon Sep 17 00:00:00 2001
+From: Lewis Huang <Lewis.Huang@amd.com>
+Date: Wed, 2 Oct 2019 14:09:52 -0400
+Subject: [PATCH 4176/4736] drm/amd/display: move the bounding box patch before
+ calculate wm
+
+[why]
+driver updateis the dcn2_1_soc into dml before call update_bw_bounding_box
+
+[How]
+Move the patch function before calculate wm.
+
+Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
+Signed-off-by: joseph graveno <joseph.gravenor@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 25 +++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 085e6d38c45e..05baf0e4d79f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1009,6 +1009,29 @@ static void calculate_wm_set_for_vlevel(
+ 
+ }
+ 
++static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
++{
++	kernel_fpu_begin();
++	if (dc->bb_overrides.sr_exit_time_ns) {
++		bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
++	}
++
++	if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
++		bb->sr_enter_plus_exit_time_us =
++				dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
++	}
++
++	if (dc->bb_overrides.urgent_latency_ns) {
++		bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
++	}
++
++	if (dc->bb_overrides.dram_clock_change_latency_ns) {
++		bb->dram_clock_change_latency_us =
++				dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
++	}
++	kernel_fpu_end();
++}
++
+ void dcn21_calculate_wm(
+ 		struct dc *dc, struct dc_state *context,
+ 		display_e2e_pipe_params_st *pipes,
+@@ -1023,6 +1046,8 @@ void dcn21_calculate_wm(
+ 
+ 	ASSERT(bw_params);
+ 
++	patch_bounding_box(dc, &context->bw_ctx.dml.soc);
++
+ 	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
+ 			if (!context->res_ctx.pipe_ctx[i].stream)
+ 				continue;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4177-drm-amd-display-enable-hostvm-based-on-roimmu-active.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4177-drm-amd-display-enable-hostvm-based-on-roimmu-active.patch
new file mode 100644
index 00000000..1840beaf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4177-drm-amd-display-enable-hostvm-based-on-roimmu-active.patch
@@ -0,0 +1,87 @@
+From 029033b0e5f6415f7e129232b13f402a41763c9d Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 2 Oct 2019 15:19:41 -0400
+Subject: [PATCH 4177/4736] drm/amd/display: enable hostvm based on roimmu
+ active for dcn2.1
+
+Enabling hostvm when ROIMMU is not active seems to break GPUVM.
+This fixes the issue by not enabling hostvm if ROIMMU is not
+activated.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../drm/amd/display/dc/dcn21/dcn21_hubbub.c   | 40 ++++++++++++-------
+ 1 file changed, 25 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+index 8e7e79f44272..bd247e5e753e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+@@ -22,6 +22,7 @@
+  * Authors: AMD
+  *
+  */
++#include <linux/delay.h>
+ #include "dm_services.h"
+ #include "dcn20/dcn20_hubbub.h"
+ #include "dcn21_hubbub.h"
+@@ -71,30 +72,39 @@ static uint32_t convert_and_clamp(
+ void dcn21_dchvm_init(struct hubbub *hubbub)
+ {
+ 	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
++	uint32_t riommu_active;
++	int i;
+ 
+ 	//Init DCHVM block
+ 	REG_UPDATE(DCHVM_CTRL0, HOSTVM_INIT_REQ, 1);
+ 
+ 	//Poll until RIOMMU_ACTIVE = 1
+-	//TODO: Figure out interval us and retry count
+-	REG_WAIT(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, 1, 5, 100);
++	for (i = 0; i < 100; i++) {
++		REG_GET(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, &riommu_active);
+ 
+-	//Reflect the power status of DCHUBBUB
+-	REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1);
++		if (riommu_active)
++			break;
++		else
++			udelay(5);
++	}
++
++	if (riommu_active) {
++		//Reflect the power status of DCHUBBUB
++		REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1);
+ 
+-	//Start rIOMMU prefetching
+-	REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1);
++		//Start rIOMMU prefetching
++		REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1);
+ 
+-	// Enable dynamic clock gating
+-	REG_UPDATE_4(DCHVM_CLK_CTRL,
+-					HVM_DISPCLK_R_GATE_DIS, 0,
+-					HVM_DISPCLK_G_GATE_DIS, 0,
+-					HVM_DCFCLK_R_GATE_DIS, 0,
+-					HVM_DCFCLK_G_GATE_DIS, 0);
++		// Enable dynamic clock gating
++		REG_UPDATE_4(DCHVM_CLK_CTRL,
++						HVM_DISPCLK_R_GATE_DIS, 0,
++						HVM_DISPCLK_G_GATE_DIS, 0,
++						HVM_DCFCLK_R_GATE_DIS, 0,
++						HVM_DCFCLK_G_GATE_DIS, 0);
+ 
+-	//Poll until HOSTVM_PREFETCH_DONE = 1
+-	//TODO: Figure out interval us and retry count
+-	REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);
++		//Poll until HOSTVM_PREFETCH_DONE = 1
++		REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);
++	}
+ }
+ 
+ int hubbub21_init_dchub(struct hubbub *hubbub,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4178-drm-amd-display-fix-incorrect-page-table-address-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4178-drm-amd-display-fix-incorrect-page-table-address-for.patch
new file mode 100644
index 00000000..df23f56e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4178-drm-amd-display-fix-incorrect-page-table-address-for.patch
@@ -0,0 +1,59 @@
+From 91e966568edf9bd745a26c96b77708cf3092a02a Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 2 Oct 2019 15:31:03 -0400
+Subject: [PATCH 4178/4736] drm/amd/display: fix incorrect page table address
+ for renoir
+
+Incorrect page table address and programming sys aperture for
+stutter gather, so fix it.
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../drm/amd/display/dc/dcn21/dcn21_hubbub.c   | 23 ++++++++++++++-----
+ 1 file changed, 17 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+index bd247e5e753e..fdfbdeb32459 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+@@ -111,19 +111,30 @@ int hubbub21_init_dchub(struct hubbub *hubbub,
+ 		struct dcn_hubbub_phys_addr_config *pa_config)
+ {
+ 	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
++	struct dcn_vmid_page_table_config phys_config;
+ 
+ 	REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
+-		FB_BASE, pa_config->system_aperture.fb_base);
++			FB_BASE, pa_config->system_aperture.fb_base >> 24);
+ 	REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
+-			FB_TOP, pa_config->system_aperture.fb_top);
++			FB_TOP, pa_config->system_aperture.fb_top >> 24);
+ 	REG_SET(DCN_VM_FB_OFFSET, 0,
+-			FB_OFFSET, pa_config->system_aperture.fb_offset);
++			FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
+ 	REG_SET(DCN_VM_AGP_BOT, 0,
+-			AGP_BOT, pa_config->system_aperture.agp_bot);
++			AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
+ 	REG_SET(DCN_VM_AGP_TOP, 0,
+-			AGP_TOP, pa_config->system_aperture.agp_top);
++			AGP_TOP, pa_config->system_aperture.agp_top >> 24);
+ 	REG_SET(DCN_VM_AGP_BASE, 0,
+-			AGP_BASE, pa_config->system_aperture.agp_base);
++			AGP_BASE, pa_config->system_aperture.agp_base >> 24);
++
++	if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
++		phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
++		phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12;
++		phys_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr | 1; //Note: hack
++		phys_config.depth = 0;
++		phys_config.block_size = 0;
++		// Init VMID 0 based on PA config
++		dcn20_vmid_setup(&hubbub1->vmid[0], &phys_config);
++	}
+ 
+ 	dcn21_dchvm_init(hubbub);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4179-drm-amd-display-Temporary-workaround-to-toggle-water.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4179-drm-amd-display-Temporary-workaround-to-toggle-water.patch
new file mode 100644
index 00000000..d76a05db
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4179-drm-amd-display-Temporary-workaround-to-toggle-water.patch
@@ -0,0 +1,92 @@
+From 4a2de49201a3d53abc4c27c8a93e368d7e65c926 Mon Sep 17 00:00:00 2001
+From: Lewis Huang <Lewis.Huang@amd.com>
+Date: Sat, 6 Jul 2019 16:02:25 -0500
+Subject: [PATCH 4179/4736] drm/amd/display: Temporary workaround to toggle
+ watermark setting
+
+[Why]
+Watermarks not propagated to DCHUBP after it is powered on
+
+[How]
+Add temoprary function apply_DEDCN21_147_wa to apply wm settings for Renoir
+
+Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 4 ++++
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c   | 9 +++++++++
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 1 +
+ drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h      | 1 +
+ 4 files changed, 15 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index ce2530509e12..6229a8ca0013 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1533,6 +1533,10 @@ static void dcn20_program_front_end_for_ctx(
+ 				msleep(1);
+ 		}
+ 	}
++
++	/* WA to apply WM setting*/
++	if (dc->hwseq->wa.DEGVIDCN21)
++		dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
+ }
+ 
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+index fdfbdeb32459..2232ccf14bdd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+@@ -616,6 +616,14 @@ void hubbub21_wm_read_state(struct hubbub *hubbub,
+ 			DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, &s->dram_clk_chanage);
+ }
+ 
++void hubbub21_apply_DEDCN21_147_wa(struct hubbub *hubbub)
++{
++	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
++	uint32_t prog_wm_value;
++
++	prog_wm_value = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
++	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
++}
+ 
+ static const struct hubbub_funcs hubbub21_funcs = {
+ 	.update_dchub = hubbub2_update_dchub,
+@@ -627,6 +635,7 @@ static const struct hubbub_funcs hubbub21_funcs = {
+ 	.wm_read_state = hubbub21_wm_read_state,
+ 	.get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
+ 	.program_watermarks = hubbub21_program_watermarks,
++	.apply_DEDCN21_147_wa = hubbub21_apply_DEDCN21_147_wa,
+ };
+ 
+ void hubbub21_construct(struct dcn20_hubbub *hubbub,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 05baf0e4d79f..a9e2dd71d7a6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1470,6 +1470,7 @@ static struct dce_hwseq *dcn21_hwseq_create(
+ 		hws->regs = &hwseq_reg;
+ 		hws->shifts = &hwseq_shift;
+ 		hws->masks = &hwseq_mask;
++		hws->wa.DEGVIDCN21 = true;
+ 	}
+ 	return hws;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+index a6297219d7fc..c81a17aeaa25 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+@@ -147,6 +147,7 @@ struct hubbub_funcs {
+ 	bool (*is_allow_self_refresh_enabled)(struct hubbub *hubbub);
+ 	void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow);
+ 
++	void (*apply_DEDCN21_147_wa)(struct hubbub *hubbub);
+ };
+ 
+ struct hubbub {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4180-drm-amd-display-initialize-RN-gpuvm-context-programm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4180-drm-amd-display-initialize-RN-gpuvm-context-programm.patch
new file mode 100644
index 00000000..92948dc2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4180-drm-amd-display-initialize-RN-gpuvm-context-programm.patch
@@ -0,0 +1,32 @@
+From 3e89f7c5fc264a02e59fefb7d9057d3801dad48b Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 2 Oct 2019 15:55:48 -0400
+Subject: [PATCH 4180/4736] drm/amd/display: initialize RN gpuvm context
+ programming function
+
+Renoir can use vm contexes as long as HOSTVM is off so
+this should be initialized.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+index 2232ccf14bdd..44f64a8e33f1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+@@ -628,7 +628,7 @@ void hubbub21_apply_DEDCN21_147_wa(struct hubbub *hubbub)
+ static const struct hubbub_funcs hubbub21_funcs = {
+ 	.update_dchub = hubbub2_update_dchub,
+ 	.init_dchub_sys_ctx = hubbub21_init_dchub,
+-	.init_vm_ctx = NULL,
++	.init_vm_ctx = hubbub2_init_vm_ctx,
+ 	.dcc_support_swizzle = hubbub2_dcc_support_swizzle,
+ 	.dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,
+ 	.get_dcc_compression_cap = hubbub2_get_dcc_compression_cap,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4181-drm-amd-display-use-dcn10-version-of-program-tiling-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4181-drm-amd-display-use-dcn10-version-of-program-tiling-.patch
new file mode 100644
index 00000000..7e2aae99
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4181-drm-amd-display-use-dcn10-version-of-program-tiling-.patch
@@ -0,0 +1,41 @@
+From f9655dbe5243835a39463a6fc5833bcc07ff64d6 Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Wed, 2 Oct 2019 15:57:13 -0400
+Subject: [PATCH 4181/4736] drm/amd/display: use dcn10 version of program
+ tiling on Renoir
+
+[Why]
+Renoir is gfx9, same as dcn10, not dcn20.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+index a00af513aa2b..2f5a5867e674 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+@@ -22,6 +22,8 @@
+  * Authors: AMD
+  *
+  */
++
++#include "dcn10/dcn10_hubp.h"
+ #include "dcn21_hubp.h"
+ 
+ #include "dm_services.h"
+@@ -202,7 +204,7 @@ static struct hubp_funcs dcn21_hubp_funcs = {
+ 	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
+ 	.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
+ 	.hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr,
+-	.hubp_program_surface_config = hubp2_program_surface_config,
++	.hubp_program_surface_config = hubp1_program_surface_config,
+ 	.hubp_is_flip_pending = hubp1_is_flip_pending,
+ 	.hubp_setup = hubp21_setup,
+ 	.hubp_setup_interdependent = hubp2_setup_interdependent,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4182-drm-amd-display-correct-dcn21-NUM_VMID-to-16.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4182-drm-amd-display-correct-dcn21-NUM_VMID-to-16.patch
new file mode 100644
index 00000000..d0549b65
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4182-drm-amd-display-correct-dcn21-NUM_VMID-to-16.patch
@@ -0,0 +1,31 @@
+From bc38311a711c0dd65138f1253bec9d8f021dc821 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 2 Oct 2019 15:59:23 -0400
+Subject: [PATCH 4182/4736] drm/amd/display: correct dcn21 NUM_VMID to 16
+
+1 vmid limitation only exists for HOSTVM which is a custom
+use case anyway.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+index 44f64a8e33f1..aeb5de6f4530 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+@@ -52,7 +52,7 @@
+ #ifdef NUM_VMID
+ #undef NUM_VMID
+ #endif
+-#define NUM_VMID 1
++#define NUM_VMID 16
+ 
+ static uint32_t convert_and_clamp(
+ 	uint32_t wm_ns,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4183-drm-amd-display-add-detile-buffer-size-for-renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4183-drm-amd-display-add-detile-buffer-size-for-renoir.patch
new file mode 100644
index 00000000..8a6b5a32
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4183-drm-amd-display-add-detile-buffer-size-for-renoir.patch
@@ -0,0 +1,27 @@
+From 42c60ff4f15362f4645549a8090d4f22ea8ef7df Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 3 Oct 2019 13:35:36 -0400
+Subject: [PATCH 4183/4736] drm/amd/display: add detile buffer size for renoir
+
+Detile buffer size affects dcc caps, it was already added for
+dcn2. Now add it for dcn21
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+index aeb5de6f4530..f546260c15b7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+@@ -653,4 +653,5 @@ void hubbub21_construct(struct dcn20_hubbub *hubbub,
+ 	hubbub->masks = hubbub_mask;
+ 
+ 	hubbub->debug_test_index_pstate = 0xB;
++	hubbub->detile_buf_size = 164 * 1024; /* 164KB for DCN2.0 */
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4184-drm-amd-display-update-dcn21-hubbub-registers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4184-drm-amd-display-update-dcn21-hubbub-registers.patch
new file mode 100644
index 00000000..3f1d24ed
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4184-drm-amd-display-update-dcn21-hubbub-registers.patch
@@ -0,0 +1,59 @@
+From 32559e89cd648263466d70e07de915d1409a9a49 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 3 Oct 2019 13:38:57 -0400
+Subject: [PATCH 4184/4736] drm/amd/display: update dcn21 hubbub registers
+
+use dcn20 common regs define to share some regs with dcn20
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h | 17 +++++++----------
+ 1 file changed, 7 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
+index 698c470cc0f6..c4840dfb1fa5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
+@@ -36,6 +36,10 @@
+ 	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
+ 	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
+ 	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
++	SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\
++	SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\
++	SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\
++	SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\
+ 	SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
+ 	SR(DCHVM_CTRL0), \
+ 	SR(DCHVM_MEM_CTRL), \
+@@ -44,16 +48,9 @@
+ 	SR(DCHVM_RIOMMU_STAT0)
+ 
+ #define HUBBUB_REG_LIST_DCN21()\
+-	HUBBUB_REG_LIST_DCN_COMMON(), \
++	HUBBUB_REG_LIST_DCN20_COMMON(), \
+ 	HUBBUB_SR_WATERMARK_REG_LIST(), \
+-	HUBBUB_HVM_REG_LIST(), \
+-	SR(DCHUBBUB_CRC_CTRL), \
+-	SR(DCN_VM_FB_LOCATION_BASE),\
+-	SR(DCN_VM_FB_LOCATION_TOP),\
+-	SR(DCN_VM_FB_OFFSET),\
+-	SR(DCN_VM_AGP_BOT),\
+-	SR(DCN_VM_AGP_TOP),\
+-	SR(DCN_VM_AGP_BASE)
++	HUBBUB_HVM_REG_LIST()
+ 
+ #define HUBBUB_MASK_SH_LIST_HVM(mask_sh) \
+ 	HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, mask_sh), \
+@@ -102,7 +99,7 @@
+ 	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh)
+ 
+ #define HUBBUB_MASK_SH_LIST_DCN21(mask_sh)\
+-	HUBBUB_MASK_SH_LIST_HVM(mask_sh),\
++	HUBBUB_MASK_SH_LIST_HVM(mask_sh), \
+ 	HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
+ 	HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
+ 	HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4185-drm-amd-display-update-renoir-bounding-box-and-res_c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4185-drm-amd-display-update-renoir-bounding-box-and-res_c.patch
new file mode 100644
index 00000000..5a4277ba
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4185-drm-amd-display-update-renoir-bounding-box-and-res_c.patch
@@ -0,0 +1,88 @@
+From c926472982c5f3f9b43d2e2c6becd6961df3e24e Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 3 Oct 2019 13:42:24 -0400
+Subject: [PATCH 4185/4736] drm/amd/display: update renoir bounding box and
+ res_caps
+
+The values for bounding box and res_caps were incorrect. So
+Fix them
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 24 ++++++++++---------
+ 1 file changed, 13 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index a9e2dd71d7a6..05b0b9ae37ac 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -82,6 +82,7 @@
+ 
+ 
+ struct _vcs_dpi_ip_params_st dcn2_1_ip = {
++	.odm_capable = 1,
+ 	.gpuvm_enable = 0,
+ 	.hostvm_enable = 0,
+ 	.gpuvm_max_page_table_levels = 1,
+@@ -203,11 +204,11 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
+ 				.state = 4,
+ 				.dcfclk_mhz = 810.0,
+ 				.fabricclk_mhz = 1600.0,
+-				.dispclk_mhz = 1015.0,
+-				.dppclk_mhz = 1015.0,
+-				.phyclk_mhz = 810.0,
++				.dispclk_mhz = 1395.0,
++				.dppclk_mhz = 1285.0,
++				.phyclk_mhz = 1325.0,
+ 				.socclk_mhz = 953.0,
+-				.dscclk_mhz = 318.334,
++				.dscclk_mhz = 489.0,
+ 				.dram_speed_mts = 4266.0,
+ 			},
+ 			/*Extra state, no dispclk ramping*/
+@@ -215,18 +216,18 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
+ 				.state = 5,
+ 				.dcfclk_mhz = 810.0,
+ 				.fabricclk_mhz = 1600.0,
+-				.dispclk_mhz = 1015.0,
+-				.dppclk_mhz = 1015.0,
+-				.phyclk_mhz = 810.0,
++				.dispclk_mhz = 1395.0,
++				.dppclk_mhz = 1285.0,
++				.phyclk_mhz = 1325.0,
+ 				.socclk_mhz = 953.0,
+-				.dscclk_mhz = 318.334,
++				.dscclk_mhz = 489.0,
+ 				.dram_speed_mts = 4266.0,
+ 			},
+ 
+ 		},
+ 
+-	.sr_exit_time_us = 9.0,
+-	.sr_enter_plus_exit_time_us = 11.0,
++	.sr_exit_time_us = 12.5,
++	.sr_enter_plus_exit_time_us = 17.0,
+ 	.urgent_latency_us = 4.0,
+ 	.urgent_latency_pixel_data_only_us = 4.0,
+ 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
+@@ -766,6 +767,7 @@ static const struct resource_caps res_cap_rn = {
+ 		.num_pll = 5,  // maybe 3 because the last two used for USB-c
+ 		.num_dwb = 1,
+ 		.num_ddc = 5,
++		.num_vmid = 1,
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 		.num_dsc = 3,
+ #endif
+@@ -835,7 +837,7 @@ static const struct dc_debug_options debug_defaults_drv = {
+ 		.disable_dcc = DCC_ENABLE,
+ 		.vsr_support = true,
+ 		.performance_trace = false,
+-		.max_downscale_src_width = 5120,/*upto 5K*/
++		.max_downscale_src_width = 3840,
+ 		.disable_pplib_wm_range = false,
+ 		.scl_reset_length10 = true,
+ 		.sanity_checks = true,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4186-drm-amd-display-add-dummy-functions-to-smu-for-Renoi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4186-drm-amd-display-add-dummy-functions-to-smu-for-Renoi.patch
new file mode 100644
index 00000000..7d97dff1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4186-drm-amd-display-add-dummy-functions-to-smu-for-Renoi.patch
@@ -0,0 +1,36 @@
+From fc5567ddc6bf05ed6d8078ca1b5d23c93f9012bb Mon Sep 17 00:00:00 2001
+From: Sung Lee <sung.lee@amd.com>
+Date: Fri, 30 Aug 2019 13:36:40 -0400
+Subject: [PATCH 4186/4736] drm/amd/display: add dummy functions to smu for
+ Renoir Silicon Diags
+
+[Why]
+Previously only dummy functions were added in Diags for FPGA.
+On silicon, this would lead to a segmentation fault on silicon diags.
+
+[How]
+Check if diags silicon and if so, add dummy functions.
+
+Signed-off-by: Sung Lee <sung.lee@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 05b0b9ae37ac..2125a3e50b0b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1399,7 +1399,7 @@ static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
+ 	if (!pp_smu)
+ 		return pp_smu;
+ 
+-	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
++	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) {
+ 		pp_smu->ctx.ver = PP_SMU_VER_RN;
+ 		pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
+ 		pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4187-drm-amd-display-update-odm-mode-validation-to-be-in-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4187-drm-amd-display-update-odm-mode-validation-to-be-in-.patch
new file mode 100644
index 00000000..5ce208f6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4187-drm-amd-display-update-odm-mode-validation-to-be-in-.patch
@@ -0,0 +1,62 @@
+From bbd12c8b9ac0d46f8738b88e6716ebabb2e7dc16 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Fri, 30 Aug 2019 16:32:13 -0400
+Subject: [PATCH 4187/4736] drm/amd/display: update odm mode validation to be
+ in line with policy
+
+Previously 8k30 worked with dsc and odm combine due to a workaround that ran
+the formula a second time with dsc support enable should dsc validation fail.
+This worked when clocks were low enough for formula to enable odm to lower
+voltage, however now broke due to increased clocks.
+
+This change updates the ODM combine policy within the formula to properly
+reflect our current policy within DC, only enabling ODM when we have to, as
+well as adding a check for viewport width when dsc is enabled.
+
+As a side effect the redundant call to dml when odm is required is now
+unnecessary.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c   | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+index 3b6ed60dcd35..fd707e7459b5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+@@ -65,6 +65,7 @@ typedef struct {
+ 
+ #define BPP_INVALID 0
+ #define BPP_BLENDED_PIPE 0xffffffff
++#define DCN21_MAX_DSC_IMAGE_WIDTH 5184
+ 
+ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib);
+ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
+@@ -3936,6 +3937,10 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
+ 				mode_lib->vba.MaximumSwathWidthInLineBuffer);
+ 	}
+ 	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
++		double MaxMaxDispclkRoundedDown = RoundToDFSGranularityDown(
++			mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states],
++			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
++
+ 		for (j = 0; j < 2; j++) {
+ 			mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(
+ 				mode_lib->vba.MaxDispclk[i],
+@@ -3965,7 +3970,9 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
+ 						&& i == mode_lib->vba.soc.num_states)
+ 					mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
+ 							* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
+-				if (mode_lib->vba.ODMCapability == false || mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine <= mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
++				if (mode_lib->vba.ODMCapability == false ||
++						(locals->PlaneRequiredDISPCLKWithoutODMCombine <= MaxMaxDispclkRoundedDown
++							&& (!locals->DSCEnabled[k] || locals->HActive[k] <= DCN21_MAX_DSC_IMAGE_WIDTH))) {
+ 					locals->ODMCombineEnablePerState[i][k] = false;
+ 					mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
+ 				} else {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4188-drm-amd-display-handle-18-case-in-TruncToValidBPP.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4188-drm-amd-display-handle-18-case-in-TruncToValidBPP.patch
new file mode 100644
index 00000000..ec668b3f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4188-drm-amd-display-handle-18-case-in-TruncToValidBPP.patch
@@ -0,0 +1,31 @@
+From b3dffd458cd73f615a072c4226fde585cc2b7e4f Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 3 Oct 2019 14:48:10 -0400
+Subject: [PATCH 4188/4736] drm/amd/display: handle "18" case in
+ TruncToValidBPP
+
+Handle 18 DecimalBPP like other cases
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+index fd707e7459b5..ba77957aefe3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+@@ -3380,6 +3380,8 @@ static unsigned int TruncToValidBPP(
+ 				return 30;
+ 			else if (DecimalBPP >= 24 && (DesiredBPP == 0 || DesiredBPP == 24))
+ 				return 24;
++			else if (DecimalBPP >= 18 && (DesiredBPP == 0 || DesiredBPP == 18))
++				return 18;
+ 			else
+ 				return BPP_INVALID;
+ 		}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4189-drm-amd-display-Fix-rn-audio-playback-and-video-play.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4189-drm-amd-display-Fix-rn-audio-playback-and-video-play.patch
new file mode 100644
index 00000000..218a424c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4189-drm-amd-display-Fix-rn-audio-playback-and-video-play.patch
@@ -0,0 +1,61 @@
+From 126d6092ca5e7273958180f377881ec38b0efa8f Mon Sep 17 00:00:00 2001
+From: Michael Strauss <michael.strauss@amd.com>
+Date: Wed, 7 Aug 2019 16:52:20 -0400
+Subject: [PATCH 4189/4736] drm/amd/display: Fix rn audio playback and video
+ playback speed
+
+[WHY]
+dprefclk is improperly read due to incorrect units used.
+Causes an audio clock to be improperly set, making audio
+non-functional and videos play back too fast
+
+[HOW]
+Scale dprefclk value from MHz to KHz (multiply by 1000)
+to ensure that dprefclk_khz is in correct units
+
+Signed-off-by: Michael Strauss <michael.strauss@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 15 +++++++--------
+ 1 file changed, 7 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 93e46e376bb1..fb8aa9436bf0 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -377,7 +377,7 @@ void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
+ 
+ 	rn_dump_clk_registers(&sb, clk_mgr_base, &log_info);
+ 
+-	s->dprefclk_khz = sb.dprefclk;
++	s->dprefclk_khz = sb.dprefclk * 1000;
+ }
+ 
+ void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
+@@ -633,16 +633,15 @@ void rn_clk_mgr_construct(
+ 			clk_mgr->dentist_vco_freq_khz = 3600000;
+ 
+ 		rn_dump_clk_registers(&s, &clk_mgr->base, &log_info);
+-		clk_mgr->base.dprefclk_khz = s.dprefclk;
+-
+-		if (clk_mgr->base.dprefclk_khz != 600000) {
+-			clk_mgr->base.dprefclk_khz = 600000;
+-			ASSERT(1); //TODO: Renoir follow up.
+-		}
++		/* Convert dprefclk units from MHz to KHz */
++		/* Value already divided by 10, some resolution lost */
++		clk_mgr->base.dprefclk_khz = s.dprefclk * 1000;
+ 
+ 		/* in case we don't get a value from the register, use default */
+-		if (clk_mgr->base.dprefclk_khz == 0)
++		if (clk_mgr->base.dprefclk_khz == 0) {
++			ASSERT(clk_mgr->base.dprefclk_khz == 600000);
+ 			clk_mgr->base.dprefclk_khz = 600000;
++		}
+ 	}
+ 
+ 	dce_clock_read_ss_info(clk_mgr);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4190-drm-amd-display-add-sanity-check-for-clk-table-from-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4190-drm-amd-display-add-sanity-check-for-clk-table-from-.patch
new file mode 100644
index 00000000..cb1dfa41
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4190-drm-amd-display-add-sanity-check-for-clk-table-from-.patch
@@ -0,0 +1,50 @@
+From cd651b9c1930cc2c2c05ea02f788c390adf9e10a Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Thu, 3 Oct 2019 15:06:01 -0400
+Subject: [PATCH 4190/4736] drm/amd/display: add sanity check for clk table
+ from smu
+
+[Why]
+Handle the case where we don't get a valid table. Also fixes compiler
+warning for variable potentially used before assignment.
+
+[How]
+If the entire table has no valid fclk, reject the table and use our own
+hard code.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index fb8aa9436bf0..0e712df87109 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -546,6 +546,8 @@ void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struc
+ {
+ 	int i, j = 0;
+ 
++	j = -1;
++
+ 	ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
+ 
+ 	/* Find lowest DPM, FCLK is filled in reverse order*/
+@@ -557,6 +559,12 @@ void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struc
+ 		}
+ 	}
+ 
++	if (j == -1) {
++		/* clock table is all 0s, just use our own hardcode */
++		ASSERT(0);
++		return;
++	}
++
+ 	bw_params->clk_table.num_entries = j + 1;
+ 
+ 	for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4191-drm-amd-display-fix-header-for-RN-clk-mgr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4191-drm-amd-display-fix-header-for-RN-clk-mgr.patch
new file mode 100644
index 00000000..d2e45a53
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4191-drm-amd-display-fix-header-for-RN-clk-mgr.patch
@@ -0,0 +1,43 @@
+From 76c869d28bc5e2577e9af4b4ad53936333cac8ef Mon Sep 17 00:00:00 2001
+From: joseph gravenor <joseph.gravenor@amd.com>
+Date: Mon, 8 Jul 2019 13:41:01 -0400
+Subject: [PATCH 4191/4736] drm/amd/display: fix header for RN clk mgr
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+[why]
+Should always MP0_BASE for any register definition from MP per-IP header files.
+I belive the reason the linux version of MP1_BASE works is The 0th element of the 0th table
+of that is identical to the corrisponding value of MP0_BASE in the renoir offset header file.
+The reason we should only use MP0_BASE is There is only one set of per-IP headers MP
+that includes all register definitions related to SMU IP block. This IP includes MP0, MP1, MP2
+and  an ecryption engine that can be used only by MP0. As a result all register definitions from
+MP file should be based only on MP0_BASE data.
+
+[How]
+Change MP1_BASE to MP0_BASE
+
+Signed-off-by: joseph gravenor <joseph.gravenor@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+index 8e860f567d5c..db28e91adb3d 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+@@ -33,7 +33,7 @@
+ #include "mp/mp_12_0_0_sh_mask.h"
+ 
+ #define REG(reg_name) \
+-	(MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
++	(MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
+ 
+ #define FN(reg_name, field) \
+ 	FD(reg_name##__##field)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4192-drm-amd-display-enable-smu-set-dcfclk.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4192-drm-amd-display-enable-smu-set-dcfclk.patch
new file mode 100644
index 00000000..c3badf7b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4192-drm-amd-display-enable-smu-set-dcfclk.patch
@@ -0,0 +1,43 @@
+From 17eb350281c4b09d8236036578f4a545af143205 Mon Sep 17 00:00:00 2001
+From: Lewis Huang <Lewis.Huang@amd.com>
+Date: Fri, 26 Jul 2019 14:02:03 -0400
+Subject: [PATCH 4192/4736] drm/amd/display: enable smu set dcfclk
+
+[Why]
+SMU fixed this issue after version 0x370c00
+
+[How]
+enable smu send message to set dcfclk after smu version 0x370c00
+
+Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c   | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+index db28e91adb3d..2650776acbc3 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+@@ -124,7 +124,7 @@ int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int reque
+ {
+ 	int actual_dcfclk_set_mhz = -1;
+ 
+-	if (clk_mgr->smu_ver < 0xFFFFFFFF)
++	if (clk_mgr->smu_ver < 0x370c00)
+ 		return actual_dcfclk_set_mhz;
+ 
+ 	actual_dcfclk_set_mhz = rn_vbios_smu_send_msg_with_param(
+@@ -139,7 +139,7 @@ int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int
+ {
+ 	int actual_min_ds_dcfclk_mhz = -1;
+ 
+-	if (clk_mgr->smu_ver < 0xFFFFFFFF)
++	if (clk_mgr->smu_ver < 0x370c00)
+ 		return actual_min_ds_dcfclk_mhz;
+ 
+ 	actual_min_ds_dcfclk_mhz = rn_vbios_smu_send_msg_with_param(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4193-drm-amd-display-use-requested_dispclk_khz-instead-of.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4193-drm-amd-display-use-requested_dispclk_khz-instead-of.patch
new file mode 100644
index 00000000..ba6e6d11
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4193-drm-amd-display-use-requested_dispclk_khz-instead-of.patch
@@ -0,0 +1,56 @@
+From a52e0d8d91005bb469581eefb5f3ec5bff836452 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 3 Oct 2019 15:39:14 -0400
+Subject: [PATCH 4193/4736] drm/amd/display: use requested_dispclk_khz instead
+ of clk
+
+Use requested_dispclk_khz / 1000 directly
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 13 ++-----------
+ 1 file changed, 2 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+index 2650776acbc3..5647fcf10717 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+@@ -84,16 +84,12 @@ int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dis
+ 	int actual_dispclk_set_mhz = -1;
+ 	struct dc *core_dc = clk_mgr->base.ctx->dc;
+ 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
+-	uint32_t clk = requested_dispclk_khz / 1000;
+-
+-	if (clk <= 100)
+-		clk = 101;
+ 
+ 	/*  Unit of SMU msg parameter is Mhz */
+ 	actual_dispclk_set_mhz = rn_vbios_smu_send_msg_with_param(
+ 			clk_mgr,
+ 			VBIOSSMC_MSG_SetDispclkFreq,
+-			clk);
++			requested_dispclk_khz / 1000);
+ 
+ 	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
+ 		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
+@@ -162,15 +158,10 @@ int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_
+ {
+ 	int actual_dppclk_set_mhz = -1;
+ 
+-	uint32_t clk = requested_dpp_khz / 1000;
+-
+-	if (clk <= 100)
+-		clk = 101;
+-
+ 	actual_dppclk_set_mhz = rn_vbios_smu_send_msg_with_param(
+ 			clk_mgr,
+ 			VBIOSSMC_MSG_SetDppclkFreq,
+-			clk);
++			requested_dpp_khz / 1000);
+ 
+ 	return actual_dppclk_set_mhz * 1000;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4194-drm-amd-display-handle-dp-is-usb-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4194-drm-amd-display-handle-dp-is-usb-c.patch
new file mode 100644
index 00000000..858e7590
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4194-drm-amd-display-handle-dp-is-usb-c.patch
@@ -0,0 +1,204 @@
+From 9f9a2f7528397a663e8472ddaa522e8bea6eece4 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 11 Oct 2019 10:37:49 -0400
+Subject: [PATCH 4194/4736] drm/amd/display: handle dp is usb-c
+
+This patch adds handling of dp is usb-c, it is not tested but is
+needed to support dp over usb-c
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ .../amd/display/dc/dcn10/dcn10_link_encoder.h | 14 +++
+ .../amd/display/dc/dcn21/dcn21_link_encoder.c | 93 ++++++++++++++++++-
+ .../amd/display/dc/dcn21/dcn21_link_encoder.h | 10 ++
+ 3 files changed, 116 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+index 239a6c90ffb9..88fcc395adf5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+@@ -113,6 +113,20 @@ struct dcn10_link_enc_registers {
+ 	uint32_t DIG_LANE_ENABLE;
+ 	/* UNIPHY */
+ 	uint32_t CHANNEL_XBAR_CNTL;
++	/* DPCS */
++	uint32_t RDPCSTX_PHY_CNTL3;
++	uint32_t RDPCSTX_PHY_CNTL4;
++	uint32_t RDPCSTX_PHY_CNTL5;
++	uint32_t RDPCSTX_PHY_CNTL6;
++	uint32_t RDPCSTX_PHY_CNTL7;
++	uint32_t RDPCSTX_PHY_CNTL8;
++	uint32_t RDPCSTX_PHY_CNTL9;
++	uint32_t RDPCSTX_PHY_CNTL10;
++	uint32_t RDPCSTX_PHY_CNTL11;
++	uint32_t RDPCSTX_PHY_CNTL12;
++	uint32_t RDPCSTX_PHY_CNTL13;
++	uint32_t RDPCSTX_PHY_CNTL14;
++	uint32_t RDPCSTX_PHY_CNTL15;
+ 	/* indirect registers */
+ 	uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
+ 	uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+index 526865c43b48..e8a504ca5890 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+@@ -203,6 +203,77 @@ static bool update_cfg_data(
+ 	return true;
+ }
+ 
++void dcn21_link_encoder_get_max_link_cap(struct link_encoder *enc,
++	struct dc_link_settings *link_settings)
++{
++	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
++	uint32_t value;
++
++	REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &value);
++
++	if (!value && link_settings->lane_count > LANE_COUNT_TWO)
++		link_settings->lane_count = LANE_COUNT_TWO;
++}
++
++bool dcn21_link_encoder_is_in_alt_mode(struct link_encoder *enc)
++{
++	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
++	uint32_t value;
++
++	REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &value);
++
++	// if value == 1 alt mode is disabled, otherwise it is enabled
++	return !value;
++}
++
++bool dcn21_link_encoder_acquire_phy(struct link_encoder *enc)
++{
++	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
++	int value;
++
++	if (enc->features.flags.bits.DP_IS_USB_C) {
++		REG_GET(RDPCSTX_PHY_CNTL6,
++				RDPCS_PHY_DPALT_DISABLE, &value);
++
++		if (value == 1) {
++			ASSERT(0);
++			return false;
++		}
++		REG_UPDATE(RDPCSTX_PHY_CNTL6,
++				RDPCS_PHY_DPALT_DISABLE_ACK, 0);
++
++		udelay(40);
++
++		REG_GET(RDPCSTX_PHY_CNTL6,
++						RDPCS_PHY_DPALT_DISABLE, &value);
++		if (value == 1) {
++			ASSERT(0);
++			REG_UPDATE(RDPCSTX_PHY_CNTL6,
++					RDPCS_PHY_DPALT_DISABLE_ACK, 1);
++			return false;
++		}
++	}
++
++	REG_UPDATE(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, 1);
++
++	return true;
++}
++
++
++
++static void dcn21_link_encoder_release_phy(struct link_encoder *enc)
++{
++	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
++
++	if (enc->features.flags.bits.DP_IS_USB_C) {
++		REG_UPDATE(RDPCSTX_PHY_CNTL6,
++				RDPCS_PHY_DPALT_DISABLE_ACK, 1);
++	}
++
++	REG_UPDATE(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, 0);
++
++}
++
+ void dcn21_link_encoder_enable_dp_output(
+ 	struct link_encoder *enc,
+ 	const struct dc_link_settings *link_settings,
+@@ -212,6 +283,9 @@ void dcn21_link_encoder_enable_dp_output(
+ 	struct dcn21_link_encoder *enc21 = (struct dcn21_link_encoder *) enc10;
+ 	struct dpcssys_phy_seq_cfg *cfg = &enc21->phy_seq_cfg;
+ 
++	if (!dcn21_link_encoder_acquire_phy(enc))
++		return;
++
+ 	if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
+ 		dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source);
+ 		return;
+@@ -226,13 +300,28 @@ void dcn21_link_encoder_enable_dp_output(
+ 
+ }
+ 
++void dcn21_link_encoder_enable_dp_mst_output(
++	struct link_encoder *enc,
++	const struct dc_link_settings *link_settings,
++	enum clock_source_id clock_source)
++{
++	if (!dcn21_link_encoder_acquire_phy(enc))
++		return;
++
++	dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);
++}
++
+ void dcn21_link_encoder_disable_output(
+ 	struct link_encoder *enc,
+ 	enum signal_type signal)
+ {
+ 	dcn10_link_encoder_disable_output(enc, signal);
+ 
++	if (dc_is_dp_signal(signal))
++		dcn21_link_encoder_release_phy(enc);
+ }
++
++
+ static const struct link_encoder_funcs dcn21_link_enc_funcs = {
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	.read_state = link_enc2_read_state,
+@@ -243,7 +332,7 @@ static const struct link_encoder_funcs dcn21_link_enc_funcs = {
+ 	.setup = dcn10_link_encoder_setup,
+ 	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
+ 	.enable_dp_output = dcn21_link_encoder_enable_dp_output,
+-	.enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
++	.enable_dp_mst_output = dcn21_link_encoder_enable_dp_mst_output,
+ 	.disable_output = dcn21_link_encoder_disable_output,
+ 	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
+ 	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
+@@ -261,6 +350,8 @@ static const struct link_encoder_funcs dcn21_link_enc_funcs = {
+ 	.fec_set_ready = enc2_fec_set_ready,
+ 	.fec_is_active = enc2_fec_is_active,
+ 	.get_dig_frontend = dcn10_get_dig_frontend,
++	.is_in_alt_mode = dcn21_link_encoder_is_in_alt_mode,
++	.get_max_link_cap = dcn21_link_encoder_get_max_link_cap,
+ };
+ 
+ void dcn21_link_encoder_construct(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
+index 438321e547db..1d7a1a51f13d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
+@@ -33,6 +33,16 @@ struct dcn21_link_encoder {
+ 	struct dpcssys_phy_seq_cfg phy_seq_cfg;
+ };
+ 
++#define LINK_ENCODER_MASK_SH_LIST_DCN21(mask_sh)\
++	LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh),\
++	LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL0_XBAR_SOURCE, mask_sh),\
++	LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL1_XBAR_SOURCE, mask_sh),\
++	LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL2_XBAR_SOURCE, mask_sh),\
++	LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL3_XBAR_SOURCE, mask_sh), \
++	SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \
++	SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \
++	SR(RDPCSTX0_RDPCSTX_SCRATCH)
++
+ void dcn21_link_encoder_enable_dp_output(
+ 	struct link_encoder *enc,
+ 	const struct dc_link_settings *link_settings,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4195-drm-amd-display-null-check-pp_smu-clock-table-before.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4195-drm-amd-display-null-check-pp_smu-clock-table-before.patch
new file mode 100644
index 00000000..7cd67919
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4195-drm-amd-display-null-check-pp_smu-clock-table-before.patch
@@ -0,0 +1,28 @@
+From 3c1c5221e17232b6e28de486f39948cc66ac3aec Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 11 Oct 2019 14:58:02 -0400
+Subject: [PATCH 4195/4736] drm/amd/display: null check pp_smu clock table
+ before using it
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 0e712df87109..b647e0320e4b 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -656,7 +656,7 @@ void rn_clk_mgr_construct(
+ 
+ 	clk_mgr->base.bw_params = &rn_bw_params;
+ 
+-	if (pp_smu) {
++	if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) {
+ 		pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table);
+ 		rn_clk_mgr_helper_populate_bw_params(clk_mgr->base.bw_params, &clock_table, &ctx->asic_id);
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4196-drm-amd-display-Make-dc_link_detect_helper-static.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4196-drm-amd-display-Make-dc_link_detect_helper-static.patch
new file mode 100644
index 00000000..ff1fe442
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4196-drm-amd-display-Make-dc_link_detect_helper-static.patch
@@ -0,0 +1,34 @@
+From 7ce4c5d8b0adaa37aaf0a0bb434274c1dec9d982 Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Wed, 16 Oct 2019 19:15:41 +0800
+Subject: [PATCH 4196/4736] drm/amd/display: Make dc_link_detect_helper static
+
+Fix sparse warning:
+
+drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:746:6:
+ warning: symbol 'dc_link_detect_helper' was not declared. Should it be static?
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 2a7fb79ad9f3..5474e2525e0c 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -741,7 +741,8 @@ static bool wait_for_alt_mode(struct dc_link *link)
+  * This does not create remote sinks but will trigger DM
+  * to start MST detection if a branch is detected.
+  */
+-bool dc_link_detect_helper(struct dc_link *link, enum dc_detect_reason reason)
++static bool dc_link_detect_helper(struct dc_link *link,
++				  enum dc_detect_reason reason)
+ {
+ 	struct dc_sink_init_data sink_init_data = { 0 };
+ 	struct display_sink_capability sink_caps = { 0 };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4197-drm-amdgpu-soc15-remove-unused-variables.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4197-drm-amdgpu-soc15-remove-unused-variables.patch
new file mode 100644
index 00000000..1d7385ec
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4197-drm-amdgpu-soc15-remove-unused-variables.patch
@@ -0,0 +1,28 @@
+From f25033019e1a27a4f1cb90dba3ce989449dfa28a Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 16 Oct 2019 12:20:09 -0400
+Subject: [PATCH 4197/4736] drm/amdgpu/soc15: remove unused variables
+
+Leftover when I rebased my last baco patches. Trivial.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 438722c0b76a..9457502a9909 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -497,8 +497,6 @@ static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
+ 
+ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+ {
+-	void *pp_handle = adev->powerplay.pp_handle;
+-	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+ 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+ 
+ 	/* avoid NBIF got stuck when do RAS recovery in BACO reset */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4198-drm-amdgpu-fix-up-for-amdgpu_tmz.c-and-removal-of-dr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4198-drm-amdgpu-fix-up-for-amdgpu_tmz.c-and-removal-of-dr.patch
new file mode 100644
index 00000000..5b7472f9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4198-drm-amdgpu-fix-up-for-amdgpu_tmz.c-and-removal-of-dr.patch
@@ -0,0 +1,31 @@
+From ba843799853807d7e4ae8dd5fe09fa9cc99e115b Mon Sep 17 00:00:00 2001
+From: Stephen Rothwell <sfr@canb.auug.org.au>
+Date: Wed, 16 Oct 2019 11:22:07 +1100
+Subject: [PATCH 4198/4736] drm/amdgpu: fix up for amdgpu_tmz.c and removal of
+ drm/drmP.h
+
+Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
+index 14a55003dd81..823527a0fa47 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.c
+@@ -20,7 +20,10 @@
+  * OTHER DEALINGS IN THE SOFTWARE.
+  */
+ 
+-#include <drm/drmP.h>
++#include <linux/device.h>
++
++#include <drm/amd_asic_type.h>
++
+ #include "amdgpu.h"
+ #include "amdgpu_tmz.h"
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4199-drm-amdgpu-uvd6-fix-allocation-size-in-enc-ring-test.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4199-drm-amdgpu-uvd6-fix-allocation-size-in-enc-ring-test.patch
new file mode 100644
index 00000000..d16214f8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4199-drm-amdgpu-uvd6-fix-allocation-size-in-enc-ring-test.patch
@@ -0,0 +1,134 @@
+From d621bffdf3894c0199526204509d46f2450a0a95 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 15 Oct 2019 18:07:19 -0400
+Subject: [PATCH 4199/4736] drm/amdgpu/uvd6: fix allocation size in enc ring
+ test (v2)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We need to allocate a large enough buffer for the
+session info, otherwise the IB test can overwrite
+other memory.
+
+v2: - session info is 128K according to mesa
+    - use the same session info for create and destroy
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241
+Acked-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: James Zhu <James.Zhu@amd.com>
+Tested-by: James Zhu <James.Zhu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 31 ++++++++++++++++++---------
+ 1 file changed, 21 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+index 16682b7998be..aa3849282bd4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+@@ -206,13 +206,14 @@ static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring)
+  * Open up a stream for HW test
+  */
+ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
++				       struct amdgpu_bo *bo,
+ 				       struct dma_fence **fence)
+ {
+ 	const unsigned ib_size_dw = 16;
+ 	struct amdgpu_job *job;
+ 	struct amdgpu_ib *ib;
+ 	struct dma_fence *f = NULL;
+-	uint64_t dummy;
++	uint64_t addr;
+ 	int i, r;
+ 
+ 	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+@@ -220,15 +221,15 @@ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle
+ 		return r;
+ 
+ 	ib = &job->ibs[0];
+-	dummy = ib->gpu_addr + 1024;
++	addr = amdgpu_bo_gpu_offset(bo);
+ 
+ 	ib->length_dw = 0;
+ 	ib->ptr[ib->length_dw++] = 0x00000018;
+ 	ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
+ 	ib->ptr[ib->length_dw++] = handle;
+ 	ib->ptr[ib->length_dw++] = 0x00010000;
+-	ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+-	ib->ptr[ib->length_dw++] = dummy;
++	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
++	ib->ptr[ib->length_dw++] = addr;
+ 
+ 	ib->ptr[ib->length_dw++] = 0x00000014;
+ 	ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
+@@ -268,13 +269,14 @@ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle
+  */
+ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
+ 					uint32_t handle,
++					struct amdgpu_bo *bo,
+ 					struct dma_fence **fence)
+ {
+ 	const unsigned ib_size_dw = 16;
+ 	struct amdgpu_job *job;
+ 	struct amdgpu_ib *ib;
+ 	struct dma_fence *f = NULL;
+-	uint64_t dummy;
++	uint64_t addr;
+ 	int i, r;
+ 
+ 	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+@@ -282,15 +284,15 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
+ 		return r;
+ 
+ 	ib = &job->ibs[0];
+-	dummy = ib->gpu_addr + 1024;
++	addr = amdgpu_bo_gpu_offset(bo);
+ 
+ 	ib->length_dw = 0;
+ 	ib->ptr[ib->length_dw++] = 0x00000018;
+ 	ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
+ 	ib->ptr[ib->length_dw++] = handle;
+ 	ib->ptr[ib->length_dw++] = 0x00010000;
+-	ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+-	ib->ptr[ib->length_dw++] = dummy;
++	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
++	ib->ptr[ib->length_dw++] = addr;
+ 
+ 	ib->ptr[ib->length_dw++] = 0x00000014;
+ 	ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
+@@ -327,13 +329,20 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
+ static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+ {
+ 	struct dma_fence *fence = NULL;
++	struct amdgpu_bo *bo = NULL;
+ 	long r;
+ 
+-	r = uvd_v6_0_enc_get_create_msg(ring, 1, NULL);
++	r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
++				      AMDGPU_GEM_DOMAIN_VRAM,
++				      &bo, NULL, NULL);
++	if (r)
++		return r;
++
++	r = uvd_v6_0_enc_get_create_msg(ring, 1, bo, NULL);
+ 	if (r)
+ 		goto error;
+ 
+-	r = uvd_v6_0_enc_get_destroy_msg(ring, 1, &fence);
++	r = uvd_v6_0_enc_get_destroy_msg(ring, 1, bo, &fence);
+ 	if (r)
+ 		goto error;
+ 
+@@ -345,6 +354,8 @@ static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+ 
+ error:
+ 	dma_fence_put(fence);
++	amdgpu_bo_unreserve(bo);
++	amdgpu_bo_unref(&bo);
+ 	return r;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4200-drm-amdgpu-uvd7-fix-allocation-size-in-enc-ring-test.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4200-drm-amdgpu-uvd7-fix-allocation-size-in-enc-ring-test.patch
new file mode 100644
index 00000000..1dec99e5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4200-drm-amdgpu-uvd7-fix-allocation-size-in-enc-ring-test.patch
@@ -0,0 +1,135 @@
+From d1e49d328cc2bb2be51b267f0a2c3db43d23155f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 15 Oct 2019 18:08:59 -0400
+Subject: [PATCH 4200/4736] drm/amdgpu/uvd7: fix allocation size in enc ring
+ test (v2)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We need to allocate a large enough buffer for the
+session info, otherwise the IB test can overwrite
+other memory.
+
+v2: - session info is 128K according to mesa
+    - use the same session info for create and destroy
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241
+Acked-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: James Zhu <James.Zhu@amd.com>
+Tested-by: James Zhu <James.Zhu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 33 ++++++++++++++++++---------
+ 1 file changed, 22 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+index 2f3d4e8032d5..8c2b31d4017e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+@@ -214,13 +214,14 @@ static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
+  * Open up a stream for HW test
+  */
+ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
++				       struct amdgpu_bo *bo,
+ 				       struct dma_fence **fence)
+ {
+ 	const unsigned ib_size_dw = 16;
+ 	struct amdgpu_job *job;
+ 	struct amdgpu_ib *ib;
+ 	struct dma_fence *f = NULL;
+-	uint64_t dummy;
++	uint64_t addr;
+ 	int i, r;
+ 
+ 	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+@@ -228,15 +229,15 @@ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle
+ 		return r;
+ 
+ 	ib = &job->ibs[0];
+-	dummy = ib->gpu_addr + 1024;
++	addr = amdgpu_bo_gpu_offset(bo);
+ 
+ 	ib->length_dw = 0;
+ 	ib->ptr[ib->length_dw++] = 0x00000018;
+ 	ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
+ 	ib->ptr[ib->length_dw++] = handle;
+ 	ib->ptr[ib->length_dw++] = 0x00000000;
+-	ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+-	ib->ptr[ib->length_dw++] = dummy;
++	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
++	ib->ptr[ib->length_dw++] = addr;
+ 
+ 	ib->ptr[ib->length_dw++] = 0x00000014;
+ 	ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
+@@ -275,13 +276,14 @@ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle
+  * Close up a stream for HW test or if userspace failed to do so
+  */
+ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
+-				struct dma_fence **fence)
++					struct amdgpu_bo *bo,
++					struct dma_fence **fence)
+ {
+ 	const unsigned ib_size_dw = 16;
+ 	struct amdgpu_job *job;
+ 	struct amdgpu_ib *ib;
+ 	struct dma_fence *f = NULL;
+-	uint64_t dummy;
++	uint64_t addr;
+ 	int i, r;
+ 
+ 	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+@@ -289,15 +291,15 @@ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handl
+ 		return r;
+ 
+ 	ib = &job->ibs[0];
+-	dummy = ib->gpu_addr + 1024;
++	addr = amdgpu_bo_gpu_offset(bo);
+ 
+ 	ib->length_dw = 0;
+ 	ib->ptr[ib->length_dw++] = 0x00000018;
+ 	ib->ptr[ib->length_dw++] = 0x00000001;
+ 	ib->ptr[ib->length_dw++] = handle;
+ 	ib->ptr[ib->length_dw++] = 0x00000000;
+-	ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+-	ib->ptr[ib->length_dw++] = dummy;
++	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
++	ib->ptr[ib->length_dw++] = addr;
+ 
+ 	ib->ptr[ib->length_dw++] = 0x00000014;
+ 	ib->ptr[ib->length_dw++] = 0x00000002;
+@@ -334,13 +336,20 @@ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handl
+ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+ {
+ 	struct dma_fence *fence = NULL;
++	struct amdgpu_bo *bo = NULL;
+ 	long r;
+ 
+-	r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL);
++	r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
++				      AMDGPU_GEM_DOMAIN_VRAM,
++				      &bo, NULL, NULL);
++	if (r)
++		return r;
++
++	r = uvd_v7_0_enc_get_create_msg(ring, 1, bo, NULL);
+ 	if (r)
+ 		goto error;
+ 
+-	r = uvd_v7_0_enc_get_destroy_msg(ring, 1, &fence);
++	r = uvd_v7_0_enc_get_destroy_msg(ring, 1, bo, &fence);
+ 	if (r)
+ 		goto error;
+ 
+@@ -352,6 +361,8 @@ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+ 
+ error:
+ 	dma_fence_put(fence);
++	amdgpu_bo_unreserve(bo);
++	amdgpu_bo_unref(&bo);
+ 	return r;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4201-drm-amdgpu-vcn-fix-allocation-size-in-enc-ring-test.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4201-drm-amdgpu-vcn-fix-allocation-size-in-enc-ring-test.patch
new file mode 100644
index 00000000..59365577
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4201-drm-amdgpu-vcn-fix-allocation-size-in-enc-ring-test.patch
@@ -0,0 +1,134 @@
+From 32f8b69dcac7547e2603bb3eb643c3eeeac2ac66 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 15 Oct 2019 18:09:41 -0400
+Subject: [PATCH 4201/4736] drm/amdgpu/vcn: fix allocation size in enc ring
+ test
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We need to allocate a large enough buffer for the
+session info, otherwise the IB test can overwrite
+other memory.
+
+- Session info is 128K according to mesa
+- Use the same session info for create and destroy
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241
+Acked-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: James Zhu <James.Zhu@amd.com>
+Tested-by: James Zhu <James.Zhu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 35 ++++++++++++++++---------
+ 1 file changed, 23 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+index 8566a264961f..6b31410a5ff9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+@@ -568,13 +568,14 @@ int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
+ }
+ 
+ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
+-			      struct dma_fence **fence)
++					 struct amdgpu_bo *bo,
++					 struct dma_fence **fence)
+ {
+ 	const unsigned ib_size_dw = 16;
+ 	struct amdgpu_job *job;
+ 	struct amdgpu_ib *ib;
+ 	struct dma_fence *f = NULL;
+-	uint64_t dummy;
++	uint64_t addr;
+ 	int i, r;
+ 
+ 	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+@@ -582,14 +583,14 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
+ 		return r;
+ 
+ 	ib = &job->ibs[0];
+-	dummy = ib->gpu_addr + 1024;
++	addr = amdgpu_bo_gpu_offset(bo);
+ 
+ 	ib->length_dw = 0;
+ 	ib->ptr[ib->length_dw++] = 0x00000018;
+ 	ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
+ 	ib->ptr[ib->length_dw++] = handle;
+-	ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+-	ib->ptr[ib->length_dw++] = dummy;
++	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
++	ib->ptr[ib->length_dw++] = addr;
+ 	ib->ptr[ib->length_dw++] = 0x0000000b;
+ 
+ 	ib->ptr[ib->length_dw++] = 0x00000014;
+@@ -620,13 +621,14 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
+ }
+ 
+ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
+-				struct dma_fence **fence)
++					  struct amdgpu_bo *bo,
++					  struct dma_fence **fence)
+ {
+ 	const unsigned ib_size_dw = 16;
+ 	struct amdgpu_job *job;
+ 	struct amdgpu_ib *ib;
+ 	struct dma_fence *f = NULL;
+-	uint64_t dummy;
++	uint64_t addr;
+ 	int i, r;
+ 
+ 	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+@@ -634,14 +636,14 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
+ 		return r;
+ 
+ 	ib = &job->ibs[0];
+-	dummy = ib->gpu_addr + 1024;
++	addr = amdgpu_bo_gpu_offset(bo);
+ 
+ 	ib->length_dw = 0;
+ 	ib->ptr[ib->length_dw++] = 0x00000018;
+ 	ib->ptr[ib->length_dw++] = 0x00000001;
+ 	ib->ptr[ib->length_dw++] = handle;
+-	ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+-	ib->ptr[ib->length_dw++] = dummy;
++	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
++	ib->ptr[ib->length_dw++] = addr;
+ 	ib->ptr[ib->length_dw++] = 0x0000000b;
+ 
+ 	ib->ptr[ib->length_dw++] = 0x00000014;
+@@ -674,13 +676,20 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
+ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+ {
+ 	struct dma_fence *fence = NULL;
++	struct amdgpu_bo *bo = NULL;
+ 	long r;
+ 
+-	r = amdgpu_vcn_enc_get_create_msg(ring, 1, NULL);
++	r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
++				      AMDGPU_GEM_DOMAIN_VRAM,
++				      &bo, NULL, NULL);
++	if (r)
++		return r;
++
++	r = amdgpu_vcn_enc_get_create_msg(ring, 1, bo, NULL);
+ 	if (r)
+ 		goto error;
+ 
+-	r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &fence);
++	r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, bo, &fence);
+ 	if (r)
+ 		goto error;
+ 
+@@ -692,6 +701,8 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+ 
+ error:
+ 	dma_fence_put(fence);
++	amdgpu_bo_unreserve(bo);
++	amdgpu_bo_unref(&bo);
+ 	return r;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4202-drm-amdgpu-powerplay-implement-interface-pp_power_pr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4202-drm-amdgpu-powerplay-implement-interface-pp_power_pr.patch
new file mode 100644
index 00000000..7986c5eb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4202-drm-amdgpu-powerplay-implement-interface-pp_power_pr.patch
@@ -0,0 +1,69 @@
+From 294d2d513a5497a9d67c88257830a27105f49de1 Mon Sep 17 00:00:00 2001
+From: Prike Liang <Prike.Liang@amd.com>
+Date: Wed, 16 Oct 2019 14:28:33 +0800
+Subject: [PATCH 4202/4736] drm/amdgpu/powerplay: implement interface
+ pp_power_profile_mode
+
+implement get_power_profile_mode for getting power profile mode status.
+
+Signed-off-by: Prike Liang <Prike.Liang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 34 ++++++++++++++++++++++
+ 1 file changed, 34 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index fa314c275a82..953e347633ec 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -640,6 +640,39 @@ static int renoir_set_watermarks_table(
+ 	return ret;
+ }
+ 
++static int renoir_get_power_profile_mode(struct smu_context *smu,
++					   char *buf)
++{
++	static const char *profile_name[] = {
++					"BOOTUP_DEFAULT",
++					"3D_FULL_SCREEN",
++					"POWER_SAVING",
++					"VIDEO",
++					"VR",
++					"COMPUTE",
++					"CUSTOM"};
++	uint32_t i, size = 0;
++	int16_t workload_type = 0;
++
++	if (!smu->pm_enabled || !buf)
++		return -EINVAL;
++
++	for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
++		/*
++		 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
++		 * Not all profile modes are supported on arcturus.
++		 */
++		workload_type = smu_workload_get_type(smu, i);
++		if (workload_type < 0)
++			continue;
++
++		size += sprintf(buf + size, "%2d %14s%s\n",
++			i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
++	}
++
++	return size;
++}
++
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_smu_msg_index = renoir_get_smu_msg_index,
+ 	.get_smu_table_index = renoir_get_smu_table_index,
+@@ -658,6 +691,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.set_performance_level = renoir_set_performance_level,
+ 	.get_dpm_clock_table = renoir_get_dpm_clock_table,
+ 	.set_watermarks_table = renoir_set_watermarks_table,
++	.get_power_profile_mode = renoir_get_power_profile_mode,
+ };
+ 
+ void renoir_set_ppt_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4203-drm-amd-display-add-NULL-checks-for-clock-manager-po.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4203-drm-amd-display-add-NULL-checks-for-clock-manager-po.patch
new file mode 100644
index 00000000..08ee2dcb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4203-drm-amd-display-add-NULL-checks-for-clock-manager-po.patch
@@ -0,0 +1,50 @@
+From a5c4f7383c296cbd8b46b997b5f10fcaa0d93f1c Mon Sep 17 00:00:00 2001
+From: Ahzo <Ahzo@tutanota.com>
+Date: Fri, 11 Oct 2019 19:55:03 +0200
+Subject: [PATCH 4203/4736] drm/amd/display: add NULL checks for clock manager
+ pointer
+
+This fixes kernel NULL pointer dereferences on shutdown:
+RIP: 0010:build_audio_output.isra.0+0x97/0x110 [amdgpu]
+RIP: 0010:enable_link_dp+0x186/0x300 [amdgpu]
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Ahzo <Ahzo@tutanota.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c               | 2 +-
+ drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 5 +++--
+ 2 files changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 5474e2525e0c..5ce5db7818e4 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -1528,7 +1528,7 @@ static enum dc_status enable_link_dp(
+ 
+ 	pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
+ 			link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
+-	if (!apply_seamless_boot_optimization)
++	if (state->clk_mgr && !apply_seamless_boot_optimization)
+ 		state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false);
+ 
+ 	dp_enable_link_phy(
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 27542c22fa55..d1e14393a0f0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -1158,8 +1158,9 @@ static void build_audio_output(
+ 		}
+ 	}
+ 
+-	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
+-			pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
++	if (state->clk_mgr &&
++		(pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
++			pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
+ 		audio_output->pll_info.dp_dto_source_clock_in_khz =
+ 				state->clk_mgr->funcs->get_dp_ref_clk_frequency(
+ 						state->clk_mgr);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4204-drm-amdgpu-psp11-wait-for-sOS-ready-for-ring-creatio.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4204-drm-amdgpu-psp11-wait-for-sOS-ready-for-ring-creatio.patch
new file mode 100644
index 00000000..6b96882c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4204-drm-amdgpu-psp11-wait-for-sOS-ready-for-ring-creatio.patch
@@ -0,0 +1,34 @@
+From 998f52b4faf6292c926fa83719fb4fa925e00ee0 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Fri, 18 Oct 2019 18:46:38 +0800
+Subject: [PATCH 4204/4736] drm/amdgpu/psp11: wait for sOS ready for ring
+ creation
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index f5bc9c176e7b..4f382bdd5f01 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -469,6 +469,14 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
+ 				   0x80000000, 0x8000FFFF, false);
+ 
+ 	} else {
++		/* Wait for sOS ready for ring creation */
++		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
++				   0x80000000, 0x80000000, false);
++		if (ret) {
++			DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
++			return ret;
++		}
++
+ 		/* Write low address of the ring to C2PMSG_69 */
+ 		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
+ 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4205-drm-amdgpu-psp11-fix-typo-in-comment.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4205-drm-amdgpu-psp11-fix-typo-in-comment.patch
new file mode 100644
index 00000000..35555a03
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4205-drm-amdgpu-psp11-fix-typo-in-comment.patch
@@ -0,0 +1,27 @@
+From 1ac72bb28d442ed2def64b9b9d1b63e1a9674c90 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Fri, 18 Oct 2019 18:47:20 +0800
+Subject: [PATCH 4205/4736] drm/amdgpu/psp11: fix typo in comment
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index 4f382bdd5f01..f2f67af65b94 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -242,7 +242,7 @@ static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
+ 	/* Copy PSP KDB binary to memory */
+ 	memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size);
+ 
+-	/* Provide the sys driver to bootloader */
++	/* Provide the PSP KDB to bootloader */
+ 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
+ 	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
+ 	psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4206-drm-amdgpu-update-amdgpu_discovery-to-handle-revisio.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4206-drm-amdgpu-update-amdgpu_discovery-to-handle-revisio.patch
new file mode 100644
index 00000000..941c710f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4206-drm-amdgpu-update-amdgpu_discovery-to-handle-revisio.patch
@@ -0,0 +1,55 @@
+From e91ec6627e027d48956b9dac7c09d160d7064977 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Mon, 30 Sep 2019 13:10:03 +0800
+Subject: [PATCH 4206/4736] drm/amdgpu: update amdgpu_discovery to handle
+ revision
+
+update amdgpu_discovery to get IP revision.
+
+Change-Id: I7a26f3b70da3b53771b5cc24e40a048d8f7ec005
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 +++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 2 +-
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+index 71198c5318e1..ddd8364102a2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+@@ -333,7 +333,7 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
+ }
+ 
+ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
+-				    int *major, int *minor)
++				    int *major, int *minor, int *revision)
+ {
+ 	struct binary_header *bhdr;
+ 	struct ip_discovery_header *ihdr;
+@@ -369,6 +369,8 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
+ 					*major = ip->major;
+ 				if (minor)
+ 					*minor = ip->minor;
++				if (revision)
++					*revision = ip->revision;
+ 				return 0;
+ 			}
+ 			ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
+index 5a6693d7d269..ba78e15d9b05 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
+@@ -30,7 +30,7 @@ int amdgpu_discovery_init(struct amdgpu_device *adev);
+ void amdgpu_discovery_fini(struct amdgpu_device *adev);
+ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);
+ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
+-                                    int *major, int *minor);
++                                    int *major, int *minor, int *revision);
+ int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);
+ 
+ #endif /* __AMDGPU_DISCOVERY__ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4207-drm-amdgpu-add-a-generic-fb-accessing-helper-functio.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4207-drm-amdgpu-add-a-generic-fb-accessing-helper-functio.patch
new file mode 100644
index 00000000..3da523f2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4207-drm-amdgpu-add-a-generic-fb-accessing-helper-functio.patch
@@ -0,0 +1,101 @@
+From 127264c9ea12a42fbb31f94eecb20d7917f73efe Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Mon, 30 Sep 2019 13:33:50 +0800
+Subject: [PATCH 4207/4736] drm/amdgpu: add a generic fb accessing helper
+ function(v3)
+
+add a generic helper function for accessing framebuffer via MMIO
+
+Change-Id: I075e138083e5aef57485a09fe44f27c34ff483a3
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h           |  2 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    | 30 +++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 12 +-------
+ 3 files changed, 33 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index e4172f9bece6..6ed17115a56d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1029,6 +1029,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ void amdgpu_device_fini(struct amdgpu_device *adev);
+ int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
+ 
++void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
++			       uint32_t *buf, size_t size, bool write);
+ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
+ 			uint32_t acc_flags);
+ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 46723a10d98a..634b581f96b8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -153,6 +153,36 @@ bool amdgpu_device_is_px(struct drm_device *dev)
+ 	return false;
+ }
+ 
++/**
++ * VRAM access helper functions.
++ *
++ * amdgpu_device_vram_access - read/write a buffer in vram
++ *
++ * @adev: amdgpu_device pointer
++ * @pos: offset of the buffer in vram
++ * @buf: virtual address of the buffer in system memory
++ * @size: read/write size, sizeof(@buf) must > @size
++ * @write: true - write to vram, otherwise - read from vram
++ */
++void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
++			       uint32_t *buf, size_t size, bool write)
++{
++	uint64_t last;
++	unsigned long flags;
++
++	last = size - 4;
++	for (last += pos; pos <= last; pos += 4) {
++		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
++		WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
++		WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
++		if (write)
++			WREG32_NO_KIQ(mmMM_DATA, *buf++);
++		else
++			*buf++ = RREG32_NO_KIQ(mmMM_DATA);
++		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
++	}
++}
++
+ /*
+  * MMIO register access helper functions.
+  */
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+index ddd8364102a2..f95092741c38 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+@@ -134,20 +134,10 @@ static int hw_id_map[MAX_HWIP] = {
+ 
+ static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *binary)
+ {
+-	uint32_t *p = (uint32_t *)binary;
+ 	uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
+ 	uint64_t pos = vram_size - DISCOVERY_TMR_SIZE;
+-	unsigned long flags;
+-
+-	while (pos < vram_size) {
+-		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
+-		WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
+-		WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
+-		*p++ = RREG32_NO_KIQ(mmMM_DATA);
+-		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
+-		pos += 4;
+-	}
+ 
++	amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, DISCOVERY_TMR_SIZE, false);
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4208-drm-amdgpu-introduce-psp_v11_0_is_sos_alive-interfac.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4208-drm-amdgpu-introduce-psp_v11_0_is_sos_alive-interfac.patch
new file mode 100644
index 00000000..3ff1fa42
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4208-drm-amdgpu-introduce-psp_v11_0_is_sos_alive-interfac.patch
@@ -0,0 +1,83 @@
+From bb67d025b4fb92d3be1356c7ccb43d89fab544c8 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Mon, 30 Sep 2019 14:16:42 +0800
+Subject: [PATCH 4208/4736] drm/amdgpu: introduce psp_v11_0_is_sos_alive
+ interface(v2)
+
+introduce psp_v11_0_is_sos_alive func for common use.
+
+Change-Id: I5ab83987da84fe19fce93f35ae385c0d8ae3c39e
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 22 +++++++++++++---------
+ 1 file changed, 13 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index f2f67af65b94..b52af59079b7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -214,18 +214,26 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
+ 	return err;
+ }
+ 
++static bool psp_v11_0_is_sos_alive(struct psp_context *psp)
++{
++	struct amdgpu_device *adev = psp->adev;
++	uint32_t sol_reg;
++
++	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
++
++	return sol_reg != 0x0;
++}
++
+ static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
+ {
+ 	int ret;
+ 	uint32_t psp_gfxdrv_command_reg = 0;
+ 	struct amdgpu_device *adev = psp->adev;
+-	uint32_t sol_reg;
+ 
+ 	/* Check tOS sign of life register to confirm sys driver and sOS
+ 	 * are already been loaded.
+ 	 */
+-	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
+-	if (sol_reg) {
++	if (psp_v11_0_is_sos_alive(psp)) {
+ 		psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
+ 		dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
+ 		return 0;
+@@ -261,13 +269,11 @@ static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
+ 	int ret;
+ 	uint32_t psp_gfxdrv_command_reg = 0;
+ 	struct amdgpu_device *adev = psp->adev;
+-	uint32_t sol_reg;
+ 
+ 	/* Check sOS sign of life register to confirm sys driver and sOS
+ 	 * are already been loaded.
+ 	 */
+-	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
+-	if (sol_reg) {
++	if (psp_v11_0_is_sos_alive(psp)) {
+ 		psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
+ 		dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
+ 		return 0;
+@@ -305,13 +311,11 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
+ 	int ret;
+ 	unsigned int psp_gfxdrv_command_reg = 0;
+ 	struct amdgpu_device *adev = psp->adev;
+-	uint32_t sol_reg;
+ 
+ 	/* Check sOS sign of life register to confirm sys driver and sOS
+ 	 * are already been loaded.
+ 	 */
+-	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
+-	if (sol_reg)
++	if (psp_v11_0_is_sos_alive(psp))
+ 		return 0;
+ 
+ 	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4209-drm-amdgpu-update-atomfirmware-header-with-memory-tr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4209-drm-amdgpu-update-atomfirmware-header-with-memory-tr.patch
new file mode 100644
index 00000000..2114c913
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4209-drm-amdgpu-update-atomfirmware-header-with-memory-tr.patch
@@ -0,0 +1,64 @@
+From dafc724cbbe01c1a41e14a948dd5165c839e8e5f Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Tue, 8 Oct 2019 13:57:28 +0800
+Subject: [PATCH 4209/4736] drm/amdgpu: update atomfirmware header with memory
+ training related members(v3)
+
+add new vram_reserve_block structure and atomfirmware_internal_constants enumeration
+
+Change-Id: I1187d8916b2ad04764e4fdad6f56b72e71adae27
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/include/atomfirmware.h | 27 +++++++++++++++++-----
+ 1 file changed, 21 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
+index 73e31c377402..4e5eb4c8097e 100644
+--- a/drivers/gpu/drm/amd/include/atomfirmware.h
++++ b/drivers/gpu/drm/amd/include/atomfirmware.h
+@@ -492,12 +492,13 @@ struct atom_firmware_info_v3_1
+ /* Total 32bit cap indication */
+ enum atombios_firmware_capability
+ {
+-  ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
+-  ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION  = 0x00000002,
+-  ATOM_FIRMWARE_CAP_WMI_SUPPORT  = 0x00000040,
+-  ATOM_FIRMWARE_CAP_HWEMU_ENABLE  = 0x00000080,
+-  ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100,
+-  ATOM_FIRMWARE_CAP_SRAM_ECC      = 0x00000200,
++	ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
++	ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION  = 0x00000002,
++	ATOM_FIRMWARE_CAP_WMI_SUPPORT  = 0x00000040,
++	ATOM_FIRMWARE_CAP_HWEMU_ENABLE  = 0x00000080,
++	ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100,
++	ATOM_FIRMWARE_CAP_SRAM_ECC      = 0x00000200,
++	ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING  = 0x00000400,
+ };
+ 
+ enum atom_cooling_solution_id{
+@@ -671,6 +672,20 @@ struct vram_usagebyfirmware_v2_1
+   uint16_t  used_by_driver_in_kb; 
+ };
+ 
++/* This is part of vram_usagebyfirmware_v2_1 */
++struct vram_reserve_block
++{
++	uint32_t start_address_in_kb;
++	uint16_t used_by_firmware_in_kb;
++	uint16_t used_by_driver_in_kb;
++};
++
++/* Definitions for constance */
++enum atomfirmware_internal_constants
++{
++	ONE_KiB	= 0x400,
++	ONE_MiB	= 0x100000,
++};
+ 
+ /* 
+   ***************************************************************************
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4210-drm-amdgpu-atomfirmware-add-memory-training-related-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4210-drm-amdgpu-atomfirmware-add-memory-training-related-.patch
new file mode 100644
index 00000000..042e3e58
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4210-drm-amdgpu-atomfirmware-add-memory-training-related-.patch
@@ -0,0 +1,227 @@
+From 99f25c59abada45c37619e5681b141bec1fb28db Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Mon, 30 Sep 2019 13:43:31 +0800
+Subject: [PATCH 4210/4736] drm/amdgpu/atomfirmware: add memory training
+ related helper functions(v3)
+
+parse firmware to get memory training capability and fb location.
+
+Change-Id: I8515203c09a207674b1721a8eac453b407394503
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h           |   8 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c  |   5 +
+ .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c  | 136 ++++++++++++++++++
+ .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h  |   1 +
+ 4 files changed, 150 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 6ed17115a56d..8c5c1833aca7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -296,6 +296,9 @@ struct amdgpu_ip_block_version {
+ 	const struct amd_ip_funcs *funcs;
+ };
+ 
++#define HW_REV(_Major, _Minor, _Rev) \
++	((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
++
+ struct amdgpu_ip_block {
+ 	struct amdgpu_ip_block_status status;
+ 	const struct amdgpu_ip_block_version *version;
+@@ -647,6 +650,11 @@ struct amdgpu_fw_vram_usage {
+ 	u64 size;
+ 	struct amdgpu_bo *reserved_bo;
+ 	void *va;
++
++	/* Offset on the top of VRAM, used as c2p write buffer.
++	*/
++	u64 mem_train_fb_loc;
++	bool mem_train_support;
+ };
+ 
+ /*
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+index e02781b37e73..a0d582a1e8c6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+@@ -2038,6 +2038,11 @@ int amdgpu_atombios_init(struct amdgpu_device *adev)
+ 	if (adev->is_atom_fw) {
+ 		amdgpu_atomfirmware_scratch_regs_init(adev);
+ 		amdgpu_atomfirmware_allocate_fb_scratch(adev);
++		ret = amdgpu_atomfirmware_get_mem_train_fb_loc(adev);
++		if (ret) {
++			DRM_ERROR("Failed to get mem train fb location.\n");
++			return ret;
++		}
+ 	} else {
+ 		amdgpu_atombios_scratch_regs_init(adev);
+ 		amdgpu_atombios_allocate_fb_scratch(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+index a253a554f41f..37ab291217f6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+@@ -27,6 +27,7 @@
+ #include "amdgpu_atomfirmware.h"
+ #include "atom.h"
+ #include "atombios.h"
++#include "soc15_hw_ip.h"
+ 
+ bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
+ {
+@@ -462,3 +463,138 @@ int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
+ 	}
+ 	return -EINVAL;
+ }
++
++/*
++ * Check if VBIOS supports GDDR6 training data save/restore
++ */
++static bool gddr6_mem_train_vbios_support(struct amdgpu_device *adev)
++{
++	uint16_t data_offset;
++	int index;
++
++	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
++					    firmwareinfo);
++	if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
++					  NULL, NULL, &data_offset)) {
++		struct atom_firmware_info_v3_1 *firmware_info =
++			(struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
++							   data_offset);
++
++		DRM_DEBUG("atom firmware capability:0x%08x.\n",
++			  le32_to_cpu(firmware_info->firmware_capability));
++
++		if (le32_to_cpu(firmware_info->firmware_capability) &
++		    ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING)
++			return true;
++	}
++
++	return false;
++}
++
++static int gddr6_mem_train_support(struct amdgpu_device *adev)
++{
++	int ret;
++	uint32_t major, minor, revision, hw_v;
++
++	if (gddr6_mem_train_vbios_support(adev)) {
++		amdgpu_discovery_get_ip_version(adev, MP0_HWID, &major, &minor, &revision);
++		hw_v = HW_REV(major, minor, revision);
++		/*
++		 * treat 0 revision as a special case since register for MP0 and MMHUB is missing
++		 * for some Navi10 A0, preventing driver from discovering the hwip information since
++		 * none of the functions will be initialized, it should not cause any problems
++		 */
++		switch (hw_v) {
++		case HW_REV(11, 0, 0):
++		case HW_REV(11, 0, 5):
++			ret = 1;
++			break;
++		default:
++			DRM_ERROR("memory training vbios supports but psp hw(%08x)"
++				  " doesn't support!\n", hw_v);
++			ret = -1;
++			break;
++		}
++	} else {
++		ret = 0;
++		hw_v = -1;
++	}
++
++
++	DRM_DEBUG("mp0 hw_v %08x, ret:%d.\n", hw_v, ret);
++	return ret;
++}
++
++int amdgpu_atomfirmware_get_mem_train_fb_loc(struct amdgpu_device *adev)
++{
++	struct atom_context *ctx = adev->mode_info.atom_context;
++	unsigned char *bios = ctx->bios;
++	struct vram_reserve_block *reserved_block;
++	int index, block_number;
++	uint8_t frev, crev;
++	uint16_t data_offset, size;
++	uint32_t start_address_in_kb;
++	uint64_t offset;
++	int ret;
++
++	adev->fw_vram_usage.mem_train_support = false;
++
++	if (adev->asic_type != CHIP_NAVI10 &&
++	    adev->asic_type != CHIP_NAVI14)
++		return 0;
++
++	if (amdgpu_sriov_vf(adev))
++		return 0;
++
++	ret = gddr6_mem_train_support(adev);
++	if (ret == -1)
++		return -EINVAL;
++	else if (ret == 0)
++		return 0;
++
++	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
++					    vram_usagebyfirmware);
++	ret = amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev,
++					    &data_offset);
++	if (ret == 0) {
++		DRM_ERROR("parse data header failed.\n");
++		return -EINVAL;
++	}
++
++	DRM_DEBUG("atom firmware common table header size:0x%04x, frev:0x%02x,"
++		  " crev:0x%02x, data_offset:0x%04x.\n", size, frev, crev, data_offset);
++	/* only support 2.1+ */
++	if (((uint16_t)frev << 8 | crev) < 0x0201) {
++		DRM_ERROR("frev:0x%02x, crev:0x%02x < 2.1 !\n", frev, crev);
++		return -EINVAL;
++	}
++
++	reserved_block = (struct vram_reserve_block *)
++		(bios + data_offset + sizeof(struct atom_common_table_header));
++	block_number = ((unsigned int)size - sizeof(struct atom_common_table_header))
++		/ sizeof(struct vram_reserve_block);
++	reserved_block += (block_number > 0) ? block_number-1 : 0;
++	DRM_DEBUG("block_number:0x%04x, last block: 0x%08xkb sz, %dkb fw, %dkb drv.\n",
++		  block_number,
++		  le32_to_cpu(reserved_block->start_address_in_kb),
++		  le16_to_cpu(reserved_block->used_by_firmware_in_kb),
++		  le16_to_cpu(reserved_block->used_by_driver_in_kb));
++	if (reserved_block->used_by_firmware_in_kb > 0) {
++		start_address_in_kb = le32_to_cpu(reserved_block->start_address_in_kb);
++		offset = (uint64_t)start_address_in_kb * ONE_KiB;
++		if ((offset & (ONE_MiB - 1)) < (4 * ONE_KiB + 1) ) {
++			offset -= ONE_MiB;
++		}
++
++		offset &= ~(ONE_MiB - 1);
++		adev->fw_vram_usage.mem_train_fb_loc = offset;
++		adev->fw_vram_usage.mem_train_support = true;
++		DRM_DEBUG("mem_train_fb_loc:0x%09llx.\n", offset);
++		ret = 0;
++	} else {
++		DRM_ERROR("used_by_firmware_in_kb is 0!\n");
++		ret = -EINVAL;
++	}
++
++	return ret;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+index 53449fc7baf4..f871af5ea6f3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+@@ -31,6 +31,7 @@ void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev);
+ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
+ int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+ 	int *vram_width, int *vram_type, int *vram_vendor);
++int amdgpu_atomfirmware_get_mem_train_fb_loc(struct amdgpu_device *adev);
+ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev);
+ int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev);
+ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4211-drm-amdgpu-add-psp-memory-training-callbacks-and-mac.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4211-drm-amdgpu-add-psp-memory-training-callbacks-and-mac.patch
new file mode 100644
index 00000000..9a3cf1d2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4211-drm-amdgpu-add-psp-memory-training-callbacks-and-mac.patch
@@ -0,0 +1,157 @@
+From e91173d7f1aa3ae91424e81e73e50072c688c522 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Mon, 30 Sep 2019 14:07:00 +0800
+Subject: [PATCH 4211/4736] drm/amdgpu: add psp memory training callbacks and
+ macro
+
+add interface for memory training.
+
+Change-Id: I20f5e3dc574d87bc6d261db69d5717bd4db73ebc
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 18 ++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 55 +++++++++++++++++++++++++
+ 2 files changed, 73 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index e4f4ae99280a..64db0c8cee4c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -88,6 +88,17 @@ static int psp_sw_init(void *handle)
+ 		return ret;
+ 	}
+ 
++	ret = psp_mem_training_init(psp);
++	if (ret) {
++		DRM_ERROR("Failed to initliaze memory training!\n");
++		return ret;
++	}
++	ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
++	if (ret) {
++		DRM_ERROR("Failed to process memory training!\n");
++		return ret;
++	}
++
+ 	return 0;
+ }
+ 
+@@ -95,6 +106,7 @@ static int psp_sw_fini(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
++	psp_mem_training_fini(&adev->psp);
+ 	release_firmware(adev->psp.sos_fw);
+ 	adev->psp.sos_fw = NULL;
+ 	release_firmware(adev->psp.asd_fw);
+@@ -1610,6 +1622,12 @@ static int psp_resume(void *handle)
+ 
+ 	DRM_INFO("PSP is resuming...\n");
+ 
++	ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
++	if (ret) {
++		DRM_ERROR("Failed to process memory training!\n");
++		return ret;
++	}
++
+ 	mutex_lock(&adev->firmware.mutex);
+ 
+ 	ret = psp_hw_start(psp);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+index 7dd9ae7dbbe4..09c5474ebcc3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+@@ -49,6 +49,8 @@ enum psp_bootloader_cmd {
+ 	PSP_BL__LOAD_SYSDRV		= 0x10000,
+ 	PSP_BL__LOAD_SOSDRV		= 0x20000,
+ 	PSP_BL__LOAD_KEY_DATABASE	= 0x80000,
++	PSP_BL__DRAM_LONG_TRAIN		= 0x100000,
++	PSP_BL__DRAM_SHORT_TRAIN	= 0x200000,
+ };
+ 
+ enum psp_ring_type
+@@ -111,6 +113,9 @@ struct psp_funcs
+ 			struct ta_ras_trigger_error_input *info);
+ 	int (*ras_cure_posion)(struct psp_context *psp, uint64_t *mode_ptr);
+ 	int (*rlc_autoload_start)(struct psp_context *psp);
++	int (*mem_training_init)(struct psp_context *psp);
++	void (*mem_training_fini)(struct psp_context *psp);
++	int (*mem_training)(struct psp_context *psp, uint32_t ops);
+ };
+ 
+ #define AMDGPU_XGMI_MAX_CONNECTED_NODES		64
+@@ -161,6 +166,49 @@ struct psp_dtm_context {
+ 	void			*dtm_shared_buf;
+ };
+ 
++#define MEM_TRAIN_SYSTEM_SIGNATURE		0x54534942
++#define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES	0x1000
++#define GDDR6_MEM_TRAINING_OFFSET		0x8000
++
++enum psp_memory_training_init_flag {
++	PSP_MEM_TRAIN_NOT_SUPPORT	= 0x0,
++	PSP_MEM_TRAIN_SUPPORT		= 0x1,
++	PSP_MEM_TRAIN_INIT_FAILED	= 0x2,
++	PSP_MEM_TRAIN_RESERVE_SUCCESS	= 0x4,
++	PSP_MEM_TRAIN_INIT_SUCCESS	= 0x8,
++};
++
++enum psp_memory_training_ops {
++	PSP_MEM_TRAIN_SEND_LONG_MSG	= 0x1,
++	PSP_MEM_TRAIN_SAVE		= 0x2,
++	PSP_MEM_TRAIN_RESTORE		= 0x4,
++	PSP_MEM_TRAIN_SEND_SHORT_MSG	= 0x8,
++	PSP_MEM_TRAIN_COLD_BOOT		= PSP_MEM_TRAIN_SEND_LONG_MSG,
++	PSP_MEM_TRAIN_RESUME		= PSP_MEM_TRAIN_SEND_SHORT_MSG,
++};
++
++struct psp_memory_training_context {
++	/*training data size*/
++	u64 train_data_size;
++	/*
++	 * sys_cache
++	 * cpu virtual address
++	 * system memory buffer that used to store the training data.
++	 */
++	void *sys_cache;
++
++	/*vram offset of the p2c training data*/
++	u64 p2c_train_data_offset;
++	struct amdgpu_bo *p2c_bo;
++
++	/*vram offset of the c2p training data*/
++	u64 c2p_train_data_offset;
++	struct amdgpu_bo *c2p_bo;
++
++	enum psp_memory_training_init_flag init;
++	u32 training_cnt;
++};
++
+ struct psp_context
+ {
+ 	struct amdgpu_device            *adev;
+@@ -239,6 +287,7 @@ struct psp_context
+ 	struct psp_hdcp_context 	hdcp_context;
+ 	struct psp_dtm_context		dtm_context;
+ 	struct mutex			mutex;
++	struct psp_memory_training_context mem_train_ctx;
+ };
+ 
+ struct amdgpu_psp_funcs {
+@@ -281,6 +330,12 @@ struct amdgpu_psp_funcs {
+ 		(psp)->funcs->xgmi_set_topology_info((psp), (num_device), (topology)) : -EINVAL)
+ #define psp_rlc_autoload(psp) \
+ 		((psp)->funcs->rlc_autoload_start ? (psp)->funcs->rlc_autoload_start((psp)) : 0)
++#define psp_mem_training_init(psp) \
++	((psp)->funcs->mem_training_init ? (psp)->funcs->mem_training_init((psp)) : 0)
++#define psp_mem_training_fini(psp) \
++	((psp)->funcs->mem_training_fini ? (psp)->funcs->mem_training_fini((psp)) : 0)
++#define psp_mem_training(psp, ops) \
++	((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
+ 
+ #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4212-drm-amdgpu-reserve-vram-for-memory-training-v4.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4212-drm-amdgpu-reserve-vram-for-memory-training-v4.patch
new file mode 100644
index 00000000..4c224e55
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4212-drm-amdgpu-reserve-vram-for-memory-training-v4.patch
@@ -0,0 +1,135 @@
+From eafe58cb56a6d67ea90e24de16257fdfab5a7e76 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Mon, 30 Sep 2019 14:28:17 +0800
+Subject: [PATCH 4212/4736] drm/amdgpu: reserve vram for memory training(v4)
+
+memory training using specific fixed vram segment, reserve these
+segments before anyone may allocate it.
+
+Change-Id: I9a37cd4f61b04ba1ca041a752bc16901488ac341
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 91 +++++++++++++++++++++++++
+ 1 file changed, 91 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 0c1af24f8bc0..968595138b32 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -1975,6 +1975,88 @@ static void amdgpu_ssg_fini(struct amdgpu_device *adev)
+ }
+ #endif
+ 
++/*
++ * Memoy training reservation functions
++ */
++
++/**
++ * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * free memory training reserved vram if it has been reserved.
++ */
++static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
++{
++	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
++
++	ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
++	amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
++	ctx->c2p_bo = NULL;
++
++	amdgpu_bo_free_kernel(&ctx->p2c_bo, NULL, NULL);
++	ctx->p2c_bo = NULL;
++
++	return 0;
++}
++
++/**
++ * amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from memory training
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * create bo vram reservation from memory training.
++ */
++static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device *adev)
++{
++	int ret;
++	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
++
++	memset(ctx, 0, sizeof(*ctx));
++	if (!adev->fw_vram_usage.mem_train_support) {
++		DRM_DEBUG("memory training does not support!\n");
++		return 0;
++	}
++
++	ctx->c2p_train_data_offset = adev->fw_vram_usage.mem_train_fb_loc;
++	ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
++	ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
++
++	DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
++		  ctx->train_data_size,
++		  ctx->p2c_train_data_offset,
++		  ctx->c2p_train_data_offset);
++
++	ret = amdgpu_bo_create_kernel_at(adev,
++					 ctx->p2c_train_data_offset,
++					 ctx->train_data_size,
++					 AMDGPU_GEM_DOMAIN_VRAM,
++					 &ctx->p2c_bo,
++					 NULL);
++	if (ret) {
++		DRM_ERROR("alloc p2c_bo failed(%d)!\n", ret);
++		goto Err_out;
++	}
++
++	ret = amdgpu_bo_create_kernel_at(adev,
++					 ctx->c2p_train_data_offset,
++					 ctx->train_data_size,
++					 AMDGPU_GEM_DOMAIN_VRAM,
++					 &ctx->c2p_bo,
++					 NULL);
++	if (ret) {
++		DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
++		goto Err_out;
++	}
++
++	ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
++	return 0;
++
++Err_out:
++	amdgpu_ttm_training_reserve_vram_fini(adev);
++	return ret;
++}
++
+ /**
+  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
+  * gtt/vram related fields.
+@@ -2053,6 +2135,14 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
+ 		return r;
+ 	}
+ 
++	/*
++	 *The reserved vram for memory training must be pinned to the specified
++	 *place on the VRAM, so reserve it early.
++	 */
++	r = amdgpu_ttm_training_reserve_vram_init(adev);
++	if (r)
++		return r;
++
+ 	/* allocate memory as required for VGA
+ 	 * This is used for VGA emulation and pre-OS scanout buffers to
+ 	 * avoid display artifacts while transitioning between pre-OS
+@@ -2160,6 +2250,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
+ 		return;
+ 
+ 	amdgpu_ttm_debugfs_fini(adev);
++	amdgpu_ttm_training_reserve_vram_fini(adev);
+ 	amdgpu_ttm_fw_reserve_vram_fini(adev);
+ 	if (adev->mman.aper_base_kaddr)
+ 		iounmap(adev->mman.aper_base_kaddr);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4213-drm-amdgpu-psp-add-psp-memory-training-implementatio.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4213-drm-amdgpu-psp-add-psp-memory-training-implementatio.patch
new file mode 100644
index 00000000..b6a6644f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4213-drm-amdgpu-psp-add-psp-memory-training-implementatio.patch
@@ -0,0 +1,246 @@
+From 7759546a09a7816345f83d60f9c04ec7ecda191a Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Mon, 30 Sep 2019 14:29:33 +0800
+Subject: [PATCH 4213/4736] drm/amdgpu/psp: add psp memory training
+ implementation(v3)
+
+add memory training implementation code to save resume time.
+
+Change-Id: Ib74fec65eb4db1f7343d5ff54e9169e3ade1a882
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h     |   1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |   9 ++
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c  | 161 ++++++++++++++++++++++++
+ 3 files changed, 171 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 8c5c1833aca7..f1f258a2790a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -156,6 +156,7 @@ extern char *amdgpu_disable_cu;
+ extern char *amdgpu_virtual_display;
+ extern uint amdgpu_pp_feature_mask;
+ extern int amdgpu_ssg_enabled;
++extern uint amdgpu_force_long_training;
+ extern int amdgpu_job_hang_limit;
+ extern int amdgpu_lbpw;
+ extern int amdgpu_compute_multipipe;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 5ab426726849..699cab407158 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -129,6 +129,7 @@ char *amdgpu_disable_cu = NULL;
+ char *amdgpu_virtual_display = NULL;
+ /* OverDrive(bit 14) disabled by default*/
+ uint amdgpu_pp_feature_mask = 0xffffbfff;
++uint amdgpu_force_long_training = 0;
+ int amdgpu_job_hang_limit = 0;
+ int amdgpu_lbpw = -1;
+ int amdgpu_compute_multipipe = -1;
+@@ -403,6 +404,14 @@ module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444);
+ MODULE_PARM_DESC(ssg, "SSG support (1 = enable, 0 = disable (default))");
+ module_param_named(ssg, amdgpu_ssg_enabled, int, 0444);
+ 
++/**
++ * DOC: forcelongtraining (uint)
++ * Force long memory training in resume.
++ * The default is zero, indicates short training in resume.
++ */
++MODULE_PARM_DESC(forcelongtraining, "force memory long training");
++module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
++
+ /**
+  * DOC: pcie_gen_cap (uint)
+  * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index b52af59079b7..0875ece1bea2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -57,6 +57,8 @@ MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
+ #define mmRLC_GPM_UCODE_DATA_NV10      0x5b62
+ #define mmSDMA0_UCODE_ADDR_NV10                0x5880
+ #define mmSDMA0_UCODE_DATA_NV10                0x5881
++/* memory training timeout define */
++#define MEM_TRAIN_SEND_MSG_TIMEOUT_US  3000000
+ 
+ #define VEGA20_BL_VERSION_VAR_NEW 0xA1
+ 
+@@ -918,6 +920,162 @@ static int psp_v11_0_rlc_autoload_start(struct psp_context *psp)
+         return psp_rlc_autoload_start(psp);
+ }
+ 
++static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
++{
++	int ret;
++	int i;
++	uint32_t data_32;
++	int max_wait;
++	struct amdgpu_device *adev = psp->adev;
++
++	data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
++	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32);
++	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg);
++
++	max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
++	for (i = 0; i < max_wait; i++) {
++		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
++				   0x80000000, 0x80000000, false);
++		if (ret == 0)
++			break;
++	}
++	if (i < max_wait)
++		ret = 0;
++	else
++		ret = -ETIME;
++
++	DRM_DEBUG("training %s %s, cost %d @ %d ms\n",
++		  (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
++		  (ret == 0) ? "succeed" : "failed",
++		  i, adev->usec_timeout/1000);
++	return ret;
++}
++
++static void psp_v11_0_memory_training_fini(struct psp_context *psp)
++{
++	struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
++
++	ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
++	kfree(ctx->sys_cache);
++	ctx->sys_cache = NULL;
++}
++
++static int psp_v11_0_memory_training_init(struct psp_context *psp)
++{
++	int ret;
++	struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
++
++	if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
++		DRM_DEBUG("memory training is not supported!\n");
++		return 0;
++	}
++
++	ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
++	if (ctx->sys_cache == NULL) {
++		DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
++		ret = -ENOMEM;
++		goto Err_out;
++	}
++
++	DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
++		  ctx->train_data_size,
++		  ctx->p2c_train_data_offset,
++		  ctx->c2p_train_data_offset);
++	ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
++	return 0;
++
++Err_out:
++	psp_v11_0_memory_training_fini(psp);
++	return ret;
++}
++
++/*
++ * save and restore proces
++ */
++static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
++{
++	int ret;
++	uint32_t p2c_header[4];
++	struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
++	uint32_t *pcache = (uint32_t*)ctx->sys_cache;
++
++	if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
++		DRM_DEBUG("Memory training is not supported.\n");
++		return 0;
++	} else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
++		DRM_ERROR("Memory training initialization failure.\n");
++		return -EINVAL;
++	}
++
++	if (psp_v11_0_is_sos_alive(psp)) {
++		DRM_DEBUG("SOS is alive, skip memory training.\n");
++		return 0;
++	}
++
++	amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
++	DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
++		  pcache[0], pcache[1], pcache[2], pcache[3],
++		  p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
++
++	if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
++		DRM_DEBUG("Short training depends on restore.\n");
++		ops |= PSP_MEM_TRAIN_RESTORE;
++	}
++
++	if ((ops & PSP_MEM_TRAIN_RESTORE) &&
++	    pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
++		DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n");
++		ops |= PSP_MEM_TRAIN_SAVE;
++	}
++
++	if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
++	    !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
++	      pcache[3] == p2c_header[3])) {
++		DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
++		ops |= PSP_MEM_TRAIN_SAVE;
++	}
++
++	if ((ops & PSP_MEM_TRAIN_SAVE) &&
++	    p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
++		DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n");
++		ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
++	}
++
++	if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
++		ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
++		ops |= PSP_MEM_TRAIN_SAVE;
++	}
++
++	DRM_DEBUG("Memory training ops:%x.\n", ops);
++
++	if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
++		ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
++		if (ret) {
++			DRM_ERROR("Send long training msg failed.\n");
++			return ret;
++		}
++	}
++
++	if (ops & PSP_MEM_TRAIN_SAVE) {
++		amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
++	}
++
++	if (ops & PSP_MEM_TRAIN_RESTORE) {
++		amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
++	}
++
++	if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
++		ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
++							 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
++		if (ret) {
++			DRM_ERROR("send training msg failed.\n");
++			return ret;
++		}
++	}
++	ctx->training_cnt++;
++	return 0;
++}
++
+ static const struct psp_funcs psp_v11_0_funcs = {
+ 	.init_microcode = psp_v11_0_init_microcode,
+ 	.bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
+@@ -938,6 +1096,9 @@ static const struct psp_funcs psp_v11_0_funcs = {
+ 	.ras_trigger_error = psp_v11_0_ras_trigger_error,
+ 	.ras_cure_posion = psp_v11_0_ras_cure_posion,
+ 	.rlc_autoload_start = psp_v11_0_rlc_autoload_start,
++	.mem_training_init = psp_v11_0_memory_training_init,
++	.mem_training_fini = psp_v11_0_memory_training_fini,
++	.mem_training = psp_v11_0_memory_training,
+ };
+ 
+ void psp_v11_0_set_psp_funcs(struct psp_context *psp)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4214-drm-amdgpu-fix-amdgpu-trace-event-print-string-forma.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4214-drm-amdgpu-fix-amdgpu-trace-event-print-string-forma.patch
new file mode 100644
index 00000000..9a278ecf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4214-drm-amdgpu-fix-amdgpu-trace-event-print-string-forma.patch
@@ -0,0 +1,114 @@
+From 650f26bbe12a83eb29debdd57b36bd20fde749e1 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Wed, 16 Oct 2019 10:51:32 +0800
+Subject: [PATCH 4214/4736] drm/amdgpu: fix amdgpu trace event print string
+ format error
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+the trace event print string format error.
+(use integer type to handle string)
+
+before:
+amdgpu_test_kev-1556  [002]   138.508781: amdgpu_cs_ioctl:
+sched_job=8, timeline=gfx_0.0.0, context=177, seqno=1,
+ring_name=ffff94d01c207bf0, num_ibs=2
+
+after:
+amdgpu_test_kev-1506  [004]   370.703783: amdgpu_cs_ioctl:
+sched_job=12, timeline=gfx_0.0.0, context=234, seqno=2,
+ring_name=gfx_0.0.0, num_ibs=1
+
+change trace event list:
+1.amdgpu_cs_ioctl
+2.amdgpu_sched_run_job
+3.amdgpu_ib_pipe_sync
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+index e9feb5a8fb9d..61d4bfa2f6cb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+@@ -172,7 +172,7 @@ TRACE_EVENT(amdgpu_cs_ioctl,
+ 			     __field(unsigned int, context)
+ 			     __field(unsigned int, seqno)
+ 			     __field(struct dma_fence *, fence)
+-			     __field(char *, ring_name)
++			     __string(ring, to_amdgpu_ring(job->base.sched)->name)
+ 			     __field(u32, num_ibs)
+ 			     ),
+ 
+@@ -181,12 +181,12 @@ TRACE_EVENT(amdgpu_cs_ioctl,
+ 			   __assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job))
+ 			   __entry->context = job->base.s_fence->finished.context;
+ 			   __entry->seqno = job->base.s_fence->finished.seqno;
+-			   __entry->ring_name = to_amdgpu_ring(job->base.sched)->name;
++			   __assign_str(ring, to_amdgpu_ring(job->base.sched)->name)
+ 			   __entry->num_ibs = job->num_ibs;
+ 			   ),
+ 	    TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u",
+ 		      __entry->sched_job_id, __get_str(timeline), __entry->context,
+-		      __entry->seqno, __entry->ring_name, __entry->num_ibs)
++		      __entry->seqno, __get_str(ring), __entry->num_ibs)
+ );
+ 
+ TRACE_EVENT(amdgpu_sched_run_job,
+@@ -197,7 +197,7 @@ TRACE_EVENT(amdgpu_sched_run_job,
+ 			     __string(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job))
+ 			     __field(unsigned int, context)
+ 			     __field(unsigned int, seqno)
+-			     __field(char *, ring_name)
++			     __string(ring, to_amdgpu_ring(job->base.sched)->name)
+ 			     __field(u32, num_ibs)
+ 			     ),
+ 
+@@ -206,12 +206,12 @@ TRACE_EVENT(amdgpu_sched_run_job,
+ 			   __assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job))
+ 			   __entry->context = job->base.s_fence->finished.context;
+ 			   __entry->seqno = job->base.s_fence->finished.seqno;
+-			   __entry->ring_name = to_amdgpu_ring(job->base.sched)->name;
++			   __assign_str(ring, to_amdgpu_ring(job->base.sched)->name)
+ 			   __entry->num_ibs = job->num_ibs;
+ 			   ),
+ 	    TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u",
+ 		      __entry->sched_job_id, __get_str(timeline), __entry->context,
+-		      __entry->seqno, __entry->ring_name, __entry->num_ibs)
++		      __entry->seqno, __get_str(ring), __entry->num_ibs)
+ );
+ 
+ 
+@@ -475,7 +475,7 @@ TRACE_EVENT(amdgpu_ib_pipe_sync,
+ 	    TP_PROTO(struct amdgpu_job *sched_job, struct dma_fence *fence),
+ 	    TP_ARGS(sched_job, fence),
+ 	    TP_STRUCT__entry(
+-			     __field(const char *,name)
++			     __string(ring, sched_job->base.sched->name);
+ 			     __field(uint64_t, id)
+ 			     __field(struct dma_fence *, fence)
+ 			     __field(uint64_t, ctx)
+@@ -483,14 +483,14 @@ TRACE_EVENT(amdgpu_ib_pipe_sync,
+ 			     ),
+ 
+ 	    TP_fast_assign(
+-			   __entry->name = sched_job->base.sched->name;
++			   __assign_str(ring, sched_job->base.sched->name)
+ 			   __entry->id = sched_job->base.id;
+ 			   __entry->fence = fence;
+ 			   __entry->ctx = fence->context;
+ 			   __entry->seqno = fence->seqno;
+ 			   ),
+ 	    TP_printk("job ring=%s, id=%llu, need pipe sync to fence=%p, context=%llu, seq=%u",
+-		      __entry->name, __entry->id,
++		      __get_str(ring), __entry->id,
+ 		      __entry->fence, __entry->ctx,
+ 		      __entry->seqno)
+ );
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4215-drm-amdgpu-disable-c-states-on-xgmi-perfmons.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4215-drm-amdgpu-disable-c-states-on-xgmi-perfmons.patch
new file mode 100644
index 00000000..d628013a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4215-drm-amdgpu-disable-c-states-on-xgmi-perfmons.patch
@@ -0,0 +1,121 @@
+From 18e07e3bc6419d1bb47aed0d7139d360982ca394 Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Wed, 16 Oct 2019 20:40:08 -0400
+Subject: [PATCH 4215/4736] drm/amdgpu: disable c-states on xgmi perfmons
+
+read or writes to df registers when gpu df is in c-states will result in
+hang.  df c-states should be disabled prior to read or writes then
+re-enabled after read or writes.
+
+Change-Id: I6d5a83e4fe13e29c73dfb03a94fe7c611e867fec
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+Reviewed-by: Evan Quan <Evan.Quan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 36 +++++++++++++++++++++++++++-
+ 1 file changed, 35 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+index 72bfefdbfa65..839a948d70de 100644
+--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
++++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+@@ -93,6 +93,21 @@ const struct attribute_group *df_v3_6_attr_groups[] = {
+ 		NULL
+ };
+ 
++static df_v3_6_set_df_cstate(struct amdgpu_device *adev, int allow)
++{
++	int r = 0;
++
++	if (is_support_sw_smu(adev)) {
++		r = smu_set_df_cstate(&adev->smu, allow);
++	} else if (adev->powerplay.pp_funcs
++			&& adev->powerplay.pp_funcs->set_df_cstate) {
++		r = adev->powerplay.pp_funcs->set_df_cstate(
++			adev->powerplay.pp_handle, allow);
++	}
++
++	return r;
++}
++
+ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
+ 				 uint32_t ficaa_val)
+ {
+@@ -102,6 +117,9 @@ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
+ 	address = adev->nbio.funcs->get_pcie_index_offset(adev);
+ 	data = adev->nbio.funcs->get_pcie_data_offset(adev);
+ 
++	if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
++		return 0xFFFFFFFFFFFFFFFF;
++
+ 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ 	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
+ 	WREG32(data, ficaa_val);
+@@ -114,6 +132,8 @@ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
+ 
+ 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+ 
++	df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
++
+ 	return (((ficadh_val & 0xFFFFFFFFFFFFFFFF) << 32) | ficadl_val);
+ }
+ 
+@@ -125,6 +145,9 @@ static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
+ 	address = adev->nbio.funcs->get_pcie_index_offset(adev);
+ 	data = adev->nbio.funcs->get_pcie_data_offset(adev);
+ 
++	if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
++		return;
++
+ 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ 	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
+ 	WREG32(data, ficaa_val);
+@@ -134,8 +157,9 @@ static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
+ 
+ 	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
+ 	WREG32(data, ficadh_val);
+-
+ 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
++
++	df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
+ }
+ 
+ /*
+@@ -153,12 +177,17 @@ static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev,
+ 	address = adev->nbio.funcs->get_pcie_index_offset(adev);
+ 	data = adev->nbio.funcs->get_pcie_data_offset(adev);
+ 
++	if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
++		return;
++
+ 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ 	WREG32(address, lo_addr);
+ 	*lo_val = RREG32(data);
+ 	WREG32(address, hi_addr);
+ 	*hi_val = RREG32(data);
+ 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
++
++	df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
+ }
+ 
+ /*
+@@ -175,12 +204,17 @@ static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr,
+ 	address = adev->nbio.funcs->get_pcie_index_offset(adev);
+ 	data = adev->nbio.funcs->get_pcie_data_offset(adev);
+ 
++	if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
++		return;
++
+ 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ 	WREG32(address, lo_addr);
+ 	WREG32(data, lo_val);
+ 	WREG32(address, hi_addr);
+ 	WREG32(data, hi_val);
+ 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
++
++	df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
+ }
+ 
+ /* get the number of df counters available */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4216-drm-amdgpu-psp-declare-PSP-TA-firmware.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4216-drm-amdgpu-psp-declare-PSP-TA-firmware.patch
new file mode 100644
index 00000000..66b4d571
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4216-drm-amdgpu-psp-declare-PSP-TA-firmware.patch
@@ -0,0 +1,30 @@
+From ab4a7e3256ba093a8d634dcac13ec33838227b5a Mon Sep 17 00:00:00 2001
+From: chen gong <curry.gong@amd.com>
+Date: Mon, 14 Oct 2019 18:27:11 +0800
+Subject: [PATCH 4216/4736] drm/amdgpu/psp: declare PSP TA firmware
+
+Add PSP TA firmware declaration for raven raven2 picasso
+
+Signed-off-by: chen gong <curry.gong@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+index f24760dab4e0..ed8beff02e62 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+@@ -37,6 +37,9 @@
+ MODULE_FIRMWARE("amdgpu/raven_asd.bin");
+ MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
+ MODULE_FIRMWARE("amdgpu/raven2_asd.bin");
++MODULE_FIRMWARE("amdgpu/picasso_ta.bin");
++MODULE_FIRMWARE("amdgpu/raven2_ta.bin");
++MODULE_FIRMWARE("amdgpu/raven_ta.bin");
+ 
+ static int psp_v10_0_init_microcode(struct psp_context *psp)
+ {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4217-drm-amdgpu-fix-compiler-warnings-for-df-perfmons.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4217-drm-amdgpu-fix-compiler-warnings-for-df-perfmons.patch
new file mode 100644
index 00000000..a75abf7c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4217-drm-amdgpu-fix-compiler-warnings-for-df-perfmons.patch
@@ -0,0 +1,39 @@
+From e83bffab9a34e2db3c19b25c2e5841fbb8c03e15 Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Thu, 17 Oct 2019 13:52:38 -0400
+Subject: [PATCH 4217/4736] drm/amdgpu: fix compiler warnings for df perfmons
+
+fixing compiler warnings in df v3.6 for c-state toggle and pmc count.
+
+Change-Id: I74f8f1eafccf523a89d60d005e3549235f75c6b8
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+Reviewed-by: Philip Yang <Philip.Yang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+index 839a948d70de..766615f8c0ba 100644
+--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
++++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+@@ -93,7 +93,7 @@ const struct attribute_group *df_v3_6_attr_groups[] = {
+ 		NULL
+ };
+ 
+-static df_v3_6_set_df_cstate(struct amdgpu_device *adev, int allow)
++static int df_v3_6_set_df_cstate(struct amdgpu_device *adev, int allow)
+ {
+ 	int r = 0;
+ 
+@@ -547,7 +547,7 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
+ 		      uint64_t config,
+ 		      uint64_t *count)
+ {
+-	uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
++	uint32_t lo_base_addr, hi_base_addr, lo_val = 0, hi_val = 0;
+ 	*count = 0;
+ 
+ 	switch (adev->asic_type) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4218-drm-amdgpu-vce-fix-allocation-size-in-enc-ring-test.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4218-drm-amdgpu-vce-fix-allocation-size-in-enc-ring-test.patch
new file mode 100644
index 00000000..4c72bc51
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4218-drm-amdgpu-vce-fix-allocation-size-in-enc-ring-test.patch
@@ -0,0 +1,106 @@
+From 44b1bc20a6e024c71c00dfd37c81c93a236ab858 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 17 Oct 2019 11:36:47 -0400
+Subject: [PATCH 4218/4736] drm/amdgpu/vce: fix allocation size in enc ring
+ test
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+We need to allocate a large enough buffer for the
+feedback buffer, otherwise the IB test can overwrite
+other memory.
+
+Reviewed-by: James Zhu<James.Zhu@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 20 +++++++++++++++-----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h |  1 +
+ 2 files changed, 16 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+index f7189e22f6b7..db545182d4bb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+@@ -429,13 +429,14 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
+  * Open up a stream for HW test
+  */
+ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
++			      struct amdgpu_bo *bo,
+ 			      struct dma_fence **fence)
+ {
+ 	const unsigned ib_size_dw = 1024;
+ 	struct amdgpu_job *job;
+ 	struct amdgpu_ib *ib;
+ 	struct dma_fence *f = NULL;
+-	uint64_t dummy;
++	uint64_t addr;
+ 	int i, r;
+ 
+ 	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+@@ -444,7 +445,7 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
+ 
+ 	ib = &job->ibs[0];
+ 
+-	dummy = ib->gpu_addr + 1024;
++	addr = amdgpu_bo_gpu_offset(bo);
+ 
+ 	/* stitch together an VCE create msg */
+ 	ib->length_dw = 0;
+@@ -476,8 +477,8 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
+ 
+ 	ib->ptr[ib->length_dw++] = 0x00000014; /* len */
+ 	ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
+-	ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+-	ib->ptr[ib->length_dw++] = dummy;
++	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
++	ib->ptr[ib->length_dw++] = addr;
+ 	ib->ptr[ib->length_dw++] = 0x00000001;
+ 
+ 	for (i = ib->length_dw; i < ib_size_dw; ++i)
+@@ -1110,13 +1111,20 @@ int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
+ int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+ {
+ 	struct dma_fence *fence = NULL;
++	struct amdgpu_bo *bo = NULL;
+ 	long r;
+ 
+ 	/* skip vce ring1/2 ib test for now, since it's not reliable */
+ 	if (ring != &ring->adev->vce.ring[0])
+ 		return 0;
+ 
+-	r = amdgpu_vce_get_create_msg(ring, 1, NULL);
++	r = amdgpu_bo_create_reserved(ring->adev, 512, PAGE_SIZE,
++				      AMDGPU_GEM_DOMAIN_VRAM,
++				      &bo, NULL, NULL);
++	if (r)
++		return r;
++
++	r = amdgpu_vce_get_create_msg(ring, 1, bo, NULL);
+ 	if (r)
+ 		goto error;
+ 
+@@ -1132,5 +1140,7 @@ int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+ 
+ error:
+ 	dma_fence_put(fence);
++	amdgpu_bo_unreserve(bo);
++	amdgpu_bo_unref(&bo);
+ 	return r;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
+index 30ea54dd9117..e802f7d9db0a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
+@@ -59,6 +59,7 @@ int amdgpu_vce_entity_init(struct amdgpu_device *adev);
+ int amdgpu_vce_suspend(struct amdgpu_device *adev);
+ int amdgpu_vce_resume(struct amdgpu_device *adev);
+ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
++			      struct amdgpu_bo *bo,
+ 			      struct dma_fence **fence);
+ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
+ 			       bool direct, struct dma_fence **fence);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4219-drm-amdgpu-vce-make-some-functions-static.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4219-drm-amdgpu-vce-make-some-functions-static.patch
new file mode 100644
index 00000000..c7b7bf5b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4219-drm-amdgpu-vce-make-some-functions-static.patch
@@ -0,0 +1,77 @@
+From 0303158fcca21d8a3fb6646e73fa1f32eed7d94e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 17 Oct 2019 11:41:13 -0400
+Subject: [PATCH 4219/4736] drm/amdgpu/vce: make some functions static
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+They are not used outside of the file they are defined in.
+
+Reviewed-by: James Zhu<James.Zhu@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 15 ++++++++++-----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h |  5 -----
+ 2 files changed, 10 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+index db545182d4bb..92aa3b1b34ce 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+@@ -80,6 +80,11 @@ MODULE_FIRMWARE(FIRMWARE_VEGA12);
+ MODULE_FIRMWARE(FIRMWARE_VEGA20);
+ 
+ static void amdgpu_vce_idle_work_handler(struct work_struct *work);
++static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
++				     struct amdgpu_bo *bo,
++				     struct dma_fence **fence);
++static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
++				      bool direct, struct dma_fence **fence);
+ 
+ /**
+  * amdgpu_vce_init - allocate memory, load vce firmware
+@@ -428,9 +433,9 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
+  *
+  * Open up a stream for HW test
+  */
+-int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
+-			      struct amdgpu_bo *bo,
+-			      struct dma_fence **fence)
++static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
++				     struct amdgpu_bo *bo,
++				     struct dma_fence **fence)
+ {
+ 	const unsigned ib_size_dw = 1024;
+ 	struct amdgpu_job *job;
+@@ -508,8 +513,8 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
+  *
+  * Close up a stream for HW test or if userspace failed to do so
+  */
+-int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
+-			       bool direct, struct dma_fence **fence)
++static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
++				      bool direct, struct dma_fence **fence)
+ {
+ 	const unsigned ib_size_dw = 1024;
+ 	struct amdgpu_job *job;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
+index e802f7d9db0a..d6d83a3ec803 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
+@@ -58,11 +58,6 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev);
+ int amdgpu_vce_entity_init(struct amdgpu_device *adev);
+ int amdgpu_vce_suspend(struct amdgpu_device *adev);
+ int amdgpu_vce_resume(struct amdgpu_device *adev);
+-int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
+-			      struct amdgpu_bo *bo,
+-			      struct dma_fence **fence);
+-int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
+-			       bool direct, struct dma_fence **fence);
+ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
+ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx);
+ int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4220-drm-amdgpu-vi-silence-an-uninitialized-variable-warn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4220-drm-amdgpu-vi-silence-an-uninitialized-variable-warn.patch
new file mode 100644
index 00000000..5fcd0074
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4220-drm-amdgpu-vi-silence-an-uninitialized-variable-warn.patch
@@ -0,0 +1,34 @@
+From 98b68ce2eed4d671b7c485352105b81a28fd5187 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Thu, 17 Oct 2019 12:12:16 +0300
+Subject: [PATCH 4220/4736] drm/amdgpu/vi: silence an uninitialized variable
+ warning
+
+Smatch complains that we need to initialized "*cap" otherwise it can
+lead to an uninitialized variable bug in the caller.  This seems like a
+reasonable warning and it doesn't hurt to silence it at least.
+
+drivers/gpu/drm/amd/amdgpu/vi.c:767 vi_asic_reset_method() error: uninitialized symbol 'baco_reset'.
+
+Fixes: 425db2553e43 ("drm/amdgpu: expose BACO interfaces to upper level from PP")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+index 83196b79edd5..f4ff15378e61 100644
+--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+@@ -1421,6 +1421,7 @@ static int pp_get_asic_baco_capability(void *handle, bool *cap)
+ {
+ 	struct pp_hwmgr *hwmgr = handle;
+ 
++	*cap = false;
+ 	if (!hwmgr)
+ 		return -EINVAL;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4221-drm-amdgpu-revert-calling-smu-msg-in-df-callbacks.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4221-drm-amdgpu-revert-calling-smu-msg-in-df-callbacks.patch
new file mode 100644
index 00000000..b8ea18d8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4221-drm-amdgpu-revert-calling-smu-msg-in-df-callbacks.patch
@@ -0,0 +1,133 @@
+From ded09343b5c1253376dca4acb97fa56e9eab2749 Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Fri, 18 Oct 2019 15:26:05 -0400
+Subject: [PATCH 4221/4736] drm/amdgpu: revert calling smu msg in df callbacks
+
+reverting the following changes:
+commit 7dd2eb31fcd5 ("drm/amdgpu: fix compiler warnings for df perfmons")
+commit 54275cd1649f ("drm/amdgpu: disable c-states on xgmi perfmons")
+
+perf events use spin-locks.  embedded smu messages have potential long
+response times and potentially deadlocks the system.
+
+Change-Id: Ic36c35a62dec116d0a2f5b69c22af4d414458679
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 38 ++--------------------------
+ 1 file changed, 2 insertions(+), 36 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+index 766615f8c0ba..72bfefdbfa65 100644
+--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
++++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+@@ -93,21 +93,6 @@ const struct attribute_group *df_v3_6_attr_groups[] = {
+ 		NULL
+ };
+ 
+-static int df_v3_6_set_df_cstate(struct amdgpu_device *adev, int allow)
+-{
+-	int r = 0;
+-
+-	if (is_support_sw_smu(adev)) {
+-		r = smu_set_df_cstate(&adev->smu, allow);
+-	} else if (adev->powerplay.pp_funcs
+-			&& adev->powerplay.pp_funcs->set_df_cstate) {
+-		r = adev->powerplay.pp_funcs->set_df_cstate(
+-			adev->powerplay.pp_handle, allow);
+-	}
+-
+-	return r;
+-}
+-
+ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
+ 				 uint32_t ficaa_val)
+ {
+@@ -117,9 +102,6 @@ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
+ 	address = adev->nbio.funcs->get_pcie_index_offset(adev);
+ 	data = adev->nbio.funcs->get_pcie_data_offset(adev);
+ 
+-	if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
+-		return 0xFFFFFFFFFFFFFFFF;
+-
+ 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ 	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
+ 	WREG32(data, ficaa_val);
+@@ -132,8 +114,6 @@ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
+ 
+ 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+ 
+-	df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
+-
+ 	return (((ficadh_val & 0xFFFFFFFFFFFFFFFF) << 32) | ficadl_val);
+ }
+ 
+@@ -145,9 +125,6 @@ static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
+ 	address = adev->nbio.funcs->get_pcie_index_offset(adev);
+ 	data = adev->nbio.funcs->get_pcie_data_offset(adev);
+ 
+-	if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
+-		return;
+-
+ 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ 	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
+ 	WREG32(data, ficaa_val);
+@@ -157,9 +134,8 @@ static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
+ 
+ 	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
+ 	WREG32(data, ficadh_val);
+-	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+ 
+-	df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
++	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+ }
+ 
+ /*
+@@ -177,17 +153,12 @@ static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev,
+ 	address = adev->nbio.funcs->get_pcie_index_offset(adev);
+ 	data = adev->nbio.funcs->get_pcie_data_offset(adev);
+ 
+-	if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
+-		return;
+-
+ 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ 	WREG32(address, lo_addr);
+ 	*lo_val = RREG32(data);
+ 	WREG32(address, hi_addr);
+ 	*hi_val = RREG32(data);
+ 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+-
+-	df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
+ }
+ 
+ /*
+@@ -204,17 +175,12 @@ static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr,
+ 	address = adev->nbio.funcs->get_pcie_index_offset(adev);
+ 	data = adev->nbio.funcs->get_pcie_data_offset(adev);
+ 
+-	if (df_v3_6_set_df_cstate(adev, DF_CSTATE_DISALLOW))
+-		return;
+-
+ 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+ 	WREG32(address, lo_addr);
+ 	WREG32(data, lo_val);
+ 	WREG32(address, hi_addr);
+ 	WREG32(data, hi_val);
+ 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+-
+-	df_v3_6_set_df_cstate(adev, DF_CSTATE_ALLOW);
+ }
+ 
+ /* get the number of df counters available */
+@@ -547,7 +513,7 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
+ 		      uint64_t config,
+ 		      uint64_t *count)
+ {
+-	uint32_t lo_base_addr, hi_base_addr, lo_val = 0, hi_val = 0;
++	uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
+ 	*count = 0;
+ 
+ 	switch (adev->asic_type) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4222-drm-amdgpu-psp-fix-spelling-mistake-initliaze-initia.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4222-drm-amdgpu-psp-fix-spelling-mistake-initliaze-initia.patch
new file mode 100644
index 00000000..07b3bd71
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4222-drm-amdgpu-psp-fix-spelling-mistake-initliaze-initia.patch
@@ -0,0 +1,30 @@
+From 4b98e703e6d18a4716e811c8373dee984821629a Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Fri, 18 Oct 2019 09:15:08 +0100
+Subject: [PATCH 4222/4736] drm/amdgpu/psp: fix spelling mistake "initliaze" ->
+ "initialize"
+
+There is a spelling mistake in a DRM_ERROR error message. Fix it.
+
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 64db0c8cee4c..f289a84363c4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -90,7 +90,7 @@ static int psp_sw_init(void *handle)
+ 
+ 	ret = psp_mem_training_init(psp);
+ 	if (ret) {
+-		DRM_ERROR("Failed to initliaze memory training!\n");
++		DRM_ERROR("Failed to initialize memory training!\n");
+ 		return ret;
+ 	}
+ 	ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4223-drm-amd-display-setting-the-DIG_MODE-to-the-correct-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4223-drm-amd-display-setting-the-DIG_MODE-to-the-correct-.patch
new file mode 100644
index 00000000..c51b4d98
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4223-drm-amd-display-setting-the-DIG_MODE-to-the-correct-.patch
@@ -0,0 +1,44 @@
+From ff90d9ae73aebf86db14dfe520031dd4226f3293 Mon Sep 17 00:00:00 2001
+From: Zhan liu <zhan.liu@amd.com>
+Date: Thu, 17 Oct 2019 14:55:56 -0400
+Subject: [PATCH 4223/4736] drm/amd/display: setting the DIG_MODE to the
+ correct value.
+
+[Why]
+This patch is for fixing Navi14 HDMI display pink screen issue.
+
+[How]
+Call stream->link->link_enc->funcs->setup twice. This is setting
+the DIG_MODE to the correct value after having been overridden by
+the call to transmitter control.
+
+Change-Id: Ie739e345753440280bfeecff0b0ac9fda09c5ed0
+Signed-off-by: Zhan liu <zhan.liu@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 5ce5db7818e4..ea50ba20dd68 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2840,6 +2840,15 @@ void core_link_enable_stream(
+ 					CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
+ 					COLOR_DEPTH_UNDEFINED);
+ 
++		/* This second call is needed to reconfigure the DIG
++		 * as a workaround for the incorrect value being applied
++		 * from transmitter control.
++		 */
++		if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
++			stream->link->link_enc->funcs->setup(
++				stream->link->link_enc,
++				pipe_ctx->stream->signal);
++
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 		if (pipe_ctx->stream->timing.flags.DSC) {
+ 			if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4224-drm-amd-display-Free-gamma-after-calculating-legacy-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4224-drm-amd-display-Free-gamma-after-calculating-legacy-.patch
new file mode 100644
index 00000000..ee892995
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4224-drm-amd-display-Free-gamma-after-calculating-legacy-.patch
@@ -0,0 +1,34 @@
+From 80f4743bc70ce2ebd516b8d5657ee5862f20d202 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Fri, 11 Oct 2019 12:26:10 -0400
+Subject: [PATCH 4224/4736] drm/amd/display: Free gamma after calculating
+ legacy transfer function
+
+[Why]
+We're leaking memory by not freeing the gamma used to calculate the
+transfer function for legacy gamma.
+
+[How]
+Release the gamma after we're done with it.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+index 5005eb07159e..2eb1313c0728 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+@@ -209,6 +209,7 @@ static int __set_legacy_tf(struct dc_transfer_func *func,
+         res = mod_color_calculate_regamma_params(func, gamma, true, has_rom,
+                                                  NULL);
+ 
++	dc_gamma_release(&gamma);
+         return res ? 0 : -ENOMEM;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4225-drm-amdgpu-powerplay-use-local-renoir-array-sizes-fo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4225-drm-amdgpu-powerplay-use-local-renoir-array-sizes-fo.patch
new file mode 100644
index 00000000..810e0d85
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4225-drm-amdgpu-powerplay-use-local-renoir-array-sizes-fo.patch
@@ -0,0 +1,49 @@
+From ea42425830d84635db15d611dcd1232b4400f5fa Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 17 Oct 2019 11:57:45 -0400
+Subject: [PATCH 4225/4736] drm/amdgpu/powerplay: use local renoir array sizes
+ for clock fetching
+
+To avoid walking past the end of the arrays since the PP_SMU
+defines don't match the renoir defines.
+
+Reviewed-by: Prike Liang <Prike.Liang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 953e347633ec..57930c9e22ff 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -427,22 +427,22 @@ static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks
+ 	if (!clock_table || !table)
+ 		return -EINVAL;
+ 
+-	for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) {
++	for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) {
+ 		clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq;
+ 		clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol;
+ 	}
+ 
+-	for (i = 0; i < PP_SMU_NUM_SOCCLK_DPM_LEVELS; i++) {
++	for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
+ 		clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq;
+ 		clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol;
+ 	}
+ 
+-	for (i = 0; i < PP_SMU_NUM_FCLK_DPM_LEVELS; i++) {
++	for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
+ 		clock_table->FClocks[i].Freq = table->FClocks[i].Freq;
+ 		clock_table->FClocks[i].Vol = table->FClocks[i].Vol;
+ 	}
+ 
+-	for (i = 0; i<  PP_SMU_NUM_MEMCLK_DPM_LEVELS; i++) {
++	for (i = 0; i<  NUM_MEMCLK_DPM_LEVELS; i++) {
+ 		clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq;
+ 		clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4226-drm-amd-powerplay-update-Arcturus-driver-smu-interfa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4226-drm-amd-powerplay-update-Arcturus-driver-smu-interfa.patch
new file mode 100644
index 00000000..d738d7f7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4226-drm-amd-powerplay-update-Arcturus-driver-smu-interfa.patch
@@ -0,0 +1,75 @@
+From 7f9d518d0ff5775839b5112e5f7d86bcafd5add2 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 18 Oct 2019 13:36:41 +0800
+Subject: [PATCH 4226/4736] drm/amd/powerplay: update Arcturus driver smu
+ interface XGMI link part
+
+To fit the latest SMU firmware.
+
+Change-Id: Ie34e6930577b7a6fe993273f213732696628b264
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ .../powerplay/inc/smu11_driver_if_arcturus.h  | 28 +++++++++++++------
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  2 +-
+ 2 files changed, 21 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+index 2248d682c462..886b9a21ebd8 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+@@ -423,18 +423,30 @@ typedef enum {
+ } PwrConfig_e;
+ 
+ typedef enum {
+-  XGMI_LINK_RATE_12 = 0,  // 12Gbps
+-  XGMI_LINK_RATE_16,      // 16Gbps
+-  XGMI_LINK_RATE_22,      // 22Gbps
+-  XGMI_LINK_RATE_25,      // 25Gbps
++  XGMI_LINK_RATE_2 = 2,    // 2Gbps
++  XGMI_LINK_RATE_4 = 4,    // 4Gbps
++  XGMI_LINK_RATE_8 = 8,    // 8Gbps
++  XGMI_LINK_RATE_12 = 12,  // 12Gbps
++  XGMI_LINK_RATE_16 = 16,  // 16Gbps
++  XGMI_LINK_RATE_17 = 17,  // 17Gbps
++  XGMI_LINK_RATE_18 = 18,  // 18Gbps
++  XGMI_LINK_RATE_19 = 19,  // 19Gbps
++  XGMI_LINK_RATE_20 = 20,  // 20Gbps
++  XGMI_LINK_RATE_21 = 21,  // 21Gbps
++  XGMI_LINK_RATE_22 = 22,  // 22Gbps
++  XGMI_LINK_RATE_23 = 23,  // 23Gbps
++  XGMI_LINK_RATE_24 = 24,  // 24Gbps
++  XGMI_LINK_RATE_25 = 25,  // 25Gbps
+   XGMI_LINK_RATE_COUNT
+ } XGMI_LINK_RATE_e;
+ 
+ typedef enum {
+-  XGMI_LINK_WIDTH_2 = 0, // x2
+-  XGMI_LINK_WIDTH_4,     // x4
+-  XGMI_LINK_WIDTH_8,     // x8
+-  XGMI_LINK_WIDTH_16,    // x16
++  XGMI_LINK_WIDTH_1 = 1,   // x1
++  XGMI_LINK_WIDTH_2 = 2,   // x2
++  XGMI_LINK_WIDTH_4 = 4,   // x4
++  XGMI_LINK_WIDTH_8 = 8,   // x8
++  XGMI_LINK_WIDTH_9 = 9,   // x9
++  XGMI_LINK_WIDTH_16 = 16, // x16
+   XGMI_LINK_WIDTH_COUNT
+ } XGMI_LINK_WIDTH_e;
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index e71f6fedf3c6..6b2a901492b2 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -27,7 +27,7 @@
+ 
+ #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
+ #define SMU11_DRIVER_IF_VERSION_VG20 0x13
+-#define SMU11_DRIVER_IF_VERSION_ARCT 0x0D
++#define SMU11_DRIVER_IF_VERSION_ARCT 0x0F
+ #define SMU11_DRIVER_IF_VERSION_NV10 0x33
+ #define SMU11_DRIVER_IF_VERSION_NV12 0x33
+ #define SMU11_DRIVER_IF_VERSION_NV14 0x34
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4227-drm-amd-display-Avoid-sending-abnormal-VSIF.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4227-drm-amd-display-Avoid-sending-abnormal-VSIF.patch
new file mode 100644
index 00000000..f90aad89
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4227-drm-amd-display-Avoid-sending-abnormal-VSIF.patch
@@ -0,0 +1,36 @@
+From dc2c0a3b42a09f7da9070d05ae16d97d15f2feec Mon Sep 17 00:00:00 2001
+From: Wayne Lin <Wayne.Lin@amd.com>
+Date: Mon, 21 Oct 2019 13:24:36 +0800
+Subject: [PATCH 4227/4736] drm/amd/display: Avoid sending abnormal VSIF
+
+[Why]
+While setting hdmi_vic, hv_frame.vic is not initialized and might
+assign a wrong value to hdmi_vic. Cause to send out VSIF with
+abnormal value.
+
+[How]
+Initialize hv_frame and avi_frame
+
+Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 70ca73d2a80b..b55dd3680581 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -3452,6 +3452,9 @@ static void fill_stream_properties_from_drm_display_mode(
+ 	struct hdmi_vendor_infoframe hv_frame;
+ 	struct hdmi_avi_infoframe avi_frame;
+ 
++	memset(&hv_frame, 0, sizeof(hv_frame));
++	memset(&avi_frame, 0, sizeof(avi_frame));
++
+ 	timing_out->h_border_left = 0;
+ 	timing_out->h_border_right = 0;
+ 	timing_out->v_border_top = 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4228-drm-amd-display-add-50us-buffer-as-WA-for-pstate-swi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4228-drm-amd-display-add-50us-buffer-as-WA-for-pstate-swi.patch
new file mode 100644
index 00000000..5d59357b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4228-drm-amd-display-add-50us-buffer-as-WA-for-pstate-swi.patch
@@ -0,0 +1,30 @@
+From 4f1c705d9a430f770150cfd26b8e929c19fe05e7 Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Thu, 19 Sep 2019 17:43:45 -0400
+Subject: [PATCH 4228/4736] drm/amd/display: add 50us buffer as WA for pstate
+ switch in active
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+index 649883777f62..6c6c486b774a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+@@ -2577,7 +2577,8 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
+ 			mode_lib->vba.MinActiveDRAMClockChangeMargin
+ 					+ mode_lib->vba.DRAMClockChangeLatency;
+ 
+-	if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
++	if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
++		mode_lib->vba.DRAMClockChangeWatermark += 25;
+ 		mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
+ 	} else {
+ 		if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4229-drm-amd-display-add-odm-visual-confirm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4229-drm-amd-display-add-odm-visual-confirm.patch
new file mode 100644
index 00000000..972ba138
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4229-drm-amd-display-add-odm-visual-confirm.patch
@@ -0,0 +1,92 @@
+From ba021ad1542c7c7c4e1739eb4b51d2288e729c43 Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Wed, 25 Sep 2019 09:46:38 -0400
+Subject: [PATCH 4229/4736] drm/amd/display: add odm visual confirm
+
+[why]
+Hard to determine if pipe combine is done with MPC or ODM
+
+[how]
+Add new visual confirm type, this will mark each MPCC tree
+with a different color
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h           |  1 +
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 25 +++++++++++++++++++
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.h    |  4 ++-
+ 3 files changed, 29 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 5967106826ca..b7e7181bad78 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -229,6 +229,7 @@ enum visual_confirm {
+ 	VISUAL_CONFIRM_DISABLE = 0,
+ 	VISUAL_CONFIRM_SURFACE = 1,
+ 	VISUAL_CONFIRM_HDR = 2,
++	VISUAL_CONFIRM_MPCTREE = 4,
+ };
+ 
+ enum dcc_option {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 6229a8ca0013..e237ec39d193 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1996,6 +1996,28 @@ static void dcn20_reset_hw_ctx_wrap(
+ 	}
+ }
+ 
++void dcn20_get_mpctree_visual_confirm_color(
++		struct pipe_ctx *pipe_ctx,
++		struct tg_color *color)
++{
++	const struct tg_color pipe_colors[6] = {
++			{MAX_TG_COLOR_VALUE, 0, 0}, // red
++			{MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, // yellow
++			{0, MAX_TG_COLOR_VALUE, 0}, // blue
++			{MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple
++			{0, 0, MAX_TG_COLOR_VALUE}, // green
++			{MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE * 2 / 3, 0}, // orange
++	};
++
++	struct pipe_ctx *top_pipe = pipe_ctx;
++
++	while (top_pipe->top_pipe) {
++		top_pipe = top_pipe->top_pipe;
++	}
++
++	*color = pipe_colors[top_pipe->pipe_idx];
++}
++
+ static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+@@ -2013,6 +2035,9 @@ static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
+ 		dcn10_get_surface_visual_confirm_color(
+ 				pipe_ctx, &blnd_cfg.black_color);
++	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
++		dcn20_get_mpctree_visual_confirm_color(
++				pipe_ctx, &blnd_cfg.black_color);
+ 	}
+ 
+ 	if (per_pixel_alpha)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+index 9dbc2effa4ea..3098f1049ed7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+@@ -109,5 +109,7 @@ bool dcn20_set_blend_lut(
+ 	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
+ bool dcn20_set_shaper_3dlut(
+ 	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
+-
++void dcn20_get_mpctree_visual_confirm_color(
++		struct pipe_ctx *pipe_ctx,
++		struct tg_color *color);
+ #endif /* __DC_HWSS_DCN20_H__ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4230-drm-amd-display-Add-unknown-clk-state.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4230-drm-amd-display-Add-unknown-clk-state.patch
new file mode 100644
index 00000000..19f913ee
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4230-drm-amd-display-Add-unknown-clk-state.patch
@@ -0,0 +1,100 @@
+From d7ca9f0278e03c1d90753feab813ac4661740c6d Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Thu, 26 Sep 2019 14:08:41 -0400
+Subject: [PATCH 4230/4736] drm/amd/display: Add unknown clk state.
+
+[Why]
+System hang during S0i3 if DP only connected due to clk is disabled when
+doing link training.
+During S0i3, clk is disabled while the clk state is updated when ini_hw
+called, and at the moment clk is still disabled which indicating a wrong
+state for next time trying to enable clk.
+
+[How]
+Add an unknown state and initialize it during int_hw, make sure enable clk
+command be sent to smu.
+
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c    | 16 ++++++++--------
+ .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c      |  2 +-
+ drivers/gpu/drm/amd/display/dc/dc.h              |  5 +++--
+ 3 files changed, 12 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index b647e0320e4b..6212b407cd01 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -114,22 +114,22 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
+ 	 */
+ 	if (safe_to_lower) {
+ 		/* check that we're not already in lower */
+-		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_OPTIMIZED) {
++		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
+ 
+ 			display_count = rn_get_active_display_cnt_wa(dc, context);
+ 			/* if we can go lower, go lower */
+ 			if (display_count == 0) {
+-				rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_OPTIMIZED);
++				rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
+ 				/* update power state */
+-				clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_OPTIMIZED;
++				clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
+ 			}
+ 		}
+ 	} else {
+-		/* check that we're not already in the normal state */
+-		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_NORMAL) {
+-			rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_NORMAL);
++		/* check that we're not already in D0 */
++		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
++			rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE);
+ 			/* update power state */
+-			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_NORMAL;
++			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
+ 		}
+ 	}
+ 
+@@ -393,7 +393,7 @@ void rn_init_clocks(struct clk_mgr *clk_mgr)
+ 	// Assumption is that boot state always supports pstate
+ 	clk_mgr->clks.p_state_change_support = true;
+ 	clk_mgr->clks.prev_p_state_change_support = true;
+-	clk_mgr->clks.pwr_state = DCN_PWR_STATE_NORMAL;
++	clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
+ }
+ 
+ static struct clk_mgr_funcs dcn21_funcs = {
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+index 5647fcf10717..cb7c0e8b7e1b 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+@@ -170,7 +170,7 @@ void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum
+ {
+ 	int disp_count;
+ 
+-	if (state == DCN_PWR_STATE_OPTIMIZED)
++	if (state == DCN_PWR_STATE_LOW_POWER)
+ 		disp_count = 0;
+ 	else
+ 		disp_count = 1;
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index b7e7181bad78..2e1d34882684 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -257,8 +257,9 @@ enum dtm_pstate{
+ };
+ 
+ enum dcn_pwr_state {
+-	DCN_PWR_STATE_OPTIMIZED = 0,
+-	DCN_PWR_STATE_NORMAL = 1
++	DCN_PWR_STATE_UNKNOWN = -1,
++	DCN_PWR_STATE_MISSION_MODE = 0,
++	DCN_PWR_STATE_LOW_POWER = 3,
+ };
+ 
+ /*
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4231-drm-amd-display-Don-t-use-optimized-gamma22-with-eet.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4231-drm-amd-display-Don-t-use-optimized-gamma22-with-eet.patch
new file mode 100644
index 00000000..07abae8c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4231-drm-amd-display-Don-t-use-optimized-gamma22-with-eet.patch
@@ -0,0 +1,101 @@
+From f4810baf1e8c60ea47c2ca238f8a5967fbbaa19d Mon Sep 17 00:00:00 2001
+From: Aidan Yang <Aidan.Yang@amd.com>
+Date: Wed, 25 Sep 2019 16:57:37 -0400
+Subject: [PATCH 4231/4736] drm/amd/display: Don't use optimized gamma22 with
+ eetf
+
+[why]
+Optimized gamma22 assumes fixed point distribution which is not true
+for eetf true.
+
+[how]
+Use long calculation for eetf.
+
+Signed-off-by: Aidan Yang <Aidan.Yang@amd.com>
+Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Acked-by: Reza Amini <Reza.Amini@amd.com>
+---
+ .../amd/display/modules/color/color_gamma.c   | 45 +++++++++++++++++--
+ 1 file changed, 41 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+index 19475cf5ab72..0accdae5e675 100644
+--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
++++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+@@ -370,7 +370,42 @@ static struct fixed31_32 translate_from_linear_space(
+ 		return dc_fixpt_mul(args->arg, args->a1);
+ }
+ 
+-static struct fixed31_32 calculate_gamma22(struct fixed31_32 arg)
++
++static struct fixed31_32 translate_from_linear_space_long(
++		struct translate_from_linear_space_args *args)
++{
++	const struct fixed31_32 one = dc_fixpt_from_int(1);
++
++	if (dc_fixpt_lt(one, args->arg))
++		return one;
++
++	if (dc_fixpt_le(args->arg, dc_fixpt_neg(args->a0)))
++		return dc_fixpt_sub(
++			args->a2,
++			dc_fixpt_mul(
++				dc_fixpt_add(
++					one,
++					args->a3),
++				dc_fixpt_pow(
++					dc_fixpt_neg(args->arg),
++					dc_fixpt_recip(args->gamma))));
++	else if (dc_fixpt_le(args->a0, args->arg))
++		return dc_fixpt_sub(
++			dc_fixpt_mul(
++				dc_fixpt_add(
++					one,
++					args->a3),
++				dc_fixpt_pow(
++						args->arg,
++					dc_fixpt_recip(args->gamma))),
++					args->a2);
++	else
++		return dc_fixpt_mul(
++			args->arg,
++			args->a1);
++}
++
++static struct fixed31_32 calculate_gamma22(struct fixed31_32 arg, bool use_eetf)
+ {
+ 	struct fixed31_32 gamma = dc_fixpt_from_fraction(22, 10);
+ 
+@@ -381,9 +416,13 @@ static struct fixed31_32 calculate_gamma22(struct fixed31_32 arg)
+ 	scratch_gamma_args.a3 = dc_fixpt_zero;
+ 	scratch_gamma_args.gamma = gamma;
+ 
++	if (use_eetf)
++		return translate_from_linear_space_long(&scratch_gamma_args);
++
+ 	return translate_from_linear_space(&scratch_gamma_args);
+ }
+ 
++
+ static struct fixed31_32 translate_to_linear_space(
+ 	struct fixed31_32 arg,
+ 	struct fixed31_32 a0,
+@@ -947,7 +986,7 @@ static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
+ 				if (dc_fixpt_lt(scaledX, dc_fixpt_zero))
+ 					output = dc_fixpt_zero;
+ 				else
+-					output = calculate_gamma22(scaledX);
++					output = calculate_gamma22(scaledX, use_eetf);
+ 
+ 				rgb->r = output;
+ 				rgb->g = output;
+@@ -2170,5 +2209,3 @@ bool  mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
+ rgb_degamma_alloc_fail:
+ 	return ret;
+ }
+-
+-
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4232-drm-amd-display-Remove-superfluous-assert.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4232-drm-amd-display-Remove-superfluous-assert.patch
new file mode 100644
index 00000000..8f43bc0d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4232-drm-amd-display-Remove-superfluous-assert.patch
@@ -0,0 +1,35 @@
+From f7fdc386484c1551024b4e8644f174bd85e2a33a Mon Sep 17 00:00:00 2001
+From: Jordan Lazare <Jordan.Lazare@amd.com>
+Date: Fri, 27 Sep 2019 14:39:01 -0400
+Subject: [PATCH 4232/4736] drm/amd/display: Remove superfluous assert
+
+[Why]
+For loop below the assert already checks for the number of instances to
+create. ASSERT is meaningless and causing spam.
+
+[How]
+dd
+
+Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
+Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 58678b679661..ac20d39ec8ce 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2942,8 +2942,6 @@ bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
+ 	int i;
+ 	uint32_t pipe_count = pool->res_cap->num_dwb;
+ 
+-	ASSERT(pipe_count > 0);
+-
+ 	for (i = 0; i < pipe_count; i++) {
+ 		struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
+ 						    GFP_KERNEL);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4233-drm-amd-display-remove-unused-code.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4233-drm-amd-display-remove-unused-code.patch
new file mode 100644
index 00000000..d015840c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4233-drm-amd-display-remove-unused-code.patch
@@ -0,0 +1,70 @@
+From 762b81f7f405abd6f034606910e7fe645b03c095 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Fri, 30 Aug 2019 16:58:29 -0400
+Subject: [PATCH 4233/4736] drm/amd/display: remove unused code
+
+Commit hints are unnecessary after front end programming redesign.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c              | 2 --
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 5 -----
+ drivers/gpu/drm/amd/display/dc/inc/core_types.h       | 4 ----
+ 3 files changed, 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 699a215ca8ce..bd623404772d 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1245,8 +1245,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ 	for (i = 0; i < context->stream_count; i++)
+                 context->streams[i]->mode_changed = false;
+ 
+-	memset(&context->commit_hints, 0, sizeof(context->commit_hints));
+-
+ 	dc_release_state(dc->current_state);
+ 
+ 	dc->current_state = context;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index ac20d39ec8ce..c60f8e538cef 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2304,7 +2304,6 @@ bool dcn20_fast_validate_bw(
+ 	int split_threshold = dc->res_pool->pipe_count / 2;
+ 	bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
+ 
+-
+ 	ASSERT(pipes);
+ 	if (!pipes)
+ 		return false;
+@@ -2382,10 +2381,6 @@ bool dcn20_fast_validate_bw(
+ 	if (vlevel > context->bw_ctx.dml.soc.num_states)
+ 		goto validate_fail;
+ 
+-	if ((context->stream_count > split_threshold && dc->current_state->stream_count <= split_threshold)
+-		|| (context->stream_count <= split_threshold && dc->current_state->stream_count > split_threshold))
+-		context->commit_hints.full_update_needed = true;
+-
+ 	/*initialize pipe_just_split_from to invalid idx*/
+ 	for (i = 0; i < MAX_PIPES; i++)
+ 		pipe_split_from[i] = -1;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index eee78a73d88c..a831079607cd 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -398,10 +398,6 @@ struct dc_state {
+ 
+ 	struct clk_mgr *clk_mgr;
+ 
+-	struct {
+-		bool full_update_needed : 1;
+-	} commit_hints;
+-
+ 	struct kref refcount;
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4234-drm-amd-display-3.2.55.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4234-drm-amd-display-3.2.55.patch
new file mode 100644
index 00000000..34f6be5f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4234-drm-amd-display-3.2.55.patch
@@ -0,0 +1,27 @@
+From 367f8878c378a314902e46420270dccc5ce7e0f9 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Sat, 28 Sep 2019 15:57:53 -0400
+Subject: [PATCH 4234/4736] drm/amd/display: 3.2.55
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 2e1d34882684..a86dad3808b6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.54"
++#define DC_VER "3.2.55"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4235-drm-amd-display-Add-debugfs-entry-for-reading-psr-st.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4235-drm-amd-display-Add-debugfs-entry-for-reading-psr-st.patch
new file mode 100644
index 00000000..4168b65b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4235-drm-amd-display-Add-debugfs-entry-for-reading-psr-st.patch
@@ -0,0 +1,225 @@
+From 9f74b4bb1486008f7a9eb18a165ceae1c87a22f6 Mon Sep 17 00:00:00 2001
+From: Roman Li <Roman.Li@amd.com>
+Date: Fri, 30 Aug 2019 10:44:48 -0400
+Subject: [PATCH 4235/4736] drm/amd/display: Add debugfs entry for reading psr
+ state
+
+[Why]
+For upcoming PSR stupport it's useful to have debug entry
+to verify psr state.
+
+[How]
+ - Enable psr dc api for Linux
+ - Add psr_state file to eDP connector debugfs
+usage e.g.: cat /sys/kernel/debug/dri/0/DP-1/psr_state
+
+Signed-off-by: Roman Li <Roman.Li@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |  21 +++
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 149 ++++++++++++++++++
+ 2 files changed, 170 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+index 1f1ed64dd78d..2bb1fae452d9 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+@@ -968,6 +968,25 @@ static int force_yuv420_output_get(void *data, u64 *val)
+ DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
+ 			 force_yuv420_output_set, "%llu\n");
+ 
++/*
++ *  Read PSR state
++ */
++static int psr_get(void *data, u64 *val)
++{
++	struct amdgpu_dm_connector *connector = data;
++	struct dc_link *link = connector->dc_link;
++	uint32_t psr_state = 0;
++
++	dc_link_get_psr_state(link, &psr_state);
++
++	*val = psr_state;
++
++	return 0;
++}
++
++
++DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
++
+ void connector_debugfs_init(struct amdgpu_dm_connector *connector)
+ {
+ 	int i;
+@@ -981,6 +1000,8 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector)
+ 					    dp_debugfs_entries[i].fops);
+ 		}
+ 	}
++	if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
++		debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
+ 
+ 	debugfs_create_file_unsafe("force_yuv420_output", 0644, dir, connector,
+ 				   &force_yuv420_output_fops);
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index ea50ba20dd68..84813ef735c1 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2434,6 +2434,155 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool
+ 	return true;
+ }
+ 
++bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state)
++{
++	struct dc  *core_dc = link->ctx->dc;
++	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++
++	if (dmcu != NULL && link->psr_feature_enabled)
++		dmcu->funcs->get_psr_state(dmcu, psr_state);
++
++	return true;
++}
++
++bool dc_link_setup_psr(struct dc_link *link,
++		const struct dc_stream_state *stream, struct psr_config *psr_config,
++		struct psr_context *psr_context)
++{
++	struct dc *core_dc;
++	struct dmcu *dmcu;
++	int i;
++	/* updateSinkPsrDpcdConfig*/
++	union dpcd_psr_configuration psr_configuration;
++
++	psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
++
++	if (!link)
++		return false;
++
++	core_dc = link->ctx->dc;
++	dmcu = core_dc->res_pool->dmcu;
++
++	if (!dmcu)
++		return false;
++
++
++	memset(&psr_configuration, 0, sizeof(psr_configuration));
++
++	psr_configuration.bits.ENABLE                    = 1;
++	psr_configuration.bits.CRC_VERIFICATION          = 1;
++	psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
++			psr_config->psr_frame_capture_indication_req;
++
++	/* Check for PSR v2*/
++	if (psr_config->psr_version == 0x2) {
++		/* For PSR v2 selective update.
++		 * Indicates whether sink should start capturing
++		 * immediately following active scan line,
++		 * or starting with the 2nd active scan line.
++		 */
++		psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
++		/*For PSR v2, determines whether Sink should generate
++		 * IRQ_HPD when CRC mismatch is detected.
++		 */
++		psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
++	}
++
++	dm_helpers_dp_write_dpcd(
++		link->ctx,
++		link,
++		368,
++		&psr_configuration.raw,
++		sizeof(psr_configuration.raw));
++
++	psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
++	psr_context->transmitterId = link->link_enc->transmitter;
++	psr_context->engineId = link->link_enc->preferred_engine;
++
++	for (i = 0; i < MAX_PIPES; i++) {
++		if (core_dc->current_state->res_ctx.pipe_ctx[i].stream
++				== stream) {
++			/* dmcu -1 for all controller id values,
++			 * therefore +1 here
++			 */
++			psr_context->controllerId =
++				core_dc->current_state->res_ctx.
++				pipe_ctx[i].stream_res.tg->inst + 1;
++			break;
++		}
++	}
++
++	/* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
++	psr_context->phyType = PHY_TYPE_UNIPHY;
++	/*PhyId is associated with the transmitter id*/
++	psr_context->smuPhyId = link->link_enc->transmitter;
++
++	psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
++	psr_context->vsyncRateHz = div64_u64(div64_u64((stream->
++					timing.pix_clk_100hz * 100),
++					stream->timing.v_total),
++					stream->timing.h_total);
++
++	psr_context->psrSupportedDisplayConfig = true;
++	psr_context->psrExitLinkTrainingRequired =
++		psr_config->psr_exit_link_training_required;
++	psr_context->sdpTransmitLineNumDeadline =
++		psr_config->psr_sdp_transmit_line_num_deadline;
++	psr_context->psrFrameCaptureIndicationReq =
++		psr_config->psr_frame_capture_indication_req;
++
++	psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
++
++	psr_context->numberOfControllers =
++			link->dc->res_pool->timing_generator_count;
++
++	psr_context->rfb_update_auto_en = true;
++
++	/* 2 frames before enter PSR. */
++	psr_context->timehyst_frames = 2;
++	/* half a frame
++	 * (units in 100 lines, i.e. a value of 1 represents 100 lines)
++	 */
++	psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
++	psr_context->aux_repeats = 10;
++
++	psr_context->psr_level.u32all = 0;
++
++#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
++	/*skip power down the single pipe since it blocks the cstate*/
++	if (ASICREV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))
++		psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
++#endif
++
++	/* SMU will perform additional powerdown sequence.
++	 * For unsupported ASICs, set psr_level flag to skip PSR
++	 *  static screen notification to SMU.
++	 *  (Always set for DAL2, did not check ASIC)
++	 */
++	psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
++
++	/* Complete PSR entry before aborting to prevent intermittent
++	 * freezes on certain eDPs
++	 */
++	psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
++
++	/* Controls additional delay after remote frame capture before
++	 * continuing power down, default = 0
++	 */
++	psr_context->frame_delay = 0;
++
++	link->psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
++
++	/* psr_enabled == 0 indicates setup_psr did not succeed, but this
++	 * should not happen since firmware should be running at this point
++	 */
++	if (link->psr_feature_enabled == 0)
++		ASSERT(0);
++
++	return true;
++
++}
++
+ const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
+ {
+ 	return &link->link_status;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4236-drm-amd-display-Enable-PSR.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4236-drm-amd-display-Enable-PSR.patch
new file mode 100644
index 00000000..7983bd1a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4236-drm-amd-display-Enable-PSR.patch
@@ -0,0 +1,229 @@
+From a8ee241de4c89b32b586e89e150b1471714b6ffa Mon Sep 17 00:00:00 2001
+From: Roman Li <Roman.Li@amd.com>
+Date: Fri, 20 Sep 2019 19:03:17 -0400
+Subject: [PATCH 4236/4736] drm/amd/display: Enable PSR
+
+[Why]
+PSR (Panel Self-Refresh) is a power-saving feature for eDP panels.
+The feature has support in DMCU (Display MicroController Unit).
+DMCU/driver communication is implemented in DC.
+DM can use existing DC PSR interface to use PSR feature.
+
+[How]
+- Read psr caps via dpcd
+- Send vsc infoframe if panel supports psr
+- Disable psr before h/w programming (FULL_UPDATE)
+- Enable psr after h/w programming
+- Disable psr for fb console
+
+Change-Id: Ic52045fc6c68d66d744b1bdd99f14274f69322c6
+Signed-off-by: Roman Li <Roman.Li@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 133 +++++++++++++++++-
+ 1 file changed, 130 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index b55dd3680581..8139cffd5b88 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -146,6 +146,12 @@ static void prepare_flip_isr(struct amdgpu_crtc *acrtc);
+ static void handle_cursor_update(struct drm_plane *plane,
+ 				 struct drm_plane_state *old_plane_state);
+ 
++static void amdgpu_dm_set_psr_caps(struct dc_link *link);
++static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
++static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
++static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
++
++
+ /*
+  * dm_vblank_get_counter
+  *
+@@ -2400,6 +2406,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
+ 		} else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
+ 			amdgpu_dm_update_connector_after_detect(aconnector);
+ 			register_backlight_device(dm, link);
++			amdgpu_dm_set_psr_caps(link);
+ 		}
+ 
+ 
+@@ -3799,7 +3806,16 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ 
+ 	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
+ 		mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket, false, false);
++	if (stream->link->psr_feature_enabled)	{
++		struct dc  *core_dc = stream->link->ctx->dc;
+ 
++		if (dc_is_dmcu_initialized(core_dc)) {
++			struct dmcu *dmcu = core_dc->res_pool->dmcu;
++
++			stream->psr_version = dmcu->dmcu_version.psr_version;
++			mod_build_vsc_infopacket(stream, &stream->vsc_infopacket);
++		}
++	}
+ finish:
+ 	dc_sink_release(sink);
+ 
+@@ -5782,6 +5798,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
+ 	uint32_t target_vblank, last_flip_vblank;
+ 	bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
+ 	bool pflip_present = false;
++	bool swizzle = true;
+ 	struct {
+ 		struct dc_surface_update surface_updates[MAX_SURFACES];
+ 		struct dc_plane_info plane_infos[MAX_SURFACES];
+@@ -5827,6 +5844,9 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
+ 
+ 		dc_plane = dm_new_plane_state->dc_state;
+ 
++		if (dc_plane && !dc_plane->tiling_info.gfx9.swizzle)
++			swizzle = false;
++
+ 		bundle->surface_updates[planes_count].surface = dc_plane;
+ 		if (new_pcrtc_state->color_mgmt_changed) {
+ 			bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
+@@ -6017,14 +6037,29 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
+ 				&acrtc_state->vrr_params.adjust);
+ 			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
+ 		}
+-
+ 		mutex_lock(&dm->dc_lock);
++		if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
++				acrtc_state->stream->link->psr_allow_active)
++			amdgpu_dm_psr_disable(acrtc_state->stream);
++
+ 		dc_commit_updates_for_stream(dm->dc,
+ 						     bundle->surface_updates,
+ 						     planes_count,
+ 						     acrtc_state->stream,
+ 						     &bundle->stream_update,
+ 						     dc_state);
++
++		if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
++						acrtc_state->stream->psr_version &&
++						!acrtc_state->stream->link->psr_feature_enabled)
++			amdgpu_dm_link_setup_psr(acrtc_state->stream);
++		else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) &&
++						acrtc_state->stream->link->psr_feature_enabled &&
++						!acrtc_state->stream->link->psr_allow_active &&
++						swizzle) {
++			amdgpu_dm_psr_enable(acrtc_state->stream);
++		}
++
+ 		mutex_unlock(&dm->dc_lock);
+ 	}
+ 
+@@ -6329,10 +6364,13 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
+ 			crtc->hwmode = new_crtc_state->mode;
+ 		} else if (modereset_required(new_crtc_state)) {
+ 			DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
+-
+ 			/* i.e. reset mode */
+-			if (dm_old_crtc_state->stream)
++			if (dm_old_crtc_state->stream) {
++				if (dm_old_crtc_state->stream->link->psr_allow_active)
++					amdgpu_dm_psr_disable(dm_old_crtc_state->stream);
++
+ 				remove_stream(adev, acrtc, dm_old_crtc_state->stream);
++			}
+ 		}
+ 	} /* for_each_crtc_in_state() */
+ 
+@@ -7688,3 +7726,92 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
+                                                        freesync_capable);
+ }
+ 
++static void amdgpu_dm_set_psr_caps(struct dc_link *link)
++{
++	uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE];
++
++	if (!(link->connector_signal & SIGNAL_TYPE_EDP))
++		return;
++	if (link->type == dc_connection_none)
++		return;
++	if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT,
++					dpcd_data, sizeof(dpcd_data))) {
++		link->psr_feature_enabled = dpcd_data[0] ? true:false;
++		DRM_INFO("PSR support:%d\n", link->psr_feature_enabled);
++	}
++}
++
++/*
++ * amdgpu_dm_link_setup_psr() - configure psr link
++ * @stream: stream state
++ *
++ * Return: true if success
++ */
++static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
++{
++	struct dc_link *link = NULL;
++	struct psr_config psr_config = {0};
++	struct psr_context psr_context = {0};
++	struct dc *dc = NULL;
++	bool ret = false;
++
++	if (stream == NULL)
++		return false;
++
++	link = stream->link;
++	dc = link->ctx->dc;
++
++	psr_config.psr_version = dc->res_pool->dmcu->dmcu_version.psr_version;
++
++	if (psr_config.psr_version > 0) {
++		psr_config.psr_exit_link_training_required = 0x1;
++		psr_config.psr_frame_capture_indication_req = 0;
++		psr_config.psr_rfb_setup_time = 0x37;
++		psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
++		psr_config.allow_smu_optimizations = 0x0;
++
++		ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
++
++	}
++	DRM_DEBUG_DRIVER("PSR link: %d\n",	link->psr_feature_enabled);
++
++	return ret;
++}
++
++/*
++ * amdgpu_dm_psr_enable() - enable psr f/w
++ * @stream: stream state
++ *
++ * Return: true if success
++ */
++bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
++{
++	struct dc_link *link = stream->link;
++	struct dc_static_screen_events triggers = {0};
++
++	DRM_DEBUG_DRIVER("Enabling psr...\n");
++
++	triggers.cursor_update = true;
++	triggers.overlay_update = true;
++	triggers.surface_update = true;
++
++	dc_stream_set_static_screen_events(link->ctx->dc,
++					   &stream, 1,
++					   &triggers);
++
++	return dc_link_set_psr_allow_active(link, true, false);
++}
++
++/*
++ * amdgpu_dm_psr_disable() - disable psr f/w
++ * @stream:  stream state
++ *
++ * Return: true if success
++ */
++static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
++{
++
++	DRM_DEBUG_DRIVER("Disabling psr...\n");
++
++	return dc_link_set_psr_allow_active(stream->link, false, true);
++}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4237-drm-amd-display-correctly-populate-dpp-refclk-in-fpg.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4237-drm-amd-display-correctly-populate-dpp-refclk-in-fpg.patch
new file mode 100644
index 00000000..cbf9be13
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4237-drm-amd-display-correctly-populate-dpp-refclk-in-fpg.patch
@@ -0,0 +1,58 @@
+From c1457d444d163b12fd5457314507acce75f9a34a Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Fri, 27 Sep 2019 10:52:15 -0400
+Subject: [PATCH 4237/4736] drm/amd/display: correctly populate dpp refclk in
+ fpga
+
+[Why]
+In diags environment we are not programming the DPP DTO
+correctly.
+
+[How]
+Populate the dpp refclk in dccg so it can be used to correctly
+program DPP DTO.
+
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c   | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index ecd2cb4840e3..69daddbfbf29 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -260,6 +260,8 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
+ 		struct dc_state *context,
+ 		bool safe_to_lower)
+ {
++	struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
++
+ 	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
+ 	/* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
+ 	int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
+@@ -297,14 +299,18 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
+ 		clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
+ 	}
+ 
+-	/* Both fclk and dppclk ref are run on the same scemi clock so we
+-	 * need to keep the same value for both
++	/* Both fclk and ref_dppclk run on the same scemi clock.
++	 * So take the higher value since the DPP DTO is typically programmed
++	 * such that max dppclk is 1:1 with ref_dppclk.
+ 	 */
+ 	if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
+ 		clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
+ 	if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
+ 		clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
+ 
++	// Both fclk and ref_dppclk run on the same scemi clock.
++	clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
++
+ 	dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4238-drm-amd-display-split-dcn20-fast-validate-into-more-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4238-drm-amd-display-split-dcn20-fast-validate-into-more-.patch
new file mode 100644
index 00000000..32ace21b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4238-drm-amd-display-split-dcn20-fast-validate-into-more-.patch
@@ -0,0 +1,373 @@
+From 5552d85b5ad24d5fa12a61d5d8e500f880a2e36d Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Mon, 23 Sep 2019 12:56:20 -0400
+Subject: [PATCH 4238/4736] drm/amd/display: split dcn20 fast validate into
+ more functions
+
+Split a large function into smaller, reusable chunks.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 182 ++++++++++--------
+ .../drm/amd/display/dc/dcn20/dcn20_resource.h |  31 +++
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c |   1 +
+ 3 files changed, 136 insertions(+), 78 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index c60f8e538cef..2ea4879b834f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1641,7 +1641,7 @@ static void swizzle_to_dml_params(
+ 	}
+ }
+ 
+-static bool dcn20_split_stream_for_odm(
++bool dcn20_split_stream_for_odm(
+ 		struct resource_context *res_ctx,
+ 		const struct resource_pool *pool,
+ 		struct pipe_ctx *prev_odm_pipe,
+@@ -1719,7 +1719,7 @@ static bool dcn20_split_stream_for_odm(
+ 	return true;
+ }
+ 
+-static void dcn20_split_stream_for_mpc(
++void dcn20_split_stream_for_mpc(
+ 		struct resource_context *res_ctx,
+ 		const struct resource_pool *pool,
+ 		struct pipe_ctx *primary_pipe,
+@@ -2177,7 +2177,7 @@ void dcn20_set_mcif_arb_params(
+ }
+ 
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+-static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
++bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
+ {
+ 	int i;
+ 
+@@ -2212,7 +2212,7 @@ static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
+ }
+ #endif
+ 
+-static struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
++struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
+ 		struct resource_context *res_ctx,
+ 		const struct resource_pool *pool,
+ 		const struct pipe_ctx *primary_pipe)
+@@ -2289,24 +2289,11 @@ static struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
+ 	return secondary_pipe;
+ }
+ 
+-bool dcn20_fast_validate_bw(
++void dcn20_merge_pipes_for_validate(
+ 		struct dc *dc,
+-		struct dc_state *context,
+-		display_e2e_pipe_params_st *pipes,
+-		int *pipe_cnt_out,
+-		int *pipe_split_from,
+-		int *vlevel_out)
++		struct dc_state *context)
+ {
+-	bool out = false;
+-
+-	int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
+-	bool force_split = false;
+-	int split_threshold = dc->res_pool->pipe_count / 2;
+-	bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
+-
+-	ASSERT(pipes);
+-	if (!pipes)
+-		return false;
++	int i;
+ 
+ 	/* merge previously split odm pipes since mode support needs to make the decision */
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+@@ -2361,31 +2348,18 @@ bool dcn20_fast_validate_bw(
+ 		if (pipe->plane_state)
+ 			resource_build_scaling_params(pipe);
+ 	}
++}
+ 
+-	if (dc->res_pool->funcs->populate_dml_pipes)
+-		pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
+-			&context->res_ctx, pipes);
+-	else
+-		pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
+-			&context->res_ctx, pipes);
+-
+-	*pipe_cnt_out = pipe_cnt;
+-
+-	if (!pipe_cnt) {
+-		out = true;
+-		goto validate_out;
+-	}
+-
+-	vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
+-
+-	if (vlevel > context->bw_ctx.dml.soc.num_states)
+-		goto validate_fail;
+-
+-	/*initialize pipe_just_split_from to invalid idx*/
+-	for (i = 0; i < MAX_PIPES; i++)
+-		pipe_split_from[i] = -1;
++int dcn20_validate_apply_pipe_split_flags(
++		struct dc *dc,
++		struct dc_state *context,
++		int vlevel,
++		bool *split)
++{
++	int i, pipe_idx, vlevel_unsplit;
++	bool force_split = false;
++	bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
+ 
+-	/* Single display only conditionals get set here */
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ 		bool exit_loop = false;
+@@ -2412,38 +2386,105 @@ bool dcn20_fast_validate_bw(
+ 		if (exit_loop)
+ 			break;
+ 	}
+-
+-	if (context->stream_count > split_threshold)
++	/* TODO: fix dc bugs and remove this split threshold thing */
++	if (context->stream_count > dc->res_pool->pipe_count / 2)
+ 		avoid_split = true;
+ 
+-	vlevel_unsplit = vlevel;
++	if (avoid_split) {
++		for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
++			if (!context->res_ctx.pipe_ctx[i].stream)
++				continue;
++
++			for (vlevel_unsplit = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
++				if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1)
++					break;
++			/* Impossible to not split this pipe */
++			if (vlevel == context->bw_ctx.dml.soc.num_states)
++				vlevel = vlevel_unsplit;
++			pipe_idx++;
++		}
++		context->bw_ctx.dml.vba.maxMpcComb = 0;
++	}
++
+ 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
++		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
++
+ 		if (!context->res_ctx.pipe_ctx[i].stream)
+ 			continue;
+-		for (; vlevel_unsplit <= context->bw_ctx.dml.soc.num_states; vlevel_unsplit++)
+-			if (context->bw_ctx.dml.vba.NoOfDPP[vlevel_unsplit][0][pipe_idx] == 1)
+-				break;
++
++		if (force_split || context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] > 1)
++			split[i] = true;
++		if ((pipe->stream->view_format ==
++				VIEW_3D_FORMAT_SIDE_BY_SIDE ||
++				pipe->stream->view_format ==
++				VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
++				(pipe->stream->timing.timing_3d_format ==
++				TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
++				 pipe->stream->timing.timing_3d_format ==
++				TIMING_3D_FORMAT_SIDE_BY_SIDE))
++			split[i] = true;
++		if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
++			split[i] = true;
++			context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;
++		}
++		context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]
++			= context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
++		/* Adjust dppclk when split is forced, do not bother with dispclk */
++		if (split[i] && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
++			context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
+ 		pipe_idx++;
+ 	}
+ 
++	return vlevel;
++}
++
++bool dcn20_fast_validate_bw(
++		struct dc *dc,
++		struct dc_state *context,
++		display_e2e_pipe_params_st *pipes,
++		int *pipe_cnt_out,
++		int *pipe_split_from,
++		int *vlevel_out)
++{
++	bool out = false;
++	bool split[MAX_PIPES] = { false };
++	int pipe_cnt, i, pipe_idx, vlevel;
++
++	ASSERT(pipes);
++	if (!pipes)
++		return false;
++
++	dcn20_merge_pipes_for_validate(dc, context);
++
++	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, &context->res_ctx, pipes);
++
++	*pipe_cnt_out = pipe_cnt;
++
++	if (!pipe_cnt) {
++		out = true;
++		goto validate_out;
++	}
++
++	vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
++
++	if (vlevel > context->bw_ctx.dml.soc.num_states)
++		goto validate_fail;
++
++	vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split);
++
++	/*initialize pipe_just_split_from to invalid idx*/
++	for (i = 0; i < MAX_PIPES; i++)
++		pipe_split_from[i] = -1;
++
+ 	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
+ 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ 		struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
+-		bool need_split = true;
+-		bool need_split3d;
+ 
+ 		if (!pipe->stream || pipe_split_from[i] >= 0)
+ 			continue;
+ 
+ 		pipe_idx++;
+ 
+-		if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
+-			force_split = true;
+-			context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] = true;
+-			context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;
+-		}
+-		if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
+-			context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
+ 		if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
+ 			hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
+ 			ASSERT(hsplit_pipe);
+@@ -2461,32 +2502,16 @@ bool dcn20_fast_validate_bw(
+ 		if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
+ 			continue;
+ 
+-		need_split3d = ((pipe->stream->view_format ==
+-				VIEW_3D_FORMAT_SIDE_BY_SIDE ||
+-				pipe->stream->view_format ==
+-				VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
+-				(pipe->stream->timing.timing_3d_format ==
+-				TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
+-				 pipe->stream->timing.timing_3d_format ==
+-				TIMING_3D_FORMAT_SIDE_BY_SIDE));
+-
+-		if (avoid_split && vlevel_unsplit <= context->bw_ctx.dml.soc.num_states && !force_split && !need_split3d) {
+-			need_split = false;
+-			vlevel = vlevel_unsplit;
+-			context->bw_ctx.dml.vba.maxMpcComb = 0;
+-		} else
+-			need_split = context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 2;
+-
+ 		/* We do not support mpo + odm at the moment */
+ 		if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
+ 				&& context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
+ 			goto validate_fail;
+ 
+-		if (need_split3d || need_split || force_split) {
++		if (split[i]) {
+ 			if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
+ 				/* pipe not split previously needs split */
+ 				hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
+-				ASSERT(hsplit_pipe || force_split);
++				ASSERT(hsplit_pipe);
+ 				if (!hsplit_pipe)
+ 					continue;
+ 
+@@ -2549,7 +2574,7 @@ void dcn20_calculate_wm(
+ 					context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
+ 			if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
+ 				pipes[pipe_cnt].pipe.dest.odm_combine =
+-						context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
++						context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
+ 			else
+ 				pipes[pipe_cnt].pipe.dest.odm_combine = 0;
+ 			pipe_idx++;
+@@ -2558,7 +2583,7 @@ void dcn20_calculate_wm(
+ 					context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
+ 			if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
+ 				pipes[pipe_cnt].pipe.dest.odm_combine =
+-						context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]];
++						context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
+ 			else
+ 				pipes[pipe_cnt].pipe.dest.odm_combine = 0;
+ 		}
+@@ -2929,6 +2954,7 @@ static struct resource_funcs dcn20_res_pool_funcs = {
+ 	.populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
+ 	.get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
+ 	.set_mcif_arb_params = dcn20_set_mcif_arb_params,
++	.populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
+ 	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+index 55006462f481..fe68669a1f0c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+@@ -113,6 +113,31 @@ void dcn20_set_mcif_arb_params(
+ 		display_e2e_pipe_params_st *pipes,
+ 		int pipe_cnt);
+ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate);
++void dcn20_merge_pipes_for_validate(
++		struct dc *dc,
++		struct dc_state *context);
++int dcn20_validate_apply_pipe_split_flags(
++		struct dc *dc,
++		struct dc_state *context,
++		int vlevel,
++		bool *split);
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx);
++#endif
++void dcn20_split_stream_for_mpc(
++		struct resource_context *res_ctx,
++		const struct resource_pool *pool,
++		struct pipe_ctx *primary_pipe,
++		struct pipe_ctx *secondary_pipe);
++bool dcn20_split_stream_for_odm(
++		struct resource_context *res_ctx,
++		const struct resource_pool *pool,
++		struct pipe_ctx *prev_odm_pipe,
++		struct pipe_ctx *next_odm_pipe);
++struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
++		struct resource_context *res_ctx,
++		const struct resource_pool *pool,
++		const struct pipe_ctx *primary_pipe);
+ bool dcn20_fast_validate_bw(
+ 		struct dc *dc,
+ 		struct dc_state *context,
+@@ -125,6 +150,12 @@ void dcn20_calculate_dlg_params(
+ 		display_e2e_pipe_params_st *pipes,
+ 		int pipe_cnt,
+ 		int vlevel);
++void dcn20_calculate_wm(
++		struct dc *dc, struct dc_state *context,
++		display_e2e_pipe_params_st *pipes,
++		int *out_pipe_cnt,
++		int *pipe_split_from,
++		int vlevel);
+ 
+ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);
+ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 2125a3e50b0b..7a87a79326ca 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1639,6 +1639,7 @@ static struct resource_funcs dcn21_res_pool_funcs = {
+ 	.destroy = dcn21_destroy_resource_pool,
+ 	.link_enc_create = dcn21_link_encoder_create,
+ 	.validate_bandwidth = dcn21_validate_bandwidth,
++	.populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
+ 	.add_stream_to_ctx = dcn20_add_stream_to_ctx,
+ 	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
+ 	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4239-drm-amd-display-correctly-initialize-dml-odm-variabl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4239-drm-amd-display-correctly-initialize-dml-odm-variabl.patch
new file mode 100644
index 00000000..aa5e5bb0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4239-drm-amd-display-correctly-initialize-dml-odm-variabl.patch
@@ -0,0 +1,64 @@
+From 90b5c719195b98a04b8ab74d4694bf55238cf684 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 25 Sep 2019 08:25:24 -0400
+Subject: [PATCH 4239/4736] drm/amd/display: correctly initialize dml odm
+ variables
+
+One of odm variables was not initialized in dml.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Chris Park <Chris.Park@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Acked-by: Tony Cheng <Tony.Cheng@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h | 6 ------
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 2 ++
+ 3 files changed, 3 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 2ea4879b834f..f283fdcfd3b2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2553,7 +2553,7 @@ bool dcn20_fast_validate_bw(
+ 	return out;
+ }
+ 
+-void dcn20_calculate_wm(
++static void dcn20_calculate_wm(
+ 		struct dc *dc, struct dc_state *context,
+ 		display_e2e_pipe_params_st *pipes,
+ 		int *out_pipe_cnt,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+index fe68669a1f0c..dccfe07832e3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+@@ -150,12 +150,6 @@ void dcn20_calculate_dlg_params(
+ 		display_e2e_pipe_params_st *pipes,
+ 		int pipe_cnt,
+ 		int vlevel);
+-void dcn20_calculate_wm(
+-		struct dc *dc, struct dc_state *context,
+-		display_e2e_pipe_params_st *pipes,
+-		int *out_pipe_cnt,
+-		int *pipe_split_from,
+-		int vlevel);
+ 
+ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);
+ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+index 362dc6ea98ae..038701d7383d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+@@ -432,6 +432,8 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
+ 				dst->recout_width; // TODO: or should this be full_recout_width???...maybe only when in hsplit mode?
+ 		mode_lib->vba.ODMCombineEnabled[mode_lib->vba.NumberOfActivePlanes] =
+ 				dst->odm_combine;
++		mode_lib->vba.ODMCombineTypeEnabled[mode_lib->vba.NumberOfActivePlanes] =
++				dst->odm_combine;
+ 		mode_lib->vba.OutputFormat[mode_lib->vba.NumberOfActivePlanes] =
+ 				(enum output_format_class) (dout->output_format);
+ 		mode_lib->vba.OutputBpp[mode_lib->vba.NumberOfActivePlanes] =
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4240-drm-amd-display-move-dispclk-vco-freq-to-clk-mgr-bas.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4240-drm-amd-display-move-dispclk-vco-freq-to-clk-mgr-bas.patch
new file mode 100644
index 00000000..2f63ca28
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4240-drm-amd-display-move-dispclk-vco-freq-to-clk-mgr-bas.patch
@@ -0,0 +1,316 @@
+From 8ee40e6139e1d3b8d5b099bfad953a8e1cdddc50 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 25 Sep 2019 17:12:10 -0400
+Subject: [PATCH 4240/4736] drm/amd/display: move dispclk vco freq to clk mgr
+ base
+
+This value will be needed by dml and therefore should be externally
+accessible.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c    | 14 +++++++-------
+ .../amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c |  4 ++--
+ .../drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 10 +++++-----
+ .../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c   | 14 +++++++-------
+ .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c  | 12 ++++++------
+ .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h  |  7 -------
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c  | 12 ++++++------
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.h  |  6 ++++++
+ drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h    |  2 +-
+ .../drm/amd/display/dc/inc/hw/clk_mgr_internal.h   |  2 --
+ 10 files changed, 40 insertions(+), 43 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+index 7634982a6bb0..aa0e6ee205c1 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+@@ -144,7 +144,7 @@ int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
+ 
+ 	/* Calculate the current DFS clock, in kHz.*/
+ 	dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+-		* clk_mgr->dentist_vco_freq_khz) / target_div;
++		* clk_mgr->base.dentist_vco_freq_khz) / target_div;
+ 
+ 	return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
+ }
+@@ -236,7 +236,7 @@ int dce_set_clock(
+ 	/* Make sure requested clock isn't lower than minimum threshold*/
+ 	if (requested_clk_khz > 0)
+ 		requested_clk_khz = max(requested_clk_khz,
+-				clk_mgr_dce->dentist_vco_freq_khz / 64);
++				clk_mgr_dce->base.dentist_vco_freq_khz / 64);
+ 
+ 	/* Prepare to program display clock*/
+ 	pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;
+@@ -273,11 +273,11 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)
+ 	int i;
+ 
+ 	if (bp->integrated_info)
+-		clk_mgr_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
+-	if (clk_mgr_dce->dentist_vco_freq_khz == 0) {
+-		clk_mgr_dce->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
+-		if (clk_mgr_dce->dentist_vco_freq_khz == 0)
+-			clk_mgr_dce->dentist_vco_freq_khz = 3600000;
++		clk_mgr_dce->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
++	if (clk_mgr_dce->base.dentist_vco_freq_khz == 0) {
++		clk_mgr_dce->base.dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
++		if (clk_mgr_dce->base.dentist_vco_freq_khz == 0)
++			clk_mgr_dce->base.dentist_vco_freq_khz = 3600000;
+ 	}
+ 
+ 	/*update the maximum display clock for each power state*/
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+index 7c746ef1e32e..a6c46e903ff9 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+@@ -81,7 +81,7 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
+ 	/* Make sure requested clock isn't lower than minimum threshold*/
+ 	if (requested_clk_khz > 0)
+ 		requested_clk_khz = max(requested_clk_khz,
+-				clk_mgr_dce->dentist_vco_freq_khz / 62);
++				clk_mgr_dce->base.dentist_vco_freq_khz / 62);
+ 
+ 	dce_clk_params.target_clock_frequency = requested_clk_khz;
+ 	dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
+@@ -135,7 +135,7 @@ int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)
+ 	/* Make sure requested clock isn't lower than minimum threshold*/
+ 	if (requested_clk_khz > 0)
+ 		requested_clk_khz = max(requested_clk_khz,
+-				clk_mgr->dentist_vco_freq_khz / 62);
++				clk_mgr->base.dentist_vco_freq_khz / 62);
+ 
+ 	dce_clk_params.target_clock_frequency = requested_clk_khz;
+ 	dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+index 6e03805e1b87..3c8b4d5dd843 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+@@ -271,11 +271,11 @@ void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_
+ 	clk_mgr->base.dprefclk_khz = 600000;
+ 
+ 	if (bp->integrated_info)
+-		clk_mgr->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
+-	if (bp->fw_info_valid && clk_mgr->dentist_vco_freq_khz == 0) {
+-		clk_mgr->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
+-		if (clk_mgr->dentist_vco_freq_khz == 0)
+-			clk_mgr->dentist_vco_freq_khz = 3600000;
++		clk_mgr->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
++	if (bp->fw_info_valid && clk_mgr->base.dentist_vco_freq_khz == 0) {
++		clk_mgr->base.dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
++		if (clk_mgr->base.dentist_vco_freq_khz == 0)
++			clk_mgr->base.dentist_vco_freq_khz = 3600000;
+ 	}
+ 
+ 	if (!debug->disable_dfs_bypass && bp->integrated_info)
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index 69daddbfbf29..607d8afc56ec 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -121,9 +121,9 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
+ void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr)
+ {
+ 	int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+-			* clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
++			* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
+ 	int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+-			* clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
++			* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
+ 
+ 	uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
+ 	uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
+@@ -412,7 +412,7 @@ void dcn20_clk_mgr_construct(
+ 
+ 	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
+ 		dcn2_funcs.update_clocks = dcn2_update_clocks_fpga;
+-		clk_mgr->dentist_vco_freq_khz = 3850000;
++		clk_mgr->base.dentist_vco_freq_khz = 3850000;
+ 
+ 	} else {
+ 		/* DFS Slice 2 should be used for DPREFCLK */
+@@ -436,15 +436,15 @@ void dcn20_clk_mgr_construct(
+ 		pll_req = dc_fixpt_mul_int(pll_req, 100000);
+ 
+ 		/* integer part is now VCO frequency in kHz */
+-		clk_mgr->dentist_vco_freq_khz = dc_fixpt_floor(pll_req);
++		clk_mgr->base.dentist_vco_freq_khz = dc_fixpt_floor(pll_req);
+ 
+ 		/* in case we don't get a value from the register, use default */
+-		if (clk_mgr->dentist_vco_freq_khz == 0)
+-			clk_mgr->dentist_vco_freq_khz = 3850000;
++		if (clk_mgr->base.dentist_vco_freq_khz == 0)
++			clk_mgr->base.dentist_vco_freq_khz = 3850000;
+ 
+ 		/* Calculate the DPREFCLK in kHz.*/
+ 		clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
+-			* clk_mgr->dentist_vco_freq_khz) / target_div;
++			* clk_mgr->base.dentist_vco_freq_khz) / target_div;
+ 	}
+ 	//Integrated_info table does not exist on dGPU projects so should not be referenced
+ 	//anywhere in code for dGPUs.
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 6212b407cd01..e8b8ee4f1b1e 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -472,7 +472,7 @@ struct clk_bw_params rn_bw_params = {
+ 	}
+ };
+ 
+-void rn_build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
++static void rn_build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
+ {
+ 	int i, num_valid_sets;
+ 
+@@ -542,7 +542,7 @@ static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsi
+ 	return 0;
+ }
+ 
+-void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
++static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
+ {
+ 	int i, j = 0;
+ 
+@@ -628,17 +628,17 @@ void rn_clk_mgr_construct(
+ 
+ 	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
+ 		dcn21_funcs.update_clocks = dcn2_update_clocks_fpga;
+-		clk_mgr->dentist_vco_freq_khz = 3600000;
++		clk_mgr->base.dentist_vco_freq_khz = 3600000;
+ 		clk_mgr->base.dprefclk_khz = 600000;
+ 	} else {
+ 		struct clk_log_info log_info = {0};
+ 
+ 		/* TODO: Check we get what we expect during bringup */
+-		clk_mgr->dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
++		clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
+ 
+ 		/* in case we don't get a value from the register, use default */
+-		if (clk_mgr->dentist_vco_freq_khz == 0)
+-			clk_mgr->dentist_vco_freq_khz = 3600000;
++		if (clk_mgr->base.dentist_vco_freq_khz == 0)
++			clk_mgr->base.dentist_vco_freq_khz = 3600000;
+ 
+ 		rn_dump_clk_registers(&s, &clk_mgr->base, &log_info);
+ 		/* Convert dprefclk units from MHz to KHz */
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
+index 761bfda970a5..e4322fa5475b 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
+@@ -33,13 +33,6 @@ struct rn_clk_registers {
+ 	uint32_t CLK1_CLK0_CURRENT_CNT; /* DPREFCLK */
+ };
+ 
+-void rn_build_watermark_ranges(
+-		struct clk_bw_params *bw_params,
+-		struct pp_smu_wm_range_sets *ranges);
+-void rn_clk_mgr_helper_populate_bw_params(
+-		struct clk_bw_params *bw_params,
+-		struct dpm_clocks *clock_table,
+-		struct hw_asic_id *asic_id);
+ void rn_clk_mgr_construct(struct dc_context *ctx,
+ 		struct clk_mgr_internal *clk_mgr,
+ 		struct pp_smu_funcs *pp_smu,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index f283fdcfd3b2..5e939d20e88f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -3031,7 +3031,7 @@ static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
+ 	}
+ }
+ 
+-static void cap_soc_clocks(
++void dcn20_cap_soc_clocks(
+ 		struct _vcs_dpi_soc_bounding_box_st *bb,
+ 		struct pp_smu_nv_clock_table max_clocks)
+ {
+@@ -3098,7 +3098,7 @@ static void cap_soc_clocks(
+ 	}
+ }
+ 
+-static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
++void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
+ 		struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
+ {
+ 	struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES];
+@@ -3156,7 +3156,7 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_
+ 	bb->clock_limits[num_calculated_states].state = bb->num_states;
+ }
+ 
+-static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
++void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
+ {
+ 	kernel_fpu_begin();
+ 	if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
+@@ -3355,14 +3355,14 @@ static bool init_soc_bounding_box(struct dc *dc,
+ 		}
+ 
+ 		if (clock_limits_available && uclk_states_available && num_states)
+-			update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
++			dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
+ 		else if (clock_limits_available)
+-			cap_soc_clocks(loaded_bb, max_clocks);
++			dcn20_cap_soc_clocks(loaded_bb, max_clocks);
+ 	}
+ 
+ 	loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
+ 	loaded_ip->max_num_dpp = pool->base.pipe_count;
+-	patch_bounding_box(dc, loaded_bb);
++	dcn20_patch_bounding_box(dc, loaded_bb);
+ 
+ 	return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+index dccfe07832e3..fef473d68a4a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+@@ -95,6 +95,12 @@ struct display_stream_compressor *dcn20_dsc_create(
+ 	struct dc_context *ctx, uint32_t inst);
+ void dcn20_dsc_destroy(struct display_stream_compressor **dsc);
+ 
++void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb);
++void dcn20_cap_soc_clocks(
++		struct _vcs_dpi_soc_bounding_box_st *bb,
++		struct pp_smu_nv_clock_table max_clocks);
++void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
++		struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states);
+ struct hubp *dcn20_hubp_create(
+ 	struct dc_context *ctx,
+ 	uint32_t inst);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+index f2e21cb9fbd5..da43523a7bfe 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+@@ -149,7 +149,6 @@ struct wm_table {
+ struct clk_bw_params {
+ 	unsigned int vram_type;
+ 	unsigned int num_channels;
+-	unsigned int dispclk_vco_khz;
+ 	struct clk_limit_table clk_table;
+ 	struct wm_table wm_table;
+ };
+@@ -192,6 +191,7 @@ struct clk_mgr {
+ 	struct dc_clocks clks;
+ 	bool psr_allow_active_cache;
+ 	int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
++	int dentist_vco_freq_khz;
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_1
+ 	struct clk_bw_params *bw_params;
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+index 2e8cd7956a17..a17a77192690 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+@@ -225,8 +225,6 @@ struct clk_mgr_internal {
+ 	struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
+ 
+ 	/*TODO: figure out which of the below fields should be here vs in asic specific portion */
+-	int dentist_vco_freq_khz;
+-
+ 	/* Cache the status of DFS-bypass feature*/
+ 	bool dfs_bypass_enabled;
+ 	/* True if the DFS-bypass feature is enabled and active. */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4241-drm-amd-display-remove-unnecessary-assert.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4241-drm-amd-display-remove-unnecessary-assert.patch
new file mode 100644
index 00000000..44f1d048
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4241-drm-amd-display-remove-unnecessary-assert.patch
@@ -0,0 +1,38 @@
+From 48f867d199e53a69984315e4a82f217bb5f03017 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Wed, 25 Sep 2019 18:11:12 -0400
+Subject: [PATCH 4241/4736] drm/amd/display: remove unnecessary assert
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Chris Park <Chris.Park@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 5e939d20e88f..58a427d30075 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1662,7 +1662,6 @@ bool dcn20_split_stream_for_odm(
+ 	next_odm_pipe->stream_res.dsc = NULL;
+ #endif
+ 	if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
+-		ASSERT(!next_odm_pipe->next_odm_pipe);
+ 		next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
+ 		next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
+ 	}
+@@ -2427,8 +2426,8 @@ int dcn20_validate_apply_pipe_split_flags(
+ 			split[i] = true;
+ 			context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;
+ 		}
+-		context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]
+-			= context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
++		context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] =
++			context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
+ 		/* Adjust dppclk when split is forced, do not bother with dispclk */
+ 		if (split[i] && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
+ 			context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4242-drm-amd-display-Fix-MPO-pipe-split-on-3-pipe-dcn2x.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4242-drm-amd-display-Fix-MPO-pipe-split-on-3-pipe-dcn2x.patch
new file mode 100644
index 00000000..b8d32ee5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4242-drm-amd-display-Fix-MPO-pipe-split-on-3-pipe-dcn2x.patch
@@ -0,0 +1,63 @@
+From f30704ee3bcfebbcd399848f2cc8dab6e78ecf9a Mon Sep 17 00:00:00 2001
+From: Michael Strauss <michael.strauss@amd.com>
+Date: Tue, 1 Oct 2019 11:24:32 -0400
+Subject: [PATCH 4242/4736] drm/amd/display: Fix MPO & pipe split on 3-pipe
+ dcn2x
+
+[WHY]
+DML is incorrectly initialized with 4 pipes on 3 pipe configs
+RequiredDPPCLK is halved on unsplit pipe due to an incorrectly handled 3 pipe
+case, causing underflow with 2 planes & pipe split (MPO, 8K + 2nd display)
+
+[HOW]
+Set correct number of DPP/OTGs for dml init to generate correct DPP topology
+Double RequiredDPPCLK after clock is halved for pipe split
+and find_secondary_pipe fails to fix underflow
+
+Signed-off-by: Michael Strauss <michael.strauss@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 5 +++--
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 8 ++++++++
+ 2 files changed, 11 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 58a427d30075..0ef5c5d60f79 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2511,9 +2511,10 @@ bool dcn20_fast_validate_bw(
+ 				/* pipe not split previously needs split */
+ 				hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
+ 				ASSERT(hsplit_pipe);
+-				if (!hsplit_pipe)
++				if (!hsplit_pipe) {
++					context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
+ 					continue;
+-
++				}
+ 				if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
+ 					if (!dcn20_split_stream_for_odm(
+ 							&context->res_ctx, dc->res_pool,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 7a87a79326ca..47a8955003a5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1772,6 +1772,14 @@ static bool construct(
+ 
+ 	pool->base.pp_smu = dcn21_pp_smu_create(ctx);
+ 
++	uint32_t num_pipes = dcn2_1_ip.max_num_dpp;
++
++	for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
++		if (pipe_fuses & 1 << i)
++			num_pipes--;
++	dcn2_1_ip.max_num_dpp = num_pipes;
++	dcn2_1_ip.max_num_otg = num_pipes;
++
+ 	dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
+ 
+ 	init_data.ctx = dc->ctx;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4243-drm-amd-display-audio-endpoint-cannot-switch.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4243-drm-amd-display-audio-endpoint-cannot-switch.patch
new file mode 100644
index 00000000..bae703da
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4243-drm-amd-display-audio-endpoint-cannot-switch.patch
@@ -0,0 +1,45 @@
+From 27c0ad919ed09d031d01e7ada90941d9758795a1 Mon Sep 17 00:00:00 2001
+From: Paul Hsieh <paul.hsieh@amd.com>
+Date: Tue, 1 Oct 2019 17:06:04 +0800
+Subject: [PATCH 4243/4736] drm/amd/display: audio endpoint cannot switch
+
+[Why]
+On some systems, we need to check the dcn version in runtime
+system, not in compile time.
+
+[How]
+Stub in dcn version parameter to find_first_free_audio
+
+Signed-off-by: Paul Hsieh <paul.hsieh@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 23313c8808b3..66a910ac3cbd 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -1626,7 +1626,8 @@ static int acquire_first_free_pipe(
+ static struct audio *find_first_free_audio(
+ 		struct resource_context *res_ctx,
+ 		const struct resource_pool *pool,
+-		enum engine_id id)
++		enum engine_id id,
++		enum dce_version dc_version)
+ {
+ 	int i, available_audio_count;
+ 
+@@ -1962,7 +1963,7 @@ enum dc_status resource_map_pool_resources(
+ 	    dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
+ 	    stream->audio_info.mode_count && stream->audio_info.flags.all) {
+ 		pipe_ctx->stream_res.audio = find_first_free_audio(
+-		&context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
++		&context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
+ 
+ 		/*
+ 		 * Audio assigned in order first come first get.
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4244-drm-amd-display-Update-min-dcfclk.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4244-drm-amd-display-Update-min-dcfclk.patch
new file mode 100644
index 00000000..e473562b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4244-drm-amd-display-Update-min-dcfclk.patch
@@ -0,0 +1,44 @@
+From c0f19d299a31a816850d57d275d5fd7225844ac1 Mon Sep 17 00:00:00 2001
+From: Alvin Lee <alvin.lee2@amd.com>
+Date: Fri, 27 Sep 2019 12:24:05 -0400
+Subject: [PATCH 4244/4736] drm/amd/display: Update min dcfclk
+
+[Why]
+NV12 has lower min dcfclk
+
+[How]
+Add update in update_bounding_box
+
+Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c    | 12 ++++++++----
+ 1 file changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 0ef5c5d60f79..a094eac4dc95 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -3113,10 +3113,14 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
+ 
+ 	if (dc->bb_overrides.min_dcfclk_mhz > 0)
+ 		min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
+-	else
+-		// Accounting for SOC/DCF relationship, we can go as high as
+-		// 506Mhz in Vmin.  We need to code 507 since SMU will round down to 506.
+-		min_dcfclk = 507;
++	else {
++		if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
++			min_dcfclk = 310;
++		else
++			// Accounting for SOC/DCF relationship, we can go as high as
++			// 506Mhz in Vmin.
++			min_dcfclk = 506;
++	}
+ 
+ 	for (i = 0; i < num_states; i++) {
+ 		int min_fclk_required_by_uclk;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4245-drm-amd-display-Allow-inverted-gamma.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4245-drm-amd-display-Allow-inverted-gamma.patch
new file mode 100644
index 00000000..a40334e4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4245-drm-amd-display-Allow-inverted-gamma.patch
@@ -0,0 +1,77 @@
+From fd51f9ea463e8b3c3f2d9827a8a591b1fd18f838 Mon Sep 17 00:00:00 2001
+From: Aidan Yang <Aidan.Yang@amd.com>
+Date: Wed, 2 Oct 2019 10:47:31 -0400
+Subject: [PATCH 4245/4736] drm/amd/display: Allow inverted gamma
+
+[why]
+There's a use case for inverted gamma
+and it's been confirmed that negative slopes are ok.
+
+[how]
+Remove code for blocking non-monotonically increasing gamma
+
+Signed-off-by: Aidan Yang <Aidan.Yang@amd.com>
+Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Acked-by: Reza Amini <Reza.Amini@amd.com>
+---
+ .../amd/display/dc/dcn10/dcn10_cm_common.c    | 22 +++++++------------
+ 1 file changed, 8 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+index 01c7e30b9ce1..bbd6e01b3eca 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+@@ -393,6 +393,10 @@ bool cm_helper_translate_curve_to_hw_format(
+ 	rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
+ 	rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
+ 
++	rgb_resulted[hw_points].red = rgb_resulted[hw_points - 1].red;
++	rgb_resulted[hw_points].green = rgb_resulted[hw_points - 1].green;
++	rgb_resulted[hw_points].blue = rgb_resulted[hw_points - 1].blue;
++
+ 	// All 3 color channels have same x
+ 	corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2),
+ 					     dc_fixpt_from_int(region_start));
+@@ -464,13 +468,6 @@ bool cm_helper_translate_curve_to_hw_format(
+ 
+ 	i = 1;
+ 	while (i != hw_points + 1) {
+-		if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
+-			rgb_plus_1->red = rgb->red;
+-		if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
+-			rgb_plus_1->green = rgb->green;
+-		if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
+-			rgb_plus_1->blue = rgb->blue;
+-
+ 		rgb->delta_red   = dc_fixpt_sub(rgb_plus_1->red,   rgb->red);
+ 		rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
+ 		rgb->delta_blue  = dc_fixpt_sub(rgb_plus_1->blue,  rgb->blue);
+@@ -562,6 +559,10 @@ bool cm_helper_translate_curve_to_degamma_hw_format(
+ 	rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
+ 	rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
+ 
++	rgb_resulted[hw_points].red = rgb_resulted[hw_points - 1].red;
++	rgb_resulted[hw_points].green = rgb_resulted[hw_points - 1].green;
++	rgb_resulted[hw_points].blue = rgb_resulted[hw_points - 1].blue;
++
+ 	corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2),
+ 					     dc_fixpt_from_int(region_start));
+ 	corner_points[0].green.x = corner_points[0].red.x;
+@@ -624,13 +625,6 @@ bool cm_helper_translate_curve_to_degamma_hw_format(
+ 
+ 	i = 1;
+ 	while (i != hw_points + 1) {
+-		if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
+-			rgb_plus_1->red = rgb->red;
+-		if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
+-			rgb_plus_1->green = rgb->green;
+-		if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
+-			rgb_plus_1->blue = rgb->blue;
+-
+ 		rgb->delta_red   = dc_fixpt_sub(rgb_plus_1->red,   rgb->red);
+ 		rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
+ 		rgb->delta_blue  = dc_fixpt_sub(rgb_plus_1->blue,  rgb->blue);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4246-drm-amd-display-enable-vm-by-default-for-rn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4246-drm-amd-display-enable-vm-by-default-for-rn.patch
new file mode 100644
index 00000000..13e19170
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4246-drm-amd-display-enable-vm-by-default-for-rn.patch
@@ -0,0 +1,85 @@
+From 414c896e764d9775d404c7dff8e90bbfd48944ff Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Wed, 2 Oct 2019 14:09:06 -0400
+Subject: [PATCH 4246/4736] drm/amd/display: enable vm by default for rn.
+
+[Why & How]
+vm should be enabled by default for rn to get
+right dml.
+
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 29 ++++++++++++++++---
+ 1 file changed, 25 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 47a8955003a5..c5c67cb823ac 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -83,8 +83,8 @@
+ 
+ struct _vcs_dpi_ip_params_st dcn2_1_ip = {
+ 	.odm_capable = 1,
+-	.gpuvm_enable = 0,
+-	.hostvm_enable = 0,
++	.gpuvm_enable = 1,
++	.hostvm_enable = 1,
+ 	.gpuvm_max_page_table_levels = 1,
+ 	.hostvm_max_page_table_levels = 4,
+ 	.hostvm_cached_page_table_levels = 2,
+@@ -669,6 +669,9 @@ static const struct dcn10_stream_encoder_mask se_mask = {
+ 
+ static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
+ 
++static int dcn21_populate_dml_pipes_from_context(
++		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
++
+ static struct input_pixel_processor *dcn21_ipp_create(
+ 	struct dc_context *ctx, uint32_t inst)
+ {
+@@ -1083,7 +1086,7 @@ void dcn21_calculate_wm(
+ 			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
+ 				&context->res_ctx, pipes);
+ 		else
+-			pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
++			pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
+ 				&context->res_ctx, pipes);
+ 	}
+ 
+@@ -1635,11 +1638,29 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx)
+ 	return value;
+ }
+ 
++static int dcn21_populate_dml_pipes_from_context(
++		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
++{
++	uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, res_ctx, pipes);
++	int i;
++
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
++
++		if (!res_ctx->pipe_ctx[i].stream)
++			continue;
++
++		pipes[i].pipe.src.hostvm = 1;
++		pipes[i].pipe.src.gpuvm = 1;
++	}
++
++	return pipe_cnt;
++}
++
+ static struct resource_funcs dcn21_res_pool_funcs = {
+ 	.destroy = dcn21_destroy_resource_pool,
+ 	.link_enc_create = dcn21_link_encoder_create,
+ 	.validate_bandwidth = dcn21_validate_bandwidth,
+-	.populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
++	.populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
+ 	.add_stream_to_ctx = dcn20_add_stream_to_ctx,
+ 	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
+ 	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4247-drm-amd-display-fix-number-of-dcn21-dpm-clock-levels.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4247-drm-amd-display-fix-number-of-dcn21-dpm-clock-levels.patch
new file mode 100644
index 00000000..8ca1deee
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4247-drm-amd-display-fix-number-of-dcn21-dpm-clock-levels.patch
@@ -0,0 +1,34 @@
+From bcd12b314c04a6585ae32353612874158493f92d Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Tue, 1 Oct 2019 11:01:00 -0400
+Subject: [PATCH 4247/4736] drm/amd/display: fix number of dcn21 dpm clock
+ levels
+
+These are specific to dcn21 and should not be increased for
+reuse on other asics.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Chris Park <Chris.Park@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+index 60d6620530a8..95f3193da951 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+@@ -245,8 +245,8 @@ struct pp_smu_funcs_nv {
+ 
+ #define PP_SMU_NUM_SOCCLK_DPM_LEVELS  8
+ #define PP_SMU_NUM_DCFCLK_DPM_LEVELS  8
+-#define PP_SMU_NUM_FCLK_DPM_LEVELS    8
+-#define PP_SMU_NUM_MEMCLK_DPM_LEVELS  8
++#define PP_SMU_NUM_FCLK_DPM_LEVELS    4
++#define PP_SMU_NUM_MEMCLK_DPM_LEVELS  4
+ 
+ struct dpm_clock {
+   uint32_t  Freq;    // In MHz
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4248-drm-amd-display-add-embedded-flag-to-dml.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4248-drm-amd-display-add-embedded-flag-to-dml.patch
new file mode 100644
index 00000000..8d80c22e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4248-drm-amd-display-add-embedded-flag-to-dml.patch
@@ -0,0 +1,53 @@
+From 516fc8ba1c91bfb9fd317d4bc1e4bf75048e8e1c Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Tue, 1 Oct 2019 16:08:31 -0400
+Subject: [PATCH 4248/4736] drm/amd/display: add embedded flag to dml
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 1 +
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c     | 1 +
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h     | 1 +
+ 3 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+index 83f84cdd4055..cfacd6027467 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+@@ -318,6 +318,7 @@ struct _vcs_dpi_display_pipe_dest_params_st {
+ 	unsigned int vupdate_width;
+ 	unsigned int vready_offset;
+ 	unsigned char interlaced;
++	unsigned char embedded;
+ 	double pixel_rate_mhz;
+ 	unsigned char synchronized_vblank_all_planes;
+ 	unsigned char otg_inst;
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+index 038701d7383d..7f9a5621922f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+@@ -375,6 +375,7 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
+ 
+ 		mode_lib->vba.pipe_plane[j] = mode_lib->vba.NumberOfActivePlanes;
+ 
++		mode_lib->vba.EmbeddedPanel[mode_lib->vba.NumberOfActivePlanes] = dst->embedded;
+ 		mode_lib->vba.DPPPerPlane[mode_lib->vba.NumberOfActivePlanes] = 1;
+ 		mode_lib->vba.SourceScan[mode_lib->vba.NumberOfActivePlanes] =
+ 				(enum scan_direction_class) (src->source_scan);
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+index 91decac50557..1540ffbe3979 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+@@ -387,6 +387,7 @@ struct vba_vars_st {
+ 
+ 	/* vba mode support */
+ 	/*inputs*/
++	bool EmbeddedPanel[DC__NUM_DPP__MAX];
+ 	bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
+ 	double MaxHSCLRatio;
+ 	double MaxVSCLRatio;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4249-drm-amd-display-add-flag-to-allow-diag-to-force-enum.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4249-drm-amd-display-add-flag-to-allow-diag-to-force-enum.patch
new file mode 100644
index 00000000..10635a7a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4249-drm-amd-display-add-flag-to-allow-diag-to-force-enum.patch
@@ -0,0 +1,49 @@
+From 84f08f4a0536fa2ff71442d177f1dc066431c377 Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Tue, 1 Oct 2019 11:31:37 -0400
+Subject: [PATCH 4249/4736] drm/amd/display: add flag to allow diag to force
+ enumerate edp
+
+[why]
+SLT tests require that diag can drive eDP even if nothing is connected, this is not
+typical production use case, so we need to add flag
+
+[how]
+add flag, and this flag supercedes "should destroy" logic
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dc.h      | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index bd623404772d..072ac5e5e99a 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -191,7 +191,7 @@ static bool create_links(
+ 				}
+ 			}
+ 
+-			if (!should_destory_link) {
++			if (dc->config.force_enum_edp || !should_destory_link) {
+ 				dc->links[dc->link_count] = link;
+ 				link->dc = dc;
+ 				++dc->link_count;
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index a86dad3808b6..b578b2148e45 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -220,6 +220,7 @@ struct dc_config {
+ 	bool allow_seamless_boot_optimization;
+ 	bool power_down_display_on_boot;
+ 	bool edp_not_connected;
++	bool force_enum_edp;
+ 	bool forced_clocks;
+ 	bool disable_extended_timeout_support; // Used to disable extended timeout and lttpr feature as well
+ 	bool multi_mon_pp_mclk_switch;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4250-drm-amd-display-Passive-DP-HDMI-dongle-detection-fix.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4250-drm-amd-display-Passive-DP-HDMI-dongle-detection-fix.patch
new file mode 100644
index 00000000..e83601c1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4250-drm-amd-display-Passive-DP-HDMI-dongle-detection-fix.patch
@@ -0,0 +1,67 @@
+From e926130b39049167cc8f9f52fb87b32a787c86c0 Mon Sep 17 00:00:00 2001
+From: Michael Strauss <michael.strauss@amd.com>
+Date: Thu, 3 Oct 2019 11:54:15 -0400
+Subject: [PATCH 4250/4736] drm/amd/display: Passive DP->HDMI dongle detection
+ fix
+
+[WHY]
+i2c_read is called to differentiate passive DP->HDMI and DP->DVI-D dongles
+The call is expected to fail in DVI-D case but pass in HDMI case
+Some HDMI dongles have a chance to fail as well, causing misdetection as DVI-D
+
+[HOW]
+Retry i2c_read to ensure failed result is valid
+
+Signed-off-by: Michael Strauss <michael.strauss@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 24 ++++++++++++++-----
+ 1 file changed, 18 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+index 580594be1de5..d98640f49874 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+@@ -372,6 +372,7 @@ void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
+ 	enum display_dongle_type *dongle = &sink_cap->dongle_type;
+ 	uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
+ 	bool is_type2_dongle = false;
++	int retry_count = 2;
+ 	struct dp_hdmi_dongle_signature_data *dongle_signature;
+ 
+ 	/* Assume we have no valid DP passive dongle connected */
+@@ -384,13 +385,24 @@ void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
+ 		DP_HDMI_DONGLE_ADDRESS,
+ 		type2_dongle_buf,
+ 		sizeof(type2_dongle_buf))) {
+-		*dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
+-		sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
++		/* Passive HDMI dongles can sometimes fail here without retrying*/
++		while (retry_count > 0) {
++			if (i2c_read(ddc,
++				DP_HDMI_DONGLE_ADDRESS,
++				type2_dongle_buf,
++				sizeof(type2_dongle_buf)))
++				break;
++			retry_count--;
++		}
++		if (retry_count == 0) {
++			*dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
++			sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
+ 
+-		CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf),
+-				"DP-DVI passive dongle %dMhz: ",
+-				DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
+-		return;
++			CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf),
++					"DP-DVI passive dongle %dMhz: ",
++					DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
++			return;
++		}
+ 	}
+ 
+ 	/* Check if Type 2 dongle.*/
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4251-drm-amd-display-Disable-force_single_disp_pipe_split.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4251-drm-amd-display-Disable-force_single_disp_pipe_split.patch
new file mode 100644
index 00000000..e7f4097d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4251-drm-amd-display-Disable-force_single_disp_pipe_split.patch
@@ -0,0 +1,48 @@
+From 46de063efa708713349a25fb1731d2f5006fa55d Mon Sep 17 00:00:00 2001
+From: Michael Strauss <michael.strauss@amd.com>
+Date: Tue, 1 Oct 2019 12:04:16 -0400
+Subject: [PATCH 4251/4736] drm/amd/display: Disable
+ force_single_disp_pipe_split on DCN2+
+
+[WHY]
+force_single_disp_pipe_split is a debug flag for use on DCN1
+but isn't necessary otherwise as DCN2+ splits by default
+
+Signed-off-by: Michael Strauss <michael.strauss@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index a094eac4dc95..b5b085aeef2b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -834,7 +834,7 @@ static const struct dc_debug_options debug_defaults_drv = {
+ 		.clock_trace = true,
+ 		.disable_pplib_clock_request = true,
+ 		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
+-		.force_single_disp_pipe_split = true,
++		.force_single_disp_pipe_split = false,
+ 		.disable_dcc = DCC_ENABLE,
+ 		.vsr_support = true,
+ 		.performance_trace = false,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index c5c67cb823ac..51f23680244a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -836,7 +836,7 @@ static const struct dc_debug_options debug_defaults_drv = {
+ 		.clock_trace = true,
+ 		.disable_pplib_clock_request = true,
+ 		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
+-		.force_single_disp_pipe_split = true,
++		.force_single_disp_pipe_split = false,
+ 		.disable_dcc = DCC_ENABLE,
+ 		.vsr_support = true,
+ 		.performance_trace = false,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4252-drm-amd-display-Proper-return-of-result-when-aux-eng.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4252-drm-amd-display-Proper-return-of-result-when-aux-eng.patch
new file mode 100644
index 00000000..96a9998e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4252-drm-amd-display-Proper-return-of-result-when-aux-eng.patch
@@ -0,0 +1,77 @@
+From 028bb6e29c093f31f569f7e129229312f25b7e7d Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Wed, 2 Oct 2019 12:22:29 -0400
+Subject: [PATCH 4252/4736] drm/amd/display: Proper return of result when aux
+ engine acquire fails
+
+[Why]
+When aux engine acquire fails, we missed populating the operation_result
+that describes the failure reason.
+
+[How]
+Set operation_result to new type:
+AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE
+in the case aux engine acquire has failed.
+
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 1 +
+ drivers/gpu/drm/amd/display/dc/dc_ddc_types.h               | 3 ++-
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c                | 5 ++++-
+ 3 files changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+index 430155730c29..c765fcbd1386 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+@@ -113,6 +113,7 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
+ 			result = -EIO;
+ 			break;
+ 		case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
++		case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
+ 			result = -EBUSY;
+ 			break;
+ 		case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h b/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
+index 4ef97f65e55d..4f8f576d5fcf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
+@@ -49,7 +49,8 @@ enum aux_channel_operation_result {
+ 	AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN,
+ 	AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY,
+ 	AUX_CHANNEL_OPERATION_FAILED_TIMEOUT,
+-	AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON
++	AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON,
++	AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE
+ };
+ 
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+index a68edd0c2172..3c3830f7908f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+@@ -535,8 +535,10 @@ int dce_aux_transfer_raw(struct ddc_service *ddc,
+ 	memset(&aux_rep, 0, sizeof(aux_rep));
+ 
+ 	aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
+-	if (!acquire(aux_engine, ddc_pin))
++	if (!acquire(aux_engine, ddc_pin)) {
++		*operation_result = AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE;
+ 		return -1;
++	}
+ 
+ 	if (payload->i2c_over_aux)
+ 		aux_req.type = AUX_TRANSACTION_TYPE_I2C;
+@@ -660,6 +662,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
+ 			break;
+ 
+ 		case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
++		case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
+ 		case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
+ 		default:
+ 			goto fail;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4253-drm-amd-display-do-not-synchronize-drr-displays.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4253-drm-amd-display-do-not-synchronize-drr-displays.patch
new file mode 100644
index 00000000..832f216f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4253-drm-amd-display-do-not-synchronize-drr-displays.patch
@@ -0,0 +1,52 @@
+From 53020e71768ea377f2ab79c94ee7a45d6d6b7565 Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Thu, 3 Oct 2019 15:09:53 -0400
+Subject: [PATCH 4253/4736] drm/amd/display: do not synchronize "drr" displays
+
+[why]
+A display that supports DRR can never really be considered
+"synchronized" with any other display because we can dynamically
+enable DRR (i.e. without modeset).  this will cause their
+relative CRTC positions to drift and lose sync.  this will disrupt
+features such as MCLK switching that assume and depend on
+their permanent alignment (that can only change with modeset)
+
+[how]
+check for ignore_msa in stream when considered synchronizability
+this ignore_msa is basically actually implemented as "supports drr"
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 66a910ac3cbd..4154f1eedece 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -401,6 +401,9 @@ bool resource_are_streams_timing_synchronizable(
+ 	if (stream1->view_format != stream2->view_format)
+ 		return false;
+ 
++	if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
++		return false;
++
+ 	return true;
+ }
+ static bool is_dp_and_hdmi_sharable(
+@@ -1537,6 +1540,9 @@ bool dc_is_stream_unchanged(
+ 	if (!are_stream_backends_same(old_stream, stream))
+ 		return false;
+ 
++	if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
++		return false;
++
+ 	return true;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4254-drm-amd-display-move-wm-ranges-reporting-to-end-of-i.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4254-drm-amd-display-move-wm-ranges-reporting-to-end-of-i.patch
new file mode 100644
index 00000000..4bfe3379
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4254-drm-amd-display-move-wm-ranges-reporting-to-end-of-i.patch
@@ -0,0 +1,231 @@
+From 9660422158b380fa32fd18ba9d56424ced83d18c Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Tue, 24 Sep 2019 12:02:38 -0400
+Subject: [PATCH 4254/4736] drm/amd/display: move wm ranges reporting to end of
+ init hw
+
+[Why]
+SMU does not keep the wm table across S3, S4, need to re-send
+the table. Also defer sending the cable to after DCN bave initialized
+
+[How]
+Send table at end of init hw
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 149 +++++++++---------
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   4 +
+ .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   |   1 +
+ 3 files changed, 81 insertions(+), 73 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index e8b8ee4f1b1e..f64d221ad6f1 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -396,12 +396,87 @@ void rn_init_clocks(struct clk_mgr *clk_mgr)
+ 	clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
+ }
+ 
++void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
++{
++	int i, num_valid_sets;
++
++	num_valid_sets = 0;
++
++	for (i = 0; i < WM_SET_COUNT; i++) {
++		/* skip empty entries, the smu array has no holes*/
++		if (!bw_params->wm_table.entries[i].valid)
++			continue;
++
++		ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
++		ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;;
++		/* We will not select WM based on dcfclk, so leave it as unconstrained */
++		ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
++		ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++		/* fclk wil be used to select WM*/
++
++		if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) {
++			if (i == 0)
++				ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = 0;
++			else {
++				/* add 1 to make it non-overlapping with next lvl */
++				ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = bw_params->clk_table.entries[i - 1].fclk_mhz + 1;
++			}
++			ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
++
++		} else {
++			/* unconstrained for memory retraining */
++			ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
++			ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++
++			/* Modify previous watermark range to cover up to max */
++			ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++		}
++		num_valid_sets++;
++	}
++
++	ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
++	ranges->num_reader_wm_sets = num_valid_sets;
++
++	/* modify the min and max to make sure we cover the whole range*/
++	ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
++	ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
++	ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++	ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++
++	/* This is for writeback only, does not matter currently as no writeback support*/
++	ranges->num_writer_wm_sets = 1;
++	ranges->writer_wm_sets[0].wm_inst = WM_A;
++	ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
++	ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++	ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
++	ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
++
++}
++
++static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
++{
++	struct dc_debug_options *debug = &clk_mgr_base->ctx->dc->debug;
++	struct pp_smu_wm_range_sets ranges = {0};
++	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
++	struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu;
++
++	if (!debug->disable_pplib_wm_range) {
++		build_watermark_ranges(clk_mgr_base->bw_params, &ranges);
++
++		/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
++		if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)
++			pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges);
++	}
++
++}
++
+ static struct clk_mgr_funcs dcn21_funcs = {
+ 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
+ 	.update_clocks = rn_update_clocks,
+ 	.init_clocks = rn_init_clocks,
+ 	.enable_pme_wa = rn_enable_pme_wa,
+-	/* .dump_clk_registers = rn_dump_clk_registers */
++	/* .dump_clk_registers = rn_dump_clk_registers, */
++	.notify_wm_ranges = rn_notify_wm_ranges
+ };
+ 
+ struct clk_bw_params rn_bw_params = {
+@@ -472,63 +547,6 @@ struct clk_bw_params rn_bw_params = {
+ 	}
+ };
+ 
+-static void rn_build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
+-{
+-	int i, num_valid_sets;
+-
+-	num_valid_sets = 0;
+-
+-	for (i = 0; i < WM_SET_COUNT; i++) {
+-		/* skip empty entries, the smu array has no holes*/
+-		if (!bw_params->wm_table.entries[i].valid)
+-			continue;
+-
+-		ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
+-		ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;;
+-		/* We will not select WM based on dcfclk, so leave it as unconstrained */
+-		ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+-		ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+-		/* fclk wil be used to select WM*/
+-
+-		if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) {
+-			if (i == 0)
+-				ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = 0;
+-			else {
+-				/* add 1 to make it non-overlapping with next lvl */
+-				ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = bw_params->clk_table.entries[i - 1].fclk_mhz + 1;
+-			}
+-			ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
+-
+-		} else {
+-			/* unconstrained for memory retraining */
+-			ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+-			ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+-
+-			/* Modify previous watermark range to cover up to max */
+-			ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+-		}
+-		num_valid_sets++;
+-	}
+-
+-	ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
+-	ranges->num_reader_wm_sets = num_valid_sets;
+-
+-	/* modify the min and max to make sure we cover the whole range*/
+-	ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+-	ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+-	ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+-	ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+-
+-	/* This is for writeback only, does not matter currently as no writeback support*/
+-	ranges->num_writer_wm_sets = 1;
+-	ranges->writer_wm_sets[0].wm_inst = WM_A;
+-	ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+-	ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+-	ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+-	ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+-
+-}
+-
+ static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
+ {
+ 	int i;
+@@ -661,21 +679,6 @@ void rn_clk_mgr_construct(
+ 		rn_clk_mgr_helper_populate_bw_params(clk_mgr->base.bw_params, &clock_table, &ctx->asic_id);
+ 	}
+ 
+-	/*
+-	 * Notify SMU which set of WM should be selected for different ranges of fclk
+-	 * On Renoir there is a maximumum of 4 DF pstates supported, could be less
+-	 * depending on DDR speed and fused maximum fclk.
+-	 */
+-	if (!debug->disable_pplib_wm_range) {
+-		struct pp_smu_wm_range_sets ranges = {0};
+-
+-		rn_build_watermark_ranges(clk_mgr->base.bw_params, &ranges);
+-
+-		/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
+-		if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)
+-			pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges);
+-	}
+-
+ 	if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) {
+ 		/* enable powerfeatures when displaycount goes to 0 */
+ 		rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 7c02f646feed..b61cc211e659 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1303,6 +1303,10 @@ static void dcn10_init_hw(struct dc *dc)
+ 	}
+ 
+ 	dc->hwss.enable_power_gating_plane(dc->hwseq, true);
++
++	if (dc->clk_mgr->funcs->notify_wm_ranges)
++		dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
++
+ }
+ 
+ static void dcn10_reset_hw_ctx_wrap(
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+index da43523a7bfe..4e18e77dcf42 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+@@ -183,6 +183,7 @@ struct clk_mgr_funcs {
+ 
+ 	bool (*are_clock_states_equal) (struct dc_clocks *a,
+ 			struct dc_clocks *b);
++	void (*notify_wm_ranges)(struct clk_mgr *clk_mgr);
+ };
+ 
+ struct clk_mgr {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4255-drm-amd-display-Only-use-EETF-when-maxCL-max-display.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4255-drm-amd-display-Only-use-EETF-when-maxCL-max-display.patch
new file mode 100644
index 00000000..a55b89c6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4255-drm-amd-display-Only-use-EETF-when-maxCL-max-display.patch
@@ -0,0 +1,43 @@
+From ccd1cf77b10a987d5287b07fef6fcb21cc647b42 Mon Sep 17 00:00:00 2001
+From: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Date: Fri, 4 Oct 2019 13:49:03 -0400
+Subject: [PATCH 4255/4736] drm/amd/display: Only use EETF when maxCL > max
+ display
+
+[Why&How]
+BT.2390 EETF is used for tone mapping/range reduction.
+Say display is 0.1 - 500 nits.
+The problematic case is when content is 0-400. We apply EETF because
+0<0.1 so we need to reduce the range by 0.1.
+
+In the commit, we ignore the bottom range. Most displays map 0 to min and
+then have a ramp to 0.1, so sending 0.1 is actually >0.1.
+Furthermode, HW that uses 3D LUT also assumes min=0.
+
+Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 6 +-----
+ 1 file changed, 1 insertion(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+index 0accdae5e675..962a57f75e12 100644
+--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
++++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+@@ -956,11 +956,7 @@ static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
+ 	if (fs_params->max_display < 100) // cap at 100 at the top
+ 		max_display = dc_fixpt_from_int(100);
+ 
+-	if (fs_params->min_content < fs_params->min_display)
+-		use_eetf = true;
+-	else
+-		min_content = min_display;
+-
++	// only max used, we don't adjust min luminance
+ 	if (fs_params->max_content > fs_params->max_display)
+ 		use_eetf = true;
+ 	else
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4256-drm-amd-display-Make-clk-mgr-the-only-dto-update-poi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4256-drm-amd-display-Make-clk-mgr-the-only-dto-update-poi.patch
new file mode 100644
index 00000000..b5339e48
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4256-drm-amd-display-Make-clk-mgr-the-only-dto-update-poi.patch
@@ -0,0 +1,135 @@
+From 45cd082ac07baee76c1abdeb52dbae610fe51a5b Mon Sep 17 00:00:00 2001
+From: Noah Abradjian <noah.abradjian@amd.com>
+Date: Fri, 27 Sep 2019 16:30:57 -0400
+Subject: [PATCH 4256/4736] drm/amd/display: Make clk mgr the only dto update
+ point
+
+[Why]
+
+* Clk Mgr DTO update point did not cover all needed updates, as it included a
+  check for plane_state which does not exist yet when the updater is called on
+  driver startup
+* This resulted in another update path in the pipe programming sequence, based
+  on a dppclk update flag
+* However, this alternate path allowed for stray DTO updates, some of which would
+  occur in the wrong order during dppclk lowering and cause underflow
+
+[How]
+
+* Remove plane_state check and use of plane_res.dpp->inst, getting rid
+  of sequence dependencies (this results in extra dto programming for unused
+  pipes but that doesn't cause issues and is a small cost)
+* Allow DTOs to be updated even if global clock is equal, to account for
+  edge case exposed by diags tests
+* Remove update_dpp_dto call in pipe programming sequence (leave update to
+  dppclk_control there, as that update is necessary and shouldn't occur in clk
+  mgr)
+* Remove call to optimize_bandwidth when committing state, as it is not needed
+  and resulted in sporadic underflows even with other fixes in place
+
+Signed-off-by: Noah Abradjian <noah.abradjian@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c   | 14 +++++++++-----
+ .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c  |  3 ++-
+ drivers/gpu/drm/amd/display/dc/core/dc.c           |  4 ----
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c |  8 +-------
+ 4 files changed, 12 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+index 607d8afc56ec..25d7b7c6681c 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+@@ -108,11 +108,12 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
+ 	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
+ 		int dpp_inst, dppclk_khz;
+ 
+-		if (!context->res_ctx.pipe_ctx[i].plane_state)
+-			continue;
+-
+-		dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
++		/* Loop index will match dpp->inst if resource exists,
++		 * and we want to avoid dependency on dpp object
++		 */
++		dpp_inst = i;
+ 		dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
++
+ 		clk_mgr->dccg->funcs->update_dpp_dto(
+ 				clk_mgr->dccg, dpp_inst, dppclk_khz);
+ 	}
+@@ -235,6 +236,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+ 
+ 		update_dispclk = true;
+ 	}
++
+ 	if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
+ 		if (dpp_clock_lowered) {
+ 			// if clock is being lowered, increase DTO before lowering refclk
+@@ -244,10 +246,12 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
+ 			// if clock is being raised, increase refclk before lowering DTO
+ 			if (update_dppclk || update_dispclk)
+ 				dcn20_update_clocks_update_dentist(clk_mgr);
+-			if (update_dppclk)
++			// always update dtos unless clock is lowered and not safe to lower
++			if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
+ 				dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
+ 		}
+ 	}
++
+ 	if (update_dispclk &&
+ 			dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
+ 		/*update dmcu for wait_loop count*/
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index f64d221ad6f1..790a2d211bd6 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -171,7 +171,8 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
+ 		// if clock is being raised, increase refclk before lowering DTO
+ 		if (update_dppclk || update_dispclk)
+ 			rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
+-		if (update_dppclk)
++		// always update dtos unless clock is lowered and not safe to lower
++		if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
+ 			dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 072ac5e5e99a..3d38e7e071a4 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1238,10 +1238,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ 
+ 	dc_enable_stereo(dc, context, dc_streams, context->stream_count);
+ 
+-	if (!dc->optimize_seamless_boot)
+-		/* pplib is notified if disp_num changed */
+-		dc->hwss.optimize_bandwidth(dc, context);
+-
+ 	for (i = 0; i < context->stream_count; i++)
+                 context->streams[i]->mode_changed = false;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index e237ec39d193..921a36668ced 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1202,15 +1202,9 @@ static void dcn20_update_dchubp_dpp(
+ 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
+ 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+ 
+-	if (pipe_ctx->update_flags.bits.dppclk) {
++	if (pipe_ctx->update_flags.bits.dppclk)
+ 		dpp->funcs->dpp_dppclk_control(dpp, false, true);
+ 
+-		dc->res_pool->dccg->funcs->update_dpp_dto(
+-				dc->res_pool->dccg,
+-				dpp->inst,
+-				pipe_ctx->plane_res.bw.dppclk_khz);
+-	}
+-
+ 	/* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
+ 	 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
+ 	 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4257-drm-amd-display-3.2.56.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4257-drm-amd-display-3.2.56.patch
new file mode 100644
index 00000000..3318974d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4257-drm-amd-display-3.2.56.patch
@@ -0,0 +1,27 @@
+From 70d7f35b7fcfabd58e68598560a498572b1312d6 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Sun, 6 Oct 2019 23:21:07 -0400
+Subject: [PATCH 4257/4736] drm/amd/display: 3.2.56
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index b578b2148e45..0416a17b0897 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.55"
++#define DC_VER "3.2.56"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4258-drm-amd-display-take-signal-type-from-link.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4258-drm-amd-display-take-signal-type-from-link.patch
new file mode 100644
index 00000000..c8aec992
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4258-drm-amd-display-take-signal-type-from-link.patch
@@ -0,0 +1,56 @@
+From 2d6d7bd8a7b1cbbb60f5a4233e389ee45d278973 Mon Sep 17 00:00:00 2001
+From: Lewis Huang <Lewis.Huang@amd.com>
+Date: Thu, 3 Oct 2019 16:01:25 +0800
+Subject: [PATCH 4258/4736] drm/amd/display: take signal type from link
+
+[Why]
+Signal is update to EDP when driver disable first encoder. The
+following encoder using SIGNAL_TYPE_EDP to handle other
+device. When encoder signal is HDMI, driver will detect it is dp
+and release phy. It cause hw hang.
+
+[How]
+Take signal type from link->connector_signal.
+
+Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c   | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index d1e14393a0f0..0d171874ef4e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -1418,8 +1418,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ static void power_down_encoders(struct dc *dc)
+ {
+ 	int i;
+-	enum connector_id connector_id;
+-	enum signal_type signal = SIGNAL_TYPE_NONE;
+ 
+ 	/* do not know BIOS back-front mapping, simply blank all. It will not
+ 	 * hurt for non-DP
+@@ -1430,15 +1428,12 @@ static void power_down_encoders(struct dc *dc)
+ 	}
+ 
+ 	for (i = 0; i < dc->link_count; i++) {
+-		connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id);
+-		if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
+-			(connector_id == CONNECTOR_ID_EDP)) {
++		enum signal_type signal = dc->links[i]->connector_signal;
+ 
++		if ((signal == SIGNAL_TYPE_EDP) ||
++			(signal == SIGNAL_TYPE_DISPLAY_PORT))
+ 			if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
+ 				dp_receiver_power_ctrl(dc->links[i], false);
+-			if (connector_id == CONNECTOR_ID_EDP)
+-				signal = SIGNAL_TYPE_EDP;
+-		}
+ 
+ 		dc->links[i]->link_enc->funcs->disable_output(
+ 				dc->links[i]->link_enc, signal);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4259-drm-amd-display-Add-center-mode-for-integer-scaling-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4259-drm-amd-display-Add-center-mode-for-integer-scaling-.patch
new file mode 100644
index 00000000..18d2ca37
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4259-drm-amd-display-Add-center-mode-for-integer-scaling-.patch
@@ -0,0 +1,98 @@
+From 9512f38631a80c41fad301c2a9bd58fe45b35798 Mon Sep 17 00:00:00 2001
+From: Reza Amini <Reza.Amini@amd.com>
+Date: Mon, 30 Sep 2019 10:11:24 -0400
+Subject: [PATCH 4259/4736] drm/amd/display: Add center mode for integer
+ scaling in DC
+
+[why]
+We want to use maximum space on display to show source
+
+[how]
+For Centered Mode: Replicate source as many times as possible to use
+maximum of display active space add borders.
+
+Signed-off-by: Reza Amini <Reza.Amini@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_resource.c | 43 +++++++++++++++----
+ 1 file changed, 35 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 4154f1eedece..e8b16b4acacc 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -948,7 +948,7 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
+ 	data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
+ 
+ }
+-static bool are_rect_integer_multiples(struct rect src, struct rect dest)
++static bool are_rects_integer_multiples(struct rect src, struct rect dest)
+ {
+ 	if (dest.width  >= src.width  && dest.width  % src.width  == 0 &&
+ 		dest.height >= src.height && dest.height % src.height == 0)
+@@ -956,6 +956,38 @@ static bool are_rect_integer_multiples(struct rect src, struct rect dest)
+ 
+ 	return false;
+ }
++
++void calculate_integer_scaling(struct pipe_ctx *pipe_ctx)
++{
++	if (!pipe_ctx->plane_state->scaling_quality.integer_scaling)
++		return;
++
++	//for Centered Mode
++	if (pipe_ctx->stream->dst.width  == pipe_ctx->stream->src.width &&
++		pipe_ctx->stream->dst.height == pipe_ctx->stream->src.height) {
++		// calculate maximum # of replication of src onto addressable
++		unsigned int integer_multiple = min(
++				pipe_ctx->stream->timing.h_addressable / pipe_ctx->stream->src.width,
++				pipe_ctx->stream->timing.v_addressable  / pipe_ctx->stream->src.height);
++
++		//scale dst
++		pipe_ctx->stream->dst.width  = integer_multiple * pipe_ctx->stream->src.width;
++		pipe_ctx->stream->dst.height = integer_multiple * pipe_ctx->stream->src.height;
++
++		//center dst onto addressable
++		pipe_ctx->stream->dst.x = (pipe_ctx->stream->timing.h_addressable - pipe_ctx->stream->dst.width)/2;
++		pipe_ctx->stream->dst.y = (pipe_ctx->stream->timing.v_addressable - pipe_ctx->stream->dst.height)/2;
++	}
++
++	//disable taps if src & dst are integer ratio
++	if (are_rects_integer_multiples(pipe_ctx->stream->src, pipe_ctx->stream->dst)) {
++		pipe_ctx->plane_state->scaling_quality.v_taps = 1;
++		pipe_ctx->plane_state->scaling_quality.h_taps = 1;
++		pipe_ctx->plane_state->scaling_quality.v_taps_c = 1;
++		pipe_ctx->plane_state->scaling_quality.h_taps_c = 1;
++	}
++}
++
+ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
+ {
+ 	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+@@ -969,6 +1001,8 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
+ 	pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
+ 			pipe_ctx->plane_state->format);
+ 
++	calculate_integer_scaling(pipe_ctx);
++
+ 	calculate_scaling_ratios(pipe_ctx);
+ 
+ 	calculate_viewport(pipe_ctx);
+@@ -999,13 +1033,6 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
+ 		res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
+ 				pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
+ 
+-	if (res &&
+-	    plane_state->scaling_quality.integer_scaling &&
+-	    are_rect_integer_multiples(pipe_ctx->plane_res.scl_data.viewport,
+-				       pipe_ctx->plane_res.scl_data.recout)) {
+-		pipe_ctx->plane_res.scl_data.taps.v_taps = 1;
+-		pipe_ctx->plane_res.scl_data.taps.h_taps = 1;
+-	}
+ 
+ 	if (!res) {
+ 		/* Try 24 bpp linebuffer */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4260-drm-amd-display-Do-not-call-update-bounding-box-on-d.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4260-drm-amd-display-Do-not-call-update-bounding-box-on-d.patch
new file mode 100644
index 00000000..fedc85cf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4260-drm-amd-display-Do-not-call-update-bounding-box-on-d.patch
@@ -0,0 +1,57 @@
+From 0caa5e8f858285f13345c2898ca9c9b680b978a6 Mon Sep 17 00:00:00 2001
+From: Sung Lee <sung.lee@amd.com>
+Date: Mon, 7 Oct 2019 12:05:34 -0400
+Subject: [PATCH 4260/4736] drm/amd/display: Do not call update bounding box on
+ dc create
+
+[Why]
+In Hybrid Graphics, dcn2_1_soc struct stays alive through PnP.
+This causes an issue on dc init where dcn2_1_soc which has been
+updated by update_bw_bounding_box gets put into dml->soc.
+As update_bw_bounding_box is currently incorrect for dcn2.1,
+this makes dml calculations fail due to incorrect parameters,
+leading to a crash on PnP.
+
+[How]
+Comment out update_bw_bounding_box call for now.
+
+Signed-off-by: Sung Lee <sung.lee@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 51f23680244a..910c850701af 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1336,6 +1336,12 @@ struct display_stream_compressor *dcn21_dsc_create(
+ 
+ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
+ {
++	/*
++	TODO: Fix this function to calcualte correct values.
++	There are known issues with this function currently
++	that will need to be investigated. Use hardcoded known good values for now.
++
++
+ 	struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
+ 	struct clk_limit_table *clk_table = &bw_params->clk_table;
+ 	int i;
+@@ -1350,11 +1356,11 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
+ 		dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+ 		dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+ 		dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
+-		/* This is probably wrong, TODO: find correct calculation */
+ 		dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 16 / 1000;
+ 	}
+ 	dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - i];
+ 	dcn2_1_soc.num_states = i;
++	*/
+ }
+ 
+ /* Temporary Place holder until we can get them from fuse */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4261-drm-amd-display-fix-avoid_split-for-dcn2-validation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4261-drm-amd-display-fix-avoid_split-for-dcn2-validation.patch
new file mode 100644
index 00000000..9b6d53ac
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4261-drm-amd-display-fix-avoid_split-for-dcn2-validation.patch
@@ -0,0 +1,64 @@
+From 98fd9d8313513693c43106e77d5cabd3cb63f6b2 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Tue, 8 Oct 2019 12:53:19 -0400
+Subject: [PATCH 4261/4736] drm/amd/display: fix avoid_split for dcn2+
+ validation
+
+We are currently incorrectly processing avoid split at highest
+voltage level.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index b5b085aeef2b..9c96242f0ad9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2355,10 +2355,11 @@ int dcn20_validate_apply_pipe_split_flags(
+ 		int vlevel,
+ 		bool *split)
+ {
+-	int i, pipe_idx, vlevel_unsplit;
++	int i, pipe_idx, vlevel_split;
+ 	bool force_split = false;
+ 	bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
+ 
++	/* Single display loop, exits if there is more than one display */
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ 		bool exit_loop = false;
+@@ -2389,22 +2390,24 @@ int dcn20_validate_apply_pipe_split_flags(
+ 	if (context->stream_count > dc->res_pool->pipe_count / 2)
+ 		avoid_split = true;
+ 
++	/* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
+ 	if (avoid_split) {
+ 		for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+ 			if (!context->res_ctx.pipe_ctx[i].stream)
+ 				continue;
+ 
+-			for (vlevel_unsplit = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
++			for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
+ 				if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1)
+ 					break;
+ 			/* Impossible to not split this pipe */
+-			if (vlevel == context->bw_ctx.dml.soc.num_states)
+-				vlevel = vlevel_unsplit;
++			if (vlevel > context->bw_ctx.dml.soc.num_states)
++				vlevel = vlevel_split;
+ 			pipe_idx++;
+ 		}
+ 		context->bw_ctx.dml.vba.maxMpcComb = 0;
+ 	}
+ 
++	/* Split loop sets which pipe should be split based on dml outputs and dc flags */
+ 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+ 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4262-drm-amd-display-fix-hubbub-deadline-programing.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4262-drm-amd-display-fix-hubbub-deadline-programing.patch
new file mode 100644
index 00000000..03552f62
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4262-drm-amd-display-fix-hubbub-deadline-programing.patch
@@ -0,0 +1,44 @@
+From 3e524c60423cee992127ddc9487298a65bffb782 Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Thu, 10 Oct 2019 11:25:48 -0400
+Subject: [PATCH 4262/4736] drm/amd/display: fix hubbub deadline programing
+
+[Why]
+Fix the programming of DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A.
+Was not filled in.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 +
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 9c96242f0ad9..b6ec81096d3a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2632,6 +2632,7 @@ static void dcn20_calculate_wm(
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ 	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ 	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
++	context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ #endif
+ 
+ 	if (vlevel < 2) {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 910c850701af..ff32c7380efb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1009,6 +1009,7 @@ static void calculate_wm_set_for_vlevel(
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ 	wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
+ 	wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
++	wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
+ #endif
+ 	dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4263-drm-amd-display-Apply-vactive-dram-clock-change-work.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4263-drm-amd-display-Apply-vactive-dram-clock-change-work.patch
new file mode 100644
index 00000000..01984706
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4263-drm-amd-display-Apply-vactive-dram-clock-change-work.patch
@@ -0,0 +1,33 @@
+From b1e8156d48159d180922edeb7083e491477ebcca Mon Sep 17 00:00:00 2001
+From: Joshua Aberback <joshua.aberback@amd.com>
+Date: Fri, 11 Oct 2019 15:49:07 -0400
+Subject: [PATCH 4263/4736] drm/amd/display: Apply vactive dram clock change
+ workaround to dcn2 DMLv2
+
+[Why]
+This workaround was put in dcn2 DMLv1, and now we need it in DMLv2.
+
+Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c   | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+index 841ed6c23f93..3c70dd577292 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+@@ -2611,7 +2611,8 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
+ 			mode_lib->vba.MinActiveDRAMClockChangeMargin
+ 					+ mode_lib->vba.DRAMClockChangeLatency;
+ 
+-	if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
++	if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
++		mode_lib->vba.DRAMClockChangeWatermark += 25;
+ 		mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
+ 	} else {
+ 		if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4264-drm-amdgpu-vcn-Enable-VCN2.5-encoding.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4264-drm-amdgpu-vcn-Enable-VCN2.5-encoding.patch
new file mode 100644
index 00000000..bdad93ff
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4264-drm-amdgpu-vcn-Enable-VCN2.5-encoding.patch
@@ -0,0 +1,35 @@
+From f263c1b507bfcd6050838e722537cf72c2efe0a1 Mon Sep 17 00:00:00 2001
+From: James Zhu <James.Zhu@amd.com>
+Date: Tue, 22 Oct 2019 10:40:45 -0400
+Subject: [PATCH 4264/4736] drm/amdgpu/vcn: Enable VCN2.5 encoding
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+After VCN2.5 firmware (Version ENC: 1.1  Revision: 11),
+VCN2.5 encoding can work properly.
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Reviewed-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index d270df892223..ff6cc77ad0b0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -265,9 +265,6 @@ static int vcn_v2_5_hw_init(void *handle)
+ 
+ 		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ 			ring = &adev->vcn.inst[j].ring_enc[i];
+-			/* disable encode rings till the robustness of the FW */
+-			ring->sched.ready = false;
+-			continue;
+ 			r = amdgpu_ring_test_helper(ring);
+ 			if (r)
+ 				goto done;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4265-drm-amdgpu-add-VCN0-and-VCN1-needed-headers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4265-drm-amdgpu-add-VCN0-and-VCN1-needed-headers.patch
new file mode 100644
index 00000000..6d99cb7a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4265-drm-amdgpu-add-VCN0-and-VCN1-needed-headers.patch
@@ -0,0 +1,39 @@
+From d2bb67b8b61d4da39441647cf483eff12f1b1dc2 Mon Sep 17 00:00:00 2001
+From: Jane Jian <jane.jian@amd.com>
+Date: Thu, 17 Oct 2019 23:30:20 +0800
+Subject: [PATCH 4265/4736] drm/amdgpu: add VCN0 and VCN1 needed headers
+
+Add mmsch part registers
+
+Signed-off-by: Jane Jian <jane.jian@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h    | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h
+index cf2149cc12ee..90350f46a0c4 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h
+@@ -24,6 +24,18 @@
+ 
+ // addressBlock: uvd0_mmsch_dec
+ // base address: 0x1e000
++#define mmMMSCH_VF_VMID                                                                                0x000b
++#define mmMMSCH_VF_VMID_BASE_IDX                                                                       0
++#define mmMMSCH_VF_CTX_ADDR_LO                                                                         0x000c
++#define mmMMSCH_VF_CTX_ADDR_LO_BASE_IDX                                                                0
++#define mmMMSCH_VF_CTX_ADDR_HI                                                                         0x000d
++#define mmMMSCH_VF_CTX_ADDR_HI_BASE_IDX                                                                0
++#define mmMMSCH_VF_CTX_SIZE                                                                            0x000e
++#define mmMMSCH_VF_CTX_SIZE_BASE_IDX                                                                   0
++#define mmMMSCH_VF_MAILBOX_HOST                                                                        0x0012
++#define mmMMSCH_VF_MAILBOX_HOST_BASE_IDX                                                               0
++#define mmMMSCH_VF_MAILBOX_RESP                                                                        0x0013
++#define mmMMSCH_VF_MAILBOX_RESP_BASE_IDX                                                               0
+ 
+ 
+ // addressBlock: uvd0_jpegnpdec
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4266-drm-amd-powerplay-add-lock-protection-for-swSMU-APIs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4266-drm-amd-powerplay-add-lock-protection-for-swSMU-APIs.patch
new file mode 100644
index 00000000..cbfdf0d1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4266-drm-amd-powerplay-add-lock-protection-for-swSMU-APIs.patch
@@ -0,0 +1,1829 @@
+From dc6cf14a58b1339db33016faef4de4f2efbb300a Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Wed, 16 Oct 2019 14:43:07 +0800
+Subject: [PATCH 4266/4736] drm/amd/powerplay: add lock protection for swSMU
+ APIs V2
+
+This is a quick and low risk fix. Those APIs which
+are exposed to other IPs or to support sysfs/hwmon
+interfaces or DAL will have lock protection. Meanwhile
+no lock protection is enforced for swSMU internal used
+APIs. Future optimization is needed.
+
+V2: strip the lock protection for all swSMU internal APIs
+
+Change-Id: I8392652c9da1574a85acd9b171f04380f3630852
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Acked-by: Feifei Xu <Feifei.Xu@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c       |   6 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h       |   6 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c        |  23 +-
+ .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c  |   6 +-
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 700 ++++++++++++++++--
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  |   3 -
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    | 162 ++--
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    |  15 +-
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c    |  14 +-
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     |  22 +-
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c     |   3 -
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c    |  20 +-
+ 12 files changed, 781 insertions(+), 199 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+index 263265245e19..28d32725285b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+@@ -912,7 +912,8 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low)
+ 	if (is_support_sw_smu(adev)) {
+ 		ret = smu_get_dpm_freq_range(&adev->smu, SMU_GFXCLK,
+ 					     low ? &clk_freq : NULL,
+-					     !low ? &clk_freq : NULL);
++					     !low ? &clk_freq : NULL,
++					     true);
+ 		if (ret)
+ 			return 0;
+ 		return clk_freq * 100;
+@@ -930,7 +931,8 @@ int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low)
+ 	if (is_support_sw_smu(adev)) {
+ 		ret = smu_get_dpm_freq_range(&adev->smu, SMU_UCLK,
+ 					     low ? &clk_freq : NULL,
+-					     !low ? &clk_freq : NULL);
++					     !low ? &clk_freq : NULL,
++					     true);
+ 		if (ret)
+ 			return 0;
+ 		return clk_freq * 100;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+index 1c5c0fd76dbf..2cfb677272af 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+@@ -298,12 +298,6 @@ enum amdgpu_pcie_gen {
+ #define amdgpu_dpm_get_current_power_state(adev) \
+ 		((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
+ 
+-#define amdgpu_smu_get_current_power_state(adev) \
+-		((adev)->smu.ppt_funcs->get_current_power_state(&((adev)->smu)))
+-
+-#define amdgpu_smu_set_power_state(adev) \
+-		((adev)->smu.ppt_funcs->set_power_state(&((adev)->smu)))
+-
+ #define amdgpu_dpm_get_pp_num_states(adev, data) \
+ 		((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index 571d10de9eca..dd94467a3d5d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -158,7 +158,7 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev,
+ 
+ 	if (is_support_sw_smu(adev)) {
+ 		if (adev->smu.ppt_funcs->get_current_power_state)
+-			pm = amdgpu_smu_get_current_power_state(adev);
++			pm = smu_get_current_power_state(&adev->smu);
+ 		else
+ 			pm = adev->pm.dpm.user_state;
+ 	} else if (adev->powerplay.pp_funcs->get_current_power_state) {
+@@ -904,7 +904,7 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
+ 		return ret;
+ 
+ 	if (is_support_sw_smu(adev))
+-		ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask);
++		ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask, true);
+ 	else if (adev->powerplay.pp_funcs->force_clock_level)
+ 		ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
+ 
+@@ -951,7 +951,7 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
+ 		return ret;
+ 
+ 	if (is_support_sw_smu(adev))
+-		ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask);
++		ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask, true);
+ 	else if (adev->powerplay.pp_funcs->force_clock_level)
+ 		ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
+ 
+@@ -991,7 +991,7 @@ static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
+ 		return ret;
+ 
+ 	if (is_support_sw_smu(adev))
+-		ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask);
++		ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask, true);
+ 	else if (adev->powerplay.pp_funcs->force_clock_level)
+ 		ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
+ 
+@@ -1031,7 +1031,7 @@ static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
+ 		return ret;
+ 
+ 	if (is_support_sw_smu(adev))
+-		ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask);
++		ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask, true);
+ 	else if (adev->powerplay.pp_funcs->force_clock_level)
+ 		ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
+ 
+@@ -1071,7 +1071,7 @@ static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
+ 		return ret;
+ 
+ 	if (is_support_sw_smu(adev))
+-		ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask);
++		ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask, true);
+ 	else if (adev->powerplay.pp_funcs->force_clock_level)
+ 		ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
+ 
+@@ -1111,7 +1111,7 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
+ 		return ret;
+ 
+ 	if (is_support_sw_smu(adev))
+-		ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask);
++		ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask, true);
+ 	else if (adev->powerplay.pp_funcs->force_clock_level)
+ 		ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
+ 
+@@ -1303,7 +1303,7 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
+ 	}
+ 	parameter[parameter_size] = profile_mode;
+ 	if (is_support_sw_smu(adev))
+-		ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);
++		ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size, true);
+ 	else if (adev->powerplay.pp_funcs->set_power_profile_mode)
+ 		ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
+ 	if (!ret)
+@@ -2012,7 +2012,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
+ 	uint32_t limit = 0;
+ 
+ 	if (is_support_sw_smu(adev)) {
+-		smu_get_power_limit(&adev->smu, &limit, true);
++		smu_get_power_limit(&adev->smu, &limit, true, true);
+ 		return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
+ 	} else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
+ 		adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
+@@ -2030,7 +2030,7 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
+ 	uint32_t limit = 0;
+ 
+ 	if (is_support_sw_smu(adev)) {
+-		smu_get_power_limit(&adev->smu, &limit, false);
++		smu_get_power_limit(&adev->smu, &limit, false,  true);
+ 		return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
+ 	} else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
+ 		adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
+@@ -3011,7 +3011,8 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
+ 		struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
+ 		smu_handle_task(&adev->smu,
+ 				smu_dpm->dpm_level,
+-				AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
++				AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
++				true);
+ 	} else {
+ 		if (adev->powerplay.pp_funcs->dispatch_tasks) {
+ 			if (!amdgpu_device_has_dc_support(adev)) {
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+index 8a5eedb6a37a..c1b6abf2634c 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+@@ -866,7 +866,7 @@ enum pp_smu_status pp_nv_get_maximum_sustainable_clocks(
+ 	if (!smu->funcs->get_max_sustainable_clocks_by_dc)
+ 		return PP_SMU_RESULT_UNSUPPORTED;
+ 
+-	if (!smu->funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks))
++	if (!smu_get_max_sustainable_clocks_by_dc(smu, max_clocks))
+ 		return PP_SMU_RESULT_OK;
+ 
+ 	return PP_SMU_RESULT_FAIL;
+@@ -885,7 +885,7 @@ enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp,
+ 	if (!smu->ppt_funcs->get_uclk_dpm_states)
+ 		return PP_SMU_RESULT_UNSUPPORTED;
+ 
+-	if (!smu->ppt_funcs->get_uclk_dpm_states(smu,
++	if (!smu_get_uclk_dpm_states(smu,
+ 			clock_values_in_khz, num_states))
+ 		return PP_SMU_RESULT_OK;
+ 
+@@ -906,7 +906,7 @@ enum pp_smu_status pp_rn_get_dpm_clock_table(
+ 	if (!smu->ppt_funcs->get_dpm_clock_table)
+ 		return PP_SMU_RESULT_UNSUPPORTED;
+ 
+-	if (!smu->ppt_funcs->get_dpm_clock_table(smu, clock_table))
++	if (!smu_get_dpm_clock_table(smu, clock_table))
+ 		return PP_SMU_RESULT_OK;
+ 
+ 	return PP_SMU_RESULT_FAIL;
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index fb5a55091292..d748ad9c2159 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -67,6 +67,8 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
+ 	uint32_t sort_feature[SMU_FEATURE_COUNT];
+ 	uint64_t hw_feature_count = 0;
+ 
++	mutex_lock(&smu->mutex);
++
+ 	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+ 	if (ret)
+ 		goto failed;
+@@ -92,6 +94,8 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
+ 	}
+ 
+ failed:
++	mutex_unlock(&smu->mutex);
++
+ 	return size;
+ }
+ 
+@@ -149,9 +153,11 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
+ 	uint64_t feature_2_disabled = 0;
+ 	uint64_t feature_enables = 0;
+ 
++	mutex_lock(&smu->mutex);
++
+ 	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+ 	if (ret)
+-		return ret;
++		goto out;
+ 
+ 	feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
+ 
+@@ -161,14 +167,17 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
+ 	if (feature_2_enabled) {
+ 		ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
+ 		if (ret)
+-			return ret;
++			goto out;
+ 	}
+ 	if (feature_2_disabled) {
+ 		ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
+ 		if (ret)
+-			return ret;
++			goto out;
+ 	}
+ 
++out:
++	mutex_unlock(&smu->mutex);
++
+ 	return ret;
+ }
+ 
+@@ -254,7 +263,7 @@ int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ }
+ 
+ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+-			   uint32_t *min, uint32_t *max)
++			   uint32_t *min, uint32_t *max, bool lock_needed)
+ {
+ 	uint32_t clock_limit;
+ 	int ret = 0;
+@@ -262,6 +271,9 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ 	if (!min && !max)
+ 		return -EINVAL;
+ 
++	if (lock_needed)
++		mutex_lock(&smu->mutex);
++
+ 	if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
+ 		switch (clk_type) {
+ 		case SMU_MCLK:
+@@ -285,14 +297,17 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ 			*min = clock_limit / 100;
+ 		if (max)
+ 			*max = clock_limit / 100;
+-
+-		return 0;
++	} else {
++		/*
++		 * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
++		 * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
++		 */
++		ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
+ 	}
+-	/*
+-	 * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
+-	 * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
+-	 */
+-	ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
++
++	if (lock_needed)
++		mutex_unlock(&smu->mutex);
++
+ 	return ret;
+ }
+ 
+@@ -369,6 +384,8 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
+ {
+ 	int ret = 0;
+ 
++	mutex_lock(&smu->mutex);
++
+ 	switch (block_type) {
+ 	case AMD_IP_BLOCK_TYPE_UVD:
+ 		ret = smu_dpm_set_uvd_enable(smu, gate);
+@@ -386,13 +403,9 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
+ 		break;
+ 	}
+ 
+-	return ret;
+-}
++	mutex_unlock(&smu->mutex);
+ 
+-enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
+-{
+-	/* not support power state */
+-	return POWER_STATE_TYPE_DEFAULT;
++	return ret;
+ }
+ 
+ int smu_get_power_num_states(struct smu_context *smu,
+@@ -520,16 +533,23 @@ bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
+ int smu_sys_get_pp_table(struct smu_context *smu, void **table)
+ {
+ 	struct smu_table_context *smu_table = &smu->smu_table;
++	uint32_t powerplay_table_size;
+ 
+ 	if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
+ 		return -EINVAL;
+ 
++	mutex_lock(&smu->mutex);
++
+ 	if (smu_table->hardcode_pptable)
+ 		*table = smu_table->hardcode_pptable;
+ 	else
+ 		*table = smu_table->power_play_table;
+ 
+-	return smu_table->power_play_table_size;
++	powerplay_table_size = smu_table->power_play_table_size;
++
++	mutex_unlock(&smu->mutex);
++
++	return powerplay_table_size;
+ }
+ 
+ int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
+@@ -556,14 +576,11 @@ int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
+ 	memcpy(smu_table->hardcode_pptable, buf, size);
+ 	smu_table->power_play_table = smu_table->hardcode_pptable;
+ 	smu_table->power_play_table_size = size;
+-	mutex_unlock(&smu->mutex);
+ 
+ 	ret = smu_reset(smu);
+ 	if (ret)
+ 		pr_info("smu reset failed, ret = %d\n", ret);
+ 
+-	return ret;
+-
+ failed:
+ 	mutex_unlock(&smu->mutex);
+ 	return ret;
+@@ -726,11 +743,10 @@ static int smu_late_init(void *handle)
+ 	if (!smu->pm_enabled)
+ 		return 0;
+ 
+-	mutex_lock(&smu->mutex);
+ 	smu_handle_task(&adev->smu,
+ 			smu->smu_dpm.dpm_level,
+-			AMD_PP_TASK_COMPLETE_INIT);
+-	mutex_unlock(&smu->mutex);
++			AMD_PP_TASK_COMPLETE_INIT,
++			false);
+ 
+ 	return 0;
+ }
+@@ -1074,7 +1090,7 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ 		if (ret)
+ 			return ret;
+ 
+-		ret = smu_get_power_limit(smu, &smu->default_power_limit, true);
++		ret = smu_get_power_limit(smu, &smu->default_power_limit, true, false);
+ 		if (ret)
+ 			return ret;
+ 	}
+@@ -1160,15 +1176,19 @@ static int smu_start_smc_engine(struct smu_context *smu)
+ 
+ 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+ 		if (adev->asic_type < CHIP_NAVI10) {
+-			ret = smu_load_microcode(smu);
+-			if (ret)
+-				return ret;
++			if (smu->funcs->load_microcode) {
++				ret = smu->funcs->load_microcode(smu);
++				if (ret)
++					return ret;
++			}
+ 		}
+ 	}
+ 
+-	ret = smu_check_fw_status(smu);
+-	if (ret)
+-		pr_err("SMC is not ready\n");
++	if (smu->funcs->check_fw_status) {
++		ret = smu->funcs->check_fw_status(smu);
++		if (ret)
++			pr_err("SMC is not ready\n");
++	}
+ 
+ 	return ret;
+ }
+@@ -1335,8 +1355,6 @@ static int smu_resume(void *handle)
+ 
+ 	pr_info("SMU is resuming...\n");
+ 
+-	mutex_lock(&smu->mutex);
+-
+ 	ret = smu_start_smc_engine(smu);
+ 	if (ret) {
+ 		pr_err("SMU is not ready yet!\n");
+@@ -1356,13 +1374,11 @@ static int smu_resume(void *handle)
+ 
+ 	smu->disable_uclk_switch = 0;
+ 
+-	mutex_unlock(&smu->mutex);
+-
+ 	pr_info("SMU is resumed successfully!\n");
+ 
+ 	return 0;
++
+ failed:
+-	mutex_unlock(&smu->mutex);
+ 	return ret;
+ }
+ 
+@@ -1380,8 +1396,9 @@ int smu_display_configuration_change(struct smu_context *smu,
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	smu_set_deep_sleep_dcefclk(smu,
+-				   display_config->min_dcef_deep_sleep_set_clk / 100);
++	if (smu->funcs->set_deep_sleep_dcefclk)
++		smu->funcs->set_deep_sleep_dcefclk(smu,
++				display_config->min_dcef_deep_sleep_set_clk / 100);
+ 
+ 	for (index = 0; index < display_config->num_path_including_non_display; index++) {
+ 		if (display_config->displays[index].controller_id != 0)
+@@ -1559,9 +1576,9 @@ static int smu_default_set_performance_level(struct smu_context *smu, enum amd_d
+ 						 &soc_mask);
+ 		if (ret)
+ 			return ret;
+-		smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
+-		smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
+-		smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
++		smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
++		smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
++		smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
+ 		break;
+ 	case AMD_DPM_FORCED_LEVEL_MANUAL:
+ 	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
+@@ -1625,7 +1642,7 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
+ 		workload = smu->workload_setting[index];
+ 
+ 		if (smu->power_profile_mode != workload)
+-			smu_set_power_profile_mode(smu, &workload, 0);
++			smu_set_power_profile_mode(smu, &workload, 0, false);
+ 	}
+ 
+ 	return ret;
+@@ -1633,18 +1650,22 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
+ 
+ int smu_handle_task(struct smu_context *smu,
+ 		    enum amd_dpm_forced_level level,
+-		    enum amd_pp_task task_id)
++		    enum amd_pp_task task_id,
++		    bool lock_needed)
+ {
+ 	int ret = 0;
+ 
++	if (lock_needed)
++		mutex_lock(&smu->mutex);
++
+ 	switch (task_id) {
+ 	case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
+ 		ret = smu_pre_display_config_changed(smu);
+ 		if (ret)
+-			return ret;
++			goto out;
+ 		ret = smu_set_cpu_power_state(smu);
+ 		if (ret)
+-			return ret;
++			goto out;
+ 		ret = smu_adjust_power_state_dynamic(smu, level, false);
+ 		break;
+ 	case AMD_PP_TASK_COMPLETE_INIT:
+@@ -1655,6 +1676,10 @@ int smu_handle_task(struct smu_context *smu,
+ 		break;
+ 	}
+ 
++out:
++	if (lock_needed)
++		mutex_unlock(&smu->mutex);
++
+ 	return ret;
+ }
+ 
+@@ -1687,7 +1712,7 @@ int smu_switch_power_profile(struct smu_context *smu,
+ 	}
+ 
+ 	if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
+-		smu_set_power_profile_mode(smu, &workload, 0);
++		smu_set_power_profile_mode(smu, &workload, 0, false);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -1717,12 +1742,19 @@ int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_lev
+ 	if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
+ 		return -EINVAL;
+ 
++	mutex_lock(&smu->mutex);
++
+ 	ret = smu_enable_umd_pstate(smu, &level);
+-	if (ret)
++	if (ret) {
++		mutex_unlock(&smu->mutex);
+ 		return ret;
++	}
+ 
+ 	ret = smu_handle_task(smu, level,
+-			      AMD_PP_TASK_READJUST_POWER_STATE);
++			      AMD_PP_TASK_READJUST_POWER_STATE,
++			      false);
++
++	mutex_unlock(&smu->mutex);
+ 
+ 	return ret;
+ }
+@@ -1740,7 +1772,8 @@ int smu_set_display_count(struct smu_context *smu, uint32_t count)
+ 
+ int smu_force_clk_levels(struct smu_context *smu,
+ 			 enum smu_clk_type clk_type,
+-			 uint32_t mask)
++			 uint32_t mask,
++			 bool lock_needed)
+ {
+ 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+ 	int ret = 0;
+@@ -1750,9 +1783,15 @@ int smu_force_clk_levels(struct smu_context *smu,
+ 		return -EINVAL;
+ 	}
+ 
++	if (lock_needed)
++		mutex_lock(&smu->mutex);
++
+ 	if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
+ 		ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
+ 
++	if (lock_needed)
++		mutex_unlock(&smu->mutex);
++
+ 	return ret;
+ }
+ 
+@@ -1770,6 +1809,8 @@ int smu_set_mp1_state(struct smu_context *smu,
+ 	if (!smu->pm_enabled)
+ 		return 0;
+ 
++	mutex_lock(&smu->mutex);
++
+ 	switch (mp1_state) {
+ 	case PP_MP1_STATE_SHUTDOWN:
+ 		msg = SMU_MSG_PrepareMp1ForShutdown;
+@@ -1782,17 +1823,22 @@ int smu_set_mp1_state(struct smu_context *smu,
+ 		break;
+ 	case PP_MP1_STATE_NONE:
+ 	default:
++		mutex_unlock(&smu->mutex);
+ 		return 0;
+ 	}
+ 
+ 	/* some asics may not support those messages */
+-	if (smu_msg_get_index(smu, msg) < 0)
++	if (smu_msg_get_index(smu, msg) < 0) {
++		mutex_unlock(&smu->mutex);
+ 		return 0;
++	}
+ 
+ 	ret = smu_send_smc_msg(smu, msg);
+ 	if (ret)
+ 		pr_err("[PrepareMp1] Failed!\n");
+ 
++	mutex_unlock(&smu->mutex);
++
+ 	return ret;
+ }
+ 
+@@ -1812,10 +1858,14 @@ int smu_set_df_cstate(struct smu_context *smu,
+ 	if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
+ 		return 0;
+ 
++	mutex_lock(&smu->mutex);
++
+ 	ret = smu->ppt_funcs->set_df_cstate(smu, state);
+ 	if (ret)
+ 		pr_err("[SetDfCstate] failed!\n");
+ 
++	mutex_unlock(&smu->mutex);
++
+ 	return ret;
+ }
+ 
+@@ -1843,6 +1893,8 @@ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
+ 	struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
+ 	void *table = watermarks->cpu_addr;
+ 
++	mutex_lock(&smu->mutex);
++
+ 	if (!smu->disable_watermark &&
+ 			smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
+ 			smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+@@ -1851,6 +1903,8 @@ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
+ 		smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
+ 	}
+ 
++	mutex_unlock(&smu->mutex);
++
+ 	return ret;
+ }
+ 
+@@ -1890,3 +1944,549 @@ const struct amdgpu_ip_block_version smu_v12_0_ip_block =
+ 	.rev = 0,
+ 	.funcs = &smu_ip_funcs,
+ };
++
++int smu_load_microcode(struct smu_context *smu)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->load_microcode)
++		ret = smu->funcs->load_microcode(smu);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_check_fw_status(struct smu_context *smu)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->check_fw_status)
++		ret = smu->funcs->check_fw_status(smu);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->set_gfx_cgpg)
++		ret = smu->funcs->set_gfx_cgpg(smu, enabled);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->set_fan_speed_rpm)
++		ret = smu->funcs->set_fan_speed_rpm(smu, speed);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_get_power_limit(struct smu_context *smu,
++			uint32_t *limit,
++			bool def,
++			bool lock_needed)
++{
++	int ret = 0;
++
++	if (lock_needed)
++		mutex_lock(&smu->mutex);
++
++	if (smu->ppt_funcs->get_power_limit)
++		ret = smu->ppt_funcs->get_power_limit(smu, limit, def);
++
++	if (lock_needed)
++		mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->set_power_limit)
++		ret = smu->funcs->set_power_limit(smu, limit);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->ppt_funcs->print_clk_levels)
++		ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->ppt_funcs->get_od_percentage)
++		ret = smu->ppt_funcs->get_od_percentage(smu, type);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->ppt_funcs->set_od_percentage)
++		ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_od_edit_dpm_table(struct smu_context *smu,
++			  enum PP_OD_DPM_TABLE_COMMAND type,
++			  long *input, uint32_t size)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->ppt_funcs->od_edit_dpm_table)
++		ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_read_sensor(struct smu_context *smu,
++		    enum amd_pp_sensors sensor,
++		    void *data, uint32_t *size)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->ppt_funcs->read_sensor)
++		ret = smu->ppt_funcs->read_sensor(smu, sensor, data, size);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->ppt_funcs->get_power_profile_mode)
++		ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_set_power_profile_mode(struct smu_context *smu,
++			       long *param,
++			       uint32_t param_size,
++			       bool lock_needed)
++{
++	int ret = 0;
++
++	if (lock_needed)
++		mutex_lock(&smu->mutex);
++
++	if (smu->ppt_funcs->set_power_profile_mode)
++		ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
++
++	if (lock_needed)
++		mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++
++int smu_get_fan_control_mode(struct smu_context *smu)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->get_fan_control_mode)
++		ret = smu->funcs->get_fan_control_mode(smu);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_set_fan_control_mode(struct smu_context *smu, int value)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->set_fan_control_mode)
++		ret = smu->funcs->set_fan_control_mode(smu, value);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->ppt_funcs->get_fan_speed_percent)
++		ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->set_fan_speed_percent)
++		ret = smu->funcs->set_fan_speed_percent(smu, speed);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->ppt_funcs->get_fan_speed_rpm)
++		ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->set_deep_sleep_dcefclk)
++		ret = smu->funcs->set_deep_sleep_dcefclk(smu, clk);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->set_active_display_count)
++		ret = smu->funcs->set_active_display_count(smu, count);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_get_clock_by_type(struct smu_context *smu,
++			  enum amd_pp_clock_type type,
++			  struct amd_pp_clocks *clocks)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->get_clock_by_type)
++		ret = smu->funcs->get_clock_by_type(smu, type, clocks);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_get_max_high_clocks(struct smu_context *smu,
++			    struct amd_pp_simple_clock_info *clocks)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->get_max_high_clocks)
++		ret = smu->funcs->get_max_high_clocks(smu, clocks);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_get_clock_by_type_with_latency(struct smu_context *smu,
++				       enum smu_clk_type clk_type,
++				       struct pp_clock_levels_with_latency *clocks)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->ppt_funcs->get_clock_by_type_with_latency)
++		ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
++				       enum amd_pp_clock_type type,
++				       struct pp_clock_levels_with_voltage *clocks)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->ppt_funcs->get_clock_by_type_with_voltage)
++		ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++
++int smu_display_clock_voltage_request(struct smu_context *smu,
++				      struct pp_display_clock_request *clock_req)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->display_clock_voltage_request)
++		ret = smu->funcs->display_clock_voltage_request(smu, clock_req);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++
++int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
++{
++	int ret = -EINVAL;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->ppt_funcs->display_disable_memory_clock_switch)
++		ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_notify_smu_enable_pwe(struct smu_context *smu)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->notify_smu_enable_pwe)
++		ret = smu->funcs->notify_smu_enable_pwe(smu);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_set_xgmi_pstate(struct smu_context *smu,
++			uint32_t pstate)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->set_xgmi_pstate)
++		ret = smu->funcs->set_xgmi_pstate(smu, pstate);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_set_azalia_d3_pme(struct smu_context *smu)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->set_azalia_d3_pme)
++		ret = smu->funcs->set_azalia_d3_pme(smu);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++bool smu_baco_is_support(struct smu_context *smu)
++{
++	bool ret = false;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->baco_is_support)
++		ret = smu->funcs->baco_is_support(smu);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
++{
++	if (smu->funcs->baco_get_state)
++		return -EINVAL;
++
++	mutex_lock(&smu->mutex);
++	*state = smu->funcs->baco_get_state(smu);
++	mutex_unlock(&smu->mutex);
++
++	return 0;
++}
++
++int smu_baco_reset(struct smu_context *smu)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->baco_reset)
++		ret = smu->funcs->baco_reset(smu);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_mode2_reset(struct smu_context *smu)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->mode2_reset)
++		ret = smu->funcs->mode2_reset(smu);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
++					 struct pp_smu_nv_clock_table *max_clocks)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->funcs->get_max_sustainable_clocks_by_dc)
++		ret = smu->funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_get_uclk_dpm_states(struct smu_context *smu,
++			    unsigned int *clock_values_in_khz,
++			    unsigned int *num_states)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->ppt_funcs->get_uclk_dpm_states)
++		ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
++{
++	enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->ppt_funcs->get_current_power_state)
++		pm_state = smu->ppt_funcs->get_current_power_state(smu);
++
++	mutex_unlock(&smu->mutex);
++
++	return pm_state;
++}
++
++int smu_get_dpm_clock_table(struct smu_context *smu,
++			    struct dpm_clocks *clock_table)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->ppt_funcs->get_dpm_clock_table)
++		ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index b33e451c7133..90b124dbdc14 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -763,8 +763,6 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
+ 	uint32_t soft_min_level, soft_max_level;
+ 	int ret = 0;
+ 
+-	mutex_lock(&(smu->mutex));
+-
+ 	soft_min_level = mask ? (ffs(mask) - 1) : 0;
+ 	soft_max_level = mask ? (fls(mask) - 1) : 0;
+ 
+@@ -883,7 +881,6 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
+ 		break;
+ 	}
+ 
+-	mutex_unlock(&(smu->mutex));
+ 	return ret;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index bf13bf33ba0c..3a1245f369a2 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -563,18 +563,17 @@ struct smu_funcs
+ 	((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
+ #define smu_fini_power(smu) \
+ 	((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
+-#define smu_load_microcode(smu) \
+-	((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
+-#define smu_check_fw_status(smu) \
+-	((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
++int smu_load_microcode(struct smu_context *smu);
++
++int smu_check_fw_status(struct smu_context *smu);
++
+ #define smu_setup_pptable(smu) \
+ 	((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
+ #define smu_powergate_sdma(smu, gate) \
+ 	((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
+ #define smu_powergate_vcn(smu, gate) \
+ 	((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
+-#define smu_set_gfx_cgpg(smu, enabled) \
+-	((smu)->funcs->set_gfx_cgpg ? (smu)->funcs->set_gfx_cgpg((smu), (enabled)) : 0)
++int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
+ #define smu_get_vbios_bootup_values(smu) \
+ 	((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
+ #define smu_get_clk_info_from_vbios(smu) \
+@@ -605,8 +604,8 @@ struct smu_funcs
+ 	((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
+ #define smu_set_default_od_settings(smu, initialize) \
+ 	((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
+-#define smu_set_fan_speed_rpm(smu, speed) \
+-	((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs->set_fan_speed_rpm((smu), (speed)) : 0)
++int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
++
+ #define smu_send_smc_msg(smu, msg) \
+ 	((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
+ #define smu_send_smc_msg_with_param(smu, msg, param) \
+@@ -637,20 +636,22 @@ struct smu_funcs
+ 	((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
+ #define smu_set_default_od8_settings(smu) \
+ 	((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
+-#define smu_get_power_limit(smu, limit, def) \
+-	((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit((smu), (limit), (def)) : 0)
+-#define smu_set_power_limit(smu, limit) \
+-	((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0)
++
++int smu_get_power_limit(struct smu_context *smu,
++			uint32_t *limit,
++			bool def,
++			bool lock_needed);
++
++int smu_set_power_limit(struct smu_context *smu, uint32_t limit);
+ #define smu_get_current_clk_freq(smu, clk_id, value) \
+ 	((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
+-#define smu_print_clk_levels(smu, clk_type, buf) \
+-	((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (clk_type), (buf)) : 0)
+-#define smu_get_od_percentage(smu, type) \
+-	((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
+-#define smu_set_od_percentage(smu, type, value) \
+-	((smu)->ppt_funcs->set_od_percentage ? (smu)->ppt_funcs->set_od_percentage((smu), (type), (value)) : 0)
+-#define smu_od_edit_dpm_table(smu, type, input, size) \
+-	((smu)->ppt_funcs->od_edit_dpm_table ? (smu)->ppt_funcs->od_edit_dpm_table((smu), (type), (input), (size)) : 0)
++int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
++int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type);
++int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value);
++
++int smu_od_edit_dpm_table(struct smu_context *smu,
++			  enum PP_OD_DPM_TABLE_COMMAND type,
++			  long *input, uint32_t size);
+ #define smu_tables_init(smu, tab) \
+ 	((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
+ #define smu_set_thermal_fan_table(smu) \
+@@ -659,14 +660,18 @@ struct smu_funcs
+ 	((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
+ #define smu_stop_thermal_control(smu) \
+ 	((smu)->funcs->stop_thermal_control? (smu)->funcs->stop_thermal_control((smu)) : 0)
+-#define smu_read_sensor(smu, sensor, data, size) \
+-	((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
++
++int smu_read_sensor(struct smu_context *smu,
++		    enum amd_pp_sensors sensor,
++		    void *data, uint32_t *size);
+ #define smu_smc_read_sensor(smu, sensor, data, size) \
+ 	((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
+-#define smu_get_power_profile_mode(smu, buf) \
+-	((smu)->ppt_funcs->get_power_profile_mode ? (smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
+-#define smu_set_power_profile_mode(smu, param, param_size) \
+-	((smu)->ppt_funcs->set_power_profile_mode ? (smu)->ppt_funcs->set_power_profile_mode((smu), (param), (param_size)) : 0)
++int smu_get_power_profile_mode(struct smu_context *smu, char *buf);
++
++int smu_set_power_profile_mode(struct smu_context *smu,
++			       long *param,
++			       uint32_t param_size,
++			       bool lock_needed);
+ #define smu_pre_display_config_changed(smu) \
+ 	((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
+ #define smu_display_config_changed(smu) \
+@@ -683,16 +688,11 @@ struct smu_funcs
+ 	((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
+ #define smu_set_cpu_power_state(smu) \
+ 	((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
+-#define smu_get_fan_control_mode(smu) \
+-	((smu)->funcs->get_fan_control_mode ? (smu)->funcs->get_fan_control_mode((smu)) : 0)
+-#define smu_set_fan_control_mode(smu, value) \
+-	((smu)->funcs->set_fan_control_mode ? (smu)->funcs->set_fan_control_mode((smu), (value)) : 0)
+-#define smu_get_fan_speed_percent(smu, speed) \
+-	((smu)->ppt_funcs->get_fan_speed_percent ? (smu)->ppt_funcs->get_fan_speed_percent((smu), (speed)) : 0)
+-#define smu_set_fan_speed_percent(smu, speed) \
+-	((smu)->funcs->set_fan_speed_percent ? (smu)->funcs->set_fan_speed_percent((smu), (speed)) : 0)
+-#define smu_get_fan_speed_rpm(smu, speed) \
+-	((smu)->ppt_funcs->get_fan_speed_rpm ? (smu)->ppt_funcs->get_fan_speed_rpm((smu), (speed)) : 0)
++int smu_get_fan_control_mode(struct smu_context *smu);
++int smu_set_fan_control_mode(struct smu_context *smu, int value);
++int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed);
++int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
++int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed);
+ 
+ #define smu_msg_get_index(smu, msg) \
+ 	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
+@@ -710,38 +710,44 @@ struct smu_funcs
+ 	((smu)->ppt_funcs? ((smu)->ppt_funcs->run_btc? (smu)->ppt_funcs->run_btc((smu)) : 0) : 0)
+ #define smu_get_allowed_feature_mask(smu, feature_mask, num) \
+ 	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
+-#define smu_set_deep_sleep_dcefclk(smu, clk) \
+-	((smu)->funcs->set_deep_sleep_dcefclk ? (smu)->funcs->set_deep_sleep_dcefclk((smu), (clk)) : 0)
+-#define smu_set_active_display_count(smu, count) \
+-	((smu)->funcs->set_active_display_count ? (smu)->funcs->set_active_display_count((smu), (count)) : 0)
++int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk);
++int smu_set_active_display_count(struct smu_context *smu, uint32_t count);
+ #define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
+ 	((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
+-#define smu_get_clock_by_type(smu, type, clocks) \
+-	((smu)->funcs->get_clock_by_type ? (smu)->funcs->get_clock_by_type((smu), (type), (clocks)) : 0)
+-#define smu_get_max_high_clocks(smu, clocks) \
+-	((smu)->funcs->get_max_high_clocks ? (smu)->funcs->get_max_high_clocks((smu), (clocks)) : 0)
+-#define smu_get_clock_by_type_with_latency(smu, clk_type, clocks) \
+-	((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)->ppt_funcs->get_clock_by_type_with_latency((smu), (clk_type), (clocks)) : 0)
+-#define smu_get_clock_by_type_with_voltage(smu, type, clocks) \
+-	((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
+-#define smu_display_clock_voltage_request(smu, clock_req) \
+-	((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
+-#define smu_display_disable_memory_clock_switch(smu, disable_memory_clock_switch) \
+-	((smu)->ppt_funcs->display_disable_memory_clock_switch ? (smu)->ppt_funcs->display_disable_memory_clock_switch((smu), (disable_memory_clock_switch)) : -EINVAL)
++
++int smu_get_clock_by_type(struct smu_context *smu,
++			  enum amd_pp_clock_type type,
++			  struct amd_pp_clocks *clocks);
++
++int smu_get_max_high_clocks(struct smu_context *smu,
++			    struct amd_pp_simple_clock_info *clocks);
++
++int smu_get_clock_by_type_with_latency(struct smu_context *smu,
++				       enum smu_clk_type clk_type,
++				       struct pp_clock_levels_with_latency *clocks);
++
++int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
++				       enum amd_pp_clock_type type,
++				       struct pp_clock_levels_with_voltage *clocks);
++
++int smu_display_clock_voltage_request(struct smu_context *smu,
++				      struct pp_display_clock_request *clock_req);
++int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch);
+ #define smu_get_dal_power_level(smu, clocks) \
+ 	((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
+ #define smu_get_perf_level(smu, designation, level) \
+ 	((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
+ #define smu_get_current_shallow_sleep_clocks(smu, clocks) \
+ 	((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
+-#define smu_notify_smu_enable_pwe(smu) \
+-	((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
++int smu_notify_smu_enable_pwe(struct smu_context *smu);
++
+ #define smu_dpm_set_uvd_enable(smu, enable) \
+ 	((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
+ #define smu_dpm_set_vce_enable(smu, enable) \
+ 	((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
+-#define smu_set_xgmi_pstate(smu, pstate) \
+-		((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
++
++int smu_set_xgmi_pstate(struct smu_context *smu,
++			uint32_t pstate);
+ #define smu_set_watermarks_table(smu, tab, clock_ranges) \
+ 	((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
+ #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
+@@ -752,22 +758,18 @@ struct smu_funcs
+ 	((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
+ #define smu_register_irq_handler(smu) \
+ 	((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
+-#define smu_set_azalia_d3_pme(smu) \
+-	((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs->set_azalia_d3_pme((smu)) : 0)
++
++int smu_set_azalia_d3_pme(struct smu_context *smu);
+ #define smu_get_dpm_ultimate_freq(smu, param, min, max) \
+ 		((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
+-#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
+-	((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
+-#define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
+-	((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
+-#define smu_baco_is_support(smu) \
+-	((smu)->funcs->baco_is_support? (smu)->funcs->baco_is_support((smu)) : false)
+-#define smu_baco_get_state(smu, state) \
+-	((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0)
+-#define smu_baco_reset(smu) \
+-	((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
+-#define smu_mode2_reset(smu) \
+-	((smu)->funcs->mode2_reset? (smu)->funcs->mode2_reset((smu)) : 0)
++
++bool smu_baco_is_support(struct smu_context *smu);
++
++int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
++
++int smu_baco_reset(struct smu_context *smu);
++
++int smu_mode2_reset(struct smu_context *smu);
+ #define smu_asic_set_performance_level(smu, level) \
+ 	((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
+ #define smu_dump_pptable(smu) \
+@@ -776,8 +778,6 @@ struct smu_funcs
+ 		((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EINVAL)
+ #define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
+ 		((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
+-#define smu_get_dpm_clock_table(smu, clock_table) \
+-		((smu)->ppt_funcs->get_dpm_clock_table ? (smu)->ppt_funcs->get_dpm_clock_table((smu), (clock_table)) : -EINVAL)
+ 
+ #define smu_override_pcie_parameters(smu) \
+ 		((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0)
+@@ -831,7 +831,8 @@ extern int smu_get_current_clocks(struct smu_context *smu,
+ extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
+ extern int smu_handle_task(struct smu_context *smu,
+ 			   enum amd_dpm_forced_level level,
+-			   enum amd_pp_task task_id);
++			   enum amd_pp_task task_id,
++			   bool lock_needed);
+ int smu_switch_power_profile(struct smu_context *smu,
+ 			     enum PP_SMC_POWER_PROFILE type,
+ 			     bool en);
+@@ -841,7 +842,7 @@ int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_typ
+ int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
+ 			    uint32_t *value);
+ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+-			   uint32_t *min, uint32_t *max);
++			   uint32_t *min, uint32_t *max, bool lock_needed);
+ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ 			    uint32_t min, uint32_t max);
+ int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
+@@ -856,10 +857,21 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
+ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
+ int smu_force_clk_levels(struct smu_context *smu,
+ 			 enum smu_clk_type clk_type,
+-			 uint32_t mask);
++			 uint32_t mask,
++			 bool lock_needed);
+ int smu_set_mp1_state(struct smu_context *smu,
+ 		      enum pp_mp1_state mp1_state);
+ int smu_set_df_cstate(struct smu_context *smu,
+ 		      enum pp_df_cstate state);
+ 
++int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
++					 struct pp_smu_nv_clock_table *max_clocks);
++
++int smu_get_uclk_dpm_states(struct smu_context *smu,
++			    unsigned int *clock_values_in_khz,
++			    unsigned int *num_states);
++
++int smu_get_dpm_clock_table(struct smu_context *smu,
++			    struct dpm_clocks *clock_table);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index b88aae9bb242..ead40b2840f9 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -795,13 +795,13 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu)
+ 	int ret = 0;
+ 	uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
+ 
+-	ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL);
++	ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
+ 	if (ret)
+ 		return ret;
+ 
+ 	smu->pstate_sclk = min_sclk_freq * 100;
+ 
+-	ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL);
++	ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -854,7 +854,7 @@ static int navi10_pre_display_config_changed(struct smu_context *smu)
+ 		return ret;
+ 
+ 	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
+-		ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq);
++		ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
+ 		if (ret)
+ 			return ret;
+ 		ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
+@@ -904,7 +904,7 @@ static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
+ 
+ 	for (i = 0; i < ARRAY_SIZE(clks); i++) {
+ 		clk_type = clks[i];
+-		ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
++		ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
+ 		if (ret)
+ 			return ret;
+ 
+@@ -931,7 +931,7 @@ static int navi10_unforce_dpm_levels(struct smu_context *smu)
+ 
+ 	for (i = 0; i < ARRAY_SIZE(clks); i++) {
+ 		clk_type = clks[i];
+-		ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
++		ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
+ 		if (ret)
+ 			return ret;
+ 
+@@ -1266,7 +1266,10 @@ static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
+ 	if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
+ 		clock_req.clock_type = amd_pp_dcef_clock;
+ 		clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
+-		if (!smu_display_clock_voltage_request(smu, &clock_req)) {
++
++		if (smu->funcs->display_clock_voltage_request)
++			ret = smu->funcs->display_clock_voltage_request(smu, &clock_req);
++		if (!ret) {
+ 			if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
+ 				ret = smu_send_smc_msg_with_param(smu,
+ 								  SMU_MSG_SetMinDeepSleepDcefclk,
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 57930c9e22ff..0203da74b7d5 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -194,7 +194,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
+ 	case SMU_SCLK:
+ 		/* retirve table returned paramters unit is MHz */
+ 		cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
+-		ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min, &max);
++		ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min, &max, false);
+ 		if (!ret) {
+ 			/* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
+ 			if (cur_value  == max)
+@@ -251,7 +251,6 @@ static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context
+ 	    !smu_dpm_ctx->dpm_current_power_state)
+ 		return -EINVAL;
+ 
+-	mutex_lock(&(smu->mutex));
+ 	switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
+ 	case SMU_STATE_UI_LABEL_BATTERY:
+ 		pm_type = POWER_STATE_TYPE_BATTERY;
+@@ -269,7 +268,6 @@ static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context
+ 			pm_type = POWER_STATE_TYPE_DEFAULT;
+ 		break;
+ 	}
+-	mutex_unlock(&(smu->mutex));
+ 
+ 	return pm_type;
+ }
+@@ -314,7 +312,7 @@ static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
+ 
+ 	for (i = 0; i < ARRAY_SIZE(clks); i++) {
+ 		clk_type = clks[i];
+-		ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
++		ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
+ 		if (ret)
+ 			return ret;
+ 
+@@ -348,7 +346,7 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
+ 
+ 		clk_type = clk_feature_map[i].clk_type;
+ 
+-		ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
++		ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
+ 		if (ret)
+ 			return ret;
+ 
+@@ -469,7 +467,7 @@ static int renoir_force_clk_levels(struct smu_context *smu,
+ 			return -EINVAL;
+ 		}
+ 
+-		ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min_freq, &max_freq);
++		ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min_freq, &max_freq, false);
+ 		if (ret)
+ 			return ret;
+ 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
+@@ -545,7 +543,7 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu)
+ 	int ret = 0;
+ 	uint32_t sclk_freq = 0, uclk_freq = 0;
+ 
+-	ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL, &sclk_freq);
++	ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL, &sclk_freq, false);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -553,7 +551,7 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu)
+ 	if (ret)
+ 		return ret;
+ 
+-	ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &uclk_freq);
++	ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &uclk_freq, false);
+ 	if (ret)
+ 		return ret;
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index ac02bcd24da0..54f9d3dd837f 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -792,8 +792,11 @@ static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
+ 	if (!table_context)
+ 		return -EINVAL;
+ 
+-	return smu_set_deep_sleep_dcefclk(smu,
+-					  table_context->boot_values.dcefclk / 100);
++	if (smu->funcs->set_deep_sleep_dcefclk)
++		return smu->funcs->set_deep_sleep_dcefclk(smu,
++				table_context->boot_values.dcefclk / 100);
++
++	return 0;
+ }
+ 
+ static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
+@@ -1308,9 +1311,7 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
+ 		if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
+ 			return 0;
+ 
+-		mutex_lock(&smu->mutex);
+ 		ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0);
+-		mutex_unlock(&smu->mutex);
+ 
+ 		if(clk_select == SMU_UCLK)
+ 			smu->hard_min_uclk_req_from_dal = clk_freq;
+@@ -1333,12 +1334,10 @@ static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
+ 	case CHIP_NAVI12:
+ 		if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
+ 			return 0;
+-		mutex_lock(&smu->mutex);
+ 		if (enable)
+ 			ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
+ 		else
+ 			ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
+-		mutex_unlock(&smu->mutex);
+ 		break;
+ 	default:
+ 		break;
+@@ -1454,10 +1453,9 @@ static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
+ 	if (!speed)
+ 		return -EINVAL;
+ 
+-	mutex_lock(&(smu->mutex));
+ 	ret = smu_v11_0_auto_fan_control(smu, 0);
+ 	if (ret)
+-		goto set_fan_speed_rpm_failed;
++		return ret;
+ 
+ 	crystal_clock_freq = amdgpu_asic_get_xclk(adev);
+ 	tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
+@@ -1468,8 +1466,6 @@ static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
+ 
+ 	ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
+ 
+-set_fan_speed_rpm_failed:
+-	mutex_unlock(&(smu->mutex));
+ 	return ret;
+ }
+ 
+@@ -1480,11 +1476,9 @@ static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
+ 				     uint32_t pstate)
+ {
+ 	int ret = 0;
+-	mutex_lock(&(smu->mutex));
+ 	ret = smu_send_smc_msg_with_param(smu,
+ 					  SMU_MSG_SetXgmiMode,
+ 					  pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
+-	mutex_unlock(&(smu->mutex));
+ 	return ret;
+ }
+ 
+@@ -1596,9 +1590,7 @@ static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
+ {
+ 	int ret = 0;
+ 
+-	mutex_lock(&smu->mutex);
+ 	ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
+-	mutex_unlock(&smu->mutex);
+ 
+ 	return ret;
+ }
+@@ -1695,7 +1687,6 @@ static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ 	int ret = 0, clk_id = 0;
+ 	uint32_t param = 0;
+ 
+-	mutex_lock(&smu->mutex);
+ 	clk_id = smu_clk_get_index(smu, clk_type);
+ 	if (clk_id < 0) {
+ 		ret = -EINVAL;
+@@ -1722,7 +1713,6 @@ static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ 	}
+ 
+ failed:
+-	mutex_unlock(&smu->mutex);
+ 	return ret;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index cac4269cf1d1..6b9eef20554b 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -316,8 +316,6 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ 	int ret = 0;
+ 	uint32_t mclk_mask, soc_mask;
+ 
+-	mutex_lock(&smu->mutex);
+-
+ 	if (max) {
+ 		ret = smu_get_profiling_clk_mask(smu, AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
+ 						 NULL,
+@@ -387,7 +385,6 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ 		}
+ 	}
+ failed:
+-	mutex_unlock(&smu->mutex);
+ 	return ret;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index a76ffd58404e..c249df9256c7 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -635,7 +635,6 @@ amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
+ 	    !smu_dpm_ctx->dpm_current_power_state)
+ 		return -EINVAL;
+ 
+-	mutex_lock(&(smu->mutex));
+ 	switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
+ 	case SMU_STATE_UI_LABEL_BATTERY:
+ 		pm_type = POWER_STATE_TYPE_BATTERY;
+@@ -653,7 +652,6 @@ amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
+ 			pm_type = POWER_STATE_TYPE_DEFAULT;
+ 		break;
+ 	}
+-	mutex_unlock(&(smu->mutex));
+ 
+ 	return pm_type;
+ }
+@@ -1277,8 +1275,6 @@ static int vega20_force_clk_levels(struct smu_context *smu,
+ 	uint32_t soft_min_level, soft_max_level, hard_min_level;
+ 	int ret = 0;
+ 
+-	mutex_lock(&(smu->mutex));
+-
+ 	soft_min_level = mask ? (ffs(mask) - 1) : 0;
+ 	soft_max_level = mask ? (fls(mask) - 1) : 0;
+ 
+@@ -1431,7 +1427,6 @@ static int vega20_force_clk_levels(struct smu_context *smu,
+ 		break;
+ 	}
+ 
+-	mutex_unlock(&(smu->mutex));
+ 	return ret;
+ }
+ 
+@@ -1446,8 +1441,6 @@ static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
+ 
+ 	dpm_table = smu_dpm->dpm_context;
+ 
+-	mutex_lock(&smu->mutex);
+-
+ 	switch (clk_type) {
+ 	case SMU_GFXCLK:
+ 		single_dpm_table = &(dpm_table->gfx_table);
+@@ -1469,7 +1462,6 @@ static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
+ 		ret = -EINVAL;
+ 	}
+ 
+-	mutex_unlock(&smu->mutex);
+ 	return ret;
+ }
+ 
+@@ -2542,8 +2534,6 @@ static int vega20_set_od_percentage(struct smu_context *smu,
+ 	int feature_enabled;
+ 	PPCLK_e clk_id;
+ 
+-	mutex_lock(&(smu->mutex));
+-
+ 	dpm_table = smu_dpm->dpm_context;
+ 	golden_table = smu_dpm->golden_dpm_context;
+ 
+@@ -2593,11 +2583,10 @@ static int vega20_set_od_percentage(struct smu_context *smu,
+ 	}
+ 
+ 	ret = smu_handle_task(smu, smu_dpm->dpm_level,
+-			      AMD_PP_TASK_READJUST_POWER_STATE);
++			      AMD_PP_TASK_READJUST_POWER_STATE,
++			      false);
+ 
+ set_od_failed:
+-	mutex_unlock(&(smu->mutex));
+-
+ 	return ret;
+ }
+ 
+@@ -2822,10 +2811,9 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu,
+ 	}
+ 
+ 	if (type == PP_OD_COMMIT_DPM_TABLE) {
+-		mutex_lock(&(smu->mutex));
+ 		ret = smu_handle_task(smu, smu_dpm->dpm_level,
+-				      AMD_PP_TASK_READJUST_POWER_STATE);
+-		mutex_unlock(&(smu->mutex));
++				      AMD_PP_TASK_READJUST_POWER_STATE,
++				      false);
+ 	}
+ 
+ 	return ret;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4267-drm-amd-powerplay-split-out-those-internal-used-swSM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4267-drm-amd-powerplay-split-out-those-internal-used-swSM.patch
new file mode 100644
index 00000000..4bb6270d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4267-drm-amd-powerplay-split-out-those-internal-used-swSM.patch
@@ -0,0 +1,555 @@
+From 3ec8ab435fb3ed0b87a4b782440df9d59ea16c21 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 17 Oct 2019 14:15:41 +0800
+Subject: [PATCH 4267/4736] drm/amd/powerplay: split out those internal used
+ swSMU APIs V2
+
+Those swSMU APIs used internally are moved to smu_internal.h while
+others are kept in amdgpu_smu.h.
+
+V2: give a better name smu_internal.h for the place to hold
+    those internal APIs
+
+Change-Id: Ib726ef7f65dee46e47a07680b71e6e043e459f42
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |   1 +
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  |   1 +
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    | 161 +-------------
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    |   1 +
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c    |   1 +
+ drivers/gpu/drm/amd/powerplay/smu_internal.h  | 204 ++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     |   1 +
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c     |   1 +
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c    |   1 +
+ 9 files changed, 212 insertions(+), 160 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/powerplay/smu_internal.h
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index d748ad9c2159..75c4e297b788 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -25,6 +25,7 @@
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
+ #include "amdgpu_smu.h"
++#include "smu_internal.h"
+ #include "soc15_common.h"
+ #include "smu_v11_0.h"
+ #include "smu_v12_0.h"
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 90b124dbdc14..a2262464d141 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -25,6 +25,7 @@
+ #include <linux/firmware.h>
+ #include "amdgpu.h"
+ #include "amdgpu_smu.h"
++#include "smu_internal.h"
+ #include "atomfirmware.h"
+ #include "amdgpu_atomfirmware.h"
+ #include "smu_v11_0.h"
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 3a1245f369a2..79fe32acc838 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -553,89 +553,13 @@ struct smu_funcs
+ 	int (*override_pcie_parameters)(struct smu_context *smu);
+ };
+ 
+-#define smu_init_microcode(smu) \
+-	((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
+-#define smu_init_smc_tables(smu) \
+-	((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
+-#define smu_fini_smc_tables(smu) \
+-	((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
+-#define smu_init_power(smu) \
+-	((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
+-#define smu_fini_power(smu) \
+-	((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
+ int smu_load_microcode(struct smu_context *smu);
+ 
+ int smu_check_fw_status(struct smu_context *smu);
+ 
+-#define smu_setup_pptable(smu) \
+-	((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
+-#define smu_powergate_sdma(smu, gate) \
+-	((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
+-#define smu_powergate_vcn(smu, gate) \
+-	((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
+ int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
+-#define smu_get_vbios_bootup_values(smu) \
+-	((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
+-#define smu_get_clk_info_from_vbios(smu) \
+-	((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
+-#define smu_check_pptable(smu) \
+-	((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
+-#define smu_parse_pptable(smu) \
+-	((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
+-#define smu_populate_smc_tables(smu) \
+-	((smu)->funcs->populate_smc_tables ? (smu)->funcs->populate_smc_tables((smu)) : 0)
+-#define smu_check_fw_version(smu) \
+-	((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
+-#define smu_write_pptable(smu) \
+-	((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
+-#define smu_set_min_dcef_deep_sleep(smu) \
+-	((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
+-#define smu_set_tool_table_location(smu) \
+-	((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
+-#define smu_notify_memory_pool_location(smu) \
+-	((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
+-#define smu_gfx_off_control(smu, enable) \
+-	((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
+-#define smu_set_last_dcef_min_deep_sleep_clk(smu) \
+-	((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
+-#define smu_system_features_control(smu, en) \
+-	((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
+-#define smu_init_max_sustainable_clocks(smu) \
+-	((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
+-#define smu_set_default_od_settings(smu, initialize) \
+-	((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
+-int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
+ 
+-#define smu_send_smc_msg(smu, msg) \
+-	((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
+-#define smu_send_smc_msg_with_param(smu, msg, param) \
+-	((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
+-#define smu_read_smc_arg(smu, arg) \
+-	((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
+-#define smu_alloc_dpm_context(smu) \
+-	((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
+-#define smu_init_display_count(smu, count) \
+-	((smu)->funcs->init_display_count ? (smu)->funcs->init_display_count((smu), (count)) : 0)
+-#define smu_feature_set_allowed_mask(smu) \
+-	((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
+-#define smu_feature_get_enabled_mask(smu, mask, num) \
+-	((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
+-#define smu_is_dpm_running(smu) \
+-	((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
+-#define smu_notify_display_change(smu) \
+-	((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
+-#define smu_store_powerplay_table(smu) \
+-	((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
+-#define smu_check_powerplay_table(smu) \
+-	((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
+-#define smu_append_powerplay_table(smu) \
+-	((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
+-#define smu_set_default_dpm_table(smu) \
+-	((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
+-#define smu_populate_umd_state_clk(smu) \
+-	((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
+-#define smu_set_default_od8_settings(smu) \
+-	((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
++int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
+ 
+ int smu_get_power_limit(struct smu_context *smu,
+ 			uint32_t *limit,
+@@ -643,8 +567,6 @@ int smu_get_power_limit(struct smu_context *smu,
+ 			bool lock_needed);
+ 
+ int smu_set_power_limit(struct smu_context *smu, uint32_t limit);
+-#define smu_get_current_clk_freq(smu, clk_id, value) \
+-	((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
+ int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
+ int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type);
+ int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value);
+@@ -652,68 +574,24 @@ int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint3
+ int smu_od_edit_dpm_table(struct smu_context *smu,
+ 			  enum PP_OD_DPM_TABLE_COMMAND type,
+ 			  long *input, uint32_t size);
+-#define smu_tables_init(smu, tab) \
+-	((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
+-#define smu_set_thermal_fan_table(smu) \
+-	((smu)->ppt_funcs->set_thermal_fan_table ? (smu)->ppt_funcs->set_thermal_fan_table((smu)) : 0)
+-#define smu_start_thermal_control(smu) \
+-	((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
+-#define smu_stop_thermal_control(smu) \
+-	((smu)->funcs->stop_thermal_control? (smu)->funcs->stop_thermal_control((smu)) : 0)
+ 
+ int smu_read_sensor(struct smu_context *smu,
+ 		    enum amd_pp_sensors sensor,
+ 		    void *data, uint32_t *size);
+-#define smu_smc_read_sensor(smu, sensor, data, size) \
+-	((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
+ int smu_get_power_profile_mode(struct smu_context *smu, char *buf);
+ 
+ int smu_set_power_profile_mode(struct smu_context *smu,
+ 			       long *param,
+ 			       uint32_t param_size,
+ 			       bool lock_needed);
+-#define smu_pre_display_config_changed(smu) \
+-	((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
+-#define smu_display_config_changed(smu) \
+-	((smu)->ppt_funcs->display_config_changed ? (smu)->ppt_funcs->display_config_changed((smu)) : 0)
+-#define smu_apply_clocks_adjust_rules(smu) \
+-	((smu)->ppt_funcs->apply_clocks_adjust_rules ? (smu)->ppt_funcs->apply_clocks_adjust_rules((smu)) : 0)
+-#define smu_notify_smc_dispaly_config(smu) \
+-	((smu)->ppt_funcs->notify_smc_dispaly_config ? (smu)->ppt_funcs->notify_smc_dispaly_config((smu)) : 0)
+-#define smu_force_dpm_limit_value(smu, highest) \
+-	((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
+-#define smu_unforce_dpm_levels(smu) \
+-	((smu)->ppt_funcs->unforce_dpm_levels ? (smu)->ppt_funcs->unforce_dpm_levels((smu)) : 0)
+-#define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
+-	((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
+-#define smu_set_cpu_power_state(smu) \
+-	((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
+ int smu_get_fan_control_mode(struct smu_context *smu);
+ int smu_set_fan_control_mode(struct smu_context *smu, int value);
+ int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed);
+ int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
+ int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed);
+ 
+-#define smu_msg_get_index(smu, msg) \
+-	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
+-#define smu_clk_get_index(smu, msg) \
+-	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_clk_index? (smu)->ppt_funcs->get_smu_clk_index((smu), (msg)) : -EINVAL) : -EINVAL)
+-#define smu_feature_get_index(smu, msg) \
+-	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_feature_index? (smu)->ppt_funcs->get_smu_feature_index((smu), (msg)) : -EINVAL) : -EINVAL)
+-#define smu_table_get_index(smu, tab) \
+-	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_table_index? (smu)->ppt_funcs->get_smu_table_index((smu), (tab)) : -EINVAL) : -EINVAL)
+-#define smu_power_get_index(smu, src) \
+-	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_power_index? (smu)->ppt_funcs->get_smu_power_index((smu), (src)) : -EINVAL) : -EINVAL)
+-#define smu_workload_get_type(smu, profile) \
+-	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_workload_type? (smu)->ppt_funcs->get_workload_type((smu), (profile)) : -EINVAL) : -EINVAL)
+-#define smu_run_btc(smu) \
+-	((smu)->ppt_funcs? ((smu)->ppt_funcs->run_btc? (smu)->ppt_funcs->run_btc((smu)) : 0) : 0)
+-#define smu_get_allowed_feature_mask(smu, feature_mask, num) \
+-	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
+ int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk);
+ int smu_set_active_display_count(struct smu_context *smu, uint32_t count);
+-#define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
+-	((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
+ 
+ int smu_get_clock_by_type(struct smu_context *smu,
+ 			  enum amd_pp_clock_type type,
+@@ -733,35 +611,12 @@ int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
+ int smu_display_clock_voltage_request(struct smu_context *smu,
+ 				      struct pp_display_clock_request *clock_req);
+ int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch);
+-#define smu_get_dal_power_level(smu, clocks) \
+-	((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
+-#define smu_get_perf_level(smu, designation, level) \
+-	((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
+-#define smu_get_current_shallow_sleep_clocks(smu, clocks) \
+-	((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
+ int smu_notify_smu_enable_pwe(struct smu_context *smu);
+ 
+-#define smu_dpm_set_uvd_enable(smu, enable) \
+-	((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
+-#define smu_dpm_set_vce_enable(smu, enable) \
+-	((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
+-
+ int smu_set_xgmi_pstate(struct smu_context *smu,
+ 			uint32_t pstate);
+-#define smu_set_watermarks_table(smu, tab, clock_ranges) \
+-	((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
+-#define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
+-	((smu)->ppt_funcs->get_current_clk_freq_by_table ? (smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0)
+-#define smu_thermal_temperature_range_update(smu, range, rw) \
+-	((smu)->ppt_funcs->thermal_temperature_range_update? (smu)->ppt_funcs->thermal_temperature_range_update((smu), (range), (rw)) : 0)
+-#define smu_get_thermal_temperature_range(smu, range) \
+-	((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
+-#define smu_register_irq_handler(smu) \
+-	((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
+ 
+ int smu_set_azalia_d3_pme(struct smu_context *smu);
+-#define smu_get_dpm_ultimate_freq(smu, param, min, max) \
+-		((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
+ 
+ bool smu_baco_is_support(struct smu_context *smu);
+ 
+@@ -770,20 +625,6 @@ int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
+ int smu_baco_reset(struct smu_context *smu);
+ 
+ int smu_mode2_reset(struct smu_context *smu);
+-#define smu_asic_set_performance_level(smu, level) \
+-	((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
+-#define smu_dump_pptable(smu) \
+-	((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0)
+-#define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) \
+-		((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EINVAL)
+-#define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
+-		((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
+-
+-#define smu_override_pcie_parameters(smu) \
+-		((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0)
+-
+-#define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) \
+-		((smu)->ppt_funcs->update_pcie_parameters ? (smu)->ppt_funcs->update_pcie_parameters((smu), (pcie_gen_cap), (pcie_width_cap)) : 0)
+ 
+ extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
+ 				   uint16_t *size, uint8_t *frev, uint8_t *crev,
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index ead40b2840f9..54d5c91dda23 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -25,6 +25,7 @@
+ #include <linux/firmware.h>
+ #include "amdgpu.h"
+ #include "amdgpu_smu.h"
++#include "smu_internal.h"
+ #include "atomfirmware.h"
+ #include "amdgpu_atomfirmware.h"
+ #include "smu_v11_0.h"
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 0203da74b7d5..6df91b1a9daa 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -23,6 +23,7 @@
+ 
+ #include "amdgpu.h"
+ #include "amdgpu_smu.h"
++#include "smu_internal.h"
+ #include "soc15_common.h"
+ #include "smu_v12_0_ppsmc.h"
+ #include "smu12_driver_if.h"
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+new file mode 100644
+index 000000000000..c26eede7e36a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+@@ -0,0 +1,204 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#ifndef __SMU_INTERNAL_H__
++#define __SMU_INTERNAL_H__
++
++#include "amdgpu_smu.h"
++
++#define smu_init_microcode(smu) \
++	((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
++#define smu_init_smc_tables(smu) \
++	((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
++#define smu_fini_smc_tables(smu) \
++	((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
++#define smu_init_power(smu) \
++	((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
++#define smu_fini_power(smu) \
++	((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
++
++#define smu_setup_pptable(smu) \
++	((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
++#define smu_powergate_sdma(smu, gate) \
++	((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
++#define smu_powergate_vcn(smu, gate) \
++	((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
++
++#define smu_get_vbios_bootup_values(smu) \
++	((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
++#define smu_get_clk_info_from_vbios(smu) \
++	((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
++#define smu_check_pptable(smu) \
++	((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
++#define smu_parse_pptable(smu) \
++	((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
++#define smu_populate_smc_tables(smu) \
++	((smu)->funcs->populate_smc_tables ? (smu)->funcs->populate_smc_tables((smu)) : 0)
++#define smu_check_fw_version(smu) \
++	((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
++#define smu_write_pptable(smu) \
++	((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
++#define smu_set_min_dcef_deep_sleep(smu) \
++	((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
++#define smu_set_tool_table_location(smu) \
++	((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
++#define smu_notify_memory_pool_location(smu) \
++	((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
++#define smu_gfx_off_control(smu, enable) \
++	((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
++
++#define smu_set_last_dcef_min_deep_sleep_clk(smu) \
++	((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
++#define smu_system_features_control(smu, en) \
++	((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
++#define smu_init_max_sustainable_clocks(smu) \
++	((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
++#define smu_set_default_od_settings(smu, initialize) \
++	((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
++
++#define smu_send_smc_msg(smu, msg) \
++	((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
++#define smu_send_smc_msg_with_param(smu, msg, param) \
++	((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
++#define smu_read_smc_arg(smu, arg) \
++	((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
++#define smu_alloc_dpm_context(smu) \
++	((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
++#define smu_init_display_count(smu, count) \
++	((smu)->funcs->init_display_count ? (smu)->funcs->init_display_count((smu), (count)) : 0)
++#define smu_feature_set_allowed_mask(smu) \
++	((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
++#define smu_feature_get_enabled_mask(smu, mask, num) \
++	((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
++#define smu_is_dpm_running(smu) \
++	((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
++#define smu_notify_display_change(smu) \
++	((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
++#define smu_store_powerplay_table(smu) \
++	((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
++#define smu_check_powerplay_table(smu) \
++	((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
++#define smu_append_powerplay_table(smu) \
++	((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
++#define smu_set_default_dpm_table(smu) \
++	((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
++#define smu_populate_umd_state_clk(smu) \
++	((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
++#define smu_set_default_od8_settings(smu) \
++	((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
++
++#define smu_get_current_clk_freq(smu, clk_id, value) \
++	((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
++
++#define smu_tables_init(smu, tab) \
++	((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
++#define smu_set_thermal_fan_table(smu) \
++	((smu)->ppt_funcs->set_thermal_fan_table ? (smu)->ppt_funcs->set_thermal_fan_table((smu)) : 0)
++#define smu_start_thermal_control(smu) \
++	((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
++#define smu_stop_thermal_control(smu) \
++	((smu)->funcs->stop_thermal_control? (smu)->funcs->stop_thermal_control((smu)) : 0)
++
++#define smu_smc_read_sensor(smu, sensor, data, size) \
++	((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
++
++#define smu_pre_display_config_changed(smu) \
++	((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
++#define smu_display_config_changed(smu) \
++	((smu)->ppt_funcs->display_config_changed ? (smu)->ppt_funcs->display_config_changed((smu)) : 0)
++#define smu_apply_clocks_adjust_rules(smu) \
++	((smu)->ppt_funcs->apply_clocks_adjust_rules ? (smu)->ppt_funcs->apply_clocks_adjust_rules((smu)) : 0)
++#define smu_notify_smc_dispaly_config(smu) \
++	((smu)->ppt_funcs->notify_smc_dispaly_config ? (smu)->ppt_funcs->notify_smc_dispaly_config((smu)) : 0)
++#define smu_force_dpm_limit_value(smu, highest) \
++	((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
++#define smu_unforce_dpm_levels(smu) \
++	((smu)->ppt_funcs->unforce_dpm_levels ? (smu)->ppt_funcs->unforce_dpm_levels((smu)) : 0)
++#define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
++	((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
++#define smu_set_cpu_power_state(smu) \
++	((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
++
++#define smu_msg_get_index(smu, msg) \
++	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
++#define smu_clk_get_index(smu, msg) \
++	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_clk_index? (smu)->ppt_funcs->get_smu_clk_index((smu), (msg)) : -EINVAL) : -EINVAL)
++#define smu_feature_get_index(smu, msg) \
++	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_feature_index? (smu)->ppt_funcs->get_smu_feature_index((smu), (msg)) : -EINVAL) : -EINVAL)
++#define smu_table_get_index(smu, tab) \
++	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_table_index? (smu)->ppt_funcs->get_smu_table_index((smu), (tab)) : -EINVAL) : -EINVAL)
++#define smu_power_get_index(smu, src) \
++	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_power_index? (smu)->ppt_funcs->get_smu_power_index((smu), (src)) : -EINVAL) : -EINVAL)
++#define smu_workload_get_type(smu, profile) \
++	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_workload_type? (smu)->ppt_funcs->get_workload_type((smu), (profile)) : -EINVAL) : -EINVAL)
++#define smu_run_btc(smu) \
++	((smu)->ppt_funcs? ((smu)->ppt_funcs->run_btc? (smu)->ppt_funcs->run_btc((smu)) : 0) : 0)
++#define smu_get_allowed_feature_mask(smu, feature_mask, num) \
++	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
++
++
++#define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
++	((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
++
++#define smu_get_dal_power_level(smu, clocks) \
++	((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
++#define smu_get_perf_level(smu, designation, level) \
++	((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
++#define smu_get_current_shallow_sleep_clocks(smu, clocks) \
++	((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
++
++#define smu_dpm_set_uvd_enable(smu, enable) \
++	((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
++#define smu_dpm_set_vce_enable(smu, enable) \
++	((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
++
++#define smu_set_watermarks_table(smu, tab, clock_ranges) \
++	((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
++#define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
++	((smu)->ppt_funcs->get_current_clk_freq_by_table ? (smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0)
++#define smu_thermal_temperature_range_update(smu, range, rw) \
++	((smu)->ppt_funcs->thermal_temperature_range_update? (smu)->ppt_funcs->thermal_temperature_range_update((smu), (range), (rw)) : 0)
++#define smu_get_thermal_temperature_range(smu, range) \
++	((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
++#define smu_register_irq_handler(smu) \
++	((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
++
++#define smu_get_dpm_ultimate_freq(smu, param, min, max) \
++		((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
++
++#define smu_asic_set_performance_level(smu, level) \
++	((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
++#define smu_dump_pptable(smu) \
++	((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0)
++#define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) \
++		((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EINVAL)
++
++#define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
++		((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
++
++#define smu_override_pcie_parameters(smu) \
++		((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0)
++
++#define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) \
++		((smu)->ppt_funcs->update_pcie_parameters ? (smu)->ppt_funcs->update_pcie_parameters((smu), (pcie_gen_cap), (pcie_width_cap)) : 0)
++
++#endif
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 54f9d3dd837f..6794fc4cacb5 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -24,6 +24,7 @@
+ #include <linux/firmware.h>
+ #include "amdgpu.h"
+ #include "amdgpu_smu.h"
++#include "smu_internal.h"
+ #include "atomfirmware.h"
+ #include "amdgpu_atomfirmware.h"
+ #include "smu_v11_0.h"
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 6b9eef20554b..92e1c0a3f428 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -24,6 +24,7 @@
+ #include <linux/firmware.h>
+ #include "amdgpu.h"
+ #include "amdgpu_smu.h"
++#include "smu_internal.h"
+ #include "atomfirmware.h"
+ #include "amdgpu_atomfirmware.h"
+ #include "smu_v12_0.h"
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index c249df9256c7..4039efcdcb1f 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -25,6 +25,7 @@
+ #include <linux/firmware.h>
+ #include "amdgpu.h"
+ #include "amdgpu_smu.h"
++#include "smu_internal.h"
+ #include "atomfirmware.h"
+ #include "amdgpu_atomfirmware.h"
+ #include "smu_v11_0.h"
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4268-drm-amd-powerplay-clear-the-swSMU-code-layer.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4268-drm-amd-powerplay-clear-the-swSMU-code-layer.patch
new file mode 100644
index 00000000..d4a448be
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4268-drm-amd-powerplay-clear-the-swSMU-code-layer.patch
@@ -0,0 +1,1907 @@
+From f8ce766413a519f8c78170815c26fa4e7bf5fbdd Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 17 Oct 2019 19:59:29 +0800
+Subject: [PATCH 4268/4736] drm/amd/powerplay: clear the swSMU code layer
+
+With this cleanup, the APIs from amdgpu_smu.c will map to
+ASIC specific ones directly. Those can be shared around
+all SMU V11/V12 ASICs will be put in smu_v11_0.c and
+smu_v12_0.c respectively.
+
+Change-Id: I9b98eb5ace5df19896de4b05c37255a38d1079ce
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c  |  42 ++--
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 115 +++++------
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  |  51 ++++-
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |   9 +-
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 120 +++++++++++-
+ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h |  41 +++-
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    |  54 +++++-
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c    |  15 ++
+ drivers/gpu/drm/amd/powerplay/smu_internal.h  |  82 ++++----
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 183 +++++-------------
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c     |  70 ++-----
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c    |  55 +++++-
+ 12 files changed, 519 insertions(+), 318 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+index c1b6abf2634c..e42b162ee5d3 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+@@ -346,7 +346,7 @@ bool dm_pp_get_clock_levels_by_type(
+ 		/* Error in pplib. Provide default values. */
+ 			return true;
+ 		}
+-	} else if (adev->smu.funcs && adev->smu.funcs->get_clock_by_type) {
++	} else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type) {
+ 		if (smu_get_clock_by_type(&adev->smu,
+ 					  dc_to_pp_clock_type(clk_type),
+ 					  &pp_clks)) {
+@@ -366,7 +366,7 @@ bool dm_pp_get_clock_levels_by_type(
+ 			validation_clks.memory_max_clock = 80000;
+ 			validation_clks.level = 0;
+ 		}
+-	} else if (adev->smu.funcs && adev->smu.funcs->get_max_high_clocks) {
++	} else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_max_high_clocks) {
+ 		if (smu_get_max_high_clocks(&adev->smu, &validation_clks)) {
+ 			DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
+ 			validation_clks.engine_max_clock = 72000;
+@@ -507,8 +507,8 @@ bool dm_pp_apply_clock_for_voltage_request(
+ 		ret = adev->powerplay.pp_funcs->display_clock_voltage_request(
+ 			adev->powerplay.pp_handle,
+ 			&pp_clock_request);
+-	else if (adev->smu.funcs &&
+-		 adev->smu.funcs->display_clock_voltage_request)
++	else if (adev->smu.ppt_funcs &&
++		 adev->smu.ppt_funcs->display_clock_voltage_request)
+ 		ret = smu_display_clock_voltage_request(&adev->smu,
+ 							&pp_clock_request);
+ 	if (ret)
+@@ -528,7 +528,7 @@ bool dm_pp_get_static_clocks(
+ 		ret = adev->powerplay.pp_funcs->get_current_clocks(
+ 			adev->powerplay.pp_handle,
+ 			&pp_clk_info);
+-	else if (adev->smu.funcs)
++	else if (adev->smu.ppt_funcs)
+ 		ret = smu_get_current_clocks(&adev->smu, &pp_clk_info);
+ 	if (ret)
+ 		return false;
+@@ -604,7 +604,7 @@ void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
+ 
+ 	if (pp_funcs && pp_funcs->notify_smu_enable_pwe)
+ 		pp_funcs->notify_smu_enable_pwe(pp_handle);
+-	else if (adev->smu.funcs)
++	else if (adev->smu.ppt_funcs)
+ 		smu_notify_smu_enable_pwe(&adev->smu);
+ }
+ 
+@@ -718,10 +718,10 @@ enum pp_smu_status pp_nv_set_pme_wa_enable(struct pp_smu *pp)
+ 	struct amdgpu_device *adev = ctx->driver_context;
+ 	struct smu_context *smu = &adev->smu;
+ 
+-	if (!smu->funcs)
++	if (!smu->ppt_funcs)
+ 		return PP_SMU_RESULT_UNSUPPORTED;
+ 
+-	/* 0: successful or smu.funcs->set_azalia_d3_pme = NULL;  1: fail */
++	/* 0: successful or smu.ppt_funcs->set_azalia_d3_pme = NULL;  1: fail */
+ 	if (smu_set_azalia_d3_pme(smu))
+ 		return PP_SMU_RESULT_FAIL;
+ 
+@@ -734,10 +734,10 @@ enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count)
+ 	struct amdgpu_device *adev = ctx->driver_context;
+ 	struct smu_context *smu = &adev->smu;
+ 
+-	if (!smu->funcs)
++	if (!smu->ppt_funcs)
+ 		return PP_SMU_RESULT_UNSUPPORTED;
+ 
+-	/* 0: successful or smu.funcs->set_display_count = NULL;  1: fail */
++	/* 0: successful or smu.ppt_funcs->set_display_count = NULL;  1: fail */
+ 	if (smu_set_display_count(smu, count))
+ 		return PP_SMU_RESULT_FAIL;
+ 
+@@ -750,10 +750,10 @@ enum pp_smu_status pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz)
+ 	struct amdgpu_device *adev = ctx->driver_context;
+ 	struct smu_context *smu = &adev->smu;
+ 
+-	if (!smu->funcs)
++	if (!smu->ppt_funcs)
+ 		return PP_SMU_RESULT_UNSUPPORTED;
+ 
+-	/* 0: successful or smu.funcs->set_deep_sleep_dcefclk = NULL;1: fail */
++	/* 0: successful or smu.ppt_funcs->set_deep_sleep_dcefclk = NULL;1: fail */
+ 	if (smu_set_deep_sleep_dcefclk(smu, mhz))
+ 		return PP_SMU_RESULT_FAIL;
+ 
+@@ -768,13 +768,13 @@ enum pp_smu_status pp_nv_set_hard_min_dcefclk_by_freq(
+ 	struct smu_context *smu = &adev->smu;
+ 	struct pp_display_clock_request clock_req;
+ 
+-	if (!smu->funcs)
++	if (!smu->ppt_funcs)
+ 		return PP_SMU_RESULT_UNSUPPORTED;
+ 
+ 	clock_req.clock_type = amd_pp_dcef_clock;
+ 	clock_req.clock_freq_in_khz = mhz * 1000;
+ 
+-	/* 0: successful or smu.funcs->display_clock_voltage_request = NULL
++	/* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
+ 	 * 1: fail
+ 	 */
+ 	if (smu_display_clock_voltage_request(smu, &clock_req))
+@@ -790,13 +790,13 @@ enum pp_smu_status pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz)
+ 	struct smu_context *smu = &adev->smu;
+ 	struct pp_display_clock_request clock_req;
+ 
+-	if (!smu->funcs)
++	if (!smu->ppt_funcs)
+ 		return PP_SMU_RESULT_UNSUPPORTED;
+ 
+ 	clock_req.clock_type = amd_pp_mem_clock;
+ 	clock_req.clock_freq_in_khz = mhz * 1000;
+ 
+-	/* 0: successful or smu.funcs->display_clock_voltage_request = NULL
++	/* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
+ 	 * 1: fail
+ 	 */
+ 	if (smu_display_clock_voltage_request(smu, &clock_req))
+@@ -826,7 +826,7 @@ enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
+ 	struct smu_context *smu = &adev->smu;
+ 	struct pp_display_clock_request clock_req;
+ 
+-	if (!smu->funcs)
++	if (!smu->ppt_funcs)
+ 		return PP_SMU_RESULT_UNSUPPORTED;
+ 
+ 	switch (clock_id) {
+@@ -844,7 +844,7 @@ enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
+ 	}
+ 	clock_req.clock_freq_in_khz = mhz * 1000;
+ 
+-	/* 0: successful or smu.funcs->display_clock_voltage_request = NULL
++	/* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
+ 	 * 1: fail
+ 	 */
+ 	if (smu_display_clock_voltage_request(smu, &clock_req))
+@@ -860,10 +860,10 @@ enum pp_smu_status pp_nv_get_maximum_sustainable_clocks(
+ 	struct amdgpu_device *adev = ctx->driver_context;
+ 	struct smu_context *smu = &adev->smu;
+ 
+-	if (!smu->funcs)
++	if (!smu->ppt_funcs)
+ 		return PP_SMU_RESULT_UNSUPPORTED;
+ 
+-	if (!smu->funcs->get_max_sustainable_clocks_by_dc)
++	if (!smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
+ 		return PP_SMU_RESULT_UNSUPPORTED;
+ 
+ 	if (!smu_get_max_sustainable_clocks_by_dc(smu, max_clocks))
+@@ -925,7 +925,7 @@ enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp,
+ 			wm_with_clock_ranges.wm_mcif_clocks_ranges;
+ 	int32_t i;
+ 
+-	if (!smu->funcs)
++	if (!smu->ppt_funcs)
+ 		return PP_SMU_RESULT_UNSUPPORTED;
+ 
+ 	wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 75c4e297b788..3ce01e1994fc 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -31,6 +31,10 @@
+ #include "smu_v12_0.h"
+ #include "atom.h"
+ #include "amd_pcie.h"
++#include "vega20_ppt.h"
++#include "arcturus_ppt.h"
++#include "navi10_ppt.h"
++#include "renoir_ppt.h"
+ 
+ #undef __SMU_DUMMY_MAP
+ #define __SMU_DUMMY_MAP(type)	#type
+@@ -703,23 +707,26 @@ static int smu_set_funcs(struct amdgpu_device *adev)
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_VEGA20:
++		vega20_set_ppt_funcs(smu);
++		break;
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+ 	case CHIP_NAVI12:
++		navi10_set_ppt_funcs(smu);
++		break;
+ 	case CHIP_ARCTURUS:
+-		if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
+-			smu->od_enabled = true;
+-		smu_v11_0_set_smu_funcs(smu);
++		arcturus_set_ppt_funcs(smu);
+ 		break;
+ 	case CHIP_RENOIR:
+-		if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
+-			smu->od_enabled = true;
+-		smu_v12_0_set_smu_funcs(smu);
++		renoir_set_ppt_funcs(smu);
+ 		break;
+ 	default:
+ 		return -EINVAL;
+ 	}
+ 
++	if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
++		smu->od_enabled = true;
++
+ 	return 0;
+ }
+ 
+@@ -1177,16 +1184,16 @@ static int smu_start_smc_engine(struct smu_context *smu)
+ 
+ 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+ 		if (adev->asic_type < CHIP_NAVI10) {
+-			if (smu->funcs->load_microcode) {
+-				ret = smu->funcs->load_microcode(smu);
++			if (smu->ppt_funcs->load_microcode) {
++				ret = smu->ppt_funcs->load_microcode(smu);
+ 				if (ret)
+ 					return ret;
+ 			}
+ 		}
+ 	}
+ 
+-	if (smu->funcs->check_fw_status) {
+-		ret = smu->funcs->check_fw_status(smu);
++	if (smu->ppt_funcs->check_fw_status) {
++		ret = smu->ppt_funcs->check_fw_status(smu);
+ 		if (ret)
+ 			pr_err("SMC is not ready\n");
+ 	}
+@@ -1397,8 +1404,8 @@ int smu_display_configuration_change(struct smu_context *smu,
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->set_deep_sleep_dcefclk)
+-		smu->funcs->set_deep_sleep_dcefclk(smu,
++	if (smu->ppt_funcs->set_deep_sleep_dcefclk)
++		smu->ppt_funcs->set_deep_sleep_dcefclk(smu,
+ 				display_config->min_dcef_deep_sleep_set_clk / 100);
+ 
+ 	for (index = 0; index < display_config->num_path_including_non_display; index++) {
+@@ -1952,8 +1959,8 @@ int smu_load_microcode(struct smu_context *smu)
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->load_microcode)
+-		ret = smu->funcs->load_microcode(smu);
++	if (smu->ppt_funcs->load_microcode)
++		ret = smu->ppt_funcs->load_microcode(smu);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -1966,8 +1973,8 @@ int smu_check_fw_status(struct smu_context *smu)
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->check_fw_status)
+-		ret = smu->funcs->check_fw_status(smu);
++	if (smu->ppt_funcs->check_fw_status)
++		ret = smu->ppt_funcs->check_fw_status(smu);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -1980,8 +1987,8 @@ int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->set_gfx_cgpg)
+-		ret = smu->funcs->set_gfx_cgpg(smu, enabled);
++	if (smu->ppt_funcs->set_gfx_cgpg)
++		ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -1994,8 +2001,8 @@ int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->set_fan_speed_rpm)
+-		ret = smu->funcs->set_fan_speed_rpm(smu, speed);
++	if (smu->ppt_funcs->set_fan_speed_rpm)
++		ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -2027,8 +2034,8 @@ int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->set_power_limit)
+-		ret = smu->funcs->set_power_limit(smu, limit);
++	if (smu->ppt_funcs->set_power_limit)
++		ret = smu->ppt_funcs->set_power_limit(smu, limit);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -2149,8 +2156,8 @@ int smu_get_fan_control_mode(struct smu_context *smu)
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->get_fan_control_mode)
+-		ret = smu->funcs->get_fan_control_mode(smu);
++	if (smu->ppt_funcs->get_fan_control_mode)
++		ret = smu->ppt_funcs->get_fan_control_mode(smu);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -2163,8 +2170,8 @@ int smu_set_fan_control_mode(struct smu_context *smu, int value)
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->set_fan_control_mode)
+-		ret = smu->funcs->set_fan_control_mode(smu, value);
++	if (smu->ppt_funcs->set_fan_control_mode)
++		ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -2191,8 +2198,8 @@ int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->set_fan_speed_percent)
+-		ret = smu->funcs->set_fan_speed_percent(smu, speed);
++	if (smu->ppt_funcs->set_fan_speed_percent)
++		ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -2219,8 +2226,8 @@ int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->set_deep_sleep_dcefclk)
+-		ret = smu->funcs->set_deep_sleep_dcefclk(smu, clk);
++	if (smu->ppt_funcs->set_deep_sleep_dcefclk)
++		ret = smu->ppt_funcs->set_deep_sleep_dcefclk(smu, clk);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -2233,8 +2240,8 @@ int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->set_active_display_count)
+-		ret = smu->funcs->set_active_display_count(smu, count);
++	if (smu->ppt_funcs->set_active_display_count)
++		ret = smu->ppt_funcs->set_active_display_count(smu, count);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -2249,8 +2256,8 @@ int smu_get_clock_by_type(struct smu_context *smu,
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->get_clock_by_type)
+-		ret = smu->funcs->get_clock_by_type(smu, type, clocks);
++	if (smu->ppt_funcs->get_clock_by_type)
++		ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -2264,8 +2271,8 @@ int smu_get_max_high_clocks(struct smu_context *smu,
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->get_max_high_clocks)
+-		ret = smu->funcs->get_max_high_clocks(smu, clocks);
++	if (smu->ppt_funcs->get_max_high_clocks)
++		ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -2312,8 +2319,8 @@ int smu_display_clock_voltage_request(struct smu_context *smu,
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->display_clock_voltage_request)
+-		ret = smu->funcs->display_clock_voltage_request(smu, clock_req);
++	if (smu->ppt_funcs->display_clock_voltage_request)
++		ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -2341,8 +2348,8 @@ int smu_notify_smu_enable_pwe(struct smu_context *smu)
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->notify_smu_enable_pwe)
+-		ret = smu->funcs->notify_smu_enable_pwe(smu);
++	if (smu->ppt_funcs->notify_smu_enable_pwe)
++		ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -2356,8 +2363,8 @@ int smu_set_xgmi_pstate(struct smu_context *smu,
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->set_xgmi_pstate)
+-		ret = smu->funcs->set_xgmi_pstate(smu, pstate);
++	if (smu->ppt_funcs->set_xgmi_pstate)
++		ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -2370,8 +2377,8 @@ int smu_set_azalia_d3_pme(struct smu_context *smu)
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->set_azalia_d3_pme)
+-		ret = smu->funcs->set_azalia_d3_pme(smu);
++	if (smu->ppt_funcs->set_azalia_d3_pme)
++		ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -2384,8 +2391,8 @@ bool smu_baco_is_support(struct smu_context *smu)
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->baco_is_support)
+-		ret = smu->funcs->baco_is_support(smu);
++	if (smu->ppt_funcs->baco_is_support)
++		ret = smu->ppt_funcs->baco_is_support(smu);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -2394,11 +2401,11 @@ bool smu_baco_is_support(struct smu_context *smu)
+ 
+ int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
+ {
+-	if (smu->funcs->baco_get_state)
++	if (smu->ppt_funcs->baco_get_state)
+ 		return -EINVAL;
+ 
+ 	mutex_lock(&smu->mutex);
+-	*state = smu->funcs->baco_get_state(smu);
++	*state = smu->ppt_funcs->baco_get_state(smu);
+ 	mutex_unlock(&smu->mutex);
+ 
+ 	return 0;
+@@ -2410,8 +2417,8 @@ int smu_baco_reset(struct smu_context *smu)
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->baco_reset)
+-		ret = smu->funcs->baco_reset(smu);
++	if (smu->ppt_funcs->baco_reset)
++		ret = smu->ppt_funcs->baco_reset(smu);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -2424,8 +2431,8 @@ int smu_mode2_reset(struct smu_context *smu)
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->mode2_reset)
+-		ret = smu->funcs->mode2_reset(smu);
++	if (smu->ppt_funcs->mode2_reset)
++		ret = smu->ppt_funcs->mode2_reset(smu);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+@@ -2439,8 +2446,8 @@ int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->funcs->get_max_sustainable_clocks_by_dc)
+-		ret = smu->funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
++	if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
++		ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index a2262464d141..ffefa89c295b 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -1048,7 +1048,7 @@ static int arcturus_read_sensor(struct smu_context *smu,
+ 		*size = 4;
+ 		break;
+ 	default:
+-		ret = smu_smc_read_sensor(smu, sensor, data, size);
++		ret = smu_v11_0_read_sensor(smu, sensor, data, size);
+ 	}
+ 	mutex_unlock(&smu->sensor_lock);
+ 
+@@ -1964,6 +1964,55 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 	.get_power_limit = arcturus_get_power_limit,
+ 	.is_dpm_running = arcturus_is_dpm_running,
+ 	.dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
++	.init_microcode = smu_v11_0_init_microcode,
++	.load_microcode = smu_v11_0_load_microcode,
++	.init_smc_tables = smu_v11_0_init_smc_tables,
++	.fini_smc_tables = smu_v11_0_fini_smc_tables,
++	.init_power = smu_v11_0_init_power,
++	.fini_power = smu_v11_0_fini_power,
++	.check_fw_status = smu_v11_0_check_fw_status,
++	.setup_pptable = smu_v11_0_setup_pptable,
++	.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
++	.get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
++	.check_pptable = smu_v11_0_check_pptable,
++	.parse_pptable = smu_v11_0_parse_pptable,
++	.populate_smc_tables = smu_v11_0_populate_smc_pptable,
++	.check_fw_version = smu_v11_0_check_fw_version,
++	.write_pptable = smu_v11_0_write_pptable,
++	.set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
++	.set_tool_table_location = smu_v11_0_set_tool_table_location,
++	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
++	.system_features_control = smu_v11_0_system_features_control,
++	.send_smc_msg = smu_v11_0_send_msg,
++	.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
++	.read_smc_arg = smu_v11_0_read_arg,
++	.init_display_count = smu_v11_0_init_display_count,
++	.set_allowed_mask = smu_v11_0_set_allowed_mask,
++	.get_enabled_mask = smu_v11_0_get_enabled_mask,
++	.notify_display_change = smu_v11_0_notify_display_change,
++	.set_power_limit = smu_v11_0_set_power_limit,
++	.get_current_clk_freq = smu_v11_0_get_current_clk_freq,
++	.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
++	.start_thermal_control = smu_v11_0_start_thermal_control,
++	.stop_thermal_control = smu_v11_0_stop_thermal_control,
++	.set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
++	.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
++	.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
++	.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
++	.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
++	.set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
++	.set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
++	.gfx_off_control = smu_v11_0_gfx_off_control,
++	.register_irq_handler = smu_v11_0_register_irq_handler,
++	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
++	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
++	.baco_is_support= smu_v11_0_baco_is_support,
++	.baco_get_state = smu_v11_0_baco_get_state,
++	.baco_set_state = smu_v11_0_baco_set_state,
++	.baco_reset = smu_v11_0_baco_reset,
++	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
++	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
++	.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+ };
+ 
+ void arcturus_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 79fe32acc838..402a021f237b 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -347,7 +347,6 @@ struct smu_context
+ 	struct amdgpu_device            *adev;
+ 	struct amdgpu_irq_src		*irq_source;
+ 
+-	const struct smu_funcs		*funcs;
+ 	const struct pptable_funcs	*ppt_funcs;
+ 	struct mutex			mutex;
+ 	struct mutex			sensor_lock;
+@@ -471,16 +470,12 @@ struct pptable_funcs {
+ 	int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
+ 	int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
+ 	int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
+-};
+-
+-struct smu_funcs
+-{
+ 	int (*init_microcode)(struct smu_context *smu);
++	int (*load_microcode)(struct smu_context *smu);
+ 	int (*init_smc_tables)(struct smu_context *smu);
+ 	int (*fini_smc_tables)(struct smu_context *smu);
+ 	int (*init_power)(struct smu_context *smu);
+ 	int (*fini_power)(struct smu_context *smu);
+-	int (*load_microcode)(struct smu_context *smu);
+ 	int (*check_fw_status)(struct smu_context *smu);
+ 	int (*setup_pptable)(struct smu_context *smu);
+ 	int (*get_vbios_bootup_values)(struct smu_context *smu);
+@@ -510,8 +505,6 @@ struct smu_funcs
+ 	int (*init_max_sustainable_clocks)(struct smu_context *smu);
+ 	int (*start_thermal_control)(struct smu_context *smu);
+ 	int (*stop_thermal_control)(struct smu_context *smu);
+-	int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
+-			   void *data, uint32_t *size);
+ 	int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);
+ 	int (*set_active_display_count)(struct smu_context *smu, uint32_t count);
+ 	int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 6b2a901492b2..88ee66683271 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -131,6 +131,124 @@ enum smu_v11_0_baco_seq {
+ 	BACO_SEQ_COUNT,
+ };
+ 
+-void smu_v11_0_set_smu_funcs(struct smu_context *smu);
++int smu_v11_0_init_microcode(struct smu_context *smu);
++
++int smu_v11_0_load_microcode(struct smu_context *smu);
++
++int smu_v11_0_init_smc_tables(struct smu_context *smu);
++
++int smu_v11_0_fini_smc_tables(struct smu_context *smu);
++
++int smu_v11_0_init_power(struct smu_context *smu);
++
++int smu_v11_0_fini_power(struct smu_context *smu);
++
++int smu_v11_0_check_fw_status(struct smu_context *smu);
++
++int smu_v11_0_setup_pptable(struct smu_context *smu);
++
++int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu);
++
++int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu);
++
++int smu_v11_0_check_pptable(struct smu_context *smu);
++
++int smu_v11_0_parse_pptable(struct smu_context *smu);
++
++int smu_v11_0_populate_smc_pptable(struct smu_context *smu);
++
++int smu_v11_0_check_fw_version(struct smu_context *smu);
++
++int smu_v11_0_write_pptable(struct smu_context *smu);
++
++int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu);
++
++int smu_v11_0_set_tool_table_location(struct smu_context *smu);
++
++int smu_v11_0_notify_memory_pool_location(struct smu_context *smu);
++
++int smu_v11_0_system_features_control(struct smu_context *smu,
++					     bool en);
++
++int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg);
++
++int
++smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
++			      uint32_t param);
++
++int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg);
++
++int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count);
++
++int smu_v11_0_set_allowed_mask(struct smu_context *smu);
++
++int smu_v11_0_get_enabled_mask(struct smu_context *smu,
++				      uint32_t *feature_mask, uint32_t num);
++
++int smu_v11_0_notify_display_change(struct smu_context *smu);
++
++int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n);
++
++int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
++					  enum smu_clk_type clk_id,
++					  uint32_t *value);
++
++int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu);
++
++int smu_v11_0_start_thermal_control(struct smu_context *smu);
++
++int smu_v11_0_stop_thermal_control(struct smu_context *smu);
++
++int smu_v11_0_read_sensor(struct smu_context *smu,
++				 enum amd_pp_sensors sensor,
++				 void *data, uint32_t *size);
++
++int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
++
++int
++smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
++					struct pp_display_clock_request
++					*clock_req);
++
++uint32_t
++smu_v11_0_get_fan_control_mode(struct smu_context *smu);
++
++int
++smu_v11_0_set_fan_control_mode(struct smu_context *smu,
++			       uint32_t mode);
++
++int
++smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed);
++
++int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
++				       uint32_t speed);
++
++int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
++				     uint32_t pstate);
++
++int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable);
++
++int smu_v11_0_register_irq_handler(struct smu_context *smu);
++
++int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu);
++
++int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
++		struct pp_smu_nv_clock_table *max_clocks);
++
++bool smu_v11_0_baco_is_support(struct smu_context *smu);
++
++enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu);
++
++int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
++
++int smu_v11_0_baco_reset(struct smu_context *smu);
++
++int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
++						 uint32_t *min, uint32_t *max);
++
++int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
++			    uint32_t min, uint32_t max);
++
++int smu_v11_0_override_pcie_parameters(struct smu_context *smu);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+index acf3db12f59f..9b9f5df0911c 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+@@ -37,6 +37,45 @@ struct smu_12_0_cmn2aisc_mapping {
+ 	int	map_to;
+ };
+ 
+-void smu_v12_0_set_smu_funcs(struct smu_context *smu);
++int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
++					      uint16_t msg);
++
++int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg);
++
++int smu_v12_0_wait_for_response(struct smu_context *smu);
++
++int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg);
++
++int
++smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
++			      uint32_t param);
++
++int smu_v12_0_check_fw_status(struct smu_context *smu);
++
++int smu_v12_0_check_fw_version(struct smu_context *smu);
++
++int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate);
++
++int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate);
++
++int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
++
++uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu);
++
++int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable);
++
++int smu_v12_0_init_smc_tables(struct smu_context *smu);
++
++int smu_v12_0_fini_smc_tables(struct smu_context *smu);
++
++int smu_v12_0_populate_smc_tables(struct smu_context *smu);
++
++int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
++						 uint32_t *min, uint32_t *max);
++
++int smu_v12_0_mode2_reset(struct smu_context *smu);
++
++int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
++			    uint32_t min, uint32_t max);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 54d5c91dda23..34390656a03e 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1268,8 +1268,7 @@ static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
+ 		clock_req.clock_type = amd_pp_dcef_clock;
+ 		clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
+ 
+-		if (smu->funcs->display_clock_voltage_request)
+-			ret = smu->funcs->display_clock_voltage_request(smu, &clock_req);
++		ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
+ 		if (!ret) {
+ 			if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
+ 				ret = smu_send_smc_msg_with_param(smu,
+@@ -1424,7 +1423,7 @@ static int navi10_read_sensor(struct smu_context *smu,
+ 		*size = 4;
+ 		break;
+ 	default:
+-		ret = smu_smc_read_sensor(smu, sensor, data, size);
++		ret = smu_v11_0_read_sensor(smu, sensor, data, size);
+ 	}
+ 	mutex_unlock(&smu->sensor_lock);
+ 
+@@ -1693,6 +1692,55 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
+ 	.get_power_limit = navi10_get_power_limit,
+ 	.update_pcie_parameters = navi10_update_pcie_parameters,
++	.init_microcode = smu_v11_0_init_microcode,
++	.load_microcode = smu_v11_0_load_microcode,
++	.init_smc_tables = smu_v11_0_init_smc_tables,
++	.fini_smc_tables = smu_v11_0_fini_smc_tables,
++	.init_power = smu_v11_0_init_power,
++	.fini_power = smu_v11_0_fini_power,
++	.check_fw_status = smu_v11_0_check_fw_status,
++	.setup_pptable = smu_v11_0_setup_pptable,
++	.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
++	.get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
++	.check_pptable = smu_v11_0_check_pptable,
++	.parse_pptable = smu_v11_0_parse_pptable,
++	.populate_smc_tables = smu_v11_0_populate_smc_pptable,
++	.check_fw_version = smu_v11_0_check_fw_version,
++	.write_pptable = smu_v11_0_write_pptable,
++	.set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
++	.set_tool_table_location = smu_v11_0_set_tool_table_location,
++	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
++	.system_features_control = smu_v11_0_system_features_control,
++	.send_smc_msg = smu_v11_0_send_msg,
++	.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
++	.read_smc_arg = smu_v11_0_read_arg,
++	.init_display_count = smu_v11_0_init_display_count,
++	.set_allowed_mask = smu_v11_0_set_allowed_mask,
++	.get_enabled_mask = smu_v11_0_get_enabled_mask,
++	.notify_display_change = smu_v11_0_notify_display_change,
++	.set_power_limit = smu_v11_0_set_power_limit,
++	.get_current_clk_freq = smu_v11_0_get_current_clk_freq,
++	.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
++	.start_thermal_control = smu_v11_0_start_thermal_control,
++	.stop_thermal_control = smu_v11_0_stop_thermal_control,
++	.set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
++	.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
++	.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
++	.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
++	.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
++	.set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
++	.set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
++	.gfx_off_control = smu_v11_0_gfx_off_control,
++	.register_irq_handler = smu_v11_0_register_irq_handler,
++	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
++	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
++	.baco_is_support= smu_v11_0_baco_is_support,
++	.baco_get_state = smu_v11_0_baco_get_state,
++	.baco_set_state = smu_v11_0_baco_set_state,
++	.baco_reset = smu_v11_0_baco_reset,
++	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
++	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
++	.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+ };
+ 
+ void navi10_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 6df91b1a9daa..45c5f54e60d8 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -691,6 +691,21 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_dpm_clock_table = renoir_get_dpm_clock_table,
+ 	.set_watermarks_table = renoir_set_watermarks_table,
+ 	.get_power_profile_mode = renoir_get_power_profile_mode,
++	.check_fw_status = smu_v12_0_check_fw_status,
++	.check_fw_version = smu_v12_0_check_fw_version,
++	.powergate_sdma = smu_v12_0_powergate_sdma,
++	.powergate_vcn = smu_v12_0_powergate_vcn,
++	.send_smc_msg = smu_v12_0_send_msg,
++	.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
++	.read_smc_arg = smu_v12_0_read_arg,
++	.set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
++	.gfx_off_control = smu_v12_0_gfx_off_control,
++	.init_smc_tables = smu_v12_0_init_smc_tables,
++	.fini_smc_tables = smu_v12_0_fini_smc_tables,
++	.populate_smc_tables = smu_v12_0_populate_smc_tables,
++	.get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
++	.mode2_reset = smu_v12_0_mode2_reset,
++	.set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
+ };
+ 
+ void renoir_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+index c26eede7e36a..8bcda7871309 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
++++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+@@ -26,73 +26,73 @@
+ #include "amdgpu_smu.h"
+ 
+ #define smu_init_microcode(smu) \
+-	((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
++	((smu)->ppt_funcs->init_microcode ? (smu)->ppt_funcs->init_microcode((smu)) : 0)
+ #define smu_init_smc_tables(smu) \
+-	((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
++	((smu)->ppt_funcs->init_smc_tables ? (smu)->ppt_funcs->init_smc_tables((smu)) : 0)
+ #define smu_fini_smc_tables(smu) \
+-	((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
++	((smu)->ppt_funcs->fini_smc_tables ? (smu)->ppt_funcs->fini_smc_tables((smu)) : 0)
+ #define smu_init_power(smu) \
+-	((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
++	((smu)->ppt_funcs->init_power ? (smu)->ppt_funcs->init_power((smu)) : 0)
+ #define smu_fini_power(smu) \
+-	((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
++	((smu)->ppt_funcs->fini_power ? (smu)->ppt_funcs->fini_power((smu)) : 0)
+ 
+ #define smu_setup_pptable(smu) \
+-	((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
++	((smu)->ppt_funcs->setup_pptable ? (smu)->ppt_funcs->setup_pptable((smu)) : 0)
+ #define smu_powergate_sdma(smu, gate) \
+-	((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
++	((smu)->ppt_funcs->powergate_sdma ? (smu)->ppt_funcs->powergate_sdma((smu), (gate)) : 0)
+ #define smu_powergate_vcn(smu, gate) \
+-	((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
++	((smu)->ppt_funcs->powergate_vcn ? (smu)->ppt_funcs->powergate_vcn((smu), (gate)) : 0)
+ 
+ #define smu_get_vbios_bootup_values(smu) \
+-	((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
++	((smu)->ppt_funcs->get_vbios_bootup_values ? (smu)->ppt_funcs->get_vbios_bootup_values((smu)) : 0)
+ #define smu_get_clk_info_from_vbios(smu) \
+-	((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
++	((smu)->ppt_funcs->get_clk_info_from_vbios ? (smu)->ppt_funcs->get_clk_info_from_vbios((smu)) : 0)
+ #define smu_check_pptable(smu) \
+-	((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
++	((smu)->ppt_funcs->check_pptable ? (smu)->ppt_funcs->check_pptable((smu)) : 0)
+ #define smu_parse_pptable(smu) \
+-	((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
++	((smu)->ppt_funcs->parse_pptable ? (smu)->ppt_funcs->parse_pptable((smu)) : 0)
+ #define smu_populate_smc_tables(smu) \
+-	((smu)->funcs->populate_smc_tables ? (smu)->funcs->populate_smc_tables((smu)) : 0)
++	((smu)->ppt_funcs->populate_smc_tables ? (smu)->ppt_funcs->populate_smc_tables((smu)) : 0)
+ #define smu_check_fw_version(smu) \
+-	((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
++	((smu)->ppt_funcs->check_fw_version ? (smu)->ppt_funcs->check_fw_version((smu)) : 0)
+ #define smu_write_pptable(smu) \
+-	((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
++	((smu)->ppt_funcs->write_pptable ? (smu)->ppt_funcs->write_pptable((smu)) : 0)
+ #define smu_set_min_dcef_deep_sleep(smu) \
+-	((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
++	((smu)->ppt_funcs->set_min_dcef_deep_sleep ? (smu)->ppt_funcs->set_min_dcef_deep_sleep((smu)) : 0)
+ #define smu_set_tool_table_location(smu) \
+-	((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
++	((smu)->ppt_funcs->set_tool_table_location ? (smu)->ppt_funcs->set_tool_table_location((smu)) : 0)
+ #define smu_notify_memory_pool_location(smu) \
+-	((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
++	((smu)->ppt_funcs->notify_memory_pool_location ? (smu)->ppt_funcs->notify_memory_pool_location((smu)) : 0)
+ #define smu_gfx_off_control(smu, enable) \
+-	((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
++	((smu)->ppt_funcs->gfx_off_control ? (smu)->ppt_funcs->gfx_off_control((smu), (enable)) : 0)
+ 
+ #define smu_set_last_dcef_min_deep_sleep_clk(smu) \
+-	((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
++	((smu)->ppt_funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->ppt_funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
+ #define smu_system_features_control(smu, en) \
+-	((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
++	((smu)->ppt_funcs->system_features_control ? (smu)->ppt_funcs->system_features_control((smu), (en)) : 0)
+ #define smu_init_max_sustainable_clocks(smu) \
+-	((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
++	((smu)->ppt_funcs->init_max_sustainable_clocks ? (smu)->ppt_funcs->init_max_sustainable_clocks((smu)) : 0)
+ #define smu_set_default_od_settings(smu, initialize) \
+ 	((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
+ 
+ #define smu_send_smc_msg(smu, msg) \
+-	((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
++	((smu)->ppt_funcs->send_smc_msg? (smu)->ppt_funcs->send_smc_msg((smu), (msg)) : 0)
+ #define smu_send_smc_msg_with_param(smu, msg, param) \
+-	((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
++	((smu)->ppt_funcs->send_smc_msg_with_param? (smu)->ppt_funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
+ #define smu_read_smc_arg(smu, arg) \
+-	((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
++	((smu)->ppt_funcs->read_smc_arg? (smu)->ppt_funcs->read_smc_arg((smu), (arg)) : 0)
+ #define smu_alloc_dpm_context(smu) \
+ 	((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
+ #define smu_init_display_count(smu, count) \
+-	((smu)->funcs->init_display_count ? (smu)->funcs->init_display_count((smu), (count)) : 0)
++	((smu)->ppt_funcs->init_display_count ? (smu)->ppt_funcs->init_display_count((smu), (count)) : 0)
+ #define smu_feature_set_allowed_mask(smu) \
+-	((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
++	((smu)->ppt_funcs->set_allowed_mask? (smu)->ppt_funcs->set_allowed_mask((smu)) : 0)
+ #define smu_feature_get_enabled_mask(smu, mask, num) \
+-	((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
++	((smu)->ppt_funcs->get_enabled_mask? (smu)->ppt_funcs->get_enabled_mask((smu), (mask), (num)) : 0)
+ #define smu_is_dpm_running(smu) \
+ 	((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
+ #define smu_notify_display_change(smu) \
+-	((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
++	((smu)->ppt_funcs->notify_display_change? (smu)->ppt_funcs->notify_display_change((smu)) : 0)
+ #define smu_store_powerplay_table(smu) \
+ 	((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
+ #define smu_check_powerplay_table(smu) \
+@@ -107,19 +107,19 @@
+ 	((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
+ 
+ #define smu_get_current_clk_freq(smu, clk_id, value) \
+-	((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
++	((smu)->ppt_funcs->get_current_clk_freq? (smu)->ppt_funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
+ 
+ #define smu_tables_init(smu, tab) \
+ 	((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
+ #define smu_set_thermal_fan_table(smu) \
+ 	((smu)->ppt_funcs->set_thermal_fan_table ? (smu)->ppt_funcs->set_thermal_fan_table((smu)) : 0)
+ #define smu_start_thermal_control(smu) \
+-	((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
++	((smu)->ppt_funcs->start_thermal_control? (smu)->ppt_funcs->start_thermal_control((smu)) : 0)
+ #define smu_stop_thermal_control(smu) \
+-	((smu)->funcs->stop_thermal_control? (smu)->funcs->stop_thermal_control((smu)) : 0)
++	((smu)->ppt_funcs->stop_thermal_control? (smu)->ppt_funcs->stop_thermal_control((smu)) : 0)
+ 
+ #define smu_smc_read_sensor(smu, sensor, data, size) \
+-	((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
++	((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
+ 
+ #define smu_pre_display_config_changed(smu) \
+ 	((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
+@@ -157,14 +157,14 @@
+ 
+ 
+ #define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
+-	((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
++	((smu)->ppt_funcs->store_cc6_data ? (smu)->ppt_funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
+ 
+ #define smu_get_dal_power_level(smu, clocks) \
+-	((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
++	((smu)->ppt_funcs->get_dal_power_level ? (smu)->ppt_funcs->get_dal_power_level((smu), (clocks)) : 0)
+ #define smu_get_perf_level(smu, designation, level) \
+-	((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
++	((smu)->ppt_funcs->get_perf_level ? (smu)->ppt_funcs->get_perf_level((smu), (designation), (level)) : 0)
+ #define smu_get_current_shallow_sleep_clocks(smu, clocks) \
+-	((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
++	((smu)->ppt_funcs->get_current_shallow_sleep_clocks ? (smu)->ppt_funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
+ 
+ #define smu_dpm_set_uvd_enable(smu, enable) \
+ 	((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
+@@ -180,10 +180,10 @@
+ #define smu_get_thermal_temperature_range(smu, range) \
+ 	((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
+ #define smu_register_irq_handler(smu) \
+-	((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
++	((smu)->ppt_funcs->register_irq_handler ? (smu)->ppt_funcs->register_irq_handler(smu) : 0)
+ 
+ #define smu_get_dpm_ultimate_freq(smu, param, min, max) \
+-		((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
++		((smu)->ppt_funcs->get_dpm_ultimate_freq ? (smu)->ppt_funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
+ 
+ #define smu_asic_set_performance_level(smu, level) \
+ 	((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
+@@ -193,10 +193,10 @@
+ 		((smu)->ppt_funcs->get_dpm_clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EINVAL)
+ 
+ #define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
+-		((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
++		((smu)->ppt_funcs->set_soft_freq_limited_range ? (smu)->ppt_funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
+ 
+ #define smu_override_pcie_parameters(smu) \
+-		((smu)->funcs->override_pcie_parameters ? (smu)->funcs->override_pcie_parameters((smu)) : 0)
++		((smu)->ppt_funcs->override_pcie_parameters ? (smu)->ppt_funcs->override_pcie_parameters((smu)) : 0)
+ 
+ #define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) \
+ 		((smu)->ppt_funcs->update_pcie_parameters ? (smu)->ppt_funcs->update_pcie_parameters((smu), (pcie_gen_cap), (pcie_width_cap)) : 0)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 6794fc4cacb5..7e882999abad 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -30,9 +30,6 @@
+ #include "smu_v11_0.h"
+ #include "soc15_common.h"
+ #include "atom.h"
+-#include "vega20_ppt.h"
+-#include "arcturus_ppt.h"
+-#include "navi10_ppt.h"
+ #include "amd_pcie.h"
+ 
+ #include "asic_reg/thm/thm_11_0_2_offset.h"
+@@ -60,7 +57,7 @@ static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
+ 	return 0;
+ }
+ 
+-static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
++int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+ 
+@@ -87,7 +84,7 @@ static int smu_v11_0_wait_for_response(struct smu_context *smu)
+ 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
+ }
+ 
+-static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
++int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+ 	int ret = 0, index = 0;
+@@ -112,7 +109,7 @@ static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
+ 
+ }
+ 
+-static int
++int
+ smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
+ 			      uint32_t param)
+ {
+@@ -143,7 +140,7 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_init_microcode(struct smu_context *smu)
++int smu_v11_0_init_microcode(struct smu_context *smu)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+ 	const char *chip_name;
+@@ -205,7 +202,7 @@ static int smu_v11_0_init_microcode(struct smu_context *smu)
+ 	return err;
+ }
+ 
+-static int smu_v11_0_load_microcode(struct smu_context *smu)
++int smu_v11_0_load_microcode(struct smu_context *smu)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+ 	const uint32_t *src;
+@@ -243,7 +240,7 @@ static int smu_v11_0_load_microcode(struct smu_context *smu)
+ 	return 0;
+ }
+ 
+-static int smu_v11_0_check_fw_status(struct smu_context *smu)
++int smu_v11_0_check_fw_status(struct smu_context *smu)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+ 	uint32_t mp1_fw_flags;
+@@ -258,7 +255,7 @@ static int smu_v11_0_check_fw_status(struct smu_context *smu)
+ 	return -EIO;
+ }
+ 
+-static int smu_v11_0_check_fw_version(struct smu_context *smu)
++int smu_v11_0_check_fw_version(struct smu_context *smu)
+ {
+ 	uint32_t if_version = 0xff, smu_version = 0xff;
+ 	uint16_t smu_major;
+@@ -356,7 +353,7 @@ static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
+ 	return 0;
+ }
+ 
+-static int smu_v11_0_setup_pptable(struct smu_context *smu)
++int smu_v11_0_setup_pptable(struct smu_context *smu)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+ 	const struct smc_firmware_header_v1_0 *hdr;
+@@ -435,7 +432,7 @@ static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
+ 	return 0;
+ }
+ 
+-static int smu_v11_0_init_smc_tables(struct smu_context *smu)
++int smu_v11_0_init_smc_tables(struct smu_context *smu)
+ {
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 	struct smu_table *tables = NULL;
+@@ -462,7 +459,7 @@ static int smu_v11_0_init_smc_tables(struct smu_context *smu)
+ 	return 0;
+ }
+ 
+-static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
++int smu_v11_0_fini_smc_tables(struct smu_context *smu)
+ {
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 	int ret = 0;
+@@ -482,7 +479,7 @@ static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
+ 	return 0;
+ }
+ 
+-static int smu_v11_0_init_power(struct smu_context *smu)
++int smu_v11_0_init_power(struct smu_context *smu)
+ {
+ 	struct smu_power_context *smu_power = &smu->smu_power;
+ 
+@@ -500,7 +497,7 @@ static int smu_v11_0_init_power(struct smu_context *smu)
+ 	return 0;
+ }
+ 
+-static int smu_v11_0_fini_power(struct smu_context *smu)
++int smu_v11_0_fini_power(struct smu_context *smu)
+ {
+ 	struct smu_power_context *smu_power = &smu->smu_power;
+ 
+@@ -577,7 +574,7 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
+ 	return 0;
+ }
+ 
+-static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
++int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
+ {
+ 	int ret, index;
+ 	struct amdgpu_device *adev = smu->adev;
+@@ -674,7 +671,7 @@ static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
+ 	return 0;
+ }
+ 
+-static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
++int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
+ {
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 	struct smu_table *memory_pool = &smu_table->memory_pool;
+@@ -720,7 +717,7 @@ static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_check_pptable(struct smu_context *smu)
++int smu_v11_0_check_pptable(struct smu_context *smu)
+ {
+ 	int ret;
+ 
+@@ -728,7 +725,7 @@ static int smu_v11_0_check_pptable(struct smu_context *smu)
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_parse_pptable(struct smu_context *smu)
++int smu_v11_0_parse_pptable(struct smu_context *smu)
+ {
+ 	int ret;
+ 
+@@ -752,7 +749,7 @@ static int smu_v11_0_parse_pptable(struct smu_context *smu)
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
++int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
+ {
+ 	int ret;
+ 
+@@ -761,7 +758,7 @@ static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_write_pptable(struct smu_context *smu)
++int smu_v11_0_write_pptable(struct smu_context *smu)
+ {
+ 	struct smu_table_context *table_context = &smu->smu_table;
+ 	int ret = 0;
+@@ -772,7 +769,7 @@ static int smu_v11_0_write_pptable(struct smu_context *smu)
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
++int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
+ {
+ 	int ret;
+ 
+@@ -784,7 +781,7 @@ static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t cl
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
++int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
+ {
+ 	struct smu_table_context *table_context = &smu->smu_table;
+ 
+@@ -793,14 +790,10 @@ static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
+ 	if (!table_context)
+ 		return -EINVAL;
+ 
+-	if (smu->funcs->set_deep_sleep_dcefclk)
+-		return smu->funcs->set_deep_sleep_dcefclk(smu,
+-				table_context->boot_values.dcefclk / 100);
+-
+-	return 0;
++	return smu_v11_0_set_deep_sleep_dcefclk(smu, table_context->boot_values.dcefclk / 100);
+ }
+ 
+-static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
++int smu_v11_0_set_tool_table_location(struct smu_context *smu)
+ {
+ 	int ret = 0;
+ 	struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
+@@ -818,7 +811,7 @@ static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
++int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
+ {
+ 	int ret = 0;
+ 
+@@ -830,7 +823,7 @@ static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
+ }
+ 
+ 
+-static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
++int smu_v11_0_set_allowed_mask(struct smu_context *smu)
+ {
+ 	struct smu_feature *feature = &smu->smu_feature;
+ 	int ret = 0;
+@@ -857,7 +850,7 @@ static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
++int smu_v11_0_get_enabled_mask(struct smu_context *smu,
+ 				      uint32_t *feature_mask, uint32_t num)
+ {
+ 	uint32_t feature_mask_high = 0, feature_mask_low = 0;
+@@ -886,7 +879,7 @@ static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_system_features_control(struct smu_context *smu,
++int smu_v11_0_system_features_control(struct smu_context *smu,
+ 					     bool en)
+ {
+ 	struct smu_feature *feature = &smu->smu_feature;
+@@ -912,7 +905,7 @@ static int smu_v11_0_system_features_control(struct smu_context *smu,
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_notify_display_change(struct smu_context *smu)
++int smu_v11_0_notify_display_change(struct smu_context *smu)
+ {
+ 	int ret = 0;
+ 
+@@ -970,7 +963,7 @@ smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
++int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
+ {
+ 	struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
+ 	int ret = 0;
+@@ -1050,7 +1043,7 @@ static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
+ 	return 0;
+ }
+ 
+-static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
++int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
+ {
+ 	int ret = 0;
+ 
+@@ -1078,7 +1071,7 @@ static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
+ 	return 0;
+ }
+ 
+-static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
++int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
+ 					  enum smu_clk_type clk_id,
+ 					  uint32_t *value)
+ {
+@@ -1157,7 +1150,7 @@ static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
+ 	return 0;
+ }
+ 
+-static int smu_v11_0_start_thermal_control(struct smu_context *smu)
++int smu_v11_0_start_thermal_control(struct smu_context *smu)
+ {
+ 	int ret = 0;
+ 	struct smu_temperature_range range;
+@@ -1199,7 +1192,7 @@ static int smu_v11_0_start_thermal_control(struct smu_context *smu)
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_stop_thermal_control(struct smu_context *smu)
++int smu_v11_0_stop_thermal_control(struct smu_context *smu)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+ 
+@@ -1232,7 +1225,7 @@ static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
+ 
+ }
+ 
+-static int smu_v11_0_read_sensor(struct smu_context *smu,
++int smu_v11_0_read_sensor(struct smu_context *smu,
+ 				 enum amd_pp_sensors sensor,
+ 				 void *data, uint32_t *size)
+ {
+@@ -1269,7 +1262,7 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
+ 	return ret;
+ }
+ 
+-static int
++int
+ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
+ 					struct pp_display_clock_request
+ 					*clock_req)
+@@ -1322,7 +1315,7 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
++int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
+ {
+ 	int ret = 0;
+ 	struct amdgpu_device *adev = smu->adev;
+@@ -1347,7 +1340,7 @@ static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
+ 	return ret;
+ }
+ 
+-static uint32_t
++uint32_t
+ smu_v11_0_get_fan_control_mode(struct smu_context *smu)
+ {
+ 	if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
+@@ -1387,7 +1380,7 @@ smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
+ 	return 0;
+ }
+ 
+-static int
++int
+ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+@@ -1416,7 +1409,7 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
+ 	return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
+ }
+ 
+-static int
++int
+ smu_v11_0_set_fan_control_mode(struct smu_context *smu,
+ 			       uint32_t mode)
+ {
+@@ -1444,7 +1437,7 @@ smu_v11_0_set_fan_control_mode(struct smu_context *smu,
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
++int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
+ 				       uint32_t speed)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+@@ -1473,7 +1466,7 @@ static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
+ #define XGMI_STATE_D0 1
+ #define XGMI_STATE_D3 0
+ 
+-static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
++int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
+ 				     uint32_t pstate)
+ {
+ 	int ret = 0;
+@@ -1525,7 +1518,7 @@ static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs= {
+ 	.process = smu_v11_0_irq_process,
+ };
+ 
+-static int smu_v11_0_register_irq_handler(struct smu_context *smu)
++int smu_v11_0_register_irq_handler(struct smu_context *smu)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+ 	struct amdgpu_irq_src *irq_src = smu->irq_source;
+@@ -1557,7 +1550,7 @@ static int smu_v11_0_register_irq_handler(struct smu_context *smu)
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
++int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
+ 		struct pp_smu_nv_clock_table *max_clocks)
+ {
+ 	struct smu_table_context *table_context = &smu->smu_table;
+@@ -1587,7 +1580,7 @@ static int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
+ 	return 0;
+ }
+ 
+-static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
++int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
+ {
+ 	int ret = 0;
+ 
+@@ -1601,7 +1594,7 @@ static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v
+ 	return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq);
+ }
+ 
+-static bool smu_v11_0_baco_is_support(struct smu_context *smu)
++bool smu_v11_0_baco_is_support(struct smu_context *smu)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+ 	struct smu_baco_context *smu_baco = &smu->smu_baco;
+@@ -1625,7 +1618,7 @@ static bool smu_v11_0_baco_is_support(struct smu_context *smu)
+ 	return false;
+ }
+ 
+-static enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
++enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
+ {
+ 	struct smu_baco_context *smu_baco = &smu->smu_baco;
+ 	enum smu_baco_state baco_state;
+@@ -1637,7 +1630,7 @@ static enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
+ 	return baco_state;
+ }
+ 
+-static int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
++int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
+ {
+ 
+ 	struct smu_baco_context *smu_baco = &smu->smu_baco;
+@@ -1661,7 +1654,7 @@ static int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_baco_reset(struct smu_context *smu)
++int smu_v11_0_baco_reset(struct smu_context *smu)
+ {
+ 	int ret = 0;
+ 
+@@ -1682,7 +1675,7 @@ static int smu_v11_0_baco_reset(struct smu_context *smu)
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
++int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
+ 						 uint32_t *min, uint32_t *max)
+ {
+ 	int ret = 0, clk_id = 0;
+@@ -1717,7 +1710,7 @@ static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
++int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ 			    uint32_t min, uint32_t max)
+ {
+ 	int ret = 0, clk_id = 0;
+@@ -1746,7 +1739,7 @@ static int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum s
+ 	return ret;
+ }
+ 
+-static int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
++int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+ 	uint32_t pcie_gen = 0, pcie_width = 0;
+@@ -1786,79 +1779,3 @@ static int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
+ 	return ret;
+ 
+ }
+-
+-
+-static const struct smu_funcs smu_v11_0_funcs = {
+-	.init_microcode = smu_v11_0_init_microcode,
+-	.load_microcode = smu_v11_0_load_microcode,
+-	.check_fw_status = smu_v11_0_check_fw_status,
+-	.check_fw_version = smu_v11_0_check_fw_version,
+-	.send_smc_msg = smu_v11_0_send_msg,
+-	.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
+-	.read_smc_arg = smu_v11_0_read_arg,
+-	.setup_pptable = smu_v11_0_setup_pptable,
+-	.init_smc_tables = smu_v11_0_init_smc_tables,
+-	.fini_smc_tables = smu_v11_0_fini_smc_tables,
+-	.init_power = smu_v11_0_init_power,
+-	.fini_power = smu_v11_0_fini_power,
+-	.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
+-	.get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
+-	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+-	.check_pptable = smu_v11_0_check_pptable,
+-	.parse_pptable = smu_v11_0_parse_pptable,
+-	.populate_smc_tables = smu_v11_0_populate_smc_pptable,
+-	.write_pptable = smu_v11_0_write_pptable,
+-	.set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
+-	.set_tool_table_location = smu_v11_0_set_tool_table_location,
+-	.init_display_count = smu_v11_0_init_display_count,
+-	.set_allowed_mask = smu_v11_0_set_allowed_mask,
+-	.get_enabled_mask = smu_v11_0_get_enabled_mask,
+-	.system_features_control = smu_v11_0_system_features_control,
+-	.notify_display_change = smu_v11_0_notify_display_change,
+-	.set_power_limit = smu_v11_0_set_power_limit,
+-	.get_current_clk_freq = smu_v11_0_get_current_clk_freq,
+-	.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
+-	.start_thermal_control = smu_v11_0_start_thermal_control,
+-	.stop_thermal_control = smu_v11_0_stop_thermal_control,
+-	.read_sensor = smu_v11_0_read_sensor,
+-	.set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
+-	.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
+-	.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
+-	.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
+-	.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
+-	.set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
+-	.set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
+-	.gfx_off_control = smu_v11_0_gfx_off_control,
+-	.register_irq_handler = smu_v11_0_register_irq_handler,
+-	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
+-	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
+-	.baco_is_support= smu_v11_0_baco_is_support,
+-	.baco_get_state = smu_v11_0_baco_get_state,
+-	.baco_set_state = smu_v11_0_baco_set_state,
+-	.baco_reset = smu_v11_0_baco_reset,
+-	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+-	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+-	.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+-};
+-
+-void smu_v11_0_set_smu_funcs(struct smu_context *smu)
+-{
+-	struct amdgpu_device *adev = smu->adev;
+-
+-	smu->funcs = &smu_v11_0_funcs;
+-	switch (adev->asic_type) {
+-	case CHIP_VEGA20:
+-		vega20_set_ppt_funcs(smu);
+-		break;
+-	case CHIP_ARCTURUS:
+-		arcturus_set_ppt_funcs(smu);
+-		break;
+-	case CHIP_NAVI10:
+-	case CHIP_NAVI14:
+-	case CHIP_NAVI12:
+-		navi10_set_ppt_funcs(smu);
+-		break;
+-	default:
+-		pr_warn("Unknown asic for smu11\n");
+-	}
+-}
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 92e1c0a3f428..139dd737eaa5 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -30,7 +30,6 @@
+ #include "smu_v12_0.h"
+ #include "soc15_common.h"
+ #include "atom.h"
+-#include "renoir_ppt.h"
+ 
+ #include "asic_reg/mp/mp_12_0_0_offset.h"
+ #include "asic_reg/mp/mp_12_0_0_sh_mask.h"
+@@ -42,7 +41,7 @@
+ #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK          0x00000006L
+ #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT        0x1
+ 
+-static int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
++int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
+ 					      uint16_t msg)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+@@ -51,7 +50,7 @@ static int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
+ 	return 0;
+ }
+ 
+-static int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg)
++int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+ 
+@@ -59,7 +58,7 @@ static int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg)
+ 	return 0;
+ }
+ 
+-static int smu_v12_0_wait_for_response(struct smu_context *smu)
++int smu_v12_0_wait_for_response(struct smu_context *smu)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+ 	uint32_t cur_value, i;
+@@ -78,7 +77,7 @@ static int smu_v12_0_wait_for_response(struct smu_context *smu)
+ 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
+ }
+ 
+-static int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
++int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+ 	int ret = 0, index = 0;
+@@ -103,7 +102,7 @@ static int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
+ 
+ }
+ 
+-static int
++int
+ smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
+ 			      uint32_t param)
+ {
+@@ -133,7 +132,7 @@ smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
+ 	return ret;
+ }
+ 
+-static int smu_v12_0_check_fw_status(struct smu_context *smu)
++int smu_v12_0_check_fw_status(struct smu_context *smu)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+ 	uint32_t mp1_fw_flags;
+@@ -148,7 +147,7 @@ static int smu_v12_0_check_fw_status(struct smu_context *smu)
+ 	return -EIO;
+ }
+ 
+-static int smu_v12_0_check_fw_version(struct smu_context *smu)
++int smu_v12_0_check_fw_version(struct smu_context *smu)
+ {
+ 	uint32_t if_version = 0xff, smu_version = 0xff;
+ 	uint16_t smu_major;
+@@ -182,7 +181,7 @@ static int smu_v12_0_check_fw_version(struct smu_context *smu)
+ 	return ret;
+ }
+ 
+-static int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
++int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
+ {
+ 	if (!(smu->adev->flags & AMD_IS_APU))
+ 		return 0;
+@@ -193,7 +192,7 @@ static int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
+ 		return smu_send_smc_msg(smu, SMU_MSG_PowerUpSdma);
+ }
+ 
+-static int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
++int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
+ {
+ 	if (!(smu->adev->flags & AMD_IS_APU))
+ 		return 0;
+@@ -204,7 +203,7 @@ static int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
+ 		return smu_send_smc_msg(smu, SMU_MSG_PowerUpVcn);
+ }
+ 
+-static int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
++int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
+ {
+ 	if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
+ 		return 0;
+@@ -225,7 +224,7 @@ static int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
+  * Returns 2=Not in GFXOFF.
+  * Returns 3=Transition into GFXOFF.
+  */
+-static uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
++uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
+ {
+ 	uint32_t reg;
+ 	uint32_t gfxOff_Status = 0;
+@@ -238,7 +237,7 @@ static uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
+ 	return gfxOff_Status;
+ }
+ 
+-static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
++int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
+ {
+ 	int ret = 0, timeout = 500;
+ 
+@@ -262,7 +261,7 @@ static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
+ 	return ret;
+ }
+ 
+-static int smu_v12_0_init_smc_tables(struct smu_context *smu)
++int smu_v12_0_init_smc_tables(struct smu_context *smu)
+ {
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 	struct smu_table *tables = NULL;
+@@ -280,7 +279,7 @@ static int smu_v12_0_init_smc_tables(struct smu_context *smu)
+ 	return smu_tables_init(smu, tables);
+ }
+ 
+-static int smu_v12_0_fini_smc_tables(struct smu_context *smu)
++int smu_v12_0_fini_smc_tables(struct smu_context *smu)
+ {
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 
+@@ -296,7 +295,7 @@ static int smu_v12_0_fini_smc_tables(struct smu_context *smu)
+ 	return 0;
+ }
+ 
+-static int smu_v12_0_populate_smc_tables(struct smu_context *smu)
++int smu_v12_0_populate_smc_tables(struct smu_context *smu)
+ {
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 	struct smu_table *table = NULL;
+@@ -311,7 +310,7 @@ static int smu_v12_0_populate_smc_tables(struct smu_context *smu)
+ 	return smu_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
+ }
+ 
+-static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
++int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
+ 						 uint32_t *min, uint32_t *max)
+ {
+ 	int ret = 0;
+@@ -389,11 +388,11 @@ static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk
+ 	return ret;
+ }
+ 
+-static int smu_v12_0_mode2_reset(struct smu_context *smu){
++int smu_v12_0_mode2_reset(struct smu_context *smu){
+ 	return smu_v12_0_send_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2);
+ }
+ 
+-static int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
++int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
+ 			    uint32_t min, uint32_t max)
+ {
+ 	int ret = 0;
+@@ -446,36 +445,3 @@ static int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum s
+ 
+ 	return ret;
+ }
+-
+-static const struct smu_funcs smu_v12_0_funcs = {
+-	.check_fw_status = smu_v12_0_check_fw_status,
+-	.check_fw_version = smu_v12_0_check_fw_version,
+-	.powergate_sdma = smu_v12_0_powergate_sdma,
+-	.powergate_vcn = smu_v12_0_powergate_vcn,
+-	.send_smc_msg = smu_v12_0_send_msg,
+-	.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
+-	.read_smc_arg = smu_v12_0_read_arg,
+-	.set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
+-	.gfx_off_control = smu_v12_0_gfx_off_control,
+-	.init_smc_tables = smu_v12_0_init_smc_tables,
+-	.fini_smc_tables = smu_v12_0_fini_smc_tables,
+-	.populate_smc_tables = smu_v12_0_populate_smc_tables,
+-	.get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
+-	.mode2_reset = smu_v12_0_mode2_reset,
+-	.set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
+-};
+-
+-void smu_v12_0_set_smu_funcs(struct smu_context *smu)
+-{
+-	struct amdgpu_device *adev = smu->adev;
+-
+-	smu->funcs = &smu_v12_0_funcs;
+-
+-	switch (adev->asic_type) {
+-	case CHIP_RENOIR:
+-		renoir_set_ppt_funcs(smu);
+-		break;
+-	default:
+-		pr_warn("Unknown asic for smu12\n");
+-	}
+-}
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 4039efcdcb1f..7125406c6256 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -2248,7 +2248,7 @@ vega20_notify_smc_dispaly_config(struct smu_context *smu)
+ 	if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
+ 		clock_req.clock_type = amd_pp_dcef_clock;
+ 		clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
+-		if (!smu->funcs->display_clock_voltage_request(smu, &clock_req)) {
++		if (!smu_v11_0_display_clock_voltage_request(smu, &clock_req)) {
+ 			if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
+ 				ret = smu_send_smc_msg_with_param(smu,
+ 								  SMU_MSG_SetMinDeepSleepDcefclk,
+@@ -3031,7 +3031,7 @@ static int vega20_read_sensor(struct smu_context *smu,
+ 		*size = 4;
+ 		break;
+ 	default:
+-		ret = smu_smc_read_sensor(smu, sensor, data, size);
++		ret = smu_v11_0_read_sensor(smu, sensor, data, size);
+ 	}
+ 	mutex_unlock(&smu->sensor_lock);
+ 
+@@ -3212,7 +3212,56 @@ static const struct pptable_funcs vega20_ppt_funcs = {
+ 	.set_watermarks_table = vega20_set_watermarks_table,
+ 	.get_thermal_temperature_range = vega20_get_thermal_temperature_range,
+ 	.set_df_cstate = vega20_set_df_cstate,
+-	.update_pcie_parameters = vega20_update_pcie_parameters
++	.update_pcie_parameters = vega20_update_pcie_parameters,
++	.init_microcode = smu_v11_0_init_microcode,
++	.load_microcode = smu_v11_0_load_microcode,
++	.init_smc_tables = smu_v11_0_init_smc_tables,
++	.fini_smc_tables = smu_v11_0_fini_smc_tables,
++	.init_power = smu_v11_0_init_power,
++	.fini_power = smu_v11_0_fini_power,
++	.check_fw_status = smu_v11_0_check_fw_status,
++	.setup_pptable = smu_v11_0_setup_pptable,
++	.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
++	.get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
++	.check_pptable = smu_v11_0_check_pptable,
++	.parse_pptable = smu_v11_0_parse_pptable,
++	.populate_smc_tables = smu_v11_0_populate_smc_pptable,
++	.check_fw_version = smu_v11_0_check_fw_version,
++	.write_pptable = smu_v11_0_write_pptable,
++	.set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
++	.set_tool_table_location = smu_v11_0_set_tool_table_location,
++	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
++	.system_features_control = smu_v11_0_system_features_control,
++	.send_smc_msg = smu_v11_0_send_msg,
++	.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
++	.read_smc_arg = smu_v11_0_read_arg,
++	.init_display_count = smu_v11_0_init_display_count,
++	.set_allowed_mask = smu_v11_0_set_allowed_mask,
++	.get_enabled_mask = smu_v11_0_get_enabled_mask,
++	.notify_display_change = smu_v11_0_notify_display_change,
++	.set_power_limit = smu_v11_0_set_power_limit,
++	.get_current_clk_freq = smu_v11_0_get_current_clk_freq,
++	.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
++	.start_thermal_control = smu_v11_0_start_thermal_control,
++	.stop_thermal_control = smu_v11_0_stop_thermal_control,
++	.set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
++	.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
++	.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
++	.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
++	.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
++	.set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
++	.set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
++	.gfx_off_control = smu_v11_0_gfx_off_control,
++	.register_irq_handler = smu_v11_0_register_irq_handler,
++	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
++	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
++	.baco_is_support= smu_v11_0_baco_is_support,
++	.baco_get_state = smu_v11_0_baco_get_state,
++	.baco_set_state = smu_v11_0_baco_set_state,
++	.baco_reset = smu_v11_0_baco_reset,
++	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
++	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
++	.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+ };
+ 
+ void vega20_set_ppt_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4269-drm-amdgpu-display-add-dc-feature-mask-for-psr-enabl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4269-drm-amdgpu-display-add-dc-feature-mask-for-psr-enabl.patch
new file mode 100644
index 00000000..a65a287e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4269-drm-amdgpu-display-add-dc-feature-mask-for-psr-enabl.patch
@@ -0,0 +1,51 @@
+From 01086a885fa31e3d4a9047d8cdddf21decd987f1 Mon Sep 17 00:00:00 2001
+From: Roman Li <Roman.Li@amd.com>
+Date: Tue, 1 Oct 2019 09:45:38 -0400
+Subject: [PATCH 4269/4736] drm/amdgpu/display: add dc feature mask for psr
+ enablement
+
+[Why]
+Adding psr mask to dc features allows selectively disable/enable psr.
+Current psr implementation may not work with non-pageflipping application.
+Until resolved it should be disabled by default.
+
+[How]
+Add dcfeaturemask for psr enablement. Disable by default.
+To enable set amdgpu.dcfeaturemask=0x8 in grub kernel command line.
+
+Signed-off-by: Roman Li <Roman.Li@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
+ drivers/gpu/drm/amd/include/amd_shared.h          | 1 +
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 8139cffd5b88..ff89ca40f82c 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -2406,7 +2406,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
+ 		} else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
+ 			amdgpu_dm_update_connector_after_detect(aconnector);
+ 			register_backlight_device(dm, link);
+-			amdgpu_dm_set_psr_caps(link);
++			if (amdgpu_dc_feature_mask & DC_PSR_MASK)
++				amdgpu_dm_set_psr_caps(link);
+ 		}
+ 
+ 
+diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
+index 8889aaceec60..8340ec0ab792 100644
+--- a/drivers/gpu/drm/amd/include/amd_shared.h
++++ b/drivers/gpu/drm/amd/include/amd_shared.h
+@@ -143,6 +143,7 @@ enum PP_FEATURE_MASK {
+ enum DC_FEATURE_MASK {
+ 	DC_FBC_MASK = 0x1,
+ 	DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,
++	DC_PSR_MASK = 0x8,
+ };
+ 
+ enum amd_dpm_forced_level;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4270-drm-amd-display-Change-Navi14-s-DWB-flag-to-1.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4270-drm-amd-display-Change-Navi14-s-DWB-flag-to-1.patch
new file mode 100644
index 00000000..2632fc48
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4270-drm-amd-display-Change-Navi14-s-DWB-flag-to-1.patch
@@ -0,0 +1,36 @@
+From b1dc55ff5d1670435b9aadcca3436248bb387ecb Mon Sep 17 00:00:00 2001
+From: Zhan liu <zhan.liu@amd.com>
+Date: Tue, 22 Oct 2019 10:50:21 -0400
+Subject: [PATCH 4270/4736] drm/amd/display: Change Navi14's DWB flag to 1
+
+[Why]
+DWB (Display Writeback) flag needs to be enabled as 1, or system
+will throw out a few warnings when creating dcn20 resource pool.
+Also, Navi14's dwb setting needs to match Navi10's,
+which has already been set to 1.
+
+[How]
+Change value of num_dwb from 0 to 1.
+
+Signed-off-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index b6ec81096d3a..d1c7e10cb722 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -823,7 +823,7 @@ static const struct resource_caps res_cap_nv14 = {
+ 		.num_audio = 6,
+ 		.num_stream_encoder = 5,
+ 		.num_pll = 5,
+-		.num_dwb = 0,
++		.num_dwb = 1,
+ 		.num_ddc = 5,
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4271-drm-amdkfd-don-t-use-dqm-lock-during-device-reset-su.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4271-drm-amdkfd-don-t-use-dqm-lock-during-device-reset-su.patch
new file mode 100644
index 00000000..6c12980b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4271-drm-amdkfd-don-t-use-dqm-lock-during-device-reset-su.patch
@@ -0,0 +1,264 @@
+From e4339c1a7be1491127ecfb14b1631197e5fdb28b Mon Sep 17 00:00:00 2001
+From: Philip Yang <Philip.Yang@amd.com>
+Date: Fri, 18 Oct 2019 10:15:21 -0400
+Subject: [PATCH 4271/4736] drm/amdkfd: don't use dqm lock during device
+ reset/suspend/resume
+
+If device reset/suspend/resume failed for some reason, dqm lock is
+hold forever and this causes deadlock. Below is a kernel backtrace when
+application open kfd after suspend/resume failed.
+
+Instead of holding dqm lock in pre_reset and releasing dqm lock in
+post_reset, add dqm->sched_running flag which is modified in
+dqm->ops.start and dqm->ops.stop. The flag doesn't need lock protection
+because write/read are all inside dqm lock.
+
+For HWS case, map_queues_cpsch and unmap_queues_cpsch checks
+sched_running flag before sending the updated runlist.
+
+v2: For no-HWS case, when device is stopped, don't call
+load/destroy_mqd for eviction, restore and create queue, and avoid
+debugfs dump hdqs.
+
+Backtrace of dqm lock deadlock:
+
+[Thu Oct 17 16:43:37 2019] INFO: task rocminfo:3024 blocked for more
+than 120 seconds.
+[Thu Oct 17 16:43:37 2019]       Not tainted
+5.0.0-rc1-kfd-compute-rocm-dkms-no-npi-1131 #1
+[Thu Oct 17 16:43:37 2019] "echo 0 >
+/proc/sys/kernel/hung_task_timeout_secs" disables this message.
+[Thu Oct 17 16:43:37 2019] rocminfo        D    0  3024   2947
+0x80000000
+[Thu Oct 17 16:43:37 2019] Call Trace:
+[Thu Oct 17 16:43:37 2019]  ? __schedule+0x3d9/0x8a0
+[Thu Oct 17 16:43:37 2019]  schedule+0x32/0x70
+[Thu Oct 17 16:43:37 2019]  schedule_preempt_disabled+0xa/0x10
+[Thu Oct 17 16:43:37 2019]  __mutex_lock.isra.9+0x1e3/0x4e0
+[Thu Oct 17 16:43:37 2019]  ? __call_srcu+0x264/0x3b0
+[Thu Oct 17 16:43:37 2019]  ? process_termination_cpsch+0x24/0x2f0
+[amdgpu]
+[Thu Oct 17 16:43:37 2019]  process_termination_cpsch+0x24/0x2f0
+[amdgpu]
+[Thu Oct 17 16:43:37 2019]
+kfd_process_dequeue_from_all_devices+0x42/0x60 [amdgpu]
+[Thu Oct 17 16:43:37 2019]  kfd_process_notifier_release+0x1be/0x220
+[amdgpu]
+[Thu Oct 17 16:43:37 2019]  __mmu_notifier_release+0x3e/0xc0
+[Thu Oct 17 16:43:37 2019]  exit_mmap+0x160/0x1a0
+[Thu Oct 17 16:43:37 2019]  ? __handle_mm_fault+0xba3/0x1200
+[Thu Oct 17 16:43:37 2019]  ? exit_robust_list+0x5a/0x110
+[Thu Oct 17 16:43:37 2019]  mmput+0x4a/0x120
+[Thu Oct 17 16:43:37 2019]  do_exit+0x284/0xb20
+[Thu Oct 17 16:43:37 2019]  ? handle_mm_fault+0xfa/0x200
+[Thu Oct 17 16:43:37 2019]  do_group_exit+0x3a/0xa0
+[Thu Oct 17 16:43:37 2019]  __x64_sys_exit_group+0x14/0x20
+[Thu Oct 17 16:43:37 2019]  do_syscall_64+0x4f/0x100
+[Thu Oct 17 16:43:37 2019]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
+
+Change-Id: Iecaa52a3fa406a8b8f219ae800993f42678ceddd
+Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Philip Yang <Philip.Yang@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c       |  5 --
+ .../drm/amd/amdkfd/kfd_device_queue_manager.c | 47 +++++++++++++++++--
+ .../drm/amd/amdkfd/kfd_device_queue_manager.h |  1 +
+ 3 files changed, 43 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index ee9b9a6968bd..eb5eeba8792d 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -744,9 +744,6 @@ int kgd2kfd_pre_reset(struct kfd_dev *kfd)
+ 		return 0;
+ 	kgd2kfd_suspend(kfd);
+ 
+-	/* hold dqm->lock to prevent further execution*/
+-	dqm_lock(kfd->dqm);
+-
+ 	kfd_signal_reset_event(kfd);
+ 	return 0;
+ }
+@@ -767,8 +764,6 @@ int kgd2kfd_post_reset(struct kfd_dev *kfd)
+ 	if (!kfd->init_complete)
+ 		return 0;
+ 
+-	dqm_unlock(kfd->dqm);
+-
+ 	ret = kfd_resume(kfd);
+ 	if (ret)
+ 		return ret;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 0b63740b4c63..2f0aeb60fe40 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -369,6 +369,10 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm,
+ 	mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
+ 				&q->gart_mqd_addr, &q->properties);
+ 	if (q->properties.is_active) {
++		if (!dqm->sched_running) {
++			WARN_ONCE(1, "Load non-HWS mqd while stopped\n");
++			goto add_queue_to_list;
++		}
+ 
+ 		if (WARN(q->process->mm != current->mm,
+ 					"should only run in user thread"))
+@@ -380,6 +384,7 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm,
+ 			goto out_free_mqd;
+ 	}
+ 
++add_queue_to_list:
+ 	list_add(&q->list, &qpd->queues_list);
+ 	qpd->queue_count++;
+ 	if (q->properties.is_active)
+@@ -487,6 +492,11 @@ static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
+ 
+ 	deallocate_doorbell(qpd, q);
+ 
++	if (!dqm->sched_running) {
++		WARN_ONCE(1, "Destroy non-HWS queue while stopped\n");
++		return 0;
++	}
++
+ 	retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
+ 				KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
+ 				KFD_UNMAP_LATENCY_MS,
+@@ -568,6 +578,12 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q)
+ 		   (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
+ 		    q->properties.type == KFD_QUEUE_TYPE_SDMA ||
+ 		    q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
++
++		if (!dqm->sched_running) {
++			WARN_ONCE(1, "Update non-HWS queue while stopped\n");
++			goto out_unlock;
++		}
++
+ 		retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
+ 				KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
+ 				KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
+@@ -719,6 +735,11 @@ static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
+ 		mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
+ 				q->properties.type)];
+ 		q->properties.is_active = false;
++		dqm->queue_count--;
++
++		if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n"))
++			continue;
++
+ 		retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
+ 				KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
+ 				KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
+@@ -727,7 +748,6 @@ static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
+ 			 * maintain a consistent eviction state
+ 			 */
+ 			ret = retval;
+-		dqm->queue_count--;
+ 		if (q->properties.is_gws) {
+ 			dqm->gws_queue_count--;
+ 			qpd->mapped_gws_queue = false;
+@@ -837,6 +857,11 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
+ 		mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
+ 				q->properties.type)];
+ 		q->properties.is_active = true;
++		dqm->queue_count++;
++
++		if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n"))
++			continue;
++
+ 		retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
+ 				       q->queue, &q->properties, mm);
+ 		if (retval && !ret)
+@@ -844,7 +869,6 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
+ 			 * maintain a consistent eviction state
+ 			 */
+ 			ret = retval;
+-		dqm->queue_count++;
+ 		if (q->properties.is_gws) {
+ 			dqm->gws_queue_count++;
+ 			qpd->mapped_gws_queue = true;
+@@ -1042,7 +1066,8 @@ static int start_nocpsch(struct device_queue_manager *dqm)
+ 	
+ 	if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
+ 		return pm_init(&dqm->packets, dqm);
+-	
++	dqm->sched_running = true;
++
+ 	return 0;
+ }
+ 
+@@ -1050,7 +1075,8 @@ static int stop_nocpsch(struct device_queue_manager *dqm)
+ {
+ 	if (dqm->dev->device_info->asic_family == CHIP_HAWAII)
+ 		pm_uninit(&dqm->packets);
+-	
++	dqm->sched_running = false;
++
+ 	return 0;
+ }
+ 
+@@ -1206,6 +1232,7 @@ static int start_cpsch(struct device_queue_manager *dqm)
+ 	dqm_lock(dqm);
+ 	/* clear hang status when driver try to start the hw scheduler */
+ 	dqm->is_hws_hang = false;
++	dqm->sched_running = true;
+ 	execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
+ 			USE_DEFAULT_GRACE_PERIOD);
+ 	dqm_unlock(dqm);
+@@ -1223,6 +1250,7 @@ static int stop_cpsch(struct device_queue_manager *dqm)
+ 	dqm_lock(dqm);
+ 	unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
+ 					 USE_DEFAULT_GRACE_PERIOD);
++	dqm->sched_running = false;
+ 	dqm_unlock(dqm);
+ 
+ 	kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
+@@ -1413,9 +1441,10 @@ static int map_queues_cpsch(struct device_queue_manager *dqm)
+ {
+ 	int retval;
+ 
++	if (!dqm->sched_running)
++		return 0;
+ 	if (dqm->queue_count <= 0 || dqm->processes_count <= 0)
+ 		return 0;
+-
+ 	if (dqm->active_runlist)
+ 		return 0;
+ 
+@@ -1438,6 +1467,8 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm,
+ {
+ 	int retval = 0;
+ 
++	if (!dqm->sched_running)
++		return 0;
+ 	if (dqm->is_hws_hang)
+ 		return -EIO;
+ 	if (!dqm->active_runlist)
+@@ -2375,6 +2406,12 @@ int dqm_debugfs_hqds(struct seq_file *m, void *data)
+ 	int pipe, queue;
+ 	int r = 0;
+ 
++	if (!dqm->sched_running) {
++		seq_printf(m, " Device is stopped\n");
++
++		return 0;
++	}
++
+         r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->kgd,
+                 KFD_CIK_HIQ_PIPE, KFD_CIK_HIQ_QUEUE, &dump, &n_regs);
+         if (!r) {
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+index 48e3b89e27c3..a5e045206fb7 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+@@ -205,6 +205,7 @@ struct device_queue_manager {
+ 	struct work_struct	hw_exception_work;
+ 	struct kfd_mem_obj	hiq_sdma_mqd;
+ 	uint32_t		wait_times;
++	bool			sched_running;
+ };
+ 
+ void device_queue_manager_init_cik(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4272-drm-amdgpu-refine-reboot-debugfs-operation-in-ras-ca.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4272-drm-amdgpu-refine-reboot-debugfs-operation-in-ras-ca.patch
new file mode 100644
index 00000000..e39a8cd2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4272-drm-amdgpu-refine-reboot-debugfs-operation-in-ras-ca.patch
@@ -0,0 +1,85 @@
+From 9b2167f3c47600d84667fb2ee5676035826d288a Mon Sep 17 00:00:00 2001
+From: Guchun Chen <guchun.chen@amd.com>
+Date: Mon, 21 Oct 2019 16:56:00 +0800
+Subject: [PATCH 4272/4736] drm/amdgpu: refine reboot debugfs operation in ras
+ case (v3)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Ras reboot debugfs node allows user one easy control to avoid
+gpu recovery hang problem and directly reboot system per card
+basis, after ras uncorrectable error happens. However, it is
+one common entry, which should get rid of ras_ctrl node and
+remove ip dependence when inputting by user. So add one new
+auto_reboot node in ras debugfs dir to achieve this.
+
+v2: in commit mssage, add justification why ras reboot debugfs
+node is needed.
+v3: use debugfs_create_bool to create debugfs file for boolean value
+
+Signed-off-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 19 ++++++++++++-------
+ 1 file changed, 12 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 1ca613014126..5b532cd254cc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -151,8 +151,6 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
+ 		op = 1;
+ 	else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
+ 		op = 2;
+-	else if (sscanf(str, "reboot %32s", block_name) == 1)
+-		op = 3;
+ 	else if (str[0] && str[1] && str[2] && str[3])
+ 		/* ascii string, but commands are not matched. */
+ 		return -EINVAL;
+@@ -216,12 +214,11 @@ static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
+  * value to the address.
+  *
+  * Second member: struct ras_debug_if::op.
+- * It has four kinds of operations.
++ * It has three kinds of operations.
+  *
+  * - 0: disable RAS on the block. Take ::head as its data.
+  * - 1: enable RAS on the block. Take ::head as its data.
+  * - 2: inject errors on the block. Take ::inject as its data.
+- * - 3: reboot on unrecoverable error
+  *
+  * How to use the interface?
+  * programs:
+@@ -303,9 +300,6 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *
+ 		/* data.inject.address is offset instead of absolute gpu address */
+ 		ret = amdgpu_ras_error_inject(adev, &data.inject);
+ 		break;
+-	case 3:
+-		amdgpu_ras_get_context(adev)->reboot = true;
+-		break;
+ 	default:
+ 		ret = -EINVAL;
+ 		break;
+@@ -1035,6 +1029,17 @@ static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
+ 				adev, &amdgpu_ras_debugfs_ctrl_ops);
+ 	debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, con->dir,
+ 				adev, &amdgpu_ras_debugfs_eeprom_ops);
++
++	/*
++	 * After one uncorrectable error happens, usually GPU recovery will
++	 * be scheduled. But due to the known problem in GPU recovery failing
++	 * to bring GPU back, below interface provides one direct way to
++	 * user to reboot system automatically in such case within
++	 * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
++	 * will never be called.
++	 */
++	debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, con->dir,
++				&con->reboot);
+ }
+ 
+ void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4273-drm-amdgpu-define-macros-for-retire-page-reservation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4273-drm-amdgpu-define-macros-for-retire-page-reservation.patch
new file mode 100644
index 00000000..13606bac
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4273-drm-amdgpu-define-macros-for-retire-page-reservation.patch
@@ -0,0 +1,69 @@
+From 1634c0392f40aaa2207a17188be18362f9e07e3b Mon Sep 17 00:00:00 2001
+From: Guchun Chen <guchun.chen@amd.com>
+Date: Tue, 22 Oct 2019 11:39:25 +0800
+Subject: [PATCH 4273/4736] drm/amdgpu: define macros for retire page
+ reservation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Easy for maintainance.
+
+Signed-off-by: Guchun Chen <guchun.chen@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 17 +++++++++++------
+ 1 file changed, 11 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 5b532cd254cc..ebc3e15eca8b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -66,6 +66,11 @@ const char *ras_block_string[] = {
+ /* inject address is 52 bits */
+ #define	RAS_UMC_INJECT_ADDR_LIMIT	(0x1ULL << 52)
+ 
++enum amdgpu_ras_retire_page_reservation {
++	AMDGPU_RAS_RETIRE_PAGE_RESERVED,
++	AMDGPU_RAS_RETIRE_PAGE_PENDING,
++	AMDGPU_RAS_RETIRE_PAGE_FAULT,
++};
+ 
+ atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
+ 
+@@ -807,11 +812,11 @@ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
+ static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
+ {
+ 	switch (flags) {
+-	case 0:
++	case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
+ 		return "R";
+-	case 1:
++	case AMDGPU_RAS_RETIRE_PAGE_PENDING:
+ 		return "P";
+-	case 2:
++	case AMDGPU_RAS_RETIRE_PAGE_FAULT:
+ 	default:
+ 		return "F";
+ 	};
+@@ -1292,13 +1297,13 @@ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
+ 		(*bps)[i] = (struct ras_badpage){
+ 			.bp = data->bps[i].retired_page,
+ 			.size = AMDGPU_GPU_PAGE_SIZE,
+-			.flags = 0,
++			.flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
+ 		};
+ 
+ 		if (data->last_reserved <= i)
+-			(*bps)[i].flags = 1;
++			(*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
+ 		else if (data->bps_bo[i] == NULL)
+-			(*bps)[i].flags = 2;
++			(*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
+ 	}
+ 
+ 	*count = data->count;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4274-drm-amdgpu-Fix-SDMA-hang-when-performing-VKexample-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4274-drm-amdgpu-Fix-SDMA-hang-when-performing-VKexample-t.patch
new file mode 100644
index 00000000..579bb56a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4274-drm-amdgpu-Fix-SDMA-hang-when-performing-VKexample-t.patch
@@ -0,0 +1,30 @@
+From 7db3a1e3e1aaa56d8024966c09d2b5480de8703e Mon Sep 17 00:00:00 2001
+From: chen gong <curry.gong@amd.com>
+Date: Wed, 23 Oct 2019 13:54:32 +0800
+Subject: [PATCH 4274/4736] drm/amdgpu: Fix SDMA hang when performing VKexample
+ test
+
+VKexample test hang during Occlusion/SDMA/Varia runs.
+Clear XNACK_WATERMK in reg SDMA0_UTCL1_WATERMK to fix this issue.
+
+Signed-off-by: chen gong <curry.gong@amd.com>
+Reviewed-by: Aaron Liu <aaron.liu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 78e21c12c17a..2653d3c6ddd3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -251,6 +251,7 @@ static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
+ 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+ 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+ 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
++	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
+ };
+ 
+ static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4275-drm-amdgpu-sdma5-do-not-execute-0-sized-IBs-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4275-drm-amdgpu-sdma5-do-not-execute-0-sized-IBs-v2.patch
new file mode 100644
index 00000000..dcff327b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4275-drm-amdgpu-sdma5-do-not-execute-0-sized-IBs-v2.patch
@@ -0,0 +1,34 @@
+From 99c7a912113644a9ab79ca59b5964473930f962d Mon Sep 17 00:00:00 2001
+From: "Pelloux-prayer, Pierre-eric" <Pierre-eric.Pelloux-prayer@amd.com>
+Date: Tue, 22 Oct 2019 19:22:11 +0200
+Subject: [PATCH 4275/4736] drm/amdgpu/sdma5: do not execute 0-sized IBs (v2)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This seems to help with https://bugs.freedesktop.org/show_bug.cgi?id=111481.
+
+v2: insert a NOP instead of skipping all 0-sized IBs to avoid breaking older hw
+
+Change-Id: I5df87b3e4eb920c645307425f7b72c430704939a
+Signed-off-by: Pelloux-prayer, Pierre-eric <Pierre-eric.Pelloux-prayer@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index 6a73e8d95f0a..3b00bce14cfb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -309,6 +309,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
+ 
+ 	job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
+ 	job->vm_needs_flush = true;
++	job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
+ 	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
+ 	r = amdgpu_job_submit(job, &adev->mman.entity,
+ 			      AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4276-drm-amdgpu-remove-unused-parameter-in-amdgpu_gfx_kiq.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4276-drm-amdgpu-remove-unused-parameter-in-amdgpu_gfx_kiq.patch
new file mode 100644
index 00000000..68656313
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4276-drm-amdgpu-remove-unused-parameter-in-amdgpu_gfx_kiq.patch
@@ -0,0 +1,89 @@
+From a74bcb4a1196e59afac59177e6d7982307c552dc Mon Sep 17 00:00:00 2001
+From: Nirmoy Das <nirmoy.das@amd.com>
+Date: Wed, 23 Oct 2019 16:33:52 +0200
+Subject: [PATCH 4276/4736] drm/amdgpu: remove unused parameter in
+ amdgpu_gfx_kiq_free_ring
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 3 +--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 3 +--
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 2 +-
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   | 2 +-
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 2 +-
+ 5 files changed, 5 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+index 56b31668d551..a492174ef29b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+@@ -319,8 +319,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
+ 	return r;
+ }
+ 
+-void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
+-			      struct amdgpu_irq_src *irq)
++void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
+ {
+ 	amdgpu_device_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
+ 	amdgpu_ring_fini(ring);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+index 35eff9e6ce16..459aa9059542 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+@@ -330,8 +330,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
+ 			     struct amdgpu_ring *ring,
+ 			     struct amdgpu_irq_src *irq);
+ 
+-void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
+-			      struct amdgpu_irq_src *irq);
++void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring);
+ 
+ void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
+ int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index f93ac8f44a58..38dd30d350a3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1439,7 +1439,7 @@ static int gfx_v10_0_sw_fini(void *handle)
+ 		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
+ 
+ 	amdgpu_gfx_mqd_sw_fini(adev);
+-	amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
++	amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
+ 	amdgpu_gfx_kiq_fini(adev);
+ 
+ 	gfx_v10_0_pfp_fini(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index 614b8226b9eb..c0bcf5d91f1f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -2099,7 +2099,7 @@ static int gfx_v8_0_sw_fini(void *handle)
+ 		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
+ 
+ 	amdgpu_gfx_mqd_sw_fini(adev);
+-	amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
++	amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
+ 	amdgpu_gfx_kiq_fini(adev);
+ 
+ 	gfx_v8_0_mec_fini(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 5e7a01c322ea..2f03bf533d41 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -2149,7 +2149,7 @@ static int gfx_v9_0_sw_fini(void *handle)
+ 		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
+ 
+ 	amdgpu_gfx_mqd_sw_fini(adev);
+-	amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
++	amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
+ 	amdgpu_gfx_kiq_fini(adev);
+ 
+ 	gfx_v9_0_mec_fini(adev);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4277-drm-amdgpu-Add-DC-feature-mask-to-disable-fractional.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4277-drm-amdgpu-Add-DC-feature-mask-to-disable-fractional.patch
new file mode 100644
index 00000000..b4d6c74c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4277-drm-amdgpu-Add-DC-feature-mask-to-disable-fractional.patch
@@ -0,0 +1,79 @@
+From e6636a3d42b3291d037aa242bbe59cd040ea5caf Mon Sep 17 00:00:00 2001
+From: Leo Li <sunpeng.li@amd.com>
+Date: Mon, 21 Oct 2019 14:58:47 -0400
+Subject: [PATCH 4277/4736] drm/amdgpu: Add DC feature mask to disable
+ fractional pwm
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+[Why]
+
+Some LED panel drivers might not like fractional PWM. In such cases,
+backlight flickering may be observed.
+
+[How]
+
+Add a DC feature mask to disable fractional PWM, and associate it with
+the preexisting dc_config flag.
+
+The flag is only plumbed through the dmcu firmware, so plumb it through
+the driver path as well.
+
+To disable, add the following to the linux cmdline:
+amdgpu.dcfeaturemask=0x4
+
+Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204957
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+Reviewed-by: Anthony Koo <anthony.koo@amd.com>
+Tested-by: Lukáš Krej�í <lskrejci@gmail.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
+ drivers/gpu/drm/amd/display/dc/dce/dce_abm.c      | 4 ++++
+ drivers/gpu/drm/amd/include/amd_shared.h          | 1 +
+ 3 files changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index ff89ca40f82c..5a20ce0541c6 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -725,6 +725,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ 	if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
+ 		init_data.flags.multi_mon_pp_mclk_switch = true;
+ 
++	if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
++		init_data.flags.disable_fractional_pwm = true;
++
+ 	init_data.flags.power_down_display_on_boot = true;
+ 
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+index 4a22b50bd38a..2946998fe6a4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+@@ -402,6 +402,10 @@ static bool dce_abm_init_backlight(struct abm *abm)
+ 	/* Enable the backlight output */
+ 	REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);
+ 
++	/* Disable fractional pwm if configured */
++	REG_UPDATE(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN,
++		   abm->ctx->dc->config.disable_fractional_pwm ? 0 : 1);
++
+ 	/* Unlock group 2 backlight registers */
+ 	REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
+ 			BL_PWM_GRP1_REG_LOCK, 0);
+diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
+index 8340ec0ab792..dc7eb28f0296 100644
+--- a/drivers/gpu/drm/amd/include/amd_shared.h
++++ b/drivers/gpu/drm/amd/include/amd_shared.h
+@@ -143,6 +143,7 @@ enum PP_FEATURE_MASK {
+ enum DC_FEATURE_MASK {
+ 	DC_FBC_MASK = 0x1,
+ 	DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,
++	DC_DISABLE_FRACTIONAL_PWM_MASK = 0x4,
+ 	DC_PSR_MASK = 0x8,
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4278-drm-amd-powerplay-Add-interface-for-I2C-transactions.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4278-drm-amd-powerplay-Add-interface-for-I2C-transactions.patch
new file mode 100644
index 00000000..ba17c20f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4278-drm-amd-powerplay-Add-interface-for-I2C-transactions.patch
@@ -0,0 +1,53 @@
+From e1a4c575f55bd3eccc3d1a079b47fe553008e0fd Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Fri, 11 Oct 2019 13:48:24 -0400
+Subject: [PATCH 4278/4736] drm/amd/powerplay: Add interface for I2C
+ transactions to SMU.
+
+Will be used by Arcturus support for RAS page retirement.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 402a021f237b..8120e7587585 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -393,6 +393,8 @@ struct smu_context
+ 
+ };
+ 
++struct i2c_adapter;
++
+ struct pptable_funcs {
+ 	int (*alloc_dpm_context)(struct smu_context *smu);
+ 	int (*store_powerplay_table)(struct smu_context *smu);
+@@ -469,6 +471,8 @@ struct pptable_funcs {
+ 				   uint32_t dpm_level, uint32_t *freq);
+ 	int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
+ 	int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
++	int (*i2c_eeprom_init)(struct i2c_adapter *control);
++	void (*i2c_eeprom_fini)(struct i2c_adapter *control);
+ 	int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
+ 	int (*init_microcode)(struct smu_context *smu);
+ 	int (*load_microcode)(struct smu_context *smu);
+@@ -552,6 +556,11 @@ int smu_check_fw_status(struct smu_context *smu);
+ 
+ int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
+ 
++#define smu_i2c_eeprom_init(smu, control) \
++		((smu)->ppt_funcs->i2c_eeprom_init ? (smu)->ppt_funcs->i2c_eeprom_init((control)) : -EINVAL)
++#define smu_i2c_eeprom_fini(smu, control) \
++		((smu)->ppt_funcs->i2c_eeprom_fini ? (smu)->ppt_funcs->i2c_eeprom_fini((control)) : -EINVAL)
++
+ int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);
+ 
+ int smu_get_power_limit(struct smu_context *smu,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4279-drm-amd-powerplay-Add-EEPROM-I2C-read-write-support-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4279-drm-amd-powerplay-Add-EEPROM-I2C-read-write-support-.patch
new file mode 100644
index 00000000..44cb5bf3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4279-drm-amd-powerplay-Add-EEPROM-I2C-read-write-support-.patch
@@ -0,0 +1,288 @@
+From 83aaefe84218f05585228130616871b50c75aabf Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Tue, 8 Oct 2019 16:27:47 -0400
+Subject: [PATCH 4279/4736] drm/amd/powerplay: Add EEPROM I2C read/write
+ support to Arcturus.
+
+The communication is done through SMU table and hence the code
+is in powerplay.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 229 +++++++++++++++++++
+ 1 file changed, 229 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index ffefa89c295b..fa573c59e813 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -37,6 +37,11 @@
+ #include "smu_v11_0_pptable.h"
+ #include "arcturus_ppsmc.h"
+ #include "nbio/nbio_7_4_sh_mask.h"
++#include <linux/i2c.h>
++#include <linux/pci.h>
++#include "amdgpu_ras.h"
++
++#define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control.eeprom_accessor))->adev
+ 
+ #define CTF_OFFSET_EDGE			5
+ #define CTF_OFFSET_HOTSPOT		5
+@@ -172,6 +177,7 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
+ 	TAB_MAP(SMU_METRICS),
+ 	TAB_MAP(DRIVER_SMU_CONFIG),
+ 	TAB_MAP(OVERDRIVE),
++	TAB_MAP(I2C_COMMANDS),
+ };
+ 
+ static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
+@@ -294,6 +300,9 @@ static int arcturus_tables_init(struct smu_context *smu, struct smu_table *table
+ 	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
+ 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ 
++	SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
++			       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
++
+ 	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
+ 	if (!smu_table->metrics_table)
+ 		return -ENOMEM;
+@@ -1925,6 +1934,224 @@ static int arcturus_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
+ 	return ret;
+ }
+ 
++
++static void arcturus_fill_eeprom_i2c_req(SwI2cRequest_t  *req, bool write,
++				  uint8_t address, uint32_t numbytes,
++				  uint8_t *data)
++{
++	int i;
++
++	BUG_ON(numbytes > MAX_SW_I2C_COMMANDS);
++
++	req->I2CcontrollerPort = 0;
++	req->I2CSpeed = 2;
++	req->SlaveAddress = address;
++	req->NumCmds = numbytes;
++
++	for (i = 0; i < numbytes; i++) {
++		SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
++
++		/* First 2 bytes are always write for lower 2b EEPROM address */
++		if (i < 2)
++			cmd->Cmd = 1;
++		else
++			cmd->Cmd = write;
++
++
++		/* Add RESTART for read  after address filled */
++		cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
++
++		/* Add STOP in the end */
++		cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
++
++		/* Fill with data regardless if read or write to simplify code */
++		cmd->RegisterAddr = data[i];
++	}
++}
++
++static int arcturus_i2c_eeprom_read_data(struct i2c_adapter *control,
++					       uint8_t address,
++					       uint8_t *data,
++					       uint32_t numbytes)
++{
++	uint32_t  i, ret = 0;
++	SwI2cRequest_t req;
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++	struct smu_table_context *smu_table = &adev->smu.smu_table;
++	struct smu_table *table = &smu_table->tables[SMU_TABLE_I2C_COMMANDS];
++
++	memset(&req, 0, sizeof(req));
++	arcturus_fill_eeprom_i2c_req(&req, false, address, numbytes, data);
++
++	mutex_lock(&adev->smu.mutex);
++	/* Now read data starting with that address */
++	ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
++					true);
++	mutex_unlock(&adev->smu.mutex);
++
++	if (!ret) {
++		SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
++
++		/* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
++		for (i = 0; i < numbytes; i++)
++			data[i] = res->SwI2cCmds[i].Data;
++
++		pr_debug("arcturus_i2c_eeprom_read_data, address = %x, bytes = %d, data :",
++				  (uint16_t)address, numbytes);
++
++		print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
++			       8, 1, data, numbytes, false);
++	} else
++		pr_err("arcturus_i2c_eeprom_read_data - error occurred :%x", ret);
++
++	return ret;
++}
++
++static int arcturus_i2c_eeprom_write_data(struct i2c_adapter *control,
++						uint8_t address,
++						uint8_t *data,
++						uint32_t numbytes)
++{
++	uint32_t ret;
++	SwI2cRequest_t req;
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++
++	memset(&req, 0, sizeof(req));
++	arcturus_fill_eeprom_i2c_req(&req, true, address, numbytes, data);
++
++	mutex_lock(&adev->smu.mutex);
++	ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
++	mutex_unlock(&adev->smu.mutex);
++
++	if (!ret) {
++		pr_debug("arcturus_i2c_write(), address = %x, bytes = %d , data: ",
++					 (uint16_t)address, numbytes);
++
++		print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
++			       8, 1, data, numbytes, false);
++		/*
++		 * According to EEPROM spec there is a MAX of 10 ms required for
++		 * EEPROM to flush internal RX buffer after STOP was issued at the
++		 * end of write transaction. During this time the EEPROM will not be
++		 * responsive to any more commands - so wait a bit more.
++		 */
++		msleep(10);
++
++	} else
++		pr_err("arcturus_i2c_write- error occurred :%x", ret);
++
++	return ret;
++}
++
++static int arcturus_i2c_eeprom_i2c_xfer(struct i2c_adapter *i2c_adap,
++			      struct i2c_msg *msgs, int num)
++{
++	uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
++	uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
++
++	for (i = 0; i < num; i++) {
++		/*
++		 * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
++		 * once and hence the data needs to be spliced into chunks and sent each
++		 * chunk separately
++		 */
++		data_size = msgs[i].len - 2;
++		data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
++		next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
++		data_ptr = msgs[i].buf + 2;
++
++		for (j = 0; j < data_size / data_chunk_size; j++) {
++			/* Insert the EEPROM dest addess, bits 0-15 */
++			data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
++			data_chunk[1] = (next_eeprom_addr & 0xff);
++
++			if (msgs[i].flags & I2C_M_RD) {
++				ret = arcturus_i2c_eeprom_read_data(i2c_adap,
++								(uint8_t)msgs[i].addr,
++								data_chunk, MAX_SW_I2C_COMMANDS);
++
++				memcpy(data_ptr, data_chunk + 2, data_chunk_size);
++			} else {
++
++				memcpy(data_chunk + 2, data_ptr, data_chunk_size);
++
++				ret = arcturus_i2c_eeprom_write_data(i2c_adap,
++								 (uint8_t)msgs[i].addr,
++								 data_chunk, MAX_SW_I2C_COMMANDS);
++			}
++
++			if (ret) {
++				num = -EIO;
++				goto fail;
++			}
++
++			next_eeprom_addr += data_chunk_size;
++			data_ptr += data_chunk_size;
++		}
++
++		if (data_size % data_chunk_size) {
++			data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
++			data_chunk[1] = (next_eeprom_addr & 0xff);
++
++			if (msgs[i].flags & I2C_M_RD) {
++				ret = arcturus_i2c_eeprom_read_data(i2c_adap,
++								(uint8_t)msgs[i].addr,
++								data_chunk, (data_size % data_chunk_size) + 2);
++
++				memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
++			} else {
++				memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
++
++				ret = arcturus_i2c_eeprom_write_data(i2c_adap,
++								 (uint8_t)msgs[i].addr,
++								 data_chunk, (data_size % data_chunk_size) + 2);
++			}
++
++			if (ret) {
++				num = -EIO;
++				goto fail;
++			}
++		}
++	}
++
++fail:
++	return num;
++}
++
++static u32 arcturus_i2c_eeprom_i2c_func(struct i2c_adapter *adap)
++{
++	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
++}
++
++
++static const struct i2c_algorithm arcturus_i2c_eeprom_i2c_algo = {
++	.master_xfer = arcturus_i2c_eeprom_i2c_xfer,
++	.functionality = arcturus_i2c_eeprom_i2c_func,
++};
++
++int arcturus_i2c_eeprom_control_init(struct i2c_adapter *control)
++{
++	struct amdgpu_device *adev = to_amdgpu_device(control);
++	int res;
++
++	control->owner = THIS_MODULE;
++	control->class = I2C_CLASS_SPD;
++	control->dev.parent = &adev->pdev->dev;
++	control->algo = &arcturus_i2c_eeprom_i2c_algo;
++	snprintf(control->name, sizeof(control->name), "RAS EEPROM");
++
++	res = i2c_add_adapter(control);
++	if (res)
++		DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
++
++	return res;
++}
++
++void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
++{
++	i2c_del_adapter(control);
++}
++
+ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 	/* translate smu index into arcturus specific index */
+ 	.get_smu_msg_index = arcturus_get_smu_msg_index,
+@@ -1964,6 +2191,8 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 	.get_power_limit = arcturus_get_power_limit,
+ 	.is_dpm_running = arcturus_is_dpm_running,
+ 	.dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
++	.i2c_eeprom_init = arcturus_i2c_eeprom_control_init,
++	.i2c_eeprom_fini = arcturus_i2c_eeprom_control_fini,
+ 	.init_microcode = smu_v11_0_init_microcode,
+ 	.load_microcode = smu_v11_0_load_microcode,
+ 	.init_smc_tables = smu_v11_0_init_smc_tables,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4280-drm-amdgpu-Use-ARCTURUS-in-RAS-EEPROM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4280-drm-amdgpu-Use-ARCTURUS-in-RAS-EEPROM.patch
new file mode 100644
index 00000000..7ba171fa
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4280-drm-amdgpu-Use-ARCTURUS-in-RAS-EEPROM.patch
@@ -0,0 +1,52 @@
+From 31aed3aa3a2b5a604e6282f5c1dadf1e6e56f8b9 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Fri, 11 Oct 2019 15:28:19 -0400
+Subject: [PATCH 4280/4736] drm/amdgpu: Use ARCTURUS in RAS EEPROM.
+
+Add Arcturus EEPROM/I2C support in generic EEPROM code.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+acked-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+index 20af0a17d00b..7de16c0c2f20 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+@@ -216,6 +216,10 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
+ 		ret = smu_v11_0_i2c_eeprom_control_init(&control->eeprom_accessor);
+ 		break;
+ 
++	case CHIP_ARCTURUS:
++		ret = smu_i2c_eeprom_init(&adev->smu, &control->eeprom_accessor);
++		break;
++
+ 	default:
+ 		return 0;
+ 	}
+@@ -260,6 +264,9 @@ void amdgpu_ras_eeprom_fini(struct amdgpu_ras_eeprom_control *control)
+ 	case CHIP_VEGA20:
+ 		smu_v11_0_i2c_eeprom_control_fini(&control->eeprom_accessor);
+ 		break;
++	case CHIP_ARCTURUS:
++		smu_i2c_eeprom_fini(&adev->smu, &control->eeprom_accessor);
++		break;
+ 
+ 	default:
+ 		return;
+@@ -364,7 +371,7 @@ int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
+ 	struct eeprom_table_record *record;
+ 	struct amdgpu_device *adev = to_amdgpu_device(control);
+ 
+-	if (adev->asic_type != CHIP_VEGA20)
++	if (adev->asic_type != CHIP_VEGA20 && adev->asic_type != CHIP_ARCTURUS)
+ 		return 0;
+ 
+ 	buffs = kcalloc(num, EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4281-drm-amdgpu-Move-amdgpu_ras_recovery_init-to-after-SM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4281-drm-amdgpu-Move-amdgpu_ras_recovery_init-to-after-SM.patch
new file mode 100644
index 00000000..7299f949
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4281-drm-amdgpu-Move-amdgpu_ras_recovery_init-to-after-SM.patch
@@ -0,0 +1,68 @@
+From 4247199656c3a7e8b1bed2c1318166bd60636da5 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Fri, 18 Oct 2019 16:15:04 -0400
+Subject: [PATCH 4281/4736] drm/amdgpu: Move amdgpu_ras_recovery_init to after
+ SMU ready.
+
+For Arcturus the I2C traffic is done through SMU tables and so
+we must postpone RAS recovery init to after they are ready
+which is in amdgpu_device_ip_hw_init_phase2.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13 +++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    | 11 -----------
+ 2 files changed, 13 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 634b581f96b8..e30e4f8f7df3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1877,6 +1877,19 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
+ 	if (r)
+ 		goto init_failed;
+ 
++	/*
++	 * retired pages will be loaded from eeprom and reserved here,
++	 * it should be called after amdgpu_device_ip_hw_init_phase2  since
++	 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
++	 * for I2C communication which only true at this point.
++	 * recovery_init may fail, but it can free all resources allocated by
++	 * itself and its failure should not stop amdgpu init process.
++	 *
++	 * Note: theoretically, this should be called before all vram allocations
++	 * to protect retired page from abusing
++	 */
++	amdgpu_ras_recovery_init(adev);
++
+ 	if (adev->gmc.xgmi.num_physical_nodes > 1)
+ 		amdgpu_xgmi_add_device(adev);
+ 	amdgpu_amdkfd_device_init(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 968595138b32..8bdc1eec496e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -2115,17 +2115,6 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
+ 						adev->gmc.visible_vram_size);
+ #endif
+ 
+-	/*
+-	 * retired pages will be loaded from eeprom and reserved here,
+-	 * it should be called after ttm init since new bo may be created,
+-	 * recovery_init may fail, but it can free all resources allocated by
+-	 * itself and its failure should not stop amdgpu init process.
+-	 *
+-	 * Note: theoretically, this should be called before all vram allocations
+-	 * to protect retired page from abusing
+-	 */
+-	amdgpu_ras_recovery_init(adev);
+-
+ 	/*
+ 	 *The reserved vram for firmware must be pinned to the specified
+ 	 *place on the VRAM, so reserve it early.
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4282-drm-amdgpu-Allow-reading-more-status-registers-on-si.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4282-drm-amdgpu-Allow-reading-more-status-registers-on-si.patch
new file mode 100644
index 00000000..2b8e4371
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4282-drm-amdgpu-Allow-reading-more-status-registers-on-si.patch
@@ -0,0 +1,119 @@
+From dc7226855bf797ba95a3b5c90bfc06a68b2af5c9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
+Date: Thu, 12 Dec 2019 10:34:08 +0530
+Subject: [PATCH 4282/4736] drm/amdgpu: Allow reading more status registers on
+ si/cik
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Allow userspace to read the same status registers for every family.
+Based on commit c7890fea, added any of these registers if defined in
+the include files of each architecture.
+
+Signed-off-by: Marek Olšák <marek.olsak@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  3 ++-
+ drivers/gpu/drm/amd/amdgpu/cik.c        | 19 +++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/nv.c         |  1 +
+ drivers/gpu/drm/amd/amdgpu/si.c         | 11 +++++++++++
+ drivers/gpu/drm/amd/amdgpu/soc15.c      |  1 +
+ 5 files changed, 34 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 699cab407158..131dd2e91bf0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -81,9 +81,10 @@
+  * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
+  * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
+  * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
++ * - 3.36.0 - Allow reading more status registers on si/cik
+  */
+ #define KMS_DRIVER_MAJOR	3
+-#define KMS_DRIVER_MINOR	35
++#define KMS_DRIVER_MINOR	36
+ #define KMS_DRIVER_PATCHLEVEL	0
+ 
+ int amdgpu_vram_limit = 0;
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
+index e3c524c8926a..cc3d9f91a769 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik.c
+@@ -965,6 +965,25 @@ static bool cik_read_bios_from_rom(struct amdgpu_device *adev,
+ 
+ static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {
+ 	{mmGRBM_STATUS},
++	{mmGRBM_STATUS2},
++	{mmGRBM_STATUS_SE0},
++	{mmGRBM_STATUS_SE1},
++	{mmGRBM_STATUS_SE2},
++	{mmGRBM_STATUS_SE3},
++	{mmSRBM_STATUS},
++	{mmSRBM_STATUS2},
++	{mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
++	{mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
++	{mmCP_STAT},
++	{mmCP_STALLED_STAT1},
++	{mmCP_STALLED_STAT2},
++	{mmCP_STALLED_STAT3},
++	{mmCP_CPF_BUSY_STAT},
++	{mmCP_CPF_STALLED_STAT1},
++	{mmCP_CPF_STATUS},
++	{mmCP_CPC_BUSY_STAT},
++	{mmCP_CPC_STALLED_STAT1},
++	{mmCP_CPC_STATUS},
+ 	{mmGB_ADDR_CONFIG},
+ 	{mmMC_ARB_RAMCFG},
+ 	{mmGB_TILE_MODE0},
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 55a6ed09a953..ebbf7712f8c8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -177,6 +177,7 @@ static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
+ 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
+ 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
+ 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
++	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
+ 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
+ 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
+ 	{ SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
+diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
+index 0d2533025227..c8d645e45821 100644
+--- a/drivers/gpu/drm/amd/amdgpu/si.c
++++ b/drivers/gpu/drm/amd/amdgpu/si.c
+@@ -974,6 +974,17 @@ static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+ 
+ static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
+ 	{GRBM_STATUS},
++	{mmGRBM_STATUS2},
++	{mmGRBM_STATUS_SE0},
++	{mmGRBM_STATUS_SE1},
++	{mmSRBM_STATUS},
++	{mmSRBM_STATUS2},
++	{DMA_STATUS_REG + DMA0_REGISTER_OFFSET},
++	{DMA_STATUS_REG + DMA1_REGISTER_OFFSET},
++	{mmCP_STAT},
++	{mmCP_STALLED_STAT1},
++	{mmCP_STALLED_STAT2},
++	{mmCP_STALLED_STAT3},
+ 	{GB_ADDR_CONFIG},
+ 	{MC_ARB_RAMCFG},
+ 	{GB_TILE_MODE0},
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 9457502a9909..d3083bd2c5ae 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -338,6 +338,7 @@ static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
+ 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
+ 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
+ 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
++	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
+ 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
+ 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
+ 	{ SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4283-drm-amd-powerplay-skip-unsupported-clock-limit-setti.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4283-drm-amd-powerplay-skip-unsupported-clock-limit-setti.patch
new file mode 100644
index 00000000..09178d48
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4283-drm-amd-powerplay-skip-unsupported-clock-limit-setti.patch
@@ -0,0 +1,258 @@
+From ea8e41069738393f33d662295b030aebb795cd94 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 22 Oct 2019 21:20:36 +0800
+Subject: [PATCH 4283/4736] drm/amd/powerplay: skip unsupported clock limit
+ settings on Arcturus V2
+
+For Arcturus, clock limit settings on uclk/socclk/fclk domains
+are not supported.
+
+V2: simplify the code to support both SGPU and MGPU cases
+
+Change-Id: I1286289e3770f0421f0d22989437e26d3f7b2ec4
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c       |  13 ++
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 142 ++++---------------
+ 2 files changed, 39 insertions(+), 116 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index dd94467a3d5d..07f620938ae4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -2828,6 +2828,19 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
+ 		DRM_ERROR("failed to create device file pp_dpm_sclk\n");
+ 		return ret;
+ 	}
++
++	/* Arcturus does not support standalone mclk/socclk/fclk level setting */
++	if (adev->asic_type == CHIP_ARCTURUS) {
++		dev_attr_pp_dpm_mclk.attr.mode &= ~S_IWUGO;
++		dev_attr_pp_dpm_mclk.store = NULL;
++
++		dev_attr_pp_dpm_socclk.attr.mode &= ~S_IWUGO;
++		dev_attr_pp_dpm_socclk.store = NULL;
++
++		dev_attr_pp_dpm_fclk.attr.mode &= ~S_IWUGO;
++		dev_attr_pp_dpm_fclk.store = NULL;
++	}
++
+ 	ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
+ 	if (ret) {
+ 		DRM_ERROR("failed to create device file pp_dpm_mclk\n");
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index fa573c59e813..48f3ddc065c0 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -37,6 +37,7 @@
+ #include "smu_v11_0_pptable.h"
+ #include "arcturus_ppsmc.h"
+ #include "nbio/nbio_7_4_sh_mask.h"
++#include "amdgpu_xgmi.h"
+ #include <linux/i2c.h>
+ #include <linux/pci.h>
+ #include "amdgpu_ras.h"
+@@ -807,84 +808,13 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
+ 		break;
+ 
+ 	case SMU_MCLK:
+-		single_dpm_table = &(dpm_table->mem_table);
+-
+-		if (soft_max_level >= single_dpm_table->count) {
+-			pr_err("Clock level specified %d is over max allowed %d\n",
+-					soft_max_level, single_dpm_table->count - 1);
+-			ret = -EINVAL;
+-			break;
+-		}
+-
+-		single_dpm_table->dpm_state.soft_min_level =
+-			single_dpm_table->dpm_levels[soft_min_level].value;
+-		single_dpm_table->dpm_state.soft_max_level =
+-			single_dpm_table->dpm_levels[soft_max_level].value;
+-
+-		ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
+-		if (ret) {
+-			pr_err("Failed to upload boot level to lowest!\n");
+-			break;
+-		}
+-
+-		ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
+-		if (ret)
+-			pr_err("Failed to upload dpm max level to highest!\n");
+-
+-		break;
+-
+ 	case SMU_SOCCLK:
+-		single_dpm_table = &(dpm_table->soc_table);
+-
+-		if (soft_max_level >= single_dpm_table->count) {
+-			pr_err("Clock level specified %d is over max allowed %d\n",
+-					soft_max_level, single_dpm_table->count - 1);
+-			ret = -EINVAL;
+-			break;
+-		}
+-
+-		single_dpm_table->dpm_state.soft_min_level =
+-			single_dpm_table->dpm_levels[soft_min_level].value;
+-		single_dpm_table->dpm_state.soft_max_level =
+-			single_dpm_table->dpm_levels[soft_max_level].value;
+-
+-		ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
+-		if (ret) {
+-			pr_err("Failed to upload boot level to lowest!\n");
+-			break;
+-		}
+-
+-		ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
+-		if (ret)
+-			pr_err("Failed to upload dpm max level to highest!\n");
+-
+-		break;
+-
+ 	case SMU_FCLK:
+-		single_dpm_table = &(dpm_table->fclk_table);
+-
+-		if (soft_max_level >= single_dpm_table->count) {
+-			pr_err("Clock level specified %d is over max allowed %d\n",
+-					soft_max_level, single_dpm_table->count - 1);
+-			ret = -EINVAL;
+-			break;
+-		}
+-
+-		single_dpm_table->dpm_state.soft_min_level =
+-			single_dpm_table->dpm_levels[soft_min_level].value;
+-		single_dpm_table->dpm_state.soft_max_level =
+-			single_dpm_table->dpm_levels[soft_max_level].value;
+-
+-		ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
+-		if (ret) {
+-			pr_err("Failed to upload boot level to lowest!\n");
+-			break;
+-		}
+-
+-		ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
+-		if (ret)
+-			pr_err("Failed to upload dpm max level to highest!\n");
+-
++		/*
++		 * Should not arrive here since Arcturus does not
++		 * support mclk/socclk/fclk softmin/softmax settings
++		 */
++		ret = -EINVAL;
+ 		break;
+ 
+ 	default:
+@@ -1200,6 +1130,7 @@ static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
+ {
+ 	struct arcturus_dpm_table *dpm_table =
+ 		(struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
++	struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
+ 	uint32_t soft_level;
+ 	int ret = 0;
+ 
+@@ -1213,40 +1144,27 @@ static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
+ 		dpm_table->gfx_table.dpm_state.soft_max_level =
+ 		dpm_table->gfx_table.dpm_levels[soft_level].value;
+ 
+-	/* uclk */
+-	if (highest)
+-		soft_level = arcturus_find_highest_dpm_level(&(dpm_table->mem_table));
+-	else
+-		soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->mem_table));
+-
+-	dpm_table->mem_table.dpm_state.soft_min_level =
+-		dpm_table->mem_table.dpm_state.soft_max_level =
+-		dpm_table->mem_table.dpm_levels[soft_level].value;
+-
+-	/* socclk */
+-	if (highest)
+-		soft_level = arcturus_find_highest_dpm_level(&(dpm_table->soc_table));
+-	else
+-		soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->soc_table));
+-
+-	dpm_table->soc_table.dpm_state.soft_min_level =
+-		dpm_table->soc_table.dpm_state.soft_max_level =
+-		dpm_table->soc_table.dpm_levels[soft_level].value;
+-
+-	ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
++	ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
+ 	if (ret) {
+ 		pr_err("Failed to upload boot level to %s!\n",
+ 				highest ? "highest" : "lowest");
+ 		return ret;
+ 	}
+ 
+-	ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
++	ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
+ 	if (ret) {
+ 		pr_err("Failed to upload dpm max level to %s!\n!",
+ 				highest ? "highest" : "lowest");
+ 		return ret;
+ 	}
+ 
++	if (hive)
++		/*
++		 * Force XGMI Pstate to highest or lowest
++		 * TODO: revise this when xgmi dpm is functional
++		 */
++		ret = smu_v11_0_set_xgmi_pstate(smu, highest ? 1 : 0);
++
+ 	return ret;
+ }
+ 
+@@ -1254,6 +1172,7 @@ static int arcturus_unforce_dpm_levels(struct smu_context *smu)
+ {
+ 	struct arcturus_dpm_table *dpm_table =
+ 		(struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
++	struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
+ 	uint32_t soft_min_level, soft_max_level;
+ 	int ret = 0;
+ 
+@@ -1265,34 +1184,25 @@ static int arcturus_unforce_dpm_levels(struct smu_context *smu)
+ 	dpm_table->gfx_table.dpm_state.soft_max_level =
+ 		dpm_table->gfx_table.dpm_levels[soft_max_level].value;
+ 
+-	/* uclk */
+-	soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->mem_table));
+-	soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->mem_table));
+-	dpm_table->mem_table.dpm_state.soft_min_level =
+-		dpm_table->gfx_table.dpm_levels[soft_min_level].value;
+-	dpm_table->mem_table.dpm_state.soft_max_level =
+-		dpm_table->gfx_table.dpm_levels[soft_max_level].value;
+-
+-	/* socclk */
+-	soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->soc_table));
+-	soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->soc_table));
+-	dpm_table->soc_table.dpm_state.soft_min_level =
+-		dpm_table->soc_table.dpm_levels[soft_min_level].value;
+-	dpm_table->soc_table.dpm_state.soft_max_level =
+-		dpm_table->soc_table.dpm_levels[soft_max_level].value;
+-
+-	ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
++	ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
+ 	if (ret) {
+ 		pr_err("Failed to upload DPM Bootup Levels!");
+ 		return ret;
+ 	}
+ 
+-	ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
++	ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
+ 	if (ret) {
+ 		pr_err("Failed to upload DPM Max Levels!");
+ 		return ret;
+ 	}
+ 
++	if (hive)
++		/*
++		 * Reset XGMI Pstate back to default
++		 * TODO: revise this when xgmi dpm is functional
++		 */
++		ret = smu_v11_0_set_xgmi_pstate(smu, 0);
++
+ 	return ret;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4284-drm-amd-powerplay-correct-current-clock-level-label-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4284-drm-amd-powerplay-correct-current-clock-level-label-.patch
new file mode 100644
index 00000000..9951b6ab
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4284-drm-amd-powerplay-correct-current-clock-level-label-.patch
@@ -0,0 +1,82 @@
+From e8b3dcadd4f4ad12369d5e4699d028504609c2e0 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 24 Oct 2019 10:01:19 +0800
+Subject: [PATCH 4284/4736] drm/amd/powerplay: correct current clock level
+ label for Arcturus
+
+For dpm disabled case, it's assumed the only one support clock
+level is always current clock level.
+
+Change-Id: I5cc2b7e82af888dc5e8268597ee761e9e1a26855
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 24 +++++++++++++-------
+ 1 file changed, 16 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 48f3ddc065c0..93633f76989e 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -628,12 +628,17 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
+ 			return ret;
+ 		}
+ 
++		/*
++		 * For DPM disabled case, there will be only one clock level.
++		 * And it's safe to assume that is always the current clock.
++		 */
+ 		for (i = 0; i < clocks.num_levels; i++)
+ 			size += sprintf(buf + size, "%d: %uMhz %s\n", i,
+ 					clocks.data[i].clocks_in_khz / 1000,
+-					arcturus_freqs_in_same_level(
++					(clocks.num_levels == 1) ? "*" :
++					(arcturus_freqs_in_same_level(
+ 					clocks.data[i].clocks_in_khz / 1000,
+-					now / 100) ? "*" : "");
++					now / 100) ? "*" : ""));
+ 		break;
+ 
+ 	case SMU_MCLK:
+@@ -653,9 +658,10 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
+ 		for (i = 0; i < clocks.num_levels; i++)
+ 			size += sprintf(buf + size, "%d: %uMhz %s\n",
+ 				i, clocks.data[i].clocks_in_khz / 1000,
+-				arcturus_freqs_in_same_level(
++				(clocks.num_levels == 1) ? "*" :
++				(arcturus_freqs_in_same_level(
+ 				clocks.data[i].clocks_in_khz / 1000,
+-				now / 100) ? "*" : "");
++				now / 100) ? "*" : ""));
+ 		break;
+ 
+ 	case SMU_SOCCLK:
+@@ -675,9 +681,10 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
+ 		for (i = 0; i < clocks.num_levels; i++)
+ 			size += sprintf(buf + size, "%d: %uMhz %s\n",
+ 				i, clocks.data[i].clocks_in_khz / 1000,
+-				arcturus_freqs_in_same_level(
++				(clocks.num_levels == 1) ? "*" :
++				(arcturus_freqs_in_same_level(
+ 				clocks.data[i].clocks_in_khz / 1000,
+-				now / 100) ? "*" : "");
++				now / 100) ? "*" : ""));
+ 		break;
+ 
+ 	case SMU_FCLK:
+@@ -697,9 +704,10 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
+ 		for (i = 0; i < single_dpm_table->count; i++)
+ 			size += sprintf(buf + size, "%d: %uMhz %s\n",
+ 				i, single_dpm_table->dpm_levels[i].value,
+-				arcturus_freqs_in_same_level(
++				(clocks.num_levels == 1) ? "*" :
++				(arcturus_freqs_in_same_level(
+ 				clocks.data[i].clocks_in_khz / 1000,
+-				now / 100) ? "*" : "");
++				now / 100) ? "*" : ""));
+ 		break;
+ 
+ 	default:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4285-drm-amdgpu-call-amdgpu_vm_prt_fini-before-deleting-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4285-drm-amdgpu-call-amdgpu_vm_prt_fini-before-deleting-t.patch
new file mode 100644
index 00000000..62b17d9b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4285-drm-amdgpu-call-amdgpu_vm_prt_fini-before-deleting-t.patch
@@ -0,0 +1,60 @@
+From 3a6825e8f5dc6c82061e2fc0a4eed682003797e6 Mon Sep 17 00:00:00 2001
+From: "Pelloux-prayer, Pierre-eric" <Pierre-eric.Pelloux-prayer@amd.com>
+Date: Wed, 23 Oct 2019 12:02:45 +0000
+Subject: [PATCH 4285/4736] drm/amdgpu: call amdgpu_vm_prt_fini before deleting
+ the root PD
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+amdgpu_vm_prt_fini uses "vm->root.base.bo" so it must still be valid when
+we call it.
+
+Fixes: b65709a92156 ("drm/amdgpu: reserve the root PD while freeing PASIDs")
+Change-Id: Idd5fef2b9344ab6129a6dcdcce2d0a568ed4dde0
+Signed-off-by: Pelloux-prayer, Pierre-eric <Pierre-eric.Pelloux-prayer@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 19 ++++++++++---------
+ 1 file changed, 10 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index c970824b041d..d0604167cd74 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -2977,6 +2977,16 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+ 		vm->pasid = 0;
+ 	}
+ 
++	list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
++		if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
++			amdgpu_vm_prt_fini(adev, vm);
++			prt_fini_needed = false;
++		}
++
++		list_del(&mapping->list);
++		amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
++	}
++
+ 	amdgpu_vm_free_pts(adev, vm, NULL);
+ 	amdgpu_bo_unreserve(root);
+ 	amdgpu_bo_unref(&root);
+@@ -2996,15 +3006,6 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+ 		list_del(&mapping->list);
+ 		kfree(mapping);
+ 	}
+-	list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
+-		if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
+-			amdgpu_vm_prt_fini(adev, vm);
+-			prt_fini_needed = false;
+-		}
+-
+-		list_del(&mapping->list);
+-		amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
+-	}
+ 
+ 	dma_fence_put(vm->last_update);
+ 	for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4286-drm-amdgpu-gfx10-update-gfx-golden-settings.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4286-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
new file mode 100644
index 00000000..51f1f5f7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4286-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
@@ -0,0 +1,30 @@
+From 750b8d117e88bf57d524ee4b460f63b1836adf01 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Thu, 24 Oct 2019 18:03:17 +0800
+Subject: [PATCH 4286/4736] drm/amdgpu/gfx10: update gfx golden settings
+
+update registers: mmCGTT_SPI_CLK_CTRL
+
+Change-Id: Ic64d532c61adfdeb681903f1133d9b353579ac55
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 38dd30d350a3..aea9e8b9b07a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -89,7 +89,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1[] =
+ {
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
+-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4287-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4287-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
new file mode 100644
index 00000000..f692264d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4287-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
@@ -0,0 +1,31 @@
+From 7a16930d26ded51f6ee263a4f73cfd3e11b0fb8b Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Thu, 24 Oct 2019 18:04:52 +0800
+Subject: [PATCH 4287/4736] drm/amdgpu/gfx10: update gfx golden settings for
+ navi14
+
+update registers: mmCGTT_SPI_CLK_CTRL
+
+Change-Id: Ib2539aae1fb0d001278b7f89c90ad6296f9fb85f
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index aea9e8b9b07a..dd879ebca1c1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -136,7 +136,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
+-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4288-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4288-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
new file mode 100644
index 00000000..82e9e0c9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4288-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
@@ -0,0 +1,31 @@
+From 50f53882430501e436d0499c322d0d5e6f8b3936 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Thu, 24 Oct 2019 18:06:06 +0800
+Subject: [PATCH 4288/4736] drm/amdgpu/gfx10: update gfx golden settings for
+ navi12
+
+update registers: mmCGTT_SPI_CLK_CTRL
+
+Change-Id: I35fb25be1340d8c062e0e5bfff642009a00d52cf
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index dd879ebca1c1..ef1975a5323a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -175,7 +175,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
+-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0xc0000100),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4289-drm-amd-display-setting-the-DIG_MODE-to-the-correct-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4289-drm-amd-display-setting-the-DIG_MODE-to-the-correct-.patch
new file mode 100644
index 00000000..71178efc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4289-drm-amd-display-setting-the-DIG_MODE-to-the-correct-.patch
@@ -0,0 +1,43 @@
+From 2d6507e7f7463cc3f1b7736dac45a3a4057a929e Mon Sep 17 00:00:00 2001
+From: Zhan liu <zhan.liu@amd.com>
+Date: Fri, 25 Oct 2019 14:26:23 -0400
+Subject: [PATCH 4289/4736] drm/amd/display: setting the DIG_MODE to the
+ correct value.
+
+[Why]
+This patch is for fixing Navi14 HDMI display pink screen issue.
+
+[How]
+Call stream->link->link_enc->funcs->setup twice. This is setting
+the DIG_MODE to the correct value after having been overridden by
+the call to transmitter control.
+
+Signed-off-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 84813ef735c1..e87124fe981c 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2998,6 +2998,15 @@ void core_link_enable_stream(
+ 				stream->link->link_enc,
+ 				pipe_ctx->stream->signal);
+ 
++		/* This second call is needed to reconfigure the DIG
++		 * as a workaround for the incorrect value being applied
++		 * from transmitter control.
++		 */
++		if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
++			stream->link->link_enc->funcs->setup(
++				stream->link->link_enc,
++				pipe_ctx->stream->signal);
++
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 		if (pipe_ctx->stream->timing.flags.DSC) {
+ 			if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4290-drm-amdgpu-powerplay-modify-the-parameters-of-SMU_MS.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4290-drm-amdgpu-powerplay-modify-the-parameters-of-SMU_MS.patch
new file mode 100644
index 00000000..3a3cf369
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4290-drm-amdgpu-powerplay-modify-the-parameters-of-SMU_MS.patch
@@ -0,0 +1,30 @@
+From 949a3dda57b99b8fb2ca025e74376802543f3e1d Mon Sep 17 00:00:00 2001
+From: chen gong <curry.gong@amd.com>
+Date: Thu, 24 Oct 2019 16:48:40 +0800
+Subject: [PATCH 4290/4736] drm/amdgpu/powerplay: modify the parameters of
+ SMU_MSG_PowerUpVcn to 0
+
+The parameters what SMU_MSG_PowerUpVcn need is 0, not 1
+
+Signed-off-by: chen gong <curry.gong@amd.com>
+Reviewed-by: Aaron Liu <aaron.liu@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 45c5f54e60d8..4a9751971a9d 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -282,7 +282,7 @@ static int renoir_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
+ 	if (enable) {
+ 		/* vcn dpm on is a prerequisite for vcn power gate messages */
+ 		if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
+-			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
++			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0);
+ 			if (ret)
+ 				return ret;
+ 		}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4291-drm-sched-Set-error-to-s_fence-if-HW-job-submission.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4291-drm-sched-Set-error-to-s_fence-if-HW-job-submission.patch
new file mode 100644
index 00000000..92572316
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4291-drm-sched-Set-error-to-s_fence-if-HW-job-submission.patch
@@ -0,0 +1,79 @@
+From a249f6b33e15ee4b699ff10e980ce9de66f7d3e8 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Thu, 12 Dec 2019 13:36:40 +0530
+Subject: [PATCH 4291/4736] drm/sched: Set error to s_fence if HW job
+ submission
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Problem:
+When run_job fails and HW fence returned is NULL we still signal
+the s_fence to avoid hangs but the user has no way of knowing if
+the actual HW job was ran and finished.
+
+Fix:
+Allow .run_job implementations to return ERR_PTR in the fence pointer
+returned and then set this error for s_fence->finished fence so whoever
+wait on this fence can inspect the signaled fence for an error.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/scheduler/sched_main.c | 17 ++++++++++++++---
+ 1 file changed, 14 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c
+index 9f362bb84d48..cef586235eaf 100644
+--- a/drivers/gpu/drm/scheduler/sched_main.c
++++ b/drivers/gpu/drm/scheduler/sched_main.c
+@@ -481,6 +481,7 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler *sched)
+         struct drm_sched_job *s_job, *tmp;
+         uint64_t guilty_context;
+         bool found_guilty = false;
++	struct dma_fence *fence;
+ 
+         list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) {
+                 struct drm_sched_fence *s_fence = s_job->s_fence;
+@@ -494,7 +495,14 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler *sched)
+                         dma_fence_set_error(&s_fence->finished, -ECANCELED);
+ 
+ 		dma_fence_put(s_job->s_fence->parent);
+-                s_job->s_fence->parent = sched->ops->run_job(s_job);
++		fence = sched->ops->run_job(s_job);
++
++		if (IS_ERR_OR_NULL(fence)) {
++			s_job->s_fence->parent = NULL;
++			dma_fence_set_error(&s_fence->finished, PTR_ERR(fence));
++		} else {
++			s_job->s_fence->parent = fence;
++		}
+         }
+ }
+ EXPORT_SYMBOL(drm_sched_resubmit_jobs);
+@@ -722,7 +730,7 @@ static int drm_sched_main(void *param)
+ 		fence = sched->ops->run_job(sched_job);
+ 		drm_sched_fence_scheduled(s_fence);
+ 
+-		if (fence) {
++		if (!IS_ERR_OR_NULL(fence)) {
+ 			s_fence->parent = dma_fence_get(fence);
+ 			r = dma_fence_add_callback(fence, &sched_job->cb,
+ 						   drm_sched_process_job);
+@@ -732,8 +740,11 @@ static int drm_sched_main(void *param)
+ 				DRM_ERROR("fence add callback failed (%d)\n",
+ 					  r);
+ 			dma_fence_put(fence);
+-		} else
++		} else {
++
++			dma_fence_set_error(&s_fence->finished, PTR_ERR(fence));
+ 			drm_sched_process_job(NULL, &sched_job->cb);
++		}
+ 
+ 		wake_up(&sched->job_scheduled);
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4292-drm-amdgpu-If-amdgpu_ib_schedule-fails-return-back-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4292-drm-amdgpu-If-amdgpu_ib_schedule-fails-return-back-t.patch
new file mode 100644
index 00000000..3ef00c6d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4292-drm-amdgpu-If-amdgpu_ib_schedule-fails-return-back-t.patch
@@ -0,0 +1,42 @@
+From 5d97e08483dc2131b8c91b1171edbe40701a6f65 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Thu, 24 Oct 2019 15:44:10 -0400
+Subject: [PATCH 4292/4736] drm/amdgpu: If amdgpu_ib_schedule fails return back
+ the error.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use ERR_PTR to return back the error happened during amdgpu_ib_schedule.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+index c043d8f6bb8b..71fd9bb7ead7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+@@ -218,7 +218,7 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
+ 	struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched);
+ 	struct dma_fence *fence = NULL, *finished;
+ 	struct amdgpu_job *job;
+-	int r;
++	int r = 0;
+ 
+ 	job = to_amdgpu_job(sched_job);
+ 	finished = &job->base.s_fence->finished;
+@@ -243,6 +243,8 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
+ 	job->fence = dma_fence_get(fence);
+ 
+ 	amdgpu_job_free_resources(job);
++
++	fence = r ? ERR_PTR(r) : fence;
+ 	return fence;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4293-drm-amd-display-fix-dcn21-Makefile-for-clang.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4293-drm-amd-display-fix-dcn21-Makefile-for-clang.patch
new file mode 100644
index 00000000..77d796ed
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4293-drm-amd-display-fix-dcn21-Makefile-for-clang.patch
@@ -0,0 +1,47 @@
+From 903e7f10e44dd02e43a9ff9fcd3f98a934adf422 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Wed, 2 Oct 2019 14:01:25 +0200
+Subject: [PATCH 4293/4736] drm/amd/display: fix dcn21 Makefile for clang
+
+Just like all the other variants, this one passes invalid
+compile-time options with clang after the new code got
+merged:
+
+clang: error: unknown argument: '-mpreferred-stack-boundary=4'
+scripts/Makefile.build:265: recipe for target 'drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_resource.o' failed
+
+Use the same variant that we have for dcn20 to fix compilation.
+
+Fixes: eced51f9babb ("drm/amd/display: Add hubp block for Renoir (v2)")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 12 +++++++++++-
+ 1 file changed, 11 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+index b7a9285348fb..4ddd4037c1f8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+@@ -3,7 +3,17 @@
+ 
+ DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o dcn21_link_encoder.o
+ 
+-CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
++ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
++	cc_stack_align := -mpreferred-stack-boundary=4
++else ifneq ($(call cc-option, -mstack-alignment=16),)
++	cc_stack_align := -mstack-alignment=16
++endif
++
++CFLAGS_dcn21_resource.o := -mhard-float -msse $(cc_stack_align)
++
++ifdef CONFIG_CC_IS_CLANG
++CFLAGS_dcn21_resource.o += -msse2
++endif
+ 
+ AMD_DAL_DCN21 = $(addprefix $(AMDDALPATH)/dc/dcn21/,$(DCN21))
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4294-drm-amd-display-remove-gcc-warning-Wunused-but-set-v.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4294-drm-amd-display-remove-gcc-warning-Wunused-but-set-v.patch
new file mode 100644
index 00000000..2c5f9a2b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4294-drm-amd-display-remove-gcc-warning-Wunused-but-set-v.patch
@@ -0,0 +1,56 @@
+From aabeeb1cd6a73dce6930209bfd8db3e27f0013db Mon Sep 17 00:00:00 2001
+From: Chenwandun <chenwandun@huawei.com>
+Date: Sat, 19 Oct 2019 11:23:51 +0800
+Subject: [PATCH 4294/4736] drm/amd/display: remove gcc warning
+ Wunused-but-set-variable
+
+drivers/gpu/drm/amd/display/dc/dce/dce_aux.c: In function dce_aux_configure_timeout:
+drivers/gpu/drm/amd/display/dc/dce/dce_aux.c: warning: variable timeout set but not used [-Wunused-but-set-variable]
+
+Signed-off-by: Chenwandun <chenwandun@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 5 -----
+ 1 file changed, 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+index 3c3830f7908f..ca1d076d4184 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+@@ -429,7 +429,6 @@ static bool dce_aux_configure_timeout(struct ddc_service *ddc,
+ {
+ 	uint32_t multiplier = 0;
+ 	uint32_t length = 0;
+-	uint32_t timeout = 0;
+ 	struct ddc *ddc_pin = ddc->ddc_pin;
+ 	struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
+ 	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine);
+@@ -443,25 +442,21 @@ static bool dce_aux_configure_timeout(struct ddc_service *ddc,
+ 		length = timeout_in_us/TIME_OUT_MULTIPLIER_8;
+ 		if (timeout_in_us % TIME_OUT_MULTIPLIER_8 != 0)
+ 			length++;
+-		timeout = length * TIME_OUT_MULTIPLIER_8;
+ 	} else if (timeout_in_us <= 2 * TIME_OUT_INCREMENT) {
+ 		multiplier = 1;
+ 		length = timeout_in_us/TIME_OUT_MULTIPLIER_16;
+ 		if (timeout_in_us % TIME_OUT_MULTIPLIER_16 != 0)
+ 			length++;
+-		timeout = length * TIME_OUT_MULTIPLIER_16;
+ 	} else if (timeout_in_us <= 4 * TIME_OUT_INCREMENT) {
+ 		multiplier = 2;
+ 		length = timeout_in_us/TIME_OUT_MULTIPLIER_32;
+ 		if (timeout_in_us % TIME_OUT_MULTIPLIER_32 != 0)
+ 			length++;
+-		timeout = length * TIME_OUT_MULTIPLIER_32;
+ 	} else if (timeout_in_us > 4 * TIME_OUT_INCREMENT) {
+ 		multiplier = 3;
+ 		length = timeout_in_us/TIME_OUT_MULTIPLIER_64;
+ 		if (timeout_in_us % TIME_OUT_MULTIPLIER_64 != 0)
+ 			length++;
+-		timeout = length * TIME_OUT_MULTIPLIER_64;
+ 	}
+ 
+ 	length = (length < MAX_TIMEOUT_LENGTH) ? length : MAX_TIMEOUT_LENGTH;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4295-drm-amdgpu-display-fix-mixed-declarations-and-code.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4295-drm-amdgpu-display-fix-mixed-declarations-and-code.patch
new file mode 100644
index 00000000..93980f7e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4295-drm-amdgpu-display-fix-mixed-declarations-and-code.patch
@@ -0,0 +1,36 @@
+From 7e9737fbdd50afa33a095132729c4a4a4c059b62 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 25 Oct 2019 16:03:17 -0400
+Subject: [PATCH 4295/4736] drm/amdgpu/display: fix mixed declarations and code
+
+Trivial.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index ff32c7380efb..987897748174 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1687,6 +1687,7 @@ static bool construct(
+ 	struct dc_context *ctx = dc->ctx;
+ 	struct irq_service_init_data init_data;
+ 	uint32_t pipe_fuses = read_pipe_fuses(ctx);
++	uint32_t num_pipes;
+ 
+ 	ctx->dc_bios->regs = &bios_regs;
+ 
+@@ -1800,7 +1801,7 @@ static bool construct(
+ 
+ 	pool->base.pp_smu = dcn21_pp_smu_create(ctx);
+ 
+-	uint32_t num_pipes = dcn2_1_ip.max_num_dpp;
++	num_pipes = dcn2_1_ip.max_num_dpp;
+ 
+ 	for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
+ 		if (pipe_fuses & 1 << i)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4296-drm-amd-powerplay-Disable-gfx-CGPG-when-suspend-smu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4296-drm-amd-powerplay-Disable-gfx-CGPG-when-suspend-smu.patch
new file mode 100644
index 00000000..8df71bd3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4296-drm-amd-powerplay-Disable-gfx-CGPG-when-suspend-smu.patch
@@ -0,0 +1,39 @@
+From edc76deef950f1305de137efda64eeca6f0ee71a Mon Sep 17 00:00:00 2001
+From: chen gong <curry.gong@amd.com>
+Date: Fri, 25 Oct 2019 18:51:23 +0800
+Subject: [PATCH 4296/4736] drm/amd/powerplay: Disable gfx CGPG when suspend
+ smu
+
+if no disable gfx CGPG when suspend smu, enabling gfx CGPG will fail when resume smu.
+
+Platform: Renoir
+dmesg log information:
+
+[  151.844110 ] amdgpu: [powerplay] SMU is resuming...
+[  151.844116 ] amdgpu: [powerplay] dpm has been disabled
+[  151.844604 ] amdgpu: [powerplay] Failed to send message 0x2f,response 0xfffffffb param 0x1
+[  151.844605 ] amdgpu: [powerplay] SMU is resumed successfully!
+
+Signed-off-by: chen gong <curry.gong@amd.com>
+Acked-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 3ce01e1994fc..cda79f0eb822 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1351,6 +1351,8 @@ static int smu_suspend(void *handle)
+ 	if (adev->asic_type >= CHIP_NAVI10 &&
+ 	    adev->gfx.rlc.funcs->stop)
+ 		adev->gfx.rlc.funcs->stop(adev);
++	if (smu->is_apu)
++		smu_set_gfx_cgpg(&adev->smu, false);
+ 
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4297-drm-amdgpu-powerplay-vega10-allow-undervolting-in-p7.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4297-drm-amdgpu-powerplay-vega10-allow-undervolting-in-p7.patch
new file mode 100644
index 00000000..8ed36862
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4297-drm-amdgpu-powerplay-vega10-allow-undervolting-in-p7.patch
@@ -0,0 +1,36 @@
+From 21e9e32420338fd825fae8951eec7381232a5d59 Mon Sep 17 00:00:00 2001
+From: Pelle van Gils <pelle@vangils.xyz>
+Date: Thu, 24 Oct 2019 16:04:31 +0200
+Subject: [PATCH 4297/4736] drm/amdgpu/powerplay/vega10: allow undervolting in
+ p7
+
+The vega10_odn_update_soc_table() function does not allow the SCLK
+dependent voltage to be set for power-state 7 to a value below the default
+in pptable. Change the for-loop condition to allow undervolting in the
+highest state.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205277
+Signed-off-by: Pelle van Gils <pelle@vangils.xyz>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+index c31ef4262c9e..f62e320ed43d 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+@@ -5095,9 +5095,7 @@ static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
+ 
+ 	if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
+ 		podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
+-		for (i = 0; i < podn_vdd_dep->count - 1; i++)
+-			od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
+-		if (od_vddc_lookup_table->entries[i].us_vdd < podn_vdd_dep->entries[i].vddc)
++		for (i = 0; i < podn_vdd_dep->count; i++)
+ 			od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
+ 	} else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
+ 		podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4298-drm-amd-powerplay-Make-two-functions-static.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4298-drm-amd-powerplay-Make-two-functions-static.patch
new file mode 100644
index 00000000..7d864985
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4298-drm-amd-powerplay-Make-two-functions-static.patch
@@ -0,0 +1,44 @@
+From 2f0a3ce21f89ed530c9fbdfdde05b8815cce575c Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Mon, 28 Oct 2019 21:36:21 +0800
+Subject: [PATCH 4298/4736] drm/amd/powerplay: Make two functions static
+
+Fix sparse warnings:
+
+drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c:2050:5:
+ warning: symbol 'arcturus_i2c_eeprom_control_init' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c:2068:6:
+ warning: symbol 'arcturus_i2c_eeprom_control_fini' was not declared. Should it be static?
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 93633f76989e..4315a887e918 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -2047,7 +2047,7 @@ static const struct i2c_algorithm arcturus_i2c_eeprom_i2c_algo = {
+ 	.functionality = arcturus_i2c_eeprom_i2c_func,
+ };
+ 
+-int arcturus_i2c_eeprom_control_init(struct i2c_adapter *control)
++static int arcturus_i2c_eeprom_control_init(struct i2c_adapter *control)
+ {
+ 	struct amdgpu_device *adev = to_amdgpu_device(control);
+ 	int res;
+@@ -2065,7 +2065,7 @@ int arcturus_i2c_eeprom_control_init(struct i2c_adapter *control)
+ 	return res;
+ }
+ 
+-void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
++static void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
+ {
+ 	i2c_del_adapter(control);
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4299-drm-amd-display-Make-calculate_integer_scaling-stati.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4299-drm-amd-display-Make-calculate_integer_scaling-stati.patch
new file mode 100644
index 00000000..41b7d4c7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4299-drm-amd-display-Make-calculate_integer_scaling-stati.patch
@@ -0,0 +1,34 @@
+From 891fb7b5e78dcbadf7f2ccf05f23ff505b32fbf4 Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Mon, 28 Oct 2019 21:34:36 +0800
+Subject: [PATCH 4299/4736] drm/amd/display: Make calculate_integer_scaling
+ static
+
+Fix sparse warning:
+
+drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_resource.c:963:6:
+ warning: symbol 'calculate_integer_scaling' was not declared. Should it be static?
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index e8b16b4acacc..42c44c05759f 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -957,7 +957,7 @@ static bool are_rects_integer_multiples(struct rect src, struct rect dest)
+ 	return false;
+ }
+ 
+-void calculate_integer_scaling(struct pipe_ctx *pipe_ctx)
++static void calculate_integer_scaling(struct pipe_ctx *pipe_ctx)
+ {
+ 	if (!pipe_ctx->plane_state->scaling_quality.integer_scaling)
+ 		return;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4300-drm-amd-declare-amdgpu_exp_hw_support-in-amdgpu.h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4300-drm-amd-declare-amdgpu_exp_hw_support-in-amdgpu.h.patch
new file mode 100644
index 00000000..ca97d02b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4300-drm-amd-declare-amdgpu_exp_hw_support-in-amdgpu.h.patch
@@ -0,0 +1,31 @@
+From 857c235862ef0e14bea15e33a23ebaf9ea7a151f Mon Sep 17 00:00:00 2001
+From: Wambui Karuga <wambui.karugax@gmail.com>
+Date: Mon, 28 Oct 2019 12:20:04 +0300
+Subject: [PATCH 4300/4736] drm/amd: declare amdgpu_exp_hw_support in amdgpu.h
+
+Declare `amdgpu_exp_hw_support` as extern in amdgpu.h to address the
+following sparse warning:
+drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c:118:5: warning: symbol 'amdgpu_exp_hw_support' was not declared. Should it be static?
+
+Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com>
+Suggested-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index f1f258a2790a..ee31b20b0656 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -142,6 +142,7 @@ extern int amdgpu_vm_fragment_size;
+ extern int amdgpu_vm_fault_stop;
+ extern int amdgpu_vm_debug;
+ extern int amdgpu_vm_update_mode;
++extern int amdgpu_exp_hw_support;
+ extern int amdgpu_dc;
+ extern int amdgpu_sched_jobs;
+ extern int amdgpu_sched_hw_submission;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4301-drm-amd-correct-_LENTH-mispelling-in-constant.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4301-drm-amd-correct-_LENTH-mispelling-in-constant.patch
new file mode 100644
index 00000000..bb07daa6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4301-drm-amd-correct-_LENTH-mispelling-in-constant.patch
@@ -0,0 +1,70 @@
+From c9c7c06085f5588971dae06a865d449bcb1d02d4 Mon Sep 17 00:00:00 2001
+From: Wambui Karuga <wambui.karugax@gmail.com>
+Date: Mon, 28 Oct 2019 12:20:05 +0300
+Subject: [PATCH 4301/4736] drm/amd: correct "_LENTH" mispelling in constant
+
+Correct the "_LENTH" mispelling in the AMDGPU_MAX_TIMEOUT_PARAM_LENGTH
+constant.
+
+Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c    | 2 +-
+ 3 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index ee31b20b0656..2eb3a6bcbd6c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -109,7 +109,7 @@ struct amdgpu_mgpu_info
+ 	uint32_t			num_apu;
+ };
+ 
+-#define AMDGPU_MAX_TIMEOUT_PARAM_LENTH	256
++#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH	256
+ 
+ /*
+  * Modules parameters.
+@@ -128,7 +128,7 @@ extern int amdgpu_disp_priority;
+ extern int amdgpu_hw_i2c;
+ extern int amdgpu_pcie_gen2;
+ extern int amdgpu_msi;
+-extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH];
++extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
+ extern int amdgpu_dpm;
+ extern int amdgpu_fw_load_type;
+ extern int amdgpu_aspm;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index e30e4f8f7df3..7d134976492a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2628,9 +2628,9 @@ static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
+ 	else
+ 		adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
+ 
+-	if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
++	if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
+ 		while ((timeout_setting = strsep(&input, ",")) &&
+-				strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
++				strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
+ 			ret = kstrtol(timeout_setting, 0, &timeout);
+ 			if (ret)
+ 				return ret;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 131dd2e91bf0..97d6103bc023 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -99,7 +99,7 @@ int amdgpu_disp_priority = 0;
+ int amdgpu_hw_i2c = 0;
+ int amdgpu_pcie_gen2 = -1;
+ int amdgpu_msi = -1;
+-char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH];
++char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
+ int amdgpu_dpm = -1;
+ int amdgpu_fw_load_type = -1;
+ int amdgpu_aspm = -1;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4302-drm-amdgpu-remove-set-but-not-used-variable-adev.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4302-drm-amdgpu-remove-set-but-not-used-variable-adev.patch
new file mode 100644
index 00000000..01b47274
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4302-drm-amdgpu-remove-set-but-not-used-variable-adev.patch
@@ -0,0 +1,68 @@
+From 48bce9df3f014a63fd877f3cd651af7bec1a87eb Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Wed, 23 Oct 2019 15:58:31 +0800
+Subject: [PATCH 4302/4736] drm/amdgpu: remove set but not used variable 'adev'
+
+drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:1221:24: warning: variable adev set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:488:24: warning: variable adev set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c:547:24: warning: variable adev set but not used [-Wunused-but-set-variable]
+
+It is never used, so can removed it.
+
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 9 ---------
+ 1 file changed, 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 8bdc1eec496e..9a094e118d96 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -596,15 +596,12 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
+ 				struct ttm_operation_ctx *ctx,
+ 				struct ttm_mem_reg *new_mem)
+ {
+-	struct amdgpu_device *adev;
+ 	struct ttm_mem_reg *old_mem = &bo->mem;
+ 	struct ttm_mem_reg tmp_mem;
+ 	struct ttm_place placements;
+ 	struct ttm_placement placement;
+ 	int r;
+ 
+-	adev = amdgpu_ttm_adev(bo->bdev);
+-
+ 	/* create space/pages for new_mem in GTT space */
+ 	tmp_mem = *new_mem;
+ 	tmp_mem.mm_node = NULL;
+@@ -655,15 +652,12 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
+ 				struct ttm_operation_ctx *ctx,
+ 				struct ttm_mem_reg *new_mem)
+ {
+-	struct amdgpu_device *adev;
+ 	struct ttm_mem_reg *old_mem = &bo->mem;
+ 	struct ttm_mem_reg tmp_mem;
+ 	struct ttm_placement placement;
+ 	struct ttm_place placements;
+ 	int r;
+ 
+-	adev = amdgpu_ttm_adev(bo->bdev);
+-
+ 	/* make space in GTT for old_mem buffer */
+ 	tmp_mem = *new_mem;
+ 	tmp_mem.mm_node = NULL;
+@@ -1372,11 +1366,8 @@ static struct ttm_backend_func amdgpu_backend_func = {
+ static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
+ 					   uint32_t page_flags)
+ {
+-	struct amdgpu_device *adev;
+ 	struct amdgpu_ttm_tt *gtt;
+ 
+-	adev = amdgpu_ttm_adev(bo->bdev);
+-
+ 	gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
+ 	if (gtt == NULL) {
+ 		return NULL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4303-drm-amdgpu-Remove-superfluous-void-cast-in-debugfs_c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4303-drm-amdgpu-Remove-superfluous-void-cast-in-debugfs_c.patch
new file mode 100644
index 00000000..60b99cc7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4303-drm-amdgpu-Remove-superfluous-void-cast-in-debugfs_c.patch
@@ -0,0 +1,34 @@
+From 18aa3bbb4b9f2dcd2a215c9cf13f3fb975ffb41c Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Mon, 21 Oct 2019 16:51:47 +0200
+Subject: [PATCH 4303/4736] drm/amdgpu: Remove superfluous void * cast in
+ debugfs_create_file() call
+
+There is no need to cast a typed pointer to a void pointer when calling
+a function that accepts the latter.  Remove it, as the cast prevents
+further compiler checks.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+index f68438e8f092..996cb998dc1f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+@@ -1086,8 +1086,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
+ {
+ 	adev->debugfs_preempt =
+ 		debugfs_create_file("amdgpu_preempt_ib", 0600,
+-				    adev->ddev->primary->debugfs_root,
+-				    (void *)adev, &fops_ib_preempt);
++				    adev->ddev->primary->debugfs_root, adev,
++				    &fops_ib_preempt);
+ 	if (!(adev->debugfs_preempt)) {
+                 DRM_ERROR("unable to create amdgpu_preempt_ib debugsfs file\n");
+ 		return -EIO;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4304-drm-amdkfd-Delete-unnecessary-pr_fmt-switch.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4304-drm-amdkfd-Delete-unnecessary-pr_fmt-switch.patch
new file mode 100644
index 00000000..9c048f9a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4304-drm-amdkfd-Delete-unnecessary-pr_fmt-switch.patch
@@ -0,0 +1,81 @@
+From 7db20f1d3760858814739b32f1e033c809123da6 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 25 Oct 2019 17:09:35 -0400
+Subject: [PATCH 4304/4736] drm/amdkfd: Delete unnecessary pr_fmt switch
+
+Given amdkfd.ko has been merged into amdgpu.ko, this switch is no
+longer useful.
+
+Change-Id: If56b80e086f4ea26f347c70b620b3892afc24ddf
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 4 ----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c  | 3 ---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c   | 4 ----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c    | 4 ----
+ 4 files changed, 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+index 7288810e0df5..b91a9be32317 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+@@ -19,10 +19,6 @@
+  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+  * OTHER DEALINGS IN THE SOFTWARE.
+  */
+-
+-#undef pr_fmt
+-#define pr_fmt(fmt) "kfd2kgd: " fmt
+-
+ #include <linux/module.h>
+ #include <linux/fdtable.h>
+ #include <linux/uaccess.h>
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+index b5091e31c83f..5eb289e887b3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+@@ -19,9 +19,6 @@
+  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+  * OTHER DEALINGS IN THE SOFTWARE.
+  */
+-#undef pr_fmt
+-#define pr_fmt(fmt) "kfd2kgd: " fmt
+-
+ #include <linux/mmu_context.h>
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+index dae572c776cc..f1884b3941e2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+@@ -19,10 +19,6 @@
+  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+  * OTHER DEALINGS IN THE SOFTWARE.
+  */
+-
+-#undef pr_fmt
+-#define pr_fmt(fmt) "kfd2kgd: " fmt
+-
+ #include <linux/mmu_context.h>
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index 3e13f3e9097a..9ce17867fac7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -19,10 +19,6 @@
+  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+  * OTHER DEALINGS IN THE SOFTWARE.
+  */
+-
+-#undef pr_fmt
+-#define pr_fmt(fmt) "kfd2kgd: " fmt
+-
+ #include <linux/list.h>
+ #include <linux/pagemap.h>
+ #include <linux/sched/mm.h>
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4305-drm-amdkfd-Delete-duplicated-queue-bit-map-reservati.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4305-drm-amdkfd-Delete-duplicated-queue-bit-map-reservati.patch
new file mode 100644
index 00000000..4aaa981e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4305-drm-amdkfd-Delete-duplicated-queue-bit-map-reservati.patch
@@ -0,0 +1,38 @@
+From bf30bff8f8fbd6e4d4cc1f2329194856fb54cb13 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Thu, 24 Oct 2019 17:05:57 -0400
+Subject: [PATCH 4305/4736] drm/amdkfd: Delete duplicated queue bit map
+ reservation
+
+The KIQ is on the second MEC and its reservation is covered in the
+latter logic, so no need to reserve its bit twice.
+
+Change-Id: Ieee390953a60c7d43de5a9aec38803f1f583a4a9
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 8 --------
+ 1 file changed, 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+index 1783883e40b6..5ed49096224b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+@@ -136,14 +136,6 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
+ 				  adev->gfx.mec.queue_bitmap,
+ 				  KGD_MAX_QUEUES);
+ 
+-		/* remove the KIQ bit as well */
+-		if (adev->gfx.kiq.ring.sched.ready)
+-			clear_bit(amdgpu_gfx_mec_queue_to_bit(adev,
+-							  adev->gfx.kiq.ring.me - 1,
+-							  adev->gfx.kiq.ring.pipe,
+-							  adev->gfx.kiq.ring.queue),
+-				  gpu_resources.queue_bitmap);
+-
+ 		/* According to linux/bitmap.h we shouldn't use bitmap_clear if
+ 		 * nbits is not compile time constant
+ 		 */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4306-drm-amdkfd-bug-fix-for-out-of-bounds-mem-on-gpu-cach.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4306-drm-amdkfd-bug-fix-for-out-of-bounds-mem-on-gpu-cach.patch
new file mode 100644
index 00000000..ae9ad4bf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4306-drm-amdkfd-bug-fix-for-out-of-bounds-mem-on-gpu-cach.patch
@@ -0,0 +1,36 @@
+From 75cf0d7a899f1dfdd25b245476ea124c1db17fca Mon Sep 17 00:00:00 2001
+From: Alex Sierra <alex.sierra@amd.com>
+Date: Thu, 24 Oct 2019 13:14:31 -0500
+Subject: [PATCH 4306/4736] drm/amdkfd: bug fix for out of bounds mem on gpu
+ cache filling info
+
+The bitmap in cu_info structure is defined as a 4x4 size array. In
+Acturus, this matrix is initialized as a 4x2. Based on the 8 shaders.
+In the gpu cache filling initialization, the access to the bitmap matrix
+was done as an 8x1 instead of 4x2. Causing an out of bounds memory
+access error.
+Due to this, the number of GPU cache entries was inconsistent.
+
+Change-Id: I20fadd0a12403a8808cf074c0d7160daad6834ee
+Signed-off-by: Alex Sierra <alex.sierra@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+index 7655c6a2b184..22fe58971a62 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+@@ -710,7 +710,7 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
+ 						pcache_info,
+ 						cu_info,
+ 						mem_available,
+-						cu_info->cu_bitmap[i][j],
++						cu_info->cu_bitmap[i % 4][j + i / 4],
+ 						ct,
+ 						cu_processor_id,
+ 						k);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4307-drm-amd-display-Add-ENGINE_ID_DIGD-condition-check-f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4307-drm-amd-display-Add-ENGINE_ID_DIGD-condition-check-f.patch
new file mode 100644
index 00000000..8445299a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4307-drm-amd-display-Add-ENGINE_ID_DIGD-condition-check-f.patch
@@ -0,0 +1,42 @@
+From e222a82077c62b125dd397a7da2167f63674d7fc Mon Sep 17 00:00:00 2001
+From: Zhan liu <zhan.liu@amd.com>
+Date: Fri, 1 Nov 2019 22:42:41 -0400
+Subject: [PATCH 4307/4736] drm/amd/display: Add ENGINE_ID_DIGD condition check
+ for Navi14
+
+[Why]
+Navi10 has 6 PHY, but Navi14 only has 5 PHY, that is
+because there is no ENGINE_ID_DIGD in Navi14. Without
+this patch, many HDMI related issues (e.g. HDMI S3
+resume failure, HDMI pink screen on boot) will be
+observed.
+
+[How]
+If "eng_id" is larger than ENGINE_ID_DIGD, then
+add "eng_id" by 1.
+
+Signed-off-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index d1c7e10cb722..ef43faa09eb3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1150,6 +1150,11 @@ struct stream_encoder *dcn20_stream_encoder_create(
+ 	if (!enc1)
+ 		return NULL;
+ 
++	if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
++		if (eng_id >= ENGINE_ID_DIGD)
++			eng_id++;
++	}
++
+ 	dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
+ 					&stream_enc_regs[eng_id],
+ 					&se_shift, &se_mask);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4308-drm-amdgpu-fix-stack-alignment-ABI-mismatch-for-Clan.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4308-drm-amdgpu-fix-stack-alignment-ABI-mismatch-for-Clan.patch
new file mode 100644
index 00000000..5268111d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4308-drm-amdgpu-fix-stack-alignment-ABI-mismatch-for-Clan.patch
@@ -0,0 +1,161 @@
+From 0549828354c1707532b672c9e9d08ecc418c1421 Mon Sep 17 00:00:00 2001
+From: Nick Desaulniers <ndesaulniers@google.com>
+Date: Wed, 16 Oct 2019 16:02:07 -0700
+Subject: [PATCH 4308/4736] drm/amdgpu: fix stack alignment ABI mismatch for
+ Clang
+
+The x86 kernel is compiled with an 8B stack alignment via
+`-mpreferred-stack-boundary=3` for GCC since 3.6-rc1 via
+commit d9b0cde91c60 ("x86-64, gcc: Use -mpreferred-stack-boundary=3 if supported")
+or `-mstack-alignment=8` for Clang. Parts of the AMDGPU driver are
+compiled with 16B stack alignment.
+
+Generally, the stack alignment is part of the ABI. Linking together two
+different translation units with differing stack alignment is dangerous,
+particularly when the translation unit with the smaller stack alignment
+makes calls into the translation unit with the larger stack alignment.
+While 8B aligned stacks are sometimes also 16B aligned, they are not
+always.
+
+Multiple users have reported General Protection Faults (GPF) when using
+the AMDGPU driver compiled with Clang. Clang is placing objects in stack
+slots assuming the stack is 16B aligned, and selecting instructions that
+require 16B aligned memory operands.
+
+At runtime, syscall handlers with 8B aligned stack call into code that
+assumes 16B stack alignment.  When the stack is a multiple of 8B but not
+16B, these instructions result in a GPF.
+
+Remove the code that added compatibility between the differing compiler
+flags, as it will result in runtime GPFs when built with Clang. Cleanups
+for GCC will be sent in later patches in the series.
+
+Link: https://github.com/ClangBuiltLinux/linux/issues/735
+Tested-by: Shirish S <shirish.s@amd.com>
+Debugged-by: Yuxuan Shui <yshuiv7@gmail.com>
+Reported-by: Shirish S <shirish.s@amd.com>
+Reported-by: Yuxuan Shui <yshuiv7@gmail.com>
+Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/calcs/Makefile | 10 ++++------
+ drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 10 ++++------
+ drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 10 ++++------
+ drivers/gpu/drm/amd/display/dc/dml/Makefile   | 10 ++++------
+ drivers/gpu/drm/amd/display/dc/dsc/Makefile   | 10 ++++------
+ 5 files changed, 20 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+index 16614d73a5fc..ab522ea992d2 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+@@ -24,13 +24,11 @@
+ # It calculates Bandwidth and Watermarks values for HW programming
+ #
+ 
+-ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
+-	cc_stack_align := -mpreferred-stack-boundary=4
+-else ifneq ($(call cc-option, -mstack-alignment=16),)
+-	cc_stack_align := -mstack-alignment=16
+-endif
++calcs_ccflags := -mhard-float -msse
+ 
+-calcs_ccflags := -mhard-float -msse $(cc_stack_align)
++ifdef CONFIG_CC_IS_GCC
++calcs_ccflags += -mpreferred-stack-boundary=4
++endif
+ 
+ ifdef CONFIG_CC_IS_CLANG
+ calcs_ccflags += -msse2
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+index f57a3b281408..a02e02980310 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+@@ -10,13 +10,11 @@ ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ DCN20 += dcn20_dsc.o
+ endif
+ 
+-ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
+-	cc_stack_align := -mpreferred-stack-boundary=4
+-else ifneq ($(call cc-option, -mstack-alignment=16),)
+-	cc_stack_align := -mstack-alignment=16
+-endif
++CFLAGS_dcn20_resource.o := -mhard-float -msse
+ 
+-CFLAGS_dcn20_resource.o := -mhard-float -msse $(cc_stack_align)
++ifdef CONFIG_CC_IS_GCC
++CFLAGS_dcn20_resource.o += -mpreferred-stack-boundary=4
++endif
+ 
+ ifdef CONFIG_CC_IS_CLANG
+ CFLAGS_dcn20_resource.o += -msse2
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+index 4ddd4037c1f8..0fa857b69143 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+@@ -3,13 +3,11 @@
+ 
+ DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o dcn21_link_encoder.o
+ 
+-ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
+-	cc_stack_align := -mpreferred-stack-boundary=4
+-else ifneq ($(call cc-option, -mstack-alignment=16),)
+-	cc_stack_align := -mstack-alignment=16
+-endif
++CFLAGS_dcn21_resource.o := -mhard-float -msse
+ 
+-CFLAGS_dcn21_resource.o := -mhard-float -msse $(cc_stack_align)
++ifdef CONFIG_CC_IS_GCC
++CFLAGS_dcn21_resource.o += -mpreferred-stack-boundary=4
++endif
+ 
+ ifdef CONFIG_CC_IS_CLANG
+ CFLAGS_dcn21_resource.o += -msse2
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+index af2a864a6da0..b3db0900b473 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+@@ -24,13 +24,11 @@
+ # It provides the general basic services required by other DAL
+ # subcomponents.
+ 
+-ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
+-	cc_stack_align := -mpreferred-stack-boundary=4
+-else ifneq ($(call cc-option, -mstack-alignment=16),)
+-	cc_stack_align := -mstack-alignment=16
+-endif
++dml_ccflags := -mhard-float -msse
+ 
+-dml_ccflags := -mhard-float -msse $(cc_stack_align)
++ifdef CONFIG_CC_IS_GCC
++dml_ccflags += -mpreferred-stack-boundary=4
++endif
+ 
+ ifdef CONFIG_CC_IS_CLANG
+ dml_ccflags += -msse2
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+index 17db603f2d1f..4d18e2b60223 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+@@ -1,13 +1,11 @@
+ #
+ # Makefile for the 'dsc' sub-component of DAL.
+ 
+-ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
+-	cc_stack_align := -mpreferred-stack-boundary=4
+-else ifneq ($(call cc-option, -mstack-alignment=16),)
+-	cc_stack_align := -mstack-alignment=16
+-endif
++dsc_ccflags := -mhard-float -msse
+ 
+-dsc_ccflags := -mhard-float -msse $(cc_stack_align)
++ifdef CONFIG_CC_IS_GCC
++dsc_ccflags += -mpreferred-stack-boundary=4
++endif
+ 
+ ifdef CONFIG_CC_IS_CLANG
+ dsc_ccflags += -msse2
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4309-drm-amdgpu-fix-stack-alignment-ABI-mismatch-for-GCC-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4309-drm-amdgpu-fix-stack-alignment-ABI-mismatch-for-GCC-.patch
new file mode 100644
index 00000000..8be7461e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4309-drm-amdgpu-fix-stack-alignment-ABI-mismatch-for-GCC-.patch
@@ -0,0 +1,155 @@
+From b7033f0828ca07dbc4e3a8b4f4c91b23e09eb08c Mon Sep 17 00:00:00 2001
+From: Nick Desaulniers <ndesaulniers@google.com>
+Date: Wed, 16 Oct 2019 16:02:08 -0700
+Subject: [PATCH 4309/4736] drm/amdgpu: fix stack alignment ABI mismatch for
+ GCC 7.1+
+
+GCC earlier than 7.1 errors when compiling code that makes use of
+`double`s and sets a stack alignment outside of the range of [2^4-2^12]:
+
+$ cat foo.c
+double foo(double x, double y) {
+  return x + y;
+}
+$ gcc-4.9 -mpreferred-stack-boundary=3 foo.c
+error: -mpreferred-stack-boundary=3 is not between 4 and 12
+
+This is likely why the AMDGPU driver was ever compiled with a different
+stack alignment (and thus different ABI) than the rest of the x86
+kernel. The kernel uses 8B stack alignment, while the driver was using
+16B stack alignment in a few places.
+
+Since GCC 7.1+ doesn't error, fix the ABI mismatch for users of newer
+versions of GCC.
+
+There was discussion about whether to mark the driver broken or not for
+users of GCC earlier than 7.1, but since the driver currently is
+working, don't explicitly break the driver for them here.
+
+Relying on differing stack alignment is unspecified behavior, and
+brittle, and may break in the future.
+
+This patch is no functional change for GCC users earlier than 7.1. It's
+been compile tested on GCC 4.9 and 8.3 to check the correct flags. It
+should be boot tested when built with GCC 7.1+.
+
+-mincoming-stack-boundary= or -mstackrealign may help keep this code
+building for pre-GCC 7.1 users.
+
+The version check for GCC is broken into two conditionals, both because
+cc-ifversion is currently GCC specific, and it simplifies a subsequent
+patch.
+
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/calcs/Makefile | 9 +++++++++
+ drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 9 +++++++++
+ drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 9 +++++++++
+ drivers/gpu/drm/amd/display/dc/dml/Makefile   | 9 +++++++++
+ drivers/gpu/drm/amd/display/dc/dsc/Makefile   | 9 +++++++++
+ 5 files changed, 45 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+index ab522ea992d2..393215ef9f98 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+@@ -27,6 +27,15 @@
+ calcs_ccflags := -mhard-float -msse
+ 
+ ifdef CONFIG_CC_IS_GCC
++ifeq ($(call cc-ifversion, -lt, 0701, y), y)
++IS_OLD_GCC = 1
++endif
++endif
++
++ifdef IS_OLD_GCC
++# Stack alignment mismatch, proceed with caution.
++# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
++# (8B stack alignment).
+ calcs_ccflags += -mpreferred-stack-boundary=4
+ endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+index a02e02980310..d684cb912d92 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+@@ -13,6 +13,15 @@ endif
+ CFLAGS_dcn20_resource.o := -mhard-float -msse
+ 
+ ifdef CONFIG_CC_IS_GCC
++ifeq ($(call cc-ifversion, -lt, 0701, y), y)
++IS_OLD_GCC = 1
++endif
++endif
++
++ifdef IS_OLD_GCC
++# Stack alignment mismatch, proceed with caution.
++# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
++# (8B stack alignment).
+ CFLAGS_dcn20_resource.o += -mpreferred-stack-boundary=4
+ endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+index 0fa857b69143..72609a40c6a3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+@@ -6,6 +6,15 @@ DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o dcn21_link_en
+ CFLAGS_dcn21_resource.o := -mhard-float -msse
+ 
+ ifdef CONFIG_CC_IS_GCC
++ifeq ($(call cc-ifversion, -lt, 0701, y), y)
++IS_OLD_GCC = 1
++endif
++endif
++
++ifdef IS_OLD_GCC
++# Stack alignment mismatch, proceed with caution.
++# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
++# (8B stack alignment).
+ CFLAGS_dcn21_resource.o += -mpreferred-stack-boundary=4
+ endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+index b3db0900b473..f85f2bb1b0c7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+@@ -27,6 +27,15 @@
+ dml_ccflags := -mhard-float -msse
+ 
+ ifdef CONFIG_CC_IS_GCC
++ifeq ($(call cc-ifversion, -lt, 0701, y), y)
++IS_OLD_GCC = 1
++endif
++endif
++
++ifdef IS_OLD_GCC
++# Stack alignment mismatch, proceed with caution.
++# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
++# (8B stack alignment).
+ dml_ccflags += -mpreferred-stack-boundary=4
+ endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+index 4d18e2b60223..ec2ebee0078f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+@@ -4,6 +4,15 @@
+ dsc_ccflags := -mhard-float -msse
+ 
+ ifdef CONFIG_CC_IS_GCC
++ifeq ($(call cc-ifversion, -lt, 0701, y), y)
++IS_OLD_GCC = 1
++endif
++endif
++
++ifdef IS_OLD_GCC
++# Stack alignment mismatch, proceed with caution.
++# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
++# (8B stack alignment).
+ dsc_ccflags += -mpreferred-stack-boundary=4
+ endif
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4310-drm-amdgpu-enable-msse2-for-GCC-7.1-users.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4310-drm-amdgpu-enable-msse2-for-GCC-7.1-users.patch
new file mode 100644
index 00000000..2925348d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4310-drm-amdgpu-enable-msse2-for-GCC-7.1-users.patch
@@ -0,0 +1,122 @@
+From 89ebce5861f64bd3fcd1aa17d12e6d181632234e Mon Sep 17 00:00:00 2001
+From: Nick Desaulniers <ndesaulniers@google.com>
+Date: Wed, 16 Oct 2019 16:02:09 -0700
+Subject: [PATCH 4310/4736] drm/amdgpu: enable -msse2 for GCC 7.1+ users
+
+A final attempt at enabling sse2 for GCC users.
+
+Orininally attempted in:
+commit 10117450735c ("drm/amd/display: add -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines")
+
+Reverted due to "reported instability" in:
+commit 193392ed9f69 ("Revert "drm/amd/display: add -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines"")
+
+Re-added just for Clang in:
+commit 0f0727d971f6 ("drm/amd/display: readd -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines")
+
+The original report didn't have enough information to know if the GPF
+was due to misalignment, but I suspect that it was. (The missing
+information was the disassembly of the function at the bottom of the
+trace, to see if the instruction pointer pointed to an instruction with
+16B alignment memory operand requirements.  The stack trace does show
+the stack was only 8B but not 16B aligned though, which makes this a
+strong possibility).
+
+Now that the stack misalignment issue has been fixed for users of GCC
+7.1+, reattempt adding -msse2. This matches Clang.
+
+It will likely never be safe to enable this for pre-GCC 7.1 AND use a
+16B aligned stack in these translation units.
+
+This is only a functional change for GCC 7.1+ users, and should be boot
+tested.
+
+Link: https://bugs.freedesktop.org/show_bug.cgi?id=109487
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/calcs/Makefile | 4 +---
+ drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 4 +---
+ drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 4 +---
+ drivers/gpu/drm/amd/display/dc/dml/Makefile   | 4 +---
+ drivers/gpu/drm/amd/display/dc/dsc/Makefile   | 4 +---
+ 5 files changed, 5 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+index 393215ef9f98..e59a7f356188 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+@@ -37,9 +37,7 @@ ifdef IS_OLD_GCC
+ # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+ # (8B stack alignment).
+ calcs_ccflags += -mpreferred-stack-boundary=4
+-endif
+-
+-ifdef CONFIG_CC_IS_CLANG
++else
+ calcs_ccflags += -msse2
+ endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+index d684cb912d92..be3a614963c6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+@@ -23,9 +23,7 @@ ifdef IS_OLD_GCC
+ # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+ # (8B stack alignment).
+ CFLAGS_dcn20_resource.o += -mpreferred-stack-boundary=4
+-endif
+-
+-ifdef CONFIG_CC_IS_CLANG
++else
+ CFLAGS_dcn20_resource.o += -msse2
+ endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+index 72609a40c6a3..feb7e705e792 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+@@ -16,9 +16,7 @@ ifdef IS_OLD_GCC
+ # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+ # (8B stack alignment).
+ CFLAGS_dcn21_resource.o += -mpreferred-stack-boundary=4
+-endif
+-
+-ifdef CONFIG_CC_IS_CLANG
++else
+ CFLAGS_dcn21_resource.o += -msse2
+ endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+index f85f2bb1b0c7..9cc2fe56ed64 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+@@ -37,9 +37,7 @@ ifdef IS_OLD_GCC
+ # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+ # (8B stack alignment).
+ dml_ccflags += -mpreferred-stack-boundary=4
+-endif
+-
+-ifdef CONFIG_CC_IS_CLANG
++else
+ dml_ccflags += -msse2
+ endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+index ec2ebee0078f..2fff8c1f1a78 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+@@ -14,9 +14,7 @@ ifdef IS_OLD_GCC
+ # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+ # (8B stack alignment).
+ dsc_ccflags += -mpreferred-stack-boundary=4
+-endif
+-
+-ifdef CONFIG_CC_IS_CLANG
++else
+ dsc_ccflags += -msse2
+ endif
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4311-drm-amdgpu-SRIOV-SRIOV-VF-doesn-t-support-BACO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4311-drm-amdgpu-SRIOV-SRIOV-VF-doesn-t-support-BACO.patch
new file mode 100644
index 00000000..af3252c0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4311-drm-amdgpu-SRIOV-SRIOV-VF-doesn-t-support-BACO.patch
@@ -0,0 +1,31 @@
+From 945b8d7e559e3fd6c9a2379318ede76d21febe02 Mon Sep 17 00:00:00 2001
+From: Jiange Zhao <Jiange.Zhao@amd.com>
+Date: Mon, 28 Oct 2019 18:04:14 +0800
+Subject: [PATCH 4311/4736] drm/amdgpu/SRIOV: SRIOV VF doesn't support BACO
+
+SRIOV VF doesn't support BACO.
+
+Only PF with BACO capability can do it.
+
+Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index ebbf7712f8c8..88e3665f7b09 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -298,7 +298,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
+ {
+ 	struct smu_context *smu = &adev->smu;
+ 
+-	if (smu_baco_is_support(smu))
++	if (!amdgpu_sriov_vf(adev) && smu_baco_is_support(smu))
+ 		return AMD_RESET_METHOD_BACO;
+ 	else
+ 		return AMD_RESET_METHOD_MODE1;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4312-drm-amdgpu-clear-UVD-VCPU-buffer-when-err_event_athu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4312-drm-amdgpu-clear-UVD-VCPU-buffer-when-err_event_athu.patch
new file mode 100644
index 00000000..eaa0a0f3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4312-drm-amdgpu-clear-UVD-VCPU-buffer-when-err_event_athu.patch
@@ -0,0 +1,46 @@
+From 986adea80905c6b7232acd8b5dc702c39fb40c3e Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 25 Oct 2019 16:50:53 +0800
+Subject: [PATCH 4312/4736] drm/amdgpu: clear UVD VCPU buffer when
+ err_event_athub generated
+
+The err_event_athub error will mess up the buffer and cause UVD resume hang.
+
+Change-Id: If17a2161fb9b1b52eac08de00d2e935191bdbf99
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+index 4e5d13e41f6a..d1b10b5583ec 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+@@ -39,6 +39,8 @@
+ #include "cikd.h"
+ #include "uvd/uvd_4_2_d.h"
+ 
++#include "amdgpu_ras.h"
++
+ /* 1 second timeout */
+ #define UVD_IDLE_TIMEOUT	msecs_to_jiffies(1000)
+ 
+@@ -372,7 +374,13 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
+ 		if (!adev->uvd.inst[j].saved_bo)
+ 			return -ENOMEM;
+ 
+-		memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
++		/* re-write 0 since err_event_athub will corrupt VCPU buffer */
++		if (amdgpu_ras_intr_triggered()) {
++			DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n");
++			memset(adev->uvd.inst[j].saved_bo, 0, size);
++		} else {
++			memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
++		}
+ 	}
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4313-drm-amdgpu-bypass-some-cleanup-work-after-err_event_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4313-drm-amdgpu-bypass-some-cleanup-work-after-err_event_.patch
new file mode 100644
index 00000000..5d876186
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4313-drm-amdgpu-bypass-some-cleanup-work-after-err_event_.patch
@@ -0,0 +1,106 @@
+From 0fc7d72e51896c4a2fbfb0bcf7f83a6fa4a50a3c Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 25 Oct 2019 17:48:52 +0800
+Subject: [PATCH 4313/4736] drm/amdgpu: bypass some cleanup work after
+ err_event_athub
+
+PSP lost connection when err_event_athub occurs. These cleanup work can be
+skipped in BACO reset.
+
+Change-Id: If54a3735edd6ccbb58d40a5f8833392981f8ce37
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  6 ++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c    |  7 +++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c    | 20 +++++++++++---------
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c      |  6 ++++--
+ 4 files changed, 28 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 7d134976492a..8e35ebdf4e10 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2270,6 +2270,12 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
+ 		/* displays are handled in phase1 */
+ 		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
+ 			continue;
++		/* PSP lost connection when err_event_athub occurs */
++		if (amdgpu_ras_intr_triggered() &&
++		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
++			adev->ip_blocks[i].status.hw = false;
++			continue;
++		}
+ 		/* XXX handle errors */
+ 		r = adev->ip_blocks[i].version->funcs->suspend(adev);
+ 		/* XXX handle errors */
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index f289a84363c4..4aa21bc1e0b9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -167,6 +167,13 @@ psp_cmd_submit_buf(struct psp_context *psp,
+ 	while (*((unsigned int *)psp->fence_buf) != index) {
+                 if (--timeout == 0)
+ 			break;
++		/*
++		 * Shouldn't wait for timeout when err_event_athub occurs,
++		 * because gpu reset thread triggered and lock resource should
++		 * be released for psp resume sequence.
++		 */
++		if (amdgpu_ras_intr_triggered())
++			break;
+ 		msleep(1);
+ 		amdgpu_asic_invalidate_hdp(psp->adev, NULL);
+ 	}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index ebc3e15eca8b..afc3ee47d1b2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -556,15 +556,17 @@ int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
+ 	if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
+ 		return 0;
+ 
+-	ret = psp_ras_enable_features(&adev->psp, &info, enable);
+-	if (ret) {
+-		DRM_ERROR("RAS ERROR: %s %s feature failed ret %d\n",
+-				enable ? "enable":"disable",
+-				ras_block_str(head->block),
+-				ret);
+-		if (ret == TA_RAS_STATUS__RESET_NEEDED)
+-			return -EAGAIN;
+-		return -EINVAL;
++	if (!amdgpu_ras_intr_triggered()) {
++		ret = psp_ras_enable_features(&adev->psp, &info, enable);
++		if (ret) {
++			DRM_ERROR("RAS ERROR: %s %s feature failed ret %d\n",
++					enable ? "enable":"disable",
++					ras_block_str(head->block),
++					ret);
++			if (ret == TA_RAS_STATUS__RESET_NEEDED)
++				return -EAGAIN;
++			return -EINVAL;
++		}
+ 	}
+ 
+ 	/* setup the obj */
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 2f03bf533d41..013c1eb990f0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -3739,8 +3739,10 @@ static int gfx_v9_0_hw_fini(void *handle)
+ 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
+ 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
+ 
+-	/* disable KCQ to avoid CPC touch memory not valid anymore */
+-	gfx_v9_0_kcq_disable(adev);
++	/* DF freeze and kcq disable will fail */
++	if (!amdgpu_ras_intr_triggered())
++		/* disable KCQ to avoid CPC touch memory not valid anymore */
++		gfx_v9_0_kcq_disable(adev);
+ 
+ 	if (amdgpu_sriov_vf(adev)) {
+ 		gfx_v9_0_cp_gfx_enable(adev, false);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4314-drm-amdgpu-add-missing-amdgpu_ras.h-header-include.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4314-drm-amdgpu-add-missing-amdgpu_ras.h-header-include.patch
new file mode 100644
index 00000000..2549a07b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4314-drm-amdgpu-add-missing-amdgpu_ras.h-header-include.patch
@@ -0,0 +1,35 @@
+From d4080f0c35aa04fd1fd837071c4beb2c96135913 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Tue, 29 Oct 2019 20:39:13 +0800
+Subject: [PATCH 4314/4736] drm/amdgpu: add missing amdgpu_ras.h header include
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fix compilation error.
+
+Change-Id: I461c558778f9a52378269324dc41b8d639f3ccbe
+Signed-off-by: Le Ma <le.ma@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Christian K�«Ónig <christian.koenig@amd.com>
+Tested-by: Tom St Denis <tom.stdenis@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 4aa21bc1e0b9..8a1960106004 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -34,6 +34,8 @@
+ #include "psp_v11_0.h"
+ #include "psp_v12_0.h"
+ 
++#include "amdgpu_ras.h"
++
+ static void psp_set_funcs(struct amdgpu_device *adev);
+ 
+ static int psp_early_init(void *handle)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4315-drm-amdgpu-fix-gfx-VF-FLR-test-fail-on-navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4315-drm-amdgpu-fix-gfx-VF-FLR-test-fail-on-navi.patch
new file mode 100644
index 00000000..33ae4de8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4315-drm-amdgpu-fix-gfx-VF-FLR-test-fail-on-navi.patch
@@ -0,0 +1,30 @@
+From 3f342675d69b28118f84ecf90469545de2b486a0 Mon Sep 17 00:00:00 2001
+From: HaiJun Chang <HaiJun.Chang@amd.com>
+Date: Tue, 29 Oct 2019 15:44:08 +0800
+Subject: [PATCH 4315/4736] drm/amdgpu: fix gfx VF FLR test fail on navi
+
+Cp wptr in wb buffer is outdated after VF FLR.
+The outdated wptr may cause cp to execute unexpected packets.
+Reset cp wptr in wb buffer.
+
+Signed-off-by: HaiJun Chang <HaiJun.Chang@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index ef1975a5323a..17a5cbfd0024 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -3094,6 +3094,7 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
+ 			memcpy(mqd, adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], sizeof(*mqd));
+ 		/* reset the ring */
+ 		ring->wptr = 0;
++		adev->wb.wb[ring->wptr_offs] = 0;
+ 		amdgpu_ring_clear_ring(ring);
+ #ifdef BRING_UP_DEBUG
+ 		mutex_lock(&adev->srbm_mutex);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4316-drm-amdkfd-Delete-unnecessary-pr_fmt-switch.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4316-drm-amdkfd-Delete-unnecessary-pr_fmt-switch.patch
new file mode 100644
index 00000000..720913f6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4316-drm-amdkfd-Delete-unnecessary-pr_fmt-switch.patch
@@ -0,0 +1,64 @@
+From 28fcbf07bd27326ecd302f1dc316bdd854dae397 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 25 Oct 2019 17:09:35 -0400
+Subject: [PATCH 4316/4736] drm/amdkfd: Delete unnecessary pr_fmt switch
+
+Given amdkfd.ko has been merged into amdgpu.ko, this switch is no
+longer useful.
+
+Change-Id: I3ef93ac4510a1caf37acc1d337afd61a8a241baa
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c        | 3 ---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 4 ----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 4 ----
+ 3 files changed, 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+index 5ed49096224b..3cccb4b10862 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+@@ -20,9 +20,6 @@
+  * OTHER DEALINGS IN THE SOFTWARE.
+  */
+ 
+-#undef pr_fmt
+-#define pr_fmt(fmt) "kfd2kgd: " fmt
+-
+ 
+ #include "amdgpu_amdkfd.h"
+ #include <linux/dma-buf.h>
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+index 495b15ed28cd..07f14a9f93b8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+@@ -19,10 +19,6 @@
+  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+  * OTHER DEALINGS IN THE SOFTWARE.
+  */
+-
+-#undef pr_fmt
+-#define pr_fmt(fmt) "kfd2kgd: " fmt
+-
+ #include <linux/mmu_context.h>
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+index 0118e6f18355..d14e85205bce 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+@@ -19,10 +19,6 @@
+  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+  * OTHER DEALINGS IN THE SOFTWARE.
+  */
+-
+-#undef pr_fmt
+-#define pr_fmt(fmt) "kfd2kgd: " fmt
+-
+ #include <linux/mmu_context.h>
+ #include <drm/drmP.h>
+ #include "amdgpu.h"
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4317-drm-amdgpu-fix-no-ACK-from-LDS-read-during-stress-te.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4317-drm-amdgpu-fix-no-ACK-from-LDS-read-during-stress-te.patch
new file mode 100644
index 00000000..011bdfb4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4317-drm-amdgpu-fix-no-ACK-from-LDS-read-during-stress-te.patch
@@ -0,0 +1,30 @@
+From a60c3cf2abde5a55177f66cc039ba6f0d7d85e70 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Wed, 30 Oct 2019 16:46:32 +0800
+Subject: [PATCH 4317/4736] drm/amdgpu: fix no ACK from LDS read during stress
+ test for Arcturus
+
+Set mmSQ_CONFIG.DISABLE_SMEM_SOFT_CLAUSE as W/R.
+
+Change-Id: I6225909fd62702427fbb807e0c6ba6bafcfa41d5
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 013c1eb990f0..005f4d0d2484 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -699,6 +699,7 @@ static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] =
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),
+ };
+ 
+ static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4318-drm-amdgpu-gmc10-properly-set-BANK_SELECT-and-FRAGME.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4318-drm-amdgpu-gmc10-properly-set-BANK_SELECT-and-FRAGME.patch
new file mode 100644
index 00000000..b0392615
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4318-drm-amdgpu-gmc10-properly-set-BANK_SELECT-and-FRAGME.patch
@@ -0,0 +1,62 @@
+From e91ddfb275ca28dc49b511edae9bad77b9c4d132 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 29 Oct 2019 17:14:15 -0400
+Subject: [PATCH 4318/4736] drm/amdgpu/gmc10: properly set BANK_SELECT and
+ FRAGMENT_SIZE
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+These were not aligned for optimal performance for GPUVM.
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Tianci Yin <tianci.yin@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 9 +++++++++
+ drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c  | 9 +++++++++
+ 2 files changed, 18 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+index b601c6740ef5..b4f32d853ca1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+@@ -155,6 +155,15 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
+ 	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
+ 
+ 	tmp = mmGCVM_L2_CNTL3_DEFAULT;
++	if (adev->gmc.translate_further) {
++		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
++		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
++				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
++	} else {
++		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
++		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
++				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
++	}
+ 	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
+ 
+ 	tmp = mmGCVM_L2_CNTL4_DEFAULT;
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+index 2eea702de8ee..945533634711 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+@@ -142,6 +142,15 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
+ 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
+ 
+ 	tmp = mmMMVM_L2_CNTL3_DEFAULT;
++	if (adev->gmc.translate_further) {
++		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
++		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
++				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
++	} else {
++		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
++		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
++				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
++	}
+ 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
+ 
+ 	tmp = mmMMVM_L2_CNTL4_DEFAULT;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4319-drm-amdgpu-arcturus-properly-set-BANK_SELECT-and-FRA.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4319-drm-amdgpu-arcturus-properly-set-BANK_SELECT-and-FRA.patch
new file mode 100644
index 00000000..7d4000bf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4319-drm-amdgpu-arcturus-properly-set-BANK_SELECT-and-FRA.patch
@@ -0,0 +1,40 @@
+From e966a78c81855195a1b694d262a3f95a5efe0594 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 30 Oct 2019 13:29:52 -0400
+Subject: [PATCH 4319/4736] drm/amdgpu/arcturus: properly set BANK_SELECT and
+ FRAGMENT_SIZE
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+These were not aligned for optimal performance for GPUVM.
+
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+index 657970f9ebfb..2c5adfe803a2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+@@ -219,6 +219,15 @@ static void mmhub_v9_4_init_cache_regs(struct amdgpu_device *adev, int hubid)
+ 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
+ 
+ 	tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT;
++	if (adev->gmc.translate_further) {
++		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12);
++		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
++				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
++	} else {
++		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9);
++		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
++				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
++	}
+ 	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
+ 			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4320-drm-amd-display-remove-redundant-null-pointer-check-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4320-drm-amd-display-remove-redundant-null-pointer-check-.patch
new file mode 100644
index 00000000..b57893e7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4320-drm-amd-display-remove-redundant-null-pointer-check-.patch
@@ -0,0 +1,34 @@
+From 4c4c22b025ba1bbd162e1e845ac29e062e08f6d9 Mon Sep 17 00:00:00 2001
+From: zhong jiang <zhongjiang@huawei.com>
+Date: Wed, 30 Oct 2019 09:57:53 +0800
+Subject: [PATCH 4320/4736] drm/amd/display: remove redundant null pointer
+ check before kfree
+
+kfree has taken null pointer into account. hence it is safe to remove
+the unnecessary check.
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: zhong jiang <zhongjiang@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
+index cf6ef387e5d2..6f730b5bfe42 100644
+--- a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
++++ b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c
+@@ -174,9 +174,7 @@ static bool hdmi_14_process_transaction(
+ 			link->ctx,
+ 			link,
+ 			&i2c_command);
+-
+-	if (buff)
+-		kfree(buff);
++	kfree(buff);
+ 
+ 	return result;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4321-drm-amd-display-Add-a-conversion-function-for-transm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4321-drm-amd-display-Add-a-conversion-function-for-transm.patch
new file mode 100644
index 00000000..daa8b2f3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4321-drm-amd-display-Add-a-conversion-function-for-transm.patch
@@ -0,0 +1,95 @@
+From 7df7fe47021bfda137254b2bd114e5728b3aa56c Mon Sep 17 00:00:00 2001
+From: Nathan Chancellor <natechancellor@gmail.com>
+Date: Tue, 29 Oct 2019 23:04:11 -0700
+Subject: [PATCH 4321/4736] drm/amd/display: Add a conversion function for
+ transmitter and phy_id enums
+
+Clang warns:
+
+../drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:2520:42:
+error: implicit conversion from enumeration type 'enum transmitter' to
+different enumeration type 'enum physical_phy_id'
+[-Werror,-Wenum-conversion]
+        psr_context->smuPhyId = link->link_enc->transmitter;
+                              ~ ~~~~~~~~~~~~~~~~^~~~~~~~~~~
+1 error generated.
+
+As the comment above this assignment states, this is intentional. To
+match previous warnings of this nature, add a conversion function that
+explicitly converts between the enums and warns when there is a
+mismatch.
+
+See commit 828cfa29093f ("drm/amdgpu: Fix amdgpu ras to ta enums
+conversion") and commit d9ec5cfd5a2e ("drm/amd/display: Use switch table
+for dc_to_smu_clock_type") for previous examples of this.
+
+v2: use PHYLD_UNKNOWN for the default case.
+
+Fixes: e0d08a40a63b ("drm/amd/display: Add debugfs entry for reading psr state")
+Link: https://github.com/ClangBuiltLinux/linux/issues/758
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 38 ++++++++++++++++++-
+ 1 file changed, 37 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index e87124fe981c..fad7f3b7bc31 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2445,6 +2445,41 @@ bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state)
+ 	return true;
+ }
+ 
++static inline enum physical_phy_id
++transmitter_to_phy_id(enum transmitter transmitter_value)
++{
++	switch (transmitter_value) {
++	case TRANSMITTER_UNIPHY_A:
++		return PHYLD_0;
++	case TRANSMITTER_UNIPHY_B:
++		return PHYLD_1;
++	case TRANSMITTER_UNIPHY_C:
++		return PHYLD_2;
++	case TRANSMITTER_UNIPHY_D:
++		return PHYLD_3;
++	case TRANSMITTER_UNIPHY_E:
++		return PHYLD_4;
++	case TRANSMITTER_UNIPHY_F:
++		return PHYLD_5;
++	case TRANSMITTER_NUTMEG_CRT:
++		return PHYLD_6;
++	case TRANSMITTER_TRAVIS_CRT:
++		return PHYLD_7;
++	case TRANSMITTER_TRAVIS_LCD:
++		return PHYLD_8;
++	case TRANSMITTER_UNIPHY_G:
++		return PHYLD_9;
++	case TRANSMITTER_COUNT:
++		return PHYLD_COUNT;
++	case TRANSMITTER_UNKNOWN:
++		return PHYLD_UNKNOWN;
++	default:
++		WARN_ONCE(1, "Unknown transmitter value %d\n",
++			  transmitter_value);
++		return PHYLD_UNKNOWN;
++	}
++}
++
+ bool dc_link_setup_psr(struct dc_link *link,
+ 		const struct dc_stream_state *stream, struct psr_config *psr_config,
+ 		struct psr_context *psr_context)
+@@ -2515,7 +2550,8 @@ bool dc_link_setup_psr(struct dc_link *link,
+ 	/* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
+ 	psr_context->phyType = PHY_TYPE_UNIPHY;
+ 	/*PhyId is associated with the transmitter id*/
+-	psr_context->smuPhyId = link->link_enc->transmitter;
++	psr_context->smuPhyId =
++		transmitter_to_phy_id(link->link_enc->transmitter);
+ 
+ 	psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
+ 	psr_context->vsyncRateHz = div64_u64(div64_u64((stream->
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4322-drm-amdgpu-dont-schedule-jobs-while-in-reset.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4322-drm-amdgpu-dont-schedule-jobs-while-in-reset.patch
new file mode 100644
index 00000000..78986057
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4322-drm-amdgpu-dont-schedule-jobs-while-in-reset.patch
@@ -0,0 +1,50 @@
+From 70c8d49e2851d253b6d9ea62beb9a2661975b633 Mon Sep 17 00:00:00 2001
+From: Shirish S <shirish.s@amd.com>
+Date: Wed, 30 Oct 2019 14:20:46 +0530
+Subject: [PATCH 4322/4736] drm/amdgpu: dont schedule jobs while in reset
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+[Why]
+
+doing kthread_park()/unpark() from drm_sched_entity_fini
+while GPU reset is in progress defeats all the purpose of
+drm_sched_stop->kthread_park.
+If drm_sched_entity_fini->kthread_unpark() happens AFTER
+drm_sched_stop->kthread_park nothing prevents from another
+(third) thread to keep submitting job to HW which will be
+picked up by the unparked scheduler thread and try to submit
+to HW but fail because the HW ring is deactivated.
+
+[How]
+grab the reset lock before calling drm_sched_entity_fini()
+
+Signed-off-by: Shirish S <shirish.s@amd.com>
+Suggested-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+index 22097a3a5bc5..0300635f6f63 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+@@ -607,8 +607,11 @@ void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr)
+ 			continue;
+ 		}
+ 
+-		for (i = 0; i < num_entities; i++)
++		for (i = 0; i < num_entities; i++) {
++			mutex_lock(&ctx->adev->lock_reset);
+ 			drm_sched_entity_fini(&ctx->entities[0][i].entity);
++			mutex_unlock(&ctx->adev->lock_reset);
++		}
+ 	}
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4323-drm-amdgpu-Add-ucode-support-for-DMCUB.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4323-drm-amdgpu-Add-ucode-support-for-DMCUB.patch
new file mode 100644
index 00000000..3c934b9a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4323-drm-amdgpu-Add-ucode-support-for-DMCUB.patch
@@ -0,0 +1,96 @@
+From 8d04ab50151f2f903e195a2b0c5d5f6bba03664a Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 22 Oct 2019 13:07:55 -0400
+Subject: [PATCH 4323/4736] drm/amdgpu: Add ucode support for DMCUB
+
+The DMCUB is a secondary DMCU (Display MicroController Unit) that has
+its own separate firmware. It's required for DMCU support on Renoir.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 11 ++++++++++-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h |  9 +++++++++
+ 2 files changed, 19 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+index fce1f71c1cff..86cd75ca39d2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+@@ -447,6 +447,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
+ 	const struct common_firmware_header *header = NULL;
+ 	const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
+ 	const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
++	const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
+ 
+ 	if (NULL == ucode->fw)
+ 		return 0;
+@@ -460,6 +461,7 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
+ 	header = (const struct common_firmware_header *)ucode->fw->data;
+ 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
+ 	dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
++	dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
+ 
+ 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
+ 	    (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
+@@ -470,7 +472,8 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
+ 	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
+ 	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&
+ 		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM &&
+-		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV)) {
++		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV &&
++		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCUB)) {
+ 		ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
+ 
+ 		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
+@@ -506,6 +509,12 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
+ 					      le32_to_cpu(header->ucode_array_offset_bytes) +
+ 					      le32_to_cpu(dmcu_hdr->intv_offset_bytes)),
+ 		       ucode->ucode_size);
++	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCUB) {
++		ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes);
++		memcpy(ucode->kaddr,
++		       (void *)((uint8_t *)ucode->fw->data +
++				le32_to_cpu(header->ucode_array_offset_bytes)),
++		       ucode->ucode_size);
+ 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {
+ 		ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
+ 		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+index 410587b950f3..eaf2d5b9c92f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+@@ -251,6 +251,13 @@ struct dmcu_firmware_header_v1_0 {
+ 	uint32_t intv_size_bytes;  /* size of interrupt vectors, in bytes */
+ };
+ 
++/* version_major=1, version_minor=0 */
++struct dmcub_firmware_header_v1_0 {
++	struct common_firmware_header header;
++	uint32_t inst_const_bytes; /* size of instruction region, in bytes */
++	uint32_t bss_data_bytes; /* size of bss/data region, in bytes */
++};
++
+ /* header is fixed size */
+ union amdgpu_firmware_header {
+ 	struct common_firmware_header common;
+@@ -268,6 +275,7 @@ union amdgpu_firmware_header {
+ 	struct sdma_firmware_header_v1_1 sdma_v1_1;
+ 	struct gpu_info_firmware_header_v1_0 gpu_info;
+ 	struct dmcu_firmware_header_v1_0 dmcu;
++	struct dmcub_firmware_header_v1_0 dmcub;
+ 	uint8_t raw[0x100];
+ };
+ 
+@@ -307,6 +315,7 @@ enum AMDGPU_UCODE_ID {
+ 	AMDGPU_UCODE_ID_DMCU_INTV,
+ 	AMDGPU_UCODE_ID_VCN0_RAM,
+ 	AMDGPU_UCODE_ID_VCN1_RAM,
++	AMDGPU_UCODE_ID_DMCUB,
+ 	AMDGPU_UCODE_ID_MAXIMUM,
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4324-drm-amdgpu-Add-PSP-loading-support-for-DMCUB-ucode.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4324-drm-amdgpu-Add-PSP-loading-support-for-DMCUB-ucode.patch
new file mode 100644
index 00000000..b87dfd62
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4324-drm-amdgpu-Add-PSP-loading-support-for-DMCUB-ucode.patch
@@ -0,0 +1,35 @@
+From 2e1b45470e9e9a97e5036f14f5e912d4c1f1a94b Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 22 Oct 2019 13:24:00 -0400
+Subject: [PATCH 4324/4736] drm/amdgpu: Add PSP loading support for DMCUB ucode
+
+DMCUB ucode requires secure loading through PSP. This is already
+supported in PSP as GFX_FW_TYPE_DMUB, it just needs to be mapped from
+AMDGPU_UCODE_ID_DMCUB to GFX_FW_TYPE_DMUB.
+
+DMUB is a shorthand name for DMCUB and can be used interchangeably.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 8a1960106004..a33d1ed6a096 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1287,6 +1287,9 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
+ 	case AMDGPU_UCODE_ID_VCN1_RAM:
+ 		*type = GFX_FW_TYPE_VCN1_RAM;
+ 		break;
++	case AMDGPU_UCODE_ID_DMCUB:
++		*type = GFX_FW_TYPE_DMUB;
++		break;
+ 	case AMDGPU_UCODE_ID_MAXIMUM:
+ 	default:
+ 		return -EINVAL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4325-drm-amd-display-Drop-DMCUB-from-DCN21-resources.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4325-drm-amd-display-Drop-DMCUB-from-DCN21-resources.patch
new file mode 100644
index 00000000..ab751029
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4325-drm-amd-display-Drop-DMCUB-from-DCN21-resources.patch
@@ -0,0 +1,80 @@
+From b9e226bd5d43b487569ff550ebdb0d9820b8bf3d Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Fri, 25 Oct 2019 12:46:52 -0400
+Subject: [PATCH 4325/4736] drm/amd/display: Drop DMCUB from DCN21 resources
+
+The interface to the DMCUB won't be through DC itself. DC will instead
+call into the DMUB interface introduced with a future change.
+
+The CONFIG_DRM_AMD_DC_DMUB defines will still be used for now but will
+be dropped at the end of the series.
+
+Since this define was never configurable in the first place this code
+wasn't used.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 31 -------------------
+ 1 file changed, 31 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 987897748174..47367446f64c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -373,20 +373,6 @@ static const struct dce_abm_mask abm_mask = {
+ 		ABM_MASK_SH_LIST_DCN20(_MASK)
+ };
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+-static const struct dcn21_dmcub_registers dmcub_regs = {
+-		DMCUB_REG_LIST_DCN()
+-};
+-
+-static const struct dcn21_dmcub_shift dmcub_shift = {
+-		DMCUB_COMMON_MASK_SH_LIST_BASE(__SHIFT)
+-};
+-
+-static const struct dcn21_dmcub_mask dmcub_mask = {
+-		DMCUB_COMMON_MASK_SH_LIST_BASE(_MASK)
+-};
+-#endif
+-
+ #define audio_regs(id)\
+ [id] = {\
+ 		AUD_COMMON_REG_LIST(id)\
+@@ -970,11 +956,6 @@ static void destruct(struct dcn21_resource_pool *pool)
+ 	if (pool->base.dmcu != NULL)
+ 		dce_dmcu_destroy(&pool->base.dmcu);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+-	if (pool->base.dmcub != NULL)
+-		dcn21_dmcub_destroy(&pool->base.dmcub);
+-#endif
+-
+ 	if (pool->base.dccg != NULL)
+ 		dcn_dccg_destroy(&pool->base.dccg);
+ 
+@@ -1787,18 +1768,6 @@ static bool construct(
+ 		goto create_fail;
+ 	}
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+-	pool->base.dmcub = dcn21_dmcub_create(ctx,
+-			&dmcub_regs,
+-			&dmcub_shift,
+-			&dmcub_mask);
+-	if (pool->base.dmcub == NULL) {
+-		dm_error("DC: failed to create dmcub!\n");
+-		BREAK_TO_DEBUGGER();
+-		goto create_fail;
+-	}
+-#endif
+-
+ 	pool->base.pp_smu = dcn21_pp_smu_create(ctx);
+ 
+ 	num_pipes = dcn2_1_ip.max_num_dpp;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4326-drm-amd-display-Add-the-DMUB-service.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4326-drm-amd-display-Add-the-DMUB-service.patch
new file mode 100644
index 00000000..0ea61b42
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4326-drm-amd-display-Add-the-DMUB-service.patch
@@ -0,0 +1,2227 @@
+From cee54bb1116f95c9283ccb627465db4f030f457f Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Fri, 25 Oct 2019 11:28:35 -0400
+Subject: [PATCH 4326/4736] drm/amd/display: Add the DMUB service
+
+The DMUB service is the interface to the DMCUB.
+
+It's required to support Renoir features so it will be enabled and
+compiled automatically when the Renoir display engine is enabled via
+CONFIG_DRM_AMD_DC_DCN2_1.
+
+DMUB code will initially be guarded by CONFIG_DRM_AMD_DC_DMUB and later
+switched to CONFIG_DRM_AMD_DC_DCN2_1 with the config option dropped.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/Kconfig           |   6 +
+ drivers/gpu/drm/amd/display/Makefile          |   8 +
+ .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 256 +++++++++
+ .../gpu/drm/amd/display/dmub/inc/dmub_rb.h    | 129 +++++
+ .../gpu/drm/amd/display/dmub/inc/dmub_srv.h   | 505 ++++++++++++++++++
+ .../amd/display/dmub/inc/dmub_trace_buffer.h  |  51 ++
+ .../gpu/drm/amd/display/dmub/inc/dmub_types.h |  64 +++
+ drivers/gpu/drm/amd/display/dmub/src/Makefile |  29 +
+ .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 137 +++++
+ .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h |  62 +++
+ .../gpu/drm/amd/display/dmub/src/dmub_dcn21.c | 126 +++++
+ .../gpu/drm/amd/display/dmub/src/dmub_dcn21.h |  45 ++
+ .../gpu/drm/amd/display/dmub/src/dmub_reg.c   | 109 ++++
+ .../gpu/drm/amd/display/dmub/src/dmub_reg.h   | 120 +++++
+ .../gpu/drm/amd/display/dmub/src/dmub_srv.c   | 415 ++++++++++++++
+ 15 files changed, 2062 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_rb.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_types.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/src/Makefile
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+
+diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
+index 9eae7c67ceb5..d9ee189aebf0 100644
+--- a/drivers/gpu/drm/amd/display/Kconfig
++++ b/drivers/gpu/drm/amd/display/Kconfig
+@@ -29,6 +29,7 @@ config DRM_AMD_DC_DCN2_1
+ 	bool "DCN 2.1 family"
+ 	depends on DRM_AMD_DC && X86
+ 	depends on DRM_AMD_DC_DCN2_0
++	select DRM_AMD_DC_DMUB
+ 	help
+ 	  Choose this option if you want to have
+ 	  Renoir support for display engine
+@@ -51,6 +52,11 @@ config DRM_AMD_DC_HDCP
+ 	 if you want to support
+ 	 HDCP authentication
+ 
++config DRM_AMD_DC_DMUB
++        def_bool n
++        help
++          DMUB support for display engine
++
+ config DEBUG_KERNEL_DC
+ 	bool "Enable kgdb break in DC"
+ 	depends on DRM_AMD_DC
+diff --git a/drivers/gpu/drm/amd/display/Makefile b/drivers/gpu/drm/amd/display/Makefile
+index 36b3d6a5d04d..3c7332be4a89 100644
+--- a/drivers/gpu/drm/amd/display/Makefile
++++ b/drivers/gpu/drm/amd/display/Makefile
+@@ -38,6 +38,10 @@ ifdef CONFIG_DRM_AMD_DC_HDCP
+ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/hdcp
+ endif
+ 
++ifdef CONFIG_DRM_AMD_DC_DMUB
++subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dmub/inc
++endif
++
+ #TODO: remove when Timing Sync feature is complete
+ subdir-ccflags-y += -DBUILD_FEATURE_TIMING_SYNC=0
+ 
+@@ -47,6 +51,10 @@ ifdef CONFIG_DRM_AMD_DC_HDCP
+ DAL_LIBS += modules/hdcp
+ endif
+ 
++ifdef CONFIG_DRM_AMD_DC_DMUB
++DAL_LIBS += dmub/src
++endif
++
+ AMD_DAL = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/,$(DAL_LIBS)))
+ 
+ include $(AMD_DAL)
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+new file mode 100644
+index 000000000000..b25f92e3280d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+@@ -0,0 +1,256 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_CMD_H_
++#define _DMUB_CMD_H_
++
++#include "dmub_types.h"
++#include "atomfirmware.h"
++
++#define DMUB_RB_CMD_SIZE 64
++#define DMUB_RB_MAX_ENTRY 128
++#define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
++#define REG_SET_MASK 0xFFFF
++
++enum dmub_cmd_type {
++	DMUB_CMD__NULL,
++	DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE,
++	DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ,
++	DMUB_CMD__REG_SEQ_BURST_WRITE,
++	DMUB_CMD__REG_REG_WAIT,
++	DMUB_CMD__DIGX_ENCODER_CONTROL,
++	DMUB_CMD__SET_PIXEL_CLOCK,
++	DMUB_CMD__ENABLE_DISP_POWER_GATING,
++	DMUB_CMD__DPPHY_INIT,
++	DMUB_CMD__DIG1_TRANSMITTER_CONTROL,
++
++	// PSR
++	DMUB_CMD__PSR_ENABLE,
++	DMUB_CMD__PSR_DISABLE,
++	DMUB_CMD__PSR_COPY_SETTINGS,
++	DMUB_CMD__PSR_SET_LEVEL,
++};
++
++#pragma pack(push, 1)
++
++struct dmub_cmd_header {
++	enum dmub_cmd_type type : 8;
++	unsigned int reserved0 : 16;
++	unsigned int payload_bytes : 6;  /* up to 60 bytes */
++	unsigned int reserved : 2;
++};
++
++/*
++ * Read modify write
++ *
++ * 60 payload bytes can hold up to 5 sets of read modify writes,
++ * each take 3 dwords.
++ *
++ * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
++ *
++ * modify_mask = 0xffff'ffff means all fields are going to be updated.  in this case
++ * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
++ */
++struct dmub_cmd_read_modify_write_sequence {
++	uint32_t addr;
++	uint32_t modify_mask;
++	uint32_t modify_value;
++};
++
++#define DMUB_READ_MODIFY_WRITE_SEQ__MAX		5
++struct dmub_rb_cmd_read_modify_write {
++	struct dmub_cmd_header header;  // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE
++	struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
++};
++
++/*
++ * Update a register with specified masks and values sequeunce
++ *
++ * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
++ *
++ * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
++ *
++ *
++ * USE CASE:
++ *   1. auto-increment register where additional read would update pointer and produce wrong result
++ *   2. toggle a bit without read in the middle
++ */
++
++struct dmub_cmd_reg_field_update_sequence {
++	uint32_t modify_mask;  // 0xffff'ffff to skip initial read
++	uint32_t modify_value;
++};
++
++#define DMUB_REG_FIELD_UPDATE_SEQ__MAX		7
++
++struct dmub_rb_cmd_reg_field_update_sequence {
++	struct dmub_cmd_header header;
++	uint32_t addr;
++	struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
++};
++
++
++/*
++ * Burst write
++ *
++ * support use case such as writing out LUTs.
++ *
++ * 60 payload bytes can hold up to 14 values to write to given address
++ *
++ * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
++ */
++#define DMUB_BURST_WRITE_VALUES__MAX  14
++struct dmub_rb_cmd_burst_write {
++	struct dmub_cmd_header header;  // type = DMUB_CMD__REG_SEQ_BURST_WRITE
++	uint32_t addr;
++	uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
++};
++
++
++struct dmub_rb_cmd_common {
++	struct dmub_cmd_header header;
++	uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
++};
++
++struct dmub_cmd_reg_wait_data {
++	uint32_t addr;
++	uint32_t mask;
++	uint32_t condition_field_value;
++	uint32_t time_out_us;
++};
++
++struct dmub_rb_cmd_reg_wait {
++	struct dmub_cmd_header header;
++	struct dmub_cmd_reg_wait_data reg_wait;
++};
++
++struct dmub_cmd_digx_encoder_control_data {
++	union dig_encoder_control_parameters_v1_5 dig;
++};
++
++struct dmub_rb_cmd_digx_encoder_control {
++	struct dmub_cmd_header header;
++	struct dmub_cmd_digx_encoder_control_data encoder_control;
++};
++
++struct dmub_cmd_set_pixel_clock_data {
++	struct set_pixel_clock_parameter_v1_7 clk;
++};
++
++struct dmub_rb_cmd_set_pixel_clock {
++	struct dmub_cmd_header header;
++	struct dmub_cmd_set_pixel_clock_data pixel_clock;
++};
++
++struct dmub_cmd_enable_disp_power_gating_data {
++	struct enable_disp_power_gating_parameters_v2_1 pwr;
++};
++
++struct dmub_rb_cmd_enable_disp_power_gating {
++	struct dmub_cmd_header header;
++	struct dmub_cmd_enable_disp_power_gating_data power_gating;
++};
++
++struct dmub_cmd_dig1_transmitter_control_data {
++	struct dig_transmitter_control_parameters_v1_6 dig;
++};
++
++struct dmub_rb_cmd_dig1_transmitter_control {
++	struct dmub_cmd_header header;
++	struct dmub_cmd_dig1_transmitter_control_data transmitter_control;
++};
++
++struct dmub_rb_cmd_dpphy_init {
++	struct dmub_cmd_header header;
++	uint8_t reserved[60];
++};
++
++struct dmub_cmd_psr_copy_settings_data {
++	uint32_t reg1;
++	uint32_t reg2;
++	uint32_t reg3;
++};
++
++struct dmub_rb_cmd_psr_copy_settings {
++	struct dmub_cmd_header header;
++	struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
++};
++
++struct dmub_cmd_psr_set_level_data {
++	uint16_t psr_level;
++};
++
++struct dmub_rb_cmd_psr_set_level {
++	struct dmub_cmd_header header;
++	struct dmub_cmd_psr_set_level_data psr_set_level_data;
++};
++
++struct dmub_rb_cmd_psr_disable {
++	struct dmub_cmd_header header;
++};
++
++struct dmub_rb_cmd_psr_enable {
++	struct dmub_cmd_header header;
++};
++
++struct dmub_cmd_psr_notify_vblank_data {
++	uint32_t vblank_int; // Which vblank interrupt was triggered
++};
++
++struct dmub_rb_cmd_notify_vblank {
++	struct dmub_cmd_header header;
++	struct dmub_cmd_psr_notify_vblank_data psr_notify_vblank_data;
++};
++
++struct dmub_cmd_psr_notify_static_state_data {
++	uint32_t ss_int;   // Which static screen interrupt was triggered
++	uint32_t ss_enter; // Enter (1) or exit (0) static screen
++};
++
++struct dmub_rb_cmd_psr_notify_static_state {
++	struct dmub_cmd_header header;
++	struct dmub_cmd_psr_notify_static_state_data psr_notify_static_state_data;
++};
++
++union dmub_rb_cmd {
++	struct dmub_rb_cmd_read_modify_write read_modify_write;
++	struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
++	struct dmub_rb_cmd_burst_write burst_write;
++	struct dmub_rb_cmd_reg_wait reg_wait;
++	struct dmub_rb_cmd_common cmd_common;
++	struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
++	struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
++	struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
++	struct dmub_rb_cmd_dpphy_init dpphy_init;
++	struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
++	struct dmub_rb_cmd_psr_enable psr_enable;
++	struct dmub_rb_cmd_psr_disable psr_disable;
++	struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
++	struct dmub_rb_cmd_psr_set_level psr_set_level;
++};
++
++#pragma pack(pop)
++
++#endif /* _DMUB_CMD_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_rb.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_rb.h
+new file mode 100644
+index 000000000000..ac22744eaa94
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_rb.h
+@@ -0,0 +1,129 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_RB_H_
++#define _DMUB_RB_H_
++
++#include "dmub_types.h"
++#include "dmub_cmd.h"
++
++#if defined(__cplusplus)
++extern "C" {
++#endif
++
++struct dmub_cmd_header;
++
++struct dmub_rb_init_params {
++	void *ctx;
++	void *base_address;
++	uint32_t capacity;
++};
++
++struct dmub_rb {
++	void *base_address;
++	uint32_t data_count;
++	uint32_t rptr;
++	uint32_t wrpt;
++	uint32_t capacity;
++
++	void *ctx;
++	void *dmub;
++};
++
++
++static inline bool dmub_rb_empty(struct dmub_rb *rb)
++{
++	return (rb->wrpt == rb->rptr);
++}
++
++static inline bool dmub_rb_full(struct dmub_rb *rb)
++{
++	uint32_t data_count;
++
++	if (rb->wrpt >= rb->rptr)
++		data_count = rb->wrpt - rb->rptr;
++	else
++		data_count = rb->capacity - (rb->rptr - rb->wrpt);
++
++	return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
++}
++
++static inline bool dmub_rb_push_front(struct dmub_rb *rb,
++				      const struct dmub_cmd_header *cmd)
++{
++	uint8_t *wt_ptr = (uint8_t *)(rb->base_address) + rb->wrpt;
++
++	if (dmub_rb_full(rb))
++		return false;
++
++	dmub_memcpy(wt_ptr, cmd, DMUB_RB_CMD_SIZE);
++	rb->wrpt += DMUB_RB_CMD_SIZE;
++
++	if (rb->wrpt >= rb->capacity)
++		rb->wrpt %= rb->capacity;
++
++	return true;
++}
++
++static inline bool dmub_rb_front(struct dmub_rb *rb,
++				 struct dmub_cmd_header *cmd)
++{
++	uint8_t *rd_ptr = (uint8_t *)rb->base_address + rb->rptr;
++
++	if (dmub_rb_empty(rb))
++		return false;
++
++	dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
++
++	return true;
++}
++
++static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
++{
++	if (dmub_rb_empty(rb))
++		return false;
++
++	rb->rptr += DMUB_RB_CMD_SIZE;
++
++	if (rb->rptr >= rb->capacity)
++		rb->rptr %= rb->capacity;
++
++	return true;
++}
++
++static inline void dmub_rb_init(struct dmub_rb *rb,
++				struct dmub_rb_init_params *init_params)
++{
++	rb->base_address = init_params->base_address;
++	rb->capacity = init_params->capacity;
++	rb->rptr = 0;
++	rb->wrpt = 0;
++}
++
++#if defined(__cplusplus)
++}
++#endif
++
++#endif /* _DMUB_RB_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+new file mode 100644
+index 000000000000..aa8f0396616d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+@@ -0,0 +1,505 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_SRV_H_
++#define _DMUB_SRV_H_
++
++/**
++ * DOC: DMUB interface and operation
++ *
++ * DMUB is the interface to the display DMCUB microcontroller on DCN hardware.
++ * It delegates hardware initialization and command submission to the
++ * microcontroller. DMUB is the shortname for DMCUB.
++ *
++ * This interface is not thread-safe. Ensure that all access to the interface
++ * is properly synchronized by the caller.
++ *
++ * Initialization and usage of the DMUB service should be done in the
++ * steps given below:
++ *
++ * 1. dmub_srv_create()
++ * 2. dmub_srv_has_hw_support()
++ * 3. dmub_srv_calc_region_info()
++ * 4. dmub_srv_hw_init()
++ *
++ * The call to dmub_srv_create() is required to use the server.
++ *
++ * The calls to dmub_srv_has_hw_support() and dmub_srv_calc_region_info()
++ * are helpers to query cache window size and allocate framebuffer(s)
++ * for the cache windows.
++ *
++ * The call to dmub_srv_hw_init() programs the DMCUB registers to prepare
++ * for command submission. Commands can be queued via dmub_srv_cmd_queue()
++ * and executed via dmub_srv_cmd_execute().
++ *
++ * If the queue is full the dmub_srv_wait_for_idle() call can be used to
++ * wait until the queue has been cleared.
++ *
++ * Destroying the DMUB service can be done by calling dmub_srv_destroy().
++ * This does not clear DMUB hardware state, only software state.
++ *
++ * The interface is intended to be standalone and should not depend on any
++ * other component within DAL.
++ */
++
++#include "dmub_types.h"
++#include "dmub_cmd.h"
++#include "dmub_rb.h"
++
++#if defined(__cplusplus)
++extern "C" {
++#endif
++
++/* Forward declarations */
++struct dmub_srv;
++struct dmub_cmd_header;
++struct dmcu;
++
++/* enum dmub_status - return code for dmcub functions */
++enum dmub_status {
++	DMUB_STATUS_OK = 0,
++	DMUB_STATUS_NO_CTX,
++	DMUB_STATUS_QUEUE_FULL,
++	DMUB_STATUS_TIMEOUT,
++	DMUB_STATUS_INVALID,
++};
++
++/* enum dmub_asic - dmub asic identifier */
++enum dmub_asic {
++	DMUB_ASIC_NONE = 0,
++	DMUB_ASIC_DCN20,
++	DMUB_ASIC_DCN21,
++	DMUB_ASIC_MAX,
++};
++
++/* enum dmub_window_id - dmub window identifier */
++enum dmub_window_id {
++	DMUB_WINDOW_0_INST_CONST = 0,
++	DMUB_WINDOW_1_STACK,
++	DMUB_WINDOW_2_BSS_DATA,
++	DMUB_WINDOW_3_VBIOS,
++	DMUB_WINDOW_4_MAILBOX,
++	DMUB_WINDOW_5_TRACEBUFF,
++	DMUB_WINDOW_6_RESERVED,
++	DMUB_WINDOW_7_RESERVED,
++	DMUB_WINDOW_TOTAL,
++};
++
++/**
++ * struct dmub_region - dmub hw memory region
++ * @base: base address for region, must be 256 byte aligned
++ * @top: top address for region
++ */
++struct dmub_region {
++	uint32_t base;
++	uint32_t top;
++};
++
++/**
++ * struct dmub_window - dmub hw cache window
++ * @off: offset to the fb memory in gpu address space
++ * @r: region in uc address space for cache window
++ */
++struct dmub_window {
++	union dmub_addr offset;
++	struct dmub_region region;
++};
++
++/**
++ * struct dmub_fb - defines a dmub framebuffer memory region
++ * @cpu_addr: cpu virtual address for the region, NULL if invalid
++ * @gpu_addr: gpu virtual address for the region, NULL if invalid
++ * @size: size of the region in bytes, zero if invalid
++ */
++struct dmub_fb {
++	void *cpu_addr;
++	uint64_t gpu_addr;
++	uint32_t size;
++};
++
++/**
++ * struct dmub_srv_region_params - params used for calculating dmub regions
++ * @inst_const_size: size of the fw inst const section
++ * @bss_data_size: size of the fw bss data section
++ * @vbios_size: size of the vbios data
++ */
++struct dmub_srv_region_params {
++	uint32_t inst_const_size;
++	uint32_t bss_data_size;
++	uint32_t vbios_size;
++};
++
++/**
++ * struct dmub_srv_region_info - output region info from the dmub service
++ * @fb_size: required minimum fb size for all regions, aligned to 4096 bytes
++ * @num_regions: number of regions used by the dmub service
++ * @regions: region info
++ *
++ * The regions are aligned such that they can be all placed within the
++ * same framebuffer but they can also be placed into different framebuffers.
++ *
++ * The size of each region can be calculated by the caller:
++ * size = reg.top - reg.base
++ *
++ * Care must be taken when performing custom allocations to ensure that each
++ * region base address is 256 byte aligned.
++ */
++struct dmub_srv_region_info {
++	uint32_t fb_size;
++	uint8_t num_regions;
++	struct dmub_region regions[DMUB_WINDOW_TOTAL];
++};
++
++/**
++ * struct dmub_srv_fb_params - parameters used for driver fb setup
++ * @region_info: region info calculated by dmub service
++ * @cpu_addr: base cpu address for the framebuffer
++ * @gpu_addr: base gpu virtual address for the framebuffer
++ */
++struct dmub_srv_fb_params {
++	const struct dmub_srv_region_info *region_info;
++	void *cpu_addr;
++	uint64_t gpu_addr;
++};
++
++/**
++ * struct dmub_srv_fb_info - output fb info from the dmub service
++ * @num_fbs: number of required dmub framebuffers
++ * @fbs: fb data for each region
++ *
++ * Output from the dmub service helper that can be used by the
++ * driver to prepare dmub_fb that can be passed into the dmub
++ * hw init service.
++ *
++ * Assumes that all regions are within the same framebuffer
++ * and have been setup according to the region_info generated
++ * by the dmub service.
++ */
++struct dmub_srv_fb_info {
++	uint8_t num_fb;
++	struct dmub_fb fb[DMUB_WINDOW_TOTAL];
++};
++
++/**
++ * struct dmub_srv_base_funcs - Driver specific base callbacks
++ */
++struct dmub_srv_base_funcs {
++	/**
++	 * @reg_read:
++	 *
++	 * Hook for reading a register.
++	 *
++	 * Return: The 32-bit register value from the given address.
++	 */
++	uint32_t (*reg_read)(void *ctx, uint32_t address);
++
++	/**
++	 * @reg_write:
++	 *
++	 * Hook for writing a value to the register specified by address.
++	 */
++	void (*reg_write)(void *ctx, uint32_t address, uint32_t value);
++};
++
++/**
++ * struct dmub_srv_hw_funcs - hardware sequencer funcs for dmub
++ */
++struct dmub_srv_hw_funcs {
++	/* private: internal use only */
++
++	void (*reset)(struct dmub_srv *dmub);
++
++	void (*reset_release)(struct dmub_srv *dmub);
++
++	void (*backdoor_load)(struct dmub_srv *dmub,
++			      const struct dmub_window *cw0,
++			      const struct dmub_window *cw1);
++
++	void (*setup_windows)(struct dmub_srv *dmub,
++			      const struct dmub_window *cw2,
++			      const struct dmub_window *cw3,
++			      const struct dmub_window *cw4,
++				  const struct dmub_window *cw5);
++
++	void (*setup_mailbox)(struct dmub_srv *dmub,
++			      const struct dmub_region *inbox1);
++
++	uint32_t (*get_inbox1_rptr)(struct dmub_srv *dmub);
++
++	void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);
++
++	bool (*is_supported)(struct dmub_srv *dmub);
++
++	bool (*is_phy_init)(struct dmub_srv *dmub);
++
++	bool (*is_auto_load_done)(struct dmub_srv *dmub);
++};
++
++/**
++ * struct dmub_srv_create_params - params for dmub service creation
++ * @base_funcs: driver supplied base routines
++ * @hw_funcs: optional overrides for hw funcs
++ * @user_ctx: context data for callback funcs
++ * @asic: driver supplied asic
++ * @is_virtual: false for hw support only
++ */
++struct dmub_srv_create_params {
++	struct dmub_srv_base_funcs funcs;
++	struct dmub_srv_hw_funcs *hw_funcs;
++	void *user_ctx;
++	enum dmub_asic asic;
++	bool is_virtual;
++};
++
++/*
++ * struct dmub_srv_hw_params - params for dmub hardware initialization
++ * @fb: framebuffer info for each region
++ * @fb_base: base of the framebuffer aperture
++ * @fb_offset: offset of the framebuffer aperture
++ * @psp_version: psp version to pass for DMCU init
++ */
++struct dmub_srv_hw_params {
++	struct dmub_fb *fb[DMUB_WINDOW_TOTAL];
++	uint64_t fb_base;
++	uint64_t fb_offset;
++	uint32_t psp_version;
++};
++
++/**
++ * struct dmub_srv - software state for dmcub
++ * @asic: dmub asic identifier
++ * @user_ctx: user provided context for the dmub_srv
++ * @is_virtual: false if hardware support only
++ */
++struct dmub_srv {
++	enum dmub_asic asic;
++	void *user_ctx;
++	bool is_virtual;
++
++	/* private: internal use only */
++	struct dmub_srv_base_funcs funcs;
++	struct dmub_srv_hw_funcs hw_funcs;
++	struct dmub_rb inbox1_rb;
++
++	bool sw_init;
++	bool hw_init;
++
++	uint64_t fb_base;
++	uint64_t fb_offset;
++	uint32_t psp_version;
++};
++
++/**
++ * dmub_srv_create() - creates the DMUB service.
++ * @dmub: the dmub service
++ * @params: creation parameters for the service
++ *
++ * Return:
++ *   DMUB_STATUS_OK - success
++ *   DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_create(struct dmub_srv *dmub,
++				 const struct dmub_srv_create_params *params);
++
++/**
++ * dmub_srv_destroy() - destroys the DMUB service.
++ * @dmub: the dmub service
++ */
++void dmub_srv_destroy(struct dmub_srv *dmub);
++
++/**
++ * dmub_srv_calc_region_info() - retreives region info from the dmub service
++ * @dmub: the dmub service
++ * @params: parameters used to calculate region locations
++ * @info_out: the output region info from dmub
++ *
++ * Calculates the base and top address for all relevant dmub regions
++ * using the parameters given (if any).
++ *
++ * Return:
++ *   DMUB_STATUS_OK - success
++ *   DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status
++dmub_srv_calc_region_info(struct dmub_srv *dmub,
++			  const struct dmub_srv_region_params *params,
++			  struct dmub_srv_region_info *out);
++
++/**
++ * dmub_srv_calc_region_info() - retreives fb info from the dmub service
++ * @dmub: the dmub service
++ * @params: parameters used to calculate fb locations
++ * @info_out: the output fb info from dmub
++ *
++ * Calculates the base and top address for all relevant dmub regions
++ * using the parameters given (if any).
++ *
++ * Return:
++ *   DMUB_STATUS_OK - success
++ *   DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub,
++				       const struct dmub_srv_fb_params *params,
++				       struct dmub_srv_fb_info *out);
++
++/**
++ * dmub_srv_has_hw_support() - returns hw support state for dmcub
++ * @dmub: the dmub service
++ * @is_supported: hw support state
++ *
++ * Queries the hardware for DMCUB support and returns the result.
++ *
++ * Can be called before dmub_srv_hw_init().
++ *
++ * Return:
++ *   DMUB_STATUS_OK - success
++ *   DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
++					 bool *is_supported);
++
++/**
++ * dmub_srv_hw_init() - initializes the underlying DMUB hardware
++ * @dmub: the dmub service
++ * @params: params for hardware initialization
++ *
++ * Resets the DMUB hardware and performs backdoor loading of the
++ * required cache regions based on the input framebuffer regions.
++ *
++ * Return:
++ *   DMUB_STATUS_OK - success
++ *   DMUB_STATUS_NO_CTX - dmcub context not initialized
++ *   DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
++				  const struct dmub_srv_hw_params *params);
++
++/**
++ * dmub_srv_cmd_queue() - queues a command to the DMUB
++ * @dmub: the dmub service
++ * @cmd: the command to queue
++ *
++ * Queues a command to the DMUB service but does not begin execution
++ * immediately.
++ *
++ * Return:
++ *   DMUB_STATUS_OK - success
++ *   DMUB_STATUS_QUEUE_FULL - no remaining room in queue
++ *   DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,
++				    const struct dmub_cmd_header *cmd);
++
++/**
++ * dmub_srv_cmd_execute() - Executes a queued sequence to the dmub
++ * @dmub: the dmub service
++ *
++ * Begins exeuction of queued commands on the dmub.
++ *
++ * Return:
++ *   DMUB_STATUS_OK - success
++ *   DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub);
++
++/**
++ * dmub_srv_cmd_submit() - submits a command to the DMUB immediately
++ * @dmub: the dmub service
++ * @cmd: the command to submit
++ * @timeout_us: the maximum number of microseconds to wait
++ *
++ * Submits a command to the DMUB with an optional timeout.
++ * If timeout_us is given then the service will attempt to
++ * resubmit for the given number of microseconds.
++ *
++ * Return:
++ *   DMUB_STATUS_OK - success
++ *   DMUB_STATUS_TIMEOUT - wait for submit timed out
++ *   DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_cmd_submit(struct dmub_srv *dmub,
++				     const struct dmub_cmd_header *cmd,
++				     uint32_t timeout_us);
++
++/**
++ * dmub_srv_wait_for_auto_load() - Waits for firmware auto load to complete
++ * @dmub: the dmub service
++ * @timeout_us: the maximum number of microseconds to wait
++ *
++ * Waits until firmware has been autoloaded by the DMCUB. The maximum
++ * wait time is given in microseconds to prevent spinning forever.
++ *
++ * On ASICs without firmware autoload support this function will return
++ * immediately.
++ *
++ * Return:
++ *   DMUB_STATUS_OK - success
++ *   DMUB_STATUS_TIMEOUT - wait for phy init timed out
++ *   DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
++					     uint32_t timeout_us);
++
++/**
++ * dmub_srv_wait_for_phy_init() - Waits for DMUB PHY init to complete
++ * @dmub: the dmub service
++ * @timeout_us: the maximum number of microseconds to wait
++ *
++ * Waits until the PHY has been initialized by the DMUB. The maximum
++ * wait time is given in microseconds to prevent spinning forever.
++ *
++ * On ASICs without PHY init support this function will return
++ * immediately.
++ *
++ * Return:
++ *   DMUB_STATUS_OK - success
++ *   DMUB_STATUS_TIMEOUT - wait for phy init timed out
++ *   DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
++					    uint32_t timeout_us);
++
++/**
++ * dmub_srv_wait_for_idle() - Waits for the DMUB to be idle
++ * @dmub: the dmub service
++ * @timeout_us: the maximum number of microseconds to wait
++ *
++ * Waits until the DMUB buffer is empty and all commands have
++ * finished processing. The maximum wait time is given in
++ * microseconds to prevent spinning forever.
++ *
++ * Return:
++ *   DMUB_STATUS_OK - success
++ *   DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out
++ *   DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
++					uint32_t timeout_us);
++
++#if defined(__cplusplus)
++}
++#endif
++
++#endif /* _DMUB_SRV_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
+new file mode 100644
+index 000000000000..9707706ba8ce
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
+@@ -0,0 +1,51 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++#ifndef _DMUB_TRACE_BUFFER_H_
++#define _DMUB_TRACE_BUFFER_H_
++
++#include "dmub_types.h"
++
++#define LOAD_DMCU_FW	1
++#define LOAD_PHY_FW	2
++
++struct dmcub_trace_buf_entry {
++	uint32_t trace_code;
++	uint32_t tick_count;
++	uint32_t param0;
++	uint32_t param1;
++};
++
++#define TRACE_BUF_SIZE (1024) //1 kB
++#define PERF_TRACE_MAX_ENTRY ((TRACE_BUF_SIZE - 8)/sizeof(struct dmcub_trace_buf_entry))
++
++struct dmcub_trace_buf {
++	uint32_t entry_count;
++	uint32_t clk_freq;
++	struct dmcub_trace_buf_entry entries[PERF_TRACE_MAX_ENTRY];
++};
++
++
++
++#endif /* _DMUB_TRACE_BUFFER_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_types.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_types.h
+new file mode 100644
+index 000000000000..41d524b0db2f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_types.h
+@@ -0,0 +1,64 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_TYPES_H_
++#define _DMUB_TYPES_H_
++
++/* Basic type definitions. */
++#include <asm/byteorder.h>
++#include <linux/types.h>
++#include <linux/string.h>
++#include <linux/delay.h>
++#include <stdarg.h>
++
++#if defined(__cplusplus)
++extern "C" {
++#endif
++
++#ifndef dmub_memcpy
++#define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
++#endif
++
++#ifndef dmub_memset
++#define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
++#endif
++
++#ifndef dmub_udelay
++#define dmub_udelay(microseconds) udelay(microseconds)
++#endif
++
++union dmub_addr {
++	struct {
++		uint32_t low_part;
++		uint32_t high_part;
++	} u;
++	uint64_t quad_part;
++};
++
++#if defined(__cplusplus)
++}
++#endif
++
++#endif /* _DMUB_TYPES_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile
+new file mode 100644
+index 000000000000..f3b844f474fd
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile
+@@ -0,0 +1,29 @@
++#
++# Copyright 2019 Advanced Micro Devices, Inc.
++#
++# Permission is hereby granted, free of charge, to any person obtaining a
++# copy of this software and associated documentation files (the "Software"),
++# to deal in the Software without restriction, including without limitation
++# the rights to use, copy, modify, merge, publish, distribute, sublicense,
++# and/or sell copies of the Software, and to permit persons to whom the
++# Software is furnished to do so, subject to the following conditions:
++#
++# The above copyright notice and this permission notice shall be included in
++# all copies or substantial portions of the Software.
++#
++# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++# OTHER DEALINGS IN THE SOFTWARE.
++#
++
++ifdef CONFIG_DRM_AMD_DC_DMUB
++DMUB = dmub_srv.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o
++
++AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))
++
++AMD_DISPLAY_FILES += $(AMD_DAL_DMUB)
++endif
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+new file mode 100644
+index 000000000000..236a4156bbe1
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+@@ -0,0 +1,137 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "../inc/dmub_srv.h"
++#include "dmub_reg.h"
++
++#include "dcn/dcn_2_0_0_offset.h"
++#include "dcn/dcn_2_0_0_sh_mask.h"
++#include "soc15_hw_ip.h"
++#include "vega10_ip_offset.h"
++
++#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
++#define CTX dmub
++
++void dmub_dcn20_reset(struct dmub_srv *dmub)
++{
++	REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1);
++	REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
++}
++
++void dmub_dcn20_reset_release(struct dmub_srv *dmub)
++{
++	REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
++	REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
++	REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 0);
++}
++
++void dmub_dcn20_backdoor_load(struct dmub_srv *dmub, struct dmub_window *cw0,
++			      struct dmub_window *cw1)
++{
++	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
++	REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x4,
++		     DMCUB_MEM_WRITE_SPACE, 0x4);
++
++	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, cw0->offset.u.low_part);
++	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, cw0->offset.u.high_part);
++	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
++	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
++		  DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
++		  DMCUB_REGION3_CW0_ENABLE, 1);
++
++	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, cw1->offset.u.low_part);
++	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, cw1->offset.u.high_part);
++	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
++	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
++		  DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
++		  DMCUB_REGION3_CW1_ENABLE, 1);
++
++	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
++		     0x20);
++}
++
++void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
++			      const struct dmub_window *cw2,
++			      const struct dmub_window *cw3,
++			      const struct dmub_window *cw4,
++				  const struct dmub_window *cw5)
++{
++	REG_WRITE(DMCUB_REGION3_CW2_OFFSET, cw2->offset.u.low_part);
++	REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, cw2->offset.u.high_part);
++	REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
++	REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
++		  DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
++		  DMCUB_REGION3_CW2_ENABLE, 1);
++
++	REG_WRITE(DMCUB_REGION3_CW3_OFFSET, cw3->offset.u.low_part);
++	REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, cw3->offset.u.high_part);
++	REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
++	REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
++		  DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
++		  DMCUB_REGION3_CW3_ENABLE, 1);
++
++	/* TODO: Move this to CW4. */
++
++	REG_WRITE(DMCUB_REGION4_OFFSET, cw4->offset.u.low_part);
++	REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, cw4->offset.u.high_part);
++	REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS,
++		  cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE,
++		  1);
++}
++
++void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
++			      const struct dmub_region *inbox1)
++{
++	/* TODO: Use CW4 instead of region 4. */
++
++	REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000);
++	REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
++	REG_WRITE(DMCUB_INBOX1_RPTR, 0);
++	REG_WRITE(DMCUB_INBOX1_WPTR, 0);
++}
++
++uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub)
++{
++	return REG_READ(DMCUB_INBOX1_RPTR);
++}
++
++void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
++{
++	REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
++}
++
++bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
++{
++	uint32_t supported = 0;
++
++	REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
++
++	return supported;
++}
++
++bool dmub_dcn20_is_phy_init(struct dmub_srv *dmub)
++{
++	return REG_READ(DMCUB_SCRATCH10) != 0;
++}
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+new file mode 100644
+index 000000000000..41269da40363
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+@@ -0,0 +1,62 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_DCN20_H_
++#define _DMUB_DCN20_H_
++
++#include "../inc/dmub_types.h"
++
++struct dmub_srv;
++
++/* Hardware functions. */
++
++void dmub_dcn20_init(struct dmub_srv *dmub);
++
++void dmub_dcn20_reset(struct dmub_srv *dmub);
++
++void dmub_dcn20_reset_release(struct dmub_srv *dmub);
++
++void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
++			      const struct dmub_window *cw0,
++			      const struct dmub_window *cw1);
++
++void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
++			      const struct dmub_window *cw2,
++			      const struct dmub_window *cw3,
++			      const struct dmub_window *cw4,
++				  const struct dmub_window *cw5);
++
++void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
++			      const struct dmub_region *inbox1);
++
++uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub);
++
++void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
++
++bool dmub_dcn20_is_supported(struct dmub_srv *dmub);
++
++bool dmub_dcn20_is_phy_init(struct dmub_srv *dmub);
++
++#endif /* _DMUB_DCN20_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
+new file mode 100644
+index 000000000000..d40a808112e7
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
+@@ -0,0 +1,126 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "../inc/dmub_srv.h"
++#include "dmub_reg.h"
++
++#include "dcn/dcn_2_1_0_offset.h"
++#include "dcn/dcn_2_1_0_sh_mask.h"
++#include "renoir_ip_offset.h"
++
++#define BASE_INNER(seg) DMU_BASE__INST0_SEG##seg
++#define CTX dmub
++
++static inline void dmub_dcn21_translate_addr(const union dmub_addr *addr_in,
++					     uint64_t fb_base,
++					     uint64_t fb_offset,
++					     union dmub_addr *addr_out)
++{
++	addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
++}
++
++void dmub_dcn21_backdoor_load(struct dmub_srv *dmub,
++			      const struct dmub_window *cw0,
++			      const struct dmub_window *cw1)
++{
++	union dmub_addr offset;
++	uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
++
++	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
++	REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3,
++		     DMCUB_MEM_WRITE_SPACE, 0x3);
++
++	dmub_dcn21_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
++
++	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
++	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
++	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
++	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
++		  DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
++		  DMCUB_REGION3_CW0_ENABLE, 1);
++
++	dmub_dcn21_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
++
++	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
++	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
++	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
++	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
++		  DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
++		  DMCUB_REGION3_CW1_ENABLE, 1);
++
++	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
++		     0x20);
++}
++
++void dmub_dcn21_setup_windows(struct dmub_srv *dmub,
++			      const struct dmub_window *cw2,
++			      const struct dmub_window *cw3,
++			      const struct dmub_window *cw4,
++				  const struct dmub_window *cw5)
++{
++	union dmub_addr offset;
++	uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
++
++	dmub_dcn21_translate_addr(&cw2->offset, fb_base, fb_offset, &offset);
++
++	REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
++	REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
++	REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
++	REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
++		  DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
++		  DMCUB_REGION3_CW2_ENABLE, 1);
++
++	dmub_dcn21_translate_addr(&cw3->offset, fb_base, fb_offset, &offset);
++
++	REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
++	REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
++	REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
++	REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
++		  DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
++		  DMCUB_REGION3_CW3_ENABLE, 1);
++
++	/* TODO: Move this to CW4. */
++	dmub_dcn21_translate_addr(&cw4->offset, fb_base, fb_offset, &offset);
++
++	REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
++	REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
++	REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS,
++		  cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE,
++		  1);
++
++	dmub_dcn21_translate_addr(&cw5->offset, fb_base, fb_offset, &offset);
++
++	REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
++	REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
++	REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
++	REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
++		  DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
++		  DMCUB_REGION3_CW5_ENABLE, 1);
++}
++
++bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub)
++{
++	return (REG_READ(DMCUB_SCRATCH0) == 3);
++}
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
+new file mode 100644
+index 000000000000..f57969d8d56f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
+@@ -0,0 +1,45 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_DCN21_H_
++#define _DMUB_DCN21_H_
++
++#include "dmub_dcn20.h"
++
++/* Hardware functions. */
++
++void dmub_dcn21_backdoor_load(struct dmub_srv *dmub,
++			      const struct dmub_window *cw0,
++			      const struct dmub_window *cw1);
++
++void dmub_dcn21_setup_windows(struct dmub_srv *dmub,
++			      const struct dmub_window *cw2,
++			      const struct dmub_window *cw3,
++			      const struct dmub_window *cw4,
++				  const struct dmub_window *cw5);
++
++bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub);
++
++#endif /* _DMUB_DCN21_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c
+new file mode 100644
+index 000000000000..4094eca212f0
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c
+@@ -0,0 +1,109 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "dmub_reg.h"
++#include "../inc/dmub_srv.h"
++
++struct dmub_reg_value_masks {
++	uint32_t value;
++	uint32_t mask;
++};
++
++static inline void
++set_reg_field_value_masks(struct dmub_reg_value_masks *field_value_mask,
++			  uint32_t value, uint32_t mask, uint8_t shift)
++{
++	field_value_mask->value =
++		(field_value_mask->value & ~mask) | (mask & (value << shift));
++	field_value_mask->mask = field_value_mask->mask | mask;
++}
++
++static void set_reg_field_values(struct dmub_reg_value_masks *field_value_mask,
++				 uint32_t addr, int n, uint8_t shift1,
++				 uint32_t mask1, uint32_t field_value1,
++				 va_list ap)
++{
++	uint32_t shift, mask, field_value;
++	int i = 1;
++
++	/* gather all bits value/mask getting updated in this register */
++	set_reg_field_value_masks(field_value_mask, field_value1, mask1,
++				  shift1);
++
++	while (i < n) {
++		shift = va_arg(ap, uint32_t);
++		mask = va_arg(ap, uint32_t);
++		field_value = va_arg(ap, uint32_t);
++
++		set_reg_field_value_masks(field_value_mask, field_value, mask,
++					  shift);
++		i++;
++	}
++}
++
++static inline uint32_t get_reg_field_value_ex(uint32_t reg_value, uint32_t mask,
++					      uint8_t shift)
++{
++	return (mask & reg_value) >> shift;
++}
++
++void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1,
++		     uint32_t mask1, uint32_t field_value1, ...)
++{
++	struct dmub_reg_value_masks field_value_mask = { 0 };
++	uint32_t reg_val;
++	va_list ap;
++
++	va_start(ap, field_value1);
++	set_reg_field_values(&field_value_mask, addr, n, shift1, mask1,
++			     field_value1, ap);
++	va_end(ap);
++
++	reg_val = srv->funcs.reg_read(srv->user_ctx, addr);
++	reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
++	srv->funcs.reg_write(srv->user_ctx, addr, reg_val);
++}
++
++void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n,
++		  uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...)
++{
++	struct dmub_reg_value_masks field_value_mask = { 0 };
++	va_list ap;
++
++	va_start(ap, field_value1);
++	set_reg_field_values(&field_value_mask, addr, n, shift1, mask1,
++			     field_value1, ap);
++	va_end(ap);
++
++	reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
++	srv->funcs.reg_write(srv->user_ctx, addr, reg_val);
++}
++
++void dmub_reg_get(struct dmub_srv *srv, uint32_t addr, uint8_t shift,
++		  uint32_t mask, uint32_t *field_value)
++{
++	uint32_t reg_val = srv->funcs.reg_read(srv->user_ctx, addr);
++	*field_value = get_reg_field_value_ex(reg_val, mask, shift);
++}
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h
+new file mode 100644
+index 000000000000..bac4ee8f745f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h
+@@ -0,0 +1,120 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_REG_H_
++#define _DMUB_REG_H_
++
++#include "../inc/dmub_types.h"
++
++struct dmub_srv;
++
++/* Register offset and field lookup. */
++
++#define BASE(seg) BASE_INNER(seg)
++
++#define REG_OFFSET(base_index, addr) (BASE(base_index) + addr)
++
++#define REG(reg_name) REG_OFFSET(mm ## reg_name ## _BASE_IDX, mm ## reg_name)
++
++#define FD(reg_field) reg_field ## __SHIFT,  reg_field ## _MASK
++
++#define FN(reg_name, field) FD(reg_name##__##field)
++
++/* Register reads and writes. */
++
++#define REG_READ(reg) ((CTX)->funcs.reg_read((CTX)->user_ctx, REG(reg)))
++
++#define REG_WRITE(reg, val) \
++	((CTX)->funcs.reg_write((CTX)->user_ctx, REG(reg), (val)))
++
++/* Register field setting. */
++
++#define REG_SET_N(reg_name, n, initial_val, ...) \
++	dmub_reg_set(CTX, REG(reg_name), initial_val, n, __VA_ARGS__)
++
++#define REG_SET(reg_name, initial_val, field, val) \
++		REG_SET_N(reg_name, 1, initial_val, \
++				FN(reg_name, field), val)
++
++#define REG_SET_2(reg, init_value, f1, v1, f2, v2) \
++		REG_SET_N(reg, 2, init_value, \
++				FN(reg, f1), v1, \
++				FN(reg, f2), v2)
++
++#define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \
++		REG_SET_N(reg, 3, init_value, \
++				FN(reg, f1), v1, \
++				FN(reg, f2), v2, \
++				FN(reg, f3), v3)
++
++#define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \
++		REG_SET_N(reg, 4, init_value, \
++				FN(reg, f1), v1, \
++				FN(reg, f2), v2, \
++				FN(reg, f3), v3, \
++				FN(reg, f4), v4)
++
++/* Register field updating. */
++
++#define REG_UPDATE_N(reg_name, n, ...)\
++		dmub_reg_update(CTX, REG(reg_name), n, __VA_ARGS__)
++
++#define REG_UPDATE(reg_name, field, val)	\
++		REG_UPDATE_N(reg_name, 1, \
++				FN(reg_name, field), val)
++
++#define REG_UPDATE_2(reg, f1, v1, f2, v2)	\
++		REG_UPDATE_N(reg, 2,\
++				FN(reg, f1), v1,\
++				FN(reg, f2), v2)
++
++#define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \
++		REG_UPDATE_N(reg, 3, \
++				FN(reg, f1), v1, \
++				FN(reg, f2), v2, \
++				FN(reg, f3), v3)
++
++#define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \
++		REG_UPDATE_N(reg, 4, \
++				FN(reg, f1), v1, \
++				FN(reg, f2), v2, \
++				FN(reg, f3), v3, \
++				FN(reg, f4), v4)
++
++/* Register field getting. */
++
++#define REG_GET(reg_name, field, val) \
++	dmub_reg_get(CTX, REG(reg_name), FN(reg_name, field), val)
++
++void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n,
++		  uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
++
++void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1,
++		     uint32_t mask1, uint32_t field_value1, ...);
++
++void dmub_reg_get(struct dmub_srv *srv, uint32_t addr, uint8_t shift,
++		  uint32_t mask, uint32_t *field_value);
++
++#endif /* _DMUB_REG_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+new file mode 100644
+index 000000000000..229eab7277d1
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+@@ -0,0 +1,415 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "../inc/dmub_srv.h"
++#include "dmub_dcn20.h"
++#include "dmub_dcn21.h"
++/*
++ * Note: the DMUB service is standalone. No additional headers should be
++ * added below or above this line unless they reside within the DMUB
++ * folder.
++ */
++
++/* Alignment for framebuffer memory. */
++#define DMUB_FB_ALIGNMENT (1024 * 1024)
++
++/* Stack size. */
++#define DMUB_STACK_SIZE (128 * 1024)
++
++/* Context size. */
++#define DMUB_CONTEXT_SIZE (512 * 1024)
++
++/* Mailbox size */
++#define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE)
++
++/* Tracebuffer size */
++#define DMUB_TRACEBUFF_SIZE (1024) //1kB buffer
++
++/* Number of windows in use. */
++#define DMUB_NUM_WINDOWS (DMUB_WINDOW_5_TRACEBUFF + 1)
++/* Base addresses. */
++
++#define DMUB_CW0_BASE (0x60000000)
++#define DMUB_CW1_BASE (0x61000000)
++#define DMUB_CW5_BASE (0x65000000)
++
++static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
++{
++	return (val + factor - 1) / factor * factor;
++}
++
++static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
++{
++	struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs;
++
++	switch (asic) {
++	case DMUB_ASIC_DCN20:
++	case DMUB_ASIC_DCN21:
++		funcs->reset = dmub_dcn20_reset;
++		funcs->reset_release = dmub_dcn20_reset_release;
++		funcs->backdoor_load = dmub_dcn20_backdoor_load;
++		funcs->setup_windows = dmub_dcn20_setup_windows;
++		funcs->setup_mailbox = dmub_dcn20_setup_mailbox;
++		funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr;
++		funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr;
++		funcs->is_supported = dmub_dcn20_is_supported;
++		funcs->is_phy_init = dmub_dcn20_is_phy_init;
++
++		if (asic == DMUB_ASIC_DCN21) {
++			funcs->backdoor_load = dmub_dcn21_backdoor_load;
++			funcs->setup_windows = dmub_dcn21_setup_windows;
++			funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done;
++		}
++		break;
++
++	default:
++		return false;
++	}
++
++	return true;
++}
++
++enum dmub_status dmub_srv_create(struct dmub_srv *dmub,
++				 const struct dmub_srv_create_params *params)
++{
++	enum dmub_status status = DMUB_STATUS_OK;
++
++	dmub_memset(dmub, 0, sizeof(*dmub));
++
++	dmub->funcs = params->funcs;
++	dmub->user_ctx = params->user_ctx;
++	dmub->asic = params->asic;
++	dmub->is_virtual = params->is_virtual;
++
++	/* Setup asic dependent hardware funcs. */
++	if (!dmub_srv_hw_setup(dmub, params->asic)) {
++		status = DMUB_STATUS_INVALID;
++		goto cleanup;
++	}
++
++	/* Override (some) hardware funcs based on user params. */
++	if (params->hw_funcs) {
++		if (params->hw_funcs->get_inbox1_rptr)
++			dmub->hw_funcs.get_inbox1_rptr =
++				params->hw_funcs->get_inbox1_rptr;
++
++		if (params->hw_funcs->set_inbox1_wptr)
++			dmub->hw_funcs.set_inbox1_wptr =
++				params->hw_funcs->set_inbox1_wptr;
++
++		if (params->hw_funcs->is_supported)
++			dmub->hw_funcs.is_supported =
++				params->hw_funcs->is_supported;
++	}
++
++	/* Sanity checks for required hw func pointers. */
++	if (!dmub->hw_funcs.get_inbox1_rptr ||
++	    !dmub->hw_funcs.set_inbox1_wptr) {
++		status = DMUB_STATUS_INVALID;
++		goto cleanup;
++	}
++
++cleanup:
++	if (status == DMUB_STATUS_OK)
++		dmub->sw_init = true;
++	else
++		dmub_srv_destroy(dmub);
++
++	return status;
++}
++
++void dmub_srv_destroy(struct dmub_srv *dmub)
++{
++	dmub_memset(dmub, 0, sizeof(*dmub));
++}
++
++enum dmub_status
++dmub_srv_calc_region_info(struct dmub_srv *dmub,
++			  const struct dmub_srv_region_params *params,
++			  struct dmub_srv_region_info *out)
++{
++	struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST];
++	struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK];
++	struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA];
++	struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS];
++	struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX];
++	struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF];
++
++	if (!dmub->sw_init)
++		return DMUB_STATUS_INVALID;
++
++	memset(out, 0, sizeof(*out));
++
++	out->num_regions = DMUB_NUM_WINDOWS;
++
++	inst->base = 0x0;
++	inst->top = inst->base + params->inst_const_size;
++
++	data->base = dmub_align(inst->top, 256);
++	data->top = data->base + params->bss_data_size;
++
++	stack->base = dmub_align(data->top, 256);
++	stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE;
++
++	bios->base = dmub_align(stack->top, 256);
++	bios->top = bios->base + params->vbios_size;
++
++	mail->base = dmub_align(bios->top, 256);
++	mail->top = mail->base + DMUB_MAILBOX_SIZE;
++
++	trace_buff->base = dmub_align(mail->top, 256);
++	trace_buff->top = trace_buff->base + DMUB_TRACEBUFF_SIZE;
++
++	out->fb_size = dmub_align(trace_buff->top, 4096);
++
++	return DMUB_STATUS_OK;
++}
++
++enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub,
++				       const struct dmub_srv_fb_params *params,
++				       struct dmub_srv_fb_info *out)
++{
++	uint8_t *cpu_base;
++	uint64_t gpu_base;
++	uint32_t i;
++
++	if (!dmub->sw_init)
++		return DMUB_STATUS_INVALID;
++
++	memset(out, 0, sizeof(*out));
++
++	if (params->region_info->num_regions != DMUB_NUM_WINDOWS)
++		return DMUB_STATUS_INVALID;
++
++	cpu_base = (uint8_t *)params->cpu_addr;
++	gpu_base = params->gpu_addr;
++
++	for (i = 0; i < DMUB_NUM_WINDOWS; ++i) {
++		const struct dmub_region *reg =
++			&params->region_info->regions[i];
++
++		out->fb[i].cpu_addr = cpu_base + reg->base;
++		out->fb[i].gpu_addr = gpu_base + reg->base;
++		out->fb[i].size = reg->top - reg->base;
++	}
++
++	out->num_fb = DMUB_NUM_WINDOWS;
++
++	return DMUB_STATUS_OK;
++}
++
++enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
++					 bool *is_supported)
++{
++	*is_supported = false;
++
++	if (!dmub->sw_init)
++		return DMUB_STATUS_INVALID;
++
++	if (dmub->hw_funcs.is_supported)
++		*is_supported = dmub->hw_funcs.is_supported(dmub);
++
++	return DMUB_STATUS_OK;
++}
++
++enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
++				  const struct dmub_srv_hw_params *params)
++{
++	struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST];
++	struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK];
++	struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA];
++	struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS];
++	struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX];
++	struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF];
++
++	struct dmub_rb_init_params rb_params;
++	struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5;
++	struct dmub_region inbox1;
++
++	if (!dmub->sw_init)
++		return DMUB_STATUS_INVALID;
++
++	dmub->fb_base = params->fb_base;
++	dmub->fb_offset = params->fb_offset;
++	dmub->psp_version = params->psp_version;
++
++	if (inst_fb && data_fb) {
++		cw0.offset.quad_part = inst_fb->gpu_addr;
++		cw0.region.base = DMUB_CW0_BASE;
++		cw0.region.top = cw0.region.base + inst_fb->size - 1;
++
++		cw1.offset.quad_part = stack_fb->gpu_addr;
++		cw1.region.base = DMUB_CW1_BASE;
++		cw1.region.top = cw1.region.base + stack_fb->size - 1;
++
++		if (dmub->hw_funcs.backdoor_load)
++			dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
++	}
++
++	if (dmub->hw_funcs.reset)
++		dmub->hw_funcs.reset(dmub);
++
++	if (inst_fb && data_fb && bios_fb && mail_fb) {
++		cw2.offset.quad_part = data_fb->gpu_addr;
++		cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
++		cw2.region.top = cw2.region.base + data_fb->size;
++
++		cw3.offset.quad_part = bios_fb->gpu_addr;
++		cw3.region.base = DMUB_CW1_BASE + stack_fb->size;
++		cw3.region.top = cw3.region.base + bios_fb->size;
++
++		cw4.offset.quad_part = mail_fb->gpu_addr;
++		cw4.region.base = cw3.region.top + 1;
++		cw4.region.top = cw4.region.base + mail_fb->size;
++
++		inbox1.base = cw4.region.base;
++		inbox1.top = cw4.region.top;
++
++		cw5.offset.quad_part = tracebuff_fb->gpu_addr;
++		cw5.region.base = DMUB_CW5_BASE;
++		cw5.region.top = cw5.region.base + tracebuff_fb->size;
++
++		if (dmub->hw_funcs.setup_windows)
++			dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5);
++
++		if (dmub->hw_funcs.setup_mailbox)
++			dmub->hw_funcs.setup_mailbox(dmub, &inbox1);
++	}
++
++	if (mail_fb) {
++		dmub_memset(&rb_params, 0, sizeof(rb_params));
++		rb_params.ctx = dmub;
++		rb_params.base_address = mail_fb->cpu_addr;
++		rb_params.capacity = DMUB_RB_SIZE;
++
++		dmub_rb_init(&dmub->inbox1_rb, &rb_params);
++	}
++
++	if (dmub->hw_funcs.reset_release)
++		dmub->hw_funcs.reset_release(dmub);
++
++	dmub->hw_init = true;
++
++	return DMUB_STATUS_OK;
++}
++
++enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,
++				    const struct dmub_cmd_header *cmd)
++{
++	if (!dmub->hw_init)
++		return DMUB_STATUS_INVALID;
++
++	if (dmub_rb_push_front(&dmub->inbox1_rb, cmd))
++		return DMUB_STATUS_OK;
++
++	return DMUB_STATUS_QUEUE_FULL;
++}
++
++enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
++{
++	if (!dmub->hw_init)
++		return DMUB_STATUS_INVALID;
++
++	dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);
++	return DMUB_STATUS_OK;
++}
++
++enum dmub_status dmub_srv_cmd_submit(struct dmub_srv *dmub,
++				     const struct dmub_cmd_header *cmd,
++				     uint32_t timeout_us)
++{
++	uint32_t i = 0;
++
++	if (!dmub->hw_init)
++		return DMUB_STATUS_INVALID;
++
++	for (i = 0; i <= timeout_us; ++i) {
++		dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
++		if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) {
++			dmub->hw_funcs.set_inbox1_wptr(dmub,
++						       dmub->inbox1_rb.wrpt);
++			return DMUB_STATUS_OK;
++		}
++
++		udelay(1);
++	}
++
++	return DMUB_STATUS_TIMEOUT;
++}
++
++enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
++					     uint32_t timeout_us)
++{
++	uint32_t i;
++
++	if (!dmub->hw_init || !dmub->hw_funcs.is_auto_load_done)
++		return DMUB_STATUS_INVALID;
++
++	for (i = 0; i <= timeout_us; i += 100) {
++		if (dmub->hw_funcs.is_auto_load_done(dmub))
++			return DMUB_STATUS_OK;
++
++		udelay(100);
++	}
++
++	return DMUB_STATUS_TIMEOUT;
++}
++
++enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
++					    uint32_t timeout_us)
++{
++	uint32_t i;
++
++	if (!dmub->hw_init || !dmub->hw_funcs.is_phy_init)
++		return DMUB_STATUS_INVALID;
++
++	for (i = 0; i <= timeout_us; i += 10) {
++		if (dmub->hw_funcs.is_phy_init(dmub))
++			return DMUB_STATUS_OK;
++
++		udelay(10);
++	}
++
++	return DMUB_STATUS_TIMEOUT;
++}
++
++enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
++					uint32_t timeout_us)
++{
++	uint32_t i;
++
++	if (!dmub->hw_init)
++		return DMUB_STATUS_INVALID;
++
++	for (i = 0; i <= timeout_us; ++i) {
++		dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
++		if (dmub_rb_empty(&dmub->inbox1_rb))
++			return DMUB_STATUS_OK;
++
++		udelay(1);
++	}
++
++	return DMUB_STATUS_TIMEOUT;
++}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4327-drm-amd-display-Change-dmcu-init-sequence-for-dmcub-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4327-drm-amd-display-Change-dmcu-init-sequence-for-dmcub-.patch
new file mode 100644
index 00000000..c644d5b0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4327-drm-amd-display-Change-dmcu-init-sequence-for-dmcub-.patch
@@ -0,0 +1,243 @@
+From 803d95182f195a176ca0ac6d7a99baeeace7225d Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Sat, 12 Oct 2019 16:06:19 -0400
+Subject: [PATCH 4327/4736] drm/amd/display: Change dmcu init sequence for
+ dmcub loading dmcu FW.
+
+[Why]
+DMCU isn't intiliazed properly by dmcub loading due to dmcub initialize
+sequence.
+
+[How]
+Change dmcu init sequece to meet dmcub initilize.
+
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 79 +++++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 13 +++
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  2 +-
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c |  4 +-
+ drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h  |  2 +
+ 5 files changed, 97 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+index f86ad9865a48..66925c8f10d9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+@@ -56,6 +56,12 @@
+ #define MCP_BL_SET_PWM_FRAC 0x6A  /* Enable or disable Fractional PWM */
+ #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK   0x00000001L
+ 
++// PSP FW version
++#define mmMP0_SMN_C2PMSG_58				0x1607A
++
++//Register access policy version
++#define mmMP0_SMN_C2PMSG_91				0x1609B
++
+ static bool dce_dmcu_init(struct dmcu *dmcu)
+ {
+ 	// Do nothing
+@@ -370,6 +376,7 @@ static bool dcn10_dmcu_init(struct dmcu *dmcu)
+ 	const struct dc_config *config = &dmcu->ctx->dc->config;
+ 	bool status = false;
+ 
++	PERF_TRACE();
+ 	/*  Definition of DC_DMCU_SCRATCH
+ 	 *  0 : firmare not loaded
+ 	 *  1 : PSP load DMCU FW but not initialized
+@@ -426,9 +433,23 @@ static bool dcn10_dmcu_init(struct dmcu *dmcu)
+ 		break;
+ 	}
+ 
++	PERF_TRACE();
+ 	return status;
+ }
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++static bool dcn21_dmcu_init(struct dmcu *dmcu)
++{
++	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
++	uint32_t dmcub_psp_version = REG_READ(DMCUB_SCRATCH15);
++
++	if (dmcu->auto_load_dmcu && dmcub_psp_version == 0) {
++		return false;
++	}
++
++	return dcn10_dmcu_init(dmcu);
++}
++#endif
+ 
+ static bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
+ 		unsigned int start_offset,
+@@ -815,6 +836,21 @@ static const struct dmcu_funcs dcn20_funcs = {
+ };
+ #endif
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++static const struct dmcu_funcs dcn21_funcs = {
++	.dmcu_init = dcn21_dmcu_init,
++	.load_iram = dcn10_dmcu_load_iram,
++	.set_psr_enable = dcn10_dmcu_set_psr_enable,
++	.setup_psr = dcn10_dmcu_setup_psr,
++	.get_psr_state = dcn10_get_dmcu_psr_state,
++	.set_psr_wait_loop = dcn10_psr_wait_loop,
++	.get_psr_wait_loop = dcn10_get_psr_wait_loop,
++	.is_dmcu_initialized = dcn10_is_dmcu_initialized,
++	.lock_phy = dcn20_lock_phy,
++	.unlock_phy = dcn20_unlock_phy
++};
++#endif
++
+ static void dce_dmcu_construct(
+ 	struct dce_dmcu *dmcu_dce,
+ 	struct dc_context *ctx,
+@@ -833,6 +869,26 @@ static void dce_dmcu_construct(
+ 	dmcu_dce->dmcu_mask = dmcu_mask;
+ }
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++static void dcn21_dmcu_construct(
++		struct dce_dmcu *dmcu_dce,
++		struct dc_context *ctx,
++		const struct dce_dmcu_registers *regs,
++		const struct dce_dmcu_shift *dmcu_shift,
++		const struct dce_dmcu_mask *dmcu_mask)
++{
++	uint32_t psp_version = 0;
++
++	dce_dmcu_construct(dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
++
++	if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
++		psp_version = dm_read_reg(ctx, mmMP0_SMN_C2PMSG_58);
++		dmcu_dce->base.auto_load_dmcu = (psp_version > 0x00110029);
++		dmcu_dce->base.psp_version = psp_version;
++	}
++}
++#endif
++
+ struct dmcu *dce_dmcu_create(
+ 	struct dc_context *ctx,
+ 	const struct dce_dmcu_registers *regs,
+@@ -900,6 +956,29 @@ struct dmcu *dcn20_dmcu_create(
+ }
+ #endif
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++struct dmcu *dcn21_dmcu_create(
++	struct dc_context *ctx,
++	const struct dce_dmcu_registers *regs,
++	const struct dce_dmcu_shift *dmcu_shift,
++	const struct dce_dmcu_mask *dmcu_mask)
++{
++	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
++
++	if (dmcu_dce == NULL) {
++		BREAK_TO_DEBUGGER();
++		return NULL;
++	}
++
++	dcn21_dmcu_construct(
++		dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
++
++	dmcu_dce->base.funcs = &dcn21_funcs;
++
++	return &dmcu_dce->base;
++}
++#endif
++
+ void dce_dmcu_destroy(struct dmcu **dmcu)
+ {
+ 	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+index cc8587683b4b..1a42b2cbb21b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+@@ -71,6 +71,10 @@
+ 	DMCU_COMMON_REG_LIST_DCE_BASE(), \
+ 	SR(DMU_MEM_PWR_CNTL)
+ 
++#define DMCU_DCN20_REG_LIST()\
++	DMCU_DCN10_REG_LIST(), \
++	SR(DMCUB_SCRATCH15)
++
+ #define DMCU_SF(reg_name, field_name, post_fix)\
+ 	.field_name = reg_name ## __ ## field_name ## post_fix
+ 
+@@ -175,6 +179,7 @@ struct dce_dmcu_registers {
+ 	uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
+ 	uint32_t SMU_INTERRUPT_CONTROL;
+ 	uint32_t DC_DMCU_SCRATCH;
++	uint32_t DMCUB_SCRATCH15;
+ };
+ 
+ struct dce_dmcu {
+@@ -269,6 +274,14 @@ struct dmcu *dcn20_dmcu_create(
+ 	const struct dce_dmcu_mask *dmcu_mask);
+ #endif
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++struct dmcu *dcn21_dmcu_create(
++	struct dc_context *ctx,
++	const struct dce_dmcu_registers *regs,
++	const struct dce_dmcu_shift *dmcu_shift,
++	const struct dce_dmcu_mask *dmcu_mask);
++#endif
++
+ void dce_dmcu_destroy(struct dmcu **dmcu);
+ 
+ static const uint32_t abm_gain_stepsize = 0x0060;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index b61cc211e659..6d84239af593 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1284,7 +1284,7 @@ static void dcn10_init_hw(struct dc *dc)
+ 		abm->funcs->abm_init(abm);
+ 	}
+ 
+-	if (dmcu != NULL)
++	if (dmcu != NULL && !dmcu->auto_load_dmcu)
+ 		dmcu->funcs->dmcu_init(dmcu);
+ 
+ 	if (abm != NULL && dmcu != NULL)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 47367446f64c..0792b1c2e673 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -350,7 +350,7 @@ static const struct bios_registers bios_regs = {
+ };
+ 
+ static const struct dce_dmcu_registers dmcu_regs = {
+-		DMCU_DCN10_REG_LIST()
++		DMCU_DCN20_REG_LIST()
+ };
+ 
+ static const struct dce_dmcu_shift dmcu_shift = {
+@@ -1748,7 +1748,7 @@ static bool construct(
+ 		goto create_fail;
+ 	}
+ 
+-	pool->base.dmcu = dcn20_dmcu_create(ctx,
++	pool->base.dmcu = dcn21_dmcu_create(ctx,
+ 			&dmcu_regs,
+ 			&dmcu_shift,
+ 			&dmcu_mask);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
+index c68f0ce346c7..5315f1f86b21 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
+@@ -52,6 +52,8 @@ struct dmcu {
+ 	enum dmcu_state dmcu_state;
+ 	struct dmcu_version dmcu_version;
+ 	unsigned int cached_wait_loop_number;
++	uint32_t psp_version;
++	bool auto_load_dmcu;
+ };
+ 
+ struct dmcu_funcs {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4328-drm-amd-display-Add-PSP-FW-version-mask.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4328-drm-amd-display-Add-PSP-FW-version-mask.patch
new file mode 100644
index 00000000..acba3c0c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4328-drm-amd-display-Add-PSP-FW-version-mask.patch
@@ -0,0 +1,39 @@
+From 2261a74af63845b23ae8b85ae95a285de019eedb Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Thu, 17 Oct 2019 21:44:50 -0400
+Subject: [PATCH 4328/4736] drm/amd/display: Add PSP FW version mask.
+
+[Why]
+PSP version format is AB.CD.EF.GH, where CD and GH is the main version.
+current psp version check for dmcub loading dmcu check 0x00110029, in
+case of some psp version eg: 0x00110227 which main version should be
+0x00110027, will result in unexpeceted dmcub loading dmcu FW.
+
+[How]
+Add psp version mask 0x00FF00FF for checking version.
+
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+index 66925c8f10d9..da9a07edcb06 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+@@ -883,7 +883,7 @@ static void dcn21_dmcu_construct(
+ 
+ 	if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
+ 		psp_version = dm_read_reg(ctx, mmMP0_SMN_C2PMSG_58);
+-		dmcu_dce->base.auto_load_dmcu = (psp_version > 0x00110029);
++		dmcu_dce->base.auto_load_dmcu = ((psp_version & 0x00FF00FF) > 0x00110029);
+ 		dmcu_dce->base.psp_version = psp_version;
+ 	}
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4329-drm-amd-display-Hook-up-the-DMUB-service-in-DM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4329-drm-amd-display-Hook-up-the-DMUB-service-in-DM.patch
new file mode 100644
index 00000000..1fd4fee1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4329-drm-amd-display-Hook-up-the-DMUB-service-in-DM.patch
@@ -0,0 +1,436 @@
+From 99fcf29399a7463d48952b81e2616f6ca5bed1ef Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Thu, 24 Oct 2019 20:38:48 -0400
+Subject: [PATCH 4329/4736] drm/amd/display: Hook up the DMUB service in DM
+
+[Why]
+We need DMCUB on Renoir to support DMCU and PHY initialization.
+The DMUB service provides a mechanism to load the DMCUB.
+
+[How]
+Include the DMUB service in amdgpu_dm.
+
+Frontdoor loading of the DMCUB firmware needs to happen via PSP. To
+pass the firmware to PSP we need to hand it off to the firmware list
+in the base driver during software initialization.
+
+Most of the DMUB service can technically be initialized at this point
+in time, but we don't want to be allocating framebuffer memory for
+hardware that doesn't support the DMCUB and in order to check that we
+need to be able to read registers - something DM helpers aren't setup
+to do in software initialization.
+
+So everything but the service creation itself will get deferred to
+hardware initialization.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 270 ++++++++++++++++++
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  50 ++++
+ 2 files changed, 320 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 5a20ce0541c6..e226e526c4df 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -30,6 +30,11 @@
+ #include "dc.h"
+ #include "dc/inc/core_types.h"
+ #include "dal_asic_id.h"
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++#include "dmub/inc/dmub_srv.h"
++#include "dc/inc/hw/dmcu.h"
++#include "dc/inc/hw/abm.h"
++#endif
+ 
+ #include "vid.h"
+ #include "amdgpu.h"
+@@ -84,6 +89,10 @@
+ #include "modules/power/power_helpers.h"
+ #include "modules/inc/mod_info_packet.h"
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++#define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
++MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
++#endif
+ #define FIRMWARE_RAVEN_DMCU		"amdgpu/raven_dmcu.bin"
+ MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
+ 
+@@ -665,11 +674,151 @@ void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
+ 	}
+ }
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++static int dm_dmub_hw_init(struct amdgpu_device *adev)
++{
++	const unsigned int psp_header_bytes = 0x100;
++	const unsigned int psp_footer_bytes = 0x100;
++	const struct dmcub_firmware_header_v1_0 *hdr;
++	struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
++	const struct firmware *dmub_fw = adev->dm.dmub_fw;
++	struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
++	struct abm *abm = adev->dm.dc->res_pool->abm;
++	struct dmub_srv_region_params region_params;
++	struct dmub_srv_region_info region_info;
++	struct dmub_srv_fb_params fb_params;
++	struct dmub_srv_fb_info fb_info;
++	struct dmub_srv_hw_params hw_params;
++	enum dmub_status status;
++	const unsigned char *fw_inst_const, *fw_bss_data;
++	uint32_t i;
++	int r;
++	bool has_hw_support;
++
++	if (!dmub_srv)
++		/* DMUB isn't supported on the ASIC. */
++		return 0;
++
++	if (!dmub_fw) {
++		/* Firmware required for DMUB support. */
++		DRM_ERROR("No firmware provided for DMUB.\n");
++		return -EINVAL;
++	}
++
++	status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
++	if (status != DMUB_STATUS_OK) {
++		DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
++		return -EINVAL;
++	}
++
++	if (!has_hw_support) {
++		DRM_INFO("DMUB unsupported on ASIC\n");
++		return 0;
++	}
++
++	hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
++
++	/* Calculate the size of all the regions for the DMUB service. */
++	memset(&region_params, 0, sizeof(region_params));
++
++	region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
++					psp_header_bytes - psp_footer_bytes;
++	region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
++	region_params.vbios_size = adev->dm.dc->ctx->dc_bios->bios_size;
++
++	status = dmub_srv_calc_region_info(dmub_srv, &region_params,
++					   &region_info);
++
++	if (status != DMUB_STATUS_OK) {
++		DRM_ERROR("Error calculating DMUB region info: %d\n", status);
++		return -EINVAL;
++	}
++
++	/*
++	* Allocate a framebuffer based on the total size of all the regions.
++	* TODO: Move this into GART.
++	*/
++	r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
++				    AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo,
++				    &adev->dm.dmub_bo_gpu_addr,
++				    &adev->dm.dmub_bo_cpu_addr);
++	if (r)
++		return r;
++
++	/* Rebase the regions on the framebuffer address. */
++	memset(&fb_params, 0, sizeof(fb_params));
++	fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
++	fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
++	fb_params.region_info = &region_info;
++
++	status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, &fb_info);
++	if (status != DMUB_STATUS_OK) {
++		DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
++		return -EINVAL;
++	}
++
++	fw_inst_const = dmub_fw->data +
++			le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
++			 psp_header_bytes;
++
++	fw_bss_data = dmub_fw->data +
++	le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
++			le32_to_cpu(hdr->inst_const_bytes);
++
++	/* Copy firmware and bios info into FB memory. */
++	memcpy(fb_info.fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
++	       region_params.inst_const_size);
++	memcpy(fb_info.fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, fw_bss_data,
++	       region_params.bss_data_size);
++	memcpy(fb_info.fb[DMUB_WINDOW_3_VBIOS].cpu_addr,
++	       adev->dm.dc->ctx->dc_bios->bios, region_params.vbios_size);
++
++	/* Initialize hardware. */
++	memset(&hw_params, 0, sizeof(hw_params));
++	hw_params.fb_base = adev->gmc.fb_start;
++	hw_params.fb_offset = adev->gmc.aper_base;
++
++	if (dmcu)
++		hw_params.psp_version = dmcu->psp_version;
++
++	for (i = 0; i < fb_info.num_fb; ++i)
++		hw_params.fb[i] = &fb_info.fb[i];
++
++	status = dmub_srv_hw_init(dmub_srv, &hw_params);
++	if (status != DMUB_STATUS_OK) {
++		DRM_ERROR("Error initializing DMUB HW: %d\n", status);
++		return -EINVAL;
++	}
++
++	/* Wait for firmware load to finish. */
++	status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
++	if (status != DMUB_STATUS_OK)
++		DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
++
++	/* Init DMCU and ABM if available. */
++	if (dmcu && abm) {
++		dmcu->funcs->dmcu_init(dmcu);
++		abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
++	}
++
++	DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
++		adev->dm.dmcub_fw_version);
++
++	return 0;
++}
++
++#endif
++
++
++
+ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ {
+ 	struct dc_init_data init_data;
+ #ifdef CONFIG_DRM_AMD_DC_HDCP
+ 	struct dc_callback_init init_params;
++#endif
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	int r;
+ #endif
+ 	adev->dm.ddev = adev->ddev;
+ 	adev->dm.adev = adev;
+@@ -746,6 +895,14 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ 
+ 	dc_hardware_init(adev->dm.dc);
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	r = dm_dmub_hw_init(adev);
++	if (r) {
++		DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
++		goto error;
++	}
++
++#endif
+ 	adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
+ 	if (!adev->dm.freesync_module) {
+ 		DRM_ERROR(
+@@ -781,6 +938,12 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ 	if (dtn_debugfs_init(adev))
+ 		DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
+ #endif
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	if (adev->dm.dmub_bo)
++		amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
++				      &adev->dm.dmub_bo_gpu_addr,
++				      &adev->dm.dmub_bo_cpu_addr);
++#endif
+ 
+ 	DRM_DEBUG_DRIVER("KMS initialized.\n");
+ 
+@@ -914,9 +1077,104 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
++{
++	struct amdgpu_device *adev = ctx;
++
++	return dm_read_reg(adev->dm.dc->ctx, address);
++}
++
++static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
++				     uint32_t value)
++{
++	struct amdgpu_device *adev = ctx;
++
++	return dm_write_reg(adev->dm.dc->ctx, address, value);
++}
++
++static int dm_dmub_sw_init(struct amdgpu_device *adev)
++{
++	struct dmub_srv_create_params create_params;
++	const struct dmcub_firmware_header_v1_0 *hdr;
++	const char *fw_name_dmub;
++	enum dmub_asic dmub_asic;
++	enum dmub_status status;
++	int r;
++
++	switch (adev->asic_type) {
++	case CHIP_RENOIR:
++		dmub_asic = DMUB_ASIC_DCN21;
++		fw_name_dmub = FIRMWARE_RENOIR_DMUB;
++		break;
++
++	default:
++		/* ASIC doesn't support DMUB. */
++		return 0;
++	}
++
++	adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
++	if (!adev->dm.dmub_srv) {
++		DRM_ERROR("Failed to allocate DMUB service!\n");
++		return -ENOMEM;
++	}
++
++	memset(&create_params, 0, sizeof(create_params));
++	create_params.user_ctx = adev;
++	create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
++	create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
++	create_params.asic = dmub_asic;
++
++	status = dmub_srv_create(adev->dm.dmub_srv, &create_params);
++	if (status != DMUB_STATUS_OK) {
++		DRM_ERROR("Error creating DMUB service: %d\n", status);
++		return -EINVAL;
++	}
++
++	r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev);
++	if (r) {
++		DRM_ERROR("DMUB firmware loading failed: %d\n", r);
++		return 0;
++	}
++
++	r = amdgpu_ucode_validate(adev->dm.dmub_fw);
++	if (r) {
++		DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r);
++		return 0;
++	}
++
++	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
++		DRM_WARN("Only PSP firmware loading is supported for DMUB\n");
++		return 0;
++	}
++
++	hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
++	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
++		AMDGPU_UCODE_ID_DMCUB;
++	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = adev->dm.dmub_fw;
++	adev->firmware.fw_size +=
++		ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
++
++	adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
++
++	DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
++		 adev->dm.dmcub_fw_version);
++
++	return 0;
++}
++
++#endif
+ static int dm_sw_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	int r;
++
++	r = dm_dmub_sw_init(adev);
++	if (r)
++		return r;
++
++#endif
+ 
+ 	return load_dmcu_fw(adev);
+ }
+@@ -925,6 +1183,18 @@ static int dm_sw_fini(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	if (adev->dm.dmub_srv) {
++		dmub_srv_destroy(adev->dm.dmub_srv);
++		adev->dm.dmub_srv = NULL;
++	}
++
++	if (adev->dm.dmub_fw) {
++		release_firmware(adev->dm.dmub_fw);
++		adev->dm.dmub_fw = NULL;
++	}
++
++#endif
+ 	if(adev->dm.fw_dmcu) {
+ 		release_firmware(adev->dm.fw_dmcu);
+ 		adev->dm.fw_dmcu = NULL;
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+index 1aba070477b9..27167d2bd654 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+@@ -54,6 +54,10 @@ struct amdgpu_device;
+ struct drm_device;
+ struct amdgpu_dm_irq_handler_data;
+ struct dc;
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++struct amdgpu_bo;
++struct dmub_srv;
++#endif
+ 
+ struct common_irq_params {
+ 	struct amdgpu_device *adev;
+@@ -145,6 +149,52 @@ struct amdgpu_display_manager {
+ 	 */
+ 	struct mutex dc_lock;
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	/**
++	 * @dmub_srv:
++	 *
++	 * DMUB service, used for controlling the DMUB on hardware
++	 * that supports it. The pointer to the dmub_srv will be
++	 * NULL on hardware that does not support it.
++	 */
++	struct dmub_srv *dmub_srv;
++
++	/**
++	 * @dmub_fw:
++	 *
++	 * DMUB firmware, required on hardware that has DMUB support.
++	 */
++	const struct firmware *dmub_fw;
++
++	/**
++	 * @dmub_bo:
++	 *
++	 * Buffer object for the DMUB.
++	 */
++	struct amdgpu_bo *dmub_bo;
++
++	/**
++	 * @dmub_bo_gpu_addr:
++	 *
++	 * GPU virtual address for the DMUB buffer object.
++	 */
++	u64 dmub_bo_gpu_addr;
++
++	/**
++	 * @dmub_bo_cpu_addr:
++	 *
++	 * CPU address for the DMUB buffer object.
++	 */
++	void *dmub_bo_cpu_addr;
++
++	/**
++	 * @dmcub_fw_version:
++	 *
++	 * DMCUB firmware version.
++	 */
++	uint32_t dmcub_fw_version;
++
++#endif
+ 	/**
+ 	 *@irq_handler_list_low_tab:
+ 	 *
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4330-drm-amdgpu-Add-DMCUB-to-firmware-query-interface.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4330-drm-amdgpu-Add-DMCUB-to-firmware-query-interface.patch
new file mode 100644
index 00000000..1075e944
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4330-drm-amdgpu-Add-DMCUB-to-firmware-query-interface.patch
@@ -0,0 +1,64 @@
+From 3faf3e71dc5db6f489cf30ec23cdd265f69f7935 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Fri, 25 Oct 2019 14:15:08 -0400
+Subject: [PATCH 4330/4736] drm/amdgpu: Add DMCUB to firmware query interface
+
+The DMCUB firmware version can be read using the AMDGPU_INFO ioctl
+or the amdgpu_firmware_info debugfs entry.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 12 ++++++++++++
+ include/uapi/drm/amdgpu_drm.h           |  3 +++
+ 2 files changed, 15 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index ff47dd26e35a..5abbfc488022 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -291,6 +291,10 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
+ 		fw_info->ver = adev->dm.dmcu_fw_version;
+ 		fw_info->feature = 0;
+ 		break;
++	case AMDGPU_INFO_FW_DMCUB:
++		fw_info->ver = adev->dm.dmcub_fw_version;
++		fw_info->feature = 0;
++		break;
+ 	default:
+ 		return -EINVAL;
+ 	}
+@@ -1430,6 +1434,14 @@ static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
+ 	seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
+ 		   fw_info.feature, fw_info.ver);
+ 
++	/* DMCUB */
++	query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
++	ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
++	if (ret)
++		return ret;
++	seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
++		   fw_info.feature, fw_info.ver);
++
+ 
+ 	seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
+ 
+diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
+index 2de868bf8266..989afacefb92 100644
+--- a/include/uapi/drm/amdgpu_drm.h
++++ b/include/uapi/drm/amdgpu_drm.h
+@@ -770,6 +770,9 @@ struct drm_amdgpu_cs_chunk_data {
+         /* Subquery id: Query DMCU firmware version */
+         #define AMDGPU_INFO_FW_DMCU             0x12
+ 	#define AMDGPU_INFO_FW_TA               0x13
++	/* Subquery id: Query DMCUB firmware version */
++	#define AMDGPU_INFO_FW_DMCUB            0x14
++
+ /* number of bytes moved for TTM migration */
+ #define AMDGPU_INFO_NUM_BYTES_MOVED		0x0f
+ /* the used VRAM size */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4331-drm-amd-display-Add-DMUB-support-to-DC.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4331-drm-amd-display-Add-DMUB-support-to-DC.patch
new file mode 100644
index 00000000..1580bb36
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4331-drm-amd-display-Add-DMUB-support-to-DC.patch
@@ -0,0 +1,968 @@
+From 23983b55e0d07ee00b2331b9c67f643281542f59 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Fri, 25 Oct 2019 15:03:58 -0400
+Subject: [PATCH 4331/4736] drm/amd/display: Add DMUB support to DC
+
+DC will use DMUB for command submission and flow control during
+initialization.
+
+Register offloading as well as submitting some BIOS commands are part
+of the DC internal interface but are guarded behind debug options.
+
+It won't be functional in amdgpu_dm yet since we don't pass the
+DMUB service to DC for use.
+
+Change-Id: Ib341af1d0d5569271cb1964de5b6ef6ba8e9d8f3
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/Makefile       |   6 +-
+ .../drm/amd/display/dc/bios/command_table2.c  |  91 ++++++
+ drivers/gpu/drm/amd/display/dc/core/dc.c      |   8 +
+ drivers/gpu/drm/amd/display/dc/dc.h           |  12 +
+ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c  | 119 ++++++++
+ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h  |  60 ++++
+ drivers/gpu/drm/amd/display/dc/dc_helper.c    | 273 ++++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/dc_types.h     |   6 +
+ .../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c   |   7 +
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c  |  11 +
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c |   3 +
+ drivers/gpu/drm/amd/display/dc/dm_services.h  |  14 +
+ .../gpu/drm/amd/display/dc/inc/reg_helper.h   |  22 ++
+ drivers/gpu/drm/amd/display/dc/os_types.h     |   2 +
+ 14 files changed, 633 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
+index a160512a2f04..6fe39f6392c7 100644
+--- a/drivers/gpu/drm/amd/display/dc/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/Makefile
+@@ -70,5 +70,9 @@ AMD_DM_REG_UPDATE = $(addprefix $(AMDDALPATH)/dc/,dc_helper.o)
+ AMD_DISPLAY_FILES += $(AMD_DISPLAY_CORE)
+ AMD_DISPLAY_FILES += $(AMD_DM_REG_UPDATE)
+ 
+-
++ifdef CONFIG_DRM_AMD_DC_DMUB
++DC_DMUB += dc_dmub_srv.o
++AMD_DISPLAY_DMUB = $(addprefix $(AMDDALPATH)/dc/,$(DC_DMUB))
++AMD_DISPLAY_FILES += $(AMD_DISPLAY_DMUB)
++endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+index bb2e8105e6ab..a3d890050e39 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+@@ -37,6 +37,10 @@
+ #include "bios_parser_types_internal2.h"
+ #include "amdgpu.h"
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++#include "dc_dmub_srv.h"
++#include "dc.h"
++#endif
+ 
+ #define DC_LOGGER \
+ 	bp->base.ctx->logger
+@@ -103,6 +107,21 @@ static void init_dig_encoder_control(struct bios_parser *bp)
+ 	}
+ }
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++static void encoder_control_dmcub(
++		struct dc_dmub_srv *dmcub,
++		struct dig_encoder_stream_setup_parameters_v1_5 *dig)
++{
++	struct dmub_rb_cmd_digx_encoder_control encoder_control = { 0 };
++
++	encoder_control.header.type = DMUB_CMD__DIGX_ENCODER_CONTROL;
++	encoder_control.encoder_control.dig.stream_param = *dig;
++
++	dc_dmub_srv_cmd_queue(dmcub, &encoder_control.header);
++	dc_dmub_srv_cmd_execute(dmcub);
++	dc_dmub_srv_wait_idle(dmcub);
++}
++#endif
+ static enum bp_result encoder_control_digx_v1_5(
+ 	struct bios_parser *bp,
+ 	struct bp_encoder_control *cntl)
+@@ -154,6 +173,13 @@ static enum bp_result encoder_control_digx_v1_5(
+ 		default:
+ 			break;
+ 		}
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	if (bp->base.ctx->dc->ctx->dmub_srv &&
++	    bp->base.ctx->dc->debug.dmub_command_table) {
++		encoder_control_dmcub(bp->base.ctx->dmub_srv, &params);
++		return BP_RESULT_OK;
++	}
++#endif
+ 
+ 	if (EXEC_BIOS_CMD_TABLE(digxencodercontrol, params))
+ 		result = BP_RESULT_OK;
+@@ -190,7 +216,21 @@ static void init_transmitter_control(struct bios_parser *bp)
+ 		break;
+ 	}
+ }
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++static void transmitter_control_dmcub(
++		struct dc_dmub_srv *dmcub,
++		struct dig_transmitter_control_parameters_v1_6 *dig)
++{
++	struct dmub_rb_cmd_dig1_transmitter_control transmitter_control;
++
++	transmitter_control.header.type = DMUB_CMD__DIG1_TRANSMITTER_CONTROL;
++	transmitter_control.transmitter_control.dig = *dig;
+ 
++	dc_dmub_srv_cmd_queue(dmcub, &transmitter_control.header);
++	dc_dmub_srv_cmd_execute(dmcub);
++	dc_dmub_srv_wait_idle(dmcub);
++}
++#endif
+ static enum bp_result transmitter_control_v1_6(
+ 	struct bios_parser *bp,
+ 	struct bp_transmitter_control *cntl)
+@@ -223,6 +263,14 @@ static enum bp_result transmitter_control_v1_6(
+ 	}
+ 
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	if (bp->base.ctx->dc->ctx->dmub_srv &&
++	    bp->base.ctx->dc->debug.dmub_command_table) {
++		transmitter_control_dmcub(bp->base.ctx->dmub_srv, &ps.param);
++		return BP_RESULT_OK;
++	}
++#endif
++
+ /*color_depth not used any more, driver has deep color factor in the Phyclk*/
+ 	if (EXEC_BIOS_CMD_TABLE(dig1transmittercontrol, ps))
+ 		result = BP_RESULT_OK;
+@@ -255,7 +303,21 @@ static void init_set_pixel_clock(struct bios_parser *bp)
+ 	}
+ }
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++static void set_pixel_clock_dmcub(
++		struct dc_dmub_srv *dmcub,
++		struct set_pixel_clock_parameter_v1_7 *clk)
++{
++	struct dmub_rb_cmd_set_pixel_clock pixel_clock = { 0 };
+ 
++	pixel_clock.header.type     = DMUB_CMD__SET_PIXEL_CLOCK;
++	pixel_clock.pixel_clock.clk = *clk;
++
++	dc_dmub_srv_cmd_queue(dmcub, &pixel_clock.header);
++	dc_dmub_srv_cmd_execute(dmcub);
++	dc_dmub_srv_wait_idle(dmcub);
++}
++#endif
+ 
+ static enum bp_result set_pixel_clock_v7(
+ 	struct bios_parser *bp,
+@@ -331,6 +393,13 @@ static enum bp_result set_pixel_clock_v7(
+ 		if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK)
+ 			clk.miscinfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++		if (bp->base.ctx->dc->ctx->dmub_srv &&
++		    bp->base.ctx->dc->debug.dmub_command_table) {
++			set_pixel_clock_dmcub(bp->base.ctx->dmub_srv, &clk);
++			return BP_RESULT_OK;
++		}
++#endif
+ 		if (EXEC_BIOS_CMD_TABLE(setpixelclock, clk))
+ 			result = BP_RESULT_OK;
+ 	}
+@@ -584,7 +653,21 @@ static void init_enable_disp_power_gating(
+ 		break;
+ 	}
+ }
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++static void enable_disp_power_gating_dmcub(
++	struct dc_dmub_srv *dmcub,
++	struct enable_disp_power_gating_parameters_v2_1 *pwr)
++{
++	struct dmub_rb_cmd_enable_disp_power_gating power_gating;
++
++	power_gating.header.type      = DMUB_CMD__ENABLE_DISP_POWER_GATING;
++	power_gating.power_gating.pwr = *pwr;
+ 
++	dc_dmub_srv_cmd_queue(dmcub, &power_gating.header);
++	dc_dmub_srv_cmd_execute(dmcub);
++	dc_dmub_srv_wait_idle(dmcub);
++}
++#endif
+ static enum bp_result enable_disp_power_gating_v2_1(
+ 	struct bios_parser *bp,
+ 	enum controller_id crtc_id,
+@@ -604,6 +687,14 @@ static enum bp_result enable_disp_power_gating_v2_1(
+ 	ps.param.enable =
+ 		bp->cmd_helper->disp_power_gating_action_to_atom(action);
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	if (bp->base.ctx->dc->ctx->dmub_srv &&
++	    bp->base.ctx->dc->debug.dmub_command_table) {
++		enable_disp_power_gating_dmcub(bp->base.ctx->dmub_srv,
++					       &ps.param);
++		return BP_RESULT_OK;
++	}
++#endif
+ 	if (EXEC_BIOS_CMD_TABLE(enabledisppowergating, ps.param))
+ 		result = BP_RESULT_OK;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 3d38e7e071a4..9ddc0124cda1 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -56,6 +56,10 @@
+ 
+ #include "dc_link_dp.h"
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++#include "dc_dmub_srv.h"
++#endif
++
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dsc.h"
+ #endif
+@@ -2399,6 +2403,10 @@ void dc_set_power_state(
+ 	switch (power_state) {
+ 	case DC_ACPI_CM_POWER_STATE_D0:
+ 		dc_resource_state_construct(dc, dc->current_state);
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++		if (dc->ctx->dmub_srv)
++			dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
++#endif
+ 
+ 		dc->hwss.init_hw(dc);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 0416a17b0897..33828f03fe9e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -112,6 +112,9 @@ struct dc_caps {
+ 	bool disable_dp_clk_share;
+ 	bool psp_setup_panel_mode;
+ 	bool extended_aux_timeout_support;
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	bool dmcub_support;
++#endif
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	bool hw_3d_lut;
+ #endif
+@@ -401,6 +404,11 @@ struct dc_debug_options {
+ 	unsigned int force_odm_combine; //bit vector based on otg inst
+ 	unsigned int force_fclk_khz;
+ 	bool disable_tri_buf;
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	bool dmub_offload_enabled;
++	bool dmcub_emulation;
++	bool dmub_command_table; /* for testing only */
++#endif
+ 	struct dc_bw_validation_profile bw_val_profile;
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	bool disable_fec;
+@@ -558,6 +566,10 @@ struct dc_init_data {
+ 	struct dc_bios *vbios_override;
+ 	enum dce_environment dce_environment;
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	struct dmub_offload_funcs *dmub_if;
++	struct dc_reg_helper_state *dmub_offload;
++#endif
+ 	struct dc_config flags;
+ 	uint32_t log_mask;
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+new file mode 100644
+index 000000000000..61cefe0a3790
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+@@ -0,0 +1,119 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "dc.h"
++#include "dc_dmub_srv.h"
++#include "../dmub/inc/dmub_srv.h"
++
++static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc,
++				  struct dmub_srv *dmub)
++{
++	dc_srv->dmub = dmub;
++	dc_srv->ctx = dc->ctx;
++}
++
++struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub)
++{
++	struct dc_dmub_srv *dc_srv =
++		kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL);
++
++	if (dc_srv == NULL) {
++		BREAK_TO_DEBUGGER();
++		return NULL;
++	}
++
++	dc_dmub_srv_construct(dc_srv, dc, dmub);
++
++	return dc_srv;
++}
++
++void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv)
++{
++	if (*dmub_srv) {
++		kfree(*dmub_srv);
++		*dmub_srv = NULL;
++	}
++}
++
++void dc_dmub_srv_cmd_queue(struct dc_dmub_srv *dc_dmub_srv,
++			   struct dmub_cmd_header *cmd)
++{
++	struct dmub_srv *dmub = dc_dmub_srv->dmub;
++	struct dc_context *dc_ctx = dc_dmub_srv->ctx;
++	enum dmub_status status;
++
++	status = dmub_srv_cmd_queue(dmub, cmd);
++	if (status == DMUB_STATUS_OK)
++		return;
++
++	if (status != DMUB_STATUS_QUEUE_FULL)
++		goto error;
++
++	/* Execute and wait for queue to become empty again. */
++	dc_dmub_srv_cmd_execute(dc_dmub_srv);
++	dc_dmub_srv_wait_idle(dc_dmub_srv);
++
++	/* Requeue the command. */
++	status = dmub_srv_cmd_queue(dmub, cmd);
++	if (status == DMUB_STATUS_OK)
++		return;
++
++error:
++	DC_ERROR("Error queuing DMUB command: status=%d\n", status);
++}
++
++void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv)
++{
++	struct dmub_srv *dmub = dc_dmub_srv->dmub;
++	struct dc_context *dc_ctx = dc_dmub_srv->ctx;
++	enum dmub_status status;
++
++	status = dmub_srv_cmd_execute(dmub);
++	if (status != DMUB_STATUS_OK)
++		DC_ERROR("Error starting DMUB exeuction: status=%d\n", status);
++}
++
++void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
++{
++	struct dmub_srv *dmub = dc_dmub_srv->dmub;
++	struct dc_context *dc_ctx = dc_dmub_srv->ctx;
++	enum dmub_status status;
++
++	status = dmub_srv_wait_for_idle(dmub, 100000);
++	if (status != DMUB_STATUS_OK)
++		DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);
++}
++
++void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv)
++{
++	struct dmub_srv *dmub = dc_dmub_srv->dmub;
++	struct dc_context *dc_ctx = dc_dmub_srv->ctx;
++	enum dmub_status status;
++
++	status = dmub_srv_wait_for_phy_init(dmub, 1000000);
++	if (status != DMUB_STATUS_OK)
++		DC_ERROR("Error waiting for DMUB phy init: status=%d\n",
++			 status);
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+new file mode 100644
+index 000000000000..754b6077539c
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+@@ -0,0 +1,60 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_DC_SRV_H_
++#define _DMUB_DC_SRV_H_
++
++#include "os_types.h"
++#include "../dmub/inc/dmub_cmd.h"
++
++struct dmub_srv;
++struct dmub_cmd_header;
++
++struct dc_reg_helper_state {
++	bool gather_in_progress;
++	uint32_t same_addr_count;
++	bool should_burst_write;
++	union dmub_rb_cmd cmd_data;
++	unsigned int reg_seq_count;
++};
++
++struct dc_dmub_srv {
++	struct dmub_srv *dmub;
++	struct dc_reg_helper_state reg_helper_offload;
++
++	struct dc_context *ctx;
++	void *dm;
++};
++
++void dc_dmub_srv_cmd_queue(struct dc_dmub_srv *dc_dmub_srv,
++			   struct dmub_cmd_header *cmd);
++
++void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv);
++
++void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv);
++
++void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv);
++
++#endif /* _DMUB_DC_SRV_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
+index 2d0acf109360..adfc6e9b59b1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
++++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
+@@ -29,6 +29,76 @@
+ #include "dm_services.h"
+ #include <stdarg.h>
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++#include "dc.h"
++#include "dc_dmub_srv.h"
++
++static inline void submit_dmub_read_modify_write(
++	struct dc_reg_helper_state *offload,
++	const struct dc_context *ctx)
++{
++	struct dmub_rb_cmd_read_modify_write *cmd_buf = &offload->cmd_data.read_modify_write;
++	bool gather = false;
++
++	offload->should_burst_write =
++			(offload->same_addr_count == (DMUB_READ_MODIFY_WRITE_SEQ__MAX - 1));
++	cmd_buf->header.payload_bytes =
++			sizeof(struct dmub_cmd_read_modify_write_sequence) * offload->reg_seq_count;
++
++	gather = ctx->dmub_srv->reg_helper_offload.gather_in_progress;
++	ctx->dmub_srv->reg_helper_offload.gather_in_progress = false;
++
++	dc_dmub_srv_cmd_queue(ctx->dmub_srv, &cmd_buf->header);
++
++	ctx->dmub_srv->reg_helper_offload.gather_in_progress = gather;
++
++	memset(cmd_buf, 0, sizeof(*cmd_buf));
++
++	offload->reg_seq_count = 0;
++	offload->same_addr_count = 0;
++}
++
++static inline void submit_dmub_burst_write(
++	struct dc_reg_helper_state *offload,
++	const struct dc_context *ctx)
++{
++	struct dmub_rb_cmd_burst_write *cmd_buf = &offload->cmd_data.burst_write;
++	bool gather = false;
++
++	cmd_buf->header.payload_bytes =
++			sizeof(uint32_t) * offload->reg_seq_count;
++
++	gather = ctx->dmub_srv->reg_helper_offload.gather_in_progress;
++	ctx->dmub_srv->reg_helper_offload.gather_in_progress = false;
++
++	dc_dmub_srv_cmd_queue(ctx->dmub_srv, &cmd_buf->header);
++
++	ctx->dmub_srv->reg_helper_offload.gather_in_progress = gather;
++
++	memset(cmd_buf, 0, sizeof(*cmd_buf));
++
++	offload->reg_seq_count = 0;
++}
++
++static inline void submit_dmub_reg_wait(
++		struct dc_reg_helper_state *offload,
++		const struct dc_context *ctx)
++{
++	struct dmub_rb_cmd_reg_wait *cmd_buf = &offload->cmd_data.reg_wait;
++	bool gather = false;
++
++	gather = ctx->dmub_srv->reg_helper_offload.gather_in_progress;
++	ctx->dmub_srv->reg_helper_offload.gather_in_progress = false;
++
++	dc_dmub_srv_cmd_queue(ctx->dmub_srv, &cmd_buf->header);
++
++	memset(cmd_buf, 0, sizeof(*cmd_buf));
++	offload->reg_seq_count = 0;
++
++	ctx->dmub_srv->reg_helper_offload.gather_in_progress = gather;
++}
++#endif
++
+ struct dc_reg_value_masks {
+ 	uint32_t value;
+ 	uint32_t mask;
+@@ -74,6 +144,100 @@ static void set_reg_field_values(struct dc_reg_value_masks *field_value_mask,
+ 	}
+ }
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++static void dmub_flush_buffer_execute(
++		struct dc_reg_helper_state *offload,
++		const struct dc_context *ctx)
++{
++	submit_dmub_read_modify_write(offload, ctx);
++	dc_dmub_srv_cmd_execute(ctx->dmub_srv);
++}
++
++static void dmub_flush_burst_write_buffer_execute(
++		struct dc_reg_helper_state *offload,
++		const struct dc_context *ctx)
++{
++	submit_dmub_burst_write(offload, ctx);
++	dc_dmub_srv_cmd_execute(ctx->dmub_srv);
++}
++
++static bool dmub_reg_value_burst_set_pack(const struct dc_context *ctx, uint32_t addr,
++		uint32_t reg_val)
++{
++	struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;
++	struct dmub_rb_cmd_burst_write *cmd_buf = &offload->cmd_data.burst_write;
++
++	/* flush command if buffer is full */
++	if (offload->reg_seq_count == DMUB_BURST_WRITE_VALUES__MAX)
++		dmub_flush_burst_write_buffer_execute(offload, ctx);
++
++	if (offload->cmd_data.cmd_common.header.type == DMUB_CMD__REG_SEQ_BURST_WRITE &&
++			addr != cmd_buf->addr) {
++		dmub_flush_burst_write_buffer_execute(offload, ctx);
++		return false;
++	}
++
++	cmd_buf->header.type = DMUB_CMD__REG_SEQ_BURST_WRITE;
++	cmd_buf->addr = addr;
++	cmd_buf->write_values[offload->reg_seq_count] = reg_val;
++	offload->reg_seq_count++;
++
++	return true;
++}
++
++static uint32_t dmub_reg_value_pack(const struct dc_context *ctx, uint32_t addr,
++		struct dc_reg_value_masks *field_value_mask)
++{
++	struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;
++	struct dmub_rb_cmd_read_modify_write *cmd_buf = &offload->cmd_data.read_modify_write;
++	struct dmub_cmd_read_modify_write_sequence *seq;
++
++	/* flush command if buffer is full */
++	if (offload->cmd_data.cmd_common.header.type != DMUB_CMD__REG_SEQ_BURST_WRITE &&
++			offload->reg_seq_count == DMUB_READ_MODIFY_WRITE_SEQ__MAX)
++		dmub_flush_buffer_execute(offload, ctx);
++
++	if (offload->should_burst_write) {
++		if (dmub_reg_value_burst_set_pack(ctx, addr, field_value_mask->value))
++			return field_value_mask->value;
++		else
++			offload->should_burst_write = false;
++	}
++
++	/* pack commands */
++	cmd_buf->header.type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE;
++	seq = &cmd_buf->seq[offload->reg_seq_count];
++
++	if (offload->reg_seq_count) {
++		if (cmd_buf->seq[offload->reg_seq_count - 1].addr == addr)
++			offload->same_addr_count++;
++		else
++			offload->same_addr_count = 0;
++	}
++
++	seq->addr = addr;
++	seq->modify_mask = field_value_mask->mask;
++	seq->modify_value = field_value_mask->value;
++	offload->reg_seq_count++;
++
++	return field_value_mask->value;
++}
++
++static void dmub_reg_wait_done_pack(const struct dc_context *ctx, uint32_t addr,
++		uint32_t mask, uint32_t shift, uint32_t condition_value, uint32_t time_out_us)
++{
++	struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;
++	struct dmub_rb_cmd_reg_wait *cmd_buf = &offload->cmd_data.reg_wait;
++
++	cmd_buf->header.type = DMUB_CMD__REG_REG_WAIT;
++	cmd_buf->reg_wait.addr = addr;
++	cmd_buf->reg_wait.condition_field_value = mask & (condition_value << shift);
++	cmd_buf->reg_wait.mask = mask;
++	cmd_buf->reg_wait.time_out_us = time_out_us;
++}
++
++#endif
++
+ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
+ 		uint32_t addr, int n,
+ 		uint8_t shift1, uint32_t mask1, uint32_t field_value1,
+@@ -90,6 +254,13 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
+ 
+ 	va_end(ap);
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	if (ctx->dmub_srv &&
++	    ctx->dmub_srv->reg_helper_offload.gather_in_progress)
++		return dmub_reg_value_pack(ctx, addr, &field_value_mask);
++		/* todo: return void so we can decouple code running in driver from register states */
++#endif
++
+ 	/* mmio write directly */
+ 	reg_val = dm_read_reg(ctx, addr);
+ 	reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
+@@ -115,6 +286,13 @@ uint32_t generic_reg_set_ex(const struct dc_context *ctx,
+ 
+ 	/* mmio write directly */
+ 	reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	if (ctx->dmub_srv &&
++	    ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
++		return dmub_reg_value_burst_set_pack(ctx, addr, reg_val);
++		/* todo: return void so we can decouple code running in driver from register states */
++	}
++#endif
+ 	dm_write_reg(ctx, addr, reg_val);
+ 	return reg_val;
+ }
+@@ -131,6 +309,16 @@ uint32_t dm_read_reg_func(
+ 		return 0;
+ 	}
+ #endif
++
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	if (ctx->dmub_srv &&
++	    ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
++	    !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
++		ASSERT(false);
++		return 0;
++	}
++#endif
++
+ 	value = cgs_read_register(ctx->cgs_device, address);
+ 	trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
+ 
+@@ -296,6 +484,15 @@ void generic_reg_wait(const struct dc_context *ctx,
+ 	uint32_t reg_val;
+ 	int i;
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	if (ctx->dmub_srv &&
++	    ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
++		dmub_reg_wait_done_pack(ctx, addr, mask, shift, condition_value,
++				delay_between_poll_us * time_out_num_tries);
++		return;
++	}
++#endif
++
+ 	/* something is terribly wrong if time out is > 200ms. (5Hz) */
+ 	ASSERT(delay_between_poll_us * time_out_num_tries <= 3000000);
+ 
+@@ -342,6 +539,13 @@ uint32_t generic_read_indirect_reg(const struct dc_context *ctx,
+ 		uint32_t index)
+ {
+ 	uint32_t value = 0;
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	// when reg read, there should not be any offload.
++	if (ctx->dmub_srv &&
++	    ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
++		ASSERT(false);
++	}
++#endif
+ 
+ 	dm_write_reg(ctx, addr_index, index);
+ 	value = dm_read_reg(ctx, addr_data);
+@@ -379,3 +583,72 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
+ 
+ 	return reg_val;
+ }
++
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++void reg_sequence_start_gather(const struct dc_context *ctx)
++{
++	/* if reg sequence is supported and enabled, set flag to
++	 * indicate we want to have REG_SET, REG_UPDATE macro build
++	 * reg sequence command buffer rather than MMIO directly.
++	 */
++
++	if (ctx->dmub_srv && ctx->dc->debug.dmub_offload_enabled) {
++		struct dc_reg_helper_state *offload =
++			&ctx->dmub_srv->reg_helper_offload;
++
++		/* caller sequence mismatch.  need to debug caller.  offload will not work!!! */
++		ASSERT(!offload->gather_in_progress);
++
++		offload->gather_in_progress = true;
++	}
++}
++
++void reg_sequence_start_execute(const struct dc_context *ctx)
++{
++	struct dc_reg_helper_state *offload;
++
++	if (!ctx->dmub_srv)
++		return;
++
++	offload = &ctx->dmub_srv->reg_helper_offload;
++
++	if (offload && offload->gather_in_progress) {
++		offload->gather_in_progress = false;
++		offload->should_burst_write = false;
++		switch (offload->cmd_data.cmd_common.header.type) {
++		case DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE:
++			submit_dmub_read_modify_write(offload, ctx);
++			break;
++		case DMUB_CMD__REG_REG_WAIT:
++			submit_dmub_reg_wait(offload, ctx);
++			break;
++		case DMUB_CMD__REG_SEQ_BURST_WRITE:
++			submit_dmub_burst_write(offload, ctx);
++			break;
++		default:
++			return;
++		}
++
++		dc_dmub_srv_cmd_execute(ctx->dmub_srv);
++	}
++}
++
++void reg_sequence_wait_done(const struct dc_context *ctx)
++{
++	/* callback to DM to poll for last submission done*/
++	struct dc_reg_helper_state *offload;
++
++	if (!ctx->dmub_srv)
++		return;
++
++	offload = &ctx->dmub_srv->reg_helper_offload;
++
++	if (offload &&
++	    ctx->dc->debug.dmub_offload_enabled &&
++	    !ctx->dc->debug.dmcub_emulation) {
++		dc_dmub_srv_wait_idle(ctx->dmub_srv);
++	}
++}
++
++
++#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
+index d9be8fc3889f..fb70ed9b351f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
+@@ -48,6 +48,9 @@ struct dc_stream_state;
+ struct dc_link;
+ struct dc_sink;
+ struct dal;
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++struct dc_dmub_srv;
++#endif
+ 
+ /********************************
+  * Environment definitions
+@@ -109,6 +112,9 @@ struct dc_context {
+ 	uint32_t dc_sink_id_count;
+ 	uint32_t dc_stream_id_count;
+ 	uint64_t fbc_gpu_addr;
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	struct dc_dmub_srv *dmub_srv;
++#endif
+ #ifdef CONFIG_DRM_AMD_DC_HDCP
+ 	struct cp_psp cp_psp;
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+index aa0c7a7d13a0..41a0e53d2ba4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+@@ -352,6 +352,9 @@ void dpp1_cm_program_regamma_lut(struct dpp *dpp_base,
+ 	uint32_t i;
+ 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	REG_SEQ_START();
++#endif
+ 	for (i = 0 ; i < num; i++) {
+ 		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);
+ 		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);
+@@ -630,6 +633,10 @@ void dpp1_set_degamma(
+ 		BREAK_TO_DEBUGGER();
+ 		break;
+ 	}
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	REG_SEQ_SUBMIT();
++	REG_SEQ_WAIT_DONE();
++#endif
+ }
+ 
+ void dpp1_degamma_ram_select(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+index 5a188b2bc033..2417d933ef2b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+@@ -345,6 +345,11 @@ static void mpc20_program_ogam_pwl(
+ 	uint32_t i;
+ 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	PERF_TRACE();
++	REG_SEQ_START();
++#endif
++
+ 	for (i = 0 ; i < num; i++) {
+ 		REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg);
+ 		REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].green_reg);
+@@ -463,6 +468,12 @@ void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)
+ 		ASSERT(!mpc_disabled);
+ 		ASSERT(!mpc_idle);
+ 	}
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	REG_SEQ_SUBMIT();
++	PERF_TRACE();
++	REG_SEQ_WAIT_DONE();
++	PERF_TRACE();
++#endif
+ }
+ 
+ static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 0792b1c2e673..30a246ebe842 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1699,6 +1699,9 @@ static bool construct(
+ 	dc->caps.post_blend_color_processing = true;
+ 	dc->caps.force_dp_tps4_for_cp2520 = true;
+ 	dc->caps.extended_aux_timeout_support = true;
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++	dc->caps.dmcub_support = true;
++#endif
+ 
+ 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
+ 		dc->debug = debug_defaults_drv;
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
+index 1a0429744630..0a3891edfd94 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
+@@ -40,6 +40,11 @@
+ 
+ #undef DEPRECATED
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++struct dmub_srv;
++struct dc_dmub_srv;
++
++#endif
+ irq_handler_idx dm_register_interrupt(
+ 	struct dc_context *ctx,
+ 	struct dc_interrupt_params *int_params,
+@@ -139,6 +144,15 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
+ 		uint32_t addr, int n,
+ 		uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
+ 
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub);
++void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv);
++
++void reg_sequence_start_gather(const struct dc_context *ctx);
++void reg_sequence_start_execute(const struct dc_context *ctx);
++void reg_sequence_wait_done(const struct dc_context *ctx);
++#endif
++
+ #define FD(reg_field)	reg_field ## __SHIFT, \
+ 						reg_field ## _MASK
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+index 8503d9cc4763..a9a9657c095a 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+@@ -485,4 +485,26 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
+ 		uint8_t shift1, uint32_t mask1, uint32_t field_value1,
+ 		...);
+ 
++
++#ifdef CONFIG_DRM_AMD_DC_DMUB
++/* register offload macros
++ *
++ * instead of MMIO to register directly, in some cases we want
++ * to gather register sequence and execute the register sequence
++ * from another thread so we optimize time required for lengthy ops
++ */
++
++/* start gathering register sequence */
++#define REG_SEQ_START() \
++	reg_sequence_start_gather(CTX)
++
++/* start execution of register sequence gathered since REG_SEQ_START */
++#define REG_SEQ_SUBMIT() \
++	reg_sequence_start_execute(CTX)
++
++/* wait for the last REG_SEQ_SUBMIT to finish */
++#define REG_SEQ_WAIT_DONE() \
++	reg_sequence_wait_done(CTX)
++#endif
++
+ #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h
+index f20996e71274..77b97559e847 100644
+--- a/drivers/gpu/drm/amd/display/dc/os_types.h
++++ b/drivers/gpu/drm/amd/display/dc/os_types.h
+@@ -26,6 +26,8 @@
+ #ifndef _OS_TYPES_H_
+ #define _OS_TYPES_H_
+ 
++#include <linux/slab.h>
++
+ #include <asm/byteorder.h>
+ #include <linux/types.h>
+ #include <drm/drmP.h>
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4332-drm-amd-display-Register-DMUB-service-with-DC.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4332-drm-amd-display-Register-DMUB-service-with-DC.patch
new file mode 100644
index 00000000..40b9de21
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4332-drm-amd-display-Register-DMUB-service-with-DC.patch
@@ -0,0 +1,61 @@
+From 5f8b8c91bfa83debf11fe47831bc49973942349f Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Mon, 28 Oct 2019 09:07:30 -0400
+Subject: [PATCH 4332/4736] drm/amd/display: Register DMUB service with DC
+
+[Why]
+DC can utilize the DMUB server to send commands to the DMUB but it's
+the DM responsibility to pass it the service to use.
+
+[How]
+Create the dc_dmub_srv after we finish initializing the dmub_srv.
+Cleanup the dc_dmub_srv before destroying the dmub_srv or dc.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index e226e526c4df..f47761a2ec9b 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -34,6 +34,7 @@
+ #include "dmub/inc/dmub_srv.h"
+ #include "dc/inc/hw/dmcu.h"
+ #include "dc/inc/hw/abm.h"
++#include "dc/dc_dmub_srv.h"
+ #endif
+ 
+ #include "vid.h"
+@@ -801,6 +802,12 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
+ 		abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
+ 	}
+ 
++	adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
++	if (!adev->dm.dc->ctx->dmub_srv) {
++		DRM_ERROR("Couldn't allocate DC DMUB server!\n");
++		return -ENOMEM;
++	}
++
+ 	DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
+ 		adev->dm.dmcub_fw_version);
+ 
+@@ -939,6 +946,11 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ 		DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
+ #endif
+ #ifdef CONFIG_DRM_AMD_DC_DMUB
++	if (adev->dm.dc->ctx->dmub_srv) {
++		dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
++		adev->dm.dc->ctx->dmub_srv = NULL;
++	}
++
+ 	if (adev->dm.dmub_bo)
+ 		amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
+ 				      &adev->dm.dmub_bo_gpu_addr,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4333-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DMUB-guards.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4333-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DMUB-guards.patch
new file mode 100644
index 00000000..8d9838b6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4333-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DMUB-guards.patch
@@ -0,0 +1,794 @@
+From b24c998450cfa186de1a9efd0f3366841577f526 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Mon, 28 Oct 2019 09:22:34 -0400
+Subject: [PATCH 4333/4736] drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards
+
+[Why]
+Support for DMUB only depends on support for DC. It doesn't use floating
+point so we don't need to guard it by any specific DCN revision.
+
+[How]
+Drop the guards and cleanup the newlines around each one.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/Kconfig           |  6 -----
+ drivers/gpu/drm/amd/display/Makefile          | 12 +++------
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 +-------------
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  4 ---
+ drivers/gpu/drm/amd/display/dc/Makefile       |  3 ---
+ .../drm/amd/display/dc/bios/command_table2.c  | 27 ++++++-------------
+ drivers/gpu/drm/amd/display/dc/core/dc.c      |  6 +----
+ drivers/gpu/drm/amd/display/dc/dc.h           |  7 +----
+ drivers/gpu/drm/amd/display/dc/dc_helper.c    | 22 +++------------
+ drivers/gpu/drm/amd/display/dc/dc_types.h     |  5 +---
+ .../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c   |  6 ++---
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c |  5 +---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c  |  5 +---
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c |  2 --
+ drivers/gpu/drm/amd/display/dc/dm_services.h  |  4 ---
+ .../gpu/drm/amd/display/dc/inc/reg_helper.h   |  3 ---
+ drivers/gpu/drm/amd/display/dmub/src/Makefile |  2 --
+ 17 files changed, 22 insertions(+), 117 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
+index d9ee189aebf0..9eae7c67ceb5 100644
+--- a/drivers/gpu/drm/amd/display/Kconfig
++++ b/drivers/gpu/drm/amd/display/Kconfig
+@@ -29,7 +29,6 @@ config DRM_AMD_DC_DCN2_1
+ 	bool "DCN 2.1 family"
+ 	depends on DRM_AMD_DC && X86
+ 	depends on DRM_AMD_DC_DCN2_0
+-	select DRM_AMD_DC_DMUB
+ 	help
+ 	  Choose this option if you want to have
+ 	  Renoir support for display engine
+@@ -52,11 +51,6 @@ config DRM_AMD_DC_HDCP
+ 	 if you want to support
+ 	 HDCP authentication
+ 
+-config DRM_AMD_DC_DMUB
+-        def_bool n
+-        help
+-          DMUB support for display engine
+-
+ config DEBUG_KERNEL_DC
+ 	bool "Enable kgdb break in DC"
+ 	depends on DRM_AMD_DC
+diff --git a/drivers/gpu/drm/amd/display/Makefile b/drivers/gpu/drm/amd/display/Makefile
+index 3c7332be4a89..2633de77de5e 100644
+--- a/drivers/gpu/drm/amd/display/Makefile
++++ b/drivers/gpu/drm/amd/display/Makefile
+@@ -34,27 +34,21 @@ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/freesync
+ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/color
+ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/info_packet
+ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/power
++subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dmub/inc
++
+ ifdef CONFIG_DRM_AMD_DC_HDCP
+ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/hdcp
+ endif
+ 
+-ifdef CONFIG_DRM_AMD_DC_DMUB
+-subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dmub/inc
+-endif
+-
+ #TODO: remove when Timing Sync feature is complete
+ subdir-ccflags-y += -DBUILD_FEATURE_TIMING_SYNC=0
+ 
+-DAL_LIBS = amdgpu_dm dc	modules/freesync modules/color modules/info_packet modules/power
++DAL_LIBS = amdgpu_dm dc	modules/freesync modules/color modules/info_packet modules/power dmub/src
+ 
+ ifdef CONFIG_DRM_AMD_DC_HDCP
+ DAL_LIBS += modules/hdcp
+ endif
+ 
+-ifdef CONFIG_DRM_AMD_DC_DMUB
+-DAL_LIBS += dmub/src
+-endif
+-
+ AMD_DAL = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/,$(DAL_LIBS)))
+ 
+ include $(AMD_DAL)
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index f47761a2ec9b..5ef3b7e842e4 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -30,12 +30,10 @@
+ #include "dc.h"
+ #include "dc/inc/core_types.h"
+ #include "dal_asic_id.h"
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ #include "dmub/inc/dmub_srv.h"
+ #include "dc/inc/hw/dmcu.h"
+ #include "dc/inc/hw/abm.h"
+ #include "dc/dc_dmub_srv.h"
+-#endif
+ 
+ #include "vid.h"
+ #include "amdgpu.h"
+@@ -90,10 +88,9 @@
+ #include "modules/power/power_helpers.h"
+ #include "modules/inc/mod_info_packet.h"
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
+ MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
+-#endif
++
+ #define FIRMWARE_RAVEN_DMCU		"amdgpu/raven_dmcu.bin"
+ MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
+ 
+@@ -675,7 +672,6 @@ void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
+ 	}
+ }
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ static int dm_dmub_hw_init(struct amdgpu_device *adev)
+ {
+ 	const unsigned int psp_header_bytes = 0x100;
+@@ -814,7 +810,6 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
+-#endif
+ 
+ 
+ 
+@@ -824,9 +819,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ #ifdef CONFIG_DRM_AMD_DC_HDCP
+ 	struct dc_callback_init init_params;
+ #endif
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	int r;
+-#endif
+ 	adev->dm.ddev = adev->ddev;
+ 	adev->dm.adev = adev;
+ 
+@@ -902,14 +895,12 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ 
+ 	dc_hardware_init(adev->dm.dc);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	r = dm_dmub_hw_init(adev);
+ 	if (r) {
+ 		DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
+ 		goto error;
+ 	}
+ 
+-#endif
+ 	adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
+ 	if (!adev->dm.freesync_module) {
+ 		DRM_ERROR(
+@@ -945,7 +936,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ 	if (dtn_debugfs_init(adev))
+ 		DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
+ #endif
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	if (adev->dm.dc->ctx->dmub_srv) {
+ 		dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
+ 		adev->dm.dc->ctx->dmub_srv = NULL;
+@@ -955,7 +945,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ 		amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
+ 				      &adev->dm.dmub_bo_gpu_addr,
+ 				      &adev->dm.dmub_bo_cpu_addr);
+-#endif
+ 
+ 	DRM_DEBUG_DRIVER("KMS initialized.\n");
+ 
+@@ -1089,7 +1078,6 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
+ {
+ 	struct amdgpu_device *adev = ctx;
+@@ -1175,19 +1163,15 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
+-#endif
+ static int dm_sw_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	int r;
+ 
+ 	r = dm_dmub_sw_init(adev);
+ 	if (r)
+ 		return r;
+ 
+-#endif
+-
+ 	return load_dmcu_fw(adev);
+ }
+ 
+@@ -1195,7 +1179,6 @@ static int dm_sw_fini(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	if (adev->dm.dmub_srv) {
+ 		dmub_srv_destroy(adev->dm.dmub_srv);
+ 		adev->dm.dmub_srv = NULL;
+@@ -1206,7 +1189,6 @@ static int dm_sw_fini(void *handle)
+ 		adev->dm.dmub_fw = NULL;
+ 	}
+ 
+-#endif
+ 	if(adev->dm.fw_dmcu) {
+ 		release_firmware(adev->dm.fw_dmcu);
+ 		adev->dm.fw_dmcu = NULL;
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+index 27167d2bd654..1fc810bf02af 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+@@ -54,10 +54,8 @@ struct amdgpu_device;
+ struct drm_device;
+ struct amdgpu_dm_irq_handler_data;
+ struct dc;
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ struct amdgpu_bo;
+ struct dmub_srv;
+-#endif
+ 
+ struct common_irq_params {
+ 	struct amdgpu_device *adev;
+@@ -149,7 +147,6 @@ struct amdgpu_display_manager {
+ 	 */
+ 	struct mutex dc_lock;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	/**
+ 	 * @dmub_srv:
+ 	 *
+@@ -194,7 +191,6 @@ struct amdgpu_display_manager {
+ 	 */
+ 	uint32_t dmcub_fw_version;
+ 
+-#endif
+ 	/**
+ 	 *@irq_handler_list_low_tab:
+ 	 *
+diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
+index 6fe39f6392c7..90482b158283 100644
+--- a/drivers/gpu/drm/amd/display/dc/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/Makefile
+@@ -70,9 +70,6 @@ AMD_DM_REG_UPDATE = $(addprefix $(AMDDALPATH)/dc/,dc_helper.o)
+ AMD_DISPLAY_FILES += $(AMD_DISPLAY_CORE)
+ AMD_DISPLAY_FILES += $(AMD_DM_REG_UPDATE)
+ 
+-ifdef CONFIG_DRM_AMD_DC_DMUB
+ DC_DMUB += dc_dmub_srv.o
+ AMD_DISPLAY_DMUB = $(addprefix $(AMDDALPATH)/dc/,$(DC_DMUB))
+ AMD_DISPLAY_FILES += $(AMD_DISPLAY_DMUB)
+-endif
+-
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+index a3d890050e39..1836f16bb7fe 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+@@ -37,10 +37,8 @@
+ #include "bios_parser_types_internal2.h"
+ #include "amdgpu.h"
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ #include "dc_dmub_srv.h"
+ #include "dc.h"
+-#endif
+ 
+ #define DC_LOGGER \
+ 	bp->base.ctx->logger
+@@ -107,7 +105,6 @@ static void init_dig_encoder_control(struct bios_parser *bp)
+ 	}
+ }
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ static void encoder_control_dmcub(
+ 		struct dc_dmub_srv *dmcub,
+ 		struct dig_encoder_stream_setup_parameters_v1_5 *dig)
+@@ -121,7 +118,7 @@ static void encoder_control_dmcub(
+ 	dc_dmub_srv_cmd_execute(dmcub);
+ 	dc_dmub_srv_wait_idle(dmcub);
+ }
+-#endif
++
+ static enum bp_result encoder_control_digx_v1_5(
+ 	struct bios_parser *bp,
+ 	struct bp_encoder_control *cntl)
+@@ -173,13 +170,12 @@ static enum bp_result encoder_control_digx_v1_5(
+ 		default:
+ 			break;
+ 		}
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
++
+ 	if (bp->base.ctx->dc->ctx->dmub_srv &&
+ 	    bp->base.ctx->dc->debug.dmub_command_table) {
+ 		encoder_control_dmcub(bp->base.ctx->dmub_srv, &params);
+ 		return BP_RESULT_OK;
+ 	}
+-#endif
+ 
+ 	if (EXEC_BIOS_CMD_TABLE(digxencodercontrol, params))
+ 		result = BP_RESULT_OK;
+@@ -216,7 +212,7 @@ static void init_transmitter_control(struct bios_parser *bp)
+ 		break;
+ 	}
+ }
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
++
+ static void transmitter_control_dmcub(
+ 		struct dc_dmub_srv *dmcub,
+ 		struct dig_transmitter_control_parameters_v1_6 *dig)
+@@ -230,7 +226,7 @@ static void transmitter_control_dmcub(
+ 	dc_dmub_srv_cmd_execute(dmcub);
+ 	dc_dmub_srv_wait_idle(dmcub);
+ }
+-#endif
++
+ static enum bp_result transmitter_control_v1_6(
+ 	struct bios_parser *bp,
+ 	struct bp_transmitter_control *cntl)
+@@ -262,14 +258,11 @@ static enum bp_result transmitter_control_v1_6(
+ 		__func__, ps.param.symclk_10khz);
+ 	}
+ 
+-
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	if (bp->base.ctx->dc->ctx->dmub_srv &&
+ 	    bp->base.ctx->dc->debug.dmub_command_table) {
+ 		transmitter_control_dmcub(bp->base.ctx->dmub_srv, &ps.param);
+ 		return BP_RESULT_OK;
+ 	}
+-#endif
+ 
+ /*color_depth not used any more, driver has deep color factor in the Phyclk*/
+ 	if (EXEC_BIOS_CMD_TABLE(dig1transmittercontrol, ps))
+@@ -303,7 +296,6 @@ static void init_set_pixel_clock(struct bios_parser *bp)
+ 	}
+ }
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ static void set_pixel_clock_dmcub(
+ 		struct dc_dmub_srv *dmcub,
+ 		struct set_pixel_clock_parameter_v1_7 *clk)
+@@ -317,7 +309,6 @@ static void set_pixel_clock_dmcub(
+ 	dc_dmub_srv_cmd_execute(dmcub);
+ 	dc_dmub_srv_wait_idle(dmcub);
+ }
+-#endif
+ 
+ static enum bp_result set_pixel_clock_v7(
+ 	struct bios_parser *bp,
+@@ -393,13 +384,12 @@ static enum bp_result set_pixel_clock_v7(
+ 		if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK)
+ 			clk.miscinfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 		if (bp->base.ctx->dc->ctx->dmub_srv &&
+ 		    bp->base.ctx->dc->debug.dmub_command_table) {
+ 			set_pixel_clock_dmcub(bp->base.ctx->dmub_srv, &clk);
+ 			return BP_RESULT_OK;
+ 		}
+-#endif
++
+ 		if (EXEC_BIOS_CMD_TABLE(setpixelclock, clk))
+ 			result = BP_RESULT_OK;
+ 	}
+@@ -653,7 +643,7 @@ static void init_enable_disp_power_gating(
+ 		break;
+ 	}
+ }
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
++
+ static void enable_disp_power_gating_dmcub(
+ 	struct dc_dmub_srv *dmcub,
+ 	struct enable_disp_power_gating_parameters_v2_1 *pwr)
+@@ -667,7 +657,7 @@ static void enable_disp_power_gating_dmcub(
+ 	dc_dmub_srv_cmd_execute(dmcub);
+ 	dc_dmub_srv_wait_idle(dmcub);
+ }
+-#endif
++
+ static enum bp_result enable_disp_power_gating_v2_1(
+ 	struct bios_parser *bp,
+ 	enum controller_id crtc_id,
+@@ -687,14 +677,13 @@ static enum bp_result enable_disp_power_gating_v2_1(
+ 	ps.param.enable =
+ 		bp->cmd_helper->disp_power_gating_action_to_atom(action);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	if (bp->base.ctx->dc->ctx->dmub_srv &&
+ 	    bp->base.ctx->dc->debug.dmub_command_table) {
+ 		enable_disp_power_gating_dmcub(bp->base.ctx->dmub_srv,
+ 					       &ps.param);
+ 		return BP_RESULT_OK;
+ 	}
+-#endif
++
+ 	if (EXEC_BIOS_CMD_TABLE(enabledisppowergating, ps.param))
+ 		result = BP_RESULT_OK;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 9ddc0124cda1..82d8b4aff88f 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -55,10 +55,7 @@
+ #include "hubp.h"
+ 
+ #include "dc_link_dp.h"
+-
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ #include "dc_dmub_srv.h"
+-#endif
+ 
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dsc.h"
+@@ -2403,10 +2400,9 @@ void dc_set_power_state(
+ 	switch (power_state) {
+ 	case DC_ACPI_CM_POWER_STATE_D0:
+ 		dc_resource_state_construct(dc, dc->current_state);
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
++
+ 		if (dc->ctx->dmub_srv)
+ 			dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
+-#endif
+ 
+ 		dc->hwss.init_hw(dc);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 33828f03fe9e..30a2783881d9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -112,9 +112,7 @@ struct dc_caps {
+ 	bool disable_dp_clk_share;
+ 	bool psp_setup_panel_mode;
+ 	bool extended_aux_timeout_support;
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	bool dmcub_support;
+-#endif
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	bool hw_3d_lut;
+ #endif
+@@ -404,11 +402,9 @@ struct dc_debug_options {
+ 	unsigned int force_odm_combine; //bit vector based on otg inst
+ 	unsigned int force_fclk_khz;
+ 	bool disable_tri_buf;
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	bool dmub_offload_enabled;
+ 	bool dmcub_emulation;
+ 	bool dmub_command_table; /* for testing only */
+-#endif
+ 	struct dc_bw_validation_profile bw_val_profile;
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	bool disable_fec;
+@@ -566,10 +562,9 @@ struct dc_init_data {
+ 	struct dc_bios *vbios_override;
+ 	enum dce_environment dce_environment;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	struct dmub_offload_funcs *dmub_if;
+ 	struct dc_reg_helper_state *dmub_offload;
+-#endif
++
+ 	struct dc_config flags;
+ 	uint32_t log_mask;
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_0
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
+index adfc6e9b59b1..24e4684034f5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
++++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
+@@ -29,7 +29,6 @@
+ #include "dm_services.h"
+ #include <stdarg.h>
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ #include "dc.h"
+ #include "dc_dmub_srv.h"
+ 
+@@ -97,7 +96,6 @@ static inline void submit_dmub_reg_wait(
+ 
+ 	ctx->dmub_srv->reg_helper_offload.gather_in_progress = gather;
+ }
+-#endif
+ 
+ struct dc_reg_value_masks {
+ 	uint32_t value;
+@@ -144,7 +142,6 @@ static void set_reg_field_values(struct dc_reg_value_masks *field_value_mask,
+ 	}
+ }
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ static void dmub_flush_buffer_execute(
+ 		struct dc_reg_helper_state *offload,
+ 		const struct dc_context *ctx)
+@@ -236,8 +233,6 @@ static void dmub_reg_wait_done_pack(const struct dc_context *ctx, uint32_t addr,
+ 	cmd_buf->reg_wait.time_out_us = time_out_us;
+ }
+ 
+-#endif
+-
+ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
+ 		uint32_t addr, int n,
+ 		uint8_t shift1, uint32_t mask1, uint32_t field_value1,
+@@ -254,12 +249,10 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
+ 
+ 	va_end(ap);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	if (ctx->dmub_srv &&
+ 	    ctx->dmub_srv->reg_helper_offload.gather_in_progress)
+ 		return dmub_reg_value_pack(ctx, addr, &field_value_mask);
+ 		/* todo: return void so we can decouple code running in driver from register states */
+-#endif
+ 
+ 	/* mmio write directly */
+ 	reg_val = dm_read_reg(ctx, addr);
+@@ -286,13 +279,13 @@ uint32_t generic_reg_set_ex(const struct dc_context *ctx,
+ 
+ 	/* mmio write directly */
+ 	reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
++
+ 	if (ctx->dmub_srv &&
+ 	    ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
+ 		return dmub_reg_value_burst_set_pack(ctx, addr, reg_val);
+ 		/* todo: return void so we can decouple code running in driver from register states */
+ 	}
+-#endif
++
+ 	dm_write_reg(ctx, addr, reg_val);
+ 	return reg_val;
+ }
+@@ -310,14 +303,12 @@ uint32_t dm_read_reg_func(
+ 	}
+ #endif
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	if (ctx->dmub_srv &&
+ 	    ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
+ 	    !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
+ 		ASSERT(false);
+ 		return 0;
+ 	}
+-#endif
+ 
+ 	value = cgs_read_register(ctx->cgs_device, address);
+ 	trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
+@@ -484,14 +475,12 @@ void generic_reg_wait(const struct dc_context *ctx,
+ 	uint32_t reg_val;
+ 	int i;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	if (ctx->dmub_srv &&
+ 	    ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
+ 		dmub_reg_wait_done_pack(ctx, addr, mask, shift, condition_value,
+ 				delay_between_poll_us * time_out_num_tries);
+ 		return;
+ 	}
+-#endif
+ 
+ 	/* something is terribly wrong if time out is > 200ms. (5Hz) */
+ 	ASSERT(delay_between_poll_us * time_out_num_tries <= 3000000);
+@@ -539,13 +528,12 @@ uint32_t generic_read_indirect_reg(const struct dc_context *ctx,
+ 		uint32_t index)
+ {
+ 	uint32_t value = 0;
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
++
+ 	// when reg read, there should not be any offload.
+ 	if (ctx->dmub_srv &&
+ 	    ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
+ 		ASSERT(false);
+ 	}
+-#endif
+ 
+ 	dm_write_reg(ctx, addr_index, index);
+ 	value = dm_read_reg(ctx, addr_data);
+@@ -584,7 +572,6 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
+ 	return reg_val;
+ }
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ void reg_sequence_start_gather(const struct dc_context *ctx)
+ {
+ 	/* if reg sequence is supported and enabled, set flag to
+@@ -649,6 +636,3 @@ void reg_sequence_wait_done(const struct dc_context *ctx)
+ 		dc_dmub_srv_wait_idle(ctx->dmub_srv);
+ 	}
+ }
+-
+-
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
+index fb70ed9b351f..7ab7644458e7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
+@@ -48,9 +48,7 @@ struct dc_stream_state;
+ struct dc_link;
+ struct dc_sink;
+ struct dal;
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ struct dc_dmub_srv;
+-#endif
+ 
+ /********************************
+  * Environment definitions
+@@ -112,9 +110,8 @@ struct dc_context {
+ 	uint32_t dc_sink_id_count;
+ 	uint32_t dc_stream_id_count;
+ 	uint64_t fbc_gpu_addr;
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	struct dc_dmub_srv *dmub_srv;
+-#endif
++
+ #ifdef CONFIG_DRM_AMD_DC_HDCP
+ 	struct cp_psp cp_psp;
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+index 41a0e53d2ba4..6f1a312c6a5a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+@@ -352,9 +352,8 @@ void dpp1_cm_program_regamma_lut(struct dpp *dpp_base,
+ 	uint32_t i;
+ 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	REG_SEQ_START();
+-#endif
++
+ 	for (i = 0 ; i < num; i++) {
+ 		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);
+ 		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);
+@@ -633,10 +632,9 @@ void dpp1_set_degamma(
+ 		BREAK_TO_DEBUGGER();
+ 		break;
+ 	}
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
++
+ 	REG_SEQ_SUBMIT();
+ 	REG_SEQ_WAIT_DONE();
+-#endif
+ }
+ 
+ void dpp1_degamma_ram_select(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+index 8710f3ac2abf..30c025918568 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+@@ -457,18 +457,15 @@ static bool optc1_enable_crtc(struct timing_generator *optc)
+ 	REG_UPDATE(CONTROL,
+ 			VTG0_ENABLE, 1);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	REG_SEQ_START();
+-#endif
++
+ 	/* Enable CRTC */
+ 	REG_UPDATE_2(OTG_CONTROL,
+ 			OTG_DISABLE_POINT_CNTL, 3,
+ 			OTG_MASTER_EN, 1);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	REG_SEQ_SUBMIT();
+ 	REG_SEQ_WAIT_DONE();
+-#endif
+ 
+ 	return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+index 2417d933ef2b..f90031ed58a6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+@@ -345,10 +345,8 @@ static void mpc20_program_ogam_pwl(
+ 	uint32_t i;
+ 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	PERF_TRACE();
+ 	REG_SEQ_START();
+-#endif
+ 
+ 	for (i = 0 ; i < num; i++) {
+ 		REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg);
+@@ -468,12 +466,11 @@ void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)
+ 		ASSERT(!mpc_disabled);
+ 		ASSERT(!mpc_idle);
+ 	}
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
++
+ 	REG_SEQ_SUBMIT();
+ 	PERF_TRACE();
+ 	REG_SEQ_WAIT_DONE();
+ 	PERF_TRACE();
+-#endif
+ }
+ 
+ static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 30a246ebe842..5f731c8a6fe1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1699,9 +1699,7 @@ static bool construct(
+ 	dc->caps.post_blend_color_processing = true;
+ 	dc->caps.force_dp_tps4_for_cp2520 = true;
+ 	dc->caps.extended_aux_timeout_support = true;
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ 	dc->caps.dmcub_support = true;
+-#endif
+ 
+ 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
+ 		dc->debug = debug_defaults_drv;
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
+index 0a3891edfd94..968ff1fef486 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
+@@ -40,11 +40,9 @@
+ 
+ #undef DEPRECATED
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ struct dmub_srv;
+ struct dc_dmub_srv;
+ 
+-#endif
+ irq_handler_idx dm_register_interrupt(
+ 	struct dc_context *ctx,
+ 	struct dc_interrupt_params *int_params,
+@@ -144,14 +142,12 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
+ 		uint32_t addr, int n,
+ 		uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub);
+ void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv);
+ 
+ void reg_sequence_start_gather(const struct dc_context *ctx);
+ void reg_sequence_start_execute(const struct dc_context *ctx);
+ void reg_sequence_wait_done(const struct dc_context *ctx);
+-#endif
+ 
+ #define FD(reg_field)	reg_field ## __SHIFT, \
+ 						reg_field ## _MASK
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+index a9a9657c095a..47e307388581 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+@@ -485,8 +485,6 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
+ 		uint8_t shift1, uint32_t mask1, uint32_t field_value1,
+ 		...);
+ 
+-
+-#ifdef CONFIG_DRM_AMD_DC_DMUB
+ /* register offload macros
+  *
+  * instead of MMIO to register directly, in some cases we want
+@@ -505,6 +503,5 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
+ /* wait for the last REG_SEQ_SUBMIT to finish */
+ #define REG_SEQ_WAIT_DONE() \
+ 	reg_sequence_wait_done(CTX)
+-#endif
+ 
+ #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile
+index f3b844f474fd..e08dfeea24b0 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/Makefile
++++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile
+@@ -20,10 +20,8 @@
+ # OTHER DEALINGS IN THE SOFTWARE.
+ #
+ 
+-ifdef CONFIG_DRM_AMD_DC_DMUB
+ DMUB = dmub_srv.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o
+ 
+ AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))
+ 
+ AMD_DISPLAY_FILES += $(AMD_DAL_DMUB)
+-endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4334-drm-ttm-bug-fix-for-sproadic-hard-hang-during-closin.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4334-drm-ttm-bug-fix-for-sproadic-hard-hang-during-closin.patch
new file mode 100644
index 00000000..a89a6272
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4334-drm-ttm-bug-fix-for-sproadic-hard-hang-during-closin.patch
@@ -0,0 +1,35 @@
+From 5fd1009b6b0a57a3b40f0d4e45f0849be9016772 Mon Sep 17 00:00:00 2001
+From: Rahul Kumar <rahul.kumar1@amd.com>
+Date: Thu, 12 Dec 2019 17:14:08 +0530
+Subject: [PATCH 4334/4736] drm/ttm: bug fix for sproadic hard hang during
+ closing(cttl+c) video playback
+
+Added reservation object as shared resource before adding reservation
+object to fence.
+
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/ttm/ttm_execbuf_util.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/ttm/ttm_execbuf_util.c b/drivers/gpu/drm/ttm/ttm_execbuf_util.c
+index e73ae0d22897..41a8dcaa1163 100644
+--- a/drivers/gpu/drm/ttm/ttm_execbuf_util.c
++++ b/drivers/gpu/drm/ttm/ttm_execbuf_util.c
+@@ -202,7 +202,13 @@ void ttm_eu_fence_buffer_objects(struct ww_acquire_ctx *ticket,
+ 	list_for_each_entry(entry, list, head) {
+ 		bo = entry->bo;
+ 		if (entry->shared)
++		{
++			int r;
++			r = reservation_object_reserve_shared(bo->resv);
++			if (r)
++				return;
+ 			reservation_object_add_shared_fence(bo->resv, fence);
++		}
+ 		else
+ 			reservation_object_add_excl_fence(bo->resv, fence);
+ 		ttm_bo_add_to_lru(bo);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4335-drm-amdgpu-change-pstate-only-after-all-XGMI-device-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4335-drm-amdgpu-change-pstate-only-after-all-XGMI-device-.patch
new file mode 100644
index 00000000..57eebf50
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4335-drm-amdgpu-change-pstate-only-after-all-XGMI-device-.patch
@@ -0,0 +1,52 @@
+From 911f01258c9fe327b6f6afbf77c693ad5c143505 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 31 Oct 2019 14:10:27 +0800
+Subject: [PATCH 4335/4736] drm/amdgpu: change pstate only after all XGMI
+ device initialized
+
+Pstate settings should be performed after all device of the
+XGMI setup get initialized.
+
+Change-Id: I5c4b3f79fbd60a5ccfb4dc6f94d9e1db6faec694
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 15 ++++++++++++---
+ 1 file changed, 12 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 8e35ebdf4e10..beeae2573cb0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2082,9 +2082,6 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
+ 	if (r)
+ 		DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
+ 
+-	/* set to low pstate by default */
+-	amdgpu_xgmi_set_pstate(adev, 0);
+-
+ 	return 0;
+ }
+ 
+@@ -2196,6 +2193,18 @@ static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
+ 	r = amdgpu_ib_ring_tests(adev);
+ 	if (r)
+ 		DRM_ERROR("ib ring test failed (%d).\n", r);
++
++	/*
++	 * set to low pstate by default
++	 * This should be performed after all devices from
++	 * XGMI finish their initializations. Thus it's moved
++	 * to here.
++	 * The time delay is 2S. TODO: confirm whether that
++	 * is enough for all possible XGMI setups.
++	 */
++	r = amdgpu_xgmi_set_pstate(adev, 0);
++	if (r)
++		DRM_ERROR("pstate setting failed (%d).\n", r);
+ }
+ 
+ static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4336-drm-amd-powerplay-update-is_sw_smu_xgmi-check.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4336-drm-amd-powerplay-update-is_sw_smu_xgmi-check.patch
new file mode 100644
index 00000000..a29b2647
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4336-drm-amd-powerplay-update-is_sw_smu_xgmi-check.patch
@@ -0,0 +1,31 @@
+From 157b0af597dc993edad883b1aa397d73b27fbe81 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 31 Oct 2019 14:29:48 +0800
+Subject: [PATCH 4336/4736] drm/amd/powerplay: update is_sw_smu_xgmi check
+
+Add check for is_sw_smu routine and drop check
+for amdgpu_dpm which seems non-sense.
+
+Change-Id: I2b694a6255a76d35305fc64ca39625730e3463db
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index cda79f0eb822..facc19cae7e5 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -526,7 +526,7 @@ bool is_support_sw_smu(struct amdgpu_device *adev)
+ 
+ bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
+ {
+-	if (amdgpu_dpm != 1)
++	if (!is_support_sw_smu(adev))
+ 		return false;
+ 
+ 	if (adev->asic_type == CHIP_VEGA20)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4337-drm-amd-powerplay-support-xgmi-pstate-setting-on-pow.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4337-drm-amd-powerplay-support-xgmi-pstate-setting-on-pow.patch
new file mode 100644
index 00000000..e92c2cad
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4337-drm-amd-powerplay-support-xgmi-pstate-setting-on-pow.patch
@@ -0,0 +1,164 @@
+From caa363053b29f60ba1174395f0d73f08a10c224a Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 31 Oct 2019 09:41:19 +0800
+Subject: [PATCH 4337/4736] drm/amd/powerplay: support xgmi pstate setting on
+ powerplay routine V2
+
+Add xgmi pstate setting on powerplay routine.
+
+V2: split the change of is_support_sw_smu_xgmi into a separate patch
+
+Change-Id: If1a49aa14c16f133e43ac1298c6b14eaeb44d79d
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c       |  5 +++++
+ drivers/gpu/drm/amd/include/kgd_pp_interface.h |  4 ++++
+ drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 18 ++++++++++++++++++
+ .../gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 15 +++++++++++++++
+ drivers/gpu/drm/amd/powerplay/inc/hwmgr.h      |  1 +
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c      |  5 +----
+ 6 files changed, 44 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+index ba88acdf87ec..44a0ee91b42d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+@@ -285,6 +285,11 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
+ 
+ 	if (is_support_sw_smu_xgmi(adev))
+ 		ret = smu_set_xgmi_pstate(&adev->smu, pstate);
++	else if (adev->powerplay.pp_funcs &&
++		 adev->powerplay.pp_funcs->set_xgmi_pstate)
++		ret = adev->powerplay.pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle,
++								pstate);
++
+ 	if (ret)
+ 		dev_err(adev->dev,
+ 			"XGMI: Set pstate failure on device %llx, hive %llx, ret %d",
+diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+index 5902f80d1fce..a7f92d0b3a90 100644
+--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
++++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+@@ -220,6 +220,9 @@ enum pp_df_cstate {
+ 		((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
+ 		(support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
+ 
++#define XGMI_MODE_PSTATE_D3 0
++#define XGMI_MODE_PSTATE_D0 1
++
+ struct seq_file;
+ enum amd_pp_clock_type;
+ struct amd_pp_simple_clock_info;
+@@ -318,6 +321,7 @@ struct amd_pm_funcs {
+ 	int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
+ 	int (*asic_reset_mode_2)(void *handle);
+ 	int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
++	int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
+ };
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+index f4ff15378e61..031447675203 100644
+--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+@@ -1566,6 +1566,23 @@ static int pp_set_df_cstate(void *handle, enum pp_df_cstate state)
+ 	return 0;
+ }
+ 
++static int pp_set_xgmi_pstate(void *handle, uint32_t pstate)
++{
++	struct pp_hwmgr *hwmgr = handle;
++
++	if (!hwmgr)
++		return -EINVAL;
++
++	if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_xgmi_pstate)
++		return 0;
++
++	mutex_lock(&hwmgr->smu_lock);
++	hwmgr->hwmgr_func->set_xgmi_pstate(hwmgr, pstate);
++	mutex_unlock(&hwmgr->smu_lock);
++
++	return 0;
++}
++
+ static const struct amd_pm_funcs pp_dpm_funcs = {
+ 	.load_firmware = pp_dpm_load_fw,
+ 	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
+@@ -1625,4 +1642,5 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
+ 	.asic_reset_mode_2 = pp_asic_reset_mode_2,
+ 	.smu_i2c_bus_access = pp_smu_i2c_bus_access,
+ 	.set_df_cstate = pp_set_df_cstate,
++	.set_xgmi_pstate = pp_set_xgmi_pstate,
+ };
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+index 9295bd90b792..5bcf0d684151 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+@@ -4176,6 +4176,20 @@ static int vega20_set_df_cstate(struct pp_hwmgr *hwmgr,
+ 	return ret;
+ }
+ 
++static int vega20_set_xgmi_pstate(struct pp_hwmgr *hwmgr,
++				  uint32_t pstate)
++{
++	int ret;
++
++	ret = smum_send_msg_to_smc_with_parameter(hwmgr,
++						  PPSMC_MSG_SetXgmiMode,
++						  pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3);
++	if (ret)
++		pr_err("SetXgmiPstate failed!\n");
++
++	return ret;
++}
++
+ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
+ 	/* init/fini related */
+ 	.backend_init = vega20_hwmgr_backend_init,
+@@ -4245,6 +4259,7 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
+ 	.set_mp1_state = vega20_set_mp1_state,
+ 	.smu_i2c_bus_access = vega20_smu_i2c_bus_access,
+ 	.set_df_cstate = vega20_set_df_cstate,
++	.set_xgmi_pstate = vega20_set_xgmi_pstate,
+ };
+ 
+ int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+index bd8c922dfd3e..40403bc76f1b 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+@@ -356,6 +356,7 @@ struct pp_hwmgr_func {
+ 	int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
+ 	int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire);
+ 	int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state);
++	int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);
+ };
+ 
+ struct pp_table_func {
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 7e882999abad..5877857760be 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1463,16 +1463,13 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
+ 	return ret;
+ }
+ 
+-#define XGMI_STATE_D0 1
+-#define XGMI_STATE_D3 0
+-
+ int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
+ 				     uint32_t pstate)
+ {
+ 	int ret = 0;
+ 	ret = smu_send_smc_msg_with_param(smu,
+ 					  SMU_MSG_SetXgmiMode,
+-					  pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
++					  pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3);
+ 	return ret;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4338-drm-amdgpu-add-navi14-PCI-ID-for-new-work-station-SK.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4338-drm-amdgpu-add-navi14-PCI-ID-for-new-work-station-SK.patch
new file mode 100644
index 00000000..31c79b3a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4338-drm-amdgpu-add-navi14-PCI-ID-for-new-work-station-SK.patch
@@ -0,0 +1,30 @@
+From cd9db8495c22cdb3dea759ed1de45279d0d8b7d3 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Tue, 8 Oct 2019 17:57:00 +0800
+Subject: [PATCH 4338/4736] drm/amdgpu: add navi14 PCI ID for new work station
+ SKU
+
+Add the navi14 PCI device id.
+
+Change-Id: I05ca1343c38f635b7c20341d09e2baf7f28a4a4b
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 97d6103bc023..298f78947048 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1046,6 +1046,7 @@ static const struct pci_device_id pciidlist[] = {
+ 	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
+ 	{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
+ 	{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
++	{0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
+ 
+ 	/* Renoir */
+ 	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4339-drm-amdgpu-gpuvm-add-some-additional-comments-in-amd.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4339-drm-amdgpu-gpuvm-add-some-additional-comments-in-amd.patch
new file mode 100644
index 00000000..1fa8121e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4339-drm-amdgpu-gpuvm-add-some-additional-comments-in-amd.patch
@@ -0,0 +1,48 @@
+From 440816a0d5fc263273fe9fb85d862ea964f99222 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 30 Oct 2019 13:53:27 -0400
+Subject: [PATCH 4339/4736] drm/amdgpu/gpuvm: add some additional comments in
+ amdgpu_vm_update_ptes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+To better clarify what is happening in this function.
+
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index d0604167cd74..7c5d9891d89a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -1408,6 +1408,9 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
+ 		uint64_t incr, entry_end, pe_start;
+ 		struct amdgpu_bo *pt;
+ 
++		/* make sure that the page tables covering the address range are
++		 * actually allocated
++		 */
+ 		r = amdgpu_vm_alloc_pts(params->adev, params->vm, &cursor,
+ 					params->direct);
+ 		if (r)
+@@ -1481,7 +1484,12 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
+ 		} while (frag_start < entry_end);
+ 
+ 		if (amdgpu_vm_pt_descendant(adev, &cursor)) {
+-			/* Free all child entries */
++			/* Free all child entries.
++			 * Update the tables with the flags and addresses and free up subsequent
++			 * tables in the case of huge pages or freed up areas.
++			 * This is the maximum you can free, because all other page tables are not
++			 * completely covered by the range and so potentially still in use.
++			 */
+ 			while (cursor.pfn < frag_start) {
+ 				amdgpu_vm_free_pts(adev, params->vm, &cursor);
+ 				amdgpu_vm_pt_next(adev, &cursor);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4340-drm-amdgpu-Show-resolution-correctly-in-mode-validat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4340-drm-amdgpu-Show-resolution-correctly-in-mode-validat.patch
new file mode 100644
index 00000000..e576cc29
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4340-drm-amdgpu-Show-resolution-correctly-in-mode-validat.patch
@@ -0,0 +1,29 @@
+From 7aed231f572bee5c39f28d1002fd490bda296dbf Mon Sep 17 00:00:00 2001
+From: Neil Mayhew <neil@neil.mayhew.name>
+Date: Wed, 30 Oct 2019 12:58:37 -0600
+Subject: [PATCH 4340/4736] drm/amdgpu: Show resolution correctly in mode
+ validation debug output
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Neil Mayhew <neil@neil.mayhew.name>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 5ef3b7e842e4..687d3ea76d4b 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -4589,8 +4589,8 @@ enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connec
+ 		result = MODE_OK;
+ 	else
+ 		DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
+-			      mode->vdisplay,
+ 			      mode->hdisplay,
++			      mode->vdisplay,
+ 			      mode->clock,
+ 			      dc_result);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4341-drm-amd-powerplay-print-the-pptable-provider.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4341-drm-amd-powerplay-print-the-pptable-provider.patch
new file mode 100644
index 00000000..8ab6524d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4341-drm-amd-powerplay-print-the-pptable-provider.patch
@@ -0,0 +1,34 @@
+From 1c03af3ae1ca41e2b70a71aca1c9a0fc0be4eb09 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 30 Oct 2019 11:38:53 +0800
+Subject: [PATCH 4341/4736] drm/amd/powerplay: print the pptable provider
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 5877857760be..9ebc00a97096 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -368,6 +368,7 @@ int smu_v11_0_setup_pptable(struct smu_context *smu)
+ 	version_major = le16_to_cpu(hdr->header.header_version_major);
+ 	version_minor = le16_to_cpu(hdr->header.header_version_minor);
+ 	if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
++		pr_info("use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
+ 		switch (version_minor) {
+ 		case 0:
+ 			ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
+@@ -384,6 +385,7 @@ int smu_v11_0_setup_pptable(struct smu_context *smu)
+ 			return ret;
+ 
+ 	} else {
++		pr_info("use vbios provided pptable\n");
+ 		index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+ 						    powerplayinfo);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4342-drm-amdgpu-discovery-Need-to-free-discovery-memory.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4342-drm-amdgpu-discovery-Need-to-free-discovery-memory.patch
new file mode 100644
index 00000000..463690cf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4342-drm-amdgpu-discovery-Need-to-free-discovery-memory.patch
@@ -0,0 +1,41 @@
+From 9c80bfb3b3f3e6cc8a69b9abc5b6e245653ebe0d Mon Sep 17 00:00:00 2001
+From: Emily Deng <Emily.Deng@amd.com>
+Date: Mon, 4 Nov 2019 12:45:09 +0800
+Subject: [PATCH 4342/4736] drm/amdgpu/discovery: Need to free discovery memory
+
+When unloading driver, need to free discovery memory.
+
+Signed-off-by: Emily Deng <Emily.Deng@amd.com>
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 9a094e118d96..b5028af50cc2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -2216,9 +2216,6 @@ void amdgpu_ttm_late_init(struct amdgpu_device *adev)
+ 	void *stolen_vga_buf;
+ 	/* return the VGA stolen memory (if any) back to VRAM */
+ 	amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
+-
+-	/* return the IP Discovery TMR memory back to VRAM */
+-	amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
+ }
+ 
+ /**
+@@ -2231,7 +2228,10 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
+ 
+ 	amdgpu_ttm_debugfs_fini(adev);
+ 	amdgpu_ttm_training_reserve_vram_fini(adev);
++	/* return the IP Discovery TMR memory back to VRAM */
++	amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
+ 	amdgpu_ttm_fw_reserve_vram_fini(adev);
++
+ 	if (adev->mman.aper_base_kaddr)
+ 		iounmap(adev->mman.aper_base_kaddr);
+ 	adev->mman.aper_base_kaddr = NULL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4343-drm-sched-Fix-passing-zero-to-PTR_ERR-warning-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4343-drm-sched-Fix-passing-zero-to-PTR_ERR-warning-v2.patch
new file mode 100644
index 00000000..b2642b1a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4343-drm-sched-Fix-passing-zero-to-PTR_ERR-warning-v2.patch
@@ -0,0 +1,49 @@
+From 3bd1ff177e6034a99a519cb3a215576de34b049f Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Tue, 29 Oct 2019 11:03:05 -0400
+Subject: [PATCH 4343/4736] drm/sched: Fix passing zero to 'PTR_ERR' warning v2
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fix a static code checker warning.
+
+v2: Drop PTR_ERR_OR_ZERO.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Emily Deng <Emily.Deng@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/scheduler/sched_main.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c
+index cef586235eaf..007abab5dae6 100644
+--- a/drivers/gpu/drm/scheduler/sched_main.c
++++ b/drivers/gpu/drm/scheduler/sched_main.c
+@@ -498,8 +498,10 @@ void drm_sched_resubmit_jobs(struct drm_gpu_scheduler *sched)
+ 		fence = sched->ops->run_job(s_job);
+ 
+ 		if (IS_ERR_OR_NULL(fence)) {
++			if (IS_ERR(fence))
++				dma_fence_set_error(&s_fence->finished, PTR_ERR(fence));
++
+ 			s_job->s_fence->parent = NULL;
+-			dma_fence_set_error(&s_fence->finished, PTR_ERR(fence));
+ 		} else {
+ 			s_job->s_fence->parent = fence;
+ 		}
+@@ -741,8 +743,9 @@ static int drm_sched_main(void *param)
+ 					  r);
+ 			dma_fence_put(fence);
+ 		} else {
++			if (IS_ERR(fence))
++				dma_fence_set_error(&s_fence->finished, PTR_ERR(fence));
+ 
+-			dma_fence_set_error(&s_fence->finished, PTR_ERR(fence));
+ 			drm_sched_process_job(NULL, &sched_job->cb);
+ 		}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4344-Revert-drm-amd-display-setting-the-DIG_MODE-to-the-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4344-Revert-drm-amd-display-setting-the-DIG_MODE-to-the-c.patch
new file mode 100644
index 00000000..ebc20c34
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4344-Revert-drm-amd-display-setting-the-DIG_MODE-to-the-c.patch
@@ -0,0 +1,49 @@
+From 7ee3c33cd19d48803b9e88e5bcc787005c06bf41 Mon Sep 17 00:00:00 2001
+From: Zhan Liu <Zhan.Liu@amd.com>
+Date: Mon, 4 Nov 2019 15:46:56 -0400
+Subject: [PATCH 4344/4736] Revert "drm/amd/display: setting the DIG_MODE to
+ the correct value."
+
+This reverts commit 6966609de439ac6ddd4438a468f83ab0a2f36de0.
+
+Reason for revert: Root cause of this issue is found. The workaround is not needed anymore.
+
+Change-Id: I193ea994b8ce5c2828dfc09b36c009546443c7d5
+Signed-off-by: Zhan Liu <Zhan.Liu@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 18 ------------------
+ 1 file changed, 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index fad7f3b7bc31..8780020d4f6a 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -3025,24 +3025,6 @@ void core_link_enable_stream(
+ 					CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
+ 					COLOR_DEPTH_UNDEFINED);
+ 
+-		/* This second call is needed to reconfigure the DIG
+-		 * as a workaround for the incorrect value being applied
+-		 * from transmitter control.
+-		 */
+-		if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
+-			stream->link->link_enc->funcs->setup(
+-				stream->link->link_enc,
+-				pipe_ctx->stream->signal);
+-
+-		/* This second call is needed to reconfigure the DIG
+-		 * as a workaround for the incorrect value being applied
+-		 * from transmitter control.
+-		 */
+-		if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
+-			stream->link->link_enc->funcs->setup(
+-				stream->link->link_enc,
+-				pipe_ctx->stream->signal);
+-
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 		if (pipe_ctx->stream->timing.flags.DSC) {
+ 			if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4345-drm-amdgpu-disallow-direct-upload-save-restore-list-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4345-drm-amdgpu-disallow-direct-upload-save-restore-list-.patch
new file mode 100644
index 00000000..538b953e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4345-drm-amdgpu-disallow-direct-upload-save-restore-list-.patch
@@ -0,0 +1,41 @@
+From d20cea67111506f14662640c257bf93c30900acf Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 4 Nov 2019 16:20:06 +0800
+Subject: [PATCH 4345/4736] drm/amdgpu: disallow direct upload save restore
+ list from gfx driver
+
+Direct uploading save/restore list via mmio register writes breaks the security
+policy. Instead, the driver should pass s&r list to psp.
+
+For all the ASICs that use rlc v2_1 headers, the driver actually upload s&r list
+twice, in non-psp ucode front door loading phase and gfx pg initialization phase.
+The latter is not allowed.
+
+VG12 is the only exception where the driver still keeps legacy approach for S&R
+list uploading. In theory, this can be elimnated if we have valid srcntl ucode
+for VG12.
+
+Change-Id: I8cc8e0126f746aae43b9114e05bc111ee7b23531
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Candice Li <Candice.Li@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 005f4d0d2484..d521facadf59 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -2728,7 +2728,8 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
+ 	 * And it's needed by gfxoff feature.
+ 	 */
+ 	if (adev->gfx.rlc.is_rlc_v2_1) {
+-		gfx_v9_1_init_rlc_save_restore_list(adev);
++		if (adev->asic_type == CHIP_VEGA12)
++			gfx_v9_1_init_rlc_save_restore_list(adev);
+ 		gfx_v9_0_enable_save_restore_machine(adev);
+ 	}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4346-drm-amd-display-3.2.57.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4346-drm-amd-display-3.2.57.patch
new file mode 100644
index 00000000..072cd612
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4346-drm-amd-display-3.2.57.patch
@@ -0,0 +1,27 @@
+From 4cf028e5c339b1d23e391f098dc237241745d6e3 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Tue, 15 Oct 2019 08:35:14 -0400
+Subject: [PATCH 4346/4736] drm/amd/display: 3.2.57
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 30a2783881d9..d37818730960 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.56"
++#define DC_VER "3.2.57"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4347-drm-amd-display-Fix-assert-observed-when-performing-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4347-drm-amd-display-Fix-assert-observed-when-performing-.patch
new file mode 100644
index 00000000..180f8cfc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4347-drm-amd-display-Fix-assert-observed-when-performing-.patch
@@ -0,0 +1,65 @@
+From 740352c8b0207bd25979c556b1a720e21816f41e Mon Sep 17 00:00:00 2001
+From: David Galiffi <David.Galiffi@amd.com>
+Date: Sat, 12 Oct 2019 16:18:32 -0400
+Subject: [PATCH 4347/4736] drm/amd/display: Fix assert observed when
+ performing dummy p-state check
+
+[WHY]
+V.Active dram clock change workaround need a small modification for DMLv2
+to ensure that the dummy p-state check doesn't fail.
+
+Signed-off-by: David Galiffi <David.Galiffi@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c  | 4 ++++
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c         | 2 ++
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h         | 1 +
+ 3 files changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+index 3c70dd577292..d63ca4ccf7cf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+@@ -2611,9 +2611,13 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
+ 			mode_lib->vba.MinActiveDRAMClockChangeMargin
+ 					+ mode_lib->vba.DRAMClockChangeLatency;
+ 
++
+ 	if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
+ 		mode_lib->vba.DRAMClockChangeWatermark += 25;
+ 		mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
++	} else if (mode_lib->vba.DummyPStateCheck &&
++				mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
++		mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
+ 	} else {
+ 		if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {
+ 			mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vblank;
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+index 7f9a5621922f..81db8517a690 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+@@ -222,6 +222,8 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
+ 	mode_lib->vba.SRExitTime = soc->sr_exit_time_us;
+ 	mode_lib->vba.SREnterPlusExitTime = soc->sr_enter_plus_exit_time_us;
+ 	mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us;
++	mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us;
++
+ 	mode_lib->vba.Downspreading = soc->downspread_percent;
+ 	mode_lib->vba.DRAMChannelWidth = soc->dram_channel_width_bytes;   // new!
+ 	mode_lib->vba.FabricDatapathToDCNDataReturn = soc->fabric_datapath_to_dcn_data_return_bytes; // new!
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+index 1540ffbe3979..6c59a332093a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+@@ -155,6 +155,7 @@ struct vba_vars_st {
+ 	double UrgentLatencySupportUsChroma;
+ 	unsigned int DSCFormatFactor;
+ 
++	bool DummyPStateCheck;
+ 	bool PrefetchModeSupported;
+ 	enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only
+ 	double XFCRemoteSurfaceFlipDelay;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4348-drm-amd-display-Renoir-chroma-viewport-WA.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4348-drm-amd-display-Renoir-chroma-viewport-WA.patch
new file mode 100644
index 00000000..fd823e27
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4348-drm-amd-display-Renoir-chroma-viewport-WA.patch
@@ -0,0 +1,135 @@
+From 4c0ce6590a0b47c2976de8115fafc98bb2fcc375 Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Fri, 11 Oct 2019 15:34:20 -0400
+Subject: [PATCH 4348/4736] drm/amd/display: Renoir chroma viewport WA
+
+[Why]
+For unknown reason, immediate flip with host VM translation on NV12
+surface will underflow on last row of PTE.
+
+[How]
+Hack chroma viewport height to make fetch one more row of PTE.
+Note that this will cause hubp underflow on all video underlay
+cases, but the underflow is not user visible since it is in
+blank region.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h           |  2 +
+ .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 65 ++++++++++++++++++-
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c |  1 +
+ 3 files changed, 67 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index d37818730960..5d47871ff19c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -421,6 +421,8 @@ struct dc_debug_options {
+ 	bool cm_in_bypass;
+ #endif
+ 	int force_clock_mode;/*every mode change.*/
++
++	bool nv12_iflip_vm_wa;
+ };
+ 
+ struct dc_debug_data {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+index 2f5a5867e674..1ddd6ae22155 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+@@ -164,6 +164,69 @@ static void hubp21_setup(
+ 
+ }
+ 
++void hubp21_set_viewport(
++	struct hubp *hubp,
++	const struct rect *viewport,
++	const struct rect *viewport_c)
++{
++	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
++	int patched_viewport_height = 0;
++	struct dc_debug_options *debug = &hubp->ctx->dc->debug;
++
++	REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
++		  PRI_VIEWPORT_WIDTH, viewport->width,
++		  PRI_VIEWPORT_HEIGHT, viewport->height);
++
++	REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
++		  PRI_VIEWPORT_X_START, viewport->x,
++		  PRI_VIEWPORT_Y_START, viewport->y);
++
++	/*for stereo*/
++	REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
++		  SEC_VIEWPORT_WIDTH, viewport->width,
++		  SEC_VIEWPORT_HEIGHT, viewport->height);
++
++	REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
++		  SEC_VIEWPORT_X_START, viewport->x,
++		  SEC_VIEWPORT_Y_START, viewport->y);
++
++	/*
++	 *	Work around for underflow issue with NV12 + rIOMMU translation
++	 *	+ immediate flip. This will cause hubp underflow, but will not
++	 *	be user visible since underflow is in blank region
++	 */
++	patched_viewport_height = viewport_c->height;
++	if (viewport_c->height != 0 && debug->nv12_iflip_vm_wa) {
++		int pte_row_height = 0;
++		int pte_rows = 0;
++
++		REG_GET(DCHUBP_REQ_SIZE_CONFIG,
++			PTE_ROW_HEIGHT_LINEAR, &pte_row_height);
++
++		pte_row_height = 1 << (pte_row_height + 3);
++		pte_rows = (viewport_c->height + pte_row_height - 1) / pte_row_height;
++		patched_viewport_height = pte_rows * pte_row_height + 3;
++	}
++
++
++	/* DC supports NV12 only at the moment */
++	REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
++		  PRI_VIEWPORT_WIDTH_C, viewport_c->width,
++		  PRI_VIEWPORT_HEIGHT_C, patched_viewport_height);
++
++	REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
++		  PRI_VIEWPORT_X_START_C, viewport_c->x,
++		  PRI_VIEWPORT_Y_START_C, viewport_c->y);
++
++	REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,
++		  SEC_VIEWPORT_WIDTH_C, viewport_c->width,
++		  SEC_VIEWPORT_HEIGHT_C, patched_viewport_height);
++
++	REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,
++		  SEC_VIEWPORT_X_START_C, viewport_c->x,
++		  SEC_VIEWPORT_Y_START_C, viewport_c->y);
++}
++
+ void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,
+ 		struct vm_system_aperture_param *apt)
+ {
+@@ -211,7 +274,7 @@ static struct hubp_funcs dcn21_hubp_funcs = {
+ 	.hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings,
+ 	.set_blank = hubp1_set_blank,
+ 	.dcc_control = hubp1_dcc_control,
+-	.mem_program_viewport = min_set_viewport,
++	.mem_program_viewport = hubp21_set_viewport,
+ 	.set_cursor_attributes	= hubp2_cursor_set_attributes,
+ 	.set_cursor_position	= hubp1_cursor_set_position,
+ 	.hubp_clk_cntl = hubp1_clk_cntl,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 5f731c8a6fe1..e9db35c24073 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -831,6 +831,7 @@ static const struct dc_debug_options debug_defaults_drv = {
+ 		.scl_reset_length10 = true,
+ 		.sanity_checks = true,
+ 		.disable_48mhz_pwrdwn = false,
++		.nv12_iflip_vm_wa = true
+ };
+ 
+ static const struct dc_debug_options debug_defaults_diags = {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4349-drm-amd-display-Use-SIGNAL_TYPE_NONE-in-disable_outp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4349-drm-amd-display-Use-SIGNAL_TYPE_NONE-in-disable_outp.patch
new file mode 100644
index 00000000..6bb117e3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4349-drm-amd-display-Use-SIGNAL_TYPE_NONE-in-disable_outp.patch
@@ -0,0 +1,39 @@
+From cd43ff2a1e13dbf27001284939bbe66f75cd5c73 Mon Sep 17 00:00:00 2001
+From: Sung Lee <sung.lee@amd.com>
+Date: Wed, 16 Oct 2019 10:24:01 -0400
+Subject: [PATCH 4349/4736] drm/amd/display: Use SIGNAL_TYPE_NONE in
+ disable_output unless eDP
+
+[WHY]
+Currently made a change where disable_output is called using signal_type.
+Using actual signal_type when calilng disable_output in power_down_encoders
+would make DP to HDMI dongle not light up on boot. As it would have signal_type
+SIGNAL_TYPE_DISPLAY_PORT.
+
+[HOW]
+Set signal_type to SIGNAL_TYPE_NONE unless it is eDP.
+
+Signed-off-by: Sung Lee <sung.lee@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 0d171874ef4e..050634926263 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -1435,6 +1435,9 @@ static void power_down_encoders(struct dc *dc)
+ 			if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
+ 				dp_receiver_power_ctrl(dc->links[i], false);
+ 
++		if (signal != SIGNAL_TYPE_EDP)
++			signal = SIGNAL_TYPE_NONE;
++
+ 		dc->links[i]->link_enc->funcs->disable_output(
+ 				dc->links[i]->link_enc, signal);
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4350-drm-amd-display-Add-a-sanity-check-for-DSC-already-e.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4350-drm-amd-display-Add-a-sanity-check-for-DSC-already-e.patch
new file mode 100644
index 00000000..3c3c7009
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4350-drm-amd-display-Add-a-sanity-check-for-DSC-already-e.patch
@@ -0,0 +1,71 @@
+From 37d0bb62a1186bd5e2141900ad1431e93f2823d5 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Wed, 16 Oct 2019 14:34:15 -0400
+Subject: [PATCH 4350/4736] drm/amd/display: Add a sanity check for DSC already
+ enabled/disabled
+
+[why]
+If acquire/release DSC resource sequence is affected by a regression,
+it can happen that the already-in-use DSC HW block is being wrongly
+re-used for a different pipe. The reverse is also possible, i.e.
+already-disabled DSC HW block could be disabled from other context.
+
+[how]
+Read back the enable state of DSC HW and report an error if duplicate
+enable or disable was attempted.
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c  | 25 ++++++++++++++++---
+ 1 file changed, 22 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+index 63eb377ed9c0..dc9944427d2f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+@@ -222,9 +222,18 @@ static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const str
+ static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)
+ {
+ 	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
++	int dsc_clock_en;
++	int dsc_fw_config;
++	int enabled_opp_pipe;
+ 
+-	/* TODO Check if DSC alreay in use? */
+-	DC_LOG_DSC("enable DSC at opp pipe %d", opp_pipe);
++	DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
++
++	REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
++	REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
++	if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {
++		DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
++		ASSERT(0);
++	}
+ 
+ 	REG_UPDATE(DSC_TOP_CONTROL,
+ 		DSC_CLOCK_EN, 1);
+@@ -238,8 +247,18 @@ static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)
+ static void dsc2_disable(struct display_stream_compressor *dsc)
+ {
+ 	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
++	int dsc_clock_en;
++	int dsc_fw_config;
++	int enabled_opp_pipe;
+ 
+-	DC_LOG_DSC("disable DSC");
++	DC_LOG_DSC("disable DSC %d", dsc->inst);
++
++	REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
++	REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
++	if (!dsc_clock_en || !dsc_fw_config) {
++		DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already disabled!", dsc->inst, enabled_opp_pipe);
++		ASSERT(0);
++	}
+ 
+ 	REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
+ 		DSCRM_DSC_FORWARD_EN, 0);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4351-drm-amd-display-set-MSA-MISC1-bit-6-while-sending-co.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4351-drm-amd-display-set-MSA-MISC1-bit-6-while-sending-co.patch
new file mode 100644
index 00000000..ea3cb010
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4351-drm-amd-display-set-MSA-MISC1-bit-6-while-sending-co.patch
@@ -0,0 +1,322 @@
+From d8379d6b42cb6e6610e4dbbf643c1ea87666dd42 Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Wed, 16 Oct 2019 23:44:55 -0400
+Subject: [PATCH 4351/4736] drm/amd/display: set MSA MISC1 bit 6 while sending
+ colorimetry in VSC SDP
+
+[Why]
+It is confusing to sinks if we send VSC SDP only on some format. Today we
+signal colorimetry format using MSA while in formats like sRGB.
+But when we switch to BT2020 we set the bit to ignore MSA  colorimetry and
+instead use the colorimetry information in the VSC SDP.
+
+But if sink supports signaling of colorimetry via VSC SDP we should always
+set the MSA MISC1 bit 6, instead of doing so selectively.
+
+[How]
+If sink supports signaling of colorimetry via VSC SDP, and we are sending
+the colorimetry info via VSC SDP with packet revision 05h, then always
+set MSA MISC1 bit 6.
+
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  4 +-
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c |  1 +
+ drivers/gpu/drm/amd/display/dc/dc_stream.h    |  1 +
+ .../amd/display/dc/dce/dce_stream_encoder.c   |  1 +
+ .../display/dc/dcn10/dcn10_stream_encoder.c   |  6 +--
+ .../display/dc/dcn10/dcn10_stream_encoder.h   |  1 +
+ .../display/dc/dcn20/dcn20_stream_encoder.c   |  7 ++-
+ .../display/dc/dcn20/dcn20_stream_encoder.h   |  1 +
+ .../amd/display/dc/inc/hw/stream_encoder.h    |  1 +
+ .../dc/virtual/virtual_stream_encoder.c       |  1 +
+ .../amd/display/modules/inc/mod_info_packet.h |  4 +-
+ .../display/modules/info_packet/info_packet.c | 46 +++++++++++++++----
+ 12 files changed, 57 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 687d3ea76d4b..2f31cbd164d9 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -4081,7 +4081,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ 			struct dmcu *dmcu = core_dc->res_pool->dmcu;
+ 
+ 			stream->psr_version = dmcu->dmcu_version.psr_version;
+-			mod_build_vsc_infopacket(stream, &stream->vsc_infopacket);
++			mod_build_vsc_infopacket(stream,
++					&stream->vsc_infopacket,
++					&stream->use_vsc_sdp_for_colorimetry);
+ 		}
+ 	}
+ finish:
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 8780020d4f6a..a014d47f0f37 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2944,6 +2944,7 @@ void core_link_enable_stream(
+ 			pipe_ctx->stream_res.stream_enc,
+ 			&stream->timing,
+ 			stream->output_color_space,
++			stream->use_vsc_sdp_for_colorimetry,
+ 			stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
+ 
+ 	if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+index fdb6adc37857..f8c07d5a4054 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+@@ -164,6 +164,7 @@ struct dc_stream_state {
+ 
+ 	enum view_3d_format view_format;
+ 
++	bool use_vsc_sdp_for_colorimetry;
+ 	bool ignore_msa_timing_param;
+ 	bool converter_disable_audio;
+ 	uint8_t qs_bit;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+index 9205fb2e08bd..544a13f2d368 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+@@ -273,6 +273,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
+ 	struct stream_encoder *enc,
+ 	struct dc_crtc_timing *crtc_timing,
+ 	enum dc_color_space output_color_space,
++	bool use_vsc_sdp_for_colorimetry,
+ 	uint32_t enable_sdp_splitting)
+ {
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+index f10c1554ec01..5b4e5b6bfa41 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+@@ -246,6 +246,7 @@ void enc1_stream_encoder_dp_set_stream_attribute(
+ 	struct stream_encoder *enc,
+ 	struct dc_crtc_timing *crtc_timing,
+ 	enum dc_color_space output_color_space,
++	bool use_vsc_sdp_for_colorimetry,
+ 	uint32_t enable_sdp_splitting)
+ {
+ 	uint32_t h_active_start;
+@@ -311,10 +312,7 @@ void enc1_stream_encoder_dp_set_stream_attribute(
+ 	 * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
+ 	 * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
+ 	 */
+-	if ((hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) ||
+-			(output_color_space == COLOR_SPACE_2020_YCBCR) ||
+-			(output_color_space == COLOR_SPACE_2020_RGB_FULLRANGE) ||
+-			(output_color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE))
++	if (use_vsc_sdp_for_colorimetry)
+ 		misc1 = misc1 | 0x40;
+ 	else
+ 		misc1 = misc1 & ~0x40;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+index c9cbc21d121e..2f00f2389e40 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+@@ -526,6 +526,7 @@ void enc1_stream_encoder_dp_set_stream_attribute(
+ 	struct stream_encoder *enc,
+ 	struct dc_crtc_timing *crtc_timing,
+ 	enum dc_color_space output_color_space,
++	bool use_vsc_sdp_for_colorimetry,
+ 	uint32_t enable_sdp_splitting);
+ 
+ void enc1_stream_encoder_hdmi_set_stream_attribute(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+index 412d3032e4ef..d60d072848ba 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+@@ -531,11 +531,16 @@ void enc2_stream_encoder_dp_set_stream_attribute(
+ 	struct stream_encoder *enc,
+ 	struct dc_crtc_timing *crtc_timing,
+ 	enum dc_color_space output_color_space,
++	bool use_vsc_sdp_for_colorimetry,
+ 	uint32_t enable_sdp_splitting)
+ {
+ 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+ 
+-	enc1_stream_encoder_dp_set_stream_attribute(enc, crtc_timing, output_color_space, enable_sdp_splitting);
++	enc1_stream_encoder_dp_set_stream_attribute(enc,
++			crtc_timing,
++			output_color_space,
++			use_vsc_sdp_for_colorimetry,
++			enable_sdp_splitting);
+ 
+ 	REG_UPDATE(DP_SEC_FRAMING4,
+ 		DP_SST_SDP_SPLITTING, enable_sdp_splitting);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
+index 3f94a9f13c4a..d2a805bd4573 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
+@@ -98,6 +98,7 @@ void enc2_stream_encoder_dp_set_stream_attribute(
+ 	struct stream_encoder *enc,
+ 	struct dc_crtc_timing *crtc_timing,
+ 	enum dc_color_space output_color_space,
++	bool use_vsc_sdp_for_colorimetry,
+ 	uint32_t enable_sdp_splitting);
+ 
+ void enc2_stream_encoder_dp_unblank(
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+index 6305e388612a..c0b93d51ca8d 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+@@ -126,6 +126,7 @@ struct stream_encoder_funcs {
+ 		struct stream_encoder *enc,
+ 		struct dc_crtc_timing *crtc_timing,
+ 		enum dc_color_space output_color_space,
++		bool use_vsc_sdp_for_colorimetry,
+ 		uint32_t enable_sdp_splitting);
+ 
+ 	void (*hdmi_set_stream_attribute)(
+diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
+index 0c6d502da8a6..b37db73478eb 100644
+--- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
+@@ -30,6 +30,7 @@ static void virtual_stream_encoder_dp_set_stream_attribute(
+ 	struct stream_encoder *enc,
+ 	struct dc_crtc_timing *crtc_timing,
+ 	enum dc_color_space output_color_space,
++	bool use_vsc_sdp_for_colorimetry,
+ 	uint32_t enable_sdp_splitting) {}
+ 
+ static void virtual_stream_encoder_hdmi_set_stream_attribute(
+diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
+index ca8ce3c55337..42cbeffac640 100644
+--- a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
+@@ -26,6 +26,7 @@
+ #ifndef MOD_INFO_PACKET_H_
+ #define MOD_INFO_PACKET_H_
+ 
++#include "dm_services.h"
+ #include "mod_shared.h"
+ //Forward Declarations
+ struct dc_stream_state;
+@@ -33,7 +34,8 @@ struct dc_info_packet;
+ struct mod_vrr_params;
+ 
+ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
+-		struct dc_info_packet *info_packet);
++		struct dc_info_packet *info_packet,
++		bool *use_vsc_sdp_for_colorimetry);
+ 
+ void mod_build_hf_vsif_infopacket(const struct dc_stream_state *stream,
+ 		struct dc_info_packet *info_packet, int ALLMEnabled, int ALLMValue);
+diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
+index db6b08f6d093..6a8a056424b8 100644
+--- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
++++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
+@@ -30,6 +30,20 @@
+ #include "mod_freesync.h"
+ #include "dc.h"
+ 
++enum vsc_packet_revision {
++	vsc_packet_undefined = 0,
++	//01h = VSC SDP supports only 3D stereo.
++	vsc_packet_rev1 = 1,
++	//02h = 3D stereo + PSR.
++	vsc_packet_rev2 = 2,
++	//03h = 3D stereo + PSR2.
++	vsc_packet_rev3 = 3,
++	//04h = 3D stereo + PSR/PSR2 + Y-coordinate.
++	vsc_packet_rev4 = 4,
++	//05h = 3D stereo + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry Format
++	vsc_packet_rev5 = 5,
++};
++
+ #define HDMI_INFOFRAME_TYPE_VENDOR 0x81
+ #define HF_VSIF_VERSION 1
+ 
+@@ -116,35 +130,41 @@ enum ColorimetryYCCDP {
+ };
+ 
+ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
+-		struct dc_info_packet *info_packet)
++		struct dc_info_packet *info_packet,
++		bool *use_vsc_sdp_for_colorimetry)
+ {
+-	unsigned int vscPacketRevision = 0;
++	unsigned int vsc_packet_revision = vsc_packet_undefined;
+ 	unsigned int i;
+ 	unsigned int pixelEncoding = 0;
+ 	unsigned int colorimetryFormat = 0;
+ 	bool stereo3dSupport = false;
+ 
++	/* Initialize first, later if infopacket is valid determine if VSC SDP
++	 * should be used to signal colorimetry format and pixel encoding.
++	 */
++	*use_vsc_sdp_for_colorimetry = false;
++
+ 	if (stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE && stream->view_format != VIEW_3D_FORMAT_NONE) {
+-		vscPacketRevision = 1;
++		vsc_packet_revision = vsc_packet_rev1;
+ 		stereo3dSupport = true;
+ 	}
+ 
+ 	/*VSC packet set to 2 when DP revision >= 1.2*/
+ 	if (stream->psr_version != 0)
+-		vscPacketRevision = 2;
++		vsc_packet_revision = vsc_packet_rev2;
+ 
+ 	/* Update to revision 5 for extended colorimetry support for DPCD 1.4+ */
+ 	if (stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 &&
+ 			stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
+-		vscPacketRevision = 5;
++		vsc_packet_revision = vsc_packet_rev5;
+ 
+ 	/* VSC packet not needed based on the features
+ 	 * supported by this DP display
+ 	 */
+-	if (vscPacketRevision == 0)
++	if (vsc_packet_revision == vsc_packet_undefined)
+ 		return;
+ 
+-	if (vscPacketRevision == 0x2) {
++	if (vsc_packet_revision == vsc_packet_rev2) {
+ 		/* Secondary-data Packet ID = 0*/
+ 		info_packet->hb0 = 0x00;
+ 		/* 07h - Packet Type Value indicating Video
+@@ -166,7 +186,7 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
+ 		info_packet->valid = true;
+ 	}
+ 
+-	if (vscPacketRevision == 0x1) {
++	if (vsc_packet_revision == vsc_packet_rev1) {
+ 
+ 		info_packet->hb0 = 0x00;	// Secondary-data Packet ID = 0
+ 		info_packet->hb1 = 0x07;	// 07h = Packet Type Value indicating Video Stream Configuration packet
+@@ -237,7 +257,7 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
+ 	 *   the Pixel Encoding/Colorimetry Format and that a Sink device must ignore MISC1, bit 7, and
+ 	 *   MISC0, bits 7:1 (MISC1, bit 7. and MISC0, bits 7:1 become "don't care").)
+ 	 */
+-	if (vscPacketRevision == 0x5) {
++	if (vsc_packet_revision == vsc_packet_rev5) {
+ 		/* Secondary-data Packet ID = 0 */
+ 		info_packet->hb0 = 0x00;
+ 		/* 07h - Packet Type Value indicating Video Stream Configuration packet */
+@@ -249,6 +269,13 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
+ 
+ 		info_packet->valid = true;
+ 
++		/* If we are using VSC SDP revision 05h, use this to signal for
++		 * colorimetry format and pixel encoding. HW should later be
++		 * programmed to set MSA MISC1 bit 6 to indicate ignore
++		 * colorimetry format and pixel encoding in the MSA.
++		 */
++		*use_vsc_sdp_for_colorimetry = true;
++
+ 		/* Set VSC SDP fields for pixel encoding and colorimetry format from DP 1.3 specs
+ 		 * Data Bytes DB 18~16
+ 		 * Bits 3:0 (Colorimetry Format)        |  Bits 7:4 (Pixel Encoding)
+@@ -393,7 +420,6 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
+ 		 */
+ 		info_packet->sb[18] = 0;
+ 	}
+-
+ }
+ 
+ /**
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4352-drm-amd-display-Create-debug-option-to-disable-v.act.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4352-drm-amd-display-Create-debug-option-to-disable-v.act.patch
new file mode 100644
index 00000000..28390086
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4352-drm-amd-display-Create-debug-option-to-disable-v.act.patch
@@ -0,0 +1,126 @@
+From 1125f87a7e9aa35f7a84916c067faf57784eca38 Mon Sep 17 00:00:00 2001
+From: David Galiffi <David.Galiffi@amd.com>
+Date: Tue, 1 Oct 2019 18:29:56 -0400
+Subject: [PATCH 4352/4736] drm/amd/display: Create debug option to disable
+ v.active clock change policy.
+
+[WHY]
+It has been a useful option in debugging GFXOFF and P.State Change issues.
+May be required as for platform specific workaround.
+
+[HOW]
+Create option in enum dc_debug_options, "disable_vactive_clock_change".
+When it is set, dm_dram_clock_change_vactive, will translate into
+p_state_change_support: false.
+
+Signed-off-by: David Galiffi <David.Galiffi@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h                         | 1 +
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c       | 1 +
+ .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c  | 3 ++-
+ .../drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c    | 6 +++---
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h   | 1 +
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c       | 2 ++
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h       | 1 +
+ 7 files changed, 11 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 5d47871ff19c..cc45d77a3b0d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -423,6 +423,7 @@ struct dc_debug_options {
+ 	int force_clock_mode;/*every mode change.*/
+ 
+ 	bool nv12_iflip_vm_wa;
++	bool disable_dram_clock_change_vactive_support;
+ };
+ 
+ struct dc_debug_data {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index ef43faa09eb3..19a4838b1ac2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2848,6 +2848,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
+ 	bool full_pstate_supported = false;
+ 	bool dummy_pstate_supported = false;
+ 	double p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
++	context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support = dc->debug.disable_dram_clock_change_vactive_support;
+ 
+ 	if (fast_validate)
+ 		return dcn20_validate_bandwidth_internal(dc, context, true);
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+index 6c6c486b774a..77b7574c63cb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+@@ -2577,7 +2577,8 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
+ 			mode_lib->vba.MinActiveDRAMClockChangeMargin
+ 					+ mode_lib->vba.DRAMClockChangeLatency;
+ 
+-	if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
++	if (mode_lib->vba.DRAMClockChangeSupportsVActive &&
++			mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
+ 		mode_lib->vba.DRAMClockChangeWatermark += 25;
+ 		mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
+ 	} else {
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+index d63ca4ccf7cf..62dfd36d830a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+@@ -2611,12 +2611,12 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
+ 			mode_lib->vba.MinActiveDRAMClockChangeMargin
+ 					+ mode_lib->vba.DRAMClockChangeLatency;
+ 
+-
+-	if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
++	if (mode_lib->vba.DRAMClockChangeSupportsVActive &&
++		mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
+ 		mode_lib->vba.DRAMClockChangeWatermark += 25;
+ 		mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
+ 	} else if (mode_lib->vba.DummyPStateCheck &&
+-				mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
++			mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
+ 		mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
+ 	} else {
+ 		if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+index cfacd6027467..19356180cbb6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+@@ -112,6 +112,7 @@ struct _vcs_dpi_soc_bounding_box_st {
+ 	bool do_urgent_latency_adjustment;
+ 	double urgent_latency_adjustment_fabric_clock_component_us;
+ 	double urgent_latency_adjustment_fabric_clock_reference_mhz;
++	bool disable_dram_clock_change_vactive_support;
+ };
+ 
+ struct _vcs_dpi_ip_params_st {
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+index 81db8517a690..da5e9d2fd6b6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+@@ -223,6 +223,8 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
+ 	mode_lib->vba.SREnterPlusExitTime = soc->sr_enter_plus_exit_time_us;
+ 	mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us;
+ 	mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us;
++	mode_lib->vba.DRAMClockChangeSupportsVActive = !soc->disable_dram_clock_change_vactive_support ||
++			mode_lib->vba.DummyPStateCheck;
+ 
+ 	mode_lib->vba.Downspreading = soc->downspread_percent;
+ 	mode_lib->vba.DRAMChannelWidth = soc->dram_channel_width_bytes;   // new!
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+index 6c59a332093a..6d8b5c61de68 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+@@ -156,6 +156,7 @@ struct vba_vars_st {
+ 	unsigned int DSCFormatFactor;
+ 
+ 	bool DummyPStateCheck;
++	bool DRAMClockChangeSupportsVActive;
+ 	bool PrefetchModeSupported;
+ 	enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only
+ 	double XFCRemoteSurfaceFlipDelay;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4353-drm-amd-display-optimize-bandwidth-after-commit-stre.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4353-drm-amd-display-optimize-bandwidth-after-commit-stre.patch
new file mode 100644
index 00000000..9e03049e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4353-drm-amd-display-optimize-bandwidth-after-commit-stre.patch
@@ -0,0 +1,43 @@
+From a61b8b1bfca590518f760c50ff81a31421e080d3 Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Fri, 18 Oct 2019 18:24:59 -0400
+Subject: [PATCH 4353/4736] drm/amd/display: optimize bandwidth after commit
+ streams.
+
+[Why]
+System is unable to enter S0i3 due to DISPLAY_OFF_MASK not asserted
+in SMU.
+
+[How]
+Optimized bandwidth should be called paired and to resolve unplug
+display underflow issue, optimize bandwidth after commit streams is
+moved to next page flip, in case of S0i3, there is a change for no
+flip coming causing display count is 1 in SMU side.
+Add optimize bandwidth after commit stream.
+
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 82d8b4aff88f..0c7925c2faf2 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1239,6 +1239,10 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ 
+ 	dc_enable_stereo(dc, context, dc_streams, context->stream_count);
+ 
++	if (!dc->optimize_seamless_boot)
++			/* pplib is notified if disp_num changed */
++			dc->hwss.optimize_bandwidth(dc, context);
++
+ 	for (i = 0; i < context->stream_count; i++)
+                 context->streams[i]->mode_changed = false;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4354-drm-amd-powerplay-fix-deadlock-on-setting-power_dpm_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4354-drm-amd-powerplay-fix-deadlock-on-setting-power_dpm_.patch
new file mode 100644
index 00000000..7a99a798
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4354-drm-amd-powerplay-fix-deadlock-on-setting-power_dpm_.patch
@@ -0,0 +1,62 @@
+From 78141a8d63f703a2b0cfd29654c6a884f971fb92 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Wed, 6 Nov 2019 12:40:12 +0800
+Subject: [PATCH 4354/4736] drm/amd/powerplay: fix deadlock on setting
+ power_dpm_force_performance_level
+
+smu_enable_umd_pstate() will try to get the smu->mutex which was already
+hold by its parent API smu_force_performance_level() on the call path.
+Thus deadlock happens.
+
+Change-Id: Ic4d3c7d06eb47eab2ea42b98f399cd95ab320f0c
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 19 ++++++++++++++-----
+ 1 file changed, 14 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index facc19cae7e5..c21fe7ac5df8 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -383,14 +383,25 @@ bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
+ 	return true;
+ }
+ 
+-
++/**
++ * smu_dpm_set_power_gate - power gate/ungate the specific IP block
++ *
++ * @smu:        smu_context pointer
++ * @block_type: the IP block to power gate/ungate
++ * @gate:       to power gate if true, ungate otherwise
++ *
++ * This API uses no smu->mutex lock protection due to:
++ * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
++ *    This is guarded to be race condition free by the caller.
++ * 2. Or get called on user setting request of power_dpm_force_performance_level.
++ *    Under this case, the smu->mutex lock protection is already enforced on
++ *    the parent API smu_force_performance_level of the call path.
++ */
+ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
+ 			   bool gate)
+ {
+ 	int ret = 0;
+ 
+-	mutex_lock(&smu->mutex);
+-
+ 	switch (block_type) {
+ 	case AMD_IP_BLOCK_TYPE_UVD:
+ 		ret = smu_dpm_set_uvd_enable(smu, gate);
+@@ -408,8 +419,6 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
+ 		break;
+ 	}
+ 
+-	mutex_unlock(&smu->mutex);
+-
+ 	return ret;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4355-drm-amd-display-3.2.58.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4355-drm-amd-display-3.2.58.patch
new file mode 100644
index 00000000..37485b70
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4355-drm-amd-display-3.2.58.patch
@@ -0,0 +1,27 @@
+From e93daa22dd3f9d8d7a86d3e3854769b0e5c0749b Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Mon, 21 Oct 2019 08:16:22 -0400
+Subject: [PATCH 4355/4736] drm/amd/display: 3.2.58
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index cc45d77a3b0d..f12ad4b17781 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.57"
++#define DC_VER "3.2.58"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4356-drm-amd-display-Add-some-hardware-status-in-DTN-log-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4356-drm-amd-display-Add-some-hardware-status-in-DTN-log-.patch
new file mode 100644
index 00000000..e42c4852
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4356-drm-amd-display-Add-some-hardware-status-in-DTN-log-.patch
@@ -0,0 +1,221 @@
+From e2e1baab88fd4354ab464cfe6ed1c5097b8ce421 Mon Sep 17 00:00:00 2001
+From: "Leo (Hanghong) Ma" <hanghong.ma@amd.com>
+Date: Fri, 6 Sep 2019 09:49:19 -0400
+Subject: [PATCH 4356/4736] drm/amd/display: Add some hardware status in DTN
+ log debugfs
+
+[Why]
+For debug purpose, we need to check the following hardware status
+in DTN log debugfs:
+1.dpp & hubp clock enable;
+2.crtc blank enable;
+3.link phy status;
+
+[How]
+Add the upper information in the amdgpu_dm_dtn_log debugfs.
+
+For CRTC blanked status, since DCN2 and greater reports it on the OPP
+instead of OTG, we patch it in after calling optc1_read_otg_states.
+Ideally, this should be done in the DCN version specific function hooks.
+It has been left as a TODO item.
+
+Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
+Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Acked-by: Harry Wentland <Harry.Wentland@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |  3 ++
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h |  1 +
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 43 +++++++++++++------
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c  |  1 +
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |  1 +
+ .../amd/display/dc/dcn20/dcn20_link_encoder.c |  1 +
+ .../drm/amd/display/dc/inc/hw/link_encoder.h  |  1 +
+ 7 files changed, 37 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+index 14d1be6c66e6..5aeee938605a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+@@ -1014,6 +1014,9 @@ void hubp1_read_state_common(struct hubp *hubp)
+ 			HUBP_TTU_DISABLE, &s->ttu_disable,
+ 			HUBP_UNDERFLOW_STATUS, &s->underflow_status);
+ 
++	REG_GET(HUBP_CLK_CNTL,
++			HUBP_CLOCK_ENABLE, &s->clock_en);
++
+ 	REG_GET(DCN_GLOBAL_TTU_CNTL,
+ 			MIN_TTU_VBLANK, &s->min_ttu_vblank);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+index ae70d9c0aa1d..e65e76f018e4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+@@ -670,6 +670,7 @@ struct dcn_hubp_state {
+ 	uint32_t sw_mode;
+ 	uint32_t dcc_en;
+ 	uint32_t blank_en;
++	uint32_t clock_en;
+ 	uint32_t underflow_status;
+ 	uint32_t ttu_disable;
+ 	uint32_t min_ttu_vblank;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 6d84239af593..4b6213d3ecbf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -128,9 +128,8 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)
+ 	struct resource_pool *pool = dc->res_pool;
+ 	int i;
+ 
+-	DTN_INFO("HUBP:  format  addr_hi  width  height"
+-			"  rot  mir  sw_mode  dcc_en  blank_en  ttu_dis  underflow"
+-			"   min_ttu_vblank       qos_low_wm      qos_high_wm\n");
++	DTN_INFO(
++		"HUBP:  format  addr_hi  width  height  rot  mir  sw_mode  dcc_en  blank_en  clock_en  ttu_dis  underflow   min_ttu_vblank       qos_low_wm      qos_high_wm\n");
+ 	for (i = 0; i < pool->pipe_count; i++) {
+ 		struct hubp *hubp = pool->hubps[i];
+ 		struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
+@@ -138,8 +137,7 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)
+ 		hubp->funcs->hubp_read_state(hubp);
+ 
+ 		if (!s->blank_en) {
+-			DTN_INFO("[%2d]:  %5xh  %6xh  %5d  %6d  %2xh  %2xh  %6xh"
+-					"  %6d  %8d  %7d  %8xh",
++			DTN_INFO("[%2d]:  %5xh  %6xh  %5d  %6d  %2xh  %2xh  %6xh  %6d  %8d  %8d  %7d  %8xh",
+ 					hubp->inst,
+ 					s->pixel_format,
+ 					s->inuse_addr_hi,
+@@ -150,6 +148,7 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)
+ 					s->sw_mode,
+ 					s->dcc_en,
+ 					s->blank_en,
++					s->clock_en,
+ 					s->ttu_disable,
+ 					s->underflow_status);
+ 			DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
+@@ -307,21 +306,35 @@ void dcn10_log_hw_state(struct dc *dc,
+ 	}
+ 	DTN_INFO("\n");
+ 
+-	DTN_INFO("OTG:  v_bs  v_be  v_ss  v_se  vpol  vmax  vmin  vmax_sel  vmin_sel"
+-			"  h_bs  h_be  h_ss  h_se  hpol  htot  vtot  underflow\n");
++	DTN_INFO("OTG:  v_bs  v_be  v_ss  v_se  vpol  vmax  vmin  vmax_sel  vmin_sel  h_bs  h_be  h_ss  h_se  hpol  htot  vtot  underflow blank_en\n");
+ 
+ 	for (i = 0; i < pool->timing_generator_count; i++) {
+ 		struct timing_generator *tg = pool->timing_generators[i];
+ 		struct dcn_otg_state s = {0};
+-
++		/* Read shared OTG state registers for all DCNx */
+ 		optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
+ 
++#ifdef CONFIG_DRM_AMD_DC_DCN2_0
++		/*
++		 * For DCN2 and greater, a register on the OPP is used to
++		 * determine if the CRTC is blanked instead of the OTG. So use
++		 * dpg_is_blanked() if exists, otherwise fallback on otg.
++		 *
++		 * TODO: Implement DCN-specific read_otg_state hooks.
++		 */
++		if (pool->opps[i]->funcs->dpg_is_blanked)
++			s.blank_enabled = pool->opps[i]->funcs->dpg_is_blanked(pool->opps[i]);
++		else
++			s.blank_enabled = tg->funcs->is_blanked(tg);
++#else
++		s.blank_enabled = tg->funcs->is_blanked(tg);
++#endif
++
+ 		//only print if OTG master is enabled
+ 		if ((s.otg_enabled & 1) == 0)
+ 			continue;
+ 
+-		DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d"
+-				" %5d %5d %5d %5d  %9d\n",
++		DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d %5d %5d %5d %5d  %9d %8d\n",
+ 				tg->inst,
+ 				s.v_blank_start,
+ 				s.v_blank_end,
+@@ -339,7 +352,8 @@ void dcn10_log_hw_state(struct dc *dc,
+ 				s.h_sync_a_pol,
+ 				s.h_total,
+ 				s.v_total,
+-				s.underflow_occurred_status);
++				s.underflow_occurred_status,
++				s.blank_enabled);
+ 
+ 		// Clear underflow for debug purposes
+ 		// We want to keep underflow sticky bit on for the longevity tests outside of test environment.
+@@ -386,7 +400,7 @@ void dcn10_log_hw_state(struct dc *dc,
+ 	}
+ 	DTN_INFO("\n");
+ 
+-	DTN_INFO("L_ENC: DPHY_FEC_EN  DPHY_FEC_READY_SHADOW  DPHY_FEC_ACTIVE_STATUS\n");
++	DTN_INFO("L_ENC: DPHY_FEC_EN  DPHY_FEC_READY_SHADOW  DPHY_FEC_ACTIVE_STATUS  DP_LINK_TRAINING_COMPLETE\n");
+ 	for (i = 0; i < dc->link_count; i++) {
+ 		struct link_encoder *lenc = dc->links[i]->link_enc;
+ 
+@@ -394,11 +408,12 @@ void dcn10_log_hw_state(struct dc *dc,
+ 
+ 		if (lenc->funcs->read_state) {
+ 			lenc->funcs->read_state(lenc, &s);
+-			DTN_INFO("[%-3d]: %-12d %-22d %-22d\n",
++			DTN_INFO("[%-3d]: %-12d %-22d %-22d %-25d\n",
+ 				i,
+ 				s.dphy_fec_en,
+ 				s.dphy_fec_ready_shadow,
+-				s.dphy_fec_active_status);
++				s.dphy_fec_active_status,
++				s.dp_link_training_complete);
+ 			DTN_INFO("\n");
+ 		}
+ 	}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+index 5be042acf9fa..8249b4429186 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+@@ -404,6 +404,7 @@ static const struct opp_funcs dcn10_opp_funcs = {
+ 		.opp_pipe_clock_control = opp1_pipe_clock_control,
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 		.opp_set_disp_pattern_generator = NULL,
++		.dpg_is_blanked = NULL,
+ #endif
+ 		.opp_destroy = opp1_destroy
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+index c8d795b335ba..4476bc8cdb4d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+@@ -542,6 +542,7 @@ struct dcn_otg_state {
+ 	uint32_t h_total;
+ 	uint32_t underflow_occurred_status;
+ 	uint32_t otg_enabled;
++	uint32_t blank_enabled;
+ };
+ 
+ void optc1_read_otg_state(struct optc *optc1,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
+index e476f27aa3a9..0e0306d84cd8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
+@@ -203,6 +203,7 @@ void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s)
+ 	REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en);
+ 	REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow);
+ 	REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status);
++	REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete);
+ }
+ #endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+index b21909216fb6..af57751ed8a1 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+@@ -124,6 +124,7 @@ struct link_enc_state {
+ 		uint32_t dphy_fec_en;
+ 		uint32_t dphy_fec_ready_shadow;
+ 		uint32_t dphy_fec_active_status;
++		uint32_t dp_link_training_complete;
+ 
+ };
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4357-drm-amd-display-add-oem-i2c-implemenation-in-dc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4357-drm-amd-display-add-oem-i2c-implemenation-in-dc.patch
new file mode 100644
index 00000000..0c38cf27
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4357-drm-amd-display-add-oem-i2c-implemenation-in-dc.patch
@@ -0,0 +1,413 @@
+From 58809698c7d678019f04e162634cf3750c3cb60b Mon Sep 17 00:00:00 2001
+From: Jun Lei <Jun.Lei@amd.com>
+Date: Fri, 2 Aug 2019 17:22:57 -0400
+Subject: [PATCH 4357/4736] drm/amd/display: add oem i2c implemenation in dc
+
+[why]
+Need it for some OEM I2C devices in Nv10
+
+[how]
+Link up code to parse OEM table and expose DC interface
+to access the pins
+
+Signed-off-by: Jun Lei <Jun.Lei@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ .../drm/amd/display/dc/bios/bios_parser2.c    | 63 ++++++++++++-------
+ drivers/gpu/drm/amd/display/dc/core/dc.c      | 11 ++++
+ .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |  5 +-
+ drivers/gpu/drm/amd/display/dc/dc_link.h      |  4 ++
+ drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c  | 19 +++---
+ .../gpu/drm/amd/display/dc/dce/dce_i2c_sw.c   | 43 -------------
+ .../gpu/drm/amd/display/dc/dce/dce_i2c_sw.h   |  6 +-
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 15 +++++
+ .../display/dc/gpio/dcn20/hw_factory_dcn20.c  | 12 ++++
+ .../gpu/drm/amd/display/dc/inc/core_types.h   |  2 +
+ .../display/include/grph_object_ctrl_defs.h   |  3 +-
+ 11 files changed, 100 insertions(+), 83 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index b4bbfb7bde12..3e2f21af2be7 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -292,11 +292,21 @@ static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
+ 	struct atom_display_object_path_v2 *object;
+ 	struct atom_common_record_header *header;
+ 	struct atom_i2c_record *record;
++	struct atom_i2c_record dummy_record = {0};
+ 	struct bios_parser *bp = BP_FROM_DCB(dcb);
+ 
+ 	if (!info)
+ 		return BP_RESULT_BADINPUT;
+ 
++	if (id.type == OBJECT_TYPE_GENERIC) {
++		dummy_record.i2c_id = id.id;
++
++		if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK)
++			return BP_RESULT_OK;
++		else
++			return BP_RESULT_NORECORD;
++	}
++
+ 	object = get_bios_object(bp, id);
+ 
+ 	if (!object)
+@@ -339,6 +349,7 @@ static enum bp_result get_gpio_i2c_info(
+ 	struct atom_gpio_pin_lut_v2_1 *header;
+ 	uint32_t count = 0;
+ 	unsigned int table_index = 0;
++	bool find_valid = false;
+ 
+ 	if (!info)
+ 		return BP_RESULT_BADINPUT;
+@@ -366,33 +377,28 @@ static enum bp_result get_gpio_i2c_info(
+ 			- sizeof(struct atom_common_table_header))
+ 				/ sizeof(struct atom_gpio_pin_assignment);
+ 
+-	table_index = record->i2c_id  & I2C_HW_LANE_MUX;
+-
+-	if (count < table_index) {
+-		bool find_valid = false;
+-
+-		for (table_index = 0; table_index < count; table_index++) {
+-			if (((record->i2c_id & I2C_HW_CAP) == (
+-			header->gpio_pin[table_index].gpio_id &
+-							I2C_HW_CAP)) &&
+-			((record->i2c_id & I2C_HW_ENGINE_ID_MASK)  ==
+-			(header->gpio_pin[table_index].gpio_id &
+-						I2C_HW_ENGINE_ID_MASK)) &&
+-			((record->i2c_id & I2C_HW_LANE_MUX) ==
+-			(header->gpio_pin[table_index].gpio_id &
+-							I2C_HW_LANE_MUX))) {
+-				/* still valid */
+-				find_valid = true;
+-				break;
+-			}
++	for (table_index = 0; table_index < count; table_index++) {
++		if (((record->i2c_id & I2C_HW_CAP) == (
++		header->gpio_pin[table_index].gpio_id &
++						I2C_HW_CAP)) &&
++		((record->i2c_id & I2C_HW_ENGINE_ID_MASK)  ==
++		(header->gpio_pin[table_index].gpio_id &
++					I2C_HW_ENGINE_ID_MASK)) &&
++		((record->i2c_id & I2C_HW_LANE_MUX) ==
++		(header->gpio_pin[table_index].gpio_id &
++						I2C_HW_LANE_MUX))) {
++			/* still valid */
++			find_valid = true;
++			break;
+ 		}
+-		/* If we don't find the entry that we are looking for then
+-		 *  we will return BP_Result_BadBiosTable.
+-		 */
+-		if (find_valid == false)
+-			return BP_RESULT_BADBIOSTABLE;
+ 	}
+ 
++	/* If we don't find the entry that we are looking for then
++	 *  we will return BP_Result_BadBiosTable.
++	 */
++	if (find_valid == false)
++		return BP_RESULT_BADBIOSTABLE;
++
+ 	/* get the GPIO_I2C_INFO */
+ 	info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;
+ 	info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX;
+@@ -1203,6 +1209,8 @@ static enum bp_result get_firmware_info_v3_1(
+ 				bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
+ 	}
+ 
++	info->oem_i2c_present = false;
++
+ 	return BP_RESULT_OK;
+ }
+ 
+@@ -1281,6 +1289,13 @@ static enum bp_result get_firmware_info_v3_2(
+ 					bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
+ 	}
+ 
++	if (firmware_info->board_i2c_feature_id == 0x2) {
++		info->oem_i2c_present = true;
++		info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
++	} else {
++		info->oem_i2c_present = false;
++	}
++
+ 	return BP_RESULT_OK;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 0c7925c2faf2..a652ebd77f7a 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -2495,6 +2495,17 @@ bool dc_submit_i2c(
+ 		cmd);
+ }
+ 
++bool dc_submit_i2c_oem(
++		struct dc *dc,
++		struct i2c_command *cmd)
++{
++	struct ddc_service *ddc = dc->res_pool->oem_device;
++	return dce_i2c_submit_command(
++		dc->res_pool,
++		ddc->ddc_pin,
++		cmd);
++}
++
+ static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
+ {
+ 	if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+index d98640f49874..747cd0fbe571 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+@@ -204,7 +204,10 @@ static void construct(
+ 		ddc_service->ddc_pin = NULL;
+ 	} else {
+ 		hw_info.ddc_channel = i2c_info.i2c_line;
+-		hw_info.hw_supported = i2c_info.i2c_hw_assist;
++		if (ddc_service->link != NULL)
++			hw_info.hw_supported = i2c_info.i2c_hw_assist;
++		else
++			hw_info.hw_supported = false;
+ 
+ 		ddc_service->ddc_pin = dal_gpio_create_ddc(
+ 			gpio_service,
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
+index f24fd19ed93d..9270e43cd5bb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
+@@ -305,6 +305,10 @@ bool dc_submit_i2c(
+ 		uint32_t link_index,
+ 		struct i2c_command *cmd);
+ 
++bool dc_submit_i2c_oem(
++		struct dc *dc,
++		struct i2c_command *cmd);
++
+ uint32_t dc_bandwidth_in_kbps_from_timing(
+ 	const struct dc_crtc_timing *timing);
+ #endif /* DC_LINK_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c
+index 35a75398fcb4..dd41736bb5c4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c
+@@ -31,7 +31,7 @@ bool dce_i2c_submit_command(
+ 	struct i2c_command *cmd)
+ {
+ 	struct dce_i2c_hw *dce_i2c_hw;
+-	struct dce_i2c_sw *dce_i2c_sw;
++	struct dce_i2c_sw dce_i2c_sw = {0};
+ 
+ 	if (!ddc) {
+ 		BREAK_TO_DEBUGGER();
+@@ -43,18 +43,15 @@ bool dce_i2c_submit_command(
+ 		return false;
+ 	}
+ 
+-	/* The software engine is only available on dce8 */
+-	dce_i2c_sw = dce_i2c_acquire_i2c_sw_engine(pool, ddc);
+-
+-	if (!dce_i2c_sw) {
+-		dce_i2c_hw = acquire_i2c_hw_engine(pool, ddc);
+-
+-		if (!dce_i2c_hw)
+-			return false;
++	dce_i2c_hw = acquire_i2c_hw_engine(pool, ddc);
+ 
++	if (dce_i2c_hw)
+ 		return dce_i2c_submit_command_hw(pool, ddc, cmd, dce_i2c_hw);
+-	}
+ 
+-	return dce_i2c_submit_command_sw(pool, ddc, cmd, dce_i2c_sw);
++	dce_i2c_sw.ctx = ddc->ctx;
++	if (dce_i2c_engine_acquire_sw(&dce_i2c_sw, ddc)) {
++		return dce_i2c_submit_command_sw(pool, ddc, cmd, &dce_i2c_sw);
++	}
+ 
++	return false;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c
+index f0266694cb56..f48dbeb75e80 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c
+@@ -70,31 +70,6 @@ static void release_engine_dce_sw(
+ 	dce_i2c_sw->ddc = NULL;
+ }
+ 
+-static bool get_hw_supported_ddc_line(
+-	struct ddc *ddc,
+-	enum gpio_ddc_line *line)
+-{
+-	enum gpio_ddc_line line_found;
+-
+-	*line = GPIO_DDC_LINE_UNKNOWN;
+-
+-	if (!ddc) {
+-		BREAK_TO_DEBUGGER();
+-		return false;
+-	}
+-
+-	if (!ddc->hw_info.hw_supported)
+-		return false;
+-
+-	line_found = dal_ddc_get_line(ddc);
+-
+-	if (line_found >= GPIO_DDC_LINE_COUNT)
+-		return false;
+-
+-	*line = line_found;
+-
+-	return true;
+-}
+ static bool wait_for_scl_high_sw(
+ 	struct dc_context *ctx,
+ 	struct ddc *ddc,
+@@ -521,21 +496,3 @@ bool dce_i2c_submit_command_sw(
+ 
+ 	return result;
+ }
+-struct dce_i2c_sw *dce_i2c_acquire_i2c_sw_engine(
+-	struct resource_pool *pool,
+-	struct ddc *ddc)
+-{
+-	enum gpio_ddc_line line;
+-	struct dce_i2c_sw *engine = NULL;
+-
+-	if (get_hw_supported_ddc_line(ddc, &line))
+-		engine = pool->sw_i2cs[line];
+-
+-	if (!engine)
+-		return NULL;
+-
+-	if (!dce_i2c_engine_acquire_sw(engine, ddc))
+-		return NULL;
+-
+-	return engine;
+-}
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.h b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.h
+index 5bbcdd455614..019fc47bb767 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.h
+@@ -49,9 +49,9 @@ bool dce_i2c_submit_command_sw(
+ 	struct i2c_command *cmd,
+ 	struct dce_i2c_sw *dce_i2c_sw);
+ 
+-struct dce_i2c_sw *dce_i2c_acquire_i2c_sw_engine(
+-	struct resource_pool *pool,
+-	struct ddc *ddc);
++bool dce_i2c_engine_acquire_sw(
++	struct dce_i2c_sw *dce_i2c_sw,
++	struct ddc *ddc_handle);
+ 
+ #endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 19a4838b1ac2..454d30bbfd20 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -57,6 +57,7 @@
+ #include "dml/display_mode_vba.h"
+ #include "dcn20_dccg.h"
+ #include "dcn20_vmid.h"
++#include "dc_link_ddc.h"
+ 
+ #include "navi10_ip_offset.h"
+ 
+@@ -1344,6 +1345,8 @@ static void destruct(struct dcn20_resource_pool *pool)
+ 	if (pool->base.pp_smu != NULL)
+ 		dcn20_pp_smu_destroy(&pool->base.pp_smu);
+ 
++	if (pool->base.oem_device != NULL)
++		dal_ddc_service_destroy(&pool->base.oem_device);
+ }
+ 
+ struct hubp *dcn20_hubp_create(
+@@ -3389,6 +3392,7 @@ static bool construct(
+ 	int i;
+ 	struct dc_context *ctx = dc->ctx;
+ 	struct irq_service_init_data init_data;
++	struct ddc_service_init_data ddc_init_data;
+ 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
+ 			get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
+ 	struct _vcs_dpi_ip_params_st *loaded_ip =
+@@ -3684,6 +3688,17 @@ static bool construct(
+ 
+ 	dc->cap_funcs = cap_funcs;
+ 
++	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
++		ddc_init_data.ctx = dc->ctx;
++		ddc_init_data.link = NULL;
++		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
++		ddc_init_data.id.enum_id = 0;
++		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
++		pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
++	} else {
++		pool->base.oem_device = NULL;
++	}
++
+ 	return true;
+ 
+ create_fail:
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
+index 43a440385b43..2664cb22dfe7 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
+@@ -110,6 +110,12 @@ static const struct ddc_registers ddc_data_regs_dcn[] = {
+ 	ddc_data_regs_dcn2(4),
+ 	ddc_data_regs_dcn2(5),
+ 	ddc_data_regs_dcn2(6),
++	{
++			DDC_GPIO_VGA_REG_LIST(DATA),
++			.ddc_setup = 0,
++			.phy_aux_cntl = 0,
++			.dc_gpio_aux_ctrl_5 = 0
++	}
+ };
+ 
+ static const struct ddc_registers ddc_clk_regs_dcn[] = {
+@@ -119,6 +125,12 @@ static const struct ddc_registers ddc_clk_regs_dcn[] = {
+ 	ddc_clk_regs_dcn2(4),
+ 	ddc_clk_regs_dcn2(5),
+ 	ddc_clk_regs_dcn2(6),
++	{
++			DDC_GPIO_VGA_REG_LIST(CLK),
++			.ddc_setup = 0,
++			.phy_aux_cntl = 0,
++			.dc_gpio_aux_ctrl_5 = 0
++	}
+ };
+ 
+ static const struct ddc_sh_mask ddc_shift[] = {
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index a831079607cd..fc9decc0a8fc 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -229,6 +229,8 @@ struct resource_pool {
+ 
+ 	const struct resource_funcs *funcs;
+ 	const struct resource_caps *res_cap;
++
++	struct ddc_service *oem_device;
+ };
+ 
+ struct dcn_fe_bandwidth {
+diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
+index f312834fef50..d51de94e4bc3 100644
+--- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
++++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
+@@ -178,7 +178,8 @@ struct dc_firmware_info {
+ 	uint32_t default_engine_clk; /* in KHz */
+ 	uint32_t dp_phy_ref_clk; /* in KHz - DCE12 only */
+ 	uint32_t i2c_engine_ref_clk; /* in KHz - DCE12 only */
+-
++	bool oem_i2c_present;
++	uint8_t oem_i2c_obj_id;
+ 
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4358-drm-amd-display-Unify-all-scaling-when-Integer-Scali.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4358-drm-amd-display-Unify-all-scaling-when-Integer-Scali.patch
new file mode 100644
index 00000000..6444cf87
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4358-drm-amd-display-Unify-all-scaling-when-Integer-Scali.patch
@@ -0,0 +1,109 @@
+From 9e82c03526a0875547dde5bfbcc0a68132a14b84 Mon Sep 17 00:00:00 2001
+From: Reza Amini <Reza.Amini@amd.com>
+Date: Thu, 17 Oct 2019 16:40:02 -0400
+Subject: [PATCH 4358/4736] drm/amd/display: Unify all scaling when Integer
+ Scaling enabled
+
+[why]
+We want to guarantee integer ratio scaling for all scaling modes.
+
+[how]
+Treat centered, fullscreen, preserve aspect ratio the same: scale
+the view as many times as possible, and fill in the rest with a black
+border.
+
+Signed-off-by: Reza Amini <Reza.Amini@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c      |  8 +++++--
+ .../gpu/drm/amd/display/dc/core/dc_resource.c | 21 ++++---------------
+ drivers/gpu/drm/amd/display/dc/dc_stream.h    |  1 +
+ 3 files changed, 11 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index a652ebd77f7a..a0ad1796af08 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1545,7 +1545,10 @@ static enum surface_update_type get_scaling_info_update_type(
+ 	if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
+ 			|| u->scaling_info->clip_rect.height != u->surface->clip_rect.height
+ 			|| u->scaling_info->dst_rect.width != u->surface->dst_rect.width
+-			|| u->scaling_info->dst_rect.height != u->surface->dst_rect.height) {
++			|| u->scaling_info->dst_rect.height != u->surface->dst_rect.height
++			|| u->scaling_info->scaling_quality.integer_scaling !=
++				u->surface->scaling_quality.integer_scaling
++			) {
+ 		update_flags->bits.scaling_change = 1;
+ 
+ 		if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
+@@ -1666,7 +1669,8 @@ static enum surface_update_type check_update_surfaces_for_stream(
+ 		union stream_update_flags *su_flags = &stream_update->stream->update_flags;
+ 
+ 		if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
+-				(stream_update->dst.height != 0 && stream_update->dst.width != 0))
++			(stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
++			stream_update->integer_scaling_update)
+ 			su_flags->bits.scaling = 1;
+ 
+ 		if (stream_update->out_transfer_func)
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 42c44c05759f..2acfaa9a24cd 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -948,25 +948,14 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
+ 	data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
+ 
+ }
+-static bool are_rects_integer_multiples(struct rect src, struct rect dest)
+-{
+-	if (dest.width  >= src.width  && dest.width  % src.width  == 0 &&
+-		dest.height >= src.height && dest.height % src.height == 0)
+-		return true;
+-
+-	return false;
+-}
+ 
+ static void calculate_integer_scaling(struct pipe_ctx *pipe_ctx)
+ {
+-	if (!pipe_ctx->plane_state->scaling_quality.integer_scaling)
+-		return;
++	unsigned int integer_multiple = 1;
+ 
+-	//for Centered Mode
+-	if (pipe_ctx->stream->dst.width  == pipe_ctx->stream->src.width &&
+-		pipe_ctx->stream->dst.height == pipe_ctx->stream->src.height) {
++	if (pipe_ctx->plane_state->scaling_quality.integer_scaling) {
+ 		// calculate maximum # of replication of src onto addressable
+-		unsigned int integer_multiple = min(
++		integer_multiple = min(
+ 				pipe_ctx->stream->timing.h_addressable / pipe_ctx->stream->src.width,
+ 				pipe_ctx->stream->timing.v_addressable  / pipe_ctx->stream->src.height);
+ 
+@@ -977,10 +966,8 @@ static void calculate_integer_scaling(struct pipe_ctx *pipe_ctx)
+ 		//center dst onto addressable
+ 		pipe_ctx->stream->dst.x = (pipe_ctx->stream->timing.h_addressable - pipe_ctx->stream->dst.width)/2;
+ 		pipe_ctx->stream->dst.y = (pipe_ctx->stream->timing.v_addressable - pipe_ctx->stream->dst.height)/2;
+-	}
+ 
+-	//disable taps if src & dst are integer ratio
+-	if (are_rects_integer_multiples(pipe_ctx->stream->src, pipe_ctx->stream->dst)) {
++		//We are guaranteed that we are scaling in integer ratio
+ 		pipe_ctx->plane_state->scaling_quality.v_taps = 1;
+ 		pipe_ctx->plane_state->scaling_quality.h_taps = 1;
+ 		pipe_ctx->plane_state->scaling_quality.v_taps_c = 1;
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+index f8c07d5a4054..70274fc43a72 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+@@ -252,6 +252,7 @@ struct dc_stream_update {
+ 	struct dc_info_packet *vsp_infopacket;
+ 
+ 	bool *dpms_off;
++	bool integer_scaling_update;
+ 
+ 	struct colorspace_transform *gamut_remap;
+ 	enum dc_color_space *output_color_space;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4359-drm-amd-powerplay-update-Arcturus-driver-smu-interfa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4359-drm-amd-powerplay-update-Arcturus-driver-smu-interfa.patch
new file mode 100644
index 00000000..91a432ec
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4359-drm-amd-powerplay-update-Arcturus-driver-smu-interfa.patch
@@ -0,0 +1,46 @@
+From bf1946e10b4db9759ecf426cbeee8b09b5597049 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 5 Nov 2019 16:13:05 +0800
+Subject: [PATCH 4359/4736] drm/amd/powerplay: update Arcturus driver-smu
+ interface header
+
+To fit the latest SMU firmware.
+
+Change-Id: Ib197e6186127121b4ae276639fa66677094a7d01
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h | 2 +-
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h                | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+index 886b9a21ebd8..a886f0644d24 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+@@ -159,7 +159,7 @@
+ //FIXME need updating
+ // Debug Overrides Bitmask
+ #define DPM_OVERRIDE_DISABLE_UCLK_PID               0x00000001
+-#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCN_FCLK      0x00000002
++#define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK     0x00000002
+ 
+ // I2C Config Bit Defines
+ #define I2C_CONTROLLER_ENABLED           1
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 88ee66683271..36028e9d1011 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -27,7 +27,7 @@
+ 
+ #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
+ #define SMU11_DRIVER_IF_VERSION_VG20 0x13
+-#define SMU11_DRIVER_IF_VERSION_ARCT 0x0F
++#define SMU11_DRIVER_IF_VERSION_ARCT 0x10
+ #define SMU11_DRIVER_IF_VERSION_NV10 0x33
+ #define SMU11_DRIVER_IF_VERSION_NV12 0x33
+ #define SMU11_DRIVER_IF_VERSION_NV14 0x34
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4360-drm-amd-swSMU-fix-smu-workload-bit-map-error.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4360-drm-amd-swSMU-fix-smu-workload-bit-map-error.patch
new file mode 100644
index 00000000..1188e489
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4360-drm-amd-swSMU-fix-smu-workload-bit-map-error.patch
@@ -0,0 +1,47 @@
+From 39bb749823ebf64f5e2a7b9d1eaeb66a57a53c51 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Tue, 5 Nov 2019 18:16:38 +0800
+Subject: [PATCH 4360/4736] drm/amd/swSMU: fix smu workload bit map error
+
+fix workload bit (WORKLOAD_PPLIB_COMPUTE_BIT) map error
+on vega20 and navi asic.
+
+fix commit:
+drm/amd/powerplay: add function get_workload_type_map for swsmu
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 2 +-
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 34390656a03e..010be21bee5b 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -206,7 +206,7 @@ static struct smu_11_0_cmn2aisc_mapping navi10_workload_map[PP_SMC_POWER_PROFILE
+ 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,		WORKLOAD_PPLIB_POWER_SAVING_BIT),
+ 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,		WORKLOAD_PPLIB_VIDEO_BIT),
+ 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,			WORKLOAD_PPLIB_VR_BIT),
+-	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,		WORKLOAD_PPLIB_CUSTOM_BIT),
++	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,		WORKLOAD_PPLIB_COMPUTE_BIT),
+ 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 7125406c6256..e00ffbbde791 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -221,7 +221,7 @@ static struct smu_11_0_cmn2aisc_mapping vega20_workload_map[PP_SMC_POWER_PROFILE
+ 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,		WORKLOAD_PPLIB_POWER_SAVING_BIT),
+ 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,		WORKLOAD_PPLIB_VIDEO_BIT),
+ 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,			WORKLOAD_PPLIB_VR_BIT),
+-	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,		WORKLOAD_PPLIB_CUSTOM_BIT),
++	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,		WORKLOAD_PPLIB_COMPUTE_BIT),
+ 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4361-drm-amdgpu-register-gpu-instance-before-fan-boost-fe.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4361-drm-amdgpu-register-gpu-instance-before-fan-boost-fe.patch
new file mode 100644
index 00000000..2593c094
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4361-drm-amdgpu-register-gpu-instance-before-fan-boost-fe.patch
@@ -0,0 +1,50 @@
+From e284bbcf32d1b56f3a271dedf13859f0d66e5208 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 5 Nov 2019 18:13:49 +0800
+Subject: [PATCH 4361/4736] drm/amdgpu: register gpu instance before fan boost
+ feature enablment
+
+Otherwise, the feature enablement will be skipped due to wrong count.
+Caused by "drm/amdgpu: fix a race in GPU reset with IB test (v2)".
+
+Change-Id: Id576090d7ce7645a5c98ac160e0af730a51526b0
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c    | 1 -
+ 2 files changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index beeae2573cb0..edc11fb2bf24 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3036,6 +3036,13 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ 			DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
+ 	}
+ 
++	/*
++	 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
++	 * Otherwise the mgpu fan boost feature will be skipped due to the
++	 * gpu instance is counted less.
++	 */
++	amdgpu_register_gpu_instance(adev);
++
+ 	/* enable clockgating, etc. after ib tests, etc. since some blocks require
+ 	 * explicit gating rather than handling it automatically.
+ 	 */
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 5abbfc488022..488258f1138d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -187,7 +187,6 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
+ 		pm_runtime_put_autosuspend(dev->dev);
+ 	}
+ 
+-	amdgpu_register_gpu_instance(adev);
+ out:
+ 	if (r) {
+ 		/* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4362-drm-amdgpu-fix-possible-pstate-switch-race-condition.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4362-drm-amdgpu-fix-possible-pstate-switch-race-condition.patch
new file mode 100644
index 00000000..0d8de457
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4362-drm-amdgpu-fix-possible-pstate-switch-race-condition.patch
@@ -0,0 +1,104 @@
+From 4f712c43a25f97247ad8b2aaa32c255b09704004 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 31 Oct 2019 14:15:29 +0800
+Subject: [PATCH 4362/4736] drm/amdgpu: fix possible pstate switch race
+ condition
+
+Added lock protection so that the p-state switch will
+be guarded to be sequential. Also update the hive
+pstate only all device from the hive are in the same
+state.
+
+Change-Id: I165a6f44e8aec1e6da56eefa0fc49d36670e56fe
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  3 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 34 ++++++++++++++++++++++--
+ 2 files changed, 35 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 2eb3a6bcbd6c..715739799383 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1025,6 +1025,9 @@ struct amdgpu_device {
+ 
+ 	uint64_t			unique_id;
+ 	uint64_t	df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
++
++	/* device pstate */
++	int				pstate;
+ };
+ 
+ static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+index 44a0ee91b42d..e58bad7f64c6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+@@ -274,12 +274,18 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
+ {
+ 	int ret = 0;
+ 	struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
++	struct amdgpu_device *tmp_adev;
++	bool update_hive_pstate = true;
+ 
+ 	if (!hive)
+ 		return 0;
+ 
+-	if (hive->pstate == pstate)
++	mutex_lock(&hive->hive_lock);
++
++	if (hive->pstate == pstate) {
++		mutex_unlock(&hive->hive_lock);
+ 		return 0;
++	}
+ 
+ 	dev_dbg(adev->dev, "Set xgmi pstate %d.\n", pstate);
+ 
+@@ -290,11 +296,32 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
+ 		ret = adev->powerplay.pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle,
+ 								pstate);
+ 
+-	if (ret)
++	if (ret) {
+ 		dev_err(adev->dev,
+ 			"XGMI: Set pstate failure on device %llx, hive %llx, ret %d",
+ 			adev->gmc.xgmi.node_id,
+ 			adev->gmc.xgmi.hive_id, ret);
++		goto out;
++	}
++
++	/* Update device pstate */
++	adev->pstate = pstate;
++
++	/*
++	 * Update the hive pstate only all devices of the hive
++	 * are in the same pstate
++	 */
++	list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
++		if (tmp_adev->pstate != adev->pstate) {
++			update_hive_pstate = false;
++			break;
++		}
++	}
++	if (update_hive_pstate)
++		hive->pstate = pstate;
++
++out:
++	mutex_unlock(&hive->hive_lock);
+ 
+ 	return ret;
+ }
+@@ -369,6 +396,9 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
+ 		goto exit;
+ 	}
+ 
++	/* Set default device pstate */
++	adev->pstate = -1;
++
+ 	top_info = &adev->psp.xgmi_context.top_info;
+ 
+ 	list_add_tail(&adev->gmc.xgmi.head, &hive->device_list);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4363-drm-amdgpu-perform-p-state-switch-after-the-whole-hi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4363-drm-amdgpu-perform-p-state-switch-after-the-whole-hi.patch
new file mode 100644
index 00000000..f96d7ef2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4363-drm-amdgpu-perform-p-state-switch-after-the-whole-hi.patch
@@ -0,0 +1,92 @@
+From aa69b8c4902268b4cc26a99362ff758d03c2710c Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 5 Nov 2019 15:15:33 +0800
+Subject: [PATCH 4363/4736] drm/amdgpu: perform p-state switch after the whole
+ hive initialized
+
+P-state switch should be performed after all devices from the hive
+get initialized.
+
+Change-Id: Ifc7cac9ef0cf250447d2a412da35d601e2ac79ec
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+Reviewed-by:  Jonathan Kim <Jonathan.Kim at amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 47 ++++++++++++++++------
+ 1 file changed, 35 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index edc11fb2bf24..21ff9f6da355 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2057,6 +2057,7 @@ static int amdgpu_device_enable_mgpu_fan_boost(void)
+  */
+ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
+ {
++	struct amdgpu_gpu_instance *gpu_instance;
+ 	int i = 0, r;
+ 
+ 	for (i = 0; i < adev->num_ip_blocks; i++) {
+@@ -2082,6 +2083,40 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
+ 	if (r)
+ 		DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
+ 
++
++	if (adev->gmc.xgmi.num_physical_nodes > 1) {
++		mutex_lock(&mgpu_info.mutex);
++
++		/*
++		 * Reset device p-state to low as this was booted with high.
++		 *
++		 * This should be performed only after all devices from the same
++		 * hive get initialized.
++		 *
++		 * However, it's unknown how many device in the hive in advance.
++		 * As this is counted one by one during devices initializations.
++		 *
++		 * So, we wait for all XGMI interlinked devices initialized.
++		 * This may bring some delays as those devices may come from
++		 * different hives. But that should be OK.
++		 */
++		if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
++			for (i = 0; i < mgpu_info.num_gpu; i++) {
++				gpu_instance = &(mgpu_info.gpu_ins[i]);
++				if (gpu_instance->adev->flags & AMD_IS_APU)
++					continue;
++
++				r = amdgpu_xgmi_set_pstate(gpu_instance->adev, 0);
++				if (r) {
++					DRM_ERROR("pstate setting failed (%d).\n", r);
++					break;
++				}
++			}
++		}
++
++		mutex_unlock(&mgpu_info.mutex);
++	}
++
+ 	return 0;
+ }
+ 
+@@ -2193,18 +2228,6 @@ static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
+ 	r = amdgpu_ib_ring_tests(adev);
+ 	if (r)
+ 		DRM_ERROR("ib ring test failed (%d).\n", r);
+-
+-	/*
+-	 * set to low pstate by default
+-	 * This should be performed after all devices from
+-	 * XGMI finish their initializations. Thus it's moved
+-	 * to here.
+-	 * The time delay is 2S. TODO: confirm whether that
+-	 * is enough for all possible XGMI setups.
+-	 */
+-	r = amdgpu_xgmi_set_pstate(adev, 0);
+-	if (r)
+-		DRM_ERROR("pstate setting failed (%d).\n", r);
+ }
+ 
+ static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4364-drm-amdgpu-add-dummy-read-by-engines-for-some-GCVM-s.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4364-drm-amdgpu-add-dummy-read-by-engines-for-some-GCVM-s.patch
new file mode 100644
index 00000000..225b7964
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4364-drm-amdgpu-add-dummy-read-by-engines-for-some-GCVM-s.patch
@@ -0,0 +1,201 @@
+From 9ec6a9973b1007b2aba9d1b28088629819859837 Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Thu, 10 Oct 2019 11:02:33 +0800
+Subject: [PATCH 4364/4736] drm/amdgpu: add dummy read by engines for some GCVM
+ status registers in gfx10
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The GRBM register interface is now capable of bursting 1 cycle per
+register wr->wr, wr->rd much faster than previous muticycle per
+transaction done interface.  This has caused a problem where
+status registers requiring HW to update have a 1 cycle delay, due
+to the register update having to go through GRBM.
+
+For cp ucode, it has realized dummy read in cp firmware.It covers
+the use of WAIT_REG_MEM operation 1 case only.So it needs to call
+gfx_v10_0_wait_reg_mem in gfx10. Besides it also needs to add warning to
+update firmware in case firmware is too old to have function to realize
+dummy read in cp firmware.
+
+For sdma ucode, it hasn't realized dummy read in sdma firmware. sdma is
+moved to gfxhub in gfx10. So it needs to add dummy read in driver
+between amdgpu_ring_emit_wreg and amdgpu_ring_emit_reg_wait for sdma_v5_0.
+
+Change-Id: Ie028f37eb789966d4593984bd661b248ebeb1ac3
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  1 +
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 48 +++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c  |  8 ++---
+ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c  | 13 ++++++-
+ 4 files changed, 64 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+index 459aa9059542..a74ecd449775 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+@@ -267,6 +267,7 @@ struct amdgpu_gfx {
+ 	uint32_t			mec2_feature_version;
+ 	bool				mec_fw_write_wait;
+ 	bool				me_fw_write_wait;
++	bool				cp_fw_write_wait;
+ 	struct amdgpu_ring		gfx_ring[AMDGPU_MAX_GFX_RINGS];
+ 	unsigned			num_gfx_rings;
+ 	struct amdgpu_ring		compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 17a5cbfd0024..c7a6f98bf6b8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -561,6 +561,32 @@ static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
+ 	kfree(adev->gfx.rlc.register_list_format);
+ }
+ 
++static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
++{
++	adev->gfx.cp_fw_write_wait = false;
++
++	switch (adev->asic_type) {
++	case CHIP_NAVI10:
++	case CHIP_NAVI12:
++	case CHIP_NAVI14:
++		if ((adev->gfx.me_fw_version >= 0x00000046) &&
++		    (adev->gfx.me_feature_version >= 27) &&
++		    (adev->gfx.pfp_fw_version >= 0x00000068) &&
++		    (adev->gfx.pfp_feature_version >= 27) &&
++		    (adev->gfx.mec_fw_version >= 0x0000005b) &&
++		    (adev->gfx.mec_feature_version >= 27))
++			adev->gfx.cp_fw_write_wait = true;
++		break;
++	default:
++		break;
++	}
++
++	if (adev->gfx.cp_fw_write_wait == false)
++		DRM_WARN_ONCE("Warning: check cp_fw_version and update it to realize \
++			      GRBM requires 1-cycle delay in cp firmware\n");
++}
++
++
+ static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
+ {
+ 	const struct rlc_firmware_header_v2_1 *rlc_hdr;
+@@ -829,6 +855,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
+ 		}
+ 	}
+ 
++	gfx_v10_0_check_fw_write_wait(adev);
+ out:
+ 	if (err) {
+ 		dev_err(adev->dev,
+@@ -4768,6 +4795,24 @@ static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+ 	gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
+ }
+ 
++static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
++						   uint32_t reg0, uint32_t reg1,
++						   uint32_t ref, uint32_t mask)
++{
++	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
++	struct amdgpu_device *adev = ring->adev;
++	bool fw_version_ok = false;
++
++	fw_version_ok = adev->gfx.cp_fw_write_wait;
++
++	if (fw_version_ok)
++		gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
++				       ref, mask, 0x20);
++	else
++		amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
++							   ref, mask);
++}
++
+ static void
+ gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
+ 				      uint32_t me, uint32_t pipe,
+@@ -5158,6 +5203,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
+ 	.emit_tmz = gfx_v10_0_ring_emit_tmz,
+ 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
+ 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
++	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
+ };
+ 
+ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
+@@ -5191,6 +5237,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
+ 	.pad_ib = amdgpu_ring_generic_pad_ib,
+ 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
+ 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
++	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
+ };
+ 
+ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
+@@ -5221,6 +5268,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
+ 	.emit_rreg = gfx_v10_0_ring_emit_rreg,
+ 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
+ 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
++	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
+ };
+ 
+ static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index 3b00bce14cfb..af2615ba52aa 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -344,11 +344,9 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+ 	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
+ 			      upper_32_bits(pd_addr));
+ 
+-	amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req);
+-
+-	/* wait for the invalidate to complete */
+-	amdgpu_ring_emit_reg_wait(ring, hub->vm_inv_eng0_ack + eng,
+-				  1 << vmid, 1 << vmid);
++	amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
++					    hub->vm_inv_eng0_ack + eng,
++					    req, 1 << vmid);
+ 
+ 	return pd_addr;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+index 3460c00f3eaa..ec47542e21b0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+@@ -1170,6 +1170,16 @@ static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+ 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
+ }
+ 
++static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
++						   uint32_t reg0, uint32_t reg1,
++						   uint32_t ref, uint32_t mask)
++{
++	amdgpu_ring_emit_wreg(ring, reg0, ref);
++	/* wait for a cycle to reset vm_inv_eng*_ack */
++	amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
++	amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
++}
++
+ static int sdma_v5_0_early_init(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+@@ -1585,7 +1595,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
+ 		6 + /* sdma_v5_0_ring_emit_pipeline_sync */
+ 		/* sdma_v5_0_ring_emit_vm_flush */
+ 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
+-		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
++		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
+ 		10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
+ 	.emit_ib_size = 7 + 6, /* sdma_v5_0_ring_emit_ib */
+ 	.emit_ib = sdma_v5_0_ring_emit_ib,
+@@ -1599,6 +1609,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
+ 	.pad_ib = sdma_v5_0_ring_pad_ib,
+ 	.emit_wreg = sdma_v5_0_ring_emit_wreg,
+ 	.emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
++	.emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
+ 	.init_cond_exec = sdma_v5_0_ring_init_cond_exec,
+ 	.patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
+ 	.preempt_ib = sdma_v5_0_ring_preempt_ib,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4365-drm-amdgpu-add-warning-for-GRBM-1-cycle-delay-issue-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4365-drm-amdgpu-add-warning-for-GRBM-1-cycle-delay-issue-.patch
new file mode 100644
index 00000000..85257463
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4365-drm-amdgpu-add-warning-for-GRBM-1-cycle-delay-issue-.patch
@@ -0,0 +1,41 @@
+From e5c5504c64389201bec2377de804e4277bb18fc8 Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Tue, 5 Nov 2019 18:29:12 +0800
+Subject: [PATCH 4365/4736] drm/amdgpu: add warning for GRBM 1-cycle delay
+ issue in gfx9
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It needs to add warning to update firmware in gfx9
+in case that firmware is too old to have function to
+realize dummy read in cp firmware.
+
+Change-Id: I6aef94f0823138f244f1eedb62fde833dd697023
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index d521facadf59..a3bb662acb1f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -982,6 +982,13 @@ static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
+ 	adev->gfx.me_fw_write_wait = false;
+ 	adev->gfx.mec_fw_write_wait = false;
+ 
++	if ((adev->gfx.mec_fw_version < 0x000001a5) ||
++	    (adev->gfx.mec_feature_version < 46) ||
++	    (adev->gfx.pfp_fw_version < 0x000000b7) ||
++	    (adev->gfx.pfp_feature_version < 46))
++		DRM_WARN_ONCE("Warning: check cp_fw_version and update it to realize \
++			      GRBM requires 1-cycle delay in cp firmware\n");
++
+ 	switch (adev->asic_type) {
+ 	case CHIP_VEGA10:
+ 		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4366-drm-amdgpu-change-read-of-GPU-clock-counter-on-Vega1.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4366-drm-amdgpu-change-read-of-GPU-clock-counter-on-Vega1.patch
new file mode 100644
index 00000000..47afacc7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4366-drm-amdgpu-change-read-of-GPU-clock-counter-on-Vega1.patch
@@ -0,0 +1,48 @@
+From d471a8a8f117b852f6aa081443747ed8e4b66aa7 Mon Sep 17 00:00:00 2001
+From: Eric Huang <JinhuiEric.Huang@amd.com>
+Date: Tue, 5 Nov 2019 16:29:57 -0500
+Subject: [PATCH 4366/4736] drm/amdgpu: change read of GPU clock counter on
+ Vega10 VF
+
+Using unified VBIOS has performance drop in sriov environment.
+The fix is switching to another register instead.
+
+Signed-off-by: Eric Huang <JinhuiEric.Huang@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 19 ++++++++++++++++---
+ 1 file changed, 16 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index a3bb662acb1f..4fe3c5ebaf58 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -3887,9 +3887,22 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
+ 	uint64_t clock;
+ 
+ 	mutex_lock(&adev->gfx.gpu_clock_mutex);
+-	WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
+-	clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
+-		((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
++	if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
++		uint32_t tmp, lsb, msb, i = 0;
++		do {
++			if (i != 0)
++				udelay(1);
++			tmp = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);
++			lsb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_LSB);
++			msb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);
++			i++;
++		} while (unlikely(tmp != msb) && (i < adev->usec_timeout));
++		clock = (uint64_t)lsb | ((uint64_t)msb << 32ULL);
++	} else {
++		WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
++		clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
++			((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
++	}
+ 	mutex_unlock(&adev->gfx.gpu_clock_mutex);
+ 	return clock;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4367-drm-amdgpu-remove-4-set-but-not-used-variable-in-amd.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4367-drm-amdgpu-remove-4-set-but-not-used-variable-in-amd.patch
new file mode 100644
index 00000000..cc8fb954
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4367-drm-amdgpu-remove-4-set-but-not-used-variable-in-amd.patch
@@ -0,0 +1,70 @@
+From cec4fa968f7c75f23a84007aa104f5816771ae6b Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Mon, 4 Nov 2019 21:27:20 +0800
+Subject: [PATCH 4367/4736] drm/amdgpu: remove 4 set but not used variable in
+ amdgpu_atombios_get_connector_info_from_object_table
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c: In function
+'amdgpu_atombios_get_connector_info_from_object_table':
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:376:26: warning: variable
+'grph_obj_num' set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:376:13: warning: variable
+'grph_obj_id' set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:341:37: warning: variable
+'con_obj_type' set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:341:24: warning: variable
+'con_obj_num' set but not used [-Wunused-but-set-variable]
+
+They are never used, so can be removed.
+
+Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 19 ++-----------------
+ 1 file changed, 2 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+index a0d582a1e8c6..7d941b3802a6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+@@ -338,17 +338,9 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *
+ 		path_size += le16_to_cpu(path->usSize);
+ 
+ 		if (device_support & le16_to_cpu(path->usDeviceTag)) {
+-			uint8_t con_obj_id, con_obj_num, con_obj_type;
+-
+-			con_obj_id =
++			uint8_t con_obj_id =
+ 			    (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
+ 			    >> OBJECT_ID_SHIFT;
+-			con_obj_num =
+-			    (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
+-			    >> ENUM_ID_SHIFT;
+-			con_obj_type =
+-			    (le16_to_cpu(path->usConnObjectId) &
+-			     OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
+ 
+ 			/* Skip TV/CV support */
+ 			if ((le16_to_cpu(path->usDeviceTag) ==
+@@ -373,14 +365,7 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *
+ 			router.ddc_valid = false;
+ 			router.cd_valid = false;
+ 			for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
+-				uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
+-
+-				grph_obj_id =
+-				    (le16_to_cpu(path->usGraphicObjIds[j]) &
+-				     OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
+-				grph_obj_num =
+-				    (le16_to_cpu(path->usGraphicObjIds[j]) &
+-				     ENUM_ID_MASK) >> ENUM_ID_SHIFT;
++				uint8_t grph_obj_type=
+ 				grph_obj_type =
+ 				    (le16_to_cpu(path->usGraphicObjIds[j]) &
+ 				     OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4368-drm-amdgpu-add-function-parameter-description-in-amd.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4368-drm-amdgpu-add-function-parameter-description-in-amd.patch
new file mode 100644
index 00000000..1b657d43
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4368-drm-amdgpu-add-function-parameter-description-in-amd.patch
@@ -0,0 +1,33 @@
+From da40b874e2cd1fd83846f38d27f240dc467c1bfc Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Mon, 4 Nov 2019 21:27:21 +0800
+Subject: [PATCH 4368/4736] drm/amdgpu: add function parameter description in
+ 'amdgpu_device_set_cg_state'
+
+Fixes gcc warning:
+
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1954: warning: Function
+parameter or member 'state' not described in 'amdgpu_device_set_cg_state'
+
+Fixes: e3ecdffac9cc ("drm/amdgpu: add documentation for amdgpu_device.c")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 21ff9f6da355..09ef0eaf1abc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1938,6 +1938,7 @@ static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
+  * amdgpu_device_set_cg_state - set clockgating for amdgpu device
+  *
+  * @adev: amdgpu_device pointer
++ * @state: clockgating state (gate or ungate)
+  *
+  * The list of all the hardware IPs that make up the asic is walked and the
+  * set_clockgating_state callbacks are run.
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4369-drm-amdgpu-add-function-parameter-description-in-amd.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4369-drm-amdgpu-add-function-parameter-description-in-amd.patch
new file mode 100644
index 00000000..d70b6a16
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4369-drm-amdgpu-add-function-parameter-description-in-amd.patch
@@ -0,0 +1,33 @@
+From fe9f281a14d18acee19a82c9843c6d53de630ac9 Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Mon, 4 Nov 2019 21:27:22 +0800
+Subject: [PATCH 4369/4736] drm/amdgpu: add function parameter description in
+ 'amdgpu_gart_bind'
+
+Fixes gcc warning:
+
+drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c:313: warning: Function
+parameter or member 'flags' not described in 'amdgpu_gart_bind'
+
+Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+index 83f4dcb7926c..f6ded1268d94 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+@@ -297,6 +297,7 @@ int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
+  * @pages: number of pages to bind
+  * @pagelist: pages to bind
+  * @dma_addr: DMA addresses of pages
++ * @flags: page table entry flags
+  *
+  * Binds the requested pages to the gart page table
+  * (all asics).
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4370-drm-amdgpu-remove-set-but-not-used-variable-dig_conn.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4370-drm-amdgpu-remove-set-but-not-used-variable-dig_conn.patch
new file mode 100644
index 00000000..05633a30
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4370-drm-amdgpu-remove-set-but-not-used-variable-dig_conn.patch
@@ -0,0 +1,49 @@
+From 00891ae85afb4ed6db6b4b091f324ac39062dc38 Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Mon, 4 Nov 2019 21:27:23 +0800
+Subject: [PATCH 4370/4736] drm/amdgpu: remove set but not used variable
+ 'dig_connector'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/atombios_dp.c: In function
+‘amdgpu_atombios_dp_get_panel_mode’:
+drivers/gpu/drm/amd/amdgpu/atombios_dp.c:364:36: warning: variable
+‘dig_connector’ set but not used [-Wunused-but-set-variable]
+
+It is never used, so can be removed.
+
+Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+index f81068ba4cc6..d712dee89254 100644
+--- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
++++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+@@ -361,7 +361,6 @@ int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder,
+ 			       struct drm_connector *connector)
+ {
+ 	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
+-	struct amdgpu_connector_atom_dig *dig_connector;
+ 	int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
+ 	u16 dp_bridge = amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector);
+ 	u8 tmp;
+@@ -369,8 +368,6 @@ int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder,
+ 	if (!amdgpu_connector->con_priv)
+ 		return panel_mode;
+ 
+-	dig_connector = amdgpu_connector->con_priv;
+-
+ 	if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
+ 		/* DP bridge chips */
+ 		if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4371-drm-amdgpu-remove-set-but-not-used-variable-dig.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4371-drm-amdgpu-remove-set-but-not-used-variable-dig.patch
new file mode 100644
index 00000000..530e16c5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4371-drm-amdgpu-remove-set-but-not-used-variable-dig.patch
@@ -0,0 +1,45 @@
+From c52fd8d3f5d9da3621ce4caef26378ae4381f402 Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Mon, 4 Nov 2019 21:27:24 +0800
+Subject: [PATCH 4371/4736] drm/amdgpu: remove set but not used variable 'dig'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/atombios_dp.c: In function
+‘amdgpu_atombios_dp_link_train’:
+drivers/gpu/drm/amd/amdgpu/atombios_dp.c:716:34: warning: variable ‘dig’
+set but not used [-Wunused-but-set-variable]
+
+Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+index d712dee89254..8abe9beab034 100644
+--- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
++++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+@@ -710,7 +710,6 @@ void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder,
+ 	struct drm_device *dev = encoder->dev;
+ 	struct amdgpu_device *adev = dev->dev_private;
+ 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
+-	struct amdgpu_encoder_atom_dig *dig;
+ 	struct amdgpu_connector *amdgpu_connector;
+ 	struct amdgpu_connector_atom_dig *dig_connector;
+ 	struct amdgpu_atombios_dp_link_train_info dp_info;
+@@ -718,7 +717,6 @@ void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder,
+ 
+ 	if (!amdgpu_encoder->enc_priv)
+ 		return;
+-	dig = amdgpu_encoder->enc_priv;
+ 
+ 	amdgpu_connector = to_amdgpu_connector(connector);
+ 	if (!amdgpu_connector->con_priv)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4372-drm-amdgpu-remove-always-false-comparison-in-amdgpu_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4372-drm-amdgpu-remove-always-false-comparison-in-amdgpu_.patch
new file mode 100644
index 00000000..b072100d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4372-drm-amdgpu-remove-always-false-comparison-in-amdgpu_.patch
@@ -0,0 +1,45 @@
+From 937e4c99390453264af0907239da7c6adf76a477 Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Mon, 4 Nov 2019 21:27:25 +0800
+Subject: [PATCH 4372/4736] drm/amdgpu: remove always false comparison in
+ 'amdgpu_atombios_i2c_process_i2c_ch'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wtype-limits' warning:
+
+drivers/gpu/drm/amd/amdgpu/atombios_i2c.c: In function
+‘amdgpu_atombios_i2c_process_i2c_ch’:
+drivers/gpu/drm/amd/amdgpu/atombios_i2c.c:79:11: warning: comparison is
+always false due to limited range of data type [-Wtype-limits]
+
+'num' is 'u8', so it will never be greater than 'TOM_MAX_HW_I2C_READ',
+which is defined as 255. Therefore, the comparison can be removed.
+
+Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/atombios_i2c.c | 5 -----
+ 1 file changed, 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
+index f9b2ce9a98f3..9c7d0bf6712a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
++++ b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
+@@ -76,11 +76,6 @@ static int amdgpu_atombios_i2c_process_i2c_ch(struct amdgpu_i2c_chan *chan,
+ 		}
+ 		args.lpI2CDataOut = cpu_to_le16(out);
+ 	} else {
+-		if (num > ATOM_MAX_HW_I2C_READ) {
+-			DRM_ERROR("hw i2c: tried to read too many bytes (%d vs 255)\n", num);
+-			r = -EINVAL;
+-			goto done;
+-		}
+ 		args.ucRegIndex = 0;
+ 		args.lpI2CDataOut = 0;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4373-drm-amdgpu-remove-set-but-not-used-variable-mc_share.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4373-drm-amdgpu-remove-set-but-not-used-variable-mc_share.patch
new file mode 100644
index 00000000..b51d17fe
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4373-drm-amdgpu-remove-set-but-not-used-variable-mc_share.patch
@@ -0,0 +1,47 @@
+From cfbff3407485e3af6c75b81c0aa39d8724600869 Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Mon, 4 Nov 2019 21:27:26 +0800
+Subject: [PATCH 4373/4736] drm/amdgpu: remove set but not used variable
+ 'mc_shared_chmap'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c: In function
+‘gfx_v8_0_gpu_early_init’:
+drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:1713:6: warning: variable
+‘mc_shared_chmap’ set but not used [-Wunused-but-set-variable]
+
+Fixes: 0bde3a95eaa9 ("drm/amdgpu: split gfx8 gpu init into sw and hw parts")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index c0bcf5d91f1f..1f4f7c05e269 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -1706,7 +1706,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
+ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
+ {
+ 	u32 gb_addr_config;
+-	u32 mc_shared_chmap, mc_arb_ramcfg;
++	u32 mc_arb_ramcfg;
+ 	u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
+ 	u32 tmp;
+ 	int ret;
+@@ -1846,7 +1846,6 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
+ 		break;
+ 	}
+ 
+-	mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
+ 	adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
+ 	mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4374-drm-amdgpu-fix-potential-double-drop-fence-reference.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4374-drm-amdgpu-fix-potential-double-drop-fence-reference.patch
new file mode 100644
index 00000000..b17f6413
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4374-drm-amdgpu-fix-potential-double-drop-fence-reference.patch
@@ -0,0 +1,44 @@
+From 08d4288d57725c283f2c0272870ee3e95788eb54 Mon Sep 17 00:00:00 2001
+From: Pan Bian <bianpan2016@163.com>
+Date: Wed, 6 Nov 2019 17:14:45 +0800
+Subject: [PATCH 4374/4736] drm/amdgpu: fix potential double drop fence
+ reference
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The object fence is not set to NULL after its reference is dropped. As a
+result, its reference may be dropped again if error occurs after that,
+which may lead to a use after free bug. To avoid the issue, fence is
+explicitly set to NULL after dropping its reference.
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Pan Bian <bianpan2016@163.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
+index 8904e62dca7a..41d3142ef3cf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
+@@ -138,6 +138,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
+ 		}
+ 
+ 		dma_fence_put(fence);
++		fence = NULL;
+ 
+ 		r = amdgpu_bo_kmap(vram_obj, &vram_map);
+ 		if (r) {
+@@ -183,6 +184,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
+ 		}
+ 
+ 		dma_fence_put(fence);
++		fence = NULL;
+ 
+ 		r = amdgpu_bo_kmap(gtt_obj[i], &gtt_map);
+ 		if (r) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4375-drm-amd-powerplay-fix-struct-init-in-renoir_print_cl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4375-drm-amd-powerplay-fix-struct-init-in-renoir_print_cl.patch
new file mode 100644
index 00000000..f8cd8c6f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4375-drm-amd-powerplay-fix-struct-init-in-renoir_print_cl.patch
@@ -0,0 +1,41 @@
+From 8122c6fe1715d14e7faf9acb35c113c3a90ede43 Mon Sep 17 00:00:00 2001
+From: Raul E Rangel <rrangel@chromium.org>
+Date: Tue, 5 Nov 2019 15:58:02 -0700
+Subject: [PATCH 4375/4736] drm/amd/powerplay: fix struct init in
+ renoir_print_clk_levels
+
+drivers/gpu/drm/amd/powerplay/renoir_ppt.c:186:2: error: missing braces
+around initializer [-Werror=missing-braces]
+  SmuMetrics_t metrics = {0};
+    ^
+
+Fixes: 8b8031703bd7 ("drm/amd/powerplay: implement sysfs for getting dpm clock")
+
+Signed-off-by: Raul E Rangel <rrangel@chromium.org>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 4a9751971a9d..04daf7e9fe05 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -180,11 +180,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
+ 	int i, size = 0, ret = 0;
+ 	uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
+ 	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
+-	SmuMetrics_t metrics = {0};
++	SmuMetrics_t metrics;
+ 
+ 	if (!clk_table || clk_type >= SMU_CLK_COUNT)
+ 		return -EINVAL;
+ 
++	memset(&metrics, 0, sizeof(metrics));
++
+ 	ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
+ 			       (void *)&metrics, false);
+ 	if (ret)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4376-drm-amdgpu-fix-double-reference-dropping.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4376-drm-amdgpu-fix-double-reference-dropping.patch
new file mode 100644
index 00000000..87c3fcc0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4376-drm-amdgpu-fix-double-reference-dropping.patch
@@ -0,0 +1,54 @@
+From 2885f3f5fb34f6e6f89821501c30491e125b4b0f Mon Sep 17 00:00:00 2001
+From: Pan Bian <bianpan2016@163.com>
+Date: Wed, 6 Nov 2019 19:35:43 +0800
+Subject: [PATCH 4376/4736] drm/amdgpu: fix double reference dropping
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The reference to object fence is dropped at the end of the loop.
+However, it is dropped again outside the loop. The reference can be
+dropped immediately after calling dma_fence_wait() in the loop and
+thus the dropping operation outside the loop can be removed.
+
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Pan Bian <bianpan2016@163.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+index 3079ea8523c5..0f2aeb41e5c8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+@@ -33,7 +33,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size,
+ {
+ 	unsigned long start_jiffies;
+ 	unsigned long end_jiffies;
+-	struct dma_fence *fence = NULL;
++	struct dma_fence *fence;
+ 	int i, r;
+ 
+ 	start_jiffies = jiffies;
+@@ -44,16 +44,14 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size,
+ 		if (r)
+ 			goto exit_do_move;
+ 		r = dma_fence_wait(fence, false);
++		dma_fence_put(fence);
+ 		if (r)
+ 			goto exit_do_move;
+-		dma_fence_put(fence);
+ 	}
+ 	end_jiffies = jiffies;
+ 	r = jiffies_to_msecs(end_jiffies - start_jiffies);
+ 
+ exit_do_move:
+-	if (fence)
+-		dma_fence_put(fence);
+ 	return r;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4377-drm-amdgpu-renoir-move-gfxoff-handling-into-gfx9-mod.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4377-drm-amdgpu-renoir-move-gfxoff-handling-into-gfx9-mod.patch
new file mode 100644
index 00000000..aeb89f2d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4377-drm-amdgpu-renoir-move-gfxoff-handling-into-gfx9-mod.patch
@@ -0,0 +1,51 @@
+From 35d085067b21003e3c56a102d765a045ff547628 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 29 Oct 2019 10:36:22 -0400
+Subject: [PATCH 4377/4736] drm/amdgpu/renoir: move gfxoff handling into gfx9
+ module
+
+To properly handle the option parsing ordering.
+
+Reviewed-by: Yong Zhao <yong.zhao@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 ++++++
+ drivers/gpu/drm/amd/amdgpu/soc15.c    | 5 -----
+ 2 files changed, 6 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 4fe3c5ebaf58..b7ce3217fcf8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -1055,6 +1055,12 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
+ 			    !adev->gfx.rlc.is_rlc_v2_1))
+ 			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ 
++		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
++			adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
++				AMD_PG_SUPPORT_CP |
++				AMD_PG_SUPPORT_RLC_SMU_HS;
++		break;
++	case CHIP_RENOIR:
+ 		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+ 			adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
+ 				AMD_PG_SUPPORT_CP |
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index d3083bd2c5ae..e12cdbdd9aed 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1232,11 +1232,6 @@ static int soc15_common_early_init(void *handle)
+ 				 AMD_PG_SUPPORT_VCN |
+ 				 AMD_PG_SUPPORT_VCN_DPG;
+ 		adev->external_rev_id = adev->rev_id + 0x91;
+-
+-		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+-			adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
+-				AMD_PG_SUPPORT_CP |
+-				AMD_PG_SUPPORT_RLC_SMU_HS;
+ 		break;
+ 	default:
+ 		/* FIXME: not supported yet */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4378-drm-amdgpu-Improve-RAS-documentation-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4378-drm-amdgpu-Improve-RAS-documentation-v2.patch
new file mode 100644
index 00000000..9960cf92
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4378-drm-amdgpu-Improve-RAS-documentation-v2.patch
@@ -0,0 +1,171 @@
+From 3bdc8244e734cff375c70e51b03220787da61eed Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 30 Oct 2019 14:40:09 -0400
+Subject: [PATCH 4378/4736] drm/amdgpu: Improve RAS documentation (v2)
+
+Clarify some areas, clean up formatting, add section for
+unrecoverable error handling.
+
+v2: fix grammatical errors
+
+Reviewed-by: Yong Zhao <yong.zhao@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ Documentation/gpu/amdgpu.rst            | 35 ++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 40 ++++++++++++++++++++-----
+ 2 files changed, 68 insertions(+), 7 deletions(-)
+
+diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
+index 5b9eaf23558e..0efede580039 100644
+--- a/Documentation/gpu/amdgpu.rst
++++ b/Documentation/gpu/amdgpu.rst
+@@ -82,12 +82,21 @@ AMDGPU XGMI Support
+ AMDGPU RAS Support
+ ==================
+ 
++The AMDGPU RAS interfaces are exposed via sysfs (for informational queries) and
++debugfs (for error injection).
++
+ RAS debugfs/sysfs Control and Error Injection Interfaces
+ --------------------------------------------------------
+ 
+ .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+    :doc: AMDGPU RAS debugfs control interface
+ 
++RAS Reboot Behavior for Unrecoverable Errors
++--------------------------------------------------------
++
++.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++   :doc: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
++
+ RAS Error Count sysfs Interface
+ -------------------------------
+ 
+@@ -109,6 +118,32 @@ RAS VRAM Bad Pages sysfs Interface
+ .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+    :internal:
+ 
++Sample Code
++-----------
++Sample code for testing error injection can be found here:
++https://cgit.freedesktop.org/mesa/drm/tree/tests/amdgpu/ras_tests.c
++
++This is part of the libdrm amdgpu unit tests which cover several areas of the GPU.
++There are four sets of tests:
++
++RAS Basic Test
++
++The test verifies the RAS feature enabled status and makes sure the necessary sysfs and debugfs files
++are present.
++
++RAS Query Test
++
++This test checks the RAS availability and enablement status for each supported IP block as well as
++the error counts.
++
++RAS Inject Test
++
++This test injects errors for each IP.
++
++RAS Disable Test
++
++This test tests disabling of RAS features for each IP block.
++
+ 
+ GPU Power/Thermal Controls and Monitoring
+ =========================================
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index afc3ee47d1b2..399617932427 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -218,7 +218,7 @@ static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
+  * As their names indicate, inject operation will write the
+  * value to the address.
+  *
+- * Second member: struct ras_debug_if::op.
++ * The second member: struct ras_debug_if::op.
+  * It has three kinds of operations.
+  *
+  * - 0: disable RAS on the block. Take ::head as its data.
+@@ -226,14 +226,20 @@ static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
+  * - 2: inject errors on the block. Take ::inject as its data.
+  *
+  * How to use the interface?
+- * programs:
+- * copy the struct ras_debug_if in your codes and initialize it.
+- * write the struct to the control node.
++ *
++ * Programs
++ *
++ * Copy the struct ras_debug_if in your codes and initialize it.
++ * Write the struct to the control node.
++ *
++ * Shells
+  *
+  * .. code-block:: bash
+  *
+  *	echo op block [error [sub_block address value]] > .../ras/ras_ctrl
+  *
++ * Parameters:
++ *
+  * op: disable, enable, inject
+  *	disable: only block is needed
+  *	enable: block and error are needed
+@@ -263,8 +269,10 @@ static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
+  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
+  *
+  * .. note::
+- *	Operation is only allowed on blocks which are supported.
++ *	Operations are only allowed on blocks which are supported.
+  *	Please check ras mask at /sys/module/amdgpu/parameters/ras_mask
++ *	to see which blocks support RAS on a particular asic.
++ *
+  */
+ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
+ 		size_t size, loff_t *pos)
+@@ -320,7 +328,7 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *
+  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
+  *
+  * Some boards contain an EEPROM which is used to persistently store a list of
+- * bad pages containing ECC errors detected in vram.  This interface provides
++ * bad pages which experiences ECC errors in vram.  This interface provides
+  * a way to reset the EEPROM, e.g., after testing error injection.
+  *
+  * Usage:
+@@ -360,7 +368,7 @@ static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
+ /**
+  * DOC: AMDGPU RAS sysfs Error Count Interface
+  *
+- * It allows user to read the error count for each IP block on the gpu through
++ * It allows the user to read the error count for each IP block on the gpu through
+  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
+  *
+  * It outputs the multiple lines which report the uncorrected (ue) and corrected
+@@ -1025,6 +1033,24 @@ static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
+ }
+ /* sysfs end */
+ 
++/**
++ * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
++ *
++ * Normally when there is an uncorrectable error, the driver will reset
++ * the GPU to recover.  However, in the event of an unrecoverable error,
++ * the driver provides an interface to reboot the system automatically
++ * in that event.
++ *
++ * The following file in debugfs provides that interface:
++ * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
++ *
++ * Usage:
++ *
++ * .. code-block:: bash
++ *
++ *	echo true > .../ras/auto_reboot
++ *
++ */
+ /* debugfs begin */
+ static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
+ {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4379-drm-amd-display-Send-vblank-and-user-events-at-vsart.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4379-drm-amd-display-Send-vblank-and-user-events-at-vsart.patch
new file mode 100644
index 00000000..25dde459
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4379-drm-amd-display-Send-vblank-and-user-events-at-vsart.patch
@@ -0,0 +1,126 @@
+From d7fcb28750038aca16cae24cf87bba005eb688cc Mon Sep 17 00:00:00 2001
+From: Leo Li <sunpeng.li@amd.com>
+Date: Mon, 4 Nov 2019 09:22:23 -0500
+Subject: [PATCH 4379/4736] drm/amd/display: Send vblank and user events at
+ vsartup for DCN
+
+[Why]
+
+For DCN hardware, the crtc_high_irq handler is assigned to the vstartup
+interrupt. This is different from DCE, which has it assigned to vblank
+start.
+
+We'd like to send vblank and user events at vstartup because:
+
+* It happens close enough to vupdate - the point of no return for HW.
+
+* It is programmed as lines relative to vblank end - i.e. it is not in
+  the variable portion when VRR is enabled. We should signal user
+  events here.
+
+* The pflip interrupt responsible for sending user events today only
+  fires if the DCH HUBP component is not clock gated. In situations
+  where planes are disabled - but the CRTC is enabled - user events won't
+  be sent out, leading to flip done timeouts.
+
+Consequently, this makes vupdate on DCN hardware redundant. It will be
+removed in the next change.
+
+[How]
+
+Add a DCN-specific crtc_high_irq handler, and hook it to the VStartup
+signal. Inside the DCN handler, we send off user events if the pflip
+handler hasn't already done so.
+
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 65 ++++++++++++++++++-
+ 1 file changed, 64 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 2f31cbd164d9..1d9fcaeda025 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -483,6 +483,69 @@ static void dm_crtc_high_irq(void *interrupt_params)
+ 	}
+ }
+ 
++
++/**
++ * dm_dcn_crtc_high_irq() - Handles VStartup interrupt for DCN generation ASICs
++ * @interrupt params - interrupt parameters
++ *
++ * Notify DRM's vblank event handler at VSTARTUP
++ *
++ * Unlike DCE hardware, we trigger the handler at VSTARTUP. at which:
++ * * We are close enough to VUPDATE - the point of no return for hw
++ * * We are in the fixed portion of variable front porch when vrr is enabled
++ * * We are before VUPDATE, where double-buffered vrr registers are swapped
++ *
++ * It is therefore the correct place to signal vblank, send user flip events,
++ * and update VRR.
++ */
++static void dm_dcn_crtc_high_irq(void *interrupt_params)
++{
++	struct common_irq_params *irq_params = interrupt_params;
++	struct amdgpu_device *adev = irq_params->adev;
++	struct amdgpu_crtc *acrtc;
++	struct dm_crtc_state *acrtc_state;
++	unsigned long flags;
++
++	acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
++
++	if (!acrtc)
++		return;
++
++	acrtc_state = to_dm_crtc_state(acrtc->base.state);
++
++	DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
++				amdgpu_dm_vrr_active(acrtc_state));
++
++	amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
++	drm_crtc_handle_vblank(&acrtc->base);
++
++	spin_lock_irqsave(&adev->ddev->event_lock, flags);
++
++	if (acrtc_state->vrr_params.supported &&
++	    acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
++		mod_freesync_handle_v_update(
++		adev->dm.freesync_module,
++		acrtc_state->stream,
++		&acrtc_state->vrr_params);
++
++		dc_stream_adjust_vmin_vmax(
++			adev->dm.dc,
++			acrtc_state->stream,
++			&acrtc_state->vrr_params.adjust);
++	}
++
++	if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) {
++		if (acrtc->event) {
++			drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
++			acrtc->event = NULL;
++			drm_crtc_vblank_put(&acrtc->base);
++		}
++		acrtc->pflip_status = AMDGPU_FLIP_NONE;
++	}
++
++	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
++}
++
+ static int dm_set_clockgating_state(void *handle,
+ 		  enum amd_clockgating_state state)
+ {
+@@ -2158,7 +2221,7 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
+ 		c_irq_params->irq_src = int_params.irq_source;
+ 
+ 		amdgpu_dm_irq_register_interrupt(adev, &int_params,
+-				dm_crtc_high_irq, c_irq_params);
++				dm_dcn_crtc_high_irq, c_irq_params);
+ 	}
+ 
+ 	/* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4380-drm-amd-display-Disable-VUpdate-interrupt-for-DCN-ha.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4380-drm-amd-display-Disable-VUpdate-interrupt-for-DCN-ha.patch
new file mode 100644
index 00000000..0cac6ec1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4380-drm-amd-display-Disable-VUpdate-interrupt-for-DCN-ha.patch
@@ -0,0 +1,86 @@
+From cade2f046bd2675034117695433d20e5027e5952 Mon Sep 17 00:00:00 2001
+From: Leo Li <sunpeng.li@amd.com>
+Date: Mon, 4 Nov 2019 14:08:05 -0500
+Subject: [PATCH 4380/4736] drm/amd/display: Disable VUpdate interrupt for DCN
+ hardware
+
+[Why]
+
+On DCN hardware, the crtc_high_irq handler makes vupdate_high_irq
+handler redundant.
+
+All the vupdate handler does is handle vblank events, and update vrr
+for DCE hw (excluding VEGA, more on that later). As far as usermode is
+concerned. vstartup happens close enough to vupdate on DCN that it can
+be considered the "same". Handling vblank and updating vrr at vstartup
+effectively replaces vupdate on DCN.
+
+Vega is a bit special. Like DCN, the VRR registers on Vega are
+double-buffered, and swapped at vupdate. But Unlike DCN, it lacks a
+vstartup interrupt. This means we can't quite remove the vupdate handler
+for it, since delayed user events due to vrr are sent off there.
+
+[How]
+
+Remove registration of vupdate interrupt handler for DCN. Disable
+vupdate interrupt if asic family DCN, enable otherwise.
+
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 +++----------------
+ 1 file changed, 4 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 1d9fcaeda025..95cfe4213362 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -2224,34 +2224,6 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
+ 				dm_dcn_crtc_high_irq, c_irq_params);
+ 	}
+ 
+-	/* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
+-	 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
+-	 * to trigger at end of each vblank, regardless of state of the lock,
+-	 * matching DCE behaviour.
+-	 */
+-	for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
+-	     i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
+-	     i++) {
+-		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
+-
+-		if (r) {
+-			DRM_ERROR("Failed to add vupdate irq id!\n");
+-			return r;
+-		}
+-
+-		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
+-		int_params.irq_source =
+-			dc_interrupt_to_irq_source(dc, i, 0);
+-
+-		c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
+-
+-		c_irq_params->adev = adev;
+-		c_irq_params->irq_src = int_params.irq_source;
+-
+-		amdgpu_dm_irq_register_interrupt(adev, &int_params,
+-				dm_vupdate_high_irq, c_irq_params);
+-	}
+-
+ 	/* Use GRPH_PFLIP interrupt */
+ 	for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
+ 			i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
+@@ -4237,6 +4209,10 @@ static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
+ 	struct amdgpu_device *adev = crtc->dev->dev_private;
+ 	int rc;
+ 
++	/* Do not set vupdate for DCN hardware */
++	if (adev->family > AMDGPU_FAMILY_AI)
++		return 0;
++
+ 	irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
+ 
+ 	rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4381-drm-amdgpu-Add-comments-to-gmc-structure.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4381-drm-amdgpu-Add-comments-to-gmc-structure.patch
new file mode 100644
index 00000000..ac2d0272
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4381-drm-amdgpu-Add-comments-to-gmc-structure.patch
@@ -0,0 +1,72 @@
+From e8aa9bdf6b3194b24b75fda36504eb93c82f0f0c Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Wed, 6 Nov 2019 11:18:54 -0600
+Subject: [PATCH 4381/4736] drm/amdgpu: Add comments to gmc structure
+
+Explain fields like aper_base, agp_start etc. The definition
+of those fields are confusing as they are from different view
+(CPU or GPU). Add comments for easier understand.
+
+Change-Id: I02c2a27cd0dbc205498eb86aafa722f2e0c25fe6
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Reviewed-by: Alex Deucher <Alex.Deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 30 +++++++++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+index f9d62e80a64e..02bbb571756a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+@@ -127,18 +127,48 @@ struct amdgpu_xgmi {
+ };
+ 
+ struct amdgpu_gmc {
++	/* FB's physical address in MMIO space (for CPU to
++	 * map FB). This is different compared to the agp/
++	 * gart/vram_start/end field as the later is from
++	 * GPU's view and aper_base is from CPU's view.
++	 */
+ 	resource_size_t		aper_size;
+ 	resource_size_t		aper_base;
+ 	/* for some chips with <= 32MB we need to lie
+ 	 * about vram size near mc fb location */
+ 	u64			mc_vram_size;
+ 	u64			visible_vram_size;
++	/* AGP aperture start and end in MC address space
++	 * Driver find a hole in the MC address space
++	 * to place AGP by setting MC_VM_AGP_BOT/TOP registers
++	 * Under VMID0, logical address == MC address. AGP
++	 * aperture maps to physical bus or IOVA addressed.
++	 * AGP aperture is used to simulate FB in ZFB case.
++	 * AGP aperture is also used for page table in system
++	 * memory (mainly for APU).
++	 *
++	 */
+ 	u64			agp_size;
+ 	u64			agp_start;
+ 	u64			agp_end;
++	/* GART aperture start and end in MC address space
++	 * Driver find a hole in the MC address space
++	 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR
++	 * registers
++	 * Under VMID0, logical address inside GART aperture will
++	 * be translated through gpuvm gart page table to access
++	 * paged system memory
++	 */
+ 	u64			gart_size;
+ 	u64			gart_start;
+ 	u64			gart_end;
++	/* Frame buffer aperture of this GPU device. Different from
++	 * fb_start (see below), this only covers the local GPU device.
++	 * Driver get fb_start from MC_VM_FB_LOCATION_BASE (set by vbios)
++	 * and calculate vram_start of this local device by adding an
++	 * offset inside the XGMI hive.
++	 * Under VMID0, logical address == MC address
++	 */
+ 	u64			vram_start;
+ 	u64			vram_end;
+ 	/* FB region , it's same as local vram region in single GPU, in XGMI
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4382-drm-amd-include-Add-gfx10-debugger-registers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4382-drm-amd-include-Add-gfx10-debugger-registers.patch
new file mode 100644
index 00000000..f71d66ee
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4382-drm-amd-include-Add-gfx10-debugger-registers.patch
@@ -0,0 +1,148 @@
+From cc5c59647d0ced3f36d32ea1142806c376e3ab72 Mon Sep 17 00:00:00 2001
+From: Philip Cox <Philip.Cox@amd.com>
+Date: Wed, 16 Oct 2019 07:12:32 -0400
+Subject: [PATCH 4382/4736] drm/amd/include: Add gfx10 debugger registers
+
+Add kfd debugger registers:
+    mmSPI_GDBG_WAVE_CNTL
+    mmSPI_GDBG_TRAP_CONFIG
+    mmSPI_GDBG_TRAP_MASK
+    mmSPI_GDBG_WAVE_CNTL2
+    mmSPI_GDBG_WAVE_CNTL3
+    mmSPI_GDBG_TRAP_DATA0
+    mmSPI_GDBG_TRAP_DATA1
+
+Change-Id: Idd2f0260e6801cf1785c33c0667c4332320fcd2d
+Signed-off-by: Philip Cox <Philip.Cox@amd.com>
+---
+ .../include/asic_reg/gc/gc_10_1_0_default.h   |  7 ++
+ .../include/asic_reg/gc/gc_10_1_0_offset.h    | 14 ++++
+ .../include/asic_reg/gc/gc_10_1_0_sh_mask.h   | 69 +++++++++++++++++++
+ 3 files changed, 90 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h
+index 320e1ee5df1a..2050888f7ec6 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h
+@@ -2616,6 +2616,13 @@
+ #define mmSPI_WCL_PIPE_PERCENT_CS5_DEFAULT                                       0x0000007f
+ #define mmSPI_WCL_PIPE_PERCENT_CS6_DEFAULT                                       0x0000007f
+ #define mmSPI_WCL_PIPE_PERCENT_CS7_DEFAULT                                       0x0000007f
++#define mmSPI_GDBG_WAVE_CNTL_DEFAULT                                             0x00000000
++#define mmSPI_GDBG_TRAP_CONFIG_DEFAULT                                           0x00000000
++#define mmSPI_GDBG_TRAP_MASK_DEFAULT                                             0x00000000
++#define mmSPI_GDBG_WAVE_CNTL2_DEFAULT                                            0x00000000
++#define mmSPI_GDBG_WAVE_CNTL3_DEFAULT                                            0x00000000
++#define mmSPI_GDBG_TRAP_DATA0_DEFAULT                                            0x00000000
++#define mmSPI_GDBG_TRAP_DATA1_DEFAULT                                            0x00000000
+ #define mmSPI_COMPUTE_QUEUE_RESET_DEFAULT                                        0x00000000
+ #define mmSPI_RESOURCE_RESERVE_CU_0_DEFAULT                                      0x00000000
+ #define mmSPI_RESOURCE_RESERVE_CU_1_DEFAULT                                      0x00000000
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+index 075867d4b1da..7dd32b10d23f 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+@@ -5187,6 +5187,20 @@
+ #define mmSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX                                                            0
+ #define mmSPI_WCL_PIPE_PERCENT_CS7                                                                     0x1f70
+ #define mmSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX                                                            0
++#define mmSPI_GDBG_WAVE_CNTL                                                                           0x11d1
++#define mmSPI_GDBG_WAVE_CNTL_BASE_IDX                                                                  0
++#define mmSPI_GDBG_TRAP_CONFIG                                                                         0x11d2
++#define mmSPI_GDBG_TRAP_CONFIG_BASE_IDX                                                                0
++#define mmSPI_GDBG_TRAP_MASK                                                                           0x11d3
++#define mmSPI_GDBG_TRAP_MASK_BASE_IDX                                                                  0
++#define mmSPI_GDBG_WAVE_CNTL2                                                                          0x11d4
++#define mmSPI_GDBG_WAVE_CNTL2_BASE_IDX                                                                 0
++#define mmSPI_GDBG_WAVE_CNTL3                                                                          0x11d5
++#define mmSPI_GDBG_WAVE_CNTL3_BASE_IDX                                                                 0
++#define mmSPI_GDBG_TRAP_DATA0                                                                          0x11d8
++#define mmSPI_GDBG_TRAP_DATA0_BASE_IDX                                                                 0
++#define mmSPI_GDBG_TRAP_DATA1                                                                          0x11d9
++#define mmSPI_GDBG_TRAP_DATA1_BASE_IDX                                                                 0
+ #define mmSPI_COMPUTE_QUEUE_RESET                                                                      0x1f7b
+ #define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX                                                             0
+ #define mmSPI_RESOURCE_RESERVE_CU_0                                                                    0x1f7c
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
+index e7db6f9f9c86..c81cfa018738 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
+@@ -19642,6 +19642,75 @@
+ //SPI_WCL_PIPE_PERCENT_CS7
+ #define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT                                                                0x0
+ #define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK                                                                  0x7FL
++//SPI_GDBG_WAVE_CNTL
++#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT                                                                   0x0
++#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT                                                                 0x1
++#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK                                                                     0x00000001L
++#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK                                                                   0x0001FFFEL
++//SPI_GDBG_TRAP_CONFIG
++#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT                                                                   0x0
++#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT                                                                 0x2
++#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT                                                                0x4
++#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT                                                                 0x7
++#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT                                                               0x8
++#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT                                                              0x9
++#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT                                                                  0xf
++#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT                                                                 0x10
++#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK                                                                     0x00000003L
++#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK                                                                   0x0000000CL
++#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK                                                                  0x00000070L
++#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK                                                                   0x00000080L
++#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK                                                                 0x00000100L
++#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK                                                                0x00000200L
++#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK                                                                    0x00008000L
++#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK                                                                   0xFFFF0000L
++//SPI_GDBG_TRAP_MASK
++#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT                                                                    0x0
++#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT                                                                    0x9
++#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK                                                                      0x01FFL
++#define SPI_GDBG_TRAP_MASK__REPLACE_MASK                                                                      0x0200L
++//SPI_GDBG_WAVE_CNTL2
++#define SPI_GDBG_WAVE_CNTL2__VMID_MASK__SHIFT                                                                 0x0
++#define SPI_GDBG_WAVE_CNTL2__MODE__SHIFT                                                                      0x10
++#define SPI_GDBG_WAVE_CNTL2__VMID_MASK_MASK                                                                   0x0000FFFFL
++#define SPI_GDBG_WAVE_CNTL2__MODE_MASK                                                                        0x00030000L
++//SPI_GDBG_WAVE_CNTL3
++#define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT                                                                  0x0
++#define SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT                                                                  0x1
++#define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT                                                                  0x2
++#define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT                                                                  0x3
++#define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT                                                                 0x4
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT                                                                 0x5
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT                                                                 0x6
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT                                                                 0x7
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT                                                                 0x8
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT                                                                 0x9
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT                                                                 0xa
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT                                                                 0xb
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT                                                                 0xc
++#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT                                                            0xd
++#define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT                                                                0x1c
++#define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK                                                                    0x00000001L
++#define SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK                                                                    0x00000002L
++#define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK                                                                    0x00000004L
++#define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK                                                                    0x00000008L
++#define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK                                                                   0x00000010L
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK                                                                   0x00000020L
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK                                                                   0x00000040L
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK                                                                   0x00000080L
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK                                                                   0x00000100L
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK                                                                   0x00000200L
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK                                                                   0x00000400L
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK                                                                   0x00000800L
++#define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK                                                                   0x00001000L
++#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK                                                              0x0FFFE000L
++#define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK                                                                  0x10000000L
++//SPI_GDBG_TRAP_DATA0
++#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT                                                                      0x0
++#define SPI_GDBG_TRAP_DATA0__DATA_MASK                                                                        0xFFFFFFFFL
++//SPI_GDBG_TRAP_DATA1
++#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT                                                                      0x0
++#define SPI_GDBG_TRAP_DATA1__DATA_MASK                                                                        0xFFFFFFFFL
+ //SPI_COMPUTE_QUEUE_RESET
+ #define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT                                                                 0x0
+ #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK                                                                   0x01L
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4383-drm-amdkfd-Add-kfd-debugger-support-for-gfx10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4383-drm-amdkfd-Add-kfd-debugger-support-for-gfx10.patch
new file mode 100644
index 00000000..60c5babc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4383-drm-amdkfd-Add-kfd-debugger-support-for-gfx10.patch
@@ -0,0 +1,322 @@
+From 600b8f93502e13d7600caa9ae38edf398c42f566 Mon Sep 17 00:00:00 2001
+From: Philip Cox <Philip.Cox@amd.com>
+Date: Thu, 5 Sep 2019 09:08:57 -0400
+Subject: [PATCH 4383/4736] drm/amdkfd: Add kfd debugger support for gfx10
+
+Adding code to the gfx10 code path to support the kfd debugger
+functionality.
+
+Change-Id: Ifc822fa877ffdabb7b8e3ad167515aaaddbc6e98
+Signed-off-by: Philip Cox <Philip.Cox@amd.com>
+---
+ .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c    | 147 ++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c        |  16 ++
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c |  72 +++++++--
+ 3 files changed, 219 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+index 5eb289e887b3..d8fc3ba71628 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+@@ -813,6 +813,147 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
+ 	gfxhub_v2_0_setup_vm_pt_regs(adev, vmid, page_table_base);
+ }
+ 
++uint32_t kgd_gfx_v10_enable_debug_trap(struct kgd_dev *kgd,
++				uint32_t trap_debug_wave_launch_mode,
++				uint32_t vmid)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++	uint32_t data = 0;
++	uint32_t orig_wave_cntl_value;
++	uint32_t orig_stall_vmid;
++
++	mutex_lock(&adev->grbm_idx_mutex);
++
++	orig_wave_cntl_value = RREG32(SOC15_REG_OFFSET(GC,
++				0,
++				mmSPI_GDBG_WAVE_CNTL));
++	orig_stall_vmid = REG_GET_FIELD(orig_wave_cntl_value,
++			SPI_GDBG_WAVE_CNTL,
++			STALL_VMID);
++
++	data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_RA, 1);
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
++
++	data = 0;
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data);
++
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), orig_stall_vmid);
++
++	mutex_unlock(&adev->grbm_idx_mutex);
++
++	return 0;
++}
++
++uint32_t kgd_gfx_v10_disable_debug_trap(struct kgd_dev *kgd)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++
++	mutex_lock(&adev->grbm_idx_mutex);
++
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
++
++	mutex_unlock(&adev->grbm_idx_mutex);
++
++	return 0;
++}
++
++uint32_t kgd_gfx_v10_set_wave_launch_trap_override(struct kgd_dev *kgd,
++						uint32_t trap_override,
++						uint32_t trap_mask)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++	uint32_t data = 0;
++
++	mutex_lock(&adev->grbm_idx_mutex);
++
++	data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
++	data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_RA, 1);
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
++
++	data = 0;
++	data = REG_SET_FIELD(data, SPI_GDBG_TRAP_MASK,
++			EXCP_EN, trap_mask);
++	data = REG_SET_FIELD(data, SPI_GDBG_TRAP_MASK,
++			REPLACE, trap_override);
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data);
++
++	data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
++	data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_RA, 0);
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
++
++	mutex_unlock(&adev->grbm_idx_mutex);
++
++	return 0;
++}
++
++uint32_t kgd_gfx_v10_set_wave_launch_mode(struct kgd_dev *kgd,
++					uint8_t wave_launch_mode,
++					uint32_t vmid)
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++	uint32_t data = 0;
++	bool is_stall_mode;
++	bool is_mode_set;
++
++	is_stall_mode = (wave_launch_mode == 4);
++	is_mode_set = (wave_launch_mode != 0 && wave_launch_mode != 4);
++
++	mutex_lock(&adev->grbm_idx_mutex);
++
++	data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL2,
++			VMID_MASK, is_mode_set ? 1 << vmid : 0);
++	data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL2,
++			MODE, is_mode_set ? wave_launch_mode : 0);
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL2), data);
++
++	data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
++	data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL,
++			STALL_VMID, is_stall_mode ? 1 << vmid : 0);
++	data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL,
++			STALL_RA, is_stall_mode ? 1 : 0);
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
++
++	mutex_unlock(&adev->grbm_idx_mutex);
++
++	return 0;
++}
++
++/* kgd_get_iq_wait_times: Returns the mmCP_IQ_WAIT_TIME1/2 values
++ * The values read are:
++ *	ib_offload_wait_time     -- Wait Count for Indirect Buffer Offloads.
++ *	atomic_offload_wait_time -- Wait Count for L2 and GDS Atomics Offloads.
++ *	wrm_offload_wait_time    -- Wait Count for WAIT_REG_MEM Offloads.
++ *	gws_wait_time            -- Wait Count for Global Wave Syncs.
++ *	que_sleep_wait_time      -- Wait Count for Dequeue Retry.
++ *	sch_wave_wait_time       -- Wait Count for Scheduling Wave Message.
++ *	sem_rearm_wait_time      -- Wait Count for Semaphore re-arm.
++ *	deq_retry_wait_time      -- Wait Count for Global Wave Syncs.
++ */
++void kgd_gfx_v10_get_iq_wait_times(struct kgd_dev *kgd,
++					uint32_t *wait_times)
++
++{
++	struct amdgpu_device *adev = get_amdgpu_device(kgd);
++
++	*wait_times = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2));
++}
++
++void kgd_gfx_v10_build_grace_period_packet_info(struct kgd_dev *kgd,
++						uint32_t wait_times,
++						uint32_t grace_period,
++						uint32_t *reg_offset,
++						uint32_t *reg_data)
++{
++	*reg_data = wait_times;
++
++	*reg_data = REG_SET_FIELD(*reg_data,
++			CP_IQ_WAIT_TIME2,
++			SCH_WAVE,
++			grace_period);
++
++	*reg_offset = mmCP_IQ_WAIT_TIME2;
++}
++
+ const struct kfd2kgd_calls gfx_v10_kfd2kgd = {
+ 	.program_sh_mem_settings = kgd_program_sh_mem_settings,
+ 	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
+@@ -836,4 +977,10 @@ const struct kfd2kgd_calls gfx_v10_kfd2kgd = {
+ 	.invalidate_tlbs = invalidate_tlbs,
+ 	.invalidate_tlbs_vmid = invalidate_tlbs_vmid,
+ 	.get_hive_id = amdgpu_amdkfd_get_hive_id,
++	.enable_debug_trap = kgd_gfx_v10_enable_debug_trap,
++	.disable_debug_trap = kgd_gfx_v10_disable_debug_trap,
++	.set_wave_launch_trap_override = kgd_gfx_v10_set_wave_launch_trap_override,
++	.set_wave_launch_mode = kgd_gfx_v10_set_wave_launch_mode,
++	.get_iq_wait_times = kgd_gfx_v10_get_iq_wait_times,
++	.build_grace_period_packet_info = kgd_gfx_v10_build_grace_period_packet_info,
+ };
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index c7a6f98bf6b8..e4b4f4b09329 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1597,6 +1597,8 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
+ {
+ 	int i;
+ 	uint32_t sh_mem_bases;
++	uint32_t trap_config_vmid_mask = 0;
++	uint32_t data;
+ 
+ 	/*
+ 	 * Configure apertures:
+@@ -1612,9 +1614,23 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
+ 		/* CP and shaders */
+ 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
+ 		WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
++
++		/* Calculate trap config vmid mask */
++		trap_config_vmid_mask |= (1 << i);
+ 	}
+ 	nv_grbm_select(adev, 0, 0, 0, 0);
+ 	mutex_unlock(&adev->srbm_mutex);
++
++	data = 0;
++	data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
++			VMID_SEL, trap_config_vmid_mask);
++	data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
++			TRAP_EN, 1);
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
++
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
++	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
+ }
+ 
+ static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
+index efc6c37ec37e..7a695b9a2bcd 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
+@@ -73,6 +73,7 @@ static int pm_map_process_v10(struct packet_manager *pm,
+ {
+ 	struct pm4_mes_map_process *packet;
+ 	uint64_t vm_page_table_base_addr = qpd->page_table_base;
++	struct kfd_dev *kfd = pm->dqm->dev;
+ 
+ 	packet = (struct pm4_mes_map_process *)buffer;
+ 	memset(buffer, 0, sizeof(struct pm4_mes_map_process));
+@@ -89,6 +90,11 @@ static int pm_map_process_v10(struct packet_manager *pm,
+ 
+ 	packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
+ 
++	if (kfd->dqm->trap_debug_vmid) {
++		packet->bitfields2.debug_vmid = kfd->dqm->trap_debug_vmid;
++		packet->bitfields2.new_debug = 1;
++	}
++
+ 	packet->sh_mem_config = qpd->sh_mem_config;
+ 	packet->sh_mem_bases = qpd->sh_mem_bases;
+ 	if (qpd->tba_addr) {
+@@ -206,6 +212,40 @@ static int pm_map_queues_v10(struct packet_manager *pm, uint32_t *buffer,
+ 	return 0;
+ }
+ 
++static int pm_set_grace_period_v10(struct packet_manager *pm,
++					uint32_t *buffer,
++					uint32_t grace_period)
++{
++	struct pm4_mec_write_data_mmio *packet;
++	uint32_t reg_offset = 0;
++	uint32_t reg_data = 0;
++
++	pm->dqm->dev->kfd2kgd->build_grace_period_packet_info(
++			pm->dqm->dev->kgd,
++			pm->dqm->wait_times,
++			grace_period,
++			&reg_offset,
++			&reg_data);
++
++	if (grace_period == USE_DEFAULT_GRACE_PERIOD)
++		reg_data = pm->dqm->wait_times;
++
++	packet = (struct pm4_mec_write_data_mmio *)buffer;
++	memset(buffer, 0, sizeof(struct pm4_mec_write_data_mmio));
++
++	packet->header.u32All = pm_build_pm4_header(IT_WRITE_DATA,
++			sizeof(struct pm4_mec_write_data_mmio));
++
++	packet->bitfields2.dst_sel  = dst_sel___write_data__mem_mapped_register;
++	packet->bitfields2.addr_incr =
++		addr_incr___write_data__do_not_increment_address;
++
++	packet->bitfields3.dst_mmreg_addr = reg_offset;
++
++	packet->data = reg_data;
++
++	return 0;
++}
+ static int pm_unmap_queues_v10(struct packet_manager *pm, uint32_t *buffer,
+ 			enum kfd_queue_type type,
+ 			enum kfd_unmap_queues_filter filter,
+@@ -330,21 +370,21 @@ static int pm_release_mem_v10(uint64_t gpu_addr, uint32_t *buffer)
+ }
+ 
+ const struct packet_manager_funcs kfd_v10_pm_funcs = {
+-	.map_process			= pm_map_process_v10,
+-	.runlist			= pm_runlist_v10,
+-	.set_resources			= pm_set_resources_vi,
+-	.map_queues			= pm_map_queues_v10,
+-	.unmap_queues			= pm_unmap_queues_v10,
+-	.set_grace_period       = NULL,
+-	.query_status			= pm_query_status_v10,
+-	.release_mem			= pm_release_mem_v10,
+-	.map_process_size		= sizeof(struct pm4_mes_map_process),
+-	.runlist_size			= sizeof(struct pm4_mes_runlist),
+-	.set_resources_size		= sizeof(struct pm4_mes_set_resources),
+-	.map_queues_size		= sizeof(struct pm4_mes_map_queues),
+-	.unmap_queues_size		= sizeof(struct pm4_mes_unmap_queues),
+-	.set_grace_period_size  = 0,
+-	.query_status_size		= sizeof(struct pm4_mes_query_status),
+-	.release_mem_size		= sizeof(struct pm4_mec_release_mem)
++	.map_process		= pm_map_process_v10,
++	.runlist		= pm_runlist_v10,
++	.set_resources		= pm_set_resources_vi,
++	.map_queues		= pm_map_queues_v10,
++	.unmap_queues		= pm_unmap_queues_v10,
++	.set_grace_period	= pm_set_grace_period_v10,
++	.query_status		= pm_query_status_v10,
++	.release_mem		= pm_release_mem_v10,
++	.map_process_size	= sizeof(struct pm4_mes_map_process),
++	.runlist_size		= sizeof(struct pm4_mes_runlist),
++	.set_resources_size	= sizeof(struct pm4_mes_set_resources),
++	.map_queues_size	= sizeof(struct pm4_mes_map_queues),
++	.unmap_queues_size	= sizeof(struct pm4_mes_unmap_queues),
++	.set_grace_period_size	= sizeof(struct pm4_mec_write_data_mmio),
++	.query_status_size	= sizeof(struct pm4_mes_query_status),
++	.release_mem_size	= sizeof(struct pm4_mec_release_mem)
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4384-drm-amdgpu-Need-to-disable-msix-when-unloading-drive.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4384-drm-amdgpu-Need-to-disable-msix-when-unloading-drive.patch
new file mode 100644
index 00000000..cee2d210
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4384-drm-amdgpu-Need-to-disable-msix-when-unloading-drive.patch
@@ -0,0 +1,32 @@
+From 744eb07f86356f4d3efc1a87c71742de310f35c0 Mon Sep 17 00:00:00 2001
+From: Emily Deng <Emily.Deng@amd.com>
+Date: Thu, 7 Nov 2019 10:26:43 +0800
+Subject: [PATCH 4384/4736] drm/amdgpu: Need to disable msix when unloading
+ driver
+
+For driver reload test, it will report "can't enable
+MSI (MSI-X already enabled)".
+
+Change-Id: I939294f06c74a6bb998ce3c7bb55d1d4e8555faf
+Signed-off-by: Emily Deng <Emily.Deng@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+index 22edda8ad261..931c9744937a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+@@ -308,7 +308,7 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
+ 		drm_irq_uninstall(adev->ddev);
+ 		adev->irq.installed = false;
+ 		if (adev->irq.msi_enabled)
+-			pci_disable_msi(adev->pdev);
++			pci_free_irq_vectors(adev->pdev);
+ 		if (!amdgpu_device_has_dc_support(adev))
+ 			flush_work(&adev->hotplug_work);
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4385-drm-amdgpu-fix-sysfs-interface-pcie_replay_count-err.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4385-drm-amdgpu-fix-sysfs-interface-pcie_replay_count-err.patch
new file mode 100644
index 00000000..f6b6ff49
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4385-drm-amdgpu-fix-sysfs-interface-pcie_replay_count-err.patch
@@ -0,0 +1,47 @@
+From 6f110828854e327b49da8fd84846facc3d2e87f8 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Tue, 5 Nov 2019 18:53:30 +0800
+Subject: [PATCH 4385/4736] drm/amdgpu: fix sysfs interface pcie_replay_count
+ error on navi asic
+
+the asic callback function of get_pcie_replay_count is not implement on navi asic,
+it will cause null pinter error when read this interface.
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Kent Russell <kent.russell@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 88e3665f7b09..b33da33214eb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -538,6 +538,16 @@ static bool nv_need_reset_on_init(struct amdgpu_device *adev)
+ 	return false;
+ }
+ 
++static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
++{
++
++	/* TODO
++	 * dummy implement for pcie_replay_count sysfs interface
++	 * */
++
++	return 0;
++}
++
+ static void nv_init_doorbell_index(struct amdgpu_device *adev)
+ {
+ 	adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
+@@ -585,6 +595,7 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
+ 	.need_full_reset = &nv_need_full_reset,
+ 	.get_pcie_usage = &nv_get_pcie_usage,
+ 	.need_reset_on_init = &nv_need_reset_on_init,
++	.get_pcie_replay_count = &nv_get_pcie_replay_count,
+ };
+ 
+ static int nv_common_early_init(void *handle)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4386-Revert-drm-amdgpu-Need-to-disable-msix-when-unloadin.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4386-Revert-drm-amdgpu-Need-to-disable-msix-when-unloadin.patch
new file mode 100644
index 00000000..401f25ef
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4386-Revert-drm-amdgpu-Need-to-disable-msix-when-unloadin.patch
@@ -0,0 +1,29 @@
+From 946c7cdb630ad0e8ab58ac963419c42b27ad2b77 Mon Sep 17 00:00:00 2001
+From: "Stanley.Yang" <Stanley.Yang@amd.com>
+Date: Thu, 7 Nov 2019 17:47:47 +0800
+Subject: [PATCH 4386/4736] Revert "drm/amdgpu: Need to disable msix when
+ unloading driver"
+
+This reverts commit 18bd755c29f993a0b206bbe084aadace5c8a1ad3.
+
+Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+index 931c9744937a..22edda8ad261 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+@@ -308,7 +308,7 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
+ 		drm_irq_uninstall(adev->ddev);
+ 		adev->irq.installed = false;
+ 		if (adev->irq.msi_enabled)
+-			pci_free_irq_vectors(adev->pdev);
++			pci_disable_msi(adev->pdev);
+ 		if (!amdgpu_device_has_dc_support(adev))
+ 			flush_work(&adev->hotplug_work);
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4387-SWDEV-210749-drm-amdgpu-Need-to-disable-msix-when-un.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4387-SWDEV-210749-drm-amdgpu-Need-to-disable-msix-when-un.patch
new file mode 100644
index 00000000..d29d88a6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4387-SWDEV-210749-drm-amdgpu-Need-to-disable-msix-when-un.patch
@@ -0,0 +1,34 @@
+From 36073510926d28de485708510ca5574fc8df0d09 Mon Sep 17 00:00:00 2001
+From: Emily Deng <Emily.Deng@amd.com>
+Date: Wed, 6 Nov 2019 16:20:54 +0800
+Subject: [PATCH 4387/4736] SWDEV-210749 drm/amdgpu: Need to disable msix when
+ unloading driver
+
+For driver reload test, it will report "can't enable
+MSI (MSI-X already enabled)".
+
+Change-Id: Id98a33e8404d8d803f20d9694f2f04a6e5251fb7
+Signed-off-by: Emily Deng <Emily.Deng@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+index 22edda8ad261..48af4830a74f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+@@ -308,7 +308,11 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
+ 		drm_irq_uninstall(adev->ddev);
+ 		adev->irq.installed = false;
+ 		if (adev->irq.msi_enabled)
++#ifdef PCI_IRQ_MSI
++			pci_free_irq_vectors(adev->pdev);
++#else
+ 			pci_disable_msi(adev->pdev);
++#endif
+ 		if (!amdgpu_device_has_dc_support(adev))
+ 			flush_work(&adev->hotplug_work);
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4388-drm-amdgpu-allow-direct-upload-save-restore-list-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4388-drm-amdgpu-allow-direct-upload-save-restore-list-for.patch
new file mode 100644
index 00000000..5acb9b86
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4388-drm-amdgpu-allow-direct-upload-save-restore-list-for.patch
@@ -0,0 +1,36 @@
+From 333f6da2575dc2c88bf5355e4dd4038c997e445d Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Thu, 7 Nov 2019 14:09:27 +0800
+Subject: [PATCH 4388/4736] drm/amdgpu: allow direct upload save restore list
+ for raven2
+
+It will cause modprobe atombios stuck problem in raven2 if it doesn't
+allow direct upload save restore list from gfx driver.
+So it needs to allow direct upload save restore list for raven2
+temporarily.
+
+Change-Id: I1fece1b9c61f7a13eec948f34eb60a9120046bc2
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index b7ce3217fcf8..79cc4b95423b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -2741,7 +2741,9 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
+ 	 * And it's needed by gfxoff feature.
+ 	 */
+ 	if (adev->gfx.rlc.is_rlc_v2_1) {
+-		if (adev->asic_type == CHIP_VEGA12)
++		if (adev->asic_type == CHIP_VEGA12 ||
++		    (adev->asic_type == CHIP_RAVEN &&
++		     adev->rev_id >= 8))
+ 			gfx_v9_1_init_rlc_save_restore_list(adev);
+ 		gfx_v9_0_enable_save_restore_machine(adev);
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4389-drm-amd-amdgpu-finish-delay-works-before-release-res.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4389-drm-amd-amdgpu-finish-delay-works-before-release-res.patch
new file mode 100644
index 00000000..2e6ac402
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4389-drm-amd-amdgpu-finish-delay-works-before-release-res.patch
@@ -0,0 +1,62 @@
+From 54629ccae746e54a45eb3ab21782716af37ea1b1 Mon Sep 17 00:00:00 2001
+From: Jesse Zhang <zhexi.zhang@amd.com>
+Date: Fri, 8 Nov 2019 18:06:07 +0800
+Subject: [PATCH 4389/4736] drm/amd/amdgpu: finish delay works before release
+ resources
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+flush/cancel delayed works before doing finalization
+to avoid concurrently requests.
+
+Change-Id: I85b7ffbb34875af1c734cb4573a6ecc71d39d652
+Signed-off-by: Jesse Zhang <zhexi.zhang@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c    | 1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c    | 1 +
+ 3 files changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 09ef0eaf1abc..8bfbcbcb7f2e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3118,6 +3118,9 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
+ 
+ 	DRM_INFO("amdgpu: finishing device.\n");
+ 	adev->shutdown = true;
++
++	flush_delayed_work(&adev->delayed_init_work);
++
+ 	/* disable all interrupts */
+ 	amdgpu_irq_disable_all(adev);
+ 	if (adev->mode_info.mode_config_initialized){
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+index d1b10b5583ec..32128e982e4c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+@@ -299,6 +299,7 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
+ {
+ 	int i, j;
+ 
++	cancel_delayed_work_sync(&adev->uvd.idle_work);
+ 	drm_sched_entity_destroy(&adev->uvd.entity);
+ 
+ 	for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+index 92aa3b1b34ce..f70b55f9d904 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+@@ -216,6 +216,7 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
+ 	if (adev->vce.vcpu_bo == NULL)
+ 		return 0;
+ 
++	cancel_delayed_work_sync(&adev->vce.idle_work);
+ 	drm_sched_entity_destroy(&adev->vce.entity);
+ 
+ 	amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, &adev->vce.gpu_addr,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4390-drm-amdgpu-fix-vega20-pstate-status-change.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4390-drm-amdgpu-fix-vega20-pstate-status-change.patch
new file mode 100644
index 00000000..712100ee
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4390-drm-amdgpu-fix-vega20-pstate-status-change.patch
@@ -0,0 +1,50 @@
+From 99e982dad30772ca6c977f5c5bc2e2ba6f89fb04 Mon Sep 17 00:00:00 2001
+From: Jonathan Kim <jonathan.kim@amd.com>
+Date: Wed, 6 Nov 2019 08:20:21 -0500
+Subject: [PATCH 4390/4736] drm/amdgpu: fix vega20 pstate status change
+
+vega20 only requires all devices be set to same pstate level for low
+pstate and not high.
+
+Change-Id: I399c84a47f6e24abca937ce950685c0c7f0e3279
+Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
+Reviewed-by: Evan Quan <Evan.Quan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+index e58bad7f64c6..6c6893b94114 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+@@ -276,6 +276,7 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
+ 	struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
+ 	struct amdgpu_device *tmp_adev;
+ 	bool update_hive_pstate = true;
++	bool is_high_pstate = pstate && adev->asic_type == CHIP_VEGA20;
+ 
+ 	if (!hive)
+ 		return 0;
+@@ -283,8 +284,8 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
+ 	mutex_lock(&hive->hive_lock);
+ 
+ 	if (hive->pstate == pstate) {
+-		mutex_unlock(&hive->hive_lock);
+-		return 0;
++		adev->pstate = is_high_pstate ? pstate : adev->pstate;
++		goto out;
+ 	}
+ 
+ 	dev_dbg(adev->dev, "Set xgmi pstate %d.\n", pstate);
+@@ -317,7 +318,7 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
+ 			break;
+ 		}
+ 	}
+-	if (update_hive_pstate)
++	if (update_hive_pstate || is_high_pstate)
+ 		hive->pstate = pstate;
+ 
+ out:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4391-drm-sched-Use-completion-to-wait-for-sched-thread-id.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4391-drm-sched-Use-completion-to-wait-for-sched-thread-id.patch
new file mode 100644
index 00000000..59b768c9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4391-drm-sched-Use-completion-to-wait-for-sched-thread-id.patch
@@ -0,0 +1,133 @@
+From f9cb85904d432a3edfa96931060e86ed1c06c741 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Mon, 4 Nov 2019 16:30:05 -0500
+Subject: [PATCH 4391/4736] drm/sched: Use completion to wait for sched->thread
+ idle v2.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Removes thread park/unpark hack from drm_sched_entity_fini and
+by this fixes reactivation of scheduler thread while the thread
+is supposed to be stopped.
+
+v2: Per sched entity completion.
+
+Change-Id: I9d1eca2ddcfaf3c1e4ed455e02358a0a396d822d
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Suggested-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/scheduler/sched_entity.c | 12 ++++++++----
+ drivers/gpu/drm/scheduler/sched_main.c   |  6 ++++++
+ include/drm/gpu_scheduler.h              |  3 +++
+ 3 files changed, 17 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c
+index 671c90f34ede..797e8ba9bafb 100644
+--- a/drivers/gpu/drm/scheduler/sched_entity.c
++++ b/drivers/gpu/drm/scheduler/sched_entity.c
+@@ -22,6 +22,7 @@
+  */
+ 
+ #include <linux/kthread.h>
++#include <linux/completion.h>
+ #include <drm/gpu_scheduler.h>
+ 
+ #include "gpu_scheduler_trace.h"
+@@ -65,6 +66,8 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
+ 	if (!entity->rq_list)
+ 		return -ENOMEM;
+ 
++	init_completion(&entity->entity_idle);
++
+ 	for (i = 0; i < num_rq_list; ++i)
+ 		entity->rq_list[i] = rq_list[i];
+ 
+@@ -283,11 +286,12 @@ void drm_sched_entity_fini(struct drm_sched_entity *entity)
+ 	 */
+ 	if (spsc_queue_count(&entity->job_queue)) {
+ 		if (sched) {
+-			/* Park the kernel for a moment to make sure it isn't processing
+-			 * our enity.
++			/*
++			 * Wait for thread to idle to make sure it isn't processing
++			 * this entity.
+ 			 */
+-			kthread_park(sched->thread);
+-			kthread_unpark(sched->thread);
++			wait_for_completion(&entity->entity_idle);
++
+ 		}
+ 		if (entity->dependency) {
+ 			dma_fence_remove_callback(entity->dependency,
+diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c
+index 007abab5dae6..108bac88dedb 100644
+--- a/drivers/gpu/drm/scheduler/sched_main.c
++++ b/drivers/gpu/drm/scheduler/sched_main.c
+@@ -47,6 +47,7 @@
+ #include <linux/kthread.h>
+ #include <linux/wait.h>
+ #include <linux/sched.h>
++#include <linux/completion.h>
+ #include <uapi/linux/sched/types.h>
+ #include <drm/drmP.h>
+ #include <drm/gpu_scheduler.h>
+@@ -135,6 +136,7 @@ drm_sched_rq_select_entity(struct drm_sched_rq *rq)
+ 		list_for_each_entry_continue(entity, &rq->entities, list) {
+ 			if (drm_sched_entity_is_ready(entity)) {
+ 				rq->current_entity = entity;
++				reinit_completion(&entity->entity_idle);
+ 				spin_unlock(&rq->lock);
+ 				return entity;
+ 			}
+@@ -145,6 +147,7 @@ drm_sched_rq_select_entity(struct drm_sched_rq *rq)
+ 
+ 		if (drm_sched_entity_is_ready(entity)) {
+ 			rq->current_entity = entity;
++			reinit_completion(&entity->entity_idle);
+ 			spin_unlock(&rq->lock);
+ 			return entity;
+ 		}
+@@ -721,6 +724,9 @@ static int drm_sched_main(void *param)
+ 			continue;
+ 
+ 		sched_job = drm_sched_entity_pop_job(entity);
++
++		complete(&entity->entity_idle);
++
+ 		if (!sched_job)
+ 			continue;
+ 
+diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
+index 4d877441145e..3dca3c8bced6 100644
+--- a/include/drm/gpu_scheduler.h
++++ b/include/drm/gpu_scheduler.h
+@@ -26,6 +26,7 @@
+ 
+ #include <drm/spsc_queue.h>
+ #include <linux/dma-fence.h>
++#include <linux/completion.h>
+ 
+ #define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000)
+ 
+@@ -68,6 +69,7 @@ enum drm_sched_priority {
+  * @last_scheduled: points to the finished fence of the last scheduled job.
+  * @last_user: last group leader pushing a job into the entity.
+  * @stopped: Marks the enity as removed from rq and destined for termination.
++ * @entity_idle: Signals when enityt is not in use
+  *
+  * Entities will emit jobs in order to their corresponding hardware
+  * ring, and the scheduler will alternate between entities based on
+@@ -91,6 +93,7 @@ struct drm_sched_entity {
+ 	struct dma_fence                *last_scheduled;
+ 	struct task_struct		*last_user;
+ 	bool 				stopped;
++	struct completion		entity_idle;
+ };
+ 
+ /**
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4392-drm-amdgpu-Avoid-accidental-thread-thread-reactivati.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4392-drm-amdgpu-Avoid-accidental-thread-thread-reactivati.patch
new file mode 100644
index 00000000..1ecb69e6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4392-drm-amdgpu-Avoid-accidental-thread-thread-reactivati.patch
@@ -0,0 +1,70 @@
+From ebe29fddda96d8c4cde06852ea93e34b4c03ceed Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Wed, 6 Nov 2019 12:36:29 -0500
+Subject: [PATCH 4392/4736] drm/amdgpu: Avoid accidental thread thread
+ reactivation.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Problem:
+During GPU reset we call the GPU scheduler to suspend it's
+thread, those two functions in amdgpu also suspend and resume
+the sceduler for their needs but this can collide with GPU
+reset in progress and accidently restart a suspended thread
+before time.
+
+Fix:
+Serialize with GPU reset.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+index 996cb998dc1f..f448b45ad802 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+@@ -856,6 +856,9 @@ static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
+ 	struct amdgpu_device *adev = dev->dev_private;
+ 	int r = 0, i;
+ 
++	/* Avoid accidently unparking the sched thread during GPU reset */
++	mutex_lock(&adev->lock_reset);
++
+ 	/* hold on the scheduler */
+ 	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
+ 		struct amdgpu_ring *ring = adev->rings[i];
+@@ -881,6 +884,8 @@ static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
+ 		kthread_unpark(ring->sched.thread);
+ 	}
+ 
++	mutex_unlock(&adev->lock_reset);
++
+ 	return 0;
+ }
+ 
+@@ -1033,6 +1038,9 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
+ 	if (!fences)
+ 		return -ENOMEM;
+ 
++	/* Avoid accidently unparking the sched thread during GPU reset */
++	mutex_lock(&adev->lock_reset);
++
+ 	/* stop the scheduler */
+ 	kthread_park(ring->sched.thread);
+ 
+@@ -1072,6 +1080,8 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
+ 	/* restart the scheduler */
+ 	kthread_unpark(ring->sched.thread);
+ 
++	mutex_unlock(&adev->lock_reset);
++
+ 	ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
+ 
+ 	kfree(fences);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4393-drm-amdkfd-Adjust-function-sequences-to-avoid-unnece.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4393-drm-amdkfd-Adjust-function-sequences-to-avoid-unnece.patch
new file mode 100644
index 00000000..f6da318e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4393-drm-amdkfd-Adjust-function-sequences-to-avoid-unnece.patch
@@ -0,0 +1,55 @@
+From b3fe14e57b9058a079e5b8314a8411a1fcdb7f35 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 30 Oct 2019 18:07:20 -0400
+Subject: [PATCH 4393/4736] drm/amdkfd: Adjust function sequences to avoid
+ unnecessary declarations
+
+This is cleaner.
+
+Change-Id: I8cdecad387d8c547a088c6050f77385ee1135be1
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c  | 19 +++++++------------
+ 1 file changed, 7 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+index f7d9dac26485..b5c077b50d1a 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+@@ -26,18 +26,6 @@
+ #include "kfd_pm4_headers_ai.h"
+ #include "kfd_pm4_opcodes.h"
+ 
+-static bool initialize_v9(struct kernel_queue *kq, struct kfd_dev *dev,
+-			enum kfd_queue_type type, unsigned int queue_size);
+-static void uninitialize_v9(struct kernel_queue *kq);
+-static void submit_packet_v9(struct kernel_queue *kq);
+-
+-void kernel_queue_init_v9(struct kernel_queue_ops *ops)
+-{
+-	ops->initialize = initialize_v9;
+-	ops->uninitialize = uninitialize_v9;
+-	ops->submit_packet = submit_packet_v9;
+-}
+-
+ static bool initialize_v9(struct kernel_queue *kq, struct kfd_dev *dev,
+ 			enum kfd_queue_type type, unsigned int queue_size)
+ {
+@@ -67,6 +55,13 @@ static void submit_packet_v9(struct kernel_queue *kq)
+ 				kq->pending_wptr64);
+ }
+ 
++void kernel_queue_init_v9(struct kernel_queue_ops *ops)
++{
++	ops->initialize = initialize_v9;
++	ops->uninitialize = uninitialize_v9;
++	ops->submit_packet = submit_packet_v9;
++}
++
+ static int pm_map_process_v9(struct packet_manager *pm,
+ 		uint32_t *buffer, struct qcm_process_device *qpd)
+ {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4394-drm-amdkfd-Only-keep-release_mem-function-for-Hawaii.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4394-drm-amdkfd-Only-keep-release_mem-function-for-Hawaii.patch
new file mode 100644
index 00000000..5b31dfde
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4394-drm-amdkfd-Only-keep-release_mem-function-for-Hawaii.patch
@@ -0,0 +1,136 @@
+From ac6b4c83d151966d129fd5eea92087da0d02702b Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 30 Oct 2019 19:22:11 -0400
+Subject: [PATCH 4394/4736] drm/amdkfd: Only keep release_mem function for
+ Hawaii
+
+release_mem is only used for Hawaii, but because GFX7 and GFX8 share the
+same function pointer structure, so we only delete release_mem for GFX9
+and GFX10.
+
+Change-Id: I13787a8a29b83e7516c582a7401f2e14721edf5f
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c | 35 ++-----------------
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c  | 33 ++---------------
+ 2 files changed, 4 insertions(+), 64 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
+index 7a695b9a2bcd..5ee593ba3137 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
+@@ -338,37 +338,6 @@ static int pm_query_status_v10(struct packet_manager *pm, uint32_t *buffer,
+ 	return 0;
+ }
+ 
+-
+-static int pm_release_mem_v10(uint64_t gpu_addr, uint32_t *buffer)
+-{
+-	struct pm4_mec_release_mem *packet;
+-
+-	WARN_ON(!buffer);
+-
+-	packet = (struct pm4_mec_release_mem *)buffer;
+-	memset(buffer, 0, sizeof(struct pm4_mec_release_mem));
+-
+-	packet->header.u32All = pm_build_pm4_header(IT_RELEASE_MEM,
+-					sizeof(struct pm4_mec_release_mem));
+-
+-	packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT;
+-	packet->bitfields2.event_index = event_index__mec_release_mem__end_of_pipe;
+-	packet->bitfields2.tcl1_action_ena = 1;
+-	packet->bitfields2.tc_action_ena = 1;
+-	packet->bitfields2.cache_policy = cache_policy__mec_release_mem__lru;
+-
+-	packet->bitfields3.data_sel = data_sel__mec_release_mem__send_32_bit_low;
+-	packet->bitfields3.int_sel =
+-		int_sel__mec_release_mem__send_interrupt_after_write_confirm;
+-
+-	packet->bitfields4.address_lo_32b = (gpu_addr & 0xffffffff) >> 2;
+-	packet->address_hi = upper_32_bits(gpu_addr);
+-
+-	packet->data_lo = 0;
+-
+-	return sizeof(struct pm4_mec_release_mem) / sizeof(unsigned int);
+-}
+-
+ const struct packet_manager_funcs kfd_v10_pm_funcs = {
+ 	.map_process		= pm_map_process_v10,
+ 	.runlist		= pm_runlist_v10,
+@@ -377,7 +346,7 @@ const struct packet_manager_funcs kfd_v10_pm_funcs = {
+ 	.unmap_queues		= pm_unmap_queues_v10,
+ 	.set_grace_period	= pm_set_grace_period_v10,
+ 	.query_status		= pm_query_status_v10,
+-	.release_mem		= pm_release_mem_v10,
++	.release_mem		= NULL,
+ 	.map_process_size	= sizeof(struct pm4_mes_map_process),
+ 	.runlist_size		= sizeof(struct pm4_mes_runlist),
+ 	.set_resources_size	= sizeof(struct pm4_mes_set_resources),
+@@ -385,6 +354,6 @@ const struct packet_manager_funcs kfd_v10_pm_funcs = {
+ 	.unmap_queues_size	= sizeof(struct pm4_mes_unmap_queues),
+ 	.set_grace_period_size	= sizeof(struct pm4_mec_write_data_mmio),
+ 	.query_status_size	= sizeof(struct pm4_mes_query_status),
+-	.release_mem_size	= sizeof(struct pm4_mec_release_mem)
++	.release_mem_size	= 0,
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+index b5c077b50d1a..42aefc976838 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+@@ -377,35 +377,6 @@ static int pm_query_status_v9(struct packet_manager *pm, uint32_t *buffer,
+ 	return 0;
+ }
+ 
+-
+-static int pm_release_mem_v9(uint64_t gpu_addr, uint32_t *buffer)
+-{
+-	struct pm4_mec_release_mem *packet;
+-
+-	packet = (struct pm4_mec_release_mem *)buffer;
+-	memset(buffer, 0, sizeof(struct pm4_mec_release_mem));
+-
+-	packet->header.u32All = pm_build_pm4_header(IT_RELEASE_MEM,
+-					sizeof(struct pm4_mec_release_mem));
+-
+-	packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT;
+-	packet->bitfields2.event_index = event_index__mec_release_mem__end_of_pipe;
+-	packet->bitfields2.tcl1_action_ena = 1;
+-	packet->bitfields2.tc_action_ena = 1;
+-	packet->bitfields2.cache_policy = cache_policy__mec_release_mem__lru;
+-
+-	packet->bitfields3.data_sel = data_sel__mec_release_mem__send_32_bit_low;
+-	packet->bitfields3.int_sel =
+-		int_sel__mec_release_mem__send_interrupt_after_write_confirm;
+-
+-	packet->bitfields4.address_lo_32b = (gpu_addr & 0xffffffff) >> 2;
+-	packet->address_hi = upper_32_bits(gpu_addr);
+-
+-	packet->data_lo = 0;
+-
+-	return 0;
+-}
+-
+ const struct packet_manager_funcs kfd_v9_pm_funcs = {
+ 	.map_process		= pm_map_process_v9,
+ 	.runlist		= pm_runlist_v9,
+@@ -414,7 +385,7 @@ const struct packet_manager_funcs kfd_v9_pm_funcs = {
+ 	.unmap_queues		= pm_unmap_queues_v9,
+ 	.set_grace_period       = pm_set_grace_period_v9,
+ 	.query_status		= pm_query_status_v9,
+-	.release_mem		= pm_release_mem_v9,
++	.release_mem		= NULL,
+ 	.map_process_size	= sizeof(struct pm4_mes_map_process),
+ 	.runlist_size		= sizeof(struct pm4_mes_runlist),
+ 	.set_resources_size	= sizeof(struct pm4_mes_set_resources),
+@@ -422,5 +393,5 @@ const struct packet_manager_funcs kfd_v9_pm_funcs = {
+ 	.unmap_queues_size	= sizeof(struct pm4_mes_unmap_queues),
+ 	.set_grace_period_size  = sizeof(struct pm4_mec_write_data_mmio),
+ 	.query_status_size	= sizeof(struct pm4_mes_query_status),
+-	.release_mem_size	= sizeof(struct pm4_mec_release_mem)
++	.release_mem_size	= 0,
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4395-drm-amd-display-initialize-lttpr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4395-drm-amd-display-initialize-lttpr.patch
new file mode 100644
index 00000000..8cc3f49f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4395-drm-amd-display-initialize-lttpr.patch
@@ -0,0 +1,184 @@
+From 78a856ebb3735507182f57303745004582b06d9d Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Fri, 19 Jul 2019 10:25:39 -0400
+Subject: [PATCH 4395/4736] drm/amd/display: initialize lttpr
+
+[Description]
+When reading link, update the procedure as follows:
+1-Set aux timeout to extended: 3.2ms
+2-Start with reading lttpr caps
+3-Determine if lttpr support should be enabled. Reset aux timeout to
+400us if no repeater is found.
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 56 +++++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/dc.h           |  2 +
+ drivers/gpu/drm/amd/display/dc/dc_link.h      |  1 +
+ drivers/gpu/drm/amd/display/dc/dc_types.h     | 36 ++++++++++++
+ 4 files changed, 95 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 0f59b68aa4c2..2a89f90ef7a7 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -21,6 +21,9 @@
+ #define DC_LOGGER \
+ 	link->ctx->logger
+ 
++
++#define DP_REPEATER_CONFIGURATION_AND_STATUS_OFFSET   0x50
++
+ /* maximum pre emphasis level allowed for each voltage swing level*/
+ static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
+ 		PRE_EMPHASIS_LEVEL3,
+@@ -2753,6 +2756,14 @@ static bool retrieve_link_cap(struct dc_link *link)
+ 	int i;
+ 	struct dp_sink_hw_fw_revision dp_hw_fw_revision;
+ 
++	/* Set default timeout to 3.2ms and read LTTPR capabilities */
++	bool ext_timeout_support = link->dc->caps.extended_aux_timeout_support &&
++			!link->dc->config.disable_extended_timeout_support;
++	if (ext_timeout_support) {
++		status = dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
++		link->is_lttpr_mode_transparent = true;
++	}
++
+ 	memset(dpcd_data, '\0', sizeof(dpcd_data));
+ 	memset(&down_strm_port_count,
+ 		'\0', sizeof(union down_stream_port_count));
+@@ -2785,6 +2796,51 @@ static bool retrieve_link_cap(struct dc_link *link)
+ 		return false;
+ 	}
+ 
++	if (ext_timeout_support) {
++		status = core_link_read_dpcd(
++				link,
++				DP_PHY_REPEATER_CNT,
++				&link->dpcd_caps.lttpr_caps.phy_repeater_cnt,
++				sizeof(link->dpcd_caps.lttpr_caps.phy_repeater_cnt));
++
++		if (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0) {
++
++			link->is_lttpr_mode_transparent = false;
++
++			status = core_link_read_dpcd(
++					link,
++					DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
++					(uint8_t *)&link->dpcd_caps.lttpr_caps.revision,
++					sizeof(link->dpcd_caps.lttpr_caps.revision));
++
++			status = core_link_read_dpcd(
++					link,
++					DP_MAX_LINK_RATE_PHY_REPEATER,
++					&link->dpcd_caps.lttpr_caps.max_link_rate,
++					sizeof(link->dpcd_caps.lttpr_caps.max_link_rate));
++
++			status = core_link_read_dpcd(
++					link,
++					DP_PHY_REPEATER_MODE,
++					(uint8_t *)&link->dpcd_caps.lttpr_caps.mode,
++					sizeof(link->dpcd_caps.lttpr_caps.mode));
++
++			status = core_link_read_dpcd(
++					link,
++					DP_MAX_LANE_COUNT_PHY_REPEATER,
++					&link->dpcd_caps.lttpr_caps.max_lane_count,
++					sizeof(link->dpcd_caps.lttpr_caps.max_lane_count));
++
++			status = core_link_read_dpcd(
++					link,
++					DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT,
++					&link->dpcd_caps.lttpr_caps.max_ext_timeout,
++					sizeof(link->dpcd_caps.lttpr_caps.max_ext_timeout));
++		} else {
++			dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
++		}
++	}
++
+ 	{
+ 		union training_aux_rd_interval aux_rd_interval;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index f12ad4b17781..8ff7556eb2c4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -994,6 +994,8 @@ struct dpcd_caps {
+ 	union dpcd_fec_capability fec_cap;
+ 	struct dpcd_dsc_capabilities dsc_caps;
+ #endif
++	struct dc_lttpr_caps lttpr_caps;
++
+ };
+ 
+ #include "dc_link.h"
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
+index 9270e43cd5bb..67ba6666a324 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
+@@ -85,6 +85,7 @@ struct dc_link {
+ 	bool link_state_valid;
+ 	bool aux_access_disabled;
+ 	bool sync_lt_in_progress;
++	bool is_lttpr_mode_transparent;
+ 
+ 	/* caps is the same as reported_link_cap. link_traing use
+ 	 * reported_link_cap. Will clean up.  TODO
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
+index 7ab7644458e7..837859e65e45 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
+@@ -122,6 +122,7 @@ struct dc_context {
+ #define DC_EDID_BLOCK_SIZE 128
+ #define MAX_SURFACE_NUM 4
+ #define NUM_PIXEL_FORMATS 10
++#define MAX_REPEATER_CNT 8
+ 
+ #include "dc_ddc_types.h"
+ 
+@@ -405,6 +406,41 @@ enum dpcd_downstream_port_max_bpc {
+ 	DOWN_STREAM_MAX_12BPC,
+ 	DOWN_STREAM_MAX_16BPC
+ };
++
++
++enum link_training_offset {
++	DPRX                = 0,
++	LTTPR_PHY_REPEATER1 = 1,
++	LTTPR_PHY_REPEATER2 = 2,
++	LTTPR_PHY_REPEATER3 = 3,
++	LTTPR_PHY_REPEATER4 = 4,
++	LTTPR_PHY_REPEATER5 = 5,
++	LTTPR_PHY_REPEATER6 = 6,
++	LTTPR_PHY_REPEATER7 = 7,
++	LTTPR_PHY_REPEATER8 = 8
++};
++
++enum lttpr_mode {
++	phy_repeater_mode_transparent		= 0x55,
++	phy_repeater_mode_non_transparent	= 0xAA
++};
++
++enum lttpr_rev {
++	lttpr_rev_unknown	= 0x0,
++	lttpr_rev_14		= 0x14,
++	lttpr_rev_max		= 0x20
++};
++
++struct dc_lttpr_caps {
++	enum lttpr_rev revision;
++	enum lttpr_mode mode;
++	uint8_t max_lane_count;
++	uint8_t max_link_rate;
++	uint8_t phy_repeater_cnt;
++	uint8_t max_ext_timeout;
++	uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1];
++};
++
+ struct dc_dongle_caps {
+ 	/* dongle type (DP converter, CV smart dongle) */
+ 	enum display_dongle_type dongle_type;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4396-drm-amd-display-check-for-dp-rev-before-reading-lttp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4396-drm-amd-display-check-for-dp-rev-before-reading-lttp.patch
new file mode 100644
index 00000000..12fcd76a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4396-drm-amd-display-check-for-dp-rev-before-reading-lttp.patch
@@ -0,0 +1,47 @@
+From 92a6ea98405ccb7b2c47b2480a1e43bbc7e5d1a1 Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Wed, 18 Sep 2019 11:57:47 -0400
+Subject: [PATCH 4396/4736] drm/amd/display: check for dp rev before reading
+ lttpr regs
+
+[Why]
+LTTPR was introduced after DP1.2. Reading LTTPR registers 0xFXXXX
+on some DP 1.2 display is causing an unexpected behavior.
+
+[How]
+Make sure that we don't read any lttpr registers on 1.2 displays.
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 2a89f90ef7a7..1e4480f3bd3c 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2759,9 +2759,10 @@ static bool retrieve_link_cap(struct dc_link *link)
+ 	/* Set default timeout to 3.2ms and read LTTPR capabilities */
+ 	bool ext_timeout_support = link->dc->caps.extended_aux_timeout_support &&
+ 			!link->dc->config.disable_extended_timeout_support;
++	link->is_lttpr_mode_transparent = true;
++
+ 	if (ext_timeout_support) {
+ 		status = dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
+-		link->is_lttpr_mode_transparent = true;
+ 	}
+ 
+ 	memset(dpcd_data, '\0', sizeof(dpcd_data));
+@@ -2796,7 +2797,7 @@ static bool retrieve_link_cap(struct dc_link *link)
+ 		return false;
+ 	}
+ 
+-	if (ext_timeout_support) {
++	if (ext_timeout_support && link->dpcd_caps.dpcd_rev.raw >= 0x14) {
+ 		status = core_link_read_dpcd(
+ 				link,
+ 				DP_PHY_REPEATER_CNT,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4397-drm-amd-display-configure-lttpr-mode.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4397-drm-amd-display-configure-lttpr-mode.patch
new file mode 100644
index 00000000..d50e4f90
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4397-drm-amd-display-configure-lttpr-mode.patch
@@ -0,0 +1,100 @@
+From e56d9800bac89178bca2adae9ce2f4775f561262 Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Fri, 19 Jul 2019 10:43:42 -0400
+Subject: [PATCH 4397/4736] drm/amd/display: configure lttpr mode
+
+[Description]
+1-Grant extended timeout request. Done once after detection
+2-Configure lttpr mode based on lttpr support before LT
+3-Account for lttpr cap when determining max link settings
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 42 +++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 1e4480f3bd3c..94d5a0ac308f 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -1057,6 +1057,26 @@ static void initialize_training_settings(
+ 		lt_settings->enhanced_framing = 1;
+ }
+ 
++static void configure_lttpr_mode(struct dc_link *link)
++{
++	/* aux timeout is already set to extended */
++	/* RESET/SET lttpr mode to enable non transparent mode */
++	enum lttpr_mode repeater_mode = phy_repeater_mode_transparent;
++
++	core_link_write_dpcd(link,
++			DP_PHY_REPEATER_MODE,
++			(uint8_t *)&repeater_mode,
++			sizeof(repeater_mode));
++
++	if (!link->is_lttpr_mode_transparent) {
++		repeater_mode = phy_repeater_mode_non_transparent;
++		core_link_write_dpcd(link,
++				DP_PHY_REPEATER_MODE,
++				(uint8_t *)&repeater_mode,
++				sizeof(repeater_mode));
++	}
++}
++
+ static void print_status_message(
+ 	struct dc_link *link,
+ 	const struct link_training_settings *lt_settings,
+@@ -1210,6 +1230,9 @@ enum link_training_result dc_link_dp_perform_link_training(
+ 	dp_set_fec_ready(link, fec_enable);
+ #endif
+ 
++	/* Configure lttpr mode */
++	if (!link->is_lttpr_mode_transparent)
++		configure_lttpr_mode(link);
+ 
+ 	/* 2. perform link training (set link training done
+ 	 *  to false is done as well)
+@@ -1426,6 +1449,17 @@ static struct dc_link_settings get_max_link_cap(struct dc_link *link)
+ 			max_link_cap.link_spread)
+ 		max_link_cap.link_spread =
+ 				link->reported_link_cap.link_spread;
++	/*
++	 * account for lttpr repeaters cap
++	 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
++	 */
++	if (!link->is_lttpr_mode_transparent) {
++		if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
++			max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
++
++		if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
++			max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
++	}
+ 	return max_link_cap;
+ }
+ 
+@@ -1571,6 +1605,13 @@ bool dp_verify_link_cap(
+ 
+ 	max_link_cap = get_max_link_cap(link);
+ 
++	/* Grant extended timeout request */
++	if (!link->is_lttpr_mode_transparent && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {
++		uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
++
++		core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
++	}
++
+ 	/* TODO implement override and monitor patch later */
+ 
+ 	/* try to train the link from high to low to
+@@ -2759,6 +2800,7 @@ static bool retrieve_link_cap(struct dc_link *link)
+ 	/* Set default timeout to 3.2ms and read LTTPR capabilities */
+ 	bool ext_timeout_support = link->dc->caps.extended_aux_timeout_support &&
+ 			!link->dc->config.disable_extended_timeout_support;
++
+ 	link->is_lttpr_mode_transparent = true;
+ 
+ 	if (ext_timeout_support) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4398-drm-amd-display-implement-lttpr-logic.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4398-drm-amd-display-implement-lttpr-logic.patch
new file mode 100644
index 00000000..556dee89
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4398-drm-amd-display-implement-lttpr-logic.patch
@@ -0,0 +1,729 @@
+From b8a60f6929135d3786e37046d7e736a6b975237d Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Wed, 24 Jul 2019 11:01:44 -0400
+Subject: [PATCH 4398/4736] drm/amd/display: implement lttpr logic
+
+1-If at least one repeater is present in the link and we are in non
+transparent mode, perform clock recovery then channel equalization
+with all repeaters one by one before training DPRX.
+
+2-Mark the end of LT with a repeater by setting training pattern 0
+at the end of channel equalization with each repeater.
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 319 ++++++++++++++----
+ .../drm/amd/display/dc/core/dc_link_hwss.c    |  39 ++-
+ .../gpu/drm/amd/display/dc/inc/link_hwss.h    |   6 +-
+ 3 files changed, 292 insertions(+), 72 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 94d5a0ac308f..11b6e14b345e 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -22,7 +22,7 @@
+ 	link->ctx->logger
+ 
+ 
+-#define DP_REPEATER_CONFIGURATION_AND_STATUS_OFFSET   0x50
++#define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE   0x50
+ 
+ /* maximum pre emphasis level allowed for each voltage swing level*/
+ static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
+@@ -224,19 +224,31 @@ static enum dpcd_training_patterns
+ 	return dpcd_tr_pattern;
+ }
+ 
++static inline bool is_repeater(struct dc_link *link, uint32_t offset)
++{
++	return (!link->is_lttpr_mode_transparent && offset != 0);
++}
++
+ static void dpcd_set_lt_pattern_and_lane_settings(
+ 	struct dc_link *link,
+ 	const struct link_training_settings *lt_settings,
+-	enum dc_dp_training_pattern pattern)
++	enum dc_dp_training_pattern pattern,
++	uint32_t offset)
+ {
+ 	union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
+-	const uint32_t dpcd_base_lt_offset =
+-	DP_TRAINING_PATTERN_SET;
++
++	uint32_t dpcd_base_lt_offset;
++
+ 	uint8_t dpcd_lt_buffer[5] = {0};
+ 	union dpcd_training_pattern dpcd_pattern = { {0} };
+ 	uint32_t lane;
+ 	uint32_t size_in_bytes;
+ 	bool edp_workaround = false; /* TODO link_prop.INTERNAL */
++	dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
++
++	if (is_repeater(link, offset))
++		dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
++			((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
+ 
+ 	/*****************************************************************
+ 	* DpcdAddress_TrainingPatternSet
+@@ -244,12 +256,12 @@ static void dpcd_set_lt_pattern_and_lane_settings(
+ 	dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
+ 		dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
+ 
+-	dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
++	dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
+ 		= dpcd_pattern.raw;
+ 
+-	DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
++	DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
+ 		__func__,
+-		DP_TRAINING_PATTERN_SET,
++		dpcd_base_lt_offset,
+ 		dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
+ 
+ 	/*****************************************************************
+@@ -271,19 +283,19 @@ static void dpcd_set_lt_pattern_and_lane_settings(
+ 		PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
+ 	}
+ 
+-	/* concatinate everything into one buffer*/
++	/* concatenate everything into one buffer*/
+ 
+ 	size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
+ 
+ 	 // 0x00103 - 0x00102
+ 	memmove(
+-		&dpcd_lt_buffer[DP_TRAINING_LANE0_SET - dpcd_base_lt_offset],
++		&dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
+ 		dpcd_lane,
+ 		size_in_bytes);
+ 
+-	DC_LOG_HW_LINK_TRAINING("%s:\n %x VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
++	DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
+ 		__func__,
+-		DP_TRAINING_LANE0_SET,
++		dpcd_base_lt_offset,
+ 		dpcd_lane[0].bits.VOLTAGE_SWING_SET,
+ 		dpcd_lane[0].bits.PRE_EMPHASIS_SET,
+ 		dpcd_lane[0].bits.MAX_SWING_REACHED,
+@@ -498,8 +510,12 @@ static void get_lane_status_and_drive_settings(
+ 	const struct link_training_settings *link_training_setting,
+ 	union lane_status *ln_status,
+ 	union lane_align_status_updated *ln_status_updated,
+-	struct link_training_settings *req_settings)
++	struct link_training_settings *req_settings,
++	uint32_t offset)
+ {
++	unsigned int lane01_status_address = DP_LANE0_1_STATUS;
++	uint8_t lane_adjust_offset = 4;
++	unsigned int lane01_adjust_address;
+ 	uint8_t dpcd_buf[6] = {0};
+ 	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
+ 	struct link_training_settings request_settings = { {0} };
+@@ -507,9 +523,16 @@ static void get_lane_status_and_drive_settings(
+ 
+ 	memset(req_settings, '\0', sizeof(struct link_training_settings));
+ 
++	if (is_repeater(link, offset)) {
++		lane01_status_address =
++				DP_LANE0_1_STATUS_PHY_REPEATER1 +
++				((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
++		lane_adjust_offset = 3;
++	}
++
+ 	core_link_read_dpcd(
+ 		link,
+-		DP_LANE0_1_STATUS,
++		lane01_status_address,
+ 		(uint8_t *)(dpcd_buf),
+ 		sizeof(dpcd_buf));
+ 
+@@ -520,22 +543,28 @@ static void get_lane_status_and_drive_settings(
+ 		ln_status[lane].raw =
+ 			get_nibble_at_index(&dpcd_buf[0], lane);
+ 		dpcd_lane_adjust[lane].raw =
+-			get_nibble_at_index(&dpcd_buf[4], lane);
++			get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
+ 	}
+ 
+ 	ln_status_updated->raw = dpcd_buf[2];
+ 
+-	DC_LOG_HW_LINK_TRAINING("%s:\n%x Lane01Status = %x\n %x Lane23Status = %x\n ",
++	DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
+ 		__func__,
+-		DP_LANE0_1_STATUS, dpcd_buf[0],
+-		DP_LANE2_3_STATUS, dpcd_buf[1]);
++		lane01_status_address, dpcd_buf[0],
++		lane01_status_address + 1, dpcd_buf[1]);
++
++	lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
++
++	if (is_repeater(link, offset))
++		lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
++				((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
+ 
+-	DC_LOG_HW_LINK_TRAINING("%s:\n %x Lane01AdjustRequest = %x\n %x Lane23AdjustRequest = %x\n",
++	DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
+ 		__func__,
+-		DP_ADJUST_REQUEST_LANE0_1,
+-		dpcd_buf[4],
+-		DP_ADJUST_REQUEST_LANE2_3,
+-		dpcd_buf[5]);
++		lane01_adjust_address,
++		dpcd_buf[lane_adjust_offset],
++		lane01_adjust_address + 1,
++		dpcd_buf[lane_adjust_offset + 1]);
+ 
+ 	/*copy to req_settings*/
+ 	request_settings.link_settings.lane_count =
+@@ -574,10 +603,18 @@ static void get_lane_status_and_drive_settings(
+ 
+ static void dpcd_set_lane_settings(
+ 	struct dc_link *link,
+-	const struct link_training_settings *link_training_setting)
++	const struct link_training_settings *link_training_setting,
++	uint32_t offset)
+ {
+ 	union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
+ 	uint32_t lane;
++	unsigned int lane0_set_address;
++
++	lane0_set_address = DP_TRAINING_LANE0_SET;
++
++	if (is_repeater(link, offset))
++		lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
++		((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
+ 
+ 	for (lane = 0; lane <
+ 		(uint32_t)(link_training_setting->
+@@ -600,7 +637,7 @@ static void dpcd_set_lane_settings(
+ 	}
+ 
+ 	core_link_write_dpcd(link,
+-		DP_TRAINING_LANE0_SET,
++		lane0_set_address,
+ 		(uint8_t *)(dpcd_lane),
+ 		link_training_setting->link_settings.lane_count);
+ 
+@@ -623,9 +660,9 @@ static void dpcd_set_lane_settings(
+ 	}
+ 	*/
+ 
+-	DC_LOG_HW_LINK_TRAINING("%s\n %x VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
++	DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
+ 		__func__,
+-		DP_TRAINING_LANE0_SET,
++		lane0_set_address,
+ 		dpcd_lane[0].bits.VOLTAGE_SWING_SET,
+ 		dpcd_lane[0].bits.PRE_EMPHASIS_SET,
+ 		dpcd_lane[0].bits.MAX_SWING_REACHED,
+@@ -650,17 +687,6 @@ static bool is_max_vs_reached(
+ 
+ }
+ 
+-void dc_link_dp_set_drive_settings(
+-	struct dc_link *link,
+-	struct link_training_settings *lt_settings)
+-{
+-	/* program ASIC PHY settings*/
+-	dp_set_hw_lane_settings(link, lt_settings);
+-
+-	/* Notify DP sink the PHY settings from source */
+-	dpcd_set_lane_settings(link, lt_settings);
+-}
+-
+ static bool perform_post_lt_adj_req_sequence(
+ 	struct dc_link *link,
+ 	struct link_training_settings *lt_settings)
+@@ -693,7 +719,8 @@ static bool perform_post_lt_adj_req_sequence(
+ 			lt_settings,
+ 			dpcd_lane_status,
+ 			&dpcd_lane_status_updated,
+-			&req_settings);
++			&req_settings,
++			DPRX);
+ 
+ 			if (dpcd_lane_status_updated.bits.
+ 					POST_LT_ADJ_REQ_IN_PROGRESS == 0)
+@@ -750,6 +777,31 @@ static bool perform_post_lt_adj_req_sequence(
+ 
+ }
+ 
++/* Only used for channel equalization */
++static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
++{
++	unsigned int aux_rd_interval_us = 400;
++
++	switch (dpcd_aux_read_interval) {
++	case 0x01:
++		aux_rd_interval_us = 400;
++		break;
++	case 0x02:
++		aux_rd_interval_us = 4000;
++		break;
++	case 0x03:
++		aux_rd_interval_us = 8000;
++		break;
++	case 0x04:
++		aux_rd_interval_us = 16000;
++		break;
++	default:
++		break;
++	}
++
++	return aux_rd_interval_us;
++}
++
+ static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
+ 					union lane_status *dpcd_lane_status)
+ {
+@@ -768,37 +820,55 @@ static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
+ 
+ static enum link_training_result perform_channel_equalization_sequence(
+ 	struct dc_link *link,
+-	struct link_training_settings *lt_settings)
++	struct link_training_settings *lt_settings,
++	uint32_t offset)
+ {
+ 	struct link_training_settings req_settings;
+ 	enum dc_dp_training_pattern tr_pattern;
+ 	uint32_t retries_ch_eq;
++	uint32_t wait_time_microsec;
+ 	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
+ 	union lane_align_status_updated dpcd_lane_status_updated = { {0} };
+ 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
+ 
++	/* Note: also check that TPS4 is a supported feature*/
++
+ 	tr_pattern = lt_settings->pattern_for_eq;
+ 
+-	dp_set_hw_training_pattern(link, tr_pattern);
++	if (is_repeater(link, offset))
++		tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
++
++	dp_set_hw_training_pattern(link, tr_pattern, offset);
+ 
+ 	for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
+ 		retries_ch_eq++) {
+ 
+-		dp_set_hw_lane_settings(link, lt_settings);
++		dp_set_hw_lane_settings(link, lt_settings, offset);
+ 
+ 		/* 2. update DPCD*/
+ 		if (!retries_ch_eq)
+ 			/* EPR #361076 - write as a 5-byte burst,
+-			 * but only for the 1-st iteration*/
++			 * but only for the 1-st iteration
++			 */
++
+ 			dpcd_set_lt_pattern_and_lane_settings(
+ 				link,
+ 				lt_settings,
+-				tr_pattern);
++				tr_pattern, offset);
+ 		else
+-			dpcd_set_lane_settings(link, lt_settings);
++			dpcd_set_lane_settings(link, lt_settings, offset);
+ 
+ 		/* 3. wait for receiver to lock-on*/
+-		wait_for_training_aux_rd_interval(link, lt_settings->eq_pattern_time);
++		wait_time_microsec = lt_settings->eq_pattern_time;
++
++		if (!link->is_lttpr_mode_transparent)
++			wait_time_microsec =
++					translate_training_aux_read_interval(
++						link->dpcd_caps.lttpr_caps.aux_rd_interval[offset]);
++
++		wait_for_training_aux_rd_interval(
++				link,
++				wait_time_microsec);
+ 
+ 		/* 4. Read lane status and requested
+ 		 * drive settings as set by the sink*/
+@@ -808,7 +878,8 @@ static enum link_training_result perform_channel_equalization_sequence(
+ 			lt_settings,
+ 			dpcd_lane_status,
+ 			&dpcd_lane_status_updated,
+-			&req_settings);
++			&req_settings,
++			offset);
+ 
+ 		/* 5. check CR done*/
+ 		if (!is_cr_done(lane_count, dpcd_lane_status))
+@@ -827,13 +898,16 @@ static enum link_training_result perform_channel_equalization_sequence(
+ 	return LINK_TRAINING_EQ_FAIL_EQ;
+ 
+ }
++#define TRAINING_AUX_RD_INTERVAL 100 //us
+ 
+ static enum link_training_result perform_clock_recovery_sequence(
+ 	struct dc_link *link,
+-	struct link_training_settings *lt_settings)
++	struct link_training_settings *lt_settings,
++	uint32_t offset)
+ {
+ 	uint32_t retries_cr;
+ 	uint32_t retry_count;
++	uint32_t wait_time_microsec;
+ 	struct link_training_settings req_settings;
+ 	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
+ 	enum dc_dp_training_pattern tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_1;
+@@ -843,7 +917,7 @@ static enum link_training_result perform_clock_recovery_sequence(
+ 	retries_cr = 0;
+ 	retry_count = 0;
+ 
+-	dp_set_hw_training_pattern(link, tr_pattern);
++	dp_set_hw_training_pattern(link, tr_pattern, offset);
+ 
+ 	/* najeeb - The synaptics MST hub can put the LT in
+ 	* infinite loop by switching the VS
+@@ -860,7 +934,8 @@ static enum link_training_result perform_clock_recovery_sequence(
+ 		/* 1. call HWSS to set lane settings*/
+ 		dp_set_hw_lane_settings(
+ 				link,
+-				lt_settings);
++				lt_settings,
++				offset);
+ 
+ 		/* 2. update DPCD of the receiver*/
+ 		if (!retries_cr)
+@@ -869,16 +944,23 @@ static enum link_training_result perform_clock_recovery_sequence(
+ 			dpcd_set_lt_pattern_and_lane_settings(
+ 					link,
+ 					lt_settings,
+-					tr_pattern);
++					tr_pattern,
++					offset);
+ 		else
+ 			dpcd_set_lane_settings(
+ 					link,
+-					lt_settings);
++					lt_settings,
++					offset);
+ 
+ 		/* 3. wait receiver to lock-on*/
++		wait_time_microsec = lt_settings->cr_pattern_time;
++
++		if (!link->is_lttpr_mode_transparent)
++			wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
++
+ 		wait_for_training_aux_rd_interval(
+ 				link,
+-				lt_settings->cr_pattern_time);
++				wait_time_microsec);
+ 
+ 		/* 4. Read lane status and requested drive
+ 		* settings as set by the sink
+@@ -888,7 +970,8 @@ static enum link_training_result perform_clock_recovery_sequence(
+ 				lt_settings,
+ 				dpcd_lane_status,
+ 				&dpcd_lane_status_updated,
+-				&req_settings);
++				&req_settings,
++				offset);
+ 
+ 		/* 5. check CR done*/
+ 		if (is_cr_done(lane_count, dpcd_lane_status))
+@@ -1057,10 +1140,38 @@ static void initialize_training_settings(
+ 		lt_settings->enhanced_framing = 1;
+ }
+ 
++static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
++{
++	switch (lttpr_repeater_count) {
++	case 0x80: // 1 lttpr repeater
++		return 1;
++	case 0x40: // 2 lttpr repeaters
++		return 2;
++	case 0x20: // 3 lttpr repeaters
++		return 3;
++	case 0x10: // 4 lttpr repeaters
++		return 4;
++	case 0x08: // 5 lttpr repeaters
++		return 5;
++	case 0x04: // 6 lttpr repeaters
++		return 6;
++	case 0x02: // 7 lttpr repeaters
++		return 7;
++	case 0x01: // 8 lttpr repeaters
++		return 8;
++	default:
++		break;
++	}
++	return 0; // invalid value
++}
++
+ static void configure_lttpr_mode(struct dc_link *link)
+ {
+ 	/* aux timeout is already set to extended */
+ 	/* RESET/SET lttpr mode to enable non transparent mode */
++	uint8_t repeater_cnt;
++	uint32_t aux_interval_address;
++	uint8_t repeater_id;
+ 	enum lttpr_mode repeater_mode = phy_repeater_mode_transparent;
+ 
+ 	core_link_write_dpcd(link,
+@@ -1074,9 +1185,43 @@ static void configure_lttpr_mode(struct dc_link *link)
+ 				DP_PHY_REPEATER_MODE,
+ 				(uint8_t *)&repeater_mode,
+ 				sizeof(repeater_mode));
++
++		repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
++		for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
++			aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
++						((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
++			core_link_read_dpcd(
++				link,
++				aux_interval_address,
++				(uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
++				sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
++			link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
++		}
+ 	}
+ }
+ 
++static void repeater_training_done(struct dc_link *link, uint32_t offset)
++{
++	union dpcd_training_pattern dpcd_pattern = { {0} };
++
++	const uint32_t dpcd_base_lt_offset =
++			DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
++				((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
++	/* Set training not in progress*/
++	dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
++
++	core_link_write_dpcd(
++		link,
++		dpcd_base_lt_offset,
++		&dpcd_pattern.raw,
++		1);
++
++	DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
++		__func__,
++		dpcd_base_lt_offset,
++		dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
++}
++
+ static void print_status_message(
+ 	struct dc_link *link,
+ 	const struct link_training_settings *lt_settings,
+@@ -1156,6 +1301,17 @@ static void print_status_message(
+ 				lt_spread);
+ }
+ 
++void dc_link_dp_set_drive_settings(
++	struct dc_link *link,
++	struct link_training_settings *lt_settings)
++{
++	/* program ASIC PHY settings*/
++	dp_set_hw_lane_settings(link, lt_settings, DPRX);
++
++	/* Notify DP sink the PHY settings from source */
++	dpcd_set_lane_settings(link, lt_settings, DPRX);
++}
++
+ bool dc_link_dp_perform_link_training_skip_aux(
+ 	struct dc_link *link,
+ 	const struct dc_link_settings *link_setting)
+@@ -1172,10 +1328,10 @@ bool dc_link_dp_perform_link_training_skip_aux(
+ 	/* 1. Perform_clock_recovery_sequence. */
+ 
+ 	/* transmit training pattern for clock recovery */
+-	dp_set_hw_training_pattern(link, pattern_for_cr);
++	dp_set_hw_training_pattern(link, pattern_for_cr, DPRX);
+ 
+ 	/* call HWSS to set lane settings*/
+-	dp_set_hw_lane_settings(link, &lt_settings);
++	dp_set_hw_lane_settings(link, &lt_settings, DPRX);
+ 
+ 	/* wait receiver to lock-on*/
+ 	wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
+@@ -1183,10 +1339,10 @@ bool dc_link_dp_perform_link_training_skip_aux(
+ 	/* 2. Perform_channel_equalization_sequence. */
+ 
+ 	/* transmit training pattern for channel equalization. */
+-	dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq);
++	dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
+ 
+ 	/* call HWSS to set lane settings*/
+-	dp_set_hw_lane_settings(link, &lt_settings);
++	dp_set_hw_lane_settings(link, &lt_settings, DPRX);
+ 
+ 	/* wait receiver to lock-on. */
+ 	wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
+@@ -1208,9 +1364,12 @@ enum link_training_result dc_link_dp_perform_link_training(
+ {
+ 	enum link_training_result status = LINK_TRAINING_SUCCESS;
+ 	struct link_training_settings lt_settings;
++
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	bool fec_enable;
+ #endif
++	uint8_t repeater_cnt;
++	uint8_t repeater_id;
+ 
+ 	initialize_training_settings(
+ 			link,
+@@ -1230,17 +1389,40 @@ enum link_training_result dc_link_dp_perform_link_training(
+ 	dp_set_fec_ready(link, fec_enable);
+ #endif
+ 
+-	/* Configure lttpr mode */
+-	if (!link->is_lttpr_mode_transparent)
++	if (!link->is_lttpr_mode_transparent) {
++		/* Configure lttpr mode */
+ 		configure_lttpr_mode(link);
+ 
+-	/* 2. perform link training (set link training done
+-	 *  to false is done as well)
+-	 */
+-	status = perform_clock_recovery_sequence(link, &lt_settings);
++		/* 2. perform link training (set link training done
++		 *  to false is done as well)
++		 */
++		repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
++
++		for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
++				repeater_id--) {
++			status = perform_clock_recovery_sequence(link, &lt_settings, repeater_id);
++
++			if (status != LINK_TRAINING_SUCCESS)
++				break;
++
++			status = perform_channel_equalization_sequence(link,
++					&lt_settings,
++					repeater_id);
++
++			if (status != LINK_TRAINING_SUCCESS)
++				break;
++
++			repeater_training_done(link, repeater_id);
++		}
++	}
++
++	if (status == LINK_TRAINING_SUCCESS) {
++		status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
+ 	if (status == LINK_TRAINING_SUCCESS) {
+ 		status = perform_channel_equalization_sequence(link,
+-				&lt_settings);
++					&lt_settings,
++					DPRX);
++		}
+ 	}
+ 
+ 	if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
+@@ -1393,10 +1575,11 @@ enum link_training_result dc_link_dp_sync_lt_attempt(
+ 	/* 2. perform link training (set link training done
+ 	 *  to false is done as well)
+ 	 */
+-	lt_status = perform_clock_recovery_sequence(link, &lt_settings);
++	lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
+ 	if (lt_status == LINK_TRAINING_SUCCESS) {
+ 		lt_status = perform_channel_equalization_sequence(link,
+-						&lt_settings);
++						&lt_settings,
++						DPRX);
+ 	}
+ 
+ 	/* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
+@@ -3355,8 +3538,8 @@ bool dc_link_dp_set_test_pattern(
+ 	if (is_dp_phy_pattern(test_pattern)) {
+ 		/* Set DPCD Lane Settings before running test pattern */
+ 		if (p_link_settings != NULL) {
+-			dp_set_hw_lane_settings(link, p_link_settings);
+-			dpcd_set_lane_settings(link, p_link_settings);
++			dp_set_hw_lane_settings(link, p_link_settings, DPRX);
++			dpcd_set_lane_settings(link, p_link_settings, DPRX);
+ 		}
+ 
+ 		/* Blank stream if running test pattern */
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index a519dbc5ecb6..5efbdc1eb173 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -19,6 +19,36 @@
+ #include "resource.h"
+ #endif
+ 
++static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
++{
++	switch (lttpr_repeater_count) {
++	case 0x80: // 1 lttpr repeater
++		return 1;
++	case 0x40: // 2 lttpr repeaters
++		return 2;
++	case 0x20: // 3 lttpr repeaters
++		return 3;
++	case 0x10: // 4 lttpr repeaters
++		return 4;
++	case 0x08: // 5 lttpr repeaters
++		return 5;
++	case 0x04: // 6 lttpr repeaters
++		return 6;
++	case 0x02: // 7 lttpr repeaters
++		return 7;
++	case 0x01: // 8 lttpr repeaters
++		return 8;
++	default:
++		break;
++	}
++	return 0; // invalid value
++}
++
++static inline bool is_immediate_downstream(struct dc_link *link, uint32_t offset)
++{
++	return (convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == offset);
++}
++
+ enum dc_status core_link_read_dpcd(
+ 	struct dc_link *link,
+ 	uint32_t address,
+@@ -212,7 +242,8 @@ void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal)
+ 
+ bool dp_set_hw_training_pattern(
+ 	struct dc_link *link,
+-	enum dc_dp_training_pattern pattern)
++	enum dc_dp_training_pattern pattern,
++	uint32_t offset)
+ {
+ 	enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
+ 
+@@ -240,10 +271,14 @@ bool dp_set_hw_training_pattern(
+ 
+ void dp_set_hw_lane_settings(
+ 	struct dc_link *link,
+-	const struct link_training_settings *link_settings)
++	const struct link_training_settings *link_settings,
++	uint32_t offset)
+ {
+ 	struct link_encoder *encoder = link->link_enc;
+ 
++	if (!link->is_lttpr_mode_transparent && !is_immediate_downstream(link, offset))
++		return;
++
+ 	/* call Encoder to set lane settings */
+ 	encoder->funcs->dp_set_lane_settings(encoder, link_settings);
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+index 4eff5d38a2f9..9af7ee5bc8ee 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+@@ -60,11 +60,13 @@ void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal);
+ 
+ bool dp_set_hw_training_pattern(
+ 	struct dc_link *link,
+-	enum dc_dp_training_pattern pattern);
++	enum dc_dp_training_pattern pattern,
++	uint32_t offset);
+ 
+ void dp_set_hw_lane_settings(
+ 	struct dc_link *link,
+-	const struct link_training_settings *link_settings);
++	const struct link_training_settings *link_settings,
++	uint32_t offset);
+ 
+ void dp_set_hw_test_pattern(
+ 	struct dc_link *link,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4399-drm-amd-display-use-previous-aux-timeout-val-if-no-r.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4399-drm-amd-display-use-previous-aux-timeout-val-if-no-r.patch
new file mode 100644
index 00000000..52fe368b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4399-drm-amd-display-use-previous-aux-timeout-val-if-no-r.patch
@@ -0,0 +1,221 @@
+From 562af0eb8901f71ee602299a46b13ae29c18a860 Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Thu, 19 Sep 2019 15:51:00 -0400
+Subject: [PATCH 4399/4736] drm/amd/display: use previous aux timeout val if no
+ repeater.
+
+[Why]
+The aux timeout value is not default before reading link cap.
+Setting it to default when lttpr is not enabled causes some monitor
+not to light up.
+
+[How]
+Read the aux engine timeout value before setting it to extended.
+Set the aux engine timeout to its previous value if no lttpr.
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 13 +++---
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  9 ++--
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c  | 46 +++++++++++++++----
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.h  |  2 +-
+ .../gpu/drm/amd/display/dc/inc/dc_link_ddc.h  |  2 +-
+ .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |  2 +-
+ 6 files changed, 52 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+index 747cd0fbe571..68c0cf85deb7 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+@@ -648,17 +648,16 @@ bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc,
+ }
+ 
+ 
+-enum dc_status dc_link_aux_configure_timeout(struct ddc_service *ddc,
++uint32_t dc_link_aux_configure_timeout(struct ddc_service *ddc,
+ 		uint32_t timeout)
+ {
+-	enum dc_status status = DC_OK;
++	uint32_t prev_timeout = 0;
+ 	struct ddc *ddc_pin = ddc->ddc_pin;
+ 
+-	if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout == NULL)
+-		return DC_ERROR_UNEXPECTED;
+-	if (!ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout))
+-		status = DC_ERROR_UNEXPECTED;
+-	return status;
++	if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout)
++		prev_timeout =
++				ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);
++	return prev_timeout;
+ }
+ 
+ /*test only function*/
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 11b6e14b345e..6e1f00ab6646 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2977,6 +2977,7 @@ static bool retrieve_link_cap(struct dc_link *link)
+ 	union dp_downstream_port_present ds_port = { 0 };
+ 	enum dc_status status = DC_ERROR_UNEXPECTED;
+ 	uint32_t read_dpcd_retry_cnt = 3;
++	uint32_t prev_timeout_val;
+ 	int i;
+ 	struct dp_sink_hw_fw_revision dp_hw_fw_revision;
+ 
+@@ -2987,7 +2988,9 @@ static bool retrieve_link_cap(struct dc_link *link)
+ 	link->is_lttpr_mode_transparent = true;
+ 
+ 	if (ext_timeout_support) {
+-		status = dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
++		prev_timeout_val =
++				dc_link_aux_configure_timeout(link->ddc,
++						LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
+ 	}
+ 
+ 	memset(dpcd_data, '\0', sizeof(dpcd_data));
+@@ -3022,7 +3025,7 @@ static bool retrieve_link_cap(struct dc_link *link)
+ 		return false;
+ 	}
+ 
+-	if (ext_timeout_support && link->dpcd_caps.dpcd_rev.raw >= 0x14) {
++	if (ext_timeout_support) {
+ 		status = core_link_read_dpcd(
+ 				link,
+ 				DP_PHY_REPEATER_CNT,
+@@ -3063,7 +3066,7 @@ static bool retrieve_link_cap(struct dc_link *link)
+ 					&link->dpcd_caps.lttpr_caps.max_ext_timeout,
+ 					sizeof(link->dpcd_caps.lttpr_caps.max_ext_timeout));
+ 		} else {
+-			dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
++			dc_link_aux_configure_timeout(link->ddc, prev_timeout_val);
+ 		}
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+index ca1d076d4184..0b9d8c5b9323 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+@@ -57,12 +57,14 @@ enum {
+ 	AUX_DEFER_RETRY_COUNTER = 6
+ };
+ 
+-#define TIME_OUT_INCREMENT      1016
+-#define TIME_OUT_MULTIPLIER_8 	8
+-#define TIME_OUT_MULTIPLIER_16  16
+-#define TIME_OUT_MULTIPLIER_32  32
+-#define TIME_OUT_MULTIPLIER_64  64
+-#define MAX_TIMEOUT_LENGTH      127
++#define TIME_OUT_INCREMENT        1016
++#define TIME_OUT_MULTIPLIER_8     8
++#define TIME_OUT_MULTIPLIER_16    16
++#define TIME_OUT_MULTIPLIER_32    32
++#define TIME_OUT_MULTIPLIER_64    64
++#define MAX_TIMEOUT_LENGTH        127
++#define DEFAULT_AUX_ENGINE_MULT   0
++#define DEFAULT_AUX_ENGINE_LENGTH 69
+ 
+ static void release_engine(
+ 	struct dce_aux *engine)
+@@ -424,11 +426,14 @@ void dce110_engine_destroy(struct dce_aux **engine)
+ 
+ }
+ 
+-static bool dce_aux_configure_timeout(struct ddc_service *ddc,
++static uint32_t dce_aux_configure_timeout(struct ddc_service *ddc,
+ 		uint32_t timeout_in_us)
+ {
+ 	uint32_t multiplier = 0;
+ 	uint32_t length = 0;
++	uint32_t prev_length = 0;
++	uint32_t prev_mult = 0;
++	uint32_t prev_timeout_val = 0;
+ 	struct ddc *ddc_pin = ddc->ddc_pin;
+ 	struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
+ 	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine);
+@@ -437,7 +442,10 @@ static bool dce_aux_configure_timeout(struct ddc_service *ddc,
+ 	aux110->polling_timeout_period = timeout_in_us * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER;
+ 
+ 	/* 2-Update aux timeout period length and multiplier */
+-	if (timeout_in_us <= TIME_OUT_INCREMENT) {
++	if (timeout_in_us == 0) {
++		multiplier = DEFAULT_AUX_ENGINE_MULT;
++		length = DEFAULT_AUX_ENGINE_LENGTH;
++	} else if (timeout_in_us <= TIME_OUT_INCREMENT) {
+ 		multiplier = 0;
+ 		length = timeout_in_us/TIME_OUT_MULTIPLIER_8;
+ 		if (timeout_in_us % TIME_OUT_MULTIPLIER_8 != 0)
+@@ -461,9 +469,29 @@ static bool dce_aux_configure_timeout(struct ddc_service *ddc,
+ 
+ 	length = (length < MAX_TIMEOUT_LENGTH) ? length : MAX_TIMEOUT_LENGTH;
+ 
++	REG_GET_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, &prev_length, AUX_RX_TIMEOUT_LEN_MUL, &prev_mult);
++
++	switch (prev_mult) {
++	case 0:
++		prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_8;
++		break;
++	case 1:
++		prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_16;
++		break;
++	case 2:
++		prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_32;
++		break;
++	case 3:
++		prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_64;
++		break;
++	default:
++		prev_timeout_val = DEFAULT_AUX_ENGINE_LENGTH * TIME_OUT_MULTIPLIER_8;
++		break;
++	}
++
+ 	REG_UPDATE_SEQ_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, length, AUX_RX_TIMEOUT_LEN_MUL, multiplier);
+ 
+-	return true;
++	return prev_timeout_val;
+ }
+ 
+ static struct dce_aux_funcs aux_functions = {
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+index b4b2c79a8073..2e2e925a506b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+@@ -311,7 +311,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
+ 		struct aux_payload *cmd);
+ 
+ struct dce_aux_funcs {
+-	bool (*configure_timeout)
++	uint32_t (*configure_timeout)
+ 		(struct ddc_service *ddc,
+ 		 uint32_t timeout);
+ 	void (*destroy)
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+index 14716ba35662..de2d160114db 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+@@ -105,7 +105,7 @@ int dc_link_aux_transfer_raw(struct ddc_service *ddc,
+ bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc,
+ 		struct aux_payload *payload);
+ 
+-enum dc_status dc_link_aux_configure_timeout(struct ddc_service *ddc,
++uint32_t dc_link_aux_configure_timeout(struct ddc_service *ddc,
+ 		uint32_t timeout);
+ 
+ void dal_ddc_service_write_scdc_data(
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+index 045138dbdccb..a6500b98fe0d 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+@@ -28,7 +28,7 @@
+ 
+ #define LINK_TRAINING_ATTEMPTS 4
+ #define LINK_TRAINING_RETRY_DELAY 50 /* ms */
+-#define LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD 32000 /*us*/
++#define LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD 3200 /*us*/
+ #define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 400 /*us*/
+ 
+ struct dc_link;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4400-drm-amd-display-disable-lttpr-for-invalid-lttpr-caps.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4400-drm-amd-display-disable-lttpr-for-invalid-lttpr-caps.patch
new file mode 100644
index 00000000..5765daa6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4400-drm-amd-display-disable-lttpr-for-invalid-lttpr-caps.patch
@@ -0,0 +1,222 @@
+From 1e75247d954914c51e84fac13a6b3cfe31670c24 Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Thu, 10 Oct 2019 16:41:52 -0400
+Subject: [PATCH 4400/4736] drm/amd/display: disable lttpr for invalid lttpr
+ caps.
+
+1-Read lttpr caps in 5-bytes
+2-Parse caps
+3-Validate caps and set lttpr_mode
+4-Use hw default timeout when lttpr is disabled.
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 90 ++++++++++---------
+ drivers/gpu/drm/amd/display/dc/dc_types.h     | 15 +---
+ .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |  2 +-
+ include/drm/drm_dp_helper.h                   |  4 +
+ 4 files changed, 53 insertions(+), 58 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 6e1f00ab6646..7d18fc1e68c6 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -1172,7 +1172,7 @@ static void configure_lttpr_mode(struct dc_link *link)
+ 	uint8_t repeater_cnt;
+ 	uint32_t aux_interval_address;
+ 	uint8_t repeater_id;
+-	enum lttpr_mode repeater_mode = phy_repeater_mode_transparent;
++	uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
+ 
+ 	core_link_write_dpcd(link,
+ 			DP_PHY_REPEATER_MODE,
+@@ -1180,7 +1180,7 @@ static void configure_lttpr_mode(struct dc_link *link)
+ 			sizeof(repeater_mode));
+ 
+ 	if (!link->is_lttpr_mode_transparent) {
+-		repeater_mode = phy_repeater_mode_non_transparent;
++		repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
+ 		core_link_write_dpcd(link,
+ 				DP_PHY_REPEATER_MODE,
+ 				(uint8_t *)&repeater_mode,
+@@ -2964,7 +2964,11 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
+ 
+ static bool retrieve_link_cap(struct dc_link *link)
+ {
+-	uint8_t dpcd_data[DP_ADAPTER_CAP - DP_DPCD_REV + 1];
++	/* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
++	 * which means size 16 will be good for both of those DPCD register block reads
++	 */
++	uint8_t dpcd_data[16];
++	uint8_t lttpr_dpcd_data[6];
+ 
+ 	/*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
+ 	 */
+@@ -2977,7 +2981,6 @@ static bool retrieve_link_cap(struct dc_link *link)
+ 	union dp_downstream_port_present ds_port = { 0 };
+ 	enum dc_status status = DC_ERROR_UNEXPECTED;
+ 	uint32_t read_dpcd_retry_cnt = 3;
+-	uint32_t prev_timeout_val;
+ 	int i;
+ 	struct dp_sink_hw_fw_revision dp_hw_fw_revision;
+ 
+@@ -2988,12 +2991,12 @@ static bool retrieve_link_cap(struct dc_link *link)
+ 	link->is_lttpr_mode_transparent = true;
+ 
+ 	if (ext_timeout_support) {
+-		prev_timeout_val =
+-				dc_link_aux_configure_timeout(link->ddc,
+-						LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
++		dc_link_aux_configure_timeout(link->ddc,
++					LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
+ 	}
+ 
+ 	memset(dpcd_data, '\0', sizeof(dpcd_data));
++	memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
+ 	memset(&down_strm_port_count,
+ 		'\0', sizeof(union down_stream_port_count));
+ 	memset(&edp_config_cap, '\0',
+@@ -3026,47 +3029,46 @@ static bool retrieve_link_cap(struct dc_link *link)
+ 	}
+ 
+ 	if (ext_timeout_support) {
++
+ 		status = core_link_read_dpcd(
+ 				link,
+-				DP_PHY_REPEATER_CNT,
+-				&link->dpcd_caps.lttpr_caps.phy_repeater_cnt,
+-				sizeof(link->dpcd_caps.lttpr_caps.phy_repeater_cnt));
+-
+-		if (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0) {
+-
++				DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
++				lttpr_dpcd_data,
++				sizeof(lttpr_dpcd_data));
++
++		link->dpcd_caps.lttpr_caps.revision.raw =
++				lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
++								DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
++
++		link->dpcd_caps.lttpr_caps.max_link_rate =
++				lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
++								DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
++
++		link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
++				lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
++								DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
++
++		link->dpcd_caps.lttpr_caps.max_lane_count =
++				lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
++								DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
++
++		link->dpcd_caps.lttpr_caps.mode =
++				lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
++								DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
++
++		link->dpcd_caps.lttpr_caps.max_ext_timeout =
++				lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
++								DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
++
++		if (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
++				link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
++				link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
++				link->dpcd_caps.lttpr_caps.revision.raw >= 0x14) {
+ 			link->is_lttpr_mode_transparent = false;
+-
+-			status = core_link_read_dpcd(
+-					link,
+-					DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
+-					(uint8_t *)&link->dpcd_caps.lttpr_caps.revision,
+-					sizeof(link->dpcd_caps.lttpr_caps.revision));
+-
+-			status = core_link_read_dpcd(
+-					link,
+-					DP_MAX_LINK_RATE_PHY_REPEATER,
+-					&link->dpcd_caps.lttpr_caps.max_link_rate,
+-					sizeof(link->dpcd_caps.lttpr_caps.max_link_rate));
+-
+-			status = core_link_read_dpcd(
+-					link,
+-					DP_PHY_REPEATER_MODE,
+-					(uint8_t *)&link->dpcd_caps.lttpr_caps.mode,
+-					sizeof(link->dpcd_caps.lttpr_caps.mode));
+-
+-			status = core_link_read_dpcd(
+-					link,
+-					DP_MAX_LANE_COUNT_PHY_REPEATER,
+-					&link->dpcd_caps.lttpr_caps.max_lane_count,
+-					sizeof(link->dpcd_caps.lttpr_caps.max_lane_count));
+-
+-			status = core_link_read_dpcd(
+-					link,
+-					DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT,
+-					&link->dpcd_caps.lttpr_caps.max_ext_timeout,
+-					sizeof(link->dpcd_caps.lttpr_caps.max_ext_timeout));
+ 		} else {
+-			dc_link_aux_configure_timeout(link->ddc, prev_timeout_val);
++			/*No lttpr reset timeout to its default value*/
++			link->is_lttpr_mode_transparent = true;
++			dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
+ 		}
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
+index 837859e65e45..45dfed8bcaf7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
+@@ -420,20 +420,9 @@ enum link_training_offset {
+ 	LTTPR_PHY_REPEATER8 = 8
+ };
+ 
+-enum lttpr_mode {
+-	phy_repeater_mode_transparent		= 0x55,
+-	phy_repeater_mode_non_transparent	= 0xAA
+-};
+-
+-enum lttpr_rev {
+-	lttpr_rev_unknown	= 0x0,
+-	lttpr_rev_14		= 0x14,
+-	lttpr_rev_max		= 0x20
+-};
+-
+ struct dc_lttpr_caps {
+-	enum lttpr_rev revision;
+-	enum lttpr_mode mode;
++	union dpcd_rev revision;
++	uint8_t mode;
+ 	uint8_t max_lane_count;
+ 	uint8_t max_link_rate;
+ 	uint8_t phy_repeater_cnt;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+index a6500b98fe0d..1e6ff6eb5bfc 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+@@ -29,7 +29,7 @@
+ #define LINK_TRAINING_ATTEMPTS 4
+ #define LINK_TRAINING_RETRY_DELAY 50 /* ms */
+ #define LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD 3200 /*us*/
+-#define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 400 /*us*/
++#define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /*us*/
+ 
+ struct dc_link;
+ struct dc_stream_state;
+diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
+index b2a2c92ac67c..4f9184a238dd 100644
+--- a/include/drm/drm_dp_helper.h
++++ b/include/drm/drm_dp_helper.h
+@@ -967,6 +967,10 @@
+ #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1	    0xf003b /* 1.3 */
+ #define DP_FEC_STATUS_PHY_REPEATER1			    0xf0290 /* 1.4 */
+ 
++/* Repeater modes */
++#define DP_PHY_REPEATER_MODE_TRANSPARENT                   0x55    /* 1.3 */
++#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT               0xaa    /* 1.3 */
++
+ /* DP HDCP message start offsets in DPCD address space */
+ #define DP_HDCP_2_2_AKE_INIT_OFFSET		DP_HDCP_2_2_REG_RTX_OFFSET
+ #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET	DP_HDCP_2_2_REG_CERT_RX_OFFSET
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4401-drm-amd-powerplay-correct-Arcturus-OD-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4401-drm-amd-powerplay-correct-Arcturus-OD-support.patch
new file mode 100644
index 00000000..ab0bc3fd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4401-drm-amd-powerplay-correct-Arcturus-OD-support.patch
@@ -0,0 +1,52 @@
+From 8a8679854d41641f7aec1706e1c2770445a65b86 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 7 Nov 2019 15:33:50 +0800
+Subject: [PATCH 4401/4736] drm/amd/powerplay: correct Arcturus OD support
+
+OD is not supported on Arcturus. Thus the
+pp_od_clk_voltage sysfs interface is also not supported.
+
+Change-Id: Ib70632a55a0980cf04c3432d43dbcf869cd1b4bf
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index c21fe7ac5df8..76a4154b3be2 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -714,6 +714,9 @@ static int smu_set_funcs(struct amdgpu_device *adev)
+ {
+ 	struct smu_context *smu = &adev->smu;
+ 
++	if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
++		smu->od_enabled = true;
++
+ 	switch (adev->asic_type) {
+ 	case CHIP_VEGA20:
+ 		vega20_set_ppt_funcs(smu);
+@@ -725,6 +728,8 @@ static int smu_set_funcs(struct amdgpu_device *adev)
+ 		break;
+ 	case CHIP_ARCTURUS:
+ 		arcturus_set_ppt_funcs(smu);
++		/* OD is not supported on Arcturus */
++		smu->od_enabled =false;
+ 		break;
+ 	case CHIP_RENOIR:
+ 		renoir_set_ppt_funcs(smu);
+@@ -733,9 +738,6 @@ static int smu_set_funcs(struct amdgpu_device *adev)
+ 		return -EINVAL;
+ 	}
+ 
+-	if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
+-		smu->od_enabled = true;
+-
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4402-drm-amdkfd-Use-kernel-queue-v9-functions-for-v10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4402-drm-amdkfd-Use-kernel-queue-v9-functions-for-v10.patch
new file mode 100644
index 00000000..5450fb3c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4402-drm-amdkfd-Use-kernel-queue-v9-functions-for-v10.patch
@@ -0,0 +1,508 @@
+From 96cdd7e6717e0d16d6f0c546976e2149f0dbfd15 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 30 Oct 2019 19:22:11 -0400
+Subject: [PATCH 4402/4736] drm/amdkfd: Use kernel queue v9 functions for v10
+
+The kernel queue functions for v9 and v10 are the same except
+pm_map_process_v* which have small difference, so they should be reused.
+This eliminates the need of reapplying several patches which were
+applied on v9 but not on v10, such as bigger GWS and more than 2
+SDMA engine support which were introduced on Arcturus.
+
+Change-Id: I2d385961e3c884db14e30b5afc98d0d9e4cb1802
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/Makefile           |   1 -
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c |   4 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h |   1 -
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c | 359 ------------------
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c  |  16 +-
+ .../gpu/drm/amd/amdkfd/kfd_packet_manager.c   |   4 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h         |   3 -
+ 7 files changed, 14 insertions(+), 374 deletions(-)
+ delete mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile
+index aa951107a895..c2c125156a62 100644
+--- a/drivers/gpu/drm/amd/amdkfd/Makefile
++++ b/drivers/gpu/drm/amd/amdkfd/Makefile
+@@ -41,7 +41,6 @@ AMDKFD_FILES	:= $(AMDKFD_PATH)/kfd_module.o \
+ 		$(AMDKFD_PATH)/kfd_kernel_queue_cik.o \
+ 		$(AMDKFD_PATH)/kfd_kernel_queue_vi.o \
+ 		$(AMDKFD_PATH)/kfd_kernel_queue_v9.o \
+-		$(AMDKFD_PATH)/kfd_kernel_queue_v10.o \
+ 		$(AMDKFD_PATH)/kfd_packet_manager.o \
+ 		$(AMDKFD_PATH)/kfd_process_queue_manager.o \
+ 		$(AMDKFD_PATH)/kfd_device_queue_manager.o \
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+index 5e2d75ca2b62..04041bab42a8 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+@@ -367,12 +367,10 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
+ 	case CHIP_RAVEN:
+ 	case CHIP_RENOIR:
+ 	case CHIP_ARCTURUS:
+-		kernel_queue_init_v9(&kq->ops_asic_specific);
+-		break;
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI12:
+ 	case CHIP_NAVI14:
+-		kernel_queue_init_v10(&kq->ops_asic_specific);
++		kernel_queue_init_v9(&kq->ops_asic_specific);
+ 		break;
+ 	default:
+ 		WARN(1, "Unexpected ASIC family %u",
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
+index a23927d809c7..384d7a37b343 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
+@@ -112,6 +112,5 @@ struct kernel_queue {
+ void kernel_queue_init_cik(struct kernel_queue_ops *ops);
+ void kernel_queue_init_vi(struct kernel_queue_ops *ops);
+ void kernel_queue_init_v9(struct kernel_queue_ops *ops);
+-void kernel_queue_init_v10(struct kernel_queue_ops *ops);
+ 
+ #endif /* KFD_KERNEL_QUEUE_H_ */
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
+deleted file mode 100644
+index 5ee593ba3137..000000000000
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v10.c
++++ /dev/null
+@@ -1,359 +0,0 @@
+-/*
+- * Copyright 2018 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included in
+- * all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+- *
+- */
+-
+-#include "kfd_kernel_queue.h"
+-#include "kfd_device_queue_manager.h"
+-#include "kfd_pm4_headers_ai.h"
+-#include "kfd_pm4_opcodes.h"
+-#include "gc/gc_10_1_0_sh_mask.h"
+-
+-static bool initialize_v10(struct kernel_queue *kq, struct kfd_dev *dev,
+-			enum kfd_queue_type type, unsigned int queue_size);
+-static void uninitialize_v10(struct kernel_queue *kq);
+-static void submit_packet_v10(struct kernel_queue *kq);
+-
+-void kernel_queue_init_v10(struct kernel_queue_ops *ops)
+-{
+-	ops->initialize = initialize_v10;
+-	ops->uninitialize = uninitialize_v10;
+-	ops->submit_packet = submit_packet_v10;
+-}
+-
+-static bool initialize_v10(struct kernel_queue *kq, struct kfd_dev *dev,
+-			enum kfd_queue_type type, unsigned int queue_size)
+-{
+-	int retval;
+-
+-	retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, &kq->eop_mem);
+-	if (retval != 0)
+-		return false;
+-
+-	kq->eop_gpu_addr = kq->eop_mem->gpu_addr;
+-	kq->eop_kernel_addr = kq->eop_mem->cpu_ptr;
+-
+-	memset(kq->eop_kernel_addr, 0, PAGE_SIZE);
+-
+-	return true;
+-}
+-
+-static void uninitialize_v10(struct kernel_queue *kq)
+-{
+-	kfd_gtt_sa_free(kq->dev, kq->eop_mem);
+-}
+-
+-static void submit_packet_v10(struct kernel_queue *kq)
+-{
+-	*kq->wptr64_kernel = kq->pending_wptr64;
+-	write_kernel_doorbell64(kq->queue->properties.doorbell_ptr,
+-				kq->pending_wptr64);
+-}
+-
+-static int pm_map_process_v10(struct packet_manager *pm,
+-		uint32_t *buffer, struct qcm_process_device *qpd)
+-{
+-	struct pm4_mes_map_process *packet;
+-	uint64_t vm_page_table_base_addr = qpd->page_table_base;
+-	struct kfd_dev *kfd = pm->dqm->dev;
+-
+-	packet = (struct pm4_mes_map_process *)buffer;
+-	memset(buffer, 0, sizeof(struct pm4_mes_map_process));
+-
+-	packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,
+-					sizeof(struct pm4_mes_map_process));
+-	packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0;
+-	packet->bitfields2.process_quantum = 1;
+-	packet->bitfields2.pasid = qpd->pqm->process->pasid;
+-	packet->bitfields14.gds_size = qpd->gds_size;
+-	packet->bitfields14.num_gws = qpd->num_gws;
+-	packet->bitfields14.num_oac = qpd->num_oac;
+-	packet->bitfields14.sdma_enable = 1;
+-
+-	packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
+-
+-	if (kfd->dqm->trap_debug_vmid) {
+-		packet->bitfields2.debug_vmid = kfd->dqm->trap_debug_vmid;
+-		packet->bitfields2.new_debug = 1;
+-	}
+-
+-	packet->sh_mem_config = qpd->sh_mem_config;
+-	packet->sh_mem_bases = qpd->sh_mem_bases;
+-	if (qpd->tba_addr) {
+-		packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
+-		packet->sq_shader_tba_hi = (1 << SQ_SHADER_TBA_HI__TRAP_EN__SHIFT) |
+-			upper_32_bits(qpd->tba_addr >> 8);
+-		packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
+-		packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);
+-	}
+-
+-	packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
+-	packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
+-
+-	packet->vm_context_page_table_base_addr_lo32 =
+-			lower_32_bits(vm_page_table_base_addr);
+-	packet->vm_context_page_table_base_addr_hi32 =
+-			upper_32_bits(vm_page_table_base_addr);
+-
+-	return 0;
+-}
+-
+-static int pm_runlist_v10(struct packet_manager *pm, uint32_t *buffer,
+-			uint64_t ib, size_t ib_size_in_dwords, bool chain)
+-{
+-	struct pm4_mes_runlist *packet;
+-
+-	int concurrent_proc_cnt = 0;
+-	struct kfd_dev *kfd = pm->dqm->dev;
+-
+-	/* Determine the number of processes to map together to HW:
+-	 * it can not exceed the number of VMIDs available to the
+-	 * scheduler, and it is determined by the smaller of the number
+-	 * of processes in the runlist and kfd module parameter
+-	 * hws_max_conc_proc.
+-	 * Note: the arbitration between the number of VMIDs and
+-	 * hws_max_conc_proc has been done in
+-	 * kgd2kfd_device_init().
+-	 */
+-	concurrent_proc_cnt = min(pm->dqm->processes_count,
+-			kfd->max_proc_per_quantum);
+-
+-
+-	packet = (struct pm4_mes_runlist *)buffer;
+-
+-	memset(buffer, 0, sizeof(struct pm4_mes_runlist));
+-	packet->header.u32All = pm_build_pm4_header(IT_RUN_LIST,
+-						sizeof(struct pm4_mes_runlist));
+-
+-	packet->bitfields4.ib_size = ib_size_in_dwords;
+-	packet->bitfields4.chain = chain ? 1 : 0;
+-	packet->bitfields4.offload_polling = 0;
+-	packet->bitfields4.valid = 1;
+-	packet->bitfields4.process_cnt = concurrent_proc_cnt;
+-	packet->ordinal2 = lower_32_bits(ib);
+-	packet->ib_base_hi = upper_32_bits(ib);
+-
+-	return 0;
+-}
+-
+-static int pm_map_queues_v10(struct packet_manager *pm, uint32_t *buffer,
+-		struct queue *q, bool is_static)
+-{
+-	struct pm4_mes_map_queues *packet;
+-	bool use_static = is_static;
+-
+-	packet = (struct pm4_mes_map_queues *)buffer;
+-	memset(buffer, 0, sizeof(struct pm4_mes_map_queues));
+-
+-	packet->header.u32All = pm_build_pm4_header(IT_MAP_QUEUES,
+-					sizeof(struct pm4_mes_map_queues));
+-	packet->bitfields2.num_queues = 1;
+-	packet->bitfields2.queue_sel =
+-		queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi;
+-
+-	packet->bitfields2.engine_sel =
+-		engine_sel__mes_map_queues__compute_vi;
+-	packet->bitfields2.queue_type =
+-		queue_type__mes_map_queues__normal_compute_vi;
+-
+-	switch (q->properties.type) {
+-	case KFD_QUEUE_TYPE_COMPUTE:
+-		if (use_static)
+-			packet->bitfields2.queue_type =
+-		queue_type__mes_map_queues__normal_latency_static_queue_vi;
+-		break;
+-	case KFD_QUEUE_TYPE_DIQ:
+-		packet->bitfields2.queue_type =
+-			queue_type__mes_map_queues__debug_interface_queue_vi;
+-		break;
+-	case KFD_QUEUE_TYPE_SDMA:
+-	case KFD_QUEUE_TYPE_SDMA_XGMI:
+-		packet->bitfields2.engine_sel = q->properties.sdma_engine_id +
+-				engine_sel__mes_map_queues__sdma0_vi;
+-		use_static = false; /* no static queues under SDMA */
+-		break;
+-	default:
+-		WARN(1, "queue type %d\n", q->properties.type);
+-		return -EINVAL;
+-	}
+-	packet->bitfields3.doorbell_offset =
+-			q->properties.doorbell_off;
+-
+-	packet->mqd_addr_lo =
+-			lower_32_bits(q->gart_mqd_addr);
+-
+-	packet->mqd_addr_hi =
+-			upper_32_bits(q->gart_mqd_addr);
+-
+-	packet->wptr_addr_lo =
+-			lower_32_bits((uint64_t)q->properties.write_ptr);
+-
+-	packet->wptr_addr_hi =
+-			upper_32_bits((uint64_t)q->properties.write_ptr);
+-
+-	return 0;
+-}
+-
+-static int pm_set_grace_period_v10(struct packet_manager *pm,
+-					uint32_t *buffer,
+-					uint32_t grace_period)
+-{
+-	struct pm4_mec_write_data_mmio *packet;
+-	uint32_t reg_offset = 0;
+-	uint32_t reg_data = 0;
+-
+-	pm->dqm->dev->kfd2kgd->build_grace_period_packet_info(
+-			pm->dqm->dev->kgd,
+-			pm->dqm->wait_times,
+-			grace_period,
+-			&reg_offset,
+-			&reg_data);
+-
+-	if (grace_period == USE_DEFAULT_GRACE_PERIOD)
+-		reg_data = pm->dqm->wait_times;
+-
+-	packet = (struct pm4_mec_write_data_mmio *)buffer;
+-	memset(buffer, 0, sizeof(struct pm4_mec_write_data_mmio));
+-
+-	packet->header.u32All = pm_build_pm4_header(IT_WRITE_DATA,
+-			sizeof(struct pm4_mec_write_data_mmio));
+-
+-	packet->bitfields2.dst_sel  = dst_sel___write_data__mem_mapped_register;
+-	packet->bitfields2.addr_incr =
+-		addr_incr___write_data__do_not_increment_address;
+-
+-	packet->bitfields3.dst_mmreg_addr = reg_offset;
+-
+-	packet->data = reg_data;
+-
+-	return 0;
+-}
+-static int pm_unmap_queues_v10(struct packet_manager *pm, uint32_t *buffer,
+-			enum kfd_queue_type type,
+-			enum kfd_unmap_queues_filter filter,
+-			uint32_t filter_param, bool reset,
+-			unsigned int sdma_engine)
+-{
+-	struct pm4_mes_unmap_queues *packet;
+-
+-	packet = (struct pm4_mes_unmap_queues *)buffer;
+-	memset(buffer, 0, sizeof(struct pm4_mes_unmap_queues));
+-
+-	packet->header.u32All = pm_build_pm4_header(IT_UNMAP_QUEUES,
+-					sizeof(struct pm4_mes_unmap_queues));
+-	switch (type) {
+-	case KFD_QUEUE_TYPE_COMPUTE:
+-	case KFD_QUEUE_TYPE_DIQ:
+-		packet->bitfields2.engine_sel =
+-			engine_sel__mes_unmap_queues__compute;
+-		break;
+-	case KFD_QUEUE_TYPE_SDMA:
+-	case KFD_QUEUE_TYPE_SDMA_XGMI:
+-		packet->bitfields2.engine_sel =
+-			engine_sel__mes_unmap_queues__sdma0 + sdma_engine;
+-		break;
+-	default:
+-		WARN(1, "queue type %d\n", type);
+-		break;
+-	}
+-
+-	if (reset)
+-		packet->bitfields2.action =
+-			action__mes_unmap_queues__reset_queues;
+-	else
+-		packet->bitfields2.action =
+-			action__mes_unmap_queues__preempt_queues;
+-
+-	switch (filter) {
+-	case KFD_UNMAP_QUEUES_FILTER_SINGLE_QUEUE:
+-		packet->bitfields2.queue_sel =
+-			queue_sel__mes_unmap_queues__perform_request_on_specified_queues;
+-		packet->bitfields2.num_queues = 1;
+-		packet->bitfields3b.doorbell_offset0 = filter_param;
+-		break;
+-	case KFD_UNMAP_QUEUES_FILTER_BY_PASID:
+-		packet->bitfields2.queue_sel =
+-			queue_sel__mes_unmap_queues__perform_request_on_pasid_queues;
+-		packet->bitfields3a.pasid = filter_param;
+-		break;
+-	case KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES:
+-		packet->bitfields2.queue_sel =
+-			queue_sel__mes_unmap_queues__unmap_all_queues;
+-		break;
+-	case KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES:
+-		/* in this case, we do not preempt static queues */
+-		packet->bitfields2.queue_sel =
+-			queue_sel__mes_unmap_queues__unmap_all_non_static_queues;
+-		break;
+-	default:
+-		WARN(1, "filter %d\n", filter);
+-		break;
+-	}
+-
+-	return 0;
+-
+-}
+-
+-static int pm_query_status_v10(struct packet_manager *pm, uint32_t *buffer,
+-			uint64_t fence_address,	uint32_t fence_value)
+-{
+-	struct pm4_mes_query_status *packet;
+-
+-	packet = (struct pm4_mes_query_status *)buffer;
+-	memset(buffer, 0, sizeof(struct pm4_mes_query_status));
+-
+-
+-	packet->header.u32All = pm_build_pm4_header(IT_QUERY_STATUS,
+-					sizeof(struct pm4_mes_query_status));
+-
+-	packet->bitfields2.context_id = 0;
+-	packet->bitfields2.interrupt_sel =
+-			interrupt_sel__mes_query_status__completion_status;
+-	packet->bitfields2.command =
+-			command__mes_query_status__fence_only_after_write_ack;
+-
+-	packet->addr_hi = upper_32_bits((uint64_t)fence_address);
+-	packet->addr_lo = lower_32_bits((uint64_t)fence_address);
+-	packet->data_hi = upper_32_bits((uint64_t)fence_value);
+-	packet->data_lo = lower_32_bits((uint64_t)fence_value);
+-
+-	return 0;
+-}
+-
+-const struct packet_manager_funcs kfd_v10_pm_funcs = {
+-	.map_process		= pm_map_process_v10,
+-	.runlist		= pm_runlist_v10,
+-	.set_resources		= pm_set_resources_vi,
+-	.map_queues		= pm_map_queues_v10,
+-	.unmap_queues		= pm_unmap_queues_v10,
+-	.set_grace_period	= pm_set_grace_period_v10,
+-	.query_status		= pm_query_status_v10,
+-	.release_mem		= NULL,
+-	.map_process_size	= sizeof(struct pm4_mes_map_process),
+-	.runlist_size		= sizeof(struct pm4_mes_runlist),
+-	.set_resources_size	= sizeof(struct pm4_mes_set_resources),
+-	.map_queues_size	= sizeof(struct pm4_mes_map_queues),
+-	.unmap_queues_size	= sizeof(struct pm4_mes_unmap_queues),
+-	.set_grace_period_size	= sizeof(struct pm4_mec_write_data_mmio),
+-	.query_status_size	= sizeof(struct pm4_mes_query_status),
+-	.release_mem_size	= 0,
+-};
+-
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+index 42aefc976838..a3d0b4cf16c6 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+@@ -25,6 +25,7 @@
+ #include "kfd_device_queue_manager.h"
+ #include "kfd_pm4_headers_ai.h"
+ #include "kfd_pm4_opcodes.h"
++#include "gc/gc_10_1_0_sh_mask.h"
+ 
+ static bool initialize_v9(struct kernel_queue *kq, struct kfd_dev *dev,
+ 			enum kfd_queue_type type, unsigned int queue_size)
+@@ -91,10 +92,17 @@ static int pm_map_process_v9(struct packet_manager *pm,
+ 
+ 	packet->sh_mem_config = qpd->sh_mem_config;
+ 	packet->sh_mem_bases = qpd->sh_mem_bases;
+-	packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
+-	packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8);
+-	packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
+-	packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);
++	if (qpd->tba_addr) {
++		packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
++		/* On GFX9, unlike GFX10, bit TRAP_EN of SQ_SHADER_TBA_HI is
++		 * not defined, so setting it won't do any harm.
++		 */
++		packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8)
++				| 1 << SQ_SHADER_TBA_HI__TRAP_EN__SHIFT;
++
++		packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
++		packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);
++	}
+ 
+ 	packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
+ 	packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+index 13bd55a92fd6..cbf83ed96dad 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+@@ -243,12 +243,10 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
+ 	case CHIP_RAVEN:
+ 	case CHIP_RENOIR:
+ 	case CHIP_ARCTURUS:
+-		pm->pmf = &kfd_v9_pm_funcs;
+-		break;
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI12:
+ 	case CHIP_NAVI14:
+-		pm->pmf = &kfd_v10_pm_funcs;
++		pm->pmf = &kfd_v9_pm_funcs;
+ 		break;
+ 	default:
+ 		WARN(1, "Unexpected ASIC family %u",
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index e7913212c1f6..829c7506539d 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -1125,7 +1125,6 @@ struct packet_manager_funcs {
+ 
+ extern const struct packet_manager_funcs kfd_vi_pm_funcs;
+ extern const struct packet_manager_funcs kfd_v9_pm_funcs;
+-extern const struct packet_manager_funcs kfd_v10_pm_funcs;
+ 
+ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm);
+ void pm_uninit(struct packet_manager *pm);
+@@ -1146,8 +1145,6 @@ int pm_update_grace_period(struct packet_manager *pm, uint32_t grace_period);
+ 
+ /* Following PM funcs can be shared among VI and AI */
+ unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size);
+-int pm_set_resources_vi(struct packet_manager *pm, uint32_t *buffer,
+-				struct scheduling_resources *res);
+ void kfd_pm_func_init_v10(struct packet_manager *pm, uint16_t fw_ver);
+ 
+ uint64_t kfd_get_number_elems(struct kfd_dev *kfd);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4403-drm-amdkfd-Simplify-the-mmap-offset-related-bit-oper.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4403-drm-amdkfd-Simplify-the-mmap-offset-related-bit-oper.patch
new file mode 100644
index 00000000..e778fb85
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4403-drm-amdkfd-Simplify-the-mmap-offset-related-bit-oper.patch
@@ -0,0 +1,130 @@
+From b5e2e678c6ca3126e8f9fdf7b1d2a1ceb58438d5 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Tue, 15 Jan 2019 18:11:32 -0500
+Subject: [PATCH 4403/4736] drm/amdkfd: Simplify the mmap offset related bit
+ operations
+
+The new code uses straightforward bit shifts and thus has better readability.
+
+Change-Id: I0c1f7cca7e24ddb7b4ffe1cb0fa71943828ae373
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 17 +++++++----------
+ drivers/gpu/drm/amd/amdkfd/kfd_events.c  |  1 -
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h    |  9 +++------
+ drivers/gpu/drm/amd/amdkfd/kfd_process.c |  3 +--
+ 4 files changed, 11 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index 22f7aa576c7e..59bfbed3c000 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -320,7 +320,6 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
+ 	/* Return gpu_id as doorbell offset for mmap usage */
+ 	args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL;
+ 	args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id);
+-	args->doorbell_offset <<= PAGE_SHIFT;
+ 	if (KFD_IS_SOC15(dev->device_info->asic_family))
+ 		/* On SOC15 ASICs, doorbell allocation must be
+ 		 * per-device, and independent from the per-process
+@@ -1348,10 +1347,9 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
+ 	/* MMIO is mapped through kfd device
+ 	 * Generate a kfd mmap offset
+ 	 */
+-	if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
+-		args->mmap_offset = KFD_MMAP_TYPE_MMIO | KFD_MMAP_GPU_ID(args->gpu_id);
+-		args->mmap_offset <<= PAGE_SHIFT;
+-	}
++	if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)
++		args->mmap_offset = KFD_MMAP_TYPE_MMIO
++					| KFD_MMAP_GPU_ID(args->gpu_id);
+ 
+ 	return 0;
+ 
+@@ -3094,20 +3092,19 @@ static int kfd_mmap(struct file *filp, struct vm_area_struct *vma)
+ {
+ 	struct kfd_process *process;
+ 	struct kfd_dev *dev = NULL;
+-	unsigned long vm_pgoff;
++	unsigned long mmap_offset;
+ 	unsigned int gpu_id;
+ 
+ 	process = kfd_get_process(current);
+ 	if (IS_ERR(process))
+ 		return PTR_ERR(process);
+ 
+-	vm_pgoff = vma->vm_pgoff;
+-	vma->vm_pgoff = KFD_MMAP_OFFSET_VALUE_GET(vm_pgoff);
+-	gpu_id = KFD_MMAP_GPU_ID_GET(vm_pgoff);
++	mmap_offset = vma->vm_pgoff << PAGE_SHIFT;
++	gpu_id = KFD_MMAP_GET_GPU_ID(mmap_offset);
+ 	if (gpu_id)
+ 		dev = kfd_device_by_id(gpu_id);
+ 
+-	switch (vm_pgoff & KFD_MMAP_TYPE_MASK) {
++	switch (mmap_offset & KFD_MMAP_TYPE_MASK) {
+ 	case KFD_MMAP_TYPE_DOORBELL:
+ 		if (!dev)
+ 			return -ENODEV;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+index 6baf78c9245f..ebab277c9814 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+@@ -346,7 +346,6 @@ int kfd_event_create(struct file *devkfd, struct kfd_process *p,
+ 		ret = create_signal_event(devkfd, p, ev);
+ 		if (!ret) {
+ 			*event_page_offset = KFD_MMAP_TYPE_EVENTS;
+-			*event_page_offset <<= PAGE_SHIFT;
+ 			*event_slot_index = ev->event_id;
+ 		}
+ 		break;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index 829c7506539d..107b23187009 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -62,24 +62,21 @@
+  * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these
+  *  defines are w.r.t to PAGE_SIZE
+  */
+-#define KFD_MMAP_TYPE_SHIFT	(62 - PAGE_SHIFT)
++#define KFD_MMAP_TYPE_SHIFT	62
+ #define KFD_MMAP_TYPE_MASK	(0x3ULL << KFD_MMAP_TYPE_SHIFT)
+ #define KFD_MMAP_TYPE_DOORBELL	(0x3ULL << KFD_MMAP_TYPE_SHIFT)
+ #define KFD_MMAP_TYPE_EVENTS	(0x2ULL << KFD_MMAP_TYPE_SHIFT)
+ #define KFD_MMAP_TYPE_RESERVED_MEM	(0x1ULL << KFD_MMAP_TYPE_SHIFT)
+ #define KFD_MMAP_TYPE_MMIO	(0x0ULL << KFD_MMAP_TYPE_SHIFT)
+ 
+-#define KFD_MMAP_GPU_ID_SHIFT (46 - PAGE_SHIFT)
++#define KFD_MMAP_GPU_ID_SHIFT 46
+ #define KFD_MMAP_GPU_ID_MASK (((1ULL << KFD_GPU_ID_HASH_WIDTH) - 1) \
+ 				<< KFD_MMAP_GPU_ID_SHIFT)
+ #define KFD_MMAP_GPU_ID(gpu_id) ((((uint64_t)gpu_id) << KFD_MMAP_GPU_ID_SHIFT)\
+ 				& KFD_MMAP_GPU_ID_MASK)
+-#define KFD_MMAP_GPU_ID_GET(offset)    ((offset & KFD_MMAP_GPU_ID_MASK) \
++#define KFD_MMAP_GET_GPU_ID(offset)    ((offset & KFD_MMAP_GPU_ID_MASK) \
+ 				>> KFD_MMAP_GPU_ID_SHIFT)
+ 
+-#define KFD_MMAP_OFFSET_VALUE_MASK	(0x3FFFFFFFFFFFULL >> PAGE_SHIFT)
+-#define KFD_MMAP_OFFSET_VALUE_GET(offset) (offset & KFD_MMAP_OFFSET_VALUE_MASK)
+-
+ /*
+  * When working with cp scheduler we should assign the HIQ manually or via
+  * the amdgpu driver to a fixed hqd slot, here are the fixed HIQ hqd slot
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+index 3f061264bae9..d78c36ba54e3 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+@@ -616,8 +616,7 @@ static int kfd_process_init_cwsr_apu(struct kfd_process *p, struct file *filep)
+ 		if (!dev->cwsr_enabled || qpd->cwsr_kaddr || qpd->cwsr_base)
+ 			continue;
+ 
+-		offset = (KFD_MMAP_TYPE_RESERVED_MEM | KFD_MMAP_GPU_ID(dev->id))
+-			<< PAGE_SHIFT;
++		offset = KFD_MMAP_TYPE_RESERVED_MEM | KFD_MMAP_GPU_ID(dev->id);
+ 		qpd->tba_addr = (int64_t)vm_mmap(filep, 0,
+ 			KFD_CWSR_TBA_TMA_SIZE, PROT_READ | PROT_EXEC,
+ 			MAP_SHARED, offset);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4404-drm-amd-powerplay-dynamically-disable-ds-and-ulv-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4404-drm-amd-powerplay-dynamically-disable-ds-and-ulv-for.patch
new file mode 100644
index 00000000..d01a6942
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4404-drm-amd-powerplay-dynamically-disable-ds-and-ulv-for.patch
@@ -0,0 +1,130 @@
+From 502b21ae7fe7e687739a5a14b15e738565a061ce Mon Sep 17 00:00:00 2001
+From: Kenneth Feng <kenneth.feng@amd.com>
+Date: Fri, 8 Nov 2019 13:20:30 +0800
+Subject: [PATCH 4404/4736] drm/amd/powerplay: dynamically disable ds and ulv
+ for compute
+
+This is to improve the performance in the compute mode
+for vega10. For example, the original performance for a rocm
+bandwidth test: 2G internal GPU copy, is about 99GB/s.
+With the idle power features disabled dynamically, the porformance
+is promoted to about 215GB/s.
+
+Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amd_powerplay.c |  8 +++
+ .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c    | 55 +++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/inc/hwmgr.h     |  2 +
+ 3 files changed, 65 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+index 031447675203..7932eb163a00 100644
+--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+@@ -969,6 +969,14 @@ static int pp_dpm_switch_power_profile(void *handle,
+ 		workload = hwmgr->workload_setting[index];
+ 	}
+ 
++	if (type == PP_SMC_POWER_PROFILE_COMPUTE &&
++		hwmgr->hwmgr_func->disable_power_features_for_compute_performance) {
++			if (hwmgr->hwmgr_func->disable_power_features_for_compute_performance(hwmgr, en)) {
++				mutex_unlock(&hwmgr->smu_lock);
++				return -EINVAL;
++			}
++	}
++
+ 	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
+ 		hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
+ 	mutex_unlock(&hwmgr->smu_lock);
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+index f62e320ed43d..8d933cb7e451 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+@@ -5262,6 +5262,59 @@ static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_
+ 	return 0;
+ }
+ 
++static int vega10_disable_power_features_for_compute_performance(struct pp_hwmgr *hwmgr, bool disable)
++{
++	struct vega10_hwmgr *data = hwmgr->backend;
++	uint32_t feature_mask = 0;
++
++	if (disable) {
++		feature_mask |= data->smu_features[GNLD_ULV].enabled ?
++			data->smu_features[GNLD_ULV].smu_feature_bitmap : 0;
++		feature_mask |= data->smu_features[GNLD_DS_GFXCLK].enabled ?
++			data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0;
++		feature_mask |= data->smu_features[GNLD_DS_SOCCLK].enabled ?
++			data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0;
++		feature_mask |= data->smu_features[GNLD_DS_LCLK].enabled ?
++			data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
++		feature_mask |= data->smu_features[GNLD_DS_DCEFCLK].enabled ?
++			data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0;
++	} else {
++		feature_mask |= (!data->smu_features[GNLD_ULV].enabled) ?
++			data->smu_features[GNLD_ULV].smu_feature_bitmap : 0;
++		feature_mask |= (!data->smu_features[GNLD_DS_GFXCLK].enabled) ?
++			data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0;
++		feature_mask |= (!data->smu_features[GNLD_DS_SOCCLK].enabled) ?
++			data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0;
++		feature_mask |= (!data->smu_features[GNLD_DS_LCLK].enabled) ?
++			data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
++		feature_mask |= (!data->smu_features[GNLD_DS_DCEFCLK].enabled) ?
++			data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0;
++	}
++
++	if (feature_mask)
++		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
++				!disable, feature_mask),
++				"enable/disable power features for compute performance Failed!",
++				return -EINVAL);
++
++	if (disable) {
++		data->smu_features[GNLD_ULV].enabled = false;
++		data->smu_features[GNLD_DS_GFXCLK].enabled = false;
++		data->smu_features[GNLD_DS_SOCCLK].enabled = false;
++		data->smu_features[GNLD_DS_LCLK].enabled = false;
++		data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
++	} else {
++		data->smu_features[GNLD_ULV].enabled = true;
++		data->smu_features[GNLD_DS_GFXCLK].enabled = true;
++		data->smu_features[GNLD_DS_SOCCLK].enabled = true;
++		data->smu_features[GNLD_DS_LCLK].enabled = true;
++		data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
++	}
++
++	return 0;
++
++}
++
+ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
+ 	.backend_init = vega10_hwmgr_backend_init,
+ 	.backend_fini = vega10_hwmgr_backend_fini,
+@@ -5328,6 +5381,8 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
+         .get_ppfeature_status = vega10_get_ppfeature_status,
+         .set_ppfeature_status = vega10_set_ppfeature_status,
+ 	.set_mp1_state = vega10_set_mp1_state,
++	.disable_power_features_for_compute_performance =
++			vega10_disable_power_features_for_compute_performance,
+ };
+ 
+ int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+index 40403bc76f1b..af977675fd33 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+@@ -357,6 +357,8 @@ struct pp_hwmgr_func {
+ 	int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire);
+ 	int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state);
+ 	int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);
++	int (*disable_power_features_for_compute_performance)(struct pp_hwmgr *hwmgr,
++					bool disable);
+ };
+ 
+ struct pp_table_func {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4405-drm-amdgpu-powerplay-fix-AVFS-handling-with-custom-p.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4405-drm-amdgpu-powerplay-fix-AVFS-handling-with-custom-p.patch
new file mode 100644
index 00000000..eda0baf2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4405-drm-amdgpu-powerplay-fix-AVFS-handling-with-custom-p.patch
@@ -0,0 +1,37 @@
+From 4c9392cb5170440181dddc15d057ef54dd416735 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 7 Nov 2019 09:50:18 -0500
+Subject: [PATCH 4405/4736] drm/amdgpu/powerplay: fix AVFS handling with custom
+ powerplay table
+
+When a custom powerplay table is provided, we need to update
+the OD VDDC flag to avoid AVFS being enabled when it shouldn't be.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205393
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+index 8d933cb7e451..1f82c1f91247 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+@@ -3688,6 +3688,13 @@ static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
+ 	PP_ASSERT_WITH_CODE(!result,
+ 			"Failed to upload PPtable!", return result);
+ 
++	/*
++	 * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag.
++	 * That effectively disables AVFS feature.
++	 */
++	if(hwmgr->hardcode_pp_table != NULL)
++		data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
++
+ 	vega10_update_avfs(hwmgr);
+ 
+ 	/*
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4406-drm-amd-display-remove-duplicated-assignment-to-grph.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4406-drm-amd-display-remove-duplicated-assignment-to-grph.patch
new file mode 100644
index 00000000..9e18b30b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4406-drm-amd-display-remove-duplicated-assignment-to-grph.patch
@@ -0,0 +1,33 @@
+From 243643406675ec9c987f47c9f6a4e0b946a75e59 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Fri, 8 Nov 2019 14:45:27 +0000
+Subject: [PATCH 4406/4736] drm/amd/display: remove duplicated assignment to
+ grph_obj_type
+
+Variable grph_obj_type is being assigned twice, one of these is
+redundant so remove it.
+
+Addresses-Coverity: ("Evaluation order violation")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+index 7d941b3802a6..6d5774144054 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+@@ -365,8 +365,7 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *
+ 			router.ddc_valid = false;
+ 			router.cd_valid = false;
+ 			for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
+-				uint8_t grph_obj_type=
+-				grph_obj_type =
++				uint8_t grph_obj_type =
+ 				    (le16_to_cpu(path->usGraphicObjIds[j]) &
+ 				     OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4407-drm-amd-display-remove-redundant-variable-status.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4407-drm-amd-display-remove-redundant-variable-status.patch
new file mode 100644
index 00000000..2b163284
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4407-drm-amd-display-remove-redundant-variable-status.patch
@@ -0,0 +1,43 @@
+From 11b697a279f0db35ec688c84d49573b70c8183f6 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Fri, 8 Nov 2019 16:29:45 +0000
+Subject: [PATCH 4407/4736] drm/amd/display: remove redundant variable status
+
+Variable status is redundant, it is being initialized with a value
+that is over-written later and this is being returned immediately
+after the assignment.  Clean up the code by removing status and
+just returning the value returned from the call to function
+dc->hwss.dmdata_status_done.
+
+Addresses-Coverity: ("Unused value")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+index 4431cc6000a1..2e03a1120bee 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+@@ -567,7 +567,6 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
+ {
+-	bool status = true;
+ 	struct pipe_ctx *pipe = NULL;
+ 	int i;
+ 
+@@ -583,8 +582,7 @@ bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
+ 	if (i == MAX_PIPES)
+ 		return true;
+ 
+-	status = dc->hwss.dmdata_status_done(pipe);
+-	return status;
++	return dc->hwss.dmdata_status_done(pipe);
+ }
+ 
+ bool dc_stream_set_dynamic_metadata(struct dc *dc,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4408-drm-amdgpu-avoid-upload-corrupted-ta-ucode-to-psp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4408-drm-amdgpu-avoid-upload-corrupted-ta-ucode-to-psp.patch
new file mode 100644
index 00000000..03af0fcd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4408-drm-amdgpu-avoid-upload-corrupted-ta-ucode-to-psp.patch
@@ -0,0 +1,79 @@
+From 90813900c001e61af7a8f453168cb74114aba154 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 11 Nov 2019 12:26:36 +0800
+Subject: [PATCH 4408/4736] drm/amdgpu: avoid upload corrupted ta ucode to psp
+
+xgmi, ras, hdcp and dtm ta are actually separated ucode and
+need to handled case by case to upload to psp.
+
+We support the case that ta binary have one or multiple of
+them built-in. As a result, the driver should check each ta
+binariy's availablity before decide to upload them to psp.
+
+In the terminate (unload) case, the driver will check the
+context readiness before perform unload activity. It's fine
+to keep it as is.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 22 +++++++++++++++++++++-
+ 1 file changed, 21 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index a33d1ed6a096..2b513e41ed3c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -569,7 +569,9 @@ static int psp_xgmi_initialize(struct psp_context *psp)
+ 	struct ta_xgmi_shared_memory *xgmi_cmd;
+ 	int ret;
+ 
+-	if (!psp->adev->psp.ta_fw)
++	if (!psp->adev->psp.ta_fw ||
++	    !psp->adev->psp.ta_xgmi_ucode_size ||
++	    !psp->adev->psp.ta_xgmi_start_addr)
+ 		return -ENOENT;
+ 
+ 	if (!psp->xgmi_context.initialized) {
+@@ -779,6 +781,12 @@ static int psp_ras_initialize(struct psp_context *psp)
+ {
+ 	int ret;
+ 
++	if (!psp->adev->psp.ta_ras_ucode_size ||
++	    !psp->adev->psp.ta_ras_start_addr) {
++		dev_warn(psp->adev->dev, "RAS: ras ta ucode is not available\n");
++		return 0;
++	}
++
+ 	if (!psp->ras.ras_initialized) {
+ 		ret = psp_ras_init_shared_buf(psp);
+ 		if (ret)
+@@ -868,6 +876,12 @@ static int psp_hdcp_initialize(struct psp_context *psp)
+ {
+ 	int ret;
+ 
++	if (!psp->adev->psp.ta_hdcp_ucode_size ||
++	    !psp->adev->psp.ta_hdcp_start_addr) {
++		dev_warn(psp->adev->dev, "HDCP: hdcp ta ucode is not available\n");
++		return 0;
++	}
++
+ 	if (!psp->hdcp_context.hdcp_initialized) {
+ 		ret = psp_hdcp_init_shared_buf(psp);
+ 		if (ret)
+@@ -1041,6 +1055,12 @@ static int psp_dtm_initialize(struct psp_context *psp)
+ {
+ 	int ret;
+ 
++	if (!psp->adev->psp.ta_dtm_ucode_size ||
++	    !psp->adev->psp.ta_dtm_start_addr) {
++		dev_warn(psp->adev->dev, "DTM: dtm ta ucode is not available\n");
++		return 0;
++	}
++
+ 	if (!psp->dtm_context.dtm_initialized) {
+ 		ret = psp_dtm_init_shared_buf(psp);
+ 		if (ret)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4409-drm-amdgpu-powerplay-smu7-fix-AVFS-handling-with-cus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4409-drm-amdgpu-powerplay-smu7-fix-AVFS-handling-with-cus.patch
new file mode 100644
index 00000000..193572a9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4409-drm-amdgpu-powerplay-smu7-fix-AVFS-handling-with-cus.patch
@@ -0,0 +1,37 @@
+From ae65cef2826c909d5652a4afe102a5075a2f97c8 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 8 Nov 2019 11:15:17 -0500
+Subject: [PATCH 4409/4736] drm/amdgpu/powerplay/smu7: fix AVFS handling with
+ custom powerplay table
+
+When a custom powerplay table is provided, we need to update
+the OD VDDC flag to avoid AVFS being enabled when it shouldn't be.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205393
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+index 80bfdf178892..570625efce9d 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -3968,6 +3968,13 @@ static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
+ 			"Failed to populate and upload SCLK MCLK DPM levels!",
+ 			result = tmp_result);
+ 
++	/*
++	 * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag.
++	 * That effectively disables AVFS feature.
++	 */
++	if (hwmgr->hardcode_pp_table != NULL)
++		data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
++
+ 	tmp_result = smu7_update_avfs(hwmgr);
+ 	PP_ASSERT_WITH_CODE((0 == tmp_result),
+ 			"Failed to update avfs voltages!",
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4410-drm-amd-display-remove-duplicated-comparison-express.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4410-drm-amd-display-remove-duplicated-comparison-express.patch
new file mode 100644
index 00000000..827e9eab
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4410-drm-amd-display-remove-duplicated-comparison-express.patch
@@ -0,0 +1,33 @@
+From 72e75e071d23d87d981018d655abcd81b24881b5 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Sat, 9 Nov 2019 15:49:21 +0000
+Subject: [PATCH 4410/4736] drm/amd/display: remove duplicated comparison
+ expression
+
+There is comparison expression that is duplicated and hence one
+of the expressions can be removed.  Remove it.
+
+Addresses-Coverity: ("Same on both sides")
+Fixes: 12e2b2d4c65f ("drm/amd/display: add dcc programming for dual plane")
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index a0ad1796af08..eda0d04f6ae5 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1506,7 +1506,6 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
+ 	}
+ 
+ 	if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
+-			|| u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
+ 			|| u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
+ 		update_flags->bits.plane_size_change = 1;
+ 		elevate_update_type(&update_type, UPDATE_TYPE_MED);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4411-drm-amd-powerplay-remove-set-but-not-used-variable-v.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4411-drm-amd-powerplay-remove-set-but-not-used-variable-v.patch
new file mode 100644
index 00000000..0ba4f0d6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4411-drm-amd-powerplay-remove-set-but-not-used-variable-v.patch
@@ -0,0 +1,66 @@
+From 096b7d05ab990ded5a3aca08430cbd3274c23c5e Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Mon, 11 Nov 2019 11:45:55 +0800
+Subject: [PATCH 4411/4736] drm/amd/powerplay: remove set but not used variable
+ 'vbios_version', 'data'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c: In function smu7_check_mc_firmware:
+drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c:4215:11: warning: variable vbios_version set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c: In function smu7_get_performance_level:
+drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c:5054:21: warning: variable data set but not used [-Wunused-but-set-variable]
+
+'vbios_version' is introduced by commit 599a7e9fe1b6 ("drm/amd/powerplay:
+implement smu7 hwmgr to manager asics with smu ip version 7."),
+but never used, so remove it.
+
+'data' is introduced by commit f688b614b643 ("drm/amd/pp:
+Implement get_performance_level for legacy dgpu"), but never used,
+so remove it.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+index 570625efce9d..d3c3b3512a16 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -4224,7 +4224,6 @@ static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr)
+ {
+ 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ 
+-	uint32_t vbios_version;
+ 	uint32_t tmp;
+ 
+ 	/* Read MC indirect register offset 0x9F bits [3:0] to see
+@@ -4233,7 +4232,6 @@ static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr)
+ 	 */
+ 
+ 	smu7_get_mc_microcode_version(hwmgr);
+-	vbios_version = hwmgr->microcode_version_info.MC & 0xf;
+ 
+ 	data->need_long_memory_training = false;
+ 
+@@ -5063,13 +5061,11 @@ static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw
+ 				PHM_PerformanceLevel *level)
+ {
+ 	const struct smu7_power_state *ps;
+-	struct smu7_hwmgr *data;
+ 	uint32_t i;
+ 
+ 	if (level == NULL || hwmgr == NULL || state == NULL)
+ 		return -EINVAL;
+ 
+-	data = hwmgr->backend;
+ 	ps = cast_const_phw_smu7_power_state(state);
+ 
+ 	i = index > ps->performance_level_count - 1 ?
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4412-drm-amd-powerplay-remove-set-but-not-used-variable-d.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4412-drm-amd-powerplay-remove-set-but-not-used-variable-d.patch
new file mode 100644
index 00000000..d58156f3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4412-drm-amd-powerplay-remove-set-but-not-used-variable-d.patch
@@ -0,0 +1,44 @@
+From a4d708c33bb4375b21b13c9765fe9c8d82946d1d Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Mon, 11 Nov 2019 11:45:56 +0800
+Subject: [PATCH 4412/4736] drm/amd/powerplay: remove set but not used variable
+ 'data'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c: In function vega10_get_performance_level:
+drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c:5217:23: warning: variable data set but not used [-Wunused-but-set-variable]
+
+'data' is introduced by commit f688b614b643 ("drm/amd/pp:
+Implement get_performance_level for legacy dgpu"), but never used,
+so remove it.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+index 1f82c1f91247..b8cb492102ff 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+@@ -5251,13 +5251,11 @@ static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_
+ 				PHM_PerformanceLevel *level)
+ {
+ 	const struct vega10_power_state *ps;
+-	struct vega10_hwmgr *data;
+ 	uint32_t i;
+ 
+ 	if (level == NULL || hwmgr == NULL || state == NULL)
+ 		return -EINVAL;
+ 
+-	data = hwmgr->backend;
+ 	ps = cast_const_phw_vega10_power_state(state);
+ 
+ 	i = index > ps->performance_level_count - 1 ?
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4413-drm-amd-display-Use-static-const-not-const-static.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4413-drm-amd-display-Use-static-const-not-const-static.patch
new file mode 100644
index 00000000..9619d40c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4413-drm-amd-display-Use-static-const-not-const-static.patch
@@ -0,0 +1,30 @@
+From 8b238f08483fbae1b1c97c50c5af4362efab2527 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Mon, 11 Nov 2019 17:33:13 +0800
+Subject: [PATCH 4413/4736] drm/amd/display: Use static const, not const static
+
+Move the static keyword to the front of declarations.
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index eda0d04f6ae5..9e600d3e2fd8 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -70,7 +70,7 @@
+ #define DC_LOGGER \
+ 	dc->ctx->logger
+ 
+-const static char DC_BUILD_ID[] = "production-build";
++static const char DC_BUILD_ID[] = "production-build";
+ 
+ /**
+  * DOC: Overview
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4414-drm-amd-powerplay-remove-set-but-not-used-variable-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4414-drm-amd-powerplay-remove-set-but-not-used-variable-t.patch
new file mode 100644
index 00000000..5278b331
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4414-drm-amd-powerplay-remove-set-but-not-used-variable-t.patch
@@ -0,0 +1,66 @@
+From b4bb7137fa42f4188a897f985455cb46f7b7c9df Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Mon, 11 Nov 2019 12:09:28 +0800
+Subject: [PATCH 4414/4736] drm/amd/powerplay: remove set but not used variable
+ 'threshold', 'state'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c: In function fiji_populate_single_graphic_level:
+drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c:943:11: warning: variable threshold set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c: In function fiji_populate_memory_timing_parameters:
+drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c:1504:8: warning: variable state set but not used [-Wunused-but-set-variable]
+
+They are introduced by commit 2e112b4ae3ba ("drm/amd/pp:
+remove fiji_smc/smumgr split."), but never used,
+so remove it.
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+index da025b1d302d..32ebb383c456 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+@@ -940,7 +940,7 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
+ {
+ 	int result;
+ 	/* PP_Clocks minClocks; */
+-	uint32_t threshold, mvdd;
++	uint32_t mvdd;
+ 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ 	struct phm_ppt_v1_information *table_info =
+ 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
+@@ -973,8 +973,6 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
+ 	level->VoltageDownHyst = 0;
+ 	level->PowerThrottle = 0;
+ 
+-	threshold = clock * data->fast_watermark_threshold / 100;
+-
+ 	data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
+ 
+ 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
+@@ -1501,7 +1499,7 @@ static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
+ 	uint32_t dram_timing;
+ 	uint32_t dram_timing2;
+ 	uint32_t burstTime;
+-	ULONG state, trrds, trrdl;
++	ULONG trrds, trrdl;
+ 	int result;
+ 
+ 	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
+@@ -1513,7 +1511,6 @@ static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
+ 	dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
+ 	burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
+ 
+-	state = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, STATE0);
+ 	trrds = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDS0);
+ 	trrdl = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDL0);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4415-drm-amd-display-remove-set-but-not-used-variable-ds_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4415-drm-amd-display-remove-set-but-not-used-variable-ds_.patch
new file mode 100644
index 00000000..26094873
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4415-drm-amd-display-remove-set-but-not-used-variable-ds_.patch
@@ -0,0 +1,45 @@
+From 5f27eada534da5d39a176e609504dc3776c6d827 Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Sat, 9 Nov 2019 17:37:25 +0800
+Subject: [PATCH 4415/4736] drm/amd/display: remove set but not used variable
+ 'ds_port'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c: In function dp_wa_power_up_0010FA:
+drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:2320:35: warning:
+ variable ds_port set but not used [-Wunused-but-set-variable]
+
+It is never used, so can be removed.
+
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 7d18fc1e68c6..66f59058b56d 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2924,7 +2924,6 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
+ 		int length)
+ {
+ 	int retry = 0;
+-	union dp_downstream_port_present ds_port = { 0 };
+ 
+ 	if (!link->dpcd_caps.dpcd_rev.raw) {
+ 		do {
+@@ -2937,9 +2936,6 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
+ 		} while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
+ 	}
+ 
+-	ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
+-				 DP_DPCD_REV];
+-
+ 	if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
+ 		switch (link->dpcd_caps.branch_dev_id) {
+ 		/* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4416-drm-amdgpu-navi10-implement-sclk-mclk-OD-via-pp_od_c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4416-drm-amdgpu-navi10-implement-sclk-mclk-OD-via-pp_od_c.patch
new file mode 100644
index 00000000..55d0d6bd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4416-drm-amdgpu-navi10-implement-sclk-mclk-OD-via-pp_od_c.patch
@@ -0,0 +1,274 @@
+From a3047065b91b159276dfcb41c6477fd27916c5d0 Mon Sep 17 00:00:00 2001
+From: Matt Coffin <mcoffin13@gmail.com>
+Date: Fri, 8 Nov 2019 14:28:06 -0700
+Subject: [PATCH 4416/4736] drm/amdgpu/navi10: implement sclk/mclk OD via
+ pp_od_clk_voltage
+
+[Why]
+Before this patch, there was no way to use pp_od_clk_voltage on navi
+
+[How]
+Similar to the vega20 implementation, but using the common smc_v11_0
+headers, implemented the pp_od_clk_voltage API for navi10's pptable
+implementation
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Matt Coffin <mcoffin13@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |   2 +
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 180 ++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     |  27 +++
+ 3 files changed, 209 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 36028e9d1011..0ec6ed0456e0 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -251,4 +251,6 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_
+ 
+ int smu_v11_0_override_pcie_parameters(struct smu_context *smu);
+ 
++int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 010be21bee5b..5c4c1f416f3e 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1648,10 +1648,188 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
+ 					  SMU_MSG_OverridePcieParameters,
+ 					  smu_pcie_arg);
+ 	}
++	return ret;
++}
++
++static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {
++	pr_debug("OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
++	pr_debug("OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
++	pr_debug("OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
++	pr_debug("OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
++	pr_debug("OD: UclkFmax: %d\n", od_table->UclkFmax);
++	pr_debug("OD: OverDrivePct: %d\n", od_table->OverDrivePct);
++}
++
++static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_ID feature)
++{
++	return od_table->cap[feature];
++}
++
++static int navi10_od_setting_check_range(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODSETTING_ID setting, uint32_t value)
++{
++	if (value < od_table->min[setting]) {
++		pr_warn("OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
++		return -EINVAL;
++	}
++	if (value > od_table->max[setting]) {
++		pr_warn("OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
++		return -EINVAL;
++	}
++	return 0;
++}
++
++static int navi10_setup_od_limits(struct smu_context *smu) {
++	struct smu_11_0_overdrive_table *overdrive_table = NULL;
++	struct smu_11_0_powerplay_table *powerplay_table = NULL;
++
++	if (!smu->smu_table.power_play_table) {
++		pr_err("powerplay table uninitialized!\n");
++		return -ENOENT;
++	}
++	powerplay_table = (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
++	overdrive_table = &powerplay_table->overdrive_table;
++	if (!smu->od_settings) {
++		smu->od_settings = kmemdup(overdrive_table, sizeof(struct smu_11_0_overdrive_table), GFP_KERNEL);
++	} else {
++		memcpy(smu->od_settings, overdrive_table, sizeof(struct smu_11_0_overdrive_table));
++	}
++	return 0;
++}
++
++static int navi10_set_default_od_settings(struct smu_context *smu, bool initialize) {
++	OverDriveTable_t *od_table;
++	int ret = 0;
++
++	ret = smu_v11_0_set_default_od_settings(smu, initialize, sizeof(OverDriveTable_t));
++	if (ret)
++		return ret;
++
++	if (initialize) {
++		ret = navi10_setup_od_limits(smu);
++		if (ret) {
++			pr_err("Failed to retrieve board OD limits\n");
++			return ret;
++		}
++
++	}
++
++	od_table = (OverDriveTable_t *)smu->smu_table.overdrive_table;
++	if (od_table) {
++		navi10_dump_od_table(od_table);
++	}
+ 
+ 	return ret;
+ }
+ 
++static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) {
++	int i;
++	int ret = 0;
++	struct smu_table_context *table_context = &smu->smu_table;
++	OverDriveTable_t *od_table;
++	struct smu_11_0_overdrive_table *od_settings;
++	od_table = (OverDriveTable_t *)table_context->overdrive_table;
++
++	if (!smu->od_enabled) {
++		pr_warn("OverDrive is not enabled!\n");
++		return -EINVAL;
++	}
++
++	if (!smu->od_settings) {
++		pr_err("OD board limits are not set!\n");
++		return -ENOENT;
++	}
++
++	od_settings = smu->od_settings;
++
++	switch (type) {
++	case PP_OD_EDIT_SCLK_VDDC_TABLE:
++		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS)) {
++			pr_warn("GFXCLK_LIMITS not supported!\n");
++			return -ENOTSUPP;
++		}
++		if (!table_context->overdrive_table) {
++			pr_err("Overdrive is not initialized\n");
++			return -EINVAL;
++		}
++		for (i = 0; i < size; i += 2) {
++			if (i + 2 > size) {
++				pr_info("invalid number of input parameters %d\n", size);
++				return -EINVAL;
++			}
++			switch (input[i]) {
++			case 0:
++				freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
++				freq_ptr = &od_table->GfxclkFmin;
++				if (input[i + 1] > od_table->GfxclkFmax) {
++					pr_info("GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
++						input[i + 1],
++						od_table->GfxclkFmin);
++					return -EINVAL;
++				}
++				break;
++			case 1:
++				freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
++				freq_ptr = &od_table->GfxclkFmax;
++				if (input[i + 1] < od_table->GfxclkFmin) {
++					pr_info("GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
++						input[i + 1],
++						od_table->GfxclkFmax);
++					return -EINVAL;
++				}
++				break;
++			default:
++				pr_info("Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
++				pr_info("Supported indices: [0:min,1:max]\n");
++				return -EINVAL;
++			}
++			ret = navi10_od_setting_check_range(od_settings, freq_setting, input[i + 1]);
++			if (ret)
++				return ret;
++			*freq_ptr = input[i + 1];
++		}
++		break;
++	case PP_OD_EDIT_MCLK_VDDC_TABLE:
++		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX)) {
++			pr_warn("UCLK_MAX not supported!\n");
++			return -ENOTSUPP;
++		}
++		if (size < 2) {
++			pr_info("invalid number of parameters: %d\n", size);
++			return -EINVAL;
++		}
++		if (input[0] != 1) {
++			pr_info("Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
++			pr_info("Supported indices: [1:max]\n");
++			return -EINVAL;
++		}
++		ret = navi10_od_setting_check_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
++		if (ret)
++			return ret;
++		od_table->UclkFmax = input[1];
++		break;
++	case PP_OD_COMMIT_DPM_TABLE:
++		navi10_dump_od_table(od_table);
++		ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
++		if (ret) {
++			pr_err("Failed to import overdrive table!\n");
++			return ret;
++		}
++		// no lock needed because smu_od_edit_dpm_table has it
++		ret = smu_handle_task(smu, smu->smu_dpm.dpm_level,
++			AMD_PP_TASK_READJUST_POWER_STATE,
++			false);
++		if (ret) {
++			return ret;
++		}
++		break;
++	case PP_OD_EDIT_VDDC_CURVE:
++		// TODO: implement
++		return -ENOSYS;
++	default:
++		return -ENOSYS;
++	}
++	return ret;
++}
+ 
+ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.tables_init = navi10_tables_init,
+@@ -1741,6 +1919,8 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+ 	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+ 	.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
++	.set_default_od_settings = navi10_set_default_od_settings,
++	.od_edit_dpm_table = navi10_od_edit_dpm_table,
+ };
+ 
+ void navi10_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 9ebc00a97096..13ae44ca3504 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1778,3 +1778,30 @@ int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
+ 	return ret;
+ 
+ }
++
++int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size)
++{
++	struct smu_table_context *table_context = &smu->smu_table;
++	int ret = 0;
++
++	if (initialize) {
++		if (table_context->overdrive_table) {
++			return -EINVAL;
++		}
++		table_context->overdrive_table = kzalloc(overdrive_table_size, GFP_KERNEL);
++		if (!table_context->overdrive_table) {
++			return -ENOMEM;
++		}
++		ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
++		if (ret) {
++			pr_err("Failed to export overdrive table!\n");
++			return ret;
++		}
++	}
++	ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
++	if (ret) {
++		pr_err("Failed to import overdrive table!\n");
++		return ret;
++	}
++	return ret;
++}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4417-drm-amdgpu-navi10-implement-GFXCLK_CURVE-overdrive.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4417-drm-amdgpu-navi10-implement-GFXCLK_CURVE-overdrive.patch
new file mode 100644
index 00000000..47b4cb82
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4417-drm-amdgpu-navi10-implement-GFXCLK_CURVE-overdrive.patch
@@ -0,0 +1,115 @@
+From 7151dd70272d2a08a36e518aaa4c3553567cbb0c Mon Sep 17 00:00:00 2001
+From: Matt Coffin <mcoffin13@gmail.com>
+Date: Fri, 8 Nov 2019 14:28:07 -0700
+Subject: [PATCH 4417/4736] drm/amdgpu/navi10: implement GFXCLK_CURVE overdrive
+
+[Why]
+Before this patch, there was no way to set the gfxclk voltage curve in
+the overdrive settings for navi10 through pp_od_clk_voltage
+
+[How]
+Add the required implementation to navi10's ppt dpm table editing
+implementation, similar to the vega20 implementation and interface.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Matt Coffin <mcoffin13@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 60 +++++++++++++++++++++-
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.h |  2 +
+ 2 files changed, 60 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 5c4c1f416f3e..c1690052538f 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1727,6 +1727,8 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL
+ 	struct smu_table_context *table_context = &smu->smu_table;
+ 	OverDriveTable_t *od_table;
+ 	struct smu_11_0_overdrive_table *od_settings;
++	enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
++	uint16_t *freq_ptr, *voltage_ptr;
+ 	od_table = (OverDriveTable_t *)table_context->overdrive_table;
+ 
+ 	if (!smu->od_enabled) {
+@@ -1823,8 +1825,62 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL
+ 		}
+ 		break;
+ 	case PP_OD_EDIT_VDDC_CURVE:
+-		// TODO: implement
+-		return -ENOSYS;
++		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE)) {
++			pr_warn("GFXCLK_CURVE not supported!\n");
++			return -ENOTSUPP;
++		}
++		if (size < 3) {
++			pr_info("invalid number of parameters: %d\n", size);
++			return -EINVAL;
++		}
++		if (!od_table) {
++			pr_info("Overdrive is not initialized\n");
++			return -EINVAL;
++		}
++
++		switch (input[0]) {
++		case 0:
++			freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
++			voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
++			freq_ptr = &od_table->GfxclkFreq1;
++			voltage_ptr = &od_table->GfxclkVolt1;
++			break;
++		case 1:
++			freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
++			voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
++			freq_ptr = &od_table->GfxclkFreq2;
++			voltage_ptr = &od_table->GfxclkVolt2;
++			break;
++		case 2:
++			freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
++			voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
++			freq_ptr = &od_table->GfxclkFreq3;
++			voltage_ptr = &od_table->GfxclkVolt3;
++			break;
++		default:
++			pr_info("Invalid VDDC_CURVE index: %ld\n", input[0]);
++			pr_info("Supported indices: [0, 1, 2]\n");
++			return -EINVAL;
++		}
++		ret = navi10_od_setting_check_range(od_settings, freq_setting, input[1]);
++		if (ret)
++			return ret;
++		// Allow setting zero to disable the OverDrive VDDC curve
++		if (input[2] != 0) {
++			ret = navi10_od_setting_check_range(od_settings, voltage_setting, input[2]);
++			if (ret)
++				return ret;
++			*freq_ptr = input[1];
++			*voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
++			pr_debug("OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
++		} else {
++			// If setting 0, disable all voltage curve settings
++			od_table->GfxclkVolt1 = 0;
++			od_table->GfxclkVolt2 = 0;
++			od_table->GfxclkVolt3 = 0;
++		}
++		navi10_dump_od_table(od_table);
++		break;
+ 	default:
+ 		return -ENOSYS;
+ 	}
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+index a37e37c5f105..fd6dda1a67a1 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+@@ -33,6 +33,8 @@
+ #define NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK     (1717)
+ #define NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK      (1448)
+ 
++#define NAVI10_VOLTAGE_SCALE (4)
++
+ extern void navi10_set_ppt_funcs(struct smu_context *smu);
+ 
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4418-drm-amdgpu-navi10-Implement-od-clk-printing.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4418-drm-amdgpu-navi10-Implement-od-clk-printing.patch
new file mode 100644
index 00000000..7762cefb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4418-drm-amdgpu-navi10-Implement-od-clk-printing.patch
@@ -0,0 +1,115 @@
+From db1efd8ead62db29d93e7ef8b8bb24069b0395b6 Mon Sep 17 00:00:00 2001
+From: Matt Coffin <mcoffin13@gmail.com>
+Date: Fri, 8 Nov 2019 14:28:08 -0700
+Subject: [PATCH 4418/4736] drm/amdgpu/navi10: Implement od clk printing
+
+[Why]
+Before this patch, navi10 overdrive settings could not be printed via
+pp_od_clk_voltage
+
+[How]
+Implement printing for the overdrive settings for the following clocks
+in navi10's ppt print_clk_levels implementation:
+
+* SMU_OD_SCLK
+* SMU_OD_MCLK
+* SMU_OD_VDDC_CURVE
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Matt Coffin <mcoffin13@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 56 ++++++++++++++++++++--
+ 1 file changed, 51 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index c1690052538f..5c6ffbd0d884 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -690,13 +690,25 @@ static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu
+ 	return dpm_desc->SnapToDiscrete == 0 ? true : false;
+ }
+ 
++static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_ID feature)
++{
++	return od_table->cap[feature];
++}
++
++
+ static int navi10_print_clk_levels(struct smu_context *smu,
+ 			enum smu_clk_type clk_type, char *buf)
+ {
++	OverDriveTable_t *od_table;
++	struct smu_11_0_overdrive_table *od_settings;
++	uint16_t *curve_settings;
+ 	int i, size = 0, ret = 0;
+ 	uint32_t cur_value = 0, value = 0, count = 0;
+ 	uint32_t freq_values[3] = {0};
+ 	uint32_t mark_index = 0;
++	struct smu_table_context *table_context = &smu->smu_table;
++	od_table = (OverDriveTable_t *)table_context->overdrive_table;
++	od_settings = smu->od_settings;
+ 
+ 	switch (clk_type) {
+ 	case SMU_GFXCLK:
+@@ -747,6 +759,45 @@ static int navi10_print_clk_levels(struct smu_context *smu,
+ 
+ 		}
+ 		break;
++	case SMU_OD_SCLK:
++		if (!smu->od_enabled || !od_table || !od_settings)
++			break;
++		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS))
++			break;
++		size += sprintf(buf + size, "OD_SCLK:\n");
++		size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
++		break;
++	case SMU_OD_MCLK:
++		if (!smu->od_enabled || !od_table || !od_settings)
++			break;
++		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX))
++			break;
++		size += sprintf(buf + size, "OD_MCLK:\n");
++		size += sprintf(buf + size, "0: %uMHz\n", od_table->UclkFmax);
++		break;
++	case SMU_OD_VDDC_CURVE:
++		if (!smu->od_enabled || !od_table || !od_settings)
++			break;
++		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE))
++			break;
++		size += sprintf(buf + size, "OD_VDDC_CURVE:\n");
++		for (i = 0; i < 3; i++) {
++			switch (i) {
++			case 0:
++				curve_settings = &od_table->GfxclkFreq1;
++				break;
++			case 1:
++				curve_settings = &od_table->GfxclkFreq2;
++				break;
++			case 2:
++				curve_settings = &od_table->GfxclkFreq3;
++				break;
++			default:
++				break;
++			}
++			size += sprintf(buf + size, "%d: %uMHz @ %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE);
++		}
++		break;
+ 	default:
+ 		break;
+ 	}
+@@ -1660,11 +1711,6 @@ static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {
+ 	pr_debug("OD: OverDrivePct: %d\n", od_table->OverDrivePct);
+ }
+ 
+-static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_ID feature)
+-{
+-	return od_table->cap[feature];
+-}
+-
+ static int navi10_od_setting_check_range(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODSETTING_ID setting, uint32_t value)
+ {
+ 	if (value < od_table->min[setting]) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4419-drm-amdgpu-smu_v11-Unify-and-fix-power-limits.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4419-drm-amdgpu-smu_v11-Unify-and-fix-power-limits.patch
new file mode 100644
index 00000000..5ab66eeb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4419-drm-amdgpu-smu_v11-Unify-and-fix-power-limits.patch
@@ -0,0 +1,318 @@
+From bded65628b641bb8cb50be6190abf36500a91624 Mon Sep 17 00:00:00 2001
+From: Matt Coffin <mcoffin13@gmail.com>
+Date: Mon, 11 Nov 2019 11:36:31 -0700
+Subject: [PATCH 4419/4736] drm/amdgpu/smu_v11: Unify and fix power limits
+
+[Why]
+On Navi10, and presumably arcterus, updating pp_table via sysfs would
+not re-scale the maximum possible power limit one can set. On navi10,
+the SMU code ignored the power percentage overdrive setting entirely,
+and would not allow you to exceed the default power limit at all.
+
+[How]
+Adding a function to the SMU interface to get the pptable version of the
+default power limit allows ASIC-specific code to provide the correct
+maximum-settable power limit for the current pptable.
+
+v3: fix spelling (Alex)
+
+Change-Id: Idfa0d2ec64da34520e2928e5011ac3c54bf60a4d
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Matt Coffin <mcoffin13@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 12 +++++-
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  | 23 ++++++-----
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  4 +-
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  2 +
+ .../drm/amd/powerplay/inc/smu_v11_0_pptable.h |  2 +
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 22 +++++-----
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 40 +++++++++++++++++--
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c    |  1 -
+ 8 files changed, 78 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 76a4154b3be2..df5487fae20a 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1109,7 +1109,7 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ 		if (ret)
+ 			return ret;
+ 
+-		ret = smu_get_power_limit(smu, &smu->default_power_limit, true, false);
++		ret = smu_get_power_limit(smu, &smu->default_power_limit, false, false);
+ 		if (ret)
+ 			return ret;
+ 	}
+@@ -2511,3 +2511,13 @@ int smu_get_dpm_clock_table(struct smu_context *smu,
+ 
+ 	return ret;
+ }
++
++uint32_t smu_get_pptable_power_limit(struct smu_context *smu)
++{
++	uint32_t ret = 0;
++
++	if (smu->ppt_funcs->get_pptable_power_limit)
++		ret = smu->ppt_funcs->get_pptable_power_limit(smu);
++
++	return ret;
++}
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 4315a887e918..6d1401b30aaf 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -1261,15 +1261,14 @@ arcturus_get_profiling_clk_mask(struct smu_context *smu,
+ 
+ static int arcturus_get_power_limit(struct smu_context *smu,
+ 				     uint32_t *limit,
+-				     bool asic_default)
++				     bool cap)
+ {
+ 	PPTable_t *pptable = smu->smu_table.driver_pptable;
+ 	uint32_t asic_default_power_limit = 0;
+ 	int ret = 0;
+ 	int power_src;
+ 
+-	if (!smu->default_power_limit ||
+-	    !smu->power_limit) {
++	if (!smu->power_limit) {
+ 		if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
+ 			power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
+ 			if (power_src < 0)
+@@ -1292,17 +1291,11 @@ static int arcturus_get_power_limit(struct smu_context *smu,
+ 				pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
+ 		}
+ 
+-		if (smu->od_enabled) {
+-			asic_default_power_limit *= (100 + smu->smu_table.TDPODLimit);
+-			asic_default_power_limit /= 100;
+-		}
+-
+-		smu->default_power_limit = asic_default_power_limit;
+ 		smu->power_limit = asic_default_power_limit;
+ 	}
+ 
+-	if (asic_default)
+-		*limit = smu->default_power_limit;
++	if (cap)
++		*limit = smu_v11_0_get_max_power_limit(smu);
+ 	else
+ 		*limit = smu->power_limit;
+ 
+@@ -2070,6 +2063,13 @@ static void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
+ 	i2c_del_adapter(control);
+ }
+ 
++static uint32_t arcturus_get_pptable_power_limit(struct smu_context *smu)
++{
++	PPTable_t *pptable = smu->smu_table.driver_pptable;
++
++	return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
++}
++
+ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 	/* translate smu index into arcturus specific index */
+ 	.get_smu_msg_index = arcturus_get_smu_msg_index,
+@@ -2160,6 +2160,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+ 	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+ 	.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
++	.get_pptable_power_limit = arcturus_get_pptable_power_limit,
+ };
+ 
+ void arcturus_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 8120e7587585..999445c5c010 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -261,7 +261,6 @@ struct smu_table_context
+ 	struct smu_table		*tables;
+ 	struct smu_table		memory_pool;
+ 	uint8_t                         thermal_controller_type;
+-	uint16_t			TDPODLimit;
+ 
+ 	void				*overdrive_table;
+ };
+@@ -548,6 +547,7 @@ struct pptable_funcs {
+ 	int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
+ 	int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
+ 	int (*override_pcie_parameters)(struct smu_context *smu);
++	uint32_t (*get_pptable_power_limit)(struct smu_context *smu);
+ };
+ 
+ int smu_load_microcode(struct smu_context *smu);
+@@ -717,4 +717,6 @@ int smu_get_uclk_dpm_states(struct smu_context *smu,
+ int smu_get_dpm_clock_table(struct smu_context *smu,
+ 			    struct dpm_clocks *clock_table);
+ 
++uint32_t smu_get_pptable_power_limit(struct smu_context *smu);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 0ec6ed0456e0..0269fac1a77b 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -253,4 +253,6 @@ int smu_v11_0_override_pcie_parameters(struct smu_context *smu);
+ 
+ int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size);
+ 
++uint32_t smu_v11_0_get_max_power_limit(struct smu_context *smu);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
+index 86cdc3393eac..b2f96a101124 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
+@@ -141,7 +141,9 @@ struct smu_11_0_powerplay_table
+       struct smu_11_0_power_saving_clock_table      power_saving_clock;
+       struct smu_11_0_overdrive_table               overdrive_table;
+ 
++#ifndef SMU_11_0_PARTIAL_PPTABLE
+       PPTable_t smc_pptable;                        //PPTable_t in smu11_driver_if.h
++#endif
+ } __attribute__((packed));
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 5c6ffbd0d884..17ccdb74f4e2 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -1632,17 +1632,22 @@ static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
+ 	return ret;
+ }
+ 
++static uint32_t navi10_get_pptable_power_limit(struct smu_context *smu)
++{
++	PPTable_t *pptable = smu->smu_table.driver_pptable;
++	return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
++}
++
+ static int navi10_get_power_limit(struct smu_context *smu,
+ 				     uint32_t *limit,
+-				     bool asic_default)
++				     bool cap)
+ {
+ 	PPTable_t *pptable = smu->smu_table.driver_pptable;
+ 	uint32_t asic_default_power_limit = 0;
+ 	int ret = 0;
+ 	int power_src;
+ 
+-	if (!smu->default_power_limit ||
+-	    !smu->power_limit) {
++	if (!smu->power_limit) {
+ 		if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
+ 			power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
+ 			if (power_src < 0)
+@@ -1665,17 +1670,11 @@ static int navi10_get_power_limit(struct smu_context *smu,
+ 				pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
+ 		}
+ 
+-		if (smu->od_enabled) {
+-			asic_default_power_limit *= (100 + smu->smu_table.TDPODLimit);
+-			asic_default_power_limit /= 100;
+-		}
+-
+-		smu->default_power_limit = asic_default_power_limit;
+ 		smu->power_limit = asic_default_power_limit;
+ 	}
+ 
+-	if (asic_default)
+-		*limit = smu->default_power_limit;
++	if (cap)
++		*limit = smu_v11_0_get_max_power_limit(smu);
+ 	else
+ 		*limit = smu->power_limit;
+ 
+@@ -2023,6 +2022,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+ 	.set_default_od_settings = navi10_set_default_od_settings,
+ 	.od_edit_dpm_table = navi10_od_edit_dpm_table,
++	.get_pptable_power_limit = navi10_get_pptable_power_limit,
+ };
+ 
+ void navi10_set_ppt_funcs(struct smu_context *smu)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 13ae44ca3504..928877f73dfd 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -20,6 +20,8 @@
+  * OTHER DEALINGS IN THE SOFTWARE.
+  */
+ 
++#define SMU_11_0_PARTIAL_PPTABLE
++
+ #include "pp_debug.h"
+ #include <linux/firmware.h>
+ #include "amdgpu.h"
+@@ -28,6 +30,7 @@
+ #include "atomfirmware.h"
+ #include "amdgpu_atomfirmware.h"
+ #include "smu_v11_0.h"
++#include "smu_v11_0_pptable.h"
+ #include "soc15_common.h"
+ #include "atom.h"
+ #include "amd_pcie.h"
+@@ -1045,13 +1048,44 @@ int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
+ 	return 0;
+ }
+ 
++uint32_t smu_v11_0_get_max_power_limit(struct smu_context *smu) {
++	uint32_t od_limit, max_power_limit;
++	struct smu_11_0_powerplay_table *powerplay_table = NULL;
++	struct smu_table_context *table_context = &smu->smu_table;
++	powerplay_table = table_context->power_play_table;
++
++	max_power_limit = smu_get_pptable_power_limit(smu);
++
++	if (!max_power_limit) {
++		// If we couldn't get the table limit, fall back on first-read value
++		if (!smu->default_power_limit)
++			smu->default_power_limit = smu->power_limit;
++		max_power_limit = smu->default_power_limit;
++	}
++
++	if (smu->od_enabled) {
++		od_limit = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
++
++		pr_debug("ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_limit, smu->default_power_limit);
++
++		max_power_limit *= (100 + od_limit);
++		max_power_limit /= 100;
++	}
++
++	return max_power_limit;
++}
++
+ int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
+ {
+ 	int ret = 0;
++	uint32_t max_power_limit;
++
++	max_power_limit = smu_v11_0_get_max_power_limit(smu);
+ 
+-	if (n > smu->default_power_limit) {
+-		pr_err("New power limit is over the max allowed %d\n",
+-				smu->default_power_limit);
++	if (n > max_power_limit) {
++		pr_err("New power limit (%d) is over the max allowed %d\n",
++				n,
++				max_power_limit);
+ 		return -EINVAL;
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index e00ffbbde791..399697a2ad7f 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -466,7 +466,6 @@ static int vega20_store_powerplay_table(struct smu_context *smu)
+ 	       sizeof(PPTable_t));
+ 
+ 	table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
+-	table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
+ 
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4420-drm-amdkfd-Use-better-name-to-indicate-the-offset-is.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4420-drm-amdkfd-Use-better-name-to-indicate-the-offset-is.patch
new file mode 100644
index 00000000..3c91bc67
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4420-drm-amdkfd-Use-better-name-to-indicate-the-offset-is.patch
@@ -0,0 +1,117 @@
+From 1997547bbbc45a9e1b616819ce3dfe998a51bb0b Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Tue, 15 Jan 2019 13:16:34 -0500
+Subject: [PATCH 4420/4736] drm/amdkfd: Use better name to indicate the offset
+ is in dwords
+
+The doorbell offset could mean the byte offset or the dword offset,
+and the 0 offset place is also different, sometimes the start of PCI
+doorbell bar or the start of process doorbell pages. Use better name
+to avoid confusion.
+
+Change-Id: I75da23bba90231762cf58da3170f5bb77ece45ed
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  |  2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c          | 14 +++++++-------
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h              |  9 +++++----
+ 3 files changed, 13 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 2f0aeb60fe40..0ec9370976d9 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -199,7 +199,7 @@ static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q)
+ 	}
+ 
+ 	q->properties.doorbell_off =
+-		kfd_doorbell_id_to_offset(dev, q->process,
++		kfd_get_doorbell_dw_offset_in_bar(dev, q->process,
+ 					  q->doorbell_id);
+ 
+ 	return 0;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
+index 9f5024bce095..d2be603f9e88 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
+@@ -91,7 +91,7 @@ int kfd_doorbell_init(struct kfd_dev *kfd)
+ 	kfd->doorbell_base = kfd->shared_resources.doorbell_physical_address +
+ 				doorbell_start_offset;
+ 
+-	kfd->doorbell_id_offset = doorbell_start_offset / sizeof(u32);
++	kfd->doorbell_base_dw_offset = doorbell_start_offset / sizeof(u32);
+ 
+ 	kfd->doorbell_kernel_ptr = ioremap(kfd->doorbell_base,
+ 					   kfd_doorbell_process_slice(kfd));
+@@ -103,8 +103,8 @@ int kfd_doorbell_init(struct kfd_dev *kfd)
+ 	pr_debug("doorbell base           == 0x%08lX\n",
+ 			(uintptr_t)kfd->doorbell_base);
+ 
+-	pr_debug("doorbell_id_offset      == 0x%08lX\n",
+-			kfd->doorbell_id_offset);
++	pr_debug("doorbell_base_dw_offset      == 0x%08lX\n",
++			kfd->doorbell_base_dw_offset);
+ 
+ 	pr_debug("doorbell_process_limit  == 0x%08lX\n",
+ 			doorbell_process_limit);
+@@ -320,7 +320,7 @@ void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd,
+ 	 * Calculating the kernel doorbell offset using the first
+ 	 * doorbell page.
+ 	 */
+-	*doorbell_off = kfd->doorbell_id_offset + inx;
++	*doorbell_off = kfd->doorbell_base_dw_offset + inx;
+ 
+ 	pr_debug("Get kernel queue doorbell\n"
+ 			"     doorbell offset   == 0x%08X\n"
+@@ -360,17 +360,17 @@ void write_kernel_doorbell64(void __iomem *db, u64 value)
+ 	}
+ }
+ 
+-unsigned int kfd_doorbell_id_to_offset(struct kfd_dev *kfd,
++unsigned int kfd_get_doorbell_dw_offset_in_bar(struct kfd_dev *kfd,
+ 					struct kfd_process *process,
+ 					unsigned int doorbell_id)
+ {
+ 	/*
+-	 * doorbell_id_offset accounts for doorbells taken by KGD.
++	 * doorbell_base_dw_offset accounts for doorbells taken by KGD.
+ 	 * index * kfd_doorbell_process_slice/sizeof(u32) adjusts to
+ 	 * the process's doorbells. The offset returned is in dword
+ 	 * units regardless of the ASIC-dependent doorbell size.
+ 	 */
+-	return kfd->doorbell_id_offset +
++	return kfd->doorbell_base_dw_offset +
+ 		process->doorbell_index
+ 		* kfd_doorbell_process_slice(kfd) / sizeof(u32) +
+ 		doorbell_id * kfd->device_info->doorbell_size / sizeof(u32);
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index 107b23187009..ff60fb75f224 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -248,9 +248,10 @@ struct kfd_dev {
+ 					 * KFD. It is aligned for mapping
+ 					 * into user mode
+ 					 */
+-	size_t doorbell_id_offset;	/* Doorbell offset (from KFD doorbell
+-					 * to HW doorbell, GFX reserved some
+-					 * at the start)
++	size_t doorbell_base_dw_offset;	/* Offset from the start of the PCI
++					 * doorbell BAR to the first KFD
++					 * doorbell in dwords. GFX reserves
++					 * the segment before this offset.
+ 					 */
+ 	u32 __iomem *doorbell_kernel_ptr; /* This is a pointer for a doorbells
+ 					   * page used by kernel queue
+@@ -958,7 +959,7 @@ void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr);
+ u32 read_kernel_doorbell(u32 __iomem *db);
+ void write_kernel_doorbell(void __iomem *db, u32 value);
+ void write_kernel_doorbell64(void __iomem *db, u64 value);
+-unsigned int kfd_doorbell_id_to_offset(struct kfd_dev *kfd,
++unsigned int kfd_get_doorbell_dw_offset_in_bar(struct kfd_dev *kfd,
+ 					struct kfd_process *process,
+ 					unsigned int doorbell_id);
+ phys_addr_t kfd_get_process_doorbells(struct kfd_dev *dev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4421-drm-amdkfd-Avoid-using-doorbell_off-as-offset-in-pro.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4421-drm-amdkfd-Avoid-using-doorbell_off-as-offset-in-pro.patch
new file mode 100644
index 00000000..c3440c11
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4421-drm-amdkfd-Avoid-using-doorbell_off-as-offset-in-pro.patch
@@ -0,0 +1,120 @@
+From b1ccb6a03bc794d974bb99fda908e3bc23c36a8e Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Tue, 15 Jan 2019 13:58:57 -0500
+Subject: [PATCH 4421/4736] drm/amdkfd: Avoid using doorbell_off as offset in
+ process doorbell pages
+
+dorbell_off in the queue properties is mainly used for the doorbell dw
+offset in pci bar. We should not set it to the doorbell byte offset in
+process doorbell pages. This makes the code much easier to read.
+
+Change-Id: I553045ff9fcb3676900c92d10426f2ceb3660005
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c             | 12 ++++++------
+ drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c              |  2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h                |  3 ++-
+ .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c   | 10 +++++++---
+ 4 files changed, 16 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index 59bfbed3c000..d9cdb25974f9 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -282,6 +282,7 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
+ 	unsigned int queue_id;
+ 	struct kfd_process_device *pdd;
+ 	struct queue_properties q_properties;
++	uint32_t doorbell_offset_in_process = 0;
+ 
+ 	memset(&q_properties, 0, sizeof(struct queue_properties));
+ 
+@@ -310,7 +311,8 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
+ 			p->pasid,
+ 			dev->id);
+ 
+-	err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id);
++	err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id,
++			&doorbell_offset_in_process);
+ 	if (err != 0)
+ 		goto err_create_queue;
+ 
+@@ -321,12 +323,10 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
+ 	args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL;
+ 	args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id);
+ 	if (KFD_IS_SOC15(dev->device_info->asic_family))
+-		/* On SOC15 ASICs, doorbell allocation must be
+-		 * per-device, and independent from the per-process
+-		 * queue_id. Return the doorbell offset within the
+-		 * doorbell aperture to user mode.
++		/* On SOC15 ASICs, include the doorbell offset within the
++		 * process doorbell frame, which is 2 pages.
+ 		 */
+-		args->doorbell_offset |= q_properties.doorbell_off;
++		args->doorbell_offset |= doorbell_offset_in_process;
+ 
+ 	mutex_unlock(&p->mutex);
+ 
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
+index 1eb0c2bedcd9..142ac7954032 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
+@@ -192,7 +192,7 @@ static int dbgdev_register_diq(struct kfd_dbgdev *dbgdev)
+ 	properties.type = KFD_QUEUE_TYPE_DIQ;
+ 
+ 	status = pqm_create_queue(dbgdev->pqm, dbgdev->dev, NULL,
+-				&properties, &qid);
++				&properties, &qid, NULL);
+ 
+ 	if (status) {
+ 		pr_err("Failed to create DIQ\n");
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index ff60fb75f224..e937679f8ca1 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -1045,7 +1045,8 @@ int pqm_create_queue(struct process_queue_manager *pqm,
+ 			    struct kfd_dev *dev,
+ 			    struct file *f,
+ 			    struct queue_properties *properties,
+-			    unsigned int *qid);
++			    unsigned int *qid,
++			    uint32_t *p_doorbell_offset_in_process);
+ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid);
+ int pqm_update_queue(struct process_queue_manager *pqm, unsigned int qid,
+ 			struct queue_properties *p);
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+index 227fb0ec8115..591b5d05ab53 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+@@ -192,7 +192,8 @@ int pqm_create_queue(struct process_queue_manager *pqm,
+ 			    struct kfd_dev *dev,
+ 			    struct file *f,
+ 			    struct queue_properties *properties,
+-			    unsigned int *qid)
++			    unsigned int *qid,
++			    uint32_t *p_doorbell_offset_in_process)
+ {
+ 	int retval;
+ 	struct kfd_process_device *pdd;
+@@ -303,12 +304,15 @@ int pqm_create_queue(struct process_queue_manager *pqm,
+ 		goto err_create_queue;
+ 	}
+ 
+-	if (q)
++	if (q && p_doorbell_offset_in_process)
+ 		/* Return the doorbell offset within the doorbell page
+ 		 * to the caller so it can be passed up to user mode
+ 		 * (in bytes).
++		 * There are always 1024 doorbells per process, so in case
++		 * of 8-byte doorbells, there are two doorbell pages per
++		 * process.
+ 		 */
+-		properties->doorbell_off =
++		*p_doorbell_offset_in_process =
+ 			(q->properties.doorbell_off * sizeof(uint32_t)) &
+ 			(kfd_doorbell_process_slice(dev) - 1);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4422-drm-amdkfd-Rename-create_cp_queue-to-init_user_queue.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4422-drm-amdkfd-Rename-create_cp_queue-to-init_user_queue.patch
new file mode 100644
index 00000000..a7c3727a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4422-drm-amdkfd-Rename-create_cp_queue-to-init_user_queue.patch
@@ -0,0 +1,50 @@
+From edd7f06fc4a2eb254e4c7c23786ecf0ae3b3634d Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Tue, 15 Jan 2019 19:23:16 -0500
+Subject: [PATCH 4422/4736] drm/amdkfd: Rename create_cp_queue() to
+ init_user_queue()
+
+create_cp_queue() could also work with SDMA queues, so we should rename
+it. It only initialize the data values rather than creating queues.
+
+Change-Id: I76cbaed8fa95dd9062d786cbc1dd037ff041da9d
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+index 591b5d05ab53..93a349f9c205 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+@@ -162,7 +162,7 @@ void pqm_uninit(struct process_queue_manager *pqm)
+ 	pqm->queue_slot_bitmap = NULL;
+ }
+ 
+-static int create_cp_queue(struct process_queue_manager *pqm,
++static int init_user_queue(struct process_queue_manager *pqm,
+ 				struct kfd_dev *dev, struct queue **q,
+ 				struct queue_properties *q_properties,
+ 				struct file *f, unsigned int qid)
+@@ -251,7 +251,7 @@ int pqm_create_queue(struct process_queue_manager *pqm,
+ 			goto err_create_queue;
+ 		}
+ 
+-		retval = create_cp_queue(pqm, dev, &q, properties, f, *qid);
++		retval = init_user_queue(pqm, dev, &q, properties, f, *qid);
+ 		if (retval != 0)
+ 			goto err_create_queue;
+ 		pqn->q = q;
+@@ -272,7 +272,7 @@ int pqm_create_queue(struct process_queue_manager *pqm,
+ 			goto err_create_queue;
+ 		}
+ 
+-		retval = create_cp_queue(pqm, dev, &q, properties, f, *qid);
++		retval = init_user_queue(pqm, dev, &q, properties, f, *qid);
+ 		if (retval != 0)
+ 			goto err_create_queue;
+ 		pqn->q = q;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4423-drm-amd-powerplay-read-pcie-speed-width-info.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4423-drm-amd-powerplay-read-pcie-speed-width-info.patch
new file mode 100644
index 00000000..666b47d4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4423-drm-amd-powerplay-read-pcie-speed-width-info.patch
@@ -0,0 +1,198 @@
+From e77465f75d251394f25f39784cec338ef492f443 Mon Sep 17 00:00:00 2001
+From: Kenneth Feng <kenneth.feng@amd.com>
+Date: Tue, 12 Nov 2019 16:27:11 +0800
+Subject: [PATCH 4423/4736] drm/amd/powerplay: read pcie speed/width info
+
+sysfs interface to read pcie speed&width info on navi1x.
+
+Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 10 ++--
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  8 +++
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 50 ++++++++++++++++++-
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.h    |  3 ++
+ 4 files changed, 66 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index df5487fae20a..18da3b393f96 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1068,10 +1068,6 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ 		return ret;
+ 
+ 	if (adev->asic_type != CHIP_ARCTURUS) {
+-		ret = smu_override_pcie_parameters(smu);
+-		if (ret)
+-			return ret;
+-
+ 		ret = smu_notify_display_change(smu);
+ 		if (ret)
+ 			return ret;
+@@ -1100,6 +1096,12 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ 			return ret;
+ 	}
+ 
++	if (adev->asic_type != CHIP_ARCTURUS) {
++		ret = smu_override_pcie_parameters(smu);
++		if (ret)
++			return ret;
++	}
++
+ 	ret = smu_set_default_od_settings(smu, initialize);
+ 	if (ret)
+ 		return ret;
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 0269fac1a77b..e71445548c6f 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -49,6 +49,8 @@
+ 
+ #define SMU11_TOOL_SIZE			0x19000
+ 
++#define MAX_PCIE_CONF 2
++
+ #define CLK_MAP(clk, index) \
+ 	[SMU_##clk] = {1, (index)}
+ 
+@@ -89,6 +91,11 @@ struct smu_11_0_dpm_table {
+ 	uint32_t    max;        /* MHz */
+ };
+ 
++struct smu_11_0_pcie_table {
++        uint8_t  pcie_gen[MAX_PCIE_CONF];
++        uint8_t  pcie_lane[MAX_PCIE_CONF];
++};
++
+ struct smu_11_0_dpm_tables {
+ 	struct smu_11_0_dpm_table        soc_table;
+ 	struct smu_11_0_dpm_table        gfx_table;
+@@ -101,6 +108,7 @@ struct smu_11_0_dpm_tables {
+ 	struct smu_11_0_dpm_table        display_table;
+ 	struct smu_11_0_dpm_table        phy_table;
+ 	struct smu_11_0_dpm_table        fclk_table;
++	struct smu_11_0_pcie_table       pcie_table;
+ };
+ 
+ struct smu_11_0_dpm_context {
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 17ccdb74f4e2..6fd808312d4e 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -35,6 +35,7 @@
+ #include "navi10_ppt.h"
+ #include "smu_v11_0_pptable.h"
+ #include "smu_v11_0_ppsmc.h"
++#include "nbio/nbio_7_4_sh_mask.h"
+ 
+ #include "asic_reg/mp/mp_11_0_sh_mask.h"
+ 
+@@ -598,6 +599,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
+ 	struct smu_table_context *table_context = &smu->smu_table;
+ 	struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+ 	PPTable_t *driver_ppt = NULL;
++	int i;
+ 
+         driver_ppt = table_context->driver_pptable;
+ 
+@@ -628,6 +630,11 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
+         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
+         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
+ 
++	for (i = 0; i < MAX_PCIE_CONF; i++) {
++		dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
++		dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
++	}
++
+ 	return 0;
+ }
+ 
+@@ -709,6 +716,11 @@ static int navi10_print_clk_levels(struct smu_context *smu,
+ 	struct smu_table_context *table_context = &smu->smu_table;
+ 	od_table = (OverDriveTable_t *)table_context->overdrive_table;
+ 	od_settings = smu->od_settings;
++	uint32_t gen_speed, lane_width;
++	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
++	struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
++	struct amdgpu_device *adev = smu->adev;
++	PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
+ 
+ 	switch (clk_type) {
+ 	case SMU_GFXCLK:
+@@ -759,6 +771,30 @@ static int navi10_print_clk_levels(struct smu_context *smu,
+ 
+ 		}
+ 		break;
++	case SMU_PCIE:
++		gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
++			     PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
++			>> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
++		lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
++			      PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
++			>> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
++		for (i = 0; i < NUM_LINK_LEVELS; i++)
++			size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
++					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
++					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
++					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
++					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
++					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
++					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
++					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
++					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
++					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
++					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
++					pptable->LclkFreq[i],
++					(gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
++					(lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
++					"*" : "");
++		break;
+ 	case SMU_OD_SCLK:
+ 		if (!smu->od_enabled || !od_table || !od_settings)
+ 			break;
+@@ -1689,6 +1725,9 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
+ 	int ret, i;
+ 	uint32_t smu_pcie_arg;
+ 
++	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
++	struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
++
+ 	for (i = 0; i < NUM_LINK_LEVELS; i++) {
+ 		smu_pcie_arg = (i << 16) |
+ 			((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
+@@ -1697,8 +1736,17 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
+ 		ret = smu_send_smc_msg_with_param(smu,
+ 					  SMU_MSG_OverridePcieParameters,
+ 					  smu_pcie_arg);
++
++		if (ret)
++			return ret;
++
++		if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
++			dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
++		if (pptable->PcieLaneCount[i] > pcie_width_cap)
++			dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
+ 	}
+-	return ret;
++
++	return 0;
+ }
+ 
+ static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+index fd6dda1a67a1..ec03c7992f6d 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+@@ -35,6 +35,9 @@
+ 
+ #define NAVI10_VOLTAGE_SCALE (4)
+ 
++#define smnPCIE_LC_SPEED_CNTL			0x11140290
++#define smnPCIE_LC_LINK_WIDTH_CNTL		0x11140288
++
+ extern void navi10_set_ppt_funcs(struct smu_context *smu);
+ 
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4424-drm-amdgpu-vcn-finish-delay-work-before-release-reso.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4424-drm-amdgpu-vcn-finish-delay-work-before-release-reso.patch
new file mode 100644
index 00000000..d3af7de5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4424-drm-amdgpu-vcn-finish-delay-work-before-release-reso.patch
@@ -0,0 +1,34 @@
+From 7aa8812dc7edd5dacf23c87d175bd7508004163f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 11 Nov 2019 15:48:48 -0500
+Subject: [PATCH 4424/4736] drm/amdgpu/vcn: finish delay work before release
+ resources
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+flush/cancel delayed works before doing finalization
+to avoid concurrently requests.
+
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+index 6b31410a5ff9..c72819d55502 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+@@ -192,6 +192,8 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
+ {
+ 	int i, j;
+ 
++	cancel_delayed_work_sync(&adev->vcn.idle_work);
++
+ 	if (adev->vcn.indirect_sram) {
+ 		amdgpu_bo_free_kernel(&adev->vcn.dpg_sram_bo,
+ 				      &adev->vcn.dpg_sram_gpu_addr,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4425-drm-amd-display-remove-set-but-not-used-variable-bpc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4425-drm-amd-display-remove-set-but-not-used-variable-bpc.patch
new file mode 100644
index 00000000..1eed3575
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4425-drm-amd-display-remove-set-but-not-used-variable-bpc.patch
@@ -0,0 +1,58 @@
+From ba1a475025810b4ab5555f93eb3700db5f44dbdc Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Tue, 12 Nov 2019 10:10:50 +0800
+Subject: [PATCH 4425/4736] drm/amd/display: remove set but not used variable
+ 'bpc'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c: In function get_pbn_from_timing:
+drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:2364:11: warning:
+ variable bpc set but not used [-Wunused-but-set-variable]
+
+It is not used since commit e49f69363adf ("drm/amd/display: use
+proper formula to calculate bandwidth from timing"), this also
+remove get_color_depth(), which is only used here.
+
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 15 ---------------
+ 1 file changed, 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index a014d47f0f37..7fab34ce0591 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2642,28 +2642,13 @@ static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
+ 	return dc_fixpt_div_int(mbytes_per_sec, 54);
+ }
+ 
+-static int get_color_depth(enum dc_color_depth color_depth)
+-{
+-	switch (color_depth) {
+-	case COLOR_DEPTH_666: return 6;
+-	case COLOR_DEPTH_888: return 8;
+-	case COLOR_DEPTH_101010: return 10;
+-	case COLOR_DEPTH_121212: return 12;
+-	case COLOR_DEPTH_141414: return 14;
+-	case COLOR_DEPTH_161616: return 16;
+-	default: return 0;
+-	}
+-}
+-
+ static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
+ {
+-	uint32_t bpc;
+ 	uint64_t kbps;
+ 	struct fixed31_32 peak_kbps;
+ 	uint32_t numerator;
+ 	uint32_t denominator;
+ 
+-	bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
+ 	kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
+ 
+ 	/*
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4426-drm-amdkfd-Implement-queue-priority-controls-for-gfx.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4426-drm-amdkfd-Implement-queue-priority-controls-for-gfx.patch
new file mode 100644
index 00000000..74923291
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4426-drm-amdkfd-Implement-queue-priority-controls-for-gfx.patch
@@ -0,0 +1,53 @@
+From ff581b5b65390250d5438649963bb79983377070 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 8 Nov 2019 21:15:48 -0500
+Subject: [PATCH 4426/4736] drm/amdkfd: Implement queue priority controls for
+ gfx10
+
+Ported from gfx9.
+
+Change-Id: I388dc7c609ed724a6d600840f8e7317d9c2c877d
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 10 +++++++---
+ 1 file changed, 7 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index e2fb76247f47..79827017ea45 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -66,6 +66,12 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd,
+ 		m->compute_static_thread_mgmt_se3);
+ }
+ 
++static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q)
++{
++	m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
++	m->cp_hqd_queue_priority = q->priority;
++}
++
+ static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,
+ 		struct queue_properties *q)
+ {
+@@ -109,9 +115,6 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,
+ 			1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
+ 			10 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
+ 
+-	m->cp_hqd_pipe_priority = 1;
+-	m->cp_hqd_queue_priority = 15;
+-
+ 	if (q->format == KFD_QUEUE_FORMAT_AQL) {
+ 		m->cp_hqd_aql_control =
+ 			1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT;
+@@ -208,6 +211,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,
+ 		m->cp_hqd_ctx_save_control = 0;
+ 
+ 	update_cu_mask(mm, mqd, q);
++	set_priority(m, q);
+ 
+ 	q->is_active = (q->queue_size > 0 &&
+ 			q->queue_address != 0 &&
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4427-drm-amdkfd-Update-get_wave_state-for-GFX10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4427-drm-amdkfd-Update-get_wave_state-for-GFX10.patch
new file mode 100644
index 00000000..28b21ed9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4427-drm-amdkfd-Update-get_wave_state-for-GFX10.patch
@@ -0,0 +1,50 @@
+From 748b3ec8dd68824402757dac7c4e6d270c34da28 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 8 Nov 2019 22:54:07 -0500
+Subject: [PATCH 4427/4736] drm/amdkfd: Update get_wave_state() for GFX10
+
+Given control stack is now in the userspace context save restore area
+on GFX10, the same as GFX8, it is not needed to copy it back to userspace.
+
+Change-Id: I063ddc3026eefa57713ec47b466a90f9bf9d49b8
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 14 +++++++++-----
+ 1 file changed, 9 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index 79827017ea45..4cb7c226d4e0 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -251,18 +251,22 @@ static int get_wave_state(struct mqd_manager *mm, void *mqd,
+ {
+ 	struct v10_compute_mqd *m;
+ 
+-	/* Control stack is located one page after MQD. */
+-	void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE);
+-
+ 	m = get_mqd(mqd);
+ 
++	/* Control stack is written backwards, while workgroup context data
++	 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size.
++	 * Current position is at m->cp_hqd_cntl_stack_offset and
++	 * m->cp_hqd_wg_state_offset, respectively.
++	 */
+ 	*ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
+ 		m->cp_hqd_cntl_stack_offset;
+ 	*save_area_used_size = m->cp_hqd_wg_state_offset -
+ 		m->cp_hqd_cntl_stack_size;
+ 
+-	if (copy_to_user(ctl_stack, mqd_ctl_stack, m->cp_hqd_cntl_stack_size))
+-		return -EFAULT;
++	/* Control stack is not copied to user mode for GFXv10 because
++	 * it's part of the context save area that is already
++	 * accessible to user mode
++	 */
+ 
+ 	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4428-drm-amdkfd-Use-QUEUE_IS_ACTIVE-macro-in-mqd-v10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4428-drm-amdkfd-Use-QUEUE_IS_ACTIVE-macro-in-mqd-v10.patch
new file mode 100644
index 00000000..90a156d0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4428-drm-amdkfd-Use-QUEUE_IS_ACTIVE-macro-in-mqd-v10.patch
@@ -0,0 +1,46 @@
+From a00e64b5598bf290b71fb6e6e72cbc71cfdcb6a1 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 8 Nov 2019 21:52:55 -0500
+Subject: [PATCH 4428/4736] drm/amdkfd: Use QUEUE_IS_ACTIVE macro in mqd v10
+
+This is done for other GFX in commit bb2d2128a54c4. Port it to GFX10.
+
+Change-Id: I9e04872be3af0e90f5f6930226896b1ea545f3d9
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 11 ++---------
+ 1 file changed, 2 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index 4cb7c226d4e0..55f1cda095d1 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -213,10 +213,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,
+ 	update_cu_mask(mm, mqd, q);
+ 	set_priority(m, q);
+ 
+-	q->is_active = (q->queue_size > 0 &&
+-			q->queue_address != 0 &&
+-			q->queue_percent > 0 &&
+-			!q->is_evicted);
++	q->is_active = QUEUE_IS_ACTIVE(*q);
+ }
+ 
+ static int destroy_mqd(struct mqd_manager *mm, void *mqd,
+@@ -348,11 +345,7 @@ static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
+ 	m->sdma_queue_id = q->sdma_queue_id;
+ 	m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT;
+ 
+-
+-	q->is_active = (q->queue_size > 0 &&
+-			q->queue_address != 0 &&
+-			q->queue_percent > 0 &&
+-			!q->is_evicted);
++	q->is_active = QUEUE_IS_ACTIVE(*q);
+ }
+ 
+ /*
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4429-drm-amdkfd-Stop-using-GFP_NOIO-explicitly-for-two-pl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4429-drm-amdkfd-Stop-using-GFP_NOIO-explicitly-for-two-pl.patch
new file mode 100644
index 00000000..395d11f1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4429-drm-amdkfd-Stop-using-GFP_NOIO-explicitly-for-two-pl.patch
@@ -0,0 +1,52 @@
+From 156064982ff08f441f5473b23eb760b5476d710f Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 8 Nov 2019 22:06:37 -0500
+Subject: [PATCH 4429/4736] drm/amdkfd: Stop using GFP_NOIO explicitly for two
+ places
+
+Adapt the change from 1cd106ecfc1f04
+
+The change is:
+
+    drm/amdkfd: Stop using GFP_NOIO explicitly
+
+    This is no longer needed with the memalloc_nofs_save/restore in
+    dqm_lock/unlock
+
+Change-Id: I42450b2c149d2b1842be99a8f355c829a0079e7c
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c  | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index 55f1cda095d1..65a03d1d79db 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -393,7 +393,7 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+ 	if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
+ 		return NULL;
+ 
+-	mqd = kzalloc(sizeof(*mqd), GFP_NOIO);
++	mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
+ 	if (!mqd)
+ 		return NULL;
+ 
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index 785ceda52c94..822747377c28 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -135,7 +135,7 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,
+ 	 * instead of sub-allocation function.
+ 	 */
+ 	if (kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) {
+-		mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_NOIO);
++		mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
+ 		if (!mqd_mem_obj)
+ 			return NULL;
+ 		retval = amdgpu_amdkfd_alloc_gtt_mem(kfd->kgd,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4430-drm-amdgpu-remove-set-but-not-used-variable-mc_share.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4430-drm-amdgpu-remove-set-but-not-used-variable-mc_share.patch
new file mode 100644
index 00000000..312bfb11
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4430-drm-amdgpu-remove-set-but-not-used-variable-mc_share.patch
@@ -0,0 +1,75 @@
+From fd2dee5bbe8c1c3611b892ff64a76a82208e8e42 Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Wed, 13 Nov 2019 20:44:28 +0800
+Subject: [PATCH 4430/4736] drm/amdgpu: remove set but not used variable
+ 'mc_shared_chmap' from 'gfx_v6_0.c' and 'gfx_v7_0.c'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c: In function
+‘gfx_v6_0_constants_init’:
+drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c:1579:6: warning: variable
+‘mc_shared_chmap’ set but not used [-Wunused-but-set-variable]
+
+drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c: In function
+‘gfx_v7_0_gpu_early_init’:
+drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:4262:6: warning: variable
+‘mc_shared_chmap’ set but not used [-Wunused-but-set-variable]
+
+Fixes: 2cd46ad22383 ("drm/amdgpu: add graphic pipeline implementation for si v8")
+Fixes: d93f3ca706b8 ("drm/amdgpu/gfx7: rework gpu_init()")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 3 +--
+ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 3 +--
+ 2 files changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+index b4af1b55f852..954fe40eacd5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+@@ -1574,7 +1574,7 @@ static void gfx_v6_0_config_init(struct amdgpu_device *adev)
+ static void gfx_v6_0_constants_init(struct amdgpu_device *adev)
+ {
+ 	u32 gb_addr_config = 0;
+-	u32 mc_shared_chmap, mc_arb_ramcfg;
++	u32 mc_arb_ramcfg;
+ 	u32 sx_debug_1;
+ 	u32 hdp_host_path_cntl;
+ 	u32 tmp;
+@@ -1676,7 +1676,6 @@ static void gfx_v6_0_constants_init(struct amdgpu_device *adev)
+ 
+ 	WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
+ 
+-	mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
+ 	adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
+ 	mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+index c08f5c53dcb4..b8c2e9d9c711 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+@@ -4248,7 +4248,7 @@ static int gfx_v7_0_late_init(void *handle)
+ static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
+ {
+ 	u32 gb_addr_config;
+-	u32 mc_shared_chmap, mc_arb_ramcfg;
++	u32 mc_arb_ramcfg;
+ 	u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
+ 	u32 tmp;
+ 
+@@ -4325,7 +4325,6 @@ static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
+ 		break;
+ 	}
+ 
+-	mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
+ 	adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
+ 	mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4431-drm-amdgpu-remove-set-but-not-used-variable-amdgpu_c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4431-drm-amdgpu-remove-set-but-not-used-variable-amdgpu_c.patch
new file mode 100644
index 00000000..8b24dd14
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4431-drm-amdgpu-remove-set-but-not-used-variable-amdgpu_c.patch
@@ -0,0 +1,46 @@
+From f76a6a1084d78d3883c1342d5ba1c64213007217 Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Wed, 13 Nov 2019 20:44:29 +0800
+Subject: [PATCH 4431/4736] drm/amdgpu: remove set but not used variable
+ 'amdgpu_connector'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/amdgpu_display.c: In function
+‘amdgpu_display_crtc_scaling_mode_fixup’:
+drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:693:27: warning: variable
+‘amdgpu_connector’ set but not used [-Wunused-but-set-variable]
+
+Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+index aad642e660b2..dcabe24e4dc3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+@@ -722,7 +722,6 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
+ 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
+ 	struct amdgpu_encoder *amdgpu_encoder;
+ 	struct drm_connector *connector;
+-	struct amdgpu_connector *amdgpu_connector;
+ 	u32 src_v = 1, dst_v = 1;
+ 	u32 src_h = 1, dst_h = 1;
+ 
+@@ -734,7 +733,6 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
+ 			continue;
+ 		amdgpu_encoder = to_amdgpu_encoder(encoder);
+ 		connector = amdgpu_get_connector_for_encoder(encoder);
+-		amdgpu_connector = to_amdgpu_connector(connector);
+ 
+ 		/* set scaling */
+ 		if (amdgpu_encoder->rmx_type == RMX_OFF)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4432-drm-amdgpu-remove-set-but-not-used-variable-count.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4432-drm-amdgpu-remove-set-but-not-used-variable-count.patch
new file mode 100644
index 00000000..f62a8d1d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4432-drm-amdgpu-remove-set-but-not-used-variable-count.patch
@@ -0,0 +1,52 @@
+From b743e01c90ccb4a6f7c412d3e2bb19791266c3b9 Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Wed, 13 Nov 2019 20:44:30 +0800
+Subject: [PATCH 4432/4736] drm/amdgpu: remove set but not used variable
+ 'count'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdkfd/kfd_device.c: In function
+‘kgd2kfd_post_reset’:
+drivers/gpu/drm/amd/amdkfd/kfd_device.c:745:11: warning:
+variable ‘count’ set but not used [-Wunused-but-set-variable]
+
+'count' is never used, so can be removed. Thus 'atomic_dec_return'
+can be replaced as 'atomic_dec'
+
+Fixes: e42051d2133b ("drm/amdkfd: Implement GPU reset handlers in KFD")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index eb5eeba8792d..3827ace06f9b 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -759,7 +759,7 @@ int kgd2kfd_post_reset(struct kfd_dev *kfd)
+ 	if (kfd_flag_for_rv2)
+ 		return 0;
+ 
+-	int ret, count;
++	int ret;
+ 
+ 	if (!kfd->init_complete)
+ 		return 0;
+@@ -767,7 +767,7 @@ int kgd2kfd_post_reset(struct kfd_dev *kfd)
+ 	ret = kfd_resume(kfd);
+ 	if (ret)
+ 		return ret;
+-	count = atomic_dec_return(&kfd_locked);
++	atomic_dec(&kfd_locked);
+ 
+ 	atomic_set(&kfd->sram_ecc_flag, 0);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4433-drm-amdgpu-remove-set-but-not-used-variable-invalid.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4433-drm-amdgpu-remove-set-but-not-used-variable-invalid.patch
new file mode 100644
index 00000000..294e404b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4433-drm-amdgpu-remove-set-but-not-used-variable-invalid.patch
@@ -0,0 +1,47 @@
+From fa007cd9d867f24f8d412ac40245f8ba7b2fbfdc Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Wed, 13 Nov 2019 20:44:31 +0800
+Subject: [PATCH 4433/4736] drm/amdgpu: remove set but not used variable
+ 'invalid'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c: In function
+‘amdgpu_amdkfd_evict_userptr’:
+drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c:1665:6: warning:
+variable ‘invalid’ set but not used [-Wunused-but-set-variable]
+
+'invalid' is never used, so can be removed. Thus 'atomic_inc_return'
+can be replaced as 'atomic_inc'
+
+Fixes: 5ae0283e831a ("drm/amdgpu: Add userptr support for KFD")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index 9ce17867fac7..083bd8fe8057 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -1926,10 +1926,10 @@ int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem,
+ 		return 0;
+ 
+ 	struct amdkfd_process_info *process_info = mem->process_info;
+-	int invalid, evicted_bos;
++	int evicted_bos;
+ 	int r = 0;
+ 
+-	invalid = atomic_inc_return(&mem->invalid);
++	atomic_inc(&mem->invalid);
+ 	evicted_bos = atomic_inc_return(&process_info->evicted_bos);
+ 	if (evicted_bos == 1) {
+ 		/* First eviction, stop the queues */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4434-drm-amd-powerplay-remove-set-but-not-used-variable-u.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4434-drm-amd-powerplay-remove-set-but-not-used-variable-u.patch
new file mode 100644
index 00000000..d880e5d0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4434-drm-amd-powerplay-remove-set-but-not-used-variable-u.patch
@@ -0,0 +1,58 @@
+From 4084f72fb6be8940786655c472117d293f44d2db Mon Sep 17 00:00:00 2001
+From: yu kuai <yukuai3@huawei.com>
+Date: Wed, 13 Nov 2019 20:44:34 +0800
+Subject: [PATCH 4434/4736] drm/amd/powerplay: remove set but not used variable
+ 'us_mvdd'
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c: In
+function ‘vegam_populate_smc_acpi_level’:
+drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c:1117:11:
+warning: variable 'us_mvdd' set but not used [-Wunused-but-set-variable]
+
+It is never used, so can be removed.
+
+Fixes: ac7822b0026f ("drm/amd/powerplay: add smumgr support for VEGAM (v2)")
+Signed-off-by: yu kuai <yukuai3@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 12 ------------
+ 1 file changed, 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+index ae18fbcb26fb..2068eb00d2f8 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+@@ -1114,7 +1114,6 @@ static int vegam_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
+ 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
+ 	SMIO_Pattern vol_level;
+ 	uint32_t mvdd;
+-	uint16_t us_mvdd;
+ 
+ 	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
+ 
+@@ -1168,17 +1167,6 @@ static int vegam_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
+ 			"in Clock Dependency Table",
+ 			);
+ 
+-	us_mvdd = 0;
+-	if ((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
+-			(data->mclk_dpm_key_disabled))
+-		us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
+-	else {
+-		if (!vegam_populate_mvdd_value(hwmgr,
+-				data->dpm_table.mclk_table.dpm_levels[0].value,
+-				&vol_level))
+-			us_mvdd = vol_level.Voltage;
+-	}
+-
+ 	if (!vegam_populate_mvdd_value(hwmgr, 0, &vol_level))
+ 		table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
+ 	else
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4435-drm-amdkfd-Merge-CIK-kernel-queue-functions-into-VI.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4435-drm-amdkfd-Merge-CIK-kernel-queue-functions-into-VI.patch
new file mode 100644
index 00000000..67599335
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4435-drm-amdkfd-Merge-CIK-kernel-queue-functions-into-VI.patch
@@ -0,0 +1,158 @@
+From 51ef2756d9b88b590d80b2fc552a7ea54e65aaa4 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Thu, 7 Nov 2019 23:18:04 -0500
+Subject: [PATCH 4435/4736] drm/amdkfd: Merge CIK kernel queue functions into
+ VI
+
+The only difference that CIK kernel queue functions are different from
+VI is avoid allocating eop_mem. We can achieve that by using a if
+condition.
+
+Change-Id: Iea9cbc82f603ff008a906c5ee32325ddcd02d963
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/Makefile           |  1 -
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c |  7 +--
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h |  1 -
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_cik.c | 53 -------------------
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c  |  7 +++
+ 5 files changed, 9 insertions(+), 60 deletions(-)
+ delete mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_cik.c
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile
+index c2c125156a62..a34a4a65970f 100644
+--- a/drivers/gpu/drm/amd/amdkfd/Makefile
++++ b/drivers/gpu/drm/amd/amdkfd/Makefile
+@@ -38,7 +38,6 @@ AMDKFD_FILES	:= $(AMDKFD_PATH)/kfd_module.o \
+ 		$(AMDKFD_PATH)/kfd_mqd_manager_v9.o \
+ 		$(AMDKFD_PATH)/kfd_mqd_manager_v10.o \
+ 		$(AMDKFD_PATH)/kfd_kernel_queue.o \
+-		$(AMDKFD_PATH)/kfd_kernel_queue_cik.o \
+ 		$(AMDKFD_PATH)/kfd_kernel_queue_vi.o \
+ 		$(AMDKFD_PATH)/kfd_kernel_queue_v9.o \
+ 		$(AMDKFD_PATH)/kfd_packet_manager.o \
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+index 04041bab42a8..f3a08145d067 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+@@ -346,6 +346,8 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
+ 	kq->ops.rollback_packet = rollback_packet;
+ 
+ 	switch (dev->device_info->asic_family) {
++	case CHIP_KAVERI:
++	case CHIP_HAWAII:
+ 	case CHIP_CARRIZO:
+ 	case CHIP_TONGA:
+ 	case CHIP_FIJI:
+@@ -356,11 +358,6 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
+ 		kernel_queue_init_vi(&kq->ops_asic_specific);
+ 		break;
+ 
+-	case CHIP_KAVERI:
+-	case CHIP_HAWAII:
+-		kernel_queue_init_cik(&kq->ops_asic_specific);
+-		break;
+-
+ 	case CHIP_VEGA10:
+ 	case CHIP_VEGA12:
+ 	case CHIP_VEGA20:
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
+index 384d7a37b343..b22ff0fb40fe 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
+@@ -109,7 +109,6 @@ struct kernel_queue {
+ 	struct list_head	list;
+ };
+ 
+-void kernel_queue_init_cik(struct kernel_queue_ops *ops);
+ void kernel_queue_init_vi(struct kernel_queue_ops *ops);
+ void kernel_queue_init_v9(struct kernel_queue_ops *ops);
+ 
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_cik.c
+deleted file mode 100644
+index 19e54acb4125..000000000000
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_cik.c
++++ /dev/null
+@@ -1,53 +0,0 @@
+-/*
+- * Copyright 2014 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included in
+- * all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- * OTHER DEALINGS IN THE SOFTWARE.
+- *
+- */
+-
+-#include "kfd_kernel_queue.h"
+-
+-static bool initialize_cik(struct kernel_queue *kq, struct kfd_dev *dev,
+-			enum kfd_queue_type type, unsigned int queue_size);
+-static void uninitialize_cik(struct kernel_queue *kq);
+-static void submit_packet_cik(struct kernel_queue *kq);
+-
+-void kernel_queue_init_cik(struct kernel_queue_ops *ops)
+-{
+-	ops->initialize = initialize_cik;
+-	ops->uninitialize = uninitialize_cik;
+-	ops->submit_packet = submit_packet_cik;
+-}
+-
+-static bool initialize_cik(struct kernel_queue *kq, struct kfd_dev *dev,
+-			enum kfd_queue_type type, unsigned int queue_size)
+-{
+-	return true;
+-}
+-
+-static void uninitialize_cik(struct kernel_queue *kq)
+-{
+-}
+-
+-static void submit_packet_cik(struct kernel_queue *kq)
+-{
+-	*kq->wptr_kernel = kq->pending_wptr;
+-	write_kernel_doorbell(kq->queue->properties.doorbell_ptr,
+-				kq->pending_wptr);
+-}
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
+index 7047f4c5a7dc..9b0380d91bfb 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
+@@ -43,6 +43,10 @@ static bool initialize_vi(struct kernel_queue *kq, struct kfd_dev *dev,
+ {
+ 	int retval;
+ 
++	/*For CIK family asics, kq->eop_mem is not needed */
++	if (dev->device_info->asic_family <= CHIP_MULLINS)
++		return true;
++
+ 	retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, &kq->eop_mem);
+ 	if (retval != 0)
+ 		return false;
+@@ -57,6 +61,9 @@ static bool initialize_vi(struct kernel_queue *kq, struct kfd_dev *dev,
+ 
+ static void uninitialize_vi(struct kernel_queue *kq)
+ {
++	/* For CIK family asics, kq->eop_mem is Null, kfd_gtt_sa_free()
++	 * is able to handle NULL properly.
++	 */
+ 	kfd_gtt_sa_free(kq->dev, kq->eop_mem);
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4436-drm-amdkfd-Eliminate-ops_asic_specific-in-kernel-que.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4436-drm-amdkfd-Eliminate-ops_asic_specific-in-kernel-que.patch
new file mode 100644
index 00000000..55d6d9ff
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4436-drm-amdkfd-Eliminate-ops_asic_specific-in-kernel-que.patch
@@ -0,0 +1,248 @@
+From 2aaa285d69d0e973d7da89cae6d77232cae25267 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Thu, 7 Nov 2019 23:59:43 -0500
+Subject: [PATCH 4436/4736] drm/amdkfd: Eliminate ops_asic_specific in kernel
+ queue
+
+The ops_asic_specific function pointers are actually quite generic after
+using a simple if condition. Eliminate it by code refactoring.
+
+Change-Id: Icb891289cca31acdbe2d2eea76a426f1738b9c08
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 63 ++++++++-----------
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h |  4 --
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c  | 36 -----------
+ .../gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c  | 48 --------------
+ 4 files changed, 26 insertions(+), 125 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+index f3a08145d067..ca7e8d299c8b 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+@@ -87,9 +87,17 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev,
+ 	kq->pq_kernel_addr = kq->pq->cpu_ptr;
+ 	kq->pq_gpu_addr = kq->pq->gpu_addr;
+ 
+-	retval = kq->ops_asic_specific.initialize(kq, dev, type, queue_size);
+-	if (!retval)
+-		goto err_eop_allocate_vidmem;
++	/* For CIK family asics, kq->eop_mem is not needed */
++	if (dev->device_info->asic_family > CHIP_HAWAII) {
++		retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, &kq->eop_mem);
++		if (retval != 0)
++			goto err_eop_allocate_vidmem;
++
++		kq->eop_gpu_addr = kq->eop_mem->gpu_addr;
++		kq->eop_kernel_addr = kq->eop_mem->cpu_ptr;
++
++		memset(kq->eop_kernel_addr, 0, PAGE_SIZE);
++	}
+ 
+ 	retval = kfd_gtt_sa_allocate(dev, sizeof(*kq->rptr_kernel),
+ 					&kq->rptr_mem);
+@@ -201,7 +209,12 @@ static void uninitialize(struct kernel_queue *kq)
+ 
+ 	kfd_gtt_sa_free(kq->dev, kq->rptr_mem);
+ 	kfd_gtt_sa_free(kq->dev, kq->wptr_mem);
+-	kq->ops_asic_specific.uninitialize(kq);
++
++	/* For CIK family asics, kq->eop_mem is Null, kfd_gtt_sa_free()
++	 * is able to handle NULL properly.
++	 */
++	kfd_gtt_sa_free(kq->dev, kq->eop_mem);
++
+ 	kfd_gtt_sa_free(kq->dev, kq->pq);
+ 	kfd_release_kernel_doorbell(kq->dev,
+ 					kq->queue->properties.doorbell_ptr);
+@@ -314,8 +327,15 @@ static void submit_packet(struct kernel_queue *kq)
+ 	}
+ 	pr_debug("\n");
+ #endif
+-
+-	kq->ops_asic_specific.submit_packet(kq);
++	if (kq->dev->device_info->doorbell_size == 8) {
++		*kq->wptr64_kernel = kq->pending_wptr64;
++		write_kernel_doorbell64(kq->queue->properties.doorbell_ptr,
++					kq->pending_wptr64);
++	} else {
++		*kq->wptr_kernel = kq->pending_wptr;
++		write_kernel_doorbell(kq->queue->properties.doorbell_ptr,
++					kq->pending_wptr);
++	}
+ }
+ 
+ static void rollback_packet(struct kernel_queue *kq)
+@@ -345,42 +365,11 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
+ 	kq->ops.submit_packet = submit_packet;
+ 	kq->ops.rollback_packet = rollback_packet;
+ 
+-	switch (dev->device_info->asic_family) {
+-	case CHIP_KAVERI:
+-	case CHIP_HAWAII:
+-	case CHIP_CARRIZO:
+-	case CHIP_TONGA:
+-	case CHIP_FIJI:
+-	case CHIP_POLARIS10:
+-	case CHIP_POLARIS11:
+-	case CHIP_POLARIS12:
+-	case CHIP_VEGAM:
+-		kernel_queue_init_vi(&kq->ops_asic_specific);
+-		break;
+-
+-	case CHIP_VEGA10:
+-	case CHIP_VEGA12:
+-	case CHIP_VEGA20:
+-	case CHIP_RAVEN:
+-	case CHIP_RENOIR:
+-	case CHIP_ARCTURUS:
+-	case CHIP_NAVI10:
+-	case CHIP_NAVI12:
+-	case CHIP_NAVI14:
+-		kernel_queue_init_v9(&kq->ops_asic_specific);
+-		break;
+-	default:
+-		WARN(1, "Unexpected ASIC family %u",
+-		     dev->device_info->asic_family);
+-		goto out_free;
+-	}
+-
+ 	if (kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE))
+ 		return kq;
+ 
+ 	pr_err("Failed to init kernel queue\n");
+ 
+-out_free:
+ 	kfree(kq);
+ 	return NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
+index b22ff0fb40fe..852de7466cc4 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
+@@ -76,7 +76,6 @@ struct kernel_queue_ops {
+ 
+ struct kernel_queue {
+ 	struct kernel_queue_ops ops;
+-	struct kernel_queue_ops ops_asic_specific;
+ 
+ 	/* data */
+ 	struct kfd_dev		*dev;
+@@ -109,7 +108,4 @@ struct kernel_queue {
+ 	struct list_head	list;
+ };
+ 
+-void kernel_queue_init_vi(struct kernel_queue_ops *ops);
+-void kernel_queue_init_v9(struct kernel_queue_ops *ops);
+-
+ #endif /* KFD_KERNEL_QUEUE_H_ */
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+index a3d0b4cf16c6..11c2d85fd614 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+@@ -27,42 +27,6 @@
+ #include "kfd_pm4_opcodes.h"
+ #include "gc/gc_10_1_0_sh_mask.h"
+ 
+-static bool initialize_v9(struct kernel_queue *kq, struct kfd_dev *dev,
+-			enum kfd_queue_type type, unsigned int queue_size)
+-{
+-	int retval;
+-
+-	retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, &kq->eop_mem);
+-	if (retval)
+-		return false;
+-
+-	kq->eop_gpu_addr = kq->eop_mem->gpu_addr;
+-	kq->eop_kernel_addr = kq->eop_mem->cpu_ptr;
+-
+-	memset(kq->eop_kernel_addr, 0, PAGE_SIZE);
+-
+-	return true;
+-}
+-
+-static void uninitialize_v9(struct kernel_queue *kq)
+-{
+-	kfd_gtt_sa_free(kq->dev, kq->eop_mem);
+-}
+-
+-static void submit_packet_v9(struct kernel_queue *kq)
+-{
+-	*kq->wptr64_kernel = kq->pending_wptr64;
+-	write_kernel_doorbell64(kq->queue->properties.doorbell_ptr,
+-				kq->pending_wptr64);
+-}
+-
+-void kernel_queue_init_v9(struct kernel_queue_ops *ops)
+-{
+-	ops->initialize = initialize_v9;
+-	ops->uninitialize = uninitialize_v9;
+-	ops->submit_packet = submit_packet_v9;
+-}
+-
+ static int pm_map_process_v9(struct packet_manager *pm,
+ 		uint32_t *buffer, struct qcm_process_device *qpd)
+ {
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
+index 9b0380d91bfb..faf0bae8223b 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
+@@ -26,54 +26,6 @@
+ #include "kfd_pm4_headers_vi.h"
+ #include "kfd_pm4_opcodes.h"
+ 
+-static bool initialize_vi(struct kernel_queue *kq, struct kfd_dev *dev,
+-			enum kfd_queue_type type, unsigned int queue_size);
+-static void uninitialize_vi(struct kernel_queue *kq);
+-static void submit_packet_vi(struct kernel_queue *kq);
+-
+-void kernel_queue_init_vi(struct kernel_queue_ops *ops)
+-{
+-	ops->initialize = initialize_vi;
+-	ops->uninitialize = uninitialize_vi;
+-	ops->submit_packet = submit_packet_vi;
+-}
+-
+-static bool initialize_vi(struct kernel_queue *kq, struct kfd_dev *dev,
+-			enum kfd_queue_type type, unsigned int queue_size)
+-{
+-	int retval;
+-
+-	/*For CIK family asics, kq->eop_mem is not needed */
+-	if (dev->device_info->asic_family <= CHIP_MULLINS)
+-		return true;
+-
+-	retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, &kq->eop_mem);
+-	if (retval != 0)
+-		return false;
+-
+-	kq->eop_gpu_addr = kq->eop_mem->gpu_addr;
+-	kq->eop_kernel_addr = kq->eop_mem->cpu_ptr;
+-
+-	memset(kq->eop_kernel_addr, 0, PAGE_SIZE);
+-
+-	return true;
+-}
+-
+-static void uninitialize_vi(struct kernel_queue *kq)
+-{
+-	/* For CIK family asics, kq->eop_mem is Null, kfd_gtt_sa_free()
+-	 * is able to handle NULL properly.
+-	 */
+-	kfd_gtt_sa_free(kq->dev, kq->eop_mem);
+-}
+-
+-static void submit_packet_vi(struct kernel_queue *kq)
+-{
+-	*kq->wptr_kernel = kq->pending_wptr;
+-	write_kernel_doorbell(kq->queue->properties.doorbell_ptr,
+-				kq->pending_wptr);
+-}
+-
+ unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size)
+ {
+ 	union PM4_MES_TYPE_3_HEADER header;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4437-drm-amdkfd-Rename-kfd_kernel_queue_-.c-to-kfd_packet.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4437-drm-amdkfd-Rename-kfd_kernel_queue_-.c-to-kfd_packet.patch
new file mode 100644
index 00000000..ac106e1f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4437-drm-amdkfd-Rename-kfd_kernel_queue_-.c-to-kfd_packet.patch
@@ -0,0 +1,48 @@
+From 257a195bdb74fd055882e998963f155812ac2d3a Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Wed, 13 Nov 2019 17:03:11 -0500
+Subject: [PATCH 4437/4736] drm/amdkfd: Rename kfd_kernel_queue_*.c to
+ kfd_packet_manager_*.c
+
+After the recent cleanup, the functionalities provided by the previous
+kfd_kernel_queue_*.c are actually all packet manager related. So rename
+them to reflect that.
+
+Change-Id: I6544ccb38da827c747544c0787aa949df20edbb0
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/Makefile                           | 4 ++--
+ .../amdkfd/{kfd_kernel_queue_v9.c => kfd_packet_manager_v9.c} | 0
+ .../amdkfd/{kfd_kernel_queue_vi.c => kfd_packet_manager_vi.c} | 0
+ 3 files changed, 2 insertions(+), 2 deletions(-)
+ rename drivers/gpu/drm/amd/amdkfd/{kfd_kernel_queue_v9.c => kfd_packet_manager_v9.c} (100%)
+ rename drivers/gpu/drm/amd/amdkfd/{kfd_kernel_queue_vi.c => kfd_packet_manager_vi.c} (100%)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile
+index a34a4a65970f..a09e4a5d754f 100644
+--- a/drivers/gpu/drm/amd/amdkfd/Makefile
++++ b/drivers/gpu/drm/amd/amdkfd/Makefile
+@@ -38,9 +38,9 @@ AMDKFD_FILES	:= $(AMDKFD_PATH)/kfd_module.o \
+ 		$(AMDKFD_PATH)/kfd_mqd_manager_v9.o \
+ 		$(AMDKFD_PATH)/kfd_mqd_manager_v10.o \
+ 		$(AMDKFD_PATH)/kfd_kernel_queue.o \
+-		$(AMDKFD_PATH)/kfd_kernel_queue_vi.o \
+-		$(AMDKFD_PATH)/kfd_kernel_queue_v9.o \
+ 		$(AMDKFD_PATH)/kfd_packet_manager.o \
++		$(AMDKFD_PATH)/kfd_packet_manager_vi.o \
++		$(AMDKFD_PATH)/kfd_packet_manager_v9.o \
+ 		$(AMDKFD_PATH)/kfd_process_queue_manager.o \
+ 		$(AMDKFD_PATH)/kfd_device_queue_manager.o \
+ 		$(AMDKFD_PATH)/kfd_device_queue_manager_cik.o \
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c
+similarity index 100%
+rename from drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
+rename to drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c
+similarity index 100%
+rename from drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
+rename to drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4438-drm-amdgpu-powerplay-properly-set-PP_GFXOFF_MASK.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4438-drm-amdgpu-powerplay-properly-set-PP_GFXOFF_MASK.patch
new file mode 100644
index 00000000..cae549dc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4438-drm-amdgpu-powerplay-properly-set-PP_GFXOFF_MASK.patch
@@ -0,0 +1,91 @@
+From e801571aa584fe7f275becec8aee71ace73288ed Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 13 Nov 2019 11:08:35 -0500
+Subject: [PATCH 4438/4736] drm/amdgpu/powerplay: properly set PP_GFXOFF_MASK
+
+So that the setting reflects what the hw supports. This will
+be used in a subsequent patch so needs to be correct.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c  | 2 ++
+ drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 7 +++++++
+ 2 files changed, 9 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 18da3b393f96..f4bb804acbeb 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -719,6 +719,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_VEGA20:
++		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ 		vega20_set_ppt_funcs(smu);
+ 		break;
+ 	case CHIP_NAVI10:
+@@ -727,6 +728,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
+ 		navi10_set_ppt_funcs(smu);
+ 		break;
+ 	case CHIP_ARCTURUS:
++		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ 		arcturus_set_ppt_funcs(smu);
+ 		/* OD is not supported on Arcturus */
+ 		smu->od_enabled =false;
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+index e8d4292bc4f0..72f2b09195dc 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+@@ -81,6 +81,8 @@ static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
+ 
+ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
+ {
++	struct amdgpu_device *adev = hwmgr->adev;
++
+ 	if (!hwmgr)
+ 		return -EINVAL;
+ 
+@@ -96,6 +98,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
+ 
+ 	switch (hwmgr->chip_family) {
+ 	case AMDGPU_FAMILY_CI:
++		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ 		hwmgr->smumgr_funcs = &ci_smu_funcs;
+ 		ci_set_asic_special_caps(hwmgr);
+ 		hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
+@@ -106,12 +109,14 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
+ 		smu7_init_function_pointers(hwmgr);
+ 		break;
+ 	case AMDGPU_FAMILY_CZ:
++		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ 		hwmgr->od_enabled = false;
+ 		hwmgr->smumgr_funcs = &smu8_smu_funcs;
+ 		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
+ 		smu8_init_function_pointers(hwmgr);
+ 		break;
+ 	case AMDGPU_FAMILY_VI:
++		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ 		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
+ 		switch (hwmgr->chip_id) {
+ 		case CHIP_TOPAZ:
+@@ -153,6 +158,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
+ 	case AMDGPU_FAMILY_AI:
+ 		switch (hwmgr->chip_id) {
+ 		case CHIP_VEGA10:
++			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ 			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
+ 			hwmgr->smumgr_funcs = &vega10_smu_funcs;
+ 			vega10_hwmgr_init(hwmgr);
+@@ -162,6 +168,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
+ 			vega12_hwmgr_init(hwmgr);
+ 			break;
+ 		case CHIP_VEGA20:
++			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ 			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
+ 			hwmgr->smumgr_funcs = &vega20_smu_funcs;
+ 			vega20_hwmgr_init(hwmgr);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4439-drm-amdgpu-don-t-read-registers-if-gfxoff-is-enabled.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4439-drm-amdgpu-don-t-read-registers-if-gfxoff-is-enabled.patch
new file mode 100644
index 00000000..1aba1752
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4439-drm-amdgpu-don-t-read-registers-if-gfxoff-is-enabled.patch
@@ -0,0 +1,126 @@
+From 3aaf57ff28015d3d07f80b8c1540d75b2d20f288 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 12 Nov 2019 09:46:54 -0500
+Subject: [PATCH 4439/4736] drm/amdgpu: don't read registers if gfxoff is
+ enabled (v2)
+
+When gfxoff is enabled, accessing gfx registers via MMIO
+can lead to a hang.
+
+v2: return cached registers properly.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c    | 27 ++++++++++++++++----------
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 31 ++++++++++++++++++------------
+ 2 files changed, 36 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index b33da33214eb..be761785b2a8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -200,17 +200,25 @@ static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
+ 	return val;
+ }
+ 
+-static uint32_t nv_get_register_value(struct amdgpu_device *adev,
++static int nv_get_register_value(struct amdgpu_device *adev,
+ 				      bool indexed, u32 se_num,
+-				      u32 sh_num, u32 reg_offset)
++				      u32 sh_num, u32 reg_offset,
++				      u32 *value)
+ {
+ 	if (indexed) {
+-		return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
++		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
++			return -EINVAL;
++		*value = nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
+ 	} else {
+-		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
+-			return adev->gfx.config.gb_addr_config;
+-		return RREG32(reg_offset);
++		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) {
++			*value = adev->gfx.config.gb_addr_config;
++		} else {
++			if (adev->pm.pp_feature & PP_GFXOFF_MASK)
++				return -EINVAL;
++			*value = RREG32(reg_offset);
++		}
+ 	}
++	return 0;
+ }
+ 
+ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
+@@ -226,10 +234,9 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
+ 		    (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
+ 			continue;
+ 
+-		*value = nv_get_register_value(adev,
+-					       nv_allowed_read_registers[i].grbm_indexed,
+-					       se_num, sh_num, reg_offset);
+-		return 0;
++		return nv_get_register_value(adev,
++					     nv_allowed_read_registers[i].grbm_indexed,
++					     se_num, sh_num, reg_offset, value);
+ 	}
+ 	return -EINVAL;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index e12cdbdd9aed..836a34c10db2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -362,19 +362,27 @@ static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_n
+ 	return val;
+ }
+ 
+-static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
++static int soc15_get_register_value(struct amdgpu_device *adev,
+ 					 bool indexed, u32 se_num,
+-					 u32 sh_num, u32 reg_offset)
++					 u32 sh_num, u32 reg_offset,
++					 u32 *value)
+ {
+ 	if (indexed) {
+-		return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
++		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
++			return -EINVAL;
++	        *value = soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
+ 	} else {
+-		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
+-			return adev->gfx.config.gb_addr_config;
+-		else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
+-			return adev->gfx.config.db_debug2;
+-		return RREG32(reg_offset);
++		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) {
++			*value = adev->gfx.config.gb_addr_config;
++		} else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) {
++			*value = adev->gfx.config.db_debug2;
++		} else {
++			if (adev->pm.pp_feature & PP_GFXOFF_MASK)
++				return -EINVAL;
++			*value = RREG32(reg_offset);
++		}
+ 	}
++	return 0;
+ }
+ 
+ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
+@@ -390,10 +398,9 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
+ 					+ en->reg_offset))
+ 			continue;
+ 
+-		*value = soc15_get_register_value(adev,
+-						  soc15_allowed_read_registers[i].grbm_indexed,
+-						  se_num, sh_num, reg_offset);
+-		return 0;
++		return soc15_get_register_value(adev,
++						soc15_allowed_read_registers[i].grbm_indexed,
++						se_num, sh_num, reg_offset, value);
+ 	}
+ 	return -EINVAL;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4440-drm-amdgpu-enable-ras-capablity-check-on-arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4440-drm-amdgpu-enable-ras-capablity-check-on-arcturus.patch
new file mode 100644
index 00000000..e64d58fd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4440-drm-amdgpu-enable-ras-capablity-check-on-arcturus.patch
@@ -0,0 +1,31 @@
+From feda5cc8a0337d8922decc724ccad100cc3a1294 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 13 Nov 2019 22:24:12 +0800
+Subject: [PATCH 4440/4736] drm/amdgpu: enable ras capablity check on arcturus
+
+check hw ras capablity via atomfirmware
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: John Clements <John.Clements@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index 399617932427..bbd4fd5d7850 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -1685,7 +1685,8 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
+ 	*supported = 0;
+ 
+ 	if (amdgpu_sriov_vf(adev) ||
+-			adev->asic_type != CHIP_VEGA20)
++	    (adev->asic_type != CHIP_VEGA20 &&
++	     adev->asic_type != CHIP_ARCTURUS))
+ 		return;
+ 
+ 	if (adev->is_atom_fw &&
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4441-drm-amdgpu-init-umc-functions-for-arcturus-umc-ras.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4441-drm-amdgpu-init-umc-functions-for-arcturus-umc-ras.patch
new file mode 100644
index 00000000..651dd29b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4441-drm-amdgpu-init-umc-functions-for-arcturus-umc-ras.patch
@@ -0,0 +1,37 @@
+From 26767064660a45a4b91a1eed997a360bb6fe723e Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 13 Nov 2019 22:26:22 +0800
+Subject: [PATCH 4441/4736] drm/amdgpu: init umc functions for arcturus umc ras
+
+reuse vg20 umc functions for arcturus umc ras
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: John Clements <John.Clements@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 6ddb8bdf77cc..db4582925b8d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -635,6 +635,7 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
+ 		adev->umc.funcs = &umc_v6_0_funcs;
+ 		break;
+ 	case CHIP_VEGA20:
++	case CHIP_ARCTURUS:
+ 		adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
+ 		adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
+ 		adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
+@@ -748,6 +749,7 @@ static int gmc_v9_0_late_init(void *handle)
+ 		switch (adev->asic_type) {
+ 		case CHIP_VEGA10:
+ 		case CHIP_VEGA20:
++		case CHIP_ARCTURUS:
+ 			r = amdgpu_atomfirmware_mem_ecc_supported(adev);
+ 			if (!r) {
+ 				DRM_INFO("ECC is not present.\n");
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4442-drm-amdgpu-gfx10-fix-mqd-backup-restore-for-gfx-ring.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4442-drm-amdgpu-gfx10-fix-mqd-backup-restore-for-gfx-ring.patch
new file mode 100644
index 00000000..dbcee19c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4442-drm-amdgpu-gfx10-fix-mqd-backup-restore-for-gfx-ring.patch
@@ -0,0 +1,61 @@
+From fcba8e7d0b5d92ad1455239d3f4f1ca4f973f888 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Tue, 29 Oct 2019 16:59:09 +0800
+Subject: [PATCH 4442/4736] drm/amdgpu/gfx10: fix mqd backup/restore for gfx
+ rings
+
+1. no need to allocate an extra member for 'mqd_backup' array
+2. backup/restore mqd to/from the correct 'mqd_backup' array slot
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 +-
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 9 +++++----
+ 2 files changed, 6 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+index a74ecd449775..0ae0a2715b0d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+@@ -225,7 +225,7 @@ struct amdgpu_me {
+ 	uint32_t			num_me;
+ 	uint32_t			num_pipe_per_me;
+ 	uint32_t			num_queue_per_pipe;
+-	void				*mqd_backup[AMDGPU_MAX_GFX_RINGS + 1];
++	void				*mqd_backup[AMDGPU_MAX_GFX_RINGS];
+ 
+ 	/* These are the resources for which amdgpu takes ownership */
+ 	DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index e4b4f4b09329..9274bd4b6c68 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -3118,6 +3118,7 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
++	int mqd_idx = ring - &adev->gfx.gfx_ring[0];
+ 
+ 	if (!adev->in_gpu_reset && !adev->in_suspend) {
+ 		memset((void *)mqd, 0, sizeof(*mqd));
+@@ -3129,12 +3130,12 @@ static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
+ #endif
+ 		nv_grbm_select(adev, 0, 0, 0, 0);
+ 		mutex_unlock(&adev->srbm_mutex);
+-		if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS])
+-			memcpy(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], mqd, sizeof(*mqd));
++		if (adev->gfx.me.mqd_backup[mqd_idx])
++			memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
+ 	} else if (adev->in_gpu_reset) {
+ 		/* reset mqd with the backup copy */
+-		if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS])
+-			memcpy(mqd, adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], sizeof(*mqd));
++		if (adev->gfx.me.mqd_backup[mqd_idx])
++			memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
+ 		/* reset the ring */
+ 		ring->wptr = 0;
+ 		adev->wb.wb[ring->wptr_offs] = 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4443-drm-amdgpu-add-JPEG-HW-IP-and-SW-structures.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4443-drm-amdgpu-add-JPEG-HW-IP-and-SW-structures.patch
new file mode 100644
index 00000000..8e58ca5f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4443-drm-amdgpu-add-JPEG-HW-IP-and-SW-structures.patch
@@ -0,0 +1,100 @@
+From cec3b16f457e14003559707bd0bb5c2f40953630 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 10:00:24 -0500
+Subject: [PATCH 4443/4736] drm/amdgpu: add JPEG HW IP and SW structures
+
+It will be used for JPEG IP 1.0, 2.0, 2.5 and later.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  5 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 46 ++++++++++++++++++++++++
+ 2 files changed, 51 insertions(+)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 715739799383..9915f0472611 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -70,6 +70,7 @@
+ #include "amdgpu_uvd.h"
+ #include "amdgpu_vce.h"
+ #include "amdgpu_vcn.h"
++#include "amdgpu_jpeg.h"
+ #include "amdgpu_mn.h"
+ #include "amdgpu_gmc.h"
+ #include "amdgpu_gfx.h"
+@@ -724,6 +725,7 @@ enum amd_hw_ip_block_type {
+ 	MP1_HWIP,
+ 	UVD_HWIP,
+ 	VCN_HWIP = UVD_HWIP,
++	JPEG_HWIP = VCN_HWIP,
+ 	VCE_HWIP,
+ 	DF_HWIP,
+ 	DCE_HWIP,
+@@ -944,6 +946,9 @@ struct amdgpu_device {
+ 	/* vcn */
+ 	struct amdgpu_vcn		vcn;
+ 
++	/* jpeg */
++	struct amdgpu_jpeg		jpeg;
++
+ 	/* firmwares */
+ 	struct amdgpu_firmware		firmware;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+new file mode 100644
+index 000000000000..36e2b7340c97
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+@@ -0,0 +1,46 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __AMDGPU_JPEG_H__
++#define __AMDGPU_JPEG_H__
++
++#define AMDGPU_MAX_JPEG_INSTANCES	2
++
++struct amdgpu_jpeg_reg{
++	unsigned jpeg_pitch;
++};
++
++struct amdgpu_jpeg_inst {
++	struct amdgpu_ring ring_dec;
++	struct amdgpu_irq_src irq;
++	struct amdgpu_jpeg_reg external;
++};
++
++struct amdgpu_jpeg {
++	uint8_t	num_jpeg_inst;
++	struct amdgpu_jpeg_inst inst[AMDGPU_MAX_JPEG_INSTANCES];
++	struct amdgpu_jpeg_reg internal;
++	unsigned harvest_config;
++};
++
++#endif /*__AMDGPU_JPEG_H__*/
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4444-drm-amdgpu-add-amdgpu_jpeg-and-JPEG-tests.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4444-drm-amdgpu-add-amdgpu_jpeg-and-JPEG-tests.patch
new file mode 100644
index 00000000..5e0114d3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4444-drm-amdgpu-add-amdgpu_jpeg-and-JPEG-tests.patch
@@ -0,0 +1,194 @@
+From c444d485db6eb0a248933b19d714d86030a2183e Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 10:07:56 -0500
+Subject: [PATCH 4444/4736] drm/amdgpu: add amdgpu_jpeg and JPEG tests
+
+It will be used for all versions of JPEG eventually. Previous
+JPEG tests will be removed later since they are still used by
+JPEG2.x.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile      |   5 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 135 +++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h |   3 +
+ 3 files changed, 141 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index d2fa7313c876..e73f71bd99c2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -148,12 +148,13 @@ amdgpu-y += \
+ 	vce_v3_0.o \
+ 	vce_v4_0.o
+ 
+-# add VCN block
++# add VCN and JPEG block
+ amdgpu-y += \
+ 	amdgpu_vcn.o \
+ 	vcn_v1_0.o \
+ 	vcn_v2_0.o \
+-	vcn_v2_5.o
++	vcn_v2_5.o \
++	amdgpu_jpeg.o
+ 
+ # add ATHUB block
+ amdgpu-y += \
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
+new file mode 100644
+index 000000000000..d9a547d4d3b2
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
+@@ -0,0 +1,135 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the
++ * "Software"), to deal in the Software without restriction, including
++ * without limitation the rights to use, copy, modify, merge, publish,
++ * distribute, sub license, and/or sell copies of the Software, and to
++ * permit persons to whom the Software is furnished to do so, subject to
++ * the following conditions:
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
++ * USE OR OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * The above copyright notice and this permission notice (including the
++ * next paragraph) shall be included in all copies or substantial portions
++ * of the Software.
++ *
++ */
++
++#include "amdgpu.h"
++#include "amdgpu_jpeg.h"
++#include "soc15d.h"
++#include "soc15_common.h"
++
++int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	uint32_t tmp = 0;
++	unsigned i;
++	int r;
++
++	WREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD);
++	r = amdgpu_ring_alloc(ring, 3);
++	if (r)
++		return r;
++
++	amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch, 0));
++	amdgpu_ring_write(ring, 0xDEADBEEF);
++	amdgpu_ring_commit(ring);
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch);
++		if (tmp == 0xDEADBEEF)
++			break;
++		udelay(1);
++	}
++
++	if (i >= adev->usec_timeout)
++		r = -ETIMEDOUT;
++
++	return r;
++}
++
++static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *ring, uint32_t handle,
++		struct dma_fence **fence)
++{
++	struct amdgpu_device *adev = ring->adev;
++	struct amdgpu_job *job;
++	struct amdgpu_ib *ib;
++	struct dma_fence *f = NULL;
++	const unsigned ib_size_dw = 16;
++	int i, r;
++
++	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
++	if (r)
++		return r;
++
++	ib = &job->ibs[0];
++
++	ib->ptr[0] = PACKETJ(adev->jpeg.internal.jpeg_pitch, 0, 0, PACKETJ_TYPE0);
++	ib->ptr[1] = 0xDEADBEEF;
++	for (i = 2; i < 16; i += 2) {
++		ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
++		ib->ptr[i+1] = 0;
++	}
++	ib->length_dw = 16;
++
++	r = amdgpu_job_submit_direct(job, ring, &f);
++	if (r)
++		goto err;
++
++	if (fence)
++		*fence = dma_fence_get(f);
++	dma_fence_put(f);
++
++	return 0;
++
++err:
++	amdgpu_job_free(job);
++	return r;
++}
++
++int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
++{
++	struct amdgpu_device *adev = ring->adev;
++	uint32_t tmp = 0;
++	unsigned i;
++	struct dma_fence *fence = NULL;
++	long r = 0;
++
++	r = amdgpu_jpeg_dec_set_reg(ring, 1, &fence);
++	if (r)
++		goto error;
++
++	r = dma_fence_wait_timeout(fence, false, timeout);
++	if (r == 0) {
++		r = -ETIMEDOUT;
++		goto error;
++	} else if (r < 0) {
++		goto error;
++	} else {
++		r = 0;
++	}
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch);
++		if (tmp == 0xDEADBEEF)
++			break;
++		udelay(1);
++	}
++
++	if (i >= adev->usec_timeout)
++		r = -ETIMEDOUT;
++
++	dma_fence_put(fence);
++error:
++	return r;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+index 36e2b7340c97..a8d988c25f45 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+@@ -43,4 +43,7 @@ struct amdgpu_jpeg {
+ 	unsigned harvest_config;
+ };
+ 
++int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring);
++int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
++
+ #endif /*__AMDGPU_JPEG_H__*/
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4445-drm-amdgpu-separate-JPEG1.0-code-out-from-VCN1.0.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4445-drm-amdgpu-separate-JPEG1.0-code-out-from-VCN1.0.patch
new file mode 100644
index 00000000..0cf4e9ae
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4445-drm-amdgpu-separate-JPEG1.0-code-out-from-VCN1.0.patch
@@ -0,0 +1,1252 @@
+From 61fef67dd52e80e895970d745aff4fdec783ad80 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 10:17:06 -0500
+Subject: [PATCH 4445/4736] drm/amdgpu: separate JPEG1.0 code out from VCN1.0
+
+For VCN1.0, the separation is just in code wise, JPEG1.0 HW is still
+included in the VCN1.0 HW.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile    |   3 +-
+ drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 584 +++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h |  32 ++
+ drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c  | 481 +-------------------
+ 4 files changed, 630 insertions(+), 470 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index e73f71bd99c2..62ef3d7955d9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -154,7 +154,8 @@ amdgpu-y += \
+ 	vcn_v1_0.o \
+ 	vcn_v2_0.o \
+ 	vcn_v2_5.o \
+-	amdgpu_jpeg.o
++	amdgpu_jpeg.o \
++	jpeg_v1_0.o
+ 
+ # add ATHUB block
+ amdgpu-y += \
+diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
+new file mode 100644
+index 000000000000..553506df077d
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
+@@ -0,0 +1,584 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include "amdgpu.h"
++#include "amdgpu_jpeg.h"
++#include "soc15.h"
++#include "soc15d.h"
++
++#include "vcn/vcn_1_0_offset.h"
++#include "vcn/vcn_1_0_sh_mask.h"
++
++static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
++static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev);
++
++static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
++{
++	struct amdgpu_device *adev = ring->adev;
++	ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
++	if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
++		((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
++		ring->ring[(*ptr)++] = 0;
++		ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);
++	} else {
++		ring->ring[(*ptr)++] = reg_offset;
++		ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0);
++	}
++	ring->ring[(*ptr)++] = val;
++}
++
++static void jpeg_v1_0_decode_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	uint32_t reg, reg_offset, val, mask, i;
++
++	// 1st: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
++	reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
++	reg_offset = (reg << 2);
++	val = lower_32_bits(ring->gpu_addr);
++	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
++
++	// 2nd: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
++	reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
++	reg_offset = (reg << 2);
++	val = upper_32_bits(ring->gpu_addr);
++	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
++
++	// 3rd to 5th: issue MEM_READ commands
++	for (i = 0; i <= 2; i++) {
++		ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2);
++		ring->ring[ptr++] = 0;
++	}
++
++	// 6th: program mmUVD_JRBC_RB_CNTL register to enable NO_FETCH and RPTR write ability
++	reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL);
++	reg_offset = (reg << 2);
++	val = 0x13;
++	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
++
++	// 7th: program mmUVD_JRBC_RB_REF_DATA
++	reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA);
++	reg_offset = (reg << 2);
++	val = 0x1;
++	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
++
++	// 8th: issue conditional register read mmUVD_JRBC_RB_CNTL
++	reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL);
++	reg_offset = (reg << 2);
++	val = 0x1;
++	mask = 0x1;
++
++	ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0);
++	ring->ring[ptr++] = 0x01400200;
++	ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);
++	ring->ring[ptr++] = val;
++	ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
++	if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
++		((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
++		ring->ring[ptr++] = 0;
++		ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3);
++	} else {
++		ring->ring[ptr++] = reg_offset;
++		ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3);
++	}
++	ring->ring[ptr++] = mask;
++
++	//9th to 21st: insert no-op
++	for (i = 0; i <= 12; i++) {
++		ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
++		ring->ring[ptr++] = 0;
++	}
++
++	//22nd: reset mmUVD_JRBC_RB_RPTR
++	reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_RPTR);
++	reg_offset = (reg << 2);
++	val = 0;
++	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
++
++	//23rd: program mmUVD_JRBC_RB_CNTL to disable no_fetch
++	reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL);
++	reg_offset = (reg << 2);
++	val = 0x12;
++	jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val);
++}
++
++/**
++ * jpeg_v1_0_decode_ring_get_rptr - get read pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware read pointer
++ */
++static uint64_t jpeg_v1_0_decode_ring_get_rptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
++}
++
++/**
++ * jpeg_v1_0_decode_ring_get_wptr - get write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware write pointer
++ */
++static uint64_t jpeg_v1_0_decode_ring_get_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
++}
++
++/**
++ * jpeg_v1_0_decode_ring_set_wptr - set write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Commits the write pointer to the hardware
++ */
++static void jpeg_v1_0_decode_ring_set_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
++}
++
++/**
++ * jpeg_v1_0_decode_ring_insert_start - insert a start command
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Write a start command to the ring.
++ */
++static void jpeg_v1_0_decode_ring_insert_start(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x68e04);
++
++	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x80010000);
++}
++
++/**
++ * jpeg_v1_0_decode_ring_insert_end - insert a end command
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Write a end command to the ring.
++ */
++static void jpeg_v1_0_decode_ring_insert_end(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x68e04);
++
++	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x00010000);
++}
++
++/**
++ * jpeg_v1_0_decode_ring_emit_fence - emit an fence & trap command
++ *
++ * @ring: amdgpu_ring pointer
++ * @fence: fence to emit
++ *
++ * Write a fence and a trap command to the ring.
++ */
++static void jpeg_v1_0_decode_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
++				     unsigned flags)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, seq);
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, seq);
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, lower_32_bits(addr));
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, upper_32_bits(addr));
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x8);
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
++	amdgpu_ring_write(ring, 0);
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x01400200);
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, seq);
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, lower_32_bits(addr));
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, upper_32_bits(addr));
++
++	amdgpu_ring_write(ring,
++		PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2));
++	amdgpu_ring_write(ring, 0xffffffff);
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x3fbc);
++
++	amdgpu_ring_write(ring,
++		PACKETJ(0, 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x1);
++
++	/* emit trap */
++	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
++	amdgpu_ring_write(ring, 0);
++}
++
++/**
++ * jpeg_v1_0_decode_ring_emit_ib - execute indirect buffer
++ *
++ * @ring: amdgpu_ring pointer
++ * @ib: indirect buffer to execute
++ *
++ * Write ring commands to execute the indirect buffer.
++ */
++static void jpeg_v1_0_decode_ring_emit_ib(struct amdgpu_ring *ring,
++					struct amdgpu_job *job,
++					struct amdgpu_ib *ib,
++					uint32_t flags)
++{
++	struct amdgpu_device *adev = ring->adev;
++	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, (vmid | (vmid << 4)));
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, (vmid | (vmid << 4)));
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, ib->length_dw);
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
++
++	amdgpu_ring_write(ring,
++		PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
++	amdgpu_ring_write(ring, 0);
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x01400200);
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x2);
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
++	amdgpu_ring_write(ring, 0x2);
++}
++
++static void jpeg_v1_0_decode_ring_emit_reg_wait(struct amdgpu_ring *ring,
++					    uint32_t reg, uint32_t val,
++					    uint32_t mask)
++{
++	struct amdgpu_device *adev = ring->adev;
++	uint32_t reg_offset = (reg << 2);
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x01400200);
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, val);
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
++	if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
++		((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
++		amdgpu_ring_write(ring, 0);
++		amdgpu_ring_write(ring,
++			PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
++	} else {
++		amdgpu_ring_write(ring, reg_offset);
++		amdgpu_ring_write(ring,
++			PACKETJ(0, 0, 0, PACKETJ_TYPE3));
++	}
++	amdgpu_ring_write(ring, mask);
++}
++
++static void jpeg_v1_0_decode_ring_emit_vm_flush(struct amdgpu_ring *ring,
++		unsigned vmid, uint64_t pd_addr)
++{
++	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
++	uint32_t data0, data1, mask;
++
++	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
++
++	/* wait for register write */
++	data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
++	data1 = lower_32_bits(pd_addr);
++	mask = 0xffffffff;
++	jpeg_v1_0_decode_ring_emit_reg_wait(ring, data0, data1, mask);
++}
++
++static void jpeg_v1_0_decode_ring_emit_wreg(struct amdgpu_ring *ring,
++					uint32_t reg, uint32_t val)
++{
++	struct amdgpu_device *adev = ring->adev;
++	uint32_t reg_offset = (reg << 2);
++
++	amdgpu_ring_write(ring,
++		PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
++	if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
++			((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
++		amdgpu_ring_write(ring, 0);
++		amdgpu_ring_write(ring,
++			PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
++	} else {
++		amdgpu_ring_write(ring, reg_offset);
++		amdgpu_ring_write(ring,
++			PACKETJ(0, 0, 0, PACKETJ_TYPE0));
++	}
++	amdgpu_ring_write(ring, val);
++}
++
++static void jpeg_v1_0_decode_ring_nop(struct amdgpu_ring *ring, uint32_t count)
++{
++	int i;
++
++	WARN_ON(ring->wptr % 2 || count % 2);
++
++	for (i = 0; i < count / 2; i++) {
++		amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
++		amdgpu_ring_write(ring, 0);
++	}
++}
++
++static int jpeg_v1_0_set_interrupt_state(struct amdgpu_device *adev,
++					struct amdgpu_irq_src *source,
++					unsigned type,
++					enum amdgpu_interrupt_state state)
++{
++	return 0;
++}
++
++static int jpeg_v1_0_process_interrupt(struct amdgpu_device *adev,
++				      struct amdgpu_irq_src *source,
++				      struct amdgpu_iv_entry *entry)
++{
++	DRM_DEBUG("IH: JPEG decode TRAP\n");
++
++	switch (entry->src_id) {
++	case 126:
++		amdgpu_fence_process(&adev->jpeg.inst->ring_dec);
++		break;
++	default:
++		DRM_ERROR("Unhandled interrupt: %d %d\n",
++			  entry->src_id, entry->src_data[0]);
++		break;
++	}
++
++	return 0;
++}
++
++/**
++ * jpeg_v1_0_early_init - set function pointers
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Set ring and irq function pointers
++ */
++int jpeg_v1_0_early_init(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++	adev->jpeg.num_jpeg_inst = 1;
++
++	jpeg_v1_0_set_dec_ring_funcs(adev);
++	jpeg_v1_0_set_irq_funcs(adev);
++
++	return 0;
++}
++
++/**
++ * jpeg_v1_0_sw_init - sw init for JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ */
++int jpeg_v1_0_sw_init(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	struct amdgpu_ring *ring;
++	int r;
++
++	/* JPEG TRAP */
++	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->jpeg.inst->irq);
++	if (r)
++		return r;
++
++	ring = &adev->jpeg.inst->ring_dec;
++	sprintf(ring->name, "jpeg_dec");
++	r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0);
++	if (r)
++		return r;
++
++	adev->jpeg.internal.jpeg_pitch = adev->jpeg.inst->external.jpeg_pitch =
++		SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
++
++	return 0;
++}
++
++/**
++ * jpeg_v1_0_sw_fini - sw fini for JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * JPEG free up sw allocation
++ */
++void jpeg_v1_0_sw_fini(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++	amdgpu_ring_fini(&adev->jpeg.inst[0].ring_dec);
++}
++
++/**
++ * jpeg_v1_0_start - start JPEG block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Setup and start the JPEG block
++ */
++void jpeg_v1_0_start(struct amdgpu_device *adev, int mode)
++{
++	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
++
++	if (mode == 0) {
++		WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
++		WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
++				UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
++		WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
++		WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
++		WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
++		WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
++	}	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
++
++	/* initialize wptr */
++	ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
++
++	/* copy patch commands to the jpeg ring */
++	jpeg_v1_0_decode_ring_set_patch_ring(ring,
++		(ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
++}
++
++static const struct amdgpu_ring_funcs jpeg_v1_0_decode_ring_vm_funcs = {
++	.type = AMDGPU_RING_TYPE_VCN_JPEG,
++	.align_mask = 0xf,
++	.nop = PACKET0(0x81ff, 0),
++	.support_64bit_ptrs = false,
++	.no_user_fence = true,
++	.vmhub = AMDGPU_MMHUB_0,
++	.extra_dw = 64,
++	.get_rptr = jpeg_v1_0_decode_ring_get_rptr,
++	.get_wptr = jpeg_v1_0_decode_ring_get_wptr,
++	.set_wptr = jpeg_v1_0_decode_ring_set_wptr,
++	.emit_frame_size =
++		6 + 6 + /* hdp invalidate / flush */
++		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
++		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
++		8 + /* jpeg_v1_0_decode_ring_emit_vm_flush */
++		26 + 26 + /* jpeg_v1_0_decode_ring_emit_fence x2 vm fence */
++		6,
++	.emit_ib_size = 22, /* jpeg_v1_0_decode_ring_emit_ib */
++	.emit_ib = jpeg_v1_0_decode_ring_emit_ib,
++	.emit_fence = jpeg_v1_0_decode_ring_emit_fence,
++	.emit_vm_flush = jpeg_v1_0_decode_ring_emit_vm_flush,
++	.test_ring = amdgpu_jpeg_dec_ring_test_ring,
++	.test_ib = amdgpu_jpeg_dec_ring_test_ib,
++	.insert_nop = jpeg_v1_0_decode_ring_nop,
++	.insert_start = jpeg_v1_0_decode_ring_insert_start,
++	.insert_end = jpeg_v1_0_decode_ring_insert_end,
++	.pad_ib = amdgpu_ring_generic_pad_ib,
++	.begin_use = amdgpu_vcn_ring_begin_use,
++	.end_use = amdgpu_vcn_ring_end_use,
++	.emit_wreg = jpeg_v1_0_decode_ring_emit_wreg,
++	.emit_reg_wait = jpeg_v1_0_decode_ring_emit_reg_wait,
++	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
++};
++
++static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
++{
++	adev->jpeg.inst->ring_dec.funcs = &jpeg_v1_0_decode_ring_vm_funcs;
++	DRM_INFO("JPEG decode is enabled in VM mode\n");
++}
++
++static const struct amdgpu_irq_src_funcs jpeg_v1_0_irq_funcs = {
++	.set = jpeg_v1_0_set_interrupt_state,
++	.process = jpeg_v1_0_process_interrupt,
++};
++
++static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->jpeg.inst->irq.funcs = &jpeg_v1_0_irq_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h
+new file mode 100644
+index 000000000000..bbf33a6a3972
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h
+@@ -0,0 +1,32 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __JPEG_V1_0_H__
++#define __JPEG_V1_0_H__
++
++int jpeg_v1_0_early_init(void *handle);
++int jpeg_v1_0_sw_init(void *handle);
++void jpeg_v1_0_sw_fini(void *handle);
++void jpeg_v1_0_start(struct amdgpu_device *adev, int mode);
++
++#endif /*__JPEG_V1_0_H__*/
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+index b23362102e51..ef3cc37802ff 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+@@ -36,6 +36,7 @@
+ #include "mmhub/mmhub_9_1_sh_mask.h"
+ 
+ #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
++#include "jpeg_v1_0.h"
+ 
+ #define mmUVD_RBC_XX_IB_REG_CHECK				0x05ab
+ #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX	1
+@@ -45,9 +46,7 @@
+ static int vcn_v1_0_stop(struct amdgpu_device *adev);
+ static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
+ static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
+-static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
+ static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
+-static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr);
+ static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);
+ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
+ 				struct dpg_pause_state *new_state);
+@@ -68,9 +67,10 @@ static int vcn_v1_0_early_init(void *handle)
+ 
+ 	vcn_v1_0_set_dec_ring_funcs(adev);
+ 	vcn_v1_0_set_enc_ring_funcs(adev);
+-	vcn_v1_0_set_jpeg_ring_funcs(adev);
+ 	vcn_v1_0_set_irq_funcs(adev);
+ 
++	jpeg_v1_0_early_init(handle);
++
+ 	return 0;
+ }
+ 
+@@ -101,11 +101,6 @@ static int vcn_v1_0_sw_init(void *handle)
+ 			return r;
+ 	}
+ 
+-	/* VCN JPEG TRAP */
+-	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.inst->irq);
+-	if (r)
+-		return r;
+-
+ 	r = amdgpu_vcn_sw_init(adev);
+ 	if (r)
+ 		return r;
+@@ -149,17 +144,11 @@ static int vcn_v1_0_sw_init(void *handle)
+ 			return r;
+ 	}
+ 
+-	ring = &adev->vcn.inst->ring_jpeg;
+-	sprintf(ring->name, "vcn_jpeg");
+-	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
+-	if (r)
+-		return r;
+-
+ 	adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode;
+-	adev->vcn.internal.jpeg_pitch = adev->vcn.inst->external.jpeg_pitch =
+-		SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
+ 
+-	return 0;
++	r = jpeg_v1_0_sw_init(handle);
++
++	return r;
+ }
+ 
+ /**
+@@ -178,6 +167,8 @@ static int vcn_v1_0_sw_fini(void *handle)
+ 	if (r)
+ 		return r;
+ 
++	jpeg_v1_0_sw_fini(handle);
++
+ 	r = amdgpu_vcn_sw_fini(adev);
+ 
+ 	return r;
+@@ -207,7 +198,7 @@ static int vcn_v1_0_hw_init(void *handle)
+ 			goto done;
+ 	}
+ 
+-	ring = &adev->vcn.inst->ring_jpeg;
++	ring = &adev->jpeg.inst->ring_dec;
+ 	r = amdgpu_ring_test_helper(ring);
+ 	if (r)
+ 		goto done;
+@@ -947,22 +938,7 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
+ 
+-	ring = &adev->vcn.inst->ring_jpeg;
+-	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
+-	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
+-			UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
+-	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
+-	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
+-	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
+-	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
+-	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
+-
+-	/* initialize wptr */
+-	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+-
+-	/* copy patch commands to the jpeg ring */
+-	vcn_v1_0_jpeg_ring_set_patch_ring(ring,
+-		(ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
++	jpeg_v1_0_start(adev, 0);
+ 
+ 	return 0;
+ }
+@@ -1106,13 +1082,7 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
+ 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
+ 			~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
+ 
+-	/* initialize JPEG wptr */
+-	ring = &adev->vcn.inst->ring_jpeg;
+-	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+-
+-	/* copy patch commands to the jpeg ring */
+-	vcn_v1_0_jpeg_ring_set_patch_ring(ring,
+-		(ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
++	jpeg_v1_0_start(adev, 1);
+ 
+ 	return 0;
+ }
+@@ -1316,7 +1286,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
+ 							UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code);
+ 
+ 				/* Restore */
+-				ring = &adev->vcn.inst->ring_jpeg;
++				ring = &adev->jpeg.inst->ring_dec;
+ 				WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
+ 				WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
+ 							UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
+@@ -1716,389 +1686,6 @@ static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
+ 	amdgpu_ring_write(ring, val);
+ }
+ 
+-
+-/**
+- * vcn_v1_0_jpeg_ring_get_rptr - get read pointer
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Returns the current hardware read pointer
+- */
+-static uint64_t vcn_v1_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-
+-	return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
+-}
+-
+-/**
+- * vcn_v1_0_jpeg_ring_get_wptr - get write pointer
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Returns the current hardware write pointer
+- */
+-static uint64_t vcn_v1_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-
+-	return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+-}
+-
+-/**
+- * vcn_v1_0_jpeg_ring_set_wptr - set write pointer
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Commits the write pointer to the hardware
+- */
+-static void vcn_v1_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-
+-	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
+-}
+-
+-/**
+- * vcn_v1_0_jpeg_ring_insert_start - insert a start command
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Write a start command to the ring.
+- */
+-static void vcn_v1_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x68e04);
+-
+-	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x80010000);
+-}
+-
+-/**
+- * vcn_v1_0_jpeg_ring_insert_end - insert a end command
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Write a end command to the ring.
+- */
+-static void vcn_v1_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x68e04);
+-
+-	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x00010000);
+-}
+-
+-/**
+- * vcn_v1_0_jpeg_ring_emit_fence - emit an fence & trap command
+- *
+- * @ring: amdgpu_ring pointer
+- * @fence: fence to emit
+- *
+- * Write a fence and a trap command to the ring.
+- */
+-static void vcn_v1_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
+-				     unsigned flags)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-
+-	WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, seq);
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, seq);
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, lower_32_bits(addr));
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, upper_32_bits(addr));
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x8);
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
+-	amdgpu_ring_write(ring, 0);
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x01400200);
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, seq);
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, lower_32_bits(addr));
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, upper_32_bits(addr));
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2));
+-	amdgpu_ring_write(ring, 0xffffffff);
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x3fbc);
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(0, 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x1);
+-
+-	/* emit trap */
+-	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
+-	amdgpu_ring_write(ring, 0);
+-}
+-
+-/**
+- * vcn_v1_0_jpeg_ring_emit_ib - execute indirect buffer
+- *
+- * @ring: amdgpu_ring pointer
+- * @ib: indirect buffer to execute
+- *
+- * Write ring commands to execute the indirect buffer.
+- */
+-static void vcn_v1_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
+-					struct amdgpu_job *job,
+-					struct amdgpu_ib *ib,
+-					uint32_t flags)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, (vmid | (vmid << 4)));
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, (vmid | (vmid << 4)));
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, ib->length_dw);
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
+-	amdgpu_ring_write(ring, 0);
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x01400200);
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x2);
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
+-	amdgpu_ring_write(ring, 0x2);
+-}
+-
+-static void vcn_v1_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring,
+-					    uint32_t reg, uint32_t val,
+-					    uint32_t mask)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-	uint32_t reg_offset = (reg << 2);
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x01400200);
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, val);
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
+-	if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
+-		((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
+-		amdgpu_ring_write(ring, 0);
+-		amdgpu_ring_write(ring,
+-			PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
+-	} else {
+-		amdgpu_ring_write(ring, reg_offset);
+-		amdgpu_ring_write(ring,
+-			PACKETJ(0, 0, 0, PACKETJ_TYPE3));
+-	}
+-	amdgpu_ring_write(ring, mask);
+-}
+-
+-static void vcn_v1_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
+-		unsigned vmid, uint64_t pd_addr)
+-{
+-	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+-	uint32_t data0, data1, mask;
+-
+-	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+-
+-	/* wait for register write */
+-	data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
+-	data1 = lower_32_bits(pd_addr);
+-	mask = 0xffffffff;
+-	vcn_v1_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask);
+-}
+-
+-static void vcn_v1_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring,
+-					uint32_t reg, uint32_t val)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-	uint32_t reg_offset = (reg << 2);
+-
+-	amdgpu_ring_write(ring,
+-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
+-	if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
+-			((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
+-		amdgpu_ring_write(ring, 0);
+-		amdgpu_ring_write(ring,
+-			PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
+-	} else {
+-		amdgpu_ring_write(ring, reg_offset);
+-		amdgpu_ring_write(ring,
+-			PACKETJ(0, 0, 0, PACKETJ_TYPE0));
+-	}
+-	amdgpu_ring_write(ring, val);
+-}
+-
+-static void vcn_v1_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
+-{
+-	int i;
+-
+-	WARN_ON(ring->wptr % 2 || count % 2);
+-
+-	for (i = 0; i < count / 2; i++) {
+-		amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
+-		amdgpu_ring_write(ring, 0);
+-	}
+-}
+-
+-static void vcn_v1_0_jpeg_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-	ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
+-	if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
+-		((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
+-		ring->ring[(*ptr)++] = 0;
+-		ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);
+-	} else {
+-		ring->ring[(*ptr)++] = reg_offset;
+-		ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0);
+-	}
+-	ring->ring[(*ptr)++] = val;
+-}
+-
+-static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-
+-	uint32_t reg, reg_offset, val, mask, i;
+-
+-	// 1st: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
+-	reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
+-	reg_offset = (reg << 2);
+-	val = lower_32_bits(ring->gpu_addr);
+-	vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
+-
+-	// 2nd: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
+-	reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
+-	reg_offset = (reg << 2);
+-	val = upper_32_bits(ring->gpu_addr);
+-	vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
+-
+-	// 3rd to 5th: issue MEM_READ commands
+-	for (i = 0; i <= 2; i++) {
+-		ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2);
+-		ring->ring[ptr++] = 0;
+-	}
+-
+-	// 6th: program mmUVD_JRBC_RB_CNTL register to enable NO_FETCH and RPTR write ability
+-	reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
+-	reg_offset = (reg << 2);
+-	val = 0x13;
+-	vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
+-
+-	// 7th: program mmUVD_JRBC_RB_REF_DATA
+-	reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA);
+-	reg_offset = (reg << 2);
+-	val = 0x1;
+-	vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
+-
+-	// 8th: issue conditional register read mmUVD_JRBC_RB_CNTL
+-	reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
+-	reg_offset = (reg << 2);
+-	val = 0x1;
+-	mask = 0x1;
+-
+-	ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0);
+-	ring->ring[ptr++] = 0x01400200;
+-	ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);
+-	ring->ring[ptr++] = val;
+-	ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
+-	if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
+-		((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
+-		ring->ring[ptr++] = 0;
+-		ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3);
+-	} else {
+-		ring->ring[ptr++] = reg_offset;
+-		ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3);
+-	}
+-	ring->ring[ptr++] = mask;
+-
+-	//9th to 21st: insert no-op
+-	for (i = 0; i <= 12; i++) {
+-		ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
+-		ring->ring[ptr++] = 0;
+-	}
+-
+-	//22nd: reset mmUVD_JRBC_RB_RPTR
+-	reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR);
+-	reg_offset = (reg << 2);
+-	val = 0;
+-	vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
+-
+-	//23rd: program mmUVD_JRBC_RB_CNTL to disable no_fetch
+-	reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
+-	reg_offset = (reg << 2);
+-	val = 0x12;
+-	vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
+-}
+-
+ static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
+ 					struct amdgpu_irq_src *source,
+ 					unsigned type,
+@@ -2123,9 +1710,6 @@ static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
+ 	case 120:
+ 		amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
+ 		break;
+-	case 126:
+-		amdgpu_fence_process(&adev->vcn.inst->ring_jpeg);
+-		break;
+ 	default:
+ 		DRM_ERROR("Unhandled interrupt: %d %d\n",
+ 			  entry->src_id, entry->src_data[0]);
+@@ -2259,41 +1843,6 @@ static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
+ 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ };
+ 
+-static const struct amdgpu_ring_funcs vcn_v1_0_jpeg_ring_vm_funcs = {
+-	.type = AMDGPU_RING_TYPE_VCN_JPEG,
+-	.align_mask = 0xf,
+-	.nop = PACKET0(0x81ff, 0),
+-	.support_64bit_ptrs = false,
+-	.no_user_fence = true,
+-	.vmhub = AMDGPU_MMHUB_0,
+-	.extra_dw = 64,
+-	.get_rptr = vcn_v1_0_jpeg_ring_get_rptr,
+-	.get_wptr = vcn_v1_0_jpeg_ring_get_wptr,
+-	.set_wptr = vcn_v1_0_jpeg_ring_set_wptr,
+-	.emit_frame_size =
+-		6 + 6 + /* hdp invalidate / flush */
+-		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
+-		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
+-		8 + /* vcn_v1_0_jpeg_ring_emit_vm_flush */
+-		26 + 26 + /* vcn_v1_0_jpeg_ring_emit_fence x2 vm fence */
+-		6,
+-	.emit_ib_size = 22, /* vcn_v1_0_jpeg_ring_emit_ib */
+-	.emit_ib = vcn_v1_0_jpeg_ring_emit_ib,
+-	.emit_fence = vcn_v1_0_jpeg_ring_emit_fence,
+-	.emit_vm_flush = vcn_v1_0_jpeg_ring_emit_vm_flush,
+-	.test_ring = amdgpu_vcn_jpeg_ring_test_ring,
+-	.test_ib = amdgpu_vcn_jpeg_ring_test_ib,
+-	.insert_nop = vcn_v1_0_jpeg_ring_nop,
+-	.insert_start = vcn_v1_0_jpeg_ring_insert_start,
+-	.insert_end = vcn_v1_0_jpeg_ring_insert_end,
+-	.pad_ib = amdgpu_ring_generic_pad_ib,
+-	.begin_use = amdgpu_vcn_ring_begin_use,
+-	.end_use = amdgpu_vcn_ring_end_use,
+-	.emit_wreg = vcn_v1_0_jpeg_ring_emit_wreg,
+-	.emit_reg_wait = vcn_v1_0_jpeg_ring_emit_reg_wait,
+-	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+-};
+-
+ static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
+ {
+ 	adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
+@@ -2310,12 +1859,6 @@ static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
+ 	DRM_INFO("VCN encode is enabled in VM mode\n");
+ }
+ 
+-static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
+-{
+-	adev->vcn.inst->ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs;
+-	DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
+-}
+-
+ static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
+ 	.set = vcn_v1_0_set_interrupt_state,
+ 	.process = vcn_v1_0_process_interrupt,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4446-drm-amdgpu-use-the-JPEG-structure-for-general-driver.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4446-drm-amdgpu-use-the-JPEG-structure-for-general-driver.patch
new file mode 100644
index 00000000..ffcbfd8a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4446-drm-amdgpu-use-the-JPEG-structure-for-general-driver.patch
@@ -0,0 +1,95 @@
+From acacc1b13681b090b5ccc01dc76706436fd659a4 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 10:23:14 -0500
+Subject: [PATCH 4446/4736] drm/amdgpu: use the JPEG structure for general
+ driver support
+
+JPEG1.0 will be functional along with VCN1.0
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8 +++-----
+ 3 files changed, 8 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+index 0300635f6f63..3ad8ccc6630b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+@@ -172,10 +172,10 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
+ 			}
+ 			break;
+ 		case AMDGPU_HW_IP_VCN_JPEG:
+-			for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
++			for (j = 0; j < adev->jpeg.num_jpeg_inst; ++j) {
+ 				if (adev->vcn.harvest_config & (1 << j))
+ 					continue;
+-				rings[num_rings++] = &adev->vcn.inst[j].ring_jpeg;
++				rings[num_rings++] = &adev->jpeg.inst[j].ring_dec;
+ 			}
+ 			break;
+ 		}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 488258f1138d..ab6e0fc5800f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -398,11 +398,11 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
+ 		break;
+ 	case AMDGPU_HW_IP_VCN_JPEG:
+ 		type = AMD_IP_BLOCK_TYPE_VCN;
+-		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+-			if (adev->uvd.harvest_config & (1 << i))
++		for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
++			if (adev->jpeg.harvest_config & (1 << i))
+ 				continue;
+ 
+-			if (adev->vcn.inst[i].ring_jpeg.sched.ready)
++			if (adev->jpeg.inst[i].ring_dec.sched.ready)
+ 				++num_rings;
+ 		}
+ 		ib_start_alignment = 16;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+index c72819d55502..9daa42f03886 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+@@ -213,8 +213,6 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
+ 
+ 		for (i = 0; i < adev->vcn.num_enc_rings; ++i)
+ 			amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
+-
+-		amdgpu_ring_fini(&adev->vcn.inst[j].ring_jpeg);
+ 	}
+ 
+ 	release_firmware(adev->vcn.fw);
+@@ -307,7 +305,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
+ 			else
+ 				new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
+ 
+-			if (amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg))
++			if (amdgpu_fence_count_emitted(&adev->jpeg.inst[j].ring_dec))
+ 				new_state.jpeg = VCN_DPG_STATE__PAUSE;
+ 			else
+ 				new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+@@ -315,7 +313,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
+ 			adev->vcn.pause_dpg_mode(adev, &new_state);
+ 		}
+ 
+-		fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg);
++		fence[j] += amdgpu_fence_count_emitted(&adev->jpeg.inst[j].ring_dec);
+ 		fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
+ 		fences += fence[j];
+ 	}
+@@ -359,7 +357,7 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
+ 		else
+ 			new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
+ 
+-		if (amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_jpeg))
++		if (amdgpu_fence_count_emitted(&adev->jpeg.inst[ring->me].ring_dec))
+ 			new_state.jpeg = VCN_DPG_STATE__PAUSE;
+ 		else
+ 			new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4447-drm-amdgpu-add-JPEG-IP-block-type.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4447-drm-amdgpu-add-JPEG-IP-block-type.patch
new file mode 100644
index 00000000..a80318a6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4447-drm-amdgpu-add-JPEG-IP-block-type.patch
@@ -0,0 +1,30 @@
+From 247de6849ea43686a357b2a5fe2784f9170d4711 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 12:44:54 -0500
+Subject: [PATCH 4447/4736] drm/amdgpu: add JPEG IP block type
+
+From VCN2.0, JPEG2.0 is a separated IP block.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/amd_shared.h | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
+index dc7eb28f0296..d5bc8be4d70c 100644
+--- a/drivers/gpu/drm/amd/include/amd_shared.h
++++ b/drivers/gpu/drm/amd/include/amd_shared.h
+@@ -53,7 +53,8 @@ enum amd_ip_block_type {
+ 	AMD_IP_BLOCK_TYPE_VCE,
+ 	AMD_IP_BLOCK_TYPE_ACP,
+ 	AMD_IP_BLOCK_TYPE_VCN,
+-	AMD_IP_BLOCK_TYPE_MES
++	AMD_IP_BLOCK_TYPE_MES,
++	AMD_IP_BLOCK_TYPE_JPEG
+ };
+ 
+ enum amd_clockgating_state {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4448-drm-amdgpu-add-JPEG-common-functions-to-amdgpu_jpeg.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4448-drm-amdgpu-add-JPEG-common-functions-to-amdgpu_jpeg.patch
new file mode 100644
index 00000000..aac3870f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4448-drm-amdgpu-add-JPEG-common-functions-to-amdgpu_jpeg.patch
@@ -0,0 +1,131 @@
+From c3341685e454cee5c72b56d69b02f50e03b1f077 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 13:12:05 -0500
+Subject: [PATCH 4448/4736] drm/amdgpu: add JPEG common functions to
+ amdgpu_jpeg
+
+They will be used for JPEG2.0 and later.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 76 ++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 10 ++++
+ 2 files changed, 86 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
+index d9a547d4d3b2..5727f00afc8e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
+@@ -26,9 +26,85 @@
+ 
+ #include "amdgpu.h"
+ #include "amdgpu_jpeg.h"
++#include "amdgpu_pm.h"
+ #include "soc15d.h"
+ #include "soc15_common.h"
+ 
++#define JPEG_IDLE_TIMEOUT	msecs_to_jiffies(1000)
++
++static void amdgpu_jpeg_idle_work_handler(struct work_struct *work);
++
++int amdgpu_jpeg_sw_init(struct amdgpu_device *adev)
++{
++	INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler);
++
++	return 0;
++}
++
++int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev)
++{
++	int i;
++
++	cancel_delayed_work_sync(&adev->jpeg.idle_work);
++
++	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++		if (adev->jpeg.harvest_config & (1 << i))
++			continue;
++
++		amdgpu_ring_fini(&adev->jpeg.inst[i].ring_dec);
++	}
++
++	return 0;
++}
++
++int amdgpu_jpeg_suspend(struct amdgpu_device *adev)
++{
++	cancel_delayed_work_sync(&adev->jpeg.idle_work);
++
++	return 0;
++}
++
++int amdgpu_jpeg_resume(struct amdgpu_device *adev)
++{
++	return 0;
++}
++
++static void amdgpu_jpeg_idle_work_handler(struct work_struct *work)
++{
++	struct amdgpu_device *adev =
++		container_of(work, struct amdgpu_device, jpeg.idle_work.work);
++	unsigned int fences = 0;
++	unsigned int i;
++
++	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++		if (adev->jpeg.harvest_config & (1 << i))
++			continue;
++
++		fences += amdgpu_fence_count_emitted(&adev->jpeg.inst[i].ring_dec);
++	}
++
++	if (fences == 0)
++		amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
++						       AMD_PG_STATE_GATE);
++	else
++		schedule_delayed_work(&adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
++}
++
++void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++	bool set_clocks = !cancel_delayed_work_sync(&adev->jpeg.idle_work);
++
++	if (set_clocks)
++		amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
++						       AMD_PG_STATE_UNGATE);
++}
++
++void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring)
++{
++	schedule_delayed_work(&ring->adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
++}
++
+ int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+index a8d988c25f45..5e2e06ec13df 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+@@ -41,8 +41,18 @@ struct amdgpu_jpeg {
+ 	struct amdgpu_jpeg_inst inst[AMDGPU_MAX_JPEG_INSTANCES];
+ 	struct amdgpu_jpeg_reg internal;
+ 	unsigned harvest_config;
++	struct delayed_work idle_work;
++	enum amd_powergating_state cur_state;
+ };
+ 
++int amdgpu_jpeg_sw_init(struct amdgpu_device *adev);
++int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev);
++int amdgpu_jpeg_suspend(struct amdgpu_device *adev);
++int amdgpu_jpeg_resume(struct amdgpu_device *adev);
++
++void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring);
++void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring);
++
+ int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring);
+ int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4449-drm-amdgpu-add-JPEG-v2.0-function-supports.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4449-drm-amdgpu-add-JPEG-v2.0-function-supports.patch
new file mode 100644
index 00000000..026bb3b4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4449-drm-amdgpu-add-JPEG-v2.0-function-supports.patch
@@ -0,0 +1,897 @@
+From 7cc43910abfb193dd38b61119bf30459551aa4a7 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 13:26:46 -0500
+Subject: [PATCH 4449/4736] drm/amdgpu: add JPEG v2.0 function supports
+
+It got separated from VCN2.0 with a new jpeg_v2_0_ip_block
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile    |   3 +-
+ drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 809 +++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h |  42 ++
+ 3 files changed, 853 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index 62ef3d7955d9..7cbe646d1ae1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -155,7 +155,8 @@ amdgpu-y += \
+ 	vcn_v2_0.o \
+ 	vcn_v2_5.o \
+ 	amdgpu_jpeg.o \
+-	jpeg_v1_0.o
++	jpeg_v1_0.o \
++	jpeg_v2_0.o
+ 
+ # add ATHUB block
+ amdgpu-y += \
+diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+new file mode 100644
+index 000000000000..4143ef6905b8
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+@@ -0,0 +1,809 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include "amdgpu.h"
++#include "amdgpu_jpeg.h"
++#include "amdgpu_pm.h"
++#include "soc15.h"
++#include "soc15d.h"
++
++#include "vcn/vcn_2_0_0_offset.h"
++#include "vcn/vcn_2_0_0_sh_mask.h"
++#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
++
++#define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 			0x1bfff
++#define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET				0x4029
++#define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET				0x402a
++#define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET				0x402b
++#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET		0x40ea
++#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 	0x40eb
++#define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET				0x40cf
++#define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET				0x40d1
++#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 		0x40e8
++#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET		0x40e9
++#define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET				0x4082
++#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET		0x40ec
++#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET 	0x40ed
++#define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET			0x4085
++#define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET				0x4084
++#define mmUVD_JRBC_STATUS_INTERNAL_OFFSET				0x4089
++#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET				0x401f
++
++#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR				0x18000
++
++static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
++static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);
++static int jpeg_v2_0_set_powergating_state(void *handle,
++				enum amd_powergating_state state);
++
++/**
++ * jpeg_v2_0_early_init - set function pointers
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Set ring and irq function pointers
++ */
++static int jpeg_v2_0_early_init(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++	adev->jpeg.num_jpeg_inst = 1;
++
++	jpeg_v2_0_set_dec_ring_funcs(adev);
++	jpeg_v2_0_set_irq_funcs(adev);
++
++	return 0;
++}
++
++/**
++ * jpeg_v2_0_sw_init - sw init for JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Load firmware and sw initialization
++ */
++static int jpeg_v2_0_sw_init(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	struct amdgpu_ring *ring;
++	int r;
++
++	/* JPEG TRAP */
++	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
++		VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
++	if (r)
++		return r;
++
++	r = amdgpu_jpeg_sw_init(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_jpeg_resume(adev);
++	if (r)
++		return r;
++
++	ring = &adev->jpeg.inst->ring_dec;
++	ring->use_doorbell = true;
++	ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
++	sprintf(ring->name, "jpeg_dec");
++	r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0);
++	if (r)
++		return r;
++
++	adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
++	adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
++
++	return 0;
++}
++
++/**
++ * jpeg_v2_0_sw_fini - sw fini for JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * JPEG suspend and free up sw allocation
++ */
++static int jpeg_v2_0_sw_fini(void *handle)
++{
++	int r;
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++	r = amdgpu_jpeg_suspend(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_jpeg_sw_fini(adev);
++
++	return r;
++}
++
++/**
++ * jpeg_v2_0_hw_init - start and test JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ */
++static int jpeg_v2_0_hw_init(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
++	int r;
++
++	adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
++		(adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
++
++	r = amdgpu_ring_test_helper(ring);
++	if (!r)
++		DRM_INFO("JPEG decode initialized successfully.\n");
++
++	return r;
++}
++
++/**
++ * jpeg_v2_0_hw_fini - stop the hardware block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Stop the JPEG block, mark ring as not ready any more
++ */
++static int jpeg_v2_0_hw_fini(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
++
++	if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
++	      RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
++		jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
++
++	ring->sched.ready = false;
++
++	return 0;
++}
++
++/**
++ * jpeg_v2_0_suspend - suspend JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * HW fini and suspend JPEG block
++ */
++static int jpeg_v2_0_suspend(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	int r;
++
++	r = jpeg_v2_0_hw_fini(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_jpeg_suspend(adev);
++
++	return r;
++}
++
++/**
++ * jpeg_v2_0_resume - resume JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Resume firmware and hw init JPEG block
++ */
++static int jpeg_v2_0_resume(void *handle)
++{
++	int r;
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++	r = amdgpu_jpeg_resume(adev);
++	if (r)
++		return r;
++
++	r = jpeg_v2_0_hw_init(adev);
++
++	return r;
++}
++
++static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev)
++{
++	uint32_t data;
++	int r = 0;
++
++	data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
++	WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
++
++	SOC15_WAIT_ON_RREG(JPEG, 0,
++		mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
++		UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
++
++	if (r) {
++		DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
++		return r;
++	}
++
++	/* Removing the anti hang mechanism to indicate the UVDJ tile is ON */
++	data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;
++	WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
++
++	return 0;
++}
++
++static int jpeg_v2_0_enable_power_gating(struct amdgpu_device* adev)
++{
++	uint32_t data;
++	int r = 0;
++
++	data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));
++	data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
++	data |=  0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
++	WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
++
++	data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
++	WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
++
++	SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
++		(2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
++		UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
++
++	if (r) {
++		DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
++		return r;
++	}
++
++	return 0;
++}
++
++static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device* adev)
++{
++	uint32_t data;
++
++	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
++	data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++
++	data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
++	data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
++	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
++
++	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
++	data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
++		| JPEG_CGC_GATE__JPEG2_DEC_MASK
++		| JPEG_CGC_GATE__JPEG_ENC_MASK
++		| JPEG_CGC_GATE__JMCIF_MASK
++		| JPEG_CGC_GATE__JRBBM_MASK);
++	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
++}
++
++static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device* adev)
++{
++	uint32_t data;
++
++	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
++	data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++
++	data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
++	data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
++	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
++
++	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
++	data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
++		|JPEG_CGC_GATE__JPEG2_DEC_MASK
++		|JPEG_CGC_GATE__JPEG_ENC_MASK
++		|JPEG_CGC_GATE__JMCIF_MASK
++		|JPEG_CGC_GATE__JRBBM_MASK);
++	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
++}
++
++/**
++ * jpeg_v2_0_start - start JPEG block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Setup and start the JPEG block
++ */
++static int jpeg_v2_0_start(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
++	int r;
++
++	/* disable power gating */
++	r = jpeg_v2_0_disable_power_gating(adev);
++	if (r)
++		return r;
++
++	/* JPEG disable CGC */
++	jpeg_v2_0_disable_clock_gating(adev);
++
++	WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
++
++	/* enable JMI channel */
++	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,
++		~UVD_JMI_CNTL__SOFT_RESET_MASK);
++
++	/* enable System Interrupt for JRBC */
++	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),
++		JPEG_SYS_INT_EN__DJRBC_MASK,
++		~JPEG_SYS_INT_EN__DJRBC_MASK);
++
++	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
++	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
++	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
++		lower_32_bits(ring->gpu_addr));
++	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
++		upper_32_bits(ring->gpu_addr));
++	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
++	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
++	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
++	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
++	ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
++
++	return 0;
++}
++
++/**
++ * jpeg_v2_0_stop - stop JPEG block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * stop the JPEG block
++ */
++static int jpeg_v2_0_stop(struct amdgpu_device *adev)
++{
++	int r;
++
++	/* reset JMI */
++	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),
++		UVD_JMI_CNTL__SOFT_RESET_MASK,
++		~UVD_JMI_CNTL__SOFT_RESET_MASK);
++
++	/* enable JPEG CGC */
++	jpeg_v2_0_enable_clock_gating(adev);
++
++	/* enable power gating */
++	r = jpeg_v2_0_enable_power_gating(adev);
++
++	return r;
++}
++
++/**
++ * jpeg_v2_0_dec_ring_get_rptr - get read pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware read pointer
++ */
++static uint64_t jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
++}
++
++/**
++ * jpeg_v2_0_dec_ring_get_wptr - get write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware write pointer
++ */
++static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	if (ring->use_doorbell)
++		return adev->wb.wb[ring->wptr_offs];
++	else
++		return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
++}
++
++/**
++ * jpeg_v2_0_dec_ring_set_wptr - set write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Commits the write pointer to the hardware
++ */
++static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	if (ring->use_doorbell) {
++		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
++		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
++	} else {
++		WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
++	}
++}
++
++/**
++ * jpeg_v2_0_dec_ring_insert_start - insert a start command
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Write a start command to the ring.
++ */
++void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
++{
++	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x68e04);
++
++	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x80010000);
++}
++
++/**
++ * jpeg_v2_0_dec_ring_insert_end - insert a end command
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Write a end command to the ring.
++ */
++void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
++{
++	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x68e04);
++
++	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x00010000);
++}
++
++/**
++ * jpeg_v2_0_dec_ring_emit_fence - emit an fence & trap command
++ *
++ * @ring: amdgpu_ring pointer
++ * @fence: fence to emit
++ *
++ * Write a fence and a trap command to the ring.
++ */
++void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
++				unsigned flags)
++{
++	WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
++
++	amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, seq);
++
++	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, seq);
++
++	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, lower_32_bits(addr));
++
++	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, upper_32_bits(addr));
++
++	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x8);
++
++	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
++		0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
++	amdgpu_ring_write(ring, 0);
++
++	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x3fbc);
++
++	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x1);
++
++	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
++	amdgpu_ring_write(ring, 0);
++}
++
++/**
++ * jpeg_v2_0_dec_ring_emit_ib - execute indirect buffer
++ *
++ * @ring: amdgpu_ring pointer
++ * @ib: indirect buffer to execute
++ *
++ * Write ring commands to execute the indirect buffer.
++ */
++void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
++				struct amdgpu_job *job,
++				struct amdgpu_ib *ib,
++				uint32_t flags)
++{
++	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
++
++	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, (vmid | (vmid << 4)));
++
++	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, (vmid | (vmid << 4)));
++
++	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
++
++	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
++
++	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, ib->length_dw);
++
++	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
++
++	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
++
++	amdgpu_ring_write(ring,	PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
++	amdgpu_ring_write(ring, 0);
++
++	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x01400200);
++
++	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x2);
++
++	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET,
++		0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
++	amdgpu_ring_write(ring, 0x2);
++}
++
++void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
++				uint32_t val, uint32_t mask)
++{
++	uint32_t reg_offset = (reg << 2);
++
++	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, 0x01400200);
++
++	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	amdgpu_ring_write(ring, val);
++
++	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
++		amdgpu_ring_write(ring, 0);
++		amdgpu_ring_write(ring,
++			PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
++	} else {
++		amdgpu_ring_write(ring, reg_offset);
++		amdgpu_ring_write(ring,	PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
++			0, 0, PACKETJ_TYPE3));
++	}
++	amdgpu_ring_write(ring, mask);
++}
++
++void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
++				unsigned vmid, uint64_t pd_addr)
++{
++	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
++	uint32_t data0, data1, mask;
++
++	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
++
++	/* wait for register write */
++	data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
++	data1 = lower_32_bits(pd_addr);
++	mask = 0xffffffff;
++	jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
++}
++
++void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
++{
++	uint32_t reg_offset = (reg << 2);
++
++	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
++		0, 0, PACKETJ_TYPE0));
++	if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
++		amdgpu_ring_write(ring, 0);
++		amdgpu_ring_write(ring,
++			PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
++	} else {
++		amdgpu_ring_write(ring, reg_offset);
++		amdgpu_ring_write(ring,	PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
++			0, 0, PACKETJ_TYPE0));
++	}
++	amdgpu_ring_write(ring, val);
++}
++
++void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)
++{
++	int i;
++
++	WARN_ON(ring->wptr % 2 || count % 2);
++
++	for (i = 0; i < count / 2; i++) {
++		amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
++		amdgpu_ring_write(ring, 0);
++	}
++}
++
++static bool jpeg_v2_0_is_idle(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++	return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
++		UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
++		UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
++}
++
++static int jpeg_v2_0_wait_for_idle(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	int ret = 0;
++
++	SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
++		UVD_JRBC_STATUS__RB_JOB_DONE_MASK, ret);
++
++	return ret;
++}
++
++static int jpeg_v2_0_set_clockgating_state(void *handle,
++					  enum amd_clockgating_state state)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
++
++	if (enable) {
++		if (jpeg_v2_0_is_idle(handle))
++			return -EBUSY;
++		jpeg_v2_0_enable_clock_gating(adev);
++	} else {
++		jpeg_v2_0_disable_clock_gating(adev);
++	}
++
++	return 0;
++}
++
++static int jpeg_v2_0_set_powergating_state(void *handle,
++					enum amd_powergating_state state)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	int ret;
++
++	if (state == adev->jpeg.cur_state)
++		return 0;
++
++	if (state == AMD_PG_STATE_GATE)
++		ret = jpeg_v2_0_stop(adev);
++	else
++		ret = jpeg_v2_0_start(adev);
++
++	if (!ret)
++		adev->jpeg.cur_state = state;
++
++	return ret;
++}
++
++static int jpeg_v2_0_set_interrupt_state(struct amdgpu_device *adev,
++					struct amdgpu_irq_src *source,
++					unsigned type,
++					enum amdgpu_interrupt_state state)
++{
++	return 0;
++}
++
++static int jpeg_v2_0_process_interrupt(struct amdgpu_device *adev,
++				      struct amdgpu_irq_src *source,
++				      struct amdgpu_iv_entry *entry)
++{
++	DRM_DEBUG("IH: JPEG TRAP\n");
++
++	switch (entry->src_id) {
++	case VCN_2_0__SRCID__JPEG_DECODE:
++		amdgpu_fence_process(&adev->jpeg.inst->ring_dec);
++		break;
++	default:
++		DRM_ERROR("Unhandled interrupt: %d %d\n",
++			  entry->src_id, entry->src_data[0]);
++		break;
++	}
++
++	return 0;
++}
++
++static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {
++	.name = "jpeg_v2_0",
++	.early_init = jpeg_v2_0_early_init,
++	.late_init = NULL,
++	.sw_init = jpeg_v2_0_sw_init,
++	.sw_fini = jpeg_v2_0_sw_fini,
++	.hw_init = jpeg_v2_0_hw_init,
++	.hw_fini = jpeg_v2_0_hw_fini,
++	.suspend = jpeg_v2_0_suspend,
++	.resume = jpeg_v2_0_resume,
++	.is_idle = jpeg_v2_0_is_idle,
++	.wait_for_idle = jpeg_v2_0_wait_for_idle,
++	.check_soft_reset = NULL,
++	.pre_soft_reset = NULL,
++	.soft_reset = NULL,
++	.post_soft_reset = NULL,
++	.set_clockgating_state = jpeg_v2_0_set_clockgating_state,
++	.set_powergating_state = jpeg_v2_0_set_powergating_state,
++};
++
++static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {
++	.type = AMDGPU_RING_TYPE_VCN_JPEG,
++	.align_mask = 0xf,
++	.vmhub = AMDGPU_MMHUB_0,
++	.get_rptr = jpeg_v2_0_dec_ring_get_rptr,
++	.get_wptr = jpeg_v2_0_dec_ring_get_wptr,
++	.set_wptr = jpeg_v2_0_dec_ring_set_wptr,
++	.emit_frame_size =
++		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
++		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
++		8 + /* jpeg_v2_0_dec_ring_emit_vm_flush */
++		18 + 18 + /* jpeg_v2_0_dec_ring_emit_fence x2 vm fence */
++		8 + 16,
++	.emit_ib_size = 22, /* jpeg_v2_0_dec_ring_emit_ib */
++	.emit_ib = jpeg_v2_0_dec_ring_emit_ib,
++	.emit_fence = jpeg_v2_0_dec_ring_emit_fence,
++	.emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
++	.test_ring = amdgpu_jpeg_dec_ring_test_ring,
++	.test_ib = amdgpu_jpeg_dec_ring_test_ib,
++	.insert_nop = jpeg_v2_0_dec_ring_nop,
++	.insert_start = jpeg_v2_0_dec_ring_insert_start,
++	.insert_end = jpeg_v2_0_dec_ring_insert_end,
++	.pad_ib = amdgpu_ring_generic_pad_ib,
++	.begin_use = amdgpu_jpeg_ring_begin_use,
++	.end_use = amdgpu_jpeg_ring_end_use,
++	.emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
++	.emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
++	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
++};
++
++static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
++{
++	adev->jpeg.inst->ring_dec.funcs = &jpeg_v2_0_dec_ring_vm_funcs;
++	DRM_INFO("JPEG decode is enabled in VM mode\n");
++}
++
++static const struct amdgpu_irq_src_funcs jpeg_v2_0_irq_funcs = {
++	.set = jpeg_v2_0_set_interrupt_state,
++	.process = jpeg_v2_0_process_interrupt,
++};
++
++static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev)
++{
++	adev->jpeg.inst->irq.num_types = 1;
++	adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs;
++}
++
++const struct amdgpu_ip_block_version jpeg_v2_0_ip_block =
++{
++		.type = AMD_IP_BLOCK_TYPE_JPEG,
++		.major = 2,
++		.minor = 0,
++		.rev = 0,
++		.funcs = &jpeg_v2_0_ip_funcs,
++};
+diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h
+new file mode 100644
+index 000000000000..15a344ed340f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h
+@@ -0,0 +1,42 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __JPEG_V2_0_H__
++#define __JPEG_V2_0_H__
++
++void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring);
++void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring);
++void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
++				unsigned flags);
++void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
++				struct amdgpu_ib *ib, uint32_t flags);
++void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
++				uint32_t val, uint32_t mask);
++void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
++				unsigned vmid, uint64_t pd_addr);
++void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
++void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count);
++
++extern const struct amdgpu_ip_block_version jpeg_v2_0_ip_block;
++
++#endif /* __JPEG_V2_0_H__ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4450-drm-amdgpu-remove-unnecessary-JPEG2.0-code-from-VCN2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4450-drm-amdgpu-remove-unnecessary-JPEG2.0-code-from-VCN2.patch
new file mode 100644
index 00000000..d5615b6c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4450-drm-amdgpu-remove-unnecessary-JPEG2.0-code-from-VCN2.patch
@@ -0,0 +1,395 @@
+From f2e6cb77cc722e76f1d89851d55c6eb4fd84b288 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 13:30:15 -0500
+Subject: [PATCH 4450/4736] drm/amdgpu: remove unnecessary JPEG2.0 code from
+ VCN2.0
+
+They are no longer needed, using from JPEG2.0 instead.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 260 +-------------------------
+ 1 file changed, 3 insertions(+), 257 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+index 16f192f6c967..4e0c3467deb2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+@@ -74,7 +74,6 @@
+ 
+ static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
+ static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
+-static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
+ static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
+ static int vcn_v2_0_set_powergating_state(void *handle,
+ 				enum amd_powergating_state state);
+@@ -97,7 +96,6 @@ static int vcn_v2_0_early_init(void *handle)
+ 
+ 	vcn_v2_0_set_dec_ring_funcs(adev);
+ 	vcn_v2_0_set_enc_ring_funcs(adev);
+-	vcn_v2_0_set_jpeg_ring_funcs(adev);
+ 	vcn_v2_0_set_irq_funcs(adev);
+ 
+ 	return 0;
+@@ -132,12 +130,6 @@ static int vcn_v2_0_sw_init(void *handle)
+ 			return r;
+ 	}
+ 
+-	/* VCN JPEG TRAP */
+-	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
+-			      VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst->irq);
+-	if (r)
+-		return r;
+-
+ 	r = amdgpu_vcn_sw_init(adev);
+ 	if (r)
+ 		return r;
+@@ -194,19 +186,8 @@ static int vcn_v2_0_sw_init(void *handle)
+ 			return r;
+ 	}
+ 
+-	ring = &adev->vcn.inst->ring_jpeg;
+-	ring->use_doorbell = true;
+-	ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
+-	sprintf(ring->name, "vcn_jpeg");
+-	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
+-	if (r)
+-		return r;
+-
+ 	adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
+ 
+-	adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
+-	adev->vcn.inst->external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
+-
+ 	return 0;
+ }
+ 
+@@ -258,11 +239,6 @@ static int vcn_v2_0_hw_init(void *handle)
+ 			goto done;
+ 	}
+ 
+-	ring = &adev->vcn.inst->ring_jpeg;
+-	r = amdgpu_ring_test_helper(ring);
+-	if (r)
+-		goto done;
+-
+ done:
+ 	if (!r)
+ 		DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
+@@ -296,9 +272,6 @@ static int vcn_v2_0_hw_fini(void *handle)
+ 		ring->sched.ready = false;
+ 	}
+ 
+-	ring = &adev->vcn.inst->ring_jpeg;
+-	ring->sched.ready = false;
+-
+ 	return 0;
+ }
+ 
+@@ -393,7 +366,6 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
+ 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
+ 
+ 	WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
+-	WREG32_SOC15(UVD, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
+ }
+ 
+ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)
+@@ -647,129 +619,6 @@ static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
+ 		UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
+ }
+ 
+-/**
+- * jpeg_v2_0_start - start JPEG block
+- *
+- * @adev: amdgpu_device pointer
+- *
+- * Setup and start the JPEG block
+- */
+-static int jpeg_v2_0_start(struct amdgpu_device *adev)
+-{
+-	struct amdgpu_ring *ring = &adev->vcn.inst->ring_jpeg;
+-	uint32_t tmp;
+-	int r = 0;
+-
+-	/* disable power gating */
+-	tmp = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
+-	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp);
+-
+-	SOC15_WAIT_ON_RREG(VCN, 0,
+-		mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
+-		UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
+-
+-	if (r) {
+-		DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
+-		return r;
+-	}
+-
+-	/* Removing the anti hang mechanism to indicate the UVDJ tile is ON */
+-	tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;
+-	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp);
+-
+-	/* JPEG disable CGC */
+-	tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
+-	tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+-	tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+-	tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+-	WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp);
+-
+-	tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
+-	tmp &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
+-		| JPEG_CGC_GATE__JPEG2_DEC_MASK
+-		| JPEG_CGC_GATE__JPEG_ENC_MASK
+-		| JPEG_CGC_GATE__JMCIF_MASK
+-		| JPEG_CGC_GATE__JRBBM_MASK);
+-	WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp);
+-
+-	/* enable JMI channel */
+-	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL), 0,
+-		~UVD_JMI_CNTL__SOFT_RESET_MASK);
+-
+-	/* enable System Interrupt for JRBC */
+-	WREG32_P(SOC15_REG_OFFSET(VCN, 0, mmJPEG_SYS_INT_EN),
+-		JPEG_SYS_INT_EN__DJRBC_MASK,
+-		~JPEG_SYS_INT_EN__DJRBC_MASK);
+-
+-	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
+-	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
+-	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
+-		lower_32_bits(ring->gpu_addr));
+-	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
+-		upper_32_bits(ring->gpu_addr));
+-	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
+-	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
+-	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
+-	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
+-	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+-
+-	return 0;
+-}
+-
+-/**
+- * jpeg_v2_0_stop - stop JPEG block
+- *
+- * @adev: amdgpu_device pointer
+- *
+- * stop the JPEG block
+- */
+-static int jpeg_v2_0_stop(struct amdgpu_device *adev)
+-{
+-	uint32_t tmp;
+-	int r = 0;
+-
+-	/* reset JMI */
+-	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL),
+-		UVD_JMI_CNTL__SOFT_RESET_MASK,
+-		~UVD_JMI_CNTL__SOFT_RESET_MASK);
+-
+-	/* enable JPEG CGC */
+-	tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
+-	tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+-	tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+-	tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+-	WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp);
+-
+-
+-	tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
+-	tmp |= (JPEG_CGC_GATE__JPEG_DEC_MASK
+-		|JPEG_CGC_GATE__JPEG2_DEC_MASK
+-		|JPEG_CGC_GATE__JPEG_ENC_MASK
+-		|JPEG_CGC_GATE__JMCIF_MASK
+-		|JPEG_CGC_GATE__JRBBM_MASK);
+-	WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp);
+-
+-	/* enable power gating */
+-	tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS));
+-	tmp &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
+-	tmp |=  0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
+-	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), tmp);
+-
+-	tmp = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
+-	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_PGFSM_CONFIG), tmp);
+-
+-	SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,
+-		(2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
+-		UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
+-
+-	if (r) {
+-		DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
+-		return r;
+-	}
+-
+-	return r;
+-}
+-
+ /**
+  * vcn_v2_0_enable_clock_gating - enable VCN clock gating
+  *
+@@ -1052,12 +901,8 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)
+ 	if (adev->pm.dpm_enabled)
+ 		amdgpu_dpm_enable_uvd(adev, true);
+ 
+-	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+-		r = vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
+-		if (r)
+-			return r;
+-		goto jpeg;
+-	}
++	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
++		return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
+ 
+ 	vcn_v2_0_disable_static_power_gating(adev);
+ 
+@@ -1209,10 +1054,7 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+ 	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
+ 
+-jpeg:
+-	r = jpeg_v2_0_start(adev);
+-
+-	return r;
++	return 0;
+ }
+ 
+ static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
+@@ -1231,9 +1073,6 @@ static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
+ 	tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
+ 	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
+ 
+-	tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+-	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
+-
+ 	tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
+ 	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
+ 
+@@ -1252,10 +1091,6 @@ static int vcn_v2_0_stop(struct amdgpu_device *adev)
+ 	uint32_t tmp;
+ 	int r;
+ 
+-	r = jpeg_v2_0_stop(adev);
+-	if (r)
+-		return r;
+-
+ 	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ 		r = vcn_v2_0_stop_dpg_mode(adev);
+ 		if (r)
+@@ -1781,56 +1616,6 @@ void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_
+ 	amdgpu_ring_write(ring, val);
+ }
+ 
+-/**
+- * vcn_v2_0_jpeg_ring_get_rptr - get read pointer
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Returns the current hardware read pointer
+- */
+-static uint64_t vcn_v2_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-
+-	return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
+-}
+-
+-/**
+- * vcn_v2_0_jpeg_ring_get_wptr - get write pointer
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Returns the current hardware write pointer
+- */
+-static uint64_t vcn_v2_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-
+-	if (ring->use_doorbell)
+-		return adev->wb.wb[ring->wptr_offs];
+-	else
+-		return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
+-}
+-
+-/**
+- * vcn_v2_0_jpeg_ring_set_wptr - set write pointer
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Commits the write pointer to the hardware
+- */
+-static void vcn_v2_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-
+-	if (ring->use_doorbell) {
+-		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+-		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
+-	} else {
+-		WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
+-	}
+-}
+-
+ /**
+  * vcn_v2_0_jpeg_ring_insert_start - insert a start command
+  *
+@@ -2071,9 +1856,6 @@ static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
+ 	case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
+ 		amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
+ 		break;
+-	case VCN_2_0__SRCID__JPEG_DECODE:
+-		amdgpu_fence_process(&adev->vcn.inst->ring_jpeg);
+-		break;
+ 	default:
+ 		DRM_ERROR("Unhandled interrupt: %d %d\n",
+ 			  entry->src_id, entry->src_data[0]);
+@@ -2219,36 +2001,6 @@ static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
+ 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ };
+ 
+-static const struct amdgpu_ring_funcs vcn_v2_0_jpeg_ring_vm_funcs = {
+-	.type = AMDGPU_RING_TYPE_VCN_JPEG,
+-	.align_mask = 0xf,
+-	.vmhub = AMDGPU_MMHUB_0,
+-	.get_rptr = vcn_v2_0_jpeg_ring_get_rptr,
+-	.get_wptr = vcn_v2_0_jpeg_ring_get_wptr,
+-	.set_wptr = vcn_v2_0_jpeg_ring_set_wptr,
+-	.emit_frame_size =
+-		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
+-		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
+-		8 + /* vcn_v2_0_jpeg_ring_emit_vm_flush */
+-		18 + 18 + /* vcn_v2_0_jpeg_ring_emit_fence x2 vm fence */
+-		8 + 16,
+-	.emit_ib_size = 22, /* vcn_v2_0_jpeg_ring_emit_ib */
+-	.emit_ib = vcn_v2_0_jpeg_ring_emit_ib,
+-	.emit_fence = vcn_v2_0_jpeg_ring_emit_fence,
+-	.emit_vm_flush = vcn_v2_0_jpeg_ring_emit_vm_flush,
+-	.test_ring = amdgpu_vcn_jpeg_ring_test_ring,
+-	.test_ib = amdgpu_vcn_jpeg_ring_test_ib,
+-	.insert_nop = vcn_v2_0_jpeg_ring_nop,
+-	.insert_start = vcn_v2_0_jpeg_ring_insert_start,
+-	.insert_end = vcn_v2_0_jpeg_ring_insert_end,
+-	.pad_ib = amdgpu_ring_generic_pad_ib,
+-	.begin_use = amdgpu_vcn_ring_begin_use,
+-	.end_use = amdgpu_vcn_ring_end_use,
+-	.emit_wreg = vcn_v2_0_jpeg_ring_emit_wreg,
+-	.emit_reg_wait = vcn_v2_0_jpeg_ring_emit_reg_wait,
+-	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+-};
+-
+ static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
+ {
+ 	adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
+@@ -2265,12 +2017,6 @@ static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)
+ 	DRM_INFO("VCN encode is enabled in VM mode\n");
+ }
+ 
+-static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
+-{
+-	adev->vcn.inst->ring_jpeg.funcs = &vcn_v2_0_jpeg_ring_vm_funcs;
+-	DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
+-}
+-
+ static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {
+ 	.set = vcn_v2_0_set_interrupt_state,
+ 	.process = vcn_v2_0_process_interrupt,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4451-drm-amdgpu-add-JPEG-PG-and-CG-interface.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4451-drm-amdgpu-add-JPEG-PG-and-CG-interface.patch
new file mode 100644
index 00000000..411357a7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4451-drm-amdgpu-add-JPEG-PG-and-CG-interface.patch
@@ -0,0 +1,36 @@
+From 0a6773cfa2f7e7619ca1dd38a0fa8880a1b4909d Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 13:17:52 -0500
+Subject: [PATCH 4451/4736] drm/amdgpu: add JPEG PG and CG interface
+
+From JPEG2.0, it will use its own PG/CG
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/amd_shared.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
+index d5bc8be4d70c..d655a76bedc6 100644
+--- a/drivers/gpu/drm/amd/include/amd_shared.h
++++ b/drivers/gpu/drm/amd/include/amd_shared.h
+@@ -100,6 +100,7 @@ enum amd_powergating_state {
+ #define AMD_CG_SUPPORT_IH_CG			(1 << 27)
+ #define AMD_CG_SUPPORT_ATHUB_LS			(1 << 28)
+ #define AMD_CG_SUPPORT_ATHUB_MGCG		(1 << 29)
++#define AMD_CG_SUPPORT_JPEG_MGCG		(1 << 30)
+ /* PG flags */
+ #define AMD_PG_SUPPORT_GFX_PG			(1 << 0)
+ #define AMD_PG_SUPPORT_GFX_SMG			(1 << 1)
+@@ -118,6 +119,7 @@ enum amd_powergating_state {
+ #define AMD_PG_SUPPORT_VCN			(1 << 14)
+ #define AMD_PG_SUPPORT_VCN_DPG			(1 << 15)
+ #define AMD_PG_SUPPORT_ATHUB			(1 << 16)
++#define AMD_PG_SUPPORT_JPEG			(1 << 17)
+ 
+ enum PP_FEATURE_MASK {
+ 	PP_SCLK_DPM_MASK = 0x1,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4452-drm-amdgpu-add-PG-and-CG-for-JPEG2.0.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4452-drm-amdgpu-add-PG-and-CG-for-JPEG2.0.patch
new file mode 100644
index 00000000..1d3c19c2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4452-drm-amdgpu-add-PG-and-CG-for-JPEG2.0.patch
@@ -0,0 +1,177 @@
+From fd3e1f0031707e8ae09a39c90519d483c1e1ffce Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Mon, 11 Nov 2019 15:09:25 -0500
+Subject: [PATCH 4452/4736] drm/amdgpu: add PG and CG for JPEG2.0
+
+And enable them for Navi1x and Renoir
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 62 +++++++++++++++-----------
+ drivers/gpu/drm/amd/amdgpu/nv.c        |  8 +++-
+ drivers/gpu/drm/amd/amdgpu/soc15.c     |  2 +
+ 3 files changed, 45 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+index 4143ef6905b8..3869730b2331 100644
+--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+@@ -227,16 +227,18 @@ static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev)
+ 	uint32_t data;
+ 	int r = 0;
+ 
+-	data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
+-	WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
+-
+-	SOC15_WAIT_ON_RREG(JPEG, 0,
+-		mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
+-		UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
+-
+-	if (r) {
+-		DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
+-		return r;
++	if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
++		data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
++		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
++
++		SOC15_WAIT_ON_RREG(JPEG, 0,
++			mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
++			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
++
++		if (r) {
++			DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
++			return r;
++		}
+ 	}
+ 
+ 	/* Removing the anti hang mechanism to indicate the UVDJ tile is ON */
+@@ -248,24 +250,26 @@ static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev)
+ 
+ static int jpeg_v2_0_enable_power_gating(struct amdgpu_device* adev)
+ {
+-	uint32_t data;
+-	int r = 0;
++	if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
++		uint32_t data;
++		int r = 0;
+ 
+-	data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));
+-	data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
+-	data |=  0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
+-	WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
++		data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));
++		data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
++		data |=  0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
++		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
+ 
+-	data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
+-	WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
++		data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
++		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
+ 
+-	SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
+-		(2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
+-		UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
++		SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
++			(2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
++			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
+ 
+-	if (r) {
+-		DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
+-		return r;
++		if (r) {
++			DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
++			return r;
++		}
+ 	}
+ 
+ 	return 0;
+@@ -276,7 +280,10 @@ static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device* adev)
+ 	uint32_t data;
+ 
+ 	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
+-	data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++	if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
++		data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++	else
++		data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+ 
+ 	data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+ 	data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+@@ -296,7 +303,10 @@ static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device* adev)
+ 	uint32_t data;
+ 
+ 	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
+-	data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++	if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
++		data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++	else
++		data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+ 
+ 	data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+ 	data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index be761785b2a8..0b8aedfe1b67 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -642,10 +642,12 @@ static int nv_common_early_init(void *handle)
+ 			AMD_CG_SUPPORT_ATHUB_MGCG |
+ 			AMD_CG_SUPPORT_ATHUB_LS |
+ 			AMD_CG_SUPPORT_VCN_MGCG |
++			AMD_CG_SUPPORT_JPEG_MGCG |
+ 			AMD_CG_SUPPORT_BIF_MGCG |
+ 			AMD_CG_SUPPORT_BIF_LS;
+ 		adev->pg_flags = AMD_PG_SUPPORT_VCN |
+ 			AMD_PG_SUPPORT_VCN_DPG |
++			AMD_PG_SUPPORT_JPEG |
+ 			AMD_PG_SUPPORT_ATHUB;
+ 		adev->external_rev_id = adev->rev_id + 0x1;
+ 		break;
+@@ -662,9 +664,11 @@ static int nv_common_early_init(void *handle)
+ 			AMD_CG_SUPPORT_ATHUB_MGCG |
+ 			AMD_CG_SUPPORT_ATHUB_LS |
+ 			AMD_CG_SUPPORT_VCN_MGCG |
++			AMD_CG_SUPPORT_JPEG_MGCG |
+ 			AMD_CG_SUPPORT_BIF_MGCG |
+ 			AMD_CG_SUPPORT_BIF_LS;
+ 		adev->pg_flags = AMD_PG_SUPPORT_VCN |
++			AMD_PG_SUPPORT_JPEG |
+ 			AMD_PG_SUPPORT_VCN_DPG;
+ 		adev->external_rev_id = adev->rev_id + 20;
+ 		break;
+@@ -683,9 +687,11 @@ static int nv_common_early_init(void *handle)
+ 			AMD_CG_SUPPORT_MC_LS |
+ 			AMD_CG_SUPPORT_ATHUB_MGCG |
+ 			AMD_CG_SUPPORT_ATHUB_LS |
+-			AMD_CG_SUPPORT_VCN_MGCG;
++			AMD_CG_SUPPORT_VCN_MGCG |
++			AMD_CG_SUPPORT_JPEG_MGCG;
+ 		adev->pg_flags = AMD_PG_SUPPORT_VCN |
+ 			AMD_PG_SUPPORT_VCN_DPG |
++			AMD_PG_SUPPORT_JPEG |
+ 			AMD_PG_SUPPORT_ATHUB;
+ 		adev->external_rev_id = adev->rev_id + 0xa;
+ 		break;
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 836a34c10db2..233d3850789e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1231,12 +1231,14 @@ static int soc15_common_early_init(void *handle)
+ 				 AMD_CG_SUPPORT_HDP_LS |
+ 				 AMD_CG_SUPPORT_ROM_MGCG |
+ 				 AMD_CG_SUPPORT_VCN_MGCG |
++				 AMD_CG_SUPPORT_JPEG_MGCG |
+ 				 AMD_CG_SUPPORT_IH_CG |
+ 				 AMD_CG_SUPPORT_ATHUB_LS |
+ 				 AMD_CG_SUPPORT_ATHUB_MGCG |
+ 				 AMD_CG_SUPPORT_DF_MGCG;
+ 		adev->pg_flags = AMD_PG_SUPPORT_SDMA |
+ 				 AMD_PG_SUPPORT_VCN |
++				 AMD_PG_SUPPORT_JPEG |
+ 				 AMD_PG_SUPPORT_VCN_DPG;
+ 		adev->external_rev_id = adev->rev_id + 0x91;
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4453-drm-amd-powerplay-add-JPEG-Powerplay-interface.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4453-drm-amd-powerplay-add-JPEG-Powerplay-interface.patch
new file mode 100644
index 00000000..54c042a9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4453-drm-amd-powerplay-add-JPEG-Powerplay-interface.patch
@@ -0,0 +1,44 @@
+From 978731660cf99a39b47f5d0c80ec6cd4286354af Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 13:54:33 -0500
+Subject: [PATCH 4453/4736] drm/amd/powerplay: add JPEG Powerplay interface
+
+It will be used for different SMU specific to HW
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 999445c5c010..cdd46cdaffb8 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -282,6 +282,7 @@ struct smu_power_gate {
+ 	bool uvd_gated;
+ 	bool vce_gated;
+ 	bool vcn_gated;
++	bool jpeg_gated;
+ };
+ 
+ struct smu_power_context {
+@@ -435,6 +436,7 @@ struct pptable_funcs {
+ 	int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
+ 	int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable);
+ 	int (*dpm_set_vce_enable)(struct smu_context *smu, bool enable);
++	int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
+ 	int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
+ 			   void *data, uint32_t *size);
+ 	int (*pre_display_config_changed)(struct smu_context *smu);
+@@ -489,6 +491,7 @@ struct pptable_funcs {
+ 	int (*check_fw_version)(struct smu_context *smu);
+ 	int (*powergate_sdma)(struct smu_context *smu, bool gate);
+ 	int (*powergate_vcn)(struct smu_context *smu, bool gate);
++	int (*powergate_jpeg)(struct smu_context *smu, bool gate);
+ 	int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
+ 	int (*write_pptable)(struct smu_context *smu);
+ 	int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4454-drm-amd-powerplay-add-JPEG-power-control-for-Navi1x.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4454-drm-amd-powerplay-add-JPEG-power-control-for-Navi1x.patch
new file mode 100644
index 00000000..5b70052c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4454-drm-amd-powerplay-add-JPEG-power-control-for-Navi1x.patch
@@ -0,0 +1,77 @@
+From 6f400e9b6048209875131ea15013028e5a3babc1 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 14:11:01 -0500
+Subject: [PATCH 4454/4736] drm/amd/powerplay: add JPEG power control for
+ Navi1x
+
+By separating the JPEG power feature, and using its
+own PowerUp and PowerDown messages
+
+v2: remove PowerUpJpeg message argument
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 32 ++++++++++++++++++++--
+ 1 file changed, 30 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 6fd808312d4e..1efe243119dd 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -383,8 +383,10 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
+ 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
+ 
+ 	if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
+-		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT)
+-				| FEATURE_MASK(FEATURE_JPEG_PG_BIT);
++		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
++
++	if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
++		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
+ 
+ 	/* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
+ 	if (is_asic_secure(smu)) {
+@@ -664,6 +666,31 @@ static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
+ 	return ret;
+ }
+ 
++static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
++{
++	struct smu_power_context *smu_power = &smu->smu_power;
++	struct smu_power_gate *power_gate = &smu_power->power_gate;
++	int ret = 0;
++
++	if (enable) {
++		if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
++			ret = smu_send_smc_msg(smu, SMU_MSG_PowerUpJpeg);
++			if (ret)
++				return ret;
++		}
++		power_gate->jpeg_gated = false;
++	} else {
++		if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
++			ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg);
++			if (ret)
++				return ret;
++		}
++		power_gate->jpeg_gated = true;
++	}
++
++	return ret;
++}
++
+ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
+ 				       enum smu_clk_type clk_type,
+ 				       uint32_t *value)
+@@ -1995,6 +2022,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.get_allowed_feature_mask = navi10_get_allowed_feature_mask,
+ 	.set_default_dpm_table = navi10_set_default_dpm_table,
+ 	.dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
++	.dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
+ 	.get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
+ 	.print_clk_levels = navi10_print_clk_levels,
+ 	.force_clk_levels = navi10_force_clk_levels,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4455-drm-amd-powerplay-add-Powergate-JPEG-for-Renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4455-drm-amd-powerplay-add-Powergate-JPEG-for-Renoir.patch
new file mode 100644
index 00000000..67b1ae12
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4455-drm-amd-powerplay-add-Powergate-JPEG-for-Renoir.patch
@@ -0,0 +1,102 @@
+From 50d48dd469a08fa771cf82602133304e1bcebba9 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 14:22:06 -0500
+Subject: [PATCH 4455/4736] drm/amd/powerplay: add Powergate JPEG for Renoir
+
+Similar to SDMA, VCN etc.
+
+v2: add argument to both PowerUpJpeg and PowerDownJpeg messages
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  2 ++
+ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h |  2 ++
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c    |  1 +
+ drivers/gpu/drm/amd/powerplay/smu_internal.h  |  2 ++
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c     | 11 +++++++++++
+ 5 files changed, 18 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index f4bb804acbeb..defd083127f3 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1231,6 +1231,7 @@ static int smu_hw_init(void *handle)
+ 	if (adev->flags & AMD_IS_APU) {
+ 		smu_powergate_sdma(&adev->smu, false);
+ 		smu_powergate_vcn(&adev->smu, false);
++		smu_powergate_jpeg(&adev->smu, false);
+ 		smu_set_gfx_cgpg(&adev->smu, true);
+ 	}
+ 
+@@ -1289,6 +1290,7 @@ static int smu_hw_fini(void *handle)
+ 	if (adev->flags & AMD_IS_APU) {
+ 		smu_powergate_sdma(&adev->smu, true);
+ 		smu_powergate_vcn(&adev->smu, true);
++		smu_powergate_jpeg(&adev->smu, true);
+ 	}
+ 
+ 	ret = smu_stop_thermal_control(smu);
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+index 9b9f5df0911c..1745e0146fba 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+@@ -58,6 +58,8 @@ int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate);
+ 
+ int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate);
+ 
++int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate);
++
+ int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
+ 
+ uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu);
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 04daf7e9fe05..492a201554e8 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -697,6 +697,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.check_fw_version = smu_v12_0_check_fw_version,
+ 	.powergate_sdma = smu_v12_0_powergate_sdma,
+ 	.powergate_vcn = smu_v12_0_powergate_vcn,
++	.powergate_jpeg = smu_v12_0_powergate_jpeg,
+ 	.send_smc_msg = smu_v12_0_send_msg,
+ 	.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
+ 	.read_smc_arg = smu_v12_0_read_arg,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+index 8bcda7871309..70c4d66721cd 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
++++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+@@ -42,6 +42,8 @@
+ 	((smu)->ppt_funcs->powergate_sdma ? (smu)->ppt_funcs->powergate_sdma((smu), (gate)) : 0)
+ #define smu_powergate_vcn(smu, gate) \
+ 	((smu)->ppt_funcs->powergate_vcn ? (smu)->ppt_funcs->powergate_vcn((smu), (gate)) : 0)
++#define smu_powergate_jpeg(smu, gate) \
++	((smu)->ppt_funcs->powergate_jpeg ? (smu)->ppt_funcs->powergate_jpeg((smu), (gate)) : 0)
+ 
+ #define smu_get_vbios_bootup_values(smu) \
+ 	((smu)->ppt_funcs->get_vbios_bootup_values ? (smu)->ppt_funcs->get_vbios_bootup_values((smu)) : 0)
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 139dd737eaa5..18b24f954380 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -203,6 +203,17 @@ int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
+ 		return smu_send_smc_msg(smu, SMU_MSG_PowerUpVcn);
+ }
+ 
++int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate)
++{
++	if (!(smu->adev->flags & AMD_IS_APU))
++		return 0;
++
++	if (gate)
++		return smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0);
++	else
++		return smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0);
++}
++
+ int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
+ {
+ 	if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4456-drm-amd-powerplay-add-JPEG-power-control-for-Renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4456-drm-amd-powerplay-add-JPEG-power-control-for-Renoir.patch
new file mode 100644
index 00000000..7ee8da30
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4456-drm-amd-powerplay-add-JPEG-power-control-for-Renoir.patch
@@ -0,0 +1,63 @@
+From 01eccfd69b33683292bb0c806ae62ea264bfae0b Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 14:33:10 -0500
+Subject: [PATCH 4456/4736] drm/amd/powerplay: add JPEG power control for
+ Renoir
+
+By using its own JPEG PowerUp and PowerDown messages
+
+v2: add argument to PowerDownJpeg message
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 26 ++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 492a201554e8..784903a313b7 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -301,6 +301,31 @@ static int renoir_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
+ 	return ret;
+ }
+ 
++static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
++{
++	struct smu_power_context *smu_power = &smu->smu_power;
++	struct smu_power_gate *power_gate = &smu_power->power_gate;
++	int ret = 0;
++
++	if (enable) {
++		if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
++			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0);
++			if (ret)
++				return ret;
++		}
++		power_gate->jpeg_gated = false;
++	} else {
++		if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
++			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0);
++			if (ret)
++				return ret;
++		}
++		power_gate->jpeg_gated = true;
++	}
++
++	return ret;
++}
++
+ static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
+ {
+ 	int ret = 0, i = 0;
+@@ -683,6 +708,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.print_clk_levels = renoir_print_clk_levels,
+ 	.get_current_power_state = renoir_get_current_power_state,
+ 	.dpm_set_uvd_enable = renoir_dpm_set_uvd_enable,
++	.dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
+ 	.force_dpm_limit_value = renoir_force_dpm_limit_value,
+ 	.unforce_dpm_levels = renoir_unforce_dpm_levels,
+ 	.get_workload_type = renoir_get_workload_type,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4457-drm-amd-powerplay-set-JPEG-to-SMU-dpm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4457-drm-amd-powerplay-set-JPEG-to-SMU-dpm.patch
new file mode 100644
index 00000000..fe5f9caa
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4457-drm-amd-powerplay-set-JPEG-to-SMU-dpm.patch
@@ -0,0 +1,44 @@
+From 905a3b89e3cfc064843a3c5271e2b852cbe3d7e4 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 14:38:08 -0500
+Subject: [PATCH 4457/4736] drm/amd/powerplay: set JPEG to SMU dpm
+
+By using its own IP block type.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c   | 3 +++
+ drivers/gpu/drm/amd/powerplay/smu_internal.h | 2 ++
+ 2 files changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index defd083127f3..d66db86836a1 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -415,6 +415,9 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
+ 	case AMD_IP_BLOCK_TYPE_SDMA:
+ 		ret = smu_powergate_sdma(smu, gate);
+ 		break;
++	case AMD_IP_BLOCK_TYPE_JPEG:
++		ret = smu_dpm_set_jpeg_enable(smu, gate);
++		break;
+ 	default:
+ 		break;
+ 	}
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+index 70c4d66721cd..b2d81d3490cd 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
++++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+@@ -172,6 +172,8 @@
+ 	((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
+ #define smu_dpm_set_vce_enable(smu, enable) \
+ 	((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
++#define smu_dpm_set_jpeg_enable(smu, enable) \
++	((smu)->ppt_funcs->dpm_set_jpeg_enable ? (smu)->ppt_funcs->dpm_set_jpeg_enable((smu), (enable)) : 0)
+ 
+ #define smu_set_watermarks_table(smu, tab, clock_ranges) \
+ 	((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4458-drm-amdgpu-enable-JPEG2.0-dpm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4458-drm-amdgpu-enable-JPEG2.0-dpm.patch
new file mode 100644
index 00000000..513e29a8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4458-drm-amdgpu-enable-JPEG2.0-dpm.patch
@@ -0,0 +1,81 @@
+From 826c350371077f7c2450fdf3e66a8431268e01f0 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Tue, 12 Nov 2019 11:57:36 -0500
+Subject: [PATCH 4458/4736] drm/amdgpu: enable JPEG2.0 dpm
+
+By using its own enabling function
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 12 ++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h |  1 +
+ drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 10 +++++++++-
+ 3 files changed, 22 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index 07f620938ae4..b4746dbe93a6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -2715,6 +2715,18 @@ void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
+ 
+ }
+ 
++void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable)
++{
++	int ret = 0;
++
++	if (is_support_sw_smu(adev)) {
++		ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_JPEG, enable);
++		if (ret)
++			DRM_ERROR("[SW SMU]: dpm enable jpeg failed, state = %s, ret = %d. \n",
++				  enable ? "true" : "false", ret);
++	}
++}
++
+ int amdgpu_pm_virt_sysfs_init(struct amdgpu_device *adev)
+ {
+        int ret = 0;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
+index ef31448ee8d8..3da1da277805 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
+@@ -41,5 +41,6 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev);
+ void amdgpu_dpm_thermal_work_handler(struct work_struct *work);
+ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
+ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);
++void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+index 3869730b2331..a78292d84854 100644
+--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+@@ -333,6 +333,9 @@ static int jpeg_v2_0_start(struct amdgpu_device *adev)
+ 	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
+ 	int r;
+ 
++	if (adev->pm.dpm_enabled)
++		amdgpu_dpm_enable_jpeg(adev, true);
++
+ 	/* disable power gating */
+ 	r = jpeg_v2_0_disable_power_gating(adev);
+ 	if (r)
+@@ -388,8 +391,13 @@ static int jpeg_v2_0_stop(struct amdgpu_device *adev)
+ 
+ 	/* enable power gating */
+ 	r = jpeg_v2_0_enable_power_gating(adev);
++	if (r)
++		return r;
+ 
+-	return r;
++	if (adev->pm.dpm_enabled)
++		amdgpu_dpm_enable_jpeg(adev, false);
++
++	return 0;
+ }
+ 
+ /**
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4459-drm-amdgpu-add-driver-support-for-JPEG2.0-and-above.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4459-drm-amdgpu-add-driver-support-for-JPEG2.0-and-above.patch
new file mode 100644
index 00000000..f79285f8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4459-drm-amdgpu-add-driver-support-for-JPEG2.0-and-above.patch
@@ -0,0 +1,67 @@
+From dda67852f76e087cf094ea0bed8610f27a6adbfc Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 15:00:58 -0500
+Subject: [PATCH 4459/4736] drm/amdgpu: add driver support for JPEG2.0 and
+ above
+
+By using JPEG IP block type
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c    | 9 +++++++--
+ 2 files changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 8bfbcbcb7f2e..7ccc9518c173 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1963,6 +1963,7 @@ static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
+ 		if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
+ 		    adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
+ 		    adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
++		    adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
+ 		    adev->ip_blocks[i].version->funcs->set_clockgating_state) {
+ 			/* enable clockgating to save power */
+ 			r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
+@@ -1993,6 +1994,7 @@ static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_power
+ 		if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
+ 		    adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
+ 		    adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
++		    adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
+ 		    adev->ip_blocks[i].version->funcs->set_powergating_state) {
+ 			/* enable powergating to save power */
+ 			r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index ab6e0fc5800f..3a7ea8e953f8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -397,7 +397,9 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
+ 		ib_size_alignment = 1;
+ 		break;
+ 	case AMDGPU_HW_IP_VCN_JPEG:
+-		type = AMD_IP_BLOCK_TYPE_VCN;
++		type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
++			AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
++
+ 		for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
+ 			if (adev->jpeg.harvest_config & (1 << i))
+ 				continue;
+@@ -535,9 +537,12 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
+ 			break;
+ 		case AMDGPU_HW_IP_VCN_DEC:
+ 		case AMDGPU_HW_IP_VCN_ENC:
+-		case AMDGPU_HW_IP_VCN_JPEG:
+ 			type = AMD_IP_BLOCK_TYPE_VCN;
+ 			break;
++		case AMDGPU_HW_IP_VCN_JPEG:
++			type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
++				AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
++			break;
+ 		default:
+ 			return -EINVAL;
+ 		}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4460-drm-amdgpu-enable-JPEG2.0-for-Navi1x-and-Renoir.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4460-drm-amdgpu-enable-JPEG2.0-for-Navi1x-and-Renoir.patch
new file mode 100644
index 00000000..e051b4ca
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4460-drm-amdgpu-enable-JPEG2.0-for-Navi1x-and-Renoir.patch
@@ -0,0 +1,65 @@
+From 8c9df10650bba97673ede035c1e5fcaba9053c87 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 8 Nov 2019 15:01:42 -0500
+Subject: [PATCH 4460/4736] drm/amdgpu: enable JPEG2.0 for Navi1x and Renoir
+
+By adding JPEG IP block to the family
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c    | 3 +++
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++
+ 2 files changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 0b8aedfe1b67..9163f3507a84 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -51,6 +51,7 @@
+ #include "gfx_v10_0.h"
+ #include "sdma_v5_0.h"
+ #include "vcn_v2_0.h"
++#include "jpeg_v2_0.h"
+ #include "dce_virtual.h"
+ #include "mes_v10_1.h"
+ #include "mxgpu_nv.h"
+@@ -462,6 +463,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ 		    is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
+ 			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
++		amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
+ 		if (adev->enable_mes)
+ 			amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
+ 		break;
+@@ -485,6 +487,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
+ 		    is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
+ 			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ 		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
++		amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
+ 		break;
+ 	default:
+ 		return -EINVAL;
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 233d3850789e..46741aefc52d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -66,6 +66,7 @@
+ #include "vce_v4_0.h"
+ #include "vcn_v1_0.h"
+ #include "vcn_v2_0.h"
++#include "jpeg_v2_0.h"
+ #include "vcn_v2_5.h"
+ #include "dce_virtual.h"
+ #include "mxgpu_ai.h"
+@@ -827,6 +828,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
+ #endif
+ 		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
++		amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
+ 		break;
+ 	default:
+ 		return -EINVAL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4461-drm-amdgpu-move-JPEG2.5-out-from-VCN2.5.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4461-drm-amdgpu-move-JPEG2.5-out-from-VCN2.5.patch
new file mode 100644
index 00000000..7ad116bf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4461-drm-amdgpu-move-JPEG2.5-out-from-VCN2.5.patch
@@ -0,0 +1,1500 @@
+From d078a2b7be1e7ff51af6940b0dac75ff90480c7b Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Mon, 11 Nov 2019 09:56:32 -0500
+Subject: [PATCH 4461/4736] drm/amdgpu: move JPEG2.5 out from VCN2.5
+
+And clean up the duplicated stuff
+
+Change-Id: Ia5502c8d4a5e1431bdd04e2392efe41f81b5ef7a
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile      |   3 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h |   3 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c  | 105 ----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h  |   5 -
+ drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c   | 641 +++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h   |  29 +
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c    | 236 ---------
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h    |  13 -
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c    | 246 +--------
+ 9 files changed, 679 insertions(+), 602 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index 7cbe646d1ae1..bfcc29fdced7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -156,7 +156,8 @@ amdgpu-y += \
+ 	vcn_v2_5.o \
+ 	amdgpu_jpeg.o \
+ 	jpeg_v1_0.o \
+-	jpeg_v2_0.o
++	jpeg_v2_0.o \
++	jpeg_v2_5.o
+ 
+ # add ATHUB block
+ amdgpu-y += \
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+index 5e2e06ec13df..5131a0a1bc8a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+@@ -26,6 +26,9 @@
+ 
+ #define AMDGPU_MAX_JPEG_INSTANCES	2
+ 
++#define AMDGPU_JPEG_HARVEST_JPEG0 (1 << 0)
++#define AMDGPU_JPEG_HARVEST_JPEG1 (1 << 1)
++
+ struct amdgpu_jpeg_reg{
+ 	unsigned jpeg_pitch;
+ };
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+index 9daa42f03886..2b9ae7725f42 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+@@ -705,108 +705,3 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+ 	amdgpu_bo_unref(&bo);
+ 	return r;
+ }
+-
+-int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-	uint32_t tmp = 0;
+-	unsigned i;
+-	int r;
+-
+-	WREG32(adev->vcn.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD);
+-	r = amdgpu_ring_alloc(ring, 3);
+-	if (r)
+-		return r;
+-
+-	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.jpeg_pitch, 0));
+-	amdgpu_ring_write(ring, 0xDEADBEEF);
+-	amdgpu_ring_commit(ring);
+-
+-	for (i = 0; i < adev->usec_timeout; i++) {
+-		tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch);
+-		if (tmp == 0xDEADBEEF)
+-			break;
+-		DRM_UDELAY(1);
+-	}
+-
+-	if (i >= adev->usec_timeout)
+-		r = -ETIMEDOUT;
+-
+-	return r;
+-}
+-
+-static int amdgpu_vcn_jpeg_set_reg(struct amdgpu_ring *ring, uint32_t handle,
+-		struct dma_fence **fence)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-	struct amdgpu_job *job;
+-	struct amdgpu_ib *ib;
+-	struct dma_fence *f = NULL;
+-	const unsigned ib_size_dw = 16;
+-	int i, r;
+-
+-	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+-	if (r)
+-		return r;
+-
+-	ib = &job->ibs[0];
+-
+-	ib->ptr[0] = PACKETJ(adev->vcn.internal.jpeg_pitch, 0, 0, PACKETJ_TYPE0);
+-	ib->ptr[1] = 0xDEADBEEF;
+-	for (i = 2; i < 16; i += 2) {
+-		ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
+-		ib->ptr[i+1] = 0;
+-	}
+-	ib->length_dw = 16;
+-
+-	r = amdgpu_job_submit_direct(job, ring, &f);
+-	if (r)
+-		goto err;
+-
+-	if (fence)
+-		*fence = dma_fence_get(f);
+-	dma_fence_put(f);
+-
+-	return 0;
+-
+-err:
+-	amdgpu_job_free(job);
+-	return r;
+-}
+-
+-int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-	uint32_t tmp = 0;
+-	unsigned i;
+-	struct dma_fence *fence = NULL;
+-	long r = 0;
+-
+-	r = amdgpu_vcn_jpeg_set_reg(ring, 1, &fence);
+-	if (r)
+-		goto error;
+-
+-	r = dma_fence_wait_timeout(fence, false, timeout);
+-	if (r == 0) {
+-		r = -ETIMEDOUT;
+-		goto error;
+-	} else if (r < 0) {
+-		goto error;
+-	} else {
+-		r = 0;
+-	}
+-
+-	for (i = 0; i < adev->usec_timeout; i++) {
+-		tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch);
+-		if (tmp == 0xDEADBEEF)
+-			break;
+-		DRM_UDELAY(1);
+-	}
+-
+-	if (i >= adev->usec_timeout)
+-		r = -ETIMEDOUT;
+-
+-	dma_fence_put(fence);
+-error:
+-	return r;
+-}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+index dface275c81a..402a5046b985 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+@@ -158,7 +158,6 @@ struct amdgpu_vcn_reg{
+ 	unsigned	ib_size;
+ 	unsigned	gp_scratch8;
+ 	unsigned	scratch9;
+-	unsigned	jpeg_pitch;
+ };
+ 
+ struct amdgpu_vcn_inst {
+@@ -168,7 +167,6 @@ struct amdgpu_vcn_inst {
+ 	void			*saved_bo;
+ 	struct amdgpu_ring	ring_dec;
+ 	struct amdgpu_ring	ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
+-	struct amdgpu_ring	ring_jpeg;
+ 	struct amdgpu_irq_src	irq;
+ 	struct amdgpu_vcn_reg	external;
+ };
+@@ -209,7 +207,4 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
+ int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
+ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
+ 
+-int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring);
+-int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout);
+-
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+new file mode 100644
+index 000000000000..2c58939e6ad0
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+@@ -0,0 +1,641 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#include "amdgpu.h"
++#include "amdgpu_jpeg.h"
++#include "soc15.h"
++#include "soc15d.h"
++#include "jpeg_v2_0.h"
++
++#include "vcn/vcn_2_5_offset.h"
++#include "vcn/vcn_2_5_sh_mask.h"
++#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
++
++#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET			0x401f
++
++#define JPEG25_MAX_HW_INSTANCES_ARCTURUS			2
++
++static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
++static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev);
++static int jpeg_v2_5_set_powergating_state(void *handle,
++				enum amd_powergating_state state);
++
++static int amdgpu_ih_clientid_jpeg[] = {
++	SOC15_IH_CLIENTID_VCN,
++	SOC15_IH_CLIENTID_VCN1
++};
++
++/**
++ * jpeg_v2_5_early_init - set function pointers
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Set ring and irq function pointers
++ */
++static int jpeg_v2_5_early_init(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	if (adev->asic_type == CHIP_ARCTURUS) {
++		u32 harvest;
++		int i;
++
++		adev->jpeg.num_jpeg_inst = JPEG25_MAX_HW_INSTANCES_ARCTURUS;
++		for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
++			harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING);
++			if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
++				adev->jpeg.harvest_config |= 1 << i;
++		}
++
++		if (adev->jpeg.harvest_config == (AMDGPU_JPEG_HARVEST_JPEG0 |
++						 AMDGPU_JPEG_HARVEST_JPEG1))
++			return -ENOENT;
++	} else
++		adev->jpeg.num_jpeg_inst = 1;
++
++	jpeg_v2_5_set_dec_ring_funcs(adev);
++	jpeg_v2_5_set_irq_funcs(adev);
++
++	return 0;
++}
++
++/**
++ * jpeg_v2_5_sw_init - sw init for JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Load firmware and sw initialization
++ */
++static int jpeg_v2_5_sw_init(void *handle)
++{
++	struct amdgpu_ring *ring;
++	int i, r;
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++		if (adev->jpeg.harvest_config & (1 << i))
++			continue;
++
++		/* JPEG TRAP */
++		r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i],
++				VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq);
++		if (r)
++			return r;
++	}
++
++	r = amdgpu_jpeg_sw_init(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_jpeg_resume(adev);
++	if (r)
++		return r;
++
++	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++		if (adev->jpeg.harvest_config & (1 << i))
++			continue;
++
++		ring = &adev->jpeg.inst[i].ring_dec;
++		ring->use_doorbell = true;
++		ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i;
++		sprintf(ring->name, "jpeg_dec_%d", i);
++		r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq, 0);
++		if (r)
++			return r;
++
++		adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
++		adev->jpeg.inst[i].external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH);
++	}
++
++	return 0;
++}
++
++/**
++ * jpeg_v2_5_sw_fini - sw fini for JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * JPEG suspend and free up sw allocation
++ */
++static int jpeg_v2_5_sw_fini(void *handle)
++{
++	int r;
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++
++	r = amdgpu_jpeg_suspend(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_jpeg_sw_fini(adev);
++
++	return r;
++}
++
++/**
++ * jpeg_v2_5_hw_init - start and test JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ */
++static int jpeg_v2_5_hw_init(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	struct amdgpu_ring *ring;
++	int i, r;
++
++	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++		if (adev->jpeg.harvest_config & (1 << i))
++			continue;
++
++		ring = &adev->jpeg.inst[i].ring_dec;
++		adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
++			(adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i, i);
++
++		r = amdgpu_ring_test_helper(ring);
++		if (r)
++			return r;
++	}
++
++	DRM_INFO("JPEG decode initialized successfully.\n");
++
++	return 0;
++}
++
++/**
++ * jpeg_v2_5_hw_fini - stop the hardware block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Stop the JPEG block, mark ring as not ready any more
++ */
++static int jpeg_v2_5_hw_fini(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	struct amdgpu_ring *ring;
++	int i;
++
++	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++		if (adev->jpeg.harvest_config & (1 << i))
++			continue;
++
++		ring = &adev->jpeg.inst[i].ring_dec;
++		if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
++		      RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
++			jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
++
++		ring->sched.ready = false;
++	}
++
++	return 0;
++}
++
++/**
++ * jpeg_v2_5_suspend - suspend JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * HW fini and suspend JPEG block
++ */
++static int jpeg_v2_5_suspend(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	int r;
++
++	r = jpeg_v2_5_hw_fini(adev);
++	if (r)
++		return r;
++
++	r = amdgpu_jpeg_suspend(adev);
++
++	return r;
++}
++
++/**
++ * jpeg_v2_5_resume - resume JPEG block
++ *
++ * @handle: amdgpu_device pointer
++ *
++ * Resume firmware and hw init JPEG block
++ */
++static int jpeg_v2_5_resume(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	int r;
++
++	r = amdgpu_jpeg_resume(adev);
++	if (r)
++		return r;
++
++	r = jpeg_v2_5_hw_init(adev);
++
++	return r;
++}
++
++static void jpeg_v2_5_disable_clock_gating(struct amdgpu_device* adev, int inst)
++{
++	uint32_t data;
++
++	data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
++	if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
++		data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++	else
++		data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
++
++	data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
++	data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
++	WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
++
++	data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
++	data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
++		| JPEG_CGC_GATE__JPEG2_DEC_MASK
++		| JPEG_CGC_GATE__JPEG_ENC_MASK
++		| JPEG_CGC_GATE__JMCIF_MASK
++		| JPEG_CGC_GATE__JRBBM_MASK);
++	WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
++
++	data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
++	data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
++		| JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
++		| JPEG_CGC_CTRL__JMCIF_MODE_MASK
++		| JPEG_CGC_CTRL__JRBBM_MODE_MASK);
++	WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
++}
++
++static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device* adev, int inst)
++{
++	uint32_t data;
++
++	data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
++	data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
++		|JPEG_CGC_GATE__JPEG2_DEC_MASK
++		|JPEG_CGC_GATE__JPEG_ENC_MASK
++		|JPEG_CGC_GATE__JMCIF_MASK
++		|JPEG_CGC_GATE__JRBBM_MASK);
++	WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
++}
++
++/**
++ * jpeg_v2_5_start - start JPEG block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * Setup and start the JPEG block
++ */
++static int jpeg_v2_5_start(struct amdgpu_device *adev)
++{
++	struct amdgpu_ring *ring;
++	int i;
++
++	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++		if (adev->jpeg.harvest_config & (1 << i))
++			continue;
++
++		ring = &adev->jpeg.inst[i].ring_dec;
++		/* disable anti hang mechanism */
++		WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0,
++			~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
++
++		/* JPEG disable CGC */
++		jpeg_v2_5_disable_clock_gating(adev, i);
++
++		/* MJPEG global tiling registers */
++		WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG,
++			adev->gfx.config.gb_addr_config);
++		WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG,
++			adev->gfx.config.gb_addr_config);
++
++		/* enable JMI channel */
++		WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0,
++			~UVD_JMI_CNTL__SOFT_RESET_MASK);
++
++		/* enable System Interrupt for JRBC */
++		WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN),
++			JPEG_SYS_INT_EN__DJRBC_MASK,
++			~JPEG_SYS_INT_EN__DJRBC_MASK);
++
++		WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0);
++		WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
++		WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
++			lower_32_bits(ring->gpu_addr));
++		WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
++			upper_32_bits(ring->gpu_addr));
++		WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0);
++		WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0);
++		WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L);
++		WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
++		ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR);
++	}
++
++	return 0;
++}
++
++/**
++ * jpeg_v2_5_stop - stop JPEG block
++ *
++ * @adev: amdgpu_device pointer
++ *
++ * stop the JPEG block
++ */
++static int jpeg_v2_5_stop(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++		if (adev->jpeg.harvest_config & (1 << i))
++			continue;
++
++		/* reset JMI */
++		WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL),
++			UVD_JMI_CNTL__SOFT_RESET_MASK,
++			~UVD_JMI_CNTL__SOFT_RESET_MASK);
++
++		jpeg_v2_5_enable_clock_gating(adev, i);
++
++		/* enable anti hang mechanism */
++		WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS),
++			UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
++			~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
++	}
++
++	return 0;
++}
++
++/**
++ * jpeg_v2_5_dec_ring_get_rptr - get read pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware read pointer
++ */
++static uint64_t jpeg_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR);
++}
++
++/**
++ * jpeg_v2_5_dec_ring_get_wptr - get write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Returns the current hardware write pointer
++ */
++static uint64_t jpeg_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	if (ring->use_doorbell)
++		return adev->wb.wb[ring->wptr_offs];
++	else
++		return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR);
++}
++
++/**
++ * jpeg_v2_5_dec_ring_set_wptr - set write pointer
++ *
++ * @ring: amdgpu_ring pointer
++ *
++ * Commits the write pointer to the hardware
++ */
++static void jpeg_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
++{
++	struct amdgpu_device *adev = ring->adev;
++
++	if (ring->use_doorbell) {
++		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
++		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
++	} else {
++		WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
++	}
++}
++
++static bool jpeg_v2_5_is_idle(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	int i, ret = 1;
++
++	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++		if (adev->jpeg.harvest_config & (1 << i))
++			continue;
++
++		ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) &
++			UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
++			UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
++	}
++
++	return ret;
++}
++
++static int jpeg_v2_5_wait_for_idle(void *handle)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	int i, ret = 0;
++
++	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++		if (adev->jpeg.harvest_config & (1 << i))
++			continue;
++
++		SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS,
++			UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
++			UVD_JRBC_STATUS__RB_JOB_DONE_MASK, ret);
++		if (ret)
++			return ret;
++	}
++
++	return ret;
++}
++
++static int jpeg_v2_5_set_clockgating_state(void *handle,
++					  enum amd_clockgating_state state)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
++	int i;
++
++	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++		if (adev->jpeg.harvest_config & (1 << i))
++			continue;
++
++		if (enable) {
++			if (jpeg_v2_5_is_idle(handle))
++				return -EBUSY;
++			jpeg_v2_5_enable_clock_gating(adev, i);
++		} else {
++			jpeg_v2_5_disable_clock_gating(adev, i);
++		}
++	}
++
++	return 0;
++}
++
++static int jpeg_v2_5_set_powergating_state(void *handle,
++					  enum amd_powergating_state state)
++{
++	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
++	int ret;
++
++	if(state == adev->jpeg.cur_state)
++		return 0;
++
++	if (state == AMD_PG_STATE_GATE)
++		ret = jpeg_v2_5_stop(adev);
++	else
++		ret = jpeg_v2_5_start(adev);
++
++	if(!ret)
++		adev->jpeg.cur_state = state;
++
++	return ret;
++}
++
++static int jpeg_v2_5_set_interrupt_state(struct amdgpu_device *adev,
++					struct amdgpu_irq_src *source,
++					unsigned type,
++					enum amdgpu_interrupt_state state)
++{
++	return 0;
++}
++
++static int jpeg_v2_5_process_interrupt(struct amdgpu_device *adev,
++				      struct amdgpu_irq_src *source,
++				      struct amdgpu_iv_entry *entry)
++{
++	uint32_t ip_instance;
++
++	switch (entry->client_id) {
++	case SOC15_IH_CLIENTID_VCN:
++		ip_instance = 0;
++		break;
++	case SOC15_IH_CLIENTID_VCN1:
++		ip_instance = 1;
++		break;
++	default:
++		DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
++		return 0;
++	}
++
++	DRM_DEBUG("IH: JPEG TRAP\n");
++
++	switch (entry->src_id) {
++	case VCN_2_0__SRCID__JPEG_DECODE:
++		amdgpu_fence_process(&adev->jpeg.inst[ip_instance].ring_dec);
++		break;
++	default:
++		DRM_ERROR("Unhandled interrupt: %d %d\n",
++			  entry->src_id, entry->src_data[0]);
++		break;
++	}
++
++	return 0;
++}
++
++static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = {
++	.name = "jpeg_v2_5",
++	.early_init = jpeg_v2_5_early_init,
++	.late_init = NULL,
++	.sw_init = jpeg_v2_5_sw_init,
++	.sw_fini = jpeg_v2_5_sw_fini,
++	.hw_init = jpeg_v2_5_hw_init,
++	.hw_fini = jpeg_v2_5_hw_fini,
++	.suspend = jpeg_v2_5_suspend,
++	.resume = jpeg_v2_5_resume,
++	.is_idle = jpeg_v2_5_is_idle,
++	.wait_for_idle = jpeg_v2_5_wait_for_idle,
++	.check_soft_reset = NULL,
++	.pre_soft_reset = NULL,
++	.soft_reset = NULL,
++	.post_soft_reset = NULL,
++	.set_clockgating_state = jpeg_v2_5_set_clockgating_state,
++	.set_powergating_state = jpeg_v2_5_set_powergating_state,
++};
++
++static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
++	.type = AMDGPU_RING_TYPE_VCN_JPEG,
++	.align_mask = 0xf,
++	.vmhub = AMDGPU_MMHUB_1,
++	.get_rptr = jpeg_v2_5_dec_ring_get_rptr,
++	.get_wptr = jpeg_v2_5_dec_ring_get_wptr,
++	.set_wptr = jpeg_v2_5_dec_ring_set_wptr,
++	.emit_frame_size =
++		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
++		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
++		8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */
++		18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */
++		8 + 16,
++	.emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */
++	.emit_ib = jpeg_v2_0_dec_ring_emit_ib,
++	.emit_fence = jpeg_v2_0_dec_ring_emit_fence,
++	.emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
++	.test_ring = amdgpu_jpeg_dec_ring_test_ring,
++	.test_ib = amdgpu_jpeg_dec_ring_test_ib,
++	.insert_nop = jpeg_v2_0_dec_ring_nop,
++	.insert_start = jpeg_v2_0_dec_ring_insert_start,
++	.insert_end = jpeg_v2_0_dec_ring_insert_end,
++	.pad_ib = amdgpu_ring_generic_pad_ib,
++	.begin_use = amdgpu_jpeg_ring_begin_use,
++	.end_use = amdgpu_jpeg_ring_end_use,
++	.emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
++	.emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
++	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
++};
++
++static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++		if (adev->jpeg.harvest_config & (1 << i))
++			continue;
++
++		adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_5_dec_ring_vm_funcs;
++		adev->jpeg.inst[i].ring_dec.me = i;
++		DRM_INFO("JPEG(%d) JPEG decode is enabled in VM mode\n", i);
++	}
++}
++
++static const struct amdgpu_irq_src_funcs jpeg_v2_5_irq_funcs = {
++	.set = jpeg_v2_5_set_interrupt_state,
++	.process = jpeg_v2_5_process_interrupt,
++};
++
++static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev)
++{
++	int i;
++
++	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
++		if (adev->jpeg.harvest_config & (1 << i))
++			continue;
++
++		adev->jpeg.inst[i].irq.num_types = 1;
++		adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs;
++	}
++}
++
++const struct amdgpu_ip_block_version jpeg_v2_5_ip_block =
++{
++		.type = AMD_IP_BLOCK_TYPE_JPEG,
++		.major = 2,
++		.minor = 5,
++		.rev = 0,
++		.funcs = &jpeg_v2_5_ip_funcs,
++};
+diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h
+new file mode 100644
+index 000000000000..2b4087c02620
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __JPEG_V2_5_H__
++#define __JPEG_V2_5_H__
++
++extern const struct amdgpu_ip_block_version jpeg_v2_5_ip_block;
++
++#endif /* __JPEG_V2_5_H__ */
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+index 4e0c3467deb2..7aba5a3ff3f7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+@@ -47,26 +47,6 @@
+ #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET		0x5a7
+ #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET			0x1e2
+ 
+-#define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 			0x1bfff
+-#define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET				0x4029
+-#define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET				0x402a
+-#define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET				0x402b
+-#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET		0x40ea
+-#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 	0x40eb
+-#define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET				0x40cf
+-#define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET				0x40d1
+-#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 		0x40e8
+-#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET		0x40e9
+-#define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET				0x4082
+-#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET		0x40ec
+-#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET 	0x40ed
+-#define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET			0x4085
+-#define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET				0x4084
+-#define mmUVD_JRBC_STATUS_INTERNAL_OFFSET				0x4089
+-#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET				0x401f
+-
+-#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR				0x18000
+-
+ #define mmUVD_RBC_XX_IB_REG_CHECK 					0x026b
+ #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 				1
+ #define mmUVD_REG_XX_MASK 						0x026c
+@@ -1616,222 +1596,6 @@ void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_
+ 	amdgpu_ring_write(ring, val);
+ }
+ 
+-/**
+- * vcn_v2_0_jpeg_ring_insert_start - insert a start command
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Write a start command to the ring.
+- */
+-void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
+-{
+-	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x68e04);
+-
+-	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x80010000);
+-}
+-
+-/**
+- * vcn_v2_0_jpeg_ring_insert_end - insert a end command
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Write a end command to the ring.
+- */
+-void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
+-{
+-	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x68e04);
+-
+-	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x00010000);
+-}
+-
+-/**
+- * vcn_v2_0_jpeg_ring_emit_fence - emit an fence & trap command
+- *
+- * @ring: amdgpu_ring pointer
+- * @fence: fence to emit
+- *
+- * Write a fence and a trap command to the ring.
+- */
+-void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
+-				unsigned flags)
+-{
+-	WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
+-
+-	amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, seq);
+-
+-	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, seq);
+-
+-	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, lower_32_bits(addr));
+-
+-	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, upper_32_bits(addr));
+-
+-	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x8);
+-
+-	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
+-		0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
+-	amdgpu_ring_write(ring, 0);
+-
+-	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x3fbc);
+-
+-	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x1);
+-
+-	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
+-	amdgpu_ring_write(ring, 0);
+-}
+-
+-/**
+- * vcn_v2_0_jpeg_ring_emit_ib - execute indirect buffer
+- *
+- * @ring: amdgpu_ring pointer
+- * @ib: indirect buffer to execute
+- *
+- * Write ring commands to execute the indirect buffer.
+- */
+-void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
+-				struct amdgpu_job *job,
+-				struct amdgpu_ib *ib,
+-				uint32_t flags)
+-{
+-	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
+-
+-	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, (vmid | (vmid << 4)));
+-
+-	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, (vmid | (vmid << 4)));
+-
+-	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
+-
+-	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
+-
+-	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, ib->length_dw);
+-
+-	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
+-
+-	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
+-
+-	amdgpu_ring_write(ring,	PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
+-	amdgpu_ring_write(ring, 0);
+-
+-	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x01400200);
+-
+-	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x2);
+-
+-	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET,
+-		0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
+-	amdgpu_ring_write(ring, 0x2);
+-}
+-
+-void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+-				uint32_t val, uint32_t mask)
+-{
+-	uint32_t reg_offset = (reg << 2);
+-
+-	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, 0x01400200);
+-
+-	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	amdgpu_ring_write(ring, val);
+-
+-	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
+-		amdgpu_ring_write(ring, 0);
+-		amdgpu_ring_write(ring,
+-			PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
+-	} else {
+-		amdgpu_ring_write(ring, reg_offset);
+-		amdgpu_ring_write(ring,	PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
+-			0, 0, PACKETJ_TYPE3));
+-	}
+-	amdgpu_ring_write(ring, mask);
+-}
+-
+-void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
+-				unsigned vmid, uint64_t pd_addr)
+-{
+-	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+-	uint32_t data0, data1, mask;
+-
+-	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
+-
+-	/* wait for register write */
+-	data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
+-	data1 = lower_32_bits(pd_addr);
+-	mask = 0xffffffff;
+-	vcn_v2_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask);
+-}
+-
+-void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
+-{
+-	uint32_t reg_offset = (reg << 2);
+-
+-	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
+-		0, 0, PACKETJ_TYPE0));
+-	if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
+-		amdgpu_ring_write(ring, 0);
+-		amdgpu_ring_write(ring,
+-			PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
+-	} else {
+-		amdgpu_ring_write(ring, reg_offset);
+-		amdgpu_ring_write(ring,	PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
+-			0, 0, PACKETJ_TYPE0));
+-	}
+-	amdgpu_ring_write(ring, val);
+-}
+-
+-void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
+-{
+-	int i;
+-
+-	WARN_ON(ring->wptr % 2 || count % 2);
+-
+-	for (i = 0; i < count / 2; i++) {
+-		amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
+-		amdgpu_ring_write(ring, 0);
+-	}
+-}
+-
+ static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev,
+ 					struct amdgpu_irq_src *source,
+ 					unsigned type,
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
+index 8467292f32e5..ef749b02ded9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
+@@ -49,19 +49,6 @@ extern void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
+ 				unsigned int vmid, uint64_t pd_addr);
+ extern void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
+ 
+-extern void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring);
+-extern void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring);
+-extern void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
+-				unsigned flags);
+-extern void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
+-				struct amdgpu_ib *ib, uint32_t flags);
+-extern void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
+-				uint32_t val, uint32_t mask);
+-extern void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
+-				unsigned vmid, uint64_t pd_addr);
+-extern void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
+-extern void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count);
+-
+ extern const struct amdgpu_ip_block_version vcn_v2_0_ip_block;
+ 
+ #endif /* __VCN_V2_0_H__ */
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index ff6cc77ad0b0..98f423f30d2f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -47,13 +47,10 @@
+ #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 	0x3b5
+ #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET			0x25c
+ 
+-#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET			0x401f
+-
+-#define VCN25_MAX_HW_INSTANCES_ARCTURUS				2
++#define VCN25_MAX_HW_INSTANCES_ARCTURUS			2
+ 
+ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
+ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
+-static void vcn_v2_5_set_jpeg_ring_funcs(struct amdgpu_device *adev);
+ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
+ static int vcn_v2_5_set_powergating_state(void *handle,
+ 				enum amd_powergating_state state);
+@@ -95,7 +92,6 @@ static int vcn_v2_5_early_init(void *handle)
+ 
+ 	vcn_v2_5_set_dec_ring_funcs(adev);
+ 	vcn_v2_5_set_enc_ring_funcs(adev);
+-	vcn_v2_5_set_jpeg_ring_funcs(adev);
+ 	vcn_v2_5_set_irq_funcs(adev);
+ 
+ 	return 0;
+@@ -130,12 +126,6 @@ static int vcn_v2_5_sw_init(void *handle)
+ 			if (r)
+ 				return r;
+ 		}
+-
+-		/* VCN JPEG TRAP */
+-		r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
+-				VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst[j].irq);
+-		if (r)
+-			return r;
+ 	}
+ 
+ 	r = amdgpu_vcn_sw_init(adev);
+@@ -184,9 +174,6 @@ static int vcn_v2_5_sw_init(void *handle)
+ 		adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
+ 		adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(UVD, j, mmUVD_NO_OP);
+ 
+-		adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
+-		adev->vcn.inst[j].external.jpeg_pitch = SOC15_REG_OFFSET(UVD, j, mmUVD_JPEG_PITCH);
+-
+ 		ring = &adev->vcn.inst[j].ring_dec;
+ 		ring->use_doorbell = true;
+ 		ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8*j;
+@@ -204,14 +191,6 @@ static int vcn_v2_5_sw_init(void *handle)
+ 			if (r)
+ 				return r;
+ 		}
+-
+-		ring = &adev->vcn.inst[j].ring_jpeg;
+-		ring->use_doorbell = true;
+-		ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8*j;
+-		sprintf(ring->name, "vcn_jpeg_%d", j);
+-		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0);
+-		if (r)
+-			return r;
+ 	}
+ 
+ 	return 0;
+@@ -269,12 +248,8 @@ static int vcn_v2_5_hw_init(void *handle)
+ 			if (r)
+ 				goto done;
+ 		}
+-
+-		ring = &adev->vcn.inst[j].ring_jpeg;
+-		r = amdgpu_ring_test_helper(ring);
+-		if (r)
+-			goto done;
+ 	}
++
+ done:
+ 	if (!r)
+ 		DRM_INFO("VCN decode and encode initialized successfully.\n");
+@@ -309,9 +284,6 @@ static int vcn_v2_5_hw_fini(void *handle)
+ 			ring = &adev->vcn.inst[i].ring_enc[i];
+ 			ring->sched.ready = false;
+ 		}
+-
+-		ring = &adev->vcn.inst[i].ring_jpeg;
+-		ring->sched.ready = false;
+ 	}
+ 
+ 	return 0;
+@@ -592,115 +564,6 @@ static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
+ 	}
+ }
+ 
+-/**
+- * jpeg_v2_5_start - start JPEG block
+- *
+- * @adev: amdgpu_device pointer
+- *
+- * Setup and start the JPEG block
+- */
+-static int jpeg_v2_5_start(struct amdgpu_device *adev)
+-{
+-	struct amdgpu_ring *ring;
+-	uint32_t tmp;
+-	int i;
+-
+-	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+-		if (adev->vcn.harvest_config & (1 << i))
+-			continue;
+-		ring = &adev->vcn.inst[i].ring_jpeg;
+-		/* disable anti hang mechanism */
+-		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS), 0,
+-			~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
+-
+-		/* JPEG disable CGC */
+-		tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL);
+-		tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+-		tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+-		tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+-		WREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL, tmp);
+-
+-		tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_GATE);
+-		tmp &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
+-			| JPEG_CGC_GATE__JPEG2_DEC_MASK
+-			| JPEG_CGC_GATE__JMCIF_MASK
+-			| JPEG_CGC_GATE__JRBBM_MASK);
+-		WREG32_SOC15(VCN, i, mmJPEG_CGC_GATE, tmp);
+-
+-		tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL);
+-		tmp &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
+-			| JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
+-			| JPEG_CGC_CTRL__JMCIF_MODE_MASK
+-			| JPEG_CGC_CTRL__JRBBM_MODE_MASK);
+-		WREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL, tmp);
+-
+-		/* MJPEG global tiling registers */
+-		WREG32_SOC15(UVD, i, mmJPEG_DEC_GFX8_ADDR_CONFIG,
+-			adev->gfx.config.gb_addr_config);
+-		WREG32_SOC15(UVD, i, mmJPEG_DEC_GFX10_ADDR_CONFIG,
+-			adev->gfx.config.gb_addr_config);
+-
+-		/* enable JMI channel */
+-		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL), 0,
+-			~UVD_JMI_CNTL__SOFT_RESET_MASK);
+-
+-		/* enable System Interrupt for JRBC */
+-		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmJPEG_SYS_INT_EN),
+-			JPEG_SYS_INT_EN__DJRBC_MASK,
+-			~JPEG_SYS_INT_EN__DJRBC_MASK);
+-
+-		WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_VMID, 0);
+-		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
+-		WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
+-			lower_32_bits(ring->gpu_addr));
+-		WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
+-			upper_32_bits(ring->gpu_addr));
+-		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_RPTR, 0);
+-		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR, 0);
+-		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_CNTL, 0x00000002L);
+-		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
+-		ring->wptr = RREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR);
+-	}
+-
+-	return 0;
+-}
+-
+-/**
+- * jpeg_v2_5_stop - stop JPEG block
+- *
+- * @adev: amdgpu_device pointer
+- *
+- * stop the JPEG block
+- */
+-static int jpeg_v2_5_stop(struct amdgpu_device *adev)
+-{
+-	uint32_t tmp;
+-	int i;
+-
+-	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+-		if (adev->vcn.harvest_config & (1 << i))
+-			continue;
+-		/* reset JMI */
+-		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL),
+-			UVD_JMI_CNTL__SOFT_RESET_MASK,
+-			~UVD_JMI_CNTL__SOFT_RESET_MASK);
+-
+-		tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_GATE);
+-		tmp |= (JPEG_CGC_GATE__JPEG_DEC_MASK
+-			|JPEG_CGC_GATE__JPEG2_DEC_MASK
+-			|JPEG_CGC_GATE__JMCIF_MASK
+-			|JPEG_CGC_GATE__JRBBM_MASK);
+-		WREG32_SOC15(VCN, i, mmJPEG_CGC_GATE, tmp);
+-
+-		/* enable anti hang mechanism */
+-		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS),
+-			UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
+-			~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
+-	}
+-
+-	return 0;
+-}
+-
+ static int vcn_v2_5_start(struct amdgpu_device *adev)
+ {
+ 	struct amdgpu_ring *ring;
+@@ -874,19 +737,14 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
+ 		WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+ 		WREG32_SOC15(UVD, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
+ 	}
+-	r = jpeg_v2_5_start(adev);
+ 
+-	return r;
++	return 0;
+ }
+ 
+ static int vcn_v2_5_stop(struct amdgpu_device *adev)
+ {
+ 	uint32_t tmp;
+-	int i, r;
+-
+-	r = jpeg_v2_5_stop(adev);
+-	if (r)
+-		return r;
++	int i, r = 0;
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ 		if (adev->vcn.harvest_config & (1 << i))
+@@ -1125,86 +983,6 @@ static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = {
+ 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+ };
+ 
+-/**
+- * vcn_v2_5_jpeg_ring_get_rptr - get read pointer
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Returns the current hardware read pointer
+- */
+-static uint64_t vcn_v2_5_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-
+-	return RREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_RPTR);
+-}
+-
+-/**
+- * vcn_v2_5_jpeg_ring_get_wptr - get write pointer
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Returns the current hardware write pointer
+- */
+-static uint64_t vcn_v2_5_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-
+-	if (ring->use_doorbell)
+-		return adev->wb.wb[ring->wptr_offs];
+-	else
+-		return RREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_WPTR);
+-}
+-
+-/**
+- * vcn_v2_5_jpeg_ring_set_wptr - set write pointer
+- *
+- * @ring: amdgpu_ring pointer
+- *
+- * Commits the write pointer to the hardware
+- */
+-static void vcn_v2_5_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
+-{
+-	struct amdgpu_device *adev = ring->adev;
+-
+-	if (ring->use_doorbell) {
+-		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+-		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
+-	} else {
+-		WREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
+-	}
+-}
+-
+-static const struct amdgpu_ring_funcs vcn_v2_5_jpeg_ring_vm_funcs = {
+-	.type = AMDGPU_RING_TYPE_VCN_JPEG,
+-	.align_mask = 0xf,
+-	.vmhub = AMDGPU_MMHUB_1,
+-	.get_rptr = vcn_v2_5_jpeg_ring_get_rptr,
+-	.get_wptr = vcn_v2_5_jpeg_ring_get_wptr,
+-	.set_wptr = vcn_v2_5_jpeg_ring_set_wptr,
+-	.emit_frame_size =
+-		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
+-		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
+-		8 + /* vcn_v2_0_jpeg_ring_emit_vm_flush */
+-		18 + 18 + /* vcn_v2_0_jpeg_ring_emit_fence x2 vm fence */
+-		8 + 16,
+-	.emit_ib_size = 22, /* vcn_v2_0_jpeg_ring_emit_ib */
+-	.emit_ib = vcn_v2_0_jpeg_ring_emit_ib,
+-	.emit_fence = vcn_v2_0_jpeg_ring_emit_fence,
+-	.emit_vm_flush = vcn_v2_0_jpeg_ring_emit_vm_flush,
+-	.test_ring = amdgpu_vcn_jpeg_ring_test_ring,
+-	.test_ib = amdgpu_vcn_jpeg_ring_test_ib,
+-	.insert_nop = vcn_v2_0_jpeg_ring_nop,
+-	.insert_start = vcn_v2_0_jpeg_ring_insert_start,
+-	.insert_end = vcn_v2_0_jpeg_ring_insert_end,
+-	.pad_ib = amdgpu_ring_generic_pad_ib,
+-	.begin_use = amdgpu_vcn_ring_begin_use,
+-	.end_use = amdgpu_vcn_ring_end_use,
+-	.emit_wreg = vcn_v2_0_jpeg_ring_emit_wreg,
+-	.emit_reg_wait = vcn_v2_0_jpeg_ring_emit_reg_wait,
+-	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+-};
+-
+ static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
+ {
+ 	int i;
+@@ -1233,19 +1011,6 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
+ 	}
+ }
+ 
+-static void vcn_v2_5_set_jpeg_ring_funcs(struct amdgpu_device *adev)
+-{
+-	int i;
+-
+-	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+-		if (adev->vcn.harvest_config & (1 << i))
+-			continue;
+-		adev->vcn.inst[i].ring_jpeg.funcs = &vcn_v2_5_jpeg_ring_vm_funcs;
+-		adev->vcn.inst[i].ring_jpeg.me = i;
+-		DRM_INFO("VCN(%d) jpeg decode is enabled in VM mode\n", i);
+-	}
+-}
+-
+ static bool vcn_v2_5_is_idle(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+@@ -1352,9 +1117,6 @@ static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev,
+ 	case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
+ 		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
+ 		break;
+-	case VCN_2_0__SRCID__JPEG_DECODE:
+-		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_jpeg);
+-		break;
+ 	default:
+ 		DRM_ERROR("Unhandled interrupt: %d %d\n",
+ 			  entry->src_id, entry->src_data[0]);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4462-drm-amdgpu-enable-Arcturus-CG-for-VCN-and-JPEG-block.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4462-drm-amdgpu-enable-Arcturus-CG-for-VCN-and-JPEG-block.patch
new file mode 100644
index 00000000..a0721f24
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4462-drm-amdgpu-enable-Arcturus-CG-for-VCN-and-JPEG-block.patch
@@ -0,0 +1,32 @@
+From c3574eb989136807e0d18af9751a29899aba2370 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Mon, 11 Nov 2019 10:27:03 -0500
+Subject: [PATCH 4462/4736] drm/amdgpu: enable Arcturus CG for VCN and JPEG
+ blocks
+
+Arcturus VCN and JPEG only got CG support, and no PG support
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 46741aefc52d..bfe82966626f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1212,7 +1212,9 @@ static int soc15_common_early_init(void *handle)
+ 			AMD_CG_SUPPORT_SDMA_LS |
+ 			AMD_CG_SUPPORT_MC_MGCG |
+ 			AMD_CG_SUPPORT_MC_LS |
+-			AMD_CG_SUPPORT_IH_CG;
++			AMD_CG_SUPPORT_IH_CG |
++			AMD_CG_SUPPORT_VCN_MGCG |
++			AMD_CG_SUPPORT_JPEG_MGCG;
+ 		adev->pg_flags = 0;
+ 		adev->external_rev_id = adev->rev_id + 0x32;
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4463-drm-amdgpu-enable-Arcturus-JPEG2.5-block.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4463-drm-amdgpu-enable-Arcturus-JPEG2.5-block.patch
new file mode 100644
index 00000000..2d3135ff
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4463-drm-amdgpu-enable-Arcturus-JPEG2.5-block.patch
@@ -0,0 +1,36 @@
+From d2f79333dd34c1cbb736976a6c46ea12aab53b70 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Mon, 11 Nov 2019 10:33:57 -0500
+Subject: [PATCH 4463/4736] drm/amdgpu: enable Arcturus JPEG2.5 block
+
+It also doen't care about FW loading type, so enabling it directly.
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index bfe82966626f..fea3222c40bc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -68,6 +68,7 @@
+ #include "vcn_v2_0.h"
+ #include "jpeg_v2_0.h"
+ #include "vcn_v2_5.h"
++#include "jpeg_v2_5.h"
+ #include "dce_virtual.h"
+ #include "mxgpu_ai.h"
+ #include "amdgpu_smu.h"
+@@ -810,6 +811,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ 
+ 		if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT))
+ 			amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
++		amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
+ 		break;
+ 	case CHIP_RENOIR:
+ 		amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4464-drm-amd-display-remove-set-but-not-used-variable-old.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4464-drm-amd-display-remove-set-but-not-used-variable-old.patch
new file mode 100644
index 00000000..42fd019e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4464-drm-amd-display-remove-set-but-not-used-variable-old.patch
@@ -0,0 +1,48 @@
+From 4aaf0fc347483a6dabdf6f101ea5efff193d53b4 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Thu, 14 Nov 2019 20:36:24 +0800
+Subject: [PATCH 4464/4736] drm/amd/display: remove set but not used variable
+ 'old_plane_crtc'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c: In function dm_determine_update_type_for_commit:
+drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:6516:36: warning: variable old_plane_crtc set but not used [-Wunused-but-set-variable]
+
+It is introduced by commit a87fa9938749 ("drm/amd/display:
+Build stream update and plane updates in dm"), but never used,
+so remove it.
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 95cfe4213362..ec9fac7d4559 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -7495,7 +7495,7 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
+ 	int i, j, num_plane, ret = 0;
+ 	struct drm_plane_state *old_plane_state, *new_plane_state;
+ 	struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
+-	struct drm_crtc *new_plane_crtc, *old_plane_crtc;
++	struct drm_crtc *new_plane_crtc;
+ 	struct drm_plane *plane;
+ 
+ 	struct drm_crtc *crtc;
+@@ -7541,7 +7541,6 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
+                         uint64_t tiling_flags;
+ 
+ 			new_plane_crtc = new_plane_state->crtc;
+-			old_plane_crtc = old_plane_state->crtc;
+ 			new_dm_plane_state = to_dm_plane_state(new_plane_state);
+ 			old_dm_plane_state = to_dm_plane_state(old_plane_state);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4465-drm-amd-display-remove-set-but-not-used-variable-bp-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4465-drm-amd-display-remove-set-but-not-used-variable-bp-.patch
new file mode 100644
index 00000000..303ae0d2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4465-drm-amd-display-remove-set-but-not-used-variable-bp-.patch
@@ -0,0 +1,46 @@
+From d893e6ec4d584cc6f51cd1607ecbb7a02e2d2e2b Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Thu, 14 Nov 2019 20:36:25 +0800
+Subject: [PATCH 4465/4736] drm/amd/display: remove set but not used variable
+ 'bp' in bios_parser2.c
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c: In function bios_get_board_layout_info:
+drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c:1826:22: warning: variable bp set but not used [-Wunused-but-set-variable]
+
+It is introduced by commit 1eeedbcc20d6 ("drm/amd/display:
+get board layout for edid emulation"), but never used,
+so remove it.
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index 3e2f21af2be7..884b07774f6d 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -1838,7 +1838,6 @@ static enum bp_result bios_get_board_layout_info(
+ 	struct board_layout_info *board_layout_info)
+ {
+ 	unsigned int i;
+-	struct bios_parser *bp;
+ 	enum bp_result record_result;
+ 
+ 	const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
+@@ -1847,7 +1846,6 @@ static enum bp_result bios_get_board_layout_info(
+ 		0, 0
+ 	};
+ 
+-	bp = BP_FROM_DCB(dcb);
+ 	if (board_layout_info == NULL) {
+ 		DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
+ 		return BP_RESULT_BADINPUT;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4466-drm-amd-display-remove-set-but-not-used-variable-bp-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4466-drm-amd-display-remove-set-but-not-used-variable-bp-.patch
new file mode 100644
index 00000000..6d2afeb6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4466-drm-amd-display-remove-set-but-not-used-variable-bp-.patch
@@ -0,0 +1,46 @@
+From f897d81ca52f3e03b453d47479292471a55a9191 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Thu, 14 Nov 2019 20:36:26 +0800
+Subject: [PATCH 4466/4736] drm/amd/display: remove set but not used variable
+ 'bp' in bios_parser.c
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/display/dc/bios/bios_parser.c: In function bios_get_board_layout_info:
+drivers/gpu/drm/amd/display/dc/bios/bios_parser.c:2743:22: warning: variable bp set but not used [-Wunused-but-set-variable]
+
+It is introduced by commit 1eeedbcc20d6 ("drm/amd/display:
+get board layout for edid emulation"), but never used,
+so remove it.
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+index 7466e6332299..0d4993691199 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+@@ -2737,7 +2737,6 @@ static enum bp_result bios_get_board_layout_info(
+ 	struct board_layout_info *board_layout_info)
+ {
+ 	unsigned int i;
+-	struct bios_parser *bp;
+ 	enum bp_result record_result;
+ 
+ 	const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
+@@ -2746,7 +2745,6 @@ static enum bp_result bios_get_board_layout_info(
+ 		0, 0
+ 	};
+ 
+-	bp = BP_FROM_DCB(dcb);
+ 	if (board_layout_info == NULL) {
+ 		DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
+ 		return BP_RESULT_BADINPUT;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4467-drm-amd-display-remove-set-but-not-used-variable-min.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4467-drm-amd-display-remove-set-but-not-used-variable-min.patch
new file mode 100644
index 00000000..73eb40d4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4467-drm-amd-display-remove-set-but-not-used-variable-min.patch
@@ -0,0 +1,45 @@
+From 8f25ee16ced424a3d2bd8af0a3513a0feeb372d4 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Thu, 14 Nov 2019 20:36:27 +0800
+Subject: [PATCH 4467/4736] drm/amd/display: remove set but not used variable
+ 'min_content'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/display/modules/color/color_gamma.c: In function build_freesync_hdr:
+drivers/gpu/drm/amd/display/modules/color/color_gamma.c:830:20: warning: variable min_content set but not used [-Wunused-but-set-variable]
+
+It is not used since commit 50575eb5b339 ("drm/amd/display:
+Only use EETF when maxCL > max display")
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+index 962a57f75e12..3f467c98b02f 100644
+--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
++++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+@@ -934,7 +934,6 @@ static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
+ 	struct fixed31_32 max_display;
+ 	struct fixed31_32 min_display;
+ 	struct fixed31_32 max_content;
+-	struct fixed31_32 min_content;
+ 	struct fixed31_32 clip = dc_fixpt_one;
+ 	struct fixed31_32 output;
+ 	bool use_eetf = false;
+@@ -948,7 +947,6 @@ static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
+ 	max_display = dc_fixpt_from_int(fs_params->max_display);
+ 	min_display = dc_fixpt_from_fraction(fs_params->min_display, 10000);
+ 	max_content = dc_fixpt_from_int(fs_params->max_content);
+-	min_content = dc_fixpt_from_fraction(fs_params->min_content, 10000);
+ 	sdr_white_level = dc_fixpt_from_int(fs_params->sdr_white_level);
+ 
+ 	if (fs_params->min_display > 1000) // cap at 0.1 at the bottom
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4468-drm-amdgpu-dm-Do-not-throw-an-error-for-a-display-wi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4468-drm-amdgpu-dm-Do-not-throw-an-error-for-a-display-wi.patch
new file mode 100644
index 00000000..6150b42b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4468-drm-amdgpu-dm-Do-not-throw-an-error-for-a-display-wi.patch
@@ -0,0 +1,38 @@
+From 9ab22e7215390717598165b675ef41eb105eeb91 Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Thu, 14 Nov 2019 20:44:13 +0000
+Subject: [PATCH 4468/4736] drm/amdgpu/dm: Do not throw an error for a display
+ with no audio
+
+An old display with no audio may not have an EDID with a CEA block, or
+it may simply be too old to support audio. This is not a driver error,
+so don't flag it as such.
+
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112140
+References: ae2a3495973e ("drm/amd: be quiet when no SAD block is found")
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Harry Wentland <harry.wentland@amd.com>
+Cc: Jean Delvare <jdelvare@suse.de>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+index d14284602ced..92ba7ca84d7c 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+@@ -98,8 +98,6 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
+ 			(struct edid *) edid->raw_edid);
+ 
+ 	sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
+-	if (sad_count < 0)
+-		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
+ 	if (sad_count <= 0)
+ 		return result;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4469-drm-amd-powerplay-avoid-DPM-reenable-process-on-Navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4469-drm-amd-powerplay-avoid-DPM-reenable-process-on-Navi.patch
new file mode 100644
index 00000000..9e104fd6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4469-drm-amd-powerplay-avoid-DPM-reenable-process-on-Navi.patch
@@ -0,0 +1,90 @@
+From a1a63a29b5717b05ea6b8e9a9a3982adfade96d4 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 11 Nov 2019 17:15:02 +0800
+Subject: [PATCH 4469/4736] drm/amd/powerplay: avoid DPM reenable process on
+ Navi1x ASICs V2
+
+Otherwise, without RLC reinitialization, the DPM reenablement
+will fail. That affects the custom pptable uploading.
+
+V2: setting/clearing uploading_custom_pp_table in
+    smu_sys_set_pp_table()
+
+Change-Id: I6fe2ed5ce23f2a5b66f371c0b6d1f924837e5af6
+Reported-by: Matt Coffin <mcoffin13@gmail.com>
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Tested-by: Matt Coffin <mcoffin13@gmail.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 31 ++++++++++++++++---
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  1 +
+ 2 files changed, 28 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index d66db86836a1..9483f5ff64e7 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -594,10 +594,18 @@ int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
+ 	smu_table->power_play_table = smu_table->hardcode_pptable;
+ 	smu_table->power_play_table_size = size;
+ 
++	/*
++	 * Special hw_fini action(for Navi1x, the DPMs disablement will be
++	 * skipped) may be needed for custom pptable uploading.
++	 */
++	smu->uploading_custom_pp_table = true;
++
+ 	ret = smu_reset(smu);
+ 	if (ret)
+ 		pr_info("smu reset failed, ret = %d\n", ret);
+ 
++	smu->uploading_custom_pp_table = false;
++
+ failed:
+ 	mutex_unlock(&smu->mutex);
+ 	return ret;
+@@ -1302,10 +1310,25 @@ static int smu_hw_fini(void *handle)
+ 		return ret;
+ 	}
+ 
+-	ret = smu_stop_dpms(smu);
+-	if (ret) {
+-		pr_warn("Fail to stop Dpms!\n");
+-		return ret;
++	/*
++	 * For custom pptable uploading, skip the DPM features
++	 * disable process on Navi1x ASICs.
++	 *   - As the gfx related features are under control of
++	 *     RLC on those ASICs. RLC reinitialization will be
++	 *     needed to reenable them. That will cost much more
++	 *     efforts.
++	 *
++	 *   - SMU firmware can handle the DPM reenablement
++	 *     properly.
++	 */
++	if (!smu->uploading_custom_pp_table ||
++	    !((adev->asic_type >= CHIP_NAVI10) &&
++	      (adev->asic_type <= CHIP_NAVI12))) {
++		ret = smu_stop_dpms(smu);
++		if (ret) {
++			pr_warn("Fail to stop Dpms!\n");
++			return ret;
++		}
+ 	}
+ 
+ 	kfree(table_context->driver_pptable);
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index cdd46cdaffb8..5bac7efcd6ee 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -391,6 +391,7 @@ struct smu_context
+ 
+ 	uint32_t smc_if_version;
+ 
++	bool uploading_custom_pp_table;
+ };
+ 
+ struct i2c_adapter;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4470-drm-amd-powerplay-issue-BTC-on-Navi-during-SMU-setup.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4470-drm-amd-powerplay-issue-BTC-on-Navi-during-SMU-setup.patch
new file mode 100644
index 00000000..6dbab59a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4470-drm-amd-powerplay-issue-BTC-on-Navi-during-SMU-setup.patch
@@ -0,0 +1,48 @@
+From ce9a49c741e9182e8ae23a9c7b774408aa33d942 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 12 Nov 2019 14:18:54 +0800
+Subject: [PATCH 4470/4736] drm/amd/powerplay: issue BTC on Navi during SMU
+ setup
+
+RunBTC is added for Navi ASIC on hardware setup.
+
+Change-Id: I1c04b481ed14d5f12c20b7b0d592b62a65889e4a
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 1efe243119dd..e0bc4f73dae9 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -2007,6 +2007,17 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL
+ 	return ret;
+ }
+ 
++static int navi10_run_btc(struct smu_context *smu)
++{
++	int ret = 0;
++
++	ret = smu_send_smc_msg(smu, SMU_MSG_RunBtc);
++	if (ret)
++		pr_err("RunBtc failed!\n");
++
++	return ret;
++}
++
+ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.tables_init = navi10_tables_init,
+ 	.alloc_dpm_context = navi10_allocate_dpm_context,
+@@ -2099,6 +2110,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.set_default_od_settings = navi10_set_default_od_settings,
+ 	.od_edit_dpm_table = navi10_od_edit_dpm_table,
+ 	.get_pptable_power_limit = navi10_get_pptable_power_limit,
++	.run_btc = navi10_run_btc,
+ };
+ 
+ void navi10_set_ppt_funcs(struct smu_context *smu)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4471-drm-amd-powerplay-issue-no-PPSMC_MSG_GetCurrPkgPwr-o.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4471-drm-amd-powerplay-issue-no-PPSMC_MSG_GetCurrPkgPwr-o.patch
new file mode 100644
index 00000000..a840d469
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4471-drm-amd-powerplay-issue-no-PPSMC_MSG_GetCurrPkgPwr-o.patch
@@ -0,0 +1,59 @@
+From d1cfc704affbbc82579adff6d3a769b38d9f6500 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 14 Nov 2019 15:30:39 +0800
+Subject: [PATCH 4471/4736] drm/amd/powerplay: issue no PPSMC_MSG_GetCurrPkgPwr
+ on unsupported ASICs
+
+Otherwise, the error message prompted will confuse user.
+
+Change-Id: I44b9f870a8663714d715a1d5bf2aa24abe75bb8e
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c  | 23 +++++++++++++++----
+ 1 file changed, 18 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+index d3c3b3512a16..5c6b71b356e7 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -3476,18 +3476,31 @@ static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
+ 
+ static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query)
+ {
++	struct amdgpu_device *adev = hwmgr->adev;
+ 	int i;
+ 	u32 tmp = 0;
+ 
+ 	if (!query)
+ 		return -EINVAL;
+ 
+-	smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0);
+-	tmp = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
+-	*query = tmp;
++	/*
++	 * PPSMC_MSG_GetCurrPkgPwr is not supported on:
++	 *  - Hawaii
++	 *  - Bonaire
++	 *  - Fiji
++	 *  - Tonga
++	 */
++	if ((adev->asic_type != CHIP_HAWAII) &&
++	    (adev->asic_type != CHIP_BONAIRE) &&
++	    (adev->asic_type != CHIP_FIJI) &&
++	    (adev->asic_type != CHIP_TONGA)) {
++		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0);
++		tmp = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
++		*query = tmp;
+ 
+-	if (tmp != 0)
+-		return 0;
++		if (tmp != 0)
++			return 0;
++	}
+ 
+ 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
+ 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4472-drm-amd-powerplay-correct-fine-grained-dpm-force-lev.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4472-drm-amd-powerplay-correct-fine-grained-dpm-force-lev.patch
new file mode 100644
index 00000000..b9de8740
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4472-drm-amd-powerplay-correct-fine-grained-dpm-force-lev.patch
@@ -0,0 +1,38 @@
+From 1572e7a9f2a2906fb27b0f79b0a64fbf2eaa9e01 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Thu, 14 Nov 2019 16:58:31 +0800
+Subject: [PATCH 4472/4736] drm/amd/powerplay: correct fine grained dpm force
+ level setting
+
+For fine grained dpm, there is only two levels supported. However
+to reflect correctly the current clock frequency, there is an
+intermediate level faked. Thus on forcing level setting, we
+need to treat level 2 correctly as level 1.
+
+Change-Id: I32f936636f27eb8d8d9002bedd701f2bb0d3060a
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index e0bc4f73dae9..8d5f33baaa77 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -886,6 +886,12 @@ static int navi10_force_clk_levels(struct smu_context *smu,
+ 	case SMU_UCLK:
+ 	case SMU_DCEFCLK:
+ 	case SMU_FCLK:
++		/* There is only 2 levels for fine grained DPM */
++		if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
++			soft_max_level = (soft_max_level >= 1 ? 1 : 0);
++			soft_min_level = (soft_min_level >= 1 ? 1 : 0);
++		}
++
+ 		ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
+ 		if (ret)
+ 			return size;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4473-drm-amd-display-Renoir-chroma-viewport-WA-change-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4473-drm-amd-display-Renoir-chroma-viewport-WA-change-for.patch
new file mode 100644
index 00000000..5e7d191a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4473-drm-amd-display-Renoir-chroma-viewport-WA-change-for.patch
@@ -0,0 +1,41 @@
+From 5ba99cdaa75b41227f78ad74625b07a686bc0279 Mon Sep 17 00:00:00 2001
+From: Joseph Gravenor <joseph.gravenor@amd.com>
+Date: Thu, 17 Oct 2019 11:56:34 -0400
+Subject: [PATCH 4473/4736] drm/amd/display: Renoir chroma viewport WA change
+ formula
+
+[why]
+we want to increase the pte row plus 1 line if chroma viewport
+height is integer multiple of the pte row height
+
+[how]
+instead of ceiling viewport height, we floor it. this allows
+us to accommodate both cases: those where the chroma viewport
+height is integer multiple of the pte row height and those where
+it is not
+
+Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+index 1ddd6ae22155..d86b6b6211bc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+@@ -204,8 +204,8 @@ void hubp21_set_viewport(
+ 			PTE_ROW_HEIGHT_LINEAR, &pte_row_height);
+ 
+ 		pte_row_height = 1 << (pte_row_height + 3);
+-		pte_rows = (viewport_c->height + pte_row_height - 1) / pte_row_height;
+-		patched_viewport_height = pte_rows * pte_row_height + 3;
++		pte_rows = (viewport_c->height / pte_row_height) + 1;
++		patched_viewport_height = pte_rows * pte_row_height + 1;
+ 	}
+ 
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4474-drm-amd-display-Renoir-chroma-viewport-WA-Read-the-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4474-drm-amd-display-Renoir-chroma-viewport-WA-Read-the-c.patch
new file mode 100644
index 00000000..9efd8311
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4474-drm-amd-display-Renoir-chroma-viewport-WA-Read-the-c.patch
@@ -0,0 +1,40 @@
+From bf8935938a1e4b88d9c1edea7ff93957b2d096e7 Mon Sep 17 00:00:00 2001
+From: Joseph Gravenor <joseph.gravenor@amd.com>
+Date: Thu, 24 Oct 2019 13:55:10 -0400
+Subject: [PATCH 4474/4736] drm/amd/display: Renoir chroma viewport WA Read the
+ correct register
+
+[why]
+Before we were reading registers specific to luma size, which caused a black line
+to appear on the screen from time to time, as although the luma row height
+is generally the same as the chroma row height for the video case, it will sometimes
+be one more
+
+[how]
+Read the register specific for the chroma size
+
+Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+index d86b6b6211bc..32e8b589aeb5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+@@ -200,8 +200,8 @@ void hubp21_set_viewport(
+ 		int pte_row_height = 0;
+ 		int pte_rows = 0;
+ 
+-		REG_GET(DCHUBP_REQ_SIZE_CONFIG,
+-			PTE_ROW_HEIGHT_LINEAR, &pte_row_height);
++		REG_GET(DCHUBP_REQ_SIZE_CONFIG_C,
++			PTE_ROW_HEIGHT_LINEAR_C, &pte_row_height);
+ 
+ 		pte_row_height = 1 << (pte_row_height + 3);
+ 		pte_rows = (viewport_c->height / pte_row_height) + 1;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4475-drm-amd-display-Add-hubp-clock-status-in-DTN-log-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4475-drm-amd-display-Add-hubp-clock-status-in-DTN-log-for.patch
new file mode 100644
index 00000000..2e708fec
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4475-drm-amd-display-Add-hubp-clock-status-in-DTN-log-for.patch
@@ -0,0 +1,37 @@
+From d6aad171628f54a3c309e4007e94fa31cb6bfae9 Mon Sep 17 00:00:00 2001
+From: "Leo (Hanghong) Ma" <hanghong.ma@amd.com>
+Date: Fri, 25 Oct 2019 09:40:13 -0400
+Subject: [PATCH 4475/4736] drm/amd/display: Add hubp clock status in DTN log
+ for Navi
+
+[Why]
+For debug purpose, we need to check HUBP_CLOCK_ENABLE in DTN
+log debugfs on Navi.
+
+[How]
+Add related register read in dcn20_hubp.c.
+
+Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
+Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+index 69e2aae42394..391f0629b955 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+@@ -1204,6 +1204,9 @@ void hubp2_read_state_common(struct hubp *hubp)
+ 			HUBP_TTU_DISABLE, &s->ttu_disable,
+ 			HUBP_UNDERFLOW_STATUS, &s->underflow_status);
+ 
++	REG_GET(HUBP_CLK_CNTL,
++			HUBP_CLOCK_ENABLE, &s->clock_en);
++
+ 	REG_GET(DCN_GLOBAL_TTU_CNTL,
+ 			MIN_TTU_VBLANK, &s->min_ttu_vblank);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4476-drm-amd-display-Update-background-color-in-bottommos.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4476-drm-amd-display-Update-background-color-in-bottommos.patch
new file mode 100644
index 00000000..1cbacf38
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4476-drm-amd-display-Update-background-color-in-bottommos.patch
@@ -0,0 +1,60 @@
+From 005868d633f371451d5954e6ad62e5be20745f9f Mon Sep 17 00:00:00 2001
+From: Hugo Hu <hugo.hu@amd.com>
+Date: Fri, 25 Oct 2019 15:33:15 +0800
+Subject: [PATCH 4476/4736] drm/amd/display: Update background color in
+ bottommost mpcc
+
+[Why]
+Background color only takes effect in bottommost mpcc.
+
+[How]
+Update background color in bottommost mpcc.
+
+Signed-off-by: Hugo Hu <hugo.hu@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c  | 19 +++++++++++++------
+ 1 file changed, 13 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+index 8b2f29f6dabd..b3f66e1de15d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+@@ -42,20 +42,27 @@ void mpc1_set_bg_color(struct mpc *mpc,
+ 		int mpcc_id)
+ {
+ 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
++	struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id);
++	uint32_t bg_r_cr, bg_g_y, bg_b_cb;
++
++	/* find bottommost mpcc. */
++	while (bottommost_mpcc->mpcc_bot) {
++		bottommost_mpcc = bottommost_mpcc->mpcc_bot;
++	}
+ 
+ 	/* mpc color is 12 bit.  tg_color is 10 bit */
+ 	/* todo: might want to use 16 bit to represent color and have each
+ 	 * hw block translate to correct color depth.
+ 	 */
+-	uint32_t bg_r_cr = bg_color->color_r_cr << 2;
+-	uint32_t bg_g_y = bg_color->color_g_y << 2;
+-	uint32_t bg_b_cb = bg_color->color_b_cb << 2;
++	bg_r_cr = bg_color->color_r_cr << 2;
++	bg_g_y = bg_color->color_g_y << 2;
++	bg_b_cb = bg_color->color_b_cb << 2;
+ 
+-	REG_SET(MPCC_BG_R_CR[mpcc_id], 0,
++	REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0,
+ 			MPCC_BG_R_CR, bg_r_cr);
+-	REG_SET(MPCC_BG_G_Y[mpcc_id], 0,
++	REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0,
+ 			MPCC_BG_G_Y, bg_g_y);
+-	REG_SET(MPCC_BG_B_CB[mpcc_id], 0,
++	REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0,
+ 			MPCC_BG_B_CB, bg_b_cb);
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4477-drm-amd-display-3.2.59.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4477-drm-amd-display-3.2.59.patch
new file mode 100644
index 00000000..b67d4c6b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4477-drm-amd-display-3.2.59.patch
@@ -0,0 +1,28 @@
+From f586a397a67b59604c7e8a21218906739f13c80a Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Mon, 28 Oct 2019 08:50:33 -0400
+Subject: [PATCH 4477/4736] drm/amd/display: 3.2.59
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 8ff7556eb2c4..b107d6fab972 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.58"
++#define DC_VER "3.2.59"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4478-drm-amd-display-Fix-stereo-with-DCC-enabled.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4478-drm-amd-display-Fix-stereo-with-DCC-enabled.patch
new file mode 100644
index 00000000..2f7c0d11
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4478-drm-amd-display-Fix-stereo-with-DCC-enabled.patch
@@ -0,0 +1,81 @@
+From 385499bca1590635946ebbfe750900f92baaf8b5 Mon Sep 17 00:00:00 2001
+From: Samson Tam <Samson.Tam@amd.com>
+Date: Wed, 23 Oct 2019 21:36:29 -0400
+Subject: [PATCH 4478/4736] drm/amd/display: Fix stereo with DCC enabled
+
+[Why]
+When sending DCC with Stereo, DCC gets enabled but the meta addresses
+are 0. This happens momentarily before the meta addresses are populated
+with a valid address.
+
+[How]
+Add call validate_dcc_with_meta_address() in
+copy_surface_update_to_plane() to check for surface address and DCC
+change.
+When DCC has changed, check if DCC enable is true but meta address is 0.
+If so, we turn DCC enable to false. When surface address has changed, we
+check if DCC enable is false but meta address is not 0. If so, we turn
+DCC enable back to true.  This will restore DCC enable to the proper
+setting once the meta address is valid.
+
+Signed-off-by: Samson Tam <Samson.Tam@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 27 ++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 9e600d3e2fd8..7a2cdf21ca34 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1764,12 +1764,37 @@ static struct dc_stream_status *stream_get_status(
+ 
+ static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
+ 
++static void validate_dcc_with_meta_address(
++	struct dc_plane_dcc_param *dcc,
++	struct dc_plane_address *address)
++{
++	if ((address->grph.meta_addr.quad_part == 0) &&
++		dcc->enable) {
++		ASSERT(!dcc->enable);
++		dcc->enable = false;
++	} else if ((address->grph.meta_addr.quad_part != 0) &&
++		!dcc->enable)
++		dcc->enable = true;
++
++	if (address->type != PLN_ADDR_TYPE_GRAPHICS) {
++		if ((address->grph_stereo.right_meta_addr.quad_part == 0) &&
++			dcc->enable) {
++			ASSERT(!dcc->enable);
++			dcc->enable = false;
++		} else if ((address->grph_stereo.right_meta_addr.quad_part != 0) &&
++			!dcc->enable)
++			dcc->enable = true;
++	}
++}
++
+ static void copy_surface_update_to_plane(
+ 		struct dc_plane_state *surface,
+ 		struct dc_surface_update *srf_update)
+ {
+ 	if (srf_update->flip_addr) {
+ 		surface->address = srf_update->flip_addr->address;
++		validate_dcc_with_meta_address(&surface->dcc, &surface->address);
++
+ 		surface->flip_immediate =
+ 			srf_update->flip_addr->flip_immediate;
+ 		surface->time.time_elapsed_in_us[surface->time.index] =
+@@ -1818,6 +1843,8 @@ static void copy_surface_update_to_plane(
+ 				srf_update->plane_info->global_alpha_value;
+ 		surface->dcc =
+ 				srf_update->plane_info->dcc;
++		validate_dcc_with_meta_address(&surface->dcc, &surface->address);
++
+ 		surface->sdr_white_level =
+ 				srf_update->plane_info->sdr_white_level;
+ 		surface->layer_index =
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4479-drm-amd-display-Changes-in-dc-to-allow-full-update-i.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4479-drm-amd-display-Changes-in-dc-to-allow-full-update-i.patch
new file mode 100644
index 00000000..c5ce8120
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4479-drm-amd-display-Changes-in-dc-to-allow-full-update-i.patch
@@ -0,0 +1,177 @@
+From 6b206971916027e93ec19a4c70ab10c36b25510a Mon Sep 17 00:00:00 2001
+From: Alvin Lee <alvin.lee2@amd.com>
+Date: Thu, 24 Oct 2019 15:45:44 -0400
+Subject: [PATCH 4479/4736] drm/amd/display: Changes in dc to allow full update
+ in some cases
+
+Changes in dc to allow for different cases where full update is
+required.
+
+Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 22 +++++++++++--------
+ .../drm/amd/display/dc/dcn20/dcn20_resource.h |  2 +-
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 11 +++++-----
+ .../gpu/drm/amd/display/dc/inc/core_types.h   |  2 +-
+ 4 files changed, 21 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 454d30bbfd20..d437be449edb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1799,10 +1799,11 @@ void dcn20_populate_dml_writeback_from_context(
+ }
+ 
+ int dcn20_populate_dml_pipes_from_context(
+-		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
++		struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
+ {
+ 	int pipe_cnt, i;
+ 	bool synchronized_vblank = true;
++	struct resource_context *res_ctx = &context->res_ctx;
+ 
+ 	for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
+ 		if (!res_ctx->pipe_ctx[i].stream)
+@@ -1822,10 +1823,13 @@ int dcn20_populate_dml_pipes_from_context(
+ 
+ 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
+ 		struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
++		unsigned int v_total;
+ 		int output_bpc;
+ 
+ 		if (!res_ctx->pipe_ctx[i].stream)
+ 			continue;
++
++		v_total = timing->v_total;
+ 		/* todo:
+ 		pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
+ 		pipes[pipe_cnt].pipe.src.dcc = 0;
+@@ -1840,7 +1844,7 @@ int dcn20_populate_dml_pipes_from_context(
+ 			pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
+ 			/* 1/2 vblank */
+ 			pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
+-				(timing->v_total - timing->v_addressable
++				(v_total - timing->v_addressable
+ 					- timing->v_border_top - timing->v_border_bottom) / 2;
+ 			/* 36 bytes dp, 32 hdmi */
+ 			pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
+@@ -1854,13 +1858,13 @@ int dcn20_populate_dml_pipes_from_context(
+ 				- timing->h_addressable
+ 				- timing->h_border_left
+ 				- timing->h_border_right;
+-		pipes[pipe_cnt].pipe.dest.vblank_start = timing->v_total - timing->v_front_porch;
++		pipes[pipe_cnt].pipe.dest.vblank_start = v_total - timing->v_front_porch;
+ 		pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
+ 				- timing->v_addressable
+ 				- timing->v_border_top
+ 				- timing->v_border_bottom;
+ 		pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
+-		pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total;
++		pipes[pipe_cnt].pipe.dest.vtotal = v_total;
+ 		pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
+ 		pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
+ 		pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
+@@ -1999,8 +2003,8 @@ int dcn20_populate_dml_pipes_from_context(
+ 			pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
+ 			pipes[pipe_cnt].pipe.src.is_hsplit = 0;
+ 			pipes[pipe_cnt].pipe.dest.odm_combine = 0;
+-			pipes[pipe_cnt].pipe.dest.vtotal_min = timing->v_total;
+-			pipes[pipe_cnt].pipe.dest.vtotal_max = timing->v_total;
++			pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
++			pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
+ 		} else {
+ 			struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
+ 			struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
+@@ -2466,7 +2470,7 @@ bool dcn20_fast_validate_bw(
+ 
+ 	dcn20_merge_pipes_for_validate(dc, context);
+ 
+-	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, &context->res_ctx, pipes);
++	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes);
+ 
+ 	*pipe_cnt_out = pipe_cnt;
+ 
+@@ -2614,10 +2618,10 @@ static void dcn20_calculate_wm(
+ 	if (pipe_cnt != pipe_idx) {
+ 		if (dc->res_pool->funcs->populate_dml_pipes)
+ 			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
+-				&context->res_ctx, pipes);
++				context, pipes);
+ 		else
+ 			pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
+-				&context->res_ctx, pipes);
++				context, pipes);
+ 	}
+ 
+ 	*out_pipe_cnt = pipe_cnt;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+index fef473d68a4a..7187e0f8eb28 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+@@ -50,7 +50,7 @@ unsigned int dcn20_calc_max_scaled_time(
+ 		enum mmhubbub_wbif_mode mode,
+ 		unsigned int urgent_watermark);
+ int dcn20_populate_dml_pipes_from_context(
+-		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
++		struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);
+ struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
+ 		struct dc_state *state,
+ 		const struct resource_pool *pool,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index e9db35c24073..de3ffefbf1f4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -656,7 +656,7 @@ static const struct dcn10_stream_encoder_mask se_mask = {
+ static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
+ 
+ static int dcn21_populate_dml_pipes_from_context(
+-		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
++		struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);
+ 
+ static struct input_pixel_processor *dcn21_ipp_create(
+ 	struct dc_context *ctx, uint32_t inst)
+@@ -1067,10 +1067,10 @@ void dcn21_calculate_wm(
+ 	if (pipe_cnt != pipe_idx) {
+ 		if (dc->res_pool->funcs->populate_dml_pipes)
+ 			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
+-				&context->res_ctx, pipes);
++				context, pipes);
+ 		else
+ 			pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
+-				&context->res_ctx, pipes);
++				context, pipes);
+ 	}
+ 
+ 	*out_pipe_cnt = pipe_cnt;
+@@ -1628,10 +1628,11 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx)
+ }
+ 
+ static int dcn21_populate_dml_pipes_from_context(
+-		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
++		struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
+ {
+-	uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, res_ctx, pipes);
++	uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes);
+ 	int i;
++	struct resource_context *res_ctx = &context->res_ctx;
+ 
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index fc9decc0a8fc..67efc8094ae7 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -105,7 +105,7 @@ struct resource_funcs {
+ 
+ 	int (*populate_dml_pipes)(
+ 		struct dc *dc,
+-		struct resource_context *res_ctx,
++		struct dc_state *context,
+ 		display_e2e_pipe_params_st *pipes);
+ 
+ 	enum dc_status (*validate_global)(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4480-drm-amd-display-Add-DMUB-service-function-check-if-h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4480-drm-amd-display-Add-DMUB-service-function-check-if-h.patch
new file mode 100644
index 00000000..491b8909
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4480-drm-amd-display-Add-DMUB-service-function-check-if-h.patch
@@ -0,0 +1,123 @@
+From c5f567be2f430aa3e888240f0fab5b90fac832bf Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 29 Oct 2019 14:23:55 -0400
+Subject: [PATCH 4480/4736] drm/amd/display: Add DMUB service function check if
+ hw initialized
+
+[Why]
+We want to avoid reprogramming the cache window when possible.
+
+We don't need to worry about it for S3 but we *do* need to worry about
+it for S4 resume.
+
+DM can check whether hardware should be reinitialized or store software
+state when going to S4 to know whether we need to reprogram hardware.
+
+[How]
+Add helpers to the DMUB service to check hardware initialization state.
+
+DM will hook it up later.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h   | 11 +++++++++++
+ drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c |  5 +++++
+ drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h |  2 ++
+ drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c   | 14 ++++++++++++++
+ 4 files changed, 32 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+index aa8f0396616d..76e80138303b 100644
+--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+@@ -252,6 +252,8 @@ struct dmub_srv_hw_funcs {
+ 
+ 	bool (*is_supported)(struct dmub_srv *dmub);
+ 
++	bool (*is_hw_init)(struct dmub_srv *dmub);
++
+ 	bool (*is_phy_init)(struct dmub_srv *dmub);
+ 
+ 	bool (*is_auto_load_done)(struct dmub_srv *dmub);
+@@ -380,6 +382,15 @@ enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub,
+ enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
+ 					 bool *is_supported);
+ 
++/**
++ * dmub_srv_is_hw_init() - returns hardware init state
++ *
++ * Return:
++ *   DMUB_STATUS_OK - success
++ *   DMUB_STATUS_INVALID - unspecified error
++ */
++enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init);
++
+ /**
+  * dmub_srv_hw_init() - initializes the underlying DMUB hardware
+  * @dmub: the dmub service
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+index 236a4156bbe1..89fd27758dd5 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+@@ -122,6 +122,11 @@ void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
+ 	REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
+ }
+ 
++bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub)
++{
++	return REG_READ(DMCUB_REGION3_CW2_BASE_ADDRESS) != 0;
++}
++
+ bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
+ {
+ 	uint32_t supported = 0;
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+index 41269da40363..e1ba748ca594 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+@@ -55,6 +55,8 @@ uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub);
+ 
+ void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
+ 
++bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub);
++
+ bool dmub_dcn20_is_supported(struct dmub_srv *dmub);
+ 
+ bool dmub_dcn20_is_phy_init(struct dmub_srv *dmub);
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+index 229eab7277d1..2d63ae80bda9 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+@@ -76,6 +76,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
+ 		funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr;
+ 		funcs->is_supported = dmub_dcn20_is_supported;
+ 		funcs->is_phy_init = dmub_dcn20_is_phy_init;
++		funcs->is_hw_init = dmub_dcn20_is_hw_init;
+ 
+ 		if (asic == DMUB_ASIC_DCN21) {
+ 			funcs->backdoor_load = dmub_dcn21_backdoor_load;
+@@ -234,6 +235,19 @@ enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
+ 	return DMUB_STATUS_OK;
+ }
+ 
++enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init)
++{
++	*is_hw_init = false;
++
++	if (!dmub->sw_init)
++		return DMUB_STATUS_INVALID;
++
++	if (dmub->hw_funcs.is_hw_init)
++		*is_hw_init = dmub->hw_funcs.is_hw_init(dmub);
++
++	return DMUB_STATUS_OK;
++}
++
+ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
+ 				  const struct dmub_srv_hw_params *params)
+ {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4481-drm-amd-display-Add-DMUB-param-to-load-inst-const-fr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4481-drm-amd-display-Add-DMUB-param-to-load-inst-const-fr.patch
new file mode 100644
index 00000000..12d5f350
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4481-drm-amd-display-Add-DMUB-param-to-load-inst-const-fr.patch
@@ -0,0 +1,57 @@
+From 8ed5f2e4b245c014046beb1f7e978dbabe6c855b Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Wed, 30 Oct 2019 09:02:39 -0400
+Subject: [PATCH 4481/4736] drm/amd/display: Add DMUB param to load inst const
+ from driver
+
+[Why]
+By default we shouldn't be trying to write secure registers during
+DMUB hardware init.
+
+[How]
+Add a parameter to control whether we put the DMCUB into secure reset
+and attempt to load CW0/CW1.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h | 2 ++
+ drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 2 +-
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+index 76e80138303b..046885940dba 100644
+--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+@@ -281,12 +281,14 @@ struct dmub_srv_create_params {
+  * @fb_base: base of the framebuffer aperture
+  * @fb_offset: offset of the framebuffer aperture
+  * @psp_version: psp version to pass for DMCU init
++ * @load_inst_const: true if DMUB should load inst const fw
+  */
+ struct dmub_srv_hw_params {
+ 	struct dmub_fb *fb[DMUB_WINDOW_TOTAL];
+ 	uint64_t fb_base;
+ 	uint64_t fb_offset;
+ 	uint32_t psp_version;
++	bool load_inst_const;
+ };
+ 
+ /**
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+index 2d63ae80bda9..0dd32edbbcb3 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+@@ -278,7 +278,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
+ 		cw1.region.base = DMUB_CW1_BASE;
+ 		cw1.region.top = cw1.region.base + stack_fb->size - 1;
+ 
+-		if (dmub->hw_funcs.backdoor_load)
++		if (params->load_inst_const && dmub->hw_funcs.backdoor_load)
+ 			dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
+ 	}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4482-drm-amd-display-Add-debugfs-initalization-on-mst-con.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4482-drm-amd-display-Add-debugfs-initalization-on-mst-con.patch
new file mode 100644
index 00000000..02b4d572
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4482-drm-amd-display-Add-debugfs-initalization-on-mst-con.patch
@@ -0,0 +1,66 @@
+From 617e750370536c817d600bc504ed48f82ef95b6c Mon Sep 17 00:00:00 2001
+From: Mikita Lipski <mikita.lipski@amd.com>
+Date: Tue, 29 Oct 2019 11:43:05 -0400
+Subject: [PATCH 4482/4736] drm/amd/display: Add debugfs initalization on mst
+ connectors
+
+[why]
+We were missing debugfs files on MST connectors as the files
+weren't initialized.
+
+[how]
+Move connector debugfs initialization into connoctor's
+init helper function so it will be called by both SST and MST
+connectors. Also move connector registration so it will be
+registered before we create the entries.
+
+Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 ++++++++-------
+ 1 file changed, 8 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index ec9fac7d4559..54a2b65dfcc1 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -5480,6 +5480,12 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
+ 			drm_connector_attach_content_protection_property(&aconnector->base, false);
+ #endif
+ 	}
++
++#if defined(CONFIG_DEBUG_FS)
++	connector_debugfs_init(aconnector);
++	aconnector->debugfs_dpcd_address = 0;
++	aconnector->debugfs_dpcd_size = 0;
++#endif
+ }
+ 
+ static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
+@@ -5602,6 +5608,8 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
+ 			&aconnector->base,
+ 			&amdgpu_dm_connector_helper_funcs);
+ 
++	drm_connector_register(&aconnector->base);
++
+ 	amdgpu_dm_connector_init_helper(
+ 		dm,
+ 		aconnector,
+@@ -5612,13 +5620,6 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
+ 	drm_connector_attach_encoder(
+ 		&aconnector->base, &aencoder->base);
+ 
+-	drm_connector_register(&aconnector->base);
+-#if defined(CONFIG_DEBUG_FS)
+-	connector_debugfs_init(aconnector);
+-	aconnector->debugfs_dpcd_address = 0;
+-	aconnector->debugfs_dpcd_size = 0;
+-#endif
+-
+ 	if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
+ 		|| connector_type == DRM_MODE_CONNECTOR_eDP)
+ 		amdgpu_dm_initialize_dp_connector(dm, aconnector);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4483-drm-amd-display-Connect-DIG-FE-to-its-BE-before-link.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4483-drm-amd-display-Connect-DIG-FE-to-its-BE-before-link.patch
new file mode 100644
index 00000000..59dc9fe1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4483-drm-amd-display-Connect-DIG-FE-to-its-BE-before-link.patch
@@ -0,0 +1,35 @@
+From d9e8bbbc6fffd210c026fa011ed1b556d00eaea0 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Tue, 29 Oct 2019 15:49:28 -0400
+Subject: [PATCH 4483/4736] drm/amd/display: Connect DIG FE to its BE before
+ link training starts
+
+[why]
+In SST mode no idle pattern will be generated after link training if
+DIG FE is not connected to DIG BE.
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 7fab34ce0591..58b63612c926 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -1546,6 +1546,10 @@ static enum dc_status enable_link_dp(
+ 	panel_mode = dp_get_panel_mode(link);
+ 	dp_set_panel_mode(link, panel_mode);
+ 
++	/* We need to do this before the link training to ensure the idle pattern in SST
++	 * mode will be sent right after the link training */
++	link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
++						    pipe_ctx->stream_res.stream_enc->id, true);
+ 	skip_video_pattern = true;
+ 
+ 	if (link_settings.link_rate == LINK_RATE_LOW)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4484-drm-amd-display-Clean-up-some-code-with-unused-regis.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4484-drm-amd-display-Clean-up-some-code-with-unused-regis.patch
new file mode 100644
index 00000000..fdbdf164
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4484-drm-amd-display-Clean-up-some-code-with-unused-regis.patch
@@ -0,0 +1,36 @@
+From 91b762a11983428a235016d132e59d4812c44875 Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Mon, 28 Oct 2019 11:45:14 -0400
+Subject: [PATCH 4484/4736] drm/amd/display: Clean up some code with unused
+ registers
+
+[Why]
+Unused register in the code
+
+[How]
+Remove unused register
+
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+index 32d145a0d6fc..a0d1c3b811a9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+@@ -800,8 +800,7 @@ struct dce_hwseq_registers {
+ 	type D2VGA_MODE_ENABLE; \
+ 	type D3VGA_MODE_ENABLE; \
+ 	type D4VGA_MODE_ENABLE; \
+-	type AZALIA_AUDIO_DTO_MODULE;\
+-	type HPO_HDMISTREAMCLK_GATE_DIS;
++	type AZALIA_AUDIO_DTO_MODULE;
+ 
+ struct dce_hwseq_shift {
+ 	HWSEQ_REG_FIELD_LIST(uint8_t)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4485-drm-amd-display-revert-change-causing-DTN-hang-for-R.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4485-drm-amd-display-revert-change-causing-DTN-hang-for-R.patch
new file mode 100644
index 00000000..1138441e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4485-drm-amd-display-revert-change-causing-DTN-hang-for-R.patch
@@ -0,0 +1,73 @@
+From 7db83a80e428a864b3d117da7d28c901a0703574 Mon Sep 17 00:00:00 2001
+From: Samson Tam <Samson.Tam@amd.com>
+Date: Thu, 31 Oct 2019 15:27:28 -0400
+Subject: [PATCH 4485/4736] drm/amd/display: revert change causing DTN hang for
+ RV
+
+[Why]
+Hanging on RV for DTN driver verifier
+
+[How]
+Roll back change and investigate further
+
+Signed-off-by: Samson Tam <Samson.Tam@amd.com>
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 27 ------------------------
+ 1 file changed, 27 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 7a2cdf21ca34..9e600d3e2fd8 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1764,37 +1764,12 @@ static struct dc_stream_status *stream_get_status(
+ 
+ static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
+ 
+-static void validate_dcc_with_meta_address(
+-	struct dc_plane_dcc_param *dcc,
+-	struct dc_plane_address *address)
+-{
+-	if ((address->grph.meta_addr.quad_part == 0) &&
+-		dcc->enable) {
+-		ASSERT(!dcc->enable);
+-		dcc->enable = false;
+-	} else if ((address->grph.meta_addr.quad_part != 0) &&
+-		!dcc->enable)
+-		dcc->enable = true;
+-
+-	if (address->type != PLN_ADDR_TYPE_GRAPHICS) {
+-		if ((address->grph_stereo.right_meta_addr.quad_part == 0) &&
+-			dcc->enable) {
+-			ASSERT(!dcc->enable);
+-			dcc->enable = false;
+-		} else if ((address->grph_stereo.right_meta_addr.quad_part != 0) &&
+-			!dcc->enable)
+-			dcc->enable = true;
+-	}
+-}
+-
+ static void copy_surface_update_to_plane(
+ 		struct dc_plane_state *surface,
+ 		struct dc_surface_update *srf_update)
+ {
+ 	if (srf_update->flip_addr) {
+ 		surface->address = srf_update->flip_addr->address;
+-		validate_dcc_with_meta_address(&surface->dcc, &surface->address);
+-
+ 		surface->flip_immediate =
+ 			srf_update->flip_addr->flip_immediate;
+ 		surface->time.time_elapsed_in_us[surface->time.index] =
+@@ -1843,8 +1818,6 @@ static void copy_surface_update_to_plane(
+ 				srf_update->plane_info->global_alpha_value;
+ 		surface->dcc =
+ 				srf_update->plane_info->dcc;
+-		validate_dcc_with_meta_address(&surface->dcc, &surface->address);
+-
+ 		surface->sdr_white_level =
+ 				srf_update->plane_info->sdr_white_level;
+ 		surface->layer_index =
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4486-drm-amd-display-Fix-debugfs-on-MST-connectors.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4486-drm-amd-display-Fix-debugfs-on-MST-connectors.patch
new file mode 100644
index 00000000..288726c1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4486-drm-amd-display-Fix-debugfs-on-MST-connectors.patch
@@ -0,0 +1,96 @@
+From 298e853d52b57d8e2e929adac65ed27a6b184e49 Mon Sep 17 00:00:00 2001
+From: Mikita Lipski <mikita.lipski@amd.com>
+Date: Thu, 31 Oct 2019 16:09:01 -0400
+Subject: [PATCH 4486/4736] drm/amd/display: Fix debugfs on MST connectors
+
+[why]
+Previous patch allowed to initialize debugfs entries on both MST
+and SST connectors, but MST connectors get registered much later
+which exposed an issue of debugfs entries being initialized in the
+same folder.
+
+[how]
+Return SST debugfs entries' initialization back to where it was.
+For MST connectors we should initialize debugfs entries in connector
+register function after the connector is registered.
+
+Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 +++++++--------
+ .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c   | 10 +++++++++-
+ 2 files changed, 16 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 54a2b65dfcc1..ec9fac7d4559 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -5480,12 +5480,6 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
+ 			drm_connector_attach_content_protection_property(&aconnector->base, false);
+ #endif
+ 	}
+-
+-#if defined(CONFIG_DEBUG_FS)
+-	connector_debugfs_init(aconnector);
+-	aconnector->debugfs_dpcd_address = 0;
+-	aconnector->debugfs_dpcd_size = 0;
+-#endif
+ }
+ 
+ static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
+@@ -5608,8 +5602,6 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
+ 			&aconnector->base,
+ 			&amdgpu_dm_connector_helper_funcs);
+ 
+-	drm_connector_register(&aconnector->base);
+-
+ 	amdgpu_dm_connector_init_helper(
+ 		dm,
+ 		aconnector,
+@@ -5620,6 +5612,13 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
+ 	drm_connector_attach_encoder(
+ 		&aconnector->base, &aencoder->base);
+ 
++	drm_connector_register(&aconnector->base);
++#if defined(CONFIG_DEBUG_FS)
++	connector_debugfs_init(aconnector);
++	aconnector->debugfs_dpcd_address = 0;
++	aconnector->debugfs_dpcd_size = 0;
++#endif
++
+ 	if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
+ 		|| connector_type == DRM_MODE_CONNECTOR_eDP)
+ 		amdgpu_dm_initialize_dp_connector(dm, aconnector);
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+index c765fcbd1386..74cadc8b4801 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+@@ -36,7 +36,9 @@
+ #include "dc_link_ddc.h"
+ 
+ #include "i2caux_interface.h"
+-
++#if defined(CONFIG_DEBUG_FS)
++#include "amdgpu_dm_debugfs.h"
++#endif
+ /* #define TRACE_DPCD */
+ 
+ #ifdef TRACE_DPCD
+@@ -161,6 +163,12 @@ amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
+ 		to_amdgpu_dm_connector(connector);
+ 	struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
+ 
++#if defined(CONFIG_DEBUG_FS)
++	connector_debugfs_init(amdgpu_dm_connector);
++	amdgpu_dm_connector->debugfs_dpcd_address = 0;
++	amdgpu_dm_connector->debugfs_dpcd_size = 0;
++#endif
++
+ 	return drm_dp_mst_connector_late_register(connector, port);
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4487-drm-amd-display-cleanup-of-construct-and-destruct-fu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4487-drm-amd-display-cleanup-of-construct-and-destruct-fu.patch
new file mode 100644
index 00000000..8fbd65ce
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4487-drm-amd-display-cleanup-of-construct-and-destruct-fu.patch
@@ -0,0 +1,1071 @@
+From a476c483cb70b9fb28ee2336785d225a0f920330 Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Thu, 31 Oct 2019 21:39:39 -0400
+Subject: [PATCH 4487/4736] drm/amd/display: cleanup of construct and destruct
+ funcs
+
+[Why]
+Too many construct functions which makes searching
+difficult, especially on some debuggers.
+
+[How]
+Append all construct and destruct functions with dcn
+number and object type to make each construct function
+name unique
+
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ .../gpu/drm/amd/display/dc/bios/bios_parser.c |  4 +--
+ .../drm/amd/display/dc/bios/bios_parser2.c    |  8 ++---
+ drivers/gpu/drm/amd/display/dc/core/dc.c      | 10 +++---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c |  8 ++---
+ .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |  8 ++---
+ drivers/gpu/drm/amd/display/dc/core/dc_sink.c |  8 ++---
+ .../gpu/drm/amd/display/dc/core/dc_stream.c   |  8 ++---
+ .../gpu/drm/amd/display/dc/core/dc_surface.c  |  8 ++---
+ .../amd/display/dc/dce100/dce100_resource.c   | 10 +++---
+ .../amd/display/dc/dce110/dce110_resource.c   | 10 +++---
+ .../amd/display/dc/dce112/dce112_resource.c   | 10 +++---
+ .../amd/display/dc/dce120/dce120_resource.c   | 10 +++---
+ .../drm/amd/display/dc/dce80/dce80_resource.c | 10 +++---
+ .../drm/amd/display/dc/dcn10/dcn10_resource.c | 10 +++---
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 10 +++---
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 10 +++---
+ drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c  | 12 +++----
+ .../gpu/drm/amd/display/dc/gpio/hw_generic.c  | 23 ++++---------
+ drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c  | 32 +++++--------------
+ .../dc/irq/dce110/irq_service_dce110.c        |  4 +--
+ .../dc/irq/dce120/irq_service_dce120.c        |  4 +--
+ .../display/dc/irq/dce80/irq_service_dce80.c  |  4 +--
+ .../display/dc/irq/dcn10/irq_service_dcn10.c  |  4 +--
+ .../display/dc/irq/dcn20/irq_service_dcn20.c  |  4 +--
+ .../display/dc/irq/dcn21/irq_service_dcn21.c  |  4 +--
+ 25 files changed, 104 insertions(+), 129 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+index 0d4993691199..714a862e7321 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+@@ -109,7 +109,7 @@ struct dc_bios *bios_parser_create(
+ 	return NULL;
+ }
+ 
+-static void destruct(struct bios_parser *bp)
++static void bios_parser_destruct(struct bios_parser *bp)
+ {
+ 	kfree(bp->base.bios_local_image);
+ 	kfree(bp->base.integrated_info);
+@@ -124,7 +124,7 @@ static void bios_parser_destroy(struct dc_bios **dcb)
+ 		return;
+ 	}
+ 
+-	destruct(bp);
++	bios_parser_destruct(bp);
+ 
+ 	kfree(bp);
+ 	*dcb = NULL;
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index 884b07774f6d..03a5e82a7b2d 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -109,7 +109,7 @@ static struct atom_encoder_caps_record *get_encoder_cap_record(
+ 
+ #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
+ 
+-static void destruct(struct bios_parser *bp)
++static void bios_parser2_destruct(struct bios_parser *bp)
+ {
+ 	kfree(bp->base.bios_local_image);
+ 	kfree(bp->base.integrated_info);
+@@ -124,7 +124,7 @@ static void firmware_parser_destroy(struct dc_bios **dcb)
+ 		return;
+ 	}
+ 
+-	destruct(bp);
++	bios_parser2_destruct(bp);
+ 
+ 	kfree(bp);
+ 	*dcb = NULL;
+@@ -1925,7 +1925,7 @@ static const struct dc_vbios_funcs vbios_funcs = {
+ 	.get_board_layout_info = bios_get_board_layout_info,
+ };
+ 
+-static bool bios_parser_construct(
++static bool bios_parser2_construct(
+ 	struct bios_parser *bp,
+ 	struct bp_init_data *init,
+ 	enum dce_version dce_version)
+@@ -2018,7 +2018,7 @@ struct dc_bios *firmware_parser_create(
+ 	if (!bp)
+ 		return NULL;
+ 
+-	if (bios_parser_construct(bp, init, dce_version))
++	if (bios_parser2_construct(bp, init, dce_version))
+ 		return &bp->base;
+ 
+ 	kfree(bp);
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 9e600d3e2fd8..7539c3accd59 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -534,7 +534,7 @@ void dc_stream_set_static_screen_events(struct dc *dc,
+ 	dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
+ }
+ 
+-static void destruct(struct dc *dc)
++static void dc_destruct(struct dc *dc)
+ {
+ 	if (dc->current_state) {
+ 		dc_release_state(dc->current_state);
+@@ -582,7 +582,7 @@ static void destruct(struct dc *dc)
+ #endif
+ }
+ 
+-static bool construct(struct dc *dc,
++static bool dc_construct(struct dc *dc,
+ 		const struct dc_init_data *init_params)
+ {
+ 	struct dc_context *dc_ctx;
+@@ -734,7 +734,7 @@ static bool construct(struct dc *dc,
+ 
+ fail:
+ 
+-	destruct(dc);
++	dc_destruct(dc);
+ 	return false;
+ }
+ 
+@@ -806,7 +806,7 @@ struct dc *dc_create(const struct dc_init_data *init_params)
+ 	if (NULL == dc)
+ 		goto alloc_fail;
+ 
+-	if (false == construct(dc, init_params))
++	if (false == dc_construct(dc, init_params))
+ 		goto construct_fail;
+ 
+ 	full_pipe_count = dc->res_pool->pipe_count;
+@@ -863,7 +863,7 @@ void dc_deinit_callbacks(struct dc *dc)
+ 
+ void dc_destroy(struct dc **dc)
+ {
+-	destruct(*dc);
++	dc_destruct(*dc);
+ 	kfree(*dc);
+ 	*dc = NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 58b63612c926..014cb7cf9cba 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -72,7 +72,7 @@ enum {
+ /*******************************************************************************
+  * Private functions
+  ******************************************************************************/
+-static void destruct(struct dc_link *link)
++static void dc_link_destruct(struct dc_link *link)
+ {
+ 	int i;
+ 
+@@ -1242,7 +1242,7 @@ static enum transmitter translate_encoder_to_transmitter(
+ 	}
+ }
+ 
+-static bool construct(
++static bool dc_link_construct(
+ 	struct dc_link *link,
+ 	const struct link_init_data *init_params)
+ {
+@@ -1444,7 +1444,7 @@ struct dc_link *link_create(const struct link_init_data *init_params)
+ 	if (NULL == link)
+ 		goto alloc_fail;
+ 
+-	if (false == construct(link, init_params))
++	if (false == dc_link_construct(link, init_params))
+ 		goto construct_fail;
+ 
+ 	return link;
+@@ -1458,7 +1458,7 @@ struct dc_link *link_create(const struct link_init_data *init_params)
+ 
+ void link_destroy(struct dc_link **link)
+ {
+-	destruct(*link);
++	dc_link_destruct(*link);
+ 	kfree(*link);
+ 	*link = NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+index 68c0cf85deb7..60d3c164495d 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+@@ -185,7 +185,7 @@ void dal_ddc_i2c_payloads_add(
+ 
+ }
+ 
+-static void construct(
++static void ddc_service_construct(
+ 	struct ddc_service *ddc_service,
+ 	struct ddc_service_init_data *init_data)
+ {
+@@ -237,11 +237,11 @@ struct ddc_service *dal_ddc_service_create(
+ 	if (!ddc_service)
+ 		return NULL;
+ 
+-	construct(ddc_service, init_data);
++	ddc_service_construct(ddc_service, init_data);
+ 	return ddc_service;
+ }
+ 
+-static void destruct(struct ddc_service *ddc)
++static void ddc_service_destruct(struct ddc_service *ddc)
+ {
+ 	if (ddc->ddc_pin)
+ 		dal_gpio_destroy_ddc(&ddc->ddc_pin);
+@@ -253,7 +253,7 @@ void dal_ddc_service_destroy(struct ddc_service **ddc)
+ 		BREAK_TO_DEBUGGER();
+ 		return;
+ 	}
+-	destruct(*ddc);
++	ddc_service_destruct(*ddc);
+ 	kfree(*ddc);
+ 	*ddc = NULL;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
+index 9971b515c3eb..a3fa001ef585 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
+@@ -31,7 +31,7 @@
+  * Private functions
+  ******************************************************************************/
+ 
+-static void destruct(struct dc_sink *sink)
++static void dc_sink_destruct(struct dc_sink *sink)
+ {
+ 	if (sink->dc_container_id) {
+ 		kfree(sink->dc_container_id);
+@@ -39,7 +39,7 @@ static void destruct(struct dc_sink *sink)
+ 	}
+ }
+ 
+-static bool construct(struct dc_sink *sink, const struct dc_sink_init_data *init_params)
++static bool dc_sink_construct(struct dc_sink *sink, const struct dc_sink_init_data *init_params)
+ {
+ 
+ 	struct dc_link *link = init_params->link;
+@@ -73,7 +73,7 @@ void dc_sink_retain(struct dc_sink *sink)
+ static void dc_sink_free(struct kref *kref)
+ {
+ 	struct dc_sink *sink = container_of(kref, struct dc_sink, refcount);
+-	destruct(sink);
++	dc_sink_destruct(sink);
+ 	kfree(sink);
+ }
+ 
+@@ -89,7 +89,7 @@ struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params)
+ 	if (NULL == sink)
+ 		goto alloc_fail;
+ 
+-	if (false == construct(sink, init_params))
++	if (false == dc_sink_construct(sink, init_params))
+ 		goto construct_fail;
+ 
+ 	kref_init(&sink->refcount);
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+index 2e03a1120bee..ae7cbb6d7847 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+@@ -55,7 +55,7 @@ void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink)
+ 	}
+ }
+ 
+-static void construct(struct dc_stream_state *stream,
++static void dc_stream_construct(struct dc_stream_state *stream,
+ 	struct dc_sink *dc_sink_data)
+ {
+ 	uint32_t i = 0;
+@@ -126,7 +126,7 @@ static void construct(struct dc_stream_state *stream,
+ 	stream->ctx->dc_stream_id_count++;
+ }
+ 
+-static void destruct(struct dc_stream_state *stream)
++static void dc_stream_destruct(struct dc_stream_state *stream)
+ {
+ 	dc_sink_release(stream->sink);
+ 	if (stream->out_transfer_func != NULL) {
+@@ -144,7 +144,7 @@ static void dc_stream_free(struct kref *kref)
+ {
+ 	struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount);
+ 
+-	destruct(stream);
++	dc_stream_destruct(stream);
+ 	kfree(stream);
+ }
+ 
+@@ -167,7 +167,7 @@ struct dc_stream_state *dc_create_stream_for_sink(
+ 	if (stream == NULL)
+ 		return NULL;
+ 
+-	construct(stream, sink);
++	dc_stream_construct(stream, sink);
+ 
+ 	kref_init(&stream->refcount);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+index 9184f877f537..d534ac166512 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+@@ -35,7 +35,7 @@
+ /*******************************************************************************
+  * Private functions
+  ******************************************************************************/
+-static void construct(struct dc_context *ctx, struct dc_plane_state *plane_state)
++static void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *plane_state)
+ {
+ 	plane_state->ctx = ctx;
+ 
+@@ -68,7 +68,7 @@ static void construct(struct dc_context *ctx, struct dc_plane_state *plane_state
+ #endif
+ }
+ 
+-static void destruct(struct dc_plane_state *plane_state)
++static void dc_plane_destruct(struct dc_plane_state *plane_state)
+ {
+ 	if (plane_state->gamma_correction != NULL) {
+ 		dc_gamma_release(&plane_state->gamma_correction);
+@@ -119,7 +119,7 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc)
+ 		return NULL;
+ 
+ 	kref_init(&plane_state->refcount);
+-	construct(core_dc->ctx, plane_state);
++	dc_plane_construct(core_dc->ctx, plane_state);
+ 
+ 	return plane_state;
+ }
+@@ -189,7 +189,7 @@ void dc_plane_state_retain(struct dc_plane_state *plane_state)
+ static void dc_plane_state_free(struct kref *kref)
+ {
+ 	struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount);
+-	destruct(plane_state);
++	dc_plane_destruct(plane_state);
+ 	kvfree(plane_state);
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+index 8ec9b4639fe7..2a5ad50ba454 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+@@ -722,7 +722,7 @@ void dce100_clock_source_destroy(struct clock_source **clk_src)
+ 	*clk_src = NULL;
+ }
+ 
+-static void destruct(struct dce110_resource_pool *pool)
++static void dce100_resource_destruct(struct dce110_resource_pool *pool)
+ {
+ 	unsigned int i;
+ 
+@@ -882,7 +882,7 @@ static void dce100_destroy_resource_pool(struct resource_pool **pool)
+ {
+ 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
+ 
+-	destruct(dce110_pool);
++	dce100_resource_destruct(dce110_pool);
+ 	kfree(dce110_pool);
+ 	*pool = NULL;
+ }
+@@ -947,7 +947,7 @@ static const struct resource_funcs dce100_res_pool_funcs = {
+ 	.find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
+ };
+ 
+-static bool construct(
++static bool dce100_resource_construct(
+ 	uint8_t num_virtual_links,
+ 	struct dc  *dc,
+ 	struct dce110_resource_pool *pool)
+@@ -1119,7 +1119,7 @@ static bool construct(
+ 	return true;
+ 
+ res_create_fail:
+-	destruct(pool);
++	dce100_resource_destruct(pool);
+ 
+ 	return false;
+ }
+@@ -1134,7 +1134,7 @@ struct resource_pool *dce100_create_resource_pool(
+ 	if (!pool)
+ 		return NULL;
+ 
+-	if (construct(num_virtual_links, dc, pool))
++	if (dce100_resource_construct(num_virtual_links, dc, pool))
+ 		return &pool->base;
+ 
+ 	kfree(pool);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index 377fa9193ce1..762f97b48f0f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -780,7 +780,7 @@ void dce110_clock_source_destroy(struct clock_source **clk_src)
+ 	*clk_src = NULL;
+ }
+ 
+-static void destruct(struct dce110_resource_pool *pool)
++static void dce110_resource_destruct(struct dce110_resource_pool *pool)
+ {
+ 	unsigned int i;
+ 
+@@ -1159,7 +1159,7 @@ static void dce110_destroy_resource_pool(struct resource_pool **pool)
+ {
+ 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
+ 
+-	destruct(dce110_pool);
++	dce110_resource_destruct(dce110_pool);
+ 	kfree(dce110_pool);
+ 	*pool = NULL;
+ }
+@@ -1311,7 +1311,7 @@ const struct resource_caps *dce110_resource_cap(
+ 		return &carrizo_resource_cap;
+ }
+ 
+-static bool construct(
++static bool dce110_resource_construct(
+ 	uint8_t num_virtual_links,
+ 	struct dc *dc,
+ 	struct dce110_resource_pool *pool,
+@@ -1490,7 +1490,7 @@ static bool construct(
+ 	return true;
+ 
+ res_create_fail:
+-	destruct(pool);
++	dce110_resource_destruct(pool);
+ 	return false;
+ }
+ 
+@@ -1505,7 +1505,7 @@ struct resource_pool *dce110_create_resource_pool(
+ 	if (!pool)
+ 		return NULL;
+ 
+-	if (construct(num_virtual_links, dc, pool, asic_id))
++	if (dce110_resource_construct(num_virtual_links, dc, pool, asic_id))
+ 		return &pool->base;
+ 
+ 	kfree(pool);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+index 5bde6ac2fa7e..b2f127bd85ee 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+@@ -742,7 +742,7 @@ void dce112_clock_source_destroy(struct clock_source **clk_src)
+ 	*clk_src = NULL;
+ }
+ 
+-static void destruct(struct dce110_resource_pool *pool)
++static void dce112_resource_destruct(struct dce110_resource_pool *pool)
+ {
+ 	unsigned int i;
+ 
+@@ -1011,7 +1011,7 @@ static void dce112_destroy_resource_pool(struct resource_pool **pool)
+ {
+ 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
+ 
+-	destruct(dce110_pool);
++	dce112_resource_destruct(dce110_pool);
+ 	kfree(dce110_pool);
+ 	*pool = NULL;
+ }
+@@ -1184,7 +1184,7 @@ const struct resource_caps *dce112_resource_cap(
+ 		return &polaris_10_resource_cap;
+ }
+ 
+-static bool construct(
++static bool dce112_resource_construct(
+ 	uint8_t num_virtual_links,
+ 	struct dc *dc,
+ 	struct dce110_resource_pool *pool)
+@@ -1370,7 +1370,7 @@ static bool construct(
+ 	return true;
+ 
+ res_create_fail:
+-	destruct(pool);
++	dce112_resource_destruct(pool);
+ 	return false;
+ }
+ 
+@@ -1384,7 +1384,7 @@ struct resource_pool *dce112_create_resource_pool(
+ 	if (!pool)
+ 		return NULL;
+ 
+-	if (construct(num_virtual_links, dc, pool))
++	if (dce112_resource_construct(num_virtual_links, dc, pool))
+ 		return &pool->base;
+ 
+ 	kfree(pool);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index c982fd336cae..e9157583817f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -585,7 +585,7 @@ static void dce120_transform_destroy(struct transform **xfm)
+ 	*xfm = NULL;
+ }
+ 
+-static void destruct(struct dce110_resource_pool *pool)
++static void dce120_resource_destruct(struct dce110_resource_pool *pool)
+ {
+ 	unsigned int i;
+ 
+@@ -870,7 +870,7 @@ static void dce120_destroy_resource_pool(struct resource_pool **pool)
+ {
+ 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
+ 
+-	destruct(dce110_pool);
++	dce120_resource_destruct(dce110_pool);
+ 	kfree(dce110_pool);
+ 	*pool = NULL;
+ }
+@@ -1022,7 +1022,7 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx)
+ 	return value;
+ }
+ 
+-static bool construct(
++static bool dce120_resource_construct(
+ 	uint8_t num_virtual_links,
+ 	struct dc *dc,
+ 	struct dce110_resource_pool *pool)
+@@ -1235,7 +1235,7 @@ static bool construct(
+ clk_src_create_fail:
+ res_create_fail:
+ 
+-	destruct(pool);
++	dce120_resource_destruct(pool);
+ 
+ 	return false;
+ }
+@@ -1250,7 +1250,7 @@ struct resource_pool *dce120_create_resource_pool(
+ 	if (!pool)
+ 		return NULL;
+ 
+-	if (construct(num_virtual_links, dc, pool))
++	if (dce120_resource_construct(num_virtual_links, dc, pool))
+ 		return &pool->base;
+ 
+ 	kfree(pool);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+index 6a9efa3bb93e..fd7acdb561b3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -771,7 +771,7 @@ static struct input_pixel_processor *dce80_ipp_create(
+ 	return &ipp->base;
+ }
+ 
+-static void destruct(struct dce110_resource_pool *pool)
++static void dce80_resource_destruct(struct dce110_resource_pool *pool)
+ {
+ 	unsigned int i;
+ 
+@@ -899,7 +899,7 @@ static void dce80_destroy_resource_pool(struct resource_pool **pool)
+ {
+ 	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
+ 
+-	destruct(dce110_pool);
++	dce80_resource_destruct(dce110_pool);
+ 	kfree(dce110_pool);
+ 	*pool = NULL;
+ }
+@@ -1091,7 +1091,7 @@ static bool dce80_construct(
+ 	return true;
+ 
+ res_create_fail:
+-	destruct(pool);
++	dce80_resource_destruct(pool);
+ 	return false;
+ }
+ 
+@@ -1288,7 +1288,7 @@ static bool dce81_construct(
+ 	return true;
+ 
+ res_create_fail:
+-	destruct(pool);
++	dce80_resource_destruct(pool);
+ 	return false;
+ }
+ 
+@@ -1481,7 +1481,7 @@ static bool dce83_construct(
+ 	return true;
+ 
+ res_create_fail:
+-	destruct(pool);
++	dce80_resource_destruct(pool);
+ 	return false;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index a38c83c6aa5c..c4129e21e643 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -917,7 +917,7 @@ static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx)
+ 	return pp_smu;
+ }
+ 
+-static void destruct(struct dcn10_resource_pool *pool)
++static void dcn10_resource_destruct(struct dcn10_resource_pool *pool)
+ {
+ 	unsigned int i;
+ 
+@@ -1164,7 +1164,7 @@ static void dcn10_destroy_resource_pool(struct resource_pool **pool)
+ {
+ 	struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
+ 
+-	destruct(dcn10_pool);
++	dcn10_resource_destruct(dcn10_pool);
+ 	kfree(dcn10_pool);
+ 	*pool = NULL;
+ }
+@@ -1303,7 +1303,7 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx)
+ 	return value;
+ }
+ 
+-static bool construct(
++static bool dcn10_resource_construct(
+ 	uint8_t num_virtual_links,
+ 	struct dc *dc,
+ 	struct dcn10_resource_pool *pool)
+@@ -1590,7 +1590,7 @@ static bool construct(
+ 
+ fail:
+ 
+-	destruct(pool);
++	dcn10_resource_destruct(pool);
+ 
+ 	return false;
+ }
+@@ -1605,7 +1605,7 @@ struct resource_pool *dcn10_create_resource_pool(
+ 	if (!pool)
+ 		return NULL;
+ 
+-	if (construct(init_data->num_virtual_links, dc, pool))
++	if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool))
+ 		return &pool->base;
+ 
+ 	kfree(pool);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index d437be449edb..3119714586dd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1236,7 +1236,7 @@ void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
+ 
+ #endif
+ 
+-static void destruct(struct dcn20_resource_pool *pool)
++static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
+ {
+ 	unsigned int i;
+ 
+@@ -2932,7 +2932,7 @@ static void dcn20_destroy_resource_pool(struct resource_pool **pool)
+ {
+ 	struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
+ 
+-	destruct(dcn20_pool);
++	dcn20_resource_destruct(dcn20_pool);
+ 	kfree(dcn20_pool);
+ 	*pool = NULL;
+ }
+@@ -3388,7 +3388,7 @@ static bool init_soc_bounding_box(struct dc *dc,
+ 	return true;
+ }
+ 
+-static bool construct(
++static bool dcn20_resource_construct(
+ 	uint8_t num_virtual_links,
+ 	struct dc *dc,
+ 	struct dcn20_resource_pool *pool)
+@@ -3707,7 +3707,7 @@ static bool construct(
+ 
+ create_fail:
+ 
+-	destruct(pool);
++	dcn20_resource_destruct(pool);
+ 
+ 	return false;
+ }
+@@ -3722,7 +3722,7 @@ struct resource_pool *dcn20_create_resource_pool(
+ 	if (!pool)
+ 		return NULL;
+ 
+-	if (construct(init_data->num_virtual_links, dc, pool))
++	if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
+ 		return &pool->base;
+ 
+ 	BREAK_TO_DEBUGGER();
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index de3ffefbf1f4..9ec73b513488 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -854,7 +854,7 @@ enum dcn20_clk_src_array_id {
+ 	DCN20_CLK_SRC_TOTAL_DCN21
+ };
+ 
+-static void destruct(struct dcn21_resource_pool *pool)
++static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
+ {
+ 	unsigned int i;
+ 
+@@ -1160,7 +1160,7 @@ static void dcn21_destroy_resource_pool(struct resource_pool **pool)
+ {
+ 	struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
+ 
+-	destruct(dcn21_pool);
++	dcn21_resource_destruct(dcn21_pool);
+ 	kfree(dcn21_pool);
+ 	*pool = NULL;
+ }
+@@ -1661,7 +1661,7 @@ static struct resource_funcs dcn21_res_pool_funcs = {
+ 	.update_bw_bounding_box = update_bw_bounding_box
+ };
+ 
+-static bool construct(
++static bool dcn21_resource_construct(
+ 	uint8_t num_virtual_links,
+ 	struct dc *dc,
+ 	struct dcn21_resource_pool *pool)
+@@ -1915,7 +1915,7 @@ static bool construct(
+ 
+ create_fail:
+ 
+-	destruct(pool);
++	dcn21_resource_destruct(pool);
+ 
+ 	return false;
+ }
+@@ -1930,7 +1930,7 @@ struct resource_pool *dcn21_create_resource_pool(
+ 	if (!pool)
+ 		return NULL;
+ 
+-	if (construct(init_data->num_virtual_links, dc, pool))
++	if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
+ 		return &pool->base;
+ 
+ 	BREAK_TO_DEBUGGER();
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
+index e1c84a2f7298..95d1c44a1d47 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
+@@ -45,18 +45,18 @@
+ 
+ struct gpio;
+ 
+-static void destruct(
++static void dal_hw_ddc_destruct(
+ 	struct hw_ddc *pin)
+ {
+ 	dal_hw_gpio_destruct(&pin->base);
+ }
+ 
+-static void destroy(
++static void dal_hw_ddc_destroy(
+ 	struct hw_gpio_pin **ptr)
+ {
+ 	struct hw_ddc *pin = HW_DDC_FROM_BASE(*ptr);
+ 
+-	destruct(pin);
++	dal_hw_ddc_destruct(pin);
+ 
+ 	kfree(pin);
+ 
+@@ -208,7 +208,7 @@ static enum gpio_result set_config(
+ }
+ 
+ static const struct hw_gpio_pin_funcs funcs = {
+-	.destroy = destroy,
++	.destroy = dal_hw_ddc_destroy,
+ 	.open = dal_hw_gpio_open,
+ 	.get_value = dal_hw_gpio_get_value,
+ 	.set_value = dal_hw_gpio_set_value,
+@@ -217,7 +217,7 @@ static const struct hw_gpio_pin_funcs funcs = {
+ 	.close = dal_hw_gpio_close,
+ };
+ 
+-static void construct(
++static void dal_hw_ddc_construct(
+ 	struct hw_ddc *ddc,
+ 	enum gpio_id id,
+ 	uint32_t en,
+@@ -244,7 +244,7 @@ void dal_hw_ddc_init(
+ 		return;
+ 	}
+ 
+-	construct(*hw_ddc, id, en, ctx);
++	dal_hw_ddc_construct(*hw_ddc, id, en, ctx);
+ }
+ 
+ struct hw_gpio_pin *dal_hw_ddc_get_pin(struct gpio *gpio)
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
+index f039c5982ac8..e41f60b23749 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
+@@ -44,22 +44,13 @@
+ 
+ struct gpio;
+ 
+-static void dal_hw_generic_construct(
+-	struct hw_generic *pin,
+-	enum gpio_id id,
+-	uint32_t en,
+-	struct dc_context *ctx)
+-{
+-	dal_hw_gpio_construct(&pin->base, id, en, ctx);
+-}
+-
+ static void dal_hw_generic_destruct(
+ 	struct hw_generic *pin)
+ {
+ 	dal_hw_gpio_destruct(&pin->base);
+ }
+ 
+-static void destroy(
++static void dal_hw_generic_destroy(
+ 	struct hw_gpio_pin **ptr)
+ {
+ 	struct hw_generic *generic = HW_GENERIC_FROM_BASE(*ptr);
+@@ -88,7 +79,7 @@ static enum gpio_result set_config(
+ }
+ 
+ static const struct hw_gpio_pin_funcs funcs = {
+-	.destroy = destroy,
++	.destroy = dal_hw_generic_destroy,
+ 	.open = dal_hw_gpio_open,
+ 	.get_value = dal_hw_gpio_get_value,
+ 	.set_value = dal_hw_gpio_set_value,
+@@ -97,14 +88,14 @@ static const struct hw_gpio_pin_funcs funcs = {
+ 	.close = dal_hw_gpio_close,
+ };
+ 
+-static void construct(
+-	struct hw_generic *generic,
++static void dal_hw_generic_construct(
++	struct hw_generic *pin,
+ 	enum gpio_id id,
+ 	uint32_t en,
+ 	struct dc_context *ctx)
+ {
+-	dal_hw_generic_construct(generic, id, en, ctx);
+-	generic->base.base.funcs = &funcs;
++	dal_hw_gpio_construct(&pin->base, id, en, ctx);
++	pin->base.base.funcs = &funcs;
+ }
+ 
+ void dal_hw_generic_init(
+@@ -124,7 +115,7 @@ void dal_hw_generic_init(
+ 		return;
+ 	}
+ 
+-	construct(*hw_generic, id, en, ctx);
++	dal_hw_generic_construct(*hw_generic, id, en, ctx);
+ }
+ 
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
+index 88798cf3965e..1489fdfaf0e7 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
+@@ -44,34 +44,18 @@
+ 
+ struct gpio;
+ 
+-static void dal_hw_hpd_construct(
+-	struct hw_hpd *pin,
+-	enum gpio_id id,
+-	uint32_t en,
+-	struct dc_context *ctx)
+-{
+-	dal_hw_gpio_construct(&pin->base, id, en, ctx);
+-}
+-
+ static void dal_hw_hpd_destruct(
+ 	struct hw_hpd *pin)
+ {
+ 	dal_hw_gpio_destruct(&pin->base);
+ }
+ 
+-
+-static void destruct(
+-	struct hw_hpd *hpd)
+-{
+-	dal_hw_hpd_destruct(hpd);
+-}
+-
+-static void destroy(
++static void dal_hw_hpd_destroy(
+ 	struct hw_gpio_pin **ptr)
+ {
+ 	struct hw_hpd *hpd = HW_HPD_FROM_BASE(*ptr);
+ 
+-	destruct(hpd);
++	dal_hw_hpd_destruct(hpd);
+ 
+ 	kfree(hpd);
+ 
+@@ -118,7 +102,7 @@ static enum gpio_result set_config(
+ }
+ 
+ static const struct hw_gpio_pin_funcs funcs = {
+-	.destroy = destroy,
++	.destroy = dal_hw_hpd_destroy,
+ 	.open = dal_hw_gpio_open,
+ 	.get_value = get_value,
+ 	.set_value = dal_hw_gpio_set_value,
+@@ -127,14 +111,14 @@ static const struct hw_gpio_pin_funcs funcs = {
+ 	.close = dal_hw_gpio_close,
+ };
+ 
+-static void construct(
+-	struct hw_hpd *hpd,
++static void dal_hw_hpd_construct(
++	struct hw_hpd *pin,
+ 	enum gpio_id id,
+ 	uint32_t en,
+ 	struct dc_context *ctx)
+ {
+-	dal_hw_hpd_construct(hpd, id, en, ctx);
+-	hpd->base.base.funcs = &funcs;
++	dal_hw_gpio_construct(&pin->base, id, en, ctx);
++	pin->base.base.funcs = &funcs;
+ }
+ 
+ void dal_hw_hpd_init(
+@@ -154,7 +138,7 @@ void dal_hw_hpd_init(
+ 		return;
+ 	}
+ 
+-	construct(*hw_hpd, id, en, ctx);
++	dal_hw_hpd_construct(*hw_hpd, id, en, ctx);
+ }
+ 
+ struct hw_gpio_pin *dal_hw_hpd_get_pin(struct gpio *gpio)
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+index 86987f5e8bd5..80603e18ecd6 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+@@ -401,7 +401,7 @@ static const struct irq_service_funcs irq_service_funcs_dce110 = {
+ 		.to_dal_irq_source = to_dal_irq_source_dce110
+ };
+ 
+-static void construct(struct irq_service *irq_service,
++static void dce110_irq_construct(struct irq_service *irq_service,
+ 		      struct irq_service_init_data *init_data)
+ {
+ 	dal_irq_service_construct(irq_service, init_data);
+@@ -419,6 +419,6 @@ dal_irq_service_dce110_create(struct irq_service_init_data *init_data)
+ 	if (!irq_service)
+ 		return NULL;
+ 
+-	construct(irq_service, init_data);
++	dce110_irq_construct(irq_service, init_data);
+ 	return irq_service;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
+index 750ba0ab4106..0a5e1a2a3c61 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
+@@ -271,7 +271,7 @@ static const struct irq_service_funcs irq_service_funcs_dce120 = {
+ 		.to_dal_irq_source = to_dal_irq_source_dce110
+ };
+ 
+-static void construct(
++static void dce120_irq_construct(
+ 	struct irq_service *irq_service,
+ 	struct irq_service_init_data *init_data)
+ {
+@@ -290,6 +290,6 @@ struct irq_service *dal_irq_service_dce120_create(
+ 	if (!irq_service)
+ 		return NULL;
+ 
+-	construct(irq_service, init_data);
++	dce120_irq_construct(irq_service, init_data);
+ 	return irq_service;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
+index de218fe84a43..85f63b4a8b90 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
+@@ -281,7 +281,7 @@ static const struct irq_service_funcs irq_service_funcs_dce80 = {
+ 		.to_dal_irq_source = to_dal_irq_source_dce110
+ };
+ 
+-static void construct(
++static void dce80_irq_construct(
+ 	struct irq_service *irq_service,
+ 	struct irq_service_init_data *init_data)
+ {
+@@ -300,7 +300,7 @@ struct irq_service *dal_irq_service_dce80_create(
+ 	if (!irq_service)
+ 		return NULL;
+ 
+-	construct(irq_service, init_data);
++	dce80_irq_construct(irq_service, init_data);
+ 	return irq_service;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
+index d179e4d8c485..f86eb50ac461 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
+@@ -353,7 +353,7 @@ static const struct irq_service_funcs irq_service_funcs_dcn10 = {
+ 		.to_dal_irq_source = to_dal_irq_source_dcn10
+ };
+ 
+-static void construct(
++static void dcn10_irq_construct(
+ 	struct irq_service *irq_service,
+ 	struct irq_service_init_data *init_data)
+ {
+@@ -372,6 +372,6 @@ struct irq_service *dal_irq_service_dcn10_create(
+ 	if (!irq_service)
+ 		return NULL;
+ 
+-	construct(irq_service, init_data);
++	dcn10_irq_construct(irq_service, init_data);
+ 	return irq_service;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
+index 1fdbc9e5f7bc..4711ea6f43e3 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
+@@ -357,7 +357,7 @@ static const struct irq_service_funcs irq_service_funcs_dcn20 = {
+ 		.to_dal_irq_source = to_dal_irq_source_dcn20
+ };
+ 
+-static void construct(
++static void dcn20_irq_construct(
+ 	struct irq_service *irq_service,
+ 	struct irq_service_init_data *init_data)
+ {
+@@ -376,6 +376,6 @@ struct irq_service *dal_irq_service_dcn20_create(
+ 	if (!irq_service)
+ 		return NULL;
+ 
+-	construct(irq_service, init_data);
++	dcn20_irq_construct(irq_service, init_data);
+ 	return irq_service;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
+index 2794c0598f1e..8ec1f8f592ae 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
+@@ -348,7 +348,7 @@ static const struct irq_service_funcs irq_service_funcs_dcn21 = {
+ 		.to_dal_irq_source = to_dal_irq_source_dcn21
+ };
+ 
+-static void construct(
++static void dcn21_irq_construct(
+ 	struct irq_service *irq_service,
+ 	struct irq_service_init_data *init_data)
+ {
+@@ -367,6 +367,6 @@ struct irq_service *dal_irq_service_dcn21_create(
+ 	if (!irq_service)
+ 		return NULL;
+ 
+-	construct(irq_service, init_data);
++	dcn21_irq_construct(irq_service, init_data);
+ 	return irq_service;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4488-drm-amd-display-add-color-space-option-when-sending-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4488-drm-amd-display-add-color-space-option-when-sending-.patch
new file mode 100644
index 00000000..6e4654bd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4488-drm-amd-display-add-color-space-option-when-sending-.patch
@@ -0,0 +1,396 @@
+From 4aa44071610a84e54543ed1afba70c295c7ab1fa Mon Sep 17 00:00:00 2001
+From: Wenjing Liu <Wenjing.Liu@amd.com>
+Date: Tue, 15 Oct 2019 15:12:57 -0400
+Subject: [PATCH 4488/4736] drm/amd/display: add color space option when
+ sending link test pattern
+
+[why]
+In the TEST_MSIC dpcd register field definition, the test equipment
+has the option to choose between YCbCr601 or YCbCr709.
+We will apply corresponding YCbCr coefficient based on this test
+request.
+
+[how]
+Add a new input parameter in dc_link_dp_set_test_pattern to allow the
+selection between different color space.
+
+Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |  1 +
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c |  2 +
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 39 +++++++++++++++++--
+ drivers/gpu/drm/amd/display/dc/dc_dp_types.h  | 10 ++---
+ drivers/gpu/drm/amd/display/dc/dc_link.h      |  2 +
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  9 ++++-
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_opp.c  | 16 +++++++-
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_opp.h  |  1 +
+ .../gpu/drm/amd/display/dc/inc/hw/hw_shared.h |  7 ++++
+ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h   |  1 +
+ .../amd/display/include/link_service_types.h  |  7 ++++
+ 11 files changed, 85 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+index 2bb1fae452d9..ae5c898ade17 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+@@ -655,6 +655,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us
+ 	dc_link_set_test_pattern(
+ 		link,
+ 		test_pattern,
++		DP_TEST_PATTERN_COLOR_SPACE_RGB,
+ 		&link_training_settings,
+ 		custom_pattern,
+ 		10);
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 014cb7cf9cba..ec010dc0de8b 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -3333,6 +3333,7 @@ void dc_link_disable_hpd(const struct dc_link *link)
+ 
+ void dc_link_set_test_pattern(struct dc_link *link,
+ 			      enum dp_test_pattern test_pattern,
++			      enum dp_test_pattern_color_space test_pattern_color_space,
+ 			      const struct link_training_settings *p_link_settings,
+ 			      const unsigned char *p_custom_pattern,
+ 			      unsigned int cust_pattern_size)
+@@ -3341,6 +3342,7 @@ void dc_link_set_test_pattern(struct dc_link *link,
+ 		dc_link_dp_set_test_pattern(
+ 			link,
+ 			test_pattern,
++			test_pattern_color_space,
+ 			p_link_settings,
+ 			p_custom_pattern,
+ 			cust_pattern_size);
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 66f59058b56d..4e0ca8d1b484 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2507,6 +2507,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
+ 	dc_link_dp_set_test_pattern(
+ 		link,
+ 		test_pattern,
++		DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
+ 		&link_training_settings,
+ 		test_80_bit_pattern,
+ 		(DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
+@@ -2518,6 +2519,8 @@ static void dp_test_send_link_test_pattern(struct dc_link *link)
+ 	union link_test_pattern dpcd_test_pattern;
+ 	union test_misc dpcd_test_params;
+ 	enum dp_test_pattern test_pattern;
++	enum dp_test_pattern_color_space test_pattern_color_space =
++			DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
+ 
+ 	memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
+ 	memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
+@@ -2552,9 +2555,14 @@ static void dp_test_send_link_test_pattern(struct dc_link *link)
+ 	break;
+ 	}
+ 
++	test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
++			DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
++			DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
++
+ 	dc_link_dp_set_test_pattern(
+ 			link,
+ 			test_pattern,
++			test_pattern_color_space,
+ 			NULL,
+ 			NULL,
+ 			0);
+@@ -3350,7 +3358,8 @@ static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
+ 
+ static void set_crtc_test_pattern(struct dc_link *link,
+ 				struct pipe_ctx *pipe_ctx,
+-				enum dp_test_pattern test_pattern)
++				enum dp_test_pattern test_pattern,
++				enum dp_test_pattern_color_space test_pattern_color_space)
+ {
+ 	enum controller_dp_test_pattern controller_test_pattern;
+ 	enum dc_color_depth color_depth = pipe_ctx->
+@@ -3411,8 +3420,27 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 		else if (opp->funcs->opp_set_disp_pattern_generator) {
+ 			struct pipe_ctx *odm_pipe;
++			enum controller_dp_color_space controller_color_space;
+ 			int opp_cnt = 1;
+ 
++			switch (test_pattern_color_space) {
++			case DP_TEST_PATTERN_COLOR_SPACE_RGB:
++				controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
++				break;
++			case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
++				controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
++				break;
++			case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
++				controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
++				break;
++			case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
++			default:
++				controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
++				DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
++				ASSERT(0);
++				break;
++			}
++
+ 			for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
+ 				opp_cnt++;
+ 
+@@ -3424,6 +3452,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ 				odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
+ 				odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
+ 					controller_test_pattern,
++					controller_color_space,
+ 					color_depth,
+ 					NULL,
+ 					width,
+@@ -3431,6 +3460,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ 			}
+ 			opp->funcs->opp_set_disp_pattern_generator(opp,
+ 				controller_test_pattern,
++				controller_color_space,
+ 				color_depth,
+ 				NULL,
+ 				width,
+@@ -3464,6 +3494,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ 				odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
+ 				odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
+ 					CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
++					CONTROLLER_DP_COLOR_SPACE_UDEFINED,
+ 					color_depth,
+ 					NULL,
+ 					width,
+@@ -3471,6 +3502,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ 			}
+ 			opp->funcs->opp_set_disp_pattern_generator(opp,
+ 				CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
++				CONTROLLER_DP_COLOR_SPACE_UDEFINED,
+ 				color_depth,
+ 				NULL,
+ 				width,
+@@ -3488,6 +3520,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ bool dc_link_dp_set_test_pattern(
+ 	struct dc_link *link,
+ 	enum dp_test_pattern test_pattern,
++	enum dp_test_pattern_color_space test_pattern_color_space,
+ 	const struct link_training_settings *p_link_settings,
+ 	const unsigned char *p_custom_pattern,
+ 	unsigned int cust_pattern_size)
+@@ -3516,7 +3549,7 @@ bool dc_link_dp_set_test_pattern(
+ 	if (link->test_pattern_enabled && test_pattern ==
+ 			DP_TEST_PATTERN_VIDEO_MODE) {
+ 		/* Set CRTC Test Pattern */
+-		set_crtc_test_pattern(link, pipe_ctx, test_pattern);
++		set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
+ 		dp_set_hw_test_pattern(link, test_pattern,
+ 				(uint8_t *)p_custom_pattern,
+ 				(uint32_t)cust_pattern_size);
+@@ -3631,7 +3664,7 @@ bool dc_link_dp_set_test_pattern(
+ 		}
+ 	} else {
+ 	/* CRTC Patterns */
+-		set_crtc_test_pattern(link, pipe_ctx, test_pattern);
++		set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
+ 		/* Set Test Pattern state */
+ 		link->test_pattern_enabled = true;
+ 	}
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+index ef79a686e4c2..f0a6e25d2d4a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+@@ -524,14 +524,14 @@ union link_test_pattern {
+ 
+ union test_misc {
+ 	struct dpcd_test_misc_bits {
+-		unsigned char SYNC_CLOCK :1;
++		unsigned char SYNC_CLOCK  :1;
+ 		/* dpcd_test_color_format */
+-		unsigned char CLR_FORMAT :2;
++		unsigned char CLR_FORMAT  :2;
+ 		/* dpcd_test_dyn_range */
+-		unsigned char DYN_RANGE  :1;
+-		unsigned char YCBCR      :1;
++		unsigned char DYN_RANGE   :1;
++		unsigned char YCBCR_COEFS :1;
+ 		/* dpcd_test_bit_depth */
+-		unsigned char BPC        :3;
++		unsigned char BPC         :3;
+ 	} bits;
+ 	unsigned char raw;
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
+index 67ba6666a324..ccb68c14a806 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
+@@ -260,6 +260,7 @@ void dc_link_dp_disable_hpd(const struct dc_link *link);
+ bool dc_link_dp_set_test_pattern(
+ 	struct dc_link *link,
+ 	enum dp_test_pattern test_pattern,
++	enum dp_test_pattern_color_space test_pattern_color_space,
+ 	const struct link_training_settings *p_link_settings,
+ 	const unsigned char *p_custom_pattern,
+ 	unsigned int cust_pattern_size);
+@@ -291,6 +292,7 @@ void dc_link_enable_hpd(const struct dc_link *link);
+ void dc_link_disable_hpd(const struct dc_link *link);
+ void dc_link_set_test_pattern(struct dc_link *link,
+ 			enum dp_test_pattern test_pattern,
++			enum dp_test_pattern_color_space test_pattern_color_space,
+ 			const struct link_training_settings *p_link_settings,
+ 			const unsigned char *p_custom_pattern,
+ 			unsigned int cust_pattern_size);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 921a36668ced..cb71b2787ddb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -225,6 +225,7 @@ void dcn20_init_blank(
+ 	opp->funcs->opp_set_disp_pattern_generator(
+ 			opp,
+ 			CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
++			CONTROLLER_DP_COLOR_SPACE_UDEFINED,
+ 			COLOR_DEPTH_UNDEFINED,
+ 			&black_color,
+ 			otg_active_width,
+@@ -234,6 +235,7 @@ void dcn20_init_blank(
+ 		bottom_opp->funcs->opp_set_disp_pattern_generator(
+ 				bottom_opp,
+ 				CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
++				CONTROLLER_DP_COLOR_SPACE_UDEFINED,
+ 				COLOR_DEPTH_UNDEFINED,
+ 				&black_color,
+ 				otg_active_width,
+@@ -855,6 +857,7 @@ void dcn20_blank_pixel_data(
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	enum dc_color_space color_space = stream->output_color_space;
+ 	enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
++	enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
+ 	struct pipe_ctx *odm_pipe;
+ 	int odm_cnt = 1;
+ 
+@@ -873,8 +876,10 @@ void dcn20_blank_pixel_data(
+ 		if (stream_res->abm)
+ 			stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
+ 
+-		if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
++		if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
+ 			test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
++			test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
++		}
+ 	} else {
+ 		test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
+ 	}
+@@ -882,6 +887,7 @@ void dcn20_blank_pixel_data(
+ 	stream_res->opp->funcs->opp_set_disp_pattern_generator(
+ 			stream_res->opp,
+ 			test_pattern,
++			test_pattern_color_space,
+ 			stream->timing.display_color_depth,
+ 			&black_color,
+ 			width,
+@@ -892,6 +898,7 @@ void dcn20_blank_pixel_data(
+ 				odm_pipe->stream_res.opp,
+ 				dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
+ 						CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
++				test_pattern_color_space,
+ 				stream->timing.display_color_depth,
+ 				&black_color,
+ 				width,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
+index 40164ed015ea..023cc71fad0f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
+@@ -41,6 +41,7 @@
+ void opp2_set_disp_pattern_generator(
+ 		struct output_pixel_processor *opp,
+ 		enum controller_dp_test_pattern test_pattern,
++		enum controller_dp_color_space color_space,
+ 		enum dc_color_depth color_depth,
+ 		const struct tg_color *solid_color,
+ 		int width,
+@@ -100,9 +101,22 @@ void opp2_set_disp_pattern_generator(
+ 				TEST_PATTERN_DYN_RANGE_CEA :
+ 				TEST_PATTERN_DYN_RANGE_VESA);
+ 
++		switch (color_space) {
++		case CONTROLLER_DP_COLOR_SPACE_YCBCR601:
++			mode = TEST_PATTERN_MODE_COLORSQUARES_YCBCR601;
++		break;
++		case CONTROLLER_DP_COLOR_SPACE_YCBCR709:
++			mode = TEST_PATTERN_MODE_COLORSQUARES_YCBCR709;
++		break;
++		case CONTROLLER_DP_COLOR_SPACE_RGB:
++		default:
++			mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
++		break;
++		}
++
+ 		REG_UPDATE_6(DPG_CONTROL,
+ 			DPG_EN, 1,
+-			DPG_MODE, TEST_PATTERN_MODE_COLORSQUARES_RGB,
++			DPG_MODE, mode,
+ 			DPG_DYNAMIC_RANGE, dyn_range,
+ 			DPG_BIT_DEPTH, bit_depth,
+ 			DPG_VRES, 6,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h
+index abd8de9a78f8..4093bec172c1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h
+@@ -140,6 +140,7 @@ void dcn20_opp_construct(struct dcn20_opp *oppn20,
+ void opp2_set_disp_pattern_generator(
+ 	struct output_pixel_processor *opp,
+ 	enum controller_dp_test_pattern test_pattern,
++	enum controller_dp_color_space color_space,
+ 	enum dc_color_depth color_depth,
+ 	const struct tg_color *solid_color,
+ 	int width,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+index f82365e2d03c..91fda51e5370 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+@@ -255,6 +255,13 @@ enum controller_dp_test_pattern {
+ 	CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR
+ };
+ 
++enum controller_dp_color_space {
++	CONTROLLER_DP_COLOR_SPACE_RGB,
++	CONTROLLER_DP_COLOR_SPACE_YCBCR601,
++	CONTROLLER_DP_COLOR_SPACE_YCBCR709,
++	CONTROLLER_DP_COLOR_SPACE_UDEFINED
++};
++
+ enum dc_lut_mode {
+ 	LUT_BYPASS,
+ 	LUT_RAM_A,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+index 18def2b6fafe..b01ff30145fd 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+@@ -309,6 +309,7 @@ struct opp_funcs {
+ 	void (*opp_set_disp_pattern_generator)(
+ 			struct output_pixel_processor *opp,
+ 			enum controller_dp_test_pattern test_pattern,
++			enum controller_dp_color_space color_space,
+ 			enum dc_color_depth color_depth,
+ 			const struct tg_color *solid_color,
+ 			int width,
+diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
+index 876b0b3e1a9c..4869d4562e4d 100644
+--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
++++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
+@@ -123,6 +123,13 @@ enum dp_test_pattern {
+ 	DP_TEST_PATTERN_UNSUPPORTED
+ };
+ 
++enum dp_test_pattern_color_space {
++	DP_TEST_PATTERN_COLOR_SPACE_RGB,
++	DP_TEST_PATTERN_COLOR_SPACE_YCBCR601,
++	DP_TEST_PATTERN_COLOR_SPACE_YCBCR709,
++	DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED
++};
++
+ enum dp_panel_mode {
+ 	/* not required */
+ 	DP_PANEL_MODE_DEFAULT,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4489-drm-amd-display-Adjust-DML-workaround-threshold.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4489-drm-amd-display-Adjust-DML-workaround-threshold.patch
new file mode 100644
index 00000000..d2853f2b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4489-drm-amd-display-Adjust-DML-workaround-threshold.patch
@@ -0,0 +1,51 @@
+From 5f7f2f8aea196df5274a3bf3a7ff96d119be54d7 Mon Sep 17 00:00:00 2001
+From: Joshua Aberback <joshua.aberback@amd.com>
+Date: Fri, 1 Nov 2019 17:29:20 -0400
+Subject: [PATCH 4489/4736] drm/amd/display: Adjust DML workaround threshold
+
+[Why]
+There is a case where the margin is between 50 and 60, but applying the
+workaround causes a hang. By increasing the threshold, we are blocking more
+cases from switching p-state during active, but those cases will fall back
+to switching during blank, which is fine.
+
+[How]
+ - increase required margin from 50 to 60
+
+Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c  | 2 +-
+ .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c    | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+index 77b7574c63cb..3b224b155e8c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+@@ -2578,7 +2578,7 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
+ 					+ mode_lib->vba.DRAMClockChangeLatency;
+ 
+ 	if (mode_lib->vba.DRAMClockChangeSupportsVActive &&
+-			mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
++			mode_lib->vba.MinActiveDRAMClockChangeMargin > 60) {
+ 		mode_lib->vba.DRAMClockChangeWatermark += 25;
+ 		mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
+ 	} else {
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+index 62dfd36d830a..6482d7b99bae 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+@@ -2612,7 +2612,7 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
+ 					+ mode_lib->vba.DRAMClockChangeLatency;
+ 
+ 	if (mode_lib->vba.DRAMClockChangeSupportsVActive &&
+-		mode_lib->vba.MinActiveDRAMClockChangeMargin > 50) {
++			mode_lib->vba.MinActiveDRAMClockChangeMargin > 60) {
+ 		mode_lib->vba.DRAMClockChangeWatermark += 25;
+ 		mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
+ 	} else if (mode_lib->vba.DummyPStateCheck &&
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4490-drm-amd-display-Add-debug-trace-for-dmcub-FW-autoloa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4490-drm-amd-display-Add-debug-trace-for-dmcub-FW-autoloa.patch
new file mode 100644
index 00000000..1dec9bea
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4490-drm-amd-display-Add-debug-trace-for-dmcub-FW-autoloa.patch
@@ -0,0 +1,163 @@
+From f5b00cee7af647b42e233533666123bdc6024de3 Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Sat, 26 Oct 2019 10:19:40 -0400
+Subject: [PATCH 4490/4736] drm/amd/display: Add debug trace for dmcub FW
+ autoload.
+
+[Why & How]
+1. Add trace code enum for easy debugging.
+2. Add trace during uC boot up, including loading phy FW
+   and dmcu FW.
+3. Change cache memory type back to write back,
+   since write through has issue when resume from S0i3 100% hang after
+   3.2ms.
+4. Change CW3 base address to hard code value to avoid memory overlap
+   with cw1.
+5. Change polling phy init done to infinite loop to avoid dcn hang when
+   dmcub uC stalled.
+6. Add dmcub FW dis-assembly file to repositatory for debug purpose.
+
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ .../amd/display/dmub/inc/dmub_trace_buffer.h  | 21 +++++++++++++++++--
+ .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c |  2 +-
+ .../gpu/drm/amd/display/dmub/src/dmub_srv.c   | 20 +++++++++++-------
+ 3 files changed, 33 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
+index 9707706ba8ce..b0ee099d8a6e 100644
+--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
+@@ -30,8 +30,25 @@
+ #define LOAD_DMCU_FW	1
+ #define LOAD_PHY_FW	2
+ 
++
++enum dmucb_trace_code {
++	DMCUB__UNKNOWN,
++	DMCUB__MAIN_BEGIN,
++	DMCUB__PHY_INIT_BEGIN,
++	DMCUB__PHY_FW_SRAM_LOAD_BEGIN,
++	DMCUB__PHY_FW_SRAM_LOAD_END,
++	DMCUB__PHY_INIT_POLL_DONE,
++	DMCUB__PHY_INIT_END,
++	DMCUB__DMCU_ERAM_LOAD_BEGIN,
++	DMCUB__DMCU_ERAM_LOAD_END,
++	DMCUB__DMCU_ISR_LOAD_BEGIN,
++	DMCUB__DMCU_ISR_LOAD_END,
++	DMCUB__MAIN_IDLE,
++	DMCUB__PERF_TRACE,
++};
++
+ struct dmcub_trace_buf_entry {
+-	uint32_t trace_code;
++	enum dmucb_trace_code trace_code;
+ 	uint32_t tick_count;
+ 	uint32_t param0;
+ 	uint32_t param1;
+@@ -40,6 +57,7 @@ struct dmcub_trace_buf_entry {
+ #define TRACE_BUF_SIZE (1024) //1 kB
+ #define PERF_TRACE_MAX_ENTRY ((TRACE_BUF_SIZE - 8)/sizeof(struct dmcub_trace_buf_entry))
+ 
++
+ struct dmcub_trace_buf {
+ 	uint32_t entry_count;
+ 	uint32_t clk_freq;
+@@ -47,5 +65,4 @@ struct dmcub_trace_buf {
+ };
+ 
+ 
+-
+ #endif /* _DMUB_TRACE_BUFFER_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+index 89fd27758dd5..e2b2cf2e01fd 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+@@ -138,5 +138,5 @@ bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
+ 
+ bool dmub_dcn20_is_phy_init(struct dmub_srv *dmub)
+ {
+-	return REG_READ(DMCUB_SCRATCH10) != 0;
++	return REG_READ(DMCUB_SCRATCH10) == 0;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+index 0dd32edbbcb3..5ae1906ff1b1 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+@@ -26,6 +26,8 @@
+ #include "../inc/dmub_srv.h"
+ #include "dmub_dcn20.h"
+ #include "dmub_dcn21.h"
++#include "dmub_trace_buffer.h"
++#include "os_types.h"
+ /*
+  * Note: the DMUB service is standalone. No additional headers should be
+  * added below or above this line unless they reside within the DMUB
+@@ -44,8 +46,6 @@
+ /* Mailbox size */
+ #define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE)
+ 
+-/* Tracebuffer size */
+-#define DMUB_TRACEBUFF_SIZE (1024) //1kB buffer
+ 
+ /* Number of windows in use. */
+ #define DMUB_NUM_WINDOWS (DMUB_WINDOW_5_TRACEBUFF + 1)
+@@ -53,6 +53,7 @@
+ 
+ #define DMUB_CW0_BASE (0x60000000)
+ #define DMUB_CW1_BASE (0x61000000)
++#define DMUB_CW3_BASE (0x63000000)
+ #define DMUB_CW5_BASE (0x65000000)
+ 
+ static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
+@@ -181,7 +182,7 @@ dmub_srv_calc_region_info(struct dmub_srv *dmub,
+ 	mail->top = mail->base + DMUB_MAILBOX_SIZE;
+ 
+ 	trace_buff->base = dmub_align(mail->top, 256);
+-	trace_buff->top = trace_buff->base + DMUB_TRACEBUFF_SIZE;
++	trace_buff->top = trace_buff->base + TRACE_BUF_SIZE;
+ 
+ 	out->fb_size = dmub_align(trace_buff->top, 4096);
+ 
+@@ -291,7 +292,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
+ 		cw2.region.top = cw2.region.base + data_fb->size;
+ 
+ 		cw3.offset.quad_part = bios_fb->gpu_addr;
+-		cw3.region.base = DMUB_CW1_BASE + stack_fb->size;
++		cw3.region.base = DMUB_CW3_BASE;
+ 		cw3.region.top = cw3.region.base + bios_fb->size;
+ 
+ 		cw4.offset.quad_part = mail_fb->gpu_addr;
+@@ -394,19 +395,24 @@ enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
+ enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
+ 					    uint32_t timeout_us)
+ {
+-	uint32_t i;
++	uint32_t i = 0;
+ 
+ 	if (!dmub->hw_init || !dmub->hw_funcs.is_phy_init)
+ 		return DMUB_STATUS_INVALID;
+ 
+-	for (i = 0; i <= timeout_us; i += 10) {
++/*	for (i = 0; i <= timeout_us; i += 10) {
+ 		if (dmub->hw_funcs.is_phy_init(dmub))
+ 			return DMUB_STATUS_OK;
+ 
+ 		udelay(10);
++	}*/
++	while (!dmub->hw_funcs.is_phy_init(dmub)) {
++		ASSERT(i <= timeout_us);
++		i += 10;
++		udelay(10);
+ 	}
+ 
+-	return DMUB_STATUS_TIMEOUT;
++	return DMUB_STATUS_OK;
+ }
+ 
+ enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4491-drm-amd-display-3.2.60.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4491-drm-amd-display-3.2.60.patch
new file mode 100644
index 00000000..3ee4d1d4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4491-drm-amd-display-3.2.60.patch
@@ -0,0 +1,28 @@
+From d93b4fe44ad3e710e20b0c58e9dd4c55dc9ebcc1 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Mon, 4 Nov 2019 08:31:14 -0500
+Subject: [PATCH 4491/4736] drm/amd/display: 3.2.60
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index b107d6fab972..068c4437fdeb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.59"
++#define DC_VER "3.2.60"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4492-drm-amd-display-add-debugfs-sdp-hook-up-function-for.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4492-drm-amd-display-add-debugfs-sdp-hook-up-function-for.patch
new file mode 100644
index 00000000..c69a9dbf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4492-drm-amd-display-add-debugfs-sdp-hook-up-function-for.patch
@@ -0,0 +1,36 @@
+From 526eba4084b53b22121ec9f467a77410ad5dc176 Mon Sep 17 00:00:00 2001
+From: "David (Dingchen) Zhang" <dingchen.zhang@amd.com>
+Date: Thu, 31 Oct 2019 14:36:51 -0400
+Subject: [PATCH 4492/4736] drm/amd/display: add debugfs sdp hook up function
+ for Navi
+
+[why]
+need to send immediate SDP message via debugfs on Navi board.
+
+[how]
+hook up the DCN1x encoder function of sending immediate sdp
+message to DCN2.
+
+Signed-off-by: David (Dingchen) Zhang <dingchen.zhang@amd.com>
+Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+index d60d072848ba..b909c526b7f9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+@@ -563,6 +563,8 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = {
+ 		enc2_stream_encoder_stop_hdmi_info_packets,
+ 	.update_dp_info_packets =
+ 		enc2_stream_encoder_update_dp_info_packets,
++	.send_immediate_sdp_message =
++		enc1_stream_encoder_send_immediate_sdp_message,
+ 	.stop_dp_info_packets =
+ 		enc1_stream_encoder_stop_dp_info_packets,
+ 	.dp_blank =
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4493-drm-amd-display-Avoid-conflict-between-HDR-multiplie.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4493-drm-amd-display-Avoid-conflict-between-HDR-multiplie.patch
new file mode 100644
index 00000000..1f3478f5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4493-drm-amd-display-Avoid-conflict-between-HDR-multiplie.patch
@@ -0,0 +1,183 @@
+From 23b89fbecda472cfbce9af0e7393f9f55f0c80e8 Mon Sep 17 00:00:00 2001
+From: Michael Strauss <michael.strauss@amd.com>
+Date: Sun, 3 Nov 2019 09:35:03 -0500
+Subject: [PATCH 4493/4736] drm/amd/display: Avoid conflict between HDR
+ multiplier and 3dlut
+
+[WHY]
+There can be a conflict between OS HDR multiplier and 3dlut HDR
+multiplier, which are both sent to DC.
+
+[HOW]
+Instead of having dc determine which HDR multiplier to use, make the
+decision in dm and send only the intended value in a surface update.
+Store the current OS HDR multiplier and determine whether to use it or
+the 3dlut's multiplier before sending the surface update to dc. Send
+multiplier to dc in fixed31_32 format, dc then converts it to hw format.
+
+Signed-off-by: Michael Strauss <michael.strauss@amd.com>
+Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c        | 17 ++++++++++-------
+ drivers/gpu/drm/amd/display/dc/dc.h             |  9 ++++-----
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c   | 10 +++++++---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c  | 10 +---------
+ 4 files changed, 22 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 7539c3accd59..66ddc2443e1e 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1484,11 +1484,6 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
+ 		elevate_update_type(&update_type, UPDATE_TYPE_MED);
+ 	}
+ 
+-	if (u->plane_info->sdr_white_level != u->surface->sdr_white_level) {
+-		update_flags->bits.sdr_white_level = 1;
+-		elevate_update_type(&update_type, UPDATE_TYPE_MED);
+-	}
+-
+ 	if (u->plane_info->dcc.enable != u->surface->dcc.enable
+ 			|| u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
+ 			|| u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
+@@ -1635,6 +1630,12 @@ static enum surface_update_type det_surface_update(const struct dc *dc,
+ 			update_flags->bits.gamma_change = 1;
+ 	}
+ 
++	if (u->hdr_mult.value)
++		if (u->hdr_mult.value != u->surface->hdr_mult.value) {
++			update_flags->bits.hdr_mult = 1;
++			elevate_update_type(&overall_type, UPDATE_TYPE_MED);
++		}
++
+ 	if (update_flags->bits.in_transfer_func_change) {
+ 		type = UPDATE_TYPE_MED;
+ 		elevate_update_type(&overall_type, type);
+@@ -1818,8 +1819,6 @@ static void copy_surface_update_to_plane(
+ 				srf_update->plane_info->global_alpha_value;
+ 		surface->dcc =
+ 				srf_update->plane_info->dcc;
+-		surface->sdr_white_level =
+-				srf_update->plane_info->sdr_white_level;
+ 		surface->layer_index =
+ 				srf_update->plane_info->layer_index;
+ 	}
+@@ -1865,6 +1864,10 @@ static void copy_surface_update_to_plane(
+ 		memcpy(surface->lut3d_func, srf_update->lut3d_func,
+ 		sizeof(*surface->lut3d_func));
+ 
++	if (srf_update->hdr_mult.value)
++		surface->hdr_mult =
++				srf_update->hdr_mult;
++
+ 	if (srf_update->blend_tf &&
+ 			(surface->blend_tf !=
+ 			srf_update->blend_tf))
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 068c4437fdeb..8af7014b1588 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -690,7 +690,7 @@ union dc_3dlut_state {
+ struct dc_3dlut {
+ 	struct kref refcount;
+ 	struct tetrahedral_params lut_3d;
+-	uint32_t hdr_multiplier;
++	struct fixed31_32 hdr_multiplier;
+ 	bool initialized; /*remove after diag fix*/
+ 	union dc_3dlut_state state;
+ 	struct dc_context *ctx;
+@@ -718,7 +718,7 @@ union surface_update_flags {
+ 		uint32_t horizontal_mirror_change:1;
+ 		uint32_t per_pixel_alpha_change:1;
+ 		uint32_t global_alpha_change:1;
+-		uint32_t sdr_white_level:1;
++		uint32_t hdr_mult:1;
+ 		uint32_t rotation_change:1;
+ 		uint32_t swizzle_change:1;
+ 		uint32_t scaling_change:1;
+@@ -764,7 +764,7 @@ struct dc_plane_state {
+ 	struct dc_bias_and_scale *bias_and_scale;
+ 	struct dc_csc_transform input_csc_color_matrix;
+ 	struct fixed31_32 coeff_reduction_factor;
+-	uint32_t sdr_white_level;
++	struct fixed31_32 hdr_mult;
+ 
+ 	// TODO: No longer used, remove
+ 	struct dc_hdr_static_metadata hdr_static_ctx;
+@@ -811,7 +811,6 @@ struct dc_plane_info {
+ 	enum dc_rotation_angle rotation;
+ 	enum plane_stereo_format stereo_format;
+ 	enum dc_color_space color_space;
+-	unsigned int sdr_white_level;
+ 	bool horizontal_mirror;
+ 	bool visible;
+ 	bool per_pixel_alpha;
+@@ -835,7 +834,7 @@ struct dc_surface_update {
+ 	const struct dc_flip_addrs *flip_addr;
+ 	const struct dc_plane_info *plane_info;
+ 	const struct dc_scaling_info *scaling_info;
+-
++	struct fixed31_32 hdr_mult;
+ 	/* following updates require alloc/sleep/spin that is not isr safe,
+ 	 * null means no updates
+ 	 */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 4b6213d3ecbf..c8bd1c0cdb45 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2471,16 +2471,20 @@ static void dcn10_blank_pixel_data(
+ 
+ void set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
+ {
+-	struct fixed31_32 multiplier = dc_fixpt_from_fraction(
+-			pipe_ctx->plane_state->sdr_white_level, 80);
++	struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult;
+ 	uint32_t hw_mult = 0x1f000; // 1.0 default multiplier
+ 	struct custom_float_format fmt;
++	bool mult_negative; // True if fixed31_32 sign bit indicates negative value
++	uint32_t mult_int; // int component of fixed31_32
+ 
+ 	fmt.exponenta_bits = 6;
+ 	fmt.mantissa_bits = 12;
+ 	fmt.sign = true;
+ 
+-	if (pipe_ctx->plane_state->sdr_white_level > 80)
++	mult_negative = multiplier.value >> 63 != 0;
++	mult_int = multiplier.value >> 32;
++
++	if (mult_int && !mult_negative) // Check if greater than 1
+ 		convert_to_custom_float_format(multiplier, &fmt, &hw_mult);
+ 
+ 	pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index cb71b2787ddb..92117b6d0012 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -738,14 +738,6 @@ bool dcn20_set_shaper_3dlut(
+ 	else
+ 		result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
+ 
+-	if (plane_state->lut3d_func &&
+-		plane_state->lut3d_func->state.bits.initialized == 1 &&
+-		plane_state->lut3d_func->hdr_multiplier != 0)
+-		dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base,
+-				plane_state->lut3d_func->hdr_multiplier);
+-	else
+-		dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base, 0x1f000);
+-
+ 	return result;
+ }
+ 
+@@ -1386,7 +1378,7 @@ static void dcn20_program_pipe(
+ 		dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
+ 
+ 	if (pipe_ctx->update_flags.bits.enable
+-			|| pipe_ctx->plane_state->update_flags.bits.sdr_white_level)
++			|| pipe_ctx->plane_state->update_flags.bits.hdr_mult)
+ 		set_hdr_multiplier(pipe_ctx);
+ 
+ 	if (pipe_ctx->update_flags.bits.enable ||
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4494-drm-amd-display-Don-t-spin-forever-waiting-for-DMCUB.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4494-drm-amd-display-Don-t-spin-forever-waiting-for-DMCUB.patch
new file mode 100644
index 00000000..e7f45eed
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4494-drm-amd-display-Don-t-spin-forever-waiting-for-DMCUB.patch
@@ -0,0 +1,68 @@
+From 19ec27063b8d4efbfcd0c9f2c0399ce53b87a2bb Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Mon, 4 Nov 2019 13:32:46 -0500
+Subject: [PATCH 4494/4736] drm/amd/display: Don't spin forever waiting for
+ DMCUB phy/auto init
+
+[Why]
+It's an interface violation to use infinite loops within DMUB
+service functions and we'll lock up the kernel by doing so.
+
+[How]
+Revert the function back to its intended functionality.
+Move the infinite loops into DC/DM as necessary.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c    | 6 ++++--
+ drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 9 ++-------
+ 2 files changed, 6 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+index 61cefe0a3790..74ffe53eb49d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+@@ -112,8 +112,10 @@ void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv)
+ 	struct dc_context *dc_ctx = dc_dmub_srv->ctx;
+ 	enum dmub_status status;
+ 
+-	status = dmub_srv_wait_for_phy_init(dmub, 1000000);
+-	if (status != DMUB_STATUS_OK)
++	status = dmub_srv_wait_for_phy_init(dmub, 10000000);
++	if (status != DMUB_STATUS_OK) {
+ 		DC_ERROR("Error waiting for DMUB phy init: status=%d\n",
+ 			 status);
++		ASSERT(0);
++	}
+ }
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+index 5ae1906ff1b1..60c574a39c6a 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+@@ -400,19 +400,14 @@ enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
+ 	if (!dmub->hw_init || !dmub->hw_funcs.is_phy_init)
+ 		return DMUB_STATUS_INVALID;
+ 
+-/*	for (i = 0; i <= timeout_us; i += 10) {
++	for (i = 0; i <= timeout_us; i += 10) {
+ 		if (dmub->hw_funcs.is_phy_init(dmub))
+ 			return DMUB_STATUS_OK;
+ 
+ 		udelay(10);
+-	}*/
+-	while (!dmub->hw_funcs.is_phy_init(dmub)) {
+-		ASSERT(i <= timeout_us);
+-		i += 10;
+-		udelay(10);
+ 	}
+ 
+-	return DMUB_STATUS_OK;
++	return DMUB_STATUS_TIMEOUT;
+ }
+ 
+ enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4495-drm-amd-display-DML-Validation-Dump-Check-with-Loggi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4495-drm-amd-display-DML-Validation-Dump-Check-with-Loggi.patch
new file mode 100644
index 00000000..4903443e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4495-drm-amd-display-DML-Validation-Dump-Check-with-Loggi.patch
@@ -0,0 +1,795 @@
+From 83f4f8104261c5f2877e3b21909ed8a9d49a59c3 Mon Sep 17 00:00:00 2001
+From: Jaehyun Chung <jaehyun.chung@amd.com>
+Date: Thu, 31 Oct 2019 15:53:24 -0400
+Subject: [PATCH 4495/4736] drm/amd/display: DML Validation Dump/Check with
+ Logging
+
+[Why]
+Need validation that we are programming the expected values (rq, ttu, dlg)
+from DML. This debug feature will output logs if we are programming
+incorrect values and may help differentiate DAL issues from HW issues.
+
+[How]
+Dump relevant registers for each pipe with active stream. Compare current
+reg values with the converted DML output. Log mismatches when found.
+
+Change-Id: I42f3f19de1f0330ddb2c0c877aa32cd7798205b0
+Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
+Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c      |  18 +-
+ drivers/gpu/drm/amd/display/dc/dc.h           |   1 +
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 310 ++++++++++++++++
+ .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 345 ++++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |   7 +
+ 5 files changed, 680 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 66ddc2443e1e..81f4499490b9 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -2198,8 +2198,24 @@ static void commit_planes_for_stream(struct dc *dc,
+ 		}
+ 	}
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+-	if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST)
++	if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
+ 		dc->hwss.program_front_end_for_ctx(dc, context);
++#ifdef CONFIG_DRM_AMD_DC_DCN1_0
++		if (dc->debug.validate_dml_output) {
++			for (i = 0; i < dc->res_pool->pipe_count; i++) {
++				struct pipe_ctx cur_pipe = context->res_ctx.pipe_ctx[i];
++				if (cur_pipe.stream == NULL)
++					continue;
++
++				cur_pipe.plane_res.hubp->funcs->validate_dml_output(
++						cur_pipe.plane_res.hubp, dc->ctx,
++						&context->res_ctx.pipe_ctx[i].rq_regs,
++						&context->res_ctx.pipe_ctx[i].dlg_regs,
++						&context->res_ctx.pipe_ctx[i].ttu_regs);
++			}
++		}
++#endif
++	}
+ #endif
+ 
+ 	// Update Type FAST, Surface updates
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 8af7014b1588..bc422728dd54 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -424,6 +424,7 @@ struct dc_debug_options {
+ 
+ 	bool nv12_iflip_vm_wa;
+ 	bool disable_dram_clock_change_vactive_support;
++	bool validate_dml_output;
+ };
+ 
+ struct dc_debug_data {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+index 391f0629b955..4c60fa4b89e7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+@@ -30,6 +30,8 @@
+ #include "reg_helper.h"
+ #include "basics/conversion.h"
+ 
++#define DC_LOGGER_INIT(logger)
++
+ #define REG(reg)\
+ 	hubp2->hubp_regs->reg
+ 
+@@ -1246,6 +1248,313 @@ void hubp2_read_state(struct hubp *hubp)
+ 
+ }
+ 
++void hubp2_validate_dml_output(struct hubp *hubp,
++		struct dc_context *ctx,
++		struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
++		struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
++		struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr)
++{
++	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
++	struct _vcs_dpi_display_rq_regs_st rq_regs = {0};
++	struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0};
++	struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0};
++	DC_LOGGER_INIT(ctx->logger);
++
++	/* Requestor Regs */
++	REG_GET(HUBPRET_CONTROL,
++		DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address);
++	REG_GET_4(DCN_EXPANSION_MODE,
++		DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode,
++		PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode,
++		MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode,
++		CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode);
++	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
++		CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,
++		MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size,
++		META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size,
++		MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size,
++		DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size,
++		MPTE_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size,
++		SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height,
++		PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear);
++	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
++		CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size,
++		MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size,
++		META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size,
++		MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size,
++		DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size,
++		MPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.mpte_group_size,
++		SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height,
++		PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear);
++
++	if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address)
++		DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u  Actual: %u\n",
++				dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address);
++	if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode)
++		DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
++				dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode);
++	if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode)
++		DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
++				dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode);
++	if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode)
++		DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u  Actual: %u\n",
++				dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode);
++	if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode)
++		DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
++				dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode);
++
++	if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size);
++	if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size);
++	if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size);
++	if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size);
++	if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size);
++	if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MPTE_GROUP_SIZE - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size);
++	if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height);
++	if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear);
++
++	if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size);
++	if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size);
++	if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size);
++	if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size);
++	if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size);
++	if (rq_regs.rq_regs_c.mpte_group_size != dml_rq_regs->rq_regs_c.mpte_group_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MPTE_GROUP_SIZE_C - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_c.mpte_group_size, rq_regs.rq_regs_c.mpte_group_size);
++	if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height);
++	if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear);
++
++	/* DLG - Per hubp */
++	REG_GET_2(BLANK_OFFSET_0,
++		REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end,
++		DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end);
++	REG_GET(BLANK_OFFSET_1,
++		MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start);
++	REG_GET(DST_DIMENSIONS,
++		REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal);
++	REG_GET_2(DST_AFTER_SCALER,
++		REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler,
++		DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler);
++	REG_GET(REF_FREQ_TO_PIX_FREQ,
++		REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq);
++
++	if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end)
++		DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end);
++	if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end)
++		DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end);
++	if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start)
++		DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start);
++	if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal)
++		DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal);
++	if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler)
++		DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler);
++	if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler)
++		DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler);
++	if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq)
++		DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq);
++
++	/* DLG - Per luma/chroma */
++	REG_GET(VBLANK_PARAMETERS_1,
++		REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l);
++	if (REG(NOM_PARAMETERS_0))
++		REG_GET(NOM_PARAMETERS_0,
++			DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l);
++	if (REG(NOM_PARAMETERS_1))
++		REG_GET(NOM_PARAMETERS_1,
++			REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l);
++	REG_GET(NOM_PARAMETERS_4,
++		DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l);
++	REG_GET(NOM_PARAMETERS_5,
++		REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l);
++	REG_GET_2(PER_LINE_DELIVERY,
++		REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l,
++		REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c);
++	REG_GET_2(PER_LINE_DELIVERY_PRE,
++		REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l,
++		REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c);
++	REG_GET(VBLANK_PARAMETERS_2,
++		REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c);
++	if (REG(NOM_PARAMETERS_2))
++		REG_GET(NOM_PARAMETERS_2,
++			DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c);
++	if (REG(NOM_PARAMETERS_3))
++		REG_GET(NOM_PARAMETERS_3,
++			REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c);
++	REG_GET(NOM_PARAMETERS_6,
++		DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c);
++	REG_GET(NOM_PARAMETERS_7,
++		REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c);
++	REG_GET(VBLANK_PARAMETERS_3,
++			REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l);
++	REG_GET(VBLANK_PARAMETERS_4,
++			REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c);
++
++	if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l)
++		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l);
++	if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l)
++		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l);
++	if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l)
++		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l);
++	if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l)
++		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l);
++	if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l)
++		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l);
++	if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l)
++		DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l);
++	if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c)
++		DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c);
++	if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c)
++		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c);
++	if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c)
++		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c);
++	if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c)
++		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c);
++	if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c)
++		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c);
++	if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c)
++		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c);
++	if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l)
++		DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l);
++	if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c)
++		DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c);
++	if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l)
++		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l);
++	if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c)
++		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c);
++
++	/* TTU - per hubp */
++	REG_GET_2(DCN_TTU_QOS_WM,
++		QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm,
++		QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm);
++
++	if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm)
++		DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm);
++	if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm)
++		DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm);
++
++	/* TTU - per luma/chroma */
++	/* Assumed surf0 is luma and 1 is chroma */
++	REG_GET_3(DCN_SURF0_TTU_CNTL0,
++		REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l,
++		QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l,
++		QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l);
++	REG_GET_3(DCN_SURF1_TTU_CNTL0,
++		REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c,
++		QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c,
++		QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c);
++	REG_GET_3(DCN_CUR0_TTU_CNTL0,
++		REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0,
++		QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0,
++		QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0);
++	REG_GET(FLIP_PARAMETERS_1,
++		REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l);
++	REG_GET(DCN_CUR0_TTU_CNTL1,
++			REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0);
++	REG_GET(DCN_CUR1_TTU_CNTL1,
++			REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1);
++	REG_GET(DCN_SURF0_TTU_CNTL1,
++			REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l);
++	REG_GET(DCN_SURF1_TTU_CNTL1,
++			REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c);
++
++	if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l)
++		DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l);
++	if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l)
++		DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l);
++	if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l)
++		DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l);
++	if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c)
++		DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c);
++	if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c)
++		DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c);
++	if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c)
++		DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c);
++	if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0)
++		DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0);
++	if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0)
++		DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0);
++	if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0)
++		DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0);
++	if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l)
++		DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l);
++	if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0)
++		DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0);
++	if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1)
++		DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1);
++	if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l)
++		DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l);
++	if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c)
++		DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c);
++}
++
+ static struct hubp_funcs dcn20_hubp_funcs = {
+ 	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
+ 	.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
+@@ -1269,6 +1578,7 @@ static struct hubp_funcs dcn20_hubp_funcs = {
+ 	.hubp_clear_underflow = hubp2_clear_underflow,
+ 	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
+ 	.hubp_init = hubp1_init,
++	.validate_dml_output = hubp2_validate_dml_output,
+ };
+ 
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+index 32e8b589aeb5..0be1c917b242 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+@@ -29,6 +29,8 @@
+ #include "dm_services.h"
+ #include "reg_helper.h"
+ 
++#define DC_LOGGER_INIT(logger)
++
+ #define REG(reg)\
+ 	hubp21->hubp_regs->reg
+ 
+@@ -254,6 +256,348 @@ void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,
+ 			SYSTEM_ACCESS_MODE, 0x3);
+ }
+ 
++void hubp21_validate_dml_output(struct hubp *hubp,
++		struct dc_context *ctx,
++		struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
++		struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
++		struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr)
++{
++	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
++	struct _vcs_dpi_display_rq_regs_st rq_regs = {0};
++	struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0};
++	struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0};
++	DC_LOGGER_INIT(ctx->logger);
++
++	/* Requester - Per hubp */
++	REG_GET(HUBPRET_CONTROL,
++		DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address);
++	REG_GET_4(DCN_EXPANSION_MODE,
++		DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode,
++		PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode,
++		MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode,
++		CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode);
++	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
++		CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,
++		MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size,
++		META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size,
++		MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size,
++		DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size,
++		VM_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size,
++		SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height,
++		PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear);
++	REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C,
++		CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size,
++		MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size,
++		META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size,
++		MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size,
++		DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size,
++		SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height,
++		PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear);
++
++	if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address)
++		DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u  Actual: %u\n",
++				dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address);
++	if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode)
++		DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
++				dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode);
++	if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode)
++		DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
++				dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode);
++	if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode)
++		DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u  Actual: %u\n",
++				dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode);
++	if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode)
++		DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
++				dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode);
++
++	if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size);
++	if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size);
++	if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size);
++	if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size);
++	if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size);
++	if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:VM_GROUP_SIZE - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size);
++	if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height);
++	if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear);
++
++	if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size);
++	if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size);
++	if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size);
++	if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size);
++	if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size);
++	if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height);
++	if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear)
++		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u  Actual: %u\n",
++				dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear);
++
++
++	/* DLG - Per hubp */
++	REG_GET_2(BLANK_OFFSET_0,
++		REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end,
++		DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end);
++	REG_GET(BLANK_OFFSET_1,
++		MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start);
++	REG_GET(DST_DIMENSIONS,
++		REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal);
++	REG_GET_2(DST_AFTER_SCALER,
++		REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler,
++		DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler);
++	REG_GET(REF_FREQ_TO_PIX_FREQ,
++		REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq);
++
++	if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end)
++		DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end);
++	if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end)
++		DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end);
++	if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start)
++		DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start);
++	if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal)
++		DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal);
++	if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler)
++		DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler);
++	if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler)
++		DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler);
++	if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq)
++		DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq);
++
++	/* DLG - Per luma/chroma */
++	REG_GET(VBLANK_PARAMETERS_1,
++		REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l);
++	if (REG(NOM_PARAMETERS_0))
++		REG_GET(NOM_PARAMETERS_0,
++			DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l);
++	if (REG(NOM_PARAMETERS_1))
++		REG_GET(NOM_PARAMETERS_1,
++			REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l);
++	REG_GET(NOM_PARAMETERS_4,
++		DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l);
++	REG_GET(NOM_PARAMETERS_5,
++		REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l);
++	REG_GET_2(PER_LINE_DELIVERY,
++		REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l,
++		REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c);
++	REG_GET_2(PER_LINE_DELIVERY_PRE,
++		REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l,
++		REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c);
++	REG_GET(VBLANK_PARAMETERS_2,
++		REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c);
++	if (REG(NOM_PARAMETERS_2))
++		REG_GET(NOM_PARAMETERS_2,
++			DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c);
++	if (REG(NOM_PARAMETERS_3))
++		REG_GET(NOM_PARAMETERS_3,
++			REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c);
++	REG_GET(NOM_PARAMETERS_6,
++		DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c);
++	REG_GET(NOM_PARAMETERS_7,
++		REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c);
++	REG_GET(VBLANK_PARAMETERS_3,
++			REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l);
++	REG_GET(VBLANK_PARAMETERS_4,
++			REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c);
++
++	if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l)
++		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l);
++	if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l)
++		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l);
++	if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l)
++		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l);
++	if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l)
++		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l);
++	if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l)
++		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l);
++	if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l)
++		DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l);
++	if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c)
++		DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c);
++	if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c)
++		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c);
++	if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c)
++		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c);
++	if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c)
++		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c);
++	if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c)
++		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c);
++	if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c)
++		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c);
++	if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l)
++		DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l);
++	if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c)
++		DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c);
++	if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l)
++		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l);
++	if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c)
++		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c);
++
++	/* TTU - per hubp */
++	REG_GET_2(DCN_TTU_QOS_WM,
++		QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm,
++		QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm);
++
++	if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm)
++		DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm);
++	if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm)
++		DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm);
++
++	/* TTU - per luma/chroma */
++	/* Assumed surf0 is luma and 1 is chroma */
++	REG_GET_3(DCN_SURF0_TTU_CNTL0,
++		REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l,
++		QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l,
++		QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l);
++	REG_GET_3(DCN_SURF1_TTU_CNTL0,
++		REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c,
++		QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c,
++		QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c);
++	REG_GET_3(DCN_CUR0_TTU_CNTL0,
++		REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0,
++		QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0,
++		QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0);
++	REG_GET(FLIP_PARAMETERS_1,
++		REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l);
++	REG_GET(DCN_CUR0_TTU_CNTL1,
++			REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0);
++	REG_GET(DCN_CUR1_TTU_CNTL1,
++			REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1);
++	REG_GET(DCN_SURF0_TTU_CNTL1,
++			REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l);
++	REG_GET(DCN_SURF1_TTU_CNTL1,
++			REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c);
++
++	if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l)
++		DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l);
++	if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l)
++		DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l);
++	if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l)
++		DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l);
++	if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c)
++		DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c);
++	if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c)
++		DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c);
++	if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c)
++		DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c);
++	if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0)
++		DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0);
++	if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0)
++		DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0);
++	if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0)
++		DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0);
++	if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l)
++		DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l);
++	if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0)
++		DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0);
++	if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1)
++		DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1);
++	if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l)
++		DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l);
++	if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c)
++		DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
++				dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c);
++
++	/* Host VM deadline regs */
++	REG_GET(VBLANK_PARAMETERS_5,
++		REFCYC_PER_VM_GROUP_VBLANK, &dlg_attr.refcyc_per_vm_group_vblank);
++	REG_GET(VBLANK_PARAMETERS_6,
++		REFCYC_PER_VM_REQ_VBLANK, &dlg_attr.refcyc_per_vm_req_vblank);
++	REG_GET(FLIP_PARAMETERS_3,
++		REFCYC_PER_VM_GROUP_FLIP, &dlg_attr.refcyc_per_vm_group_flip);
++	REG_GET(FLIP_PARAMETERS_4,
++		REFCYC_PER_VM_REQ_FLIP, &dlg_attr.refcyc_per_vm_req_flip);
++	REG_GET(FLIP_PARAMETERS_5,
++		REFCYC_PER_PTE_GROUP_FLIP_C, &dlg_attr.refcyc_per_pte_group_flip_c);
++	REG_GET(FLIP_PARAMETERS_6,
++		REFCYC_PER_META_CHUNK_FLIP_C, &dlg_attr.refcyc_per_meta_chunk_flip_c);
++	REG_GET(FLIP_PARAMETERS_2,
++		REFCYC_PER_META_CHUNK_FLIP_L, &dlg_attr.refcyc_per_meta_chunk_flip_l);
++
++	if (dlg_attr.refcyc_per_vm_group_vblank != dml_dlg_attr->refcyc_per_vm_group_vblank)
++		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_5:REFCYC_PER_VM_GROUP_VBLANK - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_vm_group_vblank, dlg_attr.refcyc_per_vm_group_vblank);
++	if (dlg_attr.refcyc_per_vm_req_vblank != dml_dlg_attr->refcyc_per_vm_req_vblank)
++		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_6:REFCYC_PER_VM_REQ_VBLANK - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_vm_req_vblank, dlg_attr.refcyc_per_vm_req_vblank);
++	if (dlg_attr.refcyc_per_vm_group_flip != dml_dlg_attr->refcyc_per_vm_group_flip)
++		DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_3:REFCYC_PER_VM_GROUP_FLIP - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_vm_group_flip, dlg_attr.refcyc_per_vm_group_flip);
++	if (dlg_attr.refcyc_per_vm_req_flip != dml_dlg_attr->refcyc_per_vm_req_flip)
++		DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_4:REFCYC_PER_VM_REQ_FLIP - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_vm_req_flip, dlg_attr.refcyc_per_vm_req_flip);
++	if (dlg_attr.refcyc_per_pte_group_flip_c != dml_dlg_attr->refcyc_per_pte_group_flip_c)
++		DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_5:REFCYC_PER_PTE_GROUP_FLIP_C - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_pte_group_flip_c, dlg_attr.refcyc_per_pte_group_flip_c);
++	if (dlg_attr.refcyc_per_meta_chunk_flip_c != dml_dlg_attr->refcyc_per_meta_chunk_flip_c)
++		DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_6:REFCYC_PER_META_CHUNK_FLIP_C - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_meta_chunk_flip_c, dlg_attr.refcyc_per_meta_chunk_flip_c);
++	if (dlg_attr.refcyc_per_meta_chunk_flip_l != dml_dlg_attr->refcyc_per_meta_chunk_flip_l)
++		DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_2:REFCYC_PER_META_CHUNK_FLIP_L - Expected: %u  Actual: %u\n",
++				dml_dlg_attr->refcyc_per_meta_chunk_flip_l, dlg_attr.refcyc_per_meta_chunk_flip_l);
++}
++
+ void hubp21_init(struct hubp *hubp)
+ {
+ 	// DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta
+@@ -286,6 +630,7 @@ static struct hubp_funcs dcn21_hubp_funcs = {
+ 	.hubp_clear_underflow = hubp1_clear_underflow,
+ 	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
+ 	.hubp_init = hubp21_init,
++	.validate_dml_output = hubp21_validate_dml_output,
+ };
+ 
+ bool hubp21_construct(
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+index 809b62b51a43..9def990d40a6 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+@@ -161,6 +161,13 @@ struct hubp_funcs {
+ 		bool enable);
+ #endif
+ 
++	void (*validate_dml_output)(
++			struct hubp *hubp,
++			struct dc_context *ctx,
++			struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
++			struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
++			struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr);
++
+ };
+ 
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4496-drm-amd-display-Spin-for-DMCUB-PHY-init-in-DC.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4496-drm-amd-display-Spin-for-DMCUB-PHY-init-in-DC.patch
new file mode 100644
index 00000000..c4ce7cb3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4496-drm-amd-display-Spin-for-DMCUB-PHY-init-in-DC.patch
@@ -0,0 +1,62 @@
+From c56c8bc443366b91351ad9f2f248b09fdc6da1da Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 5 Nov 2019 12:51:51 -0500
+Subject: [PATCH 4496/4736] drm/amd/display: Spin for DMCUB PHY init in DC
+
+[Why]
+DCN will hang if we access registers before PHY init is done.
+
+So we need to spin or abort.
+
+[How]
+On hardware with DMCUB running and working we shouldn't time out
+waiting for this to finish and we shouldn't hit the spin cycle.
+
+If there's no hardware support then we should exit out of the function
+early assuming that PHY init was already done elsewhere.
+
+If we hit the timeout then there's likely a bug in firmware or software
+and we need to debug - add errors and asserts as appropriate.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 21 ++++++++++++++++----
+ 1 file changed, 17 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+index 74ffe53eb49d..03e2842cb573 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+@@ -112,10 +112,23 @@ void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv)
+ 	struct dc_context *dc_ctx = dc_dmub_srv->ctx;
+ 	enum dmub_status status;
+ 
+-	status = dmub_srv_wait_for_phy_init(dmub, 10000000);
+-	if (status != DMUB_STATUS_OK) {
+-		DC_ERROR("Error waiting for DMUB phy init: status=%d\n",
+-			 status);
++	for (;;) {
++		/* Wait up to a second for PHY init. */
++		status = dmub_srv_wait_for_phy_init(dmub, 1000000);
++		if (status == DMUB_STATUS_OK)
++			/* Initialization OK */
++			break;
++
++		DC_ERROR("DMCUB PHY init failed: status=%d\n", status);
+ 		ASSERT(0);
++
++		if (status != DMUB_STATUS_TIMEOUT)
++			/*
++			 * Server likely initialized or we don't have
++			 * DMCUB HW support - this won't end.
++			 */
++			break;
++
++		/* Continue spinning so we don't hang the ASIC. */
+ 	}
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4497-drm-amd-display-Add-DSC-422Native-debug-option.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4497-drm-amd-display-Add-DSC-422Native-debug-option.patch
new file mode 100644
index 00000000..4ffe87de
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4497-drm-amd-display-Add-DSC-422Native-debug-option.patch
@@ -0,0 +1,61 @@
+From ac153fe111ca34f00f37d17b89a4c2c3a700650d Mon Sep 17 00:00:00 2001
+From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Date: Thu, 3 Oct 2019 17:35:32 -0400
+Subject: [PATCH 4497/4736] drm/amd/display: Add DSC 422Native debug option
+
+[Why]
+Need to be able to enable native 422 for debugging purposes.
+
+[How]
+Add new dc_debug_options bool and check it in the get_dsc_enc_caps
+function.
+
+Change-Id: I4acc72d0faf363ef1b278708db94f353471c5d01
+Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h         | 1 +
+ drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 6 +++++-
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index bc422728dd54..18fdd61a606b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -368,6 +368,7 @@ struct dc_debug_options {
+ 	bool disable_dsc_power_gate;
+ 	int dsc_min_slice_height_override;
+ #endif
++	bool native422_support;
+ 	bool disable_pplib_wm_range;
+ 	enum wm_report_mode pplib_wm_report_mode;
+ 	unsigned int min_disp_clk_khz;
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+index e60f760585e4..f76a72a96631 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+@@ -26,6 +26,7 @@
+ #include "dc_hw_types.h"
+ #include "dsc.h"
+ #include <drm/drm_dp_helper.h>
++#include "dc.h"
+ 
+ struct dc_dsc_policy {
+ 	bool use_min_slices_h;
+@@ -237,8 +238,11 @@ static void get_dsc_enc_caps(
+ 	// This is a static HW query, so we can use any DSC
+ 
+ 	memset(dsc_enc_caps, 0, sizeof(struct dsc_enc_caps));
+-	if (dsc)
++	if (dsc) {
+ 		dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz);
++		if (dsc->ctx->dc->debug.native422_support)
++			dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1;
++	}
+ }
+ 
+ /* Returns 'false' if no intersection was found for at least one capablity.
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4498-drm-amd-display-Add-Navi10-DMUB-VBIOS-code.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4498-drm-amd-display-Add-Navi10-DMUB-VBIOS-code.patch
new file mode 100644
index 00000000..6ed8e5ec
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4498-drm-amd-display-Add-Navi10-DMUB-VBIOS-code.patch
@@ -0,0 +1,45 @@
+From 7557fd5567be9994f4235ca9a074145b8067ce77 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Mon, 4 Nov 2019 15:36:16 -0500
+Subject: [PATCH 4498/4736] drm/amd/display: Add Navi10 DMUB VBIOS code
+
+[Why]
+We need some extra dmub_cmd_type for NV10
+
+[How]
+Add command table functions in DMUB firmware.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Xiong Yan <Xiong.Yan@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+---
+ drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+index b25f92e3280d..43f1cd647aab 100644
+--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+@@ -45,6 +45,17 @@ enum dmub_cmd_type {
+ 	DMUB_CMD__ENABLE_DISP_POWER_GATING,
+ 	DMUB_CMD__DPPHY_INIT,
+ 	DMUB_CMD__DIG1_TRANSMITTER_CONTROL,
++	DMUB_CMD__SETUP_DISPLAY_MODE,
++	DMUB_CMD__BLANK_CRTC,
++	DMUB_CMD__ENABLE_DISPPATH,
++	DMUB_CMD__DISABLE_DISPPATH,
++	DMUB_CMD__DISABLE_DISPPATH_OUTPUT,
++	DMUB_CMD__READ_DISPPATH_EDID,
++	DMUB_CMD__DP_PRE_LINKTRAINING,
++	DMUB_CMD__INIT_CONTROLLER,
++	DMUB_CMD__RESET_CONTROLLER,
++	DMUB_CMD__SET_BRI_LEVEL,
++	DMUB_CMD__LVTMA_CONTROL,
+ 
+ 	// PSR
+ 	DMUB_CMD__PSR_ENABLE,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4499-drm-amd-display-add-automated-audio-test-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4499-drm-amd-display-add-automated-audio-test-support.patch
new file mode 100644
index 00000000..38ff0e30
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4499-drm-amd-display-add-automated-audio-test-support.patch
@@ -0,0 +1,234 @@
+From c8b372b25d04f3b1747ce7df0680b109740d9f0f Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Fri, 26 Jul 2019 11:25:43 -0400
+Subject: [PATCH 4499/4736] drm/amd/display: add automated audio test support
+
+Change-Id: I2b01c053888b2bb3e1f117af591c8dd3f3a36111
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 92 +++++++++++++++++++
+ drivers/gpu/drm/amd/display/dc/dc_dp_types.h  | 48 ++++++++--
+ drivers/gpu/drm/amd/display/dc/dc_link.h      |  1 +
+ include/drm/drm_dp_helper.h                   | 15 +++
+ 4 files changed, 149 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 4e0ca8d1b484..a32626864154 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2568,6 +2568,92 @@ static void dp_test_send_link_test_pattern(struct dc_link *link)
+ 			0);
+ }
+ 
++static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
++{
++	union audio_test_mode            dpcd_test_mode = {0};
++	struct audio_test_pattern_type   dpcd_pattern_type = {0};
++	union audio_test_pattern_period  dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
++	enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
++
++	struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
++	struct pipe_ctx *pipe_ctx = &pipes[0];
++	unsigned int channel_count;
++	unsigned int channel = 0;
++	unsigned int modes = 0;
++	unsigned int sampling_rate_in_hz = 0;
++
++	// get audio test mode and test pattern parameters
++	core_link_read_dpcd(
++		link,
++		DP_TEST_AUDIO_MODE,
++		&dpcd_test_mode.raw,
++		sizeof(dpcd_test_mode));
++
++	core_link_read_dpcd(
++		link,
++		DP_TEST_AUDIO_PATTERN_TYPE,
++		&dpcd_pattern_type.value,
++		sizeof(dpcd_pattern_type));
++
++	channel_count = dpcd_test_mode.bits.channel_count + 1;
++
++	// read pattern periods for requested channels when sawTooth pattern is requested
++	if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
++			dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
++
++		test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
++				DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
++		// read period for each channel
++		for (channel = 0; channel < channel_count; channel++) {
++			core_link_read_dpcd(
++							link,
++							DP_TEST_AUDIO_PERIOD_CH1 + channel,
++							&dpcd_pattern_period[channel].raw,
++							sizeof(dpcd_pattern_period[channel]));
++		}
++	}
++
++	// translate sampling rate
++	switch (dpcd_test_mode.bits.sampling_rate) {
++	case AUDIO_SAMPLING_RATE_32KHZ:
++		sampling_rate_in_hz = 32000;
++		break;
++	case AUDIO_SAMPLING_RATE_44_1KHZ:
++		sampling_rate_in_hz = 44100;
++		break;
++	case AUDIO_SAMPLING_RATE_48KHZ:
++		sampling_rate_in_hz = 48000;
++		break;
++	case AUDIO_SAMPLING_RATE_88_2KHZ:
++		sampling_rate_in_hz = 88200;
++		break;
++	case AUDIO_SAMPLING_RATE_96KHZ:
++		sampling_rate_in_hz = 96000;
++		break;
++	case AUDIO_SAMPLING_RATE_176_4KHZ:
++		sampling_rate_in_hz = 176400;
++		break;
++	case AUDIO_SAMPLING_RATE_192KHZ:
++		sampling_rate_in_hz = 192000;
++		break;
++	default:
++		sampling_rate_in_hz = 0;
++		break;
++	}
++
++	link->audio_test_data.flags.test_requested = 1;
++	link->audio_test_data.flags.disable_video = disable_video;
++	link->audio_test_data.sampling_rate = sampling_rate_in_hz;
++	link->audio_test_data.channel_count = channel_count;
++	link->audio_test_data.pattern_type = test_pattern;
++
++	if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
++		for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
++			link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
++		}
++	}
++}
++
+ static void handle_automated_test(struct dc_link *link)
+ {
+ 	union test_request test_request;
+@@ -2597,6 +2683,12 @@ static void handle_automated_test(struct dc_link *link)
+ 		dp_test_send_link_test_pattern(link);
+ 		test_response.bits.ACK = 1;
+ 	}
++
++	if (test_request.bits.AUDIO_TEST_PATTERN) {
++		dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
++		test_response.bits.ACK = 1;
++	}
++
+ 	if (test_request.bits.PHY_TEST_PATTERN) {
+ 		dp_test_send_phy_test_pattern(link);
+ 		test_response.bits.ACK = 1;
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+index f0a6e25d2d4a..28234d8fdb2c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+@@ -471,13 +471,13 @@ union training_aux_rd_interval {
+ /* Automated test structures */
+ union test_request {
+ 	struct {
+-	uint8_t LINK_TRAINING         :1;
+-	uint8_t LINK_TEST_PATTRN      :1;
+-	uint8_t EDID_READ             :1;
+-	uint8_t PHY_TEST_PATTERN      :1;
+-	uint8_t AUDIO_TEST_PATTERN    :1;
+-	uint8_t RESERVED              :1;
+-	uint8_t TEST_STEREO_3D        :1;
++	uint8_t LINK_TRAINING                :1;
++	uint8_t LINK_TEST_PATTRN             :1;
++	uint8_t EDID_READ                    :1;
++	uint8_t PHY_TEST_PATTERN             :1;
++	uint8_t RESERVED                     :1;
++	uint8_t AUDIO_TEST_PATTERN           :1;
++	uint8_t TEST_AUDIO_DISABLED_VIDEO    :1;
+ 	} bits;
+ 	uint8_t raw;
+ };
+@@ -536,6 +536,40 @@ union test_misc {
+ 	unsigned char raw;
+ };
+ 
++union audio_test_mode {
++	struct {
++		unsigned char sampling_rate   :4;
++		unsigned char channel_count   :4;
++	} bits;
++	unsigned char raw;
++};
++
++union audio_test_pattern_period {
++	struct {
++		unsigned char pattern_period   :4;
++		unsigned char reserved         :4;
++	} bits;
++	unsigned char raw;
++};
++
++struct audio_test_pattern_type {
++	unsigned char value;
++};
++
++struct dp_audio_test_data_flags {
++	uint8_t test_requested  :1;
++	uint8_t disable_video   :1;
++};
++
++struct dp_audio_test_data {
++
++	struct dp_audio_test_data_flags flags;
++	uint8_t sampling_rate;
++	uint8_t channel_count;
++	uint8_t pattern_type;
++	uint8_t pattern_period[8];
++};
++
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* FEC capability DPCD register field bits-*/
+ union dpcd_fec_capability {
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
+index ccb68c14a806..03efdc1a7b03 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
+@@ -96,6 +96,7 @@ struct dc_link {
+ 	struct dc_lane_settings cur_lane_setting;
+ 	struct dc_link_settings preferred_link_setting;
+ 	struct dc_link_training_overrides preferred_training_settings;
++	struct dp_audio_test_data audio_test_data;
+ 
+ 	uint8_t ddc_hw_inst;
+ 
+diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
+index 4f9184a238dd..5de6fa29300e 100644
+--- a/include/drm/drm_dp_helper.h
++++ b/include/drm/drm_dp_helper.h
+@@ -61,6 +61,21 @@
+ #define DP_AUX_I2C_REPLY_DEFER		(0x2 << 2)
+ #define DP_AUX_I2C_REPLY_MASK		(0x3 << 2)
+ 
++
++#if !defined(DP_TEST_AUDIO_MODE)
++#define DP_TEST_AUDIO_MODE                 0x271
++#endif
++
++#if !defined(DP_TEST_AUDIO_PATTERN_TYPE)
++#define DP_TEST_AUDIO_PATTERN_TYPE         0x272
++#endif
++
++#if !defined(DP_TEST_AUDIO_PERIOD_CH1)
++#define DP_TEST_AUDIO_PERIOD_CH1           0x273
++#endif
++
++
++
+ /* AUX CH addresses */
+ /* DPCD */
+ #define DP_DPCD_REV                         0x000
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4500-drm-amd-display-Add-PSP-block-to-verify-HDCP2.2-step.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4500-drm-amd-display-Add-PSP-block-to-verify-HDCP2.2-step.patch
new file mode 100644
index 00000000..42e9d2af
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4500-drm-amd-display-Add-PSP-block-to-verify-HDCP2.2-step.patch
@@ -0,0 +1,863 @@
+From 960ca96c1baf29d4050e20323e0a8ac78b018125 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 18 Sep 2019 11:19:51 -0400
+Subject: [PATCH 4500/4736] drm/amd/display: Add PSP block to verify HDCP2.2
+ steps
+
+[Why]
+All the HDCP transactions should be verified using PSP
+
+[How]
+This patch adds the psp calls we need to verify the steps
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../gpu/drm/amd/display/modules/hdcp/hdcp.h   |  44 ++
+ .../drm/amd/display/modules/hdcp/hdcp_psp.c   | 502 +++++++++++++++++-
+ .../drm/amd/display/modules/hdcp/hdcp_psp.h   | 194 +++++++
+ 3 files changed, 739 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+index 5664bc0b5bd0..d83f0ab1cadb 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+@@ -111,8 +111,33 @@ struct mod_hdcp_message_hdcp1 {
+ 	uint16_t	binfo_dp;
+ };
+ 
++struct mod_hdcp_message_hdcp2 {
++	uint8_t		hdcp2version_hdmi;
++	uint8_t		rxcaps_dp[3];
++	uint16_t	rxstatus;
++
++	uint8_t		ake_init[12];
++	uint8_t		ake_cert[534];
++	uint8_t		ake_no_stored_km[129];
++	uint8_t		ake_stored_km[33];
++	uint8_t		ake_h_prime[33];
++	uint8_t		ake_pairing_info[17];
++	uint8_t		lc_init[9];
++	uint8_t		lc_l_prime[33];
++	uint8_t		ske_eks[25];
++	uint8_t		rx_id_list[177]; // 22 + 5 * 31
++	uint16_t	rx_id_list_size;
++	uint8_t		repeater_auth_ack[17];
++	uint8_t		repeater_auth_stream_manage[68]; // 6 + 2 * 31
++	uint16_t	stream_manage_size;
++	uint8_t		repeater_auth_stream_ready[33];
++
++	uint8_t		content_stream_type_dp[2];
++};
++
+ union mod_hdcp_message {
+ 	struct mod_hdcp_message_hdcp1 hdcp1;
++	struct mod_hdcp_message_hdcp2 hdcp2;
+ };
+ 
+ struct mod_hdcp_auth_counters {
+@@ -234,6 +259,25 @@ enum mod_hdcp_status mod_hdcp_hdcp1_enable_dp_stream_encryption(
+ enum mod_hdcp_status mod_hdcp_hdcp1_link_maintenance(struct mod_hdcp *hdcp);
+ enum mod_hdcp_status mod_hdcp_hdcp1_get_link_encryption_status(struct mod_hdcp *hdcp,
+ 							       enum mod_hdcp_encryption_status *encryption_status);
++enum mod_hdcp_status mod_hdcp_hdcp2_create_session(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_destroy_session(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_prepare_ake_init(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_ake_cert(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_h_prime(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_prepare_lc_init(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_l_prime(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_prepare_eks(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_enable_encryption(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_rx_id_list(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_enable_dp_stream_encryption(
++		struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_prepare_stream_management(
++		struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_stream_ready(
++		struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_hdcp2_get_link_encryption_status(struct mod_hdcp *hdcp,
++							       enum mod_hdcp_encryption_status *encryption_status);
++
+ /* ddc functions */
+ enum mod_hdcp_status mod_hdcp_read_bksv(struct mod_hdcp *hdcp);
+ enum mod_hdcp_status mod_hdcp_read_bcaps(struct mod_hdcp *hdcp);
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+index 646d909bbc37..ddba0cfa5722 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+@@ -31,6 +31,19 @@
+ #include "amdgpu.h"
+ #include "hdcp_psp.h"
+ 
++static void hdcp2_message_init(struct mod_hdcp *hdcp,
++			       struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *in)
++{
++	in->session_handle = hdcp->auth.id;
++	in->prepare.msg1_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
++	in->prepare.msg2_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
++	in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
++	in->process.msg1_desc.msg_size = 0;
++	in->process.msg2_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
++	in->process.msg2_desc.msg_size = 0;
++	in->process.msg3_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
++	in->process.msg3_desc.msg_id = 0;
++}
+ enum mod_hdcp_status mod_hdcp_remove_display_topology(struct mod_hdcp *hdcp)
+ {
+ 
+@@ -42,7 +55,7 @@ enum mod_hdcp_status mod_hdcp_remove_display_topology(struct mod_hdcp *hdcp)
+ 	dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.dtm_shared_buf;
+ 
+ 	for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++) {
+-		if (hdcp->connection.displays[i].state == MOD_HDCP_DISPLAY_ACTIVE_AND_ADDED) {
++		if (is_display_added(&(hdcp->connection.displays[i]))) {
+ 
+ 			memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory));
+ 
+@@ -326,3 +339,490 @@ enum mod_hdcp_status mod_hdcp_hdcp1_get_link_encryption_status(struct mod_hdcp *
+ 	return MOD_HDCP_STATUS_SUCCESS;
+ }
+ 
++enum mod_hdcp_status mod_hdcp_hdcp2_create_session(struct mod_hdcp *hdcp)
++{
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++	struct mod_hdcp_display *display = get_first_added_display(hdcp);
++
++	if (!psp->hdcp_context.hdcp_initialized) {
++		DRM_ERROR("Failed to create hdcp session, HDCP TA is not initialized");
++		return MOD_HDCP_STATUS_FAILURE;
++	}
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	if (!display)
++		return MOD_HDCP_STATUS_DISPLAY_NOT_FOUND;
++
++	hdcp_cmd->in_msg.hdcp2_create_session_v2.display_handle = display->index;
++
++	if (hdcp->connection.link.adjust.hdcp2.disable_type1)
++		hdcp_cmd->in_msg.hdcp2_create_session_v2.negotiate_content_type =
++			TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__FORCE_TYPE0;
++	else
++		hdcp_cmd->in_msg.hdcp2_create_session_v2.negotiate_content_type =
++			TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__MAX_SUPPORTED;
++
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_CREATE_SESSION_V2;
++
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE;
++
++	hdcp->auth.id = hdcp_cmd->out_msg.hdcp2_create_session_v2.session_handle;
++
++	return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_destroy_session(struct mod_hdcp *hdcp)
++{
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	hdcp_cmd->in_msg.hdcp2_destroy_session.session_handle = hdcp->auth.id;
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_DESTROY_SESSION;
++
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE;
++
++	return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_prepare_ake_init(struct mod_hdcp *hdcp)
++{
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++	msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++	hdcp2_message_init(hdcp, msg_in);
++
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2;
++	msg_in->prepare.msg1_id = TA_HDCP_HDCP2_MSG_ID__AKE_INIT;
++
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE;
++
++	memcpy(&hdcp->auth.msg.hdcp2.ake_init[0], &msg_out->prepare.transmitter_message[0],
++	       sizeof(hdcp->auth.msg.hdcp2.ake_init));
++
++	return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_ake_cert(struct mod_hdcp *hdcp)
++{
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++	msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++	hdcp2_message_init(hdcp, msg_in);
++
++	msg_in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__AKE_SEND_CERT;
++	msg_in->process.msg1_desc.msg_size = TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_CERT;
++
++	memcpy(&msg_in->process.receiver_message[0], hdcp->auth.msg.hdcp2.ake_cert,
++	       sizeof(hdcp->auth.msg.hdcp2.ake_cert));
++
++	msg_in->prepare.msg1_id = TA_HDCP_HDCP2_MSG_ID__AKE_NO_STORED_KM;
++	msg_in->prepare.msg2_id = TA_HDCP_HDCP2_MSG_ID__AKE_STORED_KM;
++
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2;
++
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE;
++
++	memcpy(hdcp->auth.msg.hdcp2.ake_no_stored_km, &msg_out->prepare.transmitter_message[0],
++	       sizeof(hdcp->auth.msg.hdcp2.ake_no_stored_km));
++
++	memcpy(hdcp->auth.msg.hdcp2.ake_stored_km,
++	       &msg_out->prepare.transmitter_message[sizeof(hdcp->auth.msg.hdcp2.ake_no_stored_km)],
++	       sizeof(hdcp->auth.msg.hdcp2.ake_stored_km));
++
++	if (msg_out->process.msg1_status == TA_HDCP2_MSG_AUTHENTICATION_STATUS__SUCCESS) {
++		hdcp->connection.is_km_stored = msg_out->process.is_km_stored ? 1 : 0;
++		hdcp->connection.is_repeater = msg_out->process.is_repeater ? 1 : 0;
++		return MOD_HDCP_STATUS_SUCCESS;
++	}
++
++	return MOD_HDCP_STATUS_FAILURE;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_h_prime(struct mod_hdcp *hdcp)
++{
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++	msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++	hdcp2_message_init(hdcp, msg_in);
++
++	msg_in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__AKE_SEND_H_PRIME;
++	msg_in->process.msg1_desc.msg_size = TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_H_PRIME;
++
++	memcpy(&msg_in->process.receiver_message[0], hdcp->auth.msg.hdcp2.ake_h_prime,
++	       sizeof(hdcp->auth.msg.hdcp2.ake_h_prime));
++
++	if (!hdcp->connection.is_km_stored) {
++		msg_in->process.msg2_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__AKE_SEND_PAIRING_INFO;
++		msg_in->process.msg2_desc.msg_size = TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_PAIRING_INFO;
++		memcpy(&msg_in->process.receiver_message[sizeof(hdcp->auth.msg.hdcp2.ake_h_prime)],
++		       hdcp->auth.msg.hdcp2.ake_pairing_info, sizeof(hdcp->auth.msg.hdcp2.ake_pairing_info));
++	}
++
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2;
++
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE;
++
++	if (msg_out->process.msg1_status != TA_HDCP2_MSG_AUTHENTICATION_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE;
++	else if (!hdcp->connection.is_km_stored &&
++		 msg_out->process.msg2_status != TA_HDCP2_MSG_AUTHENTICATION_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE;
++
++
++	return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_prepare_lc_init(struct mod_hdcp *hdcp)
++{
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++	msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++	hdcp2_message_init(hdcp, msg_in);
++
++	msg_in->prepare.msg1_id = TA_HDCP_HDCP2_MSG_ID__LC_INIT;
++
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2;
++
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE;
++
++	memcpy(hdcp->auth.msg.hdcp2.lc_init, &msg_out->prepare.transmitter_message[0],
++	       sizeof(hdcp->auth.msg.hdcp2.lc_init));
++
++	return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_l_prime(struct mod_hdcp *hdcp)
++{
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++	msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++	hdcp2_message_init(hdcp, msg_in);
++
++	msg_in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__LC_SEND_L_PRIME;
++	msg_in->process.msg1_desc.msg_size = TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__LC_SEND_L_PRIME;
++
++	memcpy(&msg_in->process.receiver_message[0], hdcp->auth.msg.hdcp2.lc_l_prime,
++	       sizeof(hdcp->auth.msg.hdcp2.lc_l_prime));
++
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2;
++
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE;
++
++	if (msg_out->process.msg1_status != TA_HDCP2_MSG_AUTHENTICATION_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE;
++
++	return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_prepare_eks(struct mod_hdcp *hdcp)
++{
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++	msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++	hdcp2_message_init(hdcp, msg_in);
++
++	msg_in->prepare.msg1_id = TA_HDCP_HDCP2_MSG_ID__SKE_SEND_EKS;
++
++	if (is_dp_hdcp(hdcp))
++		msg_in->prepare.msg2_id = TA_HDCP_HDCP2_MSG_ID__SIGNAL_CONTENT_STREAM_TYPE_DP;
++
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2;
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE;
++
++	memcpy(hdcp->auth.msg.hdcp2.ske_eks, &msg_out->prepare.transmitter_message[0],
++	       sizeof(hdcp->auth.msg.hdcp2.ske_eks));
++	msg_out->prepare.msg1_desc.msg_size = sizeof(hdcp->auth.msg.hdcp2.ske_eks);
++
++	if (is_dp_hdcp(hdcp)) {
++		memcpy(hdcp->auth.msg.hdcp2.content_stream_type_dp,
++		       &msg_out->prepare.transmitter_message[sizeof(hdcp->auth.msg.hdcp2.ske_eks)],
++		       sizeof(hdcp->auth.msg.hdcp2.content_stream_type_dp));
++	}
++
++	return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_enable_encryption(struct mod_hdcp *hdcp)
++{
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++	struct mod_hdcp_display *display = get_first_added_display(hdcp);
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++	msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++	hdcp2_message_init(hdcp, msg_in);
++
++	if (!display)
++		return MOD_HDCP_STATUS_DISPLAY_NOT_FOUND;
++
++	hdcp_cmd->in_msg.hdcp1_enable_encryption.session_handle = hdcp->auth.id;
++
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_SET_ENCRYPTION;
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE;
++
++	if (!is_dp_mst_hdcp(hdcp)) {
++		display->state = MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;
++	}
++
++	return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_rx_id_list(struct mod_hdcp *hdcp)
++{
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++	msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++	hdcp2_message_init(hdcp, msg_in);
++
++	msg_in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_SEND_RECEIVERID_LIST;
++	msg_in->process.msg1_desc.msg_size = sizeof(hdcp->auth.msg.hdcp2.rx_id_list);
++	memcpy(&msg_in->process.receiver_message[0], hdcp->auth.msg.hdcp2.rx_id_list,
++	       sizeof(hdcp->auth.msg.hdcp2.rx_id_list));
++
++	msg_in->prepare.msg1_id = TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_SEND_ACK;
++
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2;
++
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE;
++
++	memcpy(hdcp->auth.msg.hdcp2.repeater_auth_ack, &msg_out->prepare.transmitter_message[0],
++	       sizeof(hdcp->auth.msg.hdcp2.repeater_auth_ack));
++
++	if (msg_out->process.msg1_status == TA_HDCP2_MSG_AUTHENTICATION_STATUS__SUCCESS) {
++		hdcp->connection.is_km_stored = msg_out->process.is_km_stored ? 1 : 0;
++		hdcp->connection.is_repeater = msg_out->process.is_repeater ? 1 : 0;
++		return MOD_HDCP_STATUS_SUCCESS;
++	}
++
++
++	return MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_enable_dp_stream_encryption(struct mod_hdcp *hdcp)
++{
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++	uint8_t i;
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++	msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++	hdcp2_message_init(hdcp, msg_in);
++
++
++	for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++) {
++		if (hdcp->connection.displays[i].state != MOD_HDCP_DISPLAY_ACTIVE_AND_ADDED ||
++		    hdcp->connection.displays[i].adjust.disable)
++			continue;
++		hdcp_cmd->in_msg.hdcp2_enable_dp_stream_encryption.display_handle = hdcp->connection.displays[i].index;
++		hdcp_cmd->in_msg.hdcp2_enable_dp_stream_encryption.session_handle = hdcp->auth.id;
++
++		hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_ENABLE_DP_STREAM_ENCRYPTION;
++		psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++		if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++			break;
++
++		hdcp->connection.displays[i].state = MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;
++	}
++
++	return (hdcp_cmd->hdcp_status == TA_HDCP_STATUS__SUCCESS) ? MOD_HDCP_STATUS_SUCCESS
++								  : MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_prepare_stream_management(struct mod_hdcp *hdcp)
++{
++
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++	msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++	hdcp2_message_init(hdcp, msg_in);
++
++	msg_in->prepare.msg1_id = TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_STREAM_MANAGE;
++
++
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2;
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE;
++
++	hdcp->auth.msg.hdcp2.stream_manage_size = msg_out->prepare.msg1_desc.msg_size;
++
++	memcpy(hdcp->auth.msg.hdcp2.repeater_auth_stream_manage, &msg_out->prepare.transmitter_message[0],
++	       sizeof(hdcp->auth.msg.hdcp2.repeater_auth_stream_manage));
++
++	return MOD_HDCP_STATUS_SUCCESS;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_validate_stream_ready(struct mod_hdcp *hdcp)
++{
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
++	msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
++
++	hdcp2_message_init(hdcp, msg_in);
++
++	msg_in->process.msg1_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_STREAM_READY;
++
++	msg_in->process.msg1_desc.msg_size = sizeof(hdcp->auth.msg.hdcp2.repeater_auth_stream_ready);
++
++	memcpy(&msg_in->process.receiver_message[0], hdcp->auth.msg.hdcp2.repeater_auth_stream_ready,
++	       sizeof(hdcp->auth.msg.hdcp2.repeater_auth_stream_ready));
++
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2;
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	return (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS) &&
++			       (msg_out->process.msg1_status == TA_HDCP2_MSG_AUTHENTICATION_STATUS__SUCCESS)
++		       ? MOD_HDCP_STATUS_SUCCESS
++		       : MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_get_link_encryption_status(struct mod_hdcp *hdcp,
++							       enum mod_hdcp_encryption_status *encryption_status)
++{
++	struct psp_context *psp = hdcp->config.psp.handle;
++	struct ta_hdcp_shared_memory *hdcp_cmd;
++
++	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
++
++	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
++
++	hdcp_cmd->in_msg.hdcp2_get_encryption_status.session_handle = hdcp->auth.id;
++	hdcp_cmd->out_msg.hdcp2_get_encryption_status.protection_level = 0;
++	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP2_GET_ENCRYPTION_STATUS;
++	*encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
++
++	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
++
++	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
++		return MOD_HDCP_STATUS_FAILURE;
++
++	if (hdcp_cmd->out_msg.hdcp2_get_encryption_status.protection_level == 1) {
++		if (hdcp_cmd->out_msg.hdcp2_get_encryption_status.hdcp2_type == TA_HDCP2_CONTENT_TYPE__TYPE1)
++			*encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON;
++		else
++			*encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON;
++	}
++
++	return MOD_HDCP_STATUS_SUCCESS;
++}
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
+index 986fc07ea9ea..82a5e997d573 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
+@@ -36,6 +36,11 @@ enum bgd_security_hdcp_encryption_level {
+ 	HDCP_ENCRYPTION_LEVEL__ON
+ };
+ 
++enum bgd_security_hdcp2_content_type {
++	HDCP2_CONTENT_TYPE__INVALID = 0,
++	HDCP2_CONTENT_TYPE__TYPE0,
++	HDCP2_CONTENT_TYPE__TYPE1
++};
+ enum ta_dtm_command {
+ 	TA_DTM_COMMAND__UNUSED_1 = 1,
+ 	TA_DTM_COMMAND__TOPOLOGY_UPDATE_V2,
+@@ -121,8 +126,64 @@ enum ta_hdcp_command {
+ 	TA_HDCP_COMMAND__HDCP1_ENABLE_ENCRYPTION,
+ 	TA_HDCP_COMMAND__HDCP1_ENABLE_DP_STREAM_ENCRYPTION,
+ 	TA_HDCP_COMMAND__HDCP1_GET_ENCRYPTION_STATUS,
++	TA_HDCP_COMMAND__UNUSED_1,
++	TA_HDCP_COMMAND__HDCP2_DESTROY_SESSION,
++	TA_HDCP_COMMAND__UNUSED_2,
++	TA_HDCP_COMMAND__HDCP2_SET_ENCRYPTION,
++	TA_HDCP_COMMAND__HDCP2_GET_ENCRYPTION_STATUS,
++	TA_HDCP_COMMAND__UNUSED_3,
++	TA_HDCP_COMMAND__HDCP2_CREATE_SESSION_V2,
++	TA_HDCP_COMMAND__HDCP2_PREPARE_PROCESS_AUTHENTICATION_MSG_V2,
++	TA_HDCP_COMMAND__HDCP2_ENABLE_DP_STREAM_ENCRYPTION
++};
++
++enum ta_hdcp2_msg_id {
++	TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE = 1,
++	TA_HDCP_HDCP2_MSG_ID__AKE_INIT = 2,
++	TA_HDCP_HDCP2_MSG_ID__AKE_SEND_CERT = 3,
++	TA_HDCP_HDCP2_MSG_ID__AKE_NO_STORED_KM = 4,
++	TA_HDCP_HDCP2_MSG_ID__AKE_STORED_KM = 5,
++	TA_HDCP_HDCP2_MSG_ID__AKE_SEND_RRX = 6,
++	TA_HDCP_HDCP2_MSG_ID__AKE_SEND_H_PRIME = 7,
++	TA_HDCP_HDCP2_MSG_ID__AKE_SEND_PAIRING_INFO = 8,
++	TA_HDCP_HDCP2_MSG_ID__LC_INIT = 9,
++	TA_HDCP_HDCP2_MSG_ID__LC_SEND_L_PRIME = 10,
++	TA_HDCP_HDCP2_MSG_ID__SKE_SEND_EKS = 11,
++	TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_SEND_RECEIVERID_LIST = 12,
++	TA_HDCP_HDCP2_MSG_ID__RTT_READY = 13,
++	TA_HDCP_HDCP2_MSG_ID__RTT_CHALLENGE = 14,
++	TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_SEND_ACK = 15,
++	TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_STREAM_MANAGE = 16,
++	TA_HDCP_HDCP2_MSG_ID__REPEATERAUTH_STREAM_READY = 17,
++	TA_HDCP_HDCP2_MSG_ID__RECEIVER_AUTH_STATUS = 18,
++	TA_HDCP_HDCP2_MSG_ID__AKE_TRANSMITTER_INFO = 19,
++	TA_HDCP_HDCP2_MSG_ID__AKE_RECEIVER_INFO = 20,
++	TA_HDCP_HDCP2_MSG_ID__SIGNAL_CONTENT_STREAM_TYPE_DP = 129
+ };
+ 
++enum ta_hdcp2_hdcp2_msg_id_max_size {
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__NULL_MESSAGE = 0,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_INIT = 12,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_CERT = 534,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_NO_STORED_KM = 129,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_STORED_KM = 33,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_RRX = 9,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_H_PRIME = 33,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_PAIRING_INFO = 17,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__LC_INIT = 9,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__LC_SEND_L_PRIME = 33,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__SKE_SEND_EKS = 25,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__REPEATERAUTH_SEND_RECEIVERID_LIST = 181,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__RTT_READY = 1,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__RTT_CHALLENGE = 17,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__REPEATERAUTH_SEND_RACK = 17,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__REPEATERAUTH_STREAM_MANAGE = 13,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__REPEATERAUTH_STREAM_READY = 33,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__RECEIVER_AUTH_STATUS = 4,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_TRANSMITTER_INFO = 6,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_RECEIVER_INFO = 6,
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__SIGNAL_CONTENT_STREAM_TYPE_DP = 1
++};
+ 
+ /* HDCP related enumerations */
+ /**********************************************************/
+@@ -131,6 +192,12 @@ enum ta_hdcp_command {
+ #define TA_HDCP__HDCP1_KSV_SIZE 5
+ #define TA_HDCP__HDCP1_KSV_LIST_MAX_ENTRIES 127
+ #define TA_HDCP__HDCP1_V_PRIME_SIZE 20
++#define TA_HDCP__HDCP2_TX_BUF_MAX_SIZE                                                                                 \
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_NO_STORED_KM + TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_STORED_KM + 6
++
++// 64 bits boundaries
++#define TA_HDCP__HDCP2_RX_BUF_MAX_SIZE                                                                                 \
++	TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_SEND_CERT + TA_HDCP_HDCP2_MSG_ID_MAX_SIZE__AKE_RECEIVER_INFO + 4
+ 
+ enum ta_hdcp_status {
+ 	TA_HDCP_STATUS__SUCCESS = 0x00,
+@@ -165,9 +232,47 @@ enum ta_hdcp_authentication_status {
+ 	TA_HDCP_AUTHENTICATION_STATUS__HDCP1_FIRST_PART_COMPLETE = 0x02,
+ 	TA_HDCP_AUTHENTICATION_STATUS__HDCP1_SECOND_PART_FAILED = 0x03,
+ 	TA_HDCP_AUTHENTICATION_STATUS__HDCP1_AUTHENTICATED = 0x04,
++	TA_HDCP_AUTHENTICATION_STATUS__HDCP22_AUTHENTICATION_PENDING = 0x06,
++	TA_HDCP_AUTHENTICATION_STATUS__HDCP22_AUTHENTICATION_FAILED = 0x07,
++	TA_HDCP_AUTHENTICATION_STATUS__HDCP22_AUTHENTICATED = 0x08,
+ 	TA_HDCP_AUTHENTICATION_STATUS__HDCP1_KSV_VALIDATION_FAILED = 0x09
+ };
+ 
++enum ta_hdcp2_msg_authentication_status {
++	TA_HDCP2_MSG_AUTHENTICATION_STATUS__SUCCESS = 0,
++	TA_HDCP2_MSG_AUTHENTICATION_STATUS__KM_NOT_AVAILABLE,
++	TA_HDCP2_MSG_AUTHENTICATION_STATUS__UNUSED,
++	TA_HDCP2_MSG_AUTHENTICATION_STATUS__INVALID = 100, // everything above does not fail the request
++	TA_HDCP2_MSG_AUTHENTICATION_STATUS__NOT_ENOUGH_MEMORY,
++	TA_HDCP2_MSG_AUTHENTICATION_STATUS__NOT_EXPECTED_MSG,
++	TA_HDCP2_MSG_AUTHENTICATION_STATUS__SIGNATURE_CERTIFICAT_ERROR,
++	TA_HDCP2_MSG_AUTHENTICATION_STATUS__INCORRECT_HDCP_VERSION,
++	TA_HDCP2_MSG_AUTHENTICATION_STATUS__UNKNOWN_MESSAGE,
++	TA_HDCP2_MSG_AUTHENTICATION_STATUS__INVALID_HMAC,
++	TA_HDCP2_MSG_AUTHENTICATION_STATUS__INVALID_TOPOLOGY,
++	TA_HDCP2_MSG_AUTHENTICATION_STATUS__INVALID_SEQ_NUM,
++	TA_HDCP2_MSG_AUTHENTICATION_STATUS__INVALID_SIZE,
++	TA_HDCP2_MSG_AUTHENTICATION_STATUS__INVALID_LENGTH,
++	TA_HDCP2_MSG_AUTHENTICATION_STATUS__REAUTH_REQUEST
++};
++
++enum ta_hdcp_content_type {
++	TA_HDCP2_CONTENT_TYPE__TYPE0 = 1,
++	TA_HDCP2_CONTENT_TYPE__TYPE1,
++};
++
++enum ta_hdcp_content_type_negotiation_type {
++	TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__FORCE_TYPE0 = 1,
++	TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__FORCE_TYPE1,
++	TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__MAX_SUPPORTED
++};
++
++enum ta_hdcp2_version {
++	TA_HDCP2_VERSION_UNKNOWN = 0,
++	TA_HDCP2_VERSION_2_0 = 20,
++	TA_HDCP2_VERSION_2_1 = 21,
++	TA_HDCP2_VERSION_2_2 = 22
++};
+ 
+ /* input/output structures for HDCP commands */
+ /**********************************************************/
+@@ -232,6 +337,84 @@ struct ta_hdcp_cmd_hdcp1_get_encryption_status_output {
+ 	uint32_t protection_level;
+ };
+ 
++struct ta_hdcp_cmd_hdcp2_create_session_input_v2 {
++	uint32_t display_handle;
++	enum ta_hdcp_content_type_negotiation_type negotiate_content_type;
++};
++
++struct ta_hdcp_cmd_hdcp2_create_session_output_v2 {
++	uint32_t session_handle;
++};
++
++struct ta_hdcp_cmd_hdcp2_destroy_session_input {
++	uint32_t session_handle;
++};
++
++struct ta_hdcp_cmd_hdcp2_authentication_message_v2 {
++	enum ta_hdcp2_msg_id msg_id;
++	uint32_t msg_size;
++};
++
++struct ta_hdcp_cmd_hdcp2_process_authentication_message_input_v2 {
++	struct ta_hdcp_cmd_hdcp2_authentication_message_v2 msg1_desc;
++	struct ta_hdcp_cmd_hdcp2_authentication_message_v2 msg2_desc;
++	struct ta_hdcp_cmd_hdcp2_authentication_message_v2 msg3_desc;
++	uint8_t receiver_message[TA_HDCP__HDCP2_RX_BUF_MAX_SIZE];
++};
++
++struct ta_hdcp_cmd_hdcp2_process_authentication_message_output_v2 {
++	uint32_t hdcp_version;
++	uint32_t is_km_stored;
++	uint32_t is_locality_precompute_support;
++	uint32_t is_repeater;
++	enum ta_hdcp2_msg_authentication_status msg1_status;
++	enum ta_hdcp2_msg_authentication_status msg2_status;
++	enum ta_hdcp2_msg_authentication_status msg3_status;
++};
++
++struct ta_hdcp_cmd_hdcp2_prepare_authentication_message_input_v2 {
++	enum ta_hdcp2_msg_id msg1_id;
++	enum ta_hdcp2_msg_id msg2_id;
++};
++
++struct ta_hdcp_cmd_hdcp2_prepare_authentication_message_output_v2 {
++	enum ta_hdcp2_msg_authentication_status msg1_status;
++	enum ta_hdcp2_msg_authentication_status msg2_status;
++	struct ta_hdcp_cmd_hdcp2_authentication_message_v2 msg1_desc;
++	struct ta_hdcp_cmd_hdcp2_authentication_message_v2 msg2_desc;
++	uint8_t transmitter_message[TA_HDCP__HDCP2_TX_BUF_MAX_SIZE];
++};
++
++struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 {
++	uint32_t session_handle;
++	struct ta_hdcp_cmd_hdcp2_process_authentication_message_input_v2 process;
++	struct ta_hdcp_cmd_hdcp2_prepare_authentication_message_input_v2 prepare;
++};
++
++struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 {
++	uint32_t authentication_status;
++	struct ta_hdcp_cmd_hdcp2_process_authentication_message_output_v2 process;
++	struct ta_hdcp_cmd_hdcp2_prepare_authentication_message_output_v2 prepare;
++};
++
++struct ta_hdcp_cmd_hdcp2_set_encryption_input {
++	uint32_t session_handle;
++};
++
++struct ta_hdcp_cmd_hdcp2_get_encryption_status_input {
++	uint32_t session_handle;
++};
++
++struct ta_hdcp_cmd_hdcp2_get_encryption_status_output {
++	enum ta_hdcp_content_type hdcp2_type;
++	uint32_t protection_level;
++};
++
++struct ta_hdcp_cmd_hdcp2_enable_dp_stream_encryption_input {
++	uint32_t session_handle;
++	uint32_t display_handle;
++};
++
+ /**********************************************************/
+ /* Common input structure for HDCP callbacks */
+ union ta_hdcp_cmd_input {
+@@ -242,6 +425,13 @@ union ta_hdcp_cmd_input {
+ 	struct ta_hdcp_cmd_hdcp1_enable_encryption_input hdcp1_enable_encryption;
+ 	struct ta_hdcp_cmd_hdcp1_enable_dp_stream_encryption_input hdcp1_enable_dp_stream_encryption;
+ 	struct ta_hdcp_cmd_hdcp1_get_encryption_status_input hdcp1_get_encryption_status;
++	struct ta_hdcp_cmd_hdcp2_destroy_session_input hdcp2_destroy_session;
++	struct ta_hdcp_cmd_hdcp2_set_encryption_input hdcp2_set_encryption;
++	struct ta_hdcp_cmd_hdcp2_get_encryption_status_input hdcp2_get_encryption_status;
++	struct ta_hdcp_cmd_hdcp2_create_session_input_v2 hdcp2_create_session_v2;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2
++		hdcp2_prepare_process_authentication_message_v2;
++	struct ta_hdcp_cmd_hdcp2_enable_dp_stream_encryption_input hdcp2_enable_dp_stream_encryption;
+ };
+ 
+ /* Common output structure for HDCP callbacks */
+@@ -250,6 +440,10 @@ union ta_hdcp_cmd_output {
+ 	struct ta_hdcp_cmd_hdcp1_first_part_authentication_output hdcp1_first_part_authentication;
+ 	struct ta_hdcp_cmd_hdcp1_second_part_authentication_output hdcp1_second_part_authentication;
+ 	struct ta_hdcp_cmd_hdcp1_get_encryption_status_output hdcp1_get_encryption_status;
++	struct ta_hdcp_cmd_hdcp2_get_encryption_status_output hdcp2_get_encryption_status;
++	struct ta_hdcp_cmd_hdcp2_create_session_output_v2 hdcp2_create_session_v2;
++	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2
++		hdcp2_prepare_process_authentication_message_v2;
+ };
+ /**********************************************************/
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4501-drm-amd-display-Add-DDC-handles-for-HDCP2.2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4501-drm-amd-display-Add-DDC-handles-for-HDCP2.2.patch
new file mode 100644
index 00000000..2c223e04
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4501-drm-amd-display-Add-DDC-handles-for-HDCP2.2.patch
@@ -0,0 +1,377 @@
+From 4ea723ead2666d8b4634197039488c9b5fcb4fa5 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 18 Sep 2019 11:23:07 -0400
+Subject: [PATCH 4501/4736] drm/amd/display: Add DDC handles for HDCP2.2
+
+[Why]
+We need these to read and write to aux/i2c, during
+authentication
+
+[How]
+Create read/write functions for all the steps
+(Eg, h_prime, paring_info etc)
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../drm/amd/display/modules/hdcp/hdcp_ddc.c   | 326 ++++++++++++++++++
+ 1 file changed, 326 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
+index e7baae059b85..8059aff9911f 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
+@@ -51,6 +51,26 @@ enum mod_hdcp_ddc_message_id {
+ 	MOD_HDCP_MESSAGE_ID_READ_KSV_FIFO,
+ 	MOD_HDCP_MESSAGE_ID_READ_BINFO,
+ 
++	/* HDCP 2.2 */
++
++	MOD_HDCP_MESSAGE_ID_HDCP2VERSION,
++	MOD_HDCP_MESSAGE_ID_RX_CAPS,
++	MOD_HDCP_MESSAGE_ID_WRITE_AKE_INIT,
++	MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_CERT,
++	MOD_HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM,
++	MOD_HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM,
++	MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME,
++	MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO,
++	MOD_HDCP_MESSAGE_ID_WRITE_LC_INIT,
++	MOD_HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME,
++	MOD_HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS,
++	MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST,
++	MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK,
++	MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE,
++	MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY,
++	MOD_HDCP_MESSAGE_ID_READ_RXSTATUS,
++	MOD_HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE,
++
+ 	MOD_HDCP_MESSAGE_ID_MAX
+ };
+ 
+@@ -70,6 +90,22 @@ static const uint8_t hdcp_i2c_offsets[] = {
+ 	[MOD_HDCP_MESSAGE_ID_READ_BSTATUS] = 0x41,
+ 	[MOD_HDCP_MESSAGE_ID_READ_KSV_FIFO] = 0x43,
+ 	[MOD_HDCP_MESSAGE_ID_READ_BINFO] = 0xFF,
++	[MOD_HDCP_MESSAGE_ID_HDCP2VERSION] = 0x50,
++	[MOD_HDCP_MESSAGE_ID_WRITE_AKE_INIT] = 0x60,
++	[MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_CERT] = 0x80,
++	[MOD_HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM] = 0x60,
++	[MOD_HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM] = 0x60,
++	[MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME] = 0x80,
++	[MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO] = 0x80,
++	[MOD_HDCP_MESSAGE_ID_WRITE_LC_INIT] = 0x60,
++	[MOD_HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME] = 0x80,
++	[MOD_HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS] = 0x60,
++	[MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST] = 0x80,
++	[MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK] = 0x60,
++	[MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE] = 0x60,
++	[MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY] = 0x80,
++	[MOD_HDCP_MESSAGE_ID_READ_RXSTATUS] = 0x70,
++	[MOD_HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE] = 0x0
+ };
+ 
+ static const uint32_t hdcp_dpcd_addrs[] = {
+@@ -88,6 +124,22 @@ static const uint32_t hdcp_dpcd_addrs[] = {
+ 	[MOD_HDCP_MESSAGE_ID_READ_BSTATUS] = 0x68029,
+ 	[MOD_HDCP_MESSAGE_ID_READ_KSV_FIFO] = 0x6802c,
+ 	[MOD_HDCP_MESSAGE_ID_READ_BINFO] = 0x6802a,
++	[MOD_HDCP_MESSAGE_ID_RX_CAPS] = 0x6921d,
++	[MOD_HDCP_MESSAGE_ID_WRITE_AKE_INIT] = 0x69000,
++	[MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_CERT] = 0x6900b,
++	[MOD_HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM] = 0x69220,
++	[MOD_HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM] = 0x692a0,
++	[MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME] = 0x692c0,
++	[MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO] = 0x692e0,
++	[MOD_HDCP_MESSAGE_ID_WRITE_LC_INIT] = 0x692f0,
++	[MOD_HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME] = 0x692f8,
++	[MOD_HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS] = 0x69318,
++	[MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST] = 0x69330,
++	[MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK] = 0x693e0,
++	[MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE] = 0x693f0,
++	[MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY] = 0x69473,
++	[MOD_HDCP_MESSAGE_ID_READ_RXSTATUS] = 0x69493,
++	[MOD_HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE] = 0x69494
+ };
+ 
+ static enum mod_hdcp_status read(struct mod_hdcp *hdcp,
+@@ -303,3 +355,277 @@ enum mod_hdcp_status mod_hdcp_write_an(struct mod_hdcp *hdcp)
+ 			hdcp->auth.msg.hdcp1.an,
+ 			sizeof(hdcp->auth.msg.hdcp1.an));
+ }
++
++enum mod_hdcp_status mod_hdcp_read_hdcp2version(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp))
++		status = MOD_HDCP_STATUS_INVALID_OPERATION;
++	else
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_HDCP2VERSION,
++				&hdcp->auth.msg.hdcp2.hdcp2version_hdmi,
++				sizeof(hdcp->auth.msg.hdcp2.hdcp2version_hdmi));
++
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_rxcaps(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (!is_dp_hdcp(hdcp))
++		status = MOD_HDCP_STATUS_INVALID_OPERATION;
++	else
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_RX_CAPS,
++				hdcp->auth.msg.hdcp2.rxcaps_dp,
++				sizeof(hdcp->auth.msg.hdcp2.rxcaps_dp));
++
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_rxstatus(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp)) {
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_RXSTATUS,
++				(uint8_t *)&hdcp->auth.msg.hdcp2.rxstatus,
++				1);
++	} else {
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_RXSTATUS,
++					(uint8_t *)&hdcp->auth.msg.hdcp2.rxstatus,
++					sizeof(hdcp->auth.msg.hdcp2.rxstatus));
++	}
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_ake_cert(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp)) {
++		hdcp->auth.msg.hdcp2.ake_cert[0] = 3;
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_CERT,
++				hdcp->auth.msg.hdcp2.ake_cert+1,
++				sizeof(hdcp->auth.msg.hdcp2.ake_cert)-1);
++
++	} else {
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_CERT,
++					hdcp->auth.msg.hdcp2.ake_cert,
++					sizeof(hdcp->auth.msg.hdcp2.ake_cert));
++	}
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_h_prime(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp)) {
++		hdcp->auth.msg.hdcp2.ake_h_prime[0] = 7;
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME,
++				hdcp->auth.msg.hdcp2.ake_h_prime+1,
++				sizeof(hdcp->auth.msg.hdcp2.ake_h_prime)-1);
++
++	} else {
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME,
++				hdcp->auth.msg.hdcp2.ake_h_prime,
++				sizeof(hdcp->auth.msg.hdcp2.ake_h_prime));
++	}
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_pairing_info(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp)) {
++		hdcp->auth.msg.hdcp2.ake_pairing_info[0] = 8;
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO,
++				hdcp->auth.msg.hdcp2.ake_pairing_info+1,
++				sizeof(hdcp->auth.msg.hdcp2.ake_pairing_info)-1);
++
++	} else {
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO,
++				hdcp->auth.msg.hdcp2.ake_pairing_info,
++				sizeof(hdcp->auth.msg.hdcp2.ake_pairing_info));
++	}
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_l_prime(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp)) {
++		hdcp->auth.msg.hdcp2.lc_l_prime[0] = 10;
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME,
++				hdcp->auth.msg.hdcp2.lc_l_prime+1,
++				sizeof(hdcp->auth.msg.hdcp2.lc_l_prime)-1);
++
++	} else {
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME,
++				hdcp->auth.msg.hdcp2.lc_l_prime,
++				sizeof(hdcp->auth.msg.hdcp2.lc_l_prime));
++	}
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_rx_id_list(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp)) {
++		hdcp->auth.msg.hdcp2.rx_id_list[0] = 12;
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST,
++				hdcp->auth.msg.hdcp2.rx_id_list+1,
++				sizeof(hdcp->auth.msg.hdcp2.rx_id_list)-1);
++
++	} else {
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST,
++				hdcp->auth.msg.hdcp2.rx_id_list,
++				hdcp->auth.msg.hdcp2.rx_id_list_size);
++	}
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_read_stream_ready(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp)) {
++		hdcp->auth.msg.hdcp2.repeater_auth_stream_ready[0] = 17;
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY,
++				hdcp->auth.msg.hdcp2.repeater_auth_stream_ready+1,
++				sizeof(hdcp->auth.msg.hdcp2.repeater_auth_stream_ready)-1);
++
++	} else {
++		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY,
++				hdcp->auth.msg.hdcp2.repeater_auth_stream_ready,
++				sizeof(hdcp->auth.msg.hdcp2.repeater_auth_stream_ready));
++	}
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_write_ake_init(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp))
++		status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_AKE_INIT,
++				hdcp->auth.msg.hdcp2.ake_init+1,
++				sizeof(hdcp->auth.msg.hdcp2.ake_init)-1);
++	else
++		status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_AKE_INIT,
++					hdcp->auth.msg.hdcp2.ake_init,
++					sizeof(hdcp->auth.msg.hdcp2.ake_init));
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_write_no_stored_km(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp))
++		status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM,
++				hdcp->auth.msg.hdcp2.ake_no_stored_km+1,
++				sizeof(hdcp->auth.msg.hdcp2.ake_no_stored_km)-1);
++	else
++		status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM,
++			hdcp->auth.msg.hdcp2.ake_no_stored_km,
++			sizeof(hdcp->auth.msg.hdcp2.ake_no_stored_km));
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_write_stored_km(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp))
++		status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM,
++				hdcp->auth.msg.hdcp2.ake_stored_km+1,
++				sizeof(hdcp->auth.msg.hdcp2.ake_stored_km)-1);
++	else
++		status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM,
++				hdcp->auth.msg.hdcp2.ake_stored_km,
++				sizeof(hdcp->auth.msg.hdcp2.ake_stored_km));
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_write_lc_init(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp))
++		status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_LC_INIT,
++				hdcp->auth.msg.hdcp2.lc_init+1,
++				sizeof(hdcp->auth.msg.hdcp2.lc_init)-1);
++	else
++		status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_LC_INIT,
++				hdcp->auth.msg.hdcp2.lc_init,
++				sizeof(hdcp->auth.msg.hdcp2.lc_init));
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_write_eks(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp))
++		status = write(hdcp,
++				MOD_HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS,
++				hdcp->auth.msg.hdcp2.ske_eks+1,
++				sizeof(hdcp->auth.msg.hdcp2.ske_eks)-1);
++	else
++		status = write(hdcp,
++			MOD_HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS,
++			hdcp->auth.msg.hdcp2.ske_eks,
++			sizeof(hdcp->auth.msg.hdcp2.ske_eks));
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_write_repeater_auth_ack(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp))
++		status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK,
++				hdcp->auth.msg.hdcp2.repeater_auth_ack+1,
++				sizeof(hdcp->auth.msg.hdcp2.repeater_auth_ack)-1);
++	else
++		status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK,
++				hdcp->auth.msg.hdcp2.repeater_auth_ack,
++				sizeof(hdcp->auth.msg.hdcp2.repeater_auth_ack));
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_write_stream_manage(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp))
++		status = write(hdcp,
++				MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE,
++				hdcp->auth.msg.hdcp2.repeater_auth_stream_manage+1,
++				hdcp->auth.msg.hdcp2.stream_manage_size-1);
++	else
++		status = write(hdcp,
++				MOD_HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE,
++				hdcp->auth.msg.hdcp2.repeater_auth_stream_manage,
++				hdcp->auth.msg.hdcp2.stream_manage_size);
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_write_content_type(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp))
++		status = write(hdcp, MOD_HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE,
++				hdcp->auth.msg.hdcp2.content_stream_type_dp+1,
++				sizeof(hdcp->auth.msg.hdcp2.content_stream_type_dp)-1);
++	else
++		status = MOD_HDCP_STATUS_INVALID_OPERATION;
++	return status;
++}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4502-drm-amd-display-Add-execution-and-transition-states-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4502-drm-amd-display-Add-execution-and-transition-states-.patch
new file mode 100644
index 00000000..66d7df04
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4502-drm-amd-display-Add-execution-and-transition-states-.patch
@@ -0,0 +1,1992 @@
+From d3cc90c80f602b70998a55f10658fc714d481f96 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 18 Sep 2019 11:18:15 -0400
+Subject: [PATCH 4502/4736] drm/amd/display: Add execution and transition
+ states for HDCP2.2
+
+The module works like a state machine
+
+                                    +-------------+
+                            ------> | Execution.c | ------
+                            |       +-------------+       |
+                            |                             V
+    +----+              +--------+                 +--------------+
+    | DM |    ----->    | Hdcp.c |  <------------  | Transition.c |
+    +----+    <-----    +--------+                 +--------------+
+
+This patch adds the execution and transition files for 2.2
+
+Extension to "40a702d427 drm/amd/display: Add HDCP module" for 2.2
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../gpu/drm/amd/display/modules/hdcp/Makefile |   3 +-
+ .../gpu/drm/amd/display/modules/hdcp/hdcp.c   |  86 +-
+ .../gpu/drm/amd/display/modules/hdcp/hdcp.h   | 127 +++
+ .../display/modules/hdcp/hdcp2_execution.c    | 881 ++++++++++++++++++
+ .../display/modules/hdcp/hdcp2_transition.c   | 674 ++++++++++++++
+ .../drm/amd/display/modules/inc/mod_hdcp.h    |   2 +
+ 6 files changed, 1764 insertions(+), 9 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
+ create mode 100644 drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/Makefile b/drivers/gpu/drm/amd/display/modules/hdcp/Makefile
+index 1c3c6d47973a..904424da01b5 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/Makefile
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/Makefile
+@@ -24,7 +24,8 @@
+ #
+ 
+ HDCP = hdcp_ddc.o hdcp_log.o hdcp_psp.o hdcp.o \
+-		hdcp1_execution.o hdcp1_transition.o
++		hdcp1_execution.o hdcp1_transition.o \
++		hdcp2_execution.o hdcp2_transition.o
+ 
+ AMD_DAL_HDCP = $(addprefix $(AMDDALPATH)/modules/hdcp/,$(HDCP))
+ #$(info ************  DAL-HDCP_MAKEFILE ************)
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+index d7ac445dec6f..a74812977963 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+@@ -37,24 +37,52 @@ static void push_error_status(struct mod_hdcp *hdcp,
+ 		HDCP_ERROR_TRACE(hdcp, status);
+ 	}
+ 
+-	hdcp->connection.hdcp1_retry_count++;
++	if (is_hdcp1(hdcp)) {
++		hdcp->connection.hdcp1_retry_count++;
++	} else if (is_hdcp2(hdcp)) {
++		hdcp->connection.hdcp2_retry_count++;
++	}
+ }
+ 
+ static uint8_t is_cp_desired_hdcp1(struct mod_hdcp *hdcp)
+ {
+-	int i, display_enabled = 0;
++	int i, is_auth_needed = 0;
+ 
+-	/* if all displays on the link are disabled, hdcp is not desired */
++	/* if all displays on the link don't need authentication,
++	 * hdcp is not desired
++	 */
+ 	for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++) {
+ 		if (hdcp->connection.displays[i].state != MOD_HDCP_DISPLAY_INACTIVE &&
+ 				!hdcp->connection.displays[i].adjust.disable) {
+-			display_enabled = 1;
++			is_auth_needed = 1;
+ 			break;
+ 		}
+ 	}
+ 
+ 	return (hdcp->connection.hdcp1_retry_count < MAX_NUM_OF_ATTEMPTS) &&
+-			display_enabled && !hdcp->connection.link.adjust.hdcp1.disable;
++			is_auth_needed &&
++			!hdcp->connection.link.adjust.hdcp1.disable;
++}
++
++static uint8_t is_cp_desired_hdcp2(struct mod_hdcp *hdcp)
++{
++	int i, is_auth_needed = 0;
++
++	/* if all displays on the link don't need authentication,
++	 * hdcp is not desired
++	 */
++	for (i = 0; i < MAX_NUM_OF_DISPLAYS; i++) {
++		if (hdcp->connection.displays[i].state != MOD_HDCP_DISPLAY_INACTIVE &&
++				!hdcp->connection.displays[i].adjust.disable) {
++			is_auth_needed = 1;
++			break;
++		}
++	}
++
++	return (hdcp->connection.hdcp2_retry_count < MAX_NUM_OF_ATTEMPTS) &&
++			is_auth_needed &&
++			!hdcp->connection.link.adjust.hdcp2.disable &&
++			!hdcp->connection.is_hdcp2_revoked;
+ }
+ 
+ static enum mod_hdcp_status execution(struct mod_hdcp *hdcp,
+@@ -82,6 +110,11 @@ static enum mod_hdcp_status execution(struct mod_hdcp *hdcp,
+ 	} else if (is_in_hdcp1_dp_states(hdcp)) {
+ 		status = mod_hdcp_hdcp1_dp_execution(hdcp,
+ 				event_ctx, &input->hdcp1);
++	} else if (is_in_hdcp2_states(hdcp)) {
++		status = mod_hdcp_hdcp2_execution(hdcp, event_ctx, &input->hdcp2);
++	} else if (is_in_hdcp2_dp_states(hdcp)) {
++		status = mod_hdcp_hdcp2_dp_execution(hdcp,
++				event_ctx, &input->hdcp2);
+ 	}
+ out:
+ 	return status;
+@@ -99,7 +132,10 @@ static enum mod_hdcp_status transition(struct mod_hdcp *hdcp,
+ 
+ 	if (is_in_initialized_state(hdcp)) {
+ 		if (is_dp_hdcp(hdcp))
+-			if (is_cp_desired_hdcp1(hdcp)) {
++			if (is_cp_desired_hdcp2(hdcp)) {
++				callback_in_ms(0, output);
++				set_state_id(hdcp, output, D2_A0_DETERMINE_RX_HDCP_CAPABLE);
++			} else if (is_cp_desired_hdcp1(hdcp)) {
+ 				callback_in_ms(0, output);
+ 				set_state_id(hdcp, output, D1_A0_DETERMINE_RX_HDCP_CAPABLE);
+ 			} else {
+@@ -107,7 +143,10 @@ static enum mod_hdcp_status transition(struct mod_hdcp *hdcp,
+ 				set_state_id(hdcp, output, HDCP_CP_NOT_DESIRED);
+ 			}
+ 		else if (is_hdmi_dvi_sl_hdcp(hdcp))
+-			if (is_cp_desired_hdcp1(hdcp)) {
++			if (is_cp_desired_hdcp2(hdcp)) {
++				callback_in_ms(0, output);
++				set_state_id(hdcp, output, H2_A0_KNOWN_HDCP2_CAPABLE_RX);
++			} else if (is_cp_desired_hdcp1(hdcp)) {
+ 				callback_in_ms(0, output);
+ 				set_state_id(hdcp, output, H1_A0_WAIT_FOR_ACTIVE_RX);
+ 			} else {
+@@ -126,6 +165,12 @@ static enum mod_hdcp_status transition(struct mod_hdcp *hdcp,
+ 	} else if (is_in_hdcp1_dp_states(hdcp)) {
+ 		status = mod_hdcp_hdcp1_dp_transition(hdcp,
+ 				event_ctx, &input->hdcp1, output);
++	} else if (is_in_hdcp2_states(hdcp)) {
++		status = mod_hdcp_hdcp2_transition(hdcp,
++				event_ctx, &input->hdcp2, output);
++	} else if (is_in_hdcp2_dp_states(hdcp)) {
++		status = mod_hdcp_hdcp2_dp_transition(hdcp,
++				event_ctx, &input->hdcp2, output);
+ 	} else {
+ 		status = MOD_HDCP_STATUS_INVALID_STATE;
+ 	}
+@@ -139,9 +184,13 @@ static enum mod_hdcp_status reset_authentication(struct mod_hdcp *hdcp,
+ 	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
+ 
+ 	if (is_hdcp1(hdcp)) {
+-		if (hdcp->auth.trans_input.hdcp1.create_session != UNKNOWN)
++		if (hdcp->auth.trans_input.hdcp1.create_session != UNKNOWN) {
++			/* TODO - update psp to unify create session failure
++			 * recovery between hdcp1 and 2.
++			 */
+ 			mod_hdcp_hdcp1_destroy_session(hdcp);
+ 
++		}
+ 		if (hdcp->auth.trans_input.hdcp1.add_topology == PASS) {
+ 			status = mod_hdcp_remove_display_topology(hdcp);
+ 			if (status != MOD_HDCP_STATUS_SUCCESS) {
+@@ -154,6 +203,27 @@ static enum mod_hdcp_status reset_authentication(struct mod_hdcp *hdcp,
+ 		memset(&hdcp->auth, 0, sizeof(struct mod_hdcp_authentication));
+ 		memset(&hdcp->state, 0, sizeof(struct mod_hdcp_state));
+ 		set_state_id(hdcp, output, HDCP_INITIALIZED);
++	} else if (is_hdcp2(hdcp)) {
++		if (hdcp->auth.trans_input.hdcp2.create_session == PASS) {
++			status = mod_hdcp_hdcp2_destroy_session(hdcp);
++			if (status != MOD_HDCP_STATUS_SUCCESS) {
++				output->callback_needed = 0;
++				output->watchdog_timer_needed = 0;
++				goto out;
++			}
++		}
++		if (hdcp->auth.trans_input.hdcp2.add_topology == PASS) {
++			status = mod_hdcp_remove_display_topology(hdcp);
++			if (status != MOD_HDCP_STATUS_SUCCESS) {
++				output->callback_needed = 0;
++				output->watchdog_timer_needed = 0;
++				goto out;
++			}
++		}
++		HDCP_TOP_RESET_AUTH_TRACE(hdcp);
++		memset(&hdcp->auth, 0, sizeof(struct mod_hdcp_authentication));
++		memset(&hdcp->state, 0, sizeof(struct mod_hdcp_state));
++		set_state_id(hdcp, output, HDCP_INITIALIZED);
+ 	} else if (is_in_cp_not_desired_state(hdcp)) {
+ 		status = mod_hdcp_remove_display_topology(hdcp);
+ 		if (status != MOD_HDCP_STATUS_SUCCESS) {
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+index d83f0ab1cadb..9887c5ea6d5f 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+@@ -44,11 +44,13 @@
+ #define BINFO_MAX_DEVS_EXCEEDED_MASK_DP			0x0080
+ #define BINFO_MAX_CASCADE_EXCEEDED_MASK_DP		0x0800
+ 
++#define VERSION_HDCP2_MASK				0x04
+ #define RXSTATUS_MSG_SIZE_MASK				0x03FF
+ #define RXSTATUS_READY_MASK				0x0400
+ #define RXSTATUS_REAUTH_REQUEST_MASK			0x0800
+ #define RXIDLIST_DEVICE_COUNT_LOWER_MASK		0xf0
+ #define RXIDLIST_DEVICE_COUNT_UPPER_MASK		0x01
++#define RXCAPS_BYTE2_HDCP2_VERSION_DP			0x02
+ #define RXCAPS_BYTE0_HDCP_CAPABLE_MASK_DP		0x02
+ #define RXSTATUS_READY_MASK_DP				0x0001
+ #define RXSTATUS_H_P_AVAILABLE_MASK_DP			0x0002
+@@ -92,8 +94,52 @@ struct mod_hdcp_transition_input_hdcp1 {
+ 	uint8_t stream_encryption_dp;
+ };
+ 
++struct mod_hdcp_transition_input_hdcp2 {
++	uint8_t hdcp2version_read;
++	uint8_t hdcp2_capable_check;
++	uint8_t add_topology;
++	uint8_t create_session;
++	uint8_t ake_init_prepare;
++	uint8_t ake_init_write;
++	uint8_t rxstatus_read;
++	uint8_t ake_cert_available;
++	uint8_t ake_cert_read;
++	uint8_t ake_cert_validation;
++	uint8_t stored_km_write;
++	uint8_t no_stored_km_write;
++	uint8_t h_prime_available;
++	uint8_t h_prime_read;
++	uint8_t pairing_available;
++	uint8_t pairing_info_read;
++	uint8_t h_prime_validation;
++	uint8_t lc_init_prepare;
++	uint8_t lc_init_write;
++	uint8_t l_prime_available_poll;
++	uint8_t l_prime_read;
++	uint8_t l_prime_validation;
++	uint8_t eks_prepare;
++	uint8_t eks_write;
++	uint8_t enable_encryption;
++	uint8_t reauth_request_check;
++	uint8_t rx_id_list_read;
++	uint8_t device_count_check;
++	uint8_t rx_id_list_validation;
++	uint8_t repeater_auth_ack_write;
++	uint8_t prepare_stream_manage;
++	uint8_t stream_manage_write;
++	uint8_t stream_ready_available;
++	uint8_t stream_ready_read;
++	uint8_t stream_ready_validation;
++
++	uint8_t rx_caps_read_dp;
++	uint8_t content_stream_type_write;
++	uint8_t link_integrity_check_dp;
++	uint8_t stream_encryption_dp;
++};
++
+ union mod_hdcp_transition_input {
+ 	struct mod_hdcp_transition_input_hdcp1 hdcp1;
++	struct mod_hdcp_transition_input_hdcp2 hdcp2;
+ };
+ 
+ struct mod_hdcp_message_hdcp1 {
+@@ -150,8 +196,10 @@ struct mod_hdcp_connection {
+ 	struct mod_hdcp_display displays[MAX_NUM_OF_DISPLAYS];
+ 	uint8_t is_repeater;
+ 	uint8_t is_km_stored;
++	uint8_t is_hdcp2_revoked;
+ 	struct mod_hdcp_trace trace;
+ 	uint8_t hdcp1_retry_count;
++	uint8_t hdcp2_retry_count;
+ };
+ 
+ /* contains values per authentication cycle */
+@@ -219,6 +267,50 @@ enum mod_hdcp_hdcp1_dp_state_id {
+ 	HDCP1_DP_STATE_END = D1_A7_READ_KSV_LIST,
+ };
+ 
++enum mod_hdcp_hdcp2_state_id {
++	HDCP2_STATE_START = HDCP1_DP_STATE_END,
++	H2_A0_KNOWN_HDCP2_CAPABLE_RX,
++	H2_A1_SEND_AKE_INIT,
++	H2_A1_VALIDATE_AKE_CERT,
++	H2_A1_SEND_NO_STORED_KM,
++	H2_A1_READ_H_PRIME,
++	H2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME,
++	H2_A1_SEND_STORED_KM,
++	H2_A1_VALIDATE_H_PRIME,
++	H2_A2_LOCALITY_CHECK,
++	H2_A3_EXCHANGE_KS_AND_TEST_FOR_REPEATER,
++	H2_ENABLE_ENCRYPTION,
++	H2_A5_AUTHENTICATED,
++	H2_A6_WAIT_FOR_RX_ID_LIST,
++	H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK,
++	H2_A9_SEND_STREAM_MANAGEMENT,
++	H2_A9_VALIDATE_STREAM_READY,
++	HDCP2_STATE_END = H2_A9_VALIDATE_STREAM_READY,
++};
++
++enum mod_hdcp_hdcp2_dp_state_id {
++	HDCP2_DP_STATE_START = HDCP2_STATE_END,
++	D2_A0_DETERMINE_RX_HDCP_CAPABLE,
++	D2_A1_SEND_AKE_INIT,
++	D2_A1_VALIDATE_AKE_CERT,
++	D2_A1_SEND_NO_STORED_KM,
++	D2_A1_READ_H_PRIME,
++	D2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME,
++	D2_A1_SEND_STORED_KM,
++	D2_A1_VALIDATE_H_PRIME,
++	D2_A2_LOCALITY_CHECK,
++	D2_A34_EXCHANGE_KS_AND_TEST_FOR_REPEATER,
++	D2_SEND_CONTENT_STREAM_TYPE,
++	D2_ENABLE_ENCRYPTION,
++	D2_A5_AUTHENTICATED,
++	D2_A6_WAIT_FOR_RX_ID_LIST,
++	D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK,
++	D2_A9_SEND_STREAM_MANAGEMENT,
++	D2_A9_VALIDATE_STREAM_READY,
++	HDCP2_DP_STATE_END = D2_A9_VALIDATE_STREAM_READY,
++	HDCP_STATE_END = HDCP2_DP_STATE_END,
++};
++
+ /* hdcp1 executions and transitions */
+ typedef enum mod_hdcp_status (*mod_hdcp_action)(struct mod_hdcp *hdcp);
+ uint8_t mod_hdcp_execute_and_set(
+@@ -239,6 +331,22 @@ enum mod_hdcp_status mod_hdcp_hdcp1_dp_transition(struct mod_hdcp *hdcp,
+ 	struct mod_hdcp_transition_input_hdcp1 *input,
+ 	struct mod_hdcp_output *output);
+ 
++/* hdcp2 executions and transitions */
++enum mod_hdcp_status mod_hdcp_hdcp2_execution(struct mod_hdcp *hdcp,
++	struct mod_hdcp_event_context *event_ctx,
++	struct mod_hdcp_transition_input_hdcp2 *input);
++enum mod_hdcp_status mod_hdcp_hdcp2_dp_execution(struct mod_hdcp *hdcp,
++	struct mod_hdcp_event_context *event_ctx,
++	struct mod_hdcp_transition_input_hdcp2 *input);
++enum mod_hdcp_status mod_hdcp_hdcp2_transition(struct mod_hdcp *hdcp,
++	struct mod_hdcp_event_context *event_ctx,
++	struct mod_hdcp_transition_input_hdcp2 *input,
++	struct mod_hdcp_output *output);
++enum mod_hdcp_status mod_hdcp_hdcp2_dp_transition(struct mod_hdcp *hdcp,
++	struct mod_hdcp_event_context *event_ctx,
++	struct mod_hdcp_transition_input_hdcp2 *input,
++	struct mod_hdcp_output *output);
++
+ /* log functions */
+ void mod_hdcp_dump_binary_message(uint8_t *msg, uint32_t msg_size,
+ 		uint8_t *buf, uint32_t buf_size);
+@@ -289,6 +397,7 @@ enum mod_hdcp_status mod_hdcp_read_binfo(struct mod_hdcp *hdcp);
+ enum mod_hdcp_status mod_hdcp_write_aksv(struct mod_hdcp *hdcp);
+ enum mod_hdcp_status mod_hdcp_write_ainfo(struct mod_hdcp *hdcp);
+ enum mod_hdcp_status mod_hdcp_write_an(struct mod_hdcp *hdcp);
++enum mod_hdcp_status mod_hdcp_read_hdcp2version(struct mod_hdcp *hdcp);
+ enum mod_hdcp_status mod_hdcp_read_rxcaps(struct mod_hdcp *hdcp);
+ enum mod_hdcp_status mod_hdcp_read_rxstatus(struct mod_hdcp *hdcp);
+ enum mod_hdcp_status mod_hdcp_read_ake_cert(struct mod_hdcp *hdcp);
+@@ -352,11 +461,28 @@ static inline uint8_t is_in_hdcp1_dp_states(struct mod_hdcp *hdcp)
+ 			current_state(hdcp) <= HDCP1_DP_STATE_END);
+ }
+ 
++static inline uint8_t is_in_hdcp2_states(struct mod_hdcp *hdcp)
++{
++	return (current_state(hdcp) > HDCP2_STATE_START &&
++			current_state(hdcp) <= HDCP2_STATE_END);
++}
++
++static inline uint8_t is_in_hdcp2_dp_states(struct mod_hdcp *hdcp)
++{
++	return (current_state(hdcp) > HDCP2_DP_STATE_START &&
++			current_state(hdcp) <= HDCP2_DP_STATE_END);
++}
++
+ static inline uint8_t is_hdcp1(struct mod_hdcp *hdcp)
+ {
+ 	return (is_in_hdcp1_states(hdcp) || is_in_hdcp1_dp_states(hdcp));
+ }
+ 
++static inline uint8_t is_hdcp2(struct mod_hdcp *hdcp)
++{
++	return (is_in_hdcp2_states(hdcp) || is_in_hdcp2_dp_states(hdcp));
++}
++
+ static inline uint8_t is_in_cp_not_desired_state(struct mod_hdcp *hdcp)
+ {
+ 	return current_state(hdcp) == HDCP_CP_NOT_DESIRED;
+@@ -481,6 +607,7 @@ static inline struct mod_hdcp_display *get_empty_display_container(
+ static inline void reset_retry_counts(struct mod_hdcp *hdcp)
+ {
+ 	hdcp->connection.hdcp1_retry_count = 0;
++	hdcp->connection.hdcp2_retry_count = 0;
+ }
+ 
+ #endif /* HDCP_H_ */
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
+new file mode 100644
+index 000000000000..c93c8098d972
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
+@@ -0,0 +1,881 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "hdcp.h"
++
++static inline enum mod_hdcp_status check_receiver_id_list_ready(struct mod_hdcp *hdcp)
++{
++	uint8_t is_ready = 0;
++
++	if (is_dp_hdcp(hdcp))
++		is_ready = (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_READY_MASK_DP) ? 1 : 0;
++	else
++		is_ready = ((hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_READY_MASK) &&
++				(hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK)) ? 1 : 0;
++	return is_ready ? MOD_HDCP_STATUS_SUCCESS :
++			MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY;
++}
++
++static inline enum mod_hdcp_status check_hdcp2_capable(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++
++	if (is_dp_hdcp(hdcp))
++		status = ((hdcp->auth.msg.hdcp2.rxcaps_dp[2] &
++						RXCAPS_BYTE0_HDCP_CAPABLE_MASK_DP) &&
++				(hdcp->auth.msg.hdcp2.rxcaps_dp[0] ==
++						RXCAPS_BYTE2_HDCP2_VERSION_DP)) ?
++				MOD_HDCP_STATUS_SUCCESS :
++				MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE;
++	else
++		status = (hdcp->auth.msg.hdcp2.hdcp2version_hdmi & VERSION_HDCP2_MASK) ?
++				MOD_HDCP_STATUS_SUCCESS :
++				MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE;
++	return status;
++}
++
++static inline enum mod_hdcp_status check_reauthentication_request(
++		struct mod_hdcp *hdcp)
++{
++	uint8_t ret = 0;
++
++	if (is_dp_hdcp(hdcp))
++		ret = (hdcp->auth.msg.hdcp2.rxstatus &
++				RXSTATUS_REAUTH_REQUEST_MASK_DP) ?
++				MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST :
++				MOD_HDCP_STATUS_SUCCESS;
++	else
++		ret = (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_REAUTH_REQUEST_MASK) ?
++				MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST :
++				MOD_HDCP_STATUS_SUCCESS;
++	return ret;
++}
++
++static inline enum mod_hdcp_status check_link_integrity_failure_dp(
++		struct mod_hdcp *hdcp)
++{
++	return (hdcp->auth.msg.hdcp2.rxstatus &
++			RXSTATUS_LINK_INTEGRITY_FAILURE_MASK_DP) ?
++			MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE :
++			MOD_HDCP_STATUS_SUCCESS;
++}
++
++static enum mod_hdcp_status check_ake_cert_available(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++	uint16_t size;
++
++	if (is_dp_hdcp(hdcp)) {
++		status = MOD_HDCP_STATUS_SUCCESS;
++	} else {
++		status = mod_hdcp_read_rxstatus(hdcp);
++		if (status == MOD_HDCP_STATUS_SUCCESS) {
++			size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++			status = (size == sizeof(hdcp->auth.msg.hdcp2.ake_cert)) ?
++					MOD_HDCP_STATUS_SUCCESS :
++					MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING;
++		}
++	}
++	return status;
++}
++
++static enum mod_hdcp_status check_h_prime_available(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++	uint8_t size;
++
++	status = mod_hdcp_read_rxstatus(hdcp);
++	if (status != MOD_HDCP_STATUS_SUCCESS)
++		goto out;
++
++	if (is_dp_hdcp(hdcp)) {
++		status = (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_H_P_AVAILABLE_MASK_DP) ?
++				MOD_HDCP_STATUS_SUCCESS :
++				MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING;
++	} else {
++		size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++		status = (size == sizeof(hdcp->auth.msg.hdcp2.ake_h_prime)) ?
++				MOD_HDCP_STATUS_SUCCESS :
++				MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING;
++	}
++out:
++	return status;
++}
++
++static enum mod_hdcp_status check_pairing_info_available(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++	uint8_t size;
++
++	status = mod_hdcp_read_rxstatus(hdcp);
++	if (status != MOD_HDCP_STATUS_SUCCESS)
++		goto out;
++
++	if (is_dp_hdcp(hdcp)) {
++		status = (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_PAIRING_AVAILABLE_MASK_DP) ?
++				MOD_HDCP_STATUS_SUCCESS :
++				MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING;
++	} else {
++		size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++		status = (size == sizeof(hdcp->auth.msg.hdcp2.ake_pairing_info)) ?
++				MOD_HDCP_STATUS_SUCCESS :
++				MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING;
++	}
++out:
++	return status;
++}
++
++static enum mod_hdcp_status poll_l_prime_available(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++	uint8_t size;
++	uint16_t max_wait = 20000; // units of us
++	uint16_t num_polls = 5;
++	uint16_t wait_time = max_wait / num_polls;
++
++	if (is_dp_hdcp(hdcp))
++		status = MOD_HDCP_STATUS_INVALID_OPERATION;
++	else
++		for (; num_polls; num_polls--) {
++			udelay(wait_time);
++
++			status = mod_hdcp_read_rxstatus(hdcp);
++			if (status != MOD_HDCP_STATUS_SUCCESS)
++				break;
++
++			size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++			status = (size == sizeof(hdcp->auth.msg.hdcp2.lc_l_prime)) ?
++					MOD_HDCP_STATUS_SUCCESS :
++					MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING;
++			if (status == MOD_HDCP_STATUS_SUCCESS)
++				break;
++		}
++	return status;
++}
++
++static enum mod_hdcp_status check_stream_ready_available(struct mod_hdcp *hdcp)
++{
++	enum mod_hdcp_status status;
++	uint8_t size;
++
++	if (is_dp_hdcp(hdcp)) {
++		status = MOD_HDCP_STATUS_INVALID_OPERATION;
++	} else {
++		status = mod_hdcp_read_rxstatus(hdcp);
++		if (status != MOD_HDCP_STATUS_SUCCESS)
++			goto out;
++		size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++		status = (size == sizeof(hdcp->auth.msg.hdcp2.repeater_auth_stream_ready)) ?
++				MOD_HDCP_STATUS_SUCCESS :
++				MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING;
++	}
++out:
++	return status;
++}
++
++static inline uint8_t get_device_count(struct mod_hdcp *hdcp)
++{
++	return ((hdcp->auth.msg.hdcp2.rx_id_list[2] & RXIDLIST_DEVICE_COUNT_LOWER_MASK) >> 4) +
++		((hdcp->auth.msg.hdcp2.rx_id_list[1] & RXIDLIST_DEVICE_COUNT_UPPER_MASK) << 4);
++}
++
++static enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp)
++{
++	/* device count must be greater than or equal to tracked hdcp displays */
++	return (get_device_count(hdcp) < get_added_display_count(hdcp)) ?
++			MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE :
++			MOD_HDCP_STATUS_SUCCESS;
++}
++
++static uint8_t process_rxstatus(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input,
++		enum mod_hdcp_status *status)
++{
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_rxstatus,
++			&input->rxstatus_read, status,
++			hdcp, "rxstatus_read"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(check_reauthentication_request,
++			&input->reauth_request_check, status,
++			hdcp, "reauth_request_check"))
++		goto out;
++	if (is_dp_hdcp(hdcp)) {
++		if (!mod_hdcp_execute_and_set(check_link_integrity_failure_dp,
++				&input->link_integrity_check_dp, status,
++				hdcp, "link_integrity_check_dp"))
++			goto out;
++	}
++	if (hdcp->connection.is_repeater)
++		if (check_receiver_id_list_ready(hdcp) ==
++				MOD_HDCP_STATUS_SUCCESS) {
++			HDCP_INPUT_PASS_TRACE(hdcp, "rx_id_list_ready");
++			event_ctx->rx_id_list_ready = 1;
++			if (is_dp_hdcp(hdcp))
++				hdcp->auth.msg.hdcp2.rx_id_list_size =
++						sizeof(hdcp->auth.msg.hdcp2.rx_id_list);
++			else
++				hdcp->auth.msg.hdcp2.rx_id_list_size =
++						hdcp->auth.msg.hdcp2.rxstatus & 0x3FF;
++		}
++out:
++	return (*status == MOD_HDCP_STATUS_SUCCESS);
++}
++
++static enum mod_hdcp_status known_hdcp2_capable_rx(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_hdcp2version,
++			&input->hdcp2version_read, &status,
++			hdcp, "hdcp2version_read"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(check_hdcp2_capable,
++			&input->hdcp2_capable_check, &status,
++			hdcp, "hdcp2_capable"))
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status send_ake_init(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++	if (!mod_hdcp_execute_and_set(mod_hdcp_add_display_topology,
++			&input->add_topology, &status,
++			hdcp, "add_topology"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_create_session,
++			&input->create_session, &status,
++			hdcp, "create_session"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_prepare_ake_init,
++			&input->ake_init_prepare, &status,
++			hdcp, "ake_init_prepare"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_write_ake_init,
++			&input->ake_init_write, &status,
++			hdcp, "ake_init_write"))
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status validate_ake_cert(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++			event_ctx->event != MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (is_hdmi_dvi_sl_hdcp(hdcp))
++		if (!mod_hdcp_execute_and_set(check_ake_cert_available,
++				&input->ake_cert_available, &status,
++				hdcp, "ake_cert_available"))
++			goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_ake_cert,
++			&input->ake_cert_read, &status,
++			hdcp, "ake_cert_read"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_validate_ake_cert,
++			&input->ake_cert_validation, &status,
++			hdcp, "ake_cert_validation"))
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status send_no_stored_km(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (!mod_hdcp_execute_and_set(mod_hdcp_write_no_stored_km,
++			&input->no_stored_km_write, &status,
++			hdcp, "no_stored_km_write"))
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status read_h_prime(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++			event_ctx->event != MOD_HDCP_EVENT_CPIRQ &&
++			event_ctx->event != MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (!mod_hdcp_execute_and_set(check_h_prime_available,
++			&input->h_prime_available, &status,
++			hdcp, "h_prime_available"))
++		goto out;
++
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_h_prime,
++			&input->h_prime_read, &status,
++			hdcp, "h_prime_read"))
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status read_pairing_info_and_validate_h_prime(
++		struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++			event_ctx->event != MOD_HDCP_EVENT_CPIRQ &&
++			event_ctx->event != MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (!mod_hdcp_execute_and_set(check_pairing_info_available,
++			&input->pairing_available, &status,
++			hdcp, "pairing_available"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_pairing_info,
++			&input->pairing_info_read, &status,
++			hdcp, "pairing_info_read"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_validate_h_prime,
++			&input->h_prime_validation, &status,
++			hdcp, "h_prime_validation"))
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status send_stored_km(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (!mod_hdcp_execute_and_set(mod_hdcp_write_stored_km,
++			&input->stored_km_write, &status,
++			hdcp, "stored_km_write"))
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status validate_h_prime(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++			event_ctx->event != MOD_HDCP_EVENT_CPIRQ &&
++			event_ctx->event != MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (!mod_hdcp_execute_and_set(check_h_prime_available,
++			&input->h_prime_available, &status,
++			hdcp, "h_prime_available"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_h_prime,
++			&input->h_prime_read, &status,
++			hdcp, "h_prime_read"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_validate_h_prime,
++			&input->h_prime_validation, &status,
++			hdcp, "h_prime_validation"))
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status locality_check(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_prepare_lc_init,
++			&input->lc_init_prepare, &status,
++			hdcp, "lc_init_prepare"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_write_lc_init,
++			&input->lc_init_write, &status,
++			 hdcp, "lc_init_write"))
++		goto out;
++	if (is_dp_hdcp(hdcp))
++		udelay(16000);
++	else
++		if (!mod_hdcp_execute_and_set(poll_l_prime_available,
++				&input->l_prime_available_poll, &status,
++				hdcp, "l_prime_available_poll"))
++			goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_l_prime,
++			&input->l_prime_read, &status,
++			hdcp, "l_prime_read"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_validate_l_prime,
++			&input->l_prime_validation, &status,
++			hdcp, "l_prime_validation"))
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status exchange_ks_and_test_for_repeater(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_prepare_eks,
++			&input->eks_prepare, &status,
++			hdcp, "eks_prepare"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_write_eks,
++			&input->eks_write, &status,
++			hdcp, "eks_write"))
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status enable_encryption(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++			event_ctx->event != MOD_HDCP_EVENT_CPIRQ) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++	if (event_ctx->event == MOD_HDCP_EVENT_CPIRQ) {
++		process_rxstatus(hdcp, event_ctx, input, &status);
++		goto out;
++	}
++
++	if (is_hdmi_dvi_sl_hdcp(hdcp)) {
++		if (!process_rxstatus(hdcp, event_ctx, input, &status))
++			goto out;
++		if (event_ctx->rx_id_list_ready)
++			goto out;
++	}
++	if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_enable_encryption,
++			&input->enable_encryption, &status,
++			hdcp, "enable_encryption"))
++		goto out;
++	if (is_dp_mst_hdcp(hdcp)) {
++		if (!mod_hdcp_execute_and_set(
++				mod_hdcp_hdcp2_enable_dp_stream_encryption,
++				&input->stream_encryption_dp, &status,
++				hdcp, "stream_encryption_dp"))
++			goto out;
++	}
++out:
++	return status;
++}
++
++static enum mod_hdcp_status authenticated(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++			event_ctx->event != MOD_HDCP_EVENT_CPIRQ) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (!process_rxstatus(hdcp, event_ctx, input, &status))
++		goto out;
++	if (event_ctx->rx_id_list_ready)
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status wait_for_rx_id_list(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++			event_ctx->event != MOD_HDCP_EVENT_CPIRQ &&
++			event_ctx->event != MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (!process_rxstatus(hdcp, event_ctx, input, &status))
++		goto out;
++	if (!event_ctx->rx_id_list_ready) {
++		status = MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY;
++		goto out;
++	}
++out:
++	return status;
++}
++
++static enum mod_hdcp_status verify_rx_id_list_and_send_ack(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++			event_ctx->event != MOD_HDCP_EVENT_CPIRQ) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++	if (event_ctx->event == MOD_HDCP_EVENT_CPIRQ) {
++		process_rxstatus(hdcp, event_ctx, input, &status);
++		goto out;
++	}
++
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_rx_id_list,
++			&input->rx_id_list_read,
++			&status, hdcp, "receiver_id_list_read"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(check_device_count,
++			&input->device_count_check,
++			&status, hdcp, "device_count_check"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_validate_rx_id_list,
++			&input->rx_id_list_validation,
++			&status, hdcp, "rx_id_list_validation"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_write_repeater_auth_ack,
++			&input->repeater_auth_ack_write,
++			&status, hdcp, "repeater_auth_ack_write"))
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status send_stream_management(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++			event_ctx->event != MOD_HDCP_EVENT_CPIRQ) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++	if (event_ctx->event == MOD_HDCP_EVENT_CPIRQ) {
++		process_rxstatus(hdcp, event_ctx, input, &status);
++		goto out;
++	}
++
++	if (is_hdmi_dvi_sl_hdcp(hdcp)) {
++		if (!process_rxstatus(hdcp, event_ctx, input, &status))
++			goto out;
++		if (event_ctx->rx_id_list_ready)
++			goto out;
++	}
++	if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_prepare_stream_management,
++			&input->prepare_stream_manage,
++			&status, hdcp, "prepare_stream_manage"))
++		goto out;
++
++	if (!mod_hdcp_execute_and_set(mod_hdcp_write_stream_manage,
++			&input->stream_manage_write,
++			&status, hdcp, "stream_manage_write"))
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status validate_stream_ready(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++			event_ctx->event != MOD_HDCP_EVENT_CPIRQ &&
++			event_ctx->event != MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++	if (event_ctx->event == MOD_HDCP_EVENT_CPIRQ) {
++		process_rxstatus(hdcp, event_ctx, input, &status);
++		goto out;
++	}
++
++	if (is_hdmi_dvi_sl_hdcp(hdcp)) {
++		if (!process_rxstatus(hdcp, event_ctx, input, &status))
++			goto out;
++		if (event_ctx->rx_id_list_ready) {
++			goto out;
++		}
++	}
++	if (is_hdmi_dvi_sl_hdcp(hdcp))
++		if (!mod_hdcp_execute_and_set(check_stream_ready_available,
++				&input->stream_ready_available,
++				&status, hdcp, "stream_ready_available"))
++			goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_stream_ready,
++			&input->stream_ready_read,
++			&status, hdcp, "stream_ready_read"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_validate_stream_ready,
++			&input->stream_ready_validation,
++			&status, hdcp, "stream_ready_validation"))
++		goto out;
++
++out:
++	return status;
++}
++
++static enum mod_hdcp_status determine_rx_hdcp_capable_dp(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (!mod_hdcp_execute_and_set(mod_hdcp_read_rxcaps,
++			&input->rx_caps_read_dp,
++			&status, hdcp, "rx_caps_read_dp"))
++		goto out;
++	if (!mod_hdcp_execute_and_set(check_hdcp2_capable,
++			&input->hdcp2_capable_check, &status,
++			hdcp, "hdcp2_capable_check"))
++		goto out;
++out:
++	return status;
++}
++
++static enum mod_hdcp_status send_content_stream_type_dp(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK &&
++			event_ctx->event != MOD_HDCP_EVENT_CPIRQ) {
++		event_ctx->unexpected_event = 1;
++		goto out;
++	}
++
++	if (!process_rxstatus(hdcp, event_ctx, input, &status))
++		goto out;
++	if (!mod_hdcp_execute_and_set(mod_hdcp_write_content_type,
++			&input->content_stream_type_write, &status,
++			hdcp, "content_stream_type_write"))
++		goto out;
++out:
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_execution(struct mod_hdcp *hdcp,
++	struct mod_hdcp_event_context *event_ctx,
++	struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	switch (current_state(hdcp)) {
++	case H2_A0_KNOWN_HDCP2_CAPABLE_RX:
++		status = known_hdcp2_capable_rx(hdcp, event_ctx, input);
++		break;
++	case H2_A1_SEND_AKE_INIT:
++		status = send_ake_init(hdcp, event_ctx, input);
++		break;
++	case H2_A1_VALIDATE_AKE_CERT:
++		status = validate_ake_cert(hdcp, event_ctx, input);
++		break;
++	case H2_A1_SEND_NO_STORED_KM:
++		status = send_no_stored_km(hdcp, event_ctx, input);
++		break;
++	case H2_A1_READ_H_PRIME:
++		status = read_h_prime(hdcp, event_ctx, input);
++		break;
++	case H2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME:
++		status = read_pairing_info_and_validate_h_prime(hdcp,
++				event_ctx, input);
++		break;
++	case H2_A1_SEND_STORED_KM:
++		status = send_stored_km(hdcp, event_ctx, input);
++		break;
++	case H2_A1_VALIDATE_H_PRIME:
++		status = validate_h_prime(hdcp, event_ctx, input);
++		break;
++	case H2_A2_LOCALITY_CHECK:
++		status = locality_check(hdcp, event_ctx, input);
++		break;
++	case H2_A3_EXCHANGE_KS_AND_TEST_FOR_REPEATER:
++		status = exchange_ks_and_test_for_repeater(hdcp, event_ctx, input);
++		break;
++	case H2_ENABLE_ENCRYPTION:
++		status = enable_encryption(hdcp, event_ctx, input);
++		break;
++	case H2_A5_AUTHENTICATED:
++		status = authenticated(hdcp, event_ctx, input);
++		break;
++	case H2_A6_WAIT_FOR_RX_ID_LIST:
++		status = wait_for_rx_id_list(hdcp, event_ctx, input);
++		break;
++	case H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK:
++		status = verify_rx_id_list_and_send_ack(hdcp, event_ctx, input);
++		break;
++	case H2_A9_SEND_STREAM_MANAGEMENT:
++		status = send_stream_management(hdcp, event_ctx, input);
++		break;
++	case H2_A9_VALIDATE_STREAM_READY:
++		status = validate_stream_ready(hdcp, event_ctx, input);
++		break;
++	default:
++		status = MOD_HDCP_STATUS_INVALID_STATE;
++		break;
++	}
++
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_dp_execution(struct mod_hdcp *hdcp,
++	struct mod_hdcp_event_context *event_ctx,
++	struct mod_hdcp_transition_input_hdcp2 *input)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++
++	switch (current_state(hdcp)) {
++	case D2_A0_DETERMINE_RX_HDCP_CAPABLE:
++		status = determine_rx_hdcp_capable_dp(hdcp, event_ctx, input);
++		break;
++	case D2_A1_SEND_AKE_INIT:
++		status = send_ake_init(hdcp, event_ctx, input);
++		break;
++	case D2_A1_VALIDATE_AKE_CERT:
++		status = validate_ake_cert(hdcp, event_ctx, input);
++		break;
++	case D2_A1_SEND_NO_STORED_KM:
++		status = send_no_stored_km(hdcp, event_ctx, input);
++		break;
++	case D2_A1_READ_H_PRIME:
++		status = read_h_prime(hdcp, event_ctx, input);
++		break;
++	case D2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME:
++		status = read_pairing_info_and_validate_h_prime(hdcp,
++				event_ctx, input);
++		break;
++	case D2_A1_SEND_STORED_KM:
++		status = send_stored_km(hdcp, event_ctx, input);
++		break;
++	case D2_A1_VALIDATE_H_PRIME:
++		status = validate_h_prime(hdcp, event_ctx, input);
++		break;
++	case D2_A2_LOCALITY_CHECK:
++		status = locality_check(hdcp, event_ctx, input);
++		break;
++	case D2_A34_EXCHANGE_KS_AND_TEST_FOR_REPEATER:
++		status = exchange_ks_and_test_for_repeater(hdcp,
++				event_ctx, input);
++		break;
++	case D2_SEND_CONTENT_STREAM_TYPE:
++		status = send_content_stream_type_dp(hdcp, event_ctx, input);
++		break;
++	case D2_ENABLE_ENCRYPTION:
++		status = enable_encryption(hdcp, event_ctx, input);
++		break;
++	case D2_A5_AUTHENTICATED:
++		status = authenticated(hdcp, event_ctx, input);
++		break;
++	case D2_A6_WAIT_FOR_RX_ID_LIST:
++		status = wait_for_rx_id_list(hdcp, event_ctx, input);
++		break;
++	case D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK:
++		status = verify_rx_id_list_and_send_ack(hdcp, event_ctx, input);
++		break;
++	case D2_A9_SEND_STREAM_MANAGEMENT:
++		status = send_stream_management(hdcp, event_ctx, input);
++		break;
++	case D2_A9_VALIDATE_STREAM_READY:
++		status = validate_stream_ready(hdcp, event_ctx, input);
++		break;
++	default:
++		status = MOD_HDCP_STATUS_INVALID_STATE;
++		break;
++	}
++
++	return status;
++}
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
+new file mode 100644
+index 000000000000..94a0e5fa931b
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
+@@ -0,0 +1,674 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "hdcp.h"
++
++enum mod_hdcp_status mod_hdcp_hdcp2_transition(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input,
++		struct mod_hdcp_output *output)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++	struct mod_hdcp_connection *conn = &hdcp->connection;
++	struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust;
++
++	switch (current_state(hdcp)) {
++	case H2_A0_KNOWN_HDCP2_CAPABLE_RX:
++		if (input->hdcp2version_read != PASS ||
++				input->hdcp2_capable_check != PASS) {
++			adjust->hdcp2.disable = 1;
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, HDCP_INITIALIZED);
++		} else {
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, H2_A1_SEND_AKE_INIT);
++		}
++		break;
++	case H2_A1_SEND_AKE_INIT:
++		if (input->add_topology != PASS ||
++				input->create_session != PASS ||
++				input->ake_init_prepare != PASS) {
++			/* out of sync with psp state */
++			adjust->hdcp2.disable = 1;
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (input->ake_init_write != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		set_watchdog_in_ms(hdcp, 100, output);
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, H2_A1_VALIDATE_AKE_CERT);
++		break;
++	case H2_A1_VALIDATE_AKE_CERT:
++		if (input->ake_cert_available != PASS) {
++			if (event_ctx->event ==
++					MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++				/* 1A-08: consider ake timeout a failure */
++				/* some hdmi receivers are not ready for HDCP
++				 * immediately after video becomes active,
++				 * delay 1s before retry on first HDCP message
++				 * timeout.
++				 */
++				fail_and_restart_in_ms(1000, &status, output);
++			} else {
++				/* continue ake cert polling*/
++				callback_in_ms(10, output);
++				increment_stay_counter(hdcp);
++			}
++			break;
++		} else if (input->ake_cert_read != PASS ||
++				input->ake_cert_validation != PASS) {
++			/*
++			 * 1A-09: consider invalid ake cert a failure
++			 * 1A-10: consider receiver id listed in SRM a failure
++			 */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		if (conn->is_km_stored &&
++				!adjust->hdcp2.force_no_stored_km) {
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, H2_A1_SEND_STORED_KM);
++		} else {
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, H2_A1_SEND_NO_STORED_KM);
++		}
++		break;
++	case H2_A1_SEND_NO_STORED_KM:
++		if (input->no_stored_km_write != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		if (adjust->hdcp2.increase_h_prime_timeout)
++			set_watchdog_in_ms(hdcp, 2000, output);
++		else
++			set_watchdog_in_ms(hdcp, 1000, output);
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, H2_A1_READ_H_PRIME);
++		break;
++	case H2_A1_READ_H_PRIME:
++		if (input->h_prime_available != PASS) {
++			if (event_ctx->event ==
++					MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++				/* 1A-11-3: consider h' timeout a failure */
++				fail_and_restart_in_ms(0, &status, output);
++			} else {
++				/* continue h' polling */
++				callback_in_ms(100, output);
++				increment_stay_counter(hdcp);
++			}
++			break;
++		} else if (input->h_prime_read != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		set_watchdog_in_ms(hdcp, 200, output);
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, H2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME);
++		break;
++	case H2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME:
++		if (input->pairing_available != PASS) {
++			if (event_ctx->event ==
++					MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++				/* 1A-12: consider pairing info timeout
++				 * a failure
++				 */
++				fail_and_restart_in_ms(0, &status, output);
++			} else {
++				/* continue pairing info polling */
++				callback_in_ms(20, output);
++				increment_stay_counter(hdcp);
++			}
++			break;
++		} else if (input->pairing_info_read != PASS ||
++				input->h_prime_validation != PASS) {
++			/* 1A-11-1: consider invalid h' a failure */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, H2_A2_LOCALITY_CHECK);
++		break;
++	case H2_A1_SEND_STORED_KM:
++		if (input->stored_km_write != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		set_watchdog_in_ms(hdcp, 200, output);
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, H2_A1_VALIDATE_H_PRIME);
++		break;
++	case H2_A1_VALIDATE_H_PRIME:
++		if (input->h_prime_available != PASS) {
++			if (event_ctx->event ==
++					MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++				/* 1A-11-2: consider h' timeout a failure */
++				fail_and_restart_in_ms(0, &status, output);
++			} else {
++				/* continue h' polling */
++				callback_in_ms(20, output);
++				increment_stay_counter(hdcp);
++			}
++			break;
++		} else if (input->h_prime_read != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (input->h_prime_validation != PASS) {
++			/* 1A-11-1: consider invalid h' a failure */
++			adjust->hdcp2.force_no_stored_km = 1;
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, H2_A2_LOCALITY_CHECK);
++		break;
++	case H2_A2_LOCALITY_CHECK:
++		if (hdcp->state.stay_count > 10 ||
++				input->lc_init_prepare != PASS ||
++				input->lc_init_write != PASS ||
++				input->l_prime_available_poll != PASS ||
++				input->l_prime_read != PASS) {
++			/*
++			 * 1A-05: consider disconnection after LC init a failure
++			 * 1A-13-1: consider invalid l' a failure
++			 * 1A-13-2: consider l' timeout a failure
++			 */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (input->l_prime_validation != PASS) {
++			callback_in_ms(0, output);
++			increment_stay_counter(hdcp);
++			break;
++		}
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, H2_A3_EXCHANGE_KS_AND_TEST_FOR_REPEATER);
++		break;
++	case H2_A3_EXCHANGE_KS_AND_TEST_FOR_REPEATER:
++		if (input->eks_prepare != PASS ||
++				input->eks_write != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		if (conn->is_repeater) {
++			set_watchdog_in_ms(hdcp, 3000, output);
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, H2_A6_WAIT_FOR_RX_ID_LIST);
++		} else {
++			/* some CTS equipment requires a delay GREATER than
++			 * 200 ms, so delay 210 ms instead of 200 ms
++			 */
++			callback_in_ms(210, output);
++			set_state_id(hdcp, output, H2_ENABLE_ENCRYPTION);
++		}
++		break;
++	case H2_ENABLE_ENCRYPTION:
++		if (input->rxstatus_read != PASS ||
++				input->reauth_request_check != PASS) {
++			/*
++			 * 1A-07: restart hdcp on REAUTH_REQ
++			 * 1B-08: restart hdcp on REAUTH_REQ
++			 */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (event_ctx->rx_id_list_ready && conn->is_repeater) {
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++			break;
++		} else if (input->enable_encryption != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, H2_A5_AUTHENTICATED);
++		HDCP_FULL_DDC_TRACE(hdcp);
++		break;
++	case H2_A5_AUTHENTICATED:
++		if (input->rxstatus_read != PASS ||
++				input->reauth_request_check != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (event_ctx->rx_id_list_ready && conn->is_repeater) {
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++			break;
++		}
++		callback_in_ms(500, output);
++		increment_stay_counter(hdcp);
++		break;
++	case H2_A6_WAIT_FOR_RX_ID_LIST:
++		if (input->rxstatus_read != PASS ||
++				input->reauth_request_check != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (!event_ctx->rx_id_list_ready) {
++			if (event_ctx->event == MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++				/* 1B-02: consider rx id list timeout a failure */
++				/* some CTS equipment's actual timeout
++				 * measurement is slightly greater than 3000 ms.
++				 * Delay 100 ms to ensure it is fully timeout
++				 * before re-authentication.
++				 */
++				fail_and_restart_in_ms(100, &status, output);
++			} else {
++				callback_in_ms(300, output);
++				increment_stay_counter(hdcp);
++			}
++			break;
++		}
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++		break;
++	case H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK:
++		if (input->rxstatus_read != PASS ||
++				input->reauth_request_check != PASS ||
++				input->rx_id_list_read != PASS ||
++				input->device_count_check != PASS ||
++				input->rx_id_list_validation != PASS ||
++				input->repeater_auth_ack_write != PASS) {
++			/* 1B-03: consider invalid v' a failure
++			 * 1B-04: consider MAX_DEVS_EXCEEDED a failure
++			 * 1B-05: consider MAX_CASCADE_EXCEEDED a failure
++			 * 1B-06: consider invalid seq_num_V a failure
++			 * 1B-09: consider seq_num_V rollover a failure
++			 */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, H2_A9_SEND_STREAM_MANAGEMENT);
++		break;
++	case H2_A9_SEND_STREAM_MANAGEMENT:
++		if (input->rxstatus_read != PASS ||
++				input->reauth_request_check != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (event_ctx->rx_id_list_ready && conn->is_repeater) {
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++			break;
++		} else if (input->prepare_stream_manage != PASS ||
++				input->stream_manage_write != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		set_watchdog_in_ms(hdcp, 100, output);
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, H2_A9_VALIDATE_STREAM_READY);
++		break;
++	case H2_A9_VALIDATE_STREAM_READY:
++		if (input->rxstatus_read != PASS ||
++				input->reauth_request_check != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (event_ctx->rx_id_list_ready && conn->is_repeater) {
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++			break;
++		} else if (input->stream_ready_available != PASS) {
++			if (event_ctx->event == MOD_HDCP_EVENT_WATCHDOG_TIMEOUT) {
++				/* 1B-10-2: restart content stream management on
++				 * stream ready timeout
++				 */
++				hdcp->auth.count.stream_management_retry_count++;
++				callback_in_ms(0, output);
++				set_state_id(hdcp, output, H2_A9_SEND_STREAM_MANAGEMENT);
++			} else {
++				callback_in_ms(10, output);
++				increment_stay_counter(hdcp);
++			}
++			break;
++		} else if (input->stream_ready_read != PASS ||
++				input->stream_ready_validation != PASS) {
++			/*
++			 * 1B-10-1: restart content stream management
++			 * on invalid M'
++			 */
++			if (hdcp->auth.count.stream_management_retry_count > 10) {
++				fail_and_restart_in_ms(0, &status, output);
++			} else {
++				hdcp->auth.count.stream_management_retry_count++;
++				callback_in_ms(0, output);
++				set_state_id(hdcp, output, H2_A9_SEND_STREAM_MANAGEMENT);
++			}
++			break;
++		}
++		callback_in_ms(200, output);
++		set_state_id(hdcp, output, H2_ENABLE_ENCRYPTION);
++		break;
++	default:
++		status = MOD_HDCP_STATUS_INVALID_STATE;
++		fail_and_restart_in_ms(0, &status, output);
++		break;
++	}
++
++	return status;
++}
++
++enum mod_hdcp_status mod_hdcp_hdcp2_dp_transition(struct mod_hdcp *hdcp,
++		struct mod_hdcp_event_context *event_ctx,
++		struct mod_hdcp_transition_input_hdcp2 *input,
++		struct mod_hdcp_output *output)
++{
++	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
++	struct mod_hdcp_connection *conn = &hdcp->connection;
++	struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust;
++
++	switch (current_state(hdcp)) {
++	case D2_A0_DETERMINE_RX_HDCP_CAPABLE:
++		if (input->rx_caps_read_dp != PASS ||
++				input->hdcp2_capable_check != PASS) {
++			adjust->hdcp2.disable = 1;
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, HDCP_INITIALIZED);
++		} else {
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, D2_A1_SEND_AKE_INIT);
++		}
++		break;
++	case D2_A1_SEND_AKE_INIT:
++		if (input->add_topology != PASS ||
++				input->create_session != PASS ||
++				input->ake_init_prepare != PASS) {
++			/* out of sync with psp state */
++			adjust->hdcp2.disable = 1;
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (input->ake_init_write != PASS) {
++			/* possibly display not ready */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		callback_in_ms(100, output);
++		set_state_id(hdcp, output, D2_A1_VALIDATE_AKE_CERT);
++		break;
++	case D2_A1_VALIDATE_AKE_CERT:
++		if (input->ake_cert_read != PASS ||
++				input->ake_cert_validation != PASS) {
++			/*
++			 * 1A-08: consider invalid ake cert a failure
++			 * 1A-09: consider receiver id listed in SRM a failure
++			 */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		if (conn->is_km_stored &&
++				!adjust->hdcp2.force_no_stored_km) {
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, D2_A1_SEND_STORED_KM);
++		} else {
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, D2_A1_SEND_NO_STORED_KM);
++		}
++		break;
++	case D2_A1_SEND_NO_STORED_KM:
++		if (input->no_stored_km_write != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		if (adjust->hdcp2.increase_h_prime_timeout)
++			set_watchdog_in_ms(hdcp, 2000, output);
++		else
++			set_watchdog_in_ms(hdcp, 1000, output);
++		set_state_id(hdcp, output, D2_A1_READ_H_PRIME);
++		break;
++	case D2_A1_READ_H_PRIME:
++		if (input->h_prime_available != PASS) {
++			if (event_ctx->event ==
++					MOD_HDCP_EVENT_WATCHDOG_TIMEOUT)
++				/* 1A-10-3: consider h' timeout a failure */
++				fail_and_restart_in_ms(0, &status, output);
++			else
++				increment_stay_counter(hdcp);
++			break;
++		} else if (input->h_prime_read != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		set_watchdog_in_ms(hdcp, 200, output);
++		set_state_id(hdcp, output, D2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME);
++		break;
++	case D2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME:
++		if (input->pairing_available != PASS) {
++			if (event_ctx->event ==
++					MOD_HDCP_EVENT_WATCHDOG_TIMEOUT)
++				/*
++				 * 1A-11: consider pairing info timeout
++				 * a failure
++				 */
++				fail_and_restart_in_ms(0, &status, output);
++			else
++				increment_stay_counter(hdcp);
++			break;
++		} else if (input->pairing_info_read != PASS ||
++				input->h_prime_validation != PASS) {
++			/* 1A-10-1: consider invalid h' a failure */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, D2_A2_LOCALITY_CHECK);
++		break;
++	case D2_A1_SEND_STORED_KM:
++		if (input->stored_km_write != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		set_watchdog_in_ms(hdcp, 200, output);
++		set_state_id(hdcp, output, D2_A1_VALIDATE_H_PRIME);
++		break;
++	case D2_A1_VALIDATE_H_PRIME:
++		if (input->h_prime_available != PASS) {
++			if (event_ctx->event ==
++					MOD_HDCP_EVENT_WATCHDOG_TIMEOUT)
++				/* 1A-10-2: consider h' timeout a failure */
++				fail_and_restart_in_ms(0, &status, output);
++			else
++				increment_stay_counter(hdcp);
++			break;
++		} else if (input->h_prime_read != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (input->h_prime_validation != PASS) {
++			/* 1A-10-1: consider invalid h' a failure */
++			adjust->hdcp2.force_no_stored_km = 1;
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, D2_A2_LOCALITY_CHECK);
++		break;
++	case D2_A2_LOCALITY_CHECK:
++		if (hdcp->state.stay_count > 10 ||
++				input->lc_init_prepare != PASS ||
++				input->lc_init_write != PASS ||
++				input->l_prime_read != PASS) {
++			/* 1A-12: consider invalid l' a failure */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (input->l_prime_validation != PASS) {
++			callback_in_ms(0, output);
++			increment_stay_counter(hdcp);
++			break;
++		}
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, D2_A34_EXCHANGE_KS_AND_TEST_FOR_REPEATER);
++		break;
++	case D2_A34_EXCHANGE_KS_AND_TEST_FOR_REPEATER:
++		if (input->eks_prepare != PASS ||
++				input->eks_write != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		if (conn->is_repeater) {
++			set_watchdog_in_ms(hdcp, 3000, output);
++			set_state_id(hdcp, output, D2_A6_WAIT_FOR_RX_ID_LIST);
++		} else {
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, D2_SEND_CONTENT_STREAM_TYPE);
++		}
++		break;
++	case D2_SEND_CONTENT_STREAM_TYPE:
++		if (input->rxstatus_read != PASS ||
++				input->reauth_request_check != PASS ||
++				input->link_integrity_check_dp != PASS ||
++				input->content_stream_type_write != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		callback_in_ms(210, output);
++		set_state_id(hdcp, output, D2_ENABLE_ENCRYPTION);
++		break;
++	case D2_ENABLE_ENCRYPTION:
++		if (input->rxstatus_read != PASS ||
++				input->reauth_request_check != PASS ||
++				input->link_integrity_check_dp != PASS) {
++			/*
++			 * 1A-07: restart hdcp on REAUTH_REQ
++			 * 1B-08: restart hdcp on REAUTH_REQ
++			 */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (event_ctx->rx_id_list_ready && conn->is_repeater) {
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++			break;
++		} else if (input->enable_encryption != PASS ||
++				(is_dp_mst_hdcp(hdcp) && input->stream_encryption_dp != PASS)) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		set_state_id(hdcp, output, D2_A5_AUTHENTICATED);
++		HDCP_FULL_DDC_TRACE(hdcp);
++		break;
++	case D2_A5_AUTHENTICATED:
++		if (input->rxstatus_read != PASS ||
++				input->reauth_request_check != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (input->link_integrity_check_dp != PASS) {
++			if (hdcp->connection.hdcp2_retry_count >= 1)
++				adjust->hdcp2.disable_type1 = 1;
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (event_ctx->rx_id_list_ready && conn->is_repeater) {
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++			break;
++		}
++		increment_stay_counter(hdcp);
++		break;
++	case D2_A6_WAIT_FOR_RX_ID_LIST:
++		if (input->rxstatus_read != PASS ||
++				input->reauth_request_check != PASS ||
++				input->link_integrity_check_dp != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (!event_ctx->rx_id_list_ready) {
++			if (event_ctx->event == MOD_HDCP_EVENT_WATCHDOG_TIMEOUT)
++				/* 1B-02: consider rx id list timeout a failure */
++				fail_and_restart_in_ms(0, &status, output);
++			else
++				increment_stay_counter(hdcp);
++			break;
++		}
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++		break;
++	case D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK:
++		if (input->rxstatus_read != PASS ||
++				input->reauth_request_check != PASS ||
++				input->link_integrity_check_dp != PASS ||
++				input->rx_id_list_read != PASS ||
++				input->device_count_check != PASS ||
++				input->rx_id_list_validation != PASS ||
++				input->repeater_auth_ack_write != PASS) {
++			/*
++			 * 1B-03: consider invalid v' a failure
++			 * 1B-04: consider MAX_DEVS_EXCEEDED a failure
++			 * 1B-05: consider MAX_CASCADE_EXCEEDED a failure
++			 * 1B-06: consider invalid seq_num_V a failure
++			 * 1B-09: consider seq_num_V rollover a failure
++			 */
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		callback_in_ms(0, output);
++		set_state_id(hdcp, output, D2_A9_SEND_STREAM_MANAGEMENT);
++		break;
++	case D2_A9_SEND_STREAM_MANAGEMENT:
++		if (input->rxstatus_read != PASS ||
++				input->reauth_request_check != PASS ||
++				input->link_integrity_check_dp != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (event_ctx->rx_id_list_ready) {
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++			break;
++		} else if (input->prepare_stream_manage != PASS ||
++				input->stream_manage_write != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		}
++		callback_in_ms(100, output);
++		set_state_id(hdcp, output, D2_A9_VALIDATE_STREAM_READY);
++		break;
++	case D2_A9_VALIDATE_STREAM_READY:
++		if (input->rxstatus_read != PASS ||
++				input->reauth_request_check != PASS ||
++				input->link_integrity_check_dp != PASS) {
++			fail_and_restart_in_ms(0, &status, output);
++			break;
++		} else if (event_ctx->rx_id_list_ready) {
++			callback_in_ms(0, output);
++			set_state_id(hdcp, output, D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK);
++			break;
++		} else if (input->stream_ready_read != PASS ||
++				input->stream_ready_validation != PASS) {
++			/*
++			 * 1B-10-1: restart content stream management
++			 * on invalid M'
++			 * 1B-10-2: consider stream ready timeout a failure
++			 */
++			if (hdcp->auth.count.stream_management_retry_count > 10) {
++				fail_and_restart_in_ms(0, &status, output);
++			} else {
++				hdcp->auth.count.stream_management_retry_count++;
++				callback_in_ms(0, output);
++				set_state_id(hdcp, output, D2_A9_SEND_STREAM_MANAGEMENT);
++			}
++			break;
++		}
++		callback_in_ms(200, output);
++		set_state_id(hdcp, output, D2_ENABLE_ENCRYPTION);
++		break;
++	default:
++		status = MOD_HDCP_STATUS_INVALID_STATE;
++		fail_and_restart_in_ms(0, &status, output);
++		break;
++	}
++	return status;
++}
+diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+index dea21702edff..97ecbf5bfec1 100644
+--- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+@@ -77,6 +77,7 @@ enum mod_hdcp_status {
+ 	MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING,
+ 	MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING,
+ 	MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE,
++	MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED,
+ 	MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE,
+ 	MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE,
+ 	MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE,
+@@ -86,6 +87,7 @@ enum mod_hdcp_status {
+ 	MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE,
+ 	MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY,
+ 	MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE,
++	MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_REVOKED,
+ 	MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION,
+ 	MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING,
+ 	MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4503-drm-amd-display-Add-logging-for-HDCP2.2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4503-drm-amd-display-Add-logging-for-HDCP2.2.patch
new file mode 100644
index 00000000..d35a3ef4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4503-drm-amd-display-Add-logging-for-HDCP2.2.patch
@@ -0,0 +1,309 @@
+From 4f15a05fdfe99ba65a5cb3574965f6acf4316bd0 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 18 Sep 2019 11:24:09 -0400
+Subject: [PATCH 4503/4736] drm/amd/display: Add logging for HDCP2.2
+
+[Why]
+We need to log the state changes for 2.2
+This patch extends the existing logging functions to handle
+HDCP2.2.
+
+[How]
+We do this by adding if/else in the defines, and output the log
+ based on the hdcp version
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../drm/amd/display/modules/hdcp/hdcp_log.c   | 118 ++++++++++++++++++
+ .../drm/amd/display/modules/hdcp/hdcp_log.h   |  94 +++++++++++---
+ .../drm/amd/display/modules/hdcp/hdcp_psp.c   |   4 +
+ 3 files changed, 196 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
+index 3982ced5f969..724ebcee9a19 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
+@@ -116,6 +116,58 @@ char *mod_hdcp_status_to_str(int32_t status)
+ 		return "MOD_HDCP_STATUS_DDC_FAILURE";
+ 	case MOD_HDCP_STATUS_INVALID_OPERATION:
+ 		return "MOD_HDCP_STATUS_INVALID_OPERATION";
++	case MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE:
++		return "MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE";
++	case MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE";
++	case MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE";
++	case MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE";
++	case MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING:
++		return "MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING";
++	case MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING:
++		return "MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING";
++	case MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING:
++		return "MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING";
++	case MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE";
++	case MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED:
++		return "MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED";
++	case MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE";
++	case MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE";
++	case MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE";
++	case MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING:
++		return "MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING";
++	case MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE";
++	case MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE";
++	case MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE";
++	case MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE";
++	case MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_REVOKED:
++		return "MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_REVOKED";
++	case MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY:
++		return "MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY";
++	case MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION:
++		return "MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION";
++	case MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING:
++		return "MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING";
++	case MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE";
++	case MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE";
++	case MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST:
++		return "MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST";
++	case MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE";
++	case MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE:
++		return "MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE";
+ 	default:
+ 		return "MOD_HDCP_STATUS_UNKNOWN";
+ 	}
+@@ -156,6 +208,72 @@ char *mod_hdcp_state_id_to_str(int32_t id)
+ 		return "D1_A6_WAIT_FOR_READY";
+ 	case D1_A7_READ_KSV_LIST:
+ 		return "D1_A7_READ_KSV_LIST";
++	case H2_A0_KNOWN_HDCP2_CAPABLE_RX:
++		return "H2_A0_KNOWN_HDCP2_CAPABLE_RX";
++	case H2_A1_SEND_AKE_INIT:
++		return "H2_A1_SEND_AKE_INIT";
++	case H2_A1_VALIDATE_AKE_CERT:
++		return "H2_A1_VALIDATE_AKE_CERT";
++	case H2_A1_SEND_NO_STORED_KM:
++		return "H2_A1_SEND_NO_STORED_KM";
++	case H2_A1_READ_H_PRIME:
++		return "H2_A1_READ_H_PRIME";
++	case H2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME:
++		return "H2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME";
++	case H2_A1_SEND_STORED_KM:
++		return "H2_A1_SEND_STORED_KM";
++	case H2_A1_VALIDATE_H_PRIME:
++		return "H2_A1_VALIDATE_H_PRIME";
++	case H2_A2_LOCALITY_CHECK:
++		return "H2_A2_LOCALITY_CHECK";
++	case H2_A3_EXCHANGE_KS_AND_TEST_FOR_REPEATER:
++		return "H2_A3_EXCHANGE_KS_AND_TEST_FOR_REPEATER";
++	case H2_ENABLE_ENCRYPTION:
++		return "H2_ENABLE_ENCRYPTION";
++	case H2_A5_AUTHENTICATED:
++		return "H2_A5_AUTHENTICATED";
++	case H2_A6_WAIT_FOR_RX_ID_LIST:
++		return "H2_A6_WAIT_FOR_RX_ID_LIST";
++	case H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK:
++		return "H2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK";
++	case H2_A9_SEND_STREAM_MANAGEMENT:
++		return "H2_A9_SEND_STREAM_MANAGEMENT";
++	case H2_A9_VALIDATE_STREAM_READY:
++		return "H2_A9_VALIDATE_STREAM_READY";
++	case D2_A0_DETERMINE_RX_HDCP_CAPABLE:
++		return "D2_A0_DETERMINE_RX_HDCP_CAPABLE";
++	case D2_A1_SEND_AKE_INIT:
++		return "D2_A1_SEND_AKE_INIT";
++	case D2_A1_VALIDATE_AKE_CERT:
++		return "D2_A1_VALIDATE_AKE_CERT";
++	case D2_A1_SEND_NO_STORED_KM:
++		return "D2_A1_SEND_NO_STORED_KM";
++	case D2_A1_READ_H_PRIME:
++		return "D2_A1_READ_H_PRIME";
++	case D2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME:
++		return "D2_A1_READ_PAIRING_INFO_AND_VALIDATE_H_PRIME";
++	case D2_A1_SEND_STORED_KM:
++		return "D2_A1_SEND_STORED_KM";
++	case D2_A1_VALIDATE_H_PRIME:
++		return "D2_A1_VALIDATE_H_PRIME";
++	case D2_A2_LOCALITY_CHECK:
++		return "D2_A2_LOCALITY_CHECK";
++	case D2_A34_EXCHANGE_KS_AND_TEST_FOR_REPEATER:
++		return "D2_A34_EXCHANGE_KS_AND_TEST_FOR_REPEATER";
++	case D2_SEND_CONTENT_STREAM_TYPE:
++		return "D2_SEND_CONTENT_STREAM_TYPE";
++	case D2_ENABLE_ENCRYPTION:
++		return "D2_ENABLE_ENCRYPTION";
++	case D2_A5_AUTHENTICATED:
++		return "D2_A5_AUTHENTICATED";
++	case D2_A6_WAIT_FOR_RX_ID_LIST:
++		return "D2_A6_WAIT_FOR_RX_ID_LIST";
++	case D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK:
++		return "D2_A78_VERIFY_RX_ID_LIST_AND_SEND_ACK";
++	case D2_A9_SEND_STREAM_MANAGEMENT:
++		return "D2_A9_SEND_STREAM_MANAGEMENT";
++	case D2_A9_VALIDATE_STREAM_READY:
++		return "D2_A9_VALIDATE_STREAM_READY";
+ 	default:
+ 		return "UNKNOWN_STATE_ID";
+ 	};
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
+index 2fd0e0a893ef..b29322e7d5fe 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
+@@ -45,6 +45,10 @@
+ 		HDCP_LOG_VER(hdcp, \
+ 			"[Link %d] HDCP 1.4 enabled on display %d", \
+ 			hdcp->config.index, displayIndex)
++#define HDCP_HDCP2_ENABLED_TRACE(hdcp, displayIndex) \
++		HDCP_LOG_VER(hdcp, \
++			"[Link %d] HDCP 2.2 enabled on display %d", \
++			hdcp->config.index, displayIndex)
+ /* state machine logs */
+ #define HDCP_REMOVE_DISPLAY_TRACE(hdcp, displayIndex) \
+ 		HDCP_LOG_FSM(hdcp, \
+@@ -93,26 +97,73 @@
+ 				hdcp->buf); \
+ } while (0)
+ #define HDCP_FULL_DDC_TRACE(hdcp) do { \
+-	HDCP_DDC_READ_TRACE(hdcp, "BKSV", hdcp->auth.msg.hdcp1.bksv, \
+-			sizeof(hdcp->auth.msg.hdcp1.bksv)); \
+-	HDCP_DDC_READ_TRACE(hdcp, "BCAPS", &hdcp->auth.msg.hdcp1.bcaps, \
+-			sizeof(hdcp->auth.msg.hdcp1.bcaps)); \
+-	HDCP_DDC_WRITE_TRACE(hdcp, "AN", hdcp->auth.msg.hdcp1.an, \
+-			sizeof(hdcp->auth.msg.hdcp1.an)); \
+-	HDCP_DDC_WRITE_TRACE(hdcp, "AKSV", hdcp->auth.msg.hdcp1.aksv, \
+-			sizeof(hdcp->auth.msg.hdcp1.aksv)); \
+-	HDCP_DDC_WRITE_TRACE(hdcp, "AINFO", &hdcp->auth.msg.hdcp1.ainfo, \
+-			sizeof(hdcp->auth.msg.hdcp1.ainfo)); \
+-	HDCP_DDC_READ_TRACE(hdcp, "RI' / R0'", \
+-			(uint8_t *)&hdcp->auth.msg.hdcp1.r0p, \
+-			sizeof(hdcp->auth.msg.hdcp1.r0p)); \
+-	HDCP_DDC_READ_TRACE(hdcp, "BINFO", \
+-			(uint8_t *)&hdcp->auth.msg.hdcp1.binfo_dp, \
+-			sizeof(hdcp->auth.msg.hdcp1.binfo_dp)); \
+-	HDCP_DDC_READ_TRACE(hdcp, "KSVLIST", hdcp->auth.msg.hdcp1.ksvlist, \
+-			hdcp->auth.msg.hdcp1.ksvlist_size); \
+-	HDCP_DDC_READ_TRACE(hdcp, "V'", hdcp->auth.msg.hdcp1.vp, \
+-			sizeof(hdcp->auth.msg.hdcp1.vp)); \
++	if (is_hdcp1(hdcp)) { \
++		HDCP_DDC_READ_TRACE(hdcp, "BKSV", hdcp->auth.msg.hdcp1.bksv, \
++				sizeof(hdcp->auth.msg.hdcp1.bksv)); \
++		HDCP_DDC_READ_TRACE(hdcp, "BCAPS", &hdcp->auth.msg.hdcp1.bcaps, \
++				sizeof(hdcp->auth.msg.hdcp1.bcaps)); \
++		HDCP_DDC_WRITE_TRACE(hdcp, "AN", hdcp->auth.msg.hdcp1.an, \
++				sizeof(hdcp->auth.msg.hdcp1.an)); \
++		HDCP_DDC_WRITE_TRACE(hdcp, "AKSV", hdcp->auth.msg.hdcp1.aksv, \
++				sizeof(hdcp->auth.msg.hdcp1.aksv)); \
++		HDCP_DDC_WRITE_TRACE(hdcp, "AINFO", &hdcp->auth.msg.hdcp1.ainfo, \
++				sizeof(hdcp->auth.msg.hdcp1.ainfo)); \
++		HDCP_DDC_READ_TRACE(hdcp, "RI' / R0'", \
++				(uint8_t *)&hdcp->auth.msg.hdcp1.r0p, \
++				sizeof(hdcp->auth.msg.hdcp1.r0p)); \
++		HDCP_DDC_READ_TRACE(hdcp, "BINFO", \
++				(uint8_t *)&hdcp->auth.msg.hdcp1.binfo_dp, \
++				sizeof(hdcp->auth.msg.hdcp1.binfo_dp)); \
++		HDCP_DDC_READ_TRACE(hdcp, "KSVLIST", hdcp->auth.msg.hdcp1.ksvlist, \
++				hdcp->auth.msg.hdcp1.ksvlist_size); \
++		HDCP_DDC_READ_TRACE(hdcp, "V'", hdcp->auth.msg.hdcp1.vp, \
++				sizeof(hdcp->auth.msg.hdcp1.vp)); \
++	} else { \
++		HDCP_DDC_READ_TRACE(hdcp, "HDCP2Version", \
++				&hdcp->auth.msg.hdcp2.hdcp2version_hdmi, \
++				sizeof(hdcp->auth.msg.hdcp2.hdcp2version_hdmi)); \
++		HDCP_DDC_READ_TRACE(hdcp, "Rx Caps", hdcp->auth.msg.hdcp2.rxcaps_dp, \
++				sizeof(hdcp->auth.msg.hdcp2.rxcaps_dp)); \
++		HDCP_DDC_WRITE_TRACE(hdcp, "AKE Init", hdcp->auth.msg.hdcp2.ake_init, \
++				sizeof(hdcp->auth.msg.hdcp2.ake_init)); \
++		HDCP_DDC_READ_TRACE(hdcp, "AKE Cert", hdcp->auth.msg.hdcp2.ake_cert, \
++				sizeof(hdcp->auth.msg.hdcp2.ake_cert)); \
++		HDCP_DDC_WRITE_TRACE(hdcp, "Stored KM", \
++				hdcp->auth.msg.hdcp2.ake_stored_km, \
++				sizeof(hdcp->auth.msg.hdcp2.ake_stored_km)); \
++		HDCP_DDC_WRITE_TRACE(hdcp, "No Stored KM", \
++				hdcp->auth.msg.hdcp2.ake_no_stored_km, \
++				sizeof(hdcp->auth.msg.hdcp2.ake_no_stored_km)); \
++		HDCP_DDC_READ_TRACE(hdcp, "H'", hdcp->auth.msg.hdcp2.ake_h_prime, \
++				sizeof(hdcp->auth.msg.hdcp2.ake_h_prime)); \
++		HDCP_DDC_READ_TRACE(hdcp, "Pairing Info", \
++				hdcp->auth.msg.hdcp2.ake_pairing_info, \
++				sizeof(hdcp->auth.msg.hdcp2.ake_pairing_info)); \
++		HDCP_DDC_WRITE_TRACE(hdcp, "LC Init", hdcp->auth.msg.hdcp2.lc_init, \
++				sizeof(hdcp->auth.msg.hdcp2.lc_init)); \
++		HDCP_DDC_READ_TRACE(hdcp, "L'", hdcp->auth.msg.hdcp2.lc_l_prime, \
++				sizeof(hdcp->auth.msg.hdcp2.lc_l_prime)); \
++		HDCP_DDC_WRITE_TRACE(hdcp, "Exchange KS", hdcp->auth.msg.hdcp2.ske_eks, \
++				sizeof(hdcp->auth.msg.hdcp2.ske_eks)); \
++		HDCP_DDC_READ_TRACE(hdcp, "Rx Status", \
++				(uint8_t *)&hdcp->auth.msg.hdcp2.rxstatus, \
++				sizeof(hdcp->auth.msg.hdcp2.rxstatus)); \
++		HDCP_DDC_READ_TRACE(hdcp, "Rx Id List", \
++				hdcp->auth.msg.hdcp2.rx_id_list, \
++				hdcp->auth.msg.hdcp2.rx_id_list_size); \
++		HDCP_DDC_WRITE_TRACE(hdcp, "Rx Id List Ack", \
++				hdcp->auth.msg.hdcp2.repeater_auth_ack, \
++				sizeof(hdcp->auth.msg.hdcp2.repeater_auth_ack)); \
++		HDCP_DDC_WRITE_TRACE(hdcp, "Content Stream Management", \
++				hdcp->auth.msg.hdcp2.repeater_auth_stream_manage, \
++				hdcp->auth.msg.hdcp2.stream_manage_size); \
++		HDCP_DDC_READ_TRACE(hdcp, "Stream Ready", \
++				hdcp->auth.msg.hdcp2.repeater_auth_stream_ready, \
++				sizeof(hdcp->auth.msg.hdcp2.repeater_auth_stream_ready)); \
++		HDCP_DDC_WRITE_TRACE(hdcp, "Content Stream Type", \
++				hdcp->auth.msg.hdcp2.content_stream_type_dp, \
++				sizeof(hdcp->auth.msg.hdcp2.content_stream_type_dp)); \
++	} \
+ } while (0)
+ #define HDCP_TOP_ADD_DISPLAY_TRACE(hdcp, i) \
+ 		HDCP_LOG_TOP(hdcp, "[Link %d]\tadd display %d", \
+@@ -123,6 +174,9 @@
+ #define HDCP_TOP_HDCP1_DESTROY_SESSION_TRACE(hdcp) \
+ 		HDCP_LOG_TOP(hdcp, "[Link %d]\tdestroy hdcp1 session", \
+ 				hdcp->config.index)
++#define HDCP_TOP_HDCP2_DESTROY_SESSION_TRACE(hdcp) \
++		HDCP_LOG_TOP(hdcp, "[Link %d]\tdestroy hdcp2 session", \
++				hdcp->config.index)
+ #define HDCP_TOP_RESET_AUTH_TRACE(hdcp) \
+ 		HDCP_LOG_TOP(hdcp, "[Link %d]\treset authentication", hdcp->config.index)
+ #define HDCP_TOP_RESET_CONN_TRACE(hdcp) \
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+index ddba0cfa5722..a365cf00bc4c 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+@@ -393,6 +393,8 @@ enum mod_hdcp_status mod_hdcp_hdcp2_destroy_session(struct mod_hdcp *hdcp)
+ 	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
+ 		return MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE;
+ 
++	HDCP_TOP_HDCP2_DESTROY_SESSION_TRACE(hdcp);
++
+ 	return MOD_HDCP_STATUS_SUCCESS;
+ }
+ 
+@@ -649,6 +651,7 @@ enum mod_hdcp_status mod_hdcp_hdcp2_enable_encryption(struct mod_hdcp *hdcp)
+ 
+ 	if (!is_dp_mst_hdcp(hdcp)) {
+ 		display->state = MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;
++		HDCP_HDCP2_ENABLED_TRACE(hdcp, display->index);
+ 	}
+ 
+ 	return MOD_HDCP_STATUS_SUCCESS;
+@@ -727,6 +730,7 @@ enum mod_hdcp_status mod_hdcp_hdcp2_enable_dp_stream_encryption(struct mod_hdcp
+ 			break;
+ 
+ 		hdcp->connection.displays[i].state = MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED;
++		HDCP_HDCP2_ENABLED_TRACE(hdcp, hdcp->connection.displays[i].index);
+ 	}
+ 
+ 	return (hdcp_cmd->hdcp_status == TA_HDCP_STATUS__SUCCESS) ? MOD_HDCP_STATUS_SUCCESS
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4504-drm-amd-display-Change-ERROR-to-WARN-for-HDCP-module.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4504-drm-amd-display-Change-ERROR-to-WARN-for-HDCP-module.patch
new file mode 100644
index 00000000..eedcc6a9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4504-drm-amd-display-Change-ERROR-to-WARN-for-HDCP-module.patch
@@ -0,0 +1,48 @@
+From 64c431ef83bb5b79760d2ccec2e87b8e2b03a1b8 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 18 Sep 2019 11:24:39 -0400
+Subject: [PATCH 4504/4736] drm/amd/display: Change ERROR to WARN for HDCP
+ module
+
+[Why]
+HDCP is a bit finicky so we try it 3 times, this leads to a case where
+if we fail the first time and pass the second time the error is still
+shown in dmesg for the first failed attempt.
+
+This leads to false positive errors.
+
+[How]
+Change the logging from ERROR to WARNING. Warnings are still shown in dmesg
+to know what went wrong.
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
+index b29322e7d5fe..ff91373ebada 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h
+@@ -27,7 +27,7 @@
+ #define MOD_HDCP_LOG_H_
+ 
+ #ifdef CONFIG_DRM_AMD_DC_HDCP
+-#define HDCP_LOG_ERR(hdcp, ...) DRM_ERROR(__VA_ARGS__)
++#define HDCP_LOG_ERR(hdcp, ...) DRM_WARN(__VA_ARGS__)
+ #define HDCP_LOG_VER(hdcp, ...) DRM_DEBUG_KMS(__VA_ARGS__)
+ #define HDCP_LOG_FSM(hdcp, ...) DRM_DEBUG_KMS(__VA_ARGS__)
+ #define HDCP_LOG_TOP(hdcp, ...) pr_debug("[HDCP_TOP]:"__VA_ARGS__)
+@@ -37,7 +37,7 @@
+ /* default logs */
+ #define HDCP_ERROR_TRACE(hdcp, status) \
+ 		HDCP_LOG_ERR(hdcp, \
+-			"[Link %d] ERROR %s IN STATE %s", \
++			"[Link %d] WARNING %s IN STATE %s", \
+ 			hdcp->config.index, \
+ 			mod_hdcp_status_to_str(status), \
+ 			mod_hdcp_state_id_to_str(hdcp->state.id))
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4505-drm-amd-display-Enable-HDCP-2.2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4505-drm-amd-display-Enable-HDCP-2.2.patch
new file mode 100644
index 00000000..224e05ae
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4505-drm-amd-display-Enable-HDCP-2.2.patch
@@ -0,0 +1,58 @@
+From 07ec6fac9421d37e317e547585d4a37e925477c8 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Tue, 23 Jul 2019 11:25:10 -0400
+Subject: [PATCH 4505/4736] drm/amd/display: Enable HDCP 2.2
+
+[Why]
+HDCP 2.2 was disabled, we need to enable it
+
+[How]
+-Update display topology to support 2.2
+-Unset hdcp2.disable in update_config
+-Change logic of event_update_property, now we set the property to be
+ENABLED for any level of encryption (2.2 or 1.4).
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 3 +--
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c    | 2 +-
+ 2 files changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+index 77181ddf6c8e..970f2d58c6dc 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+@@ -190,7 +190,7 @@ static void event_property_update(struct work_struct *work)
+ 		}
+ 	}
+ 
+-	if (hdcp_work->encryption_status == MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON)
++	if (hdcp_work->encryption_status != MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF)
+ 		drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_ENABLED);
+ 	else
+ 		drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_DESIRED);
+@@ -294,7 +294,6 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
+ 	link->dig_be = config->link_enc_inst;
+ 	link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1;
+ 	link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
+-	link->adjust.hdcp2.disable = 1;
+ 
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+index a365cf00bc4c..a9511612f426 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+@@ -109,7 +109,7 @@ enum mod_hdcp_status mod_hdcp_add_display_topology(struct mod_hdcp *hdcp)
+ 			dtm_cmd->dtm_in_message.topology_update_v2.dig_fe = display->dig_fe;
+ 			dtm_cmd->dtm_in_message.topology_update_v2.dp_mst_vcid = display->vc_id;
+ 			dtm_cmd->dtm_in_message.topology_update_v2.max_hdcp_supported_version =
+-				TA_DTM_HDCP_VERSION_MAX_SUPPORTED__1_x;
++				TA_DTM_HDCP_VERSION_MAX_SUPPORTED__2_2;
+ 			dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE;
+ 
+ 			psp_dtm_invoke(psp, dtm_cmd->cmd_id);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4506-drm-amd-display-Handle-hdcp2.2-type0-1-in-dm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4506-drm-amd-display-Handle-hdcp2.2-type0-1-in-dm.patch
new file mode 100644
index 00000000..490a1df7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4506-drm-amd-display-Handle-hdcp2.2-type0-1-in-dm.patch
@@ -0,0 +1,164 @@
+From 370e7141a7d4f568b25dec0fda37ceaeaa77ce5e Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 16 Aug 2019 14:49:05 -0400
+Subject: [PATCH 4506/4736] drm/amd/display: Handle hdcp2.2 type0/1 in dm
+
+[Why]
+HDCP 2.2 uses type0 and type1 content type. This is passed to the receiver
+to stream the proper content.
+
+For example, in a MST case if the main
+device is HDCP2.2 capable but the secondary device is only 1.4 capabale
+we can use Type0
+
+Type0 content: use HDCP 1.4 or HDCP2.2 type0
+Type1 content: Only use HDCP 2.2 type1
+
+[How]
+We use the "hdcp content type" property in drm. We use the
+disable_type1 flag in hdcp module to select the type based on the
+properties.
+
+For updating the property we use the same logic as 1.4, but now we
+consider content_type as well and update the property if the
+requirements are met
+
+Change-Id: I17bffd50b245e119adfba8ea0ad6a1402fcdd939
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 18 ++++++++++++++----
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 17 +++++++++++++----
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h |  4 ++--
+ .../gpu/drm/amd/display/modules/hdcp/hdcp.c    |  5 ++++-
+ 4 files changed, 33 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index ec9fac7d4559..3828a19a87bb 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -43,6 +43,7 @@
+ #include "amdgpu_dm.h"
+ #ifdef CONFIG_DRM_AMD_DC_HDCP
+ #include "amdgpu_dm_hdcp.h"
++#include <drm/drm_hdcp.h>
+ #endif
+ #include "amdgpu_pm.h"
+ 
+@@ -5477,7 +5478,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
+ 				adev->mode_info.freesync_capable_property, 0);
+ #ifdef CONFIG_DRM_AMD_DC_HDCP
+ 		if (adev->asic_type >= CHIP_RAVEN)
+-			drm_connector_attach_content_protection_property(&aconnector->base, false);
++			drm_connector_attach_content_protection_property(&aconnector->base, true);
+ #endif
+ 	}
+ }
+@@ -5728,6 +5729,12 @@ static bool is_content_protection_different(struct drm_connector_state *state,
+ {
+ 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
+ 
++	if (old_state->hdcp_content_type != state->hdcp_content_type &&
++	    state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
++		state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
++		return true;
++	}
++
+ 	/* CP is being re enabled, ignore this */
+ 	if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
+ 	    state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
+@@ -5760,11 +5767,14 @@ static void update_content_protection(struct drm_connector_state *state, const s
+ 				      struct hdcp_workqueue *hdcp_w)
+ {
+ 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
++	bool disable_type1 = state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE0 ? true : false;
+ 
+-	if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
+-		hdcp_add_display(hdcp_w, aconnector->dc_link->link_index, aconnector);
+-	else if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
++	if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
++		hdcp_reset_display(hdcp_w, aconnector->dc_link->link_index);
++		hdcp_add_display(hdcp_w, aconnector->dc_link->link_index, aconnector, disable_type1);
++	} else if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
+ 		hdcp_remove_display(hdcp_w, aconnector->dc_link->link_index, aconnector->base.index);
++	}
+ 
+ }
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+index 970f2d58c6dc..a2ad1390977d 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+@@ -87,7 +87,8 @@ static void process_output(struct hdcp_workqueue *hdcp_work)
+ 
+ }
+ 
+-void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index, struct amdgpu_dm_connector *aconnector)
++void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index, struct amdgpu_dm_connector *aconnector,
++		      bool disable_type1)
+ {
+ 	struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
+ 	struct mod_hdcp_display *display = &hdcp_work[link_index].display;
+@@ -96,6 +97,8 @@ void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index,
+ 	mutex_lock(&hdcp_w->mutex);
+ 	hdcp_w->aconnector = aconnector;
+ 
++	hdcp_w->link.adjust.hdcp2.disable_type1 = disable_type1;
++
+ 	mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output);
+ 
+ 	schedule_delayed_work(&hdcp_w->property_validate_dwork, msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
+@@ -190,10 +193,16 @@ static void event_property_update(struct work_struct *work)
+ 		}
+ 	}
+ 
+-	if (hdcp_work->encryption_status != MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF)
+-		drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_ENABLED);
+-	else
++	if (hdcp_work->encryption_status != MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF) {
++		if (aconnector->base.state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE0 &&
++		    hdcp_work->encryption_status <= MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON)
++			drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_ENABLED);
++		else if (aconnector->base.state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE1 &&
++			 hdcp_work->encryption_status == MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON)
++			drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_ENABLED);
++	} else {
+ 		drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_DESIRED);
++	}
+ 
+ 
+ 	mutex_unlock(&hdcp_work->mutex);
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+index d3ba505d0696..098f7218f83a 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+@@ -54,8 +54,8 @@ struct hdcp_workqueue {
+ 	uint8_t max_link;
+ };
+ 
+-void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index,
+-		      struct amdgpu_dm_connector *aconnector);
++void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index, struct amdgpu_dm_connector *aconnector,
++		      bool disable_type1);
+ void hdcp_remove_display(struct hdcp_workqueue *work, unsigned int link_index, unsigned int display_index);
+ void hdcp_reset_display(struct hdcp_workqueue *work, unsigned int link_index);
+ void hdcp_handle_cpirq(struct hdcp_workqueue *work, unsigned int link_index);
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+index a74812977963..0f2f242710b3 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+@@ -417,7 +417,10 @@ enum mod_hdcp_status mod_hdcp_query_display(struct mod_hdcp *hdcp,
+ 	query->trace = &hdcp->connection.trace;
+ 	query->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
+ 
+-	mod_hdcp_hdcp1_get_link_encryption_status(hdcp, &query->encryption_status);
++	if (is_hdcp1(hdcp))
++		mod_hdcp_hdcp1_get_link_encryption_status(hdcp, &query->encryption_status);
++	else if (is_hdcp2(hdcp))
++		mod_hdcp_hdcp2_get_link_encryption_status(hdcp, &query->encryption_status);
+ 
+ out:
+ 	return status;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4507-drm-amd-display-Refactor-HDCP-to-handle-multiple-dis.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4507-drm-amd-display-Refactor-HDCP-to-handle-multiple-dis.patch
new file mode 100644
index 00000000..d1b0bdbb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4507-drm-amd-display-Refactor-HDCP-to-handle-multiple-dis.patch
@@ -0,0 +1,178 @@
+From 99a2fd8154613cbb8cc2720f94d56d7c1a75059b Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 28 Aug 2019 15:10:03 -0400
+Subject: [PATCH 4507/4736] drm/amd/display: Refactor HDCP to handle multiple
+ displays per link
+
+[Why]
+We need to do this to support HDCP over MST
+
+Currently we save a display per link, in a MST case we need to save
+multiple displays per link.
+
+[How]
+We can create an array per link to cache the displays, but it
+complicates the design. Instead we can use the module to cache the
+displays.
+
+Now we will always add all the displays to the module, but we use the
+adjustment flag to disable hdcp on all of them before they are added.
+
+When we want to enable hdcp we just query the display(cache), remove
+it then add it back with different adjustments. Its the similar for
+disable.
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 ++-----
+ .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c    | 53 ++++++++++---------
+ .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.h    |  9 ++--
+ 3 files changed, 40 insertions(+), 42 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 3828a19a87bb..9ca6806f7cef 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -5763,20 +5763,6 @@ static bool is_content_protection_different(struct drm_connector_state *state,
+ 	return false;
+ }
+ 
+-static void update_content_protection(struct drm_connector_state *state, const struct drm_connector *connector,
+-				      struct hdcp_workqueue *hdcp_w)
+-{
+-	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
+-	bool disable_type1 = state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE0 ? true : false;
+-
+-	if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
+-		hdcp_reset_display(hdcp_w, aconnector->dc_link->link_index);
+-		hdcp_add_display(hdcp_w, aconnector->dc_link->link_index, aconnector, disable_type1);
+-	} else if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
+-		hdcp_remove_display(hdcp_w, aconnector->dc_link->link_index, aconnector->base.index);
+-	}
+-
+-}
+ #endif
+ static void remove_stream(struct amdgpu_device *adev,
+ 			  struct amdgpu_crtc *acrtc,
+@@ -6740,7 +6726,11 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
+ 		}
+ 
+ 		if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
+-			update_content_protection(new_con_state, connector, adev->dm.hdcp_workqueue);
++			hdcp_update_display(
++				adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
++				new_con_state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE0 ? true : false,
++				new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED ? true
++													 : false);
+ 	}
+ #endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+index a2ad1390977d..53e382bff54d 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+@@ -87,43 +87,45 @@ static void process_output(struct hdcp_workqueue *hdcp_work)
+ 
+ }
+ 
+-void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index, struct amdgpu_dm_connector *aconnector,
+-		      bool disable_type1)
++void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
++			 unsigned int link_index,
++			 struct amdgpu_dm_connector *aconnector,
++			 bool disable_type1,
++			 bool enable_encryption)
+ {
+ 	struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
+ 	struct mod_hdcp_display *display = &hdcp_work[link_index].display;
+ 	struct mod_hdcp_link *link = &hdcp_work[link_index].link;
++	struct mod_hdcp_display_query query;
+ 
+ 	mutex_lock(&hdcp_w->mutex);
+ 	hdcp_w->aconnector = aconnector;
+ 
+-	hdcp_w->link.adjust.hdcp2.disable_type1 = disable_type1;
+-
+-	mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output);
+-
+-	schedule_delayed_work(&hdcp_w->property_validate_dwork, msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
+-
+-	process_output(hdcp_w);
+-
+-	mutex_unlock(&hdcp_w->mutex);
+-
+-}
+-
+-void hdcp_remove_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index,  unsigned int display_index)
+-{
+-	struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
+-
+-	mutex_lock(&hdcp_w->mutex);
++	query.display = NULL;
++	mod_hdcp_query_display(&hdcp_w->hdcp, aconnector->base.index, &query);
++
++	if (query.display != NULL) {
++		memcpy(display, query.display, sizeof(struct mod_hdcp_display));
++		mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output);
++
++		if (enable_encryption) {
++			display->adjust.disable = 0;
++			hdcp_w->link.adjust.hdcp2.disable_type1 = disable_type1;
++			schedule_delayed_work(&hdcp_w->property_validate_dwork,
++					      msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
++		} else {
++			display->adjust.disable = 1;
++			hdcp_w->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
++			cancel_delayed_work(&hdcp_w->property_validate_dwork);
++		}
+ 
+-	mod_hdcp_remove_display(&hdcp_w->hdcp, display_index, &hdcp_w->output);
++		display->state = MOD_HDCP_DISPLAY_ACTIVE;
++	}
+ 
+-	cancel_delayed_work(&hdcp_w->property_validate_dwork);
+-	hdcp_w->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
++	mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output);
+ 
+ 	process_output(hdcp_w);
+-
+ 	mutex_unlock(&hdcp_w->mutex);
+-
+ }
+ 
+ void hdcp_reset_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index)
+@@ -303,7 +305,10 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
+ 	link->dig_be = config->link_enc_inst;
+ 	link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1;
+ 	link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
++	display->adjust.disable = 1;
++	link->adjust.auth_delay = 2;
+ 
++	hdcp_update_display(hdcp_work, link_index, aconnector, false, false);
+ }
+ 
+ struct hdcp_workqueue *hdcp_create_workqueue(void *psp_context, struct cp_psp *cp_psp, struct dc *dc)
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+index 098f7218f83a..71e121f037cb 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+@@ -54,9 +54,12 @@ struct hdcp_workqueue {
+ 	uint8_t max_link;
+ };
+ 
+-void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index, struct amdgpu_dm_connector *aconnector,
+-		      bool disable_type1);
+-void hdcp_remove_display(struct hdcp_workqueue *work, unsigned int link_index, unsigned int display_index);
++void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
++			 unsigned int link_index,
++			 struct amdgpu_dm_connector *aconnector,
++			 bool disable_type1,
++			 bool enable_encryption);
++
+ void hdcp_reset_display(struct hdcp_workqueue *work, unsigned int link_index);
+ void hdcp_handle_cpirq(struct hdcp_workqueue *work, unsigned int link_index);
+ void hdcp_destroy(struct hdcp_workqueue *work);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4508-drm-amd-display-add-force-Type0-1-flag.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4508-drm-amd-display-add-force-Type0-1-flag.patch
new file mode 100644
index 00000000..58278366
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4508-drm-amd-display-add-force-Type0-1-flag.patch
@@ -0,0 +1,157 @@
+From bc8f313777b528428a92ed7477258eb6c38dbbe0 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 29 Aug 2019 15:26:54 -0400
+Subject: [PATCH 4508/4736] drm/amd/display: add force Type0/1 flag
+
+[Why]
+Before we had a disable_type1 flag, this forced HDCP 2.2 to type0
+There was no way to force type1.
+
+[How]
+Remove disable_type1 flag and instead add a flag to force type0/1.
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c    |  2 +-
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c   | 12 +++++++++---
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h   |  2 +-
+ .../drm/amd/display/modules/hdcp/hdcp2_transition.c  |  2 +-
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c  |  7 +++++--
+ drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h   | 11 +++++++++--
+ 6 files changed, 26 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 9ca6806f7cef..430008124373 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -6728,7 +6728,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
+ 		if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
+ 			hdcp_update_display(
+ 				adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
+-				new_con_state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE0 ? true : false,
++				new_con_state->hdcp_content_type,
+ 				new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED ? true
+ 													 : false);
+ 	}
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+index 53e382bff54d..244a8e80334a 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+@@ -90,7 +90,7 @@ static void process_output(struct hdcp_workqueue *hdcp_work)
+ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
+ 			 unsigned int link_index,
+ 			 struct amdgpu_dm_connector *aconnector,
+-			 bool disable_type1,
++			 uint8_t content_type,
+ 			 bool enable_encryption)
+ {
+ 	struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
+@@ -108,9 +108,15 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
+ 		memcpy(display, query.display, sizeof(struct mod_hdcp_display));
+ 		mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output);
+ 
++		hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0;
++
+ 		if (enable_encryption) {
+ 			display->adjust.disable = 0;
+-			hdcp_w->link.adjust.hdcp2.disable_type1 = disable_type1;
++			if (content_type == DRM_MODE_HDCP_CONTENT_TYPE0)
++				hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0;
++			else if (content_type == DRM_MODE_HDCP_CONTENT_TYPE1)
++				hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_1;
++
+ 			schedule_delayed_work(&hdcp_w->property_validate_dwork,
+ 					      msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
+ 		} else {
+@@ -308,7 +314,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
+ 	display->adjust.disable = 1;
+ 	link->adjust.auth_delay = 2;
+ 
+-	hdcp_update_display(hdcp_work, link_index, aconnector, false, false);
++	hdcp_update_display(hdcp_work, link_index, aconnector, DRM_MODE_HDCP_CONTENT_TYPE0, false);
+ }
+ 
+ struct hdcp_workqueue *hdcp_create_workqueue(void *psp_context, struct cp_psp *cp_psp, struct dc *dc)
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+index 71e121f037cb..6abde86bce4a 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+@@ -57,7 +57,7 @@ struct hdcp_workqueue {
+ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
+ 			 unsigned int link_index,
+ 			 struct amdgpu_dm_connector *aconnector,
+-			 bool disable_type1,
++			 uint8_t content_type,
+ 			 bool enable_encryption);
+ 
+ void hdcp_reset_display(struct hdcp_workqueue *work, unsigned int link_index);
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
+index 94a0e5fa931b..e8043c903a84 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
+@@ -570,7 +570,7 @@ enum mod_hdcp_status mod_hdcp_hdcp2_dp_transition(struct mod_hdcp *hdcp,
+ 			break;
+ 		} else if (input->link_integrity_check_dp != PASS) {
+ 			if (hdcp->connection.hdcp2_retry_count >= 1)
+-				adjust->hdcp2.disable_type1 = 1;
++				adjust->hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0;
+ 			fail_and_restart_in_ms(0, &status, output);
+ 			break;
+ 		} else if (event_ctx->rx_id_list_ready && conn->is_repeater) {
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+index a9511612f426..2dd5feec8e6c 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+@@ -358,10 +358,13 @@ enum mod_hdcp_status mod_hdcp_hdcp2_create_session(struct mod_hdcp *hdcp)
+ 
+ 	hdcp_cmd->in_msg.hdcp2_create_session_v2.display_handle = display->index;
+ 
+-	if (hdcp->connection.link.adjust.hdcp2.disable_type1)
++	if (hdcp->connection.link.adjust.hdcp2.force_type == MOD_HDCP_FORCE_TYPE_0)
+ 		hdcp_cmd->in_msg.hdcp2_create_session_v2.negotiate_content_type =
+ 			TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__FORCE_TYPE0;
+-	else
++	else if (hdcp->connection.link.adjust.hdcp2.force_type == MOD_HDCP_FORCE_TYPE_1)
++		hdcp_cmd->in_msg.hdcp2_create_session_v2.negotiate_content_type =
++			TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__FORCE_TYPE1;
++	else if (hdcp->connection.link.adjust.hdcp2.force_type == MOD_HDCP_FORCE_TYPE_MAX)
+ 		hdcp_cmd->in_msg.hdcp2_create_session_v2.negotiate_content_type =
+ 			TA_HDCP2_CONTENT_TYPE_NEGOTIATION_TYPE__MAX_SUPPORTED;
+ 
+diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+index 97ecbf5bfec1..ff2bb2bfbb53 100644
+--- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+@@ -158,12 +158,18 @@ struct mod_hdcp_link_adjustment_hdcp1 {
+ 	uint8_t reserved		: 6;
+ };
+ 
++enum mod_hdcp_force_hdcp_type {
++	MOD_HDCP_FORCE_TYPE_MAX = 0,
++	MOD_HDCP_FORCE_TYPE_0,
++	MOD_HDCP_FORCE_TYPE_1
++};
++
+ struct mod_hdcp_link_adjustment_hdcp2 {
+ 	uint8_t disable			: 1;
+-	uint8_t disable_type1		: 1;
++	uint8_t force_type		: 2;
+ 	uint8_t force_no_stored_km	: 1;
+ 	uint8_t increase_h_prime_timeout: 1;
+-	uint8_t reserved		: 4;
++	uint8_t reserved		: 3;
+ };
+ 
+ struct mod_hdcp_link_adjustment {
+@@ -185,6 +191,7 @@ struct mod_hdcp_trace {
+ enum mod_hdcp_encryption_status {
+ 	MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF = 0,
+ 	MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON,
++	MOD_HDCP_ENCRYPTION_STATUS_HDCP2_ON,
+ 	MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON,
+ 	MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4509-drm-amd-display-Refactor-HDCP-encryption-status-upda.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4509-drm-amd-display-Refactor-HDCP-encryption-status-upda.patch
new file mode 100644
index 00000000..d7deda01
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4509-drm-amd-display-Refactor-HDCP-encryption-status-upda.patch
@@ -0,0 +1,94 @@
+From e3fa5bc34929d64e2706634adbd8a6c369a7bbbe Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 4 Sep 2019 16:52:20 -0400
+Subject: [PATCH 4509/4736] drm/amd/display: Refactor HDCP encryption status
+ update
+
+[Why]
+The old way was to poll PSP and update the properties. But due to a
+limitation in the PSP interface this doesn't work for MST.
+
+[How]
+According to PSP if set_encryption return success, the link is encrypted
+and the only way it will not be is if we get a link loss(which we handle
+already).
+
+So this method should be good enough to report HDCP status.
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c |  3 +--
+ .../gpu/drm/amd/display/modules/hdcp/hdcp.c    | 18 ++++++++++++++----
+ .../gpu/drm/amd/display/modules/inc/mod_hdcp.h |  4 ++--
+ 3 files changed, 17 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+index 244a8e80334a..f6864a51891a 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+@@ -85,6 +85,7 @@ static void process_output(struct hdcp_workqueue *hdcp_work)
+ 		schedule_delayed_work(&hdcp_work->watchdog_timer_dwork,
+ 				      msecs_to_jiffies(output.watchdog_timer_delay));
+ 
++	schedule_delayed_work(&hdcp_work->property_validate_dwork, msecs_to_jiffies(0));
+ }
+ 
+ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
+@@ -234,8 +235,6 @@ static void event_property_validate(struct work_struct *work)
+ 		schedule_work(&hdcp_work->property_update_work);
+ 	}
+ 
+-	schedule_delayed_work(&hdcp_work->property_validate_dwork, msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
+-
+ 	mutex_unlock(&hdcp_work->mutex);
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+index 0f2f242710b3..cbb5e9c063ec 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+@@ -417,10 +417,20 @@ enum mod_hdcp_status mod_hdcp_query_display(struct mod_hdcp *hdcp,
+ 	query->trace = &hdcp->connection.trace;
+ 	query->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
+ 
+-	if (is_hdcp1(hdcp))
+-		mod_hdcp_hdcp1_get_link_encryption_status(hdcp, &query->encryption_status);
+-	else if (is_hdcp2(hdcp))
+-		mod_hdcp_hdcp2_get_link_encryption_status(hdcp, &query->encryption_status);
++	if (is_display_encryption_enabled(display)) {
++		if (is_hdcp1(hdcp)) {
++			query->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON;
++		} else if (is_hdcp2(hdcp)) {
++			if (query->link->adjust.hdcp2.force_type == MOD_HDCP_FORCE_TYPE_0)
++				query->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON;
++			else if (query->link->adjust.hdcp2.force_type == MOD_HDCP_FORCE_TYPE_1)
++				query->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON;
++			else
++				query->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP2_ON;
++		}
++	} else {
++		query->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
++	}
+ 
+ out:
+ 	return status;
+diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+index ff2bb2bfbb53..f2a0e1a064da 100644
+--- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+@@ -191,9 +191,9 @@ struct mod_hdcp_trace {
+ enum mod_hdcp_encryption_status {
+ 	MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF = 0,
+ 	MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON,
+-	MOD_HDCP_ENCRYPTION_STATUS_HDCP2_ON,
+ 	MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON,
+-	MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON
++	MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON,
++	MOD_HDCP_ENCRYPTION_STATUS_HDCP2_ON
+ };
+ 
+ /* per link events dm has to notify to hdcp module */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4510-drm-amd-display-add-and-use-defines-from-drm_hdcp.h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4510-drm-amd-display-add-and-use-defines-from-drm_hdcp.h.patch
new file mode 100644
index 00000000..0c7d4f74
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4510-drm-amd-display-add-and-use-defines-from-drm_hdcp.h.patch
@@ -0,0 +1,242 @@
+From 33346f2afd0be41522106850c13d8c6d76721fc6 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Mon, 21 Oct 2019 14:40:55 -0400
+Subject: [PATCH 4510/4736] drm/amd/display: add and use defines from
+ drm_hdcp.h
+
+[Why]
+These defines/macros exist already no need to redefine them
+
+[How]
+Use the defines/macros from drm_hdcp.h
+
+-we share the rxstatus between HDMI and DP (2 bytes), But upstream
+defines/macros for HDMI are for 1 byte. So we need to create a separate
+rxstatus for HDMI
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../gpu/drm/amd/display/modules/hdcp/hdcp.h   | 40 ++++++++-----------
+ .../display/modules/hdcp/hdcp1_execution.c    | 22 +++++-----
+ .../display/modules/hdcp/hdcp2_execution.c    | 24 +++++------
+ 3 files changed, 37 insertions(+), 49 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+index 9887c5ea6d5f..bfb32afc1868 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+@@ -29,34 +29,28 @@
+ #include "mod_hdcp.h"
+ #include "hdcp_log.h"
+ 
+-#define BCAPS_READY_MASK				0x20
+-#define BCAPS_REPEATER_MASK				0x40
+-#define BSTATUS_DEVICE_COUNT_MASK			0X007F
+-#define BSTATUS_MAX_DEVS_EXCEEDED_MASK			0x0080
++#include <drm/drm_hdcp.h>
++#include <drm/drm_dp_helper.h>
++
++/* TODO:
++ * Replace below defines with these
++ *
++ * #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x)        (x & BIT(3))
++ * #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x)        (x & BIT(3))
++ * #define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x)     ((x) & 0x3)
++ * #define HDCP_2_2_HDMI_RXSTATUS_READY(x)         ((x) & BIT(2))
++ * #define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x)    ((x) & BIT(3))
++ *
++ * Currently we share rx_status between HDMI and DP, so we use 16bits
++ * The upstream defines work with 1bytes at a time. So we need to
++ * split the HDMI rxstatus into 2bytes before we can use usptream defs
++ */
++
+ #define BSTATUS_MAX_CASCADE_EXCEEDED_MASK		0x0800
+-#define BCAPS_HDCP_CAPABLE_MASK_DP			0x01
+-#define BCAPS_REPEATER_MASK_DP				0x02
+-#define BSTATUS_READY_MASK_DP				0x01
+-#define BSTATUS_R0_P_AVAILABLE_MASK_DP			0x02
+-#define BSTATUS_LINK_INTEGRITY_FAILURE_MASK_DP		0x04
+-#define BSTATUS_REAUTH_REQUEST_MASK_DP			0x08
+-#define BINFO_DEVICE_COUNT_MASK_DP			0X007F
+-#define BINFO_MAX_DEVS_EXCEEDED_MASK_DP			0x0080
+ #define BINFO_MAX_CASCADE_EXCEEDED_MASK_DP		0x0800
+-
+-#define VERSION_HDCP2_MASK				0x04
+ #define RXSTATUS_MSG_SIZE_MASK				0x03FF
+ #define RXSTATUS_READY_MASK				0x0400
+ #define RXSTATUS_REAUTH_REQUEST_MASK			0x0800
+-#define RXIDLIST_DEVICE_COUNT_LOWER_MASK		0xf0
+-#define RXIDLIST_DEVICE_COUNT_UPPER_MASK		0x01
+-#define RXCAPS_BYTE2_HDCP2_VERSION_DP			0x02
+-#define RXCAPS_BYTE0_HDCP_CAPABLE_MASK_DP		0x02
+-#define RXSTATUS_READY_MASK_DP				0x0001
+-#define RXSTATUS_H_P_AVAILABLE_MASK_DP			0x0002
+-#define RXSTATUS_PAIRING_AVAILABLE_MASK_DP		0x0004
+-#define RXSTATUS_REAUTH_REQUEST_MASK_DP			0x0008
+-#define RXSTATUS_LINK_INTEGRITY_FAILURE_MASK_DP		0x0010
+ 
+ enum mod_hdcp_trans_input_result {
+ 	UNKNOWN = 0,
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+index 3db4a7da414f..4618abd6504f 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+@@ -41,17 +41,17 @@ static inline enum mod_hdcp_status validate_bksv(struct mod_hdcp *hdcp)
+ static inline enum mod_hdcp_status check_ksv_ready(struct mod_hdcp *hdcp)
+ {
+ 	if (is_dp_hdcp(hdcp))
+-		return (hdcp->auth.msg.hdcp1.bstatus & BSTATUS_READY_MASK_DP) ?
++		return (hdcp->auth.msg.hdcp1.bstatus & DP_BSTATUS_READY) ?
+ 				MOD_HDCP_STATUS_SUCCESS :
+ 				MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY;
+-	return (hdcp->auth.msg.hdcp1.bcaps & BCAPS_READY_MASK) ?
++	return (hdcp->auth.msg.hdcp1.bcaps & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY) ?
+ 			MOD_HDCP_STATUS_SUCCESS :
+ 			MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY;
+ }
+ 
+ static inline enum mod_hdcp_status check_hdcp_capable_dp(struct mod_hdcp *hdcp)
+ {
+-	return (hdcp->auth.msg.hdcp1.bcaps & BCAPS_HDCP_CAPABLE_MASK_DP) ?
++	return (hdcp->auth.msg.hdcp1.bcaps & DP_BCAPS_HDCP_CAPABLE) ?
+ 			MOD_HDCP_STATUS_SUCCESS :
+ 			MOD_HDCP_STATUS_HDCP1_NOT_CAPABLE;
+ }
+@@ -61,7 +61,7 @@ static inline enum mod_hdcp_status check_r0p_available_dp(struct mod_hdcp *hdcp)
+ 	enum mod_hdcp_status status;
+ 	if (is_dp_hdcp(hdcp)) {
+ 		status = (hdcp->auth.msg.hdcp1.bstatus &
+-				BSTATUS_R0_P_AVAILABLE_MASK_DP) ?
++				DP_BSTATUS_R0_PRIME_READY) ?
+ 			MOD_HDCP_STATUS_SUCCESS :
+ 			MOD_HDCP_STATUS_HDCP1_R0_PRIME_PENDING;
+ 	} else {
+@@ -74,7 +74,7 @@ static inline enum mod_hdcp_status check_link_integrity_dp(
+ 		struct mod_hdcp *hdcp)
+ {
+ 	return (hdcp->auth.msg.hdcp1.bstatus &
+-			BSTATUS_LINK_INTEGRITY_FAILURE_MASK_DP) ?
++			DP_BSTATUS_LINK_FAILURE) ?
+ 			MOD_HDCP_STATUS_HDCP1_LINK_INTEGRITY_FAILURE :
+ 			MOD_HDCP_STATUS_SUCCESS;
+ }
+@@ -82,7 +82,7 @@ static inline enum mod_hdcp_status check_link_integrity_dp(
+ static inline enum mod_hdcp_status check_no_reauthentication_request_dp(
+ 		struct mod_hdcp *hdcp)
+ {
+-	return (hdcp->auth.msg.hdcp1.bstatus & BSTATUS_REAUTH_REQUEST_MASK_DP) ?
++	return (hdcp->auth.msg.hdcp1.bstatus & DP_BSTATUS_REAUTH_REQ) ?
+ 			MOD_HDCP_STATUS_HDCP1_REAUTH_REQUEST_ISSUED :
+ 			MOD_HDCP_STATUS_SUCCESS;
+ }
+@@ -109,13 +109,11 @@ static inline enum mod_hdcp_status check_no_max_devs(struct mod_hdcp *hdcp)
+ 	enum mod_hdcp_status status;
+ 
+ 	if (is_dp_hdcp(hdcp))
+-		status = (hdcp->auth.msg.hdcp1.binfo_dp &
+-				BINFO_MAX_DEVS_EXCEEDED_MASK_DP) ?
++		status = DRM_HDCP_MAX_DEVICE_EXCEEDED(hdcp->auth.msg.hdcp1.binfo_dp) ?
+ 				MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE :
+ 				MOD_HDCP_STATUS_SUCCESS;
+ 	else
+-		status = (hdcp->auth.msg.hdcp1.bstatus &
+-				BSTATUS_MAX_DEVS_EXCEEDED_MASK) ?
++		status = DRM_HDCP_MAX_DEVICE_EXCEEDED(hdcp->auth.msg.hdcp1.bstatus) ?
+ 				MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE :
+ 				MOD_HDCP_STATUS_SUCCESS;
+ 	return status;
+@@ -124,8 +122,8 @@ static inline enum mod_hdcp_status check_no_max_devs(struct mod_hdcp *hdcp)
+ static inline uint8_t get_device_count(struct mod_hdcp *hdcp)
+ {
+ 	return is_dp_hdcp(hdcp) ?
+-			(hdcp->auth.msg.hdcp1.binfo_dp & BINFO_DEVICE_COUNT_MASK_DP) :
+-			(hdcp->auth.msg.hdcp1.bstatus & BSTATUS_DEVICE_COUNT_MASK);
++			DRM_HDCP_NUM_DOWNSTREAM(hdcp->auth.msg.hdcp1.binfo_dp) :
++			DRM_HDCP_NUM_DOWNSTREAM(hdcp->auth.msg.hdcp1.bstatus);
+ }
+ 
+ static inline enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp)
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
+index c93c8098d972..7513b3b3c353 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
+@@ -30,7 +30,7 @@ static inline enum mod_hdcp_status check_receiver_id_list_ready(struct mod_hdcp
+ 	uint8_t is_ready = 0;
+ 
+ 	if (is_dp_hdcp(hdcp))
+-		is_ready = (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_READY_MASK_DP) ? 1 : 0;
++		is_ready = HDCP_2_2_DP_RXSTATUS_READY(hdcp->auth.msg.hdcp2.rxstatus) ? 1 : 0;
+ 	else
+ 		is_ready = ((hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_READY_MASK) &&
+ 				(hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK)) ? 1 : 0;
+@@ -43,14 +43,12 @@ static inline enum mod_hdcp_status check_hdcp2_capable(struct mod_hdcp *hdcp)
+ 	enum mod_hdcp_status status;
+ 
+ 	if (is_dp_hdcp(hdcp))
+-		status = ((hdcp->auth.msg.hdcp2.rxcaps_dp[2] &
+-						RXCAPS_BYTE0_HDCP_CAPABLE_MASK_DP) &&
+-				(hdcp->auth.msg.hdcp2.rxcaps_dp[0] ==
+-						RXCAPS_BYTE2_HDCP2_VERSION_DP)) ?
++		status = (hdcp->auth.msg.hdcp2.rxcaps_dp[2] & HDCP_2_2_RX_CAPS_VERSION_VAL) &&
++				HDCP_2_2_DP_HDCP_CAPABLE(hdcp->auth.msg.hdcp2.rxcaps_dp[0]) ?
+ 				MOD_HDCP_STATUS_SUCCESS :
+ 				MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE;
+ 	else
+-		status = (hdcp->auth.msg.hdcp2.hdcp2version_hdmi & VERSION_HDCP2_MASK) ?
++		status = (hdcp->auth.msg.hdcp2.hdcp2version_hdmi & HDCP_2_2_HDMI_SUPPORT_MASK) ?
+ 				MOD_HDCP_STATUS_SUCCESS :
+ 				MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE;
+ 	return status;
+@@ -62,8 +60,7 @@ static inline enum mod_hdcp_status check_reauthentication_request(
+ 	uint8_t ret = 0;
+ 
+ 	if (is_dp_hdcp(hdcp))
+-		ret = (hdcp->auth.msg.hdcp2.rxstatus &
+-				RXSTATUS_REAUTH_REQUEST_MASK_DP) ?
++		ret = HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(hdcp->auth.msg.hdcp2.rxstatus) ?
+ 				MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST :
+ 				MOD_HDCP_STATUS_SUCCESS;
+ 	else
+@@ -76,8 +73,7 @@ static inline enum mod_hdcp_status check_reauthentication_request(
+ static inline enum mod_hdcp_status check_link_integrity_failure_dp(
+ 		struct mod_hdcp *hdcp)
+ {
+-	return (hdcp->auth.msg.hdcp2.rxstatus &
+-			RXSTATUS_LINK_INTEGRITY_FAILURE_MASK_DP) ?
++	return HDCP_2_2_DP_RXSTATUS_LINK_FAILED(hdcp->auth.msg.hdcp2.rxstatus) ?
+ 			MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE :
+ 			MOD_HDCP_STATUS_SUCCESS;
+ }
+@@ -111,7 +107,7 @@ static enum mod_hdcp_status check_h_prime_available(struct mod_hdcp *hdcp)
+ 		goto out;
+ 
+ 	if (is_dp_hdcp(hdcp)) {
+-		status = (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_H_P_AVAILABLE_MASK_DP) ?
++		status = HDCP_2_2_DP_RXSTATUS_H_PRIME(hdcp->auth.msg.hdcp2.rxstatus) ?
+ 				MOD_HDCP_STATUS_SUCCESS :
+ 				MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING;
+ 	} else {
+@@ -134,7 +130,7 @@ static enum mod_hdcp_status check_pairing_info_available(struct mod_hdcp *hdcp)
+ 		goto out;
+ 
+ 	if (is_dp_hdcp(hdcp)) {
+-		status = (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_PAIRING_AVAILABLE_MASK_DP) ?
++		status = HDCP_2_2_DP_RXSTATUS_PAIRING(hdcp->auth.msg.hdcp2.rxstatus) ?
+ 				MOD_HDCP_STATUS_SUCCESS :
+ 				MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING;
+ 	} else {
+@@ -197,8 +193,8 @@ static enum mod_hdcp_status check_stream_ready_available(struct mod_hdcp *hdcp)
+ 
+ static inline uint8_t get_device_count(struct mod_hdcp *hdcp)
+ {
+-	return ((hdcp->auth.msg.hdcp2.rx_id_list[2] & RXIDLIST_DEVICE_COUNT_LOWER_MASK) >> 4) +
+-		((hdcp->auth.msg.hdcp2.rx_id_list[1] & RXIDLIST_DEVICE_COUNT_UPPER_MASK) << 4);
++	return HDCP_2_2_DEV_COUNT_LO(hdcp->auth.msg.hdcp2.rx_id_list[2]) +
++			(HDCP_2_2_DEV_COUNT_HI(hdcp->auth.msg.hdcp2.rx_id_list[1]) << 4);
+ }
+ 
+ static enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4511-drm-amd-display-use-drm-defines-for-MAX-CASCADE-MASK.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4511-drm-amd-display-use-drm-defines-for-MAX-CASCADE-MASK.patch
new file mode 100644
index 00000000..20585ba3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4511-drm-amd-display-use-drm-defines-for-MAX-CASCADE-MASK.patch
@@ -0,0 +1,75 @@
+From 50a7be8911fff66f9b4a719d80aab7cf89967fc1 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 24 Oct 2019 16:07:43 -0400
+Subject: [PATCH 4511/4736] drm/amd/display: use drm defines for MAX CASCADE
+ MASK
+
+[Why]
+drm already has this define
+
+[How]
+drm Mask is 0x08 vs 0x0800. The reason is because drm mask
+works on a byte.        ^^
+                 =======||
+                 ||
+Since the first byte is always zero we can ignore it and only check the
+second byte.
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h    |  4 ----
+ .../drm/amd/display/modules/hdcp/hdcp1_execution.c | 14 ++++++--------
+ 2 files changed, 6 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+index bfb32afc1868..f6bba487d1d4 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+@@ -35,8 +35,6 @@
+ /* TODO:
+  * Replace below defines with these
+  *
+- * #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x)        (x & BIT(3))
+- * #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x)        (x & BIT(3))
+  * #define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x)     ((x) & 0x3)
+  * #define HDCP_2_2_HDMI_RXSTATUS_READY(x)         ((x) & BIT(2))
+  * #define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x)    ((x) & BIT(3))
+@@ -46,8 +44,6 @@
+  * split the HDMI rxstatus into 2bytes before we can use usptream defs
+  */
+ 
+-#define BSTATUS_MAX_CASCADE_EXCEEDED_MASK		0x0800
+-#define BINFO_MAX_CASCADE_EXCEEDED_MASK_DP		0x0800
+ #define RXSTATUS_MSG_SIZE_MASK				0x03FF
+ #define RXSTATUS_READY_MASK				0x0400
+ #define RXSTATUS_REAUTH_REQUEST_MASK			0x0800
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+index 4618abd6504f..4d11041a8c6f 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+@@ -92,15 +92,13 @@ static inline enum mod_hdcp_status check_no_max_cascade(struct mod_hdcp *hdcp)
+ 	enum mod_hdcp_status status;
+ 
+ 	if (is_dp_hdcp(hdcp))
+-		status = (hdcp->auth.msg.hdcp1.binfo_dp &
+-				BINFO_MAX_CASCADE_EXCEEDED_MASK_DP) ?
+-			MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE :
+-			MOD_HDCP_STATUS_SUCCESS;
++		status = DRM_HDCP_MAX_CASCADE_EXCEEDED(hdcp->auth.msg.hdcp1.binfo_dp >> 8)
++				 ? MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE
++				 : MOD_HDCP_STATUS_SUCCESS;
+ 	else
+-		status = (hdcp->auth.msg.hdcp1.bstatus &
+-				BSTATUS_MAX_CASCADE_EXCEEDED_MASK) ?
+-				MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE :
+-				MOD_HDCP_STATUS_SUCCESS;
++		status = DRM_HDCP_MAX_CASCADE_EXCEEDED(hdcp->auth.msg.hdcp1.bstatus >> 8)
++				 ? MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE
++				 : MOD_HDCP_STATUS_SUCCESS;
+ 	return status;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4512-drm-amd-display-split-rxstatus-for-hdmi-and-dp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4512-drm-amd-display-split-rxstatus-for-hdmi-and-dp.patch
new file mode 100644
index 00000000..92731dd0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4512-drm-amd-display-split-rxstatus-for-hdmi-and-dp.patch
@@ -0,0 +1,196 @@
+From bb329a5c7eb0e2584576fe336b329f87d8066cec Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Thu, 24 Oct 2019 16:07:58 -0400
+Subject: [PATCH 4512/4736] drm/amd/display: split rxstatus for hdmi and dp
+
+[Why]
+Currently we share rxstatus between HDMI and DP, so we use 16bits
+The drm defines work with 1bytes at a time. So we need to
+split the HDMI rxstatus into 2bytes before we can use drm defines
+
+[How]
+-create rxstatus for dp and hdmi. rxstatus for hdmi is split into bytes
+using arrays.
+-use drm_hdcp defines for the remaining structs
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../gpu/drm/amd/display/modules/hdcp/hdcp.h   | 20 ++---------
+ .../display/modules/hdcp/hdcp2_execution.c    | 35 +++++++++++--------
+ .../drm/amd/display/modules/hdcp/hdcp_ddc.c   |  2 +-
+ 3 files changed, 24 insertions(+), 33 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+index f6bba487d1d4..f98d3d9ecb6d 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+@@ -32,22 +32,6 @@
+ #include <drm/drm_hdcp.h>
+ #include <drm/drm_dp_helper.h>
+ 
+-/* TODO:
+- * Replace below defines with these
+- *
+- * #define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x)     ((x) & 0x3)
+- * #define HDCP_2_2_HDMI_RXSTATUS_READY(x)         ((x) & BIT(2))
+- * #define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x)    ((x) & BIT(3))
+- *
+- * Currently we share rx_status between HDMI and DP, so we use 16bits
+- * The upstream defines work with 1bytes at a time. So we need to
+- * split the HDMI rxstatus into 2bytes before we can use usptream defs
+- */
+-
+-#define RXSTATUS_MSG_SIZE_MASK				0x03FF
+-#define RXSTATUS_READY_MASK				0x0400
+-#define RXSTATUS_REAUTH_REQUEST_MASK			0x0800
+-
+ enum mod_hdcp_trans_input_result {
+ 	UNKNOWN = 0,
+ 	PASS,
+@@ -150,7 +134,7 @@ struct mod_hdcp_message_hdcp1 {
+ struct mod_hdcp_message_hdcp2 {
+ 	uint8_t		hdcp2version_hdmi;
+ 	uint8_t		rxcaps_dp[3];
+-	uint16_t	rxstatus;
++	uint8_t		rxstatus[2];
+ 
+ 	uint8_t		ake_init[12];
+ 	uint8_t		ake_cert[534];
+@@ -167,7 +151,7 @@ struct mod_hdcp_message_hdcp2 {
+ 	uint8_t		repeater_auth_stream_manage[68]; // 6 + 2 * 31
+ 	uint16_t	stream_manage_size;
+ 	uint8_t		repeater_auth_stream_ready[33];
+-
++	uint8_t		rxstatus_dp;
+ 	uint8_t		content_stream_type_dp[2];
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
+index 7513b3b3c353..110c8620907b 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c
+@@ -30,10 +30,11 @@ static inline enum mod_hdcp_status check_receiver_id_list_ready(struct mod_hdcp
+ 	uint8_t is_ready = 0;
+ 
+ 	if (is_dp_hdcp(hdcp))
+-		is_ready = HDCP_2_2_DP_RXSTATUS_READY(hdcp->auth.msg.hdcp2.rxstatus) ? 1 : 0;
++		is_ready = HDCP_2_2_DP_RXSTATUS_READY(hdcp->auth.msg.hdcp2.rxstatus_dp) ? 1 : 0;
+ 	else
+-		is_ready = ((hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_READY_MASK) &&
+-				(hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK)) ? 1 : 0;
++		is_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(hdcp->auth.msg.hdcp2.rxstatus[0]) &&
++				(HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 |
++						hdcp->auth.msg.hdcp2.rxstatus[0])) ? 1 : 0;
+ 	return is_ready ? MOD_HDCP_STATUS_SUCCESS :
+ 			MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY;
+ }
+@@ -60,11 +61,11 @@ static inline enum mod_hdcp_status check_reauthentication_request(
+ 	uint8_t ret = 0;
+ 
+ 	if (is_dp_hdcp(hdcp))
+-		ret = HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(hdcp->auth.msg.hdcp2.rxstatus) ?
++		ret = HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(hdcp->auth.msg.hdcp2.rxstatus_dp) ?
+ 				MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST :
+ 				MOD_HDCP_STATUS_SUCCESS;
+ 	else
+-		ret = (hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_REAUTH_REQUEST_MASK) ?
++		ret = HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(hdcp->auth.msg.hdcp2.rxstatus[0]) ?
+ 				MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST :
+ 				MOD_HDCP_STATUS_SUCCESS;
+ 	return ret;
+@@ -73,7 +74,7 @@ static inline enum mod_hdcp_status check_reauthentication_request(
+ static inline enum mod_hdcp_status check_link_integrity_failure_dp(
+ 		struct mod_hdcp *hdcp)
+ {
+-	return HDCP_2_2_DP_RXSTATUS_LINK_FAILED(hdcp->auth.msg.hdcp2.rxstatus) ?
++	return HDCP_2_2_DP_RXSTATUS_LINK_FAILED(hdcp->auth.msg.hdcp2.rxstatus_dp) ?
+ 			MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE :
+ 			MOD_HDCP_STATUS_SUCCESS;
+ }
+@@ -88,7 +89,8 @@ static enum mod_hdcp_status check_ake_cert_available(struct mod_hdcp *hdcp)
+ 	} else {
+ 		status = mod_hdcp_read_rxstatus(hdcp);
+ 		if (status == MOD_HDCP_STATUS_SUCCESS) {
+-			size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++			size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 |
++			       hdcp->auth.msg.hdcp2.rxstatus[0];
+ 			status = (size == sizeof(hdcp->auth.msg.hdcp2.ake_cert)) ?
+ 					MOD_HDCP_STATUS_SUCCESS :
+ 					MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING;
+@@ -107,11 +109,12 @@ static enum mod_hdcp_status check_h_prime_available(struct mod_hdcp *hdcp)
+ 		goto out;
+ 
+ 	if (is_dp_hdcp(hdcp)) {
+-		status = HDCP_2_2_DP_RXSTATUS_H_PRIME(hdcp->auth.msg.hdcp2.rxstatus) ?
++		status = HDCP_2_2_DP_RXSTATUS_H_PRIME(hdcp->auth.msg.hdcp2.rxstatus_dp) ?
+ 				MOD_HDCP_STATUS_SUCCESS :
+ 				MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING;
+ 	} else {
+-		size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++		size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 |
++		       hdcp->auth.msg.hdcp2.rxstatus[0];
+ 		status = (size == sizeof(hdcp->auth.msg.hdcp2.ake_h_prime)) ?
+ 				MOD_HDCP_STATUS_SUCCESS :
+ 				MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING;
+@@ -130,11 +133,12 @@ static enum mod_hdcp_status check_pairing_info_available(struct mod_hdcp *hdcp)
+ 		goto out;
+ 
+ 	if (is_dp_hdcp(hdcp)) {
+-		status = HDCP_2_2_DP_RXSTATUS_PAIRING(hdcp->auth.msg.hdcp2.rxstatus) ?
++		status = HDCP_2_2_DP_RXSTATUS_PAIRING(hdcp->auth.msg.hdcp2.rxstatus_dp) ?
+ 				MOD_HDCP_STATUS_SUCCESS :
+ 				MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING;
+ 	} else {
+-		size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++		size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 |
++		       hdcp->auth.msg.hdcp2.rxstatus[0];
+ 		status = (size == sizeof(hdcp->auth.msg.hdcp2.ake_pairing_info)) ?
+ 				MOD_HDCP_STATUS_SUCCESS :
+ 				MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING;
+@@ -161,7 +165,8 @@ static enum mod_hdcp_status poll_l_prime_available(struct mod_hdcp *hdcp)
+ 			if (status != MOD_HDCP_STATUS_SUCCESS)
+ 				break;
+ 
+-			size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++			size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 |
++			       hdcp->auth.msg.hdcp2.rxstatus[0];
+ 			status = (size == sizeof(hdcp->auth.msg.hdcp2.lc_l_prime)) ?
+ 					MOD_HDCP_STATUS_SUCCESS :
+ 					MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING;
+@@ -182,7 +187,8 @@ static enum mod_hdcp_status check_stream_ready_available(struct mod_hdcp *hdcp)
+ 		status = mod_hdcp_read_rxstatus(hdcp);
+ 		if (status != MOD_HDCP_STATUS_SUCCESS)
+ 			goto out;
+-		size = hdcp->auth.msg.hdcp2.rxstatus & RXSTATUS_MSG_SIZE_MASK;
++		size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 |
++		       hdcp->auth.msg.hdcp2.rxstatus[0];
+ 		status = (size == sizeof(hdcp->auth.msg.hdcp2.repeater_auth_stream_ready)) ?
+ 				MOD_HDCP_STATUS_SUCCESS :
+ 				MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING;
+@@ -234,7 +240,8 @@ static uint8_t process_rxstatus(struct mod_hdcp *hdcp,
+ 						sizeof(hdcp->auth.msg.hdcp2.rx_id_list);
+ 			else
+ 				hdcp->auth.msg.hdcp2.rx_id_list_size =
+-						hdcp->auth.msg.hdcp2.rxstatus & 0x3FF;
++					HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 |
++					hdcp->auth.msg.hdcp2.rxstatus[0];
+ 		}
+ out:
+ 	return (*status == MOD_HDCP_STATUS_SUCCESS);
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
+index 8059aff9911f..ff9d54812e62 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c
+@@ -390,7 +390,7 @@ enum mod_hdcp_status mod_hdcp_read_rxstatus(struct mod_hdcp *hdcp)
+ 
+ 	if (is_dp_hdcp(hdcp)) {
+ 		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_RXSTATUS,
+-				(uint8_t *)&hdcp->auth.msg.hdcp2.rxstatus,
++				&hdcp->auth.msg.hdcp2.rxstatus_dp,
+ 				1);
+ 	} else {
+ 		status = read(hdcp, MOD_HDCP_MESSAGE_ID_READ_RXSTATUS,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4513-drm-amd-display-Fix-static-analysis-bug-in-validate_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4513-drm-amd-display-Fix-static-analysis-bug-in-validate_.patch
new file mode 100644
index 00000000..73c36f1f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4513-drm-amd-display-Fix-static-analysis-bug-in-validate_.patch
@@ -0,0 +1,45 @@
+From e90602e57aacf7202229cb99d213ff0ce8954699 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 6 Nov 2019 14:58:45 -0500
+Subject: [PATCH 4513/4736] drm/amd/display: Fix static analysis bug in
+ validate_bksv
+
+[Why]
+static analysis throws the error below
+
+Out-of-bounds read (OVERRUN)
+Overrunning array of 5 bytes at byte offset 7 by dereferencing pointer
+(uint64_t *)hdcp->auth.msg.hdcp1.bksv.
+
+var n is going to contain  r0p and bcaps. if they are non-zero the count
+will be wrong
+
+How]
+Use memcpy instead to avoid this.
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+index 4d11041a8c6f..04845e43df15 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c
+@@ -27,9 +27,11 @@
+ 
+ static inline enum mod_hdcp_status validate_bksv(struct mod_hdcp *hdcp)
+ {
+-	uint64_t n = *(uint64_t *)hdcp->auth.msg.hdcp1.bksv;
++	uint64_t n = 0;
+ 	uint8_t count = 0;
+ 
++	memcpy(&n, hdcp->auth.msg.hdcp1.bksv, sizeof(uint64_t));
++
+ 	while (n) {
+ 		count++;
+ 		n &= (n - 1);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4514-drm-amdkfd-remove-set-but-not-used-variable-top_dev.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4514-drm-amdkfd-remove-set-but-not-used-variable-top_dev.patch
new file mode 100644
index 00000000..ad51cab5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4514-drm-amdkfd-remove-set-but-not-used-variable-top_dev.patch
@@ -0,0 +1,37 @@
+From d5fd1655587eb432b0d47243c678488f7253e6c4 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Thu, 14 Nov 2019 11:20:25 +0800
+Subject: [PATCH 4514/4736] drm/amdkfd: remove set but not used variable
+ 'top_dev'
+
+Fixes gcc '-Wunused-but-set-variable' warning:
+
+drivers/gpu/drm/amd/amdkfd/kfd_iommu.c: In function kfd_iommu_device_init:
+drivers/gpu/drm/amd/amdkfd/kfd_iommu.c:65:30: warning: variable top_dev set but not used [-Wunused-but-set-variable]
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Fixes: 1ae99eab34f9 ("drm/amdkfd: Initialize HSA_CAP_ATS_PRESENT capability in topology codes")
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_iommu.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c b/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
+index 193e2835bd4d..8d871514671e 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
+@@ -62,9 +62,6 @@ int kfd_iommu_device_init(struct kfd_dev *kfd)
+ 	struct amd_iommu_device_info iommu_info;
+ 	unsigned int pasid_limit;
+ 	int err;
+-	struct kfd_topology_device *top_dev;
+-
+-	top_dev = kfd_topology_device_by_id(kfd->id);
+ 
+ 	if (!kfd->device_info->needs_iommu_device)
+ 		return 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4515-drm-amdgpu-vcn2.5-fix-the-enc-loop-with-hw-fini.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4515-drm-amdgpu-vcn2.5-fix-the-enc-loop-with-hw-fini.patch
new file mode 100644
index 00000000..01d0f98c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4515-drm-amdgpu-vcn2.5-fix-the-enc-loop-with-hw-fini.patch
@@ -0,0 +1,38 @@
+From 58b0eb3e79e22759ddfb375c4e1247a2b371b631 Mon Sep 17 00:00:00 2001
+From: Leo Liu <leo.liu@amd.com>
+Date: Fri, 15 Nov 2019 17:10:34 -0500
+Subject: [PATCH 4515/4736] drm/amdgpu/vcn2.5: fix the enc loop with hw fini
+
+Signed-off-by: Leo Liu <leo.liu@amd.com>
+Reviewed-by: James Zhu <James.Zhu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+index 98f423f30d2f..11dd533fb1ab 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+@@ -268,7 +268,7 @@ static int vcn_v2_5_hw_fini(void *handle)
+ {
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 	struct amdgpu_ring *ring;
+-	int i;
++	int i, j;
+ 
+ 	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ 		if (adev->vcn.harvest_config & (1 << i))
+@@ -280,8 +280,8 @@ static int vcn_v2_5_hw_fini(void *handle)
+ 
+ 		ring->sched.ready = false;
+ 
+-		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+-			ring = &adev->vcn.inst[i].ring_enc[i];
++		for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
++			ring = &adev->vcn.inst[i].ring_enc[j];
+ 			ring->sched.ready = false;
+ 		}
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4516-drm-amdgpu-put-flush_dealyed_work-at-first.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4516-drm-amdgpu-put-flush_dealyed_work-at-first.patch
new file mode 100644
index 00000000..4d603188
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4516-drm-amdgpu-put-flush_dealyed_work-at-first.patch
@@ -0,0 +1,63 @@
+From 9852e1ef2fd04bb8469914ea973a173584b84deb Mon Sep 17 00:00:00 2001
+From: Yintian Tao <yttao@amd.com>
+Date: Mon, 18 Nov 2019 16:06:00 +0800
+Subject: [PATCH 4516/4736] drm/amdgpu: put flush_dealyed_work at first
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There is one regression from 042f3d7b745cd76aa
+To put flush_delayed_work after adev->shutdown = true
+which will make amdgpu_ih_process not response the irq
+At last, all ib ring tests will be failed just like below
+
+[drm] amdgpu: finishing device.
+[drm] Fence fallback timer expired on ring gfx
+[drm] Fence fallback timer expired on ring comp_1.0.0
+[drm] Fence fallback timer expired on ring comp_1.1.0
+[drm] Fence fallback timer expired on ring comp_1.2.0
+[drm] Fence fallback timer expired on ring comp_1.3.0
+[drm] Fence fallback timer expired on ring comp_1.0.1
+amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on comp_1.1.1 (-110).
+amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on comp_1.2.1 (-110).
+amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on comp_1.3.1 (-110).
+amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on sdma0 (-110).
+amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on sdma1 (-110).
+amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on uvd_enc_0.0 (-110).
+amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on vce0 (-110).
+[drm:amdgpu_device_delayed_init_work_handler [amdgpu]] *ERROR* ib ring test failed (-110).
+
+v2: replace cancel_delayed_work_sync() with flush_delayed_work()
+
+Signed-off-by: Yintian Tao <yttao@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 7ccc9518c173..61fb27b4e89c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3119,9 +3119,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
+ 	int r;
+ 
+ 	DRM_INFO("amdgpu: finishing device.\n");
+-	adev->shutdown = true;
+-
+ 	flush_delayed_work(&adev->delayed_init_work);
++	adev->shutdown = true;
+ 
+ 	/* disable all interrupts */
+ 	amdgpu_irq_disable_all(adev);
+@@ -3141,7 +3140,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
+ 		adev->firmware.gpu_info_fw = NULL;
+ 	}
+ 	adev->accel_working = false;
+-	cancel_delayed_work_sync(&adev->delayed_init_work);
+ 	/* free i2c buses */
+ 	if (!amdgpu_device_has_dc_support(adev))
+ 		amdgpu_i2c_fini(adev);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4517-drm-amdgpu-soc15-move-struct-definition-around-to-al.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4517-drm-amdgpu-soc15-move-struct-definition-around-to-al.patch
new file mode 100644
index 00000000..8c679e32
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4517-drm-amdgpu-soc15-move-struct-definition-around-to-al.patch
@@ -0,0 +1,38 @@
+From e82498dd48da16c5608bc8e76752ec9809c3ccfb Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 15 Oct 2019 16:21:27 -0400
+Subject: [PATCH 4517/4736] drm/amdgpu/soc15: move struct definition around to
+ align with other soc15 asics
+
+Move reset_method next to reset callback to match the struct layout and
+the other definition in this file.
+
+Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index fea3222c40bc..67e84e8493b8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -1017,6 +1017,7 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
+ 	.read_bios_from_rom = &soc15_read_bios_from_rom,
+ 	.read_register = &soc15_read_register,
+ 	.reset = &soc15_asic_reset,
++	.reset_method = &soc15_asic_reset_method,
+ 	.set_vga_state = &soc15_vga_set_state,
+ 	.get_xclk = &soc15_get_xclk,
+ 	.set_uvd_clocks = &soc15_set_uvd_clocks,
+@@ -1029,7 +1030,6 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
+ 	.get_pcie_usage = &vega20_get_pcie_usage,
+ 	.need_reset_on_init = &soc15_need_reset_on_init,
+ 	.get_pcie_replay_count = &soc15_get_pcie_replay_count,
+-	.reset_method = &soc15_asic_reset_method
+ };
+ 
+ static int soc15_common_early_init(void *handle)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4518-drm-amdgpu-nv-add-asic-func-for-fetching-vbios-from-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4518-drm-amdgpu-nv-add-asic-func-for-fetching-vbios-from-.patch
new file mode 100644
index 00000000..aaa0508d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4518-drm-amdgpu-nv-add-asic-func-for-fetching-vbios-from-.patch
@@ -0,0 +1,59 @@
+From 4baaff63c41abaecb938ac4c3b72ce6e6ce41bd9 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 13 Nov 2019 14:27:54 -0500
+Subject: [PATCH 4518/4736] drm/amdgpu/nv: add asic func for fetching vbios
+ from rom directly
+
+Needed as a fallback if the vbios can't be fetched by other means.
+
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 24 ++++++++++++++++++++++--
+ 1 file changed, 22 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 9163f3507a84..91b0482278c2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -39,6 +39,7 @@
+ #include "gc/gc_10_1_0_sh_mask.h"
+ #include "hdp/hdp_5_0_0_offset.h"
+ #include "hdp/hdp_5_0_0_sh_mask.h"
++#include "smuio/smuio_11_0_0_offset.h"
+ 
+ #include "soc15.h"
+ #include "soc15_common.h"
+@@ -156,8 +157,27 @@ static bool nv_read_disabled_bios(struct amdgpu_device *adev)
+ static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
+ 				  u8 *bios, u32 length_bytes)
+ {
+-	/* TODO: will implement it when SMU header is available */
+-	return false;
++	u32 *dw_ptr;
++	u32 i, length_dw;
++
++	if (bios == NULL)
++		return false;
++	if (length_bytes == 0)
++		return false;
++	/* APU vbios image is part of sbios image */
++	if (adev->flags & AMD_IS_APU)
++		return false;
++
++	dw_ptr = (u32 *)bios;
++	length_dw = ALIGN(length_bytes, 4) / 4;
++
++	/* set rom index to 0 */
++	WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
++	/* read out the rom data */
++	for (i = 0; i < length_dw; i++)
++		dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
++
++	return true;
+ }
+ 
+ static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4519-drm-amdgpu-fix-bad-DMA-from-INTERRUPT_CNTL2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4519-drm-amdgpu-fix-bad-DMA-from-INTERRUPT_CNTL2.patch
new file mode 100644
index 00000000..1dec60b5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4519-drm-amdgpu-fix-bad-DMA-from-INTERRUPT_CNTL2.patch
@@ -0,0 +1,37 @@
+From f7dfb5fae746cff572f21503242b9004792d9790 Mon Sep 17 00:00:00 2001
+From: Sam Bobroff <sbobroff@linux.ibm.com>
+Date: Mon, 18 Nov 2019 10:53:54 +1100
+Subject: [PATCH 4519/4736] drm/amdgpu: fix bad DMA from INTERRUPT_CNTL2
+
+The INTERRUPT_CNTL2 register expects a valid DMA address, but is
+currently set with a GPU MC address.  This can cause problems on
+systems that detect the resulting DMA read from an invalid address
+(found on a Power8 guest).
+
+Instead, use the DMA address of the dummy page because it will always
+be safe.
+
+Fixes: 27ae10641e9c ("drm/amdgpu: add interupt handler implementation for si v3")
+Signed-off-by: Sam Bobroff <sbobroff@linux.ibm.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/si_ih.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
+index 8c50c9cab455..28e04fe0ed33 100644
+--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
++++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
+@@ -62,7 +62,8 @@ static int si_ih_irq_init(struct amdgpu_device *adev)
+ 	u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
+ 
+ 	si_ih_disable_interrupts(adev);
+-	WREG32(INTERRUPT_CNTL2, adev->irq.ih.gpu_addr >> 8);
++	/* set dummy read address to dummy page address */
++	WREG32(INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
+ 	interrupt_cntl = RREG32(INTERRUPT_CNTL);
+ 	interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
+ 	interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4520-Revert-drm-amdgpu-don-t-read-registers-if-gfxoff-is-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4520-Revert-drm-amdgpu-don-t-read-registers-if-gfxoff-is-.patch
new file mode 100644
index 00000000..5aac7746
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4520-Revert-drm-amdgpu-don-t-read-registers-if-gfxoff-is-.patch
@@ -0,0 +1,124 @@
+From 9a383d04b57ff6e3339a1d679458a3dbc02e23a9 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 18 Nov 2019 12:21:26 -0500
+Subject: [PATCH 4520/4736] Revert "drm/amdgpu: don't read registers if gfxoff
+ is enabled (v2)"
+
+This reverts commit 5e49d6f654c569c2de920babbaf5cf7c4c4a353f.
+
+Drop this workaround in favor of a better one.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c    | 27 ++++++++++----------------
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 31 ++++++++++++------------------
+ 2 files changed, 22 insertions(+), 36 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 91b0482278c2..4a52e5d59807 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -221,25 +221,17 @@ static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
+ 	return val;
+ }
+ 
+-static int nv_get_register_value(struct amdgpu_device *adev,
++static uint32_t nv_get_register_value(struct amdgpu_device *adev,
+ 				      bool indexed, u32 se_num,
+-				      u32 sh_num, u32 reg_offset,
+-				      u32 *value)
++				      u32 sh_num, u32 reg_offset)
+ {
+ 	if (indexed) {
+-		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+-			return -EINVAL;
+-		*value = nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
++		return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
+ 	} else {
+-		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) {
+-			*value = adev->gfx.config.gb_addr_config;
+-		} else {
+-			if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+-				return -EINVAL;
+-			*value = RREG32(reg_offset);
+-		}
++		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
++			return adev->gfx.config.gb_addr_config;
++		return RREG32(reg_offset);
+ 	}
+-	return 0;
+ }
+ 
+ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
+@@ -255,9 +247,10 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
+ 		    (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
+ 			continue;
+ 
+-		return nv_get_register_value(adev,
+-					     nv_allowed_read_registers[i].grbm_indexed,
+-					     se_num, sh_num, reg_offset, value);
++		*value = nv_get_register_value(adev,
++					       nv_allowed_read_registers[i].grbm_indexed,
++					       se_num, sh_num, reg_offset);
++		return 0;
+ 	}
+ 	return -EINVAL;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 67e84e8493b8..a458dded99c6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -364,27 +364,19 @@ static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_n
+ 	return val;
+ }
+ 
+-static int soc15_get_register_value(struct amdgpu_device *adev,
++static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
+ 					 bool indexed, u32 se_num,
+-					 u32 sh_num, u32 reg_offset,
+-					 u32 *value)
++					 u32 sh_num, u32 reg_offset)
+ {
+ 	if (indexed) {
+-		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+-			return -EINVAL;
+-	        *value = soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
++		return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
+ 	} else {
+-		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) {
+-			*value = adev->gfx.config.gb_addr_config;
+-		} else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) {
+-			*value = adev->gfx.config.db_debug2;
+-		} else {
+-			if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+-				return -EINVAL;
+-			*value = RREG32(reg_offset);
+-		}
++		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
++			return adev->gfx.config.gb_addr_config;
++		else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
++			return adev->gfx.config.db_debug2;
++		return RREG32(reg_offset);
+ 	}
+-	return 0;
+ }
+ 
+ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
+@@ -400,9 +392,10 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
+ 					+ en->reg_offset))
+ 			continue;
+ 
+-		return soc15_get_register_value(adev,
+-						soc15_allowed_read_registers[i].grbm_indexed,
+-						se_num, sh_num, reg_offset, value);
++		*value = soc15_get_register_value(adev,
++						  soc15_allowed_read_registers[i].grbm_indexed,
++						  se_num, sh_num, reg_offset);
++		return 0;
+ 	}
+ 	return -EINVAL;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4521-drm-amdgpu-remove-not-needed-memset.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4521-drm-amdgpu-remove-not-needed-memset.patch
new file mode 100644
index 00000000..a445cbff
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4521-drm-amdgpu-remove-not-needed-memset.patch
@@ -0,0 +1,31 @@
+From d4f6653700813610901bac4467378a33e43ef68f Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Mon, 18 Nov 2019 17:00:31 +0800
+Subject: [PATCH 4521/4736] drm/amdgpu: remove not needed memset
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c:64:13-31: WARNING: dma_alloc_coherent use in ih -> ring already zeroes out memory,  so memset is not needed
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+index 934dfdcb4e73..d922187d91f5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+@@ -65,7 +65,6 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
+ 		if (ih->ring == NULL)
+ 			return -ENOMEM;
+ 
+-		memset((void *)ih->ring, 0, ih->ring_size + 8);
+ 		ih->gpu_addr = dma_addr;
+ 		ih->wptr_addr = dma_addr + ih->ring_size;
+ 		ih->wptr_cpu = &ih->ring[ih->ring_size / 4];
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4522-drm-amdgpu-expand-sdma-copy_buffer-interface-with-tm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4522-drm-amdgpu-expand-sdma-copy_buffer-interface-with-tm.patch
new file mode 100644
index 00000000..6b7d0bef
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4522-drm-amdgpu-expand-sdma-copy_buffer-interface-with-tm.patch
@@ -0,0 +1,157 @@
+From 142541f86444a33597f842aced7388bbd9698604 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Tue, 15 Oct 2019 15:37:48 +0800
+Subject: [PATCH 4522/4736] drm/amdgpu: expand sdma copy_buffer interface with
+ tmz parameter
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This patch expands sdma copy_buffer interface with tmz parameter.
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 5 +++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/cik_sdma.c    | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c   | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c   | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c   | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/si_dma.c      | 3 ++-
+ 8 files changed, 17 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+index 761ff8be6314..b3134655789f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+@@ -79,7 +79,8 @@ struct amdgpu_buffer_funcs {
+ 				 /* dst addr in bytes */
+ 				 uint64_t dst_offset,
+ 				 /* number of byte to transfer */
+-				 uint32_t byte_count);
++				 uint32_t byte_count,
++				 bool tmz);
+ 
+ 	/* maximum bytes in a single operation */
+ 	uint32_t	fill_max_bytes;
+@@ -97,7 +98,7 @@ struct amdgpu_buffer_funcs {
+ 				 uint32_t byte_count);
+ };
+ 
+-#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib),  (s), (d), (b))
++#define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib),  (s), (d), (b), (t))
+ #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
+ 
+ struct amdgpu_sdma_instance *
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index b5028af50cc2..ee5c8fec9375 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -2343,7 +2343,7 @@ static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
+ 	dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+ 	dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
+ 	amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
+-				dst_addr, num_bytes);
++				dst_addr, num_bytes, false);
+ 
+ 	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
+ 	WARN_ON(job->ibs[0].length_dw > num_dw);
+@@ -2414,7 +2414,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
+ 		uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
+ 
+ 		amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
+-					dst_offset, cur_size_in_bytes);
++					dst_offset, cur_size_in_bytes, false);
+ 
+ 		src_offset += cur_size_in_bytes;
+ 		dst_offset += cur_size_in_bytes;
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+index d42808b05971..6e52d6f86435 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+@@ -1311,7 +1311,8 @@ static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
+ static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
+ 				      uint64_t src_offset,
+ 				      uint64_t dst_offset,
+-				      uint32_t byte_count)
++				      uint32_t byte_count,
++				      bool tmz)
+ {
+ 	ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
+ 	ib->ptr[ib->length_dw++] = byte_count;
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+index 36196372e8db..c448e782fc4c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+@@ -1197,7 +1197,8 @@ static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
+ static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
+ 				       uint64_t src_offset,
+ 				       uint64_t dst_offset,
+-				       uint32_t byte_count)
++				       uint32_t byte_count,
++				       bool tmz)
+ {
+ 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
+ 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+index 6d39544e7829..017ac444f8e7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+@@ -1635,7 +1635,8 @@ static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
+ static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
+ 				       uint64_t src_offset,
+ 				       uint64_t dst_offset,
+-				       uint32_t byte_count)
++				       uint32_t byte_count,
++				       bool tmz)
+ {
+ 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
+ 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 2653d3c6ddd3..fa9dd28ebd5a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -2337,7 +2337,8 @@ static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
+ static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
+ 				       uint64_t src_offset,
+ 				       uint64_t dst_offset,
+-				       uint32_t byte_count)
++				       uint32_t byte_count,
++				       bool tmz)
+ {
+ 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
+ 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+index ec47542e21b0..66e89bebe0ed 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+@@ -1657,7 +1657,8 @@ static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
+ static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
+ 				       uint64_t src_offset,
+ 				       uint64_t dst_offset,
+-				       uint32_t byte_count)
++				       uint32_t byte_count,
++				       bool tmz)
+ {
+ 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
+ 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
+diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
+index 3eeefd40dae0..2161769c6fec 100644
+--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
++++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
+@@ -775,7 +775,8 @@ static void si_dma_set_irq_funcs(struct amdgpu_device *adev)
+ static void si_dma_emit_copy_buffer(struct amdgpu_ib *ib,
+ 				       uint64_t src_offset,
+ 				       uint64_t dst_offset,
+-				       uint32_t byte_count)
++				       uint32_t byte_count,
++				       bool tmz)
+ {
+ 	ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY,
+ 					      1, 0, 0, byte_count);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4523-drm-amdgpu-expand-amdgpu_copy_buffer-interface-with-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4523-drm-amdgpu-expand-amdgpu_copy_buffer-interface-with-.patch
new file mode 100644
index 00000000..2a286a76
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4523-drm-amdgpu-expand-amdgpu_copy_buffer-interface-with-.patch
@@ -0,0 +1,117 @@
+From a9b88b455e2bcdfd22776bb1de9ed8345bc615d9 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Tue, 15 Oct 2019 15:45:23 +0800
+Subject: [PATCH 4523/4736] drm/amdgpu: expand amdgpu_copy_buffer interface
+ with tmz parameter
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This patch expands amdgpu_copy_buffer interface with tmz parameter.
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c    | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_test.c      | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c       | 6 +++---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h       | 2 +-
+ 5 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+index 0f2aeb41e5c8..3ac31e1febb7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+@@ -40,7 +40,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size,
+ 	for (i = 0; i < n; i++) {
+ 		struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+ 		r = amdgpu_copy_buffer(ring, saddr, daddr, size, NULL, &fence,
+-				       false, false);
++				       false, false, false);
+ 		if (r)
+ 			goto exit_do_move;
+ 		r = dma_fence_wait(fence, false);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+index 1350666355e0..aaccf287141c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+@@ -785,7 +785,7 @@ int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence)
+ 
+ 	return amdgpu_copy_buffer(ring, shadow_addr, parent_addr,
+ 				  amdgpu_bo_size(shadow), NULL, fence,
+-				  true, false);
++				  true, false, false);
+ }
+ 
+ /**
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
+index 41d3142ef3cf..a8828570a526 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
+@@ -124,7 +124,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
+ 		amdgpu_bo_kunmap(gtt_obj[i]);
+ 
+ 		r = amdgpu_copy_buffer(ring, gart_addr, vram_addr,
+-				       size, NULL, &fence, false, false);
++				       size, NULL, &fence, false, false, false);
+ 
+ 		if (r) {
+ 			DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
+@@ -170,7 +170,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
+ 		amdgpu_bo_kunmap(vram_obj);
+ 
+ 		r = amdgpu_copy_buffer(ring, vram_addr, gart_addr,
+-				       size, NULL, &fence, false, false);
++				       size, NULL, &fence, false, false, false);
+ 
+ 		if (r) {
+ 			DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index ee5c8fec9375..d93bfaca5daf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -487,7 +487,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
+ 		}
+ 
+ 		r = amdgpu_copy_buffer(ring, from, to, cur_size,
+-				       resv, &next, false, true);
++				       resv, &next, false, true, false);
+ 		if (r)
+ 			goto error;
+ 
+@@ -2373,7 +2373,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
+ 		       uint64_t dst_offset, uint32_t byte_count,
+ 		       struct reservation_object *resv,
+ 		       struct dma_fence **fence, bool direct_submit,
+-		       bool vm_needs_flush)
++		       bool vm_needs_flush, bool tmz)
+ {
+ 	struct amdgpu_device *adev = ring->adev;
+ 	struct amdgpu_job *job;
+@@ -2414,7 +2414,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
+ 		uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
+ 
+ 		amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
+-					dst_offset, cur_size_in_bytes, false);
++					dst_offset, cur_size_in_bytes, tmz);
+ 
+ 		src_offset += cur_size_in_bytes;
+ 		dst_offset += cur_size_in_bytes;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+index b92297987138..f8cd8adb3337 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+@@ -93,7 +93,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
+ 		       uint64_t dst_offset, uint32_t byte_count,
+ 		       struct reservation_object *resv,
+ 		       struct dma_fence **fence, bool direct_submit,
+-		       bool vm_needs_flush);
++		       bool vm_needs_flush, bool tmz);
+ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
+ 			       struct amdgpu_copy_mem *src,
+ 			       struct amdgpu_copy_mem *dst,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4524-drm-amdgpu-enable-TMZ-bit-in-sdma-copy-pkt-for-sdma-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4524-drm-amdgpu-enable-TMZ-bit-in-sdma-copy-pkt-for-sdma-.patch
new file mode 100644
index 00000000..12c24dbf
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4524-drm-amdgpu-enable-TMZ-bit-in-sdma-copy-pkt-for-sdma-.patch
@@ -0,0 +1,36 @@
+From 35308892286076ad11b3c0297ae0178605f52005 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Tue, 15 Oct 2019 16:47:44 +0800
+Subject: [PATCH 4524/4736] drm/amdgpu: enable TMZ bit in sdma copy pkt for
+ sdma v4
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Enable sdma TMZ mode via setting TMZ bit in sdma copy pkt
+for sdma v4
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index fa9dd28ebd5a..5a5d825f5cab 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -2341,7 +2341,8 @@ static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
+ 				       bool tmz)
+ {
+ 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
+-		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
++		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
++		SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
+ 	ib->ptr[ib->length_dw++] = byte_count - 1;
+ 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
+ 	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4525-drm-amdgpu-enable-TMZ-bit-in-sdma-copy-pkt-for-sdma-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4525-drm-amdgpu-enable-TMZ-bit-in-sdma-copy-pkt-for-sdma-.patch
new file mode 100644
index 00000000..d3642b4d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4525-drm-amdgpu-enable-TMZ-bit-in-sdma-copy-pkt-for-sdma-.patch
@@ -0,0 +1,32 @@
+From 5ab485e2af46cd114f85eaef65fd6190ef64cf9b Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Fri, 15 Nov 2019 16:18:03 +0800
+Subject: [PATCH 4525/4736] drm/amdgpu: enable TMZ bit in sdma copy pkt for
+ sdma v5
+
+Enable sdma TMZ mode via setting TMZ bit in sdma copy pkt
+for sdma v5.
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+index 66e89bebe0ed..948e9a46da2d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+@@ -1661,7 +1661,8 @@ static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
+ 				       bool tmz)
+ {
+ 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
+-		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
++		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
++		SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
+ 	ib->ptr[ib->length_dw++] = byte_count - 1;
+ 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
+ 	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4526-drm-amdgpu-enable-TMZ-bit-in-FRAME_CONTROL-for-gfx10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4526-drm-amdgpu-enable-TMZ-bit-in-FRAME_CONTROL-for-gfx10.patch
new file mode 100644
index 00000000..6462a20c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4526-drm-amdgpu-enable-TMZ-bit-in-FRAME_CONTROL-for-gfx10.patch
@@ -0,0 +1,30 @@
+From 2c35b29c8a3d9ab6308d866262c5dc8c9fa5df04 Mon Sep 17 00:00:00 2001
+From: Aaron Liu <aaron.liu@amd.com>
+Date: Fri, 15 Nov 2019 15:08:36 +0800
+Subject: [PATCH 4526/4736] drm/amdgpu: enable TMZ bit in FRAME_CONTROL for
+ gfx10
+
+This patch enables TMZ bit in FRAME_CONTROL for gfx10.
+
+Signed-off-by: Aaron Liu <aaron.liu@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 9274bd4b6c68..678ad1b26535 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -4596,7 +4596,7 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
+ 		gfx_v10_0_ring_emit_ce_meta(ring,
+ 				    flags & AMDGPU_IB_PREEMPTED ? true : false);
+ 
+-	gfx_v10_0_ring_emit_tmz(ring, true, false);
++	gfx_v10_0_ring_emit_tmz(ring, true, trusted);
+ 
+ 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
+ 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4527-drm-amdgpu-powerplay-fix-dereference-before-null-che.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4527-drm-amdgpu-powerplay-fix-dereference-before-null-che.patch
new file mode 100644
index 00000000..920f9549
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4527-drm-amdgpu-powerplay-fix-dereference-before-null-che.patch
@@ -0,0 +1,43 @@
+From f70d7dab0998e1e9af945550a69c3535835c82eb Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Fri, 15 Nov 2019 09:47:54 +0000
+Subject: [PATCH 4527/4736] drm/amdgpu/powerplay: fix dereference before null
+ check of pointer hwmgr
+
+The assignment of adev dereferences pointer hwmgr before hwmgr is null
+checked, hence there is a potential null pointer deference issue. Fix
+this by assigning adev after the null check.
+
+Addresses-Coverity: ("Dereference before null check")
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+index 72f2b09195dc..cf5043bbf748 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+@@ -81,7 +81,7 @@ static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
+ 
+ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
+ {
+-	struct amdgpu_device *adev = hwmgr->adev;
++	struct amdgpu_device *adev;
+ 
+ 	if (!hwmgr)
+ 		return -EINVAL;
+@@ -96,6 +96,8 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
+ 	hwmgr_init_workload_prority(hwmgr);
+ 	hwmgr->gfxoff_state_changed_by_workload = false;
+ 
++	adev = hwmgr->adev;
++
+ 	switch (hwmgr->chip_family) {
+ 	case AMDGPU_FAMILY_CI:
+ 		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4528-drm-amd-powerplay-return-errno-code-to-caller-when-e.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4528-drm-amd-powerplay-return-errno-code-to-caller-when-e.patch
new file mode 100644
index 00000000..ce283ef4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4528-drm-amd-powerplay-return-errno-code-to-caller-when-e.patch
@@ -0,0 +1,43 @@
+From 3e7c55707c521fca516b611a8b862312e477cc69 Mon Sep 17 00:00:00 2001
+From: Chen Wandun <chenwandun@huawei.com>
+Date: Mon, 18 Nov 2019 16:03:34 +0800
+Subject: [PATCH 4528/4736] drm/amd/powerplay: return errno code to caller when
+ error occur
+
+return errno code to caller when error occur, and meanwhile
+remove gcc '-Wunused-but-set-variable' warning.
+
+drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/vegam_smumgr.c: In function vegam_populate_smc_boot_level:
+drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/vegam_smumgr.c:1364:6: warning: variable result set but not used [-Wunused-but-set-variable]
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Chen Wandun <chenwandun@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+index 2068eb00d2f8..50896e9b2579 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+@@ -1371,11 +1371,16 @@ static int vegam_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
+ 	result = phm_find_boot_level(&(data->dpm_table.sclk_table),
+ 			data->vbios_boot_state.sclk_bootup_value,
+ 			(uint32_t *)&(table->GraphicsBootLevel));
++	if (result)
++		return result;
+ 
+ 	result = phm_find_boot_level(&(data->dpm_table.mclk_table),
+ 			data->vbios_boot_state.mclk_bootup_value,
+ 			(uint32_t *)&(table->MemoryBootLevel));
+ 
++	if (result)
++		return result;
++
+ 	table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
+ 			VOLTAGE_SCALE;
+ 	table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4529-drm-amd-powerplay-correct-swSMU-baco-reset-related-s.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4529-drm-amd-powerplay-correct-swSMU-baco-reset-related-s.patch
new file mode 100644
index 00000000..1b08056d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4529-drm-amd-powerplay-correct-swSMU-baco-reset-related-s.patch
@@ -0,0 +1,68 @@
+From 1e4f35f41e12e21e3787690d9ab6a52746c868f0 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 18 Nov 2019 17:04:24 +0800
+Subject: [PATCH 4529/4736] drm/amd/powerplay: correct swSMU baco reset related
+ settings
+
+Added bif doorbell interrupt setting and applied different
+settings for BACO reset for RAS recovery.
+
+Change-Id: I823b2d478699d469ecc7746e2a8fb1110a4a146f
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 30 ++++++++++++++++++++---
+ 1 file changed, 27 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 928877f73dfd..71e2bbe25cf6 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1667,6 +1667,10 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
+ {
+ 
+ 	struct smu_baco_context *smu_baco = &smu->smu_baco;
++	struct amdgpu_device *adev = smu->adev;
++	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
++	uint32_t bif_doorbell_intr_cntl;
++	uint32_t data;
+ 	int ret = 0;
+ 
+ 	if (smu_v11_0_baco_get_state(smu) == state)
+@@ -1674,10 +1678,30 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
+ 
+ 	mutex_lock(&smu_baco->mutex);
+ 
+-	if (state == SMU_BACO_STATE_ENTER)
+-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, BACO_SEQ_BACO);
+-	else
++	bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
++
++	if (state == SMU_BACO_STATE_ENTER) {
++		bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
++						BIF_DOORBELL_INT_CNTL,
++						DOORBELL_INTERRUPT_DISABLE, 1);
++		WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
++
++		if (!ras || !ras->supported) {
++			data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
++			data |= 0x80000000;
++			WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
++
++			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0);
++		} else {
++			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1);
++		}
++	} else {
+ 		ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
++		bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
++						BIF_DOORBELL_INT_CNTL,
++						DOORBELL_INTERRUPT_DISABLE, 0);
++		WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
++	}
+ 	if (ret)
+ 		goto out;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4530-drm-amd-powerplay-add-Arcturus-baco-reset-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4530-drm-amd-powerplay-add-Arcturus-baco-reset-support.patch
new file mode 100644
index 00000000..3cc03ff1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4530-drm-amd-powerplay-add-Arcturus-baco-reset-support.patch
@@ -0,0 +1,90 @@
+From 3c0de548a406f11a7e39af0639c51771ee5cc29a Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Mon, 4 Nov 2019 17:31:29 +0800
+Subject: [PATCH 4530/4736] drm/amd/powerplay: add Arcturus baco reset support
+
+Enable baco reset support on Arcturus.
+
+Change-Id: I7b69016ee0d238e0fcb323aa10215e29924a6ca6
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c           |  1 +
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c |  7 +++++++
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c    | 14 ++++++++++----
+ 3 files changed, 18 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index a458dded99c6..41724a368d76 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -558,6 +558,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
+ 		return AMD_RESET_METHOD_MODE2;
+ 	case CHIP_VEGA10:
+ 	case CHIP_VEGA12:
++	case CHIP_ARCTURUS:
+ 		soc15_asic_get_baco_capability(adev, &baco_reset);
+ 		break;
+ 	case CHIP_VEGA20:
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 6d1401b30aaf..06c331d1e3e7 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -495,6 +495,7 @@ static int arcturus_store_powerplay_table(struct smu_context *smu)
+ {
+ 	struct smu_11_0_powerplay_table *powerplay_table = NULL;
+ 	struct smu_table_context *table_context = &smu->smu_table;
++	struct smu_baco_context *smu_baco = &smu->smu_baco;
+ 	int ret = 0;
+ 
+ 	if (!table_context->power_play_table)
+@@ -507,6 +508,12 @@ static int arcturus_store_powerplay_table(struct smu_context *smu)
+ 
+ 	table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
+ 
++	mutex_lock(&smu_baco->mutex);
++	if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
++	    powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
++		smu_baco->platform_support = true;
++	mutex_unlock(&smu_baco->mutex);
++
+ 	return ret;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 71e2bbe25cf6..238d584805b3 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1641,7 +1641,9 @@ bool smu_v11_0_baco_is_support(struct smu_context *smu)
+ 	if (!baco_support)
+ 		return false;
+ 
+-	if (!smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
++	/* Arcturus does not support this bit mask */
++	if (smu_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
++	   !smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
+ 		return false;
+ 
+ 	val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
+@@ -1713,11 +1715,15 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
+ 
+ int smu_v11_0_baco_reset(struct smu_context *smu)
+ {
++	struct amdgpu_device *adev = smu->adev;
+ 	int ret = 0;
+ 
+-	ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
+-	if (ret)
+-		return ret;
++	/* Arcturus does not need this audio workaround */
++	if (adev->asic_type != CHIP_ARCTURUS) {
++		ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
++		if (ret)
++			return ret;
++	}
+ 
+ 	ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
+ 	if (ret)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4531-drm-amd-powerplay-add-missing-header-file-declaratio.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4531-drm-amd-powerplay-add-missing-header-file-declaratio.patch
new file mode 100644
index 00000000..fa1970bc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4531-drm-amd-powerplay-add-missing-header-file-declaratio.patch
@@ -0,0 +1,40 @@
+From ca8db79cdb7fb6b91f9435e63b9fd1e064c845c6 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 19 Nov 2019 11:43:45 +0800
+Subject: [PATCH 4531/4736] drm/amd/powerplay: add missing header file
+ declaration
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This can fix the compile errors below:
+drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c: In function ‘smu_v11_0_baco_set_state’:
+drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1674:27: error: implicit declaration of function ‘amdgpu_ras_get_context’ [-Werror=implicit-function-declaration]
+  struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+                           ^
+drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1674:27: warning: initialization makes pointer from integer without a cast [-Wint-conversion]
+drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1692:19: error: dereferencing pointer to incomplete type ‘struct amdgpu_ras’
+   if (!ras || !ras->supported) {
+
+Change-Id: I1242e64e82715774b8e2931530749782b9107e32
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 238d584805b3..52aadbaaabda 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -34,6 +34,7 @@
+ #include "soc15_common.h"
+ #include "atom.h"
+ #include "amd_pcie.h"
++#include "amdgpu_ras.h"
+ 
+ #include "asic_reg/thm/thm_11_0_2_offset.h"
+ #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4532-drm-amdgpu-add-psp-funcs-for-ring-write-pointer-read.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4532-drm-amdgpu-add-psp-funcs-for-ring-write-pointer-read.patch
new file mode 100644
index 00000000..597ca5c1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4532-drm-amdgpu-add-psp-funcs-for-ring-write-pointer-read.patch
@@ -0,0 +1,217 @@
+From 5a274a9eba4f444bec6d0550400b726deb5ce4e4 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 18 Nov 2019 17:13:56 +0800
+Subject: [PATCH 4532/4736] drm/amdgpu: add psp funcs for ring write pointer
+ read/write
+
+The ring write pointer regsiter update is the only part that
+is IP specific ones in psp_cmd_submit function.
+
+Add two callbacks for wptr read/write so that we unify the
+psp_cmd_submit function for all the ASICs.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: John Clements <john.clements@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h |  5 +++++
+ drivers/gpu/drm/amd/amdgpu/psp_v10_0.c  | 16 +++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c  | 26 ++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/psp_v12_0.c  | 26 ++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/psp_v3_1.c   | 27 +++++++++++++++++++++++++
+ 5 files changed, 100 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+index 09c5474ebcc3..d5620c46f3fc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+@@ -116,6 +116,8 @@ struct psp_funcs
+ 	int (*mem_training_init)(struct psp_context *psp);
+ 	void (*mem_training_fini)(struct psp_context *psp);
+ 	int (*mem_training)(struct psp_context *psp, uint32_t ops);
++	uint32_t (*ring_get_wptr)(struct psp_context *psp);
++	void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
+ };
+ 
+ #define AMDGPU_XGMI_MAX_CONNECTED_NODES		64
+@@ -346,6 +348,9 @@ struct amdgpu_psp_funcs {
+ 	((psp)->funcs->ras_cure_posion ? \
+ 	(psp)->funcs->ras_cure_posion(psp, (addr)) : -EINVAL)
+ 
++#define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
++#define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
++
+ extern const struct amd_ip_funcs psp_ip_funcs;
+ 
+ extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+index ed8beff02e62..b8a461d46cb5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+@@ -404,6 +404,20 @@ static int psp_v10_0_mode1_reset(struct psp_context *psp)
+ 	return -EINVAL;
+ }
+ 
++static uint32_t psp_v10_0_ring_get_wptr(struct psp_context *psp)
++{
++	struct amdgpu_device *adev = psp->adev;
++
++	return RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
++}
++
++static void psp_v10_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
++{
++	struct amdgpu_device *adev = psp->adev;
++
++	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
++}
++
+ static const struct psp_funcs psp_v10_0_funcs = {
+ 	.init_microcode = psp_v10_0_init_microcode,
+ 	.ring_init = psp_v10_0_ring_init,
+@@ -413,6 +427,8 @@ static const struct psp_funcs psp_v10_0_funcs = {
+ 	.cmd_submit = psp_v10_0_cmd_submit,
+ 	.compare_sram_data = psp_v10_0_compare_sram_data,
+ 	.mode1_reset = psp_v10_0_mode1_reset,
++	.ring_get_wptr = psp_v10_0_ring_get_wptr,
++	.ring_set_wptr = psp_v10_0_ring_set_wptr,
+ };
+ 
+ void psp_v10_0_set_psp_funcs(struct psp_context *psp)
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index 0875ece1bea2..68f4cd7311a8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -1076,6 +1076,30 @@ static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
+ 	return 0;
+ }
+ 
++static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
++{
++	uint32_t data;
++	struct amdgpu_device *adev = psp->adev;
++
++	if (psp_v11_0_support_vmr_ring(psp))
++		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
++	else
++		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
++
++	return data;
++}
++
++static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
++{
++	struct amdgpu_device *adev = psp->adev;
++
++	if (psp_v11_0_support_vmr_ring(psp)) {
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
++	} else
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
++}
++
+ static const struct psp_funcs psp_v11_0_funcs = {
+ 	.init_microcode = psp_v11_0_init_microcode,
+ 	.bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
+@@ -1099,6 +1123,8 @@ static const struct psp_funcs psp_v11_0_funcs = {
+ 	.mem_training_init = psp_v11_0_memory_training_init,
+ 	.mem_training_fini = psp_v11_0_memory_training_fini,
+ 	.mem_training = psp_v11_0_memory_training,
++	.ring_get_wptr = psp_v11_0_ring_get_wptr,
++	.ring_set_wptr = psp_v11_0_ring_set_wptr,
+ };
+ 
+ void psp_v11_0_set_psp_funcs(struct psp_context *psp)
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+index 8f553f6f92d6..75b3f9d15a18 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+@@ -547,6 +547,30 @@ static int psp_v12_0_mode1_reset(struct psp_context *psp)
+ 	return 0;
+ }
+ 
++static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp)
++{
++	uint32_t data;
++	struct amdgpu_device *adev = psp->adev;
++
++	if (psp_v12_0_support_vmr_ring(psp))
++		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
++	else
++		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
++
++	return data;
++}
++
++static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
++{
++	struct amdgpu_device *adev = psp->adev;
++
++	if (psp_v12_0_support_vmr_ring(psp)) {
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
++	} else
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
++}
++
+ static const struct psp_funcs psp_v12_0_funcs = {
+ 	.init_microcode = psp_v12_0_init_microcode,
+ 	.bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
+@@ -558,6 +582,8 @@ static const struct psp_funcs psp_v12_0_funcs = {
+ 	.cmd_submit = psp_v12_0_cmd_submit,
+ 	.compare_sram_data = psp_v12_0_compare_sram_data,
+ 	.mode1_reset = psp_v12_0_mode1_reset,
++	.ring_get_wptr = psp_v12_0_ring_get_wptr,
++	.ring_set_wptr = psp_v12_0_ring_set_wptr,
+ };
+ 
+ void psp_v12_0_set_psp_funcs(struct psp_context *psp)
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+index f652241aa71a..1de86e550a90 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+@@ -640,6 +640,31 @@ static bool psp_v3_1_support_vmr_ring(struct psp_context *psp)
+ 	return false;
+ }
+ 
++static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp)
++{
++	uint32_t data;
++	struct amdgpu_device *adev = psp->adev;
++
++	if (psp_v3_1_support_vmr_ring(psp))
++		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
++	else
++		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
++	return data;
++}
++
++static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value)
++{
++	struct amdgpu_device *adev = psp->adev;
++
++	if (psp_v3_1_support_vmr_ring(psp)) {
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
++		/* send interrupt to PSP for SRIOV ring write pointer update */
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
++			GFX_CTRL_CMD_ID_CONSUME_CMD);
++	} else
++		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
++}
++
+ static const struct psp_funcs psp_v3_1_funcs = {
+ 	.init_microcode = psp_v3_1_init_microcode,
+ 	.bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
+@@ -653,6 +678,8 @@ static const struct psp_funcs psp_v3_1_funcs = {
+ 	.smu_reload_quirk = psp_v3_1_smu_reload_quirk,
+ 	.mode1_reset = psp_v3_1_mode1_reset,
+ 	.support_vmr_ring = psp_v3_1_support_vmr_ring,
++	.ring_get_wptr = psp_v3_1_ring_get_wptr,
++	.ring_set_wptr = psp_v3_1_ring_set_wptr,
+ };
+ 
+ void psp_v3_1_set_psp_funcs(struct psp_context *psp)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4533-drm-amdgpu-add-helper-func-for-psp-ring-cmd-submissi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4533-drm-amdgpu-add-helper-func-for-psp-ring-cmd-submissi.patch
new file mode 100644
index 00000000..2fe6deb2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4533-drm-amdgpu-add-helper-func-for-psp-ring-cmd-submissi.patch
@@ -0,0 +1,96 @@
+From 2c729023ab5775f2963046218e056d49528474a5 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 18 Nov 2019 17:03:12 +0800
+Subject: [PATCH 4533/4736] drm/amdgpu: add helper func for psp ring cmd
+ submission
+
+Except for ring wptr update, the psp ring cmd submission
+function shouldn't be IP specific one. Create a common
+helper function to be shared for all the ASICs.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: John Clements <john.clements@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 50 +++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h |  4 ++
+ 2 files changed, 54 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 2b513e41ed3c..648cf9a49203 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1724,6 +1724,56 @@ int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
+ 	return psp_execute_np_fw_load(&adev->psp, &ucode);
+ }
+ 
++int psp_ring_cmd_submit(struct psp_context *psp,
++			uint64_t cmd_buf_mc_addr,
++			uint64_t fence_mc_addr,
++			int index)
++{
++	unsigned int psp_write_ptr_reg = 0;
++	struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
++	struct psp_ring *ring = &psp->km_ring;
++	struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
++	struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
++		ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
++	struct amdgpu_device *adev = psp->adev;
++	uint32_t ring_size_dw = ring->ring_size / 4;
++	uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
++
++	/* KM (GPCOM) prepare write pointer */
++	psp_write_ptr_reg = psp_ring_get_wptr(psp);
++
++	/* Update KM RB frame pointer to new frame */
++	/* write_frame ptr increments by size of rb_frame in bytes */
++	/* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
++	if ((psp_write_ptr_reg % ring_size_dw) == 0)
++		write_frame = ring_buffer_start;
++	else
++		write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
++	/* Check invalid write_frame ptr address */
++	if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
++		DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
++			  ring_buffer_start, ring_buffer_end, write_frame);
++		DRM_ERROR("write_frame is pointing to address out of bounds\n");
++		return -EINVAL;
++	}
++
++	/* Initialize KM RB frame */
++	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
++
++	/* Update KM RB frame */
++	write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
++	write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
++	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
++	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
++	write_frame->fence_value = index;
++	amdgpu_asic_flush_hdp(adev, NULL);
++
++	/* Update the write Pointer in DWORDs */
++	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
++	psp_ring_set_wptr(psp, psp_write_ptr_reg);
++	return 0;
++}
++
+ static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
+ 					enum AMDGPU_UCODE_ID ucode_type)
+ {
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+index d5620c46f3fc..482e7675b7da 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+@@ -377,4 +377,8 @@ int psp_rlc_autoload_start(struct psp_context *psp);
+ extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
+ int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
+ 		uint32_t value);
++int psp_ring_cmd_submit(struct psp_context *psp,
++			uint64_t cmd_buf_mc_addr,
++			uint64_t fence_mc_addr,
++			int index);
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4534-drm-amdgpu-switch-to-common-helper-func-for-psp-cmd-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4534-drm-amdgpu-switch-to-common-helper-func-for-psp-cmd-.patch
new file mode 100644
index 00000000..0512e441
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4534-drm-amdgpu-switch-to-common-helper-func-for-psp-cmd-.patch
@@ -0,0 +1,359 @@
+From 194ee6fbff8c8a309fd7fd3be75bade3420ede60 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 18 Nov 2019 17:39:55 +0800
+Subject: [PATCH 4534/4736] drm/amdgpu: switch to common helper func for psp
+ cmd submission
+
+Drop all the IP specific cmd_submit callback function
+and use the common helper instead
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: John Clements <john.clements@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |  2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h |  5 ---
+ drivers/gpu/drm/amd/amdgpu/psp_v10_0.c  | 49 --------------------
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c  | 58 ------------------------
+ drivers/gpu/drm/amd/amdgpu/psp_v12_0.c  | 58 ------------------------
+ drivers/gpu/drm/amd/amdgpu/psp_v3_1.c   | 60 -------------------------
+ 6 files changed, 1 insertion(+), 231 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 648cf9a49203..4ba444baf6db 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -158,7 +158,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
+ 	memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
+ 
+ 	index = atomic_inc_return(&psp->fence_value);
+-	ret = psp_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
++	ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
+         if (ret) {
+                 atomic_dec(&psp->fence_value);
+ 		mutex_unlock(&psp->mutex);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+index 482e7675b7da..40594f27dab1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+@@ -94,9 +94,6 @@ struct psp_funcs
+ 			    enum psp_ring_type ring_type);
+ 	int (*ring_destroy)(struct psp_context *psp,
+ 			    enum psp_ring_type ring_type);
+-	int (*cmd_submit)(struct psp_context *psp,
+-			  uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+-			  int index);
+ 	bool (*compare_sram_data)(struct psp_context *psp,
+ 				  struct amdgpu_firmware_info *ucode,
+ 				  enum AMDGPU_UCODE_ID ucode_type);
+@@ -302,8 +299,6 @@ struct amdgpu_psp_funcs {
+ #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
+ #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
+ #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
+-#define psp_cmd_submit(psp, cmd_mc, fence_mc, index) \
+-		(psp)->funcs->cmd_submit((psp), (cmd_mc), (fence_mc), (index))
+ #define psp_compare_sram_data(psp, ucode, type) \
+ 		(psp)->funcs->compare_sram_data((psp), (ucode), (type))
+ #define psp_init_microcode(psp) \
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+index b8a461d46cb5..e7d56c25b0f8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+@@ -227,54 +227,6 @@ static int psp_v10_0_ring_destroy(struct psp_context *psp,
+ 	return ret;
+ }
+ 
+-static int psp_v10_0_cmd_submit(struct psp_context *psp,
+-				uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+-				int index)
+-{
+-	unsigned int psp_write_ptr_reg = 0;
+-	struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
+-	struct psp_ring *ring = &psp->km_ring;
+-	struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
+-	struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
+-		ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
+-	struct amdgpu_device *adev = psp->adev;
+-	uint32_t ring_size_dw = ring->ring_size / 4;
+-	uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
+-
+-	/* KM (GPCOM) prepare write pointer */
+-	psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
+-
+-	/* Update KM RB frame pointer to new frame */
+-	if ((psp_write_ptr_reg % ring_size_dw) == 0)
+-		write_frame = ring_buffer_start;
+-	else
+-		write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
+-	/* Check invalid write_frame ptr address */
+-	if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
+-		DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
+-			  ring_buffer_start, ring_buffer_end, write_frame);
+-		DRM_ERROR("write_frame is pointing to address out of bounds\n");
+-		return -EINVAL;
+-	}
+-
+-	/* Initialize KM RB frame */
+-	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
+-
+-	/* Update KM RB frame */
+-	write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
+-	write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
+-	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
+-	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
+-	write_frame->fence_value = index;
+-	amdgpu_asic_flush_hdp(adev, NULL);
+-
+-	/* Update the write Pointer in DWORDs */
+-	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
+-	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
+-
+-	return 0;
+-}
+-
+ static int
+ psp_v10_0_sram_map(struct amdgpu_device *adev,
+ 		   unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
+@@ -424,7 +376,6 @@ static const struct psp_funcs psp_v10_0_funcs = {
+ 	.ring_create = psp_v10_0_ring_create,
+ 	.ring_stop = psp_v10_0_ring_stop,
+ 	.ring_destroy = psp_v10_0_ring_destroy,
+-	.cmd_submit = psp_v10_0_cmd_submit,
+ 	.compare_sram_data = psp_v10_0_compare_sram_data,
+ 	.mode1_reset = psp_v10_0_mode1_reset,
+ 	.ring_get_wptr = psp_v10_0_ring_get_wptr,
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index 68f4cd7311a8..a12804d6bdce 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -527,63 +527,6 @@ static int psp_v11_0_ring_destroy(struct psp_context *psp,
+ 	return ret;
+ }
+ 
+-static int psp_v11_0_cmd_submit(struct psp_context *psp,
+-			       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+-			       int index)
+-{
+-	unsigned int psp_write_ptr_reg = 0;
+-	struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
+-	struct psp_ring *ring = &psp->km_ring;
+-	struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
+-	struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
+-		ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
+-	struct amdgpu_device *adev = psp->adev;
+-	uint32_t ring_size_dw = ring->ring_size / 4;
+-	uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
+-
+-	/* KM (GPCOM) prepare write pointer */
+-	if (psp_v11_0_support_vmr_ring(psp))
+-		psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+-	else
+-		psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
+-
+-	/* Update KM RB frame pointer to new frame */
+-	/* write_frame ptr increments by size of rb_frame in bytes */
+-	/* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
+-	if ((psp_write_ptr_reg % ring_size_dw) == 0)
+-		write_frame = ring_buffer_start;
+-	else
+-		write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
+-	/* Check invalid write_frame ptr address */
+-	if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
+-		DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
+-			  ring_buffer_start, ring_buffer_end, write_frame);
+-		DRM_ERROR("write_frame is pointing to address out of bounds\n");
+-		return -EINVAL;
+-	}
+-
+-	/* Initialize KM RB frame */
+-	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
+-
+-	/* Update KM RB frame */
+-	write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
+-	write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
+-	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
+-	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
+-	write_frame->fence_value = index;
+-	amdgpu_asic_flush_hdp(adev, NULL);
+-
+-	/* Update the write Pointer in DWORDs */
+-	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
+-	if (psp_v11_0_support_vmr_ring(psp)) {
+-		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
+-		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
+-	} else
+-		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
+-
+-	return 0;
+-}
+-
+ static int
+ psp_v11_0_sram_map(struct amdgpu_device *adev,
+ 		  unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
+@@ -1109,7 +1052,6 @@ static const struct psp_funcs psp_v11_0_funcs = {
+ 	.ring_create = psp_v11_0_ring_create,
+ 	.ring_stop = psp_v11_0_ring_stop,
+ 	.ring_destroy = psp_v11_0_ring_destroy,
+-	.cmd_submit = psp_v11_0_cmd_submit,
+ 	.compare_sram_data = psp_v11_0_compare_sram_data,
+ 	.mode1_reset = psp_v11_0_mode1_reset,
+ 	.xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+index 75b3f9d15a18..58d8b6d732e8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+@@ -334,63 +334,6 @@ static int psp_v12_0_ring_destroy(struct psp_context *psp,
+ 	return ret;
+ }
+ 
+-static int psp_v12_0_cmd_submit(struct psp_context *psp,
+-			       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+-			       int index)
+-{
+-	unsigned int psp_write_ptr_reg = 0;
+-	struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
+-	struct psp_ring *ring = &psp->km_ring;
+-	struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
+-	struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
+-		ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
+-	struct amdgpu_device *adev = psp->adev;
+-	uint32_t ring_size_dw = ring->ring_size / 4;
+-	uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
+-
+-	/* KM (GPCOM) prepare write pointer */
+-	if (psp_v12_0_support_vmr_ring(psp))
+-		psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+-	else
+-		psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
+-
+-	/* Update KM RB frame pointer to new frame */
+-	/* write_frame ptr increments by size of rb_frame in bytes */
+-	/* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
+-	if ((psp_write_ptr_reg % ring_size_dw) == 0)
+-		write_frame = ring_buffer_start;
+-	else
+-		write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
+-	/* Check invalid write_frame ptr address */
+-	if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
+-		DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
+-			  ring_buffer_start, ring_buffer_end, write_frame);
+-		DRM_ERROR("write_frame is pointing to address out of bounds\n");
+-		return -EINVAL;
+-	}
+-
+-	/* Initialize KM RB frame */
+-	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
+-
+-	/* Update KM RB frame */
+-	write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
+-	write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
+-	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
+-	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
+-	write_frame->fence_value = index;
+-	amdgpu_asic_flush_hdp(adev, NULL);
+-
+-	/* Update the write Pointer in DWORDs */
+-	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
+-	if (psp_v12_0_support_vmr_ring(psp)) {
+-		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
+-		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
+-	} else
+-		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
+-
+-	return 0;
+-}
+-
+ static int
+ psp_v12_0_sram_map(struct amdgpu_device *adev,
+ 		  unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
+@@ -579,7 +522,6 @@ static const struct psp_funcs psp_v12_0_funcs = {
+ 	.ring_create = psp_v12_0_ring_create,
+ 	.ring_stop = psp_v12_0_ring_stop,
+ 	.ring_destroy = psp_v12_0_ring_destroy,
+-	.cmd_submit = psp_v12_0_cmd_submit,
+ 	.compare_sram_data = psp_v12_0_compare_sram_data,
+ 	.mode1_reset = psp_v12_0_mode1_reset,
+ 	.ring_get_wptr = psp_v12_0_ring_get_wptr,
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+index 1de86e550a90..839806cf1c6a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+@@ -408,65 +408,6 @@ static int psp_v3_1_ring_destroy(struct psp_context *psp,
+ 	return ret;
+ }
+ 
+-static int psp_v3_1_cmd_submit(struct psp_context *psp,
+-			       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+-			       int index)
+-{
+-	unsigned int psp_write_ptr_reg = 0;
+-	struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
+-	struct psp_ring *ring = &psp->km_ring;
+-	struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
+-	struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
+-		ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
+-	struct amdgpu_device *adev = psp->adev;
+-	uint32_t ring_size_dw = ring->ring_size / 4;
+-	uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
+-
+-	/* KM (GPCOM) prepare write pointer */
+-	if (psp_v3_1_support_vmr_ring(psp))
+-		psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+-	else
+-		psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
+-
+-	/* Update KM RB frame pointer to new frame */
+-	/* write_frame ptr increments by size of rb_frame in bytes */
+-	/* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
+-	if ((psp_write_ptr_reg % ring_size_dw) == 0)
+-		write_frame = ring_buffer_start;
+-	else
+-		write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
+-	/* Check invalid write_frame ptr address */
+-	if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
+-		DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
+-			  ring_buffer_start, ring_buffer_end, write_frame);
+-		DRM_ERROR("write_frame is pointing to address out of bounds\n");
+-		return -EINVAL;
+-	}
+-
+-	/* Initialize KM RB frame */
+-	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
+-
+-	/* Update KM RB frame */
+-	write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
+-	write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
+-	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
+-	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
+-	write_frame->fence_value = index;
+-	amdgpu_asic_flush_hdp(adev, NULL);
+-
+-	/* Update the write Pointer in DWORDs */
+-	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
+-	if (psp_v3_1_support_vmr_ring(psp)) {
+-		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
+-		/* send interrupt to PSP for SRIOV ring write pointer update */
+-		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
+-					GFX_CTRL_CMD_ID_CONSUME_CMD);
+-	} else
+-		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
+-
+-	return 0;
+-}
+-
+ static int
+ psp_v3_1_sram_map(struct amdgpu_device *adev,
+ 		  unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
+@@ -673,7 +614,6 @@ static const struct psp_funcs psp_v3_1_funcs = {
+ 	.ring_create = psp_v3_1_ring_create,
+ 	.ring_stop = psp_v3_1_ring_stop,
+ 	.ring_destroy = psp_v3_1_ring_destroy,
+-	.cmd_submit = psp_v3_1_cmd_submit,
+ 	.compare_sram_data = psp_v3_1_compare_sram_data,
+ 	.smu_reload_quirk = psp_v3_1_smu_reload_quirk,
+ 	.mode1_reset = psp_v3_1_mode1_reset,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4535-drm-amdgpu-pull-ras-controller-int-status-only-when-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4535-drm-amdgpu-pull-ras-controller-int-status-only-when-.patch
new file mode 100644
index 00000000..0c6df126
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4535-drm-amdgpu-pull-ras-controller-int-status-only-when-.patch
@@ -0,0 +1,55 @@
+From 34280098d831c417043d90306fc61b25a39e0587 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 18 Nov 2019 18:17:12 +0800
+Subject: [PATCH 4535/4736] drm/amdgpu: pull ras controller int status only
+ when ras enabled
+
+ras_controller_irq and athub_err_event_irq are only registered
+when PCIE_BIF ras is marked as supported. as the result, the driver
+also just need pull the int status in such case.
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: John Clements <john.clements@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 17 ++++++++++-------
+ 1 file changed, 10 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+index 48af4830a74f..4f6f128d13ae 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+@@ -52,6 +52,7 @@
+ #include "amdgpu_connectors.h"
+ #include "amdgpu_trace.h"
+ #include "amdgpu_amdkfd.h"
++#include "amdgpu_ras.h"
+ 
+ #include <linux/pm_runtime.h>
+ 
+@@ -159,13 +160,15 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg)
+ 	 * register to check whether the interrupt is triggered or not, and properly
+ 	 * ack the interrupt if it is there
+ 	 */
+-	if (adev->nbio.funcs &&
+-	    adev->nbio.funcs->handle_ras_controller_intr_no_bifring)
+-		adev->nbio.funcs->handle_ras_controller_intr_no_bifring(adev);
+-
+-	if (adev->nbio.funcs &&
+-	    adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring)
+-		adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
++	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF)) {
++		if (adev->nbio.funcs &&
++		    adev->nbio.funcs->handle_ras_controller_intr_no_bifring)
++			adev->nbio.funcs->handle_ras_controller_intr_no_bifring(adev);
++
++		if (adev->nbio.funcs &&
++		    adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring)
++			adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
++	}
+ 
+ 	return ret;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4536-drm-amd-powerplay-enable-gpu_busy_percent-sys-interf.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4536-drm-amd-powerplay-enable-gpu_busy_percent-sys-interf.patch
new file mode 100644
index 00000000..d50c8652
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4536-drm-amd-powerplay-enable-gpu_busy_percent-sys-interf.patch
@@ -0,0 +1,200 @@
+From 7a2e755d51f2676519900b8e877298bf012374a1 Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Wed, 13 Nov 2019 17:17:09 +0800
+Subject: [PATCH 4536/4736] drm/amd/powerplay: enable gpu_busy_percent sys
+ interface for renoir (v2)
+
+To get the value of gpu_busy_percent, it needs to realize
+get_current_activity_percent and get_metrics_table.
+The framework of renoir smu is different from old ones like raven. It
+needs to realize get_current_activity_percent and get_metrics_table in
+renoir_ppt.c like navi10.
+
+v2: remove unused variable (Alex)
+
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h |  4 +
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c    | 76 +++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c     | 33 ++++++++
+ 3 files changed, 113 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+index 1745e0146fba..44c65dd8850d 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+@@ -62,6 +62,10 @@ int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate);
+ 
+ int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
+ 
++int smu_v12_0_read_sensor(struct smu_context *smu,
++			  enum amd_pp_sensors sensor,
++			  void *data, uint32_t *size);
++
+ uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu);
+ 
+ int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable);
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 784903a313b7..b44ce143e895 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -139,6 +139,27 @@ static int renoir_get_smu_table_index(struct smu_context *smc, uint32_t index)
+ 	return mapping.map_to;
+ }
+ 
++static int renoir_get_metrics_table(struct smu_context *smu,
++				    SmuMetrics_t *metrics_table)
++{
++	struct smu_table_context *smu_table= &smu->smu_table;
++	int ret = 0;
++
++	if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
++		ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
++				(void *)smu_table->metrics_table, false);
++		if (ret) {
++			pr_info("Failed to export SMU metrics table!\n");
++			return ret;
++		}
++		smu_table->metrics_time = jiffies;
++	}
++
++	memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
++
++	return ret;
++}
++
+ static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
+ {
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+@@ -154,6 +175,11 @@ static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
+ 	if (!smu_table->clocks_table)
+ 		return -ENOMEM;
+ 
++	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
++	if (!smu_table->metrics_table)
++		return -ENOMEM;
++	smu_table->metrics_time = 0;
++
+ 	return 0;
+ }
+ 
+@@ -386,6 +412,32 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
+ 	return ret;
+ }
+ 
++static int renoir_get_current_activity_percent(struct smu_context *smu,
++					       enum amd_pp_sensors sensor,
++					       uint32_t *value)
++{
++	int ret = 0;
++	SmuMetrics_t metrics;
++
++	if (!value)
++		return -EINVAL;
++
++	ret = renoir_get_metrics_table(smu, &metrics);
++	if (ret)
++		return ret;
++
++	switch (sensor) {
++	case AMDGPU_PP_SENSOR_GPU_LOAD:
++		*value = metrics.AverageGfxActivity;
++		break;
++	default:
++		pr_err("Invalid sensor for retrieving clock activity\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
+ static int renoir_get_workload_type(struct smu_context *smu, uint32_t profile)
+ {
+ 
+@@ -699,6 +751,29 @@ static int renoir_get_power_profile_mode(struct smu_context *smu,
+ 	return size;
+ }
+ 
++static int renoir_read_sensor(struct smu_context *smu,
++				 enum amd_pp_sensors sensor,
++				 void *data, uint32_t *size)
++{
++	int ret = 0;
++
++	if (!data || !size)
++		return -EINVAL;
++
++	mutex_lock(&smu->sensor_lock);
++	switch (sensor) {
++	case AMDGPU_PP_SENSOR_GPU_LOAD:
++		ret = renoir_get_current_activity_percent(smu, sensor, (uint32_t *)data);
++		*size = 4;
++		break;
++	default:
++		ret = smu_v12_0_read_sensor(smu, sensor, data, size);
++	}
++	mutex_unlock(&smu->sensor_lock);
++
++	return ret;
++}
++
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_smu_msg_index = renoir_get_smu_msg_index,
+ 	.get_smu_table_index = renoir_get_smu_table_index,
+@@ -719,6 +794,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_dpm_clock_table = renoir_get_dpm_clock_table,
+ 	.set_watermarks_table = renoir_set_watermarks_table,
+ 	.get_power_profile_mode = renoir_get_power_profile_mode,
++	.read_sensor = renoir_read_sensor,
+ 	.check_fw_status = smu_v12_0_check_fw_status,
+ 	.check_fw_version = smu_v12_0_check_fw_version,
+ 	.powergate_sdma = smu_v12_0_powergate_sdma,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 18b24f954380..045167311ae8 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -223,6 +223,39 @@ int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
+ 		SMU_MSG_SetGfxCGPG, enable ? 1 : 0);
+ }
+ 
++int smu_v12_0_read_sensor(struct smu_context *smu,
++				 enum amd_pp_sensors sensor,
++				 void *data, uint32_t *size)
++{
++	int ret = 0;
++
++	if(!data || !size)
++		return -EINVAL;
++
++	switch (sensor) {
++	case AMDGPU_PP_SENSOR_GFX_MCLK:
++		ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
++		*size = 4;
++		break;
++	case AMDGPU_PP_SENSOR_GFX_SCLK:
++		ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
++		*size = 4;
++		break;
++	case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
++		*(uint32_t *)data = 0;
++		*size = 4;
++		break;
++	default:
++		ret = smu_common_read_sensor(smu, sensor, data, size);
++		break;
++	}
++
++	if (ret)
++		*size = 0;
++
++	return ret;
++}
++
+ /**
+  * smu_v12_0_get_gfxoff_status - get gfxoff status
+  *
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4537-drm-amdgpu-disable-gfxoff-when-using-register-read-i.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4537-drm-amdgpu-disable-gfxoff-when-using-register-read-i.patch
new file mode 100644
index 00000000..cf032b70
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4537-drm-amdgpu-disable-gfxoff-when-using-register-read-i.patch
@@ -0,0 +1,45 @@
+From 1914c0f1e3c19c49877c37ac9bdae96b1691993c Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 14 Nov 2019 11:39:05 -0500
+Subject: [PATCH 4537/4736] drm/amdgpu: disable gfxoff when using register read
+ interface
+
+When gfxoff is enabled, accessing gfx registers via MMIO
+can lead to a hang.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497
+Acked-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 3a7ea8e953f8..74ff077e89d0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -678,15 +678,19 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
+ 			return -ENOMEM;
+ 		alloc_size = info->read_mmr_reg.count * sizeof(*regs);
+ 
+-		for (i = 0; i < info->read_mmr_reg.count; i++)
++		amdgpu_gfx_off_ctrl(adev, false);
++		for (i = 0; i < info->read_mmr_reg.count; i++) {
+ 			if (amdgpu_asic_read_register(adev, se_num, sh_num,
+ 						      info->read_mmr_reg.dword_offset + i,
+ 						      &regs[i])) {
+ 				DRM_DEBUG_KMS("unallowed offset %#x\n",
+ 					      info->read_mmr_reg.dword_offset + i);
+ 				kfree(regs);
++				amdgpu_gfx_off_ctrl(adev, true);
+ 				return -EFAULT;
+ 			}
++		}
++		amdgpu_gfx_off_ctrl(adev, true);
+ 		n = copy_to_user(out, regs, min(size, alloc_size));
+ 		kfree(regs);
+ 		return n ? -EFAULT : 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4538-drm-amdgpu-add-asic-callback-for-BACO-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4538-drm-amdgpu-add-asic-callback-for-BACO-support.patch
new file mode 100644
index 00000000..701103e5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4538-drm-amdgpu-add-asic-callback-for-BACO-support.patch
@@ -0,0 +1,41 @@
+From ac82736a44cd284962cf06b49c16c3f27746f3fd Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 10:01:35 -0500
+Subject: [PATCH 4538/4736] drm/amdgpu: add asic callback for BACO support
+
+BACO - Bus Active, Chip Off
+
+Used to check whether the device supports BACO.  This will
+be used to enable runtime pm on devices which support BACO.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 9915f0472611..0e736a65d5dc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -599,6 +599,8 @@ struct amdgpu_asic_funcs {
+ 	bool (*need_reset_on_init)(struct amdgpu_device *adev);
+ 	/* PCIe replay counter */
+ 	uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
++	/* device supports BACO */
++	bool (*supports_baco)(struct amdgpu_device *adev);
+ };
+ 
+ /*
+@@ -1168,6 +1170,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
+ #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
+ #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
+ #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
++#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
++
+ #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
+ 
+ /* Common functions */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4539-drm-amdgpu-add-supports_baco-callback-for-soc15-asic.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4539-drm-amdgpu-add-supports_baco-callback-for-soc15-asic.patch
new file mode 100644
index 00000000..aae0cba9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4539-drm-amdgpu-add-supports_baco-callback-for-soc15-asic.patch
@@ -0,0 +1,70 @@
+From 72042998f27c98580d9b30c17eab504fad1389dc Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 15 Oct 2019 16:23:31 -0400
+Subject: [PATCH 4539/4736] drm/amdgpu: add supports_baco callback for soc15
+ asics. (v2)
+
+BACO - Bus Active, Chip Off
+
+Check the BACO capabilities from the powerplay table.
+
+v2: drop unrelated struct cleanup
+
+Reviewed-by: Evan Quan <evan.quan@amd.com> (v1)
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 41724a368d76..92230f1af2dd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -601,6 +601,28 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
+ 	}
+ }
+ 
++static bool soc15_supports_baco(struct amdgpu_device *adev)
++{
++	bool baco_support;
++
++	switch (adev->asic_type) {
++	case CHIP_VEGA10:
++	case CHIP_VEGA12:
++		soc15_asic_get_baco_capability(adev, &baco_support);
++		break;
++	case CHIP_VEGA20:
++		if (adev->psp.sos_fw_version >= 0x80067)
++			soc15_asic_get_baco_capability(adev, &baco_support);
++		else
++			baco_support = false;
++		break;
++	default:
++		return false;
++	}
++
++	return baco_support;
++}
++
+ /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
+ 			u32 cntl_reg, u32 status_reg)
+ {
+@@ -1003,6 +1025,7 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs =
+ 	.get_pcie_usage = &soc15_get_pcie_usage,
+ 	.need_reset_on_init = &soc15_need_reset_on_init,
+ 	.get_pcie_replay_count = &soc15_get_pcie_replay_count,
++	.supports_baco = &soc15_supports_baco,
+ };
+ 
+ static const struct amdgpu_asic_funcs vega20_asic_funcs =
+@@ -1024,6 +1047,7 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
+ 	.get_pcie_usage = &vega20_get_pcie_usage,
+ 	.need_reset_on_init = &soc15_need_reset_on_init,
+ 	.get_pcie_replay_count = &soc15_get_pcie_replay_count,
++	.supports_baco = &soc15_supports_baco,
+ };
+ 
+ static int soc15_common_early_init(void *handle)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4540-drm-amdgpu-add-supports_baco-callback-for-SI-asics.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4540-drm-amdgpu-add-supports_baco-callback-for-SI-asics.patch
new file mode 100644
index 00000000..f212c60e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4540-drm-amdgpu-add-supports_baco-callback-for-SI-asics.patch
@@ -0,0 +1,43 @@
+From d2bae632b5d40c329461b88a0acf17144db05024 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 10:15:36 -0500
+Subject: [PATCH 4540/4736] drm/amdgpu: add supports_baco callback for SI
+ asics.
+
+BACO - Bus Active, Chip Off
+
+Not supported.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/si.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
+index c8d645e45821..214d6cf4d295 100644
+--- a/drivers/gpu/drm/amd/amdgpu/si.c
++++ b/drivers/gpu/drm/amd/amdgpu/si.c
+@@ -1196,6 +1196,11 @@ static int si_asic_reset(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
++static bool si_asic_supports_baco(struct amdgpu_device *adev)
++{
++	return false;
++}
++
+ static enum amd_reset_method
+ si_asic_reset_method(struct amdgpu_device *adev)
+ {
+@@ -1424,6 +1429,7 @@ static const struct amdgpu_asic_funcs si_asic_funcs =
+ 	.get_pcie_usage = &si_get_pcie_usage,
+ 	.need_reset_on_init = &si_need_reset_on_init,
+ 	.get_pcie_replay_count = &si_get_pcie_replay_count,
++	.supports_baco = &si_asic_supports_baco,
+ };
+ 
+ static uint32_t si_get_rev_id(struct amdgpu_device *adev)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4541-drm-amdgpu-add-supports_baco-callback-for-CIK-asics.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4541-drm-amdgpu-add-supports_baco-callback-for-CIK-asics.patch
new file mode 100644
index 00000000..24d4bb20
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4541-drm-amdgpu-add-supports_baco-callback-for-CIK-asics.patch
@@ -0,0 +1,55 @@
+From 3e71111c486161a14d4129ee2b98cb22d4f7e626 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 10:16:15 -0500
+Subject: [PATCH 4541/4736] drm/amdgpu: add supports_baco callback for CIK
+ asics.
+
+BACO - Bus Active, Chip Off
+
+Check the BACO capabilities from the powerplay table.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/cik.c | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
+index cc3d9f91a769..a5162412989b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik.c
+@@ -1309,6 +1309,23 @@ static int cik_asic_pci_config_reset(struct amdgpu_device *adev)
+ 	return r;
+ }
+ 
++static bool cik_asic_supports_baco(struct amdgpu_device *adev)
++{
++	bool baco_support;
++
++	switch (adev->asic_type) {
++	case CHIP_BONAIRE:
++	case CHIP_HAWAII:
++		smu7_asic_get_baco_capability(adev, &baco_support);
++		break;
++	default:
++		baco_support = false;
++		break;
++	}
++
++	return baco_support;
++}
++
+ static enum amd_reset_method
+ cik_asic_reset_method(struct amdgpu_device *adev)
+ {
+@@ -1898,6 +1915,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs =
+ 	.get_pcie_usage = &cik_get_pcie_usage,
+ 	.need_reset_on_init = &cik_need_reset_on_init,
+ 	.get_pcie_replay_count = &cik_get_pcie_replay_count,
++	.supports_baco = &cik_asic_supports_baco,
+ };
+ 
+ static int cik_common_early_init(void *handle)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4542-drm-amdgpu-add-supports_baco-callback-for-VI-asics.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4542-drm-amdgpu-add-supports_baco-callback-for-VI-asics.patch
new file mode 100644
index 00000000..55340936
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4542-drm-amdgpu-add-supports_baco-callback-for-VI-asics.patch
@@ -0,0 +1,59 @@
+From 3f3118cc21cbe34225274412892b9e191f073159 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 10:17:05 -0500
+Subject: [PATCH 4542/4736] drm/amdgpu: add supports_baco callback for VI
+ asics.
+
+BACO - Bus Active, Chip Off
+
+Check the BACO capabilities from the powerplay table.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/vi.c | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
+index 34a466e785cb..14228bca071b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vi.c
++++ b/drivers/gpu/drm/amd/amdgpu/vi.c
+@@ -743,6 +743,27 @@ static int vi_asic_pci_config_reset(struct amdgpu_device *adev)
+ 	return r;
+ }
+ 
++static bool vi_asic_supports_baco(struct amdgpu_device *adev)
++{
++	bool baco_support;
++
++	switch (adev->asic_type) {
++	case CHIP_FIJI:
++	case CHIP_TONGA:
++	case CHIP_POLARIS10:
++	case CHIP_POLARIS11:
++	case CHIP_POLARIS12:
++	case CHIP_TOPAZ:
++		smu7_asic_get_baco_capability(adev, &baco_support);
++		break;
++	default:
++		baco_support = false;
++		break;
++	}
++
++	return baco_support;
++}
++
+ static enum amd_reset_method
+ vi_asic_reset_method(struct amdgpu_device *adev)
+ {
+@@ -1114,6 +1135,7 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =
+ 	.get_pcie_usage = &vi_get_pcie_usage,
+ 	.need_reset_on_init = &vi_need_reset_on_init,
+ 	.get_pcie_replay_count = &vi_get_pcie_replay_count,
++	.supports_baco = &vi_asic_supports_baco,
+ };
+ 
+ #define CZ_REV_BRISTOL(rev)	 \
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4543-drm-amdgpu-add-supports_baco-callback-for-NV-asics.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4543-drm-amdgpu-add-supports_baco-callback-for-NV-asics.patch
new file mode 100644
index 00000000..b101211d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4543-drm-amdgpu-add-supports_baco-callback-for-NV-asics.patch
@@ -0,0 +1,48 @@
+From 670826463241f5b9990f453e52dc9c321a228b4b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 7 Nov 2019 18:12:17 -0500
+Subject: [PATCH 4543/4736] drm/amdgpu: add supports_baco callback for NV
+ asics.
+
+BACO - Bus Active, Chip Off
+
+Check the BACO capabilities from the powerplay table.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 4a52e5d59807..5cdd6528f011 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -314,6 +314,16 @@ static int nv_asic_mode1_reset(struct amdgpu_device *adev)
+ 	return ret;
+ }
+ 
++static bool nv_asic_supports_baco(struct amdgpu_device *adev)
++{
++	struct smu_context *smu = &adev->smu;
++
++	if (smu_baco_is_support(smu))
++		return true;
++	else
++		return false;
++}
++
+ static enum amd_reset_method
+ nv_asic_reset_method(struct amdgpu_device *adev)
+ {
+@@ -619,6 +629,7 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
+ 	.get_pcie_usage = &nv_get_pcie_usage,
+ 	.need_reset_on_init = &nv_need_reset_on_init,
+ 	.get_pcie_replay_count = &nv_get_pcie_replay_count,
++	.supports_baco = &nv_asic_supports_baco,
+ };
+ 
+ static int nv_common_early_init(void *handle)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4544-drm-amdgpu-add-a-amdgpu_device_supports_baco-helper.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4544-drm-amdgpu-add-a-amdgpu_device_supports_baco-helper.patch
new file mode 100644
index 00000000..890ae322
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4544-drm-amdgpu-add-a-amdgpu_device_supports_baco-helper.patch
@@ -0,0 +1,60 @@
+From 5074a9aaadd952d79318a24bedb2e81e470089bf Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 28 Oct 2019 14:47:38 -0400
+Subject: [PATCH 4544/4736] drm/amdgpu: add a amdgpu_device_supports_baco
+ helper
+
+BACO - Bus Active, Chip Off
+
+To check if a device supports BACO or not.  This will be
+used in determining when to enable runtime pm.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 15 +++++++++++++++
+ 2 files changed, 16 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 0e736a65d5dc..c73ef0017ca5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1189,6 +1189,7 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
+ 					     const u32 array_size);
+ 
+ bool amdgpu_device_is_px(struct drm_device *dev);
++bool amdgpu_device_supports_baco(struct drm_device *dev);
+ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
+                                       struct amdgpu_device *peer_adev);
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 61fb27b4e89c..ee045f328bf2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -153,6 +153,21 @@ bool amdgpu_device_is_px(struct drm_device *dev)
+ 	return false;
+ }
+ 
++/**
++ * amdgpu_device_supports_baco - Does the device support BACO
++ *
++ * @dev: drm_device pointer
++ *
++ * Returns true if the device supporte BACO,
++ * otherwise return false.
++ */
++bool amdgpu_device_supports_baco(struct drm_device *dev)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++
++	return amdgpu_asic_supports_baco(adev);
++}
++
+ /**
+  * VRAM access helper functions.
+  *
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4545-drm-amdgpu-rename-amdgpu_device_is_px-to-amdgpu_devi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4545-drm-amdgpu-rename-amdgpu_device_is_px-to-amdgpu_devi.patch
new file mode 100644
index 00000000..999a8d96
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4545-drm-amdgpu-rename-amdgpu_device_is_px-to-amdgpu_devi.patch
@@ -0,0 +1,154 @@
+From 217481e7563fcefd8e806cb0bd39710623d6739e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 10:42:22 -0500
+Subject: [PATCH 4545/4736] drm/amdgpu: rename amdgpu_device_is_px to
+ amdgpu_device_supports_boco (v2)
+
+BACO - Bus Active, Chip Off
+BOCO - Bus Off, Chip Off
+
+To better match what we are checking for and to align with
+amdgpu_device_supports_baco.
+
+BOCO is used on PowerXpress/Hybrid Graphics systems and BACO
+is used on desktop dGPU boards.
+
+v2: fix typo in documentation
+
+Change-Id: Iba62fb630a8a1600c72e0da59524a3d99efc052a
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++++----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c    | 8 ++++----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c    | 6 +++---
+ 4 files changed, 12 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index c73ef0017ca5..e0423a9efe14 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1188,7 +1188,7 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
+ 					     const u32 *registers,
+ 					     const u32 array_size);
+ 
+-bool amdgpu_device_is_px(struct drm_device *dev);
++bool amdgpu_device_supports_boco(struct drm_device *dev);
+ bool amdgpu_device_supports_baco(struct drm_device *dev);
+ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
+                                       struct amdgpu_device *peer_adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index ee045f328bf2..ac0dd28ca0a1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -137,14 +137,14 @@ static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
+ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
+ 
+ /**
+- * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
++ * amdgpu_device_supports_boco - Is the device a dGPU with HG/PX power control
+  *
+  * @dev: drm_device pointer
+  *
+  * Returns true if the device is a dGPU with HG/PX power control,
+  * otherwise return false.
+  */
+-bool amdgpu_device_is_px(struct drm_device *dev)
++bool amdgpu_device_supports_boco(struct drm_device *dev)
+ {
+ 	struct amdgpu_device *adev = dev->dev_private;
+ 
+@@ -1091,7 +1091,7 @@ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switchero
+ {
+ 	struct drm_device *dev = pci_get_drvdata(pdev);
+ 
+-	if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
++	if (amdgpu_device_supports_boco(dev) && state == VGA_SWITCHEROO_OFF)
+ 		return;
+ 
+ 	if (state == VGA_SWITCHEROO_ON) {
+@@ -2919,7 +2919,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ 	 * ignore it */
+ 	vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
+ 
+-	if (amdgpu_device_is_px(ddev))
++	if (amdgpu_device_supports_boco(ddev))
+ 		runtime = true;
+ 	if (!pci_is_thunderbolt_attached(adev->pdev))
+ 		vga_switcheroo_register_client(adev->pdev,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 298f78947048..3acdad16f0c2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1200,7 +1200,7 @@ static int amdgpu_pmops_resume(struct device *dev)
+ 	struct drm_device *drm_dev = dev_get_drvdata(dev);
+ 
+ 	/* GPU comes up enabled by the bios on resume */
+-	if (amdgpu_device_is_px(drm_dev)) {
++	if (amdgpu_device_supports_boco(drm_dev)) {
+ 		pm_runtime_disable(dev);
+ 		pm_runtime_set_active(dev);
+ 		pm_runtime_enable(dev);
+@@ -1248,7 +1248,7 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)
+ 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
+ 	int ret;
+ 
+-	if (!amdgpu_device_is_px(drm_dev)) {
++	if (!amdgpu_device_supports_boco(drm_dev)) {
+ 		pm_runtime_forbid(dev);
+ 		return -EBUSY;
+ 	}
+@@ -1275,7 +1275,7 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
+ 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
+ 	int ret;
+ 
+-	if (!amdgpu_device_is_px(drm_dev))
++	if (!amdgpu_device_supports_boco(drm_dev))
+ 		return -EINVAL;
+ 
+ 	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+@@ -1300,7 +1300,7 @@ static int amdgpu_pmops_runtime_idle(struct device *dev)
+ 	struct drm_device *drm_dev = dev_get_drvdata(dev);
+ 	struct drm_crtc *crtc;
+ 
+-	if (!amdgpu_device_is_px(drm_dev)) {
++	if (!amdgpu_device_supports_boco(drm_dev)) {
+ 		pm_runtime_forbid(dev);
+ 		return -EBUSY;
+ 	}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 74ff077e89d0..591558fc6a9f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -88,7 +88,7 @@ void amdgpu_driver_unload_kms(struct drm_device *dev)
+ 	if (amdgpu_sriov_vf(adev))
+ 		amdgpu_virt_request_full_gpu(adev, false);
+ 
+-	if (amdgpu_device_is_px(dev)) {
++	if (amdgpu_device_supports_boco(dev)) {
+ 		pm_runtime_get_sync(dev->dev);
+ 		pm_runtime_forbid(dev->dev);
+ 	}
+@@ -177,7 +177,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
+ 				"Error during ACPI methods call\n");
+ 	}
+ 
+-	if (amdgpu_device_is_px(dev)) {
++	if (amdgpu_device_supports_boco(dev)) {
+ 		dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
+ 		pm_runtime_use_autosuspend(dev->dev);
+ 		pm_runtime_set_autosuspend_delay(dev->dev, 5000);
+@@ -190,7 +190,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
+ out:
+ 	if (r) {
+ 		/* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
+-		if (adev->rmmio && amdgpu_device_is_px(dev))
++		if (adev->rmmio && amdgpu_device_supports_boco(dev))
+ 			pm_runtime_put_noidle(dev->dev);
+ 		amdgpu_driver_unload_kms(dev);
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4546-drm-amdgpu-add-additional-boco-checks-to-runtime-sus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4546-drm-amdgpu-add-additional-boco-checks-to-runtime-sus.patch
new file mode 100644
index 00000000..075294bc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4546-drm-amdgpu-add-additional-boco-checks-to-runtime-sus.patch
@@ -0,0 +1,94 @@
+From 1d318cb06e47cb7a5235ba28549c45ec9f6d0c2c Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 10:50:24 -0500
+Subject: [PATCH 4546/4736] drm/amdgpu: add additional boco checks to runtime
+ suspend/resume (v2)
+
+BACO - Bus Active, Chip Off
+BOCO - Bus Off, Chip Off
+
+We will take slightly different paths for boco and baco.
+
+v2: fold together two consecutive if clauses
+
+Change-Id: I2467c2906f855140f909cff322be587850c16a25
+Reviewed-by: Evan Quan <evan.quan@amd.com> (v1)
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 47 ++++++++++++++-----------
+ 1 file changed, 26 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 3acdad16f0c2..db41bdba954e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1253,18 +1253,21 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)
+ 		return -EBUSY;
+ 	}
+ 
+-	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
++	if (amdgpu_device_supports_boco(drm_dev))
++		drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+ 	drm_kms_helper_poll_disable(drm_dev);
+ 
+ 	ret = amdgpu_device_suspend(drm_dev, false, false);
+-	pci_save_state(pdev);
+-	pci_disable_device(pdev);
+-	pci_ignore_hotplug(pdev);
+-	if (amdgpu_is_atpx_hybrid())
+-		pci_set_power_state(pdev, PCI_D3cold);
+-	else if (!amdgpu_has_atpx_dgpu_power_cntl())
+-		pci_set_power_state(pdev, PCI_D3hot);
+-	drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
++	if (amdgpu_device_supports_boco(drm_dev)) {
++		pci_save_state(pdev);
++		pci_disable_device(pdev);
++		pci_ignore_hotplug(pdev);
++		if (amdgpu_is_atpx_hybrid())
++			pci_set_power_state(pdev, PCI_D3cold);
++		else if (!amdgpu_has_atpx_dgpu_power_cntl())
++			pci_set_power_state(pdev, PCI_D3hot);
++		drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
++	}
+ 
+ 	return 0;
+ }
+@@ -1278,20 +1281,22 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
+ 	if (!amdgpu_device_supports_boco(drm_dev))
+ 		return -EINVAL;
+ 
+-	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+-
+-	if (amdgpu_is_atpx_hybrid() ||
+-	    !amdgpu_has_atpx_dgpu_power_cntl())
+-		pci_set_power_state(pdev, PCI_D0);
+-	pci_restore_state(pdev);
+-	ret = pci_enable_device(pdev);
+-	if (ret)
+-		return ret;
+-	pci_set_master(pdev);
+-
++	if (amdgpu_device_supports_boco(drm_dev)) {
++		drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
++
++		if (amdgpu_is_atpx_hybrid() ||
++	    	!amdgpu_has_atpx_dgpu_power_cntl())
++			pci_set_power_state(pdev, PCI_D0);
++		pci_restore_state(pdev);
++		ret = pci_enable_device(pdev);
++		if (ret)
++			return ret;
++		pci_set_master(pdev);
++	}
+ 	ret = amdgpu_device_resume(drm_dev, false, false);
+ 	drm_kms_helper_poll_enable(drm_dev);
+-	drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
++	if (amdgpu_device_supports_boco(drm_dev))
++		drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4547-drm-amdgpu-split-swSMU-baco_reset-into-enter-and-exi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4547-drm-amdgpu-split-swSMU-baco_reset-into-enter-and-exi.patch
new file mode 100644
index 00000000..dc2324a2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4547-drm-amdgpu-split-swSMU-baco_reset-into-enter-and-exi.patch
@@ -0,0 +1,210 @@
+From 35d91a87c879ace6c7a7936a0b11a9a319f0268e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 28 Oct 2019 15:20:03 -0400
+Subject: [PATCH 4547/4736] drm/amdgpu: split swSMU baco_reset into enter and
+ exit
+
+BACO - Bus Active, Chip Off
+
+So we can use it for power savings rather than just reset.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nv.c               |  7 ++++++-
+ drivers/gpu/drm/amd/amdgpu/soc15.c            | 10 ++++++++--
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 20 ++++++++++++++++---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  |  3 ++-
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  6 ++++--
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  3 ++-
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    |  3 ++-
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     |  9 ++++++++-
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c    |  3 ++-
+ 9 files changed, 51 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
+index 5cdd6528f011..66af92e7dcdf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nv.c
++++ b/drivers/gpu/drm/amd/amdgpu/nv.c
+@@ -352,7 +352,12 @@ static int nv_asic_reset(struct amdgpu_device *adev)
+ 	if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
+ 		if (!adev->in_suspend)
+ 			amdgpu_inc_vram_lost(adev);
+-		ret = smu_baco_reset(smu);
++		ret = smu_baco_enter(smu);
++		if (ret)
++			return ret;
++		ret = smu_baco_exit(smu);
++		if (ret)
++			return ret;
+ 	} else {
+ 		if (!adev->in_suspend)
+ 			amdgpu_inc_vram_lost(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 92230f1af2dd..805a92f87bf3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -510,9 +510,15 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+ 
+ 	if (is_support_sw_smu(adev)) {
+ 		struct smu_context *smu = &adev->smu;
++		int ret;
+ 
+-		if (smu_baco_reset(smu))
+-			return -EIO;
++		ret = smu_baco_enter(smu);
++		if (ret)
++			return ret;
++
++		ret = smu_baco_exit(smu);
++		if (ret)
++			return ret;
+ 	} else {
+ 		void *pp_handle = adev->powerplay.pp_handle;
+ 		const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 9483f5ff64e7..acbbafeea01c 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -2456,14 +2456,28 @@ int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
+ 	return 0;
+ }
+ 
+-int smu_baco_reset(struct smu_context *smu)
++int smu_baco_enter(struct smu_context *smu)
+ {
+ 	int ret = 0;
+ 
+ 	mutex_lock(&smu->mutex);
+ 
+-	if (smu->ppt_funcs->baco_reset)
+-		ret = smu->ppt_funcs->baco_reset(smu);
++	if (smu->ppt_funcs->baco_enter)
++		ret = smu->ppt_funcs->baco_enter(smu);
++
++	mutex_unlock(&smu->mutex);
++
++	return ret;
++}
++
++int smu_baco_exit(struct smu_context *smu)
++{
++	int ret = 0;
++
++	mutex_lock(&smu->mutex);
++
++	if (smu->ppt_funcs->baco_exit)
++		ret = smu->ppt_funcs->baco_exit(smu);
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 06c331d1e3e7..cf3c31b0524c 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -2163,7 +2163,8 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 	.baco_is_support= smu_v11_0_baco_is_support,
+ 	.baco_get_state = smu_v11_0_baco_get_state,
+ 	.baco_set_state = smu_v11_0_baco_set_state,
+-	.baco_reset = smu_v11_0_baco_reset,
++	.baco_enter = smu_v11_0_baco_enter,
++	.baco_exit = smu_v11_0_baco_exit,
+ 	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+ 	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+ 	.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index 5bac7efcd6ee..ada4a8dc4112 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -546,7 +546,8 @@ struct pptable_funcs {
+ 	bool (*baco_is_support)(struct smu_context *smu);
+ 	enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
+ 	int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
+-	int (*baco_reset)(struct smu_context *smu);
++	int (*baco_enter)(struct smu_context *smu);
++	int (*baco_exit)(struct smu_context *smu);
+ 	int (*mode2_reset)(struct smu_context *smu);
+ 	int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
+ 	int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
+@@ -628,7 +629,8 @@ bool smu_baco_is_support(struct smu_context *smu);
+ 
+ int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
+ 
+-int smu_baco_reset(struct smu_context *smu);
++int smu_baco_enter(struct smu_context *smu);
++int smu_baco_exit(struct smu_context *smu);
+ 
+ int smu_mode2_reset(struct smu_context *smu);
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index e71445548c6f..716fcb274191 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -249,7 +249,8 @@ enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu);
+ 
+ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
+ 
+-int smu_v11_0_baco_reset(struct smu_context *smu);
++int smu_v11_0_baco_enter(struct smu_context *smu);
++int smu_v11_0_baco_exit(struct smu_context *smu);
+ 
+ int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
+ 						 uint32_t *min, uint32_t *max);
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 8d5f33baaa77..24765e813cc2 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -2109,7 +2109,8 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.baco_is_support= smu_v11_0_baco_is_support,
+ 	.baco_get_state = smu_v11_0_baco_get_state,
+ 	.baco_set_state = smu_v11_0_baco_set_state,
+-	.baco_reset = smu_v11_0_baco_reset,
++	.baco_enter = smu_v11_0_baco_enter,
++	.baco_exit = smu_v11_0_baco_exit,
+ 	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+ 	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+ 	.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 52aadbaaabda..dd4437a9b3d0 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1714,7 +1714,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
+ 	return ret;
+ }
+ 
+-int smu_v11_0_baco_reset(struct smu_context *smu)
++int smu_v11_0_baco_enter(struct smu_context *smu)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+ 	int ret = 0;
+@@ -1732,6 +1732,13 @@ int smu_v11_0_baco_reset(struct smu_context *smu)
+ 
+ 	msleep(10);
+ 
++	return ret;
++}
++
++int smu_v11_0_baco_exit(struct smu_context *smu)
++{
++	int ret = 0;
++
+ 	ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
+ 	if (ret)
+ 		return ret;
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 399697a2ad7f..83862544a45c 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -3257,7 +3257,8 @@ static const struct pptable_funcs vega20_ppt_funcs = {
+ 	.baco_is_support= smu_v11_0_baco_is_support,
+ 	.baco_get_state = smu_v11_0_baco_get_state,
+ 	.baco_set_state = smu_v11_0_baco_set_state,
+-	.baco_reset = smu_v11_0_baco_reset,
++	.baco_enter = smu_v11_0_baco_enter,
++	.baco_exit = smu_v11_0_baco_exit,
+ 	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+ 	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+ 	.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4548-drm-amdgpu-add-helpers-for-baco-entry-and-exit.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4548-drm-amdgpu-add-helpers-for-baco-entry-and-exit.patch
new file mode 100644
index 00000000..59ef9498
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4548-drm-amdgpu-add-helpers-for-baco-entry-and-exit.patch
@@ -0,0 +1,106 @@
+From f98544ea9af75cdf57211c6a55b63dcf1ffeb999 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 12:33:09 -0500
+Subject: [PATCH 4548/4736] drm/amdgpu: add helpers for baco entry and exit
+
+BACO - Bus Active, Chip Off
+
+Will be used for runtime pm.  Entry will enter the BACO
+state (chip off).  Exit will exit the BACO state (chip on).
+
+Change-Id: I051a4b9996af9ee7c7639be65fbd5009a4379ab3
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  3 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 62 ++++++++++++++++++++++
+ 2 files changed, 64 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index e0423a9efe14..9679649082cb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1192,7 +1192,8 @@ bool amdgpu_device_supports_boco(struct drm_device *dev);
+ bool amdgpu_device_supports_baco(struct drm_device *dev);
+ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
+                                       struct amdgpu_device *peer_adev);
+-
++int amdgpu_device_baco_enter(struct drm_device *dev);
++int amdgpu_device_baco_exit(struct drm_device *dev);
+ /* atpx handler */
+ #if defined(CONFIG_VGA_SWITCHEROO)
+ void amdgpu_register_atpx_handler(void);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index ac0dd28ca0a1..ebdf775ab9b0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -4333,3 +4333,65 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
+ 		!(adev->gmc.aper_base & address_mask ||
+ 		  aper_limit & address_mask);
+ }
++
++int amdgpu_device_baco_enter(struct drm_device *dev)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++
++	if (!amdgpu_device_supports_baco(adev->ddev))
++		return -ENOTSUPP;
++
++	if (is_support_sw_smu(adev)) {
++		struct smu_context *smu = &adev->smu;
++		int ret;
++
++		ret = smu_baco_enter(smu);
++		if (ret)
++			return ret;
++
++		return 0;
++	} else {
++		void *pp_handle = adev->powerplay.pp_handle;
++		const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
++
++		if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
++			return -ENOENT;
++
++		/* enter BACO state */
++		if (pp_funcs->set_asic_baco_state(pp_handle, 1))
++			return -EIO;
++
++		return 0;
++	}
++}
++
++int amdgpu_device_baco_exit(struct drm_device *dev)
++{
++	struct amdgpu_device *adev = dev->dev_private;
++
++	if (!amdgpu_device_supports_baco(adev->ddev))
++		return -ENOTSUPP;
++
++	if (is_support_sw_smu(adev)) {
++		struct smu_context *smu = &adev->smu;
++		int ret;
++
++		ret = smu_baco_exit(smu);
++		if (ret)
++			return ret;
++
++		return 0;
++	} else {
++		void *pp_handle = adev->powerplay.pp_handle;
++		const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
++
++		if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
++			return -ENOENT;
++
++		/* exit BACO state */
++		if (pp_funcs->set_asic_baco_state(pp_handle, 0))
++			return -EIO;
++
++		return 0;
++	}
++}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4549-drm-amdgpu-add-baco-support-to-runtime-suspend-resum.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4549-drm-amdgpu-add-baco-support-to-runtime-suspend-resum.patch
new file mode 100644
index 00000000..8c3a8edd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4549-drm-amdgpu-add-baco-support-to-runtime-suspend-resum.patch
@@ -0,0 +1,53 @@
+From 7c67e9f1b6ee307d0470a82e31b21936d3724e4f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 12:54:12 -0500
+Subject: [PATCH 4549/4736] drm/amdgpu: add baco support to runtime
+ suspend/resume
+
+BACO - Bus Active, Chip Off
+
+This adds the necessary support to the runtime suspend
+and resume functions to handle boards that support
+baco.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index db41bdba954e..036e253def85 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1200,7 +1200,8 @@ static int amdgpu_pmops_resume(struct device *dev)
+ 	struct drm_device *drm_dev = dev_get_drvdata(dev);
+ 
+ 	/* GPU comes up enabled by the bios on resume */
+-	if (amdgpu_device_supports_boco(drm_dev)) {
++	if (amdgpu_device_supports_boco(drm_dev) ||
++	    amdgpu_device_supports_baco(drm_dev)) {
+ 		pm_runtime_disable(dev);
+ 		pm_runtime_set_active(dev);
+ 		pm_runtime_enable(dev);
+@@ -1267,6 +1268,8 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)
+ 		else if (!amdgpu_has_atpx_dgpu_power_cntl())
+ 			pci_set_power_state(pdev, PCI_D3hot);
+ 		drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
++	} else if (amdgpu_device_supports_baco(drm_dev)) {
++		amdgpu_device_baco_enter(drm_dev);
+ 	}
+ 
+ 	return 0;
+@@ -1292,6 +1295,8 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
+ 		if (ret)
+ 			return ret;
+ 		pci_set_master(pdev);
++	} else if (amdgpu_device_supports_baco(drm_dev)) {
++		amdgpu_device_baco_exit(drm_dev);
+ 	}
+ 	ret = amdgpu_device_resume(drm_dev, false, false);
+ 	drm_kms_helper_poll_enable(drm_dev);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4550-drm-amdgpu-start-to-disentangle-boco-from-runtime-pm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4550-drm-amdgpu-start-to-disentangle-boco-from-runtime-pm.patch
new file mode 100644
index 00000000..bdfaf13b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4550-drm-amdgpu-start-to-disentangle-boco-from-runtime-pm.patch
@@ -0,0 +1,131 @@
+From 3f6b71254c91d80d5a77a0124ecb6a5587ec4b10 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 7 Nov 2019 18:13:14 -0500
+Subject: [PATCH 4550/4736] drm/amdgpu: start to disentangle boco from runtime
+ pm
+
+BACO - Bus Active, Chip Off
+BOCO - Bus Off, Chip Off
+
+We originally only supported runtime pm on PX/HG
+laptops so most of the runtime pm code looks for this.
+Add a new flag to check for runtime pm enablement and
+use this rather than checking for PX/HG.
+
+Change-Id: I09683aeef460c4a64ce904d0b21f8d949617a97c
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  2 ++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  9 ++++++---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 13 ++++++++-----
+ 3 files changed, 16 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 9679649082cb..ccb1fd7cd2b6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1035,6 +1035,8 @@ struct amdgpu_device {
+ 
+ 	/* device pstate */
+ 	int				pstate;
++	/* enable runtime pm on the device */
++	bool                            runpm;
+ };
+ 
+ static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 036e253def85..6957ef4ef514 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1247,9 +1247,10 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)
+ {
+ 	struct pci_dev *pdev = to_pci_dev(dev);
+ 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
++	struct amdgpu_device *adev = drm_dev->dev_private;
+ 	int ret;
+ 
+-	if (!amdgpu_device_supports_boco(drm_dev)) {
++	if (!adev->runpm) {
+ 		pm_runtime_forbid(dev);
+ 		return -EBUSY;
+ 	}
+@@ -1279,9 +1280,10 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
+ {
+ 	struct pci_dev *pdev = to_pci_dev(dev);
+ 	struct drm_device *drm_dev = pci_get_drvdata(pdev);
++	struct amdgpu_device *adev = drm_dev->dev_private;
+ 	int ret;
+ 
+-	if (!amdgpu_device_supports_boco(drm_dev))
++	if (!adev->runpm)
+ 		return -EINVAL;
+ 
+ 	if (amdgpu_device_supports_boco(drm_dev)) {
+@@ -1308,9 +1310,10 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
+ static int amdgpu_pmops_runtime_idle(struct device *dev)
+ {
+ 	struct drm_device *drm_dev = dev_get_drvdata(dev);
++	struct amdgpu_device *adev = drm_dev->dev_private;
+ 	struct drm_crtc *crtc;
+ 
+-	if (!amdgpu_device_supports_boco(drm_dev)) {
++	if (!adev->runpm) {
+ 		pm_runtime_forbid(dev);
+ 		return -EBUSY;
+ 	}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index 591558fc6a9f..ab7697d7b70a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -88,7 +88,7 @@ void amdgpu_driver_unload_kms(struct drm_device *dev)
+ 	if (amdgpu_sriov_vf(adev))
+ 		amdgpu_virt_request_full_gpu(adev, false);
+ 
+-	if (amdgpu_device_supports_boco(dev)) {
++	if (adev->runpm) {
+ 		pm_runtime_get_sync(dev->dev);
+ 		pm_runtime_forbid(dev->dev);
+ 	}
+@@ -147,14 +147,17 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
+ 	}
+ 	dev->dev_private = (void *)adev;
+ 
+-	if ((amdgpu_runtime_pm != 0) &&
+-	    amdgpu_has_atpx() &&
++	if (amdgpu_has_atpx() &&
+ 	    (amdgpu_is_atpx_hybrid() ||
+ 	     amdgpu_has_atpx_dgpu_power_cntl()) &&
+ 	    ((flags & AMD_IS_APU) == 0) &&
+ 	    !pci_is_thunderbolt_attached(dev->pdev))
+ 		flags |= AMD_IS_PX;
+ 
++	if ((amdgpu_runtime_pm != 0) &&
++	    (flags & AMD_IS_PX))
++		adev->runpm = true;
++
+ 	/* amdgpu_device_init should report only fatal error
+ 	 * like memory allocation failure or iomapping failure,
+ 	 * or memory manager initialization failure, it must
+@@ -177,7 +180,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
+ 				"Error during ACPI methods call\n");
+ 	}
+ 
+-	if (amdgpu_device_supports_boco(dev)) {
++	if (adev->runpm) {
+ 		dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
+ 		pm_runtime_use_autosuspend(dev->dev);
+ 		pm_runtime_set_autosuspend_delay(dev->dev, 5000);
+@@ -190,7 +193,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
+ out:
+ 	if (r) {
+ 		/* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
+-		if (adev->rmmio && amdgpu_device_supports_boco(dev))
++		if (adev->rmmio && adev->runpm)
+ 			pm_runtime_put_noidle(dev->dev);
+ 		amdgpu_driver_unload_kms(dev);
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4551-drm-amdgpu-disentangle-runtime-pm-and-vga_switcheroo.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4551-drm-amdgpu-disentangle-runtime-pm-and-vga_switcheroo.patch
new file mode 100644
index 00000000..c9248ca9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4551-drm-amdgpu-disentangle-runtime-pm-and-vga_switcheroo.patch
@@ -0,0 +1,76 @@
+From a249a5a0231132509a586738be1e179f53737913 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 13:25:37 -0500
+Subject: [PATCH 4551/4736] drm/amdgpu: disentangle runtime pm and
+ vga_switcheroo
+
+Originally we only supported runtime pm on PX/HG laptops
+so vga_switcheroo and runtime pm are sort of entangled.
+
+Attempt to logically separate them.
+
+Change-Id: Ie7cfe18f55e79557018f004ffbb5ce66822c3efe
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 20 ++++++++++++--------
+ 1 file changed, 12 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index ebdf775ab9b0..62d088a4840b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2749,7 +2749,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ 		       uint32_t flags)
+ {
+ 	int r, i;
+-	bool runtime = false;
++	bool boco = false;
+ 	u32 max_MBps;
+ 
+ 	adev->shutdown = false;
+@@ -2920,11 +2920,13 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ 	vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
+ 
+ 	if (amdgpu_device_supports_boco(ddev))
+-		runtime = true;
+-	if (!pci_is_thunderbolt_attached(adev->pdev))
++		boco = true;
++	if (amdgpu_has_atpx() &&
++	     (amdgpu_is_atpx_hybrid() ||
++	      amdgpu_has_atpx_dgpu_power_cntl()))
+ 		vga_switcheroo_register_client(adev->pdev,
+-					       &amdgpu_switcheroo_ops, runtime);
+-	if (runtime)
++					       &amdgpu_switcheroo_ops, boco);
++	if (boco)
+ 		vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
+ 
+ 	if (amdgpu_emu_mode == 1) {
+@@ -3115,7 +3117,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ 
+ failed:
+ 	amdgpu_vf_error_trans_all(adev);
+-	if (runtime)
++	if (boco)
+ 		vga_switcheroo_fini_domain_pm_ops(adev->dev);
+ 
+ 	return r;
+@@ -3164,9 +3166,11 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
+ 
+ 	kfree(adev->bios);
+ 	adev->bios = NULL;
+-	if (!pci_is_thunderbolt_attached(adev->pdev))
++	if (amdgpu_has_atpx() &&
++	    (amdgpu_is_atpx_hybrid() ||
++	      amdgpu_has_atpx_dgpu_power_cntl()))
+ 		vga_switcheroo_unregister_client(adev->pdev);
+-	if (adev->flags & AMD_IS_PX)
++	if (amdgpu_device_supports_boco(adev->ddev))
+ 		vga_switcheroo_fini_domain_pm_ops(adev->dev);
+ 	vga_client_register(adev->pdev, NULL, NULL, NULL);
+ 	if (adev->rio_mem)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4552-drm-amdgpu-enable-runtime-pm-on-BACO-capable-boards-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4552-drm-amdgpu-enable-runtime-pm-on-BACO-capable-boards-.patch
new file mode 100644
index 00000000..4ba2b701
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4552-drm-amdgpu-enable-runtime-pm-on-BACO-capable-boards-.patch
@@ -0,0 +1,50 @@
+From 6732f803e38ae86d6c4ca361808f9e508c5fde11 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 4 Oct 2019 13:47:39 -0500
+Subject: [PATCH 4552/4736] drm/amdgpu: enable runtime pm on BACO capable
+ boards if runpm=1
+
+BACO - Bus Active, Chip Off
+
+Everything is in place now.  Not enabled by default yet.  You
+still have to specify runpm=1.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+index ab7697d7b70a..5fce120e2d86 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+@@ -154,10 +154,6 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
+ 	    !pci_is_thunderbolt_attached(dev->pdev))
+ 		flags |= AMD_IS_PX;
+ 
+-	if ((amdgpu_runtime_pm != 0) &&
+-	    (flags & AMD_IS_PX))
+-		adev->runpm = true;
+-
+ 	/* amdgpu_device_init should report only fatal error
+ 	 * like memory allocation failure or iomapping failure,
+ 	 * or memory manager initialization failure, it must
+@@ -170,6 +166,13 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
+ 		goto out;
+ 	}
+ 
++	if (amdgpu_device_supports_boco(dev) &&
++	    (amdgpu_runtime_pm != 0)) /* enable runpm by default */
++		adev->runpm = true;
++	else if (amdgpu_device_supports_baco(dev) &&
++		 (amdgpu_runtime_pm > 0)) /* enable runpm if runpm=1 */
++		adev->runpm = true;
++
+ 	/* Call ACPI methods: require modeset init
+ 	 * but failure is not fatal
+ 	 */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4553-drm-amdgpu-add-flag-to-indicate-amdgpu-vm-context.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4553-drm-amdgpu-add-flag-to-indicate-amdgpu-vm-context.patch
new file mode 100644
index 00000000..771f038e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4553-drm-amdgpu-add-flag-to-indicate-amdgpu-vm-context.patch
@@ -0,0 +1,64 @@
+From 9292503daaf0f632834e3336e37b000b229e0564 Mon Sep 17 00:00:00 2001
+From: Alex Sierra <alex.sierra@amd.com>
+Date: Mon, 18 Nov 2019 13:28:46 -0600
+Subject: [PATCH 4553/4736] drm/amdgpu: add flag to indicate amdgpu vm context
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Flag added to indicate if the amdgpu vm context is used for compute or
+graphics.
+
+Change-Id: Ia813037fda2ec2947d73f5c7328388078fbeebe5
+Signed-off-by: Alex Sierra <alex.sierra@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 ++
+ 2 files changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 7c5d9891d89a..c3e87ca13c53 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -2713,6 +2713,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ 		goto error_free_direct;
+ 
+ 	vm->pte_support_ats = false;
++	vm->is_compute_context = false;
+ 
+ 	if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
+ 		vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
+@@ -2900,6 +2901,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ 		vm->update_funcs = &amdgpu_vm_sdma_funcs;
+ 	dma_fence_put(vm->last_update);
+ 	vm->last_update = NULL;
++	vm->is_compute_context = true;
+ 
+ 	if (vm->pasid) {
+ 		unsigned long flags;
+@@ -2954,6 +2956,7 @@ void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+ 		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
+ 	}
+ 	vm->pasid = 0;
++	vm->is_compute_context = false;
+ }
+ 
+ /**
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+index 5cb25c1c54e0..76fcf853035c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+@@ -301,6 +301,8 @@ struct amdgpu_vm {
+ 	struct ttm_lru_bulk_move lru_bulk_move;
+ 	/* mark whether can do the bulk move */
+ 	bool			bulk_moveable;
++	/* Flag to indicate if VM is used for compute */
++	bool			is_compute_context;
+ };
+ 
+ struct amdgpu_vm_manager {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4554-amd-amdgpu-force-to-trigger-a-no-retry-fault-after-a.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4554-amd-amdgpu-force-to-trigger-a-no-retry-fault-after-a.patch
new file mode 100644
index 00000000..9fce78ec
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4554-amd-amdgpu-force-to-trigger-a-no-retry-fault-after-a.patch
@@ -0,0 +1,60 @@
+From 871a45729603c20acb9a0927eb549b667c9b68ba Mon Sep 17 00:00:00 2001
+From: Alex Sierra <alex.sierra@amd.com>
+Date: Mon, 18 Nov 2019 15:33:07 -0600
+Subject: [PATCH 4554/4736] amd/amdgpu: force to trigger a no-retry-fault after
+ a retry-fault
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Only for the debugger use case.
+
+[why]
+Avoid endless translation retries, after an invalid address access has
+been issued to the GPU. Instead, the trap handler is forced to enter by
+generating a no-retry-fault.
+A s_trap instruction is inserted in the debugger case to let the wave to
+enter trap handler to save context.
+
+[how]
+Intentionally using an invalid flag combination (F and P set at the same
+time) to trigger a no-retry-fault, after a retry-fault happens. This is
+only valid under compute context.
+
+Change-Id: I4180c30e2631dc0401cbd6171f8a6776e4733c9a
+Signed-off-by: Alex Sierra <alex.sierra@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index c3e87ca13c53..90ac5390ecdf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -3204,11 +3204,20 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, unsigned int pasid,
+ 	flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
+ 		AMDGPU_PTE_SYSTEM;
+ 
+-	if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
++	if (vm->is_compute_context) {
++		/* Intentionally setting invalid PTE flag
++		 * combination to force a no-retry-fault
++		 */
++		flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE |
++			AMDGPU_PTE_TF;
++		value = 0;
++
++	} else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
+ 		/* Redirect the access to the dummy page */
+ 		value = adev->dummy_page_addr;
+ 		flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
+ 			AMDGPU_PTE_WRITEABLE;
++
+ 	} else {
+ 		/* Let the hw retry silently on the PTE */
+ 		value = 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4555-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DCN2_0-and-DS.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4555-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DCN2_0-and-DS.patch
new file mode 100644
index 00000000..1debddf9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4555-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DCN2_0-and-DS.patch
@@ -0,0 +1,5022 @@
+From 3ffff051d14b90a48427a1a00b28557d625a6567 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Wed, 6 Nov 2019 14:38:55 -0500
+Subject: [PATCH 4555/4736] drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and
+ DSC_SUPPORTED
+
+[Why]
+
+DCN2 and DSC are stable enough to be build by default. So drop the flags.
+
+[How]
+
+Remove them using the unifdef tool. The following commands were executed
+in sequence:
+
+$ find -name '*.c' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';'
+$ find -name '*.h' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';'
+
+In addition:
+
+* Remove from kconfig, and replace any dependencies with DCN1_0.
+* Remove from any makefiles.
+* Fix and cleanup NV defninitions in dal_asic_id.h
+* Expand DCN1 ifdef to include DCN2 code in the following files:
+    * clk_mgr/clk_mgr.c: dc_clk_mgr_create()
+    * core/dc_resources.c: dc_create_resource_pool()
+    * dce/dce_dmcu.c: dcn20_*lock_phy()
+    * dce/dce_dmcu.c: dcn20_funcs
+    * dce/dce_dmcu.c: dcn20_dmcu_create()
+    * gpio/hw_factory.c: dal_hw_factory_init()
+    * gpio/hw_translate.c: dal_hw_translate_init()
+
+Signed-off-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    |  4 --
+ drivers/gpu/drm/amd/display/Kconfig           | 13 +----
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 -----
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  2 -
+ .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  2 -
+ .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c  |  2 -
+ drivers/gpu/drm/amd/display/dc/Makefile       | 12 ++---
+ .../drm/amd/display/dc/bios/bios_parser2.c    |  2 -
+ .../display/dc/bios/command_table_helper2.c   |  2 -
+ .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c  |  4 --
+ .../gpu/drm/amd/display/dc/clk_mgr/Makefile   |  2 -
+ .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  |  4 +-
+ drivers/gpu/drm/amd/display/dc/core/dc.c      | 48 -------------------
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 18 -------
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 24 ----------
+ .../drm/amd/display/dc/core/dc_link_hwss.c    |  6 ---
+ .../gpu/drm/amd/display/dc/core/dc_resource.c |  8 +---
+ .../gpu/drm/amd/display/dc/core/dc_stream.c   |  6 ---
+ .../gpu/drm/amd/display/dc/core/dc_surface.c  |  6 ---
+ drivers/gpu/drm/amd/display/dc/dc.h           | 38 ---------------
+ drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |  4 --
+ drivers/gpu/drm/amd/display/dc/dc_dsc.h       |  2 -
+ drivers/gpu/drm/amd/display/dc/dc_hw_types.h  | 20 --------
+ drivers/gpu/drm/amd/display/dc/dc_link.h      |  4 --
+ drivers/gpu/drm/amd/display/dc/dc_stream.h    | 16 -------
+ drivers/gpu/drm/amd/display/dc/dc_types.h     |  6 ---
+ drivers/gpu/drm/amd/display/dc/dce/dce_abm.h  |  4 --
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.h  |  2 -
+ .../drm/amd/display/dc/dce/dce_clock_source.c |  4 --
+ .../drm/amd/display/dc/dce/dce_clock_source.h |  6 ---
+ drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 14 ++----
+ drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h |  2 -
+ .../gpu/drm/amd/display/dc/dce/dce_hwseq.h    |  4 --
+ .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c   |  6 ---
+ .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.h   |  8 ----
+ .../display/dc/dce110/dce110_hw_sequencer.c   |  4 --
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c  |  6 ---
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h  |  4 --
+ .../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c   |  2 -
+ .../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c |  2 -
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c  |  2 -
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |  4 --
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h |  2 -
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 16 -------
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c  |  4 --
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h  |  6 ---
+ .../amd/display/dc/dcn10/dcn10_link_encoder.h | 10 ----
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c  |  2 -
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c  |  4 --
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c |  4 --
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |  9 ----
+ .../display/dc/dcn10/dcn10_stream_encoder.h   |  8 ----
+ drivers/gpu/drm/amd/display/dc/dcn20/Makefile |  2 -
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c  |  2 -
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h  |  2 -
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c |  2 -
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 14 ------
+ .../amd/display/dc/dcn20/dcn20_link_encoder.c |  6 ---
+ .../amd/display/dc/dcn20/dcn20_link_encoder.h |  2 -
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c |  4 --
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |  2 -
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 42 ----------------
+ .../drm/amd/display/dc/dcn20/dcn20_resource.h |  2 -
+ .../display/dc/dcn20/dcn20_stream_encoder.c   |  6 ---
+ .../amd/display/dc/dcn21/dcn21_link_encoder.c |  2 -
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c | 16 -------
+ drivers/gpu/drm/amd/display/dc/dm_helpers.h   |  2 -
+ drivers/gpu/drm/amd/display/dc/dm_pp_smu.h    |  6 ---
+ drivers/gpu/drm/amd/display/dc/dml/Makefile   |  4 +-
+ .../dc/dml/dcn21/display_mode_vba_21.c        |  2 -
+ .../dc/dml/dcn21/display_rq_dlg_calc_21.c     |  2 -
+ .../amd/display/dc/dml/display_mode_enums.h   |  2 -
+ .../drm/amd/display/dc/dml/display_mode_lib.c |  6 ---
+ .../drm/amd/display/dc/dml/display_mode_lib.h |  6 ---
+ .../amd/display/dc/dml/display_mode_structs.h |  2 -
+ .../drm/amd/display/dc/dml/display_mode_vba.c |  2 -
+ .../drm/amd/display/dc/dml/display_mode_vba.h |  2 -
+ drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c   |  2 -
+ .../gpu/drm/amd/display/dc/dsc/dscc_types.h   |  2 -
+ .../gpu/drm/amd/display/dc/dsc/qp_tables.h    |  2 -
+ drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c  |  2 -
+ drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h  |  2 -
+ .../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c  |  2 -
+ drivers/gpu/drm/amd/display/dc/gpio/Makefile  |  2 -
+ .../display/dc/gpio/dcn20/hw_factory_dcn20.c  |  2 -
+ .../display/dc/gpio/dcn20/hw_factory_dcn20.h  |  2 -
+ .../dc/gpio/dcn20/hw_translate_dcn20.c        |  2 -
+ .../dc/gpio/dcn20/hw_translate_dcn20.h        |  2 -
+ .../display/dc/gpio/dcn21/hw_factory_dcn21.c  |  2 -
+ .../dc/gpio/dcn21/hw_translate_dcn21.c        |  2 -
+ .../gpu/drm/amd/display/dc/gpio/ddc_regs.h    | 12 -----
+ drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c  |  4 --
+ .../gpu/drm/amd/display/dc/gpio/hw_factory.c  |  6 +--
+ .../drm/amd/display/dc/gpio/hw_translate.c    |  6 +--
+ .../gpu/drm/amd/display/dc/inc/core_status.h  |  2 -
+ .../gpu/drm/amd/display/dc/inc/core_types.h   | 22 ---------
+ .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |  2 -
+ .../amd/display/dc/inc/hw/clk_mgr_internal.h  | 12 -----
+ .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h  |  4 --
+ drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h   | 12 -----
+ drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h   |  2 -
+ drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h   | 10 ----
+ drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |  4 --
+ .../gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 10 ----
+ .../drm/amd/display/dc/inc/hw/link_encoder.h  |  8 ----
+ drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h   | 10 ----
+ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h   |  4 --
+ .../amd/display/dc/inc/hw/stream_encoder.h    | 10 ----
+ .../amd/display/dc/inc/hw/timing_generator.h  |  8 ----
+ .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 12 -----
+ drivers/gpu/drm/amd/display/dc/inc/resource.h |  4 --
+ drivers/gpu/drm/amd/display/dc/irq/Makefile   |  2 -
+ .../dc/virtual/virtual_stream_encoder.c       |  8 ----
+ .../gpu/drm/amd/display/include/dal_asic_id.h |  2 -
+ .../gpu/drm/amd/display/include/dal_types.h   |  2 -
+ .../drm/amd/display/include/logger_types.h    |  6 ---
+ .../drm/amd/display/modules/inc/mod_shared.h  |  2 -
+ 117 files changed, 14 insertions(+), 744 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 62d088a4840b..3f587dce39e2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1545,7 +1545,6 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
+ 		}
+ 
+ parse_soc_bounding_box:
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 		/*
+ 		 * soc bounding box info is not integrated in disocovery table,
+ 		 * we always need to parse it from gpu info firmware.
+@@ -1556,7 +1555,6 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
+ 									le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+ 			adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
+ 		}
+-#endif
+ 		break;
+ 	}
+ 	default:
+@@ -2620,8 +2618,6 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
+ 	case CHIP_VEGA20:
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ 	case CHIP_RAVEN:
+-#endif
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+ 	case CHIP_NAVI12:
+diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
+index 9eae7c67ceb5..19250f316da3 100644
+--- a/drivers/gpu/drm/amd/display/Kconfig
++++ b/drivers/gpu/drm/amd/display/Kconfig
+@@ -14,21 +14,11 @@ config DRM_AMD_DC
+ config DRM_AMD_DC_DCN1_0
+ 	def_bool n
+ 	help
+-	  RV family support for display engine
+-
+-config DRM_AMD_DC_DCN2_0
+-	bool "DCN 2.0 family"
+-	default y
+-	depends on DRM_AMD_DC && X86
+-	depends on DRM_AMD_DC_DCN1_0
+-	help
+-	  Choose this option if you want to have
+-	  Navi support for display engine
++	  RV and NV family support for display engine
+ 
+ config DRM_AMD_DC_DCN2_1
+ 	bool "DCN 2.1 family"
+ 	depends on DRM_AMD_DC && X86
+-	depends on DRM_AMD_DC_DCN2_0
+ 	help
+ 	  Choose this option if you want to have
+ 	  Renoir support for display engine
+@@ -38,7 +28,6 @@ config DRM_AMD_DC_DSC_SUPPORT
+ 	default y
+ 	depends on DRM_AMD_DC && X86
+ 	depends on DRM_AMD_DC_DCN1_0
+-	depends on DRM_AMD_DC_DCN2_0
+ 	help
+ 	  Choose this option if you want to have
+ 	  Dynamic Stream Compression support
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 430008124373..3ec482e79ecf 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -943,9 +943,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ 
+ 	init_data.flags.power_down_display_on_boot = true;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	init_data.soc_bounding_box = adev->dm.soc_bounding_box;
+-#endif
+ 
+ 	/* Display Core create. */
+ 	adev->dm.dc = dc_create(&init_data);
+@@ -2741,10 +2739,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
+ 		break;
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ 	case CHIP_RAVEN:
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ 	case CHIP_RENOIR:
+ #endif
+@@ -2985,7 +2981,6 @@ static int dm_early_init(void *handle)
+ 		adev->mode_info.num_dig = 4;
+ 		break;
+ #endif
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI12:
+ 		adev->mode_info.num_crtc = 6;
+@@ -2997,7 +2992,6 @@ static int dm_early_init(void *handle)
+ 		adev->mode_info.num_hpd = 5;
+ 		adev->mode_info.num_dig = 5;
+ 		break;
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ 	case CHIP_RENOIR:
+ 		adev->mode_info.num_crtc = 4;
+@@ -3297,11 +3291,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
+ 	if (adev->asic_type == CHIP_VEGA10 ||
+ 	    adev->asic_type == CHIP_VEGA12 ||
+ 	    adev->asic_type == CHIP_VEGA20 ||
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	    adev->asic_type == CHIP_NAVI10 ||
+ 	    adev->asic_type == CHIP_NAVI14 ||
+ 	    adev->asic_type == CHIP_NAVI12 ||
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ 	    adev->asic_type == CHIP_RENOIR ||
+ #endif
+@@ -4001,10 +3993,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ 	bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
+ 	int mode_refresh;
+ 	int preferred_refresh = 0;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	struct dsc_dec_dpcd_caps dsc_caps;
+ 	uint32_t link_bandwidth_kbps;
+-#endif
+ 
+ 	struct dc_sink *sink = NULL;
+ 	if (aconnector == NULL) {
+@@ -4078,7 +4068,6 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ 		fill_stream_properties_from_drm_display_mode(stream,
+ 			&mode, &aconnector->base, con_state, old_stream);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	stream->timing.flags.DSC = 0;
+ 
+ 	if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
+@@ -4097,7 +4086,6 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ 						  &stream->timing.dsc_cfg))
+ 				stream->timing.flags.DSC = 1;
+ 	}
+-#endif
+ 
+ 	update_stream_scaling_settings(&mode, dm_state, stream);
+ 
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+index 1fc810bf02af..e5ef8be7b813 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+@@ -281,7 +281,6 @@ struct amdgpu_display_manager {
+ 
+ 	const struct firmware *fw_dmcu;
+ 	uint32_t dmcu_fw_version;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	/**
+ 	 * @soc_bounding_box:
+ 	 *
+@@ -289,7 +288,6 @@ struct amdgpu_display_manager {
+ 	 * available in FW
+ 	 */
+ 	const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
+-#endif
+ };
+ 
+ struct amdgpu_dm_connector {
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+index 92ba7ca84d7c..8522e66db4ea 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+@@ -539,7 +539,6 @@ bool dm_helpers_submit_i2c(
+ 
+ 	return result;
+ }
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool dm_helpers_dp_write_dsc_enable(
+ 		struct dc_context *ctx,
+ 		const struct dc_stream_state *stream,
+@@ -550,7 +549,6 @@ bool dm_helpers_dp_write_dsc_enable(
+ 
+ 	return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, &enable_dsc, 1);
+ }
+-#endif
+ 
+ bool dm_helpers_is_dp_sink_present(struct dc_link *link)
+ {
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+index e42b162ee5d3..254123a02aa3 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+@@ -996,7 +996,6 @@ void dm_pp_get_funcs(
+ 		funcs->rv_funcs.set_hard_min_fclk_by_freq =
+ 				pp_rv_set_hard_min_fclk_by_freq;
+ 		break;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	case DCN_VERSION_2_0:
+ 		funcs->ctx.ver = PP_SMU_VER_NV;
+ 		funcs->nv_funcs.pp_smu.dm = ctx;
+@@ -1019,7 +1018,6 @@ void dm_pp_get_funcs(
+ 		funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
+ 		funcs->nv_funcs.set_pstate_handshake_support = pp_nv_set_pstate_handshake_support;
+ 		break;
+-#endif
+ 
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_1
+ 	case DCN_VERSION_2_1:
+diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
+index 90482b158283..38ef29719400 100644
+--- a/drivers/gpu/drm/amd/display/dc/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/Makefile
+@@ -25,18 +25,12 @@
+ 
+ DC_LIBS = basics bios calcs clk_mgr dce gpio irq virtual
+ 
+-ifdef CONFIG_DRM_AMD_DC_DCN2_0
++ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ DC_LIBS += dcn20
+-endif
+-
+-
+-ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ DC_LIBS += dsc
+-endif
+-
+-ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ DC_LIBS += dcn10 dml
+ endif
++
+ ifdef CONFIG_DRM_AMD_DC_DCN2_1
+ DC_LIBS += dcn21
+ endif
+@@ -59,7 +53,7 @@ include $(AMD_DC)
+ DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \
+ dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o
+ 
+-ifdef CONFIG_DRM_AMD_DC_DCN2_0
++ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ DISPLAY_CORE += dc_vm_helper.o
+ endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index 03a5e82a7b2d..c70bfdca5d2f 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -1415,10 +1415,8 @@ static enum bp_result get_integrated_info_v11(
+ 	info->ma_channel_number = info_v11->umachannelnumber;
+ 	info->lvds_ss_percentage =
+ 	le16_to_cpu(info_v11->lvds_ss_percentage);
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	info->dp_ss_control =
+ 	le16_to_cpu(info_v11->reserved1);
+-#endif
+ 	info->lvds_sspread_rate_in_10hz =
+ 	le16_to_cpu(info_v11->lvds_ss_rate_10hz);
+ 	info->hdmi_ss_percentage =
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+index db153ddf0fee..45bb2bd81ba1 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+@@ -62,11 +62,9 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
+ 		return true;
+ #endif
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	case DCN_VERSION_2_0:
+ 		*h = dal_cmd_tbl_helper_dce112_get_table2();
+ 		return true;
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ 	case DCN_VERSION_2_1:
+ 		*h = dal_cmd_tbl_helper_dce112_get_table2();
+diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+index 9b2cb57bf2ba..a4ddd657598f 100644
+--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+@@ -53,13 +53,9 @@
+  * remain as-is as it provides us with a guarantee from HW that it is correct.
+  */
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ /* Defaults from spreadsheet rev#247.
+  * RV2 delta: dram_clock_change_latency, max_num_dpp
+  */
+-#else
+-/* Defaults from spreadsheet rev#247 */
+-#endif
+ const struct dcn_soc_bounding_box dcn10_soc_defaults = {
+ 		/* latencies */
+ 		.sr_exit_time = 17, /*us*/
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+index b864869cc7e3..9f15817a3eed 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+@@ -72,9 +72,7 @@ CLK_MGR_DCN10 = rv1_clk_mgr.o rv1_clk_mgr_vbios_smu.o rv2_clk_mgr.o
+ AMD_DAL_CLK_MGR_DCN10 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn10/,$(CLK_MGR_DCN10))
+ 
+ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN10)
+-endif
+ 
+-ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ ###############################################################################
+ # DCN20
+ ###############################################################################
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+index 8af8fab14bcb..3d42bb4355f8 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+@@ -150,13 +150,11 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
+ 			break;
+ 		}
+ 		break;
+-#endif	/* Family RV */
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	case FAMILY_NV:
+ 		dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+ 		break;
+-#endif /* Family NV */
++#endif	/* Family RV and NV*/
+ 
+ 	default:
+ 		ASSERT(0); /* Unknown Asic */
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 81f4499490b9..121465bf223f 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -57,13 +57,9 @@
+ #include "dc_link_dp.h"
+ #include "dc_dmub_srv.h"
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dsc.h"
+-#endif
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ #include "vm_helper.h"
+-#endif
+ 
+ #include "dce/dce_i2c.h"
+ 
+@@ -575,11 +571,9 @@ static void dc_destruct(struct dc *dc)
+ 	dc->dcn_ip = NULL;
+ 
+ #endif
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	kfree(dc->vm_helper);
+ 	dc->vm_helper = NULL;
+ 
+-#endif
+ }
+ 
+ static bool dc_construct(struct dc *dc,
+@@ -596,11 +590,9 @@ static bool dc_construct(struct dc *dc,
+ 	enum dce_version dc_version = DCE_VERSION_UNKNOWN;
+ 	dc->config = init_params->flags;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	// Allocate memory for the vm_helper
+ 	dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
+ 
+-#endif
+ 	memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
+ 
+ 	dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
+@@ -634,9 +626,7 @@ static bool dc_construct(struct dc *dc,
+ 	}
+ 
+ 	dc->dcn_ip = dcn_ip;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	dc->soc_bounding_box = init_params->soc_bounding_box;
+-#endif
+ #endif
+ 
+ 	dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
+@@ -738,7 +728,6 @@ static bool dc_construct(struct dc *dc,
+ 	return false;
+ }
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ static bool disable_all_writeback_pipes_for_stream(
+ 		const struct dc *dc,
+ 		struct dc_stream_state *stream,
+@@ -751,7 +740,6 @@ static bool disable_all_writeback_pipes_for_stream(
+ 
+ 	return true;
+ }
+-#endif
+ 
+ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
+ {
+@@ -777,16 +765,12 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
+ 		}
+ 		if (should_disable && old_stream) {
+ 			dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 			disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
+-#endif
+ 			if (dc->hwss.apply_ctx_for_surface)
+ 				dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
+ 		}
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 		if (dc->hwss.program_front_end_for_ctx)
+ 			dc->hwss.program_front_end_for_ctx(dc, dangling_context);
+-#endif
+ 	}
+ 
+ 	current_ctx = dc->current_state;
+@@ -1176,10 +1160,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ 				context->stream_status[i].plane_count,
+ 				context); /* use new pipe config in new context */
+ 		}
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	if (dc->hwss.program_front_end_for_ctx)
+ 		dc->hwss.program_front_end_for_ctx(dc, context);
+-#endif
+ 
+ 	/* Program hardware */
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+@@ -1198,10 +1180,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ 	}
+ 
+ 	/* Program all planes within new context*/
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	if (dc->hwss.program_front_end_for_ctx)
+ 		dc->hwss.program_front_end_for_ctx(dc, context);
+-#endif
+ 	for (i = 0; i < context->stream_count; i++) {
+ 		const struct dc_link *link = context->streams[i]->link;
+ 
+@@ -1685,10 +1665,8 @@ static enum surface_update_type check_update_surfaces_for_stream(
+ 		if (stream_update->gamut_remap)
+ 			su_flags->bits.gamut_remap = 1;
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 		if (stream_update->wb_update)
+ 			su_flags->bits.wb_update = 1;
+-#endif
+ 		if (su_flags->raw != 0)
+ 			overall_type = UPDATE_TYPE_FULL;
+ 
+@@ -1851,7 +1829,6 @@ static void copy_surface_update_to_plane(
+ 			sizeof(struct dc_transfer_func_distributed_points));
+ 	}
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	if (srf_update->func_shaper &&
+ 			(surface->in_shaper_func !=
+ 			srf_update->func_shaper))
+@@ -1874,7 +1851,6 @@ static void copy_surface_update_to_plane(
+ 		memcpy(surface->blend_tf, srf_update->blend_tf,
+ 		sizeof(*surface->blend_tf));
+ 
+-#endif
+ 	if (srf_update->input_csc_color_matrix)
+ 		surface->input_csc_color_matrix =
+ 			*srf_update->input_csc_color_matrix;
+@@ -1949,7 +1925,6 @@ static void copy_stream_update_to_stream(struct dc *dc,
+ 
+ 	if (update->dither_option)
+ 		stream->dither_option = *update->dither_option;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	/* update current stream with writeback info */
+ 	if (update->wb_update) {
+ 		int i;
+@@ -1960,8 +1935,6 @@ static void copy_stream_update_to_stream(struct dc *dc,
+ 			stream->writeback_info[i] =
+ 				update->wb_update->writeback_info[i];
+ 	}
+-#endif
+-#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
+ 	if (update->dsc_config) {
+ 		struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
+ 		uint32_t old_dsc_enabled = stream->timing.flags.DSC;
+@@ -1976,7 +1949,6 @@ static void copy_stream_update_to_stream(struct dc *dc,
+ 			stream->timing.flags.DSC = old_dsc_enabled;
+ 		}
+ 	}
+-#endif
+ }
+ 
+ static void commit_planes_do_stream_update(struct dc *dc,
+@@ -2017,31 +1989,25 @@ static void commit_planes_do_stream_update(struct dc *dc,
+ 				dc_stream_program_csc_matrix(dc, stream);
+ 
+ 			if (stream_update->dither_option) {
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 				struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
+-#endif
+ 				resource_build_bit_depth_reduction_params(pipe_ctx->stream,
+ 									&pipe_ctx->stream->bit_depth_params);
+ 				pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
+ 						&stream->bit_depth_params,
+ 						&stream->clamping);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 				while (odm_pipe) {
+ 					odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
+ 							&stream->bit_depth_params,
+ 							&stream->clamping);
+ 					odm_pipe = odm_pipe->next_odm_pipe;
+ 				}
+-#endif
+ 			}
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
+ 			if (stream_update->dsc_config && dc->hwss.pipe_control_lock_global) {
+ 				dc->hwss.pipe_control_lock_global(dc, pipe_ctx, true);
+ 				dp_update_dsc_config(pipe_ctx);
+ 				dc->hwss.pipe_control_lock_global(dc, pipe_ctx, false);
+ 			}
+-#endif
+ 			/* Full fe update*/
+ 			if (update_type == UPDATE_TYPE_FAST)
+ 				continue;
+@@ -2128,15 +2094,12 @@ static void commit_planes_for_stream(struct dc *dc,
+ 		 */
+ 		if (dc->hwss.apply_ctx_for_surface)
+ 			dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 		if (dc->hwss.program_front_end_for_ctx)
+ 			dc->hwss.program_front_end_for_ctx(dc, context);
+-#endif
+ 
+ 		return;
+ 	}
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
+ 		for (i = 0; i < surface_count; i++) {
+ 			struct dc_plane_state *plane_state = srf_updates[i].surface;
+@@ -2158,7 +2121,6 @@ static void commit_planes_for_stream(struct dc *dc,
+ 			}
+ 		}
+ 	}
+-#endif
+ 
+ 	// Update Type FULL, Surface updates
+ 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
+@@ -2179,7 +2141,6 @@ static void commit_planes_for_stream(struct dc *dc,
+ 			if (update_type == UPDATE_TYPE_FAST)
+ 				continue;
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 			ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
+ 
+ 			if (dc->hwss.program_triplebuffer != NULL &&
+@@ -2188,7 +2149,6 @@ static void commit_planes_for_stream(struct dc *dc,
+ 				dc->hwss.program_triplebuffer(
+ 					dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
+ 			}
+-#endif
+ 			stream_status =
+ 				stream_get_status(context, pipe_ctx->stream);
+ 
+@@ -2197,7 +2157,6 @@ static void commit_planes_for_stream(struct dc *dc,
+ 					dc, pipe_ctx->stream, stream_status->plane_count, context);
+ 		}
+ 	}
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
+ 		dc->hwss.program_front_end_for_ctx(dc, context);
+ #ifdef CONFIG_DRM_AMD_DC_DCN1_0
+@@ -2216,7 +2175,6 @@ static void commit_planes_for_stream(struct dc *dc,
+ 		}
+ #endif
+ 	}
+-#endif
+ 
+ 	// Update Type FAST, Surface updates
+ 	if (update_type == UPDATE_TYPE_FAST) {
+@@ -2226,7 +2184,6 @@ static void commit_planes_for_stream(struct dc *dc,
+ 		 */
+ 		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 		if (dc->hwss.set_flip_control_gsl)
+ 			for (i = 0; i < surface_count; i++) {
+ 				struct dc_plane_state *plane_state = srf_updates[i].surface;
+@@ -2245,7 +2202,6 @@ static void commit_planes_for_stream(struct dc *dc,
+ 							plane_state->flip_immediate);
+ 				}
+ 			}
+-#endif
+ 		/* Perform requested Updates */
+ 		for (i = 0; i < surface_count; i++) {
+ 			struct dc_plane_state *plane_state = srf_updates[i].surface;
+@@ -2258,7 +2214,6 @@ static void commit_planes_for_stream(struct dc *dc,
+ 
+ 				if (pipe_ctx->plane_state != plane_state)
+ 					continue;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 				/*program triple buffer after lock based on flip type*/
+ 				if (dc->hwss.program_triplebuffer != NULL &&
+ 					!dc->debug.disable_tri_buf) {
+@@ -2266,7 +2221,6 @@ static void commit_planes_for_stream(struct dc *dc,
+ 					dc->hwss.program_triplebuffer(
+ 						dc, pipe_ctx, plane_state->triplebuffer_flips);
+ 				}
+-#endif
+ 				if (srf_updates[i].flip_addr)
+ 					dc->hwss.update_plane_addr(dc, pipe_ctx);
+ 			}
+@@ -2432,12 +2386,10 @@ void dc_set_power_state(
+ 
+ 		dc->hwss.init_hw(dc);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 		if (dc->hwss.init_sys_ctx != NULL &&
+ 			dc->vm_pa_config.valid) {
+ 			dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
+ 		}
+-#endif
+ 
+ 		break;
+ 	default:
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index ec010dc0de8b..f27921e46937 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -1494,9 +1494,7 @@ static enum dc_status enable_link_dp(
+ 	struct dc_link *link = stream->link;
+ 	struct dc_link_settings link_settings = {0};
+ 	enum dp_panel_mode panel_mode;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	bool fec_enable;
+-#endif
+ 	int i;
+ 	bool apply_seamless_boot_optimization = false;
+ 
+@@ -1571,14 +1569,12 @@ static enum dc_status enable_link_dp(
+ 	else
+ 		status = DC_FAIL_DP_LINK_TRAINING;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	if (link->preferred_training_settings.fec_enable != NULL)
+ 		fec_enable = *link->preferred_training_settings.fec_enable;
+ 	else
+ 		fec_enable = true;
+ 
+ 	dp_set_fec_enable(link, fec_enable);
+-#endif
+ 	return status;
+ }
+ 
+@@ -2201,14 +2197,12 @@ static void disable_link(struct dc_link *link, enum signal_type signal)
+ 			dp_disable_link_phy(link, signal);
+ 		else
+ 			dp_disable_link_phy_mst(link, signal);
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 
+ 		if (dc_is_dp_sst_signal(signal) ||
+ 				link->mst_stream_alloc_table.stream_count == 0) {
+ 			dp_set_fec_enable(link, false);
+ 			dp_set_fec_ready(link, false);
+ 		}
+-#endif
+ 	} else {
+ 		if (signal != SIGNAL_TYPE_VIRTUAL)
+ 			link->link_enc->funcs->disable_output(link->link_enc, signal);
+@@ -3015,23 +3009,19 @@ void core_link_enable_stream(
+ 					CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
+ 					COLOR_DEPTH_UNDEFINED);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 		if (pipe_ctx->stream->timing.flags.DSC) {
+ 			if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+ 					dc_is_virtual_signal(pipe_ctx->stream->signal))
+ 				dp_set_dsc_enable(pipe_ctx, true);
+ 		}
+-#endif
+ 		core_dc->hwss.enable_stream(pipe_ctx);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 		/* Set DPS PPS SDP (AKA "info frames") */
+ 		if (pipe_ctx->stream->timing.flags.DSC) {
+ 			if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+ 					dc_is_virtual_signal(pipe_ctx->stream->signal))
+ 				dp_set_dsc_pps_sdp(pipe_ctx, true);
+ 		}
+-#endif
+ 
+ 		if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
+ 			dc_link_allocate_mst_payload(pipe_ctx);
+@@ -3045,14 +3035,12 @@ void core_link_enable_stream(
+ 		update_psp_stream_config(pipe_ctx, false);
+ #endif
+ 	}
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	else { // if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
+ 		if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+ 				dc_is_virtual_signal(pipe_ctx->stream->signal))
+ 			dp_set_dsc_enable(pipe_ctx, true);
+ 
+ 	}
+-#endif
+ }
+ 
+ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+@@ -3101,12 +3089,10 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+ 	core_dc->hwss.disable_stream(pipe_ctx);
+ 
+ 	disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	if (pipe_ctx->stream->timing.flags.DSC) {
+ 		if (dc_is_dp_signal(pipe_ctx->stream->signal))
+ 			dp_set_dsc_enable(pipe_ctx, false);
+ 	}
+-#endif
+ }
+ 
+ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
+@@ -3174,13 +3160,11 @@ uint32_t dc_bandwidth_in_kbps_from_timing(
+ 	uint32_t bits_per_channel = 0;
+ 	uint32_t kbps;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	if (timing->flags.DSC) {
+ 		kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel);
+ 		kbps = kbps / 160 + ((kbps % 160) ? 1 : 0);
+ 		return kbps;
+ 	}
+-#endif
+ 
+ 	switch (timing->display_color_depth) {
+ 	case COLOR_DEPTH_666:
+@@ -3358,7 +3342,6 @@ uint32_t dc_link_bandwidth_kbps(
+ 	link_bw_kbps *= 8;   /* 8 bits per byte*/
+ 	link_bw_kbps *= link_setting->lane_count;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	if (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
+ 		/* Account for FEC overhead.
+ 		 * We have to do it based on caps,
+@@ -3383,7 +3366,6 @@ uint32_t dc_link_bandwidth_kbps(
+ 		link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,
+ 					       link_bw_kbps, 32);
+ 	}
+-#endif
+ 
+ 	return link_bw_kbps;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index a32626864154..272261192e82 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -4,12 +4,8 @@
+ #include "dc_link_dp.h"
+ #include "dm_helpers.h"
+ #include "opp.h"
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dsc.h"
+-#endif
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "resource.h"
+-#endif
+ 
+ #include "inc/core_types.h"
+ #include "link_hwss.h"
+@@ -1365,9 +1361,7 @@ enum link_training_result dc_link_dp_perform_link_training(
+ 	enum link_training_result status = LINK_TRAINING_SUCCESS;
+ 	struct link_training_settings lt_settings;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	bool fec_enable;
+-#endif
+ 	uint8_t repeater_cnt;
+ 	uint8_t repeater_id;
+ 
+@@ -1380,14 +1374,12 @@ enum link_training_result dc_link_dp_perform_link_training(
+ 	/* 1. set link rate, lane count and spread. */
+ 	dpcd_set_link_settings(link, &lt_settings);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	if (link->preferred_training_settings.fec_enable != NULL)
+ 		fec_enable = *link->preferred_training_settings.fec_enable;
+ 	else
+ 		fec_enable = true;
+ 
+ 	dp_set_fec_ready(link, fec_enable);
+-#endif
+ 
+ 	if (!link->is_lttpr_mode_transparent) {
+ 		/* Configure lttpr mode */
+@@ -1529,9 +1521,7 @@ enum link_training_result dc_link_dp_sync_lt_attempt(
+ 	enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
+ 	enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
+ 	enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	bool fec_enable = false;
+-#endif
+ 
+ 	initialize_training_settings(
+ 		link,
+@@ -1551,11 +1541,9 @@ enum link_training_result dc_link_dp_sync_lt_attempt(
+ 	dp_enable_link_phy(link, link->connector_signal,
+ 		dp_cs_id, link_settings);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	/* Set FEC enable */
+ 	fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
+ 	dp_set_fec_ready(link, fec_enable);
+-#endif
+ 
+ 	if (lt_overrides->alternate_scrambler_reset) {
+ 		if (*lt_overrides->alternate_scrambler_reset)
+@@ -1596,9 +1584,7 @@ bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
+ 	 */
+ 	if (link_down == true) {
+ 		dp_disable_link_phy(link, link->connector_signal);
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 		dp_set_fec_ready(link, false);
+-#endif
+ 	}
+ 
+ 	link->sync_lt_in_progress = false;
+@@ -3306,7 +3292,6 @@ static bool retrieve_link_cap(struct dc_link *link)
+ 		dp_hw_fw_revision.ieee_fw_rev,
+ 		sizeof(dp_hw_fw_revision.ieee_fw_rev));
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	memset(&link->dpcd_caps.dsc_caps, '\0',
+ 			sizeof(link->dpcd_caps.dsc_caps));
+ 	memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
+@@ -3328,7 +3313,6 @@ static bool retrieve_link_cap(struct dc_link *link)
+ 				link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
+ 				sizeof(link->dpcd_caps.dsc_caps.dsc_ext_caps.raw));
+ 	}
+-#endif
+ 
+ 	/* Connectivity log: detection */
+ 	CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
+@@ -3458,14 +3442,12 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ 		stream->timing.display_color_depth;
+ 	struct bit_depth_reduction_params params;
+ 	struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	int width = pipe_ctx->stream->timing.h_addressable +
+ 		pipe_ctx->stream->timing.h_border_left +
+ 		pipe_ctx->stream->timing.h_border_right;
+ 	int height = pipe_ctx->stream->timing.v_addressable +
+ 		pipe_ctx->stream->timing.v_border_bottom +
+ 		pipe_ctx->stream->timing.v_border_top;
+-#endif
+ 
+ 	memset(&params, 0, sizeof(params));
+ 
+@@ -3509,7 +3491,6 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ 		if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
+ 			pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
+ 				controller_test_pattern, color_depth);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 		else if (opp->funcs->opp_set_disp_pattern_generator) {
+ 			struct pipe_ctx *odm_pipe;
+ 			enum controller_dp_color_space controller_color_space;
+@@ -3558,7 +3539,6 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ 				width,
+ 				height);
+ 		}
+-#endif
+ 	}
+ 	break;
+ 	case DP_TEST_PATTERN_VIDEO_MODE:
+@@ -3571,7 +3551,6 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ 			pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
+ 				CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
+ 				color_depth);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 		else if (opp->funcs->opp_set_disp_pattern_generator) {
+ 			struct pipe_ctx *odm_pipe;
+ 			int opp_cnt = 1;
+@@ -3600,7 +3579,6 @@ static void set_crtc_test_pattern(struct dc_link *link,
+ 				width,
+ 				height);
+ 		}
+-#endif
+ 	}
+ 	break;
+ 
+@@ -3876,7 +3854,6 @@ enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
+ 	return DP_PANEL_MODE_DEFAULT;
+ }
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ void dp_set_fec_ready(struct dc_link *link, bool ready)
+ {
+ 	/* FEC has to be "set ready" before the link training.
+@@ -3939,5 +3916,4 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)
+ 		}
+ 	}
+ }
+-#endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index 5efbdc1eb173..bb1e8e5b5252 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -12,12 +12,8 @@
+ #include "dc_link_ddc.h"
+ #include "dm_helpers.h"
+ #include "dpcd_defs.h"
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dsc.h"
+-#endif
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "resource.h"
+-#endif
+ 
+ static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
+ {
+@@ -374,7 +370,6 @@ void dp_retrain_link_dp_test(struct dc_link *link,
+ 	}
+ }
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #define DC_LOGGER \
+ 	dsc->ctx->logger
+ static void dsc_optc_config_log(struct display_stream_compressor *dsc,
+@@ -572,5 +567,4 @@ bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx)
+ 	dp_set_dsc_pps_sdp(pipe_ctx, true);
+ 	return true;
+ }
+-#endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 2acfaa9a24cd..081275a430ad 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -46,9 +46,7 @@
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ #include "dcn10/dcn10_resource.h"
+ #endif
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "dcn20/dcn20_resource.h"
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ #include "dcn21/dcn21_resource.h"
+ #endif
+@@ -108,11 +106,9 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
+ 		break;
+ #endif
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	case FAMILY_NV:
+ 		dc_version = DCN_VERSION_2_0;
+ 		break;
+-#endif
+ 	default:
+ 		dc_version = DCE_VERSION_UNKNOWN;
+ 		break;
+@@ -164,18 +160,16 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
+ 	case DCN_VERSION_1_01:
+ 		res_pool = dcn10_create_resource_pool(init_data, dc);
+ 		break;
+-#endif
+ 
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	case DCN_VERSION_2_0:
+ 		res_pool = dcn20_create_resource_pool(init_data, dc);
+ 		break;
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ 	case DCN_VERSION_2_1:
+ 		res_pool = dcn21_create_resource_pool(init_data, dc);
+ 		break;
++#endif
+ #endif
+ 
+ 	default:
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+index ae7cbb6d7847..59eaa5c172a9 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+@@ -105,7 +105,6 @@ static void dc_stream_construct(struct dc_stream_state *stream,
+ 	/* EDID CAP translation for HDMI 2.0 */
+ 	stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));
+ 	stream->timing.dsc_cfg.num_slices_h = 0;
+ 	stream->timing.dsc_cfg.num_slices_v = 0;
+@@ -114,7 +113,6 @@ static void dc_stream_construct(struct dc_stream_state *stream,
+ 	stream->timing.dsc_cfg.linebuf_depth = 9;
+ 	stream->timing.dsc_cfg.version_minor = 2;
+ 	stream->timing.dsc_cfg.ycbcr422_simple = 0;
+-#endif
+ 
+ 	update_stream_signal(stream, dc_sink_data);
+ 
+@@ -364,7 +362,6 @@ bool dc_stream_set_cursor_position(
+ 	return true;
+ }
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool dc_stream_add_writeback(struct dc *dc,
+ 		struct dc_stream_state *stream,
+ 		struct dc_writeback_info *wb_info)
+@@ -477,7 +474,6 @@ bool dc_stream_remove_writeback(struct dc *dc,
+ 
+ 	return true;
+ }
+-#endif
+ 
+ uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
+ {
+@@ -564,7 +560,6 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
+ 	return ret;
+ }
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
+ {
+ 	struct pipe_ctx *pipe = NULL;
+@@ -625,7 +620,6 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc,
+ 
+ 	return true;
+ }
+-#endif
+ 
+ void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)
+ {
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+index d534ac166512..5904c459fe8f 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+@@ -48,7 +48,6 @@ static void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *pl
+ 		plane_state->in_transfer_func->type = TF_TYPE_BYPASS;
+ 		plane_state->in_transfer_func->ctx = ctx;
+ 	}
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	plane_state->in_shaper_func = dc_create_transfer_func();
+ 	if (plane_state->in_shaper_func != NULL) {
+ 		plane_state->in_shaper_func->type = TF_TYPE_BYPASS;
+@@ -65,7 +64,6 @@ static void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *pl
+ 		plane_state->blend_tf->ctx = ctx;
+ 	}
+ 
+-#endif
+ }
+ 
+ static void dc_plane_destruct(struct dc_plane_state *plane_state)
+@@ -78,7 +76,6 @@ static void dc_plane_destruct(struct dc_plane_state *plane_state)
+ 				plane_state->in_transfer_func);
+ 		plane_state->in_transfer_func = NULL;
+ 	}
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	if (plane_state->in_shaper_func != NULL) {
+ 		dc_transfer_func_release(
+ 				plane_state->in_shaper_func);
+@@ -95,7 +92,6 @@ static void dc_plane_destruct(struct dc_plane_state *plane_state)
+ 		plane_state->blend_tf = NULL;
+ 	}
+ 
+-#endif
+ }
+ 
+ /*******************************************************************************
+@@ -260,7 +256,6 @@ struct dc_transfer_func *dc_create_transfer_func(void)
+ 	return NULL;
+ }
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ static void dc_3dlut_func_free(struct kref *kref)
+ {
+ 	struct dc_3dlut *lut = container_of(kref, struct dc_3dlut, refcount);
+@@ -294,6 +289,5 @@ void dc_3dlut_func_retain(struct dc_3dlut *lut)
+ {
+ 	kref_get(&lut->refcount);
+ }
+-#endif
+ 
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index 18fdd61a606b..d710e123b53a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -113,17 +113,13 @@ struct dc_caps {
+ 	bool psp_setup_panel_mode;
+ 	bool extended_aux_timeout_support;
+ 	bool dmcub_support;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	bool hw_3d_lut;
+-#endif
+ 	struct dc_plane_cap planes[MAX_PLANES];
+ };
+ 
+ struct dc_bug_wa {
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	bool no_connect_phy_config;
+ 	bool dedcn20_305_wa;
+-#endif
+ 	bool skip_clock_update;
+ };
+ 
+@@ -364,10 +360,8 @@ struct dc_debug_options {
+ 	bool disable_dfs_bypass;
+ 	bool disable_dpp_power_gate;
+ 	bool disable_hubp_power_gate;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	bool disable_dsc_power_gate;
+ 	int dsc_min_slice_height_override;
+-#endif
+ 	bool native422_support;
+ 	bool disable_pplib_wm_range;
+ 	enum wm_report_mode pplib_wm_report_mode;
+@@ -407,9 +401,7 @@ struct dc_debug_options {
+ 	bool dmcub_emulation;
+ 	bool dmub_command_table; /* for testing only */
+ 	struct dc_bw_validation_profile bw_val_profile;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	bool disable_fec;
+-#endif
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_1
+ 	bool disable_48mhz_pwrdwn;
+ #endif
+@@ -418,9 +410,7 @@ struct dc_debug_options {
+ 	 */
+ 	unsigned int force_min_dcfclk_mhz;
+ 	bool disable_timing_sync;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	bool cm_in_bypass;
+-#endif
+ 	int force_clock_mode;/*every mode change.*/
+ 
+ 	bool nv12_iflip_vm_wa;
+@@ -434,7 +424,6 @@ struct dc_debug_data {
+ 	uint32_t auxErrorCount;
+ };
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ struct dc_phy_addr_space_config {
+ 	struct {
+ 		uint64_t start_addr;
+@@ -464,7 +453,6 @@ struct dc_virtual_addr_space_config {
+ 	uint32_t	page_table_block_size_in_bytes;
+ 	uint8_t		page_table_depth; // 1 = 1 level, 2 = 2 level, etc.  0 = invalid
+ };
+-#endif
+ 
+ struct dc_bounding_box_overrides {
+ 	int sr_exit_time_ns;
+@@ -492,9 +480,7 @@ struct dc {
+ 	struct dc_bounding_box_overrides bb_overrides;
+ 	struct dc_bug_wa work_arounds;
+ 	struct dc_context *ctx;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	struct dc_phy_addr_space_config vm_pa_config;
+-#endif
+ 
+ 	uint8_t link_count;
+ 	struct dc_link *links[MAX_PIPES * 2];
+@@ -532,10 +518,8 @@ struct dc {
+ 	struct dc_debug_data debug_data;
+ 
+ 	const char *build_id;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	struct vm_helper *vm_helper;
+ 	const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
+-#endif
+ };
+ 
+ enum frame_buffer_mode {
+@@ -572,13 +556,11 @@ struct dc_init_data {
+ 
+ 	struct dc_config flags;
+ 	uint32_t log_mask;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	/**
+ 	 * gpu_info FW provided soc bounding box struct or 0 if not
+ 	 * available in FW
+ 	 */
+ 	const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
+-#endif
+ };
+ 
+ struct dc_callback_init {
+@@ -593,11 +575,9 @@ struct dc *dc_create(const struct dc_init_data *init_params);
+ void dc_hardware_init(struct dc *dc);
+ 
+ int dc_get_vmid_use_vector(struct dc *dc);
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
+ /* Returns the number of vmids supported */
+ int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
+-#endif
+ void dc_init_callbacks(struct dc *dc,
+ 		const struct dc_callback_init *init_params);
+ void dc_deinit_callbacks(struct dc *dc);
+@@ -673,7 +653,6 @@ struct dc_transfer_func {
+ 	};
+ };
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 
+ union dc_3dlut_state {
+ 	struct {
+@@ -697,7 +676,6 @@ struct dc_3dlut {
+ 	union dc_3dlut_state state;
+ 	struct dc_context *ctx;
+ };
+-#endif
+ /*
+  * This structure is filled in by dc_surface_get_status and contains
+  * the last requested address and the currently active address so the called
+@@ -748,9 +726,7 @@ union surface_update_flags {
+ struct dc_plane_state {
+ 	struct dc_plane_address address;
+ 	struct dc_plane_flip_time time;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	bool triplebuffer_flips;
+-#endif
+ 	struct scaling_taps scaling_quality;
+ 	struct rect src_rect;
+ 	struct rect dst_rect;
+@@ -773,11 +749,9 @@ struct dc_plane_state {
+ 
+ 	enum dc_color_space color_space;
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	struct dc_3dlut *lut3d_func;
+ 	struct dc_transfer_func *in_shaper_func;
+ 	struct dc_transfer_func *blend_tf;
+-#endif
+ 
+ 	enum surface_pixel_format format;
+ 	enum dc_rotation_angle rotation;
+@@ -845,11 +819,9 @@ struct dc_surface_update {
+ 
+ 	const struct dc_csc_transform *input_csc_color_matrix;
+ 	const struct fixed31_32 *coeff_reduction_factor;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	const struct dc_transfer_func *func_shaper;
+ 	const struct dc_3dlut *lut3d_func;
+ 	const struct dc_transfer_func *blend_tf;
+-#endif
+ };
+ 
+ /*
+@@ -870,11 +842,9 @@ void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
+ void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
+ struct dc_transfer_func *dc_create_transfer_func(void);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dc_3dlut *dc_create_3dlut_func(void);
+ void dc_3dlut_func_release(struct dc_3dlut *lut);
+ void dc_3dlut_func_retain(struct dc_3dlut *lut);
+-#endif
+ /*
+  * This structure holds a surface address.  There could be multiple addresses
+  * in cases such as Stereo 3D, Planar YUV, etc.  Other per-flip attributes such
+@@ -991,10 +961,8 @@ struct dpcd_caps {
+ 	bool panel_mode_edp;
+ 	bool dpcd_display_control_capable;
+ 	bool ext_receiver_cap_field_present;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	union dpcd_fec_capability fec_cap;
+ 	struct dpcd_dsc_capabilities dsc_caps;
+-#endif
+ 	struct dc_lttpr_caps lttpr_caps;
+ 
+ };
+@@ -1017,14 +985,12 @@ struct dc_container_id {
+ };
+ 
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ struct dc_sink_dsc_caps {
+ 	// 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
+ 	// 'false' if they are sink's DSC caps
+ 	bool is_virtual_dpcd_dsc;
+ 	struct dsc_dec_dpcd_caps dsc_dec_caps;
+ };
+-#endif
+ 
+ /*
+  * The sink structure contains EDID and other display device properties
+@@ -1039,9 +1005,7 @@ struct dc_sink {
+ 	struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
+ 	bool converter_disable_audio;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	struct dc_sink_dsc_caps sink_dsc_caps;
+-#endif
+ 
+ 	/* private to DC core */
+ 	struct dc_link *link;
+@@ -1102,10 +1066,8 @@ bool dc_is_dmcu_initialized(struct dc *dc);
+ 
+ enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
+ void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
+-#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
+ /*******************************************************************************
+  * DSC Interfaces
+  ******************************************************************************/
+ #include "dc_dsc.h"
+-#endif
+ #endif /* DC_INTERFACE_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+index 28234d8fdb2c..dfe4472c9e40 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+@@ -129,9 +129,7 @@ struct dc_link_training_overrides {
+ 	bool *alternate_scrambler_reset;
+ 	bool *enhanced_framing;
+ 	bool *mst_enable;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	bool *fec_enable;
+-#endif
+ };
+ 
+ union dpcd_rev {
+@@ -570,7 +568,6 @@ struct dp_audio_test_data {
+ 	uint8_t pattern_period[8];
+ };
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* FEC capability DPCD register field bits-*/
+ union dpcd_fec_capability {
+ 	struct {
+@@ -695,6 +692,5 @@ struct dpcd_dsc_capabilities {
+ 	union dpcd_dsc_ext_capabilities dsc_ext_caps;
+ };
+ 
+-#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */
+ 
+ #endif /* DC_DP_TYPES_H */
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+index 0ed2962add5a..a782ae18a1c5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+@@ -1,4 +1,3 @@
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #ifndef DC_DSC_H_
+ #define DC_DSC_H_
+ /*
+@@ -69,4 +68,3 @@ bool dc_dsc_compute_config(
+ 		const struct dc_crtc_timing *timing,
+ 		struct dc_dsc_config *dsc_cfg);
+ #endif
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+index e0856bb8511f..86043d431d40 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+@@ -167,12 +167,10 @@ enum surface_pixel_format {
+ 	/*swaped & float*/
+ 	SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
+ 	/*grow graphics here if necessary */
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX,
+ 	SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX,
+ 	SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT,
+ 	SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT,
+-#endif
+ 	SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
+ 	SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
+ 		SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
+@@ -180,10 +178,8 @@ enum surface_pixel_format {
+ 	SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr,
+ 	SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb,
+ 		SURFACE_PIXEL_FORMAT_SUBSAMPLE_END,
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010,
+ 	SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102,
+-#endif
+ 	SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888,
+ 	SURFACE_PIXEL_FORMAT_INVALID
+ 
+@@ -222,12 +218,10 @@ enum tile_split_values {
+ 	DC_ROTATED_MICRO_TILING = 0x3,
+ };
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ enum tripleBuffer_enable {
+ 	DC_TRIPLEBUFFER_DISABLE = 0x0,
+ 	DC_TRIPLEBUFFER_ENABLE = 0x1,
+ };
+-#endif
+ 
+ /* TODO: These values come from hardware spec. We need to readdress this
+  * if they ever change.
+@@ -427,13 +421,11 @@ struct dc_csc_transform {
+ 	bool enable_adjustment;
+ };
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ struct dc_rgb_fixed {
+ 	struct fixed31_32 red;
+ 	struct fixed31_32 green;
+ 	struct fixed31_32 blue;
+ };
+-#endif
+ 
+ struct dc_gamma {
+ 	struct kref refcount;
+@@ -468,10 +460,8 @@ enum dc_cursor_color_format {
+ 	CURSOR_MODE_COLOR_1BIT_AND,
+ 	CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
+ 	CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA,
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED,
+ 	CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED
+-#endif
+ };
+ 
+ /*
+@@ -626,10 +616,8 @@ enum dc_color_depth {
+ 	COLOR_DEPTH_121212,
+ 	COLOR_DEPTH_141414,
+ 	COLOR_DEPTH_161616,
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	COLOR_DEPTH_999,
+ 	COLOR_DEPTH_111111,
+-#endif
+ 	COLOR_DEPTH_COUNT
+ };
+ 
+@@ -690,9 +678,7 @@ struct dc_crtc_timing_flags {
+ 	 * rates less than or equal to 340Mcsc */
+ 	uint32_t LTE_340MCSC_SCRAMBLE:1;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	uint32_t DSC : 1; /* Use DSC with this timing */
+-#endif
+ };
+ 
+ enum dc_timing_3d_format {
+@@ -717,7 +703,6 @@ enum dc_timing_3d_format {
+ 	TIMING_3D_FORMAT_MAX,
+ };
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ struct dc_dsc_config {
+ 	uint32_t num_slices_h; /* Number of DSC slices - horizontal */
+ 	uint32_t num_slices_v; /* Number of DSC slices - vertical */
+@@ -728,7 +713,6 @@ struct dc_dsc_config {
+ 	bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */
+ 	int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
+ };
+-#endif
+ struct dc_crtc_timing {
+ 	uint32_t h_total;
+ 	uint32_t h_border_left;
+@@ -755,9 +739,7 @@ struct dc_crtc_timing {
+ 	enum scanning_type scan_type;
+ 
+ 	struct dc_crtc_timing_flags flags;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	struct dc_dsc_config dsc_cfg;
+-#endif
+ };
+ 
+ #ifndef AMD_EDID_UTILITY
+@@ -796,7 +778,6 @@ enum vram_type {
+ 	VIDEO_MEMORY_TYPE_GDDR6  = 6,
+ };
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ enum dwb_cnv_out_bpc {
+ 	DWB_CNV_OUT_BPC_8BPC  = 0,
+ 	DWB_CNV_OUT_BPC_10BPC = 1,
+@@ -847,7 +828,6 @@ struct mcif_buf_params {
+ 	unsigned int		swlock;
+ };
+ 
+-#endif
+ 
+ #define MAX_TG_COLOR_VALUE 0x3FF
+ struct tg_color {
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
+index 03efdc1a7b03..1ff79f703734 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
+@@ -29,13 +29,11 @@
+ #include "dc_types.h"
+ #include "grph_object_defs.h"
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ enum dc_link_fec_state {
+ 	dc_link_fec_not_ready,
+ 	dc_link_fec_ready,
+ 	dc_link_fec_enabled
+ };
+-#endif
+ struct dc_link_status {
+ 	bool link_active;
+ 	struct dpcd_caps *dpcd_caps;
+@@ -142,9 +140,7 @@ struct dc_link {
+ 
+ 	struct link_trace link_trace;
+ 	struct gpio *hpd_gpio;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	enum dc_link_fec_state fec_state;
+-#endif
+ };
+ 
+ const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+index 70274fc43a72..3ea54321b045 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
+@@ -52,7 +52,6 @@ struct freesync_context {
+ 	bool dummy;
+ };
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ enum hubp_dmdata_mode {
+ 	DMDATA_SW_MODE,
+ 	DMDATA_HW_MODE
+@@ -82,9 +81,7 @@ struct dc_dmdata_attributes {
+ 	/* An unbounded array of uint32s, represents software dmdata to be loaded */
+ 	uint32_t *dmdata_sw_data;
+ };
+-#endif
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dc_writeback_info {
+ 	bool wb_enabled;
+ 	int dwb_pipe_inst;
+@@ -96,7 +93,6 @@ struct dc_writeback_update {
+ 	unsigned int num_wb_info;
+ 	struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
+ };
+-#endif
+ 
+ enum vertical_interrupt_ref_point {
+ 	START_V_UPDATE = 0,
+@@ -121,9 +117,7 @@ union stream_update_flags {
+ 		uint32_t abm_level:1;
+ 		uint32_t dpms_off:1;
+ 		uint32_t gamut_remap:1;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 		uint32_t wb_update:1;
+-#endif
+ 	} bits;
+ 
+ 	uint32_t raw;
+@@ -204,11 +198,9 @@ struct dc_stream_state {
+ 
+ 	struct crtc_trigger_info triggered_crtc_reset;
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	/* writeback */
+ 	unsigned int num_wb_info;
+ 	struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
+-#endif
+ 	/* Computed state bits */
+ 	bool mode_changed : 1;
+ 
+@@ -227,9 +219,7 @@ struct dc_stream_state {
+ 	bool apply_seamless_boot_optimization;
+ 
+ 	uint32_t stream_id;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	bool is_dsc_enabled;
+-#endif
+ 	union stream_update_flags update_flags;
+ };
+ 
+@@ -260,12 +250,8 @@ struct dc_stream_update {
+ 
+ 	struct dc_csc_transform *output_csc_transform;
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	struct dc_writeback_update *wb_update;
+-#endif
+-#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
+ 	struct dc_dsc_config *dsc_config;
+-#endif
+ };
+ 
+ bool dc_is_stream_unchanged(
+@@ -355,7 +341,6 @@ bool dc_add_all_planes_for_stream(
+ 		int plane_count,
+ 		struct dc_state *context);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool dc_stream_add_writeback(struct dc *dc,
+ 		struct dc_stream_state *stream,
+ 		struct dc_writeback_info *wb_info);
+@@ -366,7 +351,6 @@ bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
+ bool dc_stream_set_dynamic_metadata(struct dc *dc,
+ 		struct dc_stream_state *stream,
+ 		struct dc_dmdata_attributes *dmdata_attr);
+-#endif
+ 
+ enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
+index 45dfed8bcaf7..1363e8907fbf 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
+@@ -468,7 +468,6 @@ enum display_content_type {
+ 	DISPLAY_CONTENT_TYPE_GAME = 8
+ };
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* writeback */
+ struct dwb_stereo_params {
+ 	bool				stereo_enabled;		/* false: normal mode, true: 3D stereo */
+@@ -499,7 +498,6 @@ struct dc_dwb_params {
+ 	enum dwb_subsample_position	subsample_position;
+ 	struct dc_transfer_func *out_transfer_func;
+ };
+-#endif
+ 
+ /* audio*/
+ 
+@@ -607,9 +605,7 @@ enum dc_infoframe_type {
+ 	DC_HDMI_INFOFRAME_TYPE_AVI = 0x82,
+ 	DC_HDMI_INFOFRAME_TYPE_SPD = 0x83,
+ 	DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84,
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	DC_DP_INFOFRAME_TYPE_PPS = 0x10,
+-#endif
+ };
+ 
+ struct dc_info_packet {
+@@ -788,7 +784,6 @@ struct dc_clock_config {
+ #endif /*AMD_EDID_UTILITY*/
+ //AMD EDID UTILITY does not need any of the above structures
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* DSC DPCD capabilities */
+ union dsc_slice_caps1 {
+ 	struct {
+@@ -858,6 +853,5 @@ struct dsc_dec_dpcd_caps {
+ 	uint32_t branch_overall_throughput_1_mps; /* In MPs */
+ 	uint32_t branch_max_line_width;
+ };
+-#endif
+ 
+ #endif /* DC_TYPES_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+index 7ba7e6f722f6..ba0caaffa24b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+@@ -67,7 +67,6 @@
+ 	SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
+ 	NBIO_SR(BIOS_SCRATCH_2)
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define ABM_DCN20_REG_LIST() \
+ 	ABM_COMMON_REG_LIST_DCE_BASE(), \
+ 	SR(DC_ABM1_HG_SAMPLE_RATE), \
+@@ -81,7 +80,6 @@
+ 	SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
+ 	SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
+ 	NBIO_SR(BIOS_SCRATCH_2)
+-#endif
+ 
+ #define ABM_SF(reg_name, field_name, post_fix)\
+ 	.field_name = reg_name ## __ ## field_name ## post_fix
+@@ -163,9 +161,7 @@
+ 	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
+ 			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
+-#endif
+ 
+ #define ABM_REG_FIELD_LIST(type) \
+ 	type ABM1_HG_NUM_OF_BINS_SEL; \
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+index 2e2e925a506b..382465862f29 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+@@ -30,7 +30,6 @@
+ #include "inc/hw/aux_engine.h"
+ 
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ #define AUX_COMMON_REG_LIST0(id)\
+ 	SRI(AUX_CONTROL, DP_AUX, id), \
+ 	SRI(AUX_ARB_CONTROL, DP_AUX, id), \
+@@ -39,7 +38,6 @@
+ 	SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
+ 	SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id), \
+ 	SRI(AUX_SW_STATUS, DP_AUX, id)
+-#endif
+ 
+ #define AUX_COMMON_REG_LIST(id)\
+ 	SRI(AUX_CONTROL, DP_AUX, id), \
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+index accae1089b83..24ad0b4dddb6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+@@ -1002,7 +1002,6 @@ static bool get_pixel_clk_frequency_100hz(
+ 	return false;
+ }
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 
+ /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
+ struct pixel_rate_range_table_entry {
+@@ -1062,7 +1061,6 @@ static const struct clock_source_funcs dcn20_clk_src_funcs = {
+ 	.get_pix_clk_dividers = dce112_get_pix_clk_dividers,
+ 	.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
+ };
+-#endif
+ 
+ /*****************************************/
+ /* Constructor                           */
+@@ -1433,7 +1431,6 @@ bool dce112_clk_src_construct(
+ 	return true;
+ }
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool dcn20_clk_src_construct(
+ 	struct dce110_clk_src *clk_src,
+ 	struct dc_context *ctx,
+@@ -1449,4 +1446,3 @@ bool dcn20_clk_src_construct(
+ 
+ 	return ret;
+ }
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+index 43c1bf60b83c..5b4a29ee1696 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+@@ -55,7 +55,6 @@
+ 	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
+ 	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define CS_COMMON_REG_LIST_DCN2_0(index, pllid) \
+ 		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
+ 		SRII(PHASE, DP_DTO, 0),\
+@@ -76,7 +75,6 @@
+ 		SRII(PIXEL_RATE_CNTL, OTG, 3),\
+ 		SRII(PIXEL_RATE_CNTL, OTG, 4),\
+ 		SRII(PIXEL_RATE_CNTL, OTG, 5)
+-#endif
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ #define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \
+@@ -95,13 +93,11 @@
+ 		SRII(PIXEL_RATE_CNTL, OTG, 3)
+ #endif
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
+ 	CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
+ 	CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
+ 	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
+ 	CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
+-#endif
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ 
+@@ -201,7 +197,6 @@ bool dce112_clk_src_construct(
+ 	const struct dce110_clk_src_shift *cs_shift,
+ 	const struct dce110_clk_src_mask *cs_mask);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool dcn20_clk_src_construct(
+ 	struct dce110_clk_src *clk_src,
+ 	struct dc_context *ctx,
+@@ -210,6 +205,5 @@ bool dcn20_clk_src_construct(
+ 	const struct dce110_clk_src_regs *regs,
+ 	const struct dce110_clk_src_shift *cs_shift,
+ 	const struct dce110_clk_src_mask *cs_mask);
+-#endif
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+index da9a07edcb06..6e23a82afe8b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+@@ -745,9 +745,7 @@ static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu)
+ 	return true;
+ }
+ 
+-#endif //(CONFIG_DRM_AMD_DC_DCN1_0)
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 
+ static bool dcn20_lock_phy(struct dmcu *dmcu)
+ {
+@@ -795,7 +793,7 @@ static bool dcn20_unlock_phy(struct dmcu *dmcu)
+ 	return true;
+ }
+ 
+-#endif //(CONFIG_DRM_AMD_DC_DCN2_0)
++#endif //(CONFIG_DRM_AMD_DC_DCN1_0)
+ 
+ static const struct dmcu_funcs dce_funcs = {
+ 	.dmcu_init = dce_dmcu_init,
+@@ -819,9 +817,7 @@ static const struct dmcu_funcs dcn10_funcs = {
+ 	.get_psr_wait_loop = dcn10_get_psr_wait_loop,
+ 	.is_dmcu_initialized = dcn10_is_dmcu_initialized
+ };
+-#endif
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ static const struct dmcu_funcs dcn20_funcs = {
+ 	.dmcu_init = dcn10_dmcu_init,
+ 	.load_iram = dcn10_dmcu_load_iram,
+@@ -834,7 +830,6 @@ static const struct dmcu_funcs dcn20_funcs = {
+ 	.lock_phy = dcn20_lock_phy,
+ 	.unlock_phy = dcn20_unlock_phy
+ };
+-#endif
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ static const struct dmcu_funcs dcn21_funcs = {
+@@ -850,6 +845,7 @@ static const struct dmcu_funcs dcn21_funcs = {
+ 	.unlock_phy = dcn20_unlock_phy
+ };
+ #endif
++#endif
+ 
+ static void dce_dmcu_construct(
+ 	struct dce_dmcu *dmcu_dce,
+@@ -869,7 +865,7 @@ static void dce_dmcu_construct(
+ 	dmcu_dce->dmcu_mask = dmcu_mask;
+ }
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
++#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ static void dcn21_dmcu_construct(
+ 		struct dce_dmcu *dmcu_dce,
+ 		struct dc_context *ctx,
+@@ -931,9 +927,7 @@ struct dmcu *dcn10_dmcu_create(
+ 
+ 	return &dmcu_dce->base;
+ }
+-#endif
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dmcu *dcn20_dmcu_create(
+ 	struct dc_context *ctx,
+ 	const struct dce_dmcu_registers *regs,
+@@ -954,7 +948,6 @@ struct dmcu *dcn20_dmcu_create(
+ 
+ 	return &dmcu_dce->base;
+ }
+-#endif
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ struct dmcu *dcn21_dmcu_create(
+@@ -978,6 +971,7 @@ struct dmcu *dcn21_dmcu_create(
+ 	return &dmcu_dce->base;
+ }
+ #endif
++#endif
+ 
+ void dce_dmcu_destroy(struct dmcu **dmcu)
+ {
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+index 1a42b2cbb21b..89277899b507 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+@@ -266,13 +266,11 @@ struct dmcu *dcn10_dmcu_create(
+ 	const struct dce_dmcu_shift *dmcu_shift,
+ 	const struct dce_dmcu_mask *dmcu_mask);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dmcu *dcn20_dmcu_create(
+ 	struct dc_context *ctx,
+ 	const struct dce_dmcu_registers *regs,
+ 	const struct dce_dmcu_shift *dmcu_shift,
+ 	const struct dce_dmcu_mask *dmcu_mask);
+-#endif
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ struct dmcu *dcn21_dmcu_create(
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+index a0d1c3b811a9..7e3dde764111 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+@@ -210,7 +210,6 @@
+ 	SR(DC_IP_REQUEST_CNTL), \
+ 	BL_REG_LIST()
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define HWSEQ_DCN2_REG_LIST()\
+ 	HWSEQ_DCN_REG_LIST(), \
+ 	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
+@@ -276,7 +275,6 @@
+ 	SR(D6VGA_CONTROL), \
+ 	SR(DC_IP_REQUEST_CNTL), \
+ 	BL_REG_LIST()
+-#endif
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ #define HWSEQ_DCN21_REG_LIST()\
+@@ -577,7 +575,6 @@ struct dce_hwseq_registers {
+ 	HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
+ 	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\
+ 	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
+ 	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+@@ -637,7 +634,6 @@ struct dce_hwseq_registers {
+ 	HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \
+ 	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+ 	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
+-#endif
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ #define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+index 0495a1b5dd74..f4c1ce4f4e6a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+@@ -293,9 +293,7 @@ static bool setup_engine(
+ 	struct dce_i2c_hw *dce_i2c_hw)
+ {
+ 	uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	uint32_t  reset_length = 0;
+-#endif
+ 	/* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/
+ 	REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
+ 
+@@ -319,14 +317,12 @@ static bool setup_engine(
+ 		REG_UPDATE_N(SETUP, 2,
+ 			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit,
+ 			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	} else {
+ 		reset_length = dce_i2c_hw->send_reset_length;
+ 		REG_UPDATE_N(SETUP, 3,
+ 			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit,
+ 			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH), reset_length,
+ 			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1);
+-#endif
+ 	}
+ 	/* Program HW priority
+ 	 * set to High - interrupt software I2C at any time
+@@ -702,7 +698,6 @@ void dcn1_i2c_hw_construct(
+ 	dce_i2c_hw->setup_limit = I2C_SETUP_TIME_LIMIT_DCN;
+ }
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void dcn2_i2c_hw_construct(
+ 	struct dce_i2c_hw *dce_i2c_hw,
+ 	struct dc_context *ctx,
+@@ -721,4 +716,3 @@ void dcn2_i2c_hw_construct(
+ 	if (ctx->dc->debug.scl_reset_length10)
+ 		dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_10;
+ }
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
+index cb0234e5d597..d4b2037f7d74 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
+@@ -177,9 +177,7 @@ struct dce_i2c_shift {
+ 	uint8_t DC_I2C_INDEX;
+ 	uint8_t DC_I2C_INDEX_WRITE;
+ 	uint8_t XTAL_REF_DIV;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH;
+-#endif
+ 	uint8_t DC_I2C_REG_RW_CNTL_STATUS;
+ };
+ 
+@@ -220,17 +218,13 @@ struct dce_i2c_mask {
+ 	uint32_t DC_I2C_INDEX;
+ 	uint32_t DC_I2C_INDEX_WRITE;
+ 	uint32_t XTAL_REF_DIV;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH;
+-#endif
+ 	uint32_t DC_I2C_REG_RW_CNTL_STATUS;
+ };
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh)\
+ 	I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh),\
+ 	I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH, mask_sh)
+-#endif
+ 
+ struct dce_i2c_registers {
+ 	uint32_t SETUP;
+@@ -312,7 +306,6 @@ void dcn1_i2c_hw_construct(
+ 	const struct dce_i2c_shift *shifts,
+ 	const struct dce_i2c_mask *masks);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void dcn2_i2c_hw_construct(
+ 	struct dce_i2c_hw *dce_i2c_hw,
+ 	struct dc_context *ctx,
+@@ -320,7 +313,6 @@ void dcn2_i2c_hw_construct(
+ 	const struct dce_i2c_registers *regs,
+ 	const struct dce_i2c_shift *shifts,
+ 	const struct dce_i2c_mask *masks);
+-#endif
+ 
+ bool dce_i2c_submit_command_hw(
+ 	struct resource_pool *pool,
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 050634926263..01fefe19ee92 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -1319,9 +1319,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	struct drr_params params = {0};
+ 	unsigned int event_triggers = 0;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
+-#endif
+ 
+ 	if (dc->hwss.disable_stream_gating) {
+ 		dc->hwss.disable_stream_gating(dc, pipe_ctx);
+@@ -1387,7 +1385,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ 		pipe_ctx->stream_res.opp,
+ 		&stream->bit_depth_params,
+ 		&stream->clamping);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	while (odm_pipe) {
+ 		odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
+ 				odm_pipe->stream_res.opp,
+@@ -1401,7 +1398,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ 				&stream->clamping);
+ 		odm_pipe = odm_pipe->next_odm_pipe;
+ 	}
+-#endif
+ 
+ 	if (!stream->dpms_off)
+ 		core_link_enable_stream(context, pipe_ctx);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+index 997e9582edc7..0e682b5aa3eb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+@@ -290,12 +290,8 @@ void dpp1_cnv_setup (
+ 		enum surface_pixel_format format,
+ 		enum expansion_mode mode,
+ 		struct dc_csc_transform input_csc_color_matrix,
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 		enum dc_color_space input_color_space,
+ 		struct cnv_alpha_2bit_lut *alpha_2bit_lut)
+-#else
+-		enum dc_color_space input_color_space)
+-#endif
+ {
+ 	uint32_t pixel_format;
+ 	uint32_t alpha_en;
+@@ -542,11 +538,9 @@ static const struct dpp_funcs dcn10_dpp_funcs = {
+ 		.set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
+ 		.dpp_dppclk_control = dpp1_dppclk_control,
+ 		.dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier,
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 		.dpp_program_blnd_lut = NULL,
+ 		.dpp_program_shaper_lut = NULL,
+ 		.dpp_program_3dlut = NULL
+-#endif
+ };
+ 
+ static struct dpp_caps dcn10_dpp_cap = {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+index 1d4a7d640334..2edf566b3a72 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+@@ -1486,12 +1486,8 @@ void dpp1_cnv_setup (
+ 		enum surface_pixel_format format,
+ 		enum expansion_mode mode,
+ 		struct dc_csc_transform input_csc_color_matrix,
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 		enum dc_color_space input_color_space,
+ 		struct cnv_alpha_2bit_lut *alpha_2bit_lut);
+-#else
+-		enum dc_color_space input_color_space);
+-#endif
+ 
+ void dpp1_full_bypass(struct dpp *dpp_base);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+index 6f1a312c6a5a..6b7593dd0c77 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+@@ -736,10 +736,8 @@ void dpp1_full_bypass(struct dpp *dpp_base)
+ 	/* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */
+ 	if (dpp->tf_mask->CM_BYPASS_EN)
+ 		REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	else
+ 		REG_SET(CM_CONTROL, 0, CM_BYPASS, 1);
+-#endif
+ 
+ 	/* Setting degamma bypass for now */
+ 	REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
+index d67e0abeee93..fce37c527a0b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
+@@ -218,14 +218,12 @@ static void dpp1_dscl_set_lb(
+ 			INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */
+ 			LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */
+ 	}
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	else {
+ 		/* DSCL caps: pixel data processed in float format */
+ 		REG_SET_2(LB_DATA_FORMAT, 0,
+ 			INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */
+ 			LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */
+ 	}
+-#endif
+ 
+ 	REG_SET_2(LB_MEMORY_CTRL, 0,
+ 		MEMORY_CONFIG, mem_size_config,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
+index 374cc9acda3b..64b31edc8cf6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
+@@ -109,9 +109,7 @@ const struct dwbc_funcs dcn10_dwbc_funcs = {
+ 	.update				= NULL,
+ 	.set_stereo			= NULL,
+ 	.set_new_content		= NULL,
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	.set_warmup			= NULL,
+-#endif
+ 	.dwb_set_scaler			= NULL,
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+index 5aeee938605a..31b64733d693 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+@@ -306,7 +306,6 @@ void hubp1_program_pixel_format(
+ 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ 				SURFACE_PIXEL_FORMAT, 12);
+ 		break;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
+ 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ 				SURFACE_PIXEL_FORMAT, 112);
+@@ -327,7 +326,6 @@ void hubp1_program_pixel_format(
+ 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ 				SURFACE_PIXEL_FORMAT, 119);
+ 		break;
+-#endif
+ 	default:
+ 		BREAK_TO_DEBUGGER();
+ 		break;
+@@ -1251,10 +1249,8 @@ static const struct hubp_funcs dcn10_hubp_funcs = {
+ 	.hubp_get_underflow_status = hubp1_get_underflow_status,
+ 	.hubp_init = hubp1_init,
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	.dmdata_set_attributes = NULL,
+ 	.dmdata_load = NULL,
+-#endif
+ };
+ 
+ /*****************************************/
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+index e65e76f018e4..780af5b3c16f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+@@ -729,13 +729,11 @@ void hubp1_dcc_control(struct hubp *hubp,
+ 		bool enable,
+ 		enum hubp_ind_block_size independent_64b_blks);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ bool hubp1_program_surface_flip_and_addr(
+ 	struct hubp *hubp,
+ 	const struct dc_plane_address *address,
+ 	bool flip_immediate);
+ 
+-#endif
+ bool hubp1_is_flip_pending(struct hubp *hubp);
+ 
+ void hubp1_cursor_set_attributes(
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index c8bd1c0cdb45..df59bd9185b5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -48,9 +48,7 @@
+ #include "clk_mgr.h"
+ 
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dsc.h"
+-#endif
+ 
+ #define DC_LOGGER_INIT(logger)
+ 
+@@ -314,7 +312,6 @@ void dcn10_log_hw_state(struct dc *dc,
+ 		/* Read shared OTG state registers for all DCNx */
+ 		optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 		/*
+ 		 * For DCN2 and greater, a register on the OPP is used to
+ 		 * determine if the CRTC is blanked instead of the OTG. So use
+@@ -326,9 +323,6 @@ void dcn10_log_hw_state(struct dc *dc,
+ 			s.blank_enabled = pool->opps[i]->funcs->dpg_is_blanked(pool->opps[i]);
+ 		else
+ 			s.blank_enabled = tg->funcs->is_blanked(tg);
+-#else
+-		s.blank_enabled = tg->funcs->is_blanked(tg);
+-#endif
+ 
+ 		//only print if OTG master is enabled
+ 		if ((s.otg_enabled & 1) == 0)
+@@ -363,7 +357,6 @@ void dcn10_log_hw_state(struct dc *dc,
+ 	}
+ 	DTN_INFO("\n");
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	DTN_INFO("DSC: CLOCK_EN  SLICE_WIDTH  Bytes_pp\n");
+ 	for (i = 0; i < pool->res_cap->num_dsc; i++) {
+ 		struct display_stream_compressor *dsc = pool->dscs[i];
+@@ -418,7 +411,6 @@ void dcn10_log_hw_state(struct dc *dc,
+ 		}
+ 	}
+ 	DTN_INFO("\n");
+-#endif
+ 
+ 	DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d  dcfclk_deep_sleep_khz:%d  dispclk_khz:%d\n"
+ 		"dppclk_khz:%d  max_supported_dppclk_khz:%d  fclk_khz:%d  socclk_khz:%d\n\n",
+@@ -1272,11 +1264,9 @@ static void dcn10_init_hw(struct dc *dc)
+ 	}
+ 
+ 	/* Power gate DSCs */
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
+ 		if (dc->hwss.dsc_pg_control != NULL)
+ 			dc->hwss.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
+-#endif
+ 
+ 	/* If taking control over from VBIOS, we may want to optimize our first
+ 	 * mode set, so we need to skip powering down pipes until we know which
+@@ -2188,12 +2178,8 @@ static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
+ 			plane_state->format,
+ 			EXPANSION_MODE_ZERO,
+ 			plane_state->input_csc_color_matrix,
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 			plane_state->color_space,
+ 			NULL);
+-#else
+-			plane_state->color_space);
+-#endif
+ 
+ 	//set scale and bias registers
+ 	dcn10_build_prescale_params(&bns_params, plane_state);
+@@ -2651,11 +2637,9 @@ static void dcn10_apply_ctx_for_surface(
+ 	if (num_planes > 0)
+ 		program_all_pipe_in_tree(dc, top_pipe_to_program, context);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	/* Program secondary blending tree and writeback pipes */
+ 	if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree))
+ 		dc->hwss.program_all_writeback_pipes_in_tree(dc, stream, context);
+-#endif
+ 	if (interdependent_update)
+ 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ 			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
+index 1580f9c6d27d..24b68337d76e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
+@@ -51,11 +51,9 @@ static const struct ipp_funcs dcn10_ipp_funcs = {
+ 	.ipp_destroy			= dcn10_ipp_destroy
+ };
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ static const struct ipp_funcs dcn20_ipp_funcs = {
+ 	.ipp_destroy			= dcn10_ipp_destroy
+ };
+-#endif
+ 
+ void dcn10_ipp_construct(
+ 	struct dcn10_ipp *ippn10,
+@@ -74,7 +72,6 @@ void dcn10_ipp_construct(
+ 	ippn10->ipp_mask = ipp_mask;
+ }
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void dcn20_ipp_construct(
+ 	struct dcn10_ipp *ippn10,
+ 	struct dc_context *ctx,
+@@ -91,4 +88,3 @@ void dcn20_ipp_construct(
+ 	ippn10->ipp_shift = ipp_shift;
+ 	ippn10->ipp_mask = ipp_mask;
+ }
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
+index cfa24459242b..f0e0d07b0311 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
+@@ -49,7 +49,6 @@
+ 	SRI(CURSOR_HOT_SPOT, CURSOR, id), \
+ 	SRI(CURSOR_DST_OFFSET, CURSOR, id)
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define IPP_REG_LIST_DCN20(id) \
+ 	IPP_REG_LIST_DCN(id), \
+ 	SRI(CURSOR_SETTINGS, HUBPREQ, id), \
+@@ -60,7 +59,6 @@
+ 	SRI(CURSOR_POSITION, CURSOR0_, id), \
+ 	SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \
+ 	SRI(CURSOR_DST_OFFSET, CURSOR0_, id)
+-#endif
+ 
+ #define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT	0x4
+ #define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK		0x00000010L
+@@ -105,7 +103,6 @@
+ 	IPP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
+ 	IPP_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh)
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define IPP_MASK_SH_LIST_DCN20(mask_sh) \
+ 	IPP_MASK_SH_LIST_DCN(mask_sh), \
+ 	IPP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
+@@ -124,7 +121,6 @@
+ 	IPP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
+ 	IPP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
+ 	IPP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
+-#endif
+ 
+ #define IPP_DCN10_REG_FIELD_LIST(type) \
+ 	type CNVC_SURFACE_PIXEL_FORMAT; \
+@@ -196,13 +192,11 @@ void dcn10_ipp_construct(struct dcn10_ipp *ippn10,
+ 	const struct dcn10_ipp_shift *ipp_shift,
+ 	const struct dcn10_ipp_mask *ipp_mask);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ void dcn20_ipp_construct(struct dcn10_ipp *ippn10,
+ 	struct dc_context *ctx,
+ 	int inst,
+ 	const struct dcn10_ipp_registers *regs,
+ 	const struct dcn10_ipp_shift *ipp_shift,
+ 	const struct dcn10_ipp_mask *ipp_mask);
+-#endif
+ 
+ #endif /* _DCN10_IPP_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+index 88fcc395adf5..7493a630f4dc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+@@ -72,9 +72,7 @@
+ struct dcn10_link_enc_aux_registers {
+ 	uint32_t AUX_CONTROL;
+ 	uint32_t AUX_DPHY_RX_CONTROL0;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	uint32_t AUX_DPHY_TX_CONTROL;
+-#endif
+ };
+ 
+ struct dcn10_link_enc_hpd_registers {
+@@ -106,7 +104,6 @@ struct dcn10_link_enc_registers {
+ 	uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
+ 	uint32_t DP_SEC_CNTL1;
+ 	uint32_t TMDS_CTL_BITS;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	/* DCCG  */
+ 	uint32_t CLOCK_ENABLE;
+ 	/* DIG */
+@@ -136,7 +133,6 @@ struct dcn10_link_enc_registers {
+ 	uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3;
+ 	uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2;
+ 	uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3;
+-#endif
+ };
+ 
+ #define LE_SF(reg_name, field_name, post_fix)\
+@@ -242,7 +238,6 @@ struct dcn10_link_enc_registers {
+ 	type AUX_LS_READ_EN;\
+ 	type AUX_RX_RECEIVE_WINDOW
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 
+ #define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \
+ 		type RDPCS_PHY_DP_TX0_DATA_EN;\
+@@ -423,20 +418,15 @@ struct dcn10_link_enc_registers {
+ 	type AUX_TX_PRECHARGE_SYMBOLS; \
+ 	type AUX_MODE_DET_CHECK_DELAY;\
+ 	type DPCS_DBG_CBUS_DIS
+-#endif
+ 
+ struct dcn10_link_enc_shift {
+ 	DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
+-#endif
+ };
+ 
+ struct dcn10_link_enc_mask {
+ 	DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
+-#endif
+ };
+ 
+ struct dcn10_link_encoder {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+index b3f66e1de15d..04f863499cfb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+@@ -464,12 +464,10 @@ static const struct mpc_funcs dcn10_mpc_funcs = {
+ 	.assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect,
+ 	.init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
+ 	.update_blending = mpc1_update_blending,
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	.set_denorm = NULL,
+ 	.set_denorm_clamp = NULL,
+ 	.set_output_csc = NULL,
+ 	.set_output_gamma = NULL,
+-#endif
+ };
+ 
+ void dcn10_mpc_construct(struct dcn10_mpc *mpc10,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+index 8249b4429186..f2368be8e06d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+@@ -371,11 +371,9 @@ void opp1_program_oppbuf(
+ 	 */
+ 	REG_UPDATE(OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, oppbuf->pixel_repetition);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	/* Controls the number of padded pixels at the end of a segment */
+ 	if (REG(OPPBUF_CONTROL1))
+ 		REG_UPDATE(OPPBUF_CONTROL1, OPPBUF_NUM_SEGMENT_PADDED_PIXELS, oppbuf->num_segment_padded_pixels);
+-#endif
+ }
+ 
+ void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable)
+@@ -402,10 +400,8 @@ static const struct opp_funcs dcn10_opp_funcs = {
+ 		.opp_program_bit_depth_reduction = opp1_program_bit_depth_reduction,
+ 		.opp_program_stereo = opp1_program_stereo,
+ 		.opp_pipe_clock_control = opp1_pipe_clock_control,
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 		.opp_set_disp_pattern_generator = NULL,
+ 		.dpg_is_blanked = NULL,
+-#endif
+ 		.opp_destroy = opp1_destroy
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+index 30c025918568..cd7412dc42d1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+@@ -1502,7 +1502,6 @@ void dcn10_timing_generator_init(struct optc *optc1)
+ 	optc1->min_v_sync_width = 1;
+ }
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this:
+  *
+  * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as
+@@ -1515,15 +1514,12 @@ void dcn10_timing_generator_init(struct optc *optc1)
+  *   to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well.
+  *
+  */
+-#endif
+ bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
+ {
+ 	bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
+ 			&& !timing->dsc_cfg.ycbcr422_simple);
+-#endif
+ 	return two_pix;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+index 4476bc8cdb4d..3afeb1a30f21 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+@@ -165,13 +165,11 @@ struct dcn_optc_registers {
+ 	uint32_t OTG_CRC0_WINDOWB_X_CONTROL;
+ 	uint32_t OTG_CRC0_WINDOWB_Y_CONTROL;
+ 	uint32_t GSL_SOURCE_SELECT;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	uint32_t DWB_SOURCE_SELECT;
+ 	uint32_t OTG_DSC_START_POSITION;
+ 	uint32_t OPTC_DATA_FORMAT_CONTROL;
+ 	uint32_t OPTC_BYTES_PER_PIXEL;
+ 	uint32_t OPTC_WIDTH_CONTROL;
+-#endif
+ };
+ 
+ #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
+@@ -456,7 +454,6 @@ struct dcn_optc_registers {
+ 	type MANUAL_FLOW_CONTROL;\
+ 	type MANUAL_FLOW_CONTROL_SEL;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 
+ #define TG_REG_FIELD_LIST(type) \
+ 	TG_REG_FIELD_LIST_DCN1_0(type)\
+@@ -479,12 +476,6 @@ struct dcn_optc_registers {
+ 	type OPTC_DWB0_SOURCE_SELECT;\
+ 	type OPTC_DWB1_SOURCE_SELECT;
+ 
+-#else
+-
+-#define TG_REG_FIELD_LIST(type) \
+-	TG_REG_FIELD_LIST_DCN1_0(type)
+-
+-#endif
+ 
+ 
+ struct dcn_optc_shift {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+index 2f00f2389e40..f9b9e221c698 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+@@ -163,14 +163,12 @@ struct dcn10_stream_enc_registers {
+ 	uint32_t DP_MSA_TIMING_PARAM3;
+ 	uint32_t DP_MSA_TIMING_PARAM4;
+ 	uint32_t HDMI_DB_CONTROL;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	uint32_t DP_DSC_CNTL;
+ 	uint32_t DP_DSC_BYTES_PER_PIXEL;
+ 	uint32_t DME_CONTROL;
+ 	uint32_t DP_SEC_METADATA_TRANSMISSION;
+ 	uint32_t HDMI_METADATA_PACKET_CONTROL;
+ 	uint32_t DP_SEC_FRAMING4;
+-#endif
+ 	uint32_t DIG_CLOCK_PATTERN;
+ };
+ 
+@@ -466,7 +464,6 @@ struct dcn10_stream_enc_registers {
+ 	type DIG_SOURCE_SELECT;\
+ 	type DIG_CLOCK_PATTERN
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define SE_REG_FIELD_LIST_DCN2_0(type) \
+ 	type DP_DSC_MODE;\
+ 	type DP_DSC_SLICE_WIDTH;\
+@@ -485,20 +482,15 @@ struct dcn10_stream_enc_registers {
+ 	type DOLBY_VISION_EN;\
+ 	type DP_PIXEL_COMBINE;\
+ 	type DP_SST_SDP_SPLITTING
+-#endif
+ 
+ struct dcn10_stream_encoder_shift {
+ 	SE_REG_FIELD_LIST_DCN1_0(uint8_t);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	SE_REG_FIELD_LIST_DCN2_0(uint8_t);
+-#endif
+ };
+ 
+ struct dcn10_stream_encoder_mask {
+ 	SE_REG_FIELD_LIST_DCN1_0(uint32_t);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	SE_REG_FIELD_LIST_DCN2_0(uint32_t);
+-#endif
+ };
+ 
+ struct dcn10_stream_encoder {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+index be3a614963c6..89c581196c4c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+@@ -6,9 +6,7 @@ DCN20 = dcn20_resource.o dcn20_hwseq.o dcn20_dpp.o dcn20_dpp_cm.o dcn20_hubp.o \
+ 		dcn20_stream_encoder.o dcn20_link_encoder.o dcn20_dccg.o \
+ 		dcn20_vmid.o dcn20_dwb.o dcn20_dwb_scl.o
+ 
+-ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ DCN20 += dcn20_dsc.o
+-endif
+ 
+ CFLAGS_dcn20_resource.o := -mhard-float -msse
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+index dc9944427d2f..0111545dac75 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+@@ -23,7 +23,6 @@
+  *
+  */
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "reg_helper.h"
+ #include "dcn20_dsc.h"
+ #include "dsc/dscc_types.h"
+@@ -734,4 +733,3 @@ static void dsc_write_to_registers(struct display_stream_compressor *dsc, const
+ 	}
+ }
+ 
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
+index 4e2fb38390a4..9855a7ed0387 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
+@@ -21,7 +21,6 @@
+  * Authors: AMD
+  *
+  */
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #ifndef __DCN20_DSC_H__
+ #define __DCN20_DSC_H__
+ 
+@@ -572,4 +571,3 @@ void dsc2_construct(struct dcn20_dsc *dsc,
+ 
+ #endif
+ 
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+index 4c60fa4b89e7..2823be75b071 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+@@ -485,7 +485,6 @@ void hubp2_program_pixel_format(
+ 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ 				SURFACE_PIXEL_FORMAT, 12);
+ 		break;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
+ 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ 				SURFACE_PIXEL_FORMAT, 112);
+@@ -506,7 +505,6 @@ void hubp2_program_pixel_format(
+ 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ 				SURFACE_PIXEL_FORMAT, 119);
+ 		break;
+-#endif
+ 	default:
+ 		BREAK_TO_DEBUGGER();
+ 		break;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 92117b6d0012..868099fbe8ba 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -33,9 +33,7 @@
+ #include "dcn10/dcn10_hw_sequencer.h"
+ #include "dcn20_hwseq.h"
+ #include "dce/dce_hwseq.h"
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dcn20/dcn20_dsc.h"
+-#endif
+ #include "abm.h"
+ #include "clk_mgr.h"
+ #include "dmcu.h"
+@@ -245,7 +243,6 @@ void dcn20_init_blank(
+ 	dcn20_hwss_wait_for_blank_complete(opp);
+ }
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ static void dcn20_dsc_pg_control(
+ 		struct dce_hwseq *hws,
+ 		unsigned int dsc_inst,
+@@ -322,7 +319,6 @@ static void dcn20_dsc_pg_control(
+ 	if (org_ip_request_cntl == 0)
+ 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
+ }
+-#endif
+ 
+ static void dcn20_dpp_pg_control(
+ 		struct dce_hwseq *hws,
+@@ -1695,7 +1691,6 @@ bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
+ 
+ static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	struct dce_hwseq *hws = dc->hwseq;
+ 
+ 	if (pipe_ctx->stream_res.dsc) {
+@@ -1707,12 +1702,10 @@ static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx
+ 			odm_pipe = odm_pipe->next_odm_pipe;
+ 		}
+ 	}
+-#endif
+ }
+ 
+ static void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	struct dce_hwseq *hws = dc->hwseq;
+ 
+ 	if (pipe_ctx->stream_res.dsc) {
+@@ -1724,7 +1717,6 @@ static void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 			odm_pipe = odm_pipe->next_odm_pipe;
+ 		}
+ 	}
+-#endif
+ }
+ 
+ void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
+@@ -1923,11 +1915,9 @@ static void dcn20_reset_back_end_for_pipe(
+ 			}
+ 		}
+ 	}
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	else if (pipe_ctx->stream_res.dsc) {
+ 		dp_set_dsc_enable(pipe_ctx, false);
+ 	}
+-#endif
+ 
+ 	/* by upper caller loop, parent pipe: pipe0, will be reset last.
+ 	 * back end share by all pipes and will be disable only when disable
+@@ -2439,11 +2429,7 @@ void dcn20_hw_sequencer_construct(struct dc *dc)
+ 	dc->hwss.enable_power_gating_plane = dcn20_enable_power_gating_plane;
+ 	dc->hwss.dpp_pg_control = dcn20_dpp_pg_control;
+ 	dc->hwss.hubp_pg_control = dcn20_hubp_pg_control;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
+-#else
+-	dc->hwss.dsc_pg_control = NULL;
+-#endif
+ 	dc->hwss.disable_vga = dcn20_disable_vga;
+ 
+ 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
+index 0e0306d84cd8..e4ac73035c84 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
+@@ -168,10 +168,8 @@ static struct mpll_cfg dcn2_mpll_cfg[] = {
+ void enc2_fec_set_enable(struct link_encoder *enc, bool enable)
+ {
+ 	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	DC_LOG_DSC("%s FEC at link encoder inst %d",
+ 			enable ? "Enabling" : "Disabling", enc->id.enum_id);
+-#endif
+ 	REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable);
+ }
+ 
+@@ -192,7 +190,6 @@ bool enc2_fec_is_active(struct link_encoder *enc)
+ 	return (active != 0);
+ }
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* this function reads dsc related register fields to be logged later in dcn10_log_hw_state
+  * into a dcn_dsc_state struct.
+  */
+@@ -205,7 +202,6 @@ void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s)
+ 	REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status);
+ 	REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete);
+ }
+-#endif
+ 
+ static bool update_cfg_data(
+ 		struct dcn10_link_encoder *enc10,
+@@ -316,9 +312,7 @@ void enc2_hw_init(struct link_encoder *enc)
+ }
+ 
+ static const struct link_encoder_funcs dcn20_link_enc_funcs = {
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	.read_state = link_enc2_read_state,
+-#endif
+ 	.validate_output_with_stream =
+ 		dcn10_link_encoder_validate_output_with_stream,
+ 	.hw_init = enc2_hw_init,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
+index 0c98a0bbbd14..62dfd34c69f1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
+@@ -158,9 +158,7 @@ void enc2_fec_set_ready(struct link_encoder *enc, bool ready);
+ bool enc2_fec_is_active(struct link_encoder *enc);
+ void enc2_hw_init(struct link_encoder *enc);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s);
+-#endif
+ 
+ void dcn20_link_encoder_enable_dp_output(
+ 	struct link_encoder *enc,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+index 3b613fb93ef8..0e50dc9b611a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+@@ -167,7 +167,6 @@ void optc2_set_gsl_source_select(
+ 	}
+ }
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* DSC encoder frame start controls: x = h position, line_num = # of lines from vstartup */
+ void optc2_set_dsc_encoder_frame_start(struct timing_generator *optc,
+ 					int x_position,
+@@ -201,7 +200,6 @@ void optc2_set_dsc_config(struct timing_generator *optc,
+ 	REG_UPDATE(OPTC_WIDTH_CONTROL,
+ 		OPTC_DSC_SLICE_WIDTH, dsc_slice_width);
+ }
+-#endif
+ 
+ /**
+  * PTI i think is already done somewhere else for 2ka
+@@ -448,9 +446,7 @@ static struct timing_generator_funcs dcn20_tg_funcs = {
+ 		.setup_global_swap_lock = NULL,
+ 		.get_crc = optc1_get_crc,
+ 		.configure_crc = optc1_configure_crc,
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 		.set_dsc_config = optc2_set_dsc_config,
+-#endif
+ 		.set_dwb_source = optc2_set_dwb_source,
+ 		.set_odm_bypass = optc2_set_odm_bypass,
+ 		.set_odm_combine = optc2_set_odm_combine,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+index 32a58431fd09..9ae22146d2d8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+@@ -86,12 +86,10 @@ void optc2_set_gsl_source_select(struct timing_generator *optc,
+ 		int group_idx,
+ 		uint32_t gsl_ready_signal);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ void optc2_set_dsc_config(struct timing_generator *optc,
+ 					enum optc_dsc_mode dsc_mode,
+ 					uint32_t dsc_bytes_per_pixel,
+ 					uint32_t dsc_slice_width);
+-#endif
+ 
+ void optc2_set_odm_bypass(struct timing_generator *optc,
+ 		const struct dc_crtc_timing *dc_crtc_timing);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 3119714586dd..9f721d5bea3b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -43,9 +43,7 @@
+ #include "dcn10/dcn10_resource.h"
+ #include "dcn20_opp.h"
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dcn20_dsc.h"
+-#endif
+ 
+ #include "dcn20_link_encoder.h"
+ #include "dcn20_stream_encoder.h"
+@@ -93,11 +91,7 @@ struct _vcs_dpi_ip_params_st dcn2_0_ip = {
+ 	.hostvm_max_page_table_levels = 4,
+ 	.hostvm_cached_page_table_levels = 0,
+ 	.pte_group_size_bytes = 2048,
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	.num_dsc = 6,
+-#else
+-	.num_dsc = 0,
+-#endif
+ 	.rob_buffer_size_kbytes = 168,
+ 	.det_buffer_size_kbytes = 164,
+ 	.dpte_buffer_size_in_pte_reqs_luma = 84,
+@@ -742,7 +736,6 @@ static const struct dce110_aux_registers_mask aux_mask = {
+ };
+ 
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #define dsc_regsDCN20(id)\
+ [id] = {\
+ 	DSC_REG_LIST_DCN20(id)\
+@@ -764,7 +757,6 @@ static const struct dcn20_dsc_shift dsc_shift = {
+ static const struct dcn20_dsc_mask dsc_mask = {
+ 	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
+ };
+-#endif
+ 
+ static const struct dccg_registers dccg_regs = {
+ 		DCCG_REG_LIST_DCN2()
+@@ -788,9 +780,7 @@ static const struct resource_caps res_cap_nv10 = {
+ 		.num_dwb = 1,
+ 		.num_ddc = 6,
+ 		.num_vmid = 16,
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 		.num_dsc = 6,
+-#endif
+ };
+ 
+ static const struct dc_plane_cap plane_cap = {
+@@ -1211,7 +1201,6 @@ void dcn20_clock_source_destroy(struct clock_source **clk_src)
+ 	*clk_src = NULL;
+ }
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 
+ struct display_stream_compressor *dcn20_dsc_create(
+ 	struct dc_context *ctx, uint32_t inst)
+@@ -1234,7 +1223,6 @@ void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
+ 	*dsc = NULL;
+ }
+ 
+-#endif
+ 
+ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
+ {
+@@ -1247,12 +1235,10 @@ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
+ 		}
+ 	}
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ 		if (pool->base.dscs[i] != NULL)
+ 			dcn20_dsc_destroy(&pool->base.dscs[i]);
+ 	}
+-#endif
+ 
+ 	if (pool->base.mpc != NULL) {
+ 		kfree(TO_DCN20_MPC(pool->base.mpc));
+@@ -1463,7 +1449,6 @@ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state
+ 	return status;
+ }
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 
+ static void acquire_dsc(struct resource_context *res_ctx,
+ 			const struct resource_pool *pool,
+@@ -1497,10 +1482,8 @@ static void release_dsc(struct resource_context *res_ctx,
+ 		}
+ }
+ 
+-#endif
+ 
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
+ 		struct dc_state *dc_ctx,
+ 		struct dc_stream_state *dc_stream)
+@@ -1552,7 +1535,6 @@ static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
+ 	else
+ 		return DC_OK;
+ }
+-#endif
+ 
+ 
+ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
+@@ -1564,11 +1546,9 @@ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx,
+ 	if (result == DC_OK)
+ 		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	/* Get a DSC if required and available */
+ 	if (result == DC_OK && dc_stream->timing.flags.DSC)
+ 		result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
+-#endif
+ 
+ 	if (result == DC_OK)
+ 		result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
+@@ -1581,9 +1561,7 @@ enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_
+ {
+ 	enum dc_status result = DC_OK;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
+-#endif
+ 
+ 	return result;
+ }
+@@ -1666,9 +1644,7 @@ bool dcn20_split_stream_for_odm(
+ 	next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
+ 	next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
+ 	next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	next_odm_pipe->stream_res.dsc = NULL;
+-#endif
+ 	if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
+ 		next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
+ 		next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
+@@ -1714,14 +1690,12 @@ bool dcn20_split_stream_for_odm(
+ 		sd->recout.x = 0;
+ 	}
+ 	next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	if (next_odm_pipe->stream->timing.flags.DSC == 1) {
+ 		acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc);
+ 		ASSERT(next_odm_pipe->stream_res.dsc);
+ 		if (next_odm_pipe->stream_res.dsc == NULL)
+ 			return false;
+ 	}
+-#endif
+ 
+ 	return true;
+ }
+@@ -1745,9 +1719,7 @@ void dcn20_split_stream_for_mpc(
+ 	secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
+ 	secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
+ 	secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	secondary_pipe->stream_res.dsc = NULL;
+-#endif
+ 	if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
+ 		ASSERT(!secondary_pipe->bottom_pipe);
+ 		secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
+@@ -1835,11 +1807,9 @@ int dcn20_populate_dml_pipes_from_context(
+ 		pipes[pipe_cnt].pipe.src.dcc = 0;
+ 		pipes[pipe_cnt].pipe.src.vm = 0;*/
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 		pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
+ 		/* todo: rotation?*/
+ 		pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
+-#endif
+ 		if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
+ 			pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
+ 			/* 1/2 vblank */
+@@ -1927,14 +1897,12 @@ int dcn20_populate_dml_pipes_from_context(
+ 		case COLOR_DEPTH_161616:
+ 			output_bpc = 16;
+ 			break;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 		case COLOR_DEPTH_999:
+ 			output_bpc = 9;
+ 			break;
+ 		case COLOR_DEPTH_111111:
+ 			output_bpc = 11;
+ 			break;
+-#endif
+ 		default:
+ 			output_bpc = 8;
+ 			break;
+@@ -1962,10 +1930,8 @@ int dcn20_populate_dml_pipes_from_context(
+ 			pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
+ 		}
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 		if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
+ 			pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
+-#endif
+ 
+ 		/* todo: default max for now, until there is logic reflecting this in dc*/
+ 		pipes[pipe_cnt].dout.output_bpc = 12;
+@@ -2187,7 +2153,6 @@ void dcn20_set_mcif_arb_params(
+ 	}
+ }
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
+ {
+ 	int i;
+@@ -2221,7 +2186,6 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
+ 	}
+ 	return true;
+ }
+-#endif
+ 
+ struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
+ 		struct resource_context *res_ctx,
+@@ -2324,10 +2288,8 @@ void dcn20_merge_pipes_for_validate(
+ 			odm_pipe->bottom_pipe = NULL;
+ 			odm_pipe->prev_odm_pipe = NULL;
+ 			odm_pipe->next_odm_pipe = NULL;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 			if (odm_pipe->stream_res.dsc)
+ 				release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
+-#endif
+ 			/* Clear plane_res and stream_res */
+ 			memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
+ 			memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
+@@ -2547,14 +2509,12 @@ bool dcn20_fast_validate_bw(
+ 			ASSERT(0);
+ 		}
+ 	}
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	/* Actual dsc count per stream dsc validation*/
+ 	if (!dcn20_validate_dsc(dc, context)) {
+ 		context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
+ 				DML_FAIL_DSC_VALIDATION_FAILURE;
+ 		goto validate_fail;
+ 	}
+-#endif
+ 
+ 	*vlevel_out = vlevel;
+ 
+@@ -3656,7 +3616,6 @@ static bool dcn20_resource_construct(
+ 		goto create_fail;
+ 	}
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ 		pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
+ 		if (pool->base.dscs[i] == NULL) {
+@@ -3665,7 +3624,6 @@ static bool dcn20_resource_construct(
+ 			goto create_fail;
+ 		}
+ 	}
+-#endif
+ 
+ 	if (!dcn20_dwbc_create(ctx, &pool->base)) {
+ 		BREAK_TO_DEBUGGER();
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+index 7187e0f8eb28..840ca66c34e1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+@@ -127,9 +127,7 @@ int dcn20_validate_apply_pipe_split_flags(
+ 		struct dc_state *context,
+ 		int vlevel,
+ 		bool *split);
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx);
+-#endif
+ void dcn20_split_stream_for_mpc(
+ 		struct resource_context *res_ctx,
+ 		const struct resource_pool *pool,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+index b909c526b7f9..3549c81b20b7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+@@ -203,7 +203,6 @@ static void enc2_stream_encoder_stop_hdmi_info_packets(
+ 		HDMI_GENERIC7_LINE, 0);
+ }
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 
+ /* Update GSP7 SDP 128 byte long */
+ static void enc2_update_gsp7_128_info_packet(
+@@ -358,7 +357,6 @@ static void enc2_read_state(struct stream_encoder *enc, struct enc_state *s)
+ 		REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
+ 	}
+ }
+-#endif
+ 
+ /* Set Dynamic Metadata-configuration.
+  *   enable_dme:         TRUE: enables Dynamic Metadata Enfine, FALSE: disables DME
+@@ -438,10 +436,8 @@ static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
+ {
+ 	bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
+ 			&& !timing->dsc_cfg.ycbcr422_simple);
+-#endif
+ 	return two_pix;
+ }
+ 
+@@ -587,11 +583,9 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = {
+ 	.dp_get_pixel_format =
+ 		enc1_stream_encoder_dp_get_pixel_format,
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	.enc_read_state = enc2_read_state,
+ 	.dp_set_dsc_config = enc2_dp_set_dsc_config,
+ 	.dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet,
+-#endif
+ 	.set_dynamic_metadata = enc2_set_dynamic_metadata,
+ 	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+index e8a504ca5890..e45683ac871a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+@@ -323,9 +323,7 @@ void dcn21_link_encoder_disable_output(
+ 
+ 
+ static const struct link_encoder_funcs dcn21_link_enc_funcs = {
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	.read_state = link_enc2_read_state,
+-#endif
+ 	.validate_output_with_stream =
+ 		dcn10_link_encoder_validate_output_with_stream,
+ 	.hw_init = enc2_hw_init,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 9ec73b513488..f68f643a82af 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -88,11 +88,7 @@ struct _vcs_dpi_ip_params_st dcn2_1_ip = {
+ 	.gpuvm_max_page_table_levels = 1,
+ 	.hostvm_max_page_table_levels = 4,
+ 	.hostvm_cached_page_table_levels = 2,
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	.num_dsc = 3,
+-#else
+-	.num_dsc = 0,
+-#endif
+ 	.rob_buffer_size_kbytes = 168,
+ 	.det_buffer_size_kbytes = 164,
+ 	.dpte_buffer_size_in_pte_reqs_luma = 44,
+@@ -538,7 +534,6 @@ static const struct dcn20_vmid_mask vmid_masks = {
+ 		DCN20_VMID_MASK_SH_LIST(_MASK)
+ };
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #define dsc_regsDCN20(id)\
+ [id] = {\
+ 	DSC_REG_LIST_DCN20(id)\
+@@ -560,7 +555,6 @@ static const struct dcn20_dsc_shift dsc_shift = {
+ static const struct dcn20_dsc_mask dsc_mask = {
+ 	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
+ };
+-#endif
+ 
+ #define ipp_regs(id)\
+ [id] = {\
+@@ -757,9 +751,7 @@ static const struct resource_caps res_cap_rn = {
+ 		.num_dwb = 1,
+ 		.num_ddc = 5,
+ 		.num_vmid = 1,
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 		.num_dsc = 3,
+-#endif
+ };
+ 
+ #ifdef DIAGS_BUILD
+@@ -784,9 +776,7 @@ static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
+ 		.num_pll = 4,
+ 		.num_dwb = 1,
+ 		.num_ddc = 4,
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 		.num_dsc = 2,
+-#endif
+ };
+ #endif
+ 
+@@ -865,12 +855,10 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
+ 		}
+ 	}
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ 		if (pool->base.dscs[i] != NULL)
+ 			dcn20_dsc_destroy(&pool->base.dscs[i]);
+ 	}
+-#endif
+ 
+ 	if (pool->base.mpc != NULL) {
+ 		kfree(TO_DCN20_MPC(pool->base.mpc));
+@@ -1299,7 +1287,6 @@ static void read_dce_straps(
+ 
+ }
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 
+ struct display_stream_compressor *dcn21_dsc_create(
+ 	struct dc_context *ctx, uint32_t inst)
+@@ -1315,7 +1302,6 @@ struct display_stream_compressor *dcn21_dsc_create(
+ 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
+ 	return &dsc->base;
+ }
+-#endif
+ 
+ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
+ {
+@@ -1875,7 +1861,6 @@ static bool dcn21_resource_construct(
+ 		goto create_fail;
+ 	}
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+ 		pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
+ 		if (pool->base.dscs[i] == NULL) {
+@@ -1884,7 +1869,6 @@ static bool dcn21_resource_construct(
+ 			goto create_fail;
+ 		}
+ 	}
+-#endif
+ 
+ 	if (!dcn20_dwbc_create(ctx, &pool->base)) {
+ 		BREAK_TO_DEBUGGER();
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+index 94b75e942607..8bde1d688f2e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+@@ -118,13 +118,11 @@ bool dm_helpers_submit_i2c(
+ 		const struct dc_link *link,
+ 		struct i2c_command *cmd);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool dm_helpers_dp_write_dsc_enable(
+ 		struct dc_context *ctx,
+ 		const struct dc_stream_state *stream,
+ 		bool enable
+ );
+-#endif
+ bool dm_helpers_is_dp_sink_present(
+ 		struct dc_link *link);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+index 95f3193da951..04d54283c94f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
++++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+@@ -41,9 +41,7 @@ enum pp_smu_ver {
+ 	 */
+ 	PP_SMU_UNSUPPORTED,
+ 	PP_SMU_VER_RV,
+-#ifndef CONFIG_TRIM_DRM_AMD_DC_DCN2_0
+ 	PP_SMU_VER_NV,
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ 	PP_SMU_VER_RN,
+ #endif
+@@ -137,7 +135,6 @@ struct pp_smu_funcs_rv {
+ 	void (*set_pme_wa_enable)(struct pp_smu *pp);
+ };
+ 
+-#ifndef CONFIG_TRIM_DRM_AMD_DC_DCN2_0
+ /* Used by pp_smu_funcs_nv.set_voltage_by_freq
+  *
+  */
+@@ -241,7 +238,6 @@ struct pp_smu_funcs_nv {
+ 	enum pp_smu_status (*set_pstate_handshake_support)(struct pp_smu *pp,
+ 			BOOLEAN pstate_handshake_supported);
+ };
+-#endif
+ 
+ #define PP_SMU_NUM_SOCCLK_DPM_LEVELS  8
+ #define PP_SMU_NUM_DCFCLK_DPM_LEVELS  8
+@@ -285,9 +281,7 @@ struct pp_smu_funcs {
+ 	struct pp_smu ctx;
+ 	union {
+ 		struct pp_smu_funcs_rv rv_funcs;
+-#ifndef CONFIG_TRIM_DRM_AMD_DC_DCN2_0
+ 		struct pp_smu_funcs_nv nv_funcs;
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ 		struct pp_smu_funcs_rn rn_funcs;
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+index 9cc2fe56ed64..e3d6546a08c2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
+@@ -43,7 +43,7 @@ endif
+ 
+ CFLAGS_display_mode_lib.o := $(dml_ccflags)
+ 
+-ifdef CONFIG_DRM_AMD_DC_DCN2_0
++ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ CFLAGS_display_mode_vba.o := $(dml_ccflags)
+ CFLAGS_display_mode_vba_20.o := $(dml_ccflags)
+ CFLAGS_display_rq_dlg_calc_20.o := $(dml_ccflags)
+@@ -64,7 +64,7 @@ CFLAGS_dml_common_defs.o := $(dml_ccflags)
+ DML = display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
+ 	dml_common_defs.o
+ 
+-ifdef CONFIG_DRM_AMD_DC_DCN2_0
++ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_20.o
+ DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o
+ endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+index ba77957aefe3..945291d5ad98 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+@@ -23,7 +23,6 @@
+  *
+  */
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 
+ #include "../display_mode_lib.h"
+ #include "../dml_inline_defs.h"
+@@ -6126,4 +6125,3 @@ static double CalculateExtraLatency(
+ 	return CalculateExtraLatency;
+ }
+ 
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+index a1f207cbb966..a4b103eb4b02 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+@@ -23,7 +23,6 @@
+  *
+  */
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 
+ #include "../display_mode_lib.h"
+ #include "../display_mode_vba.h"
+@@ -1820,4 +1819,3 @@ static void calculate_ttu_cursor(
+ 	}
+ }
+ 
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+index 1c97083b8d0b..55d4cb23a073 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+@@ -135,9 +135,7 @@ enum dm_validation_status {
+ 	DML_FAIL_DIO_SUPPORT,
+ 	DML_FAIL_NOT_ENOUGH_DSC,
+ 	DML_FAIL_DSC_CLK_REQUIRED,
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	DML_FAIL_DSC_VALIDATION_FAILURE,
+-#endif
+ 	DML_FAIL_URGENT_LATENCY,
+ 	DML_FAIL_REORDERING_BUFFER,
+ 	DML_FAIL_DISPCLK_DPPCLK,
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+index 704efefdcba8..9c6016e57d2b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+@@ -25,18 +25,15 @@
+ 
+ #include "display_mode_lib.h"
+ #include "dc_features.h"
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "dcn20/display_mode_vba_20.h"
+ #include "dcn20/display_rq_dlg_calc_20.h"
+ #include "dcn20/display_mode_vba_20v2.h"
+ #include "dcn20/display_rq_dlg_calc_20v2.h"
+-#endif
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_1
+ #include "dcn21/display_mode_vba_21.h"
+ #include "dcn21/display_rq_dlg_calc_21.h"
+ #endif
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ const struct dml_funcs dml20_funcs = {
+ 	.validate = dml20_ModeSupportAndSystemConfigurationFull,
+ 	.recalculate = dml20_recalculate,
+@@ -50,7 +47,6 @@ const struct dml_funcs dml20v2_funcs = {
+ 	.rq_dlg_get_dlg_reg = dml20v2_rq_dlg_get_dlg_reg,
+ 	.rq_dlg_get_rq_reg = dml20v2_rq_dlg_get_rq_reg
+ };
+-#endif
+ 
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_1
+ const struct dml_funcs dml21_funcs = {
+@@ -70,14 +66,12 @@ void dml_init_instance(struct display_mode_lib *lib,
+ 	lib->ip = *ip_params;
+ 	lib->project = project;
+ 	switch (project) {
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	case DML_PROJECT_NAVI10:
+ 		lib->funcs = dml20_funcs;
+ 		break;
+ 	case DML_PROJECT_NAVI10v2:
+ 		lib->funcs = dml20v2_funcs;
+ 		break;
+-#endif
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_1
+         case DML_PROJECT_DCN21:
+                 lib->funcs = dml21_funcs;
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+index d8c59aa356b6..212188be1ec1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+@@ -27,17 +27,13 @@
+ 
+ 
+ #include "dml_common_defs.h"
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ #include "display_mode_vba.h"
+-#endif
+ 
+ enum dml_project {
+ 	DML_PROJECT_UNDEFINED,
+ 	DML_PROJECT_RAVEN1,
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	DML_PROJECT_NAVI10,
+ 	DML_PROJECT_NAVI10v2,
+-#endif
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_1
+ 	DML_PROJECT_DCN21,
+ #endif
+@@ -70,9 +66,7 @@ struct display_mode_lib {
+ 	struct _vcs_dpi_ip_params_st ip;
+ 	struct _vcs_dpi_soc_bounding_box_st soc;
+ 	enum dml_project project;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	struct vba_vars_st vba;
+-#endif
+ 	struct dal_logger *logger;
+ 	struct dml_funcs funcs;
+ };
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+index 19356180cbb6..516396d53d01 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+@@ -146,7 +146,6 @@ struct _vcs_dpi_ip_params_st {
+ 	unsigned int writeback_interface_buffer_size_kbytes;
+ 	unsigned int writeback_line_buffer_buffer_size;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	unsigned int writeback_10bpc420_supported;
+ 	double writeback_max_hscl_ratio;
+ 	double writeback_max_vscl_ratio;
+@@ -156,7 +155,6 @@ struct _vcs_dpi_ip_params_st {
+ 	unsigned int writeback_max_vscl_taps;
+ 	unsigned int writeback_line_buffer_luma_buffer_size;
+ 	unsigned int writeback_line_buffer_chroma_buffer_size;
+-#endif
+ 
+ 	unsigned int max_page_table_levels;
+ 	unsigned int max_num_dpp;
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+index da5e9d2fd6b6..b1c2b79e42b6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+@@ -23,7 +23,6 @@
+  *
+  */
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 
+ #include "display_mode_lib.h"
+ #include "display_mode_vba.h"
+@@ -862,4 +861,3 @@ double CalculateWriteBackDISPCLK(
+ 	return CalculateWriteBackDISPCLK;
+ }
+ 
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+index 6d8b5c61de68..3eb657ed5714 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+@@ -23,7 +23,6 @@
+  *
+  */
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 
+ #ifndef __DML2_DISPLAY_MODE_VBA_H__
+ #define __DML2_DISPLAY_MODE_VBA_H__
+@@ -872,4 +871,3 @@ double CalculateWriteBackDISPCLK(
+ 		unsigned int WritebackChromaLineBufferWidth);
+ 
+ #endif /* _DML2_DISPLAY_MODE_VBA_H_ */
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+index f76a72a96631..ec86ba73a039 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+@@ -22,7 +22,6 @@
+  * Author: AMD
+  */
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dc_hw_types.h"
+ #include "dsc.h"
+ #include <drm/drm_dp_helper.h>
+@@ -907,4 +906,3 @@ bool dc_dsc_compute_config(
+ 			timing, dsc_min_slice_height_override, dsc_cfg);
+ 	return is_dsc_possible;
+ }
+-#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h b/drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h
+index 020ad8f685ea..9f70e87b3ecb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h
+@@ -1,4 +1,3 @@
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 
+ /*
+  * Copyright 2017 Advanced Micro Devices, Inc.
+@@ -51,4 +50,3 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct dsc_par
+ 
+ #endif
+ 
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/qp_tables.h b/drivers/gpu/drm/amd/display/dc/dsc/qp_tables.h
+index f66d006eac5d..e5fac9f4181d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/qp_tables.h
++++ b/drivers/gpu/drm/amd/display/dc/dsc/qp_tables.h
+@@ -1,4 +1,3 @@
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 
+ /*
+  * Copyright 2017 Advanced Micro Devices, Inc.
+@@ -703,4 +702,3 @@ const qp_table   qp_table_422_8bpc_max = {
+ 	{  16, { 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 4} }
+ };
+ 
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
+index 76c4b12d6824..03ae15946c6d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
++++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
+@@ -1,4 +1,3 @@
+-#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
+ 
+ /*
+  * Copyright 2017 Advanced Micro Devices, Inc.
+@@ -252,4 +251,3 @@ void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_com
+ 	rc->rc_buf_thresh[13] = 8064;
+ }
+ 
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
+index f1d6e793bc61..b6b1f09c2009 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
++++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
+@@ -1,4 +1,3 @@
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 
+ /*
+  * Copyright 2017 Advanced Micro Devices, Inc.
+@@ -82,4 +81,3 @@ void calc_rc_params(struct rc_params *rc, enum colour_mode cm, enum bits_per_com
+ 
+ #endif
+ 
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
+index 73172fd0b529..1f6e63b71456 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
++++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
+@@ -1,4 +1,3 @@
+-#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
+ /*
+  * Copyright 2012-17 Advanced Micro Devices, Inc.
+  *
+@@ -144,4 +143,3 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct dsc_par
+ 	return ret;
+ }
+ 
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+index b3062275711e..7791cd29fc18 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+@@ -67,12 +67,10 @@ GPIO_DCN10 = hw_translate_dcn10.o hw_factory_dcn10.o
+ AMD_DAL_GPIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn10/,$(GPIO_DCN10))
+ 
+ AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN10)
+-endif
+ 
+ ###############################################################################
+ # DCN 2
+ ###############################################################################
+-ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ GPIO_DCN20 = hw_translate_dcn20.o hw_factory_dcn20.o
+ 
+ AMD_DAL_GPIO_DCN20 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn20/,$(GPIO_DCN20))
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
+index 2664cb22dfe7..83f798cb8b21 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
+@@ -22,7 +22,6 @@
+  * Authors: AMD
+  *
+  */
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "dm_services.h"
+ #include "include/gpio_types.h"
+ #include "../hw_factory.h"
+@@ -258,4 +257,3 @@ void dal_hw_factory_dcn20_init(struct hw_factory *factory)
+ 	factory->funcs = &funcs;
+ }
+ 
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h
+index 43a4ce7aa3bf..0fd9b315bd7a 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h
+@@ -22,7 +22,6 @@
+  * Authors: AMD
+  *
+  */
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #ifndef __DAL_HW_FACTORY_DCN20_H__
+ #define __DAL_HW_FACTORY_DCN20_H__
+ 
+@@ -30,4 +29,3 @@
+ void dal_hw_factory_dcn20_init(struct hw_factory *factory);
+ 
+ #endif /* __DAL_HW_FACTORY_DCN20_H__ */
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
+index 915e896e0e91..52ba62b3b5e4 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
+@@ -26,7 +26,6 @@
+ /*
+  * Pre-requisites: headers required by header of this unit
+  */
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "hw_translate_dcn20.h"
+ 
+ #include "dm_services.h"
+@@ -379,4 +378,3 @@ void dal_hw_translate_dcn20_init(struct hw_translate *tr)
+ 	tr->funcs = &funcs;
+ }
+ 
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h
+index 01f52c7bed86..5f7a35530e26 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h
+@@ -22,7 +22,6 @@
+  * Authors: AMD
+  *
+  */
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #ifndef __DAL_HW_TRANSLATE_DCN20_H__
+ #define __DAL_HW_TRANSLATE_DCN20_H__
+ 
+@@ -32,4 +31,3 @@ struct hw_translate;
+ void dal_hw_translate_dcn20_init(struct hw_translate *tr);
+ 
+ #endif /* __DAL_HW_TRANSLATE_DCN20_H__ */
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
+index 8572678f8d4f..907c5911eb9e 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
+@@ -22,7 +22,6 @@
+  * Authors: AMD
+  *
+  */
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "dm_services.h"
+ #include "include/gpio_types.h"
+ #include "../hw_factory.h"
+@@ -239,4 +238,3 @@ void dal_hw_factory_dcn21_init(struct hw_factory *factory)
+ 	factory->funcs = &funcs;
+ }
+ 
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
+index fbb58fb8c318..291966efe63d 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
+@@ -26,7 +26,6 @@
+ /*
+  * Pre-requisites: headers required by header of this unit
+  */
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "hw_translate_dcn21.h"
+ 
+ #include "dm_services.h"
+@@ -382,4 +381,3 @@ void dal_hw_translate_dcn21_init(struct hw_translate *tr)
+ 	tr->funcs = &funcs;
+ }
+ 
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h b/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
+index f91e85b04956..308a543178a5 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
++++ b/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
+@@ -48,13 +48,11 @@
+ 	DDC_GPIO_REG_LIST(cd,id),\
+ 	.ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP)
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	#define DDC_REG_LIST_DCN2(cd, id) \
+ 	DDC_GPIO_REG_LIST(cd, id),\
+ 	.ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\
+ 	.phy_aux_cntl = REG(PHY_AUX_CNTL), \
+ 	.dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
+-#endif
+ 
+ #define DDC_GPIO_VGA_REG_LIST_ENTRY(type,cd)\
+ 	.type ## _reg =   REG(DC_GPIO_DDCVGA_ ## type),\
+@@ -90,13 +88,11 @@
+ 	DDC_GPIO_I2C_REG_LIST(cd),\
+ 	.ddc_setup = 0
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define DDC_I2C_REG_LIST_DCN2(cd) \
+ 	DDC_GPIO_I2C_REG_LIST(cd),\
+ 	.ddc_setup = 0,\
+ 	.phy_aux_cntl = REG(PHY_AUX_CNTL), \
+ 	.dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
+-#endif
+ #define DDC_MASK_SH_LIST_COMMON(mask_sh) \
+ 		SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\
+ 		SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_ENABLE, mask_sh),\
+@@ -110,22 +106,18 @@
+ 		SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SDA_PD_DIS, mask_sh),\
+ 		SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SCL_PD_DIS, mask_sh)
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define DDC_MASK_SH_LIST_DCN2(mask_sh, cd) \
+ 	{DDC_MASK_SH_LIST_COMMON(mask_sh),\
+ 	0,\
+ 	0,\
+ 	(PHY_AUX_CNTL__AUX## cd ##_PAD_RXSEL## mask_sh),\
+ 	(DC_GPIO_AUX_CTRL_5__DDC_PAD## cd ##_I2CMODE## mask_sh)}
+-#endif
+ 
+ struct ddc_registers {
+ 	struct gpio_registers gpio;
+ 	uint32_t ddc_setup;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	uint32_t phy_aux_cntl;
+ 	uint32_t dc_gpio_aux_ctrl_5;
+-#endif
+ };
+ 
+ struct ddc_sh_mask {
+@@ -140,11 +132,9 @@ struct ddc_sh_mask {
+ 	/* i2cpad_mask */
+ 	uint32_t DC_GPIO_SDA_PD_DIS;
+ 	uint32_t DC_GPIO_SCL_PD_DIS;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	//phy_aux_cntl
+ 	uint32_t AUX_PAD_RXSEL;
+ 	uint32_t DDC_PAD_I2CMODE;
+-#endif
+ };
+ 
+ 
+@@ -180,7 +170,6 @@ struct ddc_sh_mask {
+ {\
+ 	DDC_I2C_REG_LIST(SCL)\
+ }
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define ddc_data_regs_dcn2(id) \
+ {\
+ 	DDC_REG_LIST_DCN2(DATA, id)\
+@@ -200,7 +189,6 @@ struct ddc_sh_mask {
+ {\
+ 	DDC_REG_LIST_DCN2(SCL)\
+ }
+-#endif
+ 
+ 
+ #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
+index 95d1c44a1d47..847da5a76b70 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
+@@ -147,7 +147,6 @@ static enum gpio_result set_config(
+ 					AUX_PAD1_MODE, 0);
+ 		}
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 		if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) {
+ 				REG_UPDATE(dc_gpio_aux_ctrl_5, DDC_PAD_I2CMODE, 1);
+ 		}
+@@ -155,7 +154,6 @@ static enum gpio_result set_config(
+ 		if (ddc->regs->phy_aux_cntl != 0) {
+ 				REG_UPDATE(phy_aux_cntl, AUX_PAD_RXSEL, 1);
+ 		}
+-#endif
+ 		return GPIO_RESULT_OK;
+ 	case GPIO_DDC_CONFIG_TYPE_MODE_AUX:
+ 		/* set the AUX pad mode */
+@@ -163,12 +161,10 @@ static enum gpio_result set_config(
+ 			REG_SET(gpio.MASK_reg, regval,
+ 					AUX_PAD1_MODE, 1);
+ 		}
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 		if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) {
+ 			REG_UPDATE(dc_gpio_aux_ctrl_5,
+ 					DDC_PAD_I2CMODE, 0);
+ 		}
+-#endif
+ 
+ 		return GPIO_RESULT_OK;
+ 	case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT:
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+index cb5857c8c7e9..18b9fab15676 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+@@ -46,9 +46,7 @@
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ #include "dcn10/hw_factory_dcn10.h"
+ #endif
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "dcn20/hw_factory_dcn20.h"
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ #include "dcn21/hw_factory_dcn21.h"
+ #endif
+@@ -93,17 +91,15 @@ bool dal_hw_factory_init(
+ 	case DCN_VERSION_1_01:
+ 		dal_hw_factory_dcn10_init(factory);
+ 		return true;
+-#endif
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	case DCN_VERSION_2_0:
+ 		dal_hw_factory_dcn20_init(factory);
+ 		return true;
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ 	case DCN_VERSION_2_1:
+ 		dal_hw_factory_dcn21_init(factory);
+ 		return true;
++#endif
+ #endif
+ 
+ 	default:
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+index f2046f55d6a8..8e10bff4c074 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+@@ -46,9 +46,7 @@
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ #include "dcn10/hw_translate_dcn10.h"
+ #endif
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "dcn20/hw_translate_dcn20.h"
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ #include "dcn21/hw_translate_dcn21.h"
+ #endif
+@@ -90,17 +88,15 @@ bool dal_hw_translate_init(
+ 	case DCN_VERSION_1_01:
+ 		dal_hw_translate_dcn10_init(translate);
+ 		return true;
+-#endif
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	case DCN_VERSION_2_0:
+ 		dal_hw_translate_dcn20_init(translate);
+ 		return true;
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ 	case DCN_VERSION_2_1:
+ 		dal_hw_translate_dcn21_init(translate);
+ 		return true;
++#endif
+ #endif
+ 
+ 	default:
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+index fd39e2abe2ed..4ead89dd7c41 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+@@ -43,10 +43,8 @@ enum dc_status {
+ 	DC_FAIL_BANDWIDTH_VALIDATE = 13, /* BW and Watermark validation */
+ 	DC_FAIL_SCALING = 14,
+ 	DC_FAIL_DP_LINK_TRAINING = 15,
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	DC_FAIL_DSC_VALIDATE = 16,
+ 	DC_NO_DSC_RESOURCE = 17,
+-#endif
+ 	DC_FAIL_UNSUPPORTED_1 = 18,
+ 	DC_FAIL_CLK_EXCEED_MAX = 21,
+ 	DC_FAIL_CLK_BELOW_MIN = 22, /*THIS IS MIN PER IP*/
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+index 67efc8094ae7..d7018e894bc2 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+@@ -36,10 +36,8 @@
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ #include "mpc.h"
+ #endif
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #include "dwb.h"
+ #include "mcif_wb.h"
+-#endif
+ 
+ #define MAX_CLOCK_SOURCES 7
+ 
+@@ -135,7 +133,6 @@ struct resource_funcs {
+ 			struct resource_context *res_ctx,
+ 			const struct resource_pool *pool,
+ 			struct dc_stream_state *stream);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	void (*populate_dml_writeback_from_context)(
+ 			struct dc *dc,
+ 			struct resource_context *res_ctx,
+@@ -146,7 +143,6 @@ struct resource_funcs {
+ 			struct dc_state *context,
+ 			display_e2e_pipe_params_st *pipes,
+ 			int pipe_cnt);
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ 	void (*update_bw_bounding_box)(
+ 			struct dc *dc,
+@@ -180,7 +176,6 @@ struct resource_pool {
+ 	struct dce_i2c_sw *sw_i2cs[MAX_PIPES];
+ 	bool i2c_hw_buffer_in_use;
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	struct dwbc *dwbc[MAX_DWB_PIPES];
+ 	struct mcif_wb *mcif_wb[MAX_DWB_PIPES];
+ 	struct {
+@@ -188,11 +183,8 @@ struct resource_pool {
+ 		unsigned int gsl_1:1;
+ 		unsigned int gsl_2:1;
+ 	} gsl_groups;
+-#endif
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	struct display_stream_compressor *dscs[MAX_PIPES];
+-#endif
+ 
+ 	unsigned int pipe_count;
+ 	unsigned int underlay_pipe_index;
+@@ -206,9 +198,7 @@ struct resource_pool {
+ 	unsigned int timing_generator_count;
+ 	unsigned int mpcc_count;
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	unsigned int writeback_pipe_count;
+-#endif
+ 	/*
+ 	 * reserved clock source for DP
+ 	 */
+@@ -240,9 +230,7 @@ struct dcn_fe_bandwidth {
+ 
+ struct stream_resource {
+ 	struct output_pixel_processor *opp;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	struct display_stream_compressor *dsc;
+-#endif
+ 	struct timing_generator *tg;
+ 	struct stream_encoder *stream_enc;
+ 	struct audio *audio;
+@@ -251,12 +239,10 @@ struct stream_resource {
+ 	struct encoder_info_frame encoder_info_frame;
+ 
+ 	struct abm *abm;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	/* There are only (num_pipes+1)/2 groups. 0 means unassigned,
+ 	 * otherwise it's using group number 'gsl_group-1'
+ 	 */
+ 	uint8_t gsl_group;
+-#endif
+ };
+ 
+ struct plane_resource {
+@@ -315,10 +301,8 @@ struct pipe_ctx {
+ 	struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
+ #endif
+ 	union pipe_update_flags update_flags;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	struct dwbc *dwbc;
+ 	struct mcif_wb *mcif_wb;
+-#endif
+ };
+ 
+ struct resource_context {
+@@ -327,9 +311,7 @@ struct resource_context {
+ 	bool is_audio_acquired[MAX_PIPES];
+ 	uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
+ 	uint8_t dp_clock_source_ref_count;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	bool is_dsc_acquired[MAX_PIPES];
+-#endif
+ };
+ 
+ struct dce_bw_output {
+@@ -349,18 +331,14 @@ struct dce_bw_output {
+ 	int blackout_recovery_time_us;
+ };
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dcn_bw_writeback {
+ 	struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES];
+ };
+-#endif
+ 
+ struct dcn_bw_output {
+ 	struct dc_clocks clk;
+ 	struct dcn_watermark_set watermarks;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	struct dcn_bw_writeback bw_writeback;
+-#endif
+ };
+ 
+ union bw_output {
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+index 1e6ff6eb5bfc..4879cf54d8f1 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+@@ -75,13 +75,11 @@ void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
+ enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
+ void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ void dp_set_fec_ready(struct dc_link *link, bool ready);
+ void dp_set_fec_enable(struct dc_link *link, bool enable);
+ bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
+ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
+ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
+ bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
+-#endif
+ 
+ #endif /* __DC_LINK_DP_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+index a17a77192690..862952c0286a 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+@@ -96,12 +96,10 @@ enum dentist_divider_range {
+ 	.MP1_SMN_C2PMSG_83 = mmMP1_SMN_C2PMSG_83, \
+ 	.MP1_SMN_C2PMSG_67 = mmMP1_SMN_C2PMSG_67
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ #define CLK_REG_LIST_NV10() \
+ 	SR(DENTIST_DISPCLK_CNTL), \
+ 	CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \
+ 	CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)
+-#endif
+ 
+ #define CLK_SF(reg_name, field_name, post_fix)\
+ 	.field_name = reg_name ## __ ## field_name ## post_fix
+@@ -120,7 +118,6 @@ enum dentist_divider_range {
+ 	CLK_SF(MP1_SMN_C2PMSG_83, CONTENT, mask_sh),\
+ 	CLK_SF(MP1_SMN_C2PMSG_91, CONTENT, mask_sh),
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ #define CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh) \
+ 	CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
+ 	CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\
+@@ -130,7 +127,6 @@ enum dentist_divider_range {
+ 	CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
+ 	CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_int, mask_sh),\
+ 	CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_frac, mask_sh)
+-#endif
+ 
+ #define CLK_REG_FIELD_LIST(type) \
+ 	type DPREFCLK_SRC_SEL; \
+@@ -143,30 +139,24 @@ enum dentist_divider_range {
+  ****************** Clock Manager Private Structures ***********************************
+  ***************************************************************************************
+  */
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ #define CLK20_REG_FIELD_LIST(type) \
+ 	type DENTIST_DPPCLK_WDIVIDER; \
+ 	type DENTIST_DPPCLK_CHG_DONE; \
+ 	type FbMult_int; \
+ 	type FbMult_frac;
+-#endif
+ 
+ #define VBIOS_SMU_REG_FIELD_LIST(type) \
+ 	type CONTENT;
+ 
+ struct clk_mgr_shift {
+ 	CLK_REG_FIELD_LIST(uint8_t)
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	CLK20_REG_FIELD_LIST(uint8_t)
+-#endif
+ 	VBIOS_SMU_REG_FIELD_LIST(uint32_t)
+ };
+ 
+ struct clk_mgr_mask {
+ 	CLK_REG_FIELD_LIST(uint32_t)
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	CLK20_REG_FIELD_LIST(uint32_t)
+-#endif
+ 	VBIOS_SMU_REG_FIELD_LIST(uint32_t)
+ };
+ 
+@@ -174,10 +164,8 @@ struct clk_mgr_registers {
+ 	uint32_t DPREFCLK_CNTL;
+ 	uint32_t DENTIST_DISPCLK_CNTL;
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	uint32_t CLK3_CLK2_DFS_CNTL;
+ 	uint32_t CLK3_CLK_PLL_REQ;
+-#endif
+ 
+ 	uint32_t MP1_SMN_C2PMSG_67;
+ 	uint32_t MP1_SMN_C2PMSG_83;
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+index c81a17aeaa25..c0dc1d0f5cae 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+@@ -52,7 +52,6 @@ struct dcn_hubbub_wm {
+ 	struct dcn_hubbub_wm_set sets[4];
+ };
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ enum dcn_hubbub_page_table_depth {
+ 	DCN_PAGE_TABLE_DEPTH_1_LEVEL,
+ 	DCN_PAGE_TABLE_DEPTH_2_LEVEL,
+@@ -101,13 +100,11 @@ struct hubbub_addr_config {
+ 	} default_addrs;
+ };
+ 
+-#endif
+ struct hubbub_funcs {
+ 	void (*update_dchub)(
+ 			struct hubbub *hubbub,
+ 			struct dchub_init_data *dh_data);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	int (*init_dchub_sys_ctx)(
+ 			struct hubbub *hubbub,
+ 			struct dcn_hubbub_phys_addr_config *pa_config);
+@@ -116,7 +113,6 @@ struct hubbub_funcs {
+ 			struct dcn_hubbub_virt_addr_config *va_config,
+ 			int vmid);
+ 
+-#endif
+ 	bool (*get_dcc_compression_cap)(struct hubbub *hubbub,
+ 			const struct dc_dcc_surface_param *input,
+ 			struct dc_surface_dcc_cap *output);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+index 474c7194a9f8..125e42dbd3c5 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+@@ -36,14 +36,10 @@ struct dpp {
+ 	struct dpp_caps *caps;
+ 	struct pwl_params regamma_params;
+ 	struct pwl_params degamma_params;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	struct dpp_cursor_attributes cur_attr;
+-#endif
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	struct pwl_params shaper_params;
+ 	bool cm_bypass_mode;
+-#endif
+ };
+ 
+ struct dpp_input_csc_matrix {
+@@ -56,7 +52,6 @@ struct dpp_grph_csc_adjustment {
+ 	enum graphics_gamut_adjust_type gamut_adjust_type;
+ };
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ struct cnv_color_keyer_params {
+ 	int color_keyer_en;
+ 	int color_keyer_mode;
+@@ -82,7 +77,6 @@ struct cnv_alpha_2bit_lut {
+ 	int lut2;
+ 	int lut3;
+ };
+-#endif
+ 
+ struct dcn_dpp_state {
+ 	uint32_t is_enabled;
+@@ -190,12 +184,8 @@ struct dpp_funcs {
+ 			enum surface_pixel_format format,
+ 			enum expansion_mode mode,
+ 			struct dc_csc_transform input_csc_color_matrix,
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 			enum dc_color_space input_color_space,
+ 			struct cnv_alpha_2bit_lut *alpha_2bit_lut);
+-#else
+-			enum dc_color_space input_color_space);
+-#endif
+ 
+ 	void (*dpp_full_bypass)(struct dpp *dpp_base);
+ 
+@@ -224,7 +214,6 @@ struct dpp_funcs {
+ 			bool dppclk_div,
+ 			bool enable);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	bool (*dpp_program_blnd_lut)(
+ 			struct dpp *dpp,
+ 			const struct pwl_params *params);
+@@ -237,7 +226,6 @@ struct dpp_funcs {
+ 	void (*dpp_cnv_set_alpha_keyer)(
+ 			struct dpp *dpp_base,
+ 			struct cnv_color_keyer_params *color_keyer);
+-#endif
+ };
+ 
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
+index c6ff3d78b435..c59740084ebc 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
+@@ -22,7 +22,6 @@
+  * Authors: AMD
+  *
+  */
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #ifndef __DAL_DSC_H__
+ #define __DAL_DSC_H__
+ 
+@@ -98,4 +97,3 @@ struct dsc_funcs {
+ };
+ 
+ #endif
+-#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
+index ff1a07b35c85..aed67754e81b 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
+@@ -51,11 +51,7 @@ enum dwb_source {
+ 	dwb_src_otg3,		/* for DCN1.x/DCN2.x */
+ };
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* DCN1.x, DCN2.x support 2 pipes */
+-#else
+-/* DCN1.x supports 2 pipes */
+-#endif
+ enum dwb_pipe {
+ 	dwb_pipe0 = 0,
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+@@ -64,7 +60,6 @@ enum dwb_pipe {
+ 	dwb_pipe_max_num,
+ };
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ enum dwb_frame_capture_enable {
+ 	DWB_FRAME_CAPTURE_DISABLE = 0,
+ 	DWB_FRAME_CAPTURE_ENABLE = 1,
+@@ -77,9 +72,7 @@ enum wbscl_coef_filter_type_sel {
+ 	WBSCL_COEF_CHROMA_HORZ_FILTER = 3
+ };
+ 
+-#endif
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dwb_warmup_params {
+ 	bool	warmup_en;	/* false: normal mode, true: enable pattern generator */
+ 	bool	warmup_mode;	/* false: 420, true: 444 */
+@@ -88,7 +81,6 @@ struct dwb_warmup_params {
+ 	int	warmup_width;	/* Pattern width (pixels) */
+ 	int	warmup_height;	/* Pattern height (lines) */
+ };
+-#endif
+ 
+ struct dwb_caps {
+ 	enum dce_version hw_version;	/* DCN engine version. */
+@@ -150,13 +142,11 @@ struct dwbc_funcs {
+ 		struct dwbc *dwbc,
+ 		bool is_new_content);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 
+ 	void (*set_warmup)(
+ 		struct dwbc *dwbc,
+ 		struct dwb_warmup_params *warmup_params);
+ 
+-#endif
+ 
+ 	bool (*get_dwb_status)(
+ 		struct dwbc *dwbc);
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+index 9def990d40a6..9793da0f3c7e 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+@@ -38,9 +38,7 @@ enum cursor_pitch {
+ };
+ 
+ enum cursor_lines_per_chunk {
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	CURSOR_LINE_PER_CHUNK_1 = 0, /* new for DCN2 */
+-#endif
+ 	CURSOR_LINE_PER_CHUNK_2 = 1,
+ 	CURSOR_LINE_PER_CHUNK_4,
+ 	CURSOR_LINE_PER_CHUNK_8,
+@@ -139,7 +137,6 @@ struct hubp_funcs {
+ 	unsigned int (*hubp_get_underflow_status)(struct hubp *hubp);
+ 	void (*hubp_init)(struct hubp *hubp);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	void (*dmdata_set_attributes)(
+ 			struct hubp *hubp,
+ 			const struct dc_dmdata_attributes *attr);
+@@ -159,7 +156,6 @@ struct hubp_funcs {
+ 	void (*hubp_set_flip_control_surface_gsl)(
+ 		struct hubp *hubp,
+ 		bool enable);
+-#endif
+ 
+ 	void (*validate_dml_output)(
+ 			struct hubp *hubp,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+index 91fda51e5370..75d419081e76 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+@@ -36,9 +36,7 @@
+ 
+ #define MAX_AUDIOS 7
+ #define MAX_PIPES 6
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define MAX_DWB_PIPES	1
+-#endif
+ 
+ struct gamma_curve {
+ 	uint32_t offset;
+@@ -81,7 +79,6 @@ struct pwl_result_data {
+ 	uint32_t delta_blue_reg;
+ };
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dc_rgb {
+ 	uint32_t red;
+ 	uint32_t green;
+@@ -110,7 +107,6 @@ struct tetrahedral_params {
+ 	bool use_12bits;
+ 
+ };
+-#endif
+ 
+ /* arr_curve_points - regamma regions/segments specification
+  * arr_points - beginning and end point specified separately (only one on DCE)
+@@ -195,13 +191,11 @@ enum opp_regamma {
+ 	OPP_REGAMMA_USER
+ };
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ enum optc_dsc_mode {
+ 	OPTC_DSC_DISABLED = 0,
+ 	OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */
+ 	OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */
+ };
+-#endif
+ 
+ struct dc_bias_and_scale {
+ 	uint16_t scale_red;
+@@ -224,12 +218,8 @@ enum test_pattern_mode {
+ 	TEST_PATTERN_MODE_VERTICALBARS,
+ 	TEST_PATTERN_MODE_HORIZONTALBARS,
+ 	TEST_PATTERN_MODE_SINGLERAMP_RGB,
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	TEST_PATTERN_MODE_DUALRAMP_RGB,
+ 	TEST_PATTERN_MODE_XR_BIAS_RGB
+-#else
+-	TEST_PATTERN_MODE_DUALRAMP_RGB
+-#endif
+ };
+ 
+ enum test_pattern_color_format {
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+index af57751ed8a1..fb748f082c56 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+@@ -113,12 +113,9 @@ struct link_encoder {
+ 	struct encoder_feature_support features;
+ 	enum transmitter transmitter;
+ 	enum hpd_source_id hpd_source;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	bool usbc_combo_phy;
+-#endif
+ };
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ struct link_enc_state {
+ 
+ 		uint32_t dphy_fec_en;
+@@ -127,13 +124,10 @@ struct link_enc_state {
+ 		uint32_t dp_link_training_complete;
+ 
+ };
+-#endif
+ 
+ struct link_encoder_funcs {
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	void (*read_state)(
+ 			struct link_encoder *enc, struct link_enc_state *s);
+-#endif
+ 	bool (*validate_output_with_stream)(
+ 		struct link_encoder *enc, const struct dc_stream_state *stream);
+ 	void (*hw_init)(struct link_encoder *enc);
+@@ -175,7 +169,6 @@ struct link_encoder_funcs {
+ 	unsigned int (*get_dig_frontend)(struct link_encoder *enc);
+ 	void (*destroy)(struct link_encoder **enc);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	void (*fec_set_enable)(struct link_encoder *enc,
+ 		bool enable);
+ 
+@@ -183,7 +176,6 @@ struct link_encoder_funcs {
+ 		bool ready);
+ 
+ 	bool (*fec_is_active)(struct link_encoder *enc);
+-#endif
+ 	bool (*is_in_alt_mode) (struct link_encoder *enc);
+ 
+ 	void (*get_max_link_cap)(struct link_encoder *enc,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+index 58826be81395..094afc4c8173 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+@@ -31,9 +31,7 @@
+ #define MAX_MPCC 6
+ #define MAX_OPP 6
+ 
+-#if   defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define MAX_DWB		1
+-#endif
+ 
+ enum mpc_output_csc_mode {
+ 	MPC_OUTPUT_CSC_DISABLE = 0,
+@@ -66,14 +64,12 @@ struct mpcc_blnd_cfg {
+ 	int global_alpha;
+ 	bool overlap_only;
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	/* MPCC top/bottom gain settings */
+ 	int bottom_gain_mode;
+ 	int background_color_bpc;
+ 	int top_gain;
+ 	int bottom_inside_gain;
+ 	int bottom_outside_gain;
+-#endif
+ };
+ 
+ struct mpcc_sm_cfg {
+@@ -90,7 +86,6 @@ struct mpcc_sm_cfg {
+ 	int force_next_field_polarity;
+ };
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct mpc_denorm_clamp {
+ 	int clamp_max_r_cr;
+ 	int clamp_min_r_cr;
+@@ -99,7 +94,6 @@ struct mpc_denorm_clamp {
+ 	int clamp_max_b_cb;
+ 	int clamp_min_b_cb;
+ };
+-#endif
+ 
+ /*
+  * MPCC connection and blending configuration for a single MPCC instance.
+@@ -126,10 +120,8 @@ struct mpc {
+ 	struct dc_context *ctx;
+ 
+ 	struct mpcc mpcc_array[MAX_MPCC];
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	struct pwl_params blender_params;
+ 	bool cm_bypass_mode;
+-#endif
+ };
+ 
+ struct mpcc_state {
+@@ -230,7 +222,6 @@ struct mpc_funcs {
+ 		struct mpc *mpc,
+ 		struct mpc_tree *tree);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	void (*set_denorm)(struct mpc *mpc,
+ 			int opp_id,
+ 			enum dc_color_depth output_depth);
+@@ -258,7 +249,6 @@ struct mpc_funcs {
+ 			struct mpc *mpc,
+ 			int mpcc_id,
+ 			bool power_on);
+-#endif
+ 
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+index b01ff30145fd..7575564b2265 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+@@ -263,9 +263,7 @@ struct oppbuf_params {
+ 	enum oppbuf_display_segmentation mso_segmentation;
+ 	uint32_t mso_overlap_pixel_num;
+ 	uint32_t pixel_repetition;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	uint32_t num_segment_padded_pixels;
+-#endif
+ };
+ 
+ struct opp_funcs {
+@@ -305,7 +303,6 @@ struct opp_funcs {
+ 			struct output_pixel_processor *opp,
+ 			bool enable);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	void (*opp_set_disp_pattern_generator)(
+ 			struct output_pixel_processor *opp,
+ 			enum controller_dp_test_pattern test_pattern,
+@@ -325,7 +322,6 @@ struct opp_funcs {
+ 	void (*opp_program_left_edge_extra_pixel)(
+ 			struct output_pixel_processor *opp,
+ 			bool count);
+-#endif
+ 
+ };
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+index c0b93d51ca8d..351b387ad606 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+@@ -65,13 +65,11 @@ struct audio_clock_info {
+ 	uint32_t cts_48khz;
+ };
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ enum dynamic_metadata_mode {
+ 	dmdata_dp,
+ 	dmdata_hdmi,
+ 	dmdata_dolby_vision
+ };
+-#endif
+ 
+ struct encoder_info_frame {
+ 	/* auxiliary video information */
+@@ -90,9 +88,7 @@ struct encoder_info_frame {
+ struct encoder_unblank_param {
+ 	struct dc_link_settings link_settings;
+ 	struct dc_crtc_timing timing;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	int opp_cnt;
+-#endif
+ };
+ 
+ struct encoder_set_dp_phy_pattern_param {
+@@ -109,7 +105,6 @@ struct stream_encoder {
+ 	enum engine_id id;
+ };
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ struct enc_state {
+ 	uint32_t dsc_mode;  // DISABLED  0; 1 or 2 indicate enabled state.
+ 	uint32_t dsc_slice_width;
+@@ -119,7 +114,6 @@ struct enc_state {
+ 	uint32_t sec_gsp_pps_enable;
+ 	uint32_t sec_stream_enable;
+ };
+-#endif
+ 
+ struct stream_encoder_funcs {
+ 	void (*dp_set_stream_attribute)(
+@@ -220,8 +214,6 @@ struct stream_encoder_funcs {
+ 		enum dc_pixel_encoding *encoding,
+ 		enum dc_color_depth *depth);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	void (*enc_read_state)(struct stream_encoder *enc, struct enc_state *s);
+ 
+ 	void (*dp_set_dsc_config)(
+@@ -233,7 +225,6 @@ struct stream_encoder_funcs {
+ 	void (*dp_set_dsc_pps_info_packet)(struct stream_encoder *enc,
+ 				bool enable,
+ 				uint8_t *dsc_packed_pps);
+-#endif
+ 
+ 	void (*set_dynamic_metadata)(struct stream_encoder *enc,
+ 			bool enable,
+@@ -243,7 +234,6 @@ struct stream_encoder_funcs {
+ 	void (*dp_set_odm_combine)(
+ 		struct stream_encoder *enc,
+ 		bool odm_combine);
+-#endif
+ };
+ 
+ #endif /* STREAM_ENCODER_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+index 27c73caf74ee..2d3efd71fa51 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+@@ -195,10 +195,8 @@ struct timing_generator_funcs {
+ 	void (*lock)(struct timing_generator *tg);
+ 	void (*lock_doublebuffer_disable)(struct timing_generator *tg);
+ 	void (*lock_doublebuffer_enable)(struct timing_generator *tg);
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	void(*triplebuffer_unlock)(struct timing_generator *tg);
+ 	void(*triplebuffer_lock)(struct timing_generator *tg);
+-#endif
+ 	void (*enable_reset_trigger)(struct timing_generator *tg,
+ 				     int source_tg_inst);
+ 	void (*enable_crtc_reset)(struct timing_generator *tg,
+@@ -235,7 +233,6 @@ struct timing_generator_funcs {
+ 	bool (*is_optc_underflow_occurred)(struct timing_generator *tg);
+ 	void (*clear_optc_underflow)(struct timing_generator *tg);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	void (*set_dwb_source)(struct timing_generator *optc,
+ 		uint32_t dwb_pipe_inst);
+ 
+@@ -243,7 +240,6 @@ struct timing_generator_funcs {
+ 			uint32_t *num_of_input_segments,
+ 			uint32_t *seg0_src_sel,
+ 			uint32_t *seg1_src_sel);
+-#endif
+ 
+ 	/**
+ 	 * Configure CRCs for the given timing generator. Return false if TG is
+@@ -267,13 +263,10 @@ struct timing_generator_funcs {
+ 	void (*set_vtg_params)(struct timing_generator *optc,
+ 			const struct dc_crtc_timing *dc_crtc_timing);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	void (*set_dsc_config)(struct timing_generator *optc,
+ 			       enum optc_dsc_mode dsc_mode,
+ 			       uint32_t dsc_bytes_per_pixel,
+ 			       uint32_t dsc_slice_width);
+-#endif
+ 	void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing);
+ 	void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
+ 			struct dc_crtc_timing *timing);
+@@ -281,7 +274,6 @@ struct timing_generator_funcs {
+ 	void (*set_gsl_source_select)(struct timing_generator *optc,
+ 			int group_idx,
+ 			uint32_t gsl_ready_signal);
+-#endif
+ };
+ 
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index d39c1e11def5..23e3a541b7c9 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -66,19 +66,15 @@ struct dce_hwseq {
+ 
+ struct pipe_ctx;
+ struct dc_state;
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dc_stream_status;
+ struct dc_writeback_info;
+-#endif
+ struct dchub_init_data;
+ struct dc_static_screen_events;
+ struct resource_pool;
+ struct resource_context;
+ struct stream_resource;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ struct dc_phy_addr_space_config;
+ struct dc_virtual_addr_space_config;
+-#endif
+ struct hubp;
+ struct dpp;
+ 
+@@ -113,7 +109,6 @@ struct hw_sequencer_funcs {
+ 			uint16_t *matrix,
+ 			int opp_id);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	void (*program_front_end_for_ctx)(
+ 			struct dc *dc,
+ 			struct dc_state *context);
+@@ -124,7 +119,6 @@ struct hw_sequencer_funcs {
+ 	void (*set_flip_control_gsl)(
+ 		struct pipe_ctx *pipe_ctx,
+ 		bool flip_immediate);
+-#endif
+ 
+ 	void (*update_plane_addr)(
+ 		const struct dc *dc,
+@@ -138,7 +132,6 @@ struct hw_sequencer_funcs {
+ 		struct dce_hwseq *hws,
+ 		struct dchub_init_data *dh_data);
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	int (*init_sys_ctx)(
+ 			struct dce_hwseq *hws,
+ 			struct dc *dc,
+@@ -148,7 +141,6 @@ struct hw_sequencer_funcs {
+ 			struct dc *dc,
+ 			struct dc_virtual_addr_space_config *va_config,
+ 			int vmid);
+-#endif
+ 	void (*update_mpcc)(
+ 		struct dc *dc,
+ 		struct pipe_ctx *pipe_ctx);
+@@ -239,13 +231,11 @@ struct hw_sequencer_funcs {
+ 			const struct dc *dc,
+ 			struct dc_state *context);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	bool (*update_bandwidth)(
+ 			struct dc *dc,
+ 			struct dc_state *context);
+ 	void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx);
+ 	bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx);
+-#endif
+ 
+ 	void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
+ 			unsigned int vmin, unsigned int vmax,
+@@ -323,7 +313,6 @@ struct hw_sequencer_funcs {
+ 			bool power_on);
+ 
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
+ 	void (*program_all_writeback_pipes_in_tree)(
+ 			struct dc *dc,
+@@ -339,7 +328,6 @@ struct hw_sequencer_funcs {
+ 			struct dc_state *context);
+ 	void (*disable_writeback)(struct dc *dc,
+ 			unsigned int dwb_pipe_inst);
+-#endif
+ 	enum dc_status (*set_clock)(struct dc *dc,
+ 			enum dc_clock_type clock_type,
+ 			uint32_t clk_khz,
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
+index bef224bf803e..7a85abc53d05 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
+@@ -46,12 +46,8 @@ struct resource_caps {
+ 	int num_pll;
+ 	int num_dwb;
+ 	int num_ddc;
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	int num_vmid;
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	int num_dsc;
+-#endif
+-#endif
+ };
+ 
+ struct resource_straps {
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile
+index ea75420fc876..75db39691616 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
+@@ -66,11 +66,9 @@ IRQ_DCN1 = irq_service_dcn10.o
+ AMD_DAL_IRQ_DCN1 = $(addprefix $(AMDDALPATH)/dc/irq/dcn10/,$(IRQ_DCN1))
+ 
+ AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN1)
+-endif
+ ###############################################################################
+ # DCN 20
+ ###############################################################################
+-ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ IRQ_DCN2 = irq_service_dcn20.o
+ 
+ AMD_DAL_IRQ_DCN2 = $(addprefix $(AMDDALPATH)/dc/irq/dcn20/,$(IRQ_DCN2))
+diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
+index b37db73478eb..2d7c298cf5d2 100644
+--- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
+@@ -80,22 +80,14 @@ static void virtual_stream_encoder_reset_hdmi_stream_attribute(
+ 		struct stream_encoder *enc)
+ {}
+ 
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ static void virtual_enc_dp_set_odm_combine(
+ 	struct stream_encoder *enc,
+ 	bool odm_combine)
+ {}
+-#endif
+-#endif
+ 
+ static const struct stream_encoder_funcs virtual_str_enc_funcs = {
+-#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	.dp_set_odm_combine =
+ 		virtual_enc_dp_set_odm_combine,
+-#endif
+-#endif
+ 	.dp_set_stream_attribute =
+ 		virtual_stream_encoder_dp_set_stream_attribute,
+ 	.hdmi_set_stream_attribute =
+diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+index 68e8f6378d40..d51fe99349ed 100644
+--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
++++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+@@ -149,7 +149,6 @@
+ 
+ #define FAMILY_RV 142 /* DCN 1*/
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 
+ #define FAMILY_NV 143 /* DCN 2*/
+ 
+@@ -163,7 +162,6 @@ enum {
+ #define ASICREV_IS_NAVI10_P(eChipRev)        (eChipRev < NV_NAVI12_P_A0)
+ #define ASICREV_IS_NAVI12_P(eChipRev)        ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0))
+ #define ASICREV_IS_NAVI14_M(eChipRev)        ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN))
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ #define RENOIR_A0 0x91
+ #define DEVICE_ID_RENOIR_1636 0x1636   // Renoir
+diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
+index fcc42372b6cf..2db5d4f60ac3 100644
+--- a/drivers/gpu/drm/amd/display/include/dal_types.h
++++ b/drivers/gpu/drm/amd/display/include/dal_types.h
+@@ -46,9 +46,7 @@ enum dce_version {
+ 	DCE_VERSION_MAX,
+ 	DCN_VERSION_1_0,
+ 	DCN_VERSION_1_01,
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	DCN_VERSION_2_0,
+-#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ 	DCN_VERSION_2_1,
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h
+index 2b219cdb13ad..89a709267019 100644
+--- a/drivers/gpu/drm/amd/display/include/logger_types.h
++++ b/drivers/gpu/drm/amd/display/include/logger_types.h
+@@ -66,12 +66,8 @@
+ #define DC_LOG_GAMMA(...) pr_debug("[GAMMA]:"__VA_ARGS__)
+ #define DC_LOG_ALL_GAMMA(...) pr_debug("[GAMMA]:"__VA_ARGS__)
+ #define DC_LOG_ALL_TF_CHANNELS(...) pr_debug("[GAMMA]:"__VA_ARGS__)
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #define DC_LOG_DSC(...) DRM_DEBUG_KMS(__VA_ARGS__)
+-#endif
+-#if defined(CONFIG_DRM_AMD_DC_DCN3_0) || defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ #define DC_LOG_DWB(...) DRM_DEBUG_KMS(__VA_ARGS__)
+-#endif
+ 
+ struct dal_logger;
+ 
+@@ -116,9 +112,7 @@ enum dc_log_type {
+ 	LOG_PERF_TRACE,
+ 	LOG_DISPLAYSTATS,
+ 	LOG_HDMI_RETIMER_REDRIVER,
+-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	LOG_DSC,
+-#endif
+ 	LOG_DWB,
+ 	LOG_GAMMA_DEBUG,
+ 	LOG_MAX_HW_POINTS,
+diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h b/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
+index b45f7d65e76a..fe2117904329 100644
+--- a/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
+@@ -45,7 +45,6 @@ enum vrr_packet_type {
+ 	PACKET_TYPE_VTEM
+ };
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ union lut3d_control_flags {
+ 	unsigned int raw;
+ 	struct {
+@@ -104,6 +103,5 @@ struct lut3d_settings {
+ 	enum lut3d_control_gamut_map map2;
+ 	enum lut3d_control_rotation_mode rotation2;
+ };
+-#endif
+ 
+ #endif /* MOD_SHARED_H_ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4556-drm-amdgpu-gfx10-explicitly-wait-for-cp-idle-after-h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4556-drm-amdgpu-gfx10-explicitly-wait-for-cp-idle-after-h.patch
new file mode 100644
index 00000000..55f28921
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4556-drm-amdgpu-gfx10-explicitly-wait-for-cp-idle-after-h.patch
@@ -0,0 +1,50 @@
+From 38eb1b45802cde565f6d4b708cb5e00bb7529119 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Thu, 14 Nov 2019 16:56:08 +0800
+Subject: [PATCH 4556/4736] drm/amdgpu/gfx10: explicitly wait for cp idle after
+ halt/unhalt
+
+50us is not enough to wait for cp ready after gpu reset on some navi asics.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Suggested-by: Jack Xiao <Jack.Xiao@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 14 ++++++++++++--
+ 1 file changed, 12 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 678ad1b26535..5403567683b7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -2404,7 +2404,7 @@ static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
+-static void gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
++static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
+ {
+ 	int i;
+ 	u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
+@@ -2417,7 +2417,17 @@ static void gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
+ 			adev->gfx.gfx_ring[i].sched.ready = false;
+ 	}
+ 	WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
+-	udelay(50);
++
++	for (i = 0; i < adev->usec_timeout; i++) {
++		if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
++			break;
++		udelay(1);
++	}
++
++	if (i >= adev->usec_timeout)
++		DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
++
++	return 0;
+ }
+ 
+ static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4557-drm-amdgpu-gfx10-re-init-clear-state-buffer-after-gp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4557-drm-amdgpu-gfx10-re-init-clear-state-buffer-after-gp.patch
new file mode 100644
index 00000000..b5e3bfe3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4557-drm-amdgpu-gfx10-re-init-clear-state-buffer-after-gp.patch
@@ -0,0 +1,105 @@
+From 309d7e98b251cde7df611946887daa4b1ccc0ae2 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 20 Nov 2019 14:02:22 +0800
+Subject: [PATCH 4557/4736] drm/amdgpu/gfx10: re-init clear state buffer after
+ gpu reset
+
+This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x.
+
+clear state buffer (resides in vram) is corrupted after 1st baco reset,
+upon gfxoff exit, CPF gets garbage header in CSIB and hangs.
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++----
+ 1 file changed, 37 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 5403567683b7..a364f2f645c2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
+ 	WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
+ }
+ 
+-static void gfx_v10_0_init_csb(struct amdgpu_device *adev)
++static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
+ {
++	int r;
++
++	if (!adev->in_gpu_reset) {
++		r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
++		if (r)
++			return r;
++
++		r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj,
++				   (void **)&adev->gfx.rlc.cs_ptr);
++		if (!r) {
++			adev->gfx.rlc.funcs->get_csb_buffer(adev,
++					adev->gfx.rlc.cs_ptr);
++			amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
++		}
++
++		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
++		if (r)
++			return r;
++	}
++
+ 	/* csib */
+ 	WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
+ 		     adev->gfx.rlc.clear_state_gpu_addr >> 32);
+ 	WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
+ 		     adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
+ 	WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
++
++	return 0;
+ }
+ 
+-static void gfx_v10_0_init_pg(struct amdgpu_device *adev)
++static int gfx_v10_0_init_pg(struct amdgpu_device *adev)
+ {
+ 	int i;
++	int r;
+ 
+-	gfx_v10_0_init_csb(adev);
++	r = gfx_v10_0_init_csb(adev);
++	if (r)
++		return r;
+ 
+ 	for (i = 0; i < adev->num_vmhubs; i++)
+ 		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
+ 
+ 	/* TODO: init power gating */
+-	return;
++	return 0;
+ }
+ 
+ void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
+@@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
+ 		r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
+ 		if (r)
+ 			return r;
+-		gfx_v10_0_init_pg(adev);
++
++		r = gfx_v10_0_init_pg(adev);
++		if (r)
++			return r;
+ 
+ 		/* enable RLC SRM */
+ 		gfx_v10_0_rlc_enable_srm(adev);
+@@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
+ 				return r;
+ 		}
+ 
+-		gfx_v10_0_init_pg(adev);
++		r = gfx_v10_0_init_pg(adev);
++		if (r)
++			return r;
++
+ 		adev->gfx.rlc.funcs->start(adev);
+ 
+ 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4558-drm-amdgpu-gfx10-fix-out-of-bound-mqd_backup-array-a.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4558-drm-amdgpu-gfx10-fix-out-of-bound-mqd_backup-array-a.patch
new file mode 100644
index 00000000..aee0d5c6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4558-drm-amdgpu-gfx10-fix-out-of-bound-mqd_backup-array-a.patch
@@ -0,0 +1,29 @@
+From 1a16172d56c6074979ca02624d4be10bf2089202 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 20 Nov 2019 14:38:00 +0800
+Subject: [PATCH 4558/4736] drm/amdgpu/gfx10: fix out-of-bound mqd_backup array
+ access
+
+Fixes: 4990f957c845 ("drm/amdgpu/gfx10: fix mqd backup/restore for gfx rings")
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+index a492174ef29b..52c27e49bc7b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+@@ -454,8 +454,6 @@ void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev)
+ 	}
+ 
+ 	ring = &adev->gfx.kiq.ring;
+-	if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring)
+-		kfree(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]);
+ 	kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
+ 	amdgpu_bo_free_kernel(&ring->mqd_obj,
+ 			      &ring->mqd_gpu_addr,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4559-drm-amdgpu-define-soc15_ras_field_entry-for-reuse.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4559-drm-amdgpu-define-soc15_ras_field_entry-for-reuse.patch
new file mode 100644
index 00000000..54b3d285
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4559-drm-amdgpu-define-soc15_ras_field_entry-for-reuse.patch
@@ -0,0 +1,118 @@
+From f126c8ac8a2ce8b49ac547adfc68deab63ec7a01 Mon Sep 17 00:00:00 2001
+From: Dennis Li <Dennis.Li@amd.com>
+Date: Tue, 19 Nov 2019 16:25:25 +0800
+Subject: [PATCH 4559/4736] drm/amdgpu: define soc15_ras_field_entry for reuse
+
+The struct soc15_ras_field_entry will be reused by
+other IPs, such as mmhub and gc
+
+v2: rename ras_subblock_regs to gc_ras_fields_vg20,
+because the future asic maybe have a different table.
+
+Change-Id: I6c3388a09b5fbf927ad90fcd626baa448d1681a6
+Signed-off-by: Dennis Li <Dennis.Li@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 34 +++++++++------------------
+ drivers/gpu/drm/amd/amdgpu/soc15.h    | 12 ++++++++++
+ 2 files changed, 23 insertions(+), 23 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 79cc4b95423b..2526159c467d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -127,18 +127,6 @@ MODULE_FIRMWARE("amdgpu/renoir_rlc.bin");
+ #define mmTCP_CHAN_STEER_5_ARCT								0x0b0c
+ #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX							0
+ 
+-struct ras_gfx_subblock_reg {
+-	const char *name;
+-	uint32_t hwip;
+-	uint32_t inst;
+-	uint32_t seg;
+-	uint32_t reg_offset;
+-	uint32_t sec_count_mask;
+-	uint32_t sec_count_shift;
+-	uint32_t ded_count_mask;
+-	uint32_t ded_count_shift;
+-};
+-
+ enum ta_ras_gfx_subblock {
+ 	/*CPC*/
+ 	TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
+@@ -5490,7 +5478,7 @@ static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
+ }
+ 
+ 
+-static const struct ras_gfx_subblock_reg ras_subblock_regs[] = {
++static const struct soc15_ras_field_entry gc_ras_fields_vg20[] = {
+ 	{ "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT),
+ 	  SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
+ 	  SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT)
+@@ -6149,29 +6137,29 @@ static int __get_ras_error_count(const struct soc15_reg_entry *reg,
+ 	uint32_t i;
+ 	uint32_t sec_cnt, ded_cnt;
+ 
+-	for (i = 0; i < ARRAY_SIZE(ras_subblock_regs); i++) {
+-		if(ras_subblock_regs[i].reg_offset != reg->reg_offset ||
+-			ras_subblock_regs[i].seg != reg->seg ||
+-			ras_subblock_regs[i].inst != reg->inst)
++	for (i = 0; i < ARRAY_SIZE(gc_ras_fields_vg20); i++) {
++		if(gc_ras_fields_vg20[i].reg_offset != reg->reg_offset ||
++			gc_ras_fields_vg20[i].seg != reg->seg ||
++			gc_ras_fields_vg20[i].inst != reg->inst)
+ 			continue;
+ 
+ 		sec_cnt = (value &
+-				ras_subblock_regs[i].sec_count_mask) >>
+-				ras_subblock_regs[i].sec_count_shift;
++				gc_ras_fields_vg20[i].sec_count_mask) >>
++				gc_ras_fields_vg20[i].sec_count_shift;
+ 		if (sec_cnt) {
+ 			DRM_INFO("GFX SubBlock %s, Instance[%d][%d], SEC %d\n",
+-				ras_subblock_regs[i].name,
++				gc_ras_fields_vg20[i].name,
+ 				se_id, inst_id,
+ 				sec_cnt);
+ 			*sec_count += sec_cnt;
+ 		}
+ 
+ 		ded_cnt = (value &
+-				ras_subblock_regs[i].ded_count_mask) >>
+-				ras_subblock_regs[i].ded_count_shift;
++				gc_ras_fields_vg20[i].ded_count_mask) >>
++				gc_ras_fields_vg20[i].ded_count_shift;
+ 		if (ded_cnt) {
+ 			DRM_INFO("GFX SubBlock %s, Instance[%d][%d], DED %d\n",
+-				ras_subblock_regs[i].name,
++				gc_ras_fields_vg20[i].name,
+ 				se_id, inst_id,
+ 				ded_cnt);
+ 			*ded_count += ded_cnt;
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
+index 9af6c6ffbfa2..344280b869c4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
+@@ -60,6 +60,18 @@ struct soc15_allowed_register_entry {
+ 	bool grbm_indexed;
+ };
+ 
++struct soc15_ras_field_entry {
++	const char *name;
++	uint32_t hwip;
++	uint32_t inst;
++	uint32_t seg;
++	uint32_t reg_offset;
++	uint32_t sec_count_mask;
++	uint32_t sec_count_shift;
++	uint32_t ded_count_mask;
++	uint32_t ded_count_shift;
++};
++
+ #define SOC15_REG_ENTRY(ip, inst, reg)	ip##_HWIP, inst, reg##_BASE_IDX, reg
+ 
+ #define SOC15_REG_ENTRY_OFFSET(entry)	(adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4560-drm-amdgpu-refine-query-function-of-mmhub-EDC-counte.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4560-drm-amdgpu-refine-query-function-of-mmhub-EDC-counte.patch
new file mode 100644
index 00000000..6fec2621
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4560-drm-amdgpu-refine-query-function-of-mmhub-EDC-counte.patch
@@ -0,0 +1,769 @@
+From 2a45b43ad84392eafa5b6b974534ad0358e6ca88 Mon Sep 17 00:00:00 2001
+From: Dennis Li <Dennis.Li@amd.com>
+Date: Tue, 19 Nov 2019 16:02:28 +0800
+Subject: [PATCH 4560/4736] drm/amdgpu: refine query function of mmhub EDC
+ counter in vg20
+
+Add codes to print the detail EDC info for the subblock of mmhub
+
+v2: Move the EDC_CNT registers' defintion from mmhub_9_4 header
+files to mmhub_1_0 ones. Add mmhub_v1_0_ prefix for the local
+static variable and function.
+
+Change-Id: I1d5b3df38caa8f0b437c96b78091662aaeaf264b
+Signed-off-by: Dennis Li <Dennis.Li@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c       | 232 ++++++++++++----
+ .../include/asic_reg/mmhub/mmhub_1_0_offset.h |  16 ++
+ .../asic_reg/mmhub/mmhub_1_0_sh_mask.h        | 122 +++++++++
+ .../asic_reg/mmhub/mmhub_9_4_0_offset.h       |  53 ----
+ .../asic_reg/mmhub/mmhub_9_4_0_sh_mask.h      | 257 ------------------
+ 5 files changed, 318 insertions(+), 362 deletions(-)
+ delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h
+ delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index 41c340bfc953..c0041d74df09 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -27,17 +27,13 @@
+ #include "mmhub/mmhub_1_0_offset.h"
+ #include "mmhub/mmhub_1_0_sh_mask.h"
+ #include "mmhub/mmhub_1_0_default.h"
+-#include "mmhub/mmhub_9_4_0_offset.h"
+ #include "vega10_enum.h"
+-
++#include "soc15.h"
+ #include "soc15_common.h"
+ 
+ #define mmDAGB0_CNTL_MISC2_RV 0x008f
+ #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
+ 
+-#define EA_EDC_CNT_MASK 0x3
+-#define EA_EDC_CNT_SHIFT 0x2
+-
+ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
+ {
+ 	u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);
+@@ -562,59 +558,191 @@ void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
+ 		*flags |= AMD_CG_SUPPORT_MC_LS;
+ }
+ 
++static const struct soc15_ras_field_entry mmhub_v1_0_ras_fields[] = {
++	{ "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_CMDMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_CMDMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_DATAMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_DATAMEM_DED_COUNT),
++	},
++	{ "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, RRET_TAGMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, RRET_TAGMEM_DED_COUNT),
++	},
++	{ "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, WRET_TAGMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, WRET_TAGMEM_DED_COUNT),
++	},
++	{ "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_PAGEMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_PAGEMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IORD_CMDMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IOWR_CMDMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IOWR_DATAMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_CMDMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_CMDMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_DATAMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_DATAMEM_DED_COUNT),
++	},
++	{ "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_PAGEMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_PAGEMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_CMDMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_CMDMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_DATAMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_DATAMEM_DED_COUNT),
++	},
++	{ "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, RRET_TAGMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, RRET_TAGMEM_DED_COUNT),
++	},
++	{ "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, WRET_TAGMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, WRET_TAGMEM_DED_COUNT),
++	},
++	{ "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_PAGEMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_PAGEMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IORD_CMDMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IOWR_CMDMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IOWR_DATAMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_CMDMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_CMDMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_DATAMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_DATAMEM_DED_COUNT),
++	},
++	{ "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_PAGEMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_PAGEMEM_SED_COUNT),
++	0, 0,
++	}
++};
++
++static const struct soc15_reg_entry mmhub_v1_0_edc_cnt_regs[] = {
++   { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 0, 0, 0},
++   { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 0, 0, 0},
++   { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 0, 0, 0},
++   { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 0, 0, 0},
++};
++
++static int mmhub_v1_0_get_ras_error_count(const struct soc15_reg_entry *reg,
++	uint32_t value, uint32_t *sec_count, uint32_t *ded_count)
++{
++	uint32_t i;
++	uint32_t sec_cnt, ded_cnt;
++
++	for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_ras_fields); i++) {
++		if(mmhub_v1_0_ras_fields[i].reg_offset != reg->reg_offset)
++			continue;
++
++		sec_cnt = (value &
++				mmhub_v1_0_ras_fields[i].sec_count_mask) >>
++				mmhub_v1_0_ras_fields[i].sec_count_shift;
++		if (sec_cnt) {
++			DRM_INFO("MMHUB SubBlock %s, SEC %d\n",
++				mmhub_v1_0_ras_fields[i].name,
++				sec_cnt);
++			*sec_count += sec_cnt;
++		}
++
++		ded_cnt = (value &
++				mmhub_v1_0_ras_fields[i].ded_count_mask) >>
++				mmhub_v1_0_ras_fields[i].ded_count_shift;
++		if (ded_cnt) {
++			DRM_INFO("MMHUB SubBlock %s, DED %d\n",
++				mmhub_v1_0_ras_fields[i].name,
++				ded_cnt);
++			*ded_count += ded_cnt;
++		}
++	}
++
++	return 0;
++}
++
+ static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev,
+ 					   void *ras_error_status)
+ {
+-	int i;
+-	uint32_t ea0_edc_cnt, ea0_edc_cnt2;
+-	uint32_t ea1_edc_cnt, ea1_edc_cnt2;
+ 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+-
+-	/* EDC CNT will be cleared automatically after read */
+-	ea0_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT_VG20);
+-	ea0_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20);
+-	ea1_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT_VG20);
+-	ea1_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20);
+-
+-	/* error count of each error type is recorded by 2 bits,
+-	 * ce and ue count in EDC_CNT
+-	 */
+-	for (i = 0; i < 5; i++) {
+-		err_data->ce_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
+-		err_data->ce_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
+-		ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
+-		ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
+-		err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
+-		err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
+-		ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
+-		ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
+-	}
+-	/* successive ue count in EDC_CNT */
+-	for (i = 0; i < 5; i++) {
+-		err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
+-		err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
+-		ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
+-		ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
++	uint32_t sec_count = 0, ded_count = 0;
++	uint32_t i;
++	uint32_t reg_value;
++
++	err_data->ue_count = 0;
++	err_data->ce_count = 0;
++
++	for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_edc_cnt_regs); i++) {
++		reg_value =
++			RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i]));
++		if (reg_value)
++			mmhub_v1_0_get_ras_error_count(&mmhub_v1_0_edc_cnt_regs[i],
++				reg_value, &sec_count, &ded_count);
+ 	}
+ 
+-	/* ce and ue count in EDC_CNT2 */
+-	for (i = 0; i < 3; i++) {
+-		err_data->ce_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
+-		err_data->ce_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
+-		ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
+-		ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
+-		err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
+-		err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
+-		ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
+-		ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
+-	}
+-	/* successive ue count in EDC_CNT2 */
+-	for (i = 0; i < 6; i++) {
+-		err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
+-		err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
+-		ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
+-		ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
+-	}
++	err_data->ce_count += sec_count;
++	err_data->ue_count += ded_count;
+ }
+ 
+ const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h
+index 352ffae7a7ca..2c3ce243861a 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h
+@@ -1964,4 +1964,20 @@
+ #define mmATC_L2_PERFCOUNTER_RSLT_CNTL                                                                 0x084a
+ #define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                        0
+ 
++/* MMEA */
++#define mmMMEA0_EDC_CNT_VG20                                                                           0x0206
++#define mmMMEA0_EDC_CNT_VG20_BASE_IDX                                                                  0
++#define mmMMEA0_EDC_CNT2_VG20                                                                          0x0207
++#define mmMMEA0_EDC_CNT2_VG20_BASE_IDX                                                                 0
++#define mmMMEA1_EDC_CNT_VG20                                                                           0x0346
++#define mmMMEA1_EDC_CNT_VG20_BASE_IDX                                                                  0
++#define mmMMEA1_EDC_CNT2_VG20                                                                          0x0347
++#define mmMMEA1_EDC_CNT2_VG20_BASE_IDX                                                                 0
++
++// addressBlock: mmhub_utcl2_vmsharedpfdec
++// base address: 0x6a040
++#define mmMC_VM_XGMI_LFB_CNTL                                                                          0x0823
++#define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX                                                                 0
++#define mmMC_VM_XGMI_LFB_SIZE                                                                          0x0824
++#define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX                                                                 0
+ #endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h
+index 34278ef2aa1b..198f5f93ed1a 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h
+@@ -10124,4 +10124,126 @@
+ #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                          0x02000000L
+ #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                               0x04000000L
+ 
++//MMEA0_EDC_CNT
++#define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
++#define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
++#define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
++#define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
++#define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
++#define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
++#define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
++#define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
++#define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
++#define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
++#define MMEA0_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
++#define MMEA0_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
++#define MMEA0_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
++#define MMEA0_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
++#define MMEA0_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
++#define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
++#define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
++#define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
++#define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
++#define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
++#define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
++#define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
++#define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
++#define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
++#define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
++#define MMEA0_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
++#define MMEA0_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
++#define MMEA0_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
++#define MMEA0_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
++#define MMEA0_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
++//MMEA0_EDC_CNT2
++#define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
++#define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
++#define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
++#define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
++#define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
++#define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
++#define MMEA0_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
++#define MMEA0_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
++#define MMEA0_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT__SHIFT                                                            0x10
++#define MMEA0_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT__SHIFT                                                            0x12
++#define MMEA0_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT__SHIFT                                                            0x14
++#define MMEA0_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT__SHIFT                                                            0x16
++#define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
++#define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
++#define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
++#define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
++#define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
++#define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
++#define MMEA0_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
++#define MMEA0_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
++#define MMEA0_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT_MASK                                                              0x00030000L
++#define MMEA0_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT_MASK                                                              0x000C0000L
++#define MMEA0_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT_MASK                                                              0x00300000L
++#define MMEA0_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT_MASK                                                              0x00C00000L
++//MMEA1_EDC_CNT
++#define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
++#define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
++#define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
++#define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
++#define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
++#define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
++#define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
++#define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
++#define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
++#define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
++#define MMEA1_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
++#define MMEA1_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
++#define MMEA1_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
++#define MMEA1_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
++#define MMEA1_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
++#define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
++#define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
++#define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
++#define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
++#define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
++#define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
++#define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
++#define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
++#define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
++#define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
++#define MMEA1_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
++#define MMEA1_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
++#define MMEA1_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
++#define MMEA1_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
++#define MMEA1_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
++//MMEA1_EDC_CNT2
++#define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
++#define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
++#define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
++#define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
++#define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
++#define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
++#define MMEA1_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
++#define MMEA1_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
++#define MMEA1_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT__SHIFT                                                            0x10
++#define MMEA1_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT__SHIFT                                                            0x12
++#define MMEA1_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT__SHIFT                                                            0x14
++#define MMEA1_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT__SHIFT                                                            0x16
++#define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
++#define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
++#define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
++#define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
++#define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
++#define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
++#define MMEA1_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
++#define MMEA1_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
++#define MMEA1_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT_MASK                                                              0x00030000L
++#define MMEA1_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT_MASK                                                              0x000C0000L
++#define MMEA1_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT_MASK                                                              0x00300000L
++#define MMEA1_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT_MASK                                                              0x00C00000L
++
++// addressBlock: mmhub_utcl2_vmsharedpfdec
++//MC_VM_XGMI_LFB_CNTL
++#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT                                                             0x0
++#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT                                                             0x4
++#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK                                                               0x00000007L
++#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK                                                               0x00000070L
++//MC_VM_XGMI_LFB_SIZE
++#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT                                                               0x0
++#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK                                                                 0x0000FFFFL
+ #endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h
+deleted file mode 100644
+index f2ae3a58949e..000000000000
+--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h
++++ /dev/null
+@@ -1,53 +0,0 @@
+-/*
+- * Copyright (C) 2018  Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included
+- * in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+- */
+-#ifndef _mmhub_9_4_0_OFFSET_HEADER
+-#define _mmhub_9_4_0_OFFSET_HEADER
+-
+-/* MMEA */
+-#define mmMMEA0_SDP_ARB_FINAL_VG20                                                                     0x01ee
+-#define mmMMEA0_SDP_ARB_FINAL_VG20_BASE_IDX                                                            0
+-#define mmMMEA0_EDC_CNT_VG20                                                                           0x0206
+-#define mmMMEA0_EDC_CNT_VG20_BASE_IDX                                                                  0
+-#define mmMMEA0_EDC_CNT2_VG20                                                                          0x0207
+-#define mmMMEA0_EDC_CNT2_VG20_BASE_IDX                                                                 0
+-#define mmMMEA0_EDC_MODE_VG20                                                                          0x0210
+-#define mmMMEA0_EDC_MODE_VG20_BASE_IDX                                                                 0
+-#define mmMMEA0_ERR_STATUS_VG20                                                                        0x0211
+-#define mmMMEA0_ERR_STATUS_VG20_BASE_IDX                                                               0
+-#define mmMMEA1_SDP_ARB_FINAL_VG20                                                                     0x032e
+-#define mmMMEA1_SDP_ARB_FINAL_VG20_BASE_IDX                                                            0
+-#define mmMMEA1_EDC_CNT_VG20                                                                           0x0346
+-#define mmMMEA1_EDC_CNT_VG20_BASE_IDX                                                                  0
+-#define mmMMEA1_EDC_CNT2_VG20                                                                          0x0347
+-#define mmMMEA1_EDC_CNT2_VG20_BASE_IDX                                                                 0
+-#define mmMMEA1_EDC_MODE_VG20                                                                          0x0350
+-#define mmMMEA1_EDC_MODE_VG20_BASE_IDX                                                                 0
+-#define mmMMEA1_ERR_STATUS_VG20                                                                        0x0351
+-#define mmMMEA1_ERR_STATUS_VG20_BASE_IDX                                                               0
+-
+-// addressBlock: mmhub_utcl2_vmsharedpfdec
+-// base address: 0x6a040
+-#define mmMC_VM_XGMI_LFB_CNTL                                                                          0x0823
+-#define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX                                                                 0
+-#define mmMC_VM_XGMI_LFB_SIZE                                                                          0x0824
+-#define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX                                                                 0
+-
+-#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h
+deleted file mode 100644
+index c24259ed12a1..000000000000
+--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h
++++ /dev/null
+@@ -1,257 +0,0 @@
+-/*
+- * Copyright (C) 2018  Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included
+- * in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+- */
+-#ifndef _mmhub_9_4_0_SH_MASK_HEADER
+-#define _mmhub_9_4_0_SH_MASK_HEADER
+-
+-//MMEA0_SDP_ARB_FINAL
+-#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
+-#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
+-#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
+-#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
+-#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
+-#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
+-#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
+-#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
+-#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
+-#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
+-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
+-#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
+-#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
+-//MMEA0_EDC_CNT
+-#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
+-#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
+-#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
+-#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
+-#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
+-#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
+-#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
+-#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
+-#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
+-#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
+-#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
+-#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
+-#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
+-#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
+-#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
+-#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
+-#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
+-#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
+-#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
+-#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
+-#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
+-#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
+-#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
+-#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
+-#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
+-#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
+-#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
+-#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
+-#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
+-#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
+-//MMEA0_EDC_CNT2
+-#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
+-#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
+-#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
+-#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
+-#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
+-#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
+-#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
+-#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
+-#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT                                                            0x10
+-#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT                                                            0x12
+-#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT                                                            0x14
+-#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT                                                            0x16
+-#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
+-#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
+-#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
+-#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
+-#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
+-#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
+-#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
+-#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
+-#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK                                                              0x00030000L
+-#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK                                                              0x000C0000L
+-#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK                                                              0x00300000L
+-#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK                                                              0x00C00000L
+-//MMEA0_EDC_MODE
+-#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
+-#define MMEA0_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
+-#define MMEA0_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
+-#define MMEA0_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
+-#define MMEA0_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
+-#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
+-#define MMEA0_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
+-#define MMEA0_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
+-#define MMEA0_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
+-#define MMEA0_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
+-//MMEA0_ERR_STATUS
+-#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
+-#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
+-#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
+-#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
+-#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
+-#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
+-#define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
+-#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
+-#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
+-#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
+-#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
+-#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
+-#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
+-#define MMEA0_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
+-//MMEA1_SDP_ARB_FINAL
+-#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
+-#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
+-#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
+-#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
+-#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
+-#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
+-#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
+-#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
+-#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
+-#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
+-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
+-#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
+-#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
+-//MMEA1_EDC_CNT
+-#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
+-#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
+-#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
+-#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
+-#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
+-#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
+-#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
+-#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
+-#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
+-#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
+-#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
+-#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
+-#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
+-#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
+-#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
+-#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
+-#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
+-#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
+-#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
+-#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
+-#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
+-#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
+-#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
+-#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
+-#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
+-#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
+-#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
+-#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
+-#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
+-#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
+-//MMEA1_EDC_CNT2
+-#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
+-#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
+-#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
+-#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
+-#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
+-#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
+-#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
+-#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
+-#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT                                                            0x10
+-#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT                                                            0x12
+-#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT                                                            0x14
+-#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT                                                            0x16
+-#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
+-#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
+-#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
+-#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
+-#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
+-#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
+-#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
+-#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
+-#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK                                                              0x00030000L
+-#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK                                                              0x000C0000L
+-#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK                                                              0x00300000L
+-#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK                                                              0x00C00000L
+-//MMEA1_EDC_MODE
+-#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
+-#define MMEA1_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
+-#define MMEA1_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
+-#define MMEA1_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
+-#define MMEA1_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
+-#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
+-#define MMEA1_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
+-#define MMEA1_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
+-#define MMEA1_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
+-#define MMEA1_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
+-//MMEA1_ERR_STATUS
+-#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
+-#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
+-#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
+-#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
+-#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
+-#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
+-#define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
+-#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
+-#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
+-#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
+-#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
+-#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
+-#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
+-#define MMEA1_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
+-
+-// addressBlock: mmhub_utcl2_vmsharedpfdec
+-//MC_VM_XGMI_LFB_CNTL
+-#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT                                                             0x0
+-#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT                                                             0x4
+-#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK                                                               0x00000007L
+-#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK                                                               0x00000070L
+-//MC_VM_XGMI_LFB_SIZE
+-#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT                                                               0x0
+-#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK                                                                 0x0000FFFFL
+-
+-#endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4561-drm-amdgpu-implement-querying-ras-error-count-for-mm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4561-drm-amdgpu-implement-querying-ras-error-count-for-mm.patch
new file mode 100644
index 00000000..e5869717
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4561-drm-amdgpu-implement-querying-ras-error-count-for-mm.patch
@@ -0,0 +1,326 @@
+From 073f2de5b3fb3e5cd72a778097df09ad875f769f Mon Sep 17 00:00:00 2001
+From: Dennis Li <Dennis.Li@amd.com>
+Date: Tue, 19 Nov 2019 14:02:57 +0800
+Subject: [PATCH 4561/4736] drm/amdgpu: implement querying ras error count for
+ mmhub9.4
+
+Get mmhub error counter by accessing EDC_CNT registers.
+
+v2: Add mmhub_v9_4_ prefix for local static variable and function
+
+Change-Id: I728d4183a08707aaf0fc71d184e86322a681e725
+Signed-off-by: Dennis Li <Dennis.Li@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |   3 +
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 253 +++++++++++++++++++++++-
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h |   2 +
+ 3 files changed, 257 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index db4582925b8d..992ecc74ea38 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -654,6 +654,9 @@ static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
+ 	case CHIP_VEGA20:
+ 		adev->mmhub.funcs = &mmhub_v1_0_funcs;
+ 		break;
++	case CHIP_ARCTURUS:
++		adev->mmhub.funcs = &mmhub_v9_4_funcs;
++		break;
+ 	default:
+ 		break;
+ 	}
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+index 2c5adfe803a2..6fe5c39e5581 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+@@ -21,6 +21,7 @@
+  *
+  */
+ #include "amdgpu.h"
++#include "amdgpu_ras.h"
+ #include "mmhub_v9_4.h"
+ 
+ #include "mmhub/mmhub_9_4_1_offset.h"
+@@ -29,7 +30,7 @@
+ #include "athub/athub_1_0_offset.h"
+ #include "athub/athub_1_0_sh_mask.h"
+ #include "vega10_enum.h"
+-
++#include "soc15.h"
+ #include "soc15_common.h"
+ 
+ #define MMHUB_NUM_INSTANCES			2
+@@ -651,3 +652,253 @@ void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags)
+ 	if (data & ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
+ 		*flags |= AMD_CG_SUPPORT_MC_LS;
+ }
++
++static const struct soc15_ras_field_entry mmhub_v9_4_ras_fields[] = {
++	{ "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
++	},
++	{ "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_DED_COUNT),
++	},
++	{ "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_DED_COUNT),
++	},
++	{ "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT, IORD_CMDMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
++	},
++	{ "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
++	SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
++	0, 0,
++	SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
++	},
++	{ "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
++	0, 0,
++	SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
++	},
++	{ "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
++	0, 0,
++	SOC15_REG_FIELD(MMEA0_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
++	0, 0,
++	SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
++	0, 0,
++	SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
++	},
++	{ "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
++	0, 0,
++	SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
++	},
++	{ "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
++	0, 0,
++	SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
++	},
++	{ "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
++	},
++	{ "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_DED_COUNT),
++	},
++	{ "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_DED_COUNT),
++	},
++	{ "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT, IORD_CMDMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
++	},
++	{ "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
++	SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
++	0, 0,
++	},
++	{ "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
++	0, 0,
++	SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
++	},
++	{ "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
++	0, 0,
++	SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
++	},
++	{ "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
++	0, 0,
++	SOC15_REG_FIELD(MMEA1_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
++	0, 0,
++	SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
++	},
++	{ "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
++	0, 0,
++	SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
++	},
++	{ "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
++	0, 0,
++	SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
++	},
++	{ "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
++	0, 0,
++	SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
++	}
++};
++
++static const struct soc15_reg_entry mmhub_v9_4_edc_cnt_regs[] = {
++   { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 0, 0, 0},
++   { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 0, 0, 0},
++   { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 0, 0, 0},
++   { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 0, 0, 0},
++   { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 0, 0, 0},
++   { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 0, 0, 0},
++};
++
++static int mmhub_v9_4_get_ras_error_count(const struct soc15_reg_entry *reg,
++	uint32_t value, uint32_t *sec_count, uint32_t *ded_count)
++{
++	uint32_t i;
++	uint32_t sec_cnt, ded_cnt;
++
++	for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_ras_fields); i++) {
++		if(mmhub_v9_4_ras_fields[i].reg_offset != reg->reg_offset)
++			continue;
++
++		sec_cnt = (value &
++				mmhub_v9_4_ras_fields[i].sec_count_mask) >>
++				mmhub_v9_4_ras_fields[i].sec_count_shift;
++		if (sec_cnt) {
++			DRM_INFO("MMHUB SubBlock %s, SEC %d\n",
++				mmhub_v9_4_ras_fields[i].name,
++				sec_cnt);
++			*sec_count += sec_cnt;
++		}
++
++		ded_cnt = (value &
++				mmhub_v9_4_ras_fields[i].ded_count_mask) >>
++				mmhub_v9_4_ras_fields[i].ded_count_shift;
++		if (ded_cnt) {
++			DRM_INFO("MMHUB SubBlock %s, DED %d\n",
++				mmhub_v9_4_ras_fields[i].name,
++				ded_cnt);
++			*ded_count += ded_cnt;
++		}
++	}
++
++	return 0;
++}
++
++static void mmhub_v9_4_query_ras_error_count(struct amdgpu_device *adev,
++					   void *ras_error_status)
++{
++	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
++	uint32_t sec_count = 0, ded_count = 0;
++	uint32_t i;
++	uint32_t reg_value;
++
++	err_data->ue_count = 0;
++	err_data->ce_count = 0;
++
++	for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++) {
++		reg_value =
++			RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
++		if (reg_value)
++			mmhub_v9_4_get_ras_error_count(&mmhub_v9_4_edc_cnt_regs[i],
++				reg_value, &sec_count, &ded_count);
++	}
++
++	err_data->ce_count += sec_count;
++	err_data->ue_count += ded_count;
++}
++
++const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs = {
++	.ras_late_init = amdgpu_mmhub_ras_late_init,
++	.query_ras_error_count = mmhub_v9_4_query_ras_error_count,
++};
+\ No newline at end of file
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
+index d435cfcec1a8..354a4b7e875b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
+@@ -23,6 +23,8 @@
+ #ifndef __MMHUB_V9_4_H__
+ #define __MMHUB_V9_4_H__
+ 
++extern const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs;
++
+ u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev);
+ int mmhub_v9_4_gart_enable(struct amdgpu_device *adev);
+ void mmhub_v9_4_gart_disable(struct amdgpu_device *adev);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4562-drm-amdgpu-Update-Arcturus-golden-registers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4562-drm-amdgpu-Update-Arcturus-golden-registers.patch
new file mode 100644
index 00000000..59f0b789
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4562-drm-amdgpu-Update-Arcturus-golden-registers.patch
@@ -0,0 +1,26 @@
+From 1d650ef1104521cb6f855f77a98488714d04086d Mon Sep 17 00:00:00 2001
+From: Jay Cornwall <jay.cornwall@amd.com>
+Date: Wed, 20 Nov 2019 16:32:46 +0000
+Subject: [PATCH 4562/4736] drm/amdgpu: Update Arcturus golden registers
+
+Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 2526159c467d..0932e4a7c63c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -688,6 +688,7 @@ static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] =
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00),
+ };
+ 
+ static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4563-drm-amd-display-Change-mmhub_9_4_0_-headers-to-mmhub.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4563-drm-amd-display-Change-mmhub_9_4_0_-headers-to-mmhub.patch
new file mode 100644
index 00000000..1c0b8204
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4563-drm-amd-display-Change-mmhub_9_4_0_-headers-to-mmhub.patch
@@ -0,0 +1,39 @@
+From 8b92f281daaefb0e0c265784505e38a6afa8bac3 Mon Sep 17 00:00:00 2001
+From: Zhan Liu <zhan.liu@amd.com>
+Date: Wed, 20 Nov 2019 14:35:37 -0500
+Subject: [PATCH 4563/4736] drm/amd/display: Change mmhub_9_4_0_ headers to
+ mmhub_1_0_ ones.
+
+[Why]
+Kernal won't compile without this patch. That is because
+mmhub_9_4_0_ headers are obsolete. All contents within
+mmhub_9_4_0_ headers are inherited by their corresponding
+mmhub_1_0_ ones.
+
+[How]
+Change mmhub_9_4_0_ headers to their corresponding mmhub_1_0_ ones.
+
+Signed-off-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index e9157583817f..b00d17cade1a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -61,8 +61,8 @@
+ #include "soc15_hw_ip.h"
+ #include "vega10_ip_offset.h"
+ #include "nbio/nbio_6_1_offset.h"
+-#include "mmhub/mmhub_9_4_0_offset.h"
+-#include "mmhub/mmhub_9_4_0_sh_mask.h"
++#include "mmhub/mmhub_1_0_offset.h"
++#include "mmhub/mmhub_1_0_sh_mask.h"
+ #include "reg_helper.h"
+ 
+ #include "dce100/dce100_resource.h"
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4564-drm-amdkfd-Delete-KFD_MQD_TYPE_COMPUTE.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4564-drm-amdkfd-Delete-KFD_MQD_TYPE_COMPUTE.patch
new file mode 100644
index 00000000..9645f0b2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4564-drm-amdkfd-Delete-KFD_MQD_TYPE_COMPUTE.patch
@@ -0,0 +1,125 @@
+From 6a0c2a06d1a5df450573d6f35c258770b01480d3 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 8 Nov 2019 23:57:37 -0500
+Subject: [PATCH 4564/4736] drm/amdkfd: Delete KFD_MQD_TYPE_COMPUTE
+
+It is the same as KFD_MQD_TYPE_CP, so delete it. As a result, we will
+have one less mqd mananger per device.
+
+Change-Id: Iaa98fc17be06b216de7a826c3577f44bc0536b4c
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 4 ++--
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c      | 3 +--
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c      | 1 -
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c       | 1 -
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c       | 3 +--
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h                 | 3 +--
+ 6 files changed, 5 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 0ec9370976d9..67a364ecf8c8 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -1744,7 +1744,7 @@ static int get_wave_state(struct device_queue_manager *dqm,
+ 		goto dqm_unlock;
+ 	}
+ 
+-	mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_COMPUTE];
++	mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
+ 
+ 	if (!mqd_mgr->get_wave_state) {
+ 		r = -EINVAL;
+@@ -2187,7 +2187,7 @@ void copy_context_work_handler (struct work_struct *work)
+ 
+ 
+ 		list_for_each_entry(q, &qpd->queues_list, list) {
+-			mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_COMPUTE];
++			mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
+ 
+ 			/* We ignore the return value from get_wave_state
+ 			 * because
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+index 9431dc2ca54b..3f2220442bd9 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+@@ -403,7 +403,6 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
+ 
+ 	switch (type) {
+ 	case KFD_MQD_TYPE_CP:
+-	case KFD_MQD_TYPE_COMPUTE:
+ 		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd;
+ 		mqd->free_mqd = free_mqd;
+@@ -475,7 +474,7 @@ struct mqd_manager *mqd_manager_init_cik_hawaii(enum KFD_MQD_TYPE type,
+ 	mqd = mqd_manager_init_cik(type, dev);
+ 	if (!mqd)
+ 		return NULL;
+-	if ((type == KFD_MQD_TYPE_CP) || (type == KFD_MQD_TYPE_COMPUTE))
++	if (type == KFD_MQD_TYPE_CP)
+ 		mqd->update_mqd = update_mqd_hawaii;
+ 	return mqd;
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index 65a03d1d79db..b132bf301c63 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -401,7 +401,6 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+ 
+ 	switch (type) {
+ 	case KFD_MQD_TYPE_CP:
+-	case KFD_MQD_TYPE_COMPUTE:
+ 		pr_debug("%s@%i\n", __func__, __LINE__);
+ 		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index 822747377c28..76ad9a0891e6 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -528,7 +528,6 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
+ 
+ 	switch (type) {
+ 	case KFD_MQD_TYPE_CP:
+-	case KFD_MQD_TYPE_COMPUTE:
+ 		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd;
+ 		mqd->free_mqd = free_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+index 39c9b470e227..c93835fb6414 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+@@ -466,7 +466,6 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
+ 
+ 	switch (type) {
+ 	case KFD_MQD_TYPE_CP:
+-	case KFD_MQD_TYPE_COMPUTE:
+ 		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd;
+ 		mqd->free_mqd = free_mqd;
+@@ -539,7 +538,7 @@ struct mqd_manager *mqd_manager_init_vi_tonga(enum KFD_MQD_TYPE type,
+ 	mqd = mqd_manager_init_vi(type, dev);
+ 	if (!mqd)
+ 		return NULL;
+-	if ((type == KFD_MQD_TYPE_CP) || (type == KFD_MQD_TYPE_COMPUTE))
++	if (type == KFD_MQD_TYPE_CP)
+ 		mqd->update_mqd = update_mqd_tonga;
+ 	return mqd;
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index e937679f8ca1..b91029047953 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -576,8 +576,7 @@ struct queue {
+  * Please read the kfd_mqd_manager.h description.
+  */
+ enum KFD_MQD_TYPE {
+-	KFD_MQD_TYPE_COMPUTE = 0,	/* for no cp scheduling */
+-	KFD_MQD_TYPE_HIQ,		/* for hiq */
++	KFD_MQD_TYPE_HIQ = 0,		/* for hiq */
+ 	KFD_MQD_TYPE_CP,		/* for cp queues and diq */
+ 	KFD_MQD_TYPE_SDMA,		/* for sdma queues */
+ 	KFD_MQD_TYPE_DIQ,		/* for diq */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4565-drm-amdkfd-DIQ-should-not-use-HIQ-way-to-allocate-me.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4565-drm-amdkfd-DIQ-should-not-use-HIQ-way-to-allocate-me.patch
new file mode 100644
index 00000000..b2fe1e67
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4565-drm-amdkfd-DIQ-should-not-use-HIQ-way-to-allocate-me.patch
@@ -0,0 +1,74 @@
+From 033aff03c39979d2f714a32967091297854d34ea Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Sat, 9 Nov 2019 00:47:31 -0500
+Subject: [PATCH 4565/4736] drm/amdkfd: DIQ should not use HIQ way to allocate
+ memory
+
+In the mqd_diq_sdma buffer, there should be only one HIQ mqd. All DIQs
+should be allocated somewhere else using the regular way.
+
+Change-Id: Ibf3eb33604d0ec30501c244228cdb3b24615b699
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Oak Zeng <Oak.Zeng@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c  | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c  | 2 +-
+ 4 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+index 3f2220442bd9..37ce9571a175 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+@@ -431,7 +431,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
+ #endif
+ 		break;
+ 	case KFD_MQD_TYPE_DIQ:
+-		mqd->allocate_mqd = allocate_hiq_mqd;
++		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd_hiq;
+ 		mqd->free_mqd = free_mqd;
+ 		mqd->load_mqd = load_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index b132bf301c63..1e83abacf248 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -432,7 +432,7 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+ 		pr_debug("%s@%i\n", __func__, __LINE__);
+ 		break;
+ 	case KFD_MQD_TYPE_DIQ:
+-		mqd->allocate_mqd = allocate_hiq_mqd;
++		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd_hiq;
+ 		mqd->free_mqd = free_mqd;
+ 		mqd->load_mqd = load_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index 76ad9a0891e6..59f75b169459 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -557,7 +557,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
+ #endif
+ 		break;
+ 	case KFD_MQD_TYPE_DIQ:
+-		mqd->allocate_mqd = allocate_hiq_mqd;
++		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd_hiq;
+ 		mqd->free_mqd = free_mqd;
+ 		mqd->load_mqd = load_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+index c93835fb6414..f71679443300 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+@@ -495,7 +495,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
+ #endif
+ 		break;
+ 	case KFD_MQD_TYPE_DIQ:
+-		mqd->allocate_mqd = allocate_hiq_mqd;
++		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd_hiq;
+ 		mqd->free_mqd = free_mqd;
+ 		mqd->load_mqd = load_mqd;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4566-drm-amdgpu-initialize-vm_inv_eng0_sem-for-gfxhub-and.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4566-drm-amdgpu-initialize-vm_inv_eng0_sem-for-gfxhub-and.patch
new file mode 100644
index 00000000..96ada6d2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4566-drm-amdgpu-initialize-vm_inv_eng0_sem-for-gfxhub-and.patch
@@ -0,0 +1,109 @@
+From 36664bd1742e7a463222014761d07eea7e19261b Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Tue, 19 Nov 2019 10:18:39 +0800
+Subject: [PATCH 4566/4736] drm/amdgpu: initialize vm_inv_eng0_sem for gfxhub
+ and mmhub
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+SW must acquire/release one of the vm_invalidate_eng*_sem around the
+invalidation req/ack. Through this way,it can avoid losing invalidate
+acknowledge state across power-gating off cycle.
+To use vm_invalidate_eng*_sem, it needs to initialize
+vm_invalidate_eng*_sem firstly.
+
+Change-Id: I9f73b18c5c1f75d3195a6f5c448f71060ce0ab25
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h  | 1 +
+ drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 ++
+ drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 2 ++
+ drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 2 ++
+ drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c  | 2 ++
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c  | 4 ++++
+ 6 files changed, 13 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+index 02bbb571756a..cee7e8ae214f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+@@ -77,6 +77,7 @@ struct amdgpu_gmc_fault {
+ struct amdgpu_vmhub {
+ 	uint32_t	ctx0_ptb_addr_lo32;
+ 	uint32_t	ctx0_ptb_addr_hi32;
++	uint32_t	vm_inv_eng0_sem;
+ 	uint32_t	vm_inv_eng0_req;
+ 	uint32_t	vm_inv_eng0_ack;
+ 	uint32_t	vm_context0_cntl;
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+index db8baf733508..2c8a542cbd94 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+@@ -367,6 +367,8 @@ void gfxhub_v1_0_init(struct amdgpu_device *adev)
+ 	hub->ctx0_ptb_addr_hi32 =
+ 		SOC15_REG_OFFSET(GC, 0,
+ 				 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
++	hub->vm_inv_eng0_sem =
++		SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM);
+ 	hub->vm_inv_eng0_req =
+ 		SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
+ 	hub->vm_inv_eng0_ack =
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+index b4f32d853ca1..b70c7b483c24 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+@@ -356,6 +356,8 @@ void gfxhub_v2_0_init(struct amdgpu_device *adev)
+ 	hub->ctx0_ptb_addr_hi32 =
+ 		SOC15_REG_OFFSET(GC, 0,
+ 				 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
++	hub->vm_inv_eng0_sem =
++		SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
+ 	hub->vm_inv_eng0_req =
+ 		SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
+ 	hub->vm_inv_eng0_ack =
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+index c0041d74df09..cc4947afa34d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+@@ -416,6 +416,8 @@ void mmhub_v1_0_init(struct amdgpu_device *adev)
+ 	hub->ctx0_ptb_addr_hi32 =
+ 		SOC15_REG_OFFSET(MMHUB, 0,
+ 				 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
++	hub->vm_inv_eng0_sem =
++		SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_SEM);
+ 	hub->vm_inv_eng0_req =
+ 		SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ);
+ 	hub->vm_inv_eng0_ack =
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+index 945533634711..a7cb185d639a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+@@ -348,6 +348,8 @@ void mmhub_v2_0_init(struct amdgpu_device *adev)
+ 	hub->ctx0_ptb_addr_hi32 =
+ 		SOC15_REG_OFFSET(MMHUB, 0,
+ 				 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
++	hub->vm_inv_eng0_sem =
++		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_SEM);
+ 	hub->vm_inv_eng0_req =
+ 		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
+ 	hub->vm_inv_eng0_ack =
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+index 6fe5c39e5581..753eea25b569 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+@@ -505,6 +505,10 @@ void mmhub_v9_4_init(struct amdgpu_device *adev)
+ 			SOC15_REG_OFFSET(MMHUB, 0,
+ 			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) +
+ 			    i * MMHUB_INSTANCE_REGISTER_OFFSET;
++		hub[i]->vm_inv_eng0_sem =
++			SOC15_REG_OFFSET(MMHUB, 0,
++					 mmVML2VC0_VM_INVALIDATE_ENG0_SEM) +
++					 i * MMHUB_INSTANCE_REGISTER_OFFSET;
+ 		hub[i]->vm_inv_eng0_req =
+ 			SOC15_REG_OFFSET(MMHUB, 0,
+ 					 mmVML2VC0_VM_INVALIDATE_ENG0_REQ) +
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4567-drm-amdgpu-simplify-runtime-suspend.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4567-drm-amdgpu-simplify-runtime-suspend.patch
new file mode 100644
index 00000000..ba5d8b73
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4567-drm-amdgpu-simplify-runtime-suspend.patch
@@ -0,0 +1,77 @@
+From d01273461600fcd798305122d28fec38aa5e2773 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 20 Nov 2019 14:20:32 -0500
+Subject: [PATCH 4567/4736] drm/amdgpu: simplify runtime suspend
+
+In the standard _PR3 case, the pci core handles the pci state.
+The driver only needs to handle it in the legacy ATPX case.
+
+This may fix issues with runtime suspend/resume on certain
+hybrid graphics laptops.
+
+Change-Id: Ifa10d4905a885132c9f8d1168eac5bbd550d1ceb
+Acked-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 35 ++++++++++++++++---------
+ 1 file changed, 22 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 6957ef4ef514..4ca9b9bde917 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1261,13 +1261,17 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)
+ 
+ 	ret = amdgpu_device_suspend(drm_dev, false, false);
+ 	if (amdgpu_device_supports_boco(drm_dev)) {
+-		pci_save_state(pdev);
+-		pci_disable_device(pdev);
+-		pci_ignore_hotplug(pdev);
+-		if (amdgpu_is_atpx_hybrid())
++		/* Only need to handle PCI state in the driver for ATPX
++		 * PCI core handles it for _PR3.
++		 */
++		if (amdgpu_is_atpx_hybrid()) {
++			pci_ignore_hotplug(pdev);
++		} else {
++			pci_save_state(pdev);
++			pci_disable_device(pdev);
++			pci_ignore_hotplug(pdev);
+ 			pci_set_power_state(pdev, PCI_D3cold);
+-		else if (!amdgpu_has_atpx_dgpu_power_cntl())
+-			pci_set_power_state(pdev, PCI_D3hot);
++		}
+ 		drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
+ 	} else if (amdgpu_device_supports_baco(drm_dev)) {
+ 		amdgpu_device_baco_enter(drm_dev);
+@@ -1289,14 +1293,19 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
+ 	if (amdgpu_device_supports_boco(drm_dev)) {
+ 		drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+ 
+-		if (amdgpu_is_atpx_hybrid() ||
+-	    	!amdgpu_has_atpx_dgpu_power_cntl())
++  		/* Only need to handle PCI state in the driver for ATPX
++		 * PCI core handles it for _PR3.
++		 */
++		if (amdgpu_is_atpx_hybrid()) {
++			pci_set_master(pdev);
++		} else {
+ 			pci_set_power_state(pdev, PCI_D0);
+-		pci_restore_state(pdev);
+-		ret = pci_enable_device(pdev);
+-		if (ret)
+-			return ret;
+-		pci_set_master(pdev);
++			pci_restore_state(pdev);
++			ret = pci_enable_device(pdev);
++			if (ret)
++				return ret;
++			pci_set_master(pdev);
++		}
+ 	} else if (amdgpu_device_supports_baco(drm_dev)) {
+ 		amdgpu_device_baco_exit(drm_dev);
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4568-drm-amdgpu-remove-redundant-assignment-to-pointer-wr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4568-drm-amdgpu-remove-redundant-assignment-to-pointer-wr.patch
new file mode 100644
index 00000000..f3c29ec3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4568-drm-amdgpu-remove-redundant-assignment-to-pointer-wr.patch
@@ -0,0 +1,34 @@
+From 4af3b4fd4a39d70100720cd8fb796728e592044f Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Thu, 21 Nov 2019 16:54:01 +0000
+Subject: [PATCH 4568/4736] drm/amdgpu: remove redundant assignment to pointer
+ write_frame
+
+The pointer write_frame is being initialized with a value that is
+never read and it is being updated later with a new value. The
+initialization is redundant and can be removed.
+
+Change-Id: Iaa3ee0742a108d292b38ac4727bf7434c8103668
+Addresses-Coverity: ("Unused value")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 4ba444baf6db..b9922a5f6890 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1730,7 +1730,7 @@ int psp_ring_cmd_submit(struct psp_context *psp,
+ 			int index)
+ {
+ 	unsigned int psp_write_ptr_reg = 0;
+-	struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
++	struct psp_gfx_rb_frame *write_frame;
+ 	struct psp_ring *ring = &psp->km_ring;
+ 	struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
+ 	struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4569-Revert-drm-amdgpu-gfx10-re-init-clear-state-buffer-a.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4569-Revert-drm-amdgpu-gfx10-re-init-clear-state-buffer-a.patch
new file mode 100644
index 00000000..ae81cd1e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4569-Revert-drm-amdgpu-gfx10-re-init-clear-state-buffer-a.patch
@@ -0,0 +1,104 @@
+From 485b768977869e07005145ec36e59c97ea358090 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Fri, 22 Nov 2019 11:37:39 +0800
+Subject: [PATCH 4569/4736] Revert "drm/amdgpu/gfx10: re-init clear state
+ buffer after gpu reset"
+
+there's a copy-paste error (!adev->in_gpu_reset), re-submit the patch
+
+This reverts commit 61d914ea3925eb70960210d7e8df15b349942ddb.
+
+Change-Id: Ib49e4a6e4016154a91b422fc6855517c7ad83b07
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++----------------------
+ 1 file changed, 6 insertions(+), 37 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index a364f2f645c2..5403567683b7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1789,52 +1789,27 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
+ 	WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
+ }
+ 
+-static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
++static void gfx_v10_0_init_csb(struct amdgpu_device *adev)
+ {
+-	int r;
+-
+-	if (!adev->in_gpu_reset) {
+-		r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
+-		if (r)
+-			return r;
+-
+-		r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj,
+-				   (void **)&adev->gfx.rlc.cs_ptr);
+-		if (!r) {
+-			adev->gfx.rlc.funcs->get_csb_buffer(adev,
+-					adev->gfx.rlc.cs_ptr);
+-			amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
+-		}
+-
+-		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+-		if (r)
+-			return r;
+-	}
+-
+ 	/* csib */
+ 	WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
+ 		     adev->gfx.rlc.clear_state_gpu_addr >> 32);
+ 	WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
+ 		     adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
+ 	WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
+-
+-	return 0;
+ }
+ 
+-static int gfx_v10_0_init_pg(struct amdgpu_device *adev)
++static void gfx_v10_0_init_pg(struct amdgpu_device *adev)
+ {
+ 	int i;
+-	int r;
+ 
+-	r = gfx_v10_0_init_csb(adev);
+-	if (r)
+-		return r;
++	gfx_v10_0_init_csb(adev);
+ 
+ 	for (i = 0; i < adev->num_vmhubs; i++)
+ 		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
+ 
+ 	/* TODO: init power gating */
+-	return 0;
++	return;
+ }
+ 
+ void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
+@@ -1936,10 +1911,7 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
+ 		r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
+ 		if (r)
+ 			return r;
+-
+-		r = gfx_v10_0_init_pg(adev);
+-		if (r)
+-			return r;
++		gfx_v10_0_init_pg(adev);
+ 
+ 		/* enable RLC SRM */
+ 		gfx_v10_0_rlc_enable_srm(adev);
+@@ -1965,10 +1937,7 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
+ 				return r;
+ 		}
+ 
+-		r = gfx_v10_0_init_pg(adev);
+-		if (r)
+-			return r;
+-
++		gfx_v10_0_init_pg(adev);
+ 		adev->gfx.rlc.funcs->start(adev);
+ 
+ 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4570-drm-amdgpu-gfx10-re-init-clear-state-buffer-after-gp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4570-drm-amdgpu-gfx10-re-init-clear-state-buffer-after-gp.patch
new file mode 100644
index 00000000..a67165cc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4570-drm-amdgpu-gfx10-re-init-clear-state-buffer-after-gp.patch
@@ -0,0 +1,106 @@
+From e109af54893aafc8255e7a71b48f6c2ec8b01f8b Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 20 Nov 2019 14:02:22 +0800
+Subject: [PATCH 4570/4736] drm/amdgpu/gfx10: re-init clear state buffer after
+ gpu reset
+
+This patch fixes 2nd baco reset failure with gfxoff enabled on navi1x.
+
+clear state buffer (resides in vram) is corrupted after 1st baco reset,
+upon gfxoff exit, CPF gets garbage header in CSIB and hangs.
+
+Change-Id: Ifaf95d0aab103f87b9f7970f395e95f8c4c5cc3e
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 43 ++++++++++++++++++++++----
+ 1 file changed, 37 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 5403567683b7..bfc2b8f8c1d4 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1789,27 +1789,52 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
+ 	WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
+ }
+ 
+-static void gfx_v10_0_init_csb(struct amdgpu_device *adev)
++static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
+ {
++	int r;
++
++	if (adev->in_gpu_reset) {
++		r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
++		if (r)
++			return r;
++
++		r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj,
++				   (void **)&adev->gfx.rlc.cs_ptr);
++		if (!r) {
++			adev->gfx.rlc.funcs->get_csb_buffer(adev,
++					adev->gfx.rlc.cs_ptr);
++			amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
++		}
++
++		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
++		if (r)
++			return r;
++	}
++
+ 	/* csib */
+ 	WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
+ 		     adev->gfx.rlc.clear_state_gpu_addr >> 32);
+ 	WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
+ 		     adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
+ 	WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
++
++	return 0;
+ }
+ 
+-static void gfx_v10_0_init_pg(struct amdgpu_device *adev)
++static int gfx_v10_0_init_pg(struct amdgpu_device *adev)
+ {
+ 	int i;
++	int r;
+ 
+-	gfx_v10_0_init_csb(adev);
++	r = gfx_v10_0_init_csb(adev);
++	if (r)
++		return r;
+ 
+ 	for (i = 0; i < adev->num_vmhubs; i++)
+ 		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
+ 
+ 	/* TODO: init power gating */
+-	return;
++	return 0;
+ }
+ 
+ void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
+@@ -1911,7 +1936,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
+ 		r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
+ 		if (r)
+ 			return r;
+-		gfx_v10_0_init_pg(adev);
++
++		r = gfx_v10_0_init_pg(adev);
++		if (r)
++			return r;
+ 
+ 		/* enable RLC SRM */
+ 		gfx_v10_0_rlc_enable_srm(adev);
+@@ -1937,7 +1965,10 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
+ 				return r;
+ 		}
+ 
+-		gfx_v10_0_init_pg(adev);
++		r = gfx_v10_0_init_pg(adev);
++		if (r)
++			return r;
++
+ 		adev->gfx.rlc.funcs->start(adev);
+ 
+ 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4571-drm-amdkfd-add-kfd-missing-patch.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4571-drm-amdkfd-add-kfd-missing-patch.patch
new file mode 100644
index 00000000..bb909a3b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4571-drm-amdkfd-add-kfd-missing-patch.patch
@@ -0,0 +1,65 @@
+From 2f88fdb683379b0f32e6e44aa034147cfb99046f Mon Sep 17 00:00:00 2001
+From: Flora Cui <flora.cui@amd.com>
+Date: Mon, 25 Nov 2019 13:41:00 +0800
+Subject: [PATCH 4571/4736] drm/amdkfd: add kfd missing patch
+
+from commit 99ac52a3dd189 - Merge amd-staging-drm-next into
+amd-kfd-staging
+
+Signed-off-by: Flora Cui <flora.cui@amd.com>
+Acked-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ .../drm/amd/amdkfd/kfd_device_queue_manager.c    | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 67a364ecf8c8..f2325e5f15ce 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -736,6 +736,10 @@ static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
+ 				q->properties.type)];
+ 		q->properties.is_active = false;
+ 		dqm->queue_count--;
++		if (q->properties.is_gws) {
++			dqm->gws_queue_count--;
++			qpd->mapped_gws_queue = false;
++		}
+ 
+ 		if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n"))
+ 			continue;
+@@ -748,10 +752,6 @@ static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
+ 			 * maintain a consistent eviction state
+ 			 */
+ 			ret = retval;
+-		if (q->properties.is_gws) {
+-			dqm->gws_queue_count--;
+-			qpd->mapped_gws_queue = false;
+-		}
+ 	}
+ 
+ out:
+@@ -858,6 +858,10 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
+ 				q->properties.type)];
+ 		q->properties.is_active = true;
+ 		dqm->queue_count++;
++		if (q->properties.is_gws) {
++			dqm->gws_queue_count++;
++			qpd->mapped_gws_queue = true;
++		}
+ 
+ 		if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n"))
+ 			continue;
+@@ -869,10 +873,6 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
+ 			 * maintain a consistent eviction state
+ 			 */
+ 			ret = retval;
+-		if (q->properties.is_gws) {
+-			dqm->gws_queue_count++;
+-			qpd->mapped_gws_queue = true;
+-		}
+ 	}
+ 	qpd->evicted = 0;
+ out:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4572-drm-amdkfd-add-missing-KFD_MQD_TYPE_COMPUTE.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4572-drm-amdkfd-add-missing-KFD_MQD_TYPE_COMPUTE.patch
new file mode 100644
index 00000000..b28ee4cc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4572-drm-amdkfd-add-missing-KFD_MQD_TYPE_COMPUTE.patch
@@ -0,0 +1,123 @@
+From 0a3db18ee805bf4e05b380d052863fb3647caf7c Mon Sep 17 00:00:00 2001
+From: Flora Cui <flora.cui@amd.com>
+Date: Mon, 25 Nov 2019 14:17:44 +0800
+Subject: [PATCH 4572/4736] drm/amdkfd: add missing KFD_MQD_TYPE_COMPUTE
+
+from amd-kfd-staging branch
+
+Signed-off-by: Flora Cui <flora.cui@amd.com>
+Acked-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 4 ++--
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c      | 3 ++-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c      | 1 +
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c       | 1 +
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c       | 3 ++-
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h                 | 3 ++-
+ 6 files changed, 10 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index f2325e5f15ce..76c7f0ec3de3 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -1744,7 +1744,7 @@ static int get_wave_state(struct device_queue_manager *dqm,
+ 		goto dqm_unlock;
+ 	}
+ 
+-	mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
++	mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_COMPUTE];
+ 
+ 	if (!mqd_mgr->get_wave_state) {
+ 		r = -EINVAL;
+@@ -2187,7 +2187,7 @@ void copy_context_work_handler (struct work_struct *work)
+ 
+ 
+ 		list_for_each_entry(q, &qpd->queues_list, list) {
+-			mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
++			mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_COMPUTE];
+ 
+ 			/* We ignore the return value from get_wave_state
+ 			 * because
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+index 37ce9571a175..c8561c3283b2 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+@@ -403,6 +403,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
+ 
+ 	switch (type) {
+ 	case KFD_MQD_TYPE_CP:
++	case KFD_MQD_TYPE_COMPUTE:
+ 		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd;
+ 		mqd->free_mqd = free_mqd;
+@@ -474,7 +475,7 @@ struct mqd_manager *mqd_manager_init_cik_hawaii(enum KFD_MQD_TYPE type,
+ 	mqd = mqd_manager_init_cik(type, dev);
+ 	if (!mqd)
+ 		return NULL;
+-	if (type == KFD_MQD_TYPE_CP)
++	if ((type == KFD_MQD_TYPE_CP) || (type == KFD_MQD_TYPE_COMPUTE))
+ 		mqd->update_mqd = update_mqd_hawaii;
+ 	return mqd;
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index 1e83abacf248..df383c8ff5f9 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -401,6 +401,7 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+ 
+ 	switch (type) {
+ 	case KFD_MQD_TYPE_CP:
++	case KFD_MQD_TYPE_COMPUTE:
+ 		pr_debug("%s@%i\n", __func__, __LINE__);
+ 		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index 59f75b169459..6dec54bf49c6 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -528,6 +528,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
+ 
+ 	switch (type) {
+ 	case KFD_MQD_TYPE_CP:
++	case KFD_MQD_TYPE_COMPUTE:
+ 		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd;
+ 		mqd->free_mqd = free_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+index f71679443300..5454ee562a00 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+@@ -466,6 +466,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
+ 
+ 	switch (type) {
+ 	case KFD_MQD_TYPE_CP:
++	case KFD_MQD_TYPE_COMPUTE:
+ 		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd;
+ 		mqd->free_mqd = free_mqd;
+@@ -538,7 +539,7 @@ struct mqd_manager *mqd_manager_init_vi_tonga(enum KFD_MQD_TYPE type,
+ 	mqd = mqd_manager_init_vi(type, dev);
+ 	if (!mqd)
+ 		return NULL;
+-	if (type == KFD_MQD_TYPE_CP)
++	if ((type == KFD_MQD_TYPE_CP) || (type == KFD_MQD_TYPE_COMPUTE))
+ 		mqd->update_mqd = update_mqd_tonga;
+ 	return mqd;
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index b91029047953..e937679f8ca1 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -576,7 +576,8 @@ struct queue {
+  * Please read the kfd_mqd_manager.h description.
+  */
+ enum KFD_MQD_TYPE {
+-	KFD_MQD_TYPE_HIQ = 0,		/* for hiq */
++	KFD_MQD_TYPE_COMPUTE = 0,	/* for no cp scheduling */
++	KFD_MQD_TYPE_HIQ,		/* for hiq */
+ 	KFD_MQD_TYPE_CP,		/* for cp queues and diq */
+ 	KFD_MQD_TYPE_SDMA,		/* for sdma queues */
+ 	KFD_MQD_TYPE_DIQ,		/* for diq */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4573-drm-amdkfd-add-missing-mqd-init-from-kfd-staging.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4573-drm-amdkfd-add-missing-mqd-init-from-kfd-staging.patch
new file mode 100644
index 00000000..6b2dcf6b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4573-drm-amdkfd-add-missing-mqd-init-from-kfd-staging.patch
@@ -0,0 +1,72 @@
+From ac4523f48b820462921d04ad5124da91e5b57b06 Mon Sep 17 00:00:00 2001
+From: Flora Cui <flora.cui@amd.com>
+Date: Mon, 25 Nov 2019 14:18:09 +0800
+Subject: [PATCH 4573/4736] drm/amdkfd: add missing mqd init from kfd-staging
+
+partially missing from commit 8636e53c4715d - drm/amdkfd: Separate mqd
+allocation and initialization
+
+Signed-off-by: Flora Cui <flora.cui@amd.com>
+Acked-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c  | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c  | 2 +-
+ 4 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+index c8561c3283b2..9431dc2ca54b 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+@@ -432,7 +432,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
+ #endif
+ 		break;
+ 	case KFD_MQD_TYPE_DIQ:
+-		mqd->allocate_mqd = allocate_mqd;
++		mqd->allocate_mqd = allocate_hiq_mqd;
+ 		mqd->init_mqd = init_mqd_hiq;
+ 		mqd->free_mqd = free_mqd;
+ 		mqd->load_mqd = load_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index df383c8ff5f9..65a03d1d79db 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -433,7 +433,7 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+ 		pr_debug("%s@%i\n", __func__, __LINE__);
+ 		break;
+ 	case KFD_MQD_TYPE_DIQ:
+-		mqd->allocate_mqd = allocate_mqd;
++		mqd->allocate_mqd = allocate_hiq_mqd;
+ 		mqd->init_mqd = init_mqd_hiq;
+ 		mqd->free_mqd = free_mqd;
+ 		mqd->load_mqd = load_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index 6dec54bf49c6..822747377c28 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -558,7 +558,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
+ #endif
+ 		break;
+ 	case KFD_MQD_TYPE_DIQ:
+-		mqd->allocate_mqd = allocate_mqd;
++		mqd->allocate_mqd = allocate_hiq_mqd;
+ 		mqd->init_mqd = init_mqd_hiq;
+ 		mqd->free_mqd = free_mqd;
+ 		mqd->load_mqd = load_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+index 5454ee562a00..39c9b470e227 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+@@ -496,7 +496,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
+ #endif
+ 		break;
+ 	case KFD_MQD_TYPE_DIQ:
+-		mqd->allocate_mqd = allocate_mqd;
++		mqd->allocate_mqd = allocate_hiq_mqd;
+ 		mqd->init_mqd = init_mqd_hiq;
+ 		mqd->free_mqd = free_mqd;
+ 		mqd->load_mqd = load_mqd;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4574-drm-amdgpu-disable-gfxoff-on-original-raven.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4574-drm-amdgpu-disable-gfxoff-on-original-raven.patch
new file mode 100644
index 00000000..bbf105c6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4574-drm-amdgpu-disable-gfxoff-on-original-raven.patch
@@ -0,0 +1,41 @@
+From 86c604910dc6eb1b09587b3442a8a168caef04b1 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Nov 2019 10:21:23 -0500
+Subject: [PATCH 4574/4736] drm/amdgpu: disable gfxoff on original raven
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There are still combinations of sbios and firmware that
+are not stable.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204689
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 0932e4a7c63c..18490f23e0d9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -1036,8 +1036,13 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
+ 	case CHIP_VEGA20:
+ 		break;
+ 	case CHIP_RAVEN:
+-		if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
+-			&&((adev->gfx.rlc_fw_version != 106 &&
++		/* Disable GFXOFF on original raven.  There are combinations
++		 * of sbios and platforms that are not stable.
++		 */
++		if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8))
++			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
++		else if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
++			 &&((adev->gfx.rlc_fw_version != 106 &&
+ 			     adev->gfx.rlc_fw_version < 531) ||
+ 			    (adev->gfx.rlc_fw_version == 53815) ||
+ 			    (adev->gfx.rlc_feature_version < 1) ||
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4575-Revert-drm-amd-display-enable-S-G-for-RAVEN-chip.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4575-Revert-drm-amd-display-enable-S-G-for-RAVEN-chip.patch
new file mode 100644
index 00000000..8165f97c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4575-Revert-drm-amd-display-enable-S-G-for-RAVEN-chip.patch
@@ -0,0 +1,50 @@
+From 491a758e006216162226c162a2c1c540b8338870 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Nov 2019 10:26:52 -0500
+Subject: [PATCH 4575/4736] Revert "drm/amd/display: enable S/G for RAVEN chip"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This reverts commit 1c4259159132ae4ceaf7c6db37a6cf76417f73d9.
+
+S/G display is not stable with the IOMMU enabled on some
+platforms.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205523
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c       | 2 +-
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+index dcabe24e4dc3..cf589c055305 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+@@ -512,7 +512,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
+ 	 * Also, don't allow GTT domain if the BO doens't have USWC falg set.
+ 	 */
+ 	if (adev->asic_type >= CHIP_CARRIZO &&
+-	    adev->asic_type <= CHIP_RAVEN &&
++	    adev->asic_type < CHIP_RAVEN &&
+ 	    (adev->flags & AMD_IS_APU) &&
+ 	    (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
+ 	    amdgpu_bo_support_uswc(bo_flags) &&
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 3ec482e79ecf..841f0bfd1e4f 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -929,7 +929,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
+ 	 */
+ 	if (adev->flags & AMD_IS_APU &&
+ 	    adev->asic_type >= CHIP_CARRIZO &&
+-	    adev->asic_type <= CHIP_RAVEN)
++	    adev->asic_type < CHIP_RAVEN)
+ 		init_data.flags.gpu_vm_support = true;
+ 
+ 	if (amdgpu_dc_feature_mask & DC_FBC_MASK)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4576-drm-amd-amdgpu-sriov-temporarily-skip-ras-dtm-hdcp-f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4576-drm-amd-amdgpu-sriov-temporarily-skip-ras-dtm-hdcp-f.patch
new file mode 100644
index 00000000..e243c09e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4576-drm-amd-amdgpu-sriov-temporarily-skip-ras-dtm-hdcp-f.patch
@@ -0,0 +1,103 @@
+From 1880194a969a309d0591171b910a4cbfaaf035bf Mon Sep 17 00:00:00 2001
+From: Jack Zhang <Jack.Zhang1@amd.com>
+Date: Thu, 21 Nov 2019 13:59:28 +0800
+Subject: [PATCH 4576/4736] drm/amd/amdgpu/sriov temporarily skip ras,dtm,hdcp
+ for arcturus VF
+
+Temporarily skip ras,dtm,hdcp initialize and terminate for arcturus VF
+Currently the three features haven't been enabled at SRIOV, it would
+trigger guest driver load fail with the bare-metal path of the three
+features.
+
+Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 36 +++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index b9922a5f6890..0f903c4bab2e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -760,6 +760,12 @@ static int psp_ras_terminate(struct psp_context *psp)
+ {
+ 	int ret;
+ 
++	/*
++	 * TODO: bypass the terminate in sriov for now
++	 */
++	if (amdgpu_sriov_vf(psp->adev))
++		return 0;
++
+ 	if (!psp->ras.ras_initialized)
+ 		return 0;
+ 
+@@ -781,6 +787,12 @@ static int psp_ras_initialize(struct psp_context *psp)
+ {
+ 	int ret;
+ 
++	/*
++	 * TODO: bypass the initialize in sriov for now
++	 */
++	if (amdgpu_sriov_vf(psp->adev))
++		return 0;
++
+ 	if (!psp->adev->psp.ta_ras_ucode_size ||
+ 	    !psp->adev->psp.ta_ras_start_addr) {
+ 		dev_warn(psp->adev->dev, "RAS: ras ta ucode is not available\n");
+@@ -876,6 +888,12 @@ static int psp_hdcp_initialize(struct psp_context *psp)
+ {
+ 	int ret;
+ 
++	/*
++	 * TODO: bypass the initialize in sriov for now
++	 */
++	if (amdgpu_sriov_vf(psp->adev))
++		return 0;
++
+ 	if (!psp->adev->psp.ta_hdcp_ucode_size ||
+ 	    !psp->adev->psp.ta_hdcp_start_addr) {
+ 		dev_warn(psp->adev->dev, "HDCP: hdcp ta ucode is not available\n");
+@@ -964,6 +982,12 @@ static int psp_hdcp_terminate(struct psp_context *psp)
+ {
+ 	int ret;
+ 
++	/*
++	 * TODO: bypass the terminate in sriov for now
++	 */
++	if (amdgpu_sriov_vf(psp->adev))
++		return 0;
++
+ 	if (!psp->hdcp_context.hdcp_initialized)
+ 		return 0;
+ 
+@@ -1055,6 +1079,12 @@ static int psp_dtm_initialize(struct psp_context *psp)
+ {
+ 	int ret;
+ 
++	/*
++	 * TODO: bypass the initialize in sriov for now
++	 */
++	if (amdgpu_sriov_vf(psp->adev))
++		return 0;
++
+ 	if (!psp->adev->psp.ta_dtm_ucode_size ||
+ 	    !psp->adev->psp.ta_dtm_start_addr) {
+ 		dev_warn(psp->adev->dev, "DTM: dtm ta ucode is not available\n");
+@@ -1113,6 +1143,12 @@ static int psp_dtm_terminate(struct psp_context *psp)
+ {
+ 	int ret;
+ 
++	/*
++	 * TODO: bypass the terminate in sriov for now
++	 */
++	if (amdgpu_sriov_vf(psp->adev))
++		return 0;
++
+ 	if (!psp->dtm_context.dtm_initialized)
+ 		return 0;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4577-drm-amd-amdgpu-sriov-skip-RLCG-s-r-list-for-arcturus.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4577-drm-amd-amdgpu-sriov-skip-RLCG-s-r-list-for-arcturus.patch
new file mode 100644
index 00000000..85c999d7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4577-drm-amd-amdgpu-sriov-skip-RLCG-s-r-list-for-arcturus.patch
@@ -0,0 +1,37 @@
+From 23e70ae93d3599bd6c79232bbf67ae5929bcbdd5 Mon Sep 17 00:00:00 2001
+From: Jack Zhang <Jack.Zhang1@amd.com>
+Date: Thu, 21 Nov 2019 14:09:08 +0800
+Subject: [PATCH 4577/4736] drm/amd/amdgpu/sriov skip RLCG s/r list for
+ arcturus VF.
+
+After rlcg fw 2.1, kmd driver starts to load extra fw for
+LIST_CNTL,GPM_MEM,SRM_MEM. We needs to skip the three fw
+because all rlcg related fw have been loaded by host driver.
+Guest driver would load the three fw fail without this change.
+
+Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 0f903c4bab2e..c74c5f183a10 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1472,7 +1472,10 @@ static int psp_np_fw_load(struct psp_context *psp)
+ 		    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
+ 		    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
+ 		    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
+-		    || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
++                    || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
++	            || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
++	            || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
++	            || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM))
+ 			/*skip ucode loading in SRIOV VF */
+ 			continue;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4578-drm-amdgpu-invalidate-mmhub-semaphore-workaround-in-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4578-drm-amdgpu-invalidate-mmhub-semaphore-workaround-in-.patch
new file mode 100644
index 00000000..eb84ba85
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4578-drm-amdgpu-invalidate-mmhub-semaphore-workaround-in-.patch
@@ -0,0 +1,223 @@
+From 7d29c52c9ae3611a23c78e779ccf81ca0e7a9f8c Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Tue, 19 Nov 2019 11:13:29 +0800
+Subject: [PATCH 4578/4736] drm/amdgpu: invalidate mmhub semaphore workaround
+ in gmc9/gmc10
+
+It may lose gpuvm invalidate acknowldege state across power-gating off
+cycle. To avoid this issue in gmc9/gmc10 invalidation, add semaphore acquire
+before invalidation and semaphore release after invalidation.
+
+After adding semaphore acquire before invalidation, the semaphore
+register become read-only if another process try to acquire semaphore.
+Then it will not be able to release this semaphore. Then it may cause
+deadlock problem. If this deadlock problem happens, it needs a semaphore
+firmware fix.
+
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+Acked-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 57 ++++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 57 ++++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/soc15.h     |  4 +-
+ 3 files changed, 116 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+index af2615ba52aa..9effec6a7a67 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+@@ -234,6 +234,29 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
+ 	const unsigned eng = 17;
+ 	unsigned int i;
+ 
++	spin_lock(&adev->gmc.invalidate_lock);
++	/*
++	 * It may lose gpuvm invalidate acknowldege state across power-gating
++	 * off cycle, add semaphore acquire before invalidation and semaphore
++	 * release after invalidation to avoid entering power gated state
++	 * to WA the Issue
++	 */
++
++	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
++	if (vmhub == AMDGPU_MMHUB_0 ||
++	    vmhub == AMDGPU_MMHUB_1) {
++		for (i = 0; i < adev->usec_timeout; i++) {
++			/* a read return value of 1 means semaphore acuqire */
++			tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
++			if (tmp & 0x1)
++				break;
++			udelay(1);
++		}
++
++		if (i >= adev->usec_timeout)
++			DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
++	}
++
+ 	WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
+ 
+ 	/*
+@@ -253,6 +276,17 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
+ 		udelay(1);
+ 	}
+ 
++	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
++	if (vmhub == AMDGPU_MMHUB_0 ||
++	    vmhub == AMDGPU_MMHUB_1)
++		/*
++		 * add semaphore release after invalidation,
++		 * write with 0 means semaphore release
++		 */
++		WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
++
++	spin_unlock(&adev->gmc.invalidate_lock);
++
+ 	if (i < adev->usec_timeout)
+ 		return;
+ 
+@@ -338,6 +372,20 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+ 	uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);
+ 	unsigned eng = ring->vm_inv_eng;
+ 
++	/*
++	 * It may lose gpuvm invalidate acknowldege state across power-gating
++	 * off cycle, add semaphore acquire before invalidation and semaphore
++	 * release after invalidation to avoid entering power gated state
++	 * to WA the Issue
++	 */
++
++	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
++	if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
++	    ring->funcs->vmhub == AMDGPU_MMHUB_1)
++		/* a read return value of 1 means semaphore acuqire */
++		amdgpu_ring_emit_reg_wait(ring,
++					  hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
++
+ 	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
+ 			      lower_32_bits(pd_addr));
+ 
+@@ -348,6 +396,15 @@ static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+ 					    hub->vm_inv_eng0_ack + eng,
+ 					    req, 1 << vmid);
+ 
++	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
++	if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
++	    ring->funcs->vmhub == AMDGPU_MMHUB_1)
++		/*
++		 * add semaphore release after invalidation,
++		 * write with 0 means semaphore release
++		 */
++		amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0);
++
+ 	return pd_addr;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 992ecc74ea38..b051ede2fb83 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -455,6 +455,29 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
+         }
+ 
+         spin_lock(&adev->gmc.invalidate_lock);
++
++	/*
++	 * It may lose gpuvm invalidate acknowldege state across power-gating
++	 * off cycle, add semaphore acquire before invalidation and semaphore
++	 * release after invalidation to avoid entering power gated state
++	 * to WA the Issue
++	 */
++
++	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
++	if (vmhub == AMDGPU_MMHUB_0 ||
++	    vmhub == AMDGPU_MMHUB_1) {
++		for (j = 0; j < adev->usec_timeout; j++) {
++			/* a read return value of 1 means semaphore acuqire */
++			tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
++			if (tmp & 0x1)
++				break;
++			udelay(1);
++	}
++
++		if (j >= adev->usec_timeout)
++			DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
++	}
++	
+         WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
+ 
+         /*
+@@ -470,7 +493,18 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
+                         break;
+                 udelay(1);
+ 	}
++
++	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
++	if (vmhub == AMDGPU_MMHUB_0 ||
++	    vmhub == AMDGPU_MMHUB_1)
++		/*
++		 * add semaphore release after invalidation,
++		 * write with 0 means semaphore release
++		 */
++		WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
++
+         spin_unlock(&adev->gmc.invalidate_lock);
++
+         if (j < adev->usec_timeout)
+                 return;
+ 
+@@ -485,6 +519,20 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+ 	uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
+ 	unsigned eng = ring->vm_inv_eng;
+ 
++	/*
++	 * It may lose gpuvm invalidate acknowldege state across power-gating
++	 * off cycle, add semaphore acquire before invalidation and semaphore
++	 * release after invalidation to avoid entering power gated state
++	 * to WA the Issue
++	 */
++
++	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
++	if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
++	    ring->funcs->vmhub == AMDGPU_MMHUB_1)
++		/* a read return value of 1 means semaphore acuqire */
++		amdgpu_ring_emit_reg_wait(ring,
++					  hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
++
+ 	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
+ 			      lower_32_bits(pd_addr));
+ 
+@@ -495,6 +543,15 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
+ 					    hub->vm_inv_eng0_ack + eng,
+ 					    req, 1 << vmid);
+ 
++	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
++	if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
++	    ring->funcs->vmhub == AMDGPU_MMHUB_1)
++		/*
++		 * add semaphore release after invalidation,
++		 * write with 0 means semaphore release
++		 */
++		amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0);
++
+ 	return pd_addr;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
+index 344280b869c4..d0fb7a67c1a3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
+@@ -28,8 +28,8 @@
+ #include "nbio_v7_0.h"
+ #include "nbio_v7_4.h"
+ 
+-#define SOC15_FLUSH_GPU_TLB_NUM_WREG		4
+-#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT	1
++#define SOC15_FLUSH_GPU_TLB_NUM_WREG		6
++#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT	3
+ 
+ extern const struct amd_ip_funcs soc15_common_ip_funcs;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4579-drm-amdkfd-Remove-duplicate-functions-update_mqd_hiq.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4579-drm-amdkfd-Remove-duplicate-functions-update_mqd_hiq.patch
new file mode 100644
index 00000000..d1ee0e0c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4579-drm-amdkfd-Remove-duplicate-functions-update_mqd_hiq.patch
@@ -0,0 +1,118 @@
+From a54a55ca5ec95676e24f1dd63c048760e4f1174e Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Sat, 9 Nov 2019 01:16:05 -0500
+Subject: [PATCH 4579/4736] drm/amdkfd: Remove duplicate functions
+ update_mqd_hiq()
+
+The functions are the same as update_mqd().
+
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Zhan Liu <zhan.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 16 ++--------------
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c  | 16 ++--------------
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c  |  4 ----
+ 3 files changed, 4 insertions(+), 32 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index 65a03d1d79db..0487ddcbfa00 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -282,18 +282,6 @@ static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
+ 			1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
+ }
+ 
+-static void update_mqd_hiq(struct mqd_manager *mm, void *mqd,
+-			struct queue_properties *q)
+-{
+-	struct v10_compute_mqd *m;
+-
+-	update_mqd(mm, mqd, q);
+-
+-	/* TODO: what's the point? update_mqd already does this. */
+-	m = get_mqd(mqd);
+-	m->cp_hqd_vmid = q->vmid;
+-}
+-
+ static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
+ 		struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
+ 		struct queue_properties *q)
+@@ -423,7 +411,7 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+ 		mqd->init_mqd = init_mqd_hiq;
+ 		mqd->free_mqd = free_mqd_hiq_sdma;
+ 		mqd->load_mqd = load_mqd;
+-		mqd->update_mqd = update_mqd_hiq;
++		mqd->update_mqd = update_mqd;
+ 		mqd->destroy_mqd = destroy_mqd;
+ 		mqd->is_occupied = is_occupied;
+ 		mqd->mqd_size = sizeof(struct v10_compute_mqd);
+@@ -437,7 +425,7 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+ 		mqd->init_mqd = init_mqd_hiq;
+ 		mqd->free_mqd = free_mqd;
+ 		mqd->load_mqd = load_mqd;
+-		mqd->update_mqd = update_mqd_hiq;
++		mqd->update_mqd = update_mqd;
+ 		mqd->destroy_mqd = destroy_mqd;
+ 		mqd->is_occupied = is_occupied;
+ 		mqd->mqd_size = sizeof(struct v10_compute_mqd);
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index 822747377c28..d8fd332c7b14 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -409,18 +409,6 @@ static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
+ 			1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
+ }
+ 
+-static void update_mqd_hiq(struct mqd_manager *mm, void *mqd,
+-			struct queue_properties *q)
+-{
+-	struct v9_mqd *m;
+-
+-	update_mqd(mm, mqd, q);
+-
+-	/* TODO: what's the point? update_mqd already does this. */
+-	m = get_mqd(mqd);
+-	m->cp_hqd_vmid = q->vmid;
+-}
+-
+ static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
+ 		struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
+ 		struct queue_properties *q)
+@@ -548,7 +536,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
+ 		mqd->init_mqd = init_mqd_hiq;
+ 		mqd->free_mqd = free_mqd_hiq_sdma;
+ 		mqd->load_mqd = load_mqd;
+-		mqd->update_mqd = update_mqd_hiq;
++		mqd->update_mqd = update_mqd;
+ 		mqd->destroy_mqd = destroy_mqd;
+ 		mqd->is_occupied = is_occupied;
+ 		mqd->check_queue_active = check_queue_active;
+@@ -562,7 +550,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
+ 		mqd->init_mqd = init_mqd_hiq;
+ 		mqd->free_mqd = free_mqd;
+ 		mqd->load_mqd = load_mqd;
+-		mqd->update_mqd = update_mqd_hiq;
++		mqd->update_mqd = update_mqd;
+ 		mqd->destroy_mqd = destroy_mqd;
+ 		mqd->is_occupied = is_occupied;
+ 		mqd->check_queue_active = check_queue_active;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+index 39c9b470e227..6909b79361a7 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+@@ -353,11 +353,7 @@ static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
+ static void update_mqd_hiq(struct mqd_manager *mm, void *mqd,
+ 			struct queue_properties *q)
+ {
+-	struct vi_mqd *m;
+ 	__update_mqd(mm, mqd, q, MTYPE_UC, 0);
+-
+-	m = get_mqd(mqd);
+-	m->cp_hqd_vmid = q->vmid;
+ }
+ 
+ static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4580-drm-amd-powerplay-Use-ARRAY_SIZE-for-smu7_profiling.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4580-drm-amd-powerplay-Use-ARRAY_SIZE-for-smu7_profiling.patch
new file mode 100644
index 00000000..fac17dec
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4580-drm-amd-powerplay-Use-ARRAY_SIZE-for-smu7_profiling.patch
@@ -0,0 +1,33 @@
+From d890a769542d98fa2e26548543322354fe1dfffe Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Fri, 22 Nov 2019 11:42:51 +0800
+Subject: [PATCH 4580/4736] drm/amd/powerplay: Use ARRAY_SIZE for
+ smu7_profiling
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c:4946:28-29: WARNING: Use ARRAY_SIZE
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+index 5c6b71b356e7..901b5c263744 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -4942,7 +4942,7 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
+ 			title[0], title[1], title[2], title[3],
+ 			title[4], title[5], title[6], title[7]);
+ 
+-	len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting);
++	len = ARRAY_SIZE(smu7_profiling);
+ 
+ 	for (i = 0; i < len; i++) {
+ 		if (i == hwmgr->power_profile_mode) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4581-drm-amdgpu-Use-ARRAY_SIZE-for-sos_old_versions.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4581-drm-amdgpu-Use-ARRAY_SIZE-for-sos_old_versions.patch
new file mode 100644
index 00000000..e818f35b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4581-drm-amdgpu-Use-ARRAY_SIZE-for-sos_old_versions.patch
@@ -0,0 +1,32 @@
+From fc4ba60efac03b9af545aee58cd5918ce5e601c2 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Fri, 22 Nov 2019 11:42:52 +0800
+Subject: [PATCH 4581/4736] drm/amdgpu: Use ARRAY_SIZE for sos_old_versions
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/amdgpu/psp_v3_1.c:182:40-41: WARNING: Use ARRAY_SIZE
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+index 839806cf1c6a..773e272efc93 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+@@ -177,7 +177,7 @@ static bool psp_v3_1_match_version(struct amdgpu_device *adev, uint32_t ver)
+ 	 * Double check if the latest four legacy versions.
+ 	 * If yes, it is still the right version.
+ 	 */
+-	for (i = 0; i < sizeof(sos_old_versions) / sizeof(uint32_t); i++) {
++	for (i = 0; i < ARRAY_SIZE(sos_old_versions); i++) {
+ 		if (sos_old_versions[i] == adev->psp.sos_fw_version)
+ 			return true;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4582-drm-amd-display-add-default-clocks-if-not-able-to-fe.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4582-drm-amd-display-add-default-clocks-if-not-able-to-fe.patch
new file mode 100644
index 00000000..bf21a228
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4582-drm-amd-display-add-default-clocks-if-not-able-to-fe.patch
@@ -0,0 +1,34 @@
+From 332156cfc87987494734f42a22cfb63359313d2f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 19 Nov 2019 15:54:17 -0500
+Subject: [PATCH 4582/4736] drm/amd/display: add default clocks if not able to
+ fetch them
+
+dm_pp_get_clock_levels_by_type needs to add the default clocks
+to the powerplay case as well.  This was accidently dropped.
+
+Fixes: b3ea88fef321de ("drm/amd/powerplay: add get_clock_by_type interface for display")
+Bug: https://gitlab.freedesktop.org/drm/amd/issues/906
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+index 254123a02aa3..800cdfb5b566 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+@@ -343,7 +343,8 @@ bool dm_pp_get_clock_levels_by_type(
+ 	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_clock_by_type) {
+ 		if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,
+ 			dc_to_pp_clock_type(clk_type), &pp_clks)) {
+-		/* Error in pplib. Provide default values. */
++			/* Error in pplib. Provide default values. */
++			get_default_clock_levels(clk_type, dc_clks);
+ 			return true;
+ 		}
+ 	} else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4583-drm-amdgpu-Apply-noretry-setting-for-mmhub9.4.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4583-drm-amdgpu-Apply-noretry-setting-for-mmhub9.4.patch
new file mode 100644
index 00000000..9fb5677a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4583-drm-amdgpu-Apply-noretry-setting-for-mmhub9.4.patch
@@ -0,0 +1,40 @@
+From 806e277434cc6343e91dea823ed66099c6d1683b Mon Sep 17 00:00:00 2001
+From: Oak Zeng <Oak.Zeng@amd.com>
+Date: Fri, 22 Nov 2019 14:15:43 -0600
+Subject: [PATCH 4583/4736] drm/amdgpu: Apply noretry setting for mmhub9.4
+
+Config the translation retry behavior according to noretry
+kernel parameter
+
+Change-Id: I5b91ea77715137cf8cb84e258ccdfbb19c7a4ed1
+Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
+Suggested-by: Jay Cornwall <Jay.Cornwall@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+index 753eea25b569..8599bfdb9a9e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+@@ -314,7 +314,8 @@ static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
+ 				    adev->vm_manager.block_size - 9);
+ 		/* Send no-retry XNACK on fault to suppress VM fault storm. */
+ 		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
+-				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
++				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
++				    !amdgpu_noretry);
+ 		WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
+ 				    hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i,
+ 				    tmp);
+@@ -905,4 +906,4 @@ static void mmhub_v9_4_query_ras_error_count(struct amdgpu_device *adev,
+ const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs = {
+ 	.ras_late_init = amdgpu_mmhub_ras_late_init,
+ 	.query_ras_error_count = mmhub_v9_4_query_ras_error_count,
+-};
+\ No newline at end of file
++};
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4584-Revert-drm-amd-powerplay-read-pcie-speed-width-info.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4584-Revert-drm-amd-powerplay-read-pcie-speed-width-info.patch
new file mode 100644
index 00000000..d07ad400
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4584-Revert-drm-amd-powerplay-read-pcie-speed-width-info.patch
@@ -0,0 +1,198 @@
+From 80378c10988a4817bfffaeb7063e3dc1259f532e Mon Sep 17 00:00:00 2001
+From: "Stanley.Yang" <Stanley.Yang@amd.com>
+Date: Mon, 25 Nov 2019 15:50:45 +0800
+Subject: [PATCH 4584/4736] Revert "drm/amd/powerplay: read pcie speed/width
+ info"
+
+This reverts commit 3666556f6d713db86b4d593d5cc691cdba86fa85.
+
+Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 10 ++--
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  8 ---
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 50 +------------------
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.h    |  3 --
+ 4 files changed, 5 insertions(+), 66 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index acbbafeea01c..d5335bdc709b 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1081,6 +1081,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ 		return ret;
+ 
+ 	if (adev->asic_type != CHIP_ARCTURUS) {
++		ret = smu_override_pcie_parameters(smu);
++		if (ret)
++			return ret;
++
+ 		ret = smu_notify_display_change(smu);
+ 		if (ret)
+ 			return ret;
+@@ -1109,12 +1113,6 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ 			return ret;
+ 	}
+ 
+-	if (adev->asic_type != CHIP_ARCTURUS) {
+-		ret = smu_override_pcie_parameters(smu);
+-		if (ret)
+-			return ret;
+-	}
+-
+ 	ret = smu_set_default_od_settings(smu, initialize);
+ 	if (ret)
+ 		return ret;
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 716fcb274191..ebdf7bd79a67 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -49,8 +49,6 @@
+ 
+ #define SMU11_TOOL_SIZE			0x19000
+ 
+-#define MAX_PCIE_CONF 2
+-
+ #define CLK_MAP(clk, index) \
+ 	[SMU_##clk] = {1, (index)}
+ 
+@@ -91,11 +89,6 @@ struct smu_11_0_dpm_table {
+ 	uint32_t    max;        /* MHz */
+ };
+ 
+-struct smu_11_0_pcie_table {
+-        uint8_t  pcie_gen[MAX_PCIE_CONF];
+-        uint8_t  pcie_lane[MAX_PCIE_CONF];
+-};
+-
+ struct smu_11_0_dpm_tables {
+ 	struct smu_11_0_dpm_table        soc_table;
+ 	struct smu_11_0_dpm_table        gfx_table;
+@@ -108,7 +101,6 @@ struct smu_11_0_dpm_tables {
+ 	struct smu_11_0_dpm_table        display_table;
+ 	struct smu_11_0_dpm_table        phy_table;
+ 	struct smu_11_0_dpm_table        fclk_table;
+-	struct smu_11_0_pcie_table       pcie_table;
+ };
+ 
+ struct smu_11_0_dpm_context {
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index 24765e813cc2..aca913289e3c 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -35,7 +35,6 @@
+ #include "navi10_ppt.h"
+ #include "smu_v11_0_pptable.h"
+ #include "smu_v11_0_ppsmc.h"
+-#include "nbio/nbio_7_4_sh_mask.h"
+ 
+ #include "asic_reg/mp/mp_11_0_sh_mask.h"
+ 
+@@ -601,7 +600,6 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
+ 	struct smu_table_context *table_context = &smu->smu_table;
+ 	struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+ 	PPTable_t *driver_ppt = NULL;
+-	int i;
+ 
+         driver_ppt = table_context->driver_pptable;
+ 
+@@ -632,11 +630,6 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
+         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
+         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
+ 
+-	for (i = 0; i < MAX_PCIE_CONF; i++) {
+-		dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
+-		dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
+-	}
+-
+ 	return 0;
+ }
+ 
+@@ -743,11 +736,6 @@ static int navi10_print_clk_levels(struct smu_context *smu,
+ 	struct smu_table_context *table_context = &smu->smu_table;
+ 	od_table = (OverDriveTable_t *)table_context->overdrive_table;
+ 	od_settings = smu->od_settings;
+-	uint32_t gen_speed, lane_width;
+-	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+-	struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+-	struct amdgpu_device *adev = smu->adev;
+-	PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
+ 
+ 	switch (clk_type) {
+ 	case SMU_GFXCLK:
+@@ -798,30 +786,6 @@ static int navi10_print_clk_levels(struct smu_context *smu,
+ 
+ 		}
+ 		break;
+-	case SMU_PCIE:
+-		gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
+-			     PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
+-			>> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
+-		lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
+-			      PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
+-			>> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
+-		for (i = 0; i < NUM_LINK_LEVELS; i++)
+-			size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
+-					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
+-					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
+-					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
+-					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
+-					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
+-					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
+-					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
+-					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
+-					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
+-					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
+-					pptable->LclkFreq[i],
+-					(gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
+-					(lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
+-					"*" : "");
+-		break;
+ 	case SMU_OD_SCLK:
+ 		if (!smu->od_enabled || !od_table || !od_settings)
+ 			break;
+@@ -1758,9 +1722,6 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
+ 	int ret, i;
+ 	uint32_t smu_pcie_arg;
+ 
+-	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+-	struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+-
+ 	for (i = 0; i < NUM_LINK_LEVELS; i++) {
+ 		smu_pcie_arg = (i << 16) |
+ 			((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
+@@ -1769,17 +1730,8 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
+ 		ret = smu_send_smc_msg_with_param(smu,
+ 					  SMU_MSG_OverridePcieParameters,
+ 					  smu_pcie_arg);
+-
+-		if (ret)
+-			return ret;
+-
+-		if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
+-			dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
+-		if (pptable->PcieLaneCount[i] > pcie_width_cap)
+-			dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
+ 	}
+-
+-	return 0;
++	return ret;
+ }
+ 
+ static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+index ec03c7992f6d..fd6dda1a67a1 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+@@ -35,9 +35,6 @@
+ 
+ #define NAVI10_VOLTAGE_SCALE (4)
+ 
+-#define smnPCIE_LC_SPEED_CNTL			0x11140290
+-#define smnPCIE_LC_LINK_WIDTH_CNTL		0x11140288
+-
+ extern void navi10_set_ppt_funcs(struct smu_context *smu);
+ 
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4585-drm-amd-powerplay-read-pcie-speed-width-info-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4585-drm-amd-powerplay-read-pcie-speed-width-info-v2.patch
new file mode 100644
index 00000000..72664fbb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4585-drm-amd-powerplay-read-pcie-speed-width-info-v2.patch
@@ -0,0 +1,214 @@
+From 1eb88c64a5d5fa596fc96e37b5f72e79a7da6064 Mon Sep 17 00:00:00 2001
+From: Kenneth Feng <kenneth.feng@amd.com>
+Date: Tue, 12 Nov 2019 16:27:11 +0800
+Subject: [PATCH 4585/4736] drm/amd/powerplay: read pcie speed/width info (v2)
+
+sysfs interface to read pcie speed&width info on navi1x.
+
+v2: fix warning (trivial)
+
+Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 10 ++--
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  8 +++
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 57 +++++++++++++++++--
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.h    |  3 +
+ 4 files changed, 69 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index d5335bdc709b..acbbafeea01c 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1081,10 +1081,6 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ 		return ret;
+ 
+ 	if (adev->asic_type != CHIP_ARCTURUS) {
+-		ret = smu_override_pcie_parameters(smu);
+-		if (ret)
+-			return ret;
+-
+ 		ret = smu_notify_display_change(smu);
+ 		if (ret)
+ 			return ret;
+@@ -1113,6 +1109,12 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
+ 			return ret;
+ 	}
+ 
++	if (adev->asic_type != CHIP_ARCTURUS) {
++		ret = smu_override_pcie_parameters(smu);
++		if (ret)
++			return ret;
++	}
++
+ 	ret = smu_set_default_od_settings(smu, initialize);
+ 	if (ret)
+ 		return ret;
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index ebdf7bd79a67..716fcb274191 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -49,6 +49,8 @@
+ 
+ #define SMU11_TOOL_SIZE			0x19000
+ 
++#define MAX_PCIE_CONF 2
++
+ #define CLK_MAP(clk, index) \
+ 	[SMU_##clk] = {1, (index)}
+ 
+@@ -89,6 +91,11 @@ struct smu_11_0_dpm_table {
+ 	uint32_t    max;        /* MHz */
+ };
+ 
++struct smu_11_0_pcie_table {
++        uint8_t  pcie_gen[MAX_PCIE_CONF];
++        uint8_t  pcie_lane[MAX_PCIE_CONF];
++};
++
+ struct smu_11_0_dpm_tables {
+ 	struct smu_11_0_dpm_table        soc_table;
+ 	struct smu_11_0_dpm_table        gfx_table;
+@@ -101,6 +108,7 @@ struct smu_11_0_dpm_tables {
+ 	struct smu_11_0_dpm_table        display_table;
+ 	struct smu_11_0_dpm_table        phy_table;
+ 	struct smu_11_0_dpm_table        fclk_table;
++	struct smu_11_0_pcie_table       pcie_table;
+ };
+ 
+ struct smu_11_0_dpm_context {
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index aca913289e3c..c94c2b67c309 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -35,6 +35,7 @@
+ #include "navi10_ppt.h"
+ #include "smu_v11_0_pptable.h"
+ #include "smu_v11_0_ppsmc.h"
++#include "nbio/nbio_7_4_sh_mask.h"
+ 
+ #include "asic_reg/mp/mp_11_0_sh_mask.h"
+ 
+@@ -600,6 +601,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
+ 	struct smu_table_context *table_context = &smu->smu_table;
+ 	struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
+ 	PPTable_t *driver_ppt = NULL;
++	int i;
+ 
+         driver_ppt = table_context->driver_pptable;
+ 
+@@ -630,6 +632,11 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
+         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
+         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
+ 
++	for (i = 0; i < MAX_PCIE_CONF; i++) {
++		dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
++		dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
++	}
++
+ 	return 0;
+ }
+ 
+@@ -726,16 +733,20 @@ static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_tabl
+ static int navi10_print_clk_levels(struct smu_context *smu,
+ 			enum smu_clk_type clk_type, char *buf)
+ {
+-	OverDriveTable_t *od_table;
+-	struct smu_11_0_overdrive_table *od_settings;
+ 	uint16_t *curve_settings;
+ 	int i, size = 0, ret = 0;
+ 	uint32_t cur_value = 0, value = 0, count = 0;
+ 	uint32_t freq_values[3] = {0};
+ 	uint32_t mark_index = 0;
+ 	struct smu_table_context *table_context = &smu->smu_table;
+-	od_table = (OverDriveTable_t *)table_context->overdrive_table;
+-	od_settings = smu->od_settings;
++	uint32_t gen_speed, lane_width;
++	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
++	struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
++	struct amdgpu_device *adev = smu->adev;
++	PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
++	OverDriveTable_t *od_table =
++		(OverDriveTable_t *)table_context->overdrive_table;
++	struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
+ 
+ 	switch (clk_type) {
+ 	case SMU_GFXCLK:
+@@ -786,6 +797,30 @@ static int navi10_print_clk_levels(struct smu_context *smu,
+ 
+ 		}
+ 		break;
++	case SMU_PCIE:
++		gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
++			     PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
++			>> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
++		lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
++			      PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
++			>> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
++		for (i = 0; i < NUM_LINK_LEVELS; i++)
++			size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
++					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
++					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
++					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
++					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
++					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
++					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
++					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
++					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
++					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
++					(dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
++					pptable->LclkFreq[i],
++					(gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
++					(lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
++					"*" : "");
++		break;
+ 	case SMU_OD_SCLK:
+ 		if (!smu->od_enabled || !od_table || !od_settings)
+ 			break;
+@@ -1722,6 +1757,9 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
+ 	int ret, i;
+ 	uint32_t smu_pcie_arg;
+ 
++	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
++	struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
++
+ 	for (i = 0; i < NUM_LINK_LEVELS; i++) {
+ 		smu_pcie_arg = (i << 16) |
+ 			((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
+@@ -1730,8 +1768,17 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
+ 		ret = smu_send_smc_msg_with_param(smu,
+ 					  SMU_MSG_OverridePcieParameters,
+ 					  smu_pcie_arg);
++
++		if (ret)
++			return ret;
++
++		if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
++			dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
++		if (pptable->PcieLaneCount[i] > pcie_width_cap)
++			dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
+ 	}
+-	return ret;
++
++	return 0;
+ }
+ 
+ static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+index fd6dda1a67a1..ec03c7992f6d 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.h
+@@ -35,6 +35,9 @@
+ 
+ #define NAVI10_VOLTAGE_SCALE (4)
+ 
++#define smnPCIE_LC_SPEED_CNTL			0x11140290
++#define smnPCIE_LC_LINK_WIDTH_CNTL		0x11140288
++
+ extern void navi10_set_ppt_funcs(struct smu_context *smu);
+ 
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4586-Revert-drm-amd-powerplay-enable-gpu_busy_percent-sys.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4586-Revert-drm-amd-powerplay-enable-gpu_busy_percent-sys.patch
new file mode 100644
index 00000000..1e103903
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4586-Revert-drm-amd-powerplay-enable-gpu_busy_percent-sys.patch
@@ -0,0 +1,192 @@
+From d3356fee47c1ba461195da707e7b0c0e9868fd80 Mon Sep 17 00:00:00 2001
+From: "Stanley.Yang" <Stanley.Yang@amd.com>
+Date: Mon, 25 Nov 2019 16:51:51 +0800
+Subject: [PATCH 4586/4736] Revert "drm/amd/powerplay: enable gpu_busy_percent
+ sys interface for renoir"
+
+This reverts commit 06a4360eecaf6c178518c3b531a583f2fe4c6ae6.
+
+Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h |  4 -
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c    | 75 -------------------
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c     | 33 --------
+ 3 files changed, 112 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+index 44c65dd8850d..1745e0146fba 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+@@ -62,10 +62,6 @@ int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate);
+ 
+ int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
+ 
+-int smu_v12_0_read_sensor(struct smu_context *smu,
+-			  enum amd_pp_sensors sensor,
+-			  void *data, uint32_t *size);
+-
+ uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu);
+ 
+ int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable);
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index b44ce143e895..2c624cdf1d81 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -139,27 +139,6 @@ static int renoir_get_smu_table_index(struct smu_context *smc, uint32_t index)
+ 	return mapping.map_to;
+ }
+ 
+-static int renoir_get_metrics_table(struct smu_context *smu,
+-				    SmuMetrics_t *metrics_table)
+-{
+-	struct smu_table_context *smu_table= &smu->smu_table;
+-	int ret = 0;
+-
+-	if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
+-		ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
+-				(void *)smu_table->metrics_table, false);
+-		if (ret) {
+-			pr_info("Failed to export SMU metrics table!\n");
+-			return ret;
+-		}
+-		smu_table->metrics_time = jiffies;
+-	}
+-
+-	memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
+-
+-	return ret;
+-}
+-
+ static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
+ {
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+@@ -175,11 +154,6 @@ static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
+ 	if (!smu_table->clocks_table)
+ 		return -ENOMEM;
+ 
+-	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
+-	if (!smu_table->metrics_table)
+-		return -ENOMEM;
+-	smu_table->metrics_time = 0;
+-
+ 	return 0;
+ }
+ 
+@@ -412,32 +386,6 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
+ 	return ret;
+ }
+ 
+-static int renoir_get_current_activity_percent(struct smu_context *smu,
+-					       enum amd_pp_sensors sensor,
+-					       uint32_t *value)
+-{
+-	int ret = 0;
+-	SmuMetrics_t metrics;
+-
+-	if (!value)
+-		return -EINVAL;
+-
+-	ret = renoir_get_metrics_table(smu, &metrics);
+-	if (ret)
+-		return ret;
+-
+-	switch (sensor) {
+-	case AMDGPU_PP_SENSOR_GPU_LOAD:
+-		*value = metrics.AverageGfxActivity;
+-		break;
+-	default:
+-		pr_err("Invalid sensor for retrieving clock activity\n");
+-		return -EINVAL;
+-	}
+-
+-	return 0;
+-}
+-
+ static int renoir_get_workload_type(struct smu_context *smu, uint32_t profile)
+ {
+ 
+@@ -751,28 +699,6 @@ static int renoir_get_power_profile_mode(struct smu_context *smu,
+ 	return size;
+ }
+ 
+-static int renoir_read_sensor(struct smu_context *smu,
+-				 enum amd_pp_sensors sensor,
+-				 void *data, uint32_t *size)
+-{
+-	int ret = 0;
+-
+-	if (!data || !size)
+-		return -EINVAL;
+-
+-	mutex_lock(&smu->sensor_lock);
+-	switch (sensor) {
+-	case AMDGPU_PP_SENSOR_GPU_LOAD:
+-		ret = renoir_get_current_activity_percent(smu, sensor, (uint32_t *)data);
+-		*size = 4;
+-		break;
+-	default:
+-		ret = smu_v12_0_read_sensor(smu, sensor, data, size);
+-	}
+-	mutex_unlock(&smu->sensor_lock);
+-
+-	return ret;
+-}
+ 
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_smu_msg_index = renoir_get_smu_msg_index,
+@@ -794,7 +720,6 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_dpm_clock_table = renoir_get_dpm_clock_table,
+ 	.set_watermarks_table = renoir_set_watermarks_table,
+ 	.get_power_profile_mode = renoir_get_power_profile_mode,
+-	.read_sensor = renoir_read_sensor,
+ 	.check_fw_status = smu_v12_0_check_fw_status,
+ 	.check_fw_version = smu_v12_0_check_fw_version,
+ 	.powergate_sdma = smu_v12_0_powergate_sdma,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 045167311ae8..18b24f954380 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -223,39 +223,6 @@ int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
+ 		SMU_MSG_SetGfxCGPG, enable ? 1 : 0);
+ }
+ 
+-int smu_v12_0_read_sensor(struct smu_context *smu,
+-				 enum amd_pp_sensors sensor,
+-				 void *data, uint32_t *size)
+-{
+-	int ret = 0;
+-
+-	if(!data || !size)
+-		return -EINVAL;
+-
+-	switch (sensor) {
+-	case AMDGPU_PP_SENSOR_GFX_MCLK:
+-		ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
+-		*size = 4;
+-		break;
+-	case AMDGPU_PP_SENSOR_GFX_SCLK:
+-		ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
+-		*size = 4;
+-		break;
+-	case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
+-		*(uint32_t *)data = 0;
+-		*size = 4;
+-		break;
+-	default:
+-		ret = smu_common_read_sensor(smu, sensor, data, size);
+-		break;
+-	}
+-
+-	if (ret)
+-		*size = 0;
+-
+-	return ret;
+-}
+-
+ /**
+  * smu_v12_0_get_gfxoff_status - get gfxoff status
+  *
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4587-drm-amd-powerplay-enable-gpu_busy_percent-sys-interf.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4587-drm-amd-powerplay-enable-gpu_busy_percent-sys-interf.patch
new file mode 100644
index 00000000..9301c8cc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4587-drm-amd-powerplay-enable-gpu_busy_percent-sys-interf.patch
@@ -0,0 +1,201 @@
+From 648728cff5215646111ed6176035e676253a8c60 Mon Sep 17 00:00:00 2001
+From: changzhu <Changfeng.Zhu@amd.com>
+Date: Wed, 13 Nov 2019 17:17:09 +0800
+Subject: [PATCH 4587/4736] drm/amd/powerplay: enable gpu_busy_percent sys
+ interface for renoir (v2)
+
+To get the value of gpu_busy_percent, it needs to realize
+get_current_activity_percent and get_metrics_table.
+The framework of renoir smu is different from old ones like raven. It
+needs to realize get_current_activity_percent and get_metrics_table in
+renoir_ppt.c like navi10.
+
+v2: remove unused variable (Alex)
+
+Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h |  4 +
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c    | 76 +++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c     | 33 ++++++++
+ 3 files changed, 113 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+index 1745e0146fba..44c65dd8850d 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+@@ -62,6 +62,10 @@ int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate);
+ 
+ int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
+ 
++int smu_v12_0_read_sensor(struct smu_context *smu,
++			  enum amd_pp_sensors sensor,
++			  void *data, uint32_t *size);
++
+ uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu);
+ 
+ int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable);
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 2c624cdf1d81..e5ff08820658 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -139,6 +139,27 @@ static int renoir_get_smu_table_index(struct smu_context *smc, uint32_t index)
+ 	return mapping.map_to;
+ }
+ 
++static int renoir_get_metrics_table(struct smu_context *smu,
++				    SmuMetrics_t *metrics_table)
++{
++	struct smu_table_context *smu_table= &smu->smu_table;
++	int ret = 0;
++
++	if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
++		ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
++				(void *)smu_table->metrics_table, false);
++		if (ret) {
++			pr_info("Failed to export SMU metrics table!\n");
++			return ret;
++		}
++		smu_table->metrics_time = jiffies;
++	}
++
++	memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
++
++	return ret;
++}
++
+ static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
+ {
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+@@ -154,6 +175,11 @@ static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
+ 	if (!smu_table->clocks_table)
+ 		return -ENOMEM;
+ 
++	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
++	if (!smu_table->metrics_table)
++		return -ENOMEM;
++	smu_table->metrics_time = 0;
++
+ 	return 0;
+ }
+ 
+@@ -386,6 +412,32 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
+ 	return ret;
+ }
+ 
++static int renoir_get_current_activity_percent(struct smu_context *smu,
++					       enum amd_pp_sensors sensor,
++					       uint32_t *value)
++{
++	int ret = 0;
++	SmuMetrics_t metrics;
++
++	if (!value)
++		return -EINVAL;
++
++	ret = renoir_get_metrics_table(smu, &metrics);
++	if (ret)
++		return ret;
++
++	switch (sensor) {
++	case AMDGPU_PP_SENSOR_GPU_LOAD:
++		*value = metrics.AverageGfxActivity;
++		break;
++	default:
++		pr_err("Invalid sensor for retrieving clock activity\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
+ static int renoir_get_workload_type(struct smu_context *smu, uint32_t profile)
+ {
+ 
+@@ -700,6 +752,29 @@ static int renoir_get_power_profile_mode(struct smu_context *smu,
+ }
+ 
+ 
++static int renoir_read_sensor(struct smu_context *smu,
++				 enum amd_pp_sensors sensor,
++				 void *data, uint32_t *size)
++{
++	int ret = 0;
++
++	if (!data || !size)
++		return -EINVAL;
++
++	mutex_lock(&smu->sensor_lock);
++	switch (sensor) {
++	case AMDGPU_PP_SENSOR_GPU_LOAD:
++		ret = renoir_get_current_activity_percent(smu, sensor, (uint32_t *)data);
++		*size = 4;
++		break;
++	default:
++		ret = smu_v12_0_read_sensor(smu, sensor, data, size);
++	}
++	mutex_unlock(&smu->sensor_lock);
++
++	return ret;
++}
++
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_smu_msg_index = renoir_get_smu_msg_index,
+ 	.get_smu_table_index = renoir_get_smu_table_index,
+@@ -720,6 +795,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_dpm_clock_table = renoir_get_dpm_clock_table,
+ 	.set_watermarks_table = renoir_set_watermarks_table,
+ 	.get_power_profile_mode = renoir_get_power_profile_mode,
++	.read_sensor = renoir_read_sensor,
+ 	.check_fw_status = smu_v12_0_check_fw_status,
+ 	.check_fw_version = smu_v12_0_check_fw_version,
+ 	.powergate_sdma = smu_v12_0_powergate_sdma,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 18b24f954380..045167311ae8 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -223,6 +223,39 @@ int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
+ 		SMU_MSG_SetGfxCGPG, enable ? 1 : 0);
+ }
+ 
++int smu_v12_0_read_sensor(struct smu_context *smu,
++				 enum amd_pp_sensors sensor,
++				 void *data, uint32_t *size)
++{
++	int ret = 0;
++
++	if(!data || !size)
++		return -EINVAL;
++
++	switch (sensor) {
++	case AMDGPU_PP_SENSOR_GFX_MCLK:
++		ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
++		*size = 4;
++		break;
++	case AMDGPU_PP_SENSOR_GFX_SCLK:
++		ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
++		*size = 4;
++		break;
++	case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
++		*(uint32_t *)data = 0;
++		*size = 4;
++		break;
++	default:
++		ret = smu_common_read_sensor(smu, sensor, data, size);
++		break;
++	}
++
++	if (ret)
++		*size = 0;
++
++	return ret;
++}
++
+ /**
+  * smu_v12_0_get_gfxoff_status - get gfxoff status
+  *
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4588-Revert-drm-amdkfd-add-missing-mqd-init-from-kfd-stag.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4588-Revert-drm-amdkfd-add-missing-mqd-init-from-kfd-stag.patch
new file mode 100644
index 00000000..3bfc13c0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4588-Revert-drm-amdkfd-add-missing-mqd-init-from-kfd-stag.patch
@@ -0,0 +1,70 @@
+From 61a5456532d8e58d3d5ec61c43998179d05495be Mon Sep 17 00:00:00 2001
+From: Flora Cui <flora.cui@amd.com>
+Date: Tue, 26 Nov 2019 13:09:09 +0800
+Subject: [PATCH 4588/4736] Revert "drm/amdkfd: add missing mqd init from
+ kfd-staging"
+
+This reverts commit 898a4edbdfcd6361324cebd82ebf2eac30566f5b.
+Signed-off-by: Flora Cui <flora.cui@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c  | 2 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c  | 2 +-
+ 4 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+index 9431dc2ca54b..c8561c3283b2 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+@@ -432,7 +432,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
+ #endif
+ 		break;
+ 	case KFD_MQD_TYPE_DIQ:
+-		mqd->allocate_mqd = allocate_hiq_mqd;
++		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd_hiq;
+ 		mqd->free_mqd = free_mqd;
+ 		mqd->load_mqd = load_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index 0487ddcbfa00..afe2d3bb5c24 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -421,7 +421,7 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+ 		pr_debug("%s@%i\n", __func__, __LINE__);
+ 		break;
+ 	case KFD_MQD_TYPE_DIQ:
+-		mqd->allocate_mqd = allocate_hiq_mqd;
++		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd_hiq;
+ 		mqd->free_mqd = free_mqd;
+ 		mqd->load_mqd = load_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index d8fd332c7b14..5d691d36599f 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -546,7 +546,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
+ #endif
+ 		break;
+ 	case KFD_MQD_TYPE_DIQ:
+-		mqd->allocate_mqd = allocate_hiq_mqd;
++		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd_hiq;
+ 		mqd->free_mqd = free_mqd;
+ 		mqd->load_mqd = load_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+index 6909b79361a7..7c56b850b00f 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+@@ -492,7 +492,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
+ #endif
+ 		break;
+ 	case KFD_MQD_TYPE_DIQ:
+-		mqd->allocate_mqd = allocate_hiq_mqd;
++		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd_hiq;
+ 		mqd->free_mqd = free_mqd;
+ 		mqd->load_mqd = load_mqd;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4589-Revert-drm-amdkfd-add-missing-KFD_MQD_TYPE_COMPUTE.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4589-Revert-drm-amdkfd-add-missing-KFD_MQD_TYPE_COMPUTE.patch
new file mode 100644
index 00000000..ad79aeac
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4589-Revert-drm-amdkfd-add-missing-KFD_MQD_TYPE_COMPUTE.patch
@@ -0,0 +1,122 @@
+From 56423d2187b56d80fc34b4186b5a8ef8941eea4f Mon Sep 17 00:00:00 2001
+From: Flora Cui <flora.cui@amd.com>
+Date: Tue, 26 Nov 2019 13:10:51 +0800
+Subject: [PATCH 4589/4736] Revert "drm/amdkfd: add missing
+ KFD_MQD_TYPE_COMPUTE"
+
+This reverts commit ab30ae4ff91d3fbaffdee54985ce1b0624222bff.
+Signed-off-by: Flora Cui <flora.cui@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 4 ++--
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c      | 3 +--
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c      | 1 -
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c       | 1 -
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c       | 3 +--
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h                 | 3 +--
+ 6 files changed, 5 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 76c7f0ec3de3..f2325e5f15ce 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -1744,7 +1744,7 @@ static int get_wave_state(struct device_queue_manager *dqm,
+ 		goto dqm_unlock;
+ 	}
+ 
+-	mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_COMPUTE];
++	mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
+ 
+ 	if (!mqd_mgr->get_wave_state) {
+ 		r = -EINVAL;
+@@ -2187,7 +2187,7 @@ void copy_context_work_handler (struct work_struct *work)
+ 
+ 
+ 		list_for_each_entry(q, &qpd->queues_list, list) {
+-			mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_COMPUTE];
++			mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
+ 
+ 			/* We ignore the return value from get_wave_state
+ 			 * because
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+index c8561c3283b2..37ce9571a175 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+@@ -403,7 +403,6 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
+ 
+ 	switch (type) {
+ 	case KFD_MQD_TYPE_CP:
+-	case KFD_MQD_TYPE_COMPUTE:
+ 		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd;
+ 		mqd->free_mqd = free_mqd;
+@@ -475,7 +474,7 @@ struct mqd_manager *mqd_manager_init_cik_hawaii(enum KFD_MQD_TYPE type,
+ 	mqd = mqd_manager_init_cik(type, dev);
+ 	if (!mqd)
+ 		return NULL;
+-	if ((type == KFD_MQD_TYPE_CP) || (type == KFD_MQD_TYPE_COMPUTE))
++	if (type == KFD_MQD_TYPE_CP)
+ 		mqd->update_mqd = update_mqd_hawaii;
+ 	return mqd;
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+index afe2d3bb5c24..4677ed90d16c 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+@@ -389,7 +389,6 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
+ 
+ 	switch (type) {
+ 	case KFD_MQD_TYPE_CP:
+-	case KFD_MQD_TYPE_COMPUTE:
+ 		pr_debug("%s@%i\n", __func__, __LINE__);
+ 		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index 5d691d36599f..f9ee530774bf 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -516,7 +516,6 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
+ 
+ 	switch (type) {
+ 	case KFD_MQD_TYPE_CP:
+-	case KFD_MQD_TYPE_COMPUTE:
+ 		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd;
+ 		mqd->free_mqd = free_mqd;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+index 7c56b850b00f..2aeba387d7d6 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+@@ -462,7 +462,6 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
+ 
+ 	switch (type) {
+ 	case KFD_MQD_TYPE_CP:
+-	case KFD_MQD_TYPE_COMPUTE:
+ 		mqd->allocate_mqd = allocate_mqd;
+ 		mqd->init_mqd = init_mqd;
+ 		mqd->free_mqd = free_mqd;
+@@ -535,7 +534,7 @@ struct mqd_manager *mqd_manager_init_vi_tonga(enum KFD_MQD_TYPE type,
+ 	mqd = mqd_manager_init_vi(type, dev);
+ 	if (!mqd)
+ 		return NULL;
+-	if ((type == KFD_MQD_TYPE_CP) || (type == KFD_MQD_TYPE_COMPUTE))
++	if (type == KFD_MQD_TYPE_CP)
+ 		mqd->update_mqd = update_mqd_tonga;
+ 	return mqd;
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+index e937679f8ca1..b91029047953 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+@@ -576,8 +576,7 @@ struct queue {
+  * Please read the kfd_mqd_manager.h description.
+  */
+ enum KFD_MQD_TYPE {
+-	KFD_MQD_TYPE_COMPUTE = 0,	/* for no cp scheduling */
+-	KFD_MQD_TYPE_HIQ,		/* for hiq */
++	KFD_MQD_TYPE_HIQ = 0,		/* for hiq */
+ 	KFD_MQD_TYPE_CP,		/* for cp queues and diq */
+ 	KFD_MQD_TYPE_SDMA,		/* for sdma queues */
+ 	KFD_MQD_TYPE_DIQ,		/* for diq */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4590-drm-amd-amdgpu-sriov-skip-jpeg-ip-block-for-ARCTURUS.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4590-drm-amd-amdgpu-sriov-skip-jpeg-ip-block-for-ARCTURUS.patch
new file mode 100644
index 00000000..f0e03550
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4590-drm-amd-amdgpu-sriov-skip-jpeg-ip-block-for-ARCTURUS.patch
@@ -0,0 +1,32 @@
+From 677928bc86ece7e295bac905e8c9017e41bf9e42 Mon Sep 17 00:00:00 2001
+From: Jack Zhang <Jack.Zhang1@amd.com>
+Date: Tue, 26 Nov 2019 14:47:29 +0800
+Subject: [PATCH 4590/4736] drm/amd/amdgpu/sriov skip jpeg ip block for
+ ARCTURUS VF
+
+Currently ARCTURUS VF doesn't support jpeg ip block.
+Skip jpeg ip block in case guest driver load fail.
+
+Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
+Reviewed-by: Zhexi Zhang <zhexi.zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 805a92f87bf3..3a2ec932c0bb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -833,7 +833,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ 
+ 		if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT))
+ 			amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
+-		amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
++		if (!amdgpu_sriov_vf(adev))
++			amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
+ 		break;
+ 	case CHIP_RENOIR:
+ 		amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4591-drm-amdgpu-Resolved-offchip-EEPROM-I-O-issue.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4591-drm-amdgpu-Resolved-offchip-EEPROM-I-O-issue.patch
new file mode 100644
index 00000000..34ad9b8b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4591-drm-amdgpu-Resolved-offchip-EEPROM-I-O-issue.patch
@@ -0,0 +1,104 @@
+From 323de75bf9aaa107e8d18e3b9596a3ac2d30d578 Mon Sep 17 00:00:00 2001
+From: John Clements <john.clements@amd.com>
+Date: Mon, 25 Nov 2019 18:24:17 +0800
+Subject: [PATCH 4591/4736] drm/amdgpu: Resolved offchip EEPROM I/O issue
+
+Updated target I2C address
+
+Change-Id: Ie86f7f3214177e3902b02a6b8201421375a89ae4
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: John Clements <john.clements@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 17 ++++++++++++-----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h |  1 +
+ 2 files changed, 13 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+index 7de16c0c2f20..2a8e04895595 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+@@ -27,7 +27,8 @@
+ #include <linux/bits.h>
+ #include "smu_v11_0_i2c.h"
+ 
+-#define EEPROM_I2C_TARGET_ADDR 0xA0
++#define EEPROM_I2C_TARGET_ADDR_ARCTURUS  0xA8
++#define EEPROM_I2C_TARGET_ADDR_VEGA20    0xA0
+ 
+ /*
+  * The 2 macros bellow represent the actual size in bytes that
+@@ -83,7 +84,7 @@ static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
+ {
+ 	int ret = 0;
+ 	struct i2c_msg msg = {
+-			.addr	= EEPROM_I2C_TARGET_ADDR,
++			.addr	= 0,
+ 			.flags	= 0,
+ 			.len	= EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
+ 			.buf	= buff,
+@@ -93,6 +94,8 @@ static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
+ 	*(uint16_t *)buff = EEPROM_HDR_START;
+ 	__encode_table_header_to_buff(&control->tbl_hdr, buff + EEPROM_ADDRESS_SIZE);
+ 
++	msg.addr = control->i2c_address;
++
+ 	ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);
+ 	if (ret < 1)
+ 		DRM_ERROR("Failed to write EEPROM table header, ret:%d", ret);
+@@ -203,7 +206,7 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
+ 	unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };
+ 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
+ 	struct i2c_msg msg = {
+-			.addr	= EEPROM_I2C_TARGET_ADDR,
++			.addr	= 0,
+ 			.flags	= I2C_M_RD,
+ 			.len	= EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
+ 			.buf	= buff,
+@@ -213,10 +216,12 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_VEGA20:
++		control->i2c_address = EEPROM_I2C_TARGET_ADDR_VEGA20;
+ 		ret = smu_v11_0_i2c_eeprom_control_init(&control->eeprom_accessor);
+ 		break;
+ 
+ 	case CHIP_ARCTURUS:
++		control->i2c_address = EEPROM_I2C_TARGET_ADDR_ARCTURUS;
+ 		ret = smu_i2c_eeprom_init(&adev->smu, &control->eeprom_accessor);
+ 		break;
+ 
+@@ -229,6 +234,8 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
+ 		return ret;
+ 	}
+ 
++	msg.addr = control->i2c_address;
++
+ 	/* Read/Create table header from EEPROM address 0 */
+ 	ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);
+ 	if (ret < 1) {
+@@ -408,8 +415,8 @@ int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
+ 		 * Update bits 16,17 of EEPROM address in I2C address by setting them
+ 		 * to bits 1,2 of Device address byte
+ 		 */
+-		msg->addr = EEPROM_I2C_TARGET_ADDR |
+-			       ((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15);
++		msg->addr = control->i2c_address |
++			        ((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15);
+ 		msg->flags	= write ? 0 : I2C_M_RD;
+ 		msg->len	= EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE;
+ 		msg->buf	= buff;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
+index 622269957c1b..ca78f812d436 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
+@@ -50,6 +50,7 @@ struct amdgpu_ras_eeprom_control {
+ 	struct mutex tbl_mutex;
+ 	bool bus_locked;
+ 	uint32_t tbl_byte_sum;
++	uint16_t i2c_address; // 8-bit represented address
+ };
+ 
+ /*
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4592-drm-amd-Fix-Kconfig-indentation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4592-drm-amd-Fix-Kconfig-indentation.patch
new file mode 100644
index 00000000..fd49f296
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4592-drm-amd-Fix-Kconfig-indentation.patch
@@ -0,0 +1,40 @@
+From 61f5f09dcccbda3755e7989735e4e053161a288a Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzk@kernel.org>
+Date: Thu, 21 Nov 2019 21:29:30 +0800
+Subject: [PATCH 4592/4736] drm/amd: Fix Kconfig indentation
+
+Adjust indentation from spaces to tab (+optional two spaces) as in
+coding style with command like:
+	$ sed -e 's/^        /\t/' -i */Kconfig
+
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/acp/Kconfig | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/acp/Kconfig b/drivers/gpu/drm/amd/acp/Kconfig
+index e503e3d6d920..fc1f9194781e 100644
+--- a/drivers/gpu/drm/amd/acp/Kconfig
++++ b/drivers/gpu/drm/amd/acp/Kconfig
+@@ -1,11 +1,11 @@
+ menu "ACP (Audio CoProcessor) Configuration"
+ 
+ config DRM_AMD_ACP
+-       bool "Enable AMD Audio CoProcessor IP support"
+-       depends on DRM_AMDGPU
+-       select MFD_CORE
+-       select PM_GENERIC_DOMAINS if PM
+-       help
++	bool "Enable AMD Audio CoProcessor IP support"
++	depends on DRM_AMDGPU
++	select MFD_CORE
++	select PM_GENERIC_DOMAINS if PM
++	help
+ 	Choose this option to enable ACP IP support for AMD SOCs.
+ 	This adds the ACP (Audio CoProcessor) IP driver and wires
+ 	it up into the amdgpu driver.  The ACP block provides the DMA
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4593-MAINTAINERS-Drop-Rex-Zhu-for-amdgpu-powerplay.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4593-MAINTAINERS-Drop-Rex-Zhu-for-amdgpu-powerplay.patch
new file mode 100644
index 00000000..ba63b9af
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4593-MAINTAINERS-Drop-Rex-Zhu-for-amdgpu-powerplay.patch
@@ -0,0 +1,29 @@
+From 3268488a9583dccd84309eac3af94a5910042a2a Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 22 Nov 2019 14:16:55 -0500
+Subject: [PATCH 4593/4736] MAINTAINERS: Drop Rex Zhu for amdgpu powerplay
+
+No longer works on the driver.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ MAINTAINERS | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 38f553e09240..3a4c825b520b 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -786,7 +786,6 @@ F:	drivers/gpu/drm/amd/include/v9_structs.h
+ F:	include/uapi/linux/kfd_ioctl.h
+ 
+ AMD POWERPLAY
+-M:	Rex Zhu <rex.zhu@amd.com>
+ M:	Evan Quan <evan.quan@amd.com>
+ L:	amd-gfx@lists.freedesktop.org
+ S:	Supported
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4594-drm-amd-powerplay-remove-redundant-assignment-to-var.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4594-drm-amd-powerplay-remove-redundant-assignment-to-var.patch
new file mode 100644
index 00000000..67733212
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4594-drm-amd-powerplay-remove-redundant-assignment-to-var.patch
@@ -0,0 +1,35 @@
+From bf8c2ee372d7c70161ef6f75da978bdaa925d9c0 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Fri, 22 Nov 2019 23:04:07 +0000
+Subject: [PATCH 4594/4736] drm/amd/powerplay: remove redundant assignment to
+ variables HiSidd and LoSidd
+
+The variables HiSidd and LoSidd are being initialized with values that
+are never read and are being updated a little later with a new value.
+The initialization is redundant and can be removed.
+
+Addresses-Coverity: ("Unused value")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+index edc5fba0f3e1..405bae2872b3 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+@@ -652,8 +652,8 @@ static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct pp_hwmgr *hwmgr)
+ static int ci_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
+ {
+ 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
+-	uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
+-	uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
++	uint16_t HiSidd;
++	uint16_t LoSidd;
+ 	struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table;
+ 
+ 	HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4595-drm-amdgpu-Ensure-ret-is-always-initialized-when-usi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4595-drm-amdgpu-Ensure-ret-is-always-initialized-when-usi.patch
new file mode 100644
index 00000000..3a317415
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4595-drm-amdgpu-Ensure-ret-is-always-initialized-when-usi.patch
@@ -0,0 +1,64 @@
+From 6c13d7d3ba65090b6817972126a06f380f8e20b8 Mon Sep 17 00:00:00 2001
+From: Nathan Chancellor <natechancellor@gmail.com>
+Date: Sat, 23 Nov 2019 12:23:36 -0700
+Subject: [PATCH 4595/4736] drm/amdgpu: Ensure ret is always initialized when
+ using SOC15_WAIT_ON_RREG
+
+Commit b0f3cd3191cd ("drm/amdgpu: remove unnecessary JPEG2.0 code from
+VCN2.0") introduced a new clang warning in the vcn_v2_0_stop function:
+
+../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1082:2: warning: variable 'r'
+is used uninitialized whenever 'while' loop exits because its condition
+is false [-Wsometimes-uninitialized]
+        SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
+        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+../drivers/gpu/drm/amd/amdgpu/../amdgpu/soc15_common.h:55:10: note:
+expanded from macro 'SOC15_WAIT_ON_RREG'
+                while ((tmp_ & (mask)) != (expected_value)) {   \
+                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1083:6: note: uninitialized use
+occurs here
+        if (r)
+            ^
+../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1082:2: note: remove the
+condition if it is always true
+        SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
+        ^
+../drivers/gpu/drm/amd/amdgpu/../amdgpu/soc15_common.h:55:10: note:
+expanded from macro 'SOC15_WAIT_ON_RREG'
+                while ((tmp_ & (mask)) != (expected_value)) {   \
+                       ^
+../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1072:7: note: initialize the
+variable 'r' to silence this warning
+        int r;
+             ^
+              = 0
+1 warning generated.
+
+To prevent warnings like this from happening in the future, make the
+SOC15_WAIT_ON_RREG macro initialize its ret variable before the while
+loop that can time out. This macro's return value is always checked so
+it should set ret in both the success and fail path.
+
+Link: https://github.com/ClangBuiltLinux/linux/issues/776
+Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15_common.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+index 839f186e1182..19e870c79896 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
++++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+@@ -52,6 +52,7 @@
+ 		uint32_t old_ = 0;	\
+ 		uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
+ 		uint32_t loop = adev->usec_timeout;		\
++		ret = 0;					\
+ 		while ((tmp_ & (mask)) != (expected_value)) {	\
+ 			if (old_ != tmp_) {			\
+ 				loop = adev->usec_timeout;	\
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4596-drm-amd-display-remove-set-but-not-used-variable-msg.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4596-drm-amd-display-remove-set-but-not-used-variable-msg.patch
new file mode 100644
index 00000000..c6bf1407
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4596-drm-amd-display-remove-set-but-not-used-variable-msg.patch
@@ -0,0 +1,57 @@
+From 2444f631c300021dccd5fe68688bd78bf1da8da3 Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Mon, 25 Nov 2019 22:54:45 +0800
+Subject: [PATCH 4596/4736] drm/amd/display: remove set but not used variable
+ 'msg_out'
+
+drivers/gpu/drm/amd/amdgpu/../display/modules/hdcp/hdcp_psp.c: In function mod_hdcp_hdcp2_enable_encryption:
+drivers/gpu/drm/amd/amdgpu/../display/modules/hdcp/hdcp_psp.c:633:77: warning: variable msg_out set but not used [-Wunused-but-set-variable]
+drivers/gpu/drm/amd/amdgpu/../display/modules/hdcp/hdcp_psp.c: In function mod_hdcp_hdcp2_enable_dp_stream_encryption:
+drivers/gpu/drm/amd/amdgpu/../display/modules/hdcp/hdcp_psp.c:710:77: warning: variable msg_out set but not used [-Wunused-but-set-variable]
+
+It is never used, so remove it.
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+index 2dd5feec8e6c..468f5e6c3487 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+@@ -630,14 +630,12 @@ enum mod_hdcp_status mod_hdcp_hdcp2_enable_encryption(struct mod_hdcp *hdcp)
+ 	struct psp_context *psp = hdcp->config.psp.handle;
+ 	struct ta_hdcp_shared_memory *hdcp_cmd;
+ 	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
+-	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
+ 	struct mod_hdcp_display *display = get_first_added_display(hdcp);
+ 
+ 	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
+ 	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
+ 
+ 	msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
+-	msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
+ 
+ 	hdcp2_message_init(hdcp, msg_in);
+ 
+@@ -707,14 +705,12 @@ enum mod_hdcp_status mod_hdcp_hdcp2_enable_dp_stream_encryption(struct mod_hdcp
+ 	struct psp_context *psp = hdcp->config.psp.handle;
+ 	struct ta_hdcp_shared_memory *hdcp_cmd;
+ 	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_input_v2 *msg_in;
+-	struct ta_hdcp_cmd_hdcp2_process_prepare_authentication_message_output_v2 *msg_out;
+ 	uint8_t i;
+ 
+ 	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.hdcp_shared_buf;
+ 	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
+ 
+ 	msg_in = &hdcp_cmd->in_msg.hdcp2_prepare_process_authentication_message_v2;
+-	msg_out = &hdcp_cmd->out_msg.hdcp2_prepare_process_authentication_message_v2;
+ 
+ 	hdcp2_message_init(hdcp, msg_in);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4597-drm-amd-powerplay-remove-set-but-not-used-variable-s.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4597-drm-amd-powerplay-remove-set-but-not-used-variable-s.patch
new file mode 100644
index 00000000..e28b485d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4597-drm-amd-powerplay-remove-set-but-not-used-variable-s.patch
@@ -0,0 +1,50 @@
+From 73bbe069ff269e69ba108a150cd3139433d09930 Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Mon, 25 Nov 2019 22:58:43 +0800
+Subject: [PATCH 4597/4736] drm/amd/powerplay: remove set but not used variable
+ 'stretch_amount2'
+
+drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/vegam_smumgr.c:
+ In function vegam_populate_clock_stretcher_data_table:
+drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/vegam_smumgr.c:1489:29:
+ warning: variable stretch_amount2 set but not used [-Wunused-but-set-variable]
+
+It is never used, so can be removed.
+
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+index 50896e9b2579..b0e0d67cd54b 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+@@ -1486,7 +1486,7 @@ static int vegam_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
+ 	struct vegam_smumgr *smu_data =
+ 			(struct vegam_smumgr *)(hwmgr->smu_backend);
+ 
+-	uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
++	uint8_t i, stretch_amount, volt_offset = 0;
+ 	struct phm_ppt_v1_information *table_info =
+ 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
+ 	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
+@@ -1525,11 +1525,9 @@ static int vegam_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
+ 			(table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ?
+ 			table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 5;
+ 	/* Populate CKS Lookup Table */
+-	if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
+-		stretch_amount2 = 0;
+-	else if (stretch_amount == 3 || stretch_amount == 4)
+-		stretch_amount2 = 1;
+-	else {
++	if (!(stretch_amount == 1 || stretch_amount == 2 ||
++	      stretch_amount == 5 || stretch_amount == 3 ||
++	      stretch_amount == 4)) {
+ 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ 				PHM_PlatformCaps_ClockStretcher);
+ 		PP_ASSERT_WITH_CODE(false,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4598-drm-amd-display-Null-check-aconnector-in-event_prope.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4598-drm-amd-display-Null-check-aconnector-in-event_prope.patch
new file mode 100644
index 00000000..280900f7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4598-drm-amd-display-Null-check-aconnector-in-event_prope.patch
@@ -0,0 +1,42 @@
+From a274fbfefeca017c09c8536ac85dce2fcf9866c7 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Mon, 25 Nov 2019 10:34:13 -0500
+Subject: [PATCH 4598/4736] drm/amd/display: Null check aconnector in
+ event_property_validate
+
+[Why]
+previously event_property_validate was only called after we enabled the display.
+But after "Refactor HDCP to handle multiple displays per link" this function
+can be called at any time. In certain cases we don't have a aconnector
+
+[How]
+Null check aconnector and exit early. This is ok because we only need to check the
+ENABLED->DESIRED transition if a connector exists.
+
+Fixes: cc5dae9f6286 ("drm/amd/display: Refactor HDCP to handle multiple
+displays per link")
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+index f6864a51891a..ae329335dfcc 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+@@ -225,6 +225,9 @@ static void event_property_validate(struct work_struct *work)
+ 	struct mod_hdcp_display_query query;
+ 	struct amdgpu_dm_connector *aconnector = hdcp_work->aconnector;
+ 
++	if (!aconnector)
++		return;
++
+ 	mutex_lock(&hdcp_work->mutex);
+ 
+ 	query.encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4599-drm-amdgpu-Raise-KFD-unpinned-system-memory-limit.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4599-drm-amdgpu-Raise-KFD-unpinned-system-memory-limit.patch
new file mode 100644
index 00000000..f46adc4b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4599-drm-amdgpu-Raise-KFD-unpinned-system-memory-limit.patch
@@ -0,0 +1,39 @@
+From eeef2304ec82d7aa4a53e26d1500cd431baeb7d0 Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Mon, 25 Nov 2019 16:25:35 -0500
+Subject: [PATCH 4599/4736] drm/amdgpu: Raise KFD unpinned system memory limit
+
+Allow KFD applications to use more unpinned system memory through
+HMM.
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index 083bd8fe8057..a0d138849b61 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -85,7 +85,7 @@ static bool check_if_add_bo_to_vm(struct amdgpu_vm *avm,
+ }
+ 
+ /* Set memory usage limits. Current, limits are
+- *  System (TTM + userptr) memory - 3/4th System RAM
++ *  System (TTM + userptr) memory - 15/16th System RAM
+  *  TTM memory - 3/8th System RAM
+  */
+ void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
+@@ -98,7 +98,7 @@ void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
+ 	mem *= si.mem_unit;
+ 
+ 	spin_lock_init(&kfd_mem_limit.mem_limit_lock);
+-	kfd_mem_limit.max_system_mem_limit = (mem >> 1) + (mem >> 2);
++	kfd_mem_limit.max_system_mem_limit = mem - (mem >> 4);
+ 	kfd_mem_limit.max_ttm_mem_limit = (mem >> 1) - (mem >> 3);
+ 	pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
+ 		(kfd_mem_limit.max_system_mem_limit >> 20),
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4600-drm-amdgpu-Optimize-KFD-page-table-reservation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4600-drm-amdgpu-Optimize-KFD-page-table-reservation.patch
new file mode 100644
index 00000000..5f502cc7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4600-drm-amdgpu-Optimize-KFD-page-table-reservation.patch
@@ -0,0 +1,53 @@
+From 2bd2c52721418a622b717d892211569b53db0120 Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Mon, 15 Jul 2019 16:18:03 -0400
+Subject: [PATCH 4600/4736] drm/amdgpu: Optimize KFD page table reservation
+
+Be less pessimistic about estimated page table use for KFD. Most
+allocations use 2MB pages and therefore need less VRAM for page
+tables. This allows more VRAM to be used for applications especially
+on large systems with many GPUs and hundreds of GB of system memory.
+
+Example: 8 GPUs with 32GB VRAM each + 256GB system memory = 512GB
+Old page table reservation per GPU:  1GB
+New page table reservation per GPU: 32MB
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: xinhui pan <xinhui.pan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 15 ++++++++++++++-
+ 1 file changed, 14 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index a0d138849b61..3d7d6b5f423e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -105,11 +105,24 @@ void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
+ 		(kfd_mem_limit.max_ttm_mem_limit >> 20));
+ }
+ 
++/* Estimate page table size needed to represent a given memory size
++ *
++ * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
++ * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
++ * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
++ * for 2MB pages for TLB efficiency. However, small allocations and
++ * fragmented system memory still need some 4KB pages. We choose a
++ * compromise that should work in most cases without reserving too
++ * much memory for page tables unnecessarily (factor 16K, >> 14).
++ */
++#define ESTIMATE_PT_SIZE(mem_size) ((mem_size) >> 14)
++
+ static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
+ 		uint64_t size, u32 domain, bool sg)
+ {
++	uint64_t reserved_for_pt =
++		ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
+ 	size_t acc_size, system_mem_needed, ttm_mem_needed, vram_needed;
+-	uint64_t reserved_for_pt = amdgpu_amdkfd_total_mem_size >> 9;
+ 	int ret = 0;
+ 
+ 	acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4601-drm-amdgpu-apply-gpr-gds-workaround-before-enabling-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4601-drm-amdgpu-apply-gpr-gds-workaround-before-enabling-.patch
new file mode 100644
index 00000000..bb6a097d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4601-drm-amdgpu-apply-gpr-gds-workaround-before-enabling-.patch
@@ -0,0 +1,45 @@
+From 4dfd7149c57f60d4a25d860971f03613a5c15f77 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Wed, 20 Nov 2019 19:21:35 +0800
+Subject: [PATCH 4601/4736] drm/amdgpu: apply gpr/gds workaround before
+ enabling GFX EDC mode
+
+gfx memory should be initialized before enabling
+DED and FUE field in mmGB_EDC_MODE
+
+Change-Id: I248a087364cbd9858cba32a70be456af3f07c90d
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 18490f23e0d9..1aff77c89e7a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4238,10 +4238,6 @@ static int gfx_v9_0_ecc_late_init(void *handle)
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 	int r;
+ 
+-	r = amdgpu_gfx_ras_late_init(adev);
+-	if (r)
+-		return r;
+-
+ 	r = gfx_v9_0_do_edc_gds_workarounds(adev);
+ 	if (r)
+ 		return r;
+@@ -4251,6 +4247,10 @@ static int gfx_v9_0_ecc_late_init(void *handle)
+ 	if (r)
+ 		return r;
+ 
++	r = amdgpu_gfx_ras_late_init(adev);
++	if (r)
++		return r;
++
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4602-drm-amdgpu-move-pci-handling-out-of-pm-ops.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4602-drm-amdgpu-move-pci-handling-out-of-pm-ops.patch
new file mode 100644
index 00000000..1784d283
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4602-drm-amdgpu-move-pci-handling-out-of-pm-ops.patch
@@ -0,0 +1,196 @@
+From baf01d88b72d9251f4ea6c51dc64dce686617e87 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 20 Nov 2019 17:31:11 -0500
+Subject: [PATCH 4602/4736] drm/amdgpu: move pci handling out of pm ops
+
+The documentation says the that PCI core handles this
+for you unless you choose to implement it.  Just rely
+on the PCI core to handle the pci specific bits.
+
+Reviewed-by: Zhan Liu <zhan.liu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  4 +--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 33 +++++++++-------------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c    | 16 +++++------
+ 3 files changed, 24 insertions(+), 29 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index ccb1fd7cd2b6..553d93a45e64 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1232,8 +1232,8 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
+ void amdgpu_driver_postclose_kms(struct drm_device *dev,
+ 				 struct drm_file *file_priv);
+ int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
+-int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
+-int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
++int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
++int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
+ u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
+ int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
+ void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 3f587dce39e2..bb04f9bb038c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1090,6 +1090,7 @@ static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
+ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
+ {
+ 	struct drm_device *dev = pci_get_drvdata(pdev);
++	int r;
+ 
+ 	if (amdgpu_device_supports_boco(dev) && state == VGA_SWITCHEROO_OFF)
+ 		return;
+@@ -1099,7 +1100,12 @@ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switchero
+ 		/* don't suspend or resume card normally */
+ 		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+ 
+-		amdgpu_device_resume(dev, true, true);
++		pci_set_power_state(dev->pdev, PCI_D0);
++		pci_restore_state(dev->pdev);
++		r = pci_enable_device(dev->pdev);
++		if (r)
++			DRM_WARN("pci_enable_device failed (%d)\n", r);
++		amdgpu_device_resume(dev, true);
+ 
+ 		dev->switch_power_state = DRM_SWITCH_POWER_ON;
+ 		drm_kms_helper_poll_enable(dev);
+@@ -1107,7 +1113,11 @@ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switchero
+ 		pr_info("amdgpu: switched off\n");
+ 		drm_kms_helper_poll_disable(dev);
+ 		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+-		amdgpu_device_suspend(dev, true, true);
++		amdgpu_device_suspend(dev, true);
++		pci_save_state(dev->pdev);
++		/* Shut down the device */
++		pci_disable_device(dev->pdev);
++		pci_set_power_state(dev->pdev, PCI_D3cold);
+ 		dev->switch_power_state = DRM_SWITCH_POWER_OFF;
+ 	}
+ }
+@@ -3203,7 +3213,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
+  * Returns 0 for success or an error on failure.
+  * Called at driver suspend.
+  */
+-int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
++int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
+ {
+ 	struct amdgpu_device *adev;
+ 	struct drm_crtc *crtc;
+@@ -3286,13 +3296,6 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
+ 	 */
+ 	amdgpu_bo_evict_vram(adev);
+ 
+-	if (suspend) {
+-		pci_save_state(dev->pdev);
+-		/* Shut down the device */
+-		pci_disable_device(dev->pdev);
+-		pci_set_power_state(dev->pdev, PCI_D3hot);
+-	}
+-
+ 	return 0;
+ }
+ 
+@@ -3307,7 +3310,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
+  * Returns 0 for success or an error on failure.
+  * Called at driver resume.
+  */
+-int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
++int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
+ {
+ 	struct drm_connector *connector;
+ 	struct drm_connector_list_iter iter;
+@@ -3318,14 +3321,6 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
+ 	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
+ 		return 0;
+ 
+-	if (resume) {
+-		pci_set_power_state(dev->pdev, PCI_D0);
+-		pci_restore_state(dev->pdev);
+-		r = pci_enable_device(dev->pdev);
+-		if (r)
+-			return r;
+-	}
+-
+ 	/* post card */
+ 	if (amdgpu_device_need_post(adev)) {
+ 		r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 4ca9b9bde917..25c206d0fdfd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -1192,7 +1192,7 @@ static int amdgpu_pmops_suspend(struct device *dev)
+ {
+ 	struct drm_device *drm_dev = dev_get_drvdata(dev);
+ 
+-	return amdgpu_device_suspend(drm_dev, true, true);
++	return amdgpu_device_suspend(drm_dev, true);
+ }
+ 
+ static int amdgpu_pmops_resume(struct device *dev)
+@@ -1207,7 +1207,7 @@ static int amdgpu_pmops_resume(struct device *dev)
+ 		pm_runtime_enable(dev);
+ 	}
+ 
+-	return amdgpu_device_resume(drm_dev, true, true);
++	return amdgpu_device_resume(drm_dev, true);
+ }
+ 
+ static int amdgpu_pmops_freeze(struct device *dev)
+@@ -1216,7 +1216,7 @@ static int amdgpu_pmops_freeze(struct device *dev)
+ 	struct amdgpu_device *adev = drm_dev->dev_private;
+ 	int r;
+ 
+-	r = amdgpu_device_suspend(drm_dev, false, true);
++	r = amdgpu_device_suspend(drm_dev, true);
+ 	if (r)
+ 		return r;
+ 	return amdgpu_asic_reset(adev);
+@@ -1226,21 +1226,21 @@ static int amdgpu_pmops_thaw(struct device *dev)
+ {
+ 	struct drm_device *drm_dev = dev_get_drvdata(dev);
+ 
+-	return amdgpu_device_resume(drm_dev, false, true);
++	return amdgpu_device_resume(drm_dev, true);
+ }
+ 
+ static int amdgpu_pmops_poweroff(struct device *dev)
+ {
+ 	struct drm_device *drm_dev = dev_get_drvdata(dev);
+ 
+-	return amdgpu_device_suspend(drm_dev, true, true);
++	return amdgpu_device_suspend(drm_dev, true);
+ }
+ 
+ static int amdgpu_pmops_restore(struct device *dev)
+ {
+ 	struct drm_device *drm_dev = dev_get_drvdata(dev);
+ 
+-	return amdgpu_device_resume(drm_dev, false, true);
++	return amdgpu_device_resume(drm_dev, true);
+ }
+ 
+ static int amdgpu_pmops_runtime_suspend(struct device *dev)
+@@ -1259,7 +1259,7 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)
+ 		drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+ 	drm_kms_helper_poll_disable(drm_dev);
+ 
+-	ret = amdgpu_device_suspend(drm_dev, false, false);
++	ret = amdgpu_device_suspend(drm_dev, false);
+ 	if (amdgpu_device_supports_boco(drm_dev)) {
+ 		/* Only need to handle PCI state in the driver for ATPX
+ 		 * PCI core handles it for _PR3.
+@@ -1309,7 +1309,7 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
+ 	} else if (amdgpu_device_supports_baco(drm_dev)) {
+ 		amdgpu_device_baco_exit(drm_dev);
+ 	}
+-	ret = amdgpu_device_resume(drm_dev, false, false);
++	ret = amdgpu_device_resume(drm_dev, false);
+ 	drm_kms_helper_poll_enable(drm_dev);
+ 	if (amdgpu_device_supports_boco(drm_dev))
+ 		drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4603-drm-amdgpu-flag-vram-lost-on-baco-reset-for-VI-CIK.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4603-drm-amdgpu-flag-vram-lost-on-baco-reset-for-VI-CIK.patch
new file mode 100644
index 00000000..253523f6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4603-drm-amdgpu-flag-vram-lost-on-baco-reset-for-VI-CIK.patch
@@ -0,0 +1,62 @@
+From 8743a9f301867b65a7a690d147237052a6e5d999 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 25 Nov 2019 11:11:18 -0500
+Subject: [PATCH 4603/4736] drm/amdgpu: flag vram lost on baco reset for VI/CIK
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+VI/CIK BACO was inflight when this fix landed for SOC15/NV.
+Add the fix to VI/CIK as well.
+
+Acked-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/cik.c | 7 +++++--
+ drivers/gpu/drm/amd/amdgpu/vi.c  | 7 +++++--
+ 2 files changed, 10 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
+index a5162412989b..51cbcd36f3d0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik.c
+@@ -1362,10 +1362,13 @@ static int cik_asic_reset(struct amdgpu_device *adev)
+ {
+ 	int r;
+ 
+-	if (cik_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
++	if (cik_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
++		if (!adev->in_suspend)
++			amdgpu_inc_vram_lost(adev);
+ 		r = smu7_asic_baco_reset(adev);
+-	else
++	} else {
+ 		r = cik_asic_pci_config_reset(adev);
++	}
+ 
+ 	return r;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
+index 14228bca071b..461f13d7366a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vi.c
++++ b/drivers/gpu/drm/amd/amdgpu/vi.c
+@@ -802,10 +802,13 @@ static int vi_asic_reset(struct amdgpu_device *adev)
+ {
+ 	int r;
+ 
+-	if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
++	if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
++		if (!adev->in_suspend)
++			amdgpu_inc_vram_lost(adev);
+ 		r = smu7_asic_baco_reset(adev);
+-	else
++	} else {
+ 		r = vi_asic_pci_config_reset(adev);
++	}
+ 
+ 	return r;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4604-drm-amdgpu-Fix-a-bug-in-jpeg_v1_0_start.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4604-drm-amdgpu-Fix-a-bug-in-jpeg_v1_0_start.patch
new file mode 100644
index 00000000..4629cf2c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4604-drm-amdgpu-Fix-a-bug-in-jpeg_v1_0_start.patch
@@ -0,0 +1,32 @@
+From ae732308d0383f698a48078008fd6e79089e46cc Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Tue, 26 Nov 2019 15:10:29 +0300
+Subject: [PATCH 4604/4736] drm/amdgpu: Fix a bug in jpeg_v1_0_start()
+
+Originally the last WREG32_SOC15() was a part of the if statement block
+but the curly braces are on the wrong line.
+
+Fixes: bb0db70f3f75 ("drm/amdgpu: separate JPEG1.0 code out from VCN1.0")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
+index 553506df077d..a141408dfb23 100644
+--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
+@@ -522,7 +522,8 @@ void jpeg_v1_0_start(struct amdgpu_device *adev, int mode)
+ 		WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
+ 		WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
+ 		WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
+-	}	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
++		WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
++	}
+ 
+ 	/* initialize wptr */
+ 	ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4605-drm-amd-display-Modify-comments-to-match-the-code.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4605-drm-amd-display-Modify-comments-to-match-the-code.patch
new file mode 100644
index 00000000..b4ff537e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4605-drm-amd-display-Modify-comments-to-match-the-code.patch
@@ -0,0 +1,42 @@
+From 8b35343eac17af3e2aabd323fbf6d3dba5d8fe6b Mon Sep 17 00:00:00 2001
+From: Zhan liu <zhan.liu@amd.com>
+Date: Mon, 25 Nov 2019 17:25:18 -0500
+Subject: [PATCH 4605/4736] drm/amd/display: Modify comments to match the code
+
+[Why]
+This line of code was modified. However, comments
+remained unchanged. As a result, comments and code are
+mismatching.
+
+[How]
+Modifying comments to reflect code. At the same time,
+explaining why the value was changed from 200ms to
+3000ms.
+
+Signed-off-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc_helper.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
+index 24e4684034f5..acdedd889716 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
++++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
+@@ -482,7 +482,12 @@ void generic_reg_wait(const struct dc_context *ctx,
+ 		return;
+ 	}
+ 
+-	/* something is terribly wrong if time out is > 200ms. (5Hz) */
++	/*
++	 * Something is terribly wrong if time out is > 3000ms.
++	 * 3000ms is the maximum time needed for SMU to pass values back.
++	 * This value comes from experiments.
++	 *
++	 */
+ 	ASSERT(delay_between_poll_us * time_out_num_tries <= 3000000);
+ 
+ 	for (i = 0; i <= time_out_num_tries; i++) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4606-drm-amdkfd-Eliminate-unnecessary-kernel-queue-functi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4606-drm-amdkfd-Eliminate-unnecessary-kernel-queue-functi.patch
new file mode 100644
index 00000000..721de83b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4606-drm-amdkfd-Eliminate-unnecessary-kernel-queue-functi.patch
@@ -0,0 +1,417 @@
+From 858f55ddeac45eaca40516c74fd835777960e429 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Fri, 8 Nov 2019 00:30:49 -0500
+Subject: [PATCH 4606/4736] drm/amdkfd: Eliminate unnecessary kernel queue
+ function pointers v2
+
+Up to this point, those functions are all the same for all ASICs, so
+no need to call them by functions pointers. Removing the function
+pointers will greatly increase the code readablity. If there is ever
+need for those function pointers, we can add it back then.
+
+v2: Adapt for amd-kfd-staging branch, which has acquire_inline_ib()
+exclusively.
+
+Change-Id: I9515fdece70110067cda66e2d24d6768b4846c2f
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c       | 14 +++---
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 35 +++++++--------
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h | 44 ++++++-------------
+ .../gpu/drm/amd/amdkfd/kfd_packet_manager.c   | 34 +++++++-------
+ 4 files changed, 54 insertions(+), 73 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
+index 142ac7954032..3e5904f8876a 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
+@@ -74,11 +74,11 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev,
+ 	 * The receive packet buff will be sitting on the Indirect Buffer
+ 	 * and in the PQ we put the IB packet + sync packet(s).
+ 	 */
+-	status = kq->ops.acquire_packet_buffer(kq,
++	status = kq_acquire_packet_buffer(kq,
+ 				pq_packets_size_in_bytes / sizeof(uint32_t),
+ 				&ib_packet_buff);
+ 	if (status) {
+-		pr_err("acquire_packet_buffer failed\n");
++		pr_err("kq_acquire_packet_buffer failed\n");
+ 		return status;
+ 	}
+ 
+@@ -101,7 +101,7 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev,
+ 	ib_packet->bitfields5.pasid = pasid;
+ 
+ 	if (!sync) {
+-		kq->ops.submit_packet(kq);
++		kq_submit_packet(kq);
+ 		return status;
+ 	}
+ 
+@@ -122,7 +122,7 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev,
+ 
+ 	if (status) {
+ 		pr_err("Failed to allocate GART memory\n");
+-		kq->ops.rollback_packet(kq);
++		kq_rollback_packet(kq);
+ 		return status;
+ 	}
+ 
+@@ -158,7 +158,7 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev,
+ 
+ 	rm_packet->data_lo = QUEUESTATE__ACTIVE;
+ 
+-	kq->ops.submit_packet(kq);
++	kq_submit_packet(kq);
+ 
+ 	/* Wait till CP writes sync code: */
+ 	status = amdkfd_fence_wait_timeout(
+@@ -372,7 +372,7 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev,
+ 		return -EINVAL;
+ 	}
+ 
+-	status = dbgdev->kq->ops.acquire_inline_ib(dbgdev->kq,
++	status = kq_acquire_inline_ib(dbgdev->kq,
+ 			ib_size/sizeof(uint32_t),
+ 			&packet_buff_uint, &packet_buff_gpu_addr);
+ 	if (status) {
+@@ -652,7 +652,7 @@ static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev,
+ 
+ 	pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *");
+ 
+-	status = dbgdev->kq->ops.acquire_inline_ib(dbgdev->kq,
++	status = kq_acquire_inline_ib(dbgdev->kq,
+ 			ib_size / sizeof(uint32_t),
+ 			&packet_buff_uint, &packet_buff_gpu_addr);
+ 	if (status) {
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+index ca7e8d299c8b..236023ce1125 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+@@ -34,7 +34,10 @@
+ 
+ #define PM4_COUNT_ZERO (((1 << 15) - 1) << 16)
+ 
+-static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev,
++/* Initialize a kernel queue, including allocations of GART memory
++ * needed for the queue.
++ */
++static bool kq_initialize(struct kernel_queue *kq, struct kfd_dev *dev,
+ 		enum kfd_queue_type type, unsigned int queue_size)
+ {
+ 	struct queue_properties prop;
+@@ -88,7 +91,7 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev,
+ 	kq->pq_gpu_addr = kq->pq->gpu_addr;
+ 
+ 	/* For CIK family asics, kq->eop_mem is not needed */
+-	if (dev->device_info->asic_family > CHIP_HAWAII) {
++	if (dev->device_info->asic_family > CHIP_MULLINS) {
+ 		retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, &kq->eop_mem);
+ 		if (retval != 0)
+ 			goto err_eop_allocate_vidmem;
+@@ -192,7 +195,8 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev,
+ 
+ }
+ 
+-static void uninitialize(struct kernel_queue *kq)
++/* Uninitialize a kernel queue and free all its memory usages. */
++static void kq_uninitialize(struct kernel_queue *kq)
+ {
+ 	if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ)
+ 		kq->mqd_mgr->destroy_mqd(kq->mqd_mgr,
+@@ -221,7 +225,7 @@ static void uninitialize(struct kernel_queue *kq)
+ 	uninit_queue(kq->queue);
+ }
+ 
+-static int acquire_packet_buffer(struct kernel_queue *kq,
++int kq_acquire_packet_buffer(struct kernel_queue *kq,
+ 		size_t packet_size_in_dwords, unsigned int **buffer_ptr)
+ {
+ 	size_t available_size;
+@@ -282,7 +286,7 @@ static int acquire_packet_buffer(struct kernel_queue *kq,
+ 	return -ENOMEM;
+ }
+ 
+-static int acquire_inline_ib(struct kernel_queue *kq,
++int kq_acquire_inline_ib(struct kernel_queue *kq,
+ 			     size_t size_in_dwords,
+ 			     unsigned int **buffer_ptr,
+ 			     uint64_t *gpu_addr)
+@@ -297,7 +301,7 @@ static int acquire_inline_ib(struct kernel_queue *kq,
+ 	/* Allocate size_in_dwords on the ring, plus an extra dword
+ 	 * for a NOP packet header
+ 	 */
+-	ret = acquire_packet_buffer(kq, size_in_dwords + 1,  &buf);
++	ret = kq_acquire_packet_buffer(kq, size_in_dwords + 1,  &buf);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -315,7 +319,7 @@ static int acquire_inline_ib(struct kernel_queue *kq,
+ 	return 0;
+ }
+ 
+-static void submit_packet(struct kernel_queue *kq)
++void kq_submit_packet(struct kernel_queue *kq)
+ {
+ #ifdef DEBUG
+ 	int i;
+@@ -338,7 +342,7 @@ static void submit_packet(struct kernel_queue *kq)
+ 	}
+ }
+ 
+-static void rollback_packet(struct kernel_queue *kq)
++void kq_rollback_packet(struct kernel_queue *kq)
+ {
+ 	if (kq->dev->device_info->doorbell_size == 8) {
+ 		kq->pending_wptr64 = *kq->wptr64_kernel;
+@@ -358,14 +362,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
+ 	if (!kq)
+ 		return NULL;
+ 
+-	kq->ops.initialize = initialize;
+-	kq->ops.uninitialize = uninitialize;
+-	kq->ops.acquire_packet_buffer = acquire_packet_buffer;
+-	kq->ops.acquire_inline_ib = acquire_inline_ib;
+-	kq->ops.submit_packet = submit_packet;
+-	kq->ops.rollback_packet = rollback_packet;
+-
+-	if (kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE))
++	if (kq_initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE))
+ 		return kq;
+ 
+ 	pr_err("Failed to init kernel queue\n");
+@@ -376,7 +373,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev,
+ 
+ void kernel_queue_uninit(struct kernel_queue *kq)
+ {
+-	kq->ops.uninitialize(kq);
++	kq_uninitialize(kq);
+ 	kfree(kq);
+ }
+ 
+@@ -396,7 +393,7 @@ static __attribute__((unused)) void test_kq(struct kfd_dev *dev)
+ 		return;
+ 	}
+ 
+-	retval = kq->ops.acquire_packet_buffer(kq, 5, &buffer);
++	retval = kq_acquire_packet_buffer(kq, 5, &buffer);
+ 	if (unlikely(retval != 0)) {
+ 		pr_err("  Failed to acquire packet buffer\n");
+ 		pr_err("Kernel queue test failed\n");
+@@ -404,7 +401,7 @@ static __attribute__((unused)) void test_kq(struct kfd_dev *dev)
+ 	}
+ 	for (i = 0; i < 5; i++)
+ 		buffer[i] = kq->nop_packet;
+-	kq->ops.submit_packet(kq);
++	kq_submit_packet(kq);
+ 
+ 	pr_err("Ending kernel queue test\n");
+ }
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
+index 852de7466cc4..3e39dcb542df 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h
+@@ -29,54 +29,38 @@
+ #include "kfd_priv.h"
+ 
+ /**
+- * struct kernel_queue_ops
+- *
+- * @initialize: Initialize a kernel queue, including allocations of GART memory
+- * needed for the queue.
+- *
+- * @uninitialize: Uninitialize a kernel queue and free all its memory usages.
+- *
+- * @acquire_packet_buffer: Returns a pointer to the location in the kernel
++ * kq_acquire_packet_buffer: Returns a pointer to the location in the kernel
+  * queue ring buffer where the calling function can write its packet. It is
+  * Guaranteed that there is enough space for that packet. It also updates the
+  * pending write pointer to that location so subsequent calls to
+  * acquire_packet_buffer will get a correct write pointer
+  *
+- * @acquire_inline_ib: Returns a pointer to the location in the kernel
++ * kq_acquire_inline_ib: Returns a pointer to the location in the kernel
+  * queue ring buffer where the calling function can write an inline IB. It is
+  * Guaranteed that there is enough space for that IB. It also updates the
+  * pending write pointer to that location so subsequent calls to
+  * acquire_packet_buffer will get a correct write pointer
+  *
+- * @submit_packet: Update the write pointer and doorbell of a kernel queue.
+- *
+- * @sync_with_hw: Wait until the write pointer and the read pointer of a kernel
+- * queue are equal, which means the CP has read all the submitted packets.
++ * kq_submit_packet: Update the write pointer and doorbell of a kernel queue.
+  *
+- * @rollback_packet: This routine is called if we failed to build an acquired
++ * kq_rollback_packet: This routine is called if we failed to build an acquired
+  * packet for some reason. It just overwrites the pending wptr with the current
+  * one
+  *
+  */
+-struct kernel_queue_ops {
+-	bool	(*initialize)(struct kernel_queue *kq, struct kfd_dev *dev,
+-			enum kfd_queue_type type, unsigned int queue_size);
+-	void	(*uninitialize)(struct kernel_queue *kq);
+-	int	(*acquire_packet_buffer)(struct kernel_queue *kq,
+-					size_t packet_size_in_dwords,
+-					unsigned int **buffer_ptr);
+-	int	(*acquire_inline_ib)(struct kernel_queue *kq,
+-				     size_t packet_size_in_dwords,
+-				     unsigned int **buffer_ptr,
+-				     uint64_t *gpu_addr);
+ 
+-	void	(*submit_packet)(struct kernel_queue *kq);
+-	void	(*rollback_packet)(struct kernel_queue *kq);
+-};
++int kq_acquire_packet_buffer(struct kernel_queue *kq,
++				size_t packet_size_in_dwords,
++				unsigned int **buffer_ptr);
++int kq_acquire_inline_ib(struct kernel_queue *kq,
++			     size_t size_in_dwords,
++			     unsigned int **buffer_ptr,
++			     uint64_t *gpu_addr);
++void kq_submit_packet(struct kernel_queue *kq);
++void kq_rollback_packet(struct kernel_queue *kq);
+ 
+-struct kernel_queue {
+-	struct kernel_queue_ops ops;
+ 
++struct kernel_queue {
+ 	/* data */
+ 	struct kfd_dev		*dev;
+ 	struct mqd_manager	*mqd_mgr;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+index cbf83ed96dad..6ef4dc60852d 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+@@ -280,7 +280,7 @@ int pm_send_set_resources(struct packet_manager *pm,
+ 
+ 	size = pm->pmf->set_resources_size;
+ 	mutex_lock(&pm->lock);
+-	pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue,
++	kq_acquire_packet_buffer(pm->priv_queue,
+ 					size / sizeof(uint32_t),
+ 					(unsigned int **)&buffer);
+ 	if (!buffer) {
+@@ -291,9 +291,9 @@ int pm_send_set_resources(struct packet_manager *pm,
+ 
+ 	retval = pm->pmf->set_resources(pm, buffer, res);
+ 	if (!retval)
+-		pm->priv_queue->ops.submit_packet(pm->priv_queue);
++		kq_submit_packet(pm->priv_queue);
+ 	else
+-		pm->priv_queue->ops.rollback_packet(pm->priv_queue);
++		kq_rollback_packet(pm->priv_queue);
+ 
+ out:
+ 	mutex_unlock(&pm->lock);
+@@ -318,7 +318,7 @@ int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues)
+ 	packet_size_dwords = pm->pmf->runlist_size / sizeof(uint32_t);
+ 	mutex_lock(&pm->lock);
+ 
+-	retval = pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue,
++	retval = kq_acquire_packet_buffer(pm->priv_queue,
+ 					packet_size_dwords, &rl_buffer);
+ 	if (retval)
+ 		goto fail_acquire_packet_buffer;
+@@ -328,14 +328,14 @@ int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues)
+ 	if (retval)
+ 		goto fail_create_runlist;
+ 
+-	pm->priv_queue->ops.submit_packet(pm->priv_queue);
++	kq_submit_packet(pm->priv_queue);
+ 
+ 	mutex_unlock(&pm->lock);
+ 
+ 	return retval;
+ 
+ fail_create_runlist:
+-	pm->priv_queue->ops.rollback_packet(pm->priv_queue);
++	kq_rollback_packet(pm->priv_queue);
+ fail_acquire_packet_buffer:
+ 	mutex_unlock(&pm->lock);
+ fail_create_runlist_ib:
+@@ -354,7 +354,7 @@ int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address,
+ 
+ 	size = pm->pmf->query_status_size;
+ 	mutex_lock(&pm->lock);
+-	pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue,
++	kq_acquire_packet_buffer(pm->priv_queue,
+ 			size / sizeof(uint32_t), (unsigned int **)&buffer);
+ 	if (!buffer) {
+ 		pr_err("Failed to allocate buffer on kernel queue\n");
+@@ -364,9 +364,9 @@ int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address,
+ 
+ 	retval = pm->pmf->query_status(pm, buffer, fence_address, fence_value);
+ 	if (!retval)
+-		pm->priv_queue->ops.submit_packet(pm->priv_queue);
++		kq_submit_packet(pm->priv_queue);
+ 	else
+-		pm->priv_queue->ops.rollback_packet(pm->priv_queue);
++		kq_rollback_packet(pm->priv_queue);
+ 
+ out:
+ 	mutex_unlock(&pm->lock);
+@@ -383,7 +383,7 @@ int pm_update_grace_period(struct packet_manager *pm, uint32_t grace_period)
+ 	mutex_lock(&pm->lock);
+ 
+ 	if (size) {
+-		pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue,
++		kq_acquire_packet_buffer(pm->priv_queue,
+ 			size / sizeof(uint32_t),
+ 			(unsigned int **)&buffer);
+ 
+@@ -395,9 +395,9 @@ int pm_update_grace_period(struct packet_manager *pm, uint32_t grace_period)
+ 
+ 		retval = pm->pmf->set_grace_period(pm, buffer, grace_period);
+ 		if (!retval)
+-			pm->priv_queue->ops.submit_packet(pm->priv_queue);
++			kq_submit_packet(pm->priv_queue);
+ 		else
+-			pm->priv_queue->ops.rollback_packet(pm->priv_queue);
++			kq_rollback_packet(pm->priv_queue);
+ 	}
+ 
+ out:
+@@ -415,7 +415,7 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type,
+ 
+ 	size = pm->pmf->unmap_queues_size;
+ 	mutex_lock(&pm->lock);
+-	pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue,
++	kq_acquire_packet_buffer(pm->priv_queue,
+ 			size / sizeof(uint32_t), (unsigned int **)&buffer);
+ 	if (!buffer) {
+ 		pr_err("Failed to allocate buffer on kernel queue\n");
+@@ -426,9 +426,9 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type,
+ 	retval = pm->pmf->unmap_queues(pm, buffer, type, filter, filter_param,
+ 				       reset, sdma_engine);
+ 	if (!retval)
+-		pm->priv_queue->ops.submit_packet(pm->priv_queue);
++		kq_submit_packet(pm->priv_queue);
+ 	else
+-		pm->priv_queue->ops.rollback_packet(pm->priv_queue);
++		kq_rollback_packet(pm->priv_queue);
+ 
+ out:
+ 	mutex_unlock(&pm->lock);
+@@ -473,7 +473,7 @@ int pm_debugfs_hang_hws(struct packet_manager *pm)
+ 
+ 	size = pm->pmf->query_status_size;
+ 	mutex_lock(&pm->lock);
+-	pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue,
++	kq_acquire_packet_buffer(pm->priv_queue,
+ 			size / sizeof(uint32_t), (unsigned int **)&buffer);
+ 	if (!buffer) {
+ 		pr_err("Failed to allocate buffer on kernel queue\n");
+@@ -481,7 +481,7 @@ int pm_debugfs_hang_hws(struct packet_manager *pm)
+ 		goto out;
+ 	}
+ 	memset(buffer, 0x55, size);
+-	pm->priv_queue->ops.submit_packet(pm->priv_queue);
++	kq_submit_packet(pm->priv_queue);
+ 
+ 	pr_info("Submitting %x %x %x %x %x %x %x to HIQ to hang the HWS.",
+ 		buffer[0], buffer[1], buffer[2], buffer[3],
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4607-drm-amdgpu-gfx10-unlock-srbm_mutex-after-queue-progr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4607-drm-amdgpu-gfx10-unlock-srbm_mutex-after-queue-progr.patch
new file mode 100644
index 00000000..2c2b7f33
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4607-drm-amdgpu-gfx10-unlock-srbm_mutex-after-queue-progr.patch
@@ -0,0 +1,51 @@
+From 8ba808c2f1cf3757741eec7d2288d15ae6f2e431 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 6 Nov 2019 21:10:20 +0800
+Subject: [PATCH 4607/4736] drm/amdgpu/gfx10: unlock srbm_mutex after queue
+ programming finish
+
+srbm_mutex is to guarantee atomicity for r/w of gfx indexed registers
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index bfc2b8f8c1d4..96a9acb0dd6a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -2829,7 +2829,7 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
+ 	/* Init gfx ring 0 for pipe 0 */
+ 	mutex_lock(&adev->srbm_mutex);
+ 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
+-	mutex_unlock(&adev->srbm_mutex);
++
+ 	/* Set ring buffer size */
+ 	ring = &adev->gfx.gfx_ring[0];
+ 	rb_bufsz = order_base_2(ring->ring_size / 8);
+@@ -2867,11 +2867,11 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
+ 	WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
+ 
+ 	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
++	mutex_unlock(&adev->srbm_mutex);
+ 
+ 	/* Init gfx ring 1 for pipe 1 */
+ 	mutex_lock(&adev->srbm_mutex);
+ 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
+-	mutex_unlock(&adev->srbm_mutex);
+ 	ring = &adev->gfx.gfx_ring[1];
+ 	rb_bufsz = order_base_2(ring->ring_size / 8);
+ 	tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
+@@ -2901,6 +2901,7 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
+ 	WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
+ 
+ 	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
++	mutex_unlock(&adev->srbm_mutex);
+ 
+ 	/* Switch to pipe 0 */
+ 	mutex_lock(&adev->srbm_mutex);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4608-drm-amdgpu-gfx10-remove-outdated-comments.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4608-drm-amdgpu-gfx10-remove-outdated-comments.patch
new file mode 100644
index 00000000..b88a4a17
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4608-drm-amdgpu-gfx10-remove-outdated-comments.patch
@@ -0,0 +1,28 @@
+From 086b1d934b2a7b24b118bcfe63a2d35ae00daa04 Mon Sep 17 00:00:00 2001
+From: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Date: Wed, 6 Nov 2019 21:08:06 +0800
+Subject: [PATCH 4608/4736] drm/amdgpu/gfx10: remove outdated comments
+
+Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+Reviewed-by: Zhan Liu <zhan.liu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 96a9acb0dd6a..cd4982d70889 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -46,9 +46,6 @@
+  * Navi10 has two graphic rings to share each graphic pipe.
+  * 1. Primary ring
+  * 2. Async ring
+- *
+- * In bring-up phase, it just used primary ring so set gfx ring number as 1 at
+- * first.
+  */
+ #define GFX10_NUM_GFX_RINGS	2
+ #define GFX10_MEC_HPD_SIZE	2048
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4609-drm-amdgpu-gfx-Clear-more-EDC-cnt.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4609-drm-amdgpu-gfx-Clear-more-EDC-cnt.patch
new file mode 100644
index 00000000..d2b627bb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4609-drm-amdgpu-gfx-Clear-more-EDC-cnt.patch
@@ -0,0 +1,39 @@
+From 7662a48fa43894acc6dd80ede850985de652d213 Mon Sep 17 00:00:00 2001
+From: James Zhu <James.Zhu@amd.com>
+Date: Tue, 26 Nov 2019 14:23:10 -0500
+Subject: [PATCH 4609/4736] drm/amdgpu/gfx: Clear more EDC cnt
+
+Clear SDMA and HDP EDC counter in GPR workarounds.
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 1aff77c89e7a..d008105a5757 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -44,6 +44,8 @@
+ 
+ #include "amdgpu_ras.h"
+ 
++#include "sdma0/sdma0_4_0_offset.h"
++#include "sdma1/sdma1_4_0_offset.h"
+ #define GFX9_NUM_GFX_RINGS     1
+ #define GFX9_MEC_HPD_SIZE 4096
+ #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
+@@ -4032,6 +4034,9 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
+    { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16},
+    { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2},
+    { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
++   { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 0, 1, 1},
++   { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_EDC_COUNTER), 0, 1, 1},
++   { SOC15_REG_ENTRY(HDP, 0, mmHDP_EDC_CNT), 0, 1, 1},
+ };
+ 
+ static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4610-drm-amdgpu-gfx-Increase-dispatch-packet-number.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4610-drm-amdgpu-gfx-Increase-dispatch-packet-number.patch
new file mode 100644
index 00000000..66b1f54b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4610-drm-amdgpu-gfx-Increase-dispatch-packet-number.patch
@@ -0,0 +1,38 @@
+From be1ff76f766e0a5362640cd62e5012def7a8d031 Mon Sep 17 00:00:00 2001
+From: James Zhu <James.Zhu@amd.com>
+Date: Tue, 26 Nov 2019 14:27:46 -0500
+Subject: [PATCH 4610/4736] drm/amdgpu/gfx: Increase dispatch packet number
+
+For Arcturus, increase dispatch packet number to stress scheduler.
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index d008105a5757..8f9861361a9d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -4149,7 +4149,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
+ 
+ 	/* write dispatch packet */
+ 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
+-	ib.ptr[ib.length_dw++] = 128; /* x */
++	ib.ptr[ib.length_dw++] = 256; /* x */
+ 	ib.ptr[ib.length_dw++] = 1; /* y */
+ 	ib.ptr[ib.length_dw++] = 1; /* z */
+ 	ib.ptr[ib.length_dw++] =
+@@ -4177,7 +4177,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
+ 
+ 	/* write dispatch packet */
+ 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
+-	ib.ptr[ib.length_dw++] = 128; /* x */
++	ib.ptr[ib.length_dw++] = 256; /* x */
+ 	ib.ptr[ib.length_dw++] = 1; /* y */
+ 	ib.ptr[ib.length_dw++] = 1; /* z */
+ 	ib.ptr[ib.length_dw++] =
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4611-drm-amd-display-Include-num_vmid-and-num_dsc-within-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4611-drm-amd-display-Include-num_vmid-and-num_dsc-within-.patch
new file mode 100644
index 00000000..5cceb87b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4611-drm-amd-display-Include-num_vmid-and-num_dsc-within-.patch
@@ -0,0 +1,36 @@
+From fdf561f7ee9326da840da019007eec6f281b280a Mon Sep 17 00:00:00 2001
+From: Zhan Liu <zhan.liu@amd.com>
+Date: Thu, 28 Nov 2019 14:12:11 -0500
+Subject: [PATCH 4611/4736] drm/amd/display: Include num_vmid and num_dsc
+ within NV14's resource caps
+
+[Why]
+"num_vmid" and "num_dsc" are missing within NV14's resource caps structure.
+
+[How]
+Add the missing parts.
+
+Signed-off-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 9f721d5bea3b..f30e9aef53ba 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -816,6 +816,10 @@ static const struct resource_caps res_cap_nv14 = {
+ 		.num_pll = 5,
+ 		.num_dwb = 1,
+ 		.num_ddc = 5,
++		.num_vmid = 16,
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++		.num_dsc = 5,
++#endif
+ };
+ 
+ static const struct dc_debug_options debug_defaults_drv = {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4612-drm-amd-display-Drop-AMD_EDID_UTILITY-defines.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4612-drm-amd-display-Drop-AMD_EDID_UTILITY-defines.patch
new file mode 100644
index 00000000..fb4dfd71
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4612-drm-amd-display-Drop-AMD_EDID_UTILITY-defines.patch
@@ -0,0 +1,96 @@
+From 12d45f8bdc7c9d1d078f104da0a20788a8e3bdfc Mon Sep 17 00:00:00 2001
+From: Harry Wentland <harry.wentland@amd.com>
+Date: Thu, 28 Nov 2019 11:30:10 -0500
+Subject: [PATCH 4612/4736] drm/amd/display: Drop AMD_EDID_UTILITY defines
+
+We don't use this upstream in the Linux kernel.
+
+Change-Id: I3dd29b4bd46b3493e6a0c218df048712ea665c9a
+Signed-off-by: Harry Wentland <harry.wentland@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc_dsc.h      | 2 --
+ drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 8 --------
+ drivers/gpu/drm/amd/display/dc/dc_types.h    | 4 ----
+ 3 files changed, 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+index a782ae18a1c5..cc9915e545cd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+@@ -41,10 +41,8 @@ struct dc_dsc_bw_range {
+ 
+ struct display_stream_compressor {
+ 	const struct dsc_funcs *funcs;
+-#ifndef AMD_EDID_UTILITY
+ 	struct dc_context *ctx;
+ 	int inst;
+-#endif
+ };
+ 
+ bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_basic_data,
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+index 86043d431d40..25c50bcab9e9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+@@ -26,8 +26,6 @@
+ #ifndef DC_HW_TYPES_H
+ #define DC_HW_TYPES_H
+ 
+-#ifndef AMD_EDID_UTILITY
+-
+ #include "os_types.h"
+ #include "fixed31_32.h"
+ #include "signal_types.h"
+@@ -584,8 +582,6 @@ struct scaling_taps {
+ 	bool integer_scaling;
+ };
+ 
+-#endif /* AMD_EDID_UTILITY */
+-
+ enum dc_timing_standard {
+ 	DC_TIMING_STANDARD_UNDEFINED,
+ 	DC_TIMING_STANDARD_DMT,
+@@ -742,8 +738,6 @@ struct dc_crtc_timing {
+ 	struct dc_dsc_config dsc_cfg;
+ };
+ 
+-#ifndef AMD_EDID_UTILITY
+-
+ enum trigger_delay {
+ 	TRIGGER_DELAY_NEXT_PIXEL = 0,
+ 	TRIGGER_DELAY_NEXT_LINE,
+@@ -837,7 +831,5 @@ struct tg_color {
+ 	uint16_t color_b_cb;
+ };
+ 
+-#endif /* AMD_EDID_UTILITY */
+-
+ #endif /* DC_HW_TYPES_H */
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
+index 1363e8907fbf..2b92bfa28bde 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
+@@ -25,7 +25,6 @@
+ #ifndef DC_TYPES_H_
+ #define DC_TYPES_H_
+ 
+-#ifndef AMD_EDID_UTILITY
+ /* AND EdidUtility only needs a portion
+  * of this file, including the rest only
+  * causes additional issues.
+@@ -781,9 +780,6 @@ struct dc_clock_config {
+ 	uint32_t current_clock_khz;/*current clock in use*/
+ };
+ 
+-#endif /*AMD_EDID_UTILITY*/
+-//AMD EDID UTILITY does not need any of the above structures
+-
+ /* DSC DPCD capabilities */
+ union dsc_slice_caps1 {
+ 	struct {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4613-drm-amdgpu-fix-calltrace-during-kmd-unload-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4613-drm-amdgpu-fix-calltrace-during-kmd-unload-v3.patch
new file mode 100644
index 00000000..b47602b8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4613-drm-amdgpu-fix-calltrace-during-kmd-unload-v3.patch
@@ -0,0 +1,324 @@
+From 52f19708950e75cdb45af6c578c2b811eeb4084b Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Tue, 26 Nov 2019 19:42:25 +0800
+Subject: [PATCH 4613/4736] drm/amdgpu: fix calltrace during kmd unload(v3)
+
+issue:
+kernel would report a warning from a double unpin
+during the driver unloading on the CSB bo
+
+why:
+we unpin it during hw_fini, and there will be another
+unpin in sw_fini on CSB bo.
+
+fix:
+actually we don't need to pin/unpin it during
+hw_init/fini since it is created with kernel pinned,
+we only need to fullfill the CSB again during hw_init
+to prevent CSB/VRAM lost after S3
+
+v2:
+get_csb in init_rlc so hw_init() will make CSIB content
+back even after reset or s3
+
+v3:
+use bo_create_kernel instead of bo_create_reserved for CSB
+otherwise the bo_free_kernel() on CSB is not aligned and
+would lead to its internal reserve pending there forever
+
+take care of gfx7/8 as well
+
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c | 10 +----
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 58 +------------------------
+ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c   |  2 +
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   | 40 +----------------
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 40 +----------------
+ 5 files changed, 6 insertions(+), 144 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
+index c8793e6cc3c5..6373bfb47d55 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
+@@ -124,13 +124,12 @@ int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws)
+  */
+ int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev)
+ {
+-	volatile u32 *dst_ptr;
+ 	u32 dws;
+ 	int r;
+ 
+ 	/* allocate clear state block */
+ 	adev->gfx.rlc.clear_state_size = dws = adev->gfx.rlc.funcs->get_csb_size(adev);
+-	r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
++	r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE,
+ 				      AMDGPU_GEM_DOMAIN_VRAM,
+ 				      &adev->gfx.rlc.clear_state_obj,
+ 				      &adev->gfx.rlc.clear_state_gpu_addr,
+@@ -141,13 +140,6 @@ int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev)
+ 		return r;
+ 	}
+ 
+-	/* set up the cs buffer */
+-	dst_ptr = adev->gfx.rlc.cs_ptr;
+-	adev->gfx.rlc.funcs->get_csb_buffer(adev, dst_ptr);
+-	amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
+-	amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
+-	amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+-
+ 	return 0;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index cd4982d70889..914d4b2f8401 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -987,39 +987,6 @@ static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
+-static int gfx_v10_0_csb_vram_pin(struct amdgpu_device *adev)
+-{
+-	int r;
+-
+-	r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
+-	if (unlikely(r != 0))
+-		return r;
+-
+-	r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
+-			AMDGPU_GEM_DOMAIN_VRAM);
+-	if (!r)
+-		adev->gfx.rlc.clear_state_gpu_addr =
+-			amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
+-
+-	amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+-
+-	return r;
+-}
+-
+-static void gfx_v10_0_csb_vram_unpin(struct amdgpu_device *adev)
+-{
+-	int r;
+-
+-	if (!adev->gfx.rlc.clear_state_obj)
+-		return;
+-
+-	r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
+-	if (likely(r == 0)) {
+-		amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
+-		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+-	}
+-}
+-
+ static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
+ {
+ 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
+@@ -1788,25 +1755,7 @@ static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
+ 
+ static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
+ {
+-	int r;
+-
+-	if (adev->in_gpu_reset) {
+-		r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
+-		if (r)
+-			return r;
+-
+-		r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj,
+-				   (void **)&adev->gfx.rlc.cs_ptr);
+-		if (!r) {
+-			adev->gfx.rlc.funcs->get_csb_buffer(adev,
+-					adev->gfx.rlc.cs_ptr);
+-			amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
+-		}
+-
+-		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+-		if (r)
+-			return r;
+-	}
++	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
+ 
+ 	/* csib */
+ 	WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
+@@ -3777,10 +3726,6 @@ static int gfx_v10_0_hw_init(void *handle)
+ 	int r;
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 
+-	r = gfx_v10_0_csb_vram_pin(adev);
+-	if (r)
+-		return r;
+-
+ 	if (!amdgpu_emu_mode)
+ 		gfx_v10_0_init_golden_registers(adev);
+ 
+@@ -3868,7 +3813,6 @@ static int gfx_v10_0_hw_fini(void *handle)
+ 	}
+ 	gfx_v10_0_cp_enable(adev, false);
+ 	gfx_v10_0_enable_gui_idle_interrupt(adev, false);
+-	gfx_v10_0_csb_vram_unpin(adev);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+index b8c2e9d9c711..0dabd0d0889c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+@@ -4543,6 +4543,8 @@ static int gfx_v7_0_hw_init(void *handle)
+ 
+ 	gfx_v7_0_constants_init(adev);
+ 
++	/* init CSB */
++	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
+ 	/* init rlc */
+ 	r = adev->gfx.rlc.funcs->resume(adev);
+ 	if (r)
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index 1f4f7c05e269..387e95319594 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -1317,39 +1317,6 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
+-static int gfx_v8_0_csb_vram_pin(struct amdgpu_device *adev)
+-{
+-	int r;
+-
+-	r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
+-	if (unlikely(r != 0))
+-		return r;
+-
+-	r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
+-			AMDGPU_GEM_DOMAIN_VRAM);
+-	if (!r)
+-		adev->gfx.rlc.clear_state_gpu_addr =
+-			amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
+-
+-	amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+-
+-	return r;
+-}
+-
+-static void gfx_v8_0_csb_vram_unpin(struct amdgpu_device *adev)
+-{
+-	int r;
+-
+-	if (!adev->gfx.rlc.clear_state_obj)
+-		return;
+-
+-	r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
+-	if (likely(r == 0)) {
+-		amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
+-		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+-	}
+-}
+-
+ static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
+ {
+ 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
+@@ -3903,6 +3870,7 @@ static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
+ 
+ static void gfx_v8_0_init_csb(struct amdgpu_device *adev)
+ {
++	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
+ 	/* csib */
+ 	WREG32(mmRLC_CSIB_ADDR_HI,
+ 			adev->gfx.rlc.clear_state_gpu_addr >> 32);
+@@ -4822,10 +4790,6 @@ static int gfx_v8_0_hw_init(void *handle)
+ 	gfx_v8_0_init_golden_registers(adev);
+ 	gfx_v8_0_constants_init(adev);
+ 
+-	r = gfx_v8_0_csb_vram_pin(adev);
+-	if (r)
+-		return r;
+-
+ 	r = adev->gfx.rlc.funcs->resume(adev);
+ 	if (r)
+ 		return r;
+@@ -4943,8 +4907,6 @@ static int gfx_v8_0_hw_fini(void *handle)
+ 		pr_err("rlc is busy, skip halt rlc\n");
+ 	amdgpu_gfx_rlc_exit_safe_mode(adev);
+ 
+-	gfx_v8_0_csb_vram_unpin(adev);
+-
+ 	return 0;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 8f9861361a9d..e644d5ea56b9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -1681,39 +1681,6 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
+-static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev)
+-{
+-	int r;
+-
+-	r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
+-	if (unlikely(r != 0))
+-		return r;
+-
+-	r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
+-			AMDGPU_GEM_DOMAIN_VRAM);
+-	if (!r)
+-		adev->gfx.rlc.clear_state_gpu_addr =
+-			amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
+-
+-	amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+-
+-	return r;
+-}
+-
+-static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev)
+-{
+-	int r;
+-
+-	if (!adev->gfx.rlc.clear_state_obj)
+-		return;
+-
+-	r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
+-	if (likely(r == 0)) {
+-		amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
+-		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+-	}
+-}
+-
+ static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
+ {
+ 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
+@@ -2408,6 +2375,7 @@ static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
+ 
+ static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
+ {
++	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
+ 	/* csib */
+ 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
+ 			adev->gfx.rlc.clear_state_gpu_addr >> 32);
+@@ -3699,10 +3667,6 @@ static int gfx_v9_0_hw_init(void *handle)
+ 
+ 	gfx_v9_0_constants_init(adev);
+ 
+-	r = gfx_v9_0_csb_vram_pin(adev);
+-	if (r)
+-		return r;
+-
+ 	r = adev->gfx.rlc.funcs->resume(adev);
+ 	if (r)
+ 		return r;
+@@ -3784,8 +3748,6 @@ static int gfx_v9_0_hw_fini(void *handle)
+ 	gfx_v9_0_cp_enable(adev, false);
+ 	adev->gfx.rlc.funcs->stop(adev);
+ 
+-	gfx_v9_0_csb_vram_unpin(adev);
+-
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4614-drm-amdgpu-skip-rlc-ucode-loading-for-SRIOV-gfx10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4614-drm-amdgpu-skip-rlc-ucode-loading-for-SRIOV-gfx10.patch
new file mode 100644
index 00000000..10a5a6dc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4614-drm-amdgpu-skip-rlc-ucode-loading-for-SRIOV-gfx10.patch
@@ -0,0 +1,119 @@
+From bc96184e89b8dc328d8c0e1c533d2315f6bb48bc Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Tue, 26 Nov 2019 19:36:29 +0800
+Subject: [PATCH 4614/4736] drm/amdgpu: skip rlc ucode loading for SRIOV gfx10
+
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 80 +++++++++++++-------------
+ 1 file changed, 41 insertions(+), 39 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 914d4b2f8401..5bd31e49601c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -684,59 +684,61 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
+ 	adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+ 	adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
+ 
+-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
+-	err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
+-	if (err)
+-		goto out;
+-	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
+-	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
+-	version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
+-	version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
+-	if (version_major == 2 && version_minor == 1)
+-		adev->gfx.rlc.is_rlc_v2_1 = true;
+-
+-	adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
+-	adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
+-	adev->gfx.rlc.save_and_restore_offset =
++	if (!amdgpu_sriov_vf(adev)) {
++		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
++		err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
++		if (err)
++			goto out;
++		err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
++		rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
++		version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
++		version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
++		if (version_major == 2 && version_minor == 1)
++			adev->gfx.rlc.is_rlc_v2_1 = true;
++
++		adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
++		adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
++		adev->gfx.rlc.save_and_restore_offset =
+ 			le32_to_cpu(rlc_hdr->save_and_restore_offset);
+-	adev->gfx.rlc.clear_state_descriptor_offset =
++		adev->gfx.rlc.clear_state_descriptor_offset =
+ 			le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
+-	adev->gfx.rlc.avail_scratch_ram_locations =
++		adev->gfx.rlc.avail_scratch_ram_locations =
+ 			le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
+-	adev->gfx.rlc.reg_restore_list_size =
++		adev->gfx.rlc.reg_restore_list_size =
+ 			le32_to_cpu(rlc_hdr->reg_restore_list_size);
+-	adev->gfx.rlc.reg_list_format_start =
++		adev->gfx.rlc.reg_list_format_start =
+ 			le32_to_cpu(rlc_hdr->reg_list_format_start);
+-	adev->gfx.rlc.reg_list_format_separate_start =
++		adev->gfx.rlc.reg_list_format_separate_start =
+ 			le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
+-	adev->gfx.rlc.starting_offsets_start =
++		adev->gfx.rlc.starting_offsets_start =
+ 			le32_to_cpu(rlc_hdr->starting_offsets_start);
+-	adev->gfx.rlc.reg_list_format_size_bytes =
++		adev->gfx.rlc.reg_list_format_size_bytes =
+ 			le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
+-	adev->gfx.rlc.reg_list_size_bytes =
++		adev->gfx.rlc.reg_list_size_bytes =
+ 			le32_to_cpu(rlc_hdr->reg_list_size_bytes);
+-	adev->gfx.rlc.register_list_format =
++		adev->gfx.rlc.register_list_format =
+ 			kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
+-				adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
+-	if (!adev->gfx.rlc.register_list_format) {
+-		err = -ENOMEM;
+-		goto out;
+-	}
++					adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
++		if (!adev->gfx.rlc.register_list_format) {
++			err = -ENOMEM;
++			goto out;
++		}
+ 
+-	tmp = (unsigned int *)((uintptr_t)rlc_hdr +
+-			le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
+-	for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
+-		adev->gfx.rlc.register_list_format[i] =	le32_to_cpu(tmp[i]);
++		tmp = (unsigned int *)((uintptr_t)rlc_hdr +
++							   le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
++		for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
++			adev->gfx.rlc.register_list_format[i] =	le32_to_cpu(tmp[i]);
+ 
+-	adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
++		adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
+ 
+-	tmp = (unsigned int *)((uintptr_t)rlc_hdr +
+-			le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
+-	for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
+-		adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
++		tmp = (unsigned int *)((uintptr_t)rlc_hdr +
++							   le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
++		for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
++			adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
+ 
+-	if (adev->gfx.rlc.is_rlc_v2_1)
+-		gfx_v10_0_init_rlc_ext_microcode(adev);
++		if (adev->gfx.rlc.is_rlc_v2_1)
++			gfx_v10_0_init_rlc_ext_microcode(adev);
++	}
+ 
+ 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
+ 	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4615-drm-amdgpu-do-autoload-right-after-MEC-loaded-for-SR.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4615-drm-amdgpu-do-autoload-right-after-MEC-loaded-for-SR.patch
new file mode 100644
index 00000000..eb2e31a3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4615-drm-amdgpu-do-autoload-right-after-MEC-loaded-for-SR.patch
@@ -0,0 +1,32 @@
+From b9099db37615143bba76082cb00bf2d3c43d80a7 Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Tue, 26 Nov 2019 19:38:22 +0800
+Subject: [PATCH 4615/4736] drm/amdgpu: do autoload right after MEC loaded for
+ SRIOV VF
+
+since we don't have RLCG ucode loading and no SRlist as well
+
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index c74c5f183a10..f219e2f77b4c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1492,8 +1492,8 @@ static int psp_np_fw_load(struct psp_context *psp)
+ 			return ret;
+ 
+ 		/* Start rlc autoload after psp recieved all the gfx firmware */
+-		if (psp->autoload_supported && ucode->ucode_id ==
+-			AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
++		if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
++		    AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) {
+ 			ret = psp_rlc_autoload(psp);
+ 			if (ret) {
+ 				DRM_ERROR("Failed to start rlc autoload\n");
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4616-drm-amdgpu-should-stop-GFX-ring-in-hw_fini.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4616-drm-amdgpu-should-stop-GFX-ring-in-hw_fini.patch
new file mode 100644
index 00000000..eb7ba795
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4616-drm-amdgpu-should-stop-GFX-ring-in-hw_fini.patch
@@ -0,0 +1,33 @@
+From cf9b2a4cf8e35ce24f5d1d6f7e98579cda2ec175 Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Fri, 29 Nov 2019 16:20:51 +0800
+Subject: [PATCH 4616/4736] drm/amdgpu: should stop GFX ring in hw_fini
+
+To align with the scheme from gfx9
+
+disabling GFX ring after VM shutdown could avoid
+garbage data be fetched to GFX RB which may lead
+to unnecessary screw up on GFX
+
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 5bd31e49601c..fd7ae21eb540 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -3810,7 +3810,7 @@ static int gfx_v10_0_hw_fini(void *handle)
+ 	if (amdgpu_gfx_disable_kcq(adev))
+ 		DRM_ERROR("KCQ disable failed\n");
+ 	if (amdgpu_sriov_vf(adev)) {
+-		pr_debug("For SRIOV client, shouldn't do anything.\n");
++		gfx_v10_0_cp_gfx_enable(adev, false);
+ 		return 0;
+ 	}
+ 	gfx_v10_0_cp_enable(adev, false);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4617-drm-amdgpu-fix-GFX10-missing-CSIB-set-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4617-drm-amdgpu-fix-GFX10-missing-CSIB-set-v3.patch
new file mode 100644
index 00000000..785a0841
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4617-drm-amdgpu-fix-GFX10-missing-CSIB-set-v3.patch
@@ -0,0 +1,89 @@
+From 34d7f239a288a1195c3b802a5851f493c6dce4e4 Mon Sep 17 00:00:00 2001
+From: Monk Liu <Monk.Liu@amd.com>
+Date: Tue, 26 Nov 2019 19:33:38 +0800
+Subject: [PATCH 4617/4736] drm/amdgpu: fix GFX10 missing CSIB set(v3)
+
+still need to init csb even for SRIOV
+
+v2:
+drop init_pg() for gfx10 at all since
+PG and GFX off feature will be fully controled
+by RLC and SMU fw for gfx10
+
+v3:
+drop the flush_gpu_tlb lines since we consider
+it is only usefull in emulation
+
+Signed-off-by: Monk Liu <Monk.Liu@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 33 ++++----------------------
+ 1 file changed, 5 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index fd7ae21eb540..ed630d37c32c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -1769,22 +1769,6 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
+ 	return 0;
+ }
+ 
+-static int gfx_v10_0_init_pg(struct amdgpu_device *adev)
+-{
+-	int i;
+-	int r;
+-
+-	r = gfx_v10_0_init_csb(adev);
+-	if (r)
+-		return r;
+-
+-	for (i = 0; i < adev->num_vmhubs; i++)
+-		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
+-
+-	/* TODO: init power gating */
+-	return 0;
+-}
+-
+ void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
+ {
+ 	u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
+@@ -1877,21 +1861,16 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
+ {
+ 	int r;
+ 
+-	if (amdgpu_sriov_vf(adev))
+-		return 0;
+-
+ 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+-		r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
+-		if (r)
+-			return r;
+ 
+-		r = gfx_v10_0_init_pg(adev);
++		r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
+ 		if (r)
+ 			return r;
+ 
+-		/* enable RLC SRM */
+-		gfx_v10_0_rlc_enable_srm(adev);
++		gfx_v10_0_init_csb(adev);
+ 
++		if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
++			gfx_v10_0_rlc_enable_srm(adev);
+ 	} else {
+ 		adev->gfx.rlc.funcs->stop(adev);
+ 
+@@ -1913,9 +1892,7 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
+ 				return r;
+ 		}
+ 
+-		r = gfx_v10_0_init_pg(adev);
+-		if (r)
+-			return r;
++		gfx_v10_0_init_csb(adev);
+ 
+ 		adev->gfx.rlc.funcs->start(adev);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4618-drm-amdgpu-not-remove-sysfs-if-not-create-sysfs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4618-drm-amdgpu-not-remove-sysfs-if-not-create-sysfs.patch
new file mode 100644
index 00000000..a08e6164
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4618-drm-amdgpu-not-remove-sysfs-if-not-create-sysfs.patch
@@ -0,0 +1,126 @@
+From e619c353cc3f794e94a75070c06586c6b80d19d6 Mon Sep 17 00:00:00 2001
+From: Yintian Tao <yttao@amd.com>
+Date: Fri, 29 Nov 2019 16:05:55 +0800
+Subject: [PATCH 4618/4736] drm/amdgpu: not remove sysfs if not create sysfs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+When load amdgpu failed before create pm_sysfs and ucode_sysfs,
+the pm_sysfs and ucode_sysfs should not be removed.
+Otherwise, there will be warning call trace just like below.
+[   24.836386] [drm] VCE initialized successfully.
+[   24.841352] amdgpu 0000:00:07.0: amdgpu_device_ip_init failed
+[   25.370383] amdgpu 0000:00:07.0: Fatal error during GPU init
+[   25.889575] [drm] amdgpu: finishing device.
+[   26.069128] amdgpu 0000:00:07.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring kiq_2.1.0 test failed (-110)
+[   26.070110] [drm:gfx_v9_0_hw_fini [amdgpu]] *ERROR* KCQ disable failed
+[   26.200309] [TTM] Finalizing pool allocator
+[   26.200314] [TTM] Finalizing DMA pool allocator
+[   26.200349] [TTM] Zone  kernel: Used memory at exit: 0 KiB
+[   26.200351] [TTM] Zone   dma32: Used memory at exit: 0 KiB
+[   26.200353] [drm] amdgpu: ttm finalized
+[   26.205329] ------------[ cut here ]------------
+[   26.205330] sysfs group 'fw_version' not found for kobject '0000:00:07.0'
+[   26.205347] WARNING: CPU: 0 PID: 1228 at fs/sysfs/group.c:256 sysfs_remove_group+0x80/0x90
+[   26.205348] Modules linked in: amdgpu(OE+) gpu_sched(OE) ttm(OE) drm_kms_helper(OE) drm(OE) i2c_algo_bit fb_sys_fops syscopyarea sysfillrect sysimgblt rpcsec_gss_krb5 auth_rpcgss nfsv4 nfs lockd grace fscache binfmt_misc snd_hda_codec_generic ledtrig_audio crct10dif_pclmul snd_hda_intel crc32_pclmul snd_hda_codec ghash_clmulni_intel snd_hda_core snd_hwdep snd_pcm snd_timer input_leds snd joydev soundcore serio_raw pcspkr evbug aesni_intel aes_x86_64 crypto_simd cryptd mac_hid glue_helper sunrpc ip_tables x_tables autofs4 8139too psmouse 8139cp mii i2c_piix4 pata_acpi floppy
+[   26.205369] CPU: 0 PID: 1228 Comm: modprobe Tainted: G           OE     5.2.0-rc1 #1
+[   26.205370] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014
+[   26.205372] RIP: 0010:sysfs_remove_group+0x80/0x90
+[   26.205374] Code: e8 35 b9 ff ff 5b 41 5c 41 5d 5d c3 48 89 df e8 f6 b5 ff ff eb c6 49 8b 55 00 49 8b 34 24 48 c7 c7 48 7a 70 98 e8 60 63 d3 ff <0f> 0b eb d7 66 90 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 55
+[   26.205375] RSP: 0018:ffffbee242b0b908 EFLAGS: 00010282
+[   26.205376] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000006
+[   26.205377] RDX: 0000000000000007 RSI: 0000000000000092 RDI: ffff97ad6f817380
+[   26.205377] RBP: ffffbee242b0b920 R08: ffffffff98f520c4 R09: 00000000000002b3
+[   26.205378] R10: ffffbee242b0b8f8 R11: 00000000000002b3 R12: ffffffffc0e58240
+[   26.205379] R13: ffff97ad6d1fe0b0 R14: ffff97ad4db954c8 R15: ffff97ad4db7fff0
+[   26.205380] FS:  00007ff3d8a1c4c0(0000) GS:ffff97ad6f800000(0000) knlGS:0000000000000000
+[   26.205381] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
+[   26.205381] CR2: 00007f9b2ef1df04 CR3: 000000042aab8001 CR4: 00000000003606f0
+[   26.205384] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
+[   26.205385] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
+[   26.205385] Call Trace:
+[   26.205461]  amdgpu_ucode_sysfs_fini+0x18/0x20 [amdgpu]
+[   26.205518]  amdgpu_device_fini+0x3b4/0x560 [amdgpu]
+[   26.205573]  amdgpu_driver_unload_kms+0x4f/0xa0 [amdgpu]
+[   26.205623]  amdgpu_driver_load_kms+0xcd/0x250 [amdgpu]
+[   26.205637]  drm_dev_register+0x12b/0x1c0 [drm]
+[   26.205695]  amdgpu_pci_probe+0x12a/0x1e0 [amdgpu]
+[   26.205699]  local_pci_probe+0x47/0xa0
+[   26.205701]  pci_device_probe+0x106/0x1b0
+[   26.205704]  really_probe+0x21a/0x3f0
+[   26.205706]  driver_probe_device+0x11c/0x140
+[   26.205707]  device_driver_attach+0x58/0x60
+[   26.205709]  __driver_attach+0xc3/0x140
+
+Signed-off-by: Yintian Tao <yttao@amd.com>
+Acked-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Nirmoy Das <nirmoy.das@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  3 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 ++++++++++++----
+ 2 files changed, 15 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 553d93a45e64..4eddee90553b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1037,6 +1037,9 @@ struct amdgpu_device {
+ 	int				pstate;
+ 	/* enable runtime pm on the device */
+ 	bool                            runpm;
++
++	bool                            pm_sysfs_en;
++	bool                            ucode_sysfs_en;
+ };
+ 
+ static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index bb04f9bb038c..0cef0443340d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3049,12 +3049,18 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ 		amdgpu_pm_virt_sysfs_init(adev);
+ 
+ 	r = amdgpu_pm_sysfs_init(adev);
+-	if (r)
++	if (r) {
++		adev->pm_sysfs_en = false;
+ 		DRM_ERROR("registering pm debugfs failed (%d).\n", r);
++	} else
++		adev->pm_sysfs_en = true;
+ 
+ 	r = amdgpu_ucode_sysfs_init(adev);
+-	if (r)
++	if (r) {
++		adev->ucode_sysfs_en = false;
+ 		DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
++	} else
++		adev->ucode_sysfs_en = true;
+ 
+ 	r = amdgpu_debugfs_gem_init(adev);
+ 	if (r)
+@@ -3155,7 +3161,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
+ 	}
+ 	amdgpu_ib_pool_fini(adev);
+ 	amdgpu_fence_driver_fini(adev);
+-	amdgpu_pm_sysfs_fini(adev);
++	if (adev->pm_sysfs_en)
++		amdgpu_pm_sysfs_fini(adev);
+ 	amdgpu_fbdev_fini(adev);
+ 	r = amdgpu_device_ip_fini(adev);
+ 	if (adev->firmware.gpu_info_fw) {
+@@ -3190,7 +3197,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
+ 
+ 	amdgpu_debugfs_regs_cleanup(adev);
+ 	device_remove_file(adev->dev, &dev_attr_pcie_replay_count);
+-	amdgpu_ucode_sysfs_fini(adev);
++	if (adev->ucode_sysfs_en)
++		amdgpu_ucode_sysfs_fini(adev);
+ 	if (IS_ENABLED(CONFIG_PERF_EVENTS))
+ 		amdgpu_pmu_fini(adev);
+ 	amdgpu_debugfs_preempt_cleanup(adev);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4619-drm-amd-display-Load-TA-firmware-for-navi10-12-14.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4619-drm-amd-display-Load-TA-firmware-for-navi10-12-14.patch
new file mode 100644
index 00000000..8be98eca
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4619-drm-amd-display-Load-TA-firmware-for-navi10-12-14.patch
@@ -0,0 +1,55 @@
+From dc314ed13f38600a0dc22f8163aef634ffea8b80 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Fri, 8 Nov 2019 16:57:21 -0500
+Subject: [PATCH 4619/4736] drm/amd/display: Load TA firmware for navi10/12/14
+
+load the ta firmware for navi10/12/14.
+This is already being done for raven/picasso and
+is needed for supporting hdcp on navi
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 25 +++++++++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+index a12804d6bdce..2e936fc8b1dc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+@@ -194,6 +194,31 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
+ 	case CHIP_NAVI10:
+ 	case CHIP_NAVI14:
+ 	case CHIP_NAVI12:
++		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
++		err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
++		if (err) {
++			release_firmware(adev->psp.ta_fw);
++			adev->psp.ta_fw = NULL;
++			dev_info(adev->dev,
++				 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
++		} else {
++			err = amdgpu_ucode_validate(adev->psp.ta_fw);
++			if (err)
++				goto out2;
++
++			ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
++			adev->psp.ta_hdcp_ucode_version = le32_to_cpu(ta_hdr->ta_hdcp_ucode_version);
++			adev->psp.ta_hdcp_ucode_size = le32_to_cpu(ta_hdr->ta_hdcp_size_bytes);
++			adev->psp.ta_hdcp_start_addr = (uint8_t *)ta_hdr +
++				le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
++
++			adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
++
++			adev->psp.ta_dtm_ucode_version = le32_to_cpu(ta_hdr->ta_dtm_ucode_version);
++			adev->psp.ta_dtm_ucode_size = le32_to_cpu(ta_hdr->ta_dtm_size_bytes);
++			adev->psp.ta_dtm_start_addr = (uint8_t *)adev->psp.ta_hdcp_start_addr +
++				le32_to_cpu(ta_hdr->ta_dtm_offset_bytes);
++		}
+ 		break;
+ 	default:
+ 		BUG();
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4620-drm-amdgpu-Added-ASIC-specific-checks-in-gfxhub-V1.1.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4620-drm-amdgpu-Added-ASIC-specific-checks-in-gfxhub-V1.1.patch
new file mode 100644
index 00000000..7c1e2ab3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4620-drm-amdgpu-Added-ASIC-specific-checks-in-gfxhub-V1.1.patch
@@ -0,0 +1,56 @@
+From 65fbe53b9185dbdfd217fc78f88629535635b260 Mon Sep 17 00:00:00 2001
+From: John Clements <john.clements@amd.com>
+Date: Mon, 2 Dec 2019 17:57:25 +0800
+Subject: [PATCH 4620/4736] drm/amdgpu: Added ASIC specific checks in gfxhub
+ V1.1 get XGMI info
+
+Added max hive/node info checks per supported ASIC
+
+Change-Id: I1713285d7f650a1137b15d89fa000ea824421b6b
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: John Clements <john.clements@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c | 19 +++++++++++++++++--
+ 1 file changed, 17 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
+index 5e9ab8eb214a..c0ab71df0d90 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
+@@ -33,16 +33,31 @@ int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)
+ 	u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);
+ 	u32 max_region =
+ 		REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
++	u32 max_num_physical_nodes   = 0;
++	u32 max_physical_node_id     = 0;
++
++	switch (adev->asic_type) {
++	case CHIP_VEGA20:
++		max_num_physical_nodes   = 4;
++		max_physical_node_id     = 3;
++		break;
++	case CHIP_ARCTURUS:
++		max_num_physical_nodes   = 8;
++		max_physical_node_id     = 7;
++		break;
++	default:
++		return -EINVAL;
++	}
+ 
+ 	/* PF_MAX_REGION=0 means xgmi is disabled */
+ 	if (max_region) {
+ 		adev->gmc.xgmi.num_physical_nodes = max_region + 1;
+-		if (adev->gmc.xgmi.num_physical_nodes > 4)
++		if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
+ 			return -EINVAL;
+ 
+ 		adev->gmc.xgmi.physical_node_id =
+ 			REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION);
+-		if (adev->gmc.xgmi.physical_node_id > 3)
++		if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
+ 			return -EINVAL;
+ 		adev->gmc.xgmi.node_segment_size = REG_GET_FIELD(
+ 			RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE),
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4621-drm-amdgpu-sriov-No-need-the-event-3-and-4-now.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4621-drm-amdgpu-sriov-No-need-the-event-3-and-4-now.patch
new file mode 100644
index 00000000..800bdce2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4621-drm-amdgpu-sriov-No-need-the-event-3-and-4-now.patch
@@ -0,0 +1,30 @@
+From ad26699d7664f99259113ec33051ae9d3aafbdb8 Mon Sep 17 00:00:00 2001
+From: Emily Deng <Emily.Deng@amd.com>
+Date: Tue, 3 Dec 2019 01:53:10 +0800
+Subject: [PATCH 4621/4736] drm/amdgpu/sriov: No need the event 3 and 4 now
+
+As will call unload kms when initialize fail, and the unload kms will
+send event 3 and 4, so don't need event 3 and 4 in device init.
+
+Signed-off-by: Emily Deng <Emily.Deng@amd.com>
+Reviewed-by: Zhan Liu <zhan.liu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 0cef0443340d..db80dd97f0ef 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3019,8 +3019,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
+ 		}
+ 		dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
+ 		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
+-		if (amdgpu_virt_request_full_gpu(adev, false))
+-			amdgpu_virt_release_full_gpu(adev, false);
+ 		goto failed;
+ 	}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4622-drm-amdgpu-move-CS-secure-flag-next-the-structs-wher.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4622-drm-amdgpu-move-CS-secure-flag-next-the-structs-wher.patch
new file mode 100644
index 00000000..3988e602
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4622-drm-amdgpu-move-CS-secure-flag-next-the-structs-wher.patch
@@ -0,0 +1,45 @@
+From bfdfc240899956bb60f4c096e24245cb6f065974 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 27 Nov 2019 15:55:35 -0500
+Subject: [PATCH 4622/4736] drm/amdgpu: move CS secure flag next the structs
+ where it's used
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+So it's not mixed up with the CTX stuff.
+
+Reviewed-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ include/uapi/drm/amdgpu_drm.h | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
+index 989afacefb92..78f155da2105 100644
+--- a/include/uapi/drm/amdgpu_drm.h
++++ b/include/uapi/drm/amdgpu_drm.h
+@@ -224,9 +224,6 @@ union drm_amdgpu_bo_list {
+ #define AMDGPU_CTX_OP_QUERY_STATE	3
+ #define AMDGPU_CTX_OP_QUERY_STATE2	4
+ 
+-/* Flag the command submission as secure */
+-#define AMDGPU_CS_FLAGS_SECURE          (1 << 0)
+-
+ /* GPU reset status */
+ #define AMDGPU_CTX_NO_RESET		0
+ /* this the context caused it */
+@@ -615,6 +612,9 @@ struct drm_amdgpu_cs_chunk {
+ 	__u64		chunk_data;
+ };
+ 
++/* Flag the command submission as secure */
++#define AMDGPU_CS_FLAGS_SECURE          (1 << 0)
++
+ struct drm_amdgpu_cs_in {
+ 	/** Rendering context id */
+ 	__u32		ctx_id;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4623-amd-amdgpu-sriov-swSMU-disable-for-sriov.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4623-amd-amdgpu-sriov-swSMU-disable-for-sriov.patch
new file mode 100644
index 00000000..c8cda30d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4623-amd-amdgpu-sriov-swSMU-disable-for-sriov.patch
@@ -0,0 +1,47 @@
+From daae5be7cdfd04391cb447f0ec09f4ddc9feb1f9 Mon Sep 17 00:00:00 2001
+From: Jack Zhang <Jack.Zhang1@amd.com>
+Date: Mon, 2 Dec 2019 18:41:36 +0800
+Subject: [PATCH 4623/4736] amd/amdgpu/sriov swSMU disable for sriov
+
+For boards greater than ARCTURUS, and under sriov platform,
+swSMU is not supported because smu ip block is commented at
+guest driver.
+
+Generally for sriov, initialization of smu is moved to host driver.
+Thus, smu sw_init and hw_init will not be executed at guest driver.
+
+Without sw structure being initialized in guest driver, swSMU cannot
+declare to be supported.
+
+Change-Id: Idb1c577d0dc2fc67cb6e83352aba83c9a987875f
+Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index acbbafeea01c..b57239d2228b 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -529,10 +529,13 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int
+ bool is_support_sw_smu(struct amdgpu_device *adev)
+ {
+ 	if (adev->asic_type == CHIP_VEGA20)
+-		return (amdgpu_dpm == 2) ? true: false;
+-	else if (adev->asic_type >= CHIP_ARCTURUS)
+-		return true;
+-	else
++		return (amdgpu_dpm == 2) ? true : false;
++	else if (adev->asic_type >= CHIP_ARCTURUS) {
++		if (amdgpu_sriov_vf(adev))
++			return false;
++		else
++			return true;
++	} else
+ 		return false;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4624-drm-amd-display-Adding-NV14-IP-Parameters.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4624-drm-amd-display-Adding-NV14-IP-Parameters.patch
new file mode 100644
index 00000000..91901528
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4624-drm-amd-display-Adding-NV14-IP-Parameters.patch
@@ -0,0 +1,99 @@
+From cd1426784740abc2f9d7d71886ff87be1a28a58c Mon Sep 17 00:00:00 2001
+From: Zhan liu <zhan.liu@amd.com>
+Date: Mon, 2 Dec 2019 14:54:16 -0500
+Subject: [PATCH 4624/4736] drm/amd/display: Adding NV14 IP Parameters
+
+[Why]
+NV14 IP Parameters are missing.
+
+[How]
+Add IP Parameters in.
+
+Signed-off-by: Zhan liu <zhan.liu@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 68 +++++++++++++++++++
+ 1 file changed, 68 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index f30e9aef53ba..6e6e4bb2d5ac 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -150,6 +150,74 @@ struct _vcs_dpi_ip_params_st dcn2_0_ip = {
+ 	.xfc_fill_constant_bytes = 0,
+ };
+ 
++struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
++	.odm_capable = 1,
++	.gpuvm_enable = 0,
++	.hostvm_enable = 0,
++	.gpuvm_max_page_table_levels = 4,
++	.hostvm_max_page_table_levels = 4,
++	.hostvm_cached_page_table_levels = 0,
++	.num_dsc = 5,
++	.rob_buffer_size_kbytes = 168,
++	.det_buffer_size_kbytes = 164,
++	.dpte_buffer_size_in_pte_reqs_luma = 84,
++	.dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
++	.dpp_output_buffer_pixels = 2560,
++	.opp_output_buffer_lines = 1,
++	.pixel_chunk_size_kbytes = 8,
++	.pte_enable = 1,
++	.max_page_table_levels = 4,
++	.pte_chunk_size_kbytes = 2,
++	.meta_chunk_size_kbytes = 2,
++	.writeback_chunk_size_kbytes = 2,
++	.line_buffer_size_bits = 789504,
++	.is_line_buffer_bpp_fixed = 0,
++	.line_buffer_fixed_bpp = 0,
++	.dcc_supported = true,
++	.max_line_buffer_lines = 12,
++	.writeback_luma_buffer_size_kbytes = 12,
++	.writeback_chroma_buffer_size_kbytes = 8,
++	.writeback_chroma_line_buffer_width_pixels = 4,
++	.writeback_max_hscl_ratio = 1,
++	.writeback_max_vscl_ratio = 1,
++	.writeback_min_hscl_ratio = 1,
++	.writeback_min_vscl_ratio = 1,
++	.writeback_max_hscl_taps = 12,
++	.writeback_max_vscl_taps = 12,
++	.writeback_line_buffer_luma_buffer_size = 0,
++	.writeback_line_buffer_chroma_buffer_size = 14643,
++	.cursor_buffer_size = 8,
++	.cursor_chunk_size = 2,
++	.max_num_otg = 5,
++	.max_num_dpp = 5,
++	.max_num_wb = 1,
++	.max_dchub_pscl_bw_pix_per_clk = 4,
++	.max_pscl_lb_bw_pix_per_clk = 2,
++	.max_lb_vscl_bw_pix_per_clk = 4,
++	.max_vscl_hscl_bw_pix_per_clk = 4,
++	.max_hscl_ratio = 8,
++	.max_vscl_ratio = 8,
++	.hscl_mults = 4,
++	.vscl_mults = 4,
++	.max_hscl_taps = 8,
++	.max_vscl_taps = 8,
++	.dispclk_ramp_margin_percent = 1,
++	.underscan_factor = 1.10,
++	.min_vblank_lines = 32, //
++	.dppclk_delay_subtotal = 77, //
++	.dppclk_delay_scl_lb_only = 16,
++	.dppclk_delay_scl = 50,
++	.dppclk_delay_cnvc_formatter = 8,
++	.dppclk_delay_cnvc_cursor = 6,
++	.dispclk_delay_subtotal = 87, //
++	.dcfclk_cstate_latency = 10, // SRExitTime
++	.max_inter_dcn_tile_repeaters = 8,
++	.xfc_supported = true,
++	.xfc_fill_bw_overhead_percent = 10.0,
++	.xfc_fill_constant_bytes = 0,
++	.ptoi_supported = 0
++};
++
+ struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
+ 	/* Defaults that get patched on driver load from firmware. */
+ 	.clock_limits = {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4625-drm-amd-display-Get-NV14-specific-ip-params-as-neede.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4625-drm-amd-display-Get-NV14-specific-ip-params-as-neede.patch
new file mode 100644
index 00000000..64897879
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4625-drm-amd-display-Get-NV14-specific-ip-params-as-neede.patch
@@ -0,0 +1,38 @@
+From ab2c209b31ddbf37089a6093112c51231d80fd2d Mon Sep 17 00:00:00 2001
+From: Zhan liu <zhan.liu@amd.com>
+Date: Mon, 2 Dec 2019 15:12:27 -0500
+Subject: [PATCH 4625/4736] drm/amd/display: Get NV14 specific ip params as
+ needed
+
+[Why]
+NV14 is using its own ip params that's different from other
+DCN2.0 ASICs.
+
+[How]
+Add ASIC revision check to make sure NV14 gets correct
+ip params.
+
+Signed-off-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 6e6e4bb2d5ac..f26f79134000 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -3250,6 +3250,10 @@ static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
+ static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
+ 	uint32_t hw_internal_rev)
+ {
++	/* NV14 */
++	if (ASICREV_IS_NAVI14_M(hw_internal_rev))
++		return &dcn2_0_nv14_ip;
++
+ 	/* NV12 and NV10 */
+ 	return &dcn2_0_ip;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4626-drm-amd-display-re-enable-wait-in-pipelock-but-add-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4626-drm-amd-display-re-enable-wait-in-pipelock-but-add-t.patch
new file mode 100644
index 00000000..04814a9e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4626-drm-amd-display-re-enable-wait-in-pipelock-but-add-t.patch
@@ -0,0 +1,50 @@
+From d3dfff4a56eab00907d27cec27f84ce2a472ee07 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 15 Nov 2019 10:02:44 -0500
+Subject: [PATCH 4626/4736] drm/amd/display: re-enable wait in pipelock, but
+ add timeout
+
+Removing this causes hangs in some games, so re-add it, but add
+a timeout so we don't hang while switching flip types.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205169
+Bug: https://bugs.freedesktop.org/show_bug.cgi?id=112266
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 868099fbe8ba..fa1ecff747a1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1032,6 +1032,25 @@ void dcn20_pipe_control_lock(
+ 	if (pipe->plane_state != NULL)
+ 		flip_immediate = pipe->plane_state->flip_immediate;
+ 
++	if (flip_immediate && lock) {
++		const int TIMEOUT_FOR_FLIP_PENDING = 100000;
++		int i;
++
++		for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
++			if (!pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp))
++				break;
++			udelay(1);
++		}
++
++		if (pipe->bottom_pipe != NULL) {
++			for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
++				if (!pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp))
++					break;
++				udelay(1);
++			}
++		}
++	}
++
+ 	/* In flip immediate and pipe splitting case, we need to use GSL
+ 	 * for synchronization. Only do setup on locking and on flip type change.
+ 	 */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4627-drm-amd-display-fix-double-assignment-to-msg_id-fiel.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4627-drm-amd-display-fix-double-assignment-to-msg_id-fiel.patch
new file mode 100644
index 00000000..ed6e2dfb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4627-drm-amd-display-fix-double-assignment-to-msg_id-fiel.patch
@@ -0,0 +1,34 @@
+From 906a1abc5579e083db64a97aa813727025f5e5b9 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Wed, 20 Nov 2019 17:22:42 +0000
+Subject: [PATCH 4627/4736] drm/amd/display: fix double assignment to msg_id
+ field
+
+The msg_id field is being assigned twice. Fix this by replacing the second
+assignment with an assignment to msg_size.
+
+Addresses-Coverity: ("Unused value")
+Fixes: 11a00965d261 ("drm/amd/display: Add PSP block to verify HDCP2.2 steps")
+Reviewed-by: Harry Wentland <harry.wentland>
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+index 468f5e6c3487..ef4eb55f4474 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+@@ -42,7 +42,7 @@ static void hdcp2_message_init(struct mod_hdcp *hdcp,
+ 	in->process.msg2_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
+ 	in->process.msg2_desc.msg_size = 0;
+ 	in->process.msg3_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
+-	in->process.msg3_desc.msg_id = 0;
++	in->process.msg3_desc.msg_size = 0;
+ }
+ enum mod_hdcp_status mod_hdcp_remove_display_topology(struct mod_hdcp *hdcp)
+ {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4628-drm-amd-display-Remove-unneeded-semicolon-in-bios_pa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4628-drm-amd-display-Remove-unneeded-semicolon-in-bios_pa.patch
new file mode 100644
index 00000000..48b8e862
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4628-drm-amd-display-Remove-unneeded-semicolon-in-bios_pa.patch
@@ -0,0 +1,34 @@
+From 1d8164492291c41bf6fa12192c135b230c5b9478 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Thu, 28 Nov 2019 10:31:37 +0800
+Subject: [PATCH 4628/4736] drm/amd/display: Remove unneeded semicolon in
+ bios_parser.c
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/display/dc/bios/bios_parser.c:2192:2-3: Unneeded semicolon
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+index 714a862e7321..ca6a6a707619 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+@@ -2187,7 +2187,7 @@ static uint32_t get_support_mask_for_device_id(struct device_id device_id)
+ 		break;
+ 	default:
+ 		break;
+-	};
++	}
+ 
+ 	/* Unidentified device ID, return empty support mask. */
+ 	return 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4629-drm-amd-display-Remove-unneeded-semicolon-in-bios_pa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4629-drm-amd-display-Remove-unneeded-semicolon-in-bios_pa.patch
new file mode 100644
index 00000000..c4ae0f0c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4629-drm-amd-display-Remove-unneeded-semicolon-in-bios_pa.patch
@@ -0,0 +1,34 @@
+From 3a2f32f2c447c8973de693aeaef4136558c2fe66 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Thu, 28 Nov 2019 10:31:38 +0800
+Subject: [PATCH 4629/4736] drm/amd/display: Remove unneeded semicolon in
+ bios_parser2.c
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c:995:2-3: Unneeded semicolon
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index c70bfdca5d2f..453ac65c7ee3 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -990,7 +990,7 @@ static uint32_t get_support_mask_for_device_id(struct device_id device_id)
+ 		break;
+ 	default:
+ 		break;
+-	};
++	}
+ 
+ 	/* Unidentified device ID, return empty support mask. */
+ 	return 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4630-drm-amd-display-Remove-unneeded-semicolon-in-hdcp.c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4630-drm-amd-display-Remove-unneeded-semicolon-in-hdcp.c.patch
new file mode 100644
index 00000000..041f3700
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4630-drm-amd-display-Remove-unneeded-semicolon-in-hdcp.c.patch
@@ -0,0 +1,34 @@
+From f48b5b7ba85e258dfdc3eb0fb081cdebe54e8292 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Thu, 28 Nov 2019 10:31:39 +0800
+Subject: [PATCH 4630/4736] drm/amd/display: Remove unneeded semicolon in
+ hdcp.c
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c:506:2-3: Unneeded semicolon
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+index cbb5e9c063ec..8aa528e874c4 100644
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
+@@ -503,7 +503,7 @@ enum mod_hdcp_operation_mode mod_hdcp_signal_type_to_operation_mode(
+ 		break;
+ 	default:
+ 		break;
+-	};
++	}
+ 
+ 	return mode;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4631-drm-amd-display-Remove-unneeded-semicolon-in-display.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4631-drm-amd-display-Remove-unneeded-semicolon-in-display.patch
new file mode 100644
index 00000000..765d2b04
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4631-drm-amd-display-Remove-unneeded-semicolon-in-display.patch
@@ -0,0 +1,37 @@
+From 6bd201a6362cba670547da90bce90900e82e5d54 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Thu, 28 Nov 2019 10:31:40 +0800
+Subject: [PATCH 4631/4736] drm/amd/display: Remove unneeded semicolon in
+ display_rq_dlg_calc_21.c
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:1525:144-145: Unneeded semicolon
+drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:1526:142-143: Unneeded semicolon
+
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+index a4b103eb4b02..e60af383b4db 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+@@ -1522,8 +1522,8 @@ static void dml_rq_dlg_get_dlg_params(
+ 
+ 	disp_dlg_regs->refcyc_per_vm_group_vblank   = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;
+ 	disp_dlg_regs->refcyc_per_vm_group_flip     = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;
+-	disp_dlg_regs->refcyc_per_vm_req_vblank     = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;;
+-	disp_dlg_regs->refcyc_per_vm_req_flip       = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;;
++	disp_dlg_regs->refcyc_per_vm_req_vblank     = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;
++	disp_dlg_regs->refcyc_per_vm_req_flip       = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;
+ 
+ 	// Clamp to max for now
+ 	if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23))
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4632-drm-amd-display-remove-redundant-assignment-to-varia.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4632-drm-amd-display-remove-redundant-assignment-to-varia.patch
new file mode 100644
index 00000000..d736a34d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4632-drm-amd-display-remove-redundant-assignment-to-varia.patch
@@ -0,0 +1,33 @@
+From 517a2607999a6e4cdb4c8cdf8e21d3c7409a0466 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Mon, 2 Dec 2019 15:47:38 +0000
+Subject: [PATCH 4632/4736] drm/amd/display: remove redundant assignment to
+ variable v_total
+
+The variable v_total is being initialized with a value that is never
+read and it is being updated later with a new value.  The initialization
+is redundant and can be removed.
+
+Addresses-Coverity: ("Unused value")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+index 9d68cfecd472..52c8edbde2c4 100644
+--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
++++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+@@ -120,7 +120,7 @@ static unsigned int calc_v_total_from_refresh(
+ 		const struct dc_stream_state *stream,
+ 		unsigned int refresh_in_uhz)
+ {
+-	unsigned int v_total = stream->timing.v_total;
++	unsigned int v_total;
+ 	unsigned int frame_duration_in_ns;
+ 
+ 	frame_duration_in_ns =
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4633-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4633-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch
new file mode 100644
index 00000000..6e78bf97
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4633-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch
@@ -0,0 +1,38 @@
+From 1464891b5a6c0e9ea6ff2320a78285b2220b35f9 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Wed, 27 Nov 2019 17:33:38 +0800
+Subject: [PATCH 4633/4736] drm/amd/powerplay: Remove unneeded variable
+ 'result' in smu10_hwmgr.c
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c:1154:5-11: Unneeded variable: "result". Return "0" on line 1159
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+index 1115761982a7..4e8ab139bb3b 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+@@ -1151,12 +1151,11 @@ static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
+ 	struct smu10_hwmgr *data = hwmgr->backend;
+ 	struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
+ 	Watermarks_t *table = &(data->water_marks_table);
+-	int result = 0;
+ 
+ 	smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges);
+ 	smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);
+ 	data->water_marks_exist = true;
+-	return result;
++	return 0;
+ }
+ 
+ static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4634-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4634-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch
new file mode 100644
index 00000000..8c3a4f7f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4634-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch
@@ -0,0 +1,40 @@
+From c1b1e01ed7586270e02cd5b9218524bcb028798d Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Wed, 27 Nov 2019 17:33:39 +0800
+Subject: [PATCH 4634/4736] drm/amd/powerplay: Remove unneeded variable
+ 'result' in vega10_hwmgr.c
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c:4363:5-11: Unneeded variable: "result". Return "0" on line 4370
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+index b8cb492102ff..56feae198cae 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+@@ -4359,14 +4359,13 @@ static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
+ 	struct vega10_hwmgr *data = hwmgr->backend;
+ 	struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
+ 	Watermarks_t *table = &(data->smc_state_table.water_marks_table);
+-	int result = 0;
+ 
+ 	if (!data->registry_data.disable_water_mark) {
+ 		smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
+ 		data->water_marks_bitmap = WaterMarksExist;
+ 	}
+ 
+-	return result;
++	return 0;
+ }
+ 
+ static int vega10_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4635-drm-amd-powerplay-Remove-unneeded-variable-ret-in-sm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4635-drm-amd-powerplay-Remove-unneeded-variable-ret-in-sm.patch
new file mode 100644
index 00000000..c8ef1dc9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4635-drm-amd-powerplay-Remove-unneeded-variable-ret-in-sm.patch
@@ -0,0 +1,39 @@
+From e706756e7a90fd3577282f32683b43a141834f40 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Wed, 27 Nov 2019 17:33:40 +0800
+Subject: [PATCH 4635/4736] drm/amd/powerplay: Remove unneeded variable 'ret'
+ in smu7_hwmgr.c
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c:5188:5-8: Unneeded variable: "ret". Return "0" on line 5196
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+index 901b5c263744..9e915f680c01 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -5184,13 +5184,11 @@ uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
+ 
+ int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
+ {
+-	int ret = 0;
+-
+ 	hwmgr->hwmgr_func = &smu7_hwmgr_funcs;
+ 	if (hwmgr->pp_table_version == PP_TABLE_V0)
+ 		hwmgr->pptable_func = &pptable_funcs;
+ 	else if (hwmgr->pp_table_version == PP_TABLE_V1)
+ 		hwmgr->pptable_func = &pptable_v1_0_funcs;
+ 
+-	return ret;
++	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4636-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4636-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch
new file mode 100644
index 00000000..a01c0ef4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4636-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch
@@ -0,0 +1,42 @@
+From be1308d03d686e74251b9ea6290c03710ec9f2c0 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Wed, 27 Nov 2019 17:33:41 +0800
+Subject: [PATCH 4636/4736] drm/amd/powerplay: Remove unneeded variable
+ 'result' in vega12_hwmgr.c
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c:502:5-11: Unneeded variable: "result". Return "0" on line 515
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+index 7af9ad450ac4..aca61d1ff3c2 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+@@ -499,8 +499,6 @@ static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
+ static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
+ 		PPCLK_e clkID, uint32_t index, uint32_t *clock)
+ {
+-	int result = 0;
+-
+ 	/*
+ 	 *SMU expects the Clock ID to be in the top 16 bits.
+ 	 *Lower 16 bits specify the level
+@@ -512,7 +510,7 @@ static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
+ 
+ 	*clock = smum_get_argument(hwmgr);
+ 
+-	return result;
++	return 0;
+ }
+ 
+ static int vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4637-drm-amd-powerplay-Remove-unneeded-variable-ret-in-am.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4637-drm-amd-powerplay-Remove-unneeded-variable-ret-in-am.patch
new file mode 100644
index 00000000..9185f4ed
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4637-drm-amd-powerplay-Remove-unneeded-variable-ret-in-am.patch
@@ -0,0 +1,63 @@
+From 53207ce79068fdbac329a781fbe2a7a8802036d1 Mon Sep 17 00:00:00 2001
+From: zhengbin <zhengbin13@huawei.com>
+Date: Wed, 27 Nov 2019 17:33:42 +0800
+Subject: [PATCH 4637/4736] drm/amd/powerplay: Remove unneeded variable 'ret'
+ in amdgpu_smu.c
+
+Fixes coccicheck warning:
+
+drivers/gpu/drm/amd/powerplay/amdgpu_smu.c:1192:5-8: Unneeded variable: "ret". Return "0" on line 1195
+drivers/gpu/drm/amd/powerplay/amdgpu_smu.c:1945:5-8: Unneeded variable: "ret". Return "0" on line 1961
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: zhengbin <zhengbin13@huawei.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index b57239d2228b..42656628de90 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1192,10 +1192,9 @@ static int smu_free_memory_pool(struct smu_context *smu)
+ {
+ 	struct smu_table_context *smu_table = &smu->smu_table;
+ 	struct smu_table *memory_pool = &smu_table->memory_pool;
+-	int ret = 0;
+ 
+ 	if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
+-		return ret;
++		return 0;
+ 
+ 	amdgpu_bo_free_kernel(&memory_pool->bo,
+ 			      &memory_pool->mc_address,
+@@ -1203,7 +1202,7 @@ static int smu_free_memory_pool(struct smu_context *smu)
+ 
+ 	memset(memory_pool, 0, sizeof(struct smu_table));
+ 
+-	return ret;
++	return 0;
+ }
+ 
+ static int smu_start_smc_engine(struct smu_context *smu)
+@@ -1945,7 +1944,6 @@ int smu_write_watermarks_table(struct smu_context *smu)
+ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
+ 		struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
+ {
+-	int ret = 0;
+ 	struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
+ 	void *table = watermarks->cpu_addr;
+ 
+@@ -1961,7 +1959,7 @@ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
+ 
+ 	mutex_unlock(&smu->mutex);
+ 
+-	return ret;
++	return 0;
+ }
+ 
+ const struct amd_ip_funcs smu_ip_funcs = {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4638-Revert-drm-amdgpu-Set-GTT-size-to-be-bigger-than-3-4.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4638-Revert-drm-amdgpu-Set-GTT-size-to-be-bigger-than-3-4.patch
new file mode 100644
index 00000000..2c806064
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4638-Revert-drm-amdgpu-Set-GTT-size-to-be-bigger-than-3-4.patch
@@ -0,0 +1,39 @@
+From 7d92d9d1d3705c164cbbb83b26c0b404efcafdce Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Tue, 3 Dec 2019 19:59:55 +0800
+Subject: [PATCH 4638/4736] Revert "drm/amdgpu: Set GTT size to be bigger than
+ 3/4 of RAM"
+
+This reverts commit 55dc9b6a685260f4545a0f16c16bec9756b71a86.
+
+This commit will cause oom issue when do vulcan CTS Test.
+
+Signed-off-by:Kevin Wang <kevin1.wang@amd.com>
+Acked-by: Feifei Xu <feifei.xue@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 9 +++++----
+ 1 file changed, 5 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index d93bfaca5daf..6d295e7ee444 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -2156,10 +2156,11 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
+ 		struct sysinfo si;
+ 
+ 		si_meminfo(&si);
+-		gtt_size = max3((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
+-				adev->gmc.mc_vram_size,
+-				((uint64_t)si.totalram * si.mem_unit));
+-	} else
++		gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
++			       adev->gmc.mc_vram_size),
++			       ((uint64_t)si.totalram * si.mem_unit * 3/4));
++	}
++	else
+ 		gtt_size = (uint64_t)amdgpu_gtt_size << 20;
+ 
+ 	/* reserve for DGMA import domain */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4639-drm-amdgpu-drop-asd-shared-memory.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4639-drm-amdgpu-drop-asd-shared-memory.patch
new file mode 100644
index 00000000..90e27fd3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4639-drm-amdgpu-drop-asd-shared-memory.patch
@@ -0,0 +1,156 @@
+From d28621c36f48e8359a71a37f1f4f2e524e1cd9f8 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 2 Dec 2019 13:16:09 +0800
+Subject: [PATCH 4639/4736] drm/amdgpu: drop asd shared memory
+
+asd shared memory is not needed since drivers doesn't
+invoke any further cmd to asd directly after the asd
+loading. trust application is the one who needs
+to talk to asd after the initialization
+
+Change-Id: I4d3422cb8a2c27ece99a7373069dfc27898c5ecc
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 44 +++++++------------------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 12 ++++---
+ 2 files changed, 18 insertions(+), 38 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index f219e2f77b4c..ccd0c8d7c224 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -320,35 +320,17 @@ static int psp_tmr_load(struct psp_context *psp)
+ 	return ret;
+ }
+ 
+-static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
+-				 uint64_t asd_mc, uint64_t asd_mc_shared,
+-				 uint32_t size, uint32_t shared_size)
++static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
++				uint64_t asd_mc, uint32_t size)
+ {
+ 	cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
+ 	cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
+ 	cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
+ 	cmd->cmd.cmd_load_ta.app_len = size;
+ 
+-	cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
+-	cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
+-	cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
+-}
+-
+-static int psp_asd_init(struct psp_context *psp)
+-{
+-	int ret;
+-
+-	/*
+-	 * Allocate 16k memory aligned to 4k from Frame Buffer (local
+-	 * physical) for shared ASD <-> Driver
+-	 */
+-	ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
+-				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
+-				      &psp->asd_shared_bo,
+-				      &psp->asd_shared_mc_addr,
+-				      &psp->asd_shared_buf);
+-
+-	return ret;
++	cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0;
++	cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0;
++	cmd->cmd.cmd_load_ta.cmd_buf_len = 0;
+ }
+ 
+ static int psp_asd_load(struct psp_context *psp)
+@@ -370,11 +352,15 @@ static int psp_asd_load(struct psp_context *psp)
+ 	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
+ 	memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
+ 
+-	psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
+-			     psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
++	psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
++				  psp->asd_ucode_size);
+ 
+ 	ret = psp_cmd_submit_buf(psp, NULL, cmd,
+ 				 psp->fence_buf_mc_addr);
++	if (!ret) {
++		psp->asd_context.asd_initialized = true;
++		psp->asd_context.session_id = cmd->resp.session_id;
++	}
+ 
+ 	kfree(cmd);
+ 
+@@ -1213,12 +1199,6 @@ static int psp_hw_start(struct psp_context *psp)
+ 		return ret;
+ 	}
+ 
+-	ret = psp_asd_init(psp);
+-	if (ret) {
+-		DRM_ERROR("PSP asd init failed!\n");
+-		return ret;
+-	}
+-
+ 	ret = psp_asd_load(psp);
+ 	if (ret) {
+ 		DRM_ERROR("PSP load asd failed!\n");
+@@ -1632,8 +1612,6 @@ static int psp_hw_fini(void *handle)
+ 			      &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
+ 	amdgpu_bo_free_kernel(&psp->fence_buf_bo,
+ 			      &psp->fence_buf_mc_addr, &psp->fence_buf);
+-	amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
+-			      &psp->asd_shared_buf);
+ 	amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
+ 			      (void **)&psp->cmd_buf_mem);
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+index 40594f27dab1..5f8fd3e3535b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+@@ -32,7 +32,6 @@
+ 
+ #define PSP_FENCE_BUFFER_SIZE	0x1000
+ #define PSP_CMD_BUFFER_SIZE	0x1000
+-#define PSP_ASD_SHARED_MEM_SIZE 0x4000
+ #define PSP_XGMI_SHARED_MEM_SIZE 0x4000
+ #define PSP_RAS_SHARED_MEM_SIZE 0x4000
+ #define PSP_1_MEG		0x100000
+@@ -130,6 +129,11 @@ struct psp_xgmi_topology_info {
+ 	struct psp_xgmi_node_info	nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
+ };
+ 
++struct psp_asd_context {
++	bool			asd_initialized;
++	uint32_t		session_id;
++};
++
+ struct psp_xgmi_context {
+ 	uint8_t				initialized;
+ 	uint32_t			session_id;
+@@ -238,15 +242,12 @@ struct psp_context
+ 	struct amdgpu_bo		*tmr_bo;
+ 	uint64_t			tmr_mc_addr;
+ 
+-	/* asd firmware and buffer */
++	/* asd firmware */
+ 	const struct firmware		*asd_fw;
+ 	uint32_t			asd_fw_version;
+ 	uint32_t			asd_feature_version;
+ 	uint32_t			asd_ucode_size;
+ 	uint8_t				*asd_start_addr;
+-	struct amdgpu_bo		*asd_shared_bo;
+-	uint64_t			asd_shared_mc_addr;
+-	void				*asd_shared_buf;
+ 
+ 	/* fence buffer */
+ 	struct amdgpu_bo		*fence_buf_bo;
+@@ -281,6 +282,7 @@ struct psp_context
+ 	uint32_t			ta_dtm_ucode_size;
+ 	uint8_t				*ta_dtm_start_addr;
+ 
++	struct psp_asd_context		asd_context;
+ 	struct psp_xgmi_context		xgmi_context;
+ 	struct psp_ras_context		ras;
+ 	struct psp_hdcp_context 	hdcp_context;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4640-drm-amdgpu-unload-asd-in-psp-hw-de-init-phase.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4640-drm-amdgpu-unload-asd-in-psp-hw-de-init-phase.patch
new file mode 100644
index 00000000..540b2d02
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4640-drm-amdgpu-unload-asd-in-psp-hw-de-init-phase.patch
@@ -0,0 +1,72 @@
+From ae5de338aad5f6a846bf2398df484b4b62bf56e2 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 2 Dec 2019 13:37:42 +0800
+Subject: [PATCH 4640/4736] drm/amdgpu: unload asd in psp hw de-init phase
+
+issue unload_ta_cmd to tOS to unload asd driver
+
+Change-Id: I8edde7e57bb1920f897e16354f2fb4103a51f656
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 36 +++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index ccd0c8d7c224..fe2b24e98268 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -367,6 +367,40 @@ static int psp_asd_load(struct psp_context *psp)
+ 	return ret;
+ }
+ 
++static void psp_prep_asd_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
++					uint32_t asd_session_id)
++{
++	cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
++	cmd->cmd.cmd_unload_ta.session_id = asd_session_id;
++}
++
++static int psp_asd_unload(struct psp_context *psp)
++{
++	int ret;
++	struct psp_gfx_cmd_resp *cmd;
++
++	if (amdgpu_sriov_vf(psp->adev))
++		return 0;
++
++	if (!psp->asd_context.asd_initialized)
++		return 0;
++
++	cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
++	if (!cmd)
++		return -ENOMEM;
++
++	psp_prep_asd_unload_cmd_buf(cmd, psp->asd_context.session_id);
++
++	ret = psp_cmd_submit_buf(psp, NULL, cmd,
++				 psp->fence_buf_mc_addr);
++	if (!ret)
++		psp->asd_context.asd_initialized = false;
++
++	kfree(cmd);
++
++	return ret;
++}
++
+ static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
+ 		uint32_t id, uint32_t value)
+ {
+@@ -1604,6 +1638,8 @@ static int psp_hw_fini(void *handle)
+ 		psp_hdcp_terminate(psp);
+ 	}
+ 
++	psp_asd_unload(psp);
++
+ 	psp_ring_destroy(psp, PSP_RING_TYPE__KM);
+ 
+ 	pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4641-drm-amdgpu-load-np-fw-prior-before-loading-the-TAs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4641-drm-amdgpu-load-np-fw-prior-before-loading-the-TAs.patch
new file mode 100644
index 00000000..cb2e1dd4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4641-drm-amdgpu-load-np-fw-prior-before-loading-the-TAs.patch
@@ -0,0 +1,106 @@
+From 3e741d06ad7e1011e809c9427f2be3b830167730 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 2 Dec 2019 13:44:38 +0800
+Subject: [PATCH 4641/4736] drm/amdgpu: load np fw prior before loading the TAs
+
+Platform TAs will independently toggle DF Cstate.
+for instance, get/set topology from xgmi ta. do error
+injection from ras ta. In such case, PMFW needs to be
+loaded before TAs so that all the subsequent Cstate
+calls recieved by PSP FW can be routed to PMFW.
+
+Change-Id: I2e24b05d083349963b48674581a265bbceea1ecd
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Acked-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 66 ++++++++++++-------------
+ 1 file changed, 33 insertions(+), 33 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index fe2b24e98268..728f53ea2ad6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1233,39 +1233,6 @@ static int psp_hw_start(struct psp_context *psp)
+ 		return ret;
+ 	}
+ 
+-	ret = psp_asd_load(psp);
+-	if (ret) {
+-		DRM_ERROR("PSP load asd failed!\n");
+-		return ret;
+-	}
+-
+-	if (adev->gmc.xgmi.num_physical_nodes > 1) {
+-		ret = psp_xgmi_initialize(psp);
+-		/* Warning the XGMI seesion initialize failure
+-		 * Instead of stop driver initialization
+-		 */
+-		if (ret)
+-			dev_err(psp->adev->dev,
+-				"XGMI: Failed to initialize XGMI session\n");
+-	}
+-
+-	if (psp->adev->psp.ta_fw) {
+-		ret = psp_ras_initialize(psp);
+-		if (ret)
+-			dev_err(psp->adev->dev,
+-					"RAS: Failed to initialize RAS\n");
+-
+-		ret = psp_hdcp_initialize(psp);
+-		if (ret)
+-			dev_err(psp->adev->dev,
+-				"HDCP: Failed to initialize HDCP\n");
+-
+-		ret = psp_dtm_initialize(psp);
+-		if (ret)
+-			dev_err(psp->adev->dev,
+-				"DTM: Failed to initialize DTM\n");
+-	}
+-
+ 	return 0;
+ }
+ 
+@@ -1581,6 +1548,39 @@ static int psp_load_fw(struct amdgpu_device *adev)
+ 	if (ret)
+ 		goto failed;
+ 
++	ret = psp_asd_load(psp);
++	if (ret) {
++		DRM_ERROR("PSP load asd failed!\n");
++		return ret;
++	}
++
++	if (adev->gmc.xgmi.num_physical_nodes > 1) {
++		ret = psp_xgmi_initialize(psp);
++		/* Warning the XGMI seesion initialize failure
++		 * Instead of stop driver initialization
++		 */
++		if (ret)
++			dev_err(psp->adev->dev,
++				"XGMI: Failed to initialize XGMI session\n");
++	}
++
++	if (psp->adev->psp.ta_fw) {
++		ret = psp_ras_initialize(psp);
++		if (ret)
++			dev_err(psp->adev->dev,
++					"RAS: Failed to initialize RAS\n");
++
++		ret = psp_hdcp_initialize(psp);
++		if (ret)
++			dev_err(psp->adev->dev,
++				"HDCP: Failed to initialize HDCP\n");
++
++		ret = psp_dtm_initialize(psp);
++		if (ret)
++			dev_err(psp->adev->dev,
++				"DTM: Failed to initialize DTM\n");
++	}
++
+ 	return 0;
+ 
+ failed:
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4642-drm-amdkfd-Contain-MMHUB-number-in-mmhub_v9_4_setup_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4642-drm-amdkfd-Contain-MMHUB-number-in-mmhub_v9_4_setup_.patch
new file mode 100644
index 00000000..f46109c9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4642-drm-amdkfd-Contain-MMHUB-number-in-mmhub_v9_4_setup_.patch
@@ -0,0 +1,114 @@
+From 1bfa29f65120b85cf1a90140f62cc8f0cdd150d1 Mon Sep 17 00:00:00 2001
+From: Yong Zhao <Yong.Zhao@amd.com>
+Date: Mon, 2 Dec 2019 23:12:10 -0500
+Subject: [PATCH 4642/4736] drm/amdkfd: Contain MMHUB number in
+ mmhub_v9_4_setup_vm_pt_regs()
+
+Adjust the exposed function prototype so that the caller does not need
+to know the MMHUB number.
+
+Change-Id: I4420d1715984f703954f074682b075fc59e2a330
+Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c |  6 ++----
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h             |  8 --------
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c           | 14 ++++++++++++--
+ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h           |  2 ++
+ 4 files changed, 16 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+index f1884b3941e2..4e3570e0e394 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+@@ -41,7 +41,7 @@
+ #include "soc15d.h"
+ #include "mmhub_v1_0.h"
+ #include "gfxhub_v1_0.h"
+-#include "gmc_v9_0.h"
++#include "mmhub_v9_4.h"
+ 
+ 
+ enum hqd_dequeue_request_type {
+@@ -962,9 +962,7 @@ void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmi
+ 	 * on GFX8 and older.
+ 	 */
+ 	if (adev->asic_type == CHIP_ARCTURUS) {
+-		/* Two MMHUBs */
+-		mmhub_v9_4_setup_vm_pt_regs(adev, 0, vmid, page_table_base);
+-		mmhub_v9_4_setup_vm_pt_regs(adev, 1, vmid, page_table_base);
++		mmhub_v9_4_setup_vm_pt_regs(adev, vmid, page_table_base);
+ 	} else
+ 		mmhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base);
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
+index 971c0840358f..49e8be761214 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
+@@ -36,12 +36,4 @@
+ 
+ extern const struct amd_ip_funcs gmc_v9_0_ip_funcs;
+ extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block;
+-
+-/* amdgpu_amdkfd*.c */
+-void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
+-				uint64_t value);
+-void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
+-				uint64_t value);
+-void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, int hubid,
+-				uint32_t vmid, uint64_t value);
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+index 8599bfdb9a9e..d9301e80522a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+@@ -54,7 +54,7 @@ u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev)
+ 	return base;
+ }
+ 
+-void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, int hubid,
++static void mmhub_v9_4_setup_hubid_vm_pt_regs(struct amdgpu_device *adev, int hubid,
+ 				uint32_t vmid, uint64_t value)
+ {
+ 	/* two registers distance between mmVML2VC0_VM_CONTEXT0_* to
+@@ -80,7 +80,7 @@ static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev,
+ {
+ 	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
+ 
+-	mmhub_v9_4_setup_vm_pt_regs(adev, hubid, 0, pt_base);
++	mmhub_v9_4_setup_hubid_vm_pt_regs(adev, hubid, 0, pt_base);
+ 
+ 	WREG32_SOC15_OFFSET(MMHUB, 0,
+ 			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+@@ -101,6 +101,16 @@ static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev,
+ 			    (u32)(adev->gmc.gart_end >> 44));
+ }
+ 
++void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
++				uint64_t page_table_base)
++{
++	int i;
++
++	for (i = 0; i < MMHUB_NUM_INSTANCES; i++)
++		mmhub_v9_4_setup_hubid_vm_pt_regs(adev, i, vmid,
++				page_table_base);
++}
++
+ static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev,
+ 					         int hubid)
+ {
+diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
+index 354a4b7e875b..1b979773776c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
+@@ -34,5 +34,7 @@ void mmhub_v9_4_init(struct amdgpu_device *adev);
+ int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
+ 			       enum amd_clockgating_state state);
+ void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags);
++void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
++				uint64_t page_table_base);
+ 
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4643-drm-scheduler-Avoid-accessing-freed-bad-job.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4643-drm-scheduler-Avoid-accessing-freed-bad-job.patch
new file mode 100644
index 00000000..a2a0a85d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4643-drm-scheduler-Avoid-accessing-freed-bad-job.patch
@@ -0,0 +1,97 @@
+From de6e01403013d5d7ec970b8b4eb4ca07cc736d19 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Mon, 25 Nov 2019 15:51:29 -0500
+Subject: [PATCH 4643/4736] drm/scheduler: Avoid accessing freed bad job.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Problem:
+Due to a race between drm_sched_cleanup_jobs in sched thread and
+drm_sched_job_timedout in timeout work there is a possiblity that
+bad job was already freed while still being accessed from the
+timeout thread.
+
+Fix:
+Instead of just peeking at the bad job in the mirror list
+remove it from the list under lock and then put it back later when
+we are garanteed no race with main sched thread is possible which
+is after the thread is parked.
+
+v2: Lock around processing ring_mirror_list in drm_sched_cleanup_jobs.
+
+v3: Rebase on top of drm-misc-next. v2 is not needed anymore as
+drm_sched_get_cleanup_job already has a lock there.
+
+v4: Fix comments to relfect latest code in drm-misc.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Emily Deng <Emily.Deng@amd.com>
+Tested-by: Emily Deng <Emily.Deng@amd.com>
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Link: https://patchwork.freedesktop.org/patch/342356
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/scheduler/sched_main.c | 27 ++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c
+index 108bac88dedb..0ccce80513e5 100644
+--- a/drivers/gpu/drm/scheduler/sched_main.c
++++ b/drivers/gpu/drm/scheduler/sched_main.c
+@@ -288,10 +288,21 @@ static void drm_sched_job_timedout(struct work_struct *work)
+ 	unsigned long flags;
+ 
+ 	sched = container_of(work, struct drm_gpu_scheduler, work_tdr.work);
++
++	/* Protects against concurrent deletion in drm_sched_get_cleanup_job */
++	spin_lock_irqsave(&sched->job_list_lock, flags);
+ 	job = list_first_entry_or_null(&sched->ring_mirror_list,
+ 				       struct drm_sched_job, node);
+ 
+ 	if (job) {
++		/*
++		 * Remove the bad job so it cannot be freed by concurrent
++		 * drm_sched_cleanup_jobs. It will be reinserted back after sched->thread
++		 * is parked at which point it's safe.
++		 */
++		list_del_init(&job->node);
++		spin_unlock_irqrestore(&sched->job_list_lock, flags);
++
+ 		job->sched->ops->timedout_job(job);
+ 
+ 		/*
+@@ -302,6 +313,8 @@ static void drm_sched_job_timedout(struct work_struct *work)
+ 			job->sched->ops->free_job(job);
+ 			sched->free_guilty = false;
+ 		}
++	} else {
++		spin_unlock_irqrestore(&sched->job_list_lock, flags);
+ 	}
+ 
+ 	spin_lock_irqsave(&sched->job_list_lock, flags);
+@@ -413,6 +426,20 @@ void drm_sched_stop(struct drm_gpu_scheduler *sched, struct drm_sched_job *bad)
+ 		}
+ 	}
+ 
++	/*
++	 * Reinsert back the bad job here - now it's safe as
++	 * drm_sched_get_cleanup_job cannot race against us and release the
++	 * bad job at this point - we parked (waited for) any in progress
++	 * (earlier) cleanups and drm_sched_get_cleanup_job will not be called
++	 * now until the scheduler thread is unparked.
++	 */
++	if (bad && bad->sched == sched)
++		/*
++		 * Add at the head of the queue to reflect it was the earliest
++		 * job extracted.
++		 */
++		list_add(&bad->node, &sched->ring_mirror_list);
++
+ 	/*
+ 	 * Stop pending timer in flight as we rearm it in  drm_sched_start. This
+ 	 * avoids the pending timeout work in progress to fire right away after
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4644-drm-amdkfd-kfd-debugger-set-DISPATCH_PTR.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4644-drm-amdkfd-kfd-debugger-set-DISPATCH_PTR.patch
new file mode 100644
index 00000000..5b24b5c1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4644-drm-amdkfd-kfd-debugger-set-DISPATCH_PTR.patch
@@ -0,0 +1,35 @@
+From 148030d491eb0bc69792e800291ee61722ad1a51 Mon Sep 17 00:00:00 2001
+From: "Philip.Cox@amd.com" <Philip.Cox@amd.com>
+Date: Tue, 26 Nov 2019 14:28:24 -0500
+Subject: [PATCH 4644/4736] drm/amdkfd: kfd debugger -- set DISPATCH_PTR
+
+We need to set bit 14 in mqd var CP_HQD_HQ_STATUS0 to have the CP set
+the DISPATCH_PTR which is needed for the debugger.
+
+Bug: SWDEV-208421
+
+Change-Id: I2b98afc392a9299210aa2b6faa00fc83b27e51eb
+Signed-off-by: Philip.Cox@amd.com <Philip.Cox@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+index f9ee530774bf..1b35cad950b4 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+@@ -193,6 +193,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,
+ 			1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
+ 			10 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
+ 
++	/* Set cp_hqd_hq_status0 bit 14 to 1 to have the CP set up the
++	 * DISPATCH_PTR.  This is required for the kfd debugger
++	 */
++	m->cp_hqd_hq_status0 = 1 << 14;
++
+ 	if (q->format == KFD_QUEUE_FORMAT_AQL) {
+ 		m->cp_hqd_aql_control =
+ 			1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4645-drm-amd-display-Loading-NV10-14-Bounding-Box-Data-Di.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4645-drm-amd-display-Loading-NV10-14-Bounding-Box-Data-Di.patch
new file mode 100644
index 00000000..f1a1436b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4645-drm-amd-display-Loading-NV10-14-Bounding-Box-Data-Di.patch
@@ -0,0 +1,51 @@
+From fb7b766d7643ee5bc519bc1dcc98ac0c788306df Mon Sep 17 00:00:00 2001
+From: Zhan Liu <zhan.liu@amd.com>
+Date: Tue, 3 Dec 2019 12:46:01 -0500
+Subject: [PATCH 4645/4736] drm/amd/display: Loading NV10/14 Bounding Box Data
+ Directly From Code
+
+[Why]
+NV10/14 has released. Its time to get NV10/14 bounding box
+directly from code.
+
+[How]
+Retrieve NV10/14 bounding box data directly from code.
+
+Signed-off-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index f26f79134000..2315da20fd41 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -79,8 +79,6 @@
+ 
+ #include "amdgpu_socbb.h"
+ 
+-/* NV12 SOC BB is currently in FW, mark SW bounding box invalid. */
+-#define SOC_BOUNDING_BOX_VALID false
+ #define DC_LOGGER_INIT(logger)
+ 
+ struct _vcs_dpi_ip_params_st dcn2_0_ip = {
+@@ -3277,12 +3275,13 @@ static bool init_soc_bounding_box(struct dc *dc,
+ 
+ 	DC_LOGGER_INIT(dc->ctx->logger);
+ 
+-	if (!bb && !SOC_BOUNDING_BOX_VALID) {
++	/* TODO: upstream NV12 bounding box when its launched */
++	if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
+ 		DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
+ 		return false;
+ 	}
+ 
+-	if (bb && !SOC_BOUNDING_BOX_VALID) {
++	if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
+ 		int i;
+ 
+ 		dcn2_0_nv12_soc.sr_exit_time_us =
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4646-drm-amdgpu-powerplay-unify-smu-send-message-function.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4646-drm-amdgpu-powerplay-unify-smu-send-message-function.patch
new file mode 100644
index 00000000..4d6d51f0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4646-drm-amdgpu-powerplay-unify-smu-send-message-function.patch
@@ -0,0 +1,244 @@
+From a7f8bf4e09c82148aa690d2dc58212dd7af468a9 Mon Sep 17 00:00:00 2001
+From: Likun Gao <Likun.Gao@amd.com>
+Date: Mon, 2 Dec 2019 15:04:35 +0800
+Subject: [PATCH 4646/4736] drm/amdgpu/powerplay: unify smu send message
+ function
+
+Drop smu_send_smc_msg function from ASIC specify structure.
+Reuse smu_send_smc_msg_with_param function for smu_send_smc_msg.
+Set paramer to 0 for smu_send_msg function, otherwise it will send
+with previous paramer value (Not a certain value).
+Materialize msg type for smu send message function definition.
+
+Signed-off-by: Likun Gao <Likun.Gao@amd.com>
+Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  9 ++++++
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c  |  1 -
+ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  4 +--
+ drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  5 ++--
+ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h |  5 ++--
+ drivers/gpu/drm/amd/powerplay/navi10_ppt.c    |  1 -
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c    |  1 -
+ drivers/gpu/drm/amd/powerplay/smu_internal.h  |  4 +--
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 29 ++-----------------
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c     | 28 ++----------------
+ drivers/gpu/drm/amd/powerplay/vega20_ppt.c    |  1 -
+ 11 files changed, 21 insertions(+), 67 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 42656628de90..2dd960e85a24 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -2568,3 +2568,12 @@ uint32_t smu_get_pptable_power_limit(struct smu_context *smu)
+ 
+ 	return ret;
+ }
++
++int smu_send_smc_msg(struct smu_context *smu,
++		     enum smu_message_type msg)
++{
++	int ret;
++
++	ret = smu_send_smc_msg_with_param(smu, msg, 0);
++	return ret;
++}
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index cf3c31b0524c..b87be39c9a3b 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -2137,7 +2137,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
+ 	.set_tool_table_location = smu_v11_0_set_tool_table_location,
+ 	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+ 	.system_features_control = smu_v11_0_system_features_control,
+-	.send_smc_msg = smu_v11_0_send_msg,
+ 	.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
+ 	.read_smc_arg = smu_v11_0_read_arg,
+ 	.init_display_count = smu_v11_0_init_display_count,
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+index ada4a8dc4112..ca3fdc6777cf 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+@@ -500,8 +500,8 @@ struct pptable_funcs {
+ 	int (*notify_memory_pool_location)(struct smu_context *smu);
+ 	int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
+ 	int (*system_features_control)(struct smu_context *smu, bool en);
+-	int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
+-	int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param);
++	int (*send_smc_msg_with_param)(struct smu_context *smu,
++				       enum smu_message_type msg, uint32_t param);
+ 	int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
+ 	int (*init_display_count)(struct smu_context *smu, uint32_t count);
+ 	int (*set_allowed_mask)(struct smu_context *smu);
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+index 716fcb274191..610e301a5fce 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+@@ -178,10 +178,9 @@ int smu_v11_0_notify_memory_pool_location(struct smu_context *smu);
+ int smu_v11_0_system_features_control(struct smu_context *smu,
+ 					     bool en);
+ 
+-int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg);
+-
+ int
+-smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
++smu_v11_0_send_msg_with_param(struct smu_context *smu,
++			      enum smu_message_type msg,
+ 			      uint32_t param);
+ 
+ int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg);
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+index 44c65dd8850d..922973b7e29f 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+@@ -44,10 +44,9 @@ int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg);
+ 
+ int smu_v12_0_wait_for_response(struct smu_context *smu);
+ 
+-int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg);
+-
+ int
+-smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
++smu_v12_0_send_msg_with_param(struct smu_context *smu,
++			      enum smu_message_type msg,
+ 			      uint32_t param);
+ 
+ int smu_v12_0_check_fw_status(struct smu_context *smu);
+diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+index c94c2b67c309..cd8798610ed3 100644
+--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+@@ -2082,7 +2082,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
+ 	.set_tool_table_location = smu_v11_0_set_tool_table_location,
+ 	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+ 	.system_features_control = smu_v11_0_system_features_control,
+-	.send_smc_msg = smu_v11_0_send_msg,
+ 	.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
+ 	.read_smc_arg = smu_v11_0_read_arg,
+ 	.init_display_count = smu_v11_0_init_display_count,
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index e5ff08820658..c982f69065ae 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -801,7 +801,6 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.powergate_sdma = smu_v12_0_powergate_sdma,
+ 	.powergate_vcn = smu_v12_0_powergate_vcn,
+ 	.powergate_jpeg = smu_v12_0_powergate_jpeg,
+-	.send_smc_msg = smu_v12_0_send_msg,
+ 	.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
+ 	.read_smc_arg = smu_v12_0_read_arg,
+ 	.set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+index b2d81d3490cd..60ce1fccaeb5 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
++++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
+@@ -77,8 +77,8 @@
+ #define smu_set_default_od_settings(smu, initialize) \
+ 	((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
+ 
+-#define smu_send_smc_msg(smu, msg) \
+-	((smu)->ppt_funcs->send_smc_msg? (smu)->ppt_funcs->send_smc_msg((smu), (msg)) : 0)
++int smu_send_smc_msg(struct smu_context *smu, enum smu_message_type msg);
++
+ #define smu_send_smc_msg_with_param(smu, msg, param) \
+ 	((smu)->ppt_funcs->send_smc_msg_with_param? (smu)->ppt_funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
+ #define smu_read_smc_arg(smu, arg) \
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index dd4437a9b3d0..9e405a60ee6e 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -88,36 +88,11 @@ static int smu_v11_0_wait_for_response(struct smu_context *smu)
+ 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
+ }
+ 
+-int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
+-{
+-	struct amdgpu_device *adev = smu->adev;
+-	int ret = 0, index = 0;
+-
+-	index = smu_msg_get_index(smu, msg);
+-	if (index < 0)
+-		return index;
+-
+-	smu_v11_0_wait_for_response(smu);
+-
+-	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
+-
+-	smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
+-
+-	ret = smu_v11_0_wait_for_response(smu);
+-
+-	if (ret)
+-		pr_err("failed send message: %10s (%d) response %#x\n",
+-		       smu_get_message_name(smu, msg), index, ret);
+-
+-	return ret;
+-
+-}
+-
+ int
+-smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
++smu_v11_0_send_msg_with_param(struct smu_context *smu,
++			      enum smu_message_type msg,
+ 			      uint32_t param)
+ {
+-
+ 	struct amdgpu_device *adev = smu->adev;
+ 	int ret = 0, index = 0;
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 045167311ae8..269a7d73b58d 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -77,33 +77,9 @@ int smu_v12_0_wait_for_response(struct smu_context *smu)
+ 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
+ }
+ 
+-int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
+-{
+-	struct amdgpu_device *adev = smu->adev;
+-	int ret = 0, index = 0;
+-
+-	index = smu_msg_get_index(smu, msg);
+-	if (index < 0)
+-		return index;
+-
+-	smu_v12_0_wait_for_response(smu);
+-
+-	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
+-
+-	smu_v12_0_send_msg_without_waiting(smu, (uint16_t)index);
+-
+-	ret = smu_v12_0_wait_for_response(smu);
+-
+-	if (ret)
+-		pr_err("Failed to send message 0x%x, response 0x%x\n", index,
+-		       ret);
+-
+-	return ret;
+-
+-}
+-
+ int
+-smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
++smu_v12_0_send_msg_with_param(struct smu_context *smu,
++			      enum smu_message_type msg,
+ 			      uint32_t param)
+ {
+ 	struct amdgpu_device *adev = smu->adev;
+diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+index 83862544a45c..a371a0da427e 100644
+--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+@@ -3231,7 +3231,6 @@ static const struct pptable_funcs vega20_ppt_funcs = {
+ 	.set_tool_table_location = smu_v11_0_set_tool_table_location,
+ 	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+ 	.system_features_control = smu_v11_0_system_features_control,
+-	.send_smc_msg = smu_v11_0_send_msg,
+ 	.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
+ 	.read_smc_arg = smu_v11_0_read_arg,
+ 	.init_display_count = smu_v11_0_init_display_count,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4647-Revert-Revert-drm-amdgpu-Set-GTT-size-to-be-bigger-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4647-Revert-Revert-drm-amdgpu-Set-GTT-size-to-be-bigger-t.patch
new file mode 100644
index 00000000..0a9aa27d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4647-Revert-Revert-drm-amdgpu-Set-GTT-size-to-be-bigger-t.patch
@@ -0,0 +1,39 @@
+From 148f3d0786d30aa36adf097fe450b79446946400 Mon Sep 17 00:00:00 2001
+From: Feifei Xu <Feifei.Xu@amd.com>
+Date: Thu, 5 Dec 2019 11:25:42 +0800
+Subject: [PATCH 4647/4736] Revert "Revert "drm/amdgpu: Set GTT size to be
+ bigger than 3/4 of RAM""
+
+This reverts commit 50fab61ae24facd04e5460b1b92745c893a847b5.
+
+This patch should not be cherry-picked to release branch.
+This is for kfd/rocm performance improvement.
+
+Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 9 ++++-----
+ 1 file changed, 4 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index 6d295e7ee444..d93bfaca5daf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -2156,11 +2156,10 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
+ 		struct sysinfo si;
+ 
+ 		si_meminfo(&si);
+-		gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
+-			       adev->gmc.mc_vram_size),
+-			       ((uint64_t)si.totalram * si.mem_unit * 3/4));
+-	}
+-	else
++		gtt_size = max3((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
++				adev->gmc.mc_vram_size,
++				((uint64_t)si.totalram * si.mem_unit));
++	} else
+ 		gtt_size = (uint64_t)amdgpu_gtt_size << 20;
+ 
+ 	/* reserve for DGMA import domain */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4648-drm-amdgpu-add-check-before-enabling-disabling-broad.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4648-drm-amdgpu-add-check-before-enabling-disabling-broad.patch
new file mode 100644
index 00000000..b319af72
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4648-drm-amdgpu-add-check-before-enabling-disabling-broad.patch
@@ -0,0 +1,69 @@
+From a5f7a1f05cf52af7e351d3abd10747a1d6f67f53 Mon Sep 17 00:00:00 2001
+From: Guchun Chen <guchun.chen@amd.com>
+Date: Wed, 4 Dec 2019 15:51:16 +0800
+Subject: [PATCH 4648/4736] drm/amdgpu: add check before enabling/disabling
+ broadcast mode
+
+When security violation from new vbios happens, data fabric is
+risky to stop working. So prevent the direct access to DF
+mmFabricConfigAccessControl from the new vbios and onwards.
+
+Signed-off-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 38 ++++++++++++++++------------
+ 1 file changed, 22 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+index 72bfefdbfa65..9395aa8b8fd0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
++++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+@@ -268,23 +268,29 @@ static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+ {
+ 	u32 tmp;
+ 
+-	/* Put DF on broadcast mode */
+-	adev->df_funcs->enable_broadcast_mode(adev, true);
+-
+-	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
+-		tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
+-		tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
+-		tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
+-		WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
+-	} else {
+-		tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
+-		tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
+-		tmp |= DF_V3_6_MGCG_DISABLE;
+-		WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
+-	}
++	if (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG) {
++		/* Put DF on broadcast mode */
++		adev->df_funcs->enable_broadcast_mode(adev, true);
++
++		if (enable) {
++			tmp = RREG32_SOC15(DF, 0,
++					mmDF_PIE_AON0_DfGlobalClkGater);
++			tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
++			tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
++			WREG32_SOC15(DF, 0,
++					mmDF_PIE_AON0_DfGlobalClkGater, tmp);
++		} else {
++			tmp = RREG32_SOC15(DF, 0,
++					mmDF_PIE_AON0_DfGlobalClkGater);
++			tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
++			tmp |= DF_V3_6_MGCG_DISABLE;
++			WREG32_SOC15(DF, 0,
++					mmDF_PIE_AON0_DfGlobalClkGater, tmp);
++		}
+ 
+-	/* Exit broadcast mode */
+-	adev->df_funcs->enable_broadcast_mode(adev, false);
++		/* Exit broadcast mode */
++		adev->df_funcs->enable_broadcast_mode(adev, false);
++	}
+ }
+ 
+ static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4649-drm-amdgpu-gfx-Improvement-on-EDC-GPR-workarounds.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4649-drm-amdgpu-gfx-Improvement-on-EDC-GPR-workarounds.patch
new file mode 100644
index 00000000..d4ffdffe
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4649-drm-amdgpu-gfx-Improvement-on-EDC-GPR-workarounds.patch
@@ -0,0 +1,150 @@
+From 245b79e8a454c5cead7d7624b3824fbb6eb00b0f Mon Sep 17 00:00:00 2001
+From: James Zhu <James.Zhu@amd.com>
+Date: Tue, 3 Dec 2019 15:40:10 -0500
+Subject: [PATCH 4649/4736] drm/amdgpu/gfx: Improvement on EDC GPR workarounds
+
+SPI limits total CS waves in flight per SE to no more than 32 * num_cu and
+we need to stuff 40 waves on a CU to completely clean the SGPR. This is
+accomplished in the WR by cleaning the SE in two steps, half of the CU per
+step.
+
+Signed-off-by: James Zhu <James.Zhu@amd.com>
+Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 83 ++++++++++++++++++++-------
+ 1 file changed, 63 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index e644d5ea56b9..994b634c6355 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -3941,24 +3941,37 @@ static const struct soc15_reg_entry vgpr_init_regs[] = {
+    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
+    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
+    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
+-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x1000000 }, /* CU_GROUP_COUNT=1 */
+-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 256*2 },
+-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 1 },
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 },
+    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
+-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x100007f }, /* VGPRS=15 (256 logical VGPRs, SGPRS=1 (16 SGPRs, BULKY=1 */
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f },
+    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 },  /* 64KB LDS */
+ };
+ 
+-static const struct soc15_reg_entry sgpr_init_regs[] = {
+-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
+-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
+-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
+-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
+-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x1000000 }, /* CU_GROUP_COUNT=1 */
+-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 256*2 },
+-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 1 },
++static const struct soc15_reg_entry sgpr1_init_regs[] = {
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x000000ff },
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x000000ff },
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x000000ff },
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x000000ff },
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
++};
++
++static const struct soc15_reg_entry sgpr2_init_regs[] = {
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x0000ff00 },
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x0000ff00 },
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x0000ff00 },
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x0000ff00 },
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
+    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
+-   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x340 }, /* SGPRS=13 (112 GPRS) */
++   { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
+    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
+ };
+ 
+@@ -4068,7 +4081,9 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
+ 	total_size =
+ 		((ARRAY_SIZE(vgpr_init_regs) * 3) + 4 + 5 + 2) * 4;
+ 	total_size +=
+-		((ARRAY_SIZE(sgpr_init_regs) * 3) + 4 + 5 + 2) * 4;
++		((ARRAY_SIZE(sgpr1_init_regs) * 3) + 4 + 5 + 2) * 4;
++	total_size +=
++		((ARRAY_SIZE(sgpr2_init_regs) * 3) + 4 + 5 + 2) * 4;
+ 	total_size = ALIGN(total_size, 256);
+ 	vgpr_offset = total_size;
+ 	total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
+@@ -4111,7 +4126,35 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
+ 
+ 	/* write dispatch packet */
+ 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
+-	ib.ptr[ib.length_dw++] = 256; /* x */
++	ib.ptr[ib.length_dw++] = 0x40*2; /* x */
++	ib.ptr[ib.length_dw++] = 1; /* y */
++	ib.ptr[ib.length_dw++] = 1; /* z */
++	ib.ptr[ib.length_dw++] =
++		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
++
++	/* write CS partial flush packet */
++	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
++	ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
++
++	/* SGPR1 */
++	/* write the register state for the compute dispatch */
++	for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i++) {
++		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
++		ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i])
++								- PACKET3_SET_SH_REG_START;
++		ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value;
++	}
++	/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
++	gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
++	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
++	ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
++							- PACKET3_SET_SH_REG_START;
++	ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
++	ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
++
++	/* write dispatch packet */
++	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
++	ib.ptr[ib.length_dw++] = 0xA0*2; /* x */
+ 	ib.ptr[ib.length_dw++] = 1; /* y */
+ 	ib.ptr[ib.length_dw++] = 1; /* z */
+ 	ib.ptr[ib.length_dw++] =
+@@ -4121,13 +4164,13 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
+ 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
+ 	ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
+ 
+-	/* SGPR */
++	/* SGPR2 */
+ 	/* write the register state for the compute dispatch */
+-	for (i = 0; i < ARRAY_SIZE(sgpr_init_regs); i++) {
++	for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i++) {
+ 		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
+-		ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr_init_regs[i])
++		ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i])
+ 								- PACKET3_SET_SH_REG_START;
+-		ib.ptr[ib.length_dw++] = sgpr_init_regs[i].reg_value;
++		ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value;
+ 	}
+ 	/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
+ 	gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
+@@ -4139,7 +4182,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
+ 
+ 	/* write dispatch packet */
+ 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
+-	ib.ptr[ib.length_dw++] = 256; /* x */
++	ib.ptr[ib.length_dw++] = 0xA0*2; /* x */
+ 	ib.ptr[ib.length_dw++] = 1; /* y */
+ 	ib.ptr[ib.length_dw++] = 1; /* z */
+ 	ib.ptr[ib.length_dw++] =
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4650-drm-amdgpu-add-header-line-for-power-profile-on-Arct.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4650-drm-amdgpu-add-header-line-for-power-profile-on-Arct.patch
new file mode 100644
index 00000000..e40cd8a6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4650-drm-amdgpu-add-header-line-for-power-profile-on-Arct.patch
@@ -0,0 +1,39 @@
+From fb3ec24db056b9f2e4e37fea32d86351cb58f38f Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 4 Dec 2019 22:07:49 -0500
+Subject: [PATCH 4650/4736] drm/amdgpu: add header line for power profile on
+ Arcturus
+
+So the output is consistent with other asics.
+
+Reviewed-by: Evan Quan <evan.quan@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index b87be39c9a3b..3a793c6ccbf0 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -1320,12 +1320,17 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu,
+ 					"VR",
+ 					"COMPUTE",
+ 					"CUSTOM"};
++	static const char *title[] = {
++			"PROFILE_INDEX(NAME)"};
+ 	uint32_t i, size = 0;
+ 	int16_t workload_type = 0;
+ 
+ 	if (!smu->pm_enabled || !buf)
+ 		return -EINVAL;
+ 
++	size += sprintf(buf + size, "%16s\n",
++			title[0]);
++
+ 	for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
+ 		/*
+ 		 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4651-drm-amdgpu-display-fix-the-build-when-CONFIG_DRM_AMD.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4651-drm-amdgpu-display-fix-the-build-when-CONFIG_DRM_AMD.patch
new file mode 100644
index 00000000..9351479b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4651-drm-amdgpu-display-fix-the-build-when-CONFIG_DRM_AMD.patch
@@ -0,0 +1,57 @@
+From 26f647b03728c7a2593dad12b4767439c2b37bee Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 6 Nov 2019 20:51:14 -0500
+Subject: [PATCH 4651/4736] drm/amdgpu/display: fix the build when
+ CONFIG_DRM_AMD_DC_DCN is not set
+
+Need to protect some DSC functions.
+
+Change-Id: Ic67640caab59ec8252837f7b7fceb2a06262d728
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 841f0bfd1e4f..f98ff5f012d2 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -3993,7 +3993,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ 	bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
+ 	int mode_refresh;
+ 	int preferred_refresh = 0;
++#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ 	struct dsc_dec_dpcd_caps dsc_caps;
++#endif
+ 	uint32_t link_bandwidth_kbps;
+ 
+ 	struct dc_sink *sink = NULL;
+@@ -4071,12 +4073,15 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ 	stream->timing.flags.DSC = 0;
+ 
+ 	if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
++#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ 		dc_dsc_parse_dsc_dpcd(aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
+ 				      aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
+ 				      &dsc_caps);
++#endif
+ 		link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
+ 							     dc_link_get_link_cap(aconnector->dc_link));
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ 		if (dsc_caps.is_dsc_supported)
+ 			if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
+ 						  &dsc_caps,
+@@ -4085,6 +4090,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
+ 						  &stream->timing,
+ 						  &stream->timing.dsc_cfg))
+ 				stream->timing.flags.DSC = 1;
++#endif
+ 	}
+ 
+ 	update_stream_scaling_settings(&mode, dm_state, stream);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4652-drm-amdgpu-display-fix-warning-when-CONFIG_DRM_AMD_D.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4652-drm-amdgpu-display-fix-warning-when-CONFIG_DRM_AMD_D.patch
new file mode 100644
index 00000000..ba93b635
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4652-drm-amdgpu-display-fix-warning-when-CONFIG_DRM_AMD_D.patch
@@ -0,0 +1,39 @@
+From f061100ad969742aef328f4d1bbcac87d664ba06 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 8 Nov 2019 11:22:57 -0500
+Subject: [PATCH 4652/4736] drm/amdgpu/display: fix warning when
+ CONFIG_DRM_AMD_DC_DCN is not set
+
+dm_dcn_crtc_high_irq() is only used when CONFIG_DRM_AMD_DC_DCN is set.
+
+Change-Id: I0a986136adc5fde5e6636de458580fc6080a1b9d
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index f98ff5f012d2..bc76d49187fd 100755
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -484,7 +484,7 @@ static void dm_crtc_high_irq(void *interrupt_params)
+ 	}
+ }
+ 
+-
++#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ /**
+  * dm_dcn_crtc_high_irq() - Handles VStartup interrupt for DCN generation ASICs
+  * @interrupt params - interrupt parameters
+@@ -546,6 +546,7 @@ static void dm_dcn_crtc_high_irq(void *interrupt_params)
+ 
+ 	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
+ }
++#endif
+ 
+ static int dm_set_clockgating_state(void *handle,
+ 		  enum amd_clockgating_state state)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4653-drm-amd-display-cleanup-of-function-pointer-tables.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4653-drm-amd-display-cleanup-of-function-pointer-tables.patch
new file mode 100644
index 00000000..a45f630b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4653-drm-amd-display-cleanup-of-function-pointer-tables.patch
@@ -0,0 +1,3251 @@
+From 30f07444549b52d8d00c4b540cfce280e0943d26 Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Tue, 29 Oct 2019 15:05:56 -0400
+Subject: [PATCH 4653/4736] drm/amd/display: cleanup of function pointer tables
+
+[Why]
+It is becoming increasingly hard to figure out which
+function is called on the different DCN versions
+
+[How]
+1. Make function pointer table init in its own init.c file
+2. Remove other scenarios in hwseq.c file that need to
+include headers of other DCN versions. (If needed,
+it should have been done via the function pointers)
+
+Change-Id: I09ca21dfd5848cc7e678dbefef8df201947df7d3
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ .../gpu/drm/amd/display/dc/basics/Makefile    |   2 +-
+ .../gpu/drm/amd/display/dc/basics/dc_common.c | 101 ++++
+ .../gpu/drm/amd/display/dc/basics/dc_common.h |  42 ++
+ drivers/gpu/drm/amd/display/dc/core/dc.c      |   4 +-
+ .../gpu/drm/amd/display/dc/core/dc_stream.c   |   3 +-
+ .../display/dc/dce110/dce110_hw_sequencer.c   |  12 +-
+ .../display/dc/dce110/dce110_hw_sequencer.h   |   1 -
+ drivers/gpu/drm/amd/display/dc/dcn10/Makefile |   3 +-
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 436 +++++-------------
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 181 ++++++--
+ .../dc/dcn10/dcn10_hw_sequencer_debug.h       |  43 ++
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c | 105 +++++
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_init.h |  33 ++
+ .../drm/amd/display/dc/dcn10/dcn10_resource.c |   2 +
+ drivers/gpu/drm/amd/display/dc/dcn20/Makefile |   2 +-
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 428 +++++++----------
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.h    | 152 +++---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c | 131 ++++++
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_init.h |  33 ++
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c |  12 +-
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |   2 +-
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c |   4 +-
+ drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   3 +-
+ .../drm/amd/display/dc/dcn21/dcn21_hwseq.c    |  13 +-
+ .../drm/amd/display/dc/dcn21/dcn21_hwseq.h    |  14 +-
+ .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c | 135 ++++++
+ .../gpu/drm/amd/display/dc/dcn21/dcn21_init.h |  33 ++
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c |   2 +
+ .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  40 +-
+ 29 files changed, 1256 insertions(+), 716 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/basics/dc_common.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/basics/dc_common.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/basics/Makefile b/drivers/gpu/drm/amd/display/dc/basics/Makefile
+index a50a76471107..7ad0cad0f4ef 100644
+--- a/drivers/gpu/drm/amd/display/dc/basics/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/basics/Makefile
+@@ -25,7 +25,7 @@
+ # subcomponents.
+ 
+ BASICS = conversion.o fixpt31_32.o \
+-	log_helpers.o vector.o
++	log_helpers.o vector.o dc_common.o
+ 
+ AMD_DAL_BASICS = $(addprefix $(AMDDALPATH)/dc/basics/,$(BASICS))
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/basics/dc_common.c b/drivers/gpu/drm/amd/display/dc/basics/dc_common.c
+new file mode 100644
+index 000000000000..b2fc4f8e6482
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/basics/dc_common.c
+@@ -0,0 +1,101 @@
++/*
++ * Copyright 2012-15 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "core_types.h"
++#include "dc_common.h"
++#include "basics/conversion.h"
++
++bool is_rgb_cspace(enum dc_color_space output_color_space)
++{
++	switch (output_color_space) {
++	case COLOR_SPACE_SRGB:
++	case COLOR_SPACE_SRGB_LIMITED:
++	case COLOR_SPACE_2020_RGB_FULLRANGE:
++	case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
++	case COLOR_SPACE_ADOBERGB:
++		return true;
++	case COLOR_SPACE_YCBCR601:
++	case COLOR_SPACE_YCBCR709:
++	case COLOR_SPACE_YCBCR601_LIMITED:
++	case COLOR_SPACE_YCBCR709_LIMITED:
++	case COLOR_SPACE_2020_YCBCR:
++		return false;
++	default:
++		/* Add a case to switch */
++		BREAK_TO_DEBUGGER();
++		return false;
++	}
++}
++
++bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
++{
++	if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
++		return true;
++	if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
++		return true;
++	return false;
++}
++
++bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
++{
++	if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
++		return true;
++	if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
++		return true;
++	return false;
++}
++
++bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
++{
++	if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
++		return true;
++	if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
++		return true;
++	if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
++		return true;
++	return false;
++}
++
++void build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
++		const struct dc_plane_state *plane_state)
++{
++	if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
++			&& plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
++			&& plane_state->input_csc_color_matrix.enable_adjustment
++			&& plane_state->coeff_reduction_factor.value != 0) {
++		bias_and_scale->scale_blue = fixed_point_to_int_frac(
++			dc_fixpt_mul(plane_state->coeff_reduction_factor,
++					dc_fixpt_from_fraction(256, 255)),
++				2,
++				13);
++		bias_and_scale->scale_red = bias_and_scale->scale_blue;
++		bias_and_scale->scale_green = bias_and_scale->scale_blue;
++	} else {
++		bias_and_scale->scale_blue = 0x2000;
++		bias_and_scale->scale_red = 0x2000;
++		bias_and_scale->scale_green = 0x2000;
++	}
++}
++
+diff --git a/drivers/gpu/drm/amd/display/dc/basics/dc_common.h b/drivers/gpu/drm/amd/display/dc/basics/dc_common.h
+new file mode 100644
+index 000000000000..7c0cbf47e8ce
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/basics/dc_common.h
+@@ -0,0 +1,42 @@
++/*
++ * Copyright 2012-15 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DAL_DC_COMMON_H__
++#define __DAL_DC_COMMON_H__
++
++#include "core_types.h"
++
++bool is_rgb_cspace(enum dc_color_space output_color_space);
++
++bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
++
++bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
++
++bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
++
++void build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
++		const struct dc_plane_state *plane_state);
++
++#endif
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 121465bf223f..562a24f4553f 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1968,11 +1968,11 @@ static void commit_planes_do_stream_update(struct dc *dc,
+ 
+ 			if (stream_update->periodic_interrupt0 &&
+ 					dc->hwss.setup_periodic_interrupt)
+-				dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE0);
++				dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE0);
+ 
+ 			if (stream_update->periodic_interrupt1 &&
+ 					dc->hwss.setup_periodic_interrupt)
+-				dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE1);
++				dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE1);
+ 
+ 			if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
+ 					stream_update->vrr_infopacket ||
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+index 59eaa5c172a9..9029786c7b08 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+@@ -24,6 +24,7 @@
+  */
+ 
+ #include "dm_services.h"
++#include "basics/dc_common.h"
+ #include "dc.h"
+ #include "core_types.h"
+ #include "resource.h"
+@@ -241,7 +242,7 @@ static void delay_cursor_until_vupdate(struct pipe_ctx *pipe_ctx, struct dc *dc)
+ 	if (stream->ctx->asic_id.chip_family == FAMILY_RV &&
+ 			ASICREV_IS_RAVEN(stream->ctx->asic_id.hw_internal_rev)) {
+ 
+-		vupdate_line = get_vupdate_offset_from_vsync(pipe_ctx);
++		vupdate_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
+ 		if (!dc_stream_get_crtc_position(dc, &stream, 1, &vpos, &nvpos))
+ 			return;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 01fefe19ee92..6291f803cd16 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -58,6 +58,8 @@
+ 
+ #include "atomfirmware.h"
+ 
++#define GAMMA_HW_POINTS_NUM 256
++
+ /*
+  * All values are in milliseconds;
+  * For eDP, after power-up/power/down,
+@@ -265,7 +267,7 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params,
+ }
+ 
+ static bool
+-dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
++dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
+ 			       const struct dc_plane_state *plane_state)
+ {
+ 	struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
+@@ -593,7 +595,7 @@ dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
+ }
+ 
+ static bool
+-dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
++dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
+ 				const struct dc_stream_state *stream)
+ {
+ 	struct transform *xfm = pipe_ctx->plane_res.xfm;
+@@ -1355,7 +1357,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ 		dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
+ 
+ 	if (dc->hwss.setup_vupdate_interrupt)
+-		dc->hwss.setup_vupdate_interrupt(pipe_ctx);
++		dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
+ 
+ 	params.vertical_total_min = stream->adjust.v_total_min;
+ 	params.vertical_total_max = stream->adjust.v_total_max;
+@@ -2498,10 +2500,10 @@ static void dce110_program_front_end_for_pipe(
+ 	if (pipe_ctx->plane_state->update_flags.bits.full_update ||
+ 			pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
+ 			pipe_ctx->plane_state->update_flags.bits.gamma_change)
+-		dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
++		dc->hwss.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
+ 
+ 	if (pipe_ctx->plane_state->update_flags.bits.full_update)
+-		dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
++		dc->hwss.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
+ 
+ 	DC_LOG_SURFACE(
+ 			"Pipe:%d %p: addr hi:0x%x, "
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+index 2f9b7dbdf415..c639e1680b7b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+@@ -28,7 +28,6 @@
+ 
+ #include "core_types.h"
+ 
+-#define GAMMA_HW_POINTS_NUM 256
+ struct dc;
+ struct dc_state;
+ struct dm_pp_display_configuration;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
+index 032f872be89c..62ad1a11bff9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
+@@ -22,7 +22,8 @@
+ #
+ # Makefile for DCN.
+ 
+-DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o dcn10_hw_sequencer_debug.o \
++DCN10 = dcn10_init.o dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
++		dcn10_hw_sequencer_debug.o \
+ 		dcn10_dpp.o dcn10_opp.o dcn10_optc.o \
+ 		dcn10_hubp.o dcn10_mpc.o \
+ 		dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index df59bd9185b5..08d15982f526 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -24,17 +24,18 @@
+  */
+ 
+ #include "dm_services.h"
++#include "basics/dc_common.h"
+ #include "core_types.h"
+ #include "resource.h"
+ #include "custom_float.h"
+ #include "dcn10_hw_sequencer.h"
+-#include "dce110/dce110_hw_sequencer.h"
++#include "dcn10_hw_sequencer_debug.h"
+ #include "dce/dce_hwseq.h"
+ #include "abm.h"
+ #include "dmcu.h"
+ #include "dcn10_optc.h"
+-#include "dcn10/dcn10_dpp.h"
+-#include "dcn10/dcn10_mpc.h"
++#include "dcn10_dpp.h"
++#include "dcn10_mpc.h"
+ #include "timing_generator.h"
+ #include "opp.h"
+ #include "ipp.h"
+@@ -65,6 +66,8 @@
+ #define DTN_INFO_MICRO_SEC(ref_cycle) \
+ 	print_microsec(dc_ctx, log_ctx, ref_cycle)
+ 
++#define GAMMA_HW_POINTS_NUM 256
++
+ void print_microsec(struct dc_context *dc_ctx,
+ 	struct dc_log_buffer_ctx *log_ctx,
+ 	uint32_t ref_cycle)
+@@ -78,6 +81,33 @@ void print_microsec(struct dc_context *dc_ctx,
+ 			us_x10 % frac);
+ }
+ 
++static void dcn10_lock_all_pipes(struct dc *dc,
++	struct dc_state *context,
++	bool lock)
++{
++	struct pipe_ctx *pipe_ctx;
++	struct timing_generator *tg;
++	int i;
++
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
++		pipe_ctx = &context->res_ctx.pipe_ctx[i];
++		tg = pipe_ctx->stream_res.tg;
++		/*
++		 * Only lock the top pipe's tg to prevent redundant
++		 * (un)locking. Also skip if pipe is disabled.
++		 */
++		if (pipe_ctx->top_pipe ||
++		    !pipe_ctx->stream || !pipe_ctx->plane_state ||
++		    !tg->funcs->is_tg_enabled(tg))
++			continue;
++
++		if (lock)
++			tg->funcs->lock(tg);
++		else
++			tg->funcs->unlock(tg);
++	}
++}
++
+ static void log_mpc_crc(struct dc *dc,
+ 	struct dc_log_buffer_ctx *log_ctx)
+ {
+@@ -444,7 +474,7 @@ bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	return false;
+ }
+ 
+-static void dcn10_enable_power_gating_plane(
++void dcn10_enable_power_gating_plane(
+ 	struct dce_hwseq *hws,
+ 	bool enable)
+ {
+@@ -466,7 +496,7 @@ static void dcn10_enable_power_gating_plane(
+ 	REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
+ }
+ 
+-static void dcn10_disable_vga(
++void dcn10_disable_vga(
+ 	struct dce_hwseq *hws)
+ {
+ 	unsigned int in_vga1_mode = 0;
+@@ -499,7 +529,7 @@ static void dcn10_disable_vga(
+ 	REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
+ }
+ 
+-static void dcn10_dpp_pg_control(
++void dcn10_dpp_pg_control(
+ 		struct dce_hwseq *hws,
+ 		unsigned int dpp_inst,
+ 		bool power_on)
+@@ -551,7 +581,7 @@ static void dcn10_dpp_pg_control(
+ 	}
+ }
+ 
+-static void dcn10_hubp_pg_control(
++void dcn10_hubp_pg_control(
+ 		struct dce_hwseq *hws,
+ 		unsigned int hubp_inst,
+ 		bool power_on)
+@@ -670,7 +700,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc)
+ 	hws->wa_state.DEGVIDCN10_253_applied = true;
+ }
+ 
+-static void dcn10_bios_golden_init(struct dc *dc)
++void dcn10_bios_golden_init(struct dc *dc)
+ {
+ 	struct dc_bios *bp = dc->ctx->dc_bios;
+ 	int i;
+@@ -738,7 +768,7 @@ static void false_optc_underflow_wa(
+ 		tg->funcs->clear_optc_underflow(tg);
+ }
+ 
+-static enum dc_status dcn10_enable_stream_timing(
++enum dc_status dcn10_enable_stream_timing(
+ 		struct pipe_ctx *pipe_ctx,
+ 		struct dc_state *context,
+ 		struct dc *dc)
+@@ -984,7 +1014,7 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc)
+ }
+ 
+ /* trigger HW to start disconnect plane from stream on the next vsync */
+-void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ 	int dpp_id = pipe_ctx->plane_res.dpp->inst;
+@@ -1010,10 +1040,10 @@ void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 		hubp->funcs->hubp_disconnect(hubp);
+ 
+ 	if (dc->debug.sanity_checks)
+-		dcn10_verify_allow_pstate_change_high(dc);
++		dc->hwss.verify_allow_pstate_change_high(dc);
+ }
+ 
+-static void dcn10_plane_atomic_power_down(struct dc *dc,
++void dcn10_plane_atomic_power_down(struct dc *dc,
+ 		struct dpp *dpp,
+ 		struct hubp *hubp)
+ {
+@@ -1036,7 +1066,7 @@ static void dcn10_plane_atomic_power_down(struct dc *dc,
+ /* disable HW used by plane.
+  * note:  cannot disable until disconnect is complete
+  */
+-static void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
+@@ -1068,7 +1098,7 @@ static void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	pipe_ctx->plane_state = NULL;
+ }
+ 
+-static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	DC_LOGGER_INIT(dc->ctx->logger);
+ 
+@@ -1083,7 +1113,7 @@ static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 					pipe_ctx->pipe_idx);
+ }
+ 
+-static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
++void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
+ {
+ 	int i;
+ 	bool can_apply_seamless_boot = false;
+@@ -1182,7 +1212,7 @@ static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
+ 	}
+ }
+ 
+-static void dcn10_init_hw(struct dc *dc)
++void dcn10_init_hw(struct dc *dc)
+ {
+ 	int i;
+ 	struct abm *abm = dc->res_pool->abm;
+@@ -1314,7 +1344,7 @@ static void dcn10_init_hw(struct dc *dc)
+ 
+ }
+ 
+-static void dcn10_reset_hw_ctx_wrap(
++void dcn10_reset_hw_ctx_wrap(
+ 		struct dc *dc,
+ 		struct dc_state *context)
+ {
+@@ -1371,9 +1401,7 @@ static bool patch_address_for_sbs_tb_stereo(
+ 	return false;
+ }
+ 
+-
+-
+-static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	bool addr_patched = false;
+ 	PHYSICAL_ADDRESS_LOC addr;
+@@ -1398,8 +1426,8 @@ static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_c
+ 		pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
+ }
+ 
+-static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
+-					  const struct dc_plane_state *plane_state)
++bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
++			const struct dc_plane_state *plane_state)
+ {
+ 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
+ 	const struct dc_transfer_func *tf = NULL;
+@@ -1475,9 +1503,8 @@ static void log_tf(struct dc_context *ctx,
+ 	}
+ }
+ 
+-static bool
+-dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
+-			       const struct dc_stream_state *stream)
++bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
++				const struct dc_stream_state *stream)
+ {
+ 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
+ 
+@@ -1513,7 +1540,7 @@ dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
+ 	return true;
+ }
+ 
+-static void dcn10_pipe_control_lock(
++void dcn10_pipe_control_lock(
+ 	struct dc *dc,
+ 	struct pipe_ctx *pipe,
+ 	bool lock)
+@@ -1525,7 +1552,7 @@ static void dcn10_pipe_control_lock(
+ 		return;
+ 
+ 	if (dc->debug.sanity_checks)
+-		dcn10_verify_allow_pstate_change_high(dc);
++		dc->hwss.verify_allow_pstate_change_high(dc);
+ 
+ 	if (lock)
+ 		pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
+@@ -1533,7 +1560,7 @@ static void dcn10_pipe_control_lock(
+ 		pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
+ 
+ 	if (dc->debug.sanity_checks)
+-		dcn10_verify_allow_pstate_change_high(dc);
++		dc->hwss.verify_allow_pstate_change_high(dc);
+ }
+ 
+ static bool wait_for_reset_trigger_to_occur(
+@@ -1573,7 +1600,7 @@ static bool wait_for_reset_trigger_to_occur(
+ 	return rc;
+ }
+ 
+-static void dcn10_enable_timing_synchronization(
++void dcn10_enable_timing_synchronization(
+ 	struct dc *dc,
+ 	int group_index,
+ 	int group_size,
+@@ -1603,7 +1630,7 @@ static void dcn10_enable_timing_synchronization(
+ 	DC_SYNC_INFO("Sync complete\n");
+ }
+ 
+-static void dcn10_enable_per_frame_crtc_position_reset(
++void dcn10_enable_per_frame_crtc_position_reset(
+ 	struct dc *dc,
+ 	int group_size,
+ 	struct pipe_ctx *grouped_pipes[])
+@@ -1841,7 +1868,7 @@ static void dcn10_enable_plane(
+ 	struct dce_hwseq *hws = dc->hwseq;
+ 
+ 	if (dc->debug.sanity_checks) {
+-		dcn10_verify_allow_pstate_change_high(dc);
++		dc->hwss.verify_allow_pstate_change_high(dc);
+ 	}
+ 
+ 	undo_DEGVIDCN10_253_wa(dc);
+@@ -1898,11 +1925,11 @@ static void dcn10_enable_plane(
+ 		dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
+ 
+ 	if (dc->debug.sanity_checks) {
+-		dcn10_verify_allow_pstate_change_high(dc);
++		dc->hwss.verify_allow_pstate_change_high(dc);
+ 	}
+ }
+ 
+-static void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)
++void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)
+ {
+ 	int i = 0;
+ 	struct dpp_grph_csc_adjustment adjust;
+@@ -1950,7 +1977,7 @@ static void dcn10_set_csc_adjustment_rgb_mpo_fix(struct pipe_ctx *pipe_ctx, uint
+ 	matrix[11] = rgb_bias;
+ }
+ 
+-static void dcn10_program_output_csc(struct dc *dc,
++void dcn10_program_output_csc(struct dc *dc,
+ 		struct pipe_ctx *pipe_ctx,
+ 		enum dc_color_space colorspace,
+ 		uint16_t *matrix,
+@@ -1982,57 +2009,6 @@ static void dcn10_program_output_csc(struct dc *dc,
+ 	}
+ }
+ 
+-bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
+-{
+-	if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
+-		return true;
+-	if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
+-		return true;
+-	return false;
+-}
+-
+-bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
+-{
+-	if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
+-		return true;
+-	if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
+-		return true;
+-	return false;
+-}
+-
+-bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
+-{
+-	if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
+-		return true;
+-	if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
+-		return true;
+-	if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
+-		return true;
+-	return false;
+-}
+-
+-bool is_rgb_cspace(enum dc_color_space output_color_space)
+-{
+-	switch (output_color_space) {
+-	case COLOR_SPACE_SRGB:
+-	case COLOR_SPACE_SRGB_LIMITED:
+-	case COLOR_SPACE_2020_RGB_FULLRANGE:
+-	case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
+-	case COLOR_SPACE_ADOBERGB:
+-		return true;
+-	case COLOR_SPACE_YCBCR601:
+-	case COLOR_SPACE_YCBCR709:
+-	case COLOR_SPACE_YCBCR601_LIMITED:
+-	case COLOR_SPACE_YCBCR709_LIMITED:
+-	case COLOR_SPACE_2020_YCBCR:
+-		return false;
+-	default:
+-		/* Add a case to switch */
+-		BREAK_TO_DEBUGGER();
+-		return false;
+-	}
+-}
+-
+ void dcn10_get_surface_visual_confirm_color(
+ 		const struct pipe_ctx *pipe_ctx,
+ 		struct tg_color *color)
+@@ -2106,70 +2082,7 @@ void dcn10_get_hdr_visual_confirm_color(
+ 	}
+ }
+ 
+-static uint16_t fixed_point_to_int_frac(
+-	struct fixed31_32 arg,
+-	uint8_t integer_bits,
+-	uint8_t fractional_bits)
+-{
+-	int32_t numerator;
+-	int32_t divisor = 1 << fractional_bits;
+-
+-	uint16_t result;
+-
+-	uint16_t d = (uint16_t)dc_fixpt_floor(
+-		dc_fixpt_abs(
+-			arg));
+-
+-	if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
+-		numerator = (uint16_t)dc_fixpt_floor(
+-			dc_fixpt_mul_int(
+-				arg,
+-				divisor));
+-	else {
+-		numerator = dc_fixpt_floor(
+-			dc_fixpt_sub(
+-				dc_fixpt_from_int(
+-					1LL << integer_bits),
+-				dc_fixpt_recip(
+-					dc_fixpt_from_int(
+-						divisor))));
+-	}
+-
+-	if (numerator >= 0)
+-		result = (uint16_t)numerator;
+-	else
+-		result = (uint16_t)(
+-		(1 << (integer_bits + fractional_bits + 1)) + numerator);
+-
+-	if ((result != 0) && dc_fixpt_lt(
+-		arg, dc_fixpt_zero))
+-		result |= 1 << (integer_bits + fractional_bits);
+-
+-	return result;
+-}
+-
+-void dcn10_build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
+-		const struct dc_plane_state *plane_state)
+-{
+-	if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
+-			&& plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
+-			&& plane_state->input_csc_color_matrix.enable_adjustment
+-			&& plane_state->coeff_reduction_factor.value != 0) {
+-		bias_and_scale->scale_blue = fixed_point_to_int_frac(
+-			dc_fixpt_mul(plane_state->coeff_reduction_factor,
+-					dc_fixpt_from_fraction(256, 255)),
+-				2,
+-				13);
+-		bias_and_scale->scale_red = bias_and_scale->scale_blue;
+-		bias_and_scale->scale_green = bias_and_scale->scale_blue;
+-	} else {
+-		bias_and_scale->scale_blue = 0x2000;
+-		bias_and_scale->scale_red = 0x2000;
+-		bias_and_scale->scale_green = 0x2000;
+-	}
+-}
+-
+-static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
++static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
+ {
+ 	struct dc_bias_and_scale bns_params = {0};
+ 
+@@ -2182,12 +2095,12 @@ static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
+ 			NULL);
+ 
+ 	//set scale and bias registers
+-	dcn10_build_prescale_params(&bns_params, plane_state);
++	build_prescale_params(&bns_params, plane_state);
+ 	if (dpp->funcs->dpp_program_bias_and_scale)
+ 		dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
+ }
+ 
+-static void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ 	struct mpcc_blnd_cfg blnd_cfg = {{0}};
+@@ -2198,10 +2111,10 @@ static void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
+ 
+ 	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
+-		dcn10_get_hdr_visual_confirm_color(
++		dc->hwss.get_hdr_visual_confirm_color(
+ 				pipe_ctx, &blnd_cfg.black_color);
+ 	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
+-		dcn10_get_surface_visual_confirm_color(
++		dc->hwss.get_surface_visual_confirm_color(
+ 				pipe_ctx, &blnd_cfg.black_color);
+ 	} else {
+ 		color_space_to_black_color(
+@@ -2283,7 +2196,7 @@ static void update_scaler(struct pipe_ctx *pipe_ctx)
+ 			pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
+ }
+ 
+-void update_dchubp_dpp(
++static void dcn10_update_dchubp_dpp(
+ 	struct dc *dc,
+ 	struct pipe_ctx *pipe_ctx,
+ 	struct dc_state *context)
+@@ -2341,7 +2254,7 @@ void update_dchubp_dpp(
+ 
+ 	if (plane_state->update_flags.bits.full_update ||
+ 		plane_state->update_flags.bits.bpp_change)
+-		update_dpp(dpp, plane_state);
++		dcn10_update_dpp(dpp, plane_state);
+ 
+ 	if (plane_state->update_flags.bits.full_update ||
+ 		plane_state->update_flags.bits.per_pixel_alpha_change ||
+@@ -2412,7 +2325,7 @@ void update_dchubp_dpp(
+ 		hubp->funcs->set_blank(hubp, false);
+ }
+ 
+-static void dcn10_blank_pixel_data(
++void dcn10_blank_pixel_data(
+ 		struct dc *dc,
+ 		struct pipe_ctx *pipe_ctx,
+ 		bool blank)
+@@ -2455,7 +2368,7 @@ static void dcn10_blank_pixel_data(
+ 	}
+ }
+ 
+-void set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
++void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
+ {
+ 	struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult;
+ 	uint32_t hw_mult = 0x1f000; // 1.0 default multiplier
+@@ -2485,14 +2398,14 @@ void dcn10_program_pipe(
+ 	if (pipe_ctx->plane_state->update_flags.bits.full_update)
+ 		dcn10_enable_plane(dc, pipe_ctx, context);
+ 
+-	update_dchubp_dpp(dc, pipe_ctx, context);
++	dcn10_update_dchubp_dpp(dc, pipe_ctx, context);
+ 
+-	set_hdr_multiplier(pipe_ctx);
++	dc->hwss.set_hdr_multiplier(pipe_ctx);
+ 
+ 	if (pipe_ctx->plane_state->update_flags.bits.full_update ||
+ 			pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
+ 			pipe_ctx->plane_state->update_flags.bits.gamma_change)
+-		dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
++		dc->hwss.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
+ 
+ 	/* dcn10_translate_regamma_to_hw_format takes 750us to finish
+ 	 * only do gamma programming for full update.
+@@ -2501,10 +2414,10 @@ void dcn10_program_pipe(
+ 	 * doing heavy calculation and programming
+ 	 */
+ 	if (pipe_ctx->plane_state->update_flags.bits.full_update)
+-		dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
++		dc->hwss.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
+ }
+ 
+-static void program_all_pipe_in_tree(
++static void dcn10_program_all_pipe_in_tree(
+ 		struct dc *dc,
+ 		struct pipe_ctx *pipe_ctx,
+ 		struct dc_state *context)
+@@ -2523,19 +2436,19 @@ static void program_all_pipe_in_tree(
+ 				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+ 
+ 		if (dc->hwss.setup_vupdate_interrupt)
+-			dc->hwss.setup_vupdate_interrupt(pipe_ctx);
++			dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
+ 
+ 		dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
+ 	}
+ 
+ 	if (pipe_ctx->plane_state != NULL)
+-		dcn10_program_pipe(dc, pipe_ctx, context);
++		dc->hwss.program_pipe(dc, pipe_ctx, context);
+ 
+ 	if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
+-		program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
++		dcn10_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
+ }
+ 
+-struct pipe_ctx *find_top_pipe_for_stream(
++static struct pipe_ctx *dcn10_find_top_pipe_for_stream(
+ 		struct dc *dc,
+ 		struct dc_state *context,
+ 		const struct dc_stream_state *stream)
+@@ -2559,7 +2472,7 @@ struct pipe_ctx *find_top_pipe_for_stream(
+ 	return NULL;
+ }
+ 
+-static void dcn10_apply_ctx_for_surface(
++void dcn10_apply_ctx_for_surface(
+ 		struct dc *dc,
+ 		const struct dc_stream_state *stream,
+ 		int num_planes,
+@@ -2571,7 +2484,7 @@ static void dcn10_apply_ctx_for_surface(
+ 	bool removed_pipe[4] = { false };
+ 	bool interdependent_update = false;
+ 	struct pipe_ctx *top_pipe_to_program =
+-			find_top_pipe_for_stream(dc, context, stream);
++			dcn10_find_top_pipe_for_stream(dc, context, stream);
+ 	DC_LOGGER_INIT(dc->ctx->logger);
+ 
+ 	if (!top_pipe_to_program)
+@@ -2588,7 +2501,7 @@ static void dcn10_apply_ctx_for_surface(
+ 		ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
+ 
+ 	if (interdependent_update)
+-		lock_all_pipes(dc, context, true);
++		dcn10_lock_all_pipes(dc, context, true);
+ 	else
+ 		dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
+ 
+@@ -2635,7 +2548,7 @@ static void dcn10_apply_ctx_for_surface(
+ 	}
+ 
+ 	if (num_planes > 0)
+-		program_all_pipe_in_tree(dc, top_pipe_to_program, context);
++		dcn10_program_all_pipe_in_tree(dc, top_pipe_to_program, context);
+ 
+ 	/* Program secondary blending tree and writeback pipes */
+ 	if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree))
+@@ -2655,7 +2568,7 @@ static void dcn10_apply_ctx_for_surface(
+ 		}
+ 
+ 	if (interdependent_update)
+-		lock_all_pipes(dc, context, false);
++		dcn10_lock_all_pipes(dc, context, false);
+ 	else
+ 		dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
+ 
+@@ -2692,14 +2605,14 @@ static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *contex
+ 	}
+ }
+ 
+-static void dcn10_prepare_bandwidth(
++void dcn10_prepare_bandwidth(
+ 		struct dc *dc,
+ 		struct dc_state *context)
+ {
+ 	struct hubbub *hubbub = dc->res_pool->hubbub;
+ 
+ 	if (dc->debug.sanity_checks)
+-		dcn10_verify_allow_pstate_change_high(dc);
++		dc->hwss.verify_allow_pstate_change_high(dc);
+ 
+ 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 		if (context->stream_count == 0)
+@@ -2721,17 +2634,17 @@ static void dcn10_prepare_bandwidth(
+ 		dcn_bw_notify_pplib_of_wm_ranges(dc);
+ 
+ 	if (dc->debug.sanity_checks)
+-		dcn10_verify_allow_pstate_change_high(dc);
++		dc->hwss.verify_allow_pstate_change_high(dc);
+ }
+ 
+-static void dcn10_optimize_bandwidth(
++void dcn10_optimize_bandwidth(
+ 		struct dc *dc,
+ 		struct dc_state *context)
+ {
+ 	struct hubbub *hubbub = dc->res_pool->hubbub;
+ 
+ 	if (dc->debug.sanity_checks)
+-		dcn10_verify_allow_pstate_change_high(dc);
++		dc->hwss.verify_allow_pstate_change_high(dc);
+ 
+ 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 		if (context->stream_count == 0)
+@@ -2753,10 +2666,10 @@ static void dcn10_optimize_bandwidth(
+ 		dcn_bw_notify_pplib_of_wm_ranges(dc);
+ 
+ 	if (dc->debug.sanity_checks)
+-		dcn10_verify_allow_pstate_change_high(dc);
++		dc->hwss.verify_allow_pstate_change_high(dc);
+ }
+ 
+-static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
++void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
+ 		int num_pipes, unsigned int vmin, unsigned int vmax,
+ 		unsigned int vmid, unsigned int vmid_frame_number)
+ {
+@@ -2784,7 +2697,7 @@ static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
+ 	}
+ }
+ 
+-static void dcn10_get_position(struct pipe_ctx **pipe_ctx,
++void dcn10_get_position(struct pipe_ctx **pipe_ctx,
+ 		int num_pipes,
+ 		struct crtc_position *position)
+ {
+@@ -2796,7 +2709,7 @@ static void dcn10_get_position(struct pipe_ctx **pipe_ctx,
+ 		pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
+ }
+ 
+-static void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
++void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
+ 		int num_pipes, const struct dc_static_screen_events *events)
+ {
+ 	unsigned int i;
+@@ -2851,7 +2764,7 @@ static void dcn10_config_stereo_parameters(
+ 	return;
+ }
+ 
+-static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
++void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
+ {
+ 	struct crtc_stereo_flags flags = { 0 };
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+@@ -2890,7 +2803,7 @@ static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_in
+ 	return NULL;
+ }
+ 
+-static void dcn10_wait_for_mpcc_disconnect(
++void dcn10_wait_for_mpcc_disconnect(
+ 		struct dc *dc,
+ 		struct resource_pool *res_pool,
+ 		struct pipe_ctx *pipe_ctx)
+@@ -2898,7 +2811,7 @@ static void dcn10_wait_for_mpcc_disconnect(
+ 	int mpcc_inst;
+ 
+ 	if (dc->debug.sanity_checks) {
+-		dcn10_verify_allow_pstate_change_high(dc);
++		dc->hwss.verify_allow_pstate_change_high(dc);
+ 	}
+ 
+ 	if (!pipe_ctx->stream_res.opp)
+@@ -2915,12 +2828,12 @@ static void dcn10_wait_for_mpcc_disconnect(
+ 	}
+ 
+ 	if (dc->debug.sanity_checks) {
+-		dcn10_verify_allow_pstate_change_high(dc);
++		dc->hwss.verify_allow_pstate_change_high(dc);
+ 	}
+ 
+ }
+ 
+-static bool dcn10_dummy_display_power_gating(
++bool dcn10_dummy_display_power_gating(
+ 	struct dc *dc,
+ 	uint8_t controller_id,
+ 	struct dc_bios *dcb,
+@@ -2929,7 +2842,7 @@ static bool dcn10_dummy_display_power_gating(
+ 	return true;
+ }
+ 
+-static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
++void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
+ {
+ 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+ 	struct timing_generator *tg = pipe_ctx->stream_res.tg;
+@@ -2953,7 +2866,7 @@ static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
+ 	}
+ }
+ 
+-static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
++void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
+ {
+ 	struct hubbub *hubbub = hws->ctx->dc->res_pool->hubbub;
+ 
+@@ -2961,7 +2874,7 @@ static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh
+ 	hubbub->funcs->update_dchub(hubbub, dh_data);
+ }
+ 
+-static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
++void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
+ {
+ 	struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+@@ -3027,7 +2940,7 @@ static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
+ 	dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);
+ }
+ 
+-static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
++void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
+ {
+ 	struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
+ 
+@@ -3037,7 +2950,7 @@ static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
+ 		pipe_ctx->plane_res.dpp, attributes);
+ }
+ 
+-static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
++void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
+ {
+ 	uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level;
+ 	struct fixed31_32 multiplier;
+@@ -3064,12 +2977,12 @@ static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
+ 			pipe_ctx->plane_res.dpp, &opt_attr);
+ }
+ 
+-/**
+-* apply_front_porch_workaround  TODO FPGA still need?
+-*
+-* This is a workaround for a bug that has existed since R5xx and has not been
+-* fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
+-*/
++/*
++ * apply_front_porch_workaround  TODO FPGA still need?
++ *
++ * This is a workaround for a bug that has existed since R5xx and has not been
++ * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
++ */
+ static void apply_front_porch_workaround(
+ 	struct dc_crtc_timing *timing)
+ {
+@@ -3082,7 +2995,7 @@ static void apply_front_porch_workaround(
+ 	}
+ }
+ 
+-int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)
++int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)
+ {
+ 	const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
+ 	struct dc_crtc_timing patched_crtc_timing;
+@@ -3111,34 +3024,8 @@ int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)
+ 	return vertical_line_start;
+ }
+ 
+-void lock_all_pipes(struct dc *dc,
+-	struct dc_state *context,
+-	bool lock)
+-{
+-	struct pipe_ctx *pipe_ctx;
+-	struct timing_generator *tg;
+-	int i;
+-
+-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+-		pipe_ctx = &context->res_ctx.pipe_ctx[i];
+-		tg = pipe_ctx->stream_res.tg;
+-		/*
+-		 * Only lock the top pipe's tg to prevent redundant
+-		 * (un)locking. Also skip if pipe is disabled.
+-		 */
+-		if (pipe_ctx->top_pipe ||
+-		    !pipe_ctx->stream || !pipe_ctx->plane_state ||
+-		    !tg->funcs->is_tg_enabled(tg))
+-			continue;
+-
+-		if (lock)
+-			tg->funcs->lock(tg);
+-		else
+-			tg->funcs->unlock(tg);
+-	}
+-}
+-
+-static void calc_vupdate_position(
++static void dcn10_calc_vupdate_position(
++		struct dc *dc,
+ 		struct pipe_ctx *pipe_ctx,
+ 		uint32_t *start_line,
+ 		uint32_t *end_line)
+@@ -3146,7 +3033,7 @@ static void calc_vupdate_position(
+ 	const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
+ 	int vline_int_offset_from_vupdate =
+ 			pipe_ctx->stream->periodic_interrupt0.lines_offset;
+-	int vupdate_offset_from_vsync = get_vupdate_offset_from_vsync(pipe_ctx);
++	int vupdate_offset_from_vsync = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
+ 	int start_position;
+ 
+ 	if (vline_int_offset_from_vupdate > 0)
+@@ -3167,7 +3054,8 @@ static void calc_vupdate_position(
+ 		*end_line = 2;
+ }
+ 
+-static void cal_vline_position(
++static void dcn10_cal_vline_position(
++		struct dc *dc,
+ 		struct pipe_ctx *pipe_ctx,
+ 		enum vline_select vline,
+ 		uint32_t *start_line,
+@@ -3182,7 +3070,8 @@ static void cal_vline_position(
+ 
+ 	switch (ref_point) {
+ 	case START_V_UPDATE:
+-		calc_vupdate_position(
++		dcn10_calc_vupdate_position(
++				dc,
+ 				pipe_ctx,
+ 				start_line,
+ 				end_line);
+@@ -3196,7 +3085,8 @@ static void cal_vline_position(
+ 	}
+ }
+ 
+-static void dcn10_setup_periodic_interrupt(
++void dcn10_setup_periodic_interrupt(
++		struct dc *dc,
+ 		struct pipe_ctx *pipe_ctx,
+ 		enum vline_select vline)
+ {
+@@ -3206,7 +3096,7 @@ static void dcn10_setup_periodic_interrupt(
+ 		uint32_t start_line = 0;
+ 		uint32_t end_line = 0;
+ 
+-		cal_vline_position(pipe_ctx, vline, &start_line, &end_line);
++		dcn10_cal_vline_position(dc, pipe_ctx, vline, &start_line, &end_line);
+ 
+ 		tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line);
+ 
+@@ -3217,10 +3107,10 @@ static void dcn10_setup_periodic_interrupt(
+ 	}
+ }
+ 
+-static void dcn10_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx)
++void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	struct timing_generator *tg = pipe_ctx->stream_res.tg;
+-	int start_line = get_vupdate_offset_from_vsync(pipe_ctx);
++	int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
+ 
+ 	if (start_line < 0) {
+ 		ASSERT(0);
+@@ -3231,7 +3121,7 @@ static void dcn10_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx)
+ 		tg->funcs->setup_vertical_interrupt2(tg, start_line);
+ }
+ 
+-static void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
++void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
+ 		struct dc_link_settings *link_settings)
+ {
+ 	struct encoder_unblank_param params = { { 0 } };
+@@ -3254,7 +3144,7 @@ static void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
+ 	}
+ }
+ 
+-static void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
++void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
+ 				const uint8_t *custom_sdp_message,
+ 				unsigned int sdp_message_size)
+ {
+@@ -3265,7 +3155,7 @@ static void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
+ 				sdp_message_size);
+ 	}
+ }
+-static enum dc_status dcn10_set_clock(struct dc *dc,
++enum dc_status dcn10_set_clock(struct dc *dc,
+ 			enum dc_clock_type clock_type,
+ 			uint32_t clk_khz,
+ 			uint32_t stepping)
+@@ -3305,7 +3195,7 @@ static enum dc_status dcn10_set_clock(struct dc *dc,
+ 
+ }
+ 
+-static void dcn10_get_clock(struct dc *dc,
++void dcn10_get_clock(struct dc *dc,
+ 			enum dc_clock_type clock_type,
+ 			struct dc_clock_config *clock_cfg)
+ {
+@@ -3315,77 +3205,3 @@ static void dcn10_get_clock(struct dc *dc,
+ 				dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);
+ 
+ }
+-
+-static const struct hw_sequencer_funcs dcn10_funcs = {
+-	.program_gamut_remap = dcn10_program_gamut_remap,
+-	.init_hw = dcn10_init_hw,
+-	.init_pipes = dcn10_init_pipes,
+-	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+-	.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
+-	.update_plane_addr = dcn10_update_plane_addr,
+-	.plane_atomic_disconnect = hwss1_plane_atomic_disconnect,
+-	.update_dchub = dcn10_update_dchub,
+-	.update_mpcc = dcn10_update_mpcc,
+-	.update_pending_status = dcn10_update_pending_status,
+-	.set_input_transfer_func = dcn10_set_input_transfer_func,
+-	.set_output_transfer_func = dcn10_set_output_transfer_func,
+-	.program_output_csc = dcn10_program_output_csc,
+-	.power_down = dce110_power_down,
+-	.enable_accelerated_mode = dce110_enable_accelerated_mode,
+-	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
+-	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
+-	.update_info_frame = dce110_update_info_frame,
+-	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
+-	.enable_stream = dce110_enable_stream,
+-	.disable_stream = dce110_disable_stream,
+-	.unblank_stream = dcn10_unblank_stream,
+-	.blank_stream = dce110_blank_stream,
+-	.enable_audio_stream = dce110_enable_audio_stream,
+-	.disable_audio_stream = dce110_disable_audio_stream,
+-	.enable_display_power_gating = dcn10_dummy_display_power_gating,
+-	.disable_plane = dcn10_disable_plane,
+-	.blank_pixel_data = dcn10_blank_pixel_data,
+-	.pipe_control_lock = dcn10_pipe_control_lock,
+-	.prepare_bandwidth = dcn10_prepare_bandwidth,
+-	.optimize_bandwidth = dcn10_optimize_bandwidth,
+-	.reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
+-	.enable_stream_timing = dcn10_enable_stream_timing,
+-	.set_drr = dcn10_set_drr,
+-	.get_position = dcn10_get_position,
+-	.set_static_screen_control = dcn10_set_static_screen_control,
+-	.setup_stereo = dcn10_setup_stereo,
+-	.set_avmute = dce110_set_avmute,
+-	.log_hw_state = dcn10_log_hw_state,
+-	.get_hw_state = dcn10_get_hw_state,
+-	.clear_status_bits = dcn10_clear_status_bits,
+-	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+-	.edp_backlight_control = dce110_edp_backlight_control,
+-	.edp_power_control = dce110_edp_power_control,
+-	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+-	.set_cursor_position = dcn10_set_cursor_position,
+-	.set_cursor_attribute = dcn10_set_cursor_attribute,
+-	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
+-	.disable_stream_gating = NULL,
+-	.enable_stream_gating = NULL,
+-	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
+-	.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
+-	.set_clock = dcn10_set_clock,
+-	.get_clock = dcn10_get_clock,
+-	.did_underflow_occur = dcn10_did_underflow_occur,
+-	.init_blank = NULL,
+-	.disable_vga = dcn10_disable_vga,
+-	.bios_golden_init = dcn10_bios_golden_init,
+-	.plane_atomic_disable = dcn10_plane_atomic_disable,
+-	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
+-	.enable_power_gating_plane = dcn10_enable_power_gating_plane,
+-	.dpp_pg_control = dcn10_dpp_pg_control,
+-	.hubp_pg_control = dcn10_hubp_pg_control,
+-	.dsc_pg_control = NULL,
+-};
+-
+-
+-void dcn10_hw_sequencer_construct(struct dc *dc)
+-{
+-	dc->hwss = dcn10_funcs;
+-}
+-
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+index d3616b1948cc..5aad3922be6c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+@@ -31,64 +31,155 @@
+ struct dc;
+ 
+ void dcn10_hw_sequencer_construct(struct dc *dc);
+-extern void fill_display_configs(
+-	const struct dc_state *context,
+-	struct dm_pp_display_configuration *pp_display_cfg);
+-
+-bool is_rgb_cspace(enum dc_color_space output_color_space);
+-
+-void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);
+-
+-void dcn10_verify_allow_pstate_change_high(struct dc *dc);
+ 
++int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);
++void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
++enum dc_status dcn10_enable_stream_timing(
++		struct pipe_ctx *pipe_ctx,
++		struct dc_state *context,
++		struct dc *dc);
++void dcn10_optimize_bandwidth(
++		struct dc *dc,
++		struct dc_state *context);
++void dcn10_prepare_bandwidth(
++		struct dc *dc,
++		struct dc_state *context);
++void dcn10_pipe_control_lock(
++	struct dc *dc,
++	struct pipe_ctx *pipe,
++	bool lock);
++void dcn10_blank_pixel_data(
++		struct dc *dc,
++		struct pipe_ctx *pipe_ctx,
++		bool blank);
++void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
++		struct dc_link_settings *link_settings);
++void dcn10_program_output_csc(struct dc *dc,
++		struct pipe_ctx *pipe_ctx,
++		enum dc_color_space colorspace,
++		uint16_t *matrix,
++		int opp_id);
++bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
++				const struct dc_stream_state *stream);
++bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
++			const struct dc_plane_state *plane_state);
++void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn10_reset_hw_ctx_wrap(
++		struct dc *dc,
++		struct dc_state *context);
++void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn10_apply_ctx_for_surface(
++		struct dc *dc,
++		const struct dc_stream_state *stream,
++		int num_planes,
++		struct dc_state *context);
++void dcn10_hubp_pg_control(
++		struct dce_hwseq *hws,
++		unsigned int hubp_inst,
++		bool power_on);
++void dcn10_dpp_pg_control(
++		struct dce_hwseq *hws,
++		unsigned int dpp_inst,
++		bool power_on);
++void dcn10_enable_power_gating_plane(
++	struct dce_hwseq *hws,
++	bool enable);
++void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn10_disable_vga(
++	struct dce_hwseq *hws);
+ void dcn10_program_pipe(
+ 		struct dc *dc,
+ 		struct pipe_ctx *pipe_ctx,
+ 		struct dc_state *context);
+-
+-void dcn10_get_hw_state(
++void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx);
++void dcn10_init_hw(struct dc *dc);
++void dcn10_init_pipes(struct dc *dc, struct dc_state *context);
++enum dc_status dce110_apply_ctx_to_hw(
++		struct dc *dc,
++		struct dc_state *context);
++void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data);
++void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx);
++void dce110_power_down(struct dc *dc);
++void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);
++void dcn10_enable_timing_synchronization(
++		struct dc *dc,
++		int group_index,
++		int group_size,
++		struct pipe_ctx *grouped_pipes[]);
++void dcn10_enable_per_frame_crtc_position_reset(
++		struct dc *dc,
++		int group_size,
++		struct pipe_ctx *grouped_pipes[]);
++void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);
++void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
++		const uint8_t *custom_sdp_message,
++		unsigned int sdp_message_size);
++void dce110_blank_stream(struct pipe_ctx *pipe_ctx);
++void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);
++void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);
++bool dcn10_dummy_display_power_gating(
+ 		struct dc *dc,
+-		char *pBuf, unsigned int bufSize,
++		uint8_t controller_id,
++		struct dc_bios *dcb,
++		enum pipe_gating_control power_gating);
++void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
++		int num_pipes, unsigned int vmin, unsigned int vmax,
++		unsigned int vmid, unsigned int vmid_frame_number);
++void dcn10_get_position(struct pipe_ctx **pipe_ctx,
++		int num_pipes,
++		struct crtc_position *position);
++void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
++		int num_pipes, const struct dc_static_screen_events *events);
++void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc);
++void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
++void dcn10_log_hw_state(struct dc *dc,
++		struct dc_log_buffer_ctx *log_ctx);
++void dcn10_get_hw_state(struct dc *dc,
++		char *pBuf,
++		unsigned int bufSize,
+ 		unsigned int mask);
+-
+ void dcn10_clear_status_bits(struct dc *dc, unsigned int mask);
+-
+-bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
+-
+-bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
+-
+-bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
+-
+-void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp);
+-
+-void set_hdr_multiplier(struct pipe_ctx *pipe_ctx);
+-
++void dcn10_wait_for_mpcc_disconnect(
++		struct dc *dc,
++		struct resource_pool *res_pool,
++		struct pipe_ctx *pipe_ctx);
++void dce110_edp_backlight_control(
++		struct dc_link *link,
++		bool enable);
++void dce110_edp_power_control(
++		struct dc_link *link,
++		bool power_up);
++void dce110_edp_wait_for_hpd_ready(
++		struct dc_link *link,
++		bool power_up);
++void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx);
++void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx);
++void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx);
++void dcn10_setup_periodic_interrupt(
++		struct dc *dc,
++		struct pipe_ctx *pipe_ctx,
++		enum vline_select vline);
++enum dc_status dcn10_set_clock(struct dc *dc,
++		enum dc_clock_type clock_type,
++		uint32_t clk_khz,
++		uint32_t stepping);
++void dcn10_get_clock(struct dc *dc,
++		enum dc_clock_type clock_type,
++		struct dc_clock_config *clock_cfg);
++bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn10_bios_golden_init(struct dc *dc);
++void dcn10_plane_atomic_power_down(struct dc *dc,
++		struct dpp *dpp,
++		struct hubp *hubp);
+ void dcn10_get_surface_visual_confirm_color(
+ 		const struct pipe_ctx *pipe_ctx,
+ 		struct tg_color *color);
+-
+ void dcn10_get_hdr_visual_confirm_color(
+ 		struct pipe_ctx *pipe_ctx,
+ 		struct tg_color *color);
+-
+-bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);
+-
+-void update_dchubp_dpp(
+-	struct dc *dc,
+-	struct pipe_ctx *pipe_ctx,
+-	struct dc_state *context);
+-
+-struct pipe_ctx *find_top_pipe_for_stream(
+-		struct dc *dc,
+-		struct dc_state *context,
+-		const struct dc_stream_state *stream);
+-
+-int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);
+-
+-void dcn10_build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
+-		const struct dc_plane_state *plane_state);
+-void lock_all_pipes(struct dc *dc,
+-	struct dc_state *context,
+-	bool lock);
++void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx);
++void dcn10_verify_allow_pstate_change_high(struct dc *dc);
+ 
+ #endif /* __DC_HWSS_DCN10_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.h
+new file mode 100644
+index 000000000000..596f95c22e85
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.h
+@@ -0,0 +1,43 @@
++/*
++ * Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DC_HWSS_DCN10_DEBUG_H__
++#define __DC_HWSS_DCN10_DEBUG_H__
++
++#include "core_types.h"
++
++struct dc;
++
++void dcn10_clear_status_bits(struct dc *dc, unsigned int mask);
++
++void dcn10_log_hw_state(struct dc *dc,
++		struct dc_log_buffer_ctx *log_ctx);
++
++void dcn10_get_hw_state(struct dc *dc,
++		char *pBuf,
++		unsigned int bufSize,
++		unsigned int mask);
++
++#endif /* __DC_HWSS_DCN10_DEBUG_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+new file mode 100644
+index 000000000000..38923f3120ee
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+@@ -0,0 +1,105 @@
++/*
++ * Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "dce110/dce110_hw_sequencer.h"
++#include "dcn10_hw_sequencer.h"
++
++static const struct hw_sequencer_funcs dcn10_funcs = {
++	.program_gamut_remap = dcn10_program_gamut_remap,
++	.init_hw = dcn10_init_hw,
++	.init_pipes = dcn10_init_pipes,
++	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
++	.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
++	.update_plane_addr = dcn10_update_plane_addr,
++	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
++	.program_pipe = dcn10_program_pipe,
++	.update_dchub = dcn10_update_dchub,
++	.update_mpcc = dcn10_update_mpcc,
++	.update_pending_status = dcn10_update_pending_status,
++	.set_input_transfer_func = dcn10_set_input_transfer_func,
++	.set_output_transfer_func = dcn10_set_output_transfer_func,
++	.program_output_csc = dcn10_program_output_csc,
++	.power_down = dce110_power_down,
++	.enable_accelerated_mode = dce110_enable_accelerated_mode,
++	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
++	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
++	.update_info_frame = dce110_update_info_frame,
++	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
++	.enable_stream = dce110_enable_stream,
++	.disable_stream = dce110_disable_stream,
++	.unblank_stream = dcn10_unblank_stream,
++	.blank_stream = dce110_blank_stream,
++	.enable_audio_stream = dce110_enable_audio_stream,
++	.disable_audio_stream = dce110_disable_audio_stream,
++	.enable_display_power_gating = dcn10_dummy_display_power_gating,
++	.disable_plane = dcn10_disable_plane,
++	.blank_pixel_data = dcn10_blank_pixel_data,
++	.pipe_control_lock = dcn10_pipe_control_lock,
++	.prepare_bandwidth = dcn10_prepare_bandwidth,
++	.optimize_bandwidth = dcn10_optimize_bandwidth,
++	.reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
++	.enable_stream_timing = dcn10_enable_stream_timing,
++	.set_drr = dcn10_set_drr,
++	.get_position = dcn10_get_position,
++	.set_static_screen_control = dcn10_set_static_screen_control,
++	.setup_stereo = dcn10_setup_stereo,
++	.set_avmute = dce110_set_avmute,
++	.log_hw_state = dcn10_log_hw_state,
++	.get_hw_state = dcn10_get_hw_state,
++	.clear_status_bits = dcn10_clear_status_bits,
++	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
++	.edp_backlight_control = dce110_edp_backlight_control,
++	.edp_power_control = dce110_edp_power_control,
++	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
++	.set_cursor_position = dcn10_set_cursor_position,
++	.set_cursor_attribute = dcn10_set_cursor_attribute,
++	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
++	.disable_stream_gating = NULL,
++	.enable_stream_gating = NULL,
++	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
++	.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
++	.set_clock = dcn10_set_clock,
++	.get_clock = dcn10_get_clock,
++	.did_underflow_occur = dcn10_did_underflow_occur,
++	.init_blank = NULL,
++	.disable_vga = dcn10_disable_vga,
++	.bios_golden_init = dcn10_bios_golden_init,
++	.plane_atomic_disable = dcn10_plane_atomic_disable,
++	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
++	.enable_power_gating_plane = dcn10_enable_power_gating_plane,
++	.dpp_pg_control = dcn10_dpp_pg_control,
++	.hubp_pg_control = dcn10_hubp_pg_control,
++	.dsc_pg_control = NULL,
++	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
++	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
++	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
++	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
++	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
++};
++
++void dcn10_hw_sequencer_construct(struct dc *dc)
++{
++	dc->hwss = dcn10_funcs;
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.h
+new file mode 100644
+index 000000000000..8c6fd7b844a4
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.h
+@@ -0,0 +1,33 @@
++/*
++ * Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DC_DCN10_INIT_H__
++#define __DC_DCN10_INIT_H__
++
++struct dc;
++
++void dcn10_hw_sequencer_construct(struct dc *dc);
++
++#endif /* __DC_DCN10_INIT_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index c4129e21e643..db820a0c79d6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -26,6 +26,8 @@
+ #include "dm_services.h"
+ #include "dc.h"
+ 
++#include "dcn10_init.h"
++
+ #include "resource.h"
+ #include "include/irq_service_interface.h"
+ #include "dcn10_resource.h"
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+index 89c581196c4c..c49ebe7a6fd9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+@@ -1,7 +1,7 @@
+ #
+ # Makefile for DCN.
+ 
+-DCN20 = dcn20_resource.o dcn20_hwseq.o dcn20_dpp.o dcn20_dpp_cm.o dcn20_hubp.o \
++DCN20 = dcn20_resource.o dcn20_init.o dcn20_hwseq.o dcn20_dpp.o dcn20_dpp_cm.o dcn20_hubp.o \
+ 		dcn20_mpc.o dcn20_opp.o dcn20_hubbub.o dcn20_optc.o dcn20_mmhubbub.o \
+ 		dcn20_stream_encoder.o dcn20_link_encoder.o dcn20_dccg.o \
+ 		dcn20_vmid.o dcn20_dwb.o dcn20_dwb_scl.o
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index fa1ecff747a1..937ecb28948d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -25,15 +25,19 @@
+ #include <linux/delay.h>
+ 
+ #include "dm_services.h"
++#include "basics/dc_common.h"
+ #include "dm_helpers.h"
+ #include "core_types.h"
+ #include "resource.h"
+-#include "dcn20/dcn20_resource.h"
+-#include "dce110/dce110_hw_sequencer.h"
+-#include "dcn10/dcn10_hw_sequencer.h"
++#include "dcn20_resource.h"
+ #include "dcn20_hwseq.h"
+ #include "dce/dce_hwseq.h"
++// TODO: This may be cause problem
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dcn20/dcn20_dsc.h"
++#endif
++#include "dcn20_dsc.h"
++#include "dcn20_optc.h"
+ #include "abm.h"
+ #include "clk_mgr.h"
+ #include "dmcu.h"
+@@ -43,10 +47,9 @@
+ #include "ipp.h"
+ #include "mpc.h"
+ #include "mcif_wb.h"
++#include "dchubbub.h"
+ #include "reg_helper.h"
+ #include "dcn10/dcn10_cm_common.h"
+-#include "dcn10/dcn10_hubbub.h"
+-#include "dcn10/dcn10_optc.h"
+ #include "dc_link_dp.h"
+ #include "vm_helper.h"
+ #include "dccg.h"
+@@ -62,7 +65,125 @@
+ #define FN(reg_name, field_name) \
+ 	hws->shifts->field_name, hws->masks->field_name
+ 
+-static void dcn20_enable_power_gating_plane(
++static int find_free_gsl_group(const struct dc *dc)
++{
++	if (dc->res_pool->gsl_groups.gsl_0 == 0)
++		return 1;
++	if (dc->res_pool->gsl_groups.gsl_1 == 0)
++		return 2;
++	if (dc->res_pool->gsl_groups.gsl_2 == 0)
++		return 3;
++
++	return 0;
++}
++
++/* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
++ * This is only used to lock pipes in pipe splitting case with immediate flip
++ * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
++ * so we get tearing with freesync since we cannot flip multiple pipes
++ * atomically.
++ * We use GSL for this:
++ * - immediate flip: find first available GSL group if not already assigned
++ *                   program gsl with that group, set current OTG as master
++ *                   and always us 0x4 = AND of flip_ready from all pipes
++ * - vsync flip: disable GSL if used
++ *
++ * Groups in stream_res are stored as +1 from HW registers, i.e.
++ * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
++ * Using a magic value like -1 would require tracking all inits/resets
++ */
++static void dcn20_setup_gsl_group_as_lock(
++		const struct dc *dc,
++		struct pipe_ctx *pipe_ctx,
++		bool enable)
++{
++	struct gsl_params gsl;
++	int group_idx;
++
++	memset(&gsl, 0, sizeof(struct gsl_params));
++
++	if (enable) {
++		/* return if group already assigned since GSL was set up
++		 * for vsync flip, we would unassign so it can't be "left over"
++		 */
++		if (pipe_ctx->stream_res.gsl_group > 0)
++			return;
++
++		group_idx = find_free_gsl_group(dc);
++		ASSERT(group_idx != 0);
++		pipe_ctx->stream_res.gsl_group = group_idx;
++
++		/* set gsl group reg field and mark resource used */
++		switch (group_idx) {
++		case 1:
++			gsl.gsl0_en = 1;
++			dc->res_pool->gsl_groups.gsl_0 = 1;
++			break;
++		case 2:
++			gsl.gsl1_en = 1;
++			dc->res_pool->gsl_groups.gsl_1 = 1;
++			break;
++		case 3:
++			gsl.gsl2_en = 1;
++			dc->res_pool->gsl_groups.gsl_2 = 1;
++			break;
++		default:
++			BREAK_TO_DEBUGGER();
++			return; // invalid case
++		}
++		gsl.gsl_master_en = 1;
++	} else {
++		group_idx = pipe_ctx->stream_res.gsl_group;
++		if (group_idx == 0)
++			return; // if not in use, just return
++
++		pipe_ctx->stream_res.gsl_group = 0;
++
++		/* unset gsl group reg field and mark resource free */
++		switch (group_idx) {
++		case 1:
++			gsl.gsl0_en = 0;
++			dc->res_pool->gsl_groups.gsl_0 = 0;
++			break;
++		case 2:
++			gsl.gsl1_en = 0;
++			dc->res_pool->gsl_groups.gsl_1 = 0;
++			break;
++		case 3:
++			gsl.gsl2_en = 0;
++			dc->res_pool->gsl_groups.gsl_2 = 0;
++			break;
++		default:
++			BREAK_TO_DEBUGGER();
++			return;
++		}
++		gsl.gsl_master_en = 0;
++	}
++
++	/* at this point we want to program whether it's to enable or disable */
++	if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
++		pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
++		pipe_ctx->stream_res.tg->funcs->set_gsl(
++			pipe_ctx->stream_res.tg,
++			&gsl);
++
++		pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
++			pipe_ctx->stream_res.tg, group_idx,	enable ? 4 : 0);
++	} else
++		BREAK_TO_DEBUGGER();
++}
++
++void dcn20_set_flip_control_gsl(
++		struct pipe_ctx *pipe_ctx,
++		bool flip_immediate)
++{
++	if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
++		pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
++				pipe_ctx->plane_res.hubp, flip_immediate);
++
++}
++
++void dcn20_enable_power_gating_plane(
+ 	struct dce_hwseq *hws,
+ 	bool enable)
+ {
+@@ -126,44 +247,6 @@ void dcn20_dccg_init(struct dce_hwseq *hws)
+ 	/* This value is dependent on the hardware pipeline delay so set once per SOC */
+ 	REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
+ }
+-void dcn20_display_init(struct dc *dc)
+-{
+-	struct dce_hwseq *hws = dc->hwseq;
+-
+-	/* RBBMIF
+-	 * disable RBBMIF timeout detection for all clients
+-	 * Ensure RBBMIF does not drop register accesses due to the per-client timeout
+-	 */
+-	REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
+-	REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
+-
+-	/* DCCG */
+-	dcn20_dccg_init(hws);
+-
+-	REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 0);
+-
+-	/* DCHUB/MMHUBBUB
+-	 * set global timer refclk divider
+-	 * 100Mhz refclk -> 2
+-	 * 27Mhz refclk ->  1
+-	 * 48Mhz refclk ->  1
+-	 */
+-	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
+-	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
+-	REG_WRITE(REFCLK_CNTL, 0);
+-
+-	/* OPTC
+-	 * OTG_CONTROL.OTG_DISABLE_POINT_CNTL = 0x3; will be set during optc2_enable_crtc
+-	 */
+-
+-	/* AZ
+-	 * default value is 0x64 for 100Mhz ref clock, if the ref clock is 100Mhz, no need to program this regiser,
+-	 * if not, it should be programmed according to the ref clock
+-	 */
+-	REG_UPDATE(AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, 0x64);
+-	/* Enable controller clock gating */
+-	REG_WRITE(AZALIA_CONTROLLER_CLOCK_GATING, 0x1);
+-}
+ 
+ void dcn20_disable_vga(
+ 	struct dce_hwseq *hws)
+@@ -176,15 +259,15 @@ void dcn20_disable_vga(
+ 	REG_WRITE(D6VGA_CONTROL, 0);
+ }
+ 
+-void dcn20_program_tripleBuffer(
++void dcn20_program_triple_buffer(
+ 	const struct dc *dc,
+ 	struct pipe_ctx *pipe_ctx,
+-	bool enableTripleBuffer)
++	bool enable_triple_buffer)
+ {
+ 	if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
+ 		pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
+ 			pipe_ctx->plane_res.hubp,
+-			enableTripleBuffer);
++			enable_triple_buffer);
+ 	}
+ }
+ 
+@@ -240,10 +323,10 @@ void dcn20_init_blank(
+ 				otg_active_height);
+ 	}
+ 
+-	dcn20_hwss_wait_for_blank_complete(opp);
++	dc->hwss.wait_for_blank_complete(opp);
+ }
+ 
+-static void dcn20_dsc_pg_control(
++void dcn20_dsc_pg_control(
+ 		struct dce_hwseq *hws,
+ 		unsigned int dsc_inst,
+ 		bool power_on)
+@@ -320,7 +403,7 @@ static void dcn20_dsc_pg_control(
+ 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
+ }
+ 
+-static void dcn20_dpp_pg_control(
++void dcn20_dpp_pg_control(
+ 		struct dce_hwseq *hws,
+ 		unsigned int dpp_inst,
+ 		bool power_on)
+@@ -394,7 +477,7 @@ static void dcn20_dpp_pg_control(
+ }
+ 
+ 
+-static void dcn20_hubp_pg_control(
++void dcn20_hubp_pg_control(
+ 		struct dce_hwseq *hws,
+ 		unsigned int hubp_inst,
+ 		bool power_on)
+@@ -471,7 +554,7 @@ static void dcn20_hubp_pg_control(
+ /* disable HW used by plane.
+  * note:  cannot disable until disconnect is complete
+  */
+-static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
+@@ -591,7 +674,7 @@ enum dc_status dcn20_enable_stream_timing(
+ 		return DC_ERROR_UNEXPECTED;
+ 	}
+ 
+-	dcn20_hwss_wait_for_blank_complete(pipe_ctx->stream_res.opp);
++	dc->hwss.wait_for_blank_complete(pipe_ctx->stream_res.opp);
+ 
+ 	params.vertical_total_min = stream->adjust.v_total_min;
+ 	params.vertical_total_max = stream->adjust.v_total_max;
+@@ -647,7 +730,7 @@ void dcn20_program_output_csc(struct dc *dc,
+ 	}
+ }
+ 
+-bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
++bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
+ 				const struct dc_stream_state *stream)
+ {
+ 	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
+@@ -737,8 +820,9 @@ bool dcn20_set_shaper_3dlut(
+ 	return result;
+ }
+ 
+-bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
+-					  const struct dc_plane_state *plane_state)
++bool dcn20_set_input_transfer_func(struct dc *dc,
++				struct pipe_ctx *pipe_ctx,
++				const struct dc_plane_state *plane_state)
+ {
+ 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
+ 	const struct dc_transfer_func *tf = NULL;
+@@ -748,8 +832,8 @@ bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
+ 	if (dpp_base == NULL || plane_state == NULL)
+ 		return false;
+ 
+-	dcn20_set_shaper_3dlut(pipe_ctx, plane_state);
+-	dcn20_set_blend_lut(pipe_ctx, plane_state);
++	dc->hwss.set_shaper_3dlut(pipe_ctx, plane_state);
++	dc->hwss.set_blend_lut(pipe_ctx, plane_state);
+ 
+ 	if (plane_state->in_transfer_func)
+ 		tf = plane_state->in_transfer_func;
+@@ -814,7 +898,7 @@ bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
+ 	return result;
+ }
+ 
+-static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
++void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
+ {
+ 	struct pipe_ctx *odm_pipe;
+ 	int opp_cnt = 1;
+@@ -1256,7 +1340,7 @@ static void dcn20_update_dchubp_dpp(
+ 
+ 		if (dpp->funcs->dpp_program_bias_and_scale) {
+ 			//TODO :for CNVC set scale and bias registers if necessary
+-			dcn10_build_prescale_params(&bns_params, plane_state);
++			build_prescale_params(&bns_params, plane_state);
+ 			dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
+ 		}
+ 	}
+@@ -1380,7 +1464,7 @@ static void dcn20_program_pipe(
+ 				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+ 
+ 		if (dc->hwss.setup_vupdate_interrupt)
+-			dc->hwss.setup_vupdate_interrupt(pipe_ctx);
++			dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
+ 	}
+ 
+ 	if (pipe_ctx->update_flags.bits.odm)
+@@ -1394,19 +1478,19 @@ static void dcn20_program_pipe(
+ 
+ 	if (pipe_ctx->update_flags.bits.enable
+ 			|| pipe_ctx->plane_state->update_flags.bits.hdr_mult)
+-		set_hdr_multiplier(pipe_ctx);
++		dc->hwss.set_hdr_multiplier(pipe_ctx);
+ 
+ 	if (pipe_ctx->update_flags.bits.enable ||
+ 			pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
+ 			pipe_ctx->plane_state->update_flags.bits.gamma_change)
+-		dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
++		dc->hwss.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
+ 
+ 	/* dcn10_translate_regamma_to_hw_format takes 750us to finish
+ 	 * only do gamma programming for powering on, internal memcmp to avoid
+ 	 * updating on slave planes
+ 	 */
+ 	if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf)
+-		dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
++		dc->hwss.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
+ 
+ 	/* If the pipe has been enabled or has a different opp, we
+ 	 * should reprogram the fmt. This deals with cases where
+@@ -1440,7 +1524,7 @@ static bool does_pipe_need_lock(struct pipe_ctx *pipe)
+ 	return false;
+ }
+ 
+-static void dcn20_program_front_end_for_ctx(
++void dcn20_program_front_end_for_ctx(
+ 		struct dc *dc,
+ 		struct dc_state *context)
+ {
+@@ -1621,7 +1705,7 @@ bool dcn20_update_bandwidth(
+ 				dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
+ 
+ 			if (dc->hwss.setup_vupdate_interrupt)
+-				dc->hwss.setup_vupdate_interrupt(pipe_ctx);
++				dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
+ 		}
+ 
+ 		pipe_ctx->plane_res.hubp->funcs->hubp_setup(
+@@ -1635,7 +1719,7 @@ bool dcn20_update_bandwidth(
+ 	return true;
+ }
+ 
+-static void dcn20_enable_writeback(
++void dcn20_enable_writeback(
+ 		struct dc *dc,
+ 		const struct dc_stream_status *stream_status,
+ 		struct dc_writeback_info *wb_info,
+@@ -1679,7 +1763,7 @@ void dcn20_disable_writeback(
+ 	mcif_wb->funcs->disable_mcif(mcif_wb);
+ }
+ 
+-bool dcn20_hwss_wait_for_blank_complete(
++bool dcn20_wait_for_blank_complete(
+ 		struct output_pixel_processor *opp)
+ {
+ 	int counter;
+@@ -1708,7 +1792,7 @@ bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
+ 	return hubp->funcs->dmdata_status_done(hubp);
+ }
+ 
+-static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	struct dce_hwseq *hws = dc->hwseq;
+ 
+@@ -1723,7 +1807,7 @@ static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx
+ 	}
+ }
+ 
+-static void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	struct dce_hwseq *hws = dc->hwseq;
+ 
+@@ -1758,12 +1842,7 @@ void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
+ 	hubp->funcs->dmdata_set_attributes(hubp, &attr);
+ }
+ 
+-void dcn20_disable_stream(struct pipe_ctx *pipe_ctx)
+-{
+-	dce110_disable_stream(pipe_ctx);
+-}
+-
+-static void dcn20_init_vm_ctx(
++void dcn20_init_vm_ctx(
+ 		struct dce_hwseq *hws,
+ 		struct dc *dc,
+ 		struct dc_virtual_addr_space_config *va_config,
+@@ -1785,7 +1864,7 @@ static void dcn20_init_vm_ctx(
+ 	dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
+ }
+ 
+-static int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
++int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
+ {
+ 	struct dcn_hubbub_phys_addr_config config;
+ 
+@@ -1829,8 +1908,7 @@ static bool patch_address_for_sbs_tb_stereo(
+ 	return false;
+ }
+ 
+-
+-static void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	bool addr_patched = false;
+ 	PHYSICAL_ADDRESS_LOC addr;
+@@ -1876,7 +1954,7 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
+ 	params.link_settings.link_rate = link_settings->link_rate;
+ 
+ 	if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
+-		if (optc1_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
++		if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
+ 			params.timing.pix_clk_100hz /= 2;
+ 		pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
+ 				pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
+@@ -1888,10 +1966,10 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
+ 	}
+ }
+ 
+-void dcn20_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx)
++void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	struct timing_generator *tg = pipe_ctx->stream_res.tg;
+-	int start_line = get_vupdate_offset_from_vsync(pipe_ctx);
++	int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
+ 
+ 	if (start_line < 0)
+ 		start_line = 0;
+@@ -1967,7 +2045,7 @@ static void dcn20_reset_back_end_for_pipe(
+ 					pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
+ }
+ 
+-static void dcn20_reset_hw_ctx_wrap(
++void dcn20_reset_hw_ctx_wrap(
+ 		struct dc *dc,
+ 		struct dc_state *context)
+ {
+@@ -2020,7 +2098,7 @@ void dcn20_get_mpctree_visual_confirm_color(
+ 	*color = pipe_colors[top_pipe->pipe_idx];
+ }
+ 
+-static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
++void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ 	struct mpcc_blnd_cfg blnd_cfg = { {0} };
+@@ -2032,10 +2110,10 @@ static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 
+ 	// input to MPCC is always RGB, by default leave black_color at 0
+ 	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
+-		dcn10_get_hdr_visual_confirm_color(
++		dc->hwss.get_hdr_visual_confirm_color(
+ 				pipe_ctx, &blnd_cfg.black_color);
+ 	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
+-		dcn10_get_surface_visual_confirm_color(
++		dc->hwss.get_surface_visual_confirm_color(
+ 				pipe_ctx, &blnd_cfg.black_color);
+ 	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
+ 		dcn20_get_mpctree_visual_confirm_color(
+@@ -2102,125 +2180,7 @@ static void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	hubp->mpcc_id = mpcc_id;
+ }
+ 
+-static int find_free_gsl_group(const struct dc *dc)
+-{
+-	if (dc->res_pool->gsl_groups.gsl_0 == 0)
+-		return 1;
+-	if (dc->res_pool->gsl_groups.gsl_1 == 0)
+-		return 2;
+-	if (dc->res_pool->gsl_groups.gsl_2 == 0)
+-		return 3;
+-
+-	return 0;
+-}
+-
+-/* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
+- * This is only used to lock pipes in pipe splitting case with immediate flip
+- * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
+- * so we get tearing with freesync since we cannot flip multiple pipes
+- * atomically.
+- * We use GSL for this:
+- * - immediate flip: find first available GSL group if not already assigned
+- *                   program gsl with that group, set current OTG as master
+- *                   and always us 0x4 = AND of flip_ready from all pipes
+- * - vsync flip: disable GSL if used
+- *
+- * Groups in stream_res are stored as +1 from HW registers, i.e.
+- * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
+- * Using a magic value like -1 would require tracking all inits/resets
+- */
+-void dcn20_setup_gsl_group_as_lock(
+-		const struct dc *dc,
+-		struct pipe_ctx *pipe_ctx,
+-		bool enable)
+-{
+-	struct gsl_params gsl;
+-	int group_idx;
+-
+-	memset(&gsl, 0, sizeof(struct gsl_params));
+-
+-	if (enable) {
+-		/* return if group already assigned since GSL was set up
+-		 * for vsync flip, we would unassign so it can't be "left over"
+-		 */
+-		if (pipe_ctx->stream_res.gsl_group > 0)
+-			return;
+-
+-		group_idx = find_free_gsl_group(dc);
+-		ASSERT(group_idx != 0);
+-		pipe_ctx->stream_res.gsl_group = group_idx;
+-
+-		/* set gsl group reg field and mark resource used */
+-		switch (group_idx) {
+-		case 1:
+-			gsl.gsl0_en = 1;
+-			dc->res_pool->gsl_groups.gsl_0 = 1;
+-			break;
+-		case 2:
+-			gsl.gsl1_en = 1;
+-			dc->res_pool->gsl_groups.gsl_1 = 1;
+-			break;
+-		case 3:
+-			gsl.gsl2_en = 1;
+-			dc->res_pool->gsl_groups.gsl_2 = 1;
+-			break;
+-		default:
+-			BREAK_TO_DEBUGGER();
+-			return; // invalid case
+-		}
+-		gsl.gsl_master_en = 1;
+-	} else {
+-		group_idx = pipe_ctx->stream_res.gsl_group;
+-		if (group_idx == 0)
+-			return; // if not in use, just return
+-
+-		pipe_ctx->stream_res.gsl_group = 0;
+-
+-		/* unset gsl group reg field and mark resource free */
+-		switch (group_idx) {
+-		case 1:
+-			gsl.gsl0_en = 0;
+-			dc->res_pool->gsl_groups.gsl_0 = 0;
+-			break;
+-		case 2:
+-			gsl.gsl1_en = 0;
+-			dc->res_pool->gsl_groups.gsl_1 = 0;
+-			break;
+-		case 3:
+-			gsl.gsl2_en = 0;
+-			dc->res_pool->gsl_groups.gsl_2 = 0;
+-			break;
+-		default:
+-			BREAK_TO_DEBUGGER();
+-			return;
+-		}
+-		gsl.gsl_master_en = 0;
+-	}
+-
+-	/* at this point we want to program whether it's to enable or disable */
+-	if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
+-		pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
+-		pipe_ctx->stream_res.tg->funcs->set_gsl(
+-			pipe_ctx->stream_res.tg,
+-			&gsl);
+-
+-		pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
+-			pipe_ctx->stream_res.tg, group_idx,	enable ? 4 : 0);
+-	} else
+-		BREAK_TO_DEBUGGER();
+-}
+-
+-static void dcn20_set_flip_control_gsl(
+-		struct pipe_ctx *pipe_ctx,
+-		bool flip_immediate)
+-{
+-	if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
+-		pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
+-				pipe_ctx->plane_res.hubp, flip_immediate);
+-
+-}
+-
+-static void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
++void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
+ {
+ 	enum dc_lane_count lane_count =
+ 		pipe_ctx->stream->link->cur_link_settings.lane_count;
+@@ -2268,7 +2228,7 @@ static void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
+ 	}
+ }
+ 
+-static void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
++void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
+ {
+ 	struct dc_stream_state    *stream     = pipe_ctx->stream;
+ 	struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
+@@ -2294,7 +2254,7 @@ static void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
+ 						hubp->inst, mode);
+ }
+ 
+-static void dcn20_fpga_init_hw(struct dc *dc)
++void dcn20_fpga_init_hw(struct dc *dc)
+ {
+ 	int i, j;
+ 	struct dce_hwseq *hws = dc->hwseq;
+@@ -2315,7 +2275,7 @@ static void dcn20_fpga_init_hw(struct dc *dc)
+ 	REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
+ 	REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
+ 
+-	dcn20_dccg_init(hws);
++	dc->hwss.dccg_init(hws);
+ 
+ 	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
+ 	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
+@@ -2379,7 +2339,7 @@ static void dcn20_fpga_init_hw(struct dc *dc)
+ 		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
+ 		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
+ 		/*to do*/
+-		hwss1_plane_atomic_disconnect(dc, pipe_ctx);
++		dc->hwss.plane_atomic_disconnect(dc, pipe_ctx);
+ 	}
+ 
+ 	/* initialize DWB pointer to MCIF_WB */
+@@ -2408,53 +2368,3 @@ static void dcn20_fpga_init_hw(struct dc *dc)
+ 		tg->funcs->tg_init(tg);
+ 	}
+ }
+-
+-void dcn20_hw_sequencer_construct(struct dc *dc)
+-{
+-	dcn10_hw_sequencer_construct(dc);
+-	dc->hwss.unblank_stream = dcn20_unblank_stream;
+-	dc->hwss.update_plane_addr = dcn20_update_plane_addr;
+-	dc->hwss.enable_stream_timing = dcn20_enable_stream_timing;
+-	dc->hwss.program_triplebuffer = dcn20_program_tripleBuffer;
+-	dc->hwss.set_input_transfer_func = dcn20_set_input_transfer_func;
+-	dc->hwss.set_output_transfer_func = dcn20_set_output_transfer_func;
+-	dc->hwss.apply_ctx_for_surface = NULL;
+-	dc->hwss.program_front_end_for_ctx = dcn20_program_front_end_for_ctx;
+-	dc->hwss.pipe_control_lock = dcn20_pipe_control_lock;
+-	dc->hwss.pipe_control_lock_global = dcn20_pipe_control_lock_global;
+-	dc->hwss.optimize_bandwidth = dcn20_optimize_bandwidth;
+-	dc->hwss.prepare_bandwidth = dcn20_prepare_bandwidth;
+-	dc->hwss.update_bandwidth = dcn20_update_bandwidth;
+-	dc->hwss.enable_writeback = dcn20_enable_writeback;
+-	dc->hwss.disable_writeback = dcn20_disable_writeback;
+-	dc->hwss.program_output_csc = dcn20_program_output_csc;
+-	dc->hwss.update_odm = dcn20_update_odm;
+-	dc->hwss.blank_pixel_data = dcn20_blank_pixel_data;
+-	dc->hwss.dmdata_status_done = dcn20_dmdata_status_done;
+-	dc->hwss.program_dmdata_engine = dcn20_program_dmdata_engine;
+-	dc->hwss.enable_stream = dcn20_enable_stream;
+-	dc->hwss.disable_stream = dcn20_disable_stream;
+-	dc->hwss.init_sys_ctx = dcn20_init_sys_ctx;
+-	dc->hwss.init_vm_ctx = dcn20_init_vm_ctx;
+-	dc->hwss.disable_stream_gating = dcn20_disable_stream_gating;
+-	dc->hwss.enable_stream_gating = dcn20_enable_stream_gating;
+-	dc->hwss.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt;
+-	dc->hwss.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap;
+-	dc->hwss.update_mpcc = dcn20_update_mpcc;
+-	dc->hwss.set_flip_control_gsl = dcn20_set_flip_control_gsl;
+-	dc->hwss.init_blank = dcn20_init_blank;
+-	dc->hwss.disable_plane = dcn20_disable_plane;
+-	dc->hwss.plane_atomic_disable = dcn20_plane_atomic_disable;
+-	dc->hwss.enable_power_gating_plane = dcn20_enable_power_gating_plane;
+-	dc->hwss.dpp_pg_control = dcn20_dpp_pg_control;
+-	dc->hwss.hubp_pg_control = dcn20_hubp_pg_control;
+-	dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
+-	dc->hwss.disable_vga = dcn20_disable_vga;
+-
+-	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+-		dc->hwss.init_hw = dcn20_fpga_init_hw;
+-		dc->hwss.init_pipes = NULL;
+-	}
+-
+-
+-}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+index 3098f1049ed7..f58b69c1b321 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+@@ -26,90 +26,112 @@
+ #ifndef __DC_HWSS_DCN20_H__
+ #define __DC_HWSS_DCN20_H__
+ 
+-struct dc;
+-
+-void dcn20_hw_sequencer_construct(struct dc *dc);
+-
+-enum dc_status dcn20_enable_stream_timing(
+-		struct pipe_ctx *pipe_ctx,
+-		struct dc_state *context,
+-		struct dc *dc);
+-
+-void dcn20_blank_pixel_data(
++bool dcn20_set_blend_lut(
++	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
++bool dcn20_set_shaper_3dlut(
++	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
++void dcn20_program_front_end_for_ctx(
+ 		struct dc *dc,
+-		struct pipe_ctx *pipe_ctx,
+-		bool blank);
+-
++		struct dc_state *context);
++void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
++bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
++			const struct dc_plane_state *plane_state);
++bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
++			const struct dc_stream_state *stream);
+ void dcn20_program_output_csc(struct dc *dc,
+ 		struct pipe_ctx *pipe_ctx,
+ 		enum dc_color_space colorspace,
+ 		uint16_t *matrix,
+ 		int opp_id);
+-
++void dcn20_enable_stream(struct pipe_ctx *pipe_ctx);
++void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
++		struct dc_link_settings *link_settings);
++void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn20_blank_pixel_data(
++		struct dc *dc,
++		struct pipe_ctx *pipe_ctx,
++		bool blank);
++void dcn20_pipe_control_lock(
++	struct dc *dc,
++	struct pipe_ctx *pipe,
++	bool lock);
++void dcn20_pipe_control_lock_global(
++		struct dc *dc,
++		struct pipe_ctx *pipe,
++		bool lock);
+ void dcn20_prepare_bandwidth(
+ 		struct dc *dc,
+ 		struct dc_state *context);
+-
+ void dcn20_optimize_bandwidth(
+ 		struct dc *dc,
+ 		struct dc_state *context);
+-
+ bool dcn20_update_bandwidth(
+ 		struct dc *dc,
+ 		struct dc_state *context);
+-
++void dcn20_reset_hw_ctx_wrap(
++		struct dc *dc,
++		struct dc_state *context);
++enum dc_status dcn20_enable_stream_timing(
++		struct pipe_ctx *pipe_ctx,
++		struct dc_state *context,
++		struct dc *dc);
++void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn20_init_blank(
++		struct dc *dc,
++		struct timing_generator *tg);
++void dcn20_disable_vga(
++	struct dce_hwseq *hws);
++void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
++void dcn20_enable_power_gating_plane(
++	struct dce_hwseq *hws,
++	bool enable);
++void dcn20_dpp_pg_control(
++		struct dce_hwseq *hws,
++		unsigned int dpp_inst,
++		bool power_on);
++void dcn20_hubp_pg_control(
++		struct dce_hwseq *hws,
++		unsigned int hubp_inst,
++		bool power_on);
++void dcn20_program_triple_buffer(
++	const struct dc *dc,
++	struct pipe_ctx *pipe_ctx,
++	bool enable_triple_buffer);
++void dcn20_enable_writeback(
++		struct dc *dc,
++		const struct dc_stream_status *stream_status,
++		struct dc_writeback_info *wb_info,
++		struct dc_state *context);
+ void dcn20_disable_writeback(
+ 		struct dc *dc,
+ 		unsigned int dwb_pipe_inst);
+-
+-bool dcn20_hwss_wait_for_blank_complete(
+-		struct output_pixel_processor *opp);
+-
+-bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
+-			const struct dc_stream_state *stream);
+-
+-bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
+-			const struct dc_plane_state *plane_state);
+-
++void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
+ bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx);
+-
+-void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);
+-
+-void dcn20_disable_stream(struct pipe_ctx *pipe_ctx);
+-
+-void dcn20_program_tripleBuffer(
+-		const struct dc *dc,
+-		struct pipe_ctx *pipe_ctx,
+-		bool enableTripleBuffer);
+-
+-void dcn20_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx);
+-
+-void dcn20_pipe_control_lock_global(
++void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
++void dcn20_init_vm_ctx(
++		struct dce_hwseq *hws,
+ 		struct dc *dc,
+-		struct pipe_ctx *pipe,
+-		bool lock);
+-void dcn20_setup_gsl_group_as_lock(const struct dc *dc,
+-				struct pipe_ctx *pipe_ctx,
+-				bool enable);
+-void dcn20_dccg_init(struct dce_hwseq *hws);
+-void dcn20_init_blank(
+-	   struct dc *dc,
+-	   struct timing_generator *tg);
+-void dcn20_display_init(struct dc *dc);
+-void dcn20_pipe_control_lock(
+-	struct dc *dc,
+-	struct pipe_ctx *pipe,
+-	bool lock);
+-void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
+-void dcn20_enable_plane(
+-	struct dc *dc,
+-	struct pipe_ctx *pipe_ctx,
+-	struct dc_state *context);
+-bool dcn20_set_blend_lut(
+-	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
+-bool dcn20_set_shaper_3dlut(
+-	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
+-void dcn20_get_mpctree_visual_confirm_color(
++		struct dc_virtual_addr_space_config *va_config,
++		int vmid);
++void dcn20_set_flip_control_gsl(
+ 		struct pipe_ctx *pipe_ctx,
+-		struct tg_color *color);
++		bool flip_immediate);
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++void dcn20_dsc_pg_control(
++		struct dce_hwseq *hws,
++		unsigned int dsc_inst,
++		bool power_on);
++#endif
++void dcn20_fpga_init_hw(struct dc *dc);
++bool dcn20_wait_for_blank_complete(
++		struct output_pixel_processor *opp);
++void dcn20_dccg_init(struct dce_hwseq *hws);
++int dcn20_init_sys_ctx(struct dce_hwseq *hws,
++		struct dc *dc,
++		struct dc_phy_addr_space_config *pa_config);
++
+ #endif /* __DC_HWSS_DCN20_H__ */
++
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+new file mode 100644
+index 000000000000..10493777d192
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+@@ -0,0 +1,131 @@
++/*
++ * Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "dce110/dce110_hw_sequencer.h"
++#include "dcn10/dcn10_hw_sequencer.h"
++#include "dcn20_hwseq.h"
++
++static const struct hw_sequencer_funcs dcn20_funcs = {
++	.program_gamut_remap = dcn10_program_gamut_remap,
++	.init_hw = dcn10_init_hw,
++	.init_pipes = dcn10_init_pipes,
++	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
++	.apply_ctx_for_surface = NULL,
++	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
++	.update_plane_addr = dcn20_update_plane_addr,
++	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
++	.update_dchub = dcn10_update_dchub,
++	.update_mpcc = dcn20_update_mpcc,
++	.update_pending_status = dcn10_update_pending_status,
++	.set_input_transfer_func = dcn20_set_input_transfer_func,
++	.set_output_transfer_func = dcn20_set_output_transfer_func,
++	.program_output_csc = dcn20_program_output_csc,
++	.power_down = dce110_power_down,
++	.enable_accelerated_mode = dce110_enable_accelerated_mode,
++	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
++	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
++	.update_info_frame = dce110_update_info_frame,
++	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
++	.enable_stream = dcn20_enable_stream,
++	.disable_stream = dce110_disable_stream,
++	.unblank_stream = dcn20_unblank_stream,
++	.blank_stream = dce110_blank_stream,
++	.enable_audio_stream = dce110_enable_audio_stream,
++	.disable_audio_stream = dce110_disable_audio_stream,
++	.enable_display_power_gating = dcn10_dummy_display_power_gating,
++	.disable_plane = dcn20_disable_plane,
++	.blank_pixel_data = dcn20_blank_pixel_data,
++	.pipe_control_lock = dcn20_pipe_control_lock,
++	.pipe_control_lock_global = dcn20_pipe_control_lock_global,
++	.prepare_bandwidth = dcn20_prepare_bandwidth,
++	.optimize_bandwidth = dcn20_optimize_bandwidth,
++	.update_bandwidth = dcn20_update_bandwidth,
++	.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
++	.enable_stream_timing = dcn20_enable_stream_timing,
++	.set_drr = dcn10_set_drr,
++	.get_position = dcn10_get_position,
++	.set_static_screen_control = dcn10_set_static_screen_control,
++	.setup_stereo = dcn10_setup_stereo,
++	.set_avmute = dce110_set_avmute,
++	.log_hw_state = dcn10_log_hw_state,
++	.get_hw_state = dcn10_get_hw_state,
++	.clear_status_bits = dcn10_clear_status_bits,
++	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
++	.edp_backlight_control = dce110_edp_backlight_control,
++	.edp_power_control = dce110_edp_power_control,
++	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
++	.set_cursor_position = dcn10_set_cursor_position,
++	.set_cursor_attribute = dcn10_set_cursor_attribute,
++	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
++	.disable_stream_gating = dcn20_disable_stream_gating,
++	.enable_stream_gating = dcn20_enable_stream_gating,
++	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
++	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
++	.set_clock = dcn10_set_clock,
++	.get_clock = dcn10_get_clock,
++	.did_underflow_occur = dcn10_did_underflow_occur,
++	.init_blank = dcn20_init_blank,
++	.disable_vga = dcn20_disable_vga,
++	.bios_golden_init = dcn10_bios_golden_init,
++	.plane_atomic_disable = dcn20_plane_atomic_disable,
++	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
++	.enable_power_gating_plane = dcn20_enable_power_gating_plane,
++	.dpp_pg_control = dcn20_dpp_pg_control,
++	.hubp_pg_control = dcn20_hubp_pg_control,
++	.dsc_pg_control = NULL,
++	.program_triplebuffer = dcn20_program_triple_buffer,
++	.enable_writeback = dcn20_enable_writeback,
++	.disable_writeback = dcn20_disable_writeback,
++	.update_odm = dcn20_update_odm,
++	.dmdata_status_done = dcn20_dmdata_status_done,
++	.program_dmdata_engine = dcn20_program_dmdata_engine,
++	.init_sys_ctx = dcn20_init_sys_ctx,
++	.init_vm_ctx = dcn20_init_vm_ctx,
++	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	.dsc_pg_control = dcn20_dsc_pg_control,
++#else
++	.dsc_pg_control = NULL,
++#endif
++	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
++	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
++	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
++	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
++	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
++	.dccg_init = dcn20_dccg_init,
++	.set_blend_lut = dcn20_set_blend_lut,
++	.set_shaper_3dlut = dcn20_set_shaper_3dlut,
++	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
++};
++
++void dcn20_hw_sequencer_construct(struct dc *dc)
++{
++	dc->hwss = dcn20_funcs;
++
++	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
++		dc->hwss.init_hw = dcn20_fpga_init_hw;
++		dc->hwss.init_pipes = NULL;
++	}
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.h
+new file mode 100644
+index 000000000000..12277797cd71
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.h
+@@ -0,0 +1,33 @@
++/*
++ * Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DC_DCN20_INIT_H__
++#define __DC_DCN20_INIT_H__
++
++struct dc;
++
++void dcn20_hw_sequencer_construct(struct dc *dc);
++
++#endif /* __DC_DCN20_INIT_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+index 0e50dc9b611a..f5854a5d2b76 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+@@ -201,11 +201,11 @@ void optc2_set_dsc_config(struct timing_generator *optc,
+ 		OPTC_DSC_SLICE_WIDTH, dsc_slice_width);
+ }
+ 
+-/**
+- * PTI i think is already done somewhere else for 2ka
+- * (opp?, please double check.
+- * OPTC side only has 1 register to set for PTI_ENABLE)
+- */
++/*TEMP: Need to figure out inheritance model here.*/
++bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
++{
++	return optc1_is_two_pixels_per_containter(timing);
++}
+ 
+ void optc2_set_odm_bypass(struct timing_generator *optc,
+ 		const struct dc_crtc_timing *dc_crtc_timing)
+@@ -219,7 +219,7 @@ void optc2_set_odm_bypass(struct timing_generator *optc,
+ 			OPTC_SEG1_SRC_SEL, 0xf);
+ 	REG_WRITE(OTG_H_TIMING_CNTL, 0);
+ 
+-	h_div_2 = optc1_is_two_pixels_per_containter(dc_crtc_timing);
++	h_div_2 = optc2_is_two_pixels_per_containter(dc_crtc_timing);
+ 	REG_UPDATE(OTG_H_TIMING_CNTL,
+ 			OTG_H_TIMING_DIV_BY2, h_div_2);
+ 	REG_SET(OPTC_MEMORY_CONFIG, 0,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+index 9ae22146d2d8..ac93fbfaee03 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+@@ -107,5 +107,5 @@ void optc2_triplebuffer_unlock(struct timing_generator *optc);
+ void optc2_lock_doublebuffer_disable(struct timing_generator *optc);
+ void optc2_lock_doublebuffer_enable(struct timing_generator *optc);
+ void optc2_program_manual_trigger(struct timing_generator *optc);
+-
++bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);
+ #endif /* __DC_OPTC_DCN20_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 2315da20fd41..b000d5289684 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -26,6 +26,8 @@
+ #include "dm_services.h"
+ #include "dc.h"
+ 
++#include "dcn20_init.h"
++
+ #include "resource.h"
+ #include "include/irq_service_interface.h"
+ #include "dcn20/dcn20_resource.h"
+@@ -1453,7 +1455,7 @@ static void get_pixel_clock_parameters(
+ 
+ 	if (opp_cnt == 4)
+ 		pixel_clk_params->requested_pix_clk_100hz /= 4;
+-	else if (optc1_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
++	else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
+ 		pixel_clk_params->requested_pix_clk_100hz /= 2;
+ 
+ 	if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+index feb7e705e792..5a061e10ef4d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+@@ -1,7 +1,8 @@
+ #
+ # Makefile for DCN21.
+ 
+-DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o dcn21_link_encoder.o
++DCN21 = dcn21_init.o dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o \
++	 dcn21_hwseq.o dcn21_link_encoder.o
+ 
+ CFLAGS_dcn21_resource.o := -mhard-float -msse
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+index b25215cadf85..005894dcabc9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+@@ -28,7 +28,6 @@
+ #include "core_types.h"
+ #include "resource.h"
+ #include "dce/dce_hwseq.h"
+-#include "dcn20/dcn20_hwseq.h"
+ #include "vmid.h"
+ #include "reg_helper.h"
+ #include "hw/clk_mgr.h"
+@@ -61,7 +60,7 @@ static void mmhub_update_page_table_config(struct dcn_hubbub_phys_addr_config *c
+ 
+ }
+ 
+-static int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
++int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
+ {
+ 	struct dcn_hubbub_phys_addr_config config;
+ 
+@@ -82,7 +81,7 @@ static int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_ph
+ 
+ // work around for Renoir s0i3, if register is programmed, bypass golden init.
+ 
+-static bool dcn21_s0i3_golden_init_wa(struct dc *dc)
++bool dcn21_s0i3_golden_init_wa(struct dc *dc)
+ {
+ 	struct dce_hwseq *hws = dc->hwseq;
+ 	uint32_t value = 0;
+@@ -112,11 +111,3 @@ void dcn21_optimize_pwr_state(
+ 			true);
+ }
+ 
+-void dcn21_hw_sequencer_construct(struct dc *dc)
+-{
+-	dcn20_hw_sequencer_construct(dc);
+-	dc->hwss.init_sys_ctx = dcn21_init_sys_ctx;
+-	dc->hwss.s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa;
+-	dc->hwss.optimize_pwr_state = dcn21_optimize_pwr_state;
+-	dc->hwss.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state;
+-}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
+index be67b62e6fb1..2f7b8a220eb9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
+@@ -28,6 +28,18 @@
+ 
+ struct dc;
+ 
+-void dcn21_hw_sequencer_construct(struct dc *dc);
++int dcn21_init_sys_ctx(struct dce_hwseq *hws,
++		struct dc *dc,
++		struct dc_phy_addr_space_config *pa_config);
++
++bool dcn21_s0i3_golden_init_wa(struct dc *dc);
++
++void dcn21_exit_optimized_pwr_state(
++		const struct dc *dc,
++		struct dc_state *context);
++
++void dcn21_optimize_pwr_state(
++		const struct dc *dc,
++		struct dc_state *context);
+ 
+ #endif /* __DC_HWSS_DCN21_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+new file mode 100644
+index 000000000000..cbd55037a04a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+@@ -0,0 +1,135 @@
++/*
++ * Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#include "dce110/dce110_hw_sequencer.h"
++#include "dcn10/dcn10_hw_sequencer.h"
++#include "dcn20/dcn20_hwseq.h"
++#include "dcn21_hwseq.h"
++
++static const struct hw_sequencer_funcs dcn21_funcs = {
++	.program_gamut_remap = dcn10_program_gamut_remap,
++	.init_hw = dcn10_init_hw,
++	.init_pipes = dcn10_init_pipes,
++	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
++	.apply_ctx_for_surface = NULL,
++	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
++	.update_plane_addr = dcn20_update_plane_addr,
++	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
++	.update_dchub = dcn10_update_dchub,
++	.update_mpcc = dcn20_update_mpcc,
++	.update_pending_status = dcn10_update_pending_status,
++	.set_input_transfer_func = dcn20_set_input_transfer_func,
++	.set_output_transfer_func = dcn20_set_output_transfer_func,
++	.program_output_csc = dcn20_program_output_csc,
++	.power_down = dce110_power_down,
++	.enable_accelerated_mode = dce110_enable_accelerated_mode,
++	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
++	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
++	.update_info_frame = dce110_update_info_frame,
++	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
++	.enable_stream = dcn20_enable_stream,
++	.disable_stream = dce110_disable_stream,
++	.unblank_stream = dcn20_unblank_stream,
++	.blank_stream = dce110_blank_stream,
++	.enable_audio_stream = dce110_enable_audio_stream,
++	.disable_audio_stream = dce110_disable_audio_stream,
++	.enable_display_power_gating = dcn10_dummy_display_power_gating,
++	.disable_plane = dcn20_disable_plane,
++	.blank_pixel_data = dcn20_blank_pixel_data,
++	.pipe_control_lock = dcn20_pipe_control_lock,
++	.pipe_control_lock_global = dcn20_pipe_control_lock_global,
++	.prepare_bandwidth = dcn20_prepare_bandwidth,
++	.optimize_bandwidth = dcn20_optimize_bandwidth,
++	.update_bandwidth = dcn20_update_bandwidth,
++	.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
++	.enable_stream_timing = dcn20_enable_stream_timing,
++	.set_drr = dcn10_set_drr,
++	.get_position = dcn10_get_position,
++	.set_static_screen_control = dcn10_set_static_screen_control,
++	.setup_stereo = dcn10_setup_stereo,
++	.set_avmute = dce110_set_avmute,
++	.log_hw_state = dcn10_log_hw_state,
++	.get_hw_state = dcn10_get_hw_state,
++	.clear_status_bits = dcn10_clear_status_bits,
++	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
++	.edp_backlight_control = dce110_edp_backlight_control,
++	.edp_power_control = dce110_edp_power_control,
++	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
++	.set_cursor_position = dcn10_set_cursor_position,
++	.set_cursor_attribute = dcn10_set_cursor_attribute,
++	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
++	.disable_stream_gating = dcn20_disable_stream_gating,
++	.enable_stream_gating = dcn20_enable_stream_gating,
++	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
++	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
++	.set_clock = dcn10_set_clock,
++	.get_clock = dcn10_get_clock,
++	.did_underflow_occur = dcn10_did_underflow_occur,
++	.init_blank = dcn20_init_blank,
++	.disable_vga = dcn20_disable_vga,
++	.bios_golden_init = dcn10_bios_golden_init,
++	.plane_atomic_disable = dcn20_plane_atomic_disable,
++	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
++	.enable_power_gating_plane = dcn20_enable_power_gating_plane,
++	.dpp_pg_control = dcn20_dpp_pg_control,
++	.hubp_pg_control = dcn20_hubp_pg_control,
++	.dsc_pg_control = NULL,
++	.program_triplebuffer = dcn20_program_triple_buffer,
++	.enable_writeback = dcn20_enable_writeback,
++	.disable_writeback = dcn20_disable_writeback,
++	.update_odm = dcn20_update_odm,
++	.dmdata_status_done = dcn20_dmdata_status_done,
++	.program_dmdata_engine = dcn20_program_dmdata_engine,
++	.init_sys_ctx = dcn21_init_sys_ctx,
++	.init_vm_ctx = dcn20_init_vm_ctx,
++	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
++	.dsc_pg_control = dcn20_dsc_pg_control,
++#else
++	.dsc_pg_control = NULL,
++#endif
++	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
++	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
++	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
++	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
++	.s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa,
++	.optimize_pwr_state = dcn21_optimize_pwr_state,
++	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
++	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
++	.dccg_init = dcn20_dccg_init,
++	.set_blend_lut = dcn20_set_blend_lut,
++	.set_shaper_3dlut = dcn20_set_shaper_3dlut,
++	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
++};
++
++void dcn21_hw_sequencer_construct(struct dc *dc)
++{
++	dc->hwss = dcn21_funcs;
++
++	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
++		dc->hwss.init_hw = dcn20_fpga_init_hw;
++		dc->hwss.init_pipes = NULL;
++	}
++}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.h
+new file mode 100644
+index 000000000000..3ed24292648a
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.h
+@@ -0,0 +1,33 @@
++/*
++ * Copyright 2016 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DC_DCN21_INIT_H__
++#define __DC_DCN21_INIT_H__
++
++struct dc;
++
++void dcn21_hw_sequencer_construct(struct dc *dc);
++
++#endif /* __DC_DCN20_INIT_H__ */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index f68f643a82af..260471ac20c2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -26,6 +26,8 @@
+ #include "dm_services.h"
+ #include "dc.h"
+ 
++#include "dcn21_init.h"
++
+ #include "resource.h"
+ #include "include/irq_service_interface.h"
+ #include "dcn20/dcn20_resource.h"
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index 23e3a541b7c9..937a02d02f18 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -148,11 +148,11 @@ struct hw_sequencer_funcs {
+ 	void (*update_pending_status)(
+ 			struct pipe_ctx *pipe_ctx);
+ 
+-	bool (*set_input_transfer_func)(
++	bool (*set_input_transfer_func)(struct dc *dc,
+ 				struct pipe_ctx *pipe_ctx,
+ 				const struct dc_plane_state *plane_state);
+ 
+-	bool (*set_output_transfer_func)(
++	bool (*set_output_transfer_func)(struct dc *dc,
+ 				struct pipe_ctx *pipe_ctx,
+ 				const struct dc_stream_state *stream);
+ 
+@@ -279,8 +279,10 @@ struct hw_sequencer_funcs {
+ 	void (*set_cursor_attribute)(struct pipe_ctx *pipe);
+ 	void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);
+ 
+-	void (*setup_periodic_interrupt)(struct pipe_ctx *pipe_ctx, enum vline_select vline);
+-	void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx);
++	void (*setup_periodic_interrupt)(struct dc *dc,
++			struct pipe_ctx *pipe_ctx,
++			enum vline_select vline);
++	void (*setup_vupdate_interrupt)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+ 	bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+ 
+ 	void (*init_blank)(struct dc *dc, struct timing_generator *tg);
+@@ -340,6 +342,36 @@ struct hw_sequencer_funcs {
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ 	bool (*s0i3_golden_init_wa)(struct dc *dc);
+ #endif
++
++	void (*get_surface_visual_confirm_color)(
++			const struct pipe_ctx *pipe_ctx,
++			struct tg_color *color);
++
++	void (*get_hdr_visual_confirm_color)(
++			struct pipe_ctx *pipe_ctx,
++			struct tg_color *color);
++
++	void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);
++
++	void (*verify_allow_pstate_change_high)(struct dc *dc);
++
++	void (*program_pipe)(
++			struct dc *dc,
++			struct pipe_ctx *pipe_ctx,
++			struct dc_state *context);
++
++	bool (*wait_for_blank_complete)(
++			struct output_pixel_processor *opp);
++
++	void (*dccg_init)(struct dce_hwseq *hws);
++
++	bool (*set_blend_lut)(
++		struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
++
++	bool (*set_shaper_3dlut)(
++		struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
++
++	int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx);
+ };
+ 
+ void color_space_to_black_color(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4654-drm-amd-display-Use-a-temporary-copy-of-the-current-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4654-drm-amd-display-Use-a-temporary-copy-of-the-current-.patch
new file mode 100644
index 00000000..1a756d53
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4654-drm-amd-display-Use-a-temporary-copy-of-the-current-.patch
@@ -0,0 +1,87 @@
+From 0021da190e287eb7c2b8dd43b32f8404f7dd75bb Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Mon, 4 Nov 2019 17:44:23 -0500
+Subject: [PATCH 4654/4736] drm/amd/display: Use a temporary copy of the
+ current state when updating DSC config
+
+[why]
+When updating DSC config, a new config has to be validated before proceeding
+with applying the update. Validation, however, modifies the current state.
+This means DSC config validation would affect pipe re-assignment, causing
+intermittent screen corruption issues when ODM is required for DSC.
+
+[how]
+- Use a copy of the current state for modified DSC config validation
+- Set the update type to FULL_UPDATE to correctly validate and set the
+  actual state used for committing the streams
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 33 +++++++++++++++++++-----
+ 1 file changed, 26 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 562a24f4553f..584127a5ec18 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1672,6 +1672,11 @@ static enum surface_update_type check_update_surfaces_for_stream(
+ 
+ 		if (stream_update->output_csc_transform || stream_update->output_color_space)
+ 			su_flags->bits.out_csc = 1;
++
++#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
++		if (stream_update->dsc_config)
++			overall_type = UPDATE_TYPE_FULL;
++#endif
+ 	}
+ 
+ 	for (i = 0 ; i < surface_count; i++) {
+@@ -1863,8 +1868,10 @@ static void copy_surface_update_to_plane(
+ static void copy_stream_update_to_stream(struct dc *dc,
+ 					 struct dc_state *context,
+ 					 struct dc_stream_state *stream,
+-					 const struct dc_stream_update *update)
++					 struct dc_stream_update *update)
+ {
++	struct dc_context *dc_ctx = dc->ctx;
++
+ 	if (update == NULL || stream == NULL)
+ 		return;
+ 
+@@ -1941,12 +1948,24 @@ static void copy_stream_update_to_stream(struct dc *dc,
+ 		uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
+ 				       update->dsc_config->num_slices_v != 0);
+ 
+-		stream->timing.dsc_cfg = *update->dsc_config;
+-		stream->timing.flags.DSC = enable_dsc;
+-		if (!dc->res_pool->funcs->validate_bandwidth(dc, context,
+-							     true)) {
+-			stream->timing.dsc_cfg = old_dsc_cfg;
+-			stream->timing.flags.DSC = old_dsc_enabled;
++		/* Use temporarry context for validating new DSC config */
++		struct dc_state *dsc_validate_context = dc_create_state(dc);
++
++		if (dsc_validate_context) {
++			dc_resource_state_copy_construct(dc->current_state, dsc_validate_context);
++
++			stream->timing.dsc_cfg = *update->dsc_config;
++			stream->timing.flags.DSC = enable_dsc;
++			if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
++				stream->timing.dsc_cfg = old_dsc_cfg;
++				stream->timing.flags.DSC = old_dsc_enabled;
++				update->dsc_config = false;
++			}
++
++			dc_release_state(dsc_validate_context);
++		} else {
++			DC_ERROR("Failed to allocate new validate context for DSC change\n");
++			update->dsc_config = false;
+ 		}
+ 	}
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4655-drm-amd-display-Use-NULL-for-pointer-assignment-in-c.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4655-drm-amd-display-Use-NULL-for-pointer-assignment-in-c.patch
new file mode 100644
index 00000000..fa09c7df
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4655-drm-amd-display-Use-NULL-for-pointer-assignment-in-c.patch
@@ -0,0 +1,53 @@
+From 525c62d8f942505378461536185b29d6e35c682d Mon Sep 17 00:00:00 2001
+From: Nathan Chancellor <natechancellor@gmail.com>
+Date: Sat, 23 Nov 2019 12:36:39 -0700
+Subject: [PATCH 4655/4736] drm/amd/display: Use NULL for pointer assignment in
+ copy_stream_update_to_stream
+
+Clang warns:
+
+../drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:1965:26: warning:
+expression which evaluates to zero treated as a null pointer constant of
+type 'struct dc_dsc_config *' [-Wnon-literal-null-conversion]
+                                update->dsc_config = false;
+                                                     ^~~~~
+../drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:1971:25: warning:
+expression which evaluates to zero treated as a null pointer constant of
+type 'struct dc_dsc_config *' [-Wnon-literal-null-conversion]
+                        update->dsc_config = false;
+                                             ^~~~~
+2 warnings generated.
+
+Fixes: f6fe4053b91f ("drm/amd/display: Use a temporary copy of the current state when updating DSC config")
+Link: https://github.com/ClangBuiltLinux/linux/issues/777
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 584127a5ec18..09184adfccc8 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1959,13 +1959,13 @@ static void copy_stream_update_to_stream(struct dc *dc,
+ 			if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
+ 				stream->timing.dsc_cfg = old_dsc_cfg;
+ 				stream->timing.flags.DSC = old_dsc_enabled;
+-				update->dsc_config = false;
++				update->dsc_config = NULL;
+ 			}
+ 
+ 			dc_release_state(dsc_validate_context);
+ 		} else {
+ 			DC_ERROR("Failed to allocate new validate context for DSC change\n");
+-			update->dsc_config = false;
++			update->dsc_config = NULL;
+ 		}
+ 	}
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4656-drm-amdgpu-add-cache-flush-workaround-to-gfx8-emit_f.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4656-drm-amdgpu-add-cache-flush-workaround-to-gfx8-emit_f.patch
new file mode 100644
index 00000000..e6f0a58d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4656-drm-amdgpu-add-cache-flush-workaround-to-gfx8-emit_f.patch
@@ -0,0 +1,66 @@
+From eea79ae0d4fbca5c98b76b1d4e904de0e47ce24a Mon Sep 17 00:00:00 2001
+From: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
+Date: Thu, 28 Nov 2019 12:08:58 +0100
+Subject: [PATCH 4656/4736] drm/amdgpu: add cache flush workaround to gfx8
+ emit_fence
+
+The same workaround is used for gfx7.
+Both PAL and Mesa use it for gfx8 too, so port this commit to
+gfx_v8_0_ring_emit_fence_gfx.
+
+Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 22 +++++++++++++++++++---
+ 1 file changed, 19 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index 387e95319594..e379b1de50ba 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -6131,7 +6131,23 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
+ 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
+ 	bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
+ 
+-	/* EVENT_WRITE_EOP - flush caches, send int */
++	/* Workaround for cache flush problems. First send a dummy EOP
++	 * event down the pipe with seq one below.
++	 */
++	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
++	amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
++				 EOP_TC_ACTION_EN |
++				 EOP_TC_WB_ACTION_EN |
++				 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
++				 EVENT_INDEX(5)));
++	amdgpu_ring_write(ring, addr & 0xfffffffc);
++	amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
++				DATA_SEL(1) | INT_SEL(0));
++	amdgpu_ring_write(ring, lower_32_bits(seq - 1));
++	amdgpu_ring_write(ring, upper_32_bits(seq - 1));
++
++	/* Then send the real EOP event down the pipe:
++	 * EVENT_WRITE_EOP - flush caches, send int */
+ 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
+ 	amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
+ 				 EOP_TC_ACTION_EN |
+@@ -6874,7 +6890,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
+ 		5 +  /* COND_EXEC */
+ 		7 +  /* PIPELINE_SYNC */
+ 		VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */
+-		8 +  /* FENCE for VM_FLUSH */
++		12 +  /* FENCE for VM_FLUSH */
+ 		20 + /* GDS switch */
+ 		4 + /* double SWITCH_BUFFER,
+ 		       the first COND_EXEC jump to the place just
+@@ -6886,7 +6902,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
+ 		31 + /*	DE_META */
+ 		3 + /* CNTX_CTRL */
+ 		5 + /* HDP_INVL */
+-		8 + 8 + /* FENCE x2 */
++		12 + 12 + /* FENCE x2 */
+ 		2, /* SWITCH_BUFFER */
+ 	.emit_ib_size =	4, /* gfx_v8_0_ring_emit_ib_gfx */
+ 	.emit_ib = gfx_v8_0_ring_emit_ib_gfx,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4657-drm-amdgpu-remove-ras-global-recovery-handling-from-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4657-drm-amdgpu-remove-ras-global-recovery-handling-from-.patch
new file mode 100644
index 00000000..8677b689
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4657-drm-amdgpu-remove-ras-global-recovery-handling-from-.patch
@@ -0,0 +1,36 @@
+From 2a6a1ea67ecc93bb2e61b755093707cd1bbce018 Mon Sep 17 00:00:00 2001
+From: Le Ma <Le.Ma@amd.com>
+Date: Tue, 22 Oct 2019 02:41:26 +0800
+Subject: [PATCH 4657/4736] drm/amdgpu: remove ras global recovery handling
+ from ras_controller_int handler
+
+v2: add notification when ras controller interrupt generates
+
+Change-Id: Ic03e42e9d1c4dab1fa7f4817c191a16e485b48a9
+Signed-off-by: Le Ma <Le.Ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index 0db458f9fafc..25231d699341 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -324,7 +324,12 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device
+ 						RAS_CNTLR_INTERRUPT_CLEAR, 1);
+ 		WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
+ 
+-		amdgpu_ras_global_ras_isr(adev);
++		DRM_WARN("RAS controller interrupt triggered by NBIF error\n");
++
++		/* ras_controller_int is dedicated for nbif ras error,
++		 * not the global interrupt for sync flood
++		 */
++		amdgpu_ras_reset_gpu(adev, true);
+ 	}
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4658-drm-amdgpu-export-amdgpu_ras_find_obj-to-use-externa.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4658-drm-amdgpu-export-amdgpu_ras_find_obj-to-use-externa.patch
new file mode 100644
index 00000000..a5a5447c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4658-drm-amdgpu-export-amdgpu_ras_find_obj-to-use-externa.patch
@@ -0,0 +1,56 @@
+From c02c16055c57c778464896d81d3d17932c3c4b77 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Mon, 25 Nov 2019 12:26:09 +0800
+Subject: [PATCH 4658/4736] drm/amdgpu: export amdgpu_ras_find_obj to use
+ externally
+
+Change it to external interface.
+
+Change-Id: I2ab61f149c84a05a6f883a4c7415ea8012ec03a6
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 +----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 3 +++
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+index bbd4fd5d7850..93294782e8c2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+@@ -196,9 +196,6 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
+ 	return 0;
+ }
+ 
+-static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
+-		struct ras_common_if *head);
+-
+ /**
+  * DOC: AMDGPU RAS debugfs control interface
+  *
+@@ -443,7 +440,7 @@ static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
+ }
+ 
+ /* return an obj equal to head, or the first when head is NULL */
+-static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
++struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
+ 		struct ras_common_if *head)
+ {
+ 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index f80fd3428c98..a2c1ac1b9572 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -611,6 +611,9 @@ int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
+ int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
+ 		struct ras_dispatch_if *info);
+ 
++struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
++		struct ras_common_if *head);
++
+ extern atomic_t amdgpu_ras_in_intr;
+ 
+ static inline bool amdgpu_ras_intr_triggered(void)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4659-drm-amdgpu-clear-ras-controller-status-registers-whe.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4659-drm-amdgpu-clear-ras-controller-status-registers-whe.patch
new file mode 100644
index 00000000..55c78e06
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4659-drm-amdgpu-clear-ras-controller-status-registers-whe.patch
@@ -0,0 +1,55 @@
+From 995d14032141d5875eb3578387bce42f2deabcfc Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 22 Nov 2019 17:56:47 +0800
+Subject: [PATCH 4659/4736] drm/amdgpu: clear ras controller status registers
+ when interrupt occurs
+
+To fix issue that ras controller interrupt cannot be triggered anymore after
+one time nbif uncorrectable error. And error count is stored in nbif ras object
+for query.
+
+Change-Id: Iba482c169fdff3e9c390072c0289a622a522133c
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index 25231d699341..9a3a65a0691c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -52,6 +52,9 @@
+ #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK          0x00000FFCL
+ #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK            0x001F0000L
+ 
++static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
++					void *ras_error_status);
++
+ static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
+ {
+ 	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
+@@ -314,6 +317,7 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
+ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
+ {
+ 	uint32_t bif_doorbell_intr_cntl;
++	struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);
+ 
+ 	bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
+ 	if (REG_GET_FIELD(bif_doorbell_intr_cntl,
+@@ -324,6 +328,12 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device
+ 						RAS_CNTLR_INTERRUPT_CLEAR, 1);
+ 		WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
+ 
++		/*
++		 * clear error status after ras_controller_intr according to
++		 * hw team and count ue number for query
++		 */
++		nbio_v7_4_query_ras_error_count(adev, &obj->err_data);
++
+ 		DRM_WARN("RAS controller interrupt triggered by NBIF error\n");
+ 
+ 		/* ras_controller_int is dedicated for nbif ras error,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4660-drm-amdgpu-clear-uncorrectable-parity-error-status-b.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4660-drm-amdgpu-clear-uncorrectable-parity-error-status-b.patch
new file mode 100644
index 00000000..c4c18944
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4660-drm-amdgpu-clear-uncorrectable-parity-error-status-b.patch
@@ -0,0 +1,56 @@
+From f7af664bf62fc3f66ac1435165116700552b4c60 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 22 Nov 2019 18:39:11 +0800
+Subject: [PATCH 4660/4736] drm/amdgpu: clear uncorrectable parity error status
+ bit
+
+This should be cleared during every nbif uncorrectable error cleanup work.
+
+Change-Id: If5de1fa2779d012ad8b20de03e19251d0d590fa2
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+index 9a3a65a0691c..bb701dbfd472 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+@@ -482,10 +482,12 @@ static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *a
+ 	return 0;
+ }
+ 
++#define smnPARITY_ERROR_STATUS_UNCORR_GRP2	0x13a20030
++
+ static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
+ 					void *ras_error_status)
+ {
+-	uint32_t global_sts, central_sts, int_eoi;
++	uint32_t global_sts, central_sts, int_eoi, parity_sts;
+ 	uint32_t corr, fatal, non_fatal;
+ 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
+ 
+@@ -494,6 +496,7 @@ static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
+ 	fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal);
+ 	non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO,
+ 				ParityErrNonFatal);
++	parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2);
+ 
+ 	if (corr)
+ 		err_data->ce_count++;
+@@ -505,6 +508,11 @@ static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
+ 		/* clear error status register */
+ 		WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts);
+ 
++		if (fatal)
++			/* clear parity fatal error indication field */
++			WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2,
++				    parity_sts);
++
+ 		if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS,
+ 				BIFL_RasContller_Intr_Recv)) {
+ 			/* clear interrupt status register */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4661-drm-amdgpu-enable-disable-doorbell-interrupt-in-baco.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4661-drm-amdgpu-enable-disable-doorbell-interrupt-in-baco.patch
new file mode 100644
index 00000000..a71c7c69
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4661-drm-amdgpu-enable-disable-doorbell-interrupt-in-baco.patch
@@ -0,0 +1,85 @@
+From 2813c4e0bbdd1666e3d0f13248861d08d61c548f Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Tue, 26 Nov 2019 17:24:56 +0800
+Subject: [PATCH 4661/4736] drm/amdgpu: enable/disable doorbell interrupt in
+ baco entry/exit helper
+
+This operation is needed when baco entry/exit for ras recovery
+
+Change-Id: I535c7231693f3138a8e3d5acd55672e2ac68232f
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 ++++++++++++-------
+ 1 file changed, 12 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index db80dd97f0ef..863590e169ac 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -4338,10 +4338,14 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
+ int amdgpu_device_baco_enter(struct drm_device *dev)
+ {
+ 	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+ 
+ 	if (!amdgpu_device_supports_baco(adev->ddev))
+ 		return -ENOTSUPP;
+ 
++	if (ras && ras->supported)
++		adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
++
+ 	if (is_support_sw_smu(adev)) {
+ 		struct smu_context *smu = &adev->smu;
+ 		int ret;
+@@ -4349,8 +4353,6 @@ int amdgpu_device_baco_enter(struct drm_device *dev)
+ 		ret = smu_baco_enter(smu);
+ 		if (ret)
+ 			return ret;
+-
+-		return 0;
+ 	} else {
+ 		void *pp_handle = adev->powerplay.pp_handle;
+ 		const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+@@ -4361,14 +4363,15 @@ int amdgpu_device_baco_enter(struct drm_device *dev)
+ 		/* enter BACO state */
+ 		if (pp_funcs->set_asic_baco_state(pp_handle, 1))
+ 			return -EIO;
+-
+-		return 0;
+ 	}
++
++	return 0;
+ }
+ 
+ int amdgpu_device_baco_exit(struct drm_device *dev)
+ {
+ 	struct amdgpu_device *adev = dev->dev_private;
++	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+ 
+ 	if (!amdgpu_device_supports_baco(adev->ddev))
+ 		return -ENOTSUPP;
+@@ -4381,7 +4384,6 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
+ 		if (ret)
+ 			return ret;
+ 
+-		return 0;
+ 	} else {
+ 		void *pp_handle = adev->powerplay.pp_handle;
+ 		const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+@@ -4392,7 +4394,10 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
+ 		/* exit BACO state */
+ 		if (pp_funcs->set_asic_baco_state(pp_handle, 0))
+ 			return -EIO;
+-
+-		return 0;
+ 	}
++
++	if (ras && ras->supported)
++		adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
++
++	return 0;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4662-drm-amdgpu-add-concurrent-baco-reset-support-for-XGM.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4662-drm-amdgpu-add-concurrent-baco-reset-support-for-XGM.patch
new file mode 100644
index 00000000..b549c229
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4662-drm-amdgpu-add-concurrent-baco-reset-support-for-XGM.patch
@@ -0,0 +1,182 @@
+From 2d2a5a052ea8e4ada3cfabafd23a9e1b896a23ee Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Tue, 26 Nov 2019 22:12:31 +0800
+Subject: [PATCH 4662/4736] drm/amdgpu: add concurrent baco reset support for
+ XGMI
+
+Currently each XGMI node reset wq does not run in parrallel if bound to same
+cpu. Make change to bound the xgmi_reset_work item to different cpus.
+
+XGMI requires all nodes enter into baco within very close proximity before
+any node exit baco. So schedule the xgmi_reset_work wq twice for enter/exit
+baco respectively.
+
+To use baco for XGMI, PMFW supported for baco on XGMI needs to be involved.
+
+The case that PSP reset and baco reset coexist within an XGMI hive never exist
+and is not in the consideration.
+
+v2: define use_baco flag to simplify the code for xgmi baco sequence
+
+Change-Id: I9c08cf90134f940b42e20d2129ff87fba761c532
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  2 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 82 ++++++++++++++++++----
+ 2 files changed, 72 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 4eddee90553b..566ae8bf2ba7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1040,6 +1040,8 @@ struct amdgpu_device {
+ 
+ 	bool                            pm_sysfs_en;
+ 	bool                            ucode_sysfs_en;
++
++	bool				in_baco;
+ };
+ 
+ static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 863590e169ac..2ca9d556c084 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -2663,7 +2663,13 @@ static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
+ 	struct amdgpu_device *adev =
+ 		container_of(__work, struct amdgpu_device, xgmi_reset_work);
+ 
+-	adev->asic_reset_res =  amdgpu_asic_reset(adev);
++	if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
++		adev->asic_reset_res = (adev->in_baco == false) ?
++				amdgpu_device_baco_enter(adev->ddev) :
++				amdgpu_device_baco_exit(adev->ddev);
++	else
++		adev->asic_reset_res = amdgpu_asic_reset(adev);
++
+ 	if (adev->asic_reset_res)
+ 		DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
+ 			 adev->asic_reset_res, adev->ddev->unique);
+@@ -3795,13 +3801,18 @@ static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
+ 	return r;
+ }
+ 
+-static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
++static int amdgpu_do_asic_reset(struct amdgpu_device *adev,
++			       struct amdgpu_hive_info *hive,
+ 			       struct list_head *device_list_handle,
+ 			       bool *need_full_reset_arg)
+ {
+ 	struct amdgpu_device *tmp_adev = NULL;
+ 	bool need_full_reset = *need_full_reset_arg, vram_lost = false;
+ 	int r = 0;
++	int cpu = smp_processor_id();
++	bool use_baco =
++		(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) ?
++		true : false;
+ 
+ 	/*
+ 	 * ASIC reset has to be done on all HGMI hive nodes ASAP
+@@ -3809,21 +3820,24 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
+ 	 */
+ 	if (need_full_reset) {
+ 		list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
+-			/* For XGMI run all resets in parallel to speed up the process */
++			/*
++			 * For XGMI run all resets in parallel to speed up the
++			 * process by scheduling the highpri wq on different
++			 * cpus. For XGMI with baco reset, all nodes must enter
++			 * baco within close proximity before anyone exit.
++			 */
+ 			if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
+-				if (!queue_work(system_highpri_wq, &tmp_adev->xgmi_reset_work))
++				if (!queue_work_on(cpu, system_highpri_wq,
++						   &tmp_adev->xgmi_reset_work))
+ 					r = -EALREADY;
++				cpu = cpumask_next(cpu, cpu_online_mask);
+ 			} else
+ 				r = amdgpu_asic_reset(tmp_adev);
+-
+-			if (r) {
+-				DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s",
+-					 r, tmp_adev->ddev->unique);
++			if (r)
+ 				break;
+-			}
+ 		}
+ 
+-		/* For XGMI wait for all PSP resets to complete before proceed */
++		/* For XGMI wait for all work to complete before proceed */
+ 		if (!r) {
+ 			list_for_each_entry(tmp_adev, device_list_handle,
+ 					    gmc.xgmi.head) {
+@@ -3832,11 +3846,54 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
+ 					r = tmp_adev->asic_reset_res;
+ 					if (r)
+ 						break;
++					if (use_baco)
++						tmp_adev->in_baco = true;
+ 				}
+ 			}
+ 		}
+-	}
+ 
++		/*
++		 * For XGMI with baco reset, need exit baco phase by scheduling
++		 * xgmi_reset_work one more time. PSP reset and sGPU skips this
++		 * phase. Not assume the situation that PSP reset and baco reset
++		 * coexist within an XGMI hive.
++		 */
++
++		if (!r && use_baco) {
++			cpu = smp_processor_id();
++			list_for_each_entry(tmp_adev, device_list_handle,
++					    gmc.xgmi.head) {
++				if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
++					if (!queue_work_on(cpu,
++						system_highpri_wq,
++						&tmp_adev->xgmi_reset_work))
++						r = -EALREADY;
++					if (r)
++						break;
++					cpu = cpumask_next(cpu, cpu_online_mask);
++				}
++			}
++		}
++
++		if (!r && use_baco) {
++			list_for_each_entry(tmp_adev, device_list_handle,
++					    gmc.xgmi.head) {
++				if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
++					flush_work(&tmp_adev->xgmi_reset_work);
++					r = tmp_adev->asic_reset_res;
++					if (r)
++						break;
++					tmp_adev->in_baco = false;
++				}
++			}
++		}
++
++		if (r) {
++			DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s",
++				 r, tmp_adev->ddev->unique);
++			goto end;
++		}
++	}
+ 
+ 	list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
+ 		if (need_full_reset) {
+@@ -4121,7 +4178,8 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 		if (r)
+ 			adev->asic_reset_res = r;
+ 	} else {
+-		r  = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset);
++		r  = amdgpu_do_asic_reset(adev, hive, device_list_handle,
++					  &need_full_reset);
+ 		if (r && r == -EAGAIN)
+ 			goto retry;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4663-drm-amdgpu-support-full-gpu-reset-workflow-when-ras-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4663-drm-amdgpu-support-full-gpu-reset-workflow-when-ras-.patch
new file mode 100644
index 00000000..512f648a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4663-drm-amdgpu-support-full-gpu-reset-workflow-when-ras-.patch
@@ -0,0 +1,86 @@
+From f8258870fb3346e5920c15901858da7e88a7d29c Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Wed, 27 Nov 2019 13:17:17 +0800
+Subject: [PATCH 4663/4736] drm/amdgpu: support full gpu reset workflow when
+ ras err_event_athub occurs
+
+This athub fatal error can be recovered by baco without system-level reboot,
+so add a mode to use baco for the recovery. Not affect the default psp reset
+situations for now.
+
+Change-Id: Ib17f2a39254ff6b0473a785752adfdfea79d0e0d
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 17 +++++++++++------
+ 1 file changed, 11 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 2ca9d556c084..e20d324a6d90 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -4026,12 +4026,15 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 	struct amdgpu_device *tmp_adev = NULL;
+ 	int i, r = 0;
+ 	bool in_ras_intr = amdgpu_ras_intr_triggered();
++	bool use_baco =
++		(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) ?
++		true : false;
+ 
+ 	/*
+ 	 * Flush RAM to disk so that after reboot
+ 	 * the user can read log and see why the system rebooted.
+ 	 */
+-	if (in_ras_intr && amdgpu_ras_get_context(adev)->reboot) {
++	if (in_ras_intr && !use_baco && amdgpu_ras_get_context(adev)->reboot) {
+ 
+ 		DRM_WARN("Emergency reboot.");
+ 
+@@ -4042,7 +4045,8 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 	need_full_reset = job_signaled = false;
+ 	INIT_LIST_HEAD(&device_list);
+ 
+-	dev_info(adev->dev, "GPU %s begin!\n", in_ras_intr ? "jobs stop":"reset");
++	dev_info(adev->dev, "GPU %s begin!\n",
++		(in_ras_intr && !use_baco) ? "jobs stop":"reset");
+ 
+ 	cancel_delayed_work_sync(&adev->delayed_init_work);
+ 
+@@ -4109,7 +4113,8 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 		amdgpu_unregister_gpu_instance(tmp_adev);
+ 
+ 		/* disable ras on ALL IPs */
+-		if (!in_ras_intr && amdgpu_device_ip_need_full_reset(tmp_adev))
++		if (!(in_ras_intr && !use_baco) &&
++		      amdgpu_device_ip_need_full_reset(tmp_adev))
+ 			amdgpu_ras_suspend(tmp_adev);
+ 
+ 		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
+@@ -4120,13 +4125,13 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ 
+ 			drm_sched_stop(&ring->sched, job ? &job->base : NULL);
+ 
+-			if (in_ras_intr)
++			if (in_ras_intr && !use_baco)
+ 				amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
+ 		}
+ 	}
+ 
+ 
+-	if (in_ras_intr)
++	if (in_ras_intr && !use_baco)
+ 		goto skip_sched_resume;
+ 
+ 	/*
+@@ -4220,7 +4225,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ skip_sched_resume:
+ 	list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
+ 		/*unlock kfd: SRIOV would do it separately */
+-		if (!in_ras_intr && !amdgpu_sriov_vf(tmp_adev))
++		if (!(in_ras_intr && !use_baco) && !amdgpu_sriov_vf(tmp_adev))
+ 	                amdgpu_amdkfd_post_reset(tmp_adev);
+ 		amdgpu_device_unlock_adev(tmp_adev);
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4664-drm-amdgpu-clear-err_event_athub-flag-after-reset-ex.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4664-drm-amdgpu-clear-err_event_athub-flag-after-reset-ex.patch
new file mode 100644
index 00000000..faeca608
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4664-drm-amdgpu-clear-err_event_athub-flag-after-reset-ex.patch
@@ -0,0 +1,52 @@
+From 5b46dfbb56ac49aece9d1a2f6175e7b9ef75e083 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Fri, 25 Oct 2019 17:19:38 +0800
+Subject: [PATCH 4664/4736] drm/amdgpu: clear err_event_athub flag after reset
+ exit
+
+Otherwise next err_event_athub error cannot call gpu reset. And following
+resume sequence will not be affected by this flag.
+
+v2: create function to clear amdgpu_ras_in_intr for modularity of ras driver
+
+Change-Id: I5cd293f30f23876bf2a1860681bcb50f47713ecd
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h    | 5 +++++
+ 2 files changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index e20d324a6d90..7bedbeb12627 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3895,6 +3895,9 @@ static int amdgpu_do_asic_reset(struct amdgpu_device *adev,
+ 		}
+ 	}
+ 
++	if (!r && amdgpu_ras_intr_triggered())
++		amdgpu_ras_intr_cleared();
++
+ 	list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
+ 		if (need_full_reset) {
+ 			/* post card */
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+index a2c1ac1b9572..d4ade4739245 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+@@ -621,6 +621,11 @@ static inline bool amdgpu_ras_intr_triggered(void)
+ 	return !!atomic_read(&amdgpu_ras_in_intr);
+ }
+ 
++static inline void amdgpu_ras_intr_cleared(void)
++{
++	atomic_set(&amdgpu_ras_in_intr, 0);
++}
++
+ void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
+ 
+ #endif
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4665-drm-amdgpu-reduce-redundant-uvd-context-lost-warning.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4665-drm-amdgpu-reduce-redundant-uvd-context-lost-warning.patch
new file mode 100644
index 00000000..1041a49e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4665-drm-amdgpu-reduce-redundant-uvd-context-lost-warning.patch
@@ -0,0 +1,53 @@
+From 6a190b81b435736dbf4d2b6f12452132c624717a Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Wed, 27 Nov 2019 16:51:22 +0800
+Subject: [PATCH 4665/4736] drm/amdgpu: reduce redundant uvd context lost
+ warning message
+
+Move the print out of uvd instance loop in amdgpu_uvd_suspend
+
+v2: drop unnecessary brackets
+v3: grab ras_intr state once for multiple times use
+
+Change-Id: Ifad997debd84763e1b55d668e144b729598f115e
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+index 32128e982e4c..04bc063ba1c7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+@@ -349,6 +349,7 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
+ 	unsigned size;
+ 	void *ptr;
+ 	int i, j;
++	bool in_ras_intr = amdgpu_ras_intr_triggered();
+ 
+ 	cancel_delayed_work_sync(&adev->uvd.idle_work);
+ 
+@@ -376,13 +377,15 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
+ 			return -ENOMEM;
+ 
+ 		/* re-write 0 since err_event_athub will corrupt VCPU buffer */
+-		if (amdgpu_ras_intr_triggered()) {
+-			DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n");
++		if (in_ras_intr)
+ 			memset(adev->uvd.inst[j].saved_bo, 0, size);
+-		} else {
++		else
+ 			memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
+-		}
+ 	}
++
++	if (in_ras_intr)
++		DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n");
++
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4666-drm-amd-display-update-sr-and-pstate-latencies-for-R.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4666-drm-amd-display-update-sr-and-pstate-latencies-for-R.patch
new file mode 100644
index 00000000..8517952d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4666-drm-amd-display-update-sr-and-pstate-latencies-for-R.patch
@@ -0,0 +1,119 @@
+From d8de6521c6f1863d6c364855496b14593e66cda4 Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Tue, 5 Nov 2019 11:59:38 -0500
+Subject: [PATCH 4666/4736] drm/amd/display: update sr and pstate latencies for
+ Renoir
+
+[Why]
+DF team has produced more optimized latency numbers.
+
+[How]
+Add sr latencies to the wm table, use different latencies
+for different wm sets.
+Also fix bb override from registery key for these latencies.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c    | 16 ++++++++++++----
+ .../drm/amd/display/dc/dcn21/dcn21_resource.c    | 15 ++++++++++++---
+ drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h  |  2 ++
+ 3 files changed, 26 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 790a2d211bd6..841095d09d3c 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -523,25 +523,33 @@ struct clk_bw_params rn_bw_params = {
+ 			{
+ 				.wm_inst = WM_A,
+ 				.wm_type = WM_TYPE_PSTATE_CHG,
+-				.pstate_latency_us = 23.84,
++				.pstate_latency_us = 11.72,
++				.sr_exit_time_us = 6.09,
++				.sr_enter_plus_exit_time_us = 7.14,
+ 				.valid = true,
+ 			},
+ 			{
+ 				.wm_inst = WM_B,
+ 				.wm_type = WM_TYPE_PSTATE_CHG,
+-				.pstate_latency_us = 23.84,
++				.pstate_latency_us = 11.72,
++				.sr_exit_time_us = 10.12,
++				.sr_enter_plus_exit_time_us = 11.48,
+ 				.valid = true,
+ 			},
+ 			{
+ 				.wm_inst = WM_C,
+ 				.wm_type = WM_TYPE_PSTATE_CHG,
+-				.pstate_latency_us = 23.84,
++				.pstate_latency_us = 11.72,
++				.sr_exit_time_us = 10.12,
++				.sr_enter_plus_exit_time_us = 11.48,
+ 				.valid = true,
+ 			},
+ 			{
+ 				.wm_inst = WM_D,
+ 				.wm_type = WM_TYPE_PSTATE_CHG,
+-				.pstate_latency_us = 23.84,
++				.pstate_latency_us = 11.72,
++				.sr_exit_time_us = 10.12,
++				.sr_enter_plus_exit_time_us = 11.48,
+ 				.valid = true,
+ 			},
+ 		},
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 260471ac20c2..94a5611972cc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -972,6 +972,8 @@ static void calculate_wm_set_for_vlevel(
+ 	pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
+ 
+ 	dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
++	dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
++	dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
+ 
+ 	wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
+ 	wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
+@@ -989,14 +991,21 @@ static void calculate_wm_set_for_vlevel(
+ 
+ static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
+ {
++	int i;
++
+ 	kernel_fpu_begin();
+ 	if (dc->bb_overrides.sr_exit_time_ns) {
+-		bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
++		for (i = 0; i < WM_SET_COUNT; i++) {
++			  dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
++					  dc->bb_overrides.sr_exit_time_ns / 1000.0;
++		}
+ 	}
+ 
+ 	if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
+-		bb->sr_enter_plus_exit_time_us =
+-				dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
++		for (i = 0; i < WM_SET_COUNT; i++) {
++			  dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
++					  dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
++		}
+ 	}
+ 
+ 	if (dc->bb_overrides.urgent_latency_ns) {
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+index 4e18e77dcf42..026e6a2a2c44 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+@@ -69,6 +69,8 @@ struct wm_range_table_entry {
+ 	unsigned int wm_inst;
+ 	unsigned int wm_type;
+ 	double pstate_latency_us;
++	double sr_exit_time_us;
++	double sr_enter_plus_exit_time_us;
+ 	bool valid;
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4667-drm-amd-display-rename-core_dc-to-dc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4667-drm-amd-display-rename-core_dc-to-dc.patch
new file mode 100644
index 00000000..8a62c75b
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4667-drm-amd-display-rename-core_dc-to-dc.patch
@@ -0,0 +1,780 @@
+From 34231c7e48957fe66cb6f6469c55a2f267fda105 Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Tue, 5 Nov 2019 13:04:34 -0500
+Subject: [PATCH 4667/4736] drm/amd/display: rename core_dc to dc
+
+[Why]
+First, to make code more consistent
+Second, to get rid of those scenario where we create a second
+local pointer to dc when it's already passed in.
+
+[How]
+Rename core_dc to dc
+Remove duplicate local pointers to dc
+
+Change-Id: Ibace3c21e3722d874f36567a2e240e2112ba2b17
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ .../dc/clk_mgr/dce112/dce112_clk_mgr.c        | 12 ++--
+ .../dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c  |  6 +-
+ .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c   |  6 +-
+ .../gpu/drm/amd/display/dc/core/dc_debug.c    |  7 +-
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 64 +++++++++----------
+ .../drm/amd/display/dc/core/dc_link_hwss.c    | 26 ++++----
+ .../gpu/drm/amd/display/dc/core/dc_resource.c |  3 +-
+ .../gpu/drm/amd/display/dc/core/dc_stream.c   | 40 ++++++------
+ .../gpu/drm/amd/display/dc/core/dc_surface.c  | 22 +++----
+ .../display/dc/dce110/dce110_hw_sequencer.c   |  8 +--
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 +--
+ .../dc/irq/dce110/irq_service_dce110.c        |  4 +-
+ 12 files changed, 102 insertions(+), 106 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+index a6c46e903ff9..d031bd3d3072 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+@@ -72,8 +72,8 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
+ 	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+ 	struct bp_set_dce_clock_parameters dce_clk_params;
+ 	struct dc_bios *bp = clk_mgr_base->ctx->dc_bios;
+-	struct dc *core_dc = clk_mgr_base->ctx->dc;
+-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	struct dc *dc = clk_mgr_base->ctx->dc;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 	int actual_clock = requested_clk_khz;
+ 	/* Prepare to program display clock*/
+ 	memset(&dce_clk_params, 0, sizeof(dce_clk_params));
+@@ -110,7 +110,7 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
+ 
+ 	bp->funcs->set_dce_clock(bp, &dce_clk_params);
+ 
+-	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
+ 			if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock)
+ 				dmcu->funcs->set_psr_wait_loop(dmcu,
+@@ -126,8 +126,8 @@ int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)
+ {
+ 	struct bp_set_dce_clock_parameters dce_clk_params;
+ 	struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
+-	struct dc *core_dc = clk_mgr->base.ctx->dc;
+-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	struct dc *dc = clk_mgr->base.ctx->dc;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 	int actual_clock = requested_clk_khz;
+ 	/* Prepare to program display clock*/
+ 	memset(&dce_clk_params, 0, sizeof(dce_clk_params));
+@@ -152,7 +152,7 @@ int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)
+ 		clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
+ 
+ 
+-	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
+ 			if (clk_mgr->dfs_bypass_disp_clk != actual_clock)
+ 				dmcu->funcs->set_psr_wait_loop(dmcu,
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
+index 1897e91c8ccb..97b7f32294fd 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
+@@ -88,8 +88,8 @@ int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned
+ int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
+ {
+ 	int actual_dispclk_set_mhz = -1;
+-	struct dc *core_dc = clk_mgr->base.ctx->dc;
+-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	struct dc *dc = clk_mgr->base.ctx->dc;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 
+ 	/*  Unit of SMU msg parameter is Mhz */
+ 	actual_dispclk_set_mhz = rv1_vbios_smu_send_msg_with_param(
+@@ -100,7 +100,7 @@ int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_di
+ 	/* Actual dispclk set is returned in the parameter register */
+ 	actual_dispclk_set_mhz = REG_READ(MP1_SMN_C2PMSG_83) * 1000;
+ 
+-	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
+ 			if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
+ 				dmcu->funcs->set_psr_wait_loop(dmcu,
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+index cb7c0e8b7e1b..6878aedf1d3e 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+@@ -82,8 +82,8 @@ int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
+ int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
+ {
+ 	int actual_dispclk_set_mhz = -1;
+-	struct dc *core_dc = clk_mgr->base.ctx->dc;
+-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	struct dc *dc = clk_mgr->base.ctx->dc;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 
+ 	/*  Unit of SMU msg parameter is Mhz */
+ 	actual_dispclk_set_mhz = rn_vbios_smu_send_msg_with_param(
+@@ -91,7 +91,7 @@ int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dis
+ 			VBIOSSMC_MSG_SetDispclkFreq,
+ 			requested_dispclk_khz / 1000);
+ 
+-	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
+ 			if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
+ 				dmcu->funcs->set_psr_wait_loop(dmcu,
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+index b9227d5de3a3..5203159ad519 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+@@ -310,14 +310,13 @@ void context_timing_trace(
+ 		struct resource_context *res_ctx)
+ {
+ 	int i;
+-	struct dc  *core_dc = dc;
+ 	int h_pos[MAX_PIPES] = {0}, v_pos[MAX_PIPES] = {0};
+ 	struct crtc_position position;
+-	unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index;
++	unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
+ 	DC_LOGGER_INIT(dc->ctx->logger);
+ 
+ 
+-	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ 		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
+ 		/* get_position() returns CRTC vertical/horizontal counter
+ 		 * hence not applicable for underlay pipe
+@@ -329,7 +328,7 @@ void context_timing_trace(
+ 		h_pos[i] = position.horizontal_count;
+ 		v_pos[i] = position.vertical_count;
+ 	}
+-	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ 		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
+ 
+ 		if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx)
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index f27921e46937..9f53cbcc7152 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2353,9 +2353,9 @@ bool dc_link_set_backlight_level(const struct dc_link *link,
+ 		uint32_t backlight_pwm_u16_16,
+ 		uint32_t frame_ramp)
+ {
+-	struct dc  *core_dc = link->ctx->dc;
+-	struct abm *abm = core_dc->res_pool->abm;
+-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	struct dc  *dc = link->ctx->dc;
++	struct abm *abm = dc->res_pool->abm;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 	unsigned int controller_id = 0;
+ 	bool use_smooth_brightness = true;
+ 	int i;
+@@ -2373,22 +2373,22 @@ bool dc_link_set_backlight_level(const struct dc_link *link,
+ 
+ 	if (dc_is_embedded_signal(link->connector_signal)) {
+ 		for (i = 0; i < MAX_PIPES; i++) {
+-			if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) {
+-				if (core_dc->current_state->res_ctx.
++			if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
++				if (dc->current_state->res_ctx.
+ 						pipe_ctx[i].stream->link
+ 						== link) {
+ 					/* DMCU -1 for all controller id values,
+ 					 * therefore +1 here
+ 					 */
+ 					controller_id =
+-						core_dc->current_state->
++						dc->current_state->
+ 						res_ctx.pipe_ctx[i].stream_res.tg->inst +
+ 						1;
+ 
+ 					/* Disable brightness ramping when the display is blanked
+ 					 * as it can hang the DMCU
+ 					 */
+-					if (core_dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL)
++					if (dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL)
+ 						frame_ramp = 0;
+ 				}
+ 			}
+@@ -2406,8 +2406,8 @@ bool dc_link_set_backlight_level(const struct dc_link *link,
+ 
+ bool dc_link_set_abm_disable(const struct dc_link *link)
+ {
+-	struct dc  *core_dc = link->ctx->dc;
+-	struct abm *abm = core_dc->res_pool->abm;
++	struct dc  *dc = link->ctx->dc;
++	struct abm *abm = dc->res_pool->abm;
+ 
+ 	if ((abm == NULL) || (abm->funcs->set_backlight_level_pwm == NULL))
+ 		return false;
+@@ -2419,8 +2419,8 @@ bool dc_link_set_abm_disable(const struct dc_link *link)
+ 
+ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool wait)
+ {
+-	struct dc  *core_dc = link->ctx->dc;
+-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	struct dc  *dc = link->ctx->dc;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 
+ 
+ 
+@@ -2434,8 +2434,8 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool
+ 
+ bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state)
+ {
+-	struct dc  *core_dc = link->ctx->dc;
+-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	struct dc  *dc = link->ctx->dc;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 
+ 	if (dmcu != NULL && link->psr_feature_enabled)
+ 		dmcu->funcs->get_psr_state(dmcu, psr_state);
+@@ -2482,7 +2482,7 @@ bool dc_link_setup_psr(struct dc_link *link,
+ 		const struct dc_stream_state *stream, struct psr_config *psr_config,
+ 		struct psr_context *psr_context)
+ {
+-	struct dc *core_dc;
++	struct dc *dc;
+ 	struct dmcu *dmcu;
+ 	int i;
+ 	/* updateSinkPsrDpcdConfig*/
+@@ -2493,8 +2493,8 @@ bool dc_link_setup_psr(struct dc_link *link,
+ 	if (!link)
+ 		return false;
+ 
+-	core_dc = link->ctx->dc;
+-	dmcu = core_dc->res_pool->dmcu;
++	dc = link->ctx->dc;
++	dmcu = dc->res_pool->dmcu;
+ 
+ 	if (!dmcu)
+ 		return false;
+@@ -2533,13 +2533,13 @@ bool dc_link_setup_psr(struct dc_link *link,
+ 	psr_context->engineId = link->link_enc->preferred_engine;
+ 
+ 	for (i = 0; i < MAX_PIPES; i++) {
+-		if (core_dc->current_state->res_ctx.pipe_ctx[i].stream
++		if (dc->current_state->res_ctx.pipe_ctx[i].stream
+ 				== stream) {
+ 			/* dmcu -1 for all controller id values,
+ 			 * therefore +1 here
+ 			 */
+ 			psr_context->controllerId =
+-				core_dc->current_state->res_ctx.
++				dc->current_state->res_ctx.
+ 				pipe_ctx[i].stream_res.tg->inst + 1;
+ 			break;
+ 		}
+@@ -2903,12 +2903,12 @@ void core_link_enable_stream(
+ 		struct dc_state *state,
+ 		struct pipe_ctx *pipe_ctx)
+ {
+-	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
++	struct dc *dc = pipe_ctx->stream->ctx->dc;
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	enum dc_status status;
+ 	DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
+ 
+-	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) &&
++	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) &&
+ 			dc_is_virtual_signal(pipe_ctx->stream->signal))
+ 		return;
+ 
+@@ -2951,14 +2951,14 @@ void core_link_enable_stream(
+ 			pipe_ctx->stream_res.stream_enc,
+ 			&stream->timing);
+ 
+-	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 		bool apply_edp_fast_boot_optimization =
+ 			pipe_ctx->stream->apply_edp_fast_boot_optimization;
+ 
+ 		pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
+ 
+ 		resource_build_info_frame(pipe_ctx);
+-		core_dc->hwss.update_info_frame(pipe_ctx);
++		dc->hwss.update_info_frame(pipe_ctx);
+ 
+ 		/* Do not touch link on seamless boot optimization. */
+ 		if (pipe_ctx->stream->apply_seamless_boot_optimization) {
+@@ -3001,7 +3001,7 @@ void core_link_enable_stream(
+ 			}
+ 		}
+ 
+-		core_dc->hwss.enable_audio_stream(pipe_ctx);
++		dc->hwss.enable_audio_stream(pipe_ctx);
+ 
+ 		/* turn off otg test pattern if enable */
+ 		if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
+@@ -3014,7 +3014,7 @@ void core_link_enable_stream(
+ 					dc_is_virtual_signal(pipe_ctx->stream->signal))
+ 				dp_set_dsc_enable(pipe_ctx, true);
+ 		}
+-		core_dc->hwss.enable_stream(pipe_ctx);
++		dc->hwss.enable_stream(pipe_ctx);
+ 
+ 		/* Set DPS PPS SDP (AKA "info frames") */
+ 		if (pipe_ctx->stream->timing.flags.DSC) {
+@@ -3026,7 +3026,7 @@ void core_link_enable_stream(
+ 		if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
+ 			dc_link_allocate_mst_payload(pipe_ctx);
+ 
+-		core_dc->hwss.unblank_stream(pipe_ctx,
++		dc->hwss.unblank_stream(pipe_ctx,
+ 			&pipe_ctx->stream->link->cur_link_settings);
+ 
+ 		if (dc_is_dp_signal(pipe_ctx->stream->signal))
+@@ -3035,7 +3035,7 @@ void core_link_enable_stream(
+ 		update_psp_stream_config(pipe_ctx, false);
+ #endif
+ 	}
+-	else { // if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
++	else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+ 		if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+ 				dc_is_virtual_signal(pipe_ctx->stream->signal))
+ 			dp_set_dsc_enable(pipe_ctx, true);
+@@ -3045,11 +3045,11 @@ void core_link_enable_stream(
+ 
+ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+ {
+-	struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
++	struct dc  *dc = pipe_ctx->stream->ctx->dc;
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	struct dc_link *link = stream->sink->link;
+ 
+-	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) &&
++	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) &&
+ 			dc_is_virtual_signal(pipe_ctx->stream->signal))
+ 		return;
+ 
+@@ -3057,7 +3057,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+ 	update_psp_stream_config(pipe_ctx, true);
+ #endif
+ 
+-	core_dc->hwss.blank_stream(pipe_ctx);
++	dc->hwss.blank_stream(pipe_ctx);
+ 
+ 	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
+ 		deallocate_mst_payload(pipe_ctx);
+@@ -3086,7 +3086,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+ 			write_i2c_redriver_setting(pipe_ctx, false);
+ 		}
+ 	}
+-	core_dc->hwss.disable_stream(pipe_ctx);
++	dc->hwss.disable_stream(pipe_ctx);
+ 
+ 	disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
+ 	if (pipe_ctx->stream->timing.flags.DSC) {
+@@ -3097,12 +3097,12 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
+ 
+ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
+ {
+-	struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
++	struct dc  *dc = pipe_ctx->stream->ctx->dc;
+ 
+ 	if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
+ 		return;
+ 
+-	core_dc->hwss.set_avmute(pipe_ctx, enable);
++	dc->hwss.set_avmute(pipe_ctx, enable);
+ }
+ 
+ /**
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index bb1e8e5b5252..67ce12df23f1 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -95,8 +95,8 @@ void dp_enable_link_phy(
+ 	const struct dc_link_settings *link_settings)
+ {
+ 	struct link_encoder *link_enc = link->link_enc;
+-	struct dc  *core_dc = link->ctx->dc;
+-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	struct dc  *dc = link->ctx->dc;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 
+ 	struct pipe_ctx *pipes =
+ 			link->dc->current_state->res_ctx.pipe_ctx;
+@@ -200,8 +200,8 @@ bool edp_receiver_ready_T7(struct dc_link *link)
+ 
+ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal)
+ {
+-	struct dc  *core_dc = link->ctx->dc;
+-	struct dmcu *dmcu = core_dc->res_pool->dmcu;
++	struct dc  *dc = link->ctx->dc;
++	struct dmcu *dmcu = dc->res_pool->dmcu;
+ 
+ 	if (!link->wa_flags.dp_keep_receiver_powered)
+ 		dp_receiver_power_ctrl(link, false);
+@@ -395,14 +395,14 @@ static void dsc_optc_config_log(struct display_stream_compressor *dsc,
+ 
+ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
+ {
+-	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
++	struct dc *dc = pipe_ctx->stream->ctx->dc;
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	bool result = false;
+ 
+-	if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
++	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+ 		result = true;
+ 	else
+-		result = dm_helpers_dp_write_dsc_enable(core_dc->ctx, stream, enable);
++		result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable);
+ 	return result;
+ }
+ 
+@@ -412,7 +412,7 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
+ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ {
+ 	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
+-	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
++	struct dc *dc = pipe_ctx->stream->ctx->dc;
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	struct pipe_ctx *odm_pipe;
+ 	int opp_cnt = 1;
+@@ -448,7 +448,7 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ 		optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
+ 
+ 		/* Enable DSC in encoder */
+-		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 			DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id);
+ 			dsc_optc_config_log(dsc, &dsc_optc_cfg);
+ 			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,
+@@ -473,7 +473,7 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
+ 				OPTC_DSC_DISABLED, 0, 0);
+ 
+ 		/* disable DSC in stream encoder */
+-		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(
+ 					pipe_ctx->stream_res.stream_enc,
+ 					OPTC_DSC_DISABLED, 0, 0);
+@@ -516,7 +516,7 @@ bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable)
+ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
+ {
+ 	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
+-	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
++	struct dc *dc = pipe_ctx->stream->ctx->dc;
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 
+ 	if (!pipe_ctx->stream->timing.flags.DSC || !dsc)
+@@ -535,7 +535,7 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
+ 
+ 		DC_LOG_DSC(" ");
+ 		dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);
+-		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 			DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);
+ 			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
+ 									pipe_ctx->stream_res.stream_enc,
+@@ -544,7 +544,7 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
+ 		}
+ 	} else {
+ 		/* disable DSC PPS in stream encoder */
+-		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
+ 						pipe_ctx->stream_res.stream_enc, false, NULL);
+ 		}
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 081275a430ad..67d1c8cc583b 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -2750,9 +2750,8 @@ void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
+ 
+ enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
+ {
+-	struct dc  *core_dc = dc;
+ 	struct dc_link *link = stream->link;
+-	struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
++	struct timing_generator *tg = dc->res_pool->timing_generators[0];
+ 	enum dc_status res = DC_OK;
+ 
+ 	calculate_phy_pix_clks(stream);
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+index 9029786c7b08..a43b4d7d5a50 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+@@ -268,7 +268,7 @@ bool dc_stream_set_cursor_attributes(
+ 	const struct dc_cursor_attributes *attributes)
+ {
+ 	int i;
+-	struct dc  *core_dc;
++	struct dc  *dc;
+ 	struct resource_context *res_ctx;
+ 	struct pipe_ctx *pipe_to_program = NULL;
+ 
+@@ -286,8 +286,8 @@ bool dc_stream_set_cursor_attributes(
+ 		return false;
+ 	}
+ 
+-	core_dc = stream->ctx->dc;
+-	res_ctx = &core_dc->current_state->res_ctx;
++	dc = stream->ctx->dc;
++	res_ctx = &dc->current_state->res_ctx;
+ 	stream->cursor_attributes = *attributes;
+ 
+ 	for (i = 0; i < MAX_PIPES; i++) {
+@@ -299,17 +299,17 @@ bool dc_stream_set_cursor_attributes(
+ 		if (!pipe_to_program) {
+ 			pipe_to_program = pipe_ctx;
+ 
+-			delay_cursor_until_vupdate(pipe_ctx, core_dc);
+-			core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true);
++			delay_cursor_until_vupdate(pipe_ctx, dc);
++			dc->hwss.pipe_control_lock(dc, pipe_to_program, true);
+ 		}
+ 
+-		core_dc->hwss.set_cursor_attribute(pipe_ctx);
+-		if (core_dc->hwss.set_cursor_sdr_white_level)
+-			core_dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
++		dc->hwss.set_cursor_attribute(pipe_ctx);
++		if (dc->hwss.set_cursor_sdr_white_level)
++			dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
+ 	}
+ 
+ 	if (pipe_to_program)
+-		core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false);
++		dc->hwss.pipe_control_lock(dc, pipe_to_program, false);
+ 
+ 	return true;
+ }
+@@ -319,7 +319,7 @@ bool dc_stream_set_cursor_position(
+ 	const struct dc_cursor_position *position)
+ {
+ 	int i;
+-	struct dc  *core_dc;
++	struct dc  *dc;
+ 	struct resource_context *res_ctx;
+ 	struct pipe_ctx *pipe_to_program = NULL;
+ 
+@@ -333,8 +333,8 @@ bool dc_stream_set_cursor_position(
+ 		return false;
+ 	}
+ 
+-	core_dc = stream->ctx->dc;
+-	res_ctx = &core_dc->current_state->res_ctx;
++	dc = stream->ctx->dc;
++	res_ctx = &dc->current_state->res_ctx;
+ 	stream->cursor_position = *position;
+ 
+ 	for (i = 0; i < MAX_PIPES; i++) {
+@@ -350,15 +350,15 @@ bool dc_stream_set_cursor_position(
+ 		if (!pipe_to_program) {
+ 			pipe_to_program = pipe_ctx;
+ 
+-			delay_cursor_until_vupdate(pipe_ctx, core_dc);
+-			core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true);
++			delay_cursor_until_vupdate(pipe_ctx, dc);
++			dc->hwss.pipe_control_lock(dc, pipe_to_program, true);
+ 		}
+ 
+-		core_dc->hwss.set_cursor_position(pipe_ctx);
++		dc->hwss.set_cursor_position(pipe_ctx);
+ 	}
+ 
+ 	if (pipe_to_program)
+-		core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false);
++		dc->hwss.pipe_control_lock(dc, pipe_to_program, false);
+ 
+ 	return true;
+ }
+@@ -479,9 +479,9 @@ bool dc_stream_remove_writeback(struct dc *dc,
+ uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
+ {
+ 	uint8_t i;
+-	struct dc  *core_dc = stream->ctx->dc;
++	struct dc  *dc = stream->ctx->dc;
+ 	struct resource_context *res_ctx =
+-		&core_dc->current_state->res_ctx;
++		&dc->current_state->res_ctx;
+ 
+ 	for (i = 0; i < MAX_PIPES; i++) {
+ 		struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
+@@ -538,9 +538,9 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
+ {
+ 	uint8_t i;
+ 	bool ret = false;
+-	struct dc  *core_dc = stream->ctx->dc;
++	struct dc  *dc = stream->ctx->dc;
+ 	struct resource_context *res_ctx =
+-		&core_dc->current_state->res_ctx;
++		&dc->current_state->res_ctx;
+ 
+ 	for (i = 0; i < MAX_PIPES; i++) {
+ 		struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+index 5904c459fe8f..834d6145aab4 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+@@ -106,16 +106,14 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
+ 
+ struct dc_plane_state *dc_create_plane_state(struct dc *dc)
+ {
+-	struct dc *core_dc = dc;
+-
+ 	struct dc_plane_state *plane_state = kvzalloc(sizeof(*plane_state),
+-						      GFP_KERNEL);
++							GFP_KERNEL);
+ 
+ 	if (NULL == plane_state)
+ 		return NULL;
+ 
+ 	kref_init(&plane_state->refcount);
+-	dc_plane_construct(core_dc->ctx, plane_state);
++	dc_plane_construct(dc->ctx, plane_state);
+ 
+ 	return plane_state;
+ }
+@@ -135,7 +133,7 @@ const struct dc_plane_status *dc_plane_get_status(
+ 		const struct dc_plane_state *plane_state)
+ {
+ 	const struct dc_plane_status *plane_status;
+-	struct dc  *core_dc;
++	struct dc  *dc;
+ 	int i;
+ 
+ 	if (!plane_state ||
+@@ -146,15 +144,15 @@ const struct dc_plane_status *dc_plane_get_status(
+ 	}
+ 
+ 	plane_status = &plane_state->status;
+-	core_dc = plane_state->ctx->dc;
++	dc = plane_state->ctx->dc;
+ 
+-	if (core_dc->current_state == NULL)
++	if (dc->current_state == NULL)
+ 		return NULL;
+ 
+ 	/* Find the current plane state and set its pending bit to false */
+-	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ 		struct pipe_ctx *pipe_ctx =
+-				&core_dc->current_state->res_ctx.pipe_ctx[i];
++				&dc->current_state->res_ctx.pipe_ctx[i];
+ 
+ 		if (pipe_ctx->plane_state != plane_state)
+ 			continue;
+@@ -164,14 +162,14 @@ const struct dc_plane_status *dc_plane_get_status(
+ 		break;
+ 	}
+ 
+-	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
++	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ 		struct pipe_ctx *pipe_ctx =
+-				&core_dc->current_state->res_ctx.pipe_ctx[i];
++				&dc->current_state->res_ctx.pipe_ctx[i];
+ 
+ 		if (pipe_ctx->plane_state != plane_state)
+ 			continue;
+ 
+-		core_dc->hwss.update_pending_status(pipe_ctx);
++		dc->hwss.update_pending_status(pipe_ctx);
+ 	}
+ 
+ 	return plane_status;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 6291f803cd16..ad53e6727df2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -942,15 +942,15 @@ void dce110_edp_backlight_control(
+ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
+ {
+ 	/* notify audio driver for audio modes of monitor */
+-	struct dc *core_dc;
++	struct dc *dc;
+ 	struct clk_mgr *clk_mgr;
+ 	unsigned int i, num_audio = 1;
+ 
+ 	if (!pipe_ctx->stream)
+ 		return;
+ 
+-	core_dc = pipe_ctx->stream->ctx->dc;
+-	clk_mgr = core_dc->clk_mgr;
++	dc = pipe_ctx->stream->ctx->dc;
++	clk_mgr = dc->clk_mgr;
+ 
+ 	if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
+ 		return;
+@@ -958,7 +958,7 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
+ 	if (pipe_ctx->stream_res.audio) {
+ 		for (i = 0; i < MAX_PIPES; i++) {
+ 			/*current_state not updated yet*/
+-			if (core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
++			if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
+ 				num_audio++;
+ 		}
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 08d15982f526..1ed26ac33551 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1655,10 +1655,10 @@ void dcn10_enable_per_frame_crtc_position_reset(
+ }
+ 
+ /*static void print_rq_dlg_ttu(
+-		struct dc *core_dc,
++		struct dc *dc,
+ 		struct pipe_ctx *pipe_ctx)
+ {
+-	DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
++	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
+ 			"\n============== DML TTU Output parameters [%d] ==============\n"
+ 			"qos_level_low_wm: %d, \n"
+ 			"qos_level_high_wm: %d, \n"
+@@ -1688,7 +1688,7 @@ void dcn10_enable_per_frame_crtc_position_reset(
+ 			pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
+ 			);
+ 
+-	DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
++	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
+ 			"\n============== DML DLG Output parameters [%d] ==============\n"
+ 			"refcyc_h_blank_end: %d, \n"
+ 			"dlg_vblank_end: %d, \n"
+@@ -1723,7 +1723,7 @@ void dcn10_enable_per_frame_crtc_position_reset(
+ 			pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
+ 			);
+ 
+-	DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
++	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
+ 			"\ndst_y_per_meta_row_nom_l: %d, \n"
+ 			"refcyc_per_meta_chunk_nom_l: %d, \n"
+ 			"refcyc_per_line_delivery_pre_l: %d, \n"
+@@ -1753,7 +1753,7 @@ void dcn10_enable_per_frame_crtc_position_reset(
+ 			pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
+ 			);
+ 
+-	DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
++	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
+ 			"\n============== DML RQ Output parameters [%d] ==============\n"
+ 			"chunk_size: %d \n"
+ 			"min_chunk_size: %d \n"
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+index 80603e18ecd6..662266fc3edf 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+@@ -202,7 +202,7 @@ bool dce110_vblank_set(struct irq_service *irq_service,
+ 		       bool enable)
+ {
+ 	struct dc_context *dc_ctx = irq_service->ctx;
+-	struct dc *core_dc = irq_service->ctx->dc;
++	struct dc *dc = irq_service->ctx->dc;
+ 	enum dc_irq_source dal_irq_src =
+ 			dc_interrupt_to_irq_source(irq_service->ctx->dc,
+ 						   info->src_id,
+@@ -210,7 +210,7 @@ bool dce110_vblank_set(struct irq_service *irq_service,
+ 	uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;
+ 
+ 	struct timing_generator *tg =
+-			core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
++			dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
+ 
+ 	if (enable) {
+ 		if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4668-drm-amd-display-add-separate-of-private-hwss-functio.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4668-drm-amd-display-add-separate-of-private-hwss-functio.patch
new file mode 100644
index 00000000..9fc92880
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4668-drm-amd-display-add-separate-of-private-hwss-functio.patch
@@ -0,0 +1,2772 @@
+From ff94007b6f9295e74823b8083017abfe9c10e5a5 Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Tue, 5 Nov 2019 13:17:30 -0500
+Subject: [PATCH 4668/4736] drm/amd/display: add separate of private hwss
+ functions
+
+[Why]
+Some function pointers in the hwss function pointer table are
+meant to be hw sequencer entry points to be called from dc.
+
+However some of those function pointers are not meant to
+be entry points, but instead used as a code reuse/inheritance
+tool called directly by other hwss functions, not by dc.
+
+Therefore, we want a more clear separation of which functions
+we determine to be interface functions vs the functions we
+use within hwss.
+
+[How]
+DC interface functions will be stored in:
+    struct hw_sequencer_funcs
+Functions used within HWSS will be stored in:
+    struct hwseq_private_funcs
+
+Also compilation fix for CONFIG_DRM_AMD_DC_DCN2_0 and CONFIG_DRM_AMD_DC_DCN2_0
+are done
+Change-Id: Ia8d8be52879c996de697011d0d57feee11267a19
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/Makefile       |  11 +-
+ drivers/gpu/drm/amd/display/dc/core/dc.c      |  56 ++-
+ .../gpu/drm/amd/display/dc/core/dc_debug.c    |   1 -
+ .../gpu/drm/amd/display/dc/core/dc_resource.c |   3 +-
+ .../gpu/drm/amd/display/dc/core/dc_stream.c   |   9 +-
+ .../gpu/drm/amd/display/dc/dce/dce_hwseq.c    |   2 +-
+ .../gpu/drm/amd/display/dc/dce/dce_hwseq.h    |   6 +-
+ .../display/dc/dce100/dce100_hw_sequencer.c   |   3 +-
+ .../display/dc/dce100/dce100_hw_sequencer.h   |   1 +
+ .../display/dc/dce110/dce110_hw_sequencer.c   |  81 ++--
+ .../display/dc/dce110/dce110_hw_sequencer.h   |   1 +
+ .../amd/display/dc/dce110/dce110_resource.c   |   3 +-
+ .../display/dc/dce112/dce112_hw_sequencer.c   |   2 +-
+ .../display/dc/dce112/dce112_hw_sequencer.h   |   1 +
+ .../display/dc/dce120/dce120_hw_sequencer.c   |   2 +-
+ .../display/dc/dce120/dce120_hw_sequencer.h   |   1 +
+ .../amd/display/dc/dce80/dce80_hw_sequencer.c |   2 +-
+ .../amd/display/dc/dce80/dce80_hw_sequencer.h |   1 +
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 128 +++---
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |   1 +
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |  38 +-
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  71 ++--
+ .../drm/amd/display/dc/dcn20/dcn20_hwseq.h    |   3 +
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |  54 +--
+ .../drm/amd/display/dc/dcn21/dcn21_hwseq.c    |   1 +
+ .../drm/amd/display/dc/dcn21/dcn21_hwseq.h    |   2 +
+ .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |  63 +--
+ .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 385 +++++-------------
+ .../amd/display/dc/inc/hw_sequencer_private.h | 156 +++++++
+ 29 files changed, 613 insertions(+), 475 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
+index 38ef29719400..57e12b6c48fa 100644
+--- a/drivers/gpu/drm/amd/display/dc/Makefile
++++ b/drivers/gpu/drm/amd/display/dc/Makefile
+@@ -25,9 +25,16 @@
+ 
+ DC_LIBS = basics bios calcs clk_mgr dce gpio irq virtual
+ 
+-ifdef CONFIG_DRM_AMD_DC_DCN1_0
++ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ DC_LIBS += dcn20
++endif
++
++
++ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ DC_LIBS += dsc
++endif
++
++ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ DC_LIBS += dcn10 dml
+ endif
+ 
+@@ -53,7 +60,7 @@ include $(AMD_DC)
+ DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \
+ dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o
+ 
+-ifdef CONFIG_DRM_AMD_DC_DCN1_0
++ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ DISPLAY_CORE += dc_vm_helper.o
+ endif
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 09184adfccc8..e5cbc5bf3290 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -57,9 +57,13 @@
+ #include "dc_link_dp.h"
+ #include "dc_dmub_srv.h"
+ 
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ #include "dsc.h"
++#endif
+ 
++#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ #include "vm_helper.h"
++#endif
+ 
+ #include "dce/dce_i2c.h"
+ 
+@@ -571,8 +575,10 @@ static void dc_destruct(struct dc *dc)
+ 	dc->dcn_ip = NULL;
+ 
+ #endif
++#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	kfree(dc->vm_helper);
+ 	dc->vm_helper = NULL;
++#endif
+ 
+ }
+ 
+@@ -590,8 +596,10 @@ static bool dc_construct(struct dc *dc,
+ 	enum dce_version dc_version = DCE_VERSION_UNKNOWN;
+ 	dc->config = init_params->flags;
+ 
++#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 	// Allocate memory for the vm_helper
+ 	dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
++#endif
+ 
+ 	memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
+ 
+@@ -626,7 +634,9 @@ static bool dc_construct(struct dc *dc,
+ 	}
+ 
+ 	dc->dcn_ip = dcn_ip;
++#ifdef CONFIG_DRM_AMD_DC_DCN2_0	
+ 	dc->soc_bounding_box = init_params->soc_bounding_box;
++#endif
+ #endif
+ 
+ 	dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
+@@ -728,6 +738,7 @@ static bool dc_construct(struct dc *dc,
+ 	return false;
+ }
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ static bool disable_all_writeback_pipes_for_stream(
+ 		const struct dc *dc,
+ 		struct dc_stream_state *stream,
+@@ -740,6 +751,7 @@ static bool disable_all_writeback_pipes_for_stream(
+ 
+ 	return true;
+ }
++#endif
+ 
+ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
+ {
+@@ -765,12 +777,16 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
+ 		}
+ 		if (should_disable && old_stream) {
+ 			dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)			
+ 			disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
++#endif
+ 			if (dc->hwss.apply_ctx_for_surface)
+ 				dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
+ 		}
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)		
+ 		if (dc->hwss.program_front_end_for_ctx)
+ 			dc->hwss.program_front_end_for_ctx(dc, dangling_context);
++#endif
+ 	}
+ 
+ 	current_ctx = dc->current_state;
+@@ -1160,8 +1176,10 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ 				context->stream_status[i].plane_count,
+ 				context); /* use new pipe config in new context */
+ 		}
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	if (dc->hwss.program_front_end_for_ctx)
+ 		dc->hwss.program_front_end_for_ctx(dc, context);
++#endif
+ 
+ 	/* Program hardware */
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+@@ -1180,8 +1198,10 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ 	}
+ 
+ 	/* Program all planes within new context*/
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)	
+ 	if (dc->hwss.program_front_end_for_ctx)
+ 		dc->hwss.program_front_end_for_ctx(dc, context);
++#endif
+ 	for (i = 0; i < context->stream_count; i++) {
+ 		const struct dc_link *link = context->streams[i]->link;
+ 
+@@ -1665,8 +1685,10 @@ static enum surface_update_type check_update_surfaces_for_stream(
+ 		if (stream_update->gamut_remap)
+ 			su_flags->bits.gamut_remap = 1;
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 		if (stream_update->wb_update)
+ 			su_flags->bits.wb_update = 1;
++#endif		
+ 		if (su_flags->raw != 0)
+ 			overall_type = UPDATE_TYPE_FULL;
+ 
+@@ -1834,6 +1856,7 @@ static void copy_surface_update_to_plane(
+ 			sizeof(struct dc_transfer_func_distributed_points));
+ 	}
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)	
+ 	if (srf_update->func_shaper &&
+ 			(surface->in_shaper_func !=
+ 			srf_update->func_shaper))
+@@ -1855,6 +1878,7 @@ static void copy_surface_update_to_plane(
+ 			srf_update->blend_tf))
+ 		memcpy(surface->blend_tf, srf_update->blend_tf,
+ 		sizeof(*surface->blend_tf));
++#endif
+ 
+ 	if (srf_update->input_csc_color_matrix)
+ 		surface->input_csc_color_matrix =
+@@ -1932,6 +1956,7 @@ static void copy_stream_update_to_stream(struct dc *dc,
+ 
+ 	if (update->dither_option)
+ 		stream->dither_option = *update->dither_option;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)	
+ 	/* update current stream with writeback info */
+ 	if (update->wb_update) {
+ 		int i;
+@@ -1942,6 +1967,8 @@ static void copy_stream_update_to_stream(struct dc *dc,
+ 			stream->writeback_info[i] =
+ 				update->wb_update->writeback_info[i];
+ 	}
++#endif
++#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
+ 	if (update->dsc_config) {
+ 		struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
+ 		uint32_t old_dsc_enabled = stream->timing.flags.DSC;
+@@ -1968,6 +1995,7 @@ static void copy_stream_update_to_stream(struct dc *dc,
+ 			update->dsc_config = NULL;
+ 		}
+ 	}
++#endif
+ }
+ 
+ static void commit_planes_do_stream_update(struct dc *dc,
+@@ -2001,6 +2029,12 @@ static void commit_planes_do_stream_update(struct dc *dc,
+ 				dc->hwss.update_info_frame(pipe_ctx);
+ 			}
+ 
++			if (stream_update->hdr_static_metadata &&
++					stream->use_dynamic_meta &&
++					dc->hwss.set_dmdata_attributes &&
++					pipe_ctx->stream->dmdata_address.quad_part != 0)
++				dc->hwss.set_dmdata_attributes(pipe_ctx);
++
+ 			if (stream_update->gamut_remap)
+ 				dc_stream_set_gamut_remap(dc, stream);
+ 
+@@ -2008,25 +2042,30 @@ static void commit_planes_do_stream_update(struct dc *dc,
+ 				dc_stream_program_csc_matrix(dc, stream);
+ 
+ 			if (stream_update->dither_option) {
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)				
+ 				struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
++#endif
+ 				resource_build_bit_depth_reduction_params(pipe_ctx->stream,
+ 									&pipe_ctx->stream->bit_depth_params);
+ 				pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
+ 						&stream->bit_depth_params,
+ 						&stream->clamping);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 				while (odm_pipe) {
+ 					odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
+ 							&stream->bit_depth_params,
+ 							&stream->clamping);
+ 					odm_pipe = odm_pipe->next_odm_pipe;
+ 				}
++#endif
+ 			}
+-
++#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
+ 			if (stream_update->dsc_config && dc->hwss.pipe_control_lock_global) {
+ 				dc->hwss.pipe_control_lock_global(dc, pipe_ctx, true);
+ 				dp_update_dsc_config(pipe_ctx);
+ 				dc->hwss.pipe_control_lock_global(dc, pipe_ctx, false);
+ 			}
++#endif
+ 			/* Full fe update*/
+ 			if (update_type == UPDATE_TYPE_FAST)
+ 				continue;
+@@ -2113,12 +2152,14 @@ static void commit_planes_for_stream(struct dc *dc,
+ 		 */
+ 		if (dc->hwss.apply_ctx_for_surface)
+ 			dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)		
+ 		if (dc->hwss.program_front_end_for_ctx)
+ 			dc->hwss.program_front_end_for_ctx(dc, context);
+-
++#endif		
+ 		return;
+ 	}
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
+ 		for (i = 0; i < surface_count; i++) {
+ 			struct dc_plane_state *plane_state = srf_updates[i].surface;
+@@ -2140,6 +2181,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ 			}
+ 		}
+ 	}
++#endif
+ 
+ 	// Update Type FULL, Surface updates
+ 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
+@@ -2160,6 +2202,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ 			if (update_type == UPDATE_TYPE_FAST)
+ 				continue;
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 			ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
+ 
+ 			if (dc->hwss.program_triplebuffer != NULL &&
+@@ -2168,6 +2211,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ 				dc->hwss.program_triplebuffer(
+ 					dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
+ 			}
++#endif
+ 			stream_status =
+ 				stream_get_status(context, pipe_ctx->stream);
+ 
+@@ -2176,6 +2220,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ 					dc, pipe_ctx->stream, stream_status->plane_count, context);
+ 		}
+ 	}
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
+ 		dc->hwss.program_front_end_for_ctx(dc, context);
+ #ifdef CONFIG_DRM_AMD_DC_DCN1_0
+@@ -2194,6 +2239,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ 		}
+ #endif
+ 	}
++#endif
+ 
+ 	// Update Type FAST, Surface updates
+ 	if (update_type == UPDATE_TYPE_FAST) {
+@@ -2203,6 +2249,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ 		 */
+ 		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 		if (dc->hwss.set_flip_control_gsl)
+ 			for (i = 0; i < surface_count; i++) {
+ 				struct dc_plane_state *plane_state = srf_updates[i].surface;
+@@ -2221,6 +2268,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ 							plane_state->flip_immediate);
+ 				}
+ 			}
++#endif
+ 		/* Perform requested Updates */
+ 		for (i = 0; i < surface_count; i++) {
+ 			struct dc_plane_state *plane_state = srf_updates[i].surface;
+@@ -2233,6 +2281,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ 
+ 				if (pipe_ctx->plane_state != plane_state)
+ 					continue;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 				/*program triple buffer after lock based on flip type*/
+ 				if (dc->hwss.program_triplebuffer != NULL &&
+ 					!dc->debug.disable_tri_buf) {
+@@ -2240,6 +2289,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ 					dc->hwss.program_triplebuffer(
+ 						dc, pipe_ctx, plane_state->triplebuffer_flips);
+ 				}
++#endif
+ 				if (srf_updates[i].flip_addr)
+ 					dc->hwss.update_plane_addr(dc, pipe_ctx);
+ 			}
+@@ -2405,10 +2455,12 @@ void dc_set_power_state(
+ 
+ 		dc->hwss.init_hw(dc);
+ 
++#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ 		if (dc->hwss.init_sys_ctx != NULL &&
+ 			dc->vm_pa_config.valid) {
+ 			dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
+ 		}
++#endif
+ 
+ 		break;
+ 	default:
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+index 5203159ad519..c371e553a476 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+@@ -33,7 +33,6 @@
+ 
+ #include "core_status.h"
+ #include "core_types.h"
+-#include "hw_sequencer.h"
+ 
+ #include "resource.h"
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index 67d1c8cc583b..fd9358c11222 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -161,10 +161,11 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
+ 		res_pool = dcn10_create_resource_pool(init_data, dc);
+ 		break;
+ 
+-
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	case DCN_VERSION_2_0:
+ 		res_pool = dcn20_create_resource_pool(init_data, dc);
+ 		break;
++#endif
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ 	case DCN_VERSION_2_1:
+ 		res_pool = dcn21_create_resource_pool(init_data, dc);
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+index a43b4d7d5a50..8eb441388335 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+@@ -30,9 +30,6 @@
+ #include "resource.h"
+ #include "ipp.h"
+ #include "timing_generator.h"
+-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+-#include "dcn10/dcn10_hw_sequencer.h"
+-#endif
+ 
+ #define DC_LOGGER dc->ctx->logger
+ 
+@@ -106,6 +103,7 @@ static void dc_stream_construct(struct dc_stream_state *stream,
+ 	/* EDID CAP translation for HDMI 2.0 */
+ 	stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
+ 
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));
+ 	stream->timing.dsc_cfg.num_slices_h = 0;
+ 	stream->timing.dsc_cfg.num_slices_v = 0;
+@@ -114,6 +112,7 @@ static void dc_stream_construct(struct dc_stream_state *stream,
+ 	stream->timing.dsc_cfg.linebuf_depth = 9;
+ 	stream->timing.dsc_cfg.version_minor = 2;
+ 	stream->timing.dsc_cfg.ycbcr422_simple = 0;
++#endif
+ 
+ 	update_stream_signal(stream, dc_sink_data);
+ 
+@@ -363,6 +362,7 @@ bool dc_stream_set_cursor_position(
+ 	return true;
+ }
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool dc_stream_add_writeback(struct dc *dc,
+ 		struct dc_stream_state *stream,
+ 		struct dc_writeback_info *wb_info)
+@@ -475,6 +475,7 @@ bool dc_stream_remove_writeback(struct dc *dc,
+ 
+ 	return true;
+ }
++#endif
+ 
+ uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
+ {
+@@ -561,6 +562,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
+ 	return ret;
+ }
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
+ {
+ 	struct pipe_ctx *pipe = NULL;
+@@ -621,6 +623,7 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc,
+ 
+ 	return true;
+ }
++#endif
+ 
+ void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)
+ {
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+index 0275d6d60da4..e1c5839a80dc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+@@ -25,7 +25,7 @@
+ 
+ #include "dce_hwseq.h"
+ #include "reg_helper.h"
+-#include "hw_sequencer.h"
++#include "hw_sequencer_private.h"
+ #include "core_types.h"
+ 
+ #define CTX \
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+index 7e3dde764111..a3491fab05f6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+@@ -25,7 +25,7 @@
+ #ifndef __DCE_HWSEQ_H__
+ #define __DCE_HWSEQ_H__
+ 
+-#include "hw_sequencer.h"
++#include "dc_types.h"
+ 
+ #define BL_REG_LIST()\
+ 	SR(LVTMA_PWRSEQ_CNTL), \
+@@ -815,6 +815,10 @@ enum blnd_mode {
+ 	BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
+ };
+ 
++struct dce_hwseq;
++struct pipe_ctx;
++struct clock_source;
++
+ void dce_enable_fe_clock(struct dce_hwseq *hwss,
+ 		unsigned int inst, bool enable);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+index 799d36299c9b..753cb8edd996 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+@@ -26,7 +26,6 @@
+ #include "dc.h"
+ #include "core_types.h"
+ #include "clk_mgr.h"
+-#include "hw_sequencer.h"
+ #include "dce100_hw_sequencer.h"
+ #include "resource.h"
+ 
+@@ -136,7 +135,7 @@ void dce100_hw_sequencer_construct(struct dc *dc)
+ {
+ 	dce110_hw_sequencer_construct(dc);
+ 
+-	dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
++	dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;
+ 	dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
+ 	dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
+index a6b80fdaa666..34518da20009 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
+@@ -27,6 +27,7 @@
+ #define __DC_HWSS_DCE100_H__
+ 
+ #include "core_types.h"
++#include "hw_sequencer_private.h"
+ 
+ struct dc;
+ struct dc_state;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index ad53e6727df2..f95c122c197b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -650,10 +650,9 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
+ {
+ 	enum dc_lane_count lane_count =
+ 		pipe_ctx->stream->link->cur_link_settings.lane_count;
+-
+ 	struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
+ 	struct dc_link *link = pipe_ctx->stream->link;
+-
++	const struct dc *dc = link->dc;
+ 
+ 	uint32_t active_total_with_borders;
+ 	uint32_t early_control = 0;
+@@ -666,7 +665,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
+ 	link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
+ 						    pipe_ctx->stream_res.stream_enc->id, true);
+ 
+-	link->dc->hwss.update_info_frame(pipe_ctx);
++	dc->hwss.update_info_frame(pipe_ctx);
+ 
+ 	/* enable early control to avoid corruption on DP monitor*/
+ 	active_total_with_borders =
+@@ -1046,6 +1045,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
+ 	struct encoder_unblank_param params = { { 0 } };
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	struct dc_link *link = stream->link;
++	struct dce_hwseq *hws = link->dc->hwseq;
+ 
+ 	/* only 3 items below are used by unblank */
+ 	params.timing = pipe_ctx->stream->timing;
+@@ -1055,7 +1055,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
+ 		pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
+ 
+ 	if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
+-		link->dc->hwss.edp_backlight_control(link, true);
++		hws->funcs.edp_backlight_control(link, true);
+ 	}
+ }
+ 
+@@ -1063,9 +1063,10 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
+ {
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	struct dc_link *link = stream->link;
++	struct dce_hwseq *hws = link->dc->hwseq;
+ 
+ 	if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
+-		link->dc->hwss.edp_backlight_control(link, false);
++		hws->funcs.edp_backlight_control(link, false);
+ 		dc_link_set_abm_disable(link);
+ 	}
+ 
+@@ -1321,10 +1322,13 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	struct drr_params params = {0};
+ 	unsigned int event_triggers = 0;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
++#endif
++	struct dce_hwseq *hws = dc->hwseq;
+ 
+-	if (dc->hwss.disable_stream_gating) {
+-		dc->hwss.disable_stream_gating(dc, pipe_ctx);
++	if (hws->funcs.disable_stream_gating) {
++		hws->funcs.disable_stream_gating(dc, pipe_ctx);
+ 	}
+ 
+ 	if (pipe_ctx->stream_res.audio != NULL) {
+@@ -1354,10 +1358,10 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ 	/*  */
+ 	/* Do not touch stream timing on seamless boot optimization. */
+ 	if (!pipe_ctx->stream->apply_seamless_boot_optimization)
+-		dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
++		hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
+ 
+-	if (dc->hwss.setup_vupdate_interrupt)
+-		dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
++	if (hws->funcs.setup_vupdate_interrupt)
++		hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
+ 
+ 	params.vertical_total_min = stream->adjust.v_total_min;
+ 	params.vertical_total_max = stream->adjust.v_total_max;
+@@ -1387,6 +1391,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ 		pipe_ctx->stream_res.opp,
+ 		&stream->bit_depth_params,
+ 		&stream->clamping);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	while (odm_pipe) {
+ 		odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
+ 				odm_pipe->stream_res.opp,
+@@ -1400,6 +1405,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ 				&stream->clamping);
+ 		odm_pipe = odm_pipe->next_odm_pipe;
+ 	}
++#endif
+ 
+ 	if (!stream->dpms_off)
+ 		core_link_enable_stream(context, pipe_ctx);
+@@ -1550,9 +1556,10 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
+ 	bool can_apply_edp_fast_boot = false;
+ 	bool can_apply_seamless_boot = false;
+ 	bool keep_edp_vdd_on = false;
++	struct dce_hwseq *hws = dc->hwseq;
+ 
+-	if (dc->hwss.init_pipes)
+-		dc->hwss.init_pipes(dc, context);
++	if (hws->funcs.init_pipes)
++		hws->funcs.init_pipes(dc, context);
+ 
+ 	edp_stream = get_edp_stream(context);
+ 
+@@ -1589,7 +1596,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
+ 	if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {
+ 		if (edp_link_with_sink && !keep_edp_vdd_on) {
+ 			/*turn off backlight before DP_blank and encoder powered down*/
+-			dc->hwss.edp_backlight_control(edp_link_with_sink, false);
++			hws->funcs.edp_backlight_control(edp_link_with_sink, false);
+ 		}
+ 		/*resume from S3, no vbios posting, no need to power down again*/
+ 		power_down_all_hw_blocks(dc);
+@@ -2004,13 +2011,14 @@ enum dc_status dce110_apply_ctx_to_hw(
+ 		struct dc *dc,
+ 		struct dc_state *context)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	struct dc_bios *dcb = dc->ctx->dc_bios;
+ 	enum dc_status status;
+ 	int i;
+ 
+ 	/* Reset old context */
+ 	/* look up the targets that have been removed since last commit */
+-	dc->hwss.reset_hw_ctx_wrap(dc, context);
++	hws->funcs.reset_hw_ctx_wrap(dc, context);
+ 
+ 	/* Skip applying if no targets */
+ 	if (context->stream_count <= 0)
+@@ -2035,7 +2043,7 @@ enum dc_status dce110_apply_ctx_to_hw(
+ 			continue;
+ 		}
+ 
+-		dc->hwss.enable_display_power_gating(
++		hws->funcs.enable_display_power_gating(
+ 				dc, i, dc->ctx->dc_bios,
+ 				PIPE_GATING_CONTROL_DISABLE);
+ 	}
+@@ -2344,19 +2352,20 @@ static void init_hw(struct dc *dc)
+ 	struct transform *xfm;
+ 	struct abm *abm;
+ 	struct dmcu *dmcu;
++	struct dce_hwseq *hws = dc->hwseq;
+ 
+ 	bp = dc->ctx->dc_bios;
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ 		xfm = dc->res_pool->transforms[i];
+ 		xfm->funcs->transform_reset(xfm);
+ 
+-		dc->hwss.enable_display_power_gating(
++		hws->funcs.enable_display_power_gating(
+ 				dc, i, bp,
+ 				PIPE_GATING_CONTROL_INIT);
+-		dc->hwss.enable_display_power_gating(
++		hws->funcs.enable_display_power_gating(
+ 				dc, i, bp,
+ 				PIPE_GATING_CONTROL_DISABLE);
+-		dc->hwss.enable_display_pipe_clock_gating(
++		hws->funcs.enable_display_pipe_clock_gating(
+ 			dc->ctx,
+ 			true);
+ 	}
+@@ -2442,6 +2451,8 @@ static void dce110_program_front_end_for_pipe(
+ 	struct xfm_grph_csc_adjustment adjust;
+ 	struct out_csc_color_matrix tbl_entry;
+ 	unsigned int i;
++	struct dce_hwseq *hws = dc->hwseq;
++
+ 	DC_LOGGER_INIT();
+ 	memset(&tbl_entry, 0, sizeof(tbl_entry));
+ 
+@@ -2500,10 +2511,10 @@ static void dce110_program_front_end_for_pipe(
+ 	if (pipe_ctx->plane_state->update_flags.bits.full_update ||
+ 			pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
+ 			pipe_ctx->plane_state->update_flags.bits.gamma_change)
+-		dc->hwss.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
++		hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
+ 
+ 	if (pipe_ctx->plane_state->update_flags.bits.full_update)
+-		dc->hwss.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
++		hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
+ 
+ 	DC_LOG_SURFACE(
+ 			"Pipe:%d %p: addr hi:0x%x, "
+@@ -2606,6 +2617,7 @@ static void dce110_apply_ctx_for_surface(
+ 
+ static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	int fe_idx = pipe_ctx->plane_res.mi ?
+ 		pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
+ 
+@@ -2613,7 +2625,7 @@ static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
+ 		return;
+ 
+-	dc->hwss.enable_display_power_gating(
++	hws->funcs.enable_display_power_gating(
+ 		dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
+ 
+ 	dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
+@@ -2702,14 +2714,10 @@ static const struct hw_sequencer_funcs dce110_funcs = {
+ 	.program_gamut_remap = program_gamut_remap,
+ 	.program_output_csc = program_output_csc,
+ 	.init_hw = init_hw,
+-	.init_pipes = init_pipes,
+ 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+ 	.apply_ctx_for_surface = dce110_apply_ctx_for_surface,
+ 	.update_plane_addr = update_plane_addr,
+ 	.update_pending_status = dce110_update_pending_status,
+-	.set_input_transfer_func = dce110_set_input_transfer_func,
+-	.set_output_transfer_func = dce110_set_output_transfer_func,
+-	.power_down = dce110_power_down,
+ 	.enable_accelerated_mode = dce110_enable_accelerated_mode,
+ 	.enable_timing_synchronization = dce110_enable_timing_synchronization,
+ 	.enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
+@@ -2720,8 +2728,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
+ 	.blank_stream = dce110_blank_stream,
+ 	.enable_audio_stream = dce110_enable_audio_stream,
+ 	.disable_audio_stream = dce110_disable_audio_stream,
+-	.enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
+-	.enable_display_power_gating = dce110_enable_display_power_gating,
+ 	.disable_plane = dce110_power_down_fe,
+ 	.pipe_control_lock = dce_pipe_control_lock,
+ 	.prepare_bandwidth = dce110_prepare_bandwidth,
+@@ -2729,22 +2735,33 @@ static const struct hw_sequencer_funcs dce110_funcs = {
+ 	.set_drr = set_drr,
+ 	.get_position = get_position,
+ 	.set_static_screen_control = set_static_screen_control,
+-	.reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
+-	.enable_stream_timing = dce110_enable_stream_timing,
+-	.disable_stream_gating = NULL,
+-	.enable_stream_gating = NULL,
+ 	.setup_stereo = NULL,
+ 	.set_avmute = dce110_set_avmute,
+ 	.wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
+-	.edp_backlight_control = dce110_edp_backlight_control,
+ 	.edp_power_control = dce110_edp_power_control,
+ 	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+ 	.set_cursor_position = dce110_set_cursor_position,
+ 	.set_cursor_attribute = dce110_set_cursor_attribute
+ };
+ 
++static const struct hwseq_private_funcs dce110_private_funcs = {
++	.init_pipes = init_pipes,
++	.update_plane_addr = update_plane_addr,
++	.set_input_transfer_func = dce110_set_input_transfer_func,
++	.set_output_transfer_func = dce110_set_output_transfer_func,
++	.power_down = dce110_power_down,
++	.enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
++	.enable_display_power_gating = dce110_enable_display_power_gating,
++	.reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
++	.enable_stream_timing = dce110_enable_stream_timing,
++	.disable_stream_gating = NULL,
++	.enable_stream_gating = NULL,
++	.edp_backlight_control = dce110_edp_backlight_control,
++};
++
+ void dce110_hw_sequencer_construct(struct dc *dc)
+ {
+ 	dc->hwss = dce110_funcs;
++	dc->hwseq->funcs = dce110_private_funcs;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+index c639e1680b7b..26a9c14a58b1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+@@ -27,6 +27,7 @@
+ #define __DC_HWSS_DCE110_H__
+ 
+ #include "core_types.h"
++#include "hw_sequencer_private.h"
+ 
+ struct dc;
+ struct dc_state;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index 762f97b48f0f..75ffea78c6cc 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -1095,6 +1095,7 @@ static struct pipe_ctx *dce110_acquire_underlay(
+ 		struct dc_stream_state *stream)
+ {
+ 	struct dc *dc = stream->ctx->dc;
++	struct dce_hwseq *hws = dc->hwseq;
+ 	struct resource_context *res_ctx = &context->res_ctx;
+ 	unsigned int underlay_idx = pool->underlay_pipe_index;
+ 	struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];
+@@ -1115,7 +1116,7 @@ static struct pipe_ctx *dce110_acquire_underlay(
+ 		struct tg_color black_color = {0};
+ 		struct dc_bios *dcb = dc->ctx->dc_bios;
+ 
+-		dc->hwss.enable_display_power_gating(
++		hws->funcs.enable_display_power_gating(
+ 				dc,
+ 				pipe_ctx->stream_res.tg->inst,
+ 				dcb, PIPE_GATING_CONTROL_DISABLE);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
+index 1e4a7c13f0ed..19873ee1f78d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
+@@ -158,6 +158,6 @@ void dce112_hw_sequencer_construct(struct dc *dc)
+ 	 * structure
+ 	 */
+ 	dce110_hw_sequencer_construct(dc);
+-	dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating;
++	dc->hwseq->funcs.enable_display_power_gating = dce112_enable_display_power_gating;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h
+index e646f4a37fa2..943f1b2c5b2f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h
+@@ -27,6 +27,7 @@
+ #define __DC_HWSS_DCE112_H__
+ 
+ #include "core_types.h"
++#include "hw_sequencer_private.h"
+ 
+ struct dc;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
+index 1ca30928025e..66a13aa39c95 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
+@@ -265,7 +265,7 @@ void dce120_hw_sequencer_construct(struct dc *dc)
+ 	 * structure
+ 	 */
+ 	dce110_hw_sequencer_construct(dc);
+-	dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating;
++	dc->hwseq->funcs.enable_display_power_gating = dce120_enable_display_power_gating;
+ 	dc->hwss.update_dchub = dce120_update_dchub;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
+index c51afbd0b012..bc024534732f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
+@@ -27,6 +27,7 @@
+ #define __DC_HWSS_DCE120_H__
+ 
+ #include "core_types.h"
++#include "hw_sequencer_private.h"
+ 
+ struct dc;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
+index c4543178ba20..893261c81854 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
+@@ -74,7 +74,7 @@ void dce80_hw_sequencer_construct(struct dc *dc)
+ {
+ 	dce110_hw_sequencer_construct(dc);
+ 
+-	dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
++	dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;
+ 	dc->hwss.pipe_control_lock = dce_pipe_control_lock;
+ 	dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
+ 	dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h
+index 7a1b31def66f..e43af832d00c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h
+@@ -27,6 +27,7 @@
+ #define __DC_HWSS_DCE80_H__
+ 
+ #include "core_types.h"
++#include "hw_sequencer_private.h"
+ 
+ struct dc;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 1ed26ac33551..528a6a953be4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -641,8 +641,8 @@ static void power_on_plane(
+ 	if (REG(DC_IP_REQUEST_CNTL)) {
+ 		REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 				IP_REQUEST_EN, 1);
+-		hws->ctx->dc->hwss.dpp_pg_control(hws, plane_id, true);
+-		hws->ctx->dc->hwss.hubp_pg_control(hws, plane_id, true);
++		hws->funcs.dpp_pg_control(hws, plane_id, true);
++		hws->funcs.hubp_pg_control(hws, plane_id, true);
+ 		REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 				IP_REQUEST_EN, 0);
+ 		DC_LOG_DEBUG(
+@@ -663,7 +663,7 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc)
+ 	REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 			IP_REQUEST_EN, 1);
+ 
+-	dc->hwss.hubp_pg_control(hws, 0, false);
++	hws->funcs.hubp_pg_control(hws, 0, false);
+ 	REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 			IP_REQUEST_EN, 0);
+ 
+@@ -692,7 +692,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc)
+ 	REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 			IP_REQUEST_EN, 1);
+ 
+-	dc->hwss.hubp_pg_control(hws, 0, true);
++	hws->funcs.hubp_pg_control(hws, 0, true);
+ 	REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 			IP_REQUEST_EN, 0);
+ 
+@@ -702,14 +702,16 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc)
+ 
+ void dcn10_bios_golden_init(struct dc *dc)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	struct dc_bios *bp = dc->ctx->dc_bios;
+ 	int i;
+ 	bool allow_self_fresh_force_enable = true;
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+-	if (dc->hwss.s0i3_golden_init_wa && dc->hwss.s0i3_golden_init_wa(dc))
++	if (hws->funcs.s0i3_golden_init_wa && hws->funcs.s0i3_golden_init_wa(dc))
+ 		return;
+ #endif
++
+ 	if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)
+ 		allow_self_fresh_force_enable =
+ 				dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);
+@@ -1016,6 +1018,7 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc)
+ /* trigger HW to start disconnect plane from stream on the next vsync */
+ void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ 	int dpp_id = pipe_ctx->plane_res.dpp->inst;
+ 	struct mpc *mpc = dc->res_pool->mpc;
+@@ -1040,7 +1043,7 @@ void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 		hubp->funcs->hubp_disconnect(hubp);
+ 
+ 	if (dc->debug.sanity_checks)
+-		dc->hwss.verify_allow_pstate_change_high(dc);
++		hws->funcs.verify_allow_pstate_change_high(dc);
+ }
+ 
+ void dcn10_plane_atomic_power_down(struct dc *dc,
+@@ -1053,8 +1056,8 @@ void dcn10_plane_atomic_power_down(struct dc *dc,
+ 	if (REG(DC_IP_REQUEST_CNTL)) {
+ 		REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 				IP_REQUEST_EN, 1);
+-		dc->hwss.dpp_pg_control(hws, dpp->inst, false);
+-		dc->hwss.hubp_pg_control(hws, hubp->inst, false);
++		hws->funcs.dpp_pg_control(hws, dpp->inst, false);
++		hws->funcs.hubp_pg_control(hws, hubp->inst, false);
+ 		dpp->funcs->dpp_reset(dpp);
+ 		REG_SET(DC_IP_REQUEST_CNTL, 0,
+ 				IP_REQUEST_EN, 0);
+@@ -1068,6 +1071,7 @@ void dcn10_plane_atomic_power_down(struct dc *dc,
+  */
+ void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
+ 	int opp_id = hubp->opp_id;
+@@ -1086,7 +1090,7 @@ void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	hubp->power_gated = true;
+ 	dc->optimized_required = false; /* We're powering off, no need to optimize */
+ 
+-	dc->hwss.plane_atomic_power_down(dc,
++	hws->funcs.plane_atomic_power_down(dc,
+ 			pipe_ctx->plane_res.dpp,
+ 			pipe_ctx->plane_res.hubp);
+ 
+@@ -1100,12 +1104,13 @@ void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 
+ void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	DC_LOGGER_INIT(dc->ctx->logger);
+ 
+ 	if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
+ 		return;
+ 
+-	dc->hwss.plane_atomic_disable(dc, pipe_ctx);
++	hws->funcs.plane_atomic_disable(dc, pipe_ctx);
+ 
+ 	apply_DEGVIDCN10_253_wa(dc);
+ 
+@@ -1116,6 +1121,7 @@ void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
+ {
+ 	int i;
++	struct dce_hwseq *hws = dc->hwseq;
+ 	bool can_apply_seamless_boot = false;
+ 
+ 	for (i = 0; i < context->stream_count; i++) {
+@@ -1140,8 +1146,8 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
+ 		 * command table.
+ 		 */
+ 		if (tg->funcs->is_tg_enabled(tg)) {
+-			if (dc->hwss.init_blank != NULL) {
+-				dc->hwss.init_blank(dc, tg);
++			if (hws->funcs.init_blank != NULL) {
++				hws->funcs.init_blank(dc, tg);
+ 				tg->funcs->lock(tg);
+ 			} else {
+ 				tg->funcs->lock(tg);
+@@ -1198,7 +1204,7 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
+ 		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
+ 		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
+ 
+-		dc->hwss.plane_atomic_disconnect(dc, pipe_ctx);
++		hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
+ 
+ 		if (tg->funcs->is_tg_enabled(tg))
+ 			tg->funcs->unlock(tg);
+@@ -1244,15 +1250,15 @@ void dcn10_init_hw(struct dc *dc)
+ 		}
+ 
+ 		//Enable ability to power gate / don't force power on permanently
+-		dc->hwss.enable_power_gating_plane(hws, true);
++		hws->funcs.enable_power_gating_plane(hws, true);
+ 
+ 		return;
+ 	}
+ 
+ 	if (!dcb->funcs->is_accelerated_mode(dcb))
+-		dc->hwss.disable_vga(dc->hwseq);
++		hws->funcs.disable_vga(dc->hwseq);
+ 
+-	dc->hwss.bios_golden_init(dc);
++	hws->funcs.bios_golden_init(dc);
+ 	if (dc->ctx->dc_bios->fw_info_valid) {
+ 		res_pool->ref_clocks.xtalin_clock_inKhz =
+ 				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
+@@ -1293,10 +1299,12 @@ void dcn10_init_hw(struct dc *dc)
+ 			link->link_status.link_active = true;
+ 	}
+ 
++#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	/* Power gate DSCs */
+ 	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
+-		if (dc->hwss.dsc_pg_control != NULL)
+-			dc->hwss.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
++		if (hws->funcs.dsc_pg_control != NULL)
++			hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
++#endif
+ 
+ 	/* If taking control over from VBIOS, we may want to optimize our first
+ 	 * mode set, so we need to skip powering down pipes until we know which
+@@ -1305,7 +1313,7 @@ void dcn10_init_hw(struct dc *dc)
+ 	 * everything down.
+ 	 */
+ 	if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
+-		dc->hwss.init_pipes(dc, dc->current_state);
++		hws->funcs.init_pipes(dc, dc->current_state);
+ 	}
+ 
+ 	for (i = 0; i < res_pool->audio_count; i++) {
+@@ -1337,7 +1345,7 @@ void dcn10_init_hw(struct dc *dc)
+ 		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
+ 	}
+ 
+-	dc->hwss.enable_power_gating_plane(dc->hwseq, true);
++	hws->funcs.enable_power_gating_plane(dc->hwseq, true);
+ 
+ 	if (dc->clk_mgr->funcs->notify_wm_ranges)
+ 		dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
+@@ -1349,6 +1357,7 @@ void dcn10_reset_hw_ctx_wrap(
+ 		struct dc_state *context)
+ {
+ 	int i;
++	struct dce_hwseq *hws = dc->hwseq;
+ 
+ 	/* Reset Back End*/
+ 	for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
+@@ -1367,8 +1376,8 @@ void dcn10_reset_hw_ctx_wrap(
+ 			struct clock_source *old_clk = pipe_ctx_old->clock_source;
+ 
+ 			dcn10_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
+-			if (dc->hwss.enable_stream_gating)
+-				dc->hwss.enable_stream_gating(dc, pipe_ctx);
++			if (hws->funcs.enable_stream_gating)
++				hws->funcs.enable_stream_gating(dc, pipe_ctx);
+ 			if (old_clk)
+ 				old_clk->funcs->cs_power_down(old_clk);
+ 		}
+@@ -1545,6 +1554,8 @@ void dcn10_pipe_control_lock(
+ 	struct pipe_ctx *pipe,
+ 	bool lock)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
++
+ 	/* use TG master update lock to lock everything on the TG
+ 	 * therefore only top pipe need to lock
+ 	 */
+@@ -1552,7 +1563,7 @@ void dcn10_pipe_control_lock(
+ 		return;
+ 
+ 	if (dc->debug.sanity_checks)
+-		dc->hwss.verify_allow_pstate_change_high(dc);
++		hws->funcs.verify_allow_pstate_change_high(dc);
+ 
+ 	if (lock)
+ 		pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
+@@ -1560,7 +1571,7 @@ void dcn10_pipe_control_lock(
+ 		pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
+ 
+ 	if (dc->debug.sanity_checks)
+-		dc->hwss.verify_allow_pstate_change_high(dc);
++		hws->funcs.verify_allow_pstate_change_high(dc);
+ }
+ 
+ static bool wait_for_reset_trigger_to_occur(
+@@ -1868,7 +1879,7 @@ static void dcn10_enable_plane(
+ 	struct dce_hwseq *hws = dc->hwseq;
+ 
+ 	if (dc->debug.sanity_checks) {
+-		dc->hwss.verify_allow_pstate_change_high(dc);
++		hws->funcs.verify_allow_pstate_change_high(dc);
+ 	}
+ 
+ 	undo_DEGVIDCN10_253_wa(dc);
+@@ -1925,7 +1936,7 @@ static void dcn10_enable_plane(
+ 		dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
+ 
+ 	if (dc->debug.sanity_checks) {
+-		dc->hwss.verify_allow_pstate_change_high(dc);
++		hws->funcs.verify_allow_pstate_change_high(dc);
+ 	}
+ }
+ 
+@@ -2102,6 +2113,7 @@ static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state
+ 
+ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ 	struct mpcc_blnd_cfg blnd_cfg = {{0}};
+ 	bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
+@@ -2111,10 +2123,10 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
+ 
+ 	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
+-		dc->hwss.get_hdr_visual_confirm_color(
++		hws->funcs.get_hdr_visual_confirm_color(
+ 				pipe_ctx, &blnd_cfg.black_color);
+ 	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
+-		dc->hwss.get_surface_visual_confirm_color(
++		hws->funcs.get_surface_visual_confirm_color(
+ 				pipe_ctx, &blnd_cfg.black_color);
+ 	} else {
+ 		color_space_to_black_color(
+@@ -2201,6 +2213,7 @@ static void dcn10_update_dchubp_dpp(
+ 	struct pipe_ctx *pipe_ctx,
+ 	struct dc_state *context)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
+ 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+@@ -2259,7 +2272,7 @@ static void dcn10_update_dchubp_dpp(
+ 	if (plane_state->update_flags.bits.full_update ||
+ 		plane_state->update_flags.bits.per_pixel_alpha_change ||
+ 		plane_state->update_flags.bits.global_alpha_change)
+-		dc->hwss.update_mpcc(dc, pipe_ctx);
++		hws->funcs.update_mpcc(dc, pipe_ctx);
+ 
+ 	if (plane_state->update_flags.bits.full_update ||
+ 		plane_state->update_flags.bits.per_pixel_alpha_change ||
+@@ -2319,7 +2332,7 @@ static void dcn10_update_dchubp_dpp(
+ 
+ 	hubp->power_gated = false;
+ 
+-	dc->hwss.update_plane_addr(dc, pipe_ctx);
++	hws->funcs.update_plane_addr(dc, pipe_ctx);
+ 
+ 	if (is_pipe_tree_visible(pipe_ctx))
+ 		hubp->funcs->set_blank(hubp, false);
+@@ -2395,17 +2408,19 @@ void dcn10_program_pipe(
+ 		struct pipe_ctx *pipe_ctx,
+ 		struct dc_state *context)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
++
+ 	if (pipe_ctx->plane_state->update_flags.bits.full_update)
+ 		dcn10_enable_plane(dc, pipe_ctx, context);
+ 
+ 	dcn10_update_dchubp_dpp(dc, pipe_ctx, context);
+ 
+-	dc->hwss.set_hdr_multiplier(pipe_ctx);
++	hws->funcs.set_hdr_multiplier(pipe_ctx);
+ 
+ 	if (pipe_ctx->plane_state->update_flags.bits.full_update ||
+ 			pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
+ 			pipe_ctx->plane_state->update_flags.bits.gamma_change)
+-		dc->hwss.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
++		hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
+ 
+ 	/* dcn10_translate_regamma_to_hw_format takes 750us to finish
+ 	 * only do gamma programming for full update.
+@@ -2414,7 +2429,7 @@ void dcn10_program_pipe(
+ 	 * doing heavy calculation and programming
+ 	 */
+ 	if (pipe_ctx->plane_state->update_flags.bits.full_update)
+-		dc->hwss.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
++		hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
+ }
+ 
+ static void dcn10_program_all_pipe_in_tree(
+@@ -2422,6 +2437,8 @@ static void dcn10_program_all_pipe_in_tree(
+ 		struct pipe_ctx *pipe_ctx,
+ 		struct dc_state *context)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
++
+ 	if (pipe_ctx->top_pipe == NULL) {
+ 		bool blank = !is_pipe_tree_visible(pipe_ctx);
+ 
+@@ -2435,14 +2452,14 @@ static void dcn10_program_all_pipe_in_tree(
+ 		pipe_ctx->stream_res.tg->funcs->set_vtg_params(
+ 				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+ 
+-		if (dc->hwss.setup_vupdate_interrupt)
+-			dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
++		if (hws->funcs.setup_vupdate_interrupt)
++			hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
+ 
+-		dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
++		hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
+ 	}
+ 
+ 	if (pipe_ctx->plane_state != NULL)
+-		dc->hwss.program_pipe(dc, pipe_ctx, context);
++		hws->funcs.program_pipe(dc, pipe_ctx, context);
+ 
+ 	if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
+ 		dcn10_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
+@@ -2478,6 +2495,7 @@ void dcn10_apply_ctx_for_surface(
+ 		int num_planes,
+ 		struct dc_state *context)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	int i;
+ 	struct timing_generator *tg;
+ 	uint32_t underflow_check_delay_us;
+@@ -2497,8 +2515,8 @@ void dcn10_apply_ctx_for_surface(
+ 
+ 	underflow_check_delay_us = dc->debug.underflow_assert_delay_us;
+ 
+-	if (underflow_check_delay_us != 0xFFFFFFFF && dc->hwss.did_underflow_occur)
+-		ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
++	if (underflow_check_delay_us != 0xFFFFFFFF && hws->funcs.did_underflow_occur)
++		ASSERT(hws->funcs.did_underflow_occur(dc, top_pipe_to_program));
+ 
+ 	if (interdependent_update)
+ 		dcn10_lock_all_pipes(dc, context, true);
+@@ -2508,12 +2526,12 @@ void dcn10_apply_ctx_for_surface(
+ 	if (underflow_check_delay_us != 0xFFFFFFFF)
+ 		udelay(underflow_check_delay_us);
+ 
+-	if (underflow_check_delay_us != 0xFFFFFFFF && dc->hwss.did_underflow_occur)
+-		ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
++	if (underflow_check_delay_us != 0xFFFFFFFF && hws->funcs.did_underflow_occur)
++		ASSERT(hws->funcs.did_underflow_occur(dc, top_pipe_to_program));
+ 
+ 	if (num_planes == 0) {
+ 		/* OTG blank before remove all front end */
+-		dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
++		hws->funcs.blank_pixel_data(dc, top_pipe_to_program, true);
+ 	}
+ 
+ 	/* Disconnect unused mpcc */
+@@ -2539,7 +2557,7 @@ void dcn10_apply_ctx_for_surface(
+ 		    old_pipe_ctx->plane_state &&
+ 		    old_pipe_ctx->stream_res.tg == tg) {
+ 
+-			dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx);
++			hws->funcs.plane_atomic_disconnect(dc, old_pipe_ctx);
+ 			removed_pipe[i] = true;
+ 
+ 			DC_LOG_DC("Reset mpcc for pipe %d\n",
+@@ -2550,9 +2568,11 @@ void dcn10_apply_ctx_for_surface(
+ 	if (num_planes > 0)
+ 		dcn10_program_all_pipe_in_tree(dc, top_pipe_to_program, context);
+ 
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	/* Program secondary blending tree and writeback pipes */
+-	if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree))
+-		dc->hwss.program_all_writeback_pipes_in_tree(dc, stream, context);
++	if ((stream->num_wb_info > 0) && (hws->funcs.program_all_writeback_pipes_in_tree))	
++		hws->funcs.program_all_writeback_pipes_in_tree(dc, stream, context);
++#endif
+ 	if (interdependent_update)
+ 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ 			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+@@ -2609,10 +2629,11 @@ void dcn10_prepare_bandwidth(
+ 		struct dc *dc,
+ 		struct dc_state *context)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	struct hubbub *hubbub = dc->res_pool->hubbub;
+ 
+ 	if (dc->debug.sanity_checks)
+-		dc->hwss.verify_allow_pstate_change_high(dc);
++		hws->funcs.verify_allow_pstate_change_high(dc);
+ 
+ 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 		if (context->stream_count == 0)
+@@ -2634,17 +2655,18 @@ void dcn10_prepare_bandwidth(
+ 		dcn_bw_notify_pplib_of_wm_ranges(dc);
+ 
+ 	if (dc->debug.sanity_checks)
+-		dc->hwss.verify_allow_pstate_change_high(dc);
++		hws->funcs.verify_allow_pstate_change_high(dc);
+ }
+ 
+ void dcn10_optimize_bandwidth(
+ 		struct dc *dc,
+ 		struct dc_state *context)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	struct hubbub *hubbub = dc->res_pool->hubbub;
+ 
+ 	if (dc->debug.sanity_checks)
+-		dc->hwss.verify_allow_pstate_change_high(dc);
++		hws->funcs.verify_allow_pstate_change_high(dc);
+ 
+ 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 		if (context->stream_count == 0)
+@@ -2666,7 +2688,7 @@ void dcn10_optimize_bandwidth(
+ 		dcn_bw_notify_pplib_of_wm_ranges(dc);
+ 
+ 	if (dc->debug.sanity_checks)
+-		dc->hwss.verify_allow_pstate_change_high(dc);
++		hws->funcs.verify_allow_pstate_change_high(dc);
+ }
+ 
+ void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
+@@ -2808,10 +2830,11 @@ void dcn10_wait_for_mpcc_disconnect(
+ 		struct resource_pool *res_pool,
+ 		struct pipe_ctx *pipe_ctx)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	int mpcc_inst;
+ 
+ 	if (dc->debug.sanity_checks) {
+-		dc->hwss.verify_allow_pstate_change_high(dc);
++		hws->funcs.verify_allow_pstate_change_high(dc);
+ 	}
+ 
+ 	if (!pipe_ctx->stream_res.opp)
+@@ -2828,7 +2851,7 @@ void dcn10_wait_for_mpcc_disconnect(
+ 	}
+ 
+ 	if (dc->debug.sanity_checks) {
+-		dc->hwss.verify_allow_pstate_change_high(dc);
++		hws->funcs.verify_allow_pstate_change_high(dc);
+ 	}
+ 
+ }
+@@ -3127,6 +3150,7 @@ void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
+ 	struct encoder_unblank_param params = { { 0 } };
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	struct dc_link *link = stream->link;
++	struct dce_hwseq *hws = link->dc->hwseq;
+ 
+ 	/* only 3 items below are used by unblank */
+ 	params.timing = pipe_ctx->stream->timing;
+@@ -3140,7 +3164,7 @@ void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
+ 	}
+ 
+ 	if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
+-		link->dc->hwss.edp_backlight_control(link, true);
++		hws->funcs.edp_backlight_control(link, true);
+ 	}
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+index 5aad3922be6c..55b8f3b2fc4e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+@@ -27,6 +27,7 @@
+ #define __DC_HWSS_DCN10_H__
+ 
+ #include "core_types.h"
++#include "hw_sequencer_private.h"
+ 
+ struct dc;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+index 38923f3120ee..e7e5352ec424 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+@@ -23,25 +23,19 @@
+  *
+  */
+ 
++#include "hw_sequencer_private.h"
+ #include "dce110/dce110_hw_sequencer.h"
+ #include "dcn10_hw_sequencer.h"
+ 
+ static const struct hw_sequencer_funcs dcn10_funcs = {
+ 	.program_gamut_remap = dcn10_program_gamut_remap,
+ 	.init_hw = dcn10_init_hw,
+-	.init_pipes = dcn10_init_pipes,
+ 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+ 	.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
+ 	.update_plane_addr = dcn10_update_plane_addr,
+-	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
+-	.program_pipe = dcn10_program_pipe,
+ 	.update_dchub = dcn10_update_dchub,
+-	.update_mpcc = dcn10_update_mpcc,
+ 	.update_pending_status = dcn10_update_pending_status,
+-	.set_input_transfer_func = dcn10_set_input_transfer_func,
+-	.set_output_transfer_func = dcn10_set_output_transfer_func,
+ 	.program_output_csc = dcn10_program_output_csc,
+-	.power_down = dce110_power_down,
+ 	.enable_accelerated_mode = dce110_enable_accelerated_mode,
+ 	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
+ 	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
+@@ -53,14 +47,10 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
+ 	.blank_stream = dce110_blank_stream,
+ 	.enable_audio_stream = dce110_enable_audio_stream,
+ 	.disable_audio_stream = dce110_disable_audio_stream,
+-	.enable_display_power_gating = dcn10_dummy_display_power_gating,
+ 	.disable_plane = dcn10_disable_plane,
+-	.blank_pixel_data = dcn10_blank_pixel_data,
+ 	.pipe_control_lock = dcn10_pipe_control_lock,
+ 	.prepare_bandwidth = dcn10_prepare_bandwidth,
+ 	.optimize_bandwidth = dcn10_optimize_bandwidth,
+-	.reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
+-	.enable_stream_timing = dcn10_enable_stream_timing,
+ 	.set_drr = dcn10_set_drr,
+ 	.get_position = dcn10_get_position,
+ 	.set_static_screen_control = dcn10_set_static_screen_control,
+@@ -70,18 +60,34 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
+ 	.get_hw_state = dcn10_get_hw_state,
+ 	.clear_status_bits = dcn10_clear_status_bits,
+ 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+-	.edp_backlight_control = dce110_edp_backlight_control,
+ 	.edp_power_control = dce110_edp_power_control,
+ 	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+ 	.set_cursor_position = dcn10_set_cursor_position,
+ 	.set_cursor_attribute = dcn10_set_cursor_attribute,
+ 	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
+-	.disable_stream_gating = NULL,
+-	.enable_stream_gating = NULL,
+ 	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
+-	.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
+ 	.set_clock = dcn10_set_clock,
+ 	.get_clock = dcn10_get_clock,
++	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
++};
++
++static const struct hwseq_private_funcs dcn10_private_funcs = {
++	.init_pipes = dcn10_init_pipes,
++	.update_plane_addr = dcn10_update_plane_addr,
++	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
++	.program_pipe = dcn10_program_pipe,
++	.update_mpcc = dcn10_update_mpcc,
++	.set_input_transfer_func = dcn10_set_input_transfer_func,
++	.set_output_transfer_func = dcn10_set_output_transfer_func,
++	.power_down = dce110_power_down,
++	.enable_display_power_gating = dcn10_dummy_display_power_gating,
++	.blank_pixel_data = dcn10_blank_pixel_data,
++	.reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
++	.enable_stream_timing = dcn10_enable_stream_timing,
++	.edp_backlight_control = dce110_edp_backlight_control,
++	.disable_stream_gating = NULL,
++	.enable_stream_gating = NULL,
++	.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
+ 	.did_underflow_occur = dcn10_did_underflow_occur,
+ 	.init_blank = NULL,
+ 	.disable_vga = dcn10_disable_vga,
+@@ -96,10 +102,10 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
+ 	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
+ 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
+ 	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
+-	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
+ };
+ 
+ void dcn10_hw_sequencer_construct(struct dc *dc)
+ {
+ 	dc->hwss = dcn10_funcs;
++	dc->hwseq->funcs = dcn10_private_funcs;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 937ecb28948d..d99e882bd555 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -276,6 +276,7 @@ void dcn20_init_blank(
+ 		struct dc *dc,
+ 		struct timing_generator *tg)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	enum dc_color_space color_space;
+ 	struct tg_color black_color = {0};
+ 	struct output_pixel_processor *opp = NULL;
+@@ -323,7 +324,7 @@ void dcn20_init_blank(
+ 				otg_active_height);
+ 	}
+ 
+-	dc->hwss.wait_for_blank_complete(opp);
++	hws->funcs.wait_for_blank_complete(opp);
+ }
+ 
+ void dcn20_dsc_pg_control(
+@@ -556,6 +557,7 @@ void dcn20_hubp_pg_control(
+  */
+ void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
+ 
+@@ -576,7 +578,7 @@ void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	hubp->power_gated = true;
+ 	dc->optimized_required = false; /* We're powering off, no need to optimize */
+ 
+-	dc->hwss.plane_atomic_power_down(dc,
++	hws->funcs.plane_atomic_power_down(dc,
+ 			pipe_ctx->plane_res.dpp,
+ 			pipe_ctx->plane_res.hubp);
+ 
+@@ -607,6 +609,7 @@ enum dc_status dcn20_enable_stream_timing(
+ 		struct dc_state *context,
+ 		struct dc *dc)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	struct drr_params params = {0};
+ 	unsigned int event_triggers = 0;
+@@ -666,7 +669,7 @@ enum dc_status dcn20_enable_stream_timing(
+ 			pipe_ctx->stream_res.opp,
+ 			true);
+ 
+-	dc->hwss.blank_pixel_data(dc, pipe_ctx, true);
++	hws->funcs.blank_pixel_data(dc, pipe_ctx, true);
+ 
+ 	/* VTG is  within DCHUB command block. DCFCLK is always on */
+ 	if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
+@@ -674,7 +677,7 @@ enum dc_status dcn20_enable_stream_timing(
+ 		return DC_ERROR_UNEXPECTED;
+ 	}
+ 
+-	dc->hwss.wait_for_blank_complete(pipe_ctx->stream_res.opp);
++	hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
+ 
+ 	params.vertical_total_min = stream->adjust.v_total_min;
+ 	params.vertical_total_max = stream->adjust.v_total_max;
+@@ -824,6 +827,7 @@ bool dcn20_set_input_transfer_func(struct dc *dc,
+ 				struct pipe_ctx *pipe_ctx,
+ 				const struct dc_plane_state *plane_state)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
+ 	const struct dc_transfer_func *tf = NULL;
+ 	bool result = true;
+@@ -832,8 +836,8 @@ bool dcn20_set_input_transfer_func(struct dc *dc,
+ 	if (dpp_base == NULL || plane_state == NULL)
+ 		return false;
+ 
+-	dc->hwss.set_shaper_3dlut(pipe_ctx, plane_state);
+-	dc->hwss.set_blend_lut(pipe_ctx, plane_state);
++	hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
++	hws->funcs.set_blend_lut(pipe_ctx, plane_state);
+ 
+ 	if (plane_state->in_transfer_func)
+ 		tf = plane_state->in_transfer_func;
+@@ -1296,6 +1300,7 @@ static void dcn20_update_dchubp_dpp(
+ 	struct pipe_ctx *pipe_ctx,
+ 	struct dc_state *context)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
+ 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+@@ -1360,7 +1365,7 @@ static void dcn20_update_dchubp_dpp(
+ 				old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
+ 			}
+ 		}
+-		dc->hwss.update_mpcc(dc, pipe_ctx);
++		hws->funcs.update_mpcc(dc, pipe_ctx);
+ 	}
+ 
+ 	if (pipe_ctx->update_flags.bits.scaler ||
+@@ -1435,7 +1440,7 @@ static void dcn20_update_dchubp_dpp(
+ 	}
+ 
+ 	if (pipe_ctx->update_flags.bits.enable || plane_state->update_flags.bits.addr_update)
+-		dc->hwss.update_plane_addr(dc, pipe_ctx);
++		hws->funcs.update_plane_addr(dc, pipe_ctx);
+ 
+ 	if (pipe_ctx->update_flags.bits.enable)
+ 		hubp->funcs->set_blank(hubp, false);
+@@ -1447,10 +1452,11 @@ static void dcn20_program_pipe(
+ 		struct pipe_ctx *pipe_ctx,
+ 		struct dc_state *context)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	/* Only need to unblank on top pipe */
+ 	if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
+ 			&& !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
+-		dc->hwss.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
++		hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
+ 
+ 	if (pipe_ctx->update_flags.bits.global_sync) {
+ 		pipe_ctx->stream_res.tg->funcs->program_global_sync(
+@@ -1463,12 +1469,12 @@ static void dcn20_program_pipe(
+ 		pipe_ctx->stream_res.tg->funcs->set_vtg_params(
+ 				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+ 
+-		if (dc->hwss.setup_vupdate_interrupt)
+-			dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
++		if (hws->funcs.setup_vupdate_interrupt)
++			hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
+ 	}
+ 
+ 	if (pipe_ctx->update_flags.bits.odm)
+-		dc->hwss.update_odm(dc, context, pipe_ctx);
++		hws->funcs.update_odm(dc, context, pipe_ctx);
+ 
+ 	if (pipe_ctx->update_flags.bits.enable)
+ 		dcn20_enable_plane(dc, pipe_ctx, context);
+@@ -1478,19 +1484,19 @@ static void dcn20_program_pipe(
+ 
+ 	if (pipe_ctx->update_flags.bits.enable
+ 			|| pipe_ctx->plane_state->update_flags.bits.hdr_mult)
+-		dc->hwss.set_hdr_multiplier(pipe_ctx);
++		hws->funcs.set_hdr_multiplier(pipe_ctx);
+ 
+ 	if (pipe_ctx->update_flags.bits.enable ||
+ 			pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
+ 			pipe_ctx->plane_state->update_flags.bits.gamma_change)
+-		dc->hwss.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
++		hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
+ 
+ 	/* dcn10_translate_regamma_to_hw_format takes 750us to finish
+ 	 * only do gamma programming for powering on, internal memcmp to avoid
+ 	 * updating on slave planes
+ 	 */
+ 	if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf)
+-		dc->hwss.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
++		hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
+ 
+ 	/* If the pipe has been enabled or has a different opp, we
+ 	 * should reprogram the fmt. This deals with cases where
+@@ -1530,6 +1536,7 @@ void dcn20_program_front_end_for_ctx(
+ {
+ 	const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
+ 	int i;
++	struct dce_hwseq *hws = dc->hwseq;
+ 	bool pipe_locked[MAX_PIPES] = {false};
+ 	DC_LOGGER_INIT(dc->ctx->logger);
+ 
+@@ -1561,13 +1568,13 @@ void dcn20_program_front_end_for_ctx(
+ 				&& !context->res_ctx.pipe_ctx[i].top_pipe
+ 				&& !context->res_ctx.pipe_ctx[i].prev_odm_pipe
+ 				&& context->res_ctx.pipe_ctx[i].stream)
+-			dc->hwss.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
++			hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
+ 
+ 	/* Disconnect mpcc */
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++)
+ 		if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
+ 				|| context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
+-			dc->hwss.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
++			hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
+ 			DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
+ 		}
+ 
+@@ -1587,8 +1594,8 @@ void dcn20_program_front_end_for_ctx(
+ 			pipe = &context->res_ctx.pipe_ctx[i];
+ 			if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0
+ 					&& (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw)
+-					&& dc->hwss.program_all_writeback_pipes_in_tree)
+-				dc->hwss.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
++					&& hws->funcs.program_all_writeback_pipes_in_tree)
++				hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
+ 		}
+ 	}
+ 
+@@ -1673,6 +1680,7 @@ bool dcn20_update_bandwidth(
+ 		struct dc_state *context)
+ {
+ 	int i;
++	struct dce_hwseq *hws = dc->hwseq;
+ 
+ 	/* recalculate DML parameters */
+ 	if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
+@@ -1702,10 +1710,10 @@ bool dcn20_update_bandwidth(
+ 					pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+ 
+ 			if (pipe_ctx->prev_odm_pipe == NULL)
+-				dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
++				hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
+ 
+-			if (dc->hwss.setup_vupdate_interrupt)
+-				dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
++			if (hws->funcs.setup_vupdate_interrupt)
++				hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
+ 		}
+ 
+ 		pipe_ctx->plane_res.hubp->funcs->hubp_setup(
+@@ -1942,6 +1950,7 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
+ 	struct encoder_unblank_param params = { { 0 } };
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+ 	struct dc_link *link = stream->link;
++	struct dce_hwseq *hws = link->dc->hwseq;
+ 	struct pipe_ctx *odm_pipe;
+ 
+ 	params.opp_cnt = 1;
+@@ -1962,7 +1971,7 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
+ 	}
+ 
+ 	if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
+-		link->dc->hwss.edp_backlight_control(link, true);
++		hws->funcs.edp_backlight_control(link, true);
+ 	}
+ }
+ 
+@@ -2050,6 +2059,7 @@ void dcn20_reset_hw_ctx_wrap(
+ 		struct dc_state *context)
+ {
+ 	int i;
++	struct dce_hwseq *hws = dc->hwseq;
+ 
+ 	/* Reset Back End*/
+ 	for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
+@@ -2068,8 +2078,8 @@ void dcn20_reset_hw_ctx_wrap(
+ 			struct clock_source *old_clk = pipe_ctx_old->clock_source;
+ 
+ 			dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
+-			if (dc->hwss.enable_stream_gating)
+-				dc->hwss.enable_stream_gating(dc, pipe_ctx);
++			if (hws->funcs.enable_stream_gating)
++				hws->funcs.enable_stream_gating(dc, pipe_ctx);
+ 			if (old_clk)
+ 				old_clk->funcs->cs_power_down(old_clk);
+ 		}
+@@ -2100,6 +2110,7 @@ void dcn20_get_mpctree_visual_confirm_color(
+ 
+ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ {
++	struct dce_hwseq *hws = dc->hwseq;
+ 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+ 	struct mpcc_blnd_cfg blnd_cfg = { {0} };
+ 	bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
+@@ -2110,10 +2121,10 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 
+ 	// input to MPCC is always RGB, by default leave black_color at 0
+ 	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
+-		dc->hwss.get_hdr_visual_confirm_color(
++		hws->funcs.get_hdr_visual_confirm_color(
+ 				pipe_ctx, &blnd_cfg.black_color);
+ 	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
+-		dc->hwss.get_surface_visual_confirm_color(
++		hws->funcs.get_surface_visual_confirm_color(
+ 				pipe_ctx, &blnd_cfg.black_color);
+ 	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
+ 		dcn20_get_mpctree_visual_confirm_color(
+@@ -2269,13 +2280,13 @@ void dcn20_fpga_init_hw(struct dc *dc)
+ 		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
+ 
+ 	//Enable ability to power gate / don't force power on permanently
+-	dc->hwss.enable_power_gating_plane(hws, true);
++	hws->funcs.enable_power_gating_plane(hws, true);
+ 
+ 	// Specific to FPGA dccg and registers
+ 	REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
+ 	REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
+ 
+-	dc->hwss.dccg_init(hws);
++	hws->funcs.dccg_init(hws);
+ 
+ 	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
+ 	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
+@@ -2339,7 +2350,7 @@ void dcn20_fpga_init_hw(struct dc *dc)
+ 		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
+ 		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
+ 		/*to do*/
+-		dc->hwss.plane_atomic_disconnect(dc, pipe_ctx);
++		hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
+ 	}
+ 
+ 	/* initialize DWB pointer to MCIF_WB */
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+index f58b69c1b321..fe23a24c3325 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+@@ -26,6 +26,8 @@
+ #ifndef __DC_HWSS_DCN20_H__
+ #define __DC_HWSS_DCN20_H__
+ 
++#include "hw_sequencer_private.h"
++
+ bool dcn20_set_blend_lut(
+ 	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
+ bool dcn20_set_shaper_3dlut(
+@@ -111,6 +113,7 @@ void dcn20_disable_writeback(
+ void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
+ bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx);
+ void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
++void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);
+ void dcn20_init_vm_ctx(
+ 		struct dce_hwseq *hws,
+ 		struct dc *dc,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+index 10493777d192..7ac145ef165f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+@@ -30,19 +30,13 @@
+ static const struct hw_sequencer_funcs dcn20_funcs = {
+ 	.program_gamut_remap = dcn10_program_gamut_remap,
+ 	.init_hw = dcn10_init_hw,
+-	.init_pipes = dcn10_init_pipes,
+ 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+ 	.apply_ctx_for_surface = NULL,
+ 	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+ 	.update_plane_addr = dcn20_update_plane_addr,
+-	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
+ 	.update_dchub = dcn10_update_dchub,
+-	.update_mpcc = dcn20_update_mpcc,
+ 	.update_pending_status = dcn10_update_pending_status,
+-	.set_input_transfer_func = dcn20_set_input_transfer_func,
+-	.set_output_transfer_func = dcn20_set_output_transfer_func,
+ 	.program_output_csc = dcn20_program_output_csc,
+-	.power_down = dce110_power_down,
+ 	.enable_accelerated_mode = dce110_enable_accelerated_mode,
+ 	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
+ 	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
+@@ -54,16 +48,12 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
+ 	.blank_stream = dce110_blank_stream,
+ 	.enable_audio_stream = dce110_enable_audio_stream,
+ 	.disable_audio_stream = dce110_disable_audio_stream,
+-	.enable_display_power_gating = dcn10_dummy_display_power_gating,
+ 	.disable_plane = dcn20_disable_plane,
+-	.blank_pixel_data = dcn20_blank_pixel_data,
+ 	.pipe_control_lock = dcn20_pipe_control_lock,
+ 	.pipe_control_lock_global = dcn20_pipe_control_lock_global,
+ 	.prepare_bandwidth = dcn20_prepare_bandwidth,
+ 	.optimize_bandwidth = dcn20_optimize_bandwidth,
+ 	.update_bandwidth = dcn20_update_bandwidth,
+-	.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
+-	.enable_stream_timing = dcn20_enable_stream_timing,
+ 	.set_drr = dcn10_set_drr,
+ 	.get_position = dcn10_get_position,
+ 	.set_static_screen_control = dcn10_set_static_screen_control,
+@@ -73,18 +63,42 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
+ 	.get_hw_state = dcn10_get_hw_state,
+ 	.clear_status_bits = dcn10_clear_status_bits,
+ 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+-	.edp_backlight_control = dce110_edp_backlight_control,
+ 	.edp_power_control = dce110_edp_power_control,
+ 	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+ 	.set_cursor_position = dcn10_set_cursor_position,
+ 	.set_cursor_attribute = dcn10_set_cursor_attribute,
+ 	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
+-	.disable_stream_gating = dcn20_disable_stream_gating,
+-	.enable_stream_gating = dcn20_enable_stream_gating,
+ 	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
+-	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
+ 	.set_clock = dcn10_set_clock,
+ 	.get_clock = dcn10_get_clock,
++	.program_triplebuffer = dcn20_program_triple_buffer,
++	.enable_writeback = dcn20_enable_writeback,
++	.disable_writeback = dcn20_disable_writeback,
++	.dmdata_status_done = dcn20_dmdata_status_done,
++	.program_dmdata_engine = dcn20_program_dmdata_engine,
++	.set_dmdata_attributes = dcn20_set_dmdata_attributes,
++	.init_sys_ctx = dcn20_init_sys_ctx,
++	.init_vm_ctx = dcn20_init_vm_ctx,
++	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
++	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
++};
++
++static const struct hwseq_private_funcs dcn20_private_funcs = {
++	.init_pipes = dcn10_init_pipes,
++	.update_plane_addr = dcn20_update_plane_addr,
++	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
++	.update_mpcc = dcn20_update_mpcc,
++	.set_input_transfer_func = dcn20_set_input_transfer_func,
++	.set_output_transfer_func = dcn20_set_output_transfer_func,
++	.power_down = dce110_power_down,
++	.enable_display_power_gating = dcn10_dummy_display_power_gating,
++	.blank_pixel_data = dcn20_blank_pixel_data,
++	.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
++	.enable_stream_timing = dcn20_enable_stream_timing,
++	.edp_backlight_control = dce110_edp_backlight_control,
++	.disable_stream_gating = dcn20_disable_stream_gating,
++	.enable_stream_gating = dcn20_enable_stream_gating,
++	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
+ 	.did_underflow_occur = dcn10_did_underflow_occur,
+ 	.init_blank = dcn20_init_blank,
+ 	.disable_vga = dcn20_disable_vga,
+@@ -95,15 +109,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
+ 	.dpp_pg_control = dcn20_dpp_pg_control,
+ 	.hubp_pg_control = dcn20_hubp_pg_control,
+ 	.dsc_pg_control = NULL,
+-	.program_triplebuffer = dcn20_program_triple_buffer,
+-	.enable_writeback = dcn20_enable_writeback,
+-	.disable_writeback = dcn20_disable_writeback,
+ 	.update_odm = dcn20_update_odm,
+-	.dmdata_status_done = dcn20_dmdata_status_done,
+-	.program_dmdata_engine = dcn20_program_dmdata_engine,
+-	.init_sys_ctx = dcn20_init_sys_ctx,
+-	.init_vm_ctx = dcn20_init_vm_ctx,
+-	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	.dsc_pg_control = dcn20_dsc_pg_control,
+ #else
+@@ -117,15 +123,15 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
+ 	.dccg_init = dcn20_dccg_init,
+ 	.set_blend_lut = dcn20_set_blend_lut,
+ 	.set_shaper_3dlut = dcn20_set_shaper_3dlut,
+-	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
+ };
+ 
+ void dcn20_hw_sequencer_construct(struct dc *dc)
+ {
+ 	dc->hwss = dcn20_funcs;
++	dc->hwseq->funcs = dcn20_private_funcs;
+ 
+ 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 		dc->hwss.init_hw = dcn20_fpga_init_hw;
+-		dc->hwss.init_pipes = NULL;
++		dc->hwseq->funcs.init_pipes = NULL;
+ 	}
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+index 005894dcabc9..081ad8e43d58 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+@@ -28,6 +28,7 @@
+ #include "core_types.h"
+ #include "resource.h"
+ #include "dce/dce_hwseq.h"
++#include "dcn21_hwseq.h"
+ #include "vmid.h"
+ #include "reg_helper.h"
+ #include "hw/clk_mgr.h"
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
+index 2f7b8a220eb9..182736096123 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
+@@ -26,6 +26,8 @@
+ #ifndef __DC_HWSS_DCN21_H__
+ #define __DC_HWSS_DCN21_H__
+ 
++#include "hw_sequencer_private.h"
++
+ struct dc;
+ 
+ int dcn21_init_sys_ctx(struct dce_hwseq *hws,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+index cbd55037a04a..45e79a8b7070 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+@@ -31,19 +31,13 @@
+ static const struct hw_sequencer_funcs dcn21_funcs = {
+ 	.program_gamut_remap = dcn10_program_gamut_remap,
+ 	.init_hw = dcn10_init_hw,
+-	.init_pipes = dcn10_init_pipes,
+ 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+ 	.apply_ctx_for_surface = NULL,
+ 	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+ 	.update_plane_addr = dcn20_update_plane_addr,
+-	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
+ 	.update_dchub = dcn10_update_dchub,
+-	.update_mpcc = dcn20_update_mpcc,
+ 	.update_pending_status = dcn10_update_pending_status,
+-	.set_input_transfer_func = dcn20_set_input_transfer_func,
+-	.set_output_transfer_func = dcn20_set_output_transfer_func,
+ 	.program_output_csc = dcn20_program_output_csc,
+-	.power_down = dce110_power_down,
+ 	.enable_accelerated_mode = dce110_enable_accelerated_mode,
+ 	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
+ 	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
+@@ -55,16 +49,12 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
+ 	.blank_stream = dce110_blank_stream,
+ 	.enable_audio_stream = dce110_enable_audio_stream,
+ 	.disable_audio_stream = dce110_disable_audio_stream,
+-	.enable_display_power_gating = dcn10_dummy_display_power_gating,
+ 	.disable_plane = dcn20_disable_plane,
+-	.blank_pixel_data = dcn20_blank_pixel_data,
+ 	.pipe_control_lock = dcn20_pipe_control_lock,
+ 	.pipe_control_lock_global = dcn20_pipe_control_lock_global,
+ 	.prepare_bandwidth = dcn20_prepare_bandwidth,
+ 	.optimize_bandwidth = dcn20_optimize_bandwidth,
+ 	.update_bandwidth = dcn20_update_bandwidth,
+-	.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
+-	.enable_stream_timing = dcn20_enable_stream_timing,
+ 	.set_drr = dcn10_set_drr,
+ 	.get_position = dcn10_get_position,
+ 	.set_static_screen_control = dcn10_set_static_screen_control,
+@@ -74,18 +64,49 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
+ 	.get_hw_state = dcn10_get_hw_state,
+ 	.clear_status_bits = dcn10_clear_status_bits,
+ 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+-	.edp_backlight_control = dce110_edp_backlight_control,
+ 	.edp_power_control = dce110_edp_power_control,
+ 	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+ 	.set_cursor_position = dcn10_set_cursor_position,
+ 	.set_cursor_attribute = dcn10_set_cursor_attribute,
+ 	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
+-	.disable_stream_gating = dcn20_disable_stream_gating,
+-	.enable_stream_gating = dcn20_enable_stream_gating,
+ 	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
+-	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
+ 	.set_clock = dcn10_set_clock,
+ 	.get_clock = dcn10_get_clock,
++	.program_triplebuffer = dcn20_program_triple_buffer,
++	.enable_writeback = dcn20_enable_writeback,
++	.disable_writeback = dcn20_disable_writeback,
++	.dmdata_status_done = dcn20_dmdata_status_done,
++	.program_dmdata_engine = dcn20_program_dmdata_engine,
++	.set_dmdata_attributes = dcn20_set_dmdata_attributes,
++	.init_sys_ctx = dcn21_init_sys_ctx,
++	.init_vm_ctx = dcn20_init_vm_ctx,
++	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
++	.optimize_pwr_state = dcn21_optimize_pwr_state,
++	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
++	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
++	.set_cursor_position = dcn10_set_cursor_position,
++	.set_cursor_attribute = dcn10_set_cursor_attribute,
++	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
++	.optimize_pwr_state = dcn21_optimize_pwr_state,
++	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
++};
++
++static const struct hwseq_private_funcs dcn21_private_funcs = {
++	.init_pipes = dcn10_init_pipes,
++	.update_plane_addr = dcn20_update_plane_addr,
++	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
++	.update_mpcc = dcn20_update_mpcc,
++	.set_input_transfer_func = dcn20_set_input_transfer_func,
++	.set_output_transfer_func = dcn20_set_output_transfer_func,
++	.power_down = dce110_power_down,
++	.enable_display_power_gating = dcn10_dummy_display_power_gating,
++	.blank_pixel_data = dcn20_blank_pixel_data,
++	.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
++	.enable_stream_timing = dcn20_enable_stream_timing,
++	.edp_backlight_control = dce110_edp_backlight_control,
++	.disable_stream_gating = dcn20_disable_stream_gating,
++	.enable_stream_gating = dcn20_enable_stream_gating,
++	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
+ 	.did_underflow_occur = dcn10_did_underflow_occur,
+ 	.init_blank = dcn20_init_blank,
+ 	.disable_vga = dcn20_disable_vga,
+@@ -96,15 +117,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
+ 	.dpp_pg_control = dcn20_dpp_pg_control,
+ 	.hubp_pg_control = dcn20_hubp_pg_control,
+ 	.dsc_pg_control = NULL,
+-	.program_triplebuffer = dcn20_program_triple_buffer,
+-	.enable_writeback = dcn20_enable_writeback,
+-	.disable_writeback = dcn20_disable_writeback,
+ 	.update_odm = dcn20_update_odm,
+-	.dmdata_status_done = dcn20_dmdata_status_done,
+-	.program_dmdata_engine = dcn20_program_dmdata_engine,
+-	.init_sys_ctx = dcn21_init_sys_ctx,
+-	.init_vm_ctx = dcn20_init_vm_ctx,
+-	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
+ #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ 	.dsc_pg_control = dcn20_dsc_pg_control,
+ #else
+@@ -115,21 +128,19 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
+ 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
+ 	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
+ 	.s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa,
+-	.optimize_pwr_state = dcn21_optimize_pwr_state,
+-	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
+ 	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
+ 	.dccg_init = dcn20_dccg_init,
+ 	.set_blend_lut = dcn20_set_blend_lut,
+ 	.set_shaper_3dlut = dcn20_set_shaper_3dlut,
+-	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
+ };
+ 
+ void dcn21_hw_sequencer_construct(struct dc *dc)
+ {
+ 	dc->hwss = dcn21_funcs;
++	dc->hwseq->funcs = dcn21_private_funcs;
+ 
+ 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ 		dc->hwss.init_hw = dcn20_fpga_init_hw;
+-		dc->hwss.init_pipes = NULL;
++		dc->hwseq->funcs.init_pipes = NULL;
+ 	}
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+index 937a02d02f18..54b3e88bf0d3 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+@@ -32,294 +32,137 @@
+ #include "inc/hw/link_encoder.h"
+ #include "core_status.h"
+ 
+-enum pipe_gating_control {
+-	PIPE_GATING_CONTROL_DISABLE = 0,
+-	PIPE_GATING_CONTROL_ENABLE,
+-	PIPE_GATING_CONTROL_INIT
+-};
+-
+ enum vline_select {
+ 	VLINE0,
+ 	VLINE1
+ };
+ 
+-struct dce_hwseq_wa {
+-	bool blnd_crtc_trigger;
+-	bool DEGVIDCN10_253;
+-	bool false_optc_underflow;
+-	bool DEGVIDCN10_254;
+-	bool DEGVIDCN21;
+-};
+-
+-struct hwseq_wa_state {
+-	bool DEGVIDCN10_253_applied;
+-};
+-
+-struct dce_hwseq {
+-	struct dc_context *ctx;
+-	const struct dce_hwseq_registers *regs;
+-	const struct dce_hwseq_shift *shifts;
+-	const struct dce_hwseq_mask *masks;
+-	struct dce_hwseq_wa wa;
+-	struct hwseq_wa_state wa_state;
+-};
+-
+ struct pipe_ctx;
+ struct dc_state;
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dc_stream_status;
+ struct dc_writeback_info;
++#endif
+ struct dchub_init_data;
+ struct dc_static_screen_events;
+ struct resource_pool;
+-struct resource_context;
+-struct stream_resource;
++#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ struct dc_phy_addr_space_config;
+ struct dc_virtual_addr_space_config;
+-struct hubp;
++#endif
+ struct dpp;
++struct dce_hwseq;
+ 
+ struct hw_sequencer_funcs {
++	/* Embedded Display Related */
++	void (*edp_power_control)(struct dc_link *link, bool enable);
++	void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
+ 
+-	void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+-
+-	void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+-
++	/* Pipe Programming Related */
+ 	void (*init_hw)(struct dc *dc);
+-
+-	void (*init_pipes)(struct dc *dc, struct dc_state *context);
+-
+-	enum dc_status (*apply_ctx_to_hw)(
+-			struct dc *dc, struct dc_state *context);
+-
+-	void (*reset_hw_ctx_wrap)(
+-			struct dc *dc, struct dc_state *context);
+-
+-	void (*apply_ctx_for_surface)(
+-			struct dc *dc,
++	void (*enable_accelerated_mode)(struct dc *dc,
++			struct dc_state *context);
++	enum dc_status (*apply_ctx_to_hw)(struct dc *dc,
++			struct dc_state *context);
++	void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
++	void (*apply_ctx_for_surface)(struct dc *dc,
+ 			const struct dc_stream_state *stream,
+-			int num_planes,
++			int num_planes, struct dc_state *context);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++	void (*program_front_end_for_ctx)(struct dc *dc,
+ 			struct dc_state *context);
+-
+-	void (*program_gamut_remap)(
++#endif
++	void (*update_plane_addr)(const struct dc *dc,
+ 			struct pipe_ctx *pipe_ctx);
+-
+-	void (*program_output_csc)(struct dc *dc,
+-			struct pipe_ctx *pipe_ctx,
+-			enum dc_color_space colorspace,
+-			uint16_t *matrix,
+-			int opp_id);
+-
+-	void (*program_front_end_for_ctx)(
+-			struct dc *dc,
+-			struct dc_state *context);
+-	void (*program_triplebuffer)(
+-		const struct dc *dc,
+-		struct pipe_ctx *pipe_ctx,
+-		bool enableTripleBuffer);
+-	void (*set_flip_control_gsl)(
+-		struct pipe_ctx *pipe_ctx,
+-		bool flip_immediate);
+-
+-	void (*update_plane_addr)(
+-		const struct dc *dc,
+-		struct pipe_ctx *pipe_ctx);
+-
+-	void (*plane_atomic_disconnect)(
+-		struct dc *dc,
+-		struct pipe_ctx *pipe_ctx);
+-
+-	void (*update_dchub)(
+-		struct dce_hwseq *hws,
+-		struct dchub_init_data *dh_data);
+-
+-	int (*init_sys_ctx)(
+-			struct dce_hwseq *hws,
+-			struct dc *dc,
+-			struct dc_phy_addr_space_config *pa_config);
+-	void (*init_vm_ctx)(
+-			struct dce_hwseq *hws,
+-			struct dc *dc,
+-			struct dc_virtual_addr_space_config *va_config,
+-			int vmid);
+-	void (*update_mpcc)(
+-		struct dc *dc,
+-		struct pipe_ctx *pipe_ctx);
+-
+-	void (*update_pending_status)(
++	void (*update_dchub)(struct dce_hwseq *hws,
++			struct dchub_init_data *dh_data);
++	void (*wait_for_mpcc_disconnect)(struct dc *dc,
++			struct resource_pool *res_pool,
+ 			struct pipe_ctx *pipe_ctx);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++	void (*program_triplebuffer)(const struct dc *dc,
++		struct pipe_ctx *pipe_ctx, bool enableTripleBuffer);
++#endif
++	void (*update_pending_status)(struct pipe_ctx *pipe_ctx);
++
++	/* Pipe Lock Related */
++	void (*pipe_control_lock_global)(struct dc *dc,
++			struct pipe_ctx *pipe, bool lock);
++	void (*pipe_control_lock)(struct dc *dc,
++			struct pipe_ctx *pipe, bool lock);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++	void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx,
++			bool flip_immediate);
++#endif
+ 
+-	bool (*set_input_transfer_func)(struct dc *dc,
+-				struct pipe_ctx *pipe_ctx,
+-				const struct dc_plane_state *plane_state);
+-
+-	bool (*set_output_transfer_func)(struct dc *dc,
+-				struct pipe_ctx *pipe_ctx,
+-				const struct dc_stream_state *stream);
+-
+-	void (*power_down)(struct dc *dc);
+-
+-	void (*enable_accelerated_mode)(struct dc *dc, struct dc_state *context);
+-
+-	void (*enable_timing_synchronization)(
+-			struct dc *dc,
+-			int group_index,
+-			int group_size,
+-			struct pipe_ctx *grouped_pipes[]);
+-
+-	void (*enable_per_frame_crtc_position_reset)(
+-			struct dc *dc,
+-			int group_size,
++	/* Timing Related */
++	void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
++			struct crtc_position *position);
++	int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx);
++	void (*enable_per_frame_crtc_position_reset)(struct dc *dc,
++			int group_size, struct pipe_ctx *grouped_pipes[]);
++	void (*enable_timing_synchronization)(struct dc *dc,
++			int group_index, int group_size,
+ 			struct pipe_ctx *grouped_pipes[]);
++	void (*setup_periodic_interrupt)(struct dc *dc,
++			struct pipe_ctx *pipe_ctx,
++			enum vline_select vline);
++	void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
++			unsigned int vmin, unsigned int vmax,
++			unsigned int vmid, unsigned int vmid_frame_number);
++	void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
++			int num_pipes,
++			const struct dc_static_screen_events *events);
+ 
+-	void (*enable_display_pipe_clock_gating)(
+-					struct dc_context *ctx,
+-					bool clock_gating);
+-
+-	bool (*enable_display_power_gating)(
+-					struct dc *dc,
+-					uint8_t controller_id,
+-					struct dc_bios *dcb,
+-					enum pipe_gating_control power_gating);
+-
+-	void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+-
+-	void (*update_info_frame)(struct pipe_ctx *pipe_ctx);
+-
+-	void (*send_immediate_sdp_message)(
+-				struct pipe_ctx *pipe_ctx,
+-				const uint8_t *custom_sdp_message,
+-				unsigned int sdp_message_size);
+-
++	/* Stream Related */
+ 	void (*enable_stream)(struct pipe_ctx *pipe_ctx);
+-
+ 	void (*disable_stream)(struct pipe_ctx *pipe_ctx);
+-
++	void (*blank_stream)(struct pipe_ctx *pipe_ctx);
+ 	void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
+ 			struct dc_link_settings *link_settings);
+ 
+-	void (*blank_stream)(struct pipe_ctx *pipe_ctx);
+-
+-	void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx);
+-
+-	void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx);
+-
+-	void (*pipe_control_lock)(
+-				struct dc *dc,
+-				struct pipe_ctx *pipe,
+-				bool lock);
++	/* Bandwidth Related */
++	void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++	bool (*update_bandwidth)(struct dc *dc, struct dc_state *context);
++#endif
++	void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context);
+ 
+-	void (*pipe_control_lock_global)(
+-				struct dc *dc,
+-				struct pipe_ctx *pipe,
+-				bool lock);
+-	void (*blank_pixel_data)(
+-			struct dc *dc,
++	/* Infopacket Related */
++	void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);
++	void (*send_immediate_sdp_message)(
+ 			struct pipe_ctx *pipe_ctx,
+-			bool blank);
+-
+-	void (*prepare_bandwidth)(
+-			struct dc *dc,
+-			struct dc_state *context);
+-	void (*optimize_bandwidth)(
+-			struct dc *dc,
+-			struct dc_state *context);
+-
+-	void (*exit_optimized_pwr_state)(
+-			const struct dc *dc,
+-			struct dc_state *context);
+-	void (*optimize_pwr_state)(
+-			const struct dc *dc,
+-			struct dc_state *context);
+-
+-	bool (*update_bandwidth)(
+-			struct dc *dc,
+-			struct dc_state *context);
++			const uint8_t *custom_sdp_message,
++			unsigned int sdp_message_size);
++	void (*update_info_frame)(struct pipe_ctx *pipe_ctx);
++	void (*set_dmdata_attributes)(struct pipe_ctx *pipe);
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx);
+ 	bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx);
++#endif
+ 
+-	void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
+-			unsigned int vmin, unsigned int vmax,
+-			unsigned int vmid, unsigned int vmid_frame_number);
+-
+-	void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
+-			struct crtc_position *position);
+-
+-	void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
+-			int num_pipes, const struct dc_static_screen_events *events);
+-
+-	enum dc_status (*enable_stream_timing)(
+-			struct pipe_ctx *pipe_ctx,
+-			struct dc_state *context,
+-			struct dc *dc);
+-
+-	void (*setup_stereo)(
+-			struct pipe_ctx *pipe_ctx,
+-			struct dc *dc);
+-
+-	void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);
+-
+-	void (*log_hw_state)(struct dc *dc,
+-		struct dc_log_buffer_ctx *log_ctx);
+-	void (*get_hw_state)(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask);
+-	void (*clear_status_bits)(struct dc *dc, unsigned int mask);
+-
+-	void (*wait_for_mpcc_disconnect)(struct dc *dc,
+-			struct resource_pool *res_pool,
+-			struct pipe_ctx *pipe_ctx);
+-
+-	void (*edp_power_control)(
+-			struct dc_link *link,
+-			bool enable);
+-	void (*edp_backlight_control)(
+-			struct dc_link *link,
+-			bool enable);
+-	void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
+-
++	/* Cursor Related */
+ 	void (*set_cursor_position)(struct pipe_ctx *pipe);
+ 	void (*set_cursor_attribute)(struct pipe_ctx *pipe);
+ 	void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);
+ 
+-	void (*setup_periodic_interrupt)(struct dc *dc,
+-			struct pipe_ctx *pipe_ctx,
+-			enum vline_select vline);
+-	void (*setup_vupdate_interrupt)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+-	bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
+-
+-	void (*init_blank)(struct dc *dc, struct timing_generator *tg);
+-	void (*disable_vga)(struct dce_hwseq *hws);
+-	void (*bios_golden_init)(struct dc *dc);
+-	void (*plane_atomic_power_down)(struct dc *dc,
+-			struct dpp *dpp,
+-			struct hubp *hubp);
+-
+-	void (*plane_atomic_disable)(
+-			struct dc *dc, struct pipe_ctx *pipe_ctx);
+-
+-	void (*enable_power_gating_plane)(
+-		struct dce_hwseq *hws,
+-		bool enable);
+-
+-	void (*dpp_pg_control)(
+-			struct dce_hwseq *hws,
+-			unsigned int dpp_inst,
+-			bool power_on);
+-
+-	void (*hubp_pg_control)(
+-			struct dce_hwseq *hws,
+-			unsigned int hubp_inst,
+-			bool power_on);
+-
+-	void (*dsc_pg_control)(
+-			struct dce_hwseq *hws,
+-			unsigned int dsc_inst,
+-			bool power_on);
+-
++	/* Colour Related */
++	void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx);
++	void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx,
++			enum dc_color_space colorspace,
++			uint16_t *matrix, int opp_id);
+ 
+-	void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
+-	void (*program_all_writeback_pipes_in_tree)(
++#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
++	/* VM Related */
++	int (*init_sys_ctx)(struct dce_hwseq *hws,
+ 			struct dc *dc,
+-			const struct dc_stream_state *stream,
+-			struct dc_state *context);
++			struct dc_phy_addr_space_config *pa_config);
++	void (*init_vm_ctx)(struct dce_hwseq *hws,
++			struct dc *dc,
++			struct dc_virtual_addr_space_config *va_config,
++			int vmid);
++
++	/* Writeback Related */
+ 	void (*update_writeback)(struct dc *dc,
+ 			const struct dc_stream_status *stream_status,
+ 			struct dc_writeback_info *wb_info,
+@@ -330,48 +173,34 @@ struct hw_sequencer_funcs {
+ 			struct dc_state *context);
+ 	void (*disable_writeback)(struct dc *dc,
+ 			unsigned int dwb_pipe_inst);
+-	enum dc_status (*set_clock)(struct dc *dc,
+-			enum dc_clock_type clock_type,
+-			uint32_t clk_khz,
+-			uint32_t stepping);
++#endif
+ 
+-	void (*get_clock)(struct dc *dc,
++	/* Clock Related */
++	enum dc_status (*set_clock)(struct dc *dc,
+ 			enum dc_clock_type clock_type,
++			uint32_t clk_khz, uint32_t stepping);
++	void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type,
+ 			struct dc_clock_config *clock_cfg);
+ 
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+-	bool (*s0i3_golden_init_wa)(struct dc *dc);
+-#endif
+-
+-	void (*get_surface_visual_confirm_color)(
+-			const struct pipe_ctx *pipe_ctx,
+-			struct tg_color *color);
+-
+-	void (*get_hdr_visual_confirm_color)(
+-			struct pipe_ctx *pipe_ctx,
+-			struct tg_color *color);
+-
+-	void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);
+-
+-	void (*verify_allow_pstate_change_high)(struct dc *dc);
+-
+-	void (*program_pipe)(
+-			struct dc *dc,
+-			struct pipe_ctx *pipe_ctx,
++	void (*optimize_pwr_state)(const struct dc *dc,
++			struct dc_state *context);
++	void (*exit_optimized_pwr_state)(const struct dc *dc,
+ 			struct dc_state *context);
+ 
+-	bool (*wait_for_blank_complete)(
+-			struct output_pixel_processor *opp);
++	/* Audio Related */
++	void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx);
++	void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx);
+ 
+-	void (*dccg_init)(struct dce_hwseq *hws);
++	/* Stereo 3D Related */
++	void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc);
+ 
+-	bool (*set_blend_lut)(
+-		struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
++	/* HW State Logging Related */
++	void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx);
++	void (*get_hw_state)(struct dc *dc, char *pBuf,
++			unsigned int bufSize, unsigned int mask);
++	void (*clear_status_bits)(struct dc *dc, unsigned int mask);
+ 
+-	bool (*set_shaper_3dlut)(
+-		struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
+ 
+-	int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx);
+ };
+ 
+ void color_space_to_black_color(
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
+new file mode 100644
+index 000000000000..8ba06f015975
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
+@@ -0,0 +1,156 @@
++/*
++ * Copyright 2015 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef __DC_HW_SEQUENCER_PRIVATE_H__
++#define __DC_HW_SEQUENCER_PRIVATE_H__
++
++#include "dc_types.h"
++
++enum pipe_gating_control {
++	PIPE_GATING_CONTROL_DISABLE = 0,
++	PIPE_GATING_CONTROL_ENABLE,
++	PIPE_GATING_CONTROL_INIT
++};
++
++struct dce_hwseq_wa {
++	bool blnd_crtc_trigger;
++	bool DEGVIDCN10_253;
++	bool false_optc_underflow;
++	bool DEGVIDCN10_254;
++	bool DEGVIDCN21;
++};
++
++struct hwseq_wa_state {
++	bool DEGVIDCN10_253_applied;
++};
++
++struct pipe_ctx;
++struct dc_state;
++struct dc_stream_status;
++struct dc_writeback_info;
++struct dchub_init_data;
++struct dc_static_screen_events;
++struct resource_pool;
++struct resource_context;
++struct stream_resource;
++struct dc_phy_addr_space_config;
++struct dc_virtual_addr_space_config;
++struct hubp;
++struct dpp;
++struct dce_hwseq;
++struct timing_generator;
++struct tg_color;
++struct output_pixel_processor;
++
++struct hwseq_private_funcs {
++
++	void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
++	void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
++	void (*init_pipes)(struct dc *dc, struct dc_state *context);
++	void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
++	void (*update_plane_addr)(const struct dc *dc,
++			struct pipe_ctx *pipe_ctx);
++	void (*plane_atomic_disconnect)(struct dc *dc,
++			struct pipe_ctx *pipe_ctx);
++	void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
++	bool (*set_input_transfer_func)(struct dc *dc,
++				struct pipe_ctx *pipe_ctx,
++				const struct dc_plane_state *plane_state);
++	bool (*set_output_transfer_func)(struct dc *dc,
++				struct pipe_ctx *pipe_ctx,
++				const struct dc_stream_state *stream);
++	void (*power_down)(struct dc *dc);
++	void (*enable_display_pipe_clock_gating)(struct dc_context *ctx,
++					bool clock_gating);
++	bool (*enable_display_power_gating)(struct dc *dc,
++					uint8_t controller_id,
++					struct dc_bios *dcb,
++					enum pipe_gating_control power_gating);
++	void (*blank_pixel_data)(struct dc *dc,
++			struct pipe_ctx *pipe_ctx,
++			bool blank);
++	enum dc_status (*enable_stream_timing)(
++			struct pipe_ctx *pipe_ctx,
++			struct dc_state *context,
++			struct dc *dc);
++	void (*edp_backlight_control)(struct dc_link *link,
++			bool enable);
++	void (*setup_vupdate_interrupt)(struct dc *dc,
++			struct pipe_ctx *pipe_ctx);
++	bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
++	void (*init_blank)(struct dc *dc, struct timing_generator *tg);
++	void (*disable_vga)(struct dce_hwseq *hws);
++	void (*bios_golden_init)(struct dc *dc);
++	void (*plane_atomic_power_down)(struct dc *dc,
++			struct dpp *dpp,
++			struct hubp *hubp);
++	void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx);
++	void (*enable_power_gating_plane)(struct dce_hwseq *hws,
++		bool enable);
++	void (*dpp_pg_control)(struct dce_hwseq *hws,
++			unsigned int dpp_inst,
++			bool power_on);
++	void (*hubp_pg_control)(struct dce_hwseq *hws,
++			unsigned int hubp_inst,
++			bool power_on);
++	void (*dsc_pg_control)(struct dce_hwseq *hws,
++			unsigned int dsc_inst,
++			bool power_on);
++	void (*update_odm)(struct dc *dc, struct dc_state *context,
++			struct pipe_ctx *pipe_ctx);
++	void (*program_all_writeback_pipes_in_tree)(struct dc *dc,
++			const struct dc_stream_state *stream,
++			struct dc_state *context);
++	bool (*s0i3_golden_init_wa)(struct dc *dc);
++	void (*get_surface_visual_confirm_color)(
++			const struct pipe_ctx *pipe_ctx,
++			struct tg_color *color);
++	void (*get_hdr_visual_confirm_color)(struct pipe_ctx *pipe_ctx,
++			struct tg_color *color);
++	void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);
++	void (*verify_allow_pstate_change_high)(struct dc *dc);
++	void (*program_pipe)(struct dc *dc,
++			struct pipe_ctx *pipe_ctx,
++			struct dc_state *context);
++	bool (*wait_for_blank_complete)(struct output_pixel_processor *opp);
++	void (*dccg_init)(struct dce_hwseq *hws);
++	bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx,
++			const struct dc_plane_state *plane_state);
++	bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx,
++			const struct dc_plane_state *plane_state);
++};
++
++struct dce_hwseq {
++	struct dc_context *ctx;
++	const struct dce_hwseq_registers *regs;
++	const struct dce_hwseq_shift *shifts;
++	const struct dce_hwseq_mask *masks;
++	struct dce_hwseq_wa wa;
++	struct hwseq_wa_state wa_state;
++	struct hwseq_private_funcs funcs;
++
++};
++
++#endif /* __DC_HW_SEQUENCER_PRIVATE_H__ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4669-drm-amd-display-Fix-Dali-clk-mgr-construct.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4669-drm-amd-display-Fix-Dali-clk-mgr-construct.patch
new file mode 100644
index 00000000..d7efc9d9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4669-drm-amd-display-Fix-Dali-clk-mgr-construct.patch
@@ -0,0 +1,72 @@
+From 74ad82d1beb22c28091571a377d8f5709655591b Mon Sep 17 00:00:00 2001
+From: Michael Strauss <michael.strauss@amd.com>
+Date: Mon, 4 Nov 2019 13:39:20 -0500
+Subject: [PATCH 4669/4736] drm/amd/display: Fix Dali clk mgr construct
+
+[WHY]
+Dali is currently being misinterpreted as Renoir,
+as a result uses wrong clk mgr constructor
+
+[HOW]
+Add check to init Dali as Raven2 before it can be misidentified
+Clean up & fix Raven2 & Dali ASIC checks
+
+Change-Id: I56de017317487ab06085f56ca590680eb7a01be1
+Signed-off-by: Michael Strauss <michael.strauss@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  |  7 +++++++
+ drivers/gpu/drm/amd/display/include/dal_asic_id.h | 11 +++++------
+ 2 files changed, 12 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+index 3d42bb4355f8..5f64036982fc 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+@@ -134,6 +134,13 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
+ 
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ 	case FAMILY_RV:
++		if (ASICREV_IS_DALI(asic_id.hw_internal_rev)) {
++			/* TEMP: this check has to come before ASICREV_IS_RENOIR */
++			/* which also incorrectly returns true for Dali */
++			rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
++			break;
++		}
++
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ 		if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) {
+ 			rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+index d51fe99349ed..0b4f5fde387b 100644
+--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
++++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+@@ -134,18 +134,17 @@
+ /* DCN1_01 */
+ #define PICASSO_A0 0x41
+ #define RAVEN2_A0 0x81
++#define RAVEN2_15D8_REV_E3 0xE3
++#define RAVEN2_15D8_REV_E4 0xE4
+ #define RAVEN1_F0 0xF0
+ #define RAVEN_UNKNOWN 0xFF
+ 
+-#define PICASSO_15D8_REV_E3 0xE3
+-#define PICASSO_15D8_REV_E4 0xE4
+-
+ #define ASICREV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
+ #define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0))
+-#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < PICASSO_15D8_REV_E3))
+-#define ASICREV_IS_DALI(eChipRev) ((eChipRev >= PICASSO_15D8_REV_E3) && (eChipRev < RAVEN1_F0))
+-
++#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < RAVEN1_F0))
+ #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
++#define ASICREV_IS_DALI(eChipRev) ((eChipRev == RAVEN2_15D8_REV_E3) \
++		|| (eChipRev == RAVEN2_15D8_REV_E4))
+ 
+ #define FAMILY_RV 142 /* DCN 1*/
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4670-drm-amd-display-Map-DSC-resources-1-to-1-if-numbers-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4670-drm-amd-display-Map-DSC-resources-1-to-1-if-numbers-.patch
new file mode 100644
index 00000000..3b5227d8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4670-drm-amd-display-Map-DSC-resources-1-to-1-if-numbers-.patch
@@ -0,0 +1,72 @@
+From 9666c46fe746cf775aef8e3a8470ab4e62c15f00 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Thu, 7 Nov 2019 13:06:48 -0500
+Subject: [PATCH 4670/4736] drm/amd/display: Map DSC resources 1-to-1 if
+ numbers of OPPs and DSCs are equal
+
+[why]
+On ASICs where number of DSCs is the same as OPPs there's no need
+for DSC resource management. Mappping 1-to-1 fixes mode-set- or S3-
+-related issues for such platforms.
+
+[how]
+Map DSC resources 1-to-1 to pipes only if number of OPPs is the same
+as number of DSCs. This will still keep other ASICs working.
+A follow-up patch to fix mode-set issues on those ASICs will be
+required if testing shows issues with mode set.
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c   | 13 ++++++++++---
+ 1 file changed, 10 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index b000d5289684..2e03ff357746 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1524,13 +1524,20 @@ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state
+ 
+ static void acquire_dsc(struct resource_context *res_ctx,
+ 			const struct resource_pool *pool,
+-			struct display_stream_compressor **dsc)
++			struct display_stream_compressor **dsc,
++			int pipe_idx)
+ {
+ 	int i;
+ 
+ 	ASSERT(*dsc == NULL);
+ 	*dsc = NULL;
+ 
++	if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
++		*dsc = pool->dscs[pipe_idx];
++		res_ctx->is_dsc_acquired[pipe_idx] = true;
++		return;
++	}
++
+ 	/* Find first free DSC */
+ 	for (i = 0; i < pool->res_cap->num_dsc; i++)
+ 		if (!res_ctx->is_dsc_acquired[i]) {
+@@ -1571,7 +1578,7 @@ static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
+ 		if (pipe_ctx->stream != dc_stream)
+ 			continue;
+ 
+-		acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc);
++		acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc, i);
+ 
+ 		/* The number of DSCs can be less than the number of pipes */
+ 		if (!pipe_ctx->stream_res.dsc) {
+@@ -1763,7 +1770,7 @@ bool dcn20_split_stream_for_odm(
+ 	}
+ 	next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
+ 	if (next_odm_pipe->stream->timing.flags.DSC == 1) {
+-		acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc);
++		acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
+ 		ASSERT(next_odm_pipe->stream_res.dsc);
+ 		if (next_odm_pipe->stream_res.dsc == NULL)
+ 			return false;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4671-drm-amd-display-fix-DalDramClockChangeLatencyNs-over.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4671-drm-amd-display-fix-DalDramClockChangeLatencyNs-over.patch
new file mode 100644
index 00000000..e8896e93
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4671-drm-amd-display-fix-DalDramClockChangeLatencyNs-over.patch
@@ -0,0 +1,41 @@
+From 44cfb929dce3ec82a8c4072e8a49547dc301f2ba Mon Sep 17 00:00:00 2001
+From: Joseph Gravenor <joseph.gravenor@amd.com>
+Date: Mon, 4 Nov 2019 16:39:35 -0500
+Subject: [PATCH 4671/4736] drm/amd/display: fix DalDramClockChangeLatencyNs
+ override
+
+[why]
+pstate_latency_us never gets updated from the hard coded value
+in rn_clk_mgr.c
+
+[how]
+update the wm table's values before we do calculations with them
+
+Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 94a5611972cc..23727c3f2e01 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1013,9 +1013,12 @@ static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
+ 	}
+ 
+ 	if (dc->bb_overrides.dram_clock_change_latency_ns) {
+-		bb->dram_clock_change_latency_us =
++		for (i = 0; i < WM_SET_COUNT; i++) {
++			dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
+ 				dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
++		}
+ 	}
++
+ 	kernel_fpu_end();
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4672-drm-amd-display-Wrong-ifdef-guards-were-used-around-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4672-drm-amd-display-Wrong-ifdef-guards-were-used-around-.patch
new file mode 100644
index 00000000..babf33e1
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4672-drm-amd-display-Wrong-ifdef-guards-were-used-around-.patch
@@ -0,0 +1,62 @@
+From 3a072edc709fb45c1ca84d4a9d73ec153c9d8562 Mon Sep 17 00:00:00 2001
+From: Jaehyun Chung <jaehyun.chung@amd.com>
+Date: Thu, 7 Nov 2019 11:16:49 -0500
+Subject: [PATCH 4672/4736] drm/amd/display: Wrong ifdef guards were used
+ around DML validation
+
+[Why]
+Wrong guards were causing the debug option not to run.
+
+[How]
+Changed the guard to the correct one, matching the rq, ttu, dlg regs struct
+members that need to be guarded. Also log a message when validation starts.
+
+Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
+Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c          | 2 +-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 1 +
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 1 +
+ 3 files changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index e5cbc5bf3290..1e4919687ece 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -2223,7 +2223,7 @@ static void commit_planes_for_stream(struct dc *dc,
+ #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ 	if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
+ 		dc->hwss.program_front_end_for_ctx(dc, context);
+-#ifdef CONFIG_DRM_AMD_DC_DCN1_0
++#ifdef CONFIG_DRM_AMD_DC_DCN
+ 		if (dc->debug.validate_dml_output) {
+ 			for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ 				struct pipe_ctx cur_pipe = context->res_ctx.pipe_ctx[i];
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+index 2823be75b071..84d7ac5dd206 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+@@ -1257,6 +1257,7 @@ void hubp2_validate_dml_output(struct hubp *hubp,
+ 	struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0};
+ 	struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0};
+ 	DC_LOGGER_INIT(ctx->logger);
++	DC_LOG_DEBUG("DML Validation | Running Validation");
+ 
+ 	/* Requestor Regs */
+ 	REG_GET(HUBPRET_CONTROL,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+index 0be1c917b242..4408aed5087b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+@@ -267,6 +267,7 @@ void hubp21_validate_dml_output(struct hubp *hubp,
+ 	struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0};
+ 	struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0};
+ 	DC_LOGGER_INIT(ctx->logger);
++	DC_LOG_DEBUG("DML Validation | Running Validation");
+ 
+ 	/* Requester - Per hubp */
+ 	REG_GET(HUBPRET_CONTROL,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4673-drm-amd-display-Reset-PHY-in-link-re-training.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4673-drm-amd-display-Reset-PHY-in-link-re-training.patch
new file mode 100644
index 00000000..6b893f04
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4673-drm-amd-display-Reset-PHY-in-link-re-training.patch
@@ -0,0 +1,222 @@
+From 82e02f0a49cee28db7f5c7f222e03ab31527e8be Mon Sep 17 00:00:00 2001
+From: Paul Hsieh <paul.hsieh@amd.com>
+Date: Fri, 1 Nov 2019 14:41:37 +0800
+Subject: [PATCH 4673/4736] drm/amd/display: Reset PHY in link re-training
+
+[Why]
+Link training failed randomly when plugging USB-C display in/out.
+
+[How]
+If link training failed, reset PHY in link re-training.
+
+Change-Id: Ic0f8c50e5da346777e96fa73f1137e6c4abef9f2
+Signed-off-by: Paul Hsieh <paul.hsieh@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 31 ++-------
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 68 +++++++++++++++----
+ .../drm/amd/display/dc/core/dc_link_hwss.c    | 14 +---
+ .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |  5 +-
+ 4 files changed, 66 insertions(+), 52 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 9f53cbcc7152..1c056a687161 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -1529,40 +1529,17 @@ static enum dc_status enable_link_dp(
+ 	if (state->clk_mgr && !apply_seamless_boot_optimization)
+ 		state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false);
+ 
+-	dp_enable_link_phy(
+-		link,
+-		pipe_ctx->stream->signal,
+-		pipe_ctx->clock_source->id,
+-		&link_settings);
+-
+-	if (stream->sink_patches.dppowerup_delay > 0) {
+-		int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
+-
+-		msleep(delay_dp_power_up_in_ms);
+-	}
+-
+-	panel_mode = dp_get_panel_mode(link);
+-	dp_set_panel_mode(link, panel_mode);
+-
+-	/* We need to do this before the link training to ensure the idle pattern in SST
+-	 * mode will be sent right after the link training */
+-	link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
+-						    pipe_ctx->stream_res.stream_enc->id, true);
+ 	skip_video_pattern = true;
+ 
+ 	if (link_settings.link_rate == LINK_RATE_LOW)
+ 			skip_video_pattern = false;
+ 
+-	if (link->aux_access_disabled) {
+-		dc_link_dp_perform_link_training_skip_aux(link, &link_settings);
+-
+-		link->cur_link_settings = link_settings;
+-		status = DC_OK;
+-	} else if (perform_link_training_with_retries(
+-			link,
++	if (perform_link_training_with_retries(
+ 			&link_settings,
+ 			skip_video_pattern,
+-			LINK_TRAINING_ATTEMPTS)) {
++			LINK_TRAINING_ATTEMPTS,
++			pipe_ctx,
++			pipe_ctx->stream->signal)) {
+ 		link->cur_link_settings = link_settings;
+ 		status = DC_OK;
+ 	}
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 272261192e82..537b4dee8f22 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -1433,23 +1433,58 @@ enum link_training_result dc_link_dp_perform_link_training(
+ }
+ 
+ bool perform_link_training_with_retries(
+-	struct dc_link *link,
+ 	const struct dc_link_settings *link_setting,
+ 	bool skip_video_pattern,
+-	int attempts)
++	int attempts,
++	struct pipe_ctx *pipe_ctx,
++	enum signal_type signal)
+ {
+ 	uint8_t j;
+ 	uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
++	struct dc_stream_state *stream = pipe_ctx->stream;
++	struct dc_link *link = stream->link;
++	enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
+ 
+ 	for (j = 0; j < attempts; ++j) {
+ 
+-		if (dc_link_dp_perform_link_training(
++		dp_enable_link_phy(
++			link,
++			signal,
++			pipe_ctx->clock_source->id,
++			link_setting);
++
++		if (stream->sink_patches.dppowerup_delay > 0) {
++			int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
++
++			msleep(delay_dp_power_up_in_ms);
++		}
++
++		dp_set_panel_mode(link, panel_mode);
++
++		/* We need to do this before the link training to ensure the idle pattern in SST
++		 * mode will be sent right after the link training
++		 */
++		link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
++								pipe_ctx->stream_res.stream_enc->id, true);
++
++		if (link->aux_access_disabled) {
++			dc_link_dp_perform_link_training_skip_aux(link, link_setting);
++			return true;
++		} else if (dc_link_dp_perform_link_training(
+ 				link,
+ 				link_setting,
+ 				skip_video_pattern) == LINK_TRAINING_SUCCESS)
+ 			return true;
+ 
++		/* latest link training still fail, skip delay and keep PHY on
++		 */
++		if (j == (attempts - 1))
++			break;
++
++		dp_disable_link_phy(link, signal);
++
+ 		msleep(delay_between_attempts);
++
+ 		delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
+ 	}
+ 
+@@ -2770,17 +2805,26 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd
+ 					sizeof(hpd_irq_dpcd_data),
+ 					"Status: ");
+ 
+-		perform_link_training_with_retries(link,
+-			&link->cur_link_settings,
+-			true, LINK_TRAINING_ATTEMPTS);
+-
+ 		for (i = 0; i < MAX_PIPES; i++) {
+ 			pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
+-			if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link &&
+-					pipe_ctx->stream->dpms_off == false &&
+-					pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+-				dc_link_allocate_mst_payload(pipe_ctx);
+-			}
++			if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
++				break;
++		}
++
++		if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
++			return false;
++
++		dp_disable_link_phy(link, pipe_ctx->stream->signal);
++
++		perform_link_training_with_retries(&link->cur_link_settings,
++			true, LINK_TRAINING_ATTEMPTS,
++			pipe_ctx,
++			pipe_ctx->stream->signal);
++
++		if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link &&
++				pipe_ctx->stream->dpms_off == false &&
++				pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
++			dc_link_allocate_mst_payload(pipe_ctx);
+ 		}
+ 
+ 		status = false;
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+index 67ce12df23f1..548aac02ca11 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+@@ -333,20 +333,12 @@ void dp_retrain_link_dp_test(struct dc_link *link,
+ 			memset(&link->cur_link_settings, 0,
+ 				sizeof(link->cur_link_settings));
+ 
+-			link->link_enc->funcs->enable_dp_output(
+-						link->link_enc,
+-						link_setting,
+-						pipes[i].clock_source->id);
+-			link->cur_link_settings = *link_setting;
+-
+-			dp_receiver_power_ctrl(link, true);
+-
+ 			perform_link_training_with_retries(
+-					link,
+ 					link_setting,
+ 					skip_video_pattern,
+-					LINK_TRAINING_ATTEMPTS);
+-
++					LINK_TRAINING_ATTEMPTS,
++					&pipes[i],
++					SIGNAL_TYPE_DISPLAY_PORT);
+ 
+ 			link->dc->hwss.enable_stream(&pipes[i]);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+index 4879cf54d8f1..6198bccd6199 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+@@ -57,10 +57,11 @@ void decide_link_settings(
+ 	struct dc_link_settings *link_setting);
+ 
+ bool perform_link_training_with_retries(
+-	struct dc_link *link,
+ 	const struct dc_link_settings *link_setting,
+ 	bool skip_video_pattern,
+-	int attempts);
++	int attempts,
++	struct pipe_ctx *pipe_ctx,
++	enum signal_type signal);
+ 
+ bool is_mst_supported(struct dc_link *link);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4674-drm-amd-display-Disable-link-before-reenable.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4674-drm-amd-display-Disable-link-before-reenable.patch
new file mode 100644
index 00000000..9353d982
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4674-drm-amd-display-Disable-link-before-reenable.patch
@@ -0,0 +1,160 @@
+From 3c4dd133170621e51501ff2a16471573b918241e Mon Sep 17 00:00:00 2001
+From: Lucy Li <lucy.li@amd.com>
+Date: Fri, 25 Oct 2019 17:59:32 -0400
+Subject: [PATCH 4674/4736] drm/amd/display: Disable link before reenable
+
+[Why]
+Black screen seen after display is disabled then re-enabled.
+Caused by difference in link settings when
+switching between different resolutions.
+
+[How]
+In PnP case, or whenever the display is
+still enabled but the driver is unloaded,
+disable link before re-enabling with new link settings.
+
+Change-Id: I049a0b164daa0a2e3009227f15b4e7f1aa3e8472
+Signed-off-by: Lucy Li <lucy.li@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 101 ++++++++++--------
+ 1 file changed, 54 insertions(+), 47 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 1c056a687161..2accc35996cd 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -1510,15 +1510,6 @@ static enum dc_status enable_link_dp(
+ 	decide_link_settings(stream, &link_settings);
+ 
+ 	if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
+-		/* If link settings are different than current and link already enabled
+-		 * then need to disable before programming to new rate.
+-		 */
+-		if (link->link_status.link_active &&
+-			(link->cur_link_settings.lane_count != link_settings.lane_count ||
+-			 link->cur_link_settings.link_rate != link_settings.link_rate)) {
+-			dp_disable_link_phy(link, pipe_ctx->stream->signal);
+-		}
+-
+ 		/*in case it is not on*/
+ 		link->dc->hwss.edp_power_control(link, true);
+ 		link->dc->hwss.edp_wait_for_hpd_ready(link, true);
+@@ -2038,6 +2029,47 @@ static void write_i2c_redriver_setting(
+ 		ASSERT(i2c_success);
+ }
+ 
++static void disable_link(struct dc_link *link, enum signal_type signal)
++{
++	/*
++	 * TODO: implement call for dp_set_hw_test_pattern
++	 * it is needed for compliance testing
++	 */
++
++	/* Here we need to specify that encoder output settings
++	 * need to be calculated as for the set mode,
++	 * it will lead to querying dynamic link capabilities
++	 * which should be done before enable output
++	 */
++
++	if (dc_is_dp_signal(signal)) {
++		/* SST DP, eDP */
++		if (dc_is_dp_sst_signal(signal))
++			dp_disable_link_phy(link, signal);
++		else
++			dp_disable_link_phy_mst(link, signal);
++#if CONFIG_DRM_AMD_DC_DSC_SUPPORT
++
++		if (dc_is_dp_sst_signal(signal) ||
++				link->mst_stream_alloc_table.stream_count == 0) {
++			dp_set_fec_enable(link, false);
++			dp_set_fec_ready(link, false);
++		}
++#endif
++	} else {
++		if (signal != SIGNAL_TYPE_VIRTUAL)
++			link->link_enc->funcs->disable_output(link->link_enc, signal);
++	}
++
++	if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
++		/* MST disable link only when no stream use the link */
++		if (link->mst_stream_alloc_table.stream_count <= 0)
++			link->link_status.link_active = false;
++	} else {
++		link->link_status.link_active = false;
++	}
++}
++
+ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
+ {
+ 	struct dc_stream_state *stream = pipe_ctx->stream;
+@@ -2122,6 +2154,19 @@ static enum dc_status enable_link(
+ 		struct pipe_ctx *pipe_ctx)
+ {
+ 	enum dc_status status = DC_ERROR_UNEXPECTED;
++	struct dc_stream_state *stream = pipe_ctx->stream;
++	struct dc_link *link = stream->link;
++
++	/* There's some scenarios where driver is unloaded with display
++	 * still enabled. When driver is reloaded, it may cause a display
++	 * to not light up if there is a mismatch between old and new
++	 * link settings. Need to call disable first before enabling at
++	 * new link settings.
++	 */
++	if (link->link_status.link_active) {
++		disable_link(link, pipe_ctx->stream->signal);
++	}
++
+ 	switch (pipe_ctx->stream->signal) {
+ 	case SIGNAL_TYPE_DISPLAY_PORT:
+ 		status = enable_link_dp(state, pipe_ctx);
+@@ -2156,44 +2201,6 @@ static enum dc_status enable_link(
+ 	return status;
+ }
+ 
+-static void disable_link(struct dc_link *link, enum signal_type signal)
+-{
+-	/*
+-	 * TODO: implement call for dp_set_hw_test_pattern
+-	 * it is needed for compliance testing
+-	 */
+-
+-	/* here we need to specify that encoder output settings
+-	 * need to be calculated as for the set mode,
+-	 * it will lead to querying dynamic link capabilities
+-	 * which should be done before enable output */
+-
+-	if (dc_is_dp_signal(signal)) {
+-		/* SST DP, eDP */
+-		if (dc_is_dp_sst_signal(signal))
+-			dp_disable_link_phy(link, signal);
+-		else
+-			dp_disable_link_phy_mst(link, signal);
+-
+-		if (dc_is_dp_sst_signal(signal) ||
+-				link->mst_stream_alloc_table.stream_count == 0) {
+-			dp_set_fec_enable(link, false);
+-			dp_set_fec_ready(link, false);
+-		}
+-	} else {
+-		if (signal != SIGNAL_TYPE_VIRTUAL)
+-			link->link_enc->funcs->disable_output(link->link_enc, signal);
+-	}
+-
+-	if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+-		/* MST disable link only when no stream use the link */
+-		if (link->mst_stream_alloc_table.stream_count <= 0)
+-			link->link_status.link_active = false;
+-	} else {
+-		link->link_status.link_active = false;
+-	}
+-}
+-
+ static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
+ {
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4675-drm-amd-display-Add-DMCUB__PG_DONE-trace-code-enum.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4675-drm-amd-display-Add-DMCUB__PG_DONE-trace-code-enum.patch
new file mode 100644
index 00000000..d6e6f8cb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4675-drm-amd-display-Add-DMCUB__PG_DONE-trace-code-enum.patch
@@ -0,0 +1,27 @@
+From c19ec949b364f286216abec57bf877a785b8684d Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Thu, 7 Nov 2019 14:41:06 -0500
+Subject: [PATCH 4675/4736] drm/amd/display: Add DMCUB__PG_DONE trace code enum
+
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
+index b0ee099d8a6e..6b3ee42db350 100644
+--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_trace_buffer.h
+@@ -45,6 +45,7 @@ enum dmucb_trace_code {
+ 	DMCUB__DMCU_ISR_LOAD_END,
+ 	DMCUB__MAIN_IDLE,
+ 	DMCUB__PERF_TRACE,
++	DMCUB__PG_DONE,
+ };
+ 
+ struct dmcub_trace_buf_entry {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4676-drm-amd-display-Only-wait-for-DMUB-phy-init-on-dcn21.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4676-drm-amd-display-Only-wait-for-DMUB-phy-init-on-dcn21.patch
new file mode 100644
index 00000000..e3c108ef
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4676-drm-amd-display-Only-wait-for-DMUB-phy-init-on-dcn21.patch
@@ -0,0 +1,96 @@
+From 782580b82c79ff0c4f03499165587f81f9166545 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Thu, 7 Nov 2019 15:26:14 -0500
+Subject: [PATCH 4676/4736] drm/amd/display: Only wait for DMUB phy init on
+ dcn21
+
+[Why]
+The wait for PHY init won't finish if the firmware doesn't support it.
+
+[How]
+Only hook this functionality up on DCN21 and move it out of DCN20.
+
+For ASIC without support then this should return OK so we don't hang
+while waiting in DC.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 5 -----
+ drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 2 --
+ drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c | 5 +++++
+ drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h | 2 ++
+ drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c   | 2 +-
+ 5 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+index e2b2cf2e01fd..6b7d54572aa3 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+@@ -135,8 +135,3 @@ bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
+ 
+ 	return supported;
+ }
+-
+-bool dmub_dcn20_is_phy_init(struct dmub_srv *dmub)
+-{
+-	return REG_READ(DMCUB_SCRATCH10) == 0;
+-}
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+index e1ba748ca594..ca7db03b94f7 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+@@ -59,6 +59,4 @@ bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub);
+ 
+ bool dmub_dcn20_is_supported(struct dmub_srv *dmub);
+ 
+-bool dmub_dcn20_is_phy_init(struct dmub_srv *dmub);
+-
+ #endif /* _DMUB_DCN20_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
+index d40a808112e7..b9dc2dd645eb 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
+@@ -124,3 +124,8 @@ bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub)
+ {
+ 	return (REG_READ(DMCUB_SCRATCH0) == 3);
+ }
++
++bool dmub_dcn21_is_phy_init(struct dmub_srv *dmub)
++{
++	return REG_READ(DMCUB_SCRATCH10) == 0;
++}
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
+index f57969d8d56f..9e5f195e288f 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
+@@ -42,4 +42,6 @@ void dmub_dcn21_setup_windows(struct dmub_srv *dmub,
+ 
+ bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub);
+ 
++bool dmub_dcn21_is_phy_init(struct dmub_srv *dmub);
++
+ #endif /* _DMUB_DCN21_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+index 60c574a39c6a..3ec26f6af2e1 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+@@ -76,13 +76,13 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
+ 		funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr;
+ 		funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr;
+ 		funcs->is_supported = dmub_dcn20_is_supported;
+-		funcs->is_phy_init = dmub_dcn20_is_phy_init;
+ 		funcs->is_hw_init = dmub_dcn20_is_hw_init;
+ 
+ 		if (asic == DMUB_ASIC_DCN21) {
+ 			funcs->backdoor_load = dmub_dcn21_backdoor_load;
+ 			funcs->setup_windows = dmub_dcn21_setup_windows;
+ 			funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done;
++			funcs->is_phy_init = dmub_dcn21_is_phy_init;
+ 		}
+ 		break;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4677-drm-amd-display-Return-DMUB_STATUS_OK-when-autoload-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4677-drm-amd-display-Return-DMUB_STATUS_OK-when-autoload-.patch
new file mode 100644
index 00000000..236a3b43
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4677-drm-amd-display-Return-DMUB_STATUS_OK-when-autoload-.patch
@@ -0,0 +1,55 @@
+From c13b68221785174927af4bfa3b0fbd3a16f422d4 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Thu, 7 Nov 2019 15:29:20 -0500
+Subject: [PATCH 4677/4736] drm/amd/display: Return DMUB_STATUS_OK when
+ autoload unsupported
+
+[Why]
+Not having support for autoload isn't an error. If the DMUB firmware
+doesn't support it then don't return DMUB_STATUS_INVALID.
+
+[How]
+Return DMUB_STATUS_OK when ->is_auto_load_done is NULL.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+index 3ec26f6af2e1..70c7a4be9ccc 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+@@ -379,9 +379,12 @@ enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
+ {
+ 	uint32_t i;
+ 
+-	if (!dmub->hw_init || !dmub->hw_funcs.is_auto_load_done)
++	if (!dmub->hw_init)
+ 		return DMUB_STATUS_INVALID;
+ 
++	if (!dmub->hw_funcs.is_auto_load_done)
++		return DMUB_STATUS_OK;
++
+ 	for (i = 0; i <= timeout_us; i += 100) {
+ 		if (dmub->hw_funcs.is_auto_load_done(dmub))
+ 			return DMUB_STATUS_OK;
+@@ -397,9 +400,12 @@ enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
+ {
+ 	uint32_t i = 0;
+ 
+-	if (!dmub->hw_init || !dmub->hw_funcs.is_phy_init)
++	if (!dmub->hw_init)
+ 		return DMUB_STATUS_INVALID;
+ 
++	if (!dmub->hw_funcs.is_phy_init)
++		return DMUB_STATUS_OK;
++
+ 	for (i = 0; i <= timeout_us; i += 10) {
+ 		if (dmub->hw_funcs.is_phy_init(dmub))
+ 			return DMUB_STATUS_OK;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4678-drm-amd-display-Program-CW5-for-tracebuffer-for-dcn2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4678-drm-amd-display-Program-CW5-for-tracebuffer-for-dcn2.patch
new file mode 100644
index 00000000..8ef818c9
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4678-drm-amd-display-Program-CW5-for-tracebuffer-for-dcn2.patch
@@ -0,0 +1,44 @@
+From 707425f3dc83a06cc415181f5feaeb564a8c06ae Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Thu, 7 Nov 2019 15:47:46 -0500
+Subject: [PATCH 4678/4736] drm/amd/display: Program CW5 for tracebuffer for
+ dcn20
+
+[Why]
+On dcn21 this is programmed for tracebuffer support but isn't being
+programmed on dcn20.
+
+DMCUB execution hits an undefined address 65000000 on tracebuffer
+access.
+
+[How]
+Program CW5.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+index 6b7d54572aa3..302dd3d4b77d 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+@@ -99,6 +99,13 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
+ 	REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS,
+ 		  cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE,
+ 		  1);
++
++	REG_WRITE(DMCUB_REGION3_CW5_OFFSET, cw5->offset.u.low_part);
++	REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, cw5->offset.u.high_part);
++	REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
++	REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
++		  DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
++		  DMCUB_REGION3_CW5_ENABLE, 1);
+ }
+ 
+ void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4679-drm-amd-display-populate-bios-integrated-info-for-re.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4679-drm-amd-display-populate-bios-integrated-info-for-re.patch
new file mode 100644
index 00000000..ad12328e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4679-drm-amd-display-populate-bios-integrated-info-for-re.patch
@@ -0,0 +1,75 @@
+From fb7ee5165ca7e7f7a2e32db8335f71b73550d8ff Mon Sep 17 00:00:00 2001
+From: Joseph Gravenor <joseph.gravenor@amd.com>
+Date: Thu, 7 Nov 2019 19:20:00 -0500
+Subject: [PATCH 4679/4736] drm/amd/display: populate bios integrated info for
+ renoir
+
+[Why]
+When video_memory_type bw_params->vram_type
+is assigned, wedistinguish between Ddr4MemType and LpDdr4MemType.
+Because of this we will never report that we are using
+LpDdr4MemType and never re-purpose WM set D
+
+[How]
+populate bios integrated info for renoir by adding the
+revision number for renoir and use that integrated info
+table instead of of asic_id to get the vram type
+
+Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c     |  1 +
+ .../gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c  | 10 ++++++----
+ 2 files changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index 453ac65c7ee3..8b2426f14519 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -1636,6 +1636,7 @@ static enum bp_result construct_integrated_info(
+ 		/* Don't need to check major revision as they are all 1 */
+ 		switch (revision.minor) {
+ 		case 11:
++		case 12:
+ 			result = get_integrated_info_v11(bp, info);
+ 			break;
+ 		default:
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 841095d09d3c..9f0381c68844 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -569,7 +569,7 @@ static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsi
+ 	return 0;
+ }
+ 
+-static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
++static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info)
+ {
+ 	int i, j = 0;
+ 
+@@ -601,8 +601,8 @@ static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params
+ 		bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
+ 	}
+ 
+-	bw_params->vram_type = asic_id->vram_type;
+-	bw_params->num_channels = asic_id->vram_width / DDR4_DRAM_WIDTH;
++	bw_params->vram_type = bios_info->memory_type;
++	bw_params->num_channels = bios_info->ma_channel_number;
+ 
+ 	for (i = 0; i < WM_SET_COUNT; i++) {
+ 		bw_params->wm_table.entries[i].wm_inst = i;
+@@ -685,7 +685,9 @@ void rn_clk_mgr_construct(
+ 
+ 	if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) {
+ 		pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table);
+-		rn_clk_mgr_helper_populate_bw_params(clk_mgr->base.bw_params, &clock_table, &ctx->asic_id);
++		if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
++			rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);
++		}
+ 	}
+ 
+ 	if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4680-drm-amd-display-Fixed-kernel-panic-when-booting-with.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4680-drm-amd-display-Fixed-kernel-panic-when-booting-with.patch
new file mode 100644
index 00000000..9c6914bb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4680-drm-amd-display-Fixed-kernel-panic-when-booting-with.patch
@@ -0,0 +1,37 @@
+From 05e89b05c79f619ba3a3cedf91309d8bcd76b61d Mon Sep 17 00:00:00 2001
+From: David Galiffi <David.Galiffi@amd.com>
+Date: Thu, 7 Nov 2019 17:18:20 -0500
+Subject: [PATCH 4680/4736] drm/amd/display: Fixed kernel panic when booting
+ with DP-to-HDMI dongle
+
+[Why]
+In dc_link_is_dp_sink_present, if dal_ddc_open fails, then
+dal_gpio_destroy_ddc is called, destroying pin_data and pin_clock. They
+are created only on dc_construct, and next aux access will cause a panic.
+
+[How]
+Instead of calling dal_gpio_destroy_ddc, call dal_ddc_close.
+
+Signed-off-by: David Galiffi <David.Galiffi@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 2accc35996cd..40d6415ba54d 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -370,7 +370,7 @@ bool dc_link_is_dp_sink_present(struct dc_link *link)
+ 
+ 	if (GPIO_RESULT_OK != dal_ddc_open(
+ 		ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
+-		dal_gpio_destroy_ddc(&ddc);
++		dal_ddc_close(ddc);
+ 
+ 		return present;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4681-drm-amd-display-have-two-different-sr-and-pstate-lat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4681-drm-amd-display-have-two-different-sr-and-pstate-lat.patch
new file mode 100644
index 00000000..f7407cc3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4681-drm-amd-display-have-two-different-sr-and-pstate-lat.patch
@@ -0,0 +1,164 @@
+From 14f863bbcbc727e06ca1257e9802fb6cf74a0b60 Mon Sep 17 00:00:00 2001
+From: Joseph Gravenor <joseph.gravenor@amd.com>
+Date: Fri, 8 Nov 2019 14:30:34 -0500
+Subject: [PATCH 4681/4736] drm/amd/display: have two different sr and pstate
+ latency tables for renoir
+
+[Why]
+new sr and pstate latencies are optimized for the case when we are not
+using lpddr4 memory
+
+[How]
+have two different wm tables, one for the lpddr case and one for
+non lpddr case
+
+Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 114 ++++++++++++------
+ 1 file changed, 80 insertions(+), 34 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 9f0381c68844..89ed230cdb26 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -518,44 +518,83 @@ struct clk_bw_params rn_bw_params = {
+ 		.num_entries = 4,
+ 	},
+ 
+-	.wm_table = {
+-		.entries = {
+-			{
+-				.wm_inst = WM_A,
+-				.wm_type = WM_TYPE_PSTATE_CHG,
+-				.pstate_latency_us = 11.72,
+-				.sr_exit_time_us = 6.09,
+-				.sr_enter_plus_exit_time_us = 7.14,
+-				.valid = true,
+-			},
+-			{
+-				.wm_inst = WM_B,
+-				.wm_type = WM_TYPE_PSTATE_CHG,
+-				.pstate_latency_us = 11.72,
+-				.sr_exit_time_us = 10.12,
+-				.sr_enter_plus_exit_time_us = 11.48,
+-				.valid = true,
+-			},
+-			{
+-				.wm_inst = WM_C,
+-				.wm_type = WM_TYPE_PSTATE_CHG,
+-				.pstate_latency_us = 11.72,
+-				.sr_exit_time_us = 10.12,
+-				.sr_enter_plus_exit_time_us = 11.48,
+-				.valid = true,
+-			},
+-			{
+-				.wm_inst = WM_D,
+-				.wm_type = WM_TYPE_PSTATE_CHG,
+-				.pstate_latency_us = 11.72,
+-				.sr_exit_time_us = 10.12,
+-				.sr_enter_plus_exit_time_us = 11.48,
+-				.valid = true,
+-			},
++};
++
++struct wm_table ddr4_wm_table = {
++	.entries = {
++		{
++			.wm_inst = WM_A,
++			.wm_type = WM_TYPE_PSTATE_CHG,
++			.pstate_latency_us = 11.72,
++			.sr_exit_time_us = 6.09,
++			.sr_enter_plus_exit_time_us = 7.14,
++			.valid = true,
++		},
++		{
++			.wm_inst = WM_B,
++			.wm_type = WM_TYPE_PSTATE_CHG,
++			.pstate_latency_us = 11.72,
++			.sr_exit_time_us = 10.12,
++			.sr_enter_plus_exit_time_us = 11.48,
++			.valid = true,
++		},
++		{
++			.wm_inst = WM_C,
++			.wm_type = WM_TYPE_PSTATE_CHG,
++			.pstate_latency_us = 11.72,
++			.sr_exit_time_us = 10.12,
++			.sr_enter_plus_exit_time_us = 11.48,
++			.valid = true,
++		},
++		{
++			.wm_inst = WM_D,
++			.wm_type = WM_TYPE_PSTATE_CHG,
++			.pstate_latency_us = 11.72,
++			.sr_exit_time_us = 10.12,
++			.sr_enter_plus_exit_time_us = 11.48,
++			.valid = true,
+ 		},
+ 	}
+ };
+ 
++struct wm_table lpddr4_wm_table = {
++	.entries = {
++		{
++			.wm_inst = WM_A,
++			.wm_type = WM_TYPE_PSTATE_CHG,
++			.pstate_latency_us = 23.84,
++			.sr_exit_time_us = 12.5,
++			.sr_enter_plus_exit_time_us = 17.0,
++			.valid = true,
++		},
++		{
++			.wm_inst = WM_B,
++			.wm_type = WM_TYPE_PSTATE_CHG,
++			.pstate_latency_us = 23.84,
++			.sr_exit_time_us = 12.5,
++			.sr_enter_plus_exit_time_us = 17.0,
++			.valid = true,
++		},
++		{
++			.wm_inst = WM_C,
++			.wm_type = WM_TYPE_PSTATE_CHG,
++			.pstate_latency_us = 23.84,
++			.sr_exit_time_us = 12.5,
++			.sr_enter_plus_exit_time_us = 17.0,
++			.valid = true,
++		},
++		{
++			.wm_inst = WM_D,
++			.wm_type = WM_TYPE_PSTATE_CHG,
++			.pstate_latency_us = 23.84,
++			.sr_exit_time_us = 12.5,
++			.sr_enter_plus_exit_time_us = 17.0,
++			.valid = true,
++		},
++	}
++};
++
++
+ static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
+ {
+ 	int i;
+@@ -677,10 +716,17 @@ void rn_clk_mgr_construct(
+ 			ASSERT(clk_mgr->base.dprefclk_khz == 600000);
+ 			clk_mgr->base.dprefclk_khz = 600000;
+ 		}
++
++		if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) {
++			rn_bw_params.wm_table = lpddr4_wm_table;
++		} else {
++			rn_bw_params.wm_table = ddr4_wm_table;
++		}
+ 	}
+ 
+ 	dce_clock_read_ss_info(clk_mgr);
+ 
++
+ 	clk_mgr->base.bw_params = &rn_bw_params;
+ 
+ 	if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4682-drm-amd-display-fix-dprefclk-and-ss-percentage-readi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4682-drm-amd-display-fix-dprefclk-and-ss-percentage-readi.patch
new file mode 100644
index 00000000..f6319283
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4682-drm-amd-display-fix-dprefclk-and-ss-percentage-readi.patch
@@ -0,0 +1,103 @@
+From 05da4bf83601928e4f9292175592c4cbf74ef0cd Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Sun, 10 Nov 2019 12:08:02 -0500
+Subject: [PATCH 4682/4736] drm/amd/display: fix dprefclk and ss percentage
+ reading on RN
+
+[Why]
+Before was using HW counter value to determine the dprefclk. Which
+take into account ss, but has large variation, not good enough for
+generating audio dto. Also, the bios parser code to get the ss
+percentage was not working.
+
+[How]
+After this change, dprefclk is hard coded, same as on RV. We don't
+expect this to change on Renoir. Modified bios parser code to get
+the right ss percentage.
+
+Change-Id: Ifed07a5d523b213769b6f7ed4f207cf2dc0108cd
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ .../gpu/drm/amd/display/dc/bios/bios_parser2.c   |  1 +
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c    | 16 +++-------------
+ drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h  |  1 +
+ 3 files changed, 5 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+index 8b2426f14519..42babd82ce6b 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+@@ -832,6 +832,7 @@ static enum bp_result bios_parser_get_spread_spectrum_info(
+ 		case 1:
+ 			return get_ss_info_v4_1(bp, signal, index, ss_info);
+ 		case 2:
++		case 3:
+ 			return get_ss_info_v4_2(bp, signal, index, ss_info);
+ 		default:
+ 			break;
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 89ed230cdb26..307c8540e36f 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -675,7 +675,6 @@ void rn_clk_mgr_construct(
+ {
+ 	struct dc_debug_options *debug = &ctx->dc->debug;
+ 	struct dpm_clocks clock_table = { 0 };
+-	struct clk_state_registers_and_bypass s = { 0 };
+ 
+ 	clk_mgr->base.ctx = ctx;
+ 	clk_mgr->base.funcs = &dcn21_funcs;
+@@ -695,7 +694,6 @@ void rn_clk_mgr_construct(
+ 	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
+ 		dcn21_funcs.update_clocks = dcn2_update_clocks_fpga;
+ 		clk_mgr->base.dentist_vco_freq_khz = 3600000;
+-		clk_mgr->base.dprefclk_khz = 600000;
+ 	} else {
+ 		struct clk_log_info log_info = {0};
+ 
+@@ -706,24 +704,16 @@ void rn_clk_mgr_construct(
+ 		if (clk_mgr->base.dentist_vco_freq_khz == 0)
+ 			clk_mgr->base.dentist_vco_freq_khz = 3600000;
+ 
+-		rn_dump_clk_registers(&s, &clk_mgr->base, &log_info);
+-		/* Convert dprefclk units from MHz to KHz */
+-		/* Value already divided by 10, some resolution lost */
+-		clk_mgr->base.dprefclk_khz = s.dprefclk * 1000;
+-
+-		/* in case we don't get a value from the register, use default */
+-		if (clk_mgr->base.dprefclk_khz == 0) {
+-			ASSERT(clk_mgr->base.dprefclk_khz == 600000);
+-			clk_mgr->base.dprefclk_khz = 600000;
+-		}
+-
+ 		if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) {
+ 			rn_bw_params.wm_table = lpddr4_wm_table;
+ 		} else {
+ 			rn_bw_params.wm_table = ddr4_wm_table;
+ 		}
++		/* Saved clocks configured at boot for debug purposes */
++		rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
+ 	}
+ 
++	clk_mgr->base.dprefclk_khz = 600000;
+ 	dce_clock_read_ss_info(clk_mgr);
+ 
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+index 026e6a2a2c44..c10cb4b54fae 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+@@ -196,6 +196,7 @@ struct clk_mgr {
+ 	int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
+ 	int dentist_vco_freq_khz;
+ #ifdef CONFIG_DRM_AMD_DC_DCN2_1
++	struct clk_state_registers_and_bypass boot_snapshot;
+ 	struct clk_bw_params *bw_params;
+ #endif
+ };
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4683-drm-amd-display-3.2.61.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4683-drm-amd-display-3.2.61.patch
new file mode 100644
index 00000000..b7a20366
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4683-drm-amd-display-3.2.61.patch
@@ -0,0 +1,28 @@
+From a2504978d354a7bfe97b5cac99b19d55edb728ee Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Mon, 11 Nov 2019 10:07:50 -0500
+Subject: [PATCH 4683/4736] drm/amd/display: 3.2.61
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index d710e123b53a..df833b6937a1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.60"
++#define DC_VER "3.2.61"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4684-drm-amd-display-Change-the-delay-time-before-enablin.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4684-drm-amd-display-Change-the-delay-time-before-enablin.patch
new file mode 100644
index 00000000..2f211973
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4684-drm-amd-display-Change-the-delay-time-before-enablin.patch
@@ -0,0 +1,47 @@
+From 9dfa55f00ad9fc538d374cfc59d35b63b51f653a Mon Sep 17 00:00:00 2001
+From: "Leo (Hanghong) Ma" <hanghong.ma@amd.com>
+Date: Thu, 7 Nov 2019 16:30:04 -0500
+Subject: [PATCH 4684/4736] drm/amd/display: Change the delay time before
+ enabling FEC
+
+[why]
+DP spec requires 1000 symbols delay between the end of link training
+and enabling FEC in the stream. Currently we are using 1 miliseconds
+delay which is not accurate.
+
+[how]
+One lane RBR should have the maximum time for transmitting 1000 LL
+codes which is 6.173 us. So using 7 microseconds delay instead of
+1 miliseconds.
+
+Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
+Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
+Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 537b4dee8f22..b10019106030 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -3951,7 +3951,14 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)
+ 	if (link_enc->funcs->fec_set_enable &&
+ 			link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
+ 		if (link->fec_state == dc_link_fec_ready && enable) {
+-			msleep(1);
++			/* Accord to DP spec, FEC enable sequence can first
++			 * be transmitted anytime after 1000 LL codes have
++			 * been transmitted on the link after link training
++			 * completion. Using 1 lane RBR should have the maximum
++			 * time for transmitting 1000 LL codes which is 6.173 us.
++			 * So use 7 microseconds delay instead.
++			 */
++			udelay(7);
+ 			link_enc->funcs->fec_set_enable(link_enc, true);
+ 			link->fec_state = dc_link_fec_enabled;
+ 		} else if (link->fec_state == dc_link_fec_enabled && !enable) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4685-drm-amd-display-fixed-that-I2C-over-AUX-didn-t-read-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4685-drm-amd-display-fixed-that-I2C-over-AUX-didn-t-read-.patch
new file mode 100644
index 00000000..578655ea
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4685-drm-amd-display-fixed-that-I2C-over-AUX-didn-t-read-.patch
@@ -0,0 +1,49 @@
+From a6dc8c5b31899bb6da79f3537291a92e16fd2007 Mon Sep 17 00:00:00 2001
+From: Brandon Syu <Brandon.Syu@amd.com>
+Date: Fri, 8 Nov 2019 11:26:06 +0800
+Subject: [PATCH 4685/4736] drm/amd/display: fixed that I2C over AUX didn't
+ read data issue
+
+[Why]
+The variable mismatch assignment error.
+
+[How]
+To use uint32_t replace it.
+
+Signed-off-by: Brandon Syu <Brandon.Syu@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c      | 2 +-
+ drivers/gpu/drm/amd/display/include/i2caux_interface.h | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+index 60d3c164495d..c4950c735485 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+@@ -587,7 +587,7 @@ bool dal_ddc_service_query_ddc_data(
+ bool dal_ddc_submit_aux_command(struct ddc_service *ddc,
+ 		struct aux_payload *payload)
+ {
+-	uint8_t retrieved = 0;
++	uint32_t retrieved = 0;
+ 	bool ret = 0;
+ 
+ 	if (!ddc)
+diff --git a/drivers/gpu/drm/amd/display/include/i2caux_interface.h b/drivers/gpu/drm/amd/display/include/i2caux_interface.h
+index bb012cb1a9f5..c7fbb9c3ad6b 100644
+--- a/drivers/gpu/drm/amd/display/include/i2caux_interface.h
++++ b/drivers/gpu/drm/amd/display/include/i2caux_interface.h
+@@ -42,7 +42,7 @@ struct aux_payload {
+ 	bool write;
+ 	bool mot;
+ 	uint32_t address;
+-	uint8_t length;
++	uint32_t length;
+ 	uint8_t *data;
+ 	/*
+ 	 * used to return the reply type of the transaction
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4686-drm-amd-display-add-log-for-lttpr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4686-drm-amd-display-add-log-for-lttpr.patch
new file mode 100644
index 00000000..de5db3f8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4686-drm-amd-display-add-log-for-lttpr.patch
@@ -0,0 +1,214 @@
+From f9251f29e72debc2f3a47f3e9eacf0d6b48bf169 Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Wed, 23 Oct 2019 17:16:51 -0400
+Subject: [PATCH 4686/4736] drm/amd/display: add log for lttpr
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 125 +++++++++++++-----
+ 1 file changed, 93 insertions(+), 32 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index b10019106030..486c14e0cd41 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -255,11 +255,18 @@ static void dpcd_set_lt_pattern_and_lane_settings(
+ 	dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
+ 		= dpcd_pattern.raw;
+ 
+-	DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
+-		__func__,
+-		dpcd_base_lt_offset,
+-		dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
+-
++	if (is_repeater(link, offset)) {
++		DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
++			__func__,
++			offset,
++			dpcd_base_lt_offset,
++			dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
++	} else {
++		DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
++			__func__,
++			dpcd_base_lt_offset,
++			dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
++	}
+ 	/*****************************************************************
+ 	* DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
+ 	*****************************************************************/
+@@ -289,14 +296,25 @@ static void dpcd_set_lt_pattern_and_lane_settings(
+ 		dpcd_lane,
+ 		size_in_bytes);
+ 
+-	DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
+-		__func__,
+-		dpcd_base_lt_offset,
+-		dpcd_lane[0].bits.VOLTAGE_SWING_SET,
+-		dpcd_lane[0].bits.PRE_EMPHASIS_SET,
+-		dpcd_lane[0].bits.MAX_SWING_REACHED,
+-		dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
+-
++	if (is_repeater(link, offset)) {
++		DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
++				" 0x%X VS set = %x PE set = %x max VS Reached = %x  max PE Reached = %x\n",
++			__func__,
++			offset,
++			dpcd_base_lt_offset,
++			dpcd_lane[0].bits.VOLTAGE_SWING_SET,
++			dpcd_lane[0].bits.PRE_EMPHASIS_SET,
++			dpcd_lane[0].bits.MAX_SWING_REACHED,
++			dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
++	} else {
++		DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
++			__func__,
++			dpcd_base_lt_offset,
++			dpcd_lane[0].bits.VOLTAGE_SWING_SET,
++			dpcd_lane[0].bits.PRE_EMPHASIS_SET,
++			dpcd_lane[0].bits.MAX_SWING_REACHED,
++			dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
++	}
+ 	if (edp_workaround) {
+ 		/* for eDP write in 2 parts because the 5-byte burst is
+ 		* causing issues on some eDP panels (EPR#366724)
+@@ -544,23 +562,42 @@ static void get_lane_status_and_drive_settings(
+ 
+ 	ln_status_updated->raw = dpcd_buf[2];
+ 
+-	DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
+-		__func__,
+-		lane01_status_address, dpcd_buf[0],
+-		lane01_status_address + 1, dpcd_buf[1]);
+-
++	if (is_repeater(link, offset)) {
++		DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
++				" 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
++			__func__,
++			offset,
++			lane01_status_address, dpcd_buf[0],
++			lane01_status_address + 1, dpcd_buf[1]);
++	} else {
++		DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
++			__func__,
++			lane01_status_address, dpcd_buf[0],
++			lane01_status_address + 1, dpcd_buf[1]);
++	}
+ 	lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
+ 
+ 	if (is_repeater(link, offset))
+ 		lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
+ 				((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
+ 
+-	DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
+-		__func__,
+-		lane01_adjust_address,
+-		dpcd_buf[lane_adjust_offset],
+-		lane01_adjust_address + 1,
+-		dpcd_buf[lane_adjust_offset + 1]);
++	if (is_repeater(link, offset)) {
++		DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
++				" 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
++					__func__,
++					offset,
++					lane01_adjust_address,
++					dpcd_buf[lane_adjust_offset],
++					lane01_adjust_address + 1,
++					dpcd_buf[lane_adjust_offset + 1]);
++	} else {
++		DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
++			__func__,
++			lane01_adjust_address,
++			dpcd_buf[lane_adjust_offset],
++			lane01_adjust_address + 1,
++			dpcd_buf[lane_adjust_offset + 1]);
++	}
+ 
+ 	/*copy to req_settings*/
+ 	request_settings.link_settings.lane_count =
+@@ -656,14 +693,26 @@ static void dpcd_set_lane_settings(
+ 	}
+ 	*/
+ 
+-	DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
+-		__func__,
+-		lane0_set_address,
+-		dpcd_lane[0].bits.VOLTAGE_SWING_SET,
+-		dpcd_lane[0].bits.PRE_EMPHASIS_SET,
+-		dpcd_lane[0].bits.MAX_SWING_REACHED,
+-		dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
++	if (is_repeater(link, offset)) {
++		DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
++				" 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
++			__func__,
++			offset,
++			lane0_set_address,
++			dpcd_lane[0].bits.VOLTAGE_SWING_SET,
++			dpcd_lane[0].bits.PRE_EMPHASIS_SET,
++			dpcd_lane[0].bits.MAX_SWING_REACHED,
++			dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
+ 
++	} else {
++		DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
++			__func__,
++			lane0_set_address,
++			dpcd_lane[0].bits.VOLTAGE_SWING_SET,
++			dpcd_lane[0].bits.PRE_EMPHASIS_SET,
++			dpcd_lane[0].bits.MAX_SWING_REACHED,
++			dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
++	}
+ 	link->cur_lane_setting = link_training_setting->lane_settings[0];
+ 
+ }
+@@ -1170,12 +1219,16 @@ static void configure_lttpr_mode(struct dc_link *link)
+ 	uint8_t repeater_id;
+ 	uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
+ 
++	DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
+ 	core_link_write_dpcd(link,
+ 			DP_PHY_REPEATER_MODE,
+ 			(uint8_t *)&repeater_mode,
+ 			sizeof(repeater_mode));
+ 
+ 	if (!link->is_lttpr_mode_transparent) {
++
++		DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
++
+ 		repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
+ 		core_link_write_dpcd(link,
+ 				DP_PHY_REPEATER_MODE,
+@@ -1212,8 +1265,9 @@ static void repeater_training_done(struct dc_link *link, uint32_t offset)
+ 		&dpcd_pattern.raw,
+ 		1);
+ 
+-	DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
++	DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
+ 		__func__,
++		offset,
+ 		dpcd_base_lt_offset,
+ 		dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
+ }
+@@ -1663,6 +1717,11 @@ static struct dc_link_settings get_max_link_cap(struct dc_link *link)
+ 
+ 		if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
+ 			max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
++
++		DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR,  max_lane count %d max_link rate %d \n",
++						__func__,
++						max_link_cap.lane_count,
++						max_link_cap.link_rate);
+ 	}
+ 	return max_link_cap;
+ }
+@@ -3196,6 +3255,8 @@ static bool retrieve_link_cap(struct dc_link *link)
+ 			link->is_lttpr_mode_transparent = true;
+ 			dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
+ 		}
++
++		CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
+ 	}
+ 
+ 	{
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4687-drm-amd-display-Disable-chroma-viewport-w-a-when-rot.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4687-drm-amd-display-Disable-chroma-viewport-w-a-when-rot.patch
new file mode 100644
index 00000000..9682d6fb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4687-drm-amd-display-Disable-chroma-viewport-w-a-when-rot.patch
@@ -0,0 +1,131 @@
+From d3fbb8d0c854c97620eed517bd2b48138144f6cd Mon Sep 17 00:00:00 2001
+From: Michael Strauss <michael.strauss@amd.com>
+Date: Sun, 10 Nov 2019 15:22:15 -0500
+Subject: [PATCH 4687/4736] drm/amd/display: Disable chroma viewport w/a when
+ rotated 180 degrees
+
+[WHY]
+Previous Renoir chroma viewport workaround fixed an MPO flicker by
+increasing the chroma viewport size. However, when the MPO plane is
+rotated 180 degrees, the viewport is read in reverse. Since the workaround
+increases viewport size, when reading in reverse it causes a vertical
+chroma offset.
+
+[HOW]
+Pass rotation value to viewport set functions
+Temporarily disable the chroma viewport w/a when hubp is rotated 180 degrees
+
+Signed-off-by: Michael Strauss <michael.strauss@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c         | 3 ++-
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h         | 4 +++-
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++-
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c        | 3 ++-
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c         | 7 +++++--
+ drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h              | 4 +++-
+ 6 files changed, 17 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+index 31b64733d693..4d1301e5eaf5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+@@ -810,7 +810,8 @@ static void hubp1_set_vm_context0_settings(struct hubp *hubp,
+ void min_set_viewport(
+ 	struct hubp *hubp,
+ 	const struct rect *viewport,
+-	const struct rect *viewport_c)
++	const struct rect *viewport_c,
++	enum dc_rotation_angle rotation)
+ {
+ 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+index 780af5b3c16f..e44eaae5033b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+@@ -749,7 +749,9 @@ void hubp1_set_blank(struct hubp *hubp, bool blank);
+ 
+ void min_set_viewport(struct hubp *hubp,
+ 		const struct rect *viewport,
+-		const struct rect *viewport_c);
++		const struct rect *viewport_c,
++		enum dc_rotation_angle rotation);
++/* rotation angle added for use by hubp21_set_viewport */
+ 
+ void hubp1_clk_cntl(struct hubp *hubp, bool enable);
+ void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 528a6a953be4..24bebec84316 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2288,7 +2288,8 @@ static void dcn10_update_dchubp_dpp(
+ 		hubp->funcs->mem_program_viewport(
+ 			hubp,
+ 			&pipe_ctx->plane_res.scl_data.viewport,
+-			&pipe_ctx->plane_res.scl_data.viewport_c);
++			&pipe_ctx->plane_res.scl_data.viewport_c,
++			plane_state->rotation);
+ 	}
+ 
+ 	if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index d99e882bd555..3e016a57f1ac 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1386,7 +1386,8 @@ static void dcn20_update_dchubp_dpp(
+ 		hubp->funcs->mem_program_viewport(
+ 			hubp,
+ 			&pipe_ctx->plane_res.scl_data.viewport,
+-			&pipe_ctx->plane_res.scl_data.viewport_c);
++			&pipe_ctx->plane_res.scl_data.viewport_c,
++			plane_state->rotation);
+ 
+ 	/* Any updates are handled in dc interface, just need to apply existing for plane enable */
+ 	if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed)
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+index 4408aed5087b..38661b9c61f8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+@@ -169,7 +169,8 @@ static void hubp21_setup(
+ void hubp21_set_viewport(
+ 	struct hubp *hubp,
+ 	const struct rect *viewport,
+-	const struct rect *viewport_c)
++	const struct rect *viewport_c,
++	enum dc_rotation_angle rotation)
+ {
+ 	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
+ 	int patched_viewport_height = 0;
+@@ -196,9 +197,11 @@ void hubp21_set_viewport(
+ 	 *	Work around for underflow issue with NV12 + rIOMMU translation
+ 	 *	+ immediate flip. This will cause hubp underflow, but will not
+ 	 *	be user visible since underflow is in blank region
++	 *	Disable w/a when rotated 180 degrees, causes vertical chroma offset
+ 	 */
+ 	patched_viewport_height = viewport_c->height;
+-	if (viewport_c->height != 0 && debug->nv12_iflip_vm_wa) {
++	if (viewport_c->height != 0 && debug->nv12_iflip_vm_wa &&
++			rotation != ROTATION_ANGLE_180) {
+ 		int pte_row_height = 0;
+ 		int pte_rows = 0;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+index 9793da0f3c7e..85a34dde8526 100644
+--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+@@ -82,7 +82,9 @@ struct hubp_funcs {
+ 	void (*mem_program_viewport)(
+ 			struct hubp *hubp,
+ 			const struct rect *viewport,
+-			const struct rect *viewport_c);
++			const struct rect *viewport_c,
++			enum dc_rotation_angle rotation);
++			/* rotation needed for Renoir workaround */
+ 
+ 	bool (*hubp_program_surface_flip_and_addr)(
+ 		struct hubp *hubp,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4688-drm-amd-display-fix-dml20-min_dst_y_next_start-calcu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4688-drm-amd-display-fix-dml20-min_dst_y_next_start-calcu.patch
new file mode 100644
index 00000000..241017f7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4688-drm-amd-display-fix-dml20-min_dst_y_next_start-calcu.patch
@@ -0,0 +1,32 @@
+From 3203b77954977f6e42bd469ce6cf8bfaaa3d07d1 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Fri, 8 Nov 2019 16:20:36 -0500
+Subject: [PATCH 4688/4736] drm/amd/display: fix dml20 min_dst_y_next_start
+ calculation
+
+Bring this calculation in line with HW programming guide.
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c  | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
+index 2c7455e22a65..9df24ececcec 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c
+@@ -929,8 +929,7 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
+ 	min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
+ 	dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
+ 
+-	disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start
+-			+ min_dst_y_ttu_vblank) * dml_pow(2, 2));
++	disp_dlg_regs->min_dst_y_next_start = (unsigned int) ((double) dlg_vblank_start * dml_pow(2, 2));
+ 	ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
+ 
+ 	dml_print("DML_DLG: %s: min_dcfclk_mhz                         = %3.2f\n",
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4689-drm-amd-display-Reset-steer-fifo-before-unblanking-t.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4689-drm-amd-display-Reset-steer-fifo-before-unblanking-t.patch
new file mode 100644
index 00000000..1d5fcbee
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4689-drm-amd-display-Reset-steer-fifo-before-unblanking-t.patch
@@ -0,0 +1,56 @@
+From fc58a25e03e6f56115fda22aab113533d1932c93 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Mon, 11 Nov 2019 18:03:59 -0500
+Subject: [PATCH 4689/4736] drm/amd/display: Reset steer fifo before unblanking
+ the stream
+
+[why]
+During mode transition steer fifo could overflow. Quite often it
+recovers by itself, but sometimes it doesn't.
+
+[how]
+Add steer fifo reset before unblanking the stream. Also add a short
+delay when resetting dig resync fifo to make sure register writes
+don't end up back-to-back, in which case the HW might miss the reset
+request.
+
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_stream_encoder.c  | 12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+index 3549c81b20b7..99f33c7ae528 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+@@ -486,15 +486,23 @@ void enc2_stream_encoder_dp_unblank(
+ 				DP_VID_N_MUL, n_multiply);
+ 	}
+ 
+-	/* set DIG_START to 0x1 to reset FIFO */
++	/* make sure stream is disabled before resetting steer fifo */
++	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
++	REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);
+ 
++	/* set DIG_START to 0x1 to reset FIFO */
+ 	REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
++	udelay(1);
+ 
+ 	/* write 0 to take the FIFO out of reset */
+ 
+ 	REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
+ 
+-	/* switch DP encoder to CRTC data */
++	/* switch DP encoder to CRTC data, but reset it the fifo first. It may happen
++	 * that it overflows during mode transition, and sometimes doesn't recover.
++	 */
++	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);
++	udelay(10);
+ 
+ 	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4690-drm-amd-display-Implement-DePQ-for-DCN1.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4690-drm-amd-display-Implement-DePQ-for-DCN1.patch
new file mode 100644
index 00000000..7a67aef7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4690-drm-amd-display-Implement-DePQ-for-DCN1.patch
@@ -0,0 +1,120 @@
+From 64560f50a8b042c94320253268f0611beee3ead8 Mon Sep 17 00:00:00 2001
+From: Reza Amini <Reza.Amini@amd.com>
+Date: Thu, 7 Nov 2019 10:10:45 -0500
+Subject: [PATCH 4690/4736] drm/amd/display: Implement DePQ for DCN1
+
+[Why]
+Need support for more color management in 10bit
+surface.
+
+[How]
+Provide support for DePQ for 10bit surface
+
+Signed-off-by: Reza Amini <Reza.Amini@amd.com>
+Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c   |  3 ++
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  5 +++
+ .../amd/display/modules/color/color_gamma.c   | 39 ++++++++++++++-----
+ 3 files changed, 38 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+index 6b7593dd0c77..935c892622a0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+@@ -628,6 +628,9 @@ void dpp1_set_degamma(
+ 	case IPP_DEGAMMA_MODE_HW_xvYCC:
+ 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);
+ 			break;
++	case IPP_DEGAMMA_MODE_USER_PWL:
++		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3);
++		break;
+ 	default:
+ 		BREAK_TO_DEBUGGER();
+ 		break;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 24bebec84316..0e1e3dcf4112 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -1467,6 +1467,11 @@ bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
+ 			dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
+ 			break;
+ 		case TRANSFER_FUNCTION_PQ:
++			dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
++			cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
++			dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
++			result = true;
++			break;
+ 		default:
+ 			result = false;
+ 			break;
+diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+index 3f467c98b02f..3ab6cb3a09d6 100644
+--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
++++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+@@ -151,6 +151,7 @@ static void compute_de_pq(struct fixed31_32 in_x, struct fixed31_32 *out_y)
+ 
+ 	struct fixed31_32 l_pow_m1;
+ 	struct fixed31_32 base, div;
++	struct fixed31_32 base2;
+ 
+ 
+ 	if (dc_fixpt_lt(in_x, dc_fixpt_zero))
+@@ -160,13 +161,15 @@ static void compute_de_pq(struct fixed31_32 in_x, struct fixed31_32 *out_y)
+ 			dc_fixpt_div(dc_fixpt_one, m2));
+ 	base = dc_fixpt_sub(l_pow_m1, c1);
+ 
+-	if (dc_fixpt_lt(base, dc_fixpt_zero))
+-		base = dc_fixpt_zero;
+-
+ 	div = dc_fixpt_sub(c2, dc_fixpt_mul(c3, l_pow_m1));
+ 
+-	*out_y = dc_fixpt_pow(dc_fixpt_div(base, div),
+-			dc_fixpt_div(dc_fixpt_one, m1));
++	base2 = dc_fixpt_div(base, div);
++	//avoid complex numbers
++	if (dc_fixpt_lt(base2, dc_fixpt_zero))
++		base2 = dc_fixpt_sub(dc_fixpt_zero, base2);
++
++
++	*out_y = dc_fixpt_pow(base2, dc_fixpt_div(dc_fixpt_one, m1));
+ 
+ }
+ 
+@@ -1995,10 +1998,28 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf,
+ 	tf_pts->x_point_at_y1_green = 1;
+ 	tf_pts->x_point_at_y1_blue = 1;
+ 
+-	map_regamma_hw_to_x_user(ramp, coeff, rgb_user,
+-			coordinates_x, axis_x, curve,
+-			MAX_HW_POINTS, tf_pts,
+-			mapUserRamp && ramp && ramp->type == GAMMA_RGB_256);
++	if (input_tf->tf == TRANSFER_FUNCTION_PQ) {
++		/* just copy current rgb_regamma into  tf_pts */
++		struct pwl_float_data_ex *curvePt = curve;
++		int i = 0;
++
++		while (i <= MAX_HW_POINTS) {
++			tf_pts->red[i]   = curvePt->r;
++			tf_pts->green[i] = curvePt->g;
++			tf_pts->blue[i]  = curvePt->b;
++			++curvePt;
++			++i;
++		}
++	} else {
++		//clamps to 0-1
++		map_regamma_hw_to_x_user(ramp, coeff, rgb_user,
++				coordinates_x, axis_x, curve,
++				MAX_HW_POINTS, tf_pts,
++				mapUserRamp && ramp && ramp->type == GAMMA_RGB_256);
++	}
++
++
++
+ 	if (ramp->type == GAMMA_CUSTOM)
+ 		apply_lut_1d(ramp, MAX_HW_POINTS, tf_pts);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4691-drm-amd-display-update-p-state-latency-for-renoir-wh.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4691-drm-amd-display-update-p-state-latency-for-renoir-wh.patch
new file mode 100644
index 00000000..dd1a4f16
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4691-drm-amd-display-update-p-state-latency-for-renoir-wh.patch
@@ -0,0 +1,63 @@
+From 8968f964b88aa9e59aa07885e016a8c4acf9216f Mon Sep 17 00:00:00 2001
+From: Joseph Gravenor <joseph.gravenor@amd.com>
+Date: Tue, 12 Nov 2019 15:36:57 -0500
+Subject: [PATCH 4691/4736] drm/amd/display: update p-state latency for renoir
+ when using lpddr4
+
+[Why]
+DF team has produced more optimized latency numbers, for lpddr4
+
+[How]
+change the p-state laency in the lpddr4 wm table to the new latency
+number
+
+Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 307c8540e36f..901e7035bf8e 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -562,7 +562,7 @@ struct wm_table lpddr4_wm_table = {
+ 		{
+ 			.wm_inst = WM_A,
+ 			.wm_type = WM_TYPE_PSTATE_CHG,
+-			.pstate_latency_us = 23.84,
++			.pstate_latency_us = 11.65333,
+ 			.sr_exit_time_us = 12.5,
+ 			.sr_enter_plus_exit_time_us = 17.0,
+ 			.valid = true,
+@@ -570,7 +570,7 @@ struct wm_table lpddr4_wm_table = {
+ 		{
+ 			.wm_inst = WM_B,
+ 			.wm_type = WM_TYPE_PSTATE_CHG,
+-			.pstate_latency_us = 23.84,
++			.pstate_latency_us = 11.65333,
+ 			.sr_exit_time_us = 12.5,
+ 			.sr_enter_plus_exit_time_us = 17.0,
+ 			.valid = true,
+@@ -578,7 +578,7 @@ struct wm_table lpddr4_wm_table = {
+ 		{
+ 			.wm_inst = WM_C,
+ 			.wm_type = WM_TYPE_PSTATE_CHG,
+-			.pstate_latency_us = 23.84,
++			.pstate_latency_us = 11.65333,
+ 			.sr_exit_time_us = 12.5,
+ 			.sr_enter_plus_exit_time_us = 17.0,
+ 			.valid = true,
+@@ -586,7 +586,7 @@ struct wm_table lpddr4_wm_table = {
+ 		{
+ 			.wm_inst = WM_D,
+ 			.wm_type = WM_TYPE_PSTATE_CHG,
+-			.pstate_latency_us = 23.84,
++			.pstate_latency_us = 11.65333,
+ 			.sr_exit_time_us = 12.5,
+ 			.sr_enter_plus_exit_time_us = 17.0,
+ 			.valid = true,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4692-drm-amd-display-add-DP-protocol-version.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4692-drm-amd-display-add-DP-protocol-version.patch
new file mode 100644
index 00000000..e75d2606
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4692-drm-amd-display-add-DP-protocol-version.patch
@@ -0,0 +1,61 @@
+From fe8a3a4343e0503c30cb22f11ebd949daab072b2 Mon Sep 17 00:00:00 2001
+From: Anthony Koo <Anthony.Koo@amd.com>
+Date: Wed, 13 Nov 2019 14:04:56 -0500
+Subject: [PATCH 4692/4736] drm/amd/display: add DP protocol version
+
+[Why]
+We want to know DP protocol version
+
+[How]
+In DC create we initialize a cap to indicate the max
+DP protocol version supported
+
+Change-Id: I9a5a356fa1ec008037ce3c27fc2872da83855f1f
+Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
+ drivers/gpu/drm/amd/display/dc/dc.h      | 5 +++++
+ 2 files changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 1e4919687ece..97da6384348a 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -820,6 +820,8 @@ struct dc *dc_create(const struct dc_init_data *init_params)
+ 	dc->caps.max_audios = dc->res_pool->audio_count;
+ 	dc->caps.linear_pitch_alignment = 64;
+ 
++	dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
++
+ 	/* Populate versioning information */
+ 	dc->versions.dc_ver = DC_VER;
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index df833b6937a1..f4884548e77e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -54,6 +54,10 @@ struct dc_versions {
+ 	struct dmcu_version dmcu_version;
+ };
+ 
++enum dp_protocol_version {
++	DP_VERSION_1_4,
++};
++
+ enum dc_plane_type {
+ 	DC_PLANE_TYPE_INVALID,
+ 	DC_PLANE_TYPE_DCE_RGB,
+@@ -114,6 +118,7 @@ struct dc_caps {
+ 	bool extended_aux_timeout_support;
+ 	bool dmcub_support;
+ 	bool hw_3d_lut;
++	enum dp_protocol_version max_dp_protocol_version;
+ 	struct dc_plane_cap planes[MAX_PLANES];
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4693-drm-amd-display-Save-restore-link-setting-for-disabl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4693-drm-amd-display-Save-restore-link-setting-for-disabl.patch
new file mode 100644
index 00000000..c1ff8623
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4693-drm-amd-display-Save-restore-link-setting-for-disabl.patch
@@ -0,0 +1,50 @@
+From 427f0e33f6917ce94cf794568d357bbe66bf4d7f Mon Sep 17 00:00:00 2001
+From: Hugo Hu <hugo.hu@amd.com>
+Date: Wed, 13 Nov 2019 16:18:09 -0500
+Subject: [PATCH 4693/4736] drm/amd/display: Save/restore link setting for
+ disable phy when link retraining
+
+[Why]
+The link setting will be modify after disable phy
+and due to DP Compliance Fails.
+
+[How]
+Save and resotre link setting for disable link phy when link retraining.
+
+Signed-off-by: Hugo Hu <hugo.hu@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 486c14e0cd41..015fa0c52746 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -2788,9 +2788,9 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd
+ 	union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
+ 	union device_service_irq device_service_clear = { { 0 } };
+ 	enum dc_status result;
+-
+ 	bool status = false;
+ 	struct pipe_ctx *pipe_ctx;
++	struct dc_link_settings previous_link_settings;
+ 	int i;
+ 
+ 	if (out_link_loss)
+@@ -2873,9 +2873,10 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd
+ 		if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
+ 			return false;
+ 
++		previous_link_settings = link->cur_link_settings;
+ 		dp_disable_link_phy(link, pipe_ctx->stream->signal);
+ 
+-		perform_link_training_with_retries(&link->cur_link_settings,
++		perform_link_training_with_retries(&previous_link_settings,
+ 			true, LINK_TRAINING_ATTEMPTS,
+ 			pipe_ctx,
+ 			pipe_ctx->stream->signal);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4694-drm-amd-display-Return-a-correct-error-value.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4694-drm-amd-display-Return-a-correct-error-value.patch
new file mode 100644
index 00000000..e024377a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4694-drm-amd-display-Return-a-correct-error-value.patch
@@ -0,0 +1,47 @@
+From 1fecf0d6ffc9c8935672cacb6f2ccbdbbea1afaa Mon Sep 17 00:00:00 2001
+From: Mikita Lipski <mikita.lipski@amd.com>
+Date: Tue, 12 Nov 2019 13:58:32 -0500
+Subject: [PATCH 4694/4736] drm/amd/display: Return a correct error value
+
+[why]
+The function is expected to return instance of the timing generator
+therefore we shouldn't be returning boolean in integer function,
+and we shouldn't be returning zero so changing it to -1.
+
+Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
+Reviewed-by: Martin Leung <Martin.Leung@amd.com>
+Acked-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+index fd9358c11222..d4273527a371 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+@@ -1870,7 +1870,7 @@ static int acquire_resource_from_hw_enabled_state(
+ 	inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
+ 
+ 	if (inst == ENGINE_ID_UNKNOWN)
+-		return false;
++		return -1;
+ 
+ 	for (i = 0; i < pool->stream_enc_count; i++) {
+ 		if (pool->stream_enc[i]->id == inst) {
+@@ -1882,10 +1882,10 @@ static int acquire_resource_from_hw_enabled_state(
+ 
+ 	// tg_inst not found
+ 	if (i == pool->stream_enc_count)
+-		return false;
++		return -1;
+ 
+ 	if (tg_inst >= pool->timing_generator_count)
+-		return false;
++		return -1;
+ 
+ 	if (!res_ctx->pipe_ctx[tg_inst].stream) {
+ 		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4695-drm-amd-display-Split-DMUB-cmd-type-into-type-subtyp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4695-drm-amd-display-Split-DMUB-cmd-type-into-type-subtyp.patch
new file mode 100644
index 00000000..6919ae0e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4695-drm-amd-display-Split-DMUB-cmd-type-into-type-subtyp.patch
@@ -0,0 +1,286 @@
+From 71f9dce3ab7c375280dbc36c00eb1787083b71ec Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 12 Nov 2019 15:33:37 -0500
+Subject: [PATCH 4695/4736] drm/amd/display: Split DMUB cmd type into
+ type/subtype
+
+[Why]
+Commands will be considered a stable ABI between driver and firmware.
+
+Commands are also split between DC commands, DAL feature commands,
+and VBIOS commands.
+
+Commands are currently not designated to a specific ID and the enum
+does not provide a stable ABI.
+
+We currently group all of these into a single command type of 8-bits.
+With the stable ABI consideration in mind it's not unreasonable to
+run out of command IDs.
+
+For cleaner separation and versioning split the commands into a main
+type and a subtype.
+
+[How]
+For commands where performance matters (like reg sequences) these
+are still considered main commands.
+
+Sub commands will be split by ownership/feature.
+
+Update existing command sequences to reflect new changes.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dc/bios/command_table2.c  | 13 +++--
+ drivers/gpu/drm/amd/display/dc/dc_helper.c    |  3 ++
+ .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 48 +++++++------------
+ .../drm/amd/display/dmub/inc/dmub_cmd_dal.h   | 41 ++++++++++++++++
+ .../drm/amd/display/dmub/inc/dmub_cmd_vbios.h | 41 ++++++++++++++++
+ 5 files changed, 112 insertions(+), 34 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_vbios.h
+
+diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+index 1836f16bb7fe..2cb7a4288cb7 100644
+--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
++++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+@@ -111,7 +111,8 @@ static void encoder_control_dmcub(
+ {
+ 	struct dmub_rb_cmd_digx_encoder_control encoder_control = { 0 };
+ 
+-	encoder_control.header.type = DMUB_CMD__DIGX_ENCODER_CONTROL;
++	encoder_control.header.type = DMUB_CMD__VBIOS;
++	encoder_control.header.sub_type = DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL;
+ 	encoder_control.encoder_control.dig.stream_param = *dig;
+ 
+ 	dc_dmub_srv_cmd_queue(dmcub, &encoder_control.header);
+@@ -219,7 +220,9 @@ static void transmitter_control_dmcub(
+ {
+ 	struct dmub_rb_cmd_dig1_transmitter_control transmitter_control;
+ 
+-	transmitter_control.header.type = DMUB_CMD__DIG1_TRANSMITTER_CONTROL;
++	transmitter_control.header.type = DMUB_CMD__VBIOS;
++	transmitter_control.header.sub_type =
++		DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL;
+ 	transmitter_control.transmitter_control.dig = *dig;
+ 
+ 	dc_dmub_srv_cmd_queue(dmcub, &transmitter_control.header);
+@@ -302,7 +305,8 @@ static void set_pixel_clock_dmcub(
+ {
+ 	struct dmub_rb_cmd_set_pixel_clock pixel_clock = { 0 };
+ 
+-	pixel_clock.header.type     = DMUB_CMD__SET_PIXEL_CLOCK;
++	pixel_clock.header.type = DMUB_CMD__VBIOS;
++	pixel_clock.header.sub_type = DMUB_CMD__VBIOS_SET_PIXEL_CLOCK;
+ 	pixel_clock.pixel_clock.clk = *clk;
+ 
+ 	dc_dmub_srv_cmd_queue(dmcub, &pixel_clock.header);
+@@ -650,7 +654,8 @@ static void enable_disp_power_gating_dmcub(
+ {
+ 	struct dmub_rb_cmd_enable_disp_power_gating power_gating;
+ 
+-	power_gating.header.type      = DMUB_CMD__ENABLE_DISP_POWER_GATING;
++	power_gating.header.type = DMUB_CMD__VBIOS;
++	power_gating.header.sub_type = DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING;
+ 	power_gating.power_gating.pwr = *pwr;
+ 
+ 	dc_dmub_srv_cmd_queue(dmcub, &power_gating.header);
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
+index acdedd889716..5f59aeeac231 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
++++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
+@@ -175,6 +175,7 @@ static bool dmub_reg_value_burst_set_pack(const struct dc_context *ctx, uint32_t
+ 	}
+ 
+ 	cmd_buf->header.type = DMUB_CMD__REG_SEQ_BURST_WRITE;
++	cmd_buf->header.sub_type = 0;
+ 	cmd_buf->addr = addr;
+ 	cmd_buf->write_values[offload->reg_seq_count] = reg_val;
+ 	offload->reg_seq_count++;
+@@ -203,6 +204,7 @@ static uint32_t dmub_reg_value_pack(const struct dc_context *ctx, uint32_t addr,
+ 
+ 	/* pack commands */
+ 	cmd_buf->header.type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE;
++	cmd_buf->header.sub_type = 0;
+ 	seq = &cmd_buf->seq[offload->reg_seq_count];
+ 
+ 	if (offload->reg_seq_count) {
+@@ -227,6 +229,7 @@ static void dmub_reg_wait_done_pack(const struct dc_context *ctx, uint32_t addr,
+ 	struct dmub_rb_cmd_reg_wait *cmd_buf = &offload->cmd_data.reg_wait;
+ 
+ 	cmd_buf->header.type = DMUB_CMD__REG_REG_WAIT;
++	cmd_buf->header.sub_type = 0;
+ 	cmd_buf->reg_wait.addr = addr;
+ 	cmd_buf->reg_wait.condition_field_value = mask & (condition_value << shift);
+ 	cmd_buf->reg_wait.mask = mask;
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+index 43f1cd647aab..b10728f33f62 100644
+--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+@@ -27,6 +27,8 @@
+ #define _DMUB_CMD_H_
+ 
+ #include "dmub_types.h"
++#include "dmub_cmd_dal.h"
++#include "dmub_cmd_vbios.h"
+ #include "atomfirmware.h"
+ 
+ #define DMUB_RB_CMD_SIZE 64
+@@ -34,43 +36,29 @@
+ #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
+ #define REG_SET_MASK 0xFFFF
+ 
++/*
++ * Command IDs should be treated as stable ABI.
++ * Do not reuse or modify IDs.
++ */
++
+ enum dmub_cmd_type {
+-	DMUB_CMD__NULL,
+-	DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE,
+-	DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ,
+-	DMUB_CMD__REG_SEQ_BURST_WRITE,
+-	DMUB_CMD__REG_REG_WAIT,
+-	DMUB_CMD__DIGX_ENCODER_CONTROL,
+-	DMUB_CMD__SET_PIXEL_CLOCK,
+-	DMUB_CMD__ENABLE_DISP_POWER_GATING,
+-	DMUB_CMD__DPPHY_INIT,
+-	DMUB_CMD__DIG1_TRANSMITTER_CONTROL,
+-	DMUB_CMD__SETUP_DISPLAY_MODE,
+-	DMUB_CMD__BLANK_CRTC,
+-	DMUB_CMD__ENABLE_DISPPATH,
+-	DMUB_CMD__DISABLE_DISPPATH,
+-	DMUB_CMD__DISABLE_DISPPATH_OUTPUT,
+-	DMUB_CMD__READ_DISPPATH_EDID,
+-	DMUB_CMD__DP_PRE_LINKTRAINING,
+-	DMUB_CMD__INIT_CONTROLLER,
+-	DMUB_CMD__RESET_CONTROLLER,
+-	DMUB_CMD__SET_BRI_LEVEL,
+-	DMUB_CMD__LVTMA_CONTROL,
+-
+-	// PSR
+-	DMUB_CMD__PSR_ENABLE,
+-	DMUB_CMD__PSR_DISABLE,
+-	DMUB_CMD__PSR_COPY_SETTINGS,
+-	DMUB_CMD__PSR_SET_LEVEL,
++	DMUB_CMD__NULL = 0,
++	DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
++	DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
++	DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
++	DMUB_CMD__REG_REG_WAIT = 4,
++	DMUB_CMD__PSR = 64,
++	DMUB_CMD__VBIOS = 128,
+ };
+ 
+ #pragma pack(push, 1)
+ 
+ struct dmub_cmd_header {
+-	enum dmub_cmd_type type : 8;
+-	unsigned int reserved0 : 16;
++	unsigned int type : 8;
++	unsigned int sub_type : 8;
++	unsigned int reserved0 : 8;
+ 	unsigned int payload_bytes : 6;  /* up to 60 bytes */
+-	unsigned int reserved : 2;
++	unsigned int reserved1 : 2;
+ };
+ 
+ /*
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h
+new file mode 100644
+index 000000000000..14f13e8a6f3b
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_dal.h
+@@ -0,0 +1,41 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_CMD_DAL_H_
++#define _DMUB_CMD_DAL_H_
++
++/*
++ * Command IDs should be treated as stable ABI.
++ * Do not reuse or modify IDs.
++ */
++
++enum dmub_cmd_psr_type {
++	DMUB_CMD__PSR_ENABLE = 0,
++	DMUB_CMD__PSR_DISABLE = 1,
++	DMUB_CMD__PSR_COPY_SETTINGS = 2,
++	DMUB_CMD__PSR_SET_LEVEL = 3,
++};
++
++#endif /* _DMUB_CMD_DAL_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_vbios.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_vbios.h
+new file mode 100644
+index 000000000000..b6deb8e2590f
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd_vbios.h
+@@ -0,0 +1,41 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_CMD_VBIOS_H_
++#define _DMUB_CMD_VBIOS_H_
++
++/*
++ * Command IDs should be treated as stable ABI.
++ * Do not reuse or modify IDs.
++ */
++
++enum dmub_cmd_vbios_type {
++	DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
++	DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
++	DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
++	DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
++};
++
++#endif /* _DMUB_CMD_VBIOS_H_ */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4696-drm-amd-display-Add-shared-DMCUB-driver-firmware-sta.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4696-drm-amd-display-Add-shared-DMCUB-driver-firmware-sta.patch
new file mode 100644
index 00000000..358f5acc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4696-drm-amd-display-Add-shared-DMCUB-driver-firmware-sta.patch
@@ -0,0 +1,333 @@
+From 740f33a5fe33c62249db788bd90ce46dcbe72499 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Tue, 12 Nov 2019 13:46:34 -0500
+Subject: [PATCH 4696/4736] drm/amd/display: Add shared DMCUB/driver firmware
+ state cache window
+
+[Why]
+Scratch registers are limited on the DMCUB and we have an expanding
+list of state to track between driver and DMCUB.
+
+[How]
+Place shared state in cache window 6. The cache window size is aligned
+to the size of the cache line on the DMCUB to make it easy to
+invalidate.
+
+The shared state is intended to be read only from driver side so
+it's been marked as const.
+
+The use of volatile is intentional. The memory for the shared firmware
+state is memory mapped from the framebuffer memory. The DMCUB will
+flush its cache after modifying the region. There's no way for x86
+to known whether this data is stale or not so we want to intentionally
+disable optimization to force the read at every access.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../drm/amd/display/dmub/inc/dmub_fw_state.h  | 73 +++++++++++++++++++
+ .../gpu/drm/amd/display/dmub/inc/dmub_srv.h   |  8 +-
+ .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 10 ++-
+ .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h |  3 +-
+ .../gpu/drm/amd/display/dmub/src/dmub_dcn21.c | 12 ++-
+ .../gpu/drm/amd/display/dmub/src/dmub_dcn21.h |  3 +-
+ .../gpu/drm/amd/display/dmub/src/dmub_srv.c   | 27 +++++--
+ 7 files changed, 125 insertions(+), 11 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_state.h
+
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_state.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_state.h
+new file mode 100644
+index 000000000000..c87b1ba7590e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_state.h
+@@ -0,0 +1,73 @@
++/*
++ * Copyright 2019 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors: AMD
++ *
++ */
++
++#ifndef _DMUB_FW_STATE_H_
++#define _DMUB_FW_STATE_H_
++
++#include "dmub_types.h"
++
++#pragma pack(push, 1)
++
++struct dmub_fw_state {
++	/**
++	 * @phy_initialized_during_fw_boot:
++	 *
++	 * Detects if VBIOS/VBL has ran before firmware boot.
++	 * A value of 1 will usually mean S0i3 boot.
++	 */
++	uint8_t phy_initialized_during_fw_boot;
++
++	/**
++	 * @intialized_phy:
++	 *
++	 * Bit vector of initialized PHY.
++	 */
++	uint8_t initialized_phy;
++
++	/**
++	 * @enabled_phy:
++	 *
++	 * Bit vector of enabled PHY for DP alt mode switch tracking.
++	 */
++	uint8_t enabled_phy;
++
++	/**
++	 * @dmcu_fw_loaded:
++	 *
++	 * DMCU auto load state.
++	 */
++	uint8_t dmcu_fw_loaded;
++
++	/**
++	 * @psr_state:
++	 *
++	 * PSR state tracking.
++	 */
++	uint8_t psr_state;
++};
++
++#pragma pack(pop)
++
++#endif /* _DMUB_FW_STATE_H_ */
+diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+index 046885940dba..d678b6f0313f 100644
+--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
++++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+@@ -67,6 +67,7 @@
+ #include "dmub_types.h"
+ #include "dmub_cmd.h"
+ #include "dmub_rb.h"
++#include "dmub_fw_state.h"
+ 
+ #if defined(__cplusplus)
+ extern "C" {
+@@ -102,7 +103,7 @@ enum dmub_window_id {
+ 	DMUB_WINDOW_3_VBIOS,
+ 	DMUB_WINDOW_4_MAILBOX,
+ 	DMUB_WINDOW_5_TRACEBUFF,
+-	DMUB_WINDOW_6_RESERVED,
++	DMUB_WINDOW_6_FW_STATE,
+ 	DMUB_WINDOW_7_RESERVED,
+ 	DMUB_WINDOW_TOTAL,
+ };
+@@ -241,7 +242,8 @@ struct dmub_srv_hw_funcs {
+ 			      const struct dmub_window *cw2,
+ 			      const struct dmub_window *cw3,
+ 			      const struct dmub_window *cw4,
+-				  const struct dmub_window *cw5);
++			      const struct dmub_window *cw5,
++			      const struct dmub_window *cw6);
+ 
+ 	void (*setup_mailbox)(struct dmub_srv *dmub,
+ 			      const struct dmub_region *inbox1);
+@@ -296,11 +298,13 @@ struct dmub_srv_hw_params {
+  * @asic: dmub asic identifier
+  * @user_ctx: user provided context for the dmub_srv
+  * @is_virtual: false if hardware support only
++ * @fw_state: dmub firmware state pointer
+  */
+ struct dmub_srv {
+ 	enum dmub_asic asic;
+ 	void *user_ctx;
+ 	bool is_virtual;
++	volatile const struct dmub_fw_state *fw_state;
+ 
+ 	/* private: internal use only */
+ 	struct dmub_srv_base_funcs funcs;
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+index 302dd3d4b77d..951ea7053c7e 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+@@ -76,7 +76,8 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
+ 			      const struct dmub_window *cw2,
+ 			      const struct dmub_window *cw3,
+ 			      const struct dmub_window *cw4,
+-				  const struct dmub_window *cw5)
++			      const struct dmub_window *cw5,
++			      const struct dmub_window *cw6)
+ {
+ 	REG_WRITE(DMCUB_REGION3_CW2_OFFSET, cw2->offset.u.low_part);
+ 	REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, cw2->offset.u.high_part);
+@@ -106,6 +107,13 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
+ 	REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
+ 		  DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
+ 		  DMCUB_REGION3_CW5_ENABLE, 1);
++
++	REG_WRITE(DMCUB_REGION3_CW6_OFFSET, cw6->offset.u.low_part);
++	REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, cw6->offset.u.high_part);
++	REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
++	REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
++		  DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
++		  DMCUB_REGION3_CW6_ENABLE, 1);
+ }
+ 
+ void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+index ca7db03b94f7..e70a57573467 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+@@ -46,7 +46,8 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
+ 			      const struct dmub_window *cw2,
+ 			      const struct dmub_window *cw3,
+ 			      const struct dmub_window *cw4,
+-				  const struct dmub_window *cw5);
++			      const struct dmub_window *cw5,
++			      const struct dmub_window *cw6);
+ 
+ void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
+ 			      const struct dmub_region *inbox1);
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
+index b9dc2dd645eb..9cea7a2d8dbf 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
+@@ -78,7 +78,8 @@ void dmub_dcn21_setup_windows(struct dmub_srv *dmub,
+ 			      const struct dmub_window *cw2,
+ 			      const struct dmub_window *cw3,
+ 			      const struct dmub_window *cw4,
+-				  const struct dmub_window *cw5)
++			      const struct dmub_window *cw5,
++			      const struct dmub_window *cw6)
+ {
+ 	union dmub_addr offset;
+ 	uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
+@@ -118,6 +119,15 @@ void dmub_dcn21_setup_windows(struct dmub_srv *dmub,
+ 	REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
+ 		  DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
+ 		  DMCUB_REGION3_CW5_ENABLE, 1);
++
++	dmub_dcn21_translate_addr(&cw6->offset, fb_base, fb_offset, &offset);
++
++	REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
++	REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
++	REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
++	REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
++		  DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
++		  DMCUB_REGION3_CW6_ENABLE, 1);
+ }
+ 
+ bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub)
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
+index 9e5f195e288f..f7a93a5dcfa5 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
+@@ -38,7 +38,8 @@ void dmub_dcn21_setup_windows(struct dmub_srv *dmub,
+ 			      const struct dmub_window *cw2,
+ 			      const struct dmub_window *cw3,
+ 			      const struct dmub_window *cw4,
+-				  const struct dmub_window *cw5);
++			      const struct dmub_window *cw5,
++			      const struct dmub_window *cw6);
+ 
+ bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub);
+ 
+diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+index 70c7a4be9ccc..5f39166d3c08 100644
+--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+@@ -48,13 +48,14 @@
+ 
+ 
+ /* Number of windows in use. */
+-#define DMUB_NUM_WINDOWS (DMUB_WINDOW_5_TRACEBUFF + 1)
++#define DMUB_NUM_WINDOWS (DMUB_WINDOW_6_FW_STATE + 1)
+ /* Base addresses. */
+ 
+ #define DMUB_CW0_BASE (0x60000000)
+ #define DMUB_CW1_BASE (0x61000000)
+ #define DMUB_CW3_BASE (0x63000000)
+ #define DMUB_CW5_BASE (0x65000000)
++#define DMUB_CW6_BASE (0x66000000)
+ 
+ static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
+ {
+@@ -158,6 +159,7 @@ dmub_srv_calc_region_info(struct dmub_srv *dmub,
+ 	struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS];
+ 	struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX];
+ 	struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF];
++	struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE];
+ 
+ 	if (!dmub->sw_init)
+ 		return DMUB_STATUS_INVALID;
+@@ -184,7 +186,13 @@ dmub_srv_calc_region_info(struct dmub_srv *dmub,
+ 	trace_buff->base = dmub_align(mail->top, 256);
+ 	trace_buff->top = trace_buff->base + TRACE_BUF_SIZE;
+ 
+-	out->fb_size = dmub_align(trace_buff->top, 4096);
++	fw_state->base = dmub_align(trace_buff->top, 256);
++
++	/* Align firmware state to size of cache line. */
++	fw_state->top =
++		fw_state->base + dmub_align(sizeof(struct dmub_fw_state), 64);
++
++	out->fb_size = dmub_align(fw_state->top, 4096);
+ 
+ 	return DMUB_STATUS_OK;
+ }
+@@ -258,9 +266,10 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
+ 	struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS];
+ 	struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX];
+ 	struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF];
++	struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE];
+ 
+ 	struct dmub_rb_init_params rb_params;
+-	struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5;
++	struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6;
+ 	struct dmub_region inbox1;
+ 
+ 	if (!dmub->sw_init)
+@@ -286,7 +295,8 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
+ 	if (dmub->hw_funcs.reset)
+ 		dmub->hw_funcs.reset(dmub);
+ 
+-	if (inst_fb && data_fb && bios_fb && mail_fb) {
++	if (inst_fb && data_fb && bios_fb && mail_fb && tracebuff_fb &&
++	    fw_state_fb) {
+ 		cw2.offset.quad_part = data_fb->gpu_addr;
+ 		cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
+ 		cw2.region.top = cw2.region.base + data_fb->size;
+@@ -306,8 +316,15 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
+ 		cw5.region.base = DMUB_CW5_BASE;
+ 		cw5.region.top = cw5.region.base + tracebuff_fb->size;
+ 
++		cw6.offset.quad_part = fw_state_fb->gpu_addr;
++		cw6.region.base = DMUB_CW6_BASE;
++		cw6.region.top = cw6.region.base + fw_state_fb->size;
++
++		dmub->fw_state = fw_state_fb->cpu_addr;
++
+ 		if (dmub->hw_funcs.setup_windows)
+-			dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5);
++			dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4,
++						     &cw5, &cw6);
+ 
+ 		if (dmub->hw_funcs.setup_mailbox)
+ 			dmub->hw_funcs.setup_mailbox(dmub, &inbox1);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4697-drm-amd-display-update-sr-latency-for-renoir-when-us.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4697-drm-amd-display-update-sr-latency-for-renoir-when-us.patch
new file mode 100644
index 00000000..6f15b44f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4697-drm-amd-display-update-sr-latency-for-renoir-when-us.patch
@@ -0,0 +1,68 @@
+From ef14a8387788a849b24a54f954dbc14a807f10d4 Mon Sep 17 00:00:00 2001
+From: Joseph Gravenor <joseph.gravenor@amd.com>
+Date: Tue, 12 Nov 2019 17:48:36 -0500
+Subject: [PATCH 4697/4736] drm/amd/display: update sr latency for renoir when
+ using lpddr4
+
+[Why]
+DF team has produced more optimized sr latency numbers, for lpddr4
+
+[How]
+change the sr laency in the lpddr4 wm table to the new latency
+number
+
+Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c    | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 901e7035bf8e..37230d3d94a0 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -563,32 +563,32 @@ struct wm_table lpddr4_wm_table = {
+ 			.wm_inst = WM_A,
+ 			.wm_type = WM_TYPE_PSTATE_CHG,
+ 			.pstate_latency_us = 11.65333,
+-			.sr_exit_time_us = 12.5,
+-			.sr_enter_plus_exit_time_us = 17.0,
++			.sr_exit_time_us = 5.32,
++			.sr_enter_plus_exit_time_us = 6.38,
+ 			.valid = true,
+ 		},
+ 		{
+ 			.wm_inst = WM_B,
+ 			.wm_type = WM_TYPE_PSTATE_CHG,
+ 			.pstate_latency_us = 11.65333,
+-			.sr_exit_time_us = 12.5,
+-			.sr_enter_plus_exit_time_us = 17.0,
++			.sr_exit_time_us = 9.82,
++			.sr_enter_plus_exit_time_us = 11.196,
+ 			.valid = true,
+ 		},
+ 		{
+ 			.wm_inst = WM_C,
+ 			.wm_type = WM_TYPE_PSTATE_CHG,
+ 			.pstate_latency_us = 11.65333,
+-			.sr_exit_time_us = 12.5,
+-			.sr_enter_plus_exit_time_us = 17.0,
++			.sr_exit_time_us = 9.89,
++			.sr_enter_plus_exit_time_us = 11.24,
+ 			.valid = true,
+ 		},
+ 		{
+ 			.wm_inst = WM_D,
+ 			.wm_type = WM_TYPE_PSTATE_CHG,
+ 			.pstate_latency_us = 11.65333,
+-			.sr_exit_time_us = 12.5,
+-			.sr_enter_plus_exit_time_us = 17.0,
++			.sr_exit_time_us = 9.748,
++			.sr_enter_plus_exit_time_us = 11.102,
+ 			.valid = true,
+ 		},
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4698-drm-amd-display-Remove-flag-check-in-mpcc-update.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4698-drm-amd-display-Remove-flag-check-in-mpcc-update.patch
new file mode 100644
index 00000000..4683a59d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4698-drm-amd-display-Remove-flag-check-in-mpcc-update.patch
@@ -0,0 +1,43 @@
+From 231d52771b240b2224e4f1c2198f7870dfc4844e Mon Sep 17 00:00:00 2001
+From: Noah Abradjian <noah.abradjian@amd.com>
+Date: Wed, 13 Nov 2019 13:55:53 -0500
+Subject: [PATCH 4698/4736] drm/amd/display: Remove flag check in mpcc update
+
+[Why]
+MPCC programming was being missed during certain split pipe enables due
+to full_update flag not being true. This caused a momentary flash on
+half the screen. After discussion, determined we should not have that
+flag check within update_mpcc, as it should always perform full
+programming when called.
+
+[How]
+Remove flag check. We call update_blending within insert_plane, so we
+do not need to replace its call from the if block.
+
+Signed-off-by: Noah Abradjian <noah.abradjian@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 3e016a57f1ac..53b719c75071 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -2162,12 +2162,6 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+ 	 */
+ 	mpcc_id = hubp->inst;
+ 
+-	/* If there is no full update, don't need to touch MPC tree*/
+-	if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
+-		mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
+-		return;
+-	}
+-
+ 	/* check if this MPCC is already being used */
+ 	new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
+ 	/* remove MPCC if being used */
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4699-drm-amd-display-check-for-repeater-when-setting-aux_.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4699-drm-amd-display-check-for-repeater-when-setting-aux_.patch
new file mode 100644
index 00000000..911c1ae4
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4699-drm-amd-display-check-for-repeater-when-setting-aux_.patch
@@ -0,0 +1,43 @@
+From 7f899298da256db5ad49f3183e4a771eddc75344 Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Tue, 12 Nov 2019 11:07:24 -0500
+Subject: [PATCH 4699/4736] drm/amd/display: check for repeater when setting
+ aux_rd_interval.
+
+[Why]
+When training with repeater the aux read interval must be set to
+repeater specific aux_red_interval. This value is always 100us for CR.
+
+[How]
+Check for repeater when setting the aux_rd_interval in channel
+equalization.
+Use the right offset in the aux_rd_interval array
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Acked-by: George Shen <George.Shen@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index 015fa0c52746..dfcd6421ee01 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -906,10 +906,10 @@ static enum link_training_result perform_channel_equalization_sequence(
+ 		/* 3. wait for receiver to lock-on*/
+ 		wait_time_microsec = lt_settings->eq_pattern_time;
+ 
+-		if (!link->is_lttpr_mode_transparent)
++		if (is_repeater(link, offset))
+ 			wait_time_microsec =
+ 					translate_training_aux_read_interval(
+-						link->dpcd_caps.lttpr_caps.aux_rd_interval[offset]);
++						link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
+ 
+ 		wait_for_training_aux_rd_interval(
+ 				link,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4700-drm-amd-display-Modify-logic-for-when-to-wait-for-mp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4700-drm-amd-display-Modify-logic-for-when-to-wait-for-mp.patch
new file mode 100644
index 00000000..7e61a4b0
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4700-drm-amd-display-Modify-logic-for-when-to-wait-for-mp.patch
@@ -0,0 +1,54 @@
+From 1cfb31a1c8f703da4269ad762e6c42961149f361 Mon Sep 17 00:00:00 2001
+From: Noah Abradjian <noah.abradjian@amd.com>
+Date: Wed, 13 Nov 2019 16:56:06 -0500
+Subject: [PATCH 4700/4736] drm/amd/display: Modify logic for when to wait for
+ mpcc idle
+
+[Why]
+I was advised that we may need to check for mpcc idle in more cases
+than just when opp_changed is true. Also, mpcc_inst is equal to
+pipe_idx, so remove for loop.
+
+[How]
+Remove opp_changed flag check and mpcc_inst loop.
+
+Signed-off-by: Noah Abradjian <noah.abradjian@amd.com>
+Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 53b719c75071..036a43717a47 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -1353,16 +1353,16 @@ static void dcn20_update_dchubp_dpp(
+ 	if (pipe_ctx->update_flags.bits.mpcc
+ 			|| plane_state->update_flags.bits.global_alpha_change
+ 			|| plane_state->update_flags.bits.per_pixel_alpha_change) {
+-		/* Need mpcc to be idle if changing opp */
+-		if (pipe_ctx->update_flags.bits.opp_changed) {
+-			struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
+-			int mpcc_inst;
+-
+-			for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
+-				if (!old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst])
+-					continue;
++		// MPCC inst is equal to pipe index in practice
++		int mpcc_inst = pipe_ctx->pipe_idx;
++		int opp_inst;
++		int opp_count = dc->res_pool->res_cap->num_opp;
++
++		for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
++			if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
+ 				dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
+-				old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
++				dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
++				break;
+ 			}
+ 		}
+ 		hws->funcs.update_mpcc(dc, pipe_ctx);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4701-drm-amd-display-Remove-redundant-call.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4701-drm-amd-display-Remove-redundant-call.patch
new file mode 100644
index 00000000..d4239504
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4701-drm-amd-display-Remove-redundant-call.patch
@@ -0,0 +1,38 @@
+From b16e3871c5e322e23ec7ef4a669eea2ed83acb4d Mon Sep 17 00:00:00 2001
+From: Noah Abradjian <noah.abradjian@amd.com>
+Date: Wed, 13 Nov 2019 17:06:40 -0500
+Subject: [PATCH 4701/4736] drm/amd/display: Remove redundant call
+
+[Why]
+I was advised that we don't need this call of program_front_end, as
+earlier and later calls in the same sequence are sufficient.
+
+[How]
+Remove first call of program_front_end in dc_commit_state_no_check.
+
+Change-Id: I4a552fdd06c05a4c0ffa243c59f99b45c06a1fdd
+Signed-off-by: Noah Abradjian <noah.abradjian@amd.com>
+Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 97da6384348a..0c75ee6bbdf2 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -1178,10 +1178,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ 				context->stream_status[i].plane_count,
+ 				context); /* use new pipe config in new context */
+ 		}
+-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+-	if (dc->hwss.program_front_end_for_ctx)
+-		dc->hwss.program_front_end_for_ctx(dc, context);
+-#endif
+ 
+ 	/* Program hardware */
+ 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4702-drm-amd-display-add-dc-dsc-functions-to-return-bpp-r.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4702-drm-amd-display-add-dc-dsc-functions-to-return-bpp-r.patch
new file mode 100644
index 00000000..79ccc215
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4702-drm-amd-display-add-dc-dsc-functions-to-return-bpp-r.patch
@@ -0,0 +1,135 @@
+From ac462cfeea247e416a918528d11b62e6beb60e4a Mon Sep 17 00:00:00 2001
+From: Wenjing Liu <Wenjing.Liu@amd.com>
+Date: Wed, 13 Nov 2019 17:03:37 -0500
+Subject: [PATCH 4702/4736] drm/amd/display: add dc dsc functions to return bpp
+ range for pixel encoding
+
+[why]
+Need to support 6 bpp for 420 pixel encoding only.
+
+[how]
+Add a dc function to determine what bpp range can be supported
+for given pixel encoding.
+
+Change-Id: I438dd2e234457ab28fefd249a0f9ed17ef0dbae5
+Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc_dsc.h     |  8 +++--
+ drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 40 +++++++++++++++++----
+ 2 files changed, 39 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+index cc9915e545cd..d98b89bad353 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+@@ -52,8 +52,8 @@ bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_basic_data,
+ bool dc_dsc_compute_bandwidth_range(
+ 		const struct display_stream_compressor *dsc,
+ 		const uint32_t dsc_min_slice_height_override,
+-		const uint32_t min_kbps,
+-		const uint32_t max_kbps,
++		const uint32_t min_bpp,
++		const uint32_t max_bpp,
+ 		const struct dsc_dec_dpcd_caps *dsc_sink_caps,
+ 		const struct dc_crtc_timing *timing,
+ 		struct dc_dsc_bw_range *range);
+@@ -65,4 +65,8 @@ bool dc_dsc_compute_config(
+ 		uint32_t target_bandwidth_kbps,
+ 		const struct dc_crtc_timing *timing,
+ 		struct dc_dsc_config *dsc_cfg);
++
++bool dc_dsc_get_bpp_range_for_pixel_encoding(enum dc_pixel_encoding pixel_enc,
++		uint32_t *min_bpp,
++		uint32_t *max_bpp);
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+index ec86ba73a039..f2b724d7e372 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+@@ -31,16 +31,12 @@ struct dc_dsc_policy {
+ 	bool use_min_slices_h;
+ 	int max_slices_h; // Maximum available if 0
+ 	int min_sice_height; // Must not be less than 8
+-	int max_target_bpp;
+-	int min_target_bpp; // Minimum target bits per pixel
+ };
+ 
+ const struct dc_dsc_policy dsc_policy = {
+ 	.use_min_slices_h = true, // DSC Policy: Use minimum number of slices that fits the pixel clock
+ 	.max_slices_h = 0, // DSC Policy: Use max available slices (in our case 4 for or 8, depending on the mode)
+ 	.min_sice_height = 108, // DSC Policy: Use slice height recommended by VESA DSC Spreadsheet user guide
+-	.max_target_bpp = 16,
+-	.min_target_bpp = 8,
+ };
+ 
+ 
+@@ -374,7 +370,6 @@ static void get_dsc_bandwidth_range(
+  *        or if it couldn't be applied based on DSC policy.
+  */
+ static bool decide_dsc_target_bpp_x16(
+-		const struct dc_dsc_policy *policy,
+ 		const struct dsc_enc_caps *dsc_common_caps,
+ 		const int target_bandwidth_kbps,
+ 		const struct dc_crtc_timing *timing,
+@@ -382,10 +377,13 @@ static bool decide_dsc_target_bpp_x16(
+ {
+ 	bool should_use_dsc = false;
+ 	struct dc_dsc_bw_range range;
++	uint32_t min_target_bpp = 0;
++	uint32_t max_target_bpp = 0;
+ 
+ 	memset(&range, 0, sizeof(range));
+ 
+-	get_dsc_bandwidth_range(policy->min_target_bpp, policy->max_target_bpp,
++	dc_dsc_get_bpp_range_for_pixel_encoding(timing->pixel_encoding, &min_target_bpp, &max_target_bpp);
++	get_dsc_bandwidth_range(min_target_bpp, max_target_bpp,
+ 			dsc_common_caps, timing, &range);
+ 	if (target_bandwidth_kbps >= range.stream_kbps) {
+ 		/* enough bandwidth without dsc */
+@@ -599,7 +597,7 @@ static bool setup_dsc_config(
+ 		goto done;
+ 
+ 	if (target_bandwidth_kbps > 0) {
+-		is_dsc_possible = decide_dsc_target_bpp_x16(&dsc_policy, &dsc_common_caps, target_bandwidth_kbps, timing, &target_bpp);
++		is_dsc_possible = decide_dsc_target_bpp_x16(&dsc_common_caps, target_bandwidth_kbps, timing, &target_bpp);
+ 		dsc_cfg->bits_per_pixel = target_bpp;
+ 	}
+ 	if (!is_dsc_possible)
+@@ -906,3 +904,31 @@ bool dc_dsc_compute_config(
+ 			timing, dsc_min_slice_height_override, dsc_cfg);
+ 	return is_dsc_possible;
+ }
++
++
++bool dc_dsc_get_bpp_range_for_pixel_encoding(enum dc_pixel_encoding pixel_enc,
++		uint32_t *min_bpp,
++		uint32_t *max_bpp)
++{
++	bool result = true;
++
++	switch (pixel_enc) {
++	case PIXEL_ENCODING_RGB:
++	case PIXEL_ENCODING_YCBCR444:
++	case PIXEL_ENCODING_YCBCR422:
++		*min_bpp = 8;
++		*max_bpp = 16;
++		break;
++	case PIXEL_ENCODING_YCBCR420:
++		*min_bpp = 6;
++		*max_bpp = 16;
++		break;
++	default:
++		*min_bpp = 0;
++		*max_bpp = 0;
++		result = false;
++	}
++
++	return result;
++}
++
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4703-drm-amd-display-remove-spam-DSC-log.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4703-drm-amd-display-remove-spam-DSC-log.patch
new file mode 100644
index 00000000..15331837
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4703-drm-amd-display-remove-spam-DSC-log.patch
@@ -0,0 +1,36 @@
+From 06eba75bcead2659aa35a315723b1df23d978b2f Mon Sep 17 00:00:00 2001
+From: Wenjing Liu <Wenjing.Liu@amd.com>
+Date: Wed, 13 Nov 2019 15:59:51 -0500
+Subject: [PATCH 4703/4736] drm/amd/display: remove spam DSC log
+
+[why]
+add_dsc_to_stream_resource could be called for validation.
+Failing validation is completely fine.
+However failing it inside commit streams is bad.
+This code could be triggered for both contexts.
+The function itself cannot distinguish the caller, which
+makes it impossible to output the log only in the
+meaningful case (commit streams).
+
+Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 2e03ff357746..5c00223b279e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -1582,7 +1582,6 @@ static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
+ 
+ 		/* The number of DSCs can be less than the number of pipes */
+ 		if (!pipe_ctx->stream_res.dsc) {
+-			dm_output_to_console("No DSCs available\n");
+ 			result = DC_NO_DSC_RESOURCE;
+ 		}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4704-drm-amd-display-add-dsc-policy-getter.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4704-drm-amd-display-add-dsc-policy-getter.patch
new file mode 100644
index 00000000..5f335a3e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4704-drm-amd-display-add-dsc-policy-getter.patch
@@ -0,0 +1,235 @@
+From 564a7172d20f0f68566d58fd9278058ca1e93291 Mon Sep 17 00:00:00 2001
+From: Wenjing Liu <Wenjing.Liu@amd.com>
+Date: Fri, 15 Nov 2019 11:24:54 -0500
+Subject: [PATCH 4704/4736] drm/amd/display: add dsc policy getter
+
+dc needs to expose its internal dsc policy.
+
+Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
+Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc_dsc.h     |  14 ++-
+ drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 103 ++++++++++++--------
+ 2 files changed, 75 insertions(+), 42 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+index d98b89bad353..8ec09813ee17 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+@@ -45,6 +45,14 @@ struct display_stream_compressor {
+ 	int inst;
+ };
+ 
++struct dc_dsc_policy {
++	bool use_min_slices_h;
++	int max_slices_h; // Maximum available if 0
++	int min_slice_height; // Must not be less than 8
++	uint32_t max_target_bpp;
++	uint32_t min_target_bpp;
++};
++
+ bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_basic_data,
+ 		const uint8_t *dpcd_dsc_ext_data,
+ 		struct dsc_dec_dpcd_caps *dsc_sink_caps);
+@@ -66,7 +74,7 @@ bool dc_dsc_compute_config(
+ 		const struct dc_crtc_timing *timing,
+ 		struct dc_dsc_config *dsc_cfg);
+ 
+-bool dc_dsc_get_bpp_range_for_pixel_encoding(enum dc_pixel_encoding pixel_enc,
+-		uint32_t *min_bpp,
+-		uint32_t *max_bpp);
++void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
++		struct dc_dsc_policy *policy);
++
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+index f2b724d7e372..7469315144c1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
++++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+@@ -27,19 +27,6 @@
+ #include <drm/drm_dp_helper.h>
+ #include "dc.h"
+ 
+-struct dc_dsc_policy {
+-	bool use_min_slices_h;
+-	int max_slices_h; // Maximum available if 0
+-	int min_sice_height; // Must not be less than 8
+-};
+-
+-const struct dc_dsc_policy dsc_policy = {
+-	.use_min_slices_h = true, // DSC Policy: Use minimum number of slices that fits the pixel clock
+-	.max_slices_h = 0, // DSC Policy: Use max available slices (in our case 4 for or 8, depending on the mode)
+-	.min_sice_height = 108, // DSC Policy: Use slice height recommended by VESA DSC Spreadsheet user guide
+-};
+-
+-
+ /* This module's internal functions */
+ 
+ static uint32_t dc_dsc_bandwidth_in_kbps_from_timing(
+@@ -370,6 +357,7 @@ static void get_dsc_bandwidth_range(
+  *        or if it couldn't be applied based on DSC policy.
+  */
+ static bool decide_dsc_target_bpp_x16(
++		const struct dc_dsc_policy *policy,
+ 		const struct dsc_enc_caps *dsc_common_caps,
+ 		const int target_bandwidth_kbps,
+ 		const struct dc_crtc_timing *timing,
+@@ -377,13 +365,10 @@ static bool decide_dsc_target_bpp_x16(
+ {
+ 	bool should_use_dsc = false;
+ 	struct dc_dsc_bw_range range;
+-	uint32_t min_target_bpp = 0;
+-	uint32_t max_target_bpp = 0;
+ 
+ 	memset(&range, 0, sizeof(range));
+ 
+-	dc_dsc_get_bpp_range_for_pixel_encoding(timing->pixel_encoding, &min_target_bpp, &max_target_bpp);
+-	get_dsc_bandwidth_range(min_target_bpp, max_target_bpp,
++	get_dsc_bandwidth_range(policy->min_target_bpp, policy->max_target_bpp,
+ 			dsc_common_caps, timing, &range);
+ 	if (target_bandwidth_kbps >= range.stream_kbps) {
+ 		/* enough bandwidth without dsc */
+@@ -579,9 +564,11 @@ static bool setup_dsc_config(
+ 	bool is_dsc_possible = false;
+ 	int pic_height;
+ 	int slice_height;
++	struct dc_dsc_policy policy;
+ 
+ 	memset(dsc_cfg, 0, sizeof(struct dc_dsc_config));
+ 
++	dc_dsc_get_policy_for_timing(timing, &policy);
+ 	pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right;
+ 	pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
+ 
+@@ -597,7 +584,12 @@ static bool setup_dsc_config(
+ 		goto done;
+ 
+ 	if (target_bandwidth_kbps > 0) {
+-		is_dsc_possible = decide_dsc_target_bpp_x16(&dsc_common_caps, target_bandwidth_kbps, timing, &target_bpp);
++		is_dsc_possible = decide_dsc_target_bpp_x16(
++				&policy,
++				&dsc_common_caps,
++				target_bandwidth_kbps,
++				timing,
++				&target_bpp);
+ 		dsc_cfg->bits_per_pixel = target_bpp;
+ 	}
+ 	if (!is_dsc_possible)
+@@ -699,20 +691,20 @@ static bool setup_dsc_config(
+ 	if (!is_dsc_possible)
+ 		goto done;
+ 
+-	if (dsc_policy.use_min_slices_h) {
++	if (policy.use_min_slices_h) {
+ 		if (min_slices_h > 0)
+ 			num_slices_h = min_slices_h;
+ 		else if (max_slices_h > 0) { // Fall back to max slices if min slices is not working out
+-			if (dsc_policy.max_slices_h)
+-				num_slices_h = min(dsc_policy.max_slices_h, max_slices_h);
++			if (policy.max_slices_h)
++				num_slices_h = min(policy.max_slices_h, max_slices_h);
+ 			else
+ 				num_slices_h = max_slices_h;
+ 		} else
+ 			is_dsc_possible = false;
+ 	} else {
+ 		if (max_slices_h > 0) {
+-			if (dsc_policy.max_slices_h)
+-				num_slices_h = min(dsc_policy.max_slices_h, max_slices_h);
++			if (policy.max_slices_h)
++				num_slices_h = min(policy.max_slices_h, max_slices_h);
+ 			else
+ 				num_slices_h = max_slices_h;
+ 		} else if (min_slices_h > 0) // Fall back to min slices if max slices is not possible
+@@ -734,7 +726,7 @@ static bool setup_dsc_config(
+ 	// Slice height (i.e. number of slices per column): start with policy and pick the first one that height is divisible by.
+ 	// For 4:2:0 make sure the slice height is divisible by 2 as well.
+ 	if (min_slice_height_override == 0)
+-		slice_height = min(dsc_policy.min_sice_height, pic_height);
++		slice_height = min(policy.min_slice_height, pic_height);
+ 	else
+ 		slice_height = min(min_slice_height_override, pic_height);
+ 
+@@ -906,29 +898,62 @@ bool dc_dsc_compute_config(
+ }
+ 
+ 
+-bool dc_dsc_get_bpp_range_for_pixel_encoding(enum dc_pixel_encoding pixel_enc,
+-		uint32_t *min_bpp,
+-		uint32_t *max_bpp)
++void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, struct dc_dsc_policy *policy)
+ {
+-	bool result = true;
++	uint32_t bpc = 0;
++
++	policy->min_target_bpp = 0;
++	policy->max_target_bpp = 0;
++
++	/* DSC Policy: Use minimum number of slices that fits the pixel clock */
++	policy->use_min_slices_h = true;
+ 
+-	switch (pixel_enc) {
++	/* DSC Policy: Use max available slices
++	 * (in our case 4 for or 8, depending on the mode)
++	 */
++	policy->max_slices_h = 0;
++
++	/* DSC Policy: Use slice height recommended
++	 * by VESA DSC Spreadsheet user guide
++	 */
++	policy->min_slice_height = 108;
++
++	/* DSC Policy: follow DP specs with an internal upper limit to 16 bpp
++	 * for better interoperability
++	 */
++	switch (timing->display_color_depth) {
++	case COLOR_DEPTH_888:
++		bpc = 8;
++		break;
++	case COLOR_DEPTH_101010:
++		bpc = 10;
++		break;
++	case COLOR_DEPTH_121212:
++		bpc = 12;
++		break;
++	default:
++		return;
++	}
++	switch (timing->pixel_encoding) {
+ 	case PIXEL_ENCODING_RGB:
+ 	case PIXEL_ENCODING_YCBCR444:
+-	case PIXEL_ENCODING_YCBCR422:
+-		*min_bpp = 8;
+-		*max_bpp = 16;
++	case PIXEL_ENCODING_YCBCR422: /* assume no YCbCr422 native support */
++		/* DP specs limits to 8 */
++		policy->min_target_bpp = 8;
++		/* DP specs limits to 3 x bpc */
++		policy->max_target_bpp = 3 * bpc;
+ 		break;
+ 	case PIXEL_ENCODING_YCBCR420:
+-		*min_bpp = 6;
+-		*max_bpp = 16;
++		/* DP specs limits to 6 */
++		policy->min_target_bpp = 6;
++		/* DP specs limits to 1.5 x bpc assume bpc is an even number */
++		policy->max_target_bpp = bpc * 3 / 2;
+ 		break;
+ 	default:
+-		*min_bpp = 0;
+-		*max_bpp = 0;
+-		result = false;
++		return;
+ 	}
+-
+-	return result;
++	/* internal upper limit to 16 bpp */
++	if (policy->max_target_bpp > 16)
++		policy->max_target_bpp = 16;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4705-drm-amd-display-fix-cursor-positioning-for-multiplan.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4705-drm-amd-display-fix-cursor-positioning-for-multiplan.patch
new file mode 100644
index 00000000..bc9d5d05
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4705-drm-amd-display-fix-cursor-positioning-for-multiplan.patch
@@ -0,0 +1,67 @@
+From 460d5ac8ad145c412be735e1593b57eaa4098b19 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Sat, 9 Nov 2019 18:30:40 -0500
+Subject: [PATCH 4705/4736] drm/amd/display: fix cursor positioning for
+ multiplane cases
+
+[Why]
+Cursor position needs to take into account plane scaling as well.
+
+[How]
+Translate cursor coords from stream space to plane space.
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+---
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 33 ++++++++++++++-----
+ 1 file changed, 24 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 0e1e3dcf4112..c085a561b24c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2917,15 +2917,30 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
+ 		.rotation = pipe_ctx->plane_state->rotation,
+ 		.mirror = pipe_ctx->plane_state->horizontal_mirror
+ 	};
+-	uint32_t x_plane = pipe_ctx->plane_state->dst_rect.x;
+-	uint32_t y_plane = pipe_ctx->plane_state->dst_rect.y;
+-	uint32_t x_offset = min(x_plane, pos_cpy.x);
+-	uint32_t y_offset = min(y_plane, pos_cpy.y);
+-
+-	pos_cpy.x -= x_offset;
+-	pos_cpy.y -= y_offset;
+-	pos_cpy.x_hotspot += (x_plane - x_offset);
+-	pos_cpy.y_hotspot += (y_plane - y_offset);
++
++	int x_plane = pipe_ctx->plane_state->dst_rect.x;
++	int y_plane = pipe_ctx->plane_state->dst_rect.y;
++	int x_pos = pos_cpy.x;
++	int y_pos = pos_cpy.y;
++
++	// translate cursor from stream space to plane space
++	x_pos = (x_pos - x_plane) * pipe_ctx->plane_state->src_rect.width /
++			pipe_ctx->plane_state->dst_rect.width;
++	y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.height /
++			pipe_ctx->plane_state->dst_rect.height;
++
++	if (x_pos < 0) {
++		pos_cpy.x_hotspot -= x_pos;
++		x_pos = 0;
++	}
++
++	if (y_pos < 0) {
++		pos_cpy.y_hotspot -= y_pos;
++		y_pos = 0;
++	}
++
++	pos_cpy.x = (uint32_t)x_pos;
++	pos_cpy.y = (uint32_t)y_pos;
+ 
+ 	if (pipe_ctx->plane_state->address.type
+ 			== PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4706-drm-amd-display-Fix-screen-tearing-on-vrr-tests.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4706-drm-amd-display-Fix-screen-tearing-on-vrr-tests.patch
new file mode 100644
index 00000000..6cf94fae
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4706-drm-amd-display-Fix-screen-tearing-on-vrr-tests.patch
@@ -0,0 +1,122 @@
+From 55df5456b6e72138acecde21cccf513b9315655d Mon Sep 17 00:00:00 2001
+From: Amanda Liu <amanda.liu@amd.com>
+Date: Fri, 15 Nov 2019 17:07:27 -0500
+Subject: [PATCH 4706/4736] drm/amd/display: Fix screen tearing on vrr tests
+
+[Why]
+Screen tearing is present in tests when setting the frame rate to
+certain fps
+
+[How]
+Revert previous optimizations for low frame rates.
+
+Signed-off-by: Amanda Liu <amanda.liu@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/modules/freesync/freesync.c   | 32 ++++++++-----------
+ .../amd/display/modules/inc/mod_freesync.h    |  1 -
+ 2 files changed, 13 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+index 52c8edbde2c4..40ffed098e79 100644
+--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
++++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+@@ -35,8 +35,8 @@
+ #define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65)
+ /* Number of elements in the render times cache array */
+ #define RENDER_TIMES_MAX_COUNT 10
+-/* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */
+-#define BTR_MAX_MARGIN 2500
++/* Threshold to exit BTR (to avoid frequent enter-exits at the lower limit) */
++#define BTR_EXIT_MARGIN 2000
+ /* Threshold to change BTR multiplier (to avoid frequent changes) */
+ #define BTR_DRIFT_MARGIN 2000
+ /*Threshold to exit fixed refresh rate*/
+@@ -252,22 +252,24 @@ static void apply_below_the_range(struct core_freesync *core_freesync,
+ 	unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF;
+ 	unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF;
+ 	unsigned int frames_to_insert = 0;
++	unsigned int min_frame_duration_in_ns = 0;
++	unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us;
+ 	unsigned int delta_from_mid_point_delta_in_us;
+-	unsigned int max_render_time_in_us =
+-			in_out_vrr->max_duration_in_us - in_out_vrr->btr.margin_in_us;
++
++	min_frame_duration_in_ns = ((unsigned int) (div64_u64(
++		(1000000000ULL * 1000000),
++		in_out_vrr->max_refresh_in_uhz)));
+ 
+ 	/* Program BTR */
+-	if ((last_render_time_in_us + in_out_vrr->btr.margin_in_us / 2) < max_render_time_in_us) {
++	if (last_render_time_in_us + BTR_EXIT_MARGIN < max_render_time_in_us) {
+ 		/* Exit Below the Range */
+ 		if (in_out_vrr->btr.btr_active) {
+ 			in_out_vrr->btr.frame_counter = 0;
+ 			in_out_vrr->btr.btr_active = false;
+ 		}
+-	} else if (last_render_time_in_us > (max_render_time_in_us + in_out_vrr->btr.margin_in_us / 2)) {
++	} else if (last_render_time_in_us > max_render_time_in_us) {
+ 		/* Enter Below the Range */
+-		if (!in_out_vrr->btr.btr_active) {
+-			in_out_vrr->btr.btr_active = true;
+-		}
++		in_out_vrr->btr.btr_active = true;
+ 	}
+ 
+ 	/* BTR set to "not active" so disengage */
+@@ -323,9 +325,7 @@ static void apply_below_the_range(struct core_freesync *core_freesync,
+ 		/* Choose number of frames to insert based on how close it
+ 		 * can get to the mid point of the variable range.
+ 		 */
+-		if ((frame_time_in_us / mid_point_frames_ceil) > in_out_vrr->min_duration_in_us &&
+-				(delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2 ||
+-						mid_point_frames_floor < 2)) {
++		if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
+ 			frames_to_insert = mid_point_frames_ceil;
+ 			delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_2 -
+ 					delta_from_mid_point_in_us_1;
+@@ -341,7 +341,7 @@ static void apply_below_the_range(struct core_freesync *core_freesync,
+ 		if (in_out_vrr->btr.frames_to_insert != 0 &&
+ 				delta_from_mid_point_delta_in_us < BTR_DRIFT_MARGIN) {
+ 			if (((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) <
+-					max_render_time_in_us) &&
++					in_out_vrr->max_duration_in_us) &&
+ 				((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) >
+ 					in_out_vrr->min_duration_in_us))
+ 				frames_to_insert = in_out_vrr->btr.frames_to_insert;
+@@ -794,11 +794,6 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
+ 		refresh_range = in_out_vrr->max_refresh_in_uhz -
+ 				in_out_vrr->min_refresh_in_uhz;
+ 
+-		in_out_vrr->btr.margin_in_us = in_out_vrr->max_duration_in_us -
+-				2 * in_out_vrr->min_duration_in_us;
+-		if (in_out_vrr->btr.margin_in_us > BTR_MAX_MARGIN)
+-			in_out_vrr->btr.margin_in_us = BTR_MAX_MARGIN;
+-
+ 		in_out_vrr->supported = true;
+ 	}
+ 
+@@ -814,7 +809,6 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
+ 	in_out_vrr->btr.inserted_duration_in_us = 0;
+ 	in_out_vrr->btr.frames_to_insert = 0;
+ 	in_out_vrr->btr.frame_counter = 0;
+-
+ 	in_out_vrr->btr.mid_point_in_us =
+ 				(in_out_vrr->min_duration_in_us +
+ 				 in_out_vrr->max_duration_in_us) / 2;
+diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+index dbe7835aabcf..dc187844d10b 100644
+--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
++++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+@@ -92,7 +92,6 @@ struct mod_vrr_params_btr {
+ 	uint32_t inserted_duration_in_us;
+ 	uint32_t frames_to_insert;
+ 	uint32_t frame_counter;
+-	uint32_t margin_in_us;
+ };
+ 
+ struct mod_vrr_params_fixed_refresh {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4707-drm-amd-display-update-dispclk-and-dppclk-vco-freque.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4707-drm-amd-display-update-dispclk-and-dppclk-vco-freque.patch
new file mode 100644
index 00000000..f8c681de
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4707-drm-amd-display-update-dispclk-and-dppclk-vco-freque.patch
@@ -0,0 +1,33 @@
+From 40c811e3469cfcdf491ec358906752e99f71b56c Mon Sep 17 00:00:00 2001
+From: Eric Yang <Eric.Yang2@amd.com>
+Date: Fri, 15 Nov 2019 12:04:25 -0500
+Subject: [PATCH 4707/4736] drm/amd/display: update dispclk and dppclk vco
+ frequency
+
+Value obtained from DV is not allowing 8k60 CTA mode with DSC to
+pass, after checking real value being used in hw, find out that
+correct value is 3600, which will allow that mode.
+
+Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 23727c3f2e01..dd66be12321a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -255,7 +255,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
+ 	.vmm_page_size_bytes = 4096,
+ 	.dram_clock_change_latency_us = 23.84,
+ 	.return_bus_width_bytes = 64,
+-	.dispclk_dppclk_vco_speed_mhz = 3550,
++	.dispclk_dppclk_vco_speed_mhz = 3600,
+ 	.xfc_bus_transport_time_us = 4,
+ 	.xfc_xbuf_latency_tolerance_us = 4,
+ 	.use_urgent_burst_bw = 1,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4708-drm-amd-display-Implement-DePQ-for-DCN2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4708-drm-amd-display-Implement-DePQ-for-DCN2.patch
new file mode 100644
index 00000000..859472a6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4708-drm-amd-display-Implement-DePQ-for-DCN2.patch
@@ -0,0 +1,53 @@
+From f86e6c9ce2835a5764e92b6a71e875937d773c6f Mon Sep 17 00:00:00 2001
+From: Reza Amini <Reza.Amini@amd.com>
+Date: Fri, 15 Nov 2019 17:39:12 -0500
+Subject: [PATCH 4708/4736] drm/amd/display: Implement DePQ for DCN2
+
+[Why]
+Need support for more color management in 10bit
+surface.
+
+[How]
+Provide support for DePQ for 10bit surface
+
+Signed-off-by: Reza Amini <Reza.Amini@amd.com>
+Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c | 3 +++
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c  | 5 +++++
+ 2 files changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
+index 2d112c316424..05a3e7f97ef0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
+@@ -149,6 +149,9 @@ void dpp2_set_degamma(
+ 	case IPP_DEGAMMA_MODE_HW_xvYCC:
+ 		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);
+ 			break;
++	case IPP_DEGAMMA_MODE_USER_PWL:
++		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3);
++		break;
+ 	default:
+ 		BREAK_TO_DEBUGGER();
+ 		break;
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+index 036a43717a47..8b04c18057d3 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+@@ -882,6 +882,11 @@ bool dcn20_set_input_transfer_func(struct dc *dc,
+ 					IPP_DEGAMMA_MODE_BYPASS);
+ 			break;
+ 		case TRANSFER_FUNCTION_PQ:
++			dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
++			cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
++			dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
++			result = true;
++			break;
+ 		default:
+ 			result = false;
+ 			break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4709-drm-amd-display-3.2.62.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4709-drm-amd-display-3.2.62.patch
new file mode 100644
index 00000000..9e853c54
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4709-drm-amd-display-3.2.62.patch
@@ -0,0 +1,28 @@
+From 56b1d473452a38d614af51fc1831a18c42b88e26 Mon Sep 17 00:00:00 2001
+From: Aric Cyr <aric.cyr@amd.com>
+Date: Mon, 18 Nov 2019 08:33:34 -0500
+Subject: [PATCH 4709/4736] drm/amd/display: 3.2.62
+
+Signed-off-by: Aric Cyr <aric.cyr@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
+index f4884548e77e..f71f1e5734d8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dc.h
++++ b/drivers/gpu/drm/amd/display/dc/dc.h
+@@ -39,7 +39,7 @@
+ #include "inc/hw/dmcu.h"
+ #include "dml/display_mode_lib.h"
+ 
+-#define DC_VER "3.2.61"
++#define DC_VER "3.2.62"
+ 
+ #define MAX_SURFACES 3
+ #define MAX_PLANES 6
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4710-drm-amd-display-Change-HDR_MULT-check.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4710-drm-amd-display-Change-HDR_MULT-check.patch
new file mode 100644
index 00000000..9d9cfc50
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4710-drm-amd-display-Change-HDR_MULT-check.patch
@@ -0,0 +1,47 @@
+From d0bde5aa157cf73ba730a8c950acbeface6e6318 Mon Sep 17 00:00:00 2001
+From: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Date: Fri, 15 Nov 2019 10:00:46 -0500
+Subject: [PATCH 4710/4736] drm/amd/display: Change HDR_MULT check
+
+[Why]
+Currently we require HDR_MULT >= 1.0
+There are scenarios where we need < 1.0
+
+[How]
+Only guard against 0 - it will black-screen image.
+It is up to higher-level logic to decide what HDR_MULT
+values are allowed in each particular case.
+
+Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 +-----
+ 1 file changed, 1 insertion(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index c085a561b24c..35599d4ba6f6 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2392,17 +2392,13 @@ void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
+ 	struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult;
+ 	uint32_t hw_mult = 0x1f000; // 1.0 default multiplier
+ 	struct custom_float_format fmt;
+-	bool mult_negative; // True if fixed31_32 sign bit indicates negative value
+-	uint32_t mult_int; // int component of fixed31_32
+ 
+ 	fmt.exponenta_bits = 6;
+ 	fmt.mantissa_bits = 12;
+ 	fmt.sign = true;
+ 
+-	mult_negative = multiplier.value >> 63 != 0;
+-	mult_int = multiplier.value >> 32;
+ 
+-	if (mult_int && !mult_negative) // Check if greater than 1
++	if (!dc_fixpt_eq(multiplier, dc_fixpt_from_int(0))) // check != 0
+ 		convert_to_custom_float_format(multiplier, &fmt, &hw_mult);
+ 
+ 	pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4711-drm-amd-display-Increase-the-number-of-retries-after.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4711-drm-amd-display-Increase-the-number-of-retries-after.patch
new file mode 100644
index 00000000..baa1bce5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4711-drm-amd-display-Increase-the-number-of-retries-after.patch
@@ -0,0 +1,84 @@
+From 84f4c6b08f0e37320574201bfa16302a000cecdc Mon Sep 17 00:00:00 2001
+From: George Shen <george.shen@amd.com>
+Date: Fri, 15 Nov 2019 18:56:57 -0500
+Subject: [PATCH 4711/4736] drm/amd/display: Increase the number of retries
+ after AUX DEFER
+
+[Why]
+When a timeout occurs after a DEFER, some devices require more retries
+than in the case of a regular timeout.
+
+[How]
+In a timeout occurrence, check whether a DEFER has occurred before the
+timeout and retry MAX_DEFER_RETRIES retries times instead of
+MAX_TIMEOUT_RETRIES.
+
+Signed-off-by: George Shen <george.shen@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 32 ++++++++++++++------
+ 1 file changed, 22 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+index 0b9d8c5b9323..5bf6068da717 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+@@ -608,6 +608,8 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
+ 	uint8_t reply;
+ 	bool payload_reply = true;
+ 	enum aux_channel_operation_result operation_result;
++	bool retry_on_defer = false;
++
+ 	int aux_ack_retries = 0,
+ 		aux_defer_retries = 0,
+ 		aux_i2c_defer_retries = 0,
+@@ -638,8 +640,9 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
+ 			break;
+ 
+ 			case AUX_TRANSACTION_REPLY_AUX_DEFER:
+-			case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
+ 			case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
++				retry_on_defer = true;
++			case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
+ 				if (++aux_defer_retries >= AUX_MAX_DEFER_RETRIES) {
+ 					goto fail;
+ 				} else {
+@@ -672,15 +675,24 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
+ 			break;
+ 
+ 		case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
+-			if (++aux_timeout_retries >= AUX_MAX_TIMEOUT_RETRIES)
+-				goto fail;
+-			else {
+-				/*
+-				 * DP 1.4, 2.8.2:  AUX Transaction Response/Reply Timeouts
+-				 * According to the DP spec there should be 3 retries total
+-				 * with a 400us wait inbetween each. Hardware already waits
+-				 * for 550us therefore no wait is required here.
+-				 */
++			// Check whether a DEFER had occurred before the timeout.
++			// If so, treat timeout as a DEFER.
++			if (retry_on_defer) {
++				if (++aux_defer_retries >= AUX_MAX_DEFER_RETRIES)
++					goto fail;
++				else if (payload->defer_delay > 0)
++					msleep(payload->defer_delay);
++			} else {
++				if (++aux_timeout_retries >= AUX_MAX_TIMEOUT_RETRIES)
++					goto fail;
++				else {
++					/*
++					 * DP 1.4, 2.8.2:  AUX Transaction Response/Reply Timeouts
++					 * According to the DP spec there should be 3 retries total
++					 * with a 400us wait inbetween each. Hardware already waits
++					 * for 550us therefore no wait is required here.
++					 */
++				}
+ 			}
+ 			break;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4712-drm-amd-display-Compare-clock-state-member-to-determ.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4712-drm-amd-display-Compare-clock-state-member-to-determ.patch
new file mode 100644
index 00000000..2530ccef
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4712-drm-amd-display-Compare-clock-state-member-to-determ.patch
@@ -0,0 +1,58 @@
+From 2796f186fe4fe681f0ed1e70941a9c461a5896bb Mon Sep 17 00:00:00 2001
+From: Yongqiang Sun <yongqiang.sun@amd.com>
+Date: Mon, 18 Nov 2019 13:45:50 -0500
+Subject: [PATCH 4712/4736] drm/amd/display: Compare clock state member to
+ determine optimization.
+
+[Why]
+It seems always request passive flip on RN due to incorrect compare
+clock state to determine optization.
+
+[How]
+Instead of calling memcmp, compare clock state member to determine the
+condition.
+
+Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c  | 18 +++++++++++++++++-
+ 1 file changed, 17 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+index 37230d3d94a0..de51ef12e33a 100644
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+@@ -471,12 +471,28 @@ static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
+ 
+ }
+ 
++static bool rn_are_clock_states_equal(struct dc_clocks *a,
++		struct dc_clocks *b)
++{
++	if (a->dispclk_khz != b->dispclk_khz)
++		return false;
++	else if (a->dppclk_khz != b->dppclk_khz)
++		return false;
++	else if (a->dcfclk_khz != b->dcfclk_khz)
++		return false;
++	else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
++		return false;
++
++	return true;
++}
++
++
+ static struct clk_mgr_funcs dcn21_funcs = {
+ 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
+ 	.update_clocks = rn_update_clocks,
+ 	.init_clocks = rn_init_clocks,
+ 	.enable_pme_wa = rn_enable_pme_wa,
+-	/* .dump_clk_registers = rn_dump_clk_registers, */
++	.are_clock_states_equal = rn_are_clock_states_equal,
+ 	.notify_wm_ranges = rn_notify_wm_ranges
+ };
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4713-drm-amd-display-update-dml-related-structs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4713-drm-amd-display-update-dml-related-structs.patch
new file mode 100644
index 00000000..a895b8b5
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4713-drm-amd-display-update-dml-related-structs.patch
@@ -0,0 +1,80 @@
+From a071cf5aaedf11c10cee75867b8c72d869ed3323 Mon Sep 17 00:00:00 2001
+From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Date: Mon, 28 Oct 2019 15:42:29 -0400
+Subject: [PATCH 4713/4736] drm/amd/display: update dml related structs
+
+In preparation for further changes
+
+Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
+Reviewed-by: Chris Park <Chris.Park@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c     | 2 ++
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 3 +++
+ drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c     | 2 +-
+ 3 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index 5c00223b279e..51336b5c38ef 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -2033,6 +2033,7 @@ int dcn20_populate_dml_pipes_from_context(
+ 			pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
+ 			if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
+ 				pipes[pipe_cnt].pipe.src.viewport_height = 1080;
++			pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
+ 			pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
+ 			pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
+ 			pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
+@@ -2066,6 +2067,7 @@ int dcn20_populate_dml_pipes_from_context(
+ 			pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
+ 			pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
+ 			pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
++			pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
+ 			if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
+ 				pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
+ 				pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+index 516396d53d01..220d5e610f1f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+@@ -99,6 +99,7 @@ struct _vcs_dpi_soc_bounding_box_st {
+ 	unsigned int num_chans;
+ 	unsigned int vmm_page_size_bytes;
+ 	unsigned int hostvm_min_page_size_bytes;
++	unsigned int gpuvm_min_page_size_bytes;
+ 	double dram_clock_change_latency_us;
+ 	double dummy_pstate_latency_us;
+ 	double writeback_dram_clock_change_latency_us;
+@@ -224,6 +225,7 @@ struct _vcs_dpi_display_pipe_source_params_st {
+ 	int source_scan;
+ 	int sw_mode;
+ 	int macro_tile_size;
++	unsigned int surface_height_y;
+ 	unsigned int viewport_width;
+ 	unsigned int viewport_height;
+ 	unsigned int viewport_y_y;
+@@ -400,6 +402,7 @@ struct _vcs_dpi_display_rq_misc_params_st {
+ struct _vcs_dpi_display_rq_params_st {
+ 	unsigned char yuv420;
+ 	unsigned char yuv420_10bpc;
++	unsigned char rgbe_alpha;
+ 	display_rq_misc_params_st misc;
+ 	display_rq_sizing_params_st sizing;
+ 	display_rq_dlg_params_st dlg;
+diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+index b1c2b79e42b6..15b72a8b5174 100644
+--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+@@ -231,7 +231,7 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
+ 	mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading = soc->dcn_downspread_percent;   // new
+ 	mode_lib->vba.DISPCLKDPPCLKVCOSpeed = soc->dispclk_dppclk_vco_speed_mhz;   // new
+ 	mode_lib->vba.VMMPageSize = soc->vmm_page_size_bytes;
+-	mode_lib->vba.GPUVMMinPageSize = soc->vmm_page_size_bytes / 1024;
++	mode_lib->vba.GPUVMMinPageSize = soc->gpuvm_min_page_size_bytes / 1024;
+ 	mode_lib->vba.HostVMMinPageSize = soc->hostvm_min_page_size_bytes / 1024;
+ 	// Set the voltage scaling clocks as the defaults. Most of these will
+ 	// be set to different values by the test
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4714-drm-amd-display-correct-log-message-for-lttpr.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4714-drm-amd-display-correct-log-message-for-lttpr.patch
new file mode 100644
index 00000000..9c7f9b0a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4714-drm-amd-display-correct-log-message-for-lttpr.patch
@@ -0,0 +1,43 @@
+From 15578bf41c09dbff12183fe17d59459f40274040 Mon Sep 17 00:00:00 2001
+From: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Date: Mon, 18 Nov 2019 12:22:06 -0500
+Subject: [PATCH 4714/4736] drm/amd/display: correct log message for lttpr
+
+[Why]
+When setting lttpr mode, the new mode to bet is not logged properly.
+
+[How]
+Update log message to show the right mode.
+
+Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
+Reviewed-by: George Shen <George.Shen@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+index dfcd6421ee01..42aa889fd0f5 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+@@ -1219,7 +1219,7 @@ static void configure_lttpr_mode(struct dc_link *link)
+ 	uint8_t repeater_id;
+ 	uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
+ 
+-	DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
++	DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
+ 	core_link_write_dpcd(link,
+ 			DP_PHY_REPEATER_MODE,
+ 			(uint8_t *)&repeater_mode,
+@@ -1227,7 +1227,7 @@ static void configure_lttpr_mode(struct dc_link *link)
+ 
+ 	if (!link->is_lttpr_mode_transparent) {
+ 
+-		DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
++		DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
+ 
+ 		repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
+ 		core_link_write_dpcd(link,
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4715-drm-amd-display-Extend-DMCUB-offload-testing-into-dc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4715-drm-amd-display-Extend-DMCUB-offload-testing-into-dc.patch
new file mode 100644
index 00000000..4aed01d2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4715-drm-amd-display-Extend-DMCUB-offload-testing-into-dc.patch
@@ -0,0 +1,51 @@
+From d691a52f1ffe68a039c5f235860fef167ba339b8 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Mon, 18 Nov 2019 13:31:04 -0500
+Subject: [PATCH 4715/4736] drm/amd/display: Extend DMCUB offload testing into
+ dcn20/21
+
+[Why]
+To quickly validate whether DMCUB is running and accepting commands for
+offload testing we want to intercept a common sequence as part of
+modeset programming.
+
+[How]
+OTG enable will cause the most impact in terms of golden register
+changes and it's a single register write.
+
+This approach was previously done in dcn10 code when it was shared with
+dcn20 but it wasn't ported over to the dcn20 code.
+
+Port over start, execute and wait sequence into dcn20_optc.
+
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Leo Li <sunpeng.li@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+index f5854a5d2b76..673c83e2afd4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+@@ -59,11 +59,16 @@ bool optc2_enable_crtc(struct timing_generator *optc)
+ 	REG_UPDATE(CONTROL,
+ 			VTG0_ENABLE, 1);
+ 
++	REG_SEQ_START();
++
+ 	/* Enable CRTC */
+ 	REG_UPDATE_2(OTG_CONTROL,
+ 			OTG_DISABLE_POINT_CNTL, 3,
+ 			OTG_MASTER_EN, 1);
+ 
++	REG_SEQ_SUBMIT();
++	REG_SEQ_WAIT_DONE();
++
+ 	return true;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4716-drm-amdgpu-Fix-BACO-entry-failure-in-NAVI10.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4716-drm-amdgpu-Fix-BACO-entry-failure-in-NAVI10.patch
new file mode 100644
index 00000000..ea8a267e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4716-drm-amdgpu-Fix-BACO-entry-failure-in-NAVI10.patch
@@ -0,0 +1,31 @@
+From e16b88c7c8f840222dca7dfbf9bf6bb4f25505fc Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Thu, 5 Dec 2019 14:21:31 -0500
+Subject: [PATCH 4716/4736] drm/amdgpu: Fix BACO entry failure in NAVI10.
+
+BACO feature must be kept enabled to allow entry into
+BACO state in SMU during runtime suspend.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Tested-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+index 2dd960e85a24..4ed8bdc82fea 100644
+--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+@@ -1383,7 +1383,7 @@ static int smu_suspend(void *handle)
+ 	if (ret)
+ 		return ret;
+ 
+-	if (adev->in_gpu_reset && baco_feature_is_enabled) {
++	if (baco_feature_is_enabled) {
+ 		ret = smu_feature_set_enabled(smu, SMU_FEATURE_BACO_BIT, true);
+ 		if (ret) {
+ 			pr_warn("set BACO feature enabled failed, return %d\n", ret);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4717-drm-amd-powerplay-drop-unnecessary-warning-prompt.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4717-drm-amd-powerplay-drop-unnecessary-warning-prompt.patch
new file mode 100644
index 00000000..81355fd2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4717-drm-amd-powerplay-drop-unnecessary-warning-prompt.patch
@@ -0,0 +1,34 @@
+From 50044c3bd38a50919359d7ed31b2a9eec299170c Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Tue, 26 Nov 2019 15:05:07 +0800
+Subject: [PATCH 4717/4736] drm/amd/powerplay: drop unnecessary warning prompt
+
+As the check may be done with purpose and the warning
+output will be confusing.
+
+Change-Id: Ie0928c324a8161d44068f8ce648d56f6d9e8cd3d
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+index 3a793c6ccbf0..42a7478964eb 100644
+--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+@@ -280,10 +280,8 @@ static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER
+ 		return -EINVAL;
+ 
+ 	mapping = arcturus_workload_map[profile];
+-	if (!(mapping.valid_mapping)) {
+-		pr_warn("Unsupported SMU power source: %d\n", profile);
++	if (!(mapping.valid_mapping))
+ 		return -EINVAL;
+-	}
+ 
+ 	return mapping.map_to;
+ }
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4718-drm-amd-powerplay-pre-check-the-SMU-state-before-iss.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4718-drm-amd-powerplay-pre-check-the-SMU-state-before-iss.patch
new file mode 100644
index 00000000..c9ef1e20
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4718-drm-amd-powerplay-pre-check-the-SMU-state-before-iss.patch
@@ -0,0 +1,95 @@
+From cfa7c454a7f8b3e20067bf4b6e8084c40d5bab3c Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Wed, 4 Dec 2019 17:29:52 +0800
+Subject: [PATCH 4718/4736] drm/amd/powerplay: pre-check the SMU state before
+ issuing message
+
+Abort the message issuing if the SMU was not in the right state.
+
+Change-Id: Ida9f911e051f6e78de4f475956c78637e56e6ea3
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 16 ++++++++--------
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 16 ++++++++--------
+ 2 files changed, 16 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index 9e405a60ee6e..d65187993ef9 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -77,15 +77,13 @@ static int smu_v11_0_wait_for_response(struct smu_context *smu)
+ 	for (i = 0; i < timeout; i++) {
+ 		cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
+ 		if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
+-			break;
++			return cur_value == 0x1 ? 0 : -EIO;
++
+ 		udelay(1);
+ 	}
+ 
+ 	/* timeout means wrong logic */
+-	if (i == timeout)
+-		return -ETIME;
+-
+-	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
++	return -ETIME;
+ }
+ 
+ int
+@@ -101,9 +99,11 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu,
+ 		return index;
+ 
+ 	ret = smu_v11_0_wait_for_response(smu);
+-	if (ret)
+-		pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
+-		       smu_get_message_name(smu, msg), index, param, ret);
++	if (ret) {
++		pr_err("Msg issuing pre-check failed and "
++		       "SMU may be not in the right state!\n");
++		return ret;
++	}
+ 
+ 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 269a7d73b58d..951aa4570a04 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -66,15 +66,13 @@ int smu_v12_0_wait_for_response(struct smu_context *smu)
+ 	for (i = 0; i < adev->usec_timeout; i++) {
+ 		cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
+ 		if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
+-			break;
++			return cur_value == 0x1 ? 0 : -EIO;
++
+ 		udelay(1);
+ 	}
+ 
+ 	/* timeout means wrong logic */
+-	if (i == adev->usec_timeout)
+-		return -ETIME;
+-
+-	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
++	return -ETIME;
+ }
+ 
+ int
+@@ -90,9 +88,11 @@ smu_v12_0_send_msg_with_param(struct smu_context *smu,
+ 		return index;
+ 
+ 	ret = smu_v12_0_wait_for_response(smu);
+-	if (ret)
+-		pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
+-		       index, ret, param);
++	if (ret) {
++		pr_err("Msg issuing pre-check failed and "
++		       "SMU may be not in the right state!\n");
++		return ret;
++	}
+ 
+ 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4719-drm-amdgpu-fix-resume-failures-due-to-psp-fw-loading.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4719-drm-amdgpu-fix-resume-failures-due-to-psp-fw-loading.patch
new file mode 100644
index 00000000..6fb07e55
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4719-drm-amdgpu-fix-resume-failures-due-to-psp-fw-loading.patch
@@ -0,0 +1,68 @@
+From 167d845d08e4d436ea15f98bce4ccc24aecad582 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Fri, 6 Dec 2019 18:09:19 +0800
+Subject: [PATCH 4719/4736] drm/amdgpu: fix resume failures due to psp fw
+ loading sequence change (v3)
+
+this fix the regression caused by asd/ta loading sequence
+adjustment recently. asd/ta loading was move out from
+hw_start and should also be applied to psp_resume.
+otherwise those fw loading will be ignored in resume phase.
+
+v2: add the mutex unlock for asd loading failure case
+v3: merge the error handling to failed tag
+
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Guchun Chen <guchun.chen@amd.com>
+Reviewed-by: Le Ma <Le.Ma@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 33 +++++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 728f53ea2ad6..9b869fa9b594 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -1723,6 +1723,39 @@ static int psp_resume(void *handle)
+ 	if (ret)
+ 		goto failed;
+ 
++	ret = psp_asd_load(psp);
++	if (ret) {
++		DRM_ERROR("PSP load asd failed!\n");
++		goto failed;
++	}
++
++	if (adev->gmc.xgmi.num_physical_nodes > 1) {
++		ret = psp_xgmi_initialize(psp);
++		/* Warning the XGMI seesion initialize failure
++		 * Instead of stop driver initialization
++		 */
++		if (ret)
++			dev_err(psp->adev->dev,
++				"XGMI: Failed to initialize XGMI session\n");
++	}
++
++	if (psp->adev->psp.ta_fw) {
++		ret = psp_ras_initialize(psp);
++		if (ret)
++			dev_err(psp->adev->dev,
++					"RAS: Failed to initialize RAS\n");
++
++		ret = psp_hdcp_initialize(psp);
++		if (ret)
++			dev_err(psp->adev->dev,
++				"HDCP: Failed to initialize HDCP\n");
++
++		ret = psp_dtm_initialize(psp);
++		if (ret)
++			dev_err(psp->adev->dev,
++				"DTM: Failed to initialize DTM\n");
++	}
++
+ 	mutex_unlock(&adev->firmware.mutex);
+ 
+ 	return 0;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4720-drm-amdkfd-Improve-kfd_process-lookup-in-kfd_ioctl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4720-drm-amdkfd-Improve-kfd_process-lookup-in-kfd_ioctl.patch
new file mode 100644
index 00000000..03e077e6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4720-drm-amdkfd-Improve-kfd_process-lookup-in-kfd_ioctl.patch
@@ -0,0 +1,104 @@
+From 2ee4b662abfe96542dfd01f2013e4c509d579c57 Mon Sep 17 00:00:00 2001
+From: Felix Kuehling <Felix.Kuehling@amd.com>
+Date: Wed, 4 Dec 2019 21:23:08 -0500
+Subject: [PATCH 4720/4736] drm/amdkfd: Improve kfd_process lookup in kfd_ioctl
+
+Use filep->private_data to store a pointer to the kfd_process data
+structure. Take an extra reference for that, which gets released in
+the kfd_release callback. Check that the process calling kfd_ioctl
+is the same that opened the file descriptor. Return -EBADF if it's
+not, so that this error can be distinguished in user mode.
+
+Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Philip Yang <Philip.Yang@amd.com>
+---
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 30 ++++++++++++++++++++----
+ drivers/gpu/drm/amd/amdkfd/kfd_process.c |  2 ++
+ 2 files changed, 28 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+index d9cdb25974f9..1946ac4c95dd 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+@@ -50,6 +50,7 @@
+ 
+ static long kfd_ioctl(struct file *, unsigned int, unsigned long);
+ static int kfd_open(struct inode *, struct file *);
++static int kfd_release(struct inode *, struct file *);
+ static int kfd_mmap(struct file *, struct vm_area_struct *);
+ 
+ static const char kfd_dev_name[] = "kfd";
+@@ -59,6 +60,7 @@ static const struct file_operations kfd_fops = {
+ 	.unlocked_ioctl = kfd_ioctl,
+ 	.compat_ioctl = kfd_ioctl,
+ 	.open = kfd_open,
++	.release = kfd_release,
+ 	.mmap = kfd_mmap,
+ };
+ 
+@@ -142,8 +144,13 @@ static int kfd_open(struct inode *inode, struct file *filep)
+ 	if (IS_ERR(process))
+ 		return PTR_ERR(process);
+ 
+-	if (kfd_is_locked())
++	if (kfd_is_locked()) {
++		kfd_unref_process(process);
+ 		return -EAGAIN;
++	}
++
++	/* filep now owns the reference returned by kfd_create_process */
++	filep->private_data = process;
+ 
+ 	dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n",
+ 		process->pasid, process->is_32bit_user_mode);
+@@ -151,6 +158,16 @@ static int kfd_open(struct inode *inode, struct file *filep)
+ 	return 0;
+ }
+ 
++static int kfd_release(struct inode *inode, struct file *filep)
++{
++	struct kfd_process *process = filep->private_data;
++
++	if (process)
++		kfd_unref_process(process);
++
++	return 0;
++}
++
+ static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
+ 					void *data)
+ {
+@@ -2996,9 +3013,14 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
+ 
+ 	dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg);
+ 
+-	process = kfd_get_process(current);
+-	if (IS_ERR(process)) {
+-		dev_dbg(kfd_device, "no process\n");
++	/* Get the process struct from the filep. Only the process
++	 * that opened /dev/kfd can use the file descriptor. Child
++	 * processes need to create their own KFD device context.
++	 */
++	process = filep->private_data;
++	if (process->lead_thread != current->group_leader) {
++		dev_dbg(kfd_device, "Using KFD FD in wrong process\n");
++		retcode = -EBADF;
+ 		goto err_i1;
+ 	}
+ 
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+index d78c36ba54e3..ca7b80bd0114 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+@@ -328,6 +328,8 @@ struct kfd_process *kfd_create_process(struct file *filep)
+ 					(int)process->lead_thread->pid);
+ 	}
+ out:
++	if (!IS_ERR(process))
++		kref_get(&process->ref);
+ 	mutex_unlock(&kfd_processes_mutex);
+ 
+ 	return process;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4721-drm-amdgpu-display-add-fallthrough-comment.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4721-drm-amdgpu-display-add-fallthrough-comment.patch
new file mode 100644
index 00000000..3273b68f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4721-drm-amdgpu-display-add-fallthrough-comment.patch
@@ -0,0 +1,29 @@
+From 3e8aa1c890d1f39d366f5606b7051f4e9464dc67 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 5 Dec 2019 16:38:01 -0500
+Subject: [PATCH 4721/4736] drm/amdgpu/display: add fallthrough comment
+
+To avoid a compiler warning.
+
+Reviewed-by: Zhan Liu <zhan.liu@amd.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+index 5bf6068da717..282d7f4225d8 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+@@ -642,6 +642,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
+ 			case AUX_TRANSACTION_REPLY_AUX_DEFER:
+ 			case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
+ 				retry_on_defer = true;
++				/* fall through */
+ 			case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
+ 				if (++aux_defer_retries >= AUX_MAX_DEFER_RETRIES) {
+ 					goto fail;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4722-drm-amdgpu-move-VM-eviction-decision-into-amdgpu_vm..patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4722-drm-amdgpu-move-VM-eviction-decision-into-amdgpu_vm..patch
new file mode 100644
index 00000000..54f6b383
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4722-drm-amdgpu-move-VM-eviction-decision-into-amdgpu_vm..patch
@@ -0,0 +1,86 @@
+From b15d2a4a2436144a11919630bde2a8d37e2b9cb8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Thu, 28 Nov 2019 14:51:46 +0100
+Subject: [PATCH 4722/4736] drm/amdgpu: move VM eviction decision into
+ amdgpu_vm.c
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+When a page tables needs to be evicted the VM code should
+decide if that is possible or not.
+
+Change-Id: Ib9a934b37a39f06caeb15d7375fb1c4fc8f9b51c
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c |  5 +----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 22 ++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  1 +
+ 3 files changed, 24 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+index d93bfaca5daf..4e36ce46455f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+@@ -1624,11 +1624,8 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
+ 	struct dma_fence *f;
+ 	int i;
+ 
+-	/* Don't evict VM page tables while they are busy, otherwise we can't
+-	 * cleanly handle page faults.
+-	 */
+ 	if (bo->type == ttm_bo_type_kernel &&
+-	    !reservation_object_test_signaled_rcu(bo->resv, true))
++	    !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
+ 		return false;
+ 
+ 	/* If bo is a KFD BO, check if the bo belongs to the current process.
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 90ac5390ecdf..f47158087b83 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -2504,6 +2504,28 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
+ 	kfree(bo_va);
+ }
+ 
++/**
++ * amdgpu_vm_evictable - check if we can evict a VM
++ *
++ * @bo: A page table of the VM.
++ *
++ * Check if it is possible to evict a VM.
++ */
++bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
++{
++	struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
++
++	/* Page tables of a destroyed VM can go away immediately */
++	if (!bo_base || !bo_base->vm)
++		return true;
++
++	/* Don't evict VM page tables while they are busy */
++	if (!reservation_object_test_signaled_rcu(bo->tbo.resv, true))
++		return false;
++
++	return true;
++}
++
+ /**
+  * amdgpu_vm_bo_invalidate - mark the bo as invalid
+  *
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+index 76fcf853035c..db561765453b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+@@ -381,6 +381,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
+ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
+ 			struct amdgpu_bo_va *bo_va,
+ 			bool clear);
++bool amdgpu_vm_evictable(struct amdgpu_bo *bo);
+ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
+ 			     struct amdgpu_bo *bo, bool evicted);
+ uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4723-drm-amdgpu-explicitely-sync-to-VM-updates-v2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4723-drm-amdgpu-explicitely-sync-to-VM-updates-v2.patch
new file mode 100644
index 00000000..d97d306d
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4723-drm-amdgpu-explicitely-sync-to-VM-updates-v2.patch
@@ -0,0 +1,359 @@
+From df1e3b51e41af0ed53e425f748a2a63cefcfa62d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Fri, 29 Nov 2019 11:33:54 +0100
+Subject: [PATCH 4723/4736] drm/amdgpu: explicitely sync to VM updates v2
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Allows us to reduce the overhead while syncing to fences a bit.
+
+v2: also drop adev parameter from the functions
+
+Change-Id: I0828d0691fb87f0b9ae9205b15e18e6509c86d61
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Rahul Kumar <rahul.kumar1@amd.com>
+---
+ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |  8 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c        | 19 +++-------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c       | 13 +++----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_job.c       |  3 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c       |  2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c      | 38 ++++++++++++++-----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h      |  8 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c   |  2 +-
+ 8 files changed, 52 insertions(+), 41 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+index 3d7d6b5f423e..a21201e579b1 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+@@ -392,7 +392,7 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
+ 	if (ret)
+ 		return ret;
+ 
+-	return amdgpu_sync_fence(NULL, sync, vm->last_update, false);
++	return amdgpu_sync_fence(sync, vm->last_update, false);
+ }
+ 
+ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
+@@ -807,7 +807,7 @@ static int unmap_bo_from_gpuvm(struct amdgpu_device *adev,
+ 
+ 	amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
+ 
+-	amdgpu_sync_fence(NULL, sync, bo_va->last_pt_update, false);
++	amdgpu_sync_fence(sync, bo_va->last_pt_update, false);
+ 
+ 	return 0;
+ }
+@@ -826,7 +826,7 @@ static int update_gpuvm_pte(struct amdgpu_device *adev,
+ 		return ret;
+ 	}
+ 
+-	return amdgpu_sync_fence(NULL, sync, bo_va->last_pt_update, false);
++	return amdgpu_sync_fence(sync, bo_va->last_pt_update, false);
+ }
+ 
+ static int map_bo_to_gpuvm(struct amdgpu_device *adev,
+@@ -2337,7 +2337,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
+ 			pr_debug("Memory eviction: Validate BOs failed. Try again\n");
+ 			goto validate_map_fail;
+ 		}
+-		ret = amdgpu_sync_fence(NULL, &sync_obj, bo->tbo.moving, false);
++		ret = amdgpu_sync_fence(&sync_obj, bo->tbo.moving, false);
+ 		if (ret) {
+ 			pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
+ 			goto validate_map_fail;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+index e8dfbcfad034..2c570274b5a6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+@@ -790,29 +790,23 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
+ 	if (r)
+ 		return r;
+ 
+-	r = amdgpu_sync_fence(adev, &p->job->sync,
+-			      fpriv->prt_va->last_pt_update, false);
++	r = amdgpu_sync_vm_fence(&p->job->sync, fpriv->prt_va->last_pt_update);
+ 	if (r)
+ 		return r;
+ 
+ 	if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
+-		struct dma_fence *f;
+-
+ 		bo_va = fpriv->csa_va;
+ 		BUG_ON(!bo_va);
+ 		r = amdgpu_vm_bo_update(adev, bo_va, false);
+ 		if (r)
+ 			return r;
+ 
+-		f = bo_va->last_pt_update;
+-		r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
++		r = amdgpu_sync_vm_fence(&p->job->sync, bo_va->last_pt_update);
+ 		if (r)
+ 			return r;
+ 	}
+ 
+ 	amdgpu_bo_list_for_each_entry(e, p->bo_list) {
+-		struct dma_fence *f;
+-
+ 		/* ignore duplicates */
+ 		bo = ttm_to_amdgpu_bo(e->tv.bo);
+ 		if (!bo)
+@@ -826,8 +820,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
+ 		if (r)
+ 			return r;
+ 
+-		f = bo_va->last_pt_update;
+-		r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
++		r = amdgpu_sync_vm_fence(&p->job->sync, bo_va->last_pt_update);
+ 		if (r)
+ 			return r;
+ 	}
+@@ -840,7 +833,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
+ 	if (r)
+ 		return r;
+ 
+-	r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false);
++	r = amdgpu_sync_vm_fence(&p->job->sync, vm->last_update);
+ 	if (r)
+ 		return r;
+ 
+@@ -982,7 +975,7 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
+ 			dma_fence_put(old);
+ 		}
+ 
+-		r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
++		r = amdgpu_sync_fence(&p->job->sync, fence, true);
+ 		dma_fence_put(fence);
+ 		if (r)
+ 			return r;
+@@ -1003,7 +996,7 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
+ 
+ 		return r;
+ 	}
+-	r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
++	r = amdgpu_sync_fence(&p->job->sync, fence, true);
+ 	dma_fence_put(fence);
+ 
+ 	return r;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+index dfe155566571..dc2ea2b60ed8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+@@ -206,7 +206,7 @@ static int amdgpu_vmid_grab_idle(struct amdgpu_vm *vm,
+ 	int r;
+ 
+ 	if (ring->vmid_wait && !dma_fence_is_signaled(ring->vmid_wait))
+-		return amdgpu_sync_fence(adev, sync, ring->vmid_wait, false);
++		return amdgpu_sync_fence(sync, ring->vmid_wait, false);
+ 
+ 	fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL);
+ 	if (!fences)
+@@ -241,7 +241,7 @@ static int amdgpu_vmid_grab_idle(struct amdgpu_vm *vm,
+ 			return -ENOMEM;
+ 		}
+ 
+-		r = amdgpu_sync_fence(adev, sync, &array->base, false);
++		r = amdgpu_sync_fence(sync, &array->base, false);
+ 		dma_fence_put(ring->vmid_wait);
+ 		ring->vmid_wait = &array->base;
+ 		return r;
+@@ -294,7 +294,7 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,
+ 		tmp = amdgpu_sync_peek_fence(&(*id)->active, ring);
+ 		if (tmp) {
+ 			*id = NULL;
+-			r = amdgpu_sync_fence(adev, sync, tmp, false);
++			r = amdgpu_sync_fence(sync, tmp, false);
+ 			return r;
+ 		}
+ 		needs_flush = true;
+@@ -303,7 +303,7 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm,
+ 	/* Good we can use this VMID. Remember this submission as
+ 	* user of the VMID.
+ 	*/
+-	r = amdgpu_sync_fence(ring->adev, &(*id)->active, fence, false);
++	r = amdgpu_sync_fence(&(*id)->active, fence, false);
+ 	if (r)
+ 		return r;
+ 
+@@ -375,7 +375,7 @@ static int amdgpu_vmid_grab_used(struct amdgpu_vm *vm,
+ 		/* Good, we can use this VMID. Remember this submission as
+ 		 * user of the VMID.
+ 		 */
+-		r = amdgpu_sync_fence(ring->adev, &(*id)->active, fence, false);
++		r = amdgpu_sync_fence(&(*id)->active, fence, false);
+ 		if (r)
+ 			return r;
+ 
+@@ -435,8 +435,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
+ 			id = idle;
+ 
+ 			/* Remember this submission as user of the VMID */
+-			r = amdgpu_sync_fence(ring->adev, &id->active,
+-					      fence, false);
++			r = amdgpu_sync_fence(&id->active, fence, false);
+ 			if (r)
+ 				goto error;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+index 71fd9bb7ead7..8b7fce7c811f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+@@ -193,8 +193,7 @@ static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job,
+ 	fence = amdgpu_sync_get_fence(&job->sync, &explicit);
+ 	if (fence && explicit) {
+ 		if (drm_sched_dependency_optimized(fence, s_entity)) {
+-			r = amdgpu_sync_fence(ring->adev, &job->sched_sync,
+-					      fence, false);
++			r = amdgpu_sync_fence(&job->sched_sync, fence, false);
+ 			if (r)
+ 				DRM_ERROR("Error adding fence (%d)\n", r);
+ 		}
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
+index 3d5beb00b0db..a467b177543b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c
+@@ -408,7 +408,7 @@ int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct drm_sched_entity *entity,
+ 	mutex_lock(&centity->sem_lock);
+ 	list_for_each_entry_safe(dep, tmp, &centity->sem_dep_list,
+ 				 list) {
+-		r = amdgpu_sync_fence(ctx->adev, sync, dep->fence, true);
++		r = amdgpu_sync_fence(sync, dep->fence, true);
+ 		if (r)
+ 			goto err;
+ 		dma_fence_put(dep->fence);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+index 2d6f5ec77a68..17f017fc8fcb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+@@ -130,7 +130,8 @@ static void amdgpu_sync_keep_later(struct dma_fence **keep,
+  * Tries to add the fence to an existing hash entry. Returns true when an entry
+  * was found, false otherwise.
+  */
+-static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f, bool explicit)
++static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f,
++				  bool explicit)
+ {
+ 	struct amdgpu_sync_entry *e;
+ 
+@@ -152,19 +153,18 @@ static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f,
+  * amdgpu_sync_fence - remember to sync to this fence
+  *
+  * @sync: sync object to add fence to
+- * @fence: fence to sync to
++ * @f: fence to sync to
++ * @explicit: if this is an explicit dependency
+  *
++ * Add the fence to the sync object.
+  */
+-int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
+-		      struct dma_fence *f, bool explicit)
++int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f,
++		      bool explicit)
+ {
+ 	struct amdgpu_sync_entry *e;
+ 
+ 	if (!f)
+ 		return 0;
+-	if (amdgpu_sync_same_dev(adev, f) &&
+-	    amdgpu_sync_get_owner(f) == AMDGPU_FENCE_OWNER_VM)
+-		amdgpu_sync_keep_later(&sync->last_vm_update, f);
+ 
+ 	if (amdgpu_sync_add_later(sync, f, explicit))
+ 		return 0;
+@@ -180,6 +180,24 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
+ 	return 0;
+ }
+ 
++/**
++ * amdgpu_sync_vm_fence - remember to sync to this VM fence
++ *
++ * @adev: amdgpu device
++ * @sync: sync object to add fence to
++ * @fence: the VM fence to add
++ *
++ * Add the fence to the sync object and remember it as VM update.
++ */
++int amdgpu_sync_vm_fence(struct amdgpu_sync *sync, struct dma_fence *fence)
++{
++	if (!fence)
++		return 0;
++
++	amdgpu_sync_keep_later(&sync->last_vm_update, fence);
++	return amdgpu_sync_fence(sync, fence, false);
++}
++
+ /**
+  * amdgpu_sync_resv - sync to a reservation object
+  *
+@@ -205,7 +223,7 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
+ 
+ 	/* always sync to the exclusive fence */
+ 	f = reservation_object_get_excl(resv);
+-	r = amdgpu_sync_fence(adev, sync, f, false);
++	r = amdgpu_sync_fence(sync, f, false);
+ 
+ 	flist = reservation_object_get_list(resv);
+ 	if (!flist || r)
+@@ -240,7 +258,7 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
+ 				continue;
+ 		}
+ 
+-		r = amdgpu_sync_fence(adev, sync, f, false);
++		r = amdgpu_sync_fence(sync, f, false);
+ 		if (r)
+ 			break;
+ 	}
+@@ -341,7 +359,7 @@ int amdgpu_sync_clone(struct amdgpu_sync *source, struct amdgpu_sync *clone)
+ 	hash_for_each_safe(source->fences, i, tmp, e, node) {
+ 		f = e->fence;
+ 		if (!dma_fence_is_signaled(f)) {
+-			r = amdgpu_sync_fence(NULL, clone, f, e->explicit);
++			r = amdgpu_sync_fence(clone, f, e->explicit);
+ 			if (r)
+ 				return r;
+ 		} else {
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h
+index 10cf23a57f17..7ca71b306301 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h
+@@ -40,8 +40,9 @@ struct amdgpu_sync {
+ };
+ 
+ void amdgpu_sync_create(struct amdgpu_sync *sync);
+-int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
+-		      struct dma_fence *f, bool explicit);
++int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f,
++		      bool explicit);
++int amdgpu_sync_vm_fence(struct amdgpu_sync *sync, struct dma_fence *fence);
+ int amdgpu_sync_resv(struct amdgpu_device *adev,
+ 		     struct amdgpu_sync *sync,
+ 		     struct reservation_object *resv,
+@@ -49,7 +50,8 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
+ 		     bool explicit_sync);
+ struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
+ 				     struct amdgpu_ring *ring);
+-struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync, bool *explicit);
++struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync,
++					bool *explicit);
+ int amdgpu_sync_clone(struct amdgpu_sync *source, struct amdgpu_sync *clone);
+ int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr);
+ void amdgpu_sync_free(struct amdgpu_sync *sync);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+index e8db1467a71d..107def9c3611 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+@@ -71,7 +71,7 @@ static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p,
+ 	p->num_dw_left = ndw;
+ 
+ 	/* Wait for moves to be completed */
+-	r = amdgpu_sync_fence(p->adev, &p->job->sync, exclusive, false);
++	r = amdgpu_sync_fence(&p->job->sync, exclusive, false);
+ 	if (r)
+ 		return r;
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4724-drm-amdgpu-add-condition-to-enable-baco-for-ras-reco.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4724-drm-amdgpu-add-condition-to-enable-baco-for-ras-reco.patch
new file mode 100644
index 00000000..4857af18
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4724-drm-amdgpu-add-condition-to-enable-baco-for-ras-reco.patch
@@ -0,0 +1,60 @@
+From 09a07770eb015b075f2f1914e972f12ccb471e3c Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Tue, 26 Nov 2019 17:56:58 +0800
+Subject: [PATCH 4724/4736] drm/amdgpu: add condition to enable baco for ras
+ recovery
+
+Switch to baco reset method for ras recovery if the PMFW supported.
+If not, keep the original reset method.
+
+v2: revise the condition
+
+Change-Id: I07c3e6862be03e068745c73db8ea71f428ecba6b
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 18 ++++++++----------
+ 1 file changed, 8 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 3a2ec932c0bb..512d42b23603 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -556,7 +556,8 @@ static int soc15_mode2_reset(struct amdgpu_device *adev)
+ static enum amd_reset_method
+ soc15_asic_reset_method(struct amdgpu_device *adev)
+ {
+-	bool baco_reset;
++	bool baco_reset = false;
++	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_RAVEN:
+@@ -570,18 +571,15 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
+ 	case CHIP_VEGA20:
+ 		if (adev->psp.sos_fw_version >= 0x80067)
+ 			soc15_asic_get_baco_capability(adev, &baco_reset);
+-		else
+-			baco_reset = false;
+-		if (baco_reset) {
+-			struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
+-			struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
+ 
+-			if (hive || (ras && ras->supported))
+-				baco_reset = false;
+-		}
++		/*
++		 * 1. PMFW version > 0x284300: all cases use baco
++		 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
++		 */
++		if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
++			baco_reset = false;
+ 		break;
+ 	default:
+-		baco_reset = false;
+ 		break;
+ 	}
+ 
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4725-drm-amdgpu-Add-RAS-dbg-print-support.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4725-drm-amdgpu-Add-RAS-dbg-print-support.patch
new file mode 100644
index 00000000..59455bdc
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4725-drm-amdgpu-Add-RAS-dbg-print-support.patch
@@ -0,0 +1,124 @@
+From eaa700cb57a23278d319c888d78d597db3a35a24 Mon Sep 17 00:00:00 2001
+From: John Clements <john.clements@amd.com>
+Date: Tue, 3 Dec 2019 11:12:34 +0800
+Subject: [PATCH 4725/4736] drm/amdgpu: Add RAS dbg print support
+
+Leverage host to TA shared memory to capture dbg log information from RAS TA
+
+Change-Id: I5e287560a6d493edf9bc6ac9ebbcbaeca0017dc8
+Signed-off-by: John Clements <john.clements@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 34 +++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h |  2 +-
+ drivers/gpu/drm/amd/amdgpu/ta_ras_if.h  | 16 ++++++++++++
+ 3 files changed, 51 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+index 9b869fa9b594..f91da0b43e8c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+@@ -616,6 +616,36 @@ static int psp_xgmi_initialize(struct psp_context *psp)
+ }
+ 
+ // ras begin
++void psp_ras_print_dbg_msg(struct psp_context *psp)
++{
++	struct ta_ras_shared_memory *ras_cmd;
++	struct ta_dbg_msg_list *dbg_msgs;
++	struct ta_dbg_msg* msg;
++	uint32_t mem_offset;
++	int i, sec, m_sec;
++
++	ras_cmd  = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
++	dbg_msgs = &ras_cmd->debug_messages;
++	msg 	 = &dbg_msgs->msg;
++
++	for (i = 0; i < dbg_msgs->msg_cnt; i++)
++	{
++		mem_offset = (uint8_t*)msg - (uint8_t*)ras_cmd;
++
++		/* Validate memory access does not overflow shared region */
++		if (mem_offset >= PSP_RAS_SHARED_MEM_SIZE)
++			break;
++
++		/* Time stamp = seconds*1000000 + milli-seconds*1000 */
++		sec	= (int)msg->time_stamp/1000000;
++		m_sec 	= ((int)msg->time_stamp - sec*1000000) / 1000;
++
++		DRM_INFO("[RAS] %d.%d : %s\n", sec, m_sec, msg->msg);
++
++		msg = (struct ta_dbg_msg*)((uint8_t*)msg + SIZE_OF_MSG_STRUCT(msg));
++	}
++}
++
+ static void psp_prep_ras_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
+ 		uint64_t ras_ta_mc, uint64_t ras_mc_shared,
+ 		uint32_t ras_ta_size, uint32_t shared_size)
+@@ -679,6 +709,8 @@ static int psp_ras_load(struct psp_context *psp)
+ 
+ 	kfree(cmd);
+ 
++	psp_ras_print_dbg_msg(psp);
++
+ 	return ret;
+ }
+ 
+@@ -747,6 +779,8 @@ int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
+ 
+ 	kfree(cmd);
+ 
++	psp_ras_print_dbg_msg(psp);
++
+ 	return ret;
+ }
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+index 5f8fd3e3535b..a4d7690ea577 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+@@ -33,7 +33,7 @@
+ #define PSP_FENCE_BUFFER_SIZE	0x1000
+ #define PSP_CMD_BUFFER_SIZE	0x1000
+ #define PSP_XGMI_SHARED_MEM_SIZE 0x4000
+-#define PSP_RAS_SHARED_MEM_SIZE 0x4000
++#define PSP_RAS_SHARED_MEM_SIZE 0x8000
+ #define PSP_1_MEG		0x100000
+ #define PSP_TMR_SIZE	0x400000
+ #define PSP_HDCP_SHARED_MEM_SIZE	0x4000
+diff --git a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
+index ca7d05993ca2..bf1c4c55ce58 100644
+--- a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
++++ b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
+@@ -97,6 +97,21 @@ struct ta_ras_trigger_error_input {
+ 	uint64_t		value;			// method if error injection. i.e persistent, coherent etc.
+ };
+ 
++#define SIZE_OF_MSG_STRUCT(msg_ptr) ((msg_ptr)->msg_size + sizeof(struct ta_dbg_msg) - sizeof(char))
++struct __attribute__((__packed__)) ta_dbg_msg
++{
++	uint16_t msg_size;      // Not including string terminator
++	uint64_t time_stamp;
++	char     msg[1];	// string of size determined by msg_size
++};
++
++struct ta_dbg_msg_list
++{
++	uint32_t            total_buf_size;
++	uint32_t            msg_cnt;
++	struct ta_dbg_msg   msg;
++};
++
+ /* Common input structure for RAS callbacks */
+ /**********************************************************/
+ union ta_ras_cmd_input {
+@@ -113,6 +128,7 @@ struct ta_ras_shared_memory {
+ 	enum ta_ras_status	ras_status;
+ 	uint32_t		reserved;
+ 	union ta_ras_cmd_input	ras_in_message;
++	struct ta_dbg_msg_list	debug_messages;
+ };
+ 
+ #endif // TL_RAS_IF_H_
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4726-drm-amdgpu-Added-RAS-UMC-error-query-support-for-Arc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4726-drm-amdgpu-Added-RAS-UMC-error-query-support-for-Arc.patch
new file mode 100644
index 00000000..c91ce0bb
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4726-drm-amdgpu-Added-RAS-UMC-error-query-support-for-Arc.patch
@@ -0,0 +1,175 @@
+From b314adff2767fe2e6fdbfba1149f29d6aed845de Mon Sep 17 00:00:00 2001
+From: John Clements <john.clements@amd.com>
+Date: Wed, 11 Dec 2019 10:18:55 +0800
+Subject: [PATCH 4726/4736] drm/amdgpu: Added RAS UMC error query support for
+ Arcturus
+
+Updated UMC 6.1 function set to support UMC 6.1.1 and 6.1.2 devices
+
+Change-Id: I7b106328d24aba5ab93a8f4cddb1635392eecd0f
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: John Clements <john.clements@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  9 +++-
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 78 ++++++++++++++++++++++-----
+ drivers/gpu/drm/amd/amdgpu/umc_v6_1.h |  3 +-
+ 3 files changed, 74 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index b051ede2fb83..a2d1016ce81a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -692,11 +692,18 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
+ 		adev->umc.funcs = &umc_v6_0_funcs;
+ 		break;
+ 	case CHIP_VEGA20:
++		adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
++		adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
++		adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
++		adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
++		adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
++		adev->umc.funcs = &umc_v6_1_funcs;
++		break;
+ 	case CHIP_ARCTURUS:
+ 		adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
+ 		adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
+ 		adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
+-		adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET;
++		adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
+ 		adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
+ 		adev->umc.funcs = &umc_v6_1_funcs;
+ 		break;
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+index 47c4b96b14d1..515eb50cd0f8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+@@ -31,6 +31,14 @@
+ 
+ #define smnMCA_UMC0_MCUMC_ADDRT0	0x50f10
+ 
++/* UMC 6_1_2 register offsets */
++#define mmUMCCH0_0_EccErrCntSel_ARCT                 0x0360
++#define mmUMCCH0_0_EccErrCntSel_ARCT_BASE_IDX        1
++#define mmUMCCH0_0_EccErrCnt_ARCT                    0x0361
++#define mmUMCCH0_0_EccErrCnt_ARCT_BASE_IDX           1
++#define mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT           0x03c2
++#define mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT_BASE_IDX  1
++
+ /*
+  * (addr / 256) * 8192, the higher 26 bits in ErrorAddr
+  * is the index of 8KB block
+@@ -95,12 +103,25 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
+ 	uint64_t mc_umc_status;
+ 	uint32_t mc_umc_status_addr;
+ 
+-	ecc_err_cnt_sel_addr =
+-		SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
+-	ecc_err_cnt_addr =
+-		SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
+-	mc_umc_status_addr =
+-		SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
++	if (adev->asic_type == CHIP_ARCTURUS) {
++		/* UMC 6_1_2 registers */
++
++		ecc_err_cnt_sel_addr =
++			SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel_ARCT);
++		ecc_err_cnt_addr =
++			SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt_ARCT);
++		mc_umc_status_addr =
++			SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT);
++	} else {
++		/* UMC 6_1_1 registers */
++
++		ecc_err_cnt_sel_addr =
++			SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
++		ecc_err_cnt_addr =
++			SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
++		mc_umc_status_addr =
++			SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
++	}
+ 
+ 	/* select the lower chip and check the error count */
+ 	ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset);
+@@ -141,8 +162,17 @@ static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev
+ 	uint64_t mc_umc_status;
+ 	uint32_t mc_umc_status_addr;
+ 
+-	mc_umc_status_addr =
+-                SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
++	if (adev->asic_type == CHIP_ARCTURUS) {
++		/* UMC 6_1_2 registers */
++
++		mc_umc_status_addr =
++			SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT);
++	} else {
++		/* UMC 6_1_1 registers */
++
++		mc_umc_status_addr =
++			SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
++	}
+ 
+ 	/* check the MCUMC_STATUS */
+ 	mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
+@@ -179,8 +209,17 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
+ 	uint64_t mc_umc_status, err_addr, retired_page;
+ 	struct eeprom_table_record *err_rec;
+ 
+-	mc_umc_status_addr =
+-		SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
++	if (adev->asic_type == CHIP_ARCTURUS) {
++		/* UMC 6_1_2 registers */
++
++		mc_umc_status_addr =
++			SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT);
++	} else {
++		/* UMC 6_1_1 registers */
++
++		mc_umc_status_addr =
++			SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
++	}
+ 
+ 	/* skip error address process if -ENOMEM */
+ 	if (!err_data->err_addr) {
+@@ -241,10 +280,21 @@ static void umc_v6_1_err_cnt_init_per_channel(struct amdgpu_device *adev,
+ 	uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
+ 	uint32_t ecc_err_cnt_addr;
+ 
+-	ecc_err_cnt_sel_addr =
+-		SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
+-	ecc_err_cnt_addr =
+-		SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
++	if (adev->asic_type == CHIP_ARCTURUS) {
++		/* UMC 6_1_2 registers */
++
++		ecc_err_cnt_sel_addr =
++			SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel_ARCT);
++		ecc_err_cnt_addr =
++			SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt_ARCT);
++	} else {
++		/* UMC 6_1_1 registers */
++
++		ecc_err_cnt_sel_addr =
++			SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
++		ecc_err_cnt_addr =
++			SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
++	}
+ 
+ 	/* select the lower chip and check the error count */
+ 	ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset);
+diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
+index dab9cbd292c5..0ce1d323cfdd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
++++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
+@@ -35,7 +35,8 @@
+ /* total channel instances in one umc block */
+ #define UMC_V6_1_TOTAL_CHANNEL_NUM	(UMC_V6_1_CHANNEL_INSTANCE_NUM * UMC_V6_1_UMC_INSTANCE_NUM)
+ /* UMC regiser per channel offset */
+-#define UMC_V6_1_PER_CHANNEL_OFFSET		0x800
++#define UMC_V6_1_PER_CHANNEL_OFFSET_VG20	0x800
++#define UMC_V6_1_PER_CHANNEL_OFFSET_ARCT	0x400
+ 
+ /* EccErrCnt max value */
+ #define UMC_V6_1_CE_CNT_MAX		0xffff
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4727-drm-amd-powerplay-clear-VBIOS-scratchs-on-baco-exit-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4727-drm-amd-powerplay-clear-VBIOS-scratchs-on-baco-exit-.patch
new file mode 100644
index 00000000..53191b48
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4727-drm-amd-powerplay-clear-VBIOS-scratchs-on-baco-exit-.patch
@@ -0,0 +1,42 @@
+From 96860e79942a5f30e0234e04755c69cb6b7ea160 Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Fri, 6 Dec 2019 11:30:45 +0800
+Subject: [PATCH 4727/4736] drm/amd/powerplay: clear VBIOS scratchs on baco
+ exit V2
+
+This is needed for coming asic init on performing gpu reset.
+
+V2: use non-asic specific programing way
+
+Change-Id: If3671a24d239e3d288665fadaa2c40c87d5da40b
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+index d65187993ef9..83113cb2524c 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+@@ -1675,10 +1675,17 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
+ 		}
+ 	} else {
+ 		ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
++		if (ret)
++			goto out;
++
+ 		bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
+ 						BIF_DOORBELL_INT_CNTL,
+ 						DOORBELL_INTERRUPT_DISABLE, 0);
+ 		WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
++
++		/* clear vbios scratch 6 and 7 for coming asic reinit */
++		WREG32(adev->bios_scratch_reg_offset + 6, 0);
++		WREG32(adev->bios_scratch_reg_offset + 7, 0);
+ 	}
+ 	if (ret)
+ 		goto out;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4728-drm-amd-powerplay-implement-interface-to-retrieve-gp.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4728-drm-amd-powerplay-implement-interface-to-retrieve-gp.patch
new file mode 100644
index 00000000..b57c928e
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4728-drm-amd-powerplay-implement-interface-to-retrieve-gp.patch
@@ -0,0 +1,58 @@
+From 8dcca48dd79c24e8c92a42282025116ca5205299 Mon Sep 17 00:00:00 2001
+From: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
+Date: Wed, 4 Dec 2019 13:35:18 +0800
+Subject: [PATCH 4728/4736] drm/amd/powerplay: implement interface to retrieve
+ gpu temperature for renoir
+
+add sensor interface of get gpu temperature for debugfs.
+
+Change-Id: I2499b6652fad6d5d776b6ed4cd5157636583ed39
+Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index c982f69065ae..be3c996728b1 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -412,6 +412,24 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
+ 	return ret;
+ }
+ 
++static int renoir_get_gpu_temperature(struct smu_context *smu, uint32_t *value)
++{
++	int ret = 0;
++	SmuMetrics_t metrics;
++
++	if (!value)
++		return -EINVAL;
++
++	ret = renoir_get_metrics_table(smu, &metrics);
++	if (ret)
++		return ret;
++
++	*value = (metrics.GfxTemperature / 100) *
++		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
++
++	return 0;
++}
++
+ static int renoir_get_current_activity_percent(struct smu_context *smu,
+ 					       enum amd_pp_sensors sensor,
+ 					       uint32_t *value)
+@@ -767,6 +785,10 @@ static int renoir_read_sensor(struct smu_context *smu,
+ 		ret = renoir_get_current_activity_percent(smu, sensor, (uint32_t *)data);
+ 		*size = 4;
+ 		break;
++	case AMDGPU_PP_SENSOR_GPU_TEMP:
++		ret = renoir_get_gpu_temperature(smu, (uint32_t *)data);
++		*size = 4;
++		break;
+ 	default:
+ 		ret = smu_v12_0_read_sensor(smu, sensor, data, size);
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4729-drm-amd-powerplay-implement-interface-to-retrieve-cl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4729-drm-amd-powerplay-implement-interface-to-retrieve-cl.patch
new file mode 100644
index 00000000..d2902008
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4729-drm-amd-powerplay-implement-interface-to-retrieve-cl.patch
@@ -0,0 +1,169 @@
+From dd90194758a70456d1de08bd83f6d4fdfd682e44 Mon Sep 17 00:00:00 2001
+From: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
+Date: Wed, 4 Dec 2019 15:17:38 +0800
+Subject: [PATCH 4729/4736] drm/amd/powerplay: implement interface to retrieve
+ clock freq for renoir
+
+implement smu12 get_clk_freq interface to get clock frequency like
+MCLK/SCLK.
+
+Change-Id: I2481d649811c15cd2d8e2741242b2928a32413fc
+Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h |  4 ++
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c    | 49 +++++++++++++++++++
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c     | 20 ++++++++
+ 3 files changed, 73 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+index 922973b7e29f..ad68a5623033 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+@@ -75,6 +75,10 @@ int smu_v12_0_fini_smc_tables(struct smu_context *smu);
+ 
+ int smu_v12_0_populate_smc_tables(struct smu_context *smu);
+ 
++int smu_v12_0_get_current_clk_freq(struct smu_context *smu,
++					  enum smu_clk_type clk_id,
++					  uint32_t *value);
++
+ int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
+ 						 uint32_t *min, uint32_t *max);
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index be3c996728b1..861445f66e3e 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -31,6 +31,9 @@
+ #include "renoir_ppt.h"
+ 
+ 
++#define CLK_MAP(clk, index) \
++	[SMU_##clk] = {1, (index)}
++
+ #define MSG_MAP(msg, index) \
+ 	[SMU_MSG_##msg] = {1, (index)}
+ 
+@@ -104,6 +107,14 @@ static struct smu_12_0_cmn2aisc_mapping renoir_message_map[SMU_MSG_MAX_COUNT] =
+ 	MSG_MAP(SetHardMinFclkByFreq,           PPSMC_MSG_SetHardMinFclkByFreq),
+ };
+ 
++static struct smu_12_0_cmn2aisc_mapping renoir_clk_map[SMU_CLK_COUNT] = {
++	CLK_MAP(GFXCLK, CLOCK_GFXCLK),
++	CLK_MAP(SCLK,	CLOCK_GFXCLK),
++	CLK_MAP(SOCCLK, CLOCK_SOCCLK),
++	CLK_MAP(UCLK, CLOCK_UMCCLK),
++	CLK_MAP(MCLK, CLOCK_UMCCLK),
++};
++
+ static struct smu_12_0_cmn2aisc_mapping renoir_table_map[SMU_TABLE_COUNT] = {
+ 	TAB_MAP_VALID(WATERMARKS),
+ 	TAB_MAP_INVALID(CUSTOM_DPM),
+@@ -125,6 +136,21 @@ static int renoir_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+ 	return mapping.map_to;
+ }
+ 
++static int renoir_get_smu_clk_index(struct smu_context *smc, uint32_t index)
++{
++	struct smu_12_0_cmn2aisc_mapping mapping;
++
++	if (index >= SMU_CLK_COUNT)
++		return -EINVAL;
++
++	mapping = renoir_clk_map[index];
++	if (!(mapping.valid_mapping)) {
++		return -EINVAL;
++	}
++
++	return mapping.map_to;
++}
++
+ static int renoir_get_smu_table_index(struct smu_context *smc, uint32_t index)
+ {
+ 	struct smu_12_0_cmn2aisc_mapping mapping;
+@@ -352,6 +378,26 @@ static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
+ 	return ret;
+ }
+ 
++static int renoir_get_current_clk_freq_by_table(struct smu_context *smu,
++				       enum smu_clk_type clk_type,
++				       uint32_t *value)
++{
++	int ret = 0, clk_id = 0;
++	SmuMetrics_t metrics;
++
++	ret = renoir_get_metrics_table(smu, &metrics);
++	if (ret)
++		return ret;
++
++	clk_id = smu_clk_get_index(smu, clk_type);
++	if (clk_id < 0)
++		return clk_id;
++
++	*value = metrics.ClockFrequency[clk_id];
++
++	return ret;
++}
++
+ static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
+ {
+ 	int ret = 0, i = 0;
+@@ -799,6 +845,7 @@ static int renoir_read_sensor(struct smu_context *smu,
+ 
+ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_smu_msg_index = renoir_get_smu_msg_index,
++	.get_smu_clk_index = renoir_get_smu_clk_index,
+ 	.get_smu_table_index = renoir_get_smu_table_index,
+ 	.tables_init = renoir_tables_init,
+ 	.set_power_state = NULL,
+@@ -807,6 +854,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.get_current_power_state = renoir_get_current_power_state,
+ 	.dpm_set_uvd_enable = renoir_dpm_set_uvd_enable,
+ 	.dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
++	.get_current_clk_freq_by_table = renoir_get_current_clk_freq_by_table,
+ 	.force_dpm_limit_value = renoir_force_dpm_limit_value,
+ 	.unforce_dpm_levels = renoir_unforce_dpm_levels,
+ 	.get_workload_type = renoir_get_workload_type,
+@@ -830,6 +878,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.init_smc_tables = smu_v12_0_init_smc_tables,
+ 	.fini_smc_tables = smu_v12_0_fini_smc_tables,
+ 	.populate_smc_tables = smu_v12_0_populate_smc_tables,
++	.get_current_clk_freq = smu_v12_0_get_current_clk_freq,
+ 	.get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
+ 	.mode2_reset = smu_v12_0_mode2_reset,
+ 	.set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 951aa4570a04..0e10cec5e9c3 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -330,6 +330,26 @@ int smu_v12_0_populate_smc_tables(struct smu_context *smu)
+ 	return smu_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
+ }
+ 
++int smu_v12_0_get_current_clk_freq(struct smu_context *smu,
++					  enum smu_clk_type clk_id,
++					  uint32_t *value)
++{
++	int ret = 0;
++	uint32_t freq = 0;
++
++	if (clk_id >= SMU_CLK_COUNT || !value)
++		return -EINVAL;
++
++	ret = smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
++	if (ret)
++		return ret;
++
++	freq *= 100;
++	*value = freq;
++
++	return ret;
++}
++
+ int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
+ 						 uint32_t *min, uint32_t *max)
+ {
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4730-drm-amd-powerplay-implement-the-get_enabled_mask-cal.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4730-drm-amd-powerplay-implement-the-get_enabled_mask-cal.patch
new file mode 100644
index 00000000..6156d4fe
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4730-drm-amd-powerplay-implement-the-get_enabled_mask-cal.patch
@@ -0,0 +1,86 @@
+From 54649e5391dfd485199180fea93fbd8ba2165421 Mon Sep 17 00:00:00 2001
+From: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
+Date: Wed, 4 Dec 2019 16:16:30 +0800
+Subject: [PATCH 4730/4736] drm/amd/powerplay: implement the get_enabled_mask
+ callback for smu12
+
+implement sensor interface of feature mask for debugfs.
+
+Change-Id: Ia085aab4c82b978e1e8c8ddc3ca6278b9dec8005
+Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h |  3 ++
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c    |  1 +
+ drivers/gpu/drm/amd/powerplay/smu_v12_0.c     | 29 +++++++++++++++++++
+ 3 files changed, 33 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+index ad68a5623033..3f1cd06e273c 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+@@ -75,6 +75,9 @@ int smu_v12_0_fini_smc_tables(struct smu_context *smu);
+ 
+ int smu_v12_0_populate_smc_tables(struct smu_context *smu);
+ 
++int smu_v12_0_get_enabled_mask(struct smu_context *smu,
++				      uint32_t *feature_mask, uint32_t num);
++
+ int smu_v12_0_get_current_clk_freq(struct smu_context *smu,
+ 					  enum smu_clk_type clk_id,
+ 					  uint32_t *value);
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 861445f66e3e..5fdfbf5a1ed5 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -878,6 +878,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
+ 	.init_smc_tables = smu_v12_0_init_smc_tables,
+ 	.fini_smc_tables = smu_v12_0_fini_smc_tables,
+ 	.populate_smc_tables = smu_v12_0_populate_smc_tables,
++	.get_enabled_mask = smu_v12_0_get_enabled_mask,
+ 	.get_current_clk_freq = smu_v12_0_get_current_clk_freq,
+ 	.get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
+ 	.mode2_reset = smu_v12_0_mode2_reset,
+diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+index 0e10cec5e9c3..2ac7f2f231b6 100644
+--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
++++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+@@ -330,6 +330,35 @@ int smu_v12_0_populate_smc_tables(struct smu_context *smu)
+ 	return smu_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
+ }
+ 
++int smu_v12_0_get_enabled_mask(struct smu_context *smu,
++				      uint32_t *feature_mask, uint32_t num)
++{
++	uint32_t feature_mask_high = 0, feature_mask_low = 0;
++	int ret = 0;
++
++	if (!feature_mask || num < 2)
++		return -EINVAL;
++
++	ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
++	if (ret)
++		return ret;
++	ret = smu_read_smc_arg(smu, &feature_mask_high);
++	if (ret)
++		return ret;
++
++	ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
++	if (ret)
++		return ret;
++	ret = smu_read_smc_arg(smu, &feature_mask_low);
++	if (ret)
++		return ret;
++
++	feature_mask[0] = feature_mask_low;
++	feature_mask[1] = feature_mask_high;
++
++	return ret;
++}
++
+ int smu_v12_0_get_current_clk_freq(struct smu_context *smu,
+ 					  enum smu_clk_type clk_id,
+ 					  uint32_t *value)
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4731-drm-amd-powerplay-correct-the-value-retrieved-throug.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4731-drm-amd-powerplay-correct-the-value-retrieved-throug.patch
new file mode 100644
index 00000000..24f2c366
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4731-drm-amd-powerplay-correct-the-value-retrieved-throug.patch
@@ -0,0 +1,33 @@
+From d56aca934ff8f012a2aa4ec00575975a22e97d2e Mon Sep 17 00:00:00 2001
+From: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
+Date: Wed, 4 Dec 2019 17:01:21 +0800
+Subject: [PATCH 4731/4736] drm/amd/powerplay: correct the value retrieved
+ through GPU_LOAD sensor interface
+
+the unit of variable AverageGfxActivity defined in smu12 metrics
+struct is centi, so the retrieved value should be divided by 100 before
+return.
+
+Change-Id: Ia7873597977cb5479b015d632ab24a7aa20a1cfb
+Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+index 5fdfbf5a1ed5..0d8ea56731e4 100644
+--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
++++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+@@ -492,7 +492,7 @@ static int renoir_get_current_activity_percent(struct smu_context *smu,
+ 
+ 	switch (sensor) {
+ 	case AMDGPU_PP_SENSOR_GPU_LOAD:
+-		*value = metrics.AverageGfxActivity;
++		*value = metrics.AverageGfxActivity / 100;
+ 		break;
+ 	default:
+ 		pr_err("Invalid sensor for retrieving clock activity\n");
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4732-drm-amdgpu-enable-gfxoff-feature-for-navi10-asic.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4732-drm-amdgpu-enable-gfxoff-feature-for-navi10-asic.patch
new file mode 100644
index 00000000..803f26ae
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4732-drm-amdgpu-enable-gfxoff-feature-for-navi10-asic.patch
@@ -0,0 +1,51 @@
+From 632865701bdeaa26154bbd51bb351d73e7df5370 Mon Sep 17 00:00:00 2001
+From: Kevin Wang <kevin1.wang@amd.com>
+Date: Wed, 11 Dec 2019 17:30:26 +0800
+Subject: [PATCH 4732/4736] drm/amdgpu: enable gfxoff feature for navi10 asic
+
+enable gfxoff feature for some navi10 asics
+
+Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
+Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 20 +++++++++++++++++++-
+ 1 file changed, 19 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index ed630d37c32c..6b8f21574c7c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -605,11 +605,29 @@ static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
+ 			le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
+ }
+ 
++static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
++{
++	bool ret = false;
++
++	switch (adev->pdev->revision) {
++	case 0xc2:
++	case 0xc3:
++		ret = true;
++		break;
++	default:
++		ret = false;
++		break;
++	}
++
++	return ret ;
++}
++
+ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
+ {
+ 	switch (adev->asic_type) {
+ 	case CHIP_NAVI10:
+-		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
++		if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
++			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ 		break;
+ 	default:
+ 		break;
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4733-drm-amdgpu-gfx10-update-gfx-golden-settings.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4733-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
new file mode 100644
index 00000000..d541ea59
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4733-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
@@ -0,0 +1,27 @@
+From 62eb0590d363fe0eddf856e41fc7be7fe2e95828 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Wed, 11 Dec 2019 10:43:07 +0800
+Subject: [PATCH 4733/4736] drm/amdgpu/gfx10: update gfx golden settings
+
+add registers: mmSPI_CONFIG_CNTL
+Reviewed-by: Feifei Xu <Feifei Xu@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 6b8f21574c7c..2eb18f41a8fc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -114,6 +114,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1[] =
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000, 0x00070104),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4734-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4734-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
new file mode 100644
index 00000000..3e86dd28
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4734-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
@@ -0,0 +1,29 @@
+From 2b3d2a997a2ed76f04e518975153278200274a28 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Wed, 11 Dec 2019 10:52:14 +0800
+Subject: [PATCH 4734/4736] drm/amdgpu/gfx10: update gfx golden settings for
+ navi14
+
+add registers: mmSPI_CONFIG_CNTL
+
+Reviewed-by: Feifei Xu <Feifei Xu@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 2eb18f41a8fc..2b91e542a778 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -160,6 +160,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000, 0x00070105),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4735-drm-amdgpu-gfx10-update-gfx-golden-settings.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4735-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
new file mode 100644
index 00000000..90b742b8
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4735-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
@@ -0,0 +1,32 @@
+From ff2ef41fc95bb1da4878b2f8cfd3f9cfc79560b2 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Wed, 11 Dec 2019 19:55:49 +0800
+Subject: [PATCH 4735/4736] drm/amdgpu/gfx10: update gfx golden settings
+
+add registers: mmPA_SC_BINNER_TIMEOUT_COUNTER and mmPA_SC_ENHANCE_2
+
+Change-Id: I23dabb0e706af0b5376f9749200832e894944eca
+Reviewed-by: Feifei Xu <Feifei Xu@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 2b91e542a778..443d7277162f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -110,8 +110,10 @@ static const struct soc15_reg_golden golden_settings_gc_10_1[] =
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000, 0x00070104),
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4736-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4736-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
new file mode 100644
index 00000000..586063da
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4736-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
@@ -0,0 +1,33 @@
+From 54482cb8cb5014d349c5cf5df33dedda7b134392 Mon Sep 17 00:00:00 2001
+From: "Tianci.Yin" <tianci.yin@amd.com>
+Date: Wed, 11 Dec 2019 19:57:43 +0800
+Subject: [PATCH 4736/4736] drm/amdgpu/gfx10: update gfx golden settings for
+ navi14
+
+add registers: mmPA_SC_BINNER_TIMEOUT_COUNTER and mmPA_SC_ENHANCE_2
+
+Change-Id: I1fc3fb481b2d9edc482a32497242a8be6cd6b8d7
+Reviewed-by: Feifei Xu <Feifei Xu@amd.com>
+Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 443d7277162f..cfa2c3d81d87 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -158,8 +158,10 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
++	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
+ 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000, 0x00070105),
+-- 
+2.17.1
+
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/amdgpu-patches.scc b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/amdgpu-patches.scc
index bfc16406..9e28dba7 100755
--- a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/amdgpu-patches.scc
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/amdgpu-patches.scc
@@ -2938,4 +2938,1800 @@ patch 2937-drm-amdgpu-Clear-build-undefined-warning.patch
 patch 2938-drm-amdgpu-declare-sdma-firmware-binary-files-for-Ar.patch
 patch 2939-drm-amdgpu-VCN2-put-IB-internal-registers-offset-to-.patch
 patch 2940-drm-amdgpu-VCN2-expose-rings-functions.patch
+patch 2941-drm-amdgpu-sort-probed-modes-before-adding-common-mo.patch
+patch 2942-drm-amdgpu-add-VCN2.5-basic-supports-1-7-patch.patch
+patch 2943-drm-amdgpu-add-VCN2.5-VCPU-start-and-stop-2-7-patch.patch
+patch 2944-drm-amdgpu-add-Arcturus-to-the-VCN-family-3-7-patch.patch
+patch 2945-drm-amdgpu-VCN2.5-set-decode-ring-functions-4-7-patc.patch
+patch 2946-drm-amdgpu-VCN2.5-set-encode-ring-functions-5-7-patc.patch
+patch 2947-drm-amdgpu-add-JPEG2.5-HW-start-and-stop-6-7-patch.patch
+patch 2948-drm-amdgpu-VCN2.5-set-JPEG-decode-ring-functions-7-7.patch
+patch 2949-drm-amdgpu-enable-VCN2.5-on-Arcturus.patch
+patch 2950-drm-amdgpu-add-vcn-doorbell-range-function-to-nbio7..patch
+patch 2951-drm-amdgpu-enable-the-Doorbell-support-for-VCN2.5.patch
+patch 2952-drm-amdgpu-powerplay-add-arcturus-ppt-functions-1-2-.patch
+patch 2953-drm-amdgpu-powerplay-add-smu11-driver-interface-for-.patch
+patch 2954-drm-amd-powerplay-get-smc-firmware-and-pptable.patch
+patch 2955-drm-amdgpu-skip-get-update-xgmi-topology-info-when-n.patch
+patch 2956-drm-amdgpu-set-system-aperture-to-cover-whole-FB-reg.patch
+patch 2957-drm-amdgpu-correct-ip-for-mmHDP_READ_CACHE_INVALIDAT.patch
+patch 2958-drm-amdkfd-Set-number-of-xgmi-optimized-SDMA-engines.patch
+patch 2959-drm-amdgpu-add-clientID-for-2nd-vcn-instance.patch
+patch 2960-drm-amdgpu-add-ucodeID-for-2nd-vcn-instance.patch
+patch 2961-drm-amdgpu-add-doorbell-assignment-for-2nd-vcn-insta.patch
+patch 2962-drm-amdgpu-increase-AMDGPU_MAX_RINGS-to-add-2nd-vcn-.patch
+patch 2963-drm-amdgpu-add-vcn-nbio-doorbell-range-setting-for-2.patch
+patch 2964-drm-amdgpu-modify-amdgpu_vcn-to-support-multiple-ins.patch
+patch 2965-drm-amdgpu-add-multiple-instances-support-for-Arctur.patch
+patch 2966-drm-amdgpu-add-harvest-support-for-Arcturus.patch
+patch 2967-drm-amdgpu-assign-fb_start-end-in-mmhub-v9.4-interfa.patch
+patch 2968-drm-amdgpu-add-pci-DID-for-Arcturus-GL-XL.patch
+patch 2969-drm-amdgpu-add-arct-sdma-golden-settings.patch
+patch 2970-drm-amdgpu-add-arct-gc-golden-settings.patch
+patch 2971-drm-amdgpu-init-arct-external-rev-id.patch
+patch 2972-drm-amdgpu-keep-stolen-memory-for-arct.patch
+patch 2973-drm-amdgpu-init-gds-config-for-arct.patch
+patch 2974-drm-amdgpu-clean-up-nonexistent-firmware-declaration.patch
+patch 2975-amd-powerplay-No-SW-XGMI-dpm-for-Arcturus-rev-2.patch
+patch 2976-drm-amdkfd-Add-arcturus-CWSR-trap-handler.patch
+patch 2977-drm-amdgpu-skip-gfx-9-common-golden-settings-for-arc.patch
+patch 2978-drm-amdgpu-limit-sdma-instances-to-2-for-Arcturus-in.patch
+patch 2979-drm-amdkfd-Add-device-id-for-real-asics.patch
+patch 2980-drm-amdgpu-Add-more-detail-to-the-VM-fault-printing.patch
+patch 2981-drm-amdkfd-Merge-gfx9-arcturus-trap-handlers-add-ACC.patch
+patch 2982-drm-amdgpu-enable-all-8-sdma-instances-for-Arcturus-.patch
+patch 2983-drm-amdkfd-Increase-vcrat-size-for-GPU.patch
+patch 2984-drm-amdgpu-add-all-VCN-rings-into-schedule-request-q.patch
+patch 2985-drm-amdgpu-drop-unused-function-definitions.patch
+patch 2986-drm-amdgpu-Fix-silent-amdgpu_bo_move-failures.patch
+patch 2987-drm-amd-powerplay-fix-memory-allocation-failure-chec.patch
+patch 2988-drm-amd-powerplay-avoid-access-before-allocation.patch
+patch 2989-drm-amd-powerplay-fix-deadlock-around-smu_handle_tas.patch
+patch 2990-drm-amd-powerplay-correct-SW-SMU-valid-mapping-check.patch
+patch 2991-drm-amd-powerplay-input-check-for-unsupported-messag.patch
+patch 2992-drm-amd-powerplay-correct-smu_update_table-usage.patch
+patch 2993-drm-amd-powerplay-maintain-SMU-FW-backward-compatibi.patch
+patch 2994-drm-amd-powerplay-update-vega20-driver-if-to-fit-lat.patch
+patch 2995-drm-amd-amdgpu-Fix-offset-for-vmid-selection-in-debu.patch
+patch 2996-drm-amdkfd-Remove-GWS-from-process-during-uninit.patch
+patch 2997-drm-amdgpu-exposing-fica-registers-to-df-offsets.patch
+patch 2998-drm-amdgpu-Default-disable-GDS-for-compute-VMIDs.patch
+patch 2999-drm-amdgpu-Add-navi10-kfd-support-for-amdgpu-v3.patch
+patch 3000-drm-amd-powerplay-change-sysfs-pp_dpm_xxx-format-for.patch
+patch 3001-drm-amdgpu-do-not-create-ras-debugfs-sysfs-node-for-.patch
+patch 3002-drm-amdgpu-disable-GFX-RAS-by-default.patch
+patch 3003-drm-amdgpu-only-allow-error-injection-to-UMC-IP-bloc.patch
+patch 3004-drm-amdgpu-drop-ras-self-test.patch
+patch 3005-drm-amd-powerplay-custom-peak-clock-freq-for-navi10.patch
+patch 3006-drm-amd-powerplay-remove-redundancy-debug-log-in-smu.patch
+patch 3007-drm-amdgpu-set-sdma-irq-src-num-according-to-sdma-in.patch
+patch 3008-drm-amd-powerplay-report-bootup-clock-as-max-support.patch
+patch 3009-drm-amd-display-initialize-p_state-to-proper-value.patch
+patch 3010-drm-amd-display-Add-ability-to-set-preferred-link-tr.patch
+patch 3011-drm-amd-display-3.2.36.patch
+patch 3012-drm-amd-display-fix-up-HUBBUB-hw-programming-for-VM.patch
+patch 3013-drm-amd-display-fix-dsc-disable.patch
+patch 3014-drm-amd-display-3.2.37.patch
+patch 3015-drm-amd-display-move-bw-calc-code-into-helpers.patch
+patch 3016-drm-amd-display-cap-DCFCLK-hardmin-to-507-for-NV10.patch
+patch 3017-drm-amd-display-No-audio-endpoint-for-Dell-MST-displ.patch
+patch 3018-drm-amd-display-Add-aux-tracing-log-in-dce.patch
+patch 3019-drm-amd-display-Update-drm_dsc-to-reflect-native-4.2.patch
+patch 3020-drm-amd-display-early-return-when-pipe_cnt-is-0-in-b.patch
+patch 3021-drm-amd-display-Set-default-block_size-even-in-unexp.patch
+patch 3022-drm-amd-display-Set-one-4-2-0-related-PPS-field-as-r.patch
+patch 3023-drm-amd-display-swap-system-aperture-high-low.patch
+patch 3024-drm-amd-display-skip-retrain-in-dc_link_set_preferre.patch
+patch 3025-drm-amd-display-Split-out-common-HUBP-registers-and-.patch
+patch 3026-drm-amd-display-3.2.38.patch
+patch 3027-drm-amd-display-Incorrect-Read-Interval-Time-For-CR-.patch
+patch 3028-drm-amd-display-Clock-does-not-lower-in-Updateplanes.patch
+patch 3029-drm-amd-display-Copy-max_clks_by_state-after-dce_clk.patch
+patch 3030-drm-amd-display-Use-Pixel-clock-in-100Hz-units-for-H.patch
+patch 3031-drm-amd-display-wait-for-the-whole-frame-after-globa.patch
+patch 3032-drm-amd-display-refactor-dump_clk_registers.patch
+patch 3033-drm-amd-display-add-hdmi2.1-dsc-pps-packet-programmi.patch
+patch 3034-drm-amd-display-add-monitor-patch-to-add-T7-delay.patch
+patch 3035-drm-amd-display-Poll-for-GPUVM-context-ready.patch
+patch 3036-drm-amd-display-dc-fix-TRANSMITTER_UNIPHY_G-offset.patch
+patch 3037-drm-amd-display-add-functionality-to-grab-DPRX-CRC-e.patch
+patch 3038-drm-amd-display-add-functionality-to-get-pipe-CRC-so.patch
+patch 3039-drm-amd-display-Wait-for-backlight-programming-compl.patch
+patch 3040-drm-amd-display-3.2.39.patch
+patch 3041-drm-amd-display-Expose-enc2_set_dynamic_metadata.patch
+patch 3042-drm-amd-display-Check-for-valid-stream_encode.patch
+patch 3043-drm-amd-display-Fix-some-HUBP-programming-issues.patch
+patch 3044-drm-amd-display-Read-max-down-spread.patch
+patch 3045-drm-amd-display-Remove-dsc-disable_ich-flag-programm.patch
+patch 3046-drm-amd-display-Power-gate-all-DSCs-at-driver-init-t.patch
+patch 3047-drm-amd-display-Disable-Audio-on-reinitialize-hardwa.patch
+patch 3048-drm-amd-display-fix-DMCU-hang-when-going-into-Modern.patch
+patch 3049-drm-amd-display-Do-not-fill-Null-packet-in-the-blank.patch
+patch 3050-drm-amd-display-Remove-unnecessary-NULL-check-in-set.patch
+patch 3051-drm-amd-display-use-encoder-s-engine-id-to-find-matc.patch
+patch 3052-drm-amd-display-fix-not-calling-ppsmu-to-trigger-PME.patch
+patch 3053-drm-amd-display-Change-min_h_sync_width-from-8-to-4.patch
+patch 3054-drm-amd-display-Remove-second-initialization-of-pp_s.patch
+patch 3055-drm-amd-display-3.2.40.patch
+patch 3056-drm-amd-display-Wait-for-flip-to-complete.patch
+patch 3057-drm-amd-display-Implement-generic-MUX-registers.patch
+patch 3058-drm-amd-display-Use-helper-for-determining-HDMI-sign.patch
+patch 3059-drm-amd-display-Set-FEC_READY-always-before-link-tra.patch
+patch 3060-drm-amd-display-put-back-front-end-initialization-se.patch
+patch 3061-drm-amd-display-Optimize-gamma-calculations.patch
+patch 3062-drm-amd-display-Clear-FEC_READY-shadow-register-if-D.patch
+patch 3063-drm-amd-display-Add-debug-option-to-disable-timing-s.patch
+patch 3064-drm-amd-display-Add-MPC-3DLUT-resource-management.patch
+patch 3065-drm-amd-display-Add-CM_BYPASS-via-debug-option.patch
+patch 3066-drm-amd-display-Add-DIG_CLOCK_PATTERN-register.patch
+patch 3067-drm-amd-display-Cache-the-use_pitch_c-conditional.patch
+patch 3068-drm-amd-display-Fixes-for-some-MPO-cases.patch
+patch 3069-drm-amd-display-3.2.41.patch
+patch 3070-drm-amd-display-Hook-up-calls-to-do-stereo-mux-and-d.patch
+patch 3071-drm-amd-display-allocate-4-ddc-engines-for-RV2.patch
+patch 3072-drm-amd-display-add-set-and-get-clock-for-testing-pu.patch
+patch 3073-drm-amd-display-Change-offset_to_id-to-reflect-what-.patch
+patch 3074-drm-amd-display-init-res_pool-dccg_ref-dchub_ref-wit.patch
+patch 3075-drm-amd-display-add-a-option-to-force-the-clock-at-e.patch
+patch 3076-drm-amd-display-use-min-disp-and-dpp-clk-debug-optio.patch
+patch 3077-drm-amd-display-add-pipe-CRC-sources-without-disabli.patch
+patch 3078-drm-amd-display-Implement-DAL3-GPU-Integer-Scaling.patch
+patch 3079-drm-amd-display-add-dcc-programming-for-dual-plane.patch
+patch 3080-drm-amd-display-populate-last-calculated-bb-state-wi.patch
+patch 3081-drm-amd-display-Fix-dc_create-failure-handling-and-6.patch
+patch 3082-drm-amd-display-Only-enable-audio-if-speaker-allocat.patch
+patch 3083-drm-amd-display-Clean-up-dynamic-metadata-logic.patch
+patch 3084-drm-amd-display-Set-enabled-to-false-at-start-of-aud.patch
+patch 3085-drm-amd-display-drop-ASSERT-if-eDP-panel-is-not-conn.patch
+patch 3086-drm-amd-display-3.2.42.patch
+patch 3087-drm-amd-display-Increase-size-of-audios-array.patch
+patch 3088-drm-amd-display-do-not-read-link-setting-if-edp-not-.patch
+patch 3089-drm-amd-display-fix-mpcc-assert-condition.patch
+patch 3090-drm-amd-display-support-dummy-pstate.patch
+patch 3091-drm-amd-display-Add-SMU-version-field-to-clk_mgr_int.patch
+patch 3092-drm-amd-display-avoid-power-gate-domains-that-doesn-.patch
+patch 3093-drm-amd-display-Add-debug-entry-to-destroy-disconnec.patch
+patch 3094-drm-amd-display-Copy-GSL-groups-when-committing-a-ne.patch
+patch 3095-drm-amd-display-handle-active-dongle-port-type-is-DP.patch
+patch 3096-drm-ttm-use-the-same-attributes-when-freeing-d_page-.patch
+patch 3097-drm-amdgpu-use-VCN-firmware-offset-for-cache-window.patch
+patch 3098-drm-amdgpu-pm-remove-check-for-pp-funcs-in-freq-sysf.patch
+patch 3099-drm-amd-display-Force-uclk-to-max-for-every-state.patch
+patch 3100-drm-amdgpu-Remove-undefined-amdgpu_device_parse_fake.patch
+patch 3101-drm-amdgpu-smu-move-fan-rpm-query-into-the-asic-spec.patch
+patch 3102-drm-amdkfd-Fix-sdma_bitmap-overflow-issue.patch
+patch 3103-drm-amdkfd-Fix-missing-break-in-switch-statement.patch
+patch 3104-drm-amdgpu-gfx10-Fix-missing-break-in-switch-stateme.patch
+patch 3105-drm-amdkfd-kfd_mqd_manager_v10-Avoid-fall-through-wa.patch
+patch 3106-drm-amd-powerplay-add-callback-function-of-get_therm.patch
+patch 3107-drm-amdkfd-Fix-byte-align-on-VegaM.patch
+patch 3108-drm-amd-display-readd-msse2-to-prevent-Clang-from-em.patch
+patch 3109-drm-amdgpu-Use-dev_get_drvdata-where-possible.patch
+patch 3110-drm-amd-display-Use-dev_get_drvdata.patch
+patch 3111-drm-amd-display-fix-a-missing-null-check-on-a-failed.patch
+patch 3112-amd-amdgpu-Enable-debug-vmid-trap-mask.patch
+patch 3113-drm-amdgpu-use-VCN-firmware-offset-for-cache-window.patch
+patch 3114-drm-amd-powerplay-no-pptable-transfer-and-dpms-enabl.patch
+patch 3115-drm-amd-powerplay-some-cosmetic-fixes.patch
+patch 3116-drm-amd-powerplay-fix-temperature-granularity-error-.patch
+patch 3117-drm-amdgpu-gmc10-fix-pte-mytpe-field-error-for-navi1.patch
+patch 3118-drm-amdkfd-Fix-lost-single-step-exceptions-in-gfx9-t.patch
+patch 3119-drm-amdkfd-Replace-gfx10-trap-handler-with-correct-b.patch
+patch 3120-drm-amdkfd-Remove-dead-code-from-gfx8-gfx9-trap-hand.patch
+patch 3121-drm-amdgpu-add-perfmon-and-fica-atomics-for-df.patch
+patch 3122-drm-amdgpu-Fix-hard-hang-for-S-G-display-BOs.patch
+patch 3123-drm-amdgpu-Create-helper-to-clear-AMDGPU_GEM_CREATE_.patch
+patch 3124-drm-amdgpu-Add-check-for-USWC-support-for-amdgpu_dis.patch
+patch 3125-drm-amd-display-enable-S-G-for-RAVEN-chip.patch
+patch 3126-drm-amd-powerplay-minor-fixes-around-SW-SMU-power-an.patch
+patch 3127-drm-amd-powerplay-fix-null-pointer-dereference-aroun.patch
+patch 3128-drm-amd-powerplay-enable-SW-SMU-reset-functionality.patch
+patch 3129-drm-amdgpu-add-an-asic-callback-to-determine-the-res.patch
+patch 3130-drm-amdgpu-add-reset_method-asic-callback-for-si.patch
+patch 3131-drm-amdgpu-add-reset_method-asic-callback-for-cik.patch
+patch 3132-drm-amdgpu-add-reset_method-asic-callback-for-vi.patch
+patch 3133-drm-amdgpu-add-reset_method-asic-callback-for-soc15.patch
+patch 3134-drm-amdgpu-add-reset_method-asic-callback-for-navi.patch
+patch 3135-drm-amdgpu-powerplay-add-a-new-interface-to-set-the-.patch
+patch 3136-drm-amdgpu-powerplay-add-set_mp1_state-for-vega20.patch
+patch 3137-drm-amdgpu-powerplay-add-set_mp1_state-for-vega10.patch
+patch 3138-drm-amdgpu-powerplay-add-set_mp1_state-for-vega12.patch
+patch 3139-drm-amdgpu-put-the-SMC-into-the-proper-state-on-rese.patch
+patch 3140-drm-amdgpu-powerplay-use-proper-revision-id-for-navi.patch
+patch 3141-drm-amdgpu-Fix-amdgpu_display_supported_domains-logi.patch
+patch 3142-drm-amd-amdgpu-vcn_v2_0-Mark-RB-commands-as-KMD-comm.patch
+patch 3143-drm-amdkfd-Fill-the-name-field-in-node-topology-with.patch
+patch 3144-drm-amdgpu-Default-disable-GDS-for-compute-gfx.patch
+patch 3145-drm-amd-powerplay-move-smu-types-to-smu_types.h.patch
+patch 3146-drm-amd-powerplay-add-smu-message-name-support.patch
+patch 3147-drm-amd-powerplay-add-smu-feature-name-support.patch
+patch 3148-drm-amd-powerplay-move-smu_feature_update_enable_sta.patch
+patch 3149-drm-amd-powerplay-implment-sysfs-feature-status-func.patch
+patch 3150-drm-amdgpu-gfx10-update-golden-settings-for-navi14.patch
+patch 3151-drm-amd-amdgpu-vcn_v2_0-Move-VCN-2.0-specific-dec-ri.patch
+patch 3152-drm-amdgpu-powerplay-provide-the-interface-to-disabl.patch
+patch 3153-drm-syncobj-fix-leaking-dma_fence-in-drm_syncobj_que.patch
+patch 3154-drm-amdgpu-fix-error-handling-in-amdgpu_cs_process_f.patch
+patch 3155-dma-buf-add-dma_fence_chain_for_each_unwrap-helper.patch
+patch 3156-dma-buf-add-dma_fence_chain_remove_fence.patch
+patch 3157-drm-amdgpu-fix-a-potential-information-leaking-bug.patch
+patch 3158-Revert-accidential-push.patch
+patch 3159-drm-amd-display-Embed-DCN2-SOC-bounding-box.patch
+patch 3160-drm-amd-display-Support-uclk-switching-for-DCN2.patch
+patch 3161-drm-amdkfd-Fix-gfx10-wave64-VGPR-context-restore.patch
+patch 3162-drm-amdkfd-Save-restore-flat_scratch_lo-hi-on-gfx10.patch
+patch 3163-drm-amdkfd-Save-restore-vcc-on-gfx10.patch
+patch 3164-drm-amdkfd-kfd_events-SIGUSR2-interrupt-changes.patch
+patch 3165-drm-amd-powerplay-add-smcdpminfo-table-v4_6-support.patch
+patch 3166-drm-amd-powerplay-add-SW-SMU-interface-for-dumping-p.patch
+patch 3167-drm-amd-powerplay-update-smu11_driver_if_arcturus.h.patch
+patch 3168-drm-amd-powerplay-update-arcturus_ppsmc.h.patch
+patch 3169-drm-amd-powerplay-update-arcturus_ppt.c-h-V3.patch
+patch 3170-drm-amd-powerplay-enable-SW-SMU-routine-support-for-.patch
+patch 3171-drm-amd-powerplay-initialize-arcturus-MP1-and-THM-ba.patch
+patch 3172-drm-amd-powerplay-enable-arcturus-powerplay.patch
+patch 3173-drm-amdgpu-correct-VCN-powergate-routine-for-acturus.patch
+patch 3174-drm-amd-powerplay-hold-on-the-arcturus-gfx-dpm-suppo.patch
+patch 3175-drm-amd-include-adjust-base-offset-of-SMUIO-and-THM-.patch
+patch 3176-drm-amdgpu-update-more-sdma-instances-irq-support.patch
+patch 3177-drm-amd-powerplay-add-new-sensor-type-for-VCN-powerg.patch
+patch 3178-drm-amd-powerplay-support-VCN-powergate-status-retri.patch
+patch 3179-drm-amd-powerplay-support-VCN-powergate-status-retri.patch
+patch 3180-drm-amd-powerplay-correct-Navi10-VCN-powergate-contr.patch
+patch 3181-drm-amd-powerplay-correct-UVD-VCE-VCN-power-status-r.patch
+patch 3182-drm-amd-powerplay-init-arcturus-SMU-metrics-table-on.patch
+patch 3183-drm-amd-powerplay-support-sensor-reading-on-arcturus.patch
+patch 3184-drm-amd-powerplay-support-real-time-clock-retrieval-.patch
+patch 3185-drm-amd-powerplay-support-fan-speed-retrieval-on-arc.patch
+patch 3186-drm-amd-powerplay-add-missing-arcturus-feature-maps.patch
+patch 3187-drm-amd-powerplay-correct-the-bitmask-used-in-arctur.patch
+patch 3188-drm-amd-powerplay-fix-arcturus-real-time-clock-frequ.patch
+patch 3189-drm-amd-powerplay-support-UMD-PSTATE-settings-on-arc.patch
+patch 3190-drm-amd-powerplay-correct-arcturus-current-clock-lev.patch
+patch 3191-drm-amd-powerplay-make-power-limit-retrieval-as-asic.patch
+patch 3192-drm-amdgpu-correct-irq-type-used-for-sdma-ecc.patch
+patch 3193-drm-amd-powerplay-determine-the-features-to-enable-b.patch
+patch 3194-drm-amdgpu-powerplay-return-success-if-set_mp1_state.patch
+patch 3195-drm-amdgpu-move-some-ras-data-structure-to-amdgpu_ra.patch
+patch 3196-drm-amdgpu-init-RSMU-and-UMC-ip-base-address-for-veg.patch
+patch 3197-drm-amdgpu-add-amdgpu_umc_functions-structure.patch
+patch 3198-drm-amdgpu-add-rsmu-v_0_0_2-ip-headers.patch
+patch 3199-drm-amdgpu-add-umc-v6_1_1-IP-headers.patch
+patch 3200-drm-amdgpu-add-umc-v6_1-query-error-count-support.patch
+patch 3201-drm-amdgpu-init-umc-v6_1-functions-for-vega20.patch
+patch 3202-drm-amdgpu-querry-umc-error-count.patch
+patch 3203-drm-amdgpu-add-ras-error-count-after-each-query-v2.patch
+patch 3204-drm-amdgpu-add-RREG64-WREG64-_PCIE-operations.patch
+patch 3205-drm-amdgpu-use-64bit-operation-macros-for-umc.patch
+patch 3206-drm-amdgpu-switch-to-amdgpu_umc-structure.patch
+patch 3207-drm-amdgpu-update-algorithm-of-umc-uncorrectable-err.patch
+patch 3208-drm-amdgpu-add-support-for-recording-ras-error-addre.patch
+patch 3209-drm-amdgpu-add-structures-for-umc-error-address-tran.patch
+patch 3210-drm-amdgpu-query-umc-ras-error-address.patch
+patch 3211-drm-amdgpu-allow-ras-interrupt-callback-to-return-er.patch
+patch 3212-drm-amdgpu-update-interrupt-callback-for-all-ras-cli.patch
+patch 3213-drm-amdgpu-add-check-for-ras-error-type.patch
+patch 3214-drm-amdgpu-remove-ras_reserve_vram-in-ras-injection.patch
+patch 3215-drm-amd-include-add-bitfield-define-for-EDC-register.patch
+patch 3216-drm-amd-include-add-define-of-TCP_EDC_CNT_NEW.patch
+patch 3217-drm-amdgpu-add-define-for-gfx-ras-subblock.patch
+patch 3218-drm-amdgpu-add-RAS-callback-for-gfx.patch
+patch 3219-drm-amdgpu-support-gfx-ras-error-injection-and-err_c.patch
+patch 3220-drm-amdgpu-disable-inject-for-failed-subblocks-of-gf.patch
+patch 3221-drm-amdkfd-enable-KFD-support-for-navi14.patch
+patch 3222-drm-amd-powerplay-sort-feature-status-index-by-asic-.patch
+patch 3223-drm-amdgpu-cleanup-vega10-SRIOV-code-path.patch
+patch 3224-drm-amdgpu-fix-incorrect-judge-on-sos-fw-version.patch
+patch 3225-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch
+patch 3226-drm-amd-display-Use-proper-enum-conversion-functions.patch
+patch 3227-drm-amd-display-Use-switch-table-for-dc_to_smu_clock.patch
+patch 3228-drm-ttm-Add-release_notify-callback-to-ttm_bo_driver.patch
+patch 3229-drm-amdgpu-Add-flag-to-wipe-VRAM-on-release.patch
+patch 3230-drm-amdgpu-Implement-VRAM-wipe-on-release.patch
+patch 3231-drm-amdgpu-Add-amdgpu_asic_funcs.reset_method-for-Ve.patch
+patch 3232-drm-amdgpu-Update-NBIO-headers-to-add-TXCLK3-4.patch
+patch 3233-drm-amdgpu-Fix-pcie_bw-on-Vega20.patch
+patch 3234-drm-amdgpu-support-get_cu_info-for-Arcturus.patch
+patch 3235-drm-amdkfd-Extend-CU-mask-to-8-SEs-v3.patch
+patch 3236-drm-amd-powerplay-fix-off-by-one-upper-bounds-limit-.patch
+patch 3237-drm-amd-powerplay-fix-a-few-spelling-mistakes.patch
+patch 3238-drm-amd-powerplay-Allow-changing-of-fan_control-in-s.patch
+patch 3239-drm-amdgpu-fix-unsigned-variable-instance-compared-t.patch
+patch 3240-drm-amd-display-Allow-cursor-async-updates-for-frame.patch
+patch 3241-drm-amd-display-Skip-determining-update-type-for-asy.patch
+patch 3242-drm-amd-display-Don-t-replace-the-dc_state-for-fast-.patch
+patch 3243-drm-amd-powerplay-correct-navi10-vcn-powergate.patch
+patch 3244-drm-amd-powerplay-honor-hw-limit-on-fetching-metrics.patch
+patch 3245-drm-amdgpu-remove-the-clear-of-MCA_ADDR.patch
+patch 3246-drm-amdgpu-add-more-parameters-and-functions-to-amdg.patch
+patch 3247-drm-amdgpu-initialize-new-parameters-and-functions-f.patch
+patch 3248-drm-amdgpu-add-macro-of-umc-for-each-channel.patch
+patch 3249-drm-amdgpu-apply-umc_for_each_channel-macro-to-umc_6.patch
+patch 3250-drm-amdgpu-add-error-address-query-for-umc-ras.patch
+patch 3251-drm-amdgpu-support-ce-interrupt-in-ras-module.patch
+patch 3252-drm-amdgpu-implement-umc-ras-init-function.patch
+patch 3253-drm-amdgpu-update-the-calc-algorithm-of-umc-ecc-erro.patch
+patch 3254-drm-amdgpu-only-uncorrectable-error-needs-gpu-reset.patch
+patch 3255-drm-amdgpu-replace-AMDGPU_RAS_UE-with-AMDGPU_RAS_SUC.patch
+patch 3256-drm-amd-powerplay-guard-consistency-between-CPU-copy.patch
+patch 3257-drm-amd-powerplay-support-power-profile-retrieval-an.patch
+patch 3258-drm-amd-powerplay-enable-SW-SMU-power-profile-switch.patch
+patch 3259-drm-amdgpu-removed-duplicate-line.patch
+patch 3260-drm-amdgpu-add-PSP-SW-init-support-for-Arcturus.patch
+patch 3261-drm-amdgpu-add-PSP-KDB-loading-support-for-Arcturus.patch
+patch 3262-drm-amdgpu-update-PSP-CMD-fail-response-status-print.patch
+patch 3263-drm-amdgpu-disable-MEC2-JT-context-init-for-Arcturus.patch
+patch 3264-drm-amdgpu-extend-PSP-FW-loading-support-to-8-SDMA-i.patch
+patch 3265-drm-amdgpu-update-SDMA-V4-microcode-init.patch
+patch 3266-drm-amdgpu-add-ip-offset-header-for-navi12-v2.patch
+patch 3267-drm-amdgpu-initialize-reg-base-for-navi12.patch
+patch 3268-drm-amdgpu-add-navi12-asic-type.patch
+patch 3269-drm-amdgpu-add-gpu_info-firmware-for-navi12.patch
+patch 3270-drm-amdgpu-set-asic-family-and-ip-blocks-for-navi12.patch
+patch 3271-drm-amdgpu-use-front-door-firmware-loading-for-navi1.patch
+patch 3272-drm-amdgpu-initialize-cg-pg-flags-and-external-rev-i.patch
+patch 3273-drm-amdgpu-set-nbio-hdp-cg-for-navi12.patch
+patch 3274-drm-amdgpu-gfx10-set-gfx-cg-for-navi12.patch
+patch 3275-drm-amdgpu-gfx10-add-gfx-config-for-navi12.patch
+patch 3276-drm-amdgpu-gfx10-declare-cp-rlc-firmwares-for-navi12.patch
+patch 3277-drm-amdgpu-gfx10-add-placeholder-for-navi12-golden-s.patch
+patch 3278-drm-amdgpu-gfx10-set-number-of-me-c-pipe-queue-for-n.patch
+patch 3279-drm-amdgpu-gfx10-set-rlc-funcs-for-navi12.patch
+patch 3280-drm-amdgpu-sdma5-declare-sdma-firmwares-for-navi12.patch
+patch 3281-drm-amdgpu-sdma5-add-placeholder-for-navi12-golden-s.patch
+patch 3282-drm-amdgpu-gmc10-set-gart-size-and-vm-size-for-navi1.patch
+patch 3283-drm-amdgpu-add-ip-blocks-for-navi12.patch
+patch 3284-drm-amdgpu-gfx10-set-tcp-harvest-for-navi12.patch
+patch 3285-drm-amdgpu-enable-virtual-display-for-navi12.patch
+patch 3286-drm-amdgpu-gfx10-add-golden-settings-for-navi12-v2.patch
+patch 3287-drm-amdgpu-sdma5-add-golden-settings-for-navi12-v2.patch
+patch 3288-drm-amdgpu-add-CGTT_GS_NGG_CLK_CTRL-register-to-gc-h.patch
+patch 3289-drm-amdgpu-correct-smu-rlc-handshake-enablement-bit.patch
+patch 3290-drm-amdgpu-smu11-add-smu-support-for-navi12.patch
+patch 3291-drm-amdgpu-psp11-add-psp-support-for-navi12.patch
+patch 3292-drm-amdgpu-start-autoload-till-RLCG-fw-for-navi12.patch
+patch 3293-drm-amdgpu-add-smu-ip-block-for-navi12.patch
+patch 3294-drm-amdgpu-add-psp-ip-block-for-navi12.patch
+patch 3295-drm-amdgpu-add-Navi12-VCN-firmware-support.patch
+patch 3296-drm-amdgpu-add-VCN-ip-block-for-Navi12.patch
+patch 3297-drm-amdgpu-enable-DPG-mode-for-Navi12.patch
+patch 3298-drm-amd-display-Add-ASICREV_IS_NAVI-macros.patch
+patch 3299-drm-amdgpu-Add-nv12-DC-ip-block.patch
+patch 3300-drm-amd-display-Add-missing-NV12-asic-IDs.patch
+patch 3301-drm-amdgpu-enable-Navi12-kfd-support-for-amdgpu.patch
+patch 3302-drm-amd-display-Validate-dc_plane_info-and-dc_plane_.patch
+patch 3303-drm-amd-display-Block-immediate-flips-for-non-fast-u.patch
+patch 3304-Revert-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch
+patch 3305-Revert-drm-amd-powerplay-honor-hw-limit-on-fetching-.patch
+patch 3306-drm-amd-powerplay-skip-pcie-params-override-on-Arctu.patch
+patch 3307-drm-amdkfd-fix-missing-break-in-kfd2kgd-pointer-init.patch
+patch 3308-drm-amd-powerplay-remove-redundancy-debug-log-in-smu.patch
+patch 3309-drm-amdgpu-pin-the-csb-buffer-on-hw-init-for-gfx-v8.patch
+patch 3310-drm-amdgpu-Fix-panic-during-gpu-reset.patch
+patch 3311-drm-amdgpu-update-ras-sysfs-feature-info.patch
+patch 3312-drm-amdgpu-soc15-fix-external_rev_id-for-navi14.patch
+patch 3313-drm-amdgpu-discovery-move-common-discovery-code-out-.patch
+patch 3314-drm-amd-powerplay-check-before-issuing-messages-for-.patch
+patch 3315-drm-amdgpu-Fix-GPU-reset-crash-regression.patch
+patch 3316-MAINTAINERS-update-amdkfd-maintainer-v3.patch
+patch 3317-drm-amd-powerplay-Zero-initialize-some-variables.patch
+patch 3318-gpu-drm-amd-powerplay-Remove-logically-dead-code.patch
+patch 3319-drm-amdkfd-Remove-GPU-ID-in-GWS-queue-creation.patch
+patch 3320-drm-amdgpu-Mark-KFD-VRAM-allocations-for-wipe-on-rel.patch
+patch 3321-drm-amdgpu-enable-gfx-clock-gating-for-Arcturus.patch
+patch 3322-drm-amdgpu-add-hdp-clock-gating-for-Arcturus.patch
+patch 3323-drm-amdgpu-enable-hdp-clock-gating-for-Arcturus.patch
+patch 3324-drm-amdgpu-support-sdma-clock-gating-for-more-instan.patch
+patch 3325-drm-amdgpu-add-sdma-clock-gating-for-Arcturus.patch
+patch 3326-drm-amdgpu-enable-sdma-clock-gating-for-Arcturus.patch
+patch 3327-drm-amdgpu-split-athub-clock-gating-from-mmhub.patch
+patch 3328-drm-amdgpu-add-GFX_CP_LS-flag-to-Arcturus.patch
+patch 3329-drm-amdgpu-increase-CGCG-gfx-idle-threshold-for-Arct.patch
+patch 3330-drm-amdgpu-add-mmhub-clock-gating-for-Arcturus.patch
+patch 3331-drm-amdgpu-enable-mmhub-clock-gating-for-Arcturus.patch
+patch 3332-drm-amdgpu-add-gfx-clock-gating-for-Arcturus.patch
+patch 3333-drm-amdgpu-replace-readq-writeq-with-atomic64-operat.patch
+patch 3334-drm-amdgpu-enable-gfx-clock-gatings-for-navi12.patch
+patch 3335-drm-amdgpu-enable-hdp-clock-gating-for-navi12.patch
+patch 3336-drm-amdgpu-sdma5-set-sdma-clock-gating-for-navi12.patch
+patch 3337-drm-amdgpu-enable-sdma-clock-gating-for-navi12.patch
+patch 3338-drm-amdgpu-mmhub2-set-clock-gating-for-navi12.patch
+patch 3339-drm-amdgpu-enable-mmhub-clock-gating-for-navi12.patch
+patch 3340-drm-amdgpu-enable-ih-clock-gating-for-navi12.patch
+patch 3341-drm-amdgpu-athub2-set-clock-gating-for-navi12.patch
+patch 3342-drm-amdgpu-enable-athub-clock-gating-for-navi12.patch
+patch 3343-drm-amdgpu-enable-vcn-clock-gating-for-navi12.patch
+patch 3344-drm-amd-display-Remove-drm_dsc_dc.c.patch
+patch 3345-drm-amdgpu-Update-pitch-on-page-flips-without-DC-as-.patch
+patch 3346-drm-dp-Use-non-cyclic-idr.patch
+patch 3347-drm-amd-display-Use-connector-kdev-as-aux-device-par.patch
+patch 3348-drm-amd-display-Implement-MST-Aux-device-registratio.patch
+patch 3349-drm-amdgpu-add-navi14-PCI-ID.patch
+patch 3350-drm-amd-powerplay-re-define-smu-interface-version-fo.patch
+patch 3351-drm-amdgpu-add-check-to-avoid-array-bound-issue.patch
+patch 3352-drm-amdgpu-add-sub-block-parameter-in-ras-inject-com.patch
+patch 3353-drm-amdgpu-fix-transform-feedback-GDS-hang-on-gfx10-.patch
+patch 3354-drm-amdgpu-handle-AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_.patch
+patch 3355-Revert-drm-amdgpu-fix-transform-feedback-GDS-hang-on.patch
+patch 3356-drm-amdgpu-add-amdgpu_mmhub_funcs-definition.patch
+patch 3357-drm-amdgpu-support-mmhub-ras-in-amdgpu-ras.patch
+patch 3358-drm-amdgpu-create-mmhub-ras-framework.patch
+patch 3359-drm-amd-powerplay-change-smu_read_sensor-sequence-in.patch
+patch 3360-drm-amdgpu-implement-UMC-64-bits-REG-operations.patch
+patch 3361-drm-amdgpu-remove-RREG64-WREG64.patch
+patch 3362-drm-amdgpu-remove-ras-block-s-feature-status-info-in.patch
+patch 3363-drm-amdgpu-powerplay-update-Arcturus-smu-version-in-.patch
+patch 3364-drm-amd-powerplay-honor-hw-limit-on-fetching-metrics.patch
+patch 3365-drm-amdgpu-fix-gfx9-soft-recovery.patch
+patch 3366-drm-amd-display-use-kvmalloc-for-dc_state-v2.patch
+patch 3367-drm-amd-display-Fix-a-typo-dce_aduio_mask-dce_audio_.patch
+patch 3368-drm-amd-powerplay-remove-redundant-duplicated-return.patch
+patch 3369-drm-amdgpu-add-renoir-header-files-v2.patch
+patch 3370-drm-amdgpu-add-renoir-asic_type-enum.patch
+patch 3371-drm-amdgpu-add-renoir-support-for-gpu_info-and-ip-bl.patch
+patch 3372-drm-amdgpu-add-soc15-common-ip-block-support-for-ren.patch
+patch 3373-drm-amdgpu-add-gmc-v9-supports-for-renoir.patch
+patch 3374-drm-amdgpu-set-fw-load-type-for-renoir.patch
+patch 3375-drm-amdgpu-add-gfx-support-for-renoir.patch
+patch 3376-drm-amdgpu-add-sdma-support-for-renoir.patch
+patch 3377-drm-amdgpu-set-ip-blocks-for-renoir.patch
+patch 3378-drm-amdgpu-add-renoir-pci-id.patch
+patch 3379-drm-amdgpu-fix-no-interrupt-issue-for-renoir-emu.patch
+patch 3380-drm-amdgpu-enable-dce-virtual-ip-module-for-Renoir.patch
+patch 3381-drm-amdgpu-add-asic-funcs-for-renoir.patch
+patch 3382-drm-amdgpu-set-rlc-funcs-for-renoir.patch
+patch 3383-drm-amdgpu-add-psp_v12_0-for-renoir-v2.patch
+patch 3384-drm-amdgpu-add-gfx-golden-settings-for-renoir-v2.patch
+patch 3385-drm-amdgpu-add-sdma-golden-settings-for-renoir.patch
+patch 3386-drm-amdgpu-enable-Renoir-VCN-firmware-loading.patch
+patch 3387-drm-amdgpu-enable-Doorbell-support-for-Renoir-v2.patch
+patch 3388-drm-amdgpu-add-VCN2.0-to-Renoir-IP-blocks.patch
+patch 3389-drm-amdgpu-enable-clock-gating-for-renoir.patch
+patch 3390-drm-amdgpu-enable-power-gating-for-renoir.patch
+patch 3391-drm-amdgpu-update-lbpw-for-renoir.patch
+patch 3392-drm-amdgpu-set-fw-default-loading-by-psp-for-renoir.patch
+patch 3393-drm-amdgpu-skip-mec2-jump-table-loading-for-renoir.patch
+patch 3394-drm-amd-powerplay-remove-redundancy-debug-log-about-.patch
+patch 3395-drm-amd-powerplay-add-arcturus_is_dpm_running-functi.patch
+patch 3396-drm-amdkfd-Fill-amdgpu_task_info-for-KFD-VMs.patch
+patch 3397-drm-amd-display-reset-drr-programming-on-pipe-reset.patch
+patch 3398-drm-amd-display-reset-hdmi-tmds-rate-and-data-scramb.patch
+patch 3399-drm-amd-display-fix-issue-where-252-255-values-are-c.patch
+patch 3400-drm-amd-display-Fix-frames_to_insert-math.patch
+patch 3401-drm-amd-display-Add-22-24-and-26-degamma.patch
+patch 3402-drm-amd-display-Improve-sharing-of-HUBBUB-register-l.patch
+patch 3403-drm-amd-display-Synchronous-DisplayPort-Link-Trainin.patch
+patch 3404-drm-amd-display-make-firmware-info-only-load-once-du.patch
+patch 3405-drm-amd-display-fixup-DPP-programming-sequence.patch
+patch 3406-drm-amd-display-Add-work-around-option-to-skip-DCN20.patch
+patch 3407-drm-amd-display-refactor-gpio-to-allocate-hw_contain.patch
+patch 3408-drm-amd-display-wait-for-pending-complete-when-enabl.patch
+patch 3409-drm-amd-display-3.2.43.patch
+patch 3410-drm-amd-display-Make-init_hw-and-init_pipes-generic-.patch
+patch 3411-drm-amd-display-fix-dcn-specific-clk_mgr-init_clocks.patch
+patch 3412-drm-amd-display-enabling-seamless-boot-sequence-for-.patch
+patch 3413-drm-amd-display-clean-up-DML-for-DCN2x.patch
+patch 3414-drm-amd-display-Add-HLG-support-in-color-module.patch
+patch 3415-drm-amd-display-Change-DSC-policy-from-slices-per-co.patch
+patch 3416-drm-amd-display-Set-DSC-before-DIG-front-end-is-conn.patch
+patch 3417-drm-amd-display-3.2.44.patch
+patch 3418-drm-amd-display-fix-pipe-selection-logic-in-validate.patch
+patch 3419-drm-amd-display-Remove-duplicate-interface-for-progr.patch
+patch 3420-drm-amd-display-Update-DML-parameters.patch
+patch 3421-drm-amd-display-update-optc-odm-interface-for-more-t.patch
+patch 3422-drm-amd-display-HUBP-HUBBUB-register-programming-fix.patch
+patch 3423-drm-amd-display-Enable-type-C-hotplug.patch
+patch 3424-drm-amd-display-reprogram-VM-config-when-system-resu.patch
+patch 3425-drm-amd-display-Remove-4-2-2-DSC-support.patch
+patch 3426-drm-amd-display-Add-Logging-for-Gamma-Related-inform.patch
+patch 3427-drm-amd-display-Fix-type-of-ODMCombineType-field.patch
+patch 3428-drm-amd-display-Check-if-set_blank_data_double_buffe.patch
+patch 3429-drm-amd-display-Correct-DSC-PPS-log.patch
+patch 3430-drm-amd-display-wake-up-ogam-mem-pwr-before-programm.patch
+patch 3431-drm-amd-display-Register-VUPDATE_NO_LOCK-interrupts-.patch
+patch 3432-drm-amd-display-Add-enum-for-H-timing-divider-mode.patch
+patch 3433-drm-amd-display-Remove-redundant-definition-of-dwb_s.patch
+patch 3434-drm-amd-display-Add-Logging-for-Gamma-Related-inform.patch
+patch 3435-drm-amd-display-Add-and-refine-DSC-logs-in-enable-se.patch
+patch 3436-drm-amd-display-3.2.45.patch
+patch 3437-drm-amd-display-fix-dcn20-global-sync-dml-param-extr.patch
+patch 3438-drm-amd-display-3.2.46.patch
+patch 3439-drm-amd-display-enable-dcn_mem_pwr-as-golden-setting.patch
+patch 3440-drm-amd-display-check-hpd-before-retry-verify-link-c.patch
+patch 3441-drm-amd-display-audio-cannot-switch-to-internal-when.patch
+patch 3442-drm-amd-display-Enable-MPO-with-pre-blend-color-proc.patch
+patch 3443-drm-amd-display-Load-NV12-SOC-BB-from-firmware.patch
+patch 3444-drm-amdkfd-add-debug-notification.patch
+patch 3445-Revert-drm-amdkfd-add-debug-notification.patch
+patch 3446-drm-amd-powerplay-add-smu-if-version-for-navi12.patch
+patch 3447-drm-amd-powerplay-disable-gfxoff-for-navi12.patch
+patch 3448-Revert-drm-amd-display-Make-init_hw-and-init_pipes-g.patch
+patch 3449-Revert-drm-amd-display-make-firmware-info-only-load-.patch
+patch 3450-drm-amdgpu-Set-no-retry-as-default.patch
+patch 3451-drm-amdgpu-Add-printing-for-RW-extracted-from-VM_L2_.patch
+patch 3452-drm-amdgpu-Add-more-page-fault-info-printing-for-GFX.patch
+patch 3453-drm-amdgpu-Set-VM_L2_CNTL.PDE_FAULT_CLASSIFICATION-t.patch
+patch 3454-drm-amd-amdgpu-Update-VM-function-pointer.patch
+patch 3455-drm-amdkfd-add-debug-notification.patch
+patch 3456-drm-amdkfd-Remove-temporary-hack-to-enable-notificat.patch
+patch 3457-drm-amd-powerplay-smu7-enforce-minimal-VBITimeout-v2.patch
+patch 3458-dmr-amdgpu-Fix-compile-error-with-CONFIG_DRM_AMDGPU_.patch
+patch 3459-drm-amd-powerplay-Fix-meaning-of-0x1E-PPSMC_MSG.patch
+patch 3460-drm-amd-powerplay-add-mode2-reset-callback-for-pp_sm.patch
+patch 3461-drm-amd-powerpay-Implement-mode2-reset-callback-for-.patch
+patch 3462-drm-amd-poweplay-Add-amd_pm_funcs-callback-for-mode-.patch
+patch 3463-drm-amdgpu-Use-new-mode2-reset-interface-for-RV.patch
+patch 3464-drm-amdgpu-remove-special-autoload-handling-for-navi.patch
+patch 3465-drm-amdgpu-fix-debug-level-for-ppt-offset-size.patch
+patch 3466-drm-amdgpu-remove-redundant-argument-for-psp_funcs-c.patch
+patch 3467-drm-amdgpu-gfx9-update-pg_flags-after-determining-if.patch
+patch 3468-drm-amdgpu-Fix-a-typo-in-the-include-header-guard-of.patch
+patch 3469-drm-amdkfd-Fill-the-name-field-in-node-topology-with.patch
+patch 3470-drm-amd-powerplay-add-smu_smc_read_sensor-support-fo.patch
+patch 3471-drm-amd-powerplay-fix-variable-type-errors-in-smu_v1.patch
+patch 3472-drm-amd-powerplay-remove-duplicate-macro-smu_get_ucl.patch
+patch 3473-drm-amd-powerplay-update-Arcturus-smc-fw-and-driver-.patch
+patch 3474-drm-amd-powerplay-expose-supported-clock-domains-onl.patch
+patch 3475-drm-amd-powerplay-get-bootup-fclk-value.patch
+patch 3476-drm-amd-powerplay-set-Arcturus-default-fclk-as-bootu.patch
+patch 3477-drm-amd-powerplay-correct-SW-smu11-thermal-range-set.patch
+patch 3478-drm-amd-powerplay-correct-typo.patch
+patch 3479-drm-amd-amdgpu-disable-MMHUB-PG-for-navi10.patch
+patch 3480-drm-amdkfd-fix-kfd-SWDEV-200283-test-issue.patch
+patch 3481-drm-amdkfd-Report-domain-with-topology.patch
+patch 3482-drm-amd-display-Check-return-code-for-CRC-drm_crtc_v.patch
+patch 3483-drm-amd-display-Use-connector-list-for-finding-DPRX-.patch
+patch 3484-drm-amd-display-Split-out-DC-programming-for-CRC-cap.patch
+patch 3485-drm-amd-display-Lock-the-CRTC-when-setting-CRC-sourc.patch
+patch 3486-drm-amdgpu-prevent-memory-leaks-in-AMDGPU_CS-ioctl.patch
+patch 3487-drm-amd-display-Calculate-bpc-based-on-max_requested.patch
+patch 3488-drm-amd-display-Fix-32-bit-divide-error-in-wait_for_.patch
+patch 3489-drm-amdgpu-remove-set-but-not-used-variable-psp_enab.patch
+patch 3490-drm-amdgpu-remove-duplicated-include-from-gfx_v9_0.c.patch
+patch 3491-drm-amd-display-remove-duplicated-include-from-dc_li.patch
+patch 3492-drm-amdkfd-remove-set-but-not-used-variable-pdd.patch
+patch 3493-drm-amdgpu-disable-agp-for-sriov.patch
+patch 3494-drm-amdgpu-unity-mc-base-address-for-arcturus.patch
+patch 3495-amd-amdgpu-add-Arcturus-vf-DID-support.patch
+patch 3496-drm-powerplay-Fix-Vega20-Average-Power-value-v4.patch
+patch 3497-Revert-drm-amd-display-skip-dsc-config-for-navi10-br.patch
+patch 3498-drm-amdgpu-fix-dma_fence_wait-without-reference.patch
+patch 3499-Revert-drm-amd-display-navi10-bring-up-skip-dsc-enco.patch
+patch 3500-Revert-drm-amd-display-add-global-master-update-lock.patch
+patch 3501-Revert-drm-amd-display-Fix-underscan-not-using-prope.patch
+patch 3502-drm-amd-display-Enable-SST-DSC-in-DM.patch
+patch 3503-drm-amdgpu-sdma5-fix-number-of-sdma5-trap-irq-types-.patch
+patch 3504-drm-amdkfd-Make-deallocate_hiq_sdma_mqd-static.patch
+patch 3505-drm-amdgpu-powerplay-remove-redundant-assignment-to-.patch
+patch 3506-drm-amdgpu-powerplay-silence-a-warning-in-smu_v11_0_.patch
+patch 3507-drm-amdgpu-powerplay-Add-smu_v12_0_ppsmc.h-v2.patch
+patch 3508-drm-amd-powerplay-add-smu12_driver_if.h-v3.patch
+patch 3509-drm-amdgpu-powerplay-add-initial-renoir_ppt.c-for-re.patch
+patch 3510-drm-amdgpu-powerplay-add-smu_v12_0.c-smu_v12_0.h-for.patch
+patch 3511-drm-amdgpu-powerplay-add-smu-ip-block-for-renoir-v2.patch
+patch 3512-drm-amdgpu-powerplay-add-power-up-down-SDMA-interfac.patch
+patch 3513-drm-amdgpu-skip-dpm-init-for-renoir.patch
+patch 3514-drm-amdgpu-powerplay-add-Renoir-VCN-power-management.patch
+patch 3515-drm-amd-powerplay-powerup-sdma-vcn-for-all-apu-serie.patch
+patch 3516-drm-amd-powerplay-udpate-smu_v12_0_check_fw_version-.patch
+patch 3517-drm-amdgpu-add-set_gfx_cgpg-implement-v2.patch
+patch 3518-drm-amdgpu-add-and-enable-gfxoff-feature.patch
+patch 3519-drm-amd-powerplay-fix-checking-gfxoff-status-for-rn.patch
+patch 3520-drm-amd-powerplay-using-valid-mapping-check-for-rn.patch
+patch 3521-drm-amd-powerplay-add-smu-tables-for-rn.patch
+patch 3522-drm-amd-powerplay-init-smu-tables-for-rn.patch
+patch 3523-drm-amd-powerplay-add-DPMCLOCKS-table-implementation.patch
+patch 3524-drm-amdgpu-enable-gfx-clock-gating-for-rn.patch
+patch 3525-drm-amdgpu-enable-mmhub-clock-gating-for-rn.patch
+patch 3526-drm-amdgpu-enable-sdma-clock-gating-for-rn.patch
+patch 3527-drm-amdgpu-enable-BIF-clock-gating-for-rn.patch
+patch 3528-drm-amdgpu-enable-HDP-clock-gating-for-rn.patch
+patch 3529-drm-amdgpu-enable-rom-clock-gating-for-rn.patch
+patch 3530-drm-amdgpu-enable-vcn-clock-gating-for-rn.patch
+patch 3531-drm-amdgpu-enable-IH-clock-gating-for-rn.patch
+patch 3532-drm-amdgpu-enable-athub-clock-gating-for-rn.patch
+patch 3533-drm-amdgpu-enable-DF-clock-gating-for-rn.patch
+patch 3534-drm-amdgpu-mmhub1-set-mmhub-clock-gating-for-rn.patch
+patch 3535-drm-amdgpu-sdma4-set-sdma-clock-gating-for-rn.patch
+patch 3536-drm-amdgpu-enable-SDMA-power-gating-for-rn.patch
+patch 3537-drm-amd-powerplay-enable-renoir-dpm-feature.patch
+patch 3538-drm-amd-powerplay-Disable-renoir-smu-feature-retrive.patch
+patch 3539-drm-amdgpu-update-gc-sdma-goldensetting-for-rn.patch
+patch 3540-drm-amdgpu-enable-VCN-DPG-for-Renoir.patch
+patch 3541-drm-amdgpu-correct-ras-error-count-type.patch
+patch 3542-drm-amdkfd-updated-read-to-set-errno-to-eagain.patch
+patch 3543-drm-amdkfd-add-new-queue-status.patch
+patch 3544-drm-amd-powerplay-fix-message-of-SetHardMinByFreq-fa.patch
+patch 3545-drm-amdgpu-fix-typo-error-amdgput-amdgpu.patch
+patch 3546-drm-amdgpu-use-exiting-amdgpu_ctx_total_num_entities.patch
+patch 3547-drm-amdgpu-implement-querying-ras-error-count-for-mm.patch
+patch 3548-drm-amdgpu-powerplay-fix-spelling-mistake-unsuported.patch
+patch 3549-drm-amdgpu-MODULE_FIRMWARE-requires-linux-module.h.patch
+patch 3550-drm-scheduler-use-job-count-instead-of-peek.patch
+patch 3551-drm-amd-display-Add-PIXEL_RATE-control-regs-for-more.patch
+patch 3552-drm-amd-display-Add-DFS-reference-clock-field.patch
+patch 3553-drm-amd-powerpaly-fix-navi-series-custom-peak-level-.patch
+patch 3554-drm-amd-display-make-firmware-info-only-load-once-du.patch
+patch 3555-drm-amd-display-Make-init_hw-and-init_pipes-generic-.patch
+patch 3556-drm-amd-display-fix-a-potential-null-pointer-derefer.patch
+patch 3557-amd-amdkfd-add-Arcturus-vf-DID-support.patch
+patch 3558-drm-powerplay-Fix-Vega20-power-reading-again.patch
+patch 3559-drm-amdgpu-powerplay-smu7-enable-mclk-switching-if-m.patch
+patch 3560-drm-amdgpu-powerplay-vega10-enable-mclk-switching-if.patch
+patch 3561-drm-amd-display-update-bw_calcs-to-take-pipe-sync-in.patch
+patch 3562-drm-amdgpu-display-add-flag-for-multi-display-mclk-s.patch
+patch 3563-drm-amdgpu-set-adev-num_vmhubs-for-gmc6-7-8.patch
+patch 3564-drm-amd-display-re-structure-odm-to-allow-4-to-1-sup.patch
+patch 3565-drm-amd-display-Delete-dead-code-in-command_table_he.patch
+patch 3566-drm-amd-display-fix-audio-endpoint-not-getting-disab.patch
+patch 3567-drm-amd-display-fix-MPO-HUBP-underflow-with-Scatter-.patch
+patch 3568-drm-amd-display-load-iram-for-abm-2.3.patch
+patch 3569-drm-amd-display-fix-dp-stream-enable.patch
+patch 3570-drm-amd-display-set-Hratio-and-VRatio-in-dml.patch
+patch 3571-drm-amd-display-add-null-checks-before-logging.patch
+patch 3572-drm-amd-display-Implement-voltage-limitation-stub.patch
+patch 3573-drm-amd-display-Zero-out-dsc-init-regs.patch
+patch 3574-drm-amd-display-refactor-Device-ID-for-external-chip.patch
+patch 3575-drm-amd-display-Add-VM-page-fault-handle-implementat.patch
+patch 3576-drm-amd-display-cleaned-up-coding-error-in-init_hw.patch
+patch 3577-drm-amd-display-remove-unused-function.patch
+patch 3578-drm-amd-display-3.2.47.patch
+patch 3579-drm-amd-display-Refactoring-VTEM.patch
+patch 3580-drm-amd-display-support-spdif.patch
+patch 3581-drm-amd-display-fix-stuck-test-pattern-on-right-half.patch
+patch 3582-drm-amd-display-fix-odm-pipe-copy.patch
+patch 3583-drm-amd-display-Fix-number-of-slices-not-being-check.patch
+patch 3584-drm-amd-display-fix-dcn20-odm-dpp-programming.patch
+patch 3585-drm-amd-display-fix-odm-stream-release.patch
+patch 3586-drm-amd-display-fix-odm-validation.patch
+patch 3587-drm-amd-display-add-Cursor-Degamma-logic-for-DCN2.patch
+patch 3588-drm-amd-display-Enable-HW-rotation.patch
+patch 3589-drm-amd-display-Add-Logging-for-Gamma-Related-inform.patch
+patch 3590-drm-amd-display-set-av_mute-in-hw_init-for-HDMI.patch
+patch 3591-drm-amd-display-MST-topology-debugfs.patch
+patch 3592-drm-amd-display-fix-DML-not-calculating-delivery-tim.patch
+patch 3593-drm-amd-display-Expose-OTG_V_TOTAL_MID-for-HW-Diags.patch
+patch 3594-drm-amd-display-Use-res_cap-to-acquire-i2c-instead-o.patch
+patch 3595-drm-amd-display-revert-wait-in-pipelock.patch
+patch 3596-drm-amd-display-Properly-read-LVTMA_PWRSEQ_CNTL.patch
+patch 3597-drm-amd-display-flicking-observed-while-installing-d.patch
+patch 3598-drm-amd-display-3.2.48.patch
+patch 3599-drm-amd-display-fix-calc_pll_max_vco_construct.patch
+patch 3600-drm-amdgpu-fix-commit-4ef9d7d.patch
+patch 3601-drm-amdgpu-enable-vcn-powergating-for-navi12.patch
+patch 3602-drm-amdgpu-enable-athub-powergating-for-navi12.patch
+patch 3603-drm-amd-powerplay-enable-jpeg-powergating-for-navi1x.patch
+patch 3604-drm-amd-powerplay-correct-Vega20-dpm-level-related-s.patch
+patch 3605-drm-amd-powerplay-correct-the-pp_feature-output-on-A.patch
+patch 3606-drm-amdgpu-Export-function-to-flush-TLB-of-specific-.patch
+patch 3607-drm-amdkfd-gfx10-Calling-amdgpu-functions-to-invalid.patch
+patch 3608-drm-amdgpu-add-dummy-read-for-some-GCVM-status-regis.patch
+patch 3609-drm-amd-display-Fix-error-message.patch
+patch 3610-drm-amd-powerplay-Fix-an-off-by-one-in-navi10_get_sm.patch
+patch 3611-drm-amdgpu-display-fix-build-error-without-CONFIG_DR.patch
+patch 3612-Revert-drm-amdgpu-free-up-the-first-paging-queue-v2.patch
+patch 3613-drm-amdgpu-Add-RAS-EEPROM-table.patch
+patch 3614-drm-amd-Import-smuio_11_0-headres-for-EEPROM-access-.patch
+patch 3615-drm-amd-powerplay-Add-interface-to-lock-SMU-HW-I2C.patch
+patch 3616-drm-amdgpu-Vega20-SMU-I2C-HW-engine-controller.patch
+patch 3617-drm-amdgpu-fix-a-warning-in-smu11-i2c-code.patch
+patch 3618-drm-amdgpu-correct-in_suspend-setting-for-navi-serie.patch
+patch 3619-drm-amd-display-remove-unused-function-setFieldWithM.patch
+patch 3620-drm-amdgpu-Add-APTX-quirk-for-Dell-Latitude-5495.patch
+patch 3621-drm-amd-remove-meaningless-descending-into-amd-amdkf.patch
+patch 3622-drm-amdgpu-introduce-vram-lost-for-reset-v2.patch
+patch 3623-drm-amd-amdgpu-hide-voltage-and-power-sensors-on-SI-.patch
+patch 3624-drm-amdgpu-si-fix-ASIC-tests.patch
+patch 3625-drm-amdgpu-virtual_dce-drop-error-message-in-hw_init.patch
+patch 3626-drm-amdgpu-fix-spelling-mistake-jumpimng-jumping.patch
+patch 3627-drm-amdgpu-psp-keep-TMR-in-visible-vram-region-for-S.patch
+patch 3628-drm-amd-powerplay-regards-the-APU-always-enable-the-.patch
+patch 3629-drm-amd-powerplay-enable-populate-DPM-clocks-table-f.patch
+patch 3630-drm-amd-powerplay-add-the-interface-for-getting-ulti.patch
+patch 3631-drm-amd-display-Add-Renoir-registers-v3.patch
+patch 3632-drm-amd-display-Add-Renoir-clock-registers-list.patch
+patch 3633-drm-amd-display-Add-Renoir-hw_seq-register-list.patch
+patch 3634-drm-amd-display-Add-pp_smu-functions-for-Renoir.patch
+patch 3635-drm-amd-display-Add-Renoir-irq_services.patch
+patch 3636-drm-amd-display-Add-hubp-block-for-Renoir-v2.patch
+patch 3637-drm-amd-display-Add-Renoir-hubbub-registers-list.patch
+patch 3638-drm-amd-display-Add-Renoir-Hubbub-v2.patch
+patch 3639-drm-amd-display-Add-Renoir-clock-manager.patch
+patch 3640-drm-amd-display-Add-Renoir-resource-v2.patch
+patch 3641-drm-amd-display-Add-Renoir-GPIO.patch
+patch 3642-drm-amd-display-Add-Renoir-DML.patch
+patch 3643-drm-amd-display-Fix-register-names.patch
+patch 3644-drm-amd-display-Handle-Renoir-in-DC.patch
+patch 3645-drm-amd-display-Handle-Renoir-in-amdgpu_dm-v2.patch
+patch 3646-drm-amd-display-call-update_bw_bounding_box.patch
+patch 3647-drm-amd-display-add-dal_asic_id-for-renoir.patch
+patch 3648-drm-amd-display-add-dcn21-core-DC-changes.patch
+patch 3649-drm-amd-display-build-dcn21-blocks.patch
+patch 3650-drm-amd-display-add-Renoir-to-kconfig.patch
+patch 3651-drm-amd-display-Correct-order-of-RV-family-clk-manag.patch
+patch 3652-drm-amd-display-Add-DCN2.1-changes-to-DML.patch
+patch 3653-drm-amdgpu-Enable-DC-on-Renoir.patch
+patch 3654-drm-amdgpu-Handle-job-is-NULL-use-case-in-amdgpu_dev.patch
+patch 3655-drm-amdgpu-add-new-amdgpu-nbio-header-file.patch
+patch 3656-drm-amdgpu-switch-to-new-amdgpu_nbio-structure.patch
+patch 3657-drm-amdgpu-nbio-add-functions-to-query-ras-specific-.patch
+patch 3658-drm-amdgpu-add-nbif-v7_4-irq-source-header-for-vega2.patch
+patch 3659-drm-amdgpu-update-nbio-v7_4-ip-header-files.patch
+patch 3660-drm-amdgpu-add-ras_controller-and-err_event_athub-in.patch
+patch 3661-drm-amdgpu-keep-the-stolen-memory-in-visible-vram-re.patch
+patch 3662-drm-amdgpu-Initialize-and-update-SDMA-power-gating.patch
+patch 3663-drm-amd-powerplay-replace-smu-table_count-with-SMU_T.patch
+patch 3664-drm-amd-powerplay-SMU_MSG_OverridePcieParameters-is-.patch
+patch 3665-drm-amdgpu-update-IH_CHICKEN-in-oss-4.0-IP-header-fo.patch
+patch 3666-drm-amdgpu-fix-no-interrupt-issue-for-renoir-emu-v2.patch
+patch 3667-drm-amdgpu-Move-null-pointer-dereference-check.patch
+patch 3668-drm-amdgpu-Remove-unnecessary-TLB-workaround-v2.patch
+patch 3669-drm-amd-powerplay-guard-manual-mode-prerequisite-for.patch
+patch 3670-drm-amd-powerplay-update-cached-feature-enablement-s.patch
+patch 3671-drm-amd-powerplay-do-proper-cleanups-on-hw_fini.patch
+patch 3672-drm-amdgpu-use-moving-fence-instead-of-exclusive-for.patch
+patch 3673-drm-amdgpu-reserve-at-least-4MB-of-VRAM-for-page-tab.patch
+patch 3674-drm-amdgpu-remove-amdgpu_cs_try_evict.patch
+patch 3675-drm-amdgpu-Fix-bugs-in-amdgpu_device_gpu_recover-in-.patch
+patch 3676-drm-amd-amdgpu-add-sw_fini-interface-for-df_funcs.patch
+patch 3677-drm-amdgpu-change-r-type-to-int-in-gmc_v9_0_late_ini.patch
+patch 3678-drm-amd-display-update-renoir_ip_offset.h.patch
+patch 3679-drm-amdgpu-disable-stutter-mode-for-renoir.patch
+patch 3680-drm-amd-display-Add-stereo-mux-and-dig-programming-c.patch
+patch 3681-drm-amdgpu-Determing-PTE-flags-separately-for-each-m.patch
+patch 3682-drm-amdgpu-Support-new-arcturus-mtype.patch
+patch 3683-drm-amdgpu-Extends-amdgpu-vm-definitions-v2.patch
+patch 3684-drm-amdgpu-Fix-cherry-pick-and-revert-issues-on-amdg.patch
+patch 3685-drm-amd-powerplay-update-smu11_driver_if_navi10.h.patch
+patch 3686-drm-amdgpu-poll-ras_controller_irq-and-err_event_ath.patch
+patch 3687-drm-amdgpu-irq-check-if-nbio-funcs-exist.patch
+patch 3688-drm-amdgpu-add-helper-function-to-do-common-ras_late.patch
+patch 3689-drm-amdgpu-only-apply-gds-clearing-workaround-when-r.patch
+patch 3690-drm-amdgpu-add-ras_late_init-callback-function-for-n.patch
+patch 3691-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-gfx-v9.patch
+patch 3692-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-gmc-v9.patch
+patch 3693-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-sdma-v.patch
+patch 3694-drm-amdgpu-add-mmhub-ras_late_init-callback-function.patch
+patch 3695-drm-amdgpu-switch-to-amdgpu_ras_late_init-for-nbio-v.patch
+patch 3696-drm-amdgpu-check-mmhub_funcs-pointer-before-refering.patch
+patch 3697-drm-amdgpu-fix-memory-leak-when-ras-is-not-supported.patch
+patch 3698-drm-amdgpu-Fix-undefined-dm_ip_block-for-navi12.patch
+patch 3699-drm-amdgpu-psp-move-TMR-to-cpu-invisible-vram-region.patch
+patch 3700-drm-amdgpu-clean-up-load-TMR-sequence.patch
+patch 3701-drm-amd-powerplay-implement-sysfs-for-getting-dpm-cl.patch
+patch 3702-drm-amdgpu-Disable-page-faults-while-reading-user-wp.patch
+patch 3703-drm-amdkfd-Query-kfd-device-info-by-CHIP-id-instead-.patch
+patch 3704-drm-amd-powerplay-fix-unused-variable-compile-warnin.patch
+patch 3705-drm-amdkfd-Fix-a-building-error-when-KFD_SUPPORT_IOM.patch
+patch 3706-drm-amd-display-Fix-DML-tests.patch
+patch 3707-drm-amd-display-refine-i2c-over-aux.patch
+patch 3708-drm-amd-display-Subsample-mode-suboptimal-for-YCbCr4.patch
+patch 3709-drm-amd-display-Don-t-allocate-payloads-if-link-lost.patch
+patch 3710-drm-amd-display-Add-back-support-for-DSC-4-2-2-Simpl.patch
+patch 3711-drm-amd-display-config-to-override-DSC-start-slice-h.patch
+patch 3712-drm-amd-display-3.2.49.patch
+patch 3713-drm-amd-display-Add-missing-surface-address-register.patch
+patch 3714-drm-amd-display-update-navi-to-use-new-surface-progr.patch
+patch 3715-drm-amd-display-remove-temporary-transition-code.patch
+patch 3716-drm-amd-display-Reuse-dcn2-registers.patch
+patch 3717-drm-amd-display-remove-hw-access-from-dc_destroy.patch
+patch 3718-drm-amd-display-OTC-underflow-fix.patch
+patch 3719-drm-amd-display-Isolate-DSC-module-from-driver-depen.patch
+patch 3720-drm-amd-display-dce11.x-dce12-update-formula-input.patch
+patch 3721-drm-amd-display-verify-stream-link-before-link-test.patch
+patch 3722-drm-amd-display-replace-FIXME-with-TODO.patch
+patch 3723-drm-amdgpu-Add-a-kernel-parameter-for-specifying-the.patch
+patch 3724-drm-amdgpu-Disable-retry-faults-in-VMID0.patch
+patch 3725-drm-amdkfd-Support-Navi14-in-KFD.patch
+patch 3726-drm-amdkfd-enable-renoir-while-device-probes.patch
+patch 3727-drm-amdkfd-add-renoir-kfd-device-info-v2.patch
+patch 3728-drm-amdkfd-add-renoir-cache-info-for-CRAT-v2.patch
+patch 3729-drm-amdkfd-add-renoir-type-for-the-workaround-of-iom.patch
+patch 3730-drm-amdgpu-disable-gfxoff-while-use-no-H-W-schedulin.patch
+patch 3731-drm-amdkfd-enable-kfd-device-queue-manager-v9-for-re.patch
+patch 3732-drm-amdkfd-init-kfd-apertures-v9-for-renoir.patch
+patch 3733-drm-amdkfd-init-kernel-queue-for-renoir.patch
+patch 3734-drm-amdkfd-add-renoir-kfd-topology.patch
+patch 3735-drm-amdkfd-add-package-manager-for-renoir.patch
+patch 3736-dmr-amdgpu-Avoid-HW-GPU-reset-for-RAS.patch
+patch 3737-drm-amdgpu-check-if-nbio-ras_if-exist.patch
+patch 3738-dmr-amdgpu-Add-system-auto-reboot-to-RAS.patch
+patch 3739-drm-amdgpu-fix-ras-parameter-descriptions.patch
+patch 3740-drm-amdgpu-set-ip-specific-ras-interface-pointer-to-.patch
+patch 3741-drm-amdgpu-gmc-switch-to-amdgpu_gmc_ras_late_init-he.patch
+patch 3742-drm-amdgpu-gfx-switch-to-amdgpu_gfx_ras_late_init-he.patch
+patch 3743-drm-amdgpu-sdma-switch-to-amdgpu_sdma_ras_late_init-.patch
+patch 3744-drm-amdgpu-mmhub-switch-to-amdgpu_mmhub_ras_late_ini.patch
+patch 3745-drm-amdgpu-nbio-switch-to-amdgpu_nbio_ras_late_init-.patch
+patch 3746-drm-amdgpu-init-UMC-RSMU-register-base-address.patch
+patch 3747-drm-amdgpu-Add-smu-lock-around-in-pp_smu_i2c_bus_acc.patch
+patch 3748-drm-amdgpu-Remove-clock-gating-restore.patch
+patch 3749-drm-madgpu-Fix-EEPROM-Checksum-calculation.patch
+patch 3750-drm-amdgpu-change-ras-bps-type-to-eeprom-table-recor.patch
+patch 3751-drm-amdgpu-Hook-EEPROM-table-to-RAS.patch
+patch 3752-drm-amdgpu-save-umc-error-records.patch
+patch 3753-drm-amdgpu-move-the-call-of-ras-recovery_init-and-ba.patch
+patch 3754-drm-amdgpu-enable-TA-load-support-in-Arcturus.patch
+patch 3755-drm-amd-powerplay-Add-the-interface-for-geting-dpm-c.patch
+patch 3756-drm-amd-powerplay-issue-DC-BTC-for-arcturus-on-SMU-i.patch
+patch 3757-drm-amdgpu-add-firmware-header-printing-for-psp-fw-l.patch
+patch 3758-drm-amdgpu-fix-null-pointer-deref-in-firmware-header.patch
+patch 3759-drm-amdgpu-add-navi14-PCI-ID-for-work-station-SKU.patch
+patch 3760-drm-amdgpu-Avoid-RAS-recovery-init-when-no-RAS-suppo.patch
+patch 3761-drm-amdgpu-psp-fix-warning-in-switch-statement.patch
+patch 3762-drm-amdgpu-fix-build-error-without-CONFIG_HSA_AMD.patch
+patch 3763-drm-amdgpu-remove-duplicated-header-file-include.patch
+patch 3764-drm-amdgpu-move-umc-late-init-from-gmc-to-umc-block.patch
+patch 3765-drm-amdgpu-move-umc-ras-init-to-umc-block.patch
+patch 3766-drm-amdgpu-rename-umc-ras_init-to-err_cnt_init.patch
+patch 3767-drm-amdgpu-Add-amdgpu_ras_eeprom_reset_table.patch
+patch 3768-drm-amdgpu-Allow-to-reset-to-EERPOM-table.patch
+patch 3769-drm-amdgpu-adding-xgmi-error-monitoring.patch
+patch 3770-drm-amdgpu-initialize-ras-structures-for-xgmi-block-.patch
+patch 3771-drm-amdgpu-enable-error-injection-to-XGMI-block-via-.patch
+patch 3772-drm-amdgpu-fix-CPDMA-hang-in-PRT-mode-for-VEGA10.patch
+patch 3773-drm-amdkfd-fix-the-missed-asic-name-while-inited-ren.patch
+patch 3774-drm-amdgpu-add-ras-error-query-count-interface-for-n.patch
+patch 3775-drm-amdgpu-support-pcie-bif-ras-query-and-inject.patch
+patch 3776-drm-amdgpu-add-pcie-bif-ras-related-registers.patch
+patch 3777-drm-amdgpu-implement-ras-query-function-for-pcie-bif.patch
+patch 3778-drm-amd-display-add-Asic-ID-for-Dali.patch
+patch 3779-drm-amd-display-Implement-voltage-limitation-for-dal.patch
+patch 3780-drm-amdkfd-add-queue-snapshot.patch
+patch 3781-drm-amdgpu-Add-SRIOV-mailbox-backend-for-Navi1x.patch
+patch 3782-drm-amdgpu-Fix-mutex-lock-from-atomic-context.patch
+patch 3783-drm-amdgpu-Fix-KFD-related-kernel-oops-on-Hawaii.patch
+patch 3784-drm-amd-powerplay-properly-set-mp1-state-for-SW-SMU-.patch
+patch 3785-drm-amd-powerplay-check-SMU-engine-readiness-before-.patch
+patch 3786-drm-amd-powerplay-update-smu11_driver_if_arcturus.h.patch
+patch 3787-drm-amdgpu-sriov-add-ring_stop-before-ring_create-in.patch
+patch 3788-drm-amdgpu-For-Navi12-SRIOV-VF-register-mailbox-func.patch
+patch 3789-drm-amd-amdgpu-power-up-sdma-engine-when-S3-resume-b.patch
+patch 3790-drm-amdgpu-SRIOV-Navi10-12-VF-doesn-t-support-SMU.patch
+patch 3791-drm-amdgpu-SRIOV-Navi12-SRIOV-VF-doesn-t-load-TOC.patch
+patch 3792-drm-amdgpu-grab-the-id-mgr-lock-while-accessing-pass.patch
+patch 3793-drm-amdgpu-split-the-VM-entity-into-direct-and-delay.patch
+patch 3794-drm-amdgpu-allow-direct-submission-in-the-VM-backend.patch
+patch 3795-drm-amdgpu-allow-direct-submission-of-PDE-updates-v2.patch
+patch 3796-drm-amdgpu-allow-direct-submission-of-PTE-updates.patch
+patch 3797-drm-amdgpu-allow-direct-submission-of-clears.patch
+patch 3798-drm-amdgpu-allocate-PDs-PTs-with-no_gpu_wait-in-a-pa.patch
+patch 3799-drm-amdgpu-reserve-the-root-PD-while-freeing-PASIDs.patch
+patch 3800-drm-amdgpu-add-graceful-VM-fault-handling-v3.patch
+patch 3801-drm-amdgpu-remove-needless-usage-of-ifdef.patch
+patch 3802-Revert-drm-amdgpu-nbio7.4-add-hw-bug-workaround-for-.patch
+patch 3803-drm-amd-display-rename-variable-eanble-enable.patch
+patch 3804-drm-amdgpu-Check-for-valid-number-of-registers-to-re.patch
+patch 3805-drm-amd-be-quiet-when-no-SAD-block-is-found.patch
+patch 3806-drm-amdgpu-remove-the-redundant-null-checks.patch
+patch 3807-drm-amdkfd-Swap-trap-temporary-registers-in-gfx10-tr.patch
+patch 3808-drm-amdgpu-fix-double-ucode-load-by-PSP-v3.patch
+patch 3809-drm-amdgpu-add-navi12-pci-id.patch
+patch 3810-drm-amd-powerplay-implement-VCN-power-gating-control.patch
+patch 3811-drm-amdgpu-remove-program-of-lbpw-for-renoir.patch
+patch 3812-drm-amdgpu-SRIOV-Navi12-SRIOV-VF-gets-GTT-base.patch
+patch 3813-drm-amdgpu-set-bulk_moveable-to-false-when-lru-chang.patch
+patch 3814-drm-amdgpu-Set-pasid-for-compute-vm-v2.patch
+patch 3815-drm-amdgpu-cleanup-coding-style-in-the-VM-code-a-bit.patch
+patch 3816-drm-amdgpu-drop-double-HDP-flush-in-the-VM-code.patch
+patch 3817-drm-amdgpu-trace-if-a-PD-PT-update-is-done-directly.patch
+patch 3818-drm-amdgpu-fix-ras-ctrl-debugfs-node-leak.patch
+patch 3819-drm-amdgpu-Fix-EEPROM-checksum-calculation.patch
+patch 3820-drm-amdgpu-cleanup-mtype-mapping.patch
+patch 3821-drm-amdgpu-check-large-bar-when-map-peer-device.patch
+patch 3822-drm-amdgpu-cleanup-PTE-flag-generation-v3.patch
+patch 3823-drm-amdkfd-fix-queue-snapshot-input-handling-and-ret.patch
+patch 3824-drm-amdgpu-gfx10-add-support-for-wks-firmware-loadin.patch
+patch 3825-drm-amd-display-Fix-HUBP-secondary-viewport-programm.patch
+patch 3826-drm-amd-display-define-parameters-for-abm-2.3.patch
+patch 3827-drm-amd-display-3.2.50.patch
+patch 3828-drm-amd-display-Rebuild-mapped-resources-after-pipe-.patch
+patch 3829-drm-amd-display-Replace-for-loop-w-function-call.patch
+patch 3830-drm-amd-display-add-additional-flag-consideration-fo.patch
+patch 3831-drm-amd-display-Add-debugfs-entry-to-force-YUV420-ou.patch
+patch 3832-drm-amd-display-add-vtg-update-after-global-sync-upd.patch
+patch 3833-drm-amd-display-fix-global-sync-param-extraction-ind.patch
+patch 3834-drm-amd-display-Handle-virtual-signal-type-in-disabl.patch
+patch 3835-drm-amd-display-fix-i2c-wtire-mot-incorrect-issue.patch
+patch 3836-drm-amd-display-Separate-hardware-initialization-fro.patch
+patch 3837-drm-amd-display-Do-not-double-buffer-DTO-adjustments.patch
+patch 3838-drm-amd-display-Revert-fixup-DPP-programming-sequenc.patch
+patch 3839-drm-amd-display-set-minimum-abm-backlight-level.patch
+patch 3840-drm-amd-display-Set-number-of-pipes-to-1-if-the-seco.patch
+patch 3841-drm-amd-display-Optimize-clocks-on-clock-change.patch
+patch 3842-drm-amd-display-update-odm-mode-validation-to-be-in-.patch
+patch 3843-drm-amd-display-enable-single-dp-seamless-boot.patch
+patch 3844-drm-amd-display-3.2.51.patch
+patch 3845-drm-amd-display-Add-missing-HBM-support-and-raise-Ve.patch
+patch 3846-drm-amd-display-3.2.51.1.patch
+patch 3847-drm-amd-display-fix-use-of-uninitialized-variable.patch
+patch 3848-drm-amd-display-Add-detile-buffer-size-for-DCN20.patch
+patch 3849-drm-amd-display-Improve-LFC-behaviour.patch
+patch 3850-drm-amdgpu-gmc10-apply-the-invalidation-from-sdma-wo.patch
+patch 3851-drm-amdgpu-gfx10-enable-gfxoff-for-navi12.patch
+patch 3852-drm-amdgpu-add-psp-ip-block-for-arct.patch
+patch 3853-drm-amdgpu-disable-vcn-ip-block-for-front-door-loadi.patch
+patch 3854-drm-amdgpu-enable-psp-front-door-loading-by-default-.patch
+patch 3855-drm-amdgpu-add-command-id-in-psp-response-failure-me.patch
+patch 3856-drm-amdgpu-correct-condition-check-for-psp-rlc-autol.patch
+patch 3857-Revert-drm-amd-display-Add-dmub-offload-functions.patch
+patch 3858-drm-amdgpu-psp-HDCP-init.patch
+patch 3859-drm-amdgpu-psp-DTM-init.patch
+patch 3860-drm-amd-display-Add-HDCP-module.patch
+patch 3861-drm-amd-display-add-PSP-block-to-verify-hdcp-steps.patch
+patch 3862-drm-amd-display-Update-hdcp-display-config.patch
+patch 3863-drm-amd-display-Create-amdgpu_dm_hdcp.patch
+patch 3864-drm-amd-display-Create-dpcd-and-i2c-packing-function.patch
+patch 3865-drm-amd-display-Initialize-HDCP-work-queue.patch
+patch 3866-drm-amd-display-Handle-Content-protection-property-c.patch
+patch 3867-drm-amd-display-handle-DP-cpirq.patch
+patch 3868-drm-amd-display-Update-CP-property-based-on-HW-query.patch
+patch 3869-drm-amd-display-only-enable-HDCP-for-DCN.patch
+patch 3870-drm-amd-display-Add-hdcp-to-Kconfig.patch
+patch 3871-drm-amdkfd-Delete-unused-KFD_IS_-macro.patch
+patch 3872-drm-amdgpu-vm-fix-documentation-for-amdgpu_vm_bo_par.patch
+patch 3873-docs-drm-amdgpu-Resolve-build-warnings.patch
+patch 3874-drm-amdgpu-add-navi12-pci-id.patch
+patch 3875-drm-amdgpu-use-GPU-PAGE-SHIFT-for-umc-retired-page.patch
+patch 3876-drm-amdgpu-discovery-get-gpu-info-from-ip-discovery-.patch
+patch 3877-drm-amdgpu-do-not-init-mec2-jt-for-renoir.patch
+patch 3878-drm-amdgpu-powerplay-add-new-mapping-for-APCC_DFLL-f.patch
+patch 3879-drm-amdgpu-avoid-null-pointer-dereference.patch
+patch 3880-drm-amdgpu-remove-redundant-variable-definition.patch
+patch 3881-drm-amdgpu-psp-flush-HDP-write-fifo-after-submitting.patch
+patch 3882-drm-amdgpu-psp-invalidate-the-hdp-read-cache-before-.patch
+patch 3883-drm-amdgpu-flag-navi12-and-14-as-experimental-for-5..patch
+patch 3884-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
+patch 3885-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
+patch 3886-drm-amdgpu-SRIOV-add-navi12-pci-id-for-SRIOV-v2.patch
+patch 3887-drm-amdgpu-enable-full-ras-by-default.patch
+patch 3888-drm-amdgpu-remove-excess-function-parameter-descript.patch
+patch 3889-Revert-drm-amdgpu-enable-full-ras-by-default.patch
+patch 3890-drm-amd-display-Restore-backlight-brightness-after-s.patch
+patch 3891-drm-amd-display-hide-an-unused-variable.patch
+patch 3892-drm-amd-display-Fix-kernel-doc-warnings.patch
+patch 3893-Fix-the-messed-up-format.patch
+patch 3894-drm-amdgpu-drop-experimental-flag-for-amd-staging-dr.patch
+patch 3895-drm-amdgpu-fix-documentation-for-amdgpu_gem_prime_ex.patch
+patch 3896-drm-amdgpu-mn-fix-documentation-for-amdgpu_mn_read_l.patch
+patch 3897-drm-amdgpu-vm-fix-up-documentation-in-amdgpu_vm.c.patch
+patch 3898-drm-amdgpu-ih-fix-documentation-in-amdgpu_irq_dispat.patch
+patch 3899-drm-amdgpu-fix-documentation-for-amdgpu_pm.c.patch
+patch 3900-drm-amdgpu-ras-fix-and-update-the-documentation-for-.patch
+patch 3901-drm-amdkfd-fix-a-potential-NULL-pointer-dereference-.patch
+patch 3902-drm-amdkfd-Add-an-error-print-if-SDMA-RLC-is-not-idl.patch
+patch 3903-drm-amdkfd-Remove-excessive-print-when-reserving-doo.patch
+patch 3904-drm-amdkfd-Remove-unnecessary-pm_init-for-non-HWS-mo.patch
+patch 3905-drm-amdkfd-Fix-NULL-pointer-dereference-for-set_scra.patch
+patch 3906-drm-amdkfd-Sync-gfx10-kfd2kgd_calls-function-pointer.patch
+patch 3907-drm-amdgpu-display-fix-64-bit-divide.patch
+patch 3908-drm-amd-powerplay-Add-mode2-mode-for-GPU-RESET-in-SM.patch
+patch 3909-drm-amd-powerplay-A-workaround-to-GPU-RESET-on-APU.patch
+patch 3910-drm-amdgpu-Use-mode2-mode-to-perform-GPU-RESET-for-R.patch
+patch 3911-drm-amdgpu-fix-an-UMC-hw-arbitrator-bug.patch
+patch 3912-Revert-drm-amdgpu-fix-an-UMC-hw-arbitrator-bug.patch
+patch 3913-drm-amd-powerplay-Vega10-Vega10-BKM0.83-AVFS-paramet.patch
+patch 3914-drm-amd-amdgpu-Fix-compute-ring-unable-to-detect-han.patch
+patch 3915-Revert-drm-amd-powerplay-Vega10-Vega10-BKM0.83-AVFS-.patch
+patch 3916-drm-amd-powerplay-remove-duplicate-macro-of-smu_get_.patch
+patch 3917-drm-amdgpu-psp-silence-response-status-warning.patch
+patch 3918-drm-amdgpu-display-include-slab.h-in-dcn21_resource..patch
+patch 3919-drm-amdgpu-atomfirmware-use-proper-index-for-queryin.patch
+patch 3920-drm-amdgpu-atomfirmware-simplify-the-interface-to-ge.patch
+patch 3921-Enable-over-subscription-with-1-GWS-queue.patch
+patch 3922-drm-amdkfd-add-pre-alpha-debugger-versioning.patch
+patch 3923-drm-amdkfd-fix-query-pending-event-with-unspecified-.patch
+patch 3924-include-uapi-linux-up-rev-debugger-pr-alpha-minor-re.patch
+patch 3925-drm-amdgpu-remove-gfx9-NGG.patch
+patch 3926-drm-amdgpu-fix-an-UMC-hw-arbitrator-bug-v3.patch
+patch 3927-drm-amdgpu-update-parameter-of-ras_ih_cb.patch
+patch 3928-drm-amdgpu-move-umc-ras-irq-functions-to-umc-block.patch
+patch 3929-drm-amdgpu-move-gfx-ecc-functions-to-generic-gfx-fil.patch
+patch 3930-drm-amdgpu-move-sdma-ecc-functions-to-generic-sdma-f.patch
+patch 3931-drm-amdgpu-refine-sdma4-ras_data_cb.patch
+patch 3932-drm-amdgpu-move-umc_ras_if-from-gmc-to-umc-block.patch
+patch 3933-drm-amdgpu-add-common-mmhub-member-for-adev.patch
+patch 3934-drm-amdgpu-replace-mmhub_funcs-with-mmhub.funcs.patch
+patch 3935-drm-amdgpu-move-mmhub_ras_if-from-gmc-to-mmhub-block.patch
+patch 3936-drm-amdgpu-add-common-gmc_ras_fini-function.patch
+patch 3937-drm-amdgpu-add-common-gfx_ras_fini-function.patch
+patch 3938-drm-amdgpu-add-common-sdma_ras_fini-function.patch
+patch 3939-drm-amdgpu-remove-ih_info-parameter-of-umc_ras_late_.patch
+patch 3940-drm-amdgpu-remove-ih_info-parameter-of-gfx_ras_late_.patch
+patch 3941-drm-amdgpu-simplify-the-access-to-eeprom_control-str.patch
+patch 3942-drm-amdgpu-add-ras-fini-for-nbio.patch
+patch 3943-drm-amdgpu-add-ras-fini-for-xgmi.patch
+patch 3944-drm-amdgpu-move-umc-ras-fini-to-umc-block.patch
+patch 3945-drm-amdgpu-move-mmhub-ras-fini-to-mmhub-block.patch
+patch 3946-drm-amdgpu-move-xgmi-ras-fini-to-xgmi-block.patch
+patch 3947-drm-amdgpu-implement-common-gmc_ras_late_init.patch
+patch 3948-drm-amdgpu-add-comments-in-ras-interrupt-callback.patch
+patch 3949-drm-amd-powerplay-update-arcturus-smu-driver-interac.patch
+patch 3950-drm-amdgpu-cleanup-creating-BOs-at-fixed-location-v2.patch
+patch 3951-drm-amdgpu-replace-DRM_ERROR-with-DRM_WARN-in-ras_re.patch
+patch 3952-drm-amdgpu-ras-use-GPU-PAGE_SIZE-SHIFT-for-reserving.patch
+patch 3953-drm-amdgpu-once-more-fix-amdgpu_bo_create_kernel_at.patch
+patch 3954-drm-amdgpu-restrict-hotplug-error-message.patch
+patch 3955-drm-amd-display-prevent-memory-leak.patch
+patch 3956-Revert-drm-amd-display-dc-fix-TRANSMITTER_UNIPHY_G-o.patch
+patch 3957-SWDEV-202843-drm-amd-display-dc-map-TRANSMITTER_UNIP.patch
+patch 3958-drm-amdgpu-Fix-error-handling-in-amdgpu_ras_recovery.patch
+patch 3959-drm-ttm-Refactor-ttm_bo_pipeline_move.patch
+patch 3960-drm-ttm-Restore-ttm-prefaulting.patch
+patch 3961-drm-ttm-Remove-explicit-typecasts-of-vm_private_data.patch
+patch 3962-drm-amdkfd-Add-NAVI12-support-from-kfd-side.patch
+patch 3963-drm-kms-Duct-tape-for-mode-object-lifetime-checks.patch
+patch 3964-drm-amdkfd-Delete-useless-SDMA-register-setting-on-n.patch
+patch 3965-drm-amdkfd-Use-better-name-for-sdma-queue-non-HWS-pa.patch
+patch 3966-drm-amdgpu-Add-SMUIO-values-for-other-I2C-controller.patch
+patch 3967-drm-amdkfd-use-navi12-specific-family-id-for-navi12-.patch
+patch 3968-device_cgroup-Export-devcgroup_check_permission.patch
+patch 3969-drm-amdkfd-Move-the-control-stack-on-GFX10-to-usersp.patch
+patch 3970-drm-amdkfd-Delete-unused-defines.patch
+patch 3971-drm-amdkfd-Use-hex-print-format-for-pasid.patch
+patch 3972-drm-amdkfd-Record-vmid-pasid-mapping-in-the-driver-f.patch
+patch 3973-drm-amdkfd-Query-vmid-pasid-mapping-through-stored-i.patch
+patch 3974-drm-amdkfd-Eliminate-get_atc_vmid_pasid_mapping_vali.patch
+patch 3975-drm-amdgpu-Export-setup_vm_pt_regs-logic-for-gfxhub-.patch
+patch 3976-drm-amdkfd-Use-setup_vm_pt_regs-function-from-base-d.patch
+patch 3977-drm-amdkfd-Fix-race-in-gfx10-context-restore-handler.patch
+patch 3978-drm-amdkfd-Fix-MQD-size-calculation.patch
+patch 3979-drm-amdkfd-Print-more-sdma-engine-hqds-in-debug-fs.patch
+patch 3980-drm-amd-powerplay-change-metrics-update-period-from-.patch
+patch 3981-drm-amd-powerplay-add-sensor-lock-support-for-smu.patch
+patch 3982-drm-amd-amdgpu-add-IH-cg-support-on-soc15-project.patch
+patch 3983-drm-amd-powerplay-bypass-dpm_context-null-pointer-ch.patch
+patch 3984-drm-amd-powerplay-implement-the-interface-for-settin.patch
+patch 3985-drm-amd-powerplay-add-interface-for-forcing-and-unfo.patch
+patch 3986-drm-amd-powerplay-add-interface-for-getting-workload.patch
+patch 3987-drm-amd-powerplay-add-the-interfaces-for-getting-and.patch
+patch 3988-drm-amd-powerplay-implement-interface-set_power_prof.patch
+patch 3989-drm-amd-powerplay-implement-the-interface-for-settin.patch
+patch 3990-drm-amd-powerplay-update-the-interface-for-getting-d.patch
+patch 3991-drm-amd-powerplay-initlialize-smu-is_apu-is-false-by.patch
+patch 3992-drm-amd-powerplay-unlock-on-error-in-smu_resume.patch
+patch 3993-drm-amd-powerplay-Fix-error-handling-in-smu_init_fb_.patch
+patch 3994-Revert-drm-amdgpu-disable-stutter-mode-for-renoir.patch
+patch 3995-drm-amdgpu-dm-Resume-short-HPD-IRQs-before-resuming-.patch
+patch 3996-drm-amdgpu-Iterate-through-DRM-connectors-correctly.patch
+patch 3997-drm-amdgpu-dm-mst-Remove-unnecessary-NULL-check.patch
+patch 3998-drm-amdgpu-dm-mst-Don-t-create-MST-topology-managers.patch
+patch 3999-drm-amdgpu-dm-mst-Use-atomic_best_encoder.patch
+patch 4000-drm-amdgpu-return-tcc_disabled_mask-to-userspace.patch
+patch 4001-drm-amd-amdgpu-sriov-ip-block-setting-of-Arcturus.patch
+patch 4002-drm-amd-display-memory-leak.patch
+patch 4003-drm-amdgpu-display_mode_vba_21-remove-uint-typedef.patch
+patch 4004-drm-amd-display-fix-spelling-mistake-AUTHENICATED-AU.patch
+patch 4005-drm-amd-display-fix-struct-init-in-update_bounding_b.patch
+patch 4006-drm-amd-display-Make-some-functions-static.patch
+patch 4007-drm-amd-display-Fix-typo-in-some-comments.patch
+patch 4008-drm-amd-display-remove-set-but-not-used-variable-cor.patch
+patch 4009-drm-amd-display-Make-function-wait_for_alt_mode-stat.patch
+patch 4010-drm-amd-display-Remove-set-but-not-used-variable-sou.patch
+patch 4011-drm-amd-display-Remove-set-but-not-used-variables-h_.patch
+patch 4012-drm-amd-display-Remove-set-but-not-used-variable-pix.patch
+patch 4013-drm-amd-display-Remove-set-but-not-used-variables-pp.patch
+patch 4014-drm-amd-powerplay-add-more-feature-bits.patch
+patch 4015-drm-amdgpu-add-lock-for-i2c-bus.patch
+patch 4016-drm-amdgpu-Delete-useless-header-file-reference.patch
+patch 4017-drm-amdkfd-Delete-unnecessary-function-declarations.patch
+patch 4018-drm-amdkfd-Use-array-to-probe-kfd2kgd_calls.patch
+patch 4019-drm-amdgpu-Add-the-HDP-flush-support-for-Navi.patch
+patch 4020-drm-amdgpu-Export-setup_vm_pt_regs-logic-for-mmhub-2.patch
+patch 4021-drm-amdkfd-Improve-KFD-IOCTL-printing.patch
+patch 4022-drm-amdgpu-enable-msix-for-amdgpu-driver.patch
+patch 4023-drm-amdgpu-don-t-increment-vram-lost-if-we-are-in-hi.patch
+patch 4024-drm-amdgpu-fix-multiple-memory-leaks-in-acp_hw_init.patch
+patch 4025-drm-amdgpu-Drop-unused-variable-and-statement.patch
+patch 4026-drm-amdgpu-remove-set-but-not-used-variable-pipe.patch
+patch 4027-drm-amdgpu-make-pmu-support-optional-again.patch
+patch 4028-drm-amdgpu-hide-another-warning.patch
+patch 4029-drm-amdgpu-work-around-llvm-bug-42576.patch
+patch 4030-drm-amdgpu-improve-MSI-X-handling-v3.patch
+patch 4031-drm-amdgpu-vcn-use-amdgpu_ring_test_helper.patch
+patch 4032-drm-amdgpu-add-code-comment-in-vcn_v2_5_hw_init.patch
+patch 4033-drm-amdgpu-fix-uninitialized-variable-pasid_mapping_.patch
+patch 4034-drm-amdgpu-remove-redundant-variable-r-and-redundant.patch
+patch 4035-drm-amdgpu-move-amdgpu_device_get_job_timeout_settin.patch
+patch 4036-drm-amdkfd-add-missing-void-argument-to-function-kgd.patch
+patch 4037-drm-amdkfd-Fix-a-vs-typo.patch
+patch 4038-drm-amdgpu-Report-vram-vendor-with-sysfs-v3.patch
+patch 4039-drm-amd-Fix-Kconfig-indentation.patch
+patch 4040-drm-amdgpu-simplify-gds_compute_max_wave_id-computat.patch
+patch 4041-drm-amdgpu-Clean-up-gmc_v9_0_gart_enable.patch
+patch 4042-drm-amdgpu-Enable-gfx-cache-probing-on-HDP-write-for.patch
+patch 4043-drm-amdgpu-swSMU-custom-UMD-pstate-peak-clock-for-na.patch
+patch 4044-drm-amd-display-Added-pixel-dynamic-expansion-contro.patch
+patch 4045-drm-amd-display-Correct-values-in-AVI-infoframe.patch
+patch 4046-drm-amd-display-skip-enable-stream-on-disconnected-d.patch
+patch 4047-drm-amd-display-Add-Logging-for-Gamma-Related-inform.patch
+patch 4048-drm-amd-display-Update-V_UPDATE-whenever-VSTARTUP-ch.patch
+patch 4049-drm-amd-display-Reprogram-FMT-on-pipe-change.patch
+patch 4050-drm-amd-display-fix-pipe-re-assignment-when-odm-pres.patch
+patch 4051-drm-amd-display-fix-hotplug-during-display-off.patch
+patch 4052-drm-amd-display-add-support-for-VSIP-info-packet.patch
+patch 4053-drm-amd-display-add-explicit-comparator-as-default-o.patch
+patch 4054-drm-amd-display-Add-missing-shifts-and-masks-for-dpp.patch
+patch 4055-drm-amd-display-3.2.52.patch
+patch 4056-drm-amd-display-build-up-VSIF-infopacket.patch
+patch 4057-drm-amd-display-check-phy-dpalt-lane-count-config.patch
+patch 4058-drm-amd-display-Restore-should_update_pstate_support.patch
+patch 4059-drm-amd-display-Properly-round-nominal-frequency-for.patch
+patch 4060-drm-amd-display-Add-output-bitrate-to-DML-calculatio.patch
+patch 4061-drm-amd-display-add-config-check-for-DSC-support.patch
+patch 4062-drm-amd-display-wait-for-set-pipe-mcp-command-comple.patch
+patch 4063-drm-amd-display-fix-bug-with-check-for-HPD-Low-in-ve.patch
+patch 4064-drm-amd-display-Use-dcn1-Optimal-Taps-Get.patch
+patch 4065-drm-amd-display-3.2.53.patch
+patch 4066-drm-amd-display-Program-DWB-watermarks-from-correct-.patch
+patch 4067-drm-amd-display-exit-PSR-during-detection.patch
+patch 4068-drm-amd-display-fix-code-to-control-48mhz-refclk.patch
+patch 4069-drm-amd-display-add-guard-for-SMU-ver-for-48mhz-clk.patch
+patch 4070-drm-amd-display-Update-number-of-dcn21-audio-endpoin.patch
+patch 4071-drm-amd-display-add-new-active-dongle-to-existent-w-.patch
+patch 4072-drm-amd-display-add-more-checks-to-validate-seamless.patch
+patch 4073-drm-amd-display-Fix-maybe-uninitialized-warning.patch
+patch 4074-drm-amd-display-use-vbios-message-to-call-smu-for-dp.patch
+patch 4075-drm-amd-display-make-aux-defer-delay-and-aux-sw-star.patch
+patch 4076-drm-amd-display-3.2.54.patch
+patch 4077-drm-amd-display-Add-capability-check-for-static-ramp.patch
+patch 4078-drm-amd-display-Fix-dongle_caps-containing-stale-inf.patch
+patch 4079-drm-amd-display-correct-stream-LTE_340MCSC_SCRAMBLE-.patch
+patch 4080-drm-amd-display-Skip-DIG-Check-if-Link-is-Virtual-fo.patch
+patch 4081-drm-amd-display-hook-up-notify-watermark-ranges-and-.patch
+patch 4082-drm-amd-display-add-renoir-specific-watermark-range-.patch
+patch 4083-drm-ttm-fix-handling-in-ttm_bo_add_mem_to_lru.patch
+patch 4084-drm-amdgpu-remove-duplicated-include-from-mmhub_v1_0.patch
+patch 4085-drm-amdgpu-ras-fix-typos-in-documentation.patch
+patch 4086-drm-amdgpu-ras-document-the-reboot-ras-option.patch
+patch 4087-drm-amdgpu-Use-the-ALIGN-macro.patch
+patch 4088-drm-amdgpu-add-amdgpu_tmz-data-structure.patch
+patch 4089-drm-amdgpu-add-tmz-feature-parameter-v2.patch
+patch 4090-drm-amdgpu-add-function-to-check-tmz-capability-v4.patch
+patch 4091-drm-amdgpu-add-tmz-bit-in-frame-control-packet.patch
+patch 4092-drm-amdgpu-expand-the-emit-tmz-interface-with-truste.patch
+patch 4093-drm-amdgpu-expand-the-context-control-interface-with.patch
+patch 4094-drm-amdgpu-add-UAPI-to-create-secure-commands-v3.patch
+patch 4095-drm-amdgpu-job-is-secure-iff-CS-is-secure-v5.patch
+patch 4096-drm-amdgpu-add-UAPI-for-creating-encrypted-buffers.patch
+patch 4097-drm-amdgpu-define-the-TMZ-bit-for-the-PTE.patch
+patch 4098-drm-amdgpu-set-TMZ-bits-in-PTEs-for-secure-BO-v4.patch
+patch 4099-Removing-the-AMDGPU-VERSION-print.patch
+patch 4100-drm-amdgpu-enable-VCN-DPG-on-Raven-and-Raven2.patch
+patch 4101-drm-amd-amdkfd-This-patch-does-not-initialize-kfd-fo.patch
+patch 4102-drm-amd-display-Fixes-the-unigine-heaven-hang-when.patch
+patch 4103-modifying-link-and-led-state-with-respect-to-cable-c.patch
+patch 4104-Fix-hot-plug-failure-with-SFP-RJ45-module.-Do-force-.patch
+patch 4105-Reverting-enable-VCN-DPG-on-Raven-and-Raven2-due-to-.patch
+patch 4106-drm-amdgpu-sdma5-fix-mask-value-of-POLL_REGMEM-packe.patch
+patch 4107-drm-amdgpu-powerplay-fix-typo-in-mvdd-table-setup.patch
+patch 4108-drm-amdgpu-powerplay-Use-swap-where-appropriate.patch
+patch 4109-drm-amdgpu-swSMU-navi-add-feature-toggles-for-more-t.patch
+patch 4110-drm-amd-powerplay-enable-df-cstate-control-on-powerp.patch
+patch 4111-drm-amd-powerplay-enable-df-cstate-control-on-swSMU-.patch
+patch 4112-drm-amdgpu-avoid-ras-error-injection-for-retired-pag.patch
+patch 4113-drm-amdgpu-fix-memory-leak.patch
+patch 4114-drm-HDMI-and-DP-specific-HDCP2.2-defines.patch
+patch 4115-drm-Add-link-training-repeaters-addresses.patch
+patch 4116-drm-amdkfd-update-for-drmP.h-removal.patch
+patch 4117-drm-amdgpu-Do-not-implement-power-on-for-SDMA-after-.patch
+patch 4118-drm-amdgpu-discovery-reserve-discovery-data-at-the-t.patch
+patch 4119-drm-amd-display-Use-swap-where-appropriate.patch
+patch 4120-drm-amdgpu-display-clean-up-dcn2-_pp_smu-functions.patch
+patch 4121-drm-amd-powerplay-re-enable-FW_DSTATE-feature-bit.patch
+patch 4122-drm-amdgpu-soc15-disable-doorbell-interrupt-as-part-.patch
+patch 4123-drm-amd-powerplay-avoid-disabling-ECC-if-RAS-is-enab.patch
+patch 4124-drm-amd-powerplay-send-EnterBaco-msg-with-argument-a.patch
+patch 4125-drm-amd-powerplay-add-BACO-platformCaps-for-VEGA20.patch
+patch 4126-drm-amdgpu-Bail-earlier-when-amdgpu.cik_-si_support-.patch
+patch 4127-drm-amdgpu-change-to-query-the-actual-EDC-counter.patch
+patch 4128-drm-amd-include-add-register-define-for-VML2-and-ATC.patch
+patch 4129-drm-amdgpu-add-RAS-support-for-VML2-and-ATCL2.patch
+patch 4130-drm-amdgpu-fix-error-handling-in-amdgpu_bo_list_crea.patch
+patch 4131-drm-amdgpu-fix-potential-VM-faults.patch
+patch 4132-drm-amdgpu-Fix-tdr3-could-hang-with-slow-compute-iss.patch
+patch 4133-drm-amd-powerplay-bug-fix-for-pcie-parameters-overri.patch
+patch 4134-drm-amd-powerplay-enable-Arcturus-runtime-VCN-dpm-on.patch
+patch 4135-drm-amdgpu-display-hook-renoir-dc-to-pplib-funcs.patch
+patch 4136-drm-amdgpu-display-fix-build-error-casused-by-CONFIG.patch
+patch 4137-drm-amd-display-change-PP_SM-defs-to-8.patch
+patch 4138-drm-amdgpu-powerplay-add-renoir-funcs-to-support-dc.patch
+patch 4139-drm-amdgpu-add-GFX_PIPELINE-capacity-check-for-updat.patch
+patch 4140-drm-amdgpu-fix-S3-failed-as-RLC-safe-mode-entry-stuc.patch
+patch 4141-drm-amdgpu-set-debug-register-values-at-init-time.patch
+patch 4142-drm-amdkfd-No-longer-support-debug-reg-data-vars.patch
+patch 4143-drm-amdkfd-Debugger-block-non-default-trap-masks.patch
+patch 4144-drm-amdgpu-user-pages-array-memory-leak-fix.patch
+patch 4145-dmr-amdgpu-Fix-crash-on-SRIOV-for-ERREVENT_ATHUB_INT.patch
+patch 4146-drm-amdgpu-move-pci_save_state-into-suspend-path.patch
+patch 4147-drm-amdgpu-move-gpu-reset-out-of-amdgpu_device_suspe.patch
+patch 4148-drm-amdgpu-remove-in_baco_reset-hack.patch
+patch 4149-drm-amdgpu-soc15-add-support-for-baco-reset-with-swS.patch
+patch 4150-drm-amdgpu-add-new-BIF-4.1-register-for-BACO.patch
+patch 4151-drm-amdgpu-add-new-BIF-5.0-register-for-BACO.patch
+patch 4152-drm-amdgpu-add-new-SMU-7.0.1-registers-for-BACO.patch
+patch 4153-drm-amdgpu-add-new-SMU-7.1.2-registers-for-BACO.patch
+patch 4154-drm-amdgpu-add-new-SMU-7.1.3-registers-for-BACO.patch
+patch 4155-drm-amdgpu-powerplay-add-core-support-for-pre-SOC15-.patch
+patch 4156-drm-amdgpu-powerplay-add-support-for-BACO-on-tonga.patch
+patch 4157-drm-amdgpu-powerplay-add-support-for-BACO-on-Iceland.patch
+patch 4158-drm-amdgpu-powerplay-add-support-for-BACO-on-polaris.patch
+patch 4159-drm-amdgpu-powerplay-add-support-for-BACO-on-VegaM.patch
+patch 4160-drm-amdgpu-powerplay-add-support-for-BACO-on-Fiji.patch
+patch 4161-drm-amdgpu-powerplay-add-support-for-BACO-on-CI.patch
+patch 4162-drm-amdgpu-powerplay-split-out-common-smu7-BACO-code.patch
+patch 4163-drm-amdgpu-powerplay-wire-up-BACO-to-powerplay-API-f.patch
+patch 4164-drm-amdgpu-enable-BACO-reset-for-SMU7-based-dGPUs-v2.patch
+patch 4165-drm-amdgpu-simplify-ATPX-detection.patch
+patch 4166-drm-amd-powerplay-bug-fix-for-memory-clock-request-f.patch
+patch 4167-drm-amdgpu-No-need-to-check-gfxoff-status-after-enab.patch
+patch 4168-drm-amd-display-update-register-field-access-mechani.patch
+patch 4169-drm-amd-display-configurable-aux-timeout-support.patch
+patch 4170-drm-amd-display-disable-ext-aux-support-for-vega.patch
+patch 4171-drm-amd-display-Add-DP_DPHY_INTERNAL_CTR-regs.patch
+patch 4172-drm-amd-display-Add-DCN_BASE-regs.patch
+patch 4173-drm-amd-display-Add-renoir-hw_seq.patch
+patch 4174-drm-amd-display-create-dcn21_link_encoder-files.patch
+patch 4175-drm-amd-display-add-REFCYC_PER_TRIP_TO_MEMORY-progra.patch
+patch 4176-drm-amd-display-move-the-bounding-box-patch-before-c.patch
+patch 4177-drm-amd-display-enable-hostvm-based-on-roimmu-active.patch
+patch 4178-drm-amd-display-fix-incorrect-page-table-address-for.patch
+patch 4179-drm-amd-display-Temporary-workaround-to-toggle-water.patch
+patch 4180-drm-amd-display-initialize-RN-gpuvm-context-programm.patch
+patch 4181-drm-amd-display-use-dcn10-version-of-program-tiling-.patch
+patch 4182-drm-amd-display-correct-dcn21-NUM_VMID-to-16.patch
+patch 4183-drm-amd-display-add-detile-buffer-size-for-renoir.patch
+patch 4184-drm-amd-display-update-dcn21-hubbub-registers.patch
+patch 4185-drm-amd-display-update-renoir-bounding-box-and-res_c.patch
+patch 4186-drm-amd-display-add-dummy-functions-to-smu-for-Renoi.patch
+patch 4187-drm-amd-display-update-odm-mode-validation-to-be-in-.patch
+patch 4188-drm-amd-display-handle-18-case-in-TruncToValidBPP.patch
+patch 4189-drm-amd-display-Fix-rn-audio-playback-and-video-play.patch
+patch 4190-drm-amd-display-add-sanity-check-for-clk-table-from-.patch
+patch 4191-drm-amd-display-fix-header-for-RN-clk-mgr.patch
+patch 4192-drm-amd-display-enable-smu-set-dcfclk.patch
+patch 4193-drm-amd-display-use-requested_dispclk_khz-instead-of.patch
+patch 4194-drm-amd-display-handle-dp-is-usb-c.patch
+patch 4195-drm-amd-display-null-check-pp_smu-clock-table-before.patch
+patch 4196-drm-amd-display-Make-dc_link_detect_helper-static.patch
+patch 4197-drm-amdgpu-soc15-remove-unused-variables.patch
+patch 4198-drm-amdgpu-fix-up-for-amdgpu_tmz.c-and-removal-of-dr.patch
+patch 4199-drm-amdgpu-uvd6-fix-allocation-size-in-enc-ring-test.patch
+patch 4200-drm-amdgpu-uvd7-fix-allocation-size-in-enc-ring-test.patch
+patch 4201-drm-amdgpu-vcn-fix-allocation-size-in-enc-ring-test.patch
+patch 4202-drm-amdgpu-powerplay-implement-interface-pp_power_pr.patch
+patch 4203-drm-amd-display-add-NULL-checks-for-clock-manager-po.patch
+patch 4204-drm-amdgpu-psp11-wait-for-sOS-ready-for-ring-creatio.patch
+patch 4205-drm-amdgpu-psp11-fix-typo-in-comment.patch
+patch 4206-drm-amdgpu-update-amdgpu_discovery-to-handle-revisio.patch
+patch 4207-drm-amdgpu-add-a-generic-fb-accessing-helper-functio.patch
+patch 4208-drm-amdgpu-introduce-psp_v11_0_is_sos_alive-interfac.patch
+patch 4209-drm-amdgpu-update-atomfirmware-header-with-memory-tr.patch
+patch 4210-drm-amdgpu-atomfirmware-add-memory-training-related-.patch
+patch 4211-drm-amdgpu-add-psp-memory-training-callbacks-and-mac.patch
+patch 4212-drm-amdgpu-reserve-vram-for-memory-training-v4.patch
+patch 4213-drm-amdgpu-psp-add-psp-memory-training-implementatio.patch
+patch 4214-drm-amdgpu-fix-amdgpu-trace-event-print-string-forma.patch
+patch 4215-drm-amdgpu-disable-c-states-on-xgmi-perfmons.patch
+patch 4216-drm-amdgpu-psp-declare-PSP-TA-firmware.patch
+patch 4217-drm-amdgpu-fix-compiler-warnings-for-df-perfmons.patch
+patch 4218-drm-amdgpu-vce-fix-allocation-size-in-enc-ring-test.patch
+patch 4219-drm-amdgpu-vce-make-some-functions-static.patch
+patch 4220-drm-amdgpu-vi-silence-an-uninitialized-variable-warn.patch
+patch 4221-drm-amdgpu-revert-calling-smu-msg-in-df-callbacks.patch
+patch 4222-drm-amdgpu-psp-fix-spelling-mistake-initliaze-initia.patch
+patch 4223-drm-amd-display-setting-the-DIG_MODE-to-the-correct-.patch
+patch 4224-drm-amd-display-Free-gamma-after-calculating-legacy-.patch
+patch 4225-drm-amdgpu-powerplay-use-local-renoir-array-sizes-fo.patch
+patch 4226-drm-amd-powerplay-update-Arcturus-driver-smu-interfa.patch
+patch 4227-drm-amd-display-Avoid-sending-abnormal-VSIF.patch
+patch 4228-drm-amd-display-add-50us-buffer-as-WA-for-pstate-swi.patch
+patch 4229-drm-amd-display-add-odm-visual-confirm.patch
+patch 4230-drm-amd-display-Add-unknown-clk-state.patch
+patch 4231-drm-amd-display-Don-t-use-optimized-gamma22-with-eet.patch
+patch 4232-drm-amd-display-Remove-superfluous-assert.patch
+patch 4233-drm-amd-display-remove-unused-code.patch
+patch 4234-drm-amd-display-3.2.55.patch
+patch 4235-drm-amd-display-Add-debugfs-entry-for-reading-psr-st.patch
+patch 4236-drm-amd-display-Enable-PSR.patch
+patch 4237-drm-amd-display-correctly-populate-dpp-refclk-in-fpg.patch
+patch 4238-drm-amd-display-split-dcn20-fast-validate-into-more-.patch
+patch 4239-drm-amd-display-correctly-initialize-dml-odm-variabl.patch
+patch 4240-drm-amd-display-move-dispclk-vco-freq-to-clk-mgr-bas.patch
+patch 4241-drm-amd-display-remove-unnecessary-assert.patch
+patch 4242-drm-amd-display-Fix-MPO-pipe-split-on-3-pipe-dcn2x.patch
+patch 4243-drm-amd-display-audio-endpoint-cannot-switch.patch
+patch 4244-drm-amd-display-Update-min-dcfclk.patch
+patch 4245-drm-amd-display-Allow-inverted-gamma.patch
+patch 4246-drm-amd-display-enable-vm-by-default-for-rn.patch
+patch 4247-drm-amd-display-fix-number-of-dcn21-dpm-clock-levels.patch
+patch 4248-drm-amd-display-add-embedded-flag-to-dml.patch
+patch 4249-drm-amd-display-add-flag-to-allow-diag-to-force-enum.patch
+patch 4250-drm-amd-display-Passive-DP-HDMI-dongle-detection-fix.patch
+patch 4251-drm-amd-display-Disable-force_single_disp_pipe_split.patch
+patch 4252-drm-amd-display-Proper-return-of-result-when-aux-eng.patch
+patch 4253-drm-amd-display-do-not-synchronize-drr-displays.patch
+patch 4254-drm-amd-display-move-wm-ranges-reporting-to-end-of-i.patch
+patch 4255-drm-amd-display-Only-use-EETF-when-maxCL-max-display.patch
+patch 4256-drm-amd-display-Make-clk-mgr-the-only-dto-update-poi.patch
+patch 4257-drm-amd-display-3.2.56.patch
+patch 4258-drm-amd-display-take-signal-type-from-link.patch
+patch 4259-drm-amd-display-Add-center-mode-for-integer-scaling-.patch
+patch 4260-drm-amd-display-Do-not-call-update-bounding-box-on-d.patch
+patch 4261-drm-amd-display-fix-avoid_split-for-dcn2-validation.patch
+patch 4262-drm-amd-display-fix-hubbub-deadline-programing.patch
+patch 4263-drm-amd-display-Apply-vactive-dram-clock-change-work.patch
+patch 4264-drm-amdgpu-vcn-Enable-VCN2.5-encoding.patch
+patch 4265-drm-amdgpu-add-VCN0-and-VCN1-needed-headers.patch
+patch 4266-drm-amd-powerplay-add-lock-protection-for-swSMU-APIs.patch
+patch 4267-drm-amd-powerplay-split-out-those-internal-used-swSM.patch
+patch 4268-drm-amd-powerplay-clear-the-swSMU-code-layer.patch
+patch 4269-drm-amdgpu-display-add-dc-feature-mask-for-psr-enabl.patch
+patch 4270-drm-amd-display-Change-Navi14-s-DWB-flag-to-1.patch
+patch 4271-drm-amdkfd-don-t-use-dqm-lock-during-device-reset-su.patch
+patch 4272-drm-amdgpu-refine-reboot-debugfs-operation-in-ras-ca.patch
+patch 4273-drm-amdgpu-define-macros-for-retire-page-reservation.patch
+patch 4274-drm-amdgpu-Fix-SDMA-hang-when-performing-VKexample-t.patch
+patch 4275-drm-amdgpu-sdma5-do-not-execute-0-sized-IBs-v2.patch
+patch 4276-drm-amdgpu-remove-unused-parameter-in-amdgpu_gfx_kiq.patch
+patch 4277-drm-amdgpu-Add-DC-feature-mask-to-disable-fractional.patch
+patch 4278-drm-amd-powerplay-Add-interface-for-I2C-transactions.patch
+patch 4279-drm-amd-powerplay-Add-EEPROM-I2C-read-write-support-.patch
+patch 4280-drm-amdgpu-Use-ARCTURUS-in-RAS-EEPROM.patch
+patch 4281-drm-amdgpu-Move-amdgpu_ras_recovery_init-to-after-SM.patch
+patch 4282-drm-amdgpu-Allow-reading-more-status-registers-on-si.patch
+patch 4283-drm-amd-powerplay-skip-unsupported-clock-limit-setti.patch
+patch 4284-drm-amd-powerplay-correct-current-clock-level-label-.patch
+patch 4285-drm-amdgpu-call-amdgpu_vm_prt_fini-before-deleting-t.patch
+patch 4286-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
+patch 4287-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
+patch 4288-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
+patch 4289-drm-amd-display-setting-the-DIG_MODE-to-the-correct-.patch
+patch 4290-drm-amdgpu-powerplay-modify-the-parameters-of-SMU_MS.patch
+patch 4291-drm-sched-Set-error-to-s_fence-if-HW-job-submission.patch
+patch 4292-drm-amdgpu-If-amdgpu_ib_schedule-fails-return-back-t.patch
+patch 4293-drm-amd-display-fix-dcn21-Makefile-for-clang.patch
+patch 4294-drm-amd-display-remove-gcc-warning-Wunused-but-set-v.patch
+patch 4295-drm-amdgpu-display-fix-mixed-declarations-and-code.patch
+patch 4296-drm-amd-powerplay-Disable-gfx-CGPG-when-suspend-smu.patch
+patch 4297-drm-amdgpu-powerplay-vega10-allow-undervolting-in-p7.patch
+patch 4298-drm-amd-powerplay-Make-two-functions-static.patch
+patch 4299-drm-amd-display-Make-calculate_integer_scaling-stati.patch
+patch 4300-drm-amd-declare-amdgpu_exp_hw_support-in-amdgpu.h.patch
+patch 4301-drm-amd-correct-_LENTH-mispelling-in-constant.patch
+patch 4302-drm-amdgpu-remove-set-but-not-used-variable-adev.patch
+patch 4303-drm-amdgpu-Remove-superfluous-void-cast-in-debugfs_c.patch
+patch 4304-drm-amdkfd-Delete-unnecessary-pr_fmt-switch.patch
+patch 4305-drm-amdkfd-Delete-duplicated-queue-bit-map-reservati.patch
+patch 4306-drm-amdkfd-bug-fix-for-out-of-bounds-mem-on-gpu-cach.patch
+patch 4307-drm-amd-display-Add-ENGINE_ID_DIGD-condition-check-f.patch
+patch 4308-drm-amdgpu-fix-stack-alignment-ABI-mismatch-for-Clan.patch
+patch 4309-drm-amdgpu-fix-stack-alignment-ABI-mismatch-for-GCC-.patch
+patch 4310-drm-amdgpu-enable-msse2-for-GCC-7.1-users.patch
+patch 4311-drm-amdgpu-SRIOV-SRIOV-VF-doesn-t-support-BACO.patch
+patch 4312-drm-amdgpu-clear-UVD-VCPU-buffer-when-err_event_athu.patch
+patch 4313-drm-amdgpu-bypass-some-cleanup-work-after-err_event_.patch
+patch 4314-drm-amdgpu-add-missing-amdgpu_ras.h-header-include.patch
+patch 4315-drm-amdgpu-fix-gfx-VF-FLR-test-fail-on-navi.patch
+patch 4316-drm-amdkfd-Delete-unnecessary-pr_fmt-switch.patch
+patch 4317-drm-amdgpu-fix-no-ACK-from-LDS-read-during-stress-te.patch
+patch 4318-drm-amdgpu-gmc10-properly-set-BANK_SELECT-and-FRAGME.patch
+patch 4319-drm-amdgpu-arcturus-properly-set-BANK_SELECT-and-FRA.patch
+patch 4320-drm-amd-display-remove-redundant-null-pointer-check-.patch
+patch 4321-drm-amd-display-Add-a-conversion-function-for-transm.patch
+patch 4322-drm-amdgpu-dont-schedule-jobs-while-in-reset.patch
+patch 4323-drm-amdgpu-Add-ucode-support-for-DMCUB.patch
+patch 4324-drm-amdgpu-Add-PSP-loading-support-for-DMCUB-ucode.patch
+patch 4325-drm-amd-display-Drop-DMCUB-from-DCN21-resources.patch
+patch 4326-drm-amd-display-Add-the-DMUB-service.patch
+patch 4327-drm-amd-display-Change-dmcu-init-sequence-for-dmcub-.patch
+patch 4328-drm-amd-display-Add-PSP-FW-version-mask.patch
+patch 4329-drm-amd-display-Hook-up-the-DMUB-service-in-DM.patch
+patch 4330-drm-amdgpu-Add-DMCUB-to-firmware-query-interface.patch
+patch 4331-drm-amd-display-Add-DMUB-support-to-DC.patch
+patch 4332-drm-amd-display-Register-DMUB-service-with-DC.patch
+patch 4333-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DMUB-guards.patch
+patch 4334-drm-ttm-bug-fix-for-sproadic-hard-hang-during-closin.patch
+patch 4335-drm-amdgpu-change-pstate-only-after-all-XGMI-device-.patch
+patch 4336-drm-amd-powerplay-update-is_sw_smu_xgmi-check.patch
+patch 4337-drm-amd-powerplay-support-xgmi-pstate-setting-on-pow.patch
+patch 4338-drm-amdgpu-add-navi14-PCI-ID-for-new-work-station-SK.patch
+patch 4339-drm-amdgpu-gpuvm-add-some-additional-comments-in-amd.patch
+patch 4340-drm-amdgpu-Show-resolution-correctly-in-mode-validat.patch
+patch 4341-drm-amd-powerplay-print-the-pptable-provider.patch
+patch 4342-drm-amdgpu-discovery-Need-to-free-discovery-memory.patch
+patch 4343-drm-sched-Fix-passing-zero-to-PTR_ERR-warning-v2.patch
+patch 4344-Revert-drm-amd-display-setting-the-DIG_MODE-to-the-c.patch
+patch 4345-drm-amdgpu-disallow-direct-upload-save-restore-list-.patch
+patch 4346-drm-amd-display-3.2.57.patch
+patch 4347-drm-amd-display-Fix-assert-observed-when-performing-.patch
+patch 4348-drm-amd-display-Renoir-chroma-viewport-WA.patch
+patch 4349-drm-amd-display-Use-SIGNAL_TYPE_NONE-in-disable_outp.patch
+patch 4350-drm-amd-display-Add-a-sanity-check-for-DSC-already-e.patch
+patch 4351-drm-amd-display-set-MSA-MISC1-bit-6-while-sending-co.patch
+patch 4352-drm-amd-display-Create-debug-option-to-disable-v.act.patch
+patch 4353-drm-amd-display-optimize-bandwidth-after-commit-stre.patch
+patch 4354-drm-amd-powerplay-fix-deadlock-on-setting-power_dpm_.patch
+patch 4355-drm-amd-display-3.2.58.patch
+patch 4356-drm-amd-display-Add-some-hardware-status-in-DTN-log-.patch
+patch 4357-drm-amd-display-add-oem-i2c-implemenation-in-dc.patch
+patch 4358-drm-amd-display-Unify-all-scaling-when-Integer-Scali.patch
+patch 4359-drm-amd-powerplay-update-Arcturus-driver-smu-interfa.patch
+patch 4360-drm-amd-swSMU-fix-smu-workload-bit-map-error.patch
+patch 4361-drm-amdgpu-register-gpu-instance-before-fan-boost-fe.patch
+patch 4362-drm-amdgpu-fix-possible-pstate-switch-race-condition.patch
+patch 4363-drm-amdgpu-perform-p-state-switch-after-the-whole-hi.patch
+patch 4364-drm-amdgpu-add-dummy-read-by-engines-for-some-GCVM-s.patch
+patch 4365-drm-amdgpu-add-warning-for-GRBM-1-cycle-delay-issue-.patch
+patch 4366-drm-amdgpu-change-read-of-GPU-clock-counter-on-Vega1.patch
+patch 4367-drm-amdgpu-remove-4-set-but-not-used-variable-in-amd.patch
+patch 4368-drm-amdgpu-add-function-parameter-description-in-amd.patch
+patch 4369-drm-amdgpu-add-function-parameter-description-in-amd.patch
+patch 4370-drm-amdgpu-remove-set-but-not-used-variable-dig_conn.patch
+patch 4371-drm-amdgpu-remove-set-but-not-used-variable-dig.patch
+patch 4372-drm-amdgpu-remove-always-false-comparison-in-amdgpu_.patch
+patch 4373-drm-amdgpu-remove-set-but-not-used-variable-mc_share.patch
+patch 4374-drm-amdgpu-fix-potential-double-drop-fence-reference.patch
+patch 4375-drm-amd-powerplay-fix-struct-init-in-renoir_print_cl.patch
+patch 4376-drm-amdgpu-fix-double-reference-dropping.patch
+patch 4377-drm-amdgpu-renoir-move-gfxoff-handling-into-gfx9-mod.patch
+patch 4378-drm-amdgpu-Improve-RAS-documentation-v2.patch
+patch 4379-drm-amd-display-Send-vblank-and-user-events-at-vsart.patch
+patch 4380-drm-amd-display-Disable-VUpdate-interrupt-for-DCN-ha.patch
+patch 4381-drm-amdgpu-Add-comments-to-gmc-structure.patch
+patch 4382-drm-amd-include-Add-gfx10-debugger-registers.patch
+patch 4383-drm-amdkfd-Add-kfd-debugger-support-for-gfx10.patch
+patch 4384-drm-amdgpu-Need-to-disable-msix-when-unloading-drive.patch
+patch 4385-drm-amdgpu-fix-sysfs-interface-pcie_replay_count-err.patch
+patch 4386-Revert-drm-amdgpu-Need-to-disable-msix-when-unloadin.patch
+patch 4387-SWDEV-210749-drm-amdgpu-Need-to-disable-msix-when-un.patch
+patch 4388-drm-amdgpu-allow-direct-upload-save-restore-list-for.patch
+patch 4389-drm-amd-amdgpu-finish-delay-works-before-release-res.patch
+patch 4390-drm-amdgpu-fix-vega20-pstate-status-change.patch
+patch 4391-drm-sched-Use-completion-to-wait-for-sched-thread-id.patch
+patch 4392-drm-amdgpu-Avoid-accidental-thread-thread-reactivati.patch
+patch 4393-drm-amdkfd-Adjust-function-sequences-to-avoid-unnece.patch
+patch 4394-drm-amdkfd-Only-keep-release_mem-function-for-Hawaii.patch
+patch 4395-drm-amd-display-initialize-lttpr.patch
+patch 4396-drm-amd-display-check-for-dp-rev-before-reading-lttp.patch
+patch 4397-drm-amd-display-configure-lttpr-mode.patch
+patch 4398-drm-amd-display-implement-lttpr-logic.patch
+patch 4399-drm-amd-display-use-previous-aux-timeout-val-if-no-r.patch
+patch 4400-drm-amd-display-disable-lttpr-for-invalid-lttpr-caps.patch
+patch 4401-drm-amd-powerplay-correct-Arcturus-OD-support.patch
+patch 4402-drm-amdkfd-Use-kernel-queue-v9-functions-for-v10.patch
+patch 4403-drm-amdkfd-Simplify-the-mmap-offset-related-bit-oper.patch
+patch 4404-drm-amd-powerplay-dynamically-disable-ds-and-ulv-for.patch
+patch 4405-drm-amdgpu-powerplay-fix-AVFS-handling-with-custom-p.patch
+patch 4406-drm-amd-display-remove-duplicated-assignment-to-grph.patch
+patch 4407-drm-amd-display-remove-redundant-variable-status.patch
+patch 4408-drm-amdgpu-avoid-upload-corrupted-ta-ucode-to-psp.patch
+patch 4409-drm-amdgpu-powerplay-smu7-fix-AVFS-handling-with-cus.patch
+patch 4410-drm-amd-display-remove-duplicated-comparison-express.patch
+patch 4411-drm-amd-powerplay-remove-set-but-not-used-variable-v.patch
+patch 4412-drm-amd-powerplay-remove-set-but-not-used-variable-d.patch
+patch 4413-drm-amd-display-Use-static-const-not-const-static.patch
+patch 4414-drm-amd-powerplay-remove-set-but-not-used-variable-t.patch
+patch 4415-drm-amd-display-remove-set-but-not-used-variable-ds_.patch
+patch 4416-drm-amdgpu-navi10-implement-sclk-mclk-OD-via-pp_od_c.patch
+patch 4417-drm-amdgpu-navi10-implement-GFXCLK_CURVE-overdrive.patch
+patch 4418-drm-amdgpu-navi10-Implement-od-clk-printing.patch
+patch 4419-drm-amdgpu-smu_v11-Unify-and-fix-power-limits.patch
+patch 4420-drm-amdkfd-Use-better-name-to-indicate-the-offset-is.patch
+patch 4421-drm-amdkfd-Avoid-using-doorbell_off-as-offset-in-pro.patch
+patch 4422-drm-amdkfd-Rename-create_cp_queue-to-init_user_queue.patch
+patch 4423-drm-amd-powerplay-read-pcie-speed-width-info.patch
+patch 4424-drm-amdgpu-vcn-finish-delay-work-before-release-reso.patch
+patch 4425-drm-amd-display-remove-set-but-not-used-variable-bpc.patch
+patch 4426-drm-amdkfd-Implement-queue-priority-controls-for-gfx.patch
+patch 4427-drm-amdkfd-Update-get_wave_state-for-GFX10.patch
+patch 4428-drm-amdkfd-Use-QUEUE_IS_ACTIVE-macro-in-mqd-v10.patch
+patch 4429-drm-amdkfd-Stop-using-GFP_NOIO-explicitly-for-two-pl.patch
+patch 4430-drm-amdgpu-remove-set-but-not-used-variable-mc_share.patch
+patch 4431-drm-amdgpu-remove-set-but-not-used-variable-amdgpu_c.patch
+patch 4432-drm-amdgpu-remove-set-but-not-used-variable-count.patch
+patch 4433-drm-amdgpu-remove-set-but-not-used-variable-invalid.patch
+patch 4434-drm-amd-powerplay-remove-set-but-not-used-variable-u.patch
+patch 4435-drm-amdkfd-Merge-CIK-kernel-queue-functions-into-VI.patch
+patch 4436-drm-amdkfd-Eliminate-ops_asic_specific-in-kernel-que.patch
+patch 4437-drm-amdkfd-Rename-kfd_kernel_queue_-.c-to-kfd_packet.patch
+patch 4438-drm-amdgpu-powerplay-properly-set-PP_GFXOFF_MASK.patch
+patch 4439-drm-amdgpu-don-t-read-registers-if-gfxoff-is-enabled.patch
+patch 4440-drm-amdgpu-enable-ras-capablity-check-on-arcturus.patch
+patch 4441-drm-amdgpu-init-umc-functions-for-arcturus-umc-ras.patch
+patch 4442-drm-amdgpu-gfx10-fix-mqd-backup-restore-for-gfx-ring.patch
+patch 4443-drm-amdgpu-add-JPEG-HW-IP-and-SW-structures.patch
+patch 4444-drm-amdgpu-add-amdgpu_jpeg-and-JPEG-tests.patch
+patch 4445-drm-amdgpu-separate-JPEG1.0-code-out-from-VCN1.0.patch
+patch 4446-drm-amdgpu-use-the-JPEG-structure-for-general-driver.patch
+patch 4447-drm-amdgpu-add-JPEG-IP-block-type.patch
+patch 4448-drm-amdgpu-add-JPEG-common-functions-to-amdgpu_jpeg.patch
+patch 4449-drm-amdgpu-add-JPEG-v2.0-function-supports.patch
+patch 4450-drm-amdgpu-remove-unnecessary-JPEG2.0-code-from-VCN2.patch
+patch 4451-drm-amdgpu-add-JPEG-PG-and-CG-interface.patch
+patch 4452-drm-amdgpu-add-PG-and-CG-for-JPEG2.0.patch
+patch 4453-drm-amd-powerplay-add-JPEG-Powerplay-interface.patch
+patch 4454-drm-amd-powerplay-add-JPEG-power-control-for-Navi1x.patch
+patch 4455-drm-amd-powerplay-add-Powergate-JPEG-for-Renoir.patch
+patch 4456-drm-amd-powerplay-add-JPEG-power-control-for-Renoir.patch
+patch 4457-drm-amd-powerplay-set-JPEG-to-SMU-dpm.patch
+patch 4458-drm-amdgpu-enable-JPEG2.0-dpm.patch
+patch 4459-drm-amdgpu-add-driver-support-for-JPEG2.0-and-above.patch
+patch 4460-drm-amdgpu-enable-JPEG2.0-for-Navi1x-and-Renoir.patch
+patch 4461-drm-amdgpu-move-JPEG2.5-out-from-VCN2.5.patch
+patch 4462-drm-amdgpu-enable-Arcturus-CG-for-VCN-and-JPEG-block.patch
+patch 4463-drm-amdgpu-enable-Arcturus-JPEG2.5-block.patch
+patch 4464-drm-amd-display-remove-set-but-not-used-variable-old.patch
+patch 4465-drm-amd-display-remove-set-but-not-used-variable-bp-.patch
+patch 4466-drm-amd-display-remove-set-but-not-used-variable-bp-.patch
+patch 4467-drm-amd-display-remove-set-but-not-used-variable-min.patch
+patch 4468-drm-amdgpu-dm-Do-not-throw-an-error-for-a-display-wi.patch
+patch 4469-drm-amd-powerplay-avoid-DPM-reenable-process-on-Navi.patch
+patch 4470-drm-amd-powerplay-issue-BTC-on-Navi-during-SMU-setup.patch
+patch 4471-drm-amd-powerplay-issue-no-PPSMC_MSG_GetCurrPkgPwr-o.patch
+patch 4472-drm-amd-powerplay-correct-fine-grained-dpm-force-lev.patch
+patch 4473-drm-amd-display-Renoir-chroma-viewport-WA-change-for.patch
+patch 4474-drm-amd-display-Renoir-chroma-viewport-WA-Read-the-c.patch
+patch 4475-drm-amd-display-Add-hubp-clock-status-in-DTN-log-for.patch
+patch 4476-drm-amd-display-Update-background-color-in-bottommos.patch
+patch 4477-drm-amd-display-3.2.59.patch
+patch 4478-drm-amd-display-Fix-stereo-with-DCC-enabled.patch
+patch 4479-drm-amd-display-Changes-in-dc-to-allow-full-update-i.patch
+patch 4480-drm-amd-display-Add-DMUB-service-function-check-if-h.patch
+patch 4481-drm-amd-display-Add-DMUB-param-to-load-inst-const-fr.patch
+patch 4482-drm-amd-display-Add-debugfs-initalization-on-mst-con.patch
+patch 4483-drm-amd-display-Connect-DIG-FE-to-its-BE-before-link.patch
+patch 4484-drm-amd-display-Clean-up-some-code-with-unused-regis.patch
+patch 4485-drm-amd-display-revert-change-causing-DTN-hang-for-R.patch
+patch 4486-drm-amd-display-Fix-debugfs-on-MST-connectors.patch
+patch 4487-drm-amd-display-cleanup-of-construct-and-destruct-fu.patch
+patch 4488-drm-amd-display-add-color-space-option-when-sending-.patch
+patch 4489-drm-amd-display-Adjust-DML-workaround-threshold.patch
+patch 4490-drm-amd-display-Add-debug-trace-for-dmcub-FW-autoloa.patch
+patch 4491-drm-amd-display-3.2.60.patch
+patch 4492-drm-amd-display-add-debugfs-sdp-hook-up-function-for.patch
+patch 4493-drm-amd-display-Avoid-conflict-between-HDR-multiplie.patch
+patch 4494-drm-amd-display-Don-t-spin-forever-waiting-for-DMCUB.patch
+patch 4495-drm-amd-display-DML-Validation-Dump-Check-with-Loggi.patch
+patch 4496-drm-amd-display-Spin-for-DMCUB-PHY-init-in-DC.patch
+patch 4497-drm-amd-display-Add-DSC-422Native-debug-option.patch
+patch 4498-drm-amd-display-Add-Navi10-DMUB-VBIOS-code.patch
+patch 4499-drm-amd-display-add-automated-audio-test-support.patch
+patch 4500-drm-amd-display-Add-PSP-block-to-verify-HDCP2.2-step.patch
+patch 4501-drm-amd-display-Add-DDC-handles-for-HDCP2.2.patch
+patch 4502-drm-amd-display-Add-execution-and-transition-states-.patch
+patch 4503-drm-amd-display-Add-logging-for-HDCP2.2.patch
+patch 4504-drm-amd-display-Change-ERROR-to-WARN-for-HDCP-module.patch
+patch 4505-drm-amd-display-Enable-HDCP-2.2.patch
+patch 4506-drm-amd-display-Handle-hdcp2.2-type0-1-in-dm.patch
+patch 4507-drm-amd-display-Refactor-HDCP-to-handle-multiple-dis.patch
+patch 4508-drm-amd-display-add-force-Type0-1-flag.patch
+patch 4509-drm-amd-display-Refactor-HDCP-encryption-status-upda.patch
+patch 4510-drm-amd-display-add-and-use-defines-from-drm_hdcp.h.patch
+patch 4511-drm-amd-display-use-drm-defines-for-MAX-CASCADE-MASK.patch
+patch 4512-drm-amd-display-split-rxstatus-for-hdmi-and-dp.patch
+patch 4513-drm-amd-display-Fix-static-analysis-bug-in-validate_.patch
+patch 4514-drm-amdkfd-remove-set-but-not-used-variable-top_dev.patch
+patch 4515-drm-amdgpu-vcn2.5-fix-the-enc-loop-with-hw-fini.patch
+patch 4516-drm-amdgpu-put-flush_dealyed_work-at-first.patch
+patch 4517-drm-amdgpu-soc15-move-struct-definition-around-to-al.patch
+patch 4518-drm-amdgpu-nv-add-asic-func-for-fetching-vbios-from-.patch
+patch 4519-drm-amdgpu-fix-bad-DMA-from-INTERRUPT_CNTL2.patch
+patch 4520-Revert-drm-amdgpu-don-t-read-registers-if-gfxoff-is-.patch
+patch 4521-drm-amdgpu-remove-not-needed-memset.patch
+patch 4522-drm-amdgpu-expand-sdma-copy_buffer-interface-with-tm.patch
+patch 4523-drm-amdgpu-expand-amdgpu_copy_buffer-interface-with-.patch
+patch 4524-drm-amdgpu-enable-TMZ-bit-in-sdma-copy-pkt-for-sdma-.patch
+patch 4525-drm-amdgpu-enable-TMZ-bit-in-sdma-copy-pkt-for-sdma-.patch
+patch 4526-drm-amdgpu-enable-TMZ-bit-in-FRAME_CONTROL-for-gfx10.patch
+patch 4527-drm-amdgpu-powerplay-fix-dereference-before-null-che.patch
+patch 4528-drm-amd-powerplay-return-errno-code-to-caller-when-e.patch
+patch 4529-drm-amd-powerplay-correct-swSMU-baco-reset-related-s.patch
+patch 4530-drm-amd-powerplay-add-Arcturus-baco-reset-support.patch
+patch 4531-drm-amd-powerplay-add-missing-header-file-declaratio.patch
+patch 4532-drm-amdgpu-add-psp-funcs-for-ring-write-pointer-read.patch
+patch 4533-drm-amdgpu-add-helper-func-for-psp-ring-cmd-submissi.patch
+patch 4534-drm-amdgpu-switch-to-common-helper-func-for-psp-cmd-.patch
+patch 4535-drm-amdgpu-pull-ras-controller-int-status-only-when-.patch
+patch 4536-drm-amd-powerplay-enable-gpu_busy_percent-sys-interf.patch
+patch 4537-drm-amdgpu-disable-gfxoff-when-using-register-read-i.patch
+patch 4538-drm-amdgpu-add-asic-callback-for-BACO-support.patch
+patch 4539-drm-amdgpu-add-supports_baco-callback-for-soc15-asic.patch
+patch 4540-drm-amdgpu-add-supports_baco-callback-for-SI-asics.patch
+patch 4541-drm-amdgpu-add-supports_baco-callback-for-CIK-asics.patch
+patch 4542-drm-amdgpu-add-supports_baco-callback-for-VI-asics.patch
+patch 4543-drm-amdgpu-add-supports_baco-callback-for-NV-asics.patch
+patch 4544-drm-amdgpu-add-a-amdgpu_device_supports_baco-helper.patch
+patch 4545-drm-amdgpu-rename-amdgpu_device_is_px-to-amdgpu_devi.patch
+patch 4546-drm-amdgpu-add-additional-boco-checks-to-runtime-sus.patch
+patch 4547-drm-amdgpu-split-swSMU-baco_reset-into-enter-and-exi.patch
+patch 4548-drm-amdgpu-add-helpers-for-baco-entry-and-exit.patch
+patch 4549-drm-amdgpu-add-baco-support-to-runtime-suspend-resum.patch
+patch 4550-drm-amdgpu-start-to-disentangle-boco-from-runtime-pm.patch
+patch 4551-drm-amdgpu-disentangle-runtime-pm-and-vga_switcheroo.patch
+patch 4552-drm-amdgpu-enable-runtime-pm-on-BACO-capable-boards-.patch
+patch 4553-drm-amdgpu-add-flag-to-indicate-amdgpu-vm-context.patch
+patch 4554-amd-amdgpu-force-to-trigger-a-no-retry-fault-after-a.patch
+patch 4555-drm-amd-display-Drop-CONFIG_DRM_AMD_DC_DCN2_0-and-DS.patch
+patch 4556-drm-amdgpu-gfx10-explicitly-wait-for-cp-idle-after-h.patch
+patch 4557-drm-amdgpu-gfx10-re-init-clear-state-buffer-after-gp.patch
+patch 4558-drm-amdgpu-gfx10-fix-out-of-bound-mqd_backup-array-a.patch
+patch 4559-drm-amdgpu-define-soc15_ras_field_entry-for-reuse.patch
+patch 4560-drm-amdgpu-refine-query-function-of-mmhub-EDC-counte.patch
+patch 4561-drm-amdgpu-implement-querying-ras-error-count-for-mm.patch
+patch 4562-drm-amdgpu-Update-Arcturus-golden-registers.patch
+patch 4563-drm-amd-display-Change-mmhub_9_4_0_-headers-to-mmhub.patch
+patch 4564-drm-amdkfd-Delete-KFD_MQD_TYPE_COMPUTE.patch
+patch 4565-drm-amdkfd-DIQ-should-not-use-HIQ-way-to-allocate-me.patch
+patch 4566-drm-amdgpu-initialize-vm_inv_eng0_sem-for-gfxhub-and.patch
+patch 4567-drm-amdgpu-simplify-runtime-suspend.patch
+patch 4568-drm-amdgpu-remove-redundant-assignment-to-pointer-wr.patch
+patch 4569-Revert-drm-amdgpu-gfx10-re-init-clear-state-buffer-a.patch
+patch 4570-drm-amdgpu-gfx10-re-init-clear-state-buffer-after-gp.patch
+patch 4571-drm-amdkfd-add-kfd-missing-patch.patch
+patch 4572-drm-amdkfd-add-missing-KFD_MQD_TYPE_COMPUTE.patch
+patch 4573-drm-amdkfd-add-missing-mqd-init-from-kfd-staging.patch
+patch 4574-drm-amdgpu-disable-gfxoff-on-original-raven.patch
+patch 4575-Revert-drm-amd-display-enable-S-G-for-RAVEN-chip.patch
+patch 4576-drm-amd-amdgpu-sriov-temporarily-skip-ras-dtm-hdcp-f.patch
+patch 4577-drm-amd-amdgpu-sriov-skip-RLCG-s-r-list-for-arcturus.patch
+patch 4578-drm-amdgpu-invalidate-mmhub-semaphore-workaround-in-.patch
+patch 4579-drm-amdkfd-Remove-duplicate-functions-update_mqd_hiq.patch
+patch 4580-drm-amd-powerplay-Use-ARRAY_SIZE-for-smu7_profiling.patch
+patch 4581-drm-amdgpu-Use-ARRAY_SIZE-for-sos_old_versions.patch
+patch 4582-drm-amd-display-add-default-clocks-if-not-able-to-fe.patch
+patch 4583-drm-amdgpu-Apply-noretry-setting-for-mmhub9.4.patch
+patch 4584-Revert-drm-amd-powerplay-read-pcie-speed-width-info.patch
+patch 4585-drm-amd-powerplay-read-pcie-speed-width-info-v2.patch
+patch 4586-Revert-drm-amd-powerplay-enable-gpu_busy_percent-sys.patch
+patch 4587-drm-amd-powerplay-enable-gpu_busy_percent-sys-interf.patch
+patch 4588-Revert-drm-amdkfd-add-missing-mqd-init-from-kfd-stag.patch
+patch 4589-Revert-drm-amdkfd-add-missing-KFD_MQD_TYPE_COMPUTE.patch
+patch 4590-drm-amd-amdgpu-sriov-skip-jpeg-ip-block-for-ARCTURUS.patch
+patch 4591-drm-amdgpu-Resolved-offchip-EEPROM-I-O-issue.patch
+patch 4592-drm-amd-Fix-Kconfig-indentation.patch
+patch 4593-MAINTAINERS-Drop-Rex-Zhu-for-amdgpu-powerplay.patch
+patch 4594-drm-amd-powerplay-remove-redundant-assignment-to-var.patch
+patch 4595-drm-amdgpu-Ensure-ret-is-always-initialized-when-usi.patch
+patch 4596-drm-amd-display-remove-set-but-not-used-variable-msg.patch
+patch 4597-drm-amd-powerplay-remove-set-but-not-used-variable-s.patch
+patch 4598-drm-amd-display-Null-check-aconnector-in-event_prope.patch
+patch 4599-drm-amdgpu-Raise-KFD-unpinned-system-memory-limit.patch
+patch 4600-drm-amdgpu-Optimize-KFD-page-table-reservation.patch
+patch 4601-drm-amdgpu-apply-gpr-gds-workaround-before-enabling-.patch
+patch 4602-drm-amdgpu-move-pci-handling-out-of-pm-ops.patch
+patch 4603-drm-amdgpu-flag-vram-lost-on-baco-reset-for-VI-CIK.patch
+patch 4604-drm-amdgpu-Fix-a-bug-in-jpeg_v1_0_start.patch
+patch 4605-drm-amd-display-Modify-comments-to-match-the-code.patch
+patch 4606-drm-amdkfd-Eliminate-unnecessary-kernel-queue-functi.patch
+patch 4607-drm-amdgpu-gfx10-unlock-srbm_mutex-after-queue-progr.patch
+patch 4608-drm-amdgpu-gfx10-remove-outdated-comments.patch
+patch 4609-drm-amdgpu-gfx-Clear-more-EDC-cnt.patch
+patch 4610-drm-amdgpu-gfx-Increase-dispatch-packet-number.patch
+patch 4611-drm-amd-display-Include-num_vmid-and-num_dsc-within-.patch
+patch 4612-drm-amd-display-Drop-AMD_EDID_UTILITY-defines.patch
+patch 4613-drm-amdgpu-fix-calltrace-during-kmd-unload-v3.patch
+patch 4614-drm-amdgpu-skip-rlc-ucode-loading-for-SRIOV-gfx10.patch
+patch 4615-drm-amdgpu-do-autoload-right-after-MEC-loaded-for-SR.patch
+patch 4616-drm-amdgpu-should-stop-GFX-ring-in-hw_fini.patch
+patch 4617-drm-amdgpu-fix-GFX10-missing-CSIB-set-v3.patch
+patch 4618-drm-amdgpu-not-remove-sysfs-if-not-create-sysfs.patch
+patch 4619-drm-amd-display-Load-TA-firmware-for-navi10-12-14.patch
+patch 4620-drm-amdgpu-Added-ASIC-specific-checks-in-gfxhub-V1.1.patch
+patch 4621-drm-amdgpu-sriov-No-need-the-event-3-and-4-now.patch
+patch 4622-drm-amdgpu-move-CS-secure-flag-next-the-structs-wher.patch
+patch 4623-amd-amdgpu-sriov-swSMU-disable-for-sriov.patch
+patch 4624-drm-amd-display-Adding-NV14-IP-Parameters.patch
+patch 4625-drm-amd-display-Get-NV14-specific-ip-params-as-neede.patch
+patch 4626-drm-amd-display-re-enable-wait-in-pipelock-but-add-t.patch
+patch 4627-drm-amd-display-fix-double-assignment-to-msg_id-fiel.patch
+patch 4628-drm-amd-display-Remove-unneeded-semicolon-in-bios_pa.patch
+patch 4629-drm-amd-display-Remove-unneeded-semicolon-in-bios_pa.patch
+patch 4630-drm-amd-display-Remove-unneeded-semicolon-in-hdcp.c.patch
+patch 4631-drm-amd-display-Remove-unneeded-semicolon-in-display.patch
+patch 4632-drm-amd-display-remove-redundant-assignment-to-varia.patch
+patch 4633-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch
+patch 4634-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch
+patch 4635-drm-amd-powerplay-Remove-unneeded-variable-ret-in-sm.patch
+patch 4636-drm-amd-powerplay-Remove-unneeded-variable-result-in.patch
+patch 4637-drm-amd-powerplay-Remove-unneeded-variable-ret-in-am.patch
+patch 4638-Revert-drm-amdgpu-Set-GTT-size-to-be-bigger-than-3-4.patch
+patch 4639-drm-amdgpu-drop-asd-shared-memory.patch
+patch 4640-drm-amdgpu-unload-asd-in-psp-hw-de-init-phase.patch
+patch 4641-drm-amdgpu-load-np-fw-prior-before-loading-the-TAs.patch
+patch 4642-drm-amdkfd-Contain-MMHUB-number-in-mmhub_v9_4_setup_.patch
+patch 4643-drm-scheduler-Avoid-accessing-freed-bad-job.patch
+patch 4644-drm-amdkfd-kfd-debugger-set-DISPATCH_PTR.patch
+patch 4645-drm-amd-display-Loading-NV10-14-Bounding-Box-Data-Di.patch
+patch 4646-drm-amdgpu-powerplay-unify-smu-send-message-function.patch
+patch 4647-Revert-Revert-drm-amdgpu-Set-GTT-size-to-be-bigger-t.patch
+patch 4648-drm-amdgpu-add-check-before-enabling-disabling-broad.patch
+patch 4649-drm-amdgpu-gfx-Improvement-on-EDC-GPR-workarounds.patch
+patch 4650-drm-amdgpu-add-header-line-for-power-profile-on-Arct.patch
+patch 4651-drm-amdgpu-display-fix-the-build-when-CONFIG_DRM_AMD.patch
+patch 4652-drm-amdgpu-display-fix-warning-when-CONFIG_DRM_AMD_D.patch
+patch 4653-drm-amd-display-cleanup-of-function-pointer-tables.patch
+patch 4654-drm-amd-display-Use-a-temporary-copy-of-the-current-.patch
+patch 4655-drm-amd-display-Use-NULL-for-pointer-assignment-in-c.patch
+patch 4656-drm-amdgpu-add-cache-flush-workaround-to-gfx8-emit_f.patch
+patch 4657-drm-amdgpu-remove-ras-global-recovery-handling-from-.patch
+patch 4658-drm-amdgpu-export-amdgpu_ras_find_obj-to-use-externa.patch
+patch 4659-drm-amdgpu-clear-ras-controller-status-registers-whe.patch
+patch 4660-drm-amdgpu-clear-uncorrectable-parity-error-status-b.patch
+patch 4661-drm-amdgpu-enable-disable-doorbell-interrupt-in-baco.patch
+patch 4662-drm-amdgpu-add-concurrent-baco-reset-support-for-XGM.patch
+patch 4663-drm-amdgpu-support-full-gpu-reset-workflow-when-ras-.patch
+patch 4664-drm-amdgpu-clear-err_event_athub-flag-after-reset-ex.patch
+patch 4665-drm-amdgpu-reduce-redundant-uvd-context-lost-warning.patch
+patch 4666-drm-amd-display-update-sr-and-pstate-latencies-for-R.patch
+patch 4667-drm-amd-display-rename-core_dc-to-dc.patch
+patch 4668-drm-amd-display-add-separate-of-private-hwss-functio.patch
+patch 4669-drm-amd-display-Fix-Dali-clk-mgr-construct.patch
+patch 4670-drm-amd-display-Map-DSC-resources-1-to-1-if-numbers-.patch
+patch 4671-drm-amd-display-fix-DalDramClockChangeLatencyNs-over.patch
+patch 4672-drm-amd-display-Wrong-ifdef-guards-were-used-around-.patch
+patch 4673-drm-amd-display-Reset-PHY-in-link-re-training.patch
+patch 4674-drm-amd-display-Disable-link-before-reenable.patch
+patch 4675-drm-amd-display-Add-DMCUB__PG_DONE-trace-code-enum.patch
+patch 4676-drm-amd-display-Only-wait-for-DMUB-phy-init-on-dcn21.patch
+patch 4677-drm-amd-display-Return-DMUB_STATUS_OK-when-autoload-.patch
+patch 4678-drm-amd-display-Program-CW5-for-tracebuffer-for-dcn2.patch
+patch 4679-drm-amd-display-populate-bios-integrated-info-for-re.patch
+patch 4680-drm-amd-display-Fixed-kernel-panic-when-booting-with.patch
+patch 4681-drm-amd-display-have-two-different-sr-and-pstate-lat.patch
+patch 4682-drm-amd-display-fix-dprefclk-and-ss-percentage-readi.patch
+patch 4683-drm-amd-display-3.2.61.patch
+patch 4684-drm-amd-display-Change-the-delay-time-before-enablin.patch
+patch 4685-drm-amd-display-fixed-that-I2C-over-AUX-didn-t-read-.patch
+patch 4686-drm-amd-display-add-log-for-lttpr.patch
+patch 4687-drm-amd-display-Disable-chroma-viewport-w-a-when-rot.patch
+patch 4688-drm-amd-display-fix-dml20-min_dst_y_next_start-calcu.patch
+patch 4689-drm-amd-display-Reset-steer-fifo-before-unblanking-t.patch
+patch 4690-drm-amd-display-Implement-DePQ-for-DCN1.patch
+patch 4691-drm-amd-display-update-p-state-latency-for-renoir-wh.patch
+patch 4692-drm-amd-display-add-DP-protocol-version.patch
+patch 4693-drm-amd-display-Save-restore-link-setting-for-disabl.patch
+patch 4694-drm-amd-display-Return-a-correct-error-value.patch
+patch 4695-drm-amd-display-Split-DMUB-cmd-type-into-type-subtyp.patch
+patch 4696-drm-amd-display-Add-shared-DMCUB-driver-firmware-sta.patch
+patch 4697-drm-amd-display-update-sr-latency-for-renoir-when-us.patch
+patch 4698-drm-amd-display-Remove-flag-check-in-mpcc-update.patch
+patch 4699-drm-amd-display-check-for-repeater-when-setting-aux_.patch
+patch 4700-drm-amd-display-Modify-logic-for-when-to-wait-for-mp.patch
+patch 4701-drm-amd-display-Remove-redundant-call.patch
+patch 4702-drm-amd-display-add-dc-dsc-functions-to-return-bpp-r.patch
+patch 4703-drm-amd-display-remove-spam-DSC-log.patch
+patch 4704-drm-amd-display-add-dsc-policy-getter.patch
+patch 4705-drm-amd-display-fix-cursor-positioning-for-multiplan.patch
+patch 4706-drm-amd-display-Fix-screen-tearing-on-vrr-tests.patch
+patch 4707-drm-amd-display-update-dispclk-and-dppclk-vco-freque.patch
+patch 4708-drm-amd-display-Implement-DePQ-for-DCN2.patch
+patch 4709-drm-amd-display-3.2.62.patch
+patch 4710-drm-amd-display-Change-HDR_MULT-check.patch
+patch 4711-drm-amd-display-Increase-the-number-of-retries-after.patch
+patch 4712-drm-amd-display-Compare-clock-state-member-to-determ.patch
+patch 4713-drm-amd-display-update-dml-related-structs.patch
+patch 4714-drm-amd-display-correct-log-message-for-lttpr.patch
+patch 4715-drm-amd-display-Extend-DMCUB-offload-testing-into-dc.patch
+patch 4716-drm-amdgpu-Fix-BACO-entry-failure-in-NAVI10.patch
+patch 4717-drm-amd-powerplay-drop-unnecessary-warning-prompt.patch
+patch 4718-drm-amd-powerplay-pre-check-the-SMU-state-before-iss.patch
+patch 4719-drm-amdgpu-fix-resume-failures-due-to-psp-fw-loading.patch
+patch 4720-drm-amdkfd-Improve-kfd_process-lookup-in-kfd_ioctl.patch
+patch 4721-drm-amdgpu-display-add-fallthrough-comment.patch
+patch 4722-drm-amdgpu-move-VM-eviction-decision-into-amdgpu_vm..patch
+patch 4723-drm-amdgpu-explicitely-sync-to-VM-updates-v2.patch
+patch 4724-drm-amdgpu-add-condition-to-enable-baco-for-ras-reco.patch
+patch 4725-drm-amdgpu-Add-RAS-dbg-print-support.patch
+patch 4726-drm-amdgpu-Added-RAS-UMC-error-query-support-for-Arc.patch
+patch 4727-drm-amd-powerplay-clear-VBIOS-scratchs-on-baco-exit-.patch
+patch 4728-drm-amd-powerplay-implement-interface-to-retrieve-gp.patch
+patch 4729-drm-amd-powerplay-implement-interface-to-retrieve-cl.patch
+patch 4730-drm-amd-powerplay-implement-the-get_enabled_mask-cal.patch
+patch 4731-drm-amd-powerplay-correct-the-value-retrieved-throug.patch
+patch 4732-drm-amdgpu-enable-gfxoff-feature-for-navi10-asic.patch
+patch 4733-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
+patch 4734-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
+patch 4735-drm-amdgpu-gfx10-update-gfx-golden-settings.patch
+patch 4736-drm-amdgpu-gfx10-update-gfx-golden-settings-for-navi.patch
 
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-e3000_4.19.inc b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-e3000_4.19.inc
new file mode 100644
index 00000000..bd87f03f
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-e3000_4.19.inc
@@ -0,0 +1,29 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/linux-yocto-${LINUX_VERSION}-${MACHINE}:"
+
+SRC_URI_append_e3000 += "file://e3000-user-features.scc \
+    file://e3000-user-patches.scc \
+    file://e3000.cfg \
+    file://e3000-user-config.cfg \
+    file://e3000-extra-config.cfg \
+    file://amd-xgbe.cfg \
+    file://amd-ccp.cfg \
+    file://kvm.cfg \
+    file://afalg.cfg \
+    file://disable-graphics.cfg \
+    file://e3000-standard-only.cfg \
+"
+
+COMPATIBLE_MACHINE_e3000 = "e3000"
+
+do_validate_branches_append() {
+    # Droping configs related to sound generating spurious warnings
+    sed -i '/kconf hardware snd_hda_intel.cfg/d' ${WORKDIR}/${KMETA}/features/sound/snd_hda_intel.scc
+
+    # Droping configs related to graphics generating spurious warnings
+    sed -i '/CONFIG_FB/d' ${WORKDIR}/${KMETA}/bsp/common-pc/common-pc-gfx.cfg
+    sed -i '/CONFIG_DRM/d' ${WORKDIR}/${KMETA}/bsp/common-pc/common-pc-gfx.cfg
+    sed -i '/CONFIG_FRAMEBUFFER_CONSOLE/d' ${WORKDIR}/${KMETA}/bsp/common-pc/common-pc-gfx.cfg
+    sed -i '/kconf hardware i915.cfg/d' ${WORKDIR}/${KMETA}/features/i915/i915.scc
+    sed -i '/CONFIG_FB/d' ${WORKDIR}/${KMETA}/cfg/efi-ext.cfg
+    sed -i '/CONFIG_FRAMEBUFFER_CONSOLE/d' ${WORKDIR}/${KMETA}/cfg/efi-ext.cfg
+}
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-rt_4.19.bbappend b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-rt_4.19.bbappend
new file mode 100644
index 00000000..c24a0a20
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-rt_4.19.bbappend
@@ -0,0 +1,6 @@
+require linux-yocto-common_4.19.inc
+
+KBRANCH_amdx86 ?= "v4.19/standard/preempt-rt/base"
+SRCREV_machine_amdx86 ?= "bd456d13d8bea4c416209a59f9e0bf50f8511c47"
+
+include linux-yocto-${MACHINE}_4.19.inc
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-v1000_4.19.inc b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-v1000_4.19.inc
new file mode 100644
index 00000000..09acaf96
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-v1000_4.19.inc
@@ -0,0 +1,14 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/linux-yocto-${LINUX_VERSION}-${MACHINE}:"
+
+SRC_URI_append_v1000 += "file://v1000-user-features.scc \
+    file://v1000-user-patches.scc \
+    file://v1000.cfg \
+    file://v1000-user-config.cfg \
+    file://v1000-gpu-config.cfg \
+    file://v1000-extra-config.cfg \
+    file://v1000-standard-only.cfg \
+"
+
+KERNEL_FEATURES_append_v1000 = " cfg/sound.scc"
+
+COMPATIBLE_MACHINE_v1000 = "v1000"